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x64dbg-development/setupdeps.bat | @echo off
git submodule update --init --recursive
mkdir bin\x32
xcopy deps\x32 bin\x32 /S /Y
mkdir bin\x64
xcopy deps\x64 bin\x64 /S /Y
mkdir bin\x32d
xcopy deps\x32 bin\x32d /S /Y
xcopy deps\x32d bin\x32d /S /Y
mkdir bin\x64d
xcopy deps\x64 bin\x64d /S /Y
xcopy deps\x64d bin\x64d /S /Y |
|
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Markdown | x64dbg-development/.github/CODE_OF_CONDUCT.md | # Contributor Covenant Code of Conduct
## Our Pledge
In the interest of fostering an open and welcoming environment, we as contributors and maintainers pledge to making participation in our project and our community a harassment-free experience for everyone, regardless of age, body size, disability, ethnicity, gender identity and expression, level of experience, nationality, personal appearance, race, religion, or sexual identity and orientation.
## Our Standards
Examples of behavior that contributes to creating a positive environment include:
* Using welcoming and inclusive language
* Being respectful of differing viewpoints and experiences
* Gracefully accepting constructive criticism
* Focusing on what is best for the community
* Showing empathy towards other community members
Examples of unacceptable behavior by participants include:
* The use of sexualized language or imagery and unwelcome sexual attention or advances
* Trolling, insulting/derogatory comments, and personal or political attacks
* Public or private harassment
* Publishing others' private information, such as a physical or electronic address, without explicit permission
* Other conduct which could reasonably be considered inappropriate in a professional setting
## Our Responsibilities
Project maintainers are responsible for clarifying the standards of acceptable behavior and are expected to take appropriate and fair corrective action in response to any instances of unacceptable behavior.
Project maintainers have the right and responsibility to remove, edit, or reject comments, commits, code, wiki edits, issues, and other contributions that are not aligned to this Code of Conduct, or to ban temporarily or permanently any contributor for other behaviors that they deem inappropriate, threatening, offensive, or harmful.
## Scope
This Code of Conduct applies both within project spaces and in public spaces when an individual is representing the project or its community. Examples of representing a project or community include using an official project e-mail address, posting via an official social media account, or acting as an appointed representative at an online or offline event. Representation of a project may be further defined and clarified by project maintainers.
## Enforcement
Instances of abusive, harassing, or otherwise unacceptable behavior may be reported by contacting the project team at [email protected]. The project team will review and investigate all complaints, and will respond in a way that it deems appropriate to the circumstances. The project team is obligated to maintain confidentiality with regard to the reporter of an incident. Further details of specific enforcement policies may be posted separately.
Project maintainers who do not follow or enforce the Code of Conduct in good faith may face temporary or permanent repercussions as determined by other members of the project's leadership.
## Attribution
This Code of Conduct is adapted from the [Contributor Covenant][homepage], version 1.4, available at [http://contributor-covenant.org/version/1/4][version]
[homepage]: http://contributor-covenant.org
[version]: http://contributor-covenant.org/version/1/4/ |
Markdown | x64dbg-development/.github/CONTRIBUTING.md | # Contributing
Welcome to x64dbg! This document is relevant for you if you want to contribute to the project. If you just want to use x64dbg, go to the [website](https://x64dbg.com) instead.
## Overview
This is a list of things you can do to help us out (in no particular order). Each item will be expanded upon later in the document.
- [Compile x64dbg](https://github.com/x64dbg/x64dbg/wiki/Compiling-the-whole-project) and add new features ([good first issues](https://easy.x64dbg.com) are a good place to start).
- [Report bugs](https://report.x64dbg.com) at the issue tracker.
- Add feature requests to the [issue tracker](https://issues.x64dbg.com).
- [Write a blogpost](https://x64dbg.com/blog/2016/07/09/Looking-for-writers.html) for the [official blog](https://blog.x64dbg.com).
- [Contact us](https://x64dbg.com/#contact) and talk about x64dbg.
- Send a [donation](https://donate.x64dbg.com) to support the project.
- [Translate](https://translate.x64dbg.com) x64dbg (contact us if your language isn't listed).
- Help us improve the [documentation](https://github.com/x64dbg/docs/issues).
### Compile x64dbg
There is a guide to [compiling the whole project](https://github.com/x64dbg/x64dbg/wiki/Compiling-the-whole-project) available. This might seem difficult at first, but if you install the correct versions of the *Prerequisites* it will be a breeze.
Compiling x64dbg is very useful to us (even if you don't add any code). Your experience can improve this guide and help new contributors.
#### Getting started with development
As with any open source project, documentation is lacking and the code can seem very daunting at first. Here is a list of resources that can help you understand the architecture and get you started.
- [Architecture of x64dbg](https://x64dbg.com/blog/2016/10/04/architecture-of-x64dbg.html) (**must read**)
- [The x64dbg threading model](https://x64dbg.com/blog/2016/10/20/threading-model.html) (**must read**)
- [User interface design principles](https://x64dbg.com/blog/2016/08/08/user-interface-design-principles.html) blog post. It explains some of the design philosophy.
- [Control flow graph](https://x64dbg.com/blog/2016/07/27/Control-flow-graph.html) blog post. The post links to the relevant code sections.
- Blog post about the [plugin SDK](https://x64dbg.com/blog/2016/07/30/x64dbg-plugin-sdk.html). Writing an x64dbg plugin can also help you understand the code structure.
This is by no means an exhaustive list and we are still working on lowering the barrier for new contributors. The feedback of new contributors is vital to reaching this goal.
#### Sending a pull request
Here is a little guide on how to do a clean pull request for people who don't yet know how to use git. We recommend using [Git Extensions](https://gitextensions.github.io), but any git interface is fine.
1. First we need to [fork](https://help.github.com/articles/fork-a-repo/) the actual x64dbg repo on our github account.
2. When the fork is finished, clone the repo (`git clone https://github.com/myname/x64dbg.git`).
3. When pushing new features/bug/whatever to a github project the best practice is to create branches. The command `git checkout -b my-branch-name` will automatically create a branch and check it out.
4. Make all the changes you want and when finishing it, use `git add myfiles` to add it to the repo.
5. Commit your change. `git commit -m 'a message about what you changed'`. The change are applied to your local git repo.
6. Push it to your `origin`. The `origin` is your repo which is hosted on github. `git push --set-upstream origin your-branch-name`.
7. Sync with the `upstream` repo, the real x64dbg repo. `git remote add upstream https://github.com/x64dbg/x64dbg.git`, using `git remote -v` will show which origin/upstream are setup in the local repo.
8. Sync your fork with the `upstream`, `git fetch upstream`. Now checkout your local `development` branch again `git checkout development` and merge the upstream `git merge upstream/development`.
9. Time to create the pull request! Using the github ui, go to your account/repo, select the branch you already pushed, and click `Pull request`. Review your pull request and send it.
Happy PRs!
### Report bugs
If you want to have the highest chance of getting your problem solved, you are going to have to put in some effort. The vital things are:
1. Search the issue tracker to see if your bug has not been reported already.
2. Give concrete steps on how to reproduce your bug.
3. Tell us exactly which version of x64dbg you used and the environment(s) you reproduced the bug in.
You can take a look at the [issue template](https://github.com/x64dbg/x64dbg/blob/development/.github/ISSUE_TEMPLATE.md) for more details.
### Request features
Feature requests are often closed because they are out of scope. If you request one anyway, make sure to give a clear description of the desired behaviour and give clear examples of cases where your feature would be useful.
We understand that it can be disappointing to not get your feature implemented, but opening an issue is the best way to communicate it regardless.
### Write a blogpost
The x64dbg blog is open to all contributors (foreign and domestic). We encourage anyone who has an interesting encounter with the x64dbg code base, or a use case to share it with the community. For a guideline on how/what to contribute see the [blog post](https://x64dbg.com/blog/2016/07/09/Looking-for-writers.html) about contributing to the blog. Don't worry about contributing complex posts, we welcome ALL experience levels to add content to the blog!
### Contact us
There are several ways to reach out to the community of x64dbg developers, contributors and users. Chat channels consist of a [Telegram](https://telegram.me/x64dbg), [Gitter](https://gitter.x64dbg.com/) and [IRC](https://webchat.freenode.net/?channels=x64dbg) channel. Most questions regarding contributing, developing and using x64dbg can be answered here. To ensure channel cohesion a bot will sync messages across all three channels. (when it is not down ;))
### Translate
To help translate x64dbg, just head over to https://translate.x64dbg.com, click a language you want to translate and start filling in entries.
### Improve the documentation
If you see any room for improvement in the [documentation](https://help.x64dbg.com), just send a pull request or contact us to discuss your changes.
### Triage Issues [](https://www.codetriage.com/x64dbg/x64dbg)
You can triage issues which may include reproducing bug reports or asking for vital information, such as version numbers or reproduction instructions. If you would like to start triaging issues, one easy way to get started is to [subscribe to x64dbg on CodeTriage](https://www.codetriage.com/x64dbg/x64dbg). |
YAML | x64dbg-development/.github/FUNDING.yml | # These are supported funding model platforms
github: [mrexodia]
#patreon: # Replace with a single Patreon username
#open_collective: # Replace with a single Open Collective username
#ko_fi: # Replace with a single Ko-fi username
#tidelift: # Replace with a single Tidelift platform-name/package-name e.g., npm/babel
#community_bridge: # Replace with a single Community Bridge project-name e.g., cloud-foundry
#liberapay: # Replace with a single Liberapay username
#issuehunt: x64dbg/x64dbg # Replace with a single IssueHunt username
#otechie: # Replace with a single Otechie username
#custom: ['https://www.bountysource.com/teams/x64dbg'] |
YAML | x64dbg-development/.github/ISSUE_TEMPLATE/bug_report.yaml | name: Bug report
description: Issues and bugs for x64dbg.
labels:
- bug
- pending reproduction
body:
- type: markdown
attributes:
value: Before filing this bug, [please check if it hasn't already been reported](https://github.com/x64dbg/x64dbg/issues?q=is%3Aissue+label%3Abug). If it has, please add useful information to the existing issue instead.
- type: input
attributes:
label: Operating System
placeholder: Window 10 64bit, Build 18363
validations:
required: true
- type: input
attributes:
label: x64dbg Version
placeholder: Jul 29 2021
description: To get the version information, press "Help" on the menu bar and press "About".
validations:
required: true
- type: textarea
attributes:
label: Describe the issue
description: Please describe the issue you are experiencing here.
validations:
required: true
- type: textarea
attributes:
label: Steps to reproduce
description: Please describe in small and detailed steps on how to reproduce the issue.
placeholder: Steps required to reproduce the issue.
value: |
1.
2.
3.
validations:
required: true
- type: textarea
attributes:
label: Attachments
description: If you can provide crashdumps or screenshots that help to investigate the issue please provide them.
placeholder: Drag and drop files here to add them
validations:
required: false |
YAML | x64dbg-development/.github/ISSUE_TEMPLATE/feature_request.yaml | name: Feature request
description: Request a new feature to be added to x64dbg.
labels:
- feature
body:
- type: markdown
attributes:
value: Before filing this request, [please check if it hasn't already been suggested before](https://github.com/x64dbg/x64dbg/issues?q=is%3Aissue+label%3Afeature). If it has, please add to the existing issue instead.
- type: dropdown
attributes:
label: Feature type
description: Tell us what this feature would improve.
multiple: true
options:
- Quality of life
- Debugging
- Plug-ins
- Other
validations:
required: true
- type: textarea
attributes:
label: Describe the feature
placeholder: Describe your feature idea here. You can paste or drag & drop attachments here to help on illustrating it.
validations:
required: true |
Text | x64dbg-development/bin/errordb.txt | 0 ERROR_SUCCESS
1 ERROR_INVALID_FUNCTION
2 ERROR_FILE_NOT_FOUND
3 ERROR_PATH_NOT_FOUND
4 ERROR_TOO_MANY_OPEN_FILES
5 ERROR_ACCESS_DENIED
6 ERROR_INVALID_HANDLE
7 ERROR_ARENA_TRASHED
8 ERROR_NOT_ENOUGH_MEMORY
9 ERROR_INVALID_BLOCK
10 ERROR_BAD_ENVIRONMENT
11 ERROR_BAD_FORMAT
12 ERROR_INVALID_ACCESS
13 ERROR_INVALID_DATA
14 ERROR_OUTOFMEMORY
15 ERROR_INVALID_DRIVE
16 ERROR_CURRENT_DIRECTORY
17 ERROR_NOT_SAME_DEVICE
18 ERROR_NO_MORE_FILES
19 ERROR_WRITE_PROTECT
20 ERROR_BAD_UNIT
21 ERROR_NOT_READY
22 ERROR_BAD_COMMAND
23 ERROR_CRC
24 ERROR_BAD_LENGTH
25 ERROR_SEEK
26 ERROR_NOT_DOS_DISK
27 ERROR_SECTOR_NOT_FOUND
28 ERROR_OUT_OF_PAPER
29 ERROR_WRITE_FAULT
30 ERROR_READ_FAULT
31 ERROR_GEN_FAILURE
32 ERROR_SHARING_VIOLATION
33 ERROR_LOCK_VIOLATION
34 ERROR_WRONG_DISK
36 ERROR_SHARING_BUFFER_EXCEEDED
38 ERROR_HANDLE_EOF
39 ERROR_HANDLE_DISK_FULL
50 ERROR_NOT_SUPPORTED
51 ERROR_REM_NOT_LIST
52 ERROR_DUP_NAME
53 ERROR_BAD_NETPATH
54 ERROR_NETWORK_BUSY
55 ERROR_DEV_NOT_EXIST
56 ERROR_TOO_MANY_CMDS
57 ERROR_ADAP_HDW_ERR
58 ERROR_BAD_NET_RESP
59 ERROR_UNEXP_NET_ERR
60 ERROR_BAD_REM_ADAP
61 ERROR_PRINTQ_FULL
62 ERROR_NO_SPOOL_SPACE
63 ERROR_PRINT_CANCELLED
64 ERROR_NETNAME_DELETED
65 ERROR_NETWORK_ACCESS_DENIED
66 ERROR_BAD_DEV_TYPE
67 ERROR_BAD_NET_NAME
68 ERROR_TOO_MANY_NAMES
69 ERROR_TOO_MANY_SESS
70 ERROR_SHARING_PAUSED
71 ERROR_REQ_NOT_ACCEP
72 ERROR_REDIR_PAUSED
80 ERROR_FILE_EXISTS
82 ERROR_CANNOT_MAKE
83 ERROR_FAIL_I24
84 ERROR_OUT_OF_STRUCTURES
85 ERROR_ALREADY_ASSIGNED
86 ERROR_INVALID_PASSWORD
87 ERROR_INVALID_PARAMETER
88 ERROR_NET_WRITE_FAULT
89 ERROR_NO_PROC_SLOTS
100 ERROR_TOO_MANY_SEMAPHORES
101 ERROR_EXCL_SEM_ALREADY_OWNED
102 ERROR_SEM_IS_SET
103 ERROR_TOO_MANY_SEM_REQUESTS
104 ERROR_INVALID_AT_INTERRUPT_TIME
105 ERROR_SEM_OWNER_DIED
106 ERROR_SEM_USER_LIMIT
107 ERROR_DISK_CHANGE
108 ERROR_DRIVE_LOCKED
109 ERROR_BROKEN_PIPE
110 ERROR_OPEN_FAILED
111 ERROR_BUFFER_OVERFLOW
112 ERROR_DISK_FULL
113 ERROR_NO_MORE_SEARCH_HANDLES
114 ERROR_INVALID_TARGET_HANDLE
117 ERROR_INVALID_CATEGORY
118 ERROR_INVALID_VERIFY_SWITCH
119 ERROR_BAD_DRIVER_LEVEL
120 ERROR_CALL_NOT_IMPLEMENTED
121 ERROR_SEM_TIMEOUT
122 ERROR_INSUFFICIENT_BUFFER
123 ERROR_INVALID_NAME
124 ERROR_INVALID_LEVEL
125 ERROR_NO_VOLUME_LABEL
126 ERROR_MOD_NOT_FOUND
127 ERROR_PROC_NOT_FOUND
128 ERROR_WAIT_NO_CHILDREN
129 ERROR_CHILD_NOT_COMPLETE
130 ERROR_DIRECT_ACCESS_HANDLE
131 ERROR_NEGATIVE_SEEK
132 ERROR_SEEK_ON_DEVICE
133 ERROR_IS_JOIN_TARGET
134 ERROR_IS_JOINED
135 ERROR_IS_SUBSTED
136 ERROR_NOT_JOINED
137 ERROR_NOT_SUBSTED
138 ERROR_JOIN_TO_JOIN
139 ERROR_SUBST_TO_SUBST
140 ERROR_JOIN_TO_SUBST
141 ERROR_SUBST_TO_JOIN
142 ERROR_BUSY_DRIVE
143 ERROR_SAME_DRIVE
144 ERROR_DIR_NOT_ROOT
145 ERROR_DIR_NOT_EMPTY
146 ERROR_IS_SUBST_PATH
147 ERROR_IS_JOIN_PATH
148 ERROR_PATH_BUSY
149 ERROR_IS_SUBST_TARGET
150 ERROR_SYSTEM_TRACE
151 ERROR_INVALID_EVENT_COUNT
152 ERROR_TOO_MANY_MUXWAITERS
153 ERROR_INVALID_LIST_FORMAT
154 ERROR_LABEL_TOO_LONG
155 ERROR_TOO_MANY_TCBS
156 ERROR_SIGNAL_REFUSED
157 ERROR_DISCARDED
158 ERROR_NOT_LOCKED
159 ERROR_BAD_THREADID_ADDR
160 ERROR_BAD_ARGUMENTS
161 ERROR_BAD_PATHNAME
162 ERROR_SIGNAL_PENDING
164 ERROR_MAX_THRDS_REACHED
167 ERROR_LOCK_FAILED
170 ERROR_BUSY
171 ERROR_DEVICE_SUPPORT_IN_PROGRESS
173 ERROR_CANCEL_VIOLATION
174 ERROR_ATOMIC_LOCKS_NOT_SUPPORTED
180 ERROR_INVALID_SEGMENT_NUMBER
182 ERROR_INVALID_ORDINAL
183 ERROR_ALREADY_EXISTS
186 ERROR_INVALID_FLAG_NUMBER
187 ERROR_SEM_NOT_FOUND
188 ERROR_INVALID_STARTING_CODESEG
189 ERROR_INVALID_STACKSEG
190 ERROR_INVALID_MODULETYPE
191 ERROR_INVALID_EXE_SIGNATURE
192 ERROR_EXE_MARKED_INVALID
193 ERROR_BAD_EXE_FORMAT
194 ERROR_ITERATED_DATA_EXCEEDS_64k
195 ERROR_INVALID_MINALLOCSIZE
196 ERROR_DYNLINK_FROM_INVALID_RING
197 ERROR_IOPL_NOT_ENABLED
198 ERROR_INVALID_SEGDPL
199 ERROR_AUTODATASEG_EXCEEDS_64k
200 ERROR_RING2SEG_MUST_BE_MOVABLE
201 ERROR_RELOC_CHAIN_XEEDS_SEGLIM
202 ERROR_INFLOOP_IN_RELOC_CHAIN
203 ERROR_ENVVAR_NOT_FOUND
205 ERROR_NO_SIGNAL_SENT
206 ERROR_FILENAME_EXCED_RANGE
207 ERROR_RING2_STACK_IN_USE
208 ERROR_META_EXPANSION_TOO_LONG
209 ERROR_INVALID_SIGNAL_NUMBER
210 ERROR_THREAD_1_INACTIVE
212 ERROR_LOCKED
214 ERROR_TOO_MANY_MODULES
215 ERROR_NESTING_NOT_ALLOWED
216 ERROR_EXE_MACHINE_TYPE_MISMATCH
217 ERROR_EXE_CANNOT_MODIFY_SIGNED_BINARY
218 ERROR_EXE_CANNOT_MODIFY_STRONG_SIGNED_BINARY
220 ERROR_FILE_CHECKED_OUT
221 ERROR_CHECKOUT_REQUIRED
222 ERROR_BAD_FILE_TYPE
223 ERROR_FILE_TOO_LARGE
224 ERROR_FORMS_AUTH_REQUIRED
225 ERROR_VIRUS_INFECTED
226 ERROR_VIRUS_DELETED
229 ERROR_PIPE_LOCAL
230 ERROR_BAD_PIPE
231 ERROR_PIPE_BUSY
232 ERROR_NO_DATA
233 ERROR_PIPE_NOT_CONNECTED
234 ERROR_MORE_DATA
235 ERROR_NO_WORK_DONE
240 ERROR_VC_DISCONNECTED
254 ERROR_INVALID_EA_NAME
255 ERROR_EA_LIST_INCONSISTENT
258 WAIT_TIMEOUT
259 ERROR_NO_MORE_ITEMS
266 ERROR_CANNOT_COPY
267 ERROR_DIRECTORY
275 ERROR_EAS_DIDNT_FIT
276 ERROR_EA_FILE_CORRUPT
277 ERROR_EA_TABLE_FULL
278 ERROR_INVALID_EA_HANDLE
282 ERROR_EAS_NOT_SUPPORTED
288 ERROR_NOT_OWNER
298 ERROR_TOO_MANY_POSTS
299 ERROR_PARTIAL_COPY
300 ERROR_OPLOCK_NOT_GRANTED
301 ERROR_INVALID_OPLOCK_PROTOCOL
302 ERROR_DISK_TOO_FRAGMENTED
303 ERROR_DELETE_PENDING
304 ERROR_INCOMPATIBLE_WITH_GLOBAL_SHORT_NAME_REGISTRY_SETTING
305 ERROR_SHORT_NAMES_NOT_ENABLED_ON_VOLUME
306 ERROR_SECURITY_STREAM_IS_INCONSISTENT
307 ERROR_INVALID_LOCK_RANGE
308 ERROR_IMAGE_SUBSYSTEM_NOT_PRESENT
309 ERROR_NOTIFICATION_GUID_ALREADY_DEFINED
310 ERROR_INVALID_EXCEPTION_HANDLER
311 ERROR_DUPLICATE_PRIVILEGES
312 ERROR_NO_RANGES_PROCESSED
313 ERROR_NOT_ALLOWED_ON_SYSTEM_FILE
314 ERROR_DISK_RESOURCES_EXHAUSTED
315 ERROR_INVALID_TOKEN
316 ERROR_DEVICE_FEATURE_NOT_SUPPORTED
317 ERROR_MR_MID_NOT_FOUND
318 ERROR_SCOPE_NOT_FOUND
319 ERROR_UNDEFINED_SCOPE
320 ERROR_INVALID_CAP
321 ERROR_DEVICE_UNREACHABLE
322 ERROR_DEVICE_NO_RESOURCES
323 ERROR_DATA_CHECKSUM_ERROR
324 ERROR_INTERMIXED_KERNEL_EA_OPERATION
326 ERROR_FILE_LEVEL_TRIM_NOT_SUPPORTED
327 ERROR_OFFSET_ALIGNMENT_VIOLATION
328 ERROR_INVALID_FIELD_IN_PARAMETER_LIST
329 ERROR_OPERATION_IN_PROGRESS
330 ERROR_BAD_DEVICE_PATH
331 ERROR_TOO_MANY_DESCRIPTORS
332 ERROR_SCRUB_DATA_DISABLED
333 ERROR_NOT_REDUNDANT_STORAGE
334 ERROR_RESIDENT_FILE_NOT_SUPPORTED
335 ERROR_COMPRESSED_FILE_NOT_SUPPORTED
336 ERROR_DIRECTORY_NOT_SUPPORTED
337 ERROR_NOT_READ_FROM_COPY
338 ERROR_FT_WRITE_FAILURE
339 ERROR_FT_DI_SCAN_REQUIRED
340 ERROR_INVALID_KERNEL_INFO_VERSION
341 ERROR_INVALID_PEP_INFO_VERSION
342 ERROR_OBJECT_NOT_EXTERNALLY_BACKED
343 ERROR_EXTERNAL_BACKING_PROVIDER_UNKNOWN
344 ERROR_COMPRESSION_NOT_BENEFICIAL
345 ERROR_STORAGE_TOPOLOGY_ID_MISMATCH
346 ERROR_BLOCKED_BY_PARENTAL_CONTROLS
347 ERROR_BLOCK_TOO_MANY_REFERENCES
348 ERROR_MARKED_TO_DISALLOW_WRITES
349 ERROR_ENCLAVE_FAILURE
350 ERROR_FAIL_NOACTION_REBOOT
351 ERROR_FAIL_SHUTDOWN
352 ERROR_FAIL_RESTART
353 ERROR_MAX_SESSIONS_REACHED
354 ERROR_NETWORK_ACCESS_DENIED_EDP
355 ERROR_DEVICE_HINT_NAME_BUFFER_TOO_SMALL
356 ERROR_EDP_POLICY_DENIES_OPERATION
357 ERROR_EDP_DPL_POLICY_CANT_BE_SATISFIED
358 ERROR_CLOUD_FILE_SYNC_ROOT_METADATA_CORRUPT
359 ERROR_DEVICE_IN_MAINTENANCE
360 ERROR_NOT_SUPPORTED_ON_DAX
361 ERROR_DAX_MAPPING_EXISTS
362 ERROR_CLOUD_FILE_PROVIDER_NOT_RUNNING
363 ERROR_CLOUD_FILE_METADATA_CORRUPT
364 ERROR_CLOUD_FILE_METADATA_TOO_LARGE
365 ERROR_CLOUD_FILE_PROPERTY_BLOB_TOO_LARGE
366 ERROR_CLOUD_FILE_PROPERTY_BLOB_CHECKSUM_MISMATCH
367 ERROR_CHILD_PROCESS_BLOCKED
368 ERROR_STORAGE_LOST_DATA_PERSISTENCE
369 ERROR_FILE_SYSTEM_VIRTUALIZATION_UNAVAILABLE
370 ERROR_FILE_SYSTEM_VIRTUALIZATION_METADATA_CORRUPT
371 ERROR_FILE_SYSTEM_VIRTUALIZATION_BUSY
372 ERROR_FILE_SYSTEM_VIRTUALIZATION_PROVIDER_UNKNOWN
373 ERROR_GDI_HANDLE_LEAK
374 ERROR_CLOUD_FILE_TOO_MANY_PROPERTY_BLOBS
375 ERROR_CLOUD_FILE_PROPERTY_VERSION_NOT_SUPPORTED
376 ERROR_NOT_A_CLOUD_FILE
377 ERROR_CLOUD_FILE_NOT_IN_SYNC
378 ERROR_CLOUD_FILE_ALREADY_CONNECTED
379 ERROR_CLOUD_FILE_NOT_SUPPORTED
380 ERROR_CLOUD_FILE_INVALID_REQUEST
381 ERROR_CLOUD_FILE_READ_ONLY_VOLUME
382 ERROR_CLOUD_FILE_CONNECTED_PROVIDER_ONLY
383 ERROR_CLOUD_FILE_VALIDATION_FAILED
384 ERROR_SMB1_NOT_AVAILABLE
385 ERROR_FILE_SYSTEM_VIRTUALIZATION_INVALID_OPERATION
386 ERROR_CLOUD_FILE_AUTHENTICATION_FAILED
387 ERROR_CLOUD_FILE_INSUFFICIENT_RESOURCES
388 ERROR_CLOUD_FILE_NETWORK_UNAVAILABLE
389 ERROR_CLOUD_FILE_UNSUCCESSFUL
390 ERROR_CLOUD_FILE_NOT_UNDER_SYNC_ROOT
391 ERROR_CLOUD_FILE_IN_USE
392 ERROR_CLOUD_FILE_PINNED
393 ERROR_CLOUD_FILE_REQUEST_ABORTED
394 ERROR_CLOUD_FILE_PROPERTY_CORRUPT
395 ERROR_CLOUD_FILE_ACCESS_DENIED
396 ERROR_CLOUD_FILE_INCOMPATIBLE_HARDLINKS
397 ERROR_CLOUD_FILE_PROPERTY_LOCK_CONFLICT
398 ERROR_CLOUD_FILE_REQUEST_CANCELED
399 ERROR_EXTERNAL_SYSKEY_NOT_SUPPORTED
400 ERROR_THREAD_MODE_ALREADY_BACKGROUND
401 ERROR_THREAD_MODE_NOT_BACKGROUND
402 ERROR_PROCESS_MODE_ALREADY_BACKGROUND
403 ERROR_PROCESS_MODE_NOT_BACKGROUND
450 ERROR_CAPAUTHZ_NOT_DEVUNLOCKED
451 ERROR_CAPAUTHZ_CHANGE_TYPE
452 ERROR_CAPAUTHZ_NOT_PROVISIONED
453 ERROR_CAPAUTHZ_NOT_AUTHORIZED
454 ERROR_CAPAUTHZ_NO_POLICY
455 ERROR_CAPAUTHZ_DB_CORRUPTED
456 ERROR_CAPAUTHZ_SCCD_INVALID_CATALOG
457 ERROR_CAPAUTHZ_SCCD_NO_AUTH_ENTITY
458 ERROR_CAPAUTHZ_SCCD_PARSE_ERROR
459 ERROR_CAPAUTHZ_SCCD_DEV_MODE_REQUIRED
460 ERROR_CAPAUTHZ_SCCD_NO_CAPABILITY_MATCH
480 ERROR_PNP_QUERY_REMOVE_DEVICE_TIMEOUT
481 ERROR_PNP_QUERY_REMOVE_RELATED_DEVICE_TIMEOUT
482 ERROR_PNP_QUERY_REMOVE_UNRELATED_DEVICE_TIMEOUT
483 ERROR_DEVICE_HARDWARE_ERROR
487 ERROR_INVALID_ADDRESS
500 ERROR_USER_PROFILE_LOAD
534 ERROR_ARITHMETIC_OVERFLOW
535 ERROR_PIPE_CONNECTED
536 ERROR_PIPE_LISTENING
537 ERROR_VERIFIER_STOP
538 ERROR_ABIOS_ERROR
539 ERROR_WX86_WARNING
540 ERROR_WX86_ERROR
541 ERROR_TIMER_NOT_CANCELED
542 ERROR_UNWIND
543 ERROR_BAD_STACK
544 ERROR_INVALID_UNWIND_TARGET
545 ERROR_INVALID_PORT_ATTRIBUTES
546 ERROR_PORT_MESSAGE_TOO_LONG
547 ERROR_INVALID_QUOTA_LOWER
548 ERROR_DEVICE_ALREADY_ATTACHED
549 ERROR_INSTRUCTION_MISALIGNMENT
550 ERROR_PROFILING_NOT_STARTED
551 ERROR_PROFILING_NOT_STOPPED
552 ERROR_COULD_NOT_INTERPRET
553 ERROR_PROFILING_AT_LIMIT
554 ERROR_CANT_WAIT
555 ERROR_CANT_TERMINATE_SELF
556 ERROR_UNEXPECTED_MM_CREATE_ERR
557 ERROR_UNEXPECTED_MM_MAP_ERROR
558 ERROR_UNEXPECTED_MM_EXTEND_ERR
559 ERROR_BAD_FUNCTION_TABLE
560 ERROR_NO_GUID_TRANSLATION
561 ERROR_INVALID_LDT_SIZE
563 ERROR_INVALID_LDT_OFFSET
564 ERROR_INVALID_LDT_DESCRIPTOR
565 ERROR_TOO_MANY_THREADS
566 ERROR_THREAD_NOT_IN_PROCESS
567 ERROR_PAGEFILE_QUOTA_EXCEEDED
568 ERROR_LOGON_SERVER_CONFLICT
569 ERROR_SYNCHRONIZATION_REQUIRED
570 ERROR_NET_OPEN_FAILED
571 ERROR_IO_PRIVILEGE_FAILED
572 ERROR_CONTROL_C_EXIT
573 ERROR_MISSING_SYSTEMFILE
574 ERROR_UNHANDLED_EXCEPTION
575 ERROR_APP_INIT_FAILURE
576 ERROR_PAGEFILE_CREATE_FAILED
577 ERROR_INVALID_IMAGE_HASH
578 ERROR_NO_PAGEFILE
579 ERROR_ILLEGAL_FLOAT_CONTEXT
580 ERROR_NO_EVENT_PAIR
581 ERROR_DOMAIN_CTRLR_CONFIG_ERROR
582 ERROR_ILLEGAL_CHARACTER
583 ERROR_UNDEFINED_CHARACTER
584 ERROR_FLOPPY_VOLUME
585 ERROR_BIOS_FAILED_TO_CONNECT_INTERRUPT
586 ERROR_BACKUP_CONTROLLER
587 ERROR_MUTANT_LIMIT_EXCEEDED
588 ERROR_FS_DRIVER_REQUIRED
589 ERROR_CANNOT_LOAD_REGISTRY_FILE
590 ERROR_DEBUG_ATTACH_FAILED
591 ERROR_SYSTEM_PROCESS_TERMINATED
592 ERROR_DATA_NOT_ACCEPTED
593 ERROR_VDM_HARD_ERROR
594 ERROR_DRIVER_CANCEL_TIMEOUT
595 ERROR_REPLY_MESSAGE_MISMATCH
596 ERROR_LOST_WRITEBEHIND_DATA
597 ERROR_CLIENT_SERVER_PARAMETERS_INVALID
598 ERROR_NOT_TINY_STREAM
599 ERROR_STACK_OVERFLOW_READ
600 ERROR_CONVERT_TO_LARGE
601 ERROR_FOUND_OUT_OF_SCOPE
602 ERROR_ALLOCATE_BUCKET
603 ERROR_MARSHALL_OVERFLOW
604 ERROR_INVALID_VARIANT
605 ERROR_BAD_COMPRESSION_BUFFER
606 ERROR_AUDIT_FAILED
607 ERROR_TIMER_RESOLUTION_NOT_SET
608 ERROR_INSUFFICIENT_LOGON_INFO
609 ERROR_BAD_DLL_ENTRYPOINT
610 ERROR_BAD_SERVICE_ENTRYPOINT
611 ERROR_IP_ADDRESS_CONFLICT1
612 ERROR_IP_ADDRESS_CONFLICT2
613 ERROR_REGISTRY_QUOTA_LIMIT
614 ERROR_NO_CALLBACK_ACTIVE
615 ERROR_PWD_TOO_SHORT
616 ERROR_PWD_TOO_RECENT
617 ERROR_PWD_HISTORY_CONFLICT
618 ERROR_UNSUPPORTED_COMPRESSION
619 ERROR_INVALID_HW_PROFILE
620 ERROR_INVALID_PLUGPLAY_DEVICE_PATH
621 ERROR_QUOTA_LIST_INCONSISTENT
622 ERROR_EVALUATION_EXPIRATION
623 ERROR_ILLEGAL_DLL_RELOCATION
624 ERROR_DLL_INIT_FAILED_LOGOFF
625 ERROR_VALIDATE_CONTINUE
626 ERROR_NO_MORE_MATCHES
627 ERROR_RANGE_LIST_CONFLICT
628 ERROR_SERVER_SID_MISMATCH
629 ERROR_CANT_ENABLE_DENY_ONLY
630 ERROR_FLOAT_MULTIPLE_FAULTS
631 ERROR_FLOAT_MULTIPLE_TRAPS
632 ERROR_NOINTERFACE
633 ERROR_DRIVER_FAILED_SLEEP
634 ERROR_CORRUPT_SYSTEM_FILE
635 ERROR_COMMITMENT_MINIMUM
636 ERROR_PNP_RESTART_ENUMERATION
637 ERROR_SYSTEM_IMAGE_BAD_SIGNATURE
638 ERROR_PNP_REBOOT_REQUIRED
639 ERROR_INSUFFICIENT_POWER
640 ERROR_MULTIPLE_FAULT_VIOLATION
641 ERROR_SYSTEM_SHUTDOWN
642 ERROR_PORT_NOT_SET
643 ERROR_DS_VERSION_CHECK_FAILURE
644 ERROR_RANGE_NOT_FOUND
646 ERROR_NOT_SAFE_MODE_DRIVER
647 ERROR_FAILED_DRIVER_ENTRY
648 ERROR_DEVICE_ENUMERATION_ERROR
649 ERROR_MOUNT_POINT_NOT_RESOLVED
650 ERROR_INVALID_DEVICE_OBJECT_PARAMETER
651 ERROR_MCA_OCCURED
652 ERROR_DRIVER_DATABASE_ERROR
653 ERROR_SYSTEM_HIVE_TOO_LARGE
654 ERROR_DRIVER_FAILED_PRIOR_UNLOAD
655 ERROR_VOLSNAP_PREPARE_HIBERNATE
656 ERROR_HIBERNATION_FAILURE
657 ERROR_PWD_TOO_LONG
665 ERROR_FILE_SYSTEM_LIMITATION
668 ERROR_ASSERTION_FAILURE
669 ERROR_ACPI_ERROR
670 ERROR_WOW_ASSERTION
671 ERROR_PNP_BAD_MPS_TABLE
672 ERROR_PNP_TRANSLATION_FAILED
673 ERROR_PNP_IRQ_TRANSLATION_FAILED
674 ERROR_PNP_INVALID_ID
675 ERROR_WAKE_SYSTEM_DEBUGGER
676 ERROR_HANDLES_CLOSED
677 ERROR_EXTRANEOUS_INFORMATION
678 ERROR_RXACT_COMMIT_NECESSARY
679 ERROR_MEDIA_CHECK
680 ERROR_GUID_SUBSTITUTION_MADE
681 ERROR_STOPPED_ON_SYMLINK
682 ERROR_LONGJUMP
683 ERROR_PLUGPLAY_QUERY_VETOED
684 ERROR_UNWIND_CONSOLIDATE
685 ERROR_REGISTRY_HIVE_RECOVERED
686 ERROR_DLL_MIGHT_BE_INSECURE
687 ERROR_DLL_MIGHT_BE_INCOMPATIBLE
688 ERROR_DBG_EXCEPTION_NOT_HANDLED
689 ERROR_DBG_REPLY_LATER
690 ERROR_DBG_UNABLE_TO_PROVIDE_HANDLE
691 ERROR_DBG_TERMINATE_THREAD
692 ERROR_DBG_TERMINATE_PROCESS
693 ERROR_DBG_CONTROL_C
694 ERROR_DBG_PRINTEXCEPTION_C
695 ERROR_DBG_RIPEXCEPTION
696 ERROR_DBG_CONTROL_BREAK
697 ERROR_DBG_COMMAND_EXCEPTION
698 ERROR_OBJECT_NAME_EXISTS
699 ERROR_THREAD_WAS_SUSPENDED
700 ERROR_IMAGE_NOT_AT_BASE
701 ERROR_RXACT_STATE_CREATED
702 ERROR_SEGMENT_NOTIFICATION
703 ERROR_BAD_CURRENT_DIRECTORY
704 ERROR_FT_READ_RECOVERY_FROM_BACKUP
705 ERROR_FT_WRITE_RECOVERY
706 ERROR_IMAGE_MACHINE_TYPE_MISMATCH
707 ERROR_RECEIVE_PARTIAL
708 ERROR_RECEIVE_EXPEDITED
709 ERROR_RECEIVE_PARTIAL_EXPEDITED
710 ERROR_EVENT_DONE
711 ERROR_EVENT_PENDING
712 ERROR_CHECKING_FILE_SYSTEM
713 ERROR_FATAL_APP_EXIT
714 ERROR_PREDEFINED_HANDLE
715 ERROR_WAS_UNLOCKED
716 ERROR_SERVICE_NOTIFICATION
717 ERROR_WAS_LOCKED
718 ERROR_LOG_HARD_ERROR
719 ERROR_ALREADY_WIN32
720 ERROR_IMAGE_MACHINE_TYPE_MISMATCH_EXE
721 ERROR_NO_YIELD_PERFORMED
722 ERROR_TIMER_RESUME_IGNORED
723 ERROR_ARBITRATION_UNHANDLED
724 ERROR_CARDBUS_NOT_SUPPORTED
725 ERROR_MP_PROCESSOR_MISMATCH
726 ERROR_HIBERNATED
727 ERROR_RESUME_HIBERNATION
728 ERROR_FIRMWARE_UPDATED
729 ERROR_DRIVERS_LEAKING_LOCKED_PAGES
730 ERROR_WAKE_SYSTEM
731 ERROR_WAIT_1
732 ERROR_WAIT_2
733 ERROR_WAIT_3
734 ERROR_WAIT_63
735 ERROR_ABANDONED_WAIT_0
736 ERROR_ABANDONED_WAIT_63
737 ERROR_USER_APC
738 ERROR_KERNEL_APC
739 ERROR_ALERTED
740 ERROR_ELEVATION_REQUIRED
741 ERROR_REPARSE
742 ERROR_OPLOCK_BREAK_IN_PROGRESS
743 ERROR_VOLUME_MOUNTED
744 ERROR_RXACT_COMMITTED
745 ERROR_NOTIFY_CLEANUP
746 ERROR_PRIMARY_TRANSPORT_CONNECT_FAILED
747 ERROR_PAGE_FAULT_TRANSITION
748 ERROR_PAGE_FAULT_DEMAND_ZERO
749 ERROR_PAGE_FAULT_COPY_ON_WRITE
750 ERROR_PAGE_FAULT_GUARD_PAGE
751 ERROR_PAGE_FAULT_PAGING_FILE
752 ERROR_CACHE_PAGE_LOCKED
753 ERROR_CRASH_DUMP
754 ERROR_BUFFER_ALL_ZEROS
755 ERROR_REPARSE_OBJECT
756 ERROR_RESOURCE_REQUIREMENTS_CHANGED
757 ERROR_TRANSLATION_COMPLETE
758 ERROR_NOTHING_TO_TERMINATE
759 ERROR_PROCESS_NOT_IN_JOB
760 ERROR_PROCESS_IN_JOB
761 ERROR_VOLSNAP_HIBERNATE_READY
762 ERROR_FSFILTER_OP_COMPLETED_SUCCESSFULLY
763 ERROR_INTERRUPT_VECTOR_ALREADY_CONNECTED
764 ERROR_INTERRUPT_STILL_CONNECTED
765 ERROR_WAIT_FOR_OPLOCK
766 ERROR_DBG_EXCEPTION_HANDLED
767 ERROR_DBG_CONTINUE
768 ERROR_CALLBACK_POP_STACK
769 ERROR_COMPRESSION_DISABLED
770 ERROR_CANTFETCHBACKWARDS
771 ERROR_CANTSCROLLBACKWARDS
772 ERROR_ROWSNOTRELEASED
773 ERROR_BAD_ACCESSOR_FLAGS
774 ERROR_ERRORS_ENCOUNTERED
775 ERROR_NOT_CAPABLE
776 ERROR_REQUEST_OUT_OF_SEQUENCE
777 ERROR_VERSION_PARSE_ERROR
778 ERROR_BADSTARTPOSITION
779 ERROR_MEMORY_HARDWARE
780 ERROR_DISK_REPAIR_DISABLED
781 ERROR_INSUFFICIENT_RESOURCE_FOR_SPECIFIED_SHARED_SECTION_SIZE
782 ERROR_SYSTEM_POWERSTATE_TRANSITION
783 ERROR_SYSTEM_POWERSTATE_COMPLEX_TRANSITION
784 ERROR_MCA_EXCEPTION
785 ERROR_ACCESS_AUDIT_BY_POLICY
786 ERROR_ACCESS_DISABLED_NO_SAFER_UI_BY_POLICY
787 ERROR_ABANDON_HIBERFILE
788 ERROR_LOST_WRITEBEHIND_DATA_NETWORK_DISCONNECTED
789 ERROR_LOST_WRITEBEHIND_DATA_NETWORK_SERVER_ERROR
790 ERROR_LOST_WRITEBEHIND_DATA_LOCAL_DISK_ERROR
791 ERROR_BAD_MCFG_TABLE
792 ERROR_DISK_REPAIR_REDIRECTED
793 ERROR_DISK_REPAIR_UNSUCCESSFUL
794 ERROR_CORRUPT_LOG_OVERFULL
795 ERROR_CORRUPT_LOG_CORRUPTED
796 ERROR_CORRUPT_LOG_UNAVAILABLE
797 ERROR_CORRUPT_LOG_DELETED_FULL
798 ERROR_CORRUPT_LOG_CLEARED
799 ERROR_ORPHAN_NAME_EXHAUSTED
800 ERROR_OPLOCK_SWITCHED_TO_NEW_HANDLE
801 ERROR_CANNOT_GRANT_REQUESTED_OPLOCK
802 ERROR_CANNOT_BREAK_OPLOCK
803 ERROR_OPLOCK_HANDLE_CLOSED
804 ERROR_NO_ACE_CONDITION
805 ERROR_INVALID_ACE_CONDITION
806 ERROR_FILE_HANDLE_REVOKED
807 ERROR_IMAGE_AT_DIFFERENT_BASE
808 ERROR_ENCRYPTED_IO_NOT_POSSIBLE
809 ERROR_FILE_METADATA_OPTIMIZATION_IN_PROGRESS
810 ERROR_QUOTA_ACTIVITY
811 ERROR_HANDLE_REVOKED
812 ERROR_CALLBACK_INVOKE_INLINE
813 ERROR_CPU_SET_INVALID
814 ERROR_ENCLAVE_NOT_TERMINATED
994 ERROR_EA_ACCESS_DENIED
995 ERROR_OPERATION_ABORTED
996 ERROR_IO_INCOMPLETE
997 ERROR_IO_PENDING
998 ERROR_NOACCESS
999 ERROR_SWAPERROR
1001 ERROR_STACK_OVERFLOW
1002 ERROR_INVALID_MESSAGE
1003 ERROR_CAN_NOT_COMPLETE
1004 ERROR_INVALID_FLAGS
1005 ERROR_UNRECOGNIZED_VOLUME
1006 ERROR_FILE_INVALID
1007 ERROR_FULLSCREEN_MODE
1008 ERROR_NO_TOKEN
1009 ERROR_BADDB
1010 ERROR_BADKEY
1011 ERROR_CANTOPEN
1012 ERROR_CANTREAD
1013 ERROR_CANTWRITE
1014 ERROR_REGISTRY_RECOVERED
1015 ERROR_REGISTRY_CORRUPT
1016 ERROR_REGISTRY_IO_FAILED
1017 ERROR_NOT_REGISTRY_FILE
1018 ERROR_KEY_DELETED
1019 ERROR_NO_LOG_SPACE
1020 ERROR_KEY_HAS_CHILDREN
1021 ERROR_CHILD_MUST_BE_VOLATILE
1022 ERROR_NOTIFY_ENUM_DIR
1051 ERROR_DEPENDENT_SERVICES_RUNNING
1052 ERROR_INVALID_SERVICE_CONTROL
1053 ERROR_SERVICE_REQUEST_TIMEOUT
1054 ERROR_SERVICE_NO_THREAD
1055 ERROR_SERVICE_DATABASE_LOCKED
1056 ERROR_SERVICE_ALREADY_RUNNING
1057 ERROR_INVALID_SERVICE_ACCOUNT
1058 ERROR_SERVICE_DISABLED
1059 ERROR_CIRCULAR_DEPENDENCY
1060 ERROR_SERVICE_DOES_NOT_EXIST
1061 ERROR_SERVICE_CANNOT_ACCEPT_CTRL
1062 ERROR_SERVICE_NOT_ACTIVE
1063 ERROR_FAILED_SERVICE_CONTROLLER_CONNECT
1064 ERROR_EXCEPTION_IN_SERVICE
1065 ERROR_DATABASE_DOES_NOT_EXIST
1066 ERROR_SERVICE_SPECIFIC_ERROR
1067 ERROR_PROCESS_ABORTED
1068 ERROR_SERVICE_DEPENDENCY_FAIL
1069 ERROR_SERVICE_LOGON_FAILED
1070 ERROR_SERVICE_START_HANG
1071 ERROR_INVALID_SERVICE_LOCK
1072 ERROR_SERVICE_MARKED_FOR_DELETE
1073 ERROR_SERVICE_EXISTS
1074 ERROR_ALREADY_RUNNING_LKG
1075 ERROR_SERVICE_DEPENDENCY_DELETED
1076 ERROR_BOOT_ALREADY_ACCEPTED
1077 ERROR_SERVICE_NEVER_STARTED
1078 ERROR_DUPLICATE_SERVICE_NAME
1079 ERROR_DIFFERENT_SERVICE_ACCOUNT
1080 ERROR_CANNOT_DETECT_DRIVER_FAILURE
1081 ERROR_CANNOT_DETECT_PROCESS_ABORT
1082 ERROR_NO_RECOVERY_PROGRAM
1083 ERROR_SERVICE_NOT_IN_EXE
1084 ERROR_NOT_SAFEBOOT_SERVICE
1100 ERROR_END_OF_MEDIA
1101 ERROR_FILEMARK_DETECTED
1102 ERROR_BEGINNING_OF_MEDIA
1103 ERROR_SETMARK_DETECTED
1104 ERROR_NO_DATA_DETECTED
1105 ERROR_PARTITION_FAILURE
1106 ERROR_INVALID_BLOCK_LENGTH
1107 ERROR_DEVICE_NOT_PARTITIONED
1108 ERROR_UNABLE_TO_LOCK_MEDIA
1109 ERROR_UNABLE_TO_UNLOAD_MEDIA
1110 ERROR_MEDIA_CHANGED
1111 ERROR_BUS_RESET
1112 ERROR_NO_MEDIA_IN_DRIVE
1113 ERROR_NO_UNICODE_TRANSLATION
1114 ERROR_DLL_INIT_FAILED
1115 ERROR_SHUTDOWN_IN_PROGRESS
1116 ERROR_NO_SHUTDOWN_IN_PROGRESS
1117 ERROR_IO_DEVICE
1118 ERROR_SERIAL_NO_DEVICE
1119 ERROR_IRQ_BUSY
1120 ERROR_MORE_WRITES
1121 ERROR_COUNTER_TIMEOUT
1122 ERROR_FLOPPY_ID_MARK_NOT_FOUND
1123 ERROR_FLOPPY_WRONG_CYLINDER
1124 ERROR_FLOPPY_UNKNOWN_ERROR
1125 ERROR_FLOPPY_BAD_REGISTERS
1126 ERROR_DISK_RECALIBRATE_FAILED
1127 ERROR_DISK_OPERATION_FAILED
1128 ERROR_DISK_RESET_FAILED
1129 ERROR_EOM_OVERFLOW
1130 ERROR_NOT_ENOUGH_SERVER_MEMORY
1131 ERROR_POSSIBLE_DEADLOCK
1132 ERROR_MAPPED_ALIGNMENT
1140 ERROR_SET_POWER_STATE_VETOED
1141 ERROR_SET_POWER_STATE_FAILED
1142 ERROR_TOO_MANY_LINKS
1150 ERROR_OLD_WIN_VERSION
1151 ERROR_APP_WRONG_OS
1152 ERROR_SINGLE_INSTANCE_APP
1153 ERROR_RMODE_APP
1154 ERROR_INVALID_DLL
1155 ERROR_NO_ASSOCIATION
1156 ERROR_DDE_FAIL
1157 ERROR_DLL_NOT_FOUND
1158 ERROR_NO_MORE_USER_HANDLES
1159 ERROR_MESSAGE_SYNC_ONLY
1160 ERROR_SOURCE_ELEMENT_EMPTY
1161 ERROR_DESTINATION_ELEMENT_FULL
1162 ERROR_ILLEGAL_ELEMENT_ADDRESS
1163 ERROR_MAGAZINE_NOT_PRESENT
1164 ERROR_DEVICE_REINITIALIZATION_NEEDED
1165 ERROR_DEVICE_REQUIRES_CLEANING
1166 ERROR_DEVICE_DOOR_OPEN
1167 ERROR_DEVICE_NOT_CONNECTED
1168 ERROR_NOT_FOUND
1169 ERROR_NO_MATCH
1170 ERROR_SET_NOT_FOUND
1171 ERROR_POINT_NOT_FOUND
1172 ERROR_NO_TRACKING_SERVICE
1173 ERROR_NO_VOLUME_ID
1175 ERROR_UNABLE_TO_REMOVE_REPLACED
1176 ERROR_UNABLE_TO_MOVE_REPLACEMENT
1177 ERROR_UNABLE_TO_MOVE_REPLACEMENT_2
1178 ERROR_JOURNAL_DELETE_IN_PROGRESS
1179 ERROR_JOURNAL_NOT_ACTIVE
1180 ERROR_POTENTIAL_FILE_FOUND
1181 ERROR_JOURNAL_ENTRY_DELETED
1183 ERROR_VRF_CFG_ENABLED
1184 ERROR_PARTITION_TERMINATING
1190 ERROR_SHUTDOWN_IS_SCHEDULED
1191 ERROR_SHUTDOWN_USERS_LOGGED_ON
1200 ERROR_BAD_DEVICE
1201 ERROR_CONNECTION_UNAVAIL
1202 ERROR_DEVICE_ALREADY_REMEMBERED
1203 ERROR_NO_NET_OR_BAD_PATH
1204 ERROR_BAD_PROVIDER
1205 ERROR_CANNOT_OPEN_PROFILE
1206 ERROR_BAD_PROFILE
1207 ERROR_NOT_CONTAINER
1208 ERROR_EXTENDED_ERROR
1209 ERROR_INVALID_GROUPNAME
1210 ERROR_INVALID_COMPUTERNAME
1211 ERROR_INVALID_EVENTNAME
1212 ERROR_INVALID_DOMAINNAME
1213 ERROR_INVALID_SERVICENAME
1214 ERROR_INVALID_NETNAME
1215 ERROR_INVALID_SHARENAME
1216 ERROR_INVALID_PASSWORDNAME
1217 ERROR_INVALID_MESSAGENAME
1218 ERROR_INVALID_MESSAGEDEST
1219 ERROR_SESSION_CREDENTIAL_CONFLICT
1220 ERROR_REMOTE_SESSION_LIMIT_EXCEEDED
1221 ERROR_DUP_DOMAINNAME
1222 ERROR_NO_NETWORK
1223 ERROR_CANCELLED
1224 ERROR_USER_MAPPED_FILE
1225 ERROR_CONNECTION_REFUSED
1226 ERROR_GRACEFUL_DISCONNECT
1227 ERROR_ADDRESS_ALREADY_ASSOCIATED
1228 ERROR_ADDRESS_NOT_ASSOCIATED
1229 ERROR_CONNECTION_INVALID
1230 ERROR_CONNECTION_ACTIVE
1231 ERROR_NETWORK_UNREACHABLE
1232 ERROR_HOST_UNREACHABLE
1233 ERROR_PROTOCOL_UNREACHABLE
1234 ERROR_PORT_UNREACHABLE
1235 ERROR_REQUEST_ABORTED
1236 ERROR_CONNECTION_ABORTED
1237 ERROR_RETRY
1238 ERROR_CONNECTION_COUNT_LIMIT
1239 ERROR_LOGIN_TIME_RESTRICTION
1240 ERROR_LOGIN_WKSTA_RESTRICTION
1241 ERROR_INCORRECT_ADDRESS
1242 ERROR_ALREADY_REGISTERED
1243 ERROR_SERVICE_NOT_FOUND
1244 ERROR_NOT_AUTHENTICATED
1245 ERROR_NOT_LOGGED_ON
1246 ERROR_CONTINUE
1247 ERROR_ALREADY_INITIALIZED
1248 ERROR_NO_MORE_DEVICES
1249 ERROR_NO_SUCH_SITE
1250 ERROR_DOMAIN_CONTROLLER_EXISTS
1251 ERROR_ONLY_IF_CONNECTED
1252 ERROR_OVERRIDE_NOCHANGES
1253 ERROR_BAD_USER_PROFILE
1254 ERROR_NOT_SUPPORTED_ON_SBS
1255 ERROR_SERVER_SHUTDOWN_IN_PROGRESS
1256 ERROR_HOST_DOWN
1257 ERROR_NON_ACCOUNT_SID
1258 ERROR_NON_DOMAIN_SID
1259 ERROR_APPHELP_BLOCK
1260 ERROR_ACCESS_DISABLED_BY_POLICY
1261 ERROR_REG_NAT_CONSUMPTION
1262 ERROR_CSCSHARE_OFFLINE
1263 ERROR_PKINIT_FAILURE
1264 ERROR_SMARTCARD_SUBSYSTEM_FAILURE
1265 ERROR_DOWNGRADE_DETECTED
1271 ERROR_MACHINE_LOCKED
1272 ERROR_SMB_GUEST_LOGON_BLOCKED
1273 ERROR_CALLBACK_SUPPLIED_INVALID_DATA
1274 ERROR_SYNC_FOREGROUND_REFRESH_REQUIRED
1275 ERROR_DRIVER_BLOCKED
1276 ERROR_INVALID_IMPORT_OF_NON_DLL
1277 ERROR_ACCESS_DISABLED_WEBBLADE
1278 ERROR_ACCESS_DISABLED_WEBBLADE_TAMPER
1279 ERROR_RECOVERY_FAILURE
1280 ERROR_ALREADY_FIBER
1281 ERROR_ALREADY_THREAD
1282 ERROR_STACK_BUFFER_OVERRUN
1283 ERROR_PARAMETER_QUOTA_EXCEEDED
1284 ERROR_DEBUGGER_INACTIVE
1285 ERROR_DELAY_LOAD_FAILED
1286 ERROR_VDM_DISALLOWED
1287 ERROR_UNIDENTIFIED_ERROR
1288 ERROR_INVALID_CRUNTIME_PARAMETER
1289 ERROR_BEYOND_VDL
1290 ERROR_INCOMPATIBLE_SERVICE_SID_TYPE
1291 ERROR_DRIVER_PROCESS_TERMINATED
1292 ERROR_IMPLEMENTATION_LIMIT
1293 ERROR_PROCESS_IS_PROTECTED
1294 ERROR_SERVICE_NOTIFY_CLIENT_LAGGING
1295 ERROR_DISK_QUOTA_EXCEEDED
1296 ERROR_CONTENT_BLOCKED
1297 ERROR_INCOMPATIBLE_SERVICE_PRIVILEGE
1298 ERROR_APP_HANG
1299 ERROR_INVALID_LABEL
1300 ERROR_NOT_ALL_ASSIGNED
1301 ERROR_SOME_NOT_MAPPED
1302 ERROR_NO_QUOTAS_FOR_ACCOUNT
1303 ERROR_LOCAL_USER_SESSION_KEY
1304 ERROR_NULL_LM_PASSWORD
1305 ERROR_UNKNOWN_REVISION
1306 ERROR_REVISION_MISMATCH
1307 ERROR_INVALID_OWNER
1308 ERROR_INVALID_PRIMARY_GROUP
1309 ERROR_NO_IMPERSONATION_TOKEN
1310 ERROR_CANT_DISABLE_MANDATORY
1311 ERROR_NO_LOGON_SERVERS
1312 ERROR_NO_SUCH_LOGON_SESSION
1313 ERROR_NO_SUCH_PRIVILEGE
1314 ERROR_PRIVILEGE_NOT_HELD
1315 ERROR_INVALID_ACCOUNT_NAME
1316 ERROR_USER_EXISTS
1317 ERROR_NO_SUCH_USER
1318 ERROR_GROUP_EXISTS
1319 ERROR_NO_SUCH_GROUP
1320 ERROR_MEMBER_IN_GROUP
1321 ERROR_MEMBER_NOT_IN_GROUP
1322 ERROR_LAST_ADMIN
1323 ERROR_WRONG_PASSWORD
1324 ERROR_ILL_FORMED_PASSWORD
1325 ERROR_PASSWORD_RESTRICTION
1326 ERROR_LOGON_FAILURE
1327 ERROR_ACCOUNT_RESTRICTION
1328 ERROR_INVALID_LOGON_HOURS
1329 ERROR_INVALID_WORKSTATION
1330 ERROR_PASSWORD_EXPIRED
1331 ERROR_ACCOUNT_DISABLED
1332 ERROR_NONE_MAPPED
1333 ERROR_TOO_MANY_LUIDS_REQUESTED
1334 ERROR_LUIDS_EXHAUSTED
1335 ERROR_INVALID_SUB_AUTHORITY
1336 ERROR_INVALID_ACL
1337 ERROR_INVALID_SID
1338 ERROR_INVALID_SECURITY_DESCR
1340 ERROR_BAD_INHERITANCE_ACL
1341 ERROR_SERVER_DISABLED
1342 ERROR_SERVER_NOT_DISABLED
1343 ERROR_INVALID_ID_AUTHORITY
1344 ERROR_ALLOTTED_SPACE_EXCEEDED
1345 ERROR_INVALID_GROUP_ATTRIBUTES
1346 ERROR_BAD_IMPERSONATION_LEVEL
1347 ERROR_CANT_OPEN_ANONYMOUS
1348 ERROR_BAD_VALIDATION_CLASS
1349 ERROR_BAD_TOKEN_TYPE
1350 ERROR_NO_SECURITY_ON_OBJECT
1351 ERROR_CANT_ACCESS_DOMAIN_INFO
1352 ERROR_INVALID_SERVER_STATE
1353 ERROR_INVALID_DOMAIN_STATE
1354 ERROR_INVALID_DOMAIN_ROLE
1355 ERROR_NO_SUCH_DOMAIN
1356 ERROR_DOMAIN_EXISTS
1357 ERROR_DOMAIN_LIMIT_EXCEEDED
1358 ERROR_INTERNAL_DB_CORRUPTION
1359 ERROR_INTERNAL_ERROR
1360 ERROR_GENERIC_NOT_MAPPED
1361 ERROR_BAD_DESCRIPTOR_FORMAT
1362 ERROR_NOT_LOGON_PROCESS
1363 ERROR_LOGON_SESSION_EXISTS
1364 ERROR_NO_SUCH_PACKAGE
1365 ERROR_BAD_LOGON_SESSION_STATE
1366 ERROR_LOGON_SESSION_COLLISION
1367 ERROR_INVALID_LOGON_TYPE
1368 ERROR_CANNOT_IMPERSONATE
1369 ERROR_RXACT_INVALID_STATE
1370 ERROR_RXACT_COMMIT_FAILURE
1371 ERROR_SPECIAL_ACCOUNT
1372 ERROR_SPECIAL_GROUP
1373 ERROR_SPECIAL_USER
1374 ERROR_MEMBERS_PRIMARY_GROUP
1375 ERROR_TOKEN_ALREADY_IN_USE
1376 ERROR_NO_SUCH_ALIAS
1377 ERROR_MEMBER_NOT_IN_ALIAS
1378 ERROR_MEMBER_IN_ALIAS
1379 ERROR_ALIAS_EXISTS
1380 ERROR_LOGON_NOT_GRANTED
1381 ERROR_TOO_MANY_SECRETS
1382 ERROR_SECRET_TOO_LONG
1383 ERROR_INTERNAL_DB_ERROR
1384 ERROR_TOO_MANY_CONTEXT_IDS
1385 ERROR_LOGON_TYPE_NOT_GRANTED
1386 ERROR_NT_CROSS_ENCRYPTION_REQUIRED
1387 ERROR_NO_SUCH_MEMBER
1388 ERROR_INVALID_MEMBER
1389 ERROR_TOO_MANY_SIDS
1390 ERROR_LM_CROSS_ENCRYPTION_REQUIRED
1391 ERROR_NO_INHERITANCE
1392 ERROR_FILE_CORRUPT
1393 ERROR_DISK_CORRUPT
1394 ERROR_NO_USER_SESSION_KEY
1395 ERROR_LICENSE_QUOTA_EXCEEDED
1396 ERROR_WRONG_TARGET_NAME
1397 ERROR_MUTUAL_AUTH_FAILED
1398 ERROR_TIME_SKEW
1399 ERROR_CURRENT_DOMAIN_NOT_ALLOWED
1400 ERROR_INVALID_WINDOW_HANDLE
1401 ERROR_INVALID_MENU_HANDLE
1402 ERROR_INVALID_CURSOR_HANDLE
1403 ERROR_INVALID_ACCEL_HANDLE
1404 ERROR_INVALID_HOOK_HANDLE
1405 ERROR_INVALID_DWP_HANDLE
1406 ERROR_TLW_WITH_WSCHILD
1407 ERROR_CANNOT_FIND_WND_CLASS
1408 ERROR_WINDOW_OF_OTHER_THREAD
1409 ERROR_HOTKEY_ALREADY_REGISTERED
1410 ERROR_CLASS_ALREADY_EXISTS
1411 ERROR_CLASS_DOES_NOT_EXIST
1412 ERROR_CLASS_HAS_WINDOWS
1413 ERROR_INVALID_INDEX
1414 ERROR_INVALID_ICON_HANDLE
1415 ERROR_PRIVATE_DIALOG_INDEX
1416 ERROR_LISTBOX_ID_NOT_FOUND
1417 ERROR_NO_WILDCARD_CHARACTERS
1418 ERROR_CLIPBOARD_NOT_OPEN
1419 ERROR_HOTKEY_NOT_REGISTERED
1420 ERROR_WINDOW_NOT_DIALOG
1421 ERROR_CONTROL_ID_NOT_FOUND
1422 ERROR_INVALID_COMBOBOX_MESSAGE
1423 ERROR_WINDOW_NOT_COMBOBOX
1424 ERROR_INVALID_EDIT_HEIGHT
1425 ERROR_DC_NOT_FOUND
1426 ERROR_INVALID_HOOK_FILTER
1427 ERROR_INVALID_FILTER_PROC
1428 ERROR_HOOK_NEEDS_HMOD
1429 ERROR_GLOBAL_ONLY_HOOK
1430 ERROR_JOURNAL_HOOK_SET
1431 ERROR_HOOK_NOT_INSTALLED
1432 ERROR_INVALID_LB_MESSAGE
1433 ERROR_SETCOUNT_ON_BAD_LB
1434 ERROR_LB_WITHOUT_TABSTOPS
1435 ERROR_DESTROY_OBJECT_OF_OTHER_THREAD
1436 ERROR_CHILD_WINDOW_MENU
1437 ERROR_NO_SYSTEM_MENU
1438 ERROR_INVALID_MSGBOX_STYLE
1439 ERROR_INVALID_SPI_VALUE
1440 ERROR_SCREEN_ALREADY_LOCKED
1441 ERROR_HWNDS_HAVE_DIFF_PARENT
1442 ERROR_NOT_CHILD_WINDOW
1443 ERROR_INVALID_GW_COMMAND
1444 ERROR_INVALID_THREAD_ID
1445 ERROR_NON_MDICHILD_WINDOW
1446 ERROR_POPUP_ALREADY_ACTIVE
1447 ERROR_NO_SCROLLBARS
1448 ERROR_INVALID_SCROLLBAR_RANGE
1449 ERROR_INVALID_SHOWWIN_COMMAND
1450 ERROR_NO_SYSTEM_RESOURCES
1451 ERROR_NONPAGED_SYSTEM_RESOURCES
1452 ERROR_PAGED_SYSTEM_RESOURCES
1453 ERROR_WORKING_SET_QUOTA
1454 ERROR_PAGEFILE_QUOTA
1455 ERROR_COMMITMENT_LIMIT
1456 ERROR_MENU_ITEM_NOT_FOUND
1457 ERROR_INVALID_KEYBOARD_HANDLE
1458 ERROR_HOOK_TYPE_NOT_ALLOWED
1459 ERROR_REQUIRES_INTERACTIVE_WINDOWSTATION
1460 ERROR_TIMEOUT
1461 ERROR_INVALID_MONITOR_HANDLE
1462 ERROR_INCORRECT_SIZE
1463 ERROR_SYMLINK_CLASS_DISABLED
1464 ERROR_SYMLINK_NOT_SUPPORTED
1465 ERROR_XML_PARSE_ERROR
1466 ERROR_XMLDSIG_ERROR
1467 ERROR_RESTART_APPLICATION
1468 ERROR_WRONG_COMPARTMENT
1469 ERROR_AUTHIP_FAILURE
1470 ERROR_NO_NVRAM_RESOURCES
1471 ERROR_NOT_GUI_PROCESS
1500 ERROR_EVENTLOG_FILE_CORRUPT
1501 ERROR_EVENTLOG_CANT_START
1502 ERROR_LOG_FILE_FULL
1503 ERROR_EVENTLOG_FILE_CHANGED
1504 ERROR_CONTAINER_ASSIGNED
1505 ERROR_JOB_NO_CONTAINER
1550 ERROR_INVALID_TASK_NAME
1551 ERROR_INVALID_TASK_INDEX
1552 ERROR_THREAD_ALREADY_IN_TASK
1601 ERROR_INSTALL_SERVICE_FAILURE
1602 ERROR_INSTALL_USEREXIT
1603 ERROR_INSTALL_FAILURE
1604 ERROR_INSTALL_SUSPEND
1605 ERROR_UNKNOWN_PRODUCT
1606 ERROR_UNKNOWN_FEATURE
1607 ERROR_UNKNOWN_COMPONENT
1608 ERROR_UNKNOWN_PROPERTY
1609 ERROR_INVALID_HANDLE_STATE
1610 ERROR_BAD_CONFIGURATION
1611 ERROR_INDEX_ABSENT
1612 ERROR_INSTALL_SOURCE_ABSENT
1613 ERROR_INSTALL_PACKAGE_VERSION
1614 ERROR_PRODUCT_UNINSTALLED
1615 ERROR_BAD_QUERY_SYNTAX
1616 ERROR_INVALID_FIELD
1617 ERROR_DEVICE_REMOVED
1618 ERROR_INSTALL_ALREADY_RUNNING
1619 ERROR_INSTALL_PACKAGE_OPEN_FAILED
1620 ERROR_INSTALL_PACKAGE_INVALID
1621 ERROR_INSTALL_UI_FAILURE
1622 ERROR_INSTALL_LOG_FAILURE
1623 ERROR_INSTALL_LANGUAGE_UNSUPPORTED
1624 ERROR_INSTALL_TRANSFORM_FAILURE
1625 ERROR_INSTALL_PACKAGE_REJECTED
1626 ERROR_FUNCTION_NOT_CALLED
1627 ERROR_FUNCTION_FAILED
1628 ERROR_INVALID_TABLE
1629 ERROR_DATATYPE_MISMATCH
1630 ERROR_UNSUPPORTED_TYPE
1631 ERROR_CREATE_FAILED
1632 ERROR_INSTALL_TEMP_UNWRITABLE
1633 ERROR_INSTALL_PLATFORM_UNSUPPORTED
1634 ERROR_INSTALL_NOTUSED
1635 ERROR_PATCH_PACKAGE_OPEN_FAILED
1636 ERROR_PATCH_PACKAGE_INVALID
1637 ERROR_PATCH_PACKAGE_UNSUPPORTED
1638 ERROR_PRODUCT_VERSION
1639 ERROR_INVALID_COMMAND_LINE
1640 ERROR_INSTALL_REMOTE_DISALLOWED
1641 ERROR_SUCCESS_REBOOT_INITIATED
1642 ERROR_PATCH_TARGET_NOT_FOUND
1643 ERROR_PATCH_PACKAGE_REJECTED
1644 ERROR_INSTALL_TRANSFORM_REJECTED
1645 ERROR_INSTALL_REMOTE_PROHIBITED
1646 ERROR_PATCH_REMOVAL_UNSUPPORTED
1647 ERROR_UNKNOWN_PATCH
1648 ERROR_PATCH_NO_SEQUENCE
1649 ERROR_PATCH_REMOVAL_DISALLOWED
1650 ERROR_INVALID_PATCH_XML
1651 ERROR_PATCH_MANAGED_ADVERTISED_PRODUCT
1652 ERROR_INSTALL_SERVICE_SAFEBOOT
1653 ERROR_FAIL_FAST_EXCEPTION
1654 ERROR_INSTALL_REJECTED
1655 ERROR_DYNAMIC_CODE_BLOCKED
1656 ERROR_NOT_SAME_OBJECT
1657 ERROR_STRICT_CFG_VIOLATION
1660 ERROR_SET_CONTEXT_DENIED
1661 ERROR_CROSS_PARTITION_VIOLATION
1700 RPC_S_INVALID_STRING_BINDING
1701 RPC_S_WRONG_KIND_OF_BINDING
1702 RPC_S_INVALID_BINDING
1703 RPC_S_PROTSEQ_NOT_SUPPORTED
1704 RPC_S_INVALID_RPC_PROTSEQ
1705 RPC_S_INVALID_STRING_UUID
1706 RPC_S_INVALID_ENDPOINT_FORMAT
1707 RPC_S_INVALID_NET_ADDR
1708 RPC_S_NO_ENDPOINT_FOUND
1709 RPC_S_INVALID_TIMEOUT
1710 RPC_S_OBJECT_NOT_FOUND
1711 RPC_S_ALREADY_REGISTERED
1712 RPC_S_TYPE_ALREADY_REGISTERED
1713 RPC_S_ALREADY_LISTENING
1714 RPC_S_NO_PROTSEQS_REGISTERED
1715 RPC_S_NOT_LISTENING
1716 RPC_S_UNKNOWN_MGR_TYPE
1717 RPC_S_UNKNOWN_IF
1718 RPC_S_NO_BINDINGS
1719 RPC_S_NO_PROTSEQS
1720 RPC_S_CANT_CREATE_ENDPOINT
1721 RPC_S_OUT_OF_RESOURCES
1722 RPC_S_SERVER_UNAVAILABLE
1723 RPC_S_SERVER_TOO_BUSY
1724 RPC_S_INVALID_NETWORK_OPTIONS
1725 RPC_S_NO_CALL_ACTIVE
1726 RPC_S_CALL_FAILED
1727 RPC_S_CALL_FAILED_DNE
1728 RPC_S_PROTOCOL_ERROR
1729 RPC_S_PROXY_ACCESS_DENIED
1730 RPC_S_UNSUPPORTED_TRANS_SYN
1732 RPC_S_UNSUPPORTED_TYPE
1733 RPC_S_INVALID_TAG
1734 RPC_S_INVALID_BOUND
1735 RPC_S_NO_ENTRY_NAME
1736 RPC_S_INVALID_NAME_SYNTAX
1737 RPC_S_UNSUPPORTED_NAME_SYNTAX
1739 RPC_S_UUID_NO_ADDRESS
1740 RPC_S_DUPLICATE_ENDPOINT
1741 RPC_S_UNKNOWN_AUTHN_TYPE
1742 RPC_S_MAX_CALLS_TOO_SMALL
1743 RPC_S_STRING_TOO_LONG
1744 RPC_S_PROTSEQ_NOT_FOUND
1745 RPC_S_PROCNUM_OUT_OF_RANGE
1746 RPC_S_BINDING_HAS_NO_AUTH
1747 RPC_S_UNKNOWN_AUTHN_SERVICE
1748 RPC_S_UNKNOWN_AUTHN_LEVEL
1749 RPC_S_INVALID_AUTH_IDENTITY
1750 RPC_S_UNKNOWN_AUTHZ_SERVICE
1751 EPT_S_INVALID_ENTRY
1752 EPT_S_CANT_PERFORM_OP
1753 EPT_S_NOT_REGISTERED
1754 RPC_S_NOTHING_TO_EXPORT
1755 RPC_S_INCOMPLETE_NAME
1756 RPC_S_INVALID_VERS_OPTION
1757 RPC_S_NO_MORE_MEMBERS
1758 RPC_S_NOT_ALL_OBJS_UNEXPORTED
1759 RPC_S_INTERFACE_NOT_FOUND
1760 RPC_S_ENTRY_ALREADY_EXISTS
1761 RPC_S_ENTRY_NOT_FOUND
1762 RPC_S_NAME_SERVICE_UNAVAILABLE
1763 RPC_S_INVALID_NAF_ID
1764 RPC_S_CANNOT_SUPPORT
1765 RPC_S_NO_CONTEXT_AVAILABLE
1766 RPC_S_INTERNAL_ERROR
1767 RPC_S_ZERO_DIVIDE
1768 RPC_S_ADDRESS_ERROR
1769 RPC_S_FP_DIV_ZERO
1770 RPC_S_FP_UNDERFLOW
1771 RPC_S_FP_OVERFLOW
1772 RPC_X_NO_MORE_ENTRIES
1773 RPC_X_SS_CHAR_TRANS_OPEN_FAIL
1774 RPC_X_SS_CHAR_TRANS_SHORT_FILE
1775 RPC_X_SS_IN_NULL_CONTEXT
1777 RPC_X_SS_CONTEXT_DAMAGED
1778 RPC_X_SS_HANDLES_MISMATCH
1779 RPC_X_SS_CANNOT_GET_CALL_HANDLE
1780 RPC_X_NULL_REF_POINTER
1781 RPC_X_ENUM_VALUE_OUT_OF_RANGE
1782 RPC_X_BYTE_COUNT_TOO_SMALL
1783 RPC_X_BAD_STUB_DATA
1784 ERROR_INVALID_USER_BUFFER
1785 ERROR_UNRECOGNIZED_MEDIA
1786 ERROR_NO_TRUST_LSA_SECRET
1787 ERROR_NO_TRUST_SAM_ACCOUNT
1788 ERROR_TRUSTED_DOMAIN_FAILURE
1789 ERROR_TRUSTED_RELATIONSHIP_FAILURE
1790 ERROR_TRUST_FAILURE
1791 RPC_S_CALL_IN_PROGRESS
1792 ERROR_NETLOGON_NOT_STARTED
1793 ERROR_ACCOUNT_EXPIRED
1794 ERROR_REDIRECTOR_HAS_OPEN_HANDLES
1795 ERROR_PRINTER_DRIVER_ALREADY_INSTALLED
1796 ERROR_UNKNOWN_PORT
1797 ERROR_UNKNOWN_PRINTER_DRIVER
1798 ERROR_UNKNOWN_PRINTPROCESSOR
1799 ERROR_INVALID_SEPARATOR_FILE
1800 ERROR_INVALID_PRIORITY
1801 ERROR_INVALID_PRINTER_NAME
1802 ERROR_PRINTER_ALREADY_EXISTS
1803 ERROR_INVALID_PRINTER_COMMAND
1804 ERROR_INVALID_DATATYPE
1805 ERROR_INVALID_ENVIRONMENT
1806 RPC_S_NO_MORE_BINDINGS
1807 ERROR_NOLOGON_INTERDOMAIN_TRUST_ACCOUNT
1808 ERROR_NOLOGON_WORKSTATION_TRUST_ACCOUNT
1809 ERROR_NOLOGON_SERVER_TRUST_ACCOUNT
1810 ERROR_DOMAIN_TRUST_INCONSISTENT
1811 ERROR_SERVER_HAS_OPEN_HANDLES
1812 ERROR_RESOURCE_DATA_NOT_FOUND
1813 ERROR_RESOURCE_TYPE_NOT_FOUND
1814 ERROR_RESOURCE_NAME_NOT_FOUND
1815 ERROR_RESOURCE_LANG_NOT_FOUND
1816 ERROR_NOT_ENOUGH_QUOTA
1817 RPC_S_NO_INTERFACES
1818 RPC_S_CALL_CANCELLED
1819 RPC_S_BINDING_INCOMPLETE
1820 RPC_S_COMM_FAILURE
1821 RPC_S_UNSUPPORTED_AUTHN_LEVEL
1822 RPC_S_NO_PRINC_NAME
1823 RPC_S_NOT_RPC_ERROR
1824 RPC_S_UUID_LOCAL_ONLY
1825 RPC_S_SEC_PKG_ERROR
1826 RPC_S_NOT_CANCELLED
1827 RPC_X_INVALID_ES_ACTION
1828 RPC_X_WRONG_ES_VERSION
1829 RPC_X_WRONG_STUB_VERSION
1830 RPC_X_INVALID_PIPE_OBJECT
1831 RPC_X_WRONG_PIPE_ORDER
1832 RPC_X_WRONG_PIPE_VERSION
1833 RPC_S_COOKIE_AUTH_FAILED
1834 RPC_S_DO_NOT_DISTURB
1835 RPC_S_SYSTEM_HANDLE_COUNT_EXCEEDED
1836 RPC_S_SYSTEM_HANDLE_TYPE_MISMATCH
1898 RPC_S_GROUP_MEMBER_NOT_FOUND
1899 EPT_S_CANT_CREATE
1900 RPC_S_INVALID_OBJECT
1901 ERROR_INVALID_TIME
1902 ERROR_INVALID_FORM_NAME
1903 ERROR_INVALID_FORM_SIZE
1904 ERROR_ALREADY_WAITING
1905 ERROR_PRINTER_DELETED
1906 ERROR_INVALID_PRINTER_STATE
1907 ERROR_PASSWORD_MUST_CHANGE
1908 ERROR_DOMAIN_CONTROLLER_NOT_FOUND
1909 ERROR_ACCOUNT_LOCKED_OUT
1910 OR_INVALID_OXID
1911 OR_INVALID_OID
1912 OR_INVALID_SET
1913 RPC_S_SEND_INCOMPLETE
1914 RPC_S_INVALID_ASYNC_HANDLE
1915 RPC_S_INVALID_ASYNC_CALL
1916 RPC_X_PIPE_CLOSED
1917 RPC_X_PIPE_DISCIPLINE_ERROR
1918 RPC_X_PIPE_EMPTY
1919 ERROR_NO_SITENAME
1920 ERROR_CANT_ACCESS_FILE
1921 ERROR_CANT_RESOLVE_FILENAME
1922 RPC_S_ENTRY_TYPE_MISMATCH
1923 RPC_S_NOT_ALL_OBJS_EXPORTED
1924 RPC_S_INTERFACE_NOT_EXPORTED
1925 RPC_S_PROFILE_NOT_ADDED
1926 RPC_S_PRF_ELT_NOT_ADDED
1927 RPC_S_PRF_ELT_NOT_REMOVED
1928 RPC_S_GRP_ELT_NOT_ADDED
1929 RPC_S_GRP_ELT_NOT_REMOVED
1930 ERROR_KM_DRIVER_BLOCKED
1931 ERROR_CONTEXT_EXPIRED
1932 ERROR_PER_USER_TRUST_QUOTA_EXCEEDED
1933 ERROR_ALL_USER_TRUST_QUOTA_EXCEEDED
1934 ERROR_USER_DELETE_TRUST_QUOTA_EXCEEDED
1935 ERROR_AUTHENTICATION_FIREWALL_FAILED
1936 ERROR_REMOTE_PRINT_CONNECTIONS_BLOCKED
1937 ERROR_NTLM_BLOCKED
1938 ERROR_PASSWORD_CHANGE_REQUIRED
1939 ERROR_LOST_MODE_LOGON_RESTRICTION
2000 ERROR_INVALID_PIXEL_FORMAT
2001 ERROR_BAD_DRIVER
2002 ERROR_INVALID_WINDOW_STYLE
2003 ERROR_METAFILE_NOT_SUPPORTED
2004 ERROR_TRANSFORM_NOT_SUPPORTED
2005 ERROR_CLIPPING_NOT_SUPPORTED
2010 ERROR_INVALID_CMM
2011 ERROR_INVALID_PROFILE
2012 ERROR_TAG_NOT_FOUND
2013 ERROR_TAG_NOT_PRESENT
2014 ERROR_DUPLICATE_TAG
2015 ERROR_PROFILE_NOT_ASSOCIATED_WITH_DEVICE
2016 ERROR_PROFILE_NOT_FOUND
2017 ERROR_INVALID_COLORSPACE
2018 ERROR_ICM_NOT_ENABLED
2019 ERROR_DELETING_ICM_XFORM
2020 ERROR_INVALID_TRANSFORM
2021 ERROR_COLORSPACE_MISMATCH
2022 ERROR_INVALID_COLORINDEX
2023 ERROR_PROFILE_DOES_NOT_MATCH_DEVICE
2108 ERROR_CONNECTED_OTHER_PASSWORD
2109 ERROR_CONNECTED_OTHER_PASSWORD_DEFAULT
2202 ERROR_BAD_USERNAME
2250 ERROR_NOT_CONNECTED
2401 ERROR_OPEN_FILES
2402 ERROR_ACTIVE_CONNECTIONS
2404 ERROR_DEVICE_IN_USE
3000 ERROR_UNKNOWN_PRINT_MONITOR
3001 ERROR_PRINTER_DRIVER_IN_USE
3002 ERROR_SPOOL_FILE_NOT_FOUND
3003 ERROR_SPL_NO_STARTDOC
3004 ERROR_SPL_NO_ADDJOB
3005 ERROR_PRINT_PROCESSOR_ALREADY_INSTALLED
3006 ERROR_PRINT_MONITOR_ALREADY_INSTALLED
3007 ERROR_INVALID_PRINT_MONITOR
3008 ERROR_PRINT_MONITOR_IN_USE
3009 ERROR_PRINTER_HAS_JOBS_QUEUED
3010 ERROR_SUCCESS_REBOOT_REQUIRED
3011 ERROR_SUCCESS_RESTART_REQUIRED
3012 ERROR_PRINTER_NOT_FOUND
3013 ERROR_PRINTER_DRIVER_WARNED
3014 ERROR_PRINTER_DRIVER_BLOCKED
3015 ERROR_PRINTER_DRIVER_PACKAGE_IN_USE
3016 ERROR_CORE_DRIVER_PACKAGE_NOT_FOUND
3017 ERROR_FAIL_REBOOT_REQUIRED
3018 ERROR_FAIL_REBOOT_INITIATED
3019 ERROR_PRINTER_DRIVER_DOWNLOAD_NEEDED
3020 ERROR_PRINT_JOB_RESTART_REQUIRED
3021 ERROR_INVALID_PRINTER_DRIVER_MANIFEST
3022 ERROR_PRINTER_NOT_SHAREABLE
3050 ERROR_REQUEST_PAUSED
3950 ERROR_IO_REISSUE_AS_CACHED
4000 ERROR_WINS_INTERNAL
4001 ERROR_CAN_NOT_DEL_LOCAL_WINS
4002 ERROR_STATIC_INIT
4003 ERROR_INC_BACKUP
4004 ERROR_FULL_BACKUP
4005 ERROR_REC_NON_EXISTENT
4006 ERROR_RPL_NOT_ALLOWED
4050 PEERDIST_ERROR_CONTENTINFO_VERSION_UNSUPPORTED
4051 PEERDIST_ERROR_CANNOT_PARSE_CONTENTINFO
4052 PEERDIST_ERROR_MISSING_DATA
4053 PEERDIST_ERROR_NO_MORE
4054 PEERDIST_ERROR_NOT_INITIALIZED
4055 PEERDIST_ERROR_ALREADY_INITIALIZED
4056 PEERDIST_ERROR_SHUTDOWN_IN_PROGRESS
4057 PEERDIST_ERROR_INVALIDATED
4058 PEERDIST_ERROR_ALREADY_EXISTS
4059 PEERDIST_ERROR_OPERATION_NOTFOUND
4060 PEERDIST_ERROR_ALREADY_COMPLETED
4061 PEERDIST_ERROR_OUT_OF_BOUNDS
4062 PEERDIST_ERROR_VERSION_UNSUPPORTED
4063 PEERDIST_ERROR_INVALID_CONFIGURATION
4064 PEERDIST_ERROR_NOT_LICENSED
4065 PEERDIST_ERROR_SERVICE_UNAVAILABLE
4066 PEERDIST_ERROR_TRUST_FAILURE
4100 ERROR_DHCP_ADDRESS_CONFLICT
4200 ERROR_WMI_GUID_NOT_FOUND
4201 ERROR_WMI_INSTANCE_NOT_FOUND
4202 ERROR_WMI_ITEMID_NOT_FOUND
4203 ERROR_WMI_TRY_AGAIN
4204 ERROR_WMI_DP_NOT_FOUND
4205 ERROR_WMI_UNRESOLVED_INSTANCE_REF
4206 ERROR_WMI_ALREADY_ENABLED
4207 ERROR_WMI_GUID_DISCONNECTED
4208 ERROR_WMI_SERVER_UNAVAILABLE
4209 ERROR_WMI_DP_FAILED
4210 ERROR_WMI_INVALID_MOF
4211 ERROR_WMI_INVALID_REGINFO
4212 ERROR_WMI_ALREADY_DISABLED
4213 ERROR_WMI_READ_ONLY
4214 ERROR_WMI_SET_FAILURE
4250 ERROR_NOT_APPCONTAINER
4251 ERROR_APPCONTAINER_REQUIRED
4252 ERROR_NOT_SUPPORTED_IN_APPCONTAINER
4253 ERROR_INVALID_PACKAGE_SID_LENGTH
4300 ERROR_INVALID_MEDIA
4301 ERROR_INVALID_LIBRARY
4302 ERROR_INVALID_MEDIA_POOL
4303 ERROR_DRIVE_MEDIA_MISMATCH
4304 ERROR_MEDIA_OFFLINE
4305 ERROR_LIBRARY_OFFLINE
4306 ERROR_EMPTY
4307 ERROR_NOT_EMPTY
4308 ERROR_MEDIA_UNAVAILABLE
4309 ERROR_RESOURCE_DISABLED
4310 ERROR_INVALID_CLEANER
4311 ERROR_UNABLE_TO_CLEAN
4312 ERROR_OBJECT_NOT_FOUND
4313 ERROR_DATABASE_FAILURE
4314 ERROR_DATABASE_FULL
4315 ERROR_MEDIA_INCOMPATIBLE
4316 ERROR_RESOURCE_NOT_PRESENT
4317 ERROR_INVALID_OPERATION
4318 ERROR_MEDIA_NOT_AVAILABLE
4319 ERROR_DEVICE_NOT_AVAILABLE
4320 ERROR_REQUEST_REFUSED
4321 ERROR_INVALID_DRIVE_OBJECT
4322 ERROR_LIBRARY_FULL
4323 ERROR_MEDIUM_NOT_ACCESSIBLE
4324 ERROR_UNABLE_TO_LOAD_MEDIUM
4325 ERROR_UNABLE_TO_INVENTORY_DRIVE
4326 ERROR_UNABLE_TO_INVENTORY_SLOT
4327 ERROR_UNABLE_TO_INVENTORY_TRANSPORT
4328 ERROR_TRANSPORT_FULL
4329 ERROR_CONTROLLING_IEPORT
4330 ERROR_UNABLE_TO_EJECT_MOUNTED_MEDIA
4331 ERROR_CLEANER_SLOT_SET
4332 ERROR_CLEANER_SLOT_NOT_SET
4333 ERROR_CLEANER_CARTRIDGE_SPENT
4334 ERROR_UNEXPECTED_OMID
4335 ERROR_CANT_DELETE_LAST_ITEM
4336 ERROR_MESSAGE_EXCEEDS_MAX_SIZE
4337 ERROR_VOLUME_CONTAINS_SYS_FILES
4338 ERROR_INDIGENOUS_TYPE
4339 ERROR_NO_SUPPORTING_DRIVES
4340 ERROR_CLEANER_CARTRIDGE_INSTALLED
4341 ERROR_IEPORT_FULL
4350 ERROR_FILE_OFFLINE
4351 ERROR_REMOTE_STORAGE_NOT_ACTIVE
4352 ERROR_REMOTE_STORAGE_MEDIA_ERROR
4390 ERROR_NOT_A_REPARSE_POINT
4391 ERROR_REPARSE_ATTRIBUTE_CONFLICT
4392 ERROR_INVALID_REPARSE_DATA
4393 ERROR_REPARSE_TAG_INVALID
4394 ERROR_REPARSE_TAG_MISMATCH
4395 ERROR_REPARSE_POINT_ENCOUNTERED
4400 ERROR_APP_DATA_NOT_FOUND
4401 ERROR_APP_DATA_EXPIRED
4402 ERROR_APP_DATA_CORRUPT
4403 ERROR_APP_DATA_LIMIT_EXCEEDED
4404 ERROR_APP_DATA_REBOOT_REQUIRED
4420 ERROR_SECUREBOOT_ROLLBACK_DETECTED
4421 ERROR_SECUREBOOT_POLICY_VIOLATION
4422 ERROR_SECUREBOOT_INVALID_POLICY
4423 ERROR_SECUREBOOT_POLICY_PUBLISHER_NOT_FOUND
4424 ERROR_SECUREBOOT_POLICY_NOT_SIGNED
4425 ERROR_SECUREBOOT_NOT_ENABLED
4426 ERROR_SECUREBOOT_FILE_REPLACED
4427 ERROR_SECUREBOOT_POLICY_NOT_AUTHORIZED
4428 ERROR_SECUREBOOT_POLICY_UNKNOWN
4429 ERROR_SECUREBOOT_POLICY_MISSING_ANTIROLLBACKVERSION
4430 ERROR_SECUREBOOT_PLATFORM_ID_MISMATCH
4431 ERROR_SECUREBOOT_POLICY_ROLLBACK_DETECTED
4432 ERROR_SECUREBOOT_POLICY_UPGRADE_MISMATCH
4433 ERROR_SECUREBOOT_REQUIRED_POLICY_FILE_MISSING
4434 ERROR_SECUREBOOT_NOT_BASE_POLICY
4435 ERROR_SECUREBOOT_NOT_SUPPLEMENTAL_POLICY
4440 ERROR_OFFLOAD_READ_FLT_NOT_SUPPORTED
4441 ERROR_OFFLOAD_WRITE_FLT_NOT_SUPPORTED
4442 ERROR_OFFLOAD_READ_FILE_NOT_SUPPORTED
4443 ERROR_OFFLOAD_WRITE_FILE_NOT_SUPPORTED
4444 ERROR_ALREADY_HAS_STREAM_ID
4445 ERROR_SMR_GARBAGE_COLLECTION_REQUIRED
4500 ERROR_VOLUME_NOT_SIS_ENABLED
4550 ERROR_SYSTEM_INTEGRITY_ROLLBACK_DETECTED
4551 ERROR_SYSTEM_INTEGRITY_POLICY_VIOLATION
4552 ERROR_SYSTEM_INTEGRITY_INVALID_POLICY
4553 ERROR_SYSTEM_INTEGRITY_POLICY_NOT_SIGNED
4560 ERROR_VSM_NOT_INITIALIZED
4561 ERROR_VSM_DMA_PROTECTION_NOT_IN_USE
4570 ERROR_PLATFORM_MANIFEST_NOT_AUTHORIZED
4571 ERROR_PLATFORM_MANIFEST_INVALID
4572 ERROR_PLATFORM_MANIFEST_FILE_NOT_AUTHORIZED
4573 ERROR_PLATFORM_MANIFEST_CATALOG_NOT_AUTHORIZED
4574 ERROR_PLATFORM_MANIFEST_BINARY_ID_NOT_FOUND
4575 ERROR_PLATFORM_MANIFEST_NOT_ACTIVE
4576 ERROR_PLATFORM_MANIFEST_NOT_SIGNED
5001 ERROR_DEPENDENT_RESOURCE_EXISTS
5002 ERROR_DEPENDENCY_NOT_FOUND
5003 ERROR_DEPENDENCY_ALREADY_EXISTS
5004 ERROR_RESOURCE_NOT_ONLINE
5005 ERROR_HOST_NODE_NOT_AVAILABLE
5006 ERROR_RESOURCE_NOT_AVAILABLE
5007 ERROR_RESOURCE_NOT_FOUND
5008 ERROR_SHUTDOWN_CLUSTER
5009 ERROR_CANT_EVICT_ACTIVE_NODE
5010 ERROR_OBJECT_ALREADY_EXISTS
5011 ERROR_OBJECT_IN_LIST
5012 ERROR_GROUP_NOT_AVAILABLE
5013 ERROR_GROUP_NOT_FOUND
5014 ERROR_GROUP_NOT_ONLINE
5015 ERROR_HOST_NODE_NOT_RESOURCE_OWNER
5016 ERROR_HOST_NODE_NOT_GROUP_OWNER
5017 ERROR_RESMON_CREATE_FAILED
5018 ERROR_RESMON_ONLINE_FAILED
5019 ERROR_RESOURCE_ONLINE
5020 ERROR_QUORUM_RESOURCE
5021 ERROR_NOT_QUORUM_CAPABLE
5022 ERROR_CLUSTER_SHUTTING_DOWN
5023 ERROR_INVALID_STATE
5024 ERROR_RESOURCE_PROPERTIES_STORED
5025 ERROR_NOT_QUORUM_CLASS
5026 ERROR_CORE_RESOURCE
5027 ERROR_QUORUM_RESOURCE_ONLINE_FAILED
5028 ERROR_QUORUMLOG_OPEN_FAILED
5029 ERROR_CLUSTERLOG_CORRUPT
5030 ERROR_CLUSTERLOG_RECORD_EXCEEDS_MAXSIZE
5031 ERROR_CLUSTERLOG_EXCEEDS_MAXSIZE
5032 ERROR_CLUSTERLOG_CHKPOINT_NOT_FOUND
5033 ERROR_CLUSTERLOG_NOT_ENOUGH_SPACE
5034 ERROR_QUORUM_OWNER_ALIVE
5035 ERROR_NETWORK_NOT_AVAILABLE
5036 ERROR_NODE_NOT_AVAILABLE
5037 ERROR_ALL_NODES_NOT_AVAILABLE
5038 ERROR_RESOURCE_FAILED
5039 ERROR_CLUSTER_INVALID_NODE
5040 ERROR_CLUSTER_NODE_EXISTS
5041 ERROR_CLUSTER_JOIN_IN_PROGRESS
5042 ERROR_CLUSTER_NODE_NOT_FOUND
5043 ERROR_CLUSTER_LOCAL_NODE_NOT_FOUND
5044 ERROR_CLUSTER_NETWORK_EXISTS
5045 ERROR_CLUSTER_NETWORK_NOT_FOUND
5046 ERROR_CLUSTER_NETINTERFACE_EXISTS
5047 ERROR_CLUSTER_NETINTERFACE_NOT_FOUND
5048 ERROR_CLUSTER_INVALID_REQUEST
5049 ERROR_CLUSTER_INVALID_NETWORK_PROVIDER
5050 ERROR_CLUSTER_NODE_DOWN
5051 ERROR_CLUSTER_NODE_UNREACHABLE
5052 ERROR_CLUSTER_NODE_NOT_MEMBER
5053 ERROR_CLUSTER_JOIN_NOT_IN_PROGRESS
5054 ERROR_CLUSTER_INVALID_NETWORK
5056 ERROR_CLUSTER_NODE_UP
5057 ERROR_CLUSTER_IPADDR_IN_USE
5058 ERROR_CLUSTER_NODE_NOT_PAUSED
5059 ERROR_CLUSTER_NO_SECURITY_CONTEXT
5060 ERROR_CLUSTER_NETWORK_NOT_INTERNAL
5061 ERROR_CLUSTER_NODE_ALREADY_UP
5062 ERROR_CLUSTER_NODE_ALREADY_DOWN
5063 ERROR_CLUSTER_NETWORK_ALREADY_ONLINE
5064 ERROR_CLUSTER_NETWORK_ALREADY_OFFLINE
5065 ERROR_CLUSTER_NODE_ALREADY_MEMBER
5066 ERROR_CLUSTER_LAST_INTERNAL_NETWORK
5067 ERROR_CLUSTER_NETWORK_HAS_DEPENDENTS
5068 ERROR_INVALID_OPERATION_ON_QUORUM
5069 ERROR_DEPENDENCY_NOT_ALLOWED
5070 ERROR_CLUSTER_NODE_PAUSED
5071 ERROR_NODE_CANT_HOST_RESOURCE
5072 ERROR_CLUSTER_NODE_NOT_READY
5073 ERROR_CLUSTER_NODE_SHUTTING_DOWN
5074 ERROR_CLUSTER_JOIN_ABORTED
5075 ERROR_CLUSTER_INCOMPATIBLE_VERSIONS
5076 ERROR_CLUSTER_MAXNUM_OF_RESOURCES_EXCEEDED
5077 ERROR_CLUSTER_SYSTEM_CONFIG_CHANGED
5078 ERROR_CLUSTER_RESOURCE_TYPE_NOT_FOUND
5079 ERROR_CLUSTER_RESTYPE_NOT_SUPPORTED
5080 ERROR_CLUSTER_RESNAME_NOT_FOUND
5081 ERROR_CLUSTER_NO_RPC_PACKAGES_REGISTERED
5082 ERROR_CLUSTER_OWNER_NOT_IN_PREFLIST
5083 ERROR_CLUSTER_DATABASE_SEQMISMATCH
5084 ERROR_RESMON_INVALID_STATE
5085 ERROR_CLUSTER_GUM_NOT_LOCKER
5086 ERROR_QUORUM_DISK_NOT_FOUND
5087 ERROR_DATABASE_BACKUP_CORRUPT
5088 ERROR_CLUSTER_NODE_ALREADY_HAS_DFS_ROOT
5089 ERROR_RESOURCE_PROPERTY_UNCHANGEABLE
5090 ERROR_NO_ADMIN_ACCESS_POINT
5890 ERROR_CLUSTER_MEMBERSHIP_INVALID_STATE
5891 ERROR_CLUSTER_QUORUMLOG_NOT_FOUND
5892 ERROR_CLUSTER_MEMBERSHIP_HALT
5893 ERROR_CLUSTER_INSTANCE_ID_MISMATCH
5894 ERROR_CLUSTER_NETWORK_NOT_FOUND_FOR_IP
5895 ERROR_CLUSTER_PROPERTY_DATA_TYPE_MISMATCH
5896 ERROR_CLUSTER_EVICT_WITHOUT_CLEANUP
5897 ERROR_CLUSTER_PARAMETER_MISMATCH
5898 ERROR_NODE_CANNOT_BE_CLUSTERED
5899 ERROR_CLUSTER_WRONG_OS_VERSION
5900 ERROR_CLUSTER_CANT_CREATE_DUP_CLUSTER_NAME
5901 ERROR_CLUSCFG_ALREADY_COMMITTED
5902 ERROR_CLUSCFG_ROLLBACK_FAILED
5903 ERROR_CLUSCFG_SYSTEM_DISK_DRIVE_LETTER_CONFLICT
5904 ERROR_CLUSTER_OLD_VERSION
5905 ERROR_CLUSTER_MISMATCHED_COMPUTER_ACCT_NAME
5906 ERROR_CLUSTER_NO_NET_ADAPTERS
5907 ERROR_CLUSTER_POISONED
5908 ERROR_CLUSTER_GROUP_MOVING
5909 ERROR_CLUSTER_RESOURCE_TYPE_BUSY
5910 ERROR_RESOURCE_CALL_TIMED_OUT
5911 ERROR_INVALID_CLUSTER_IPV6_ADDRESS
5912 ERROR_CLUSTER_INTERNAL_INVALID_FUNCTION
5913 ERROR_CLUSTER_PARAMETER_OUT_OF_BOUNDS
5914 ERROR_CLUSTER_PARTIAL_SEND
5915 ERROR_CLUSTER_REGISTRY_INVALID_FUNCTION
5916 ERROR_CLUSTER_INVALID_STRING_TERMINATION
5917 ERROR_CLUSTER_INVALID_STRING_FORMAT
5918 ERROR_CLUSTER_DATABASE_TRANSACTION_IN_PROGRESS
5919 ERROR_CLUSTER_DATABASE_TRANSACTION_NOT_IN_PROGRESS
5920 ERROR_CLUSTER_NULL_DATA
5921 ERROR_CLUSTER_PARTIAL_READ
5922 ERROR_CLUSTER_PARTIAL_WRITE
5923 ERROR_CLUSTER_CANT_DESERIALIZE_DATA
5924 ERROR_DEPENDENT_RESOURCE_PROPERTY_CONFLICT
5925 ERROR_CLUSTER_NO_QUORUM
5926 ERROR_CLUSTER_INVALID_IPV6_NETWORK
5927 ERROR_CLUSTER_INVALID_IPV6_TUNNEL_NETWORK
5928 ERROR_QUORUM_NOT_ALLOWED_IN_THIS_GROUP
5929 ERROR_DEPENDENCY_TREE_TOO_COMPLEX
5930 ERROR_EXCEPTION_IN_RESOURCE_CALL
5931 ERROR_CLUSTER_RHS_FAILED_INITIALIZATION
5932 ERROR_CLUSTER_NOT_INSTALLED
5933 ERROR_CLUSTER_RESOURCES_MUST_BE_ONLINE_ON_THE_SAME_NODE
5934 ERROR_CLUSTER_MAX_NODES_IN_CLUSTER
5935 ERROR_CLUSTER_TOO_MANY_NODES
5936 ERROR_CLUSTER_OBJECT_ALREADY_USED
5937 ERROR_NONCORE_GROUPS_FOUND
5938 ERROR_FILE_SHARE_RESOURCE_CONFLICT
5939 ERROR_CLUSTER_EVICT_INVALID_REQUEST
5940 ERROR_CLUSTER_SINGLETON_RESOURCE
5941 ERROR_CLUSTER_GROUP_SINGLETON_RESOURCE
5942 ERROR_CLUSTER_RESOURCE_PROVIDER_FAILED
5943 ERROR_CLUSTER_RESOURCE_CONFIGURATION_ERROR
5944 ERROR_CLUSTER_GROUP_BUSY
5945 ERROR_CLUSTER_NOT_SHARED_VOLUME
5946 ERROR_CLUSTER_INVALID_SECURITY_DESCRIPTOR
5947 ERROR_CLUSTER_SHARED_VOLUMES_IN_USE
5948 ERROR_CLUSTER_USE_SHARED_VOLUMES_API
5949 ERROR_CLUSTER_BACKUP_IN_PROGRESS
5950 ERROR_NON_CSV_PATH
5951 ERROR_CSV_VOLUME_NOT_LOCAL
5952 ERROR_CLUSTER_WATCHDOG_TERMINATING
5953 ERROR_CLUSTER_RESOURCE_VETOED_MOVE_INCOMPATIBLE_NODES
5954 ERROR_CLUSTER_INVALID_NODE_WEIGHT
5955 ERROR_CLUSTER_RESOURCE_VETOED_CALL
5956 ERROR_RESMON_SYSTEM_RESOURCES_LACKING
5957 ERROR_CLUSTER_RESOURCE_VETOED_MOVE_NOT_ENOUGH_RESOURCES_ON_DESTINATION
5958 ERROR_CLUSTER_RESOURCE_VETOED_MOVE_NOT_ENOUGH_RESOURCES_ON_SOURCE
5959 ERROR_CLUSTER_GROUP_QUEUED
5960 ERROR_CLUSTER_RESOURCE_LOCKED_STATUS
5961 ERROR_CLUSTER_SHARED_VOLUME_FAILOVER_NOT_ALLOWED
5962 ERROR_CLUSTER_NODE_DRAIN_IN_PROGRESS
5963 ERROR_CLUSTER_DISK_NOT_CONNECTED
5964 ERROR_DISK_NOT_CSV_CAPABLE
5965 ERROR_RESOURCE_NOT_IN_AVAILABLE_STORAGE
5966 ERROR_CLUSTER_SHARED_VOLUME_REDIRECTED
5967 ERROR_CLUSTER_SHARED_VOLUME_NOT_REDIRECTED
5968 ERROR_CLUSTER_CANNOT_RETURN_PROPERTIES
5969 ERROR_CLUSTER_RESOURCE_CONTAINS_UNSUPPORTED_DIFF_AREA_FOR_SHARED_VOLUMES
5970 ERROR_CLUSTER_RESOURCE_IS_IN_MAINTENANCE_MODE
5971 ERROR_CLUSTER_AFFINITY_CONFLICT
5972 ERROR_CLUSTER_RESOURCE_IS_REPLICA_VIRTUAL_MACHINE
5973 ERROR_CLUSTER_UPGRADE_INCOMPATIBLE_VERSIONS
5974 ERROR_CLUSTER_UPGRADE_FIX_QUORUM_NOT_SUPPORTED
5975 ERROR_CLUSTER_UPGRADE_RESTART_REQUIRED
5976 ERROR_CLUSTER_UPGRADE_IN_PROGRESS
5977 ERROR_CLUSTER_UPGRADE_INCOMPLETE
5978 ERROR_CLUSTER_NODE_IN_GRACE_PERIOD
5979 ERROR_CLUSTER_CSV_IO_PAUSE_TIMEOUT
5980 ERROR_NODE_NOT_ACTIVE_CLUSTER_MEMBER
5981 ERROR_CLUSTER_RESOURCE_NOT_MONITORED
5982 ERROR_CLUSTER_RESOURCE_DOES_NOT_SUPPORT_UNMONITORED
5983 ERROR_CLUSTER_RESOURCE_IS_REPLICATED
5984 ERROR_CLUSTER_NODE_ISOLATED
5985 ERROR_CLUSTER_NODE_QUARANTINED
5986 ERROR_CLUSTER_DATABASE_UPDATE_CONDITION_FAILED
5987 ERROR_CLUSTER_SPACE_DEGRADED
5988 ERROR_CLUSTER_TOKEN_DELEGATION_NOT_SUPPORTED
5989 ERROR_CLUSTER_CSV_INVALID_HANDLE
5990 ERROR_CLUSTER_CSV_SUPPORTED_ONLY_ON_COORDINATOR
5991 ERROR_GROUPSET_NOT_AVAILABLE
5992 ERROR_GROUPSET_NOT_FOUND
5993 ERROR_GROUPSET_CANT_PROVIDE
5994 ERROR_CLUSTER_FAULT_DOMAIN_PARENT_NOT_FOUND
5995 ERROR_CLUSTER_FAULT_DOMAIN_INVALID_HIERARCHY
5996 ERROR_CLUSTER_FAULT_DOMAIN_FAILED_S2D_VALIDATION
5997 ERROR_CLUSTER_FAULT_DOMAIN_S2D_CONNECTIVITY_LOSS
5998 ERROR_CLUSTER_INVALID_INFRASTRUCTURE_FILESERVER_NAME
5999 ERROR_CLUSTERSET_MANAGEMENT_CLUSTER_UNREACHABLE
6000 ERROR_ENCRYPTION_FAILED
6001 ERROR_DECRYPTION_FAILED
6002 ERROR_FILE_ENCRYPTED
6003 ERROR_NO_RECOVERY_POLICY
6004 ERROR_NO_EFS
6005 ERROR_WRONG_EFS
6006 ERROR_NO_USER_KEYS
6007 ERROR_FILE_NOT_ENCRYPTED
6008 ERROR_NOT_EXPORT_FORMAT
6009 ERROR_FILE_READ_ONLY
6010 ERROR_DIR_EFS_DISALLOWED
6011 ERROR_EFS_SERVER_NOT_TRUSTED
6012 ERROR_BAD_RECOVERY_POLICY
6013 ERROR_EFS_ALG_BLOB_TOO_BIG
6014 ERROR_VOLUME_NOT_SUPPORT_EFS
6015 ERROR_EFS_DISABLED
6016 ERROR_EFS_VERSION_NOT_SUPPORT
6017 ERROR_CS_ENCRYPTION_INVALID_SERVER_RESPONSE
6018 ERROR_CS_ENCRYPTION_UNSUPPORTED_SERVER
6019 ERROR_CS_ENCRYPTION_EXISTING_ENCRYPTED_FILE
6020 ERROR_CS_ENCRYPTION_NEW_ENCRYPTED_FILE
6021 ERROR_CS_ENCRYPTION_FILE_NOT_CSE
6022 ERROR_ENCRYPTION_POLICY_DENIES_OPERATION
6118 ERROR_NO_BROWSER_SERVERS_FOUND
6200 SCHED_E_SERVICE_NOT_LOCALSYSTEM
6600 ERROR_LOG_SECTOR_INVALID
6601 ERROR_LOG_SECTOR_PARITY_INVALID
6602 ERROR_LOG_SECTOR_REMAPPED
6603 ERROR_LOG_BLOCK_INCOMPLETE
6604 ERROR_LOG_INVALID_RANGE
6605 ERROR_LOG_BLOCKS_EXHAUSTED
6606 ERROR_LOG_READ_CONTEXT_INVALID
6607 ERROR_LOG_RESTART_INVALID
6608 ERROR_LOG_BLOCK_VERSION
6609 ERROR_LOG_BLOCK_INVALID
6610 ERROR_LOG_READ_MODE_INVALID
6611 ERROR_LOG_NO_RESTART
6612 ERROR_LOG_METADATA_CORRUPT
6613 ERROR_LOG_METADATA_INVALID
6614 ERROR_LOG_METADATA_INCONSISTENT
6615 ERROR_LOG_RESERVATION_INVALID
6616 ERROR_LOG_CANT_DELETE
6617 ERROR_LOG_CONTAINER_LIMIT_EXCEEDED
6618 ERROR_LOG_START_OF_LOG
6619 ERROR_LOG_POLICY_ALREADY_INSTALLED
6620 ERROR_LOG_POLICY_NOT_INSTALLED
6621 ERROR_LOG_POLICY_INVALID
6622 ERROR_LOG_POLICY_CONFLICT
6623 ERROR_LOG_PINNED_ARCHIVE_TAIL
6624 ERROR_LOG_RECORD_NONEXISTENT
6625 ERROR_LOG_RECORDS_RESERVED_INVALID
6626 ERROR_LOG_SPACE_RESERVED_INVALID
6627 ERROR_LOG_TAIL_INVALID
6628 ERROR_LOG_FULL
6629 ERROR_COULD_NOT_RESIZE_LOG
6630 ERROR_LOG_MULTIPLEXED
6631 ERROR_LOG_DEDICATED
6632 ERROR_LOG_ARCHIVE_NOT_IN_PROGRESS
6633 ERROR_LOG_ARCHIVE_IN_PROGRESS
6634 ERROR_LOG_EPHEMERAL
6635 ERROR_LOG_NOT_ENOUGH_CONTAINERS
6636 ERROR_LOG_CLIENT_ALREADY_REGISTERED
6637 ERROR_LOG_CLIENT_NOT_REGISTERED
6638 ERROR_LOG_FULL_HANDLER_IN_PROGRESS
6639 ERROR_LOG_CONTAINER_READ_FAILED
6640 ERROR_LOG_CONTAINER_WRITE_FAILED
6641 ERROR_LOG_CONTAINER_OPEN_FAILED
6642 ERROR_LOG_CONTAINER_STATE_INVALID
6643 ERROR_LOG_STATE_INVALID
6644 ERROR_LOG_PINNED
6645 ERROR_LOG_METADATA_FLUSH_FAILED
6646 ERROR_LOG_INCONSISTENT_SECURITY
6647 ERROR_LOG_APPENDED_FLUSH_FAILED
6648 ERROR_LOG_PINNED_RESERVATION
6700 ERROR_INVALID_TRANSACTION
6701 ERROR_TRANSACTION_NOT_ACTIVE
6702 ERROR_TRANSACTION_REQUEST_NOT_VALID
6703 ERROR_TRANSACTION_NOT_REQUESTED
6704 ERROR_TRANSACTION_ALREADY_ABORTED
6705 ERROR_TRANSACTION_ALREADY_COMMITTED
6706 ERROR_TM_INITIALIZATION_FAILED
6707 ERROR_RESOURCEMANAGER_READ_ONLY
6708 ERROR_TRANSACTION_NOT_JOINED
6709 ERROR_TRANSACTION_SUPERIOR_EXISTS
6710 ERROR_CRM_PROTOCOL_ALREADY_EXISTS
6711 ERROR_TRANSACTION_PROPAGATION_FAILED
6712 ERROR_CRM_PROTOCOL_NOT_FOUND
6713 ERROR_TRANSACTION_INVALID_MARSHALL_BUFFER
6714 ERROR_CURRENT_TRANSACTION_NOT_VALID
6715 ERROR_TRANSACTION_NOT_FOUND
6716 ERROR_RESOURCEMANAGER_NOT_FOUND
6717 ERROR_ENLISTMENT_NOT_FOUND
6718 ERROR_TRANSACTIONMANAGER_NOT_FOUND
6719 ERROR_TRANSACTIONMANAGER_NOT_ONLINE
6720 ERROR_TRANSACTIONMANAGER_RECOVERY_NAME_COLLISION
6721 ERROR_TRANSACTION_NOT_ROOT
6722 ERROR_TRANSACTION_OBJECT_EXPIRED
6723 ERROR_TRANSACTION_RESPONSE_NOT_ENLISTED
6724 ERROR_TRANSACTION_RECORD_TOO_LONG
6725 ERROR_IMPLICIT_TRANSACTION_NOT_SUPPORTED
6726 ERROR_TRANSACTION_INTEGRITY_VIOLATED
6727 ERROR_TRANSACTIONMANAGER_IDENTITY_MISMATCH
6728 ERROR_RM_CANNOT_BE_FROZEN_FOR_SNAPSHOT
6729 ERROR_TRANSACTION_MUST_WRITETHROUGH
6730 ERROR_TRANSACTION_NO_SUPERIOR
6731 ERROR_HEURISTIC_DAMAGE_POSSIBLE
6800 ERROR_TRANSACTIONAL_CONFLICT
6801 ERROR_RM_NOT_ACTIVE
6802 ERROR_RM_METADATA_CORRUPT
6803 ERROR_DIRECTORY_NOT_RM
6805 ERROR_TRANSACTIONS_UNSUPPORTED_REMOTE
6806 ERROR_LOG_RESIZE_INVALID_SIZE
6807 ERROR_OBJECT_NO_LONGER_EXISTS
6808 ERROR_STREAM_MINIVERSION_NOT_FOUND
6809 ERROR_STREAM_MINIVERSION_NOT_VALID
6810 ERROR_MINIVERSION_INACCESSIBLE_FROM_SPECIFIED_TRANSACTION
6811 ERROR_CANT_OPEN_MINIVERSION_WITH_MODIFY_INTENT
6812 ERROR_CANT_CREATE_MORE_STREAM_MINIVERSIONS
6814 ERROR_REMOTE_FILE_VERSION_MISMATCH
6815 ERROR_HANDLE_NO_LONGER_VALID
6816 ERROR_NO_TXF_METADATA
6817 ERROR_LOG_CORRUPTION_DETECTED
6818 ERROR_CANT_RECOVER_WITH_HANDLE_OPEN
6819 ERROR_RM_DISCONNECTED
6820 ERROR_ENLISTMENT_NOT_SUPERIOR
6821 ERROR_RECOVERY_NOT_NEEDED
6822 ERROR_RM_ALREADY_STARTED
6823 ERROR_FILE_IDENTITY_NOT_PERSISTENT
6824 ERROR_CANT_BREAK_TRANSACTIONAL_DEPENDENCY
6825 ERROR_CANT_CROSS_RM_BOUNDARY
6826 ERROR_TXF_DIR_NOT_EMPTY
6827 ERROR_INDOUBT_TRANSACTIONS_EXIST
6828 ERROR_TM_VOLATILE
6829 ERROR_ROLLBACK_TIMER_EXPIRED
6830 ERROR_TXF_ATTRIBUTE_CORRUPT
6831 ERROR_EFS_NOT_ALLOWED_IN_TRANSACTION
6832 ERROR_TRANSACTIONAL_OPEN_NOT_ALLOWED
6833 ERROR_LOG_GROWTH_FAILED
6834 ERROR_TRANSACTED_MAPPING_UNSUPPORTED_REMOTE
6835 ERROR_TXF_METADATA_ALREADY_PRESENT
6836 ERROR_TRANSACTION_SCOPE_CALLBACKS_NOT_SET
6837 ERROR_TRANSACTION_REQUIRED_PROMOTION
6838 ERROR_CANNOT_EXECUTE_FILE_IN_TRANSACTION
6839 ERROR_TRANSACTIONS_NOT_FROZEN
6840 ERROR_TRANSACTION_FREEZE_IN_PROGRESS
6841 ERROR_NOT_SNAPSHOT_VOLUME
6842 ERROR_NO_SAVEPOINT_WITH_OPEN_FILES
6843 ERROR_DATA_LOST_REPAIR
6844 ERROR_SPARSE_NOT_ALLOWED_IN_TRANSACTION
6845 ERROR_TM_IDENTITY_MISMATCH
6846 ERROR_FLOATED_SECTION
6847 ERROR_CANNOT_ACCEPT_TRANSACTED_WORK
6848 ERROR_CANNOT_ABORT_TRANSACTIONS
6849 ERROR_BAD_CLUSTERS
6850 ERROR_COMPRESSION_NOT_ALLOWED_IN_TRANSACTION
6851 ERROR_VOLUME_DIRTY
6852 ERROR_NO_LINK_TRACKING_IN_TRANSACTION
6853 ERROR_OPERATION_NOT_SUPPORTED_IN_TRANSACTION
6854 ERROR_EXPIRED_HANDLE
6855 ERROR_TRANSACTION_NOT_ENLISTED
7001 ERROR_CTX_WINSTATION_NAME_INVALID
7002 ERROR_CTX_INVALID_PD
7003 ERROR_CTX_PD_NOT_FOUND
7004 ERROR_CTX_WD_NOT_FOUND
7005 ERROR_CTX_CANNOT_MAKE_EVENTLOG_ENTRY
7006 ERROR_CTX_SERVICE_NAME_COLLISION
7007 ERROR_CTX_CLOSE_PENDING
7008 ERROR_CTX_NO_OUTBUF
7009 ERROR_CTX_MODEM_INF_NOT_FOUND
7010 ERROR_CTX_INVALID_MODEMNAME
7011 ERROR_CTX_MODEM_RESPONSE_ERROR
7012 ERROR_CTX_MODEM_RESPONSE_TIMEOUT
7013 ERROR_CTX_MODEM_RESPONSE_NO_CARRIER
7014 ERROR_CTX_MODEM_RESPONSE_NO_DIALTONE
7015 ERROR_CTX_MODEM_RESPONSE_BUSY
7016 ERROR_CTX_MODEM_RESPONSE_VOICE
7017 ERROR_CTX_TD_ERROR
7022 ERROR_CTX_WINSTATION_NOT_FOUND
7023 ERROR_CTX_WINSTATION_ALREADY_EXISTS
7024 ERROR_CTX_WINSTATION_BUSY
7025 ERROR_CTX_BAD_VIDEO_MODE
7035 ERROR_CTX_GRAPHICS_INVALID
7037 ERROR_CTX_LOGON_DISABLED
7038 ERROR_CTX_NOT_CONSOLE
7040 ERROR_CTX_CLIENT_QUERY_TIMEOUT
7041 ERROR_CTX_CONSOLE_DISCONNECT
7042 ERROR_CTX_CONSOLE_CONNECT
7044 ERROR_CTX_SHADOW_DENIED
7045 ERROR_CTX_WINSTATION_ACCESS_DENIED
7049 ERROR_CTX_INVALID_WD
7050 ERROR_CTX_SHADOW_INVALID
7051 ERROR_CTX_SHADOW_DISABLED
7052 ERROR_CTX_CLIENT_LICENSE_IN_USE
7053 ERROR_CTX_CLIENT_LICENSE_NOT_SET
7054 ERROR_CTX_LICENSE_NOT_AVAILABLE
7055 ERROR_CTX_LICENSE_CLIENT_INVALID
7056 ERROR_CTX_LICENSE_EXPIRED
7057 ERROR_CTX_SHADOW_NOT_RUNNING
7058 ERROR_CTX_SHADOW_ENDED_BY_MODE_CHANGE
7059 ERROR_ACTIVATION_COUNT_EXCEEDED
7060 ERROR_CTX_WINSTATIONS_DISABLED
7061 ERROR_CTX_ENCRYPTION_LEVEL_REQUIRED
7062 ERROR_CTX_SESSION_IN_USE
7063 ERROR_CTX_NO_FORCE_LOGOFF
7064 ERROR_CTX_ACCOUNT_RESTRICTION
7065 ERROR_RDP_PROTOCOL_ERROR
7066 ERROR_CTX_CDM_CONNECT
7067 ERROR_CTX_CDM_DISCONNECT
7068 ERROR_CTX_SECURITY_LAYER_ERROR
7069 ERROR_TS_INCOMPATIBLE_SESSIONS
7070 ERROR_TS_VIDEO_SUBSYSTEM_ERROR
8001 FRS_ERR_INVALID_API_SEQUENCE
8002 FRS_ERR_STARTING_SERVICE
8003 FRS_ERR_STOPPING_SERVICE
8004 FRS_ERR_INTERNAL_API
8005 FRS_ERR_INTERNAL
8006 FRS_ERR_SERVICE_COMM
8007 FRS_ERR_INSUFFICIENT_PRIV
8008 FRS_ERR_AUTHENTICATION
8009 FRS_ERR_PARENT_INSUFFICIENT_PRIV
8010 FRS_ERR_PARENT_AUTHENTICATION
8011 FRS_ERR_CHILD_TO_PARENT_COMM
8012 FRS_ERR_PARENT_TO_CHILD_COMM
8013 FRS_ERR_SYSVOL_POPULATE
8014 FRS_ERR_SYSVOL_POPULATE_TIMEOUT
8015 FRS_ERR_SYSVOL_IS_BUSY
8016 FRS_ERR_SYSVOL_DEMOTE
8017 FRS_ERR_INVALID_SERVICE_PARAMETER
8200 ERROR_DS_NOT_INSTALLED
8201 ERROR_DS_MEMBERSHIP_EVALUATED_LOCALLY
8202 ERROR_DS_NO_ATTRIBUTE_OR_VALUE
8203 ERROR_DS_INVALID_ATTRIBUTE_SYNTAX
8204 ERROR_DS_ATTRIBUTE_TYPE_UNDEFINED
8205 ERROR_DS_ATTRIBUTE_OR_VALUE_EXISTS
8206 ERROR_DS_BUSY
8207 ERROR_DS_UNAVAILABLE
8208 ERROR_DS_NO_RIDS_ALLOCATED
8209 ERROR_DS_NO_MORE_RIDS
8210 ERROR_DS_INCORRECT_ROLE_OWNER
8211 ERROR_DS_RIDMGR_INIT_ERROR
8212 ERROR_DS_OBJ_CLASS_VIOLATION
8213 ERROR_DS_CANT_ON_NON_LEAF
8214 ERROR_DS_CANT_ON_RDN
8215 ERROR_DS_CANT_MOD_OBJ_CLASS
8216 ERROR_DS_CROSS_DOM_MOVE_ERROR
8217 ERROR_DS_GC_NOT_AVAILABLE
8218 ERROR_SHARED_POLICY
8219 ERROR_POLICY_OBJECT_NOT_FOUND
8220 ERROR_POLICY_ONLY_IN_DS
8221 ERROR_PROMOTION_ACTIVE
8222 ERROR_NO_PROMOTION_ACTIVE
8224 ERROR_DS_OPERATIONS_ERROR
8225 ERROR_DS_PROTOCOL_ERROR
8226 ERROR_DS_TIMELIMIT_EXCEEDED
8227 ERROR_DS_SIZELIMIT_EXCEEDED
8228 ERROR_DS_ADMIN_LIMIT_EXCEEDED
8229 ERROR_DS_COMPARE_FALSE
8230 ERROR_DS_COMPARE_TRUE
8231 ERROR_DS_AUTH_METHOD_NOT_SUPPORTED
8232 ERROR_DS_STRONG_AUTH_REQUIRED
8233 ERROR_DS_INAPPROPRIATE_AUTH
8234 ERROR_DS_AUTH_UNKNOWN
8235 ERROR_DS_REFERRAL
8236 ERROR_DS_UNAVAILABLE_CRIT_EXTENSION
8237 ERROR_DS_CONFIDENTIALITY_REQUIRED
8238 ERROR_DS_INAPPROPRIATE_MATCHING
8239 ERROR_DS_CONSTRAINT_VIOLATION
8240 ERROR_DS_NO_SUCH_OBJECT
8241 ERROR_DS_ALIAS_PROBLEM
8242 ERROR_DS_INVALID_DN_SYNTAX
8243 ERROR_DS_IS_LEAF
8244 ERROR_DS_ALIAS_DEREF_PROBLEM
8245 ERROR_DS_UNWILLING_TO_PERFORM
8246 ERROR_DS_LOOP_DETECT
8247 ERROR_DS_NAMING_VIOLATION
8248 ERROR_DS_OBJECT_RESULTS_TOO_LARGE
8249 ERROR_DS_AFFECTS_MULTIPLE_DSAS
8250 ERROR_DS_SERVER_DOWN
8251 ERROR_DS_LOCAL_ERROR
8252 ERROR_DS_ENCODING_ERROR
8253 ERROR_DS_DECODING_ERROR
8254 ERROR_DS_FILTER_UNKNOWN
8255 ERROR_DS_PARAM_ERROR
8256 ERROR_DS_NOT_SUPPORTED
8257 ERROR_DS_NO_RESULTS_RETURNED
8258 ERROR_DS_CONTROL_NOT_FOUND
8259 ERROR_DS_CLIENT_LOOP
8260 ERROR_DS_REFERRAL_LIMIT_EXCEEDED
8261 ERROR_DS_SORT_CONTROL_MISSING
8262 ERROR_DS_OFFSET_RANGE_ERROR
8263 ERROR_DS_RIDMGR_DISABLED
8301 ERROR_DS_ROOT_MUST_BE_NC
8302 ERROR_DS_ADD_REPLICA_INHIBITED
8303 ERROR_DS_ATT_NOT_DEF_IN_SCHEMA
8304 ERROR_DS_MAX_OBJ_SIZE_EXCEEDED
8305 ERROR_DS_OBJ_STRING_NAME_EXISTS
8306 ERROR_DS_NO_RDN_DEFINED_IN_SCHEMA
8307 ERROR_DS_RDN_DOESNT_MATCH_SCHEMA
8308 ERROR_DS_NO_REQUESTED_ATTS_FOUND
8309 ERROR_DS_USER_BUFFER_TO_SMALL
8310 ERROR_DS_ATT_IS_NOT_ON_OBJ
8311 ERROR_DS_ILLEGAL_MOD_OPERATION
8312 ERROR_DS_OBJ_TOO_LARGE
8313 ERROR_DS_BAD_INSTANCE_TYPE
8314 ERROR_DS_MASTERDSA_REQUIRED
8315 ERROR_DS_OBJECT_CLASS_REQUIRED
8316 ERROR_DS_MISSING_REQUIRED_ATT
8317 ERROR_DS_ATT_NOT_DEF_FOR_CLASS
8318 ERROR_DS_ATT_ALREADY_EXISTS
8320 ERROR_DS_CANT_ADD_ATT_VALUES
8321 ERROR_DS_SINGLE_VALUE_CONSTRAINT
8322 ERROR_DS_RANGE_CONSTRAINT
8323 ERROR_DS_ATT_VAL_ALREADY_EXISTS
8324 ERROR_DS_CANT_REM_MISSING_ATT
8325 ERROR_DS_CANT_REM_MISSING_ATT_VAL
8326 ERROR_DS_ROOT_CANT_BE_SUBREF
8327 ERROR_DS_NO_CHAINING
8328 ERROR_DS_NO_CHAINED_EVAL
8329 ERROR_DS_NO_PARENT_OBJECT
8330 ERROR_DS_PARENT_IS_AN_ALIAS
8331 ERROR_DS_CANT_MIX_MASTER_AND_REPS
8332 ERROR_DS_CHILDREN_EXIST
8333 ERROR_DS_OBJ_NOT_FOUND
8334 ERROR_DS_ALIASED_OBJ_MISSING
8335 ERROR_DS_BAD_NAME_SYNTAX
8336 ERROR_DS_ALIAS_POINTS_TO_ALIAS
8337 ERROR_DS_CANT_DEREF_ALIAS
8338 ERROR_DS_OUT_OF_SCOPE
8339 ERROR_DS_OBJECT_BEING_REMOVED
8340 ERROR_DS_CANT_DELETE_DSA_OBJ
8341 ERROR_DS_GENERIC_ERROR
8342 ERROR_DS_DSA_MUST_BE_INT_MASTER
8343 ERROR_DS_CLASS_NOT_DSA
8344 ERROR_DS_INSUFF_ACCESS_RIGHTS
8345 ERROR_DS_ILLEGAL_SUPERIOR
8346 ERROR_DS_ATTRIBUTE_OWNED_BY_SAM
8347 ERROR_DS_NAME_TOO_MANY_PARTS
8348 ERROR_DS_NAME_TOO_LONG
8349 ERROR_DS_NAME_VALUE_TOO_LONG
8350 ERROR_DS_NAME_UNPARSEABLE
8351 ERROR_DS_NAME_TYPE_UNKNOWN
8352 ERROR_DS_NOT_AN_OBJECT
8353 ERROR_DS_SEC_DESC_TOO_SHORT
8354 ERROR_DS_SEC_DESC_INVALID
8355 ERROR_DS_NO_DELETED_NAME
8356 ERROR_DS_SUBREF_MUST_HAVE_PARENT
8357 ERROR_DS_NCNAME_MUST_BE_NC
8358 ERROR_DS_CANT_ADD_SYSTEM_ONLY
8359 ERROR_DS_CLASS_MUST_BE_CONCRETE
8360 ERROR_DS_INVALID_DMD
8361 ERROR_DS_OBJ_GUID_EXISTS
8362 ERROR_DS_NOT_ON_BACKLINK
8363 ERROR_DS_NO_CROSSREF_FOR_NC
8364 ERROR_DS_SHUTTING_DOWN
8365 ERROR_DS_UNKNOWN_OPERATION
8366 ERROR_DS_INVALID_ROLE_OWNER
8367 ERROR_DS_COULDNT_CONTACT_FSMO
8368 ERROR_DS_CROSS_NC_DN_RENAME
8369 ERROR_DS_CANT_MOD_SYSTEM_ONLY
8370 ERROR_DS_REPLICATOR_ONLY
8371 ERROR_DS_OBJ_CLASS_NOT_DEFINED
8372 ERROR_DS_OBJ_CLASS_NOT_SUBCLASS
8373 ERROR_DS_NAME_REFERENCE_INVALID
8374 ERROR_DS_CROSS_REF_EXISTS
8375 ERROR_DS_CANT_DEL_MASTER_CROSSREF
8376 ERROR_DS_SUBTREE_NOTIFY_NOT_NC_HEAD
8377 ERROR_DS_NOTIFY_FILTER_TOO_COMPLEX
8378 ERROR_DS_DUP_RDN
8379 ERROR_DS_DUP_OID
8380 ERROR_DS_DUP_MAPI_ID
8381 ERROR_DS_DUP_SCHEMA_ID_GUID
8382 ERROR_DS_DUP_LDAP_DISPLAY_NAME
8383 ERROR_DS_SEMANTIC_ATT_TEST
8384 ERROR_DS_SYNTAX_MISMATCH
8385 ERROR_DS_EXISTS_IN_MUST_HAVE
8386 ERROR_DS_EXISTS_IN_MAY_HAVE
8387 ERROR_DS_NONEXISTENT_MAY_HAVE
8388 ERROR_DS_NONEXISTENT_MUST_HAVE
8389 ERROR_DS_AUX_CLS_TEST_FAIL
8390 ERROR_DS_NONEXISTENT_POSS_SUP
8391 ERROR_DS_SUB_CLS_TEST_FAIL
8392 ERROR_DS_BAD_RDN_ATT_ID_SYNTAX
8393 ERROR_DS_EXISTS_IN_AUX_CLS
8394 ERROR_DS_EXISTS_IN_SUB_CLS
8395 ERROR_DS_EXISTS_IN_POSS_SUP
8396 ERROR_DS_RECALCSCHEMA_FAILED
8397 ERROR_DS_TREE_DELETE_NOT_FINISHED
8398 ERROR_DS_CANT_DELETE
8399 ERROR_DS_ATT_SCHEMA_REQ_ID
8400 ERROR_DS_BAD_ATT_SCHEMA_SYNTAX
8401 ERROR_DS_CANT_CACHE_ATT
8402 ERROR_DS_CANT_CACHE_CLASS
8403 ERROR_DS_CANT_REMOVE_ATT_CACHE
8404 ERROR_DS_CANT_REMOVE_CLASS_CACHE
8405 ERROR_DS_CANT_RETRIEVE_DN
8406 ERROR_DS_MISSING_SUPREF
8407 ERROR_DS_CANT_RETRIEVE_INSTANCE
8408 ERROR_DS_CODE_INCONSISTENCY
8409 ERROR_DS_DATABASE_ERROR
8410 ERROR_DS_GOVERNSID_MISSING
8411 ERROR_DS_MISSING_EXPECTED_ATT
8412 ERROR_DS_NCNAME_MISSING_CR_REF
8413 ERROR_DS_SECURITY_CHECKING_ERROR
8414 ERROR_DS_SCHEMA_NOT_LOADED
8415 ERROR_DS_SCHEMA_ALLOC_FAILED
8416 ERROR_DS_ATT_SCHEMA_REQ_SYNTAX
8417 ERROR_DS_GCVERIFY_ERROR
8418 ERROR_DS_DRA_SCHEMA_MISMATCH
8419 ERROR_DS_CANT_FIND_DSA_OBJ
8420 ERROR_DS_CANT_FIND_EXPECTED_NC
8421 ERROR_DS_CANT_FIND_NC_IN_CACHE
8422 ERROR_DS_CANT_RETRIEVE_CHILD
8423 ERROR_DS_SECURITY_ILLEGAL_MODIFY
8424 ERROR_DS_CANT_REPLACE_HIDDEN_REC
8425 ERROR_DS_BAD_HIERARCHY_FILE
8426 ERROR_DS_BUILD_HIERARCHY_TABLE_FAILED
8427 ERROR_DS_CONFIG_PARAM_MISSING
8428 ERROR_DS_COUNTING_AB_INDICES_FAILED
8429 ERROR_DS_HIERARCHY_TABLE_MALLOC_FAILED
8430 ERROR_DS_INTERNAL_FAILURE
8431 ERROR_DS_UNKNOWN_ERROR
8432 ERROR_DS_ROOT_REQUIRES_CLASS_TOP
8433 ERROR_DS_REFUSING_FSMO_ROLES
8434 ERROR_DS_MISSING_FSMO_SETTINGS
8435 ERROR_DS_UNABLE_TO_SURRENDER_ROLES
8436 ERROR_DS_DRA_GENERIC
8437 ERROR_DS_DRA_INVALID_PARAMETER
8438 ERROR_DS_DRA_BUSY
8439 ERROR_DS_DRA_BAD_DN
8440 ERROR_DS_DRA_BAD_NC
8441 ERROR_DS_DRA_DN_EXISTS
8442 ERROR_DS_DRA_INTERNAL_ERROR
8443 ERROR_DS_DRA_INCONSISTENT_DIT
8444 ERROR_DS_DRA_CONNECTION_FAILED
8445 ERROR_DS_DRA_BAD_INSTANCE_TYPE
8446 ERROR_DS_DRA_OUT_OF_MEM
8447 ERROR_DS_DRA_MAIL_PROBLEM
8448 ERROR_DS_DRA_REF_ALREADY_EXISTS
8449 ERROR_DS_DRA_REF_NOT_FOUND
8450 ERROR_DS_DRA_OBJ_IS_REP_SOURCE
8451 ERROR_DS_DRA_DB_ERROR
8452 ERROR_DS_DRA_NO_REPLICA
8453 ERROR_DS_DRA_ACCESS_DENIED
8454 ERROR_DS_DRA_NOT_SUPPORTED
8455 ERROR_DS_DRA_RPC_CANCELLED
8456 ERROR_DS_DRA_SOURCE_DISABLED
8457 ERROR_DS_DRA_SINK_DISABLED
8458 ERROR_DS_DRA_NAME_COLLISION
8459 ERROR_DS_DRA_SOURCE_REINSTALLED
8460 ERROR_DS_DRA_MISSING_PARENT
8461 ERROR_DS_DRA_PREEMPTED
8462 ERROR_DS_DRA_ABANDON_SYNC
8463 ERROR_DS_DRA_SHUTDOWN
8464 ERROR_DS_DRA_INCOMPATIBLE_PARTIAL_SET
8465 ERROR_DS_DRA_SOURCE_IS_PARTIAL_REPLICA
8466 ERROR_DS_DRA_EXTN_CONNECTION_FAILED
8467 ERROR_DS_INSTALL_SCHEMA_MISMATCH
8468 ERROR_DS_DUP_LINK_ID
8469 ERROR_DS_NAME_ERROR_RESOLVING
8470 ERROR_DS_NAME_ERROR_NOT_FOUND
8471 ERROR_DS_NAME_ERROR_NOT_UNIQUE
8472 ERROR_DS_NAME_ERROR_NO_MAPPING
8473 ERROR_DS_NAME_ERROR_DOMAIN_ONLY
8474 ERROR_DS_NAME_ERROR_NO_SYNTACTICAL_MAPPING
8475 ERROR_DS_CONSTRUCTED_ATT_MOD
8476 ERROR_DS_WRONG_OM_OBJ_CLASS
8477 ERROR_DS_DRA_REPL_PENDING
8478 ERROR_DS_DS_REQUIRED
8479 ERROR_DS_INVALID_LDAP_DISPLAY_NAME
8480 ERROR_DS_NON_BASE_SEARCH
8481 ERROR_DS_CANT_RETRIEVE_ATTS
8482 ERROR_DS_BACKLINK_WITHOUT_LINK
8483 ERROR_DS_EPOCH_MISMATCH
8484 ERROR_DS_SRC_NAME_MISMATCH
8485 ERROR_DS_SRC_AND_DST_NC_IDENTICAL
8486 ERROR_DS_DST_NC_MISMATCH
8487 ERROR_DS_NOT_AUTHORITIVE_FOR_DST_NC
8488 ERROR_DS_SRC_GUID_MISMATCH
8489 ERROR_DS_CANT_MOVE_DELETED_OBJECT
8490 ERROR_DS_PDC_OPERATION_IN_PROGRESS
8491 ERROR_DS_CROSS_DOMAIN_CLEANUP_REQD
8492 ERROR_DS_ILLEGAL_XDOM_MOVE_OPERATION
8493 ERROR_DS_CANT_WITH_ACCT_GROUP_MEMBERSHPS
8494 ERROR_DS_NC_MUST_HAVE_NC_PARENT
8495 ERROR_DS_CR_IMPOSSIBLE_TO_VALIDATE
8496 ERROR_DS_DST_DOMAIN_NOT_NATIVE
8497 ERROR_DS_MISSING_INFRASTRUCTURE_CONTAINER
8498 ERROR_DS_CANT_MOVE_ACCOUNT_GROUP
8499 ERROR_DS_CANT_MOVE_RESOURCE_GROUP
8500 ERROR_DS_INVALID_SEARCH_FLAG
8501 ERROR_DS_NO_TREE_DELETE_ABOVE_NC
8502 ERROR_DS_COULDNT_LOCK_TREE_FOR_DELETE
8503 ERROR_DS_COULDNT_IDENTIFY_OBJECTS_FOR_TREE_DELETE
8504 ERROR_DS_SAM_INIT_FAILURE
8505 ERROR_DS_SENSITIVE_GROUP_VIOLATION
8506 ERROR_DS_CANT_MOD_PRIMARYGROUPID
8507 ERROR_DS_ILLEGAL_BASE_SCHEMA_MOD
8508 ERROR_DS_NONSAFE_SCHEMA_CHANGE
8509 ERROR_DS_SCHEMA_UPDATE_DISALLOWED
8510 ERROR_DS_CANT_CREATE_UNDER_SCHEMA
8511 ERROR_DS_INSTALL_NO_SRC_SCH_VERSION
8512 ERROR_DS_INSTALL_NO_SCH_VERSION_IN_INIFILE
8513 ERROR_DS_INVALID_GROUP_TYPE
8514 ERROR_DS_NO_NEST_GLOBALGROUP_IN_MIXEDDOMAIN
8515 ERROR_DS_NO_NEST_LOCALGROUP_IN_MIXEDDOMAIN
8516 ERROR_DS_GLOBAL_CANT_HAVE_LOCAL_MEMBER
8517 ERROR_DS_GLOBAL_CANT_HAVE_UNIVERSAL_MEMBER
8518 ERROR_DS_UNIVERSAL_CANT_HAVE_LOCAL_MEMBER
8519 ERROR_DS_GLOBAL_CANT_HAVE_CROSSDOMAIN_MEMBER
8520 ERROR_DS_LOCAL_CANT_HAVE_CROSSDOMAIN_LOCAL_MEMBER
8521 ERROR_DS_HAVE_PRIMARY_MEMBERS
8522 ERROR_DS_STRING_SD_CONVERSION_FAILED
8523 ERROR_DS_NAMING_MASTER_GC
8524 ERROR_DS_DNS_LOOKUP_FAILURE
8525 ERROR_DS_COULDNT_UPDATE_SPNS
8526 ERROR_DS_CANT_RETRIEVE_SD
8527 ERROR_DS_KEY_NOT_UNIQUE
8528 ERROR_DS_WRONG_LINKED_ATT_SYNTAX
8529 ERROR_DS_SAM_NEED_BOOTKEY_PASSWORD
8530 ERROR_DS_SAM_NEED_BOOTKEY_FLOPPY
8531 ERROR_DS_CANT_START
8532 ERROR_DS_INIT_FAILURE
8533 ERROR_DS_NO_PKT_PRIVACY_ON_CONNECTION
8534 ERROR_DS_SOURCE_DOMAIN_IN_FOREST
8535 ERROR_DS_DESTINATION_DOMAIN_NOT_IN_FOREST
8536 ERROR_DS_DESTINATION_AUDITING_NOT_ENABLED
8537 ERROR_DS_CANT_FIND_DC_FOR_SRC_DOMAIN
8538 ERROR_DS_SRC_OBJ_NOT_GROUP_OR_USER
8539 ERROR_DS_SRC_SID_EXISTS_IN_FOREST
8540 ERROR_DS_SRC_AND_DST_OBJECT_CLASS_MISMATCH
8541 ERROR_SAM_INIT_FAILURE
8542 ERROR_DS_DRA_SCHEMA_INFO_SHIP
8543 ERROR_DS_DRA_SCHEMA_CONFLICT
8544 ERROR_DS_DRA_EARLIER_SCHEMA_CONFLICT
8545 ERROR_DS_DRA_OBJ_NC_MISMATCH
8546 ERROR_DS_NC_STILL_HAS_DSAS
8547 ERROR_DS_GC_REQUIRED
8548 ERROR_DS_LOCAL_MEMBER_OF_LOCAL_ONLY
8549 ERROR_DS_NO_FPO_IN_UNIVERSAL_GROUPS
8550 ERROR_DS_CANT_ADD_TO_GC
8551 ERROR_DS_NO_CHECKPOINT_WITH_PDC
8552 ERROR_DS_SOURCE_AUDITING_NOT_ENABLED
8553 ERROR_DS_CANT_CREATE_IN_NONDOMAIN_NC
8554 ERROR_DS_INVALID_NAME_FOR_SPN
8555 ERROR_DS_FILTER_USES_CONTRUCTED_ATTRS
8556 ERROR_DS_UNICODEPWD_NOT_IN_QUOTES
8557 ERROR_DS_MACHINE_ACCOUNT_QUOTA_EXCEEDED
8558 ERROR_DS_MUST_BE_RUN_ON_DST_DC
8559 ERROR_DS_SRC_DC_MUST_BE_SP4_OR_GREATER
8560 ERROR_DS_CANT_TREE_DELETE_CRITICAL_OBJ
8561 ERROR_DS_INIT_FAILURE_CONSOLE
8562 ERROR_DS_SAM_INIT_FAILURE_CONSOLE
8563 ERROR_DS_FOREST_VERSION_TOO_HIGH
8564 ERROR_DS_DOMAIN_VERSION_TOO_HIGH
8565 ERROR_DS_FOREST_VERSION_TOO_LOW
8566 ERROR_DS_DOMAIN_VERSION_TOO_LOW
8567 ERROR_DS_INCOMPATIBLE_VERSION
8568 ERROR_DS_LOW_DSA_VERSION
8569 ERROR_DS_NO_BEHAVIOR_VERSION_IN_MIXEDDOMAIN
8570 ERROR_DS_NOT_SUPPORTED_SORT_ORDER
8571 ERROR_DS_NAME_NOT_UNIQUE
8572 ERROR_DS_MACHINE_ACCOUNT_CREATED_PRENT4
8573 ERROR_DS_OUT_OF_VERSION_STORE
8574 ERROR_DS_INCOMPATIBLE_CONTROLS_USED
8575 ERROR_DS_NO_REF_DOMAIN
8576 ERROR_DS_RESERVED_LINK_ID
8577 ERROR_DS_LINK_ID_NOT_AVAILABLE
8578 ERROR_DS_AG_CANT_HAVE_UNIVERSAL_MEMBER
8579 ERROR_DS_MODIFYDN_DISALLOWED_BY_INSTANCE_TYPE
8580 ERROR_DS_NO_OBJECT_MOVE_IN_SCHEMA_NC
8581 ERROR_DS_MODIFYDN_DISALLOWED_BY_FLAG
8582 ERROR_DS_MODIFYDN_WRONG_GRANDPARENT
8583 ERROR_DS_NAME_ERROR_TRUST_REFERRAL
8584 ERROR_NOT_SUPPORTED_ON_STANDARD_SERVER
8585 ERROR_DS_CANT_ACCESS_REMOTE_PART_OF_AD
8586 ERROR_DS_CR_IMPOSSIBLE_TO_VALIDATE_V2
8587 ERROR_DS_THREAD_LIMIT_EXCEEDED
8588 ERROR_DS_NOT_CLOSEST
8589 ERROR_DS_CANT_DERIVE_SPN_WITHOUT_SERVER_REF
8590 ERROR_DS_SINGLE_USER_MODE_FAILED
8591 ERROR_DS_NTDSCRIPT_SYNTAX_ERROR
8592 ERROR_DS_NTDSCRIPT_PROCESS_ERROR
8593 ERROR_DS_DIFFERENT_REPL_EPOCHS
8594 ERROR_DS_DRS_EXTENSIONS_CHANGED
8595 ERROR_DS_REPLICA_SET_CHANGE_NOT_ALLOWED_ON_DISABLED_CR
8596 ERROR_DS_NO_MSDS_INTID
8597 ERROR_DS_DUP_MSDS_INTID
8598 ERROR_DS_EXISTS_IN_RDNATTID
8599 ERROR_DS_AUTHORIZATION_FAILED
8600 ERROR_DS_INVALID_SCRIPT
8601 ERROR_DS_REMOTE_CROSSREF_OP_FAILED
8602 ERROR_DS_CROSS_REF_BUSY
8603 ERROR_DS_CANT_DERIVE_SPN_FOR_DELETED_DOMAIN
8604 ERROR_DS_CANT_DEMOTE_WITH_WRITEABLE_NC
8605 ERROR_DS_DUPLICATE_ID_FOUND
8606 ERROR_DS_INSUFFICIENT_ATTR_TO_CREATE_OBJECT
8607 ERROR_DS_GROUP_CONVERSION_ERROR
8608 ERROR_DS_CANT_MOVE_APP_BASIC_GROUP
8609 ERROR_DS_CANT_MOVE_APP_QUERY_GROUP
8610 ERROR_DS_ROLE_NOT_VERIFIED
8611 ERROR_DS_WKO_CONTAINER_CANNOT_BE_SPECIAL
8612 ERROR_DS_DOMAIN_RENAME_IN_PROGRESS
8613 ERROR_DS_EXISTING_AD_CHILD_NC
8614 ERROR_DS_REPL_LIFETIME_EXCEEDED
8615 ERROR_DS_DISALLOWED_IN_SYSTEM_CONTAINER
8616 ERROR_DS_LDAP_SEND_QUEUE_FULL
8617 ERROR_DS_DRA_OUT_SCHEDULE_WINDOW
8618 ERROR_DS_POLICY_NOT_KNOWN
8619 ERROR_NO_SITE_SETTINGS_OBJECT
8620 ERROR_NO_SECRETS
8621 ERROR_NO_WRITABLE_DC_FOUND
8622 ERROR_DS_NO_SERVER_OBJECT
8623 ERROR_DS_NO_NTDSA_OBJECT
8624 ERROR_DS_NON_ASQ_SEARCH
8625 ERROR_DS_AUDIT_FAILURE
8626 ERROR_DS_INVALID_SEARCH_FLAG_SUBTREE
8627 ERROR_DS_INVALID_SEARCH_FLAG_TUPLE
8628 ERROR_DS_HIERARCHY_TABLE_TOO_DEEP
8629 ERROR_DS_DRA_CORRUPT_UTD_VECTOR
8630 ERROR_DS_DRA_SECRETS_DENIED
8631 ERROR_DS_RESERVED_MAPI_ID
8632 ERROR_DS_MAPI_ID_NOT_AVAILABLE
8633 ERROR_DS_DRA_MISSING_KRBTGT_SECRET
8634 ERROR_DS_DOMAIN_NAME_EXISTS_IN_FOREST
8635 ERROR_DS_FLAT_NAME_EXISTS_IN_FOREST
8636 ERROR_INVALID_USER_PRINCIPAL_NAME
8637 ERROR_DS_OID_MAPPED_GROUP_CANT_HAVE_MEMBERS
8638 ERROR_DS_OID_NOT_FOUND
8639 ERROR_DS_DRA_RECYCLED_TARGET
8640 ERROR_DS_DISALLOWED_NC_REDIRECT
8641 ERROR_DS_HIGH_ADLDS_FFL
8642 ERROR_DS_HIGH_DSA_VERSION
8643 ERROR_DS_LOW_ADLDS_FFL
8644 ERROR_DOMAIN_SID_SAME_AS_LOCAL_WORKSTATION
8645 ERROR_DS_UNDELETE_SAM_VALIDATION_FAILED
8646 ERROR_INCORRECT_ACCOUNT_TYPE
8647 ERROR_DS_SPN_VALUE_NOT_UNIQUE_IN_FOREST
8648 ERROR_DS_UPN_VALUE_NOT_UNIQUE_IN_FOREST
8649 ERROR_DS_MISSING_FOREST_TRUST
8650 ERROR_DS_VALUE_KEY_NOT_UNIQUE
9000 DNS_ERROR_RESPONSE_CODES_BASE
9001 DNS_ERROR_RCODE_FORMAT_ERROR
9002 DNS_ERROR_RCODE_SERVER_FAILURE
9003 DNS_ERROR_RCODE_NAME_ERROR
9004 DNS_ERROR_RCODE_NOT_IMPLEMENTED
9005 DNS_ERROR_RCODE_REFUSED
9006 DNS_ERROR_RCODE_YXDOMAIN
9007 DNS_ERROR_RCODE_YXRRSET
9008 DNS_ERROR_RCODE_NXRRSET
9009 DNS_ERROR_RCODE_NOTAUTH
9010 DNS_ERROR_RCODE_NOTZONE
9016 DNS_ERROR_RCODE_BADSIG
9017 DNS_ERROR_RCODE_BADKEY
9018 DNS_ERROR_RCODE_BADTIME
9100 DNS_ERROR_DNSSEC_BASE
9101 DNS_ERROR_KEYMASTER_REQUIRED
9102 DNS_ERROR_NOT_ALLOWED_ON_SIGNED_ZONE
9103 DNS_ERROR_NSEC3_INCOMPATIBLE_WITH_RSA_SHA1
9104 DNS_ERROR_NOT_ENOUGH_SIGNING_KEY_DESCRIPTORS
9105 DNS_ERROR_UNSUPPORTED_ALGORITHM
9106 DNS_ERROR_INVALID_KEY_SIZE
9107 DNS_ERROR_SIGNING_KEY_NOT_ACCESSIBLE
9108 DNS_ERROR_KSP_DOES_NOT_SUPPORT_PROTECTION
9109 DNS_ERROR_UNEXPECTED_DATA_PROTECTION_ERROR
9110 DNS_ERROR_UNEXPECTED_CNG_ERROR
9111 DNS_ERROR_UNKNOWN_SIGNING_PARAMETER_VERSION
9112 DNS_ERROR_KSP_NOT_ACCESSIBLE
9113 DNS_ERROR_TOO_MANY_SKDS
9114 DNS_ERROR_INVALID_ROLLOVER_PERIOD
9115 DNS_ERROR_INVALID_INITIAL_ROLLOVER_OFFSET
9116 DNS_ERROR_ROLLOVER_IN_PROGRESS
9117 DNS_ERROR_STANDBY_KEY_NOT_PRESENT
9118 DNS_ERROR_NOT_ALLOWED_ON_ZSK
9119 DNS_ERROR_NOT_ALLOWED_ON_ACTIVE_SKD
9120 DNS_ERROR_ROLLOVER_ALREADY_QUEUED
9121 DNS_ERROR_NOT_ALLOWED_ON_UNSIGNED_ZONE
9122 DNS_ERROR_BAD_KEYMASTER
9123 DNS_ERROR_INVALID_SIGNATURE_VALIDITY_PERIOD
9124 DNS_ERROR_INVALID_NSEC3_ITERATION_COUNT
9125 DNS_ERROR_DNSSEC_IS_DISABLED
9126 DNS_ERROR_INVALID_XML
9127 DNS_ERROR_NO_VALID_TRUST_ANCHORS
9128 DNS_ERROR_ROLLOVER_NOT_POKEABLE
9129 DNS_ERROR_NSEC3_NAME_COLLISION
9130 DNS_ERROR_NSEC_INCOMPATIBLE_WITH_NSEC3_RSA_SHA1
9500 DNS_ERROR_PACKET_FMT_BASE
9501 DNS_INFO_NO_RECORDS
9502 DNS_ERROR_BAD_PACKET
9503 DNS_ERROR_NO_PACKET
9504 DNS_ERROR_RCODE
9505 DNS_ERROR_UNSECURE_PACKET
9506 DNS_REQUEST_PENDING
9550 DNS_ERROR_GENERAL_API_BASE
9551 DNS_ERROR_INVALID_TYPE
9552 DNS_ERROR_INVALID_IP_ADDRESS
9553 DNS_ERROR_INVALID_PROPERTY
9554 DNS_ERROR_TRY_AGAIN_LATER
9555 DNS_ERROR_NOT_UNIQUE
9556 DNS_ERROR_NON_RFC_NAME
9557 DNS_STATUS_FQDN
9558 DNS_STATUS_DOTTED_NAME
9559 DNS_STATUS_SINGLE_PART_NAME
9560 DNS_ERROR_INVALID_NAME_CHAR
9561 DNS_ERROR_NUMERIC_NAME
9562 DNS_ERROR_NOT_ALLOWED_ON_ROOT_SERVER
9563 DNS_ERROR_NOT_ALLOWED_UNDER_DELEGATION
9564 DNS_ERROR_CANNOT_FIND_ROOT_HINTS
9565 DNS_ERROR_INCONSISTENT_ROOT_HINTS
9566 DNS_ERROR_DWORD_VALUE_TOO_SMALL
9567 DNS_ERROR_DWORD_VALUE_TOO_LARGE
9568 DNS_ERROR_BACKGROUND_LOADING
9569 DNS_ERROR_NOT_ALLOWED_ON_RODC
9570 DNS_ERROR_NOT_ALLOWED_UNDER_DNAME
9571 DNS_ERROR_DELEGATION_REQUIRED
9572 DNS_ERROR_INVALID_POLICY_TABLE
9573 DNS_ERROR_ADDRESS_REQUIRED
9600 DNS_ERROR_ZONE_BASE
9601 DNS_ERROR_ZONE_DOES_NOT_EXIST
9602 DNS_ERROR_NO_ZONE_INFO
9603 DNS_ERROR_INVALID_ZONE_OPERATION
9604 DNS_ERROR_ZONE_CONFIGURATION_ERROR
9605 DNS_ERROR_ZONE_HAS_NO_SOA_RECORD
9606 DNS_ERROR_ZONE_HAS_NO_NS_RECORDS
9607 DNS_ERROR_ZONE_LOCKED
9608 DNS_ERROR_ZONE_CREATION_FAILED
9609 DNS_ERROR_ZONE_ALREADY_EXISTS
9610 DNS_ERROR_AUTOZONE_ALREADY_EXISTS
9611 DNS_ERROR_INVALID_ZONE_TYPE
9612 DNS_ERROR_SECONDARY_REQUIRES_MASTER_IP
9613 DNS_ERROR_ZONE_NOT_SECONDARY
9614 DNS_ERROR_NEED_SECONDARY_ADDRESSES
9615 DNS_ERROR_WINS_INIT_FAILED
9616 DNS_ERROR_NEED_WINS_SERVERS
9617 DNS_ERROR_NBSTAT_INIT_FAILED
9618 DNS_ERROR_SOA_DELETE_INVALID
9619 DNS_ERROR_FORWARDER_ALREADY_EXISTS
9620 DNS_ERROR_ZONE_REQUIRES_MASTER_IP
9621 DNS_ERROR_ZONE_IS_SHUTDOWN
9622 DNS_ERROR_ZONE_LOCKED_FOR_SIGNING
9650 DNS_ERROR_DATAFILE_BASE
9651 DNS_ERROR_PRIMARY_REQUIRES_DATAFILE
9652 DNS_ERROR_INVALID_DATAFILE_NAME
9653 DNS_ERROR_DATAFILE_OPEN_FAILURE
9654 DNS_ERROR_FILE_WRITEBACK_FAILED
9655 DNS_ERROR_DATAFILE_PARSING
9700 DNS_ERROR_DATABASE_BASE
9701 DNS_ERROR_RECORD_DOES_NOT_EXIST
9702 DNS_ERROR_RECORD_FORMAT
9703 DNS_ERROR_NODE_CREATION_FAILED
9704 DNS_ERROR_UNKNOWN_RECORD_TYPE
9705 DNS_ERROR_RECORD_TIMED_OUT
9706 DNS_ERROR_NAME_NOT_IN_ZONE
9707 DNS_ERROR_CNAME_LOOP
9708 DNS_ERROR_NODE_IS_CNAME
9709 DNS_ERROR_CNAME_COLLISION
9710 DNS_ERROR_RECORD_ONLY_AT_ZONE_ROOT
9711 DNS_ERROR_RECORD_ALREADY_EXISTS
9712 DNS_ERROR_SECONDARY_DATA
9713 DNS_ERROR_NO_CREATE_CACHE_DATA
9714 DNS_ERROR_NAME_DOES_NOT_EXIST
9715 DNS_WARNING_PTR_CREATE_FAILED
9716 DNS_WARNING_DOMAIN_UNDELETED
9717 DNS_ERROR_DS_UNAVAILABLE
9718 DNS_ERROR_DS_ZONE_ALREADY_EXISTS
9719 DNS_ERROR_NO_BOOTFILE_IF_DS_ZONE
9720 DNS_ERROR_NODE_IS_DNAME
9721 DNS_ERROR_DNAME_COLLISION
9722 DNS_ERROR_ALIAS_LOOP
9750 DNS_ERROR_OPERATION_BASE
9751 DNS_INFO_AXFR_COMPLETE
9752 DNS_ERROR_AXFR
9753 DNS_INFO_ADDED_LOCAL_WINS
9800 DNS_ERROR_SECURE_BASE
9801 DNS_STATUS_CONTINUE_NEEDED
9850 DNS_ERROR_SETUP_BASE
9851 DNS_ERROR_NO_TCPIP
9852 DNS_ERROR_NO_DNS_SERVERS
9900 DNS_ERROR_DP_BASE
9901 DNS_ERROR_DP_DOES_NOT_EXIST
9902 DNS_ERROR_DP_ALREADY_EXISTS
9903 DNS_ERROR_DP_NOT_ENLISTED
9904 DNS_ERROR_DP_ALREADY_ENLISTED
9905 DNS_ERROR_DP_NOT_AVAILABLE
9906 DNS_ERROR_DP_FSMO_ERROR
9911 DNS_ERROR_RRL_NOT_ENABLED
9912 DNS_ERROR_RRL_INVALID_WINDOW_SIZE
9913 DNS_ERROR_RRL_INVALID_IPV4_PREFIX
9914 DNS_ERROR_RRL_INVALID_IPV6_PREFIX
9915 DNS_ERROR_RRL_INVALID_TC_RATE
9916 DNS_ERROR_RRL_INVALID_LEAK_RATE
9917 DNS_ERROR_RRL_LEAK_RATE_LESSTHAN_TC_RATE
9921 DNS_ERROR_VIRTUALIZATION_INSTANCE_ALREADY_EXISTS
9922 DNS_ERROR_VIRTUALIZATION_INSTANCE_DOES_NOT_EXIST
9923 DNS_ERROR_VIRTUALIZATION_TREE_LOCKED
9924 DNS_ERROR_INVAILD_VIRTUALIZATION_INSTANCE_NAME
9925 DNS_ERROR_DEFAULT_VIRTUALIZATION_INSTANCE
9951 DNS_ERROR_ZONESCOPE_ALREADY_EXISTS
9952 DNS_ERROR_ZONESCOPE_DOES_NOT_EXIST
9953 DNS_ERROR_DEFAULT_ZONESCOPE
9954 DNS_ERROR_INVALID_ZONESCOPE_NAME
9955 DNS_ERROR_NOT_ALLOWED_WITH_ZONESCOPES
9956 DNS_ERROR_LOAD_ZONESCOPE_FAILED
9957 DNS_ERROR_ZONESCOPE_FILE_WRITEBACK_FAILED
9958 DNS_ERROR_INVALID_SCOPE_NAME
9959 DNS_ERROR_SCOPE_DOES_NOT_EXIST
9960 DNS_ERROR_DEFAULT_SCOPE
9961 DNS_ERROR_INVALID_SCOPE_OPERATION
9962 DNS_ERROR_SCOPE_LOCKED
9963 DNS_ERROR_SCOPE_ALREADY_EXISTS
9971 DNS_ERROR_POLICY_ALREADY_EXISTS
9972 DNS_ERROR_POLICY_DOES_NOT_EXIST
9973 DNS_ERROR_POLICY_INVALID_CRITERIA
9974 DNS_ERROR_POLICY_INVALID_SETTINGS
9975 DNS_ERROR_CLIENT_SUBNET_IS_ACCESSED
9976 DNS_ERROR_CLIENT_SUBNET_DOES_NOT_EXIST
9977 DNS_ERROR_CLIENT_SUBNET_ALREADY_EXISTS
9978 DNS_ERROR_SUBNET_DOES_NOT_EXIST
9979 DNS_ERROR_SUBNET_ALREADY_EXISTS
9980 DNS_ERROR_POLICY_LOCKED
9981 DNS_ERROR_POLICY_INVALID_WEIGHT
9982 DNS_ERROR_POLICY_INVALID_NAME
9983 DNS_ERROR_POLICY_MISSING_CRITERIA
9984 DNS_ERROR_INVALID_CLIENT_SUBNET_NAME
9985 DNS_ERROR_POLICY_PROCESSING_ORDER_INVALID
9986 DNS_ERROR_POLICY_SCOPE_MISSING
9987 DNS_ERROR_POLICY_SCOPE_NOT_ALLOWED
9988 DNS_ERROR_SERVERSCOPE_IS_REFERENCED
9989 DNS_ERROR_ZONESCOPE_IS_REFERENCED
9990 DNS_ERROR_POLICY_INVALID_CRITERIA_CLIENT_SUBNET
9991 DNS_ERROR_POLICY_INVALID_CRITERIA_TRANSPORT_PROTOCOL
9992 DNS_ERROR_POLICY_INVALID_CRITERIA_NETWORK_PROTOCOL
9993 DNS_ERROR_POLICY_INVALID_CRITERIA_INTERFACE
9994 DNS_ERROR_POLICY_INVALID_CRITERIA_FQDN
9995 DNS_ERROR_POLICY_INVALID_CRITERIA_QUERY_TYPE
9996 DNS_ERROR_POLICY_INVALID_CRITERIA_TIME_OF_DAY
10000 WSABASEERR
10004 WSAEINTR
10009 WSAEBADF
10013 WSAEACCES
10014 WSAEFAULT
10022 WSAEINVAL
10024 WSAEMFILE
10035 WSAEWOULDBLOCK
10036 WSAEINPROGRESS
10037 WSAEALREADY
10038 WSAENOTSOCK
10039 WSAEDESTADDRREQ
10040 WSAEMSGSIZE
10041 WSAEPROTOTYPE
10042 WSAENOPROTOOPT
10043 WSAEPROTONOSUPPORT
10044 WSAESOCKTNOSUPPORT
10045 WSAEOPNOTSUPP
10046 WSAEPFNOSUPPORT
10047 WSAEAFNOSUPPORT
10048 WSAEADDRINUSE
10049 WSAEADDRNOTAVAIL
10050 WSAENETDOWN
10051 WSAENETUNREACH
10052 WSAENETRESET
10053 WSAECONNABORTED
10054 WSAECONNRESET
10055 WSAENOBUFS
10056 WSAEISCONN
10057 WSAENOTCONN
10058 WSAESHUTDOWN
10059 WSAETOOMANYREFS
10060 WSAETIMEDOUT
10061 WSAECONNREFUSED
10062 WSAELOOP
10063 WSAENAMETOOLONG
10064 WSAEHOSTDOWN
10065 WSAEHOSTUNREACH
10066 WSAENOTEMPTY
10067 WSAEPROCLIM
10068 WSAEUSERS
10069 WSAEDQUOT
10070 WSAESTALE
10071 WSAEREMOTE
10091 WSASYSNOTREADY
10092 WSAVERNOTSUPPORTED
10093 WSANOTINITIALISED
10101 WSAEDISCON
10102 WSAENOMORE
10103 WSAECANCELLED
10104 WSAEINVALIDPROCTABLE
10105 WSAEINVALIDPROVIDER
10106 WSAEPROVIDERFAILEDINIT
10107 WSASYSCALLFAILURE
10108 WSASERVICE_NOT_FOUND
10109 WSATYPE_NOT_FOUND
10110 WSA_E_NO_MORE
10111 WSA_E_CANCELLED
10112 WSAEREFUSED
11001 WSAHOST_NOT_FOUND
11002 WSATRY_AGAIN
11003 WSANO_RECOVERY
11004 WSANO_DATA
11005 WSA_QOS_RECEIVERS
11006 WSA_QOS_SENDERS
11007 WSA_QOS_NO_SENDERS
11008 WSA_QOS_NO_RECEIVERS
11009 WSA_QOS_REQUEST_CONFIRMED
11010 WSA_QOS_ADMISSION_FAILURE
11011 WSA_QOS_POLICY_FAILURE
11012 WSA_QOS_BAD_STYLE
11013 WSA_QOS_BAD_OBJECT
11014 WSA_QOS_TRAFFIC_CTRL_ERROR
11015 WSA_QOS_GENERIC_ERROR
11016 WSA_QOS_ESERVICETYPE
11017 WSA_QOS_EFLOWSPEC
11018 WSA_QOS_EPROVSPECBUF
11019 WSA_QOS_EFILTERSTYLE
11020 WSA_QOS_EFILTERTYPE
11021 WSA_QOS_EFILTERCOUNT
11022 WSA_QOS_EOBJLENGTH
11023 WSA_QOS_EFLOWCOUNT
11024 WSA_QOS_EUNKOWNPSOBJ
11025 WSA_QOS_EPOLICYOBJ
11026 WSA_QOS_EFLOWDESC
11027 WSA_QOS_EPSFLOWSPEC
11028 WSA_QOS_EPSFILTERSPEC
11029 WSA_QOS_ESDMODEOBJ
11030 WSA_QOS_ESHAPERATEOBJ
11031 WSA_QOS_RESERVED_PETYPE
11032 WSA_SECURE_HOST_NOT_FOUND
11033 WSA_IPSEC_NAME_POLICY_ERROR
13000 ERROR_IPSEC_QM_POLICY_EXISTS
13001 ERROR_IPSEC_QM_POLICY_NOT_FOUND
13002 ERROR_IPSEC_QM_POLICY_IN_USE
13003 ERROR_IPSEC_MM_POLICY_EXISTS
13004 ERROR_IPSEC_MM_POLICY_NOT_FOUND
13005 ERROR_IPSEC_MM_POLICY_IN_USE
13006 ERROR_IPSEC_MM_FILTER_EXISTS
13007 ERROR_IPSEC_MM_FILTER_NOT_FOUND
13008 ERROR_IPSEC_TRANSPORT_FILTER_EXISTS
13009 ERROR_IPSEC_TRANSPORT_FILTER_NOT_FOUND
13010 ERROR_IPSEC_MM_AUTH_EXISTS
13011 ERROR_IPSEC_MM_AUTH_NOT_FOUND
13012 ERROR_IPSEC_MM_AUTH_IN_USE
13013 ERROR_IPSEC_DEFAULT_MM_POLICY_NOT_FOUND
13014 ERROR_IPSEC_DEFAULT_MM_AUTH_NOT_FOUND
13015 ERROR_IPSEC_DEFAULT_QM_POLICY_NOT_FOUND
13016 ERROR_IPSEC_TUNNEL_FILTER_EXISTS
13017 ERROR_IPSEC_TUNNEL_FILTER_NOT_FOUND
13018 ERROR_IPSEC_MM_FILTER_PENDING_DELETION
13019 ERROR_IPSEC_TRANSPORT_FILTER_PENDING_DELETION
13020 ERROR_IPSEC_TUNNEL_FILTER_PENDING_DELETION
13021 ERROR_IPSEC_MM_POLICY_PENDING_DELETION
13022 ERROR_IPSEC_MM_AUTH_PENDING_DELETION
13023 ERROR_IPSEC_QM_POLICY_PENDING_DELETION
13024 WARNING_IPSEC_MM_POLICY_PRUNED
13025 WARNING_IPSEC_QM_POLICY_PRUNED
13800 ERROR_IPSEC_IKE_NEG_STATUS_BEGIN
13801 ERROR_IPSEC_IKE_AUTH_FAIL
13802 ERROR_IPSEC_IKE_ATTRIB_FAIL
13803 ERROR_IPSEC_IKE_NEGOTIATION_PENDING
13804 ERROR_IPSEC_IKE_GENERAL_PROCESSING_ERROR
13805 ERROR_IPSEC_IKE_TIMED_OUT
13806 ERROR_IPSEC_IKE_NO_CERT
13807 ERROR_IPSEC_IKE_SA_DELETED
13808 ERROR_IPSEC_IKE_SA_REAPED
13809 ERROR_IPSEC_IKE_MM_ACQUIRE_DROP
13810 ERROR_IPSEC_IKE_QM_ACQUIRE_DROP
13811 ERROR_IPSEC_IKE_QUEUE_DROP_MM
13812 ERROR_IPSEC_IKE_QUEUE_DROP_NO_MM
13813 ERROR_IPSEC_IKE_DROP_NO_RESPONSE
13814 ERROR_IPSEC_IKE_MM_DELAY_DROP
13815 ERROR_IPSEC_IKE_QM_DELAY_DROP
13816 ERROR_IPSEC_IKE_ERROR
13817 ERROR_IPSEC_IKE_CRL_FAILED
13818 ERROR_IPSEC_IKE_INVALID_KEY_USAGE
13819 ERROR_IPSEC_IKE_INVALID_CERT_TYPE
13820 ERROR_IPSEC_IKE_NO_PRIVATE_KEY
13821 ERROR_IPSEC_IKE_SIMULTANEOUS_REKEY
13822 ERROR_IPSEC_IKE_DH_FAIL
13823 ERROR_IPSEC_IKE_CRITICAL_PAYLOAD_NOT_RECOGNIZED
13824 ERROR_IPSEC_IKE_INVALID_HEADER
13825 ERROR_IPSEC_IKE_NO_POLICY
13826 ERROR_IPSEC_IKE_INVALID_SIGNATURE
13827 ERROR_IPSEC_IKE_KERBEROS_ERROR
13828 ERROR_IPSEC_IKE_NO_PUBLIC_KEY
13829 ERROR_IPSEC_IKE_PROCESS_ERR
13830 ERROR_IPSEC_IKE_PROCESS_ERR_SA
13831 ERROR_IPSEC_IKE_PROCESS_ERR_PROP
13832 ERROR_IPSEC_IKE_PROCESS_ERR_TRANS
13833 ERROR_IPSEC_IKE_PROCESS_ERR_KE
13834 ERROR_IPSEC_IKE_PROCESS_ERR_ID
13835 ERROR_IPSEC_IKE_PROCESS_ERR_CERT
13836 ERROR_IPSEC_IKE_PROCESS_ERR_CERT_REQ
13837 ERROR_IPSEC_IKE_PROCESS_ERR_HASH
13838 ERROR_IPSEC_IKE_PROCESS_ERR_SIG
13839 ERROR_IPSEC_IKE_PROCESS_ERR_NONCE
13840 ERROR_IPSEC_IKE_PROCESS_ERR_NOTIFY
13841 ERROR_IPSEC_IKE_PROCESS_ERR_DELETE
13842 ERROR_IPSEC_IKE_PROCESS_ERR_VENDOR
13843 ERROR_IPSEC_IKE_INVALID_PAYLOAD
13844 ERROR_IPSEC_IKE_LOAD_SOFT_SA
13845 ERROR_IPSEC_IKE_SOFT_SA_TORN_DOWN
13846 ERROR_IPSEC_IKE_INVALID_COOKIE
13847 ERROR_IPSEC_IKE_NO_PEER_CERT
13848 ERROR_IPSEC_IKE_PEER_CRL_FAILED
13849 ERROR_IPSEC_IKE_POLICY_CHANGE
13850 ERROR_IPSEC_IKE_NO_MM_POLICY
13851 ERROR_IPSEC_IKE_NOTCBPRIV
13852 ERROR_IPSEC_IKE_SECLOADFAIL
13853 ERROR_IPSEC_IKE_FAILSSPINIT
13854 ERROR_IPSEC_IKE_FAILQUERYSSP
13855 ERROR_IPSEC_IKE_SRVACQFAIL
13856 ERROR_IPSEC_IKE_SRVQUERYCRED
13857 ERROR_IPSEC_IKE_GETSPIFAIL
13858 ERROR_IPSEC_IKE_INVALID_FILTER
13859 ERROR_IPSEC_IKE_OUT_OF_MEMORY
13860 ERROR_IPSEC_IKE_ADD_UPDATE_KEY_FAILED
13861 ERROR_IPSEC_IKE_INVALID_POLICY
13862 ERROR_IPSEC_IKE_UNKNOWN_DOI
13863 ERROR_IPSEC_IKE_INVALID_SITUATION
13864 ERROR_IPSEC_IKE_DH_FAILURE
13865 ERROR_IPSEC_IKE_INVALID_GROUP
13866 ERROR_IPSEC_IKE_ENCRYPT
13867 ERROR_IPSEC_IKE_DECRYPT
13868 ERROR_IPSEC_IKE_POLICY_MATCH
13869 ERROR_IPSEC_IKE_UNSUPPORTED_ID
13870 ERROR_IPSEC_IKE_INVALID_HASH
13871 ERROR_IPSEC_IKE_INVALID_HASH_ALG
13872 ERROR_IPSEC_IKE_INVALID_HASH_SIZE
13873 ERROR_IPSEC_IKE_INVALID_ENCRYPT_ALG
13874 ERROR_IPSEC_IKE_INVALID_AUTH_ALG
13875 ERROR_IPSEC_IKE_INVALID_SIG
13876 ERROR_IPSEC_IKE_LOAD_FAILED
13877 ERROR_IPSEC_IKE_RPC_DELETE
13878 ERROR_IPSEC_IKE_BENIGN_REINIT
13879 ERROR_IPSEC_IKE_INVALID_RESPONDER_LIFETIME_NOTIFY
13880 ERROR_IPSEC_IKE_INVALID_MAJOR_VERSION
13881 ERROR_IPSEC_IKE_INVALID_CERT_KEYLEN
13882 ERROR_IPSEC_IKE_MM_LIMIT
13883 ERROR_IPSEC_IKE_NEGOTIATION_DISABLED
13884 ERROR_IPSEC_IKE_QM_LIMIT
13885 ERROR_IPSEC_IKE_MM_EXPIRED
13886 ERROR_IPSEC_IKE_PEER_MM_ASSUMED_INVALID
13887 ERROR_IPSEC_IKE_CERT_CHAIN_POLICY_MISMATCH
13888 ERROR_IPSEC_IKE_UNEXPECTED_MESSAGE_ID
13889 ERROR_IPSEC_IKE_INVALID_AUTH_PAYLOAD
13890 ERROR_IPSEC_IKE_DOS_COOKIE_SENT
13891 ERROR_IPSEC_IKE_SHUTTING_DOWN
13892 ERROR_IPSEC_IKE_CGA_AUTH_FAILED
13893 ERROR_IPSEC_IKE_PROCESS_ERR_NATOA
13894 ERROR_IPSEC_IKE_INVALID_MM_FOR_QM
13895 ERROR_IPSEC_IKE_QM_EXPIRED
13896 ERROR_IPSEC_IKE_TOO_MANY_FILTERS
13897 ERROR_IPSEC_IKE_NEG_STATUS_END
13898 ERROR_IPSEC_IKE_KILL_DUMMY_NAP_TUNNEL
13899 ERROR_IPSEC_IKE_INNER_IP_ASSIGNMENT_FAILURE
13900 ERROR_IPSEC_IKE_REQUIRE_CP_PAYLOAD_MISSING
13901 ERROR_IPSEC_KEY_MODULE_IMPERSONATION_NEGOTIATION_PENDING
13902 ERROR_IPSEC_IKE_COEXISTENCE_SUPPRESS
13903 ERROR_IPSEC_IKE_RATELIMIT_DROP
13904 ERROR_IPSEC_IKE_PEER_DOESNT_SUPPORT_MOBIKE
13905 ERROR_IPSEC_IKE_AUTHORIZATION_FAILURE
13906 ERROR_IPSEC_IKE_STRONG_CRED_AUTHORIZATION_FAILURE
13907 ERROR_IPSEC_IKE_AUTHORIZATION_FAILURE_WITH_OPTIONAL_RETRY
13908 ERROR_IPSEC_IKE_STRONG_CRED_AUTHORIZATION_AND_CERTMAP_FAILURE
13909 ERROR_IPSEC_IKE_NEG_STATUS_EXTENDED_END
13910 ERROR_IPSEC_BAD_SPI
13911 ERROR_IPSEC_SA_LIFETIME_EXPIRED
13912 ERROR_IPSEC_WRONG_SA
13913 ERROR_IPSEC_REPLAY_CHECK_FAILED
13914 ERROR_IPSEC_INVALID_PACKET
13915 ERROR_IPSEC_INTEGRITY_CHECK_FAILED
13916 ERROR_IPSEC_CLEAR_TEXT_DROP
13917 ERROR_IPSEC_AUTH_FIREWALL_DROP
13918 ERROR_IPSEC_THROTTLE_DROP
13925 ERROR_IPSEC_DOSP_BLOCK
13926 ERROR_IPSEC_DOSP_RECEIVED_MULTICAST
13927 ERROR_IPSEC_DOSP_INVALID_PACKET
13928 ERROR_IPSEC_DOSP_STATE_LOOKUP_FAILED
13929 ERROR_IPSEC_DOSP_MAX_ENTRIES
13930 ERROR_IPSEC_DOSP_KEYMOD_NOT_ALLOWED
13931 ERROR_IPSEC_DOSP_NOT_INSTALLED
13932 ERROR_IPSEC_DOSP_MAX_PER_IP_RATELIMIT_QUEUES
14000 ERROR_SXS_SECTION_NOT_FOUND
14001 ERROR_SXS_CANT_GEN_ACTCTX
14002 ERROR_SXS_INVALID_ACTCTXDATA_FORMAT
14003 ERROR_SXS_ASSEMBLY_NOT_FOUND
14004 ERROR_SXS_MANIFEST_FORMAT_ERROR
14005 ERROR_SXS_MANIFEST_PARSE_ERROR
14006 ERROR_SXS_ACTIVATION_CONTEXT_DISABLED
14007 ERROR_SXS_KEY_NOT_FOUND
14008 ERROR_SXS_VERSION_CONFLICT
14009 ERROR_SXS_WRONG_SECTION_TYPE
14010 ERROR_SXS_THREAD_QUERIES_DISABLED
14011 ERROR_SXS_PROCESS_DEFAULT_ALREADY_SET
14012 ERROR_SXS_UNKNOWN_ENCODING_GROUP
14013 ERROR_SXS_UNKNOWN_ENCODING
14014 ERROR_SXS_INVALID_XML_NAMESPACE_URI
14015 ERROR_SXS_ROOT_MANIFEST_DEPENDENCY_NOT_INSTALLED
14016 ERROR_SXS_LEAF_MANIFEST_DEPENDENCY_NOT_INSTALLED
14017 ERROR_SXS_INVALID_ASSEMBLY_IDENTITY_ATTRIBUTE
14018 ERROR_SXS_MANIFEST_MISSING_REQUIRED_DEFAULT_NAMESPACE
14019 ERROR_SXS_MANIFEST_INVALID_REQUIRED_DEFAULT_NAMESPACE
14020 ERROR_SXS_PRIVATE_MANIFEST_CROSS_PATH_WITH_REPARSE_POINT
14021 ERROR_SXS_DUPLICATE_DLL_NAME
14022 ERROR_SXS_DUPLICATE_WINDOWCLASS_NAME
14023 ERROR_SXS_DUPLICATE_CLSID
14024 ERROR_SXS_DUPLICATE_IID
14025 ERROR_SXS_DUPLICATE_TLBID
14026 ERROR_SXS_DUPLICATE_PROGID
14027 ERROR_SXS_DUPLICATE_ASSEMBLY_NAME
14028 ERROR_SXS_FILE_HASH_MISMATCH
14029 ERROR_SXS_POLICY_PARSE_ERROR
14030 ERROR_SXS_XML_E_MISSINGQUOTE
14031 ERROR_SXS_XML_E_COMMENTSYNTAX
14032 ERROR_SXS_XML_E_BADSTARTNAMECHAR
14033 ERROR_SXS_XML_E_BADNAMECHAR
14034 ERROR_SXS_XML_E_BADCHARINSTRING
14035 ERROR_SXS_XML_E_XMLDECLSYNTAX
14036 ERROR_SXS_XML_E_BADCHARDATA
14037 ERROR_SXS_XML_E_MISSINGWHITESPACE
14038 ERROR_SXS_XML_E_EXPECTINGTAGEND
14039 ERROR_SXS_XML_E_MISSINGSEMICOLON
14040 ERROR_SXS_XML_E_UNBALANCEDPAREN
14041 ERROR_SXS_XML_E_INTERNALERROR
14042 ERROR_SXS_XML_E_UNEXPECTED_WHITESPACE
14043 ERROR_SXS_XML_E_INCOMPLETE_ENCODING
14044 ERROR_SXS_XML_E_MISSING_PAREN
14045 ERROR_SXS_XML_E_EXPECTINGCLOSEQUOTE
14046 ERROR_SXS_XML_E_MULTIPLE_COLONS
14047 ERROR_SXS_XML_E_INVALID_DECIMAL
14048 ERROR_SXS_XML_E_INVALID_HEXIDECIMAL
14049 ERROR_SXS_XML_E_INVALID_UNICODE
14050 ERROR_SXS_XML_E_WHITESPACEORQUESTIONMARK
14051 ERROR_SXS_XML_E_UNEXPECTEDENDTAG
14052 ERROR_SXS_XML_E_UNCLOSEDTAG
14053 ERROR_SXS_XML_E_DUPLICATEATTRIBUTE
14054 ERROR_SXS_XML_E_MULTIPLEROOTS
14055 ERROR_SXS_XML_E_INVALIDATROOTLEVEL
14056 ERROR_SXS_XML_E_BADXMLDECL
14057 ERROR_SXS_XML_E_MISSINGROOT
14058 ERROR_SXS_XML_E_UNEXPECTEDEOF
14059 ERROR_SXS_XML_E_BADPEREFINSUBSET
14060 ERROR_SXS_XML_E_UNCLOSEDSTARTTAG
14061 ERROR_SXS_XML_E_UNCLOSEDENDTAG
14062 ERROR_SXS_XML_E_UNCLOSEDSTRING
14063 ERROR_SXS_XML_E_UNCLOSEDCOMMENT
14064 ERROR_SXS_XML_E_UNCLOSEDDECL
14065 ERROR_SXS_XML_E_UNCLOSEDCDATA
14066 ERROR_SXS_XML_E_RESERVEDNAMESPACE
14067 ERROR_SXS_XML_E_INVALIDENCODING
14068 ERROR_SXS_XML_E_INVALIDSWITCH
14069 ERROR_SXS_XML_E_BADXMLCASE
14070 ERROR_SXS_XML_E_INVALID_STANDALONE
14071 ERROR_SXS_XML_E_UNEXPECTED_STANDALONE
14072 ERROR_SXS_XML_E_INVALID_VERSION
14073 ERROR_SXS_XML_E_MISSINGEQUALS
14074 ERROR_SXS_PROTECTION_RECOVERY_FAILED
14075 ERROR_SXS_PROTECTION_PUBLIC_KEY_TOO_SHORT
14076 ERROR_SXS_PROTECTION_CATALOG_NOT_VALID
14077 ERROR_SXS_UNTRANSLATABLE_HRESULT
14078 ERROR_SXS_PROTECTION_CATALOG_FILE_MISSING
14079 ERROR_SXS_MISSING_ASSEMBLY_IDENTITY_ATTRIBUTE
14080 ERROR_SXS_INVALID_ASSEMBLY_IDENTITY_ATTRIBUTE_NAME
14081 ERROR_SXS_ASSEMBLY_MISSING
14082 ERROR_SXS_CORRUPT_ACTIVATION_STACK
14083 ERROR_SXS_CORRUPTION
14084 ERROR_SXS_EARLY_DEACTIVATION
14085 ERROR_SXS_INVALID_DEACTIVATION
14086 ERROR_SXS_MULTIPLE_DEACTIVATION
14087 ERROR_SXS_PROCESS_TERMINATION_REQUESTED
14088 ERROR_SXS_RELEASE_ACTIVATION_CONTEXT
14089 ERROR_SXS_SYSTEM_DEFAULT_ACTIVATION_CONTEXT_EMPTY
14090 ERROR_SXS_INVALID_IDENTITY_ATTRIBUTE_VALUE
14091 ERROR_SXS_INVALID_IDENTITY_ATTRIBUTE_NAME
14092 ERROR_SXS_IDENTITY_DUPLICATE_ATTRIBUTE
14093 ERROR_SXS_IDENTITY_PARSE_ERROR
14094 ERROR_MALFORMED_SUBSTITUTION_STRING
14095 ERROR_SXS_INCORRECT_PUBLIC_KEY_TOKEN
14096 ERROR_UNMAPPED_SUBSTITUTION_STRING
14097 ERROR_SXS_ASSEMBLY_NOT_LOCKED
14098 ERROR_SXS_COMPONENT_STORE_CORRUPT
14099 ERROR_ADVANCED_INSTALLER_FAILED
14100 ERROR_XML_ENCODING_MISMATCH
14101 ERROR_SXS_MANIFEST_IDENTITY_SAME_BUT_CONTENTS_DIFFERENT
14102 ERROR_SXS_IDENTITIES_DIFFERENT
14103 ERROR_SXS_ASSEMBLY_IS_NOT_A_DEPLOYMENT
14104 ERROR_SXS_FILE_NOT_PART_OF_ASSEMBLY
14105 ERROR_SXS_MANIFEST_TOO_BIG
14106 ERROR_SXS_SETTING_NOT_REGISTERED
14107 ERROR_SXS_TRANSACTION_CLOSURE_INCOMPLETE
14108 ERROR_SMI_PRIMITIVE_INSTALLER_FAILED
14109 ERROR_GENERIC_COMMAND_FAILED
14110 ERROR_SXS_FILE_HASH_MISSING
15000 ERROR_EVT_INVALID_CHANNEL_PATH
15001 ERROR_EVT_INVALID_QUERY
15002 ERROR_EVT_PUBLISHER_METADATA_NOT_FOUND
15003 ERROR_EVT_EVENT_TEMPLATE_NOT_FOUND
15004 ERROR_EVT_INVALID_PUBLISHER_NAME
15005 ERROR_EVT_INVALID_EVENT_DATA
15007 ERROR_EVT_CHANNEL_NOT_FOUND
15008 ERROR_EVT_MALFORMED_XML_TEXT
15009 ERROR_EVT_SUBSCRIPTION_TO_DIRECT_CHANNEL
15010 ERROR_EVT_CONFIGURATION_ERROR
15011 ERROR_EVT_QUERY_RESULT_STALE
15012 ERROR_EVT_QUERY_RESULT_INVALID_POSITION
15013 ERROR_EVT_NON_VALIDATING_MSXML
15014 ERROR_EVT_FILTER_ALREADYSCOPED
15015 ERROR_EVT_FILTER_NOTELTSET
15016 ERROR_EVT_FILTER_INVARG
15017 ERROR_EVT_FILTER_INVTEST
15018 ERROR_EVT_FILTER_INVTYPE
15019 ERROR_EVT_FILTER_PARSEERR
15020 ERROR_EVT_FILTER_UNSUPPORTEDOP
15021 ERROR_EVT_FILTER_UNEXPECTEDTOKEN
15022 ERROR_EVT_INVALID_OPERATION_OVER_ENABLED_DIRECT_CHANNEL
15023 ERROR_EVT_INVALID_CHANNEL_PROPERTY_VALUE
15024 ERROR_EVT_INVALID_PUBLISHER_PROPERTY_VALUE
15025 ERROR_EVT_CHANNEL_CANNOT_ACTIVATE
15026 ERROR_EVT_FILTER_TOO_COMPLEX
15027 ERROR_EVT_MESSAGE_NOT_FOUND
15028 ERROR_EVT_MESSAGE_ID_NOT_FOUND
15029 ERROR_EVT_UNRESOLVED_VALUE_INSERT
15030 ERROR_EVT_UNRESOLVED_PARAMETER_INSERT
15031 ERROR_EVT_MAX_INSERTS_REACHED
15032 ERROR_EVT_EVENT_DEFINITION_NOT_FOUND
15033 ERROR_EVT_MESSAGE_LOCALE_NOT_FOUND
15034 ERROR_EVT_VERSION_TOO_OLD
15035 ERROR_EVT_VERSION_TOO_NEW
15036 ERROR_EVT_CANNOT_OPEN_CHANNEL_OF_QUERY
15037 ERROR_EVT_PUBLISHER_DISABLED
15038 ERROR_EVT_FILTER_OUT_OF_RANGE
15080 ERROR_EC_SUBSCRIPTION_CANNOT_ACTIVATE
15081 ERROR_EC_LOG_DISABLED
15082 ERROR_EC_CIRCULAR_FORWARDING
15083 ERROR_EC_CREDSTORE_FULL
15084 ERROR_EC_CRED_NOT_FOUND
15085 ERROR_EC_NO_ACTIVE_CHANNEL
15100 ERROR_MUI_FILE_NOT_FOUND
15101 ERROR_MUI_INVALID_FILE
15102 ERROR_MUI_INVALID_RC_CONFIG
15103 ERROR_MUI_INVALID_LOCALE_NAME
15104 ERROR_MUI_INVALID_ULTIMATEFALLBACK_NAME
15105 ERROR_MUI_FILE_NOT_LOADED
15106 ERROR_RESOURCE_ENUM_USER_STOP
15107 ERROR_MUI_INTLSETTINGS_UILANG_NOT_INSTALLED
15108 ERROR_MUI_INTLSETTINGS_INVALID_LOCALE_NAME
15110 ERROR_MRM_RUNTIME_NO_DEFAULT_OR_NEUTRAL_RESOURCE
15111 ERROR_MRM_INVALID_PRICONFIG
15112 ERROR_MRM_INVALID_FILE_TYPE
15113 ERROR_MRM_UNKNOWN_QUALIFIER
15114 ERROR_MRM_INVALID_QUALIFIER_VALUE
15115 ERROR_MRM_NO_CANDIDATE
15116 ERROR_MRM_NO_MATCH_OR_DEFAULT_CANDIDATE
15117 ERROR_MRM_RESOURCE_TYPE_MISMATCH
15118 ERROR_MRM_DUPLICATE_MAP_NAME
15119 ERROR_MRM_DUPLICATE_ENTRY
15120 ERROR_MRM_INVALID_RESOURCE_IDENTIFIER
15121 ERROR_MRM_FILEPATH_TOO_LONG
15122 ERROR_MRM_UNSUPPORTED_DIRECTORY_TYPE
15126 ERROR_MRM_INVALID_PRI_FILE
15127 ERROR_MRM_NAMED_RESOURCE_NOT_FOUND
15135 ERROR_MRM_MAP_NOT_FOUND
15136 ERROR_MRM_UNSUPPORTED_PROFILE_TYPE
15137 ERROR_MRM_INVALID_QUALIFIER_OPERATOR
15138 ERROR_MRM_INDETERMINATE_QUALIFIER_VALUE
15139 ERROR_MRM_AUTOMERGE_ENABLED
15140 ERROR_MRM_TOO_MANY_RESOURCES
15141 ERROR_MRM_UNSUPPORTED_FILE_TYPE_FOR_MERGE
15142 ERROR_MRM_UNSUPPORTED_FILE_TYPE_FOR_LOAD_UNLOAD_PRI_FILE
15143 ERROR_MRM_NO_CURRENT_VIEW_ON_THREAD
15144 ERROR_DIFFERENT_PROFILE_RESOURCE_MANAGER_EXIST
15145 ERROR_OPERATION_NOT_ALLOWED_FROM_SYSTEM_COMPONENT
15146 ERROR_MRM_DIRECT_REF_TO_NON_DEFAULT_RESOURCE
15147 ERROR_MRM_GENERATION_COUNT_MISMATCH
15148 ERROR_PRI_MERGE_VERSION_MISMATCH
15149 ERROR_PRI_MERGE_MISSING_SCHEMA
15150 ERROR_PRI_MERGE_LOAD_FILE_FAILED
15151 ERROR_PRI_MERGE_ADD_FILE_FAILED
15152 ERROR_PRI_MERGE_WRITE_FILE_FAILED
15153 ERROR_PRI_MERGE_MULTIPLE_PACKAGE_FAMILIES_NOT_ALLOWED
15154 ERROR_PRI_MERGE_MULTIPLE_MAIN_PACKAGES_NOT_ALLOWED
15155 ERROR_PRI_MERGE_BUNDLE_PACKAGES_NOT_ALLOWED
15156 ERROR_PRI_MERGE_MAIN_PACKAGE_REQUIRED
15157 ERROR_PRI_MERGE_RESOURCE_PACKAGE_REQUIRED
15158 ERROR_PRI_MERGE_INVALID_FILE_NAME
15200 ERROR_MCA_INVALID_CAPABILITIES_STRING
15201 ERROR_MCA_INVALID_VCP_VERSION
15202 ERROR_MCA_MONITOR_VIOLATES_MCCS_SPECIFICATION
15203 ERROR_MCA_MCCS_VERSION_MISMATCH
15204 ERROR_MCA_UNSUPPORTED_MCCS_VERSION
15205 ERROR_MCA_INTERNAL_ERROR
15206 ERROR_MCA_INVALID_TECHNOLOGY_TYPE_RETURNED
15207 ERROR_MCA_UNSUPPORTED_COLOR_TEMPERATURE
15250 ERROR_AMBIGUOUS_SYSTEM_DEVICE
15299 ERROR_SYSTEM_DEVICE_NOT_FOUND
15300 ERROR_HASH_NOT_SUPPORTED
15301 ERROR_HASH_NOT_PRESENT
15321 ERROR_SECONDARY_IC_PROVIDER_NOT_REGISTERED
15322 ERROR_GPIO_CLIENT_INFORMATION_INVALID
15323 ERROR_GPIO_VERSION_NOT_SUPPORTED
15324 ERROR_GPIO_INVALID_REGISTRATION_PACKET
15325 ERROR_GPIO_OPERATION_DENIED
15326 ERROR_GPIO_INCOMPATIBLE_CONNECT_MODE
15327 ERROR_GPIO_INTERRUPT_ALREADY_UNMASKED
15400 ERROR_CANNOT_SWITCH_RUNLEVEL
15401 ERROR_INVALID_RUNLEVEL_SETTING
15402 ERROR_RUNLEVEL_SWITCH_TIMEOUT
15403 ERROR_RUNLEVEL_SWITCH_AGENT_TIMEOUT
15404 ERROR_RUNLEVEL_SWITCH_IN_PROGRESS
15405 ERROR_SERVICES_FAILED_AUTOSTART
15501 ERROR_COM_TASK_STOP_PENDING
15600 ERROR_INSTALL_OPEN_PACKAGE_FAILED
15601 ERROR_INSTALL_PACKAGE_NOT_FOUND
15602 ERROR_INSTALL_INVALID_PACKAGE
15603 ERROR_INSTALL_RESOLVE_DEPENDENCY_FAILED
15604 ERROR_INSTALL_OUT_OF_DISK_SPACE
15605 ERROR_INSTALL_NETWORK_FAILURE
15606 ERROR_INSTALL_REGISTRATION_FAILURE
15607 ERROR_INSTALL_DEREGISTRATION_FAILURE
15608 ERROR_INSTALL_CANCEL
15609 ERROR_INSTALL_FAILED
15610 ERROR_REMOVE_FAILED
15611 ERROR_PACKAGE_ALREADY_EXISTS
15612 ERROR_NEEDS_REMEDIATION
15613 ERROR_INSTALL_PREREQUISITE_FAILED
15614 ERROR_PACKAGE_REPOSITORY_CORRUPTED
15615 ERROR_INSTALL_POLICY_FAILURE
15616 ERROR_PACKAGE_UPDATING
15617 ERROR_DEPLOYMENT_BLOCKED_BY_POLICY
15618 ERROR_PACKAGES_IN_USE
15619 ERROR_RECOVERY_FILE_CORRUPT
15620 ERROR_INVALID_STAGED_SIGNATURE
15621 ERROR_DELETING_EXISTING_APPLICATIONDATA_STORE_FAILED
15622 ERROR_INSTALL_PACKAGE_DOWNGRADE
15623 ERROR_SYSTEM_NEEDS_REMEDIATION
15624 ERROR_APPX_INTEGRITY_FAILURE_CLR_NGEN
15625 ERROR_RESILIENCY_FILE_CORRUPT
15626 ERROR_INSTALL_FIREWALL_SERVICE_NOT_RUNNING
15627 ERROR_PACKAGE_MOVE_FAILED
15628 ERROR_INSTALL_VOLUME_NOT_EMPTY
15629 ERROR_INSTALL_VOLUME_OFFLINE
15630 ERROR_INSTALL_VOLUME_CORRUPT
15631 ERROR_NEEDS_REGISTRATION
15632 ERROR_INSTALL_WRONG_PROCESSOR_ARCHITECTURE
15633 ERROR_DEV_SIDELOAD_LIMIT_EXCEEDED
15634 ERROR_INSTALL_OPTIONAL_PACKAGE_REQUIRES_MAIN_PACKAGE
15635 ERROR_PACKAGE_NOT_SUPPORTED_ON_FILESYSTEM
15636 ERROR_PACKAGE_MOVE_BLOCKED_BY_STREAMING
15637 ERROR_INSTALL_OPTIONAL_PACKAGE_APPLICATIONID_NOT_UNIQUE
15638 ERROR_PACKAGE_STAGING_ONHOLD
15639 ERROR_INSTALL_INVALID_RELATED_SET_UPDATE
15640 ERROR_INSTALL_OPTIONAL_PACKAGE_REQUIRES_MAIN_PACKAGE_FULLTRUST_CAPABILITY
15641 ERROR_DEPLOYMENT_BLOCKED_BY_USER_LOG_OFF
15642 ERROR_PROVISION_OPTIONAL_PACKAGE_REQUIRES_MAIN_PACKAGE_PROVISIONED
15643 ERROR_PACKAGES_REPUTATION_CHECK_FAILED
15644 ERROR_PACKAGES_REPUTATION_CHECK_TIMEDOUT
15700 APPMODEL_ERROR_NO_PACKAGE
15701 APPMODEL_ERROR_PACKAGE_RUNTIME_CORRUPT
15702 APPMODEL_ERROR_PACKAGE_IDENTITY_CORRUPT
15703 APPMODEL_ERROR_NO_APPLICATION
15704 APPMODEL_ERROR_DYNAMIC_PROPERTY_READ_FAILED
15705 APPMODEL_ERROR_DYNAMIC_PROPERTY_INVALID
15706 APPMODEL_ERROR_PACKAGE_NOT_AVAILABLE
15800 ERROR_STATE_LOAD_STORE_FAILED
15801 ERROR_STATE_GET_VERSION_FAILED
15802 ERROR_STATE_SET_VERSION_FAILED
15803 ERROR_STATE_STRUCTURED_RESET_FAILED
15804 ERROR_STATE_OPEN_CONTAINER_FAILED
15805 ERROR_STATE_CREATE_CONTAINER_FAILED
15806 ERROR_STATE_DELETE_CONTAINER_FAILED
15807 ERROR_STATE_READ_SETTING_FAILED
15808 ERROR_STATE_WRITE_SETTING_FAILED
15809 ERROR_STATE_DELETE_SETTING_FAILED
15810 ERROR_STATE_QUERY_SETTING_FAILED
15811 ERROR_STATE_READ_COMPOSITE_SETTING_FAILED
15812 ERROR_STATE_WRITE_COMPOSITE_SETTING_FAILED
15813 ERROR_STATE_ENUMERATE_CONTAINER_FAILED
15814 ERROR_STATE_ENUMERATE_SETTINGS_FAILED
15815 ERROR_STATE_COMPOSITE_SETTING_VALUE_SIZE_LIMIT_EXCEEDED
15816 ERROR_STATE_SETTING_VALUE_SIZE_LIMIT_EXCEEDED
15817 ERROR_STATE_SETTING_NAME_SIZE_LIMIT_EXCEEDED
15818 ERROR_STATE_CONTAINER_NAME_SIZE_LIMIT_EXCEEDED
15841 ERROR_API_UNAVAILABLE
15861 STORE_ERROR_UNLICENSED
15862 STORE_ERROR_UNLICENSED_USER
15863 STORE_ERROR_PENDING_COM_TRANSACTION
15864 STORE_ERROR_LICENSE_REVOKED |
Text | x64dbg-development/bin/exceptiondb.txt | 0x04242420 CLRDBG_NOTIFICATION_EXCEPTION_CODE
0x40000005 STATUS_SEGMENT_NOTIFICATION
0x40000015 STATUS_FATAL_APP_EXIT
0x4000001C STATUS_WX86_UNSIMULATE
0x4000001D STATUS_WX86_CONTINUE
0x4000001E STATUS_WX86_SINGLE_STEP
0x4000001F STATUS_WX86_BREAKPOINT
0x40000020 STATUS_WX86_EXCEPTION_CONTINUE
0x40000021 STATUS_WX86_EXCEPTION_LASTCHANCE
0x40000022 STATUS_WX86_EXCEPTION_CHAIN
0x40000028 STATUS_WX86_CREATEWX86TIB
0x40010003 DBG_TERMINATE_THREAD
0x40010004 DBG_TERMINATE_PROCESS
0x40010005 DBG_CONTROL_C
0x40010006 DBG_PRINTEXCEPTION_C
0x40010007 DBG_RIPEXCEPTION
0x40010008 DBG_CONTROL_BREAK
0x40010009 DBG_COMMAND_EXCEPTION
0x4001000A DBG_PRINTEXCEPTION_WIDE_C
0x40080201 EXCEPTION_RO_ORIGINATEERROR
0x40080202 EXCEPTION_RO_TRANSFORMERROR
0x406D1388 MS_VC_EXCEPTION
0x80000001 EXCEPTION_GUARD_PAGE
0x80000002 EXCEPTION_DATATYPE_MISALIGNMENT
0x80000003 EXCEPTION_BREAKPOINT
0x80000004 EXCEPTION_SINGLE_STEP
0x80000026 STATUS_LONGJUMP
0x80000029 STATUS_UNWIND_CONSOLIDATE
0x80010001 DBG_EXCEPTION_NOT_HANDLED
0xC0000005 EXCEPTION_ACCESS_VIOLATION
0xC0000006 EXCEPTION_IN_PAGE_ERROR
0xC0000008 EXCEPTION_INVALID_HANDLE
0xC000000D STATUS_INVALID_PARAMETER
0xC0000017 STATUS_NO_MEMORY
0xC000001D EXCEPTION_ILLEGAL_INSTRUCTION
0xC0000025 EXCEPTION_NONCONTINUABLE_EXCEPTION
0xC0000026 EXCEPTION_INVALID_DISPOSITION
0xC000008C EXCEPTION_ARRAY_BOUNDS_EXCEEDED
0xC000008D EXCEPTION_FLT_DENORMAL_OPERAND
0xC000008E EXCEPTION_FLT_DIVIDE_BY_ZERO
0xC000008F EXCEPTION_FLT_INEXACT_RESULT
0xC0000090 EXCEPTION_FLT_INVALID_OPERATION
0xC0000091 EXCEPTION_FLT_OVERFLOW
0xC0000092 EXCEPTION_FLT_STACK_CHECK
0xC0000093 EXCEPTION_FLT_UNDERFLOW
0xC0000094 EXCEPTION_INT_DIVIDE_BY_ZERO
0xC0000095 EXCEPTION_INT_OVERFLOW
0xC0000096 EXCEPTION_PRIV_INSTRUCTION
0xC00000FD EXCEPTION_STACK_OVERFLOW
0xC0000135 STATUS_DLL_NOT_FOUND
0xC0000138 STATUS_ORDINAL_NOT_FOUND
0xC0000139 STATUS_ENTRYPOINT_NOT_FOUND
0xC000013A STATUS_CONTROL_C_EXIT
0xC0000142 STATUS_DLL_INIT_FAILED
0xC000014A STATUS_ILLEGAL_FLOAT_CONTEXT
0xC0000194 EXCEPTION_POSSIBLE_DEADLOCK
0xC00001A5 STATUS_INVALID_EXCEPTION_HANDLER
0xC00002B4 STATUS_FLOAT_MULTIPLE_FAULTS
0xC00002B5 STATUS_FLOAT_MULTIPLE_TRAPS
0xC00002C5 STATUS_DATATYPE_MISALIGNMENT_ERROR
0xC00002C9 STATUS_REG_NAT_CONSUMPTION
0xC0000374 STATUS_HEAP_CORRUPTION
0xC0000409 STATUS_STACK_BUFFER_OVERRUN
0xC0000417 STATUS_INVALID_CRUNTIME_PARAMETER
0xC000041D STATUS_USER_CALLBACK
0xC0000420 STATUS_ASSERTION_FAILURE
0xC015000F STATUS_SXS_EARLY_DEACTIVATION
0xC0150010 STATUS_SXS_INVALID_DEACTIVATION
0xE0434352 CLR_EXCEPTION
0xE06D7363 CPP_EH_EXCEPTION
0xC06D0057 VCPP_EXCEPTION_ERROR_INVALID_PARAMETER
0xC06D007E VCPP_EXCEPTION_ERROR_MOD_NOT_FOUND
0xC06D007F VCPP_EXCEPTION_ERROR_PROC_NOT_FOUND |
JSON | x64dbg-development/bin/mnemdb.json | {
"__github_x86-64": "https://github.com/nologic/idaref/blob/master/x86-64.sql",
"__license_x86-64": "GPLv2",
"_github_x86-64-brief": "https://github.com/radareorg/radare2/blob/c4d416c7b96d2735c24a2f9e2787df3fdb764c71/libr/asm/d/x86.sdb.txt",
"_license_x86-64-brief": "GPLv3",
"x86-64": [
{
"description": "AAA-ASCII Adjust After Addition\r\nOpcode Instruction Op/ 64-bit Compat/ Description\r\n En Mode Leg Mode\r\n37 AAA NP Invalid Valid ASCII adjust AL after addition.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nAdjusts the sum of two unpacked BCD values to create an unpacked BCD result. The AL register is the implied\r\nsource and destination operand for this instruction. The AAA instruction is only useful when it follows an ADD\r\ninstruction that adds (binary addition) two unpacked BCD values and stores a byte result in the AL register. The\r\nAAA instruction then adjusts the contents of the AL register to contain the correct 1-digit unpacked BCD result.\r\nIf the addition produces a decimal carry, the AH register increments by 1, and the CF and AF flags are set. If there\r\nwas no decimal carry, the CF and AF flags are cleared and the AH register is unchanged. In either case, bits 4\r\nthrough 7 of the AL register are set to 0.\r\nThis instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.\r\n\r\nOperation\r\nIF 64-Bit Mode\r\n THEN\r\n #UD;\r\n ELSE\r\n IF ((AL AND 0FH) > 9) or (AF = 1)\r\n THEN\r\n AX <- AX + 106H;\r\n AF <- 1;\r\n CF <- 1;\r\n ELSE\r\n AF <- 0;\r\n CF <- 0;\r\n FI;\r\n AL <- AL AND 0FH;\r\nFI;\r\n\r\nFlags Affected\r\nThe AF and CF flags are set to 1 if the adjustment results in a decimal carry; otherwise they are set to 0. The OF,\r\nSF, ZF, and PF flags are undefined.\r\n\r\nProtected Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\n\r\n\r\n\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD If in 64-bit mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "AAA"
},
{
"description": "AAD-ASCII Adjust AX Before Division\r\nOpcode Instruction Op/ 64-bit Compat/ Description\r\n En Mode Leg Mode\r\nD5 0A AAD NP Invalid Valid ASCII adjust AX before division.\r\nD5 ib AAD imm8 NP Invalid Valid Adjust AX before division to number base\r\n imm8.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nAdjusts two unpacked BCD digits (the least-significant digit in the AL register and the most-significant digit in the\r\nAH register) so that a division operation performed on the result will yield a correct unpacked BCD value. The AAD\r\ninstruction is only useful when it precedes a DIV instruction that divides (binary division) the adjusted value in the\r\nAX register by an unpacked BCD value.\r\nThe AAD instruction sets the value in the AL register to (AL + (10 * AH)), and then clears the AH register to 00H.\r\nThe value in the AX register is then equal to the binary equivalent of the original unpacked two-digit (base 10)\r\nnumber in registers AH and AL.\r\nThe generalized version of this instruction allows adjustment of two unpacked digits of any number base (see the\r\n\"Operation\" section below), by setting the imm8 byte to the selected number base (for example, 08H for octal, 0AH\r\nfor decimal, or 0CH for base 12 numbers). The AAD mnemonic is interpreted by all assemblers to mean adjust\r\nASCII (base 10) values. To adjust values in another number base, the instruction must be hand coded in machine\r\ncode (D5 imm8).\r\nThis instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.\r\n\r\nOperation\r\nIF 64-Bit Mode\r\n THEN\r\n #UD;\r\n ELSE\r\n tempAL <- AL;\r\n tempAH <- AH;\r\n AL <- (tempAL + (tempAH * imm8)) AND FFH;\r\n (* imm8 is set to 0AH for the AAD mnemonic.*)\r\n AH <- 0;\r\nFI;\r\nThe immediate value (imm8) is taken from the second byte of the instruction.\r\n\r\nFlags Affected\r\nThe SF, ZF, and PF flags are set according to the resulting binary value in the AL register; the OF, AF, and CF flags\r\nare undefined.\r\n\r\nProtected Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD If in 64-bit mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "AAD"
},
{
"description": "AAM-ASCII Adjust AX After Multiply\r\nOpcode Instruction Op/ 64-bit Compat/ Description\r\n En Mode Leg Mode\r\nD4 0A AAM NP Invalid Valid ASCII adjust AX after multiply.\r\nD4 ib AAM imm8 NP Invalid Valid Adjust AX after multiply to number base\r\n imm8.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nAdjusts the result of the multiplication of two unpacked BCD values to create a pair of unpacked (base 10) BCD\r\nvalues. The AX register is the implied source and destination operand for this instruction. The AAM instruction is\r\nonly useful when it follows an MUL instruction that multiplies (binary multiplication) two unpacked BCD values and\r\nstores a word result in the AX register. The AAM instruction then adjusts the contents of the AX register to contain\r\nthe correct 2-digit unpacked (base 10) BCD result.\r\nThe generalized version of this instruction allows adjustment of the contents of the AX to create two unpacked\r\ndigits of any number base (see the \"Operation\" section below). Here, the imm8 byte is set to the selected number\r\nbase (for example, 08H for octal, 0AH for decimal, or 0CH for base 12 numbers). The AAM mnemonic is interpreted\r\nby all assemblers to mean adjust to ASCII (base 10) values. To adjust to values in another number base, the\r\ninstruction must be hand coded in machine code (D4 imm8).\r\nThis instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.\r\n\r\nOperation\r\nIF 64-Bit Mode\r\n THEN\r\n #UD;\r\n ELSE\r\n tempAL <- AL;\r\n AH <- tempAL / imm8; (* imm8 is set to 0AH for the AAM mnemonic *)\r\n AL <- tempAL MOD imm8;\r\nFI;\r\nThe immediate value (imm8) is taken from the second byte of the instruction.\r\n\r\nFlags Affected\r\nThe SF, ZF, and PF flags are set according to the resulting binary value in the AL register. The OF, AF, and CF flags\r\nare undefined.\r\n\r\nProtected Mode Exceptions\r\n#DE If an immediate value of 0 is used.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\n\r\n\r\n\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD If in 64-bit mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "AAM"
},
{
"description": "AAS-ASCII Adjust AL After Subtraction\r\nOpcode Instruction Op/ 64-bit Compat/ Description\r\n En Mode Leg Mode\r\n3F AAS NP Invalid Valid ASCII adjust AL after subtraction.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nAdjusts the result of the subtraction of two unpacked BCD values to create a unpacked BCD result. The AL register\r\nis the implied source and destination operand for this instruction. The AAS instruction is only useful when it follows\r\na SUB instruction that subtracts (binary subtraction) one unpacked BCD value from another and stores a byte\r\nresult in the AL register. The AAA instruction then adjusts the contents of the AL register to contain the correct 1-\r\ndigit unpacked BCD result.\r\nIf the subtraction produced a decimal carry, the AH register decrements by 1, and the CF and AF flags are set. If no\r\ndecimal carry occurred, the CF and AF flags are cleared, and the AH register is unchanged. In either case, the AL\r\nregister is left with its top four bits set to 0.\r\nThis instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.\r\n\r\nOperation\r\nIF 64-bit mode\r\n THEN\r\n #UD;\r\n ELSE\r\n IF ((AL AND 0FH) > 9) or (AF = 1)\r\n THEN\r\n AX <- AX - 6;\r\n AH <- AH - 1;\r\n AF <- 1;\r\n CF <- 1;\r\n AL <- AL AND 0FH;\r\n ELSE\r\n CF <- 0;\r\n AF <- 0;\r\n AL <- AL AND 0FH;\r\n FI;\r\nFI;\r\n\r\nFlags Affected\r\nThe AF and CF flags are set to 1 if there is a decimal borrow; otherwise, they are cleared to 0. The OF, SF, ZF, and\r\nPF flags are undefined.\r\n\r\nProtected Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD If in 64-bit mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "AAS"
},
{
"description": "ADC-Add with Carry\r\nOpcode Instruction Op/ 64-bit Compat/ Description\r\n En Mode Leg Mode\r\n14 ib ADC AL, imm8 I Valid Valid Add with carry imm8 to AL.\r\n15 iw ADC AX, imm16 I Valid Valid Add with carry imm16 to AX.\r\n15 id ADC EAX, imm32 I Valid Valid Add with carry imm32 to EAX.\r\nREX.W + 15 id ADC RAX, imm32 I Valid N.E. Add with carry imm32 sign extended to 64-\r\n bits to RAX.\r\n80 /2 ib ADC r/m8, imm8 MI Valid Valid Add with carry imm8 to r/m8.\r\n *\r\nREX + 80 /2 ib ADC r/m8 , imm8 MI Valid N.E. Add with carry imm8 to r/m8.\r\n81 /2 iw ADC r/m16, imm16 MI Valid Valid Add with carry imm16 to r/m16.\r\n81 /2 id ADC r/m32, imm32 MI Valid Valid Add with CF imm32 to r/m32.\r\nREX.W + 81 /2 id ADC r/m64, imm32 MI Valid N.E. Add with CF imm32 sign extended to 64-bits\r\n to r/m64.\r\n83 /2 ib ADC r/m16, imm8 MI Valid Valid Add with CF sign-extended imm8 to r/m16.\r\n83 /2 ib ADC r/m32, imm8 MI Valid Valid Add with CF sign-extended imm8 into r/m32.\r\nREX.W + 83 /2 ib ADC r/m64, imm8 MI Valid N.E. Add with CF sign-extended imm8 into r/m64.\r\n10 /r ADC r/m8, r8 MR Valid Valid Add with carry byte register to r/m8.\r\nREX + 10 /r ADC r/m8*, r8* MR Valid N.E. Add with carry byte register to r/m64.\r\n11 /r ADC r/m16, r16 MR Valid Valid Add with carry r16 to r/m16.\r\n11 /r ADC r/m32, r32 MR Valid Valid Add with CF r32 to r/m32.\r\nREX.W + 11 /r ADC r/m64, r64 MR Valid N.E. Add with CF r64 to r/m64.\r\n12 /r ADC r8, r/m8 RM Valid Valid Add with carry r/m8 to byte register.\r\nREX + 12 /r ADC r8*, r/m8* RM Valid N.E. Add with carry r/m64 to byte register.\r\n13 /r ADC r16, r/m16 RM Valid Valid Add with carry r/m16 to r16.\r\n13 /r ADC r32, r/m32 RM Valid Valid Add with CF r/m32 to r32.\r\nREX.W + 13 /r ADC r64, r/m64 RM Valid N.E. Add with CF r/m64 to r64.\r\nNOTES:\r\n*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n MR ModRM:r/m (r, w) ModRM:reg (r) NA NA\r\n MI ModRM:r/m (r, w) imm8 NA NA\r\n I AL/AX/EAX/RAX imm8 NA NA\r\n\r\nDescription\r\nAdds the destination operand (first operand), the source operand (second operand), and the carry (CF) flag and\r\nstores the result in the destination operand. The destination operand can be a register or a memory location; the\r\nsource operand can be an immediate, a register, or a memory location. (However, two memory operands cannot be\r\nused in one instruction.) The state of the CF flag represents a carry from a previous addition. When an immediate\r\nvalue is used as an operand, it is sign-extended to the length of the destination operand format.\r\n\r\n\r\n\r\n\r\n\r\nThe ADC instruction does not distinguish between signed or unsigned operands. Instead, the processor evaluates\r\nthe result for both data types and sets the OF and CF flags to indicate a carry in the signed or unsigned result,\r\nrespectively. The SF flag indicates the sign of the signed result.\r\nThe ADC instruction is usually executed as part of a multibyte or multiword addition in which an ADD instruction is\r\nfollowed by an ADC instruction.\r\nThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nDEST <- DEST + SRC + CF;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nADC: extern unsigned char _addcarry_u8(unsigned char c_in, unsigned char src1, unsigned char src2, unsigned char *sum_out);\r\n\r\nADC: extern unsigned char _addcarry_u16(unsigned char c_in, unsigned short src1, unsigned short src2, unsigned short\r\n*sum_out);\r\n\r\nADC: extern unsigned char _addcarry_u32(unsigned char c_in, unsigned int src1, unsigned char int, unsigned int *sum_out);\r\n\r\nADC: extern unsigned char _addcarry_u64(unsigned char c_in, unsigned __int64 src1, unsigned __int64 src2, unsigned __int64\r\n*sum_out);\r\n\r\nFlags Affected\r\nThe OF, SF, ZF, AF, CF, and PF flags are set according to the result.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination is located in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n",
"mnem": "ADC"
},
{
"description": "ADCX - Unsigned Integer Addition of Two Operands with Carry Flag\r\n Opcode/ Op/ 64/32bit CPUID Description\r\n Instruction En Mode Feature\r\n Support Flag\r\n 66 0F 38 F6 /r RM V/V ADX Unsigned addition of r32 with CF, r/m32 to r32, writes CF.\r\n ADCX r32, r/m32\r\n 66 REX.w 0F 38 F6 /r RM V/NE ADX Unsigned addition of r64 with CF, r/m64 to r64, writes CF.\r\n ADCX r64, r/m64\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nPerforms an unsigned addition of the destination operand (first operand), the source operand (second operand)\r\nand the carry-flag (CF) and stores the result in the destination operand. The destination operand is a general-\r\npurpose register, whereas the source operand can be a general-purpose register or memory location. The state of\r\nCF can represent a carry from a previous addition. The instruction sets the CF flag with the carry generated by the\r\nunsigned addition of the operands.\r\nThe ADCX instruction is executed in the context of multi-precision addition, where we add a series of operands with\r\na carry-chain. At the beginning of a chain of additions, we need to make sure the CF is in a desired initial state.\r\nOften, this initial state needs to be 0, which can be achieved with an instruction to zero the CF (e.g. XOR).\r\nThis instruction is supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-\r\nbit mode.\r\nIn 64-bit mode, the default operation size is 32 bits. Using a REX Prefix in the form of REX.R permits access to addi-\r\ntional registers (R8-15). Using REX Prefix in the form of REX.W promotes operation to 64 bits.\r\nADCX executes normally either inside or outside a transaction region.\r\nNote: ADCX defines the OF flag differently than the ADD/ADC instructions as defined in Intel 64 and IA-32 Archi-\r\ntectures Software Developer's Manual, Volume 2A.\r\n\r\nOperation\r\nIF OperandSize is 64-bit\r\n THEN CF:DEST[63:0] <- DEST[63:0] + SRC[63:0] + CF;\r\n ELSE CF:DEST[31:0] <- DEST[31:0] + SRC[31:0] + CF;\r\nFI;\r\n\r\nFlags Affected\r\nCF is updated based on result. OF, SF, ZF, AF and PF flags are unmodified.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nunsigned char _addcarryx_u32 (unsigned char c_in, unsigned int src1, unsigned int src2, unsigned int *sum_out);\r\nunsigned char _addcarryx_u64 (unsigned char c_in, unsigned __int64 src1, unsigned __int64 src2, unsigned __int64 *sum_out);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.\r\n#SS(0) For an illegal address in the SS segment.\r\n\r\n\r\n\r\n#GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a null segment\r\n selector.\r\n#PF(fault-code) For a page fault.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n\r\nReal-Address Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.\r\n#SS(0) For an illegal address in the SS segment.\r\n#GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.\r\n#SS(0) For an illegal address in the SS segment.\r\n#GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH.\r\n#PF(fault-code) For a page fault.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) For a page fault.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "ADCX"
},
{
"description": "ADD-Add\r\nOpcode Instruction Op/ 64-bit Compat/ Description\r\n En Mode Leg Mode\r\n04 ib ADD AL, imm8 I Valid Valid Add imm8 to AL.\r\n05 iw ADD AX, imm16 I Valid Valid Add imm16 to AX.\r\n05 id ADD EAX, imm32 I Valid Valid Add imm32 to EAX.\r\nREX.W + 05 id ADD RAX, imm32 I Valid N.E. Add imm32 sign-extended to 64-bits to RAX.\r\n80 /0 ib ADD r/m8, imm8 MI Valid Valid Add imm8 to r/m8.\r\nREX + 80 /0 ib ADD r/m8*, imm8 MI Valid N.E. Add sign-extended imm8 to r/m64.\r\n81 /0 iw ADD r/m16, imm16 MI Valid Valid Add imm16 to r/m16.\r\n81 /0 id ADD r/m32, imm32 MI Valid Valid Add imm32 to r/m32.\r\nREX.W + 81 /0 id ADD r/m64, imm32 MI Valid N.E. Add imm32 sign-extended to 64-bits to\r\n r/m64.\r\n83 /0 ib ADD r/m16, imm8 MI Valid Valid Add sign-extended imm8 to r/m16.\r\n83 /0 ib ADD r/m32, imm8 MI Valid Valid Add sign-extended imm8 to r/m32.\r\nREX.W + 83 /0 ib ADD r/m64, imm8 MI Valid N.E. Add sign-extended imm8 to r/m64.\r\n00 /r ADD r/m8, r8 MR Valid Valid Add r8 to r/m8.\r\n * *\r\nREX + 00 /r ADD r/m8 , r8 MR Valid N.E. Add r8 to r/m8.\r\n01 /r ADD r/m16, r16 MR Valid Valid Add r16 to r/m16.\r\n01 /r ADD r/m32, r32 MR Valid Valid Add r32 to r/m32.\r\nREX.W + 01 /r ADD r/m64, r64 MR Valid N.E. Add r64 to r/m64.\r\n02 /r ADD r8, r/m8 RM Valid Valid Add r/m8 to r8.\r\n * *\r\nREX + 02 /r ADD r8 , r/m8 RM Valid N.E. Add r/m8 to r8.\r\n03 /r ADD r16, r/m16 RM Valid Valid Add r/m16 to r16.\r\n03 /r ADD r32, r/m32 RM Valid Valid Add r/m32 to r32.\r\nREX.W + 03 /r ADD r64, r/m64 RM Valid N.E. Add r/m64 to r64.\r\nNOTES:\r\n*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n MR ModRM:r/m (r, w) ModRM:reg (r) NA NA\r\n MI ModRM:r/m (r, w) imm8 NA NA\r\n I AL/AX/EAX/RAX imm8 NA NA\r\n\r\nDescription\r\nAdds the destination operand (first operand) and the source operand (second operand) and then stores the result\r\nin the destination operand. The destination operand can be a register or a memory location; the source operand\r\ncan be an immediate, a register, or a memory location. (However, two memory operands cannot be used in one\r\ninstruction.) When an immediate value is used as an operand, it is sign-extended to the length of the destination\r\noperand format.\r\nThe ADD instruction performs integer addition. It evaluates the result for both signed and unsigned integer oper-\r\nands and sets the CF and OF flags to indicate a carry (overflow) in the signed or unsigned result, respectively. The\r\nSF flag indicates the sign of the signed result.\r\n\r\n\r\n\r\nThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nDEST <- DEST + SRC;\r\n\r\nFlags Affected\r\nThe OF, SF, ZF, AF, CF, and PF flags are set according to the result.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination is located in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n",
"mnem": "ADD"
},
{
"description": "ADDPD-Add Packed Double-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0F 58 /r RM V/V SSE2 Add packed double-precision floating-point values from\r\n ADDPD xmm1, xmm2/m128 xmm2/mem to xmm1 and store result in xmm1.\r\n VEX.NDS.128.66.0F.WIG 58 /r RVM V/V AVX Add packed double-precision floating-point values from\r\n VADDPD xmm1,xmm2, xmm3/mem to xmm2 and store result in xmm1.\r\n xmm3/m128\r\n VEX.NDS.256.66.0F.WIG 58 /r RVM V/V AVX Add packed double-precision floating-point values from\r\n VADDPD ymm1, ymm2, ymm3/mem to ymm2 and store result in ymm1.\r\n ymm3/m256\r\n EVEX.NDS.128.66.0F.W1 58 /r FV V/V AVX512VL Add packed double-precision floating-point values from\r\n VADDPD xmm1 {k1}{z}, xmm2, AVX512F xmm3/m128/m64bcst to xmm2 and store result in xmm1\r\n xmm3/m128/m64bcst with writemask k1.\r\n EVEX.NDS.256.66.0F.W1 58 /r FV V/V AVX512VL Add packed double-precision floating-point values from\r\n VADDPD ymm1 {k1}{z}, ymm2, AVX512F ymm3/m256/m64bcst to ymm2 and store result in ymm1\r\n ymm3/m256/m64bcst with writemask k1.\r\n EVEX.NDS.512.66.0F.W1 58 /r FV V/V AVX512F Add packed double-precision floating-point values from\r\n VADDPD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst to zmm2 and store result in zmm1\r\n zmm3/m512/m64bcst{er} with writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n FV-RVM ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nAdd two, four or eight packed double-precision floating-point values from the first source operand to the second\r\nsource operand, and stores the packed double-precision floating-point results in the destination operand.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be\r\na ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a\r\n64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with\r\nwritemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)\r\nof the corresponding ZMM register destination are zeroed.\r\nVEX.128 encoded version: the first source operand is a XMM register. The second source operand is an XMM\r\nregister or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper Bits (MAX_VL-1:128) of the corresponding\r\nZMM register destination are unmodified.\r\n\r\nOperation\r\nVADDPD (EVEX encoded versions) when src2 operand is a vector register\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n\r\n\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- SRC1[i+63:i] + SRC2[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVADDPD (EVEX encoded versions) when src2 operand is a memory source\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+63:i] <- SRC1[i+63:i] + SRC2[63:0]\r\n ELSE\r\n DEST[i+63:i] <- SRC1[i+63:i] + SRC2[i+63:i]\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVADDPD (VEX.256 encoded version)\r\nDEST[63:0] <- SRC1[63:0] + SRC2[63:0]\r\nDEST[127:64] <- SRC1[127:64] + SRC2[127:64]\r\nDEST[191:128] <- SRC1[191:128] + SRC2[191:128]\r\nDEST[255:192] <- SRC1[255:192] + SRC2[255:192]\r\nDEST[MAX_VL-1:256] <- 0\r\n.\r\n\r\n\r\n\r\n\r\n\r\nVADDPD (VEX.128 encoded version)\r\nDEST[63:0] <- SRC1[63:0] + SRC2[63:0]\r\nDEST[127:64] <- SRC1[127:64] + SRC2[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nADDPD (128-bit Legacy SSE version)\r\nDEST[63:0] <- DEST[63:0] + SRC[63:0]\r\nDEST[127:64] <- DEST[127:64] + SRC[127:64]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVADDPD __m512d _mm512_add_pd (__m512d a, __m512d b);\r\nVADDPD __m512d _mm512_mask_add_pd (__m512d s, __mmask8 k, __m512d a, __m512d b);\r\nVADDPD __m512d _mm512_maskz_add_pd (__mmask8 k, __m512d a, __m512d b);\r\nVADDPD __m256d _mm256_mask_add_pd (__m256d s, __mmask8 k, __m256d a, __m256d b);\r\nVADDPD __m256d _mm256_maskz_add_pd (__mmask8 k, __m256d a, __m256d b);\r\nVADDPD __m128d _mm_mask_add_pd (__m128d s, __mmask8 k, __m128d a, __m128d b);\r\nVADDPD __m128d _mm_maskz_add_pd (__mmask8 k, __m128d a, __m128d b);\r\nVADDPD __m512d _mm512_add_round_pd (__m512d a, __m512d b, int);\r\nVADDPD __m512d _mm512_mask_add_round_pd (__m512d s, __mmask8 k, __m512d a, __m512d b, int);\r\nVADDPD __m512d _mm512_maskz_add_round_pd (__mmask8 k, __m512d a, __m512d b, int);\r\nADDPD __m256d _mm256_add_pd (__m256d a, __m256d b);\r\nADDPD __m128d _mm_add_pd (__m128d a, __m128d b);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instruction, see Exceptions Type 2.\r\nEVEX-encoded instruction, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "ADDPD"
},
{
"description": "ADDPS-Add Packed Single-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 0F 58 /r RM V/V SSE Add packed single-precision floating-point values from\r\n ADDPS xmm1, xmm2/m128 xmm2/m128 to xmm1 and store result in xmm1.\r\n VEX.NDS.128.0F.WIG 58 /r RVM V/V AVX Add packed single-precision floating-point values from\r\n VADDPS xmm1,xmm2, xmm3/m128 xmm3/m128 to xmm2 and store result in xmm1.\r\n VEX.NDS.256.0F.WIG 58 /r RVM V/V AVX Add packed single-precision floating-point values from\r\n VADDPS ymm1, ymm2, ymm3/m256 ymm3/m256 to ymm2 and store result in ymm1.\r\n EVEX.NDS.128.0F.W0 58 /r FV V/V AVX512VL Add packed single-precision floating-point values from\r\n VADDPS xmm1 {k1}{z}, xmm2, AVX512F xmm3/m128/m32bcst to xmm2 and store result in\r\n xmm3/m128/m32bcst xmm1 with writemask k1.\r\n EVEX.NDS.256.0F.W0 58 /r FV V/V AVX512VL Add packed single-precision floating-point values from\r\n VADDPS ymm1 {k1}{z}, ymm2, AVX512F ymm3/m256/m32bcst to ymm2 and store result in\r\n ymm3/m256/m32bcst ymm1 with writemask k1.\r\n EVEX.NDS.512.0F.W0 58 /r FV V/V AVX512F Add packed single-precision floating-point values from\r\n VADDPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst to zmm2 and store result in\r\n zmm3/m512/m32bcst {er} zmm1 with writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n FV-RVM ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nAdd four, eight or sixteen packed single-precision floating-point values from the first source operand with the\r\nsecond source operand, and stores the packed single-precision floating-point results in the destination operand.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be\r\na ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a\r\n32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with\r\nwritemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)\r\nof the corresponding ZMM register destination are zeroed.\r\nVEX.128 encoded version: the first source operand is a XMM register. The second source operand is an XMM\r\nregister or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper Bits (MAX_VL-1:128) of the corresponding\r\nZMM register destination are unmodified.\r\n\r\nOperation\r\nVADDPS (EVEX encoded versions) when src2 operand is a register\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\n\r\n\r\n\r\n\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- SRC1[i+31:i] + SRC2[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVADDPS (EVEX encoded versions) when src2 operand is a memory source\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <-j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <- SRC1[i+31:i] + SRC2[31:0]\r\n ELSE\r\n DEST[i+31:i] <- SRC1[i+31:i] + SRC2[i+31:i]\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVADDPS (VEX.256 encoded version)\r\nDEST[31:0] <- SRC1[31:0] + SRC2[31:0]\r\nDEST[63:32] <- SRC1[63:32] + SRC2[63:32]\r\nDEST[95:64] <- SRC1[95:64] + SRC2[95:64]\r\nDEST[127:96] <- SRC1[127:96] + SRC2[127:96]\r\nDEST[159:128] <- SRC1[159:128] + SRC2[159:128]\r\nDEST[191:160]<- SRC1[191:160] + SRC2[191:160]\r\nDEST[223:192] <- SRC1[223:192] + SRC2[223:192]\r\nDEST[255:224] <- SRC1[255:224] + SRC2[255:224].\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVADDPS (VEX.128 encoded version)\r\nDEST[31:0] <- SRC1[31:0] + SRC2[31:0]\r\nDEST[63:32] <- SRC1[63:32] + SRC2[63:32]\r\nDEST[95:64] <- SRC1[95:64] + SRC2[95:64]\r\nDEST[127:96] <- SRC1[127:96] + SRC2[127:96]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nADDPS (128-bit Legacy SSE version)\r\nDEST[31:0] <- SRC1[31:0] + SRC2[31:0]\r\nDEST[63:32] <- SRC1[63:32] + SRC2[63:32]\r\nDEST[95:64] <- SRC1[95:64] + SRC2[95:64]\r\nDEST[127:96] <- SRC1[127:96] + SRC2[127:96]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVADDPS __m512 _mm512_add_ps (__m512 a, __m512 b);\r\nVADDPS __m512 _mm512_mask_add_ps (__m512 s, __mmask16 k, __m512 a, __m512 b);\r\nVADDPS __m512 _mm512_maskz_add_ps (__mmask16 k, __m512 a, __m512 b);\r\nVADDPS __m256 _mm256_mask_add_ps (__m256 s, __mmask8 k, __m256 a, __m256 b);\r\nVADDPS __m256 _mm256_maskz_add_ps (__mmask8 k, __m256 a, __m256 b);\r\nVADDPS __m128 _mm_mask_add_ps (__m128d s, __mmask8 k, __m128 a, __m128 b);\r\nVADDPS __m128 _mm_maskz_add_ps (__mmask8 k, __m128 a, __m128 b);\r\nVADDPS __m512 _mm512_add_round_ps (__m512 a, __m512 b, int);\r\nVADDPS __m512 _mm512_mask_add_round_ps (__m512 s, __mmask16 k, __m512 a, __m512 b, int);\r\nVADDPS __m512 _mm512_maskz_add_round_ps (__mmask16 k, __m512 a, __m512 b, int);\r\nADDPS __m256 _mm256_add_ps (__m256 a, __m256 b);\r\nADDPS __m128 _mm_add_ps (__m128 a, __m128 b);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instruction, see Exceptions Type 2.\r\nEVEX-encoded instruction, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "ADDPS"
},
{
"description": "ADDSD-Add Scalar Double-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n F2 0F 58 /r RM V/V SSE2 Add the low double-precision floating-point value from\r\n ADDSD xmm1, xmm2/m64 xmm2/mem to xmm1 and store the result in xmm1.\r\n VEX.NDS.128.F2.0F.WIG 58 /r RVM V/V AVX Add the low double-precision floating-point value from\r\n VADDSD xmm1, xmm2, xmm3/mem to xmm2 and store the result in xmm1.\r\n xmm3/m64\r\n EVEX.NDS.LIG.F2.0F.W1 58 /r T1S V/V AVX512F Add the low double-precision floating-point value from\r\n VADDSD xmm1 {k1}{z}, xmm3/m64 to xmm2 and store the result in xmm1 with\r\n xmm2, xmm3/m64{er} writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n T1S-RVM ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nAdds the low double-precision floating-point values from the second source operand and the first source operand\r\nand stores the double-precision floating-point result in the destination operand.\r\nThe second source operand can be an XMM register or a 64-bit memory location. The first source and destination\r\noperands are XMM registers.\r\n128-bit Legacy SSE version: The first source and destination operands are the same. Bits (MAX_VL-1:64) of the\r\ncorresponding destination register remain unchanged.\r\nEVEX and VEX.128 encoded version: The first source operand is encoded by EVEX.vvvv/VEX.vvvv. Bits (127:64) of\r\nthe XMM register destination are copied from corresponding bits in the first source operand. Bits (MAX_VL-1:128)\r\nof the destination register are zeroed.\r\nEVEX version: The low quadword element of the destination is updated according to the writemask.\r\nSoftware should ensure VADDSD is encoded with VEX.L=0. Encoding VADDSD with VEX.L=1 may encounter\r\nunpredictable behavior across different processor generations.\r\n\r\nOperation\r\nVADDSD (EVEX encoded version)\r\nIF (EVEX.b = 1) AND SRC2 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[63:0] <- SRC1[63:0] + SRC2[63:0]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[63:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:64] <- SRC1[127:64]\r\n\r\n\r\n\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVADDSD (VEX.128 encoded version)\r\nDEST[63:0] <-SRC1[63:0] + SRC2[63:0]\r\nDEST[127:64] <-SRC1[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nADDSD (128-bit Legacy SSE version)\r\nDEST[63:0] <-DEST[63:0] + SRC[63:0]\r\nDEST[MAX_VL-1:64] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVADDSD __m128d _mm_mask_add_sd (__m128d s, __mmask8 k, __m128d a, __m128d b);\r\nVADDSD __m128d _mm_maskz_add_sd (__mmask8 k, __m128d a, __m128d b);\r\nVADDSD __m128d _mm_add_round_sd (__m128d a, __m128d b, int);\r\nVADDSD __m128d _mm_mask_add_round_sd (__m128d s, __mmask8 k, __m128d a, __m128d b, int);\r\nVADDSD __m128d _mm_maskz_add_round_sd (__mmask8 k, __m128d a, __m128d b, int);\r\nADDSD __m128d _mm_add_sd (__m128d a, __m128d b);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instruction, see Exceptions Type 3.\r\nEVEX-encoded instruction, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "ADDSD"
},
{
"description": "ADDSS-Add Scalar Single-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n F3 0F 58 /r RM V/V SSE Add the low single-precision floating-point value from\r\n ADDSS xmm1, xmm2/m32 xmm2/mem to xmm1 and store the result in xmm1.\r\n VEX.NDS.128.F3.0F.WIG 58 /r RVM V/V AVX Add the low single-precision floating-point value from\r\n VADDSS xmm1,xmm2, xmm3/mem to xmm2 and store the result in xmm1.\r\n xmm3/m32\r\n EVEX.NDS.LIG.F3.0F.W0 58 /r T1S V/V AVX512F Add the low single-precision floating-point value from\r\n VADDSS xmm1{k1}{z}, xmm2, xmm3/m32 to xmm2 and store the result in xmm1with\r\n xmm3/m32{er} writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n T1S ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nAdds the low single-precision floating-point values from the second source operand and the first source operand,\r\nand stores the double-precision floating-point result in the destination operand.\r\nThe second source operand can be an XMM register or a 64-bit memory location. The first source and destination\r\noperands are XMM registers.\r\n128-bit Legacy SSE version: The first source and destination operands are the same. Bits (MAX_VL-1:32) of the\r\ncorresponding the destination register remain unchanged.\r\nEVEX and VEX.128 encoded version: The first source operand is encoded by EVEX.vvvv/VEX.vvvv. Bits (127:32) of\r\nthe XMM register destination are copied from corresponding bits in the first source operand. Bits (MAX_VL-1:128)\r\nof the destination register are zeroed.\r\nEVEX version: The low doubleword element of the destination is updated according to the writemask.\r\nSoftware should ensure VADDSS is encoded with VEX.L=0. Encoding VADDSS with VEX.L=1 may encounter unpre-\r\ndictable behavior across different processor generations.\r\n\r\nOperation\r\nVADDSS (EVEX encoded versions)\r\nIF (EVEX.b = 1) AND SRC2 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[31:0] <- SRC1[31:0] + SRC2[31:0]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[31:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:32] <- SRC1[127:32]\r\n\r\n\r\n\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVADDSS DEST, SRC1, SRC2 (VEX.128 encoded version)\r\nDEST[31:0] <-SRC1[31:0] + SRC2[31:0]\r\nDEST[127:32] <-SRC1[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nADDSS DEST, SRC (128-bit Legacy SSE version)\r\nDEST[31:0] <-DEST[31:0] + SRC[31:0]\r\nDEST[MAX_VL-1:32] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVADDSS __m128 _mm_mask_add_ss (__m128 s, __mmask8 k, __m128 a, __m128 b);\r\nVADDSS __m128 _mm_maskz_add_ss (__mmask8 k, __m128 a, __m128 b);\r\nVADDSS __m128 _mm_add_round_ss (__m128 a, __m128 b, int);\r\nVADDSS __m128 _mm_mask_add_round_ss (__m128 s, __mmask8 k, __m128 a, __m128 b, int);\r\nVADDSS __m128 _mm_maskz_add_round_ss (__mmask8 k, __m128 a, __m128 b, int);\r\nADDSS __m128 _mm_add_ss (__m128 a, __m128 b);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instruction, see Exceptions Type 3.\r\nEVEX-encoded instruction, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "ADDSS"
},
{
"description": "ADDSUBPD-Packed Double-FP Add/Subtract\r\nOpcode/ Op/ 64/32-bit CPUID Description\r\nInstruction En Mode Feature\r\n Flag\r\n66 0F D0 /r RM V/V SSE3 Add/subtract double-precision floating-point\r\nADDSUBPD xmm1, xmm2/m128 values from xmm2/m128 to xmm1.\r\n\r\nVEX.NDS.128.66.0F.WIG D0 /r RVM V/V AVX Add/subtract packed double-precision\r\nVADDSUBPD xmm1, xmm2, xmm3/m128 floating-point values from xmm3/mem to\r\n xmm2 and stores result in xmm1.\r\nVEX.NDS.256.66.0F.WIG D0 /r RVM V/V AVX Add / subtract packed double-precision\r\nVADDSUBPD ymm1, ymm2, ymm3/m256 floating-point values from ymm3/mem to\r\n ymm2 and stores result in ymm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nAdds odd-numbered double-precision floating-point values of the first source operand (second operand) with the\r\ncorresponding double-precision floating-point values from the second source operand (third operand); stores the\r\nresult in the odd-numbered values of the destination operand (first operand). Subtracts the even-numbered\r\ndouble-precision floating-point values from the second source operand from the corresponding double-precision\r\nfloating values in the first source operand; stores the result into the even-numbered values of the destination\r\noperand.\r\nIn 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers\r\n(XMM8-XMM15).\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding\r\nYMM register destination are unmodified. See Figure 3-3.\r\nVEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination\r\noperand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are\r\nzeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register.\r\n\r\n\r\n\r\n\r\n\r\n ADDSUBPD xmm1, xmm2/m128\r\n\r\n\r\n [127:64] [63:0] xmm2/m128\r\n\r\n\r\n\r\n\r\n RESULT:\r\n xmm1[127:64] + xmm2/m128[127:64] xmm1[63:0] - xmm2/m128[63:0]\r\n xmm1\r\n\r\n [127:64] [63:0]\r\n\r\n\r\n\r\n Figure 3-3. ADDSUBPD-Packed Double-FP Add/Subtract\r\n\r\n\r\nOperation\r\nADDSUBPD (128-bit Legacy SSE version)\r\nDEST[63:0] <- DEST[63:0] - SRC[63:0]\r\nDEST[127:64] <- DEST[127:64] + SRC[127:64]\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVADDSUBPD (VEX.128 encoded version)\r\nDEST[63:0] <- SRC1[63:0] - SRC2[63:0]\r\nDEST[127:64] <- SRC1[127:64] + SRC2[127:64]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVADDSUBPD (VEX.256 encoded version)\r\nDEST[63:0] <- SRC1[63:0] - SRC2[63:0]\r\nDEST[127:64] <- SRC1[127:64] + SRC2[127:64]\r\nDEST[191:128] <- SRC1[191:128] - SRC2[191:128]\r\nDEST[255:192] <- SRC1[255:192] + SRC2[255:192]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nADDSUBPD: __m128d _mm_addsub_pd(__m128d a, __m128d b)\r\n\r\nVADDSUBPD: __m256d _mm256_addsub_pd (__m256d a, __m256d b)\r\n\r\nExceptions\r\nWhen the source operand is a memory operand, it must be aligned on a 16-byte boundary or a general-protection\r\nexception (#GP) will be generated.\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "ADDSUBPD"
},
{
"description": "ADDSUBPS-Packed Single-FP Add/Subtract\r\n Opcode/ Op/ 64/32-bit CPUID Description\r\n Instruction En Mode Feature\r\n Flag\r\n F2 0F D0 /r RM V/V SSE3 Add/subtract single-precision floating-point\r\n ADDSUBPS xmm1, xmm2/m128 values from xmm2/m128 to xmm1.\r\n\r\n VEX.NDS.128.F2.0F.WIG D0 /r RVM V/V AVX Add/subtract single-precision floating-point\r\n VADDSUBPS xmm1, xmm2, xmm3/m128 values from xmm3/mem to xmm2 and stores\r\n result in xmm1.\r\n VEX.NDS.256.F2.0F.WIG D0 /r RVM V/V AVX Add / subtract single-precision floating-point\r\n VADDSUBPS ymm1, ymm2, ymm3/m256 values from ymm3/mem to ymm2 and stores\r\n result in ymm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nAdds odd-numbered single-precision floating-point values of the first source operand (second operand) with the\r\ncorresponding single-precision floating-point values from the second source operand (third operand); stores the\r\nresult in the odd-numbered values of the destination operand (first operand). Subtracts the even-numbered\r\nsingle-precision floating-point values from the second source operand from the corresponding single-precision\r\nfloating values in the first source operand; stores the result into the even-numbered values of the destination\r\noperand.\r\nIn 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers\r\n(XMM8-XMM15).\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding\r\nYMM register destination are unmodified. See Figure 3-4.\r\nVEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination\r\noperand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are\r\nzeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register.\r\n\r\n\r\n\r\n\r\n\r\n ADDSUBPS xmm1, xmm2/m128\r\n\r\n xmm2/\r\n [127:96] [95:64] [63:32] [31:0]\r\n m128\r\n\r\n\r\n\r\n\r\n xmm1[127:96] + xmm1[95:64] - xmm2/ xmm1[63:32] + xmm1[31:0] - RESULT:\r\n xmm2/m128[127:96] m128[95:64] xmm2/m128[63:32] xmm2/m128[31:0] xmm1\r\n\r\n [127:96] [95:64] [63:32] [31:0]\r\n\r\n\r\n OM15992\r\n\r\n\r\n\r\n Figure 3-4. ADDSUBPS-Packed Single-FP Add/Subtract\r\n\r\n\r\nOperation\r\nADDSUBPS (128-bit Legacy SSE version)\r\nDEST[31:0] <- DEST[31:0] - SRC[31:0]\r\nDEST[63:32] <- DEST[63:32] + SRC[63:32]\r\nDEST[95:64] <- DEST[95:64] - SRC[95:64]\r\nDEST[127:96] <- DEST[127:96] + SRC[127:96]\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVADDSUBPS (VEX.128 encoded version)\r\nDEST[31:0] <- SRC1[31:0] - SRC2[31:0]\r\nDEST[63:32] <- SRC1[63:32] + SRC2[63:32]\r\nDEST[95:64] <- SRC1[95:64] - SRC2[95:64]\r\nDEST[127:96] <- SRC1[127:96] + SRC2[127:96]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVADDSUBPS (VEX.256 encoded version)\r\nDEST[31:0] <- SRC1[31:0] - SRC2[31:0]\r\nDEST[63:32] <- SRC1[63:32] + SRC2[63:32]\r\nDEST[95:64] <- SRC1[95:64] - SRC2[95:64]\r\nDEST[127:96] <- SRC1[127:96] + SRC2[127:96]\r\nDEST[159:128] <- SRC1[159:128] - SRC2[159:128]\r\nDEST[191:160]<- SRC1[191:160] + SRC2[191:160]\r\nDEST[223:192] <- SRC1[223:192] - SRC2[223:192]\r\nDEST[255:224] <- SRC1[255:224] + SRC2[255:224].\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nADDSUBPS: __m128 _mm_addsub_ps(__m128 a, __m128 b)\r\n\r\nVADDSUBPS: __m256 _mm256_addsub_ps (__m256 a, __m256 b)\r\n\r\nExceptions\r\nWhen the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-\r\nprotection exception (#GP) will be generated.\r\n\r\n\r\n\r\n\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "ADDSUBPS"
},
{
"description": "ADOX - Unsigned Integer Addition of Two Operands with Overflow Flag\r\n Opcode/ Op/ 64/32bit CPUID Description\r\n Instruction En Mode Feature\r\n Support Flag\r\n F3 0F 38 F6 /r RM V/V ADX Unsigned addition of r32 with OF, r/m32 to r32, writes OF.\r\n ADOX r32, r/m32\r\n F3 REX.w 0F 38 F6 /r RM V/NE ADX Unsigned addition of r64 with OF, r/m64 to r64, writes OF.\r\n ADOX r64, r/m64\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nPerforms an unsigned addition of the destination operand (first operand), the source operand (second operand)\r\nand the overflow-flag (OF) and stores the result in the destination operand. The destination operand is a general-\r\npurpose register, whereas the source operand can be a general-purpose register or memory location. The state of\r\nOF represents a carry from a previous addition. The instruction sets the OF flag with the carry generated by the\r\nunsigned addition of the operands.\r\nThe ADOX instruction is executed in the context of multi-precision addition, where we add a series of operands with\r\na carry-chain. At the beginning of a chain of additions, we execute an instruction to zero the OF (e.g. XOR).\r\nThis instruction is supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit\r\nmode.\r\nIn 64-bit mode, the default operation size is 32 bits. Using a REX Prefix in the form of REX.R permits access to addi-\r\ntional registers (R8-15). Using REX Prefix in the form of REX.W promotes operation to 64-bits.\r\nADOX executes normally either inside or outside a transaction region.\r\nNote: ADOX defines the CF and OF flags differently than the ADD/ADC instructions as defined in Intel 64 and\r\nIA-32 Architectures Software Developer's Manual, Volume 2A.\r\n\r\nOperation\r\nIF OperandSize is 64-bit\r\n THEN OF:DEST[63:0] <- DEST[63:0] + SRC[63:0] + OF;\r\n ELSE OF:DEST[31:0] <- DEST[31:0] + SRC[31:0] + OF;\r\nFI;\r\n\r\nFlags Affected\r\nOF is updated based on result. CF, SF, ZF, AF and PF flags are unmodified.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nunsigned char _addcarryx_u32 (unsigned char c_in, unsigned int src1, unsigned int src2, unsigned int *sum_out);\r\nunsigned char _addcarryx_u64 (unsigned char c_in, unsigned __int64 src1, unsigned __int64 src2, unsigned __int64 *sum_out);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.\r\n#SS(0) For an illegal address in the SS segment.\r\n#GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a null segment\r\n selector.\r\n#PF(fault-code) For a page fault.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n\r\nReal-Address Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.\r\n#SS(0) For an illegal address in the SS segment.\r\n#GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.\r\n#SS(0) For an illegal address in the SS segment.\r\n#GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH.\r\n#PF(fault-code) For a page fault.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) For a page fault.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "ADOX"
},
{
"description": "AESDEC-Perform One Round of an AES Decryption Flow\r\nOpcode/ Op/ 64/32-bit CPUID Description\r\nInstruction En Mode Feature\r\n Flag\r\n66 0F 38 DE /r RM V/V AES Perform one round of an AES decryption flow,\r\nAESDEC xmm1, xmm2/m128 using the Equivalent Inverse Cipher, operating\r\n on a 128-bit data (state) from xmm1 with a\r\n 128-bit round key from xmm2/m128.\r\nVEX.NDS.128.66.0F38.WIG DE /r RVM V/V Both AES Perform one round of an AES decryption flow,\r\nVAESDEC xmm1, xmm2, xmm3/m128 and using the Equivalent Inverse Cipher, operating\r\n AVX flags on a 128-bit data (state) from xmm2 with a\r\n 128-bit round key from xmm3/m128; store\r\n the result in xmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand2 Operand3 Operand4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nThis instruction performs a single round of the AES decryption flow using the Equivalent Inverse Cipher, with the\r\nround key from the second source operand, operating on a 128-bit data (state) from the first source operand, and\r\nstore the result in the destination operand.\r\nUse the AESDEC instruction for all but the last decryption round. For the last decryption round, use the AESDE-\r\nCLAST instruction.\r\n128-bit Legacy SSE version: The first source operand and the destination operand are the same and must be an\r\nXMM register. The second source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-\r\n1:128) of the corresponding YMM destination register remain unchanged.\r\nVEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second\r\nsource operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM\r\nregister are zeroed.\r\n\r\nOperation\r\nAESDEC\r\nSTATE <- SRC1;\r\nRoundKey <- SRC2;\r\nSTATE <- InvShiftRows( STATE );\r\nSTATE <- InvSubBytes( STATE );\r\nSTATE <- InvMixColumns( STATE );\r\nDEST[127:0] <- STATE XOR RoundKey;\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVAESDEC\r\nSTATE <- SRC1;\r\nRoundKey <- SRC2;\r\nSTATE <- InvShiftRows( STATE );\r\nSTATE <- InvSubBytes( STATE );\r\nSTATE <- InvMixColumns( STATE );\r\nDEST[127:0] <- STATE XOR RoundKey;\r\nDEST[VLMAX-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n(V)AESDEC: __m128i _mm_aesdec (__m128i, __m128i)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "AESDEC"
},
{
"description": "AESDECLAST-Perform Last Round of an AES Decryption Flow\r\nOpcode/ Op/ 64/32-bit CPUID Description\r\nInstruction En Mode Feature\r\n Flag\r\n66 0F 38 DF /r RM V/V AES Perform the last round of an AES decryption\r\nAESDECLAST xmm1, xmm2/m128 flow, using the Equivalent Inverse Cipher,\r\n operating on a 128-bit data (state) from\r\n xmm1 with a 128-bit round key from\r\n xmm2/m128.\r\nVEX.NDS.128.66.0F38.WIG DF /r RVM V/V Both AES Perform the last round of an AES decryption\r\nVAESDECLAST xmm1, xmm2, xmm3/m128 and flow, using the Equivalent Inverse Cipher,\r\n AVX flags operating on a 128-bit data (state) from\r\n xmm2 with a 128-bit round key from\r\n xmm3/m128; store the result in xmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand2 Operand3 Operand4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nThis instruction performs the last round of the AES decryption flow using the Equivalent Inverse Cipher, with the\r\nround key from the second source operand, operating on a 128-bit data (state) from the first source operand, and\r\nstore the result in the destination operand.\r\n128-bit Legacy SSE version: The first source operand and the destination operand are the same and must be an\r\nXMM register. The second source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-\r\n1:128) of the corresponding YMM destination register remain unchanged.\r\nVEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second\r\nsource operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM\r\nregister are zeroed.\r\n\r\nOperation\r\nAESDECLAST\r\nSTATE <- SRC1;\r\nRoundKey <- SRC2;\r\nSTATE <- InvShiftRows( STATE );\r\nSTATE <- InvSubBytes( STATE );\r\nDEST[127:0] <- STATE XOR RoundKey;\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVAESDECLAST\r\nSTATE <- SRC1;\r\nRoundKey <- SRC2;\r\nSTATE <- InvShiftRows( STATE );\r\nSTATE <- InvSubBytes( STATE );\r\nDEST[127:0] <- STATE XOR RoundKey;\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n(V)AESDECLAST: __m128i _mm_aesdeclast (__m128i, __m128i)\r\n\r\n\r\n\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "AESDECLAST"
},
{
"description": "AESENC-Perform One Round of an AES Encryption Flow\r\nOpcode/ Op/ 64/32-bit CPUID Description\r\nInstruction En Mode Feature\r\n Flag\r\n66 0F 38 DC /r RM V/V AES Perform one round of an AES encryption flow,\r\nAESENC xmm1, xmm2/m128 operating on a 128-bit data (state) from\r\n xmm1 with a 128-bit round key from\r\n xmm2/m128.\r\nVEX.NDS.128.66.0F38.WIG DC /r RVM V/V Both AES Perform one round of an AES encryption flow,\r\nVAESENC xmm1, xmm2, xmm3/m128 and operating on a 128-bit data (state) from\r\n AVX flags xmm2 with a 128-bit round key from the\r\n xmm3/m128; store the result in xmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand2 Operand3 Operand4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nThis instruction performs a single round of an AES encryption flow using a round key from the second source\r\noperand, operating on 128-bit data (state) from the first source operand, and store the result in the destination\r\noperand.\r\nUse the AESENC instruction for all but the last encryption rounds. For the last encryption round, use the AESENC-\r\nCLAST instruction.\r\n128-bit Legacy SSE version: The first source operand and the destination operand are the same and must be an\r\nXMM register. The second source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-\r\n1:128) of the corresponding YMM destination register remain unchanged.\r\nVEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second\r\nsource operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM\r\nregister are zeroed.\r\n\r\nOperation\r\nAESENC\r\nSTATE <- SRC1;\r\nRoundKey <- SRC2;\r\nSTATE <- ShiftRows( STATE );\r\nSTATE <- SubBytes( STATE );\r\nSTATE <- MixColumns( STATE );\r\nDEST[127:0] <- STATE XOR RoundKey;\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVAESENC\r\nSTATE <- SRC1;\r\nRoundKey <- SRC2;\r\nSTATE <- ShiftRows( STATE );\r\nSTATE <- SubBytes( STATE );\r\nSTATE <- MixColumns( STATE );\r\nDEST[127:0] <- STATE XOR RoundKey;\r\nDEST[VLMAX-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n(V)AESENC: __m128i _mm_aesenc (__m128i, __m128i)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "AESENC"
},
{
"description": "AESENCLAST-Perform Last Round of an AES Encryption Flow\r\nOpcode/ Op/ 64/32-bit CPUID Description\r\nInstruction En Mode Feature\r\n Flag\r\n66 0F 38 DD /r RM V/V AES Perform the last round of an AES encryption\r\nAESENCLAST xmm1, xmm2/m128 flow, operating on a 128-bit data (state) from\r\n xmm1 with a 128-bit round key from\r\n xmm2/m128.\r\nVEX.NDS.128.66.0F38.WIG DD /r RVM V/V Both AES Perform the last round of an AES encryption\r\nVAESENCLAST xmm1, xmm2, xmm3/m128 and flow, operating on a 128-bit data (state) from\r\n AVX flags xmm2 with a 128 bit round key from\r\n xmm3/m128; store the result in xmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand2 Operand3 Operand4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nThis instruction performs the last round of an AES encryption flow using a round key from the second source\r\noperand, operating on 128-bit data (state) from the first source operand, and store the result in the destination\r\noperand.\r\n128-bit Legacy SSE version: The first source operand and the destination operand are the same and must be an\r\nXMM register. The second source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-\r\n1:128) of the corresponding YMM destination register remain unchanged.\r\nVEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second\r\nsource operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM\r\nregister are zeroed.\r\n\r\nOperation\r\nAESENCLAST\r\nSTATE <- SRC1;\r\nRoundKey <- SRC2;\r\nSTATE <- ShiftRows( STATE );\r\nSTATE <- SubBytes( STATE );\r\nDEST[127:0] <- STATE XOR RoundKey;\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVAESENCLAST\r\nSTATE <- SRC1;\r\nRoundKey <- SRC2;\r\nSTATE <- ShiftRows( STATE );\r\nSTATE <- SubBytes( STATE );\r\nDEST[127:0] <- STATE XOR RoundKey;\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n(V)AESENCLAST: __m128i _mm_aesenclast (__m128i, __m128i)\r\n\r\n\r\n\r\n\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "AESENCLAST"
},
{
"description": "AESIMC-Perform the AES InvMixColumn Transformation\r\nOpcode/ Op/ 64/32-bit CPUID Description\r\nInstruction En Mode Feature\r\n Flag\r\n66 0F 38 DB /r RM V/V AES Perform the InvMixColumn transformation on\r\nAESIMC xmm1, xmm2/m128 a 128-bit round key from xmm2/m128 and\r\n store the result in xmm1.\r\nVEX.128.66.0F38.WIG DB /r RM V/V Both AES Perform the InvMixColumn transformation on\r\nVAESIMC xmm1, xmm2/m128 and a 128-bit round key from xmm2/m128 and\r\n AVX flags store the result in xmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand2 Operand3 Operand4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nPerform the InvMixColumns transformation on the source operand and store the result in the destination operand.\r\nThe destination operand is an XMM register. The source operand can be an XMM register or a 128-bit memory loca-\r\ntion.\r\nNote: the AESIMC instruction should be applied to the expanded AES round keys (except for the first and last round\r\nkey) in order to prepare them for decryption using the \"Equivalent Inverse Cipher\" (defined in FIPS 197).\r\n128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain\r\nunchanged.\r\nVEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.\r\nNote: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\nOperation\r\nAESIMC\r\nDEST[127:0] <- InvMixColumns( SRC );\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVAESIMC\r\nDEST[127:0] <- InvMixColumns( SRC );\r\nDEST[VLMAX-1:128] <- 0;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n(V)AESIMC: __m128i _mm_aesimc (__m128i)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4; additionally\r\n#UD If VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "AESIMC"
},
{
"description": "AESKEYGENASSIST-AES Round Key Generation Assist\r\n Opcode/ Op/ 64/32-bit CPUID Description\r\n Instruction En Mode Feature\r\n Flag\r\n 66 0F 3A DF /r ib RMI V/V AES Assist in AES round key generation using an 8\r\n AESKEYGENASSIST xmm1, xmm2/m128, imm8 bits Round Constant (RCON) specified in the\r\n immediate byte, operating on 128 bits of data\r\n specified in xmm2/m128 and stores the\r\n result in xmm1.\r\n VEX.128.66.0F3A.WIG DF /r ib RMI V/V Both AES Assist in AES round key generation using 8\r\n VAESKEYGENASSIST xmm1, xmm2/m128, imm8 and bits Round Constant (RCON) specified in the\r\n AVX flags immediate byte, operating on 128 bits of data\r\n specified in xmm2/m128 and stores the\r\n result in xmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand2 Operand3 Operand4\r\n RMI ModRM:reg (w) ModRM:r/m (r) imm8 NA\r\n\r\nDescription\r\nAssist in expanding the AES cipher key, by computing steps towards generating a round key for encryption, using\r\n128-bit data specified in the source operand and an 8-bit round constant specified as an immediate, store the\r\nresult in the destination operand.\r\nThe destination operand is an XMM register. The source operand can be an XMM register or a 128-bit memory loca-\r\ntion.\r\n128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain\r\nunchanged.\r\nVEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.\r\nNote: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\nOperation\r\nAESKEYGENASSIST\r\nX3[31:0] <- SRC [127: 96];\r\nX2[31:0] <- SRC [95: 64];\r\nX1[31:0] <- SRC [63: 32];\r\nX0[31:0] <- SRC [31: 0];\r\nRCON[31:0] <- ZeroExtend(Imm8[7:0]);\r\nDEST[31:0] <- SubWord(X1);\r\nDEST[63:32 ] <- RotWord( SubWord(X1) ) XOR RCON;\r\nDEST[95:64] <- SubWord(X3);\r\nDEST[127:96] <- RotWord( SubWord(X3) ) XOR RCON;\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\n\r\n\r\n\r\n\r\nVAESKEYGENASSIST\r\nX3[31:0] <- SRC [127: 96];\r\nX2[31:0] <- SRC [95: 64];\r\nX1[31:0] <- SRC [63: 32];\r\nX0[31:0] <- SRC [31: 0];\r\nRCON[31:0] <- ZeroExtend(Imm8[7:0]);\r\nDEST[31:0] <- SubWord(X1);\r\nDEST[63:32 ] <- RotWord( SubWord(X1) ) XOR RCON;\r\nDEST[95:64] <- SubWord(X3);\r\nDEST[127:96] <- RotWord( SubWord(X3) ) XOR RCON;\r\nDEST[VLMAX-1:128] <- 0;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n(V)AESKEYGENASSIST: __m128i _mm_aeskeygenassist (__m128i, const int)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4; additionally\r\n#UD If VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "AESKEYGENASSIST"
},
{
"description": "AND-Logical AND\r\n Opcode Instruction Op/ 64-bit Compat/ Description\r\n En Mode Leg Mode\r\n 24 ib AND AL, imm8 I Valid Valid AL AND imm8.\r\n 25 iw AND AX, imm16 I Valid Valid AX AND imm16.\r\n 25 id AND EAX, imm32 I Valid Valid EAX AND imm32.\r\n REX.W + 25 id AND RAX, imm32 I Valid N.E. RAX AND imm32 sign-extended to 64-bits.\r\n 80 /4 ib AND r/m8, imm8 MI Valid Valid r/m8 AND imm8.\r\n REX + 80 /4 ib AND r/m8*, imm8 MI Valid N.E. r/m8 AND imm8.\r\n 81 /4 iw AND r/m16, imm16 MI Valid Valid r/m16 AND imm16.\r\n 81 /4 id AND r/m32, imm32 MI Valid Valid r/m32 AND imm32.\r\n REX.W + 81 /4 id AND r/m64, imm32 MI Valid N.E. r/m64 AND imm32 sign extended to 64-bits.\r\n 83 /4 ib AND r/m16, imm8 MI Valid Valid r/m16 AND imm8 (sign-extended).\r\n 83 /4 ib AND r/m32, imm8 MI Valid Valid r/m32 AND imm8 (sign-extended).\r\n REX.W + 83 /4 ib AND r/m64, imm8 MI Valid N.E. r/m64 AND imm8 (sign-extended).\r\n 20 /r AND r/m8, r8 MR Valid Valid r/m8 AND r8.\r\n REX + 20 /r AND r/m8*, r8* MR Valid N.E. r/m64 AND r8 (sign-extended).\r\n 21 /r AND r/m16, r16 MR Valid Valid r/m16 AND r16.\r\n 21 /r AND r/m32, r32 MR Valid Valid r/m32 AND r32.\r\n REX.W + 21 /r AND r/m64, r64 MR Valid N.E. r/m64 AND r32.\r\n 22 /r AND r8, r/m8 RM Valid Valid r8 AND r/m8.\r\n REX + 22 /r AND r8*, r/m8* RM Valid N.E. r/m64 AND r8 (sign-extended).\r\n 23 /r AND r16, r/m16 RM Valid Valid r16 AND r/m16.\r\n 23 /r AND r32, r/m32 RM Valid Valid r32 AND r/m32.\r\n REX.W + 23 /r AND r64, r/m64 RM Valid N.E. r64 AND r/m64.\r\n NOTES:\r\n *In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n MR ModRM:r/m (r, w) ModRM:reg (r) NA NA\r\n MI ModRM:r/m (r, w) imm8 NA NA\r\n I AL/AX/EAX/RAX imm8 NA NA\r\n\r\nDescription\r\nPerforms a bitwise AND operation on the destination (first) and source (second) operands and stores the result in\r\nthe destination operand location. The source operand can be an immediate, a register, or a memory location; the\r\ndestination operand can be a register or a memory location. (However, two memory operands cannot be used in\r\none instruction.) Each bit of the result is set to 1 if both corresponding bits of the first and second operands are 1;\r\notherwise, it is set to 0.\r\nThis instruction can be used with a LOCK prefix to allow the it to be executed atomically.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\n\r\n\r\n\r\nOperation\r\nDEST <- DEST AND SRC;\r\n\r\nFlags Affected\r\nThe OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is\r\nundefined.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination operand points to a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n",
"mnem": "AND"
},
{
"description": "ANDN - Logical AND NOT\r\n Opcode/Instruction Op/ 64/32 CPUID Description\r\n En -bit Feature\r\n Mode Flag\r\n VEX.NDS.LZ.0F38.W0 F2 /r RVM V/V BMI1 Bitwise AND of inverted r32b with r/m32, store result in r32a.\r\n ANDN r32a, r32b, r/m32\r\n VEX.NDS.LZ. 0F38.W1 F2 /r RVM V/NE BMI1 Bitwise AND of inverted r64b with r/m64, store result in r64a.\r\n ANDN r64a, r64b, r/m64\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a bitwise logical AND of inverted second operand (the first source operand) with the third operand (the\r\nsecond source operand). The result is stored in the first operand (destination operand).\r\nThis instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in\r\n64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An\r\nattempt to execute this instruction with VEX.L not equal to 0 will cause #UD.\r\n\r\nOperation\r\nDEST <- (NOT SRC1) bitwiseAND SRC2;\r\nSF <- DEST[OperandSize -1];\r\nZF <- (DEST = 0);\r\n\r\nFlags Affected\r\nSF and ZF are updated based on result. OF and CF flags are cleared. AF and PF flags are undefined.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nAuto-generated from high-level language.\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Section 2.5.1, \"Exception Conditions for VEX-Encoded GPR Instructions\", Table 2-29; additionally\r\n#UD If VEX.W = 1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "ANDN"
},
{
"description": "ANDNPD-Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0F 55 /r RM V/V SSE2 Return the bitwise logical AND NOT of packed double-\r\n ANDNPD xmm1, xmm2/m128 precision floating-point values in xmm1 and xmm2/mem.\r\n VEX.NDS.128.66.0F 55 /r RVM V/V AVX Return the bitwise logical AND NOT of packed double-\r\n VANDNPD xmm1, xmm2, precision floating-point values in xmm2 and xmm3/mem.\r\n xmm3/m128\r\n VEX.NDS.256.66.0F 55/r RVM V/V AVX Return the bitwise logical AND NOT of packed double-\r\n VANDNPD ymm1, ymm2, precision floating-point values in ymm2 and ymm3/mem.\r\n ymm3/m256\r\n EVEX.NDS.128.66.0F.W1 55 /r FV V/V AVX512VL Return the bitwise logical AND NOT of packed double-\r\n VANDNPD xmm1 {k1}{z}, xmm2, AVX512DQ precision floating-point values in xmm2 and\r\n xmm3/m128/m64bcst xmm3/m128/m64bcst subject to writemask k1.\r\n EVEX.NDS.256.66.0F.W1 55 /r FV V/V AVX512VL Return the bitwise logical AND NOT of packed double-\r\n VANDNPD ymm1 {k1}{z}, ymm2, AVX512DQ precision floating-point values in ymm2 and\r\n ymm3/m256/m64bcst ymm3/m256/m64bcst subject to writemask k1.\r\n EVEX.NDS.512.66.0F.W1 55 /r FV V/V AVX512DQ Return the bitwise logical AND NOT of packed double-\r\n VANDNPD zmm1 {k1}{z}, zmm2, precision floating-point values in zmm2 and\r\n zmm3/m512/m64bcst zmm3/m512/m64bcst subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a bitwise logical AND NOT of the two, four or eight packed double-precision floating-point values from the\r\nfirst source operand and the second source operand, and stores the result in the destination operand.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be\r\na ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a\r\n64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with\r\nwritemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register\r\nor a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the\r\ncorresponding ZMM register destination are zeroed.\r\nVEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM\r\nregister or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nregister destination are unmodified.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVANDNPD (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n IF (EVEX.b == 1) AND (SRC2 *is memory*)\r\n THEN\r\n DEST[i+63:i] <- (NOT(SRC1[i+63:i])) BITWISE AND SRC2[63:0]\r\n ELSE\r\n DEST[i+63:i] <- (NOT(SRC1[i+63:i])) BITWISE AND SRC2[i+63:i]\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] = 0\r\n FI;\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVANDNPD (VEX.256 encoded version)\r\nDEST[63:0] <- (NOT(SRC1[63:0])) BITWISE AND SRC2[63:0]\r\nDEST[127:64] <- (NOT(SRC1[127:64])) BITWISE AND SRC2[127:64]\r\nDEST[191:128] <- (NOT(SRC1[191:128])) BITWISE AND SRC2[191:128]\r\nDEST[255:192] <- (NOT(SRC1[255:192])) BITWISE AND SRC2[255:192]\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVANDNPD (VEX.128 encoded version)\r\nDEST[63:0] <- (NOT(SRC1[63:0])) BITWISE AND SRC2[63:0]\r\nDEST[127:64] <- (NOT(SRC1[127:64])) BITWISE AND SRC2[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nANDNPD (128-bit Legacy SSE version)\r\nDEST[63:0] <- (NOT(DEST[63:0])) BITWISE AND SRC[63:0]\r\nDEST[127:64] <- (NOT(DEST[127:64])) BITWISE AND SRC[127:64]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVANDNPD __m512d _mm512_andnot_pd (__m512d a, __m512d b);\r\nVANDNPD __m512d _mm512_mask_andnot_pd (__m512d s, __mmask8 k, __m512d a, __m512d b);\r\nVANDNPD __m512d _mm512_maskz_andnot_pd (__mmask8 k, __m512d a, __m512d b);\r\nVANDNPD __m256d _mm256_mask_andnot_pd (__m256d s, __mmask8 k, __m256d a, __m256d b);\r\nVANDNPD __m256d _mm256_maskz_andnot_pd (__mmask8 k, __m256d a, __m256d b);\r\nVANDNPD __m128d _mm_mask_andnot_pd (__m128d s, __mmask8 k, __m128d a, __m128d b);\r\nVANDNPD __m128d _mm_maskz_andnot_pd (__mmask8 k, __m128d a, __m128d b);\r\nVANDNPD __m256d _mm256_andnot_pd (__m256d a, __m256d b);\r\nANDNPD __m128d _mm_andnot_pd (__m128d a, __m128d b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nOther Exceptions\r\nVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "ANDNPD"
},
{
"description": "ANDNPS-Bitwise Logical AND NOT of Packed Single Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 0F 55 /r RM V/V SSE Return the bitwise logical AND NOT of packed single-precision\r\n ANDNPS xmm1, xmm2/m128 floating-point values in xmm1 and xmm2/mem.\r\n VEX.NDS.128.0F 55 /r RVM V/V AVX Return the bitwise logical AND NOT of packed single-precision\r\n VANDNPS xmm1, xmm2, floating-point values in xmm2 and xmm3/mem.\r\n xmm3/m128\r\n VEX.NDS.256.0F 55 /r RVM V/V AVX Return the bitwise logical AND NOT of packed single-precision\r\n VANDNPS ymm1, ymm2, floating-point values in ymm2 and ymm3/mem.\r\n ymm3/m256\r\n EVEX.NDS.128.0F.W0 55 /r FV V/V AVX512VL Return the bitwise logical AND of packed single-precision\r\n VANDNPS xmm1 {k1}{z}, AVX512DQ floating-point values in xmm2 and xmm3/m128/m32bcst\r\n xmm2, xmm3/m128/m32bcst subject to writemask k1.\r\n EVEX.NDS.256.0F.W0 55 /r FV V/V AVX512VL Return the bitwise logical AND of packed single-precision\r\n VANDNPS ymm1 {k1}{z}, AVX512DQ floating-point values in ymm2 and ymm3/m256/m32bcst\r\n ymm2, ymm3/m256/m32bcst subject to writemask k1.\r\n EVEX.NDS.512.0F.W0 55 /r FV V/V AVX512DQ Return the bitwise logical AND of packed single-precision\r\n VANDNPS zmm1 {k1}{z}, floating-point values in zmm2 and zmm3/m512/m32bcst\r\n zmm2, zmm3/m512/m32bcst subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a bitwise logical AND NOT of the four, eight or sixteen packed single-precision floating-point values from\r\nthe first source operand and the second source operand, and stores the result in the destination operand.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be\r\na ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a\r\n32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with\r\nwritemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register\r\nor a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the\r\ncorresponding ZMM register destination are zeroed.\r\nVEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM\r\nregister or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nZMM register destination are unmodified.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVANDNPS (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n IF (EVEX.b == 1) AND (SRC2 *is memory*)\r\n THEN\r\n DEST[i+31:i] <- (NOT(SRC1[i+31:i])) BITWISE AND SRC2[31:0]\r\n ELSE\r\n DEST[i+31:i] <- (NOT(SRC1[i+31:i])) BITWISE AND SRC2[i+31:i]\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] = 0\r\n FI;\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVANDNPS (VEX.256 encoded version)\r\nDEST[31:0] <- (NOT(SRC1[31:0])) BITWISE AND SRC2[31:0]\r\nDEST[63:32] <- (NOT(SRC1[63:32])) BITWISE AND SRC2[63:32]\r\nDEST[95:64] <- (NOT(SRC1[95:64])) BITWISE AND SRC2[95:64]\r\nDEST[127:96] <- (NOT(SRC1[127:96])) BITWISE AND SRC2[127:96]\r\nDEST[159:128] <- (NOT(SRC1[159:128])) BITWISE AND SRC2[159:128]\r\nDEST[191:160] <- (NOT(SRC1[191:160])) BITWISE AND SRC2[191:160]\r\nDEST[223:192] <- (NOT(SRC1[223:192])) BITWISE AND SRC2[223:192]\r\nDEST[255:224] <- (NOT(SRC1[255:224])) BITWISE AND SRC2[255:224].\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVANDNPS (VEX.128 encoded version)\r\nDEST[31:0] <- (NOT(SRC1[31:0])) BITWISE AND SRC2[31:0]\r\nDEST[63:32] <- (NOT(SRC1[63:32])) BITWISE AND SRC2[63:32]\r\nDEST[95:64] <- (NOT(SRC1[95:64])) BITWISE AND SRC2[95:64]\r\nDEST[127:96] <- (NOT(SRC1[127:96])) BITWISE AND SRC2[127:96]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nANDNPS (128-bit Legacy SSE version)\r\nDEST[31:0] <- (NOT(DEST[31:0])) BITWISE AND SRC[31:0]\r\nDEST[63:32] <- (NOT(DEST[63:32])) BITWISE AND SRC[63:32]\r\nDEST[95:64] <- (NOT(DEST[95:64])) BITWISE AND SRC[95:64]\r\nDEST[127:96] <- (NOT(DEST[127:96])) BITWISE AND SRC[127:96]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVANDNPS __m512 _mm512_andnot_ps (__m512 a, __m512 b);\r\nVANDNPS __m512 _mm512_mask_andnot_ps (__m512 s, __mmask16 k, __m512 a, __m512 b);\r\nVANDNPS __m512 _mm512_maskz_andnot_ps (__mmask16 k, __m512 a, __m512 b);\r\nVANDNPS __m256 _mm256_mask_andnot_ps (__m256 s, __mmask8 k, __m256 a, __m256 b);\r\nVANDNPS __m256 _mm256_maskz_andnot_ps (__mmask8 k, __m256 a, __m256 b);\r\nVANDNPS __m128 _mm_mask_andnot_ps (__m128 s, __mmask8 k, __m128 a, __m128 b);\r\nVANDNPS __m128 _mm_maskz_andnot_ps (__mmask8 k, __m128 a, __m128 b);\r\nVANDNPS __m256 _mm256_andnot_ps (__m256 a, __m256 b);\r\nANDNPS __m128 _mm_andnot_ps (__m128 a, __m128 b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "ANDNPS"
},
{
"description": "ANDPD-Bitwise Logical AND of Packed Double Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0F 54 /r RM V/V SSE2 Return the bitwise logical AND of packed double-\r\n ANDPD xmm1, xmm2/m128 precision floating-point values in xmm1 and xmm2/mem.\r\n VEX.NDS.128.66.0F 54 /r RVM V/V AVX Return the bitwise logical AND of packed double-\r\n VANDPD xmm1, xmm2, precision floating-point values in xmm2 and xmm3/mem.\r\n xmm3/m128\r\n VEX.NDS.256.66.0F 54 /r RVM V/V AVX Return the bitwise logical AND of packed double-\r\n VANDPD ymm1, ymm2, precision floating-point values in ymm2 and ymm3/mem.\r\n ymm3/m256\r\n EVEX.NDS.128.66.0F.W1 54 /r FV V/V AVX512VL Return the bitwise logical AND of packed double-\r\n VANDPD xmm1 {k1}{z}, xmm2, AVX512DQ precision floating-point values in xmm2 and\r\n xmm3/m128/m64bcst xmm3/m128/m64bcst subject to writemask k1.\r\n EVEX.NDS.256.66.0F.W1 54 /r FV V/V AVX512VL Return the bitwise logical AND of packed double-\r\n VANDPD ymm1 {k1}{z}, ymm2, AVX512DQ precision floating-point values in ymm2 and\r\n ymm3/m256/m64bcst ymm3/m256/m64bcst subject to writemask k1.\r\n EVEX.NDS.512.66.0F.W1 54 /r FV V/V AVX512DQ Return the bitwise logical AND of packed double-\r\n VANDPD zmm1 {k1}{z}, zmm2, precision floating-point values in zmm2 and\r\n zmm3/m512/m64bcst zmm3/m512/m64bcst subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a bitwise logical AND of the two, four or eight packed double-precision floating-point values from the first\r\nsource operand and the second source operand, and stores the result in the destination operand.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be\r\na ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a\r\n64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with\r\nwritemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register\r\nor a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the\r\ncorresponding ZMM register destination are zeroed.\r\nVEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM\r\nregister or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nregister destination are unmodified.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVANDPD (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b == 1) AND (SRC2 *is memory*)\r\n THEN\r\n DEST[i+63:i] <- SRC1[i+63:i] BITWISE AND SRC2[63:0]\r\n ELSE\r\n DEST[i+63:i] <- SRC1[i+63:i] BITWISE AND SRC2[i+63:i]\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] = 0\r\n FI;\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVANDPD (VEX.256 encoded version)\r\nDEST[63:0] <- SRC1[63:0] BITWISE AND SRC2[63:0]\r\nDEST[127:64] <- SRC1[127:64] BITWISE AND SRC2[127:64]\r\nDEST[191:128] <- SRC1[191:128] BITWISE AND SRC2[191:128]\r\nDEST[255:192] <- SRC1[255:192] BITWISE AND SRC2[255:192]\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVANDPD (VEX.128 encoded version)\r\nDEST[63:0] <- SRC1[63:0] BITWISE AND SRC2[63:0]\r\nDEST[127:64] <- SRC1[127:64] BITWISE AND SRC2[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nANDPD (128-bit Legacy SSE version)\r\nDEST[63:0] <- DEST[63:0] BITWISE AND SRC[63:0]\r\nDEST[127:64] <- DEST[127:64] BITWISE AND SRC[127:64]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVANDPD __m512d _mm512_and_pd (__m512d a, __m512d b);\r\nVANDPD __m512d _mm512_mask_and_pd (__m512d s, __mmask8 k, __m512d a, __m512d b);\r\nVANDPD __m512d _mm512_maskz_and_pd (__mmask8 k, __m512d a, __m512d b);\r\nVANDPD __m256d _mm256_mask_and_pd (__m256d s, __mmask8 k, __m256d a, __m256d b);\r\nVANDPD __m256d _mm256_maskz_and_pd (__mmask8 k, __m256d a, __m256d b);\r\nVANDPD __m128d _mm_mask_and_pd (__m128d s, __mmask8 k, __m128d a, __m128d b);\r\nVANDPD __m128d _mm_maskz_and_pd (__mmask8 k, __m128d a, __m128d b);\r\nVANDPD __m256d _mm256_and_pd (__m256d a, __m256d b);\r\nANDPD __m128d _mm_and_pd (__m128d a, __m128d b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\nOther Exceptions\r\nVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "ANDPD"
},
{
"description": "ANDPS-Bitwise Logical AND of Packed Single Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 0F 54 /r RM V/V SSE Return the bitwise logical AND of packed single-precision\r\n ANDPS xmm1, xmm2/m128 floating-point values in xmm1 and xmm2/mem.\r\n VEX.NDS.128.0F 54 /r RVM V/V AVX Return the bitwise logical AND of packed single-precision\r\n VANDPS xmm1,xmm2, floating-point values in xmm2 and xmm3/mem.\r\n xmm3/m128\r\n VEX.NDS.256.0F 54 /r RVM V/V AVX Return the bitwise logical AND of packed single-precision\r\n VANDPS ymm1, ymm2, floating-point values in ymm2 and ymm3/mem.\r\n ymm3/m256\r\n EVEX.NDS.128.0F.W0 54 /r FV V/V AVX512VL Return the bitwise logical AND of packed single-precision\r\n VANDPS xmm1 {k1}{z}, xmm2, AVX512DQ floating-point values in xmm2 and xmm3/m128/m32bcst\r\n xmm3/m128/m32bcst subject to writemask k1.\r\n EVEX.NDS.256.0F.W0 54 /r FV V/V AVX512VL Return the bitwise logical AND of packed single-precision\r\n VANDPS ymm1 {k1}{z}, ymm2, AVX512DQ floating-point values in ymm2 and ymm3/m256/m32bcst\r\n ymm3/m256/m32bcst subject to writemask k1.\r\n EVEX.NDS.512.0F.W0 54 /r FV V/V AVX512DQ Return the bitwise logical AND of packed single-precision\r\n VANDPS zmm1 {k1}{z}, zmm2, floating-point values in zmm2 and zmm3/m512/m32bcst\r\n zmm3/m512/m32bcst subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a bitwise logical AND of the four, eight or sixteen packed single-precision floating-point values from the\r\nfirst source operand and the second source operand, and stores the result in the destination operand.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be\r\na ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a\r\n32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with\r\nwritemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register\r\nor a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the\r\ncorresponding ZMM register destination are zeroed.\r\nVEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM\r\nregister or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nZMM register destination are unmodified.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVANDPS (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n IF (EVEX.b == 1) AND (SRC2 *is memory*)\r\n THEN\r\n DEST[i+63:i] <- SRC1[i+31:i] BITWISE AND SRC2[31:0]\r\n ELSE\r\n DEST[i+31:i] <- SRC1[i+31:i] BITWISE AND SRC2[i+31:i]\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI;\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0;\r\n\r\nVANDPS (VEX.256 encoded version)\r\nDEST[31:0] <- SRC1[31:0] BITWISE AND SRC2[31:0]\r\nDEST[63:32] <- SRC1[63:32] BITWISE AND SRC2[63:32]\r\nDEST[95:64] <- SRC1[95:64] BITWISE AND SRC2[95:64]\r\nDEST[127:96] <- SRC1[127:96] BITWISE AND SRC2[127:96]\r\nDEST[159:128] <- SRC1[159:128] BITWISE AND SRC2[159:128]\r\nDEST[191:160] <- SRC1[191:160] BITWISE AND SRC2[191:160]\r\nDEST[223:192] <- SRC1[223:192] BITWISE AND SRC2[223:192]\r\nDEST[255:224] <- SRC1[255:224] BITWISE AND SRC2[255:224].\r\nDEST[MAX_VL-1:256] <- 0;\r\n\r\nVANDPS (VEX.128 encoded version)\r\nDEST[31:0] <- SRC1[31:0] BITWISE AND SRC2[31:0]\r\nDEST[63:32] <- SRC1[63:32] BITWISE AND SRC2[63:32]\r\nDEST[95:64] <- SRC1[95:64] BITWISE AND SRC2[95:64]\r\nDEST[127:96] <- SRC1[127:96] BITWISE AND SRC2[127:96]\r\nDEST[MAX_VL-1:128] <- 0;\r\n\r\nANDPS (128-bit Legacy SSE version)\r\nDEST[31:0] <- DEST[31:0] BITWISE AND SRC[31:0]\r\nDEST[63:32] <- DEST[63:32] BITWISE AND SRC[63:32]\r\nDEST[95:64] <- DEST[95:64] BITWISE AND SRC[95:64]\r\nDEST[127:96] <- DEST[127:96] BITWISE AND SRC[127:96]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVANDPS __m512 _mm512_and_ps (__m512 a, __m512 b);\r\nVANDPS __m512 _mm512_mask_and_ps (__m512 s, __mmask16 k, __m512 a, __m512 b);\r\nVANDPS __m512 _mm512_maskz_and_ps (__mmask16 k, __m512 a, __m512 b);\r\nVANDPS __m256 _mm256_mask_and_ps (__m256 s, __mmask8 k, __m256 a, __m256 b);\r\nVANDPS __m256 _mm256_maskz_and_ps (__mmask8 k, __m256 a, __m256 b);\r\nVANDPS __m128 _mm_mask_and_ps (__m128 s, __mmask8 k, __m128 a, __m128 b);\r\nVANDPS __m128 _mm_maskz_and_ps (__mmask8 k, __m128 a, __m128 b);\r\nVANDPS __m256 _mm256_and_ps (__m256 a, __m256 b);\r\nANDPS __m128 _mm_and_ps (__m128 a, __m128 b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "ANDPS"
},
{
"description": "ARPL-Adjust RPL Field of Segment Selector\r\nOpcode Instruction Op/ 64-bit Compat/ Description\r\n En Mode Leg Mode\r\n63 /r ARPL r/m16, r16 NP N. E. Valid Adjust RPL of r/m16 to not less than RPL of\r\n r16.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\nDescription\r\nCompares the RPL fields of two segment selectors. The first operand (the destination operand) contains one\r\nsegment selector and the second operand (source operand) contains the other. (The RPL field is located in bits 0\r\nand 1 of each operand.) If the RPL field of the destination operand is less than the RPL field of the source operand,\r\nthe ZF flag is set and the RPL field of the destination operand is increased to match that of the source operand.\r\nOtherwise, the ZF flag is cleared and no change is made to the destination operand. (The destination operand can\r\nbe a word register or a memory location; the source operand must be a word register.)\r\nThe ARPL instruction is provided for use by operating-system procedures (however, it can also be used by applica-\r\ntions). It is generally used to adjust the RPL of a segment selector that has been passed to the operating system\r\nby an application program to match the privilege level of the application program. Here the segment selector\r\npassed to the operating system is placed in the destination operand and segment selector for the application\r\nprogram's code segment is placed in the source operand. (The RPL field in the source operand represents the priv-\r\nilege level of the application program.) Execution of the ARPL instruction then ensures that the RPL of the segment\r\nselector received by the operating system is no lower (does not have a higher privilege) than the privilege level of\r\nthe application program (the segment selector for the application program's code segment can be read from the\r\nstack following a procedure call).\r\nThis instruction executes as described in compatibility mode and legacy mode. It is not encodable in 64-bit mode.\r\nSee \"Checking Caller Access Privileges\" in Chapter 3, \"Protected-Mode Memory Management,\" of the Intel 64 and\r\nIA-32 Architectures Software Developer's Manual, Volume 3A, for more information about the use of this instruc-\r\ntion.\r\n\r\nOperation\r\nIF 64-BIT MODE\r\n THEN\r\n See MOVSXD;\r\n ELSE\r\n IF DEST[RPL] < SRC[RPL]\r\n THEN\r\n ZF <- 1;\r\n DEST[RPL] <- SRC[RPL];\r\n ELSE\r\n ZF <- 0;\r\n FI;\r\nFI;\r\n\r\nFlags Affected\r\nThe ZF flag is set to 1 if the RPL field of the destination operand is less than that of the source operand; otherwise,\r\nit is set to 0.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination is located in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD The ARPL instruction is not recognized in real-address mode.\r\n If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD The ARPL instruction is not recognized in virtual-8086 mode.\r\n If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nNot applicable.\r\n\r\n\r\n\r\n\r\n",
"mnem": "ARPL"
},
{
"description": "BEXTR - Bit Field Extract\r\n Opcode/Instruction Op/ 64/32 CPUID Description\r\n En -bit Feature\r\n Mode Flag\r\n VEX.NDS.LZ.0F38.W0 F7 /r RMV V/V BMI1 Contiguous bitwise extract from r/m32 using r32b as control; store\r\n BEXTR r32a, r/m32, r32b result in r32a.\r\n VEX.NDS.LZ.0F38.W1 F7 /r RMV V/N.E. BMI1 Contiguous bitwise extract from r/m64 using r64b as control; store\r\n BEXTR r64a, r/m64, r64b result in r64a\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMV ModRM:reg (w) ModRM:r/m (r) VEX.vvvv (r) NA\r\n\r\nDescription\r\nExtracts contiguous bits from the first source operand (the second operand) using an index value and length value\r\nspecified in the second source operand (the third operand). Bit 7:0 of the second source operand specifies the\r\nstarting bit position of bit extraction. A START value exceeding the operand size will not extract any bits from the\r\nsecond source operand. Bit 15:8 of the second source operand specifies the maximum number of bits (LENGTH)\r\nbeginning at the START position to extract. Only bit positions up to (OperandSize -1) of the first source operand are\r\nextracted. The extracted bits are written to the destination register, starting from the least significant bit. All higher\r\norder bits in the destination operand (starting at bit position LENGTH) are zeroed. The destination register is\r\ncleared if no bits are extracted.\r\nThis instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in\r\n64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An\r\nattempt to execute this instruction with VEX.L not equal to 0 will cause #UD.\r\n\r\nOperation\r\nSTART <- SRC2[7:0];\r\nLEN <- SRC2[15:8];\r\nTEMP <- ZERO_EXTEND_TO_512 (SRC1 );\r\nDEST <- ZERO_EXTEND(TEMP[START+LEN -1: START]);\r\nZF <- (DEST = 0);\r\n\r\nFlags Affected\r\nZF is updated based on the result. AF, SF, and PF are undefined. All other flags are cleared.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBEXTR: unsigned __int32 _bextr_u32(unsigned __int32 src, unsigned __int32 start. unsigned __int32 len);\r\n\r\nBEXTR: unsigned __int64 _bextr_u64(unsigned __int64 src, unsigned __int32 start. unsigned __int32 len);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Section 2.5.1, \"Exception Conditions for VEX-Encoded GPR Instructions\", Table 2-29; additionally\r\n#UD If VEX.W = 1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "BEXTR"
},
{
"description": "BLENDPD - Blend Packed Double Precision Floating-Point Values\r\n Opcode/ Op/ 64/32-bit CPUID Description\r\n Instruction En Mode Feature\r\n Flag\r\n 66 0F 3A 0D /r ib RMI V/V SSE4_1 Select packed DP-FP values from xmm1 and\r\n BLENDPD xmm1, xmm2/m128, imm8 xmm2/m128 from mask specified in imm8\r\n and store the values into xmm1.\r\n VEX.NDS.128.66.0F3A.WIG 0D /r ib RVMI V/V AVX Select packed double-precision floating-point\r\n VBLENDPD xmm1, xmm2, xmm3/m128, imm8 Values from xmm2 and xmm3/m128 from\r\n mask in imm8 and store the values in xmm1.\r\n VEX.NDS.256.66.0F3A.WIG 0D /r ib RVMI V/V AVX Select packed double-precision floating-point\r\n VBLENDPD ymm1, ymm2, ymm3/m256, imm8 Values from ymm2 and ymm3/m256 from\r\n mask in imm8 and store the values in ymm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (r, w) ModRM:r/m (r) imm8 NA\r\n RVMI ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8[3:0]\r\n\r\nDescription\r\nDouble-precision floating-point values from the second source operand (third operand) are conditionally merged\r\nwith values from the first source operand (second operand) and written to the destination operand (first operand).\r\nThe immediate bits [3:0] determine whether the corresponding double-precision floating-point value in the desti-\r\nnation is copied from the second source or first source. If a bit in the mask, corresponding to a word, is \"1\", then\r\nthe double-precision floating-point value in the second source operand is copied, else the value in the first source\r\noperand is copied.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding\r\nYMM register destination are unmodified.\r\nVEX.128 encoded version: the first source operand is an XMM register. The second source operand is an XMM\r\nregister or 128-bit memory location. The destination operand is an XMM register. The upper bits (VLMAX-1:128) of\r\nthe corresponding YMM register destination are zeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register.\r\n\r\nOperation\r\nBLENDPD (128-bit Legacy SSE version)\r\nIF (IMM8[0] = 0)THEN DEST[63:0] <- DEST[63:0]\r\n ELSE DEST [63:0] <- SRC[63:0] FI\r\nIF (IMM8[1] = 0) THEN DEST[127:64] <- DEST[127:64]\r\n ELSE DEST [127:64] <- SRC[127:64] FI\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVBLENDPD (VEX.128 encoded version)\r\nIF (IMM8[0] = 0)THEN DEST[63:0] <- SRC1[63:0]\r\n ELSE DEST [63:0] <- SRC2[63:0] FI\r\nIF (IMM8[1] = 0) THEN DEST[127:64] <- SRC1[127:64]\r\n ELSE DEST [127:64] <- SRC2[127:64] FI\r\nDEST[VLMAX-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVBLENDPD (VEX.256 encoded version)\r\nIF (IMM8[0] = 0)THEN DEST[63:0] <- SRC1[63:0]\r\n ELSE DEST [63:0] <- SRC2[63:0] FI\r\nIF (IMM8[1] = 0) THEN DEST[127:64] <- SRC1[127:64]\r\n ELSE DEST [127:64] <- SRC2[127:64] FI\r\nIF (IMM8[2] = 0) THEN DEST[191:128] <- SRC1[191:128]\r\n ELSE DEST [191:128] <- SRC2[191:128] FI\r\nIF (IMM8[3] = 0) THEN DEST[255:192] <- SRC1[255:192]\r\n ELSE DEST [255:192] <- SRC2[255:192] FI\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBLENDPD: __m128d _mm_blend_pd (__m128d v1, __m128d v2, const int mask);\r\n\r\nVBLENDPD: __m256d _mm256_blend_pd (__m256d a, __m256d b, const int mask);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "BLENDPD"
},
{
"description": "BLENDPS - Blend Packed Single Precision Floating-Point Values\r\n Opcode/ Op/ 64/32-bit CPUID Description\r\n Instruction En Mode Feature\r\n Flag\r\n 66 0F 3A 0C /r ib RMI V/V SSE4_1 Select packed single precision floating-point\r\n BLENDPS xmm1, xmm2/m128, imm8 values from xmm1 and xmm2/m128 from\r\n mask specified in imm8 and store the values\r\n into xmm1.\r\n VEX.NDS.128.66.0F3A.WIG 0C /r ib RVMI V/V AVX Select packed single-precision floating-point\r\n VBLENDPS xmm1, xmm2, xmm3/m128, imm8 values from xmm2 and xmm3/m128 from\r\n mask in imm8 and store the values in xmm1.\r\n VEX.NDS.256.66.0F3A.WIG 0C /r ib RVMI V/V AVX Select packed single-precision floating-point\r\n VBLENDPS ymm1, ymm2, ymm3/m256, imm8 values from ymm2 and ymm3/m256 from\r\n mask in imm8 and store the values in ymm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (r, w) ModRM:r/m (r) imm8 NA\r\n RVMI ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8\r\n\r\nDescription\r\nPacked single-precision floating-point values from the second source operand (third operand) are conditionally\r\nmerged with values from the first source operand (second operand) and written to the destination operand (first\r\noperand). The immediate bits [7:0] determine whether the corresponding single precision floating-point value in\r\nthe destination is copied from the second source or first source. If a bit in the mask, corresponding to a word, is\r\n\"1\", then the single-precision floating-point value in the second source operand is copied, else the value in the first\r\nsource operand is copied.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding\r\nYMM register destination are unmodified.\r\nVEX.128 encoded version: The first source operand an XMM register. The second source operand is an XMM register\r\nor 128-bit memory location. The destination operand is an XMM register. The upper bits (VLMAX-1:128) of the\r\ncorresponding YMM register destination are zeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register.\r\n\r\nOperation\r\nBLENDPS (128-bit Legacy SSE version)\r\nIF (IMM8[0] = 0) THEN DEST[31:0] <-DEST[31:0]\r\n ELSE DEST [31:0] <- SRC[31:0] FI\r\nIF (IMM8[1] = 0) THEN DEST[63:32] <- DEST[63:32]\r\n ELSE DEST [63:32] <- SRC[63:32] FI\r\nIF (IMM8[2] = 0) THEN DEST[95:64] <- DEST[95:64]\r\n ELSE DEST [95:64] <- SRC[95:64] FI\r\nIF (IMM8[3] = 0) THEN DEST[127:96] <- DEST[127:96]\r\n ELSE DEST [127:96] <- SRC[127:96] FI\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\n\r\n\r\n\r\n\r\nVBLENDPS (VEX.128 encoded version)\r\nIF (IMM8[0] = 0) THEN DEST[31:0] <-SRC1[31:0]\r\n ELSE DEST [31:0] <- SRC2[31:0] FI\r\nIF (IMM8[1] = 0) THEN DEST[63:32] <- SRC1[63:32]\r\n ELSE DEST [63:32] <- SRC2[63:32] FI\r\nIF (IMM8[2] = 0) THEN DEST[95:64] <- SRC1[95:64]\r\n ELSE DEST [95:64] <- SRC2[95:64] FI\r\nIF (IMM8[3] = 0) THEN DEST[127:96] <- SRC1[127:96]\r\n ELSE DEST [127:96] <- SRC2[127:96] FI\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVBLENDPS (VEX.256 encoded version)\r\nIF (IMM8[0] = 0) THEN DEST[31:0] <-SRC1[31:0]\r\n ELSE DEST [31:0] <- SRC2[31:0] FI\r\nIF (IMM8[1] = 0) THEN DEST[63:32] <- SRC1[63:32]\r\n ELSE DEST [63:32] <- SRC2[63:32] FI\r\nIF (IMM8[2] = 0) THEN DEST[95:64] <- SRC1[95:64]\r\n ELSE DEST [95:64] <- SRC2[95:64] FI\r\nIF (IMM8[3] = 0) THEN DEST[127:96] <- SRC1[127:96]\r\n ELSE DEST [127:96] <- SRC2[127:96] FI\r\nIF (IMM8[4] = 0) THEN DEST[159:128] <- SRC1[159:128]\r\n ELSE DEST [159:128] <- SRC2[159:128] FI\r\nIF (IMM8[5] = 0) THEN DEST[191:160] <- SRC1[191:160]\r\n ELSE DEST [191:160] <- SRC2[191:160] FI\r\nIF (IMM8[6] = 0) THEN DEST[223:192] <- SRC1[223:192]\r\n ELSE DEST [223:192] <- SRC2[223:192] FI\r\nIF (IMM8[7] = 0) THEN DEST[255:224] <- SRC1[255:224]\r\n ELSE DEST [255:224] <- SRC2[255:224] FI.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBLENDPS: __m128 _mm_blend_ps (__m128 v1, __m128 v2, const int mask);\r\n\r\nVBLENDPS: __m256 _mm256_blend_ps (__m256 a, __m256 b, const int mask);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "BLENDPS"
},
{
"description": "BLENDVPD - Variable Blend Packed Double Precision Floating-Point Values\r\n Opcode/ Op/ 64/32-bit CPUID Description\r\n Instruction En Mode Feature\r\n Flag\r\n 66 0F 38 15 /r RM0 V/V SSE4_1 Select packed DP FP values from xmm1 and\r\n BLENDVPD xmm1, xmm2/m128 , <XMM0> xmm2 from mask specified in XMM0 and\r\n store the values in xmm1.\r\n VEX.NDS.128.66.0F3A.W0 4B /r /is4 RVMR V/V AVX Conditionally copy double-precision floating-\r\n VBLENDVPD xmm1, xmm2, xmm3/m128, xmm4 point values from xmm2 or xmm3/m128 to\r\n xmm1, based on mask bits in the mask\r\n operand, xmm4.\r\n VEX.NDS.256.66.0F3A.W0 4B /r /is4 RVMR V/V AVX Conditionally copy double-precision floating-\r\n VBLENDVPD ymm1, ymm2, ymm3/m256, ymm4 point values from ymm2 or ymm3/m256 to\r\n ymm1, based on mask bits in the mask\r\n operand, ymm4.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM0 ModRM:reg (r, w) ModRM:r/m (r) implicit XMM0 NA\r\n RVMR ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8[7:4]\r\n\r\nDescription\r\nConditionally copy each quadword data element of double-precision floating-point value from the second source\r\noperand and the first source operand depending on mask bits defined in the mask register operand. The mask bits\r\nare the most significant bit in each quadword element of the mask register.\r\nEach quadword element of the destination operand is copied from:\r\n. the corresponding quadword element in the second source operand, if a mask bit is \"1\"; or\r\n. the corresponding quadword element in the first source operand, if a mask bit is \"0\"\r\nThe register assignment of the implicit mask operand for BLENDVPD is defined to be the architectural register\r\nXMM0.\r\n128-bit Legacy SSE version: The first source operand and the destination operand is the same. Bits (VLMAX-1:128)\r\nof the corresponding YMM destination register remain unchanged. The mask register operand is implicitly defined\r\nto be the architectural register XMM0. An attempt to execute BLENDVPD with a VEX prefix will cause #UD.\r\nVEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second\r\nsource operand is an XMM register or 128-bit memory location. The mask operand is the third source register, and\r\nencoded in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is\r\nignored. The upper bits (VLMAX-1:128) of the corresponding YMM register (destination register) are zeroed.\r\nVEX.W must be 0, otherwise, the instruction will #UD.\r\nVEX.256 encoded version: The first source operand and destination operand are YMM registers. The second source\r\noperand can be a YMM register or a 256-bit memory location. The mask operand is the third source register, and\r\nencoded in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is\r\nignored. VEX.W must be 0, otherwise, the instruction will #UD.\r\nVBLENDVPD permits the mask to be any XMM or YMM register. In contrast, BLENDVPD treats XMM0 implicitly as the\r\nmask and do not support non-destructive destination operation.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nBLENDVPD (128-bit Legacy SSE version)\r\nMASK <- XMM0\r\nIF (MASK[63] = 0) THEN DEST[63:0] <- DEST[63:0]\r\n ELSE DEST [63:0] <- SRC[63:0] FI\r\nIF (MASK[127] = 0) THEN DEST[127:64] <- DEST[127:64]\r\n ELSE DEST [127:64] <- SRC[127:64] FI\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVBLENDVPD (VEX.128 encoded version)\r\nMASK <- SRC3\r\nIF (MASK[63] = 0) THEN DEST[63:0] <- SRC1[63:0]\r\n ELSE DEST [63:0] <- SRC2[63:0] FI\r\nIF (MASK[127] = 0) THEN DEST[127:64] <- SRC1[127:64]\r\n ELSE DEST [127:64] <- SRC2[127:64] FI\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVBLENDVPD (VEX.256 encoded version)\r\nMASK <- SRC3\r\nIF (MASK[63] = 0) THEN DEST[63:0] <- SRC1[63:0]\r\n ELSE DEST [63:0] <- SRC2[63:0] FI\r\nIF (MASK[127] = 0) THEN DEST[127:64] <- SRC1[127:64]\r\n ELSE DEST [127:64] <- SRC2[127:64] FI\r\nIF (MASK[191] = 0) THEN DEST[191:128] <- SRC1[191:128]\r\n ELSE DEST [191:128] <- SRC2[191:128] FI\r\nIF (MASK[255] = 0) THEN DEST[255:192] <- SRC1[255:192]\r\n ELSE DEST [255:192] <- SRC2[255:192] FI\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBLENDVPD: __m128d _mm_blendv_pd(__m128d v1, __m128d v2, __m128d v3);\r\n\r\nVBLENDVPD: __m128 _mm_blendv_pd (__m128d a, __m128d b, __m128d mask);\r\n\r\nVBLENDVPD: __m256 _mm256_blendv_pd (__m256d a, __m256d b, __m256d mask);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4; additionally\r\n#UD If VEX.W = 1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "BLENDVPD"
},
{
"description": "BLENDVPS - Variable Blend Packed Single Precision Floating-Point Values\r\n Opcode/ Op/ 64/32-bit CPUID Description\r\n Instruction En Mode Feature\r\n Flag\r\n 66 0F 38 14 /r RM0 V/V SSE4_1 Select packed single precision floating-point\r\n BLENDVPS xmm1, xmm2/m128, <XMM0> values from xmm1 and xmm2/m128 from\r\n mask specified in XMM0 and store the values\r\n into xmm1.\r\n VEX.NDS.128.66.0F3A.W0 4A /r /is4 RVMR V/V AVX Conditionally copy single-precision floating-\r\n VBLENDVPS xmm1, xmm2, xmm3/m128, xmm4 point values from xmm2 or xmm3/m128 to\r\n xmm1, based on mask bits in the specified\r\n mask operand, xmm4.\r\n VEX.NDS.256.66.0F3A.W0 4A /r /is4 RVMR V/V AVX Conditionally copy single-precision floating-\r\n VBLENDVPS ymm1, ymm2, ymm3/m256, ymm4 point values from ymm2 or ymm3/m256 to\r\n ymm1, based on mask bits in the specified\r\n mask register, ymm4.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM0 ModRM:reg (r, w) ModRM:r/m (r) implicit XMM0 NA\r\n RVMR ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8[7:4]\r\n\r\nDescription\r\nConditionally copy each dword data element of single-precision floating-point value from the second source\r\noperand and the first source operand depending on mask bits defined in the mask register operand. The mask bits\r\nare the most significant bit in each dword element of the mask register.\r\nEach quadword element of the destination operand is copied from:\r\n. the corresponding dword element in the second source operand, if a mask bit is \"1\"; or\r\n. the corresponding dword element in the first source operand, if a mask bit is \"0\"\r\nThe register assignment of the implicit mask operand for BLENDVPS is defined to be the architectural register\r\nXMM0.\r\n128-bit Legacy SSE version: The first source operand and the destination operand is the same. Bits (VLMAX-1:128)\r\nof the corresponding YMM destination register remain unchanged. The mask register operand is implicitly defined\r\nto be the architectural register XMM0. An attempt to execute BLENDVPS with a VEX prefix will cause #UD.\r\nVEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second\r\nsource operand is an XMM register or 128-bit memory location. The mask operand is the third source register, and\r\nencoded in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is\r\nignored. The upper bits (VLMAX-1:128) of the corresponding YMM register (destination register) are zeroed.\r\nVEX.W must be 0, otherwise, the instruction will #UD.\r\nVEX.256 encoded version: The first source operand and destination operand are YMM registers. The second source\r\noperand can be a YMM register or a 256-bit memory location. The mask operand is the third source register, and\r\nencoded in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is\r\nignored. VEX.W must be 0, otherwise, the instruction will #UD.\r\nVBLENDVPS permits the mask to be any XMM or YMM register. In contrast, BLENDVPS treats XMM0 implicitly as the\r\nmask and do not support non-destructive destination operation.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nBLENDVPS (128-bit Legacy SSE version)\r\nMASK <- XMM0\r\nIF (MASK[31] = 0) THEN DEST[31:0] <- DEST[31:0]\r\n ELSE DEST [31:0] <- SRC[31:0] FI\r\nIF (MASK[63] = 0) THEN DEST[63:32] <- DEST[63:32]\r\n ELSE DEST [63:32] <- SRC[63:32] FI\r\nIF (MASK[95] = 0) THEN DEST[95:64] <- DEST[95:64]\r\n ELSE DEST [95:64] <- SRC[95:64] FI\r\nIF (MASK[127] = 0) THEN DEST[127:96] <- DEST[127:96]\r\n ELSE DEST [127:96] <- SRC[127:96] FI\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVBLENDVPS (VEX.128 encoded version)\r\nMASK <- SRC3\r\nIF (MASK[31] = 0) THEN DEST[31:0] <- SRC1[31:0]\r\n ELSE DEST [31:0] <- SRC2[31:0] FI\r\nIF (MASK[63] = 0) THEN DEST[63:32] <- SRC1[63:32]\r\n ELSE DEST [63:32] <- SRC2[63:32] FI\r\nIF (MASK[95] = 0) THEN DEST[95:64] <- SRC1[95:64]\r\n ELSE DEST [95:64] <- SRC2[95:64] FI\r\nIF (MASK[127] = 0) THEN DEST[127:96] <- SRC1[127:96]\r\n ELSE DEST [127:96] <- SRC2[127:96] FI\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVBLENDVPS (VEX.256 encoded version)\r\nMASK <- SRC3\r\nIF (MASK[31] = 0) THEN DEST[31:0] <- SRC1[31:0]\r\n ELSE DEST [31:0] <- SRC2[31:0] FI\r\nIF (MASK[63] = 0) THEN DEST[63:32] <- SRC1[63:32]\r\n ELSE DEST [63:32] <- SRC2[63:32] FI\r\nIF (MASK[95] = 0) THEN DEST[95:64] <- SRC1[95:64]\r\n ELSE DEST [95:64] <- SRC2[95:64] FI\r\nIF (MASK[127] = 0) THEN DEST[127:96] <- SRC1[127:96]\r\n ELSE DEST [127:96] <- SRC2[127:96] FI\r\nIF (MASK[159] = 0) THEN DEST[159:128] <- SRC1[159:128]\r\n ELSE DEST [159:128] <- SRC2[159:128] FI\r\nIF (MASK[191] = 0) THEN DEST[191:160] <- SRC1[191:160]\r\n ELSE DEST [191:160] <- SRC2[191:160] FI\r\nIF (MASK[223] = 0) THEN DEST[223:192] <- SRC1[223:192]\r\n ELSE DEST [223:192] <- SRC2[223:192] FI\r\nIF (MASK[255] = 0) THEN DEST[255:224] <- SRC1[255:224]\r\n ELSE DEST [255:224] <- SRC2[255:224] FI\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBLENDVPS: __m128 _mm_blendv_ps(__m128 v1, __m128 v2, __m128 v3);\r\n\r\nVBLENDVPS: __m128 _mm_blendv_ps (__m128 a, __m128 b, __m128 mask);\r\n\r\nVBLENDVPS: __m256 _mm256_blendv_ps (__m256 a, __m256 b, __m256 mask);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4; additionally\r\n#UD If VEX.W = 1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "BLENDVPS"
},
{
"description": "BLSI - Extract Lowest Set Isolated Bit\r\n Opcode/Instruction Op/ 64/32 CPUID Description\r\n En -bit Feature\r\n Mode Flag\r\n VEX.NDD.LZ.0F38.W0 F3 /3 VM V/V BMI1 Extract lowest set bit from r/m32 and set that bit in r32.\r\n BLSI r32, r/m32\r\n VEX.NDD.LZ.0F38.W1 F3 /3 VM V/N.E. BMI1 Extract lowest set bit from r/m64, and set that bit in r64.\r\n BLSI r64, r/m64\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n VM VEX.vvvv (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nExtracts the lowest set bit from the source operand and set the corresponding bit in the destination register. All\r\nother bits in the destination operand are zeroed. If no bits are set in the source operand, BLSI sets all the bits in\r\nthe destination to 0 and sets ZF and CF.\r\nThis instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in\r\n64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An\r\nattempt to execute this instruction with VEX.L not equal to 0 will cause #UD.\r\n\r\nOperation\r\ntemp <- (-SRC) bitwiseAND (SRC);\r\nSF <- temp[OperandSize -1];\r\nZF <- (temp = 0);\r\nIF SRC = 0\r\n CF <- 0;\r\nELSE\r\n CF <- 1;\r\nFI\r\nDEST <- temp;\r\n\r\nFlags Affected\r\nZF and SF are updated based on the result. CF is set if the source is not zero. OF flags are cleared. AF and PF\r\nflags are undefined.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBLSI: unsigned __int32 _blsi_u32(unsigned __int32 src);\r\n\r\nBLSI: unsigned __int64 _blsi_u64(unsigned __int64 src);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Section 2.5.1, \"Exception Conditions for VEX-Encoded GPR Instructions\", Table 2-29; additionally\r\n#UD If VEX.W = 1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "BLSI"
},
{
"description": "BLSMSK - Get Mask Up to Lowest Set Bit\r\n Opcode/Instruction Op/ 64/32 CPUID Description\r\n En -bit Feature\r\n Mode Flag\r\n VEX.NDD.LZ.0F38.W0 F3 /2 VM V/V BMI1 Set all lower bits in r32 to \"1\" starting from bit 0 to lowest set bit in\r\n BLSMSK r32, r/m32 r/m32.\r\n VEX.NDD.LZ.0F38.W1 F3 /2 VM V/N.E. BMI1 Set all lower bits in r64 to \"1\" starting from bit 0 to lowest set bit in\r\n BLSMSK r64, r/m64 r/m64.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n VM VEX.vvvv (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nSets all the lower bits of the destination operand to \"1\" up to and including lowest set bit (=1) in the source\r\noperand. If source operand is zero, BLSMSK sets all bits of the destination operand to 1 and also sets CF to 1.\r\nThis instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in\r\n64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An\r\nattempt to execute this instruction with VEX.L not equal to 0 will cause #UD.\r\n\r\nOperation\r\ntemp <- (SRC-1) XOR (SRC) ;\r\nSF <- temp[OperandSize -1];\r\nZF <- 0;\r\nIF SRC = 0\r\n CF <- 1;\r\nELSE\r\n CF <- 0;\r\nFI\r\nDEST <- temp;\r\n\r\nFlags Affected\r\nSF is updated based on the result. CF is set if the source if zero. ZF and OF flags are cleared. AF and PF flag are\r\nundefined.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBLSMSK: unsigned __int32 _blsmsk_u32(unsigned __int32 src);\r\n\r\nBLSMSK: unsigned __int64 _blsmsk_u64(unsigned __int64 src);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Section 2.5.1, \"Exception Conditions for VEX-Encoded GPR Instructions\", Table 2-29; additionally\r\n#UD If VEX.W = 1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "BLSMSK"
},
{
"description": "BLSR - Reset Lowest Set Bit\r\n Opcode/Instruction Op/ 64/32 CPUID Description\r\n En -bit Feature\r\n Mode Flag\r\n VEX.NDD.LZ.0F38.W0 F3 /1 VM V/V BMI1 Reset lowest set bit of r/m32, keep all other bits of r/m32 and write\r\n BLSR r32, r/m32 result to r32.\r\n VEX.NDD.LZ.0F38.W1 F3 /1 VM V/N.E. BMI1 Reset lowest set bit of r/m64, keep all other bits of r/m64 and write\r\n BLSR r64, r/m64 result to r64.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n VM VEX.vvvv (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nCopies all bits from the source operand to the destination operand and resets (=0) the bit position in the destina-\r\ntion operand that corresponds to the lowest set bit of the source operand. If the source operand is zero BLSR sets\r\nCF.\r\nThis instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in\r\n64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An\r\nattempt to execute this instruction with VEX.L not equal to 0 will cause #UD.\r\n\r\nOperation\r\ntemp <- (SRC-1) bitwiseAND ( SRC );\r\nSF <- temp[OperandSize -1];\r\nZF <- (temp = 0);\r\nIF SRC = 0\r\n CF <- 1;\r\nELSE\r\n CF <- 0;\r\nFI\r\nDEST <- temp;\r\n\r\nFlags Affected\r\nZF and SF flags are updated based on the result. CF is set if the source is zero. OF flag is cleared. AF and PF flags\r\nare undefined.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBLSR: unsigned __int32 _blsr_u32(unsigned __int32 src);\r\n\r\nBLSR: unsigned __int64 _blsr_u64(unsigned __int64 src);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Section 2.5.1, \"Exception Conditions for VEX-Encoded GPR Instructions\", Table 2-29; additionally\r\n#UD If VEX.W = 1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "BLSR"
},
{
"description": "BNDCL-Check Lower Bound\r\n Opcode/ Op/En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n F3 0F 1A /r RM NE/V MPX Generate a #BR if the address in r/m32 is lower than the lower\r\n BNDCL bnd, r/m32 bound in bnd.LB.\r\n F3 0F 1A /r RM V/NE MPX Generate a #BR if the address in r/m64 is lower than the lower\r\n BNDCL bnd, r/m64 bound in bnd.LB.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3\r\n RM ModRM:reg (w) ModRM:r/m (r) NA\r\n\r\nDescription\r\nCompare the address in the second operand with the lower bound in bnd. The second operand can be either a\r\nregister or memory operand. If the address is lower than the lower bound in bnd.LB, it will set BNDSTATUS to 01H\r\nand signal a #BR exception.\r\nThis instruction does not cause any memory access, and does not read or write any flags.\r\n\r\nOperation\r\nBNDCL BND, reg\r\nIF reg < BND.LB Then\r\n BNDSTATUS <- 01H;\r\n #BR;\r\nFI;\r\n\r\nBNDCL BND, mem\r\nTEMP <- LEA(mem);\r\nIF TEMP < BND.LB Then\r\n BNDSTATUS <- 01H;\r\n #BR;\r\nFI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBNDCL void _bnd_chk_ptr_lbounds(const void *q)\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#BR If lower bound check fails.\r\n#UD If the LOCK prefix is used.\r\n If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n If 67H prefix is not used and CS.D=0.\r\n If 67H prefix is used and CS.D=1.\r\n\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#BR If lower bound check fails.\r\n#UD If the LOCK prefix is used.\r\n If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n If 16-bit addressing is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#BR If lower bound check fails.\r\n#UD If the LOCK prefix is used.\r\n If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n If 16-bit addressing is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "BNDCL"
},
{
"description": "-R:BNDCU",
"mnem": "BNDCN"
},
{
"description": "BNDCU/BNDCN-Check Upper Bound\r\n Opcode/ Op/En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n F2 0F 1A /r RM NE/V MPX Generate a #BR if the address in r/m32 is higher than the upper\r\n BNDCU bnd, r/m32 bound in bnd.UB (bnb.UB in 1's complement form).\r\n F2 0F 1A /r RM V/NE MPX Generate a #BR if the address in r/m64 is higher than the upper\r\n BNDCU bnd, r/m64 bound in bnd.UB (bnb.UB in 1's complement form).\r\n F2 0F 1B /r RM NE/V MPX Generate a #BR if the address in r/m32 is higher than the upper\r\n BNDCN bnd, r/m32 bound in bnd.UB (bnb.UB not in 1's complement form).\r\n F2 0F 1B /r RM V/NE MPX Generate a #BR if the address in r/m64 is higher than the upper\r\n BNDCN bnd, r/m64 bound in bnd.UB (bnb.UB not in 1's complement form).\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3\r\n RM ModRM:reg (w) ModRM:r/m (r) NA\r\n\r\nDescription\r\nCompare the address in the second operand with the upper bound in bnd. The second operand can be either a\r\nregister or a memory operand. If the address is higher than the upper bound in bnd.UB, it will set BNDSTATUS to\r\n01H and signal a #BR exception.\r\nBNDCU perform 1's complement operation on the upper bound of bnd first before proceeding with address compar-\r\nison. BNDCN perform address comparison directly using the upper bound in bnd that is already reverted out of 1's\r\ncomplement form.\r\nThis instruction does not cause any memory access, and does not read or write any flags.\r\nEffective address computation of m32/64 has identical behavior to LEA\r\n\r\nOperation\r\nBNDCU BND, reg\r\nIF reg > NOT(BND.UB) Then\r\n BNDSTATUS <- 01H;\r\n #BR;\r\nFI;\r\n\r\nBNDCU BND, mem\r\nTEMP <- LEA(mem);\r\nIF TEMP > NOT(BND.UB) Then\r\n BNDSTATUS <- 01H;\r\n #BR;\r\nFI;\r\n\r\nBNDCN BND, reg\r\nIF reg > BND.UB Then\r\n BNDSTATUS <- 01H;\r\n #BR;\r\nFI;\r\n\r\n\r\n\r\n\r\n\r\nBNDCN BND, mem\r\nTEMP <- LEA(mem);\r\nIF TEMP > BND.UB Then\r\n BNDSTATUS <- 01H;\r\n #BR;\r\nFI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBNDCU .void _bnd_chk_ptr_ubounds(const void *q)\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#BR If upper bound check fails.\r\n#UD If the LOCK prefix is used.\r\n If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n If 67H prefix is not used and CS.D=0.\r\n If 67H prefix is used and CS.D=1.\r\n\r\nReal-Address Mode Exceptions\r\n#BR If upper bound check fails.\r\n#UD If the LOCK prefix is used.\r\n If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n If 16-bit addressing is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#BR If upper bound check fails.\r\n#UD If the LOCK prefix is used.\r\n If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n If 16-bit addressing is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "BNDCU"
},
{
"description": "BNDLDX-Load Extended Bounds Using Address Translation\r\n Opcode/ Op/En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n 0F 1A /r RM V/V MPX Load the bounds stored in a bound table entry (BTE) into bnd with\r\n BNDLDX bnd, mib address translation using the base of mib and conditional on the\r\n index of mib matching the pointer value in the BTE.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3\r\n SIB.base (r): Address of pointer\r\n RM ModRM:reg (w) NA\r\n SIB.index(r)\r\n\r\nDescription\r\nBNDLDX uses the linear address constructed from the base register and displacement of the SIB-addressing form\r\nof the memory operand (mib) to perform address translation to access a bound table entry and conditionally load\r\nthe bounds in the BTE to the destination. The destination register is updated with the bounds in the BTE, if the\r\ncontent of the index register of mib matches the pointer value stored in the BTE.\r\nIf the pointer value comparison fails, the destination is updated with INIT bounds (lb = 0x0, ub = 0x0) (note: as\r\narticulated earlier, the upper bound is represented using 1's complement, therefore, the 0x0 value of upper bound\r\nallows for access to full memory).\r\nThis instruction does not cause memory access to the linear address of mib nor the effective address referenced by\r\nthe base, and does not read or write any flags.\r\nSegment overrides apply to the linear address computation with the base of mib, and are used during address\r\ntranslation to generate the address of the bound table entry. By default, the address of the BTE is assumed to be\r\nlinear address. There are no segmentation checks performed on the base of mib.\r\nThe base of mib will not be checked for canonical address violation as it does not access memory.\r\nAny encoding of this instruction that does not specify base or index register will treat those registers as zero\r\n(constant). The reg-reg form of this instruction will remain a NOP.\r\nThe scale field of the SIB byte has no effect on these instructions and is ignored.\r\nThe bound register may be partially updated on memory faults. The order in which memory operands are loaded is\r\nimplementation specific.\r\n\r\nOperation\r\nbase <- mib.SIB.base ? mib.SIB.base + Disp: 0;\r\nptr_value <- mib.SIB.index ? mib.SIB.index : 0;\r\n\r\nOutside 64-bit mode\r\nA_BDE[31:0] <- (Zero_extend32(base[31:12] << 2) + (BNDCFG[31:12] <<12 );\r\nA_BT[31:0] <- LoadFrom(A_BDE );\r\nIF A_BT[0] equal 0 Then\r\n BNDSTATUS <- A_BDE | 02H;\r\n #BR;\r\nFI;\r\nA_BTE[31:0] <- (Zero_extend32(base[11:2] << 4) + (A_BT[31:2] << 2 );\r\nTemp_lb[31:0] <- LoadFrom(A_BTE);\r\nTemp_ub[31:0] <- LoadFrom(A_BTE + 4);\r\nTemp_ptr[31:0] <- LoadFrom(A_BTE + 8);\r\nIF Temp_ptr equal ptr_value Then\r\n BND.LB <- Temp_lb;\r\n BND.UB <- Temp_ub;\r\n\r\n\r\n\r\nELSE\r\n BND.LB <- 0;\r\n BND.UB <- 0;\r\nFI;\r\n\r\nIn 64-bit mode\r\nA_BDE[63:0] <- (Zero_extend64(base[47+MAWA:20] << 3) + (BNDCFG[63:20] <<12 );1\r\nA_BT[63:0] <- LoadFrom(A_BDE);\r\nIF A_BT[0] equal 0 Then\r\n BNDSTATUS <- A_BDE | 02H;\r\n #BR;\r\nFI;\r\nA_BTE[63:0] <- (Zero_extend64(base[19:3] << 5) + (A_BT[63:3] << 3 );\r\nTemp_lb[63:0] <- LoadFrom(A_BTE);\r\nTemp_ub[63:0] <- LoadFrom(A_BTE + 8);\r\nTemp_ptr[63:0] <- LoadFrom(A_BTE + 16);\r\nIF Temp_ptr equal ptr_value Then\r\n BND.LB <- Temp_lb;\r\n BND.UB <- Temp_ub;\r\nELSE\r\n BND.LB <- 0;\r\n BND.UB <- 0;\r\nFI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBNDLDX: Generated by compiler as needed.\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#BR If the bound directory entry is invalid.\r\n#UD If the LOCK prefix is used.\r\n If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n If 67H prefix is not used and CS.D=0.\r\n If 67H prefix is used and CS.D=1.\r\n#GP(0) If a destination effective address of the Bound Table entry is outside the DS segment limit.\r\n If DS register contains a NULL segment selector.\r\n#PF(fault code) If a page fault occurs.\r\n\r\nReal-Address Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n If 16-bit addressing is used.\r\n#GP(0) If a destination effective address of the Bound Table entry is outside the DS segment limit.\r\n\r\n\r\n\r\n\r\n1. If CPL < 3, the supervisor MAWA (MAWAS) is used; this value is 0. If CPL = 3, the user MAWA (MAWAU) is used; this value is enumer-\r\n ated in CPUID.(EAX=07H,ECX=0H):ECX.MAWAU[bits 21:17]. See Section 17.3.1 of Intel 64 and IA-32 Architectures Software Devel-\r\n oper's Manual, Volume 1.\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n If 16-bit addressing is used.\r\n#GP(0) If a destination effective address of the Bound Table entry is outside the DS segment limit.\r\n#PF(fault code) If a page fault occurs.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#BR If the bound directory entry is invalid.\r\n#UD If ModRM is RIP relative.\r\n If the LOCK prefix is used.\r\n If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.\r\n#GP(0) If the memory address (A_BDE or A_BTE) is in a non-canonical form.\r\n#PF(fault code) If a page fault occurs.\r\n\r\n\r\n\r\n\r\n",
"mnem": "BNDLDX"
},
{
"description": "BNDMK-Make Bounds\r\n Opcode/ Op/En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n F3 0F 1B /r RM NE/V MPX Make lower and upper bounds from m32 and store them in bnd.\r\n BNDMK bnd, m32\r\n F3 0F 1B /r RM V/NE MPX Make lower and upper bounds from m64 and store them in bnd.\r\n BNDMK bnd, m64\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3\r\n RM ModRM:reg (w) ModRM:r/m (r) NA\r\n\r\nDescription\r\nMakes bounds from the second operand and stores the lower and upper bounds in the bound register bnd. The\r\nsecond operand must be a memory operand. The content of the base register from the memory operand is stored\r\nin the lower bound bnd.LB. The 1's complement of the effective address of m32/m64 is stored in the upper bound\r\nb.UB. Computation of m32/m64 has identical behavior to LEA.\r\nThis instruction does not cause any memory access, and does not read or write any flags.\r\nIf the instruction did not specify base register, the lower bound will be zero. The reg-reg form of this instruction\r\nretains legacy behavior (NOP).\r\nRIP relative instruction in 64-bit will #UD.\r\n\r\nOperation\r\nBND.LB <- SRCMEM.base;\r\nIF 64-bit mode Then\r\n BND.UB <- NOT(LEA.64_bits(SRCMEM));\r\nELSE\r\n BND.UB <- Zero_Extend.64_bits(NOT(LEA.32_bits(SRCMEM)));\r\nFI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBNDMKvoid * _bnd_set_ptr_bounds(const void * q, size_t size);\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#UD If ModRM is RIP relative.\r\n If the LOCK prefix is used.\r\n If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n If 67H prefix is not used and CS.D=0.\r\n If 67H prefix is used and CS.D=1.\r\n\r\nReal-Address Mode Exceptions\r\n#UD If ModRM is RIP relative.\r\n If the LOCK prefix is used.\r\n If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n If 16-bit addressing is used.\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD If ModRM is RIP relative.\r\n If the LOCK prefix is used.\r\n If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n If 16-bit addressing is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.\r\n#SS(0) If the memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "BNDMK"
},
{
"description": "BNDMOV-Move Bounds\r\n Opcode/ Op/En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n 66 0F 1A /r RM NE/V MPX Move lower and upper bound from bnd2/m64 to bound register\r\n BNDMOV bnd1, bnd2/m64 bnd1.\r\n 66 0F 1A /r RM V/NE MPX Move lower and upper bound from bnd2/m128 to bound register\r\n BNDMOV bnd1, bnd2/m128 bnd1.\r\n 66 0F 1B /r MR NE/V MPX Move lower and upper bound from bnd2 to bnd1/m64.\r\n BNDMOV bnd1/m64, bnd2\r\n 66 0F 1B /r MR V/NE MPX Move lower and upper bound from bnd2 to bound register\r\n BNDMOV bnd1/m128, bnd2 bnd1/m128.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3\r\n RM ModRM:reg (w) ModRM:r/m (r) NA\r\n MR ModRM:r/m (w) ModRM:reg (r) NA\r\n\r\nDescription\r\nBNDMOV moves a pair of lower and upper bound values from the source operand (the second operand) to the\r\ndestination (the first operand). Each operation is 128-bit move. The exceptions are same as the MOV instruction.\r\nThe memory format for loading/store bounds in 64-bit mode is shown in Figure 3-5.\r\n\r\n\r\n\r\n\r\n BNDMOV to memory in 64-bit mode\r\n Upper Bound (UB) Lower Bound (LB)\r\n\r\n\r\n 16 8 0 Byte offset\r\n\r\n\r\n\r\n\r\n BNDMOV to memory in 32-bit mode\r\n Upper Bound (UB) Lower Bound (LB)\r\n\r\n\r\n 16 8 4 0 Byte offset\r\n\r\n\r\n\r\n\r\n Figure 3-5. Memory Layout of BNDMOV to/from Memory\r\n\r\n\r\nThis instruction does not change flags.\r\n\r\nOperation\r\nBNDMOV register to register\r\nDEST.LB <- SRC.LB;\r\nDEST.UB <- SRC.UB;\r\n\r\n\r\n\r\n\r\n\r\nBNDMOV from memory\r\nIF 64-bit mode THEN\r\n DEST.LB <- LOAD_QWORD(SRC);\r\n DEST.UB <- LOAD_QWORD(SRC+8);\r\n ELSE\r\n DEST.LB <- LOAD_DWORD_ZERO_EXT(SRC);\r\n DEST.UB <- LOAD_DWORD_ZERO_EXT(SRC+4);\r\nFI;\r\n\r\nBNDMOV to memory\r\nIF 64-bit mode THEN\r\n DEST[63:0] <- SRC.LB;\r\n DEST[127:64] <- SRC.UB;\r\n ELSE\r\n DEST[31:0] <- SRC.LB;\r\n DEST[63:32] <- SRC.UB;\r\nFI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBNDMOV void * _bnd_copy_ptr_bounds(const void *q, const void *r)\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n If 67H prefix is not used and CS.D=0.\r\n If 67H prefix is used and CS.D=1.\r\n#SS(0) If the memory operand effective address is outside the SS segment limit.\r\n#GP(0) If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the destination operand points to a non-writable segment\r\n If the DS, ES, FS, or GS segment register contains a NULL segment selector.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while CPL is 3.\r\n#PF(fault code) If a page fault occurs.\r\n\r\nReal-Address Mode Exceptions\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n If 16-bit addressing is used.\r\n#GP(0) If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If the memory operand effective address is outside the SS segment limit.\r\n\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n If 16-bit addressing is used.\r\n#GP(0) If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If the memory operand effective address is outside the SS segment limit.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while CPL is 3.\r\n#PF(fault code) If a page fault occurs.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.\r\n#SS(0) If the memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while CPL is 3.\r\n#PF(fault code) If a page fault occurs.\r\n\r\n\r\n\r\n\r\n",
"mnem": "BNDMOV"
},
{
"description": "BNDSTX-Store Extended Bounds Using Address Translation\r\n Opcode/ Op/En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n 0F 1B /r MR V/V MPX Store the bounds in bnd and the pointer value in the index regis-\r\n BNDSTX mib, bnd ter of mib to a bound table entry (BTE) with address translation\r\n using the base of mib.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3\r\n SIB.base (r): Address of pointer\r\n MR ModRM:reg (r) NA\r\n SIB.index(r)\r\n\r\nDescription\r\nBNDSTX uses the linear address constructed from the displacement and base register of the SIB-addressing form\r\nof the memory operand (mib) to perform address translation to store to a bound table entry. The bounds in the\r\nsource operand bnd are written to the lower and upper bounds in the BTE. The content of the index register of mib\r\nis written to the pointer value field in the BTE.\r\nThis instruction does not cause memory access to the linear address of mib nor the effective address referenced by\r\nthe base, and does not read or write any flags.\r\nSegment overrides apply to the linear address computation with the base of mib, and are used during address\r\ntranslation to generate the address of the bound table entry. By default, the address of the BTE is assumed to be\r\nlinear address. There are no segmentation checks performed on the base of mib.\r\nThe base of mib will not be checked for canonical address violation as it does not access memory.\r\nAny encoding of this instruction that does not specify base or index register will treat those registers as zero\r\n(constant). The reg-reg form of this instruction will remain a NOP.\r\nThe scale field of the SIB byte has no effect on these instructions and is ignored.\r\nThe bound register may be partially updated on memory faults. The order in which memory operands are loaded is\r\nimplementation specific.\r\n\r\nOperation\r\nbase <- mib.SIB.base ? mib.SIB.base + Disp: 0;\r\nptr_value <- mib.SIB.index ? mib.SIB.index : 0;\r\n\r\nOutside 64-bit mode\r\nA_BDE[31:0] <- (Zero_extend32(base[31:12] << 2) + (BNDCFG[31:12] <<12 );\r\nA_BT[31:0] <- LoadFrom(A_BDE);\r\nIF A_BT[0] equal 0 Then\r\n BNDSTATUS <- A_BDE | 02H;\r\n #BR;\r\nFI;\r\nA_DEST[31:0] <- (Zero_extend32(base[11:2] << 4) + (A_BT[31:2] << 2 ); // address of Bound table entry\r\nA_DEST[8][31:0] <- ptr_value;\r\nA_DEST[0][31:0] <- BND.LB;\r\nA_DEST[4][31:0] <- BND.UB;\r\n\r\n\r\n\r\n\r\n\r\nIn 64-bit mode\r\nA_BDE[63:0] <- (Zero_extend64(base[47+MAWA:20] << 3) + (BNDCFG[63:20] <<12 );1\r\nA_BT[63:0] <- LoadFrom(A_BDE);\r\nIF A_BT[0] equal 0 Then\r\n BNDSTATUS <- A_BDE | 02H;\r\n #BR;\r\nFI;\r\nA_DEST[63:0] <- (Zero_extend64(base[19:3] << 5) + (A_BT[63:3] << 3 ); // address of Bound table entry\r\nA_DEST[16][63:0] <- ptr_value;\r\nA_DEST[0][63:0] <- BND.LB;\r\nA_DEST[8][63:0] <- BND.UB;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBNDSTX: _bnd_store_ptr_bounds(const void **ptr_addr, const void *ptr_val);\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#BR If the bound directory entry is invalid.\r\n#UD If the LOCK prefix is used.\r\n If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n If 67H prefix is not used and CS.D=0.\r\n If 67H prefix is used and CS.D=1.\r\n#GP(0) If a destination effective address of the Bound Table entry is outside the DS segment limit.\r\n If DS register contains a NULL segment selector.\r\n If the destination operand points to a non-writable segment\r\n#PF(fault code) If a page fault occurs.\r\n\r\nReal-Address Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n If 16-bit addressing is used.\r\n#GP(0) If a destination effective address of the Bound Table entry is outside the DS segment limit.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.\r\n If 16-bit addressing is used.\r\n#GP(0) If a destination effective address of the Bound Table entry is outside the DS segment limit.\r\n#PF(fault code) If a page fault occurs.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n1. If CPL < 3, the supervisor MAWA (MAWAS) is used; this value is 0. If CPL = 3, the user MAWA (MAWAU) is used; this value is enumer-\r\n ated in CPUID.(EAX=07H,ECX=0H):ECX.MAWAU[bits 21:17]. See Section 17.3.1 of Intel 64 and IA-32 Architectures Software Devel-\r\n oper's Manual, Volume 1.\r\n\r\n\r\n\r\n64-Bit Mode Exceptions\r\n#BR If the bound directory entry is invalid.\r\n#UD If ModRM is RIP relative.\r\n If the LOCK prefix is used.\r\n If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.\r\n#GP(0) If the memory address (A_BDE or A_BTE) is in a non-canonical form.\r\n If the destination operand points to a non-writable segment\r\n#PF(fault code) If a page fault occurs.\r\n\r\n\r\n\r\n\r\n",
"mnem": "BNDSTX"
},
{
"description": "BOUND-Check Array Index Against Bounds\r\nOpcode Instruction Op/ 64-bit Compat/ Description\r\n En Mode Leg Mode\r\n62 /r BOUND r16, m16&16 RM Invalid Valid Check if r16 (array index) is within bounds\r\n specified by m16&16.\r\n62 /r BOUND r32, m32&32 RM Invalid Valid Check if r32 (array index) is within bounds\r\n specified by m32&32.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nBOUND determines if the first operand (array index) is within the bounds of an array specified the second operand\r\n(bounds operand). The array index is a signed integer located in a register. The bounds operand is a memory loca-\r\ntion that contains a pair of signed doubleword-integers (when the operand-size attribute is 32) or a pair of signed\r\nword-integers (when the operand-size attribute is 16). The first doubleword (or word) is the lower bound of the\r\narray and the second doubleword (or word) is the upper bound of the array. The array index must be greater than\r\nor equal to the lower bound and less than or equal to the upper bound plus the operand size in bytes. If the index\r\nis not within bounds, a BOUND range exceeded exception (#BR) is signaled. When this exception is generated, the\r\nsaved return instruction pointer points to the BOUND instruction.\r\nThe bounds limit data structure (two words or doublewords containing the lower and upper limits of the array) is\r\nusually placed just before the array itself, making the limits addressable via a constant offset from the beginning of\r\nthe array. Because the address of the array already will be present in a register, this practice avoids extra bus cycles\r\nto obtain the effective address of the array bounds.\r\nThis instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.\r\n\r\nOperation\r\nIF 64bit Mode\r\n THEN\r\n #UD;\r\n ELSE\r\n IF (ArrayIndex < LowerBound OR ArrayIndex > UpperBound)\r\n (* Below lower bound or above upper bound *)\r\n THEN #BR; FI;\r\nFI;\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#BR If the bounds test fails.\r\n#UD If second operand is not a memory location.\r\n If the LOCK prefix is used.\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#BR If the bounds test fails.\r\n#UD If second operand is not a memory location.\r\n If the LOCK prefix is used.\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#BR If the bounds test fails.\r\n#UD If second operand is not a memory location.\r\n If the LOCK prefix is used.\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD If in 64-bit mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "BOUND"
},
{
"description": "BSF-Bit Scan Forward\r\n Opcode Instruction Op/ 64-bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F BC /r BSF r16, r/m16 RM Valid Valid Bit scan forward on r/m16.\r\n 0F BC /r BSF r32, r/m32 RM Valid Valid Bit scan forward on r/m32.\r\n REX.W + 0F BC /r BSF r64, r/m64 RM Valid N.E. Bit scan forward on r/m64.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nSearches the source operand (second operand) for the least significant set bit (1 bit). If a least significant 1 bit is\r\nfound, its bit index is stored in the destination operand (first operand). The source operand can be a register or a\r\nmemory location; the destination operand is a register. The bit index is an unsigned offset from bit 0 of the source\r\noperand. If the content of the source operand is 0, the content of the destination operand is undefined.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nIF SRC = 0\r\n THEN\r\n ZF <- 1;\r\n DEST is undefined;\r\n ELSE\r\n ZF <- 0;\r\n temp <- 0;\r\n WHILE Bit(SRC, temp) = 0\r\n DO\r\n temp <- temp + 1;\r\n OD;\r\n DEST <- temp;\r\nFI;\r\n\r\nFlags Affected\r\nThe ZF flag is set to 1 if all the source operand is 0; otherwise, the ZF flag is cleared. The CF, OF, SF, AF, and PF, flags\r\nare undefined.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "BSF"
},
{
"description": "BSR-Bit Scan Reverse\r\nOpcode Instruction Op/ 64-bit Compat/ Description\r\n En Mode Leg Mode\r\n0F BD /r BSR r16, r/m16 RM Valid Valid Bit scan reverse on r/m16.\r\n0F BD /r BSR r32, r/m32 RM Valid Valid Bit scan reverse on r/m32.\r\nREX.W + 0F BD /r BSR r64, r/m64 RM Valid N.E. Bit scan reverse on r/m64.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nSearches the source operand (second operand) for the most significant set bit (1 bit). If a most significant 1 bit is\r\nfound, its bit index is stored in the destination operand (first operand). The source operand can be a register or a\r\nmemory location; the destination operand is a register. The bit index is an unsigned offset from bit 0 of the source\r\noperand. If the content source operand is 0, the content of the destination operand is undefined.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nIF SRC = 0\r\n THEN\r\n ZF <- 1;\r\n DEST is undefined;\r\n ELSE\r\n ZF <- 0;\r\n temp <- OperandSize - 1;\r\n WHILE Bit(SRC, temp) = 0\r\n DO\r\n temp <- temp - 1;\r\n OD;\r\n DEST <- temp;\r\nFI;\r\n\r\nFlags Affected\r\nThe ZF flag is set to 1 if all the source operand is 0; otherwise, the ZF flag is cleared. The CF, OF, SF, AF, and PF, flags\r\nare undefined.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "BSR"
},
{
"description": "BSWAP-Byte Swap\r\nOpcode Instruction Op/ 64-bit Compat/ Description\r\n En Mode Leg Mode\r\n0F C8+rd BSWAP r32 O Valid* Valid Reverses the byte order of a 32-bit register.\r\nREX.W + 0F C8+rd BSWAP r64 O Valid N.E. Reverses the byte order of a 64-bit register.\r\nNOTES:\r\n* See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n O opcode + rd (r, w) NA NA NA\r\n\r\nDescription\r\nReverses the byte order of a 32-bit or 64-bit (destination) register. This instruction is provided for converting little-\r\nendian values to big-endian format and vice versa. To swap bytes in a word value (16-bit register), use the XCHG\r\ninstruction. When the BSWAP instruction references a 16-bit register, the result is undefined.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\n\r\nIA-32 Architecture Legacy Compatibility\r\nThe BSWAP instruction is not supported on IA-32 processors earlier than the Intel486 processor family. For\r\ncompatibility with this instruction, software should include functionally equivalent code for execution on Intel\r\nprocessors earlier than the Intel486 processor family.\r\n\r\nOperation\r\nTEMP <- DEST\r\nIF 64-bit mode AND OperandSize = 64\r\n THEN\r\n DEST[7:0] <- TEMP[63:56];\r\n DEST[15:8] <- TEMP[55:48];\r\n DEST[23:16] <- TEMP[47:40];\r\n DEST[31:24] <- TEMP[39:32];\r\n DEST[39:32] <- TEMP[31:24];\r\n DEST[47:40] <- TEMP[23:16];\r\n DEST[55:48] <- TEMP[15:8];\r\n DEST[63:56] <- TEMP[7:0];\r\n ELSE\r\n DEST[7:0] <- TEMP[31:24];\r\n DEST[15:8] <- TEMP[23:16];\r\n DEST[23:16] <- TEMP[15:8];\r\n DEST[31:24] <- TEMP[7:0];\r\nFI;\r\n\r\nFlags Affected\r\nNone.\r\n\r\nExceptions (All Operating Modes)\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n",
"mnem": "BSWAP"
},
{
"description": "BT-Bit Test\r\n Opcode Instruction Op/ 64-bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F A3 /r BT r/m16, r16 MR Valid Valid Store selected bit in CF flag.\r\n 0F A3 /r BT r/m32, r32 MR Valid Valid Store selected bit in CF flag.\r\n REX.W + 0F A3 /r BT r/m64, r64 MR Valid N.E. Store selected bit in CF flag.\r\n 0F BA /4 ib BT r/m16, imm8 MI Valid Valid Store selected bit in CF flag.\r\n 0F BA /4 ib BT r/m32, imm8 MI Valid Valid Store selected bit in CF flag.\r\n REX.W + 0F BA /4 ib BT r/m64, imm8 MI Valid N.E. Store selected bit in CF flag.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n MR ModRM:r/m (r) ModRM:reg (r) NA NA\r\n MI ModRM:r/m (r) imm8 NA NA\r\n\r\nDescription\r\nSelects the bit in a bit string (specified with the first operand, called the bit base) at the bit-position designated by\r\nthe bit offset (specified by the second operand) and stores the value of the bit in the CF flag. The bit base operand\r\ncan be a register or a memory location; the bit offset operand can be a register or an immediate value:\r\n. If the bit base operand specifies a register, the instruction takes the modulo 16, 32, or 64 of the bit offset\r\n operand (modulo size depends on the mode and register size; 64-bit operands are available only in 64-bit\r\n mode).\r\n. If the bit base operand specifies a memory location, the operand represents the address of the byte in memory\r\n that contains the bit base (bit 0 of the specified byte) of the bit string. The range of the bit position that can be\r\n referenced by the offset operand depends on the operand size.\r\nSee also: Bit(BitBase, BitOffset) on page 3-11.\r\nSome assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combina-\r\ntion with the displacement field of the memory operand. In this case, the low-order 3 or 5 bits (3 for 16-bit oper-\r\nands, 5 for 32-bit operands) of the immediate bit offset are stored in the immediate bit offset field, and the high-\r\norder bits are shifted and combined with the byte displacement in the addressing mode by the assembler. The\r\nprocessor will ignore the high order bits if they are not zero.\r\nWhen accessing a bit in memory, the processor may access 4 bytes starting from the memory address for a 32-bit\r\noperand size, using by the following relationship:\r\n\r\n Effective Address + (4 * (BitOffset DIV 32))\r\nOr, it may access 2 bytes starting from the memory address for a 16-bit operand, using this relationship:\r\n\r\n Effective Address + (2 * (BitOffset DIV 16))\r\nIt may do so even when only a single byte needs to be accessed to reach the given bit. When using this bit\r\naddressing mechanism, software should avoid referencing areas of memory close to address space holes. In partic-\r\nular, it should avoid references to memory-mapped I/O registers. Instead, software should use the MOV instruc-\r\ntions to load from or store to these addresses, and use the register form of these instructions to manipulate the\r\ndata.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bit oper-\r\nands. See the summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nCF <- Bit(BitBase, BitOffset);\r\n\r\n\r\n\r\nFlags Affected\r\nThe CF flag contains the value of the selected bit. The ZF flag is unaffected. The OF, SF, AF, and PF flags are\r\nundefined.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "BT"
},
{
"description": "BTC-Bit Test and Complement\r\n Opcode Instruction Op/ 64-bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F BB /r BTC r/m16, r16 MR Valid Valid Store selected bit in CF flag and complement.\r\n 0F BB /r BTC r/m32, r32 MR Valid Valid Store selected bit in CF flag and complement.\r\n REX.W + 0F BB /r BTC r/m64, r64 MR Valid N.E. Store selected bit in CF flag and complement.\r\n 0F BA /7 ib BTC r/m16, imm8 MI Valid Valid Store selected bit in CF flag and complement.\r\n 0F BA /7 ib BTC r/m32, imm8 MI Valid Valid Store selected bit in CF flag and complement.\r\n REX.W + 0F BA /7 ib BTC r/m64, imm8 MI Valid N.E. Store selected bit in CF flag and complement.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n MR ModRM:r/m (r, w) ModRM:reg (r) NA NA\r\n MI ModRM:r/m (r, w) imm8 NA NA\r\n\r\nDescription\r\nSelects the bit in a bit string (specified with the first operand, called the bit base) at the bit-position designated by\r\nthe bit offset operand (second operand), stores the value of the bit in the CF flag, and complements the selected\r\nbit in the bit string. The bit base operand can be a register or a memory location; the bit offset operand can be a\r\nregister or an immediate value:\r\n. If the bit base operand specifies a register, the instruction takes the modulo 16, 32, or 64 of the bit offset\r\n operand (modulo size depends on the mode and register size; 64-bit operands are available only in 64-bit\r\n mode). This allows any bit position to be selected.\r\n. If the bit base operand specifies a memory location, the operand represents the address of the byte in memory\r\n that contains the bit base (bit 0 of the specified byte) of the bit string. The range of the bit position that can be\r\n referenced by the offset operand depends on the operand size.\r\nSee also: Bit(BitBase, BitOffset) on page 3-11.\r\nSome assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combina-\r\ntion with the displacement field of the memory operand. See \"BT-Bit Test\" in this chapter for more information on\r\nthis addressing mechanism.\r\nThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nCF <- Bit(BitBase, BitOffset);\r\nBit(BitBase, BitOffset) <- NOT Bit(BitBase, BitOffset);\r\n\r\nFlags Affected\r\nThe CF flag contains the value of the selected bit before it is complemented. The ZF flag is unaffected. The OF, SF,\r\nAF, and PF flags are undefined.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination operand points to a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n",
"mnem": "BTC"
},
{
"description": "BTR-Bit Test and Reset\r\n Opcode Instruction Op/ 64-bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F B3 /r BTR r/m16, r16 MR Valid Valid Store selected bit in CF flag and clear.\r\n 0F B3 /r BTR r/m32, r32 MR Valid Valid Store selected bit in CF flag and clear.\r\n REX.W + 0F B3 /r BTR r/m64, r64 MR Valid N.E. Store selected bit in CF flag and clear.\r\n 0F BA /6 ib BTR r/m16, imm8 MI Valid Valid Store selected bit in CF flag and clear.\r\n 0F BA /6 ib BTR r/m32, imm8 MI Valid Valid Store selected bit in CF flag and clear.\r\n REX.W + 0F BA /6 ib BTR r/m64, imm8 MI Valid N.E. Store selected bit in CF flag and clear.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n MR ModRM:r/m (r, w) ModRM:reg (r) NA NA\r\n MI ModRM:r/m (r, w) imm8 NA NA\r\n\r\nDescription\r\nSelects the bit in a bit string (specified with the first operand, called the bit base) at the bit-position designated by\r\nthe bit offset operand (second operand), stores the value of the bit in the CF flag, and clears the selected bit in the\r\nbit string to 0. The bit base operand can be a register or a memory location; the bit offset operand can be a register\r\nor an immediate value:\r\n. If the bit base operand specifies a register, the instruction takes the modulo 16, 32, or 64 of the bit offset\r\n operand (modulo size depends on the mode and register size; 64-bit operands are available only in 64-bit\r\n mode). This allows any bit position to be selected.\r\n. If the bit base operand specifies a memory location, the operand represents the address of the byte in memory\r\n that contains the bit base (bit 0 of the specified byte) of the bit string. The range of the bit position that can be\r\n referenced by the offset operand depends on the operand size.\r\nSee also: Bit(BitBase, BitOffset) on page 3-11.\r\nSome assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combina-\r\ntion with the displacement field of the memory operand. See \"BT-Bit Test\" in this chapter for more information on\r\nthis addressing mechanism.\r\nThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nCF <- Bit(BitBase, BitOffset);\r\nBit(BitBase, BitOffset) <- 0;\r\n\r\nFlags Affected\r\nThe CF flag contains the value of the selected bit before it is cleared. The ZF flag is unaffected. The OF, SF, AF, and\r\nPF flags are undefined.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination operand points to a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n",
"mnem": "BTR"
},
{
"description": "BTS-Bit Test and Set\r\n Opcode Instruction Op/ 64-bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F AB /r BTS r/m16, r16 MR Valid Valid Store selected bit in CF flag and set.\r\n 0F AB /r BTS r/m32, r32 MR Valid Valid Store selected bit in CF flag and set.\r\n REX.W + 0F AB /r BTS r/m64, r64 MR Valid N.E. Store selected bit in CF flag and set.\r\n 0F BA /5 ib BTS r/m16, imm8 MI Valid Valid Store selected bit in CF flag and set.\r\n 0F BA /5 ib BTS r/m32, imm8 MI Valid Valid Store selected bit in CF flag and set.\r\n REX.W + 0F BA /5 ib BTS r/m64, imm8 MI Valid N.E. Store selected bit in CF flag and set.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n MR ModRM:r/m (r, w) ModRM:reg (r) NA NA\r\n MI ModRM:r/m (r, w) imm8 NA NA\r\n\r\nDescription\r\nSelects the bit in a bit string (specified with the first operand, called the bit base) at the bit-position designated by\r\nthe bit offset operand (second operand), stores the value of the bit in the CF flag, and sets the selected bit in the\r\nbit string to 1. The bit base operand can be a register or a memory location; the bit offset operand can be a register\r\nor an immediate value:\r\n. If the bit base operand specifies a register, the instruction takes the modulo 16, 32, or 64 of the bit offset\r\n operand (modulo size depends on the mode and register size; 64-bit operands are available only in 64-bit\r\n mode). This allows any bit position to be selected.\r\n. If the bit base operand specifies a memory location, the operand represents the address of the byte in memory\r\n that contains the bit base (bit 0 of the specified byte) of the bit string. The range of the bit position that can be\r\n referenced by the offset operand depends on the operand size.\r\nSee also: Bit(BitBase, BitOffset) on page 3-11.\r\nSome assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combina-\r\ntion with the displacement field of the memory operand. See \"BT-Bit Test\" in this chapter for more information on\r\nthis addressing mechanism.\r\nThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nCF <- Bit(BitBase, BitOffset);\r\nBit(BitBase, BitOffset) <- 1;\r\n\r\nFlags Affected\r\nThe CF flag contains the value of the selected bit before it is set. The ZF flag is unaffected. The OF, SF, AF, and PF\r\nflags are undefined.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination operand points to a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n",
"mnem": "BTS"
},
{
"description": "BZHI - Zero High Bits Starting with Specified Bit Position\r\n Opcode/Instruction Op/ 64/32 CPUID Description\r\n En -bit Feature\r\n Mode Flag\r\n VEX.NDS.LZ.0F38.W0 F5 /r RMV V/V BMI2 Zero bits in r/m32 starting with the position in r32b, write result to\r\n BZHI r32a, r/m32, r32b r32a.\r\n VEX.NDS.LZ.0F38.W1 F5 /r RMV V/N.E. BMI2 Zero bits in r/m64 starting with the position in r64b, write result to\r\n BZHI r64a, r/m64, r64b r64a.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMV ModRM:reg (w) ModRM:r/m (r) VEX.vvvv (r) NA\r\n\r\nDescription\r\nBZHI copies the bits of the first source operand (the second operand) into the destination operand (the first\r\noperand) and clears the higher bits in the destination according to the INDEX value specified by the second source\r\noperand (the third operand). The INDEX is specified by bits 7:0 of the second source operand. The INDEX value is\r\nsaturated at the value of OperandSize -1. CF is set, if the number contained in the 8 low bits of the third operand\r\nis greater than OperandSize -1.\r\nThis instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in\r\n64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An\r\nattempt to execute this instruction with VEX.L not equal to 0 will cause #UD.\r\n\r\nOperation\r\nN <- SRC2[7:0]\r\nDEST <- SRC1\r\nIF (N < OperandSize)\r\n DEST[OperandSize-1:N] <- 0\r\nFI\r\nIF (N > OperandSize - 1)\r\n CF <- 1\r\nELSE\r\n CF <- 0\r\nFI\r\n\r\nFlags Affected\r\nZF, CF and SF flags are updated based on the result. OF flag is cleared. AF and PF flags are undefined.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nBZHI: unsigned __int32 _bzhi_u32(unsigned __int32 src, unsigned __int32 index);\r\n\r\nBZHI: unsigned __int64 _bzhi_u64(unsigned __int64 src, unsigned __int32 index);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Section 2.5.1, \"Exception Conditions for VEX-Encoded GPR Instructions\", Table 2-29; additionally\r\n#UD If VEX.W = 1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "BZHI"
},
{
"description": "CALL-Call Procedure\r\n Opcode Instruction Op/ 64-bit Compat/ Description\r\n En Mode Leg Mode\r\n E8 cw CALL rel16 M N.S. Valid Call near, relative, displacement relative to next\r\n instruction.\r\n E8 cd CALL rel32 M Valid Valid Call near, relative, displacement relative to next\r\n instruction. 32-bit displacement sign extended to\r\n 64-bits in 64-bit mode.\r\n FF /2 CALL r/m16 M N.E. Valid Call near, absolute indirect, address given in r/m16.\r\n FF /2 CALL r/m32 M N.E. Valid Call near, absolute indirect, address given in r/m32.\r\n FF /2 CALL r/m64 M Valid N.E. Call near, absolute indirect, address given in r/m64.\r\n 9A cd CALL ptr16:16 D Invalid Valid Call far, absolute, address given in operand.\r\n 9A cp CALL ptr16:32 D Invalid Valid Call far, absolute, address given in operand.\r\n FF /3 CALL m16:16 M Valid Valid Call far, absolute indirect address given in m16:16.\r\n In 32-bit mode: if selector points to a gate, then RIP\r\n = 32-bit zero extended displacement taken from\r\n gate; else RIP = zero extended 16-bit offset from\r\n far pointer referenced in the instruction.\r\n FF /3 CALL m16:32 M Valid Valid In 64-bit mode: If selector points to a gate, then RIP\r\n = 64-bit displacement taken from gate; else RIP =\r\n zero extended 32-bit offset from far pointer\r\n referenced in the instruction.\r\n REX.W + FF /3 CALL m16:64 M Valid N.E. In 64-bit mode: If selector points to a gate, then RIP\r\n = 64-bit displacement taken from gate; else RIP =\r\n 64-bit offset from far pointer referenced in the\r\n instruction.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n D Offset NA NA NA\r\n M ModRM:r/m (r) NA NA NA\r\n\r\nDescription\r\nSaves procedure linking information on the stack and branches to the called procedure specified using the target\r\noperand. The target operand specifies the address of the first instruction in the called procedure. The operand can\r\nbe an immediate value, a general-purpose register, or a memory location.\r\nThis instruction can be used to execute four types of calls:\r\n. Near Call - A call to a procedure in the current code segment (the segment currently pointed to by the CS\r\n register), sometimes referred to as an intra-segment call.\r\n. Far Call - A call to a procedure located in a different segment than the current code segment, sometimes\r\n referred to as an inter-segment call.\r\n. Inter-privilege-level far call - A far call to a procedure in a segment at a different privilege level than that\r\n of the currently executing program or procedure.\r\n. Task switch - A call to a procedure located in a different task.\r\nThe latter two call types (inter-privilege-level call and task switch) can only be executed in protected mode. See\r\n\"Calling Procedures Using Call and RET\" in Chapter 6 of the Intel 64 and IA-32 Architectures Software Devel-\r\noper's Manual, Volume 1, for additional information on near, far, and inter-privilege-level calls. See Chapter 7,\r\n\"Task Management,\" in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, for infor-\r\nmation on performing task switches with the CALL instruction.\r\n\r\n\r\n\r\nNear Call. When executing a near call, the processor pushes the value of the EIP register (which contains the offset\r\nof the instruction following the CALL instruction) on the stack (for use later as a return-instruction pointer). The\r\nprocessor then branches to the address in the current code segment specified by the target operand. The target\r\noperand specifies either an absolute offset in the code segment (an offset from the base of the code segment) or a\r\nrelative offset (a signed displacement relative to the current value of the instruction pointer in the EIP register; this\r\nvalue points to the instruction following the CALL instruction). The CS register is not changed on near calls.\r\nFor a near call absolute, an absolute offset is specified indirectly in a general-purpose register or a memory location\r\n(r/m16, r/m32, or r/m64). The operand-size attribute determines the size of the target operand (16, 32 or 64\r\nbits). When in 64-bit mode, the operand size for near call (and all near branches) is forced to 64-bits. Absolute\r\noffsets are loaded directly into the EIP(RIP) register. If the operand size attribute is 16, the upper two bytes of the\r\nEIP register are cleared, resulting in a maximum instruction pointer size of 16 bits. When accessing an absolute\r\noffset indirectly using the stack pointer [ESP] as the base register, the base value used is the value of the ESP\r\nbefore the instruction executes.\r\nA relative offset (rel16 or rel32) is generally specified as a label in assembly code. But at the machine code level, it\r\nis encoded as a signed, 16- or 32-bit immediate value. This value is added to the value in the EIP(RIP) register. In\r\n64-bit mode the relative offset is always a 32-bit immediate value which is sign extended to 64-bits before it is\r\nadded to the value in the RIP register for the target calculation. As with absolute offsets, the operand-size attribute\r\ndetermines the size of the target operand (16, 32, or 64 bits). In 64-bit mode the target operand will always be 64-\r\nbits because the operand size is forced to 64-bits for near branches.\r\nFar Calls in Real-Address or Virtual-8086 Mode. When executing a far call in real- address or virtual-8086 mode, the\r\nprocessor pushes the current value of both the CS and EIP registers on the stack for use as a return-instruction\r\npointer. The processor then performs a \"far branch\" to the code segment and offset specified with the target\r\noperand for the called procedure. The target operand specifies an absolute far address either directly with a pointer\r\n(ptr16:16 or ptr16:32) or indirectly with a memory location (m16:16 or m16:32). With the pointer method, the\r\nsegment and offset of the called procedure is encoded in the instruction using a 4-byte (16-bit operand size) or 6-\r\nbyte (32-bit operand size) far address immediate. With the indirect method, the target operand specifies a memory\r\nlocation that contains a 4-byte (16-bit operand size) or 6-byte (32-bit operand size) far address. The operand-size\r\nattribute determines the size of the offset (16 or 32 bits) in the far address. The far address is loaded directly into\r\nthe CS and EIP registers. If the operand-size attribute is 16, the upper two bytes of the EIP register are cleared.\r\nFar Calls in Protected Mode. When the processor is operating in protected mode, the CALL instruction can be used to\r\nperform the following types of far calls:\r\n. Far call to the same privilege level\r\n. Far call to a different privilege level (inter-privilege level call)\r\n. Task switch (far call to another task)\r\nIn protected mode, the processor always uses the segment selector part of the far address to access the corre-\r\nsponding descriptor in the GDT or LDT. The descriptor type (code segment, call gate, task gate, or TSS) and access\r\nrights determine the type of call operation to be performed.\r\nIf the selected descriptor is for a code segment, a far call to a code segment at the same privilege level is\r\nperformed. (If the selected code segment is at a different privilege level and the code segment is non-conforming,\r\na general-protection exception is generated.) A far call to the same privilege level in protected mode is very similar\r\nto one carried out in real-address or virtual-8086 mode. The target operand specifies an absolute far address either\r\ndirectly with a pointer (ptr16:16 or ptr16:32) or indirectly with a memory location (m16:16 or m16:32). The\r\noperand- size attribute determines the size of the offset (16 or 32 bits) in the far address. The new code segment\r\nselector and its descriptor are loaded into CS register; the offset from the instruction is loaded into the EIP register.\r\nA call gate (described in the next paragraph) can also be used to perform a far call to a code segment at the same\r\nprivilege level. Using this mechanism provides an extra level of indirection and is the preferred method of making\r\ncalls between 16-bit and 32-bit code segments.\r\nWhen executing an inter-privilege-level far call, the code segment for the procedure being called must be accessed\r\nthrough a call gate. The segment selector specified by the target operand identifies the call gate. The target\r\noperand can specify the call gate segment selector either directly with a pointer (ptr16:16 or ptr16:32) or indirectly\r\nwith a memory location (m16:16 or m16:32). The processor obtains the segment selector for the new code\r\nsegment and the new instruction pointer (offset) from the call gate descriptor. (The offset from the target operand\r\nis ignored when a call gate is used.)\r\n\r\n\r\n\r\n\r\nOn inter-privilege-level calls, the processor switches to the stack for the privilege level of the called procedure. The\r\nsegment selector for the new stack segment is specified in the TSS for the currently running task. The branch to\r\nthe new code segment occurs after the stack switch. (Note that when using a call gate to perform a far call to a\r\nsegment at the same privilege level, no stack switch occurs.) On the new stack, the processor pushes the segment\r\nselector and stack pointer for the calling procedure's stack, an optional set of parameters from the calling proce-\r\ndures stack, and the segment selector and instruction pointer for the calling procedure's code segment. (A value in\r\nthe call gate descriptor determines how many parameters to copy to the new stack.) Finally, the processor\r\nbranches to the address of the procedure being called within the new code segment.\r\nExecuting a task switch with the CALL instruction is similar to executing a call through a call gate. The target\r\noperand specifies the segment selector of the task gate for the new task activated by the switch (the offset in the\r\ntarget operand is ignored). The task gate in turn points to the TSS for the new task, which contains the segment\r\nselectors for the task's code and stack segments. Note that the TSS also contains the EIP value for the next instruc-\r\ntion that was to be executed before the calling task was suspended. This instruction pointer value is loaded into the\r\nEIP register to re-start the calling task.\r\nThe CALL instruction can also specify the segment selector of the TSS directly, which eliminates the indirection of\r\nthe task gate. See Chapter 7, \"Task Management,\" in the Intel 64 and IA-32 Architectures Software Developer's\r\nManual, Volume 3A, for information on the mechanics of a task switch.\r\nWhen you execute at task switch with a CALL instruction, the nested task flag (NT) is set in the EFLAGS register and\r\nthe new TSS's previous task link field is loaded with the old task's TSS selector. Code is expected to suspend this\r\nnested task by executing an IRET instruction which, because the NT flag is set, automatically uses the previous\r\ntask link to return to the calling task. (See \"Task Linking\" in Chapter 7 of the Intel 64 and IA-32 Architectures\r\nSoftware Developer's Manual, Volume 3A, for information on nested tasks.) Switching tasks with the CALL instruc-\r\ntion differs in this regard from JMP instruction. JMP does not set the NT flag and therefore does not expect an IRET\r\ninstruction to suspend the task.\r\nMixing 16-Bit and 32-Bit Calls. When making far calls between 16-bit and 32-bit code segments, use a call gate. If\r\nthe far call is from a 32-bit code segment to a 16-bit code segment, the call should be made from the first 64\r\nKBytes of the 32-bit code segment. This is because the operand-size attribute of the instruction is set to 16, so only\r\na 16-bit return address offset can be saved. Also, the call should be made using a 16-bit call gate so that 16-bit\r\nvalues can be pushed on the stack. See Chapter 21, \"Mixing 16-Bit and 32-Bit Code,\" in the Intel 64 and IA-32\r\nArchitectures Software Developer's Manual, Volume 3B, for more information.\r\nFar Calls in Compatibility Mode. When the processor is operating in compatibility mode, the CALL instruction can be\r\nused to perform the following types of far calls:\r\n. Far call to the same privilege level, remaining in compatibility mode\r\n. Far call to the same privilege level, transitioning to 64-bit mode\r\n. Far call to a different privilege level (inter-privilege level call), transitioning to 64-bit mode\r\nNote that a CALL instruction can not be used to cause a task switch in compatibility mode since task switches are\r\nnot supported in IA-32e mode.\r\nIn compatibility mode, the processor always uses the segment selector part of the far address to access the corre-\r\nsponding descriptor in the GDT or LDT. The descriptor type (code segment, call gate) and access rights determine\r\nthe type of call operation to be performed.\r\nIf the selected descriptor is for a code segment, a far call to a code segment at the same privilege level is\r\nperformed. (If the selected code segment is at a different privilege level and the code segment is non-conforming,\r\na general-protection exception is generated.) A far call to the same privilege level in compatibility mode is very\r\nsimilar to one carried out in protected mode. The target operand specifies an absolute far address either directly\r\nwith a pointer (ptr16:16 or ptr16:32) or indirectly with a memory location (m16:16 or m16:32). The operand-size\r\nattribute determines the size of the offset (16 or 32 bits) in the far address. The new code segment selector and its\r\ndescriptor are loaded into CS register and the offset from the instruction is loaded into the EIP register. The differ-\r\nence is that 64-bit mode may be entered. This specified by the L bit in the new code segment descriptor.\r\nNote that a 64-bit call gate (described in the next paragraph) can also be used to perform a far call to a code\r\nsegment at the same privilege level. However, using this mechanism requires that the target code segment\r\ndescriptor have the L bit set, causing an entry to 64-bit mode.\r\nWhen executing an inter-privilege-level far call, the code segment for the procedure being called must be accessed\r\nthrough a 64-bit call gate. The segment selector specified by the target operand identifies the call gate. The target\r\n\r\n\r\n\r\noperand can specify the call gate segment selector either directly with a pointer (ptr16:16 or ptr16:32) or indirectly\r\nwith a memory location (m16:16 or m16:32). The processor obtains the segment selector for the new code\r\nsegment and the new instruction pointer (offset) from the 16-byte call gate descriptor. (The offset from the target\r\noperand is ignored when a call gate is used.)\r\nOn inter-privilege-level calls, the processor switches to the stack for the privilege level of the called procedure. The\r\nsegment selector for the new stack segment is set to NULL. The new stack pointer is specified in the TSS for the\r\ncurrently running task. The branch to the new code segment occurs after the stack switch. (Note that when using\r\na call gate to perform a far call to a segment at the same privilege level, an implicit stack switch occurs as a result\r\nof entering 64-bit mode. The SS selector is unchanged, but stack segment accesses use a segment base of 0x0,\r\nthe limit is ignored, and the default stack size is 64-bits. The full value of RSP is used for the offset, of which the\r\nupper 32-bits are undefined.) On the new stack, the processor pushes the segment selector and stack pointer for\r\nthe calling procedure's stack and the segment selector and instruction pointer for the calling procedure's code\r\nsegment. (Parameter copy is not supported in IA-32e mode.) Finally, the processor branches to the address of the\r\nprocedure being called within the new code segment.\r\nNear/(Far) Calls in 64-bit Mode. When the processor is operating in 64-bit mode, the CALL instruction can be used to\r\nperform the following types of far calls:\r\n. Far call to the same privilege level, transitioning to compatibility mode\r\n. Far call to the same privilege level, remaining in 64-bit mode\r\n. Far call to a different privilege level (inter-privilege level call), remaining in 64-bit mode\r\nNote that in this mode the CALL instruction can not be used to cause a task switch in 64-bit mode since task\r\nswitches are not supported in IA-32e mode.\r\nIn 64-bit mode, the processor always uses the segment selector part of the far address to access the corresponding\r\ndescriptor in the GDT or LDT. The descriptor type (code segment, call gate) and access rights determine the type\r\nof call operation to be performed.\r\nIf the selected descriptor is for a code segment, a far call to a code segment at the same privilege level is\r\nperformed. (If the selected code segment is at a different privilege level and the code segment is non-conforming,\r\na general-protection exception is generated.) A far call to the same privilege level in 64-bit mode is very similar to\r\none carried out in compatibility mode. The target operand specifies an absolute far address indirectly with a\r\nmemory location (m16:16, m16:32 or m16:64). The form of CALL with a direct specification of absolute far\r\naddress is not defined in 64-bit mode. The operand-size attribute determines the size of the offset (16, 32, or 64\r\nbits) in the far address. The new code segment selector and its descriptor are loaded into the CS register; the offset\r\nfrom the instruction is loaded into the EIP register. The new code segment may specify entry either into compati-\r\nbility or 64-bit mode, based on the L bit value.\r\nA 64-bit call gate (described in the next paragraph) can also be used to perform a far call to a code segment at the\r\nsame privilege level. However, using this mechanism requires that the target code segment descriptor have the L\r\nbit set.\r\nWhen executing an inter-privilege-level far call, the code segment for the procedure being called must be accessed\r\nthrough a 64-bit call gate. The segment selector specified by the target operand identifies the call gate. The target\r\noperand can only specify the call gate segment selector indirectly with a memory location (m16:16, m16:32 or\r\nm16:64). The processor obtains the segment selector for the new code segment and the new instruction pointer\r\n(offset) from the 16-byte call gate descriptor. (The offset from the target operand is ignored when a call gate is\r\nused.)\r\nOn inter-privilege-level calls, the processor switches to the stack for the privilege level of the called procedure. The\r\nsegment selector for the new stack segment is set to NULL. The new stack pointer is specified in the TSS for the\r\ncurrently running task. The branch to the new code segment occurs after the stack switch.\r\nNote that when using a call gate to perform a far call to a segment at the same privilege level, an implicit stack\r\nswitch occurs as a result of entering 64-bit mode. The SS selector is unchanged, but stack segment accesses use\r\na segment base of 0x0, the limit is ignored, and the default stack size is 64-bits. (The full value of RSP is used for\r\nthe offset.) On the new stack, the processor pushes the segment selector and stack pointer for the calling proce-\r\ndure's stack and the segment selector and instruction pointer for the calling procedure's code segment. (Parameter\r\ncopy is not supported in IA-32e mode.) Finally, the processor branches to the address of the procedure being called\r\nwithin the new code segment.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIF near call\r\n THEN IF near relative call\r\n THEN\r\n IF OperandSize = 64\r\n THEN\r\n tempDEST <- SignExtend(DEST); (* DEST is rel32 *)\r\n tempRIP <- RIP + tempDEST;\r\n IF stack not large enough for a 8-byte return address\r\n THEN #SS(0); FI;\r\n Push(RIP);\r\n RIP <- tempRIP;\r\n FI;\r\n IF OperandSize = 32\r\n THEN\r\n tempEIP <- EIP + DEST; (* DEST is rel32 *)\r\n IF tempEIP is not within code segment limit THEN #GP(0); FI;\r\n IF stack not large enough for a 4-byte return address\r\n THEN #SS(0); FI;\r\n Push(EIP);\r\n EIP <- tempEIP;\r\n FI;\r\n IF OperandSize = 16\r\n THEN\r\n tempEIP <- (EIP + DEST) AND 0000FFFFH; (* DEST is rel16 *)\r\n IF tempEIP is not within code segment limit THEN #GP(0); FI;\r\n IF stack not large enough for a 2-byte return address\r\n THEN #SS(0); FI;\r\n Push(IP);\r\n EIP <- tempEIP;\r\n FI;\r\n ELSE (* Near absolute call *)\r\n IF OperandSize = 64\r\n THEN\r\n tempRIP <- DEST; (* DEST is r/m64 *)\r\n IF stack not large enough for a 8-byte return address\r\n THEN #SS(0); FI;\r\n Push(RIP);\r\n RIP <- tempRIP;\r\n FI;\r\n IF OperandSize = 32\r\n THEN\r\n tempEIP <- DEST; (* DEST is r/m32 *)\r\n IF tempEIP is not within code segment limit THEN #GP(0); FI;\r\n IF stack not large enough for a 4-byte return address\r\n THEN #SS(0); FI;\r\n Push(EIP);\r\n EIP <- tempEIP;\r\n FI;\r\n IF OperandSize = 16\r\n THEN\r\n tempEIP <- DEST AND 0000FFFFH; (* DEST is r/m16 *)\r\n IF tempEIP is not within code segment limit THEN #GP(0); FI;\r\n\r\n\r\n\r\n IF stack not large enough for a 2-byte return address\r\n THEN #SS(0); FI;\r\n Push(IP);\r\n EIP <- tempEIP;\r\n FI;\r\n FI;rel/abs\r\nFI; near\r\n\r\nIF far call and (PE = 0 or (PE = 1 and VM = 1)) (* Real-address or virtual-8086 mode *)\r\n THEN\r\n IF OperandSize = 32\r\n THEN\r\n IF stack not large enough for a 6-byte return address\r\n THEN #SS(0); FI;\r\n IF DEST[31:16] is not zero THEN #GP(0); FI;\r\n Push(CS); (* Padded with 16 high-order bits *)\r\n Push(EIP);\r\n CS <- DEST[47:32]; (* DEST is ptr16:32 or [m16:32] *)\r\n EIP <- DEST[31:0]; (* DEST is ptr16:32 or [m16:32] *)\r\n ELSE (* OperandSize = 16 *)\r\n IF stack not large enough for a 4-byte return address\r\n THEN #SS(0); FI;\r\n Push(CS);\r\n Push(IP);\r\n CS <- DEST[31:16]; (* DEST is ptr16:16 or [m16:16] *)\r\n EIP <- DEST[15:0]; (* DEST is ptr16:16 or [m16:16]; clear upper 16 bits *)\r\n FI;\r\nFI;\r\n\r\nIF far call and (PE = 1 and VM = 0) (* Protected mode or IA-32e Mode, not virtual-8086 mode*)\r\n THEN\r\n IF segment selector in target operand NULL\r\n THEN #GP(0); FI;\r\n IF segment selector index not within descriptor table limits\r\n THEN #GP(new code segment selector); FI;\r\n Read type and access rights of selected segment descriptor;\r\n IF IA32_EFER.LMA = 0\r\n THEN\r\n IF segment type is not a conforming or nonconforming code segment, call\r\n gate, task gate, or TSS\r\n THEN #GP(segment selector); FI;\r\n ELSE\r\n IF segment type is not a conforming or nonconforming code segment or\r\n 64-bit call gate,\r\n THEN #GP(segment selector); FI;\r\n FI;\r\n Depending on type and access rights:\r\n GO TO CONFORMING-CODE-SEGMENT;\r\n GO TO NONCONFORMING-CODE-SEGMENT;\r\n GO TO CALL-GATE;\r\n GO TO TASK-GATE;\r\n GO TO TASK-STATE-SEGMENT;\r\nFI;\r\n\r\n\r\n\r\n\r\nCONFORMING-CODE-SEGMENT:\r\n IF L bit = 1 and D bit = 1 and IA32_EFER.LMA = 1\r\n THEN GP(new code segment selector); FI;\r\n IF DPL > CPL\r\n THEN #GP(new code segment selector); FI;\r\n IF segment not present\r\n THEN #NP(new code segment selector); FI;\r\n IF stack not large enough for return address\r\n THEN #SS(0); FI;\r\n tempEIP <- DEST(Offset);\r\n IF OperandSize = 16\r\n THEN\r\n tempEIP <- tempEIP AND 0000FFFFH; FI; (* Clear upper 16 bits *)\r\n IF (EFER.LMA = 0 or target mode = Compatibility mode) and (tempEIP outside new code\r\n segment limit)\r\n THEN #GP(0); FI;\r\n IF tempEIP is non-canonical\r\n THEN #GP(0); FI;\r\n IF OperandSize = 32\r\n THEN\r\n Push(CS); (* Padded with 16 high-order bits *)\r\n Push(EIP);\r\n CS <- DEST(CodeSegmentSelector);\r\n (* Segment descriptor information also loaded *)\r\n CS(RPL) <- CPL;\r\n EIP <- tempEIP;\r\n ELSE\r\n IF OperandSize = 16\r\n THEN\r\n Push(CS);\r\n Push(IP);\r\n CS <- DEST(CodeSegmentSelector);\r\n (* Segment descriptor information also loaded *)\r\n CS(RPL) <- CPL;\r\n EIP <- tempEIP;\r\n ELSE (* OperandSize = 64 *)\r\n Push(CS); (* Padded with 48 high-order bits *)\r\n Push(RIP);\r\n CS <- DEST(CodeSegmentSelector);\r\n (* Segment descriptor information also loaded *)\r\n CS(RPL) <- CPL;\r\n RIP <- tempEIP;\r\n FI;\r\n FI;\r\nEND;\r\n\r\nNONCONFORMING-CODE-SEGMENT:\r\n IF L-Bit = 1 and D-BIT = 1 and IA32_EFER.LMA = 1\r\n THEN GP(new code segment selector); FI;\r\n IF (RPL > CPL) or (DPL != CPL)\r\n THEN #GP(new code segment selector); FI;\r\n IF segment not present\r\n THEN #NP(new code segment selector); FI;\r\n IF stack not large enough for return address\r\n\r\n\r\n\r\n THEN #SS(0); FI;\r\n tempEIP <- DEST(Offset);\r\n IF OperandSize = 16\r\n THEN tempEIP <- tempEIP AND 0000FFFFH; FI; (* Clear upper 16 bits *)\r\n IF (EFER.LMA = 0 or target mode = Compatibility mode) and (tempEIP outside new code\r\n segment limit)\r\n THEN #GP(0); FI;\r\n IF tempEIP is non-canonical\r\n THEN #GP(0); FI;\r\n IF OperandSize = 32\r\n THEN\r\n Push(CS); (* Padded with 16 high-order bits *)\r\n Push(EIP);\r\n CS <- DEST(CodeSegmentSelector);\r\n (* Segment descriptor information also loaded *)\r\n CS(RPL) <- CPL;\r\n EIP <- tempEIP;\r\n ELSE\r\n IF OperandSize = 16\r\n THEN\r\n Push(CS);\r\n Push(IP);\r\n CS <- DEST(CodeSegmentSelector);\r\n (* Segment descriptor information also loaded *)\r\n CS(RPL) <- CPL;\r\n EIP <- tempEIP;\r\n ELSE (* OperandSize = 64 *)\r\n Push(CS); (* Padded with 48 high-order bits *)\r\n Push(RIP);\r\n CS <- DEST(CodeSegmentSelector);\r\n (* Segment descriptor information also loaded *)\r\n CS(RPL) <- CPL;\r\n RIP <- tempEIP;\r\n FI;\r\n FI;\r\nEND;\r\n\r\nCALL-GATE:\r\n IF call gate (DPL < CPL) or (RPL > DPL)\r\n THEN #GP(call-gate selector); FI;\r\n IF call gate not present\r\n THEN #NP(call-gate selector); FI;\r\n IF call-gate code-segment selector is NULL\r\n THEN #GP(0); FI;\r\n IF call-gate code-segment selector index is outside descriptor table limits\r\n THEN #GP(call-gate code-segment selector); FI;\r\n Read call-gate code-segment descriptor;\r\n IF call-gate code-segment descriptor does not indicate a code segment\r\n or call-gate code-segment descriptor DPL > CPL\r\n THEN #GP(call-gate code-segment selector); FI;\r\n IF IA32_EFER.LMA = 1 AND (call-gate code-segment descriptor is\r\n not a 64-bit code segment or call-gate code-segment descriptor has both L-bit and D-bit set)\r\n THEN #GP(call-gate code-segment selector); FI;\r\n IF call-gate code segment not present\r\n\r\n\r\n\r\n THEN #NP(call-gate code-segment selector); FI;\r\n IF call-gate code segment is non-conforming and DPL < CPL\r\n THEN go to MORE-PRIVILEGE;\r\n ELSE go to SAME-PRIVILEGE;\r\n FI;\r\nEND;\r\n\r\nMORE-PRIVILEGE:\r\n IF current TSS is 32-bit\r\n THEN\r\n TSSstackAddress <- (new code-segment DPL * 8) + 4;\r\n IF (TSSstackAddress + 5) > current TSS limit\r\n THEN #TS(current TSS selector); FI;\r\n NewSS <- 2 bytes loaded from (TSS base + TSSstackAddress + 4);\r\n NewESP <- 4 bytes loaded from (TSS base + TSSstackAddress);\r\n ELSE\r\n IF current TSS is 16-bit\r\n THEN\r\n TSSstackAddress <- (new code-segment DPL * 4) + 2\r\n IF (TSSstackAddress + 3) > current TSS limit\r\n THEN #TS(current TSS selector); FI;\r\n NewSS <- 2 bytes loaded from (TSS base + TSSstackAddress + 2);\r\n NewESP <- 2 bytes loaded from (TSS base + TSSstackAddress);\r\n ELSE (* current TSS is 64-bit *)\r\n TSSstackAddress <- (new code-segment DPL * 8) + 4;\r\n IF (TSSstackAddress + 7) > current TSS limit\r\n THEN #TS(current TSS selector); FI;\r\n NewSS <- new code-segment DPL; (* NULL selector with RPL = new CPL *)\r\n NewRSP <- 8 bytes loaded from (current TSS base + TSSstackAddress);\r\n FI;\r\n FI;\r\n IF IA32_EFER.LMA = 0 and NewSS is NULL\r\n THEN #TS(NewSS); FI;\r\n Read new code-segment descriptor and new stack-segment descriptor;\r\n IF IA32_EFER.LMA = 0 and (NewSS RPL != new code-segment DPL\r\n or new stack-segment DPL != new code-segment DPL or new stack segment is not a\r\n writable data segment)\r\n THEN #TS(NewSS); FI\r\n IF IA32_EFER.LMA = 0 and new stack segment not present\r\n THEN #SS(NewSS); FI;\r\n IF CallGateSize = 32\r\n THEN\r\n IF new stack does not have room for parameters plus 16 bytes\r\n THEN #SS(NewSS); FI;\r\n IF CallGate(InstructionPointer) not within new code-segment limit\r\n THEN #GP(0); FI;\r\n SS <- newSS; (* Segment descriptor information also loaded *)\r\n ESP <- newESP;\r\n CS:EIP <- CallGate(CS:InstructionPointer);\r\n (* Segment descriptor information also loaded *)\r\n Push(oldSS:oldESP); (* From calling procedure *)\r\n temp <- parameter count from call gate, masked to 5 bits;\r\n Push(parameters from calling procedure's stack, temp)\r\n Push(oldCS:oldEIP); (* Return address to calling procedure *)\r\n\r\n\r\n\r\n ELSE\r\n IF CallGateSize = 16\r\n THEN\r\n IF new stack does not have room for parameters plus 8 bytes\r\n THEN #SS(NewSS); FI;\r\n IF (CallGate(InstructionPointer) AND FFFFH) not in new code-segment limit\r\n THEN #GP(0); FI;\r\n SS <- newSS; (* Segment descriptor information also loaded *)\r\n ESP <- newESP;\r\n CS:IP <- CallGate(CS:InstructionPointer);\r\n (* Segment descriptor information also loaded *)\r\n Push(oldSS:oldESP); (* From calling procedure *)\r\n temp <- parameter count from call gate, masked to 5 bits;\r\n Push(parameters from calling procedure's stack, temp)\r\n Push(oldCS:oldEIP); (* Return address to calling procedure *)\r\n ELSE (* CallGateSize = 64 *)\r\n IF pushing 32 bytes on the stack would use a non-canonical address\r\n THEN #SS(NewSS); FI;\r\n IF (CallGate(InstructionPointer) is non-canonical)\r\n THEN #GP(0); FI;\r\n SS <- NewSS; (* NewSS is NULL)\r\n RSP <- NewESP;\r\n CS:IP <- CallGate(CS:InstructionPointer);\r\n (* Segment descriptor information also loaded *)\r\n Push(oldSS:oldESP); (* From calling procedure *)\r\n Push(oldCS:oldEIP); (* Return address to calling procedure *)\r\n FI;\r\n FI;\r\n CPL <- CodeSegment(DPL)\r\n CS(RPL) <- CPL\r\nEND;\r\n\r\nSAME-PRIVILEGE:\r\n IF CallGateSize = 32\r\n THEN\r\n IF stack does not have room for 8 bytes\r\n THEN #SS(0); FI;\r\n IF CallGate(InstructionPointer) not within code segment limit\r\n THEN #GP(0); FI;\r\n CS:EIP <- CallGate(CS:EIP) (* Segment descriptor information also loaded *)\r\n Push(oldCS:oldEIP); (* Return address to calling procedure *)\r\n ELSE\r\n If CallGateSize = 16\r\n THEN\r\n IF stack does not have room for 4 bytes\r\n THEN #SS(0); FI;\r\n IF CallGate(InstructionPointer) not within code segment limit\r\n THEN #GP(0); FI;\r\n CS:IP <- CallGate(CS:instruction pointer);\r\n (* Segment descriptor information also loaded *)\r\n Push(oldCS:oldIP); (* Return address to calling procedure *)\r\n ELSE (* CallGateSize = 64)\r\n IF pushing 16 bytes on the stack touches non-canonical addresses\r\n THEN #SS(0); FI;\r\n\r\n\r\n\r\n IF RIP non-canonical\r\n THEN #GP(0); FI;\r\n CS:IP <- CallGate(CS:instruction pointer);\r\n (* Segment descriptor information also loaded *)\r\n Push(oldCS:oldIP); (* Return address to calling procedure *)\r\n FI;\r\n FI;\r\n CS(RPL) <- CPL\r\nEND;\r\n\r\nTASK-GATE:\r\n IF task gate DPL < CPL or RPL\r\n THEN #GP(task gate selector); FI;\r\n IF task gate not present\r\n THEN #NP(task gate selector); FI;\r\n Read the TSS segment selector in the task-gate descriptor;\r\n IF TSS segment selector local/global bit is set to local\r\n or index not within GDT limits\r\n THEN #GP(TSS selector); FI;\r\n Access TSS descriptor in GDT;\r\n IF TSS descriptor specifies that the TSS is busy (low-order 5 bits set to 00001)\r\n THEN #GP(TSS selector); FI;\r\n IF TSS not present\r\n THEN #NP(TSS selector); FI;\r\n SWITCH-TASKS (with nesting) to TSS;\r\n IF EIP not within code segment limit\r\n THEN #GP(0); FI;\r\nEND;\r\n\r\nTASK-STATE-SEGMENT:\r\n IF TSS DPL < CPL or RPL\r\n or TSS descriptor indicates TSS not available\r\n THEN #GP(TSS selector); FI;\r\n IF TSS is not present\r\n THEN #NP(TSS selector); FI;\r\n SWITCH-TASKS (with nesting) to TSS;\r\n IF EIP not within code segment limit\r\n THEN #GP(0); FI;\r\nEND;\r\n\r\n\r\nFlags Affected\r\nAll flags are affected if a task switch occurs; no flags are affected if a task switch does not occur.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the target offset in destination operand is beyond the new code segment limit.\r\n If the segment selector in the destination operand is NULL.\r\n If the code segment selector in the gate is NULL.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n#GP(selector) If a code segment or gate or TSS selector index is outside descriptor table limits.\r\n If the segment descriptor pointed to by the segment selector in the destination operand is not\r\n for a conforming-code segment, nonconforming-code segment, call gate, task gate, or task\r\n state segment.\r\n If the DPL for a nonconforming-code segment is not equal to the CPL or the RPL for the\r\n segment's segment selector is greater than the CPL.\r\n If the DPL for a conforming-code segment is greater than the CPL.\r\n If the DPL from a call-gate, task-gate, or TSS segment descriptor is less than the CPL or than\r\n the RPL of the call-gate, task-gate, or TSS's segment selector.\r\n If the segment descriptor for a segment selector from a call gate does not indicate it is a code\r\n segment.\r\n If the segment selector from a call gate is beyond the descriptor table limits.\r\n If the DPL for a code-segment obtained from a call gate is greater than the CPL.\r\n If the segment selector for a TSS has its local/global bit set for local.\r\n If a TSS segment descriptor specifies that the TSS is busy or not available.\r\n#SS(0) If pushing the return address, parameters, or stack segment pointer onto the stack exceeds\r\n the bounds of the stack segment, when no stack switch occurs.\r\n If a memory operand effective address is outside the SS segment limit.\r\n#SS(selector) If pushing the return address, parameters, or stack segment pointer onto the stack exceeds\r\n the bounds of the stack segment, when a stack switch occurs.\r\n If the SS register is being loaded as part of a stack switch and the segment pointed to is\r\n marked not present.\r\n If stack segment does not have room for the return address, parameters, or stack segment\r\n pointer, when stack switch occurs.\r\n#NP(selector) If a code segment, data segment, stack segment, call gate, task gate, or TSS is not present.\r\n#TS(selector) If the new stack segment selector and ESP are beyond the end of the TSS.\r\n If the new stack segment selector is NULL.\r\n If the RPL of the new stack segment selector in the TSS is not equal to the DPL of the code\r\n segment being accessed.\r\n If DPL of the stack segment descriptor for the new stack segment is not equal to the DPL of the\r\n code segment descriptor.\r\n If the new stack segment is not a writable data segment.\r\n If segment-selector index for stack segment is outside descriptor table limits.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the target offset is beyond the code segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the target offset is beyond the code segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n#GP(selector) If a memory address accessed by the selector is in non-canonical space.\r\n#GP(0) If the target offset in the destination operand is non-canonical.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If a memory address is non-canonical.\r\n If target offset in destination operand is non-canonical.\r\n If the segment selector in the destination operand is NULL.\r\n If the code segment selector in the 64-bit gate is NULL.\r\n#GP(selector) If code segment or 64-bit call gate is outside descriptor table limits.\r\n If code segment or 64-bit call gate overlaps non-canonical space.\r\n If the segment descriptor pointed to by the segment selector in the destination operand is not\r\n for a conforming-code segment, nonconforming-code segment, or 64-bit call gate.\r\n If the segment descriptor pointed to by the segment selector in the destination operand is a\r\n code segment and has both the D-bit and the L- bit set.\r\n If the DPL for a nonconforming-code segment is not equal to the CPL, or the RPL for the\r\n segment's segment selector is greater than the CPL.\r\n If the DPL for a conforming-code segment is greater than the CPL.\r\n If the DPL from a 64-bit call-gate is less than the CPL or than the RPL of the 64-bit call-gate.\r\n If the upper type field of a 64-bit call gate is not 0x0.\r\n If the segment selector from a 64-bit call gate is beyond the descriptor table limits.\r\n If the DPL for a code-segment obtained from a 64-bit call gate is greater than the CPL.\r\n If the code segment descriptor pointed to by the selector in the 64-bit gate doesn't have the L-\r\n bit set and the D-bit clear.\r\n If the segment descriptor for a segment selector from the 64-bit call gate does not indicate it\r\n is a code segment.\r\n#SS(0) If pushing the return offset or CS selector onto the stack exceeds the bounds of the stack\r\n segment when no stack switch occurs.\r\n If a memory operand effective address is outside the SS segment limit.\r\n If the stack address is in a non-canonical form.\r\n#SS(selector) If pushing the old values of SS selector, stack pointer, EFLAGS, CS selector, offset, or error\r\n code onto the stack violates the canonical boundary when a stack switch occurs.\r\n#NP(selector) If a code segment or 64-bit call gate is not present.\r\n#TS(selector) If the load of the new RSP exceeds the limit of the TSS.\r\n#UD (64-bit mode only) If a far call is direct to an absolute address in memory.\r\n If the LOCK prefix is used.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CALL"
},
{
"description": "CBW/CWDE/CDQE-Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to Quadword\r\nOpcode Instruction Op/ 64-bit Compat/ Description\r\n En Mode Leg Mode\r\n98 CBW NP Valid Valid AX <- sign-extend of AL.\r\n98 CWDE NP Valid Valid EAX <- sign-extend of AX.\r\nREX.W + 98 CDQE NP Valid N.E. RAX <- sign-extend of EAX.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nDouble the size of the source operand by means of sign extension. The CBW (convert byte to word) instruction\r\ncopies the sign (bit 7) in the source operand into every bit in the AH register. The CWDE (convert word to double-\r\nword) instruction copies the sign (bit 15) of the word in the AX register into the high 16 bits of the EAX register.\r\nCBW and CWDE reference the same opcode. The CBW instruction is intended for use when the operand-size attri-\r\nbute is 16; CWDE is intended for use when the operand-size attribute is 32. Some assemblers may force the\r\noperand size. Others may treat these two mnemonics as synonyms (CBW/CWDE) and use the setting of the\r\noperand-size attribute to determine the size of values to be converted.\r\nIn 64-bit mode, the default operation size is the size of the destination register. Use of the REX.W prefix promotes\r\nthis instruction (CDQE when promoted) to operate on 64-bit operands. In which case, CDQE copies the sign (bit\r\n31) of the doubleword in the EAX register into the high 32 bits of RAX.\r\n\r\nOperation\r\nIF OperandSize = 16 (* Instruction = CBW *)\r\n THEN\r\n AX <- SignExtend(AL);\r\n ELSE IF (OperandSize = 32, Instruction = CWDE)\r\n EAX <- SignExtend(AX); FI;\r\n ELSE (* 64-Bit Mode, OperandSize = 64, Instruction = CDQE*)\r\n RAX <- SignExtend(EAX);\r\nFI;\r\n\r\nFlags Affected\r\nNone.\r\n\r\nExceptions (All Operating Modes)\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CBW"
},
{
"description": "-R:CWD",
"mnem": "CDQ"
},
{
"description": "-R:CBW",
"mnem": "CDQE"
},
{
"description": "CLAC-Clear AC Flag in EFLAGS Register\r\nOpcode/ Op / 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F 01 CA NP V/V SMAP Clear the AC flag in the EFLAGS register.\r\nCLAC\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nClears the AC flag bit in EFLAGS register. This disables any alignment checking of user-mode data accesses. If the\r\nSMAP bit is set in the CR4 register, this disallows explicit supervisor-mode data accesses to user-mode pages.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode. Attempts to execute CLAC when\r\nCPL > 0 cause #UD.\r\n\r\nOperation\r\nEFLAGS.AC <- 0;\r\n\r\nFlags Affected\r\nAC cleared. Other flags are unaffected.\r\n\r\nProtected Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If the CPL > 0.\r\n If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.\r\n\r\nReal-Address Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD The CLAC instruction is not recognized in virtual-8086 mode.\r\n\r\nCompatibility Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If the CPL > 0.\r\n If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.\r\n\r\n64-Bit Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If the CPL > 0.\r\n If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CLAC"
},
{
"description": "CLC-Clear Carry Flag\r\n Opcode Instruction Op/ 64-bit Compat/ Description\r\n En Mode Leg Mode\r\n F8 CLC NP Valid Valid Clear CF flag.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nClears the CF flag in the EFLAGS register. Operation is the same in all modes.\r\n\r\nOperation\r\nCF <- 0;\r\n\r\nFlags Affected\r\nThe CF flag is set to 0. The OF, ZF, SF, AF, and PF flags are unaffected.\r\n\r\nExceptions (All Operating Modes)\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CLC"
},
{
"description": "CLD-Clear Direction Flag\r\nOpcode Instruction Op/ 64-bit Compat/ Description\r\n En Mode Leg Mode\r\nFC CLD NP Valid Valid Clear DF flag.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nClears the DF flag in the EFLAGS register. When the DF flag is set to 0, string operations increment the index regis-\r\nters (ESI and/or EDI). Operation is the same in all modes.\r\n\r\nOperation\r\nDF <- 0;\r\n\r\nFlags Affected\r\nThe DF flag is set to 0. The CF, OF, ZF, SF, AF, and PF flags are unaffected.\r\n\r\nExceptions (All Operating Modes)\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CLD"
},
{
"description": "CLFLUSH-Flush Cache Line\r\n Opcode Instruction Op/ 64-bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F AE /7 CLFLUSH m8 M Valid Valid Flushes cache line containing m8.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (w) NA NA NA\r\n\r\nDescription\r\nInvalidates from every level of the cache hierarchy in the cache coherence domain the cache line that contains the\r\nlinear address specified with the memory operand. If that cache line contains modified data at any level of the\r\ncache hierarchy, that data is written back to memory. The source operand is a byte memory location.\r\nThe availability of CLFLUSH is indicated by the presence of the CPUID feature flag CLFSH\r\n(CPUID.01H:EDX[bit 19]). The aligned cache line size affected is also indicated with the CPUID instruction (bits 8\r\nthrough 15 of the EBX register when the initial value in the EAX register is 1).\r\nThe memory attribute of the page containing the affected line has no effect on the behavior of this instruction. It\r\nshould be noted that processors are free to speculatively fetch and cache data from system memory regions\r\nassigned a memory-type allowing for speculative reads (such as, the WB, WC, and WT memory types). PREFETCHh\r\ninstructions can be used to provide the processor with hints for this speculative behavior. Because this speculative\r\nfetching can occur at any time and is not tied to instruction execution, the CLFLUSH instruction is not ordered with\r\nrespect to PREFETCHh instructions or any of the speculative fetching mechanisms (that is, data can be specula-\r\ntively loaded into a cache line just before, during, or after the execution of a CLFLUSH instruction that references\r\nthe cache line).\r\nExecutions of the CLFLUSH instruction are ordered with respect to each other and with respect to writes, locked\r\nread-modify-write instructions, fence instructions, and executions of CLFLUSHOPT to the same cache line.1 They\r\nare not ordered with respect to executions of CLFLUSHOPT to different cache lines.\r\nThe CLFLUSH instruction can be used at all privilege levels and is subject to all permission checking and faults asso-\r\nciated with a byte load (and in addition, a CLFLUSH instruction is allowed to flush a linear address in an execute-\r\nonly segment). Like a load, the CLFLUSH instruction sets the A bit but not the D bit in the page tables.\r\nIn some implementations, the CLFLUSH instruction may always cause transactional abort with Transactional\r\nSynchronization Extensions (TSX). The CLFLUSH instruction is not expected to be commonly used inside typical\r\ntransactional regions. However, programmers must not rely on CLFLUSH instruction to force a transactional abort,\r\nsince whether they cause transactional abort is implementation dependent.\r\nThe CLFLUSH instruction was introduced with the SSE2 extensions; however, because it has its own CPUID feature\r\nflag, it can be implemented in IA-32 processors that do not include the SSE2 extensions. Also, detecting the pres-\r\nence of the SSE2 extensions with the CPUID instruction does not guarantee that the CLFLUSH instruction is imple-\r\nmented in the processor.\r\nCLFLUSH operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nFlush_Cache_Line(SRC);\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nCLFLUSH: void _mm_clflush(void const *p)\r\n\r\n\r\n\r\n\r\n1. Earlier versions of this manual specified that executions of the CLFLUSH instruction were ordered only by the MFENCE instruction.\r\n All processors implementing the CLFLUSH instruction also order it relative to the other operations enumerated above.\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.\r\n#SS(0) For an illegal address in the SS segment.\r\n#PF(fault-code) For a page fault.\r\n#UD If CPUID.01H:EDX.CLFSH[bit 19] = 0.\r\n If the LOCK prefix is used.\r\n If an instruction prefix F2H or F3H is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If any part of the operand lies outside the effective address space from 0 to FFFFH.\r\n#UD If CPUID.01H:EDX.CLFSH[bit 19] = 0.\r\n If the LOCK prefix is used.\r\n If an instruction prefix F2H or F3H is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in real address mode.\r\n#PF(fault-code) For a page fault.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) For a page fault.\r\n#UD If CPUID.01H:EDX.CLFSH[bit 19] = 0.\r\n If the LOCK prefix is used.\r\n If an instruction prefix F2H or F3H is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CLFLUSH"
},
{
"description": "CLFLUSHOPT-Flush Cache Line Optimized\r\n Opcode Instruction Op/ 64-bit Compat/ Description\r\n En Mode Leg Mode\r\n 66 0F AE /7 CLFLUSHOPT m8 M Valid Valid Flushes cache line containing m8.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (w) NA NA NA\r\n\r\nDescription\r\nInvalidates from every level of the cache hierarchy in the cache coherence domain the cache line that contains the\r\nlinear address specified with the memory operand. If that cache line contains modified data at any level of the\r\ncache hierarchy, that data is written back to memory. The source operand is a byte memory location.\r\nThe availability of CLFLUSHOPT is indicated by the presence of the CPUID feature flag CLFLUSHOPT\r\n(CPUID.(EAX=7,ECX=0):EBX[bit 23]). The aligned cache line size affected is also indicated with the CPUID instruc-\r\ntion (bits 8 through 15 of the EBX register when the initial value in the EAX register is 1).\r\nThe memory attribute of the page containing the affected line has no effect on the behavior of this instruction. It\r\nshould be noted that processors are free to speculatively fetch and cache data from system memory regions\r\nassigned a memory-type allowing for speculative reads (such as, the WB, WC, and WT memory types). PREFETCHh\r\ninstructions can be used to provide the processor with hints for this speculative behavior. Because this speculative\r\nfetching can occur at any time and is not tied to instruction execution, the CLFLUSH instruction is not ordered with\r\nrespect to PREFETCHh instructions or any of the speculative fetching mechanisms (that is, data can be specula-\r\ntively loaded into a cache line just before, during, or after the execution of a CLFLUSH instruction that references\r\nthe cache line).\r\nExecutions of the CLFLUSHOPT instruction are ordered with respect to fence instructions and to locked read-\r\nmodify-write instructions; they are also ordered with respect to the following accesses to the cache line being\r\ninvalidated: writes, executions of CLFLUSH, and executions of CLFLUSHOPT. They are not ordered with respect to\r\nwrites, executions of CLFLUSH, or executions of CLFLUSHOPT that access other cache lines; to enforce ordering\r\nwith such an operation, software can insert an SFENCE instruction between CFLUSHOPT and that operation.\r\nThe CLFLUSHOPT instruction can be used at all privilege levels and is subject to all permission checking and faults\r\nassociated with a byte load (and in addition, a CLFLUSHOPT instruction is allowed to flush a linear address in an\r\nexecute-only segment). Like a load, the CLFLUSHOPT instruction sets the A bit but not the D bit in the page tables.\r\nIn some implementations, the CLFLUSHOPT instruction may always cause transactional abort with Transactional\r\nSynchronization Extensions (TSX). The CLFLUSHOPT instruction is not expected to be commonly used inside\r\ntypical transactional regions. However, programmers must not rely on CLFLUSHOPT instruction to force a transac-\r\ntional abort, since whether they cause transactional abort is implementation dependent.\r\nCLFLUSHOPT operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nFlush_Cache_Line_Optimized(SRC);\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nCLFLUSHOPT:void _mm_clflushopt(void const *p)\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.\r\n#SS(0) For an illegal address in the SS segment.\r\n#PF(fault-code) For a page fault.\r\n#UD If CPUID.(EAX=7,ECX=0):EBX.CLFLUSHOPT[bit 23] = 0.\r\n If the LOCK prefix is used.\r\n If an instruction prefix F2H or F3H is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If any part of the operand lies outside the effective address space from 0 to FFFFH.\r\n#UD If CPUID.(EAX=7,ECX=0):EBX.CLFLUSHOPT[bit 23] = 0.\r\n If the LOCK prefix is used.\r\n If an instruction prefix F2H or F3H is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in real address mode.\r\n#PF(fault-code) For a page fault.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) For a page fault.\r\n#UD If CPUID.(EAX=7,ECX=0):EBX.CLFLUSHOPT[bit 23] = 0.\r\n If the LOCK prefix is used.\r\n If an instruction prefix F2H or F3H is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CLFLUSHOPT"
},
{
"description": "CLI - Clear Interrupt Flag\r\n Opcode Instruction Op/ 64-bit Compat/ Description\r\n En Mode Leg Mode\r\n FA CLI NP Valid Valid Clear interrupt flag; interrupts disabled when\r\n interrupt flag cleared.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nIf protected-mode virtual interrupts are not enabled, CLI clears the IF flag in the EFLAGS register. No other flags\r\nare affected. Clearing the IF flag causes the processor to ignore maskable external interrupts. The IF flag and the\r\nCLI and STI instruction have no affect on the generation of exceptions and NMI interrupts.\r\nWhen protected-mode virtual interrupts are enabled, CPL is 3, and IOPL is less than 3; CLI clears the VIF flag in the\r\nEFLAGS register, leaving IF unaffected. Table 3-7 indicates the action of the CLI instruction depending on the\r\nprocessor operating mode and the CPL/IOPL of the running program or procedure.\r\nOperation is the same in all modes.\r\n\r\n\r\n Table 3-7. Decision Table for CLI Results\r\n PE VM IOPL CPL PVI VIP VME CLI Result\r\n 0 X X X X X X IF = 0\r\n 1 0 >= CPL X X X X IF = 0\r\n 1 0 < CPL 3 1 X X VIF = 0\r\n 1 0 < CPL <3 X X X GP Fault\r\n 1 0 < CPL X 0 X X GP Fault\r\n 1 1 3 X X X X IF = 0\r\n 1 1 <3 X X X 1 VIF = 0\r\n 1 1 <3 X X X 0 GP Fault\r\n NOTES:\r\n * X = This setting has no impact.\r\n\r\nOperation\r\nIF PE = 0\r\n THEN\r\n IF <- 0; (* Reset Interrupt Flag *)\r\n ELSE\r\n IF VM = 0;\r\n THEN\r\n IF IOPL >= CPL\r\n THEN\r\n IF <- 0; (* Reset Interrupt Flag *)\r\n ELSE\r\n IF ((IOPL < CPL) and (CPL = 3) and (PVI = 1))\r\n THEN\r\n VIF <- 0; (* Reset Virtual Interrupt Flag *)\r\n ELSE\r\n #GP(0);\r\n\r\n\r\n FI;\r\n FI;\r\n ELSE (* VM = 1 *)\r\n IF IOPL = 3\r\n THEN\r\n IF <- 0; (* Reset Interrupt Flag *)\r\n ELSE\r\n IF (IOPL < 3) AND (VME = 1)\r\n THEN\r\n VIF <- 0; (* Reset Virtual Interrupt Flag *)\r\n ELSE\r\n #GP(0);\r\n FI;\r\n FI;\r\n FI;\r\nFI;\r\n\r\nFlags Affected\r\nIf protected-mode virtual interrupts are not enabled, IF is set to 0 if the CPL is equal to or less than the IOPL; other-\r\nwise, it is not affected. Other flags are unaffected.\r\nWhen protected-mode virtual interrupts are enabled, CPL is 3, and IOPL is less than 3; CLI clears the VIF flag in the\r\nEFLAGS register, leaving IF unaffected. Other flags are unaffected.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the CPL is greater (has less privilege) than the IOPL of the current program or procedure.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If the CPL is greater (has less privilege) than the IOPL of the current program or procedure.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the CPL is greater (has less privilege) than the IOPL of the current program or procedure.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CLI"
},
{
"description": "CLTS-Clear Task-Switched Flag in CR0\r\n Opcode Instruction Op/ 64-bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F 06 CLTS NP Valid Valid Clears TS flag in CR0.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nClears the task-switched (TS) flag in the CR0 register. This instruction is intended for use in operating-system\r\nprocedures. It is a privileged instruction that can only be executed at a CPL of 0. It is allowed to be executed in real-\r\naddress mode to allow initialization for protected mode.\r\nThe processor sets the TS flag every time a task switch occurs. The flag is used to synchronize the saving of FPU\r\ncontext in multitasking applications. See the description of the TS flag in the section titled \"Control Registers\" in\r\nChapter 2 of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, for more information\r\nabout this flag.\r\nCLTS operation is the same in non-64-bit modes and 64-bit mode.\r\nSee Chapter 25, \"VMX Non-Root Operation,\" of the Intel 64 and IA-32 Architectures Software Developer's\r\nManual, Volume 3C, for more information about the behavior of this instruction in VMX non-root operation.\r\n\r\nOperation\r\nCR0.TS[bit 3] <- 0;\r\n\r\nFlags Affected\r\nThe TS flag in CR0 register is cleared.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the current privilege level is not 0.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) CLTS is not recognized in virtual-8086 mode.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the CPL is greater than 0.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CLTS"
},
{
"description": "CLWB-Cache Line Write Back\r\n Opcode/ Op/ 64/32 bit CPUID Description\r\n Instruction En Mode Feature Flag\r\n Support\r\n 66 0F AE /6 M V/V CLWB Writes back modified cache line containing m8, and may\r\n CLWB m8 retain the line in cache hierarchy in non-modified state.\r\n\r\n\r\n Instruction Operand Encoding1\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (w) NA NA NA\r\n\r\nDescription\r\nWrites back to memory the cache line (if modified) that contains the linear address specified with the memory\r\noperand from any level of the cache hierarchy in the cache coherence domain. The line may be retained in the\r\ncache hierarchy in non-modified state. Retaining the line in the cache hierarchy is a performance optimization\r\n(treated as a hint by hardware) to reduce the possibility of cache miss on a subsequent access. Hardware may\r\nchoose to retain the line at any of the levels in the cache hierarchy, and in some cases, may invalidate the line from\r\nthe cache hierarchy. The source operand is a byte memory location.\r\nThe availability of CLWB instruction is indicated by the presence of the CPUID feature flag CLWB (bit 24 of the EBX\r\nregister, see \"CPUID - CPU Identification\" in this chapter). The aligned cache line size affected is also indicated\r\nwith the CPUID instruction (bits 8 through 15 of the EBX register when the initial value in the EAX register is 1).\r\nThe memory attribute of the page containing the affected line has no effect on the behavior of this instruction. It\r\nshould be noted that processors are free to speculatively fetch and cache data from system memory regions that\r\nare assigned a memory-type allowing for speculative reads (such as, the WB, WC, and WT memory types).\r\nPREFETCHh instructions can be used to provide the processor with hints for this speculative behavior. Because this\r\nspeculative fetching can occur at any time and is not tied to instruction execution, the CLWB instruction is not\r\nordered with respect to PREFETCHh instructions or any of the speculative fetching mechanisms (that is, data can\r\nbe speculatively loaded into a cache line just before, during, or after the execution of a CLWB instruction that refer-\r\nences the cache line).\r\nCLWB instruction is ordered only by store-fencing operations. For example, software can use an SFENCE, MFENCE,\r\nXCHG, or LOCK-prefixed instructions to ensure that previous stores are included in the write-back. CLWB instruc-\r\ntion need not be ordered by another CLWB or CLFLUSHOPT instruction. CLWB is implicitly ordered with older stores\r\nexecuted by the logical processor to the same address.\r\nFor usages that require only writing back modified data from cache lines to memory (do not require the line to be\r\ninvalidated), and expect to subsequently access the data, software is recommended to use CLWB (with appropriate\r\nfencing) instead of CLFLUSH or CLFLUSHOPT for improved performance.\r\nThe CLWB instruction can be used at all privilege levels and is subject to all permission checking and faults associ-\r\nated with a byte load. Like a load, the CLWB instruction sets the accessed flag but not the dirty flag in the page\r\ntables.\r\nIn some implementations, the CLWB instruction may always cause transactional abort with Transactional Synchro-\r\nnization Extensions (TSX). CLWB instruction is not expected to be commonly used inside typical transactional\r\nregions. However, programmers must not rely on CLWB instruction to force a transactional abort, since whether\r\nthey cause transactional abort is implementation dependent.\r\n\r\nOperation\r\nCache_Line_Write_Back(m8);\r\n\r\nFlags Affected\r\nNone.\r\n\r\n\r\n1. ModRM.MOD != 011B\r\n\r\n\r\n\r\nC/C++ Compiler Intrinsic Equivalent\r\nCLWB void _mm_clwb(void const *p);\r\n\r\nProtected Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If CPUID.(EAX=07H, ECX=0H):EBX.CLWB[bit 24] = 0.\r\n#GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.\r\n#SS(0) For an illegal address in the SS segment.\r\n#PF(fault-code) For a page fault.\r\n\r\nReal-Address Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If CPUID.(EAX=07H, ECX=0H):EBX.CLWB[bit 24] = 0.\r\n#GP If any part of the operand lies outside the effective address space from 0 to FFFFH.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in real address mode.\r\n#PF(fault-code) For a page fault.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If CPUID.(EAX=07H, ECX=0H):EBX.CLWB[bit 24] = 0.\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) For a page fault.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CLWB"
},
{
"description": "CMC-Complement Carry Flag\r\nOpcode Instruction Op/ 64-bit Compat/ Description\r\n En Mode Leg Mode\r\nF5 CMC NP Valid Valid Complement CF flag.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nComplements the CF flag in the EFLAGS register. CMC operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nEFLAGS.CF[bit 0]<- NOT EFLAGS.CF[bit 0];\r\n\r\nFlags Affected\r\nThe CF flag contains the complement of its original value. The OF, ZF, SF, AF, and PF flags are unaffected.\r\n\r\nExceptions (All Operating Modes)\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CMC"
},
{
"description": "CMOVcc-Conditional Move\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F 47 /r CMOVA r16, r/m16 RM Valid Valid Move if above (CF=0 and ZF=0).\r\n 0F 47 /r CMOVA r32, r/m32 RM Valid Valid Move if above (CF=0 and ZF=0).\r\n REX.W + 0F 47 /r CMOVA r64, r/m64 RM Valid N.E. Move if above (CF=0 and ZF=0).\r\n 0F 43 /r CMOVAE r16, r/m16 RM Valid Valid Move if above or equal (CF=0).\r\n 0F 43 /r CMOVAE r32, r/m32 RM Valid Valid Move if above or equal (CF=0).\r\n REX.W + 0F 43 /r CMOVAE r64, r/m64 RM Valid N.E. Move if above or equal (CF=0).\r\n 0F 42 /r CMOVB r16, r/m16 RM Valid Valid Move if below (CF=1).\r\n 0F 42 /r CMOVB r32, r/m32 RM Valid Valid Move if below (CF=1).\r\n REX.W + 0F 42 /r CMOVB r64, r/m64 RM Valid N.E. Move if below (CF=1).\r\n 0F 46 /r CMOVBE r16, r/m16 RM Valid Valid Move if below or equal (CF=1 or ZF=1).\r\n 0F 46 /r CMOVBE r32, r/m32 RM Valid Valid Move if below or equal (CF=1 or ZF=1).\r\n REX.W + 0F 46 /r CMOVBE r64, r/m64 RM Valid N.E. Move if below or equal (CF=1 or ZF=1).\r\n 0F 42 /r CMOVC r16, r/m16 RM Valid Valid Move if carry (CF=1).\r\n 0F 42 /r CMOVC r32, r/m32 RM Valid Valid Move if carry (CF=1).\r\n REX.W + 0F 42 /r CMOVC r64, r/m64 RM Valid N.E. Move if carry (CF=1).\r\n 0F 44 /r CMOVE r16, r/m16 RM Valid Valid Move if equal (ZF=1).\r\n 0F 44 /r CMOVE r32, r/m32 RM Valid Valid Move if equal (ZF=1).\r\n REX.W + 0F 44 /r CMOVE r64, r/m64 RM Valid N.E. Move if equal (ZF=1).\r\n 0F 4F /r CMOVG r16, r/m16 RM Valid Valid Move if greater (ZF=0 and SF=OF).\r\n 0F 4F /r CMOVG r32, r/m32 RM Valid Valid Move if greater (ZF=0 and SF=OF).\r\n REX.W + 0F 4F /r CMOVG r64, r/m64 RM V/N.E. NA Move if greater (ZF=0 and SF=OF).\r\n 0F 4D /r CMOVGE r16, r/m16 RM Valid Valid Move if greater or equal (SF=OF).\r\n 0F 4D /r CMOVGE r32, r/m32 RM Valid Valid Move if greater or equal (SF=OF).\r\n REX.W + 0F 4D /r CMOVGE r64, r/m64 RM Valid N.E. Move if greater or equal (SF=OF).\r\n 0F 4C /r CMOVL r16, r/m16 RM Valid Valid Move if less (SF!= OF).\r\n 0F 4C /r CMOVL r32, r/m32 RM Valid Valid Move if less (SF!= OF).\r\n REX.W + 0F 4C /r CMOVL r64, r/m64 RM Valid N.E. Move if less (SF!= OF).\r\n 0F 4E /r CMOVLE r16, r/m16 RM Valid Valid Move if less or equal (ZF=1 or SF!= OF).\r\n 0F 4E /r CMOVLE r32, r/m32 RM Valid Valid Move if less or equal (ZF=1 or SF!= OF).\r\n REX.W + 0F 4E /r CMOVLE r64, r/m64 RM Valid N.E. Move if less or equal (ZF=1 or SF!= OF).\r\n 0F 46 /r CMOVNA r16, r/m16 RM Valid Valid Move if not above (CF=1 or ZF=1).\r\n 0F 46 /r CMOVNA r32, r/m32 RM Valid Valid Move if not above (CF=1 or ZF=1).\r\n REX.W + 0F 46 /r CMOVNA r64, r/m64 RM Valid N.E. Move if not above (CF=1 or ZF=1).\r\n 0F 42 /r CMOVNAE r16, r/m16 RM Valid Valid Move if not above or equal (CF=1).\r\n 0F 42 /r CMOVNAE r32, r/m32 RM Valid Valid Move if not above or equal (CF=1).\r\n REX.W + 0F 42 /r CMOVNAE r64, r/m64 RM Valid N.E. Move if not above or equal (CF=1).\r\n 0F 43 /r CMOVNB r16, r/m16 RM Valid Valid Move if not below (CF=0).\r\n 0F 43 /r CMOVNB r32, r/m32 RM Valid Valid Move if not below (CF=0).\r\n REX.W + 0F 43 /r CMOVNB r64, r/m64 RM Valid N.E. Move if not below (CF=0).\r\n 0F 47 /r CMOVNBE r16, r/m16 RM Valid Valid Move if not below or equal (CF=0 and ZF=0).\r\n\r\n\r\n\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F 47 /r CMOVNBE r32, r/m32 RM Valid Valid Move if not below or equal (CF=0 and ZF=0).\r\n REX.W + 0F 47 /r CMOVNBE r64, r/m64 RM Valid N.E. Move if not below or equal (CF=0 and ZF=0).\r\n 0F 43 /r CMOVNC r16, r/m16 RM Valid Valid Move if not carry (CF=0).\r\n 0F 43 /r CMOVNC r32, r/m32 RM Valid Valid Move if not carry (CF=0).\r\n REX.W + 0F 43 /r CMOVNC r64, r/m64 RM Valid N.E. Move if not carry (CF=0).\r\n 0F 45 /r CMOVNE r16, r/m16 RM Valid Valid Move if not equal (ZF=0).\r\n 0F 45 /r CMOVNE r32, r/m32 RM Valid Valid Move if not equal (ZF=0).\r\n REX.W + 0F 45 /r CMOVNE r64, r/m64 RM Valid N.E. Move if not equal (ZF=0).\r\n 0F 4E /r CMOVNG r16, r/m16 RM Valid Valid Move if not greater (ZF=1 or SF!= OF).\r\n 0F 4E /r CMOVNG r32, r/m32 RM Valid Valid Move if not greater (ZF=1 or SF!= OF).\r\n REX.W + 0F 4E /r CMOVNG r64, r/m64 RM Valid N.E. Move if not greater (ZF=1 or SF!= OF).\r\n 0F 4C /r CMOVNGE r16, r/m16 RM Valid Valid Move if not greater or equal (SF!= OF).\r\n 0F 4C /r CMOVNGE r32, r/m32 RM Valid Valid Move if not greater or equal (SF!= OF).\r\n REX.W + 0F 4C /r CMOVNGE r64, r/m64 RM Valid N.E. Move if not greater or equal (SF!= OF).\r\n 0F 4D /r CMOVNL r16, r/m16 RM Valid Valid Move if not less (SF=OF).\r\n 0F 4D /r CMOVNL r32, r/m32 RM Valid Valid Move if not less (SF=OF).\r\n REX.W + 0F 4D /r CMOVNL r64, r/m64 RM Valid N.E. Move if not less (SF=OF).\r\n 0F 4F /r CMOVNLE r16, r/m16 RM Valid Valid Move if not less or equal (ZF=0 and SF=OF).\r\n 0F 4F /r CMOVNLE r32, r/m32 RM Valid Valid Move if not less or equal (ZF=0 and SF=OF).\r\n REX.W + 0F 4F /r CMOVNLE r64, r/m64 RM Valid N.E. Move if not less or equal (ZF=0 and SF=OF).\r\n 0F 41 /r CMOVNO r16, r/m16 RM Valid Valid Move if not overflow (OF=0).\r\n 0F 41 /r CMOVNO r32, r/m32 RM Valid Valid Move if not overflow (OF=0).\r\n REX.W + 0F 41 /r CMOVNO r64, r/m64 RM Valid N.E. Move if not overflow (OF=0).\r\n 0F 4B /r CMOVNP r16, r/m16 RM Valid Valid Move if not parity (PF=0).\r\n 0F 4B /r CMOVNP r32, r/m32 RM Valid Valid Move if not parity (PF=0).\r\n REX.W + 0F 4B /r CMOVNP r64, r/m64 RM Valid N.E. Move if not parity (PF=0).\r\n 0F 49 /r CMOVNS r16, r/m16 RM Valid Valid Move if not sign (SF=0).\r\n 0F 49 /r CMOVNS r32, r/m32 RM Valid Valid Move if not sign (SF=0).\r\n REX.W + 0F 49 /r CMOVNS r64, r/m64 RM Valid N.E. Move if not sign (SF=0).\r\n 0F 45 /r CMOVNZ r16, r/m16 RM Valid Valid Move if not zero (ZF=0).\r\n 0F 45 /r CMOVNZ r32, r/m32 RM Valid Valid Move if not zero (ZF=0).\r\n REX.W + 0F 45 /r CMOVNZ r64, r/m64 RM Valid N.E. Move if not zero (ZF=0).\r\n 0F 40 /r CMOVO r16, r/m16 RM Valid Valid Move if overflow (OF=1).\r\n 0F 40 /r CMOVO r32, r/m32 RM Valid Valid Move if overflow (OF=1).\r\n REX.W + 0F 40 /r CMOVO r64, r/m64 RM Valid N.E. Move if overflow (OF=1).\r\n 0F 4A /r CMOVP r16, r/m16 RM Valid Valid Move if parity (PF=1).\r\n 0F 4A /r CMOVP r32, r/m32 RM Valid Valid Move if parity (PF=1).\r\n REX.W + 0F 4A /r CMOVP r64, r/m64 RM Valid N.E. Move if parity (PF=1).\r\n 0F 4A /r CMOVPE r16, r/m16 RM Valid Valid Move if parity even (PF=1).\r\n 0F 4A /r CMOVPE r32, r/m32 RM Valid Valid Move if parity even (PF=1).\r\n REX.W + 0F 4A /r CMOVPE r64, r/m64 RM Valid N.E. Move if parity even (PF=1).\r\n\r\n\r\n\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F 4B /r CMOVPO r16, r/m16 RM Valid Valid Move if parity odd (PF=0).\r\n 0F 4B /r CMOVPO r32, r/m32 RM Valid Valid Move if parity odd (PF=0).\r\n REX.W + 0F 4B /r CMOVPO r64, r/m64 RM Valid N.E. Move if parity odd (PF=0).\r\n 0F 48 /r CMOVS r16, r/m16 RM Valid Valid Move if sign (SF=1).\r\n 0F 48 /r CMOVS r32, r/m32 RM Valid Valid Move if sign (SF=1).\r\n REX.W + 0F 48 /r CMOVS r64, r/m64 RM Valid N.E. Move if sign (SF=1).\r\n 0F 44 /r CMOVZ r16, r/m16 RM Valid Valid Move if zero (ZF=1).\r\n 0F 44 /r CMOVZ r32, r/m32 RM Valid Valid Move if zero (ZF=1).\r\n REX.W + 0F 44 /r CMOVZ r64, r/m64 RM Valid N.E. Move if zero (ZF=1).\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nThe CMOVcc instructions check the state of one or more of the status flags in the EFLAGS register (CF, OF, PF, SF,\r\nand ZF) and perform a move operation if the flags are in a specified state (or condition). A condition code (cc) is\r\nassociated with each instruction to indicate the condition being tested for. If the condition is not satisfied, a move\r\nis not performed and execution continues with the instruction following the CMOVcc instruction.\r\nThese instructions can move 16-bit, 32-bit or 64-bit values from memory to a general-purpose register or from one\r\ngeneral-purpose register to another. Conditional moves of 8-bit register operands are not supported.\r\nThe condition for each CMOVcc mnemonic is given in the description column of the above table. The terms \"less\"\r\nand \"greater\" are used for comparisons of signed integers and the terms \"above\" and \"below\" are used for\r\nunsigned integers.\r\nBecause a particular state of the status flags can sometimes be interpreted in two ways, two mnemonics are\r\ndefined for some opcodes. For example, the CMOVA (conditional move if above) instruction and the CMOVNBE\r\n(conditional move if not below or equal) instruction are alternate mnemonics for the opcode 0F 47H.\r\nThe CMOVcc instructions were introduced in P6 family processors; however, these instructions may not be\r\nsupported by all IA-32 processors. Software can determine if the CMOVcc instructions are supported by checking\r\nthe processor's feature information with the CPUID instruction (see \"CPUID-CPU Identification\" in this chapter).\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-\r\ntional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the\r\nbeginning of this section for encoding data and limits.\r\n\r\nOperation\r\ntemp <- SRC\r\n\r\nIF condition TRUE\r\n THEN\r\n DEST <- temp;\r\n FI;\r\nELSE\r\n IF (OperandSize = 32 and IA-32e mode active)\r\n THEN\r\n DEST[63:32] <- 0;\r\n FI;\r\nFI;\r\n\r\n\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CMOVcc"
},
{
"description": "CMP-Compare Two Operands\r\nOpcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n3C ib CMP AL, imm8 I Valid Valid Compare imm8 with AL.\r\n3D iw CMP AX, imm16 I Valid Valid Compare imm16 with AX.\r\n3D id CMP EAX, imm32 I Valid Valid Compare imm32 with EAX.\r\nREX.W + 3D id CMP RAX, imm32 I Valid N.E. Compare imm32 sign-extended to 64-bits\r\n with RAX.\r\n80 /7 ib CMP r/m8, imm8 MI Valid Valid Compare imm8 with r/m8.\r\nREX + 80 /7 ib CMP r/m8*, imm8 MI Valid N.E. Compare imm8 with r/m8.\r\n81 /7 iw CMP r/m16, imm16 MI Valid Valid Compare imm16 with r/m16.\r\n81 /7 id CMP r/m32, imm32 MI Valid Valid Compare imm32 with r/m32.\r\nREX.W + 81 /7 id CMP r/m64, imm32 MI Valid N.E. Compare imm32 sign-extended to 64-bits\r\n with r/m64.\r\n83 /7 ib CMP r/m16, imm8 MI Valid Valid Compare imm8 with r/m16.\r\n83 /7 ib CMP r/m32, imm8 MI Valid Valid Compare imm8 with r/m32.\r\nREX.W + 83 /7 ib CMP r/m64, imm8 MI Valid N.E. Compare imm8 with r/m64.\r\n38 /r CMP r/m8, r8 MR Valid Valid Compare r8 with r/m8.\r\n * *\r\nREX + 38 /r CMP r/m8 , r8 MR Valid N.E. Compare r8 with r/m8.\r\n39 /r CMP r/m16, r16 MR Valid Valid Compare r16 with r/m16.\r\n39 /r CMP r/m32, r32 MR Valid Valid Compare r32 with r/m32.\r\nREX.W + 39 /r CMP r/m64,r64 MR Valid N.E. Compare r64 with r/m64.\r\n3A /r CMP r8, r/m8 RM Valid Valid Compare r/m8 with r8.\r\n * *\r\nREX + 3A /r CMP r8 , r/m8 RM Valid N.E. Compare r/m8 with r8.\r\n3B /r CMP r16, r/m16 RM Valid Valid Compare r/m16 with r16.\r\n3B /r CMP r32, r/m32 RM Valid Valid Compare r/m32 with r32.\r\nREX.W + 3B /r CMP r64, r/m64 RM Valid N.E. Compare r/m64 with r64.\r\nNOTES:\r\n* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r) ModRM:r/m (r) NA NA\r\n MR ModRM:r/m (r) ModRM:reg (r) NA NA\r\n MI ModRM:r/m (r) imm8 NA NA\r\n I AL/AX/EAX/RAX (r) imm8 NA NA\r\n\r\nDescription\r\nCompares the first source operand with the second source operand and sets the status flags in the EFLAGS register\r\naccording to the results. The comparison is performed by subtracting the second operand from the first operand\r\nand then setting the status flags in the same manner as the SUB instruction. When an immediate value is used as\r\nan operand, it is sign-extended to the length of the first operand.\r\nThe condition codes used by the Jcc, CMOVcc, and SETcc instructions are based on the results of a CMP instruction.\r\nAppendix B, \"EFLAGS Condition Codes,\" in the Intel 64 and IA-32 Architectures Software Developer's Manual,\r\nVolume 1, shows the relationship of the status flags and the condition codes.\r\n\r\n\r\n\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-\r\ntional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the\r\nbeginning of this section for encoding data and limits.\r\n\r\nOperation\r\ntemp <- SRC1 - SignExtend(SRC2);\r\nModifyStatusFlags; (* Modify status flags in the same manner as the SUB instruction*)\r\n\r\nFlags Affected\r\nThe CF, OF, SF, ZF, AF, and PF flags are set according to the result.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CMP"
},
{
"description": "CMPPD-Compare Packed Double-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0F C2 /r ib RMI V/V SSE2 Compare packed double-precision floating-point values\r\n CMPPD xmm1, xmm2/m128, imm8 in xmm2/m128 and xmm1 using bits 2:0 of imm8 as a\r\n comparison predicate.\r\n VEX.NDS.128.66.0F.WIG C2 /r ib RVMI V/V AVX Compare packed double-precision floating-point values\r\n VCMPPD xmm1, xmm2, xmm3/m128, in xmm3/m128 and xmm2 using bits 4:0 of imm8 as a\r\n imm8 comparison predicate.\r\n VEX.NDS.256.66.0F.WIG C2 /r ib RVMI V/V AVX Compare packed double-precision floating-point values\r\n VCMPPD ymm1, ymm2, ymm3/m256, in ymm3/m256 and ymm2 using bits 4:0 of imm8 as a\r\n imm8 comparison predicate.\r\n EVEX.NDS.128.66.0F.W1 C2 /r ib FV V/V AVX512VL Compare packed double-precision floating-point values\r\n VCMPPD k1 {k2}, xmm2, AVX512F in xmm3/m128/m64bcst and xmm2 using bits 4:0 of\r\n xmm3/m128/m64bcst, imm8 imm8 as a comparison predicate with writemask k2\r\n and leave the result in mask register k1.\r\n EVEX.NDS.256.66.0F.W1 C2 /r ib FV V/V AVX512VL Compare packed double-precision floating-point values\r\n VCMPPD k1 {k2}, ymm2, AVX512F in ymm3/m256/m64bcst and ymm2 using bits 4:0 of\r\n ymm3/m256/m64bcst, imm8 imm8 as a comparison predicate with writemask k2\r\n and leave the result in mask register k1.\r\n EVEX.NDS.512.66.0F.W1 C2 /r ib FV V/V AVX512F Compare packed double-precision floating-point values\r\n VCMPPD k1 {k2}, zmm2, in zmm3/m512/m64bcst and zmm2 using bits 4:0 of\r\n zmm3/m512/m64bcst{sae}, imm8 imm8 as a comparison predicate with writemask k2\r\n and leave the result in mask register k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (r, w) ModRM:r/m (r) Imm8 NA\r\n RVMI ModRM:reg (w) VEX.vvvv ModRM:r/m (r) Imm8\r\n FV ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) Imm8\r\n\r\nDescription\r\nPerforms a SIMD compare of the packed double-precision floating-point values in the second source operand and\r\nthe first source operand and returns the results of the comparison to the destination operand. The comparison\r\npredicate operand (immediate byte) specifies the type of comparison performed on each pair of packed values in\r\nthe two source operands.\r\nEVEX encoded versions: The first source operand (second operand) is a ZMM/YMM/XMM register. The second\r\nsource operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector\r\nbroadcasted from a 64-bit memory location. The destination operand (first operand) is an opmask register.\r\nComparison results are written to the destination operand under the writemask k2. Each comparison result is a\r\nsingle mask bit of 1 (comparison true) or 0 (comparison false).\r\nVEX.256 encoded version: The first source operand (second operand) is a YMM register. The second source\r\noperand (third operand) can be a YMM register or a 256-bit memory location. The destination operand (first\r\noperand) is a YMM register. Four comparisons are performed with results written to the destination operand. The\r\nresult of each comparison is a quadword mask of all 1s (comparison true) or all 0s (comparison false).\r\n128-bit Legacy SSE version: The first source and destination operand (first operand) is an XMM register. The\r\nsecond source operand (second operand) can be an XMM register or 128-bit memory location. Bits (MAX_VL-\r\n1:128) of the corresponding ZMM destination register remain unchanged. Two comparisons are performed with\r\nresults written to bits 127:0 of the destination operand. The result of each comparison is a quadword mask of all\r\n1s (comparison true) or all 0s (comparison false).\r\n\r\n\r\n\r\n\r\n\r\nVEX.128 encoded version: The first source operand (second operand) is an XMM register. The second source\r\noperand (third operand) can be an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the desti-\r\nnation ZMM register are zeroed. Two comparisons are performed with results written to bits 127:0 of the destina-\r\ntion operand.\r\nThe comparison predicate operand is an 8-bit immediate:\r\n. For instructions encoded using the VEX or EVEX prefix, bits 4:0 define the type of comparison to be performed\r\n (see Table 3-1). Bits 5 through 7 of the immediate are reserved.\r\n. For instruction encodings that do not use VEX prefix, bits 2:0 define the type of comparison to be made (see the\r\n first 8 rows of Table 3-1). Bits 3 through 7 of the immediate are reserved.\r\n\r\n\r\n Table 3-1. Comparison Predicate for CMPPD and CMPPS Instructions\r\nPredicate imm8 Description Result: A Is 1st Operand, B Is 2nd Operand Signals\r\n Value #IA on\r\n A >B A<B A=B Unordered1 QNAN\r\n\r\nEQ_OQ (EQ) 0H Equal (ordered, non-signaling) False False True False No\r\nLT_OS (LT) 1H Less-than (ordered, signaling) False True False False Yes\r\nLE_OS (LE) 2H Less-than-or-equal (ordered, signaling) False True True False Yes\r\nUNORD_Q (UNORD) 3H Unordered (non-signaling) False False False True No\r\nNEQ_UQ (NEQ) 4H Not-equal (unordered, non-signaling) True True False True No\r\nNLT_US (NLT) 5H Not-less-than (unordered, signaling) True False True True Yes\r\nNLE_US (NLE) 6H Not-less-than-or-equal (unordered, signaling) True False False True Yes\r\nORD_Q (ORD) 7H Ordered (non-signaling) True True True False No\r\nEQ_UQ 8H Equal (unordered, non-signaling) False False True True No\r\nNGE_US (NGE) 9H Not-greater-than-or-equal (unordered, False True False True Yes\r\n signaling)\r\nNGT_US (NGT) AH Not-greater-than (unordered, signaling) False True True True Yes\r\nFALSE_OQ(FALSE) BH False (ordered, non-signaling) False False False False No\r\nNEQ_OQ CH Not-equal (ordered, non-signaling) True True False False No\r\nGE_OS (GE) DH Greater-than-or-equal (ordered, signaling) True False True False Yes\r\nGT_OS (GT) EH Greater-than (ordered, signaling) True False False False Yes\r\nTRUE_UQ(TRUE) FH True (unordered, non-signaling) True True True True No\r\nEQ_OS 10H Equal (ordered, signaling) False False True False Yes\r\nLT_OQ 11H Less-than (ordered, nonsignaling) False True False False No\r\nLE_OQ 12H Less-than-or-equal (ordered, nonsignaling) False True True False No\r\nUNORD_S 13H Unordered (signaling) False False False True Yes\r\nNEQ_US 14H Not-equal (unordered, signaling) True True False True Yes\r\nNLT_UQ 15H Not-less-than (unordered, nonsignaling) True False True True No\r\nNLE_UQ 16H Not-less-than-or-equal (unordered, nonsig- True False False True No\r\n naling)\r\nORD_S 17H Ordered (signaling) True True True False Yes\r\n\r\n\r\nEQ_US 18H Equal (unordered, signaling) False False True True Yes\r\nNGE_UQ 19H Not-greater-than-or-equal (unordered, non- False True False True No\r\n signaling)\r\n\r\n\r\n\r\n\r\n Table 3-1. Comparison Predicate for CMPPD and CMPPS Instructions (Contd.)\r\n Predicate imm8 Description Result: A Is 1st Operand, B Is 2nd Operand Signals\r\n Value #IA on\r\n A >B A<B A=B Unordered1 QNAN\r\n\r\n NGT_UQ 1AH Not-greater-than (unordered, nonsignaling) False True True True No\r\n FALSE_OS 1BH False (ordered, signaling) False False False False Yes\r\n NEQ_OS 1CH Not-equal (ordered, signaling) True True False False Yes\r\n GE_OQ 1DH Greater-than-or-equal (ordered, nonsignal- True False True False No\r\n ing)\r\n GT_OQ 1EH Greater-than (ordered, nonsignaling) True False False False No\r\n TRUE_US 1FH True (unordered, signaling) True True True True Yes\r\n\r\n\r\nNOTES:\r\n1. If either operand A or B is a NAN.\r\n\r\nThe unordered relationship is true when at least one of the two source operands being compared is a NaN; the\r\nordered relationship is true when neither source operand is a NaN.\r\nA subsequent computational instruction that uses the mask result in the destination operand as an input operand\r\nwill not generate an exception, because a mask of all 0s corresponds to a floating-point value of +0.0 and a mask\r\nof all 1s corresponds to a QNaN.\r\nNote that processors with \"CPUID.1H:ECX.AVX =0\" do not implement the \"greater-than\", \"greater-than-or-equal\",\r\n\"not-greater than\", and \"not-greater-than-or-equal relations\" predicates. These comparisons can be made either\r\nby using the inverse relationship (that is, use the \"not-less-than-or-equal\" to make a \"greater-than\" comparison)\r\nor by using software emulation. When using software emulation, the program must swap the operands (copying\r\nregisters when necessary to protect the data that will now be in the destination), and then perform the compare\r\nusing a different predicate. The predicate to be used for these emulations is listed in the first 8 rows of Table 3-7\r\n(Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A) under the heading Emulation.\r\nCompilers and assemblers may implement the following two-operand pseudo-ops in addition to the three-operand\r\nCMPPD instruction, for processors with \"CPUID.1H:ECX.AVX =0\". See Table 3-2. Compiler should treat reserved\r\nImm8 values as illegal syntax.\r\n Table 3-2. Pseudo-Op and CMPPD Implementation\r\n:\r\n\r\n\r\n\r\n\r\n Pseudo-Op CMPPD Implementation\r\n CMPEQPD xmm1, xmm2 CMPPD xmm1, xmm2, 0\r\n CMPLTPD xmm1, xmm2 CMPPD xmm1, xmm2, 1\r\n CMPLEPD xmm1, xmm2 CMPPD xmm1, xmm2, 2\r\n CMPUNORDPD xmm1, xmm2 CMPPD xmm1, xmm2, 3\r\n CMPNEQPD xmm1, xmm2 CMPPD xmm1, xmm2, 4\r\n CMPNLTPD xmm1, xmm2 CMPPD xmm1, xmm2, 5\r\n CMPNLEPD xmm1, xmm2 CMPPD xmm1, xmm2, 6\r\n CMPORDPD xmm1, xmm2 CMPPD xmm1, xmm2, 7\r\n\r\nThe greater-than relations that the processor does not implement require more than one instruction to emulate in\r\nsoftware and therefore should not be implemented as pseudo-ops. (For these, the programmer should reverse the\r\noperands of the corresponding less than relations and use move instructions to ensure that the mask is moved to\r\nthe correct destination register and that the source operand is left intact.)\r\nProcessors with \"CPUID.1H:ECX.AVX =1\" implement the full complement of 32 predicates shown in Table 3-3, soft-\r\nware emulation is no longer needed. Compilers and assemblers may implement the following three-operand\r\npseudo-ops in addition to the four-operand VCMPPD instruction. See Table 3-3, where the notations of reg1 reg2,\r\nand reg3 represent either XMM registers or YMM registers. Compiler should treat reserved Imm8 values as illegal\r\n\r\n\r\n\r\nsyntax. Alternately, intrinsics can map the pseudo-ops to pre-defined constants to support a simpler intrinsic inter-\r\nface. Compilers and assemblers may implement three-operand pseudo-ops for EVEX encoded VCMPPD instructions\r\nin a similar fashion by extending the syntax listed in Table 3-3.\r\n Table 3-3. Pseudo-Op and VCMPPD Implementation\r\n:\r\n\r\n\r\n\r\n\r\n Pseudo-Op CMPPD Implementation\r\n VCMPEQPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 0\r\n VCMPLTPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 1\r\n VCMPLEPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 2\r\n VCMPUNORDPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 3\r\n VCMPNEQPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 4\r\n VCMPNLTPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 5\r\n VCMPNLEPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 6\r\n VCMPORDPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 7\r\n VCMPEQ_UQPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 8\r\n VCMPNGEPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 9\r\n VCMPNGTPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 0AH\r\n VCMPFALSEPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 0BH\r\n VCMPNEQ_OQPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 0CH\r\n VCMPGEPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 0DH\r\n VCMPGTPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 0EH\r\n VCMPTRUEPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 0FH\r\n VCMPEQ_OSPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 10H\r\n VCMPLT_OQPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 11H\r\n VCMPLE_OQPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 12H\r\n VCMPUNORD_SPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 13H\r\n VCMPNEQ_USPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 14H\r\n VCMPNLT_UQPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 15H\r\n VCMPNLE_UQPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 16H\r\n VCMPORD_SPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 17H\r\n VCMPEQ_USPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 18H\r\n VCMPNGE_UQPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 19H\r\n VCMPNGT_UQPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 1AH\r\n VCMPFALSE_OSPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 1BH\r\n VCMPNEQ_OSPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 1CH\r\n VCMPGE_OQPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 1DH\r\n VCMPGT_OQPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 1EH\r\n VCMPTRUE_USPD reg1, reg2, reg3 VCMPPD reg1, reg2, reg3, 1FH\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nCASE (COMPARISON PREDICATE) OF\r\n0: OP3 <- EQ_OQ; OP5 <- EQ_OQ;\r\n 1: OP3 <- LT_OS; OP5 <- LT_OS;\r\n 2: OP3 <- LE_OS; OP5 <- LE_OS;\r\n 3: OP3 <- UNORD_Q; OP5 <- UNORD_Q;\r\n 4: OP3 <- NEQ_UQ; OP5 <- NEQ_UQ;\r\n 5: OP3 <- NLT_US; OP5 <- NLT_US;\r\n 6: OP3 <- NLE_US; OP5 <- NLE_US;\r\n 7: OP3 <- ORD_Q; OP5 <- ORD_Q;\r\n 8: OP5 <- EQ_UQ;\r\n 9: OP5 <- NGE_US;\r\n 10: OP5 <- NGT_US;\r\n 11: OP5 <- FALSE_OQ;\r\n 12: OP5 <- NEQ_OQ;\r\n 13: OP5 <- GE_OS;\r\n 14: OP5 <- GT_OS;\r\n 15: OP5 <- TRUE_UQ;\r\n 16: OP5 <- EQ_OS;\r\n 17: OP5 <- LT_OQ;\r\n 18: OP5 <- LE_OQ;\r\n 19: OP5 <- UNORD_S;\r\n 20: OP5 <- NEQ_US;\r\n 21: OP5 <- NLT_UQ;\r\n 22: OP5 <- NLE_UQ;\r\n 23: OP5 <- ORD_S;\r\n 24: OP5 <- EQ_US;\r\n 25: OP5 <- NGE_UQ;\r\n 26: OP5 <- NGT_UQ;\r\n 27: OP5 <- FALSE_OS;\r\n 28: OP5 <- NEQ_OS;\r\n 29: OP5 <- GE_OQ;\r\n 30: OP5 <- GT_OQ;\r\n 31: OP5 <- TRUE_US;\r\n DEFAULT: Reserved;\r\nESAC;\r\n\r\n\r\n\r\n\r\n\r\nVCMPPD (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k2[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN\r\n CMP <- SRC1[i+63:i] OP5 SRC2[63:0]\r\n ELSE\r\n CMP <- SRC1[i+63:i] OP5 SRC2[i+63:i]\r\n FI;\r\n IF CMP = TRUE\r\n THEN DEST[j] <- 1;\r\n ELSE DEST[j] <- 0; FI;\r\n ELSE DEST[j] <- 0 ; zeroing-masking only\r\n FI;\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\nVCMPPD (VEX.256 encoded version)\r\nCMP0 <- SRC1[63:0] OP5 SRC2[63:0];\r\nCMP1 <- SRC1[127:64] OP5 SRC2[127:64];\r\nCMP2 <- SRC1[191:128] OP5 SRC2[191:128];\r\nCMP3 <- SRC1[255:192] OP5 SRC2[255:192];\r\nIF CMP0 = TRUE\r\n THEN DEST[63:0] <- FFFFFFFFFFFFFFFFH;\r\n ELSE DEST[63:0] <- 0000000000000000H; FI;\r\nIF CMP1 = TRUE\r\n THEN DEST[127:64] <- FFFFFFFFFFFFFFFFH;\r\n ELSE DEST[127:64] <- 0000000000000000H; FI;\r\nIF CMP2 = TRUE\r\n THEN DEST[191:128] <- FFFFFFFFFFFFFFFFH;\r\n ELSE DEST[191:128] <- 0000000000000000H; FI;\r\nIF CMP3 = TRUE\r\n THEN DEST[255:192] <- FFFFFFFFFFFFFFFFH;\r\n ELSE DEST[255:192] <- 0000000000000000H; FI;\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVCMPPD (VEX.128 encoded version)\r\nCMP0 <- SRC1[63:0] OP5 SRC2[63:0];\r\nCMP1 <- SRC1[127:64] OP5 SRC2[127:64];\r\nIF CMP0 = TRUE\r\n THEN DEST[63:0] <- FFFFFFFFFFFFFFFFH;\r\n ELSE DEST[63:0] <- 0000000000000000H; FI;\r\nIF CMP1 = TRUE\r\n THEN DEST[127:64] <- FFFFFFFFFFFFFFFFH;\r\n ELSE DEST[127:64] <- 0000000000000000H; FI;\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nCMPPD (128-bit Legacy SSE version)\r\nCMP0 <- SRC1[63:0] OP3 SRC2[63:0];\r\nCMP1 <- SRC1[127:64] OP3 SRC2[127:64];\r\nIF CMP0 = TRUE\r\n THEN DEST[63:0] <- FFFFFFFFFFFFFFFFH;\r\n ELSE DEST[63:0] <- 0000000000000000H; FI;\r\nIF CMP1 = TRUE\r\n THEN DEST[127:64] <- FFFFFFFFFFFFFFFFH;\r\n ELSE DEST[127:64] <- 0000000000000000H; FI;\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCMPPD __mmask8 _mm512_cmp_pd_mask( __m512d a, __m512d b, int imm);\r\nVCMPPD __mmask8 _mm512_cmp_round_pd_mask( __m512d a, __m512d b, int imm, int sae);\r\nVCMPPD __mmask8 _mm512_mask_cmp_pd_mask( __mmask8 k1, __m512d a, __m512d b, int imm);\r\nVCMPPD __mmask8 _mm512_mask_cmp_round_pd_mask( __mmask8 k1, __m512d a, __m512d b, int imm, int sae);\r\nVCMPPD __mmask8 _mm256_cmp_pd_mask( __m256d a, __m256d b, int imm);\r\nVCMPPD __mmask8 _mm256_mask_cmp_pd_mask( __mmask8 k1, __m256d a, __m256d b, int imm);\r\nVCMPPD __mmask8 _mm_cmp_pd_mask( __m128d a, __m128d b, int imm);\r\nVCMPPD __mmask8 _mm_mask_cmp_pd_mask( __mmask8 k1, __m128d a, __m128d b, int imm);\r\nVCMPPD __m256 _mm256_cmp_pd(__m256d a, __m256d b, int imm)\r\n(V)CMPPD __m128 _mm_cmp_pd(__m128d a, __m128d b, int imm)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid if SNaN operand and invalid if QNaN and predicate as listed in Table 3-1.\r\nDenormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2.\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CMPPD"
},
{
"description": "CMPPS-Compare Packed Single-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 0F C2 /r ib RMI V/V SSE Compare packed single-precision floating-point values in\r\n CMPPS xmm1, xmm2/m128, xmm2/m128 and xmm1 using bits 2:0 of imm8 as a\r\n imm8 comparison predicate.\r\n VEX.NDS.128.0F.WIG C2 /r ib RVMI V/V AVX Compare packed single-precision floating-point values in\r\n VCMPPS xmm1, xmm2, xmm3/m128 and xmm2 using bits 4:0 of imm8 as a\r\n xmm3/m128, imm8 comparison predicate.\r\n VEX.NDS.256.0F.WIG C2 /r ib RVMI V/V AVX Compare packed single-precision floating-point values in\r\n VCMPPS ymm1, ymm2, ymm3/m256 and ymm2 using bits 4:0 of imm8 as a\r\n ymm3/m256, imm8 comparison predicate.\r\n EVEX.NDS.128.0F.W0 C2 /r ib FV V/V AVX512VL Compare packed single-precision floating-point values in\r\n VCMPPS k1 {k2}, xmm2, AVX512F xmm3/m128/m32bcst and xmm2 using bits 4:0 of imm8 as\r\n xmm3/m128/m32bcst, imm8 a comparison predicate with writemask k2 and leave the\r\n result in mask register k1.\r\n EVEX.NDS.256.0F.W0 C2 /r ib FV V/V AVX512VL Compare packed single-precision floating-point values in\r\n VCMPPS k1 {k2}, ymm2, AVX512F ymm3/m256/m32bcst and ymm2 using bits 4:0 of imm8 as\r\n ymm3/m256/m32bcst, imm8 a comparison predicate with writemask k2 and leave the\r\n result in mask register k1.\r\n EVEX.NDS.512.0F.W0 C2 /r ib FV V/V AVX512F Compare packed single-precision floating-point values in\r\n VCMPPS k1 {k2}, zmm2, zmm3/m512/m32bcst and zmm2 using bits 4:0 of imm8 as\r\n zmm3/m512/m32bcst{sae}, imm8 a comparison predicate with writemask k2 and leave the\r\n result in mask register k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (r, w) ModRM:r/m (r) Imm8 NA\r\n RVMI ModRM:reg (w) VEX.vvvv ModRM:r/m (r) Imm8\r\n FV ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) Imm8\r\n\r\nDescription\r\nPerforms a SIMD compare of the packed single-precision floating-point values in the second source operand and\r\nthe first source operand and returns the results of the comparison to the destination operand. The comparison\r\npredicate operand (immediate byte) specifies the type of comparison performed on each of the pairs of packed\r\nvalues.\r\nEVEX encoded versions: The first source operand (second operand) is a ZMM/YMM/XMM register. The second\r\nsource operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector\r\nbroadcasted from a 32-bit memory location. The destination operand (first operand) is an opmask register.\r\nComparison results are written to the destination operand under the writemask k2. Each comparison result is a\r\nsingle mask bit of 1 (comparison true) or 0 (comparison false).\r\nVEX.256 encoded version: The first source operand (second operand) is a YMM register. The second source operand\r\n(third operand) can be a YMM register or a 256-bit memory location. The destination operand (first operand) is a\r\nYMM register. Eight comparisons are performed with results written to the destination operand. The result of each\r\ncomparison is a doubleword mask of all 1s (comparison true) or all 0s (comparison false).\r\n128-bit Legacy SSE version: The first source and destination operand (first operand) is an XMM register. The\r\nsecond source operand (second operand) can be an XMM register or 128-bit memory location. Bits (MAX_VL-\r\n1:128) of the corresponding ZMM destination register remain unchanged. Four comparisons are performed with\r\nresults written to bits 127:0 of the destination operand. The result of each comparison is a doubleword mask of all\r\n1s (comparison true) or all 0s (comparison false).\r\n\r\n\r\n\r\n\r\n\r\nVEX.128 encoded version: The first source operand (second operand) is an XMM register. The second source\r\noperand (third operand) can be an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the desti-\r\nnation ZMM register are zeroed. Four comparisons are performed with results written to bits 127:0 of the destina-\r\ntion operand.\r\nThe comparison predicate operand is an 8-bit immediate:\r\n. For instructions encoded using the VEX prefix and EVEX prefix, bits 4:0 define the type of comparison to be\r\n performed (see Table 3-1). Bits 5 through 7 of the immediate are reserved.\r\n. For instruction encodings that do not use VEX prefix, bits 2:0 define the type of comparison to be made (see\r\n the first 8 rows of Table 3-1). Bits 3 through 7 of the immediate are reserved.\r\nThe unordered relationship is true when at least one of the two source operands being compared is a NaN; the\r\nordered relationship is true when neither source operand is a NaN.\r\nA subsequent computational instruction that uses the mask result in the destination operand as an input operand\r\nwill not generate an exception, because a mask of all 0s corresponds to a floating-point value of +0.0 and a mask\r\nof all 1s corresponds to a QNaN.\r\nNote that processors with \"CPUID.1H:ECX.AVX =0\" do not implement the \"greater-than\", \"greater-than-or-equal\",\r\n\"not-greater than\", and \"not-greater-than-or-equal relations\" predicates. These comparisons can be made either\r\nby using the inverse relationship (that is, use the \"not-less-than-or-equal\" to make a \"greater-than\" comparison)\r\nor by using software emulation. When using software emulation, the program must swap the operands (copying\r\nregisters when necessary to protect the data that will now be in the destination), and then perform the compare\r\nusing a different predicate. The predicate to be used for these emulations is listed in the first 8 rows of Table 3-7\r\n(Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A) under the heading Emulation.\r\nCompilers and assemblers may implement the following two-operand pseudo-ops in addition to the three-operand\r\nCMPPS instruction, for processors with \"CPUID.1H:ECX.AVX =0\". See Table 3-4. Compiler should treat reserved\r\nImm8 values as illegal syntax.\r\n Table 3-4. Pseudo-Op and CMPPS Implementation\r\n:\r\n\r\n\r\n\r\n\r\n Pseudo-Op CMPPS Implementation\r\n CMPEQPS xmm1, xmm2 CMPPS xmm1, xmm2, 0\r\n CMPLTPS xmm1, xmm2 CMPPS xmm1, xmm2, 1\r\n CMPLEPS xmm1, xmm2 CMPPS xmm1, xmm2, 2\r\n CMPUNORDPS xmm1, xmm2 CMPPS xmm1, xmm2, 3\r\n CMPNEQPS xmm1, xmm2 CMPPS xmm1, xmm2, 4\r\n CMPNLTPS xmm1, xmm2 CMPPS xmm1, xmm2, 5\r\n CMPNLEPS xmm1, xmm2 CMPPS xmm1, xmm2, 6\r\n CMPORDPS xmm1, xmm2 CMPPS xmm1, xmm2, 7\r\n\r\nThe greater-than relations that the processor does not implement require more than one instruction to emulate in\r\nsoftware and therefore should not be implemented as pseudo-ops. (For these, the programmer should reverse the\r\noperands of the corresponding less than relations and use move instructions to ensure that the mask is moved to\r\nthe correct destination register and that the source operand is left intact.)\r\nProcessors with \"CPUID.1H:ECX.AVX =1\" implement the full complement of 32 predicates shown in Table 3-5, soft-\r\nware emulation is no longer needed. Compilers and assemblers may implement the following three-operand\r\npseudo-ops in addition to the four-operand VCMPPS instruction. See Table 3-5, where the notation of reg1 and\r\nreg2 represent either XMM registers or YMM registers. Compiler should treat reserved Imm8 values as illegal\r\nsyntax. Alternately, intrinsics can map the pseudo-ops to pre-defined constants to support a simpler intrinsic inter-\r\nface. Compilers and assemblers may implement three-operand pseudo-ops for EVEX encoded VCMPPS instructions\r\nin a similar fashion by extending the syntax listed in Table 3-5.\r\n:\r\n\r\n\r\n\r\n\r\n\r\n Table 3-5. Pseudo-Op and VCMPPS Implementation\r\n Pseudo-Op CMPPS Implementation\r\n VCMPEQPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 0\r\n VCMPLTPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 1\r\n VCMPLEPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 2\r\n VCMPUNORDPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 3\r\n VCMPNEQPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 4\r\n VCMPNLTPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 5\r\n VCMPNLEPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 6\r\n VCMPORDPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 7\r\n VCMPEQ_UQPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 8\r\n VCMPNGEPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 9\r\n VCMPNGTPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 0AH\r\n VCMPFALSEPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 0BH\r\n VCMPNEQ_OQPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 0CH\r\n VCMPGEPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 0DH\r\n VCMPGTPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 0EH\r\n VCMPTRUEPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 0FH\r\n VCMPEQ_OSPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 10H\r\n VCMPLT_OQPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 11H\r\n VCMPLE_OQPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 12H\r\n VCMPUNORD_SPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 13H\r\n VCMPNEQ_USPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 14H\r\n VCMPNLT_UQPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 15H\r\n VCMPNLE_UQPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 16H\r\n VCMPORD_SPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 17H\r\n VCMPEQ_USPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 18H\r\n VCMPNGE_UQPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 19H\r\n VCMPNGT_UQPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 1AH\r\n VCMPFALSE_OSPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 1BH\r\n VCMPNEQ_OSPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 1CH\r\n VCMPGE_OQPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 1DH\r\n VCMPGT_OQPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 1EH\r\n VCMPTRUE_USPS reg1, reg2, reg3 VCMPPS reg1, reg2, reg3, 1FH\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nCASE (COMPARISON PREDICATE) OF\r\n 0: OP3 <- EQ_OQ; OP5 <- EQ_OQ;\r\n 1: OP3 <- LT_OS; OP5 <- LT_OS;\r\n 2: OP3 <- LE_OS; OP5 <- LE_OS;\r\n 3: OP3 <- UNORD_Q; OP5 <- UNORD_Q;\r\n 4: OP3 <- NEQ_UQ; OP5 <- NEQ_UQ;\r\n 5: OP3 <- NLT_US; OP5 <- NLT_US;\r\n 6: OP3 <- NLE_US; OP5 <- NLE_US;\r\n 7: OP3 <- ORD_Q; OP5 <- ORD_Q;\r\n 8: OP5 <- EQ_UQ;\r\n 9: OP5 <- NGE_US;\r\n 10: OP5 <- NGT_US;\r\n 11: OP5 <- FALSE_OQ;\r\n 12: OP5 <- NEQ_OQ;\r\n 13: OP5 <- GE_OS;\r\n 14: OP5 <- GT_OS;\r\n 15: OP5 <- TRUE_UQ;\r\n 16: OP5 <- EQ_OS;\r\n 17: OP5 <- LT_OQ;\r\n 18: OP5 <- LE_OQ;\r\n 19: OP5 <- UNORD_S;\r\n 20: OP5 <- NEQ_US;\r\n 21: OP5 <- NLT_UQ;\r\n 22: OP5 <- NLE_UQ;\r\n 23: OP5 <- ORD_S;\r\n 24: OP5 <- EQ_US;\r\n 25: OP5 <- NGE_UQ;\r\n 26: OP5 <- NGT_UQ;\r\n 27: OP5 <- FALSE_OS;\r\n 28: OP5 <- NEQ_OS;\r\n 29: OP5 <- GE_OQ;\r\n 30: OP5 <- GT_OQ;\r\n 31: OP5 <- TRUE_US;\r\n DEFAULT: Reserved\r\nESAC;\r\n\r\n\r\n\r\n\r\n\r\nVCMPPS (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k2[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN\r\n CMP <- SRC1[i+31:i] OP5 SRC2[31:0]\r\n ELSE\r\n CMP <- SRC1[i+31:i] OP5 SRC2[i+31:i]\r\n FI;\r\n IF CMP = TRUE\r\n THEN DEST[j] <- 1;\r\n ELSE DEST[j] <- 0; FI;\r\n ELSE DEST[j] <- 0 ; zeroing-masking onlyFI;\r\n FI;\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\nVCMPPS (VEX.256 encoded version)\r\nCMP0 <- SRC1[31:0] OP5 SRC2[31:0];\r\nCMP1 <- SRC1[63:32] OP5 SRC2[63:32];\r\nCMP2 <- SRC1[95:64] OP5 SRC2[95:64];\r\nCMP3 <- SRC1[127:96] OP5 SRC2[127:96];\r\nCMP4 <- SRC1[159:128] OP5 SRC2[159:128];\r\nCMP5 <- SRC1[191:160] OP5 SRC2[191:160];\r\nCMP6 <- SRC1[223:192] OP5 SRC2[223:192];\r\nCMP7 <- SRC1[255:224] OP5 SRC2[255:224];\r\nIF CMP0 = TRUE\r\n THEN DEST[31:0] <-FFFFFFFFH;\r\n ELSE DEST[31:0] <- 000000000H; FI;\r\nIF CMP1 = TRUE\r\n THEN DEST[63:32] <- FFFFFFFFH;\r\n ELSE DEST[63:32] <-000000000H; FI;\r\nIF CMP2 = TRUE\r\n THEN DEST[95:64] <- FFFFFFFFH;\r\n ELSE DEST[95:64] <- 000000000H; FI;\r\nIF CMP3 = TRUE\r\n THEN DEST[127:96] <- FFFFFFFFH;\r\n ELSE DEST[127:96] <- 000000000H; FI;\r\nIF CMP4 = TRUE\r\n THEN DEST[159:128] <- FFFFFFFFH;\r\n ELSE DEST[159:128] <- 000000000H; FI;\r\nIF CMP5 = TRUE\r\n THEN DEST[191:160] <- FFFFFFFFH;\r\n ELSE DEST[191:160] <- 000000000H; FI;\r\nIF CMP6 = TRUE\r\n THEN DEST[223:192] <- FFFFFFFFH;\r\n ELSE DEST[223:192] <-000000000H; FI;\r\nIF CMP7 = TRUE\r\n THEN DEST[255:224] <- FFFFFFFFH;\r\n ELSE DEST[255:224] <- 000000000H; FI;\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\n\r\n\r\nVCMPPS (VEX.128 encoded version)\r\nCMP0 <- SRC1[31:0] OP5 SRC2[31:0];\r\nCMP1 <- SRC1[63:32] OP5 SRC2[63:32];\r\nCMP2 <- SRC1[95:64] OP5 SRC2[95:64];\r\nCMP3 <- SRC1[127:96] OP5 SRC2[127:96];\r\nIF CMP0 = TRUE\r\n THEN DEST[31:0] <-FFFFFFFFH;\r\n ELSE DEST[31:0] <- 000000000H; FI;\r\nIF CMP1 = TRUE\r\n THEN DEST[63:32] <- FFFFFFFFH;\r\n ELSE DEST[63:32] <- 000000000H; FI;\r\nIF CMP2 = TRUE\r\n THEN DEST[95:64] <- FFFFFFFFH;\r\n ELSE DEST[95:64] <- 000000000H; FI;\r\nIF CMP3 = TRUE\r\n THEN DEST[127:96] <- FFFFFFFFH;\r\n ELSE DEST[127:96] <-000000000H; FI;\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nCMPPS (128-bit Legacy SSE version)\r\nCMP0 <- SRC1[31:0] OP3 SRC2[31:0];\r\nCMP1 <- SRC1[63:32] OP3 SRC2[63:32];\r\nCMP2 <- SRC1[95:64] OP3 SRC2[95:64];\r\nCMP3 <- SRC1[127:96] OP3 SRC2[127:96];\r\nIF CMP0 = TRUE\r\n THEN DEST[31:0] <-FFFFFFFFH;\r\n ELSE DEST[31:0] <- 000000000H; FI;\r\nIF CMP1 = TRUE\r\n THEN DEST[63:32] <- FFFFFFFFH;\r\n ELSE DEST[63:32] <- 000000000H; FI;\r\nIF CMP2 = TRUE\r\n THEN DEST[95:64] <- FFFFFFFFH;\r\n ELSE DEST[95:64] <- 000000000H; FI;\r\nIF CMP3 = TRUE\r\n THEN DEST[127:96] <- FFFFFFFFH;\r\n ELSE DEST[127:96] <-000000000H; FI;\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCMPPS __mmask16 _mm512_cmp_ps_mask( __m512 a, __m512 b, int imm);\r\nVCMPPS __mmask16 _mm512_cmp_round_ps_mask( __m512 a, __m512 b, int imm, int sae);\r\nVCMPPS __mmask16 _mm512_mask_cmp_ps_mask( __mmask16 k1, __m512 a, __m512 b, int imm);\r\nVCMPPS __mmask16 _mm512_mask_cmp_round_ps_mask( __mmask16 k1, __m512 a, __m512 b, int imm, int sae);\r\nVCMPPD __mmask8 _mm256_cmp_ps_mask( __m256 a, __m256 b, int imm);\r\nVCMPPS __mmask8 _mm256_mask_cmp_ps_mask( __mmask8 k1, __m256 a, __m256 b, int imm);\r\nVCMPPS __mmask8 _mm_cmp_ps_mask( __m128 a, __m128 b, int imm);\r\nVCMPPS __mmask8 _mm_mask_cmp_ps_mask( __mmask8 k1, __m128 a, __m128 b, int imm);\r\nVCMPPS __m256 _mm256_cmp_ps(__m256 a, __m256 b, int imm)\r\nCMPPS __m128 _mm_cmp_ps(__m128 a, __m128 b, int imm)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid if SNaN operand and invalid if QNaN and predicate as listed in Table 3-1.\r\nDenormal\r\n\r\n\r\n\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2.\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CMPPS"
},
{
"description": "CMPS/CMPSB/CMPSW/CMPSD/CMPSQ-Compare String Operands\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n A6 CMPS m8, m8 NP Valid Valid For legacy mode, compare byte at address DS:(E)SI with\r\n byte at address ES:(E)DI; For 64-bit mode compare byte\r\n at address (R|E)SI to byte at address (R|E)DI. The status\r\n flags are set accordingly.\r\n A7 CMPS m16, m16 NP Valid Valid For legacy mode, compare word at address DS:(E)SI\r\n with word at address ES:(E)DI; For 64-bit mode\r\n compare word at address (R|E)SI with word at address\r\n (R|E)DI. The status flags are set accordingly.\r\n A7 CMPS m32, m32 NP Valid Valid For legacy mode, compare dword at address DS:(E)SI at\r\n dword at address ES:(E)DI; For 64-bit mode compare\r\n dword at address (R|E)SI at dword at address (R|E)DI.\r\n The status flags are set accordingly.\r\n REX.W + A7 CMPS m64, m64 NP Valid N.E. Compares quadword at address (R|E)SI with quadword\r\n at address (R|E)DI and sets the status flags accordingly.\r\n A6 CMPSB NP Valid Valid For legacy mode, compare byte at address DS:(E)SI with\r\n byte at address ES:(E)DI; For 64-bit mode compare byte\r\n at address (R|E)SI with byte at address (R|E)DI. The\r\n status flags are set accordingly.\r\n A7 CMPSW NP Valid Valid For legacy mode, compare word at address DS:(E)SI\r\n with word at address ES:(E)DI; For 64-bit mode\r\n compare word at address (R|E)SI with word at address\r\n (R|E)DI. The status flags are set accordingly.\r\n A7 CMPSD NP Valid Valid For legacy mode, compare dword at address DS:(E)SI\r\n with dword at address ES:(E)DI; For 64-bit mode\r\n compare dword at address (R|E)SI with dword at\r\n address (R|E)DI. The status flags are set accordingly.\r\n REX.W + A7 CMPSQ NP Valid N.E. Compares quadword at address (R|E)SI with quadword\r\n at address (R|E)DI and sets the status flags accordingly.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nCompares the byte, word, doubleword, or quadword specified with the first source operand with the byte, word,\r\ndoubleword, or quadword specified with the second source operand and sets the status flags in the EFLAGS register\r\naccording to the results.\r\nBoth source operands are located in memory. The address of the first source operand is read from DS:SI, DS:ESI\r\nor RSI (depending on the address-size attribute of the instruction is 16, 32, or 64, respectively). The address of the\r\nsecond source operand is read from ES:DI, ES:EDI or RDI (again depending on the address-size attribute of the\r\ninstruction is 16, 32, or 64). The DS segment may be overridden with a segment override prefix, but the ES\r\nsegment cannot be overridden.\r\nAt the assembly-code level, two forms of this instruction are allowed: the \"explicit-operands\" form and the \"no-\r\noperands\" form. The explicit-operands form (specified with the CMPS mnemonic) allows the two source operands\r\nto be specified explicitly. Here, the source operands should be symbols that indicate the size and location of the\r\nsource values. This explicit-operand form is provided to allow documentation. However, note that the documenta-\r\ntion provided by this form can be misleading. That is, the source operand symbols must specify the correct type\r\n(size) of the operands (bytes, words, or doublewords, quadwords), but they do not have to specify the correct loca-\r\n\r\n\r\n\r\n\r\ntion. Locations of the source operands are always specified by the DS:(E)SI (or RSI) and ES:(E)DI (or RDI) regis-\r\nters, which must be loaded correctly before the compare string instruction is executed.\r\nThe no-operands form provides \"short forms\" of the byte, word, and doubleword versions of the CMPS instructions.\r\nHere also the DS:(E)SI (or RSI) and ES:(E)DI (or RDI) registers are assumed by the processor to specify the loca-\r\ntion of the source operands. The size of the source operands is selected with the mnemonic: CMPSB (byte compar-\r\nison), CMPSW (word comparison), CMPSD (doubleword comparison), or CMPSQ (quadword comparison using\r\nREX.W).\r\nAfter the comparison, the (E/R)SI and (E/R)DI registers increment or decrement automatically according to the\r\nsetting of the DF flag in the EFLAGS register. (If the DF flag is 0, the (E/R)SI and (E/R)DI register increment; if the\r\nDF flag is 1, the registers decrement.) The registers increment or decrement by 1 for byte operations, by 2 for word\r\noperations, 4 for doubleword operations. If operand size is 64, RSI and RDI registers increment by 8 for quadword\r\noperations.\r\nThe CMPS, CMPSB, CMPSW, CMPSD, and CMPSQ instructions can be preceded by the REP prefix for block compar-\r\nisons. More often, however, these instructions will be used in a LOOP construct that takes some action based on the\r\nsetting of the status flags before the next comparison is made. See \"REP/REPE/REPZ /REPNE/REPNZ-Repeat\r\nString Operation Prefix\" in Chapter 4 of the Intel 64 and IA-32 Architectures Software Developer's Manual,\r\nVolume 2B, for a description of the REP prefix.\r\nIn 64-bit mode, the instruction's default address size is 64 bits, 32 bit address size is supported using the prefix\r\n67H. Use of the REX.W prefix promotes doubleword operation to 64 bits (see CMPSQ). See the summary chart at\r\nthe beginning of this section for encoding data and limits.\r\n\r\nOperation\r\ntemp <- SRC1 - SRC2;\r\nSetStatusFlags(temp);\r\n\r\nIF (64-Bit Mode)\r\n THEN\r\n IF (Byte comparison)\r\n THEN IF DF = 0\r\n THEN\r\n (R|E)SI <- (R|E)SI + 1;\r\n (R|E)DI <- (R|E)DI + 1;\r\n ELSE\r\n (R|E)SI <- (R|E)SI - 1;\r\n (R|E)DI <- (R|E)DI - 1;\r\n FI;\r\n ELSE IF (Word comparison)\r\n THEN IF DF = 0\r\n THEN\r\n (R|E)SI <- (R|E)SI + 2;\r\n (R|E)DI <- (R|E)DI + 2;\r\n ELSE\r\n (R|E)SI <- (R|E)SI - 2;\r\n (R|E)DI <- (R|E)DI - 2;\r\n FI;\r\n ELSE IF (Doubleword comparison)\r\n THEN IF DF = 0\r\n THEN\r\n (R|E)SI <- (R|E)SI + 4;\r\n (R|E)DI <- (R|E)DI + 4;\r\n ELSE\r\n (R|E)SI <- (R|E)SI - 4;\r\n (R|E)DI <- (R|E)DI - 4;\r\n FI;\r\n\r\n\r\n\r\n ELSE (* Quadword comparison *)\r\n THEN IF DF = 0\r\n (R|E)SI <- (R|E)SI + 8;\r\n (R|E)DI <- (R|E)DI + 8;\r\n ELSE\r\n (R|E)SI <- (R|E)SI - 8;\r\n (R|E)DI <- (R|E)DI - 8;\r\n FI;\r\n FI;\r\n ELSE (* Non-64-bit Mode *)\r\n IF (byte comparison)\r\n THEN IF DF = 0\r\n THEN\r\n (E)SI <- (E)SI + 1;\r\n (E)DI <- (E)DI + 1;\r\n ELSE\r\n (E)SI <- (E)SI - 1;\r\n (E)DI <- (E)DI - 1;\r\n FI;\r\n ELSE IF (Word comparison)\r\n THEN IF DF = 0\r\n (E)SI <- (E)SI + 2;\r\n (E)DI <- (E)DI + 2;\r\n ELSE\r\n (E)SI <- (E)SI - 2;\r\n (E)DI <- (E)DI - 2;\r\n FI;\r\n ELSE (* Doubleword comparison *)\r\n THEN IF DF = 0\r\n (E)SI <- (E)SI + 4;\r\n (E)DI <- (E)DI + 4;\r\n ELSE\r\n (E)SI <- (E)SI - 4;\r\n (E)DI <- (E)DI - 4;\r\n FI;\r\n FI;\r\nFI;\r\n\r\nFlags Affected\r\nThe CF, OF, SF, ZF, AF, and PF flags are set according to the temporary result of the comparison.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CMPS"
},
{
"description": "-R:CMPS",
"mnem": "CMPSB"
},
{
"description": "-R:CMPS",
"mnem": "CMPSD"
},
{
"description": "CMPSD-Compare Scalar Double-Precision Floating-Point Value\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n F2 0F C2 /r ib RMI V/V SSE2 Compare low double-precision floating-point value in\r\n CMPSD xmm1, xmm2/m64, imm8 xmm2/m64 and xmm1 using bits 2:0 of imm8 as comparison\r\n predicate.\r\n VEX.NDS.128.F2.0F.WIG C2 /r ib RVMI V/V AVX Compare low double-precision floating-point value in\r\n VCMPSD xmm1, xmm2, xmm3/m64 and xmm2 using bits 4:0 of imm8 as comparison\r\n xmm3/m64, imm8 predicate.\r\n EVEX.NDS.LIG.F2.0F.W1 C2 /r ib T1S V/V AVX512F Compare low double-precision floating-point value in\r\n VCMPSD k1 {k2}, xmm2, xmm3/m64 and xmm2 using bits 4:0 of imm8 as comparison\r\n xmm3/m64{sae}, imm8 predicate with writemask k2 and leave the result in mask\r\n register k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (r, w) ModRM:r/m (r) Imm8 NA\r\n RVMI ModRM:reg (w) VEX.vvvv ModRM:r/m (r) Imm8\r\n T1S ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) Imm8\r\n\r\nDescription\r\nCompares the low double-precision floating-point values in the second source operand and the first source operand\r\nand returns the results in of the comparison to the destination operand. The comparison predicate operand (imme-\r\ndiate operand) specifies the type of comparison performed.\r\n128-bit Legacy SSE version: The first source and destination operand (first operand) is an XMM register. The\r\nsecond source operand (second operand) can be an XMM register or 64-bit memory location. Bits (MAX_VL-1:64)\r\nof the corresponding YMM destination register remain unchanged. The comparison result is a quadword mask of all\r\n1s (comparison true) or all 0s (comparison false).\r\nVEX.128 encoded version: The first source operand (second operand) is an XMM register. The second source\r\noperand (third operand) can be an XMM register or a 64-bit memory location. The result is stored in the low quad-\r\nword of the destination operand; the high quadword is filled with the contents of the high quadword of the first\r\nsource operand. Bits (MAX_VL-1:128) of the destination ZMM register are zeroed. The comparison result is a quad-\r\nword mask of all 1s (comparison true) or all 0s (comparison false).\r\nEVEX encoded version: The first source operand (second operand) is an XMM register. The second source operand\r\ncan be a XMM register or a 64-bit memory location. The destination operand (first operand) is an opmask register.\r\nThe comparison result is a single mask bit of 1 (comparison true) or 0 (comparison false), written to the destination\r\nstarting from the LSB according to the writemask k2. Bits (MAX_KL-1:128) of the destination register are cleared.\r\nThe comparison predicate operand is an 8-bit immediate:\r\n. For instructions encoded using the VEX prefix, bits 4:0 define the type of comparison to be performed (see\r\n Table 3-1). Bits 5 through 7 of the immediate are reserved.\r\n. For instruction encodings that do not use VEX prefix, bits 2:0 define the type of comparison to be made (see\r\n the first 8 rows of Table 3-1). Bits 3 through 7 of the immediate are reserved.\r\nThe unordered relationship is true when at least one of the two source operands being compared is a NaN; the\r\nordered relationship is true when neither source operand is a NaN.\r\nA subsequent computational instruction that uses the mask result in the destination operand as an input operand\r\nwill not generate an exception, because a mask of all 0s corresponds to a floating-point value of +0.0 and a mask\r\nof all 1s corresponds to a QNaN.\r\nNote that processors with \"CPUID.1H:ECX.AVX =0\" do not implement the \"greater-than\", \"greater-than-or-equal\",\r\n\"not-greater than\", and \"not-greater-than-or-equal relations\" predicates. These comparisons can be made either\r\nby using the inverse relationship (that is, use the \"not-less-than-or-equal\" to make a \"greater-than\" comparison)\r\n\r\n\r\n\r\nor by using software emulation. When using software emulation, the program must swap the operands (copying\r\nregisters when necessary to protect the data that will now be in the destination), and then perform the compare\r\nusing a different predicate. The predicate to be used for these emulations is listed in the first 8 rows of Table 3-7\r\n(Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A) under the heading Emulation.\r\nCompilers and assemblers may implement the following two-operand pseudo-ops in addition to the three-operand\r\nCMPSD instruction, for processors with \"CPUID.1H:ECX.AVX =0\". See Table 3-6. Compiler should treat reserved\r\nImm8 values as illegal syntax.\r\n Table 3-6. Pseudo-Op and CMPSD Implementation\r\n:\r\n\r\n\r\n\r\n\r\n Pseudo-Op CMPSD Implementation\r\n CMPEQSD xmm1, xmm2 CMPSD xmm1, xmm2, 0\r\n CMPLTSD xmm1, xmm2 CMPSD xmm1, xmm2, 1\r\n CMPLESD xmm1, xmm2 CMPSD xmm1, xmm2, 2\r\n CMPUNORDSD xmm1, xmm2 CMPSD xmm1, xmm2, 3\r\n CMPNEQSD xmm1, xmm2 CMPSD xmm1, xmm2, 4\r\n CMPNLTSD xmm1, xmm2 CMPSD xmm1, xmm2, 5\r\n CMPNLESD xmm1, xmm2 CMPSD xmm1, xmm2, 6\r\n CMPORDSD xmm1, xmm2 CMPSD xmm1, xmm2, 7\r\n\r\nThe greater-than relations that the processor does not implement require more than one instruction to emulate in\r\nsoftware and therefore should not be implemented as pseudo-ops. (For these, the programmer should reverse the\r\noperands of the corresponding less than relations and use move instructions to ensure that the mask is moved to\r\nthe correct destination register and that the source operand is left intact.)\r\nProcessors with \"CPUID.1H:ECX.AVX =1\" implement the full complement of 32 predicates shown in Table 3-7, soft-\r\nware emulation is no longer needed. Compilers and assemblers may implement the following three-operand\r\npseudo-ops in addition to the four-operand VCMPSD instruction. See Table 3-7, where the notations of reg1 reg2,\r\nand reg3 represent either XMM registers or YMM registers. Compiler should treat reserved Imm8 values as illegal\r\nsyntax. Alternately, intrinsics can map the pseudo-ops to pre-defined constants to support a simpler intrinsic inter-\r\nface. Compilers and assemblers may implement three-operand pseudo-ops for EVEX encoded VCMPSD instructions\r\nin a similar fashion by extending the syntax listed in Table 3-7.\r\n Table 3-7. Pseudo-Op and VCMPSD Implementation\r\n:\r\n\r\n\r\n\r\n\r\n Pseudo-Op CMPSD Implementation\r\n VCMPEQSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 0\r\n VCMPLTSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 1\r\n VCMPLESD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 2\r\n VCMPUNORDSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 3\r\n VCMPNEQSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 4\r\n VCMPNLTSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 5\r\n VCMPNLESD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 6\r\n VCMPORDSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 7\r\n VCMPEQ_UQSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 8\r\n VCMPNGESD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 9\r\n VCMPNGTSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 0AH\r\n VCMPFALSESD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 0BH\r\n VCMPNEQ_OQSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 0CH\r\n VCMPGESD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 0DH\r\n\r\n\r\n\r\n\r\n Table 3-7. Pseudo-Op and VCMPSD Implementation\r\n Pseudo-Op CMPSD Implementation\r\n VCMPGTSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 0EH\r\n VCMPTRUESD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 0FH\r\n VCMPEQ_OSSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 10H\r\n VCMPLT_OQSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 11H\r\n VCMPLE_OQSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 12H\r\n VCMPUNORD_SSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 13H\r\n VCMPNEQ_USSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 14H\r\n VCMPNLT_UQSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 15H\r\n VCMPNLE_UQSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 16H\r\n VCMPORD_SSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 17H\r\n VCMPEQ_USSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 18H\r\n VCMPNGE_UQSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 19H\r\n VCMPNGT_UQSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 1AH\r\n VCMPFALSE_OSSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 1BH\r\n VCMPNEQ_OSSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 1CH\r\n VCMPGE_OQSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 1DH\r\n VCMPGT_OQSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 1EH\r\n VCMPTRUE_USSD reg1, reg2, reg3 VCMPSD reg1, reg2, reg3, 1FH\r\n\r\nSoftware should ensure VCMPSD is encoded with VEX.L=0. Encoding VCMPSD with VEX.L=1 may encounter unpre-\r\ndictable behavior across different processor generations.\r\n\r\nOperation\r\nCASE (COMPARISON PREDICATE) OF\r\n 0: OP3 <-EQ_OQ; OP5 <-EQ_OQ;\r\n 1: OP3 <-LT_OS; OP5 <-LT_OS;\r\n 2: OP3 <-LE_OS; OP5 <-LE_OS;\r\n 3: OP3 <-UNORD_Q; OP5 <-UNORD_Q;\r\n 4: OP3 <-NEQ_UQ; OP5 <-NEQ_UQ;\r\n 5: OP3 <-NLT_US; OP5 <-NLT_US;\r\n 6: OP3 <-NLE_US; OP5 <-NLE_US;\r\n 7: OP3 <-ORD_Q; OP5 <-ORD_Q;\r\n 8: OP5 <-EQ_UQ;\r\n 9: OP5 <-NGE_US;\r\n 10: OP5 <-NGT_US;\r\n 11: OP5 <-FALSE_OQ;\r\n 12: OP5 <-NEQ_OQ;\r\n 13: OP5 <-GE_OS;\r\n 14: OP5 <-GT_OS;\r\n 15: OP5 <-TRUE_UQ;\r\n 16: OP5 <-EQ_OS;\r\n 17: OP5 <-LT_OQ;\r\n 18: OP5 <-LE_OQ;\r\n 19: OP5 <-UNORD_S;\r\n 20: OP5 <-NEQ_US;\r\n 21: OP5 <-NLT_UQ;\r\n\r\n\r\n\r\n 22: OP5 <-NLE_UQ;\r\n 23: OP5 <-ORD_S;\r\n 24: OP5 <-EQ_US;\r\n 25: OP5 <-NGE_UQ;\r\n 26: OP5 <-NGT_UQ;\r\n 27: OP5 <-FALSE_OS;\r\n 28: OP5 <-NEQ_OS;\r\n 29: OP5 <-GE_OQ;\r\n 30: OP5 <-GT_OQ;\r\n 31: OP5 <-TRUE_US;\r\n DEFAULT: Reserved\r\nESAC;\r\n\r\nVCMPSD (EVEX encoded version)\r\nCMP0 <- SRC1[63:0] OP5 SRC2[63:0];\r\n\r\nIF k2[0] or *no writemask*\r\n THEN IF CMP0 = TRUE\r\n THEN DEST[0] <- 1;\r\n ELSE DEST[0] <- 0; FI;\r\n ELSE DEST[0] <- 0 ; zeroing-masking only\r\nFI;\r\nDEST[MAX_KL-1:1] <- 0\r\n\r\nCMPSD (128-bit Legacy SSE version)\r\nCMP0 <-DEST[63:0] OP3 SRC[63:0];\r\nIF CMP0 = TRUE\r\nTHEN DEST[63:0] <-FFFFFFFFFFFFFFFFH;\r\nELSE DEST[63:0] <-0000000000000000H; FI;\r\nDEST[MAX_VL-1:64] (Unmodified)\r\n\r\nVCMPSD (VEX.128 encoded version)\r\nCMP0 <-SRC1[63:0] OP5 SRC2[63:0];\r\nIF CMP0 = TRUE\r\nTHEN DEST[63:0] <-FFFFFFFFFFFFFFFFH;\r\nELSE DEST[63:0] <-0000000000000000H; FI;\r\nDEST[127:64] <-SRC1[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCMPSD __mmask8 _mm_cmp_sd_mask( __m128d a, __m128d b, int imm);\r\nVCMPSD __mmask8 _mm_cmp_round_sd_mask( __m128d a, __m128d b, int imm, int sae);\r\nVCMPSD __mmask8 _mm_mask_cmp_sd_mask( __mmask8 k1, __m128d a, __m128d b, int imm);\r\nVCMPSD __mmask8 _mm_mask_cmp_round_sd_mask( __mmask8 k1, __m128d a, __m128d b, int imm, int sae);\r\n(V)CMPSD __m128d _mm_cmp_sd(__m128d a, __m128d b, const int imm)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid if SNaN operand, Invalid if QNaN and predicate as listed in Table 3-1 Denormal.\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3.\r\nEVEX-encoded instructions, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CMPSD"
},
{
"description": "-R:CMPS",
"mnem": "CMPSQ"
},
{
"description": "CMPSS-Compare Scalar Single-Precision Floating-Point Value\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n F3 0F C2 /r ib RMI V/V SSE Compare low single-precision floating-point value in\r\n CMPSS xmm1, xmm2/m32, imm8 xmm2/m32 and xmm1 using bits 2:0 of imm8 as\r\n comparison predicate.\r\n VEX.NDS.128.F3.0F.WIG C2 /r ib RVMI V/V AVX Compare low single-precision floating-point value in\r\n VCMPSS xmm1, xmm2, xmm3/m32, xmm3/m32 and xmm2 using bits 4:0 of imm8 as\r\n imm8 comparison predicate.\r\n EVEX.NDS.LIG.F3.0F.W0 C2 /r ib T1S V/V AVX512F Compare low single-precision floating-point value in\r\n VCMPSS k1 {k2}, xmm2, xmm3/m32 and xmm2 using bits 4:0 of imm8 as\r\n xmm3/m32{sae}, imm8 comparison predicate with writemask k2 and leave the\r\n result in mask register k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (r, w) ModRM:r/m (r) Imm8 NA\r\n RVMI ModRM:reg (w) VEX.vvvv ModRM:r/m (r) Imm8\r\n T1S ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) Imm8\r\n\r\nDescription\r\nCompares the low single-precision floating-point values in the second source operand and the first source operand\r\nand returns the results of the comparison to the destination operand. The comparison predicate operand (imme-\r\ndiate operand) specifies the type of comparison performed.\r\n128-bit Legacy SSE version: The first source and destination operand (first operand) is an XMM register. The\r\nsecond source operand (second operand) can be an XMM register or 32-bit memory location. Bits (MAX_VL-1:32)\r\nof the corresponding YMM destination register remain unchanged. The comparison result is a doubleword mask of\r\nall 1s (comparison true) or all 0s (comparison false).\r\nVEX.128 encoded version: The first source operand (second operand) is an XMM register. The second source\r\noperand (third operand) can be an XMM register or a 32-bit memory location. The result is stored in the low 32 bits\r\nof the destination operand; bits 128:32 of the destination operand are copied from the first source operand. Bits\r\n(MAX_VL-1:128) of the destination ZMM register are zeroed. The comparison result is a doubleword mask of all 1s\r\n(comparison true) or all 0s (comparison false).\r\nEVEX encoded version: The first source operand (second operand) is an XMM register. The second source operand\r\ncan be a XMM register or a 32-bit memory location. The destination operand (first operand) is an opmask register.\r\nThe comparison result is a single mask bit of 1 (comparison true) or 0 (comparison false), written to the destination\r\nstarting from the LSB according to the writemask k2. Bits (MAX_KL-1:128) of the destination register are cleared.\r\nThe comparison predicate operand is an 8-bit immediate:\r\n. For instructions encoded using the VEX prefix, bits 4:0 define the type of comparison to be performed (see\r\n Table 3-1). Bits 5 through 7 of the immediate are reserved.\r\n. For instruction encodings that do not use VEX prefix, bits 2:0 define the type of comparison to be made (see\r\n the first 8 rows of Table 3-1). Bits 3 through 7 of the immediate are reserved.\r\n\r\n\r\nThe unordered relationship is true when at least one of the two source operands being compared is a NaN; the\r\nordered relationship is true when neither source operand is a NaN.\r\nA subsequent computational instruction that uses the mask result in the destination operand as an input operand\r\nwill not generate an exception, because a mask of all 0s corresponds to a floating-point value of +0.0 and a mask\r\nof all 1s corresponds to a QNaN.\r\nNote that processors with \"CPUID.1H:ECX.AVX =0\" do not implement the \"greater-than\", \"greater-than-or-equal\",\r\n\"not-greater than\", and \"not-greater-than-or-equal relations\" predicates. These comparisons can be made either\r\n\r\n\r\n\r\nby using the inverse relationship (that is, use the \"not-less-than-or-equal\" to make a \"greater-than\" comparison)\r\nor by using software emulation. When using software emulation, the program must swap the operands (copying\r\nregisters when necessary to protect the data that will now be in the destination), and then perform the compare\r\nusing a different predicate. The predicate to be used for these emulations is listed in the first 8 rows of Table 3-7\r\n(Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A) under the heading Emulation.\r\nCompilers and assemblers may implement the following two-operand pseudo-ops in addition to the three-operand\r\nCMPSS instruction, for processors with \"CPUID.1H:ECX.AVX =0\". See Table 3-8. Compiler should treat reserved\r\nImm8 values as illegal syntax.\r\n Table 3-8. Pseudo-Op and CMPSS Implementation\r\n:\r\n\r\n\r\n\r\n\r\n Pseudo-Op CMPSS Implementation\r\n CMPEQSS xmm1, xmm2 CMPSS xmm1, xmm2, 0\r\n CMPLTSS xmm1, xmm2 CMPSS xmm1, xmm2, 1\r\n CMPLESS xmm1, xmm2 CMPSS xmm1, xmm2, 2\r\n CMPUNORDSS xmm1, xmm2 CMPSS xmm1, xmm2, 3\r\n CMPNEQSS xmm1, xmm2 CMPSS xmm1, xmm2, 4\r\n CMPNLTSS xmm1, xmm2 CMPSS xmm1, xmm2, 5\r\n CMPNLESS xmm1, xmm2 CMPSS xmm1, xmm2, 6\r\n CMPORDSS xmm1, xmm2 CMPSS xmm1, xmm2, 7\r\n\r\nThe greater-than relations that the processor does not implement require more than one instruction to emulate in\r\nsoftware and therefore should not be implemented as pseudo-ops. (For these, the programmer should reverse the\r\noperands of the corresponding less than relations and use move instructions to ensure that the mask is moved to\r\nthe correct destination register and that the source operand is left intact.)\r\nProcessors with \"CPUID.1H:ECX.AVX =1\" implement the full complement of 32 predicates shown in Table 3-7, soft-\r\nware emulation is no longer needed. Compilers and assemblers may implement the following three-operand\r\npseudo-ops in addition to the four-operand VCMPSS instruction. See Table 3-9, where the notations of reg1 reg2,\r\nand reg3 represent either XMM registers or YMM registers. Compiler should treat reserved Imm8 values as illegal\r\nsyntax. Alternately, intrinsics can map the pseudo-ops to pre-defined constants to support a simpler intrinsic inter-\r\nface. Compilers and assemblers may implement three-operand pseudo-ops for EVEX encoded VCMPSS instructions\r\nin a similar fashion by extending the syntax listed in Table 3-9.\r\n Table 3-9. Pseudo-Op and VCMPSS Implementation\r\n:\r\n\r\n\r\n\r\n\r\n Pseudo-Op CMPSS Implementation\r\n VCMPEQSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 0\r\n VCMPLTSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 1\r\n VCMPLESS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 2\r\n VCMPUNORDSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 3\r\n VCMPNEQSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 4\r\n VCMPNLTSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 5\r\n VCMPNLESS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 6\r\n VCMPORDSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 7\r\n VCMPEQ_UQSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 8\r\n VCMPNGESS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 9\r\n VCMPNGTSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 0AH\r\n VCMPFALSESS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 0BH\r\n VCMPNEQ_OQSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 0CH\r\n VCMPGESS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 0DH\r\n\r\n\r\n\r\n Table 3-9. Pseudo-Op and VCMPSS Implementation\r\n Pseudo-Op CMPSS Implementation\r\n VCMPGTSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 0EH\r\n VCMPTRUESS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 0FH\r\n VCMPEQ_OSSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 10H\r\n VCMPLT_OQSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 11H\r\n VCMPLE_OQSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 12H\r\n VCMPUNORD_SSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 13H\r\n VCMPNEQ_USSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 14H\r\n VCMPNLT_UQSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 15H\r\n VCMPNLE_UQSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 16H\r\n VCMPORD_SSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 17H\r\n VCMPEQ_USSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 18H\r\n VCMPNGE_UQSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 19H\r\n VCMPNGT_UQSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 1AH\r\n VCMPFALSE_OSSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 1BH\r\n VCMPNEQ_OSSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 1CH\r\n VCMPGE_OQSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 1DH\r\n VCMPGT_OQSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 1EH\r\n VCMPTRUE_USSS reg1, reg2, reg3 VCMPSS reg1, reg2, reg3, 1FH\r\n\r\nSoftware should ensure VCMPSS is encoded with VEX.L=0. Encoding VCMPSS with VEX.L=1 may encounter unpre-\r\ndictable behavior across different processor generations.\r\n\r\nOperation\r\nCASE (COMPARISON PREDICATE) OF\r\n 0: OP3 <-EQ_OQ; OP5 <-EQ_OQ;\r\n 1: OP3 <-LT_OS; OP5 <-LT_OS;\r\n 2: OP3 <-LE_OS; OP5 <-LE_OS;\r\n 3: OP3 <-UNORD_Q; OP5 <-UNORD_Q;\r\n 4: OP3 <-NEQ_UQ; OP5 <-NEQ_UQ;\r\n 5: OP3 <-NLT_US; OP5 <-NLT_US;\r\n 6: OP3 <-NLE_US; OP5 <-NLE_US;\r\n 7: OP3 <-ORD_Q; OP5 <-ORD_Q;\r\n 8: OP5 <-EQ_UQ;\r\n 9: OP5 <-NGE_US;\r\n 10: OP5 <-NGT_US;\r\n 11: OP5 <-FALSE_OQ;\r\n 12: OP5 <-NEQ_OQ;\r\n 13: OP5 <-GE_OS;\r\n 14: OP5 <-GT_OS;\r\n 15: OP5 <-TRUE_UQ;\r\n 16: OP5 <-EQ_OS;\r\n 17: OP5 <-LT_OQ;\r\n 18: OP5 <-LE_OQ;\r\n 19: OP5 <-UNORD_S;\r\n 20: OP5 <-NEQ_US;\r\n 21: OP5 <-NLT_UQ;\r\n\r\n\r\n\r\n 22: OP5 <-NLE_UQ;\r\n 23: OP5 <-ORD_S;\r\n 24: OP5 <-EQ_US;\r\n 25: OP5 <-NGE_UQ;\r\n 26: OP5 <-NGT_UQ;\r\n 27: OP5 <-FALSE_OS;\r\n 28: OP5 <-NEQ_OS;\r\n 29: OP5 <-GE_OQ;\r\n 30: OP5 <-GT_OQ;\r\n 31: OP5 <-TRUE_US;\r\n DEFAULT: Reserved\r\nESAC;\r\n\r\nVCMPSS (EVEX encoded version)\r\nCMP0 <- SRC1[31:0] OP5 SRC2[31:0];\r\n\r\nIF k2[0] or *no writemask*\r\n THEN IF CMP0 = TRUE\r\n THEN DEST[0] <- 1;\r\n ELSE DEST[0] <- 0; FI;\r\n ELSE DEST[0] <- 0 ; zeroing-masking only\r\nFI;\r\nDEST[MAX_KL-1:1] <- 0\r\n\r\nCMPSS (128-bit Legacy SSE version)\r\nCMP0 <-DEST[31:0] OP3 SRC[31:0];\r\nIF CMP0 = TRUE\r\nTHEN DEST[31:0] <-FFFFFFFFH;\r\nELSE DEST[31:0] <-00000000H; FI;\r\nDEST[MAX_VL-1:32] (Unmodified)\r\n\r\nVCMPSS (VEX.128 encoded version)\r\nCMP0 <-SRC1[31:0] OP5 SRC2[31:0];\r\nIF CMP0 = TRUE\r\nTHEN DEST[31:0] <-FFFFFFFFH;\r\nELSE DEST[31:0] <-00000000H; FI;\r\nDEST[127:32] <-SRC1[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCMPSS __mmask8 _mm_cmp_ss_mask( __m128 a, __m128 b, int imm);\r\nVCMPSS __mmask8 _mm_cmp_round_ss_mask( __m128 a, __m128 b, int imm, int sae);\r\nVCMPSS __mmask8 _mm_mask_cmp_ss_mask( __mmask8 k1, __m128 a, __m128 b, int imm);\r\nVCMPSS __mmask8 _mm_mask_cmp_round_ss_mask( __mmask8 k1, __m128 a, __m128 b, int imm, int sae);\r\n(V)CMPSS __m128 _mm_cmp_ss(__m128 a, __m128 b, const int imm)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid if SNaN operand, Invalid if QNaN and predicate as listed in Table 3-1, Denormal.\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3.\r\nEVEX-encoded instructions, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CMPSS"
},
{
"description": "-R:CMPS",
"mnem": "CMPSW"
},
{
"description": "CMPXCHG-Compare and Exchange\r\nOpcode/ Op/ 64-Bit Compat/ Description\r\nInstruction En Mode Leg Mode\r\n0F B0/r MR Valid Valid* Compare AL with r/m8. If equal, ZF is set and r8 is loaded into\r\nCMPXCHG r/m8, r8 r/m8. Else, clear ZF and load r/m8 into AL.\r\n\r\nREX + 0F B0/r MR Valid N.E. Compare AL with r/m8. If equal, ZF is set and r8 is loaded into\r\nCMPXCHG r/m8**,r8 r/m8. Else, clear ZF and load r/m8 into AL.\r\n\r\n0F B1/r MR Valid Valid* Compare AX with r/m16. If equal, ZF is set and r16 is loaded\r\nCMPXCHG r/m16, r16 into r/m16. Else, clear ZF and load r/m16 into AX.\r\n0F B1/r MR Valid Valid* Compare EAX with r/m32. If equal, ZF is set and r32 is loaded\r\nCMPXCHG r/m32, r32 into r/m32. Else, clear ZF and load r/m32 into EAX.\r\n\r\nREX.W + 0F B1/r MR Valid N.E. Compare RAX with r/m64. If equal, ZF is set and r64 is loaded\r\nCMPXCHG r/m64, r64 into r/m64. Else, clear ZF and load r/m64 into RAX.\r\n\r\nNOTES:\r\n* See the IA-32 Architecture Compatibility section below.\r\n** In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n MR ModRM:r/m (r, w) ModRM:reg (r) NA NA\r\n\r\nDescription\r\nCompares the value in the AL, AX, EAX, or RAX register with the first operand (destination operand). If the two\r\nvalues are equal, the second operand (source operand) is loaded into the destination operand. Otherwise, the\r\ndestination operand is loaded into the AL, AX, EAX or RAX register. RAX register is available only in 64-bit mode.\r\nThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically. To simplify the\r\ninterface to the processor's bus, the destination operand receives a write cycle without regard to the result of the\r\ncomparison. The destination operand is written back if the comparison fails; otherwise, the source operand is\r\nwritten into the destination. (The processor never produces a locked read without also producing a locked write.)\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-\r\ntional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the\r\nbeginning of this section for encoding data and limits.\r\n\r\nIA-32 Architecture Compatibility\r\nThis instruction is not supported on Intel processors earlier than the Intel486 processors.\r\n\r\nOperation\r\n(* Accumulator = AL, AX, EAX, or RAX depending on whether a byte, word, doubleword, or quadword comparison is being performed *)\r\nTEMP <- DEST\r\nIF accumulator = TEMP\r\n THEN\r\n ZF <- 1;\r\n DEST <- SRC;\r\n ELSE\r\n ZF <- 0;\r\n accumulator <- TEMP;\r\n DEST <- TEMP;\r\nFI;\r\n\r\n\r\n\r\nFlags Affected\r\nThe ZF flag is set if the values in the destination operand and register AL, AX, or EAX are equal; otherwise it is\r\ncleared. The CF, PF, AF, SF, and OF flags are set according to the results of the comparison operation.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination is located in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CMPXCHG"
},
{
"description": "-R:CMPXCHG8B",
"mnem": "CMPXCHG16B"
},
{
"description": "CMPXCHG8B/CMPXCHG16B-Compare and Exchange Bytes\r\nOpcode/ Op/ 64-Bit Compat/ Description\r\nInstruction En Mode Leg Mode\r\n0F C7 /1 m64 M Valid Valid* Compare EDX:EAX with m64. If equal, set ZF and load\r\nCMPXCHG8B m64 ECX:EBX into m64. Else, clear ZF and load m64 into EDX:EAX.\r\n\r\nREX.W + 0F C7 /1 m128 M Valid N.E. Compare RDX:RAX with m128. If equal, set ZF and load\r\nCMPXCHG16B m128 RCX:RBX into m128. Else, clear ZF and load m128 into\r\n RDX:RAX.\r\nNOTES:\r\n*See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (r, w) NA NA NA\r\n\r\nDescription\r\nCompares the 64-bit value in EDX:EAX (or 128-bit value in RDX:RAX if operand size is 128 bits) with the operand\r\n(destination operand). If the values are equal, the 64-bit value in ECX:EBX (or 128-bit value in RCX:RBX) is stored\r\nin the destination operand. Otherwise, the value in the destination operand is loaded into EDX:EAX (or RDX:RAX).\r\nThe destination operand is an 8-byte memory location (or 16-byte memory location if operand size is 128 bits). For\r\nthe EDX:EAX and ECX:EBX register pairs, EDX and ECX contain the high-order 32 bits and EAX and EBX contain the\r\nlow-order 32 bits of a 64-bit value. For the RDX:RAX and RCX:RBX register pairs, RDX and RCX contain the high-\r\norder 64 bits and RAX and RBX contain the low-order 64bits of a 128-bit value.\r\nThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically. To simplify the\r\ninterface to the processor's bus, the destination operand receives a write cycle without regard to the result of the\r\ncomparison. The destination operand is written back if the comparison fails; otherwise, the source operand is\r\nwritten into the destination. (The processor never produces a locked read without also producing a locked write.)\r\nIn 64-bit mode, default operation size is 64 bits. Use of the REX.W prefix promotes operation to 128 bits. Note that\r\nCMPXCHG16B requires that the destination (memory) operand be 16-byte aligned. See the summary chart at the\r\nbeginning of this section for encoding data and limits. For information on the CPUID flag that indicates\r\nCMPXCHG16B, see page 3-206.\r\n\r\nIA-32 Architecture Compatibility\r\nThis instruction encoding is not supported on Intel processors earlier than the Pentium processors.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIF (64-Bit Mode and OperandSize = 64)\r\n THEN\r\n TEMP128 <- DEST\r\n IF (RDX:RAX = TEMP128)\r\n THEN\r\n ZF <- 1;\r\n DEST <- RCX:RBX;\r\n ELSE\r\n ZF <- 0;\r\n RDX:RAX <- TEMP128;\r\n DEST <- TEMP128;\r\n FI;\r\n FI\r\n ELSE\r\n TEMP64 <- DEST;\r\n IF (EDX:EAX = TEMP64)\r\n THEN\r\n ZF <- 1;\r\n DEST <- ECX:EBX;\r\n ELSE\r\n ZF <- 0;\r\n EDX:EAX <- TEMP64;\r\n DEST <- TEMP64;\r\n FI;\r\n FI;\r\nFI;\r\n\r\nFlags Affected\r\nThe ZF flag is set if the destination operand and EDX:EAX are equal; otherwise it is cleared. The CF, PF, AF, SF, and\r\nOF flags are unaffected.\r\n\r\nProtected Mode Exceptions\r\n#UD If the destination is not a memory operand.\r\n#GP(0) If the destination is located in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n\r\nReal-Address Mode Exceptions\r\n#UD If the destination operand is not a memory location.\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD If the destination operand is not a memory location.\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n If memory operand for CMPXCHG16B is not aligned on a 16-byte boundary.\r\n If CPUID.01H:ECX.CMPXCHG16B[bit 13] = 0.\r\n#UD If the destination operand is not a memory location.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CMPXCHG8B"
},
{
"description": "COMISD-Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0F 2F /r RM V/V SSE2 Compare low double-precision floating-point values in\r\n COMISD xmm1, xmm2/m64 xmm1 and xmm2/mem64 and set the EFLAGS flags\r\n accordingly.\r\n VEX.128.66.0F.WIG 2F /r RM V/V AVX Compare low double-precision floating-point values in\r\n VCOMISD xmm1, xmm2/m64 xmm1 and xmm2/mem64 and set the EFLAGS flags\r\n accordingly.\r\n EVEX.LIG.66.0F.W1 2F /r T1S V/V AVX512F Compare low double-precision floating-point values in\r\n VCOMISD xmm1, xmm2/m64{sae} xmm1 and xmm2/mem64 and set the EFLAGS flags\r\n accordingly.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n T1S ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nCompares the double-precision floating-point values in the low quadwords of operand 1 (first operand) and\r\noperand 2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unor-\r\ndered, greater than, less than, or equal). The OF, SF and AF flags in the EFLAGS register are set to 0. The unor-\r\ndered result is returned if either source operand is a NaN (QNaN or SNaN).\r\nOperand 1 is an XMM register; operand 2 can be an XMM register or a 64 bit memory\r\nlocation. The COMISD instruction differs from the UCOMISD instruction in that it signals a SIMD floating-point\r\ninvalid operation exception (#I) when a source operand is either a QNaN or SNaN. The UCOMISD instruction signals\r\nan invalid numeric exception only if a source operand is an SNaN.\r\nThe EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated.\r\nVEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.\r\nSoftware should ensure VCOMISD is encoded with VEX.L=0. Encoding VCOMISD with VEX.L=1 may encounter\r\nunpredictable behavior across different processor generations.\r\n\r\nOperation\r\nCOMISD (all versions)\r\nRESULT <- OrderedCompare(DEST[63:0] <> SRC[63:0]) {\r\n(* Set EFLAGS *) CASE (RESULT) OF\r\n UNORDERED: ZF,PF,CF <- 111;\r\n GREATER_THAN: ZF,PF,CF <- 000;\r\n LESS_THAN: ZF,PF,CF <- 001;\r\n EQUAL: ZF,PF,CF <- 100;\r\nESAC;\r\nOF, AF, SF <-0; }\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCOMISD int _mm_comi_round_sd(__m128d a, __m128d b, int imm, int sae);\r\nVCOMISD int _mm_comieq_sd (__m128d a, __m128d b)\r\nVCOMISD int _mm_comilt_sd (__m128d a, __m128d b)\r\nVCOMISD int _mm_comile_sd (__m128d a, __m128d b)\r\nVCOMISD int _mm_comigt_sd (__m128d a, __m128d b)\r\nVCOMISD int _mm_comige_sd (__m128d a, __m128d b)\r\nVCOMISD int _mm_comineq_sd (__m128d a, __m128d b)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid (if SNaN or QNaN operands), Denormal.\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3;\r\nEVEX-encoded instructions, see Exceptions Type E3NF.\r\n#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "COMISD"
},
{
"description": "COMISS-Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 0F 2F /r RM V/V SSE Compare low single-precision floating-point values in\r\n COMISS xmm1, xmm2/m32 xmm1 and xmm2/mem32 and set the EFLAGS flags\r\n accordingly.\r\n VEX.128.0F.WIG 2F /r RM V/V AVX Compare low single-precision floating-point values in\r\n VCOMISS xmm1, xmm2/m32 xmm1 and xmm2/mem32 and set the EFLAGS flags\r\n accordingly.\r\n EVEX.LIG.0F.W0 2F /r T1S V/V AVX512F Compare low single-precision floating-point values in\r\n VCOMISS xmm1, xmm2/m32{sae} xmm1 and xmm2/mem32 and set the EFLAGS flags\r\n accordingly.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n T1S ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nCompares the single-precision floating-point values in the low quadwords of operand 1 (first operand) and operand\r\n2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unordered,\r\ngreater than, less than, or equal). The OF, SF and AF flags in the EFLAGS register are set to 0. The unordered result\r\nis returned if either source operand is a NaN (QNaN or SNaN).\r\nOperand 1 is an XMM register; operand 2 can be an XMM register or a 32 bit memory location.\r\nThe COMISS instruction differs from the UCOMISS instruction in that it signals a SIMD floating-point invalid opera-\r\ntion exception (#I) when a source operand is either a QNaN or SNaN. The UCOMISS instruction signals an invalid\r\nnumeric exception only if a source operand is an SNaN.\r\nThe EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated.\r\nVEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.\r\nSoftware should ensure VCOMISS is encoded with VEX.L=0. Encoding VCOMISS with VEX.L=1 may encounter\r\nunpredictable behavior across different processor generations.\r\n\r\nOperation\r\nCOMISS (all versions)\r\nRESULT <- OrderedCompare(DEST[31:0] <> SRC[31:0]) {\r\n(* Set EFLAGS *) CASE (RESULT) OF\r\n UNORDERED: ZF,PF,CF <- 111;\r\n GREATER_THAN: ZF,PF,CF <- 000;\r\n LESS_THAN: ZF,PF,CF <- 001;\r\n EQUAL: ZF,PF,CF <- 100;\r\nESAC;\r\nOF, AF, SF <- 0; }\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCOMISS int _mm_comi_round_ss(__m128 a, __m128 b, int imm, int sae);\r\nVCOMISS int _mm_comieq_ss (__m128 a, __m128 b)\r\nVCOMISS int _mm_comilt_ss (__m128 a, __m128 b)\r\nVCOMISS int _mm_comile_ss (__m128 a, __m128 b)\r\nVCOMISS int _mm_comigt_ss (__m128 a, __m128 b)\r\nVCOMISS int _mm_comige_ss (__m128 a, __m128 b)\r\nVCOMISS int _mm_comineq_ss (__m128 a, __m128 b)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid (if SNaN or QNaN operands), Denormal.\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3;\r\nEVEX-encoded instructions, see Exceptions Type E3NF.\r\n#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "COMISS"
},
{
"description": "CPUID-CPU Identification\r\nOpcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n0F A2 CPUID NP Valid Valid Returns processor identification and feature\r\n information to the EAX, EBX, ECX, and EDX\r\n registers, as determined by input entered in\r\n EAX (in some cases, ECX as well).\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nThe ID flag (bit 21) in the EFLAGS register indicates support for the CPUID instruction. If a software procedure can\r\nset and clear this flag, the processor executing the procedure supports the CPUID instruction. This instruction oper-\r\nates the same in non-64-bit modes and 64-bit mode.\r\nCPUID returns processor identification and feature information in the EAX, EBX, ECX, and EDX registers.1 The\r\ninstruction's output is dependent on the contents of the EAX register upon execution (in some cases, ECX as well).\r\nFor example, the following pseudocode loads EAX with 00H and causes CPUID to return a Maximum Return Value\r\nand the Vendor Identification String in the appropriate registers:\r\n\r\n MOV EAX, 00H\r\n CPUID\r\nTable 3-8 shows information returned, depending on the initial value loaded into the EAX register.\r\nTwo types of information are returned: basic and extended function information. If a value entered for CPUID.EAX\r\nis higher than the maximum input value for basic or extended function for that processor then the data for the\r\nhighest basic information leaf is returned. For example, using the Intel Core i7 processor, the following is true:\r\n CPUID.EAX = 05H (* Returns MONITOR/MWAIT leaf. *)\r\n CPUID.EAX = 0AH (* Returns Architectural Performance Monitoring leaf. *)\r\n CPUID.EAX = 0BH (* Returns Extended Topology Enumeration leaf. *)\r\n CPUID.EAX = 0CH (* INVALID: Returns the same information as CPUID.EAX = 0BH. *)\r\n CPUID.EAX = 80000008H (* Returns linear/physical address size data. *)\r\n CPUID.EAX = 8000000AH (* INVALID: Returns same information as CPUID.EAX = 0BH. *)\r\nIf a value entered for CPUID.EAX is less than or equal to the maximum input value and the leaf is not supported on\r\nthat processor then 0 is returned in all the registers.\r\nWhen CPUID returns the highest basic leaf information as a result of an invalid input EAX value, any dependence\r\non input ECX value in the basic leaf is honored.\r\nCPUID can be executed at any privilege level to serialize instruction execution. Serializing instruction execution\r\nguarantees that any modifications to flags, registers, and memory for previous instructions are completed before\r\nthe next instruction is fetched and executed.\r\nSee also:\r\n\"Serializing Instructions\" in Chapter 8, \"Multiple-Processor Management,\" in the Intel 64 and IA-32 Architectures\r\nSoftware Developer's Manual, Volume 3A.\r\n\"Caching Translation Information\" in Chapter 4, \"Paging,\" in the Intel 64 and IA-32 Architectures Software Devel-\r\noper's Manual, Volume 3A.\r\n\r\n\r\n\r\n\r\n1. On Intel 64 processors, CPUID clears the high 32 bits of the RAX/RBX/RCX/RDX registers in all modes.\r\n\r\n\r\n\r\n Table 3-8. Information Returned by CPUID Instruction\r\n Initial EAX\r\n Value Information Provided about the Processor\r\n Basic CPUID Information\r\n 0H EAX Maximum Input Value for Basic CPUID Information.\r\n EBX \"Genu\"\r\n ECX \"ntel\"\r\n EDX \"ineI\"\r\n 01H EAX Version Information: Type, Family, Model, and Stepping ID (see Figure 3-6).\r\n EBX Bits 07 - 00: Brand Index.\r\n Bits 15 - 08: CLFLUSH line size (Value * 8 = cache line size in bytes; used also by CLFLUSHOPT).\r\n Bits 23 - 16: Maximum number of addressable IDs for logical processors in this physical package*.\r\n Bits 31 - 24: Initial APIC ID.\r\n ECX Feature Information (see Figure 3-7 and Table 3-10).\r\n EDX Feature Information (see Figure 3-8 and Table 3-11).\r\n NOTES:\r\n * The nearest power-of-2 integer that is not smaller than EBX[23:16] is the number of unique initial APIC\r\n IDs reserved for addressing different logical processors in a physical package. This field is only valid if\r\n CPUID.1.EDX.HTT[bit 28]= 1.\r\n 02H EAX Cache and TLB Information (see Table 3-12).\r\n EBX Cache and TLB Information.\r\n ECX Cache and TLB Information.\r\n EDX Cache and TLB Information.\r\n 03H EAX Reserved.\r\n EBX Reserved.\r\n ECX Bits 00 - 31 of 96 bit processor serial number. (Available in Pentium III processor only; otherwise, the\r\n value in this register is reserved.)\r\n EDX Bits 32 - 63 of 96 bit processor serial number. (Available in Pentium III processor only; otherwise, the\r\n value in this register is reserved.)\r\n NOTES:\r\n Processor serial number (PSN) is not supported in the Pentium 4 processor or later. On all models, use\r\n the PSN flag (returned using CPUID) to check for PSN support before accessing the feature.\r\n CPUID leaves above 2 and below 80000000H are visible only when IA32_MISC_ENABLE[bit 22] has its default value of 0.\r\n Deterministic Cache Parameters Leaf\r\n 04H NOTES:\r\n Leaf 04H output depends on the initial value in ECX.*\r\n See also: \"INPUT EAX = 04H: Returns Deterministic Cache Parameters for Each Level\" on page 214.\r\n\r\n EAX Bits 04 - 00: Cache Type Field.\r\n 0 = Null - No more caches.\r\n 1 = Data Cache.\r\n 2 = Instruction Cache.\r\n 3 = Unified Cache.\r\n 4-31 = Reserved.\r\n\r\n\r\n\r\n\r\n\r\n Table 3-8. Information Returned by CPUID Instruction (Contd.)\r\n Initial EAX\r\n Value Information Provided about the Processor\r\n Bits 07 - 05: Cache Level (starts at 1).\r\n Bit 08: Self Initializing cache level (does not need SW initialization).\r\n Bit 09: Fully Associative cache.\r\n Bits 13 - 10: Reserved.\r\n Bits 25 - 14: Maximum number of addressable IDs for logical processors sharing this cache**, ***.\r\n Bits 31 - 26: Maximum number of addressable IDs for processor cores in the physical\r\n package**, ****, *****.\r\n EBX Bits 11 - 00: L = System Coherency Line Size**.\r\n Bits 21 - 12: P = Physical Line partitions**.\r\n Bits 31 - 22: W = Ways of associativity**.\r\n ECX Bits 31-00: S = Number of Sets**.\r\n EDX Bit 00: Write-Back Invalidate/Invalidate.\r\n 0 = WBINVD/INVD from threads sharing this cache acts upon lower level caches for threads sharing this\r\n cache.\r\n 1 = WBINVD/INVD is not guaranteed to act upon lower level caches of non-originating threads sharing\r\n this cache.\r\n Bit 01: Cache Inclusiveness.\r\n 0 = Cache is not inclusive of lower cache levels.\r\n 1 = Cache is inclusive of lower cache levels.\r\n Bit 02: Complex Cache Indexing.\r\n 0 = Direct mapped cache.\r\n 1 = A complex function is used to index the cache, potentially using all address bits.\r\n Bits 31 - 03: Reserved = 0.\r\n NOTES:\r\n * If ECX contains an invalid sub leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n+1 is invalid if sub-\r\n leaf n returns EAX[4:0] as 0.\r\n ** Add one to the return value to get the result.\r\n ***The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14]) is the number of unique ini-\r\n tial APIC IDs reserved for addressing different logical processors sharing this cache.\r\n **** The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26]) is the number of unique\r\n Core_IDs reserved for addressing different processor cores in a physical package. Core ID is a subset of\r\n bits of the initial APIC ID.\r\n ***** The returned value is constant for valid initial values in ECX. Valid ECX values start from 0.\r\n MONITOR/MWAIT Leaf\r\n 05H EAX Bits 15 - 00: Smallest monitor-line size in bytes (default is processor's monitor granularity).\r\n Bits 31 - 16: Reserved = 0.\r\n EBX Bits 15 - 00: Largest monitor-line size in bytes (default is processor's monitor granularity).\r\n Bits 31 - 16: Reserved = 0.\r\n ECX Bit 00: Enumeration of Monitor-Mwait extensions (beyond EAX and EBX registers) supported.\r\n Bit 01: Supports treating interrupts as break-event for MWAIT, even when interrupts disabled.\r\n Bits 31 - 02: Reserved.\r\n\r\n\r\n\r\n\r\n\r\n Table 3-8. Information Returned by CPUID Instruction (Contd.)\r\n Initial EAX\r\n Value Information Provided about the Processor\r\n EDX Bits 03 - 00: Number of C0* sub C-states supported using MWAIT.\r\n Bits 07 - 04: Number of C1* sub C-states supported using MWAIT.\r\n Bits 11 - 08: Number of C2* sub C-states supported using MWAIT.\r\n Bits 15 - 12: Number of C3* sub C-states supported using MWAIT.\r\n Bits 19 - 16: Number of C4* sub C-states supported using MWAIT.\r\n Bits 23 - 20: Number of C5* sub C-states supported using MWAIT.\r\n Bits 27 - 24: Number of C6* sub C-states supported using MWAIT.\r\n Bits 31 - 28: Number of C7* sub C-states supported using MWAIT.\r\n NOTE:\r\n * The definition of C0 through C7 states for MWAIT extension are processor-specific C-states, not ACPI C-\r\n states.\r\n Thermal and Power Management Leaf\r\n 06H EAX Bit 00: Digital temperature sensor is supported if set.\r\n Bit 01: Intel Turbo Boost Technology Available (see description of IA32_MISC_ENABLE[38]).\r\n Bit 02: ARAT. APIC-Timer-always-running feature is supported if set.\r\n Bit 03: Reserved.\r\n Bit 04: PLN. Power limit notification controls are supported if set.\r\n Bit 05: ECMD. Clock modulation duty cycle extension is supported if set.\r\n Bit 06: PTM. Package thermal management is supported if set.\r\n Bit 07: HWP. HWP base registers (IA32_PM_ENABLE[bit 0], IA32_HWP_CAPABILITIES,\r\n IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.\r\n Bit 08: HWP_Notification. IA32_HWP_INTERRUPT MSR is supported if set.\r\n Bit 09: HWP_Activity_Window. IA32_HWP_REQUEST[bits 41:32] is supported if set.\r\n Bit 10: HWP_Energy_Performance_Preference. IA32_HWP_REQUEST[bits 31:24] is supported if set.\r\n Bit 11: HWP_Package_Level_Request. IA32_HWP_REQUEST_PKG MSR is supported if set.\r\n Bit 12: Reserved.\r\n Bit 13: HDC. HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1, IA32_THREAD_STALL MSRs are\r\n supported if set.\r\n Bits 31 - 15: Reserved.\r\n EBX Bits 03 - 00: Number of Interrupt Thresholds in Digital Thermal Sensor.\r\n Bits 31 - 04: Reserved.\r\n ECX Bit 00: Hardware Coordination Feedback Capability (Presence of IA32_MPERF and IA32_APERF). The\r\n capability to provide a measure of delivered processor performance (since last reset of the counters), as\r\n a percentage of the expected processor performance when running at the TSC frequency.\r\n Bits 02 - 01: Reserved = 0.\r\n Bit 03: The processor supports performance-energy bias preference if CPUID.06H:ECX.SETBH[bit 3] is set\r\n and it also implies the presence of a new architectural MSR called IA32_ENERGY_PERF_BIAS (1B0H).\r\n Bits 31 - 04: Reserved = 0.\r\n EDX Reserved = 0.\r\n\r\n\r\n\r\n\r\n\r\n Table 3-8. Information Returned by CPUID Instruction (Contd.)\r\n Initial EAX\r\n Value Information Provided about the Processor\r\n Structured Extended Feature Flags Enumeration Leaf (Output depends on ECX input value)\r\n 07H Sub-leaf 0 (Input ECX = 0). *\r\n\r\n\r\n EAX Bits 31 - 00: Reports the maximum input value for supported leaf 7 sub-leaves.\r\n EBX Bit 00: FSGSBASE. Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.\r\n Bit 01: IA32_TSC_ADJUST MSR is supported if 1.\r\n Bit 02: SGX. Supports Intel Software Guard Extensions (Intel SGX Extensions) if 1.\r\n Bit 03: BMI1.\r\n Bit 04: HLE.\r\n Bit 05: AVX2.\r\n Bit 06: FDP_EXCPTN_ONLY. x87 FPU Data Pointer updated only on x87 exceptions if 1.\r\n Bit 07: SMEP. Supports Supervisor-Mode Execution Prevention if 1.\r\n Bit 08: BMI2.\r\n Bit 09: Supports Enhanced REP MOVSB/STOSB if 1.\r\n Bit 10: INVPCID. If 1, supports INVPCID instruction for system software that manages process-context\r\n identifiers.\r\n Bit 11: RTM.\r\n Bit 12: RDT-M. Supports Intel Resource Director Technology (Intel RDT) Monitoring capability if 1.\r\n Bit 13: Deprecates FPU CS and FPU DS values if 1.\r\n Bit 14: MPX. Supports Intel Memory Protection Extensions if 1.\r\n Bit 15: RDT-A. Supports Intel Resource Director Technology (Intel RDT) Allocation capability if 1.\r\n Bits 17:16: Reserved.\r\n Bit 18: RDSEED.\r\n Bit 19: ADX.\r\n Bit 20: SMAP. Supports Supervisor-Mode Access Prevention (and the CLAC/STAC instructions) if 1.\r\n Bits 22 - 21: Reserved.\r\n Bit 23: CLFLUSHOPT.\r\n Bit 24: CLWB.\r\n Bit 25: Intel Processor Trace.\r\n Bits 28 - 26: Reserved.\r\n Bit 29: SHA. supports Intel Secure Hash Algorithm Extensions (Intel SHA Extensions) if 1.\r\n Bits 31 - 30: Reserved.\r\n ECX Bit 00: PREFETCHWT1.\r\n Bit 01: Reserved.\r\n Bit 02: UMIP. Supports user-mode instruction prevention if 1.\r\n Bit 03: PKU. Supports protection keys for user-mode pages if 1.\r\n Bit 04: OSPKE. If 1, OS has set CR4.PKE to enable protection keys (and the RDPKRU/WRPKRU instruc-\r\n tions).\r\n Bits 16 - 5: Reserved.\r\n Bits 21 - 17: The value of MAWAU used by the BNDLDX and BNDSTX instructions in 64-bit mode.\r\n Bit 22: RDPID. Supports Read Processor ID if 1.\r\n Bits 29 - 23: Reserved.\r\n Bit 30: SGX_LC. Supports SGX Launch Configuration if 1.\r\n Bit 31: Reserved.\r\n EDX Reserved.\r\n\r\n NOTE:\r\n * If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n is invalid if n\r\n exceeds the value that sub-leaf 0 returns in EAX.\r\n\r\n\r\n\r\n\r\n\r\n Table 3-8. Information Returned by CPUID Instruction (Contd.)\r\n Initial EAX\r\n Value Information Provided about the Processor\r\n Direct Cache Access Information Leaf\r\n 09H EAX Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H).\r\n EBX Reserved.\r\n ECX Reserved.\r\n EDX Reserved.\r\n Architectural Performance Monitoring Leaf\r\n 0AH EAX Bits 07 - 00: Version ID of architectural performance monitoring.\r\n Bits 15 - 08: Number of general-purpose performance monitoring counter per logical processor.\r\n Bits 23 - 16: Bit width of general-purpose, performance monitoring counter.\r\n Bits 31 - 24: Length of EBX bit vector to enumerate architectural performance monitoring events.\r\n EBX Bit 00: Core cycle event not available if 1.\r\n Bit 01: Instruction retired event not available if 1.\r\n Bit 02: Reference cycles event not available if 1.\r\n Bit 03: Last-level cache reference event not available if 1.\r\n Bit 04: Last-level cache misses event not available if 1.\r\n Bit 05: Branch instruction retired event not available if 1.\r\n Bit 06: Branch mispredict retired event not available if 1.\r\n Bits 31 - 07: Reserved = 0.\r\n ECX Reserved = 0.\r\n EDX Bits 04 - 00: Number of fixed-function performance counters (if Version ID > 1).\r\n Bits 12 - 05: Bit width of fixed-function performance counters (if Version ID > 1).\r\n Reserved = 0.\r\n Extended Topology Enumeration Leaf\r\n 0BH NOTES:\r\n Most of Leaf 0BH output depends on the initial value in ECX.\r\n The EDX output of leaf 0BH is always valid and does not vary with input value in ECX.\r\n Output value in ECX[7:0] always equals input value in ECX[7:0].\r\n For sub-leaves that return an invalid level-type of 0 in ECX[15:8]; EAX and EBX will return 0.\r\n If an input value n in ECX returns the invalid level-type of 0 in ECX[15:8], other input values with ECX >\r\n n also return 0 in ECX[15:8].\r\n\r\n\r\n EAX Bits 04 - 00: Number of bits to shift right on x2APIC ID to get a unique topology ID of the next level type*.\r\n All logical processors with the same next level ID share current level.\r\n Bits 31 - 05: Reserved.\r\n EBX Bits 15 - 00: Number of logical processors at this level type. The number reflects configuration as shipped\r\n by Intel**.\r\n Bits 31- 16: Reserved.\r\n ECX Bits 07 - 00: Level number. Same value in ECX input.\r\n Bits 15 - 08: Level type***.\r\n Bits 31 - 16: Reserved.\r\n EDX Bits 31- 00: x2APIC ID the current logical processor.\r\n NOTES:\r\n * Software should use this field (EAX[4:0]) to enumerate processor topology of the system.\r\n\r\n\r\n\r\n\r\n\r\n Table 3-8. Information Returned by CPUID Instruction (Contd.)\r\n Initial EAX\r\n Value Information Provided about the Processor\r\n ** Software must not use EBX[15:0] to enumerate processor topology of the system. This value in this\r\n field (EBX[15:0]) is only intended for display/diagnostic purposes. The actual number of logical processors\r\n available to BIOS/OS/Applications may be different from the value of EBX[15:0], depending on software\r\n and platform hardware configurations.\r\n\r\n *** The value of the \"level type\" field is not related to level numbers in any way, higher \"level type\" val-\r\n ues do not mean higher levels. Level type field has the following encoding:\r\n 0: Invalid.\r\n 1: SMT.\r\n 2: Core.\r\n 3-255: Reserved.\r\n Processor Extended State Enumeration Main Leaf (EAX = 0DH, ECX = 0)\r\n 0DH NOTES:\r\n Leaf 0DH main leaf (ECX = 0).\r\n EAX Bits 31 - 00: Reports the supported bits of the lower 32 bits of XCR0. XCR0[n] can be set to 1 only if\r\n EAX[n] is 1.\r\n Bit 00: x87 state.\r\n Bit 01: SSE state.\r\n Bit 02: AVX state.\r\n Bits 04 - 03: MPX state.\r\n Bits 07 - 05: AVX-512 state.\r\n Bit 08: Used for IA32_XSS.\r\n Bit 09: PKRU state.\r\n Bits 31 - 10: Reserved.\r\n EBX Bits 31 - 00: Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save area) required by\r\n enabled features in XCR0. May be different than ECX if some features at the end of the XSAVE save area\r\n are not enabled.\r\n ECX Bit 31 - 00: Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save area) of the\r\n XSAVE/XRSTOR save area required by all supported features in the processor, i.e., all the valid bit fields in\r\n XCR0.\r\n EDX Bit 31 - 00: Reports the supported bits of the upper 32 bits of XCR0. XCR0[n+32] can be set to 1 only if\r\n EDX[n] is 1.\r\n Bits 31 - 00: Reserved.\r\n Processor Extended State Enumeration Sub-leaf (EAX = 0DH, ECX = 1)\r\n 0DH EAX Bit 00: XSAVEOPT is available.\r\n Bit 01: Supports XSAVEC and the compacted form of XRSTOR if set.\r\n Bit 02: Supports XGETBV with ECX = 1 if set.\r\n Bit 03: Supports XSAVES/XRSTORS and IA32_XSS if set.\r\n Bits 31 - 04: Reserved.\r\n EBX Bits 31 - 00: The size in bytes of the XSAVE area containing all states enabled by XCRO | IA32_XSS.\r\n ECX Bits 31 - 00: Reports the supported bits of the lower 32 bits of the IA32_XSS MSR. IA32_XSS[n] can be\r\n set to 1 only if ECX[n] is 1.\r\n Bits 07 - 00: Used for XCR0.\r\n Bit 08: PT state.\r\n Bit 09: Used for XCR0.\r\n Bits 31 - 10: Reserved.\r\n EDX Bits 31 - 00: Reports the supported bits of the upper 32 bits of the IA32_XSS MSR. IA32_XSS[n+32] can\r\n be set to 1 only if EDX[n] is 1.\r\n Bits 31 - 00: Reserved.\r\n\r\n\r\n\r\n\r\n Table 3-8. Information Returned by CPUID Instruction (Contd.)\r\n Initial EAX\r\n Value Information Provided about the Processor\r\n Processor Extended State Enumeration Sub-leaves (EAX = 0DH, ECX = n, n > 1)\r\n 0DH NOTES:\r\n Leaf 0DH output depends on the initial value in ECX.\r\n Each sub-leaf index (starting at position 2) is supported if it corresponds to a supported bit in either the\r\n XCR0 register or the IA32_XSS MSR.\r\n * If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf n (0 <= n <= 31) is invalid\r\n if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1 returns 0 in ECX[n]. Sub-leaf n (32 <= n <= 63) is invalid if\r\n sub-leaf 0 returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32].\r\n EAX Bits 31 - 0: The size in bytes (from the offset specified in EBX) of the save area for an extended state\r\n feature associated with a valid sub-leaf index, n.\r\n EBX Bits 31 - 0: The offset in bytes of this extended state component's save area from the beginning of the\r\n XSAVE/XRSTOR area.\r\n This field reports 0 if the sub-leaf index, n, does not map to a valid bit in the XCR0 register*.\r\n ECX Bit 00 is set if the bit n (corresponding to the sub-leaf index) is supported in the IA32_XSS MSR; it is clear\r\n if bit n is instead supported in XCR0.\r\n Bit 01 is set if, when the compacted format of an XSAVE area is used, this extended state component\r\n located on the next 64-byte boundary following the preceding state component (otherwise, it is located\r\n immediately following the preceding state component).\r\n Bits 31 - 02 are reserved.\r\n This field reports 0 if the sub-leaf index, n, is invalid*.\r\n EDX This field reports 0 if the sub-leaf index, n, is invalid*; otherwise it is reserved.\r\n Intel Resource Director Technology (Intel RDT) Monitoring Enumeration Sub-leaf (EAX = 0FH, ECX = 0)\r\n 0FH NOTES:\r\n Leaf 0FH output depends on the initial value in ECX.\r\n Sub-leaf index 0 reports valid resource type starting at bit position 1 of EDX.\r\n EAX Reserved.\r\n EBX Bits 31 - 00: Maximum range (zero-based) of RMID within this physical processor of all types.\r\n ECX Reserved.\r\n EDX Bit 00: Reserved.\r\n Bit 01: Supports L3 Cache Intel RDT Monitoring if 1.\r\n Bits 31 - 02: Reserved.\r\n L3 Cache Intel RDT Monitoring Capability Enumeration Sub-leaf (EAX = 0FH, ECX = 1)\r\n 0FH NOTES:\r\n Leaf 0FH output depends on the initial value in ECX.\r\n EAX Reserved.\r\n EBX Bits 31 - 00: Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes).\r\n ECX Maximum range (zero-based) of RMID of this resource type.\r\n EDX Bit 00: Supports L3 occupancy monitoring if 1.\r\n Bit 01: Supports L3 Total Bandwidth monitoring if 1.\r\n Bit 02: Supports L3 Local Bandwidth monitoring if 1.\r\n Bits 31 - 03: Reserved.\r\n\r\n\r\n\r\n\r\n\r\n Table 3-8. Information Returned by CPUID Instruction (Contd.)\r\n Initial EAX\r\n Value Information Provided about the Processor\r\n Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf (EAX = 10H, ECX = 0)\r\n 10H NOTES:\r\n Leaf 10H output depends on the initial value in ECX.\r\n Sub-leaf index 0 reports valid resource identification (ResID) starting at bit position 1 of EBX.\r\n EAX Reserved.\r\n EBX Bit 00: Reserved.\r\n Bit 01: Supports L3 Cache Allocation Technology if 1.\r\n Bit 02: Supports L2 Cache Allocation Technology if 1.\r\n Bits 31 - 03: Reserved.\r\n ECX Reserved.\r\n EDX Reserved.\r\n L3 Cache Allocation Technology Enumeration Sub-leaf (EAX = 10H, ECX = ResID =1)\r\n 10H NOTES:\r\n Leaf 10H output depends on the initial value in ECX.\r\n EAX Bits 4 - 00: Length of the capacity bit mask for the corresponding ResID using minus-one notation.\r\n Bits 31 - 05: Reserved.\r\n EBX Bits 31 - 00: Bit-granular map of isolation/contention of allocation units.\r\n ECX Bit 00: Reserved.\r\n Bit 01: Updates of COS should be infrequent if 1.\r\n Bit 02: Code and Data Prioritization Technology supported if 1.\r\n Bits 31 - 03: Reserved.\r\n EDX Bits 15 - 00: Highest COS number supported for this ResID.\r\n Bits 31 - 16: Reserved.\r\n L2 Cache Allocation Technology Enumeration Sub-leaf (EAX = 10H, ECX = ResID =2)\r\n 10H NOTES:\r\n Leaf 10H output depends on the initial value in ECX.\r\n EAX Bits 4 - 00: Length of the capacity bit mask for the corresponding ResID using minus-one notation.\r\n Bits 31 - 05: Reserved.\r\n EBX Bits 31 - 00: Bit-granular map of isolation/contention of allocation units.\r\n ECX Bits 31 - 00: Reserved.\r\n EDX Bits 15 - 00: Highest COS number supported for this ResID.\r\n Bits 31 - 16: Reserved.\r\n Intel SGX Capability Enumeration Leaf, sub-leaf 0 (EAX = 12H, ECX = 0)\r\n 12H NOTES:\r\n Leaf 12H sub-leaf 0 (ECX = 0) is supported if CPUID.(EAX=07H, ECX=0H):EBX[SGX] = 1.\r\n EAX Bit 00: SGX1. If 1, Indicates Intel SGX supports the collection of SGX1 leaf functions.\r\n Bit 01: SGX2. If 1, Indicates Intel SGX supports the collection of SGX2 leaf functions.\r\n Bit 31 - 02: Reserved.\r\n EBX Bit 31 - 00: MISCSELECT. Bit vector of supported extended SGX features.\r\n ECX Bit 31 - 00: Reserved.\r\n\r\n\r\n\r\n\r\n\r\n Table 3-8. Information Returned by CPUID Instruction (Contd.)\r\n Initial EAX\r\n Value Information Provided about the Processor\r\n EDX Bit 07 - 00: MaxEnclaveSize_Not64. The maximum supported enclave size in non-64-bit mode is\r\n 2^(EDX[7:0]).\r\n Bit 15 - 08: MaxEnclaveSize_64. The maximum supported enclave size in 64-bit mode is 2^(EDX[15:8]).\r\n Bits 31 - 16: Reserved.\r\n Intel SGX Attributes Enumeration Leaf, sub-leaf 1 (EAX = 12H, ECX = 1)\r\n 12H NOTES:\r\n Leaf 12H sub-leaf 1 (ECX = 1) is supported if CPUID.(EAX=07H, ECX=0H):EBX[SGX] = 1.\r\n EAX Bit 31 - 00: Reports the valid bits of SECS.ATTRIBUTES[31:0] that software can set with ECREATE.\r\n EBX Bit 31 - 00: Reports the valid bits of SECS.ATTRIBUTES[63:32] that software can set with ECREATE.\r\n ECX Bit 31 - 00: Reports the valid bits of SECS.ATTRIBUTES[95:64] that software can set with ECREATE.\r\n EDX Bit 31 - 00: Reports the valid bits of SECS.ATTRIBUTES[127:96] that software can set with ECREATE.\r\n Intel SGX EPC Enumeration Leaf, sub-leaves (EAX = 12H, ECX = 2 or higher)\r\n 12H NOTES:\r\n Leaf 12H sub-leaf 2 or higher (ECX >= 2) is supported if CPUID.(EAX=07H, ECX=0H):EBX[SGX] = 1.\r\n For sub-leaves (ECX = 2 or higher), definition of EDX,ECX,EBX,EAX[31:4] depends on the sub-leaf type\r\n listed below.\r\n EAX Bit 03 - 00: Sub-leaf Type\r\n 0000b: Indicates this sub-leaf is invalid.\r\n 0001b: This sub-leaf enumerates an EPC section. EBX:EAX and EDX:ECX provide information on the\r\n Enclave Page Cache (EPC) section.\r\n All other type encodings are reserved.\r\n Type 0000b. This sub-leaf is invalid.\r\n EDX:ECX:EBX:EAX return 0.\r\n Type 0001b. This sub-leaf enumerates an EPC sections with EDX:ECX, EBX:EAX defined as follows.\r\n EAX[11:04]: Reserved (enumerate 0).\r\n EAX[31:12]: Bits 31:12 of the physical address of the base of the EPC section.\r\n\r\n EBX[19:00]: Bits 51:32 of the physical address of the base of the EPC section.\r\n EBX[31:20]: Reserved.\r\n\r\n ECX[03:00]: EPC section property encoding defined as follows:\r\n If EAX[3:0] 0000b, then all bits of the EDX:ECX pair are enumerated as 0.\r\n If EAX[3:0] 0001b, then this section has confidentiality and integrity protection.\r\n All other encodings are reserved.\r\n ECX[11:04]: Reserved (enumerate 0).\r\n ECX[31:12]: Bits 31:12 of the size of the corresponding EPC section within the Processor Reserved\r\n Memory.\r\n\r\n EDX[19:00]: Bits 51:32 of the size of the corresponding EPC section within the Processor Reserved\r\n Memory.\r\n EDX[31:20]: Reserved.\r\n\r\n\r\n\r\n\r\n\r\n Table 3-8. Information Returned by CPUID Instruction (Contd.)\r\n Initial EAX\r\n Value Information Provided about the Processor\r\n Intel Processor Trace Enumeration Main Leaf (EAX = 14H, ECX = 0)\r\n 14H NOTES:\r\n Leaf 14H main leaf (ECX = 0).\r\n EAX Bits 31 - 00: Reports the maximum sub-leaf supported in leaf 14H.\r\n EBX Bit 00: If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1, and that IA32_RTIT_CR3_MATCH\r\n MSR can be accessed.\r\n Bit 01: If 1, indicates support of Configurable PSB and Cycle-Accurate Mode.\r\n Bit 02: If 1, indicates support of IP Filtering, TraceStop filtering, and preservation of Intel PT MSRs across\r\n warm reset.\r\n Bit 03: If 1, indicates support of MTC timing packet and suppression of COFI-based packets.\r\n Bit 04: If 1, indicates support of PTWRITE. Writes can set IA32_RTIT_CTL[12] (PTWEn) and\r\n IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE can generate packets.\r\n Bit 05: If 1, indicates support of Power Event Trace. Writes can set IA32_RTIT_CTL[4] (PwrEvtEn),\r\n enabling Power Event Trace packet generation.\r\n Bit 31 - 06: Reserved.\r\n ECX Bit 00: If 1, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence utilizing the ToPA output\r\n scheme; IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.\r\n Bit 01: If 1, ToPA tables can hold any number of output entries, up to the maximum allowed by the Mas-\r\n kOrTableOffset field of IA32_RTIT_OUTPUT_MASK_PTRS.\r\n Bit 02: If 1, indicates support of Single-Range Output scheme.\r\n Bit 03: If 1, indicates support of output to Trace Transport subsystem.\r\n Bit 30 - 04: Reserved.\r\n Bit 31: If 1, generated packets which contain IP payloads have LIP values, which include the CS base com-\r\n ponent.\r\n EDX Bits 31 - 00: Reserved.\r\n Intel Processor Trace Enumeration Sub-leaf (EAX = 14H, ECX = 1)\r\n 14H EAX Bits 02 - 00: Number of configurable Address Ranges for filtering.\r\n Bits 15 - 03: Reserved.\r\n Bits 31 - 16: Bitmap of supported MTC period encodings.\r\n EBX Bits 15 - 00: Bitmap of supported Cycle Threshold value encodings.\r\n Bit 31 - 16: Bitmap of supported Configurable PSB frequency encodings.\r\n ECX Bits 31 - 00: Reserved.\r\n EDX Bits 31 - 00: Reserved.\r\n Time Stamp Counter and Nominal Core Crystal Clock Information Leaf\r\n 15H NOTES:\r\n If EBX[31:0] is 0, the TSC/\"core crystal clock\" ratio is not enumerated.\r\n EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core crystal clock frequency.\r\n If ECX is 0, the nominal core crystal clock frequency is not enumerated.\r\n \"TSC frequency\" = \"core crystal clock frequency\" * EBX/EAX.\r\n The core crystal clock may differ from the reference clock, bus clock, or core clock frequencies.\r\n EAX Bits 31 - 00: An unsigned integer which is the denominator of the TSC/\"core crystal clock\" ratio.\r\n EBX Bits 31 - 00: An unsigned integer which is the numerator of the TSC/\"core crystal clock\" ratio.\r\n ECX Bits 31 - 00: An unsigned integer which is the nominal frequency of the core crystal clock in Hz.\r\n EDX Bits 31 - 00: Reserved = 0.\r\n\r\n\r\n\r\n\r\n\r\n Table 3-8. Information Returned by CPUID Instruction (Contd.)\r\n Initial EAX\r\n Value Information Provided about the Processor\r\n Processor Frequency Information Leaf\r\n 16H EAX Bits 15 - 00: Processor Base Frequency (in MHz).\r\n Bits 31 - 16: Reserved =0.\r\n EBX Bits 15 - 00: Maximum Frequency (in MHz).\r\n Bits 31 - 16: Reserved = 0.\r\n ECX Bits 15 - 00: Bus (Reference) Frequency (in MHz).\r\n Bits 31 - 16: Reserved = 0.\r\n EDX Reserved.\r\n NOTES:\r\n * Data is returned from this interface in accordance with the processor's specification and does not reflect\r\n actual values. Suitable use of this data includes the display of processor information in like manner to the\r\n processor brand string and for determining the appropriate range to use when displaying processor\r\n information e.g. frequency history graphs. The returned information should not be used for any other\r\n purpose as the returned information does not accurately correlate to information / counters returned by\r\n other processor interfaces.\r\n\r\n While a processor may support the Processor Frequency Information leaf, fields that return a value of\r\n zero are not supported.\r\n System-On-Chip Vendor Attribute Enumeration Main Leaf (EAX = 17H, ECX = 0)\r\n 17H NOTES:\r\n Leaf 17H main leaf (ECX = 0).\r\n Leaf 17H output depends on the initial value in ECX.\r\n Leaf 17H sub-leaves 1 through 3 reports SOC Vendor Brand String.\r\n Leaf 17H is valid if MaxSOCID_Index >= 3.\r\n Leaf 17H sub-leaves 4 and above are reserved.\r\n\r\n\r\n EAX Bits 31 - 00: MaxSOCID_Index. Reports the maximum input value of supported sub-leaf in leaf 17H.\r\n EBX Bits 15 - 00: SOC Vendor ID.\r\n Bit 16: IsVendorScheme. If 1, the SOC Vendor ID field is assigned via an industry standard enumeration\r\n scheme. Otherwise, the SOC Vendor ID field is assigned by Intel.\r\n Bits 31 - 17: Reserved = 0.\r\n ECX Bits 31 - 00: Project ID. A unique number an SOC vendor assigns to its SOC projects.\r\n EDX Bits 31 - 00: Stepping ID. A unique number within an SOC project that an SOC vendor assigns.\r\n System-On-Chip Vendor Attribute Enumeration Sub-leaf (EAX = 17H, ECX = 1..3)\r\n 17H EAX Bit 31 - 00: SOC Vendor Brand String. UTF-8 encoded string.\r\n EBX Bit 31 - 00: SOC Vendor Brand String. UTF-8 encoded string.\r\n ECX Bit 31 - 00: SOC Vendor Brand String. UTF-8 encoded string.\r\n EDX Bit 31 - 00: SOC Vendor Brand String. UTF-8 encoded string.\r\n NOTES:\r\n Leaf 17H output depends on the initial value in ECX.\r\n SOC Vendor Brand String is a UTF-8 encoded string padded with trailing bytes of 00H.\r\n The complete SOC Vendor Brand String is constructed by concatenating in ascending order of\r\n EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3.\r\n\r\n\r\n\r\n\r\n\r\n Table 3-8. Information Returned by CPUID Instruction (Contd.)\r\n Initial EAX\r\n Value Information Provided about the Processor\r\n System-On-Chip Vendor Attribute Enumeration Sub-leaves (EAX = 17H, ECX > MaxSOCID_Index)\r\n 17H NOTES:\r\n Leaf 17H output depends on the initial value in ECX.\r\n\r\n\r\n EAX Bits 31 - 00: Reserved = 0.\r\n EBX Bits 31 - 00: Reserved = 0.\r\n ECX Bits 31 - 00: Reserved = 0.\r\n EDX Bits 31 - 00: Reserved = 0.\r\n Unimplemented CPUID Leaf Functions\r\n 40000000H Invalid. No existing or future CPU will return processor identification or feature information if the initial\r\n - EAX value is in the range 40000000H to 4FFFFFFFH.\r\n 4FFFFFFFH\r\n Extended Function CPUID Information\r\n 80000000H EAX Maximum Input Value for Extended Function CPUID Information.\r\n EBX Reserved.\r\n ECX Reserved.\r\n EDX Reserved.\r\n 80000001H EAX Extended Processor Signature and Feature Bits.\r\n EBX Reserved.\r\n ECX Bit 00: LAHF/SAHF available in 64-bit mode.\r\n Bits 04 - 01: Reserved.\r\n Bit 05: LZCNT.\r\n Bits 07 - 06: Reserved.\r\n Bit 08: PREFETCHW.\r\n Bits 31 - 09: Reserved.\r\n EDX Bits 10 - 00: Reserved.\r\n Bit 11: SYSCALL/SYSRET available in 64-bit mode.\r\n Bits 19 - 12: Reserved = 0.\r\n Bit 20: Execute Disable Bit available.\r\n Bits 25 - 21: Reserved = 0.\r\n Bit 26: 1-GByte pages are available if 1.\r\n Bit 27: RDTSCP and IA32_TSC_AUX are available if 1.\r\n Bit 28: Reserved = 0.\r\n Bit 29: Intel 64 Architecture available if 1.\r\n Bits 31 - 30: Reserved = 0.\r\n 80000002H EAX Processor Brand String.\r\n EBX Processor Brand String Continued.\r\n ECX Processor Brand String Continued.\r\n EDX Processor Brand String Continued.\r\n 80000003H EAX Processor Brand String Continued.\r\n EBX Processor Brand String Continued.\r\n ECX Processor Brand String Continued.\r\n EDX Processor Brand String Continued.\r\n\r\n\r\n\r\n\r\n\r\n Table 3-8. Information Returned by CPUID Instruction (Contd.)\r\n Initial EAX\r\n Value Information Provided about the Processor\r\n 80000004H EAX Processor Brand String Continued.\r\n EBX Processor Brand String Continued.\r\n ECX Processor Brand String Continued.\r\n EDX Processor Brand String Continued.\r\n 80000005H EAX Reserved = 0.\r\n EBX Reserved = 0.\r\n ECX Reserved = 0.\r\n EDX Reserved = 0.\r\n 80000006H EAX Reserved = 0.\r\n EBX Reserved = 0.\r\n ECX Bits 07 - 00: Cache Line size in bytes.\r\n Bits 11 - 08: Reserved.\r\n Bits 15 - 12: L2 Associativity field *.\r\n Bits 31 - 16: Cache size in 1K units.\r\n EDX Reserved = 0.\r\n NOTES:\r\n * L2 associativity field encodings:\r\n 00H - Disabled.\r\n 01H - Direct mapped.\r\n 02H - 2-way.\r\n 04H - 4-way.\r\n 06H - 8-way.\r\n 08H - 16-way.\r\n 0FH - Fully associative.\r\n 80000007H EAX Reserved = 0.\r\n EBX Reserved = 0.\r\n ECX Reserved = 0.\r\n EDX Bits 07 - 00: Reserved = 0.\r\n Bit 08: Invariant TSC available if 1.\r\n Bits 31 - 09: Reserved = 0.\r\n 80000008H EAX Linear/Physical Address size.\r\n Bits 07 - 00: #Physical Address Bits*.\r\n Bits 15 - 08: #Linear Address Bits.\r\n Bits 31 - 16: Reserved = 0.\r\n EBX Reserved = 0.\r\n ECX Reserved = 0.\r\n EDX Reserved = 0.\r\n\r\n NOTES:\r\n * If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address number supported should\r\n come from this field.\r\n\r\n\r\nINPUT EAX = 0: Returns CPUID's Highest Value for Basic Processor Information and the Vendor Identification String\r\nWhen CPUID executes with EAX set to 0, the processor returns the highest value the CPUID recognizes for\r\nreturning basic processor information. The value is returned in the EAX register and is processor specific.\r\n\r\n\r\n\r\n\r\n\r\nA vendor identification string is also returned in EBX, EDX, and ECX. For Intel processors, the string is \"Genuin-\r\neIntel\" and is expressed:\r\n EBX <- 756e6547h (* \"Genu\", with G in the low eight bits of BL *)\r\n EDX <- 49656e69h (* \"ineI\", with i in the low eight bits of DL *)\r\n ECX <- 6c65746eh (* \"ntel\", with n in the low eight bits of CL *)\r\n\r\nINPUT EAX = 80000000H: Returns CPUID's Highest Value for Extended Processor Information\r\nWhen CPUID executes with EAX set to 80000000H, the processor returns the highest value the processor recog-\r\nnizes for returning extended processor information. The value is returned in the EAX register and is processor\r\nspecific.\r\n\r\nIA32_BIOS_SIGN_ID Returns Microcode Update Signature\r\nFor processors that support the microcode update facility, the IA32_BIOS_SIGN_ID MSR is loaded with the update\r\nsignature whenever CPUID executes. The signature is returned in the upper DWORD. For details, see Chapter 9 in\r\nthe Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\nINPUT EAX = 01H: Returns Model, Family, Stepping Information\r\nWhen CPUID executes with EAX set to 01H, version information is returned in EAX (see Figure 3-6). For example:\r\nmodel, family, and processor type for the Intel Xeon processor 5100 series is as follows:\r\n. Model - 1111B\r\n. Family - 0101B\r\n. Processor Type - 00B\r\nSee Table 3-9 for available processor type values. Stepping IDs are provided as needed.\r\n\r\n\r\n\r\n\r\n 31 28 27 20 19 16 15 14 13 12 11 8 7 4 3 0\r\n\r\n\r\n Extended Extended Family Stepping\r\n EAX Model\r\n Family ID Model ID ID ID\r\n\r\n\r\n Extended Family ID (0)\r\n Extended Model ID (0)\r\n Processor Type\r\n Family (0FH for the Pentium 4 Processor Family)\r\n Model\r\n\r\n Reserved\r\n OM16525\r\n\r\n\r\n Figure 3-6. Version Information Returned by CPUID in EAX\r\n\r\n\r\n\r\n\r\n\r\n Table 3-9. Processor Type Field\r\n Type Encoding\r\n Original OEM Processor 00B\r\n \r\n Intel OverDrive Processor 01B\r\n Dual processor (not applicable to Intel486 processors) 10B\r\n Intel reserved 11B\r\n\r\n NOTE\r\n See Chapter 19 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1,\r\n for information on identifying earlier IA-32 processors.\r\n\r\n\r\nThe Extended Family ID needs to be examined only when the Family ID is 0FH. Integrate the fields into a display\r\nusing the following rule:\r\n\r\n IF Family_ID != 0FH\r\n THEN DisplayFamily = Family_ID;\r\n ELSE DisplayFamily = Extended_Family_ID + Family_ID;\r\n (* Right justify and zero-extend 4-bit field. *)\r\n FI;\r\n (* Show DisplayFamily as HEX field. *)\r\nThe Extended Model ID needs to be examined only when the Family ID is 06H or 0FH. Integrate the field into a\r\ndisplay using the following rule:\r\n\r\n IF (Family_ID = 06H or Family_ID = 0FH)\r\n THEN DisplayModel = (Extended_Model_ID << 4) + Model_ID;\r\n (* Right justify and zero-extend 4-bit field; display Model_ID as HEX field.*)\r\n ELSE DisplayModel = Model_ID;\r\n FI;\r\n (* Show DisplayModel as HEX field. *)\r\n\r\nINPUT EAX = 01H: Returns Additional Information in EBX\r\nWhen CPUID executes with EAX set to 01H, additional information is returned to the EBX register:\r\n. Brand index (low byte of EBX) - this number provides an entry into a brand string table that contains brand\r\n strings for IA-32 processors. More information about this field is provided later in this section.\r\n. CLFLUSH instruction cache line size (second byte of EBX) - this number indicates the size of the cache line\r\n flushed by the CLFLUSH and CLFLUSHOPT instructions in 8-byte increments. This field was introduced in the\r\n Pentium 4 processor.\r\n. Local APIC ID (high byte of EBX) - this number is the 8-bit ID that is assigned to the local APIC on the\r\n processor during power up. This field was introduced in the Pentium 4 processor.\r\n\r\nINPUT EAX = 01H: Returns Feature Information in ECX and EDX\r\nWhen CPUID executes with EAX set to 01H, feature information is returned in ECX and EDX.\r\n. Figure 3-7 and Table 3-10 show encodings for ECX.\r\n. Figure 3-8 and Table 3-11 show encodings for EDX.\r\nFor all feature flags, a 1 indicates that the feature is supported. Use Intel to properly interpret feature flags.\r\n\r\n NOTE\r\n Software must confirm that a processor feature is present using feature flags returned by CPUID\r\n prior to using the feature. Software should not depend on future offerings retaining all features.\r\n\r\n\r\n\r\n\r\n\r\n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0\r\n\r\n\r\n\r\n ECX\r\n 0\r\n\r\n\r\n RDRAND\r\n F16C\r\n AVX\r\n OSXSAVE\r\n XSAVE\r\n AES\r\n TSC-Deadline\r\n POPCNT\r\n MOVBE\r\n x2APIC\r\n SSE4_2 - SSE4.2\r\n SSE4_1 - SSE4.1\r\n DCA - Direct Cache Access\r\n PCID - Process-context Identifiers\r\n PDCM - Perf/Debug Capability MSR\r\n xTPR Update Control\r\n CMPXCHG16B\r\n FMA - Fused Multiply Add\r\n SDBG\r\n CNXT-ID - L1 Context ID\r\n SSSE3 - SSSE3 Extensions\r\n TM2 - Thermal Monitor 2\r\n EIST - Enhanced Intel SpeedStep Technology\r\n SMX - Safer Mode Extensions\r\n VMX - Virtual Machine Extensions\r\n DS-CPL - CPL Qualified Debug Store\r\n MONITOR - MONITOR/MWAIT\r\n DTES64 - 64-bit DS Area\r\n PCLMULQDQ - Carryless Multiplication\r\n SSE3 - SSE3 Extensions\r\n OM16524b\r\n Reserved\r\n\r\n Figure 3-7. Feature Information Returned in the ECX Register\r\n\r\n\r\n Table 3-10. Feature Information Returned in the ECX Register\r\n Bit # Mnemonic Description\r\n 0 SSE3 Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the processor supports this\r\n technology.\r\n 1 PCLMULQDQ PCLMULQDQ. A value of 1 indicates the processor supports the PCLMULQDQ instruction.\r\n 2 DTES64 64-bit DS Area. A value of 1 indicates the processor supports DS area using 64-bit layout.\r\n 3 MONITOR MONITOR/MWAIT. A value of 1 indicates the processor supports this feature.\r\n 4 DS-CPL CPL Qualified Debug Store. A value of 1 indicates the processor supports the extensions to the\r\n Debug Store feature to allow for branch message storage qualified by CPL.\r\n 5 VMX Virtual Machine Extensions. A value of 1 indicates that the processor supports this technology.\r\n 6 SMX Safer Mode Extensions. A value of 1 indicates that the processor supports this technology. See\r\n Chapter 6, \"Safer Mode Extensions Reference\".\r\n 7 EIST Enhanced Intel SpeedStep technology. A value of 1 indicates that the processor supports this\r\n technology.\r\n 8 TM2 Thermal Monitor 2. A value of 1 indicates whether the processor supports this technology.\r\n 9 SSSE3 A value of 1 indicates the presence of the Supplemental Streaming SIMD Extensions 3 (SSSE3). A\r\n value of 0 indicates the instruction extensions are not present in the processor.\r\n\r\n\r\n\r\n Table 3-10. Feature Information Returned in the ECX Register (Contd.)\r\n Bit # Mnemonic Description\r\n 10 CNXT-ID L1 Context ID. A value of 1 indicates the L1 data cache mode can be set to either adaptive mode\r\n or shared mode. A value of 0 indicates this feature is not supported. See definition of the\r\n IA32_MISC_ENABLE MSR Bit 24 (L1 Data Cache Context Mode) for details.\r\n 11 SDBG A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE MSR for silicon debug.\r\n 12 FMA A value of 1 indicates the processor supports FMA extensions using YMM state.\r\n 13 CMPXCHG16B CMPXCHG16B Available. A value of 1 indicates that the feature is available. See the\r\n \"CMPXCHG8B/CMPXCHG16B-Compare and Exchange Bytes\" section in this chapter for a\r\n description.\r\n 14 xTPR Update xTPR Update Control. A value of 1 indicates that the processor supports changing\r\n Control IA32_MISC_ENABLE[bit 23].\r\n 15 PDCM Perfmon and Debug Capability: A value of 1 indicates the processor supports the performance\r\n and debug feature indication MSR IA32_PERF_CAPABILITIES.\r\n 16 Reserved Reserved\r\n 17 PCID Process-context identifiers. A value of 1 indicates that the processor supports PCIDs and that\r\n software may set CR4.PCIDE to 1.\r\n 18 DCA A value of 1 indicates the processor supports the ability to prefetch data from a memory mapped\r\n device.\r\n 19 SSE4.1 A value of 1 indicates that the processor supports SSE4.1.\r\n 20 SSE4.2 A value of 1 indicates that the processor supports SSE4.2.\r\n 21 x2APIC A value of 1 indicates that the processor supports x2APIC feature.\r\n 22 MOVBE A value of 1 indicates that the processor supports MOVBE instruction.\r\n 23 POPCNT A value of 1 indicates that the processor supports the POPCNT instruction.\r\n 24 TSC-Deadline A value of 1 indicates that the processor's local APIC timer supports one-shot operation using a\r\n TSC deadline value.\r\n 25 AESNI A value of 1 indicates that the processor supports the AESNI instruction extensions.\r\n 26 XSAVE A value of 1 indicates that the processor supports the XSAVE/XRSTOR processor extended states\r\n feature, the XSETBV/XGETBV instructions, and XCR0.\r\n 27 OSXSAVE A value of 1 indicates that the OS has set CR4.OSXSAVE[bit 18] to enable XSETBV/XGETBV\r\n instructions to access XCR0 and to support processor extended state management using\r\n XSAVE/XRSTOR.\r\n 28 AVX A value of 1 indicates the processor supports the AVX instruction extensions.\r\n 29 F16C A value of 1 indicates that processor supports 16-bit floating-point conversion instructions.\r\n 30 RDRAND A value of 1 indicates that processor supports RDRAND instruction.\r\n 31 Not Used Always returns 0.\r\n\r\n\r\n\r\n\r\n\r\n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0\r\n\r\n\r\n EDX\r\n\r\n\r\n PBE-Pend. Brk. EN.\r\n TM-Therm. Monitor\r\n HTT-Multi-threading\r\n SS-Self Snoop\r\n SSE2-SSE2 Extensions\r\n SSE-SSE Extensions\r\n FXSR-FXSAVE/FXRSTOR\r\n MMX-MMX Technology\r\n ACPI-Thermal Monitor and Clock Ctrl\r\n DS-Debug Store\r\n CLFSH-CLFLUSH instruction\r\n PSN-Processor Serial Number\r\n PSE-36 - Page Size Extension\r\n PAT-Page Attribute Table\r\n CMOV-Conditional Move/Compare Instruction\r\n MCA-Machine Check Architecture\r\n PGE-PTE Global Bit\r\n MTRR-Memory Type Range Registers\r\n SEP-SYSENTER and SYSEXIT\r\n APIC-APIC on Chip\r\n CX8-CMPXCHG8B Inst.\r\n MCE-Machine Check Exception\r\n PAE-Physical Address Extensions\r\n MSR-RDMSR and WRMSR Support\r\n TSC-Time Stamp Counter\r\n PSE-Page Size Extensions\r\n DE-Debugging Extensions\r\n VME-Virtual-8086 Mode Enhancement\r\n FPU-x87 FPU on Chip\r\n\r\n Reserved\r\n OM16523\r\n\r\n\r\n\r\n Figure 3-8. Feature Information Returned in the EDX Register\r\n\r\n\r\n\r\n\r\n\r\n Table 3-11. More on Feature Information Returned in the EDX Register\r\n Bit # Mnemonic Description\r\n 0 FPU Floating Point Unit On-Chip. The processor contains an x87 FPU.\r\n 1 VME Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements, including CR4.VME for controlling the\r\n feature, CR4.PVI for protected mode virtual interrupts, software interrupt indirection, expansion of the TSS\r\n with the software indirection bitmap, and EFLAGS.VIF and EFLAGS.VIP flags.\r\n 2 DE Debugging Extensions. Support for I/O breakpoints, including CR4.DE for controlling the feature, and optional\r\n trapping of accesses to DR4 and DR5.\r\n 3 PSE Page Size Extension. Large pages of size 4 MByte are supported, including CR4.PSE for controlling the\r\n feature, the defined dirty bit in PDE (Page Directory Entries), optional reserved bit trapping in CR3, PDEs, and\r\n PTEs.\r\n 4 TSC Time Stamp Counter. The RDTSC instruction is supported, including CR4.TSD for controlling privilege.\r\n 5 MSR Model Specific Registers RDMSR and WRMSR Instructions. The RDMSR and WRMSR instructions are\r\n supported. Some of the MSRs are implementation dependent.\r\n 6 PAE Physical Address Extension. Physical addresses greater than 32 bits are supported: extended page table\r\n entry formats, an extra level in the page translation tables is defined, 2-MByte pages are supported instead of\r\n 4 Mbyte pages if PAE bit is 1.\r\n 7 MCE Machine Check Exception. Exception 18 is defined for Machine Checks, including CR4.MCE for controlling the\r\n feature. This feature does not define the model-specific implementations of machine-check error logging,\r\n reporting, and processor shutdowns. Machine Check exception handlers may have to depend on processor\r\n version to do model specific processing of the exception, or test for the presence of the Machine Check feature.\r\n 8 CX8 CMPXCHG8B Instruction. The compare-and-exchange 8 bytes (64 bits) instruction is supported (implicitly\r\n locked and atomic).\r\n 9 APIC APIC On-Chip. The processor contains an Advanced Programmable Interrupt Controller (APIC), responding to\r\n memory mapped commands in the physical address range FFFE0000H to FFFE0FFFH (by default - some\r\n processors permit the APIC to be relocated).\r\n 10 Reserved Reserved\r\n 11 SEP SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT and associated MSRs are supported.\r\n 12 MTRR Memory Type Range Registers. MTRRs are supported. The MTRRcap MSR contains feature bits that describe\r\n what memory types are supported, how many variable MTRRs are supported, and whether fixed MTRRs are\r\n supported.\r\n 13 PGE Page Global Bit. The global bit is supported in paging-structure entries that map a page, indicating TLB entries\r\n that are common to different processes and need not be flushed. The CR4.PGE bit controls this feature.\r\n 14 MCA Machine Check Architecture. A value of 1 indicates the Machine Check Architecture of reporting machine\r\n errors is supported. The MCG_CAP MSR contains feature bits describing how many banks of error reporting\r\n MSRs are supported.\r\n 15 CMOV Conditional Move Instructions. The conditional move instruction CMOV is supported. In addition, if x87 FPU is\r\n present as indicated by the CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported\r\n 16 PAT Page Attribute Table. Page Attribute Table is supported. This feature augments the Memory Type Range\r\n Registers (MTRRs), allowing an operating system to specify attributes of memory accessed through a linear\r\n address on a 4KB granularity.\r\n 17 PSE-36 36-Bit Page Size Extension. 4-MByte pages addressing physical memory beyond 4 GBytes are supported with\r\n 32-bit paging. This feature indicates that upper bits of the physical address of a 4-MByte page are encoded in\r\n bits 20:13 of the page-directory entry. Such physical addresses are limited by MAXPHYADDR and may be up to\r\n 40 bits in size.\r\n 18 PSN Processor Serial Number. The processor supports the 96-bit processor identification number feature and the\r\n feature is enabled.\r\n 19 CLFSH CLFLUSH Instruction. CLFLUSH Instruction is supported.\r\n 20 Reserved Reserved\r\n\r\n\r\n\r\n Table 3-11. More on Feature Information Returned in the EDX Register (Contd.)\r\n Bit # Mnemonic Description\r\n 21 DS Debug Store. The processor supports the ability to write debug information into a memory resident buffer.\r\n This feature is used by the branch trace store (BTS) and precise event-based sampling (PEBS) facilities (see\r\n Chapter 23, \"Introduction to Virtual-Machine Extensions,\" in the Intel 64 and IA-32 Architectures Software\r\n Developer's Manual, Volume 3C).\r\n 22 ACPI Thermal Monitor and Software Controlled Clock Facilities. The processor implements internal MSRs that\r\n allow processor temperature to be monitored and processor performance to be modulated in predefined duty\r\n cycles under software control.\r\n 23 MMX Intel MMX Technology. The processor supports the Intel MMX technology.\r\n 24 FXSR FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR instructions are supported for fast save and\r\n restore of the floating point context. Presence of this bit also indicates that CR4.OSFXSR is available for an\r\n operating system to indicate that it supports the FXSAVE and FXRSTOR instructions.\r\n 25 SSE SSE. The processor supports the SSE extensions.\r\n 26 SSE2 SSE2. The processor supports the SSE2 extensions.\r\n 27 SS Self Snoop. The processor supports the management of conflicting memory types by performing a snoop of its\r\n own cache structure for transactions issued to the bus.\r\n 28 HTT Max APIC IDs reserved field is Valid. A value of 0 for HTT indicates there is only a single logical processor in\r\n the package and software should assume only a single APIC ID is reserved. A value of 1 for HTT indicates the\r\n value in CPUID.1.EBX[23:16] (the Maximum number of addressable IDs for logical processors in this package) is\r\n valid for the package.\r\n 29 TM Thermal Monitor. The processor implements the thermal monitor automatic thermal control circuitry (TCC).\r\n 30 Reserved Reserved\r\n 31 PBE Pending Break Enable. The processor supports the use of the FERR#/PBE# pin when the processor is in the\r\n stop-clock state (STPCLK# is asserted) to signal the processor that an interrupt is pending and that the\r\n processor should return to normal operation to handle the interrupt. Bit 10 (PBE enable) in the\r\n IA32_MISC_ENABLE MSR enables this capability.\r\n\r\n\r\n\r\nINPUT EAX = 02H: TLB/Cache/Prefetch Information Returned in EAX, EBX, ECX, EDX\r\nWhen CPUID executes with EAX set to 02H, the processor returns information about the processor's internal TLBs,\r\ncache and prefetch hardware in the EAX, EBX, ECX, and EDX registers. The information is reported in encoded form\r\nand fall into the following categories:\r\n. The least-significant byte in register EAX (register AL) will always return 01H. Software should ignore this value\r\n and not interpret it as an informational descriptor.\r\n. The most significant bit (bit 31) of each register indicates whether the register contains valid information (set\r\n to 0) or is reserved (set to 1).\r\n. If a register contains valid information, the information is contained in 1 byte descriptors. There are four types\r\n of encoding values for the byte descriptor, the encoding type is noted in the second column of Table 3-12. Table\r\n 3-12 lists the encoding of these descriptors. Note that the order of descriptors in the EAX, EBX, ECX, and EDX\r\n registers is not defined; that is, specific bytes are not designated to contain descriptors for specific cache,\r\n prefetch, or TLB types. The descriptors may appear in any order. Note also a processor may report a general\r\n descriptor type (FFH) and not report any byte descriptor of \"cache type\" via CPUID leaf 2.\r\n\r\n\r\n\r\n\r\n\r\n Table 3-12. Encoding of CPUID Leaf 2 Descriptors\r\n Value Type Description\r\n 00H General Null descriptor, this byte contains no information\r\n 01H TLB Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries\r\n 02H TLB Instruction TLB: 4 MByte pages, fully associative, 2 entries\r\n 03H TLB Data TLB: 4 KByte pages, 4-way set associative, 64 entries\r\n 04H TLB Data TLB: 4 MByte pages, 4-way set associative, 8 entries\r\n 05H TLB Data TLB1: 4 MByte pages, 4-way set associative, 32 entries\r\n 06H Cache 1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size\r\n 08H Cache 1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size\r\n 09H Cache 1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size\r\n 0AH Cache 1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size\r\n 0BH TLB Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\r\n 0CH Cache 1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size\r\n 0DH Cache 1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size\r\n 0EH Cache 1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\r\n 1DH Cache 2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\r\n 21H Cache 2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\r\n 22H Cache 3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector\r\n 23H Cache 3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector\r\n 24H Cache 2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\r\n 25H Cache 3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector\r\n 29H Cache 3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector\r\n 2CH Cache 1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size\r\n 30H Cache 1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size\r\n 40H Cache No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache\r\n 41H Cache 2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size\r\n 42H Cache 2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size\r\n 43H Cache 2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size\r\n 44H Cache 2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size\r\n 45H Cache 2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size\r\n 46H Cache 3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size\r\n 47H Cache 3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size\r\n 48H Cache 2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\r\n 49H Cache 3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model\r\n 06H);\r\n 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size\r\n 4AH Cache 3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\r\n 4BH Cache 3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\r\n 4CH Cache 3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\r\n 4DH Cache 3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\r\n 4EH Cache 2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\r\n 4FH TLB Instruction TLB: 4 KByte pages, 32 entries\r\n\r\n\r\n\r\n\r\n Table 3-12. Encoding of CPUID Leaf 2 Descriptors (Contd.)\r\n Value Type Description\r\n 50H TLB Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries\r\n 51H TLB Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries\r\n 52H TLB Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries\r\n 55H TLB Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\r\n 56H TLB Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\r\n 57H TLB Data TLB0: 4 KByte pages, 4-way associative, 16 entries\r\n 59H TLB Data TLB0: 4 KByte pages, fully associative, 16 entries\r\n 5AH TLB Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries\r\n 5BH TLB Data TLB: 4 KByte and 4 MByte pages, 64 entries\r\n 5CH TLB Data TLB: 4 KByte and 4 MByte pages,128 entries\r\n 5DH TLB Data TLB: 4 KByte and 4 MByte pages,256 entries\r\n 60H Cache 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size\r\n 61H TLB Instruction TLB: 4 KByte pages, fully associative, 48 entries\r\n 63H TLB Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte\r\n pages, 4-way set associative, 4 entries\r\n 64H TLB Data TLB: 4 KByte pages, 4-way set associative, 512 entries\r\n 66H Cache 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size\r\n 67H Cache 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size\r\n 68H Cache 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size\r\n 6AH Cache uTLB: 4 KByte pages, 8-way set associative, 64 entries\r\n 6BH Cache DTLB: 4 KByte pages, 8-way set associative, 256 entries\r\n 6CH Cache DTLB: 2M/4M pages, 8-way set associative, 128 entries\r\n 6DH Cache DTLB: 1 GByte pages, fully associative, 16 entries\r\n 70H Cache Trace cache: 12 K-muop, 8-way set associative\r\n 71H Cache Trace cache: 16 K-muop, 8-way set associative\r\n 72H Cache Trace cache: 32 K-muop, 8-way set associative\r\n 76H TLB Instruction TLB: 2M/4M pages, fully associative, 8 entries\r\n 78H Cache 2nd-level cache: 1 MByte, 4-way set associative, 64byte line size\r\n 79H Cache 2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector\r\n 7AH Cache 2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector\r\n 7BH Cache 2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector\r\n 7CH Cache 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector\r\n 7DH Cache 2nd-level cache: 2 MByte, 8-way set associative, 64byte line size\r\n 7FH Cache 2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size\r\n 80H Cache 2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\r\n 82H Cache 2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size\r\n 83H Cache 2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size\r\n 84H Cache 2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size\r\n 85H Cache 2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size\r\n 86H Cache 2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size\r\n 87H Cache 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size\r\n\r\n\r\n\r\n\r\n Table 3-12. Encoding of CPUID Leaf 2 Descriptors (Contd.)\r\n Value Type Description\r\n A0H DTLB DTLB: 4k pages, fully associative, 32 entries\r\n B0H TLB Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries\r\n B1H TLB Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\r\n B2H TLB Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\r\n B3H TLB Data TLB: 4 KByte pages, 4-way set associative, 128 entries\r\n B4H TLB Data TLB1: 4 KByte pages, 4-way associative, 256 entries\r\n B5H TLB Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\r\n B6H TLB Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\r\n BAH TLB Data TLB1: 4 KByte pages, 4-way associative, 64 entries\r\n C0H TLB Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\r\n C1H STLB Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\r\n C2H DTLB DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\r\n C3H STLB Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way,\r\n 16 entries.\r\n C4H DTLB DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\r\n CAH STLB Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\r\n D0H Cache 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\r\n D1H Cache 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\r\n D2H Cache 3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\r\n D6H Cache 3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\r\n D7H Cache 3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\r\n D8H Cache 3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\r\n DCH Cache 3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\r\n DDH Cache 3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\r\n DEH Cache 3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\r\n E2H Cache 3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\r\n E3H Cache 3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\r\n E4H Cache 3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\r\n EAH Cache 3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\r\n EBH Cache 3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\r\n ECH Cache 3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\r\n F0H Prefetch 64-Byte prefetching\r\n F1H Prefetch 128-Byte prefetching\r\n FFH General CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters\r\n\r\n\r\nExample 3-1. Example of Cache and TLB Interpretation\r\nThe first member of the family of Pentium 4 processors returns the following information about caches and TLBs\r\nwhen the CPUID executes with an input value of 2:\r\n\r\n EAX 66 5B 50 01H\r\n EBX 0H\r\n ECX 0H\r\n EDX 00 7A 70 00H\r\n\r\n\r\n\r\n\r\nWhich means:\r\n. The least-significant byte (byte 0) of register EAX is set to 01H. This value should be ignored.\r\n. The most-significant bit of all four registers (EAX, EBX, ECX, and EDX) is set to 0, indicating that each register\r\n contains valid 1-byte descriptors.\r\n. Bytes 1, 2, and 3 of register EAX indicate that the processor has:\r\n - 50H - a 64-entry instruction TLB, for mapping 4-KByte and 2-MByte or 4-MByte pages.\r\n - 5BH - a 64-entry data TLB, for mapping 4-KByte and 4-MByte pages.\r\n - 66H - an 8-KByte 1st level data cache, 4-way set associative, with a 64-Byte cache line size.\r\n. The descriptors in registers EBX and ECX are valid, but contain NULL descriptors.\r\n. Bytes 0, 1, 2, and 3 of register EDX indicate that the processor has:\r\n - 00H - NULL descriptor.\r\n - 70H - Trace cache: 12 K-muop, 8-way set associative.\r\n - 7AH - a 256-KByte 2nd level cache, 8-way set associative, with a sectored, 64-byte cache line size.\r\n - 00H - NULL descriptor.\r\n\r\nINPUT EAX = 04H: Returns Deterministic Cache Parameters for Each Level\r\nWhen CPUID executes with EAX set to 04H and ECX contains an index value, the processor returns encoded data\r\nthat describe a set of deterministic cache parameters (for the cache level associated with the input in ECX). Valid\r\nindex values start from 0.\r\nSoftware can enumerate the deterministic cache parameters for each level of the cache hierarchy starting with an\r\nindex value of 0, until the parameters report the value associated with the cache type field is 0. The architecturally\r\ndefined fields reported by deterministic cache parameters are documented in Table 3-8.\r\nThis Cache Size in Bytes\r\n= (Ways + 1) * (Partitions + 1) * (Line_Size + 1) * (Sets + 1)\r\n= (EBX[31:22] + 1) * (EBX[21:12] + 1) * (EBX[11:0] + 1) * (ECX + 1)\r\n\r\n\r\nThe CPUID leaf 04H also reports data that can be used to derive the topology of processor cores in a physical\r\npackage. This information is constant for all valid index values. Software can query the raw data reported by\r\nexecuting CPUID with EAX=04H and ECX=0 and use it as part of the topology enumeration algorithm described in\r\nChapter 8, \"Multiple-Processor Management,\" in the Intel 64 and IA-32 Architectures Software Developer's\r\nManual, Volume 3A.\r\n\r\nINPUT EAX = 05H: Returns MONITOR and MWAIT Features\r\nWhen CPUID executes with EAX set to 05H, the processor returns information about features available to\r\nMONITOR/MWAIT instructions. The MONITOR instruction is used for address-range monitoring in conjunction with\r\nMWAIT instruction. The MWAIT instruction optionally provides additional extensions for advanced power manage-\r\nment. See Table 3-8.\r\n\r\nINPUT EAX = 06H: Returns Thermal and Power Management Features\r\nWhen CPUID executes with EAX set to 06H, the processor returns information about thermal and power manage-\r\nment features. See Table 3-8.\r\n\r\nINPUT EAX = 07H: Returns Structured Extended Feature Enumeration Information\r\nWhen CPUID executes with EAX set to 07H and ECX = 0, the processor returns information about the maximum\r\ninput value for sub-leaves that contain extended feature flags. See Table 3-8.\r\nWhen CPUID executes with EAX set to 07H and the input value of ECX is invalid (see leaf 07H entry in Table 3-8),\r\nthe processor returns 0 in EAX/EBX/ECX/EDX. In subleaf 0, EAX returns the maximum input value of the highest\r\nleaf 7 sub-leaf, and EBX, ECX & EDX contain information of extended feature flags.\r\n\r\n\r\n\r\n\r\nINPUT EAX = 09H: Returns Direct Cache Access Information\r\nWhen CPUID executes with EAX set to 09H, the processor returns information about Direct Cache Access capabili-\r\nties. See Table 3-8.\r\n\r\nINPUT EAX = 0AH: Returns Architectural Performance Monitoring Features\r\nWhen CPUID executes with EAX set to 0AH, the processor returns information about support for architectural\r\nperformance monitoring capabilities. Architectural performance monitoring is supported if the version ID (see\r\nTable 3-8) is greater than Pn 0. See Table 3-8.\r\nFor each version of architectural performance monitoring capability, software must enumerate this leaf to discover\r\nthe programming facilities and the architectural performance events available in the processor. The details are\r\ndescribed in Chapter 23, \"Introduction to Virtual-Machine Extensions,\" in the Intel 64 and IA-32 Architectures\r\nSoftware Developer's Manual, Volume 3C.\r\n\r\nINPUT EAX = 0BH: Returns Extended Topology Information\r\nWhen CPUID executes with EAX set to 0BH, the processor returns information about extended topology enumera-\r\ntion data. Software must detect the presence of CPUID leaf 0BH by verifying (a) the highest leaf index supported\r\nby CPUID is >= 0BH, and (b) CPUID.0BH:EBX[15:0] reports a non-zero value. See Table 3-8.\r\n\r\nINPUT EAX = 0DH: Returns Processor Extended States Enumeration Information\r\nWhen CPUID executes with EAX set to 0DH and ECX = 0, the processor returns information about the bit-vector\r\nrepresentation of all processor state extensions that are supported in the processor and storage size requirements\r\nof the XSAVE/XRSTOR area. See Table 3-8.\r\nWhen CPUID executes with EAX set to 0DH and ECX = n (n > 1, and is a valid sub-leaf index), the processor returns\r\ninformation about the size and offset of each processor extended state save area within the XSAVE/XRSTOR area.\r\nSee Table 3-8. Software can use the forward-extendable technique depicted below to query the valid sub-leaves\r\nand obtain size and offset information for each processor extended state save area:\r\n\r\nFor i = 2 to 62 // sub-leaf 1 is reserved\r\n IF (CPUID.(EAX=0DH, ECX=0):VECTOR[i] = 1 ) // VECTOR is the 64-bit value of EDX:EAX\r\n Execute CPUID.(EAX=0DH, ECX = i) to examine size and offset for sub-leaf i;\r\n FI;\r\n\r\nINPUT EAX = 0FH: Returns Intel Resource Director Technology (Intel RDT) Monitoring Enumeration Information\r\nWhen CPUID executes with EAX set to 0FH and ECX = 0, the processor returns information about the bit-vector\r\nrepresentation of QoS monitoring resource types that are supported in the processor and maximum range of RMID\r\nvalues the processor can use to monitor of any supported resource types. Each bit, starting from bit 1, corresponds\r\nto a specific resource type if the bit is set. The bit position corresponds to the sub-leaf index (or ResID) that soft-\r\nware must use to query QoS monitoring capability available for that type. See Table 3-8.\r\nWhen CPUID executes with EAX set to 0FH and ECX = n (n >= 1, and is a valid ResID), the processor returns infor-\r\nmation software can use to program IA32_PQR_ASSOC, IA32_QM_EVTSEL MSRs before reading QoS data from the\r\nIA32_QM_CTR MSR.\r\n\r\nINPUT EAX = 10H: Returns Intel Resource Director Technology (Intel RDT) Allocation Enumeration Information\r\nWhen CPUID executes with EAX set to 10H and ECX = 0, the processor returns information about the bit-vector\r\nrepresentation of QoS Enforcement resource types that are supported in the processor. Each bit, starting from bit\r\n1, corresponds to a specific resource type if the bit is set. The bit position corresponds to the sub-leaf index (or\r\nResID) that software must use to query QoS enforcement capability available for that type. See Table 3-8.\r\nWhen CPUID executes with EAX set to 10H and ECX = n (n >= 1, and is a valid ResID), the processor returns infor-\r\nmation about available classes of service and range of QoS mask MSRs that software can use to configure each\r\nclass of services using capability bit masks in the QoS Mask registers, IA32_resourceType_Mask_n.\r\n\r\n\r\n\r\n\r\n\r\nINPUT EAX = 12H: Returns Intel SGX Enumeration Information\r\nWhen CPUID executes with EAX set to 12H and ECX = 0H, the processor returns information about Intel SGX capa-\r\nbilities. See Table 3-8.\r\nWhen CPUID executes with EAX set to 12H and ECX = 1H, the processor returns information about Intel SGX attri-\r\nbutes. See Table 3-8.\r\nWhen CPUID executes with EAX set to 12H and ECX = n (n > 1), the processor returns information about Intel SGX\r\nEnclave Page Cache. See Table 3-8.\r\n\r\nINPUT EAX = 14H: Returns Intel Processor Trace Enumeration Information\r\nWhen CPUID executes with EAX set to 14H and ECX = 0H, the processor returns information about Intel Processor\r\nTrace extensions. See Table 3-8.\r\nWhen CPUID executes with EAX set to 14H and ECX = n (n > 0 and less than the number of non-zero bits in\r\nCPUID.(EAX=14H, ECX= 0H).EAX), the processor returns information about packet generation in Intel Processor\r\nTrace. See Table 3-8.\r\n\r\nINPUT EAX = 15H: Returns Time Stamp Counter and Nominal Core Crystal Clock Information\r\nWhen CPUID executes with EAX set to 15H and ECX = 0H, the processor returns information about Time Stamp\r\nCounter and Core Crystal Clock. See Table 3-8.\r\n\r\nINPUT EAX = 16H: Returns Processor Frequency Information\r\nWhen CPUID executes with EAX set to 16H, the processor returns information about Processor Frequency Informa-\r\ntion. See Table 3-8.\r\n\r\nINPUT EAX = 17H: Returns System-On-Chip Information\r\nWhen CPUID executes with EAX set to 17H, the processor returns information about the System-On-Chip Vendor\r\nAttribute Enumeration. See Table 3-8.\r\n\r\nMETHODS FOR RETURNING BRANDING INFORMATION\r\nUse the following techniques to access branding information:\r\n1. Processor brand string method.\r\n2. Processor brand index; this method uses a software supplied brand string table.\r\nThese two methods are discussed in the following sections. For methods that are available in early processors, see\r\nSection: \"Identification of Earlier IA-32 Processors\" in Chapter 19 of the Intel 64 and IA-32 Architectures Soft-\r\nware Developer's Manual, Volume 1.\r\n\r\nThe Processor Brand String Method\r\nFigure 3-9 describes the algorithm used for detection of the brand string. Processor brand identification software\r\nshould execute this algorithm on all Intel 64 and IA-32 processors.\r\nThis method (introduced with Pentium 4 processors) returns an ASCII brand identification string and the Processor\r\nBase frequency of the processor to the EAX, EBX, ECX, and EDX registers.\r\n\r\n\r\n\r\n\r\n\r\n Input: EAX=\r\n 0x80000000\r\n\r\n CPUID\r\n\r\n\r\n False Processor Brand\r\n IF (EAX & 0x80000000) String Not\r\n Supported\r\n\r\n\r\n CPUID\r\n True >=\r\n Function\r\n Extended\r\n Supported\r\n\r\n EAX Return Value =\r\n Max. Extended CPUID\r\n Function Index\r\n\r\n\r\n\r\n\r\n True Processor Brand\r\n IF (EAX Return Value\r\n >= 0x80000004) String Supported\r\n\r\n\r\n OM15194\r\n\r\n\r\n\r\n Figure 3-9. Determination of Support for the Processor Brand String\r\n\r\n\r\nHow Brand Strings Work\r\nTo use the brand string method, execute CPUID with EAX input of 8000002H through 80000004H. For each input\r\nvalue, CPUID returns 16 ASCII characters using EAX, EBX, ECX, and EDX. The returned string will be NULL-termi-\r\nnated.\r\n\r\n\r\n\r\n\r\n\r\nTable 3-13 shows the brand string that is returned by the first processor in the Pentium 4 processor family.\r\n\r\n Table 3-13. Processor Brand String Returned with Pentium 4 Processor\r\n EAX Input Value Return Values ASCII Equivalent\r\n 80000002H EAX = 20202020H \" \"\r\n EBX = 20202020H \" \"\r\n ECX = 20202020H \" \"\r\n EDX = 6E492020H \"nI \"\r\n 80000003H EAX = 286C6574H \"(let\"\r\n EBX = 50202952H \"P )R\"\r\n ECX = 69746E65H \"itne\"\r\n EDX = 52286D75H \"R(mu\"\r\n 80000004H EAX = 20342029H \" 4 )\"\r\n EBX = 20555043H \" UPC\"\r\n ECX = 30303531H \"0051\"\r\n EDX = 007A484DH \"\\0zHM\"\r\n\r\n\r\n\r\nExtracting the Processor Frequency from Brand Strings\r\nFigure 3-10 provides an algorithm which software can use to extract the Processor Base frequency from the\r\nprocessor brand string.\r\n\r\n\r\n Scan \"Brand String\" in\r\n Reverse Byte Order\r\n\r\n \"zHM\", or\r\n Match\r\n \"zHG\", or\r\n Substring\r\n \"zHT\"\r\n\r\n\r\n False\r\n IF Substring Matched Report Error\r\n\r\n\r\n\r\n\r\n Determine \"Freq\" True If \"zHM\"\r\n and \"Multiplier\" Multiplier = 1 x 106\r\n\r\n If \"zHG\"\r\n Multiplier = 1 x 109\r\n Determine \"Multiplier\" If \"zHT\"\r\n Multiplier = 1 x 1012\r\n\r\n\r\n Scan Digits\r\n Until Blank Reverse Digits\r\n Determine \"Freq\"\r\n In Reverse Order To Decimal Value\r\n\r\n\r\n\r\n\r\n Processor Base\r\n Frequency =\r\n \"Freq\" = X.YZ if\r\n \"Freq\" x \"Multiplier\"\r\n Digits = \"ZY.X\"\r\n\r\n OM15195\r\n\r\n\r\n Figure 3-10. Algorithm for Extracting Processor Frequency\r\n\r\n\r\n\r\n\r\nThe Processor Brand Index Method\r\nThe brand index method (introduced with Pentium III Xeon processors) provides an entry point into a brand\r\nidentification table that is maintained in memory by system software and is accessible from system- and user-level\r\ncode. In this table, each brand index is associate with an ASCII brand identification string that identifies the official\r\nIntel family and model number of a processor.\r\nWhen CPUID executes with EAX set to 1, the processor returns a brand index to the low byte in EBX. Software can\r\nthen use this index to locate the brand identification string for the processor in the brand identification table. The\r\nfirst entry (brand index 0) in this table is reserved, allowing for backward compatibility with processors that do not\r\nsupport the brand identification feature. Starting with processor signature family ID = 0FH, model = 03H, brand\r\nindex method is no longer supported. Use brand string method instead.\r\nTable 3-14 shows brand indices that have identification strings associated with them.\r\n Table 3-14. Mapping of Brand Indices; and Intel 64 and IA-32 Processor Brand Strings\r\n Brand Index Brand String\r\n 00H This processor does not support the brand identification feature\r\n 01H Intel(R) Celeron(R) processor1\r\n 02H Intel(R) Pentium(R) III processor1\r\n 03H Intel(R) Pentium(R) III Xeon(R) processor; If processor signature = 000006B1h, then Intel(R) Celeron(R)\r\n processor\r\n 04H Intel(R) Pentium(R) III processor\r\n 06H Mobile Intel(R) Pentium(R) III processor-M\r\n 07H Mobile Intel(R) Celeron(R) processor1\r\n 08H Intel(R) Pentium(R) 4 processor\r\n 09H Intel(R) Pentium(R) 4 processor\r\n 0AH Intel(R) Celeron(R) processor1\r\n 0BH Intel(R) Xeon(R) processor; If processor signature = 00000F13h, then Intel(R) Xeon(R) processor MP\r\n 0CH Intel(R) Xeon(R) processor MP\r\n 0EH Mobile Intel(R) Pentium(R) 4 processor-M; If processor signature = 00000F13h, then Intel(R) Xeon(R) processor\r\n 0FH Mobile Intel(R) Celeron(R) processor1\r\n 11H Mobile Genuine Intel(R) processor\r\n 12H Intel(R) Celeron(R) M processor\r\n 13H Mobile Intel(R) Celeron(R) processor1\r\n 14H Intel(R) Celeron(R) processor\r\n 15H Mobile Genuine Intel(R) processor\r\n 16H Intel(R) Pentium(R) M processor\r\n 17H Mobile Intel(R) Celeron(R) processor1\r\n 18H - 0FFH RESERVED\r\n NOTES:\r\n 1. Indicates versions of these processors that were introduced after the Pentium III\r\n\r\nIA-32 Architecture Compatibility\r\nCPUID is not supported in early models of the Intel486 processor or in any IA-32 processor earlier than the\r\nIntel486 processor.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIA32_BIOS_SIGN_ID MSR <- Update with installed microcode revision number;\r\n\r\nCASE (EAX) OF\r\n EAX = 0:\r\n EAX <- Highest basic function input value understood by CPUID;\r\n EBX <- Vendor identification string;\r\n EDX <- Vendor identification string;\r\n ECX <- Vendor identification string;\r\n BREAK;\r\n EAX = 1H:\r\n EAX[3:0] <- Stepping ID;\r\n EAX[7:4] <- Model;\r\n EAX[11:8] <- Family;\r\n EAX[13:12] <- Processor type;\r\n EAX[15:14] <- Reserved;\r\n EAX[19:16] <- Extended Model;\r\n EAX[27:20] <- Extended Family;\r\n EAX[31:28] <- Reserved;\r\n EBX[7:0] <- Brand Index; (* Reserved if the value is zero. *)\r\n EBX[15:8] <- CLFLUSH Line Size;\r\n EBX[16:23] <- Reserved; (* Number of threads enabled = 2 if MT enable fuse set. *)\r\n EBX[24:31] <- Initial APIC ID;\r\n ECX <- Feature flags; (* See Figure 3-7. *)\r\n EDX <- Feature flags; (* See Figure 3-8. *)\r\n BREAK;\r\n EAX = 2H:\r\n EAX <- Cache and TLB information;\r\n EBX <- Cache and TLB information;\r\n ECX <- Cache and TLB information;\r\n EDX <- Cache and TLB information;\r\n BREAK;\r\n EAX = 3H:\r\n EAX <- Reserved;\r\n EBX <- Reserved;\r\n ECX <- ProcessorSerialNumber[31:0];\r\n (* Pentium III processors only, otherwise reserved. *)\r\n EDX <- ProcessorSerialNumber[63:32];\r\n (* Pentium III processors only, otherwise reserved. *\r\n BREAK\r\n EAX = 4H:\r\n EAX <- Deterministic Cache Parameters Leaf; (* See Table 3-8. *)\r\n EBX <- Deterministic Cache Parameters Leaf;\r\n ECX <- Deterministic Cache Parameters Leaf;\r\n EDX <- Deterministic Cache Parameters Leaf;\r\n BREAK;\r\n EAX = 5H:\r\n EAX <- MONITOR/MWAIT Leaf; (* See Table 3-8. *)\r\n EBX <- MONITOR/MWAIT Leaf;\r\n ECX <- MONITOR/MWAIT Leaf;\r\n EDX <- MONITOR/MWAIT Leaf;\r\n BREAK;\r\n\r\n\r\n\r\n\r\n\r\n EAX = 6H:\r\n EAX <- Thermal and Power Management Leaf; (* See Table 3-8. *)\r\n EBX <- Thermal and Power Management Leaf;\r\n ECX <- Thermal and Power Management Leaf;\r\n EDX <- Thermal and Power Management Leaf;\r\n BREAK;\r\n EAX = 7H:\r\n EAX <- Structured Extended Feature Flags Enumeration Leaf; (* See Table 3-8. *)\r\n EBX <- Structured Extended Feature Flags Enumeration Leaf;\r\n ECX <- Structured Extended Feature Flags Enumeration Leaf;\r\n EDX <- Structured Extended Feature Flags Enumeration Leaf;\r\n BREAK;\r\n EAX = 8H:\r\n EAX <- Reserved = 0;\r\n EBX <- Reserved = 0;\r\n ECX <- Reserved = 0;\r\n EDX <- Reserved = 0;\r\n BREAK;\r\n EAX = 9H:\r\n EAX <- Direct Cache Access Information Leaf; (* See Table 3-8. *)\r\n EBX <- Direct Cache Access Information Leaf;\r\n ECX <- Direct Cache Access Information Leaf;\r\n EDX <- Direct Cache Access Information Leaf;\r\n BREAK;\r\n EAX = AH:\r\n EAX <- Architectural Performance Monitoring Leaf; (* See Table 3-8. *)\r\n EBX <- Architectural Performance Monitoring Leaf;\r\n ECX <- Architectural Performance Monitoring Leaf;\r\n EDX <- Architectural Performance Monitoring Leaf;\r\n BREAK\r\n EAX = BH:\r\n EAX <- Extended Topology Enumeration Leaf; (* See Table 3-8. *)\r\n EBX <- Extended Topology Enumeration Leaf;\r\n ECX <- Extended Topology Enumeration Leaf;\r\n EDX <- Extended Topology Enumeration Leaf;\r\n BREAK;\r\n EAX = CH:\r\n EAX <- Reserved = 0;\r\n EBX <- Reserved = 0;\r\n ECX <- Reserved = 0;\r\n EDX <- Reserved = 0;\r\n BREAK;\r\n EAX = DH:\r\n EAX <- Processor Extended State Enumeration Leaf; (* See Table 3-8. *)\r\n EBX <- Processor Extended State Enumeration Leaf;\r\n ECX <- Processor Extended State Enumeration Leaf;\r\n EDX <- Processor Extended State Enumeration Leaf;\r\n BREAK;\r\n EAX = EH:\r\n EAX <- Reserved = 0;\r\n EBX <- Reserved = 0;\r\n ECX <- Reserved = 0;\r\n EDX <- Reserved = 0;\r\n BREAK;\r\n\r\n\r\n\r\n EAX = FH:\r\n EAX <- Intel Resource Director Technology Monitoring Enumeration Leaf; (* See Table 3-8. *)\r\n EBX <- Intel Resource Director Technology Monitoring Enumeration Leaf;\r\n ECX <- Intel Resource Director Technology Monitoring Enumeration Leaf;\r\n EDX <- Intel Resource Director Technology Monitoring Enumeration Leaf;\r\n BREAK;\r\n EAX = 10H:\r\n EAX <- Intel Resource Director Technology Allocation Enumeration Leaf; (* See Table 3-8. *)\r\n EBX <- Intel Resource Director Technology Allocation Enumeration Leaf;\r\n ECX <- Intel Resource Director Technology Allocation Enumeration Leaf;\r\n EDX <- Intel Resource Director Technology Allocation Enumeration Leaf;\r\n BREAK;\r\n EAX = 12H:\r\n EAX <- Intel SGX Enumeration Leaf; (* See Table 3-8. *)\r\n EBX <- Intel SGX Enumeration Leaf;\r\n ECX <- Intel SGX Enumeration Leaf;\r\n EDX <- Intel SGX Enumeration Leaf;\r\n BREAK;\r\n EAX = 14H:\r\n EAX <- Intel Processor Trace Enumeration Leaf; (* See Table 3-8. *)\r\n EBX <- Intel Processor Trace Enumeration Leaf;\r\n ECX <- Intel Processor Trace Enumeration Leaf;\r\n EDX <- Intel Processor Trace Enumeration Leaf;\r\n BREAK;\r\n EAX = 15H:\r\n EAX <- Time Stamp Counter and Nominal Core Crystal Clock Information Leaf; (* See Table 3-8. *)\r\n EBX <- Time Stamp Counter and Nominal Core Crystal Clock Information Leaf;\r\n ECX <- Time Stamp Counter and Nominal Core Crystal Clock Information Leaf;\r\n EDX <- Time Stamp Counter and Nominal Core Crystal Clock Information Leaf;\r\n BREAK;\r\n EAX = 16H:\r\n EAX <- Processor Frequency Information Enumeration Leaf; (* See Table 3-8. *)\r\n EBX <- Processor Frequency Information Enumeration Leaf;\r\n ECX <- Processor Frequency Information Enumeration Leaf;\r\n EDX <- Processor Frequency Information Enumeration Leaf;\r\n BREAK;\r\n EAX = 17H:\r\n EAX <- System-On-Chip Vendor Attribute Enumeration Leaf; (* See Table 3-8. *)\r\n EBX <- System-On-Chip Vendor Attribute Enumeration Leaf;\r\n ECX <- System-On-Chip Vendor Attribute Enumeration Leaf;\r\n EDX <- System-On-Chip Vendor Attribute Enumeration Leaf;\r\n BREAK;\r\n EAX = 80000000H:\r\n EAX <- Highest extended function input value understood by CPUID;\r\n EBX <- Reserved;\r\n ECX <- Reserved;\r\n EDX <- Reserved;\r\n BREAK;\r\n EAX = 80000001H:\r\n EAX <- Reserved;\r\n EBX <- Reserved;\r\n ECX <- Extended Feature Bits (* See Table 3-8.*);\r\n EDX <- Extended Feature Bits (* See Table 3-8. *);\r\n BREAK;\r\n\r\n\r\n\r\n EAX = 80000002H:\r\n EAX <- Processor Brand String;\r\n EBX <- Processor Brand String, continued;\r\n ECX <- Processor Brand String, continued;\r\n EDX <- Processor Brand String, continued;\r\n BREAK;\r\n EAX = 80000003H:\r\n EAX <- Processor Brand String, continued;\r\n EBX <- Processor Brand String, continued;\r\n ECX <- Processor Brand String, continued;\r\n EDX <- Processor Brand String, continued;\r\n BREAK;\r\n EAX = 80000004H:\r\n EAX <- Processor Brand String, continued;\r\n EBX <- Processor Brand String, continued;\r\n ECX <- Processor Brand String, continued;\r\n EDX <- Processor Brand String, continued;\r\n BREAK;\r\n EAX = 80000005H:\r\n EAX <- Reserved = 0;\r\n EBX <- Reserved = 0;\r\n ECX <- Reserved = 0;\r\n EDX <- Reserved = 0;\r\n BREAK;\r\n EAX = 80000006H:\r\n EAX <- Reserved = 0;\r\n EBX <- Reserved = 0;\r\n ECX <- Cache information;\r\n EDX <- Reserved = 0;\r\n BREAK;\r\n EAX = 80000007H:\r\n EAX <- Reserved = 0;\r\n EBX <- Reserved = 0;\r\n ECX <- Reserved = 0;\r\n EDX <- Reserved = Misc Feature Flags;\r\n BREAK;\r\n EAX = 80000008H:\r\n EAX <- Reserved = Physical Address Size Information;\r\n EBX <- Reserved = Virtual Address Size Information;\r\n ECX <- Reserved = 0;\r\n EDX <- Reserved = 0;\r\n BREAK;\r\n EAX >= 40000000H and EAX <= 4FFFFFFFH:\r\n DEFAULT: (* EAX = Value outside of recognized range for CPUID. *)\r\n (* If the highest basic information leaf data depend on ECX input value, ECX is honored.*)\r\n EAX <- Reserved; (* Information returned for highest basic information leaf. *)\r\n EBX <- Reserved; (* Information returned for highest basic information leaf. *)\r\n ECX <- Reserved; (* Information returned for highest basic information leaf. *)\r\n EDX <- Reserved; (* Information returned for highest basic information leaf. *)\r\n BREAK;\r\nESAC;\r\n\r\nFlags Affected\r\nNone.\r\n\r\n\r\n\r\nExceptions (All Operating Modes)\r\n#UD If the LOCK prefix is used.\r\n In earlier IA-32 processors that do not support the CPUID instruction, execution of the instruc-\r\n tion results in an invalid opcode (#UD) exception being generated.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CPUID"
},
{
"description": "-R:CWD",
"mnem": "CQO"
},
{
"description": "CRC32 - Accumulate CRC32 Value\r\nOpcode/ Op/ 64-Bit Compat/ Description\r\nInstruction En Mode Leg Mode\r\nF2 0F 38 F0 /r RM Valid Valid Accumulate CRC32 on r/m8.\r\nCRC32 r32, r/m8\r\nF2 REX 0F 38 F0 /r RM Valid N.E. Accumulate CRC32 on r/m8.\r\nCRC32 r32, r/m8*\r\nF2 0F 38 F1 /r RM Valid Valid Accumulate CRC32 on r/m16.\r\nCRC32 r32, r/m16\r\nF2 0F 38 F1 /r RM Valid Valid Accumulate CRC32 on r/m32.\r\nCRC32 r32, r/m32\r\nF2 REX.W 0F 38 F0 /r RM Valid N.E. Accumulate CRC32 on r/m8.\r\nCRC32 r64, r/m8\r\nF2 REX.W 0F 38 F1 /r RM Valid N.E. Accumulate CRC32 on r/m64.\r\nCRC32 r64, r/m64\r\nNOTES:\r\n*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nStarting with an initial value in the first operand (destination operand), accumulates a CRC32 (polynomial\r\n11EDC6F41H) value for the second operand (source operand) and stores the result in the destination operand. The\r\nsource operand can be a register or a memory location. The destination operand must be an r32 or r64 register. If\r\nthe destination is an r64 register, then the 32-bit result is stored in the least significant double word and\r\n00000000H is stored in the most significant double word of the r64 register.\r\nThe initial value supplied in the destination operand is a double word integer stored in the r32 register or the least\r\nsignificant double word of the r64 register. To incrementally accumulate a CRC32 value, software retains the result\r\nof the previous CRC32 operation in the destination operand, then executes the CRC32 instruction again with new\r\ninput data in the source operand. Data contained in the source operand is processed in reflected bit order. This\r\nmeans that the most significant bit of the source operand is treated as the least significant bit of the quotient, and\r\nso on, for all the bits of the source operand. Likewise, the result of the CRC operation is stored in the destination\r\noperand in reflected bit order. This means that the most significant bit of the resulting CRC (bit 31) is stored in the\r\nleast significant bit of the destination operand (bit 0), and so on, for all the bits of the CRC.\r\n\r\nOperation\r\n\r\nNotes:\r\n BIT_REFLECT64: DST[63-0] = SRC[0-63]\r\n BIT_REFLECT32: DST[31-0] = SRC[0-31]\r\n BIT_REFLECT16: DST[15-0] = SRC[0-15]\r\n BIT_REFLECT8: DST[7-0] = SRC[0-7]\r\n MOD2: Remainder from Polynomial division modulus 2\r\n\r\n\r\n\r\n\r\n\r\nCRC32 instruction for 64-bit source operand and 64-bit destination operand:\r\n\r\n TEMP1[63-0] <- BIT_REFLECT64 (SRC[63-0])\r\n TEMP2[31-0] <- BIT_REFLECT32 (DEST[31-0])\r\n TEMP3[95-0] <- TEMP1[63-0] << 32\r\n TEMP4[95-0] <- TEMP2[31-0] << 64\r\n TEMP5[95-0] <- TEMP3[95-0] XOR TEMP4[95-0]\r\n TEMP6[31-0] <- TEMP5[95-0] MOD2 11EDC6F41H\r\n DEST[31-0] <- BIT_REFLECT (TEMP6[31-0])\r\n DEST[63-32] <- 00000000H\r\nCRC32 instruction for 32-bit source operand and 32-bit destination operand:\r\n\r\n TEMP1[31-0] <- BIT_REFLECT32 (SRC[31-0])\r\n TEMP2[31-0] <- BIT_REFLECT32 (DEST[31-0])\r\n TEMP3[63-0] <- TEMP1[31-0] << 32\r\n TEMP4[63-0] <- TEMP2[31-0] << 32\r\n TEMP5[63-0] <- TEMP3[63-0] XOR TEMP4[63-0]\r\n TEMP6[31-0] <- TEMP5[63-0] MOD2 11EDC6F41H\r\n DEST[31-0] <- BIT_REFLECT (TEMP6[31-0])\r\nCRC32 instruction for 16-bit source operand and 32-bit destination operand:\r\n\r\n TEMP1[15-0] <- BIT_REFLECT16 (SRC[15-0])\r\n TEMP2[31-0] <- BIT_REFLECT32 (DEST[31-0])\r\n TEMP3[47-0] <- TEMP1[15-0] << 32\r\n TEMP4[47-0] <- TEMP2[31-0] << 16\r\n TEMP5[47-0] <- TEMP3[47-0] XOR TEMP4[47-0]\r\n TEMP6[31-0] <- TEMP5[47-0] MOD2 11EDC6F41H\r\n DEST[31-0] <- BIT_REFLECT (TEMP6[31-0])\r\nCRC32 instruction for 8-bit source operand and 64-bit destination operand:\r\n\r\n TEMP1[7-0] <- BIT_REFLECT8(SRC[7-0])\r\n TEMP2[31-0] <- BIT_REFLECT32 (DEST[31-0])\r\n TEMP3[39-0] <- TEMP1[7-0] << 32\r\n TEMP4[39-0] <- TEMP2[31-0] << 8\r\n TEMP5[39-0] <- TEMP3[39-0] XOR TEMP4[39-0]\r\n TEMP6[31-0] <- TEMP5[39-0] MOD2 11EDC6F41H\r\n DEST[31-0] <- BIT_REFLECT (TEMP6[31-0])\r\n DEST[63-32] <- 00000000H\r\nCRC32 instruction for 8-bit source operand and 32-bit destination operand:\r\n\r\n TEMP1[7-0] <- BIT_REFLECT8(SRC[7-0])\r\n TEMP2[31-0] <- BIT_REFLECT32 (DEST[31-0])\r\n TEMP3[39-0] <- TEMP1[7-0] << 32\r\n TEMP4[39-0] <- TEMP2[31-0] << 8\r\n TEMP5[39-0] <- TEMP3[39-0] XOR TEMP4[39-0]\r\n TEMP6[31-0] <- TEMP5[39-0] MOD2 11EDC6F41H\r\n DEST[31-0] <- BIT_REFLECT (TEMP6[31-0])\r\n\r\nFlags Affected\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nunsigned int _mm_crc32_u8( unsigned int crc, unsigned char data )\r\nunsigned int _mm_crc32_u16( unsigned int crc, unsigned short data )\r\nunsigned int _mm_crc32_u32( unsigned int crc, unsigned int data )\r\nunsinged __int64 _mm_crc32_u64( unsinged __int64 crc, unsigned __int64 data )\r\n\r\nSIMD Floating Point Exceptions\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS or GS segments.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF (fault-code) For a page fault.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.\r\n If LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP(0) If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#UD If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.\r\n If LOCK prefix is used.\r\n\r\nVirtual 8086 Mode Exceptions\r\n#GP(0) If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF (fault-code) For a page fault.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.\r\n If LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in Protected Mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#PF (fault-code) For a page fault.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.\r\n If LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CRC32"
},
{
"description": "CVTDQ2PD-Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point\r\nValues\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n F3 0F E6 /r RM V/V SSE2 Convert two packed signed doubleword integers from\r\n CVTDQ2PD xmm1, xmm2/m64 xmm2/mem to two packed double-precision floating-\r\n point values in xmm1.\r\n VEX.128.F3.0F.WIG E6 /r RM V/V AVX Convert two packed signed doubleword integers from\r\n VCVTDQ2PD xmm1, xmm2/m64 xmm2/mem to two packed double-precision floating-\r\n point values in xmm1.\r\n VEX.256.F3.0F.WIG E6 /r RM V/V AVX Convert four packed signed doubleword integers from\r\n VCVTDQ2PD ymm1, xmm2/m128 xmm2/mem to four packed double-precision floating-\r\n point values in ymm1.\r\n EVEX.128.F3.0F.W0 E6 /r HV V/V AVX512VL Convert 2 packed signed doubleword integers from\r\n VCVTDQ2PD xmm1 {k1}{z}, AVX512F xmm2/m128/m32bcst to eight packed double-precision\r\n xmm2/m128/m32bcst floating-point values in xmm1 with writemask k1.\r\n EVEX.256.F3.0F.W0 E6 /r HV V/V AVX512VL Convert 4 packed signed doubleword integers from\r\n VCVTDQ2PD ymm1 {k1}{z}, AVX512F xmm2/m128/m32bcst to 4 packed double-precision\r\n xmm2/m128/m32bcst floating-point values in ymm1 with writemask k1.\r\n EVEX.512.F3.0F.W0 E6 /r HV V/V AVX512F Convert eight packed signed doubleword integers from\r\n VCVTDQ2PD zmm1 {k1}{z}, ymm2/m256/m32bcst to eight packed double-precision\r\n ymm2/m256/m32bcst floating-point values in zmm1 with writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n HV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts two, four or eight packed signed doubleword integers in the source operand (the second operand) to two,\r\nfour or eight packed double-precision floating-point values in the destination operand (the first operand).\r\nEVEX encoded versions: The source operand can be a YMM/XMM/XMM (low 64 bits) register, a 256/128/64-bit\r\nmemory location or a 256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand\r\nis a ZMM/YMM/XMM register conditionally updated with writemask k1. Attempt to encode this instruction with EVEX\r\nembedded rounding is ignored.\r\nVEX.256 encoded version: The source operand is an XMM register or 128- bit memory location. The destination\r\noperand is a YMM register.\r\nVEX.128 encoded version: The source operand is an XMM register or 64- bit memory location. The destination\r\noperand is a XMM register. The upper Bits (MAX_VL-1:128) of the corresponding ZMM register destination are\r\nzeroed.\r\n128-bit Legacy SSE version: The source operand is an XMM register or 64- bit memory location. The destination\r\noperand is an XMM register. The upper Bits (MAX_VL-1:128) of the corresponding ZMM register destination are\r\nunmodified.\r\nVEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\n SRC X3 X2 X1 X0\r\n\r\n\r\n\r\n\r\n DEST X3 X2 X1 X0\r\n\r\n\r\n\r\n Figure 3-11. CVTDQ2PD (VEX.256 encoded version)\r\n\r\n\r\nOperation\r\nVCVTDQ2PD (EVEX encoded versions) when src operand is a register\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n k <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <-\r\n Convert_Integer_To_Double_Precision_Floating_Point(SRC[k+31:k])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVCVTDQ2PD (EVEX encoded versions) when src operand is a memory source\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n k <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])\r\n ELSE\r\n DEST[i+63:i] <-\r\n Convert_Integer_To_Double_Precision_Floating_Point(SRC[k+31:k])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVCVTDQ2PD (VEX.256 encoded version)\r\nDEST[63:0] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])\r\nDEST[127:64] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])\r\nDEST[191:128] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[95:64])\r\nDEST[255:192] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[127:96)\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVCVTDQ2PD (VEX.128 encoded version)\r\nDEST[63:0] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])\r\nDEST[127:64] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nCVTDQ2PD (128-bit Legacy SSE version)\r\nDEST[63:0] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])\r\nDEST[127:64] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])\r\nDEST[MAX_VL-1:128] (unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTDQ2PD __m512d _mm512_cvtepi32_pd( __m256i a);\r\nVCVTDQ2PD __m512d _mm512_mask_cvtepi32_pd( __m512d s, __mmask8 k, __m256i a);\r\nVCVTDQ2PD __m512d _mm512_maskz_cvtepi32_pd( __mmask8 k, __m256i a);\r\nVCVTDQ2PD __m256d _mm256_mask_cvtepi32_pd( __m256d s, __mmask8 k, __m256i a);\r\nVCVTDQ2PD __m256d _mm256_maskz_cvtepi32_pd( __mmask8 k, __m256i a);\r\nVCVTDQ2PD __m128d _mm_mask_cvtepi32_pd( __m128d s, __mmask8 k, __m128i a);\r\nVCVTDQ2PD __m128d _mm_maskz_cvtepi32_pd( __mmask8 k, __m128i a);\r\nCVTDQ2PD __m256d _mm256_cvtepi32_pd (__m128i src)\r\nCVTDQ2PD __m128d _mm_cvtepi32_pd (__m128i src)\r\n\r\n\r\n\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 5;\r\nEVEX-encoded instructions, see Exceptions Type E5.\r\n#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CVTDQ2PD"
},
{
"description": "CVTDQ2PS-Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point\r\nValues\r\n Opcode Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 0F 5B /r RM V/V SSE2 Convert four packed signed doubleword integers from\r\n CVTDQ2PS xmm1, xmm2/m128 xmm2/mem to four packed single-precision floating-\r\n point values in xmm1.\r\n VEX.128.0F.WIG 5B /r RM V/V AVX Convert four packed signed doubleword integers from\r\n VCVTDQ2PS xmm1, xmm2/m128 xmm2/mem to four packed single-precision floating-\r\n point values in xmm1.\r\n VEX.256.0F.WIG 5B /r RM V/V AVX Convert eight packed signed doubleword integers from\r\n VCVTDQ2PS ymm1, ymm2/m256 ymm2/mem to eight packed single-precision floating-\r\n point values in ymm1.\r\n EVEX.128.0F.W0 5B /r FV V/V AVX512VL Convert four packed signed doubleword integers from\r\n VCVTDQ2PS xmm1 {k1}{z}, AVX512F xmm2/m128/m32bcst to four packed single-precision\r\n xmm2/m128/m32bcst floating-point values in xmm1with writemask k1.\r\n EVEX.256.0F.W0 5B /r FV V/V AVX512VL Convert eight packed signed doubleword integers from\r\n VCVTDQ2PS ymm1 {k1}{z}, AVX512F ymm2/m256/m32bcst to eight packed single-precision\r\n ymm2/m256/m32bcst floating-point values in ymm1with writemask k1.\r\n EVEX.512.0F.W0 5B /r FV V/V AVX512F Convert sixteen packed signed doubleword integers\r\n VCVTDQ2PS zmm1 {k1}{z}, from zmm2/m512/m32bcst to sixteen packed single-\r\n zmm2/m512/m32bcst{er} precision floating-point values in zmm1with writemask\r\n k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts four, eight or sixteen packed signed doubleword integers in the source operand to four, eight or sixteen\r\npacked single-precision floating-point values in the destination operand.\r\nEVEX encoded versions: The source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-\r\ntion or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a\r\nZMM/YMM/XMM register conditionally updated with writemask k1.\r\nVEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination\r\noperand is a YMM register. Bits (MAX_VL-1:256) of the corresponding register destination are zeroed.\r\nVEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination\r\noperand is a XMM register. The upper bits (MAX_VL-1:128) of the corresponding register destination are zeroed.\r\n128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination\r\noperand is an XMM register. The upper Bits (MAX_VL-1:128) of the corresponding register destination are unmod-\r\nified.\r\nVEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVCVTDQ2PS (EVEX encoded versions) when SRC operand is a register\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC); ; refer to Table 2-4 in the Intel Architecture Instruction Set Extensions Programming Reference\r\n ELSE\r\n SET_RM(MXCSR.RM); ; refer to Table 2-4 in the Intel Architecture Instruction Set Extensions Programming Reference\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <-\r\n Convert_Integer_To_Single_Precision_Floating_Point(SRC[i+31:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVCVTDQ2PS (EVEX encoded versions) when SRC operand is a memory source\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <-j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])\r\n ELSE\r\n DEST[i+31:i] <-\r\n Convert_Integer_To_Single_Precision_Floating_Point(SRC[i+31:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVCVTDQ2PS (VEX.256 encoded version)\r\nDEST[31:0] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])\r\nDEST[63:32] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])\r\nDEST[95:64] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])\r\nDEST[127:96] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[127:96)\r\nDEST[159:128] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[159:128])\r\nDEST[191:160] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[191:160])\r\nDEST[223:192] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[223:192])\r\nDEST[255:224] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[255:224)\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVCVTDQ2PS (VEX.128 encoded version)\r\nDEST[31:0] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])\r\nDEST[63:32] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])\r\nDEST[95:64] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])\r\nDEST[127:96] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[127z:96)\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nCVTDQ2PS (128-bit Legacy SSE version)\r\nDEST[31:0] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])\r\nDEST[63:32] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])\r\nDEST[95:64] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])\r\nDEST[127:96] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[127z:96)\r\nDEST[MAX_VL-1:128] (unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTDQ2PS __m512 _mm512_cvtepi32_ps( __m512i a);\r\nVCVTDQ2PS __m512 _mm512_mask_cvtepi32_ps( __m512 s, __mmask16 k, __m512i a);\r\nVCVTDQ2PS __m512 _mm512_maskz_cvtepi32_ps( __mmask16 k, __m512i a);\r\nVCVTDQ2PS __m512 _mm512_cvt_roundepi32_ps( __m512i a, int r);\r\nVCVTDQ2PS __m512 _mm512_mask_cvt_roundepi_ps( __m512 s, __mmask16 k, __m512i a, int r);\r\nVCVTDQ2PS __m512 _mm512_maskz_cvt_roundepi32_ps( __mmask16 k, __m512i a, int r);\r\nVCVTDQ2PS __m256 _mm256_mask_cvtepi32_ps( __m256 s, __mmask8 k, __m256i a);\r\nVCVTDQ2PS __m256 _mm256_maskz_cvtepi32_ps( __mmask8 k, __m256i a);\r\nVCVTDQ2PS __m128 _mm_mask_cvtepi32_ps( __m128 s, __mmask8 k, __m128i a);\r\nVCVTDQ2PS __m128 _mm_maskz_cvtepi32_ps( __mmask8 k, __m128i a);\r\nCVTDQ2PS __m256 _mm256_cvtepi32_ps (__m256i src)\r\nCVTDQ2PS __m128 _mm_cvtepi32_ps (__m128i src)\r\n\r\nSIMD Floating-Point Exceptions\r\nPrecision\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2;\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CVTDQ2PS"
},
{
"description": "CVTPD2DQ-Convert Packed Double-Precision Floating-Point Values to Packed Doubleword\r\nIntegers\r\n Opcode Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n F2 0F E6 /r RM V/V SSE2 Convert two packed double-precision floating-point\r\n CVTPD2DQ xmm1, xmm2/m128 values in xmm2/mem to two signed doubleword\r\n integers in xmm1.\r\n VEX.128.F2.0F.WIG E6 /r RM V/V AVX Convert two packed double-precision floating-point\r\n VCVTPD2DQ xmm1, xmm2/m128 values in xmm2/mem to two signed doubleword\r\n integers in xmm1.\r\n VEX.256.F2.0F.WIG E6 /r RM V/V AVX Convert four packed double-precision floating-point\r\n VCVTPD2DQ xmm1, ymm2/m256 values in ymm2/mem to four signed doubleword\r\n integers in xmm1.\r\n EVEX.128.F2.0F.W1 E6 /r FV V/V AVX512VL Convert two packed double-precision floating-point\r\n VCVTPD2DQ xmm1 {k1}{z}, AVX512F values in xmm2/m128/m64bcst to two signed\r\n xmm2/m128/m64bcst doubleword integers in xmm1 subject to writemask k1.\r\n EVEX.256.F2.0F.W1 E6 /r FV V/V AVX512VL Convert four packed double-precision floating-point\r\n VCVTPD2DQ xmm1 {k1}{z}, AVX512F values in ymm2/m256/m64bcst to four signed\r\n ymm2/m256/m64bcst doubleword integers in xmm1 subject to writemask k1.\r\n EVEX.512.F2.0F.W1 E6 /r FV V/V AVX512F Convert eight packed double-precision floating-point\r\n VCVTPD2DQ ymm1 {k1}{z}, values in zmm2/m512/m64bcst to eight signed\r\n zmm2/m512/m64bcst{er} doubleword integers in ymm1 subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts packed double-precision floating-point values in the source operand (second operand) to packed signed\r\ndoubleword integers in the destination operand (first operand).\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR\r\nregister or the embedded rounding control bits. If a converted result cannot be represented in the destination\r\nformat, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value\r\n(2w-1, where w represents the number of bits in the destination format) is returned.\r\nEVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512-bit memory location, or a 512-bit\r\nvector broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register condi-\r\ntionally updated with writemask k1. The upper bits (MAX_VL-1:256/128/64) of the corresponding destination are\r\nzeroed.\r\nVEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination\r\noperand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are\r\nzeroed.\r\nVEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination\r\noperand is a XMM register. The upper bits (MAX_VL-1:64) of the corresponding ZMM register destination are\r\nzeroed.\r\n128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination\r\noperand is an XMM register. Bits[127:64] of the destination XMM register are zeroed. However, the upper bits\r\n(MAX_VL-1:128) of the corresponding ZMM register destination are unmodified.\r\nVEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\n SRC X3 X2 X1 X0\r\n\r\n\r\n\r\n\r\n DEST 0 X3 X2 X1 X0\r\n\r\n\r\n\r\n Figure 3-12. VCVTPD2DQ (VEX.256 encoded version)\r\n\r\n\r\nOperation\r\nVCVTPD2DQ (EVEX encoded versions) when src operand is a register\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n k <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <-\r\n Convert_Double_Precision_Floating_Point_To_Integer(SRC[k+63:k])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL/2] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVCVTPD2DQ (EVEX encoded versions) when src operand is a memory source\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n k <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])\r\n ELSE\r\n DEST[i+31:i] <-\r\n Convert_Double_Precision_Floating_Point_To_Integer(SRC[k+63:k])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL/2] <- 0\r\n\r\nVCVTPD2DQ (VEX.256 encoded version)\r\nDEST[31:0] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])\r\nDEST[63:32] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])\r\nDEST[95:64] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[191:128])\r\nDEST[127:96] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[255:192)\r\nDEST[MAX_VL-1:128]<-0\r\n\r\nVCVTPD2DQ (VEX.128 encoded version)\r\nDEST[31:0] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])\r\nDEST[63:32] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])\r\nDEST[MAX_VL-1:64]<-0\r\n\r\nCVTPD2DQ (128-bit Legacy SSE version)\r\nDEST[31:0] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])\r\nDEST[63:32] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])\r\nDEST[127:64] <-0\r\nDEST[MAX_VL-1:128] (unmodified)\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTPD2DQ __m256i _mm512_cvtpd_epi32( __m512d a);\r\nVCVTPD2DQ __m256i _mm512_mask_cvtpd_epi32( __m256i s, __mmask8 k, __m512d a);\r\nVCVTPD2DQ __m256i _mm512_maskz_cvtpd_epi32( __mmask8 k, __m512d a);\r\nVCVTPD2DQ __m256i _mm512_cvt_roundpd_epi32( __m512d a, int r);\r\nVCVTPD2DQ __m256i _mm512_mask_cvt_roundpd_epi32( __m256i s, __mmask8 k, __m512d a, int r);\r\nVCVTPD2DQ __m256i _mm512_maskz_cvt_roundpd_epi32( __mmask8 k, __m512d a, int r);\r\nVCVTPD2DQ __m128i _mm256_mask_cvtpd_epi32( __m128i s, __mmask8 k, __m256d a);\r\nVCVTPD2DQ __m128i _mm256_maskz_cvtpd_epi32( __mmask8 k, __m256d a);\r\nVCVTPD2DQ __m128i _mm_mask_cvtpd_epi32( __m128i s, __mmask8 k, __m128d a);\r\nVCVTPD2DQ __m128i _mm_maskz_cvtpd_epi32( __mmask8 k, __m128d a);\r\nVCVTPD2DQ __m128i _mm256_cvtpd_epi32 (__m256d src)\r\nCVTPD2DQ __m128i _mm_cvtpd_epi32 (__m128d src)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nSee Exceptions Type 2; additionally\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CVTPD2DQ"
},
{
"description": "CVTPD2PI-Convert Packed Double-Precision FP Values to Packed Dword Integers\r\nOpcode/ Op/ 64-Bit Compat/ Description\r\nInstruction En Mode Leg Mode\r\n66 0F 2D /r RM Valid Valid Convert two packed double-precision floating-\r\nCVTPD2PI mm, xmm/m128 point values from xmm/m128 to two packed\r\n signed doubleword integers in mm.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts two packed double-precision floating-point values in the source operand (second operand) to two packed\r\nsigned doubleword integers in the destination operand (first operand).\r\nThe source operand can be an XMM register or a 128-bit memory location. The destination operand is an MMX tech-\r\nnology register.\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR\r\nregister. If a converted result is larger than the maximum signed doubleword integer, the floating-point invalid\r\nexception is raised, and if this exception is masked, the indefinite integer value (80000000H) is returned.\r\nThis instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack\r\npointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU\r\nfloating-point exception is pending, the exception is handled before the CVTPD2PI instruction is executed.\r\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).\r\n\r\nOperation\r\nDEST[31:0] <- Convert_Double_Precision_Floating_Point_To_Integer32(SRC[63:0]);\r\nDEST[63:32] <- Convert_Double_Precision_Floating_Point_To_Integer32(SRC[127:64]);\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nCVTPD1PI: __m64 _mm_cvtpd_pi32(__m128d a)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision.\r\n\r\nOther Exceptions\r\nSee Table 22-4, \"Exception Conditions for Legacy SIMD/MMX Instructions with FP Exception and 16-Byte Align-\r\nment,\" in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CVTPD2PI"
},
{
"description": "CVTPD2PS-Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision\r\nFloating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0F 5A /r RM V/V SSE2 Convert two packed double-precision floating-point\r\n CVTPD2PS xmm1, xmm2/m128 values in xmm2/mem to two single-precision\r\n floating-point values in xmm1.\r\n VEX.128.66.0F.WIG 5A /r RM V/V AVX Convert two packed double-precision floating-point\r\n VCVTPD2PS xmm1, xmm2/m128 values in xmm2/mem to two single-precision\r\n floating-point values in xmm1.\r\n VEX.256.66.0F.WIG 5A /r RM V/V AVX Convert four packed double-precision floating-point\r\n VCVTPD2PS xmm1, ymm2/m256 values in ymm2/mem to four single-precision\r\n floating-point values in xmm1.\r\n EVEX.128.66.0F.W1 5A /r FV V/V AVX512VL Convert two packed double-precision floating-point\r\n VCVTPD2PS xmm1 {k1}{z}, AVX512F values in xmm2/m128/m64bcst to two single-\r\n xmm2/m128/m64bcst precision floating-point values in xmm1with\r\n writemask k1.\r\n EVEX.256.66.0F.W1 5A /r FV V/V AVX512VL Convert four packed double-precision floating-point\r\n VCVTPD2PS xmm1 {k1}{z}, AVX512F values in ymm2/m256/m64bcst to four single-\r\n ymm2/m256/m64bcst precision floating-point values in xmm1with\r\n writemask k1.\r\n EVEX.512.66.0F.W1 5A /r FV V/V AVX512F Convert eight packed double-precision floating-point\r\n VCVTPD2PS ymm1 {k1}{z}, values in zmm2/m512/m64bcst to eight single-\r\n zmm2/m512/m64bcst{er} precision floating-point values in ymm1with\r\n writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts two, four or eight packed double-precision floating-point values in the source operand (second operand)\r\nto two, four or eight packed single-precision floating-point values in the destination operand (first operand).\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR\r\nregister or the embedded rounding control bits.\r\nEVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or\r\na 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a\r\nYMM/XMM/XMM (low 64-bits) register conditionally updated with writemask k1. The upper bits (MAX_VL-\r\n1:256/128/64) of the corresponding destination are zeroed.\r\nVEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination\r\noperand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are\r\nzeroed.\r\nVEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination\r\noperand is a XMM register. The upper bits (MAX_VL-1:64) of the corresponding ZMM register destination are\r\nzeroed.\r\n128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination\r\noperand is an XMM register. Bits[127:64] of the destination XMM register are zeroed. However, the upper Bits\r\n(MAX_VL-1:128) of the corresponding ZMM register destination are unmodified.\r\nVEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n SRC X3 X2 X1 X0\r\n\r\n\r\n\r\n\r\n DEST 0 X3 X2 X1 X0\r\n\r\n\r\n\r\n Figure 3-13. VCVTPD2PS (VEX.256 encoded version)\r\n\r\n\r\nOperation\r\nVCVTPD2PS (EVEX encoded version) when src operand is a register\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n k <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n DEST[i+31:i] <- Convert_Double_Precision_Floating_Point_To_Single_Precision_Floating_Point(SRC[k+63:k])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL/2] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVCVTPD2PS (EVEX encoded version) when src operand is a memory source\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n k <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-Convert_Double_Precision_Floating_Point_To_Single_Precision_Floating_Point(SRC[63:0])\r\n ELSE\r\n DEST[i+31:i] <- Convert_Double_Precision_Floating_Point_To_Single_Precision_Floating_Point(SRC[k+63:k])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL/2] <- 0\r\n\r\nVCVTPD2PS (VEX.256 encoded version)\r\nDEST[31:0] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0])\r\nDEST[63:32] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[127:64])\r\nDEST[95:64] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[191:128])\r\nDEST[127:96] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[255:192)\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVCVTPD2PS (VEX.128 encoded version)\r\nDEST[31:0] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0])\r\nDEST[63:32] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[127:64])\r\nDEST[MAX_VL-1:64] <- 0\r\n\r\nCVTPD2PS (128-bit Legacy SSE version)\r\nDEST[31:0] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0])\r\nDEST[63:32] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[127:64])\r\nDEST[127:64] <- 0\r\nDEST[MAX_VL-1:128] (unmodified)\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTPD2PS __m256 _mm512_cvtpd_ps( __m512d a);\r\nVCVTPD2PS __m256 _mm512_mask_cvtpd_ps( __m256 s, __mmask8 k, __m512d a);\r\nVCVTPD2PS __m256 _mm512_maskz_cvtpd_ps( __mmask8 k, __m512d a);\r\nVCVTPD2PS __m256 _mm512_cvt_roundpd_ps( __m512d a, int r);\r\nVCVTPD2PS __m256 _mm512_mask_cvt_roundpd_ps( __m256 s, __mmask8 k, __m512d a, int r);\r\nVCVTPD2PS __m256 _mm512_maskz_cvt_roundpd_ps( __mmask8 k, __m512d a, int r);\r\nVCVTPD2PS __m128 _mm256_mask_cvtpd_ps( __m128 s, __mmask8 k, __m256d a);\r\nVCVTPD2PS __m128 _mm256_maskz_cvtpd_ps( __mmask8 k, __m256d a);\r\nVCVTPD2PS __m128 _mm_mask_cvtpd_ps( __m128 s, __mmask8 k, __m128d a);\r\nVCVTPD2PS __m128 _mm_maskz_cvtpd_ps( __mmask8 k, __m128d a);\r\nVCVTPD2PS __m128 _mm256_cvtpd_ps (__m256d a)\r\nCVTPD2PS __m128 _mm_cvtpd_ps (__m128d a)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision, Underflow, Overflow, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2;\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CVTPD2PS"
},
{
"description": "CVTPI2PD-Convert Packed Dword Integers to Packed Double-Precision FP Values\r\nOpcode/ Op/ 64-Bit Compat/ Description\r\nInstruction En Mode Leg Mode\r\n66 0F 2A /r RM Valid Valid Convert two packed signed doubleword\r\nCVTPI2PD xmm, mm/m64* integers from mm/mem64 to two packed\r\n double-precision floating-point values in xmm.\r\nNOTES:\r\n*Operation is different for different operand sets; see the Description section.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts two packed signed doubleword integers in the source operand (second operand) to two packed double-\r\nprecision floating-point values in the destination operand (first operand).\r\nThe source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an\r\nXMM register. In addition, depending on the operand configuration:\r\n. For operands xmm, mm: the instruction causes a transition from x87 FPU to MMX technology operation (that\r\n is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this\r\n instruction is executed while an x87 FPU floating-point exception is pending, the exception is handled before\r\n the CVTPI2PD instruction is executed.\r\n. For operands xmm, m64: the instruction does not cause a transition to MMX technology and does not take\r\n x87 FPU exceptions.\r\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).\r\n\r\nOperation\r\nDEST[63:0] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0]);\r\nDEST[127:64] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32]);\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nCVTPI2PD: __m128d _mm_cvtpi32_pd(__m64 a)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Table 22-6, \"Exception Conditions for Legacy SIMD/MMX Instructions with XMM and without FP Exception,\" in\r\nthe Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CVTPI2PD"
},
{
"description": "CVTPI2PS-Convert Packed Dword Integers to Packed Single-Precision FP Values\r\nOpcode/ Op/ 64-Bit Compat/ Description\r\nInstruction En Mode Leg Mode\r\n0F 2A /r RM Valid Valid Convert two signed doubleword integers\r\nCVTPI2PS xmm, mm/m64 from mm/m64 to two single-precision\r\n floating-point values in xmm.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts two packed signed doubleword integers in the source operand (second operand) to two packed single-\r\nprecision floating-point values in the destination operand (first operand).\r\nThe source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an\r\nXMM register. The results are stored in the low quadword of the destination operand, and the high quadword\r\nremains unchanged. When a conversion is inexact, the value returned is rounded according to the rounding control\r\nbits in the MXCSR register.\r\nThis instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack\r\npointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU\r\nfloating-point exception is pending, the exception is handled before the CVTPI2PS instruction is executed.\r\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).\r\n\r\nOperation\r\nDEST[31:0] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);\r\nDEST[63:32] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32]);\r\n(* High quadword of destination unchanged *)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nCVTPI2PS: __m128 _mm_cvtpi32_ps(__m128 a, __m64 b)\r\n\r\nSIMD Floating-Point Exceptions\r\nPrecision\r\n\r\nOther Exceptions\r\nSee Table 22-5, \"Exception Conditions for Legacy SIMD/MMX Instructions with XMM and FP Exception,\" in the\r\nIntel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CVTPI2PS"
},
{
"description": "CVTPS2DQ-Convert Packed Single-Precision Floating-Point Values to Packed Signed\r\nDoubleword Integer Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0F 5B /r RM V/V SSE2 Convert four packed single-precision floating-point values\r\n CVTPS2DQ xmm1, xmm2/m128 from xmm2/mem to four packed signed doubleword\r\n values in xmm1.\r\n VEX.128.66.0F.WIG 5B /r RM V/V AVX Convert four packed single-precision floating-point values\r\n VCVTPS2DQ xmm1, xmm2/m128 from xmm2/mem to four packed signed doubleword\r\n values in xmm1.\r\n VEX.256.66.0F.WIG 5B /r RM V/V AVX Convert eight packed single-precision floating-point values\r\n VCVTPS2DQ ymm1, ymm2/m256 from ymm2/mem to eight packed signed doubleword\r\n values in ymm1.\r\n EVEX.128.66.0F.W0 5B /r FV V/V AVX512VL Convert four packed single precision floating-point values\r\n VCVTPS2DQ xmm1 {k1}{z}, AVX512F from xmm2/m128/m32bcst to four packed signed\r\n xmm2/m128/m32bcst doubleword values in xmm1 subject to writemask k1.\r\n EVEX.256.66.0F.W0 5B /r FV V/V AVX512VL Convert eight packed single precision floating-point values\r\n VCVTPS2DQ ymm1 {k1}{z}, AVX512F from ymm2/m256/m32bcst to eight packed signed\r\n ymm2/m256/m32bcst doubleword values in ymm1 subject to writemask k1.\r\n EVEX.512.66.0F.W0 5B /r FV V/V AVX512F Convert sixteen packed single-precision floating-point\r\n VCVTPS2DQ zmm1 {k1}{z}, values from zmm2/m512/m32bcst to sixteen packed\r\n zmm2/m512/m32bcst{er} signed doubleword values in zmm1 subject to writemask\r\n k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts four, eight or sixteen packed single-precision floating-point values in the source operand to four, eight or\r\nsixteen signed doubleword integers in the destination operand.\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR\r\nregister or the embedded rounding control bits. If a converted result cannot be represented in the destination\r\nformat, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value\r\n(2w-1, where w represents the number of bits in the destination format) is returned.\r\nEVEX encoded versions: The source operand is a ZMM register, a 512-bit memory location or a 512-bit vector\r\nbroadcasted from a 32-bit memory location. The destination operand is a ZMM register conditionally updated with\r\nwritemask k1.\r\nVEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination\r\noperand is a YMM register. The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination are\r\nzeroed.\r\nVEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination\r\noperand is a XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are\r\nzeroed.\r\n128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination\r\noperand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are\r\nunmodified.\r\nVEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVCVTPS2DQ (encoded versions) when src operand is a register\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <-\r\n Convert_Single_Precision_Floating_Point_To_Integer(SRC[i+31:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVCVTPS2DQ (EVEX encoded versions) when src operand is a memory source\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO 15\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])\r\n ELSE\r\n DEST[i+31:i] <-\r\n Convert_Single_Precision_Floating_Point_To_Integer(SRC[i+31:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVCVTPS2DQ (VEX.256 encoded version)\r\nDEST[31:0] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])\r\nDEST[63:32] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32])\r\nDEST[95:64] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64])\r\nDEST[127:96] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[127:96)\r\nDEST[159:128] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[159:128])\r\nDEST[191:160] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[191:160])\r\nDEST[223:192] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[223:192])\r\nDEST[255:224] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[255:224])\r\n\r\nVCVTPS2DQ (VEX.128 encoded version)\r\nDEST[31:0] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])\r\nDEST[63:32] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32])\r\nDEST[95:64] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64])\r\nDEST[127:96] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[127:96])\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nCVTPS2DQ (128-bit Legacy SSE version)\r\nDEST[31:0] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])\r\nDEST[63:32] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32])\r\nDEST[95:64] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64])\r\nDEST[127:96] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[127:96])\r\nDEST[MAX_VL-1:128] (unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTPS2DQ __m512i _mm512_cvtps_epi32( __m512 a);\r\nVCVTPS2DQ __m512i _mm512_mask_cvtps_epi32( __m512i s, __mmask16 k, __m512 a);\r\nVCVTPS2DQ __m512i _mm512_maskz_cvtps_epi32( __mmask16 k, __m512 a);\r\nVCVTPS2DQ __m512i _mm512_cvt_roundps_epi32( __m512 a, int r);\r\nVCVTPS2DQ __m512i _mm512_mask_cvt_roundps_epi32( __m512i s, __mmask16 k, __m512 a, int r);\r\nVCVTPS2DQ __m512i _mm512_maskz_cvt_roundps_epi32( __mmask16 k, __m512 a, int r);\r\nVCVTPS2DQ __m256i _mm256_mask_cvtps_epi32( __m256i s, __mmask8 k, __m256 a);\r\nVCVTPS2DQ __m256i _mm256_maskz_cvtps_epi32( __mmask8 k, __m256 a);\r\nVCVTPS2DQ __m128i _mm_mask_cvtps_epi32( __m128i s, __mmask8 k, __m128 a);\r\nVCVTPS2DQ __m128i _mm_maskz_cvtps_epi32( __mmask8 k, __m128 a);\r\nVCVTPS2DQ __ m256i _mm256_cvtps_epi32 (__m256 a)\r\nCVTPS2DQ __m128i _mm_cvtps_epi32 (__m128 a)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2;\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CVTPS2DQ"
},
{
"description": "CVTPS2PD-Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision\r\nFloating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 0F 5A /r RM V/V SSE2 Convert two packed single-precision floating-point values in\r\n CVTPS2PD xmm1, xmm2/m64 xmm2/m64 to two packed double-precision floating-point\r\n values in xmm1.\r\n VEX.128.0F.WIG 5A /r RM V/V AVX Convert two packed single-precision floating-point values in\r\n VCVTPS2PD xmm1, xmm2/m64 xmm2/m64 to two packed double-precision floating-point\r\n values in xmm1.\r\n VEX.256.0F.WIG 5A /r RM V/V AVX Convert four packed single-precision floating-point values\r\n VCVTPS2PD ymm1, xmm2/m128 in xmm2/m128 to four packed double-precision floating-\r\n point values in ymm1.\r\n EVEX.128.0F.W0 5A /r HV V/V AVX512VL Convert two packed single-precision floating-point values in\r\n VCVTPS2PD xmm1 {k1}{z}, AVX512F xmm2/m64/m32bcst to packed double-precision floating-\r\n xmm2/m64/m32bcst point values in xmm1 with writemask k1.\r\n EVEX.256.0F.W0 5A /r HV V/V AVX512VL Convert four packed single-precision floating-point values\r\n VCVTPS2PD ymm1 {k1}{z}, in xmm2/m128/m32bcst to packed double-precision\r\n xmm2/m128/m32bcst floating-point values in ymm1 with writemask k1.\r\n EVEX.512.0F.W0 5A /r HV V/V AVX512F Convert eight packed single-precision floating-point values\r\n VCVTPS2PD zmm1 {k1}{z}, in ymm2/m256/b32bcst to eight packed double-precision\r\n ymm2/m256/m32bcst{sae} floating-point values in zmm1 with writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n HV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts two, four or eight packed single-precision floating-point values in the source operand (second operand)\r\nto two, four or eight packed double-precision floating-point values in the destination operand (first operand).\r\nEVEX encoded versions: The source operand is a YMM/XMM/XMM (low 64-bits) register, a 256/128/64-bit memory\r\nlocation or a 256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand is a\r\nZMM/YMM/XMM register conditionally updated with writemask k1.\r\nVEX.256 encoded version: The source operand is an XMM register or 128- bit memory location. The destination\r\noperand is a YMM register. Bits (MAX_VL-1:256) of the corresponding destination ZMM register are zeroed.\r\nVEX.128 encoded version: The source operand is an XMM register or 64- bit memory location. The destination\r\noperand is a XMM register. The upper Bits (MAX_VL-1:128) of the corresponding ZMM register destination are\r\nzeroed.\r\n128-bit Legacy SSE version: The source operand is an XMM register or 64- bit memory location. The destination\r\noperand is an XMM register. The upper Bits (MAX_VL-1:128) of the corresponding ZMM register destination are\r\nunmodified.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\n SRC X3 X2 X1 X0\r\n\r\n\r\n\r\n\r\n DEST X3 X2 X1 X0\r\n\r\n\r\n\r\n\r\n Figure 3-14. CVTPS2PD (VEX.256 encoded version)\r\n\r\n\r\nOperation\r\nVCVTPS2PD (EVEX encoded versions) when src operand is a register\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n k <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <-\r\n Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[k+31:k])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVCVTPS2PD (EVEX encoded versions) when src operand is a memory source\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n k <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])\r\n ELSE\r\n DEST[i+63:i] <-\r\n Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[k+31:k])\r\n FI;\r\n ELSE\r\n\r\n\r\n\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVCVTPS2PD (VEX.256 encoded version)\r\nDEST[63:0] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])\r\nDEST[127:64] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32])\r\nDEST[191:128] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[95:64])\r\nDEST[255:192] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[127:96)\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVCVTPS2PD (VEX.128 encoded version)\r\nDEST[63:0] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])\r\nDEST[127:64] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32])\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nCVTPS2PD (128-bit Legacy SSE version)\r\nDEST[63:0] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])\r\nDEST[127:64] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32])\r\nDEST[MAX_VL-1:128] (unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTPS2PD __m512d _mm512_cvtps_pd( __m256 a);\r\nVCVTPS2PD __m512d _mm512_mask_cvtps_pd( __m512d s, __mmask8 k, __m256 a);\r\nVCVTPS2PD __m512d _mm512_maskz_cvtps_pd( __mmask8 k, __m256 a);\r\nVCVTPS2PD __m512d _mm512_cvt_roundps_pd( __m256 a, int sae);\r\nVCVTPS2PD __m512d _mm512_mask_cvt_roundps_pd( __m512d s, __mmask8 k, __m256 a, int sae);\r\nVCVTPS2PD __m512d _mm512_maskz_cvt_roundps_pd( __mmask8 k, __m256 a, int sae);\r\nVCVTPS2PD __m256d _mm256_mask_cvtps_pd( __m256d s, __mmask8 k, __m128 a);\r\nVCVTPS2PD __m256d _mm256_maskz_cvtps_pd( __mmask8 k, __m128a);\r\nVCVTPS2PD __m128d _mm_mask_cvtps_pd( __m128d s, __mmask8 k, __m128 a);\r\nVCVTPS2PD __m128d _mm_maskz_cvtps_pd( __mmask8 k, __m128 a);\r\nVCVTPS2PD __m256d _mm256_cvtps_pd (__m128 a)\r\nCVTPS2PD __m128d _mm_cvtps_pd (__m128 a)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3;\r\nEVEX-encoded instructions, see Exceptions Type E3.\r\n#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CVTPS2PD"
},
{
"description": "CVTPS2PI-Convert Packed Single-Precision FP Values to Packed Dword Integers\r\n Opcode/ Op/ 64-Bit Compat/ Description\r\n Instruction En Mode Leg Mode\r\n 0F 2D /r RM Valid Valid Convert two packed single-precision floating-\r\n CVTPS2PI mm, xmm/m64 point values from xmm/m64 to two packed\r\n signed doubleword integers in mm.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts two packed single-precision floating-point values in the source operand (second operand) to two packed\r\nsigned doubleword integers in the destination operand (first operand).\r\nThe source operand can be an XMM register or a 128-bit memory location. The destination operand is an MMX tech-\r\nnology register. When the source operand is an XMM register, the two single-precision floating-point values are\r\ncontained in the low quadword of the register. When a conversion is inexact, the value returned is rounded\r\naccording to the rounding control bits in the MXCSR register. If a converted result is larger than the maximum\r\nsigned doubleword integer, the floating-point invalid exception is raised, and if this exception is masked, the indef-\r\ninite integer value (80000000H) is returned.\r\nCVTPS2PI causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack pointer\r\nis set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU floating-\r\npoint exception is pending, the exception is handled before the CVTPS2PI instruction is executed.\r\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).\r\n\r\nOperation\r\nDEST[31:0] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);\r\nDEST[63:32] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32]);\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nCVTPS2PI: __m64 _mm_cvtps_pi32(__m128 a)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nSee Table 22-5, \"Exception Conditions for Legacy SIMD/MMX Instructions with XMM and FP Exception,\" in the\r\nIntel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CVTPS2PI"
},
{
"description": "CVTSD2SI-Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n F2 0F 2D /r RM V/V SSE2 Convert one double-precision floating-point value from\r\n CVTSD2SI r32, xmm1/m64 xmm1/m64 to one signed doubleword integer r32.\r\n F2 REX.W 0F 2D /r RM V/N.E. SSE2 Convert one double-precision floating-point value from\r\n CVTSD2SI r64, xmm1/m64 xmm1/m64 to one signed quadword integer sign-\r\n extended into r64.\r\n VEX.128.F2.0F.W0 2D /r RM V/V AVX Convert one double-precision floating-point value from\r\n VCVTSD2SI r32, xmm1/m64 xmm1/m64 to one signed doubleword integer r32.\r\n VEX.128.F2.0F.W1 2D /r RM V/N.E.1 AVX Convert one double-precision floating-point value from\r\n VCVTSD2SI r64, xmm1/m64 xmm1/m64 to one signed quadword integer sign-\r\n extended into r64.\r\n EVEX.LIG.F2.0F.W0 2D /r T1F V/V AVX512F Convert one double-precision floating-point value from\r\n VCVTSD2SI r32, xmm1/m64{er} xmm1/m64 to one signed doubleword integer r32.\r\n EVEX.LIG.F2.0F.W1 2D /r T1F V/N.E.1 AVX512F Convert one double-precision floating-point value from\r\n VCVTSD2SI r64, xmm1/m64{er} xmm1/m64 to one signed quadword integer sign-\r\n extended into r64.\r\nNOTES:\r\n1. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n T1F ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts a double-precision floating-point value in the source operand (the second operand) to a signed double-\r\nword integer in the destination operand (first operand). The source operand can be an XMM register or a 64-bit\r\nmemory location. The destination operand is a general-purpose register. When the source operand is an XMM\r\nregister, the double-precision floating-point value is contained in the low quadword of the register.\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR\r\nregister.\r\nIf a converted result exceeds the range limits of signed doubleword integer (in non-64-bit modes or 64-bit mode\r\nwith REX.W/VEX.W/EVEX.W=0), the floating-point invalid exception is raised, and if this exception is masked, the\r\nindefinite integer value (80000000H) is returned.\r\nIf a converted result exceeds the range limits of signed quadword integer (in 64-bit mode and\r\nREX.W/VEX.W/EVEX.W = 1), the floating-point invalid exception is raised, and if this exception is masked, the\r\nindefinite integer value (80000000_00000000H) is returned.\r\nLegacy SSE instruction: Use of the REX.W prefix promotes the instruction to produce 64-bit data in 64-bit mode.\r\nSee the summary chart at the beginning of this section for encoding data and limits.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.\r\nSoftware should ensure VCVTSD2SI is encoded with VEX.L=0. Encoding VCVTSD2SI with VEX.L=1 may encounter\r\nunpredictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVCVTSD2SI (EVEX encoded version)\r\nIF SRC *is register* AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF 64-Bit Mode and OperandSize = 64\r\n THEN DEST[63:0] <- Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);\r\n ELSE DEST[31:0] <- Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);\r\nFI\r\n\r\n(V)CVTSD2SI\r\nIF 64-Bit Mode and OperandSize = 64\r\nTHEN\r\n DEST[63:0] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);\r\nELSE\r\n DEST[31:0] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);\r\nFI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTSD2SI int _mm_cvtsd_i32(__m128d);\r\nVCVTSD2SI int _mm_cvt_roundsd_i32(__m128d, int r);\r\nVCVTSD2SI __int64 _mm_cvtsd_i64(__m128d);\r\nVCVTSD2SI __int64 _mm_cvt_roundsd_i64(__m128d, int r);\r\nCVTSD2SI __int64 _mm_cvtsd_si64(__m128d);\r\nCVTSD2SI int _mm_cvtsd_si32(__m128d a)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3;\r\nEVEX-encoded instructions, see Exceptions Type E3NF.\r\n#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CVTSD2SI"
},
{
"description": "CVTSD2SS-Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision\r\nFloating-Point Value\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n F2 0F 5A /r RM V/V SSE2 Convert one double-precision floating-point value in\r\n CVTSD2SS xmm1, xmm2/m64 xmm2/m64 to one single-precision floating-point value\r\n in xmm1.\r\n VEX.NDS.128.F2.0F.WIG 5A /r RVM V/V AVX Convert one double-precision floating-point value in\r\n VCVTSD2SS xmm1,xmm2, xmm3/m64 to one single-precision floating-point value\r\n xmm3/m64 and merge with high bits in xmm2.\r\n EVEX.NDS.LIG.F2.0F.W1 5A /r T1S V/V AVX512F Convert one double-precision floating-point value in\r\n VCVTSD2SS xmm1 {k1}{z}, xmm2, xmm3/m64 to one single-precision floating-point value\r\n xmm3/m64{er} and merge with high bits in xmm2 under writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n T1S ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nConverts a double-precision floating-point value in the \"convert-from\" source operand (the second operand in\r\nSSE2 version, otherwise the third operand) to a single-precision floating-point value in the destination operand.\r\nWhen the \"convert-from\" operand is an XMM register, the double-precision floating-point value is contained in the\r\nlow quadword of the register. The result is stored in the low doubleword of the destination operand. When the\r\nconversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register.\r\n128-bit Legacy SSE version: The \"convert-from\" source operand (the second operand) is an XMM register or\r\nmemory location. Bits (MAX_VL-1:32) of the corresponding destination register remain unchanged. The destina-\r\ntion operand is an XMM register.\r\nVEX.128 and EVEX encoded versions: The \"convert-from\" source operand (the third operand) can be an XMM\r\nregister or a 64-bit memory location. The first source and destination operands are XMM registers. Bits (127:32) of\r\nthe XMM register destination are copied from the corresponding bits in the first source operand. Bits (MAX_VL-\r\n1:128) of the destination register are zeroed.\r\nEVEX encoded version: the converted result in written to the low doubleword element of the destination under the\r\nwritemask.\r\nSoftware should ensure VCVTSD2SS is encoded with VEX.L=0. Encoding VCVTSD2SS with VEX.L=1 may encounter\r\nunpredictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVCVTSD2SS (EVEX encoded version)\r\nIF (SRC2 *is register*) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[31:0] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC2[63:0]);\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[31:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:32] <- SRC1[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVCVTSD2SS (VEX.128 encoded version)\r\nDEST[31:0] <-Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC2[63:0]);\r\nDEST[127:32] <-SRC1[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nCVTSD2SS (128-bit Legacy SSE version)\r\nDEST[31:0] <-Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0]);\r\n(* DEST[MAX_VL-1:32] Unmodified *)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTSD2SS __m128 _mm_mask_cvtsd_ss(__m128 s, __mmask8 k, __m128 a, __m128d b);\r\nVCVTSD2SS __m128 _mm_maskz_cvtsd_ss( __mmask8 k, __m128 a,__m128d b);\r\nVCVTSD2SS __m128 _mm_cvt_roundsd_ss(__m128 a, __m128d b, int r);\r\nVCVTSD2SS __m128 _mm_mask_cvt_roundsd_ss(__m128 s, __mmask8 k, __m128 a, __m128d b, int r);\r\nVCVTSD2SS __m128 _mm_maskz_cvt_roundsd_ss( __mmask8 k, __m128 a,__m128d b, int r);\r\nCVTSD2SS __m128_mm_cvtsd_ss(__m128 a, __m128d b)\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3.\r\nEVEX-encoded instructions, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CVTSD2SS"
},
{
"description": "CVTSI2SD-Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n F2 0F 2A /r RM V/V SSE2 Convert one signed doubleword integer from\r\n CVTSI2SD xmm1, r32/m32 r32/m32 to one double-precision floating-point\r\n value in xmm1.\r\n F2 REX.W 0F 2A /r RM V/N.E. SSE2 Convert one signed quadword integer from r/m64\r\n CVTSI2SD xmm1, r/m64 to one double-precision floating-point value in\r\n xmm1.\r\n VEX.NDS.128.F2.0F.W0 2A /r RVM V/V AVX Convert one signed doubleword integer from\r\n VCVTSI2SD xmm1, xmm2, r/m32 r/m32 to one double-precision floating-point\r\n value in xmm1.\r\n VEX.NDS.128.F2.0F.W1 2A /r RVM V/N.E.1 AVX Convert one signed quadword integer from r/m64\r\n VCVTSI2SD xmm1, xmm2, r/m64 to one double-precision floating-point value in\r\n xmm1.\r\n EVEX.NDS.LIG.F2.0F.W0 2A /r T1S V/V AVX512F Convert one signed doubleword integer from\r\n VCVTSI2SD xmm1, xmm2, r/m32 r/m32 to one double-precision floating-point\r\n value in xmm1.\r\n EVEX.NDS.LIG.F2.0F.W1 2A /r T1S V/N.E.1 AVX512F Convert one signed quadword integer from r/m64\r\n VCVTSI2SD xmm1, xmm2, r/m64{er} to one double-precision floating-point value in\r\n xmm1.\r\nNOTES:\r\n1. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n T1S ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nConverts a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the \"convert-from\"\r\nsource operand to a double-precision floating-point value in the destination operand. The result is stored in the low\r\nquadword of the destination operand, and the high quadword left unchanged. When conversion is inexact, the\r\nvalue returned is rounded according to the rounding control bits in the MXCSR register.\r\nThe second source operand can be a general-purpose register or a 32/64-bit memory location. The first source and\r\ndestination operands are XMM registers.\r\n128-bit Legacy SSE version: Use of the REX.W prefix promotes the instruction to 64-bit operands. The \"convert-\r\nfrom\" source operand (the second operand) is a general-purpose register or memory location. The destination is\r\nan XMM register Bits (MAX_VL-1:64) of the corresponding destination register remain unchanged.\r\nVEX.128 and EVEX encoded versions: The \"convert-from\" source operand (the third operand) can be a general-\r\npurpose register or a memory location. The first source and destination operands are XMM registers. Bits (127:64)\r\nof the XMM register destination are copied from the corresponding bits in the first source operand. Bits (MAX_VL-\r\n1:128) of the destination register are zeroed.\r\nEVEX.W0 version: attempt to encode this instruction with EVEX embedded rounding is ignored.\r\nVEX.W1 and EVEX.W1 versions: promotes the instruction to use 64-bit input value in 64-bit mode.\r\nSoftware should ensure VCVTSI2SD is encoded with VEX.L=0. Encoding VCVTSI2SD with VEX.L=1 may encounter\r\nunpredictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVCVTSI2SD (EVEX encoded version)\r\nIF (SRC2 *is register*) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF 64-Bit Mode And OperandSize = 64\r\nTHEN\r\n DEST[63:0] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC2[63:0]);\r\nELSE\r\n DEST[63:0] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC2[31:0]);\r\nFI;\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVCVTSI2SD (VEX.128 encoded version)\r\nIF 64-Bit Mode And OperandSize = 64\r\nTHEN\r\n DEST[63:0] <-Convert_Integer_To_Double_Precision_Floating_Point(SRC2[63:0]);\r\nELSE\r\n DEST[63:0] <-Convert_Integer_To_Double_Precision_Floating_Point(SRC2[31:0]);\r\nFI;\r\nDEST[127:64] <-SRC1[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nCVTSI2SD\r\nIF 64-Bit Mode And OperandSize = 64\r\nTHEN\r\n DEST[63:0] <-Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:0]);\r\nELSE\r\n DEST[63:0] <-Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0]);\r\nFI;\r\nDEST[MAX_VL-1:64] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTSI2SD __m128d _mm_cvti32_sd(__m128d s, int a);\r\nVCVTSI2SD __m128d _mm_cvt_roundi32_sd(__m128d s, int a, int r);\r\nVCVTSI2SD __m128d _mm_cvti64_sd(__m128d s, __int64 a);\r\nVCVTSI2SD __m128d _mm_cvt_roundi64_sd(__m128d s, __int64 a, int r);\r\nCVTSI2SD __m128d _mm_cvtsi64_sd(__m128d s, __int64 a);\r\nCVTSI2SD __m128d_mm_cvtsi32_sd(__m128d a, int b)\r\n\r\nSIMD Floating-Point Exceptions\r\nPrecision\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3 if W1, else Type 5.\r\nEVEX-encoded instructions, see Exceptions Type E3NF if W1, else Type E10NF.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CVTSI2SD"
},
{
"description": "CVTSI2SS-Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n F3 0F 2A /r RM V/V SSE Convert one signed doubleword integer from r/m32\r\n CVTSI2SS xmm1, r/m32 to one single-precision floating-point value in xmm1.\r\n F3 REX.W 0F 2A /r RM V/N.E. SSE Convert one signed quadword integer from r/m64\r\n CVTSI2SS xmm1, r/m64 to one single-precision floating-point value in xmm1.\r\n VEX.NDS.128.F3.0F.W0 2A /r RVM V/V AVX Convert one signed doubleword integer from r/m32\r\n VCVTSI2SS xmm1, xmm2, r/m32 to one single-precision floating-point value in xmm1.\r\n VEX.NDS.128.F3.0F.W1 2A /r RVM V/N.E.1 AVX Convert one signed quadword integer from r/m64\r\n VCVTSI2SS xmm1, xmm2, r/m64 to one single-precision floating-point value in xmm1.\r\n EVEX.NDS.LIG.F3.0F.W0 2A /r T1S V/V AVX512F Convert one signed doubleword integer from r/m32\r\n VCVTSI2SS xmm1, xmm2, r/m32{er} to one single-precision floating-point value in xmm1.\r\n EVEX.NDS.LIG.F3.0F.W1 2A /r T1S V/N.E.1 AVX512F Convert one signed quadword integer from r/m64\r\n VCVTSI2SS xmm1, xmm2, r/m64{er} to one single-precision floating-point value in xmm1.\r\nNOTES:\r\n1. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n T1S ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nConverts a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the \"convert-from\"\r\nsource operand to a single-precision floating-point value in the destination operand (first operand). The \"convert-\r\nfrom\" source operand can be a general-purpose register or a memory location. The destination operand is an XMM\r\nregister. The result is stored in the low doubleword of the destination operand, and the upper three doublewords\r\nare left unchanged. When a conversion is inexact, the value returned is rounded according to the rounding control\r\nbits in the MXCSR register or the embedded rounding control bits.\r\n128-bit Legacy SSE version: In 64-bit mode, Use of the REX.W prefix promotes the instruction to use 64-bit input\r\nvalue. The \"convert-from\" source operand (the second operand) is a general-purpose register or memory location.\r\nBits (MAX_VL-1:32) of the corresponding destination register remain unchanged.\r\nVEX.128 and EVEX encoded versions: The \"convert-from\" source operand (the third operand) can be a general-\r\npurpose register or a memory location. The first source and destination operands are XMM registers. Bits (127:32)\r\nof the XMM register destination are copied from corresponding bits in the first source operand. Bits (MAX_VL-\r\n1:128) of the destination register are zeroed.\r\nEVEX encoded version: the converted result in written to the low doubleword element of the destination under the\r\nwritemask.\r\nSoftware should ensure VCVTSI2SS is encoded with VEX.L=0. Encoding VCVTSI2SS with VEX.L=1 may encounter\r\nunpredictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVCVTSI2SS (EVEX encoded version)\r\nIF (SRC2 *is register*) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF 64-Bit Mode And OperandSize = 64\r\nTHEN\r\n DEST[31:0] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:0]);\r\nELSE\r\n DEST[31:0] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);\r\nFI;\r\nDEST[127:32] <- SRC1[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVCVTSI2SS (VEX.128 encoded version)\r\nIF 64-Bit Mode And OperandSize = 64\r\nTHEN\r\n DEST[31:0] <-Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:0]);\r\nELSE\r\n DEST[31:0] <-Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);\r\nFI;\r\nDEST[127:32] <-SRC1[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nCVTSI2SS (128-bit Legacy SSE version)\r\nIF 64-Bit Mode And OperandSize = 64\r\nTHEN\r\n DEST[31:0] <-Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:0]);\r\nELSE\r\n DEST[31:0] <-Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);\r\nFI;\r\nDEST[MAX_VL-1:32] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTSI2SS __m128 _mm_cvti32_ss(__m128 s, int a);\r\nVCVTSI2SS __m128 _mm_cvt_roundi32_ss(__m128 s, int a, int r);\r\nVCVTSI2SS __m128 _mm_cvti64_ss(__m128 s, __int64 a);\r\nVCVTSI2SS __m128 _mm_cvt_roundi64_ss(__m128 s, __int64 a, int r);\r\nCVTSI2SS __m128 _mm_cvtsi64_ss(__m128 s, __int64 a);\r\nCVTSI2SS __m128 _mm_cvtsi32_ss(__m128 a, int b);\r\n\r\nSIMD Floating-Point Exceptions\r\nPrecision\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3.\r\nEVEX-encoded instructions, see Exceptions Type E3NF.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CVTSI2SS"
},
{
"description": "CVTSS2SD-Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision\r\nFloating-Point Value\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n F3 0F 5A /r RM V/V SSE2 Convert one single-precision floating-point value in\r\n CVTSS2SD xmm1, xmm2/m32 xmm2/m32 to one double-precision floating-point value\r\n in xmm1.\r\n VEX.NDS.128.F3.0F.WIG 5A /r RVM V/V AVX Convert one single-precision floating-point value in\r\n VCVTSS2SD xmm1, xmm2, xmm3/m32 to one double-precision floating-point value\r\n xmm3/m32 and merge with high bits of xmm2.\r\n EVEX.NDS.LIG.F3.0F.W0 5A /r T1S V/V AVX512F Convert one single-precision floating-point value in\r\n VCVTSS2SD xmm1 {k1}{z}, xmm2, xmm3/m32 to one double-precision floating-point value\r\n xmm3/m32{sae} and merge with high bits of xmm2 under writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n T1S ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nConverts a single-precision floating-point value in the \"convert-from\" source operand to a double-precision\r\nfloating-point value in the destination operand. When the \"convert-from\" source operand is an XMM register, the\r\nsingle-precision floating-point value is contained in the low doubleword of the register. The result is stored in the\r\nlow quadword of the destination operand.\r\n128-bit Legacy SSE version: The \"convert-from\" source operand (the second operand) is an XMM register or\r\nmemory location. Bits (MAX_VL-1:64) of the corresponding destination register remain unchanged. The destina-\r\ntion operand is an XMM register.\r\nVEX.128 and EVEX encoded versions: The \"convert-from\" source operand (the third operand) can be an XMM\r\nregister or a 32-bit memory location. The first source and destination operands are XMM registers. Bits (127:64) of\r\nthe XMM register destination are copied from the corresponding bits in the first source operand. Bits (MAX_VL-\r\n1:128) of the destination register are zeroed.\r\nSoftware should ensure VCVTSS2SD is encoded with VEX.L=0. Encoding VCVTSS2SD with VEX.L=1 may encounter\r\nunpredictable behavior across different processor generations.\r\n\r\nOperation\r\nVCVTSS2SD (EVEX encoded version)\r\nIF k1[0] or *no writemask*\r\n THEN DEST[63:0] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC2[31:0]);\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[63:0] = 0\r\n FI;\r\nFI;\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVCVTSS2SD (VEX.128 encoded version)\r\nDEST[63:0] <-Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC2[31:0])\r\nDEST[127:64] <-SRC1[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nCVTSS2SD (128-bit Legacy SSE version)\r\nDEST[63:0] <-Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0]);\r\nDEST[MAX_VL-1:64] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTSS2SD __m128d _mm_cvt_roundss_sd(__m128d a, __m128 b, int r);\r\nVCVTSS2SD __m128d _mm_mask_cvt_roundss_sd(__m128d s, __mmask8 m, __m128d a,__m128 b, int r);\r\nVCVTSS2SD __m128d _mm_maskz_cvt_roundss_sd(__mmask8 k, __m128d a, __m128 a, int r);\r\nVCVTSS2SD __m128d _mm_mask_cvtss_sd(__m128d s, __mmask8 m, __m128d a,__m128 b);\r\nVCVTSS2SD __m128d _mm_maskz_cvtss_sd(__mmask8 m, __m128d a,__m128 b);\r\nCVTSS2SD __m128d_mm_cvtss_sd(__m128d a, __m128 a);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3.\r\nEVEX-encoded instructions, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CVTSS2SD"
},
{
"description": "CVTSS2SI-Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n F3 0F 2D /r RM V/V SSE Convert one single-precision floating-point value from\r\n CVTSS2SI r32, xmm1/m32 xmm1/m32 to one signed doubleword integer in r32.\r\n F3 REX.W 0F 2D /r RM V/N.E. SSE Convert one single-precision floating-point value from\r\n CVTSS2SI r64, xmm1/m32 xmm1/m32 to one signed quadword integer in r64.\r\n VEX.128.F3.0F.W0 2D /r RM V/V AVX Convert one single-precision floating-point value from\r\n VCVTSS2SI r32, xmm1/m32 xmm1/m32 to one signed doubleword integer in r32.\r\n VEX.128.F3.0F.W1 2D /r RM V/N.E.1 AVX Convert one single-precision floating-point value from\r\n VCVTSS2SI r64, xmm1/m32 xmm1/m32 to one signed quadword integer in r64.\r\n EVEX.LIG.F3.0F.W0 2D /r T1F V/V AVX512F Convert one single-precision floating-point value from\r\n VCVTSS2SI r32, xmm1/m32{er} xmm1/m32 to one signed doubleword integer in r32.\r\n EVEX.LIG.F3.0F.W1 2D /r T1F V/N.E.1 AVX512F Convert one single-precision floating-point value from\r\n VCVTSS2SI r64, xmm1/m32{er} xmm1/m32 to one signed quadword integer in r64.\r\nNOTES:\r\n1. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n T1F ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts a single-precision floating-point value in the source operand (the second operand) to a signed double-\r\nword integer (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand).\r\nThe source operand can be an XMM register or a memory location. The destination operand is a general-purpose\r\nregister. When the source operand is an XMM register, the single-precision floating-point value is contained in the\r\nlow doubleword of the register.\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR\r\nregister or the embedded rounding control bits. If a converted result cannot be represented in the destination\r\nformat, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value\r\n(2w-1, where w represents the number of bits in the destination format) is returned.\r\nLegacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to produce 64-bit data.\r\nSee the summary chart at the beginning of this section for encoding data and limits.\r\nVEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.\r\nSoftware should ensure VCVTSS2SI is encoded with VEX.L=0. Encoding VCVTSS2SI with VEX.L=1 may encounter\r\nunpredictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVCVTSS2SI (EVEX encoded version)\r\nIF (SRC *is register*) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF 64-bit Mode and OperandSize = 64\r\nTHEN\r\n DEST[63:0] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);\r\nELSE\r\n DEST[31:0] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);\r\nFI;\r\n\r\n(V)CVTSS2SI (Legacy and VEX.128 encoded version)\r\nIF 64-bit Mode and OperandSize = 64\r\nTHEN\r\n DEST[63:0] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);\r\nELSE\r\n DEST[31:0] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);\r\nFI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTSS2SI int _mm_cvtss_i32( __m128 a);\r\nVCVTSS2SI int _mm_cvt_roundss_i32( __m128 a, int r);\r\nVCVTSS2SI __int64 _mm_cvtss_i64( __m128 a);\r\nVCVTSS2SI __int64 _mm_cvt_roundss_i64( __m128 a, int r);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3; additionally\r\n#UD If VEX.vvvv != 1111B.\r\nEVEX-encoded instructions, see Exceptions Type E3NF.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CVTSS2SI"
},
{
"description": "CVTTPD2DQ-Convert with Truncation Packed Double-Precision Floating-Point Values to\r\nPacked Doubleword Integers\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0F E6 /r RM V/V SSE2 Convert two packed double-precision floating-point\r\n CVTTPD2DQ xmm1, xmm2/m128 values in xmm2/mem to two signed doubleword\r\n integers in xmm1 using truncation.\r\n VEX.128.66.0F.WIG E6 /r RM V/V AVX Convert two packed double-precision floating-point\r\n VCVTTPD2DQ xmm1, xmm2/m128 values in xmm2/mem to two signed doubleword\r\n integers in xmm1 using truncation.\r\n VEX.256.66.0F.WIG E6 /r RM V/V AVX Convert four packed double-precision floating-point\r\n VCVTTPD2DQ xmm1, ymm2/m256 values in ymm2/mem to four signed doubleword\r\n integers in xmm1 using truncation.\r\n EVEX.128.66.0F.W1 E6 /r FV V/V AVX512VL Convert two packed double-precision floating-point\r\n VCVTTPD2DQ xmm1 {k1}{z}, AVX512F values in xmm2/m128/m64bcst to two signed\r\n xmm2/m128/m64bcst doubleword integers in xmm1 using truncation subject\r\n to writemask k1.\r\n EVEX.256.66.0F.W1 E6 /r FV V/V AVX512VL Convert four packed double-precision floating-point\r\n VCVTTPD2DQ xmm1 {k1}{z}, AVX512F values in ymm2/m256/m64bcst to four signed\r\n ymm2/m256/m64bcst doubleword integers in xmm1 using truncation subject\r\n to writemask k1.\r\n EVEX.512.66.0F.W1 E6 /r FV V/V AVX512F Convert eight packed double-precision floating-point\r\n VCVTTPD2DQ ymm1 {k1}{z}, values in zmm2/m512/m64bcst to eight signed\r\n zmm2/m512/m64bcst{sae} doubleword integers in ymm1 using truncation subject\r\n to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts two, four or eight packed double-precision floating-point values in the source operand (second operand)\r\nto two, four or eight packed signed doubleword integers in the destination operand (first operand).\r\nWhen a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result is larger than\r\nthe maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is\r\nmasked, the indefinite integer value (80000000H) is returned.\r\nEVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or\r\na 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a\r\nYMM/XMM/XMM (low 64 bits) register conditionally updated with writemask k1. The upper bits (MAX_VL-1:256) of\r\nthe corresponding destination are zeroed.\r\nVEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination\r\noperand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are\r\nzeroed.\r\nVEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination\r\noperand is a XMM register. The upper bits (MAX_VL-1:64) of the corresponding ZMM register destination are\r\nzeroed.\r\n128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination\r\noperand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are\r\nunmodified.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\n\r\n\r\n SRC X3 X2 X1 X0\r\n\r\n\r\n\r\n\r\n DEST 0 X3 X2 X1 X0\r\n\r\n\r\n\r\n\r\n Figure 3-15. VCVTTPD2DQ (VEX.256 encoded version)\r\n\r\n\r\nOperation\r\nVCVTTPD2DQ (EVEX encoded versions) when src operand is a register\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n k <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <-\r\n Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[k+63:k])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL/2] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVCVTTPD2DQ (EVEX encoded versions) when src operand is a memory source\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n k <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0])\r\n ELSE\r\n DEST[i+31:i] <-\r\n Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[k+63:k])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL/2] <- 0\r\n\r\nVCVTTPD2DQ (VEX.256 encoded version)\r\nDEST[31:0] <-Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0])\r\nDEST[63:32] <-Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[127:64])\r\nDEST[95:64] <-Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[191:128])\r\nDEST[127:96] <-Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[255:192)\r\nDEST[MAX_VL-1:128]<-0\r\n\r\nVCVTTPD2DQ (VEX.128 encoded version)\r\nDEST[31:0] <-Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0])\r\nDEST[63:32] <-Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[127:64])\r\nDEST[MAX_VL-1:64]<-0\r\n\r\nCVTTPD2DQ (128-bit Legacy SSE version)\r\nDEST[31:0] <-Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0])\r\nDEST[63:32] <-Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[127:64])\r\nDEST[127:64] <-0\r\nDEST[MAX_VL-1:128] (unmodified)\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTTPD2DQ __m256i _mm512_cvttpd_epi32( __m512d a);\r\nVCVTTPD2DQ __m256i _mm512_mask_cvttpd_epi32( __m256i s, __mmask8 k, __m512d a);\r\nVCVTTPD2DQ __m256i _mm512_maskz_cvttpd_epi32( __mmask8 k, __m512d a);\r\nVCVTTPD2DQ __m256i _mm512_cvtt_roundpd_epi32( __m512d a, int sae);\r\nVCVTTPD2DQ __m256i _mm512_mask_cvtt_roundpd_epi32( __m256i s, __mmask8 k, __m512d a, int sae);\r\nVCVTTPD2DQ __m256i _mm512_maskz_cvtt_roundpd_epi32( __mmask8 k, __m512d a, int sae);\r\nVCVTTPD2DQ __m128i _mm256_mask_cvttpd_epi32( __m128i s, __mmask8 k, __m256d a);\r\nVCVTTPD2DQ __m128i _mm256_maskz_cvttpd_epi32( __mmask8 k, __m256d a);\r\nVCVTTPD2DQ __m128i _mm_mask_cvttpd_epi32( __m128i s, __mmask8 k, __m128d a);\r\nVCVTTPD2DQ __m128i _mm_maskz_cvttpd_epi32( __mmask8 k, __m128d a);\r\nVCVTTPD2DQ __m128i _mm256_cvttpd_epi32 (__m256d src);\r\nCVTTPD2DQ __m128i _mm_cvttpd_epi32 (__m128d src);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2;\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CVTTPD2DQ"
},
{
"description": "CVTTPD2PI-Convert with Truncation Packed Double-Precision FP Values to Packed Dword\r\nIntegers\r\n Opcode/ Op/ 64-Bit Compat/ Description\r\n Instruction En Mode Leg Mode\r\n 66 0F 2C /r RM Valid Valid Convert two packer double-precision floating-\r\n CVTTPD2PI mm, xmm/m128 point values from xmm/m128 to two packed\r\n signed doubleword integers in mm using\r\n truncation.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts two packed double-precision floating-point values in the source operand (second operand) to two packed\r\nsigned doubleword integers in the destination operand (first operand). The source operand can be an XMM register\r\nor a 128-bit memory location. The destination operand is an MMX technology register.\r\nWhen a conversion is inexact, a truncated (round toward zero) result is returned. If a converted result is larger\r\nthan the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is\r\nmasked, the indefinite integer value (80000000H) is returned.\r\nThis instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack\r\npointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU\r\nfloating-point exception is pending, the exception is handled before the CVTTPD2PI instruction is executed.\r\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).\r\n\r\nOperation\r\nDEST[31:0] <- Convert_Double_Precision_Floating_Point_To_Integer32_Truncate(SRC[63:0]);\r\nDEST[63:32] <- Convert_Double_Precision_Floating_Point_To_Integer32_\r\n Truncate(SRC[127:64]);\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nCVTTPD1PI: __m64 _mm_cvttpd_pi32(__m128d a)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Mode Exceptions\r\nSee Table 22-4, \"Exception Conditions for Legacy SIMD/MMX Instructions with FP Exception and 16-Byte Align-\r\nment,\" in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CVTTPD2PI"
},
{
"description": "CVTTPS2DQ-Convert with Truncation Packed Single-Precision Floating-Point Values to Packed\r\nSigned Doubleword Integer Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n F3 0F 5B /r RM V/V SSE2 Convert four packed single-precision floating-point\r\n CVTTPS2DQ xmm1, xmm2/m128 values from xmm2/mem to four packed signed\r\n doubleword values in xmm1 using truncation.\r\n VEX.128.F3.0F.WIG 5B /r RM V/V AVX Convert four packed single-precision floating-point\r\n VCVTTPS2DQ xmm1, xmm2/m128 values from xmm2/mem to four packed signed\r\n doubleword values in xmm1 using truncation.\r\n VEX.256.F3.0F.WIG 5B /r RM V/V AVX Convert eight packed single-precision floating-point\r\n VCVTTPS2DQ ymm1, ymm2/m256 values from ymm2/mem to eight packed signed\r\n doubleword values in ymm1 using truncation.\r\n EVEX.128.F3.0F.W0 5B /r FV V/V AVX512VL Convert four packed single precision floating-point\r\n VCVTTPS2DQ xmm1 {k1}{z}, AVX512F values from xmm2/m128/m32bcst to four packed\r\n xmm2/m128/m32bcst signed doubleword values in xmm1 using truncation\r\n subject to writemask k1.\r\n EVEX.256.F3.0F.W0 5B /r FV V/V AVX512VL Convert eight packed single precision floating-point\r\n VCVTTPS2DQ ymm1 {k1}{z}, AVX512F values from ymm2/m256/m32bcst to eight packed\r\n ymm2/m256/m32bcst signed doubleword values in ymm1 using truncation\r\n subject to writemask k1.\r\n EVEX.512.F3.0F.W0 5B /r FV V/V AVX512F Convert sixteen packed single-precision floating-point\r\n VCVTTPS2DQ zmm1 {k1}{z}, values from zmm2/m512/m32bcst to sixteen packed\r\n zmm2/m512/m32bcst {sae} signed doubleword values in zmm1 using truncation\r\n subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts four, eight or sixteen packed single-precision floating-point values in the source operand to four, eight or\r\nsixteen signed doubleword integers in the destination operand.\r\nWhen a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result is larger than\r\nthe maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is\r\nmasked, the indefinite integer value (80000000H) is returned.\r\nEVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or\r\na 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a\r\nZMM/YMM/XMM register conditionally updated with writemask k1.\r\nVEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination\r\noperand is a YMM register. The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination are\r\nzeroed.\r\nVEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination\r\noperand is a XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are\r\nzeroed.\r\n128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination\r\noperand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are\r\nunmodified.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\nOperation\r\nVCVTTPS2DQ (EVEX encoded versions) when src operand is a register\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <-\r\n Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[i+31:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVCVTTPS2DQ (EVEX encoded versions) when src operand is a memory source\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO 15\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0])\r\n ELSE\r\n DEST[i+31:i] <-\r\n Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[i+31:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVCVTTPS2DQ (VEX.256 encoded version)\r\nDEST[31:0] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0])\r\nDEST[63:32] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32])\r\nDEST[95:64] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[95:64])\r\nDEST[127:96] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[127:96)\r\nDEST[159:128] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[159:128])\r\nDEST[191:160] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[191:160])\r\nDEST[223:192] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[223:192])\r\nDEST[255:224] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[255:224])\r\n\r\n\r\n\r\nVCVTTPS2DQ (VEX.128 encoded version)\r\nDEST[31:0] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0])\r\nDEST[63:32] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32])\r\nDEST[95:64] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[95:64])\r\nDEST[127:96] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[127:96])\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nCVTTPS2DQ (128-bit Legacy SSE version)\r\nDEST[31:0] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0])\r\nDEST[63:32] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32])\r\nDEST[95:64] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[95:64])\r\nDEST[127:96] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[127:96])\r\nDEST[MAX_VL-1:128] (unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTTPS2DQ __m512i _mm512_cvttps_epi32( __m512 a);\r\nVCVTTPS2DQ __m512i _mm512_mask_cvttps_epi32( __m512i s, __mmask16 k, __m512 a);\r\nVCVTTPS2DQ __m512i _mm512_maskz_cvttps_epi32( __mmask16 k, __m512 a);\r\nVCVTTPS2DQ __m512i _mm512_cvtt_roundps_epi32( __m512 a, int sae);\r\nVCVTTPS2DQ __m512i _mm512_mask_cvtt_roundps_epi32( __m512i s, __mmask16 k, __m512 a, int sae);\r\nVCVTTPS2DQ __m512i _mm512_maskz_cvtt_roundps_epi32( __mmask16 k, __m512 a, int sae);\r\nVCVTTPS2DQ __m256i _mm256_mask_cvttps_epi32( __m256i s, __mmask8 k, __m256 a);\r\nVCVTTPS2DQ __m256i _mm256_maskz_cvttps_epi32( __mmask8 k, __m256 a);\r\nVCVTTPS2DQ __m128i _mm_mask_cvttps_epi32( __m128i s, __mmask8 k, __m128 a);\r\nVCVTTPS2DQ __m128i _mm_maskz_cvttps_epi32( __mmask8 k, __m128 a);\r\nVCVTTPS2DQ __m256i _mm256_cvttps_epi32 (__m256 a)\r\nCVTTPS2DQ __m128i _mm_cvttps_epi32 (__m128 a)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2; additionally\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CVTTPS2DQ"
},
{
"description": "CVTTPS2PI-Convert with Truncation Packed Single-Precision FP Values to Packed Dword\r\nIntegers\r\n Opcode/ Op/ 64-Bit Compat/ Description\r\n Instruction En Mode Leg Mode\r\n 0F 2C /r RM Valid Valid Convert two single-precision floating-point\r\n CVTTPS2PI mm, xmm/m64 values from xmm/m64 to two signed\r\n doubleword signed integers in mm using\r\n truncation.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts two packed single-precision floating-point values in the source operand (second operand) to two packed\r\nsigned doubleword integers in the destination operand (first operand). The source operand can be an XMM register\r\nor a 64-bit memory location. The destination operand is an MMX technology register. When the source operand is\r\nan XMM register, the two single-precision floating-point values are contained in the low quadword of the register.\r\nWhen a conversion is inexact, a truncated (round toward zero) result is returned. If a converted result is larger\r\nthan the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is\r\nmasked, the indefinite integer value (80000000H) is returned.\r\nThis instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack\r\npointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU\r\nfloating-point exception is pending, the exception is handled before the CVTTPS2PI instruction is executed.\r\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).\r\n\r\nOperation\r\nDEST[31:0] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);\r\nDEST[63:32] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32]);\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nCVTTPS2PI: __m64 _mm_cvttps_pi32(__m128 a)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nSee Table 22-5, \"Exception Conditions for Legacy SIMD/MMX Instructions with XMM and FP Exception,\" in the\r\nIntel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CVTTPS2PI"
},
{
"description": "CVTTSD2SI-Convert with Truncation Scalar Double-Precision Floating-Point Value to Signed\r\nInteger\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n F2 0F 2C /r RM V/V SSE2 Convert one double-precision floating-point value from\r\n CVTTSD2SI r32, xmm1/m64 xmm1/m64 to one signed doubleword integer in r32\r\n using truncation.\r\n F2 REX.W 0F 2C /r RM V/N.E. SSE2 Convert one double-precision floating-point value from\r\n CVTTSD2SI r64, xmm1/m64 xmm1/m64 to one signed quadword integer in r64\r\n using truncation.\r\n VEX.128.F2.0F.W0 2C /r RM V/V AVX Convert one double-precision floating-point value from\r\n VCVTTSD2SI r32, xmm1/m64 xmm1/m64 to one signed doubleword integer in r32\r\n using truncation.\r\n VEX.128.F2.0F.W1 2C /r T1F V/N.E.1 AVX Convert one double-precision floating-point value from\r\n VCVTTSD2SI r64, xmm1/m64 xmm1/m64 to one signed quadword integer in r64\r\n using truncation.\r\n EVEX.LIG.F2.0F.W0 2C /r T1F V/V AVX512F Convert one double-precision floating-point value from\r\n VCVTTSD2SI r32, xmm1/m64{sae} xmm1/m64 to one signed doubleword integer in r32\r\n using truncation.\r\n EVEX.LIG.F2.0F.W1 2C /r T1F V/N.E.1 AVX512F Convert one double-precision floating-point value from\r\n VCVTTSD2SI r64, xmm1/m64{sae} xmm1/m64 to one signed quadword integer in r64\r\n using truncation.\r\nNOTES:\r\n1. For this specific instruction, VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 ver-\r\n sion is used.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n T1F ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts a double-precision floating-point value in the source operand (the second operand) to a signed double-\r\nword integer (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand).\r\nThe source operand can be an XMM register or a 64-bit memory location. The destination operand is a general\r\npurpose register. When the source operand is an XMM register, the double-precision floating-point value is\r\ncontained in the low quadword of the register.\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR\r\nregister.\r\nIf a converted result exceeds the range limits of signed doubleword integer (in non-64-bit modes or 64-bit mode\r\nwith REX.W/VEX.W/EVEX.W=0), the floating-point invalid exception is raised, and if this exception is masked, the\r\nindefinite integer value (80000000H) is returned.\r\nIf a converted result exceeds the range limits of signed quadword integer (in 64-bit mode and\r\nREX.W/VEX.W/EVEX.W = 1), the floating-point invalid exception is raised, and if this exception is masked, the\r\nindefinite integer value (80000000_00000000H) is returned.\r\nLegacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to 64-bit operation. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\nVEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\nSoftware should ensure VCVTTSD2SI is encoded with VEX.L=0. Encoding VCVTTSD2SI with VEX.L=1 may\r\nencounter unpredictable behavior across different processor generations.\r\n\r\nOperation\r\n(V)CVTTSD2SI (All versions)\r\nIF 64-Bit Mode and OperandSize = 64\r\nTHEN\r\n DEST[63:0] <- Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0]);\r\nELSE\r\n DEST[31:0] <- Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0]);\r\nFI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTTSD2SI int _mm_cvttsd_i32( __m128d a);\r\nVCVTTSD2SI int _mm_cvtt_roundsd_i32( __m128d a, int sae);\r\nVCVTTSD2SI __int64 _mm_cvttsd_i64( __m128d a);\r\nVCVTTSD2SI __int64 _mm_cvtt_roundsd_i64( __m128d a, int sae);\r\nCVTTSD2SI int _mm_cvttsd_si32( __m128d a);\r\nCVTTSD2SI __int64 _mm_cvttsd_si64( __m128d a);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3; additionally\r\n#UD If VEX.vvvv != 1111B.\r\nEVEX-encoded instructions, see Exceptions Type E3NF.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CVTTSD2SI"
},
{
"description": "CVTTSS2SI-Convert with Truncation Scalar Single-Precision Floating-Point Value to Integer\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n F3 0F 2C /r RM V/V SSE Convert one single-precision floating-point value from\r\n CVTTSS2SI r32, xmm1/m32 xmm1/m32 to one signed doubleword integer in r32\r\n using truncation.\r\n F3 REX.W 0F 2C /r RM V/N.E. SSE Convert one single-precision floating-point value from\r\n CVTTSS2SI r64, xmm1/m32 xmm1/m32 to one signed quadword integer in r64\r\n using truncation.\r\n VEX.128.F3.0F.W0 2C /r RM V/V AVX Convert one single-precision floating-point value from\r\n VCVTTSS2SI r32, xmm1/m32 xmm1/m32 to one signed doubleword integer in r32\r\n using truncation.\r\n VEX.128.F3.0F.W1 2C /r RM V/N.E.1 AVX Convert one single-precision floating-point value from\r\n VCVTTSS2SI r64, xmm1/m32 xmm1/m32 to one signed quadword integer in r64\r\n using truncation.\r\n EVEX.LIG.F3.0F.W0 2C /r T1F V/V AVX512F Convert one single-precision floating-point value from\r\n VCVTTSS2SI r32, xmm1/m32{sae} xmm1/m32 to one signed doubleword integer in r32\r\n using truncation.\r\n EVEX.LIG.F3.0F.W1 2C /r T1F V/N.E.1 AVX512F Convert one single-precision floating-point value from\r\n VCVTTSS2SI r64, xmm1/m32{sae} xmm1/m32 to one signed quadword integer in r64\r\n using truncation.\r\nNOTES:\r\n1. For this specific instruction, VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 ver-\r\n sion is used.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n T1F ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts a single-precision floating-point value in the source operand (the second operand) to a signed doubleword\r\ninteger (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand). The\r\nsource operand can be an XMM register or a 32-bit memory location. The destination operand is a general purpose\r\nregister. When the source operand is an XMM register, the single-precision floating-point value is contained in the\r\nlow doubleword of the register.\r\nWhen a conversion is inexact, a truncated (round toward zero) result is returned. If a converted result is larger than\r\nthe maximum signed doubleword integer, the floating-point invalid exception is raised. If this exception is masked,\r\nthe indefinite integer value (80000000H or 80000000_00000000H if operand size is 64 bits) is returned.\r\nLegacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to 64-bit operation. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\nVEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.\r\nSoftware should ensure VCVTTSS2SI is encoded with VEX.L=0. Encoding VCVTTSS2SI with VEX.L=1 may\r\nencounter unpredictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\n(V)CVTTSS2SI (All versions)\r\nIF 64-Bit Mode and OperandSize = 64\r\nTHEN\r\n DEST[63:0] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);\r\nELSE\r\n DEST[31:0] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);\r\nFI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTTSS2SI int _mm_cvttss_i32( __m128 a);\r\nVCVTTSS2SI int _mm_cvtt_roundss_i32( __m128 a, int sae);\r\nVCVTTSS2SI __int64 _mm_cvttss_i64( __m128 a);\r\nVCVTTSS2SI __int64 _mm_cvtt_roundss_i64( __m128 a, int sae);\r\nCVTTSS2SI int _mm_cvttss_si32( __m128 a);\r\nCVTTSS2SI __int64 _mm_cvttss_si64( __m128 a);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nSee Exceptions Type 3; additionally\r\n#UD If VEX.vvvv != 1111B.\r\nEVEX-encoded instructions, see Exceptions Type E3NF.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CVTTSS2SI"
},
{
"description": "CWD/CDQ/CQO-Convert Word to Doubleword/Convert Doubleword to Quadword\r\nOpcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n99 CWD NP Valid Valid DX:AX <- sign-extend of AX.\r\n99 CDQ NP Valid Valid EDX:EAX <- sign-extend of EAX.\r\nREX.W + 99 CQO NP Valid N.E. RDX:RAX<- sign-extend of RAX.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nDoubles the size of the operand in register AX, EAX, or RAX (depending on the operand size) by means of sign\r\nextension and stores the result in registers DX:AX, EDX:EAX, or RDX:RAX, respectively. The CWD instruction\r\ncopies the sign (bit 15) of the value in the AX register into every bit position in the DX register. The CDQ instruction\r\ncopies the sign (bit 31) of the value in the EAX register into every bit position in the EDX register. The CQO instruc-\r\ntion (available in 64-bit mode only) copies the sign (bit 63) of the value in the RAX register into every bit position\r\nin the RDX register.\r\nThe CWD instruction can be used to produce a doubleword dividend from a word before word division. The CDQ\r\ninstruction can be used to produce a quadword dividend from a doubleword before doubleword division. The CQO\r\ninstruction can be used to produce a double quadword dividend from a quadword before a quadword division.\r\nThe CWD and CDQ mnemonics reference the same opcode. The CWD instruction is intended for use when the\r\noperand-size attribute is 16 and the CDQ instruction for when the operand-size attribute is 32. Some assemblers\r\nmay force the operand size to 16 when CWD is used and to 32 when CDQ is used. Others may treat these\r\nmnemonics as synonyms (CWD/CDQ) and use the current setting of the operand-size attribute to determine the\r\nsize of values to be converted, regardless of the mnemonic used.\r\nIn 64-bit mode, use of the REX.W prefix promotes operation to 64 bits. The CQO mnemonics reference the same\r\nopcode as CWD/CDQ. See the summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\n\r\nIF OperandSize = 16 (* CWD instruction *)\r\n THEN\r\n DX <- SignExtend(AX);\r\n ELSE IF OperandSize = 32 (* CDQ instruction *)\r\n EDX <- SignExtend(EAX); FI;\r\n ELSE IF 64-Bit Mode and OperandSize = 64 (* CQO instruction*)\r\n RDX <- SignExtend(RAX); FI;\r\nFI;\r\n\r\nFlags Affected\r\nNone\r\n\r\nExceptions (All Operating Modes)\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "CWD"
},
{
"description": "-R:CBW",
"mnem": "CWDE"
},
{
"description": "DAA-Decimal Adjust AL after Addition\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 27 DAA NP Invalid Valid Decimal adjust AL after addition.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nAdjusts the sum of two packed BCD values to create a packed BCD result. The AL register is the implied source and\r\ndestination operand. The DAA instruction is only useful when it follows an ADD instruction that adds (binary addi-\r\ntion) two 2-digit, packed BCD values and stores a byte result in the AL register. The DAA instruction then adjusts\r\nthe contents of the AL register to contain the correct 2-digit, packed BCD result. If a decimal carry is detected, the\r\nCF and AF flags are set accordingly.\r\nThis instruction executes as described above in compatibility mode and legacy mode. It is not valid in 64-bit mode.\r\n\r\nOperation\r\nIF 64-Bit Mode\r\n THEN\r\n #UD;\r\n ELSE\r\n old_AL <- AL;\r\n old_CF <- CF;\r\n CF <- 0;\r\n IF (((AL AND 0FH) > 9) or AF = 1)\r\n THEN\r\n AL <- AL + 6;\r\n CF <- old_CF or (Carry from AL <- AL + 6);\r\n AF <- 1;\r\n ELSE\r\n AF <- 0;\r\n FI;\r\n IF ((old_AL > 99H) or (old_CF = 1))\r\n THEN\r\n AL <- AL + 60H;\r\n CF <- 1;\r\n ELSE\r\n CF <- 0;\r\n FI;\r\nFI;\r\n\r\nExample\r\nADD AL, BL Before: AL=79H BL=35H EFLAGS(OSZAPC)=XXXXXX\r\n After: AL=AEH BL=35H EFLAGS(0SZAPC)=110000\r\nDAA Before: AL=AEH BL=35H EFLAGS(OSZAPC)=110000\r\n After: AL=14H BL=35H EFLAGS(0SZAPC)=X00111\r\nDAA Before: AL=2EH BL=35H EFLAGS(OSZAPC)=110000\r\n After: AL=34H BL=35H EFLAGS(0SZAPC)=X00101\r\n\r\n\r\n\r\n\r\n\r\nFlags Affected\r\nThe CF and AF flags are set if the adjustment of the value results in a decimal carry in either digit of the result (see\r\nthe \"Operation\" section above). The SF, ZF, and PF flags are set according to the result. The OF flag is undefined.\r\n\r\nProtected Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\n64-Bit Mode Exceptions\r\n#UD If in 64-bit mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "DAA"
},
{
"description": "DAS-Decimal Adjust AL after Subtraction\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 2F DAS NP Invalid Valid Decimal adjust AL after subtraction.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nAdjusts the result of the subtraction of two packed BCD values to create a packed BCD result. The AL register is the\r\nimplied source and destination operand. The DAS instruction is only useful when it follows a SUB instruction that\r\nsubtracts (binary subtraction) one 2-digit, packed BCD value from another and stores a byte result in the AL\r\nregister. The DAS instruction then adjusts the contents of the AL register to contain the correct 2-digit, packed BCD\r\nresult. If a decimal borrow is detected, the CF and AF flags are set accordingly.\r\nThis instruction executes as described above in compatibility mode and legacy mode. It is not valid in 64-bit mode.\r\n\r\nOperation\r\nIF 64-Bit Mode\r\n THEN\r\n #UD;\r\n ELSE\r\n old_AL <- AL;\r\n old_CF <- CF;\r\n CF <- 0;\r\n IF (((AL AND 0FH) > 9) or AF = 1)\r\n THEN\r\n AL <- AL - 6;\r\n CF <- old_CF or (Borrow from AL <- AL - 6);\r\n AF <- 1;\r\n ELSE\r\n AF <- 0;\r\n FI;\r\n IF ((old_AL > 99H) or (old_CF = 1))\r\n THEN\r\n AL <- AL - 60H;\r\n CF <- 1;\r\n FI;\r\nFI;\r\n\r\nExample\r\nSUB AL, BL Before: AL = 35H, BL = 47H, EFLAGS(OSZAPC) = XXXXXX\r\n After: AL = EEH, BL = 47H, EFLAGS(0SZAPC) = 010111\r\nDAA Before: AL = EEH, BL = 47H, EFLAGS(OSZAPC) = 010111\r\n After: AL = 88H, BL = 47H, EFLAGS(0SZAPC) = X10111\r\n\r\nFlags Affected\r\nThe CF and AF flags are set if the adjustment of the value results in a decimal borrow in either digit of the result\r\n(see the \"Operation\" section above). The SF, ZF, and PF flags are set according to the result. The OF flag is unde-\r\nfined.\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\n64-Bit Mode Exceptions\r\n#UD If in 64-bit mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "DAS"
},
{
"description": "DEC-Decrement by 1\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n FE /1 DEC r/m8 M Valid Valid Decrement r/m8 by 1.\r\n *\r\n REX + FE /1 DEC r/m8 M Valid N.E. Decrement r/m8 by 1.\r\n FF /1 DEC r/m16 M Valid Valid Decrement r/m16 by 1.\r\n FF /1 DEC r/m32 M Valid Valid Decrement r/m32 by 1.\r\n REX.W + FF /1 DEC r/m64 M Valid N.E. Decrement r/m64 by 1.\r\n 48+rw DEC r16 O N.E. Valid Decrement r16 by 1.\r\n 48+rd DEC r32 O N.E. Valid Decrement r32 by 1.\r\n NOTES:\r\n * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (r, w) NA NA NA\r\n O opcode + rd (r, w) NA NA NA\r\n\r\nDescription\r\nSubtracts 1 from the destination operand, while preserving the state of the CF flag. The destination operand can be\r\na register or a memory location. This instruction allows a loop counter to be updated without disturbing the CF flag.\r\n(To perform a decrement operation that updates the CF flag, use a SUB instruction with an immediate operand of\r\n1.)\r\nThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.\r\nIn 64-bit mode, DEC r16 and DEC r32 are not encodable (because opcodes 48H through 4FH are REX prefixes).\r\nOtherwise, the instruction's 64-bit mode default operation size is 32 bits. Use of the REX.R prefix permits access to\r\nadditional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits.\r\nSee the summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nDEST <- DEST - 1;\r\n\r\nFlags Affected\r\nThe CF flag is not affected. The OF, SF, ZF, AF, and PF flags are set according to the result.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination operand is located in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n",
"mnem": "DEC"
},
{
"description": "DIV-Unsigned Divide\r\nOpcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\nF6 /6 DIV r/m8 M Valid Valid Unsigned divide AX by r/m8, with result\r\n stored in AL <- Quotient, AH <- Remainder.\r\nREX + F6 /6 DIV r/m8* M Valid N.E. Unsigned divide AX by r/m8, with result\r\n stored in AL <- Quotient, AH <- Remainder.\r\nF7 /6 DIV r/m16 M Valid Valid Unsigned divide DX:AX by r/m16, with result\r\n stored in AX <- Quotient, DX <- Remainder.\r\nF7 /6 DIV r/m32 M Valid Valid Unsigned divide EDX:EAX by r/m32, with\r\n result stored in EAX <- Quotient, EDX <-\r\n Remainder.\r\nREX.W + F7 /6 DIV r/m64 M Valid N.E. Unsigned divide RDX:RAX by r/m64, with\r\n result stored in RAX <- Quotient, RDX <-\r\n Remainder.\r\nNOTES:\r\n* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (w) NA NA NA\r\n\r\nDescription\r\nDivides unsigned the value in the AX, DX:AX, EDX:EAX, or RDX:RAX registers (dividend) by the source operand\r\n(divisor) and stores the result in the AX (AH:AL), DX:AX, EDX:EAX, or RDX:RAX registers. The source operand can\r\nbe a general-purpose register or a memory location. The action of this instruction depends on the operand size\r\n(dividend/divisor). Division using 64-bit operand is available only in 64-bit mode.\r\nNon-integral results are truncated (chopped) towards 0. The remainder is always less than the divisor in magni-\r\ntude. Overflow is indicated with the #DE (divide error) exception rather than with the CF flag.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-\r\ntional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. In 64-bit mode when REX.W is\r\napplied, the instruction divides the unsigned value in RDX:RAX by the source operand and stores the quotient in\r\nRAX, the remainder in RDX.\r\nSee the summary chart at the beginning of this section for encoding data and limits. See Table 3-15.\r\n Table 3-15. DIV Action\r\n Maximum\r\n Operand Size Dividend Divisor Quotient Remainder Quotient\r\n Word/byte AX r/m8 AL AH 255\r\n Doubleword/word DX:AX r/m16 AX DX 65,535\r\n Quadword/doubleword EDX:EAX r/m32 EAX EDX 232 - 1\r\n Doublequadword/ RDX:RAX r/m64 RAX RDX 264 - 1\r\n quadword\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIF SRC = 0\r\n THEN #DE; FI; (* Divide Error *)\r\nIF OperandSize = 8 (* Word/Byte Operation *)\r\n THEN\r\n temp <- AX / SRC;\r\n IF temp > FFH\r\n THEN #DE; (* Divide error *)\r\n ELSE\r\n AL <- temp;\r\n AH <- AX MOD SRC;\r\n FI;\r\n ELSE IF OperandSize = 16 (* Doubleword/word operation *)\r\n THEN\r\n temp <- DX:AX / SRC;\r\n IF temp > FFFFH\r\n THEN #DE; (* Divide error *)\r\n ELSE\r\n AX <- temp;\r\n DX <- DX:AX MOD SRC;\r\n FI;\r\n FI;\r\n ELSE IF Operandsize = 32 (* Quadword/doubleword operation *)\r\n THEN\r\n temp <- EDX:EAX / SRC;\r\n IF temp > FFFFFFFFH\r\n THEN #DE; (* Divide error *)\r\n ELSE\r\n EAX <- temp;\r\n EDX <- EDX:EAX MOD SRC;\r\n FI;\r\n FI;\r\n ELSE IF 64-Bit Mode and Operandsize = 64 (* Doublequadword/quadword operation *)\r\n THEN\r\n temp <- RDX:RAX / SRC;\r\n IF temp > FFFFFFFFFFFFFFFFH\r\n THEN #DE; (* Divide error *)\r\n ELSE\r\n RAX <- temp;\r\n RDX <- RDX:RAX MOD SRC;\r\n FI;\r\n FI;\r\nFI;\r\n\r\nFlags Affected\r\nThe CF, OF, SF, ZF, AF, and PF flags are undefined.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#DE If the source operand (divisor) is 0\r\n If the quotient is too large for the designated register.\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#DE If the source operand (divisor) is 0.\r\n If the quotient is too large for the designated register.\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#DE If the source operand (divisor) is 0.\r\n If the quotient is too large for the designated register.\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#DE If the source operand (divisor) is 0\r\n If the quotient is too large for the designated register.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "DIV"
},
{
"description": "DIVPD-Divide Packed Double-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0F 5E /r RM V/V SSE2 Divide packed double-precision floating-point values\r\n DIVPD xmm1, xmm2/m128 in xmm1 by packed double-precision floating-point\r\n values in xmm2/mem.\r\n VEX.NDS.128.66.0F.WIG 5E /r RVM V/V AVX Divide packed double-precision floating-point values\r\n VDIVPD xmm1, xmm2, xmm3/m128 in xmm2 by packed double-precision floating-point\r\n values in xmm3/mem.\r\n VEX.NDS.256.66.0F.WIG 5E /r RVM V/V AVX Divide packed double-precision floating-point values\r\n VDIVPD ymm1, ymm2, ymm3/m256 in ymm2 by packed double-precision floating-point\r\n values in ymm3/mem.\r\n EVEX.NDS.128.66.0F.W1 5E /r FV V/V AVX512VL Divide packed double-precision floating-point values\r\n VDIVPD xmm1 {k1}{z}, xmm2, AVX512F in xmm2 by packed double-precision floating-point\r\n xmm3/m128/m64bcst values in xmm3/m128/m64bcst and write results to\r\n xmm1 subject to writemask k1.\r\n EVEX.NDS.256.66.0F.W1 5E /r FV V/V AVX512VL Divide packed double-precision floating-point values\r\n VDIVPD ymm1 {k1}{z}, ymm2, AVX512F in ymm2 by packed double-precision floating-point\r\n ymm3/m256/m64bcst values in ymm3/m256/m64bcst and write results to\r\n ymm1 subject to writemask k1.\r\n EVEX.NDS.512.66.0F.W1 5E /r FV V/V AVX512F Divide packed double-precision floating-point values\r\n VDIVPD zmm1 {k1}{z}, zmm2, in zmm2 by packed double-precision FP values in\r\n zmm3/m512/m64bcst{er} zmm3/m512/m64bcst and write results to zmm1\r\n subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a SIMD divide of the double-precision floating-point values in the first source operand by the floating-\r\npoint values in the second source operand (the third operand). Results are written to the destination operand (the\r\nfirst operand).\r\nEVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second\r\nsource operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector\r\nbroadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally\r\nupdated with writemask k1.\r\nVEX.256 encoded version: The first source operand (the second operand) is a YMM register. The second source\r\noperand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper\r\nbits (MAX_VL-1:256) of the corresponding destination are zeroed.\r\nVEX.128 encoded version: The first source operand (the second operand) is a XMM register. The second source\r\noperand can be a XMM register or a 128-bit memory location. The destination operand is a XMM register. The upper\r\nbits (MAX_VL-1:128) of the corresponding destination are zeroed.\r\n128-bit Legacy SSE version: The second source operand (the second operand) can be an XMM register or an 128-\r\nbit memory location. The destination is the same as the first source operand. The upper bits (MAX_VL-1:128) of the\r\ncorresponding destination are unmodified.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVDIVPD (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1) AND SRC2 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC); ; refer to Table 2-4 in the Intel Architecture Instruction Set Extensions Programming Reference\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN\r\n DEST[i+63:i] <- SRC1[i+63:i] / SRC2[63:0]\r\n ELSE\r\n DEST[i+63:i] <- SRC1[i+63:i] / SRC2[i+63:i]\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVDIVPD (VEX.256 encoded version)\r\nDEST[63:0] <-SRC1[63:0] / SRC2[63:0]\r\nDEST[127:64] <-SRC1[127:64] / SRC2[127:64]\r\nDEST[191:128] <-SRC1[191:128] / SRC2[191:128]\r\nDEST[255:192] <-SRC1[255:192] / SRC2[255:192]\r\nDEST[MAX_VL-1:256] <-0;\r\n\r\nVDIVPD (VEX.128 encoded version)\r\nDEST[63:0] <-SRC1[63:0] / SRC2[63:0]\r\nDEST[127:64] <-SRC1[127:64] / SRC2[127:64]\r\nDEST[MAX_VL-1:128] <-0;\r\n\r\nDIVPD (128-bit Legacy SSE version)\r\nDEST[63:0] <-SRC1[63:0] / SRC2[63:0]\r\nDEST[127:64] <-SRC1[127:64] / SRC2[127:64]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVDIVPD __m512d _mm512_div_pd( __m512d a, __m512d b);\r\nVDIVPD __m512d _mm512_mask_div_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);\r\nVDIVPD __m512d _mm512_maskz_div_pd( __mmask8 k, __m512d a, __m512d b);\r\nVDIVPD __m256d _mm256_mask_div_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);\r\nVDIVPD __m256d _mm256_maskz_div_pd( __mmask8 k, __m256d a, __m256d b);\r\nVDIVPD __m128d _mm_mask_div_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);\r\nVDIVPD __m128d _mm_maskz_div_pd( __mmask8 k, __m128d a, __m128d b);\r\nVDIVPD __m512d _mm512_div_round_pd( __m512d a, __m512d b, int);\r\nVDIVPD __m512d _mm512_mask_div_round_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int);\r\nVDIVPD __m512d _mm512_maskz_div_round_pd( __mmask8 k, __m512d a, __m512d b, int);\r\nVDIVPD __m256d _mm256_div_pd (__m256d a, __m256d b);\r\nDIVPD __m128d _mm_div_pd (__m128d a, __m128d b);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2.\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "DIVPD"
},
{
"description": "DIVPS-Divide Packed Single-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 0F 5E /r RM V/V SSE Divide packed single-precision floating-point values\r\n DIVPS xmm1, xmm2/m128 in xmm1 by packed single-precision floating-point\r\n values in xmm2/mem.\r\n VEX.NDS.128.0F.WIG 5E /r RVM V/V AVX Divide packed single-precision floating-point values\r\n VDIVPS xmm1, xmm2, xmm3/m128 in xmm2 by packed single-precision floating-point\r\n values in xmm3/mem.\r\n VEX.NDS.256.0F.WIG 5E /r RVM V/V AVX Divide packed single-precision floating-point values\r\n VDIVPS ymm1, ymm2, ymm3/m256 in ymm2 by packed single-precision floating-point\r\n values in ymm3/mem.\r\n EVEX.NDS.128.0F.W0 5E /r FV V/V AVX512VL Divide packed single-precision floating-point values\r\n VDIVPS xmm1 {k1}{z}, xmm2, AVX512F in xmm2 by packed single-precision floating-point\r\n xmm3/m128/m32bcst values in xmm3/m128/m32bcst and write results to\r\n xmm1 subject to writemask k1.\r\n EVEX.NDS.256.0F.W0 5E /r FV V/V AVX512VL Divide packed single-precision floating-point values\r\n VDIVPS ymm1 {k1}{z}, ymm2, AVX512F in ymm2 by packed single-precision floating-point\r\n ymm3/m256/m32bcst values in ymm3/m256/m32bcst and write results to\r\n ymm1 subject to writemask k1.\r\n EVEX.NDS.512.0F.W0 5E /r FV V/V AVX512F Divide packed single-precision floating-point values\r\n VDIVPS zmm1 {k1}{z}, zmm2, in zmm2 by packed single-precision floating-point\r\n zmm3/m512/m32bcst{er} values in zmm3/m512/m32bcst and write results to\r\n zmm1 subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a SIMD divide of the four, eight or sixteen packed single-precision floating-point values in the first source\r\noperand (the second operand) by the four, eight or sixteen packed single-precision floating-point values in the\r\nsecond source operand (the third operand). Results are written to the destination operand (the first operand).\r\nEVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second\r\nsource operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector\r\nbroadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally\r\nupdated with writemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register.\r\nVEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM\r\nregister or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nZMM register destination are unmodified.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVDIVPS (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1) AND SRC2 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN\r\n DEST[i+31:i] <- SRC1[i+31:i] / SRC2[31:0]\r\n ELSE\r\n DEST[i+31:i] <- SRC1[i+31:i] / SRC2[i+31:i]\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVDIVPS (VEX.256 encoded version)\r\nDEST[31:0] <-SRC1[31:0] / SRC2[31:0]\r\nDEST[63:32] <-SRC1[63:32] / SRC2[63:32]\r\nDEST[95:64] <-SRC1[95:64] / SRC2[95:64]\r\nDEST[127:96] <-SRC1[127:96] / SRC2[127:96]\r\nDEST[159:128] <-SRC1[159:128] / SRC2[159:128]\r\nDEST[191:160]<-SRC1[191:160] / SRC2[191:160]\r\nDEST[223:192] <-SRC1[223:192] / SRC2[223:192]\r\nDEST[255:224] <-SRC1[255:224] / SRC2[255:224].\r\nDEST[MAX_VL-1:256] <-0;\r\n\r\nVDIVPS (VEX.128 encoded version)\r\nDEST[31:0] <-SRC1[31:0] / SRC2[31:0]\r\nDEST[63:32] <-SRC1[63:32] / SRC2[63:32]\r\nDEST[95:64] <-SRC1[95:64] / SRC2[95:64]\r\nDEST[127:96] <-SRC1[127:96] / SRC2[127:96]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\n\r\n\r\n\r\n\r\nDIVPS (128-bit Legacy SSE version)\r\nDEST[31:0] <-SRC1[31:0] / SRC2[31:0]\r\nDEST[63:32] <-SRC1[63:32] / SRC2[63:32]\r\nDEST[95:64] <-SRC1[95:64] / SRC2[95:64]\r\nDEST[127:96] <-SRC1[127:96] / SRC2[127:96]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVDIVPS __m512 _mm512_div_ps( __m512 a, __m512 b);\r\nVDIVPS __m512 _mm512_mask_div_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);\r\nVDIVPS __m512 _mm512_maskz_div_ps(__mmask16 k, __m512 a, __m512 b);\r\nVDIVPD __m256d _mm256_mask_div_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);\r\nVDIVPD __m256d _mm256_maskz_div_pd( __mmask8 k, __m256d a, __m256d b);\r\nVDIVPD __m128d _mm_mask_div_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);\r\nVDIVPD __m128d _mm_maskz_div_pd( __mmask8 k, __m128d a, __m128d b);\r\nVDIVPS __m512 _mm512_div_round_ps( __m512 a, __m512 b, int);\r\nVDIVPS __m512 _mm512_mask_div_round_ps(__m512 s, __mmask16 k, __m512 a, __m512 b, int);\r\nVDIVPS __m512 _mm512_maskz_div_round_ps(__mmask16 k, __m512 a, __m512 b, int);\r\nVDIVPS __m256 _mm256_div_ps (__m256 a, __m256 b);\r\nDIVPS __m128 _mm_div_ps (__m128 a, __m128 b);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2.\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "DIVPS"
},
{
"description": "DIVSD-Divide Scalar Double-Precision Floating-Point Value\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n F2 0F 5E /r RM V/V SSE2 Divide low double-precision floating-point value in\r\n DIVSD xmm1, xmm2/m64 xmm1 by low double-precision floating-point value\r\n in xmm2/m64.\r\n VEX.NDS.128.F2.0F.WIG 5E /r RVM V/V AVX Divide low double-precision floating-point value in\r\n VDIVSD xmm1, xmm2, xmm3/m64 xmm2 by low double-precision floating-point value\r\n in xmm3/m64.\r\n EVEX.NDS.LIG.F2.0F.W1 5E /r T1S V/V AVX512F Divide low double-precision floating-point value in\r\n VDIVSD xmm1 {k1}{z}, xmm2, xmm2 by low double-precision floating-point value\r\n xmm3/m64{er} in xmm3/m64.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n T1S ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nDivides the low double-precision floating-point value in the first source operand by the low double-precision\r\nfloating-point value in the second source operand, and stores the double-precision floating-point result in the desti-\r\nnation operand. The second source operand can be an XMM register or a 64-bit memory location. The first source\r\nand destination are XMM registers.\r\n128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAX_VL-\r\n1:64) of the corresponding ZMM destination register remain unchanged.\r\nVEX.128 encoded version: The first source operand is an xmm register encoded by VEX.vvvv. The quadword at bits\r\n127:64 of the destination operand is copied from the corresponding quadword of the first source operand. Bits\r\n(MAX_VL-1:128) of the destination register are zeroed.\r\nEVEX.128 encoded version: The first source operand is an xmm register encoded by EVEX.vvvv. The quadword\r\nelement of the destination operand at bits 127:64 are copied from the first source operand. Bits (MAX_VL-1:128)\r\nof the destination register are zeroed.\r\nEVEX version: The low quadword element of the destination is updated according to the writemask.\r\nSoftware should ensure VDIVSD is encoded with VEX.L=0. Encoding VDIVSD with VEX.L=1 may encounter unpre-\r\ndictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVDIVSD (EVEX encoded version)\r\nIF (EVEX.b = 1) AND SRC2 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[63:0] <- SRC1[63:0] / SRC2[63:0]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[63:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVDIVSD (VEX.128 encoded version)\r\nDEST[63:0] <-SRC1[63:0] / SRC2[63:0]\r\nDEST[127:64] <-SRC1[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nDIVSD (128-bit Legacy SSE version)\r\nDEST[63:0] <-DEST[63:0] / SRC[63:0]\r\nDEST[MAX_VL-1:64] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVDIVSD __m128d _mm_mask_div_sd(__m128d s, __mmask8 k, __m128d a, __m128d b);\r\nVDIVSD __m128d _mm_maskz_div_sd( __mmask8 k, __m128d a, __m128d b);\r\nVDIVSD __m128d _mm_div_round_sd( __m128d a, __m128d b, int);\r\nVDIVSD __m128d _mm_mask_div_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int);\r\nVDIVSD __m128d _mm_maskz_div_round_sd( __mmask8 k, __m128d a, __m128d b, int);\r\nDIVSD __m128d _mm_div_sd (__m128d a, __m128d b);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3.\r\nEVEX-encoded instructions, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "DIVSD"
},
{
"description": "DIVSS-Divide Scalar Single-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n F3 0F 5E /r RM V/V SSE Divide low single-precision floating-point value in\r\n DIVSS xmm1, xmm2/m32 xmm1 by low single-precision floating-point value in\r\n xmm2/m32.\r\n VEX.NDS.128.F3.0F.WIG 5E /r RVM V/V AVX Divide low single-precision floating-point value in\r\n VDIVSS xmm1, xmm2, xmm3/m32 xmm2 by low single-precision floating-point value in\r\n xmm3/m32.\r\n EVEX.NDS.LIG.F3.0F.W0 5E /r T1S V/V AVX512F Divide low single-precision floating-point value in\r\n VDIVSS xmm1 {k1}{z}, xmm2, xmm2 by low single-precision floating-point value in\r\n xmm3/m32{er} xmm3/m32.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n T1S ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nDivides the low single-precision floating-point value in the first source operand by the low single-precision floating-\r\npoint value in the second source operand, and stores the single-precision floating-point result in the destination\r\noperand. The second source operand can be an XMM register or a 32-bit memory location.\r\n128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAX_VL-\r\n1:32) of the corresponding YMM destination register remain unchanged.\r\nVEX.128 encoded version: The first source operand is an xmm register encoded by VEX.vvvv. The three high-order\r\ndoublewords of the destination operand are copied from the first source operand. Bits (MAX_VL-1:128) of the\r\ndestination register are zeroed.\r\nEVEX.128 encoded version: The first source operand is an xmm register encoded by EVEX.vvvv. The doubleword\r\nelements of the destination operand at bits 127:32 are copied from the first source operand. Bits (MAX_VL-1:128)\r\nof the destination register are zeroed.\r\nEVEX version: The low doubleword element of the destination is updated according to the writemask.\r\nSoftware should ensure VDIVSS is encoded with VEX.L=0. Encoding VDIVSS with VEX.L=1 may encounter unpre-\r\ndictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVDIVSS (EVEX encoded version)\r\nIF (EVEX.b = 1) AND SRC2 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[31:0] <- SRC1[31:0] / SRC2[31:0]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[31:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:32] <- SRC1[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVDIVSS (VEX.128 encoded version)\r\nDEST[31:0] <-SRC1[31:0] / SRC2[31:0]\r\nDEST[127:32] <-SRC1[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nDIVSS (128-bit Legacy SSE version)\r\nDEST[31:0] <-DEST[31:0] / SRC[31:0]\r\nDEST[MAX_VL-1:32] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVDIVSS __m128 _mm_mask_div_ss(__m128 s, __mmask8 k, __m128 a, __m128 b);\r\nVDIVSS __m128 _mm_maskz_div_ss( __mmask8 k, __m128 a, __m128 b);\r\nVDIVSS __m128 _mm_div_round_ss( __m128 a, __m128 b, int);\r\nVDIVSS __m128 _mm_mask_div_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int);\r\nVDIVSS __m128 _mm_maskz_div_round_ss( __mmask8 k, __m128 a, __m128 b, int);\r\nDIVSS __m128 _mm_div_ss(__m128 a, __m128 b);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3.\r\nEVEX-encoded instructions, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "DIVSS"
},
{
"description": "DPPD - Dot Product of Packed Double Precision Floating-Point Values\r\n Opcode/ Op/ 64/32-bit CPUID Description\r\n Instruction En Mode Feature\r\n Flag\r\n 66 0F 3A 41 /r ib RMI V/V SSE4_1 Selectively multiply packed DP floating-point\r\n DPPD xmm1, xmm2/m128, imm8 values from xmm1 with packed DP floating-\r\n point values from xmm2, add and selectively\r\n store the packed DP floating-point values to\r\n xmm1.\r\n VEX.NDS.128.66.0F3A.WIG 41 /r ib RVMI V/V AVX Selectively multiply packed DP floating-point\r\n VDPPD xmm1,xmm2, xmm3/m128, imm8 values from xmm2 with packed DP floating-\r\n point values from xmm3, add and selectively\r\n store the packed DP floating-point values to\r\n xmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (r, w) ModRM:r/m (r) imm8 NA\r\n RVMI ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8\r\n\r\nDescription\r\nConditionally multiplies the packed double-precision floating-point values in the destination operand (first operand)\r\nwith the packed double-precision floating-point values in the source (second operand) depending on a mask\r\nextracted from bits [5:4] of the immediate operand (third operand). If a condition mask bit is zero, the corre-\r\nsponding multiplication is replaced by a value of 0.0 in the manner described by Section 12.8.4 of Intel 64 and\r\nIA-32 Architectures Software Developer's Manual, Volume 1.\r\nThe two resulting double-precision values are summed into an intermediate result. The intermediate result is\r\nconditionally broadcasted to the destination using a broadcast mask specified by bits [1:0] of the immediate byte.\r\nIf a broadcast mask bit is \"1\", the intermediate result is copied to the corresponding qword element in the destina-\r\ntion operand. If a broadcast mask bit is zero, the corresponding element in the destination is set to zero.\r\nDPPD follows the NaN forwarding rules stated in the Software Developer's Manual, vol. 1, table 4.7. These rules do\r\nnot cover horizontal prioritization of NaNs. Horizontal propagation of NaNs to the destination and the positioning of\r\nthose NaNs in the destination is implementation dependent. NaNs on the input sources or computationally gener-\r\nated NaNs will have at least one NaN propagated to the destination.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding\r\nYMM register destination are unmodified.\r\nVEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination\r\noperand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are\r\nzeroed.\r\nIf VDPPD is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause an\r\n#UD exception.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nDP_primitive (SRC1, SRC2)\r\nIF (imm8[4] = 1)\r\n THEN Temp1[63:0] <- DEST[63:0] * SRC[63:0]; // update SIMD exception flags\r\n ELSE Temp1[63:0] <- +0.0; FI;\r\nIF (imm8[5] = 1)\r\n THEN Temp1[127:64] <- DEST[127:64] * SRC[127:64]; // update SIMD exception flags\r\n ELSE Temp1[127:64] <- +0.0; FI;\r\n/* if unmasked exception reported, execute exception handler*/\r\n\r\nTemp2[63:0] <- Temp1[63:0] + Temp1[127:64]; // update SIMD exception flags\r\n/* if unmasked exception reported, execute exception handler*/\r\n\r\nIF (imm8[0] = 1)\r\n THEN DEST[63:0] <- Temp2[63:0];\r\n ELSE DEST[63:0] <- +0.0; FI;\r\nIF (imm8[1] = 1)\r\n THEN DEST[127:64] <- Temp2[63:0];\r\n ELSE DEST[127:64] <- +0.0; FI;\r\n\r\nDPPD (128-bit Legacy SSE version)\r\nDEST[127:0]<-DP_Primitive(SRC1[127:0], SRC2[127:0]);\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVDPPD (VEX.128 encoded version)\r\nDEST[127:0]<-DP_Primitive(SRC1[127:0], SRC2[127:0]);\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nFlags Affected\r\nNone\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nDPPD: __m128d _mm_dp_pd ( __m128d a, __m128d b, const int mask);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\nExceptions are determined separately for each add and multiply operation. Unmasked exceptions will leave the\r\ndestination untouched.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 2; additionally\r\n#UD If VEX.L= 1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "DPPD"
},
{
"description": "DPPS - Dot Product of Packed Single Precision Floating-Point Values\r\n Opcode/ Op/ 64/32-bit CPUID Description\r\n Instruction En Mode Feature\r\n Flag\r\n 66 0F 3A 40 /r ib RMI V/V SSE4_1 Selectively multiply packed SP floating-point\r\n DPPS xmm1, xmm2/m128, imm8 values from xmm1 with packed SP floating-\r\n point values from xmm2, add and selectively\r\n store the packed SP floating-point values or\r\n zero values to xmm1.\r\n VEX.NDS.128.66.0F3A.WIG 40 /r ib RVMI V/V AVX Multiply packed SP floating point values from\r\n VDPPS xmm1,xmm2, xmm3/m128, imm8 xmm1 with packed SP floating point values\r\n from xmm2/mem selectively add and store to\r\n xmm1.\r\n VEX.NDS.256.66.0F3A.WIG 40 /r ib RVMI V/V AVX Multiply packed single-precision floating-point\r\n VDPPS ymm1, ymm2, ymm3/m256, imm8 values from ymm2 with packed SP floating\r\n point values from ymm3/mem, selectively add\r\n pairs of elements and store to ymm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (r, w) ModRM:r/m (r) imm8 NA\r\n RVMI ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8\r\n\r\nDescription\r\nConditionally multiplies the packed single precision floating-point values in the destination operand (first operand)\r\nwith the packed single-precision floats in the source (second operand) depending on a mask extracted from the\r\nhigh 4 bits of the immediate byte (third operand). If a condition mask bit in Imm8[7:4] is zero, the corresponding\r\nmultiplication is replaced by a value of 0.0 in the manner described by Section 12.8.4 of Intel 64 and IA-32 Archi-\r\ntectures Software Developer's Manual, Volume 1.\r\nThe four resulting single-precision values are summed into an intermediate result. The intermediate result is condi-\r\ntionally broadcasted to the destination using a broadcast mask specified by bits [3:0] of the immediate byte.\r\nIf a broadcast mask bit is \"1\", the intermediate result is copied to the corresponding dword element in the destina-\r\ntion operand. If a broadcast mask bit is zero, the corresponding element in the destination is set to zero.\r\nDPPS follows the NaN forwarding rules stated in the Software Developer's Manual, vol. 1, table 4.7. These rules do\r\nnot cover horizontal prioritization of NaNs. Horizontal propagation of NaNs to the destination and the positioning of\r\nthose NaNs in the destination is implementation dependent. NaNs on the input sources or computationally gener-\r\nated NaNs will have at least one NaN propagated to the destination.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding\r\nYMM register destination are unmodified.\r\nVEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination\r\noperand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are\r\nzeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nDP_primitive (SRC1, SRC2)\r\nIF (imm8[4] = 1)\r\n THEN Temp1[31:0] <- DEST[31:0] * SRC[31:0]; // update SIMD exception flags\r\n ELSE Temp1[31:0] <- +0.0; FI;\r\nIF (imm8[5] = 1)\r\n THEN Temp1[63:32] <- DEST[63:32] * SRC[63:32]; // update SIMD exception flags\r\n ELSE Temp1[63:32] <- +0.0; FI;\r\nIF (imm8[6] = 1)\r\n THEN Temp1[95:64] <- DEST[95:64] * SRC[95:64]; // update SIMD exception flags\r\n ELSE Temp1[95:64] <- +0.0; FI;\r\nIF (imm8[7] = 1)\r\n THEN Temp1[127:96] <- DEST[127:96] * SRC[127:96]; // update SIMD exception flags\r\n ELSE Temp1[127:96] <- +0.0; FI;\r\n\r\nTemp2[31:0] <- Temp1[31:0] + Temp1[63:32]; // update SIMD exception flags\r\n/* if unmasked exception reported, execute exception handler*/\r\nTemp3[31:0] <- Temp1[95:64] + Temp1[127:96]; // update SIMD exception flags\r\n/* if unmasked exception reported, execute exception handler*/\r\nTemp4[31:0] <- Temp2[31:0] + Temp3[31:0]; // update SIMD exception flags\r\n/* if unmasked exception reported, execute exception handler*/\r\n\r\nIF (imm8[0] = 1)\r\n THEN DEST[31:0] <- Temp4[31:0];\r\n ELSE DEST[31:0] <- +0.0; FI;\r\nIF (imm8[1] = 1)\r\n THEN DEST[63:32] <- Temp4[31:0];\r\n ELSE DEST[63:32] <- +0.0; FI;\r\nIF (imm8[2] = 1)\r\n THEN DEST[95:64] <- Temp4[31:0];\r\n ELSE DEST[95:64] <- +0.0; FI;\r\nIF (imm8[3] = 1)\r\n THEN DEST[127:96] <- Temp4[31:0];\r\n ELSE DEST[127:96] <- +0.0; FI;\r\n\r\nDPPS (128-bit Legacy SSE version)\r\nDEST[127:0]<-DP_Primitive(SRC1[127:0], SRC2[127:0]);\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVDPPS (VEX.128 encoded version)\r\nDEST[127:0]<-DP_Primitive(SRC1[127:0], SRC2[127:0]);\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVDPPS (VEX.256 encoded version)\r\nDEST[127:0]<-DP_Primitive(SRC1[127:0], SRC2[127:0]);\r\nDEST[255:128]<-DP_Primitive(SRC1[255:128], SRC2[255:128]);\r\n\r\nFlags Affected\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n(V)DPPS: __m128 _mm_dp_ps ( __m128 a, __m128 b, const int mask);\r\n\r\nVDPPS: __m256 _mm256_dp_ps ( __m256 a, __m256 b, const int mask);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\nExceptions are determined separately for each add and multiply operation, in the order of their execution.\r\nUnmasked exceptions will leave the destination operands unchanged.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "DPPS"
},
{
"description": "EMMS-Empty MMX Technology State\r\nOpcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n0F 77 EMMS NP Valid Valid Set the x87 FPU tag word to empty.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nSets the values of all the tags in the x87 FPU tag word to empty (all 1s). This operation marks the x87 FPU data\r\nregisters (which are aliased to the MMX technology registers) as available for use by x87 FPU floating-point instruc-\r\ntions. (See Figure 8-7 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for the\r\nformat of the x87 FPU tag word.) All other MMX instructions (other than the EMMS instruction) set all the tags in\r\nx87 FPU tag word to valid (all 0s).\r\nThe EMMS instruction must be used to clear the MMX technology state at the end of all MMX technology procedures\r\nor subroutines and before calling other procedures or subroutines that may execute x87 floating-point instructions.\r\nIf a floating-point instruction loads one of the registers in the x87 FPU data register stack before the x87 FPU tag\r\nword has been reset by the EMMS instruction, an x87 floating-point register stack overflow can occur that will\r\nresult in an x87 floating-point exception or incorrect result.\r\nEMMS operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nx87FPUTagWord <- FFFFH;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nvoid _mm_empty()\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#UD If CR0.EM[bit 2] = 1.\r\n#NM If CR0.TS[bit 3] = 1.\r\n#MF If there is a pending FPU exception.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n",
"mnem": "EMMS"
},
{
"description": "ENTER-Make Stack Frame for Procedure Parameters\r\nOpcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\nC8 iw 00 ENTER imm16, 0 II Valid Valid Create a stack frame for a procedure.\r\nC8 iw 01 ENTER imm16,1 II Valid Valid Create a stack frame with a nested pointer for\r\n a procedure.\r\nC8 iw ib ENTER imm16, imm8 II Valid Valid Create a stack frame with nested pointers for\r\n a procedure.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n II iw imm8 NA NA\r\n\r\nDescription\r\nCreates a stack frame (comprising of space for dynamic storage and 1-32 frame pointer storage) for a procedure.\r\nThe first operand (imm16) specifies the size of the dynamic storage in the stack frame (that is, the number of bytes\r\nof dynamically allocated on the stack for the procedure). The second operand (imm8) gives the lexical nesting level\r\n(0 to 31) of the procedure. The nesting level (imm8 mod 32) and the OperandSize attribute determine the size in\r\nbytes of the storage space for frame pointers.\r\nThe nesting level determines the number of frame pointers that are copied into the \"display area\" of the new stack\r\nframe from the preceding frame. The default size of the frame pointer is the StackAddrSize attribute, but can be\r\noverridden using the 66H prefix. Thus, the OperandSize attribute determines the size of each frame pointer that\r\nwill be copied into the stack frame and the data being transferred from SP/ESP/RSP register into the BP/EBP/RBP\r\nregister.\r\nThe ENTER and companion LEAVE instructions are provided to support block structured languages. The ENTER\r\ninstruction (when used) is typically the first instruction in a procedure and is used to set up a new stack frame for\r\na procedure. The LEAVE instruction is then used at the end of the procedure (just before the RET instruction) to\r\nrelease the stack frame.\r\nIf the nesting level is 0, the processor pushes the frame pointer from the BP/EBP/RBP register onto the stack,\r\ncopies the current stack pointer from the SP/ESP/RSP register into the BP/EBP/RBP register, and loads the\r\nSP/ESP/RSP register with the current stack-pointer value minus the value in the size operand. For nesting levels of\r\n1 or greater, the processor pushes additional frame pointers on the stack before adjusting the stack pointer. These\r\nadditional frame pointers provide the called procedure with access points to other nested frames on the stack. See\r\n\"Procedure Calls for Block-Structured Languages\" in Chapter 6 of the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 1, for more information about the actions of the ENTER instruction.\r\nThe ENTER instruction causes a page fault whenever a write using the final value of the stack pointer (within the\r\ncurrent stack segment) would do so.\r\nIn 64-bit mode, default operation size is 64 bits; 32-bit operation size cannot be encoded. Use of 66H prefix\r\nchanges frame pointer operand size to 16 bits.\r\nWhen the 66H prefix is used and causing the OperandSize attribute to be less than the StackAddrSize, software is\r\nresponsible for the following:\r\n. The companion LEAVE instruction must also use the 66H prefix,\r\n. The value in the RBP/EBP register prior to executing \"66H ENTER\" must be within the same 16KByte region of\r\n the current stack pointer (RSP/ESP), such that the value of RBP/EBP after \"66H ENTER\" remains a valid address\r\n in the stack. This ensures \"66H LEAVE\" can restore 16-bits of data from the stack.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nAllocSize <- imm16;\r\nNestingLevel <- imm8 MOD 32;\r\nIF (OperandSize = 64)\r\n THEN\r\n Push(RBP); (* RSP decrements by 8 *)\r\n FrameTemp <- RSP;\r\n ELSE IF OperandSize = 32\r\n THEN\r\n Push(EBP); (* (E)SP decrements by 4 *)\r\n FrameTemp <- ESP; FI;\r\n ELSE (* OperandSize = 16 *)\r\n Push(BP); (* RSP or (E)SP decrements by 2 *)\r\n FrameTemp <- SP;\r\nFI;\r\n\r\nIF NestingLevel = 0\r\n THEN GOTO CONTINUE;\r\nFI;\r\n\r\nIF (NestingLevel > 1)\r\n THEN FOR i <- 1 to (NestingLevel - 1)\r\n DO\r\n IF (OperandSize = 64)\r\n THEN\r\n RBP <- RBP - 8;\r\n Push([RBP]); (* Quadword push *)\r\n ELSE IF OperandSize = 32\r\n THEN\r\n IF StackSize = 32\r\n EBP <- EBP - 4;\r\n Push([EBP]); (* Doubleword push *)\r\n ELSE (* StackSize = 16 *)\r\n BP <- BP - 4;\r\n Push([BP]); (* Doubleword push *)\r\n FI;\r\n FI;\r\n ELSE (* OperandSize = 16 *)\r\n IF StackSize = 32\r\n THEN\r\n EBP <- EBP - 2;\r\n Push([EBP]); (* Word push *)\r\n ELSE (* StackSize = 16 *)\r\n BP <- BP - 2;\r\n Push([BP]); (* Word push *)\r\n FI;\r\n FI;\r\n OD;\r\nFI;\r\n\r\nIF (OperandSize = 64) (* nestinglevel 1 *)\r\n THEN\r\n Push(FrameTemp); (* Quadword push and RSP decrements by 8 *)\r\n ELSE IF OperandSize = 32\r\n\r\n\r\n\r\n\r\n THEN\r\n Push(FrameTemp); FI; (* Doubleword push and (E)SP decrements by 4 *)\r\n ELSE (* OperandSize = 16 *)\r\n Push(FrameTemp); (* Word push and RSP|ESP|SP decrements by 2 *)\r\nFI;\r\n\r\nCONTINUE:\r\nIF 64-Bit Mode (StackSize = 64)\r\n THEN\r\n RBP <- FrameTemp;\r\n RSP <- RSP - AllocSize;\r\n ELSE IF OperandSize = 32\r\n THEN\r\n EBP <- FrameTemp;\r\n ESP <- ESP - AllocSize; FI;\r\n ELSE (* OperandSize = 16 *)\r\n BP <- FrameTemp[15:1]; (* Bits 16 and above of applicable RBP/EBP are unmodified *)\r\n SP <- SP - AllocSize;\r\nFI;\r\n\r\nEND;\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#SS(0) If the new value of the SP or ESP register is outside the stack segment limit.\r\n#PF(fault-code) If a page fault occurs or if a write using the final value of the stack pointer (within the current\r\n stack segment) would cause a page fault.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#SS If the new value of the SP or ESP register is outside the stack segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#SS(0) If the new value of the SP or ESP register is outside the stack segment limit.\r\n#PF(fault-code) If a page fault occurs or if a write using the final value of the stack pointer (within the current\r\n stack segment) would cause a page fault.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If the stack address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs or if a write using the final value of the stack pointer (within the current\r\n stack segment) would cause a page fault.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "ENTER"
},
{
"description": "EXTRACTPS-Extract Packed Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0F 3A 17 /r ib RMI VV SSE4_1 Extract one single-precision floating-point value\r\n EXTRACTPS reg/m32, xmm1, imm8 from xmm1 at the offset specified by imm8 and\r\n store the result in reg or m32. Zero extend the\r\n results in 64-bit register if applicable.\r\n VEX.128.66.0F3A.WIG 17 /r ib RMI V/V AVX Extract one single-precision floating-point value\r\n VEXTRACTPS reg/m32, xmm1, imm8 from xmm1 at the offset specified by imm8 and\r\n store the result in reg or m32. Zero extend the\r\n results in 64-bit register if applicable.\r\n EVEX.128.66.0F3A.WIG 17 /r ib T1S V/V AVX512F Extract one single-precision floating-point value\r\n VEXTRACTPS reg/m32, xmm1, imm8 from xmm1 at the offset specified by imm8 and\r\n store the result in reg or m32. Zero extend the\r\n results in 64-bit register if applicable.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:r/m (w) ModRM:reg (r) Imm8 NA\r\n T1S ModRM:r/m (w) ModRM:reg (r) Imm8 NA\r\n\r\nDescription\r\nExtracts a single-precision floating-point value from the source operand (second operand) at the 32-bit offset spec-\r\nified from imm8. Immediate bits higher than the most significant offset for the vector length are ignored.\r\nThe extracted single-precision floating-point value is stored in the low 32-bits of the destination operand\r\nIn 64-bit mode, destination register operand has default operand size of 64 bits. The upper 32-bits of the register\r\nare filled with zero. REX.W is ignored.\r\nVEX.128 and EVEX encoded version: When VEX.W1 or EVEX.W1 form is used in 64-bit mode with a general\r\npurpose register (GPR) as a destination operand, the packed single quantity is zero extended to 64 bits.\r\nVEX.vvvv/EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n128-bit Legacy SSE version: When a REX.W prefix is used in 64-bit mode with a general purpose register (GPR) as\r\na destination operand, the packed single quantity is zero extended to 64 bits.\r\nThe source register is an XMM register. Imm8[1:0] determine the starting DWORD offset from which to extract the\r\n32-bit floating-point value.\r\nIf VEXTRACTPS is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause\r\nan #UD exception.\r\n\r\nOperation\r\nVEXTRACTPS (EVEX and VEX.128 encoded version)\r\nSRC_OFFSET <- IMM8[1:0]\r\nIF (64-Bit Mode and DEST is register)\r\n DEST[31:0] <- (SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh\r\n DEST[63:32] <- 0\r\nELSE\r\n DEST[31:0] <- (SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh\r\nFI\r\n\r\n\r\n\r\n\r\n\r\nEXTRACTPS (128-bit Legacy SSE version)\r\nSRC_OFFSET <-IMM8[1:0]\r\nIF (64-Bit Mode and DEST is register)\r\n DEST[31:0] <-(SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh\r\n DEST[63:32] <-0\r\nELSE\r\n DEST[31:0] <-(SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh\r\nFI\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nEXTRACTPS int _mm_extract_ps (__m128 a, const int nidx);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 5; Additionally\r\nEVEX-encoded instructions, see Exceptions Type E9NF.\r\n#UD IF VEX.L = 0.\r\n#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "EXTRACTPS"
},
{
"description": "F2XM1-Compute 2x-1\r\nOpcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\nD9 F0 F2XM1 Valid Valid Replace ST(0) with (2ST(0) - 1).\r\n\r\n\r\n\r\nDescription\r\nComputes the exponential value of 2 to the power of the source operand minus 1. The source operand is located in\r\nregister ST(0) and the result is also stored in ST(0). The value of the source operand must lie in the range -1.0 to\r\n+1.0. If the source value is outside this range, the result is undefined.\r\nThe following table shows the results obtained when computing the exponential value of various classes of\r\nnumbers, assuming that neither overflow nor underflow occurs.\r\n Table 3-16. Results Obtained from F2XM1\r\n ST(0) SRC ST(0) DEST\r\n - 1.0 to -0 - 0.5 to - 0\r\n -0 -0\r\n +0 +0\r\n + 0 to +1.0 + 0 to 1.0\r\n\r\nValues other than 2 can be exponentiated using the following formula:\r\n\r\n xy <- 2(y * log2x)\r\n\r\n\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nST(0) <- (2ST(0) - 1);\r\n\r\nFPU Flags Affected\r\nC1 Set to 0 if stack underflow occurred.\r\n Set if result was rounded up; cleared otherwise.\r\nC0, C2, C3 Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow occurred.\r\n#IA Source operand is an SNaN value or unsupported format.\r\n#D Source is a denormal value.\r\n#U Result is too small for destination format.\r\n#P Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "F2XM1"
},
{
"description": "FABS-Absolute Value\r\n Opcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\n D9 E1 FABS Valid Valid Replace ST with its absolute value.\r\n\r\n\r\n\r\nDescription\r\nClears the sign bit of ST(0) to create the absolute value of the operand. The following table shows the results\r\nobtained when creating the absolute value of various classes of numbers.\r\n\r\n Table 3-17. Results Obtained from FABS\r\n ST(0) SRC ST(0) DEST\r\n -inf +inf\r\n -F +F\r\n -0 +0\r\n +0 +0\r\n +F +F\r\n +inf +inf\r\n NaN NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nST(0) <- |ST(0)|;\r\n\r\nFPU Flags Affected\r\nC1 Set to 0.\r\nC0, C2, C3 Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow occurred.\r\n\r\nProtected Mode Exceptions\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n",
"mnem": "FABS"
},
{
"description": "FADD/FADDP/FIADD-Add\r\nOpcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\nD8 /0 FADD m32fp Valid Valid Add m32fp to ST(0) and store result in ST(0).\r\nDC /0 FADD m64fp Valid Valid Add m64fp to ST(0) and store result in ST(0).\r\nD8 C0+i FADD ST(0), ST(i) Valid Valid Add ST(0) to ST(i) and store result in ST(0).\r\nDC C0+i FADD ST(i), ST(0) Valid Valid Add ST(i) to ST(0) and store result in ST(i).\r\nDE C0+i FADDP ST(i), ST(0) Valid Valid Add ST(0) to ST(i), store result in ST(i), and pop the\r\n register stack.\r\nDE C1 FADDP Valid Valid Add ST(0) to ST(1), store result in ST(1), and pop the\r\n register stack.\r\nDA /0 FIADD m32int Valid Valid Add m32int to ST(0) and store result in ST(0).\r\nDE /0 FIADD m16int Valid Valid Add m16int to ST(0) and store result in ST(0).\r\n\r\n\r\n\r\nDescription\r\nAdds the destination and source operands and stores the sum in the destination location. The destination operand\r\nis always an FPU register; the source operand can be a register or a memory location. Source operands in memory\r\ncan be in single-precision or double-precision floating-point format or in word or doubleword integer format.\r\nThe no-operand version of the instruction adds the contents of the ST(0) register to the ST(1) register. The one-\r\noperand version adds the contents of a memory location (either a floating-point or an integer value) to the contents\r\nof the ST(0) register. The two-operand version, adds the contents of the ST(0) register to the ST(i) register or vice\r\nversa. The value in ST(0) can be doubled by coding:\r\n\r\n FADD ST(0), ST(0);\r\nThe FADDP instructions perform the additional operation of popping the FPU register stack after storing the result.\r\nTo pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP)\r\nby 1. (The no-operand version of the floating-point add instructions always results in the register stack being\r\npopped. In some assemblers, the mnemonic for this instruction is FADD rather than FADDP.)\r\nThe FIADD instructions convert an integer source operand to double extended-precision floating-point format\r\nbefore performing the addition.\r\nThe table on the following page shows the results obtained when adding various classes of numbers, assuming that\r\nneither overflow nor underflow occurs.\r\nWhen the sum of two operands with opposite signs is 0, the result is +0, except for the round toward -inf mode, in\r\nwhich case the result is -0. When the source operand is an integer 0, it is treated as a +0.\r\nWhen both operand are infinities of the same sign, the result is inf of the expected sign. If both operands are infini-\r\nties of opposite signs, an invalid-operation exception is generated. See Table 3-18.\r\n\r\n\r\n\r\n\r\n\r\n Table 3-18. FADD/FADDP/FIADD Results\r\n DEST\r\n -inf -F -0 +0 +F +inf NaN\r\n -inf -inf -inf -inf -inf -inf * NaN\r\n - F or - I -inf -F SRC SRC +- F or +- 0 +inf NaN\r\n SRC -0 -inf DEST -0 +-0 DEST +inf NaN\r\n +0 -inf DEST +-0 +0 DEST +inf NaN\r\n + F or + I -inf +- F or +- 0 SRC SRC +F +inf NaN\r\n +inf * +inf +inf +inf +inf +inf NaN\r\n NaN NaN NaN NaN NaN NaN NaN NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n I Means integer.\r\n * Indicates floating-point invalid-arithmetic-operand (#IA) exception.\r\n\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nIF Instruction = FIADD\r\n THEN\r\n DEST <- DEST + ConvertToDoubleExtendedPrecisionFP(SRC);\r\n ELSE (* Source operand is floating-point value *)\r\n DEST <- DEST + SRC;\r\nFI;\r\n\r\nIF Instruction = FADDP\r\n THEN\r\n PopRegisterStack;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1 Set to 0 if stack underflow occurred.\r\n Set if result was rounded up; cleared otherwise.\r\nC0, C2, C3 Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow occurred.\r\n#IA Operand is an SNaN value or unsupported format.\r\n Operands are infinities of unlike sign.\r\n#D Source operand is a denormal value.\r\n#U Result is too small for destination format.\r\n#O Result is too large for destination format.\r\n#P Value cannot be represented exactly in destination format.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FADD"
},
{
"description": "-R:FADD",
"mnem": "FADDP"
},
{
"description": "FBLD-Load Binary Coded Decimal\r\n Opcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\n DF /4 FBLD m80dec Valid Valid Convert BCD value to floating-point and push onto the\r\n FPU stack.\r\n\r\n\r\n\r\nDescription\r\nConverts the BCD source operand into double extended-precision floating-point format and pushes the value onto\r\nthe FPU stack. The source operand is loaded without rounding errors. The sign of the source operand is preserved,\r\nincluding that of -0.\r\nThe packed BCD digits are assumed to be in the range 0 through 9; the instruction does not check for invalid digits\r\n(AH through FH). Attempting to load an invalid encoding produces an undefined result.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nTOP <- TOP - 1;\r\nST(0) <- ConvertToDoubleExtendedPrecisionFP(SRC);\r\n\r\nFPU Flags Affected\r\nC1 Set to 1 if stack overflow occurred; otherwise, set to 0.\r\nC0, C2, C3 Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS Stack overflow occurred.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FBLD"
},
{
"description": "FBSTP-Store BCD Integer and Pop\r\nOpcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\nDF /6 FBSTP m80bcd Valid Valid Store ST(0) in m80bcd and pop ST(0).\r\n\r\n\r\n\r\nDescription\r\nConverts the value in the ST(0) register to an 18-digit packed BCD integer, stores the result in the destination\r\noperand, and pops the register stack. If the source value is a non-integral value, it is rounded to an integer value,\r\naccording to rounding mode specified by the RC field of the FPU control word. To pop the register stack, the\r\nprocessor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1.\r\nThe destination operand specifies the address where the first byte destination value is to be stored. The BCD value\r\n(including its sign bit) requires 10 bytes of space in memory.\r\nThe following table shows the results obtained when storing various classes of numbers in packed BCD format.\r\n Table 3-19. FBSTP Results\r\n ST(0) DEST\r\n - inf or Value Too Large for DEST Format *\r\n F<=-1 -D\r\n -1 < F < -0 **\r\n -0 -0\r\n +0 +0\r\n + 0 < F < +1 **\r\n F >= +1 +D\r\n + inf or Value Too Large for DEST Format *\r\n NaN *\r\n NOTES:\r\n F Means finite floating-point value.\r\n D Means packed-BCD number.\r\n * Indicates floating-point invalid-operation (#IA) exception.\r\n ** +-0 or +-1, depending on the rounding mode.\r\n\r\nIf the converted value is too large for the destination format, or if the source operand is an inf, SNaN, QNAN, or is in\r\nan unsupported format, an invalid-arithmetic-operand condition is signaled. If the invalid-operation exception is\r\nnot masked, an invalid-arithmetic-operand exception (#IA) is generated and no value is stored in the destination\r\noperand. If the invalid-operation exception is masked, the packed BCD indefinite value is stored in memory.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nDEST <- BCD(ST(0));\r\nPopRegisterStack;\r\n\r\nFPU Flags Affected\r\nC1 Set to 0 if stack underflow occurred.\r\n Set if result was rounded up; cleared otherwise.\r\nC0, C2, C3 Undefined.\r\n\r\n\r\n\r\n\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow occurred.\r\n#IA Converted value that exceeds 18 BCD digits in length.\r\n Source operand is an SNaN, QNaN, +-inf, or in an unsupported format.\r\n#P Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a segment register is being loaded with a segment selector that points to a non-writable\r\n segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FBSTP"
},
{
"description": "FCHS-Change Sign\r\nOpcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\nD9 E0 FCHS Valid Valid Complements sign of ST(0).\r\n\r\n\r\n\r\nDescription\r\nComplements the sign bit of ST(0). This operation changes a positive value into a negative value of equal magni-\r\ntude or vice versa. The following table shows the results obtained when changing the sign of various classes of\r\nnumbers.\r\n Table 3-20. FCHS Results\r\n ST(0) SRC ST(0) DEST\r\n -inf +inf\r\n -F +F\r\n -0 +0\r\n +0 -0\r\n +F -F\r\n +inf -inf\r\n NaN NaN\r\n NOTES:\r\n * F means finite floating-point value.\r\n\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nSignBit(ST(0)) <- NOT (SignBit(ST(0)));\r\n\r\nFPU Flags Affected\r\nC1 Set to 0.\r\nC0, C2, C3 Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow occurred.\r\n\r\nProtected Mode Exceptions\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FCHS"
},
{
"description": "FCLEX/FNCLEX - Clear Exceptions\r\n Opcode* Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\n 9B DB E2 FCLEX Valid Valid Clear floating-point exception flags after checking for\r\n pending unmasked floating-point exceptions.\r\n DB E2 FNCLEX* Valid Valid Clear floating-point exception flags without checking for\r\n pending unmasked floating-point exceptions.\r\n NOTES:\r\n * See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\nDescription\r\nClears the floating-point exception flags (PE, UE, OE, ZE, DE, and IE), the exception summary status flag (ES), the\r\nstack fault flag (SF), and the busy flag (B) in the FPU status word. The FCLEX instruction checks for and handles\r\nany pending unmasked floating-point exceptions before clearing the exception flags; the FNCLEX instruction does\r\nnot.\r\nThe assembler issues two instructions for the FCLEX instruction (an FWAIT instruction followed by an FNCLEX\r\ninstruction), and the processor executes each of these instructions separately. If an exception is generated for\r\neither of these instructions, the save EIP points to the instruction that caused the exception.\r\n\r\nIA-32 Architecture Compatibility\r\nWhen operating a Pentium or Intel486 processor in MS-DOS* compatibility mode, it is possible (under unusual\r\ncircumstances) for an FNCLEX instruction to be interrupted prior to being executed to handle a pending FPU excep-\r\ntion. See the section titled \"No-Wait FPU Instructions Can Get FPU Interrupt in Window\" in Appendix D of the Intel\r\n64 and IA-32 Architectures Software Developer's Manual, Volume 1, for a description of these circumstances. An\r\nFNCLEX instruction cannot be interrupted in this way on later Intel processors, except for the Intel QuarkTM X1000\r\nprocessor.\r\nThis instruction affects only the x87 FPU floating-point exception flags. It does not affect the SIMD floating-point\r\nexception flags in the MXCRS register.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nFPUStatusWord[0:7] <- 0;\r\nFPUStatusWord[15] <- 0;\r\n\r\nFPU Flags Affected\r\nThe PE, UE, OE, ZE, DE, IE, ES, SF, and B flags in the FPU status word are cleared. The C0, C1, C2, and C3 flags are\r\nundefined.\r\n\r\nFloating-Point Exceptions\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FCLEX"
},
{
"description": "FCMOVcc-Floating-Point Conditional Move\r\nOpcode* Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode*\r\nDA C0+i FCMOVB ST(0), ST(i) Valid Valid Move if below (CF=1).\r\nDA C8+i FCMOVE ST(0), ST(i) Valid Valid Move if equal (ZF=1).\r\nDA D0+i FCMOVBE ST(0), ST(i) Valid Valid Move if below or equal (CF=1 or ZF=1).\r\nDA D8+i FCMOVU ST(0), ST(i) Valid Valid Move if unordered (PF=1).\r\nDB C0+i FCMOVNB ST(0), ST(i) Valid Valid Move if not below (CF=0).\r\nDB C8+i FCMOVNE ST(0), ST(i) Valid Valid Move if not equal (ZF=0).\r\nDB D0+i FCMOVNBE ST(0), ST(i) Valid Valid Move if not below or equal (CF=0 and ZF=0).\r\nDB D8+i FCMOVNU ST(0), ST(i) Valid Valid Move if not unordered (PF=0).\r\nNOTES:\r\n* See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\nDescription\r\nTests the status flags in the EFLAGS register and moves the source operand (second operand) to the destination\r\noperand (first operand) if the given test condition is true. The condition for each mnemonic os given in the Descrip-\r\ntion column above and in Chapter 8 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume\r\n1. The source operand is always in the ST(i) register and the destination operand is always ST(0).\r\nThe FCMOVcc instructions are useful for optimizing small IF constructions. They also help eliminate branching\r\noverhead for IF operations and the possibility of branch mispredictions by the processor.\r\nA processor may not support the FCMOVcc instructions. Software can check if the FCMOVcc instructions are\r\nsupported by checking the processor's feature information with the CPUID instruction (see \"COMISS-Compare\r\nScalar Ordered Single-Precision Floating-Point Values and Set EFLAGS\" in this chapter). If both the CMOV and FPU\r\nfeature bits are set, the FCMOVcc instructions are supported.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nIA-32 Architecture Compatibility\r\nThe FCMOVcc instructions were introduced to the IA-32 Architecture in the P6 family processors and are not avail-\r\nable in earlier IA-32 processors.\r\n\r\nOperation\r\nIF condition TRUE\r\n THEN ST(0) <- ST(i);\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1 Set to 0 if stack underflow occurred.\r\nC0, C2, C3 Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow occurred.\r\n\r\nInteger Flags Affected\r\nNone.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FCMOVcc"
},
{
"description": "FCOM/FCOMP/FCOMPP-Compare Floating Point Values\r\n Opcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\n D8 /2 FCOM m32fp Valid Valid Compare ST(0) with m32fp.\r\n DC /2 FCOM m64fp Valid Valid Compare ST(0) with m64fp.\r\n D8 D0+i FCOM ST(i) Valid Valid Compare ST(0) with ST(i).\r\n D8 D1 FCOM Valid Valid Compare ST(0) with ST(1).\r\n D8 /3 FCOMP m32fp Valid Valid Compare ST(0) with m32fp and pop register stack.\r\n DC /3 FCOMP m64fp Valid Valid Compare ST(0) with m64fp and pop register stack.\r\n D8 D8+i FCOMP ST(i) Valid Valid Compare ST(0) with ST(i) and pop register stack.\r\n D8 D9 FCOMP Valid Valid Compare ST(0) with ST(1) and pop register stack.\r\n DE D9 FCOMPP Valid Valid Compare ST(0) with ST(1) and pop register stack\r\n twice.\r\n\r\n\r\n\r\nDescription\r\nCompares the contents of register ST(0) and source value and sets condition code flags C0, C2, and C3 in the FPU\r\nstatus word according to the results (see the table below). The source operand can be a data register or a memory\r\nlocation. If no source operand is given, the value in ST(0) is compared with the value in ST(1). The sign of zero is\r\nignored, so that -0.0 is equal to +0.0.\r\n Table 3-21. FCOM/FCOMP/FCOMPP Results\r\n Condition C3 C2 C0\r\n ST(0) > SRC 0 0 0\r\n ST(0) < SRC 0 0 1\r\n ST(0) = SRC 1 0 0\r\n Unordered* 1 1 1\r\n NOTES:\r\n * Flags not set if unmasked invalid-arithmetic-operand (#IA) exception is generated.\r\n\r\nThis instruction checks the class of the numbers being compared (see \"FXAM-Examine Floating-Point\" in this\r\nchapter). If either operand is a NaN or is in an unsupported format, an invalid-arithmetic-operand exception (#IA)\r\nis raised and, if the exception is masked, the condition flags are set to \"unordered.\" If the invalid-arithmetic-\r\noperand exception is unmasked, the condition code flags are not set.\r\nThe FCOMP instruction pops the register stack following the comparison operation and the FCOMPP instruction\r\npops the register stack twice following the comparison operation. To pop the register stack, the processor marks\r\nthe ST(0) register as empty and increments the stack pointer (TOP) by 1.\r\nThe FCOM instructions perform the same operation as the FUCOM instructions. The only difference is how they\r\nhandle QNaN operands. The FCOM instructions raise an invalid-arithmetic-operand exception (#IA) when either or\r\nboth of the operands is a NaN value or is in an unsupported format. The FUCOM instructions perform the same\r\noperation as the FCOM instructions, except that they do not generate an invalid-arithmetic-operand exception for\r\nQNaNs.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nCASE (relation of operands) OF\r\n ST > SRC: C3, C2, C0 <- 000;\r\n ST < SRC: C3, C2, C0 <- 001;\r\n ST = SRC: C3, C2, C0 <- 100;\r\nESAC;\r\n\r\nIF ST(0) or SRC = NaN or unsupported format\r\n THEN\r\n #IA\r\n IF FPUControlWord.IM = 1\r\n THEN\r\n C3, C2, C0 <- 111;\r\n FI;\r\nFI;\r\n\r\nIF Instruction = FCOMP\r\n THEN\r\n PopRegisterStack;\r\nFI;\r\n\r\nIF Instruction = FCOMPP\r\n THEN\r\n PopRegisterStack;\r\n PopRegisterStack;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1 Set to 0.\r\nC0, C2, C3 See table on previous page.\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow occurred.\r\n#IA One or both operands are NaN values or have unsupported formats.\r\n Register is marked empty.\r\n#D One or both operands are denormal values.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FCOM"
},
{
"description": "FCOMI/FCOMIP/ FUCOMI/FUCOMIP-Compare Floating Point Values and Set EFLAGS\r\n Opcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\n DB F0+i FCOMI ST, ST(i) Valid Valid Compare ST(0) with ST(i) and set status flags accordingly.\r\n DF F0+i FCOMIP ST, ST(i) Valid Valid Compare ST(0) with ST(i), set status flags accordingly, and\r\n pop register stack.\r\n DB E8+i FUCOMI ST, ST(i) Valid Valid Compare ST(0) with ST(i), check for ordered values, and set\r\n status flags accordingly.\r\n DF E8+i FUCOMIP ST, ST(i) Valid Valid Compare ST(0) with ST(i), check for ordered values, set\r\n status flags accordingly, and pop register stack.\r\n\r\n\r\n\r\nDescription\r\nPerforms an unordered comparison of the contents of registers ST(0) and ST(i) and sets the status flags ZF, PF, and\r\nCF in the EFLAGS register according to the results (see the table below). The sign of zero is ignored for compari-\r\nsons, so that -0.0 is equal to +0.0.\r\n Table 3-22. FCOMI/FCOMIP/ FUCOMI/FUCOMIP Results\r\n Comparison Results* ZF PF CF\r\n ST0 > ST(i) 0 0 0\r\n ST0 < ST(i) 0 0 1\r\n ST0 = ST(i) 1 0 0\r\n Unordered** 1 1 1\r\n NOTES:\r\n * See the IA-32 Architecture Compatibility section below.\r\n ** Flags not set if unmasked invalid-arithmetic-operand (#IA) exception is generated.\r\n\r\nAn unordered comparison checks the class of the numbers being compared (see \"FXAM-Examine Floating-Point\"\r\nin this chapter). The FUCOMI/FUCOMIP instructions perform the same operations as the FCOMI/FCOMIP instruc-\r\ntions. The only difference is that the FUCOMI/FUCOMIP instructions raise the invalid-arithmetic-operand exception\r\n(#IA) only when either or both operands are an SNaN or are in an unsupported format; QNaNs cause the condition\r\ncode flags to be set to unordered, but do not cause an exception to be generated. The FCOMI/FCOMIP instructions\r\nraise an invalid-operation exception when either or both of the operands are a NaN value of any kind or are in an\r\nunsupported format.\r\nIf the operation results in an invalid-arithmetic-operand exception being raised, the status flags in the EFLAGS\r\nregister are set only if the exception is masked.\r\nThe FCOMI/FCOMIP and FUCOMI/FUCOMIP instructions set the OF, SF and AF flags to zero in the EFLAGS register\r\n(regardless of whether an invalid-operation exception is detected).\r\nThe FCOMIP and FUCOMIP instructions also pop the register stack following the comparison operation. To pop the\r\nregister stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nIA-32 Architecture Compatibility\r\nThe FCOMI/FCOMIP/FUCOMI/FUCOMIP instructions were introduced to the IA-32 Architecture in the P6 family\r\nprocessors and are not available in earlier IA-32 processors.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nCASE (relation of operands) OF\r\n ST(0) > ST(i): ZF, PF, CF <- 000;\r\n ST(0) < ST(i): ZF, PF, CF <- 001;\r\n ST(0) = ST(i): ZF, PF, CF <- 100;\r\nESAC;\r\n\r\nIF Instruction is FCOMI or FCOMIP\r\n THEN\r\n IF ST(0) or ST(i) = NaN or unsupported format\r\n THEN\r\n #IA\r\n IF FPUControlWord.IM = 1\r\n THEN\r\n ZF, PF, CF <- 111;\r\n FI;\r\n FI;\r\nFI;\r\n\r\nIF Instruction is FUCOMI or FUCOMIP\r\n THEN\r\n IF ST(0) or ST(i) = QNaN, but not SNaN or unsupported format\r\n THEN\r\n ZF, PF, CF <- 111;\r\n ELSE (* ST(0) or ST(i) is SNaN or unsupported format *)\r\n #IA;\r\n IF FPUControlWord.IM = 1\r\n THEN\r\n ZF, PF, CF <- 111;\r\n FI;\r\n FI;\r\nFI;\r\n\r\nIF Instruction is FCOMIP or FUCOMIP\r\n THEN\r\n PopRegisterStack;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1 Set to 0.\r\nC0, C2, C3 Not affected.\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow occurred.\r\n#IA (FCOMI or FCOMIP instruction) One or both operands are NaN values or have unsupported\r\n formats.\r\n (FUCOMI or FUCOMIP instruction) One or both operands are SNaN values (but not QNaNs) or\r\n have undefined formats. Detection of a QNaN value does not raise an invalid-operand excep-\r\n tion.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FCOMI"
},
{
"description": "-R:FCOMI",
"mnem": "FCOMIP"
},
{
"description": "-R:FCOM",
"mnem": "FCOMP"
},
{
"description": "-R:FCOM",
"mnem": "FCOMPP"
},
{
"description": "FCOS- Cosine\r\nOpcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\nD9 FF FCOS Valid Valid Replace ST(0) with its approximate cosine.\r\n\r\n\r\n\r\nDescription\r\nComputes the approximate cosine of the source operand in register ST(0) and stores the result in ST(0). The\r\nsource operand must be given in radians and must be within the range -263 to +263. The following table shows the\r\nresults obtained when taking the cosine of various classes of numbers.\r\n Table 3-23. FCOS Results\r\n ST(0) SRC ST(0) DEST\r\n -inf *\r\n -F -1 to +1\r\n -0 +1\r\n +0 +1\r\n +F - 1 to + 1\r\n +inf *\r\n NaN NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n * Indicates floating-point invalid-arithmetic-operand (#IA) exception.\r\n\r\nIf the source operand is outside the acceptable range, the C2 flag in the FPU status word is set, and the value in\r\nregister ST(0) remains unchanged. The instruction does not raise an exception when the source operand is out of\r\nrange. It is up to the program to check the C2 flag for out-of-range conditions. Source values outside the range -\r\n263 to +263 can be reduced to the range of the instruction by subtracting an appropriate integer multiple of 2pi.\r\nHowever, even within the range -263 to +263, inaccurate results can occur because the finite approximation of pi\r\nused internally for argument reduction is not sufficient in all cases. Therefore, for accurate results it is safe to apply\r\nFCOS only to arguments reduced accurately in software, to a value smaller in absolute value than 3pi/8. See the\r\nsections titled \"Approximation of Pi\" and \"Transcendental Instruction Accuracy\" in Chapter 8 of the Intel 64 and\r\nIA-32 Architectures Software Developer's Manual, Volume 1, for a discussion of the proper value to use for pi in\r\nperforming such reductions.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nIF |ST(0)| < 263\r\nTHEN\r\n C2 <- 0;\r\n ST(0) <- FCOS(ST(0)); // approximation of cosine\r\nELSE (* Source operand is out-of-range *)\r\n C2 <- 1;\r\nFI;\r\n\r\n\r\n\r\n\r\n\r\nFPU Flags Affected\r\nC1 Set to 0 if stack underflow occurred.\r\n Set if result was rounded up; cleared otherwise.\r\n Undefined if C2 is 1.\r\nC2 Set to 1 if outside range (-263 < source operand < +263); otherwise, set to 0.\r\nC0, C3 Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow occurred.\r\n#IA Source operand is an SNaN value, inf, or unsupported format.\r\n#D Source is a denormal value.\r\n#P Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FCOS"
},
{
"description": "FDECSTP-Decrement Stack-Top Pointer\r\n Opcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\n D9 F6 FDECSTP Valid Valid Decrement TOP field in FPU status word.\r\n\r\n\r\n\r\nDescription\r\nSubtracts one from the TOP field of the FPU status word (decrements the top-of-stack pointer). If the TOP field\r\ncontains a 0, it is set to 7. The effect of this instruction is to rotate the stack by one position. The contents of the\r\nFPU data registers and tag register are not affected.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nIF TOP = 0\r\n THEN TOP <- 7;\r\n ELSE TOP <- TOP - 1;\r\nFI;\r\n\r\nFPU Flags Affected\r\nThe C1 flag is set to 0. The C0, C2, and C3 flags are undefined.\r\n\r\nFloating-Point Exceptions\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FDECSTP"
},
{
"description": "FDIV/FDIVP/FIDIV-Divide\r\nOpcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\nD8 /6 FDIV m32fp Valid Valid Divide ST(0) by m32fp and store result in ST(0).\r\nDC /6 FDIV m64fp Valid Valid Divide ST(0) by m64fp and store result in ST(0).\r\nD8 F0+i FDIV ST(0), ST(i) Valid Valid Divide ST(0) by ST(i) and store result in ST(0).\r\nDC F8+i FDIV ST(i), ST(0) Valid Valid Divide ST(i) by ST(0) and store result in ST(i).\r\nDE F8+i FDIVP ST(i), ST(0) Valid Valid Divide ST(i) by ST(0), store result in ST(i), and pop the\r\n register stack.\r\nDE F9 FDIVP Valid Valid Divide ST(1) by ST(0), store result in ST(1), and pop\r\n the register stack.\r\nDA /6 FIDIV m32int Valid Valid Divide ST(0) by m32int and store result in ST(0).\r\nDE /6 FIDIV m16int Valid Valid Divide ST(0) by m16int and store result in ST(0).\r\n\r\n\r\n\r\nDescription\r\nDivides the destination operand by the source operand and stores the result in the destination location. The desti-\r\nnation operand (dividend) is always in an FPU register; the source operand (divisor) can be a register or a memory\r\nlocation. Source operands in memory can be in single-precision or double-precision floating-point format, word or\r\ndoubleword integer format.\r\nThe no-operand version of the instruction divides the contents of the ST(1) register by the contents of the ST(0)\r\nregister. The one-operand version divides the contents of the ST(0) register by the contents of a memory location\r\n(either a floating-point or an integer value). The two-operand version, divides the contents of the ST(0) register by\r\nthe contents of the ST(i) register or vice versa.\r\nThe FDIVP instructions perform the additional operation of popping the FPU register stack after storing the result.\r\nTo pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP)\r\nby 1. The no-operand version of the floating-point divide instructions always results in the register stack being\r\npopped. In some assemblers, the mnemonic for this instruction is FDIV rather than FDIVP.\r\nThe FIDIV instructions convert an integer source operand to double extended-precision floating-point format\r\nbefore performing the division. When the source operand is an integer 0, it is treated as a +0.\r\nIf an unmasked divide-by-zero exception (#Z) is generated, no result is stored; if the exception is masked, an inf of\r\nthe appropriate sign is stored in the destination operand.\r\nThe following table shows the results obtained when dividing various classes of numbers, assuming that neither\r\noverflow nor underflow occurs.\r\n\r\n\r\n\r\n\r\n\r\n Table 3-24. FDIV/FDIVP/FIDIV Results\r\n DEST\r\n -inf -F -0 +0 +F +inf NaN\r\n -inf * +0 +0 -0 -0 * NaN\r\n -F +inf +F +0 -0 -F -inf NaN\r\n -I +inf +F +0 -0 -F -inf NaN\r\n SRC -0 +inf ** * * ** -inf NaN\r\n +0 -inf ** * * ** +inf NaN\r\n +I -inf -F -0 +0 +F +inf NaN\r\n +F -inf -F -0 +0 +F +inf NaN\r\n +inf * -0 -0 +0 +0 * NaN\r\n NaN NaN NaN NaN NaN NaN NaN NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n I Means integer.\r\n * Indicates floating-point invalid-arithmetic-operand (#IA) exception.\r\n ** Indicates floating-point zero-divide (#Z) exception.\r\n\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nIF SRC = 0\r\n THEN\r\n #Z;\r\n ELSE\r\n IF Instruction is FIDIV\r\n THEN\r\n DEST <- DEST / ConvertToDoubleExtendedPrecisionFP(SRC);\r\n ELSE (* Source operand is floating-point value *)\r\n DEST <- DEST / SRC;\r\n FI;\r\nFI;\r\n\r\nIF Instruction = FDIVP\r\n THEN\r\n PopRegisterStack;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1 Set to 0 if stack underflow occurred.\r\n Set if result was rounded up; cleared otherwise.\r\nC0, C2, C3 Undefined.\r\n\r\n\r\n\r\n\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow occurred.\r\n#IA Operand is an SNaN value or unsupported format.\r\n +-inf / +-inf; +-0 / +-0\r\n#D Source is a denormal value.\r\n#Z DEST / +-0, where DEST is not equal to +-0.\r\n#U Result is too small for destination format.\r\n#O Result is too large for destination format.\r\n#P Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FDIV"
},
{
"description": "-R:FDIV",
"mnem": "FDIVP"
},
{
"description": "FDIVR/FDIVRP/FIDIVR-Reverse Divide\r\nOpcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\nD8 /7 FDIVR m32fp Valid Valid Divide m32fp by ST(0) and store result in ST(0).\r\nDC /7 FDIVR m64fp Valid Valid Divide m64fp by ST(0) and store result in ST(0).\r\nD8 F8+i FDIVR ST(0), ST(i) Valid Valid Divide ST(i) by ST(0) and store result in ST(0).\r\nDC F0+i FDIVR ST(i), ST(0) Valid Valid Divide ST(0) by ST(i) and store result in ST(i).\r\nDE F0+i FDIVRP ST(i), ST(0) Valid Valid Divide ST(0) by ST(i), store result in ST(i), and pop the\r\n register stack.\r\nDE F1 FDIVRP Valid Valid Divide ST(0) by ST(1), store result in ST(1), and pop the\r\n register stack.\r\nDA /7 FIDIVR m32int Valid Valid Divide m32int by ST(0) and store result in ST(0).\r\nDE /7 FIDIVR m16int Valid Valid Divide m16int by ST(0) and store result in ST(0).\r\n\r\n\r\n\r\nDescription\r\nDivides the source operand by the destination operand and stores the result in the destination location. The desti-\r\nnation operand (divisor) is always in an FPU register; the source operand (dividend) can be a register or a memory\r\nlocation. Source operands in memory can be in single-precision or double-precision floating-point format, word or\r\ndoubleword integer format.\r\nThese instructions perform the reverse operations of the FDIV, FDIVP, and FIDIV instructions. They are provided to\r\nsupport more efficient coding.\r\nThe no-operand version of the instruction divides the contents of the ST(0) register by the contents of the ST(1)\r\nregister. The one-operand version divides the contents of a memory location (either a floating-point or an integer\r\nvalue) by the contents of the ST(0) register. The two-operand version, divides the contents of the ST(i) register by\r\nthe contents of the ST(0) register or vice versa.\r\nThe FDIVRP instructions perform the additional operation of popping the FPU register stack after storing the result.\r\nTo pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP)\r\nby 1. The no-operand version of the floating-point divide instructions always results in the register stack being\r\npopped. In some assemblers, the mnemonic for this instruction is FDIVR rather than FDIVRP.\r\nThe FIDIVR instructions convert an integer source operand to double extended-precision floating-point format\r\nbefore performing the division.\r\nIf an unmasked divide-by-zero exception (#Z) is generated, no result is stored; if the exception is masked, an inf of\r\nthe appropriate sign is stored in the destination operand.\r\nThe following table shows the results obtained when dividing various classes of numbers, assuming that neither\r\noverflow nor underflow occurs.\r\n\r\n\r\n\r\n\r\n\r\n Table 3-25. FDIVR/FDIVRP/FIDIVR Results\r\n DEST\r\n -inf -F -0 +0 +F +inf NaN\r\n -inf * +inf +inf -inf -inf * NaN\r\n SRC -F +0 +F ** ** -F -0 NaN\r\n -I +0 +F ** ** -F -0 NaN\r\n -0 +0 +0 * * -0 -0 NaN\r\n +0 -0 -0 * * +0 +0 NaN\r\n +I -0 -F ** ** +F +0 NaN\r\n +F -0 -F ** ** +F +0 NaN\r\n +inf * -inf -inf +inf +inf * NaN\r\n NaN NaN NaN NaN NaN NaN NaN NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n I Means integer.\r\n * Indicates floating-point invalid-arithmetic-operand (#IA) exception.\r\n ** Indicates floating-point zero-divide (#Z) exception.\r\n\r\nWhen the source operand is an integer 0, it is treated as a +0. This instruction's operation is the same in non-64-bit\r\nmodes and 64-bit mode.\r\n\r\nOperation\r\nIF DEST = 0\r\n THEN\r\n #Z;\r\n ELSE\r\n IF Instruction = FIDIVR\r\n THEN\r\n DEST <- ConvertToDoubleExtendedPrecisionFP(SRC) / DEST;\r\n ELSE (* Source operand is floating-point value *)\r\n DEST <- SRC / DEST;\r\n FI;\r\nFI;\r\n\r\nIF Instruction = FDIVRP\r\n THEN\r\n PopRegisterStack;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1 Set to 0 if stack underflow occurred.\r\n Set if result was rounded up; cleared otherwise.\r\nC0, C2, C3 Undefined.\r\n\r\n\r\n\r\n\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow occurred.\r\n#IA Operand is an SNaN value or unsupported format.\r\n +-inf / +-inf; +-0 / +-0\r\n#D Source is a denormal value.\r\n#Z SRC / +-0, where SRC is not equal to +-0.\r\n#U Result is too small for destination format.\r\n#O Result is too large for destination format.\r\n#P Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FDIVR"
},
{
"description": "-R:FDIVR",
"mnem": "FDIVRP"
},
{
"description": "FFREE-Free Floating-Point Register\r\nOpcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\nDD C0+i FFREE ST(i) Valid Valid Sets tag for ST(i) to empty.\r\n\r\n\r\n\r\nDescription\r\nSets the tag in the FPU tag register associated with register ST(i) to empty (11B). The contents of ST(i) and the FPU\r\nstack-top pointer (TOP) are not affected.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nTAG(i) <- 11B;\r\n\r\nFPU Flags Affected\r\nC0, C1, C2, C3 undefined.\r\n\r\nFloating-Point Exceptions\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FFREE"
},
{
"description": "-R:FADD",
"mnem": "FIADD"
},
{
"description": "FICOM/FICOMP-Compare Integer\r\n Opcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\n DE /2 FICOM m16int Valid Valid Compare ST(0) with m16int.\r\n DA /2 FICOM m32int Valid Valid Compare ST(0) with m32int.\r\n DE /3 FICOMP m16int Valid Valid Compare ST(0) with m16int and pop stack register.\r\n DA /3 FICOMP m32int Valid Valid Compare ST(0) with m32int and pop stack register.\r\n\r\n\r\n\r\nDescription\r\nCompares the value in ST(0) with an integer source operand and sets the condition code flags C0, C2, and C3 in\r\nthe FPU status word according to the results (see table below). The integer value is converted to double extended-\r\nprecision floating-point format before the comparison is made.\r\n Table 3-26. FICOM/FICOMP Results\r\n Condition C3 C2 C0\r\n ST(0) > SRC 0 0 0\r\n ST(0) < SRC 0 0 1\r\n ST(0) = SRC 1 0 0\r\n Unordered 1 1 1\r\n\r\nThese instructions perform an \"unordered comparison.\" An unordered comparison also checks the class of the\r\nnumbers being compared (see \"FXAM-Examine Floating-Point\" in this chapter). If either operand is a NaN or is in\r\nan undefined format, the condition flags are set to \"unordered.\"\r\nThe sign of zero is ignored, so that -0.0 <- +0.0.\r\nThe FICOMP instructions pop the register stack following the comparison. To pop the register stack, the processor\r\nmarks the ST(0) register empty and increments the stack pointer (TOP) by 1.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nCASE (relation of operands) OF\r\n ST(0) > SRC: C3, C2, C0 <- 000;\r\n ST(0) < SRC: C3, C2, C0 <- 001;\r\n ST(0) = SRC: C3, C2, C0 <- 100;\r\n Unordered: C3, C2, C0 <- 111;\r\nESAC;\r\n\r\nIF Instruction = FICOMP\r\n THEN\r\n PopRegisterStack;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1 Set to 0.\r\nC0, C2, C3 See table on previous page.\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow occurred.\r\n#IA One or both operands are NaN values or have unsupported formats.\r\n#D One or both operands are denormal values.\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FICOM"
},
{
"description": "-R:FICOM",
"mnem": "FICOMP"
},
{
"description": "-R:FDIV",
"mnem": "FIDIV"
},
{
"description": "-R:FDIVR",
"mnem": "FIDIVR"
},
{
"description": "FILD-Load Integer\r\n Opcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\n DF /0 FILD m16int Valid Valid Push m16int onto the FPU register stack.\r\n DB /0 FILD m32int Valid Valid Push m32int onto the FPU register stack.\r\n DF /5 FILD m64int Valid Valid Push m64int onto the FPU register stack.\r\n\r\n\r\n\r\nDescription\r\nConverts the signed-integer source operand into double extended-precision floating-point format and pushes the\r\nvalue onto the FPU register stack. The source operand can be a word, doubleword, or quadword integer. It is loaded\r\nwithout rounding errors. The sign of the source operand is preserved.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nTOP <- TOP - 1;\r\nST(0) <- ConvertToDoubleExtendedPrecisionFP(SRC);\r\n\r\nFPU Flags Affected\r\nC1 Set to 1 if stack overflow occurred; set to 0 otherwise.\r\nC0, C2, C3 Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS Stack overflow occurred.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FILD"
},
{
"description": "-R:FMUL",
"mnem": "FIMUL"
},
{
"description": "FINCSTP-Increment Stack-Top Pointer\r\n Opcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\n D9 F7 FINCSTP Valid Valid Increment the TOP field in the FPU status register.\r\n\r\n\r\n\r\nDescription\r\nAdds one to the TOP field of the FPU status word (increments the top-of-stack pointer). If the TOP field contains a\r\n7, it is set to 0. The effect of this instruction is to rotate the stack by one position. The contents of the FPU data\r\nregisters and tag register are not affected. This operation is not equivalent to popping the stack, because the tag\r\nfor the previous top-of-stack register is not marked empty.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nIF TOP = 7\r\n THEN TOP <- 0;\r\n ELSE TOP <- TOP + 1;\r\nFI;\r\n\r\nFPU Flags Affected\r\nThe C1 flag is set to 0. The C0, C2, and C3 flags are undefined.\r\n\r\nFloating-Point Exceptions\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FINCSTP"
},
{
"description": "FINIT/FNINIT-Initialize Floating-Point Unit\r\nOpcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\n9B DB E3 FINIT Valid Valid Initialize FPU after checking for pending unmasked\r\n floating-point exceptions.\r\nDB E3 FNINIT* Valid Valid Initialize FPU without checking for pending unmasked\r\n floating-point exceptions.\r\nNOTES:\r\n* See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\nDescription\r\nSets the FPU control, status, tag, instruction pointer, and data pointer registers to their default states. The FPU\r\ncontrol word is set to 037FH (round to nearest, all exceptions masked, 64-bit precision). The status word is cleared\r\n(no exception flags set, TOP is set to 0). The data registers in the register stack are left unchanged, but they are all\r\ntagged as empty (11B). Both the instruction and data pointers are cleared.\r\nThe FINIT instruction checks for and handles any pending unmasked floating-point exceptions before performing\r\nthe initialization; the FNINIT instruction does not.\r\nThe assembler issues two instructions for the FINIT instruction (an FWAIT instruction followed by an FNINIT\r\ninstruction), and the processor executes each of these instructions in separately. If an exception is generated for\r\neither of these instructions, the save EIP points to the instruction that caused the exception.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nIA-32 Architecture Compatibility\r\nWhen operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it is possible (under unusual\r\ncircumstances) for an FNINIT instruction to be interrupted prior to being executed to handle a pending FPU excep-\r\ntion. See the section titled \"No-Wait FPU Instructions Can Get FPU Interrupt in Window\" in Appendix D of the Intel\r\n64 and IA-32 Architectures Software Developer's Manual, Volume 1, for a description of these circumstances. An\r\nFNINIT instruction cannot be interrupted in this way on later Intel processors, except for the Intel QuarkTM X1000\r\nprocessor.\r\nIn the Intel387 math coprocessor, the FINIT/FNINIT instruction does not clear the instruction and data pointers.\r\nThis instruction affects only the x87 FPU. It does not affect the XMM and MXCSR registers.\r\n\r\nOperation\r\nFPUControlWord <- 037FH;\r\nFPUStatusWord <- 0;\r\nFPUTagWord <- FFFFH;\r\nFPUDataPointer <- 0;\r\nFPUInstructionPointer <- 0;\r\nFPULastInstructionOpcode <- 0;\r\n\r\nFPU Flags Affected\r\nC0, C1, C2, C3 set to 0.\r\n\r\nFloating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FINIT"
},
{
"description": "FIST/FISTP-Store Integer\r\nOpcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\nDF /2 FIST m16int Valid Valid Store ST(0) in m16int.\r\nDB /2 FIST m32int Valid Valid Store ST(0) in m32int.\r\nDF /3 FISTP m16int Valid Valid Store ST(0) in m16int and pop register stack.\r\nDB /3 FISTP m32int Valid Valid Store ST(0) in m32int and pop register stack.\r\nDF /7 FISTP m64int Valid Valid Store ST(0) in m64int and pop register stack.\r\n\r\n\r\n\r\nDescription\r\nThe FIST instruction converts the value in the ST(0) register to a signed integer and stores the result in the desti-\r\nnation operand. Values can be stored in word or doubleword integer format. The destination operand specifies the\r\naddress where the first byte of the destination value is to be stored.\r\nThe FISTP instruction performs the same operation as the FIST instruction and then pops the register stack. To pop\r\nthe register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1.\r\nThe FISTP instruction also stores values in quadword integer format.\r\nThe following table shows the results obtained when storing various classes of numbers in integer format.\r\n Table 3-27. FIST/FISTP Results\r\n ST(0) DEST\r\n - inf or Value Too Large for DEST Format *\r\n F <= -1 -I\r\n -1 < F < -0 **\r\n -0 0\r\n +0 0\r\n +0<F<+1 **\r\n F>=+1 +I\r\n + inf or Value Too Large for DEST Format *\r\n NaN *\r\nNOTES:\r\nF Means finite floating-point value.\r\nI Means integer.\r\n* Indicates floating-point invalid-operation (#IA) exception.\r\n** 0 or +-1, depending on the rounding mode.\r\n\r\n\r\nIf the source value is a non-integral value, it is rounded to an integer value, according to the rounding mode spec-\r\nified by the RC field of the FPU control word.\r\nIf the converted value is too large for the destination format, or if the source operand is an inf, SNaN, QNAN, or is in\r\nan unsupported format, an invalid-arithmetic-operand condition is signaled. If the invalid-operation exception is\r\nnot masked, an invalid-arithmetic-operand exception (#IA) is generated and no value is stored in the destination\r\noperand. If the invalid-operation exception is masked, the integer indefinite value is stored in memory.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nDEST <- Integer(ST(0));\r\n\r\nIF Instruction = FISTP\r\n THEN\r\n PopRegisterStack;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1 Set to 0 if stack underflow occurred.\r\n Indicates rounding direction of if the inexact exception (#P) is generated: 0 <- not roundup; 1\r\n <- roundup.\r\n Set to 0 otherwise.\r\nC0, C2, C3 Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow occurred.\r\n#IA Converted value is too large for the destination format.\r\n Source operand is an SNaN, QNaN, +-inf, or unsupported format.\r\n#P Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination is located in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FIST"
},
{
"description": "-R:FIST",
"mnem": "FISTP"
},
{
"description": "FISTTP-Store Integer with Truncation\r\n Opcode Instruction 64-Bit Mode Compat/ Description\r\n Leg Mode\r\n DF /1 FISTTP m16int Valid Valid Store ST(0) in m16int with truncation.\r\n DB /1 FISTTP m32int Valid Valid Store ST(0) in m32int with truncation.\r\n DD /1 FISTTP m64int Valid Valid Store ST(0) in m64int with truncation.\r\n\r\n\r\n\r\nDescription\r\nFISTTP converts the value in ST into a signed integer using truncation (chop) as rounding mode, transfers the\r\nresult to the destination, and pop ST. FISTTP accepts word, short integer, and long integer destinations.\r\nThe following table shows the results obtained when storing various classes of numbers in integer format.\r\n Table 3-28. FISTTP Results\r\n ST(0) DEST\r\n- inf or Value Too Large for DEST Format *\r\nF<= -1 -I\r\n-1<F<+1 0\r\nFS+1 +I\r\n+ inf or Value Too Large for DEST Format *\r\nNaN *\r\nNOTES:\r\nF Means finite floating-point value.\r\nI Means integer.\r\n* Indicates floating-point invalid-operation (#IA) exception.\r\n\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nDEST <- ST;\r\npop ST;\r\n\r\nFlags Affected\r\nC1 is cleared; C0, C2, C3 undefined.\r\n\r\nNumeric Exceptions\r\nInvalid, Stack Invalid (stack underflow), Precision.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination is in a nonwritable segment.\r\n For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.\r\n#SS(0) For an illegal address in the SS segment.\r\n#PF(fault-code) For a page fault.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#NM If CR0.EM[bit 2] = 1.\r\n If CR0.TS[bit 3] = 1.\r\n#UD If CPUID.01H:ECX.SSE3[bit 0] = 0.\r\n If the LOCK prefix is used.\r\n\r\n\r\n\r\nReal Address Mode Exceptions\r\nGP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH.\r\n#NM If CR0.EM[bit 2] = 1.\r\n If CR0.TS[bit 3] = 1.\r\n#UD If CPUID.01H:ECX.SSE3[bit 0] = 0.\r\n If the LOCK prefix is used.\r\n\r\nVirtual 8086 Mode Exceptions\r\nGP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH.\r\n#NM If CR0.EM[bit 2] = 1.\r\n If CR0.TS[bit 3] = 1.\r\n#UD If CPUID.01H:ECX.SSE3[bit 0] = 0.\r\n If the LOCK prefix is used.\r\n#PF(fault-code) For a page fault.\r\n#AC(0) For unaligned memory reference if the current privilege is 3.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FISTTP"
},
{
"description": "-R:FSUB",
"mnem": "FISUB"
},
{
"description": "-R:FSUBR",
"mnem": "FISUBR"
},
{
"description": "FLD-Load Floating Point Value\r\n Opcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\n D9 /0 FLD m32fp Valid Valid Push m32fp onto the FPU register stack.\r\n DD /0 FLD m64fp Valid Valid Push m64fp onto the FPU register stack.\r\n DB /5 FLD m80fp Valid Valid Push m80fp onto the FPU register stack.\r\n D9 C0+i FLD ST(i) Valid Valid Push ST(i) onto the FPU register stack.\r\n\r\n\r\n\r\nDescription\r\nPushes the source operand onto the FPU register stack. The source operand can be in single-precision, double-\r\nprecision, or double extended-precision floating-point format. If the source operand is in single-precision or\r\ndouble-precision floating-point format, it is automatically converted to the double extended-precision floating-\r\npoint format before being pushed on the stack.\r\nThe FLD instruction can also push the value in a selected FPU register [ST(i)] onto the stack. Here, pushing register\r\nST(0) duplicates the stack top.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nIF SRC is ST(i)\r\n THEN\r\n temp <- ST(i);\r\nFI;\r\n\r\nTOP <- TOP - 1;\r\nIF SRC is memory-operand\r\n THEN\r\n ST(0) <- ConvertToDoubleExtendedPrecisionFP(SRC);\r\n ELSE (* SRC is ST(i) *)\r\n ST(0) <- temp;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1 Set to 1 if stack overflow occurred; otherwise, set to 0.\r\nC0, C2, C3 Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow or overflow occurred.\r\n#IA Source operand is an SNaN. Does not occur if the source operand is in double extended-preci-\r\n sion floating-point format (FLD m80fp or FLD ST(i)).\r\n#D Source operand is a denormal value. Does not occur if the source operand is in double\r\n extended-precision floating-point format.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If destination is located in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FLD"
},
{
"description": "FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ-Load Constant\r\nOpcode* Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\nD9 E8 FLD1 Valid Valid Push +1.0 onto the FPU register stack.\r\nD9 E9 FLDL2T Valid Valid Push log210 onto the FPU register stack.\r\nD9 EA FLDL2E Valid Valid Push log2e onto the FPU register stack.\r\nD9 EB FLDPI Valid Valid Push pi onto the FPU register stack.\r\nD9 EC FLDLG2 Valid Valid Push log102 onto the FPU register stack.\r\nD9 ED FLDLN2 Valid Valid Push loge2 onto the FPU register stack.\r\nD9 EE FLDZ Valid Valid Push +0.0 onto the FPU register stack.\r\nNOTES:\r\n* See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\nDescription\r\nPush one of seven commonly used constants (in double extended-precision floating-point format) onto the FPU\r\nregister stack. The constants that can be loaded with these instructions include +1.0, +0.0, log210, log2e, pi, log102,\r\nand loge2. For each constant, an internal 66-bit constant is rounded (as specified by the RC field in the FPU control\r\nword) to double extended-precision floating-point format. The inexact-result exception (#P) is not generated as a\r\nresult of the rounding, nor is the C1 flag set in the x87 FPU status word if the value is rounded up.\r\nSee the section titled \"Approximation of Pi\" in Chapter 8 of the Intel 64 and IA-32 Architectures Software Devel-\r\noper's Manual, Volume 1, for a description of the pi constant.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nIA-32 Architecture Compatibility\r\nWhen the RC field is set to round-to-nearest, the FPU produces the same constants that is produced by the Intel\r\n8087 and Intel 287 math coprocessors.\r\n\r\nOperation\r\nTOP <- TOP - 1;\r\nST(0) <- CONSTANT;\r\n\r\nFPU Flags Affected\r\nC1 Set to 1 if stack overflow occurred; otherwise, set to 0.\r\nC0, C2, C3 Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS Stack overflow occurred.\r\n\r\nProtected Mode Exceptions\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FLD1"
},
{
"description": "FLDCW-Load x87 FPU Control Word\r\n Opcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\n D9 /5 FLDCW m2byte Valid Valid Load FPU control word from m2byte.\r\n\r\n\r\n\r\nDescription\r\nLoads the 16-bit source operand into the FPU control word. The source operand is a memory location. This instruc-\r\ntion is typically used to establish or change the FPU's mode of operation.\r\nIf one or more exception flags are set in the FPU status word prior to loading a new FPU control word and the new\r\ncontrol word unmasks one or more of those exceptions, a floating-point exception will be generated upon execution\r\nof the next floating-point instruction (except for the no-wait floating-point instructions, see the section titled \"Soft-\r\nware Exception Handling\" in Chapter 8 of the Intel 64 and IA-32 Architectures Software Developer's Manual,\r\nVolume 1). To avoid raising exceptions when changing FPU operating modes, clear any pending exceptions (using\r\nthe FCLEX or FNCLEX instruction) before loading the new control word.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nFPUControlWord <- SRC;\r\n\r\nFPU Flags Affected\r\nC0, C1, C2, C3 undefined.\r\n\r\nFloating-Point Exceptions\r\nNone; however, this operation might unmask a pending exception in the FPU status word. That exception is then\r\ngenerated upon execution of the next \"waiting\" floating-point instruction.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FLDCW"
},
{
"description": "FLDENV-Load x87 FPU Environment\r\nOpcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\nD9 /4 FLDENV m14/28byte Valid Valid Load FPU environment from m14byte or m28byte.\r\n\r\n\r\n\r\nDescription\r\nLoads the complete x87 FPU operating environment from memory into the FPU registers. The source operand spec-\r\nifies the first byte of the operating-environment data in memory. This data is typically written to the specified\r\nmemory location by a FSTENV or FNSTENV instruction.\r\nThe FPU operating environment consists of the FPU control word, status word, tag word, instruction pointer, data\r\npointer, and last opcode. Figures 8-9 through 8-12 in the Intel 64 and IA-32 Architectures Software Developer's\r\nManual, Volume 1, show the layout in memory of the loaded environment, depending on the operating mode of the\r\nprocessor (protected or real) and the current operand-size attribute (16-bit or 32-bit). In virtual-8086 mode, the\r\nreal mode layouts are used.\r\nThe FLDENV instruction should be executed in the same operating mode as the corresponding FSTENV/FNSTENV\r\ninstruction.\r\nIf one or more unmasked exception flags are set in the new FPU status word, a floating-point exception will be\r\ngenerated upon execution of the next floating-point instruction (except for the no-wait floating-point instructions,\r\nsee the section titled \"Software Exception Handling\" in Chapter 8 of the Intel 64 and IA-32 Architectures Soft-\r\nware Developer's Manual, Volume 1). To avoid generating exceptions when loading a new environment, clear all\r\nthe exception flags in the FPU status word that is being loaded.\r\nIf a page or limit fault occurs during the execution of this instruction, the state of the x87 FPU registers as seen by\r\nthe fault handler may be different than the state being loaded from memory. In such situations, the fault handler\r\nshould ignore the status of the x87 FPU registers, handle the fault, and return. The FLDENV instruction will then\r\ncomplete the loading of the x87 FPU registers with no resulting context inconsistency.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nFPUControlWord <- SRC[FPUControlWord];\r\nFPUStatusWord <- SRC[FPUStatusWord];\r\nFPUTagWord <- SRC[FPUTagWord];\r\nFPUDataPointer <- SRC[FPUDataPointer];\r\nFPUInstructionPointer <- SRC[FPUInstructionPointer];\r\nFPULastInstructionOpcode <- SRC[FPULastInstructionOpcode];\r\n\r\nFPU Flags Affected\r\nThe C0, C1, C2, C3 flags are loaded.\r\n\r\nFloating-Point Exceptions\r\nNone; however, if an unmasked exception is loaded in the status word, it is generated upon execution of the next\r\n\"waiting\" floating-point instruction.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FLDENV"
},
{
"description": "-R:FLD1",
"mnem": "FLDL2E"
},
{
"description": "-R:FLD1",
"mnem": "FLDL2T"
},
{
"description": "-R:FLD1",
"mnem": "FLDLG2"
},
{
"description": "-R:FLD1",
"mnem": "FLDLN2"
},
{
"description": "-R:FLD1",
"mnem": "FLDPI"
},
{
"description": "-R:FLD1",
"mnem": "FLDZ"
},
{
"description": "FMUL/FMULP/FIMUL-Multiply\r\n Opcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\n D8 /1 FMUL m32fp Valid Valid Multiply ST(0) by m32fp and store result in ST(0).\r\n DC /1 FMUL m64fp Valid Valid Multiply ST(0) by m64fp and store result in ST(0).\r\n D8 C8+i FMUL ST(0), ST(i) Valid Valid Multiply ST(0) by ST(i) and store result in ST(0).\r\n DC C8+i FMUL ST(i), ST(0) Valid Valid Multiply ST(i) by ST(0) and store result in ST(i).\r\n DE C8+i FMULP ST(i), ST(0) Valid Valid Multiply ST(i) by ST(0), store result in ST(i), and pop the\r\n register stack.\r\n DE C9 FMULP Valid Valid Multiply ST(1) by ST(0), store result in ST(1), and pop\r\n the register stack.\r\n DA /1 FIMUL m32int Valid Valid Multiply ST(0) by m32int and store result in ST(0).\r\n DE /1 FIMUL m16int Valid Valid Multiply ST(0) by m16int and store result in ST(0).\r\n\r\n\r\n\r\nDescription\r\nMultiplies the destination and source operands and stores the product in the destination location. The destination\r\noperand is always an FPU data register; the source operand can be an FPU data register or a memory location.\r\nSource operands in memory can be in single-precision or double-precision floating-point format or in word or\r\ndoubleword integer format.\r\nThe no-operand version of the instruction multiplies the contents of the ST(1) register by the contents of the ST(0)\r\nregister and stores the product in the ST(1) register. The one-operand version multiplies the contents of the ST(0)\r\nregister by the contents of a memory location (either a floating point or an integer value) and stores the product in\r\nthe ST(0) register. The two-operand version, multiplies the contents of the ST(0) register by the contents of the\r\nST(i) register, or vice versa, with the result being stored in the register specified with the first operand (the desti-\r\nnation operand).\r\nThe FMULP instructions perform the additional operation of popping the FPU register stack after storing the\r\nproduct. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack\r\npointer (TOP) by 1. The no-operand version of the floating-point multiply instructions always results in the register\r\nstack being popped. In some assemblers, the mnemonic for this instruction is FMUL rather than FMULP.\r\nThe FIMUL instructions convert an integer source operand to double extended-\r\nprecision floating-point format before performing the multiplication.\r\nThe sign of the result is always the exclusive-OR of the source signs, even if one or more of the values being multi-\r\nplied is 0 or inf. When the source operand is an integer 0, it is treated as a +0.\r\nThe following table shows the results obtained when multiplying various classes of numbers, assuming that neither\r\noverflow nor underflow occurs.\r\n\r\n\r\n\r\n\r\n\r\n Table 3-29. FMUL/FMULP/FIMUL Results\r\n DEST\r\n -inf -F -0 +0 +F +inf NaN\r\n -inf +inf +inf * * -inf -inf NaN\r\n -F +inf +F +0 -0 -F -inf NaN\r\n -I +inf +F +0 -0 -F -inf NaN\r\n SRC -0 * +0 +0 -0 -0 * NaN\r\n +0 * -0 -0 +0 +0 * NaN\r\n +I -inf -F -0 +0 +F +inf NaN\r\n +F -inf -F -0 +0 +F +inf NaN\r\n +inf -inf -inf * * +inf +inf NaN\r\n NaN NaN NaN NaN NaN NaN NaN NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n I Means Integer.\r\n * Indicates invalid-arithmetic-operand (#IA) exception.\r\n\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nIF Instruction = FIMUL\r\n THEN\r\n DEST <- DEST * ConvertToDoubleExtendedPrecisionFP(SRC);\r\n ELSE (* Source operand is floating-point value *)\r\n DEST <- DEST * SRC;\r\nFI;\r\n\r\nIF Instruction = FMULP\r\n THEN\r\n PopRegisterStack;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1 Set to 0 if stack underflow occurred.\r\n Set if result was rounded up; cleared otherwise.\r\nC0, C2, C3 Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow occurred.\r\n#IA Operand is an SNaN value or unsupported format.\r\n One operand is +-0 and the other is +-inf.\r\n#D Source operand is a denormal value.\r\n#U Result is too small for destination format.\r\n#O Result is too large for destination format.\r\n#P Value cannot be represented exactly in destination format.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FMUL"
},
{
"description": "-R:FMUL",
"mnem": "FMULP"
},
{
"description": "-R:FCLEX",
"mnem": "FNCLEX"
},
{
"description": "-R:FINIT",
"mnem": "FNINIT"
},
{
"description": "FNOP-No Operation\r\n Opcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\n D9 D0 FNOP Valid Valid No operation is performed.\r\n\r\n\r\n\r\nDescription\r\nPerforms no FPU operation. This instruction takes up space in the instruction stream but does not affect the FPU or\r\nmachine context, except the EIP register and the FPU Instruction Pointer.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nFPU Flags Affected\r\nC0, C1, C2, C3 undefined.\r\n\r\nFloating-Point Exceptions\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FNOP"
},
{
"description": "-R:FSAVE",
"mnem": "FNSAVE"
},
{
"description": "-R:FSTCW",
"mnem": "FNSTCW"
},
{
"description": "-R:FSTENV",
"mnem": "FNSTENV"
},
{
"description": "-R:FSTSW",
"mnem": "FNSTSW"
},
{
"description": "FPATAN-Partial Arctangent\r\nOpcode* Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\nD9 F3 FPATAN Valid Valid Replace ST(1) with arctan(ST(1)/ST(0)) and pop the register stack.\r\nNOTES:\r\n* See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\nDescription\r\nComputes the arctangent of the source operand in register ST(1) divided by the source operand in register ST(0),\r\nstores the result in ST(1), and pops the FPU register stack. The result in register ST(0) has the same sign as the\r\nsource operand ST(1) and a magnitude less than +pi.\r\nThe FPATAN instruction returns the angle between the X axis and the line from the origin to the point (X,Y), where\r\nY (the ordinate) is ST(1) and X (the abscissa) is ST(0). The angle depends on the sign of X and Y independently,\r\nnot just on the sign of the ratio Y/X. This is because a point (-X,Y) is in the second quadrant, resulting in an angle\r\nbetween pi/2 and pi, while a point (X,-Y) is in the fourth quadrant, resulting in an angle between 0 and -pi/2. A point\r\n(-X,-Y) is in the third quadrant, giving an angle between -pi/2 and -pi.\r\nThe following table shows the results obtained when computing the arctangent of various classes of numbers,\r\nassuming that underflow does not occur.\r\n Table 3-30. FPATAN Results\r\n ST(0)\r\n -inf -F -0 +0 +F +inf NaN\r\n -inf - 3pi/4* - pi/2 - pi/2 - pi/2 - pi/2 - pi/4* NaN\r\n ST(1) -F -p -pi to -pi/2 -pi/2 -pi/2 -pi/2 to -0 -0 NaN\r\n -0 -p -p -p* - 0* -0 -0 NaN\r\n +0 +p +p + pi* + 0* +0 +0 NaN\r\n +F +p +pi to +pi/2 + pi/2 +pi/2 +pi/2 to +0 +0 NaN\r\n +inf +3pi/4* +pi/2 +pi/2 +pi/2 + pi/2 + pi/4* NaN\r\n NaN NaN NaN NaN NaN NaN NaN NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n * Table 8-10 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, specifies that the ratios 0/0 and inf/inf\r\n generate the floating-point invalid arithmetic-operation exception and, if this exception is masked, the floating-point QNaN indefi-\r\n nite value is returned. With the FPATAN instruction, the 0/0 or inf/inf value is actually not calculated using division. Instead, the arc-\r\n tangent of the two variables is derived from a standard mathematical formulation that is generalized to allow complex numbers as\r\n arguments. In this complex variable formulation, arctangent(0,0) etc. has well defined values. These values are needed to develop\r\n a library to compute transcendental functions with complex arguments, based on the FPU functions that only allow floating-point\r\n values as arguments.\r\n\r\nThere is no restriction on the range of source operands that FPATAN can accept.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nIA-32 Architecture Compatibility\r\nThe source operands for this instruction are restricted for the 80287 math coprocessor to the following range:\r\n\r\n0 <= |ST(1)| < |ST(0)| < +inf\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nST(1) <- arctan(ST(1) / ST(0));\r\nPopRegisterStack;\r\n\r\nFPU Flags Affected\r\nC1 Set to 0 if stack underflow occurred.\r\n Set if result was rounded up; cleared otherwise.\r\nC0, C2, C3 Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow occurred.\r\n#IA Source operand is an SNaN value or unsupported format.\r\n#D Source operand is a denormal value.\r\n#U Result is too small for destination format.\r\n#P Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FPATAN"
},
{
"description": "FPREM-Partial Remainder\r\nOpcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\nD9 F8 FPREM Valid Valid Replace ST(0) with the remainder obtained from dividing\r\n ST(0) by ST(1).\r\n\r\n\r\n\r\nDescription\r\nComputes the remainder obtained from dividing the value in the ST(0) register (the dividend) by the value in the\r\nST(1) register (the divisor or modulus), and stores the result in ST(0). The remainder represents the following\r\nvalue:\r\nRemainder <- ST(0) - (Q * ST(1))\r\nHere, Q is an integer value that is obtained by truncating the floating-point number quotient of [ST(0) / ST(1)]\r\ntoward zero. The sign of the remainder is the same as the sign of the dividend. The magnitude of the remainder is\r\nless than that of the modulus, unless a partial remainder was computed (as described below).\r\nThis instruction produces an exact result; the inexact-result exception does not occur and the rounding control has\r\nno effect. The following table shows the results obtained when computing the remainder of various classes of\r\nnumbers, assuming that underflow does not occur.\r\n Table 3-31. FPREM Results\r\n ST(1)\r\n -inf -F -0 +0 +F +inf NaN\r\n -inf * * * * * * NaN\r\n ST(0) -F ST(0) -F or -0 ** ** -F or -0 ST(0) NaN\r\n -0 -0 -0 * * -0 -0 NaN\r\n +0 +0 +0 * * +0 +0 NaN\r\n +F ST(0) +F or +0 ** ** +F or +0 ST(0) NaN\r\n +inf * * * * * * NaN\r\n NaN NaN NaN NaN NaN NaN NaN NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n * Indicates floating-point invalid-arithmetic-operand (#IA) exception.\r\n ** Indicates floating-point zero-divide (#Z) exception.\r\n\r\nWhen the result is 0, its sign is the same as that of the dividend. When the modulus is inf, the result is equal to the\r\nvalue in ST(0).\r\nThe FPREM instruction does not compute the remainder specified in IEEE Std 754. The IEEE specified remainder\r\ncan be computed with the FPREM1 instruction. The FPREM instruction is provided for compatibility with the Intel\r\n8087 and Intel287 math coprocessors.\r\nThe FPREM instruction gets its name \"partial remainder\" because of the way it computes the remainder. This\r\ninstruction arrives at a remainder through iterative subtraction. It can, however, reduce the exponent of ST(0) by\r\nno more than 63 in one execution of the instruction. If the instruction succeeds in producing a remainder that is\r\nless than the modulus, the operation is complete and the C2 flag in the FPU status word is cleared. Otherwise, C2\r\nis set, and the result in ST(0) is called the partial remainder. The exponent of the partial remainder will be less\r\nthan the exponent of the original dividend by at least 32. Software can re-execute the instruction (using the partial\r\nremainder in ST(0) as the dividend) until C2 is cleared. (Note that while executing such a remainder-computation\r\nloop, a higher-priority interrupting routine that needs the FPU can force a context switch in-between the instruc-\r\ntions in the loop.)\r\nAn important use of the FPREM instruction is to reduce the arguments of periodic functions. When reduction is\r\ncomplete, the instruction stores the three least-significant bits of the quotient in the C3, C1, and C0 flags of the FPU\r\n\r\n\r\n\r\nstatus word. This information is important in argument reduction for the tangent function (using a modulus of pi/4),\r\nbecause it locates the original angle in the correct one of eight sectors of the unit circle.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nD <- exponent(ST(0)) - exponent(ST(1));\r\n\r\nIF D < 64\r\n THEN\r\n Q <- Integer(TruncateTowardZero(ST(0) / ST(1)));\r\n ST(0) <- ST(0) - (ST(1) * Q);\r\n C2 <- 0;\r\n C0, C3, C1 <- LeastSignificantBits(Q); (* Q2, Q1, Q0 *)\r\n ELSE\r\n C2 <- 1;\r\n N <- An implementation-dependent number between 32 and 63;\r\n QQ <- Integer(TruncateTowardZero((ST(0) / ST(1)) / 2(D - N)));\r\n ST(0) <- ST(0) - (ST(1) * QQ * 2(D - N));\r\nFI;\r\n\r\nFPU Flags Affected\r\nC0 Set to bit 2 (Q2) of the quotient.\r\nC1 Set to 0 if stack underflow occurred; otherwise, set to least significant bit of quotient (Q0).\r\nC2 Set to 0 if reduction complete; set to 1 if incomplete.\r\nC3 Set to bit 1 (Q1) of the quotient.\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow occurred.\r\n#IA Source operand is an SNaN value, modulus is 0, dividend is inf, or unsupported format.\r\n#D Source operand is a denormal value.\r\n#U Result is too small for destination format.\r\n\r\nProtected Mode Exceptions\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FPREM"
},
{
"description": "FPREM1-Partial Remainder\r\n Opcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\n D9 F5 FPREM1 Valid Valid Replace ST(0) with the IEEE remainder obtained from dividing\r\n ST(0) by ST(1).\r\n\r\n\r\n\r\nDescription\r\nComputes the IEEE remainder obtained from dividing the value in the ST(0) register (the dividend) by the value in\r\nthe ST(1) register (the divisor or modulus), and stores the result in ST(0). The remainder represents the following\r\nvalue:\r\nRemainder <- ST(0) - (Q * ST(1))\r\nHere, Q is an integer value that is obtained by rounding the floating-point number quotient of [ST(0) / ST(1)]\r\ntoward the nearest integer value. The magnitude of the remainder is less than or equal to half the magnitude of the\r\nmodulus, unless a partial remainder was computed (as described below).\r\nThis instruction produces an exact result; the precision (inexact) exception does not occur and the rounding control\r\nhas no effect. The following table shows the results obtained when computing the remainder of various classes of\r\nnumbers, assuming that underflow does not occur.\r\n Table 3-32. FPREM1 Results\r\n ST(1)\r\n -inf -F -0 +0 +F +inf NaN\r\n -inf * * * * * * NaN\r\n ST(0) -F ST(0) +-F or -0 ** ** +- F or - 0 ST(0) NaN\r\n -0 -0 -0 * * -0 -0 NaN\r\n +0 +0 +0 * * +0 +0 NaN\r\n +F ST(0) +- F or + 0 ** ** +- F or + 0 ST(0) NaN\r\n +inf * * * * * * NaN\r\n NaN NaN NaN NaN NaN NaN NaN NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n * Indicates floating-point invalid-arithmetic-operand (#IA) exception.\r\n ** Indicates floating-point zero-divide (#Z) exception.\r\n\r\nWhen the result is 0, its sign is the same as that of the dividend. When the modulus is inf, the result is equal to the\r\nvalue in ST(0).\r\nThe FPREM1 instruction computes the remainder specified in IEEE Standard 754. This instruction operates differ-\r\nently from the FPREM instruction in the way that it rounds the quotient of ST(0) divided by ST(1) to an integer (see\r\nthe \"Operation\" section below).\r\nLike the FPREM instruction, FPREM1 computes the remainder through iterative subtraction, but can reduce the\r\nexponent of ST(0) by no more than 63 in one execution of the instruction. If the instruction succeeds in producing\r\na remainder that is less than one half the modulus, the operation is complete and the C2 flag in the FPU status word\r\nis cleared. Otherwise, C2 is set, and the result in ST(0) is called the partial remainder. The exponent of the partial\r\nremainder will be less than the exponent of the original dividend by at least 32. Software can re-execute the\r\ninstruction (using the partial remainder in ST(0) as the dividend) until C2 is cleared. (Note that while executing\r\nsuch a remainder-computation loop, a higher-priority interrupting routine that needs the FPU can force a context\r\nswitch in-between the instructions in the loop.)\r\nAn important use of the FPREM1 instruction is to reduce the arguments of periodic functions. When reduction is\r\ncomplete, the instruction stores the three least-significant bits of the quotient in the C3, C1, and C0 flags of the FPU\r\n\r\n\r\n\r\n\r\nstatus word. This information is important in argument reduction for the tangent function (using a modulus of pi/4),\r\nbecause it locates the original angle in the correct one of eight sectors of the unit circle.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nD <- exponent(ST(0)) - exponent(ST(1));\r\n\r\nIF D < 64\r\n THEN\r\n Q <- Integer(RoundTowardNearestInteger(ST(0) / ST(1)));\r\n ST(0) <- ST(0) - (ST(1) * Q);\r\n C2 <- 0;\r\n C0, C3, C1 <- LeastSignificantBits(Q); (* Q2, Q1, Q0 *)\r\n ELSE\r\n C2 <- 1;\r\n N <- An implementation-dependent number between 32 and 63;\r\n QQ <- Integer(TruncateTowardZero((ST(0) / ST(1)) / 2(D - N)));\r\n ST(0) <- ST(0) - (ST(1) * QQ * 2(D - N));\r\nFI;\r\n\r\nFPU Flags Affected\r\nC0 Set to bit 2 (Q2) of the quotient.\r\nC1 Set to 0 if stack underflow occurred; otherwise, set to least significant bit of quotient (Q0).\r\nC2 Set to 0 if reduction complete; set to 1 if incomplete.\r\nC3 Set to bit 1 (Q1) of the quotient.\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow occurred.\r\n#IA Source operand is an SNaN value, modulus (divisor) is 0, dividend is inf, or unsupported\r\n format.\r\n#D Source operand is a denormal value.\r\n#U Result is too small for destination format.\r\n\r\nProtected Mode Exceptions\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FPREM1"
},
{
"description": "FPTAN-Partial Tangent\r\nOpcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\nD9 F2 FPTAN Valid Valid Replace ST(0) with its approximate tangent and push 1\r\n onto the FPU stack.\r\n\r\n\r\n\r\nDescription\r\nComputes the approximate tangent of the source operand in register ST(0), stores the result in ST(0), and pushes\r\na 1.0 onto the FPU register stack. The source operand must be given in radians and must be less than +-263. The\r\nfollowing table shows the unmasked results obtained when computing the partial tangent of various classes of\r\nnumbers, assuming that underflow does not occur.\r\n Table 3-33. FPTAN Results\r\n ST(0) SRC ST(0) DEST\r\n -inf *\r\n -F - F to + F\r\n -0 -0\r\n +0 +0\r\n +F - F to + F\r\n +inf *\r\n NaN NaN\r\nNOTES:\r\nF Means finite floating-point value.\r\n* Indicates floating-point invalid-arithmetic-operand (#IA) exception.\r\n\r\nIf the source operand is outside the acceptable range, the C2 flag in the FPU status word is set, and the value in\r\nregister ST(0) remains unchanged. The instruction does not raise an exception when the source operand is out of\r\nrange. It is up to the program to check the C2 flag for out-of-range conditions. Source values outside the range -\r\n263 to +263 can be reduced to the range of the instruction by subtracting an appropriate integer multiple of 2pi.\r\nHowever, even within the range -263 to +263, inaccurate results can occur because the finite approximation of pi\r\nused internally for argument reduction is not sufficient in all cases. Therefore, for accurate results it is safe to apply\r\nFPTAN only to arguments reduced accurately in software, to a value smaller in absolute value than 3pi/8. See the\r\nsections titled \"Approximation of Pi\" and \"Transcendental Instruction Accuracy\" in Chapter 8 of the Intel 64 and\r\nIA-32 Architectures Software Developer's Manual, Volume 1, for a discussion of the proper value to use for pi in\r\nperforming such reductions.\r\nThe value 1.0 is pushed onto the register stack after the tangent has been computed to maintain compatibility with\r\nthe Intel 8087 and Intel287 math coprocessors. This operation also simplifies the calculation of other trigonometric\r\nfunctions. For instance, the cotangent (which is the reciprocal of the tangent) can be computed by executing a\r\nFDIVR instruction after the FPTAN instruction.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIF ST(0) < 263\r\n THEN\r\n C2 <- 0;\r\n ST(0) <- fptan(ST(0)); // approximation of tan\r\n TOP <- TOP - 1;\r\n ST(0) <- 1.0;\r\n ELSE (* Source operand is out-of-range *)\r\n C2 <- 1;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1 Set to 0 if stack underflow occurred; set to 1 if stack overflow occurred.\r\n Set if result was rounded up; cleared otherwise.\r\nC2 Set to 1 if outside range (-263 < source operand < +263); otherwise, set to 0.\r\nC0, C3 Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow or overflow occurred.\r\n#IA Source operand is an SNaN value, inf, or unsupported format.\r\n#D Source operand is a denormal value.\r\n#U Result is too small for destination format.\r\n#P Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FPTAN"
},
{
"description": "FRNDINT-Round to Integer\r\nOpcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\nD9 FC FRNDINT Valid Valid Round ST(0) to an integer.\r\n\r\n\r\n\r\nDescription\r\nRounds the source value in the ST(0) register to the nearest integral value, depending on the current rounding\r\nmode (setting of the RC field of the FPU control word), and stores the result in ST(0).\r\nIf the source value is inf, the value is not changed. If the source value is not an integral value, the floating-point\r\ninexact-result exception (#P) is generated.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nST(0) <- RoundToIntegralValue(ST(0));\r\n\r\nFPU Flags Affected\r\nC1 Set to 0 if stack underflow occurred.\r\n Set if result was rounded up; cleared otherwise.\r\nC0, C2, C3 Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow occurred.\r\n#IA Source operand is an SNaN value or unsupported format.\r\n#D Source operand is a denormal value.\r\n#P Source operand is not an integral value.\r\n\r\nProtected Mode Exceptions\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FRNDINT"
},
{
"description": "FRSTOR-Restore x87 FPU State\r\nOpcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\nDD /4 FRSTOR m94/108byte Valid Valid Load FPU state from m94byte or m108byte.\r\n\r\n\r\n\r\nDescription\r\nLoads the FPU state (operating environment and register stack) from the memory area specified with the source\r\noperand. This state data is typically written to the specified memory location by a previous FSAVE/FNSAVE instruc-\r\ntion.\r\nThe FPU operating environment consists of the FPU control word, status word, tag word, instruction pointer, data\r\npointer, and last opcode. Figures 8-9 through 8-12 in the Intel 64 and IA-32 Architectures Software Developer's\r\nManual, Volume 1, show the layout in memory of the stored environment, depending on the operating mode of the\r\nprocessor (protected or real) and the current operand-size attribute (16-bit or 32-bit). In virtual-8086 mode, the\r\nreal mode layouts are used. The contents of the FPU register stack are stored in the 80 bytes immediately following\r\nthe operating environment image.\r\nThe FRSTOR instruction should be executed in the same operating mode as the corresponding FSAVE/FNSAVE\r\ninstruction.\r\nIf one or more unmasked exception bits are set in the new FPU status word, a floating-point exception will be\r\ngenerated. To avoid raising exceptions when loading a new operating environment, clear all the exception flags in\r\nthe FPU status word that is being loaded.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nFPUControlWord <- SRC[FPUControlWord];\r\nFPUStatusWord <- SRC[FPUStatusWord];\r\nFPUTagWord <- SRC[FPUTagWord];\r\nFPUDataPointer <- SRC[FPUDataPointer];\r\nFPUInstructionPointer <- SRC[FPUInstructionPointer];\r\nFPULastInstructionOpcode <- SRC[FPULastInstructionOpcode];\r\n\r\nST(0) <- SRC[ST(0)];\r\nST(1) <- SRC[ST(1)];\r\nST(2) <- SRC[ST(2)];\r\nST(3) <- SRC[ST(3)];\r\nST(4) <- SRC[ST(4)];\r\nST(5) <- SRC[ST(5)];\r\nST(6) <- SRC[ST(6)];\r\nST(7) <- SRC[ST(7)];\r\n\r\nFPU Flags Affected\r\nThe C0, C1, C2, C3 flags are loaded.\r\n\r\nFloating-Point Exceptions\r\nNone; however, this operation might unmask an existing exception that has been detected but not generated,\r\nbecause it was masked. Here, the exception is generated at the completion of the instruction.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FRSTOR"
},
{
"description": "FSAVE/FNSAVE-Store x87 FPU State\r\n Opcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\n 9B DD /6 FSAVE m94/108byte Valid Valid Store FPU state to m94byte or m108byte after\r\n checking for pending unmasked floating-point\r\n exceptions. Then re-initialize the FPU.\r\n DD /6 FNSAVE* m94/108byte Valid Valid Store FPU environment to m94byte or m108byte\r\n without checking for pending unmasked floating-\r\n point exceptions. Then re-initialize the FPU.\r\n NOTES:\r\n * See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\nDescription\r\nStores the current FPU state (operating environment and register stack) at the specified destination in memory,\r\nand then re-initializes the FPU. The FSAVE instruction checks for and handles pending unmasked floating-point\r\nexceptions before storing the FPU state; the FNSAVE instruction does not.\r\nThe FPU operating environment consists of the FPU control word, status word, tag word, instruction pointer, data\r\npointer, and last opcode. Figures 8-9 through 8-12 in the Intel 64 and IA-32 Architectures Software Developer's\r\nManual, Volume 1, show the layout in memory of the stored environment, depending on the operating mode of the\r\nprocessor (protected or real) and the current operand-size attribute (16-bit or 32-bit). In virtual-8086 mode, the\r\nreal mode layouts are used. The contents of the FPU register stack are stored in the 80 bytes immediately follow\r\nthe operating environment image.\r\nThe saved image reflects the state of the FPU after all floating-point instructions preceding the FSAVE/FNSAVE\r\ninstruction in the instruction stream have been executed.\r\nAfter the FPU state has been saved, the FPU is reset to the same default values it is set to with the FINIT/FNINIT\r\ninstructions (see \"FINIT/FNINIT-Initialize Floating-Point Unit\" in this chapter).\r\nThe FSAVE/FNSAVE instructions are typically used when the operating system needs to perform a context switch,\r\nan exception handler needs to use the FPU, or an application program needs to pass a \"clean\" FPU to a procedure.\r\nThe assembler issues two instructions for the FSAVE instruction (an FWAIT instruction followed by an FNSAVE\r\ninstruction), and the processor executes each of these instructions separately. If an exception is generated for\r\neither of these instructions, the save EIP points to the instruction that caused the exception.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nIA-32 Architecture Compatibility\r\nFor Intel math coprocessors and FPUs prior to the Intel Pentium processor, an FWAIT instruction should be\r\nexecuted before attempting to read from the memory image stored with a prior FSAVE/FNSAVE instruction. This\r\nFWAIT instruction helps ensure that the storage operation has been completed.\r\nWhen operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it is possible (under unusual\r\ncircumstances) for an FNSAVE instruction to be interrupted prior to being executed to handle a pending FPU excep-\r\ntion. See the section titled \"No-Wait FPU Instructions Can Get FPU Interrupt in Window\" in Appendix D of the Intel\r\n64 and IA-32 Architectures Software Developer's Manual, Volume 1, for a description of these circumstances. An\r\nFNSAVE instruction cannot be interrupted in this way on later Intel processors, except for the Intel QuarkTM X1000\r\nprocessor.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\n(* Save FPU State and Registers *)\r\n\r\nDEST[FPUControlWord] <- FPUControlWord;\r\nDEST[FPUStatusWord] <- FPUStatusWord;\r\nDEST[FPUTagWord] <- FPUTagWord;\r\nDEST[FPUDataPointer] <- FPUDataPointer;\r\nDEST[FPUInstructionPointer] <- FPUInstructionPointer;\r\nDEST[FPULastInstructionOpcode] <- FPULastInstructionOpcode;\r\n\r\nDEST[ST(0)] <- ST(0);\r\nDEST[ST(1)] <- ST(1);\r\nDEST[ST(2)] <- ST(2);\r\nDEST[ST(3)] <- ST(3);\r\nDEST[ST(4)]<- ST(4);\r\nDEST[ST(5)] <- ST(5);\r\nDEST[ST(6)] <- ST(6);\r\nDEST[ST(7)] <- ST(7);\r\n\r\n(* Initialize FPU *)\r\n\r\nFPUControlWord <- 037FH;\r\nFPUStatusWord <- 0;\r\nFPUTagWord <- FFFFH;\r\nFPUDataPointer <- 0;\r\nFPUInstructionPointer <- 0;\r\nFPULastInstructionOpcode <- 0;\r\n\r\nFPU Flags Affected\r\nThe C0, C1, C2, and C3 flags are saved and then cleared.\r\n\r\nFloating-Point Exceptions\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If destination is located in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FSAVE"
},
{
"description": "FSCALE-Scale\r\nOpcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\nD9 FD FSCALE Valid Valid Scale ST(0) by ST(1).\r\n\r\n\r\n\r\nDescription\r\nTruncates the value in the source operand (toward 0) to an integral value and adds that value to the exponent of\r\nthe destination operand. The destination and source operands are floating-point values located in registers ST(0)\r\nand ST(1), respectively. This instruction provides rapid multiplication or division by integral powers of 2. The\r\nfollowing table shows the results obtained when scaling various classes of numbers, assuming that neither over-\r\nflow nor underflow occurs.\r\n\r\n\r\n Table 3-34. FSCALE Results\r\n ST(1)\r\n -inf -F -0 +0 +F +inf NaN\r\n -inf NaN -inf -inf -inf -inf -inf NaN\r\n ST(0) -F -0 -F -F -F -F -inf NaN\r\n -0 -0 -0 -0 -0 -0 NaN NaN\r\n +0 +0 +0 +0 +0 +0 NaN NaN\r\n +F +0 +F +F +F +F +inf NaN\r\n +inf NaN +inf +inf +inf +inf +inf NaN\r\n NaN NaN NaN NaN NaN NaN NaN NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n\r\nIn most cases, only the exponent is changed and the mantissa (significand) remains unchanged. However, when\r\nthe value being scaled in ST(0) is a denormal value, the mantissa is also changed and the result may turn out to be\r\na normalized number. Similarly, if overflow or underflow results from a scale operation, the resulting mantissa will\r\ndiffer from the source's mantissa.\r\nThe FSCALE instruction can also be used to reverse the action of the FXTRACT instruction, as shown in the following\r\nexample:\r\n FXTRACT;\r\n FSCALE;\r\n FSTP ST(1);\r\nIn this example, the FXTRACT instruction extracts the significand and exponent from the value in ST(0) and stores\r\nthem in ST(0) and ST(1) respectively. The FSCALE then scales the significand in ST(0) by the exponent in ST(1),\r\nrecreating the original value before the FXTRACT operation was performed. The FSTP ST(1) instruction overwrites\r\nthe exponent (extracted by the FXTRACT instruction) with the recreated value, which returns the stack to its orig-\r\ninal state with only one register [ST(0)] occupied.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nST(0) <- ST(0) * 2RoundTowardZero(ST(1));\r\n\r\nFPU Flags Affected\r\nC1 Set to 0 if stack underflow occurred.\r\n Set if result was rounded up; cleared otherwise.\r\nC0, C2, C3 Undefined.\r\n\r\n\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow occurred.\r\n#IA Source operand is an SNaN value or unsupported format.\r\n#D Source operand is a denormal value.\r\n#U Result is too small for destination format.\r\n#O Result is too large for destination format.\r\n#P Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FSCALE"
},
{
"description": "FSIN-Sine\r\nOpcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\nD9 FE FSIN Valid Valid Replace ST(0) with the approximate of its sine.\r\n\r\n\r\n\r\nDescription\r\nComputes an approximation of the sine of the source operand in register ST(0) and stores the result in ST(0). The\r\nsource operand must be given in radians and must be within the range -263 to +263. The following table shows the\r\nresults obtained when taking the sine of various classes of numbers, assuming that underflow does not occur.\r\n Table 3-35. FSIN Results\r\n SRC (ST(0)) DEST (ST(0))\r\n -inf *\r\n -F - 1 to + 1\r\n -0 -0\r\n +0 +0\r\n +F - 1 to +1\r\n +inf *\r\n NaN NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n * Indicates floating-point invalid-arithmetic-operand (#IA) exception.\r\n\r\nIf the source operand is outside the acceptable range, the C2 flag in the FPU status word is set, and the value in\r\nregister ST(0) remains unchanged. The instruction does not raise an exception when the source operand is out of\r\nrange. It is up to the program to check the C2 flag for out-of-range conditions. Source values outside the range -\r\n263 to +263 can be reduced to the range of the instruction by subtracting an appropriate integer multiple of 2pi.\r\nHowever, even within the range -263 to +263, inaccurate results can occur because the finite approximation of pi\r\nused internally for argument reduction is not sufficient in all cases. Therefore, for accurate results it is safe to apply\r\nFSIN only to arguments reduced accurately in software, to a value smaller in absolute value than 3pi/4. See the\r\nsections titled \"Approximation of Pi\" and \"Transcendental Instruction Accuracy\" in Chapter 8 of the Intel 64 and\r\nIA-32 Architectures Software Developer's Manual, Volume 1, for a discussion of the proper value to use for pi in\r\nperforming such reductions.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nIF -263 < ST(0) < 263\r\n THEN\r\n C2 <- 0;\r\n ST(0) <- fsin(ST(0)); // approximation of the mathematical sin function\r\n ELSE (* Source operand out of range *)\r\n C2 <- 1;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1 Set to 0 if stack underflow occurred.\r\n Set if result was rounded up; cleared otherwise.\r\nC2 Set to 1 if outside range (-263 < source operand < +263); otherwise, set to 0.\r\nC0, C3 Undefined.\r\n\r\n\r\n\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow occurred.\r\n#IA Source operand is an SNaN value, inf, or unsupported format.\r\n#D Source operand is a denormal value.\r\n#P Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FSIN"
},
{
"description": "FSINCOS-Sine and Cosine\r\n Opcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\n D9 FB FSINCOS Valid Valid Compute the sine and cosine of ST(0); replace ST(0) with the\r\n approximate sine, and push the approximate cosine onto the\r\n register stack.\r\n\r\n\r\n\r\nDescription\r\nComputes both the approximate sine and the cosine of the source operand in register ST(0), stores the sine in\r\nST(0), and pushes the cosine onto the top of the FPU register stack. (This instruction is faster than executing the\r\nFSIN and FCOS instructions in succession.)\r\nThe source operand must be given in radians and must be within the range -263 to +263. The following table shows\r\nthe results obtained when taking the sine and cosine of various classes of numbers, assuming that underflow does\r\nnot occur.\r\n Table 3-36. FSINCOS Results\r\n SRC DEST\r\n ST(0) ST(1) Cosine ST(0) Sine\r\n -inf * *\r\n -F - 1 to + 1 - 1 to + 1\r\n -0 +1 -0\r\n +0 +1 +0\r\n +F - 1 to + 1 - 1 to + 1\r\n +inf * *\r\n NaN NaN NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n * Indicates floating-point invalid-arithmetic-operand (#IA) exception.\r\n\r\nIf the source operand is outside the acceptable range, the C2 flag in the FPU status word is set, and the value in\r\nregister ST(0) remains unchanged. The instruction does not raise an exception when the source operand is out of\r\nrange. It is up to the program to check the C2 flag for out-of-range conditions. Source values outside the range -\r\n263 to +263 can be reduced to the range of the instruction by subtracting an appropriate integer multiple of 2pi.\r\nHowever, even within the range -263 to +263, inaccurate results can occur because the finite approximation of pi\r\nused internally for argument reduction is not sufficient in all cases. Therefore, for accurate results it is safe to apply\r\nFSINCOS only to arguments reduced accurately in software, to a value smaller in absolute value than 3pi/8. See the\r\nsections titled \"Approximation of Pi\" and \"Transcendental Instruction Accuracy\" in Chapter 8 of the Intel 64 and\r\nIA-32 Architectures Software Developer's Manual, Volume 1, for a discussion of the proper value to use for pi in\r\nperforming such reductions.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIF ST(0) < 263\r\n THEN\r\n C2 <- 0;\r\n TEMP <- fcos(ST(0)); // approximation of cosine\r\n ST(0) <- fsin(ST(0)); // approximation of sine\r\n TOP <- TOP - 1;\r\n ST(0) <- TEMP;\r\n ELSE (* Source operand out of range *)\r\n C2 <- 1;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1 Set to 0 if stack underflow occurred; set to 1 of stack overflow occurs.\r\n Set if result was rounded up; cleared otherwise.\r\nC2 Set to 1 if outside range (-263 < source operand < +263); otherwise, set to 0.\r\nC0, C3 Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow or overflow occurred.\r\n#IA Source operand is an SNaN value, inf, or unsupported format.\r\n#D Source operand is a denormal value.\r\n#U Result is too small for destination format.\r\n#P Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FSINCOS"
},
{
"description": "FSQRT-Square Root\r\nOpcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\nD9 FA FSQRT Valid Valid Computes square root of ST(0) and stores the result in ST(0).\r\n\r\n\r\n\r\nDescription\r\nComputes the square root of the source value in the ST(0) register and stores the result in ST(0).\r\nThe following table shows the results obtained when taking the square root of various classes of numbers,\r\nassuming that neither overflow nor underflow occurs.\r\n Table 3-37. FSQRT Results\r\n SRC (ST(0)) DEST (ST(0))\r\n -inf *\r\n -F *\r\n -0 -0\r\n +0 +0\r\n +F +F\r\n +inf +inf\r\n NaN NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n * Indicates floating-point invalid-arithmetic-operand (#IA) exception.\r\n\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nST(0) <- SquareRoot(ST(0));\r\n\r\nFPU Flags Affected\r\nC1 Set to 0 if stack underflow occurred.\r\n Set if result was rounded up; cleared otherwise.\r\nC0, C2, C3 Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow occurred.\r\n#IA Source operand is an SNaN value or unsupported format.\r\n Source operand is a negative value (except for -0).\r\n#D Source operand is a denormal value.\r\n#P Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FSQRT"
},
{
"description": "FST/FSTP-Store Floating Point Value\r\n Opcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\n D9 /2 FST m32fp Valid Valid Copy ST(0) to m32fp.\r\n DD /2 FST m64fp Valid Valid Copy ST(0) to m64fp.\r\n DD D0+i FST ST(i) Valid Valid Copy ST(0) to ST(i).\r\n D9 /3 FSTP m32fp Valid Valid Copy ST(0) to m32fp and pop register stack.\r\n DD /3 FSTP m64fp Valid Valid Copy ST(0) to m64fp and pop register stack.\r\n DB /7 FSTP m80fp Valid Valid Copy ST(0) to m80fp and pop register stack.\r\n DD D8+i FSTP ST(i) Valid Valid Copy ST(0) to ST(i) and pop register stack.\r\n\r\n\r\n\r\nDescription\r\nThe FST instruction copies the value in the ST(0) register to the destination operand, which can be a memory loca-\r\ntion or another register in the FPU register stack. When storing the value in memory, the value is converted to\r\nsingle-precision or double-precision floating-point format.\r\nThe FSTP instruction performs the same operation as the FST instruction and then pops the register stack. To pop\r\nthe register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1.\r\nThe FSTP instruction can also store values in memory in double extended-precision floating-point format.\r\nIf the destination operand is a memory location, the operand specifies the address where the first byte of the desti-\r\nnation value is to be stored. If the destination operand is a register, the operand specifies a register in the register\r\nstack relative to the top of the stack.\r\nIf the destination size is single-precision or double-precision, the significand of the value being stored is rounded\r\nto the width of the destination (according to the rounding mode specified by the RC field of the FPU control word),\r\nand the exponent is converted to the width and bias of the destination format. If the value being stored is too large\r\nfor the destination format, a numeric overflow exception (#O) is generated and, if the exception is unmasked, no\r\nvalue is stored in the destination operand. If the value being stored is a denormal value, the denormal exception\r\n(#D) is not generated. This condition is simply signaled as a numeric underflow exception (#U) condition.\r\nIf the value being stored is +-0, +-inf, or a NaN, the least-significant bits of the significand and the exponent are trun-\r\ncated to fit the destination format. This operation preserves the value's identity as a 0, inf, or NaN.\r\nIf the destination operand is a non-empty register, the invalid-operation exception is not generated.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nDEST <- ST(0);\r\n\r\nIF Instruction = FSTP\r\n THEN\r\n PopRegisterStack;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1 Set to 0 if stack underflow occurred.\r\n Indicates rounding direction of if the floating-point inexact exception (#P) is generated: 0 <-\r\n not roundup; 1 <- roundup.\r\nC0, C2, C3 Undefined.\r\n\r\n\r\n\r\n\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow occurred.\r\n#IA If destination result is an SNaN value or unsupported format, except when the destination\r\n format is in double extended-precision floating-point format.\r\n#U Result is too small for the destination format.\r\n#O Result is too large for the destination format.\r\n#P Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination is located in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FST"
},
{
"description": "FSTCW/FNSTCW-Store x87 FPU Control Word\r\nOpcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\n9B D9 /7 FSTCW m2byte Valid Valid Store FPU control word to m2byte after checking for\r\n pending unmasked floating-point exceptions.\r\nD9 /7 FNSTCW* m2byte Valid Valid Store FPU control word to m2byte without checking for\r\n pending unmasked floating-point exceptions.\r\nNOTES:\r\n* See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\nDescription\r\nStores the current value of the FPU control word at the specified destination in memory. The FSTCW instruction\r\nchecks for and handles pending unmasked floating-point exceptions before storing the control word; the FNSTCW\r\ninstruction does not.\r\nThe assembler issues two instructions for the FSTCW instruction (an FWAIT instruction followed by an FNSTCW\r\ninstruction), and the processor executes each of these instructions in separately. If an exception is generated for\r\neither of these instructions, the save EIP points to the instruction that caused the exception.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nIA-32 Architecture Compatibility\r\nWhen operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it is possible (under unusual\r\ncircumstances) for an FNSTCW instruction to be interrupted prior to being executed to handle a pending FPU\r\nexception. See the section titled \"No-Wait FPU Instructions Can Get FPU Interrupt in Window\" in Appendix D of the\r\nIntel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for a description of these circum-\r\nstances. An FNSTCW instruction cannot be interrupted in this way on later Intel processors, except for the Intel\r\nQuarkTM X1000 processor.\r\n\r\nOperation\r\nDEST <- FPUControlWord;\r\n\r\nFPU Flags Affected\r\nThe C0, C1, C2, and C3 flags are undefined.\r\n\r\nFloating-Point Exceptions\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination is located in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FSTCW"
},
{
"description": "FSTENV/FNSTENV-Store x87 FPU Environment\r\n Opcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\n 9B D9 /6 FSTENV m14/28byte Valid Valid Store FPU environment to m14byte or m28byte\r\n after checking for pending unmasked floating-point\r\n exceptions. Then mask all floating-point exceptions.\r\n D9 /6 FNSTENV* m14/28byte Valid Valid Store FPU environment to m14byte or m28byte\r\n without checking for pending unmasked floating-\r\n point exceptions. Then mask all floating-\r\n point exceptions.\r\n NOTES:\r\n * See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\nDescription\r\nSaves the current FPU operating environment at the memory location specified with the destination operand, and\r\nthen masks all floating-point exceptions. The FPU operating environment consists of the FPU control word, status\r\nword, tag word, instruction pointer, data pointer, and last opcode. Figures 8-9 through 8-12 in the Intel 64 and\r\nIA-32 Architectures Software Developer's Manual, Volume 1, show the layout in memory of the stored environ-\r\nment, depending on the operating mode of the processor (protected or real) and the current operand-size attribute\r\n(16-bit or 32-bit). In virtual-8086 mode, the real mode layouts are used.\r\nThe FSTENV instruction checks for and handles any pending unmasked floating-point exceptions before storing\r\nthe FPU environment; the FNSTENV instruction does not. The saved image reflects the state of the FPU after all\r\nfloating-point instructions preceding the FSTENV/FNSTENV instruction in the instruction stream have been\r\nexecuted.\r\nThese instructions are often used by exception handlers because they provide access to the FPU instruction and\r\ndata pointers. The environment is typically saved in the stack. Masking all exceptions after saving the environment\r\nprevents floating-point exceptions from interrupting the exception handler.\r\nThe assembler issues two instructions for the FSTENV instruction (an FWAIT instruction followed by an FNSTENV\r\ninstruction), and the processor executes each of these instructions separately. If an exception is generated for\r\neither of these instructions, the save EIP points to the instruction that caused the exception.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nIA-32 Architecture Compatibility\r\nWhen operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it is possible (under unusual\r\ncircumstances) for an FNSTENV instruction to be interrupted prior to being executed to handle a pending FPU\r\nexception. See the section titled \"No-Wait FPU Instructions Can Get FPU Interrupt in Window\" in Appendix D of the\r\nIntel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for a description of these circum-\r\nstances. An FNSTENV instruction cannot be interrupted in this way on later Intel processors, except for the Intel\r\nQuarkTM X1000 processor.\r\n\r\nOperation\r\nDEST[FPUControlWord] <- FPUControlWord;\r\nDEST[FPUStatusWord] <- FPUStatusWord;\r\nDEST[FPUTagWord] <- FPUTagWord;\r\nDEST[FPUDataPointer] <- FPUDataPointer;\r\nDEST[FPUInstructionPointer] <- FPUInstructionPointer;\r\nDEST[FPULastInstructionOpcode] <- FPULastInstructionOpcode;\r\n\r\nFPU Flags Affected\r\nThe C0, C1, C2, and C3 are undefined.\r\n\r\n\r\n\r\n\r\nFloating-Point Exceptions\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination is located in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FSTENV"
},
{
"description": "-R:FST",
"mnem": "FSTP"
},
{
"description": "FSTSW/FNSTSW-Store x87 FPU Status Word\r\nOpcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\n9B DD /7 FSTSW m2byte Valid Valid Store FPU status word at m2byte after checking\r\n for pending unmasked floating-point exceptions.\r\n9B DF E0 FSTSW AX Valid Valid Store FPU status word in AX register after\r\n checking for pending unmasked floating-point\r\n exceptions.\r\nDD /7 FNSTSW* m2byte Valid Valid Store FPU status word at m2byte without\r\n checking for pending unmasked floating-point\r\n exceptions.\r\nDF E0 FNSTSW* AX Valid Valid Store FPU status word in AX register without\r\n checking for pending unmasked floating-point\r\n exceptions.\r\nNOTES:\r\n* See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\nDescription\r\nStores the current value of the x87 FPU status word in the destination location. The destination operand can be\r\neither a two-byte memory location or the AX register. The FSTSW instruction checks for and handles pending\r\nunmasked floating-point exceptions before storing the status word; the FNSTSW instruction does not.\r\nThe FNSTSW AX form of the instruction is used primarily in conditional branching (for instance, after an FPU\r\ncomparison instruction or an FPREM, FPREM1, or FXAM instruction), where the direction of the branch depends on\r\nthe state of the FPU condition code flags. (See the section titled \"Branching and Conditional Moves on FPU Condi-\r\ntion Codes\" in Chapter 8 of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1.) This\r\ninstruction can also be used to invoke exception handlers (by examining the exception flags) in environments that\r\ndo not use interrupts. When the FNSTSW AX instruction is executed, the AX register is updated before the\r\nprocessor executes any further instructions. The status stored in the AX register is thus guaranteed to be from the\r\ncompletion of the prior FPU instruction.\r\nThe assembler issues two instructions for the FSTSW instruction (an FWAIT instruction followed by an FNSTSW\r\ninstruction), and the processor executes each of these instructions separately. If an exception is generated for\r\neither of these instructions, the save EIP points to the instruction that caused the exception.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nIA-32 Architecture Compatibility\r\nWhen operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it is possible (under unusual\r\ncircumstances) for an FNSTSW instruction to be interrupted prior to being executed to handle a pending FPU\r\nexception. See the section titled \"No-Wait FPU Instructions Can Get FPU Interrupt in Window\" in Appendix D of the\r\nIntel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for a description of these circum-\r\nstances. An FNSTSW instruction cannot be interrupted in this way on later Intel processors, except for the Intel\r\nQuarkTM X1000 processor.\r\n\r\nOperation\r\nDEST <- FPUStatusWord;\r\n\r\nFPU Flags Affected\r\nThe C0, C1, C2, and C3 are undefined.\r\n\r\nFloating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination is located in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FSTSW"
},
{
"description": "FSUB/FSUBP/FISUB-Subtract\r\nOpcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\nD8 /4 FSUB m32fp Valid Valid Subtract m32fp from ST(0) and store result in ST(0).\r\nDC /4 FSUB m64fp Valid Valid Subtract m64fp from ST(0) and store result in ST(0).\r\nD8 E0+i FSUB ST(0), ST(i) Valid Valid Subtract ST(i) from ST(0) and store result in ST(0).\r\nDC E8+i FSUB ST(i), ST(0) Valid Valid Subtract ST(0) from ST(i) and store result in ST(i).\r\nDE E8+i FSUBP ST(i), ST(0) Valid Valid Subtract ST(0) from ST(i), store result in ST(i), and\r\n pop register stack.\r\nDE E9 FSUBP Valid Valid Subtract ST(0) from ST(1), store result in ST(1), and\r\n pop register stack.\r\nDA /4 FISUB m32int Valid Valid Subtract m32int from ST(0) and store result in ST(0).\r\nDE /4 FISUB m16int Valid Valid Subtract m16int from ST(0) and store result in ST(0).\r\n\r\n\r\n\r\nDescription\r\nSubtracts the source operand from the destination operand and stores the difference in the destination location.\r\nThe destination operand is always an FPU data register; the source operand can be a register or a memory location.\r\nSource operands in memory can be in single-precision or double-precision floating-point format or in word or\r\ndoubleword integer format.\r\nThe no-operand version of the instruction subtracts the contents of the ST(0) register from the ST(1) register and\r\nstores the result in ST(1). The one-operand version subtracts the contents of a memory location (either a floating-\r\npoint or an integer value) from the contents of the ST(0) register and stores the result in ST(0). The two-operand\r\nversion, subtracts the contents of the ST(0) register from the ST(i) register or vice versa.\r\nThe FSUBP instructions perform the additional operation of popping the FPU register stack following the subtrac-\r\ntion. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer\r\n(TOP) by 1. The no-operand version of the floating-point subtract instructions always results in the register stack\r\nbeing popped. In some assemblers, the mnemonic for this instruction is FSUB rather than FSUBP.\r\nThe FISUB instructions convert an integer source operand to double extended-precision floating-point format\r\nbefore performing the subtraction.\r\nTable 3-38 shows the results obtained when subtracting various classes of numbers from one another, assuming\r\nthat neither overflow nor underflow occurs. Here, the SRC value is subtracted from the DEST value (DEST - SRC =\r\nresult).\r\nWhen the difference between two operands of like sign is 0, the result is +0, except for the round toward -inf mode,\r\nin which case the result is -0. This instruction also guarantees that +0 - (-0) = +0, and that -0 - (+0) = -0. When the\r\nsource operand is an integer 0, it is treated as a +0.\r\nWhen one operand is inf, the result is inf of the expected sign. If both operands are inf of the same sign, an invalid-\r\noperation exception is generated.\r\n\r\n\r\n\r\n\r\n\r\n Table 3-38. FSUB/FSUBP/FISUB Results\r\n SRC\r\n -inf - F or - I -0 +0 + F or + I +inf NaN\r\n -inf * -inf -inf -inf -inf -inf NaN\r\n -F +inf +-F or +-0 DEST DEST -F -inf NaN\r\n DEST -0 +inf -SRC +-0 -0 - SRC -inf NaN\r\n +0 +inf -SRC +0 +-0 - SRC -inf NaN\r\n +F +inf +F DEST DEST +-F or +-0 -inf NaN\r\n +inf +inf +inf +inf +inf +inf * NaN\r\n NaN NaN NaN NaN NaN NaN NaN NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n I Means integer.\r\n * Indicates floating-point invalid-arithmetic-operand (#IA) exception.\r\n\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nIF Instruction = FISUB\r\n THEN\r\n DEST <- DEST - ConvertToDoubleExtendedPrecisionFP(SRC);\r\n ELSE (* Source operand is floating-point value *)\r\n DEST <- DEST - SRC;\r\nFI;\r\n\r\nIF Instruction = FSUBP\r\n THEN\r\n PopRegisterStack;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1 Set to 0 if stack underflow occurred.\r\n Set if result was rounded up; cleared otherwise.\r\nC0, C2, C3 Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow occurred.\r\n#IA Operand is an SNaN value or unsupported format.\r\n Operands are infinities of like sign.\r\n#D Source operand is a denormal value.\r\n#U Result is too small for destination format.\r\n#O Result is too large for destination format.\r\n#P Value cannot be represented exactly in destination format.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FSUB"
},
{
"description": "-R:FSUB",
"mnem": "FSUBP"
},
{
"description": "FSUBR/FSUBRP/FISUBR-Reverse Subtract\r\n Opcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\n D8 /5 FSUBR m32fp Valid Valid Subtract ST(0) from m32fp and store result in ST(0).\r\n DC /5 FSUBR m64fp Valid Valid Subtract ST(0) from m64fp and store result in ST(0).\r\n D8 E8+i FSUBR ST(0), ST(i) Valid Valid Subtract ST(0) from ST(i) and store result in ST(0).\r\n DC E0+i FSUBR ST(i), ST(0) Valid Valid Subtract ST(i) from ST(0) and store result in ST(i).\r\n DE E0+i FSUBRP ST(i), ST(0) Valid Valid Subtract ST(i) from ST(0), store result in ST(i), and\r\n pop register stack.\r\n DE E1 FSUBRP Valid Valid Subtract ST(1) from ST(0), store result in ST(1), and\r\n pop register stack.\r\n DA /5 FISUBR m32int Valid Valid Subtract ST(0) from m32int and store result in ST(0).\r\n DE /5 FISUBR m16int Valid Valid Subtract ST(0) from m16int and store result in ST(0).\r\n\r\n\r\n\r\nDescription\r\nSubtracts the destination operand from the source operand and stores the difference in the destination location.\r\nThe destination operand is always an FPU register; the source operand can be a register or a memory location.\r\nSource operands in memory can be in single-precision or double-precision floating-point format or in word or\r\ndoubleword integer format.\r\nThese instructions perform the reverse operations of the FSUB, FSUBP, and FISUB instructions. They are provided\r\nto support more efficient coding.\r\nThe no-operand version of the instruction subtracts the contents of the ST(1) register from the ST(0) register and\r\nstores the result in ST(1). The one-operand version subtracts the contents of the ST(0) register from the contents\r\nof a memory location (either a floating-point or an integer value) and stores the result in ST(0). The two-operand\r\nversion, subtracts the contents of the ST(i) register from the ST(0) register or vice versa.\r\nThe FSUBRP instructions perform the additional operation of popping the FPU register stack following the subtrac-\r\ntion. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer\r\n(TOP) by 1. The no-operand version of the floating-point reverse subtract instructions always results in the register\r\nstack being popped. In some assemblers, the mnemonic for this instruction is FSUBR rather than FSUBRP.\r\nThe FISUBR instructions convert an integer source operand to double extended-precision floating-point format\r\nbefore performing the subtraction.\r\nThe following table shows the results obtained when subtracting various classes of numbers from one another,\r\nassuming that neither overflow nor underflow occurs. Here, the DEST value is subtracted from the SRC value (SRC\r\n- DEST = result).\r\nWhen the difference between two operands of like sign is 0, the result is +0, except for the round toward -inf mode,\r\nin which case the result is -0. This instruction also guarantees that +0 - (-0) = +0, and that -0 - (+0) = -0. When the\r\nsource operand is an integer 0, it is treated as a +0.\r\nWhen one operand is inf, the result is inf of the expected sign. If both operands are inf of the same sign, an invalid-\r\noperation exception is generated.\r\n\r\n\r\n\r\n\r\n\r\n Table 3-39. FSUBR/FSUBRP/FISUBR Results\r\n SRC\r\n -inf -F or -I -0 +0 +F or +I +inf NaN\r\n -inf * +inf +inf +inf +inf +inf NaN\r\n -F -inf +-F or +-0 -DEST -DEST +F +inf NaN\r\n DEST -0 -inf SRC +-0 +0 SRC +inf NaN\r\n +0 -inf SRC -0 +-0 SRC +inf NaN\r\n +F -inf -F -DEST -DEST +-F or +-0 +inf NaN\r\n +inf -inf -inf -inf -inf -inf * NaN\r\n NaN NaN NaN NaN NaN NaN NaN NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n I Means integer.\r\n * Indicates floating-point invalid-arithmetic-operand (#IA) exception.\r\n\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nIF Instruction = FISUBR\r\n THEN\r\n DEST <- ConvertToDoubleExtendedPrecisionFP(SRC) - DEST;\r\n ELSE (* Source operand is floating-point value *)\r\n DEST <- SRC - DEST; FI;\r\nIF Instruction = FSUBRP\r\n THEN\r\n PopRegisterStack; FI;\r\n\r\nFPU Flags Affected\r\nC1 Set to 0 if stack underflow occurred.\r\n Set if result was rounded up; cleared otherwise.\r\nC0, C2, C3 Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow occurred.\r\n#IA Operand is an SNaN value or unsupported format.\r\n Operands are infinities of like sign.\r\n#D Source operand is a denormal value.\r\n#U Result is too small for destination format.\r\n#O Result is too large for destination format.\r\n#P Value cannot be represented exactly in destination format.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FSUBR"
},
{
"description": "-R:FSUBR",
"mnem": "FSUBRP"
},
{
"description": "FTST-TEST\r\nOpcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\nD9 E4 FTST Valid Valid Compare ST(0) with 0.0.\r\n\r\n\r\n\r\nDescription\r\nCompares the value in the ST(0) register with 0.0 and sets the condition code flags C0, C2, and C3 in the FPU\r\nstatus word according to the results (see table below).\r\n Table 3-40. FTST Results\r\n Condition C3 C2 C0\r\n ST(0) > 0.0 0 0 0\r\n ST(0) < 0.0 0 0 1\r\n ST(0) = 0.0 1 0 0\r\n Unordered 1 1 1\r\n\r\nThis instruction performs an \"unordered comparison.\" An unordered comparison also checks the class of the\r\nnumbers being compared (see \"FXAM-Examine Floating-Point\" in this chapter). If the value in register ST(0) is a\r\nNaN or is in an undefined format, the condition flags are set to \"unordered\" and the invalid operation exception is\r\ngenerated.\r\nThe sign of zero is ignored, so that (- 0.0 <- +0.0).\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nCASE (relation of operands) OF\r\n Not comparable: C3, C2, C0 <- 111;\r\n ST(0) > 0.0: C3, C2, C0 <- 000;\r\n ST(0) < 0.0: C3, C2, C0 <- 001;\r\n ST(0) = 0.0: C3, C2, C0 <- 100;\r\nESAC;\r\n\r\nFPU Flags Affected\r\nC1 Set to 0.\r\nC0, C2, C3 See Table 3-40.\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow occurred.\r\n#IA The source operand is a NaN value or is in an unsupported format.\r\n#D The source operand is a denormal value.\r\n\r\nProtected Mode Exceptions\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FTST"
},
{
"description": "FUCOM/FUCOMP/FUCOMPP-Unordered Compare Floating Point Values\r\nOpcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\nDD E0+i FUCOM ST(i) Valid Valid Compare ST(0) with ST(i).\r\nDD E1 FUCOM Valid Valid Compare ST(0) with ST(1).\r\nDD E8+i FUCOMP ST(i) Valid Valid Compare ST(0) with ST(i) and pop register stack.\r\nDD E9 FUCOMP Valid Valid Compare ST(0) with ST(1) and pop register stack.\r\nDA E9 FUCOMPP Valid Valid Compare ST(0) with ST(1) and pop register stack twice.\r\n\r\n\r\n\r\nDescription\r\nPerforms an unordered comparison of the contents of register ST(0) and ST(i) and sets condition code flags C0, C2,\r\nand C3 in the FPU status word according to the results (see the table below). If no operand is specified, the\r\ncontents of registers ST(0) and ST(1) are compared. The sign of zero is ignored, so that -0.0 is equal to +0.0.\r\n Table 3-41. FUCOM/FUCOMP/FUCOMPP Results\r\n Comparison Results* C3 C2 C0\r\n ST0 > ST(i) 0 0 0\r\n ST0 < ST(i) 0 0 1\r\n ST0 = ST(i) 1 0 0\r\n Unordered 1 1 1\r\n NOTES:\r\n * Flags not set if unmasked invalid-arithmetic-operand (#IA) exception is generated.\r\n\r\nAn unordered comparison checks the class of the numbers being compared (see \"FXAM-Examine Floating-Point\"\r\nin this chapter). The FUCOM/FUCOMP/FUCOMPP instructions perform the same operations as the\r\nFCOM/FCOMP/FCOMPP instructions. The only difference is that the FUCOM/FUCOMP/FUCOMPP instructions raise\r\nthe invalid-arithmetic-operand exception (#IA) only when either or both operands are an SNaN or are in an unsup-\r\nported format; QNaNs cause the condition code flags to be set to unordered, but do not cause an exception to be\r\ngenerated. The FCOM/FCOMP/FCOMPP instructions raise an invalid-operation exception when either or both of the\r\noperands are a NaN value of any kind or are in an unsupported format.\r\nAs with the FCOM/FCOMP/FCOMPP instructions, if the operation results in an invalid-arithmetic-operand exception\r\nbeing raised, the condition code flags are set only if the exception is masked.\r\nThe FUCOMP instruction pops the register stack following the comparison operation and the FUCOMPP instruction\r\npops the register stack twice following the comparison operation. To pop the register stack, the processor marks\r\nthe ST(0) register as empty and increments the stack pointer (TOP) by 1.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nCASE (relation of operands) OF\r\n ST > SRC: C3, C2, C0 <- 000;\r\n ST < SRC: C3, C2, C0 <- 001;\r\n ST = SRC: C3, C2, C0 <- 100;\r\nESAC;\r\n\r\nIF ST(0) or SRC = QNaN, but not SNaN or unsupported format\r\n THEN\r\n C3, C2, C0 <- 111;\r\n ELSE (* ST(0) or SRC is SNaN or unsupported format *)\r\n #IA;\r\n IF FPUControlWord.IM = 1\r\n THEN\r\n C3, C2, C0 <- 111;\r\n FI;\r\nFI;\r\n\r\nIF Instruction = FUCOMP\r\n THEN\r\n PopRegisterStack;\r\nFI;\r\n\r\nIF Instruction = FUCOMPP\r\n THEN\r\n PopRegisterStack;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1 Set to 0 if stack underflow occurred.\r\nC0, C2, C3 See Table 3-41.\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow occurred.\r\n#IA One or both operands are SNaN values or have unsupported formats. Detection of a QNaN\r\n value in and of itself does not raise an invalid-operand exception.\r\n#D One or both operands are denormal values.\r\n\r\nProtected Mode Exceptions\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FUCOM"
},
{
"description": "-R:FCOMI",
"mnem": "FUCOMI"
},
{
"description": "-R:FCOMI",
"mnem": "FUCOMIP"
},
{
"description": "-R:FUCOM",
"mnem": "FUCOMP"
},
{
"description": "-R:FUCOM",
"mnem": "FUCOMPP"
},
{
"description": "-R:WAIT",
"mnem": "FWAIT"
},
{
"description": "FXAM-Examine Floating-Point\r\n Opcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\n D9 E5 FXAM Valid Valid Classify value or number in ST(0).\r\n\r\n\r\n\r\nDescription\r\nExamines the contents of the ST(0) register and sets the condition code flags C0, C2, and C3 in the FPU status word\r\nto indicate the class of value or number in the register (see the table below).\r\n Table 3-42. FXAM Results\r\n.\r\n\r\n\r\n\r\n\r\n Class C3 C2 C0\r\n Unsupported 0 0 0\r\n NaN 0 0 1\r\n Normal finite number 0 1 0\r\n Infinity 0 1 1\r\n Zero 1 0 0\r\n Empty 1 0 1\r\n Denormal number 1 1 0\r\n\r\nThe C1 flag is set to the sign of the value in ST(0), regardless of whether the register is empty or full.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nC1 <- sign bit of ST; (* 0 for positive, 1 for negative *)\r\n\r\nCASE (class of value or number in ST(0)) OF\r\n Unsupported:C3, C2, C0 <- 000;\r\n NaN: C3, C2, C0 <- 001;\r\n Normal: C3, C2, C0 <- 010;\r\n Infinity: C3, C2, C0 <- 011;\r\n Zero: C3, C2, C0 <- 100;\r\n Empty: C3, C2, C0 <- 101;\r\n Denormal: C3, C2, C0 <- 110;\r\nESAC;\r\n\r\nFPU Flags Affected\r\nC1 Sign of value in ST(0).\r\nC0, C2, C3 See Table 3-42.\r\n\r\nFloating-Point Exceptions\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FXAM"
},
{
"description": "FXCH-Exchange Register Contents\r\nOpcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\nD9 C8+i FXCH ST(i) Valid Valid Exchange the contents of ST(0) and ST(i).\r\nD9 C9 FXCH Valid Valid Exchange the contents of ST(0) and ST(1).\r\n\r\n\r\n\r\nDescription\r\nExchanges the contents of registers ST(0) and ST(i). If no source operand is specified, the contents of ST(0) and\r\nST(1) are exchanged.\r\nThis instruction provides a simple means of moving values in the FPU register stack to the top of the stack [ST(0)],\r\nso that they can be operated on by those floating-point instructions that can only operate on values in ST(0). For\r\nexample, the following instruction sequence takes the square root of the third register from the top of the register\r\nstack:\r\n FXCH ST(3);\r\n FSQRT;\r\n FXCH ST(3);\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nIF (Number-of-operands) is 1\r\n THEN\r\n temp <- ST(0);\r\n ST(0) <- SRC;\r\n SRC <- temp;\r\n ELSE\r\n temp <- ST(0);\r\n ST(0) <- ST(1);\r\n ST(1) <- temp;\r\nFI;\r\n\r\nFPU Flags Affected\r\nC1 Set to 0.\r\nC0, C2, C3 Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow occurred.\r\n\r\nProtected Mode Exceptions\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FXCH"
},
{
"description": "FXRSTOR-Restore x87 FPU, MMX, XMM, and MXCSR State\r\n Opcode/ Op/ 64-Bit Compat/ Description\r\n Instruction En Mode Leg Mode\r\n 0F AE /1 M Valid Valid Restore the x87 FPU, MMX, XMM, and MXCSR\r\n FXRSTOR m512byte register state from m512byte.\r\n\r\n REX.W+ 0F AE /1 M Valid N.E. Restore the x87 FPU, MMX, XMM, and MXCSR\r\n FXRSTOR64 m512byte register state from m512byte.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (r) NA NA NA\r\n\r\nDescription\r\nReloads the x87 FPU, MMX technology, XMM, and MXCSR registers from the 512-byte memory image specified in\r\nthe source operand. This data should have been written to memory previously using the FXSAVE instruction, and\r\nin the same format as required by the operating modes. The first byte of the data should be located on a 16-byte\r\nboundary. There are three distinct layouts of the FXSAVE state map: one for legacy and compatibility mode, a\r\nsecond format for 64-bit mode FXSAVE/FXRSTOR with REX.W=0, and the third format is for 64-bit mode with\r\nFXSAVE64/FXRSTOR64. Table 3-43 shows the layout of the legacy/compatibility mode state information in memory\r\nand describes the fields in the memory image for the FXRSTOR and FXSAVE instructions. Table 3-46 shows the\r\nlayout of the 64-bit mode state information when REX.W is set (FXSAVE64/FXRSTOR64). Table 3-47 shows the\r\nlayout of the 64-bit mode state information when REX.W is clear (FXSAVE/FXRSTOR).\r\nThe state image referenced with an FXRSTOR instruction must have been saved using an FXSAVE instruction or be\r\nin the same format as required by Table 3-43, Table 3-46, or Table 3-47. Referencing a state image saved with an\r\nFSAVE, FNSAVE instruction or incompatible field layout will result in an incorrect state restoration.\r\nThe FXRSTOR instruction does not flush pending x87 FPU exceptions. To check and raise exceptions when loading\r\nx87 FPU state information with the FXRSTOR instruction, use an FWAIT instruction after the FXRSTOR instruction.\r\nIf the OSFXSR bit in control register CR4 is not set, the FXRSTOR instruction may not restore the states of the XMM\r\nand MXCSR registers. This behavior is implementation dependent.\r\nIf the MXCSR state contains an unmasked exception with a corresponding status flag also set, loading the register\r\nwith the FXRSTOR instruction will not result in a SIMD floating-point error condition being generated. Only the next\r\noccurrence of this unmasked exception will result in the exception being generated.\r\nBits 16 through 32 of the MXCSR register are defined as reserved and should be set to 0. Attempting to write a 1 in\r\nany of these bits from the saved state image will result in a general protection exception (#GP) being generated.\r\nBytes 464:511 of an FXSAVE image are available for software use. FXRSTOR ignores the content of bytes 464:511\r\nin an FXSAVE state image.\r\n\r\nOperation\r\nIF 64-Bit Mode\r\n THEN\r\n (x87 FPU, MMX, XMM15-XMM0, MXCSR) Load(SRC);\r\n ELSE\r\n (x87 FPU, MMX, XMM7-XMM0, MXCSR) <- Load(SRC);\r\nFI;\r\n\r\nx87 FPU and SIMD Floating-Point Exceptions\r\nNone.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.\r\n If a memory operand is not aligned on a 16-byte boundary, regardless of segment. (See align-\r\n ment check exception [#AC] below.)\r\n For an attempt to set reserved bits in MXCSR.\r\n#SS(0) For an illegal address in the SS segment.\r\n#PF(fault-code) For a page fault.\r\n#NM If CR0.TS[bit 3] = 1.\r\n If CR0.EM[bit 2] = 1.\r\n#UD If CPUID.01H:EDX.FXSR[bit 24] = 0.\r\n If instruction is preceded by a LOCK prefix.\r\n#AC If this exception is disabled a general protection exception (#GP) is signaled if the memory\r\n operand is not aligned on a 16-byte boundary, as described above. If the alignment check\r\n exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may\r\n vary with implementation, as follows. In all implementations where #AC is not signaled, a\r\n general protection exception is signaled in its place. In addition, the width of the alignment\r\n check may also vary with implementation. For instance, for a given implementation, an align-\r\n ment check exception might be signaled for a 2-byte misalignment, whereas a general protec-\r\n tion exception might be signaled for all other misalignments (4-, 8-, or 16-byte\r\n misalignments).\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand is not aligned on a 16-byte boundary, regardless of segment.\r\n If any part of the operand lies outside the effective address space from 0 to FFFFH.\r\n For an attempt to set reserved bits in MXCSR.\r\n#NM If CR0.TS[bit 3] = 1.\r\n If CR0.EM[bit 2] = 1.\r\n#UD If CPUID.01H:EDX.FXSR[bit 24] = 0.\r\n If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in real address mode.\r\n#PF(fault-code) For a page fault.\r\n#AC For unaligned memory reference.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n If memory operand is not aligned on a 16-byte boundary, regardless of segment.\r\n For an attempt to set reserved bits in MXCSR.\r\n#PF(fault-code) For a page fault.\r\n#NM If CR0.TS[bit 3] = 1.\r\n If CR0.EM[bit 2] = 1.\r\n#UD If CPUID.01H:EDX.FXSR[bit 24] = 0.\r\n If instruction is preceded by a LOCK prefix.\r\n#AC If this exception is disabled a general protection exception (#GP) is signaled if the memory\r\n operand is not aligned on a 16-byte boundary, as described above. If the alignment check\r\n exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may\r\n vary with implementation, as follows. In all implementations where #AC is not signaled, a\r\n general protection exception is signaled in its place. In addition, the width of the alignment\r\n check may also vary with implementation. For instance, for a given implementation, an align-\r\n ment check exception might be signaled for a 2-byte misalignment, whereas a general protec-\r\n tion exception might be signaled for all other misalignments (4-, 8-, or 16-byte\r\n misalignments).\r\n\r\n\r\n\r\n\r\n",
"mnem": "FXRSTOR"
},
{
"description": "FXSAVE-Save x87 FPU, MMX Technology, and SSE State\r\n Opcode/ Op/ 64-Bit Compat/ Description\r\n Instruction En Mode Leg Mode\r\n 0F AE /0 M Valid Valid Save the x87 FPU, MMX, XMM, and MXCSR\r\n FXSAVE m512byte register state to m512byte.\r\n\r\n REX.W+ 0F AE /0 M Valid N.E. Save the x87 FPU, MMX, XMM, and MXCSR\r\n FXSAVE64 m512byte register state to m512byte.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (w) NA NA NA\r\n\r\nDescription\r\nSaves the current state of the x87 FPU, MMX technology, XMM, and MXCSR registers to a 512-byte memory loca-\r\ntion specified in the destination operand. The content layout of the 512 byte region depends on whether the\r\nprocessor is operating in non-64-bit operating modes or 64-bit sub-mode of IA-32e mode.\r\nBytes 464:511 are available to software use. The processor does not write to bytes 464:511 of an FXSAVE area.\r\nThe operation of FXSAVE in non-64-bit modes is described first.\r\n\r\nNon-64-Bit Mode Operation\r\nTable 3-43 shows the layout of the state information in memory when the processor is operating in legacy modes.\r\n\r\n Table 3-43. Non-64-bit-Mode Layout of FXSAVE and FXRSTOR\r\n Memory Region\r\n 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0\r\n Rsvd FCS FIP[31:0] FOP Rsvd FTW FSW FCW 0\r\n MXCSR_MASK MXCSR Rsrvd FDS FDP[31:0] 16\r\n Reserved ST0/MM0 32\r\n Reserved ST1/MM1 48\r\n Reserved ST2/MM2 64\r\n Reserved ST3/MM3 80\r\n Reserved ST4/MM4 96\r\n Reserved ST5/MM5 112\r\n Reserved ST6/MM6 128\r\n Reserved ST7/MM7 144\r\n XMM0 160\r\n XMM1 176\r\n XMM2 192\r\n XMM3 208\r\n XMM4 224\r\n XMM5 240\r\n XMM6 256\r\n XMM7 272\r\n Reserved 288\r\n\r\n\r\n\r\n Table 3-43. Non-64-bit-Mode Layout of FXSAVE and FXRSTOR\r\n Memory Region (Contd.)\r\n 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0\r\n Reserved 304\r\n Reserved 320\r\n Reserved 336\r\n Reserved 352\r\n Reserved 368\r\n Reserved 384\r\n Reserved 400\r\n Reserved 416\r\n Reserved 432\r\n Reserved 448\r\n Available 464\r\n Available 480\r\n Available 496\r\n\r\nThe destination operand contains the first byte of the memory image, and it must be aligned on a 16-byte\r\nboundary. A misaligned destination operand will result in a general-protection (#GP) exception being generated (or\r\nin some cases, an alignment check exception [#AC]).\r\nThe FXSAVE instruction is used when an operating system needs to perform a context switch or when an exception\r\nhandler needs to save and examine the current state of the x87 FPU, MMX technology, and/or XMM and MXCSR\r\nregisters.\r\nThe fields in Table 3-43 are defined in Table 3-44.\r\n\r\n\r\n Table 3-44. Field Definitions\r\n Field Definition\r\n FCW x87 FPU Control Word (16 bits). See Figure 8-6 in the Intel 64 and IA-32 Architectures Software\r\n Developer's Manual, Volume 1, for the layout of the x87 FPU control word.\r\n FSW x87 FPU Status Word (16 bits). See Figure 8-4 in the Intel 64 and IA-32 Architectures Software\r\n Developer's Manual, Volume 1, for the layout of the x87 FPU status word.\r\n Abridged FTW x87 FPU Tag Word (8 bits). The tag information saved here is abridged, as described in the following\r\n paragraphs.\r\n FOP x87 FPU Opcode (16 bits). The lower 11 bits of this field contain the opcode, upper 5 bits are reserved.\r\n See Figure 8-8 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for\r\n the layout of the x87 FPU opcode field.\r\n FIP x87 FPU Instruction Pointer Offset (64 bits). The contents of this field differ depending on the current\r\n addressing mode (32-bit, 16-bit, or 64-bit) of the processor when the FXSAVE instruction was\r\n executed:\r\n 32-bit mode - 32-bit IP offset.\r\n 16-bit mode - low 16 bits are IP offset; high 16 bits are reserved.\r\n 64-bit mode with REX.W - 64-bit IP offset.\r\n 64-bit mode without REX.W - 32-bit IP offset.\r\n See \"x87 FPU Instruction and Operand (Data) Pointers\" in Chapter 8 of the Intel 64 and IA-32\r\n Architectures Software Developer's Manual, Volume 1, for a description of the x87 FPU instruction\r\n pointer.\r\n\r\n\r\n\r\n\r\n\r\n Table 3-44. Field Definitions (Contd.)\r\n Field Definition\r\n FCS x87 FPU Instruction Pointer Selector (16 bits). If CPUID.(EAX=07H,ECX=0H):EBX[bit 13] = 1, the\r\n processor deprecates FCS and FDS, and this field is saved as 0000H.\r\n FDP x87 FPU Instruction Operand (Data) Pointer Offset (64 bits). The contents of this field differ\r\n depending on the current addressing mode (32-bit, 16-bit, or 64-bit) of the processor when the\r\n FXSAVE instruction was executed:\r\n 32-bit mode - 32-bit DP offset.\r\n 16-bit mode - low 16 bits are DP offset; high 16 bits are reserved.\r\n 64-bit mode with REX.W - 64-bit DP offset.\r\n 64-bit mode without REX.W - 32-bit DP offset.\r\n See \"x87 FPU Instruction and Operand (Data) Pointers\" in Chapter 8 of the Intel 64 and IA-32\r\n Architectures Software Developer's Manual, Volume 1, for a description of the x87 FPU operand\r\n pointer.\r\n FDS x87 FPU Instruction Operand (Data) Pointer Selector (16 bits). If CPUID.(EAX=07H,ECX=0H):EBX[bit\r\n 13] = 1, the processor deprecates FCS and FDS, and this field is saved as 0000H.\r\n MXCSR MXCSR Register State (32 bits). See Figure 10-3 in the Intel 64 and IA-32 Architectures Software\r\n Developer's Manual, Volume 1, for the layout of the MXCSR register. If the OSFXSR bit in control\r\n register CR4 is not set, the FXSAVE instruction may not save this register. This behavior is\r\n implementation dependent.\r\n MXCSR_ MXCSR_MASK (32 bits). This mask can be used to adjust values written to the MXCSR register,\r\n MASK ensuring that reserved bits are set to 0. Set the mask bits and flags in MXCSR to the mode of\r\n operation desired for SSE and SSE2 SIMD floating-point instructions. See \"Guidelines for Writing to the\r\n MXCSR Register\" in Chapter 11 of the Intel 64 and IA-32 Architectures Software Developer's Manual,\r\n Volume 1, for instructions for how to determine and use the MXCSR_MASK value.\r\n ST0/MM0 through x87 FPU or MMX technology registers. These 80-bit fields contain the x87 FPU data registers or the\r\n ST7/MM7 MMX technology registers, depending on the state of the processor prior to the execution of the\r\n FXSAVE instruction. If the processor had been executing x87 FPU instruction prior to the FXSAVE\r\n instruction, the x87 FPU data registers are saved; if it had been executing MMX instructions (or SSE or\r\n SSE2 instructions that operated on the MMX technology registers), the MMX technology registers are\r\n saved. When the MMX technology registers are saved, the high 16 bits of the field are reserved.\r\n XMM0 through XMM7 XMM registers (128 bits per field). If the OSFXSR bit in control register CR4 is not set, the FXSAVE\r\n instruction may not save these registers. This behavior is implementation dependent.\r\n\r\nThe FXSAVE instruction saves an abridged version of the x87 FPU tag word in the FTW field (unlike the FSAVE\r\ninstruction, which saves the complete tag word). The tag information is saved in physical register order (R0\r\nthrough R7), rather than in top-of-stack (TOS) order. With the FXSAVE instruction, however, only a single bit (1 for\r\nvalid or 0 for empty) is saved for each tag. For example, assume that the tag word is currently set as follows:\r\n\r\n R7 R6 R5 R4 R3 R2 R1 R0\r\n 11 xx xx xx 11 11 11 11\r\nHere, 11B indicates empty stack elements and \"xx\" indicates valid (00B), zero (01B), or special (10B).\r\nFor this example, the FXSAVE instruction saves only the following 8 bits of information:\r\n\r\n R7 R6 R5 R4 R3 R2 R1 R0\r\n 0 1 1 1 0 0 0 0\r\nHere, a 1 is saved for any valid, zero, or special tag, and a 0 is saved for any empty tag.\r\nThe operation of the FXSAVE instruction differs from that of the FSAVE instruction, the as follows:\r\n. FXSAVE instruction does not check for pending unmasked floating-point exceptions. (The FXSAVE operation in\r\n this regard is similar to the operation of the FNSAVE instruction).\r\n. After the FXSAVE instruction has saved the state of the x87 FPU, MMX technology, XMM, and MXCSR registers,\r\n the processor retains the contents of the registers. Because of this behavior, the FXSAVE instruction cannot be\r\n\r\n\r\n\r\n used by an application program to pass a \"clean\" x87 FPU state to a procedure, since it retains the current\r\n state. To clean the x87 FPU state, an application must explicitly execute an FINIT instruction after an FXSAVE\r\n instruction to reinitialize the x87 FPU state.\r\n. The format of the memory image saved with the FXSAVE instruction is the same regardless of the current\r\n addressing mode (32-bit or 16-bit) and operating mode (protected, real address, or system management).\r\n This behavior differs from the FSAVE instructions, where the memory image format is different depending on\r\n the addressing mode and operating mode. Because of the different image formats, the memory image saved\r\n with the FXSAVE instruction cannot be restored correctly with the FRSTOR instruction, and likewise the state\r\n saved with the FSAVE instruction cannot be restored correctly with the FXRSTOR instruction.\r\nThe FSAVE format for FTW can be recreated from the FTW valid bits and the stored 80-bit FP data (assuming the\r\nstored data was not the contents of MMX technology registers) using Table 3-45.\r\n\r\n Table 3-45. Recreating FSAVE Format\r\n Exponent Exponent Fraction J and M FTW valid bit\r\n all 1's all 0's all 0's bits x87 FTW\r\n 0 0 0 0x 1 Special 10\r\n 0 0 0 1x 1 Valid 00\r\n 0 0 1 00 1 Special 10\r\n 0 0 1 10 1 Valid 00\r\n 0 1 0 0x 1 Special 10\r\n 0 1 0 1x 1 Special 10\r\n 0 1 1 00 1 Zero 01\r\n 0 1 1 10 1 Special 10\r\n 1 0 0 1x 1 Special 10\r\n 1 0 0 1x 1 Special 10\r\n 1 0 1 00 1 Special 10\r\n 1 0 1 10 1 Special 10\r\n For all legal combinations above. 0 Empty 11\r\n\r\nThe J-bit is defined to be the 1-bit binary integer to the left of the decimal place in the significand. The M-bit is\r\ndefined to be the most significant bit of the fractional portion of the significand (i.e., the bit immediately to the right\r\nof the decimal place).\r\nWhen the M-bit is the most significant bit of the fractional portion of the significand, it must be 0 if the fraction is all\r\n0's.\r\n\r\nIA-32e Mode Operation\r\nIn compatibility sub-mode of IA-32e mode, legacy SSE registers, XMM0 through XMM7, are saved according to the\r\nlegacy FXSAVE map. In 64-bit mode, all of the SSE registers, XMM0 through XMM15, are saved. Additionally, there\r\nare two different layouts of the FXSAVE map in 64-bit mode, corresponding to FXSAVE64 (which requires\r\nREX.W=1) and FXSAVE (REX.W=0). In the FXSAVE64 map (Table 3-46), the FPU IP and FPU DP pointers are 64-bit\r\nwide. In the FXSAVE map for 64-bit mode (Table 3-47), the FPU IP and FPU DP pointers are 32-bits.\r\n\r\n\r\n\r\n\r\n\r\n Table 3-46. Layout of the 64-bit-mode FXSAVE64 Map\r\n (requires REX.W = 1)\r\n 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0\r\n FIP FOP Reserved FTW FSW FCW 0\r\n MXCSR_MASK MXCSR FDP 16\r\n Reserved ST0/MM0 32\r\n Reserved ST1/MM1 48\r\n Reserved ST2/MM2 64\r\n Reserved ST3/MM3 80\r\n Reserved ST4/MM4 96\r\n Reserved ST5/MM5 112\r\n Reserved ST6/MM6 128\r\n Reserved ST7/MM7 144\r\n XMM0 160\r\n XMM1 176\r\n XMM2 192\r\n XMM3 208\r\n XMM4 224\r\n XMM5 240\r\n XMM6 256\r\n XMM7 272\r\n XMM8 288\r\n XMM9 304\r\n XMM10 320\r\n XMM11 336\r\n XMM12 352\r\n XMM13 368\r\n XMM14 384\r\n XMM15 400\r\n Reserved 416\r\n Reserved 432\r\n Reserved 448\r\n Available 464\r\n Available 480\r\n Available 496\r\n\r\n\r\n\r\n\r\n\r\n Table 3-47. Layout of the 64-bit-mode FXSAVE Map (REX.W = 0)\r\n 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0\r\n Reserved FCS FIP[31:0] FOP Reserved FTW FSW FCW 0\r\n MXCSR_MASK MXCSR Reserved FDS FDP[31:0] 16\r\n Reserved ST0/MM0 32\r\n Reserved ST1/MM1 48\r\n Reserved ST2/MM2 64\r\n Reserved ST3/MM3 80\r\n Reserved ST4/MM4 96\r\n Reserved ST5/MM5 112\r\n Reserved ST6/MM6 128\r\n Reserved ST7/MM7 144\r\n XMM0 160\r\n XMM1 176\r\n XMM2 192\r\n XMM3 208\r\n XMM4 224\r\n XMM5 240\r\n XMM6 256\r\n XMM7 272\r\n XMM8 288\r\n XMM9 304\r\n XMM10 320\r\n XMM11 336\r\n XMM12 352\r\n XMM13 368\r\n XMM14 384\r\n XMM15 400\r\n Reserved 416\r\n Reserved 432\r\n Reserved 448\r\n Available 464\r\n Available 480\r\n Available 496\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIF 64-Bit Mode\r\n THEN\r\n IF REX.W = 1\r\n THEN\r\n DEST <- Save64BitPromotedFxsave(x87 FPU, MMX, XMM15-XMM0,\r\n MXCSR);\r\n ELSE\r\n DEST <- Save64BitDefaultFxsave(x87 FPU, MMX, XMM15-XMM0, MXCSR);\r\n FI;\r\n ELSE\r\n DEST <- SaveLegacyFxsave(x87 FPU, MMX, XMM7-XMM0, MXCSR);\r\nFI;\r\n\r\nProtected Mode Exceptions\r\n#GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.\r\n If a memory operand is not aligned on a 16-byte boundary, regardless of segment. (See the\r\n description of the alignment check exception [#AC] below.)\r\n#SS(0) For an illegal address in the SS segment.\r\n#PF(fault-code) For a page fault.\r\n#NM If CR0.TS[bit 3] = 1.\r\n If CR0.EM[bit 2] = 1.\r\n#UD If CPUID.01H:EDX.FXSR[bit 24] = 0.\r\n#UD If the LOCK prefix is used.\r\n#AC If this exception is disabled a general protection exception (#GP) is signaled if the memory\r\n operand is not aligned on a 16-byte boundary, as described above. If the alignment check\r\n exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may\r\n vary with implementation, as follows. In all implementations where #AC is not signaled, a\r\n general protection exception is signaled in its place. In addition, the width of the alignment\r\n check may also vary with implementation. For instance, for a given implementation, an align-\r\n ment check exception might be signaled for a 2-byte misalignment, whereas a general protec-\r\n tion exception might be signaled for all other misalignments (4-, 8-, or 16-byte\r\n misalignments).\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand is not aligned on a 16-byte boundary, regardless of segment.\r\n If any part of the operand lies outside the effective address space from 0 to FFFFH.\r\n#NM If CR0.TS[bit 3] = 1.\r\n If CR0.EM[bit 2] = 1.\r\n#UD If CPUID.01H:EDX.FXSR[bit 24] = 0.\r\n If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in real address mode.\r\n#PF(fault-code) For a page fault.\r\n#AC For unaligned memory reference.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n If memory operand is not aligned on a 16-byte boundary, regardless of segment.\r\n#PF(fault-code) For a page fault.\r\n#NM If CR0.TS[bit 3] = 1.\r\n If CR0.EM[bit 2] = 1.\r\n#UD If CPUID.01H:EDX.FXSR[bit 24] = 0.\r\n If the LOCK prefix is used.\r\n#AC If this exception is disabled a general protection exception (#GP) is signaled if the memory\r\n operand is not aligned on a 16-byte boundary, as described above. If the alignment check\r\n exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may\r\n vary with implementation, as follows. In all implementations where #AC is not signaled, a\r\n general protection exception is signaled in its place. In addition, the width of the alignment\r\n check may also vary with implementation. For instance, for a given implementation, an align-\r\n ment check exception might be signaled for a 2-byte misalignment, whereas a general protec-\r\n tion exception might be signaled for all other misalignments (4-, 8-, or 16-byte\r\n misalignments).\r\n\r\nImplementation Note\r\nThe order in which the processor signals general-protection (#GP) and page-fault (#PF) exceptions when they both\r\noccur on an instruction boundary is given in Table 5-2 in the Intel 64 and IA-32 Architectures Software Devel-\r\noper's Manual, Volume 3B. This order vary for FXSAVE for different processor implementations.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FXSAVE"
},
{
"description": "FXTRACT-Extract Exponent and Significand\r\n Opcode/ 64-Bit Compat/ Description\r\n Instruction Mode Leg Mode\r\n D9 F4 Valid Valid Separate value in ST(0) into exponent and significand, store\r\n FXTRACT exponent in ST(0), and push the significand onto the register\r\n stack.\r\n\r\n\r\n\r\nDescription\r\nSeparates the source value in the ST(0) register into its exponent and significand, stores the exponent in ST(0),\r\nand pushes the significand onto the register stack. Following this operation, the new top-of-stack register ST(0)\r\ncontains the value of the original significand expressed as a floating-point value. The sign and significand of this\r\nvalue are the same as those found in the source operand, and the exponent is 3FFFH (biased value for a true expo-\r\nnent of zero). The ST(1) register contains the value of the original operand's true (unbiased) exponent expressed\r\nas a floating-point value. (The operation performed by this instruction is a superset of the IEEE-recommended\r\nlogb(x) function.)\r\nThis instruction and the F2XM1 instruction are useful for performing power and range scaling operations. The\r\nFXTRACT instruction is also useful for converting numbers in double extended-precision floating-point format to\r\ndecimal representations (e.g., for printing or displaying).\r\nIf the floating-point zero-divide exception (#Z) is masked and the source operand is zero, an exponent value of -\r\ninf is stored in register ST(1) and 0 with the sign of the source operand is stored in register ST(0).\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nTEMP <- Significand(ST(0));\r\nST(0) <- Exponent(ST(0));\r\nTOP<- TOP - 1;\r\nST(0) <- TEMP;\r\n\r\nFPU Flags Affected\r\nC1 Set to 0 if stack underflow occurred; set to 1 if stack overflow occurred.\r\nC0, C2, C3 Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow or overflow occurred.\r\n#IA Source operand is an SNaN value or unsupported format.\r\n#Z ST(0) operand is +-0.\r\n#D Source operand is a denormal value.\r\n\r\nProtected Mode Exceptions\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FXTRACT"
},
{
"description": "FYL2X-Compute y * log2x\r\nOpcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\nD9 F1 FYL2X Valid Valid Replace ST(1) with (ST(1) * log2ST(0)) and pop the\r\n register stack.\r\n\r\n\r\n\r\nDescription\r\nComputes (ST(1) * log2 (ST(0))), stores the result in resister ST(1), and pops the FPU register stack. The source\r\noperand in ST(0) must be a non-zero positive number.\r\nThe following table shows the results obtained when taking the log of various classes of numbers, assuming that\r\nneither overflow nor underflow occurs.\r\n Table 3-48. FYL2X Results\r\n ST(0)\r\n -inf -F +-0 +0<+F<+1 +1 +F>+1 +inf NaN\r\n\r\n -inf * * +inf +inf * -inf -inf NaN\r\n\r\n ST(1) -F * * ** +F -0 -F -inf NaN\r\n\r\n -0 * * * +0 -0 -0 * NaN\r\n\r\n +0 * * * -0 +0 +0 * NaN\r\n\r\n +F * * ** -F +0 +F +inf NaN\r\n\r\n +inf * * - inf -inf * +inf +inf NaN\r\n\r\n NaN NaN NaN NaN NaN NaN NaN NaN NaN\r\n\r\n NOTES:\r\n F Means finite floating-point value.\r\n * Indicates floating-point invalid-operation (#IA) exception.\r\n ** Indicates floating-point zero-divide (#Z) exception.\r\n\r\n\r\nIf the divide-by-zero exception is masked and register ST(0) contains +-0, the instruction returns inf with a sign that\r\nis the opposite of the sign of the source operand in register ST(1).\r\nThe FYL2X instruction is designed with a built-in multiplication to optimize the calculation of logarithms with an\r\narbitrary positive base (b):\r\n\r\n logbx <- (log2b)-1 * log2x\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nST(1) <- ST(1) * log2ST(0);\r\nPopRegisterStack;\r\n\r\nFPU Flags Affected\r\nC1 Set to 0 if stack underflow occurred.\r\n Set if result was rounded up; cleared otherwise.\r\nC0, C2, C3 Undefined.\r\n\r\n\r\n\r\n\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow occurred.\r\n#IA Either operand is an SNaN or unsupported format.\r\n Source operand in register ST(0) is a negative finite value\r\n (not -0).\r\n#Z Source operand in register ST(0) is +-0.\r\n#D Source operand is a denormal value.\r\n#U Result is too small for destination format.\r\n#O Result is too large for destination format.\r\n#P Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FYL2X"
},
{
"description": "FYL2XP1-Compute y * log2(x +1)\r\n Opcode Instruction 64-Bit Compat/ Description\r\n Mode Leg Mode\r\n D9 F9 FYL2XP1 Valid Valid Replace ST(1) with ST(1) * log2(ST(0) + 1.0) and pop the\r\n register stack.\r\n\r\n\r\n\r\nDescription\r\nComputes (ST(1) * log2(ST(0) + 1.0)), stores the result in register ST(1), and pops the FPU register stack. The\r\nsource operand in ST(0) must be in the range:\r\n - ( 1 - 2 / 2 ) )to ( 1 - 2 / 2 )\r\nThe source operand in ST(1) can range from -inf to +inf. If the ST(0) operand is outside of its acceptable range, the\r\nresult is undefined and software should not rely on an exception being generated. Under some circumstances\r\nexceptions may be generated when ST(0) is out of range, but this behavior is implementation specific and not\r\nguaranteed.\r\nThe following table shows the results obtained when taking the log epsilon of various classes of numbers, assuming\r\nthat underflow does not occur.\r\n Table 3-49. FYL2XP1 Results\r\n ST(0)\r\n -(1 - ( 2 / 2 )) to -0 -0 +0 +0 to +(1 - ( 2 / 2 )) NaN\r\n -inf +inf * * -inf NaN\r\n ST(1) -F +F +0 -0 -F NaN\r\n -0 +0 +0 -0 -0 NaN\r\n +0 -0 -0 +0 +0 NaN\r\n +F -F -0 +0 +F NaN\r\n +inf -inf * * +inf NaN\r\n NaN NaN NaN NaN NaN NaN\r\n NOTES:\r\n F Means finite floating-point value.\r\n * Indicates floating-point invalid-operation (#IA) exception.\r\n\r\nThis instruction provides optimal accuracy for values of epsilon [the value in register ST(0)] that are close to 0. For\r\nsmall epsilon (e) values, more significant digits can be retained by using the FYL2XP1 instruction than by using\r\n(e+1) as an argument to the FYL2X instruction. The (e+1) expression is commonly found in compound interest and\r\nannuity calculations. The result can be simply converted into a value in another logarithm base by including a scale\r\nfactor in the ST(1) source operand. The following equation is used to calculate the scale factor for a particular loga-\r\nrithm base, where n is the logarithm base desired for the result of the FYL2XP1 instruction:\r\n\r\n scale factor <- logn 2\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nST(1) <- ST(1) * log2(ST(0) + 1.0);\r\nPopRegisterStack;\r\n\r\n\r\n\r\n\r\n\r\nFPU Flags Affected\r\nC1 Set to 0 if stack underflow occurred.\r\n Set if result was rounded up; cleared otherwise.\r\nC0, C2, C3 Undefined.\r\n\r\nFloating-Point Exceptions\r\n#IS Stack underflow occurred.\r\n#IA Either operand is an SNaN value or unsupported format.\r\n#D Source operand is a denormal value.\r\n#U Result is too small for destination format.\r\n#O Result is too large for destination format.\r\n#P Value cannot be represented exactly in destination format.\r\n\r\nProtected Mode Exceptions\r\n#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.\r\n#MF If there is a pending x87 FPU exception.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "FYL2XP1"
},
{
"description": "HADDPD-Packed Double-FP Horizontal Add\r\n Opcode/ Op/ 64/32-bit CPUID Description\r\n Instruction En Mode Feature\r\n Flag\r\n 66 0F 7C /r RM V/V SSE3 Horizontal add packed double-precision\r\n HADDPD xmm1, xmm2/m128 floating-point values from xmm2/m128 to\r\n xmm1.\r\n VEX.NDS.128.66.0F.WIG 7C /r RVM V/V AVX Horizontal add packed double-precision\r\n VHADDPD xmm1,xmm2, xmm3/m128 floating-point values from xmm2 and\r\n xmm3/mem.\r\n VEX.NDS.256.66.0F.WIG 7C /r RVM V/V AVX Horizontal add packed double-precision\r\n VHADDPD ymm1, ymm2, ymm3/m256 floating-point values from ymm2 and\r\n ymm3/mem.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nAdds the double-precision floating-point values in the high and low quadwords of the destination operand and\r\nstores the result in the low quadword of the destination operand.\r\nAdds the double-precision floating-point values in the high and low quadwords of the source operand and stores the\r\nresult in the high quadword of the destination operand.\r\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).\r\nSee Figure 3-16 for HADDPD; see Figure 3-17 for VHADDPD.\r\n\r\n\r\n\r\n\r\n HADDPD xmm1, xmm2/m128\r\n\r\n xmm2\r\n [127:64] [63:0]\r\n /m128\r\n\r\n\r\n\r\n\r\n [127:64] [63:0] xmm1\r\n\r\n\r\n\r\n\r\n xmm2/m128[63:0] + Result:\r\n xmm1[63:0] + xmm1[127:64]\r\n xmm2/m128[127:64] xmm1\r\n\r\n [127:64] [63:0]\r\n\r\n\r\n OM15993\r\n\r\n\r\n\r\n Figure 3-16. HADDPD-Packed Double-FP Horizontal Add\r\n\r\n\r\n\r\n\r\n\r\n SRC1 X3 X2 X1 X0\r\n\r\n\r\n\r\n SRC2 Y3 Y2 Y1 Y0\r\n\r\n\r\n\r\n DEST Y2 + Y3 X2 + X3 Y0 + Y1 X0 + X1\r\n\r\n\r\n\r\n\r\n Figure 3-17. VHADDPD operation\r\n\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding\r\nYMM register destination are unmodified.\r\nVEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination\r\noperand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are\r\nzeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register.\r\n\r\nOperation\r\nHADDPD (128-bit Legacy SSE version)\r\nDEST[63:0] <- SRC1[127:64] + SRC1[63:0]\r\nDEST[127:64] <- SRC2[127:64] + SRC2[63:0]\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVHADDPD (VEX.128 encoded version)\r\nDEST[63:0] <- SRC1[127:64] + SRC1[63:0]\r\nDEST[127:64] <- SRC2[127:64] + SRC2[63:0]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVHADDPD (VEX.256 encoded version)\r\nDEST[63:0] <- SRC1[127:64] + SRC1[63:0]\r\nDEST[127:64] <- SRC2[127:64] + SRC2[63:0]\r\nDEST[191:128] <- SRC1[255:192] + SRC1[191:128]\r\nDEST[255:192] <- SRC2[255:192] + SRC2[191:128]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVHADDPD: __m256d _mm256_hadd_pd (__m256d a, __m256d b);\r\n\r\nHADDPD: __m128d _mm_hadd_pd (__m128d a, __m128d b);\r\n\r\nExceptions\r\nWhen the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-\r\nprotection exception (#GP) will be generated.\r\n\r\n\r\n\r\n\r\n\r\nNumeric Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nSee Exceptions Type 2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "HADDPD"
},
{
"description": "HADDPS-Packed Single-FP Horizontal Add\r\nOpcode/ Op/ 64/32-bit CPUID Description\r\nInstruction En Mode Feature\r\n Flag\r\nF2 0F 7C /r RM V/V SSE3 Horizontal add packed single-precision\r\nHADDPS xmm1, xmm2/m128 floating-point values from xmm2/m128 to\r\n xmm1.\r\nVEX.NDS.128.F2.0F.WIG 7C /r RVM V/V AVX Horizontal add packed single-precision\r\nVHADDPS xmm1, xmm2, xmm3/m128 floating-point values from xmm2 and\r\n xmm3/mem.\r\nVEX.NDS.256.F2.0F.WIG 7C /r RVM V/V AVX Horizontal add packed single-precision\r\nVHADDPS ymm1, ymm2, ymm3/m256 floating-point values from ymm2 and\r\n ymm3/mem.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nAdds the single-precision floating-point values in the first and second dwords of the destination operand and stores\r\nthe result in the first dword of the destination operand.\r\nAdds single-precision floating-point values in the third and fourth dword of the destination operand and stores the\r\nresult in the second dword of the destination operand.\r\nAdds single-precision floating-point values in the first and second dword of the source operand and stores the\r\nresult in the third dword of the destination operand.\r\nAdds single-precision floating-point values in the third and fourth dword of the source operand and stores the result\r\nin the fourth dword of the destination operand.\r\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).\r\n\r\n\r\n\r\n\r\n\r\nSee Figure 3-18 for HADDPS; see Figure 3-19 for VHADDPS.\r\n\r\n\r\n\r\n HADDPS xmm1, xmm2/m128\r\n\r\n xmm2/\r\n [127:96] [95:64] [63:32] [31:0]\r\n m128\r\n\r\n\r\n\r\n\r\n [127:96] [95:64] [63:32] [31:0] xmm1\r\n\r\n\r\n\r\n\r\n xmm2/m128 xmm2/m128\r\n xmm1[95:64] + xmm1[31:0] + RESULT:\r\n [95:64] + xmm2/ [31:0] + xmm2/\r\n xmm1[127:96] xmm1[63:32] xmm1\r\n m128[127:96] m128[63:32]\r\n\r\n\r\n [127:96] [95:64] [63:32] [31:0]\r\n\r\n\r\n OM15994\r\n\r\n\r\n Figure 3-18. HADDPS-Packed Single-FP Horizontal Add\r\n\r\n\r\n\r\n\r\n SRC1 X7 X6 X5 X4 X3 X2 X1 X0\r\n\r\n\r\n\r\n SRC2 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0\r\n\r\n\r\n\r\n DEST Y6+Y7 Y4+Y5 X6+X7 X4+X5 Y2+Y3 Y0+Y1 X2+X3 X0+X1\r\n\r\n\r\n\r\n\r\n Figure 3-19. VHADDPS operation\r\n\r\n\r\n\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding\r\nYMM register destination are unmodified.\r\nVEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination\r\noperand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are\r\nzeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nHADDPS (128-bit Legacy SSE version)\r\nDEST[31:0] <- SRC1[63:32] + SRC1[31:0]\r\nDEST[63:32] <- SRC1[127:96] + SRC1[95:64]\r\nDEST[95:64] <- SRC2[63:32] + SRC2[31:0]\r\nDEST[127:96] <- SRC2[127:96] + SRC2[95:64]\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVHADDPS (VEX.128 encoded version)\r\nDEST[31:0] <- SRC1[63:32] + SRC1[31:0]\r\nDEST[63:32] <- SRC1[127:96] + SRC1[95:64]\r\nDEST[95:64] <- SRC2[63:32] + SRC2[31:0]\r\nDEST[127:96] <- SRC2[127:96] + SRC2[95:64]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVHADDPS (VEX.256 encoded version)\r\nDEST[31:0] <- SRC1[63:32] + SRC1[31:0]\r\nDEST[63:32] <- SRC1[127:96] + SRC1[95:64]\r\nDEST[95:64] <- SRC2[63:32] + SRC2[31:0]\r\nDEST[127:96] <- SRC2[127:96] + SRC2[95:64]\r\nDEST[159:128] <- SRC1[191:160] + SRC1[159:128]\r\nDEST[191:160] <- SRC1[255:224] + SRC1[223:192]\r\nDEST[223:192] <- SRC2[191:160] + SRC2[159:128]\r\nDEST[255:224] <- SRC2[255:224] + SRC2[223:192]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nHADDPS: __m128 _mm_hadd_ps (__m128 a, __m128 b);\r\n\r\nVHADDPS: __m256 _mm256_hadd_ps (__m256 a, __m256 b);\r\n\r\nExceptions\r\nWhen the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-\r\nprotection exception (#GP) will be generated.\r\n\r\nNumeric Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nSee Exceptions Type 2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "HADDPS"
},
{
"description": "HLT-Halt\r\nOpcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\nF4 HLT NP Valid Valid Halt\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nStops instruction execution and places the processor in a HALT state. An enabled interrupt (including NMI and\r\nSMI), a debug exception, the BINIT# signal, the INIT# signal, or the RESET# signal will resume execution. If an\r\ninterrupt (including NMI) is used to resume execution after a HLT instruction, the saved instruction pointer\r\n(CS:EIP) points to the instruction following the HLT instruction.\r\nWhen a HLT instruction is executed on an Intel 64 or IA-32 processor supporting Intel Hyper-Threading Technology,\r\nonly the logical processor that executes the instruction is halted. The other logical processors in the physical\r\nprocessor remain active, unless they are each individually halted by executing a HLT instruction.\r\nThe HLT instruction is a privileged instruction. When the processor is running in protected or virtual-8086 mode,\r\nthe privilege level of a program or procedure must be 0 to execute the HLT instruction.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nEnter Halt state;\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the current privilege level is not 0.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nNone.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "HLT"
},
{
"description": "HSUBPD-Packed Double-FP Horizontal Subtract\r\nOpcode/ Op/ 64/32-bit CPUID Description\r\nInstruction En Mode Feature\r\n Flag\r\n66 0F 7D /r RM V/V SSE3 Horizontal subtract packed double-precision\r\nHSUBPD xmm1, xmm2/m128 floating-point values from xmm2/m128 to\r\n xmm1.\r\nVEX.NDS.128.66.0F.WIG 7D /r RVM V/V AVX Horizontal subtract packed double-precision\r\nVHSUBPD xmm1,xmm2, xmm3/m128 floating-point values from xmm2 and\r\n xmm3/mem.\r\nVEX.NDS.256.66.0F.WIG 7D /r RVM V/V AVX Horizontal subtract packed double-precision\r\nVHSUBPD ymm1, ymm2, ymm3/m256 floating-point values from ymm2 and\r\n ymm3/mem.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nThe HSUBPD instruction subtracts horizontally the packed DP FP numbers of both operands.\r\nSubtracts the double-precision floating-point value in the high quadword of the destination operand from the low\r\nquadword of the destination operand and stores the result in the low quadword of the destination operand.\r\nSubtracts the double-precision floating-point value in the high quadword of the source operand from the low quad-\r\nword of the source operand and stores the result in the high quadword of the destination operand.\r\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).\r\n\r\n\r\nSee Figure 3-20 for HSUBPD; see Figure 3-21 for VHSUBPD.\r\n\r\n\r\n HSUBPD xmm1, xmm2/m128\r\n\r\n xmm2\r\n [127:64] [63:0]\r\n /m128\r\n\r\n\r\n\r\n\r\n [127:64] [63:0] xmm1\r\n\r\n\r\n\r\n\r\n xmm2/m128[63:0] - Result:\r\n xmm1[63:0] - xmm1[127:64]\r\n xmm2/m128[127:64] xmm1\r\n\r\n [127:64] [63:0]\r\n\r\n\r\n OM15995\r\n\r\n\r\n\r\n Figure 3-20. HSUBPD-Packed Double-FP Horizontal Subtract\r\n\r\n\r\n\r\n\r\n\r\n SRC1 X3 X2 X1 X0\r\n\r\n\r\n\r\n SRC2 Y3 Y2 Y1 Y0\r\n\r\n\r\n\r\n DEST Y2 - Y3 X2 - X3 Y0 - Y1 X0 - X1\r\n\r\n\r\n\r\n\r\n Figure 3-21. VHSUBPD operation\r\n\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding\r\nYMM register destination are unmodified.\r\nVEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination\r\noperand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are\r\nzeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register.\r\n\r\nOperation\r\nHSUBPD (128-bit Legacy SSE version)\r\nDEST[63:0] <- SRC1[63:0] - SRC1[127:64]\r\nDEST[127:64] <- SRC2[63:0] - SRC2[127:64]\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVHSUBPD (VEX.128 encoded version)\r\nDEST[63:0] <- SRC1[63:0] - SRC1[127:64]\r\nDEST[127:64] <- SRC2[63:0] - SRC2[127:64]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVHSUBPD (VEX.256 encoded version)\r\nDEST[63:0] <- SRC1[63:0] - SRC1[127:64]\r\nDEST[127:64] <- SRC2[63:0] - SRC2[127:64]\r\nDEST[191:128] <- SRC1[191:128] - SRC1[255:192]\r\nDEST[255:192] <- SRC2[191:128] - SRC2[255:192]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nHSUBPD: __m128d _mm_hsub_pd(__m128d a, __m128d b)\r\n\r\nVHSUBPD: __m256d _mm256_hsub_pd (__m256d a, __m256d b);\r\n\r\nExceptions\r\nWhen the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-\r\nprotection exception (#GP) will be generated.\r\n\r\nNumeric Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\n\r\n\r\nOther Exceptions\r\nSee Exceptions Type 2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "HSUBPD"
},
{
"description": "HSUBPS-Packed Single-FP Horizontal Subtract\r\n Opcode/ Op/ 64/32-bit CPUID Description\r\n Instruction En Mode Feature\r\n Flag\r\n F2 0F 7D /r RM V/V SSE3 Horizontal subtract packed single-precision\r\n HSUBPS xmm1, xmm2/m128 floating-point values from xmm2/m128 to\r\n xmm1.\r\n VEX.NDS.128.F2.0F.WIG 7D /r RVM V/V AVX Horizontal subtract packed single-precision\r\n VHSUBPS xmm1, xmm2, xmm3/m128 floating-point values from xmm2 and\r\n xmm3/mem.\r\n VEX.NDS.256.F2.0F.WIG 7D /r RVM V/V AVX Horizontal subtract packed single-precision\r\n VHSUBPS ymm1, ymm2, ymm3/m256 floating-point values from ymm2 and\r\n ymm3/mem.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nSubtracts the single-precision floating-point value in the second dword of the destination operand from the first\r\ndword of the destination operand and stores the result in the first dword of the destination operand.\r\nSubtracts the single-precision floating-point value in the fourth dword of the destination operand from the third\r\ndword of the destination operand and stores the result in the second dword of the destination operand.\r\nSubtracts the single-precision floating-point value in the second dword of the source operand from the first dword\r\nof the source operand and stores the result in the third dword of the destination operand.\r\nSubtracts the single-precision floating-point value in the fourth dword of the source operand from the third dword\r\nof the source operand and stores the result in the fourth dword of the destination operand.\r\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).\r\nSee Figure 3-22 for HSUBPS; see Figure 3-23 for VHSUBPS.\r\n\r\n\r\n\r\n\r\n\r\n HSUBPS xmm1, xmm2/m128\r\n\r\n xmm2/\r\n [127:96] [95:64] [63:32] [31:0]\r\n m128\r\n\r\n\r\n\r\n\r\n [127:96] [95:64] [63:32] [31:0] xmm1\r\n\r\n\r\n\r\n\r\n xmm2/m128 xmm2/m128\r\n xmm1[95:64] - xmm1[31:0] - RESULT:\r\n [95:64] - xmm2/ [31:0] - xmm2/\r\n xmm1[127:96] xmm1[63:32] xmm1\r\n m128[127:96] m128[63:32]\r\n\r\n\r\n [127:96] [95:64] [63:32] [31:0]\r\n\r\n\r\n OM15996\r\n\r\n\r\n\r\n Figure 3-22. HSUBPS-Packed Single-FP Horizontal Subtract\r\n\r\n\r\n\r\n\r\n SRC1 X7 X6 X5 X4 X3 X2 X1 X0\r\n\r\n\r\n\r\n SRC2 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0\r\n\r\n\r\n\r\n DEST Y6-Y7 Y4-Y5 X6-X7 X4-X5 Y2-Y3 Y0-Y1 X2-X3 X0-X1\r\n\r\n\r\n\r\n\r\n Figure 3-23. VHSUBPS operation\r\n\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding\r\nYMM register destination are unmodified.\r\nVEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination\r\noperand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are\r\nzeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nHSUBPS (128-bit Legacy SSE version)\r\nDEST[31:0] <- SRC1[31:0] - SRC1[63:32]\r\nDEST[63:32] <- SRC1[95:64] - SRC1[127:96]\r\nDEST[95:64] <- SRC2[31:0] - SRC2[63:32]\r\nDEST[127:96] <- SRC2[95:64] - SRC2[127:96]\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVHSUBPS (VEX.128 encoded version)\r\nDEST[31:0] <- SRC1[31:0] - SRC1[63:32]\r\nDEST[63:32] <- SRC1[95:64] - SRC1[127:96]\r\nDEST[95:64] <- SRC2[31:0] - SRC2[63:32]\r\nDEST[127:96] <- SRC2[95:64] - SRC2[127:96]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVHSUBPS (VEX.256 encoded version)\r\nDEST[31:0] <- SRC1[31:0] - SRC1[63:32]\r\nDEST[63:32] <- SRC1[95:64] - SRC1[127:96]\r\nDEST[95:64] <- SRC2[31:0] - SRC2[63:32]\r\nDEST[127:96] <- SRC2[95:64] - SRC2[127:96]\r\nDEST[159:128] <- SRC1[159:128] - SRC1[191:160]\r\nDEST[191:160] <- SRC1[223:192] - SRC1[255:224]\r\nDEST[223:192] <- SRC2[159:128] - SRC2[191:160]\r\nDEST[255:224] <- SRC2[223:192] - SRC2[255:224]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nHSUBPS: __m128 _mm_hsub_ps(__m128 a, __m128 b);\r\n\r\nVHSUBPS: __m256 _mm256_hsub_ps (__m256 a, __m256 b);\r\n\r\nExceptions\r\nWhen the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-\r\nprotection exception (#GP) will be generated.\r\n\r\nNumeric Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nSee Exceptions Type 2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "HSUBPS"
},
{
"description": "IDIV-Signed Divide\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n F6 /7 IDIV r/m8 M Valid Valid Signed divide AX by r/m8, with result stored in:\r\n AL <- Quotient, AH <- Remainder.\r\n REX + F6 /7 IDIV r/m8* M Valid N.E. Signed divide AX by r/m8, with result stored in\r\n AL <- Quotient, AH <- Remainder.\r\n F7 /7 IDIV r/m16 M Valid Valid Signed divide DX:AX by r/m16, with result\r\n stored in AX <- Quotient, DX <- Remainder.\r\n F7 /7 IDIV r/m32 M Valid Valid Signed divide EDX:EAX by r/m32, with result\r\n stored in EAX <- Quotient, EDX <- Remainder.\r\n REX.W + F7 /7 IDIV r/m64 M Valid N.E. Signed divide RDX:RAX by r/m64, with result\r\n stored in RAX <- Quotient, RDX <- Remainder.\r\n NOTES:\r\n * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (r) NA NA NA\r\n\r\nDescription\r\nDivides the (signed) value in the AX, DX:AX, or EDX:EAX (dividend) by the source operand (divisor) and stores the\r\nresult in the AX (AH:AL), DX:AX, or EDX:EAX registers. The source operand can be a general-purpose register or a\r\nmemory location. The action of this instruction depends on the operand size (dividend/divisor).\r\nNon-integral results are truncated (chopped) towards 0. The remainder is always less than the divisor in magni-\r\ntude. Overflow is indicated with the #DE (divide error) exception rather than with the CF flag.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-\r\ntional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. In 64-bit mode when REX.W is\r\napplied, the instruction divides the signed value in RDX:RAX by the source operand. RAX contains a 64-bit\r\nquotient; RDX contains a 64-bit remainder.\r\nSee the summary chart at the beginning of this section for encoding data and limits. See Table 3-50.\r\n Table 3-50. IDIV Results\r\n Operand Size Dividend Divisor Quotient Remainder Quotient Range\r\n Word/byte AX r/m8 AL AH -128 to +127\r\n Doubleword/word DX:AX r/m16 AX DX -32,768 to +32,767\r\n Quadword/doubleword EDX:EAX r/m32 EAX EDX -231 to 231 - 1\r\n Doublequadword/ quadword RDX:RAX r/m64 RAX RDX -263 to 263 - 1\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIF SRC = 0\r\n THEN #DE; (* Divide error *)\r\nFI;\r\n\r\nIF OperandSize = 8 (* Word/byte operation *)\r\n THEN\r\n temp <- AX / SRC; (* Signed division *)\r\n IF (temp > 7FH) or (temp < 80H)\r\n (* If a positive result is greater than 7FH or a negative result is less than 80H *)\r\n THEN #DE; (* Divide error *)\r\n ELSE\r\n AL <- temp;\r\n AH <- AX SignedModulus SRC;\r\n FI;\r\n ELSE IF OperandSize = 16 (* Doubleword/word operation *)\r\n THEN\r\n temp <- DX:AX / SRC; (* Signed division *)\r\n IF (temp > 7FFFH) or (temp < 8000H)\r\n (* If a positive result is greater than 7FFFH\r\n or a negative result is less than 8000H *)\r\n THEN\r\n #DE; (* Divide error *)\r\n ELSE\r\n AX <- temp;\r\n DX <- DX:AX SignedModulus SRC;\r\n FI;\r\n FI;\r\n ELSE IF OperandSize = 32 (* Quadword/doubleword operation *)\r\n temp <- EDX:EAX / SRC; (* Signed division *)\r\n IF (temp > 7FFFFFFFH) or (temp < 80000000H)\r\n (* If a positive result is greater than 7FFFFFFFH\r\n or a negative result is less than 80000000H *)\r\n THEN\r\n #DE; (* Divide error *)\r\n ELSE\r\n EAX <- temp;\r\n EDX <- EDXE:AX SignedModulus SRC;\r\n FI;\r\n FI;\r\n ELSE IF OperandSize = 64 (* Doublequadword/quadword operation *)\r\n temp <- RDX:RAX / SRC; (* Signed division *)\r\n IF (temp > 7FFFFFFFFFFFFFFFH) or (temp < 8000000000000000H)\r\n (* If a positive result is greater than 7FFFFFFFFFFFFFFFH\r\n or a negative result is less than 8000000000000000H *)\r\n THEN\r\n #DE; (* Divide error *)\r\n ELSE\r\n RAX <- temp;\r\n RDX <- RDE:RAX SignedModulus SRC;\r\n FI;\r\n FI;\r\nFI;\r\n\r\n\r\n\r\n\r\nFlags Affected\r\nThe CF, OF, SF, ZF, AF, and PF flags are undefined.\r\n\r\nProtected Mode Exceptions\r\n#DE If the source operand (divisor) is 0.\r\n The signed result (quotient) is too large for the destination.\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#DE If the source operand (divisor) is 0.\r\n\r\n The signed result (quotient) is too large for the destination.\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#DE If the source operand (divisor) is 0.\r\n\r\n The signed result (quotient) is too large for the destination.\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#DE If the source operand (divisor) is 0\r\n If the quotient is too large for the designated register.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "IDIV"
},
{
"description": "IMUL-Signed Multiply\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n F6 /5 IMUL r/m8* M Valid Valid AX<- AL * r/m byte.\r\n F7 /5 IMUL r/m16 M Valid Valid DX:AX <- AX * r/m word.\r\n F7 /5 IMUL r/m32 M Valid Valid EDX:EAX <- EAX * r/m32.\r\n REX.W + F7 /5 IMUL r/m64 M Valid N.E. RDX:RAX <- RAX * r/m64.\r\n 0F AF /r IMUL r16, r/m16 RM Valid Valid word register <- word register * r/m16.\r\n 0F AF /r IMUL r32, r/m32 RM Valid Valid doubleword register <- doubleword register *\r\n r/m32.\r\n REX.W + 0F AF /r IMUL r64, r/m64 RM Valid N.E. Quadword register <- Quadword register *\r\n r/m64.\r\n 6B /r ib IMUL r16, r/m16, imm8 RMI Valid Valid word register <- r/m16 * sign-extended\r\n immediate byte.\r\n 6B /r ib IMUL r32, r/m32, imm8 RMI Valid Valid doubleword register <- r/m32 * sign-\r\n extended immediate byte.\r\n REX.W + 6B /r ib IMUL r64, r/m64, imm8 RMI Valid N.E. Quadword register <- r/m64 * sign-extended\r\n immediate byte.\r\n 69 /r iw IMUL r16, r/m16, imm16 RMI Valid Valid word register <- r/m16 * immediate word.\r\n 69 /r id IMUL r32, r/m32, imm32 RMI Valid Valid doubleword register <- r/m32 * immediate\r\n doubleword.\r\n REX.W + 69 /r id IMUL r64, r/m64, imm32 RMI Valid N.E. Quadword register <- r/m64 * immediate\r\n doubleword.\r\n NOTES:\r\n * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (r, w) NA NA NA\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RMI ModRM:reg (r, w) ModRM:r/m (r) imm8/16/32 NA\r\n\r\nDescription\r\nPerforms a signed multiplication of two operands. This instruction has three forms, depending on the number of\r\noperands.\r\n. One-operand form - This form is identical to that used by the MUL instruction. Here, the source operand (in\r\n a general-purpose register or memory location) is multiplied by the value in the AL, AX, EAX, or RAX register\r\n (depending on the operand size) and the product (twice the size of the input operand) is stored in the AX,\r\n DX:AX, EDX:EAX, or RDX:RAX registers, respectively.\r\n. Two-operand form - With this form the destination operand (the first operand) is multiplied by the source\r\n operand (second operand). The destination operand is a general-purpose register and the source operand is an\r\n immediate value, a general-purpose register, or a memory location. The intermediate product (twice the size of\r\n the input operand) is truncated and stored in the destination operand location.\r\n. Three-operand form - This form requires a destination operand (the first operand) and two source operands\r\n (the second and the third operands). Here, the first source operand (which can be a general-purpose register\r\n or a memory location) is multiplied by the second source operand (an immediate value). The intermediate\r\n product (twice the size of the first source operand) is truncated and stored in the destination operand (a\r\n general-purpose register).\r\n\r\n\r\n\r\nWhen an immediate value is used as an operand, it is sign-extended to the length of the destination operand\r\nformat.\r\nThe CF and OF flags are set when the signed integer value of the intermediate product differs from the sign\r\nextended operand-size-truncated product, otherwise the CF and OF flags are cleared.\r\nThe three forms of the IMUL instruction are similar in that the length of the product is calculated to twice the length\r\nof the operands. With the one-operand form, the product is stored exactly in the destination. With the two- and\r\nthree- operand forms, however, the result is truncated to the length of the destination before it is stored in the\r\ndestination register. Because of this truncation, the CF or OF flag should be tested to ensure that no significant bits\r\nare lost.\r\nThe two- and three-operand forms may also be used with unsigned operands because the lower half of the product\r\nis the same regardless if the operands are signed or unsigned. The CF and OF flags, however, cannot be used to\r\ndetermine if the upper half of the result is non-zero.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-\r\ntional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. Use of REX.W modifies the three\r\nforms of the instruction as follows.\r\n. One-operand form -The source operand (in a 64-bit general-purpose register or memory location) is\r\n multiplied by the value in the RAX register and the product is stored in the RDX:RAX registers.\r\n. Two-operand form - The source operand is promoted to 64 bits if it is a register or a memory location. The\r\n destination operand is promoted to 64 bits.\r\n. Three-operand form - The first source operand (either a register or a memory location) and destination\r\n operand are promoted to 64 bits. If the source operand is an immediate, it is sign extended to 64 bits.\r\n\r\nOperation\r\nIF (NumberOfOperands = 1)\r\n THEN IF (OperandSize = 8)\r\n THEN\r\n TMP_XP <- AL * SRC (* Signed multiplication; TMP_XP is a signed integer at twice the width of the SRC *);\r\n AX <- TMP_XP[15:0];\r\n IF SignExtend(TMP_XP[7:0]) = TMP_XP\r\n THEN CF <- 0; OF <- 0;\r\n ELSE CF <- 1; OF <- 1; FI;\r\n ELSE IF OperandSize = 16\r\n THEN\r\n TMP_XP <- AX * SRC (* Signed multiplication; TMP_XP is a signed integer at twice the width of the SRC *)\r\n DX:AX <- TMP_XP[31:0];\r\n IF SignExtend(TMP_XP[15:0]) = TMP_XP\r\n THEN CF <- 0; OF <- 0;\r\n ELSE CF <- 1; OF <- 1; FI;\r\n ELSE IF OperandSize = 32\r\n THEN\r\n TMP_XP <- EAX * SRC (* Signed multiplication; TMP_XP is a signed integer at twice the width of the SRC*)\r\n EDX:EAX <- TMP_XP[63:0];\r\n IF SignExtend(TMP_XP[31:0]) = TMP_XP\r\n THEN CF <- 0; OF <- 0;\r\n ELSE CF <- 1; OF <- 1; FI;\r\n ELSE (* OperandSize = 64 *)\r\n TMP_XP <- RAX * SRC (* Signed multiplication; TMP_XP is a signed integer at twice the width of the SRC *)\r\n EDX:EAX <- TMP_XP[127:0];\r\n IF SignExtend(TMP_XP[63:0]) = TMP_XP\r\n THEN CF <- 0; OF <- 0;\r\n ELSE CF <- 1; OF <- 1; FI;\r\n FI;\r\n\r\n\r\n\r\n\r\n FI;\r\n ELSE IF (NumberOfOperands = 2)\r\n THEN\r\n TMP_XP <- DEST * SRC (* Signed multiplication; TMP_XP is a signed integer at twice the width of the SRC *)\r\n DEST <- TruncateToOperandSize(TMP_XP);\r\n IF SignExtend(DEST) != TMP_XP\r\n THEN CF <- 1; OF <- 1;\r\n ELSE CF <- 0; OF <- 0; FI;\r\n ELSE (* NumberOfOperands = 3 *)\r\n TMP_XP <- SRC1 * SRC2 (* Signed multiplication; TMP_XP is a signed integer at twice the width of the SRC1 *)\r\n DEST <- TruncateToOperandSize(TMP_XP);\r\n IF SignExtend(DEST) != TMP_XP\r\n THEN CF <- 1; OF <- 1;\r\n ELSE CF <- 0; OF <- 0; FI;\r\n FI;\r\nFI;\r\n\r\nFlags Affected\r\nFor the one operand form of the instruction, the CF and OF flags are set when significant bits are carried into the\r\nupper half of the result and cleared when the result fits exactly in the lower half of the result. For the two- and\r\nthree-operand forms of the instruction, the CF and OF flags are set when the result must be truncated to fit in the\r\ndestination operand size and cleared when the result fits exactly in the destination operand size. The SF, ZF, AF, and\r\nPF flags are undefined.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL NULL\r\n segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "IMUL"
},
{
"description": "IN-Input from Port\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n E4 ib IN AL, imm8 I Valid Valid Input byte from imm8 I/O port address into\r\n AL.\r\n E5 ib IN AX, imm8 I Valid Valid Input word from imm8 I/O port address into\r\n AX.\r\n E5 ib IN EAX, imm8 I Valid Valid Input dword from imm8 I/O port address into\r\n EAX.\r\n EC IN AL,DX NP Valid Valid Input byte from I/O port in DX into AL.\r\n ED IN AX,DX NP Valid Valid Input word from I/O port in DX into AX.\r\n ED IN EAX,DX NP Valid Valid Input doubleword from I/O port in DX into\r\n EAX.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n I imm8 NA NA NA\r\n NP NA NA NA NA\r\n\r\nDescription\r\nCopies the value from the I/O port specified with the second operand (source operand) to the destination operand\r\n(first operand). The source operand can be a byte-immediate or the DX register; the destination operand can be\r\nregister AL, AX, or EAX, depending on the size of the port being accessed (8, 16, or 32 bits, respectively). Using the\r\nDX register as a source operand allows I/O port addresses from 0 to 65,535 to be accessed; using a byte imme-\r\ndiate allows I/O port addresses 0 to 255 to be accessed.\r\nWhen accessing an 8-bit I/O port, the opcode determines the port size; when accessing a 16- and 32-bit I/O port,\r\nthe operand-size attribute determines the port size. At the machine code level, I/O instructions are shorter when\r\naccessing 8-bit I/O ports. Here, the upper eight bits of the port address will be 0.\r\nThis instruction is only useful for accessing I/O ports located in the processor's I/O address space. See Chapter 18,\r\n\"Input/Output,\" in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for more infor-\r\nmation on accessing I/O ports in the I/O address space.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nIF ((PE = 1) and ((CPL > IOPL) or (VM = 1)))\r\n THEN (* Protected mode with CPL > IOPL or virtual-8086 mode *)\r\n IF (Any I/O Permission Bit for I/O port being accessed = 1)\r\n THEN (* I/O operation is not allowed *)\r\n #GP(0);\r\n ELSE ( * I/O operation is allowed *)\r\n DEST <- SRC; (* Read from selected I/O port *)\r\n FI;\r\n ELSE (Real Mode or Protected Mode with CPL <= IOPL *)\r\n DEST <- SRC; (* Read from selected I/O port *)\r\nFI;\r\n\r\nFlags Affected\r\nNone\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the\r\n corresponding I/O permission bits in TSS for the I/O port being accessed is 1.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If any of the I/O permission bits in the TSS for the I/O port being accessed is 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the\r\n corresponding I/O permission bits in TSS for the I/O port being accessed is 1.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "IN"
},
{
"description": "INC-Increment by 1\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n FE /0 INC r/m8 M Valid Valid Increment r/m byte by 1.\r\n REX + FE /0 INC r/m8* M Valid N.E. Increment r/m byte by 1.\r\n FF /0 INC r/m16 M Valid Valid Increment r/m word by 1.\r\n FF /0 INC r/m32 M Valid Valid Increment r/m doubleword by 1.\r\n REX.W + FF /0 INC r/m64 M Valid N.E. Increment r/m quadword by 1.\r\n **\r\n 40+ rw INC r16 O N.E. Valid Increment word register by 1.\r\n 40+ rd INC r32 O N.E. Valid Increment doubleword register by 1.\r\n NOTES:\r\n * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n ** 40H through 47H are REX prefixes in 64-bit mode.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (r, w) NA NA NA\r\n O opcode + rd (r, w) NA NA NA\r\n\r\nDescription\r\nAdds 1 to the destination operand, while preserving the state of the CF flag. The destination operand can be a\r\nregister or a memory location. This instruction allows a loop counter to be updated without disturbing the CF flag.\r\n(Use a ADD instruction with an immediate operand of 1 to perform an increment operation that does updates the\r\nCF flag.)\r\nThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.\r\nIn 64-bit mode, INC r16 and INC r32 are not encodable (because opcodes 40H through 47H are REX prefixes).\r\nOtherwise, the instruction's 64-bit mode default operation size is 32 bits. Use of the REX.R prefix permits access to\r\nadditional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits.\r\n\r\nOperation\r\nDEST <- DEST + 1;\r\n\r\nAFlags Affected\r\nThe CF flag is not affected. The OF, SF, ZF, AF, and PF flags are set according to the result.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination operand is located in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULLsegment\r\n selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n",
"mnem": "INC"
},
{
"description": "INS/INSB/INSW/INSD-Input from Port to String\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 6C INS m8, DX NP Valid Valid Input byte from I/O port specified in DX into\r\n memory location specified in ES:(E)DI or RDI.*\r\n 6D INS m16, DX NP Valid Valid Input word from I/O port specified in DX into\r\n memory location specified in ES:(E)DI or RDI.1\r\n 6D INS m32, DX NP Valid Valid Input doubleword from I/O port specified in DX\r\n into memory location specified in ES:(E)DI or\r\n RDI.1\r\n 6C INSB NP Valid Valid Input byte from I/O port specified in DX into\r\n memory location specified with ES:(E)DI or\r\n RDI.1\r\n 6D INSW NP Valid Valid Input word from I/O port specified in DX into\r\n memory location specified in ES:(E)DI or RDI.1\r\n 6D INSD NP Valid Valid Input doubleword from I/O port specified in DX\r\n into memory location specified in ES:(E)DI or\r\n RDI.1\r\n NOTES:\r\n * In 64-bit mode, only 64-bit (RDI) and 32-bit (EDI) address sizes are supported. In non-64-bit mode, only 32-bit (EDI) and 16-bit (DI)\r\n address sizes are supported.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nCopies the data from the I/O port specified with the source operand (second operand) to the destination operand\r\n(first operand). The source operand is an I/O port address (from 0 to 65,535) that is read from the DX register. The\r\ndestination operand is a memory location, the address of which is read from either the ES:DI, ES:EDI or the RDI\r\nregisters (depending on the address-size attribute of the instruction, 16, 32 or 64, respectively). (The ES segment\r\ncannot be overridden with a segment override prefix.) The size of the I/O port being accessed (that is, the size of\r\nthe source and destination operands) is determined by the opcode for an 8-bit I/O port or by the operand-size attri-\r\nbute of the instruction for a 16- or 32-bit I/O port.\r\nAt the assembly-code level, two forms of this instruction are allowed: the \"explicit-operands\" form and the \"no-\r\noperands\" form. The explicit-operands form (specified with the INS mnemonic) allows the source and destination\r\noperands to be specified explicitly. Here, the source operand must be \"DX,\" and the destination operand should be\r\na symbol that indicates the size of the I/O port and the destination address. This explicit-operands form is provided\r\nto allow documentation; however, note that the documentation provided by this form can be misleading. That is,\r\nthe destination operand symbol must specify the correct type (size) of the operand (byte, word, or doubleword),\r\nbut it does not have to specify the correct location. The location is always specified by the ES:(E)DI registers,\r\nwhich must be loaded correctly before the INS instruction is executed.\r\nThe no-operands form provides \"short forms\" of the byte, word, and doubleword versions of the INS instructions.\r\nHere also DX is assumed by the processor to be the source operand and ES:(E)DI is assumed to be the destination\r\noperand. The size of the I/O port is specified with the choice of mnemonic: INSB (byte), INSW (word), or INSD\r\n(doubleword).\r\nAfter the byte, word, or doubleword is transfer from the I/O port to the memory location, the DI/EDI/RDI register\r\nis incremented or decremented automatically according to the setting of the DF flag in the EFLAGS register. (If the\r\nDF flag is 0, the (E)DI register is incremented; if the DF flag is 1, the (E)DI register is decremented.) The (E)DI\r\nregister is incremented or decremented by 1 for byte operations, by 2 for word operations, or by 4 for doubleword\r\noperations.\r\n\r\n\r\n\r\nThe INS, INSB, INSW, and INSD instructions can be preceded by the REP prefix for block input of ECX bytes, words,\r\nor doublewords. See \"REP/REPE/REPZ /REPNE/REPNZ-Repeat String Operation Prefix\" in Chapter 4 of the Intel\r\n64 and IA-32 Architectures Software Developer's Manual, Volume 2B, for a description of the REP prefix.\r\nThese instructions are only useful for accessing I/O ports located in the processor's I/O address space. See Chapter\r\n18, \"Input/Output,\" in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for more\r\ninformation on accessing I/O ports in the I/O address space.\r\nIn 64-bit mode, default address size is 64 bits, 32 bit address size is supported using the prefix 67H. The address\r\nof the memory destination is specified by RDI or EDI. 16-bit address size is not supported in 64-bit mode. The\r\noperand size is not promoted.\r\nThese instructions may read from the I/O port without writing to the memory location if an exception or VM exit\r\noccurs due to the write (e.g. #PF). If this would be problematic, for example because the I/O port read has side-\r\neffects, software should ensure the write to the memory location does not cause an exception or VM exit.\r\n\r\nOperation\r\nIF ((PE = 1) and ((CPL > IOPL) or (VM = 1)))\r\n THEN (* Protected mode with CPL > IOPL or virtual-8086 mode *)\r\n IF (Any I/O Permission Bit for I/O port being accessed = 1)\r\n THEN (* I/O operation is not allowed *)\r\n #GP(0);\r\n ELSE (* I/O operation is allowed *)\r\n DEST <- SRC; (* Read from I/O port *)\r\n FI;\r\n ELSE (Real Mode or Protected Mode with CPL IOPL *)\r\n DEST <- SRC; (* Read from I/O port *)\r\nFI;\r\n\r\nNon-64-bit Mode:\r\n\r\nIF (Byte transfer)\r\n THEN IF DF = 0\r\n THEN (E)DI <- (E)DI + 1;\r\n ELSE (E)DI <- (E)DI - 1; FI;\r\n ELSE IF (Word transfer)\r\n THEN IF DF = 0\r\n THEN (E)DI <- (E)DI + 2;\r\n ELSE (E)DI <- (E)DI - 2; FI;\r\n ELSE (* Doubleword transfer *)\r\n THEN IF DF = 0\r\n THEN (E)DI <- (E)DI + 4;\r\n ELSE (E)DI <- (E)DI - 4; FI;\r\n FI;\r\nFI;\r\n\r\nFI64-bit Mode:\r\n\r\nIF (Byte transfer)\r\n THEN IF DF = 0\r\n THEN (E|R)DI <- (E|R)DI + 1;\r\n ELSE (E|R)DI <- (E|R)DI - 1; FI;\r\n ELSE IF (Word transfer)\r\n THEN IF DF = 0\r\n THEN (E)DI <- (E)DI + 2;\r\n ELSE (E)DI <- (E)DI - 2; FI;\r\n ELSE (* Doubleword transfer *)\r\n\r\n\r\n\r\n\r\n THEN IF DF = 0\r\n THEN (E|R)DI <- (E|R)DI + 4;\r\n ELSE (E|R)DI <- (E|R)DI - 4; FI;\r\n FI;\r\nFI;\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the\r\n corresponding I/O permission bits in TSS for the I/O port being accessed is 1.\r\n If the destination is located in a non-writable segment.\r\n If an illegal memory operand effective address in the ES segments is given.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If any of the I/O permission bits in the TSS for the I/O port being accessed is 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the\r\n corresponding I/O permission bits in TSS for the I/O port being accessed is 1.\r\n If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "INS"
},
{
"description": "-R:INS",
"mnem": "INSB"
},
{
"description": "-R:INS",
"mnem": "INSD"
},
{
"description": "INSERTPS-Insert Scalar Single-Precision Floating-Point Value\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0F 3A 21 /r ib RMI V/V SSE4_1 Insert a single-precision floating-point value selected\r\n INSERTPS xmm1, xmm2/m32, imm8 by imm8 from xmm2/m32 into xmm1 at the specified\r\n destination element specified by imm8 and zero out\r\n destination elements in xmm1 as indicated in imm8.\r\n VEX.NDS.128.66.0F3A.WIG 21 /r ib RVMI V/V AVX Insert a single-precision floating-point value selected\r\n VINSERTPS xmm1, xmm2, by imm8 from xmm3/m32 and merge with values in\r\n xmm3/m32, imm8 xmm2 at the specified destination element specified\r\n by imm8 and write out the result and zero out\r\n destination elements in xmm1 as indicated in imm8.\r\n EVEX.NDS.128.66.0F3A.W0 21 /r ib T1S V/V AVX512F Insert a single-precision floating-point value selected\r\n VINSERTPS xmm1, xmm2, by imm8 from xmm3/m32 and merge with values in\r\n xmm3/m32, imm8 xmm2 at the specified destination element specified\r\n by imm8 and write out the result and zero out\r\n destination elements in xmm1 as indicated in imm8.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (r, w) ModRM:r/m (r) Imm8 NA\r\n RVMI ModRM:reg (w) VEX.vvvv ModRM:r/m (r) Imm8\r\n T1S ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) Imm8\r\n\r\nDescription\r\n(register source form)\r\nSelect a single-precision floating-point element from second source as indicated by Count_S bits of the immediate\r\noperand and destination operand it into the first source at the location indicated by the Count_D bits of the imme-\r\ndiate operand. Store in the destination and zero out destination elements based on the ZMask bits of the immediate\r\noperand.\r\n(memory source form)\r\nLoad a floating-point element from a 32-bit memory location and destination operand it into the first source at the\r\nlocation indicated by the Count_D bits of the immediate operand. Store in the destination and zero out destination\r\nelements based on the ZMask bits of the immediate operand.\r\n128-bit Legacy SSE version: The first source register is an XMM register. The second source operand is either an\r\nXMM register or a 32-bit memory location. The destination is not distinct from the first source XMM register and the\r\nupper bits (MAX_VL-1:128) of the corresponding register destination are unmodified.\r\nVEX.128 and EVEX encoded version: The destination and first source register is an XMM register. The second\r\nsource operand is either an XMM register or a 32-bit memory location. The upper bits (MAX_VL-1:128) of the corre-\r\nsponding register destination are zeroed.\r\nIf VINSERTPS is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause\r\nan #UD exception.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVINSERTPS (VEX.128 and EVEX encoded version)\r\nIF (SRC = REG) THEN COUNT_S <- imm8[7:6]\r\n ELSE COUNT_S <- 0\r\nCOUNT_D <- imm8[5:4]\r\nZMASK <- imm8[3:0]\r\nCASE (COUNT_S) OF\r\n 0: TMP <- SRC2[31:0]\r\n 1: TMP <- SRC2[63:32]\r\n 2: TMP <- SRC2[95:64]\r\n 3: TMP <- SRC2[127:96]\r\nESAC;\r\nCASE (COUNT_D) OF\r\n 0: TMP2[31:0] <- TMP\r\n TMP2[127:32] <- SRC1[127:32]\r\n 1: TMP2[63:32] <- TMP\r\n TMP2[31:0] <- SRC1[31:0]\r\n TMP2[127:64] <- SRC1[127:64]\r\n 2: TMP2[95:64] <- TMP\r\n TMP2[63:0] <- SRC1[63:0]\r\n TMP2[127:96] <- SRC1[127:96]\r\n 3: TMP2[127:96] <- TMP\r\n TMP2[95:0] <- SRC1[95:0]\r\nESAC;\r\n\r\nIF (ZMASK[0] = 1) THEN DEST[31:0] <- 00000000H\r\n ELSE DEST[31:0] <- TMP2[31:0]\r\nIF (ZMASK[1] = 1) THEN DEST[63:32] <- 00000000H\r\n ELSE DEST[63:32] <- TMP2[63:32]\r\nIF (ZMASK[2] = 1) THEN DEST[95:64] <- 00000000H\r\n ELSE DEST[95:64] <- TMP2[95:64]\r\nIF (ZMASK[3] = 1) THEN DEST[127:96] <- 00000000H\r\n ELSE DEST[127:96] <- TMP2[127:96]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nINSERTPS (128-bit Legacy SSE version)\r\nIF (SRC = REG) THEN COUNT_S <-imm8[7:6]\r\n ELSE COUNT_S <-0\r\nCOUNT_D <-imm8[5:4]\r\nZMASK <-imm8[3:0]\r\nCASE (COUNT_S) OF\r\n 0: TMP <-SRC[31:0]\r\n 1: TMP <-SRC[63:32]\r\n 2: TMP <-SRC[95:64]\r\n 3: TMP <-SRC[127:96]\r\nESAC;\r\n\r\nCASE (COUNT_D) OF\r\n 0: TMP2[31:0] <-TMP\r\n TMP2[127:32] <-DEST[127:32]\r\n 1: TMP2[63:32] <-TMP\r\n TMP2[31:0] <-DEST[31:0]\r\n TMP2[127:64] <-DEST[127:64]\r\n 2: TMP2[95:64] <-TMP\r\n\r\n\r\n\r\n TMP2[63:0] <-DEST[63:0]\r\n TMP2[127:96] <-DEST[127:96]\r\n 3: TMP2[127:96] <-TMP\r\n TMP2[95:0] <-DEST[95:0]\r\nESAC;\r\n\r\nIF (ZMASK[0] = 1) THEN DEST[31:0] <-00000000H\r\n ELSE DEST[31:0] <-TMP2[31:0]\r\nIF (ZMASK[1] = 1) THEN DEST[63:32] <-00000000H\r\n ELSE DEST[63:32] <-TMP2[63:32]\r\nIF (ZMASK[2] = 1) THEN DEST[95:64] <-00000000H\r\n ELSE DEST[95:64] <-TMP2[95:64]\r\nIF (ZMASK[3] = 1) THEN DEST[127:96] <-00000000H\r\n ELSE DEST[127:96] <-TMP2[127:96]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVINSERTPS __m128 _mm_insert_ps(__m128 dst, __m128 src, const int nidx);\r\nINSETRTPS __m128 _mm_insert_ps(__m128 dst, __m128 src, const int nidx);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 5; additionally\r\n#UD If VEX.L = 0.\r\nEVEX-encoded instruction, see Exceptions Type E9NF.\r\n\r\n\r\n\r\n\r\n",
"mnem": "INSERTPS"
},
{
"description": "-R:INS",
"mnem": "INSW"
},
{
"description": "-R:INT n",
"mnem": "INT 3"
},
{
"description": "INT n/INTO/INT 3-Call to Interrupt Procedure\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n CC INT 3 NP Valid Valid Interrupt 3-trap to debugger.\r\n CD ib INT imm8 I Valid Valid Interrupt vector specified by immediate byte.\r\n CE INTO NP Invalid Valid Interrupt 4-if overflow flag is 1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n I imm8 NA NA NA\r\n\r\nDescription\r\nThe INT n instruction generates a call to the interrupt or exception handler specified with the destination operand\r\n(see the section titled \"Interrupts and Exceptions\" in Chapter 6 of the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 1). The destination operand specifies a vector from 0 to 255, encoded as an 8-bit\r\nunsigned intermediate value. Each vector provides an index to a gate descriptor in the IDT. The first 32 vectors are\r\nreserved by Intel for system use. Some of these vectors are used for internally generated exceptions.\r\nThe INT n instruction is the general mnemonic for executing a software-generated call to an interrupt handler. The\r\nINTO instruction is a special mnemonic for calling overflow exception (#OF), exception 4. The overflow interrupt\r\nchecks the OF flag in the EFLAGS register and calls the overflow interrupt handler if the OF flag is set to 1. (The\r\nINTO instruction cannot be used in 64-bit mode.)\r\nThe INT 3 instruction generates a special one byte opcode (CC) that is intended for calling the debug exception\r\nhandler. (This one byte form is valuable because it can be used to replace the first byte of any instruction with a\r\nbreakpoint, including other one byte instructions, without over-writing other code). To further support its function\r\nas a debug breakpoint, the interrupt generated with the CC opcode also differs from the regular software interrupts\r\nas follows:\r\n. Interrupt redirection does not happen when in VME mode; the interrupt is handled by a protected-mode\r\n handler.\r\n. The virtual-8086 mode IOPL checks do not occur. The interrupt is taken without faulting at any IOPL level.\r\nNote that the \"normal\" 2-byte opcode for INT 3 (CD03) does not have these special features. Intel and Microsoft\r\nassemblers will not generate the CD03 opcode from any mnemonic, but this opcode can be created by direct\r\nnumeric code definition or by self-modifying code.\r\nThe action of the INT n instruction (including the INTO and INT 3 instructions) is similar to that of a far call made\r\nwith the CALL instruction. The primary difference is that with the INT n instruction, the EFLAGS register is pushed\r\nonto the stack before the return address. (The return address is a far address consisting of the current values of\r\nthe CS and EIP registers.) Returns from interrupt procedures are handled with the IRET instruction, which pops the\r\nEFLAGS information and return address from the stack.\r\nThe vector specifies an interrupt descriptor in the interrupt descriptor table (IDT); that is, it provides index into the\r\nIDT. The selected interrupt descriptor in turn contains a pointer to an interrupt or exception handler procedure.\r\nIn protected mode, the IDT contains an array of 8-byte descriptors, each of which is an interrupt gate, trap gate,\r\nor task gate. In real-address mode, the IDT is an array of 4-byte far pointers (2-byte code segment selector and\r\na 2-byte instruction pointer), each of which point directly to a procedure in the selected segment. (Note that in\r\nreal-address mode, the IDT is called the interrupt vector table, and its pointers are called interrupt vectors.)\r\nThe following decision table indicates which action in the lower portion of the table is taken given the conditions in\r\nthe upper portion of the table. Each Y in the lower section of the decision table represents a procedure defined in\r\nthe \"Operation\" section for this instruction (except #GP).\r\n\r\n\r\n\r\n\r\n\r\n Table 3-51. Decision Table\r\nPE 0 1 1 1 1 1 1 1\r\nVM - - - - - 0 1 1\r\nIOPL - - - - - - <3 =3\r\nDPL/CPL - DPL< - DPL> DPL= DPL< - -\r\nRELATIONSHIP CPL CPL CPL or C CPL & NC\r\nINTERRUPT TYPE - S/W - - - - - -\r\nGATE TYPE - - Task Trap or Trap or Trap or Trap or Trap or\r\n Interrupt Interrupt Interrupt Interrupt Interrupt\r\nREAL-ADDRESS-MODE Y\r\nPROTECTED-MODE Y Y Y Y Y Y Y\r\nTRAP-OR-INTERRUPT- Y Y Y Y Y\r\nGATE\r\nINTER-PRIVILEGE-LEVEL- Y\r\nINTERRUPT\r\nINTRA-PRIVILEGE-LEVEL- Y\r\nINTERRUPT\r\nINTERRUPT-FROM- Y\r\nVIRTUAL-8086-MODE\r\nTASK-GATE Y\r\n#GP Y Y Y\r\nNOTES:\r\n - Don't Care.\r\n Y Yes, action taken.\r\nBlank Action not taken.\r\n\r\nWhen the processor is executing in virtual-8086 mode, the IOPL determines the action of the INT n instruction. If\r\nthe IOPL is less than 3, the processor generates a #GP(selector) exception; if the IOPL is 3, the processor executes\r\na protected mode interrupt to privilege level 0. The interrupt gate's DPL must be set to 3 and the target CPL of the\r\ninterrupt handler procedure must be 0 to execute the protected mode interrupt to privilege level 0.\r\nThe interrupt descriptor table register (IDTR) specifies the base linear address and limit of the IDT. The initial base\r\naddress value of the IDTR after the processor is powered up or reset is 0.\r\n\r\nOperation\r\nThe following operational description applies not only to the INT n and INTO instructions, but also to external inter-\r\nrupts, nonmaskable interrupts (NMIs), and exceptions. Some of these events push onto the stack an error code.\r\nThe operational description specifies numerous checks whose failure may result in delivery of a nested exception.\r\nIn these cases, the original event is not delivered.\r\nThe operational description specifies the error code delivered by any nested exception. In some cases, the error\r\ncode is specified with a pseudofunction error_code(num,idt,ext), where idt and ext are bit values. The pseudofunc-\r\ntion produces an error code as follows: (1) if idt is 0, the error code is (num & FCH) | ext; (2) if idt is 1, the error\r\ncode is (num << 3) | 2 | ext.\r\nIn many cases, the pseudofunction error_code is invoked with a pseudovariable EXT. The value of EXT depends on\r\nthe nature of the event whose delivery encountered a nested exception: if that event is a software interrupt, EXT is\r\n0; otherwise, EXT is 1.\r\n\r\n\r\n\r\n\r\n\r\nIF PE = 0\r\n THEN\r\n GOTO REAL-ADDRESS-MODE;\r\n ELSE (* PE = 1 *)\r\n IF (VM = 1 and IOPL < 3 AND INT n)\r\n THEN\r\n #GP(0); (* Bit 0 of error code is 0 because INT n *)\r\n ELSE (* Protected mode, IA-32e mode, or virtual-8086 mode interrupt *)\r\n IF (IA32_EFER.LMA = 0)\r\n THEN (* Protected mode, or virtual-8086 mode interrupt *)\r\n GOTO PROTECTED-MODE;\r\n ELSE (* IA-32e mode interrupt *)\r\n GOTO IA-32e-MODE;\r\n FI;\r\n FI;\r\nFI;\r\nREAL-ADDRESS-MODE:\r\n IF ((vector_number << 2) + 3) is not within IDT limit\r\n THEN #GP; FI;\r\n IF stack not large enough for a 6-byte return information\r\n THEN #SS; FI;\r\n Push (EFLAGS[15:0]);\r\n IF <- 0; (* Clear interrupt flag *)\r\n TF <- 0; (* Clear trap flag *)\r\n AC <- 0; (* Clear AC flag *)\r\n Push(CS);\r\n Push(IP);\r\n (* No error codes are pushed in real-address mode*)\r\n CS <- IDT(Descriptor (vector_number << 2), selector));\r\n EIP <- IDT(Descriptor (vector_number << 2), offset)); (* 16 bit offset AND 0000FFFFH *)\r\nEND;\r\nPROTECTED-MODE:\r\n IF ((vector_number << 3) + 7) is not within IDT limits\r\n or selected IDT descriptor is not an interrupt-, trap-, or task-gate type\r\n THEN #GP(error_code(vector_number,1,EXT)); FI;\r\n (* idt operand to error_code set because vector is used *)\r\n IF software interrupt (* Generated by INT n, INT3, or INTO *)\r\n THEN\r\n IF gate DPL < CPL (* PE = 1, DPL < CPL, software interrupt *)\r\n THEN #GP(error_code(vector_number,1,0)); FI;\r\n (* idt operand to error_code set because vector is used *)\r\n (* ext operand to error_code is 0 because INT n, INT3, or INTO*)\r\n FI;\r\n IF gate not present\r\n THEN #NP(error_code(vector_number,1,EXT)); FI;\r\n (* idt operand to error_code set because vector is used *)\r\n IF task gate (* Specified in the selected interrupt table descriptor *)\r\n THEN GOTO TASK-GATE;\r\n ELSE GOTO TRAP-OR-INTERRUPT-GATE; (* PE = 1, trap/interrupt gate *)\r\n FI;\r\nEND;\r\nIA-32e-MODE:\r\n IF INTO and CS.L = 1 (64-bit mode)\r\n THEN #UD;\r\n\r\n\r\n\r\n FI;\r\n IF ((vector_number << 4) + 15) is not in IDT limits\r\n or selected IDT descriptor is not an interrupt-, or trap-gate type\r\n THEN #GP(error_code(vector_number,1,EXT));\r\n (* idt operand to error_code set because vector is used *)\r\n FI;\r\n IF software interrupt (* Generated by INT n, INT 3, or INTO *)\r\n THEN\r\n IF gate DPL < CPL (* PE = 1, DPL < CPL, software interrupt *)\r\n THEN #GP(error_code(vector_number,1,0));\r\n (* idt operand to error_code set because vector is used *)\r\n (* ext operand to error_code is 0 because INT n, INT3, or INTO*)\r\n FI;\r\n FI;\r\n IF gate not present\r\n THEN #NP(error_code(vector_number,1,EXT));\r\n (* idt operand to error_code set because vector is used *)\r\n FI;\r\n GOTO TRAP-OR-INTERRUPT-GATE; (* Trap/interrupt gate *)\r\nEND;\r\nTASK-GATE: (* PE = 1, task gate *)\r\n Read TSS selector in task gate (IDT descriptor);\r\n IF local/global bit is set to local or index not within GDT limits\r\n THEN #GP(error_code(TSS selector,0,EXT)); FI;\r\n (* idt operand to error_code is 0 because selector is used *)\r\n Access TSS descriptor in GDT;\r\n IF TSS descriptor specifies that the TSS is busy (low-order 5 bits set to 00001)\r\n THEN #GP(TSS selector,0,EXT)); FI;\r\n (* idt operand to error_code is 0 because selector is used *)\r\n IF TSS not present\r\n THEN #NP(TSS selector,0,EXT)); FI;\r\n (* idt operand to error_code is 0 because selector is used *)\r\n SWITCH-TASKS (with nesting) to TSS;\r\n IF interrupt caused by fault with error code\r\n THEN\r\n IF stack limit does not allow push of error code\r\n THEN #SS(EXT); FI;\r\n Push(error code);\r\n FI;\r\n IF EIP not within code segment limit\r\n THEN #GP(EXT); FI;\r\nEND;\r\nTRAP-OR-INTERRUPT-GATE:\r\n Read new code-segment selector for trap or interrupt gate (IDT descriptor);\r\n IF new code-segment selector is NULL\r\n THEN #GP(EXT); FI; (* Error code contains NULL selector *)\r\n IF new code-segment selector is not within its descriptor table limits\r\n THEN #GP(error_code(new code-segment selector,0,EXT)); FI;\r\n (* idt operand to error_code is 0 because selector is used *)\r\n Read descriptor referenced by new code-segment selector;\r\n IF descriptor does not indicate a code segment or new code-segment DPL > CPL\r\n THEN #GP(error_code(new code-segment selector,0,EXT)); FI;\r\n (* idt operand to error_code is 0 because selector is used *)\r\n IF new code-segment descriptor is not present,\r\n\r\n\r\n\r\n THEN #NP(error_code(new code-segment selector,0,EXT)); FI;\r\n (* idt operand to error_code is 0 because selector is used *)\r\n IF new code segment is non-conforming with DPL < CPL\r\n THEN\r\n IF VM = 0\r\n THEN\r\n GOTO INTER-PRIVILEGE-LEVEL-INTERRUPT;\r\n (* PE = 1, VM = 0, interrupt or trap gate, nonconforming code segment,\r\n DPL < CPL *)\r\n ELSE (* VM = 1 *)\r\n IF new code-segment DPL != 0\r\n THEN #GP(error_code(new code-segment selector,0,EXT));\r\n (* idt operand to error_code is 0 because selector is used *)\r\n GOTO INTERRUPT-FROM-VIRTUAL-8086-MODE; FI;\r\n (* PE = 1, interrupt or trap gate, DPL < CPL, VM = 1 *)\r\n FI;\r\n ELSE (* PE = 1, interrupt or trap gate, DPL >= CPL *)\r\n IF VM = 1\r\n THEN #GP(error_code(new code-segment selector,0,EXT));\r\n (* idt operand to error_code is 0 because selector is used *)\r\n IF new code segment is conforming or new code-segment DPL = CPL\r\n THEN\r\n GOTO INTRA-PRIVILEGE-LEVEL-INTERRUPT;\r\n ELSE (* PE = 1, interrupt or trap gate, nonconforming code segment, DPL > CPL *)\r\n #GP(error_code(new code-segment selector,0,EXT));\r\n (* idt operand to error_code is 0 because selector is used *)\r\n FI;\r\n FI;\r\nEND;\r\nINTER-PRIVILEGE-LEVEL-INTERRUPT:\r\n (* PE = 1, interrupt or trap gate, non-conforming code segment, DPL < CPL *)\r\n IF (IA32_EFER.LMA = 0) (* Not IA-32e mode *)\r\n THEN\r\n (* Identify stack-segment selector for new privilege level in current TSS *)\r\n IF current TSS is 32-bit\r\n THEN\r\n TSSstackAddress <- (new code-segment DPL << 3) + 4;\r\n IF (TSSstackAddress + 5) > current TSS limit\r\n THEN #TS(error_code(current TSS selector,0,EXT)); FI;\r\n (* idt operand to error_code is 0 because selector is used *)\r\n NewSS <- 2 bytes loaded from (TSS base + TSSstackAddress + 4);\r\n NewESP <- 4 bytes loaded from (TSS base + TSSstackAddress);\r\n ELSE (* current TSS is 16-bit *)\r\n TSSstackAddress <- (new code-segment DPL << 2) + 2\r\n IF (TSSstackAddress + 3) > current TSS limit\r\n THEN #TS(error_code(current TSS selector,0,EXT)); FI;\r\n (* idt operand to error_code is 0 because selector is used *)\r\n NewSS <- 2 bytes loaded from (TSS base + TSSstackAddress + 2);\r\n NewESP <- 2 bytes loaded from (TSS base + TSSstackAddress);\r\n FI;\r\n IF NewSS is NULL\r\n THEN #TS(EXT); FI;\r\n IF NewSS index is not within its descriptor-table limits\r\n or NewSS RPL != new code-segment DPL\r\n\r\n\r\n\r\n THEN #TS(error_code(NewSS,0,EXT)); FI;\r\n (* idt operand to error_code is 0 because selector is used *)\r\n Read new stack-segment descriptor for NewSS in GDT or LDT;\r\n IF new stack-segment DPL != new code-segment DPL\r\n or new stack-segment Type does not indicate writable data segment\r\n THEN #TS(error_code(NewSS,0,EXT)); FI;\r\n (* idt operand to error_code is 0 because selector is used *)\r\n IF NewSS is not present\r\n THEN #SS(error_code(NewSS,0,EXT)); FI;\r\n (* idt operand to error_code is 0 because selector is used *)\r\n ELSE (* IA-32e mode *)\r\n IF IDT-gate IST = 0\r\n THEN TSSstackAddress <- (new code-segment DPL << 3) + 4;\r\n ELSE TSSstackAddress <- (IDT gate IST << 3) + 28;\r\n FI;\r\n IF (TSSstackAddress + 7) > current TSS limit\r\n THEN #TS(error_code(current TSS selector,0,EXT); FI;\r\n (* idt operand to error_code is 0 because selector is used *)\r\n NewRSP <- 8 bytes loaded from (current TSS base + TSSstackAddress);\r\n NewSS <- new code-segment DPL; (* NULL selector with RPL = new CPL *)\r\n FI;\r\n IF IDT gate is 32-bit\r\n THEN\r\n IF new stack does not have room for 24 bytes (error code pushed)\r\n or 20 bytes (no error code pushed)\r\n THEN #SS(error_code(NewSS,0,EXT)); FI;\r\n (* idt operand to error_code is 0 because selector is used *)\r\n FI\r\n ELSE\r\n IF IDT gate is 16-bit\r\n THEN\r\n IF new stack does not have room for 12 bytes (error code pushed)\r\n or 10 bytes (no error code pushed);\r\n THEN #SS(error_code(NewSS,0,EXT)); FI;\r\n (* idt operand to error_code is 0 because selector is used *)\r\n ELSE (* 64-bit IDT gate*)\r\n IF StackAddress is non-canonical\r\n THEN #SS(EXT); FI; (* Error code contains NULL selector *)\r\n FI;\r\n FI;\r\n IF (IA32_EFER.LMA = 0) (* Not IA-32e mode *)\r\n THEN\r\n IF instruction pointer from IDT gate is not within new code-segment limits\r\n THEN #GP(EXT); FI; (* Error code contains NULL selector *)\r\n ESP <- NewESP;\r\n SS <- NewSS; (* Segment descriptor information also loaded *)\r\n ELSE (* IA-32e mode *)\r\n IF instruction pointer from IDT gate contains a non-canonical address\r\n THEN #GP(EXT); FI; (* Error code contains NULL selector *)\r\n RSP <- NewRSP & FFFFFFFFFFFFFFF0H;\r\n SS <- NewSS;\r\n FI;\r\n IF IDT gate is 32-bit\r\n THEN\r\n\r\n\r\n\r\n CS:EIP <- Gate(CS:EIP); (* Segment descriptor information also loaded *)\r\n ELSE\r\n IF IDT gate 16-bit\r\n THEN\r\n CS:IP <- Gate(CS:IP);\r\n (* Segment descriptor information also loaded *)\r\n ELSE (* 64-bit IDT gate *)\r\n CS:RIP <- Gate(CS:RIP);\r\n (* Segment descriptor information also loaded *)\r\n FI;\r\n FI;\r\n IF IDT gate is 32-bit\r\n THEN\r\n Push(far pointer to old stack);\r\n (* Old SS and ESP, 3 words padded to 4 *)\r\n Push(EFLAGS);\r\n Push(far pointer to return instruction);\r\n (* Old CS and EIP, 3 words padded to 4 *)\r\n Push(ErrorCode); (* If needed, 4 bytes *)\r\n ELSE\r\n IF IDT gate 16-bit\r\n THEN\r\n Push(far pointer to old stack);\r\n (* Old SS and SP, 2 words *)\r\n Push(EFLAGS(15-0]);\r\n Push(far pointer to return instruction);\r\n (* Old CS and IP, 2 words *)\r\n Push(ErrorCode); (* If needed, 2 bytes *)\r\n ELSE (* 64-bit IDT gate *)\r\n Push(far pointer to old stack);\r\n (* Old SS and SP, each an 8-byte push *)\r\n Push(RFLAGS); (* 8-byte push *)\r\n Push(far pointer to return instruction);\r\n (* Old CS and RIP, each an 8-byte push *)\r\n Push(ErrorCode); (* If needed, 8-bytes *)\r\n FI;\r\n FI;\r\n CPL <- new code-segment DPL;\r\n CS(RPL) <- CPL;\r\n IF IDT gate is interrupt gate\r\n THEN IF <- 0 (* Interrupt flag set to 0, interrupts disabled *); FI;\r\n TF <- 0;\r\n VM <- 0;\r\n RF <- 0;\r\n NT <- 0;\r\nEND;\r\nINTERRUPT-FROM-VIRTUAL-8086-MODE:\r\n (* Identify stack-segment selector for privilege level 0 in current TSS *)\r\n IF current TSS is 32-bit\r\n THEN\r\n IF TSS limit < 9\r\n THEN #TS(error_code(current TSS selector,0,EXT)); FI;\r\n (* idt operand to error_code is 0 because selector is used *)\r\n NewSS <- 2 bytes loaded from (current TSS base + 8);\r\n\r\n\r\n\r\n NewESP <- 4 bytes loaded from (current TSS base + 4);\r\n ELSE (* current TSS is 16-bit *)\r\n IF TSS limit < 5\r\n THEN #TS(error_code(current TSS selector,0,EXT)); FI;\r\n (* idt operand to error_code is 0 because selector is used *)\r\n NewSS <- 2 bytes loaded from (current TSS base + 4);\r\n NewESP <- 2 bytes loaded from (current TSS base + 2);\r\n FI;\r\n IF NewSS is NULL\r\n THEN #TS(EXT); FI; (* Error code contains NULL selector *)\r\n IF NewSS index is not within its descriptor table limits\r\n or NewSS RPL != 0\r\n THEN #TS(error_code(NewSS,0,EXT)); FI;\r\n (* idt operand to error_code is 0 because selector is used *)\r\n Read new stack-segment descriptor for NewSS in GDT or LDT;\r\n IF new stack-segment DPL != 0 or stack segment does not indicate writable data segment\r\n THEN #TS(error_code(NewSS,0,EXT)); FI;\r\n (* idt operand to error_code is 0 because selector is used *)\r\n IF new stack segment not present\r\n THEN #SS(error_code(NewSS,0,EXT)); FI;\r\n (* idt operand to error_code is 0 because selector is used *)\r\n IF IDT gate is 32-bit\r\n THEN\r\n IF new stack does not have room for 40 bytes (error code pushed)\r\n or 36 bytes (no error code pushed)\r\n THEN #SS(error_code(NewSS,0,EXT)); FI;\r\n (* idt operand to error_code is 0 because selector is used *)\r\n ELSE (* IDT gate is 16-bit)\r\n IF new stack does not have room for 20 bytes (error code pushed)\r\n or 18 bytes (no error code pushed)\r\n THEN #SS(error_code(NewSS,0,EXT)); FI;\r\n (* idt operand to error_code is 0 because selector is used *)\r\n FI;\r\n IF instruction pointer from IDT gate is not within new code-segment limits\r\n THEN #GP(EXT); FI; (* Error code contains NULL selector *)\r\n tempEFLAGS <- EFLAGS;\r\n VM <- 0;\r\n TF <- 0;\r\n RF <- 0;\r\n NT <- 0;\r\n IF service through interrupt gate\r\n THEN IF = 0; FI;\r\n TempSS <- SS;\r\n TempESP <- ESP;\r\n SS <- NewSS;\r\n ESP <- NewESP;\r\n (* Following pushes are 16 bits for 16-bit IDT gates and 32 bits for 32-bit IDT gates;\r\n Segment selector pushes in 32-bit mode are padded to two words *)\r\n Push(GS);\r\n Push(FS);\r\n Push(DS);\r\n Push(ES);\r\n Push(TempSS);\r\n Push(TempESP);\r\n\r\n\r\n\r\n Push(TempEFlags);\r\n Push(CS);\r\n Push(EIP);\r\n GS <- 0; (* Segment registers made NULL, invalid for use in protected mode *)\r\n FS <- 0;\r\n DS <- 0;\r\n ES <- 0;\r\n CS:IP <- Gate(CS); (* Segment descriptor information also loaded *)\r\n IF OperandSize = 32\r\n THEN\r\n EIP <- Gate(instruction pointer);\r\n ELSE (* OperandSize is 16 *)\r\n EIP <- Gate(instruction pointer) AND 0000FFFFH;\r\n FI;\r\n (* Start execution of new routine in Protected Mode *)\r\nEND;\r\nINTRA-PRIVILEGE-LEVEL-INTERRUPT:\r\n (* PE = 1, DPL = CPL or conforming segment *)\r\n IF IA32_EFER.LMA = 1 (* IA-32e mode *)\r\n IF IDT-descriptor IST != 0\r\n THEN\r\n TSSstackAddress <- (IDT-descriptor IST << 3) + 28;\r\n IF (TSSstackAddress + 7) > TSS limit\r\n THEN #TS(error_code(current TSS selector,0,EXT)); FI;\r\n (* idt operand to error_code is 0 because selector is used *)\r\n NewRSP <- 8 bytes loaded from (current TSS base + TSSstackAddress);\r\n FI;\r\n IF 32-bit gate (* implies IA32_EFER.LMA = 0 *)\r\n THEN\r\n IF current stack does not have room for 16 bytes (error code pushed)\r\n or 12 bytes (no error code pushed)\r\n THEN #SS(EXT); FI; (* Error code contains NULL selector *)\r\n ELSE IF 16-bit gate (* implies IA32_EFER.LMA = 0 *)\r\n IF current stack does not have room for 8 bytes (error code pushed)\r\n or 6 bytes (no error code pushed)\r\n THEN #SS(EXT); FI; (* Error code contains NULL selector *)\r\n ELSE (* IA32_EFER.LMA = 1, 64-bit gate*)\r\n IF NewRSP contains a non-canonical address\r\n THEN #SS(EXT); (* Error code contains NULL selector *)\r\n FI;\r\n FI;\r\n IF (IA32_EFER.LMA = 0) (* Not IA-32e mode *)\r\n THEN\r\n IF instruction pointer from IDT gate is not within new code-segment limit\r\n THEN #GP(EXT); FI; (* Error code contains NULL selector *)\r\n ELSE\r\n IF instruction pointer from IDT gate contains a non-canonical address\r\n THEN #GP(EXT); FI; (* Error code contains NULL selector *)\r\n RSP <- NewRSP & FFFFFFFFFFFFFFF0H;\r\n FI;\r\n IF IDT gate is 32-bit (* implies IA32_EFER.LMA = 0 *)\r\n THEN\r\n Push (EFLAGS);\r\n Push (far pointer to return instruction); (* 3 words padded to 4 *)\r\n\r\n\r\n\r\n CS:EIP <- Gate(CS:EIP); (* Segment descriptor information also loaded *)\r\n Push (ErrorCode); (* If any *)\r\n ELSE\r\n IF IDT gate is 16-bit (* implies IA32_EFER.LMA = 0 *)\r\n THEN\r\n Push (FLAGS);\r\n Push (far pointer to return location); (* 2 words *)\r\n CS:IP <- Gate(CS:IP);\r\n (* Segment descriptor information also loaded *)\r\n Push (ErrorCode); (* If any *)\r\n ELSE (* IA32_EFER.LMA = 1, 64-bit gate*)\r\n Push(far pointer to old stack);\r\n (* Old SS and SP, each an 8-byte push *)\r\n Push(RFLAGS); (* 8-byte push *)\r\n Push(far pointer to return instruction);\r\n (* Old CS and RIP, each an 8-byte push *)\r\n Push(ErrorCode); (* If needed, 8 bytes *)\r\n CS:RIP <- GATE(CS:RIP);\r\n (* Segment descriptor information also loaded *)\r\n FI;\r\n FI;\r\n CS(RPL) <- CPL;\r\n IF IDT gate is interrupt gate\r\n THEN IF <- 0; FI; (* Interrupt flag set to 0; interrupts disabled *)\r\n TF <- 0;\r\n NT <- 0;\r\n VM <- 0;\r\n RF <- 0;\r\nEND;\r\n\r\nFlags Affected\r\nThe EFLAGS register is pushed onto the stack. The IF, TF, NT, AC, RF, and VM flags may be cleared, depending on\r\nthe mode of operation of the processor when the INT instruction is executed (see the \"Operation\" section). If the\r\ninterrupt uses a task gate, any flags may be set or cleared, controlled by the EFLAGS image in the new task's TSS.\r\n\r\nProtected Mode Exceptions\r\n#GP(error_code) If the instruction pointer in the IDT or in the interrupt-, trap-, or task gate is beyond the code\r\n segment limits.\r\n If the segment selector in the interrupt-, trap-, or task gate is NULL.\r\n If an interrupt-, trap-, or task gate, code segment, or TSS segment selector index is outside its\r\n descriptor table limits.\r\n If the vector selects a descriptor outside the IDT limits.\r\n If an IDT descriptor is not an interrupt-, trap-, or task-descriptor.\r\n If an interrupt is generated by the INT n, INT 3, or INTO instruction and the DPL of an inter-\r\n rupt-, trap-, or task-descriptor is less than the CPL.\r\n If the segment selector in an interrupt- or trap-gate does not point to a segment descriptor for\r\n a code segment.\r\n If the segment selector for a TSS has its local/global bit set for local.\r\n If a TSS segment descriptor specifies that the TSS is busy or not available.\r\n\r\n\r\n\r\n\r\n\r\n#SS(error_code) If pushing the return address, flags, or error code onto the stack exceeds the bounds of the\r\n stack segment and no stack switch occurs.\r\n If the SS register is being loaded and the segment pointed to is marked not present.\r\n If pushing the return address, flags, error code, or stack segment pointer exceeds the bounds\r\n of the new stack segment when a stack switch occurs.\r\n#NP(error_code) If code segment, interrupt-, trap-, or task gate, or TSS is not present.\r\n#TS(error_code) If the RPL of the stack segment selector in the TSS is not equal to the DPL of the code segment\r\n being accessed by the interrupt or trap gate.\r\n If DPL of the stack segment descriptor pointed to by the stack segment selector in the TSS is\r\n not equal to the DPL of the code segment descriptor for the interrupt or trap gate.\r\n If the stack segment selector in the TSS is NULL.\r\n If the stack segment for the TSS is not a writable data segment.\r\n If segment-selector index for stack segment is outside descriptor table limits.\r\n#PF(fault-code) If a page fault occurs.\r\n#UD If the LOCK prefix is used.\r\n#AC(EXT) If alignment checking is enabled, the gate DPL is 3, and a stack push is unaligned.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the interrupt vector number is outside the IDT limits.\r\n#SS If stack limit violation on push.\r\n If pushing the return address, flags, or error code onto the stack exceeds the bounds of the\r\n stack segment.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(error_code) (For INT n, INTO, or BOUND instruction) If the IOPL is less than 3 or the DPL of the interrupt-\r\n , trap-, or task-gate descriptor is not equal to 3.\r\n If the instruction pointer in the IDT or in the interrupt-, trap-, or task gate is beyond the code\r\n segment limits.\r\n If the segment selector in the interrupt-, trap-, or task gate is NULL.\r\n If a interrupt-, trap-, or task gate, code segment, or TSS segment selector index is outside its\r\n descriptor table limits.\r\n If the vector selects a descriptor outside the IDT limits.\r\n If an IDT descriptor is not an interrupt-, trap-, or task-descriptor.\r\n If an interrupt is generated by the INT n instruction and the DPL of an interrupt-, trap-, or\r\n task-descriptor is less than the CPL.\r\n If the segment selector in an interrupt- or trap-gate does not point to a segment descriptor for\r\n a code segment.\r\n If the segment selector for a TSS has its local/global bit set for local.\r\n#SS(error_code) If the SS register is being loaded and the segment pointed to is marked not present.\r\n If pushing the return address, flags, error code, stack segment pointer, or data segments\r\n exceeds the bounds of the stack segment.\r\n#NP(error_code) If code segment, interrupt-, trap-, or task gate, or TSS is not present.\r\n\r\n\r\n\r\n\r\n\r\n#TS(error_code) If the RPL of the stack segment selector in the TSS is not equal to the DPL of the code segment\r\n being accessed by the interrupt or trap gate.\r\n If DPL of the stack segment descriptor for the TSS's stack segment is not equal to the DPL of\r\n the code segment descriptor for the interrupt or trap gate.\r\n If the stack segment selector in the TSS is NULL.\r\n If the stack segment for the TSS is not a writable data segment.\r\n If segment-selector index for stack segment is outside descriptor table limits.\r\n#PF(fault-code) If a page fault occurs.\r\n#BP If the INT 3 instruction is executed.\r\n#OF If the INTO instruction is executed and the OF flag is set.\r\n#UD If the LOCK prefix is used.\r\n#AC(EXT) If alignment checking is enabled, the gate DPL is 3, and a stack push is unaligned.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(error_code) If the instruction pointer in the 64-bit interrupt gate or 64-bit trap gate is non-canonical.\r\n If the segment selector in the 64-bit interrupt or trap gate is NULL.\r\n If the vector selects a descriptor outside the IDT limits.\r\n If the vector points to a gate which is in non-canonical space.\r\n If the vector points to a descriptor which is not a 64-bit interrupt gate or 64-bit trap gate.\r\n If the descriptor pointed to by the gate selector is outside the descriptor table limit.\r\n If the descriptor pointed to by the gate selector is in non-canonical space.\r\n If the descriptor pointed to by the gate selector is not a code segment.\r\n If the descriptor pointed to by the gate selector doesn't have the L-bit set, or has both the L-\r\n bit and D-bit set.\r\n If the descriptor pointed to by the gate selector has DPL > CPL.\r\n#SS(error_code) If a push of the old EFLAGS, CS selector, EIP, or error code is in non-canonical space with no\r\n stack switch.\r\n If a push of the old SS selector, ESP, EFLAGS, CS selector, EIP, or error code is in non-canonical\r\n space on a stack switch (either CPL change or no-CPL with IST).\r\n#NP(error_code) If the 64-bit interrupt-gate, 64-bit trap-gate, or code segment is not present.\r\n#TS(error_code) If an attempt to load RSP from the TSS causes an access to non-canonical space.\r\n If the RSP from the TSS is outside descriptor table limits.\r\n#PF(fault-code) If a page fault occurs.\r\n#UD If the LOCK prefix is used.\r\n#AC(EXT) If alignment checking is enabled, the gate DPL is 3, and a stack push is unaligned.\r\n\r\n\r\n\r\n\r\n",
"mnem": "INT n"
},
{
"description": "-R:INT n",
"mnem": "INTO"
},
{
"description": "INVD-Invalidate Internal Caches\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F 08 INVD NP Valid Valid Flush internal caches; initiate flushing of\r\n external caches.\r\n NOTES:\r\n * See the IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nInvalidates (flushes) the processor's internal caches and issues a special-function bus cycle that directs external\r\ncaches to also flush themselves. Data held in internal caches is not written back to main memory.\r\nAfter executing this instruction, the processor does not wait for the external caches to complete their flushing oper-\r\nation before proceeding with instruction execution. It is the responsibility of hardware to respond to the cache flush\r\nsignal.\r\nThe INVD instruction is a privileged instruction. When the processor is running in protected mode, the CPL of a\r\nprogram or procedure must be 0 to execute this instruction.\r\nThe INVD instruction may be used when the cache is used as temporary memory and the cache contents need to\r\nbe invalidated rather than written back to memory. When the cache is used as temporary memory, no external\r\ndevice should be actively writing data to main memory.\r\nUse this instruction with care. Data cached internally and not written back to main memory will be lost. Note that\r\nany data from an external device to main memory (for example, via a PCIWrite) can be temporarily stored in the\r\ncaches; these data can be lost when an INVD instruction is executed. Unless there is a specific requirement or\r\nbenefit to flushing caches without writing back modified cache lines (for example, temporary memory, testing, or\r\nfault recovery where cache coherency with main memory is not a concern), software should instead use the\r\nWBINVD instruction.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nIA-32 Architecture Compatibility\r\nThe INVD instruction is implementation dependent; it may be implemented differently on different families of Intel\r\n64 or IA-32 processors. This instruction is not supported on IA-32 processors earlier than the Intel486 processor.\r\n\r\nOperation\r\nFlush(InternalCaches);\r\nSignalFlush(ExternalCaches);\r\nContinue (* Continue execution *)\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the current privilege level is not 0.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) The INVD instruction cannot be executed in virtual-8086 mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "INVD"
},
{
"description": "INVLPG-Invalidate TLB Entries\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F 01/7 INVLPG m M Valid Valid Invalidate TLB entries for page containing m.\r\n NOTES:\r\n * See the IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (r) NA NA NA\r\n\r\nDescription\r\nInvalidates any translation lookaside buffer (TLB) entries specified with the source operand. The source operand is\r\na memory address. The processor determines the page that contains that address and flushes all TLB entries for\r\nthat page.1\r\nThe INVLPG instruction is a privileged instruction. When the processor is running in protected mode, the CPL must\r\nbe 0 to execute this instruction.\r\nThe INVLPG instruction normally flushes TLB entries only for the specified page; however, in some cases, it may\r\nflush more entries, even the entire TLB. The instruction is guaranteed to invalidates only TLB entries associated\r\nwith the current PCID. (If PCIDs are disabled - CR4.PCIDE = 0 - the current PCID is 000H.) The instruction also\r\ninvalidates any global TLB entries for the specified page, regardless of PCID.\r\nFor more details on operations that flush the TLB, see \"MOV-Move to/from Control Registers\" in the Intel 64 and\r\nIA-32 Architectures Software Developer's Manual, Volume 2B and Section 4.10.4.1, \"Operations that Invalidate\r\nTLBs and Paging-Structure Caches,\" in the Intel 64 and IA-32 Architectures Software Developer's Manual,\r\nVolume 3A.\r\nThis instruction's operation is the same in all non-64-bit modes. It also operates the same in 64-bit mode, except\r\nif the memory address is in non-canonical form. In this case, INVLPG is the same as a NOP.\r\n\r\nIA-32 Architecture Compatibility\r\nThe INVLPG instruction is implementation dependent, and its function may be implemented differently on different\r\nfamilies of Intel 64 or IA-32 processors. This instruction is not supported on IA-32 processors earlier than the\r\nIntel486 processor.\r\n\r\nOperation\r\nInvalidate(RelevantTLBEntries);\r\nContinue; (* Continue execution *)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the current privilege level is not 0.\r\n#UD Operand is a register.\r\n If the LOCK prefix is used.\r\n\r\n\r\n\r\n1. If the paging structures map the linear address using a page larger than 4 KBytes and there are multiple TLB entries for that page\r\n (see Section 4.10.2.3, \"Details of TLB Use,\" in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A), the\r\n instruction invalidates all of them.\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#UD Operand is a register.\r\n If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) The INVLPG instruction cannot be executed at the virtual-8086 mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the current privilege level is not 0.\r\n#UD Operand is a register.\r\n If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "INVLPG"
},
{
"description": "INVPCID-Invalidate Process-Context Identifier\r\n Opcode/Instruction Op/ 64/32- CPUID Description\r\n En bit Feature\r\n Mode Flag\r\n 66 0F 38 82 /r RM NE/V INVPCID Invalidates entries in the TLBs and paging-structure\r\n INVPCID r32, m128 caches based on invalidation type in r32 and descrip-\r\n tor in m128.\r\n\r\n 66 0F 38 82 /r RM V/NE INVPCID Invalidates entries in the TLBs and paging-structure\r\n INVPCID r64, m128 caches based on invalidation type in r64 and descrip-\r\n tor in m128.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (R) ModRM:r/m (R) NA NA\r\n\r\nDescription\r\nInvalidates mappings in the translation lookaside buffers (TLBs) and paging-structure caches based on process-\r\ncontext identifier (PCID). (See Section 4.10, \"Caching Translation Information,\" in Intel 64 and IA-32 Architecture\r\nSoftware Developer's Manual, Volume 3A.) Invalidation is based on the INVPCID type specified in the register\r\noperand and the INVPCID descriptor specified in the memory operand.\r\nOutside 64-bit mode, the register operand is always 32 bits, regardless of the value of CS.D. In 64-bit mode the\r\nregister operand has 64 bits.\r\nThere are four INVPCID types currently defined:\r\n. Individual-address invalidation: If the INVPCID type is 0, the logical processor invalidates mappings-except\r\n global translations-for the linear address and PCID specified in the INVPCID descriptor.1 In some cases, the\r\n instruction may invalidate global translations or mappings for other linear addresses (or other PCIDs) as well.\r\n. Single-context invalidation: If the INVPCID type is 1, the logical processor invalidates all mappings-except\r\n global translations-associated with the PCID specified in the INVPCID descriptor. In some cases, the\r\n instruction may invalidate global translations or mappings for other PCIDs as well.\r\n. All-context invalidation, including global translations: If the INVPCID type is 2, the logical processor invalidates\r\n all mappings-including global translations-associated with any PCID.\r\n. All-context invalidation: If the INVPCID type is 3, the logical processor invalidates all mappings-except global\r\n translations-associated with any PCID. In some case, the instruction may invalidate global translations as\r\n well.\r\nThe INVPCID descriptor comprises 128 bits and consists of a PCID and a linear address as shown in Figure 3-24.\r\nFor INVPCID type 0, the processor uses the full 64 bits of the linear address even outside 64-bit mode; the linear\r\naddress is not used for other INVPCID types.\r\n\r\n\r\n\r\n\r\n 127 64 63 12 11 0\r\n Linear Address Reserved (must be zero) PCID\r\n\r\n\r\n\r\n\r\n Figure 3-24. INVPCID Descriptor\r\n\r\n1. If the paging structures map the linear address using a page larger than 4 KBytes and there are multiple TLB entries for that page\r\n (see Section 4.10.2.3, \"Details of TLB Use,\" in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A), the\r\n instruction invalidates all of them.\r\n\r\n\r\n\r\nIf CR4.PCIDE = 0, a logical processor does not cache information for any PCID other than 000H. In this case,\r\nexecutions with INVPCID types 0 and 1 are allowed only if the PCID specified in the INVPCID descriptor is 000H;\r\nexecutions with INVPCID types 2 and 3 invalidate mappings only for PCID 000H. Note that CR4.PCIDE must be 0\r\noutside 64-bit mode (see Chapter 4.10.1, \"Process-Context Identifiers (PCIDs)\" of the Intel 64 and IA-32 Archi-\r\ntectures Software Developer's Manual, Volume 3A).\r\n\r\nOperation\r\nINVPCID_TYPE <- value of register operand; // must be in the range of 0-3\r\nINVPCID_DESC <- value of memory operand;\r\nCASE INVPCID_TYPE OF\r\n 0: // individual-address invalidation\r\n PCID <- INVPCID_DESC[11:0];\r\n L_ADDR <- INVPCID_DESC[127:64];\r\n Invalidate mappings for L_ADDR associated with PCID except global translations;\r\n BREAK;\r\n 1: // single PCID invalidation\r\n PCID <- INVPCID_DESC[11:0];\r\n Invalidate all mappings associated with PCID except global translations;\r\n BREAK;\r\n 2: // all PCID invalidation including global translations\r\n Invalidate all mappings for all PCIDs, including global translations;\r\n BREAK;\r\n 3: // all PCID invalidation retaining global translations\r\n Invalidate all mappings for all PCIDs except global translations;\r\n BREAK;\r\nESAC;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nINVPCID: void _invpcid(unsigned __int32 type, void * descriptor);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the current privilege level is not 0.\r\n If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains an unusable segment.\r\n If the source operand is located in an execute-only code segment.\r\n If an invalid type is specified in the register operand, i.e., INVPCID_TYPE > 3.\r\n If bits 63:12 of INVPCID_DESC are not all zero.\r\n If INVPCID_TYPE is either 0 or 1 and INVPCID_DESC[11:0] is not zero.\r\n If INVPCID_TYPE is 0 and the linear address in INVPCID_DESC[127:64] is not canonical.\r\n#PF(fault-code) If a page fault occurs in accessing the memory operand.\r\n#SS(0) If the memory operand effective address is outside the SS segment limit.\r\n If the SS register contains an unusable segment.\r\n#UD If if CPUID.(EAX=07H, ECX=0H):EBX.INVPCID (bit 10) = 0.\r\n If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#GP If an invalid type is specified in the register operand, i.e., INVPCID_TYPE > 3.\r\n If bits 63:12 of INVPCID_DESC are not all zero.\r\n If INVPCID_TYPE is either 0 or 1 and INVPCID_DESC[11:0] is not zero.\r\n If INVPCID_TYPE is 0 and the linear address in INVPCID_DESC[127:64] is not canonical.\r\n#UD If CPUID.(EAX=07H, ECX=0H):EBX.INVPCID (bit 10) = 0.\r\n If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) The INVPCID instruction is not recognized in virtual-8086 mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the current privilege level is not 0.\r\n If the memory operand is in the CS, DS, ES, FS, or GS segments and the memory address is\r\n in a non-canonical form.\r\n If an invalid type is specified in the register operand, i.e., INVPCID_TYPE > 3.\r\n If bits 63:12 of INVPCID_DESC are not all zero.\r\n If CR4.PCIDE=0, INVPCID_TYPE is either 0 or 1, and INVPCID_DESC[11:0] is not zero.\r\n If INVPCID_TYPE is 0 and the linear address in INVPCID_DESC[127:64] is not canonical.\r\n#PF(fault-code) If a page fault occurs in accessing the memory operand.\r\n#SS(0) If the memory destination operand is in the SS segment and the memory address is in a non-\r\n canonical form.\r\n#UD If the LOCK prefix is used.\r\n If CPUID.(EAX=07H, ECX=0H):EBX.INVPCID (bit 10) = 0.\r\n\r\n\r\n\r\n\r\n",
"mnem": "INVPCID"
},
{
"description": "IRET/IRETD-Interrupt Return\r\nOpcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\nCF IRET NP Valid Valid Interrupt return (16-bit operand size).\r\nCF IRETD NP Valid Valid Interrupt return (32-bit operand size).\r\nREX.W + CF IRETQ NP Valid N.E. Interrupt return (64-bit operand size).\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nReturns program control from an exception or interrupt handler to a program or procedure that was interrupted by\r\nan exception, an external interrupt, or a software-generated interrupt. These instructions are also used to perform\r\na return from a nested task. (A nested task is created when a CALL instruction is used to initiate a task switch or\r\nwhen an interrupt or exception causes a task switch to an interrupt or exception handler.) See the section titled\r\n\"Task Linking\" in Chapter 7 of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\nIRET and IRETD are mnemonics for the same opcode. The IRETD mnemonic (interrupt return double) is intended\r\nfor use when returning from an interrupt when using the 32-bit operand size; however, most assemblers use the\r\nIRET mnemonic interchangeably for both operand sizes.\r\nIn Real-Address Mode, the IRET instruction preforms a far return to the interrupted program or procedure. During\r\nthis operation, the processor pops the return instruction pointer, return code segment selector, and EFLAGS image\r\nfrom the stack to the EIP, CS, and EFLAGS registers, respectively, and then resumes execution of the interrupted\r\nprogram or procedure.\r\nIn Protected Mode, the action of the IRET instruction depends on the settings of the NT (nested task) and VM flags\r\nin the EFLAGS register and the VM flag in the EFLAGS image stored on the current stack. Depending on the setting\r\nof these flags, the processor performs the following types of interrupt returns:\r\n. Return from virtual-8086 mode.\r\n. Return to virtual-8086 mode.\r\n. Intra-privilege level return.\r\n. Inter-privilege level return.\r\n. Return from nested task (task switch).\r\nIf the NT flag (EFLAGS register) is cleared, the IRET instruction performs a far return from the interrupt procedure,\r\nwithout a task switch. The code segment being returned to must be equally or less privileged than the interrupt\r\nhandler routine (as indicated by the RPL field of the code segment selector popped from the stack).\r\nAs with a real-address mode interrupt return, the IRET instruction pops the return instruction pointer, return code\r\nsegment selector, and EFLAGS image from the stack to the EIP, CS, and EFLAGS registers, respectively, and then\r\nresumes execution of the interrupted program or procedure. If the return is to another privilege level, the IRET\r\ninstruction also pops the stack pointer and SS from the stack, before resuming program execution. If the return is\r\nto virtual-8086 mode, the processor also pops the data segment registers from the stack.\r\nIf the NT flag is set, the IRET instruction performs a task switch (return) from a nested task (a task called with a\r\nCALL instruction, an interrupt, or an exception) back to the calling or interrupted task. The updated state of the\r\ntask executing the IRET instruction is saved in its TSS. If the task is re-entered later, the code that follows the IRET\r\ninstruction is executed.\r\nIf the NT flag is set and the processor is in IA-32e mode, the IRET instruction causes a general protection excep-\r\ntion.\r\nIf nonmaskable interrupts (NMIs) are blocked (see Section 6.7.1, \"Handling Multiple NMIs\" in the Intel 64 and\r\nIA-32 Architectures Software Developer's Manual, Volume 3A), execution of the IRET instruction unblocks NMIs.\r\n\r\n\r\n\r\n\r\nThis unblocking occurs even if the instruction causes a fault. In such a case, NMIs are unmasked before the excep-\r\ntion handler is invoked.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.W prefix promotes operation to 64\r\nbits (IRETQ). See the summary chart at the beginning of this section for encoding data and limits.\r\nSee \"Changes to Instruction Behavior in VMX Non-Root Operation\" in Chapter 25 of the Intel 64 and IA-32 Archi-\r\ntectures Software Developer's Manual, Volume 3C, for more information about the behavior of this instruction in\r\nVMX non-root operation.\r\n\r\nOperation\r\nIF PE = 0\r\n THEN GOTO REAL-ADDRESS-MODE;\r\nELSIF (IA32_EFER.LMA = 0)\r\n THEN\r\n IF (EFLAGS.VM = 1)\r\n THEN GOTO RETURN-FROM-VIRTUAL-8086-MODE;\r\n ELSE GOTO PROTECTED-MODE;\r\n FI;\r\n ELSE GOTO IA-32e-MODE;\r\nFI;\r\n\r\nREAL-ADDRESS-MODE;\r\n IF OperandSize = 32\r\n THEN\r\n EIP <- Pop();\r\n CS <- Pop(); (* 32-bit pop, high-order 16 bits discarded *)\r\n tempEFLAGS <- Pop();\r\n EFLAGS <- (tempEFLAGS AND 257FD5H) OR (EFLAGS AND 1A0000H);\r\n ELSE (* OperandSize = 16 *)\r\n EIP <- Pop(); (* 16-bit pop; clear upper 16 bits *)\r\n CS <- Pop(); (* 16-bit pop *)\r\n EFLAGS[15:0] <- Pop();\r\n FI;\r\n END;\r\n\r\nRETURN-FROM-VIRTUAL-8086-MODE:\r\n(* Processor is in virtual-8086 mode when IRET is executed and stays in virtual-8086 mode *)\r\n IF IOPL = 3 (* Virtual mode: PE = 1, VM = 1, IOPL = 3 *)\r\n THEN IF OperandSize = 32\r\n THEN\r\n EIP <- Pop();\r\n CS <- Pop(); (* 32-bit pop, high-order 16 bits discarded *)\r\n EFLAGS <- Pop();\r\n (* VM, IOPL,VIP and VIF EFLAG bits not modified by pop *)\r\n IF EIP not within CS limit\r\n THEN #GP(0); FI;\r\n ELSE (* OperandSize = 16 *)\r\n EIP <- Pop(); (* 16-bit pop; clear upper 16 bits *)\r\n CS <- Pop(); (* 16-bit pop *)\r\n EFLAGS[15:0] <- Pop(); (* IOPL in EFLAGS not modified by pop *)\r\n IF EIP not within CS limit\r\n THEN #GP(0); FI;\r\n FI;\r\n ELSE\r\n\r\n\r\n\r\n #GP(0); (* Trap to virtual-8086 monitor: PE = 1, VM = 1, IOPL < 3 *)\r\n FI;\r\nEND;\r\n\r\nPROTECTED-MODE:\r\n IF NT = 1\r\n THEN GOTO TASK-RETURN; (* PE = 1, VM = 0, NT = 1 *)\r\n FI;\r\n IF OperandSize = 32\r\n THEN\r\n EIP <- Pop();\r\n CS <- Pop(); (* 32-bit pop, high-order 16 bits discarded *)\r\n tempEFLAGS <- Pop();\r\n ELSE (* OperandSize = 16 *)\r\n EIP <- Pop(); (* 16-bit pop; clear upper bits *)\r\n CS <- Pop(); (* 16-bit pop *)\r\n tempEFLAGS <- Pop(); (* 16-bit pop; clear upper bits *)\r\n FI;\r\n IF tempEFLAGS(VM) = 1 and CPL = 0\r\n THEN GOTO RETURN-TO-VIRTUAL-8086-MODE;\r\n ELSE GOTO PROTECTED-MODE-RETURN;\r\n FI;\r\n\r\nTASK-RETURN: (* PE = 1, VM = 0, NT = 1 *)\r\n SWITCH-TASKS (without nesting) to TSS specified in link field of current TSS;\r\n Mark the task just abandoned as NOT BUSY;\r\n IF EIP is not within CS limit\r\n THEN #GP(0); FI;\r\nEND;\r\n\r\nRETURN-TO-VIRTUAL-8086-MODE:\r\n (* Interrupted procedure was in virtual-8086 mode: PE = 1, CPL=0, VM = 1 in flag image *)\r\n IF EIP not within CS limit\r\n THEN #GP(0); FI;\r\n EFLAGS <- tempEFLAGS;\r\n ESP <- Pop();\r\n SS <- Pop(); (* Pop 2 words; throw away high-order word *)\r\n ES <- Pop(); (* Pop 2 words; throw away high-order word *)\r\n DS <- Pop(); (* Pop 2 words; throw away high-order word *)\r\n FS <- Pop(); (* Pop 2 words; throw away high-order word *)\r\n GS <- Pop(); (* Pop 2 words; throw away high-order word *)\r\n CPL <- 3;\r\n (* Resume execution in Virtual-8086 mode *)\r\nEND;\r\n\r\nPROTECTED-MODE-RETURN: (* PE = 1 *)\r\n IF CS(RPL) > CPL\r\n THEN GOTO RETURN-TO-OUTER-PRIVILEGE-LEVEL;\r\n ELSE GOTO RETURN-TO-SAME-PRIVILEGE-LEVEL; FI;\r\nEND;\r\n\r\nRETURN-TO-OUTER-PRIVILEGE-LEVEL:\r\n IF OperandSize = 32\r\n THEN\r\n\r\n\r\n\r\n ESP <- Pop();\r\n SS <- Pop(); (* 32-bit pop, high-order 16 bits discarded *)\r\n ELSE IF OperandSize = 16\r\n THEN\r\n ESP <- Pop(); (* 16-bit pop; clear upper bits *)\r\n SS <- Pop(); (* 16-bit pop *)\r\n ELSE (* OperandSize = 64 *)\r\n RSP <- Pop();\r\n SS <- Pop(); (* 64-bit pop, high-order 48 bits discarded *)\r\n FI;\r\n IF new mode != 64-Bit Mode\r\n THEN\r\n IF EIP is not within CS limit\r\n THEN #GP(0); FI;\r\n ELSE (* new mode = 64-bit mode *)\r\n IF RIP is non-canonical\r\n THEN #GP(0); FI;\r\n FI;\r\n EFLAGS (CF, PF, AF, ZF, SF, TF, DF, OF, NT) <- tempEFLAGS;\r\n IF OperandSize = 32\r\n THEN EFLAGS(RF, AC, ID) <- tempEFLAGS; FI;\r\n IF CPL <= IOPL\r\n THEN EFLAGS(IF) <- tempEFLAGS; FI;\r\n IF CPL = 0\r\n THEN\r\n EFLAGS(IOPL) <- tempEFLAGS;\r\n IF OperandSize = 32\r\n THEN EFLAGS(VM, VIF, VIP) <- tempEFLAGS; FI;\r\n IF OperandSize = 64\r\n THEN EFLAGS(VIF, VIP) <- tempEFLAGS; FI;\r\n FI;\r\n CPL <- CS(RPL);\r\n FOR each SegReg in (ES, FS, GS, and DS)\r\n DO\r\n tempDesc <- descriptor cache for SegReg (* hidden part of segment register *)\r\n IF tempDesc(DPL) < CPL AND tempDesc(Type) is data or non-conforming code\r\n THEN (* Segment register invalid *)\r\n SegReg <- NULL;\r\n FI;\r\n OD;\r\nEND;\r\n\r\nRETURN-TO-SAME-PRIVILEGE-LEVEL: (* PE = 1, RPL = CPL *)\r\n IF new mode != 64-Bit Mode\r\n THEN\r\n IF EIP is not within CS limit\r\n THEN #GP(0); FI;\r\n ELSE (* new mode = 64-bit mode *)\r\n IF RIP is non-canonical\r\n THEN #GP(0); FI;\r\n FI;\r\n EFLAGS (CF, PF, AF, ZF, SF, TF, DF, OF, NT) <- tempEFLAGS;\r\n IF OperandSize = 32 or OperandSize = 64\r\n THEN EFLAGS(RF, AC, ID) <- tempEFLAGS; FI;\r\n\r\n\r\n\r\n IF CPL <= IOPL\r\n THEN EFLAGS(IF) <- tempEFLAGS; FI;\r\n IF CPL = 0\r\n THEN (* VM = 0 in flags image *)\r\n EFLAGS(IOPL) <- tempEFLAGS;\r\n IF OperandSize = 32 or OperandSize = 64\r\n THEN EFLAGS(VIF, VIP) <- tempEFLAGS; FI;\r\n FI;\r\nEND;\r\n\r\nIA-32e-MODE:\r\n IF NT = 1\r\n THEN #GP(0);\r\n ELSE IF OperandSize = 32\r\n THEN\r\n EIP <- Pop();\r\n CS <- Pop();\r\n tempEFLAGS <- Pop();\r\n ELSE IF OperandSize = 16\r\n THEN\r\n EIP <- Pop(); (* 16-bit pop; clear upper bits *)\r\n CS <- Pop(); (* 16-bit pop *)\r\n tempEFLAGS <- Pop(); (* 16-bit pop; clear upper bits *)\r\n FI;\r\n ELSE (* OperandSize = 64 *)\r\n THEN\r\n RIP <- Pop();\r\n CS <- Pop(); (* 64-bit pop, high-order 48 bits discarded *)\r\n tempRFLAGS <- Pop();\r\n FI;\r\n IF tempCS.RPL > CPL\r\n THEN GOTO RETURN-TO-OUTER-PRIVILEGE-LEVEL;\r\n ELSE\r\n IF instruction began in 64-Bit Mode\r\n THEN\r\n IF OperandSize = 32\r\n THEN\r\n ESP <- Pop();\r\n SS <- Pop(); (* 32-bit pop, high-order 16 bits discarded *)\r\n ELSE IF OperandSize = 16\r\n THEN\r\n ESP <- Pop(); (* 16-bit pop; clear upper bits *)\r\n SS <- Pop(); (* 16-bit pop *)\r\n ELSE (* OperandSize = 64 *)\r\n RSP <- Pop();\r\n SS <- Pop(); (* 64-bit pop, high-order 48 bits discarded *)\r\n FI;\r\n FI;\r\n GOTO RETURN-TO-SAME-PRIVILEGE-LEVEL; FI;\r\nEND;\r\n\r\n\r\n\r\n\r\n\r\nFlags Affected\r\nAll the flags and fields in the EFLAGS register are potentially modified, depending on the mode of operation of the\r\nprocessor. If performing a return from a nested task to a previous task, the EFLAGS register will be modified\r\naccording to the EFLAGS image stored in the previous task's TSS.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the return code or stack segment selector is NULL.\r\n If the return instruction pointer is not within the return code segment limit.\r\n#GP(selector) If a segment selector index is outside its descriptor table limits.\r\n If the return code segment selector RPL is less than the CPL.\r\n If the DPL of a conforming-code segment is greater than the return code segment selector\r\n RPL.\r\n If the DPL for a nonconforming-code segment is not equal to the RPL of the code segment\r\n selector.\r\n If the stack segment descriptor DPL is not equal to the RPL of the return code segment\r\n selector.\r\n If the stack segment is not a writable data segment.\r\n If the stack segment selector RPL is not equal to the RPL of the return code segment selector.\r\n If the segment descriptor for a code segment does not indicate it is a code segment.\r\n If the segment selector for a TSS has its local/global bit set for local.\r\n If a TSS segment descriptor specifies that the TSS is not busy.\r\n If a TSS segment descriptor specifies that the TSS is not available.\r\n#SS(0) If the top bytes of stack are not within stack limits.\r\n#NP(selector) If the return code or stack segment is not present.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If an unaligned memory reference occurs when the CPL is 3 and alignment checking is\r\n enabled.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If the return instruction pointer is not within the return code segment limit.\r\n#SS If the top bytes of stack are not within stack limits.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If the return instruction pointer is not within the return code segment limit.\r\n IF IOPL not equal to 3.\r\n#PF(fault-code) If a page fault occurs.\r\n#SS(0) If the top bytes of stack are not within stack limits.\r\n#AC(0) If an unaligned memory reference occurs and alignment checking is enabled.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\n#GP(0) If EFLAGS.NT[bit 14] = 1.\r\nOther exceptions same as in Protected Mode.\r\n\r\n\r\n\r\n\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If EFLAGS.NT[bit 14] = 1.\r\n If the return code segment selector is NULL.\r\n If the stack segment selector is NULL going back to compatibility mode.\r\n If the stack segment selector is NULL going back to CPL3 64-bit mode.\r\n If a NULL stack segment selector RPL is not equal to CPL going back to non-CPL3 64-bit mode.\r\n If the return instruction pointer is not within the return code segment limit.\r\n If the return instruction pointer is non-canonical.\r\n#GP(Selector) If a segment selector index is outside its descriptor table limits.\r\n If a segment descriptor memory address is non-canonical.\r\n If the segment descriptor for a code segment does not indicate it is a code segment.\r\n If the proposed new code segment descriptor has both the D-bit and L-bit set.\r\n If the DPL for a nonconforming-code segment is not equal to the RPL of the code segment\r\n selector.\r\n If CPL is greater than the RPL of the code segment selector.\r\n If the DPL of a conforming-code segment is greater than the return code segment selector\r\n RPL.\r\n If the stack segment is not a writable data segment.\r\n If the stack segment descriptor DPL is not equal to the RPL of the return code segment\r\n selector.\r\n If the stack segment selector RPL is not equal to the RPL of the return code segment selector.\r\n#SS(0) If an attempt to pop a value off the stack violates the SS limit.\r\n If an attempt to pop a value off the stack causes a non-canonical address to be referenced.\r\n#NP(selector) If the return code or stack segment is not present.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If an unaligned memory reference occurs when the CPL is 3 and alignment checking is\r\n enabled.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "IRET"
},
{
"description": "-R:IRET",
"mnem": "IRETD"
},
{
"description": "-R:IRET",
"mnem": "IRETQ"
},
{
"description": "JMP-Jump\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n EB cb JMP rel8 D Valid Valid Jump short, RIP = RIP + 8-bit displacement sign\r\n extended to 64-bits\r\n E9 cw JMP rel16 D N.S. Valid Jump near, relative, displacement relative to\r\n next instruction. Not supported in 64-bit\r\n mode.\r\n E9 cd JMP rel32 D Valid Valid Jump near, relative, RIP = RIP + 32-bit\r\n displacement sign extended to 64-bits\r\n FF /4 JMP r/m16 M N.S. Valid Jump near, absolute indirect, address = zero-\r\n extended r/m16. Not supported in 64-bit\r\n mode.\r\n FF /4 JMP r/m32 M N.S. Valid Jump near, absolute indirect, address given in\r\n r/m32. Not supported in 64-bit mode.\r\n FF /4 JMP r/m64 M Valid N.E. Jump near, absolute indirect, RIP = 64-Bit\r\n offset from register or memory\r\n EA cd JMP ptr16:16 D Inv. Valid Jump far, absolute, address given in operand\r\n EA cp JMP ptr16:32 D Inv. Valid Jump far, absolute, address given in operand\r\n FF /5 JMP m16:16 D Valid Valid Jump far, absolute indirect, address given in\r\n m16:16\r\n FF /5 JMP m16:32 D Valid Valid Jump far, absolute indirect, address given in\r\n m16:32.\r\n REX.W + FF /5 JMP m16:64 D Valid N.E. Jump far, absolute indirect, address given in\r\n m16:64.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n D Offset NA NA NA\r\n M ModRM:r/m (r) NA NA NA\r\n\r\nDescription\r\nTransfers program control to a different point in the instruction stream without recording return information. The\r\ndestination (target) operand specifies the address of the instruction being jumped to. This operand can be an\r\nimmediate value, a general-purpose register, or a memory location.\r\nThis instruction can be used to execute four different types of jumps:\r\n. Near jump-A jump to an instruction within the current code segment (the segment currently pointed to by the\r\n CS register), sometimes referred to as an intrasegment jump.\r\n. Short jump-A near jump where the jump range is limited to -128 to +127 from the current EIP value.\r\n. Far jump-A jump to an instruction located in a different segment than the current code segment but at the\r\n same privilege level, sometimes referred to as an intersegment jump.\r\n. Task switch-A jump to an instruction located in a different task.\r\nA task switch can only be executed in protected mode (see Chapter 7, in the Intel 64 and IA-32 Architectures\r\nSoftware Developer's Manual, Volume 3A, for information on performing task switches with the JMP instruction).\r\nNear and Short Jumps. When executing a near jump, the processor jumps to the address (within the current code\r\nsegment) that is specified with the target operand. The target operand specifies either an absolute offset (that is\r\nan offset from the base of the code segment) or a relative offset (a signed displacement relative to the current\r\n\r\n\r\n\r\n\r\n\r\nvalue of the instruction pointer in the EIP register). A near jump to a relative offset of 8-bits (rel8) is referred to as\r\na short jump. The CS register is not changed on near and short jumps.\r\nAn absolute offset is specified indirectly in a general-purpose register or a memory location (r/m16 or r/m32). The\r\noperand-size attribute determines the size of the target operand (16 or 32 bits). Absolute offsets are loaded\r\ndirectly into the EIP register. If the operand-size attribute is 16, the upper two bytes of the EIP register are cleared,\r\nresulting in a maximum instruction pointer size of 16 bits.\r\nA relative offset (rel8, rel16, or rel32) is generally specified as a label in assembly code, but at the machine code\r\nlevel, it is encoded as a signed 8-, 16-, or 32-bit immediate value. This value is added to the value in the EIP\r\nregister. (Here, the EIP register contains the address of the instruction following the JMP instruction). When using\r\nrelative offsets, the opcode (for short vs. near jumps) and the operand-size attribute (for near relative jumps)\r\ndetermines the size of the target operand (8, 16, or 32 bits).\r\nFar Jumps in Real-Address or Virtual-8086 Mode. When executing a far jump in real-address or virtual-8086 mode,\r\nthe processor jumps to the code segment and offset specified with the target operand. Here the target operand\r\nspecifies an absolute far address either directly with a pointer (ptr16:16 or ptr16:32) or indirectly with a memory\r\nlocation (m16:16 or m16:32). With the pointer method, the segment and address of the called procedure is\r\nencoded in the instruction, using a 4-byte (16-bit operand size) or 6-byte (32-bit operand size) far address imme-\r\ndiate. With the indirect method, the target operand specifies a memory location that contains a 4-byte (16-bit\r\noperand size) or 6-byte (32-bit operand size) far address. The far address is loaded directly into the CS and EIP\r\nregisters. If the operand-size attribute is 16, the upper two bytes of the EIP register are cleared.\r\nFar Jumps in Protected Mode. When the processor is operating in protected mode, the JMP instruction can be used\r\nto perform the following three types of far jumps:\r\n. A far jump to a conforming or non-conforming code segment.\r\n. A far jump through a call gate.\r\n. A task switch.\r\n(The JMP instruction cannot be used to perform inter-privilege-level far jumps.)\r\nIn protected mode, the processor always uses the segment selector part of the far address to access the corre-\r\nsponding descriptor in the GDT or LDT. The descriptor type (code segment, call gate, task gate, or TSS) and access\r\nrights determine the type of jump to be performed.\r\nIf the selected descriptor is for a code segment, a far jump to a code segment at the same privilege level is\r\nperformed. (If the selected code segment is at a different privilege level and the code segment is non-conforming,\r\na general-protection exception is generated.) A far jump to the same privilege level in protected mode is very\r\nsimilar to one carried out in real-address or virtual-8086 mode. The target operand specifies an absolute far\r\naddress either directly with a pointer (ptr16:16 or ptr16:32) or indirectly with a memory location (m16:16 or\r\nm16:32). The operand-size attribute determines the size of the offset (16 or 32 bits) in the far address. The new\r\ncode segment selector and its descriptor are loaded into CS register, and the offset from the instruction is loaded\r\ninto the EIP register. Note that a call gate (described in the next paragraph) can also be used to perform far call to\r\na code segment at the same privilege level. Using this mechanism provides an extra level of indirection and is the\r\npreferred method of making jumps between 16-bit and 32-bit code segments.\r\nWhen executing a far jump through a call gate, the segment selector specified by the target operand identifies the\r\ncall gate. (The offset part of the target operand is ignored.) The processor then jumps to the code segment speci-\r\nfied in the call gate descriptor and begins executing the instruction at the offset specified in the call gate. No stack\r\nswitch occurs. Here again, the target operand can specify the far address of the call gate either directly with a\r\npointer (ptr16:16 or ptr16:32) or indirectly with a memory location (m16:16 or m16:32).\r\nExecuting a task switch with the JMP instruction is somewhat similar to executing a jump through a call gate. Here\r\nthe target operand specifies the segment selector of the task gate for the task being switched to (and the offset\r\npart of the target operand is ignored). The task gate in turn points to the TSS for the task, which contains the\r\nsegment selectors for the task's code and stack segments. The TSS also contains the EIP value for the next instruc-\r\ntion that was to be executed before the task was suspended. This instruction pointer value is loaded into the EIP\r\nregister so that the task begins executing again at this next instruction.\r\nThe JMP instruction can also specify the segment selector of the TSS directly, which eliminates the indirection of the\r\ntask gate. See Chapter 7 in Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, for\r\ndetailed information on the mechanics of a task switch.\r\n\r\n\r\n\r\n\r\nNote that when you execute at task switch with a JMP instruction, the nested task flag (NT) is not set in the EFLAGS\r\nregister and the new TSS's previous task link field is not loaded with the old task's TSS selector. A return to the\r\nprevious task can thus not be carried out by executing the IRET instruction. Switching tasks with the JMP instruc-\r\ntion differs in this regard from the CALL instruction which does set the NT flag and save the previous task link infor-\r\nmation, allowing a return to the calling task with an IRET instruction.\r\nIn 64-Bit Mode - The instruction's operation size is fixed at 64 bits. If a selector points to a gate, then RIP equals\r\nthe 64-bit displacement taken from gate; else RIP equals the zero-extended offset from the far pointer referenced\r\nin the instruction.\r\nSee the summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nIF near jump\r\n IF 64-bit Mode\r\n THEN\r\n IF near relative jump\r\n THEN\r\n tempRIP <- RIP + DEST; (* RIP is instruction following JMP instruction*)\r\n ELSE (* Near absolute jump *)\r\n tempRIP <- DEST;\r\n FI;\r\n ELSE\r\n IF near relative jump\r\n THEN\r\n tempEIP <- EIP + DEST; (* EIP is instruction following JMP instruction*)\r\n ELSE (* Near absolute jump *)\r\n tempEIP <- DEST;\r\n FI;\r\n FI;\r\n IF (IA32_EFER.LMA = 0 or target mode = Compatibility mode)\r\n and tempEIP outside code segment limit\r\n THEN #GP(0); FI\r\n IF 64-bit mode and tempRIP is not canonical\r\n THEN #GP(0);\r\n FI;\r\n IF OperandSize = 32\r\n THEN\r\n EIP <- tempEIP;\r\n ELSE\r\n IF OperandSize = 16\r\n THEN (* OperandSize = 16 *)\r\n EIP <- tempEIP AND 0000FFFFH;\r\n ELSE (* OperandSize = 64)\r\n RIP <- tempRIP;\r\n FI;\r\n FI;\r\nFI;\r\nIF far jump and (PE = 0 or (PE = 1 AND VM = 1)) (* Real-address or virtual-8086 mode *)\r\n THEN\r\n tempEIP <- DEST(Offset); (* DEST is ptr16:32 or [m16:32] *)\r\n IF tempEIP is beyond code segment limit\r\n THEN #GP(0); FI;\r\n CS <- DEST(segment selector); (* DEST is ptr16:32 or [m16:32] *)\r\n IF OperandSize = 32\r\n\r\n\r\n\r\n THEN\r\n EIP <- tempEIP; (* DEST is ptr16:32 or [m16:32] *)\r\n ELSE (* OperandSize = 16 *)\r\n EIP <- tempEIP AND 0000FFFFH; (* Clear upper 16 bits *)\r\n FI;\r\nFI;\r\nIF far jump and (PE = 1 and VM = 0)\r\n(* IA-32e mode or protected mode, not virtual-8086 mode *)\r\n THEN\r\n IF effective address in the CS, DS, ES, FS, GS, or SS segment is illegal\r\n or segment selector in target operand NULL\r\n THEN #GP(0); FI;\r\n IF segment selector index not within descriptor table limits\r\n THEN #GP(new selector); FI;\r\n Read type and access rights of segment descriptor;\r\n IF (EFER.LMA = 0)\r\n THEN\r\n IF segment type is not a conforming or nonconforming code\r\n segment, call gate, task gate, or TSS\r\n THEN #GP(segment selector); FI;\r\n ELSE\r\n IF segment type is not a conforming or nonconforming code segment\r\n call gate\r\n THEN #GP(segment selector); FI;\r\n FI;\r\n Depending on type and access rights:\r\n GO TO CONFORMING-CODE-SEGMENT;\r\n GO TO NONCONFORMING-CODE-SEGMENT;\r\n GO TO CALL-GATE;\r\n GO TO TASK-GATE;\r\n GO TO TASK-STATE-SEGMENT;\r\n ELSE\r\n #GP(segment selector);\r\nFI;\r\nCONFORMING-CODE-SEGMENT:\r\n IF L-Bit = 1 and D-BIT = 1 and IA32_EFER.LMA = 1\r\n THEN GP(new code segment selector); FI;\r\n IF DPL > CPL\r\n THEN #GP(segment selector); FI;\r\n IF segment not present\r\n THEN #NP(segment selector); FI;\r\n tempEIP <- DEST(Offset);\r\n IF OperandSize = 16\r\n THEN tempEIP <- tempEIP AND 0000FFFFH;\r\n FI;\r\n IF (IA32_EFER.LMA = 0 or target mode = Compatibility mode) and\r\n tempEIP outside code segment limit\r\n THEN #GP(0); FI\r\n IF tempEIP is non-canonical\r\n THEN #GP(0); FI;\r\n CS <- DEST[segment selector]; (* Segment descriptor information also loaded *)\r\n CS(RPL) <- CPL\r\n EIP <- tempEIP;\r\nEND;\r\n\r\n\r\n\r\nNONCONFORMING-CODE-SEGMENT:\r\n IF L-Bit = 1 and D-BIT = 1 and IA32_EFER.LMA = 1\r\n THEN GP(new code segment selector); FI;\r\n IF (RPL > CPL) OR (DPL != CPL)\r\n THEN #GP(code segment selector); FI;\r\n IF segment not present\r\n THEN #NP(segment selector); FI;\r\n tempEIP <- DEST(Offset);\r\n IF OperandSize = 16\r\n THEN tempEIP <- tempEIP AND 0000FFFFH; FI;\r\n IF (IA32_EFER.LMA = 0 OR target mode = Compatibility mode)\r\n and tempEIP outside code segment limit\r\n THEN #GP(0); FI\r\n IF tempEIP is non-canonical THEN #GP(0); FI;\r\n CS <- DEST[segment selector]; (* Segment descriptor information also loaded *)\r\n CS(RPL) <- CPL;\r\n EIP <- tempEIP;\r\nEND;\r\n\r\nCALL-GATE:\r\n IF call gate DPL < CPL\r\n or call gate DPL < call gate segment-selector RPL\r\n THEN #GP(call gate selector); FI;\r\n IF call gate not present\r\n THEN #NP(call gate selector); FI;\r\n IF call gate code-segment selector is NULL\r\n THEN #GP(0); FI;\r\n IF call gate code-segment selector index outside descriptor table limits\r\n THEN #GP(code segment selector); FI;\r\n Read code segment descriptor;\r\n IF code-segment segment descriptor does not indicate a code segment\r\n or code-segment segment descriptor is conforming and DPL > CPL\r\n or code-segment segment descriptor is non-conforming and DPL != CPL\r\n THEN #GP(code segment selector); FI;\r\n IF IA32_EFER.LMA = 1 and (code-segment descriptor is not a 64-bit code segment\r\n or code-segment segment descriptor has both L-Bit and D-bit set)\r\n THEN #GP(code segment selector); FI;\r\n IF code segment is not present\r\n THEN #NP(code-segment selector); FI;\r\n IF instruction pointer is not within code-segment limit\r\n THEN #GP(0); FI;\r\n tempEIP <- DEST(Offset);\r\n IF GateSize = 16\r\n THEN tempEIP <- tempEIP AND 0000FFFFH; FI;\r\n IF (IA32_EFER.LMA = 0 OR target mode = Compatibility mode) AND tempEIP\r\n outside code segment limit\r\n THEN #GP(0); FI\r\n CS <- DEST[SegmentSelector); (* Segment descriptor information also loaded *)\r\n CS(RPL) <- CPL;\r\n EIP <- tempEIP;\r\nEND;\r\nTASK-GATE:\r\n IF task gate DPL < CPL\r\n or task gate DPL < task gate segment-selector RPL\r\n\r\n\r\n\r\n THEN #GP(task gate selector); FI;\r\n IF task gate not present\r\n THEN #NP(gate selector); FI;\r\n Read the TSS segment selector in the task-gate descriptor;\r\n IF TSS segment selector local/global bit is set to local\r\n or index not within GDT limits\r\n or TSS descriptor specifies that the TSS is busy\r\n THEN #GP(TSS selector); FI;\r\n IF TSS not present\r\n THEN #NP(TSS selector); FI;\r\n SWITCH-TASKS to TSS;\r\n IF EIP not within code segment limit\r\n THEN #GP(0); FI;\r\nEND;\r\nTASK-STATE-SEGMENT:\r\n IF TSS DPL < CPL\r\n or TSS DPL < TSS segment-selector RPL\r\n or TSS descriptor indicates TSS not available\r\n THEN #GP(TSS selector); FI;\r\n IF TSS is not present\r\n THEN #NP(TSS selector); FI;\r\n SWITCH-TASKS to TSS;\r\n IF EIP not within code segment limit\r\n THEN #GP(0); FI;\r\nEND;\r\n\r\nFlags Affected\r\nAll flags are affected if a task switch occurs; no flags are affected if a task switch does not occur.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If offset in target operand, call gate, or TSS is beyond the code segment limits.\r\n If the segment selector in the destination operand, call gate, task gate, or TSS is NULL.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n#GP(selector) If the segment selector index is outside descriptor table limits.\r\n If the segment descriptor pointed to by the segment selector in the destination operand is not\r\n for a conforming-code segment, nonconforming-code segment, call gate, task gate, or task\r\n state segment.\r\n If the DPL for a nonconforming-code segment is not equal to the CPL\r\n (When not using a call gate.) If the RPL for the segment's segment selector is greater than the\r\n CPL.\r\n If the DPL for a conforming-code segment is greater than the CPL.\r\n If the DPL from a call-gate, task-gate, or TSS segment descriptor is less than the CPL or than\r\n the RPL of the call-gate, task-gate, or TSS's segment selector.\r\n If the segment descriptor for selector in a call gate does not indicate it is a code segment.\r\n If the segment descriptor for the segment selector in a task gate does not indicate an available\r\n TSS.\r\n If the segment selector for a TSS has its local/global bit set for local.\r\n If a TSS segment descriptor specifies that the TSS is busy or not available.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n\r\n\r\n\r\n\r\n#NP (selector) If the code segment being accessed is not present.\r\n If call gate, task gate, or TSS not present.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3. (Only occurs when fetching target from memory.)\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If the target operand is beyond the code segment limits.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made. (Only occurs\r\n when fetching target from memory.)\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame as 64-bit mode exceptions.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If a memory address is non-canonical.\r\n If target offset in destination operand is non-canonical.\r\n If target offset in destination operand is beyond the new code segment limit.\r\n If the segment selector in the destination operand is NULL.\r\n If the code segment selector in the 64-bit gate is NULL.\r\n#GP(selector) If the code segment or 64-bit call gate is outside descriptor table limits.\r\n If the code segment or 64-bit call gate overlaps non-canonical space.\r\n If the segment descriptor from a 64-bit call gate is in non-canonical space.\r\n If the segment descriptor pointed to by the segment selector in the destination operand is not\r\n for a conforming-code segment, nonconforming-code segment, 64-bit call gate.\r\n If the segment descriptor pointed to by the segment selector in the destination operand is a\r\n code segment, and has both the D-bit and the L-bit set.\r\n If the DPL for a nonconforming-code segment is not equal to the CPL, or the RPL for the\r\n segment's segment selector is greater than the CPL.\r\n If the DPL for a conforming-code segment is greater than the CPL.\r\n If the DPL from a 64-bit call-gate is less than the CPL or than the RPL of the 64-bit call-gate.\r\n If the upper type field of a 64-bit call gate is not 0x0.\r\n If the segment selector from a 64-bit call gate is beyond the descriptor table limits.\r\n If the code segment descriptor pointed to by the selector in the 64-bit gate doesn't have the L-\r\n bit set and the D-bit clear.\r\n If the segment descriptor for a segment selector from the 64-bit call gate does not indicate it\r\n is a code segment.\r\n If the code segment is non-conforming and CPL != DPL.\r\n\r\n\r\n\r\n If the code segment is confirming and CPL < DPL.\r\n#NP(selector) If a code segment or 64-bit call gate is not present.\r\n#UD (64-bit mode only) If a far jump is direct to an absolute address in memory.\r\n If the LOCK prefix is used.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "JMP"
},
{
"description": "Jcc-Jump if Condition Is Met\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 77 cb JA rel8 D Valid Valid Jump short if above (CF=0 and ZF=0).\r\n 73 cb JAE rel8 D Valid Valid Jump short if above or equal (CF=0).\r\n 72 cb JB rel8 D Valid Valid Jump short if below (CF=1).\r\n 76 cb JBE rel8 D Valid Valid Jump short if below or equal (CF=1 or ZF=1).\r\n 72 cb JC rel8 D Valid Valid Jump short if carry (CF=1).\r\n E3 cb JCXZ rel8 D N.E. Valid Jump short if CX register is 0.\r\n E3 cb JECXZ rel8 D Valid Valid Jump short if ECX register is 0.\r\n E3 cb JRCXZ rel8 D Valid N.E. Jump short if RCX register is 0.\r\n 74 cb JE rel8 D Valid Valid Jump short if equal (ZF=1).\r\n 7F cb JG rel8 D Valid Valid Jump short if greater (ZF=0 and SF=OF).\r\n 7D cb JGE rel8 D Valid Valid Jump short if greater or equal (SF=OF).\r\n 7C cb JL rel8 D Valid Valid Jump short if less (SF!= OF).\r\n 7E cb JLE rel8 D Valid Valid Jump short if less or equal (ZF=1 or SF!= OF).\r\n 76 cb JNA rel8 D Valid Valid Jump short if not above (CF=1 or ZF=1).\r\n 72 cb JNAE rel8 D Valid Valid Jump short if not above or equal (CF=1).\r\n 73 cb JNB rel8 D Valid Valid Jump short if not below (CF=0).\r\n 77 cb JNBE rel8 D Valid Valid Jump short if not below or equal (CF=0 and\r\n ZF=0).\r\n 73 cb JNC rel8 D Valid Valid Jump short if not carry (CF=0).\r\n 75 cb JNE rel8 D Valid Valid Jump short if not equal (ZF=0).\r\n 7E cb JNG rel8 D Valid Valid Jump short if not greater (ZF=1 or SF!= OF).\r\n 7C cb JNGE rel8 D Valid Valid Jump short if not greater or equal (SF!= OF).\r\n 7D cb JNL rel8 D Valid Valid Jump short if not less (SF=OF).\r\n 7F cb JNLE rel8 D Valid Valid Jump short if not less or equal (ZF=0 and\r\n SF=OF).\r\n 71 cb JNO rel8 D Valid Valid Jump short if not overflow (OF=0).\r\n 7B cb JNP rel8 D Valid Valid Jump short if not parity (PF=0).\r\n 79 cb JNS rel8 D Valid Valid Jump short if not sign (SF=0).\r\n\r\n\r\n 75 cb JNZ rel8 D Valid Valid Jump short if not zero (ZF=0).\r\n 70 cb JO rel8 D Valid Valid Jump short if overflow (OF=1).\r\n 7A cb JP rel8 D Valid Valid Jump short if parity (PF=1).\r\n 7A cb JPE rel8 D Valid Valid Jump short if parity even (PF=1).\r\n 7B cb JPO rel8 D Valid Valid Jump short if parity odd (PF=0).\r\n 78 cb JS rel8 D Valid Valid Jump short if sign (SF=1).\r\n 74 cb JZ rel8 D Valid Valid Jump short if zero (ZF = 1).\r\n 0F 87 cw JA rel16 D N.S. Valid Jump near if above (CF=0 and ZF=0). Not\r\n supported in 64-bit mode.\r\n 0F 87 cd JA rel32 D Valid Valid Jump near if above (CF=0 and ZF=0).\r\n 0F 83 cw JAE rel16 D N.S. Valid Jump near if above or equal (CF=0). Not\r\n supported in 64-bit mode.\r\n\r\n\r\n\r\nOpcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n0F 83 cd JAE rel32 D Valid Valid Jump near if above or equal (CF=0).\r\n0F 82 cw JB rel16 D N.S. Valid Jump near if below (CF=1). Not supported in\r\n 64-bit mode.\r\n0F 82 cd JB rel32 D Valid Valid Jump near if below (CF=1).\r\n0F 86 cw JBE rel16 D N.S. Valid Jump near if below or equal (CF=1 or ZF=1).\r\n Not supported in 64-bit mode.\r\n0F 86 cd JBE rel32 D Valid Valid Jump near if below or equal (CF=1 or ZF=1).\r\n0F 82 cw JC rel16 D N.S. Valid Jump near if carry (CF=1). Not supported in\r\n 64-bit mode.\r\n0F 82 cd JC rel32 D Valid Valid Jump near if carry (CF=1).\r\n0F 84 cw JE rel16 D N.S. Valid Jump near if equal (ZF=1). Not supported in\r\n 64-bit mode.\r\n0F 84 cd JE rel32 D Valid Valid Jump near if equal (ZF=1).\r\n0F 84 cw JZ rel16 D N.S. Valid Jump near if 0 (ZF=1). Not supported in 64-bit\r\n mode.\r\n0F 84 cd JZ rel32 D Valid Valid Jump near if 0 (ZF=1).\r\n0F 8F cw JG rel16 D N.S. Valid Jump near if greater (ZF=0 and SF=OF). Not\r\n supported in 64-bit mode.\r\n0F 8F cd JG rel32 D Valid Valid Jump near if greater (ZF=0 and SF=OF).\r\n0F 8D cw JGE rel16 D N.S. Valid Jump near if greater or equal (SF=OF). Not\r\n supported in 64-bit mode.\r\n0F 8D cd JGE rel32 D Valid Valid Jump near if greater or equal (SF=OF).\r\n0F 8C cw JL rel16 D N.S. Valid Jump near if less (SF!= OF). Not supported in\r\n 64-bit mode.\r\n0F 8C cd JL rel32 D Valid Valid Jump near if less (SF!= OF).\r\n0F 8E cw JLE rel16 D N.S. Valid Jump near if less or equal (ZF=1 or SF!= OF).\r\n Not supported in 64-bit mode.\r\n0F 8E cd JLE rel32 D Valid Valid Jump near if less or equal (ZF=1 or SF!= OF).\r\n0F 86 cw JNA rel16 D N.S. Valid Jump near if not above (CF=1 or ZF=1). Not\r\n supported in 64-bit mode.\r\n0F 86 cd JNA rel32 D Valid Valid Jump near if not above (CF=1 or ZF=1).\r\n0F 82 cw JNAE rel16 D N.S. Valid Jump near if not above or equal (CF=1). Not\r\n supported in 64-bit mode.\r\n0F 82 cd JNAE rel32 D Valid Valid Jump near if not above or equal (CF=1).\r\n0F 83 cw JNB rel16 D N.S. Valid Jump near if not below (CF=0). Not supported\r\n in 64-bit mode.\r\n0F 83 cd JNB rel32 D Valid Valid Jump near if not below (CF=0).\r\n0F 87 cw JNBE rel16 D N.S. Valid Jump near if not below or equal (CF=0 and\r\n ZF=0). Not supported in 64-bit mode.\r\n0F 87 cd JNBE rel32 D Valid Valid Jump near if not below or equal (CF=0 and\r\n ZF=0).\r\n\r\n\r\n0F 83 cw JNC rel16 D N.S. Valid Jump near if not carry (CF=0). Not supported\r\n in 64-bit mode.\r\n0F 83 cd JNC rel32 D Valid Valid Jump near if not carry (CF=0).\r\n\r\n\r\n\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F 85 cw JNE rel16 D N.S. Valid Jump near if not equal (ZF=0). Not supported\r\n in 64-bit mode.\r\n 0F 85 cd JNE rel32 D Valid Valid Jump near if not equal (ZF=0).\r\n 0F 8E cw JNG rel16 D N.S. Valid Jump near if not greater (ZF=1 or SF!= OF).\r\n Not supported in 64-bit mode.\r\n 0F 8E cd JNG rel32 D Valid Valid Jump near if not greater (ZF=1 or SF!= OF).\r\n 0F 8C cw JNGE rel16 D N.S. Valid Jump near if not greater or equal (SF!= OF).\r\n Not supported in 64-bit mode.\r\n 0F 8C cd JNGE rel32 D Valid Valid Jump near if not greater or equal (SF!= OF).\r\n 0F 8D cw JNL rel16 D N.S. Valid Jump near if not less (SF=OF). Not supported\r\n in 64-bit mode.\r\n 0F 8D cd JNL rel32 D Valid Valid Jump near if not less (SF=OF).\r\n 0F 8F cw JNLE rel16 D N.S. Valid Jump near if not less or equal (ZF=0 and\r\n SF=OF). Not supported in 64-bit mode.\r\n 0F 8F cd JNLE rel32 D Valid Valid Jump near if not less or equal (ZF=0 and\r\n SF=OF).\r\n 0F 81 cw JNO rel16 D N.S. Valid Jump near if not overflow (OF=0). Not\r\n supported in 64-bit mode.\r\n 0F 81 cd JNO rel32 D Valid Valid Jump near if not overflow (OF=0).\r\n 0F 8B cw JNP rel16 D N.S. Valid Jump near if not parity (PF=0). Not supported\r\n in 64-bit mode.\r\n 0F 8B cd JNP rel32 D Valid Valid Jump near if not parity (PF=0).\r\n 0F 89 cw JNS rel16 D N.S. Valid Jump near if not sign (SF=0). Not supported in\r\n 64-bit mode.\r\n 0F 89 cd JNS rel32 D Valid Valid Jump near if not sign (SF=0).\r\n 0F 85 cw JNZ rel16 D N.S. Valid Jump near if not zero (ZF=0). Not supported in\r\n 64-bit mode.\r\n 0F 85 cd JNZ rel32 D Valid Valid Jump near if not zero (ZF=0).\r\n 0F 80 cw JO rel16 D N.S. Valid Jump near if overflow (OF=1). Not supported\r\n in 64-bit mode.\r\n 0F 80 cd JO rel32 D Valid Valid Jump near if overflow (OF=1).\r\n 0F 8A cw JP rel16 D N.S. Valid Jump near if parity (PF=1). Not supported in\r\n 64-bit mode.\r\n 0F 8A cd JP rel32 D Valid Valid Jump near if parity (PF=1).\r\n 0F 8A cw JPE rel16 D N.S. Valid Jump near if parity even (PF=1). Not\r\n supported in 64-bit mode.\r\n 0F 8A cd JPE rel32 D Valid Valid Jump near if parity even (PF=1).\r\n 0F 8B cw JPO rel16 D N.S. Valid Jump near if parity odd (PF=0). Not supported\r\n in 64-bit mode.\r\n 0F 8B cd JPO rel32 D Valid Valid Jump near if parity odd (PF=0).\r\n 0F 88 cw JS rel16 D N.S. Valid Jump near if sign (SF=1). Not supported in 64-\r\n bit mode.\r\n\r\n\r\n\r\n\r\nOpcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n0F 88 cd JS rel32 D Valid Valid Jump near if sign (SF=1).\r\n0F 84 cw JZ rel16 D N.S. Valid Jump near if 0 (ZF=1). Not supported in 64-bit\r\n mode.\r\n0F 84 cd JZ rel32 D Valid Valid Jump near if 0 (ZF=1).\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n D Offset NA NA NA\r\n\r\nDescription\r\nChecks the state of one or more of the status flags in the EFLAGS register (CF, OF, PF, SF, and ZF) and, if the flags\r\nare in the specified state (condition), performs a jump to the target instruction specified by the destination\r\noperand. A condition code (cc) is associated with each instruction to indicate the condition being tested for. If the\r\ncondition is not satisfied, the jump is not performed and execution continues with the instruction following the Jcc\r\ninstruction.\r\nThe target instruction is specified with a relative offset (a signed offset relative to the current value of the instruc-\r\ntion pointer in the EIP register). A relative offset (rel8, rel16, or rel32) is generally specified as a label in assembly\r\ncode, but at the machine code level, it is encoded as a signed, 8-bit or 32-bit immediate value, which is added to\r\nthe instruction pointer. Instruction coding is most efficient for offsets of -128 to +127. If the operand-size attribute\r\nis 16, the upper two bytes of the EIP register are cleared, resulting in a maximum instruction pointer size of 16 bits.\r\nThe conditions for each Jcc mnemonic are given in the \"Description\" column of the table on the preceding page. The\r\nterms \"less\" and \"greater\" are used for comparisons of signed integers and the terms \"above\" and \"below\" are used\r\nfor unsigned integers.\r\nBecause a particular state of the status flags can sometimes be interpreted in two ways, two mnemonics are\r\ndefined for some opcodes. For example, the JA (jump if above) instruction and the JNBE (jump if not below or\r\nequal) instruction are alternate mnemonics for the opcode 77H.\r\nThe Jcc instruction does not support far jumps (jumps to other code segments). When the target for the conditional\r\njump is in a different segment, use the opposite condition from the condition being tested for the Jcc instruction,\r\nand then access the target with an unconditional far jump (JMP instruction) to the other segment. For example, the\r\nfollowing conditional far jump is illegal:\r\n JZ FARLABEL;\r\nTo accomplish this far jump, use the following two instructions:\r\n JNZ BEYOND;\r\n JMP FARLABEL;\r\n BEYOND:\r\nThe JRCXZ, JECXZ and JCXZ instructions differ from other Jcc instructions because they do not check status flags.\r\nInstead, they check RCX, ECX or CX for 0. The register checked is determined by the address-size attribute. These\r\ninstructions are useful when used at the beginning of a loop that terminates with a conditional loop instruction\r\n(such as LOOPNE). They can be used to prevent an instruction sequence from entering a loop when RCX, ECX or CX\r\nis 0. This would cause the loop to execute 264, 232 or 64K times (not zero times).\r\nAll conditional jumps are converted to code fetches of one or two cache lines, regardless of jump address or cache-\r\nability.\r\nIn 64-bit mode, operand size is fixed at 64 bits. JMP Short is RIP = RIP + 8-bit offset sign extended to 64 bits. JMP\r\nNear is RIP = RIP + 32-bit offset sign extended to 64-bits.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIF condition\r\n THEN\r\n tempEIP <- EIP + SignExtend(DEST);\r\n IF OperandSize = 16\r\n THEN tempEIP <- tempEIP AND 0000FFFFH;\r\n FI;\r\n IF tempEIP is not within code segment limit\r\n THEN #GP(0);\r\n ELSE EIP <- tempEIP\r\n FI;\r\nFI;\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the offset being jumped to is beyond the limits of the CS segment.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If the offset being jumped to is beyond the limits of the CS segment or is outside of the effec-\r\n tive address space from 0 to FFFFH. This condition can occur if a 32-bit address size override\r\n prefix is used.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in real address mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "Jcc"
},
{
"description": "-R:KADDW",
"mnem": "KADDB"
},
{
"description": "-R:KADDW",
"mnem": "KADDD"
},
{
"description": "-R:KADDW",
"mnem": "KADDQ"
},
{
"description": "KADDW/KADDB/KADDQ/KADDD-ADD Two Masks\r\n Opcode/ Op/En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n VEX.L1.0F.W0 4A /r RVR V/V AVX512DQ Add 16 bits masks in k2 and k3 and place result in k1.\r\n KADDW k1, k2, k3\r\n VEX.L1.66.0F.W0 4A /r RVR V/V AVX512DQ Add 8 bits masks in k2 and k3 and place result in k1.\r\n KADDB k1, k2, k3\r\n VEX.L1.0F.W1 4A /r RVR V/V AVX512BW Add 64 bits masks in k2 and k3 and place result in k1.\r\n KADDQ k1, k2, k3\r\n VEX.L1.66.0F.W1 4A /r RVR V/V AVX512BW Add 32 bits masks in k2 and k3 and place result in k1.\r\n KADDD k1, k2, k3\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3\r\n RVR ModRM:reg (w) VEX.1vvv (r) ModRM:r/m (r, ModRM:[7:6] must be 11b)\r\n\r\nDescription\r\nAdds the vector mask k2 and the vector mask k3, and writes the result into vector mask k1.\r\n\r\nOperation\r\nKADDW\r\nDEST[15:0] <- SRC1[15:0] + SRC2[15:0]\r\nDEST[MAX_KL-1:16] <- 0\r\n\r\nKADDB\r\nDEST[7:0] <- SRC1[7:0] + SRC2[7:0]\r\nDEST[MAX_KL-1:8] <- 0\r\n\r\nKADDQ\r\nDEST[63:0] <- SRC1[63:0] + SRC2[63:0]\r\nDEST[MAX_KL-1:64] <- 0\r\n\r\nKADDD\r\nDEST[31:0] <- SRC1[31:0] + SRC2[31:0]\r\nDEST[MAX_KL-1:32] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type K20.\r\n\r\n\r\n\r\n\r\n",
"mnem": "KADDW"
},
{
"description": "-R:KANDW",
"mnem": "KANDB"
},
{
"description": "-R:KANDW",
"mnem": "KANDD"
},
{
"description": "-R:KANDNW",
"mnem": "KANDNB"
},
{
"description": "-R:KANDNW",
"mnem": "KANDND"
},
{
"description": "-R:KANDNW",
"mnem": "KANDNQ"
},
{
"description": "KANDNW/KANDNB/KANDNQ/KANDND-Bitwise Logical AND NOT Masks\r\n Opcode/ Op/En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n VEX.NDS.L1.0F.W0 42 /r RVR V/V AVX512F Bitwise AND NOT 16 bits masks k2 and k3 and place result in\r\n KANDNW k1, k2, k3 k1.\r\n VEX.L1.66.0F.W0 42 /r RVR V/V AVX512DQ Bitwise AND NOT 8 bits masks k1 and k2 and place result in k1.\r\n KANDNB k1, k2, k3\r\n VEX.L1.0F.W1 42 /r RVR V/V AVX512BW Bitwise AND NOT 64 bits masks k2 and k3 and place result in\r\n KANDNQ k1, k2, k3 k1.\r\n VEX.L1.66.0F.W1 42 /r RVR V/V AVX512BW Bitwise AND NOT 32 bits masks k2 and k3 and place result in\r\n KANDND k1, k2, k3 k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3\r\n RVR ModRM:reg (w) VEX.1vvv (r) ModRM:r/m (r, ModRM:[7:6] must be 11b)\r\n\r\nDescription\r\nPerforms a bitwise AND NOT between the vector mask k2 and the vector mask k3, and writes the result into vector\r\nmask k1.\r\n\r\nOperation\r\nKANDNW\r\nDEST[15:0] <- (BITWISE NOT SRC1[15:0]) BITWISE AND SRC2[15:0]\r\nDEST[MAX_KL-1:16] <- 0\r\n\r\nKANDNB\r\nDEST[7:0] <- (BITWISE NOT SRC1[7:0]) BITWISE AND SRC2[7:0]\r\nDEST[MAX_KL-1:8] <- 0\r\n\r\nKANDNQ\r\nDEST[63:0] <- (BITWISE NOT SRC1[63:0]) BITWISE AND SRC2[63:0]\r\nDEST[MAX_KL-1:64] <- 0\r\n\r\nKANDND\r\nDEST[31:0] <- (BITWISE NOT SRC1[31:0]) BITWISE AND SRC2[31:0]\r\nDEST[MAX_KL-1:32] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nKANDNW __mmask16 _mm512_kandn(__mmask16 a, __mmask16 b);\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type K20.\r\n\r\n\r\n\r\n\r\n",
"mnem": "KANDNW"
},
{
"description": "-R:KANDW",
"mnem": "KANDQ"
},
{
"description": "KANDW/KANDB/KANDQ/KANDD-Bitwise Logical AND Masks\r\n Opcode/ Op/En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n VEX.NDS.L1.0F.W0 41 /r RVR V/V AVX512F Bitwise AND 16 bits masks k2 and k3 and place result in k1.\r\n KANDW k1, k2, k3\r\n VEX.L1.66.0F.W0 41 /r RVR V/V AVX512DQ Bitwise AND 8 bits masks k2 and k3 and place result in k1.\r\n KANDB k1, k2, k3\r\n VEX.L1.0F.W1 41 /r RVR V/V AVX512BW Bitwise AND 64 bits masks k2 and k3 and place result in k1.\r\n KANDQ k1, k2, k3\r\n VEX.L1.66.0F.W1 41 /r RVR V/V AVX512BW Bitwise AND 32 bits masks k2 and k3 and place result in k1.\r\n KANDD k1, k2, k3\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3\r\n RVR ModRM:reg (w) VEX.1vvv (r) ModRM:r/m (r, ModRM:[7:6] must be 11b)\r\n\r\nDescription\r\nPerforms a bitwise AND between the vector mask k2 and the vector mask k3, and writes the result into vector mask\r\nk1.\r\n\r\nOperation\r\nKANDW\r\nDEST[15:0] <- SRC1[15:0] BITWISE AND SRC2[15:0]\r\nDEST[MAX_KL-1:16] <- 0\r\n\r\nKANDB\r\nDEST[7:0] <- SRC1[7:0] BITWISE AND SRC2[7:0]\r\nDEST[MAX_KL-1:8] <- 0\r\n\r\n\r\nKANDQ\r\nDEST[63:0] <- SRC1[63:0] BITWISE AND SRC2[63:0]\r\nDEST[MAX_KL-1:64] <- 0\r\n\r\nKANDD\r\nDEST[31:0] <- SRC1[31:0] BITWISE AND SRC2[31:0]\r\nDEST[MAX_KL-1:32] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nKANDW __mmask16 _mm512_kand(__mmask16 a, __mmask16 b);\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type K20.\r\n\r\n\r\n\r\n\r\n",
"mnem": "KANDW"
},
{
"description": "-R:KMOVW",
"mnem": "KMOVB"
},
{
"description": "-R:KMOVW",
"mnem": "KMOVD"
},
{
"description": "-R:KMOVW",
"mnem": "KMOVQ"
},
{
"description": "KMOVW/KMOVB/KMOVQ/KMOVD-Move from and to Mask Registers\r\n Opcode/ Op/En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n VEX.L0.0F.W0 90 /r RM V/V AVX512F Move 16 bits mask from k2/m16 and store the result in k1.\r\n KMOVW k1, k2/m16\r\n VEX.L0.66.0F.W0 90 /r RM V/V AVX512DQ Move 8 bits mask from k2/m8 and store the result in k1.\r\n KMOVB k1, k2/m8\r\n VEX.L0.0F.W1 90 /r RM V/V AVX512BW Move 64 bits mask from k2/m64 and store the result in k1.\r\n KMOVQ k1, k2/m64\r\n VEX.L0.66.0F.W1 90 /r RM V/V AVX512BW Move 32 bits mask from k2/m32 and store the result in k1.\r\n KMOVD k1, k2/m32\r\n VEX.L0.0F.W0 91 /r MR V/V AVX512F Move 16 bits mask from k1 and store the result in m16.\r\n KMOVW m16, k1\r\n VEX.L0.66.0F.W0 91 /r MR V/V AVX512DQ Move 8 bits mask from k1 and store the result in m8.\r\n KMOVB m8, k1\r\n VEX.L0.0F.W1 91 /r MR V/V AVX512BW Move 64 bits mask from k1 and store the result in m64.\r\n KMOVQ m64, k1\r\n VEX.L0.66.0F.W1 91 /r MR V/V AVX512BW Move 32 bits mask from k1 and store the result in m32.\r\n KMOVD m32, k1\r\n VEX.L0.0F.W0 92 /r RR V/V AVX512F Move 16 bits mask from r32 to k1.\r\n KMOVW k1, r32\r\n VEX.L0.66.0F.W0 92 /r RR V/V AVX512DQ Move 8 bits mask from r32 to k1.\r\n KMOVB k1, r32\r\n VEX.L0.F2.0F.W1 92 /r RR V/I AVX512BW Move 64 bits mask from r64 to k1.\r\n KMOVQ k1, r64\r\n VEX.L0.F2.0F.W0 92 /r RR V/V AVX512BW Move 32 bits mask from r32 to k1.\r\n KMOVD k1, r32\r\n VEX.L0.0F.W0 93 /r RR V/V AVX512F Move 16 bits mask from k1 to r32.\r\n KMOVW r32, k1\r\n VEX.L0.66.0F.W0 93 /r RR V/V AVX512DQ Move 8 bits mask from k1 to r32.\r\n KMOVB r32, k1\r\n VEX.L0.F2.0F.W1 93 /r RR V/I AVX512BW Move 64 bits mask from k1 to r64.\r\n KMOVQ r64, k1\r\n VEX.L0.F2.0F.W0 93 /r RR V/V AVX512BW Move 32 bits mask from k1 to r32.\r\n KMOVD r32, k1\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2\r\n RM ModRM:reg (w) ModRM:r/m (r)\r\n MR ModRM:r/m (w, ModRM:[7:6] must not be 11b) ModRM:reg (r)\r\n RR ModRM:reg (w) ModRM:r/m (r, ModRM:[7:6] must be 11b)\r\n\r\nDescription\r\nCopies values from the source operand (second operand) to the destination operand (first operand). The source\r\nand destination operands can be mask registers, memory location or general purpose. The instruction cannot be\r\nused to transfer data between general purpose registers and or memory locations.\r\nWhen moving to a mask register, the result is zero extended to MAX_KL size (i.e., 64 bits currently). When moving\r\nto a general-purpose register (GPR), the result is zero-extended to the size of the destination. In 32-bit mode, the\r\ndefault GPR destination's size is 32 bits. In 64-bit mode, the default GPR destination's size is 64 bits. Note that\r\nREX.W cannot be used to modify the size of the general-purpose destination.\r\n\r\n\r\n\r\n\r\nOperation\r\nKMOVW\r\nIF *destination is a memory location*\r\n DEST[15:0] <- SRC[15:0]\r\nIF *destination is a mask register or a GPR *\r\n DEST <- ZeroExtension(SRC[15:0])\r\n\r\nKMOVB\r\nIF *destination is a memory location*\r\n DEST[7:0] <- SRC[7:0]\r\nIF *destination is a mask register or a GPR *\r\n DEST <- ZeroExtension(SRC[7:0])\r\n\r\nKMOVQ\r\nIF *destination is a memory location or a GPR*\r\n DEST[63:0] <- SRC[63:0]\r\nIF *destination is a mask register*\r\n DEST <- ZeroExtension(SRC[63:0])\r\n\r\nKMOVD\r\nIF *destination is a memory location*\r\n DEST[31:0] <- SRC[31:0]\r\nIF *destination is a mask register or a GPR *\r\n DEST <- ZeroExtension(SRC[31:0])\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nKMOVW __mmask16 _mm512_kmov(__mmask16 a);\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nInstructions with RR operand encoding See Exceptions Type K20.\r\nInstructions with RM or MR operand encoding See Exceptions Type K21.\r\n\r\n\r\n\r\n\r\n",
"mnem": "KMOVW"
},
{
"description": "-R:KNOTW",
"mnem": "KNOTB"
},
{
"description": "-R:KNOTW",
"mnem": "KNOTD"
},
{
"description": "-R:KNOTW",
"mnem": "KNOTQ"
},
{
"description": "KNOTW/KNOTB/KNOTQ/KNOTD-NOT Mask Register\r\n Opcode/ Op/En 64/32 CPUID Description\r\n Instruction bit Mode Feature Flag\r\n Support\r\n VEX.L0.0F.W0 44 /r RR V/V AVX512F Bitwise NOT of 16 bits mask k2.\r\n KNOTW k1, k2\r\n VEX.L0.66.0F.W0 44 /r RR V/V AVX512DQ Bitwise NOT of 8 bits mask k2.\r\n KNOTB k1, k2\r\n VEX.L0.0F.W1 44 /r RR V/V AVX512BW Bitwise NOT of 64 bits mask k2.\r\n KNOTQ k1, k2\r\n VEX.L0.66.0F.W1 44 /r RR V/V AVX512BW Bitwise NOT of 32 bits mask k2.\r\n KNOTD k1, k2\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2\r\n RR ModRM:reg (w) ModRM:r/m (r, ModRM:[7:6] must be 11b)\r\n\r\nDescription\r\nPerforms a bitwise NOT of vector mask k2 and writes the result into vector mask k1.\r\n\r\nOperation\r\nKNOTW\r\nDEST[15:0] <- BITWISE NOT SRC[15:0]\r\nDEST[MAX_KL-1:16] <- 0\r\n\r\nKNOTB\r\nDEST[7:0] <- BITWISE NOT SRC[7:0]\r\nDEST[MAX_KL-1:8] <- 0\r\n\r\nKNOTQ\r\nDEST[63:0] <- BITWISE NOT SRC[63:0]\r\nDEST[MAX_KL-1:64] <- 0\r\n\r\nKNOTD\r\nDEST[31:0] <- BITWISE NOT SRC[31:0]\r\nDEST[MAX_KL-1:32] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nKNOTW __mmask16 _mm512_knot(__mmask16 a);\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type K20.\r\n\r\n\r\n\r\n\r\n",
"mnem": "KNOTW"
},
{
"description": "-R:KORW",
"mnem": "KORB"
},
{
"description": "-R:KORW",
"mnem": "KORD"
},
{
"description": "-R:KORW",
"mnem": "KORQ"
},
{
"description": "-R:KORTESTW",
"mnem": "KORTESTB"
},
{
"description": "-R:KORTESTW",
"mnem": "KORTESTD"
},
{
"description": "-R:KORTESTW",
"mnem": "KORTESTQ"
},
{
"description": "KORTESTW/KORTESTB/KORTESTQ/KORTESTD-OR Masks And Set Flags\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.L0.0F.W0 98 /r RR V/V AVX512F Bitwise OR 16 bits masks k1 and k2 and update ZF and CF accordingly.\r\n KORTESTW k1, k2\r\n VEX.L0.66.0F.W0 98 /r RR V/V AVX512DQ Bitwise OR 8 bits masks k1 and k2 and update ZF and CF accordingly.\r\n KORTESTB k1, k2\r\n VEX.L0.0F.W1 98 /r RR V/V AVX512BW Bitwise OR 64 bits masks k1 and k2 and update ZF and CF accordingly.\r\n KORTESTQ k1, k2\r\n VEX.L0.66.0F.W1 98 /r RR V/V AVX512BW Bitwise OR 32 bits masks k1 and k2 and update ZF and CF accordingly.\r\n KORTESTD k1, k2\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2\r\n RR ModRM:reg (w) ModRM:r/m (r, ModRM:[7:6] must be 11b)\r\n\r\nDescription\r\nPerforms a bitwise OR between the vector mask register k2, and the vector mask register k1, and sets CF and ZF\r\nbased on the operation result.\r\nZF flag is set if both sources are 0x0. CF is set if, after the OR operation is done, the operation result is all 1's.\r\n\r\nOperation\r\nKORTESTW\r\nTMP[15:0] <- DEST[15:0] BITWISE OR SRC[15:0]\r\nIF(TMP[15:0]=0)\r\n THEN ZF <- 1\r\n ELSE ZF <- 0\r\nFI;\r\nIF(TMP[15:0]=FFFFh)\r\n THEN CF <- 1\r\n ELSE CF <- 0\r\nFI;\r\n\r\nKORTESTB\r\nTMP[7:0] <- DEST[7:0] BITWISE OR SRC[7:0]\r\nIF(TMP[7:0]=0)\r\n THEN ZF <- 1\r\n ELSE ZF <- 0\r\nFI;\r\nIF(TMP[7:0]==FFh)\r\n THEN CF <- 1\r\n ELSE CF <- 0\r\n\r\nFI;\r\n\r\n\r\n\r\n\r\n\r\nKORTESTQ\r\nTMP[63:0] <- DEST[63:0] BITWISE OR SRC[63:0]\r\nIF(TMP[63:0]=0)\r\n THEN ZF <- 1\r\n ELSE ZF <- 0\r\nFI;\r\nIF(TMP[63:0]==FFFFFFFF_FFFFFFFFh)\r\n THEN CF <- 1\r\n ELSE CF <- 0\r\nFI;\r\n\r\nKORTESTD\r\nTMP[31:0] <- DEST[31:0] BITWISE OR SRC[31:0]\r\nIF(TMP[31:0]=0)\r\n THEN ZF <- 1\r\n ELSE ZF <- 0\r\nFI;\r\nIF(TMP[31:0]=FFFFFFFFh)\r\n THEN CF <- 1\r\n ELSE CF <- 0\r\nFI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nKORTESTW __mmask16 _mm512_kortest[cz](__mmask16 a, __mmask16 b);\r\n\r\nFlags Affected\r\nThe ZF flag is set if the result of OR-ing both sources is all 0s.\r\nThe CF flag is set if the result of OR-ing both sources is all 1s.\r\nThe OF, SF, AF, and PF flags are set to 0.\r\n\r\nOther Exceptions\r\nSee Exceptions Type K20.\r\n\r\n\r\n\r\n\r\n",
"mnem": "KORTESTW"
},
{
"description": "KORW/KORB/KORQ/KORD-Bitwise Logical OR Masks\r\n Opcode/ Op/En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n VEX.NDS.L1.0F.W0 45 /r RVR V/V AVX512F Bitwise OR 16 bits masks k2 and k3 and place result in k1.\r\n KORW k1, k2, k3\r\n VEX.L1.66.0F.W0 45 /r RVR V/V AVX512DQ Bitwise OR 8 bits masks k2 and k3 and place result in k1.\r\n KORB k1, k2, k3\r\n VEX.L1.0F.W1 45 /r RVR V/V AVX512BW Bitwise OR 64 bits masks k2 and k3 and place result in k1.\r\n KORQ k1, k2, k3\r\n VEX.L1.66.0F.W1 45 /r RVR V/V AVX512BW Bitwise OR 32 bits masks k2 and k3 and place result in k1.\r\n KORD k1, k2, k3\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3\r\n RVR ModRM:reg (w) VEX.1vvv (r) ModRM:r/m (r, ModRM:[7:6] must be 11b)\r\n\r\nDescription\r\nPerforms a bitwise OR between the vector mask k2 and the vector mask k3, and writes the result into vector mask\r\nk1 (three-operand form).\r\n\r\nOperation\r\nKORW\r\nDEST[15:0] <- SRC1[15:0] BITWISE OR SRC2[15:0]\r\nDEST[MAX_KL-1:16] <- 0\r\n\r\nKORB\r\nDEST[7:0] <- SRC1[7:0] BITWISE OR SRC2[7:0]\r\nDEST[MAX_KL-1:8] <- 0\r\n\r\nKORQ\r\nDEST[63:0] <- SRC1[63:0] BITWISE OR SRC2[63:0]\r\nDEST[MAX_KL-1:64] <- 0\r\n\r\nKORD\r\nDEST[31:0] <- SRC1[31:0] BITWISE OR SRC2[31:0]\r\nDEST[MAX_KL-1:32] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nKORW __mmask16 _mm512_kor(__mmask16 a, __mmask16 b);\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type K20.\r\n\r\n\r\n\r\n\r\n",
"mnem": "KORW"
},
{
"description": "-R:KSHIFTLW",
"mnem": "KSHIFTLB"
},
{
"description": "-R:KSHIFTLW",
"mnem": "KSHIFTLD"
},
{
"description": "-R:KSHIFTLW",
"mnem": "KSHIFTLQ"
},
{
"description": "KSHIFTLW/KSHIFTLB/KSHIFTLQ/KSHIFTLD-Shift Left Mask Registers\r\n Opcode/ Op/En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n VEX.L0.66.0F3A.W1 32 /r RRI V/V AVX512F Shift left 16 bits in k2 by immediate and write result in k1.\r\n KSHIFTLW k1, k2, imm8\r\n VEX.L0.66.0F3A.W0 32 /r RRI V/V AVX512DQ Shift left 8 bits in k2 by immediate and write result in k1.\r\n KSHIFTLB k1, k2, imm8\r\n VEX.L0.66.0F3A.W1 33 /r RRI V/V AVX512BW Shift left 64 bits in k2 by immediate and write result in k1.\r\n KSHIFTLQ k1, k2, imm8\r\n VEX.L0.66.0F3A.W0 33 /r RRI V/V AVX512BW Shift left 32 bits in k2 by immediate and write result in k1.\r\n KSHIFTLD k1, k2, imm8\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3\r\n RRI ModRM:reg (w) ModRM:r/m (r, ModRM:[7:6] must be 11b) Imm8\r\n\r\nDescription\r\nShifts 8/16/32/64 bits in the second operand (source operand) left by the count specified in immediate byte and\r\nplace the least significant 8/16/32/64 bits of the result in the destination operand. The higher bits of the destina-\r\ntion are zero-extended. The destination is set to zero if the count value is greater than 7 (for byte shift), 15 (for\r\nword shift), 31 (for doubleword shift) or 63 (for quadword shift).\r\n\r\nOperation\r\nKSHIFTLW\r\nCOUNT <- imm8[7:0]\r\nDEST[MAX_KL-1:0] <- 0\r\nIF COUNT <=15\r\n THEN DEST[15:0] <- SRC1[15:0] << COUNT;\r\nFI;\r\n\r\nKSHIFTLB\r\nCOUNT <- imm8[7:0]\r\nDEST[MAX_KL-1:0] <- 0\r\nIF COUNT <=7\r\n THEN DEST[7:0] <- SRC1[7:0] << COUNT;\r\nFI;\r\n\r\nKSHIFTLQ\r\nCOUNT <- imm8[7:0]\r\nDEST[MAX_KL-1:0] <- 0\r\nIF COUNT <=63\r\n THEN DEST[63:0] <- SRC1[63:0] << COUNT;\r\nFI;\r\n\r\n\r\n\r\n\r\n\r\nKSHIFTLD\r\nCOUNT <- imm8[7:0]\r\nDEST[MAX_KL-1:0] <- 0\r\nIF COUNT <=31\r\n THEN DEST[31:0] <- SRC1[31:0] << COUNT;\r\nFI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nCompiler auto generates KSHIFTLW when needed.\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type K20.\r\n\r\n\r\n\r\n\r\n",
"mnem": "KSHIFTLW"
},
{
"description": "-R:KSHIFTRW",
"mnem": "KSHIFTRB"
},
{
"description": "-R:KSHIFTRW",
"mnem": "KSHIFTRD"
},
{
"description": "-R:KSHIFTRW",
"mnem": "KSHIFTRQ"
},
{
"description": "KSHIFTRW/KSHIFTRB/KSHIFTRQ/KSHIFTRD-Shift Right Mask Registers\r\n Opcode/ Op/En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n VEX.L0.66.0F3A.W1 30 /r RRI V/V AVX512F Shift right 16 bits in k2 by immediate and write result in k1.\r\n KSHIFTRW k1, k2, imm8\r\n VEX.L0.66.0F3A.W0 30 /r RRI V/V AVX512DQ Shift right 8 bits in k2 by immediate and write result in k1.\r\n KSHIFTRB k1, k2, imm8\r\n VEX.L0.66.0F3A.W1 31 /r RRI V/V AVX512BW Shift right 64 bits in k2 by immediate and write result in k1.\r\n KSHIFTRQ k1, k2, imm8\r\n VEX.L0.66.0F3A.W0 31 /r RRI V/V AVX512BW Shift right 32 bits in k2 by immediate and write result in k1.\r\n KSHIFTRD k1, k2, imm8\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3\r\n RRI ModRM:reg (w) ModRM:r/m (r, ModRM:[7:6] must be 11b) Imm8\r\n\r\nDescription\r\nShifts 8/16/32/64 bits in the second operand (source operand) right by the count specified in immediate and place\r\nthe least significant 8/16/32/64 bits of the result in the destination operand. The higher bits of the destination are\r\nzero-extended. The destination is set to zero if the count value is greater than 7 (for byte shift), 15 (for word shift),\r\n31 (for doubleword shift) or 63 (for quadword shift).\r\n\r\nOperation\r\nKSHIFTRW\r\nCOUNT <- imm8[7:0]\r\nDEST[MAX_KL-1:0] <- 0\r\nIF COUNT <=15\r\n THEN DEST[15:0] <- SRC1[15:0] >> COUNT;\r\nFI;\r\n\r\nKSHIFTRB\r\nCOUNT <- imm8[7:0]\r\nDEST[MAX_KL-1:0] <- 0\r\nIF COUNT <=7\r\n THEN DEST[7:0] <- SRC1[7:0] >> COUNT;\r\nFI;\r\n\r\nKSHIFTRQ\r\nCOUNT <- imm8[7:0]\r\nDEST[MAX_KL-1:0] <- 0\r\nIF COUNT <=63\r\n THEN DEST[63:0] <- SRC1[63:0] >> COUNT;\r\nFI;\r\n\r\n\r\n\r\n\r\n\r\nKSHIFTRD\r\nCOUNT <- imm8[7:0]\r\nDEST[MAX_KL-1:0] <- 0\r\nIF COUNT <=31\r\n THEN DEST[31:0] <- SRC1[31:0] >> COUNT;\r\nFI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nCompiler auto generates KSHIFTRW when needed.\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type K20.\r\n\r\n\r\n\r\n\r\n",
"mnem": "KSHIFTRW"
},
{
"description": "-R:KTESTW",
"mnem": "KTESTB"
},
{
"description": "-R:KTESTW",
"mnem": "KTESTD"
},
{
"description": "-R:KTESTW",
"mnem": "KTESTQ"
},
{
"description": "KTESTW/KTESTB/KTESTQ/KTESTD-Packed Bit Test Masks and Set Flags\r\n Opcode/ Op 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.L0.0F.W0 99 /r RR V/V AVX512DQ Set ZF and CF depending on sign bit AND and ANDN of 16 bits mask\r\n KTESTW k1, k2 register sources.\r\n VEX.L0.66.0F.W0 99 /r RR V/V AVX512DQ Set ZF and CF depending on sign bit AND and ANDN of 8 bits mask\r\n KTESTB k1, k2 register sources.\r\n VEX.L0.0F.W1 99 /r RR V/V AVX512BW Set ZF and CF depending on sign bit AND and ANDN of 64 bits mask\r\n KTESTQ k1, k2 register sources.\r\n VEX.L0.66.0F.W1 99 /r RR V/V AVX512BW Set ZF and CF depending on sign bit AND and ANDN of 32 bits mask\r\n KTESTD k1, k2 register sources.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand2\r\n RR ModRM:reg (r) ModRM:r/m (r, ModRM:[7:6] must be 11b)\r\n\r\nDescription\r\nPerforms a bitwise comparison of the bits of the first source operand and corresponding bits in the second source\r\noperand. If the AND operation produces all zeros, the ZF is set else the ZF is clear. If the bitwise AND operation of\r\nthe inverted first source operand with the second source operand produces all zeros the CF is set else the CF is\r\nclear. Only the EFLAGS register is updated.\r\nNote: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\nOperation\r\nKTESTW\r\nTEMP[15:0] <- SRC2[15:0] AND SRC1[15:0]\r\nIF (TEMP[15:0] = = 0)\r\n THEN ZF <-1;\r\n ELSE ZF <- 0;\r\nFI;\r\nTEMP[15:0] <- SRC2[15:0] AND NOT SRC1[15:0]\r\nIF (TEMP[15:0] = = 0)\r\n THEN CF <-1;\r\n ELSE CF <- 0;\r\nFI;\r\nAF <- OF <- PF <- SF <- 0;\r\n\r\nKTESTB\r\nTEMP[7:0] <- SRC2[7:0] AND SRC1[7:0]\r\nIF (TEMP[7:0] = = 0)\r\n THEN ZF <-1;\r\n ELSE ZF <- 0;\r\nFI;\r\nTEMP[7:0] <- SRC2[7:0] AND NOT SRC1[7:0]\r\nIF (TEMP[7:0] = = 0)\r\n THEN CF <-1;\r\n ELSE CF <- 0;\r\nFI;\r\nAF <- OF <- PF <- SF <- 0;\r\n\r\n\r\n\r\n\r\n\r\nKTESTQ\r\nTEMP[63:0] <- SRC2[63:0] AND SRC1[63:0]\r\nIF (TEMP[63:0] = = 0)\r\n THEN ZF <-1;\r\n ELSE ZF <- 0;\r\nFI;\r\nTEMP[63:0] <- SRC2[63:0] AND NOT SRC1[63:0]\r\nIF (TEMP[63:0] = = 0)\r\n THEN CF <-1;\r\n ELSE CF <- 0;\r\nFI;\r\nAF <- OF <- PF <- SF <- 0;\r\n\r\nKTESTD\r\nTEMP[31:0] <- SRC2[31:0] AND SRC1[31:0]\r\nIF (TEMP[31:0] = = 0)\r\n THEN ZF <-1;\r\n ELSE ZF <- 0;\r\nFI;\r\nTEMP[31:0] <- SRC2[31:0] AND NOT SRC1[31:0]\r\nIF (TEMP[31:0] = = 0)\r\n THEN CF <-1;\r\n ELSE CF <- 0;\r\nFI;\r\nAF <- OF <- PF <- SF <- 0;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n\r\n\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type K20.\r\n\r\n\r\n\r\n\r\n",
"mnem": "KTESTW"
},
{
"description": "KUNPCKBW/KUNPCKWD/KUNPCKDQ-Unpack for Mask Registers\r\n Opcode/ Op/En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n VEX.NDS.L1.66.0F.W0 4B /r RVR V/V AVX512F Unpack and interleave 8 bits masks in k2 and k3 and write\r\n KUNPCKBW k1, k2, k3 word result in k1.\r\n VEX.NDS.L1.0F.W0 4B /r RVR V/V AVX512BW Unpack and interleave 16 bits in k2 and k3 and write double-\r\n KUNPCKWD k1, k2, k3 word result in k1.\r\n VEX.NDS.L1.0F.W1 4B /r RVR V/V AVX512BW Unpack and interleave 32 bits masks in k2 and k3 and write\r\n KUNPCKDQ k1, k2, k3 quadword result in k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3\r\n RVR ModRM:reg (w) VEX.1vvv (r) ModRM:r/m (r, ModRM:[7:6] must be 11b)\r\n\r\nDescription\r\nUnpacks the lower 8/16/32 bits of the second and third operands (source operands) into the low part of the first\r\noperand (destination operand), starting from the low bytes. The result is zero-extended in the destination.\r\n\r\nOperation\r\nKUNPCKBW\r\nDEST[7:0] <- SRC2[7:0]\r\nDEST[15:8] <- SRC1[7:0]\r\nDEST[MAX_KL-1:16] <- 0\r\n\r\nKUNPCKWD\r\nDEST[15:0] <- SRC2[15:0]\r\nDEST[31:16] <- SRC1[15:0]\r\nDEST[MAX_KL-1:32] <- 0\r\n\r\nKUNPCKDQ\r\nDEST[31:0] <- SRC2[31:0]\r\nDEST[63:32] <- SRC1[31:0]\r\nDEST[MAX_KL-1:64] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nKUNPCKBW __mmask16 _mm512_kunpackb(__mmask16 a, __mmask16 b);\r\nKUNPCKDQ __mmask64 _mm512_kunpackd(__mmask64 a, __mmask64 b);\r\nKUNPCKWD __mmask32 _mm512_kunpackw(__mmask32 a, __mmask32 b);\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type K20.\r\n\r\n\r\n\r\n\r\n",
"mnem": "KUNPCKBW"
},
{
"description": "-R:KUNPCKBW",
"mnem": "KUNPCKDQ"
},
{
"description": "-R:KUNPCKBW",
"mnem": "KUNPCKWD"
},
{
"description": "-R:KXNORW",
"mnem": "KXNORB"
},
{
"description": "-R:KXNORW",
"mnem": "KXNORD"
},
{
"description": "-R:KXNORW",
"mnem": "KXNORQ"
},
{
"description": "KXNORW/KXNORB/KXNORQ/KXNORD-Bitwise Logical XNOR Masks\r\n Opcode/ Op/En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n VEX.NDS.L1.0F.W0 46 /r RVR V/V AVX512F Bitwise XNOR 16 bits masks k2 and k3 and place result in k1.\r\n KXNORW k1, k2, k3\r\n VEX.L1.66.0F.W0 46 /r RVR V/V AVX512DQ Bitwise XNOR 8 bits masks k2 and k3 and place result in k1.\r\n KXNORB k1, k2, k3\r\n VEX.L1.0F.W1 46 /r RVR V/V AVX512BW Bitwise XNOR 64 bits masks k2 and k3 and place result in k1.\r\n KXNORQ k1, k2, k3\r\n VEX.L1.66.0F.W1 46 /r RVR V/V AVX512BW Bitwise XNOR 32 bits masks k2 and k3 and place result in k1.\r\n KXNORD k1, k2, k3\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3\r\n RVR ModRM:reg (w) VEX.1vvv (r) ModRM:r/m (r, ModRM:[7:6] must be 11b)\r\n\r\nDescription\r\nPerforms a bitwise XNOR between the vector mask k2 and the vector mask k3, and writes the result into vector\r\nmask k1 (three-operand form).\r\n\r\nOperation\r\nKXNORW\r\nDEST[15:0] <- NOT (SRC1[15:0] BITWISE XOR SRC2[15:0])\r\nDEST[MAX_KL-1:16] <- 0\r\n\r\nKXNORB\r\nDEST[7:0] <- NOT (SRC1[7:0] BITWISE XOR SRC2[7:0])\r\nDEST[MAX_KL-1:8] <- 0\r\n\r\nKXNORQ\r\nDEST[63:0] <- NOT (SRC1[63:0] BITWISE XOR SRC2[63:0])\r\nDEST[MAX_KL-1:64] <- 0\r\n\r\nKXNORD\r\nDEST[31:0] <- NOT (SRC1[31:0] BITWISE XOR SRC2[31:0])\r\nDEST[MAX_KL-1:32] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nKXNORW __mmask16 _mm512_kxnor(__mmask16 a, __mmask16 b);\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type K20.\r\n\r\n\r\n\r\n\r\n",
"mnem": "KXNORW"
},
{
"description": "-R:KXORW",
"mnem": "KXORB"
},
{
"description": "-R:KXORW",
"mnem": "KXORD"
},
{
"description": "-R:KXORW",
"mnem": "KXORQ"
},
{
"description": "KXORW/KXORB/KXORQ/KXORD-Bitwise Logical XOR Masks\r\n Opcode/ Op/En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n VEX.NDS.L1.0F.W0 47 /r RVR V/V AVX512F Bitwise XOR 16 bits masks k2 and k3 and place result in k1.\r\n KXORW k1, k2, k3\r\n VEX.L1.66.0F.W0 47 /r RVR V/V AVX512DQ Bitwise XOR 8 bits masks k2 and k3 and place result in k1.\r\n KXORB k1, k2, k3\r\n VEX.L1.0F.W1 47 /r RVR V/V AVX512BW Bitwise XOR 64 bits masks k2 and k3 and place result in k1.\r\n KXORQ k1, k2, k3\r\n VEX.L1.66.0F.W1 47 /r RVR V/V AVX512BW Bitwise XOR 32 bits masks k2 and k3 and place result in k1.\r\n KXORD k1, k2, k3\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3\r\n RVR ModRM:reg (w) VEX.1vvv (r) ModRM:r/m (r, ModRM:[7:6] must be 11b)\r\n\r\nDescription\r\nPerforms a bitwise XOR between the vector mask k2 and the vector mask k3, and writes the result into vector mask\r\nk1 (three-operand form).\r\n\r\nOperation\r\nKXORW\r\nDEST[15:0] <- SRC1[15:0] BITWISE XOR SRC2[15:0]\r\nDEST[MAX_KL-1:16] <- 0\r\n\r\nKXORB\r\nDEST[7:0] <- SRC1[7:0] BITWISE XOR SRC2[7:0]\r\nDEST[MAX_KL-1:8] <- 0\r\n\r\nKXORQ\r\nDEST[63:0] <- SRC1[63:0] BITWISE XOR SRC2[63:0]\r\nDEST[MAX_KL-1:64] <- 0\r\n\r\nKXORD\r\nDEST[31:0] <- SRC1[31:0] BITWISE XOR SRC2[31:0]\r\nDEST[MAX_KL-1:32] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nKXORW __mmask16 _mm512_kxor(__mmask16 a, __mmask16 b);\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type K20.\r\n\r\n\r\n\r\n\r\n",
"mnem": "KXORW"
},
{
"description": "LAHF-Load Status Flags into AH Register\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 9F LAHF NP Invalid* Valid Load: AH <- EFLAGS(SF:ZF:0:AF:0:PF:1:CF).\r\n NOTES:\r\n *Valid in specific steppings. See Description section.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nThis instruction executes as described above in compatibility mode and legacy mode. It is valid in 64-bit mode only\r\nif CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1.\r\n\r\nOperation\r\nIF 64-Bit Mode\r\n THEN\r\n IF CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1;\r\n THEN AH <- RFLAGS(SF:ZF:0:AF:0:PF:1:CF);\r\n ELSE #UD;\r\n FI;\r\n ELSE\r\n AH <- EFLAGS(SF:ZF:0:AF:0:PF:1:CF);\r\nFI;\r\n\r\nFlags Affected\r\nNone. The state of the flags in the EFLAGS register is not affected.\r\n\r\nProtected Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD If CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 0.\r\n If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "LAHF"
},
{
"description": "LAR-Load Access Rights Byte\r\nOpcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n0F 02 /r LAR r16, r16/m16 RM Valid Valid r16 <- access rights referenced by r16/m16\r\n0F 02 /r LAR reg, r32/m161 RM Valid Valid reg <- access rights referenced by r32/m16\r\nNOTES:\r\n1. For all loads (regardless of source or destination sizing) only bits 16-0 are used. Other bits are ignored.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nLoads the access rights from the segment descriptor specified by the second operand (source operand) into the\r\nfirst operand (destination operand) and sets the ZF flag in the flag register. The source operand (which can be a\r\nregister or a memory location) contains the segment selector for the segment descriptor being accessed. If the\r\nsource operand is a memory address, only 16 bits of data are accessed. The destination operand is a general-\r\npurpose register.\r\nThe processor performs access checks as part of the loading process. Once loaded in the destination register, soft-\r\nware can perform additional checks on the access rights information.\r\nThe access rights for a segment descriptor include fields located in the second doubleword (bytes 4-7) of the\r\nsegment descriptor. The following fields are loaded by the LAR instruction:\r\n. Bits 7:0 are returned as 0\r\n. Bits 11:8 return the segment type.\r\n. Bit 12 returns the S flag.\r\n. Bits 14:13 return the DPL.\r\n. Bit 15 returns the P flag.\r\n. The following fields are returned only if the operand size is greater than 16 bits:\r\n - Bits 19:16 are undefined.\r\n - Bit 20 returns the software-available bit in the descriptor.\r\n - Bit 21 returns the L flag.\r\n - Bit 22 returns the D/B flag.\r\n - Bit 23 returns the G flag.\r\n - Bits 31:24 are returned as 0.\r\nThis instruction performs the following checks before it loads the access rights in the destination register:\r\n. Checks that the segment selector is not NULL.\r\n. Checks that the segment selector points to a descriptor that is within the limits of the GDT or LDT being\r\n accessed\r\n. Checks that the descriptor type is valid for this instruction. All code and data segment descriptors are valid for\r\n (can be accessed with) the LAR instruction. The valid system segment and gate descriptor types are given in\r\n Table 3-52.\r\n. If the segment is not a conforming code segment, it checks that the specified segment descriptor is visible at\r\n the CPL (that is, if the CPL and the RPL of the segment selector are less than or equal to the DPL of the segment\r\n selector).\r\nIf the segment descriptor cannot be accessed or is an invalid type for the instruction, the ZF flag is cleared and no\r\naccess rights are loaded in the destination operand.\r\n\r\n\r\n\r\nThe LAR instruction can only be executed in protected mode and IA-32e mode.\r\n Table 3-52. Segment and Gate Types\r\n Type Protected Mode IA-32e Mode\r\n Name Valid Name Valid\r\n 0 Reserved No Reserved No\r\n 1 Available 16-bit TSS Yes Reserved No\r\n 2 LDT Yes LDT No\r\n 3 Busy 16-bit TSS Yes Reserved No\r\n 4 16-bit call gate Yes Reserved No\r\n 5 16-bit/32-bit task gate Yes Reserved No\r\n 6 16-bit interrupt gate No Reserved No\r\n 7 16-bit trap gate No Reserved No\r\n 8 Reserved No Reserved No\r\n 9 Available 32-bit TSS Yes Available 64-bit TSS Yes\r\n A Reserved No Reserved No\r\n B Busy 32-bit TSS Yes Busy 64-bit TSS Yes\r\n C 32-bit call gate Yes 64-bit call gate Yes\r\n D Reserved No Reserved No\r\n E 32-bit interrupt gate No 64-bit interrupt gate No\r\n F 32-bit trap gate No 64-bit trap gate No\r\n\r\nOperation\r\nIF Offset(SRC) > descriptor table limit\r\n THEN\r\n ZF <- 0;\r\n ELSE\r\n SegmentDescriptor <- descriptor referenced by SRC;\r\n IF SegmentDescriptor(Type) != conforming code segment\r\n and (CPL > DPL) or (RPL > DPL)\r\n or SegmentDescriptor(Type) is not valid for instruction\r\n THEN\r\n ZF <- 0;\r\n ELSE\r\n DEST <- access rights from SegmentDescriptor as given in Description section;\r\n ZF <- 1;\r\n FI;\r\nFI;\r\n\r\nFlags Affected\r\nThe ZF flag is set to 1 if the access rights are loaded successfully; otherwise, it is cleared to 0.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and the memory operand effective address is unaligned while\r\n the current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD The LAR instruction is not recognized in real-address mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD The LAR instruction cannot be executed in virtual-8086 mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If the memory operand effective address referencing the SS segment is in a non-canonical\r\n form.\r\n#GP(0) If the memory operand effective address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and the memory operand effective address is unaligned while\r\n the current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "LAR"
},
{
"description": "LDDQU-Load Unaligned Integer 128 Bits\r\n Opcode/ Op/ 64/32-bit CPUID Description\r\n Instruction En Mode Feature\r\n Flag\r\n F2 0F F0 /r RM V/V SSE3 Load unaligned data from mem and return\r\n LDDQU xmm1, mem double quadword in xmm1.\r\n\r\n VEX.128.F2.0F.WIG F0 /r RM V/V AVX Load unaligned packed integer values from\r\n VLDDQU xmm1, m128 mem to xmm1.\r\n\r\n VEX.256.F2.0F.WIG F0 /r RM V/V AVX Load unaligned packed integer values from\r\n VLDDQU ymm1, m256 mem to ymm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nThe instruction is functionally similar to (V)MOVDQU ymm/xmm, m256/m128 for loading from memory. That is:\r\n32/16 bytes of data starting at an address specified by the source memory operand (second operand) are fetched\r\nfrom memory and placed in a destination register (first operand). The source operand need not be aligned on a\r\n32/16-byte boundary. Up to 64/32 bytes may be loaded from memory; this is implementation dependent.\r\nThis instruction may improve performance relative to (V)MOVDQU if the source operand crosses a cache line\r\nboundary. In situations that require the data loaded by (V)LDDQU be modified and stored to the same location, use\r\n(V)MOVDQU or (V)MOVDQA instead of (V)LDDQU. To move a double quadword to or from memory locations that\r\nare known to be aligned on 16-byte boundaries, use the (V)MOVDQA instruction.\r\n\r\nImplementation Notes\r\n. If the source is aligned to a 32/16-byte boundary, based on the implementation, the 32/16 bytes may be\r\n loaded more than once. For that reason, the usage of (V)LDDQU should be avoided when using uncached or\r\n write-combining (WC) memory regions. For uncached or WC memory regions, keep using (V)MOVDQU.\r\n. This instruction is a replacement for (V)MOVDQU (load) in situations where cache line splits significantly affect\r\n performance. It should not be used in situations where store-load forwarding is performance critical. If\r\n performance of store-load forwarding is critical to the application, use (V)MOVDQA store-load pairs when data\r\n is 256/128-bit aligned or (V)MOVDQU store-load pairs when data is 256/128-bit unaligned.\r\n. If the memory address is not aligned on 32/16-byte boundary, some implementations may load up to 64/32\r\n bytes and return 32/16 bytes in the destination. Some processor implementations may issue multiple loads to\r\n access the appropriate 32/16 bytes. Developers of multi-threaded or multi-processor software should be aware\r\n that on these processors the loads will be performed in a non-atomic way.\r\n. If alignment checking is enabled (CR0.AM = 1, RFLAGS.AC = 1, and CPL = 3), an alignment-check exception\r\n (#AC) may or may not be generated (depending on processor implementation) when the memory address is\r\n not aligned on an 8-byte boundary.\r\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).\r\nNote: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\nOperation\r\nLDDQU (128-bit Legacy SSE version)\r\nDEST[127:0] <- SRC[127:0]\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\n\r\n\r\n\r\n\r\nVLDDQU (VEX.128 encoded version)\r\nDEST[127:0] <- SRC[127:0]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVLDDQU (VEX.256 encoded version)\r\nDEST[255:0] <- SRC[255:0]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nLDDQU: __m128i _mm_lddqu_si128 (__m128i * p);\r\n\r\nVLDDQU: __m256i _mm256_lddqu_si256 (__m256i * p);\r\n\r\nNumeric Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4;\r\nNote treatment of #AC varies.\r\n\r\n\r\n\r\n\r\n",
"mnem": "LDDQU"
},
{
"description": "LDMXCSR-Load MXCSR Register\r\n Opcode/ Op/ 64/32-bit CPUID Description\r\n Instruction En Mode Feature\r\n Flag\r\n 0F AE /2 M V/V SSE Load MXCSR register from m32.\r\n LDMXCSR m32\r\n VEX.LZ.0F.WIG AE /2 M V/V AVX Load MXCSR register from m32.\r\n VLDMXCSR m32\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (r) NA NA NA\r\n\r\nDescription\r\nLoads the source operand into the MXCSR control/status register. The source operand is a 32-bit memory location.\r\nSee \"MXCSR Control and Status Register\" in Chapter 10, of the Intel 64 and IA-32 Architectures Software Devel-\r\noper's Manual, Volume 1, for a description of the MXCSR register and its contents.\r\nThe LDMXCSR instruction is typically used in conjunction with the (V)STMXCSR instruction, which stores the\r\ncontents of the MXCSR register in memory.\r\nThe default MXCSR value at reset is 1F80H.\r\nIf a (V)LDMXCSR instruction clears a SIMD floating-point exception mask bit and sets the corresponding exception\r\nflag bit, a SIMD floating-point exception will not be immediately generated. The exception will be generated only\r\nupon the execution of the next instruction that meets both conditions below:\r\n. the instruction must operate on an XMM or YMM register operand,\r\n. the instruction causes that particular SIMD floating-point exception to be reported.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\nIf VLDMXCSR is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause an\r\n#UD exception.\r\nNote: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\nOperation\r\nMXCSR <- m32;\r\n\r\nC/C++ Compiler Intrinsic Equivalent\r\n_mm_setcsr(unsigned int i)\r\n\r\nNumeric Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 5; additionally\r\n#GP For an attempt to set reserved bits in MXCSR.\r\n#UD If VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "LDMXCSR"
},
{
"description": "LDS/LES/LFS/LGS/LSS-Load Far Pointer\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n C5 /r LDS r16,m16:16 RM Invalid Valid Load DS:r16 with far pointer from memory.\r\n C5 /r LDS r32,m16:32 RM Invalid Valid Load DS:r32 with far pointer from memory.\r\n 0F B2 /r LSS r16,m16:16 RM Valid Valid Load SS:r16 with far pointer from memory.\r\n 0F B2 /r LSS r32,m16:32 RM Valid Valid Load SS:r32 with far pointer from memory.\r\n REX + 0F B2 /r LSS r64,m16:64 RM Valid N.E. Load SS:r64 with far pointer from memory.\r\n C4 /r LES r16,m16:16 RM Invalid Valid Load ES:r16 with far pointer from memory.\r\n C4 /r LES r32,m16:32 RM Invalid Valid Load ES:r32 with far pointer from memory.\r\n 0F B4 /r LFS r16,m16:16 RM Valid Valid Load FS:r16 with far pointer from memory.\r\n 0F B4 /r LFS r32,m16:32 RM Valid Valid Load FS:r32 with far pointer from memory.\r\n REX + 0F B4 /r LFS r64,m16:64 RM Valid N.E. Load FS:r64 with far pointer from memory.\r\n 0F B5 /r LGS r16,m16:16 RM Valid Valid Load GS:r16 with far pointer from memory.\r\n 0F B5 /r LGS r32,m16:32 RM Valid Valid Load GS:r32 with far pointer from memory.\r\n REX + 0F B5 /r LGS r64,m16:64 RM Valid N.E. Load GS:r64 with far pointer from memory.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nLoads a far pointer (segment selector and offset) from the second operand (source operand) into a segment\r\nregister and the first operand (destination operand). The source operand specifies a 48-bit or a 32-bit pointer in\r\nmemory depending on the current setting of the operand-size attribute (32 bits or 16 bits, respectively). The\r\ninstruction opcode and the destination operand specify a segment register/general-purpose register pair. The 16-\r\nbit segment selector from the source operand is loaded into the segment register specified with the opcode (DS,\r\nSS, ES, FS, or GS). The 32-bit or 16-bit offset is loaded into the register specified with the destination operand.\r\nIf one of these instructions is executed in protected mode, additional information from the segment descriptor\r\npointed to by the segment selector in the source operand is loaded in the hidden part of the selected segment\r\nregister.\r\nAlso in protected mode, a NULL selector (values 0000 through 0003) can be loaded into DS, ES, FS, or GS registers\r\nwithout causing a protection exception. (Any subsequent reference to a segment whose corresponding segment\r\nregister is loaded with a NULL selector, causes a general-protection exception (#GP) and no memory reference to\r\nthe segment occurs.)\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.W promotes\r\noperation to specify a source operand referencing an 80-bit pointer (16-bit selector, 64-bit offset) in memory.\r\nUsing a REX prefix in the form of REX.R permits access to additional registers (R8-R15). See the summary chart at\r\nthe beginning of this section for encoding data and limits.\r\n\r\nOperation\r\n64-BIT_MODE\r\n IF SS is loaded\r\n THEN\r\n IF SegmentSelector = NULL and ( (RPL = 3) or\r\n (RPL != 3 and RPL != CPL) )\r\n THEN #GP(0);\r\n ELSE IF descriptor is in non-canonical space\r\n\r\n\r\n\r\n THEN #GP(0); FI;\r\n ELSE IF Segment selector index is not within descriptor table limits\r\n or segment selector RPL != CPL\r\n or access rights indicate nonwritable data segment\r\n or DPL != CPL\r\n THEN #GP(selector); FI;\r\n ELSE IF Segment marked not present\r\n THEN #SS(selector); FI;\r\n FI;\r\n SS <- SegmentSelector(SRC);\r\n SS <- SegmentDescriptor([SRC]);\r\n ELSE IF attempt to load DS, or ES\r\n THEN #UD;\r\n ELSE IF FS, or GS is loaded with non-NULL segment selector\r\n THEN IF Segment selector index is not within descriptor table limits\r\n or access rights indicate segment neither data nor readable code segment\r\n or segment is data or nonconforming-code segment\r\n and ( RPL > DPL or CPL > DPL)\r\n THEN #GP(selector); FI;\r\n ELSE IF Segment marked not present\r\n THEN #NP(selector); FI;\r\n FI;\r\n SegmentRegister <- SegmentSelector(SRC) ;\r\n SegmentRegister <- SegmentDescriptor([SRC]);\r\n FI;\r\n ELSE IF FS, or GS is loaded with a NULL selector:\r\n THEN\r\n SegmentRegister <- NULLSelector;\r\n SegmentRegister(DescriptorValidBit) <- 0; FI; (* Hidden flag;\r\n not accessible by software *)\r\n FI;\r\n DEST <- Offset(SRC);\r\n\r\nPREOTECTED MODE OR COMPATIBILITY MODE;\r\n IF SS is loaded\r\n THEN\r\n IF SegementSelector = NULL\r\n THEN #GP(0);\r\n ELSE IF Segment selector index is not within descriptor table limits\r\n or segment selector RPL != CPL\r\n or access rights indicate nonwritable data segment\r\n or DPL != CPL\r\n THEN #GP(selector); FI;\r\n ELSE IF Segment marked not present\r\n THEN #SS(selector); FI;\r\n FI;\r\n SS <- SegmentSelector(SRC);\r\n SS <- SegmentDescriptor([SRC]);\r\n ELSE IF DS, ES, FS, or GS is loaded with non-NULL segment selector\r\n THEN IF Segment selector index is not within descriptor table limits\r\n or access rights indicate segment neither data nor readable code segment\r\n or segment is data or nonconforming-code segment\r\n and (RPL > DPL or CPL > DPL)\r\n THEN #GP(selector); FI;\r\n\r\n\r\n\r\n\r\n ELSE IF Segment marked not present\r\n THEN #NP(selector); FI;\r\n FI;\r\n SegmentRegister <- SegmentSelector(SRC) AND RPL;\r\n SegmentRegister <- SegmentDescriptor([SRC]);\r\n FI;\r\n ELSE IF DS, ES, FS, or GS is loaded with a NULL selector:\r\n THEN\r\n SegmentRegister <- NULLSelector;\r\n SegmentRegister(DescriptorValidBit) <- 0; FI; (* Hidden flag;\r\n not accessible by software *)\r\n FI;\r\n DEST <- Offset(SRC);\r\n\r\nReal-Address or Virtual-8086 Mode\r\n SegmentRegister <- SegmentSelector(SRC); FI;\r\n DEST <- Offset(SRC);\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#UD If source operand is not a memory location.\r\n If the LOCK prefix is used.\r\n#GP(0) If a NULL selector is loaded into the SS register.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n#GP(selector) If the SS register is being loaded and any of the following is true: the segment selector index\r\n is not within the descriptor table limits, the segment selector RPL is not equal to CPL, the\r\n segment is a non-writable data segment, or DPL is not equal to CPL.\r\n If the DS, ES, FS, or GS register is being loaded with a non-NULL segment selector and any of\r\n the following is true: the segment selector index is not within descriptor table limits, the\r\n segment is neither a data nor a readable code segment, or the segment is a data or noncon-\r\n forming-code segment and both RPL and CPL are greater than DPL.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#SS(selector) If the SS register is being loaded and the segment is marked not present.\r\n#NP(selector) If DS, ES, FS, or GS register is being loaded with a non-NULL segment selector and the\r\n segment is marked not present.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If source operand is not a memory location.\r\n If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD If source operand is not a memory location.\r\n If the LOCK prefix is used.\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the memory address is in a non-canonical form.\r\n If a NULL selector is attempted to be loaded into the SS register in compatibility mode.\r\n If a NULL selector is attempted to be loaded into the SS register in CPL3 and 64-bit mode.\r\n If a NULL selector is attempted to be loaded into the SS register in non-CPL3 and 64-bit mode\r\n where its RPL is not equal to CPL.\r\n#GP(Selector) If the FS, or GS register is being loaded with a non-NULL segment selector and any of the\r\n following is true: the segment selector index is not within descriptor table limits, the memory\r\n address of the descriptor is non-canonical, the segment is neither a data nor a readable code\r\n segment, or the segment is a data or nonconforming-code segment and both RPL and CPL are\r\n greater than DPL.\r\n If the SS register is being loaded and any of the following is true: the segment selector index\r\n is not within the descriptor table limits, the memory address of the descriptor is non-canonical,\r\n the segment selector RPL is not equal to CPL, the segment is a nonwritable data segment, or\r\n DPL is not equal to CPL.\r\n#SS(0) If a memory operand effective address is non-canonical\r\n#SS(Selector) If the SS register is being loaded and the segment is marked not present.\r\n#NP(selector) If FS, or GS register is being loaded with a non-NULL segment selector and the segment is\r\n marked not present.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If source operand is not a memory location.\r\n If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "LDS"
},
{
"description": "LEA-Load Effective Address\r\nOpcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n8D /r LEA r16,m RM Valid Valid Store effective address for m in register r16.\r\n8D /r LEA r32,m RM Valid Valid Store effective address for m in register r32.\r\nREX.W + 8D /r LEA r64,m RM Valid N.E. Store effective address for m in register r64.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nComputes the effective address of the second operand (the source operand) and stores it in the first operand\r\n(destination operand). The source operand is a memory address (offset part) specified with one of the processors\r\naddressing modes; the destination operand is a general-purpose register. The address-size and operand-size attri-\r\nbutes affect the action performed by this instruction, as shown in the following table. The operand-size attribute of\r\nthe instruction is determined by the chosen register; the address-size attribute is determined by the attribute of\r\nthe code segment.\r\n Table 3-53. Non-64-bit Mode LEA Operation with Address and Operand Size Attributes\r\n Operand Size Address Size Action Performed\r\n 16 16 16-bit effective address is calculated and stored in requested 16-bit register destination.\r\n 16 32 32-bit effective address is calculated. The lower 16 bits of the address are stored in the\r\n requested 16-bit register destination.\r\n 32 16 16-bit effective address is calculated. The 16-bit address is zero-extended and stored in the\r\n requested 32-bit register destination.\r\n 32 32 32-bit effective address is calculated and stored in the requested 32-bit register destination.\r\n\r\nDifferent assemblers may use different algorithms based on the size attribute and symbolic reference of the source\r\noperand.\r\nIn 64-bit mode, the instruction's destination operand is governed by operand size attribute, the default operand\r\nsize is 32 bits. Address calculation is governed by address size attribute, the default address size is 64-bits. In 64-\r\nbit mode, address size of 16 bits is not encodable. See Table 3-54.\r\n Table 3-54. 64-bit Mode LEA Operation with Address and Operand Size Attributes\r\n Operand Size Address Size Action Performed\r\n 16 32 32-bit effective address is calculated (using 67H prefix). The lower 16 bits of the address are\r\n stored in the requested 16-bit register destination (using 66H prefix).\r\n 16 64 64-bit effective address is calculated (default address size). The lower 16 bits of the address\r\n are stored in the requested 16-bit register destination (using 66H prefix).\r\n 32 32 32-bit effective address is calculated (using 67H prefix) and stored in the requested 32-bit\r\n register destination.\r\n 32 64 64-bit effective address is calculated (default address size) and the lower 32 bits of the\r\n address are stored in the requested 32-bit register destination.\r\n 64 32 32-bit effective address is calculated (using 67H prefix), zero-extended to 64-bits, and stored\r\n in the requested 64-bit register destination (using REX.W).\r\n 64 64 64-bit effective address is calculated (default address size) and all 64-bits of the address are\r\n stored in the requested 64-bit register destination (using REX.W).\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIF OperandSize = 16 and AddressSize = 16\r\n THEN\r\n DEST <- EffectiveAddress(SRC); (* 16-bit address *)\r\n ELSE IF OperandSize = 16 and AddressSize = 32\r\n THEN\r\n temp <- EffectiveAddress(SRC); (* 32-bit address *)\r\n DEST <- temp[0:15]; (* 16-bit address *)\r\n FI;\r\n ELSE IF OperandSize = 32 and AddressSize = 16\r\n THEN\r\n temp <- EffectiveAddress(SRC); (* 16-bit address *)\r\n DEST <- ZeroExtend(temp); (* 32-bit address *)\r\n FI;\r\n ELSE IF OperandSize = 32 and AddressSize = 32\r\n THEN\r\n DEST <- EffectiveAddress(SRC); (* 32-bit address *)\r\n FI;\r\n ELSE IF OperandSize = 16 and AddressSize = 64\r\n THEN\r\n temp <- EffectiveAddress(SRC); (* 64-bit address *)\r\n DEST <- temp[0:15]; (* 16-bit address *)\r\n FI;\r\n ELSE IF OperandSize = 32 and AddressSize = 64\r\n THEN\r\n temp <- EffectiveAddress(SRC); (* 64-bit address *)\r\n DEST <- temp[0:31]; (* 16-bit address *)\r\n FI;\r\n ELSE IF OperandSize = 64 and AddressSize = 64\r\n THEN\r\n DEST <- EffectiveAddress(SRC); (* 64-bit address *)\r\n FI;\r\nFI;\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#UD If source operand is not a memory location.\r\n If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n",
"mnem": "LEA"
},
{
"description": "LEAVE-High Level Procedure Exit\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n C9 LEAVE NP Valid Valid Set SP to BP, then pop BP.\r\n C9 LEAVE NP N.E. Valid Set ESP to EBP, then pop EBP.\r\n C9 LEAVE NP Valid N.E. Set RSP to RBP, then pop RBP.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nReleases the stack frame set up by an earlier ENTER instruction. The LEAVE instruction copies the frame pointer (in\r\nthe EBP register) into the stack pointer register (ESP), which releases the stack space allocated to the stack frame.\r\nThe old frame pointer (the frame pointer for the calling procedure that was saved by the ENTER instruction) is then\r\npopped from the stack into the EBP register, restoring the calling procedure's stack frame.\r\nA RET instruction is commonly executed following a LEAVE instruction to return program control to the calling\r\nprocedure.\r\nSee \"Procedure Calls for Block-Structured Languages\" in Chapter 7 of the Intel 64 and IA-32 Architectures Soft-\r\nware Developer's Manual, Volume 1, for detailed information on the use of the ENTER and LEAVE instructions.\r\nIn 64-bit mode, the instruction's default operation size is 64 bits; 32-bit operation cannot be encoded. See the\r\nsummary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nIF StackAddressSize = 32\r\n THEN\r\n ESP <- EBP;\r\n ELSE IF StackAddressSize = 64\r\n THEN RSP <- RBP; FI;\r\n ELSE IF StackAddressSize = 16\r\n THEN SP <- BP; FI;\r\nFI;\r\n\r\nIF OperandSize = 32\r\n THEN EBP <- Pop();\r\n ELSE IF OperandSize = 64\r\n THEN RBP <- Pop(); FI;\r\n ELSE IF OperandSize = 16\r\n THEN BP <- Pop(); FI;\r\nFI;\r\n\r\nFlags Affected\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#SS(0) If the EBP register points to a location that is not within the limits of the current stack\r\n segment.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If the EBP register points to a location outside of the effective address space from 0 to FFFFH.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If the EBP register points to a location outside of the effective address space from 0 to FFFFH.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If the stack address is in a non-canonical form.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "LEAVE"
},
{
"description": "-R:LDS",
"mnem": "LES"
},
{
"description": "LFENCE-Load Fence\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F AE E8 LFENCE NP Valid Valid Serializes load operations.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nPerforms a serializing operation on all load-from-memory instructions that were issued prior the LFENCE instruc-\r\ntion. Specifically, LFENCE does not execute until all prior instructions have completed locally, and no later instruc-\r\ntion begins execution until LFENCE completes. In particular, an instruction that loads from memory and that\r\nprecedes an LFENCE receives data from memory prior to completion of the LFENCE. (An LFENCE that follows an\r\ninstruction that stores to memory might complete before the data being stored have become globally visible.)\r\nInstructions following an LFENCE may be fetched from memory before the LFENCE, but they will not execute until\r\nthe LFENCE completes.\r\nWeakly ordered memory types can be used to achieve higher processor performance through such techniques as\r\nout-of-order issue and speculative reads. The degree to which a consumer of data recognizes or knows that the\r\ndata is weakly ordered varies among applications and may be unknown to the producer of this data. The LFENCE\r\ninstruction provides a performance-efficient way of ensuring load ordering between routines that produce weakly-\r\nordered results and routines that consume that data.\r\nProcessors are free to fetch and cache data speculatively from regions of system memory that use the WB, WC,\r\nand WT memory types. This speculative fetching can occur at any time and is not tied to instruction execution.\r\nThus, it is not ordered with respect to executions of the LFENCE instruction; data can be brought into the caches\r\nspeculatively just before, during, or after the execution of an LFENCE instruction.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\nSpecification of the instruction's opcode above indicates a ModR/M byte of E8. For this instruction, the processor\r\nignores the r/m field of the ModR/M byte. Thus, LFENCE is encoded by any opcode of the form 0F AE Ex, where x is\r\nin the range 8-F.\r\n\r\nOperation\r\nWait_On_Following_Instructions_Until(preceding_instructions_complete);\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nvoid _mm_lfence(void)\r\n\r\nExceptions (All Modes of Operation)\r\n#UD If CPUID.01H:EDX.SSE2[bit 26] = 0.\r\n If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "LFENCE"
},
{
"description": "-R:LDS",
"mnem": "LFS"
},
{
"description": "LGDT/LIDT-Load Global/Interrupt Descriptor Table Register\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F 01 /2 LGDT m16&32 M N.E. Valid Load m into GDTR.\r\n 0F 01 /3 LIDT m16&32 M N.E. Valid Load m into IDTR.\r\n 0F 01 /2 LGDT m16&64 M Valid N.E. Load m into GDTR.\r\n 0F 01 /3 LIDT m16&64 M Valid N.E. Load m into IDTR.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (r) NA NA NA\r\n\r\nDescription\r\nLoads the values in the source operand into the global descriptor table register (GDTR) or the interrupt descriptor\r\ntable register (IDTR). The source operand specifies a 6-byte memory location that contains the base address (a\r\nlinear address) and the limit (size of table in bytes) of the global descriptor table (GDT) or the interrupt descriptor\r\ntable (IDT). If operand-size attribute is 32 bits, a 16-bit limit (lower 2 bytes of the 6-byte data operand) and a 32-\r\nbit base address (upper 4 bytes of the data operand) are loaded into the register. If the operand-size attribute\r\nis 16 bits, a 16-bit limit (lower 2 bytes) and a 24-bit base address (third, fourth, and fifth byte) are loaded. Here,\r\nthe high-order byte of the operand is not used and the high-order byte of the base address in the GDTR or IDTR is\r\nfilled with zeros.\r\nThe LGDT and LIDT instructions are used only in operating-system software; they are not used in application\r\nprograms. They are the only instructions that directly load a linear address (that is, not a segment-relative\r\naddress) and a limit in protected mode. They are commonly executed in real-address mode to allow processor\r\ninitialization prior to switching to protected mode.\r\nIn 64-bit mode, the instruction's operand size is fixed at 8+2 bytes (an 8-byte base and a 2-byte limit). See the\r\nsummary chart at the beginning of this section for encoding data and limits.\r\nSee \"SGDT-Store Global Descriptor Table Register\" in Chapter 4, Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2B, for information on storing the contents of the GDTR and IDTR.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIF Instruction is LIDT\r\n THEN\r\n IF OperandSize = 16\r\n THEN\r\n IDTR(Limit) <- SRC[0:15];\r\n IDTR(Base) <- SRC[16:47] AND 00FFFFFFH;\r\n ELSE IF 32-bit Operand Size\r\n THEN\r\n IDTR(Limit) <- SRC[0:15];\r\n IDTR(Base) <- SRC[16:47];\r\n FI;\r\n ELSE IF 64-bit Operand Size (* In 64-Bit Mode *)\r\n THEN\r\n IDTR(Limit) <- SRC[0:15];\r\n IDTR(Base) <- SRC[16:79];\r\n FI;\r\n FI;\r\n ELSE (* Instruction is LGDT *)\r\n IF OperandSize = 16\r\n THEN\r\n GDTR(Limit) <- SRC[0:15];\r\n GDTR(Base) <- SRC[16:47] AND 00FFFFFFH;\r\n ELSE IF 32-bit Operand Size\r\n THEN\r\n GDTR(Limit) <- SRC[0:15];\r\n GDTR(Base) <- SRC[16:47];\r\n FI;\r\n ELSE IF 64-bit Operand Size (* In 64-Bit Mode *)\r\n THEN\r\n GDTR(Limit) <- SRC[0:15];\r\n GDTR(Base) <- SRC[16:79];\r\n FI;\r\n FI;\r\nFI;\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#UD If source operand is not a memory location.\r\n If the LOCK prefix is used.\r\n#GP(0) If the current privilege level is not 0.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#UD If source operand is not a memory location.\r\n If the LOCK prefix is used.\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD If source operand is not a memory location.\r\n If the LOCK prefix is used.\r\n#GP(0) The LGDT and LIDT instructions are not recognized in virtual-8086 mode.\r\n#GP If the current privilege level is not 0.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the current privilege level is not 0.\r\n If the memory address is in a non-canonical form.\r\n#UD If source operand is not a memory location.\r\n If the LOCK prefix is used.\r\n#PF(fault-code) If a page fault occurs.\r\n\r\n\r\n\r\n\r\n",
"mnem": "LGDT"
},
{
"description": "-R:LDS",
"mnem": "LGS"
},
{
"description": "-R:LGDT",
"mnem": "LIDT"
},
{
"description": "LLDT-Load Local Descriptor Table Register\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F 00 /2 LLDT r/m16 M Valid Valid Load segment selector r/m16 into LDTR.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (r) NA NA NA\r\n\r\nDescription\r\nLoads the source operand into the segment selector field of the local descriptor table register (LDTR). The source\r\noperand (a general-purpose register or a memory location) contains a segment selector that points to a local\r\ndescriptor table (LDT). After the segment selector is loaded in the LDTR, the processor uses the segment selector\r\nto locate the segment descriptor for the LDT in the global descriptor table (GDT). It then loads the segment limit\r\nand base address for the LDT from the segment descriptor into the LDTR. The segment registers DS, ES, SS, FS,\r\nGS, and CS are not affected by this instruction, nor is the LDTR field in the task state segment (TSS) for the current\r\ntask.\r\nIf bits 2-15 of the source operand are 0, LDTR is marked invalid and the LLDT instruction completes silently.\r\nHowever, all subsequent references to descriptors in the LDT (except by the LAR, VERR, VERW or LSL instructions)\r\ncause a general protection exception (#GP).\r\nThe operand-size attribute has no effect on this instruction.\r\nThe LLDT instruction is provided for use in operating-system software; it should not be used in application\r\nprograms. This instruction can only be executed in protected mode or 64-bit mode.\r\nIn 64-bit mode, the operand size is fixed at 16 bits.\r\n\r\nOperation\r\nIF SRC(Offset) > descriptor table limit\r\n THEN #GP(segment selector); FI;\r\n\r\nIF segment selector is valid\r\n\r\n Read segment descriptor;\r\n\r\n IF SegmentDescriptor(Type) != LDT\r\n THEN #GP(segment selector); FI;\r\n IF segment descriptor is not present\r\n THEN #NP(segment selector); FI;\r\n\r\n LDTR(SegmentSelector) <- SRC;\r\n LDTR(SegmentDescriptor) <- GDTSegmentDescriptor;\r\nELSE LDTR <- INVALID\r\nFI;\r\n\r\nFlags Affected\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the current privilege level is not 0.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#GP(selector) If the selector operand does not point into the Global Descriptor Table or if the entry in the GDT\r\n is not a Local Descriptor Table.\r\n Segment selector is beyond GDT limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#NP(selector) If the LDT descriptor is not present.\r\n#PF(fault-code) If a page fault occurs.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD The LLDT instruction is not recognized in real-address mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD The LLDT instruction is not recognized in virtual-8086 mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the current privilege level is not 0.\r\n If the memory address is in a non-canonical form.\r\n#GP(selector) If the selector operand does not point into the Global Descriptor Table or if the entry in the GDT\r\n is not a Local Descriptor Table.\r\n Segment selector is beyond GDT limit.\r\n#NP(selector) If the LDT descriptor is not present.\r\n#PF(fault-code) If a page fault occurs.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "LLDT"
},
{
"description": "LMSW-Load Machine Status Word\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F 01 /6 LMSW r/m16 M Valid Valid Loads r/m16 in machine status word of CR0.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (r) NA NA NA\r\n\r\nDescription\r\nLoads the source operand into the machine status word, bits 0 through 15 of register CR0. The source operand can\r\nbe a 16-bit general-purpose register or a memory location. Only the low-order 4 bits of the source operand (which\r\ncontains the PE, MP, EM, and TS flags) are loaded into CR0. The PG, CD, NW, AM, WP, NE, and ET flags of CR0 are\r\nnot affected. The operand-size attribute has no effect on this instruction.\r\nIf the PE flag of the source operand (bit 0) is set to 1, the instruction causes the processor to switch to protected\r\nmode. While in protected mode, the LMSW instruction cannot be used to clear the PE flag and force a switch back\r\nto real-address mode.\r\nThe LMSW instruction is provided for use in operating-system software; it should not be used in application\r\nprograms. In protected or virtual-8086 mode, it can only be executed at CPL 0.\r\nThis instruction is provided for compatibility with the Intel 286 processor; programs and procedures intended to\r\nrun on IA-32 and Intel 64 processors beginning with Intel386 processors should use the MOV (control registers)\r\ninstruction to load the whole CR0 register. The MOV CR0 instruction can be used to set and clear the PE flag in CR0,\r\nallowing a procedure or program to switch between protected and real-address modes.\r\nThis instruction is a serializing instruction.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode. Note that the operand size is fixed\r\nat 16 bits.\r\nSee \"Changes to Instruction Behavior in VMX Non-Root Operation\" in Chapter 25 of the Intel 64 and IA-32 Archi-\r\ntectures Software Developer's Manual, Volume 3C, for more information about the behavior of this instruction in\r\nVMX non-root operation.\r\n\r\nOperation\r\nCR0[0:3] <- SRC[0:3];\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the current privilege level is not 0.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) The LMSW instruction is not recognized in real-address mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the current privilege level is not 0.\r\n If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "LMSW"
},
{
"description": "LOCK-Assert LOCK# Signal Prefix\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n F0 LOCK NP Valid Valid Asserts LOCK# signal for duration of the\r\n accompanying instruction.\r\n NOTES:\r\n * See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nCauses the processor's LOCK# signal to be asserted during execution of the accompanying instruction (turns the\r\ninstruction into an atomic instruction). In a multiprocessor environment, the LOCK# signal ensures that the\r\nprocessor has exclusive use of any shared memory while the signal is asserted.\r\nIn most IA-32 and all Intel 64 processors, locking may occur without the LOCK# signal being asserted. See the \"IA-\r\n32 Architecture Compatibility\" section below for more details.\r\nThe LOCK prefix can be prepended only to the following instructions and only to those forms of the instructions\r\nwhere the destination operand is a memory operand: ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG, CMPXCH8B,\r\nCMPXCHG16B, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD, and XCHG. If the LOCK prefix is used with one of\r\nthese instructions and the source operand is a memory operand, an undefined opcode exception (#UD) may be\r\ngenerated. An undefined opcode exception will also be generated if the LOCK prefix is used with any instruction not\r\nin the above list. The XCHG instruction always asserts the LOCK# signal regardless of the presence or absence of\r\nthe LOCK prefix.\r\nThe LOCK prefix is typically used with the BTS instruction to perform a read-modify-write operation on a memory\r\nlocation in shared memory environment.\r\nThe integrity of the LOCK prefix is not affected by the alignment of the memory field. Memory locking is observed\r\nfor arbitrarily misaligned fields.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nIA-32 Architecture Compatibility\r\nBeginning with the P6 family processors, when the LOCK prefix is prefixed to an instruction and the memory area\r\nbeing accessed is cached internally in the processor, the LOCK# signal is generally not asserted. Instead, only the\r\nprocessor's cache is locked. Here, the processor's cache coherency mechanism ensures that the operation is\r\ncarried out atomically with regards to memory. See \"Effects of a Locked Operation on Internal Processor Caches\"\r\nin Chapter 8 of Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, the for more informa-\r\ntion on locking of caches.\r\n\r\nOperation\r\nAssertLOCK#(DurationOfAccompaningInstruction);\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#UD If the LOCK prefix is used with an instruction not listed: ADD, ADC, AND, BTC, BTR, BTS,\r\n CMPXCHG, CMPXCH8B, CMPXCHG16B, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD,\r\n XCHG.\r\n Other exceptions can be generated by the instruction when the LOCK prefix is applied.\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "LOCK"
},
{
"description": "LODS/LODSB/LODSW/LODSD/LODSQ-Load String\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n AC LODS m8 NP Valid Valid For legacy mode, Load byte at address DS:(E)SI\r\n into AL. For 64-bit mode load byte at address\r\n (R)SI into AL.\r\n AD LODS m16 NP Valid Valid For legacy mode, Load word at address\r\n DS:(E)SI into AX. For 64-bit mode load word at\r\n address (R)SI into AX.\r\n AD LODS m32 NP Valid Valid For legacy mode, Load dword at address\r\n DS:(E)SI into EAX. For 64-bit mode load dword\r\n at address (R)SI into EAX.\r\n REX.W + AD LODS m64 NP Valid N.E. Load qword at address (R)SI into RAX.\r\n AC LODSB NP Valid Valid For legacy mode, Load byte at address DS:(E)SI\r\n into AL. For 64-bit mode load byte at address\r\n (R)SI into AL.\r\n AD LODSW NP Valid Valid For legacy mode, Load word at address\r\n DS:(E)SI into AX. For 64-bit mode load word at\r\n address (R)SI into AX.\r\n AD LODSD NP Valid Valid For legacy mode, Load dword at address\r\n DS:(E)SI into EAX. For 64-bit mode load dword\r\n at address (R)SI into EAX.\r\n REX.W + AD LODSQ NP Valid N.E. Load qword at address (R)SI into RAX.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nLoads a byte, word, or doubleword from the source operand into the AL, AX, or EAX register, respectively. The\r\nsource operand is a memory location, the address of which is read from the DS:ESI or the DS:SI registers\r\n(depending on the address-size attribute of the instruction, 32 or 16, respectively). The DS segment may be over-\r\nridden with a segment override prefix.\r\nAt the assembly-code level, two forms of this instruction are allowed: the \"explicit-operands\" form and the \"no-\r\noperands\" form. The explicit-operands form (specified with the LODS mnemonic) allows the source operand to be\r\nspecified explicitly. Here, the source operand should be a symbol that indicates the size and location of the source\r\nvalue. The destination operand is then automatically selected to match the size of the source operand (the AL\r\nregister for byte operands, AX for word operands, and EAX for doubleword operands). This explicit-operands form\r\nis provided to allow documentation; however, note that the documentation provided by this form can be\r\nmisleading. That is, the source operand symbol must specify the correct type (size) of the operand (byte, word, or\r\ndoubleword), but it does not have to specify the correct location. The location is always specified by the DS:(E)SI\r\nregisters, which must be loaded correctly before the load string instruction is executed.\r\nThe no-operands form provides \"short forms\" of the byte, word, and doubleword versions of the LODS instructions.\r\nHere also DS:(E)SI is assumed to be the source operand and the AL, AX, or EAX register is assumed to be the desti-\r\nnation operand. The size of the source and destination operands is selected with the mnemonic: LODSB (byte\r\nloaded into register AL), LODSW (word loaded into AX), or LODSD (doubleword loaded into EAX).\r\nAfter the byte, word, or doubleword is transferred from the memory location into the AL, AX, or EAX register, the\r\n(E)SI register is incremented or decremented automatically according to the setting of the DF flag in the EFLAGS\r\nregister. (If the DF flag is 0, the (E)SI register is incremented; if the DF flag is 1, the ESI register is decremented.)\r\nThe (E)SI register is incremented or decremented by 1 for byte operations, by 2 for word operations, or by 4 for\r\ndoubleword operations.\r\n\r\n\r\n\r\nIn 64-bit mode, use of the REX.W prefix promotes operation to 64 bits. LODS/LODSQ load the quadword at address\r\n(R)SI into RAX. The (R)SI register is then incremented or decremented automatically according to the setting of\r\nthe DF flag in the EFLAGS register.\r\nThe LODS, LODSB, LODSW, and LODSD instructions can be preceded by the REP prefix for block loads of ECX bytes,\r\nwords, or doublewords. More often, however, these instructions are used within a LOOP construct because further\r\nprocessing of the data moved into the register is usually necessary before the next transfer can be made. See\r\n\"REP/REPE/REPZ /REPNE/REPNZ-Repeat String Operation Prefix\" in Chapter 4 of the Intel 64 and IA-32 Archi-\r\ntectures Software Developer's Manual, Volume 2B, for a description of the REP prefix.\r\n\r\nOperation\r\nIF AL <- SRC; (* Byte load *)\r\n THEN AL <- SRC; (* Byte load *)\r\n IF DF = 0\r\n THEN (E)SI <- (E)SI + 1;\r\n ELSE (E)SI <- (E)SI - 1;\r\n FI;\r\nELSE IF AX <- SRC; (* Word load *)\r\n THEN IF DF = 0\r\n THEN (E)SI <- (E)SI + 2;\r\n ELSE (E)SI <- (E)SI - 2;\r\n IF;\r\n FI;\r\nELSE IF EAX <- SRC; (* Doubleword load *)\r\n THEN IF DF = 0\r\n THEN (E)SI <- (E)SI + 4;\r\n ELSE (E)SI <- (E)SI - 4;\r\n FI;\r\n FI;\r\nELSE IF RAX <- SRC; (* Quadword load *)\r\n THEN IF DF = 0\r\n THEN (R)SI <- (R)SI + 8;\r\n ELSE (R)SI <- (R)SI - 8;\r\n FI;\r\n FI;\r\nFI;\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "LODS"
},
{
"description": "-R:LODS",
"mnem": "LODSB"
},
{
"description": "-R:LODS",
"mnem": "LODSD"
},
{
"description": "-R:LODS",
"mnem": "LODSQ"
},
{
"description": "-R:LODS",
"mnem": "LODSW"
},
{
"description": "LOOP/LOOPcc-Loop According to ECX Counter\r\nOpcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\nE2 cb LOOP rel8 D Valid Valid Decrement count; jump short if count != 0.\r\nE1 cb LOOPE rel8 D Valid Valid Decrement count; jump short if count != 0 and\r\n ZF = 1.\r\nE0 cb LOOPNE rel8 D Valid Valid Decrement count; jump short if count != 0 and\r\n ZF = 0.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n D Offset NA NA NA\r\n\r\nDescription\r\nPerforms a loop operation using the RCX, ECX or CX register as a counter (depending on whether address size is 64\r\nbits, 32 bits, or 16 bits). Note that the LOOP instruction ignores REX.W; but 64-bit address size can be over-ridden\r\nusing a 67H prefix.\r\nEach time the LOOP instruction is executed, the count register is decremented, then checked for 0. If the count is\r\n0, the loop is terminated and program execution continues with the instruction following the LOOP instruction. If\r\nthe count is not zero, a near jump is performed to the destination (target) operand, which is presumably the\r\ninstruction at the beginning of the loop.\r\nThe target instruction is specified with a relative offset (a signed offset relative to the current value of the instruc-\r\ntion pointer in the IP/EIP/RIP register). This offset is generally specified as a label in assembly code, but at the\r\nmachine code level, it is encoded as a signed, 8-bit immediate value, which is added to the instruction pointer.\r\nOffsets of -128 to +127 are allowed with this instruction.\r\nSome forms of the loop instruction (LOOPcc) also accept the ZF flag as a condition for terminating the loop before\r\nthe count reaches zero. With these forms of the instruction, a condition code (cc) is associated with each instruction\r\nto indicate the condition being tested for. Here, the LOOPcc instruction itself does not affect the state of the ZF flag;\r\nthe ZF flag is changed by other instructions in the loop.\r\n\r\nOperation\r\nIF (AddressSize = 32)\r\n THEN Count is ECX;\r\nELSE IF (AddressSize = 64)\r\n Count is RCX;\r\nELSE Count is CX;\r\nFI;\r\n\r\nCount <- Count - 1;\r\n\r\nIF Instruction is not LOOP\r\n THEN\r\n IF (Instruction <- LOOPE) or (Instruction <- LOOPZ)\r\n THEN IF (ZF = 1) and (Count != 0)\r\n THEN BranchCond <- 1;\r\n ELSE BranchCond <- 0;\r\n FI;\r\n ELSE (Instruction = LOOPNE) or (Instruction = LOOPNZ)\r\n IF (ZF = 0 ) and (Count != 0)\r\n THEN BranchCond <- 1;\r\n ELSE BranchCond <- 0;\r\n\r\n\r\n\r\n\r\n FI;\r\n FI;\r\n ELSE (* Instruction = LOOP *)\r\n IF (Count != 0)\r\n THEN BranchCond <- 1;\r\n ELSE BranchCond <- 0;\r\n FI;\r\nFI;\r\n\r\nIF BranchCond = 1\r\n THEN\r\n IF OperandSize = 32\r\n THEN EIP <- EIP + SignExtend(DEST);\r\n ELSE IF OperandSize = 64\r\n THEN RIP <- RIP + SignExtend(DEST);\r\n FI;\r\n ELSE IF OperandSize = 16\r\n THEN EIP <- EIP AND 0000FFFFH;\r\n FI;\r\n FI;\r\n IF OperandSize = (32 or 64)\r\n THEN IF (R/E)IP < CS.Base or (R/E)IP > CS.Limit\r\n #GP; FI;\r\n FI;\r\n FI;\r\n ELSE\r\n Terminate loop and continue program execution at (R/E)IP;\r\nFI;\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the offset being jumped to is beyond the limits of the CS segment.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If the offset being jumped to is beyond the limits of the CS segment or is outside of the effec-\r\n tive address space from 0 to FFFFH. This condition can occur if a 32-bit address size override\r\n prefix is used.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in real address mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the offset being jumped to is in a non-canonical form.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "LOOP"
},
{
"description": "-R:LOOP",
"mnem": "LOOPcc"
},
{
"description": "LSL-Load Segment Limit\r\nOpcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n0F 03 /r LSL r16, r16/m16 RM Valid Valid Load: r16 <- segment limit, selector r16/m16.\r\n0F 03 /r LSL r32, r32/m16* RM Valid Valid Load: r32 <- segment limit, selector r32/m16.\r\nREX.W + 0F 03 /r LSL r64, r32/m16* RM Valid Valid Load: r64 <- segment limit, selector r32/m16\r\nNOTES:\r\n* For all loads (regardless of destination sizing), only bits 16-0 are used. Other bits are ignored.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nLoads the unscrambled segment limit from the segment descriptor specified with the second operand (source\r\noperand) into the first operand (destination operand) and sets the ZF flag in the EFLAGS register. The source\r\noperand (which can be a register or a memory location) contains the segment selector for the segment descriptor\r\nbeing accessed. The destination operand is a general-purpose register.\r\nThe processor performs access checks as part of the loading process. Once loaded in the destination register, soft-\r\nware can compare the segment limit with the offset of a pointer.\r\nThe segment limit is a 20-bit value contained in bytes 0 and 1 and in the first 4 bits of byte 6 of the segment\r\ndescriptor. If the descriptor has a byte granular segment limit (the granularity flag is set to 0), the destination\r\noperand is loaded with a byte granular value (byte limit). If the descriptor has a page granular segment limit (the\r\ngranularity flag is set to 1), the LSL instruction will translate the page granular limit (page limit) into a byte limit\r\nbefore loading it into the destination operand. The translation is performed by shifting the 20-bit \"raw\" limit left 12\r\nbits and filling the low-order 12 bits with 1s.\r\nWhen the operand size is 32 bits, the 32-bit byte limit is stored in the destination operand. When the operand size\r\nis 16 bits, a valid 32-bit limit is computed; however, the upper 16 bits are truncated and only the low-order 16 bits\r\nare loaded into the destination operand.\r\nThis instruction performs the following checks before it loads the segment limit into the destination register:\r\n. Checks that the segment selector is not NULL.\r\n. Checks that the segment selector points to a descriptor that is within the limits of the GDT or LDT being\r\n accessed\r\n. Checks that the descriptor type is valid for this instruction. All code and data segment descriptors are valid for\r\n (can be accessed with) the LSL instruction. The valid special segment and gate descriptor types are given in the\r\n following table.\r\n. If the segment is not a conforming code segment, the instruction checks that the specified segment descriptor\r\n is visible at the CPL (that is, if the CPL and the RPL of the segment selector are less than or equal to the DPL of\r\n the segment selector).\r\nIf the segment descriptor cannot be accessed or is an invalid type for the instruction, the ZF flag is cleared and no\r\nvalue is loaded in the destination operand.\r\n\r\n\r\n\r\n\r\n\r\n Table 3-55. Segment and Gate Descriptor Types\r\n Type Protected Mode IA-32e Mode\r\n Name Valid Name Valid\r\n 0 Reserved No Upper 8 byte of a 16-Byte Yes\r\n descriptor\r\n 1 Available 16-bit TSS Yes Reserved No\r\n 2 LDT Yes LDT Yes\r\n 3 Busy 16-bit TSS Yes Reserved No\r\n 4 16-bit call gate No Reserved No\r\n 5 16-bit/32-bit task gate No Reserved No\r\n 6 16-bit interrupt gate No Reserved No\r\n 7 16-bit trap gate No Reserved No\r\n 8 Reserved No Reserved No\r\n 9 Available 32-bit TSS Yes 64-bit TSS Yes\r\n A Reserved No Reserved No\r\n B Busy 32-bit TSS Yes Busy 64-bit TSS Yes\r\n C 32-bit call gate No 64-bit call gate No\r\n D Reserved No Reserved No\r\n E 32-bit interrupt gate No 64-bit interrupt gate No\r\n F 32-bit trap gate No 64-bit trap gate No\r\n\r\nOperation\r\nIF SRC(Offset) > descriptor table limit\r\n THEN ZF <- 0; FI;\r\n\r\nRead segment descriptor;\r\n\r\nIF SegmentDescriptor(Type) != conforming code segment\r\nand (CPL > DPL) OR (RPL > DPL)\r\nor Segment type is not valid for instruction\r\n THEN\r\n ZF <- 0;\r\n ELSE\r\n temp <- SegmentLimit([SRC]);\r\n IF (G <- 1)\r\n THEN temp <- ShiftLeft(12, temp) OR 00000FFFH;\r\n ELSE IF OperandSize = 32\r\n THEN DEST <- temp; FI;\r\n ELSE IF OperandSize = 64 (* REX.W used *)\r\n THEN DEST (* Zero-extended *) <- temp; FI;\r\n ELSE (* OperandSize = 16 *)\r\n DEST <- temp AND FFFFH;\r\n FI;\r\nFI;\r\n\r\nFlags Affected\r\nThe ZF flag is set to 1 if the segment limit is loaded successfully; otherwise, it is set to 0.\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and the memory operand effective address is unaligned while\r\n the current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD The LSL instruction cannot be executed in real-address mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD The LSL instruction cannot be executed in virtual-8086 mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If the memory operand effective address referencing the SS segment is in a non-canonical\r\n form.\r\n#GP(0) If the memory operand effective address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and the memory operand effective address is unaligned while\r\n the current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "LSL"
},
{
"description": "-R:LDS",
"mnem": "LSS"
},
{
"description": "LTR-Load Task Register\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F 00 /3 LTR r/m16 M Valid Valid Load r/m16 into task register.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (r) NA NA NA\r\n\r\nDescription\r\nLoads the source operand into the segment selector field of the task register. The source operand (a general-\r\npurpose register or a memory location) contains a segment selector that points to a task state segment (TSS).\r\nAfter the segment selector is loaded in the task register, the processor uses the segment selector to locate the\r\nsegment descriptor for the TSS in the global descriptor table (GDT). It then loads the segment limit and base\r\naddress for the TSS from the segment descriptor into the task register. The task pointed to by the task register is\r\nmarked busy, but a switch to the task does not occur.\r\nThe LTR instruction is provided for use in operating-system software; it should not be used in application programs.\r\nIt can only be executed in protected mode when the CPL is 0. It is commonly used in initialization code to establish\r\nthe first task to be executed.\r\nThe operand-size attribute has no effect on this instruction.\r\nIn 64-bit mode, the operand size is still fixed at 16 bits. The instruction references a 16-byte descriptor to load the\r\n64-bit base.\r\n\r\nOperation\r\nIF SRC is a NULL selector\r\n THEN #GP(0);\r\n\r\nIF SRC(Offset) > descriptor table limit OR IF SRC(type) != global\r\n THEN #GP(segment selector); FI;\r\n\r\nRead segment descriptor;\r\n\r\nIF segment descriptor is not for an available TSS\r\n THEN #GP(segment selector); FI;\r\nIF segment descriptor is not present\r\n THEN #NP(segment selector); FI;\r\n\r\nTSSsegmentDescriptor(busy) <- 1;\r\n(* Locked read-modify-write operation on the entire descriptor when setting busy flag *)\r\n\r\nTaskRegister(SegmentSelector) <- SRC;\r\nTaskRegister(SegmentDescriptor) <- TSSSegmentDescriptor;\r\n\r\nFlags Affected\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the current privilege level is not 0.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the source operand contains a NULL segment selector.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n#GP(selector) If the source selector points to a segment that is not a TSS or to one for a task that is already\r\n busy.\r\n If the selector points to LDT or is beyond the GDT limit.\r\n#NP(selector) If the TSS is marked not present.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD The LTR instruction is not recognized in real-address mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD The LTR instruction is not recognized in virtual-8086 mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the current privilege level is not 0.\r\n If the memory address is in a non-canonical form.\r\n If the source operand contains a NULL segment selector.\r\n#GP(selector) If the source selector points to a segment that is not a TSS or to one for a task that is already\r\n busy.\r\n If the selector points to LDT or is beyond the GDT limit.\r\n If the descriptor type of the upper 8-byte of the 16-byte descriptor is non-zero.\r\n#NP(selector) If the TSS is marked not present.\r\n#PF(fault-code) If a page fault occurs.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "LTR"
},
{
"description": "LZCNT- Count the Number of Leading Zero Bits\r\n Opcode/Instruction Op/ 64/32 CPUID Description\r\n En -bit Feature\r\n Mode Flag\r\n F3 0F BD /r RM V/V LZCNT Count the number of leading zero bits in r/m16, return result in r16.\r\n LZCNT r16, r/m16\r\n\r\n F3 0F BD /r RM V/V LZCNT Count the number of leading zero bits in r/m32, return result in r32.\r\n LZCNT r32, r/m32\r\n\r\n F3 REX.W 0F BD /r RM V/N.E. LZCNT Count the number of leading zero bits in r/m64, return result in r64.\r\n LZCNT r64, r/m64\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nCounts the number of leading most significant zero bits in a source operand (second operand) returning the result\r\ninto a destination (first operand).\r\nLZCNT differs from BSR. For example, LZCNT will produce the operand size when the input operand is zero. It\r\nshould be noted that on processors that do not support LZCNT, the instruction byte encoding is executed as BSR.\r\nIn 64-bit mode 64-bit operand size requires REX.W=1.\r\n\r\nOperation\r\ntemp <- OperandSize - 1\r\nDEST <- 0\r\nWHILE (temp >= 0) AND (Bit(SRC, temp) = 0)\r\nDO\r\n temp <- temp - 1\r\n DEST <- DEST+ 1\r\nOD\r\n\r\nIF DEST = OperandSize\r\n CF <- 1\r\nELSE\r\n CF <- 0\r\nFI\r\n\r\nIF DEST = 0\r\n ZF <- 1\r\nELSE\r\n ZF <- 0\r\nFI\r\n\r\nFlags Affected\r\nZF flag is set to 1 in case of zero output (most significant bit of the source is set), and to 0 otherwise, CF flag is set\r\nto 1 if input was zero and cleared otherwise. OF, SF, PF and AF flags are undefined.\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nLZCNT: unsigned __int32 _lzcnt_u32(unsigned __int32 src);\r\n\r\nLZCNT: unsigned __int64 _lzcnt_u64(unsigned __int64 src);\r\n\r\nProtected Mode Exceptions\r\n#GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a null segment\r\n selector.\r\n#SS(0) For an illegal address in the SS segment.\r\n#PF (fault-code) For a page fault.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n\r\nReal-Address Mode Exceptions\r\n#GP(0) If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.\r\n#SS(0) For an illegal address in the SS segment.\r\n\r\nVirtual 8086 Mode Exceptions\r\n#GP(0) If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.\r\n#SS(0) For an illegal address in the SS segment.\r\n#PF (fault-code) For a page fault.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in Protected Mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#PF (fault-code) For a page fault.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "LZCNT"
},
{
"description": "MASKMOVDQU-Store Selected Bytes of Double Quadword\r\n Opcode/ Op/ 64/32-bit CPUID Description\r\n Instruction En Mode Feature\r\n Flag\r\n 66 0F F7 /r RM V/V SSE2 Selectively write bytes from xmm1 to\r\n MASKMOVDQU xmm1, xmm2 memory location using the byte mask in\r\n xmm2. The default memory location is\r\n specified by DS:DI/EDI/RDI.\r\n VEX.128.66.0F.WIG F7 /r RM V/V AVX Selectively write bytes from xmm1 to\r\n VMASKMOVDQU xmm1, xmm2 memory location using the byte mask in\r\n xmm2. The default memory location is\r\n specified by DS:DI/EDI/RDI.\r\n\r\n\r\n\r\n Instruction Operand Encoding1\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r) ModRM:r/m (r) NA NA\r\n\r\n\r\nDescription\r\nStores selected bytes from the source operand (first operand) into an 128-bit memory location. The mask operand\r\n(second operand) selects which bytes from the source operand are written to memory. The source and mask oper-\r\nands are XMM registers. The memory location specified by the effective address in the DI/EDI/RDI register (the\r\ndefault segment register is DS, but this may be overridden with a segment-override prefix). The memory location\r\ndoes not need to be aligned on a natural boundary. (The size of the store address depends on the address-size\r\nattribute.)\r\nThe most significant bit in each byte of the mask operand determines whether the corresponding byte in the source\r\noperand is written to the corresponding byte location in memory: 0 indicates no write and 1 indicates write.\r\nThe MASKMOVDQU instruction generates a non-temporal hint to the processor to minimize cache pollution. The\r\nnon-temporal hint is implemented by using a write combining (WC) memory type protocol (see \"Caching of\r\nTemporal vs. Non-Temporal Data\" in Chapter 10, of the Intel 64 and IA-32 Architectures Software Developer's\r\nManual, Volume 1). Because the WC protocol uses a weakly-ordered memory consistency model, a fencing opera-\r\ntion implemented with the SFENCE or MFENCE instruction should be used in conjunction with MASKMOVDQU\r\ninstructions if multiple processors might use different memory types to read/write the destination memory loca-\r\ntions.\r\nBehavior with a mask of all 0s is as follows:\r\n. No data will be written to memory.\r\n. Signaling of breakpoints (code or data) is not guaranteed; different processor implementations may signal or\r\n not signal these breakpoints.\r\n. Exceptions associated with addressing memory and page faults may still be signaled (implementation\r\n dependent).\r\n. If the destination memory region is mapped as UC or WP, enforcement of associated semantics for these\r\n memory types is not guaranteed (that is, is reserved) and is implementation-specific.\r\nThe MASKMOVDQU instruction can be used to improve performance of algorithms that need to merge data on a\r\nbyte-by-byte basis. MASKMOVDQU should not cause a read for ownership; doing so generates unnecessary band-\r\nwidth since data is to be written directly using the byte-mask without allocating old data prior to the store.\r\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).\r\nNote: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\nIf VMASKMOVDQU is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will\r\ncause an #UD exception.\r\n\r\n1.ModRM.MOD = 011B required\r\n\r\n\r\n\r\nOperation\r\n\r\nIF (MASK[7] = 1)\r\n THEN DEST[DI/EDI] <- SRC[7:0] ELSE (* Memory location unchanged *); FI;\r\nIF (MASK[15] = 1)\r\n THEN DEST[DI/EDI +1] <- SRC[15:8] ELSE (* Memory location unchanged *); FI;\r\n (* Repeat operation for 3rd through 14th bytes in source operand *)\r\nIF (MASK[127] = 1)\r\n THEN DEST[DI/EDI +15] <- SRC[127:120] ELSE (* Memory location unchanged *); FI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nvoid _mm_maskmoveu_si128(__m128i d, __m128i n, char * p)\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4; additionally\r\n#UD If VEX.L= 1\r\n If VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MASKMOVDQU"
},
{
"description": "MASKMOVQ-Store Selected Bytes of Quadword\r\n Opcode/ Op/ 64-Bit Compat/ Description\r\n Instruction En Mode Leg Mode\r\n 0F F7 /r RM Valid Valid Selectively write bytes from mm1 to memory\r\n MASKMOVQ mm1, mm2 location using the byte mask in mm2. The\r\n default memory location is specified by\r\n DS:DI/EDI/RDI.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r) ModRM:r/m (r) NA NA\r\n\r\n\r\nDescription\r\nStores selected bytes from the source operand (first operand) into a 64-bit memory location. The mask operand\r\n(second operand) selects which bytes from the source operand are written to memory. The source and mask oper-\r\nands are MMX technology registers. The memory location specified by the effective address in the DI/EDI/RDI\r\nregister (the default segment register is DS, but this may be overridden with a segment-override prefix). The\r\nmemory location does not need to be aligned on a natural boundary. (The size of the store address depends on the\r\naddress-size attribute.)\r\nThe most significant bit in each byte of the mask operand determines whether the corresponding byte in the source\r\noperand is written to the corresponding byte location in memory: 0 indicates no write and 1 indicates write.\r\nThe MASKMOVQ instruction generates a non-temporal hint to the processor to minimize cache pollution. The non-\r\ntemporal hint is implemented by using a write combining (WC) memory type protocol (see \"Caching of Temporal\r\nvs. Non-Temporal Data\" in Chapter 10, of the Intel 64 and IA-32 Architectures Software Developer's Manual,\r\nVolume 1). Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation imple-\r\nmented with the SFENCE or MFENCE instruction should be used in conjunction with MASKMOVQ instructions if\r\nmultiple processors might use different memory types to read/write the destination memory locations.\r\nThis instruction causes a transition from x87 FPU to MMX technology state (that is, the x87 FPU top-of-stack pointer\r\nis set to 0 and the x87 FPU tag word is set to all 0s [valid]).\r\nThe behavior of the MASKMOVQ instruction with a mask of all 0s is as follows:\r\n. No data will be written to memory.\r\n. Transition from x87 FPU to MMX technology state will occur.\r\n. Exceptions associated with addressing memory and page faults may still be signaled (implementation\r\n dependent).\r\n. Signaling of breakpoints (code or data) is not guaranteed (implementation dependent).\r\n. If the destination memory region is mapped as UC or WP, enforcement of associated semantics for these\r\n memory types is not guaranteed (that is, is reserved) and is implementation-specific.\r\nThe MASKMOVQ instruction can be used to improve performance for algorithms that need to merge data on a byte-\r\nby-byte basis. It should not cause a read for ownership; doing so generates unnecessary bandwidth since data is\r\nto be written directly using the byte-mask without allocating old data prior to the store.\r\nIn 64-bit mode, the memory address is specified by DS:RDI.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\n\r\nIF (MASK[7] = 1)\r\n THEN DEST[DI/EDI] <- SRC[7:0] ELSE (* Memory location unchanged *); FI;\r\nIF (MASK[15] = 1)\r\n THEN DEST[DI/EDI +1] <- SRC[15:8] ELSE (* Memory location unchanged *); FI;\r\n (* Repeat operation for 3rd through 6th bytes in source operand *)\r\nIF (MASK[63] = 1)\r\n THEN DEST[DI/EDI +15] <- SRC[63:56] ELSE (* Memory location unchanged *); FI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nvoid _mm_maskmove_si64(__m64d, __m64n, char * p)\r\n\r\nOther Exceptions\r\nSee Table 22-8, \"Exception Conditions for Legacy SIMD/MMX Instructions without FP Exception,\" in the Intel 64\r\nand IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MASKMOVQ"
},
{
"description": "MAXPD-Maximum of Packed Double-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0F 5F /r RM V/V SSE2 Return the maximum double-precision floating-point\r\n MAXPD xmm1, xmm2/m128 values between xmm1 and xmm2/m128.\r\n VEX.NDS.128.66.0F.WIG 5F /r RVM V/V AVX Return the maximum double-precision floating-point\r\n VMAXPD xmm1, xmm2, xmm3/m128 values between xmm2 and xmm3/m128.\r\n VEX.NDS.256.66.0F.WIG 5F /r RVM V/V AVX Return the maximum packed double-precision\r\n VMAXPD ymm1, ymm2, ymm3/m256 floating-point values between ymm2 and\r\n ymm3/m256.\r\n EVEX.NDS.128.66.0F.W1 5F /r FV V/V AVX512VL Return the maximum packed double-precision\r\n VMAXPD xmm1 {k1}{z}, xmm2, AVX512F floating-point values between xmm2 and\r\n xmm3/m128/m64bcst xmm3/m128/m64bcst and store result in xmm1\r\n subject to writemask k1.\r\n EVEX.NDS.256.66.0F.W1 5F /r FV V/V AVX512VL Return the maximum packed double-precision\r\n VMAXPD ymm1 {k1}{z}, ymm2, AVX512F floating-point values between ymm2 and\r\n ymm3/m256/m64bcst ymm3/m256/m64bcst and store result in ymm1\r\n subject to writemask k1.\r\n EVEX.NDS.512.66.0F.W1 5F /r FV V/V AVX512F Return the maximum packed double-precision\r\n VMAXPD zmm1 {k1}{z}, zmm2, floating-point values between zmm2 and\r\n zmm3/m512/m64bcst{sae} zmm3/m512/m64bcst and store result in zmm1\r\n subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a SIMD compare of the packed double-precision floating-point values in the first source operand and the\r\nsecond source operand and returns the maximum value for each pair of values to the destination operand.\r\nIf the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is\r\nreturned. If a value in the second operand is an SNaN, then SNaN is forwarded unchanged to the destination (that\r\nis, a QNaN version of the SNaN is not returned).\r\nIf only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN\r\nor a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source\r\noperand (from either the first or second operand) be returned, the action of MAXPD can be emulated using a\r\nsequence of instructions, such as a comparison followed by AND, ANDN and OR.\r\nEVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second\r\nsource operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector\r\nbroadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally\r\nupdated with writemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)\r\nof the corresponding ZMM register destination are zeroed.\r\nVEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM\r\nregister or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n\r\n\r\n\r\n\r\n\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nZMM register destination are unmodified.\r\n\r\nOperation\r\nMAX(SRC1, SRC2)\r\n{\r\n IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST <-SRC2;\r\n ELSE IF (SRC1 = SNaN) THEN DEST <-SRC2; FI;\r\n ELSE IF (SRC2 = SNaN) THEN DEST <-SRC2; FI;\r\n ELSE IF (SRC1 > SRC2) THEN DEST <-SRC1;\r\n ELSE DEST <-SRC2;\r\n FI;\r\n}\r\n\r\nVMAXPD (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN\r\n DEST[i+63:i] <- MAX(SRC1[i+63:i], SRC2[63:0])\r\n ELSE\r\n DEST[i+63:i] <- MAX(SRC1[i+63:i], SRC2[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE DEST[i+63:i] <- 0 ; zeroing-masking\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMAXPD (VEX.256 encoded version)\r\nDEST[63:0] <-MAX(SRC1[63:0], SRC2[63:0])\r\nDEST[127:64] <-MAX(SRC1[127:64], SRC2[127:64])\r\nDEST[191:128] <-MAX(SRC1[191:128], SRC2[191:128])\r\nDEST[255:192] <-MAX(SRC1[255:192], SRC2[255:192])\r\nDEST[MAX_VL-1:256] <-0\r\n\r\nVMAXPD (VEX.128 encoded version)\r\nDEST[63:0] <-MAX(SRC1[63:0], SRC2[63:0])\r\nDEST[127:64] <-MAX(SRC1[127:64], SRC2[127:64])\r\nDEST[MAX_VL-1:128] <-0\r\n\r\n\r\n\r\n\r\n\r\nMAXPD (128-bit Legacy SSE version)\r\nDEST[63:0] <-MAX(DEST[63:0], SRC[63:0])\r\nDEST[127:64] <-MAX(DEST[127:64], SRC[127:64])\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMAXPD __m512d _mm512_max_pd( __m512d a, __m512d b);\r\nVMAXPD __m512d _mm512_mask_max_pd(__m512d s, __mmask8 k, __m512d a, __m512d b,);\r\nVMAXPD __m512d _mm512_maskz_max_pd( __mmask8 k, __m512d a, __m512d b);\r\nVMAXPD __m512d _mm512_max_round_pd( __m512d a, __m512d b, int);\r\nVMAXPD __m512d _mm512_mask_max_round_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int);\r\nVMAXPD __m512d _mm512_maskz_max_round_pd( __mmask8 k, __m512d a, __m512d b, int);\r\nVMAXPD __m256d _mm256_mask_max_pd(__m5256d s, __mmask8 k, __m256d a, __m256d b);\r\nVMAXPD __m256d _mm256_maskz_max_pd( __mmask8 k, __m256d a, __m256d b);\r\nVMAXPD __m128d _mm_mask_max_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);\r\nVMAXPD __m128d _mm_maskz_max_pd( __mmask8 k, __m128d a, __m128d b);\r\nVMAXPD __m256d _mm256_max_pd (__m256d a, __m256d b);\r\n(V)MAXPD __m128d _mm_max_pd (__m128d a, __m128d b);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid (including QNaN Source Operand), Denormal\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 2.\r\nEVEX-encoded instruction, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MAXPD"
},
{
"description": "MAXPS-Maximum of Packed Single-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 0F 5F /r RM V/V SSE Return the maximum single-precision floating-point values\r\n MAXPS xmm1, xmm2/m128 between xmm1 and xmm2/mem.\r\n VEX.NDS.128.0F.WIG 5F /r RVM V/V AVX Return the maximum single-precision floating-point values\r\n VMAXPS xmm1, xmm2, between xmm2 and xmm3/mem.\r\n xmm3/m128\r\n VEX.NDS.256.0F.WIG 5F /r RVM V/V AVX Return the maximum single-precision floating-point values\r\n VMAXPS ymm1, ymm2, between ymm2 and ymm3/mem.\r\n ymm3/m256\r\n EVEX.NDS.128.0F.W0 5F /r FV V/V AVX512VL Return the maximum packed single-precision floating-point\r\n VMAXPS xmm1 {k1}{z}, xmm2, AVX512F values between xmm2 and xmm3/m128/m32bcst and store\r\n xmm3/m128/m32bcst result in xmm1 subject to writemask k1.\r\n EVEX.NDS.256.0F.W0 5F /r FV V/V AVX512VL Return the maximum packed single-precision floating-point\r\n VMAXPS ymm1 {k1}{z}, ymm2, AVX512F values between ymm2 and ymm3/m256/m32bcst and store\r\n ymm3/m256/m32bcst result in ymm1 subject to writemask k1.\r\n EVEX.NDS.512.0F.W0 5F /r FV V/V AVX512F Return the maximum packed single-precision floating-point\r\n VMAXPS zmm1 {k1}{z}, zmm2, values between zmm2 and zmm3/m512/m32bcst and store\r\n zmm3/m512/m32bcst{sae} result in zmm1 subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a SIMD compare of the packed single-precision floating-point values in the first source operand and the\r\nsecond source operand and returns the maximum value for each pair of values to the destination operand.\r\nIf the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is\r\nreturned. If a value in the second operand is an SNaN, then SNaN is forwarded unchanged to the destination (that\r\nis, a QNaN version of the SNaN is not returned).\r\nIf only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN\r\nor a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source\r\noperand (from either the first or second operand) be returned, the action of MAXPS can be emulated using a\r\nsequence of instructions, such as, a comparison followed by AND, ANDN and OR.\r\nEVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second\r\nsource operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector\r\nbroadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally\r\nupdated with writemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)\r\nof the corresponding ZMM register destination are zeroed.\r\nVEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM\r\nregister or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nZMM register destination are unmodified.\r\n\r\n\r\n\r\n\r\nOperation\r\nMAX(SRC1, SRC2)\r\n{\r\n IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST <-SRC2;\r\n ELSE IF (SRC1 = SNaN) THEN DEST <-SRC2; FI;\r\n ELSE IF (SRC2 = SNaN) THEN DEST <-SRC2; FI;\r\n ELSE IF (SRC1 > SRC2) THEN DEST <-SRC1;\r\n ELSE DEST <-SRC2;\r\n FI;\r\n}\r\n\r\nVMAXPS (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN\r\n DEST[i+31:i] <- MAX(SRC1[i+31:i], SRC2[31:0])\r\n ELSE\r\n DEST[i+31:i] <- MAX(SRC1[i+31:i], SRC2[i+31:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE DEST[i+31:i] <- 0 ; zeroing-masking\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMAXPS (VEX.256 encoded version)\r\nDEST[31:0] <-MAX(SRC1[31:0], SRC2[31:0])\r\nDEST[63:32] <-MAX(SRC1[63:32], SRC2[63:32])\r\nDEST[95:64] <-MAX(SRC1[95:64], SRC2[95:64])\r\nDEST[127:96] <-MAX(SRC1[127:96], SRC2[127:96])\r\nDEST[159:128] <-MAX(SRC1[159:128], SRC2[159:128])\r\nDEST[191:160] <-MAX(SRC1[191:160], SRC2[191:160])\r\nDEST[223:192] <-MAX(SRC1[223:192], SRC2[223:192])\r\nDEST[255:224] <-MAX(SRC1[255:224], SRC2[255:224])\r\nDEST[MAX_VL-1:256] <-0\r\n\r\nVMAXPS (VEX.128 encoded version)\r\nDEST[31:0] <-MAX(SRC1[31:0], SRC2[31:0])\r\nDEST[63:32] <-MAX(SRC1[63:32], SRC2[63:32])\r\nDEST[95:64] <-MAX(SRC1[95:64], SRC2[95:64])\r\nDEST[127:96] <-MAX(SRC1[127:96], SRC2[127:96])\r\nDEST[MAX_VL-1:128] <-0\r\n\r\n\r\n\r\n\r\n\r\nMAXPS (128-bit Legacy SSE version)\r\nDEST[31:0] <-MAX(DEST[31:0], SRC[31:0])\r\nDEST[63:32] <-MAX(DEST[63:32], SRC[63:32])\r\nDEST[95:64] <-MAX(DEST[95:64], SRC[95:64])\r\nDEST[127:96] <-MAX(DEST[127:96], SRC[127:96])\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMAXPS __m512 _mm512_max_ps( __m512 a, __m512 b);\r\nVMAXPS __m512 _mm512_mask_max_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);\r\nVMAXPS __m512 _mm512_maskz_max_ps( __mmask16 k, __m512 a, __m512 b);\r\nVMAXPS __m512 _mm512_max_round_ps( __m512 a, __m512 b, int);\r\nVMAXPS __m512 _mm512_mask_max_round_ps(__m512 s, __mmask16 k, __m512 a, __m512 b, int);\r\nVMAXPS __m512 _mm512_maskz_max_round_ps( __mmask16 k, __m512 a, __m512 b, int);\r\nVMAXPS __m256 _mm256_mask_max_ps(__m256 s, __mmask8 k, __m256 a, __m256 b);\r\nVMAXPS __m256 _mm256_maskz_max_ps( __mmask8 k, __m256 a, __m256 b);\r\nVMAXPS __m128 _mm_mask_max_ps(__m128 s, __mmask8 k, __m128 a, __m128 b);\r\nVMAXPS __m128 _mm_maskz_max_ps( __mmask8 k, __m128 a, __m128 b);\r\nVMAXPS __m256 _mm256_max_ps (__m256 a, __m256 b);\r\nMAXPS __m128 _mm_max_ps (__m128 a, __m128 b);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid (including QNaN Source Operand), Denormal\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 2.\r\nEVEX-encoded instruction, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MAXPS"
},
{
"description": "MAXSD-Return Maximum Scalar Double-Precision Floating-Point Value\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n F2 0F 5F /r RM V/V SSE2 Return the maximum scalar double-precision floating-point\r\n MAXSD xmm1, xmm2/m64 value between xmm2/m64 and xmm1.\r\n VEX.NDS.128.F2.0F.WIG 5F /r RVM V/V AVX Return the maximum scalar double-precision floating-point\r\n VMAXSD xmm1, xmm2, value between xmm3/m64 and xmm2.\r\n xmm3/m64\r\n EVEX.NDS.LIG.F2.0F.W1 5F /r T1S V/V AVX512F Return the maximum scalar double-precision floating-point\r\n VMAXSD xmm1 {k1}{z}, xmm2, value between xmm3/m64 and xmm2.\r\n xmm3/m64{sae}\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n T1S ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nCompares the low double-precision floating-point values in the first source operand and the second source\r\noperand, and returns the maximum value to the low quadword of the destination operand. The second source\r\noperand can be an XMM register or a 64-bit memory location. The first source and destination operands are XMM\r\nregisters. When the second source operand is a memory operand, only 64 bits are accessed.\r\nIf the values being compared are both 0.0s (of either sign), the value in the second source operand is returned. If\r\na value in the second source operand is an SNaN, that SNaN is returned unchanged to the destination (that is, a\r\nQNaN version of the SNaN is not returned).\r\nIf only one value is a NaN (SNaN or QNaN) for this instruction, the second source operand, either a NaN or a valid\r\nfloating-point value, is written to the result. If instead of this behavior, it is required that the NaN of either source\r\noperand be returned, the action of MAXSD can be emulated using a sequence of instructions, such as, a comparison\r\nfollowed by AND, ANDN and OR.\r\n128-bit Legacy SSE version: The destination and first source operand are the same. Bits (MAX_VL-1:64) of the\r\ncorresponding destination register remain unchanged.\r\nVEX.128 and EVEX encoded version: Bits (127:64) of the XMM register destination are copied from corresponding\r\nbits in the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.\r\nEVEX encoded version: The low quadword element of the destination operand is updated according to the\r\nwritemask.\r\nSoftware should ensure VMAXSD is encoded with VEX.L=0. Encoding VMAXSD with VEX.L=1 may encounter unpre-\r\ndictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nMAX(SRC1, SRC2)\r\n{\r\n IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST <-SRC2;\r\n ELSE IF (SRC1 = SNaN) THEN DEST <-SRC2; FI;\r\n ELSE IF (SRC2 = SNaN) THEN DEST <-SRC2; FI;\r\n ELSE IF (SRC1 > SRC2) THEN DEST <-SRC1;\r\n ELSE DEST <-SRC2;\r\n FI;\r\n}\r\n\r\nVMAXSD (EVEX encoded version)\r\nIF k1[0] or *no writemask*\r\n THEN DEST[63:0] <- MAX(SRC1[63:0], SRC2[63:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[63:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVMAXSD (VEX.128 encoded version)\r\nDEST[63:0] <-MAX(SRC1[63:0], SRC2[63:0])\r\nDEST[127:64] <-SRC1[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nMAXSD (128-bit Legacy SSE version)\r\nDEST[63:0] <-MAX(DEST[63:0], SRC[63:0])\r\nDEST[MAX_VL-1:64] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMAXSD __m128d _mm_max_round_sd( __m128d a, __m128d b, int);\r\nVMAXSD __m128d _mm_mask_max_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int);\r\nVMAXSD __m128d _mm_maskz_max_round_sd( __mmask8 k, __m128d a, __m128d b, int);\r\nMAXSD __m128d _mm_max_sd(__m128d a, __m128d b)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid (Including QNaN Source Operand), Denormal\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 3.\r\nEVEX-encoded instruction, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MAXSD"
},
{
"description": "MAXSS-Return Maximum Scalar Single-Precision Floating-Point Value\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n F3 0F 5F /r RM V/V SSE Return the maximum scalar single-precision floating-point\r\n MAXSS xmm1, xmm2/m32 value between xmm2/m32 and xmm1.\r\n VEX.NDS.128.F3.0F.WIG 5F /r RVM V/V AVX Return the maximum scalar single-precision floating-point\r\n VMAXSS xmm1, xmm2, value between xmm3/m32 and xmm2.\r\n xmm3/m32\r\n EVEX.NDS.LIG.F3.0F.W0 5F /r T1S V/V AVX512F Return the maximum scalar single-precision floating-point\r\n VMAXSS xmm1 {k1}{z}, xmm2, value between xmm3/m32 and xmm2.\r\n xmm3/m32{sae}\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n T1S ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nCompares the low single-precision floating-point values in the first source operand and the second source operand,\r\nand returns the maximum value to the low doubleword of the destination operand.\r\nIf the values being compared are both 0.0s (of either sign), the value in the second source operand is returned. If\r\na value in the second source operand is an SNaN, that SNaN is returned unchanged to the destination (that is, a\r\nQNaN version of the SNaN is not returned).\r\nIf only one value is a NaN (SNaN or QNaN) for this instruction, the second source operand, either a NaN or a valid\r\nfloating-point value, is written to the result. If instead of this behavior, it is required that the NaN from either source\r\noperand be returned, the action of MAXSS can be emulated using a sequence of instructions, such as, a comparison\r\nfollowed by AND, ANDN and OR.\r\nThe second source operand can be an XMM register or a 32-bit memory location. The first source and destination\r\noperands are XMM registers.\r\n128-bit Legacy SSE version: The destination and first source operand are the same. Bits (MAX_VL:32) of the corre-\r\nsponding destination register remain unchanged.\r\nVEX.128 and EVEX encoded version: The first source operand is an xmm register encoded by VEX.vvvv. Bits\r\n(127:32) of the XMM register destination are copied from corresponding bits in the first source operand. Bits\r\n(MAX_VL:128) of the destination register are zeroed.\r\nEVEX encoded version: The low doubleword element of the destination operand is updated according to the\r\nwritemask.\r\nSoftware should ensure VMAXSS is encoded with VEX.L=0. Encoding VMAXSS with VEX.L=1 may encounter unpre-\r\ndictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nMAX(SRC1, SRC2)\r\n{\r\n IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST <-SRC2;\r\n ELSE IF (SRC1 = SNaN) THEN DEST <-SRC2; FI;\r\n ELSE IF (SRC2 = SNaN) THEN DEST <-SRC2; FI;\r\n ELSE IF (SRC1 > SRC2) THEN DEST <-SRC1;\r\n ELSE DEST <-SRC2;\r\n FI;\r\n}\r\n\r\nVMAXSS (EVEX encoded version)\r\nIF k1[0] or *no writemask*\r\n THEN DEST[31:0] <- MAX(SRC1[31:0], SRC2[31:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[31:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:32] <- SRC1[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVMAXSS (VEX.128 encoded version)\r\nDEST[31:0] <-MAX(SRC1[31:0], SRC2[31:0])\r\nDEST[127:32] <-SRC1[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nMAXSS (128-bit Legacy SSE version)\r\nDEST[31:0] <-MAX(DEST[31:0], SRC[31:0])\r\nDEST[MAX_VL-1:32] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMAXSS __m128 _mm_max_round_ss( __m128 a, __m128 b, int);\r\nVMAXSS __m128 _mm_mask_max_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int);\r\nVMAXSS __m128 _mm_maskz_max_round_ss( __mmask8 k, __m128 a, __m128 b, int);\r\nMAXSS __m128 _mm_max_ss(__m128 a, __m128 b)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid (Including QNaN Source Operand), Denormal\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 3.\r\nEVEX-encoded instruction, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MAXSS"
},
{
"description": "MFENCE-Memory Fence\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F AE F0 MFENCE NP Valid Valid Serializes load and store operations.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nPerforms a serializing operation on all load-from-memory and store-to-memory instructions that were issued prior\r\nthe MFENCE instruction. This serializing operation guarantees that every load and store instruction that precedes\r\nthe MFENCE instruction in program order becomes globally visible before any load or store instruction that follows\r\nthe MFENCE instruction.1 The MFENCE instruction is ordered with respect to all load and store instructions, other\r\nMFENCE instructions, any LFENCE and SFENCE instructions, and any serializing instructions (such as the CPUID\r\ninstruction). MFENCE does not serialize the instruction stream.\r\nWeakly ordered memory types can be used to achieve higher processor performance through such techniques as\r\nout-of-order issue, speculative reads, write-combining, and write-collapsing. The degree to which a consumer of\r\ndata recognizes or knows that the data is weakly ordered varies among applications and may be unknown to the\r\nproducer of this data. The MFENCE instruction provides a performance-efficient way of ensuring load and store\r\nordering between routines that produce weakly-ordered results and routines that consume that data.\r\nProcessors are free to fetch and cache data speculatively from regions of system memory that use the WB, WC, and\r\nWT memory types. This speculative fetching can occur at any time and is not tied to instruction execution. Thus, it\r\nis not ordered with respect to executions of the MFENCE instruction; data can be brought into the caches specula-\r\ntively just before, during, or after the execution of an MFENCE instruction.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\nSpecification of the instruction's opcode above indicates a ModR/M byte of F0. For this instruction, the processor\r\nignores the r/m field of the ModR/M byte. Thus, MFENCE is encoded by any opcode of the form 0F AE Fx, where x\r\nis in the range 0-7.\r\n\r\nOperation\r\n\r\nWait_On_Following_Loads_And_Stores_Until(preceding_loads_and_stores_globally_visible);\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nvoid _mm_mfence(void)\r\n\r\nExceptions (All Modes of Operation)\r\n#UD If CPUID.01H:EDX.SSE2[bit 26] = 0.\r\n If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n1. A load instruction is considered to become globally visible when the value to be loaded into its destination register is determined.\r\n\r\n\r\n",
"mnem": "MFENCE"
},
{
"description": "MINPD-Minimum of Packed Double-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0F 5D /r RM V/V SSE2 Return the minimum double-precision floating-point values\r\n MINPD xmm1, xmm2/m128 between xmm1 and xmm2/mem\r\n VEX.NDS.128.66.0F.WIG 5D /r RVM V/V AVX Return the minimum double-precision floating-point values\r\n VMINPD xmm1, xmm2, between xmm2 and xmm3/mem.\r\n xmm3/m128\r\n VEX.NDS.256.66.0F.WIG 5D /r RVM V/V AVX Return the minimum packed double-precision floating-point\r\n VMINPD ymm1, ymm2, values between ymm2 and ymm3/mem.\r\n ymm3/m256\r\n EVEX.NDS.128.66.0F.W1 5D /r FV V/V AVX512VL Return the minimum packed double-precision floating-point\r\n VMINPD xmm1 {k1}{z}, xmm2, AVX512F values between xmm2 and xmm3/m128/m64bcst and store\r\n xmm3/m128/m64bcst result in xmm1 subject to writemask k1.\r\n EVEX.NDS.256.66.0F.W1 5D /r FV V/V AVX512VL Return the minimum packed double-precision floating-point\r\n VMINPD ymm1 {k1}{z}, ymm2, AVX512F values between ymm2 and ymm3/m256/m64bcst and store\r\n ymm3/m256/m64bcst result in ymm1 subject to writemask k1.\r\n EVEX.NDS.512.66.0F.W1 5D /r FV V/V AVX512F Return the minimum packed double-precision floating-point\r\n VMINPD zmm1 {k1}{z}, zmm2, values between zmm2 and zmm3/m512/m64bcst and store\r\n zmm3/m512/m64bcst{sae} result in zmm1 subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a SIMD compare of the packed double-precision floating-point values in the first source operand and the\r\nsecond source operand and returns the minimum value for each pair of values to the destination operand.\r\nIf the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is\r\nreturned. If a value in the second operand is an SNaN, then SNaN is forwarded unchanged to the destination (that\r\nis, a QNaN version of the SNaN is not returned).\r\nIf only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN\r\nor a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source\r\noperand (from either the first or second operand) be returned, the action of MINPD can be emulated using a\r\nsequence of instructions, such as, a comparison followed by AND, ANDN and OR.\r\nEVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second\r\nsource operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector\r\nbroadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally\r\nupdated with writemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)\r\nof the corresponding ZMM register destination are zeroed.\r\nVEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM\r\nregister or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nZMM register destination are unmodified.\r\n\r\n\r\n\r\n\r\nOperation\r\nMIN(SRC1, SRC2)\r\n{\r\n IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST <-SRC2;\r\n ELSE IF (SRC1 = SNaN) THEN DEST <-SRC2; FI;\r\n ELSE IF (SRC2 = SNaN) THEN DEST <-SRC2; FI;\r\n ELSE IF (SRC1 < SRC2) THEN DEST <-SRC1;\r\n ELSE DEST <-SRC2;\r\n FI;\r\n}\r\n\r\nVMINPD (EVEX encoded version)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN\r\n DEST[i+63:i] <- MIN(SRC1[i+63:i], SRC2[63:0])\r\n ELSE\r\n DEST[i+63:i] <- MIN(SRC1[i+63:i], SRC2[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE DEST[i+63:i] <- 0 ; zeroing-masking\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMINPD (VEX.256 encoded version)\r\nDEST[63:0] <-MIN(SRC1[63:0], SRC2[63:0])\r\nDEST[127:64] <-MIN(SRC1[127:64], SRC2[127:64])\r\nDEST[191:128] <-MIN(SRC1[191:128], SRC2[191:128])\r\nDEST[255:192] <-MIN(SRC1[255:192], SRC2[255:192])\r\n\r\nVMINPD (VEX.128 encoded version)\r\nDEST[63:0] <-MIN(SRC1[63:0], SRC2[63:0])\r\nDEST[127:64] <-MIN(SRC1[127:64], SRC2[127:64])\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nMINPD (128-bit Legacy SSE version)\r\nDEST[63:0] <-MIN(SRC1[63:0], SRC2[63:0])\r\nDEST[127:64] <-MIN(SRC1[127:64], SRC2[127:64])\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMINPD __m512d _mm512_min_pd( __m512d a, __m512d b);\r\nVMINPD __m512d _mm512_mask_min_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);\r\nVMINPD __m512d _mm512_maskz_min_pd( __mmask8 k, __m512d a, __m512d b);\r\nVMINPD __m512d _mm512_min_round_pd( __m512d a, __m512d b, int);\r\nVMINPD __m512d _mm512_mask_min_round_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int);\r\nVMINPD __m512d _mm512_maskz_min_round_pd( __mmask8 k, __m512d a, __m512d b, int);\r\nVMINPD __m256d _mm256_mask_min_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);\r\nVMINPD __m256d _mm256_maskz_min_pd( __mmask8 k, __m256d a, __m256d b);\r\nVMINPD __m128d _mm_mask_min_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);\r\nVMINPD __m128d _mm_maskz_min_pd( __mmask8 k, __m128d a, __m128d b);\r\nVMINPD __m256d _mm256_min_pd (__m256d a, __m256d b);\r\nMINPD __m128d _mm_min_pd (__m128d a, __m128d b);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid (including QNaN Source Operand), Denormal\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 2.\r\nEVEX-encoded instruction, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MINPD"
},
{
"description": "MINPS-Minimum of Packed Single-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 0F 5D /r RM V/V SSE Return the minimum single-precision floating-point values\r\n MINPS xmm1, xmm2/m128 between xmm1 and xmm2/mem.\r\n VEX.NDS.128.0F.WIG 5D /r RVM V/V AVX Return the minimum single-precision floating-point values\r\n VMINPS xmm1, xmm2, between xmm2 and xmm3/mem.\r\n xmm3/m128\r\n VEX.NDS.256.0F.WIG 5D /r RVM V/V AVX Return the minimum single double-precision floating-point\r\n VMINPS ymm1, ymm2, values between ymm2 and ymm3/mem.\r\n ymm3/m256\r\n EVEX.NDS.128.0F.W0 5D /r FV V/V AVX512VL Return the minimum packed single-precision floating-point\r\n VMINPS xmm1 {k1}{z}, xmm2, AVX512F values between xmm2 and xmm3/m128/m32bcst and store\r\n xmm3/m128/m32bcst result in xmm1 subject to writemask k1.\r\n EVEX.NDS.256.0F.W0 5D /r FV V/V AVX512VL Return the minimum packed single-precision floating-point\r\n VMINPS ymm1 {k1}{z}, ymm2, AVX512F values between ymm2 and ymm3/m256/m32bcst and store\r\n ymm3/m256/m32bcst result in ymm1 subject to writemask k1.\r\n EVEX.NDS.512.0F.W0 5D /r FV V/V AVX512F Return the minimum packed single-precision floating-point\r\n VMINPS zmm1 {k1}{z}, zmm2, values between zmm2 and zmm3/m512/m32bcst and store\r\n zmm3/m512/m32bcst{sae} result in zmm1 subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a SIMD compare of the packed single-precision floating-point values in the first source operand and the\r\nsecond source operand and returns the minimum value for each pair of values to the destination operand.\r\nIf the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is\r\nreturned. If a value in the second operand is an SNaN, then SNaN is forwarded unchanged to the destination (that\r\nis, a QNaN version of the SNaN is not returned).\r\nIf only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN\r\nor a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source\r\noperand (from either the first or second operand) be returned, the action of MINPS can be emulated using a\r\nsequence of instructions, such as, a comparison followed by AND, ANDN and OR.\r\nEVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second\r\nsource operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector\r\nbroadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally\r\nupdated with writemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)\r\nof the corresponding ZMM register destination are zeroed.\r\nVEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM\r\nregister or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nZMM register destination are unmodified.\r\n\r\n\r\n\r\n\r\nOperation\r\nMIN(SRC1, SRC2)\r\n{\r\n IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST <-SRC2;\r\n ELSE IF (SRC1 = SNaN) THEN DEST <-SRC2; FI;\r\n ELSE IF (SRC2 = SNaN) THEN DEST <-SRC2; FI;\r\n ELSE IF (SRC1 < SRC2) THEN DEST <-SRC1;\r\n ELSE DEST <-SRC2;\r\n FI;\r\n}\r\n\r\nVMINPS (EVEX encoded version)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN\r\n DEST[i+31:i] <- MIN(SRC1[i+31:i], SRC2[31:0])\r\n ELSE\r\n DEST[i+31:i] <- MIN(SRC1[i+31:i], SRC2[i+31:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE DEST[i+31:i] <- 0 ; zeroing-masking\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMINPS (VEX.256 encoded version)\r\nDEST[31:0] <-MIN(SRC1[31:0], SRC2[31:0])\r\nDEST[63:32] <-MIN(SRC1[63:32], SRC2[63:32])\r\nDEST[95:64] <-MIN(SRC1[95:64], SRC2[95:64])\r\nDEST[127:96] <-MIN(SRC1[127:96], SRC2[127:96])\r\nDEST[159:128] <-MIN(SRC1[159:128], SRC2[159:128])\r\nDEST[191:160] <-MIN(SRC1[191:160], SRC2[191:160])\r\nDEST[223:192] <-MIN(SRC1[223:192], SRC2[223:192])\r\nDEST[255:224] <-MIN(SRC1[255:224], SRC2[255:224])\r\n\r\nVMINPS (VEX.128 encoded version)\r\nDEST[31:0] <-MIN(SRC1[31:0], SRC2[31:0])\r\nDEST[63:32] <-MIN(SRC1[63:32], SRC2[63:32])\r\nDEST[95:64] <-MIN(SRC1[95:64], SRC2[95:64])\r\nDEST[127:96] <-MIN(SRC1[127:96], SRC2[127:96])\r\nDEST[MAX_VL-1:128] <-0\r\n\r\n\r\n\r\n\r\n\r\nMINPS (128-bit Legacy SSE version)\r\nDEST[31:0] <-MIN(SRC1[31:0], SRC2[31:0])\r\nDEST[63:32] <-MIN(SRC1[63:32], SRC2[63:32])\r\nDEST[95:64] <-MIN(SRC1[95:64], SRC2[95:64])\r\nDEST[127:96] <-MIN(SRC1[127:96], SRC2[127:96])\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMINPS __m512 _mm512_min_ps( __m512 a, __m512 b);\r\nVMINPS __m512 _mm512_mask_min_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);\r\nVMINPS __m512 _mm512_maskz_min_ps( __mmask16 k, __m512 a, __m512 b);\r\nVMINPS __m512 _mm512_min_round_ps( __m512 a, __m512 b, int);\r\nVMINPS __m512 _mm512_mask_min_round_ps(__m512 s, __mmask16 k, __m512 a, __m512 b, int);\r\nVMINPS __m512 _mm512_maskz_min_round_ps( __mmask16 k, __m512 a, __m512 b, int);\r\nVMINPS __m256 _mm256_mask_min_ps(__m256 s, __mmask8 k, __m256 a, __m256 b);\r\nVMINPS __m256 _mm256_maskz_min_ps( __mmask8 k, __m256 a, __m25 b);\r\nVMINPS __m128 _mm_mask_min_ps(__m128 s, __mmask8 k, __m128 a, __m128 b);\r\nVMINPS __m128 _mm_maskz_min_ps( __mmask8 k, __m128 a, __m128 b);\r\nVMINPS __m256 _mm256_min_ps (__m256 a, __m256 b);\r\nMINPS __m128 _mm_min_ps (__m128 a, __m128 b);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid (including QNaN Source Operand), Denormal\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 2.\r\nEVEX-encoded instruction, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MINPS"
},
{
"description": "MINSD-Return Minimum Scalar Double-Precision Floating-Point Value\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n F2 0F 5D /r RM V/V SSE2 Return the minimum scalar double-precision floating-\r\n MINSD xmm1, xmm2/m64 point value between xmm2/m64 and xmm1.\r\n VEX.NDS.128.F2.0F.WIG 5D /r RVM V/V AVX Return the minimum scalar double-precision floating-\r\n VMINSD xmm1, xmm2, xmm3/m64 point value between xmm3/m64 and xmm2.\r\n EVEX.NDS.LIG.F2.0F.W1 5D /r T1S V/V AVX512F Return the minimum scalar double-precision floating-\r\n VMINSD xmm1 {k1}{z}, xmm2, point value between xmm3/m64 and xmm2.\r\n xmm3/m64{sae}\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n T1S ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nCompares the low double-precision floating-point values in the first source operand and the second source\r\noperand, and returns the minimum value to the low quadword of the destination operand. When the source\r\noperand is a memory operand, only the 64 bits are accessed.\r\nIf the values being compared are both 0.0s (of either sign), the value in the second source operand is returned. If\r\na value in the second source operand is an SNaN, then SNaN is returned unchanged to the destination (that is, a\r\nQNaN version of the SNaN is not returned).\r\nIf only one value is a NaN (SNaN or QNaN) for this instruction, the second source operand, either a NaN or a valid\r\nfloating-point value, is written to the result. If instead of this behavior, it is required that the NaN source operand\r\n(from either the first or second source) be returned, the action of MINSD can be emulated using a sequence of\r\ninstructions, such as, a comparison followed by AND, ANDN and OR.\r\nThe second source operand can be an XMM register or a 64-bit memory location. The first source and destination\r\noperands are XMM registers.\r\n128-bit Legacy SSE version: The destination and first source operand are the same. Bits (MAX_VL-1:64) of the\r\ncorresponding destination register remain unchanged.\r\nVEX.128 and EVEX encoded version: Bits (127:64) of the XMM register destination are copied from corresponding\r\nbits in the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.\r\nEVEX encoded version: The low quadword element of the destination operand is updated according to the\r\nwritemask.\r\nSoftware should ensure VMINSD is encoded with VEX.L=0. Encoding VMINSD with VEX.L=1 may encounter unpre-\r\ndictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nMIN(SRC1, SRC2)\r\n{\r\n IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST <-SRC2;\r\n ELSE IF (SRC1 = SNaN) THEN DEST <-SRC2; FI;\r\n ELSE IF (SRC2 = SNaN) THEN DEST <-SRC2; FI;\r\n ELSE IF (SRC1 < SRC2) THEN DEST <-SRC1;\r\n ELSE DEST <-SRC2;\r\n FI;\r\n}\r\n\r\nMINSD (EVEX encoded version)\r\nIF k1[0] or *no writemask*\r\n THEN DEST[63:0] <- MIN(SRC1[63:0], SRC2[63:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[63:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nMINSD (VEX.128 encoded version)\r\nDEST[63:0] <-MIN(SRC1[63:0], SRC2[63:0])\r\nDEST[127:64] <-SRC1[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nMINSD (128-bit Legacy SSE version)\r\nDEST[63:0] <-MIN(SRC1[63:0], SRC2[63:0])\r\nDEST[MAX_VL-1:64] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMINSD __m128d _mm_min_round_sd(__m128d a, __m128d b, int);\r\nVMINSD __m128d _mm_mask_min_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int);\r\nVMINSD __m128d _mm_maskz_min_round_sd( __mmask8 k, __m128d a, __m128d b, int);\r\nMINSD __m128d _mm_min_sd(__m128d a, __m128d b)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid (including QNaN Source Operand), Denormal\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 3.\r\nEVEX-encoded instruction, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MINSD"
},
{
"description": "MINSS-Return Minimum Scalar Single-Precision Floating-Point Value\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n F3 0F 5D /r RM V/V SSE Return the minimum scalar single-precision floating-\r\n MINSS xmm1,xmm2/m32 point value between xmm2/m32 and xmm1.\r\n VEX.NDS.128.F3.0F.WIG 5D /r RVM V/V AVX Return the minimum scalar single-precision floating-\r\n VMINSS xmm1,xmm2, xmm3/m32 point value between xmm3/m32 and xmm2.\r\n EVEX.NDS.LIG.F3.0F.W0 5D /r T1S V/V AVX512F Return the minimum scalar single-precision floating-\r\n VMINSS xmm1 {k1}{z}, xmm2, point value between xmm3/m32 and xmm2.\r\n xmm3/m32{sae}\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n T1S ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nCompares the low single-precision floating-point values in the first source operand and the second source operand\r\nand returns the minimum value to the low doubleword of the destination operand.\r\nIf the values being compared are both 0.0s (of either sign), the value in the second source operand is returned. If\r\na value in the second operand is an SNaN, that SNaN is returned unchanged to the destination (that is, a QNaN\r\nversion of the SNaN is not returned).\r\nIf only one value is a NaN (SNaN or QNaN) for this instruction, the second source operand, either a NaN or a valid\r\nfloating-point value, is written to the result. If instead of this behavior, it is required that the NaN in either source\r\noperand be returned, the action of MINSD can be emulated using a sequence of instructions, such as, a comparison\r\nfollowed by AND, ANDN and OR.\r\nThe second source operand can be an XMM register or a 32-bit memory location. The first source and destination\r\noperands are XMM registers.\r\n128-bit Legacy SSE version: The destination and first source operand are the same. Bits (MAX_VL:32) of the corre-\r\nsponding destination register remain unchanged.\r\nVEX.128 and EVEX encoded version: The first source operand is an xmm register encoded by (E)VEX.vvvv. Bits\r\n(127:32) of the XMM register destination are copied from corresponding bits in the first source operand. Bits\r\n(MAX_VL-1:128) of the destination register are zeroed.\r\nEVEX encoded version: The low doubleword element of the destination operand is updated according to the\r\nwritemask.\r\nSoftware should ensure VMINSS is encoded with VEX.L=0. Encoding VMINSS with VEX.L=1 may encounter unpre-\r\ndictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nMIN(SRC1, SRC2)\r\n{\r\n IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST <-SRC2;\r\n ELSE IF (SRC1 = SNaN) THEN DEST <-SRC2; FI;\r\n ELSE IF (SRC2 = SNaN) THEN DEST <-SRC2; FI;\r\n ELSE IF (SRC1 < SRC2) THEN DEST <-SRC1;\r\n ELSE DEST <-SRC2;\r\n FI;\r\n}\r\n\r\nMINSS (EVEX encoded version)\r\nIF k1[0] or *no writemask*\r\n THEN DEST[31:0] <- MIN(SRC1[31:0], SRC2[31:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[31:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:32] <- SRC1[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVMINSS (VEX.128 encoded version)\r\nDEST[31:0] <-MIN(SRC1[31:0], SRC2[31:0])\r\nDEST[127:32] <-SRC1[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nMINSS (128-bit Legacy SSE version)\r\nDEST[31:0] <-MIN(SRC1[31:0], SRC2[31:0])\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMINSS __m128 _mm_min_round_ss( __m128 a, __m128 b, int);\r\nVMINSS __m128 _mm_mask_min_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int);\r\nVMINSS __m128 _mm_maskz_min_round_ss( __mmask8 k, __m128 a, __m128 b, int);\r\nMINSS __m128 _mm_min_ss(__m128 a, __m128 b)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid (Including QNaN Source Operand), Denormal\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 2.\r\nEVEX-encoded instruction, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MINSS"
},
{
"description": "MONITOR-Set Up Monitor Address\r\nOpcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n0F 01 C8 MONITOR NP Valid Valid Sets up a linear address range to be\r\n monitored by hardware and activates the\r\n monitor. The address range should be a write-\r\n back memory caching type. The address is\r\n DS:EAX (DS:RAX in 64-bit mode).\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nThe MONITOR instruction arms address monitoring hardware using an address specified in EAX (the address range\r\nthat the monitoring hardware checks for store operations can be determined by using CPUID). A store to an\r\naddress within the specified address range triggers the monitoring hardware. The state of monitor hardware is\r\nused by MWAIT.\r\nThe content of EAX is an effective address (in 64-bit mode, RAX is used). By default, the DS segment is used to\r\ncreate a linear address that is monitored. Segment overrides can be used.\r\nECX and EDX are also used. They communicate other information to MONITOR. ECX specifies optional extensions.\r\nEDX specifies optional hints; it does not change the architectural behavior of the instruction. For the Pentium 4\r\nprocessor (family 15, model 3), no extensions or hints are defined. Undefined hints in EDX are ignored by the\r\nprocessor; undefined extensions in ECX raises a general protection fault.\r\nThe address range must use memory of the write-back type. Only write-back memory will correctly trigger the\r\nmonitoring hardware. Additional information on determining what address range to use in order to prevent false\r\nwake-ups is described in Chapter 8, \"Multiple-Processor Management\" of the Intel 64 and IA-32 Architectures\r\nSoftware Developer's Manual, Volume 3A.\r\nThe MONITOR instruction is ordered as a load operation with respect to other memory transactions. The instruction\r\nis subject to the permission checking and faults associated with a byte load. Like a load, MONITOR sets the A-bit\r\nbut not the D-bit in page tables.\r\nCPUID.01H:ECX.MONITOR[bit 3] indicates the availability of MONITOR and MWAIT in the processor. When set,\r\nMONITOR may be executed only at privilege level 0 (use at any other privilege level results in an invalid-opcode\r\nexception). The operating system or system BIOS may disable this instruction by using the IA32_MISC_ENABLE\r\nMSR; disabling MONITOR clears the CPUID feature flag and causes execution to generate an invalid-opcode excep-\r\ntion.\r\nThe instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nMONITOR sets up an address range for the monitor hardware using the content of EAX (RAX in 64-bit mode) as an\r\neffective address and puts the monitor hardware in armed state. Always use memory of the write-back caching\r\ntype. A store to the specified address range will trigger the monitor hardware. The content of ECX and EDX are\r\nused to communicate other information to the monitor hardware.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nMONITOR: void _mm_monitor(void const *p, unsigned extensions,unsigned hints)\r\n\r\nNumeric Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the value in EAX is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n If ECX != 0.\r\n#SS(0) If the value in EAX is outside the SS segment limit.\r\n#PF(fault-code) For a page fault.\r\n#UD If CPUID.01H:ECX.MONITOR[bit 3] = 0.\r\n If current privilege level is not 0.\r\n\r\nReal Address Mode Exceptions\r\n#GP If the CS, DS, ES, FS, or GS register is used to access memory and the value in EAX is outside\r\n of the effective address space from 0 to FFFFH.\r\n If ECX != 0.\r\n#SS If the SS register is used to access memory and the value in EAX is outside of the effective\r\n address space from 0 to FFFFH.\r\n#UD If CPUID.01H:ECX.MONITOR[bit 3] = 0.\r\n\r\nVirtual 8086 Mode Exceptions\r\n#UD The MONITOR instruction is not recognized in virtual-8086 mode (even if\r\n CPUID.01H:ECX.MONITOR[bit 3] = 1).\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the linear address of the operand in the CS, DS, ES, FS, or GS segment is in a non-canonical\r\n form.\r\n If RCX != 0.\r\n#SS(0) If the SS register is used to access memory and the value in EAX is in a non-canonical form.\r\n#PF(fault-code) For a page fault.\r\n#UD If the current privilege level is not 0.\r\n If CPUID.01H:ECX.MONITOR[bit 3] = 0.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MONITOR"
},
{
"description": "MOV-Move\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 88 /r MOV r/m8,r8 MR Valid Valid Move r8 to r/m8.\r\n REX + 88 /r MOV r/m8***,r8*** MR Valid N.E. Move r8 to r/m8.\r\n 89 /r MOV r/m16,r16 MR Valid Valid Move r16 to r/m16.\r\n 89 /r MOV r/m32,r32 MR Valid Valid Move r32 to r/m32.\r\n REX.W + 89 /r MOV r/m64,r64 MR Valid N.E. Move r64 to r/m64.\r\n 8A /r MOV r8,r/m8 RM Valid Valid Move r/m8 to r8.\r\n REX + 8A /r MOV r8***,r/m8*** RM Valid N.E. Move r/m8 to r8.\r\n 8B /r MOV r16,r/m16 RM Valid Valid Move r/m16 to r16.\r\n 8B /r MOV r32,r/m32 RM Valid Valid Move r/m32 to r32.\r\n REX.W + 8B /r MOV r64,r/m64 RM Valid N.E. Move r/m64 to r64.\r\n 8C /r MOV r/m16,Sreg** MR Valid Valid Move segment register to r/m16.\r\n REX.W + 8C /r MOV r/m64,Sreg** MR Valid Valid Move zero extended 16-bit segment register\r\n to r/m64.\r\n 8E /r MOV Sreg,r/m16** RM Valid Valid Move r/m16 to segment register.\r\n REX.W + 8E /r MOV Sreg,r/m64** RM Valid Valid Move lower 16 bits of r/m64 to segment\r\n register.\r\n A0 MOV AL,moffs8* FD Valid Valid Move byte at (seg:offset) to AL.\r\n REX.W + A0 MOV AL,moffs8* FD Valid N.E. Move byte at (offset) to AL.\r\n A1 MOV AX,moffs16* FD Valid Valid Move word at (seg:offset) to AX.\r\n A1 MOV EAX,moffs32* FD Valid Valid Move doubleword at (seg:offset) to EAX.\r\n REX.W + A1 MOV RAX,moffs64* FD Valid N.E. Move quadword at (offset) to RAX.\r\n A2 MOV moffs8,AL TD Valid Valid Move AL to (seg:offset).\r\n REX.W + A2 MOV moffs8***,AL TD Valid N.E. Move AL to (offset).\r\n A3 MOV moffs16*,AX TD Valid Valid Move AX to (seg:offset).\r\n A3 MOV moffs32*,EAX TD Valid Valid Move EAX to (seg:offset).\r\n REX.W + A3 MOV moffs64*,RAX TD Valid N.E. Move RAX to (offset).\r\n B0+ rb ib MOV r8, imm8 OI Valid Valid Move imm8 to r8.\r\n ***\r\n REX + B0+ rb ib MOV r8 , imm8 OI Valid N.E. Move imm8 to r8.\r\n B8+ rw iw MOV r16, imm16 OI Valid Valid Move imm16 to r16.\r\n B8+ rd id MOV r32, imm32 OI Valid Valid Move imm32 to r32.\r\n REX.W + B8+ rd io MOV r64, imm64 OI Valid N.E. Move imm64 to r64.\r\n C6 /0 ib MOV r/m8, imm8 MI Valid Valid Move imm8 to r/m8.\r\n REX + C6 /0 ib MOV r/m8***, imm8 MI Valid N.E. Move imm8 to r/m8.\r\n C7 /0 iw MOV r/m16, imm16 MI Valid Valid Move imm16 to r/m16.\r\n C7 /0 id MOV r/m32, imm32 MI Valid Valid Move imm32 to r/m32.\r\n REX.W + C7 /0 id MOV r/m64, imm32 MI Valid N.E. Move imm32 sign extended to 64-bits to\r\n r/m64.\r\n\r\n\r\n\r\n\r\n\r\n NOTES:\r\n * The moffs8, moffs16, moffs32 and moffs64 operands specify a simple offset relative to the segment base, where 8, 16, 32 and 64\r\n refer to the size of the data. The address-size attribute of the instruction determines the size of the offset, either 16, 32 or 64\r\n bits.\r\n ** In 32-bit mode, the assembler may insert the 16-bit operand-size prefix with this instruction (see the following \"Description\" sec-\r\n tion for further information).\r\n ***In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n FD AL/AX/EAX/RAX Moffs NA NA\r\n TD Moffs (w) AL/AX/EAX/RAX NA NA\r\n OI opcode + rd (w) imm8/16/32/64 NA NA\r\n MI ModRM:r/m (w) imm8/16/32/64 NA NA\r\n\r\n\r\nDescription\r\nCopies the second operand (source operand) to the first operand (destination operand). The source operand can be\r\nan immediate value, general-purpose register, segment register, or memory location; the destination register can\r\nbe a general-purpose register, segment register, or memory location. Both operands must be the same size, which\r\ncan be a byte, a word, a doubleword, or a quadword.\r\nThe MOV instruction cannot be used to load the CS register. Attempting to do so results in an invalid opcode excep-\r\ntion (#UD). To load the CS register, use the far JMP, CALL, or RET instruction.\r\nIf the destination operand is a segment register (DS, ES, FS, GS, or SS), the source operand must be a valid\r\nsegment selector. In protected mode, moving a segment selector into a segment register automatically causes the\r\nsegment descriptor information associated with that segment selector to be loaded into the hidden (shadow) part\r\nof the segment register. While loading this information, the segment selector and segment descriptor information\r\nis validated (see the \"Operation\" algorithm below). The segment descriptor data is obtained from the GDT or LDT\r\nentry for the specified segment selector.\r\nA NULL segment selector (values 0000-0003) can be loaded into the DS, ES, FS, and GS registers without causing\r\na protection exception. However, any subsequent attempt to reference a segment whose corresponding segment\r\nregister is loaded with a NULL value causes a general protection exception (#GP) and no memory reference occurs.\r\nLoading the SS register with a MOV instruction inhibits all interrupts until after the execution of the next instruc-\r\ntion. This operation allows a stack pointer to be loaded into the ESP register with the next instruction (MOV ESP,\r\nstack-pointer value) before an interrupt occurs1. Be aware that the LSS instruction offers a more efficient\r\nmethod of loading the SS and ESP registers.\r\nWhen executing MOV Reg, Sreg, the processor copies the content of Sreg to the 16 least significant bits of the\r\ngeneral-purpose register. The upper bits of the destination register are zero for most IA-32 processors (Pentium\r\n\r\n\r\n1. If a code instruction breakpoint (for debug) is placed on an instruction located immediately after a MOV SS instruction, the break-\r\n point may not be triggered. However, in a sequence of instructions that load the SS register, only the first instruction in the\r\n sequence is guaranteed to delay an interrupt.\r\n In the following sequence, interrupts may be recognized before MOV ESP, EBP executes:\r\n MOV SS, EDX\r\n MOV SS, EAX\r\n MOV ESP, EBP\r\n\r\n\r\n\r\n\r\n\r\nPro processors and later) and all Intel 64 processors, with the exception that bits 31:16 are undefined for Intel\r\nQuark X1000 processors, Pentium and earlier processors.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-\r\ntional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the\r\nbeginning of this section for encoding data and limits.\r\n\r\nOperation\r\nDEST <- SRC;\r\nLoading a segment register while in protected mode results in special checks and actions, as described in the\r\nfollowing listing. These checks are performed on the segment selector and the segment descriptor to which it\r\npoints.\r\n\r\nIF SS is loaded\r\n THEN\r\n IF segment selector is NULL\r\n THEN #GP(0); FI;\r\n IF segment selector index is outside descriptor table limits\r\n or segment selector's RPL != CPL\r\n or segment is not a writable data segment\r\n or DPL != CPL\r\n THEN #GP(selector); FI;\r\n IF segment not marked present\r\n THEN #SS(selector);\r\n ELSE\r\n SS <- segment selector;\r\n SS <- segment descriptor; FI;\r\nFI;\r\n\r\nIF DS, ES, FS, or GS is loaded with non-NULL selector\r\nTHEN\r\n IF segment selector index is outside descriptor table limits\r\n or segment is not a data or readable code segment\r\n or ((segment is a data or nonconforming code segment)\r\n or ((RPL > DPL) and (CPL > DPL))\r\n THEN #GP(selector); FI;\r\n IF segment not marked present\r\n THEN #NP(selector);\r\n ELSE\r\n SegmentRegister <- segment selector;\r\n SegmentRegister <- segment descriptor; FI;\r\nFI;\r\n\r\nIF DS, ES, FS, or GS is loaded with NULL selector\r\n THEN\r\n SegmentRegister <- segment selector;\r\n SegmentRegister <- segment descriptor;\r\nFI;\r\n\r\nFlags Affected\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If attempt is made to load SS register with NULL segment selector.\r\n If the destination operand is in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#GP(selector) If segment selector index is outside descriptor table limits.\r\n If the SS register is being loaded and the segment selector's RPL and the segment descriptor's\r\n DPL are not equal to the CPL.\r\n If the SS register is being loaded and the segment pointed to is a\r\n non-writable data segment.\r\n If the DS, ES, FS, or GS register is being loaded and the segment pointed to is not a data or\r\n readable code segment.\r\n If the DS, ES, FS, or GS register is being loaded and the segment pointed to is a data or\r\n nonconforming code segment, but both the RPL and the CPL are greater than the DPL.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#SS(selector) If the SS register is being loaded and the segment pointed to is marked not present.\r\n#NP If the DS, ES, FS, or GS register is being loaded and the segment pointed to is marked not\r\n present.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If attempt is made to load the CS register.\r\n If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If attempt is made to load the CS register.\r\n If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If attempt is made to load the CS register.\r\n If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the memory address is in a non-canonical form.\r\n If an attempt is made to load SS register with NULL segment selector when CPL = 3.\r\n If an attempt is made to load SS register with NULL segment selector when CPL < 3 and CPL\r\n != RPL.\r\n#GP(selector) If segment selector index is outside descriptor table limits.\r\n If the memory access to the descriptor table is non-canonical.\r\n If the SS register is being loaded and the segment selector's RPL and the segment descriptor's\r\n DPL are not equal to the CPL.\r\n If the SS register is being loaded and the segment pointed to is a nonwritable data segment.\r\n If the DS, ES, FS, or GS register is being loaded and the segment pointed to is not a data or\r\n readable code segment.\r\n If the DS, ES, FS, or GS register is being loaded and the segment pointed to is a data or\r\n nonconforming code segment, but both the RPL and the CPL are greater than the DPL.\r\n#SS(0) If the stack address is in a non-canonical form.\r\n#SS(selector) If the SS register is being loaded and the segment pointed to is marked not present.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If attempt is made to load the CS register.\r\n If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOV"
},
{
"description": "MOV-Move to/from Control Registers\r\nOpcode/ Op/ 64-Bit Compat/ Description\r\nInstruction En Mode Leg Mode\r\n0F 20/r MR N.E. Valid Move control register to r32.\r\nMOV r32, CR0-CR7\r\n0F 20/r MR Valid N.E. Move extended control register to r64.\r\nMOV r64, CR0-CR7\r\nREX.R + 0F 20 /0 MR Valid N.E. Move extended CR8 to r64.1\r\nMOV r64, CR8\r\n0F 22 /r RM N.E. Valid Move r32 to control register.\r\nMOV CR0-CR7, r32\r\n0F 22 /r RM Valid N.E. Move r64 to extended control register.\r\nMOV CR0-CR7, r64\r\nREX.R + 0F 22 /0 RM Valid N.E. Move r64 to extended CR8.1\r\nMOV CR8, r64\r\nNOTE:\r\n1. MOV CR* instructions, except for MOV CR8, are serializing instructions. MOV CR8 is not\r\n architecturally defined as a serializing instruction. For more information, see Chapter 8 in Intel 64 and IA-32 Architectures Soft-\r\n ware Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\n\r\nDescription\r\nMoves the contents of a control register (CR0, CR2, CR3, CR4, or CR8) to a general-purpose register or the\r\ncontents of a general purpose register to a control register. The operand size for these instructions is always 32 bits\r\nin non-64-bit modes, regardless of the operand-size attribute. (See \"Control Registers\" in Chapter 2 of the Intel\r\n64 and IA-32 Architectures Software Developer's Manual, Volume 3A, for a detailed description of the flags and\r\nfields in the control registers.) This instruction can be executed only when the current privilege level is 0.\r\nAt the opcode level, the reg field within the ModR/M byte specifies which of the control registers is loaded or read.\r\nThe 2 bits in the mod field are ignored. The r/m field specifies the general-purpose register loaded or read.\r\nAttempts to reference CR1, CR5, CR6, CR7, and CR9-CR15 result in undefined opcode (#UD) exceptions.\r\nWhen loading control registers, programs should not attempt to change the reserved bits; that is, always set\r\nreserved bits to the value previously read. An attempt to change CR4's reserved bits will cause a general protection\r\nfault. Reserved bits in CR0 and CR3 remain clear after any load of those registers; attempts to set them have no\r\nimpact. On Pentium 4, Intel Xeon and P6 family processors, CR0.ET remains set after any load of CR0; attempts to\r\nclear this bit have no impact.\r\nIn certain cases, these instructions have the side effect of invalidating entries in the TLBs and the paging-structure\r\ncaches. See Section 4.10.4.1, \"Operations that Invalidate TLBs and Paging-Structure Caches,\" in the Intel 64 and\r\nIA-32 Architectures Software Developer's Manual, Volume 3A for details.\r\nThe following side effects are implementation-specific for the Pentium 4, Intel Xeon, and P6 processor family: when\r\nmodifying PE or PG in register CR0, or PSE or PAE in register CR4, all TLB entries are flushed, including global\r\nentries. Software should not depend on this functionality in all Intel 64 or IA-32 processors.\r\nIn 64-bit mode, the instruction's default operation size is 64 bits. The REX.R prefix must be used to access CR8. Use\r\nof REX.B permits access to additional registers (R8-R15). Use of the REX.W prefix or 66H prefix is ignored. Use of\r\n\r\n\r\n\r\n\r\nthe REX.R prefix to specify a register other than CR8 causes an invalid-opcode exception. See the summary chart\r\nat the beginning of this section for encoding data and limits.\r\nIf CR4.PCIDE = 1, bit 63 of the source operand to MOV to CR3 determines whether the instruction invalidates\r\nentries in the TLBs and the paging-structure caches (see Section 4.10.4.1, \"Operations that Invalidate TLBs and\r\nPaging-Structure Caches,\" in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A). The\r\ninstruction does not modify bit 63 of CR3, which is reserved and always 0.\r\nSee \"Changes to Instruction Behavior in VMX Non-Root Operation\" in Chapter 25 of the Intel 64 and IA-32 Archi-\r\ntectures Software Developer's Manual, Volume 3C, for more information about the behavior of this instruction in\r\nVMX non-root operation.\r\n\r\nOperation\r\nDEST <- SRC;\r\n\r\nFlags Affected\r\nThe OF, SF, ZF, AF, PF, and CF flags are undefined.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the current privilege level is not 0.\r\n If an attempt is made to write invalid bit combinations in CR0 (such as setting the PG flag to 1\r\n when the PE flag is set to 0, or setting the CD flag to 0 when the NW flag is set to 1).\r\n If an attempt is made to write a 1 to any reserved bit in CR4.\r\n If an attempt is made to write 1 to CR4.PCIDE.\r\n If any of the reserved bits are set in the page-directory pointers table (PDPT) and the loading\r\n of a control register causes the PDPT to be loaded into the processor.\r\n#UD If the LOCK prefix is used.\r\n If an attempt is made to access CR1, CR5, CR6, or CR7.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If an attempt is made to write a 1 to any reserved bit in CR4.\r\n If an attempt is made to write 1 to CR4.PCIDE.\r\n If an attempt is made to write invalid bit combinations in CR0 (such as setting the PG flag to 1\r\n when the PE flag is set to 0).\r\n#UD If the LOCK prefix is used.\r\n If an attempt is made to access CR1, CR5, CR6, or CR7.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) These instructions cannot be executed in virtual-8086 mode.\r\n\r\nCompatibility Mode Exceptions\r\n#GP(0) If the current privilege level is not 0.\r\n If an attempt is made to write invalid bit combinations in CR0 (such as setting the PG flag to 1\r\n when the PE flag is set to 0, or setting the CD flag to 0 when the NW flag is set to 1).\r\n If an attempt is made to change CR4.PCIDE from 0 to 1 while CR3[11:0] != 000H.\r\n If an attempt is made to clear CR0.PG[bit 31] while CR4.PCIDE = 1.\r\n If an attempt is made to write a 1 to any reserved bit in CR3.\r\n If an attempt is made to leave IA-32e mode by clearing CR4.PAE[bit 5].\r\n#UD If the LOCK prefix is used.\r\n If an attempt is made to access CR1, CR5, CR6, or CR7.\r\n\r\n\r\n\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the current privilege level is not 0.\r\n If an attempt is made to write invalid bit combinations in CR0 (such as setting the PG flag to 1\r\n when the PE flag is set to 0, or setting the CD flag to 0 when the NW flag is set to 1).\r\n If an attempt is made to change CR4.PCIDE from 0 to 1 while CR3[11:0] != 000H.\r\n If an attempt is made to clear CR0.PG[bit 31].\r\n If an attempt is made to write a 1 to any reserved bit in CR4.\r\n If an attempt is made to write a 1 to any reserved bit in CR8.\r\n If an attempt is made to write a 1 to any reserved bit in CR3.\r\n If an attempt is made to leave IA-32e mode by clearing CR4.PAE[bit 5].\r\n#UD If the LOCK prefix is used.\r\n If an attempt is made to access CR1, CR5, CR6, or CR7.\r\n If the REX.R prefix is used to specify a register other than CR8.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOV"
},
{
"description": "MOV-Move to/from Debug Registers\r\nOpcode/ Op/ 64-Bit Compat/ Description\r\nInstruction En Mode Leg Mode\r\n0F 21/r MR N.E. Valid Move debug register to r32.\r\nMOV r32, DR0-DR7\r\n0F 21/r MR Valid N.E. Move extended debug register to r64.\r\nMOV r64, DR0-DR7\r\n0F 23 /r RM N.E. Valid Move r32 to debug register.\r\nMOV DR0-DR7, r32\r\n0F 23 /r RM Valid N.E. Move r64 to extended debug register.\r\nMOV DR0-DR7, r64\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\n\r\nDescription\r\nMoves the contents of a debug register (DR0, DR1, DR2, DR3, DR4, DR5, DR6, or DR7) to a general-purpose\r\nregister or vice versa. The operand size for these instructions is always 32 bits in non-64-bit modes, regardless of\r\nthe operand-size attribute. (See Section 17.2, \"Debug Registers\", of the Intel 64 and IA-32 Architectures Soft-\r\nware Developer's Manual, Volume 3A, for a detailed description of the flags and fields in the debug registers.)\r\nThe instructions must be executed at privilege level 0 or in real-address mode.\r\nWhen the debug extension (DE) flag in register CR4 is clear, these instructions operate on debug registers in a\r\nmanner that is compatible with Intel386 and Intel486 processors. In this mode, references to DR4 and DR5 refer\r\nto DR6 and DR7, respectively. When the DE flag in CR4 is set, attempts to reference DR4 and DR5 result in an\r\nundefined opcode (#UD) exception. (The CR4 register was added to the IA-32 Architecture beginning with the\r\nPentium processor.)\r\nAt the opcode level, the reg field within the ModR/M byte specifies which of the debug registers is loaded or read.\r\nThe two bits in the mod field are ignored. The r/m field specifies the general-purpose register loaded or read.\r\nIn 64-bit mode, the instruction's default operation size is 64 bits. Use of the REX.B prefix permits access to addi-\r\ntional registers (R8-R15). Use of the REX.W or 66H prefix is ignored. Use of the REX.R prefix causes an invalid-\r\nopcode exception. See the summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nIF ((DE = 1) and (SRC or DEST = DR4 or DR5))\r\n THEN\r\n #UD;\r\n ELSE\r\n DEST <- SRC;\r\n\r\nFI;\r\n\r\nFlags Affected\r\nThe OF, SF, ZF, AF, PF, and CF flags are undefined.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the current privilege level is not 0.\r\n#UD If CR4.DE[bit 3] = 1 (debug extensions) and a MOV instruction is executed involving DR4 or\r\n DR5.\r\n If the LOCK prefix is used.\r\n#DB If any debug register is accessed while the DR7.GD[bit 13] = 1.\r\n\r\nReal-Address Mode Exceptions\r\n#UD If CR4.DE[bit 3] = 1 (debug extensions) and a MOV instruction is executed involving DR4 or\r\n DR5.\r\n If the LOCK prefix is used.\r\n#DB If any debug register is accessed while the DR7.GD[bit 13] = 1.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) The debug registers cannot be loaded or read when in virtual-8086 mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the current privilege level is not 0.\r\n If an attempt is made to write a 1 to any of bits 63:32 in DR6.\r\n If an attempt is made to write a 1 to any of bits 63:32 in DR7.\r\n#UD If CR4.DE[bit 3] = 1 (debug extensions) and a MOV instruction is executed involving DR4 or\r\n DR5.\r\n If the LOCK prefix is used.\r\n If the REX.R prefix is used.\r\n#DB If any debug register is accessed while the DR7.GD[bit 13] = 1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOV"
},
{
"description": "MOVAPD-Move Aligned Packed Double-Precision Floating-Point Values\r\n Opcode/ Op/En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n 66 0F 28 /r RM V/V SSE2 Move aligned packed double-precision floating-\r\n MOVAPD xmm1, xmm2/m128 point values from xmm2/mem to xmm1.\r\n 66 0F 29 /r MR V/V SSE2 Move aligned packed double-precision floating-\r\n MOVAPD xmm2/m128, xmm1 point values from xmm1 to xmm2/mem.\r\n VEX.128.66.0F.WIG 28 /r RM V/V AVX Move aligned packed double-precision floating-\r\n VMOVAPD xmm1, xmm2/m128 point values from xmm2/mem to xmm1.\r\n VEX.128.66.0F.WIG 29 /r MR V/V AVX Move aligned packed double-precision floating-\r\n VMOVAPD xmm2/m128, xmm1 point values from xmm1 to xmm2/mem.\r\n VEX.256.66.0F.WIG 28 /r RM V/V AVX Move aligned packed double-precision floating-\r\n VMOVAPD ymm1, ymm2/m256 point values from ymm2/mem to ymm1.\r\n VEX.256.66.0F.WIG 29 /r MR V/V AVX Move aligned packed double-precision floating-\r\n VMOVAPD ymm2/m256, ymm1 point values from ymm1 to ymm2/mem.\r\n EVEX.128.66.0F.W1 28 /r FVM-RM V/V AVX512VL Move aligned packed double-precision floating-\r\n VMOVAPD xmm1 {k1}{z}, xmm2/m128 AVX512F point values from xmm2/m128 to xmm1 using\r\n writemask k1.\r\n EVEX.256.66.0F.W1 28 /r FVM-RM V/V AVX512VL Move aligned packed double-precision floating-\r\n VMOVAPD ymm1 {k1}{z}, ymm2/m256 AVX512F point values from ymm2/m256 to ymm1 using\r\n writemask k1.\r\n EVEX.512.66.0F.W1 28 /r FVM-RM V/V AVX512F Move aligned packed double-precision floating-\r\n VMOVAPD zmm1 {k1}{z}, zmm2/m512 point values from zmm2/m512 to zmm1 using\r\n writemask k1.\r\n EVEX.128.66.0F.W1 29 /r FVM-MR V/V AVX512VL Move aligned packed double-precision floating-\r\n VMOVAPD xmm2/m128 {k1}{z}, xmm1 AVX512F point values from xmm1 to xmm2/m128 using\r\n writemask k1.\r\n EVEX.256.66.0F.W1 29 /r FVM-MR V/V AVX512VL Move aligned packed double-precision floating-\r\n VMOVAPD ymm2/m256 {k1}{z}, ymm1 AVX512F point values from ymm1 to ymm2/m256 using\r\n writemask k1.\r\n EVEX.512.66.0F.W1 29 /r FVM-MR V/V AVX512F Move aligned packed double-precision floating-\r\n VMOVAPD zmm2/m512 {k1}{z}, zmm1 point values from zmm1 to zmm2/m512 using\r\n writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n FVM-RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n FVM-MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\n\r\n\r\n\r\n\r\nDescription\r\nMoves 2, 4 or 8 double-precision floating-point values from the source operand (second operand) to the destination\r\noperand (first operand). This instruction can be used to load an XMM, YMM or ZMM register from an 128-bit, 256-\r\nbit or 512-bit memory location, to store the contents of an XMM, YMM or ZMM register into a 128-bit, 256-bit or\r\n512-bit memory location, or to move data between two XMM, two YMM or two ZMM registers.\r\nWhen the source or destination operand is a memory operand, the operand must be aligned on a 16-byte (128-bit\r\nversions), 32-byte (256-bit version) or 64-byte (EVEX.512 encoded version) boundary or a general-protection\r\nexception (#GP) will be generated. For EVEX encoded versions, the operand must be aligned to the size of the\r\nmemory operand. To move double-precision floating-point values to and from unaligned memory locations, use the\r\nVMOVUPD instruction.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\nEVEX.512 encoded version:\r\nMoves 512 bits of packed double-precision floating-point values from the source operand (second operand) to the\r\ndestination operand (first operand). This instruction can be used to load a ZMM register from a 512-bit float64\r\nmemory location, to store the contents of a ZMM register into a 512-bit float64 memory location, or to move data\r\nbetween two ZMM registers. When the source or destination operand is a memory operand, the operand must be\r\naligned on a 64-byte boundary or a general-protection exception (#GP) will be generated. To move single-precision\r\nfloating-point values to and from unaligned memory locations, use the VMOVUPD instruction.\r\nVEX.256 and EVEX.256 encoded versions:\r\nMoves 256 bits of packed double-precision floating-point values from the source operand (second operand) to the\r\ndestination operand (first operand). This instruction can be used to load a YMM register from a 256-bit memory\r\nlocation, to store the contents of a YMM register into a 256-bit memory location, or to move data between two YMM\r\nregisters. When the source or destination operand is a memory operand, the operand must be aligned on a 32-byte\r\nboundary or a general-protection exception (#GP) will be generated. To move double-precision floating-point\r\nvalues to and from unaligned memory locations, use the VMOVUPD instruction.\r\n128-bit versions:\r\nMoves 128 bits of packed double-precision floating-point values from the source operand (second operand) to the\r\ndestination operand (first operand). This instruction can be used to load an XMM register from a 128-bit memory\r\nlocation, to store the contents of an XMM register into a 128-bit memory location, or to move data between two\r\nXMM registers. When the source or destination operand is a memory operand, the operand must be aligned on a\r\n16-byte boundary or a general-protection exception (#GP) will be generated. To move single-precision floating-\r\npoint values to and from unaligned memory locations, use the VMOVUPD instruction.\r\n128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding ZMM destination register remain\r\nunchanged.\r\n(E)VEX.128 encoded version: Bits (MAX_VL-1:128) of the destination ZMM register destination are zeroed.\r\n\r\nOperation\r\nVMOVAPD (EVEX encoded versions, register-copy form)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- SRC[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE DEST[i+63:i] <- 0 ; zeroing-masking\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVMOVAPD (EVEX encoded versions, store-form)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i]<- SRC[i+63:i]\r\n ELSE\r\n ELSE *DEST[i+63:i] remains unchanged* ; merging-masking\r\n\r\n FI;\r\nENDFOR;\r\n\r\nVMOVAPD (EVEX encoded versions, load-form)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- SRC[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE DEST[i+63:i] <- 0 ; zeroing-masking\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMOVAPD (VEX.256 encoded version, load - and register copy)\r\nDEST[255:0] <- SRC[255:0]\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVMOVAPD (VEX.256 encoded version, store-form)\r\nDEST[255:0] <- SRC[255:0]\r\n\r\nVMOVAPD (VEX.128 encoded version, load - and register copy)\r\nDEST[127:0] <- SRC[127:0]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nMOVAPD (128-bit load- and register-copy- form Legacy SSE version)\r\nDEST[127:0] <- SRC[127:0]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\n(V)MOVAPD (128-bit store-form version)\r\nDEST[127:0] <- SRC[127:0]\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMOVAPD __m512d _mm512_load_pd( void * m);\r\nVMOVAPD __m512d _mm512_mask_load_pd(__m512d s, __mmask8 k, void * m);\r\nVMOVAPD __m512d _mm512_maskz_load_pd( __mmask8 k, void * m);\r\nVMOVAPD void _mm512_store_pd( void * d, __m512d a);\r\nVMOVAPD void _mm512_mask_store_pd( void * d, __mmask8 k, __m512d a);\r\nVMOVAPD __m256d _mm256_mask_load_pd(__m256d s, __mmask8 k, void * m);\r\nVMOVAPD __m256d _mm256_maskz_load_pd( __mmask8 k, void * m);\r\nVMOVAPD void _mm256_mask_store_pd( void * d, __mmask8 k, __m256d a);\r\nVMOVAPD __m128d _mm_mask_load_pd(__m128d s, __mmask8 k, void * m);\r\nVMOVAPD __m128d _mm_maskz_load_pd( __mmask8 k, void * m);\r\nVMOVAPD void _mm_mask_store_pd( void * d, __mmask8 k, __m128d a);\r\nMOVAPD __m256d _mm256_load_pd (double * p);\r\nMOVAPD void _mm256_store_pd(double * p, __m256d a);\r\nMOVAPD __m128d _mm_load_pd (double * p);\r\nMOVAPD void _mm_store_pd(double * p, __m128d a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type1.SSE2;\r\nEVEX-encoded instruction, see Exceptions Type E1.\r\n#UD If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVAPD"
},
{
"description": "MOVAPS-Move Aligned Packed Single-Precision Floating-Point Values\r\n Opcode/ Op/En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n 0F 28 /r RM V/V SSE Move aligned packed single-precision floating-point\r\n MOVAPS xmm1, xmm2/m128 values from xmm2/mem to xmm1.\r\n 0F 29 /r MR V/V SSE Move aligned packed single-precision floating-point\r\n MOVAPS xmm2/m128, xmm1 values from xmm1 to xmm2/mem.\r\n VEX.128.0F.WIG 28 /r RM V/V AVX Move aligned packed single-precision floating-point\r\n VMOVAPS xmm1, xmm2/m128 values from xmm2/mem to xmm1.\r\n VEX.128.0F.WIG 29 /r MR V/V AVX Move aligned packed single-precision floating-point\r\n VMOVAPS xmm2/m128, xmm1 values from xmm1 to xmm2/mem.\r\n VEX.256.0F.WIG 28 /r RM V/V AVX Move aligned packed single-precision floating-point\r\n VMOVAPS ymm1, ymm2/m256 values from ymm2/mem to ymm1.\r\n VEX.256.0F.WIG 29 /r MR V/V AVX Move aligned packed single-precision floating-point\r\n VMOVAPS ymm2/m256, ymm1 values from ymm1 to ymm2/mem.\r\n EVEX.128.0F.W0 28 /r FVM-RM V/V AVX512VL Move aligned packed single-precision floating-point\r\n VMOVAPS xmm1 {k1}{z}, xmm2/m128 AVX512F values from xmm2/m128 to xmm1 using\r\n writemask k1.\r\n EVEX.256.0F.W0 28 /r FVM-RM V/V AVX512VL Move aligned packed single-precision floating-point\r\n VMOVAPS ymm1 {k1}{z}, ymm2/m256 AVX512F values from ymm2/m256 to ymm1 using\r\n writemask k1.\r\n EVEX.512.0F.W0 28 /r FVM-RM V/V AVX512F Move aligned packed single-precision floating-point\r\n VMOVAPS zmm1 {k1}{z}, zmm2/m512 values from zmm2/m512 to zmm1 using\r\n writemask k1.\r\n EVEX.128.0F.W0 29 /r FVM-MR V/V AVX512VL Move aligned packed single-precision floating-point\r\n VMOVAPS xmm2/m128 {k1}{z}, xmm1 AVX512F values from xmm1 to xmm2/m128 using\r\n writemask k1.\r\n EVEX.256.0F.W0 29 /r FVM-MR V/V AVX512VL Move aligned packed single-precision floating-point\r\n VMOVAPS ymm2/m256 {k1}{z}, ymm1 AVX512F values from ymm1 to ymm2/m256 using\r\n writemask k1.\r\n EVEX.512.0F.W0 29 /r FVM-MR V/V AVX512F Move aligned packed single-precision floating-point\r\n VMOVAPS zmm2/m512 {k1}{z}, zmm1 values from zmm1 to zmm2/m512 using\r\n writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n FVM-RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n FVM-MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\nDescription\r\nMoves 4, 8 or 16 single-precision floating-point values from the source operand (second operand) to the destina-\r\ntion operand (first operand). This instruction can be used to load an XMM, YMM or ZMM register from an 128-bit,\r\n256-bit or 512-bit memory location, to store the contents of an XMM, YMM or ZMM register into a 128-bit, 256-bit\r\nor 512-bit memory location, or to move data between two XMM, two YMM or two ZMM registers.\r\nWhen the source or destination operand is a memory operand, the operand must be aligned on a 16-byte (128-bit\r\nversion), 32-byte (VEX.256 encoded version) or 64-byte (EVEX.512 encoded version) boundary or a general-\r\nprotection exception (#GP) will be generated. For EVEX.512 encoded versions, the operand must be aligned to the\r\nsize of the memory operand. To move single-precision floating-point values to and from unaligned memory loca-\r\ntions, use the VMOVUPS instruction.\r\n\r\n\r\n\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\nEVEX.512 encoded version:\r\nMoves 512 bits of packed single-precision floating-point values from the source operand (second operand) to the\r\ndestination operand (first operand). This instruction can be used to load a ZMM register from a 512-bit float32\r\nmemory location, to store the contents of a ZMM register into a float32 memory location, or to move data between\r\ntwo ZMM registers. When the source or destination operand is a memory operand, the operand must be aligned on\r\na 64-byte boundary or a general-protection exception (#GP) will be generated. To move single-precision floating-\r\npoint values to and from unaligned memory locations, use the VMOVUPS instruction.\r\nVEX.256 and EVEX.256 encoded version:\r\nMoves 256 bits of packed single-precision floating-point values from the source operand (second operand) to the\r\ndestination operand (first operand). This instruction can be used to load a YMM register from a 256-bit memory\r\nlocation, to store the contents of a YMM register into a 256-bit memory location, or to move data between two YMM\r\nregisters. When the source or destination operand is a memory operand, the operand must be aligned on a 32-byte\r\nboundary or a general-protection exception (#GP) will be generated.\r\n128-bit versions:\r\nMoves 128 bits of packed single-precision floating-point values from the source operand (second operand) to the\r\ndestination operand (first operand). This instruction can be used to load an XMM register from a 128-bit memory\r\nlocation, to store the contents of an XMM register into a 128-bit memory location, or to move data between two\r\nXMM registers. When the source or destination operand is a memory operand, the operand must be aligned on a\r\n16-byte boundary or a general-protection exception (#GP) will be generated. To move single-precision floating-\r\npoint values to and from unaligned memory locations, use the VMOVUPS instruction.\r\n128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding ZMM destination register remain\r\nunchanged.\r\n(E)VEX.128 encoded version: Bits (MAX_VL-1:128) of the destination ZMM register are zeroed.\r\n\r\nOperation\r\nVMOVAPS (EVEX encoded versions, register-copy form)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- SRC[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE DEST[i+31:i] <- 0 ; zeroing-masking\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMOVAPS (EVEX encoded versions, store-form)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i]<-\r\n SRC[i+31:i]\r\n ELSE *DEST[i+31:i] remains unchanged* ; merging-masking\r\n FI;\r\nENDFOR;\r\n\r\n\r\n\r\n\r\n\r\nVMOVAPS (EVEX encoded versions, load-form)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- SRC[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE DEST[i+31:i] <- 0 ; zeroing-masking\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMOVAPS (VEX.256 encoded version, load - and register copy)\r\nDEST[255:0] <- SRC[255:0]\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVMOVAPS (VEX.256 encoded version, store-form)\r\nDEST[255:0] <- SRC[255:0]\r\n\r\nVMOVAPS (VEX.128 encoded version, load - and register copy)\r\nDEST[127:0] <- SRC[127:0]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nMOVAPS (128-bit load- and register-copy- form Legacy SSE version)\r\nDEST[127:0] <- SRC[127:0]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\n(V)MOVAPS (128-bit store-form version)\r\nDEST[127:0] <- SRC[127:0]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMOVAPS __m512 _mm512_load_ps( void * m);\r\nVMOVAPS __m512 _mm512_mask_load_ps(__m512 s, __mmask16 k, void * m);\r\nVMOVAPS __m512 _mm512_maskz_load_ps( __mmask16 k, void * m);\r\nVMOVAPS void _mm512_store_ps( void * d, __m512 a);\r\nVMOVAPS void _mm512_mask_store_ps( void * d, __mmask16 k, __m512 a);\r\nVMOVAPS __m256 _mm256_mask_load_ps(__m256 a, __mmask8 k, void * s);\r\nVMOVAPS __m256 _mm256_maskz_load_ps( __mmask8 k, void * s);\r\nVMOVAPS void _mm256_mask_store_ps( void * d, __mmask8 k, __m256 a);\r\nVMOVAPS __m128 _mm_mask_load_ps(__m128 a, __mmask8 k, void * s);\r\nVMOVAPS __m128 _mm_maskz_load_ps( __mmask8 k, void * s);\r\nVMOVAPS void _mm_mask_store_ps( void * d, __mmask8 k, __m128 a);\r\nMOVAPS __m256 _mm256_load_ps (float * p);\r\nMOVAPS void _mm256_store_ps(float * p, __m256 a);\r\nMOVAPS __m128 _mm_load_ps (float * p);\r\nMOVAPS void _mm_store_ps(float * p, __m128 a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type1.SSE; additionally\r\n#UD If VEX.vvvv != 1111B.\r\nEVEX-encoded instruction, see Exceptions Type E1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVAPS"
},
{
"description": "MOVBE-Move Data After Swapping Bytes\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F 38 F0 /r MOVBE r16, m16 RM Valid Valid Reverse byte order in m16 and move to r16.\r\n 0F 38 F0 /r MOVBE r32, m32 RM Valid Valid Reverse byte order in m32 and move to r32.\r\n REX.W + 0F 38 F0 /r MOVBE r64, m64 RM Valid N.E. Reverse byte order in m64 and move to r64.\r\n 0F 38 F1 /r MOVBE m16, r16 MR Valid Valid Reverse byte order in r16 and move to m16.\r\n 0F 38 F1 /r MOVBE m32, r32 MR Valid Valid Reverse byte order in r32 and move to m32.\r\n REX.W + 0F 38 F1 /r MOVBE m64, r64 MR Valid N.E. Reverse byte order in r64 and move to m64.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\n\r\nDescription\r\nPerforms a byte swap operation on the data copied from the second operand (source operand) and store the result\r\nin the first operand (destination operand). The source operand can be a general-purpose register, or memory loca-\r\ntion; the destination register can be a general-purpose register, or a memory location; however, both operands can\r\nnot be registers, and only one operand can be a memory location. Both operands must be the same size, which can\r\nbe a word, a doubleword or quadword.\r\nThe MOVBE instruction is provided for swapping the bytes on a read from memory or on a write to memory; thus\r\nproviding support for converting little-endian values to big-endian format and vice versa.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-\r\ntional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the\r\nbeginning of this section for encoding data and limits.\r\n\r\nOperation\r\nTEMP <- SRC\r\n\r\nIF ( OperandSize = 16)\r\n THEN\r\n DEST[7:0] <- TEMP[15:8];\r\n DEST[15:8] <- TEMP[7:0];\r\n ELES IF ( OperandSize = 32)\r\n DEST[7:0] <- TEMP[31:24];\r\n DEST[15:8] <- TEMP[23:16];\r\n DEST[23:16] <- TEMP[15:8];\r\n DEST[31:23] <- TEMP[7:0];\r\n ELSE IF ( OperandSize = 64)\r\n DEST[7:0] <- TEMP[63:56];\r\n DEST[15:8] <- TEMP[55:48];\r\n DEST[23:16] <- TEMP[47:40];\r\n DEST[31:24] <- TEMP[39:32];\r\n DEST[39:32] <- TEMP[31:24];\r\n DEST[47:40] <- TEMP[23:16];\r\n DEST[55:48] <- TEMP[15:8];\r\n DEST[63:56] <- TEMP[7:0];\r\n\r\nFI;\r\n\r\n\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination operand is in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If CPUID.01H:ECX.MOVBE[bit 22] = 0.\r\n If the LOCK prefix is used.\r\n If REP (F3H) prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If CPUID.01H:ECX.MOVBE[bit 22] = 0.\r\n If the LOCK prefix is used.\r\n If REP (F3H) prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If CPUID.01H:ECX.MOVBE[bit 22] = 0.\r\n If the LOCK prefix is used.\r\n If REP (F3H) prefix is used.\r\n If REPNE (F2H) prefix is used and CPUID.01H:ECX.SSE4_2[bit 20] = 0.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#SS(0) If the stack address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If CPUID.01H:ECX.MOVBE[bit 22] = 0.\r\n If the LOCK prefix is used.\r\n If REP (F3H) prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVBE"
},
{
"description": "MOVD/MOVQ-Move Doubleword/Move Quadword\r\nOpcode/ Op/ En 64/32-bit CPUID Description\r\nInstruction Mode Feature\r\n Flag\r\n0F 6E /r RM V/V MMX Move doubleword from r/m32 to mm.\r\nMOVD mm, r/m32\r\nREX.W + 0F 6E /r RM V/N.E. MMX Move quadword from r/m64 to mm.\r\nMOVQ mm, r/m64\r\n0F 7E /r MR V/V MMX Move doubleword from mm to r/m32.\r\nMOVD r/m32, mm\r\nREX.W + 0F 7E /r MR V/N.E. MMX Move quadword from mm to r/m64.\r\nMOVQ r/m64, mm\r\n66 0F 6E /r RM V/V SSE2 Move doubleword from r/m32 to xmm.\r\nMOVD xmm, r/m32\r\n66 REX.W 0F 6E /r RM V/N.E. SSE2 Move quadword from r/m64 to xmm.\r\nMOVQ xmm, r/m64\r\n66 0F 7E /r MR V/V SSE2 Move doubleword from xmm register to r/m32.\r\nMOVD r/m32, xmm\r\n 66 REX.W 0F 7E /r MR V/N.E. SSE2 Move quadword from xmm register to r/m64.\r\nMOVQ r/m64, xmm\r\nVEX.128.66.0F.W0 6E / RM V/V AVX Move doubleword from r/m32 to xmm1.\r\nVMOVD xmm1, r32/m32\r\nVEX.128.66.0F.W1 6E /r RM V/N.E1. AVX Move quadword from r/m64 to xmm1.\r\nVMOVQ xmm1, r64/m64\r\nVEX.128.66.0F.W0 7E /r MR V/V AVX Move doubleword from xmm1 register to r/m32.\r\nVMOVD r32/m32, xmm1\r\nVEX.128.66.0F.W1 7E /r MR V/N.E1. AVX Move quadword from xmm1 register to r/m64.\r\nVMOVQ r64/m64, xmm1\r\nEVEX.128.66.0F.W0 6E /r T1S-RM V/V AVX512F Move doubleword from r/m32 to xmm1.\r\nVMOVD xmm1, r32/m32\r\nEVEX.128.66.0F.W1 6E /r T1S-RM V/N.E.1 AVX512F Move quadword from r/m64 to xmm1.\r\nVMOVQ xmm1, r64/m64\r\nEVEX.128.66.0F.W0 7E /r T1S-MR V/V AVX512F Move doubleword from xmm1 register to r/m32.\r\nVMOVD r32/m32, xmm1\r\nEVEX.128.66.0F.W1 7E /r T1S-MR V/N.E.1 AVX512F Move quadword from xmm1 register to r/m64.\r\nVMOVQ r64/m64, xmm1\r\n\r\nNOTES:\r\n1. For this specific instruction, VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 ver-\r\n sion is used.\r\n\r\n\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n T1S-RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n T1S-MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\n\r\nDescription\r\nCopies a doubleword from the source operand (second operand) to the destination operand (first operand). The\r\nsource and destination operands can be general-purpose registers, MMX technology registers, XMM registers, or\r\n32-bit memory locations. This instruction can be used to move a doubleword to and from the low doubleword of an\r\nMMX technology register and a general-purpose register or a 32-bit memory location, or to and from the low\r\ndoubleword of an XMM register and a general-purpose register or a 32-bit memory location. The instruction cannot\r\nbe used to transfer data between MMX technology registers, between XMM registers, between general-purpose\r\nregisters, or between memory locations.\r\nWhen the destination operand is an MMX technology register, the source operand is written to the low doubleword\r\nof the register, and the register is zero-extended to 64 bits. When the destination operand is an XMM register, the\r\nsource operand is written to the low doubleword of the register, and the register is zero-extended to 128 bits.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-\r\ntional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the\r\nbeginning of this section for encoding data and limits.\r\nMOVD/Q with XMM destination:\r\nMoves a dword/qword integer from the source operand and stores it in the low 32/64-bits of the destination XMM\r\nregister. The upper bits of the destination are zeroed. The source operand can be a 32/64-bit register or 32/64-bit\r\nmemory location.\r\n128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding YMM destination register remain\r\nunchanged. Qword operation requires the use of REX.W=1.\r\nVEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed. Qword operation requires\r\nthe use of VEX.W=1.\r\nEVEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed. Qword operation requires\r\nthe use of EVEX.W=1.\r\n\r\n\r\nMOVD/Q with 32/64 reg/mem destination:\r\nStores the low dword/qword of the source XMM register to 32/64-bit memory location or general-purpose register.\r\nQword operation requires the use of REX.W=1, VEX.W=1, or EVEX.W=1.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\nIf VMOVD or VMOVQ is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will\r\ncause an #UD exception.\r\n\r\nOperation\r\nMOVD (when destination operand is MMX technology register)\r\n DEST[31:0] <- SRC;\r\n DEST[63:32] <- 00000000H;\r\n\r\nMOVD (when destination operand is XMM register)\r\n DEST[31:0] <- SRC;\r\n DEST[127:32] <- 000000000000000000000000H;\r\n DEST[VLMAX-1:128] (Unmodified)\r\n\r\n\r\n\r\n\r\n\r\nMOVD (when source operand is MMX technology or XMM register)\r\n DEST <- SRC[31:0];\r\n\r\nVMOVD (VEX-encoded version when destination is an XMM register)\r\n DEST[31:0] <- SRC[31:0]\r\n DEST[VLMAX-1:32] <- 0\r\n\r\nMOVQ (when destination operand is XMM register)\r\n DEST[63:0] <- SRC[63:0];\r\n DEST[127:64] <- 0000000000000000H;\r\n DEST[VLMAX-1:128] (Unmodified)\r\n\r\nMOVQ (when destination operand is r/m64)\r\n DEST[63:0] <- SRC[63:0];\r\n\r\nMOVQ (when source operand is XMM register or r/m64)\r\n DEST <- SRC[63:0];\r\n\r\nVMOVQ (VEX-encoded version when destination is an XMM register)\r\n DEST[63:0] <- SRC[63:0]\r\n DEST[VLMAX-1:64] <- 0\r\n\r\nVMOVD (EVEX-encoded version when destination is an XMM register)\r\nDEST[31:0] <- SRC[31:0]\r\nDEST[511:32] <- 0H\r\n\r\nVMOVQ (EVEX-encoded version when destination is an XMM register)\r\nDEST[63:0] <- SRC[63:0]\r\nDEST[511:64] <- 0H\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nMOVD: __m64 _mm_cvtsi32_si64 (int i )\r\nMOVD: int _mm_cvtsi64_si32 ( __m64m )\r\nMOVD: __m128i _mm_cvtsi32_si128 (int a)\r\nMOVD: int _mm_cvtsi128_si32 ( __m128i a)\r\nMOVQ: __int64 _mm_cvtsi128_si64(__m128i);\r\nMOVQ: __m128i _mm_cvtsi64_si128(__int64);\r\nVMOVD __m128i _mm_cvtsi32_si128( int);\r\nVMOVD int _mm_cvtsi128_si32( __m128i );\r\nVMOVQ __m128i _mm_cvtsi64_si128 (__int64);\r\nVMOVQ __int64 _mm_cvtsi128_si64(__m128i );\r\nVMOVQ __m128i _mm_loadl_epi64( __m128i * s);\r\nVMOVQ void _mm_storel_epi64( __m128i * d, __m128i s);\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 5.\r\nEVEX-encoded instruction, see Exceptions Type E9NF.\r\n#UD If VEX.L = 1.\r\n If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVD"
},
{
"description": "MOVDDUP-Replicate Double FP Values\r\n Opcode/ Op / En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n F2 0F 12 /r RM V/V SSE3 Move double-precision floating-point value from\r\n MOVDDUP xmm1, xmm2/m64 xmm2/m64 and duplicate into xmm1.\r\n VEX.128.F2.0F.WIG 12 /r RM V/V AVX Move double-precision floating-point value from\r\n VMOVDDUP xmm1, xmm2/m64 xmm2/m64 and duplicate into xmm1.\r\n VEX.256.F2.0F.WIG 12 /r RM V/V AVX Move even index double-precision floating-point\r\n VMOVDDUP ymm1, ymm2/m256 values from ymm2/mem and duplicate each element\r\n into ymm1.\r\n EVEX.128.F2.0F.W1 12 /r DUP-RM V/V AVX512VL Move double-precision floating-point value from\r\n VMOVDDUP xmm1 {k1}{z}, AVX512F xmm2/m64 and duplicate each element into xmm1\r\n xmm2/m64 subject to writemask k1.\r\n EVEX.256.F2.0F.W1 12 /r DUP-RM V/V AVX512VL Move even index double-precision floating-point\r\n VMOVDDUP ymm1 {k1}{z}, AVX512F values from ymm2/m256 and duplicate each element\r\n ymm2/m256 into ymm1 subject to writemask k1.\r\n EVEX.512.F2.0F.W1 12 /r DUP-RM V/V AVX512F Move even index double-precision floating-point\r\n VMOVDDUP zmm1 {k1}{z}, values from zmm2/m512 and duplicate each element\r\n zmm2/m512 into zmm1 subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n DUP-RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nFor 256-bit or higher versions: Duplicates even-indexed double-precision floating-point values from the source\r\noperand (the second operand) and into adjacent pair and store to the destination operand (the first operand).\r\nFor 128-bit versions: Duplicates the low double-precision floating-point value from the source operand (the second\r\noperand) and store to the destination operand (the first operand).\r\n128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register are unchanged. The\r\nsource operand is XMM register or a 64-bit memory location.\r\nVEX.128 and EVEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed. The source\r\noperand is XMM register or a 64-bit memory location. The destination is updated conditionally under the writemask\r\nfor EVEX version.\r\nVEX.256 and EVEX.256 encoded version: Bits (MAX_VL-1:256) of the destination register are zeroed. The source\r\noperand is YMM register or a 256-bit memory location. The destination is updated conditionally under the\r\nwritemask for EVEX version.\r\nEVEX.512 encoded version: The destination is updated according to the writemask. The source operand is ZMM\r\nregister or a 512-bit memory location.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\n SRC X3 X2 X1 X0\r\n\r\n\r\n\r\n\r\n DEST X2 X2 X0 X0\r\n\r\n\r\n Figure 4-2. VMOVDDUP Operation\r\n\r\n\r\nOperation\r\nVMOVDDUP (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nTMP_SRC[63:0] <- SRC[63:0]\r\nTMP_SRC[127:64] <- SRC[63:0]\r\nIF VL >= 256\r\n TMP_SRC[191:128] <- SRC[191:128]\r\n TMP_SRC[255:192] <- SRC[191:128]\r\nFI;\r\nIF VL >= 512\r\n TMP_SRC[319:256] <- SRC[319:256]\r\n TMP_SRC[383:320] <- SRC[319:256]\r\n TMP_SRC[477:384] <- SRC[477:384]\r\n TMP_SRC[511:484] <- SRC[477:384]\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_SRC[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0 ; zeroing-masking\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMOVDDUP (VEX.256 encoded version)\r\nDEST[63:0] <-SRC[63:0]\r\nDEST[127:64] <-SRC[63:0]\r\nDEST[191:128] <-SRC[191:128]\r\nDEST[255:192] <-SRC[191:128]\r\nDEST[MAX_VL-1:256] <-0\r\n\r\nVMOVDDUP (VEX.128 encoded version)\r\nDEST[63:0] <-SRC[63:0]\r\nDEST[127:64] <-SRC[63:0]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\n\r\n\r\n\r\nMOVDDUP (128-bit Legacy SSE version)\r\nDEST[63:0] <-SRC[63:0]\r\nDEST[127:64] <-SRC[63:0]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMOVDDUP __m512d _mm512_movedup_pd( __m512d a);\r\nVMOVDDUP __m512d _mm512_mask_movedup_pd(__m512d s, __mmask8 k, __m512d a);\r\nVMOVDDUP __m512d _mm512_maskz_movedup_pd( __mmask8 k, __m512d a);\r\nVMOVDDUP __m256d _mm256_mask_movedup_pd(__m256d s, __mmask8 k, __m256d a);\r\nVMOVDDUP __m256d _mm256_maskz_movedup_pd( __mmask8 k, __m256d a);\r\nVMOVDDUP __m128d _mm_mask_movedup_pd(__m128d s, __mmask8 k, __m128d a);\r\nVMOVDDUP __m128d _mm_maskz_movedup_pd( __mmask8 k, __m128d a);\r\nMOVDDUP __m256d _mm256_movedup_pd (__m256d a);\r\nMOVDDUP __m128d _mm_movedup_pd (__m128d a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 5;\r\nEVEX-encoded instruction, see Exceptions Type E5NF.\r\n#UD If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVDDUP"
},
{
"description": "MOVDQ2Q-Move Quadword from XMM to MMX Technology Register\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n F2 0F D6 /r MOVDQ2Q mm, xmm RM Valid Valid Move low quadword from xmm to mmx\r\n register.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\n\r\nDescription\r\nMoves the low quadword from the source operand (second operand) to the destination operand (first operand).\r\nThe source operand is an XMM register and the destination operand is an MMX technology register.\r\nThis instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack\r\npointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU\r\nfloating-point exception is pending, the exception is handled before the MOVDQ2Q instruction is executed.\r\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).\r\n\r\nOperation\r\nDEST <- SRC[63:0];\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nMOVDQ2Q: __m64 _mm_movepi64_pi64 ( __m128i a)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#NM If CR0.TS[bit 3] = 1.\r\n#UD If CR0.EM[bit 2] = 1.\r\n If CR4.OSFXSR[bit 9] = 0.\r\n If CPUID.01H:EDX.SSE2[bit 26] = 0.\r\n If the LOCK prefix is used.\r\n#MF If there is a pending x87 FPU exception.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n",
"mnem": "MOVDQ2Q"
},
{
"description": "MOVDQA/VMOVDQA/VMOVDQA32/VMOVDQA64-Move Aligned Packed Integer Values\r\n Opcode/ Op/En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n 66 0F 6F /r RM V/V SSE2 Move aligned packed integer values from\r\n MOVDQA xmm1, xmm2/m128 xmm2/mem to xmm1.\r\n 66 0F 7F /r MR V/V SSE2 Move aligned packed integer values from xmm1\r\n MOVDQA xmm2/m128, xmm1 to xmm2/mem.\r\n VEX.128.66.0F.WIG 6F /r RM V/V AVX Move aligned packed integer values from\r\n VMOVDQA xmm1, xmm2/m128 xmm2/mem to xmm1.\r\n VEX.128.66.0F.WIG 7F /r MR V/V AVX Move aligned packed integer values from xmm1\r\n VMOVDQA xmm2/m128, xmm1 to xmm2/mem.\r\n VEX.256.66.0F.WIG 6F /r RM V/V AVX Move aligned packed integer values from\r\n VMOVDQA ymm1, ymm2/m256 ymm2/mem to ymm1.\r\n VEX.256.66.0F.WIG 7F /r MR V/V AVX Move aligned packed integer values from ymm1\r\n VMOVDQA ymm2/m256, ymm1 to ymm2/mem.\r\n EVEX.128.66.0F.W0 6F /r FVM-RM V/V AVX512VL Move aligned packed doubleword integer values\r\n VMOVDQA32 xmm1 {k1}{z}, AVX512F from xmm2/m128 to xmm1 using writemask\r\n xmm2/m128 k1.\r\n EVEX.256.66.0F.W0 6F /r FVM-RM V/V AVX512VL Move aligned packed doubleword integer values\r\n VMOVDQA32 ymm1 {k1}{z}, AVX512F from ymm2/m256 to ymm1 using writemask\r\n ymm2/m256 k1.\r\n EVEX.512.66.0F.W0 6F /r FVM-RM V/V AVX512F Move aligned packed doubleword integer values\r\n VMOVDQA32 zmm1 {k1}{z}, from zmm2/m512 to zmm1 using writemask k1.\r\n zmm2/m512\r\n EVEX.128.66.0F.W0 7F /r FVM-MR V/V AVX512VL Move aligned packed doubleword integer values\r\n VMOVDQA32 xmm2/m128 {k1}{z}, AVX512F from xmm1 to xmm2/m128 using writemask\r\n xmm1 k1.\r\n EVEX.256.66.0F.W0 7F /r FVM-MR V/V AVX512VL Move aligned packed doubleword integer values\r\n VMOVDQA32 ymm2/m256 {k1}{z}, AVX512F from ymm1 to ymm2/m256 using writemask\r\n ymm1 k1.\r\n EVEX.512.66.0F.W0 7F /r FVM-MR V/V AVX512F Move aligned packed doubleword integer values\r\n VMOVDQA32 zmm2/m512 {k1}{z}, from zmm1 to zmm2/m512 using writemask k1.\r\n zmm1\r\n EVEX.128.66.0F.W1 6F /r FVM-RM V/V AVX512VL Move aligned quadword integer values from\r\n VMOVDQA64 xmm1 {k1}{z}, AVX512F xmm2/m128 to xmm1 using writemask k1.\r\n xmm2/m128\r\n EVEX.256.66.0F.W1 6F /r FVM-RM V/V AVX512VL Move aligned quadword integer values from\r\n VMOVDQA64 ymm1 {k1}{z}, AVX512F ymm2/m256 to ymm1 using writemask k1.\r\n ymm2/m256\r\n EVEX.512.66.0F.W1 6F /r FVM-RM V/V AVX512F Move aligned packed quadword integer values\r\n VMOVDQA64 zmm1 {k1}{z}, from zmm2/m512 to zmm1 using writemask k1.\r\n zmm2/m512\r\n EVEX.128.66.0F.W1 7F /r FVM-MR V/V AVX512VL Move aligned packed quadword integer values\r\n VMOVDQA64 xmm2/m128 {k1}{z}, AVX512F from xmm1 to xmm2/m128 using writemask\r\n xmm1 k1.\r\n EVEX.256.66.0F.W1 7F /r FVM-MR V/V AVX512VL Move aligned packed quadword integer values\r\n VMOVDQA64 ymm2/m256 {k1}{z}, AVX512F from ymm1 to ymm2/m256 using writemask\r\n ymm1 k1.\r\n EVEX.512.66.0F.W1 7F /r FVM-MR V/V AVX512F Move aligned packed quadword integer values\r\n VMOVDQA64 zmm2/m512 {k1}{z}, from zmm1 to zmm2/m512 using writemask k1.\r\n zmm1\r\n\r\n\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n FVM-RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n FVM-MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\nDescription\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\nEVEX encoded versions:\r\nMoves 128, 256 or 512 bits of packed doubleword/quadword integer values from the source operand (the second\r\noperand) to the destination operand (the first operand). This instruction can be used to load a vector register from\r\nan int32/int64 memory location, to store the contents of a vector register into an int32/int64 memory location, or\r\nto move data between two ZMM registers. When the source or destination operand is a memory operand, the\r\noperand must be aligned on a 16 (EVEX.128)/32(EVEX.256)/64(EVEX.512)-byte boundary or a general-protection\r\nexception (#GP) will be generated. To move integer data to and from unaligned memory locations, use the\r\nVMOVDQU instruction.\r\nThe destination operand is updated at 32-bit (VMOVDQA32) or 64-bit (VMOVDQA64) granularity according to the\r\nwritemask.\r\nVEX.256 encoded version:\r\nMoves 256 bits of packed integer values from the source operand (second operand) to the destination operand\r\n(first operand). This instruction can be used to load a YMM register from a 256-bit memory location, to store the\r\ncontents of a YMM register into a 256-bit memory location, or to move data between two YMM registers.\r\nWhen the source or destination operand is a memory operand, the operand must be aligned on a 32-byte boundary\r\nor a general-protection exception (#GP) will be generated. To move integer data to and from unaligned memory\r\nlocations, use the VMOVDQU instruction. Bits (MAX_VL-1:256) of the destination register are zeroed.\r\n128-bit versions:\r\nMoves 128 bits of packed integer values from the source operand (second operand) to the destination operand\r\n(first operand). This instruction can be used to load an XMM register from a 128-bit memory location, to store the\r\ncontents of an XMM register into a 128-bit memory location, or to move data between two XMM registers.\r\nWhen the source or destination operand is a memory operand, the operand must be aligned on a 16-byte boundary\r\nor a general-protection exception (#GP) will be generated. To move integer data to and from unaligned memory\r\nlocations, use the VMOVDQU instruction.\r\n128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding ZMM destination register remain\r\nunchanged.\r\nVEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVMOVDQA32 (EVEX encoded versions, register-copy form)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- SRC[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE DEST[i+31:i] <- 0 ; zeroing-masking\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMOVDQA32 (EVEX encoded versions, store-form)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i]<- SRC[i+31:i]\r\n ELSE *DEST[i+31:i] remains unchanged* ; merging-masking\r\n FI;\r\nENDFOR;\r\n\r\nVMOVDQA32 (EVEX encoded versions, load-form)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- SRC[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE DEST[i+31:i] <- 0 ; zeroing-masking\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVMOVDQA64 (EVEX encoded versions, register-copy form)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- SRC[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE DEST[i+63:i] <- 0 ; zeroing-masking\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMOVDQA64 (EVEX encoded versions, store-form)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i]<- SRC[i+63:i]\r\n ELSE *DEST[i+63:i] remains unchanged* ; merging-masking\r\n FI;\r\nENDFOR;\r\n\r\nVMOVDQA64 (EVEX encoded versions, load-form)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- SRC[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE DEST[i+63:i] <- 0 ; zeroing-masking\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMOVDQA (VEX.256 encoded version, load - and register copy)\r\nDEST[255:0] <- SRC[255:0]\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVMOVDQA (VEX.256 encoded version, store-form)\r\nDEST[255:0] <- SRC[255:0]\r\nVMOVDQA (VEX.128 encoded version)\r\nDEST[127:0] <- SRC[127:0]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVMOVDQA (128-bit load- and register-copy- form Legacy SSE version)\r\nDEST[127:0] <- SRC[127:0]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\n\r\n\r\n\r\n(V)MOVDQA (128-bit store-form version)\r\nDEST[127:0] <- SRC[127:0]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMOVDQA32 __m512i _mm512_load_epi32( void * sa);\r\nVMOVDQA32 __m512i _mm512_mask_load_epi32(__m512i s, __mmask16 k, void * sa);\r\nVMOVDQA32 __m512i _mm512_maskz_load_epi32( __mmask16 k, void * sa);\r\nVMOVDQA32 void _mm512_store_epi32(void * d, __m512i a);\r\nVMOVDQA32 void _mm512_mask_store_epi32(void * d, __mmask16 k, __m512i a);\r\nVMOVDQA32 __m256i _mm256_mask_load_epi32(__m256i s, __mmask8 k, void * sa);\r\nVMOVDQA32 __m256i _mm256_maskz_load_epi32( __mmask8 k, void * sa);\r\nVMOVDQA32 void _mm256_store_epi32(void * d, __m256i a);\r\nVMOVDQA32 void _mm256_mask_store_epi32(void * d, __mmask8 k, __m256i a);\r\nVMOVDQA32 __m128i _mm_mask_load_epi32(__m128i s, __mmask8 k, void * sa);\r\nVMOVDQA32 __m128i _mm_maskz_load_epi32( __mmask8 k, void * sa);\r\nVMOVDQA32 void _mm_store_epi32(void * d, __m128i a);\r\nVMOVDQA32 void _mm_mask_store_epi32(void * d, __mmask8 k, __m128i a);\r\nVMOVDQA64 __m512i _mm512_load_epi64( void * sa);\r\nVMOVDQA64 __m512i _mm512_mask_load_epi64(__m512i s, __mmask8 k, void * sa);\r\nVMOVDQA64 __m512i _mm512_maskz_load_epi64( __mmask8 k, void * sa);\r\nVMOVDQA64 void _mm512_store_epi64(void * d, __m512i a);\r\nVMOVDQA64 void _mm512_mask_store_epi64(void * d, __mmask8 k, __m512i a);\r\nVMOVDQA64 __m256i _mm256_mask_load_epi64(__m256i s, __mmask8 k, void * sa);\r\nVMOVDQA64 __m256i _mm256_maskz_load_epi64( __mmask8 k, void * sa);\r\nVMOVDQA64 void _mm256_store_epi64(void * d, __m256i a);\r\nVMOVDQA64 void _mm256_mask_store_epi64(void * d, __mmask8 k, __m256i a);\r\nVMOVDQA64 __m128i _mm_mask_load_epi64(__m128i s, __mmask8 k, void * sa);\r\nVMOVDQA64 __m128i _mm_maskz_load_epi64( __mmask8 k, void * sa);\r\nVMOVDQA64 void _mm_store_epi64(void * d, __m128i a);\r\nVMOVDQA64 void _mm_mask_store_epi64(void * d, __mmask8 k, __m128i a);\r\nMOVDQA void __m256i _mm256_load_si256 (__m256i * p);\r\nMOVDQA _mm256_store_si256(_m256i *p, __m256i a);\r\nMOVDQA __m128i _mm_load_si128 (__m128i * p);\r\nMOVDQA void _mm_store_si128(__m128i *p, __m128i a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type1.SSE2;\r\nEVEX-encoded instruction, see Exceptions Type E1.\r\n#UD If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVDQA"
},
{
"description": "MOVDQU/VMOVDQU/VMOVDQU8/VMOVDQU16/VMOVDQU32/VMOVDQU64-Move Unaligned Packed Integer Values\r\n Opcode/ Op/En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n F3 0F 6F /r RM V/V SSE2 Move unaligned packed integer values from\r\n MOVDQU xmm1, xmm2/m128 xmm2/m128 to xmm1.\r\n F3 0F 7F /r MR V/V SSE2 Move unaligned packed integer values from\r\n MOVDQU xmm2/m128, xmm1 xmm1 to xmm2/m128.\r\n VEX.128.F3.0F.WIG 6F /r RM V/V AVX Move unaligned packed integer values from\r\n VMOVDQU xmm1, xmm2/m128 xmm2/m128 to xmm1.\r\n VEX.128.F3.0F.WIG 7F /r MR V/V AVX Move unaligned packed integer values from\r\n VMOVDQU xmm2/m128, xmm1 xmm1 to xmm2/m128.\r\n VEX.256.F3.0F.WIG 6F /r RM V/V AVX Move unaligned packed integer values from\r\n VMOVDQU ymm1, ymm2/m256 ymm2/m256 to ymm1.\r\n VEX.256.F3.0F.WIG 7F /r MR V/V AVX Move unaligned packed integer values from\r\n VMOVDQU ymm2/m256, ymm1 ymm1 to ymm2/m256.\r\n EVEX.128.F2.0F.W0 6F /r FVM-RM V/V AVX512VL Move unaligned packed byte integer values\r\n VMOVDQU8 xmm1 {k1}{z}, xmm2/m128 AVX512BW from xmm2/m128 to xmm1 using writemask\r\n k1.\r\n EVEX.256.F2.0F.W0 6F /r FVM-RM V/V AVX512VL Move unaligned packed byte integer values\r\n VMOVDQU8 ymm1 {k1}{z}, ymm2/m256 AVX512BW from ymm2/m256 to ymm1 using writemask\r\n k1.\r\n EVEX.512.F2.0F.W0 6F /r FVM-RM V/V AVX512BW Move unaligned packed byte integer values\r\n VMOVDQU8 zmm1 {k1}{z}, zmm2/m512 from zmm2/m512 to zmm1 using writemask\r\n k1.\r\n EVEX.128.F2.0F.W0 7F /r FVM-MR V/V AVX512VL Move unaligned packed byte integer values\r\n VMOVDQU8 xmm2/m128 {k1}{z}, xmm1 AVX512BW from xmm1 to xmm2/m128 using writemask\r\n k1.\r\n EVEX.256.F2.0F.W0 7F /r FVM-MR V/V AVX512VL Move unaligned packed byte integer values\r\n VMOVDQU8 ymm2/m256 {k1}{z}, ymm1 AVX512BW from ymm1 to ymm2/m256 using writemask\r\n k1.\r\n EVEX.512.F2.0F.W0 7F /r FVM-MR V/V AVX512BW Move unaligned packed byte integer values\r\n VMOVDQU8 zmm2/m512 {k1}{z}, zmm1 from zmm1 to zmm2/m512 using writemask\r\n k1.\r\n EVEX.128.F2.0F.W1 6F /r FVM-RM V/V AVX512VL Move unaligned packed word integer values\r\n VMOVDQU16 xmm1 {k1}{z}, xmm2/m128 AVX512BW from xmm2/m128 to xmm1 using writemask\r\n k1.\r\n EVEX.256.F2.0F.W1 6F /r FVM-RM V/V AVX512VL Move unaligned packed word integer values\r\n VMOVDQU16 ymm1 {k1}{z}, ymm2/m256 AVX512BW from ymm2/m256 to ymm1 using writemask\r\n k1.\r\n EVEX.512.F2.0F.W1 6F /r FVM-RM V/V AVX512BW Move unaligned packed word integer values\r\n VMOVDQU16 zmm1 {k1}{z}, zmm2/m512 from zmm2/m512 to zmm1 using writemask\r\n k1.\r\n EVEX.128.F2.0F.W1 7F /r FVM-MR V/V AVX512VL Move unaligned packed word integer values\r\n VMOVDQU16 xmm2/m128 {k1}{z}, xmm1 AVX512BW from xmm1 to xmm2/m128 using writemask\r\n k1.\r\n EVEX.256.F2.0F.W1 7F /r FVM-MR V/V AVX512VL Move unaligned packed word integer values\r\n VMOVDQU16 ymm2/m256 {k1}{z}, ymm1 AVX512BW from ymm1 to ymm2/m256 using writemask\r\n k1.\r\n EVEX.512.F2.0F.W1 7F /r FVM-MR V/V AVX512BW Move unaligned packed word integer values\r\n VMOVDQU16 zmm2/m512 {k1}{z}, zmm1 from zmm1 to zmm2/m512 using writemask\r\n k1.\r\n EVEX.128.F3.0F.W0 6F /r FVM-RM V/V AVX512VL Move unaligned packed doubleword integer\r\n VMOVDQU32 xmm1 {k1}{z}, AVX512F values from xmm2/m128 to xmm1 using\r\n xmm2/mm128 writemask k1.\r\n\r\n\r\n Opcode/ Op/En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n EVEX.256.F3.0F.W0 6F /r FVM-RM V/V AVX512VL Move unaligned packed doubleword integer\r\n VMOVDQU32 ymm1 {k1}{z}, ymm2/m256 AVX512F values from ymm2/m256 to ymm1 using\r\n writemask k1.\r\n EVEX.512.F3.0F.W0 6F /r FVM-RM V/V AVX512F Move unaligned packed doubleword integer\r\n VMOVDQU32 zmm1 {k1}{z}, zmm2/m512 values from zmm2/m512 to zmm1 using\r\n writemask k1.\r\n EVEX.128.F3.0F.W0 7F /r FVM-MR V/V AVX512VL Move unaligned packed doubleword integer\r\n VMOVDQU32 xmm2/m128 {k1}{z}, xmm1 AVX512F values from xmm1 to xmm2/m128 using\r\n writemask k1.\r\n EVEX.256.F3.0F.W0 7F /r FVM-MR V/V AVX512VL Move unaligned packed doubleword integer\r\n VMOVDQU32 ymm2/m256 {k1}{z}, ymm1 AVX512F values from ymm1 to ymm2/m256 using\r\n writemask k1.\r\n EVEX.512.F3.0F.W0 7F /r FVM-MR V/V AVX512F Move unaligned packed doubleword integer\r\n VMOVDQU32 zmm2/m512 {k1}{z}, zmm1 values from zmm1 to zmm2/m512 using\r\n writemask k1.\r\n EVEX.128.F3.0F.W1 6F /r FVM-RM V/V AVX512VL Move unaligned packed quadword integer\r\n VMOVDQU64 xmm1 {k1}{z}, xmm2/m128 AVX512F values from xmm2/m128 to xmm1 using\r\n writemask k1.\r\n EVEX.256.F3.0F.W1 6F /r FVM-RM V/V AVX512VL Move unaligned packed quadword integer\r\n VMOVDQU64 ymm1 {k1}{z}, ymm2/m256 AVX512F values from ymm2/m256 to ymm1 using\r\n writemask k1.\r\n EVEX.512.F3.0F.W1 6F /r FVM-RM V/V AVX512F Move unaligned packed quadword integer\r\n VMOVDQU64 zmm1 {k1}{z}, zmm2/m512 values from zmm2/m512 to zmm1 using\r\n writemask k1.\r\n EVEX.128.F3.0F.W1 7F /r FVM-MR V/V AVX512VL Move unaligned packed quadword integer\r\n VMOVDQU64 xmm2/m128 {k1}{z}, xmm1 AVX512F values from xmm1 to xmm2/m128 using\r\n writemask k1.\r\n EVEX.256.F3.0F.W1 7F /r FVM-MR V/V AVX512VL Move unaligned packed quadword integer\r\n VMOVDQU64 ymm2/m256 {k1}{z}, ymm1 AVX512F values from ymm1 to ymm2/m256 using\r\n writemask k1.\r\n EVEX.512.F3.0F.W1 7F /r FVM-MR V/V AVX512F Move unaligned packed quadword integer\r\n VMOVDQU64 zmm2/m512 {k1}{z}, zmm1 values from zmm1 to zmm2/m512 using\r\n writemask k1.\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n FVM-RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n FVM-MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\nDescription\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\nEVEX encoded versions:\r\nMoves 128, 256 or 512 bits of packed byte/word/doubleword/quadword integer values from the source operand\r\n(the second operand) to the destination operand (first operand). This instruction can be used to load a vector\r\nregister from a memory location, to store the contents of a vector register into a memory location, or to move data\r\nbetween two vector registers.\r\n\r\n\r\n\r\n\r\nThe destination operand is updated at 8-bit (VMOVDQU8), 16-bit (VMOVDQU16), 32-bit (VMOVDQU32), or 64-bit\r\n(VMOVDQU64) granularity according to the writemask.\r\nVEX.256 encoded version:\r\nMoves 256 bits of packed integer values from the source operand (second operand) to the destination operand\r\n(first operand). This instruction can be used to load a YMM register from a 256-bit memory location, to store the\r\ncontents of a YMM register into a 256-bit memory location, or to move data between two YMM registers.\r\nBits (MAX_VL-1:256) of the destination register are zeroed.\r\n\r\n\r\n128-bit versions:\r\nMoves 128 bits of packed integer values from the source operand (second operand) to the destination operand\r\n(first operand). This instruction can be used to load an XMM register from a 128-bit memory location, to store the\r\ncontents of an XMM register into a 128-bit memory location, or to move data between two XMM registers.\r\n128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register remain unchanged.\r\nWhen the source or destination operand is a memory operand, the operand may be unaligned to any alignment\r\nwithout causing a general-protection exception (#GP) to be generated\r\nVEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed.\r\n\r\nOperation\r\nVMOVDQU8 (EVEX encoded versions, register-copy form)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\nFOR j <- 0 TO KL-1\r\n i<-j*8\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- SRC[i+7:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE DEST[i+7:i] <- 0 ; zeroing-masking\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMOVDQU8 (EVEX encoded versions, store-form)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\nFOR j <- 0 TO KL-1\r\n i<-j*8\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i]<-\r\n SRC[i+7:i]\r\n ELSE *DEST[i+7:i] remains unchanged* ; merging-masking\r\n FI;\r\nENDFOR;\r\n\r\n\r\n\r\n\r\n\r\nVMOVDQU8 (EVEX encoded versions, load-form)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\nFOR j <- 0 TO KL-1\r\n i<-j*8\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- SRC[i+7:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE DEST[i+7:i] <- 0 ; zeroing-masking\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMOVDQU16 (EVEX encoded versions, register-copy form)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- SRC[i+15:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE DEST[i+15:i] <- 0 ; zeroing-masking\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMOVDQU16 (EVEX encoded versions, store-form)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i]<-\r\n SRC[i+15:i]\r\n ELSE *DEST[i+15:i] remains unchanged* ; merging-masking\r\n FI;\r\nENDFOR;\r\n\r\n\r\n\r\n\r\n\r\nVMOVDQU16 (EVEX encoded versions, load-form)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- SRC[i+15:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE DEST[i+15:i] <- 0 ; zeroing-masking\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMOVDQU32 (EVEX encoded versions, register-copy form)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- SRC[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE DEST[i+31:i] <- 0 ; zeroing-masking\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMOVDQU32 (EVEX encoded versions, store-form)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i]<-\r\n SRC[i+31:i]\r\n ELSE *DEST[i+31:i] remains unchanged* ; merging-masking\r\n FI;\r\nENDFOR;\r\n\r\n\r\n\r\n\r\n\r\nVMOVDQU32 (EVEX encoded versions, load-form)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- SRC[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE DEST[i+31:i] <- 0 ; zeroing-masking\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMOVDQU64 (EVEX encoded versions, register-copy form)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- SRC[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE DEST[i+63:i] <- 0 ; zeroing-masking\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMOVDQU64 (EVEX encoded versions, store-form)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i]<- SRC[i+63:i]\r\n ELSE *DEST[i+63:i] remains unchanged* ; merging-masking\r\n\r\n FI;\r\nENDFOR;\r\n\r\n\r\n\r\n\r\n\r\nVMOVDQU64 (EVEX encoded versions, load-form)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- SRC[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE DEST[i+63:i] <- 0 ; zeroing-masking\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMOVDQU (VEX.256 encoded version, load - and register copy)\r\nDEST[255:0] <- SRC[255:0]\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVMOVDQU (VEX.256 encoded version, store-form)\r\nDEST[255:0] <- SRC[255:0]\r\n\r\nVMOVDQU (VEX.128 encoded version)\r\nDEST[127:0] <- SRC[127:0]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVMOVDQU (128-bit load- and register-copy- form Legacy SSE version)\r\nDEST[127:0] <- SRC[127:0]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\n(V)MOVDQU (128-bit store-form version)\r\nDEST[127:0] <- SRC[127:0]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMOVDQU16 __m512i _mm512_mask_loadu_epi16(__m512i s, __mmask32 k, void * sa);\r\nVMOVDQU16 __m512i _mm512_maskz_loadu_epi16( __mmask32 k, void * sa);\r\nVMOVDQU16 void _mm512_mask_storeu_epi16(void * d, __mmask32 k, __m512i a);\r\nVMOVDQU16 __m256i _mm256_mask_loadu_epi16(__m256i s, __mmask16 k, void * sa);\r\nVMOVDQU16 __m256i _mm256_maskz_loadu_epi16( __mmask16 k, void * sa);\r\nVMOVDQU16 void _mm256_mask_storeu_epi16(void * d, __mmask16 k, __m256i a);\r\nVMOVDQU16 void _mm256_maskz_storeu_epi16(void * d, __mmask16 k);\r\nVMOVDQU16 __m128i _mm_mask_loadu_epi16(__m128i s, __mmask8 k, void * sa);\r\nVMOVDQU16 __m128i _mm_maskz_loadu_epi16( __mmask8 k, void * sa);\r\nVMOVDQU16 void _mm_mask_storeu_epi16(void * d, __mmask8 k, __m128i a);\r\nVMOVDQU32 __m512i _mm512_loadu_epi32( void * sa);\r\nVMOVDQU32 __m512i _mm512_mask_loadu_epi32(__m512i s, __mmask16 k, void * sa);\r\nVMOVDQU32 __m512i _mm512_maskz_loadu_epi32( __mmask16 k, void * sa);\r\nVMOVDQU32 void _mm512_storeu_epi32(void * d, __m512i a);\r\nVMOVDQU32 void _mm512_mask_storeu_epi32(void * d, __mmask16 k, __m512i a);\r\nVMOVDQU32 __m256i _mm256_mask_loadu_epi32(__m256i s, __mmask8 k, void * sa);\r\nVMOVDQU32 __m256i _mm256_maskz_loadu_epi32( __mmask8 k, void * sa);\r\nVMOVDQU32 void _mm256_storeu_epi32(void * d, __m256i a);\r\nVMOVDQU32 void _mm256_mask_storeu_epi32(void * d, __mmask8 k, __m256i a);\r\nVMOVDQU32 __m128i _mm_mask_loadu_epi32(__m128i s, __mmask8 k, void * sa);\r\n\r\n\r\n\r\nVMOVDQU32 __m128i _mm_maskz_loadu_epi32( __mmask8 k, void * sa);\r\nVMOVDQU32 void _mm_storeu_epi32(void * d, __m128i a);\r\nVMOVDQU32 void _mm_mask_storeu_epi32(void * d, __mmask8 k, __m128i a);\r\nVMOVDQU64 __m512i _mm512_loadu_epi64( void * sa);\r\nVMOVDQU64 __m512i _mm512_mask_loadu_epi64(__m512i s, __mmask8 k, void * sa);\r\nVMOVDQU64 __m512i _mm512_maskz_loadu_epi64( __mmask8 k, void * sa);\r\nVMOVDQU64 void _mm512_storeu_epi64(void * d, __m512i a);\r\nVMOVDQU64 void _mm512_mask_storeu_epi64(void * d, __mmask8 k, __m512i a);\r\nVMOVDQU64 __m256i _mm256_mask_loadu_epi64(__m256i s, __mmask8 k, void * sa);\r\nVMOVDQU64 __m256i _mm256_maskz_loadu_epi64( __mmask8 k, void * sa);\r\nVMOVDQU64 void _mm256_storeu_epi64(void * d, __m256i a);\r\nVMOVDQU64 void _mm256_mask_storeu_epi64(void * d, __mmask8 k, __m256i a);\r\nVMOVDQU64 __m128i _mm_mask_loadu_epi64(__m128i s, __mmask8 k, void * sa);\r\nVMOVDQU64 __m128i _mm_maskz_loadu_epi64( __mmask8 k, void * sa);\r\nVMOVDQU64 void _mm_storeu_epi64(void * d, __m128i a);\r\nVMOVDQU64 void _mm_mask_storeu_epi64(void * d, __mmask8 k, __m128i a);\r\nVMOVDQU8 __m512i _mm512_mask_loadu_epi8(__m512i s, __mmask64 k, void * sa);\r\nVMOVDQU8 __m512i _mm512_maskz_loadu_epi8( __mmask64 k, void * sa);\r\nVMOVDQU8 void _mm512_mask_storeu_epi8(void * d, __mmask64 k, __m512i a);\r\nVMOVDQU8 __m256i _mm256_mask_loadu_epi8(__m256i s, __mmask32 k, void * sa);\r\nVMOVDQU8 __m256i _mm256_maskz_loadu_epi8( __mmask32 k, void * sa);\r\nVMOVDQU8 void _mm256_mask_storeu_epi8(void * d, __mmask32 k, __m256i a);\r\nVMOVDQU8 void _mm256_maskz_storeu_epi8(void * d, __mmask32 k);\r\nVMOVDQU8 __m128i _mm_mask_loadu_epi8(__m128i s, __mmask16 k, void * sa);\r\nVMOVDQU8 __m128i _mm_maskz_loadu_epi8( __mmask16 k, void * sa);\r\nVMOVDQU8 void _mm_mask_storeu_epi8(void * d, __mmask16 k, __m128i a);\r\nMOVDQU __m256i _mm256_loadu_si256 (__m256i * p);\r\nMOVDQU _mm256_storeu_si256(_m256i *p, __m256i a);\r\nMOVDQU __m128i _mm_loadu_si128 (__m128i * p);\r\nMOVDQU _mm_storeu_si128(__m128i *p, __m128i a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4;\r\nEVEX-encoded instruction, see Exceptions Type E4.nb.\r\n#UD If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVDQU"
},
{
"description": "MOVHLPS-Move Packed Single-Precision Floating-Point Values High to Low\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 0F 12 /r RM V/V SSE Move two packed single-precision floating-point values\r\n MOVHLPS xmm1, xmm2 from high quadword of xmm2 to low quadword of xmm1.\r\n VEX.NDS.128.0F.WIG 12 /r RVM V/V AVX Merge two packed single-precision floating-point values\r\n VMOVHLPS xmm1, xmm2, xmm3 from high quadword of xmm3 and low quadword of xmm2.\r\n EVEX.NDS.128.0F.W0 12 /r RVM V/V AVX512F Merge two packed single-precision floating-point values\r\n VMOVHLPS xmm1, xmm2, xmm3 from high quadword of xmm3 and low quadword of xmm2.\r\n\r\n\r\n\r\n Instruction Operand Encoding1\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nThis instruction cannot be used for memory to register moves.\r\n128-bit two-argument form:\r\nMoves two packed single-precision floating-point values from the high quadword of the second XMM argument\r\n(second operand) to the low quadword of the first XMM register (first argument). The quadword at bits 127:64 of\r\nthe destination operand is left unchanged. Bits (MAX_VL-1:128) of the corresponding destination register remain\r\nunchanged.\r\n128-bit and EVEX three-argument form\r\nMoves two packed single-precision floating-point values from the high quadword of the third XMM argument (third\r\noperand) to the low quadword of the destination (first operand). Copies the high quadword from the second XMM\r\nargument (second operand) to the high quadword of the destination (first operand). Bits (MAX_VL-1:128) of the\r\ncorresponding destination register are zeroed.\r\nIf VMOVHLPS is encoded with VEX.L or EVEX.L'L= 1, an attempt to execute the instruction encoded with VEX.L or\r\nEVEX.L'L= 1 will cause an #UD exception.\r\n\r\nOperation\r\nMOVHLPS (128-bit two-argument form)\r\nDEST[63:0] <- SRC[127:64]\r\nDEST[MAX_VL-1:64] (Unmodified)\r\n\r\nVMOVHLPS (128-bit three-argument form - VEX & EVEX)\r\nDEST[63:0] <- SRC2[127:64]\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nMOVHLPS __m128 _mm_movehl_ps(__m128 a, __m128 b)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\n1. ModRM.MOD = 011B required\r\n\r\n\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 7; additionally\r\n#UD If VEX.L = 1.\r\nEVEX-encoded instruction, see Exceptions Type E7NM.128.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVHLPS"
},
{
"description": "MOVHPD-Move High Packed Double-Precision Floating-Point Value\r\n Opcode/ Op / En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n 66 0F 16 /r RM V/V SSE2 Move double-precision floating-point value from m64\r\n MOVHPD xmm1, m64 to high quadword of xmm1.\r\n VEX.NDS.128.66.0F.WIG 16 /r RVM V/V AVX Merge double-precision floating-point value from m64\r\n VMOVHPD xmm2, xmm1, m64 and the low quadword of xmm1.\r\n EVEX.NDS.128.66.0F.W1 16 /r T1S V/V AVX512F Merge double-precision floating-point value from m64\r\n VMOVHPD xmm2, xmm1, m64 and the low quadword of xmm1.\r\n 66 0F 17 /r MR V/V SSE2 Move double-precision floating-point value from high\r\n MOVHPD m64, xmm1 quadword of xmm1 to m64.\r\n VEX.128.66.0F.WIG 17 /r MR V/V AVX Move double-precision floating-point value from high\r\n VMOVHPD m64, xmm1 quadword of xmm1 to m64.\r\n EVEX.128.66.0F.W1 17 /r T1S-MR V/V AVX512F Move double-precision floating-point value from high\r\n VMOVHPD m64, xmm1 quadword of xmm1 to m64.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n T1S ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n T1S-MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\nDescription\r\nThis instruction cannot be used for register to register or memory to memory moves.\r\n128-bit Legacy SSE load:\r\nMoves a double-precision floating-point value from the source 64-bit memory operand and stores it in the high 64-\r\nbits of the destination XMM register. The lower 64bits of the XMM register are preserved. Bits (MAX_VL-1:128) of\r\nthe corresponding destination register are preserved.\r\nVEX.128 & EVEX encoded load:\r\nLoads a double-precision floating-point value from the source 64-bit memory operand (the third operand) and\r\nstores it in the upper 64-bits of the destination XMM register (first operand). The low 64-bits from the first source\r\noperand (second operand) are copied to the low 64-bits of the destination. Bits (MAX_VL-1:128) of the corre-\r\nsponding destination register are zeroed.\r\n128-bit store:\r\nStores a double-precision floating-point value from the high 64-bits of the XMM register source (second operand)\r\nto the 64-bit memory location (first operand).\r\nNote: VMOVHPD (store) (VEX.128.66.0F 17 /r) is legal and has the same behavior as the existing 66 0F 17 store.\r\nFor VMOVHPD (store) VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will #UD.\r\nIf VMOVHPD is encoded with VEX.L or EVEX.L'L= 1, an attempt to execute the instruction encoded with VEX.L or\r\nEVEX.L'L= 1 will cause an #UD exception.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nMOVHPD (128-bit Legacy SSE load)\r\nDEST[63:0] (Unmodified)\r\nDEST[127:64] <- SRC[63:0]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVMOVHPD (VEX.128 & EVEX encoded load)\r\nDEST[63:0] <- SRC1[63:0]\r\nDEST[127:64] <- SRC2[63:0]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVMOVHPD (store)\r\nDEST[63:0] <- SRC[127:64]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nMOVHPD __m128d _mm_loadh_pd ( __m128d a, double *p)\r\nMOVHPD void _mm_storeh_pd (double *p, __m128d a)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 5; additionally\r\n#UD If VEX.L = 1.\r\nEVEX-encoded instruction, see Exceptions Type E9NF.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVHPD"
},
{
"description": "MOVHPS-Move High Packed Single-Precision Floating-Point Values\r\n Opcode/ Op / En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n 0F 16 /r RM V/V SSE Move two packed single-precision floating-point values\r\n MOVHPS xmm1, m64 from m64 to high quadword of xmm1.\r\n VEX.NDS.128.0F.WIG 16 /r RVM V/V AVX Merge two packed single-precision floating-point values\r\n VMOVHPS xmm2, xmm1, m64 from m64 and the low quadword of xmm1.\r\n EVEX.NDS.128.0F.W0 16 /r T2 V/V AVX512F Merge two packed single-precision floating-point values\r\n VMOVHPS xmm2, xmm1, m64 from m64 and the low quadword of xmm1.\r\n 0F 17 /r MR V/V SSE Move two packed single-precision floating-point values\r\n MOVHPS m64, xmm1 from high quadword of xmm1 to m64.\r\n VEX.128.0F.WIG 17 /r MR V/V AVX Move two packed single-precision floating-point values\r\n VMOVHPS m64, xmm1 from high quadword of xmm1 to m64.\r\n EVEX.128.0F.W0 17 /r T2-MR V/V AVX512F Move two packed single-precision floating-point values\r\n VMOVHPS m64, xmm1 from high quadword of xmm1 to m64.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n T2 ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n T2-MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\nDescription\r\nThis instruction cannot be used for register to register or memory to memory moves.\r\n128-bit Legacy SSE load:\r\nMoves two packed single-precision floating-point values from the source 64-bit memory operand and stores them\r\nin the high 64-bits of the destination XMM register. The lower 64bits of the XMM register are preserved. Bits\r\n(MAX_VL-1:128) of the corresponding destination register are preserved.\r\nVEX.128 & EVEX encoded load:\r\nLoads two single-precision floating-point values from the source 64-bit memory operand (the third operand) and\r\nstores it in the upper 64-bits of the destination XMM register (first operand). The low 64-bits from the first source\r\noperand (the second operand) are copied to the lower 64-bits of the destination. Bits (MAX_VL-1:128) of the corre-\r\nsponding destination register are zeroed.\r\n128-bit store:\r\nStores two packed single-precision floating-point values from the high 64-bits of the XMM register source (second\r\noperand) to the 64-bit memory location (first operand).\r\nNote: VMOVHPS (store) (VEX.NDS.128.0F 17 /r) is legal and has the same behavior as the existing 0F 17 store.\r\nFor VMOVHPS (store) VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will #UD.\r\nIf VMOVHPS is encoded with VEX.L or EVEX.L'L= 1, an attempt to execute the instruction encoded with VEX.L or\r\nEVEX.L'L= 1 will cause an #UD exception.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nMOVHPS (128-bit Legacy SSE load)\r\nDEST[63:0] (Unmodified)\r\nDEST[127:64] <- SRC[63:0]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVMOVHPS (VEX.128 and EVEX encoded load)\r\nDEST[63:0] <- SRC1[63:0]\r\nDEST[127:64] <- SRC2[63:0]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVMOVHPS (store)\r\nDEST[63:0] <- SRC[127:64]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nMOVHPS __m128 _mm_loadh_pi ( __m128 a, __m64 *p)\r\nMOVHPS void _mm_storeh_pi (__m64 *p, __m128 a)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 5; additionally\r\n#UD If VEX.L = 1.\r\nEVEX-encoded instruction, see Exceptions Type E9NF.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVHPS"
},
{
"description": "MOVLHPS-Move Packed Single-Precision Floating-Point Values Low to High\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 0F 16 /r RM V/V SSE Move two packed single-precision floating-point values from\r\n MOVLHPS xmm1, xmm2 low quadword of xmm2 to high quadword of xmm1.\r\n VEX.NDS.128.0F.WIG 16 /r RVM V/V AVX Merge two packed single-precision floating-point values\r\n VMOVLHPS xmm1, xmm2, xmm3 from low quadword of xmm3 and low quadword of xmm2.\r\n EVEX.NDS.128.0F.W0 16 /r RVM V/V AVX512F Merge two packed single-precision floating-point values\r\n VMOVLHPS xmm1, xmm2, xmm3 from low quadword of xmm3 and low quadword of xmm2.\r\n\r\n\r\n\r\n Instruction Operand Encoding1\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nThis instruction cannot be used for memory to register moves.\r\n128-bit two-argument form:\r\nMoves two packed single-precision floating-point values from the low quadword of the second XMM argument\r\n(second operand) to the high quadword of the first XMM register (first argument). The low quadword of the desti-\r\nnation operand is left unchanged. Bits (MAX_VL-1:128) of the corresponding destination register are unmodified.\r\n128-bit three-argument forms:\r\nMoves two packed single-precision floating-point values from the low quadword of the third XMM argument (third\r\noperand) to the high quadword of the destination (first operand). Copies the low quadword from the second XMM\r\nargument (second operand) to the low quadword of the destination (first operand). Bits (MAX_VL-1:128) of the\r\ncorresponding destination register are zeroed.\r\nIf VMOVLHPS is encoded with VEX.L or EVEX.L'L= 1, an attempt to execute the instruction encoded with VEX.L or\r\nEVEX.L'L= 1 will cause an #UD exception.\r\n\r\nOperation\r\nMOVLHPS (128-bit two-argument form)\r\nDEST[63:0] (Unmodified)\r\nDEST[127:64] <- SRC[63:0]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVMOVLHPS (128-bit three-argument form - VEX & EVEX)\r\nDEST[63:0] <- SRC1[63:0]\r\nDEST[127:64] <- SRC2[63:0]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nMOVLHPS __m128 _mm_movelh_ps(__m128 a, __m128 b)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\n1. ModRM.MOD = 011B required\r\n\r\n\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 7; additionally\r\n#UD If VEX.L = 1.\r\nEVEX-encoded instruction, see Exceptions Type E7NM.128.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVLHPS"
},
{
"description": "MOVLPD-Move Low Packed Double-Precision Floating-Point Value\r\n Opcode/ Op / En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n 66 0F 12 /r RM V/V SSE2 Move double-precision floating-point value from m64 to\r\n MOVLPD xmm1, m64 low quadword of xmm1.\r\n VEX.NDS.128.66.0F.WIG 12 /r RVM V/V AVX Merge double-precision floating-point value from m64\r\n VMOVLPD xmm2, xmm1, m64 and the high quadword of xmm1.\r\n EVEX.NDS.128.66.0F.W1 12 /r T1S V/V AVX512F Merge double-precision floating-point value from m64\r\n VMOVLPD xmm2, xmm1, m64 and the high quadword of xmm1.\r\n 66 0F 13/r MR V/V SSE2 Move double-precision floating-point value from low\r\n MOVLPD m64, xmm1 quadword of xmm1 to m64.\r\n VEX.128.66.0F.WIG 13/r MR V/V AVX Move double-precision floating-point value from low\r\n VMOVLPD m64, xmm1 quadword of xmm1 to m64.\r\n EVEX.128.66.0F.W1 13/r T1S-MR V/V AVX512F Move double-precision floating-point value from low\r\n VMOVLPD m64, xmm1 quadword of xmm1 to m64.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:r/m (r) VEX.vvvv ModRM:r/m (r) NA\r\n MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n T1S ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n T1S-MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\nDescription\r\nThis instruction cannot be used for register to register or memory to memory moves.\r\n128-bit Legacy SSE load:\r\nMoves a double-precision floating-point value from the source 64-bit memory operand and stores it in the low 64-\r\nbits of the destination XMM register. The upper 64bits of the XMM register are preserved. Bits (MAX_VL-1:128) of\r\nthe corresponding destination register are preserved.\r\nVEX.128 & EVEX encoded load:\r\nLoads a double-precision floating-point value from the source 64-bit memory operand (third operand), merges it\r\nwith the upper 64-bits of the first source XMM register (second operand), and stores it in the low 128-bits of the\r\ndestination XMM register (first operand). Bits (MAX_VL-1:128) of the corresponding destination register are\r\nzeroed.\r\n128-bit store:\r\nStores a double-precision floating-point value from the low 64-bits of the XMM register source (second operand) to\r\nthe 64-bit memory location (first operand).\r\nNote: VMOVLPD (store) (VEX.128.66.0F 13 /r) is legal and has the same behavior as the existing 66 0F 13 store.\r\nFor VMOVLPD (store) VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will #UD.\r\nIf VMOVLPD is encoded with VEX.L or EVEX.L'L= 1, an attempt to execute the instruction encoded with VEX.L or\r\nEVEX.L'L= 1 will cause an #UD exception.\r\n\r\nOperation\r\nMOVLPD (128-bit Legacy SSE load)\r\nDEST[63:0] <- SRC[63:0]\r\nDEST[MAX_VL-1:64] (Unmodified)\r\nVMOVLPD (VEX.128 & EVEX encoded load)\r\n\r\n\r\n\r\nDEST[63:0] <- SRC2[63:0]\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVMOVLPD (store)\r\nDEST[63:0] <- SRC[63:0]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nMOVLPD __m128d _mm_loadl_pd ( __m128d a, double *p)\r\nMOVLPD void _mm_storel_pd (double *p, __m128d a)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 5; additionally\r\n#UD If VEX.L = 1.\r\nEVEX-encoded instruction, see Exceptions Type E9NF.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVLPD"
},
{
"description": "MOVLPS-Move Low Packed Single-Precision Floating-Point Values\r\n Opcode/ Op / En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n 0F 12 /r RM V/V SSE Move two packed single-precision floating-point values\r\n MOVLPS xmm1, m64 from m64 to low quadword of xmm1.\r\n VEX.NDS.128.0F.WIG 12 /r RVM V/V AVX Merge two packed single-precision floating-point values\r\n VMOVLPS xmm2, xmm1, m64 from m64 and the high quadword of xmm1.\r\n EVEX.NDS.128.0F.W0 12 /r T2 V/V AVX512F Merge two packed single-precision floating-point values\r\n VMOVLPS xmm2, xmm1, m64 from m64 and the high quadword of xmm1.\r\n 0F 13/r MR V/V SSE Move two packed single-precision floating-point values\r\n MOVLPS m64, xmm1 from low quadword of xmm1 to m64.\r\n VEX.128.0F.WIG 13/r MR V/V AVX Move two packed single-precision floating-point values\r\n VMOVLPS m64, xmm1 from low quadword of xmm1 to m64.\r\n EVEX.128.0F.W0 13/r T2-MR V/V AVX512F Move two packed single-precision floating-point values\r\n VMOVLPS m64, xmm1 from low quadword of xmm1 to m64.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n T2 ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n T2-MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\nDescription\r\nThis instruction cannot be used for register to register or memory to memory moves.\r\n128-bit Legacy SSE load:\r\nMoves two packed single-precision floating-point values from the source 64-bit memory operand and stores them\r\nin the low 64-bits of the destination XMM register. The upper 64bits of the XMM register are preserved. Bits\r\n(MAX_VL-1:128) of the corresponding destination register are preserved.\r\nVEX.128 & EVEX encoded load:\r\nLoads two packed single-precision floating-point values from the source 64-bit memory operand (the third\r\noperand), merges them with the upper 64-bits of the first source operand (the second operand), and stores them\r\nin the low 128-bits of the destination register (the first operand). Bits (MAX_VL-1:128) of the corresponding desti-\r\nnation register are zeroed.\r\n128-bit store:\r\nLoads two packed single-precision floating-point values from the low 64-bits of the XMM register source (second\r\noperand) to the 64-bit memory location (first operand).\r\nNote: VMOVLPS (store) (VEX.128.0F 13 /r) is legal and has the same behavior as the existing 0F 13 store. For\r\nVMOVLPS (store) VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will #UD.\r\n\r\n\r\nIf VMOVLPS is encoded with VEX.L or EVEX.L'L= 1, an attempt to execute the instruction encoded with VEX.L or\r\nEVEX.L'L= 1 will cause an #UD exception.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nMOVLPS (128-bit Legacy SSE load)\r\nDEST[63:0] <- SRC[63:0]\r\nDEST[MAX_VL-1:64] (Unmodified)\r\n\r\nVMOVLPS (VEX.128 & EVEX encoded load)\r\nDEST[63:0] <- SRC2[63:0]\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVMOVLPS (store)\r\nDEST[63:0] <- SRC[63:0]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nMOVLPS __m128 _mm_loadl_pi ( __m128 a, __m64 *p)\r\nMOVLPS void _mm_storel_pi (__m64 *p, __m128 a)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 5; additionally\r\n#UD If VEX.L = 1.\r\nEVEX-encoded instruction, see Exceptions Type E9NF.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVLPS"
},
{
"description": "MOVMSKPD-Extract Packed Double-Precision Floating-Point Sign Mask\r\nOpcode/ Op/ 64/32-bit CPUID Description\r\nInstruction En Mode Feature\r\n Flag\r\n66 0F 50 /r RM V/V SSE2 Extract 2-bit sign mask from xmm and store in reg. The\r\nMOVMSKPD reg, xmm upper bits of r32 or r64 are filled with zeros.\r\n\r\nVEX.128.66.0F.WIG 50 /r RM V/V AVX Extract 2-bit sign mask from xmm2 and store in reg.\r\nVMOVMSKPD reg, xmm2 The upper bits of r32 or r64 are zeroed.\r\n\r\nVEX.256.66.0F.WIG 50 /r RM V/V AVX Extract 4-bit sign mask from ymm2 and store in reg.\r\nVMOVMSKPD reg, ymm2 The upper bits of r32 or r64 are zeroed.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\n\r\nDescription\r\nExtracts the sign bits from the packed double-precision floating-point values in the source operand (second\r\noperand), formats them into a 2-bit mask, and stores the mask in the destination operand (first operand). The\r\nsource operand is an XMM register, and the destination operand is a general-purpose register. The mask is stored\r\nin the 2 low-order bits of the destination operand. Zero-extend the upper bits of the destination.\r\nIn 64-bit mode, the instruction can access additional registers (XMM8-XMM15, R8-R15) when used with a REX.R\r\nprefix. The default operand size is 64-bit in 64-bit mode.\r\n128-bit versions: The source operand is a YMM register. The destination operand is a general purpose register.\r\nVEX.256 encoded version: The source operand is a YMM register. The destination operand is a general purpose\r\nregister.\r\nNote: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\nOperation\r\n(V)MOVMSKPD (128-bit versions)\r\nDEST[0] <- SRC[63]\r\nDEST[1] <- SRC[127]\r\nIF DEST = r32\r\n THEN DEST[31:2] <- 0;\r\n ELSE DEST[63:2] <- 0;\r\nFI\r\n\r\nVMOVMSKPD (VEX.256 encoded version)\r\nDEST[0] <- SRC[63]\r\nDEST[1] <- SRC[127]\r\nDEST[2] <- SRC[191]\r\nDEST[3] <- SRC[255]\r\nIF DEST = r32\r\n THEN DEST[31:4] <- 0;\r\n ELSE DEST[63:4] <- 0;\r\nFI\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nMOVMSKPD: int _mm_movemask_pd ( __m128d a)\r\nVMOVMSKPD: _mm256_movemask_pd(__m256d a)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 7; additionally\r\n#UD If VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVMSKPD"
},
{
"description": "MOVMSKPS-Extract Packed Single-Precision Floating-Point Sign Mask\r\n Opcode/ Op/ 64/32-bit CPUID Description\r\n Instruction En Mode Feature\r\n Flag\r\n 0F 50 /r RM V/V SSE Extract 4-bit sign mask from xmm and store in reg.\r\n MOVMSKPS reg, xmm The upper bits of r32 or r64 are filled with zeros.\r\n\r\n VEX.128.0F.WIG 50 /r RM V/V AVX Extract 4-bit sign mask from xmm2 and store in reg.\r\n VMOVMSKPS reg, xmm2 The upper bits of r32 or r64 are zeroed.\r\n\r\n VEX.256.0F.WIG 50 /r RM V/V AVX Extract 8-bit sign mask from ymm2 and store in reg.\r\n VMOVMSKPS reg, ymm2 The upper bits of r32 or r64 are zeroed.\r\n\r\n\r\n\r\n Instruction Operand Encoding1\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\n\r\nDescription\r\nExtracts the sign bits from the packed single-precision floating-point values in the source operand (second\r\noperand), formats them into a 4- or 8-bit mask, and stores the mask in the destination operand (first operand).\r\nThe source operand is an XMM or YMM register, and the destination operand is a general-purpose register. The\r\nmask is stored in the 4 or 8 low-order bits of the destination operand. The upper bits of the destination operand\r\nbeyond the mask are filled with zeros.\r\nIn 64-bit mode, the instruction can access additional registers (XMM8-XMM15, R8-R15) when used with a REX.R\r\nprefix. The default operand size is 64-bit in 64-bit mode.\r\n128-bit versions: The source operand is a YMM register. The destination operand is a general purpose register.\r\nVEX.256 encoded version: The source operand is a YMM register. The destination operand is a general purpose\r\nregister.\r\nNote: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\nOperation\r\nDEST[0] <- SRC[31];\r\nDEST[1] <- SRC[63];\r\nDEST[2] <- SRC[95];\r\nDEST[3] <- SRC[127];\r\n\r\nIF DEST = r32\r\n THEN DEST[31:4] <- ZeroExtend;\r\n ELSE DEST[63:4] <- ZeroExtend;\r\nFI;\r\n\r\n\r\n\r\n\r\n1. ModRM.MOD = 011B required\r\n\r\n\r\n\r\n(V)MOVMSKPS (128-bit version)\r\nDEST[0] <- SRC[31]\r\nDEST[1] <- SRC[63]\r\nDEST[2] <- SRC[95]\r\nDEST[3] <- SRC[127]\r\nIF DEST = r32\r\n THEN DEST[31:4] <- 0;\r\n ELSE DEST[63:4] <- 0;\r\nFI\r\n\r\nVMOVMSKPS (VEX.256 encoded version)\r\nDEST[0] <- SRC[31]\r\nDEST[1] <- SRC[63]\r\nDEST[2] <- SRC[95]\r\nDEST[3] <- SRC[127]\r\nDEST[4] <- SRC[159]\r\nDEST[5] <- SRC[191]\r\nDEST[6] <- SRC[223]\r\nDEST[7] <- SRC[255]\r\nIF DEST = r32\r\n THEN DEST[31:8] <- 0;\r\n ELSE DEST[63:8] <- 0;\r\nFI\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nint _mm_movemask_ps(__m128 a)\r\nint _mm256_movemask_ps(__m256 a)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 7; additionally\r\n#UD If VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVMSKPS"
},
{
"description": "MOVNTDQ-Store Packed Integers Using Non-Temporal Hint\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature Flag\r\n Support\r\n 66 0F E7 /r MR V/V SSE2 Move packed integer values in xmm1 to m128 using non-\r\n MOVNTDQ m128, xmm1 temporal hint.\r\n VEX.128.66.0F.WIG E7 /r MR V/V AVX Move packed integer values in xmm1 to m128 using non-\r\n VMOVNTDQ m128, xmm1 temporal hint.\r\n VEX.256.66.0F.WIG E7 /r MR V/V AVX Move packed integer values in ymm1 to m256 using non-\r\n VMOVNTDQ m256, ymm1 temporal hint.\r\n EVEX.128.66.0F.W0 E7 /r FVM V/V AVX512VL Move packed integer values in xmm1 to m128 using non-\r\n VMOVNTDQ m128, xmm1 AVX512F temporal hint.\r\n EVEX.256.66.0F.W0 E7 /r FVM V/V AVX512VL Move packed integer values in zmm1 to m256 using non-\r\n VMOVNTDQ m256, ymm1 AVX512F temporal hint.\r\n EVEX.512.66.0F.W0 E7 /r FVM V/V AVX512F Move packed integer values in zmm1 to m512 using non-\r\n VMOVNTDQ m512, zmm1 temporal hint.\r\n\r\n\r\n\r\n Instruction Operand Encoding1\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n FVM ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\nDescription\r\nMoves the packed integers in the source operand (second operand) to the destination operand (first operand) using\r\na non-temporal hint to prevent caching of the data during the write to memory. The source operand is an XMM\r\nregister, YMM register or ZMM register, which is assumed to contain integer data (packed bytes, words, double-\r\nwords, or quadwords). The destination operand is a 128-bit, 256-bit or 512-bit memory location. The memory\r\noperand must be aligned on a 16-byte (128-bit version), 32-byte (VEX.256 encoded version) or 64-byte (512-bit\r\nversion) boundary otherwise a general-protection exception (#GP) will be generated.\r\nThe non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the\r\ndata to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it\r\nfetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being\r\nwritten to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an\r\nuncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see\r\n\"Caching of Temporal vs. Non-Temporal Data\" in Chapter 10 in the IA-32 Intel Architecture Software Developer's\r\nManual, Volume 1.\r\nBecause the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with\r\nthe SFENCE or MFENCE instruction should be used in conjunction with VMOVNTDQ instructions if multiple proces-\r\nsors might use different memory types to read/write the destination memory locations.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, VEX.L must be 0; otherwise instructions will\r\n#UD.\r\n\r\nOperation\r\nVMOVNTDQ(EVEX encoded versions)\r\nVL = 128, 256, 512\r\nDEST[VL-1:0] <- SRC[VL-1:0]\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n1. ModRM.MOD = 011B required\r\n\r\n\r\n\r\nMOVNTDQ (Legacy and VEX versions)\r\nDEST <- SRC\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMOVNTDQ void _mm512_stream_si512(void * p, __m512i a);\r\nVMOVNTDQ void _mm256_stream_si256 (__m256i * p, __m256i a);\r\nMOVNTDQ void _mm_stream_si128 (__m128i * p, __m128i a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type1.SSE2;\r\nEVEX-encoded instruction, see Exceptions Type E1NF.\r\n#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVNTDQ"
},
{
"description": "MOVNTDQA-Load Double Quadword Non-Temporal Aligned Hint\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature Flag\r\n Support\r\n 66 0F 38 2A /r RM V/V SSE4_1 Move double quadword from m128 to xmm1 using non-\r\n MOVNTDQA xmm1, m128 temporal hint if WC memory type.\r\n VEX.128.66.0F38.WIG 2A /r RM V/V AVX Move double quadword from m128 to xmm using non-\r\n VMOVNTDQA xmm1, m128 temporal hint if WC memory type.\r\n VEX.256.66.0F38.WIG 2A /r RM V/V AVX2 Move 256-bit data from m256 to ymm using non-temporal\r\n VMOVNTDQA ymm1, m256 hint if WC memory type.\r\n EVEX.128.66.0F38.W0 2A /r FVM V/V AVX512VL Move 128-bit data from m128 to xmm using non-temporal\r\n VMOVNTDQA xmm1, m128 AVX512F hint if WC memory type.\r\n EVEX.256.66.0F38.W0 2A /r FVM V/V AVX512VL Move 256-bit data from m256 to ymm using non-temporal\r\n VMOVNTDQA ymm1, m256 AVX512F hint if WC memory type.\r\n EVEX.512.66.0F38.W0 2A /r FVM V/V AVX512F Move 512-bit data from m512 to zmm using non-temporal\r\n VMOVNTDQA zmm1, m512 hint if WC memory type.\r\n\r\n\r\n\r\n Instruction Operand Encoding1\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n FVM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nMOVNTDQA loads a double quadword from the source operand (second operand) to the destination operand (first\r\noperand) using a non-temporal hint if the memory source is WC (write combining) memory type. For WC memory\r\ntype, the nontemporal hint may be implemented by loading a temporary internal buffer with the equivalent of an\r\naligned cache line without filling this data to the cache. Any memory-type aliased lines in the cache will be snooped\r\nand flushed. Subsequent MOVNTDQA reads to unread portions of the WC cache line will receive data from the\r\ntemporary internal buffer if data is available. The temporary internal buffer may be flushed by the processor at any\r\ntime for any reason, for example:\r\n. A load operation other than a MOVNTDQA which references memory already resident in a temporary internal\r\nbuffer.\r\n. A non-WC reference to memory already resident in a temporary internal buffer.\r\n. Interleaving of reads and writes to a single temporary internal buffer.\r\n. Repeated (V)MOVNTDQA loads of a particular 16-byte item in a streaming line.\r\n. Certain micro-architectural conditions including resource shortages, detection of\r\na mis-speculation condition, and various fault conditions\r\nThe non-temporal hint is implemented by using a write combining (WC) memory type protocol when reading the\r\ndata from memory. Using this protocol, the processor\r\ndoes not read the data into the cache hierarchy, nor does it fetch the corresponding cache line from memory into\r\nthe cache hierarchy. The memory type of the region being read can override the non-temporal hint, if the memory\r\naddress specified for the non-temporal read is not a WC memory region. Information on non-temporal reads and\r\nwrites can be found in \"Caching of Temporal vs. Non-Temporal Data\" in Chapter 10 in the Intel 64 and IA-32\r\nArchitecture Software Developer's Manual, Volume 3A.\r\nBecause the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with\r\na MFENCE instruction should be used in conjunction with MOVNTDQA instructions if multiple processors might use\r\ndifferent memory types for the referenced memory locations or to synchronize reads of a processor with writes by\r\nother agents in the system. A processor's implementation of the streaming load hint does not override the effective\r\nmemory type, but the implementation of the hint is processor dependent. For example, a processor implementa-\r\n\r\n1. ModRM.MOD = 011B required\r\n\r\n\r\n\r\ntion may choose to ignore the hint and process the instruction as a normal MOVDQA for any memory type. Alter-\r\nnatively, another implementation may optimize cache reads generated by MOVNTDQA on WB memory type to\r\nreduce cache evictions.\r\nThe 128-bit (V)MOVNTDQA addresses must be 16-byte aligned or the instruction will cause a #GP.\r\nThe 256-bit VMOVNTDQA addresses must be 32-byte aligned or the instruction will cause a #GP.\r\nThe 512-bit VMOVNTDQA addresses must be 64-byte aligned or the instruction will cause a #GP.\r\n\r\nOperation\r\nMOVNTDQA (128bit- Legacy SSE form)\r\nDEST <-SRC\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVMOVNTDQA (VEX.128 and EVEX.128 encoded form)\r\nDEST <- SRC\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVMOVNTDQA (VEX.256 and EVEX.256 encoded forms)\r\nDEST[255:0] <- SRC[255:0]\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVMOVNTDQA (EVEX.512 encoded form)\r\nDEST[511:0] <- SRC[511:0]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMOVNTDQA __m512i _mm512_stream_load_si512(void * p);\r\nMOVNTDQA __m128i _mm_stream_load_si128 (__m128i *p);\r\nVMOVNTDQA __m256i _mm_stream_load_si256 (__m256i *p);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type1;\r\nEVEX-encoded instruction, see Exceptions Type E1NF.\r\n#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVNTDQA"
},
{
"description": "MOVNTI-Store Doubleword Using Non-Temporal Hint\r\nOpcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n0F C3 /r MOVNTI m32, r32 MR Valid Valid Move doubleword from r32 to m32 using non-\r\n temporal hint.\r\nREX.W + 0F C3 /r MOVNTI m64, r64 MR Valid N.E. Move quadword from r64 to m64 using non-\r\n temporal hint.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\n\r\nDescription\r\nMoves the doubleword integer in the source operand (second operand) to the destination operand (first operand)\r\nusing a non-temporal hint to minimize cache pollution during the write to memory. The source operand is a\r\ngeneral-purpose register. The destination operand is a 32-bit memory location.\r\nThe non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the\r\ndata to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it\r\nfetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being\r\nwritten to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an\r\nuncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see\r\n\"Caching of Temporal vs. Non-Temporal Data\" in Chapter 10 in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 1.\r\nBecause the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with\r\nthe SFENCE or MFENCE instruction should be used in conjunction with MOVNTI instructions if multiple processors\r\nmight use different memory types to read/write the destination memory locations.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-\r\ntional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the\r\nbeginning of this section for encoding data and limits.\r\n\r\nOperation\r\nDEST <- SRC;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nMOVNTI: void _mm_stream_si32 (int *p, int a)\r\nMOVNTI: void _mm_stream_si64(__int64 *p, __int64 a)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.\r\n#SS(0) For an illegal address in the SS segment.\r\n#PF(fault-code) For a page fault.\r\n#UD If CPUID.01H:EDX.SSE2[bit 26] = 0.\r\n If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#GP If any part of the operand lies outside the effective address space from 0 to FFFFH.\r\n#UD If CPUID.01H:EDX.SSE2[bit 26] = 0.\r\n If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in real address mode.\r\n#PF(fault-code) For a page fault.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) For a page fault.\r\n#UD If CPUID.01H:EDX.SSE2[bit 26] = 0.\r\n If the LOCK prefix is used.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVNTI"
},
{
"description": "MOVNTPD-Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0F 2B /r MR V/V SSE2 Move packed double-precision values in xmm1 to m128 using\r\n MOVNTPD m128, xmm1 non-temporal hint.\r\n VEX.128.66.0F.WIG 2B /r MR V/V AVX Move packed double-precision values in xmm1 to m128 using\r\n VMOVNTPD m128, xmm1 non-temporal hint.\r\n VEX.256.66.0F.WIG 2B /r MR V/V AVX Move packed double-precision values in ymm1 to m256 using\r\n VMOVNTPD m256, ymm1 non-temporal hint.\r\n EVEX.128.66.0F.W1 2B /r FVM V/V AVX512VL Move packed double-precision values in xmm1 to m128 using\r\n VMOVNTPD m128, xmm1 AVX512F non-temporal hint.\r\n EVEX.256.66.0F.W1 2B /r FVM V/V AVX512VL Move packed double-precision values in ymm1 to m256 using\r\n VMOVNTPD m256, ymm1 AVX512F non-temporal hint.\r\n EVEX.512.66.0F.W1 2B /r FVM V/V AVX512F Move packed double-precision values in zmm1 to m512 using\r\n VMOVNTPD m512, zmm1 non-temporal hint.\r\n\r\n\r\n\r\n Instruction Operand Encoding1\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n FVM ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\nDescription\r\nMoves the packed double-precision floating-point values in the source operand (second operand) to the destination\r\noperand (first operand) using a non-temporal hint to prevent caching of the data during the write to memory. The\r\nsource operand is an XMM register, YMM register or ZMM register, which is assumed to contain packed double-\r\nprecision, floating-pointing data. The destination operand is a 128-bit, 256-bit or 512-bit memory location. The\r\nmemory operand must be aligned on a 16-byte (128-bit version), 32-byte (VEX.256 encoded version) or 64-byte\r\n(EVEX.512 encoded version) boundary otherwise a general-protection exception (#GP) will be generated.\r\nThe non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the\r\ndata to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it\r\nfetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being\r\nwritten to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an\r\nuncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see\r\n\"Caching of Temporal vs. Non-Temporal Data\" in Chapter 10 in the IA-32 Intel Architecture Software Developer's\r\nManual, Volume 1.\r\nBecause the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with\r\nthe SFENCE or MFENCE instruction should be used in conjunction with MOVNTPD instructions if multiple processors\r\nmight use different memory types to read/write the destination memory locations.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, VEX.L must be 0; otherwise instructions will\r\n#UD.\r\n\r\nOperation\r\nVMOVNTPD (EVEX encoded versions)\r\nVL = 128, 256, 512\r\nDEST[VL-1:0] <- SRC[VL-1:0]\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n1. ModRM.MOD = 011B required\r\n\r\n\r\n\r\nMOVNTPD (Legacy and VEX versions)\r\nDEST <- SRC\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMOVNTPD void _mm512_stream_pd(double * p, __m512d a);\r\nVMOVNTPD void _mm256_stream_pd (double * p, __m256d a);\r\nMOVNTPD void _mm_stream_pd (double * p, __m128d a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type1.SSE2;\r\nEVEX-encoded instruction, see Exceptions Type E1NF.\r\n#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVNTPD"
},
{
"description": "MOVNTPS-Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 0F 2B /r MR V/V SSE Move packed single-precision values xmm1 to mem using\r\n MOVNTPS m128, xmm1 non-temporal hint.\r\n VEX.128.0F.WIG 2B /r MR V/V AVX Move packed single-precision values xmm1 to mem using\r\n VMOVNTPS m128, xmm1 non-temporal hint.\r\n VEX.256.0F.WIG 2B /r MR V/V AVX Move packed single-precision values ymm1 to mem using\r\n VMOVNTPS m256, ymm1 non-temporal hint.\r\n EVEX.128.0F.W0 2B /r FVM V/V AVX512VL Move packed single-precision values in xmm1 to m128\r\n VMOVNTPS m128, xmm1 AVX512F using non-temporal hint.\r\n EVEX.256.0F.W0 2B /r FVM V/V AVX512VL Move packed single-precision values in ymm1 to m256\r\n VMOVNTPS m256, ymm1 AVX512F using non-temporal hint.\r\n EVEX.512.0F.W0 2B /r FVM V/V AVX512F Move packed single-precision values in zmm1 to m512\r\n VMOVNTPS m512, zmm1 using non-temporal hint.\r\n\r\n\r\n\r\n Instruction Operand Encoding1\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n FVM ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\nDescription\r\nMoves the packed single-precision floating-point values in the source operand (second operand) to the destination\r\noperand (first operand) using a non-temporal hint to prevent caching of the data during the write to memory. The\r\nsource operand is an XMM register, YMM register or ZMM register, which is assumed to contain packed single-preci-\r\nsion, floating-pointing. The destination operand is a 128-bit, 256-bit or 512-bit memory location. The memory\r\noperand must be aligned on a 16-byte (128-bit version), 32-byte (VEX.256 encoded version) or 64-byte (EVEX.512\r\nencoded version) boundary otherwise a general-protection exception (#GP) will be generated.\r\nThe non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the\r\ndata to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it\r\nfetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being\r\nwritten to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an\r\nuncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see\r\n\"Caching of Temporal vs. Non-Temporal Data\" in Chapter 10 in the IA-32 Intel Architecture Software Developer's\r\nManual, Volume 1.\r\nBecause the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with\r\nthe SFENCE or MFENCE instruction should be used in conjunction with MOVNTPS instructions if multiple processors\r\nmight use different memory types to read/write the destination memory locations.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\n\r\nOperation\r\nVMOVNTPS (EVEX encoded versions)\r\nVL = 128, 256, 512\r\nDEST[VL-1:0] <- SRC[VL-1:0]\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n1. ModRM.MOD = 011B required\r\n\r\n\r\n\r\nMOVNTPS\r\nDEST <- SRC\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMOVNTPS void _mm512_stream_ps(float * p, __m512d a);\r\nMOVNTPS void _mm_stream_ps (float * p, __m128d a);\r\nVMOVNTPS void _mm256_stream_ps (float * p, __m256 a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type1.SSE; additionally\r\nEVEX-encoded instruction, see Exceptions Type E1NF.\r\n#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVNTPS"
},
{
"description": "MOVNTQ-Store of Quadword Using Non-Temporal Hint\r\nOpcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n0F E7 /r MOVNTQ m64, mm MR Valid Valid Move quadword from mm to m64 using non-\r\n temporal hint.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\n\r\nDescription\r\nMoves the quadword in the source operand (second operand) to the destination operand (first operand) using a\r\nnon-temporal hint to minimize cache pollution during the write to memory. The source operand is an MMX tech-\r\nnology register, which is assumed to contain packed integer data (packed bytes, words, or doublewords). The\r\ndestination operand is a 64-bit memory location.\r\nThe non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the\r\ndata to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it\r\nfetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being\r\nwritten to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an\r\nuncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see\r\n\"Caching of Temporal vs. Non-Temporal Data\" in Chapter 10 in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 1.\r\nBecause the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with\r\nthe SFENCE or MFENCE instruction should be used in conjunction with MOVNTQ instructions if multiple processors\r\nmight use different memory types to read/write the destination memory locations.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nDEST <- SRC;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nMOVNTQ: void _mm_stream_pi(__m64 * p, __m64 a)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Table 22-8, \"Exception Conditions for Legacy SIMD/MMX Instructions without FP Exception,\" in the Intel 64\r\nand IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVNTQ"
},
{
"description": "-R:MOVD",
"mnem": "MOVQ"
},
{
"description": "MOVQ-Move Quadword\r\nOpcode/ Op/ En 64/32-bit CPUID Description\r\nInstruction Mode Feature\r\n Flag\r\n0F 6F /r RM V/V MMX Move quadword from mm/m64 to mm.\r\nMOVQ mm, mm/m64\r\n0F 7F /r MR V/V MMX Move quadword from mm to mm/m64.\r\nMOVQ mm/m64, mm\r\nF3 0F 7E /r RM V/V SSE2 Move quadword from xmm2/mem64 to xmm1.\r\nMOVQ xmm1, xmm2/m64\r\nVEX.128.F3.0F.WIG 7E /r RM V/V AVX Move quadword from xmm2 to xmm1.\r\nVMOVQ xmm1, xmm2/m64\r\nEVEX.128.F3.0F.W1 7E /r T1S-RM V/V AVX512F Move quadword from xmm2/m64 to xmm1.\r\nVMOVQ xmm1, xmm2/m64\r\n66 0F D6 /r MR V/V SSE2 Move quadword from xmm1 to xmm2/mem64.\r\nMOVQ xmm2/m64, xmm1\r\nVEX.128.66.0F.WIG D6 /r MR V/V AVX Move quadword from xmm2 register to xmm1/m64.\r\nVMOVQ xmm1/m64, xmm2\r\nEVEX.128.66.0F.W1 D6 /r T1S-MR V/V AVX512F Move quadword from xmm2 register to xmm1/m64.\r\nVMOVQ xmm1/m64, xmm2\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n T1S-RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n T1S-MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\n\r\nDescription\r\nCopies a quadword from the source operand (second operand) to the destination operand (first operand). The\r\nsource and destination operands can be MMX technology registers, XMM registers, or 64-bit memory locations.\r\nThis instruction can be used to move a quadword between two MMX technology registers or between an MMX tech-\r\nnology register and a 64-bit memory location, or to move data between two XMM registers or between an XMM\r\nregister and a 64-bit memory location. The instruction cannot be used to transfer data between memory locations.\r\nWhen the source operand is an XMM register, the low quadword is moved; when the destination operand is an XMM\r\nregister, the quadword is stored to the low quadword of the register, and the high quadword is cleared to all 0s.\r\nIn 64-bit mode and if not encoded using VEX/EVEX, use of the REX prefix in the form of REX.R permits this instruc-\r\ntion to access additional registers (XMM8-XMM15).\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.\r\nIf VMOVQ is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause an\r\n#UD exception.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nMOVQ instruction when operating on MMX technology registers and memory locations:\r\n DEST <- SRC;\r\n\r\nMOVQ instruction when source and destination operands are XMM registers:\r\n DEST[63:0] <- SRC[63:0];\r\n DEST[127:64] <- 0000000000000000H;\r\n\r\nMOVQ instruction when source operand is XMM register and destination\r\noperand is memory location:\r\n DEST <- SRC[63:0];\r\n\r\nMOVQ instruction when source operand is memory location and destination\r\noperand is XMM register:\r\n DEST[63:0] <- SRC;\r\n DEST[127:64] <- 0000000000000000H;\r\n\r\nVMOVQ (VEX.NDS.128.F3.0F 7E) with XMM register source and destination:\r\nDEST[63:0] <- SRC[63:0]\r\nDEST[VLMAX-1:64] <- 0\r\n\r\nVMOVQ (VEX.128.66.0F D6) with XMM register source and destination:\r\nDEST[63:0] <- SRC[63:0]\r\nDEST[VLMAX-1:64] <- 0\r\n\r\nVMOVQ (7E - EVEX encoded version) with XMM register source and destination:\r\nDEST[63:0] <- SRC[63:0]\r\nDEST[MAX_VL-1:64] <- 0\r\n\r\nVMOVQ (D6 - EVEX encoded version) with XMM register source and destination:\r\nDEST[63:0] <- SRC[63:0]\r\nDEST[MAX_VL-1:64] <- 0\r\n\r\nVMOVQ (7E) with memory source:\r\nDEST[63:0] <- SRC[63:0]\r\nDEST[VLMAX-1:64] <- 0\r\n\r\nVMOVQ (7E - EVEX encoded version) with memory source:\r\nDEST[63:0] <- SRC[63:0]\r\nDEST[:MAX_VL-1:64] <- 0\r\n\r\nVMOVQ (D6) with memory dest:\r\nDEST[63:0] <- SRC2[63:0]\r\n\r\nFlags Affected\r\nNone.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMOVQ __m128i _mm_loadu_si64( void * s);\r\nVMOVQ void _mm_storeu_si64( void * d, __m128i s);\r\nMOVQ m128i _mm_mov_epi64(__m128i a)\r\n\r\n\r\n\r\n\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Table 22-8, \"Exception Conditions for Legacy SIMD/MMX Instructions without FP Exception,\" in the Intel 64\r\nand IA-32 Architectures Software Developer's Manual, Volume 3B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVQ"
},
{
"description": "MOVQ2DQ-Move Quadword from MMX Technology to XMM Register\r\nOpcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\nF3 0F D6 /r MOVQ2DQ xmm, mm RM Valid Valid Move quadword from mmx to low quadword\r\n of xmm.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\n\r\nDescription\r\nMoves the quadword from the source operand (second operand) to the low quadword of the destination operand\r\n(first operand). The source operand is an MMX technology register and the destination operand is an XMM register.\r\nThis instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack\r\npointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU\r\nfloating-point exception is pending, the exception is handled before the MOVQ2DQ instruction is executed.\r\nIn 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).\r\n\r\nOperation\r\nDEST[63:0] <- SRC[63:0];\r\nDEST[127:64] <- 00000000000000000H;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nMOVQ2DQ: __128i _mm_movpi64_pi64 ( __m64 a)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#NM If CR0.TS[bit 3] = 1.\r\n#UD If CR0.EM[bit 2] = 1.\r\n If CR4.OSFXSR[bit 9] = 0.\r\n If CPUID.01H:EDX.SSE2[bit 26] = 0.\r\n If the LOCK prefix is used.\r\n#MF If there is a pending x87 FPU exception.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n",
"mnem": "MOVQ2DQ"
},
{
"description": "MOVS/MOVSB/MOVSW/MOVSD/MOVSQ - Move Data from String to String\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n A4 MOVS m8, m8 NP Valid Valid For legacy mode, Move byte from address\r\n DS:(E)SI to ES:(E)DI. For 64-bit mode move\r\n byte from address (R|E)SI to (R|E)DI.\r\n A5 MOVS m16, m16 NP Valid Valid For legacy mode, move word from address\r\n DS:(E)SI to ES:(E)DI. For 64-bit mode move\r\n word at address (R|E)SI to (R|E)DI.\r\n A5 MOVS m32, m32 NP Valid Valid For legacy mode, move dword from address\r\n DS:(E)SI to ES:(E)DI. For 64-bit mode move\r\n dword from address (R|E)SI to (R|E)DI.\r\n REX.W + A5 MOVS m64, m64 NP Valid N.E. Move qword from address (R|E)SI to (R|E)DI.\r\n A4 MOVSB NP Valid Valid For legacy mode, Move byte from address\r\n DS:(E)SI to ES:(E)DI. For 64-bit mode move\r\n byte from address (R|E)SI to (R|E)DI.\r\n A5 MOVSW NP Valid Valid For legacy mode, move word from address\r\n DS:(E)SI to ES:(E)DI. For 64-bit mode move\r\n word at address (R|E)SI to (R|E)DI.\r\n A5 MOVSD NP Valid Valid For legacy mode, move dword from address\r\n DS:(E)SI to ES:(E)DI. For 64-bit mode move\r\n dword from address (R|E)SI to (R|E)DI.\r\n REX.W + A5 MOVSQ NP Valid N.E. Move qword from address (R|E)SI to (R|E)DI.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nMoves the byte, word, or doubleword specified with the second operand (source operand) to the location specified\r\nwith the first operand (destination operand). Both the source and destination operands are located in memory. The\r\naddress of the source operand is read from the DS:ESI or the DS:SI registers (depending on the address-size attri-\r\nbute of the instruction, 32 or 16, respectively). The address of the destination operand is read from the ES:EDI or\r\nthe ES:DI registers (again depending on the address-size attribute of the instruction). The DS segment may be\r\noverridden with a segment override prefix, but the ES segment cannot be overridden.\r\nAt the assembly-code level, two forms of this instruction are allowed: the \"explicit-operands\" form and the \"no-\r\noperands\" form. The explicit-operands form (specified with the MOVS mnemonic) allows the source and destination\r\noperands to be specified explicitly. Here, the source and destination operands should be symbols that indicate the\r\nsize and location of the source value and the destination, respectively. This explicit-operands form is provided to\r\nallow documentation; however, note that the documentation provided by this form can be misleading. That is, the\r\nsource and destination operand symbols must specify the correct type (size) of the operands (bytes, words, or\r\ndoublewords), but they do not have to specify the correct location. The locations of the source and destination\r\noperands are always specified by the DS:(E)SI and ES:(E)DI registers, which must be loaded correctly before the\r\nmove string instruction is executed.\r\nThe no-operands form provides \"short forms\" of the byte, word, and doubleword versions of the MOVS instruc-\r\ntions. Here also DS:(E)SI and ES:(E)DI are assumed to be the source and destination operands, respectively. The\r\nsize of the source and destination operands is selected with the mnemonic: MOVSB (byte move), MOVSW (word\r\nmove), or MOVSD (doubleword move).\r\nAfter the move operation, the (E)SI and (E)DI registers are incremented or decremented automatically according\r\nto the setting of the DF flag in the EFLAGS register. (If the DF flag is 0, the (E)SI and (E)DI register are incre-\r\n\r\n\r\n\r\n\r\nmented; if the DF flag is 1, the (E)SI and (E)DI registers are decremented.) The registers are incremented or\r\ndecremented by 1 for byte operations, by 2 for word operations, or by 4 for doubleword operations.\r\n\r\n NOTE\r\n To improve performance, more recent processors support modifications to the processor's\r\n operation during the string store operations initiated with MOVS and MOVSB. See Section 7.3.9.3\r\n in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 for additional\r\n information on fast-string operation.\r\nThe MOVS, MOVSB, MOVSW, and MOVSD instructions can be preceded by the REP prefix (see \"REP/REPE/REPZ\r\n/REPNE/REPNZ-Repeat String Operation Prefix\" for a description of the REP prefix) for block moves of ECX bytes,\r\nwords, or doublewords.\r\nIn 64-bit mode, the instruction's default address size is 64 bits, 32-bit address size is supported using the prefix\r\n67H. The 64-bit addresses are specified by RSI and RDI; 32-bit address are specified by ESI and EDI. Use of the\r\nREX.W prefix promotes doubleword operation to 64 bits. See the summary chart at the beginning of this section for\r\nencoding data and limits.\r\n\r\nOperation\r\nDEST <- SRC;\r\n\r\nNon-64-bit Mode:\r\n\r\nIF (Byte move)\r\n THEN IF DF = 0\r\n THEN\r\n (E)SI <- (E)SI + 1;\r\n (E)DI <- (E)DI + 1;\r\n ELSE\r\n (E)SI <- (E)SI - 1;\r\n (E)DI <- (E)DI - 1;\r\n FI;\r\n ELSE IF (Word move)\r\n THEN IF DF = 0\r\n (E)SI <- (E)SI + 2;\r\n (E)DI <- (E)DI + 2;\r\n FI;\r\n ELSE\r\n (E)SI <- (E)SI - 2;\r\n (E)DI <- (E)DI - 2;\r\n FI;\r\n ELSE IF (Doubleword move)\r\n THEN IF DF = 0\r\n (E)SI <- (E)SI + 4;\r\n (E)DI <- (E)DI + 4;\r\n FI;\r\n ELSE\r\n (E)SI <- (E)SI - 4;\r\n (E)DI <- (E)DI - 4;\r\n FI;\r\nFI;\r\n64-bit Mode:\r\n\r\nIF (Byte move)\r\n THEN IF DF = 0\r\n THEN\r\n\r\n\r\n\r\n (R|E)SI <- (R|E)SI + 1;\r\n (R|E)DI <- (R|E)DI + 1;\r\n ELSE\r\n (R|E)SI <- (R|E)SI - 1;\r\n (R|E)DI <- (R|E)DI - 1;\r\n FI;\r\n ELSE IF (Word move)\r\n THEN IF DF = 0\r\n (R|E)SI <- (R|E)SI + 2;\r\n (R|E)DI <- (R|E)DI + 2;\r\n FI;\r\n ELSE\r\n (R|E)SI <- (R|E)SI - 2;\r\n (R|E)DI <- (R|E)DI - 2;\r\n FI;\r\n ELSE IF (Doubleword move)\r\n THEN IF DF = 0\r\n (R|E)SI <- (R|E)SI + 4;\r\n (R|E)DI <- (R|E)DI + 4;\r\n FI;\r\n ELSE\r\n (R|E)SI <- (R|E)SI - 4;\r\n (R|E)DI <- (R|E)DI - 4;\r\n FI;\r\n ELSE IF (Quadword move)\r\n THEN IF DF = 0\r\n (R|E)SI <- (R|E)SI + 8;\r\n (R|E)DI <- (R|E)DI + 8;\r\n FI;\r\n ELSE\r\n (R|E)SI <- (R|E)SI - 8;\r\n (R|E)DI <- (R|E)DI - 8;\r\n FI;\r\nFI;\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination is located in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVS"
},
{
"description": "-R:MOVS",
"mnem": "MOVSB"
},
{
"description": "-R:MOVS",
"mnem": "MOVSD"
},
{
"description": "MOVSD-Move or Merge Scalar Double-Precision Floating-Point Value\r\n Opcode/ Op / En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n F2 0F 10 /r RM V/V SSE2 Move scalar double-precision floating-point value\r\n MOVSD xmm1, xmm2 from xmm2 to xmm1 register.\r\n F2 0F 10 /r RM V/V SSE2 Load scalar double-precision floating-point value\r\n MOVSD xmm1, m64 from m64 to xmm1 register.\r\n F2 0F 11 /r MR V/V SSE2 Move scalar double-precision floating-point value\r\n MOVSD xmm1/m64, xmm2 from xmm2 register to xmm1/m64.\r\n VEX.NDS.LIG.F2.0F.WIG 10 /r RVM V/V AVX Merge scalar double-precision floating-point value\r\n VMOVSD xmm1, xmm2, xmm3 from xmm2 and xmm3 to xmm1 register.\r\n VEX.LIG.F2.0F.WIG 10 /r XM V/V AVX Load scalar double-precision floating-point value\r\n VMOVSD xmm1, m64 from m64 to xmm1 register.\r\n VEX.NDS.LIG.F2.0F.WIG 11 /r MVR V/V AVX Merge scalar double-precision floating-point value\r\n VMOVSD xmm1, xmm2, xmm3 from xmm2 and xmm3 registers to xmm1.\r\n VEX.LIG.F2.0F.WIG 11 /r MR V/V AVX Store scalar double-precision floating-point value\r\n VMOVSD m64, xmm1 from xmm1 register to m64.\r\n EVEX.NDS.LIG.F2.0F.W1 10 /r RVM V/V AVX512F Merge scalar double-precision floating-point value\r\n VMOVSD xmm1 {k1}{z}, xmm2, xmm3 from xmm2 and xmm3 registers to xmm1 under\r\n writemask k1.\r\n EVEX.LIG.F2.0F.W1 10 /r T1S-RM V/V AVX512F Load scalar double-precision floating-point value\r\n VMOVSD xmm1 {k1}{z}, m64 from m64 to xmm1 register under writemask k1.\r\n EVEX.NDS.LIG.F2.0F.W1 11 /r MVR V/V AVX512F Merge scalar double-precision floating-point value\r\n VMOVSD xmm1 {k1}{z}, xmm2, xmm3 from xmm2 and xmm3 registers to xmm1 under\r\n writemask k1.\r\n EVEX.LIG.F2.0F.W1 11 /r T1S-MR V/V AVX512F Store scalar double-precision floating-point value\r\n VMOVSD m64 {k1}, xmm1 from xmm1 register to m64 under writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n XM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n MVR ModRM:r/m (w) vvvv (r) ModRM:reg (r) NA\r\n T1S-RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n T1S-MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\n\r\n\r\n\r\n\r\nDescription\r\nMoves a scalar double-precision floating-point value from the source operand (second operand) to the destination\r\noperand (first operand). The source and destination operands can be XMM registers or 64-bit memory locations.\r\nThis instruction can be used to move a double-precision floating-point value to and from the low quadword of an\r\nXMM register and a 64-bit memory location, or to move a double-precision floating-point value between the low\r\nquadwords of two XMM registers. The instruction cannot be used to transfer data between memory locations.\r\nLegacy version: When the source and destination operands are XMM registers, bits MAX_VL:64 of the destination\r\noperand remains unchanged. When the source operand is a memory location and destination operand is an XMM\r\nregisters, the quadword at bits 127:64 of the destination operand is cleared to all 0s, bits MAX_VL:128 of the desti-\r\nnation operand remains unchanged.\r\nVEX and EVEX encoded register-register syntax: Moves a scalar double-precision floating-point value from the\r\nsecond source operand (the third operand) to the low quadword element of the destination operand (the first\r\noperand). Bits 127:64 of the destination operand are copied from the first source operand (the second operand).\r\nBits (MAX_VL-1:128) of the corresponding destination register are zeroed.\r\nVEX and EVEX encoded memory store syntax: When the source operand is a memory location and destination\r\noperand is an XMM registers, bits MAX_VL:64 of the destination operand is cleared to all 0s.\r\nEVEX encoded versions: The low quadword of the destination is updated according to the writemask.\r\nNote: For VMOVSD (memory store and load forms), VEX.vvvv and EVEX.vvvv are reserved and must be 1111b,\r\notherwise instruction will #UD.\r\n\r\nOperation\r\nVMOVSD (EVEX.NDS.LIG.F2.0F 10 /r: VMOVSD xmm1, m64 with support for 32 registers)\r\nIF k1[0] or *no writemask*\r\n THEN DEST[63:0] <- SRC[63:0]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[63:0] <- 0\r\n FI;\r\nFI;\r\nDEST[511:64] <- 0\r\n\r\nVMOVSD (EVEX.NDS.LIG.F2.0F 11 /r: VMOVSD m64, xmm1 with support for 32 registers)\r\nIF k1[0] or *no writemask*\r\n THEN DEST[63:0] <- SRC[63:0]\r\n ELSE *DEST[63:0] remains unchanged* ; merging-masking\r\nFI;\r\n\r\nVMOVSD (EVEX.NDS.LIG.F2.0F 11 /r: VMOVSD xmm1, xmm2, xmm3)\r\nIF k1[0] or *no writemask*\r\n THEN DEST[63:0] <- SRC2[63:0]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[63:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nMOVSD (128-bit Legacy SSE version: MOVSD XMM1, XMM2)\r\nDEST[63:0] <-SRC[63:0]\r\nDEST[MAX_VL-1:64] (Unmodified)\r\n\r\nVMOVSD (VEX.NDS.128.F2.0F 11 /r: VMOVSD xmm1, xmm2, xmm3)\r\nDEST[63:0] <-SRC2[63:0]\r\nDEST[127:64] <-SRC1[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVMOVSD (VEX.NDS.128.F2.0F 10 /r: VMOVSD xmm1, xmm2, xmm3)\r\nDEST[63:0] <-SRC2[63:0]\r\nDEST[127:64] <-SRC1[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVMOVSD (VEX.NDS.128.F2.0F 10 /r: VMOVSD xmm1, m64)\r\nDEST[63:0] <-SRC[63:0]\r\nDEST[MAX_VL-1:64] <-0\r\n\r\nMOVSD/VMOVSD (128-bit versions: MOVSD m64, xmm1 or VMOVSD m64, xmm1)\r\nDEST[63:0] <-SRC[63:0]\r\n\r\nMOVSD (128-bit Legacy SSE version: MOVSD XMM1, m64)\r\nDEST[63:0] <-SRC[63:0]\r\nDEST[127:64] <-0\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMOVSD __m128d _mm_mask_load_sd(__m128d s, __mmask8 k, double * p);\r\nVMOVSD __m128d _mm_maskz_load_sd( __mmask8 k, double * p);\r\nVMOVSD __m128d _mm_mask_move_sd(__m128d sh, __mmask8 k, __m128d sl, __m128d a);\r\nVMOVSD __m128d _mm_maskz_move_sd( __mmask8 k, __m128d s, __m128d a);\r\nVMOVSD void _mm_mask_store_sd(double * p, __mmask8 k, __m128d s);\r\nMOVSD __m128d _mm_load_sd (double *p)\r\nMOVSD void _mm_store_sd (double *p, __m128d a)\r\nMOVSD __m128d _mm_move_sd ( __m128d a, __m128d b)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 5; additionally\r\n#UD If VEX.vvvv != 1111B.\r\nEVEX-encoded instruction, see Exceptions Type E10.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVSD"
},
{
"description": "MOVSHDUP-Replicate Single FP Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n F3 0F 16 /r RM V/V SSE3 Move odd index single-precision floating-point values from\r\n MOVSHDUP xmm1, xmm2/m128 xmm2/mem and duplicate each element into xmm1.\r\n VEX.128.F3.0F.WIG 16 /r RM V/V AVX Move odd index single-precision floating-point values from\r\n VMOVSHDUP xmm1, xmm2/m128 xmm2/mem and duplicate each element into xmm1.\r\n VEX.256.F3.0F.WIG 16 /r RM V/V AVX Move odd index single-precision floating-point values from\r\n VMOVSHDUP ymm1, ymm2/m256 ymm2/mem and duplicate each element into ymm1.\r\n EVEX.128.F3.0F.W0 16 /r FVM V/V AVX512VL Move odd index single-precision floating-point values from\r\n VMOVSHDUP xmm1 {k1}{z}, AVX512F xmm2/m128 and duplicate each element into xmm1 under\r\n xmm2/m128 writemask.\r\n EVEX.256.F3.0F.W0 16 /r FVM V/V AVX512VL Move odd index single-precision floating-point values from\r\n VMOVSHDUP ymm1 {k1}{z}, AVX512F ymm2/m256 and duplicate each element into ymm1 under\r\n ymm2/m256 writemask.\r\n EVEX.512.F3.0F.W0 16 /r FVM V/V AVX512F Move odd index single-precision floating-point values from\r\n VMOVSHDUP zmm1 {k1}{z}, zmm2/m512 and duplicate each element into zmm1 under\r\n zmm2/m512 writemask.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n FVM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nDuplicates odd-indexed single-precision floating-point values from the source operand (the second operand) to\r\nadjacent element pair in the destination operand (the first operand). See Figure 4-3. The source operand is an\r\nXMM, YMM or ZMM register or 128, 256 or 512-bit memory location and the destination operand is an XMM, YMM\r\nor ZMM register.\r\n128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register remain unchanged.\r\nVEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed.\r\nVEX.256 encoded version: Bits (MAX_VL-1:256) of the destination register are zeroed.\r\nEVEX encoded version: The destination operand is updated at 32-bit granularity according to the writemask.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n SRC X7 X6 X5 X4 X3 X2 X1 X0\r\n\r\n\r\n\r\n\r\n DEST X7 X7 X5 X5 X3 X3 X1 X1\r\n\r\n\r\n Figure 4-3. MOVSHDUP Operation\r\n\r\n\r\nOperation\r\nVMOVSHDUP (EVEX encoded versions)\r\n\r\n\r\n\r\n\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nTMP_SRC[31:0] <- SRC[63:32]\r\nTMP_SRC[63:32] <- SRC[63:32]\r\nTMP_SRC[95:64] <- SRC[127:96]\r\nTMP_SRC[127:96] <- SRC[127:96]\r\nIF VL >= 256\r\n TMP_SRC[159:128] <- SRC[191:160]\r\n TMP_SRC[191:160] <- SRC[191:160]\r\n TMP_SRC[223:192] <- SRC[255:224]\r\n TMP_SRC[255:224] <- SRC[255:224]\r\nFI;\r\nIF VL >= 512\r\n TMP_SRC[287:256] <- SRC[319:288]\r\n TMP_SRC[319:288] <- SRC[319:288]\r\n TMP_SRC[351:320] <- SRC[383:352]\r\n TMP_SRC[383:352] <- SRC[383:352]\r\n TMP_SRC[415:384] <- SRC[447:416]\r\n TMP_SRC[447:416] <- SRC[447:416]\r\n TMP_SRC[479:448] <- SRC[511:480]\r\n TMP_SRC[511:480] <- SRC[511:480]\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_SRC[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMOVSHDUP (VEX.256 encoded version)\r\nDEST[31:0] <- SRC[63:32]\r\nDEST[63:32] <- SRC[63:32]\r\nDEST[95:64] <- SRC[127:96]\r\nDEST[127:96] <- SRC[127:96]\r\nDEST[159:128] <- SRC[191:160]\r\nDEST[191:160] <- SRC[191:160]\r\nDEST[223:192] <- SRC[255:224]\r\nDEST[255:224] <- SRC[255:224]\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVMOVSHDUP (VEX.128 encoded version)\r\nDEST[31:0] <- SRC[63:32]\r\nDEST[63:32] <- SRC[63:32]\r\nDEST[95:64] <- SRC[127:96]\r\nDEST[127:96] <- SRC[127:96]\r\nDEST[MAX_VL-1:128] <- 0\r\nMOVSHDUP (128-bit Legacy SSE version)\r\nDEST[31:0] <-SRC[63:32]\r\n\r\n\r\n\r\nDEST[63:32] <-SRC[63:32]\r\nDEST[95:64] <-SRC[127:96]\r\nDEST[127:96] <-SRC[127:96]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMOVSHDUP __m512 _mm512_movehdup_ps( __m512 a);\r\nVMOVSHDUP __m512 _mm512_mask_movehdup_ps(__m512 s, __mmask16 k, __m512 a);\r\nVMOVSHDUP __m512 _mm512_maskz_movehdup_ps( __mmask16 k, __m512 a);\r\nVMOVSHDUP __m256 _mm256_mask_movehdup_ps(__m256 s, __mmask8 k, __m256 a);\r\nVMOVSHDUP __m256 _mm256_maskz_movehdup_ps( __mmask8 k, __m256 a);\r\nVMOVSHDUP __m128 _mm_mask_movehdup_ps(__m128 s, __mmask8 k, __m128 a);\r\nVMOVSHDUP __m128 _mm_maskz_movehdup_ps( __mmask8 k, __m128 a);\r\nVMOVSHDUP __m256 _mm256_movehdup_ps (__m256 a);\r\nVMOVSHDUP __m128 _mm_movehdup_ps (__m128 a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4;\r\nEVEX-encoded instruction, see Exceptions Type E4NF.nb.\r\n#UD If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVSHDUP"
},
{
"description": "MOVSLDUP-Replicate Single FP Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n F3 0F 12 /r A V/V SSE3 Move even index single-precision floating-point values from\r\n MOVSLDUP xmm1, xmm2/m128 xmm2/mem and duplicate each element into xmm1.\r\n VEX.128.F3.0F.WIG 12 /r RM V/V AVX Move even index single-precision floating-point values from\r\n VMOVSLDUP xmm1, xmm2/m128 xmm2/mem and duplicate each element into xmm1.\r\n VEX.256.F3.0F.WIG 12 /r RM V/V AVX Move even index single-precision floating-point values from\r\n VMOVSLDUP ymm1, ymm2/m256 ymm2/mem and duplicate each element into ymm1.\r\n EVEX.128.F3.0F.W0 12 /r FVM V/V AVX512VL Move even index single-precision floating-point values from\r\n VMOVSLDUP xmm1 {k1}{z}, AVX512F xmm2/m128 and duplicate each element into xmm1 under\r\n xmm2/m128 writemask.\r\n EVEX.256.F3.0F.W0 12 /r FVM V/V AVX512VL Move even index single-precision floating-point values from\r\n VMOVSLDUP ymm1 {k1}{z}, AVX512F ymm2/m256 and duplicate each element into ymm1 under\r\n ymm2/m256 writemask.\r\n EVEX.512.F3.0F.W0 12 /r FVM V/V AVX512F Move even index single-precision floating-point values from\r\n VMOVSLDUP zmm1 {k1}{z}, zmm2/m512 and duplicate each element into zmm1 under\r\n zmm2/m512 writemask.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n FVM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nDuplicates even-indexed single-precision floating-point values from the source operand (the second operand). See\r\nFigure 4-4. The source operand is an XMM, YMM or ZMM register or 128, 256 or 512-bit memory location and the\r\ndestination operand is an XMM, YMM or ZMM register.\r\n128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register remain unchanged.\r\nVEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed.\r\nVEX.256 encoded version: Bits (MAX_VL-1:256) of the destination register are zeroed.\r\nEVEX encoded version: The destination operand is updated at 32-bit granularity according to the writemask.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n SRC X7 X6 X5 X4 X3 X2 X1 X0\r\n\r\n\r\n\r\n\r\n DEST X6 X6 X4 X4 X2 X2 X0 X0\r\n\r\n\r\n Figure 4-4. MOVSLDUP Operation\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVMOVSLDUP (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nTMP_SRC[31:0] <- SRC[31:0]\r\nTMP_SRC[63:32] <- SRC[31:0]\r\nTMP_SRC[95:64] <- SRC[95:64]\r\nTMP_SRC[127:96] <- SRC[95:64]\r\nIF VL >= 256\r\n TMP_SRC[159:128] <- SRC[159:128]\r\n TMP_SRC[191:160] <- SRC[159:128]\r\n TMP_SRC[223:192] <- SRC[223:192]\r\n TMP_SRC[255:224] <- SRC[223:192]\r\nFI;\r\nIF VL >= 512\r\n TMP_SRC[287:256] <- SRC[287:256]\r\n TMP_SRC[319:288] <- SRC[287:256]\r\n TMP_SRC[351:320] <- SRC[351:320]\r\n TMP_SRC[383:352] <- SRC[351:320]\r\n TMP_SRC[415:384] <- SRC[415:384]\r\n TMP_SRC[447:416] <- SRC[415:384]\r\n TMP_SRC[479:448] <- SRC[479:448]\r\n TMP_SRC[511:480] <- SRC[479:448]\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_SRC[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMOVSLDUP (VEX.256 encoded version)\r\nDEST[31:0] <- SRC[31:0]\r\nDEST[63:32] <- SRC[31:0]\r\nDEST[95:64] <- SRC[95:64]\r\nDEST[127:96] <- SRC[95:64]\r\nDEST[159:128] <- SRC[159:128]\r\nDEST[191:160] <- SRC[159:128]\r\nDEST[223:192] <- SRC[223:192]\r\nDEST[255:224] <- SRC[223:192]\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVMOVSLDUP (VEX.128 encoded version)\r\nDEST[31:0] <- SRC[31:0]\r\nDEST[63:32] <- SRC[31:0]\r\nDEST[95:64] <- SRC[95:64]\r\nDEST[127:96] <- SRC[95:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\nMOVSLDUP (128-bit Legacy SSE version)\r\nDEST[31:0] <-SRC[31:0]\r\nDEST[63:32] <-SRC[31:0]\r\nDEST[95:64] <-SRC[95:64]\r\nDEST[127:96] <-SRC[95:64]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMOVSLDUP __m512 _mm512_moveldup_ps( __m512 a);\r\nVMOVSLDUP __m512 _mm512_mask_moveldup_ps(__m512 s, __mmask16 k, __m512 a);\r\nVMOVSLDUP __m512 _mm512_maskz_moveldup_ps( __mmask16 k, __m512 a);\r\nVMOVSLDUP __m256 _mm256_mask_moveldup_ps(__m256 s, __mmask8 k, __m256 a);\r\nVMOVSLDUP __m256 _mm256_maskz_moveldup_ps( __mmask8 k, __m256 a);\r\nVMOVSLDUP __m128 _mm_mask_moveldup_ps(__m128 s, __mmask8 k, __m128 a);\r\nVMOVSLDUP __m128 _mm_maskz_moveldup_ps( __mmask8 k, __m128 a);\r\nVMOVSLDUP __m256 _mm256_moveldup_ps (__m256 a);\r\nVMOVSLDUP __m128 _mm_moveldup_ps (__m128 a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4;\r\nEVEX-encoded instruction, see Exceptions Type E4NF.nb.\r\n#UD If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVSLDUP"
},
{
"description": "-R:MOVS",
"mnem": "MOVSQ"
},
{
"description": "MOVSS-Move or Merge Scalar Single-Precision Floating-Point Value\r\n Opcode/ Op / En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n F3 0F 10 /r RM V/V SSE Merge scalar single-precision floating-point value\r\n MOVSS xmm1, xmm2 from xmm2 to xmm1 register.\r\n F3 0F 10 /r RM V/V SSE Load scalar single-precision floating-point value from\r\n MOVSS xmm1, m32 m32 to xmm1 register.\r\n VEX.NDS.LIG.F3.0F.WIG 10 /r RVM V/V AVX Merge scalar single-precision floating-point value\r\n VMOVSS xmm1, xmm2, xmm3 from xmm2 and xmm3 to xmm1 register\r\n VEX.LIG.F3.0F.WIG 10 /r XM V/V AVX Load scalar single-precision floating-point value from\r\n VMOVSS xmm1, m32 m32 to xmm1 register.\r\n F3 0F 11 /r MR V/V SSE Move scalar single-precision floating-point value\r\n MOVSS xmm2/m32, xmm1 from xmm1 register to xmm2/m32.\r\n VEX.NDS.LIG.F3.0F.WIG 11 /r MVR V/V AVX Move scalar single-precision floating-point value\r\n VMOVSS xmm1, xmm2, xmm3 from xmm2 and xmm3 to xmm1 register.\r\n VEX.LIG.F3.0F.WIG 11 /r MR V/V AVX Move scalar single-precision floating-point value\r\n VMOVSS m32, xmm1 from xmm1 register to m32.\r\n EVEX.NDS.LIG.F3.0F.W0 10 /r RVM V/V AVX512F Move scalar single-precision floating-point value\r\n VMOVSS xmm1 {k1}{z}, xmm2, xmm3 from xmm2 and xmm3 to xmm1 register under\r\n writemask k1.\r\n EVEX.LIG.F3.0F.W0 10 /r T1S-RM V/V AVX512F Move scalar single-precision floating-point values\r\n VMOVSS xmm1 {k1}{z}, m32 from m32 to xmm1 under writemask k1.\r\n EVEX.NDS.LIG.F3.0F.W0 11 /r MVR V/V AVX512F Move scalar single-precision floating-point value\r\n VMOVSS xmm1 {k1}{z}, xmm2, xmm3 from xmm2 and xmm3 to xmm1 register under\r\n writemask k1.\r\n EVEX.LIG.F3.0F.W0 11 /r T1S-MR V/V AVX512F Move scalar single-precision floating-point values\r\n VMOVSS m32 {k1}, xmm1 from xmm1 to m32 under writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n XM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n MVR ModRM:r/m (w) vvvv (r) ModRM:reg (r) NA\r\n T1S-RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n T1S-MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\n\r\n\r\n\r\n\r\nDescription\r\nMoves a scalar single-precision floating-point value from the source operand (second operand) to the destination\r\noperand (first operand). The source and destination operands can be XMM registers or 32-bit memory locations.\r\nThis instruction can be used to move a single-precision floating-point value to and from the low doubleword of an\r\nXMM register and a 32-bit memory location, or to move a single-precision floating-point value between the low\r\ndoublewords of two XMM registers. The instruction cannot be used to transfer data between memory locations.\r\nLegacy version: When the source and destination operands are XMM registers, bits (MAX_VL-1:32) of the corre-\r\nsponding destination register are unmodified. When the source operand is a memory location and destination\r\noperand is an XMM registers, Bits (127:32) of the destination operand is cleared to all 0s, bits MAX_VL:128 of the\r\ndestination operand remains unchanged.\r\nVEX and EVEX encoded register-register syntax: Moves a scalar single-precision floating-point value from the\r\nsecond source operand (the third operand) to the low doubleword element of the destination operand (the first\r\noperand). Bits 127:32 of the destination operand are copied from the first source operand (the second operand).\r\nBits (MAX_VL-1:128) of the corresponding destination register are zeroed.\r\nVEX and EVEX encoded memory load syntax: When the source operand is a memory location and destination\r\noperand is an XMM registers, bits MAX_VL:32 of the destination operand is cleared to all 0s.\r\nEVEX encoded versions: The low doubleword of the destination is updated according to the writemask.\r\nNote: For memory store form instruction \"VMOVSS m32, xmm1\", VEX.vvvv is reserved and must be 1111b other-\r\nwise instruction will #UD. For memory store form instruction \"VMOVSS mv {k1}, xmm1\", EVEX.vvvv is reserved\r\nand must be 1111b otherwise instruction will #UD.\r\nSoftware should ensure VMOVSS is encoded with VEX.L=0. Encoding VMOVSS with VEX.L=1 may encounter\r\nunpredictable behavior across different processor generations.\r\n\r\nOperation\r\nVMOVSS (EVEX.NDS.LIG.F3.0F.W0 11 /r when the source operand is memory and the destination is an XMM register)\r\nIF k1[0] or *no writemask*\r\n THEN DEST[31:0] <- SRC[31:0]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[31:0] <- 0\r\n FI;\r\nFI;\r\nDEST[511:32] <- 0\r\n\r\nVMOVSS (EVEX.NDS.LIG.F3.0F.W0 10 /r when the source operand is an XMM register and the destination is memory)\r\nIF k1[0] or *no writemask*\r\n THEN DEST[31:0] <- SRC[31:0]\r\n ELSE *DEST[31:0] remains unchanged* ; merging-masking\r\nFI;\r\n\r\n\r\n\r\n\r\n\r\nVMOVSS (EVEX.NDS.LIG.F3.0F.W0 10/11 /r where the source and destination are XMM registers)\r\nIF k1[0] or *no writemask*\r\n THEN DEST[31:0] <- SRC2[31:0]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[31:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:32] <- SRC1[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nMOVSS (Legacy SSE version when the source and destination operands are both XMM registers)\r\nDEST[31:0] <-SRC[31:0]\r\nDEST[MAX_VL-1:32] (Unmodified)\r\n\r\nVMOVSS (VEX.NDS.128.F3.0F 11 /r where the destination is an XMM register)\r\nDEST[31:0] <-SRC2[31:0]\r\nDEST[127:32] <-SRC1[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVMOVSS (VEX.NDS.128.F3.0F 10 /r where the source and destination are XMM registers)\r\nDEST[31:0] <-SRC2[31:0]\r\nDEST[127:32] <-SRC1[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVMOVSS (VEX.NDS.128.F3.0F 10 /r when the source operand is memory and the destination is an XMM register)\r\nDEST[31:0] <-SRC[31:0]\r\nDEST[MAX_VL-1:32] <-0\r\n\r\nMOVSS/VMOVSS (when the source operand is an XMM register and the destination is memory)\r\nDEST[31:0] <-SRC[31:0]\r\n\r\nMOVSS (Legacy SSE version when the source operand is memory and the destination is an XMM register)\r\nDEST[31:0] <-SRC[31:0]\r\nDEST[127:32] <-0\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMOVSS __m128 _mm_mask_load_ss(__m128 s, __mmask8 k, float * p);\r\nVMOVSS __m128 _mm_maskz_load_ss( __mmask8 k, float * p);\r\nVMOVSS __m128 _mm_mask_move_ss(__m128 sh, __mmask8 k, __m128 sl, __m128 a);\r\nVMOVSS __m128 _mm_maskz_move_ss( __mmask8 k, __m128 s, __m128 a);\r\nVMOVSS void _mm_mask_store_ss(float * p, __mmask8 k, __m128 a);\r\nMOVSS __m128 _mm_load_ss(float * p)\r\nMOVSS void_mm_store_ss(float * p, __m128 a)\r\nMOVSS __m128 _mm_move_ss(__m128 a, __m128 b)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 5; additionally\r\n#UD If VEX.vvvv != 1111B.\r\nEVEX-encoded instruction, see Exceptions Type E10.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVSS"
},
{
"description": "-R:MOVS",
"mnem": "MOVSW"
},
{
"description": "MOVSX/MOVSXD-Move with Sign-Extension\r\nOpcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n0F BE /r MOVSX r16, r/m8 RM Valid Valid Move byte to word with sign-extension.\r\n0F BE /r MOVSX r32, r/m8 RM Valid Valid Move byte to doubleword with sign-\r\n extension.\r\nREX + 0F BE /r MOVSX r64, r/m8* RM Valid N.E. Move byte to quadword with sign-extension.\r\n0F BF /r MOVSX r32, r/m16 RM Valid Valid Move word to doubleword, with sign-\r\n extension.\r\nREX.W + 0F BF /r MOVSX r64, r/m16 RM Valid N.E. Move word to quadword with sign-extension.\r\nREX.W** + 63 /r MOVSXD r64, r/m32 RM Valid N.E. Move doubleword to quadword with sign-\r\n extension.\r\nNOTES:\r\n* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n** The use of MOVSXD without REX.W in 64-bit mode is discouraged, Regular MOV should be used instead of using MOVSXD without\r\n REX.W.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\n\r\nDescription\r\nCopies the contents of the source operand (register or memory location) to the destination operand (register) and\r\nsign extends the value to 16 or 32 bits (see Figure 7-6 in the Intel 64 and IA-32 Architectures Software Devel-\r\noper's Manual, Volume 1). The size of the converted value depends on the operand-size attribute.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-\r\ntional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the\r\nbeginning of this section for encoding data and limits.\r\n\r\nOperation\r\nDEST <- SignExtend(SRC);\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVSX"
},
{
"description": "-R:MOVSX",
"mnem": "MOVSXD"
},
{
"description": "MOVUPD-Move Unaligned Packed Double-Precision Floating-Point Values\r\n Opcode/ Op / En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n 66 0F 10 /r RM V/V SSE2 Move unaligned packed double-precision floating-\r\n MOVUPD xmm1, xmm2/m128 point from xmm2/mem to xmm1.\r\n 66 0F 11 /r MR V/V SSE2 Move unaligned packed double-precision floating-\r\n MOVUPD xmm2/m128, xmm1 point from xmm1 to xmm2/mem.\r\n VEX.128.66.0F.WIG 10 /r RM V/V AVX Move unaligned packed double-precision floating-\r\n VMOVUPD xmm1, xmm2/m128 point from xmm2/mem to xmm1.\r\n VEX.128.66.0F.WIG 11 /r MR V/V AVX Move unaligned packed double-precision floating-\r\n VMOVUPD xmm2/m128, xmm1 point from xmm1 to xmm2/mem.\r\n VEX.256.66.0F.WIG 10 /r RM V/V AVX Move unaligned packed double-precision floating-\r\n VMOVUPD ymm1, ymm2/m256 point from ymm2/mem to ymm1.\r\n VEX.256.66.0F.WIG 11 /r MR V/V AVX Move unaligned packed double-precision floating-\r\n VMOVUPD ymm2/m256, ymm1 point from ymm1 to ymm2/mem.\r\n EVEX.128.66.0F.W1 10 /r FVM-RM V/V AVX512VL Move unaligned packed double-precision floating-\r\n VMOVUPD xmm1 {k1}{z}, xmm2/m128 AVX512F point from xmm2/m128 to xmm1 using\r\n writemask k1.\r\n EVEX.128.66.0F.W1 11 /r FVM-MR V/V AVX512VL Move unaligned packed double-precision floating-\r\n VMOVUPD xmm2/m128 {k1}{z}, xmm1 AVX512F point from xmm1 to xmm2/m128 using\r\n writemask k1.\r\n EVEX.256.66.0F.W1 10 /r FVM-RM V/V AVX512VL Move unaligned packed double-precision floating-\r\n VMOVUPD ymm1 {k1}{z}, ymm2/m256 AVX512F point from ymm2/m256 to ymm1 using\r\n writemask k1.\r\n EVEX.256.66.0F.W1 11 /r FVM-MR V/V AVX512VL Move unaligned packed double-precision floating-\r\n VMOVUPD ymm2/m256 {k1}{z}, ymm1 AVX512F point from ymm1 to ymm2/m256 using\r\n writemask k1.\r\n EVEX.512.66.0F.W1 10 /r FVM-RM V/V AVX512F Move unaligned packed double-precision floating-\r\n VMOVUPD zmm1 {k1}{z}, zmm2/m512 point values from zmm2/m512 to zmm1 using\r\n writemask k1.\r\n EVEX.512.66.0F.W1 11 /r FVM-MR V/V AVX512F Move unaligned packed double-precision floating-\r\n VMOVUPD zmm2/m512 {k1}{z}, zmm1 point values from zmm1 to zmm2/m512 using\r\n writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n FVM-RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n RVM-MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\nDescription\r\nNote: VEX.vvvv and EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\nEVEX.512 encoded version:\r\nMoves 512 bits of packed double-precision floating-point values from the source operand (second operand) to the\r\ndestination operand (first operand). This instruction can be used to load a ZMM register from a float64 memory\r\nlocation, to store the contents of a ZMM register into a memory. The destination operand is updated according to\r\nthe writemask.\r\n\r\n\r\n\r\n\r\n\r\nVEX.256 encoded version:\r\nMoves 256 bits of packed double-precision floating-point values from the source operand (second operand) to the\r\ndestination operand (first operand). This instruction can be used to load a YMM register from a 256-bit memory\r\nlocation, to store the contents of a YMM register into a 256-bit memory location, or to move data between two YMM\r\nregisters. Bits (MAX_VL-1:256) of the destination register are zeroed.\r\n\r\n\r\n128-bit versions:\r\nMoves 128 bits of packed double-precision floating-point values from the source operand (second operand) to the\r\ndestination operand (first operand). This instruction can be used to load an XMM register from a 128-bit memory\r\nlocation, to store the contents of an XMM register into a 128-bit memory location, or to move data between two\r\nXMM registers.\r\n128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register remain unchanged.\r\nWhen the source or destination operand is a memory operand, the operand may be unaligned on a 16-byte\r\nboundary without causing a general-protection exception (#GP) to be generated\r\nVEX.128 and EVEX.128 encoded versions: Bits (MAX_VL-1:128) of the destination register are zeroed.\r\n\r\nOperation\r\nVMOVUPD (EVEX encoded versions, register-copy form)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- SRC[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE DEST[i+63:i] <- 0 ; zeroing-masking\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMOVUPD (EVEX encoded versions, store-form)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i]<- SRC[i+63:i]\r\n ELSE *DEST[i+63:i] remains unchanged* ; merging-masking\r\n\r\n FI;\r\nENDFOR;\r\n\r\n\r\n\r\n\r\n\r\nVMOVUPD (EVEX encoded versions, load-form)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- SRC[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE DEST[i+63:i] <- 0 ; zeroing-masking\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMOVUPD (VEX.256 encoded version, load - and register copy)\r\nDEST[255:0] <- SRC[255:0]\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVMOVUPD (VEX.256 encoded version, store-form)\r\nDEST[255:0] <- SRC[255:0]\r\n\r\nVMOVUPD (VEX.128 encoded version)\r\nDEST[127:0] <- SRC[127:0]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nMOVUPD (128-bit load- and register-copy- form Legacy SSE version)\r\nDEST[127:0] <- SRC[127:0]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\n(V)MOVUPD (128-bit store-form version)\r\nDEST[127:0] <- SRC[127:0]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMOVUPD __m512d _mm512_loadu_pd( void * s);\r\nVMOVUPD __m512d _mm512_mask_loadu_pd(__m512d a, __mmask8 k, void * s);\r\nVMOVUPD __m512d _mm512_maskz_loadu_pd( __mmask8 k, void * s);\r\nVMOVUPD void _mm512_storeu_pd( void * d, __m512d a);\r\nVMOVUPD void _mm512_mask_storeu_pd( void * d, __mmask8 k, __m512d a);\r\nVMOVUPD __m256d _mm256_mask_loadu_pd(__m256d s, __mmask8 k, void * m);\r\nVMOVUPD __m256d _mm256_maskz_loadu_pd( __mmask8 k, void * m);\r\nVMOVUPD void _mm256_mask_storeu_pd( void * d, __mmask8 k, __m256d a);\r\nVMOVUPD __m128d _mm_mask_loadu_pd(__m128d s, __mmask8 k, void * m);\r\nVMOVUPD __m128d _mm_maskz_loadu_pd( __mmask8 k, void * m);\r\nVMOVUPD void _mm_mask_storeu_pd( void * d, __mmask8 k, __m128d a);\r\nMOVUPD __m256d _mm256_loadu_pd (double * p);\r\nMOVUPD void _mm256_storeu_pd( double *p, __m256d a);\r\nMOVUPD __m128d _mm_loadu_pd (double * p);\r\nMOVUPD void _mm_storeu_pd( double *p, __m128d a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nNote treatment of #AC varies; additionally\r\n#UD If VEX.vvvv != 1111B.\r\nEVEX-encoded instruction, see Exceptions Type E4.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVUPD"
},
{
"description": "MOVUPS-Move Unaligned Packed Single-Precision Floating-Point Values\r\n Opcode/ Op / En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n 0F 10 /r RM V/V SSE Move unaligned packed single-precision\r\n MOVUPS xmm1, xmm2/m128 floating-point from xmm2/mem to xmm1.\r\n 0F 11 /r MR V/V SSE Move unaligned packed single-precision\r\n MOVUPS xmm2/m128, xmm1 floating-point from xmm1 to xmm2/mem.\r\n VEX.128.0F.WIG 10 /r RM V/V AVX Move unaligned packed single-precision\r\n VMOVUPS xmm1, xmm2/m128 floating-point from xmm2/mem to xmm1.\r\n VEX.128.0F 11.WIG /r MR V/V AVX Move unaligned packed single-precision\r\n VMOVUPS xmm2/m128, xmm1 floating-point from xmm1 to xmm2/mem.\r\n VEX.256.0F 10.WIG /r RM V/V AVX Move unaligned packed single-precision\r\n VMOVUPS ymm1, ymm2/m256 floating-point from ymm2/mem to ymm1.\r\n VEX.256.0F 11.WIG /r MR V/V AVX Move unaligned packed single-precision\r\n VMOVUPS ymm2/m256, ymm1 floating-point from ymm1 to ymm2/mem.\r\n EVEX.128.0F.W0 10 /r FVM-RM V/V AVX512VL Move unaligned packed single-precision\r\n VMOVUPS xmm1 {k1}{z}, xmm2/m128 AVX512F floating-point values from xmm2/m128 to\r\n xmm1 using writemask k1.\r\n EVEX.256.0F.W0 10 /r FVM-RM V/V AVX512VL Move unaligned packed single-precision\r\n VMOVUPS ymm1 {k1}{z}, ymm2/m256 AVX512F floating-point values from ymm2/m256 to\r\n ymm1 using writemask k1.\r\n EVEX.512.0F.W0 10 /r FVM-RM V/V AVX512F Move unaligned packed single-precision\r\n VMOVUPS zmm1 {k1}{z}, zmm2/m512 floating-point values from zmm2/m512 to\r\n zmm1 using writemask k1.\r\n EVEX.128.0F.W0 11 /r FVM-MR V/V AVX512VL Move unaligned packed single-precision\r\n VMOVUPS xmm2/m128 {k1}{z}, xmm1 AVX512F floating-point values from xmm1 to\r\n xmm2/m128 using writemask k1.\r\n EVEX.256.0F.W0 11 /r FVM-MR V/V AVX512VL Move unaligned packed single-precision\r\n VMOVUPS ymm2/m256 {k1}{z}, ymm1 AVX512F floating-point values from ymm1 to\r\n ymm2/m256 using writemask k1.\r\n EVEX.512.0F.W0 11 /r FVM-MR V/V AVX512F Move unaligned packed single-precision\r\n VMOVUPS zmm2/m512 {k1}{z}, zmm1 floating-point values from zmm1 to\r\n zmm2/m512 using writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n FVM-RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n RVM-MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\nDescription\r\nNote: VEX.vvvv and EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\nEVEX.512 encoded version:\r\nMoves 512 bits of packed single-precision floating-point values from the source operand (second operand) to the\r\ndestination operand (first operand). This instruction can be used to load a ZMM register from a 512-bit float32\r\nmemory location, to store the contents of a ZMM register into memory. The destination operand is updated\r\naccording to the writemask.\r\n\r\n\r\n\r\n\r\n\r\nVEX.256 and EVEX.256 encoded versions:\r\nMoves 256 bits of packed single-precision floating-point values from the source operand (second operand) to the\r\ndestination operand (first operand). This instruction can be used to load a YMM register from a 256-bit memory\r\nlocation, to store the contents of a YMM register into a 256-bit memory location, or to move data between two YMM\r\nregisters. Bits (MAX_VL-1:256) of the destination register are zeroed.\r\n\r\n\r\n128-bit versions:\r\nMoves 128 bits of packed single-precision floating-point values from the source operand (second operand) to the\r\ndestination operand (first operand). This instruction can be used to load an XMM register from a 128-bit memory\r\nlocation, to store the contents of an XMM register into a 128-bit memory location, or to move data between two\r\nXMM registers.\r\n128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register remain unchanged.\r\nWhen the source or destination operand is a memory operand, the operand may be unaligned without causing a\r\ngeneral-protection exception (#GP) to be generated.\r\nVEX.128 and EVEX.128 encoded versions: Bits (MAX_VL-1:128) of the destination register are zeroed.\r\n\r\nOperation\r\nVMOVUPS (EVEX encoded versions, register-copy form)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- SRC[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE DEST[i+31:i] <- 0 ; zeroing-masking\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMOVUPS (EVEX encoded versions, store-form)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i]<- SRC[i+31:i]\r\n ELSE *DEST[i+31:i] remains unchanged* ; merging-masking\r\n FI;\r\nENDFOR;\r\n\r\n\r\n\r\n\r\n\r\nVMOVUPS (EVEX encoded versions, load-form)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- SRC[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE DEST[i+31:i] <- 0 ; zeroing-masking\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMOVUPS (VEX.256 encoded version, load - and register copy)\r\nDEST[255:0] <- SRC[255:0]\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVMOVUPS (VEX.256 encoded version, store-form)\r\nDEST[255:0] <- SRC[255:0]\r\n\r\nVMOVUPS (VEX.128 encoded version)\r\nDEST[127:0] <- SRC[127:0]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nMOVUPS (128-bit load- and register-copy- form Legacy SSE version)\r\nDEST[127:0] <- SRC[127:0]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\n(V)MOVUPS (128-bit store-form version)\r\nDEST[127:0] <- SRC[127:0]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMOVUPS __m512 _mm512_loadu_ps( void * s);\r\nVMOVUPS __m512 _mm512_mask_loadu_ps(__m512 a, __mmask16 k, void * s);\r\nVMOVUPS __m512 _mm512_maskz_loadu_ps( __mmask16 k, void * s);\r\nVMOVUPS void _mm512_storeu_ps( void * d, __m512 a);\r\nVMOVUPS void _mm512_mask_storeu_ps( void * d, __mmask8 k, __m512 a);\r\nVMOVUPS __m256 _mm256_mask_loadu_ps(__m256 a, __mmask8 k, void * s);\r\nVMOVUPS __m256 _mm256_maskz_loadu_ps( __mmask8 k, void * s);\r\nVMOVUPS void _mm256_mask_storeu_ps( void * d, __mmask8 k, __m256 a);\r\nVMOVUPS __m128 _mm_mask_loadu_ps(__m128 a, __mmask8 k, void * s);\r\nVMOVUPS __m128 _mm_maskz_loadu_ps( __mmask8 k, void * s);\r\nVMOVUPS void _mm_mask_storeu_ps( void * d, __mmask8 k, __m128 a);\r\nMOVUPS __m256 _mm256_loadu_ps ( float * p);\r\nMOVUPS void _mm256 _storeu_ps( float *p, __m256 a);\r\nMOVUPS __m128 _mm_loadu_ps ( float * p);\r\nMOVUPS void _mm_storeu_ps( float *p, __m128 a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nNote treatment of #AC varies;\r\nEVEX-encoded instruction, see Exceptions Type E4.nb.\r\n#UD If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVUPS"
},
{
"description": "MOVZX-Move with Zero-Extend\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F B6 /r MOVZX r16, r/m8 RM Valid Valid Move byte to word with zero-extension.\r\n 0F B6 /r MOVZX r32, r/m8 RM Valid Valid Move byte to doubleword, zero-extension.\r\n REX.W + 0F B6 /r MOVZX r64, r/m8* RM Valid N.E. Move byte to quadword, zero-extension.\r\n 0F B7 /r MOVZX r32, r/m16 RM Valid Valid Move word to doubleword, zero-extension.\r\n REX.W + 0F B7 /r MOVZX r64, r/m16 RM Valid N.E. Move word to quadword, zero-extension.\r\n NOTES:\r\n * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if the REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\n\r\nDescription\r\nCopies the contents of the source operand (register or memory location) to the destination operand (register) and\r\nzero extends the value. The size of the converted value depends on the operand-size attribute.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-\r\ntional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bit operands. See the summary chart\r\nat the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nDEST <- ZeroExtend(SRC);\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MOVZX"
},
{
"description": "MPSADBW - Compute Multiple Packed Sums of Absolute Difference\r\nOpcode/ Op/ 64/32-bit CPUID Description\r\nInstruction En Mode Feature\r\n Flag\r\n66 0F 3A 42 /r ib RMI V/V SSE4_1 Sums absolute 8-bit integer difference of\r\nMPSADBW xmm1, xmm2/m128, imm8 adjacent groups of 4 byte integers in xmm1\r\n and xmm2/m128 and writes the results in\r\n xmm1. Starting offsets within xmm1 and\r\n xmm2/m128 are determined by imm8.\r\nVEX.NDS.128.66.0F3A.WIG 42 /r ib RVMI V/V AVX Sums absolute 8-bit integer difference of\r\nVMPSADBW xmm1, xmm2, xmm3/m128, imm8 adjacent groups of 4 byte integers in xmm2\r\n and xmm3/m128 and writes the results in\r\n xmm1. Starting offsets within xmm2 and\r\n xmm3/m128 are determined by imm8.\r\nVEX.NDS.256.66.0F3A.WIG 42 /r ib RVMI V/V AVX2 Sums absolute 8-bit integer difference of\r\nVMPSADBW ymm1, ymm2, ymm3/m256, imm8 adjacent groups of 4 byte integers in xmm2\r\n and ymm3/m128 and writes the results in\r\n ymm1. Starting offsets within ymm2 and\r\n xmm3/m128 are determined by imm8.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (r, w) ModRM:r/m (r) imm8 NA\r\n RVMI ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8\r\n\r\n\r\nDescription\r\n(V)MPSADBW calculates packed word results of sum-absolute-difference (SAD) of unsigned bytes from two blocks\r\nof 32-bit dword elements, using two select fields in the immediate byte to select the offsets of the two blocks within\r\nthe first source operand and the second operand. Packed SAD word results are calculated within each 128-bit lane.\r\nEach SAD word result is calculated between a stationary block_2 (whose offset within the second source operand\r\nis selected by a two bit select control, multiplied by 32 bits) and a sliding block_1 at consecutive byte-granular\r\nposition within the first source operand. The offset of the first 32-bit block of block_1 is selectable using a one bit\r\nselect control, multiplied by 32 bits.\r\n128-bit Legacy SSE version: Imm8[1:0]*32 specifies the bit offset of block_2 within the second source operand.\r\nImm[2]*32 specifies the initial bit offset of the block_1 within the first source operand. The first source operand\r\nand destination operand are the same. The first source and destination operands are XMM registers. The second\r\nsource operand is either an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding\r\nYMM destination register remain unchanged. Bits 7:3 of the immediate byte are ignored.\r\nVEX.128 encoded version: Imm8[1:0]*32 specifies the bit offset of block_2 within the second source operand.\r\nImm[2]*32 specifies the initial bit offset of the block_1 within the first source operand. The first source and desti-\r\nnation operands are XMM registers. The second source operand is either an XMM register or a 128-bit memory\r\nlocation. Bits (127:128) of the corresponding YMM register are zeroed. Bits 7:3 of the immediate byte are ignored.\r\nVEX.256 encoded version: The sum-absolute-difference (SAD) operation is repeated 8 times for MPSADW between\r\nthe same block_2 (fixed offset within the second source operand) and a variable block_1 (offset is shifted by 8 bits\r\nfor each SAD operation) in the first source operand. Each 16-bit result of eight SAD operations between block_2\r\nand block_1 is written to the respective word in the lower 128 bits of the destination operand.\r\nAdditionally, VMPSADBW performs another eight SAD operations on block_4 of the second source operand and\r\nblock_3 of the first source operand. (Imm8[4:3]*32 + 128) specifies the bit offset of block_4 within the second\r\nsource operand. (Imm[5]*32+128) specifies the initial bit offset of the block_3 within the first source operand.\r\nEach 16-bit result of eight SAD operations between block_4 and block_3 is written to the respective word in the\r\nupper 128 bits of the destination operand.\r\n\r\n\r\n\r\n\r\n\r\nThe first source operand is a YMM register. The second source register can be a YMM register or a 256-bit memory\r\nlocation. The destination operand is a YMM register. Bits 7:6 of the immediate byte are ignored.\r\nNote: If VMPSADBW is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will\r\ncause an #UD exception.\r\n\r\n\r\n\r\n\r\n Imm[4:3]*32+128\r\n 255 224 192 128\r\n\r\n\r\n\r\n Src2 Abs. Diff. Imm[5]*32+128\r\n\r\n\r\n\r\n\r\n Src1\r\n Sum\r\n\r\n 255 144 128\r\n\r\n\r\n Destination\r\n\r\n\r\n\r\n Imm[1:0]*32\r\n 127 96 64 0\r\n\r\n\r\n\r\n Src2 Abs. Diff. Imm[2]*32\r\n\r\n\r\n\r\n\r\n Src1\r\n Sum\r\n\r\n 127 16 0\r\n\r\n\r\n\r\n Destination\r\n\r\n\r\n\r\n\r\n Figure 4-5. 256-bit VMPSADBW Operation\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVMPSADBW (VEX.256 encoded version)\r\nBLK2_OFFSET <- imm8[1:0]*32\r\nBLK1_OFFSET <- imm8[2]*32\r\nSRC1_BYTE0 <- SRC1[BLK1_OFFSET+7:BLK1_OFFSET]\r\nSRC1_BYTE1 <- SRC1[BLK1_OFFSET+15:BLK1_OFFSET+8]\r\nSRC1_BYTE2 <- SRC1[BLK1_OFFSET+23:BLK1_OFFSET+16]\r\nSRC1_BYTE3 <- SRC1[BLK1_OFFSET+31:BLK1_OFFSET+24]\r\nSRC1_BYTE4 <-SRC1[BLK1_OFFSET+39:BLK1_OFFSET+32]\r\nSRC1_BYTE5 <- SRC1[BLK1_OFFSET+47:BLK1_OFFSET+40]\r\nSRC1_BYTE6 <- SRC1[BLK1_OFFSET+55:BLK1_OFFSET+48]\r\nSRC1_BYTE7 <- SRC1[BLK1_OFFSET+63:BLK1_OFFSET+56]\r\nSRC1_BYTE8 <- SRC1[BLK1_OFFSET+71:BLK1_OFFSET+64]\r\nSRC1_BYTE9 <- SRC1[BLK1_OFFSET+79:BLK1_OFFSET+72]\r\nSRC1_BYTE10 <- SRC1[BLK1_OFFSET+87:BLK1_OFFSET+80]\r\nSRC2_BYTE0 <-SRC2[BLK2_OFFSET+7:BLK2_OFFSET]\r\nSRC2_BYTE1 <- SRC2[BLK2_OFFSET+15:BLK2_OFFSET+8]\r\nSRC2_BYTE2 <- SRC2[BLK2_OFFSET+23:BLK2_OFFSET+16]\r\nSRC2_BYTE3 <- SRC2[BLK2_OFFSET+31:BLK2_OFFSET+24]\r\n\r\nTEMP0 <- ABS(SRC1_BYTE0 - SRC2_BYTE0)\r\nTEMP1 <- ABS(SRC1_BYTE1 - SRC2_BYTE1)\r\nTEMP2 <- ABS(SRC1_BYTE2 - SRC2_BYTE2)\r\nTEMP3 <- ABS(SRC1_BYTE3 - SRC2_BYTE3)\r\nDEST[15:0] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\nTEMP0 <- ABS(SRC1_BYTE1 - SRC2_BYTE0)\r\nTEMP1 <- ABS(SRC1_BYTE2 - SRC2_BYTE1)\r\nTEMP2 <- ABS(SRC1_BYTE3 - SRC2_BYTE2)\r\nTEMP3 <- ABS(SRC1_BYTE4 - SRC2_BYTE3)\r\nDEST[31:16] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\nTEMP0 <- ABS(SRC1_BYTE2 - SRC2_BYTE0)\r\nTEMP1 <- ABS(SRC1_BYTE3 - SRC2_BYTE1)\r\nTEMP2 <- ABS(SRC1_BYTE4 - SRC2_BYTE2)\r\nTEMP3 <- ABS(SRC1_BYTE5 - SRC2_BYTE3)\r\nDEST[47:32] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\nTEMP0 <- ABS(SRC1_BYTE3 - SRC2_BYTE0)\r\nTEMP1 <- ABS(SRC1_BYTE4 - SRC2_BYTE1)\r\nTEMP2 <- ABS(SRC1_BYTE5 - SRC2_BYTE2)\r\nTEMP3 <- ABS(SRC1_BYTE6 - SRC2_BYTE3)\r\nDEST[63:48] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\nTEMP0 <- ABS(SRC1_BYTE4 - SRC2_BYTE0)\r\nTEMP1 <- ABS(SRC1_BYTE5 - SRC2_BYTE1)\r\nTEMP2 <- ABS(SRC1_BYTE6 - SRC2_BYTE2)\r\nTEMP3 <- ABS(SRC1_BYTE7 - SRC2_BYTE3)\r\nDEST[79:64] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\n\r\n\r\n\r\n\r\nTEMP0 <- ABS(SRC1_BYTE5 - SRC2_BYTE0)\r\nTEMP1 <- ABS(SRC1_BYTE6 - SRC2_BYTE1)\r\nTEMP2 <- ABS(SRC1_BYTE7 - SRC2_BYTE2)\r\nTEMP3 <- ABS(SRC1_BYTE8 - SRC2_BYTE3)\r\nDEST[95:80] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\nTEMP0 <- ABS(SRC1_BYTE6 - SRC2_BYTE0)\r\nTEMP1 <- ABS(SRC1_BYTE7 - SRC2_BYTE1)\r\nTEMP2 <- ABS(SRC1_BYTE8 - SRC2_BYTE2)\r\nTEMP3 <- ABS(SRC1_BYTE9 - SRC2_BYTE3)\r\nDEST[111:96] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\nTEMP0 <- ABS(SRC1_BYTE7 - SRC2_BYTE0)\r\nTEMP1 <- ABS(SRC1_BYTE8 - SRC2_BYTE1)\r\nTEMP2 <- ABS(SRC1_BYTE9 - SRC2_BYTE2)\r\nTEMP3 <- ABS(SRC1_BYTE10 - SRC2_BYTE3)\r\nDEST[127:112] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\nBLK2_OFFSET <- imm8[4:3]*32 + 128\r\nBLK1_OFFSET <- imm8[5]*32 + 128\r\nSRC1_BYTE0 <- SRC1[BLK1_OFFSET+7:BLK1_OFFSET]\r\nSRC1_BYTE1 <- SRC1[BLK1_OFFSET+15:BLK1_OFFSET+8]\r\nSRC1_BYTE2 <- SRC1[BLK1_OFFSET+23:BLK1_OFFSET+16]\r\nSRC1_BYTE3 <- SRC1[BLK1_OFFSET+31:BLK1_OFFSET+24]\r\nSRC1_BYTE4 <- SRC1[BLK1_OFFSET+39:BLK1_OFFSET+32]\r\nSRC1_BYTE5 <- SRC1[BLK1_OFFSET+47:BLK1_OFFSET+40]\r\nSRC1_BYTE6 <- SRC1[BLK1_OFFSET+55:BLK1_OFFSET+48]\r\nSRC1_BYTE7 <- SRC1[BLK1_OFFSET+63:BLK1_OFFSET+56]\r\nSRC1_BYTE8 <- SRC1[BLK1_OFFSET+71:BLK1_OFFSET+64]\r\nSRC1_BYTE9 <- SRC1[BLK1_OFFSET+79:BLK1_OFFSET+72]\r\nSRC1_BYTE10 <- SRC1[BLK1_OFFSET+87:BLK1_OFFSET+80]\r\n\r\nSRC2_BYTE0 <-SRC2[BLK2_OFFSET+7:BLK2_OFFSET]\r\nSRC2_BYTE1 <- SRC2[BLK2_OFFSET+15:BLK2_OFFSET+8]\r\nSRC2_BYTE2 <- SRC2[BLK2_OFFSET+23:BLK2_OFFSET+16]\r\nSRC2_BYTE3 <- SRC2[BLK2_OFFSET+31:BLK2_OFFSET+24]\r\n\r\nTEMP0 <- ABS(SRC1_BYTE0 - SRC2_BYTE0)\r\nTEMP1 <- ABS(SRC1_BYTE1 - SRC2_BYTE1)\r\nTEMP2 <- ABS(SRC1_BYTE2 - SRC2_BYTE2)\r\nTEMP3 <- ABS(SRC1_BYTE3 - SRC2_BYTE3)\r\nDEST[143:128] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\nTEMP0 <-ABS(SRC1_BYTE1 - SRC2_BYTE0)\r\nTEMP1 <- ABS(SRC1_BYTE2 - SRC2_BYTE1)\r\nTEMP2 <- ABS(SRC1_BYTE3 - SRC2_BYTE2)\r\nTEMP3 <- ABS(SRC1_BYTE4 - SRC2_BYTE3)\r\nDEST[159:144] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\nTEMP0 <- ABS(SRC1_BYTE2 - SRC2_BYTE0)\r\nTEMP1 <- ABS(SRC1_BYTE3 - SRC2_BYTE1)\r\nTEMP2 <- ABS(SRC1_BYTE4 - SRC2_BYTE2)\r\nTEMP3 <- ABS(SRC1_BYTE5 - SRC2_BYTE3)\r\nDEST[175:160] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\n\r\n\r\nTEMP0 <-ABS(SRC1_BYTE3 - SRC2_BYTE0)\r\nTEMP1 <- ABS(SRC1_BYTE4 - SRC2_BYTE1)\r\nTEMP2 <- ABS(SRC1_BYTE5 - SRC2_BYTE2)\r\nTEMP3 <- ABS(SRC1_BYTE6 - SRC2_BYTE3)\r\nDEST[191:176] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\nTEMP0 <- ABS(SRC1_BYTE4 - SRC2_BYTE0)\r\nTEMP1 <- ABS(SRC1_BYTE5 - SRC2_BYTE1)\r\nTEMP2 <- ABS(SRC1_BYTE6 - SRC2_BYTE2)\r\nTEMP3 <- ABS(SRC1_BYTE7 - SRC2_BYTE3)\r\nDEST[207:192] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\nTEMP0 <- ABS(SRC1_BYTE5 - SRC2_BYTE0)\r\nTEMP1 <- ABS(SRC1_BYTE6 - SRC2_BYTE1)\r\nTEMP2 <- ABS(SRC1_BYTE7 - SRC2_BYTE2)\r\nTEMP3 <- ABS(SRC1_BYTE8 - SRC2_BYTE3)\r\nDEST[223:208] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\nTEMP0 <- ABS(SRC1_BYTE6 - SRC2_BYTE0)\r\nTEMP1 <- ABS(SRC1_BYTE7 - SRC2_BYTE1)\r\nTEMP2 <- ABS(SRC1_BYTE8 - SRC2_BYTE2)\r\nTEMP3 <- ABS(SRC1_BYTE9 - SRC2_BYTE3)\r\nDEST[239:224] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\nTEMP0 <- ABS(SRC1_BYTE7 - SRC2_BYTE0)\r\nTEMP1 <- ABS(SRC1_BYTE8 - SRC2_BYTE1)\r\nTEMP2 <- ABS(SRC1_BYTE9 - SRC2_BYTE2)\r\nTEMP3 <- ABS(SRC1_BYTE10 - SRC2_BYTE3)\r\nDEST[255:240] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\nVMPSADBW (VEX.128 encoded version)\r\nBLK2_OFFSET <- imm8[1:0]*32\r\nBLK1_OFFSET <- imm8[2]*32\r\nSRC1_BYTE0 <- SRC1[BLK1_OFFSET+7:BLK1_OFFSET]\r\nSRC1_BYTE1 <- SRC1[BLK1_OFFSET+15:BLK1_OFFSET+8]\r\nSRC1_BYTE2 <- SRC1[BLK1_OFFSET+23:BLK1_OFFSET+16]\r\nSRC1_BYTE3 <- SRC1[BLK1_OFFSET+31:BLK1_OFFSET+24]\r\nSRC1_BYTE4 <- SRC1[BLK1_OFFSET+39:BLK1_OFFSET+32]\r\nSRC1_BYTE5 <- SRC1[BLK1_OFFSET+47:BLK1_OFFSET+40]\r\nSRC1_BYTE6 <- SRC1[BLK1_OFFSET+55:BLK1_OFFSET+48]\r\nSRC1_BYTE7 <- SRC1[BLK1_OFFSET+63:BLK1_OFFSET+56]\r\nSRC1_BYTE8 <- SRC1[BLK1_OFFSET+71:BLK1_OFFSET+64]\r\nSRC1_BYTE9 <- SRC1[BLK1_OFFSET+79:BLK1_OFFSET+72]\r\nSRC1_BYTE10 <- SRC1[BLK1_OFFSET+87:BLK1_OFFSET+80]\r\n\r\nSRC2_BYTE0 <-SRC2[BLK2_OFFSET+7:BLK2_OFFSET]\r\nSRC2_BYTE1 <- SRC2[BLK2_OFFSET+15:BLK2_OFFSET+8]\r\nSRC2_BYTE2 <- SRC2[BLK2_OFFSET+23:BLK2_OFFSET+16]\r\nSRC2_BYTE3 <- SRC2[BLK2_OFFSET+31:BLK2_OFFSET+24]\r\n\r\n\r\n\r\n\r\n\r\nTEMP0 <- ABS(SRC1_BYTE0 - SRC2_BYTE0)\r\nTEMP1 <- ABS(SRC1_BYTE1 - SRC2_BYTE1)\r\nTEMP2 <- ABS(SRC1_BYTE2 - SRC2_BYTE2)\r\nTEMP3 <- ABS(SRC1_BYTE3 - SRC2_BYTE3)\r\nDEST[15:0] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\nTEMP0 <- ABS(SRC1_BYTE1 - SRC2_BYTE0)\r\nTEMP1 <- ABS(SRC1_BYTE2 - SRC2_BYTE1)\r\nTEMP2 <- ABS(SRC1_BYTE3 - SRC2_BYTE2)\r\nTEMP3 <- ABS(SRC1_BYTE4 - SRC2_BYTE3)\r\nDEST[31:16] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\nTEMP0 <- ABS(SRC1_BYTE2 - SRC2_BYTE0)\r\nTEMP1 <- ABS(SRC1_BYTE3 - SRC2_BYTE1)\r\nTEMP2 <- ABS(SRC1_BYTE4 - SRC2_BYTE2)\r\nTEMP3 <- ABS(SRC1_BYTE5 - SRC2_BYTE3)\r\nDEST[47:32] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\nTEMP0 <- ABS(SRC1_BYTE3 - SRC2_BYTE0)\r\nTEMP1 <- ABS(SRC1_BYTE4 - SRC2_BYTE1)\r\nTEMP2 <- ABS(SRC1_BYTE5 - SRC2_BYTE2)\r\nTEMP3 <- ABS(SRC1_BYTE6 - SRC2_BYTE3)\r\nDEST[63:48] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\nTEMP0 <- ABS(SRC1_BYTE4 - SRC2_BYTE0)\r\nTEMP1 <- ABS(SRC1_BYTE5 - SRC2_BYTE1)\r\nTEMP2 <- ABS(SRC1_BYTE6 - SRC2_BYTE2)\r\nTEMP3 <- ABS(SRC1_BYTE7 - SRC2_BYTE3)\r\nDEST[79:64] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\nTEMP0 <- ABS(SRC1_BYTE5 - SRC2_BYTE0)\r\nTEMP1 <- ABS(SRC1_BYTE6 - SRC2_BYTE1)\r\nTEMP2 <- ABS(SRC1_BYTE7 - SRC2_BYTE2)\r\nTEMP3 <- ABS(SRC1_BYTE8 - SRC2_BYTE3)\r\nDEST[95:80] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\nTEMP0 <- ABS(SRC1_BYTE6 - SRC2_BYTE0)\r\nTEMP1 <- ABS(SRC1_BYTE7 - SRC2_BYTE1)\r\nTEMP2 <- ABS(SRC1_BYTE8 - SRC2_BYTE2)\r\nTEMP3 <- ABS(SRC1_BYTE9 - SRC2_BYTE3)\r\nDEST[111:96] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\nTEMP0 <- ABS(SRC1_BYTE7 - SRC2_BYTE0)\r\nTEMP1 <- ABS(SRC1_BYTE8 - SRC2_BYTE1)\r\nTEMP2 <- ABS(SRC1_BYTE9 - SRC2_BYTE2)\r\nTEMP3 <- ABS(SRC1_BYTE10 - SRC2_BYTE3)\r\nDEST[127:112] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\nDEST[VLMAX-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nMPSADBW (128-bit Legacy SSE version)\r\nSRC_OFFSET <- imm8[1:0]*32\r\nDEST_OFFSET <- imm8[2]*32\r\nDEST_BYTE0 <- DEST[DEST_OFFSET+7:DEST_OFFSET]\r\nDEST_BYTE1 <- DEST[DEST_OFFSET+15:DEST_OFFSET+8]\r\nDEST_BYTE2 <- DEST[DEST_OFFSET+23:DEST_OFFSET+16]\r\nDEST_BYTE3 <- DEST[DEST_OFFSET+31:DEST_OFFSET+24]\r\nDEST_BYTE4 <- DEST[DEST_OFFSET+39:DEST_OFFSET+32]\r\nDEST_BYTE5 <- DEST[DEST_OFFSET+47:DEST_OFFSET+40]\r\nDEST_BYTE6 <- DEST[DEST_OFFSET+55:DEST_OFFSET+48]\r\nDEST_BYTE7 <- DEST[DEST_OFFSET+63:DEST_OFFSET+56]\r\nDEST_BYTE8 <- DEST[DEST_OFFSET+71:DEST_OFFSET+64]\r\nDEST_BYTE9 <- DEST[DEST_OFFSET+79:DEST_OFFSET+72]\r\nDEST_BYTE10 <- DEST[DEST_OFFSET+87:DEST_OFFSET+80]\r\n\r\nSRC_BYTE0 <- SRC[SRC_OFFSET+7:SRC_OFFSET]\r\nSRC_BYTE1 <- SRC[SRC_OFFSET+15:SRC_OFFSET+8]\r\nSRC_BYTE2 <- SRC[SRC_OFFSET+23:SRC_OFFSET+16]\r\nSRC_BYTE3 <- SRC[SRC_OFFSET+31:SRC_OFFSET+24]\r\n\r\nTEMP0 <- ABS( DEST_BYTE0 - SRC_BYTE0)\r\nTEMP1 <- ABS( DEST_BYTE1 - SRC_BYTE1)\r\nTEMP2 <- ABS( DEST_BYTE2 - SRC_BYTE2)\r\nTEMP3 <- ABS( DEST_BYTE3 - SRC_BYTE3)\r\nDEST[15:0] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\nTEMP0 <- ABS( DEST_BYTE1 - SRC_BYTE0)\r\nTEMP1 <- ABS( DEST_BYTE2 - SRC_BYTE1)\r\nTEMP2 <- ABS( DEST_BYTE3 - SRC_BYTE2)\r\nTEMP3 <- ABS( DEST_BYTE4 - SRC_BYTE3)\r\nDEST[31:16] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\nTEMP0 <- ABS( DEST_BYTE2 - SRC_BYTE0)\r\nTEMP1 <- ABS( DEST_BYTE3 - SRC_BYTE1)\r\nTEMP2 <- ABS( DEST_BYTE4 - SRC_BYTE2)\r\nTEMP3 <- ABS( DEST_BYTE5 - SRC_BYTE3)\r\nDEST[47:32] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\nTEMP0 <- ABS( DEST_BYTE3 - SRC_BYTE0)\r\nTEMP1 <- ABS( DEST_BYTE4 - SRC_BYTE1)\r\nTEMP2 <- ABS( DEST_BYTE5 - SRC_BYTE2)\r\nTEMP3 <- ABS( DEST_BYTE6 - SRC_BYTE3)\r\nDEST[63:48] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\nTEMP0 <- ABS( DEST_BYTE4 - SRC_BYTE0)\r\nTEMP1 <- ABS( DEST_BYTE5 - SRC_BYTE1)\r\nTEMP2 <- ABS( DEST_BYTE6 - SRC_BYTE2)\r\nTEMP3 <- ABS( DEST_BYTE7 - SRC_BYTE3)\r\nDEST[79:64] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\n\r\n\r\n\r\n\r\nTEMP0 <- ABS( DEST_BYTE5 - SRC_BYTE0)\r\nTEMP1 <- ABS( DEST_BYTE6 - SRC_BYTE1)\r\nTEMP2 <- ABS( DEST_BYTE7 - SRC_BYTE2)\r\nTEMP3 <- ABS( DEST_BYTE8 - SRC_BYTE3)\r\nDEST[95:80] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\nTEMP0 <- ABS( DEST_BYTE6 - SRC_BYTE0)\r\nTEMP1 <- ABS( DEST_BYTE7 - SRC_BYTE1)\r\nTEMP2 <- ABS( DEST_BYTE8 - SRC_BYTE2)\r\nTEMP3 <- ABS( DEST_BYTE9 - SRC_BYTE3)\r\nDEST[111:96] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\n\r\nTEMP0 <- ABS( DEST_BYTE7 - SRC_BYTE0)\r\nTEMP1 <- ABS( DEST_BYTE8 - SRC_BYTE1)\r\nTEMP2 <- ABS( DEST_BYTE9 - SRC_BYTE2)\r\nTEMP3 <- ABS( DEST_BYTE10 - SRC_BYTE3)\r\nDEST[127:112] <- TEMP0 + TEMP1 + TEMP2 + TEMP3\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n(V)MPSADBW: __m128i _mm_mpsadbw_epu8 (__m128i s1, __m128i s2, const int mask);\r\nVMPSADBW: __m256i _mm256_mpsadbw_epu8 (__m256i s1, __m256i s2, const int mask);\r\n\r\nFlags Affected\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4; additionally\r\n#UD If VEX.L = 1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MPSADBW"
},
{
"description": "MUL-Unsigned Multiply\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n F6 /4 MUL r/m8 M Valid Valid Unsigned multiply (AX <- AL * r/m8).\r\n REX + F6 /4 MUL r/m8* M Valid N.E. Unsigned multiply (AX <- AL * r/m8).\r\n F7 /4 MUL r/m16 M Valid Valid Unsigned multiply (DX:AX <- AX * r/m16).\r\n F7 /4 MUL r/m32 M Valid Valid Unsigned multiply (EDX:EAX <- EAX * r/m32).\r\n REX.W + F7 /4 MUL r/m64 M Valid N.E. Unsigned multiply (RDX:RAX <- RAX * r/m64).\r\n NOTES:\r\n * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (r) NA NA NA\r\n\r\n\r\nDescription\r\nPerforms an unsigned multiplication of the first operand (destination operand) and the second operand (source\r\noperand) and stores the result in the destination operand. The destination operand is an implied operand located in\r\nregister AL, AX or EAX (depending on the size of the operand); the source operand is located in a general-purpose\r\nregister or a memory location. The action of this instruction and the location of the result depends on the opcode\r\nand the operand size as shown in Table 4-9.\r\nThe result is stored in register AX, register pair DX:AX, or register pair EDX:EAX (depending on the operand size),\r\nwith the high-order bits of the product contained in register AH, DX, or EDX, respectively. If the high-order bits of\r\nthe product are 0, the CF and OF flags are cleared; otherwise, the flags are set.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-\r\ntional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits.\r\nSee the summary chart at the beginning of this section for encoding data and limits.\r\n\r\n\r\n Table 4-9. MUL Results\r\n Operand Size Source 1 Source 2 Destination\r\n Byte AL r/m8 AX\r\n Word AX r/m16 DX:AX\r\n Doubleword EAX r/m32 EDX:EAX\r\n Quadword RAX r/m64 RDX:RAX\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIF (Byte operation)\r\n THEN\r\n AX <- AL * SRC;\r\n ELSE (* Word or doubleword operation *)\r\n IF OperandSize = 16\r\n THEN\r\n DX:AX <- AX * SRC;\r\n ELSE IF OperandSize = 32\r\n THEN EDX:EAX <- EAX * SRC; FI;\r\n ELSE (* OperandSize = 64 *)\r\n RDX:RAX <- RAX * SRC;\r\n FI;\r\nFI;\r\n\r\nFlags Affected\r\nThe OF and CF flags are set to 0 if the upper half of the result is 0; otherwise, they are set to 1. The SF, ZF, AF, and\r\nPF flags are undefined.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n\r\n\r\n",
"mnem": "MUL"
},
{
"description": "MULPD-Multiply Packed Double-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0F 59 /r RM V/V SSE2 Multiply packed double-precision floating-point values\r\n MULPD xmm1, xmm2/m128 in xmm2/m128 with xmm1 and store result in xmm1.\r\n VEX.NDS.128.66.0F.WIG 59 /r RVM V/V AVX Multiply packed double-precision floating-point values\r\n VMULPD xmm1,xmm2, xmm3/m128 in xmm3/m128 with xmm2 and store result in xmm1.\r\n VEX.NDS.256.66.0F.WIG 59 /r RVM V/V AVX Multiply packed double-precision floating-point values\r\n VMULPD ymm1, ymm2, ymm3/m256 in ymm3/m256 with ymm2 and store result in ymm1.\r\n EVEX.NDS.128.66.0F.W1 59 /r FV V/V AVX512VL Multiply packed double-precision floating-point values\r\n VMULPD xmm1 {k1}{z}, xmm2, AVX512F from xmm3/m128/m64bcst to xmm2 and store result\r\n xmm3/m128/m64bcst in xmm1.\r\n EVEX.NDS.256.66.0F.W1 59 /r FV V/V AVX512VL Multiply packed double-precision floating-point values\r\n VMULPD ymm1 {k1}{z}, ymm2, AVX512F from ymm3/m256/m64bcst to ymm2 and store result\r\n ymm3/m256/m64bcst in ymm1.\r\n EVEX.NDS.512.66.0F.W1 59 /r FV V/V AVX512F Multiply packed double-precision floating-point values\r\n VMULPD zmm1 {k1}{z}, zmm2, in zmm3/m512/m64bcst with zmm2 and store result\r\n zmm3/m512/m64bcst{er} in zmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nMultiply packed double-precision floating-point values from the first source operand with corresponding values in\r\nthe second source operand, and stores the packed double-precision floating-point results in the destination\r\noperand.\r\nEVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second\r\nsource operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector\r\nbroadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally\r\nupdated with writemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register. Bits (MAX_VL-1:256) of the\r\ncorresponding destination ZMM register are zeroed.\r\nVEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM\r\nregister or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)\r\nof the destination YMM register destination are zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nZMM register destination are unmodified.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVMULPD (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1) AND SRC2 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN\r\n DEST[i+63:i] <- SRC1[i+63:i] * SRC2[63:0]\r\n ELSE\r\n DEST[i+63:i] <- SRC1[i+63:i] * SRC2[i+63:i]\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMULPD (VEX.256 encoded version)\r\nDEST[63:0] <-SRC1[63:0] * SRC2[63:0]\r\nDEST[127:64] <-SRC1[127:64] * SRC2[127:64]\r\nDEST[191:128] <-SRC1[191:128] * SRC2[191:128]\r\nDEST[255:192] <-SRC1[255:192] * SRC2[255:192]\r\nDEST[MAX_VL-1:256] <-0;\r\n.\r\nVMULPD (VEX.128 encoded version)\r\nDEST[63:0] <-SRC1[63:0] * SRC2[63:0]\r\nDEST[127:64] <-SRC1[127:64] * SRC2[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nMULPD (128-bit Legacy SSE version)\r\nDEST[63:0] <-DEST[63:0] * SRC[63:0]\r\nDEST[127:64] <-DEST[127:64] * SRC[127:64]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMULPD __m512d _mm512_mul_pd( __m512d a, __m512d b);\r\nVMULPD __m512d _mm512_mask_mul_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);\r\nVMULPD __m512d _mm512_maskz_mul_pd( __mmask8 k, __m512d a, __m512d b);\r\nVMULPD __m512d _mm512_mul_round_pd( __m512d a, __m512d b, int);\r\nVMULPD __m512d _mm512_mask_mul_round_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int);\r\nVMULPD __m512d _mm512_maskz_mul_round_pd( __mmask8 k, __m512d a, __m512d b, int);\r\nVMULPD __m256d _mm256_mul_pd (__m256d a, __m256d b);\r\nMULPD __m128d _mm_mul_pd (__m128d a, __m128d b);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 2.\r\nEVEX-encoded instruction, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MULPD"
},
{
"description": "MULPS-Multiply Packed Single-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 0F 59 /r RM V/V SSE Multiply packed single-precision floating-point values in\r\n MULPS xmm1, xmm2/m128 xmm2/m128 with xmm1 and store result in xmm1.\r\n VEX.NDS.128.0F.WIG 59 /r RVM V/V AVX Multiply packed single-precision floating-point values in\r\n VMULPS xmm1,xmm2, xmm3/m128 xmm3/m128 with xmm2 and store result in xmm1.\r\n VEX.NDS.256.0F.WIG 59 /r RVM V/V AVX Multiply packed single-precision floating-point values in\r\n VMULPS ymm1, ymm2, ymm3/m256 ymm3/m256 with ymm2 and store result in ymm1.\r\n EVEX.NDS.128.0F.W0 59 /r FV V/V AVX512VL Multiply packed single-precision floating-point values\r\n VMULPS xmm1 {k1}{z}, xmm2, AVX512F from xmm3/m128/m32bcst to xmm2 and store result in\r\n xmm3/m128/m32bcst xmm1.\r\n EVEX.NDS.256.0F.W0 59 /r FV V/V AVX512VL Multiply packed single-precision floating-point values\r\n VMULPS ymm1 {k1}{z}, ymm2, AVX512F from ymm3/m256/m32bcst to ymm2 and store result in\r\n ymm3/m256/m32bcst ymm1.\r\n EVEX.NDS.512.0F.W0 59 /r FV V/V AVX512F Multiply packed single-precision floating-point values in\r\n VMULPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst with zmm2 and store result in\r\n zmm3/m512/m32bcst {er} zmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nMultiply the packed single-precision floating-point values from the first source operand with the corresponding\r\nvalues in the second source operand, and stores the packed double-precision floating-point results in the destina-\r\ntion operand.\r\nEVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second\r\nsource operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector\r\nbroadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally\r\nupdated with writemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register. Bits (MAX_VL-1:256) of the\r\ncorresponding destination ZMM register are zeroed.\r\nVEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM\r\nregister or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)\r\nof the destination YMM register destination are zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nZMM register destination are unmodified.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVMULPS (EVEX encoded version)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1) AND SRC2 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN\r\n DEST[i+31:i] <- SRC1[i+31:i] * SRC2[31:0]\r\n ELSE\r\n DEST[i+31:i] <- SRC1[i+31:i] * SRC2[i+31:i]\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVMULPS (VEX.256 encoded version)\r\nDEST[31:0] <-SRC1[31:0] * SRC2[31:0]\r\nDEST[63:32] <-SRC1[63:32] * SRC2[63:32]\r\nDEST[95:64] <-SRC1[95:64] * SRC2[95:64]\r\nDEST[127:96] <-SRC1[127:96] * SRC2[127:96]\r\nDEST[159:128] <-SRC1[159:128] * SRC2[159:128]\r\nDEST[191:160]<-SRC1[191:160] * SRC2[191:160]\r\nDEST[223:192] <-SRC1[223:192] * SRC2[223:192]\r\nDEST[255:224] <-SRC1[255:224] * SRC2[255:224].\r\nDEST[MAX_VL-1:256] <-0;\r\n\r\nVMULPS (VEX.128 encoded version)\r\nDEST[31:0] <-SRC1[31:0] * SRC2[31:0]\r\nDEST[63:32] <-SRC1[63:32] * SRC2[63:32]\r\nDEST[95:64] <-SRC1[95:64] * SRC2[95:64]\r\nDEST[127:96] <-SRC1[127:96] * SRC2[127:96]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nMULPS (128-bit Legacy SSE version)\r\nDEST[31:0] <-SRC1[31:0] * SRC2[31:0]\r\nDEST[63:32] <-SRC1[63:32] * SRC2[63:32]\r\nDEST[95:64] <-SRC1[95:64] * SRC2[95:64]\r\nDEST[127:96] <-SRC1[127:96] * SRC2[127:96]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMULPS __m512 _mm512_mul_ps( __m512 a, __m512 b);\r\nVMULPS __m512 _mm512_mask_mul_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);\r\nVMULPS __m512 _mm512_maskz_mul_ps(__mmask16 k, __m512 a, __m512 b);\r\nVMULPS __m512 _mm512_mul_round_ps( __m512 a, __m512 b, int);\r\nVMULPS __m512 _mm512_mask_mul_round_ps(__m512 s, __mmask16 k, __m512 a, __m512 b, int);\r\nVMULPS __m512 _mm512_maskz_mul_round_ps(__mmask16 k, __m512 a, __m512 b, int);\r\nVMULPS __m256 _mm256_mask_mul_ps(__m256 s, __mmask8 k, __m256 a, __m256 b);\r\nVMULPS __m256 _mm256_maskz_mul_ps(__mmask8 k, __m256 a, __m256 b);\r\nVMULPS __m128 _mm_mask_mul_ps(__m128 s, __mmask8 k, __m128 a, __m128 b);\r\nVMULPS __m128 _mm_maskz_mul_ps(__mmask8 k, __m128 a, __m128 b);\r\nVMULPS __m256 _mm256_mul_ps (__m256 a, __m256 b);\r\nMULPS __m128 _mm_mul_ps (__m128 a, __m128 b);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 2.\r\nEVEX-encoded instruction, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MULPS"
},
{
"description": "MULSD-Multiply Scalar Double-Precision Floating-Point Value\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n F2 0F 59 /r RM V/V SSE2 Multiply the low double-precision floating-point value in\r\n MULSD xmm1,xmm2/m64 xmm2/m64 by low double-precision floating-point\r\n value in xmm1.\r\n VEX.NDS.128.F2.0F.WIG 59 /r RVM V/V AVX Multiply the low double-precision floating-point value in\r\n VMULSD xmm1,xmm2, xmm3/m64 xmm3/m64 by low double-precision floating-point\r\n value in xmm2.\r\n EVEX.NDS.LIG.F2.0F.W1 59 /r T1S V/V AVX512F Multiply the low double-precision floating-point value in\r\n VMULSD xmm1 {k1}{z}, xmm2, xmm3/m64 by low double-precision floating-point\r\n xmm3/m64 {er} value in xmm2.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n T1S ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nMultiplies the low double-precision floating-point value in the second source operand by the low double-precision\r\nfloating-point value in the first source operand, and stores the double-precision floating-point result in the destina-\r\ntion operand. The second source operand can be an XMM register or a 64-bit memory location. The first source\r\noperand and the destination operands are XMM registers.\r\n128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAX_VL-\r\n1:64) of the corresponding destination register remain unchanged.\r\nVEX.128 and EVEX encoded version: The quadword at bits 127:64 of the destination operand is copied from the\r\nsame bits of the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.\r\nEVEX encoded version: The low quadword element of the destination operand is updated according to the\r\nwritemask.\r\nSoftware should ensure VMULSD is encoded with VEX.L=0. Encoding VMULSD with VEX.L=1 may encounter unpre-\r\ndictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVMULSD (EVEX encoded version)\r\nIF (EVEX.b = 1) AND SRC2 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[63:0] <- SRC1[63:0] * SRC2[63:0]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[63:0] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVMULSD (VEX.128 encoded version)\r\nDEST[63:0] <-SRC1[63:0] * SRC2[63:0]\r\nDEST[127:64] <-SRC1[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nMULSD (128-bit Legacy SSE version)\r\nDEST[63:0] <-DEST[63:0] * SRC[63:0]\r\nDEST[MAX_VL-1:64] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMULSD __m128d _mm_mask_mul_sd(__m128d s, __mmask8 k, __m128d a, __m128d b);\r\nVMULSD __m128d _mm_maskz_mul_sd( __mmask8 k, __m128d a, __m128d b);\r\nVMULSD __m128d _mm_mul_round_sd( __m128d a, __m128d b, int);\r\nVMULSD __m128d _mm_mask_mul_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int);\r\nVMULSD __m128d _mm_maskz_mul_round_sd( __mmask8 k, __m128d a, __m128d b, int);\r\nMULSD __m128d _mm_mul_sd (__m128d a, __m128d b)\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 3.\r\nEVEX-encoded instruction, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MULSD"
},
{
"description": "MULSS-Multiply Scalar Single-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n F3 0F 59 /r RM V/V SSE Multiply the low single-precision floating-point value in\r\n MULSS xmm1,xmm2/m32 xmm2/m32 by the low single-precision floating-point\r\n value in xmm1.\r\n VEX.NDS.128.F3.0F.WIG 59 /r RVM V/V AVX Multiply the low single-precision floating-point value in\r\n VMULSS xmm1,xmm2, xmm3/m32 xmm3/m32 by the low single-precision floating-point\r\n value in xmm2.\r\n EVEX.NDS.LIG.F3.0F.W0 59 /r T1S V/V AVX512F Multiply the low single-precision floating-point value in\r\n VMULSS xmm1 {k1}{z}, xmm2, xmm3/m32 by the low single-precision floating-point\r\n xmm3/m32 {er} value in xmm2.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n T1S ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nMultiplies the low single-precision floating-point value from the second source operand by the low single-precision\r\nfloating-point value in the first source operand, and stores the single-precision floating-point result in the destina-\r\ntion operand. The second source operand can be an XMM register or a 32-bit memory location. The first source\r\noperand and the destination operands are XMM registers.\r\n128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAX_VL-\r\n1:32) of the corresponding YMM destination register remain unchanged.\r\nVEX.128 and EVEX encoded version: The first source operand is an xmm register encoded by VEX.vvvv. The three\r\nhigh-order doublewords of the destination operand are copied from the first source operand. Bits (MAX_VL-1:128)\r\nof the destination register are zeroed.\r\nEVEX encoded version: The low doubleword element of the destination operand is updated according to the\r\nwritemask.\r\nSoftware should ensure VMULSS is encoded with VEX.L=0. Encoding VMULSS with VEX.L=1 may encounter unpre-\r\ndictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVMULSS (EVEX encoded version)\r\nIF (EVEX.b = 1) AND SRC2 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[31:0] <- SRC1[31:0] * SRC2[31:0]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[31:0] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[127:32] <- SRC1[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVMULSS (VEX.128 encoded version)\r\nDEST[31:0] <-SRC1[31:0] * SRC2[31:0]\r\nDEST[127:32] <-SRC1[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nMULSS (128-bit Legacy SSE version)\r\nDEST[31:0] <-DEST[31:0] * SRC[31:0]\r\nDEST[MAX_VL-1:32] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVMULSS __m128 _mm_mask_mul_ss(__m128 s, __mmask8 k, __m128 a, __m128 b);\r\nVMULSS __m128 _mm_maskz_mul_ss( __mmask8 k, __m128 a, __m128 b);\r\nVMULSS __m128 _mm_mul_round_ss( __m128 a, __m128 b, int);\r\nVMULSS __m128 _mm_mask_mul_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int);\r\nVMULSS __m128 _mm_maskz_mul_round_ss( __mmask8 k, __m128 a, __m128 b, int);\r\nMULSS __m128 _mm_mul_ss(__m128 a, __m128 b)\r\n\r\nSIMD Floating-Point Exceptions\r\nUnderflow, Overflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 3.\r\nEVEX-encoded instruction, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MULSS"
},
{
"description": "MULX - Unsigned Multiply Without Affecting Flags\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En -bit Feature\r\n Mode Flag\r\n VEX.NDD.LZ.F2.0F38.W0 F6 /r RVM V/V BMI2 Unsigned multiply of r/m32 with EDX without affecting arithmetic\r\n MULX r32a, r32b, r/m32 flags.\r\n VEX.NDD.LZ.F2.0F38.W1 F6 /r RVM V/N.E. BMI2 Unsigned multiply of r/m64 with RDX without affecting arithmetic\r\n MULX r64a, r64b, r/m64 flags.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RDX/EDX is implied 64/32 bits\r\n RVM ModRM:reg (w) VEX.vvvv (w) ModRM:r/m (r)\r\n source\r\n\r\n\r\nDescription\r\nPerforms an unsigned multiplication of the implicit source operand (EDX/RDX) and the specified source operand\r\n(the third operand) and stores the low half of the result in the second destination (second operand), the high half\r\nof the result in the first destination operand (first operand), without reading or writing the arithmetic flags. This\r\nenables efficient programming where the software can interleave add with carry operations and multiplications.\r\nIf the first and second operand are identical, it will contain the high half of the multiplication result.\r\nThis instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in\r\n64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An\r\nattempt to execute this instruction with VEX.L not equal to 0 will cause #UD.\r\n\r\nOperation\r\n// DEST1: ModRM:reg\r\n// DEST2: VEX.vvvv\r\nIF (OperandSize = 32)\r\n SRC1 <- EDX;\r\n DEST2 <- (SRC1*SRC2)[31:0];\r\n DEST1 <- (SRC1*SRC2)[63:32];\r\nELSE IF (OperandSize = 64)\r\n SRC1 <- RDX;\r\n DEST2 <- (SRC1*SRC2)[63:0];\r\n DEST1 <- (SRC1*SRC2)[127:64];\r\nFI\r\n\r\nFlags Affected\r\nNone\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nAuto-generated from high-level language when possible.\r\nunsigned int mulx_u32(unsigned int a, unsigned int b, unsigned int * hi);\r\nunsigned __int64 mulx_u64(unsigned __int64 a, unsigned __int64 b, unsigned __int64 * hi);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nOther Exceptions\r\nSee Section 2.5.1, \"Exception Conditions for VEX-Encoded GPR Instructions\", Table 2-29; additionally\r\n#UD If VEX.W = 1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MULX"
},
{
"description": "MWAIT-Monitor Wait\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F 01 C9 MWAIT NP Valid Valid A hint that allow the processor to stop\r\n instruction execution and enter an\r\n implementation-dependent optimized state\r\n until occurrence of a class of events.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nMWAIT instruction provides hints to allow the processor to enter an implementation-dependent optimized state.\r\nThere are two principal targeted usages: address-range monitor and advanced power management. Both usages\r\nof MWAIT require the use of the MONITOR instruction.\r\nCPUID.01H:ECX.MONITOR[bit 3] indicates the availability of MONITOR and MWAIT in the processor. When set,\r\nMWAIT may be executed only at privilege level 0 (use at any other privilege level results in an invalid-opcode\r\nexception). The operating system or system BIOS may disable this instruction by using the IA32_MISC_ENABLE\r\nMSR; disabling MWAIT clears the CPUID feature flag and causes execution to generate an invalid-opcode excep-\r\ntion.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\nECX specifies optional extensions for the MWAIT instruction. EAX may contain hints such as the preferred optimized\r\nstate the processor should enter. The first processors to implement MWAIT supported only the zero value for EAX\r\nand ECX. Later processors allowed setting ECX[0] to enable masked interrupts as break events for MWAIT (see\r\nbelow). Software can use the CPUID instruction to determine the extensions and hints supported by the processor.\r\n\r\nMWAIT for Address Range Monitoring\r\nFor address-range monitoring, the MWAIT instruction operates with the MONITOR instruction. The two instructions\r\nallow the definition of an address at which to wait (MONITOR) and a implementation-dependent-optimized opera-\r\ntion to commence at the wait address (MWAIT). The execution of MWAIT is a hint to the processor that it can enter\r\nan implementation-dependent-optimized state while waiting for an event or a store operation to the address range\r\narmed by MONITOR.\r\nThe following cause the processor to exit the implementation-dependent-optimized state: a store to the address\r\nrange armed by the MONITOR instruction, an NMI or SMI, a debug exception, a machine check exception, the\r\nBINIT# signal, the INIT# signal, and the RESET# signal. Other implementation-dependent events may also cause\r\nthe processor to exit the implementation-dependent-optimized state.\r\nIn addition, an external interrupt causes the processor to exit the implementation-dependent-optimized state\r\neither (1) if the interrupt would be delivered to software (e.g., as it would be if HLT had been executed instead of\r\nMWAIT); or (2) if ECX[0] = 1. Software can execute MWAIT with ECX[0] = 1 only if CPUID.05H:ECX[bit 1] = 1.\r\n(Implementation-specific conditions may result in an interrupt causing the processor to exit the implementation-\r\ndependent-optimized state even if interrupts are masked and ECX[0] = 0.)\r\nFollowing exit from the implementation-dependent-optimized state, control passes to the instruction following the\r\nMWAIT instruction. A pending interrupt that is not masked (including an NMI or an SMI) may be delivered before\r\nexecution of that instruction. Unlike the HLT instruction, the MWAIT instruction does not support a restart at the\r\nMWAIT instruction following the handling of an SMI.\r\nIf the preceding MONITOR instruction did not successfully arm an address range or if the MONITOR instruction has\r\nnot been executed prior to executing MWAIT, then the processor will not enter the implementation-dependent-opti-\r\nmized state. Execution will resume at the instruction following the MWAIT.\r\n\r\n\r\n\r\n\r\n\r\nMWAIT for Power Management\r\nMWAIT accepts a hint and optional extension to the processor that it can enter a specified target C state while\r\nwaiting for an event or a store operation to the address range armed by MONITOR. Support for MWAIT extensions\r\nfor power management is indicated by CPUID.05H:ECX[bit 0] reporting 1.\r\nEAX and ECX are used to communicate the additional information to the MWAIT instruction, such as the kind of\r\noptimized state the processor should enter. ECX specifies optional extensions for the MWAIT instruction. EAX may\r\ncontain hints such as the preferred optimized state the processor should enter. Implementation-specific conditions\r\nmay cause a processor to ignore the hint and enter a different optimized state. Future processor implementations\r\nmay implement several optimized \"waiting\" states and will select among those states based on the hint argument.\r\nTable 4-10 describes the meaning of ECX and EAX registers for MWAIT extensions.\r\n\r\n\r\n Table 4-10. MWAIT Extension Register (ECX)\r\n Bits Description\r\n 0 Treat interrupts as break events even if masked (e.g., even if EFLAGS.IF=0). May be set only if\r\n CPUID.05H:ECX[bit 1] = 1.\r\n 31: 1 Reserved\r\n\r\n\r\n\r\n Table 4-11. MWAIT Hints Register (EAX)\r\n Bits Description\r\n 3:0 Sub C-state within a C-state, indicated by bits [7:4]\r\n 7:4 Target C-state*\r\n Value of 0 means C1; 1 means C2 and so on\r\n Value of 01111B means C0\r\n\r\n\r\n Note: Target C states for MWAIT extensions are processor-specific C-states, not ACPI C-states\r\n 31: 8 Reserved\r\n\r\nNote that if MWAIT is used to enter any of the C-states that are numerically higher than C1, a store to the address\r\nrange armed by the MONITOR instruction will cause the processor to exit MWAIT only if the store was originated by\r\nother processor agents. A store from non-processor agent might not cause the processor to exit MWAIT in such\r\ncases.\r\nFor additional details of MWAIT extensions, see Chapter 14, \"Power and Thermal Management,\" of Intel 64 and\r\nIA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\nOperation\r\n(* MWAIT takes the argument in EAX as a hint extension and is architected to take the argument in ECX as an instruction extension\r\nMWAIT EAX, ECX *)\r\n{\r\nWHILE ( (\"Monitor Hardware is in armed state\")) {\r\n implementation_dependent_optimized_state(EAX, ECX); }\r\nSet the state of Monitor Hardware as triggered;\r\n}\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nMWAIT: void _mm_mwait(unsigned extensions, unsigned hints)\r\n\r\n\r\n\r\n\r\n\r\nExample\r\nMONITOR/MWAIT instruction pair must be coded in the same loop because execution of the MWAIT instruction will\r\ntrigger the monitor hardware. It is not a proper usage to execute MONITOR once and then execute MWAIT in a\r\nloop. Setting up MONITOR without executing MWAIT has no adverse effects.\r\nTypically the MONITOR/MWAIT pair is used in a sequence, such as:\r\n\r\nEAX = Logical Address(Trigger)\r\nECX = 0 (*Hints *)\r\nEDX = 0 (* Hints *)\r\n\r\nIF ( !trigger_store_happened) {\r\n MONITOR EAX, ECX, EDX\r\n IF ( !trigger_store_happened ) {\r\n MWAIT EAX, ECX\r\n }\r\n}\r\nThe above code sequence makes sure that a triggering store does not happen between the first check of the trigger\r\nand the execution of the monitor instruction. Without the second check that triggering store would go un-noticed.\r\nTypical usage of MONITOR and MWAIT would have the above code sequence within a loop.\r\n\r\nNumeric Exceptions\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If ECX[31:1] != 0.\r\n If ECX[0] = 1 and CPUID.05H:ECX[bit 1] = 0.\r\n#UD If CPUID.01H:ECX.MONITOR[bit 3] = 0.\r\n If current privilege level is not 0.\r\n\r\nReal Address Mode Exceptions\r\n#GP If ECX[31:1] != 0.\r\n If ECX[0] = 1 and CPUID.05H:ECX[bit 1] = 0.\r\n#UD If CPUID.01H:ECX.MONITOR[bit 3] = 0.\r\n\r\nVirtual 8086 Mode Exceptions\r\n#UD The MWAIT instruction is not recognized in virtual-8086 mode (even if\r\n CPUID.01H:ECX.MONITOR[bit 3] = 1).\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If RCX[63:1] != 0.\r\n If RCX[0] = 1 and CPUID.05H:ECX[bit 1] = 0.\r\n#UD If the current privilege level is not 0.\r\n If CPUID.01H:ECX.MONITOR[bit 3] = 0.\r\n\r\n\r\n\r\n\r\n",
"mnem": "MWAIT"
},
{
"description": "NEG-Two's Complement Negation\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n F6 /3 NEG r/m8 M Valid Valid Two's complement negate r/m8.\r\n REX + F6 /3 NEG r/m8* M Valid N.E. Two's complement negate r/m8.\r\n F7 /3 NEG r/m16 M Valid Valid Two's complement negate r/m16.\r\n F7 /3 NEG r/m32 M Valid Valid Two's complement negate r/m32.\r\n REX.W + F7 /3 NEG r/m64 M Valid N.E. Two's complement negate r/m64.\r\n NOTES:\r\n * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (r, w) NA NA NA\r\n\r\n\r\nDescription\r\nReplaces the value of operand (the destination operand) with its two's complement. (This operation is equivalent\r\nto subtracting the operand from 0.) The destination operand is located in a general-purpose register or a memory\r\nlocation.\r\nThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nIF DEST = 0\r\n THEN CF <- 0;\r\n ELSE CF <- 1;\r\nFI;\r\nDEST <- [- (DEST)]\r\n\r\nFlags Affected\r\nThe CF flag set to 0 if the source operand is 0; otherwise it is set to 1. The OF, SF, ZF, AF, and PF flags are set\r\naccording to the result.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination is located in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nCompatibility Mode Exceptions\r\nSame as for protected mode exceptions.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) For a page fault.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n",
"mnem": "NEG"
},
{
"description": "NOP-No Operation\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 90 NOP NP Valid Valid One byte no-operation instruction.\r\n 0F 1F /0 NOP r/m16 M Valid Valid Multi-byte no-operation instruction.\r\n 0F 1F /0 NOP r/m32 M Valid Valid Multi-byte no-operation instruction.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n M ModRM:r/m (r) NA NA NA\r\n\r\n\r\nDescription\r\nThis instruction performs no operation. It is a one-byte or multi-byte NOP that takes up space in the instruction\r\nstream but does not impact machine context, except for the EIP register.\r\nThe multi-byte form of NOP is available on processors with model encoding:\r\n. CPUID.01H.EAX[Bytes 11:8] = 0110B or 1111B\r\nThe multi-byte NOP instruction does not alter the content of a register and will not issue a memory operation. The\r\ninstruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nThe one-byte NOP instruction is an alias mnemonic for the XCHG (E)AX, (E)AX instruction.\r\nThe multi-byte NOP instruction performs no operation on supported processors and generates undefined opcode\r\nexception on processors that do not support the multi-byte NOP instruction.\r\nThe memory operand form of the instruction allows software to create a byte sequence of \"no operation\" as one\r\ninstruction. For situations where multiple-byte NOPs are needed, the recommended operations (32-bit mode and\r\n64-bit mode) are:\r\n\r\n\r\n Table 4-12. Recommended Multi-Byte Sequence of NOP Instruction\r\n Length Assembly Byte Sequence\r\n 2 bytes 66 NOP 66 90H\r\n 3 bytes NOP DWORD ptr [EAX] 0F 1F 00H\r\n 4 bytes NOP DWORD ptr [EAX + 00H] 0F 1F 40 00H\r\n 5 bytes NOP DWORD ptr [EAX + EAX*1 + 00H] 0F 1F 44 00 00H\r\n 6 bytes 66 NOP DWORD ptr [EAX + EAX*1 + 00H] 66 0F 1F 44 00 00H\r\n 7 bytes NOP DWORD ptr [EAX + 00000000H] 0F 1F 80 00 00 00 00H\r\n 8 bytes NOP DWORD ptr [EAX + EAX*1 + 00000000H] 0F 1F 84 00 00 00 00 00H\r\n 9 bytes 66 NOP DWORD ptr [EAX + EAX*1 + 00000000H] 66 0F 1F 84 00 00 00 00 00H\r\n\r\n\r\nFlags Affected\r\nNone\r\n\r\nExceptions (All Operating Modes)\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "NOP"
},
{
"description": "NOT-One's Complement Negation\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n F6 /2 NOT r/m8 M Valid Valid Reverse each bit of r/m8.\r\n REX + F6 /2 NOT r/m8* M Valid N.E. Reverse each bit of r/m8.\r\n F7 /2 NOT r/m16 M Valid Valid Reverse each bit of r/m16.\r\n F7 /2 NOT r/m32 M Valid Valid Reverse each bit of r/m32.\r\n REX.W + F7 /2 NOT r/m64 M Valid N.E. Reverse each bit of r/m64.\r\n NOTES:\r\n * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (r, w) NA NA NA\r\n\r\n\r\nDescription\r\nPerforms a bitwise NOT operation (each 1 is set to 0, and each 0 is set to 1) on the destination operand and stores\r\nthe result in the destination operand location. The destination operand can be a register or a memory location.\r\nThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nDEST <- NOT DEST;\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination operand points to a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nCompatibility Mode Exceptions\r\nSame as for protected mode exceptions.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n",
"mnem": "NOT"
},
{
"description": "OR-Logical Inclusive OR\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0C ib OR AL, imm8 I Valid Valid AL OR imm8.\r\n 0D iw OR AX, imm16 I Valid Valid AX OR imm16.\r\n 0D id OR EAX, imm32 I Valid Valid EAX OR imm32.\r\n REX.W + 0D id OR RAX, imm32 I Valid N.E. RAX OR imm32 (sign-extended).\r\n 80 /1 ib OR r/m8, imm8 MI Valid Valid r/m8 OR imm8.\r\n REX + 80 /1 ib OR r/m8*, imm8 MI Valid N.E. r/m8 OR imm8.\r\n 81 /1 iw OR r/m16, imm16 MI Valid Valid r/m16 OR imm16.\r\n 81 /1 id OR r/m32, imm32 MI Valid Valid r/m32 OR imm32.\r\n REX.W + 81 /1 id OR r/m64, imm32 MI Valid N.E. r/m64 OR imm32 (sign-extended).\r\n 83 /1 ib OR r/m16, imm8 MI Valid Valid r/m16 OR imm8 (sign-extended).\r\n 83 /1 ib OR r/m32, imm8 MI Valid Valid r/m32 OR imm8 (sign-extended).\r\n REX.W + 83 /1 ib OR r/m64, imm8 MI Valid N.E. r/m64 OR imm8 (sign-extended).\r\n 08 /r OR r/m8, r8 MR Valid Valid r/m8 OR r8.\r\n REX + 08 /r OR r/m8*, r8* MR Valid N.E. r/m8 OR r8.\r\n 09 /r OR r/m16, r16 MR Valid Valid r/m16 OR r16.\r\n 09 /r OR r/m32, r32 MR Valid Valid r/m32 OR r32.\r\n REX.W + 09 /r OR r/m64, r64 MR Valid N.E. r/m64 OR r64.\r\n 0A /r OR r8, r/m8 RM Valid Valid r8 OR r/m8.\r\n REX + 0A /r OR r8*, r/m8* RM Valid N.E. r8 OR r/m8.\r\n 0B /r OR r16, r/m16 RM Valid Valid r16 OR r/m16.\r\n 0B /r OR r32, r/m32 RM Valid Valid r32 OR r/m32.\r\n REX.W + 0B /r OR r64, r/m64 RM Valid N.E. r64 OR r/m64.\r\n NOTES:\r\n * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n I AL/AX/EAX/RAX imm8/16/32 NA NA\r\n MI ModRM:r/m (r, w) imm8/16/32 NA NA\r\n MR ModRM:r/m (r, w) ModRM:reg (r) NA NA\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n\r\n\r\nDescription\r\nPerforms a bitwise inclusive OR operation between the destination (first) and source (second) operands and stores\r\nthe result in the destination operand location. The source operand can be an immediate, a register, or a memory\r\nlocation; the destination operand can be a register or a memory location. (However, two memory operands cannot\r\nbe used in one instruction.) Each bit of the result of the OR instruction is set to 0 if both corresponding bits of the\r\nfirst and second operands are 0; otherwise, each bit is set to 1.\r\nThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.\r\n\r\n\r\n\r\n\r\n\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nDEST <- DEST OR SRC;\r\n\r\nFlags Affected\r\nThe OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is\r\nundefined.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination operand points to a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nCompatibility Mode Exceptions\r\nSame as for protected mode exceptions.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n",
"mnem": "OR"
},
{
"description": "ORPD-Bitwise Logical OR of Packed Double Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0F 56/r RM V/V SSE2 Return the bitwise logical OR of packed double-precision\r\n ORPD xmm1, xmm2/m128 floating-point values in xmm1 and xmm2/mem.\r\n VEX.NDS.128.66.0F 56 /r RVM V/V AVX Return the bitwise logical OR of packed double-precision\r\n VORPD xmm1,xmm2, xmm3/m128 floating-point values in xmm2 and xmm3/mem.\r\n VEX.NDS.256.66.0F 56 /r RVM V/V AVX Return the bitwise logical OR of packed double-precision\r\n VORPD ymm1, ymm2, ymm3/m256 floating-point values in ymm2 and ymm3/mem.\r\n EVEX.NDS.128.66.0F.W1 56 /r FV V/V AVX512VL Return the bitwise logical OR of packed double-precision\r\n VORPD xmm1 {k1}{z}, xmm2, AVX512DQ floating-point values in xmm2 and xmm3/m128/m64bcst\r\n xmm3/m128/m64bcst subject to writemask k1.\r\n EVEX.NDS.256.66.0F.W1 56 /r FV V/V AVX512VL Return the bitwise logical OR of packed double-precision\r\n VORPD ymm1 {k1}{z}, ymm2, AVX512DQ floating-point values in ymm2 and ymm3/m256/m64bcst\r\n ymm3/m256/m64bcst subject to writemask k1.\r\n EVEX.NDS.512.66.0F.W1 56 /r FV V/V AVX512DQ Return the bitwise logical OR of packed double-precision\r\n VORPD zmm1 {k1}{z}, zmm2, floating-point values in zmm2 and zmm3/m512/m64bcst\r\n zmm3/m512/m64bcst subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a bitwise logical OR of the two, four or eight packed double-precision floating-point values from the first\r\nsource operand and the second source operand, and stores the result in the destination operand.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be\r\na ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a\r\n32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with\r\nwritemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register\r\nor a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the\r\ncorresponding ZMM register destination are zeroed.\r\nVEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM\r\nregister or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nregister destination are unmodified.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVORPD (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b == 1) AND (SRC2 *is memory*)\r\n THEN\r\n DEST[i+63:i] <- SRC1[i+63:i] BITWISE OR SRC2[63:0]\r\n ELSE\r\n DEST[i+63:i] <- SRC1[i+63:i] BITWISE OR SRC2[i+63:i]\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVORPD (VEX.256 encoded version)\r\nDEST[63:0] <- SRC1[63:0] BITWISE OR SRC2[63:0]\r\nDEST[127:64] <- SRC1[127:64] BITWISE OR SRC2[127:64]\r\nDEST[191:128] <- SRC1[191:128] BITWISE OR SRC2[191:128]\r\nDEST[255:192] <- SRC1[255:192] BITWISE OR SRC2[255:192]\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVORPD (VEX.128 encoded version)\r\nDEST[63:0] <- SRC1[63:0] BITWISE OR SRC2[63:0]\r\nDEST[127:64] <- SRC1[127:64] BITWISE OR SRC2[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nORPD (128-bit Legacy SSE version)\r\nDEST[63:0] <- DEST[63:0] BITWISE OR SRC[63:0]\r\nDEST[127:64] <- DEST[127:64] BITWISE OR SRC[127:64]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVORPD __m512d _mm512_or_pd ( __m512d a, __m512d b);\r\nVORPD __m512d _mm512_mask_or_pd ( __m512d s, __mmask8 k, __m512d a, __m512d b);\r\nVORPD __m512d _mm512_maskz_or_pd (__mmask8 k, __m512d a, __m512d b);\r\nVORPD __m256d _mm256_mask_or_pd (__m256d s, ___mmask8 k, __m256d a, __m256d b);\r\nVORPD __m256d _mm256_maskz_or_pd (__mmask8 k, __m256d a, __m256d b);\r\nVORPD __m128d _mm_mask_or_pd ( __m128d s, __mmask8 k, __m128d a, __m128d b);\r\nVORPD __m128d _mm_maskz_or_pd (__mmask8 k, __m128d a, __m128d b);\r\nVORPD __m256d _mm256_or_pd (__m256d a, __m256d b);\r\nORPD __m128d _mm_or_pd (__m128d a, __m128d b);\r\n\r\n\r\n\r\n\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "ORPD"
},
{
"description": "ORPS-Bitwise Logical OR of Packed Single Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 0F 56 /r RM V/V SSE Return the bitwise logical OR of packed single-precision\r\n ORPS xmm1, xmm2/m128 floating-point values in xmm1 and xmm2/mem.\r\n VEX.NDS.128.0F 56 /r RVM V/V AVX Return the bitwise logical OR of packed single-precision\r\n VORPS xmm1,xmm2, xmm3/m128 floating-point values in xmm2 and xmm3/mem.\r\n VEX.NDS.256.0F 56 /r RVM V/V AVX Return the bitwise logical OR of packed single-precision\r\n VORPS ymm1, ymm2, ymm3/m256 floating-point values in ymm2 and ymm3/mem.\r\n EVEX.NDS.128.0F.W0 56 /r FV V/V AVX512VL Return the bitwise logical OR of packed single-precision\r\n VORPS xmm1 {k1}{z}, xmm2, AVX512DQ floating-point values in xmm2 and xmm3/m128/m32bcst\r\n xmm3/m128/m32bcst subject to writemask k1.\r\n EVEX.NDS.256.0F.W0 56 /r FV V/V AVX512VL Return the bitwise logical OR of packed single-precision\r\n VORPS ymm1 {k1}{z}, ymm2, AVX512DQ floating-point values in ymm2 and ymm3/m256/m32bcst\r\n ymm3/m256/m32bcst subject to writemask k1.\r\n EVEX.NDS.512.0F.W0 56 /r FV V/V AVX512DQ Return the bitwise logical OR of packed single-precision\r\n VORPS zmm1 {k1}{z}, zmm2, floating-point values in zmm2 and zmm3/m512/m32bcst\r\n zmm3/m512/m32bcst subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a bitwise logical OR of the four, eight or sixteen packed single-precision floating-point values from the\r\nfirst source operand and the second source operand, and stores the result in the destination operand\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be\r\na ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a\r\n32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with\r\nwritemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register\r\nor a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the\r\ncorresponding ZMM register destination are zeroed.\r\nVEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM\r\nregister or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nregister destination are unmodified.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVORPS (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b == 1) AND (SRC2 *is memory*)\r\n THEN\r\n DEST[i+31:i] <- SRC1[i+31:i] BITWISE OR SRC2[31:0]\r\n ELSE\r\n DEST[i+31:i] <- SRC1[i+31:i] BITWISE OR SRC2[i+31:i]\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVORPS (VEX.256 encoded version)\r\nDEST[31:0] <- SRC1[31:0] BITWISE OR SRC2[31:0]\r\nDEST[63:32] <- SRC1[63:32] BITWISE OR SRC2[63:32]\r\nDEST[95:64] <- SRC1[95:64] BITWISE OR SRC2[95:64]\r\nDEST[127:96] <- SRC1[127:96] BITWISE OR SRC2[127:96]\r\nDEST[159:128] <- SRC1[159:128] BITWISE OR SRC2[159:128]\r\nDEST[191:160] <- SRC1[191:160] BITWISE OR SRC2[191:160]\r\nDEST[223:192] <- SRC1[223:192] BITWISE OR SRC2[223:192]\r\nDEST[255:224] <- SRC1[255:224] BITWISE OR SRC2[255:224].\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVORPS (VEX.128 encoded version)\r\nDEST[31:0] <- SRC1[31:0] BITWISE OR SRC2[31:0]\r\nDEST[63:32] <- SRC1[63:32] BITWISE OR SRC2[63:32]\r\nDEST[95:64] <- SRC1[95:64] BITWISE OR SRC2[95:64]\r\nDEST[127:96] <- SRC1[127:96] BITWISE OR SRC2[127:96]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nORPS (128-bit Legacy SSE version)\r\nDEST[31:0] <- SRC1[31:0] BITWISE OR SRC2[31:0]\r\nDEST[63:32] <- SRC1[63:32] BITWISE OR SRC2[63:32]\r\nDEST[95:64] <- SRC1[95:64] BITWISE OR SRC2[95:64]\r\nDEST[127:96] <- SRC1[127:96] BITWISE OR SRC2[127:96]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVORPS __m512 _mm512_or_ps ( __m512 a, __m512 b);\r\nVORPS __m512 _mm512_mask_or_ps ( __m512 s, __mmask16 k, __m512 a, __m512 b);\r\nVORPS __m512 _mm512_maskz_or_ps (__mmask16 k, __m512 a, __m512 b);\r\nVORPS __m256 _mm256_mask_or_ps (__m256 s, ___mmask8 k, __m256 a, __m256 b);\r\nVORPS __m256 _mm256_maskz_or_ps (__mmask8 k, __m256 a, __m256 b);\r\nVORPS __m128 _mm_mask_or_ps ( __m128 s, __mmask8 k, __m128 a, __m128 b);\r\nVORPS __m128 _mm_maskz_or_ps (__mmask8 k, __m128 a, __m128 b);\r\nVORPS __m256 _mm256_or_ps (__m256 a, __m256 b);\r\nORPS __m128 _mm_or_ps (__m128 a, __m128 b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "ORPS"
},
{
"description": "OUT-Output to Port\r\n Opcode* Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n E6 ib OUT imm8, AL I Valid Valid Output byte in AL to I/O port address imm8.\r\n E7 ib OUT imm8, AX I Valid Valid Output word in AX to I/O port address imm8.\r\n E7 ib OUT imm8, EAX I Valid Valid Output doubleword in EAX to I/O port address\r\n imm8.\r\n EE OUT DX, AL NP Valid Valid Output byte in AL to I/O port address in DX.\r\n EF OUT DX, AX NP Valid Valid Output word in AX to I/O port address in DX.\r\n EF OUT DX, EAX NP Valid Valid Output doubleword in EAX to I/O port address\r\n in DX.\r\n NOTES:\r\n * See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n I imm8 NA NA NA\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nCopies the value from the second operand (source operand) to the I/O port specified with the destination operand\r\n(first operand). The source operand can be register AL, AX, or EAX, depending on the size of the port being\r\naccessed (8, 16, or 32 bits, respectively); the destination operand can be a byte-immediate or the DX register.\r\nUsing a byte immediate allows I/O port addresses 0 to 255 to be accessed; using the DX register as a source\r\noperand allows I/O ports from 0 to 65,535 to be accessed.\r\nThe size of the I/O port being accessed is determined by the opcode for an 8-bit I/O port or by the operand-size\r\nattribute of the instruction for a 16- or 32-bit I/O port.\r\nAt the machine code level, I/O instructions are shorter when accessing 8-bit I/O ports. Here, the upper eight bits\r\nof the port address will be 0.\r\nThis instruction is only useful for accessing I/O ports located in the processor's I/O address space. See Chapter 18,\r\n\"Input/Output,\" in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for more infor-\r\nmation on accessing I/O ports in the I/O address space.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nIA-32 Architecture Compatibility\r\nAfter executing an OUT instruction, the Pentium processor ensures that the EWBE# pin has been sampled active\r\nbefore it begins to execute the next instruction. (Note that the instruction can be prefetched if EWBE# is not active,\r\nbut it will not be executed until the EWBE# pin is sampled active.) Only the Pentium processor family has the\r\nEWBE# pin.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIF ((PE = 1) and ((CPL > IOPL) or (VM = 1)))\r\n THEN (* Protected mode with CPL > IOPL or virtual-8086 mode *)\r\n IF (Any I/O Permission Bit for I/O port being accessed = 1)\r\n THEN (* I/O operation is not allowed *)\r\n #GP(0);\r\n ELSE ( * I/O operation is allowed *)\r\n DEST <- SRC; (* Writes to selected I/O port *)\r\n FI;\r\n ELSE (Real Mode or Protected Mode with CPL <= IOPL *)\r\n DEST <- SRC; (* Writes to selected I/O port *)\r\nFI;\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the\r\n corresponding I/O permission bits in TSS for the I/O port being accessed is 1.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If any of the I/O permission bits in the TSS for the I/O port being accessed is 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame as protected mode exceptions.\r\n\r\n64-Bit Mode Exceptions\r\nSame as protected mode exceptions.\r\n\r\n\r\n\r\n\r\n",
"mnem": "OUT"
},
{
"description": "OUTS/OUTSB/OUTSW/OUTSD-Output String to Port\r\n Opcode* Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 6E OUTS DX, m8 NP Valid Valid Output byte from memory location specified\r\n in DS:(E)SI or RSI to I/O port specified in DX**.\r\n 6F OUTS DX, m16 NP Valid Valid Output word from memory location specified\r\n in DS:(E)SI or RSI to I/O port specified in DX**.\r\n 6F OUTS DX, m32 NP Valid Valid Output doubleword from memory location\r\n specified in DS:(E)SI or RSI to I/O port specified\r\n in DX**.\r\n 6E OUTSB NP Valid Valid Output byte from memory location specified\r\n in DS:(E)SI or RSI to I/O port specified in DX**.\r\n 6F OUTSW NP Valid Valid Output word from memory location specified\r\n in DS:(E)SI or RSI to I/O port specified in DX**.\r\n 6F OUTSD NP Valid Valid Output doubleword from memory location\r\n specified in DS:(E)SI or RSI to I/O port specified\r\n in DX**.\r\n NOTES:\r\n * See IA-32 Architecture Compatibility section below.\r\n ** In 64-bit mode, only 64-bit (RSI) and 32-bit (ESI) address sizes are supported. In non-64-bit mode, only 32-bit (ESI) and 16-bit (SI)\r\n address sizes are supported.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nCopies data from the source operand (second operand) to the I/O port specified with the destination operand (first\r\noperand). The source operand is a memory location, the address of which is read from either the DS:SI, DS:ESI or\r\nthe RSI registers (depending on the address-size attribute of the instruction, 16, 32 or 64, respectively). (The DS\r\nsegment may be overridden with a segment override prefix.) The destination operand is an I/O port address (from\r\n0 to 65,535) that is read from the DX register. The size of the I/O port being accessed (that is, the size of the source\r\nand destination operands) is determined by the opcode for an 8-bit I/O port or by the operand-size attribute of the\r\ninstruction for a 16- or 32-bit I/O port.\r\nAt the assembly-code level, two forms of this instruction are allowed: the \"explicit-operands\" form and the \"no-\r\noperands\" form. The explicit-operands form (specified with the OUTS mnemonic) allows the source and destination\r\noperands to be specified explicitly. Here, the source operand should be a symbol that indicates the size of the I/O\r\nport and the source address, and the destination operand must be DX. This explicit-operands form is provided to\r\nallow documentation; however, note that the documentation provided by this form can be misleading. That is, the\r\nsource operand symbol must specify the correct type (size) of the operand (byte, word, or doubleword), but it does\r\nnot have to specify the correct location. The location is always specified by the DS:(E)SI or RSI registers, which\r\nmust be loaded correctly before the OUTS instruction is executed.\r\nThe no-operands form provides \"short forms\" of the byte, word, and doubleword versions of the OUTS instructions.\r\nHere also DS:(E)SI is assumed to be the source operand and DX is assumed to be the destination operand. The size\r\nof the I/O port is specified with the choice of mnemonic: OUTSB (byte), OUTSW (word), or OUTSD (doubleword).\r\nAfter the byte, word, or doubleword is transferred from the memory location to the I/O port, the SI/ESI/RSI\r\nregister is incremented or decremented automatically according to the setting of the DF flag in the EFLAGS register.\r\n(If the DF flag is 0, the (E)SI register is incremented; if the DF flag is 1, the SI/ESI/RSI register is decremented.)\r\nThe SI/ESI/RSI register is incremented or decremented by 1 for byte operations, by 2 for word operations, and by\r\n4 for doubleword operations.\r\n\r\n\r\n\r\n\r\nThe OUTS, OUTSB, OUTSW, and OUTSD instructions can be preceded by the REP prefix for block input of ECX\r\nbytes, words, or doublewords. See \"REP/REPE/REPZ /REPNE/REPNZ-Repeat String Operation Prefix\" in this\r\nchapter for a description of the REP prefix. This instruction is only useful for accessing I/O ports located in the\r\nprocessor's I/O address space. See Chapter 18, \"Input/Output,\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 1, for more information on accessing I/O ports in the I/O address space.\r\nIn 64-bit mode, the default operand size is 32 bits; operand size is not promoted by the use of REX.W. In 64-bit\r\nmode, the default address size is 64 bits, and 64-bit address is specified using RSI by default. 32-bit address using\r\nESI is support using the prefix 67H, but 16-bit address is not supported in 64-bit mode.\r\n\r\nIA-32 Architecture Compatibility\r\nAfter executing an OUTS, OUTSB, OUTSW, or OUTSD instruction, the Pentium processor ensures that the EWBE#\r\npin has been sampled active before it begins to execute the next instruction. (Note that the instruction can be\r\nprefetched if EWBE# is not active, but it will not be executed until the EWBE# pin is sampled active.) Only the\r\nPentium processor family has the EWBE# pin.\r\nFor the Pentium 4, Intel Xeon, and P6 processor family, upon execution of an OUTS, OUTSB, OUTSW, or OUTSD\r\ninstruction, the processor will not execute the next instruction until the data phase of the transaction is complete.\r\n\r\nOperation\r\nIF ((PE = 1) and ((CPL > IOPL) or (VM = 1)))\r\n THEN (* Protected mode with CPL > IOPL or virtual-8086 mode *)\r\n IF (Any I/O Permission Bit for I/O port being accessed = 1)\r\n THEN (* I/O operation is not allowed *)\r\n #GP(0);\r\n ELSE (* I/O operation is allowed *)\r\n DEST <- SRC; (* Writes to I/O port *)\r\n FI;\r\n ELSE (Real Mode or Protected Mode or 64-Bit Mode with CPL <= IOPL *)\r\n DEST <- SRC; (* Writes to I/O port *)\r\nFI;\r\n\r\nByte transfer:\r\n IF 64-bit mode\r\n Then\r\n IF 64-Bit Address Size\r\n THEN\r\n IF DF = 0\r\n THEN RSI <- RSI RSI + 1;\r\n ELSE RSI <- RSI or - 1;\r\n FI;\r\n ELSE (* 32-Bit Address Size *)\r\n IF DF = 0\r\n THEN ESI <- ESI + 1;\r\n ELSE ESI <- ESI - 1;\r\n FI;\r\n FI;\r\n ELSE\r\n IF DF = 0\r\n THEN (E)SI <- (E)SI + 1;\r\n ELSE (E)SI <- (E)SI - 1;\r\n FI;\r\n FI;\r\nWord transfer:\r\n IF 64-bit mode\r\n\r\n\r\n\r\n Then\r\n IF 64-Bit Address Size\r\n THEN\r\n IF DF = 0\r\n THEN RSI <- RSI RSI + 2;\r\n ELSE RSI <- RSI or - 2;\r\n FI;\r\n ELSE (* 32-Bit Address Size *)\r\n IF DF = 0\r\n THEN ESI <- ESI + 2;\r\n ELSE ESI <- ESI - 2;\r\n FI;\r\n FI;\r\n ELSE\r\n IF DF = 0\r\n THEN (E)SI <- (E)SI + 2;\r\n ELSE (E)SI <- (E)SI - 2;\r\n FI;\r\n FI;\r\nDoubleword transfer:\r\n IF 64-bit mode\r\n Then\r\n IF 64-Bit Address Size\r\n THEN\r\n IF DF = 0\r\n THEN RSI <- RSI RSI + 4;\r\n ELSE RSI <- RSI or - 4;\r\n FI;\r\n ELSE (* 32-Bit Address Size *)\r\n IF DF = 0\r\n THEN ESI <- ESI + 4;\r\n ELSE ESI <- ESI - 4;\r\n FI;\r\n FI;\r\n ELSE\r\n IF DF = 0\r\n THEN (E)SI <- (E)SI + 4;\r\n ELSE (E)SI <- (E)SI - 4;\r\n FI;\r\n FI;\r\n\r\nFlags Affected\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the\r\n corresponding I/O permission bits in TSS for the I/O port being accessed is 1.\r\n If a memory operand effective address is outside the limit of the CS, DS, ES, FS, or GS\r\n segment.\r\n If the segment register contains a NULL segment selector.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If any of the I/O permission bits in the TSS for the I/O port being accessed is 1.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame as for protected mode exceptions.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the\r\n corresponding I/O permission bits in TSS for the I/O port being accessed is 1.\r\n If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "OUTS"
},
{
"description": "-R:OUTS",
"mnem": "OUTSB"
},
{
"description": "-R:OUTS",
"mnem": "OUTSD"
},
{
"description": "-R:OUTS",
"mnem": "OUTSW"
},
{
"description": "PABSB/PABSW/PABSD/PABSQ - Packed Absolute Value\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F 38 1C /r1 RM V/V SSSE3 Compute the absolute value of bytes in\r\nPABSB mm1, mm2/m64 mm2/m64 and store UNSIGNED result in mm1.\r\n\r\n66 0F 38 1C /r RM V/V SSSE3 Compute the absolute value of bytes in\r\nPABSB xmm1, xmm2/m128 xmm2/m128 and store UNSIGNED result in\r\n xmm1.\r\n0F 38 1D /r1 RM V/V SSSE3 Compute the absolute value of 16-bit integers\r\nPABSW mm1, mm2/m64 in mm2/m64 and store UNSIGNED result in\r\n mm1.\r\n66 0F 38 1D /r RM V/V SSSE3 Compute the absolute value of 16-bit integers\r\nPABSW xmm1, xmm2/m128 in xmm2/m128 and store UNSIGNED result in\r\n xmm1.\r\n0F 38 1E /r1 RM V/V SSSE3 Compute the absolute value of 32-bit integers\r\nPABSD mm1, mm2/m64 in mm2/m64 and store UNSIGNED result in\r\n mm1.\r\n66 0F 38 1E /r RM V/V SSSE3 Compute the absolute value of 32-bit integers\r\nPABSD xmm1, xmm2/m128 in xmm2/m128 and store UNSIGNED result in\r\n xmm1.\r\nVEX.128.66.0F38.WIG 1C /r RM V/V AVX Compute the absolute value of bytes in\r\nVPABSB xmm1, xmm2/m128 xmm2/m128 and store UNSIGNED result in\r\n xmm1.\r\nVEX.128.66.0F38.WIG 1D /r RM V/V AVX Compute the absolute value of 16- bit\r\nVPABSW xmm1, xmm2/m128 integers in xmm2/m128 and store UNSIGNED\r\n result in xmm1.\r\nVEX.128.66.0F38.WIG 1E /r RM V/V AVX Compute the absolute value of 32- bit\r\nVPABSD xmm1, xmm2/m128 integers in xmm2/m128 and store UNSIGNED\r\n result in xmm1.\r\nVEX.256.66.0F38.WIG 1C /r RM V/V AVX2 Compute the absolute value of bytes in\r\nVPABSB ymm1, ymm2/m256 ymm2/m256 and store UNSIGNED result in\r\n ymm1.\r\nVEX.256.66.0F38.WIG 1D /r RM V/V AVX2 Compute the absolute value of 16-bit integers\r\nVPABSW ymm1, ymm2/m256 in ymm2/m256 and store UNSIGNED result in\r\n ymm1.\r\nVEX.256.66.0F38.WIG 1E /r RM V/V AVX2 Compute the absolute value of 32-bit integers\r\nVPABSD ymm1, ymm2/m256 in ymm2/m256 and store UNSIGNED result in\r\n ymm1.\r\nEVEX.128.66.0F38.WIG 1C /r FVM V/V AVX512VL Compute the absolute value of bytes in\r\nVPABSB xmm1 {k1}{z}, xmm2/m128 AVX512BW xmm2/m128 and store UNSIGNED result in\r\n xmm1 using writemask k1.\r\nEVEX.256.66.0F38.WIG 1C /r FVM V/V AVX512VL Compute the absolute value of bytes in\r\nVPABSB ymm1 {k1}{z}, ymm2/m256 AVX512BW ymm2/m256 and store UNSIGNED result in\r\n ymm1 using writemask k1.\r\nEVEX.512.66.0F38.WIG 1C /r FVM V/V AVX512BW Compute the absolute value of bytes in\r\nVPABSB zmm1 {k1}{z}, zmm2/m512 zmm2/m512 and store UNSIGNED result in\r\n zmm1 using writemask k1.\r\nEVEX.128.66.0F38.WIG 1D /r FVM V/V AVX512VL Compute the absolute value of 16-bit integers\r\nVPABSW xmm1 {k1}{z}, xmm2/m128 AVX512BW in xmm2/m128 and store UNSIGNED result in\r\n xmm1 using writemask k1.\r\n\r\n\r\n\r\n\r\nEVEX.256.66.0F38.WIG 1D /r FVM V/V AVX512VL Compute the absolute value of 16-bit integers\r\nVPABSW ymm1 {k1}{z}, ymm2/m256 AVX512BW in ymm2/m256 and store UNSIGNED result in\r\n ymm1 using writemask k1.\r\nEVEX.512.66.0F38.WIG 1D /r FVM V/V AVX512BW Compute the absolute value of 16-bit integers\r\nVPABSW zmm1 {k1}{z}, zmm2/m512 in zmm2/m512 and store UNSIGNED result in\r\n zmm1 using writemask k1.\r\nEVEX.128.66.0F38.W0 1E /r FV V/V AVX512VL Compute the absolute value of 32-bit integers\r\nVPABSD xmm1 {k1}{z}, xmm2/m128/m32bcst AVX512F in xmm2/m128/m32bcst and store UNSIGNED\r\n result in xmm1 using writemask k1.\r\nEVEX.256.66.0F38.W0 1E /r FV V/V AVX512VL Compute the absolute value of 32-bit integers\r\nVPABSD ymm1 {k1}{z}, ymm2/m256/m32bcst AVX512F in ymm2/m256/m32bcst and store UNSIGNED\r\n result in ymm1 using writemask k1.\r\nVPABSD zmm1 {k1}{z}, zmm2/m512/m32bcst FV V/V AVX512F Compute the absolute value of 32-bit integers\r\n in zmm2/m512/m32bcst and store UNSIGNED\r\n result in zmm1 using writemask k1.\r\nEVEX.128.66.0F38.W1 1F /r FV V/V AVX512VL Compute the absolute value of 64-bit integers\r\nVPABSQ xmm1 {k1}{z}, xmm2/m128/m64bcst AVX512F in xmm2/m128/m64bcst and store UNSIGNED\r\n result in xmm1 using writemask k1.\r\nEVEX.256.66.0F38.W1 1F /r FV V/V AVX512VL Compute the absolute value of 64-bit integers\r\nVPABSQ ymm1 {k1}{z}, ymm2/m256/m64bcst AVX512F in ymm2/m256/m64bcst and store UNSIGNED\r\n result in ymm1 using writemask k1.\r\nEVEX.512.66.0F38.W1 1F /r FV V/V AVX512F Compute the absolute value of 64-bit integers\r\nVPABSQ zmm1 {k1}{z}, zmm2/m512/m64bcst in zmm2/m512/m64bcst and store UNSIGNED\r\n result in zmm1 using writemask k1.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n FVM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\n\r\nDescription\r\nPABSB/W/D computes the absolute value of each data element of the source operand (the second operand) and\r\nstores the UNSIGNED results in the destination operand (the first operand). PABSB operates on signed bytes,\r\nPABSW operates on signed 16-bit words, and PABSD operates on signed 32-bit integers.\r\nEVEX encoded VPABSD/Q: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location,\r\nor a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a\r\nZMM/YMM/XMM register updated according to the writemask.\r\nEVEX encoded VPABSB/W: The source operand is a ZMM/YMM/XMM register, or a 512/256/128-bit memory loca-\r\ntion. The destination operand is a ZMM/YMM/XMM register updated according to the writemask.\r\nVEX.256 encoded versions: The source operand is a YMM register or a 256-bit memory location. The destination\r\noperand is a YMM register. The upper bits (MAX_VL-1:256) of the corresponding register destination are zeroed.\r\nVEX.128 encoded versions: The source operand is an XMM register or 128-bit memory location. The destination\r\noperand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding register destination are zeroed.\r\n\r\n\r\n\r\n\r\n\r\n128-bit Legacy SSE version: The source operand can be an XMM register or an 128-bit memory location. The desti-\r\nnation is an XMM register. The upper bits (VL_MAX-1:128) of the corresponding register destination are unmodi-\r\nfied.\r\nVEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\n\r\nOperation\r\nPABSB with 128 bit operands:\r\n Unsigned DEST[7:0] <-ABS(SRC[7: 0])\r\n Repeat operation for 2nd through 15th bytes\r\n Unsigned DEST[127:120] <-ABS(SRC[127:120])\r\n\r\nVPABSB with 128 bit operands:\r\n Unsigned DEST[7:0] <-ABS(SRC[7: 0])\r\n Repeat operation for 2nd through 15th bytes\r\n Unsigned DEST[127:120]<-ABS(SRC[127:120])\r\n\r\nVPABSB with 256 bit operands:\r\n Unsigned DEST[7:0]<-ABS(SRC[7: 0])\r\n Repeat operation for 2nd through 31st bytes\r\n Unsigned DEST[255:248]<-ABS(SRC[255:248])\r\n\r\nVPABSB (EVEX encoded versions)\r\n (KL, VL) = (16, 128), (32, 256), (64, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i<-j*8\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n Unsigned DEST[i+7:i] <- ABS(SRC[i+7:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+7:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nPABSW with 128 bit operands:\r\n Unsigned DEST[15:0]<-ABS(SRC[15:0])\r\n Repeat operation for 2nd through 7th 16-bit words\r\n Unsigned DEST[127:112]<-ABS(SRC[127:112])\r\n\r\nVPABSW with 128 bit operands:\r\n Unsigned DEST[15:0] <-ABS(SRC[15:0])\r\n Repeat operation for 2nd through 7th 16-bit words\r\n Unsigned DEST[127:112]<-ABS(SRC[127:112])\r\n\r\nVPABSW with 256 bit operands:\r\n Unsigned DEST[15:0]<-ABS(SRC[15:0])\r\n Repeat operation for 2nd through 15th 16-bit words\r\n Unsigned DEST[255:240] <-ABS(SRC[255:240])\r\n\r\n\r\n\r\n\r\nVPABSW (EVEX encoded versions)\r\n (KL, VL) = (8, 128), (16, 256), (32, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n Unsigned DEST[i+15:i] <- ABS(SRC[i+15:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nPABSD with 128 bit operands:\r\n Unsigned DEST[31:0]<-ABS(SRC[31:0])\r\n Repeat operation for 2nd through 3rd 32-bit double words\r\n Unsigned DEST[127:96]<-ABS(SRC[127:96])\r\n\r\nVPABSD with 128 bit operands:\r\n Unsigned DEST[31:0]<-ABS(SRC[31:0])\r\n Repeat operation for 2nd through 3rd 32-bit double words\r\n Unsigned DEST[127:96]<-ABS(SRC[127:96])\r\n\r\nVPABSD with 256 bit operands:\r\n Unsigned DEST[31:0] <-ABS(SRC[31:0])\r\n Repeat operation for 2nd through 7th 32-bit double words\r\n Unsigned DEST[255:224] <-ABS(SRC[255:224])\r\n\r\nVPABSD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC *is memory*)\r\n THEN\r\n Unsigned DEST[i+31:i] <- ABS(SRC[31:0])\r\n ELSE\r\n Unsigned DEST[i+31:i] <- ABS(SRC[i+31:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\nVPABSQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC *is memory*)\r\n THEN\r\n Unsigned DEST[i+63:i] <- ABS(SRC[63:0])\r\n ELSE\r\n Unsigned DEST[i+63:i] <- ABS(SRC[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPABSB__m512i _mm512_abs_epi8 ( __m512i a)\r\nVPABSW__m512i _mm512_abs_epi16 ( __m512i a)\r\nVPABSB__m512i _mm512_mask_abs_epi8 ( __m512i s, __mmask64 m, __m512i a)\r\nVPABSW__m512i _mm512_mask_abs_epi16 ( __m512i s, __mmask32 m, __m512i a)\r\nVPABSB__m512i _mm512_maskz_abs_epi8 (__mmask64 m, __m512i a)\r\nVPABSW__m512i _mm512_maskz_abs_epi16 (__mmask32 m, __m512i a)\r\nVPABSB__m256i _mm256_mask_abs_epi8 (__m256i s, __mmask32 m, __m256i a)\r\nVPABSW__m256i _mm256_mask_abs_epi16 (__m256i s, __mmask16 m, __m256i a)\r\nVPABSB__m256i _mm256_maskz_abs_epi8 (__mmask32 m, __m256i a)\r\nVPABSW__m256i _mm256_maskz_abs_epi16 (__mmask16 m, __m256i a)\r\nVPABSB__m128i _mm_mask_abs_epi8 (__m128i s, __mmask16 m, __m128i a)\r\nVPABSW__m128i _mm_mask_abs_epi16 (__m128i s, __mmask8 m, __m128i a)\r\nVPABSB__m128i _mm_maskz_abs_epi8 (__mmask16 m, __m128i a)\r\nVPABSW__m128i _mm_maskz_abs_epi16 (__mmask8 m, __m128i a)\r\nVPABSD __m256i _mm256_mask_abs_epi32(__m256i s, __mmask8 k, __m256i a);\r\nVPABSD __m256i _mm256_maskz_abs_epi32( __mmask8 k, __m256i a);\r\nVPABSD __m128i _mm_mask_abs_epi32(__m128i s, __mmask8 k, __m128i a);\r\nVPABSD __m128i _mm_maskz_abs_epi32( __mmask8 k, __m128i a);\r\nVPABSD __m512i _mm512_abs_epi32( __m512i a);\r\nVPABSD __m512i _mm512_mask_abs_epi32(__m512i s, __mmask16 k, __m512i a);\r\nVPABSD __m512i _mm512_maskz_abs_epi32( __mmask16 k, __m512i a);\r\nVPABSQ __m512i _mm512_abs_epi64( __m512i a);\r\nVPABSQ __m512i _mm512_mask_abs_epi64(__m512i s, __mmask8 k, __m512i a);\r\nVPABSQ __m512i _mm512_maskz_abs_epi64( __mmask8 k, __m512i a);\r\nVPABSQ __m256i _mm256_mask_abs_epi64(__m256i s, __mmask8 k, __m256i a);\r\nVPABSQ __m256i _mm256_maskz_abs_epi64( __mmask8 k, __m256i a);\r\nVPABSQ __m128i _mm_mask_abs_epi64(__m128i s, __mmask8 k, __m128i a);\r\nVPABSQ __m128i _mm_maskz_abs_epi64( __mmask8 k, __m128i a);\r\nPABSB __m128i _mm_abs_epi8 (__m128i a)\r\nVPABSB __m128i _mm_abs_epi8 (__m128i a)\r\n\r\n\r\n\r\nVPABSB __m256i _mm256_abs_epi8 (__m256i a)\r\nPABSW __m128i _mm_abs_epi16 (__m128i a)\r\nVPABSW __m128i _mm_abs_epi16 (__m128i a)\r\nVPABSW __m256i _mm256_abs_epi16 (__m256i a)\r\nPABSD __m128i _mm_abs_epi32 (__m128i a)\r\nVPABSD __m128i _mm_abs_epi32 (__m128i a)\r\nVPABSD __m256i _mm256_abs_epi32 (__m256i a)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded VPABSD/Q, see Exceptions Type E4.\r\nEVEX-encoded VPABSB/W, see Exceptions Type E4.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PABSB"
},
{
"description": "-R:PABSB",
"mnem": "PABSD"
},
{
"description": "-R:PABSB",
"mnem": "PABSQ"
},
{
"description": "-R:PABSB",
"mnem": "PABSW"
},
{
"description": "-R:PACKSSWB",
"mnem": "PACKSSDW"
},
{
"description": "PACKSSWB/PACKSSDW-Pack with Signed Saturation\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature Flag\r\n Support\r\n0F 63 /r1 RM V/V MMX Converts 4 packed signed word integers from\r\nPACKSSWB mm1, mm2/m64 mm1 and from mm2/m64 into 8 packed\r\n signed byte integers in mm1 using signed\r\n saturation.\r\n66 0F 63 /r RM V/V SSE2 Converts 8 packed signed word integers from\r\nPACKSSWB xmm1, xmm2/m128 xmm1 and from xxm2/m128 into 16 packed\r\n signed byte integers in xxm1 using signed\r\n saturation.\r\n0F 6B /r1 RM V/V MMX Converts 2 packed signed doubleword\r\nPACKSSDW mm1, mm2/m64 integers from mm1 and from mm2/m64 into 4\r\n packed signed word integers in mm1 using\r\n signed saturation.\r\n66 0F 6B /r RM V/V SSE2 Converts 4 packed signed doubleword\r\nPACKSSDW xmm1, xmm2/m128 integers from xmm1 and from xxm2/m128\r\n into 8 packed signed word integers in xxm1\r\n using signed saturation.\r\nVEX.NDS.128.66.0F.WIG 63 /r RVM V/V AVX Converts 8 packed signed word integers from\r\nVPACKSSWB xmm1,xmm2, xmm3/m128 xmm2 and from xmm3/m128 into 16 packed\r\n signed byte integers in xmm1 using signed\r\n saturation.\r\nVEX.NDS.128.66.0F.WIG 6B /r RVM V/V AVX Converts 4 packed signed doubleword\r\nVPACKSSDW xmm1,xmm2, xmm3/m128 integers from xmm2 and from xmm3/m128\r\n into 8 packed signed word integers in xmm1\r\n using signed saturation.\r\nVEX.NDS.256.66.0F.WIG 63 /r RVM V/V AVX2 Converts 16 packed signed word integers\r\nVPACKSSWB ymm1, ymm2, ymm3/m256 from ymm2 and from ymm3/m256 into 32\r\n packed signed byte integers in ymm1 using\r\n signed saturation.\r\nVEX.NDS.256.66.0F.WIG 6B /r RVM V/V AVX2 Converts 8 packed signed doubleword\r\nVPACKSSDW ymm1, ymm2, ymm3/m256 integers from ymm2 and from ymm3/m256\r\n into 16 packed signed word integers in\r\n ymm1using signed saturation.\r\nEVEX.NDS.128.66.0F.WIG 63 /r FVM V/V AVX512VL Converts packed signed word integers from\r\nVPACKSSWB xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512BW xmm2 and from xmm3/m128 into packed\r\n signed byte integers in xmm1 using signed\r\n saturation under writemask k1.\r\nEVEX.NDS.256.66.0F.WIG 63 /r FVM V/V AVX512VL Converts packed signed word integers from\r\nVPACKSSWB ymm1 {k1}{z}, ymm2, ymm3/m256 AVX512BW ymm2 and from ymm3/m256 into packed\r\n signed byte integers in ymm1 using signed\r\n saturation under writemask k1.\r\nEVEX.NDS.512.66.0F.WIG 63 /r FVM V/V AVX512BW Converts packed signed word integers from\r\nVPACKSSWB zmm1 {k1}{z}, zmm2, zmm3/m512 zmm2 and from zmm3/m512 into packed\r\n signed byte integers in zmm1 using signed\r\n saturation under writemask k1.\r\nEVEX.NDS.128.66.0F.W0 6B /r FV V/V AVX512VL Converts packed signed doubleword integers\r\nVPACKSSDW xmm1 {k1}{z}, xmm2, AVX512BW from xmm2 and from xmm3/m128/m32bcst\r\nxmm3/m128/m32bcst into packed signed word integers in xmm1\r\n using signed saturation under writemask k1.\r\n\r\n\r\n\r\n\r\n\r\nEVEX.NDS.256.66.0F.W0 6B /r FV V/V AVX512VL Converts packed signed doubleword integers\r\nVPACKSSDW ymm1 {k1}{z}, ymm2, AVX512BW from ymm2 and from ymm3/m256/m32bcst\r\nymm3/m256/m32bcst into packed signed word integers in ymm1\r\n using signed saturation under writemask k1.\r\nEVEX.NDS.512.66.0F.W0 6B /r FV V/V AVX512BW Converts packed signed doubleword integers\r\nVPACKSSDW zmm1 {k1}{z}, zmm2, from zmm2 and from zmm3/m512/m32bcst\r\nzmm3/m512/m32bcst into packed signed word integers in zmm1\r\n using signed saturation under writemask k1.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nConverts packed signed word integers into packed signed byte integers (PACKSSWB) or converts packed signed\r\ndoubleword integers into packed signed word integers (PACKSSDW), using saturation to handle overflow condi-\r\ntions. See Figure 4-6 for an example of the packing operation.\r\n\r\n\r\n 64-Bit SRC 64-Bit DEST\r\n D C B A\r\n\r\n\r\n\r\n D' C' B' A'\r\n 64-Bit DEST\r\n\r\n Figure 4-6. Operation of the PACKSSDW Instruction Using 64-bit Operands\r\n\r\nPACKSSWB converts packed signed word integers in the first and second source operands into packed signed byte\r\nintegers using signed saturation to handle overflow conditions beyond the range of signed byte integers. If the\r\nsigned doubleword value is beyond the range of an unsigned word (i.e. greater than 7FH or less than 80H), the\r\nsaturated signed byte integer value of 7FH or 80H, respectively, is stored in the destination. PACKSSDW converts\r\npacked signed doubleword integers in the first and second source operands into packed signed word integers using\r\nsigned saturation to handle overflow conditions beyond 7FFFH and 8000H.\r\nEVEX encoded PACKSSWB: The first source operand is a ZMM/YMM/XMM register. The second source operand is a\r\nZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand is a ZMM/YMM/XMM\r\nregister, updated conditional under the writemask k1.\r\nEVEX encoded PACKSSDW: The first source operand is a ZMM/YMM/XMM register. The second source operand is a\r\nZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32-\r\nbit memory location. The destination operand is a ZMM/YMM/XMM register, updated conditional under the\r\nwritemask k1.\r\n\r\n\r\n\r\n\r\n\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register\r\nor a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the\r\ncorresponding ZMM register destination are zeroed.\r\nVEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM\r\nregister or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM\r\nregister or an 128-bit memory location. The destination is not distinct from the first source XMM register and the\r\nupper bits (MAX_VL-1:128) of the corresponding ZMM destination register destination are unmodified.\r\n\r\nOperation\r\nPACKSSWB instruction (128-bit Legacy SSE version)\r\n DEST[7:0] <- SaturateSignedWordToSignedByte (DEST[15:0]);\r\n DEST[15:8] <- SaturateSignedWordToSignedByte (DEST[31:16]);\r\n DEST[23:16] <- SaturateSignedWordToSignedByte (DEST[47:32]);\r\n DEST[31:24] <- SaturateSignedWordToSignedByte (DEST[63:48]);\r\n DEST[39:32] <- SaturateSignedWordToSignedByte (DEST[79:64]);\r\n DEST[47:40] <- SaturateSignedWordToSignedByte (DEST[95:80]);\r\n DEST[55:48] <- SaturateSignedWordToSignedByte (DEST[111:96]);\r\n DEST[63:56] <- SaturateSignedWordToSignedByte (DEST[127:112]);\r\n DEST[71:64] <- SaturateSignedWordToSignedByte (SRC[15:0]);\r\n DEST[79:72] <- SaturateSignedWordToSignedByte (SRC[31:16]);\r\n DEST[87:80] <- SaturateSignedWordToSignedByte (SRC[47:32]);\r\n DEST[95:88] <- SaturateSignedWordToSignedByte (SRC[63:48]);\r\n DEST[103:96] <- SaturateSignedWordToSignedByte (SRC[79:64]);\r\n DEST[111:104] <- SaturateSignedWordToSignedByte (SRC[95:80]);\r\n DEST[119:112] <- SaturateSignedWordToSignedByte (SRC[111:96]);\r\n DEST[127:120] <- SaturateSignedWordToSignedByte (SRC[127:112]);\r\n DEST[MAX_VL-1:128] (Unmodified)\r\n\r\nPACKSSDW instruction (128-bit Legacy SSE version)\r\n DEST[15:0] <- SaturateSignedDwordToSignedWord (DEST[31:0]);\r\n DEST[31:16] <- SaturateSignedDwordToSignedWord (DEST[63:32]);\r\n DEST[47:32] <- SaturateSignedDwordToSignedWord (DEST[95:64]);\r\n DEST[63:48] <- SaturateSignedDwordToSignedWord (DEST[127:96]);\r\n DEST[79:64] <- SaturateSignedDwordToSignedWord (SRC[31:0]);\r\n DEST[95:80] <- SaturateSignedDwordToSignedWord (SRC[63:32]);\r\n DEST[111:96] <- SaturateSignedDwordToSignedWord (SRC[95:64]);\r\n DEST[127:112] <- SaturateSignedDwordToSignedWord (SRC[127:96]);\r\n DEST[MAX_VL-1:128] (Unmodified)\r\n\r\n\r\n\r\n\r\n\r\nVPACKSSWB instruction (VEX.128 encoded version)\r\n DEST[7:0] <- SaturateSignedWordToSignedByte (SRC1[15:0]);\r\n DEST[15:8] <- SaturateSignedWordToSignedByte (SRC1[31:16]);\r\n DEST[23:16] <- SaturateSignedWordToSignedByte (SRC1[47:32]);\r\n DEST[31:24] <- SaturateSignedWordToSignedByte (SRC1[63:48]);\r\n DEST[39:32] <- SaturateSignedWordToSignedByte (SRC1[79:64]);\r\n DEST[47:40] <- SaturateSignedWordToSignedByte (SRC1[95:80]);\r\n DEST[55:48] <- SaturateSignedWordToSignedByte (SRC1[111:96]);\r\n DEST[63:56] <- SaturateSignedWordToSignedByte (SRC1[127:112]);\r\n DEST[71:64] <- SaturateSignedWordToSignedByte (SRC2[15:0]);\r\n DEST[79:72] <- SaturateSignedWordToSignedByte (SRC2[31:16]);\r\n DEST[87:80] <- SaturateSignedWordToSignedByte (SRC2[47:32]);\r\n DEST[95:88] <- SaturateSignedWordToSignedByte (SRC2[63:48]);\r\n DEST[103:96] <- SaturateSignedWordToSignedByte (SRC2[79:64]);\r\n DEST[111:104] <- SaturateSignedWordToSignedByte (SRC2[95:80]);\r\n DEST[119:112] <- SaturateSignedWordToSignedByte (SRC2[111:96]);\r\n DEST[127:120] <- SaturateSignedWordToSignedByte (SRC2[127:112]);\r\n DEST[MAX_VL-1:128] <- 0;\r\n\r\nVPACKSSDW instruction (VEX.128 encoded version)\r\n DEST[15:0] <- SaturateSignedDwordToSignedWord (SRC1[31:0]);\r\n DEST[31:16] <- SaturateSignedDwordToSignedWord (SRC1[63:32]);\r\n DEST[47:32] <- SaturateSignedDwordToSignedWord (SRC1[95:64]);\r\n DEST[63:48] <- SaturateSignedDwordToSignedWord (SRC1[127:96]);\r\n DEST[79:64] <- SaturateSignedDwordToSignedWord (SRC2[31:0]);\r\n DEST[95:80] <- SaturateSignedDwordToSignedWord (SRC2[63:32]);\r\n DEST[111:96] <- SaturateSignedDwordToSignedWord (SRC2[95:64]);\r\n DEST[127:112] <- SaturateSignedDwordToSignedWord (SRC2[127:96]);\r\n DEST[MAX_VL-1:128] <- 0;\r\n\r\nVPACKSSWB instruction (VEX.256 encoded version)\r\n DEST[7:0] <- SaturateSignedWordToSignedByte (SRC1[15:0]);\r\n DEST[15:8] <- SaturateSignedWordToSignedByte (SRC1[31:16]);\r\n DEST[23:16] <- SaturateSignedWordToSignedByte (SRC1[47:32]);\r\n DEST[31:24] <- SaturateSignedWordToSignedByte (SRC1[63:48]);\r\n DEST[39:32] <- SaturateSignedWordToSignedByte (SRC1[79:64]);\r\n DEST[47:40] <- SaturateSignedWordToSignedByte (SRC1[95:80]);\r\n DEST[55:48] <- SaturateSignedWordToSignedByte (SRC1[111:96]);\r\n DEST[63:56] <- SaturateSignedWordToSignedByte (SRC1[127:112]);\r\n DEST[71:64] <- SaturateSignedWordToSignedByte (SRC2[15:0]);\r\n DEST[79:72] <- SaturateSignedWordToSignedByte (SRC2[31:16]);\r\n DEST[87:80] <- SaturateSignedWordToSignedByte (SRC2[47:32]);\r\n DEST[95:88] <- SaturateSignedWordToSignedByte (SRC2[63:48]);\r\n DEST[103:96] <- SaturateSignedWordToSignedByte (SRC2[79:64]);\r\n DEST[111:104] <- SaturateSignedWordToSignedByte (SRC2[95:80]);\r\n DEST[119:112] <- SaturateSignedWordToSignedByte (SRC2[111:96]);\r\n DEST[127:120] <- SaturateSignedWordToSignedByte (SRC2[127:112]);\r\n DEST[135:128] <- SaturateSignedWordToSignedByte (SRC1[143:128]);\r\n DEST[143:136] <- SaturateSignedWordToSignedByte (SRC1[159:144]);\r\n DEST[151:144] <- SaturateSignedWordToSignedByte (SRC1[175:160]);\r\n DEST[159:152] <- SaturateSignedWordToSignedByte (SRC1[191:176]);\r\n DEST[167:160] <- SaturateSignedWordToSignedByte (SRC1[207:192]);\r\n DEST[175:168] <- SaturateSignedWordToSignedByte (SRC1[223:208]);\r\n DEST[183:176] <- SaturateSignedWordToSignedByte (SRC1[239:224]);\r\n\r\n\r\n\r\n DEST[191:184] <- SaturateSignedWordToSignedByte (SRC1[255:240]);\r\n DEST[199:192] <- SaturateSignedWordToSignedByte (SRC2[143:128]);\r\n DEST[207:200] <- SaturateSignedWordToSignedByte (SRC2[159:144]);\r\n DEST[215:208] <- SaturateSignedWordToSignedByte (SRC2[175:160]);\r\n DEST[223:216] <- SaturateSignedWordToSignedByte (SRC2[191:176]);\r\n DEST[231:224] <- SaturateSignedWordToSignedByte (SRC2[207:192]);\r\n DEST[239:232] <- SaturateSignedWordToSignedByte (SRC2[223:208]);\r\n DEST[247:240] <- SaturateSignedWordToSignedByte (SRC2[239:224]);\r\n DEST[255:248] <- SaturateSignedWordToSignedByte (SRC2[255:240]);\r\n DEST[MAX_VL-1:256] <- 0;\r\n\r\nVPACKSSDW instruction (VEX.256 encoded version)\r\n DEST[15:0] <- SaturateSignedDwordToSignedWord (SRC1[31:0]);\r\n DEST[31:16] <- SaturateSignedDwordToSignedWord (SRC1[63:32]);\r\n DEST[47:32] <- SaturateSignedDwordToSignedWord (SRC1[95:64]);\r\n DEST[63:48] <- SaturateSignedDwordToSignedWord (SRC1[127:96]);\r\n DEST[79:64] <- SaturateSignedDwordToSignedWord (SRC2[31:0]);\r\n DEST[95:80] <- SaturateSignedDwordToSignedWord (SRC2[63:32]);\r\n DEST[111:96] <- SaturateSignedDwordToSignedWord (SRC2[95:64]);\r\n DEST[127:112] <- SaturateSignedDwordToSignedWord (SRC2[127:96]);\r\n DEST[143:128] <- SaturateSignedDwordToSignedWord (SRC1[159:128]);\r\n DEST[159:144] <- SaturateSignedDwordToSignedWord (SRC1[191:160]);\r\n DEST[175:160] <- SaturateSignedDwordToSignedWord (SRC1[223:192]);\r\n DEST[191:176] <- SaturateSignedDwordToSignedWord (SRC1[255:224]);\r\n DEST[207:192] <- SaturateSignedDwordToSignedWord (SRC2[159:128]);\r\n DEST[223:208] <- SaturateSignedDwordToSignedWord (SRC2[191:160]);\r\n DEST[239:224] <- SaturateSignedDwordToSignedWord (SRC2[223:192]);\r\n DEST[255:240] <- SaturateSignedDwordToSignedWord (SRC2[255:224]);\r\n DEST[MAX_VL-1:256] <- 0;\r\n\r\nVPACKSSWB (EVEX encoded versions)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\nTMP_DEST[7:0] <- SaturateSignedWordToSignedByte (SRC1[15:0]);\r\nTMP_DEST[15:8] <- SaturateSignedWordToSignedByte (SRC1[31:16]);\r\nTMP_DEST[23:16] <- SaturateSignedWordToSignedByte (SRC1[47:32]);\r\nTMP_DEST[31:24] <- SaturateSignedWordToSignedByte (SRC1[63:48]);\r\nTMP_DEST[39:32] <- SaturateSignedWordToSignedByte (SRC1[79:64]);\r\nTMP_DEST[47:40] <- SaturateSignedWordToSignedByte (SRC1[95:80]);\r\nTMP_DEST[55:48] <- SaturateSignedWordToSignedByte (SRC1[111:96]);\r\nTMP_DEST[63:56] <- SaturateSignedWordToSignedByte (SRC1[127:112]);\r\nTMP_DEST[71:64] <- SaturateSignedWordToSignedByte (SRC2[15:0]);\r\nTMP_DEST[79:72] <- SaturateSignedWordToSignedByte (SRC2[31:16]);\r\nTMP_DEST[87:80] <- SaturateSignedWordToSignedByte (SRC2[47:32]);\r\nTMP_DEST[95:88] <- SaturateSignedWordToSignedByte (SRC2[63:48]);\r\nTMP_DEST[103:96] <- SaturateSignedWordToSignedByte (SRC2[79:64]);\r\nTMP_DEST[111:104] <- SaturateSignedWordToSignedByte (SRC2[95:80]);\r\nTMP_DEST[119:112] <- SaturateSignedWordToSignedByte (SRC2[111:96]);\r\nTMP_DEST[127:120] <- SaturateSignedWordToSignedByte (SRC2[127:112]);\r\nIF VL >= 256\r\n TMP_DEST[135:128]<- SaturateSignedWordToSignedByte (SRC1[143:128]);\r\n TMP_DEST[143:136] <- SaturateSignedWordToSignedByte (SRC1[159:144]);\r\n TMP_DEST[151:144] <- SaturateSignedWordToSignedByte (SRC1[175:160]);\r\n TMP_DEST[159:152] <- SaturateSignedWordToSignedByte (SRC1[191:176]);\r\n TMP_DEST[167:160] <- SaturateSignedWordToSignedByte (SRC1[207:192]);\r\n\r\n\r\n\r\n TMP_DEST[175:168] <- SaturateSignedWordToSignedByte (SRC1[223:208]);\r\n TMP_DEST[183:176] <- SaturateSignedWordToSignedByte (SRC1[239:224]);\r\n TMP_DEST[191:184] <- SaturateSignedWordToSignedByte (SRC1[255:240]);\r\n TMP_DEST[199:192] <- SaturateSignedWordToSignedByte (SRC2[143:128]);\r\n TMP_DEST[207:200] <- SaturateSignedWordToSignedByte (SRC2[159:144]);\r\n TMP_DEST[215:208] <- SaturateSignedWordToSignedByte (SRC2[175:160]);\r\n TMP_DEST[223:216] <- SaturateSignedWordToSignedByte (SRC2[191:176]);\r\n TMP_DEST[231:224] <- SaturateSignedWordToSignedByte (SRC2[207:192]);\r\n TMP_DEST[239:232] <- SaturateSignedWordToSignedByte (SRC2[223:208]);\r\n TMP_DEST[247:240] <- SaturateSignedWordToSignedByte (SRC2[239:224]);\r\n TMP_DEST[255:248] <- SaturateSignedWordToSignedByte (SRC2[255:240]);\r\nFI;\r\nIF VL >= 512\r\n TMP_DEST[263:256] <- SaturateSignedWordToSignedByte (SRC1[271:256]);\r\n TMP_DEST[271:264] <- SaturateSignedWordToSignedByte (SRC1[287:272]);\r\n TMP_DEST[279:272] <- SaturateSignedWordToSignedByte (SRC1[303:288]);\r\n TMP_DEST[287:280] <- SaturateSignedWordToSignedByte (SRC1[319:304]);\r\n TMP_DEST[295:288] <- SaturateSignedWordToSignedByte (SRC1[335:320]);\r\n TMP_DEST[303:296] <- SaturateSignedWordToSignedByte (SRC1[351:336]);\r\n TMP_DEST[311:304] <- SaturateSignedWordToSignedByte (SRC1[367:352]);\r\n TMP_DEST[319:312] <- SaturateSignedWordToSignedByte (SRC1[383:368]);\r\n\r\n TMP_DEST[327:320] <- SaturateSignedWordToSignedByte (SRC2[271:256]);\r\n TMP_DEST[335:328] <- SaturateSignedWordToSignedByte (SRC2[287:272]);\r\n TMP_DEST[343:336] <- SaturateSignedWordToSignedByte (SRC2[303:288]);\r\n TMP_DEST[351:344] <- SaturateSignedWordToSignedByte (SRC2[319:304]);\r\n TMP_DEST[359:352] <- SaturateSignedWordToSignedByte (SRC2[335:320]);\r\n TMP_DEST[367:360] <- SaturateSignedWordToSignedByte (SRC2[351:336]);\r\n TMP_DEST[375:368] <- SaturateSignedWordToSignedByte (SRC2[367:352]);\r\n TMP_DEST[383:376] <- SaturateSignedWordToSignedByte (SRC2[383:368]);\r\n\r\n TMP_DEST[391:384] <- SaturateSignedWordToSignedByte (SRC1[399:384]);\r\n TMP_DEST[399:392] <- SaturateSignedWordToSignedByte (SRC1[415:400]);\r\n TMP_DEST[407:400] <- SaturateSignedWordToSignedByte (SRC1[431:416]);\r\n TMP_DEST[415:408] <- SaturateSignedWordToSignedByte (SRC1[447:432]);\r\n TMP_DEST[423:416] <- SaturateSignedWordToSignedByte (SRC1[463:448]);\r\n TMP_DEST[431:424] <- SaturateSignedWordToSignedByte (SRC1[479:464]);\r\n TMP_DEST[439:432] <- SaturateSignedWordToSignedByte (SRC1[495:480]);\r\n TMP_DEST[447:440] <- SaturateSignedWordToSignedByte (SRC1[511:496]);\r\n\r\n TMP_DEST[455:448] <- SaturateSignedWordToSignedByte (SRC2[399:384]);\r\n TMP_DEST[463:456] <- SaturateSignedWordToSignedByte (SRC2[415:400]);\r\n TMP_DEST[471:464] <- SaturateSignedWordToSignedByte (SRC2[431:416]);\r\n TMP_DEST[479:472] <- SaturateSignedWordToSignedByte (SRC2[447:432]);\r\n TMP_DEST[487:480] <- SaturateSignedWordToSignedByte (SRC2[463:448]);\r\n TMP_DEST[495:488] <- SaturateSignedWordToSignedByte (SRC2[479:464]);\r\n TMP_DEST[503:496] <- SaturateSignedWordToSignedByte (SRC2[495:480]);\r\n TMP_DEST[511:504] <- SaturateSignedWordToSignedByte (SRC2[511:496]);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i<-j*8\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n DEST[i+7:i] <- TMP_DEST[i+7:i]\r\n\r\n\r\n\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+7:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPACKSSDW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nFOR j <- 0 TO ((KL/2) - 1)\r\n i <- j * 32\r\n\r\n IF (EVEX.b == 1) AND (SRC2 *is memory*)\r\n THEN\r\n TMP_SRC2[i+31:i] <- SRC2[31:0]\r\n ELSE\r\n TMP_SRC2[i+31:i] <- SRC2[i+31:i]\r\n FI;\r\nENDFOR;\r\n\r\nTMP_DEST[15:0] <- SaturateSignedDwordToSignedWord (SRC1[31:0]);\r\nTMP_DEST[31:16] <- SaturateSignedDwordToSignedWord (SRC1[63:32]);\r\nTMP_DEST[47:32] <- SaturateSignedDwordToSignedWord (SRC1[95:64]);\r\nTMP_DEST[63:48] <- SaturateSignedDwordToSignedWord (SRC1[127:96]);\r\nTMP_DEST[79:64] <- SaturateSignedDwordToSignedWord (TMP_SRC2[31:0]);\r\nTMP_DEST[95:80] <- SaturateSignedDwordToSignedWord (TMP_SRC2[63:32]);\r\nTMP_DEST[111:96] <- SaturateSignedDwordToSignedWord (TMP_SRC2[95:64]);\r\nTMP_DEST[127:112] <- SaturateSignedDwordToSignedWord (TMP_SRC2[127:96]);\r\nIF VL >= 256\r\n TMP_DEST[143:128] <- SaturateSignedDwordToSignedWord (SRC1[159:128]);\r\n TMP_DEST[159:144] <- SaturateSignedDwordToSignedWord (SRC1[191:160]);\r\n TMP_DEST[175:160] <- SaturateSignedDwordToSignedWord (SRC1[223:192]);\r\n TMP_DEST[191:176] <- SaturateSignedDwordToSignedWord (SRC1[255:224]);\r\n TMP_DEST[207:192] <- SaturateSignedDwordToSignedWord (TMP_SRC2[159:128]);\r\n TMP_DEST[223:208] <- SaturateSignedDwordToSignedWord (TMP_SRC2[191:160]);\r\n TMP_DEST[239:224] <- SaturateSignedDwordToSignedWord (TMP_SRC2[223:192]);\r\n TMP_DEST[255:240] <- SaturateSignedDwordToSignedWord (TMP_SRC2[255:224]);\r\nFI;\r\nIF VL >= 512\r\n TMP_DEST[271:256] <- SaturateSignedDwordToSignedWord (SRC1[287:256]);\r\n TMP_DEST[287:272] <- SaturateSignedDwordToSignedWord (SRC1[319:288]);\r\n TMP_DEST[303:288] <- SaturateSignedDwordToSignedWord (SRC1[351:320]);\r\n TMP_DEST[319:304] <- SaturateSignedDwordToSignedWord (SRC1[383:352]);\r\n TMP_DEST[335:320] <- SaturateSignedDwordToSignedWord (TMP_SRC2[287:256]);\r\n TMP_DEST[351:336] <- SaturateSignedDwordToSignedWord (TMP_SRC2[319:288]);\r\n TMP_DEST[367:352] <- SaturateSignedDwordToSignedWord (TMP_SRC2[351:320]);\r\n TMP_DEST[383:368] <- SaturateSignedDwordToSignedWord (TMP_SRC2[383:352]);\r\n\r\n TMP_DEST[399:384] <- SaturateSignedDwordToSignedWord (SRC1[415:384]);\r\n TMP_DEST[415:400] <- SaturateSignedDwordToSignedWord (SRC1[447:416]);\r\n TMP_DEST[431:416] <- SaturateSignedDwordToSignedWord (SRC1[479:448]);\r\n\r\n\r\n\r\n TMP_DEST[447:432] <- SaturateSignedDwordToSignedWord (SRC1[511:480]);\r\n TMP_DEST[463:448] <- SaturateSignedDwordToSignedWord (TMP_SRC2[415:384]);\r\n TMP_DEST[479:464] <- SaturateSignedDwordToSignedWord (TMP_SRC2[447:416]);\r\n TMP_DEST[495:480] <- SaturateSignedDwordToSignedWord (TMP_SRC2[479:448]);\r\n TMP_DEST[511:496] <- SaturateSignedDwordToSignedWord (TMP_SRC2[511:480]);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- TMP_DEST[i+15:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPACKSSDW__m512i _mm512_packs_epi32(__m512i m1, __m512i m2);\r\nVPACKSSDW__m512i _mm512_mask_packs_epi32(__m512i s, __mmask32 k, __m512i m1, __m512i m2);\r\nVPACKSSDW__m512i _mm512_maskz_packs_epi32( __mmask32 k, __m512i m1, __m512i m2);\r\nVPACKSSDW__m256i _mm256_mask_packs_epi32( __m256i s, __mmask16 k, __m256i m1, __m256i m2);\r\nVPACKSSDW__m256i _mm256_maskz_packs_epi32( __mmask16 k, __m256i m1, __m256i m2);\r\nVPACKSSDW__m128i _mm_mask_packs_epi32( __m128i s, __mmask8 k, __m128i m1, __m128i m2);\r\nVPACKSSDW__m128i _mm_maskz_packs_epi32( __mmask8 k, __m128i m1, __m128i m2);\r\nVPACKSSWB__m512i _mm512_packs_epi16(__m512i m1, __m512i m2);\r\nVPACKSSWB__m512i _mm512_mask_packs_epi16(__m512i s, __mmask32 k, __m512i m1, __m512i m2);\r\nVPACKSSWB__m512i _mm512_maskz_packs_epi16( __mmask32 k, __m512i m1, __m512i m2);\r\nVPACKSSWB__m256i _mm256_mask_packs_epi16( __m256i s, __mmask16 k, __m256i m1, __m256i m2);\r\nVPACKSSWB__m256i _mm256_maskz_packs_epi16( __mmask16 k, __m256i m1, __m256i m2);\r\nVPACKSSWB__m128i _mm_mask_packs_epi16( __m128i s, __mmask8 k, __m128i m1, __m128i m2);\r\nVPACKSSWB__m128i _mm_maskz_packs_epi16( __mmask8 k, __m128i m1, __m128i m2);\r\nPACKSSWB __m128i _mm_packs_epi16(__m128i m1, __m128i m2)\r\nPACKSSDW __m128i _mm_packs_epi32(__m128i m1, __m128i m2)\r\nVPACKSSWB __m256i _mm256_packs_epi16(__m256i m1, __m256i m2)\r\nVPACKSSDW __m256i _mm256_packs_epi32(__m256i m1, __m256i m2)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded VPACKSSDW, see Exceptions Type E4NF.\r\nEVEX-encoded VPACKSSWB, see Exceptions Type E4NF.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PACKSSWB"
},
{
"description": "PACKUSDW-Pack with Unsigned Saturation\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0F 38 2B /r RM V/V SSE4_1 Convert 4 packed signed doubleword integers from xmm1\r\n PACKUSDW xmm1, xmm2/m128 and 4 packed signed doubleword integers from\r\n xmm2/m128 into 8 packed unsigned word integers in\r\n xmm1 using unsigned saturation.\r\n VEX.NDS.128.66.0F38 2B /r RVM V/V AVX Convert 4 packed signed doubleword integers from xmm2\r\n VPACKUSDW xmm1,xmm2, and 4 packed signed doubleword integers from\r\n xmm3/m128 xmm3/m128 into 8 packed unsigned word integers in\r\n xmm1 using unsigned saturation.\r\n VEX.NDS.256.66.0F38 2B /r RVM V/V AVX2 Convert 8 packed signed doubleword integers from ymm2\r\n VPACKUSDW ymm1, ymm2, and 8 packed signed doubleword integers from\r\n ymm3/m256 ymm3/m256 into 16 packed unsigned word integers in\r\n ymm1 using unsigned saturation.\r\n EVEX.NDS.128.66.0F38.W0 2B /r FV V/V AVX512VL Convert packed signed doubleword integers from xmm2\r\n VPACKUSDW xmm1{k1}{z}, AVX512BW and packed signed doubleword integers from\r\n xmm2, xmm3/m128/m32bcst xmm3/m128/m32bcst into packed unsigned word integers\r\n in xmm1 using unsigned saturation under writemask k1.\r\n EVEX.NDS.256.66.0F38.W0 2B /r FV V/V AVX512VL Convert packed signed doubleword integers from ymm2\r\n AVX512BW and packed signed doubleword integers from\r\n ymm3/m256/m32bcst into packed unsigned word integers\r\n in ymm1 using unsigned saturation under writemask k1.\r\n EVEX.NDS.512.66.0F38.W0 2B /r FV V/V AVX512BW Convert packed signed doubleword integers from zmm2\r\n VPACKUSDW zmm1{k1}{z}, and packed signed doubleword integers from\r\n zmm2, zmm3/m512/m32bcst zmm3/m512/m32bcst into packed unsigned word integers\r\n in zmm1 using unsigned saturation under writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nConverts packed signed doubleword integers in the first and second source operands into packed unsigned word\r\nintegers using unsigned saturation to handle overflow conditions. If the signed doubleword value is beyond the\r\nrange of an unsigned word (that is, greater than FFFFH or less than 0000H), the saturated unsigned word integer\r\nvalue of FFFFH or 0000H, respectively, is stored in the destination.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand is a\r\nZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32-\r\nbit memory location. The destination operand is a ZMM register, updated conditionally under the writemask k1.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register\r\nor a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the\r\ncorresponding ZMM register destination are zeroed.\r\nVEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM\r\nregister or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM\r\nregister or an 128-bit memory location. The destination is not distinct from the first source XMM register and the\r\nupper bits (MAX_VL-1:128) of the corresponding destination register destination are unmodified.\r\n\r\n\r\n\r\n\r\nOperation\r\nPACKUSDW (Legacy SSE instruction)\r\nTMP[15:0] <- (DEST[31:0] < 0) ? 0 : DEST[15:0];\r\nDEST[15:0] <- (DEST[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;\r\nTMP[31:16] <- (DEST[63:32] < 0) ? 0 : DEST[47:32];\r\nDEST[31:16] <- (DEST[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;\r\nTMP[47:32] <- (DEST[95:64] < 0) ? 0 : DEST[79:64];\r\nDEST[47:32] <- (DEST[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;\r\nTMP[63:48] <- (DEST[127:96] < 0) ? 0 : DEST[111:96];\r\nDEST[63:48] <- (DEST[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;\r\nTMP[79:64] <- (SRC[31:0] < 0) ? 0 : SRC[15:0];\r\nDEST[79:64] <- (SRC[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;\r\nTMP[95:80] <- (SRC[63:32] < 0) ? 0 : SRC[47:32];\r\nDEST[95:80] <- (SRC[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;\r\nTMP[111:96] <- (SRC[95:64] < 0) ? 0 : SRC[79:64];\r\nDEST[111:96] <- (SRC[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;\r\nTMP[127:112] <- (SRC[127:96] < 0) ? 0 : SRC[111:96];\r\nDEST[127:112] <- (SRC[127:96] > FFFFH) ? FFFFH : TMP[127:112] ;\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nPACKUSDW (VEX.128 encoded version)\r\nTMP[15:0] <- (SRC1[31:0] < 0) ? 0 : SRC1[15:0];\r\nDEST[15:0] <- (SRC1[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;\r\nTMP[31:16] <- (SRC1[63:32] < 0) ? 0 : SRC1[47:32];\r\nDEST[31:16] <- (SRC1[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;\r\nTMP[47:32] <- (SRC1[95:64] < 0) ? 0 : SRC1[79:64];\r\nDEST[47:32] <- (SRC1[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;\r\nTMP[63:48] <- (SRC1[127:96] < 0) ? 0 : SRC1[111:96];\r\nDEST[63:48] <- (SRC1[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;\r\nTMP[79:64] <- (SRC2[31:0] < 0) ? 0 : SRC2[15:0];\r\nDEST[79:64] <- (SRC2[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;\r\nTMP[95:80] <- (SRC2[63:32] < 0) ? 0 : SRC2[47:32];\r\nDEST[95:80] <- (SRC2[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;\r\nTMP[111:96] <- (SRC2[95:64] < 0) ? 0 : SRC2[79:64];\r\nDEST[111:96] <- (SRC2[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;\r\nTMP[127:112] <- (SRC2[127:96] < 0) ? 0 : SRC2[111:96];\r\nDEST[127:112] <- (SRC2[127:96] > FFFFH) ? FFFFH : TMP[127:112];\r\nDEST[MAX_VL-1:128] <- 0;\r\n\r\nVPACKUSDW (VEX.256 encoded version)\r\nTMP[15:0] <- (SRC1[31:0] < 0) ? 0 : SRC1[15:0];\r\nDEST[15:0] <- (SRC1[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;\r\nTMP[31:16] <- (SRC1[63:32] < 0) ? 0 : SRC1[47:32];\r\nDEST[31:16] <- (SRC1[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;\r\nTMP[47:32] <- (SRC1[95:64] < 0) ? 0 : SRC1[79:64];\r\nDEST[47:32] <- (SRC1[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;\r\nTMP[63:48] <- (SRC1[127:96] < 0) ? 0 : SRC1[111:96];\r\nDEST[63:48] <- (SRC1[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;\r\nTMP[79:64] <- (SRC2[31:0] < 0) ? 0 : SRC2[15:0];\r\nDEST[79:64] <- (SRC2[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;\r\nTMP[95:80] <- (SRC2[63:32] < 0) ? 0 : SRC2[47:32];\r\nDEST[95:80] <- (SRC2[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;\r\nTMP[111:96] <- (SRC2[95:64] < 0) ? 0 : SRC2[79:64];\r\nDEST[111:96] <- (SRC2[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;\r\n\r\n\r\n\r\nTMP[127:112] <- (SRC2[127:96] < 0) ? 0 : SRC2[111:96];\r\nDEST[127:112] <- (SRC2[127:96] > FFFFH) ? FFFFH : TMP[127:112] ;\r\nTMP[143:128] <- (SRC1[159:128] < 0) ? 0 : SRC1[143:128];\r\nDEST[143:128] <- (SRC1[159:128] > FFFFH) ? FFFFH : TMP[143:128] ;\r\nTMP[159:144] <- (SRC1[191:160] < 0) ? 0 : SRC1[175:160];\r\nDEST[159:144] <- (SRC1[191:160] > FFFFH) ? FFFFH : TMP[159:144] ;\r\nTMP[175:160] <- (SRC1[223:192] < 0) ? 0 : SRC1[207:192];\r\nDEST[175:160] <- (SRC1[223:192] > FFFFH) ? FFFFH : TMP[175:160] ;\r\nTMP[191:176] <- (SRC1[255:224] < 0) ? 0 : SRC1[239:224];\r\nDEST[191:176] <- (SRC1[255:224] > FFFFH) ? FFFFH : TMP[191:176] ;\r\nTMP[207:192] <- (SRC2[159:128] < 0) ? 0 : SRC2[143:128];\r\nDEST[207:192] <- (SRC2[159:128] > FFFFH) ? FFFFH : TMP[207:192] ;\r\nTMP[223:208] <- (SRC2[191:160] < 0) ? 0 : SRC2[175:160];\r\nDEST[223:208] <- (SRC2[191:160] > FFFFH) ? FFFFH : TMP[223:208] ;\r\nTMP[239:224] <- (SRC2[223:192] < 0) ? 0 : SRC2[207:192];\r\nDEST[239:224] <- (SRC2[223:192] > FFFFH) ? FFFFH : TMP[239:224] ;\r\nTMP[255:240] <- (SRC2[255:224] < 0) ? 0 : SRC2[239:224];\r\nDEST[255:240] <- (SRC2[255:224] > FFFFH) ? FFFFH : TMP[255:240] ;\r\nDEST[MAX_VL-1:256] <- 0;\r\n\r\nVPACKUSDW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nFOR j <- 0 TO ((KL/2) - 1)\r\n i <- j * 32\r\n\r\n IF (EVEX.b == 1) AND (SRC2 *is memory*)\r\n THEN\r\n TMP_SRC2[i+31:i] <- SRC2[31:0]\r\n ELSE\r\n TMP_SRC2[i+31:i] <- SRC2[i+31:i]\r\n FI;\r\nENDFOR;\r\n\r\nTMP[15:0] <- (SRC1[31:0] < 0) ? 0 : SRC1[15:0];\r\nDEST[15:0] <- (SRC1[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;\r\nTMP[31:16] <- (SRC1[63:32] < 0) ? 0 : SRC1[47:32];\r\nDEST[31:16] <- (SRC1[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;\r\nTMP[47:32] <- (SRC1[95:64] < 0) ? 0 : SRC1[79:64];\r\nDEST[47:32] <- (SRC1[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;\r\nTMP[63:48] <- (SRC1[127:96] < 0) ? 0 : SRC1[111:96];\r\nDEST[63:48] <- (SRC1[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;\r\nTMP[79:64] <- (TMP_SRC2[31:0] < 0) ? 0 : TMP_SRC2[15:0];\r\nDEST[79:64] <- (TMP_SRC2[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;\r\nTMP[95:80] <- (TMP_SRC2[63:32] < 0) ? 0 : TMP_SRC2[47:32];\r\nDEST[95:80] <- (TMP_SRC2[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;\r\nTMP[111:96] <- (TMP_SRC2[95:64] < 0) ? 0 : TMP_SRC2[79:64];\r\nDEST[111:96] <- (TMP_SRC2[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;\r\nTMP[127:112] <- (TMP_SRC2[127:96] < 0) ? 0 : TMP_SRC2[111:96];\r\nDEST[127:112] <- (TMP_SRC2[127:96] > FFFFH) ? FFFFH : TMP[127:112] ;\r\nIF VL >= 256\r\n TMP[143:128] <- (SRC1[159:128] < 0) ? 0 : SRC1[143:128];\r\n DEST[143:128] <- (SRC1[159:128] > FFFFH) ? FFFFH : TMP[143:128] ;\r\n TMP[159:144] <- (SRC1[191:160] < 0) ? 0 : SRC1[175:160];\r\n DEST[159:144] <- (SRC1[191:160] > FFFFH) ? FFFFH : TMP[159:144] ;\r\n\r\n\r\n\r\n TMP[175:160] <- (SRC1[223:192] < 0) ? 0 : SRC1[207:192];\r\n DEST[175:160] <- (SRC1[223:192] > FFFFH) ? FFFFH : TMP[175:160] ;\r\n TMP[191:176] <- (SRC1[255:224] < 0) ? 0 : SRC1[239:224];\r\n DEST[191:176] <- (SRC1[255:224] > FFFFH) ? FFFFH : TMP[191:176] ;\r\n TMP[207:192] <- (TMP_SRC2[159:128] < 0) ? 0 : TMP_SRC2[143:128];\r\n DEST[207:192] <- (TMP_SRC2[159:128] > FFFFH) ? FFFFH : TMP[207:192] ;\r\n TMP[223:208] <- (TMP_SRC2[191:160] < 0) ? 0 : TMP_SRC2[175:160];\r\n DEST[223:208] <- (TMP_SRC2[191:160] > FFFFH) ? FFFFH : TMP[223:208] ;\r\n TMP[239:224] <- (TMP_SRC2[223:192] < 0) ? 0 : TMP_SRC2[207:192];\r\n DEST[239:224] <- (TMP_SRC2[223:192] > FFFFH) ? FFFFH : TMP[239:224] ;\r\n TMP[255:240] <- (TMP_SRC2[255:224] < 0) ? 0 : TMP_SRC2[239:224];\r\n DEST[255:240] <- (TMP_SRC2[255:224] > FFFFH) ? FFFFH : TMP[255:240] ;\r\nFI;\r\nIF VL >= 512\r\n TMP[271:256] <- (SRC1[287:256] < 0) ? 0 : SRC1[271:256];\r\n DEST[271:256] <- (SRC1[287:256] > FFFFH) ? FFFFH : TMP[271:256] ;\r\n TMP[287:272] <- (SRC1[319:288] < 0) ? 0 : SRC1[303:288];\r\n DEST[287:272] <- (SRC1[319:288] > FFFFH) ? FFFFH : TMP[287:272] ;\r\n TMP[303:288] <- (SRC1[351:320] < 0) ? 0 : SRC1[335:320];\r\n DEST[303:288] <- (SRC1[351:320] > FFFFH) ? FFFFH : TMP[303:288] ;\r\n TMP[319:304] <- (SRC1[383:352] < 0) ? 0 : SRC1[367:352];\r\n DEST[319:304] <- (SRC1[383:352] > FFFFH) ? FFFFH : TMP[319:304] ;\r\n TMP[335:320] <- (TMP_SRC2[287:256] < 0) ? 0 : TMP_SRC2[271:256];\r\n DEST[335:304] <- (TMP_SRC2[287:256] > FFFFH) ? FFFFH : TMP[79:64] ;\r\n TMP[351:336] <- (TMP_SRC2[319:288] < 0) ? 0 : TMP_SRC2[303:288];\r\n DEST[351:336] <- (TMP_SRC2[319:288] > FFFFH) ? FFFFH : TMP[351:336] ;\r\n TMP[367:352] <- (TMP_SRC2[351:320] < 0) ? 0 : TMP_SRC2[315:320];\r\n DEST[367:352] <- (TMP_SRC2[351:320] > FFFFH) ? FFFFH : TMP[367:352] ;\r\n TMP[383:368] <- (TMP_SRC2[383:352] < 0) ? 0 : TMP_SRC2[367:352];\r\n DEST[383:368] <- (TMP_SRC2[383:352] > FFFFH) ? FFFFH : TMP[383:368] ;\r\n TMP[399:384] <- (SRC1[415:384] < 0) ? 0 : SRC1[399:384];\r\n DEST[399:384] <- (SRC1[415:384] > FFFFH) ? FFFFH : TMP[399:384] ;\r\n TMP[415:400] <- (SRC1[447:416] < 0) ? 0 : SRC1[431:416];\r\n DEST[415:400] <- (SRC1[447:416] > FFFFH) ? FFFFH : TMP[415:400] ;\r\n TMP[431:416] <- (SRC1[479:448] < 0) ? 0 : SRC1[463:448];\r\n DEST[431:416] <- (SRC1[479:448] > FFFFH) ? FFFFH : TMP[431:416] ;\r\n TMP[447:432] <- (SRC1[511:480] < 0) ? 0 : SRC1[495:480];\r\n DEST[447:432] <- (SRC1[511:480] > FFFFH) ? FFFFH : TMP[447:432] ;\r\n TMP[463:448] <- (TMP_SRC2[415:384] < 0) ? 0 : TMP_SRC2[399:384];\r\n DEST[463:448] <- (TMP_SRC2[415:384] > FFFFH) ? FFFFH : TMP[463:448] ;\r\n TMP[475:464] <- (TMP_SRC2[447:416] < 0) ? 0 : TMP_SRC2[431:416];\r\n DEST[475:464] <- (TMP_SRC2[447:416] > FFFFH) ? FFFFH : TMP[475:464] ;\r\n TMP[491:476] <- (TMP_SRC2[479:448] < 0) ? 0 : TMP_SRC2[463:448];\r\n DEST[491:476] <- (TMP_SRC2[479:448] > FFFFH) ? FFFFH : TMP[491:476] ;\r\n TMP[511:492] <- (TMP_SRC2[511:480] < 0) ? 0 : TMP_SRC2[495:480];\r\n DEST[511:492] <- (TMP_SRC2[511:480] > FFFFH) ? FFFFH : TMP[511:492] ;\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n DEST[i+15:i] <- TMP_DEST[i+15:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n\r\n\r\n\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPACKUSDW__m512i _mm512_packus_epi32(__m512i m1, __m512i m2);\r\nVPACKUSDW__m512i _mm512_mask_packus_epi32(__m512i s, __mmask32 k, __m512i m1, __m512i m2);\r\nVPACKUSDW__m512i _mm512_maskz_packus_epi32( __mmask32 k, __m512i m1, __m512i m2);\r\nVPACKUSDW__m256i _mm256_mask_packus_epi32( __m256i s, __mmask16 k, __m256i m1, __m256i m2);\r\nVPACKUSDW__m256i _mm256_maskz_packus_epi32( __mmask16 k, __m256i m1, __m256i m2);\r\nVPACKUSDW__m128i _mm_mask_packus_epi32( __m128i s, __mmask8 k, __m128i m1, __m128i m2);\r\nVPACKUSDW__m128i _mm_maskz_packus_epi32( __mmask8 k, __m128i m1, __m128i m2);\r\nPACKUSDW__m128i _mm_packus_epi32(__m128i m1, __m128i m2);\r\nVPACKUSDW__m256i _mm256_packus_epi32(__m256i m1, __m256i m2);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4NF.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PACKUSDW"
},
{
"description": "PACKUSWB-Pack with Unsigned Saturation\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature Flag\r\n Support\r\n0F 67 /r1 RM V/V MMX Converts 4 signed word integers from mm and\r\nPACKUSWB mm, mm/m64 4 signed word integers from mm/m64 into 8\r\n unsigned byte integers in mm using unsigned\r\n saturation.\r\n66 0F 67 /r RM V/V SSE2 Converts 8 signed word integers from xmm1\r\nPACKUSWB xmm1, xmm2/m128 and 8 signed word integers from xmm2/m128\r\n into 16 unsigned byte integers in xmm1 using\r\n unsigned saturation.\r\nVEX.NDS.128.66.0F.WIG 67 /r RVM V/V AVX Converts 8 signed word integers from xmm2\r\nVPACKUSWB xmm1, xmm2, xmm3/m128 and 8 signed word integers from xmm3/m128\r\n into 16 unsigned byte integers in xmm1 using\r\n unsigned saturation.\r\nVEX.NDS.256.66.0F.WIG 67 /r RVM V/V AVX2 Converts 16 signed word integers from ymm2\r\nVPACKUSWB ymm1, ymm2, ymm3/m256 and 16signed word integers from\r\n ymm3/m256 into 32 unsigned byte integers\r\n in ymm1 using unsigned saturation.\r\nEVEX.NDS.128.66.0F.WIG 67 /r FVM V/V AVX512VL Converts signed word integers from xmm2\r\nVPACKUSWB xmm1{k1}{z}, xmm2, xmm3/m128 AVX512BW and signed word integers from xmm3/m128\r\n into unsigned byte integers in xmm1 using\r\n unsigned saturation under writemask k1.\r\nEVEX.NDS.256.66.0F.WIG 67 /r FVM V/V AVX512VL Converts signed word integers from ymm2\r\nVPACKUSWB ymm1{k1}{z}, ymm2, ymm3/m256 AVX512BW and signed word integers from ymm3/m256\r\n into unsigned byte integers in ymm1 using\r\n unsigned saturation under writemask k1.\r\nEVEX.NDS.512.66.0F.WIG 67 /r FVM V/V AVX512BW Converts signed word integers from zmm2\r\nVPACKUSWB zmm1{k1}{z}, zmm2, zmm3/m512 and signed word integers from zmm3/m512\r\n into unsigned byte integers in zmm1 using\r\n unsigned saturation under writemask k1.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\" in\r\nthe Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nConverts 4, 8, 16 or 32 signed word integers from the destination operand (first operand) and 4, 8, 16 or 32 signed\r\nword integers from the source operand (second operand) into 8, 16, 32 or 64 unsigned byte integers and stores the\r\nresult in the destination operand. (See Figure 4-6 for an example of the packing operation.) If a signed word\r\ninteger value is beyond the range of an unsigned byte integer (that is, greater than FFH or less than 00H), the satu-\r\nrated unsigned byte integer value of FFH or 00H, respectively, is stored in the destination.\r\nEVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM\r\nregister or a 512-bit memory location. The destination operand is a ZMM register.\r\n\r\n\r\n\r\nVEX.256 and EVEX.256 encoded versions: The first source operand is a YMM register. The second source operand\r\nis a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper bits\r\n(MAX_VL-1:256) of the corresponding ZMM register destination are zeroed.\r\nVEX.128 and EVEX.128 encoded versions: The first source operand is an XMM register. The second source operand\r\nis an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits\r\n(MAX_VL-1:128) of the corresponding register destination are zeroed.\r\n128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM\r\nregister or an 128-bit memory location. The destination is not distinct from the first source XMM register and the\r\nupper bits (MAX_VL-1:128) of the corresponding register destination are unmodified.\r\n\r\nOperation\r\nPACKUSWB (with 64-bit operands)\r\n DEST[7:0] <- SaturateSignedWordToUnsignedByte DEST[15:0];\r\n DEST[15:8] <- SaturateSignedWordToUnsignedByte DEST[31:16];\r\n DEST[23:16] <- SaturateSignedWordToUnsignedByte DEST[47:32];\r\n DEST[31:24] <- SaturateSignedWordToUnsignedByte DEST[63:48];\r\n DEST[39:32] <- SaturateSignedWordToUnsignedByte SRC[15:0];\r\n DEST[47:40] <- SaturateSignedWordToUnsignedByte SRC[31:16];\r\n DEST[55:48] <- SaturateSignedWordToUnsignedByte SRC[47:32];\r\n DEST[63:56] <- SaturateSignedWordToUnsignedByte SRC[63:48];\r\n\r\nPACKUSWB (Legacy SSE instruction)\r\n DEST[7:0]<-SaturateSignedWordToUnsignedByte (DEST[15:0]);\r\n DEST[15:8] <-SaturateSignedWordToUnsignedByte (DEST[31:16]);\r\n DEST[23:16] <-SaturateSignedWordToUnsignedByte (DEST[47:32]);\r\n DEST[31:24] <- SaturateSignedWordToUnsignedByte (DEST[63:48]);\r\n DEST[39:32] <- SaturateSignedWordToUnsignedByte (DEST[79:64]);\r\n DEST[47:40] <- SaturateSignedWordToUnsignedByte (DEST[95:80]);\r\n DEST[55:48] <- SaturateSignedWordToUnsignedByte (DEST[111:96]);\r\n DEST[63:56] <- SaturateSignedWordToUnsignedByte (DEST[127:112]);\r\n DEST[71:64] <- SaturateSignedWordToUnsignedByte (SRC[15:0]);\r\n DEST[79:72] <- SaturateSignedWordToUnsignedByte (SRC[31:16]);\r\n DEST[87:80] <- SaturateSignedWordToUnsignedByte (SRC[47:32]);\r\n DEST[95:88] <- SaturateSignedWordToUnsignedByte (SRC[63:48]);\r\n DEST[103:96] <- SaturateSignedWordToUnsignedByte (SRC[79:64]);\r\n DEST[111:104] <- SaturateSignedWordToUnsignedByte (SRC[95:80]);\r\n DEST[119:112] <- SaturateSignedWordToUnsignedByte (SRC[111:96]);\r\n DEST[127:120] <- SaturateSignedWordToUnsignedByte (SRC[127:112]);\r\n\r\nPACKUSWB (VEX.128 encoded version)\r\n DEST[7:0]<- SaturateSignedWordToUnsignedByte (SRC1[15:0]);\r\n DEST[15:8] <-SaturateSignedWordToUnsignedByte (SRC1[31:16]);\r\n DEST[23:16] <-SaturateSignedWordToUnsignedByte (SRC1[47:32]);\r\n DEST[31:24] <- SaturateSignedWordToUnsignedByte (SRC1[63:48]);\r\n DEST[39:32] <- SaturateSignedWordToUnsignedByte (SRC1[79:64]);\r\n DEST[47:40] <- SaturateSignedWordToUnsignedByte (SRC1[95:80]);\r\n DEST[55:48] <- SaturateSignedWordToUnsignedByte (SRC1[111:96]);\r\n DEST[63:56] <- SaturateSignedWordToUnsignedByte (SRC1[127:112]);\r\n DEST[71:64] <- SaturateSignedWordToUnsignedByte (SRC2[15:0]);\r\n DEST[79:72] <- SaturateSignedWordToUnsignedByte (SRC2[31:16]);\r\n DEST[87:80] <- SaturateSignedWordToUnsignedByte (SRC2[47:32]);\r\n DEST[95:88] <- SaturateSignedWordToUnsignedByte (SRC2[63:48]);\r\n DEST[103:96] <- SaturateSignedWordToUnsignedByte (SRC2[79:64]);\r\n DEST[111:104] <- SaturateSignedWordToUnsignedByte (SRC2[95:80]);\r\n\r\n\r\n\r\n DEST[119:112] <- SaturateSignedWordToUnsignedByte (SRC2[111:96]);\r\n DEST[127:120] <- SaturateSignedWordToUnsignedByte (SRC2[127:112]);\r\n DEST[VLMAX-1:128] <- 0;\r\n\r\nVPACKUSWB (VEX.256 encoded version)\r\n DEST[7:0]<- SaturateSignedWordToUnsignedByte (SRC1[15:0]);\r\n DEST[15:8] <-SaturateSignedWordToUnsignedByte (SRC1[31:16]);\r\n DEST[23:16] <-SaturateSignedWordToUnsignedByte (SRC1[47:32]);\r\n DEST[31:24] <- SaturateSignedWordToUnsignedByte (SRC1[63:48]);\r\n DEST[39:32] <-SaturateSignedWordToUnsignedByte (SRC1[79:64]);\r\n DEST[47:40] <- SaturateSignedWordToUnsignedByte (SRC1[95:80]);\r\n DEST[55:48] <- SaturateSignedWordToUnsignedByte (SRC1[111:96]);\r\n DEST[63:56] <- SaturateSignedWordToUnsignedByte (SRC1[127:112]);\r\n DEST[71:64] <-SaturateSignedWordToUnsignedByte (SRC2[15:0]);\r\n DEST[79:72] <- SaturateSignedWordToUnsignedByte (SRC2[31:16]);\r\n DEST[87:80] <- SaturateSignedWordToUnsignedByte (SRC2[47:32]);\r\n DEST[95:88] <- SaturateSignedWordToUnsignedByte (SRC2[63:48]);\r\n DEST[103:96] <- SaturateSignedWordToUnsignedByte (SRC2[79:64]);\r\n DEST[111:104] <- SaturateSignedWordToUnsignedByte (SRC2[95:80]);\r\n DEST[119:112] <- SaturateSignedWordToUnsignedByte (SRC2[111:96]);\r\n DEST[127:120] <- SaturateSignedWordToUnsignedByte (SRC2[127:112]);\r\n DEST[135:128]<- SaturateSignedWordToUnsignedByte (SRC1[143:128]);\r\n DEST[143:136] <-SaturateSignedWordToUnsignedByte (SRC1[159:144]);\r\n DEST[151:144] <-SaturateSignedWordToUnsignedByte (SRC1[175:160]);\r\n DEST[159:152] <-SaturateSignedWordToUnsignedByte (SRC1[191:176]);\r\n DEST[167:160] <- SaturateSignedWordToUnsignedByte (SRC1[207:192]);\r\n DEST[175:168] <- SaturateSignedWordToUnsignedByte (SRC1[223:208]);\r\n DEST[183:176] <- SaturateSignedWordToUnsignedByte (SRC1[239:224]);\r\n DEST[191:184] <- SaturateSignedWordToUnsignedByte (SRC1[255:240]);\r\n DEST[199:192] <- SaturateSignedWordToUnsignedByte (SRC2[143:128]);\r\n DEST[207:200] <- SaturateSignedWordToUnsignedByte (SRC2[159:144]);\r\n DEST[215:208] <- SaturateSignedWordToUnsignedByte (SRC2[175:160]);\r\n DEST[223:216] <- SaturateSignedWordToUnsignedByte (SRC2[191:176]);\r\n DEST[231:224] <- SaturateSignedWordToUnsignedByte (SRC2[207:192]);\r\n DEST[239:232] <- SaturateSignedWordToUnsignedByte (SRC2[223:208]);\r\n DEST[247:240] <- SaturateSignedWordToUnsignedByte (SRC2[239:224]);\r\n DEST[255:248] <- SaturateSignedWordToUnsignedByte (SRC2[255:240]);\r\n\r\nVPACKUSWB (EVEX encoded versions)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\nTMP_DEST[7:0] <- SaturateSignedWordToUnsignedByte (SRC1[15:0]);\r\nTMP_DEST[15:8] <- SaturateSignedWordToUnsignedByte (SRC1[31:16]);\r\nTMP_DEST[23:16] <- SaturateSignedWordToUnsignedByte (SRC1[47:32]);\r\nTMP_DEST[31:24] <- SaturateSignedWordToUnsignedByte (SRC1[63:48]);\r\nTMP_DEST[39:32] <- SaturateSignedWordToUnsignedByte (SRC1[79:64]);\r\nTMP_DEST[47:40] <- SaturateSignedWordToUnsignedByte (SRC1[95:80]);\r\nTMP_DEST[55:48] <- SaturateSignedWordToUnsignedByte (SRC1[111:96]);\r\nTMP_DEST[63:56] <- SaturateSignedWordToUnsignedByte (SRC1[127:112]);\r\nTMP_DEST[71:64] <- SaturateSignedWordToUnsignedByte (SRC2[15:0]);\r\nTMP_DEST[79:72] <- SaturateSignedWordToUnsignedByte (SRC2[31:16]);\r\nTMP_DEST[87:80] <- SaturateSignedWordToUnsignedByte (SRC2[47:32]);\r\nTMP_DEST[95:88] <- SaturateSignedWordToUnsignedByte (SRC2[63:48]);\r\nTMP_DEST[103:96] <- SaturateSignedWordToUnsignedByte (SRC2[79:64]);\r\nTMP_DEST[111:104] <- SaturateSignedWordToUnsignedByte (SRC2[95:80]);\r\n\r\n\r\n\r\nTMP_DEST[119:112] <- SaturateSignedWordToUnsignedByte (SRC2[111:96]);\r\nTMP_DEST[127:120] <- SaturateSignedWordToUnsignedByte (SRC2[127:112]);\r\nIF VL >= 256\r\n TMP_DEST[135:128]<- SaturateSignedWordToUnsignedByte (SRC1[143:128]);\r\n TMP_DEST[143:136] <- SaturateSignedWordToUnsignedByte (SRC1[159:144]);\r\n TMP_DEST[151:144] <- SaturateSignedWordToUnsignedByte (SRC1[175:160]);\r\n TMP_DEST[159:152] <- SaturateSignedWordToUnsignedByte (SRC1[191:176]);\r\n TMP_DEST[167:160] <- SaturateSignedWordToUnsignedByte (SRC1[207:192]);\r\n TMP_DEST[175:168] <- SaturateSignedWordToUnsignedByte (SRC1[223:208]);\r\n TMP_DEST[183:176] <- SaturateSignedWordToUnsignedByte (SRC1[239:224]);\r\n TMP_DEST[191:184] <- SaturateSignedWordToUnsignedByte (SRC1[255:240]);\r\n TMP_DEST[199:192] <- SaturateSignedWordToUnsignedByte (SRC2[143:128]);\r\n TMP_DEST[207:200] <- SaturateSignedWordToUnsignedByte (SRC2[159:144]);\r\n TMP_DEST[215:208] <- SaturateSignedWordToUnsignedByte (SRC2[175:160]);\r\n TMP_DEST[223:216] <- SaturateSignedWordToUnsignedByte (SRC2[191:176]);\r\n TMP_DEST[231:224] <- SaturateSignedWordToUnsignedByte (SRC2[207:192]);\r\n TMP_DEST[239:232] <- SaturateSignedWordToUnsignedByte (SRC2[223:208]);\r\n TMP_DEST[247:240] <- SaturateSignedWordToUnsignedByte (SRC2[239:224]);\r\n TMP_DEST[255:248] <- SaturateSignedWordToUnsignedByte (SRC2[255:240]);\r\nFI;\r\nIF VL >= 512\r\n TMP_DEST[263:256] <- SaturateSignedWordToUnsignedByte (SRC1[271:256]);\r\n TMP_DEST[271:264] <- SaturateSignedWordToUnsignedByte (SRC1[287:272]);\r\n TMP_DEST[279:272] <- SaturateSignedWordToUnsignedByte (SRC1[303:288]);\r\n TMP_DEST[287:280] <- SaturateSignedWordToUnsignedByte (SRC1[319:304]);\r\n TMP_DEST[295:288] <- SaturateSignedWordToUnsignedByte (SRC1[335:320]);\r\n TMP_DEST[303:296] <- SaturateSignedWordToUnsignedByte (SRC1[351:336]);\r\n TMP_DEST[311:304] <- SaturateSignedWordToUnsignedByte (SRC1[367:352]);\r\n TMP_DEST[319:312] <- SaturateSignedWordToUnsignedByte (SRC1[383:368]);\r\n\r\n TMP_DEST[327:320] <- SaturateSignedWordToUnsignedByte (SRC2[271:256]);\r\n TMP_DEST[335:328] <- SaturateSignedWordToUnsignedByte (SRC2[287:272]);\r\n TMP_DEST[343:336] <- SaturateSignedWordToUnsignedByte (SRC2[303:288]);\r\n TMP_DEST[351:344] <- SaturateSignedWordToUnsignedByte (SRC2[319:304]);\r\n TMP_DEST[359:352] <- SaturateSignedWordToUnsignedByte (SRC2[335:320]);\r\n TMP_DEST[367:360] <- SaturateSignedWordToUnsignedByte (SRC2[351:336]);\r\n TMP_DEST[375:368] <- SaturateSignedWordToUnsignedByte (SRC2[367:352]);\r\n TMP_DEST[383:376] <- SaturateSignedWordToUnsignedByte (SRC2[383:368]);\r\n\r\n TMP_DEST[391:384] <- SaturateSignedWordToUnsignedByte (SRC1[399:384]);\r\n TMP_DEST[399:392] <- SaturateSignedWordToUnsignedByte (SRC1[415:400]);\r\n TMP_DEST[407:400] <- SaturateSignedWordToUnsignedByte (SRC1[431:416]);\r\n TMP_DEST[415:408] <- SaturateSignedWordToUnsignedByte (SRC1[447:432]);\r\n TMP_DEST[423:416] <- SaturateSignedWordToUnsignedByte (SRC1[463:448]);\r\n TMP_DEST[431:424] <- SaturateSignedWordToUnsignedByte (SRC1[479:464]);\r\n TMP_DEST[439:432] <- SaturateSignedWordToUnsignedByte (SRC1[495:480]);\r\n TMP_DEST[447:440] <- SaturateSignedWordToUnsignedByte (SRC1[511:496]);\r\n\r\n TMP_DEST[455:448] <- SaturateSignedWordToUnsignedByte (SRC2[399:384]);\r\n TMP_DEST[463:456] <- SaturateSignedWordToUnsignedByte (SRC2[415:400]);\r\n TMP_DEST[471:464] <- SaturateSignedWordToUnsignedByte (SRC2[431:416]);\r\n TMP_DEST[479:472] <- SaturateSignedWordToUnsignedByte (SRC2[447:432]);\r\n TMP_DEST[487:480] <- SaturateSignedWordToUnsignedByte (SRC2[463:448]);\r\n TMP_DEST[495:488] <- SaturateSignedWordToUnsignedByte (SRC2[479:464]);\r\n\r\n\r\n\r\n TMP_DEST[503:496] <- SaturateSignedWordToUnsignedByte (SRC2[495:480]);\r\n TMP_DEST[511:504] <- SaturateSignedWordToUnsignedByte (SRC2[511:496]);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i<-j*8\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n DEST[i+7:i] <- TMP_DEST[i+7:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+7:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPACKUSWB__m512i _mm512_packus_epi16(__m512i m1, __m512i m2);\r\nVPACKUSWB__m512i _mm512_mask_packus_epi16(__m512i s, __mmask64 k, __m512i m1, __m512i m2);\r\nVPACKUSWB__m512i _mm512_maskz_packus_epi16(__mmask64 k, __m512i m1, __m512i m2);\r\nVPACKUSWB__m256i _mm256_mask_packus_epi16(__m256i s, __mmask32 k, __m256i m1, __m256i m2);\r\nVPACKUSWB__m256i _mm256_maskz_packus_epi16(__mmask32 k, __m256i m1, __m256i m2);\r\nVPACKUSWB__m128i _mm_mask_packus_epi16(__m128i s, __mmask16 k, __m128i m1, __m128i m2);\r\nVPACKUSWB__m128i _mm_maskz_packus_epi16(__mmask16 k, __m128i m1, __m128i m2);\r\nPACKUSWB: __m64 _mm_packs_pu16(__m64 m1, __m64 m2)\r\n(V)PACKUSWB: __m128i _mm_packus_epi16(__m128i m1, __m128i m2)\r\nVPACKUSWB: __m256i _mm256_packus_epi16(__m256i m1, __m256i m2);\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4NF.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PACKUSWB"
},
{
"description": "PADDB/PADDW/PADDD/PADDQ-Add Packed Integers\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 0F FC /r1 RM V/V MMX Add packed byte integers from mm/m64 and mm.\r\n PADDB mm, mm/m64\r\n 0F FD /r1 RM V/V MMX Add packed word integers from mm/m64 and mm.\r\n PADDW mm, mm/m64\r\n 66 0F FC /r RM V/V SSE2 Add packed byte integers from xmm2/m128 and\r\n PADDB xmm1, xmm2/m128 xmm1.\r\n 66 0F FD /r RM V/V SSE2 Add packed word integers from xmm2/m128 and\r\n PADDW xmm1, xmm2/m128 xmm1.\r\n 66 0F FE /r RM V/V SSE2 Add packed doubleword integers from xmm2/m128\r\n PADDD xmm1, xmm2/m128 and xmm1.\r\n 66 0F D4 /r RM V/V SSE2 Add packed quadword integers from xmm2/m128\r\n PADDQ xmm1, xmm2/m128 and xmm1.\r\n VEX.NDS.128.66.0F.WIG FC /r RVM V/V AVX Add packed byte integers from xmm2, and\r\n VPADDB xmm1, xmm2, xmm3/m128 xmm3/m128 and store in xmm1.\r\n VEX.NDS.128.66.0F.WIG FD /r RVM V/V AVX Add packed word integers from xmm2, xmm3/m128\r\n VPADDW xmm1, xmm2, xmm3/m128 and store in xmm1.\r\n VEX.NDS.128.66.0F.WIG FE /r RVM V/V AVX Add packed doubleword integers from xmm2,\r\n VPADDD xmm1, xmm2, xmm3/m128 xmm3/m128 and store in xmm1.\r\n VEX.NDS.128.66.0F.WIG D4 /r RVM V/V AVX Add packed quadword integers from xmm2,\r\n VPADDQ xmm1, xmm2, xmm3/m128 xmm3/m128 and store in xmm1.\r\n VEX.NDS.256.66.0F.WIG FC /r RVM V/V AVX2 Add packed byte integers from ymm2, and\r\n VPADDB ymm1, ymm2, ymm3/m256 ymm3/m256 and store in ymm1.\r\n VEX.NDS.256.66.0F.WIG FD /r RVM V/V AVX2 Add packed word integers from ymm2, ymm3/m256\r\n VPADDW ymm1, ymm2, ymm3/m256 and store in ymm1.\r\n VEX.NDS.256.66.0F.WIG FE /r RVM V/V AVX2 Add packed doubleword integers from ymm2,\r\n VPADDD ymm1, ymm2, ymm3/m256 ymm3/m256 and store in ymm1.\r\n VEX.NDS.256.66.0F.WIG D4 /r RVM V/V AVX2 Add packed quadword integers from ymm2,\r\n VPADDQ ymm1, ymm2, ymm3/m256 ymm3/m256 and store in ymm1.\r\n EVEX.NDS.128.66.0F.WIG FC /r FVM V/V AVX512VL Add packed byte integers from xmm2, and\r\n VPADDB xmm1 {k1}{z}, xmm2, AVX512BW xmm3/m128 and store in xmm1 using writemask k1.\r\n xmm3/m128\r\n EVEX.NDS.128.66.0F.WIG FD /r FVM V/V AVX512VL Add packed word integers from xmm2, and\r\n VPADDW xmm1 {k1}{z}, xmm2, AVX512BW xmm3/m128 and store in xmm1 using writemask k1.\r\n xmm3/m128\r\n EVEX.NDS.128.66.0F.W0 FE /r FV V/V AVX512VL Add packed doubleword integers from xmm2, and\r\n VPADDD xmm1 {k1}{z}, xmm2, AVX512F xmm3/m128/m32bcst and store in xmm1 using\r\n xmm3/m128/m32bcst writemask k1.\r\n EVEX.NDS.128.66.0F.W1 D4 /r FV V/V AVX512VL Add packed quadword integers from xmm2, and\r\n VPADDQ xmm1 {k1}{z}, xmm2, AVX512F xmm3/m128/m64bcst and store in xmm1 using\r\n xmm3/m128/m64bcst writemask k1.\r\n EVEX.NDS.256.66.0F.WIG FC /r FVM V/V AVX512VL Add packed byte integers from ymm2, and\r\n VPADDB ymm1 {k1}{z}, ymm2, AVX512BW ymm3/m256 and store in ymm1 using writemask k1.\r\n ymm3/m256\r\n EVEX.NDS.256.66.0F.WIG FD /r FVM V/V AVX512VL Add packed word integers from ymm2, and\r\n VPADDW ymm1 {k1}{z}, ymm2, AVX512BW ymm3/m256 and store in ymm1 using writemask k1.\r\n ymm3/m256\r\n EVEX.NDS.256.66.0F.W0 FE /r FV V/V AVX512VL Add packed doubleword integers from ymm2,\r\n VPADDD ymm1 {k1}{z}, ymm2, AVX512F ymm3/m256/m32bcst and store in ymm1 using\r\n ymm3/m256/m32bcst writemask k1.\r\n\r\n\r\n\r\n\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.256.66.0F.W1 D4 /r FV V/V AVX512VL Add packed quadword integers from ymm2,\r\n VPADDQ ymm1 {k1}{z}, ymm2, AVX512F ymm3/m256/m64bcst and store in ymm1 using\r\n ymm3/m256/m64bcst writemask k1.\r\n EVEX.NDS.512.66.0F.WIG FC /r FVM V/V AVX512BW Add packed byte integers from zmm2, and\r\n VPADDB zmm1 {k1}{z}, zmm2, zmm3/m512 and store in zmm1 using writemask k1.\r\n zmm3/m512\r\n EVEX.NDS.512.66.0F.WIG FD /r FVM V/V AVX512BW Add packed word integers from zmm2, and\r\n VPADDW zmm1 {k1}{z}, zmm2, zmm3/m512 and store in zmm1 using writemask k1.\r\n zmm3/m512\r\n EVEX.NDS.512.66.0F.W0 FE /r FV V/V AVX512F Add packed doubleword integers from zmm2,\r\n VPADDD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst and store in zmm1 using\r\n zmm3/m512/m32bcst writemask k1.\r\n EVEX.NDS.512.66.0F.W1 D4 /r FV V/V AVX512F Add packed quadword integers from zmm2,\r\n VPADDQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst and store in zmm1 using\r\n zmm3/m512/m64bcst writemask k1.\r\n NOTES:\r\n 1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\n Developer's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX\r\n Registers\" in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a SIMD add of the packed integers from the source operand (second operand) and the destination\r\noperand (first operand), and stores the packed integer results in the destination operand. See Figure 9-4 in the\r\nIntel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for an illustration of a SIMD operation.\r\nOverflow is handled with wraparound, as described in the following paragraphs.\r\nThe PADDB and VPADDB instructions add packed byte integers from the first source operand and second source\r\noperand and store the packed integer results in the destination operand. When an individual result is too large to\r\nbe represented in 8 bits (overflow), the result is wrapped around and the low 8 bits are written to the destination\r\noperand (that is, the carry is ignored).\r\nThe PADDW and VPADDW instructions add packed word integers from the first source operand and second source\r\noperand and store the packed integer results in the destination operand. When an individual result is too large to\r\nbe represented in 16 bits (overflow), the result is wrapped around and the low 16 bits are written to the destination\r\noperand (that is, the carry is ignored).\r\nThe PADDD and VPADDD instructions add packed doubleword integers from the first source operand and second\r\nsource operand and store the packed integer results in the destination operand. When an individual result is too\r\nlarge to be represented in 32 bits (overflow), the result is wrapped around and the low 32 bits are written to the\r\ndestination operand (that is, the carry is ignored).\r\nThe PADDQ and VPADDQ instructions add packed quadword integers from the first source operand and second\r\nsource operand and store the packed integer results in the destination operand. When a quadword result is too\r\nlarge to be represented in 64 bits (overflow), the result is wrapped around and the low 64 bits are written to the\r\ndestination operand (that is, the carry is ignored).\r\n\r\n\r\n\r\n\r\nNote that the (V)PADDB, (V)PADDW, (V)PADDD and (V)PADDQ instructions can operate on either unsigned or\r\nsigned (two's complement notation) packed integers; however, it does not set bits in the EFLAGS register to indi-\r\ncate overflow and/or a carry. To prevent undetected overflow conditions, software must control the ranges of\r\nvalues operated on.\r\nEVEX encoded VPADDD/Q: The first source operand is a ZMM/YMM/XMM register. The second source operand is a\r\nZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a\r\n32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register updated according to the\r\nwritemask.\r\nEVEX encoded VPADDB/W: The first source operand is a ZMM/YMM/XMM register. The second source operand is a\r\nZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand is a ZMM/YMM/XMM\r\nregister updated according to the writemask.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register\r\nor a 256-bit memory location. The destination operand is a YMM register. the upper bits (MAX_VL-1:256) of the\r\ndestination are cleared.\r\nVEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM\r\nregister or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM\r\nregister or an 128-bit memory location. The destination is not distinct from the first source XMM register and the\r\nupper bits (MAX_VL-1:128) of the corresponding ZMM register destination are unmodified.\r\n\r\nOperation\r\nPADDB (with 64-bit operands)\r\n DEST[7:0] <- DEST[7:0] + SRC[7:0];\r\n (* Repeat add operation for 2nd through 7th byte *)\r\n DEST[63:56] <- DEST[63:56] + SRC[63:56];\r\n\r\nPADDW (with 64-bit operands)\r\n DEST[15:0] <- DEST[15:0] + SRC[15:0];\r\n (* Repeat add operation for 2nd and 3th word *)\r\n DEST[63:48] <- DEST[63:48] + SRC[63:48];\r\n\r\nPADDD (with 64-bit operands)\r\n DEST[31:0] <- DEST[31:0] + SRC[31:0];\r\n DEST[63:32] <- DEST[63:32] + SRC[63:32];\r\nPADDQ (with 64-Bit operands)\r\n DEST[63:0] <- DEST[63:0] + SRC[63:0];\r\n\r\nPADDB (Legacy SSE instruction)\r\n DEST[7:0]<- DEST[7:0] + SRC[7:0];\r\n (* Repeat add operation for 2nd through 15th byte *)\r\n DEST[127:120]<- DEST[127:120] + SRC[127:120];\r\n DEST[MAX_VL-1:128] (Unmodified)\r\n\r\nPADDW (Legacy SSE instruction)\r\n DEST[15:0] <- DEST[15:0] + SRC[15:0];\r\n (* Repeat add operation for 2nd through 7th word *)\r\n DEST[127:112]<- DEST[127:112] + SRC[127:112];\r\n DEST[MAX_VL-1:128] (Unmodified)\r\n\r\nPADDD (Legacy SSE instruction)\r\n DEST[31:0]<- DEST[31:0] + SRC[31:0];\r\n (* Repeat add operation for 2nd and 3th doubleword *)\r\n DEST[127:96]<- DEST[127:96] + SRC[127:96];\r\n\r\n\r\n\r\n DEST[MAX_VL-1:128] (Unmodified)\r\n\r\nPADDQ (Legacy SSE instruction)\r\n DEST[63:0]<- DEST[63:0] + SRC[63:0];\r\n DEST[127:64]<- DEST[127:64] + SRC[127:64];\r\n DEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVPADDB (VEX.128 encoded instruction)\r\n DEST[7:0]<- SRC1[7:0] + SRC2[7:0];\r\n (* Repeat add operation for 2nd through 15th byte *)\r\n DEST[127:120]<- SRC1[127:120] + SRC2[127:120];\r\n DEST[MAX_VL-1:128] <- 0;\r\n\r\nVPADDW (VEX.128 encoded instruction)\r\n DEST[15:0] <- SRC1[15:0] + SRC2[15:0];\r\n (* Repeat add operation for 2nd through 7th word *)\r\n DEST[127:112]<- SRC1[127:112] + SRC2[127:112];\r\n DEST[MAX_VL-1:128] <- 0;\r\n\r\nVPADDD (VEX.128 encoded instruction)\r\n DEST[31:0]<- SRC1[31:0] + SRC2[31:0];\r\n (* Repeat add operation for 2nd and 3th doubleword *)\r\n DEST[127:96] <- SRC1[127:96] + SRC2[127:96];\r\n DEST[MAX_VL-1:128] <- 0;\r\n\r\nVPADDQ (VEX.128 encoded instruction)\r\n DEST[63:0]<- SRC1[63:0] + SRC2[63:0];\r\n DEST[127:64] <- SRC1[127:64] + SRC2[127:64];\r\n DEST[MAX_VL-1:128] <- 0;\r\n\r\nVPADDB (VEX.256 encoded instruction)\r\n DEST[7:0]<- SRC1[7:0] + SRC2[7:0];\r\n (* Repeat add operation for 2nd through 31th byte *)\r\n DEST[255:248]<- SRC1[255:248] + SRC2[255:248];\r\n\r\nVPADDW (VEX.256 encoded instruction)\r\n DEST[15:0] <- SRC1[15:0] + SRC2[15:0];\r\n (* Repeat add operation for 2nd through 15th word *)\r\n DEST[255:240]<- SRC1[255:240] + SRC2[255:240];\r\n\r\nVPADDD (VEX.256 encoded instruction)\r\n DEST[31:0]<- SRC1[31:0] + SRC2[31:0];\r\n (* Repeat add operation for 2nd and 7th doubleword *)\r\n DEST[255:224] <- SRC1[255:224] + SRC2[255:224];\r\n\r\nVPADDQ (VEX.256 encoded instruction)\r\n DEST[63:0]<- SRC1[63:0] + SRC2[63:0];\r\n DEST[127:64] <- SRC1[127:64] + SRC2[127:64];\r\n DEST[191:128]<- SRC1[191:128] + SRC2[191:128];\r\n DEST[255:192] <- SRC1[255:192] + SRC2[255:192];\r\n\r\nVPADDB (EVEX encoded versions)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\n\r\n\r\n\r\n\r\nFOR j <- 0 TO KL-1\r\n i<-j*8\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- SRC1[i+7:i] + SRC2[i+7:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+7:i] = 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPADDW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- SRC1[i+15:i] + SRC2[i+15:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] = 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPADDD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN DEST[i+31:i] <- SRC1[i+31:i] + SRC2[31:0]\r\n ELSE DEST[i+31:i] <- SRC1[i+31:i] + SRC2[i+31:i]\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPADDQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n\r\n\r\n\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN DEST[i+63:i] <- SRC1[i+63:i] + SRC2[63:0]\r\n ELSE DEST[i+63:i] <- SRC1[i+63:i] + SRC2[i+63:i]\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPADDB__m512i _mm512_add_epi8 ( __m512i a, __m512i b)\r\nVPADDW__m512i _mm512_add_epi16 ( __m512i a, __m512i b)\r\nVPADDB__m512i _mm512_mask_add_epi8 ( __m512i s, __mmask64 m, __m512i a, __m512i b)\r\nVPADDW__m512i _mm512_mask_add_epi16 ( __m512i s, __mmask32 m, __m512i a, __m512i b)\r\nVPADDB__m512i _mm512_maskz_add_epi8 (__mmask64 m, __m512i a, __m512i b)\r\nVPADDW__m512i _mm512_maskz_add_epi16 (__mmask32 m, __m512i a, __m512i b)\r\nVPADDB__m256i _mm256_mask_add_epi8 (__m256i s, __mmask32 m, __m256i a, __m256i b)\r\nVPADDW__m256i _mm256_mask_add_epi16 (__m256i s, __mmask16 m, __m256i a, __m256i b)\r\nVPADDB__m256i _mm256_maskz_add_epi8 (__mmask32 m, __m256i a, __m256i b)\r\nVPADDW__m256i _mm256_maskz_add_epi16 (__mmask16 m, __m256i a, __m256i b)\r\nVPADDB__m128i _mm_mask_add_epi8 (__m128i s, __mmask16 m, __m128i a, __m128i b)\r\nVPADDW__m128i _mm_mask_add_epi16 (__m128i s, __mmask8 m, __m128i a, __m128i b)\r\nVPADDB__m128i _mm_maskz_add_epi8 (__mmask16 m, __m128i a, __m128i b)\r\nVPADDW__m128i _mm_maskz_add_epi16 (__mmask8 m, __m128i a, __m128i b)\r\nVPADDD __m512i _mm512_add_epi32( __m512i a, __m512i b);\r\nVPADDD __m512i _mm512_mask_add_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);\r\nVPADDD __m512i _mm512_maskz_add_epi32( __mmask16 k, __m512i a, __m512i b);\r\nVPADDD __m256i _mm256_mask_add_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);\r\nVPADDD __m256i _mm256_maskz_add_epi32( __mmask8 k, __m256i a, __m256i b);\r\nVPADDD __m128i _mm_mask_add_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPADDD __m128i _mm_maskz_add_epi32( __mmask8 k, __m128i a, __m128i b);\r\nVPADDQ __m512i _mm512_add_epi64( __m512i a, __m512i b);\r\nVPADDQ __m512i _mm512_mask_add_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);\r\nVPADDQ __m512i _mm512_maskz_add_epi64( __mmask8 k, __m512i a, __m512i b);\r\nVPADDQ __m256i _mm256_mask_add_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);\r\nVPADDQ __m256i _mm256_maskz_add_epi64( __mmask8 k, __m256i a, __m256i b);\r\nVPADDQ __m128i _mm_mask_add_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPADDQ __m128i _mm_maskz_add_epi64( __mmask8 k, __m128i a, __m128i b);\r\nPADDB __m128i _mm_add_epi8 (__m128i a,__m128i b );\r\nPADDW __m128i _mm_add_epi16 ( __m128i a, __m128i b);\r\nPADDD __m128i _mm_add_epi32 ( __m128i a, __m128i b);\r\nPADDQ __m128i _mm_add_epi64 ( __m128i a, __m128i b);\r\nVPADDB __m256i _mm256_add_epi8 (__m256ia,__m256i b );\r\nVPADDW __m256i _mm256_add_epi16 ( __m256i a, __m256i b);\r\nVPADDD __m256i _mm256_add_epi32 ( __m256i a, __m256i b);\r\nVPADDQ __m256i _mm256_add_epi64 ( __m256i a, __m256i b);\r\n\r\n\r\n\r\nPADDB __m64 _mm_add_pi8(__m64 m1, __m64 m2)\r\nPADDW __m64 _mm_add_pi16(__m64 m1, __m64 m2)\r\nPADDD __m64 _mm_add_pi32(__m64 m1, __m64 m2)\r\nPADDQ __m64 _mm_add_pi64(__m64 m1, __m64 m2)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded VPADDD/Q, see Exceptions Type E4.\r\nEVEX-encoded VPADDB/W, see Exceptions Type E4.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PADDB"
},
{
"description": "-R:PADDB",
"mnem": "PADDD"
},
{
"description": "-R:PADDB",
"mnem": "PADDQ"
},
{
"description": "PADDSB/PADDSW-Add Packed Signed Integers with Signed Saturation\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F EC /r1 RM V/V MMX Add packed signed byte integers from\r\nPADDSB mm, mm/m64 mm/m64 and mm and saturate the results.\r\n\r\n66 0F EC /r RM V/V SSE2 Add packed signed byte integers from\r\nPADDSB xmm1, xmm2/m128 xmm2/m128 and xmm1 saturate the results.\r\n\r\n0F ED /r1 RM V/V MMX Add packed signed word integers from\r\nPADDSW mm, mm/m64 mm/m64 and mm and saturate the results.\r\n\r\n66 0F ED /r RM V/V SSE2 Add packed signed word integers from\r\nPADDSW xmm1, xmm2/m128 xmm2/m128 and xmm1 and saturate the\r\n results.\r\nVEX.NDS.128.66.0F.WIG EC /r RVM V/V AVX Add packed signed byte integers from\r\nVPADDSB xmm1, xmm2, xmm3/m128 xmm3/m128 and xmm2 saturate the results.\r\nVEX.NDS.128.66.0F.WIG ED /r RVM V/V AVX Add packed signed word integers from\r\nVPADDSW xmm1, xmm2, xmm3/m128 xmm3/m128 and xmm2 and saturate the\r\n results.\r\nVEX.NDS.256.66.0F.WIG EC /r RVM V/V AVX2 Add packed signed byte integers from ymm2,\r\nVPADDSB ymm1, ymm2, ymm3/m256 and ymm3/m256 and store the saturated\r\n results in ymm1.\r\nVEX.NDS.256.66.0F.WIG ED /r RVM V/V AVX2 Add packed signed word integers from ymm2,\r\nVPADDSW ymm1, ymm2, ymm3/m256 and ymm3/m256 and store the saturated\r\n results in ymm1.\r\nEVEX.NDS.128.66.0F.WIG EC /r FVM V/V AVX512VL Add packed signed byte integers from xmm2,\r\nVPADDSB xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512BW and xmm3/m128 and store the saturated\r\n results in xmm1 under writemask k1.\r\nEVEX.NDS.256.66.0F.WIG EC /r FVM V/V AVX512VL Add packed signed byte integers from ymm2,\r\nVPADDSB ymm1 {k1}{z}, ymm2, ymm3/m256 AVX512BW and ymm3/m256 and store the saturated\r\n results in ymm1 under writemask k1.\r\nEVEX.NDS.512.66.0F.WIG EC /r FVM V/V AVX512BW Add packed signed byte integers from zmm2,\r\nVPADDSB zmm1 {k1}{z}, zmm2, zmm3/m512 and zmm3/m512 and store the saturated\r\n results in zmm1 under writemask k1.\r\nEVEX.NDS.128.66.0F.WIG ED /r FVM V/V AVX512VL Add packed signed word integers from xmm2,\r\nVPADDSW xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512BW and xmm3/m128 and store the saturated\r\n results in xmm1 under writemask k1.\r\nEVEX.NDS.256.66.0F.WIG ED /r FVM V/V AVX512VL Add packed signed word integers from ymm2,\r\nVPADDSW ymm1 {k1}{z}, ymm2, ymm3/m256 AVX512BW and ymm3/m256 and store the saturated\r\n results in ymm1 under writemask k1.\r\nEVEX.NDS.512.66.0F.WIG ED /r FVM V/V AVX512BW Add packed signed word integers from zmm2,\r\nVPADDSW zmm1 {k1}{z}, zmm2, zmm3/m512 and zmm3/m512 and store the saturated\r\n results in zmm1 under writemask k1.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nPerforms a SIMD add of the packed signed integers from the source operand (second operand) and the destination\r\noperand (first operand), and stores the packed integer results in the destination operand. See Figure 9-4 in the\r\nIntel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for an illustration of a SIMD operation.\r\nOverflow is handled with signed saturation, as described in the following paragraphs.\r\n(V)PADDSB performs a SIMD add of the packed signed integers with saturation from the first source operand and\r\nsecond source operand and stores the packed integer results in the destination operand. When an individual byte\r\nresult is beyond the range of a signed byte integer (that is, greater than 7FH or less than 80H), the saturated value\r\nof 7FH or 80H, respectively, is written to the destination operand.\r\n(V)PADDSW performs a SIMD add of the packed signed word integers with saturation from the first source operand\r\nand second source operand and stores the packed integer results in the destination operand. When an individual\r\nword result is beyond the range of a signed word integer (that is, greater than 7FFFH or less than 8000H), the satu-\r\nrated value of 7FFFH or 8000H, respectively, is written to the destination operand.\r\nEVEX encoded versions: The first source operand is an ZMM/YMM/XMM register. The second source operand is an\r\nZMM/YMM/XMM register or a memory location. The destination operand is an ZMM/YMM/XMM register.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register\r\nor a 256-bit memory location. The destination operand is a YMM register.\r\nVEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM\r\nregister or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128) of\r\nthe corresponding register destination are zeroed.\r\n128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM\r\nregister or an 128-bit memory location. The destination is not distinct from the first source XMM register and the\r\nupper bits (MAX_VL-1:128) of the corresponding register destination are unmodified.\r\n\r\nOperation\r\nPADDSB (with 64-bit operands)\r\n DEST[7:0] <- SaturateToSignedByte(DEST[7:0] + SRC (7:0]);\r\n (* Repeat add operation for 2nd through 7th bytes *)\r\n DEST[63:56] <- SaturateToSignedByte(DEST[63:56] + SRC[63:56] );\r\n\r\nPADDSB (with 128-bit operands)\r\n DEST[7:0] <-SaturateToSignedByte (DEST[7:0] + SRC[7:0]);\r\n (* Repeat add operation for 2nd through 14th bytes *)\r\n DEST[127:120] <- SaturateToSignedByte (DEST[111:120] + SRC[127:120]);\r\n\r\nVPADDSB (VEX.128 encoded version)\r\n DEST[7:0] <- SaturateToSignedByte (SRC1[7:0] + SRC2[7:0]);\r\n (* Repeat subtract operation for 2nd through 14th bytes *)\r\n DEST[127:120] <- SaturateToSignedByte (SRC1[111:120] + SRC2[127:120]);\r\n DEST[VLMAX-1:128] <- 0\r\n\r\nVPADDSB (VEX.256 encoded version)\r\n DEST[7:0] <- SaturateToSignedByte (SRC1[7:0] + SRC2[7:0]);\r\n (* Repeat add operation for 2nd through 31st bytes *)\r\n DEST[255:248]<- SaturateToSignedByte (SRC1[255:248] + SRC2[255:248]);\r\n\r\n\r\n\r\n\r\nVPADDSB (EVEX encoded versions)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i<-j*8\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- SaturateToSignedByte (SRC1[i+7:i] + SRC2[i+7:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+7:i] = 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nPADDSW (with 64-bit operands)\r\n DEST[15:0] <- SaturateToSignedWord(DEST[15:0] + SRC[15:0] );\r\n (* Repeat add operation for 2nd and 7th words *)\r\n DEST[63:48] <- SaturateToSignedWord(DEST[63:48] + SRC[63:48] );\r\n\r\nPADDSW (with 128-bit operands)\r\n DEST[15:0] <- SaturateToSignedWord (DEST[15:0] + SRC[15:0]);\r\n (* Repeat add operation for 2nd through 7th words *)\r\n DEST[127:112] <- SaturateToSignedWord (DEST[127:112] + SRC[127:112]);\r\n\r\nVPADDSW (VEX.128 encoded version)\r\n DEST[15:0] <- SaturateToSignedWord (SRC1[15:0] + SRC2[15:0]);\r\n (* Repeat subtract operation for 2nd through 7th words *)\r\n DEST[127:112] <- SaturateToSignedWord (SRC1[127:112] + SRC2[127:112]);\r\n DEST[VLMAX-1:128] <- 0\r\n\r\nVPADDSW (VEX.256 encoded version)\r\n DEST[15:0] <- SaturateToSignedWord (SRC1[15:0] + SRC2[15:0]);\r\n (* Repeat add operation for 2nd through 15th words *)\r\n DEST[255:240] <- SaturateToSignedWord (SRC1[255:240] + SRC2[255:240])\r\n\r\nVPADDSW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- SaturateToSignedWord (SRC1[i+15:i] + SRC2[i+15:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] = 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nPADDSB: __m64 _mm_adds_pi8(__m64 m1, __m64 m2)\r\n(V)PADDSB: __m128i _mm_adds_epi8 ( __m128i a, __m128i b)\r\nVPADDSB: __m256i _mm256_adds_epi8 ( __m256i a, __m256i b)\r\nPADDSW: __m64 _mm_adds_pi16(__m64 m1, __m64 m2)\r\n(V)PADDSW: __m128i _mm_adds_epi16 ( __m128i a, __m128i b)\r\nVPADDSW: __m256i _mm256_adds_epi16 ( __m256i a, __m256i b)\r\nVPADDSB__m512i _mm512_adds_epi8 ( __m512i a, __m512i b)\r\nVPADDSW__m512i _mm512_adds_epi16 ( __m512i a, __m512i b)\r\nVPADDSB__m512i _mm512_mask_adds_epi8 ( __m512i s, __mmask64 m, __m512i a, __m512i b)\r\nVPADDSW__m512i _mm512_mask_adds_epi16 ( __m512i s, __mmask32 m, __m512i a, __m512i b)\r\nVPADDSB__m512i _mm512_maskz_adds_epi8 (__mmask64 m, __m512i a, __m512i b)\r\nVPADDSW__m512i _mm512_maskz_adds_epi16 (__mmask32 m, __m512i a, __m512i b)\r\nVPADDSB__m256i _mm256_mask_adds_epi8 (__m256i s, __mmask32 m, __m256i a, __m256i b)\r\nVPADDSW__m256i _mm256_mask_adds_epi16 (__m256i s, __mmask16 m, __m256i a, __m256i b)\r\nVPADDSB__m256i _mm256_maskz_adds_epi8 (__mmask32 m, __m256i a, __m256i b)\r\nVPADDSW__m256i _mm256_maskz_adds_epi16 (__mmask16 m, __m256i a, __m256i b)\r\nVPADDSB__m128i _mm_mask_adds_epi8 (__m128i s, __mmask16 m, __m128i a, __m128i b)\r\nVPADDSW__m128i _mm_mask_adds_epi16 (__m128i s, __mmask8 m, __m128i a, __m128i b)\r\nVPADDSB__m128i _mm_maskz_adds_epi8 (__mmask16 m, __m128i a, __m128i b)\r\nVPADDSW__m128i _mm_maskz_adds_epi16 (__mmask8 m, __m128i a, __m128i b)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PADDSB"
},
{
"description": "-R:PADDSB",
"mnem": "PADDSW"
},
{
"description": "PADDUSB/PADDUSW-Add Packed Unsigned Integers with Unsigned Saturation\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature Flag\r\n Support\r\n0F DC /r1 RM V/V MMX Add packed unsigned byte integers from\r\nPADDUSB mm, mm/m64 mm/m64 and mm and saturate the results.\r\n\r\n66 0F DC /r RM V/V SSE2 Add packed unsigned byte integers from\r\nPADDUSB xmm1, xmm2/m128 xmm2/m128 and xmm1 saturate the results.\r\n\r\n0F DD /r1 RM V/V MMX Add packed unsigned word integers from\r\nPADDUSW mm, mm/m64 mm/m64 and mm and saturate the results.\r\n\r\n66 0F DD /r RM V/V SSE2 Add packed unsigned word integers from\r\nPADDUSW xmm1, xmm2/m128 xmm2/m128 to xmm1 and saturate the\r\n results.\r\nVEX.NDS.128.660F.WIG DC /r RVM V/V AVX Add packed unsigned byte integers from\r\nVPADDUSB xmm1, xmm2, xmm3/m128 xmm3/m128 to xmm2 and saturate the\r\n results.\r\nVEX.NDS.128.66.0F.WIG DD /r RVM V/V AVX Add packed unsigned word integers from\r\nVPADDUSW xmm1, xmm2, xmm3/m128 xmm3/m128 to xmm2 and saturate the\r\n results.\r\nVEX.NDS.256.66.0F.WIG DC /r RVM V/V AVX2 Add packed unsigned byte integers from\r\nVPADDUSB ymm1, ymm2, ymm3/m256 ymm2, and ymm3/m256 and store the\r\n saturated results in ymm1.\r\nVEX.NDS.256.66.0F.WIG DD /r RVM V/V AVX2 Add packed unsigned word integers from\r\nVPADDUSW ymm1, ymm2, ymm3/m256 ymm2, and ymm3/m256 and store the\r\n saturated results in ymm1.\r\nEVEX.NDS.128.66.0F.WIG DC /r FVM V/V AVX512VL Add packed unsigned byte integers from\r\nVPADDUSB xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512BW xmm2, and xmm3/m128 and store the\r\n saturated results in xmm1 under writemask\r\n k1.\r\nEVEX.NDS.256.66.0F.WIG DC /r FVM V/V AVX512VL Add packed unsigned byte integers from\r\nVPADDUSB ymm1 {k1}{z}, ymm2, ymm3/m256 AVX512BW ymm2, and ymm3/m256 and store the\r\n saturated results in ymm1 under writemask\r\n k1.\r\nEVEX.NDS.512.66.0F.WIG DC /r FVM V/V AVX512BW Add packed unsigned byte integers from\r\nVPADDUSB zmm1 {k1}{z}, zmm2, zmm3/m512 zmm2, and zmm3/m512 and store the\r\n saturated results in zmm1 under writemask\r\n k1.\r\nEVEX.NDS.128.66.0F.WIG DD /r FVM V/V AVX512VL Add packed unsigned word integers from\r\nVPADDUSW xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512BW xmm2, and xmm3/m128 and store the\r\n saturated results in xmm1 under writemask\r\n k1.\r\nEVEX.NDS.256.66.0F.WIG DD /r FVM V/V AVX512VL Add packed unsigned word integers from\r\nVPADDUSW ymm1 {k1}{z}, ymm2, ymm3/m256 AVX512BW ymm2, and ymm3/m256 and store the\r\n saturated results in ymm1 under writemask\r\n k1.\r\n\r\n\r\n\r\n\r\n\r\nEVEX.NDS.512.66.0F.WIG DD /r FVM V/V AVX512BW Add packed unsigned word integers from\r\nVPADDUSW zmm1 {k1}{z}, zmm2, zmm3/m512 zmm2, and zmm3/m512 and store the\r\n saturated results in zmm1 under writemask\r\n k1.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nPerforms a SIMD add of the packed unsigned integers from the source operand (second operand) and the destina-\r\ntion operand (first operand), and stores the packed integer results in the destination operand. See Figure 9-4 in the\r\nIntel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for an illustration of a SIMD operation.\r\nOverflow is handled with unsigned saturation, as described in the following paragraphs.\r\n(V)PADDUSB performs a SIMD add of the packed unsigned integers with saturation from the first source operand\r\nand second source operand and stores the packed integer results in the destination operand. When an individual\r\nbyte result is beyond the range of an unsigned byte integer (that is, greater than FFH), the saturated value of FFH\r\nis written to the destination operand.\r\n(V)PADDUSW performs a SIMD add of the packed unsigned word integers with saturation from the first source\r\noperand and second source operand and stores the packed integer results in the destination operand. When an\r\nindividual word result is beyond the range of an unsigned word integer (that is, greater than FFFFH), the saturated\r\nvalue of FFFFH is written to the destination operand.\r\nEVEX encoded versions: The first source operand is an ZMM/YMM/XMM register. The second source operand is an\r\nZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination is an ZMM/YMM/XMM register.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register\r\nor a 256-bit memory location. The destination operand is a YMM register.\r\nVEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM\r\nregister or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding destination register destination are zeroed.\r\n128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM\r\nregister or an 128-bit memory location. The destination is not distinct from the first source XMM register and the\r\nupper bits (MAX_VL-1:128) of the corresponding register destination are unmodified.\r\n\r\nOperation\r\nPADDUSB (with 64-bit operands)\r\n DEST[7:0] <- SaturateToUnsignedByte(DEST[7:0] + SRC (7:0] );\r\n (* Repeat add operation for 2nd through 7th bytes *)\r\n DEST[63:56] <- SaturateToUnsignedByte(DEST[63:56] + SRC[63:56]\r\n\r\nPADDUSB (with 128-bit operands)\r\n DEST[7:0] <- SaturateToUnsignedByte (DEST[7:0] + SRC[7:0]);\r\n (* Repeat add operation for 2nd through 14th bytes *)\r\n DEST[127:120] <- SaturateToUnSignedByte (DEST[127:120] + SRC[127:120]);\r\n\r\n\r\n\r\n\r\n\r\nVPADDUSB (VEX.128 encoded version)\r\n DEST[7:0] <- SaturateToUnsignedByte (SRC1[7:0] + SRC2[7:0]);\r\n (* Repeat subtract operation for 2nd through 14th bytes *)\r\n DEST[127:120] <- SaturateToUnsignedByte (SRC1[111:120] + SRC2[127:120]);\r\n DEST[VLMAX-1:128] <- 0\r\n\r\nVPADDUSB (VEX.256 encoded version)\r\n DEST[7:0] <- SaturateToUnsignedByte (SRC1[7:0] + SRC2[7:0]);\r\n (* Repeat add operation for 2nd through 31st bytes *)\r\n DEST[255:248]<- SaturateToUnsignedByte (SRC1[255:248] + SRC2[255:248]);\r\n\r\nPADDUSW (with 64-bit operands)\r\n DEST[15:0] <- SaturateToUnsignedWord(DEST[15:0] + SRC[15:0] );\r\n (* Repeat add operation for 2nd and 3rd words *)\r\n DEST[63:48] <- SaturateToUnsignedWord(DEST[63:48] + SRC[63:48] );\r\n\r\nPADDUSW (with 128-bit operands)\r\n DEST[15:0] <- SaturateToUnsignedWord (DEST[15:0] + SRC[15:0]);\r\n (* Repeat add operation for 2nd through 7th words *)\r\n DEST[127:112] <- SaturateToUnSignedWord (DEST[127:112] + SRC[127:112]);\r\n\r\nVPADDUSW (VEX.128 encoded version)\r\n DEST[15:0] <- SaturateToUnsignedWord (SRC1[15:0] + SRC2[15:0]);\r\n (* Repeat subtract operation for 2nd through 7th words *)\r\n DEST[127:112] <- SaturateToUnsignedWord (SRC1[127:112] + SRC2[127:112]);\r\n DEST[VLMAX-1:128] <- 0\r\n\r\nVPADDUSW (VEX.256 encoded version)\r\n DEST[15:0] <- SaturateToUnsignedWord (SRC1[15:0] + SRC2[15:0]);\r\n (* Repeat add operation for 2nd through 15th words *)\r\n DEST[255:240] <- SaturateToUnsignedWord (SRC1[255:240] + SRC2[255:240])\r\n\r\nVPADDUSB (EVEX encoded versions)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i<-j*8\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- SaturateToUnsignedByte (SRC1[i+7:i] + SRC2[i+7:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+7:i] = 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPADDUSW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n\r\n\r\n\r\n THEN DEST[i+15:i] <- SaturateToUnsignedWord (SRC1[i+15:i] + SRC2[i+15:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] = 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nPADDUSB: __m64 _mm_adds_pu8(__m64 m1, __m64 m2)\r\nPADDUSW: __m64 _mm_adds_pu16(__m64 m1, __m64 m2)\r\n(V)PADDUSB: __m128i _mm_adds_epu8 ( __m128i a, __m128i b)\r\n(V)PADDUSW: __m128i _mm_adds_epu16 ( __m128i a, __m128i b)\r\nVPADDUSB: __m256i _mm256_adds_epu8 ( __m256i a, __m256i b)\r\nVPADDUSW: __m256i _mm256_adds_epu16 ( __m256i a, __m256i b)\r\nVPADDUSB__m512i _mm512_adds_epu8 ( __m512i a, __m512i b)\r\nVPADDUSW__m512i _mm512_adds_epu16 ( __m512i a, __m512i b)\r\nVPADDUSB__m512i _mm512_mask_adds_epu8 ( __m512i s, __mmask64 m, __m512i a, __m512i b)\r\nVPADDUSW__m512i _mm512_mask_adds_epu16 ( __m512i s, __mmask32 m, __m512i a, __m512i b)\r\nVPADDUSB__m512i _mm512_maskz_adds_epu8 (__mmask64 m, __m512i a, __m512i b)\r\nVPADDUSW__m512i _mm512_maskz_adds_epu16 (__mmask32 m, __m512i a, __m512i b)\r\nVPADDUSB__m256i _mm256_mask_adds_epu8 (__m256i s, __mmask32 m, __m256i a, __m256i b)\r\nVPADDUSW__m256i _mm256_mask_adds_epu16 (__m256i s, __mmask16 m, __m256i a, __m256i b)\r\nVPADDUSB__m256i _mm256_maskz_adds_epu8 (__mmask32 m, __m256i a, __m256i b)\r\nVPADDUSW__m256i _mm256_maskz_adds_epu16 (__mmask16 m, __m256i a, __m256i b)\r\nVPADDUSB__m128i _mm_mask_adds_epu8 (__m128i s, __mmask16 m, __m128i a, __m128i b)\r\nVPADDUSW__m128i _mm_mask_adds_epu16 (__m128i s, __mmask8 m, __m128i a, __m128i b)\r\nVPADDUSB__m128i _mm_maskz_adds_epu8 (__mmask16 m, __m128i a, __m128i b)\r\nVPADDUSW__m128i _mm_maskz_adds_epu16 (__mmask8 m, __m128i a, __m128i b)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nNumeric Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PADDUSB"
},
{
"description": "-R:PADDUSB",
"mnem": "PADDUSW"
},
{
"description": "-R:PADDB",
"mnem": "PADDW"
},
{
"description": "PALIGNR - Packed Align Right\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F 3A 0F /r ib1 RMI V/V SSSE3 Concatenate destination and source operands,\r\nPALIGNR mm1, mm2/m64, imm8 extract byte-aligned result shifted to the right by\r\n constant value in imm8 into mm1.\r\n66 0F 3A 0F /r ib RMI V/V SSSE3 Concatenate destination and source operands,\r\nPALIGNR xmm1, xmm2/m128, imm8 extract byte-aligned result shifted to the right by\r\n constant value in imm8 into xmm1.\r\nVEX.NDS.128.66.0F3A.WIG 0F /r ib RVMI V/V AVX Concatenate xmm2 and xmm3/m128, extract\r\nVPALIGNR xmm1, xmm2, xmm3/m128, imm8 byte aligned result shifted to the right by\r\n constant value in imm8 and result is stored in\r\n xmm1.\r\nVEX.NDS.256.66.0F3A.WIG 0F /r ib RVMI V/V AVX2 Concatenate pairs of 16 bytes in ymm2 and\r\nVPALIGNR ymm1, ymm2, ymm3/m256, imm8 ymm3/m256 into 32-byte intermediate result,\r\n extract byte-aligned, 16-byte result shifted to\r\n the right by constant values in imm8 from each\r\n intermediate result, and two 16-byte results are\r\n stored in ymm1.\r\nEVEX.NDS.128.66.0F3A.WIG 0F /r ib FVM V/V AVX512VL Concatenate xmm2 and xmm3/m128 into a 32-\r\nVPALIGNR xmm1 {k1}{z}, xmm2, xmm3/m128, AVX512BW byte intermediate result, extract byte aligned\r\nimm8 result shifted to the right by constant value in\r\n imm8 and result is stored in xmm1.\r\nEVEX.NDS.256.66.0F3A.WIG 0F /r ib FVM V/V AVX512VL Concatenate pairs of 16 bytes in ymm2 and\r\nVPALIGNR ymm1 {k1}{z}, ymm2, ymm3/m256, AVX512BW ymm3/m256 into 32-byte intermediate result,\r\nimm8 extract byte-aligned, 16-byte result shifted to\r\n the right by constant values in imm8 from each\r\n intermediate result, and two 16-byte results are\r\n stored in ymm1.\r\nEVEX.NDS.512.66.0F3A.WIG 0F /r ib FVM V/V AVX512BW Concatenate pairs of 16 bytes in zmm2 and\r\nVPALIGNR zmm1 {k1}{z}, zmm2, zmm3/m512, zmm3/m512 into 32-byte intermediate result,\r\nimm8 extract byte-aligned, 16-byte result shifted to\r\n the right by constant values in imm8 from each\r\n intermediate result, and four 16-byte results are\r\n stored in zmm1.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (r, w) ModRM:r/m (r) imm8 NA\r\n RVMI ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\n(V)PALIGNR concatenates the destination operand (the first operand) and the source operand (the second\r\noperand) into an intermediate composite, shifts the composite at byte granularity to the right by a constant imme-\r\ndiate, and extracts the right-aligned result into the destination. The first and the second operands can be an MMX,\r\n\r\n\r\n\r\nXMM or a YMM register. The immediate value is considered unsigned. Immediate shift counts larger than the 2L\r\n(i.e. 32 for 128-bit operands, or 16 for 64-bit operands) produce a zero result. Both operands can be MMX regis-\r\nters, XMM registers or YMM registers. When the source operand is a 128-bit memory operand, the operand must\r\nbe aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.\r\nIn 64-bit mode and not encoded by VEX/EVEX prefix, use the REX prefix to access additional registers.\r\n128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain\r\nunchanged.\r\nEVEX.512 encoded version: The first source operand is a ZMM register and contains four 16-byte blocks. The\r\nsecond source operand is a ZMM register or a 512-bit memory location containing four 16-byte block. The destina-\r\ntion operand is a ZMM register and contain four 16-byte results. The imm8[7:0] is the common shift count\r\nused for each of the four successive 16-byte block sources. The low 16-byte block of the two source operands\r\nproduce the low 16-byte result of the destination operand, the high 16-byte block of the two source operands\r\nproduce the high 16-byte result of the destination operand and so on for the blocks in the middle.\r\nVEX.256 and EVEX.256 encoded versions: The first source operand is a YMM register and contains two 16-byte\r\nblocks. The second source operand is a YMM register or a 256-bit memory location containing two 16-byte block.\r\nThe destination operand is a YMM register and contain two 16-byte results. The imm8[7:0] is the common shift\r\ncount used for the two lower 16-byte block sources and the two upper 16-byte block sources. The low 16-byte\r\nblock of the two source operands produce the low 16-byte result of the destination operand, the high 16-byte block\r\nof the two source operands produce the high 16-byte result of the destination operand. The upper bits (MAX_VL-\r\n1:256) of the corresponding ZMM register destination are zeroed.\r\nVEX.128 and EVEX.128 encoded versions: The first source operand is an XMM register. The second source operand\r\nis an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits\r\n(MAX_VL-1:128) of the corresponding ZMM register destination are zeroed.\r\nConcatenation is done with 128-bit data in the first and second source operand for both 128-bit and 256-bit\r\ninstructions. The high 128-bits of the intermediate composite 256-bit result came from the 128-bit data from the\r\nfirst source operand; the low 128-bits of the intermediate result came from the 128-bit data of the second source\r\noperand.\r\nNote: VEX.L must be 0, otherwise the instruction will #UD.\r\n\r\n\r\n 127 0 127 0\r\n\r\n SRC1 SRC2\r\n\r\n\r\n Imm8[7:0]*8\r\n 255 128 255 128\r\n\r\n SRC1 SRC2\r\n\r\n\r\n Imm8[7:0]*8\r\n\r\n 255 128 127 0\r\n\r\n DEST DEST\r\n\r\n\r\n\r\n\r\n Figure 4-7. 256-bit VPALIGN Instruction Operation\r\n\r\nOperation\r\nPALIGNR (with 64-bit operands)\r\n temp1[127:0] = CONCATENATE(DEST,SRC)>>(imm8*8)\r\n DEST[63:0] = temp1[63:0]\r\n\r\n\r\n\r\n\r\n\r\nPALIGNR (with 128-bit operands)\r\ntemp1[255:0] <- ((DEST[127:0] << 128) OR SRC[127:0])>>(imm8*8);\r\nDEST[127:0] <- temp1[127:0]\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVPALIGNR (VEX.128 encoded version)\r\ntemp1[255:0] <- ((SRC1[127:0] << 128) OR SRC2[127:0])>>(imm8*8);\r\nDEST[127:0] <- temp1[127:0]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPALIGNR (VEX.256 encoded version)\r\ntemp1[255:0] <- ((SRC1[127:0] << 128) OR SRC2[127:0])>>(imm8[7:0]*8);\r\nDEST[127:0] <- temp1[127:0]\r\ntemp1[255:0] <- ((SRC1[255:128] << 128) OR SRC2[255:128])>>(imm8[7:0]*8);\r\nDEST[MAX_VL-1:128] <- temp1[127:0]\r\n\r\nVPALIGNR (EVEX encoded versions)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\n\r\nFOR l <- 0 TO VL-1 with increments of 128\r\n temp1[255:0] <- ((SRC1[l+127:l] << 128) OR SRC2[l+127:l])>>(imm8[7:0]*8);\r\n TMP_DEST[l+127:l] <- temp1[127:0]\r\nENDFOR;\r\n\r\nFOR j <- 0 TO KL-1\r\n i<-j*8\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- TMP_DEST[i+7:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+7:i] = 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nPALIGNR: __m64 _mm_alignr_pi8 (__m64 a, __m64 b, int n)\r\n(V)PALIGNR: __m128i _mm_alignr_epi8 (__m128i a, __m128i b, int n)\r\nVPALIGNR: __m256i _mm256_alignr_epi8 (__m256i a, __m256i b, const int n)\r\nVPALIGNR __m512i _mm512_alignr_epi8 (__m512i a, __m512i b, const int n)\r\nVPALIGNR __m512i _mm512_mask_alignr_epi8 (__m512i s, __mmask64 m, __m512i a, __m512i b, const int n)\r\nVPALIGNR __m512i _mm512_maskz_alignr_epi8 ( __mmask64 m, __m512i a, __m512i b, const int n)\r\nVPALIGNR __m256i _mm256_mask_alignr_epi8 (__m256i s, __mmask32 m, __m256i a, __m256i b, const int n)\r\nVPALIGNR __m256i _mm256_maskz_alignr_epi8 (__mmask32 m, __m256i a, __m256i b, const int n)\r\nVPALIGNR __m128i _mm_mask_alignr_epi8 (__m128i s, __mmask16 m, __m128i a, __m128i b, const int n)\r\nVPALIGNR __m128i _mm_maskz_alignr_epi8 (__mmask16 m, __m128i a, __m128i b, const int n)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\n\r\n\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4NF.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PALIGNR"
},
{
"description": "PAND-Logical AND\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature Flag\r\n Support\r\n0F DB /r1 RM V/V MMX Bitwise AND mm/m64 and mm.\r\nPAND mm, mm/m64\r\n66 0F DB /r RM V/V SSE2 Bitwise AND of xmm2/m128 and xmm1.\r\nPAND xmm1, xmm2/m128\r\nVEX.NDS.128.66.0F.WIG DB /r RVM V/V AVX Bitwise AND of xmm3/m128 and xmm.\r\nVPAND xmm1, xmm2, xmm3/m128\r\nVEX.NDS.256.66.0F.WIG DB /r RVM V/V AVX2 Bitwise AND of ymm2, and ymm3/m256 and\r\nVPAND ymm1, ymm2, ymm3/.m256 store result in ymm1.\r\n\r\nEVEX.NDS.128.66.0F.W0 DB /r FV V/V AVX512VL Bitwise AND of packed doubleword integers in\r\nVPANDD xmm1 {k1}{z}, xmm2, AVX512F xmm2 and xmm3/m128/m32bcst and store\r\nxmm3/m128/m32bcst result in xmm1 using writemask k1.\r\nEVEX.NDS.256.66.0F.W0 DB /r FV V/V AVX512VL Bitwise AND of packed doubleword integers in\r\nVPANDD ymm1 {k1}{z}, ymm2, AVX512F ymm2 and ymm3/m256/m32bcst and store\r\nymm3/m256/m32bcst result in ymm1 using writemask k1.\r\nEVEX.NDS.512.66.0F.W0 DB /r FV V/V AVX512F Bitwise AND of packed doubleword integers in\r\nVPANDD zmm1 {k1}{z}, zmm2, zmm2 and zmm3/m512/m32bcst and store\r\nzmm3/m512/m32bcst result in zmm1 using writemask k1.\r\nEVEX.NDS.128.66.0F.W1 DB /r FV V/V AVX512VL Bitwise AND of packed quadword integers in\r\nVPANDQ xmm1 {k1}{z}, xmm2, AVX512F xmm2 and xmm3/m128/m64bcst and store\r\nxmm3/m128/m64bcst result in xmm1 using writemask k1.\r\nEVEX.NDS.256.66.0F.W1 DB /r FV V/V AVX512VL Bitwise AND of packed quadword integers in\r\nVPANDQ ymm1 {k1}{z}, ymm2, AVX512F ymm2 and ymm3/m256/m64bcst and store\r\nymm3/m256/m64bcst result in ymm1 using writemask k1.\r\nEVEX.NDS.512.66.0F.W1 DB /r FV V/V AVX512F Bitwise AND of packed quadword integers in\r\nVPANDQ zmm1 {k1}{z}, zmm2, zmm2 and zmm3/m512/m64bcst and store\r\nzmm3/m512/m64bcst result in zmm1 using writemask k1.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nPerforms a bitwise logical AND operation on the first source operand and second source operand and stores the\r\nresult in the destination operand. Each bit of the result is set to 1 if the corresponding bits of the first and second\r\noperands are 1, otherwise it is set to 0.\r\nIn 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to\r\naccess additional registers (XMM8-XMM15).\r\n\r\n\r\n\r\n\r\n\r\nLegacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The\r\ndestination operand can be an MMX technology register.\r\n128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM\r\nregister or an 128-bit memory location. The destination is not distinct from the first source XMM register and the\r\nupper bits (MAX_VL-1:128) of the corresponding ZMM register destination are unmodified.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be\r\na ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a\r\n32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with\r\nwritemask k1 at 32/64-bit granularity.\r\nVEX.256 encoded versions: The first source operand is a YMM register. The second source operand is a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)\r\nof the corresponding ZMM register destination are zeroed.\r\nVEX.128 encoded versions: The first source operand is an XMM register. The second source operand is an XMM\r\nregister or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n\r\nOperation\r\nPAND (64-bit operand)\r\nDEST <- DEST AND SRC\r\n\r\n\r\nPAND (128-bit Legacy SSE version)\r\nDEST <- DEST AND SRC\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVPAND (VEX.128 encoded version)\r\nDEST <- SRC1 AND SRC2\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPAND (VEX.256 encoded instruction)\r\nDEST[255:0] <- (SRC1[255:0] AND SRC2[255:0])\r\nDEST[VLMAX-1:256] <- 0\r\n\r\nVPANDD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN DEST[i+31:i] <- SRC1[i+31:i] BITWISE AND SRC2[31:0]\r\n ELSE DEST[i+31:i] <- SRC1[i+31:i] BITWISE AND SRC2[i+31:i]\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPANDQ (EVEX encoded versions)\r\n\r\n\r\n\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN DEST[i+63:i] <- SRC1[i+63:i] BITWISE AND SRC2[63:0]\r\n ELSE DEST[i+63:i] <- SRC1[i+63:i] BITWISE AND SRC2[i+63:i]\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPANDD __m512i _mm512_and_epi32( __m512i a, __m512i b);\r\nVPANDD __m512i _mm512_mask_and_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);\r\nVPANDD __m512i _mm512_maskz_and_epi32( __mmask16 k, __m512i a, __m512i b);\r\nVPANDQ __m512i _mm512_and_epi64( __m512i a, __m512i b);\r\nVPANDQ __m512i _mm512_mask_and_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);\r\nVPANDQ __m512i _mm512_maskz_and_epi64( __mmask8 k, __m512i a, __m512i b);\r\nVPANDND __m256i _mm256_mask_and_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);\r\nVPANDND __m256i _mm256_maskz_and_epi32( __mmask8 k, __m256i a, __m256i b);\r\nVPANDND __m128i _mm_mask_and_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPANDND __m128i _mm_maskz_and_epi32( __mmask8 k, __m128i a, __m128i b);\r\nVPANDNQ __m256i _mm256_mask_and_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);\r\nVPANDNQ __m256i _mm256_maskz_and_epi64( __mmask8 k, __m256i a, __m256i b);\r\nVPANDNQ __m128i _mm_mask_and_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPANDNQ __m128i _mm_maskz_and_epi64( __mmask8 k, __m128i a, __m128i b);\r\nPAND: __m64 _mm_and_si64 (__m64 m1, __m64 m2)\r\n(V)PAND:__m128i _mm_and_si128 ( __m128i a, __m128i b)\r\nVPAND: __m256i _mm256_and_si256 ( __m256i a, __m256i b)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nNumeric Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PAND"
},
{
"description": "PANDN-Logical AND NOT\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F DF /r1 RM V/V MMX Bitwise AND NOT of mm/m64 and mm.\r\nPANDN mm, mm/m64\r\n66 0F DF /r RM V/V SSE2 Bitwise AND NOT of xmm2/m128 and xmm1.\r\nPANDN xmm1, xmm2/m128\r\nVEX.NDS.128.66.0F.WIG DF /r RVM V/V AVX Bitwise AND NOT of xmm3/m128 and xmm2.\r\nVPANDN xmm1, xmm2, xmm3/m128\r\nVEX.NDS.256.66.0F.WIG DF /r RVM V/V AVX2 Bitwise AND NOT of ymm2, and ymm3/m256\r\nVPANDN ymm1, ymm2, ymm3/m256 and store result in ymm1.\r\n\r\nEVEX.NDS.128.66.0F.W0 DF /r FV V/V AVX512VL Bitwise AND NOT of packed doubleword\r\nVPANDND xmm1 {k1}{z}, xmm2, AVX512F integers in xmm2 and xmm3/m128/m32bcst\r\nxmm3/m128/m32bcst and store result in xmm1 using writemask k1.\r\nEVEX.NDS.256.66.0F.W0 DF /r FV V/V AVX512VL Bitwise AND NOT of packed doubleword\r\nVPANDND ymm1 {k1}{z}, ymm2, AVX512F integers in ymm2 and ymm3/m256/m32bcst\r\nymm3/m256/m32bcst and store result in ymm1 using writemask k1.\r\nEVEX.NDS.512.66.0F.W0 DF /r FV V/V AVX512F Bitwise AND NOT of packed doubleword\r\nVPANDND zmm1 {k1}{z}, zmm2, integers in zmm2 and zmm3/m512/m32bcst\r\nzmm3/m512/m32bcst and store result in zmm1 using writemask k1.\r\nEVEX.NDS.128.66.0F.W1 DF /r FV V/V AVX512VL Bitwise AND NOT of packed quadword\r\nVPANDNQ xmm1 {k1}{z}, xmm2, AVX512F integers in xmm2 and xmm3/m128/m64bcst\r\nxmm3/m128/m64bcst and store result in xmm1 using writemask k1.\r\nEVEX.NDS.256.66.0F.W1 DF /r FV V/V AVX512VL Bitwise AND NOT of packed quadword\r\nVPANDNQ ymm1 {k1}{z}, ymm2, AVX512F integers in ymm2 and ymm3/m256/m64bcst\r\nymm3/m256/m64bcst and store result in ymm1 using writemask k1.\r\nEVEX.NDS.512.66.0F.W1 DF /r FV V/V AVX512F Bitwise AND NOT of packed quadword\r\nVPANDNQ zmm1 {k1}{z}, zmm2, integers in zmm2 and zmm3/m512/m64bcst\r\nzmm3/m512/m64bcst and store result in zmm1 using writemask k1.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nPerforms a bitwise logical NOT operation on the first source operand, then performs bitwise AND with second\r\nsource operand and stores the result in the destination operand. Each bit of the result is set to 1 if the corre-\r\nsponding bit in the first operand is 0 and the corresponding bit in the second operand is 1, otherwise it is set to 0.\r\nIn 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to\r\naccess additional registers (XMM8-XMM15).\r\n\r\n\r\n\r\n\r\n\r\nLegacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The\r\ndestination operand can be an MMX technology register.\r\n128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM\r\nregister or an 128-bit memory location. The destination is not distinct from the first source XMM register and the\r\nupper bits (MAX_VL-1:128) of the corresponding ZMM register destination are unmodified.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be\r\na ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a\r\n32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with\r\nwritemask k1 at 32/64-bit granularity.\r\nVEX.256 encoded versions: The first source operand is a YMM register. The second source operand is a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)\r\nof the corresponding ZMM register destination are zeroed.\r\nVEX.128 encoded versions: The first source operand is an XMM register. The second source operand is an XMM\r\nregister or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\n\r\nOperation\r\nPANDN (64-bit operand)\r\nDEST <- NOT(DEST) AND SRC\r\n\r\n\r\nPANDN (128-bit Legacy SSE version)\r\nDEST <- NOT(DEST) AND SRC\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVPANDN (VEX.128 encoded version)\r\nDEST <- NOT(SRC1) AND SRC2\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPANDN (VEX.256 encoded instruction)\r\nDEST[255:0] <- ((NOT SRC1[255:0]) AND SRC2[255:0])\r\nDEST[VLMAX-1:256] <- 0\r\n\r\nVPANDND (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN DEST[i+31:i] <- ((NOT SRC1[i+31:i]) AND SRC2[31:0])\r\n ELSE DEST[i+31:i] <- ((NOT SRC1[i+31:i]) AND SRC2[i+31:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPANDNQ (EVEX encoded versions)\r\n\r\n\r\n\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN DEST[i+63:i] <- ((NOT SRC1[i+63:i]) AND SRC2[63:0])\r\n ELSE DEST[i+63:i] <- ((NOT SRC1[i+63:i]) AND SRC2[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPANDND __m512i _mm512_andnot_epi32( __m512i a, __m512i b);\r\nVPANDND __m512i _mm512_mask_andnot_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);\r\nVPANDND __m512i _mm512_maskz_andnot_epi32( __mmask16 k, __m512i a, __m512i b);\r\nVPANDND __m256i _mm256_mask_andnot_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);\r\nVPANDND __m256i _mm256_maskz_andnot_epi32( __mmask8 k, __m256i a, __m256i b);\r\nVPANDND __m128i _mm_mask_andnot_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPANDND __m128i _mm_maskz_andnot_epi32( __mmask8 k, __m128i a, __m128i b);\r\nVPANDNQ __m512i _mm512_andnot_epi64( __m512i a, __m512i b);\r\nVPANDNQ __m512i _mm512_mask_andnot_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);\r\nVPANDNQ __m512i _mm512_maskz_andnot_epi64( __mmask8 k, __m512i a, __m512i b);\r\nVPANDNQ __m256i _mm256_mask_andnot_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);\r\nVPANDNQ __m256i _mm256_maskz_andnot_epi64( __mmask8 k, __m256i a, __m256i b);\r\nVPANDNQ __m128i _mm_mask_andnot_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPANDNQ __m128i _mm_maskz_andnot_epi64( __mmask8 k, __m128i a, __m128i b);\r\nPANDN: __m64 _mm_andnot_si64 (__m64 m1, __m64 m2)\r\n(V)PANDN:__m128i _mm_andnot_si128 ( __m128i a, __m128i b)\r\nVPANDN: __m256i _mm256_andnot_si256 ( __m256i a, __m256i b)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nNumeric Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PANDN"
},
{
"description": "PAUSE-Spin Loop Hint\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n F3 90 PAUSE NP Valid Valid Gives hint to processor that improves\r\n performance of spin-wait loops.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nImproves the performance of spin-wait loops. When executing a \"spin-wait loop,\" processors will suffer a severe\r\nperformance penalty when exiting the loop because it detects a possible memory order violation. The PAUSE\r\ninstruction provides a hint to the processor that the code sequence is a spin-wait loop. The processor uses this hint\r\nto avoid the memory order violation in most situations, which greatly improves processor performance. For this\r\nreason, it is recommended that a PAUSE instruction be placed in all spin-wait loops.\r\nAn additional function of the PAUSE instruction is to reduce the power consumed by a processor while executing a\r\nspin loop. A processor can execute a spin-wait loop extremely quickly, causing the processor to consume a lot of\r\npower while it waits for the resource it is spinning on to become available. Inserting a pause instruction in a spin-\r\nwait loop greatly reduces the processor's power consumption.\r\nThis instruction was introduced in the Pentium 4 processors, but is backward compatible with all IA-32 processors.\r\nIn earlier IA-32 processors, the PAUSE instruction operates like a NOP instruction. The Pentium 4 and Intel Xeon\r\nprocessors implement the PAUSE instruction as a delay. The delay is finite and can be zero for some processors.\r\nThis instruction does not change the architectural state of the processor (that is, it performs essentially a delaying\r\nno-op operation).\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nExecute_Next_Instruction(DELAY);\r\n\r\nNumeric Exceptions\r\nNone.\r\n\r\nExceptions (All Operating Modes)\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PAUSE"
},
{
"description": "PAVGB/PAVGW-Average Packed Integers\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F E0 /r1 RM V/V SSE Average packed unsigned byte integers from\r\nPAVGB mm1, mm2/m64 mm2/m64 and mm1 with rounding.\r\n\r\n66 0F E0, /r RM V/V SSE2 Average packed unsigned byte integers from\r\nPAVGB xmm1, xmm2/m128 xmm2/m128 and xmm1 with rounding.\r\n\r\n0F E3 /r1 RM V/V SSE Average packed unsigned word integers from\r\nPAVGW mm1, mm2/m64 mm2/m64 and mm1 with rounding.\r\n\r\n66 0F E3 /r RM V/V SSE2 Average packed unsigned word integers from\r\nPAVGW xmm1, xmm2/m128 xmm2/m128 and xmm1 with rounding.\r\n\r\nVEX.NDS.128.66.0F.WIG E0 /r RVM V/V AVX Average packed unsigned byte integers from\r\nVPAVGB xmm1, xmm2, xmm3/m128 xmm3/m128 and xmm2 with rounding.\r\n\r\nVEX.NDS.128.66.0F.WIG E3 /r RVM V/V AVX Average packed unsigned word integers from\r\nVPAVGW xmm1, xmm2, xmm3/m128 xmm3/m128 and xmm2 with rounding.\r\n\r\nVEX.NDS.256.66.0F.WIG E0 /r RVM V/V AVX2 Average packed unsigned byte integers from\r\nVPAVGB ymm1, ymm2, ymm3/m256 ymm2, and ymm3/m256 with rounding and\r\n store to ymm1.\r\nVEX.NDS.256.66.0F.WIG E3 /r RVM V/V AVX2 Average packed unsigned word integers from\r\nVPAVGW ymm1, ymm2, ymm3/m256 ymm2, ymm3/m256 with rounding to ymm1.\r\n\r\nEVEX.NDS.128.66.0F.WIG E0 /r FVM V/V AVX512VL Average packed unsigned byte integers from\r\nVPAVGB xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512BW xmm2, and xmm3/m128 with rounding and\r\n store to xmm1 under writemask k1.\r\nEVEX.NDS.256.66.0F.WIG E0 /r FVM V/V AVX512VL Average packed unsigned byte integers from\r\nVPAVGB ymm1 {k1}{z}, ymm2, ymm3/m256 AVX512BW ymm2, and ymm3/m256 with rounding and\r\n store to ymm1 under writemask k1.\r\nEVEX.NDS.512.66.0F.WIG E0 /r FVM V/V AVX512BW Average packed unsigned byte integers from\r\nVPAVGB zmm1 {k1}{z}, zmm2, zmm3/m512 zmm2, and zmm3/m512 with rounding and\r\n store to zmm1 under writemask k1.\r\nEVEX.NDS.128.66.0F.WIG E3 /r FVM V/V AVX512VL Average packed unsigned word integers from\r\nVPAVGW xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512BW xmm2, xmm3/m128 with rounding to xmm1\r\n under writemask k1.\r\nEVEX.NDS.256.66.0F.WIG E3 /r FVM V/V AVX512VL Average packed unsigned word integers from\r\nVPAVGW ymm1 {k1}{z}, ymm2, ymm3/m256 AVX512BW ymm2, ymm3/m256 with rounding to ymm1\r\n under writemask k1.\r\nEVEX.NDS.512.66.0F.WIG E3 /r FVM V/V AVX512BW Average packed unsigned word integers from\r\nVPAVGW zmm1 {k1}{z}, zmm2, zmm3/m512 zmm2, zmm3/m512 with rounding to zmm1\r\n under writemask k1.\r\n\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n\r\n\r\n\r\n\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a SIMD average of the packed unsigned integers from the source operand (second operand) and the\r\ndestination operand (first operand), and stores the results in the destination operand. For each corresponding pair\r\nof data elements in the first and second operands, the elements are added together, a 1 is added to the temporary\r\nsum, and that result is shifted right one bit position.\r\nThe (V)PAVGB instruction operates on packed unsigned bytes and the (V)PAVGW instruction operates on packed\r\nunsigned words.\r\nIn 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to\r\naccess additional registers (XMM8-XMM15).\r\nLegacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The\r\ndestination operand can be an MMX technology register.\r\n128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM\r\nregister or an 128-bit memory location. The destination is not distinct from the first source XMM register and the\r\nupper bits (MAX_VL-1:128) of the corresponding register destination are unmodified.\r\nEVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM\r\nregister or a 512-bit memory location. The destination operand is a ZMM register.\r\nVEX.256 and EVEX.256 encoded versions: The first source operand is a YMM register. The second source operand\r\nis a YMM register or a 256-bit memory location. The destination operand is a YMM register.\r\nVEX.128 and EVEX.128 encoded versions: The first source operand is an XMM register. The second source operand\r\nis an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits\r\n(MAX_VL-1:128) of the corresponding register destination are zeroed.\r\n\r\nOperation\r\nPAVGB (with 64-bit operands)\r\n DEST[7:0] <- (SRC[7:0] + DEST[7:0] + 1) >> 1; (* Temp sum before shifting is 9 bits *)\r\n (* Repeat operation performed for bytes 2 through 6 *)\r\n DEST[63:56] <- (SRC[63:56] + DEST[63:56] + 1) >> 1;\r\n\r\nPAVGW (with 64-bit operands)\r\n DEST[15:0] <- (SRC[15:0] + DEST[15:0] + 1) >> 1; (* Temp sum before shifting is 17 bits *)\r\n (* Repeat operation performed for words 2 and 3 *)\r\n DEST[63:48] <- (SRC[63:48] + DEST[63:48] + 1) >> 1;\r\n\r\nPAVGB (with 128-bit operands)\r\n DEST[7:0] <- (SRC[7:0] + DEST[7:0] + 1) >> 1; (* Temp sum before shifting is 9 bits *)\r\n (* Repeat operation performed for bytes 2 through 14 *)\r\n DEST[127:120] <- (SRC[127:120] + DEST[127:120] + 1) >> 1;\r\n\r\nPAVGW (with 128-bit operands)\r\n DEST[15:0] <- (SRC[15:0] + DEST[15:0] + 1) >> 1; (* Temp sum before shifting is 17 bits *)\r\n (* Repeat operation performed for words 2 through 6 *)\r\n DEST[127:112] <- (SRC[127:112] + DEST[127:112] + 1) >> 1;\r\n\r\n\r\n\r\n\r\n\r\nVPAVGB (VEX.128 encoded version)\r\n DEST[7:0] <- (SRC1[7:0] + SRC2[7:0] + 1) >> 1;\r\n (* Repeat operation performed for bytes 2 through 15 *)\r\n DEST[127:120] <- (SRC1[127:120] + SRC2[127:120] + 1) >> 1\r\n DEST[VLMAX-1:128] <- 0\r\n\r\nVPAVGW (VEX.128 encoded version)\r\n DEST[15:0] <- (SRC1[15:0] + SRC2[15:0] + 1) >> 1;\r\n (* Repeat operation performed for 16-bit words 2 through 7 *)\r\n DEST[127:112] <- (SRC1[127:112] + SRC2[127:112] + 1) >> 1\r\n DEST[VLMAX-1:128] <- 0\r\n\r\nVPAVGB (VEX.256 encoded instruction)\r\n DEST[7:0] <- (SRC1[7:0] + SRC2[7:0] + 1) >> 1; (* Temp sum before shifting is 9 bits *)\r\n (* Repeat operation performed for bytes 2 through 31)\r\n DEST[255:248] <- (SRC1[255:248] + SRC2[255:248] + 1) >> 1;\r\n\r\nVPAVGW (VEX.256 encoded instruction)\r\n DEST[15:0] <- (SRC1[15:0] + SRC2[15:0] + 1) >> 1; (* Temp sum before shifting is 17 bits *)\r\n (* Repeat operation performed for words 2 through 15)\r\n DEST[255:14]) <- (SRC1[255:240] + SRC2[255:240] + 1) >> 1;\r\nVPAVGB (EVEX encoded versions)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\nFOR j <- 0 TO KL-1\r\n i<-j*8\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- (SRC1[i+7:i] + SRC2[i+7:i] + 1) >> 1; (* Temp sum before shifting is 9 bits *)\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+7:i] = 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPAVGW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- (SRC1[i+15:i] + SRC2[i+15:i] + 1) >> 1\r\n ; (* Temp sum before shifting is 17 bits *)\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] = 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPAVGB __m512i _mm512_avg_epu8( __m512i a, __m512i b);\r\nVPAVGW __m512i _mm512_avg_epu16( __m512i a, __m512i b);\r\nVPAVGB __m512i _mm512_mask_avg_epu8(__m512i s, __mmask64 m, __m512i a, __m512i b);\r\nVPAVGW __m512i _mm512_mask_avg_epu16(__m512i s, __mmask32 m, __m512i a, __m512i b);\r\nVPAVGB __m512i _mm512_maskz_avg_epu8( __mmask64 m, __m512i a, __m512i b);\r\nVPAVGW __m512i _mm512_maskz_avg_epu16( __mmask32 m, __m512i a, __m512i b);\r\nVPAVGB __m256i _mm256_mask_avg_epu8(__m256i s, __mmask32 m, __m256i a, __m256i b);\r\nVPAVGW __m256i _mm256_mask_avg_epu16(__m256i s, __mmask16 m, __m256i a, __m256i b);\r\nVPAVGB __m256i _mm256_maskz_avg_epu8( __mmask32 m, __m256i a, __m256i b);\r\nVPAVGW __m256i _mm256_maskz_avg_epu16( __mmask16 m, __m256i a, __m256i b);\r\nVPAVGB __m128i _mm_mask_avg_epu8(__m128i s, __mmask16 m, __m128i a, __m128i b);\r\nVPAVGW __m128i _mm_mask_avg_epu16(__m128i s, __mmask8 m, __m128i a, __m128i b);\r\nVPAVGB __m128i _mm_maskz_avg_epu8( __mmask16 m, __m128i a, __m128i b);\r\nVPAVGW __m128i _mm_maskz_avg_epu16( __mmask8 m, __m128i a, __m128i b);\r\nPAVGB: __m64 _mm_avg_pu8 (__m64 a, __m64 b)\r\nPAVGW: __m64 _mm_avg_pu16 (__m64 a, __m64 b)\r\n(V)PAVGB: __m128i _mm_avg_epu8 ( __m128i a, __m128i b)\r\n(V)PAVGW: __m128i _mm_avg_epu16 ( __m128i a, __m128i b)\r\nVPAVGB: __m256i _mm256_avg_epu8 ( __m256i a, __m256i b)\r\nVPAVGW: __m256i _mm256_avg_epu16 ( __m256i a, __m256i b)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nNumeric Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PAVGB"
},
{
"description": "-R:PAVGB",
"mnem": "PAVGW"
},
{
"description": "PBLENDVB - Variable Blend Packed Bytes\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n66 0F 38 10 /r RM V/V SSE4_1 Select byte values from xmm1 and\r\nPBLENDVB xmm1, xmm2/m128, <XMM0> xmm2/m128 from mask specified in the high\r\n bit of each byte in XMM0 and store the\r\n values into xmm1.\r\nVEX.NDS.128.66.0F3A.W0 4C /r /is4 RVMR V/V AVX Select byte values from xmm2 and\r\nVPBLENDVB xmm1, xmm2, xmm3/m128, xmm4 xmm3/m128 using mask bits in the specified\r\n mask register, xmm4, and store the values\r\n into xmm1.\r\nVEX.NDS.256.66.0F3A.W0 4C /r /is4 RVMR V/V AVX2 Select byte values from ymm2 and\r\nVPBLENDVB ymm1, ymm2, ymm3/m256, ymm4 ymm3/m256 from mask specified in the high\r\n bit of each byte in ymm4 and store the\r\n values into ymm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) <XMM0> NA\r\n RVMR ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8[7:4]\r\n\r\n\r\nDescription\r\nConditionally copies byte elements from the source operand (second operand) to the destination operand (first\r\noperand) depending on mask bits defined in the implicit third register argument, XMM0. The mask bits are the most\r\nsignificant bit in each byte element of the XMM0 register.\r\nIf a mask bit is \"1\", then the corresponding byte element in the source operand is copied to the destination, else\r\nthe byte element in the destination operand is left unchanged.\r\nThe register assignment of the implicit third operand is defined to be the architectural register XMM0.\r\n128-bit Legacy SSE version: The first source operand and the destination operand is the same. Bits (VLMAX-1:128)\r\nof the corresponding YMM destination register remain unchanged. The mask register operand is implicitly defined\r\nto be the architectural register XMM0. An attempt to execute PBLENDVB with a VEX prefix will cause #UD.\r\nVEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second\r\nsource operand is an XMM register or 128-bit memory location. The mask operand is the third source register, and\r\nencoded in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is\r\nignored. The upper bits (VLMAX-1:128) of the corresponding YMM register (destination register) are zeroed. VEX.L\r\nmust be 0, otherwise the instruction will #UD. VEX.W must be 0, otherwise, the instruction will #UD.\r\nVEX.256 encoded version: The first source operand and the destination operand are YMM registers. The second\r\nsource operand is an YMM register or 256-bit memory location. The third source register is an YMM register and\r\nencoded in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is\r\nignored.\r\nVPBLENDVB permits the mask to be any XMM or YMM register. In contrast, PBLENDVB treats XMM0 implicitly as the\r\nmask and do not support non-destructive destination operation. An attempt to execute PBLENDVB encoded with a\r\nVEX prefix will cause a #UD exception.\r\n\r\nOperation\r\nPBLENDVB (128-bit Legacy SSE version)\r\nMASK <- XMM0\r\nIF (MASK[7] = 1) THEN DEST[7:0] <- SRC[7:0];\r\nELSE DEST[7:0] <- DEST[7:0];\r\nIF (MASK[15] = 1) THEN DEST[15:8] <- SRC[15:8];\r\n\r\n\r\nELSE DEST[15:8] <- DEST[15:8];\r\nIF (MASK[23] = 1) THEN DEST[23:16] <- SRC[23:16]\r\nELSE DEST[23:16] <- DEST[23:16];\r\nIF (MASK[31] = 1) THEN DEST[31:24] <- SRC[31:24]\r\nELSE DEST[31:24] <- DEST[31:24];\r\nIF (MASK[39] = 1) THEN DEST[39:32] <- SRC[39:32]\r\nELSE DEST[39:32] <- DEST[39:32];\r\nIF (MASK[47] = 1) THEN DEST[47:40] <- SRC[47:40]\r\nELSE DEST[47:40] <- DEST[47:40];\r\nIF (MASK[55] = 1) THEN DEST[55:48] <- SRC[55:48]\r\nELSE DEST[55:48] <- DEST[55:48];\r\nIF (MASK[63] = 1) THEN DEST[63:56] <- SRC[63:56]\r\nELSE DEST[63:56] <- DEST[63:56];\r\nIF (MASK[71] = 1) THEN DEST[71:64] <- SRC[71:64]\r\nELSE DEST[71:64] <- DEST[71:64];\r\nIF (MASK[79] = 1) THEN DEST[79:72] <- SRC[79:72]\r\nELSE DEST[79:72] <- DEST[79:72];\r\nIF (MASK[87] = 1) THEN DEST[87:80] <- SRC[87:80]\r\nELSE DEST[87:80] <- DEST[87:80];\r\nIF (MASK[95] = 1) THEN DEST[95:88] <- SRC[95:88]\r\nELSE DEST[95:88] <- DEST[95:88];\r\nIF (MASK[103] = 1) THEN DEST[103:96] <- SRC[103:96]\r\nELSE DEST[103:96] <- DEST[103:96];\r\nIF (MASK[111] = 1) THEN DEST[111:104] <- SRC[111:104]\r\nELSE DEST[111:104] <- DEST[111:104];\r\nIF (MASK[119] = 1) THEN DEST[119:112] <- SRC[119:112]\r\nELSE DEST[119:112] <- DEST[119:112];\r\nIF (MASK[127] = 1) THEN DEST[127:120] <- SRC[127:120]\r\nELSE DEST[127:120] <- DEST[127:120])\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVPBLENDVB (VEX.128 encoded version)\r\nMASK <- SRC3\r\nIF (MASK[7] = 1) THEN DEST[7:0] <- SRC2[7:0];\r\nELSE DEST[7:0] <- SRC1[7:0];\r\nIF (MASK[15] = 1) THEN DEST[15:8] <- SRC2[15:8];\r\nELSE DEST[15:8] <- SRC1[15:8];\r\nIF (MASK[23] = 1) THEN DEST[23:16] <- SRC2[23:16]\r\nELSE DEST[23:16] <- SRC1[23:16];\r\nIF (MASK[31] = 1) THEN DEST[31:24] <- SRC2[31:24]\r\nELSE DEST[31:24] <- SRC1[31:24];\r\nIF (MASK[39] = 1) THEN DEST[39:32] <- SRC2[39:32]\r\nELSE DEST[39:32] <- SRC1[39:32];\r\nIF (MASK[47] = 1) THEN DEST[47:40] <- SRC2[47:40]\r\nELSE DEST[47:40] <- SRC1[47:40];\r\nIF (MASK[55] = 1) THEN DEST[55:48] <- SRC2[55:48]\r\nELSE DEST[55:48] <- SRC1[55:48];\r\nIF (MASK[63] = 1) THEN DEST[63:56] <- SRC2[63:56]\r\nELSE DEST[63:56] <- SRC1[63:56];\r\nIF (MASK[71] = 1) THEN DEST[71:64] <- SRC2[71:64]\r\nELSE DEST[71:64] <- SRC1[71:64];\r\nIF (MASK[79] = 1) THEN DEST[79:72] <- SRC2[79:72]\r\nELSE DEST[79:72] <- SRC1[79:72];\r\nIF (MASK[87] = 1) THEN DEST[87:80] <- SRC2[87:80]\r\n\r\n\r\n\r\nELSE DEST[87:80] <- SRC1[87:80];\r\nIF (MASK[95] = 1) THEN DEST[95:88] <- SRC2[95:88]\r\nELSE DEST[95:88] <- SRC1[95:88];\r\nIF (MASK[103] = 1) THEN DEST[103:96] <- SRC2[103:96]\r\nELSE DEST[103:96] <- SRC1[103:96];\r\nIF (MASK[111] = 1) THEN DEST[111:104] <- SRC2[111:104]\r\nELSE DEST[111:104] <- SRC1[111:104];\r\nIF (MASK[119] = 1) THEN DEST[119:112] <- SRC2[119:112]\r\nELSE DEST[119:112] <- SRC1[119:112];\r\nIF (MASK[127] = 1) THEN DEST[127:120] <- SRC2[127:120]\r\nELSE DEST[127:120] <- SRC1[127:120])\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPBLENDVB (VEX.256 encoded version)\r\nMASK <- SRC3\r\nIF (MASK[7] == 1) THEN DEST[7:0] <- SRC2[7:0];\r\nELSE DEST[7:0] <- SRC1[7:0];\r\nIF (MASK[15] == 1) THEN DEST[15:8] <-SRC2[15:8];\r\nELSE DEST[15:8] <- SRC1[15:8];\r\nIF (MASK[23] == 1) THEN DEST[23:16] <-SRC2[23:16]\r\nELSE DEST[23:16] <- SRC1[23:16];\r\nIF (MASK[31] == 1) THEN DEST[31:24] <- SRC2[31:24]\r\nELSE DEST[31:24] <- SRC1[31:24];\r\nIF (MASK[39] == 1) THEN DEST[39:32] <- SRC2[39:32]\r\nELSE DEST[39:32] <- SRC1[39:32];\r\nIF (MASK[47] == 1) THEN DEST[47:40] <- SRC2[47:40]\r\nELSE DEST[47:40] <- SRC1[47:40];\r\nIF (MASK[55] == 1) THEN DEST[55:48] <- SRC2[55:48]\r\nELSE DEST[55:48] <- SRC1[55:48];\r\nIF (MASK[63] == 1) THEN DEST[63:56] <-SRC2[63:56]\r\nELSE DEST[63:56] <- SRC1[63:56];\r\nIF (MASK[71] == 1) THEN DEST[71:64] <-SRC2[71:64]\r\nELSE DEST[71:64] <- SRC1[71:64];\r\nIF (MASK[79] == 1) THEN DEST[79:72] <- SRC2[79:72]\r\nELSE DEST[79:72] <- SRC1[79:72];\r\nIF (MASK[87] == 1) THEN DEST[87:80] <- SRC2[87:80]\r\nELSE DEST[87:80] <- SRC1[87:80];\r\nIF (MASK[95] == 1) THEN DEST[95:88] <- SRC2[95:88]\r\nELSE DEST[95:88] <- SRC1[95:88];\r\nIF (MASK[103] == 1) THEN DEST[103:96] <- SRC2[103:96]\r\nELSE DEST[103:96] <- SRC1[103:96];\r\nIF (MASK[111] == 1) THEN DEST[111:104] <- SRC2[111:104]\r\nELSE DEST[111:104] <- SRC1[111:104];\r\nIF (MASK[119] == 1) THEN DEST[119:112] <- SRC2[119:112]\r\nELSE DEST[119:112] <- SRC1[119:112];\r\nIF (MASK[127] == 1) THEN DEST[127:120] <- SRC2[127:120]\r\nELSE DEST[127:120] <- SRC1[127:120])\r\nIF (MASK[135] == 1) THEN DEST[135:128] <- SRC2[135:128];\r\nELSE DEST[135:128] <- SRC1[135:128];\r\nIF (MASK[143] == 1) THEN DEST[143:136] <- SRC2[143:136];\r\nELSE DEST[[143:136] <- SRC1[143:136];\r\nIF (MASK[151] == 1) THEN DEST[151:144] <- SRC2[151:144]\r\nELSE DEST[151:144] <- SRC1[151:144];\r\nIF (MASK[159] == 1) THEN DEST[159:152] <- SRC2[159:152]\r\n\r\n\r\n\r\nELSE DEST[159:152] <- SRC1[159:152];\r\nIF (MASK[167] == 1) THEN DEST[167:160] <- SRC2[167:160]\r\nELSE DEST[167:160] <- SRC1[167:160];\r\nIF (MASK[175] == 1) THEN DEST[175:168] <- SRC2[175:168]\r\nELSE DEST[175:168] <- SRC1[175:168];\r\nIF (MASK[183] == 1) THEN DEST[183:176] <- SRC2[183:176]\r\nELSE DEST[183:176] <- SRC1[183:176];\r\nIF (MASK[191] == 1) THEN DEST[191:184] <- SRC2[191:184]\r\nELSE DEST[191:184] <- SRC1[191:184];\r\nIF (MASK[199] == 1) THEN DEST[199:192] <- SRC2[199:192]\r\nELSE DEST[199:192] <- SRC1[199:192];\r\nIF (MASK[207] == 1) THEN DEST[207:200] <- SRC2[207:200]\r\nELSE DEST[207:200] <- SRC1[207:200]\r\nIF (MASK[215] == 1) THEN DEST[215:208] <- SRC2[215:208]\r\nELSE DEST[215:208] <- SRC1[215:208];\r\nIF (MASK[223] == 1) THEN DEST[223:216] <- SRC2[223:216]\r\nELSE DEST[223:216] <- SRC1[223:216];\r\nIF (MASK[231] == 1) THEN DEST[231:224] <- SRC2[231:224]\r\nELSE DEST[231:224] <- SRC1[231:224];\r\nIF (MASK[239] == 1) THEN DEST[239:232] <- SRC2[239:232]\r\nELSE DEST[239:232] <- SRC1[239:232];\r\nIF (MASK[247] == 1) THEN DEST[247:240] <- SRC2[247:240]\r\nELSE DEST[247:240] <- SRC1[247:240];\r\nIF (MASK[255] == 1) THEN DEST[255:248] <- SRC2[255:248]\r\nELSE DEST[255:248] <- SRC1[255:248]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n(V)PBLENDVB: __m128i _mm_blendv_epi8 (__m128i v1, __m128i v2, __m128i mask);\r\nVPBLENDVB: __m256i _mm256_blendv_epi8 (__m256i v1, __m256i v2, __m256i mask);\r\n\r\nFlags Affected\r\nNone.\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4; additionally\r\n#UD If VEX.W = 1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PBLENDVB"
},
{
"description": "PBLENDW - Blend Packed Words\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n66 0F 3A 0E /r ib RMI V/V SSE4_1 Select words from xmm1 and xmm2/m128\r\nPBLENDW xmm1, xmm2/m128, imm8 from mask specified in imm8 and store the\r\n values into xmm1.\r\nVEX.NDS.128.66.0F3A.WIG 0E /r ib RVMI V/V AVX Select words from xmm2 and xmm3/m128\r\nVPBLENDW xmm1, xmm2, xmm3/m128, imm8 from mask specified in imm8 and store the\r\n values into xmm1.\r\nVEX.NDS.256.66.0F3A.WIG 0E /r ib RVMI V/V AVX2 Select words from ymm2 and ymm3/m256\r\nVPBLENDW ymm1, ymm2, ymm3/m256, imm8 from mask specified in imm8 and store the\r\n values into ymm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (r, w) ModRM:r/m (r) imm8 NA\r\n RVMI ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8\r\n\r\n\r\nDescription\r\nWords from the source operand (second operand) are conditionally written to the destination operand (first\r\noperand) depending on bits in the immediate operand (third operand). The immediate bits (bits 7:0) form a mask\r\nthat determines whether the corresponding word in the destination is copied from the source. If a bit in the mask,\r\ncorresponding to a word, is \"1\", then the word is copied, else the word element in the destination operand is\r\nunchanged.\r\n128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The\r\nfirst source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination\r\nregister remain unchanged.\r\nVEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The\r\nfirst source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM register\r\nare zeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register\r\nor a 256-bit memory location. The destination operand is a YMM register.\r\n\r\nOperation\r\nPBLENDW (128-bit Legacy SSE version)\r\nIF (imm8[0] = 1) THEN DEST[15:0] <- SRC[15:0]\r\nELSE DEST[15:0] <- DEST[15:0]\r\nIF (imm8[1] = 1) THEN DEST[31:16] <- SRC[31:16]\r\nELSE DEST[31:16] <- DEST[31:16]\r\nIF (imm8[2] = 1) THEN DEST[47:32] <- SRC[47:32]\r\nELSE DEST[47:32] <- DEST[47:32]\r\nIF (imm8[3] = 1) THEN DEST[63:48] <- SRC[63:48]\r\nELSE DEST[63:48] <- DEST[63:48]\r\nIF (imm8[4] = 1) THEN DEST[79:64] <- SRC[79:64]\r\nELSE DEST[79:64] <- DEST[79:64]\r\nIF (imm8[5] = 1) THEN DEST[95:80] <- SRC[95:80]\r\nELSE DEST[95:80] <- DEST[95:80]\r\nIF (imm8[6] = 1) THEN DEST[111:96] <- SRC[111:96]\r\nELSE DEST[111:96] <- DEST[111:96]\r\nIF (imm8[7] = 1) THEN DEST[127:112] <- SRC[127:112]\r\n\r\n\r\n\r\nELSE DEST[127:112] <- DEST[127:112]\r\n\r\nVPBLENDW (VEX.128 encoded version)\r\nIF (imm8[0] = 1) THEN DEST[15:0] <- SRC2[15:0]\r\nELSE DEST[15:0] <- SRC1[15:0]\r\nIF (imm8[1] = 1) THEN DEST[31:16] <- SRC2[31:16]\r\nELSE DEST[31:16] <- SRC1[31:16]\r\nIF (imm8[2] = 1) THEN DEST[47:32] <- SRC2[47:32]\r\nELSE DEST[47:32] <- SRC1[47:32]\r\nIF (imm8[3] = 1) THEN DEST[63:48] <- SRC2[63:48]\r\nELSE DEST[63:48] <- SRC1[63:48]\r\nIF (imm8[4] = 1) THEN DEST[79:64] <- SRC2[79:64]\r\nELSE DEST[79:64] <- SRC1[79:64]\r\nIF (imm8[5] = 1) THEN DEST[95:80] <- SRC2[95:80]\r\nELSE DEST[95:80] <- SRC1[95:80]\r\nIF (imm8[6] = 1) THEN DEST[111:96] <- SRC2[111:96]\r\nELSE DEST[111:96] <- SRC1[111:96]\r\nIF (imm8[7] = 1) THEN DEST[127:112] <- SRC2[127:112]\r\nELSE DEST[127:112] <- SRC1[127:112]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPBLENDW (VEX.256 encoded version)\r\nIF (imm8[0] == 1) THEN DEST[15:0] <- SRC2[15:0]\r\nELSE DEST[15:0] <- SRC1[15:0]\r\nIF (imm8[1] == 1) THEN DEST[31:16] <- SRC2[31:16]\r\nELSE DEST[31:16] <- SRC1[31:16]\r\nIF (imm8[2] == 1) THEN DEST[47:32] <- SRC2[47:32]\r\nELSE DEST[47:32] <- SRC1[47:32]\r\nIF (imm8[3] == 1) THEN DEST[63:48] <- SRC2[63:48]\r\nELSE DEST[63:48] <- SRC1[63:48]\r\nIF (imm8[4] == 1) THEN DEST[79:64] <- SRC2[79:64]\r\nELSE DEST[79:64] <- SRC1[79:64]\r\nIF (imm8[5] == 1) THEN DEST[95:80] <- SRC2[95:80]\r\nELSE DEST[95:80] <- SRC1[95:80]\r\nIF (imm8[6] == 1) THEN DEST[111:96] <- SRC2[111:96]\r\nELSE DEST[111:96] <- SRC1[111:96]\r\nIF (imm8[7] == 1) THEN DEST[127:112] <- SRC2[127:112]\r\nELSE DEST[127:112] <- SRC1[127:112]\r\nIF (imm8[0] == 1) THEN DEST[143:128] <- SRC2[143:128]\r\nELSE DEST[143:128] <- SRC1[143:128]\r\nIF (imm8[1] == 1) THEN DEST[159:144] <- SRC2[159:144]\r\nELSE DEST[159:144] <- SRC1[159:144]\r\nIF (imm8[2] == 1) THEN DEST[175:160] <- SRC2[175:160]\r\nELSE DEST[175:160] <- SRC1[175:160]\r\nIF (imm8[3] == 1) THEN DEST[191:176] <- SRC2[191:176]\r\nELSE DEST[191:176] <- SRC1[191:176]\r\nIF (imm8[4] == 1) THEN DEST[207:192] <- SRC2[207:192]\r\nELSE DEST[207:192] <- SRC1[207:192]\r\nIF (imm8[5] == 1) THEN DEST[223:208] <- SRC2[223:208]\r\nELSE DEST[223:208] <- SRC1[223:208]\r\nIF (imm8[6] == 1) THEN DEST[239:224] <- SRC2[239:224]\r\nELSE DEST[239:224] <- SRC1[239:224]\r\nIF (imm8[7] == 1) THEN DEST[255:240] <- SRC2[255:240]\r\nELSE DEST[255:240] <- SRC1[255:240]\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n(V)PBLENDW: __m128i _mm_blend_epi16 (__m128i v1, __m128i v2, const int mask);\r\nVPBLENDW: __m256i _mm256_blend_epi16 (__m256i v1, __m256i v2, const int mask)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4; additionally\r\n#UD If VEX.L = 1 and AVX2 = 0.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PBLENDW"
},
{
"description": "PCLMULQDQ - Carry-Less Multiplication Quadword\r\n Opcode/ Op/ 64/32 bit CPUID Description\r\n Instruction En Mode Feature\r\n Support Flag\r\n 66 0F 3A 44 /r ib RMI V/V PCLMUL- Carry-less multiplication of one quadword of\r\n PCLMULQDQ xmm1, xmm2/m128, imm8 QDQ xmm1 by one quadword of xmm2/m128,\r\n stores the 128-bit result in xmm1. The imme-\r\n diate is used to determine which quadwords\r\n of xmm1 and xmm2/m128 should be used.\r\n VEX.NDS.128.66.0F3A.WIG 44 /r ib RVMI V/V Both PCL- Carry-less multiplication of one quadword of\r\n VPCLMULQDQ xmm1, xmm2, xmm3/m128, imm8 MULQDQ xmm2 by one quadword of xmm3/m128,\r\n and AVX stores the 128-bit result in xmm1. The imme-\r\n flags diate is used to determine which quadwords\r\n of xmm2 and xmm3/m128 should be used.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand2 Operand3 Operand4\r\n RMI ModRM:reg (r, w) ModRM:r/m (r) imm8 NA\r\n RVMI ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8\r\n\r\n\r\nDescription\r\nPerforms a carry-less multiplication of two quadwords, selected from the first source and second source operand\r\naccording to the value of the immediate byte. Bits 4 and 0 are used to select which 64-bit half of each operand to\r\nuse according to Table 4-13, other bits of the immediate byte are ignored.\r\n\r\n Table 4-13. PCLMULQDQ Quadword Selection of Immediate Byte\r\n Imm[4] Imm[0] PCLMULQDQ Operation\r\n 1\r\n 0 0 CL_MUL( SRC2 [63:0], SRC1[63:0] )\r\n 0 1 CL_MUL( SRC2[63:0], SRC1[127:64] )\r\n 1 0 CL_MUL( SRC2[127:64], SRC1[63:0] )\r\n 1 1 CL_MUL( SRC2[127:64], SRC1[127:64] )\r\nNOTES:\r\n1. SRC2 denotes the second source operand, which can be a register or memory; SRC1 denotes the first source and destination oper-\r\n and.\r\n\r\n\r\n The first source operand and the destination operand are the same and must be an XMM register. The second\r\nsource operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding\r\nYMM destination register remain unchanged.\r\nCompilers and assemblers may implement the following pseudo-op syntax to simply programming and emit the\r\nrequired encoding for Imm8.\r\n\r\n Table 4-14. Pseudo-Op and PCLMULQDQ Implementation\r\n Pseudo-Op Imm8 Encoding\r\n PCLMULLQLQDQ xmm1, xmm2 0000_0000B\r\n PCLMULHQLQDQ xmm1, xmm2 0000_0001B\r\n PCLMULLQHQDQ xmm1, xmm2 0001_0000B\r\n PCLMULHQHQDQ xmm1, xmm2 0001_0001B\r\n\r\n\r\n\r\nOperation\r\nPCLMULQDQ\r\nIF (Imm8[0] = 0 )\r\n THEN\r\n TEMP1 <- SRC1 [63:0];\r\n ELSE\r\n TEMP1 <- SRC1 [127:64];\r\nFI\r\nIF (Imm8[4] = 0 )\r\n THEN\r\n TEMP2 <- SRC2 [63:0];\r\n ELSE\r\n TEMP2 <- SRC2 [127:64];\r\nFI\r\nFor i = 0 to 63 {\r\n TmpB [ i ] <- (TEMP1[ 0 ] and TEMP2[ i ]);\r\n For j = 1 to i {\r\n TmpB [ i ] <- TmpB [ i ] xor (TEMP1[ j ] and TEMP2[ i - j ])\r\n }\r\n DEST[ i ] <- TmpB[ i ];\r\n}\r\nFor i = 64 to 126 {\r\n TmpB [ i ] <- 0;\r\n For j = i - 63 to 63 {\r\n TmpB [ i ] <- TmpB [ i ] xor (TEMP1[ j ] and TEMP2[ i - j ])\r\n }\r\n DEST[ i ] <- TmpB[ i ];\r\n}\r\nDEST[127] <- 0;\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVPCLMULQDQ\r\nIF (Imm8[0] = 0 )\r\n THEN\r\n TEMP1 <- SRC1 [63:0];\r\n ELSE\r\n TEMP1 <- SRC1 [127:64];\r\nFI\r\nIF (Imm8[4] = 0 )\r\n THEN\r\n TEMP2 <- SRC2 [63:0];\r\n ELSE\r\n TEMP2 <- SRC2 [127:64];\r\nFI\r\nFor i = 0 to 63 {\r\n TmpB [ i ] <- (TEMP1[ 0 ] and TEMP2[ i ]);\r\n For j = 1 to i {\r\n TmpB [i] <- TmpB [i] xor (TEMP1[ j ] and TEMP2[ i - j ])\r\n }\r\n DEST[i] <- TmpB[i];\r\n}\r\nFor i = 64 to 126 {\r\n TmpB [ i ] <- 0;\r\n For j = i - 63 to 63 {\r\n\r\n\r\n TmpB [i] <- TmpB [i] xor (TEMP1[ j ] and TEMP2[ i - j ])\r\n }\r\n DEST[i] <- TmpB[i];\r\n}\r\nDEST[VLMAX-1:127] <- 0;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n(V)PCLMULQDQ: __m128i _mm_clmulepi64_si128 (__m128i, __m128i, const int)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4, additionally\r\n#UD If VEX.L = 1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PCLMULQDQ"
},
{
"description": "PCMPEQB/PCMPEQW/PCMPEQD- Compare Packed Data for Equal\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F 74 /r1 RM V/V MMX Compare packed bytes in mm/m64 and mm\r\nPCMPEQB mm, mm/m64 for equality.\r\n\r\n66 0F 74 /r RM V/V SSE2 Compare packed bytes in xmm2/m128 and\r\nPCMPEQB xmm1, xmm2/m128 xmm1 for equality.\r\n\r\n0F 75 /r1 RM V/V MMX Compare packed words in mm/m64 and mm\r\nPCMPEQW mm, mm/m64 for equality.\r\n\r\n66 0F 75 /r RM V/V SSE2 Compare packed words in xmm2/m128 and\r\nPCMPEQW xmm1, xmm2/m128 xmm1 for equality.\r\n\r\n0F 76 /r1 RM V/V MMX Compare packed doublewords in mm/m64 and\r\nPCMPEQD mm, mm/m64 mm for equality.\r\n\r\n66 0F 76 /r RM V/V SSE2 Compare packed doublewords in xmm2/m128\r\nPCMPEQD xmm1, xmm2/m128 and xmm1 for equality.\r\n\r\nVEX.NDS.128.66.0F.WIG 74 /r RVM V/V AVX Compare packed bytes in xmm3/m128 and\r\nVPCMPEQB xmm1, xmm2, xmm3/m128 xmm2 for equality.\r\n\r\nVEX.NDS.128.66.0F.WIG 75 /r RVM V/V AVX Compare packed words in xmm3/m128 and\r\nVPCMPEQW xmm1, xmm2, xmm3/m128 xmm2 for equality.\r\n\r\nVEX.NDS.128.66.0F.WIG 76 /r RVM V/V AVX Compare packed doublewords in xmm3/m128\r\nVPCMPEQD xmm1, xmm2, xmm3/m128 and xmm2 for equality.\r\n\r\nVEX.NDS.256.66.0F.WIG 74 /r RVM V/V AVX2 Compare packed bytes in ymm3/m256 and\r\nVPCMPEQB ymm1, ymm2, ymm3 /m256 ymm2 for equality.\r\nVEX.NDS.256.66.0F.WIG 75 /r RVM V/V AVX2 Compare packed words in ymm3/m256 and\r\nVPCMPEQW ymm1, ymm2, ymm3 /m256 ymm2 for equality.\r\n\r\nVEX.NDS.256.66.0F.WIG 76 /r RVM V/V AVX2 Compare packed doublewords in ymm3/m256\r\nVPCMPEQD ymm1, ymm2, ymm3 /m256 and ymm2 for equality.\r\n\r\nEVEX.NDS.128.66.0F.W0 76 /r FV V/V AVX512V Compare Equal between int32 vector xmm2\r\nVPCMPEQD k1 {k2}, xmm2, xmm3/m128/m32bcst L and int32 vector xmm3/m128/m32bcst, and\r\n AVX512F set vector mask k1 to reflect the\r\n zero/nonzero status of each element of the\r\n result, under writemask.\r\nEVEX.NDS.256.66.0F.W0 76 /r FV V/V AVX512V Compare Equal between int32 vector ymm2\r\nVPCMPEQD k1 {k2}, ymm2, ymm3/m256/m32bcst L and int32 vector ymm3/m256/m32bcst, and\r\n AVX512F set vector mask k1 to reflect the\r\n zero/nonzero status of each element of the\r\n result, under writemask.\r\nEVEX.NDS.512.66.0F.W0 76 /r FV V/V AVX512F Compare Equal between int32 vectors in\r\nVPCMPEQD k1 {k2}, zmm2, zmm3/m512/m32bcst zmm2 and zmm3/m512/m32bcst, and set\r\n destination k1 according to the comparison\r\n results under writemask k2.\r\nEVEX.NDS.128.66.0F.WIG 74 /r FVM V/V AVX512V Compare packed bytes in xmm3/m128 and\r\nVPCMPEQB k1 {k2}, xmm2, xmm3 /m128 L xmm2 for equality and set vector mask k1 to\r\n AVX512B reflect the zero/nonzero status of each\r\n W element of the result, under writemask.\r\n\r\n\r\n\r\n\r\n\r\nEVEX.NDS.256.66.0F.WIG 74 /r FVM V/V AVX512V Compare packed bytes in ymm3/m256 and\r\nVPCMPEQB k1 {k2}, ymm2, ymm3 /m256 L ymm2 for equality and set vector mask k1 to\r\n AVX512B reflect the zero/nonzero status of each\r\n W element of the result, under writemask.\r\nEVEX.NDS.512.66.0F.WIG 74 /r FVM V/V AVX512B Compare packed bytes in zmm3/m512 and\r\nVPCMPEQB k1 {k2}, zmm2, zmm3 /m512 W zmm2 for equality and set vector mask k1 to\r\n reflect the zero/nonzero status of each\r\n element of the result, under writemask.\r\nEVEX.NDS.128.66.0F.WIG 75 /r FVM V/V AVX512V Compare packed words in xmm3/m128 and\r\nVPCMPEQW k1 {k2}, xmm2, xmm3 /m128 L xmm2 for equality and set vector mask k1 to\r\n AVX512B reflect the zero/nonzero status of each\r\n W element of the result, under writemask.\r\nEVEX.NDS.256.66.0F.WIG 75 /r FVM V/V AVX512V Compare packed words in ymm3/m256 and\r\nVPCMPEQW k1 {k2}, ymm2, ymm3 /m256 L ymm2 for equality and set vector mask k1 to\r\n AVX512B reflect the zero/nonzero status of each\r\n W element of the result, under writemask.\r\nEVEX.NDS.512.66.0F.WIG 75 /r FVM V/V AVX512B Compare packed words in zmm3/m512 and\r\nVPCMPEQW k1 {k2}, zmm2, zmm3 /m512 W zmm2 for equality and set vector mask k1 to\r\n reflect the zero/nonzero status of each\r\n element of the result, under writemask.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nPerforms a SIMD compare for equality of the packed bytes, words, or doublewords in the destination operand (first\r\noperand) and the source operand (second operand). If a pair of data elements is equal, the corresponding data\r\nelement in the destination operand is set to all 1s; otherwise, it is set to all 0s.\r\nThe (V)PCMPEQB instruction compares the corresponding bytes in the destination and source operands; the\r\n(V)PCMPEQW instruction compares the corresponding words in the destination and source operands; and the\r\n(V)PCMPEQD instruction compares the corresponding doublewords in the destination and source operands.\r\nIn 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to\r\naccess additional registers (XMM8-XMM15).\r\nLegacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The\r\ndestination operand can be an MMX technology register.\r\n128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The\r\nfirst source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination\r\nregister remain unchanged.\r\nVEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The\r\nfirst source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM register\r\nare zeroed.\r\n\r\n\r\n\r\n\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register\r\nor a 256-bit memory location. The destination operand is a YMM register.\r\nEVEX encoded VPCMPEQD: The first source operand (second operand) is a ZMM/YMM/XMM register. The second\r\nsource operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector\r\nbroadcasted from a 32-bit memory location. The destination operand (first operand) is a mask register updated\r\naccording to the writemask k2.\r\nEVEX encoded VPCMPEQB/W: The first source operand (second operand) is a ZMM/YMM/XMM register. The second\r\nsource operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand\r\n(first operand) is a mask register updated according to the writemask k2.\r\n\r\nOperation\r\nPCMPEQB (with 64-bit operands)\r\n IF DEST[7:0] = SRC[7:0]\r\n THEN DEST[7:0) <- FFH;\r\n ELSE DEST[7:0] <- 0; FI;\r\n (* Continue comparison of 2nd through 7th bytes in DEST and SRC *)\r\n IF DEST[63:56] = SRC[63:56]\r\n THEN DEST[63:56] <- FFH;\r\n ELSE DEST[63:56] <- 0; FI;\r\n\r\nCOMPARE_BYTES_EQUAL (SRC1, SRC2)\r\n IF SRC1[7:0] = SRC2[7:0]\r\n THEN DEST[7:0] <-FFH;\r\n ELSE DEST[7:0] <-0; FI;\r\n(* Continue comparison of 2nd through 15th bytes in SRC1 and SRC2 *)\r\n IF SRC1[127:120] = SRC2[127:120]\r\n THEN DEST[127:120] <-FFH;\r\n ELSE DEST[127:120] <-0; FI;\r\n\r\nCOMPARE_WORDS_EQUAL (SRC1, SRC2)\r\n IF SRC1[15:0] = SRC2[15:0]\r\n THEN DEST[15:0] <-FFFFH;\r\n ELSE DEST[15:0] <-0; FI;\r\n(* Continue comparison of 2nd through 7th 16-bit words in SRC1 and SRC2 *)\r\n IF SRC1[127:112] = SRC2[127:112]\r\n THEN DEST[127:112] <-FFFFH;\r\n ELSE DEST[127:112] <-0; FI;\r\n\r\nCOMPARE_DWORDS_EQUAL (SRC1, SRC2)\r\n IF SRC1[31:0] = SRC2[31:0]\r\n THEN DEST[31:0] <-FFFFFFFFH;\r\n ELSE DEST[31:0] <-0; FI;\r\n(* Continue comparison of 2nd through 3rd 32-bit dwords in SRC1 and SRC2 *)\r\n IF SRC1[127:96] = SRC2[127:96]\r\n THEN DEST[127:96] <-FFFFFFFFH;\r\n ELSE DEST[127:96] <-0; FI;\r\n\r\n\r\nPCMPEQB (with 128-bit operands)\r\nDEST[127:0] <-COMPARE_BYTES_EQUAL(DEST[127:0],SRC[127:0])\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVPCMPEQB (VEX.128 encoded version)\r\nDEST[127:0] <-COMPARE_BYTES_EQUAL(SRC1[127:0],SRC2[127:0])\r\n\r\n\r\n\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPCMPEQB (VEX.256 encoded version)\r\nDEST[127:0] <-COMPARE_BYTES_EQUAL(SRC1[127:0],SRC2[127:0])\r\nDEST[255:128] <-COMPARE_BYTES_EQUAL(SRC1[255:128],SRC2[255:128])\r\nDEST[VLMAX-1:256] <- 0\r\n\r\nVPCMPEQB (EVEX encoded versions)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i<-j*8\r\n IF k2[j] OR *no writemask*\r\n THEN\r\n /* signed comparison */\r\n CMP <- SRC1[i+7:i] == SRC2[i+7:i];\r\n IF CMP = TRUE\r\n THEN DEST[j] <- 1;\r\n ELSE DEST[j] <- 0; FI;\r\n ELSE DEST[j] <- 0 ; zeroing-masking onlyFI;\r\n FI;\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\nPCMPEQW (with 64-bit operands)\r\n IF DEST[15:0] = SRC[15:0]\r\n THEN DEST[15:0] <- FFFFH;\r\n ELSE DEST[15:0] <- 0; FI;\r\n (* Continue comparison of 2nd and 3rd words in DEST and SRC *)\r\n IF DEST[63:48] = SRC[63:48]\r\n THEN DEST[63:48] <- FFFFH;\r\n ELSE DEST[63:48] <- 0; FI;\r\n\r\nPCMPEQW (with 128-bit operands)\r\nDEST[127:0] <-COMPARE_WORDS_EQUAL(DEST[127:0],SRC[127:0])\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVPCMPEQW (VEX.128 encoded version)\r\nDEST[127:0] <-COMPARE_WORDS_EQUAL(SRC1[127:0],SRC2[127:0])\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPCMPEQW (VEX.256 encoded version)\r\nDEST[127:0] <-COMPARE_WORDS_EQUAL(SRC1[127:0],SRC2[127:0])\r\nDEST[255:128] <-COMPARE_WORDS_EQUAL(SRC1[255:128],SRC2[255:128])\r\nDEST[VLMAX-1:256] <- 0\r\n\r\nVPCMPEQW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k2[j] OR *no writemask*\r\n THEN\r\n /* signed comparison */\r\n CMP <- SRC1[i+15:i] == SRC2[i+15:i];\r\n IF CMP = TRUE\r\n\r\n\r\n\r\n THEN DEST[j] <- 1;\r\n ELSE DEST[j] <- 0; FI;\r\n ELSE DEST[j] <- 0 ; zeroing-masking onlyFI;\r\n FI;\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\nPCMPEQD (with 64-bit operands)\r\n IF DEST[31:0] = SRC[31:0]\r\n THEN DEST[31:0] <- FFFFFFFFH;\r\n ELSE DEST[31:0] <- 0; FI;\r\n IF DEST[63:32] = SRC[63:32]\r\n THEN DEST[63:32] <- FFFFFFFFH;\r\n ELSE DEST[63:32] <- 0; FI;\r\n\r\nPCMPEQD (with 128-bit operands)\r\nDEST[127:0] <-COMPARE_DWORDS_EQUAL(DEST[127:0],SRC[127:0])\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVPCMPEQD (VEX.128 encoded version)\r\nDEST[127:0] <-COMPARE_DWORDS_EQUAL(SRC1[127:0],SRC2[127:0])\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPCMPEQD (VEX.256 encoded version)\r\nDEST[127:0] <-COMPARE_DWORDS_EQUAL(SRC1[127:0],SRC2[127:0])\r\nDEST[255:128] <-COMPARE_DWORDS_EQUAL(SRC1[255:128],SRC2[255:128])\r\nDEST[VLMAX-1:256] <- 0\r\n\r\nVPCMPEQD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k2[j] OR *no writemask*\r\n THEN\r\n /* signed comparison */\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN CMP <- SRC1[i+31:i] = SRC2[31:0];\r\n ELSE CMP <- SRC1[i+31:i] = SRC2[i+31:i];\r\n FI;\r\n IF CMP = TRUE\r\n THEN DEST[j] <- 1;\r\n ELSE DEST[j] <- 0; FI;\r\n ELSE DEST[j] <- 0 ; zeroing-masking only\r\n FI;\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPCMPEQB __mmask64 _mm512_cmpeq_epi8_mask(__m512i a, __m512i b);\r\nVPCMPEQB __mmask64 _mm512_mask_cmpeq_epi8_mask(__mmask64 k, __m512i a, __m512i b);\r\nVPCMPEQB __mmask32 _mm256_cmpeq_epi8_mask(__m256i a, __m256i b);\r\nVPCMPEQB __mmask32 _mm256_mask_cmpeq_epi8_mask(__mmask32 k, __m256i a, __m256i b);\r\nVPCMPEQB __mmask16 _mm_cmpeq_epi8_mask(__m128i a, __m128i b);\r\nVPCMPEQB __mmask16 _mm_mask_cmpeq_epi8_mask(__mmask16 k, __m128i a, __m128i b);\r\n\r\n\r\n\r\n\r\nVPCMPEQW __mmask32 _mm512_cmpeq_epi16_mask(__m512i a, __m512i b);\r\nVPCMPEQW __mmask32 _mm512_mask_cmpeq_epi16_mask(__mmask32 k, __m512i a, __m512i b);\r\nVPCMPEQW __mmask16 _mm256_cmpeq_epi16_mask(__m256i a, __m256i b);\r\nVPCMPEQW __mmask16 _mm256_mask_cmpeq_epi16_mask(__mmask16 k, __m256i a, __m256i b);\r\nVPCMPEQW __mmask8 _mm_cmpeq_epi16_mask(__m128i a, __m128i b);\r\nVPCMPEQW __mmask8 _mm_mask_cmpeq_epi16_mask(__mmask8 k, __m128i a, __m128i b);\r\nVPCMPEQD __mmask16 _mm512_cmpeq_epi32_mask( __m512i a, __m512i b);\r\nVPCMPEQD __mmask16 _mm512_mask_cmpeq_epi32_mask(__mmask16 k, __m512i a, __m512i b);\r\nVPCMPEQD __mmask8 _mm256_cmpeq_epi32_mask(__m256i a, __m256i b);\r\nVPCMPEQD __mmask8 _mm256_mask_cmpeq_epi32_mask(__mmask8 k, __m256i a, __m256i b);\r\nVPCMPEQD __mmask8 _mm_cmpeq_epi32_mask(__m128i a, __m128i b);\r\nVPCMPEQD __mmask8 _mm_mask_cmpeq_epi32_mask(__mmask8 k, __m128i a, __m128i b);\r\nPCMPEQB: __m64 _mm_cmpeq_pi8 (__m64 m1, __m64 m2)\r\nPCMPEQW: __m64 _mm_cmpeq_pi16 (__m64 m1, __m64 m2)\r\nPCMPEQD: __m64 _mm_cmpeq_pi32 (__m64 m1, __m64 m2)\r\n(V)PCMPEQB: __m128i _mm_cmpeq_epi8 ( __m128i a, __m128i b)\r\n(V)PCMPEQW: __m128i _mm_cmpeq_epi16 ( __m128i a, __m128i b)\r\n(V)PCMPEQD: __m128i _mm_cmpeq_epi32 ( __m128i a, __m128i b)\r\nVPCMPEQB: __m256i _mm256_cmpeq_epi8 ( __m256i a, __m256i b)\r\nVPCMPEQW: __m256i _mm256_cmpeq_epi16 ( __m256i a, __m256i b)\r\nVPCMPEQD: __m256i _mm256_cmpeq_epi32 ( __m256i a, __m256i b)\r\n\r\n\r\n\r\nFlags Affected\r\nNone.\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded VPCMPEQD, see Exceptions Type E4.\r\nEVEX-encoded VPCMPEQB/W, see Exceptions Type E4.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PCMPEQB"
},
{
"description": "-R:PCMPEQB",
"mnem": "PCMPEQD"
},
{
"description": "PCMPEQQ - Compare Packed Qword Data for Equal\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n66 0F 38 29 /r RM V/V SSE4_1 Compare packed qwords in xmm2/m128 and\r\nPCMPEQQ xmm1, xmm2/m128 xmm1 for equality.\r\nVEX.NDS.128.66.0F38.WIG 29 /r RVM V/V AVX Compare packed quadwords in xmm3/m128\r\nVPCMPEQQ xmm1, xmm2, xmm3/m128 and xmm2 for equality.\r\nVEX.NDS.256.66.0F38.WIG 29 /r RVM V/V AVX2 Compare packed quadwords in ymm3/m256\r\nVPCMPEQQ ymm1, ymm2, ymm3 /m256 and ymm2 for equality.\r\nEVEX.NDS.128.66.0F38.W1 29 /r FV V/V AVX512VL Compare Equal between int64 vector xmm2\r\nVPCMPEQQ k1 {k2}, xmm2, xmm3/m128/m64bcst AVX512F and int64 vector xmm3/m128/m64bcst, and\r\n set vector mask k1 to reflect the zero/nonzero\r\n status of each element of the result, under\r\n writemask.\r\nEVEX.NDS.256.66.0F38.W1 29 /r FV V/V AVX512VL Compare Equal between int64 vector ymm2\r\nVPCMPEQQ k1 {k2}, ymm2, ymm3/m256/m64bcst AVX512F and int64 vector ymm3/m256/m64bcst, and\r\n set vector mask k1 to reflect the zero/nonzero\r\n status of each element of the result, under\r\n writemask.\r\nEVEX.NDS.512.66.0F38.W1 29 /r FV V/V AVX512F Compare Equal between int64 vector zmm2\r\nVPCMPEQQ k1 {k2}, zmm2, zmm3/m512/m64bcst and int64 vector zmm3/m512/m64bcst, and\r\n set vector mask k1 to reflect the zero/nonzero\r\n status of each element of the result, under\r\n writemask.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nPerforms an SIMD compare for equality of the packed quadwords in the destination operand (first operand) and the\r\nsource operand (second operand). If a pair of data elements is equal, the corresponding data element in the desti-\r\nnation is set to all 1s; otherwise, it is set to 0s.\r\n128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The\r\nfirst source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination\r\nregister remain unchanged.\r\nVEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The\r\nfirst source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM register\r\nare zeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register\r\nor a 256-bit memory location. The destination operand is a YMM register.\r\nEVEX encoded VPCMPEQQ: The first source operand (second operand) is a ZMM/YMM/XMM register. The second\r\nsource operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector\r\nbroadcasted from a 64-bit memory location. The destination operand (first operand) is a mask register updated\r\naccording to the writemask k2.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\n\r\nPCMPEQQ (with 128-bit operands)\r\nIF (DEST[63:0] = SRC[63:0])\r\n THEN DEST[63:0] <- FFFFFFFFFFFFFFFFH;\r\n ELSE DEST[63:0] <- 0; FI;\r\nIF (DEST[127:64] = SRC[127:64])\r\n THEN DEST[127:64] <- FFFFFFFFFFFFFFFFH;\r\n ELSE DEST[127:64] <- 0; FI;\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nCOMPARE_QWORDS_EQUAL (SRC1, SRC2)\r\n IF SRC1[63:0] = SRC2[63:0]\r\n THEN DEST[63:0] <-FFFFFFFFFFFFFFFFH;\r\n ELSE DEST[63:0] <-0; FI;\r\n IF SRC1[127:64] = SRC2[127:64]\r\n THEN DEST[127:64] <-FFFFFFFFFFFFFFFFH;\r\n ELSE DEST[127:64] <-0; FI;\r\n\r\nVPCMPEQQ (VEX.128 encoded version)\r\nDEST[127:0] <-COMPARE_QWORDS_EQUAL(SRC1,SRC2)\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPCMPEQQ (VEX.256 encoded version)\r\nDEST[127:0] <-COMPARE_QWORDS_EQUAL(SRC1[127:0],SRC2[127:0])\r\nDEST[255:128] <-COMPARE_QWORDS_EQUAL(SRC1[255:128],SRC2[255:128])\r\nDEST[VLMAX-1:256] <- 0\r\n\r\nVPCMPEQQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k2[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN CMP <- SRC1[i+63:i] = SRC2[63:0];\r\n ELSE CMP <- SRC1[i+63:i] = SRC2[i+63:i];\r\n FI;\r\n IF CMP = TRUE\r\n THEN DEST[j] <- 1;\r\n ELSE DEST[j] <- 0; FI;\r\n ELSE DEST[j] <- 0 ; zeroing-masking only\r\n FI;\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPCMPEQQ __mmask8 _mm512_cmpeq_epi64_mask( __m512i a, __m512i b);\r\nVPCMPEQQ __mmask8 _mm512_mask_cmpeq_epi64_mask(__mmask8 k, __m512i a, __m512i b);\r\nVPCMPEQQ __mmask8 _mm256_cmpeq_epi64_mask( __m256i a, __m256i b);\r\nVPCMPEQQ __mmask8 _mm256_mask_cmpeq_epi64_mask(__mmask8 k, __m256i a, __m256i b);\r\nVPCMPEQQ __mmask8 _mm_cmpeq_epi64_mask( __m128i a, __m128i b);\r\nVPCMPEQQ __mmask8 _mm_mask_cmpeq_epi64_mask(__mmask8 k, __m128i a, __m128i b);\r\n(V)PCMPEQQ: __m128i _mm_cmpeq_epi64(__m128i a, __m128i b);\r\n\r\n\r\n\r\nVPCMPEQQ: __m256i _mm256_cmpeq_epi64( __m256i a, __m256i b);\r\n\r\nFlags Affected\r\nNone.\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded VPCMPEQQ, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PCMPEQQ"
},
{
"description": "-R:PCMPEQB",
"mnem": "PCMPEQW"
},
{
"description": "PCMPESTRI - Packed Compare Explicit Length Strings, Return Index\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n66 0F 3A 61 /r imm8 RMI V/V SSE4_2 Perform a packed comparison of string data\r\nPCMPESTRI xmm1, xmm2/m128, imm8 with explicit lengths, generating an index, and\r\n storing the result in ECX.\r\nVEX.128.66.0F3A 61 /r ib RMI V/V AVX Perform a packed comparison of string data\r\nVPCMPESTRI xmm1, xmm2/m128, imm8 with explicit lengths, generating an index, and\r\n storing the result in ECX.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (r) ModRM:r/m (r) imm8 NA\r\n\r\n\r\nDescription\r\nThe instruction compares and processes data from two string fragments based on the encoded value in the Imm8\r\nControl Byte (see Section 4.1, \"Imm8 Control Byte Operation for PCMPESTRI / PCMPESTRM / PCMPISTRI / PCMP-\r\nISTRM\"), and generates an index stored to the count register (ECX).\r\nEach string fragment is represented by two values. The first value is an xmm (or possibly m128 for the second\r\noperand) which contains the data elements of the string (byte or word data). The second value is stored in an input\r\nlength register. The input length register is EAX/RAX (for xmm1) or EDX/RDX (for xmm2/m128). The length repre-\r\nsents the number of bytes/words which are valid for the respective xmm/m128 data.\r\nThe length of each input is interpreted as being the absolute-value of the value in the length register. The absolute-\r\nvalue computation saturates to 16 (for bytes) and 8 (for words), based on the value of imm8[bit3] when the value\r\nin the length register is greater than 16 (8) or less than -16 (-8).\r\nThe comparison and aggregation operations are performed according to the encoded value of Imm8 bit fields (see\r\nSection 4.1). The index of the first (or last, according to imm8[6]) set bit of IntRes2 (see Section 4.1.4) is returned\r\nin ECX. If no bits are set in IntRes2, ECX is set to 16 (8).\r\nNote that the Arithmetic Flags are written in a non-standard manner in order to supply the most relevant informa-\r\ntion:\r\n\r\n CFlag - Reset if IntRes2 is equal to zero, set otherwise\r\n ZFlag - Set if absolute-value of EDX is < 16 (8), reset otherwise\r\n SFlag - Set if absolute-value of EAX is < 16 (8), reset otherwise\r\n OFlag - IntRes2[0]\r\n AFlag - Reset\r\n PFlag - Reset\r\n\r\nEffective Operand Size\r\n Operating mode/size Operand 1 Operand 2 Length 1 Length 2 Result\r\n 16 bit xmm xmm/m128 EAX EDX ECX\r\n 32 bit xmm xmm/m128 EAX EDX ECX\r\n 64 bit xmm xmm/m128 EAX EDX ECX\r\n 64 bit + REX.W xmm xmm/m128 RAX RDX ECX\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent For Returning Index\r\nint _mm_cmpestri (__m128i a, int la, __m128i b, int lb, const int mode);\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsics For Reading EFlag Results\r\nint _mm_cmpestra (__m128i a, int la, __m128i b, int lb, const int mode);\r\nint _mm_cmpestrc (__m128i a, int la, __m128i b, int lb, const int mode);\r\nint _mm_cmpestro (__m128i a, int la, __m128i b, int lb, const int mode);\r\nint _mm_cmpestrs (__m128i a, int la, __m128i b, int lb, const int mode);\r\nint _mm_cmpestrz (__m128i a, int la, __m128i b, int lb, const int mode);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4; additionally, this instruction does not cause #GP if the memory operand is not aligned to 16\r\nByte boundary, and\r\n#UD If VEX.L = 1.\r\n If VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PCMPESTRI"
},
{
"description": "PCMPESTRM - Packed Compare Explicit Length Strings, Return Mask\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n66 0F 3A 60 /r imm8 RMI V/V SSE4_2 Perform a packed comparison of string data\r\nPCMPESTRM xmm1, xmm2/m128, imm8 with explicit lengths, generating a mask, and\r\n storing the result in XMM0.\r\nVEX.128.66.0F3A 60 /r ib RMI V/V AVX Perform a packed comparison of string data\r\nVPCMPESTRM xmm1, xmm2/m128, imm8 with explicit lengths, generating a mask, and\r\n storing the result in XMM0.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (r) ModRM:r/m (r) imm8 NA\r\n\r\n\r\nDescription\r\nThe instruction compares data from two string fragments based on the encoded value in the imm8 contol byte (see\r\nSection 4.1, \"Imm8 Control Byte Operation for PCMPESTRI / PCMPESTRM / PCMPISTRI / PCMPISTRM\"), and gener-\r\nates a mask stored to XMM0.\r\nEach string fragment is represented by two values. The first value is an xmm (or possibly m128 for the second\r\noperand) which contains the data elements of the string (byte or word data). The second value is stored in an input\r\nlength register. The input length register is EAX/RAX (for xmm1) or EDX/RDX (for xmm2/m128). The length repre-\r\nsents the number of bytes/words which are valid for the respective xmm/m128 data.\r\nThe length of each input is interpreted as being the absolute-value of the value in the length register. The absolute-\r\nvalue computation saturates to 16 (for bytes) and 8 (for words), based on the value of imm8[bit3] when the value\r\nin the length register is greater than 16 (8) or less than -16 (-8).\r\nThe comparison and aggregation operations are performed according to the encoded value of Imm8 bit fields (see\r\nSection 4.1). As defined by imm8[6], IntRes2 is then either stored to the least significant bits of XMM0 (zero\r\nextended to 128 bits) or expanded into a byte/word-mask and then stored to XMM0.\r\nNote that the Arithmetic Flags are written in a non-standard manner in order to supply the most relevant informa-\r\ntion:\r\n\r\n CFlag - Reset if IntRes2 is equal to zero, set otherwise\r\n ZFlag - Set if absolute-value of EDX is < 16 (8), reset otherwise\r\n SFlag - Set if absolute-value of EAX is < 16 (8), reset otherwise\r\n OFlag -IntRes2[0]\r\n AFlag - Reset\r\n PFlag - Reset\r\n\r\n\r\nNote: In VEX.128 encoded versions, bits (VLMAX-1:128) of XMM0 are zeroed. VEX.vvvv is reserved and must be\r\n1111b, VEX.L must be 0, otherwise the instruction will #UD.\r\n\r\n\r\n\r\n\r\n\r\nEffective Operand Size\r\n\r\n Operating mode/size Operand1 Operand 2 Length1 Length2 Result\r\n 16 bit xmm xmm/m128 EAX EDX XMM0\r\n 32 bit xmm xmm/m128 EAX EDX XMM0\r\n 64 bit xmm xmm/m128 EAX EDX XMM0\r\n 64 bit + REX.W xmm xmm/m128 RAX RDX XMM0\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent For Returning Mask\r\n__m128i _mm_cmpestrm (__m128i a, int la, __m128i b, int lb, const int mode);\r\n\r\nIntel C/C++ Compiler Intrinsics For Reading EFlag Results\r\nint _mm_cmpestra (__m128i a, int la, __m128i b, int lb, const int mode);\r\nint _mm_cmpestrc (__m128i a, int la, __m128i b, int lb, const int mode);\r\nint _mm_cmpestro (__m128i a, int la, __m128i b, int lb, const int mode);\r\nint _mm_cmpestrs (__m128i a, int la, __m128i b, int lb, const int mode);\r\nint _mm_cmpestrz (__m128i a, int la, __m128i b, int lb, const int mode);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4; additionally, this instruction does not cause #GP if the memory operand is not aligned to 16\r\nByte boundary, and\r\n#UD If VEX.L = 1.\r\n If VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PCMPESTRM"
},
{
"description": "PCMPGTB/PCMPGTW/PCMPGTD-Compare Packed Signed Integers for Greater Than\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F 64 /r1 RM V/V MMX Compare packed signed byte integers in mm and\r\nPCMPGTB mm, mm/m64 mm/m64 for greater than.\r\n\r\n66 0F 64 /r RM V/V SSE2 Compare packed signed byte integers in xmm1\r\nPCMPGTB xmm1, xmm2/m128 and xmm2/m128 for greater than.\r\n\r\n0F 65 /r1 RM V/V MMX Compare packed signed word integers in mm and\r\nPCMPGTW mm, mm/m64 mm/m64 for greater than.\r\n\r\n66 0F 65 /r RM V/V SSE2 Compare packed signed word integers in xmm1\r\nPCMPGTW xmm1, xmm2/m128 and xmm2/m128 for greater than.\r\n\r\n0F 66 /r1 RM V/V MMX Compare packed signed doubleword integers in\r\nPCMPGTD mm, mm/m64 mm and mm/m64 for greater than.\r\n\r\n66 0F 66 /r RM V/V SSE2 Compare packed signed doubleword integers in\r\nPCMPGTD xmm1, xmm2/m128 xmm1 and xmm2/m128 for greater than.\r\n\r\nVEX.NDS.128.66.0F.WIG 64 /r RVM V/V AVX Compare packed signed byte integers in xmm2\r\nVPCMPGTB xmm1, xmm2, xmm3/m128 and xmm3/m128 for greater than.\r\n\r\nVEX.NDS.128.66.0F.WIG 65 /r RVM V/V AVX Compare packed signed word integers in xmm2\r\nVPCMPGTW xmm1, xmm2, xmm3/m128 and xmm3/m128 for greater than.\r\n\r\nVEX.NDS.128.66.0F.WIG 66 /r RVM V/V AVX Compare packed signed doubleword integers in\r\nVPCMPGTD xmm1, xmm2, xmm3/m128 xmm2 and xmm3/m128 for greater than.\r\n\r\nVEX.NDS.256.66.0F.WIG 64 /r RVM V/V AVX2 Compare packed signed byte integers in ymm2\r\nVPCMPGTB ymm1, ymm2, ymm3/m256 and ymm3/m256 for greater than.\r\n\r\nVEX.NDS.256.66.0F.WIG 65 /r RVM V/V AVX2 Compare packed signed word integers in ymm2\r\nVPCMPGTW ymm1, ymm2, ymm3/m256 and ymm3/m256 for greater than.\r\nVEX.NDS.256.66.0F.WIG 66 /r RVM V/V AVX2 Compare packed signed doubleword integers in\r\nVPCMPGTD ymm1, ymm2, ymm3/m256 ymm2 and ymm3/m256 for greater than.\r\n\r\nEVEX.NDS.128.66.0F.W0 66 /r FV V/V AVX512VL Compare Greater between int32 vector xmm2 and\r\nVPCMPGTD k1 {k2}, xmm2, AVX512F int32 vector xmm3/m128/m32bcst, and set\r\nxmm3/m128/m32bcst vector mask k1 to reflect the zero/nonzero status\r\n of each element of the result, under writemask.\r\nEVEX.NDS.256.66.0F.W0 66 /r FV V/V AVX512VL Compare Greater between int32 vector ymm2 and\r\nVPCMPGTD k1 {k2}, ymm2, AVX512F int32 vector ymm3/m256/m32bcst, and set\r\nymm3/m256/m32bcst vector mask k1 to reflect the zero/nonzero status\r\n of each element of the result, under writemask.\r\nEVEX.NDS.512.66.0F.W0 66 /r FV V/V AVX512F Compare Greater between int32 elements in\r\nVPCMPGTD k1 {k2}, zmm2, zmm2 and zmm3/m512/m32bcst, and set\r\nzmm3/m512/m32bcst destination k1 according to the comparison results\r\n under writemask. k2.\r\nEVEX.NDS.128.66.0F.WIG 64 /r FVM V/V AVX512VL Compare packed signed byte integers in xmm2\r\nVPCMPGTB k1 {k2}, xmm2, xmm3/m128 AVX512BW and xmm3/m128 for greater than, and set vector\r\n mask k1 to reflect the zero/nonzero status of each\r\n element of the result, under writemask.\r\nEVEX.NDS.256.66.0F.WIG 64 /r FVM V/V AVX512VL Compare packed signed byte integers in ymm2\r\nVPCMPGTB k1 {k2}, ymm2, ymm3/m256 AVX512BW and ymm3/m256 for greater than, and set vector\r\n mask k1 to reflect the zero/nonzero status of each\r\n element of the result, under writemask.\r\n\r\n\r\n\r\n\r\nEVEX.NDS.512.66.0F.WIG 64 /r FVM V/V AVX512BW Compare packed signed byte integers in zmm2 and\r\nVPCMPGTB k1 {k2}, zmm2, zmm3/m512 zmm3/m512 for greater than, and set vector\r\n mask k1 to reflect the zero/nonzero status of each\r\n element of the result, under writemask.\r\nEVEX.NDS.128.66.0F.WIG 65 /r FVM V/V AVX512VL Compare packed signed word integers in xmm2\r\nVPCMPGTW k1 {k2}, xmm2, xmm3/m128 AVX512BW and xmm3/m128 for greater than, and set vector\r\n mask k1 to reflect the zero/nonzero status of each\r\n element of the result, under writemask.\r\nEVEX.NDS.256.66.0F.WIG 65 /r FVM V/V AVX512VL Compare packed signed word integers in ymm2\r\nVPCMPGTW k1 {k2}, ymm2, ymm3/m256 AVX512BW and ymm3/m256 for greater than, and set vector\r\n mask k1 to reflect the zero/nonzero status of each\r\n element of the result, under writemask.\r\nEVEX.NDS.512.66.0F.WIG 65 /r FVM V/V AVX512BW Compare packed signed word integers in zmm2\r\nVPCMPGTW k1 {k2}, zmm2, zmm3/m512 and zmm3/m512 for greater than, and set vector\r\n mask k1 to reflect the zero/nonzero status of each\r\n element of the result, under writemask.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nPerforms an SIMD signed compare for the greater value of the packed byte, word, or doubleword integers in the\r\ndestination operand (first operand) and the source operand (second operand). If a data element in the destination\r\noperand is greater than the corresponding date element in the source operand, the corresponding data element in\r\nthe destination operand is set to all 1s; otherwise, it is set to all 0s.\r\nThe PCMPGTB instruction compares the corresponding signed byte integers in the destination and source oper-\r\nands; the PCMPGTW instruction compares the corresponding signed word integers in the destination and source\r\noperands; and the PCMPGTD instruction compares the corresponding signed doubleword integers in the destina-\r\ntion and source operands.\r\nIn 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to\r\naccess additional registers (XMM8-XMM15).\r\nLegacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The\r\ndestination operand can be an MMX technology register.\r\n128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The\r\nfirst source operand and destination operand are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM\r\ndestination register remain unchanged.\r\nVEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The\r\nfirst source operand and destination operand are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM\r\nregister are zeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register\r\nor a 256-bit memory location. The destination operand is a YMM register.\r\n\r\n\r\n\r\n\r\nEVEX encoded VPCMPGTD: The first source operand (second operand) is a ZMM/YMM/XMM register. The second\r\nsource operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector\r\nbroadcasted from a 32-bit memory location. The destination operand (first operand) is a mask register updated\r\naccording to the writemask k2.\r\nEVEX encoded VPCMPGTB/W: The first source operand (second operand) is a ZMM/YMM/XMM register. The second\r\nsource operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand\r\n(first operand) is a mask register updated according to the writemask k2.\r\n\r\nOperation\r\nPCMPGTB (with 64-bit operands)\r\n IF DEST[7:0] > SRC[7:0]\r\n THEN DEST[7:0) <- FFH;\r\n ELSE DEST[7:0] <- 0; FI;\r\n (* Continue comparison of 2nd through 7th bytes in DEST and SRC *)\r\n IF DEST[63:56] > SRC[63:56]\r\n THEN DEST[63:56] <- FFH;\r\n ELSE DEST[63:56] <- 0; FI;\r\n\r\nCOMPARE_BYTES_GREATER (SRC1, SRC2)\r\n IF SRC1[7:0] > SRC2[7:0]\r\n THEN DEST[7:0] <-FFH;\r\n ELSE DEST[7:0] <-0; FI;\r\n(* Continue comparison of 2nd through 15th bytes in SRC1 and SRC2 *)\r\n IF SRC1[127:120] > SRC2[127:120]\r\n THEN DEST[127:120] <-FFH;\r\n ELSE DEST[127:120] <-0; FI;\r\n\r\nCOMPARE_WORDS_GREATER (SRC1, SRC2)\r\n IF SRC1[15:0] > SRC2[15:0]\r\n THEN DEST[15:0] <-FFFFH;\r\n ELSE DEST[15:0] <-0; FI;\r\n(* Continue comparison of 2nd through 7th 16-bit words in SRC1 and SRC2 *)\r\n IF SRC1[127:112] > SRC2[127:112]\r\n THEN DEST[127:112] <-FFFFH;\r\n ELSE DEST[127:112] <-0; FI;\r\n\r\nCOMPARE_DWORDS_GREATER (SRC1, SRC2)\r\n IF SRC1[31:0] > SRC2[31:0]\r\n THEN DEST[31:0] <-FFFFFFFFH;\r\n ELSE DEST[31:0] <-0; FI;\r\n(* Continue comparison of 2nd through 3rd 32-bit dwords in SRC1 and SRC2 *)\r\n IF SRC1[127:96] > SRC2[127:96]\r\n THEN DEST[127:96] <-FFFFFFFFH;\r\n ELSE DEST[127:96] <-0; FI;\r\n\r\n\r\nPCMPGTB (with 128-bit operands)\r\nDEST[127:0] <-COMPARE_BYTES_GREATER(DEST[127:0],SRC[127:0])\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVPCMPGTB (VEX.128 encoded version)\r\nDEST[127:0] <-COMPARE_BYTES_GREATER(SRC1,SRC2)\r\nDEST[VLMAX-1:128] <- 0\r\n\r\n\r\n\r\n\r\nVPCMPGTB (VEX.256 encoded version)\r\nDEST[127:0] <-COMPARE_BYTES_GREATER(SRC1[127:0],SRC2[127:0])\r\nDEST[255:128] <-COMPARE_BYTES_GREATER(SRC1[255:128],SRC2[255:128])\r\nDEST[VLMAX-1:256] <- 0\r\n\r\nVPCMPGTB (EVEX encoded versions)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\nFOR j <- 0 TO KL-1\r\n i<-j*8\r\n IF k2[j] OR *no writemask*\r\n THEN\r\n /* signed comparison */\r\n CMP <- SRC1[i+7:i] > SRC2[i+7:i];\r\n IF CMP = TRUE\r\n THEN DEST[j] <- 1;\r\n ELSE DEST[j] <- 0; FI;\r\n ELSE DEST[j] <- 0 ; zeroing-masking onlyFI;\r\n FI;\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\n\r\nPCMPGTW (with 64-bit operands)\r\n IF DEST[15:0] > SRC[15:0]\r\n THEN DEST[15:0] <- FFFFH;\r\n ELSE DEST[15:0] <- 0; FI;\r\n (* Continue comparison of 2nd and 3rd words in DEST and SRC *)\r\n IF DEST[63:48] > SRC[63:48]\r\n THEN DEST[63:48] <- FFFFH;\r\n ELSE DEST[63:48] <- 0; FI;\r\n\r\nPCMPGTW (with 128-bit operands)\r\nDEST[127:0] <-COMPARE_WORDS_GREATER(DEST[127:0],SRC[127:0])\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVPCMPGTW (VEX.128 encoded version)\r\nDEST[127:0] <-COMPARE_WORDS_GREATER(SRC1,SRC2)\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPCMPGTW (VEX.256 encoded version)\r\nDEST[127:0] <-COMPARE_WORDS_GREATER(SRC1[127:0],SRC2[127:0])\r\nDEST[255:128] <-COMPARE_WORDS_GREATER(SRC1[255:128],SRC2[255:128])\r\nDEST[VLMAX-1:256] <- 0\r\n\r\nVPCMPGTW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k2[j] OR *no writemask*\r\n THEN\r\n /* signed comparison */\r\n CMP <- SRC1[i+15:i] > SRC2[i+15:i];\r\n IF CMP = TRUE\r\n THEN DEST[j] <- 1;\r\n ELSE DEST[j] <- 0; FI;\r\n\r\n\r\n\r\n ELSE DEST[j] <- 0 ; zeroing-masking onlyFI;\r\n FI;\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\n\r\nPCMPGTD (with 64-bit operands)\r\n IF DEST[31:0] > SRC[31:0]\r\n THEN DEST[31:0] <- FFFFFFFFH;\r\n ELSE DEST[31:0] <- 0; FI;\r\n IF DEST[63:32] > SRC[63:32]\r\n THEN DEST[63:32] <- FFFFFFFFH;\r\n ELSE DEST[63:32] <- 0; FI;\r\n\r\nPCMPGTD (with 128-bit operands)\r\nDEST[127:0] <-COMPARE_DWORDS_GREATER(DEST[127:0],SRC[127:0])\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVPCMPGTD (VEX.128 encoded version)\r\nDEST[127:0] <-COMPARE_DWORDS_GREATER(SRC1,SRC2)\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPCMPGTD (VEX.256 encoded version)\r\nDEST[127:0] <-COMPARE_DWORDS_GREATER(SRC1[127:0],SRC2[127:0])\r\nDEST[255:128] <-COMPARE_DWORDS_GREATER(SRC1[255:128],SRC2[255:128])\r\nDEST[VLMAX-1:256] <- 0\r\n\r\nVPCMPGTD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k2[j] OR *no writemask*\r\n THEN\r\n /* signed comparison */\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN CMP <- SRC1[i+31:i] > SRC2[31:0];\r\n ELSE CMP <- SRC1[i+31:i] > SRC2[i+31:i];\r\n FI;\r\n IF CMP = TRUE\r\n THEN DEST[j] <- 1;\r\n ELSE DEST[j] <- 0; FI;\r\n ELSE DEST[j] <- 0 ; zeroing-masking only\r\n FI;\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPCMPGTB __mmask64 _mm512_cmpgt_epi8_mask(__m512i a, __m512i b);\r\nVPCMPGTB __mmask64 _mm512_mask_cmpgt_epi8_mask(__mmask64 k, __m512i a, __m512i b);\r\nVPCMPGTB __mmask32 _mm256_cmpgt_epi8_mask(__m256i a, __m256i b);\r\nVPCMPGTB __mmask32 _mm256_mask_cmpgt_epi8_mask(__mmask32 k, __m256i a, __m256i b);\r\nVPCMPGTB __mmask16 _mm_cmpgt_epi8_mask(__m128i a, __m128i b);\r\nVPCMPGTB __mmask16 _mm_mask_cmpgt_epi8_mask(__mmask16 k, __m128i a, __m128i b);\r\nVPCMPGTD __mmask16 _mm512_cmpgt_epi32_mask(__m512i a, __m512i b);\r\n\r\n\r\n\r\n\r\nVPCMPGTD __mmask16 _mm512_mask_cmpgt_epi32_mask(__mmask16 k, __m512i a, __m512i b);\r\nVPCMPGTD __mmask8 _mm256_cmpgt_epi32_mask(__m256i a, __m256i b);\r\nVPCMPGTD __mmask8 _mm256_mask_cmpgt_epi32_mask(__mmask8 k, __m256i a, __m256i b);\r\nVPCMPGTD __mmask8 _mm_cmpgt_epi32_mask(__m128i a, __m128i b);\r\nVPCMPGTD __mmask8 _mm_mask_cmpgt_epi32_mask(__mmask8 k, __m128i a, __m128i b);\r\nVPCMPGTW __mmask32 _mm512_cmpgt_epi16_mask(__m512i a, __m512i b);\r\nVPCMPGTW __mmask32 _mm512_mask_cmpgt_epi16_mask(__mmask32 k, __m512i a, __m512i b);\r\nVPCMPGTW __mmask16 _mm256_cmpgt_epi16_mask(__m256i a, __m256i b);\r\nVPCMPGTW __mmask16 _mm256_mask_cmpgt_epi16_mask(__mmask16 k, __m256i a, __m256i b);\r\nVPCMPGTW __mmask8 _mm_cmpgt_epi16_mask(__m128i a, __m128i b);\r\nVPCMPGTW __mmask8 _mm_mask_cmpgt_epi16_mask(__mmask8 k, __m128i a, __m128i b);\r\nPCMPGTB:__m64 _mm_cmpgt_pi8 (__m64 m1, __m64 m2)\r\nPCMPGTW:__m64 _mm_pcmpgt_pi16 (__m64 m1, __m64 m2)\r\nPCMPGTD:__m64 _mm_pcmpgt_pi32 (__m64 m1, __m64 m2)\r\n(V)PCMPGTB:__m128i _mm_cmpgt_epi8 ( __m128i a, __m128i b)\r\n(V)PCMPGTW:__m128i _mm_cmpgt_epi16 ( __m128i a, __m128i b)\r\n(V)DCMPGTD:__m128i _mm_cmpgt_epi32 ( __m128i a, __m128i b)\r\nVPCMPGTB: __m256i _mm256_cmpgt_epi8 ( __m256i a, __m256i b)\r\nVPCMPGTW: __m256i _mm256_cmpgt_epi16 ( __m256i a, __m256i b)\r\nVPCMPGTD: __m256i _mm256_cmpgt_epi32 ( __m256i a, __m256i b)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nNumeric Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded VPCMPGTD, see Exceptions Type E4.\r\nEVEX-encoded VPCMPGTB/W, see Exceptions Type E4.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PCMPGTB"
},
{
"description": "-R:PCMPGTB",
"mnem": "PCMPGTD"
},
{
"description": "PCMPGTQ - Compare Packed Data for Greater Than\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n66 0F 38 37 /r RM V/V SSE4_2 Compare packed signed qwords in xmm2/m128\r\nPCMPGTQ xmm1,xmm2/m128 and xmm1 for greater than.\r\nVEX.NDS.128.66.0F38.WIG 37 /r RVM V/V AVX Compare packed signed qwords in xmm2 and\r\nVPCMPGTQ xmm1, xmm2, xmm3/m128 xmm3/m128 for greater than.\r\nVEX.NDS.256.66.0F38.WIG 37 /r RVM V/V AVX2 Compare packed signed qwords in ymm2 and\r\nVPCMPGTQ ymm1, ymm2, ymm3/m256 ymm3/m256 for greater than.\r\nEVEX.NDS.128.66.0F38.W1 37 /r FV V/V AVX512VL Compare Greater between int64 vector xmm2 and\r\nVPCMPGTQ k1 {k2}, xmm2, AVX512F int64 vector xmm3/m128/m64bcst, and set\r\nxmm3/m128/m64bcst vector mask k1 to reflect the zero/nonzero status\r\n of each element of the result, under writemask.\r\nEVEX.NDS.256.66.0F38.W1 37 /r FV V/V AVX512VL Compare Greater between int64 vector ymm2 and\r\nVPCMPGTQ k1 {k2}, ymm2, AVX512F int64 vector ymm3/m256/m64bcst, and set\r\nymm3/m256/m64bcst vector mask k1 to reflect the zero/nonzero status\r\n of each element of the result, under writemask.\r\nEVEX.NDS.512.66.0F38.W1 37 /r FV V/V AVX512F Compare Greater between int64 vector zmm2 and\r\nVPCMPGTQ k1 {k2}, zmm2, zmm3/m512/m64bcst int64 vector zmm3/m512/m64bcst, and set\r\n vector mask k1 to reflect the zero/nonzero status\r\n of each element of the result, under writemask.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nPerforms an SIMD signed compare for the packed quadwords in the destination operand (first operand) and the\r\nsource operand (second operand). If the data element in the first (destination) operand is greater than the\r\ncorresponding element in the second (source) operand, the corresponding data element in the destination is set\r\nto all 1s; otherwise, it is set to 0s.\r\n128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The\r\nfirst source operand and destination operand are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM\r\ndestination register remain unchanged.\r\nVEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The\r\nfirst source operand and destination operand are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM\r\nregister are zeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register\r\nor a 256-bit memory location. The destination operand is a YMM register.\r\nEVEX encoded VPCMPGTD/Q: The first source operand (second operand) is a ZMM/YMM/XMM register. The second\r\nsource operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector\r\nbroadcasted from a 64-bit memory location. The destination operand (first operand) is a mask register updated\r\naccording to the writemask k2.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nCOMPARE_QWORDS_GREATER (SRC1, SRC2)\r\n IF SRC1[63:0] > SRC2[63:0]\r\n THEN DEST[63:0] <-FFFFFFFFFFFFFFFFH;\r\n ELSE DEST[63:0] <-0; FI;\r\n IF SRC1[127:64] > SRC2[127:64]\r\n THEN DEST[127:64] <-FFFFFFFFFFFFFFFFH;\r\n ELSE DEST[127:64] <-0; FI;\r\n\r\nVPCMPGTQ (VEX.128 encoded version)\r\nDEST[127:0] <-COMPARE_QWORDS_GREATER(SRC1,SRC2)\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPCMPGTQ (VEX.256 encoded version)\r\nDEST[127:0] <-COMPARE_QWORDS_GREATER(SRC1[127:0],SRC2[127:0])\r\nDEST[255:128] <-COMPARE_QWORDS_GREATER(SRC1[255:128],SRC2[255:128])\r\nDEST[VLMAX-1:256] <- 0\r\n\r\nVPCMPGTQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k2[j] OR *no writemask*\r\n THEN\r\n /* signed comparison */\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN CMP <- SRC1[i+63:i] > SRC2[63:0];\r\n ELSE CMP <- SRC1[i+63:i] > SRC2[i+63:i];\r\n FI;\r\n IF CMP = TRUE\r\n THEN DEST[j] <- 1;\r\n ELSE DEST[j] <- 0; FI;\r\n ELSE DEST[j] <- 0 ; zeroing-masking only\r\n FI;\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPCMPGTQ __mmask8 _mm512_cmpgt_epi64_mask( __m512i a, __m512i b);\r\nVPCMPGTQ __mmask8 _mm512_mask_cmpgt_epi64_mask(__mmask8 k, __m512i a, __m512i b);\r\nVPCMPGTQ __mmask8 _mm256_cmpgt_epi64_mask( __m256i a, __m256i b);\r\nVPCMPGTQ __mmask8 _mm256_mask_cmpgt_epi64_mask(__mmask8 k, __m256i a, __m256i b);\r\nVPCMPGTQ __mmask8 _mm_cmpgt_epi64_mask( __m128i a, __m128i b);\r\nVPCMPGTQ __mmask8 _mm_mask_cmpgt_epi64_mask(__mmask8 k, __m128i a, __m128i b);\r\n(V)PCMPGTQ: __m128i _mm_cmpgt_epi64(__m128i a, __m128i b)\r\nVPCMPGTQ: __m256i _mm256_cmpgt_epi64( __m256i a, __m256i b);\r\n\r\nFlags Affected\r\nNone.\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\n\r\n\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded VPCMPGTQ, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PCMPGTQ"
},
{
"description": "-R:PCMPGTB",
"mnem": "PCMPGTW"
},
{
"description": "PCMPISTRI - Packed Compare Implicit Length Strings, Return Index\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n66 0F 3A 63 /r imm8 RM V/V SSE4_2 Perform a packed comparison of string data\r\nPCMPISTRI xmm1, xmm2/m128, imm8 with implicit lengths, generating an index, and\r\n storing the result in ECX.\r\nVEX.128.66.0F3A.WIG 63 /r ib RM V/V AVX Perform a packed comparison of string data\r\nVPCMPISTRI xmm1, xmm2/m128, imm8 with implicit lengths, generating an index, and\r\n storing the result in ECX.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r) ModRM:r/m (r) imm8 NA\r\n\r\n\r\nDescription\r\nThe instruction compares data from two strings based on the encoded value in the Imm8 Control Byte (see Section\r\n4.1, \"Imm8 Control Byte Operation for PCMPESTRI / PCMPESTRM / PCMPISTRI / PCMPISTRM\"), and generates an\r\nindex stored to ECX.\r\nEach string is represented by a single value. The value is an xmm (or possibly m128 for the second operand) which\r\ncontains the data elements of the string (byte or word data). Each input byte/word is augmented with a\r\nvalid/invalid tag. A byte/word is considered valid only if it has a lower index than the least significant null\r\nbyte/word. (The least significant null byte/word is also considered invalid.)\r\nThe comparison and aggregation operations are performed according to the encoded value of Imm8 bit fields (see\r\nSection 4.1). The index of the first (or last, according to imm8[6]) set bit of IntRes2 is returned in ECX. If no bits\r\nare set in IntRes2, ECX is set to 16 (8).\r\nNote that the Arithmetic Flags are written in a non-standard manner in order to supply the most relevant informa-\r\ntion:\r\n\r\n CFlag - Reset if IntRes2 is equal to zero, set otherwise\r\n ZFlag - Set if any byte/word of xmm2/mem128 is null, reset otherwise\r\n SFlag - Set if any byte/word of xmm1 is null, reset otherwise\r\n OFlag -IntRes2[0]\r\n AFlag - Reset\r\n PFlag - Reset\r\nNote: In VEX.128 encoded version, VEX.vvvv is reserved and must be 1111b, VEX.L must be 0, otherwise the\r\ninstruction will #UD.\r\n\r\nEffective Operand Size\r\n\r\n Operating mode/size Operand1 Operand 2 Result\r\n\r\n 16 bit xmm xmm/m128 ECX\r\n\r\n 32 bit xmm xmm/m128 ECX\r\n\r\n 64 bit xmm xmm/m128 ECX\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent For Returning Index\r\nint _mm_cmpistri (__m128i a, __m128i b, const int mode);\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsics For Reading EFlag Results\r\nint _mm_cmpistra (__m128i a, __m128i b, const int mode);\r\nint _mm_cmpistrc (__m128i a, __m128i b, const int mode);\r\nint _mm_cmpistro (__m128i a, __m128i b, const int mode);\r\nint _mm_cmpistrs (__m128i a, __m128i b, const int mode);\r\nint _mm_cmpistrz (__m128i a, __m128i b, const int mode);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4; additionally, this instruction does not cause #GP if the memory operand is not aligned to\r\n16 Byte boundary, and\r\n#UD If VEX.L = 1.\r\n If VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PCMPISTRI"
},
{
"description": "PCMPISTRM - Packed Compare Implicit Length Strings, Return Mask\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n66 0F 3A 62 /r imm8 RM V/V SSE4_2 Perform a packed comparison of string data\r\nPCMPISTRM xmm1, xmm2/m128, imm8 with implicit lengths, generating a mask, and\r\n storing the result in XMM0.\r\nVEX.128.66.0F3A.WIG 62 /r ib RM V/V AVX Perform a packed comparison of string data\r\nVPCMPISTRM xmm1, xmm2/m128, imm8 with implicit lengths, generating a Mask, and\r\n storing the result in XMM0.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r) ModRM:r/m (r) imm8 NA\r\n\r\n\r\nDescription\r\nThe instruction compares data from two strings based on the encoded value in the imm8 byte (see Section 4.1,\r\n\"Imm8 Control Byte Operation for PCMPESTRI / PCMPESTRM / PCMPISTRI / PCMPISTRM\") generating a mask\r\nstored to XMM0.\r\nEach string is represented by a single value. The value is an xmm (or possibly m128 for the second operand) which\r\ncontains the data elements of the string (byte or word data). Each input byte/word is augmented with a\r\nvalid/invalid tag. A byte/word is considered valid only if it has a lower index than the least significant null\r\nbyte/word. (The least significant null byte/word is also considered invalid.)\r\nThe comparison and aggregation operation are performed according to the encoded value of Imm8 bit fields (see\r\nSection 4.1). As defined by imm8[6], IntRes2 is then either stored to the least significant bits of XMM0 (zero\r\nextended to 128 bits) or expanded into a byte/word-mask and then stored to XMM0.\r\nNote that the Arithmetic Flags are written in a non-standard manner in order to supply the most relevant informa-\r\ntion:\r\n\r\n CFlag - Reset if IntRes2 is equal to zero, set otherwise\r\n ZFlag - Set if any byte/word of xmm2/mem128 is null, reset otherwise\r\n SFlag - Set if any byte/word of xmm1 is null, reset otherwise\r\n OFlag - IntRes2[0]\r\n AFlag - Reset\r\n PFlag - Reset\r\nNote: In VEX.128 encoded versions, bits (VLMAX-1:128) of XMM0 are zeroed. VEX.vvvv is reserved and must be\r\n1111b, VEX.L must be 0, otherwise the instruction will #UD.\r\n\r\nEffective Operand Size\r\n\r\n Operating mode/size Operand1 Operand 2 Result\r\n 16 bit xmm xmm/m128 XMM0\r\n 32 bit xmm xmm/m128 XMM0\r\n 64 bit xmm xmm/m128 XMM0\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent For Returning Mask\r\n__m128i _mm_cmpistrm (__m128i a, __m128i b, const int mode);\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsics For Reading EFlag Results\r\nint _mm_cmpistra (__m128i a, __m128i b, const int mode);\r\nint _mm_cmpistrc (__m128i a, __m128i b, const int mode);\r\nint _mm_cmpistro (__m128i a, __m128i b, const int mode);\r\nint _mm_cmpistrs (__m128i a, __m128i b, const int mode);\r\nint _mm_cmpistrz (__m128i a, __m128i b, const int mode);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4; additionally, this instruction does not cause #GP if the memory operand is not aligned to\r\n16 Byte boundary, and\r\n#UD If VEX.L = 1.\r\n If VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PCMPISTRM"
},
{
"description": "PDEP - Parallel Bits Deposit\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En -bit Feature\r\n Mode Flag\r\n VEX.NDS.LZ.F2.0F38.W0 F5 /r RVM V/V BMI2 Parallel deposit of bits from r32b using mask in r/m32, result is writ-\r\n PDEP r32a, r32b, r/m32 ten to r32a.\r\n VEX.NDS.LZ.F2.0F38.W1 F5 /r RVM V/N.E. BMI2 Parallel deposit of bits from r64b using mask in r/m64, result is writ-\r\n PDEP r64a, r64b, r/m64 ten to r64a.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nPDEP uses a mask in the second source operand (the third operand) to transfer/scatter contiguous low order bits\r\nin the first source operand (the second operand) into the destination (the first operand). PDEP takes the low bits\r\nfrom the first source operand and deposit them in the destination operand at the corresponding bit locations that\r\nare set in the second source operand (mask). All other bits (bits not set in mask) in destination are set to zero.\r\n\r\n\r\n\r\n SRC1 S31 S30 S29 S28 S27 S7 S6 S5 S4 S3 S2 S1 S0\r\n\r\n\r\n\r\n SRC2 0 0 0 1 0 1 0 1 0 0 1 0 0\r\n (mask)\r\n\r\n\r\n DEST 0 0 0 S3 0 S2 0 S1 0 0 S0 0 0\r\n\r\n bit 31 bit 0\r\n\r\n\r\n Figure 4-8. PDEP Example\r\n\r\nThis instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in\r\n64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An\r\nattempt to execute this instruction with VEX.L not equal to 0 will cause #UD.\r\n\r\nOperation\r\nTEMP <- SRC1;\r\nMASK <- SRC2;\r\nDEST <- 0 ;\r\nm<- 0, k<- 0;\r\nDO WHILE m< OperandSize\r\n\r\n IF MASK[ m] = 1 THEN\r\n DEST[ m] <- TEMP[ k];\r\n k <- k+ 1;\r\n FI\r\n m <- m+ 1;\r\nOD\r\n\r\n\r\n\r\n\r\nFlags Affected\r\nNone.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nPDEP: unsigned __int32 _pdep_u32(unsigned __int32 src, unsigned __int32 mask);\r\nPDEP: unsigned __int64 _pdep_u64(unsigned __int64 src, unsigned __int32 mask);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Section 2.5.1, \"Exception Conditions for VEX-Encoded GPR Instructions\", Table 2-29; additionally\r\n#UD If VEX.W = 1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PDEP"
},
{
"description": "PEXT - Parallel Bits Extract\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En -bit Feature\r\n Mode Flag\r\n VEX.NDS.LZ.F3.0F38.W0 F5 /r RVM V/V BMI2 Parallel extract of bits from r32b using mask in r/m32, result is writ-\r\n PEXT r32a, r32b, r/m32 ten to r32a.\r\n VEX.NDS.LZ.F3.0F38.W1 F5 /r RVM V/N.E. BMI2 Parallel extract of bits from r64b using mask in r/m64, result is writ-\r\n PEXT r64a, r64b, r/m64 ten to r64a.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nPEXT uses a mask in the second source operand (the third operand) to transfer either contiguous or non-contig-\r\nuous bits in the first source operand (the second operand) to contiguous low order bit positions in the destination\r\n(the first operand). For each bit set in the MASK, PEXT extracts the corresponding bits from the first source operand\r\nand writes them into contiguous lower bits of destination operand. The remaining upper bits of destination are\r\nzeroed.\r\n\r\n\r\n\r\n SRC1 S S\r\n 31 30 S29 S28 S27 S7 S6 S5 S4 S3 S2 S1 S0\r\n\r\n\r\n\r\n SRC2 0\r\n 0 0 0 1 0 1 0 1 0 1 0 0\r\n (mask)\r\n\r\n\r\n\r\n\r\n DEST 0 0 0 0 0 0 0 0 0 S28 S7 S5 S2\r\n\r\n bit 31 bit 0\r\n\r\n\r\n Figure 4-9. PEXT Example\r\n\r\nThis instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in\r\n64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An\r\nattempt to execute this instruction with VEX.L not equal to 0 will cause #UD.\r\n\r\nOperation\r\nTEMP <- SRC1;\r\nMASK <- SRC2;\r\nDEST <- 0 ;\r\nm<- 0, k<- 0;\r\nDO WHILE m< OperandSize\r\n\r\n IF MASK[ m] = 1 THEN\r\n DEST[ k] <- TEMP[ m];\r\n k <- k+ 1;\r\n FI\r\n\r\n\r\n\r\n m <- m+ 1;\r\n\r\nOD\r\n\r\nFlags Affected\r\nNone.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nPEXT: unsigned __int32 _pext_u32(unsigned __int32 src, unsigned __int32 mask);\r\nPEXT: unsigned __int64 _pext_u64(unsigned __int64 src, unsigned __int32 mask);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Section 2.5.1, \"Exception Conditions for VEX-Encoded GPR Instructions\", Table 2-29; additionally\r\n#UD If VEX.W = 1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PEXT"
},
{
"description": "PEXTRB/PEXTRD/PEXTRQ - Extract Byte/Dword/Qword\r\nOpcode/ Op/ En 64/32 bit CPUID Description\r\nInstruction Mode Feature\r\n Support Flag\r\n66 0F 3A 14 MRI V/V SSE4_1 Extract a byte integer value from xmm2 at the\r\n/r ib source byte offset specified by imm8 into reg or\r\nPEXTRB reg/m8, xmm2, imm8 m8. The upper bits of r32 or r64 are zeroed.\r\n66 0F 3A 16 MRI V/V SSE4_1 Extract a dword integer value from xmm2 at the\r\n/r ib source dword offset specified by imm8 into r/m32.\r\nPEXTRD r/m32, xmm2, imm8\r\n66 REX.W 0F 3A 16 MRI V/N.E. SSE4_1 Extract a qword integer value from xmm2 at the\r\n/r ib source qword offset specified by imm8 into r/m64.\r\nPEXTRQ r/m64, xmm2, imm8\r\n\r\nVEX.128.66.0F3A.W0 14 /r ib MRI V1/V AVX Extract a byte integer value from xmm2 at the\r\nVPEXTRB reg/m8, xmm2, imm8 source byte offset specified by imm8 into reg or\r\n m8. The upper bits of r64/r32 is filled with zeros.\r\nVEX.128.66.0F3A.W0 16 /r ib MRI V/V AVX Extract a dword integer value from xmm2 at the\r\nVPEXTRD r32/m32, xmm2, imm8 source dword offset specified by imm8 into\r\n r32/m32.\r\nVEX.128.66.0F3A.W1 16 /r ib MRI V/i AVX Extract a qword integer value from xmm2 at the\r\nVPEXTRQ r64/m64, xmm2, imm8 source dword offset specified by imm8 into\r\n r64/m64.\r\nEVEX.128.66.0F3A.WIG 14 /r ib T1S-MRI V/V AVX512BW Extract a byte integer value from xmm2 at the\r\nVPEXTRB reg/m8, xmm2, imm8 source byte offset specified by imm8 into reg or\r\n m8. The upper bits of r64/r32 is filled with zeros.\r\nEVEX.128.66.0F3A.W0 16 /r ib T1S-MRI V/V AVX512DQ Extract a dword integer value from xmm2 at the\r\nVPEXTRD r32/m32, xmm2, imm8 source dword offset specified by imm8 into\r\n r32/m32.\r\nEVEX.128.66.0F3A.W1 16 /r ib T1S-MRI V/N.E.1 AVX512DQ Extract a qword integer value from xmm2 at the\r\nVPEXTRQ r64/m64, xmm2, imm8 source dword offset specified by imm8 into\r\n r64/m64.\r\n\r\n\r\nNOTES:\r\n1. In 64-bit mode, VEX.W1 is ignored for VPEXTRB (similar to legacy REX.W=1 prefix in PEXTRB).\r\n2. VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is used.\r\n\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n MRI ModRM:r/m (w) ModRM:reg (r) imm8 NA\r\n\r\n\r\nDescription\r\nExtract a byte/dword/qword integer value from the source XMM register at a byte/dword/qword offset determined\r\nfrom imm8[3:0]. The destination can be a register or byte/dword/qword memory location. If the destination is a\r\nregister, the upper bits of the register are zero extended.\r\nIn legacy non-VEX encoded version and if the destination operand is a register, the default operand size in 64-bit\r\nmode for PEXTRB/PEXTRD is 64 bits, the bits above the least significant byte/dword data are filled with zeros.\r\nPEXTRQ is not encodable in non-64-bit modes and requires REX.W in 64-bit mode.\r\n\r\n\r\n\r\n\r\nNote: In VEX.128 encoded versions, VEX.vvvv is reserved and must be 1111b, VEX.L must be 0, otherwise the\r\ninstruction will #UD. In EVEX.128 encoded versions, EVEX.vvvv is reserved and must be 1111b, EVEX.L\"L must be\r\n0, otherwise the instruction will #UD. If the destination operand is a register, the default operand size in 64-bit\r\nmode for VPEXTRB/VPEXTRD is 64 bits, the bits above the least significant byte/word/dword data are filled with\r\nzeros. Attempt to execute VPEXTRQ in non-64-bit mode will cause #UD.\r\n\r\nOperation\r\nCASE of\r\n PEXTRB: SEL <- COUNT[3:0];\r\n TEMP <- (Src >> SEL*8) AND FFH;\r\n IF (DEST = Mem8)\r\n THEN\r\n Mem8 <- TEMP[7:0];\r\n ELSE IF (64-Bit Mode and 64-bit register selected)\r\n THEN\r\n R64[7:0] <- TEMP[7:0];\r\n r64[63:8] <- ZERO_FILL; };\r\n ELSE\r\n R32[7:0] <- TEMP[7:0];\r\n r32[31:8] <- ZERO_FILL; };\r\n FI;\r\n PEXTRD:SEL <- COUNT[1:0];\r\n TEMP <- (Src >> SEL*32) AND FFFF_FFFFH;\r\n DEST <- TEMP;\r\n PEXTRQ: SEL <- COUNT[0];\r\n TEMP <- (Src >> SEL*64);\r\n DEST <- TEMP;\r\nEASC:\r\n\r\nVPEXTRTD/VPEXTRQ\r\nIF (64-Bit Mode and 64-bit dest operand)\r\nTHEN\r\n Src_Offset <- Imm8[0]\r\n r64/m64 <-(Src >> Src_Offset * 64)\r\nELSE\r\n Src_Offset <- Imm8[1:0]\r\n r32/m32 <- ((Src >> Src_Offset *32) AND 0FFFFFFFFh);\r\nFI\r\n\r\nVPEXTRB ( dest=m8)\r\nSRC_Offset <- Imm8[3:0]\r\nMem8 <- (Src >> Src_Offset*8)\r\n\r\nVPEXTRB ( dest=reg)\r\nIF (64-Bit Mode )\r\nTHEN\r\n SRC_Offset <- Imm8[3:0]\r\n DEST[7:0] <- ((Src >> Src_Offset*8) AND 0FFh)\r\n DEST[63:8] <- ZERO_FILL;\r\nELSE\r\n SRC_Offset <-. Imm8[3:0];\r\n DEST[7:0] <- ((Src >> Src_Offset*8) AND 0FFh);\r\n DEST[31:8] <- ZERO_FILL;\r\nFI\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nPEXTRB: int _mm_extract_epi8 (__m128i src, const int ndx);\r\nPEXTRD: int _mm_extract_epi32 (__m128i src, const int ndx);\r\nPEXTRQ: __int64 _mm_extract_epi64 (__m128i src, const int ndx);\r\n\r\nFlags Affected\r\nNone.\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 5;\r\nEVEX-encoded instruction, see Exceptions Type E9NF.\r\n#UD If VEX.L = 1 or EVEX.L'L > 0.\r\n If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n If VPEXTRQ in non-64-bit mode, VEX.W=1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PEXTRB"
},
{
"description": "-R:PEXTRB",
"mnem": "PEXTRD"
},
{
"description": "-R:PEXTRB",
"mnem": "PEXTRQ"
},
{
"description": "PEXTRW-Extract Word\r\n Opcode/ Op/ 64/32 bit CPUID Description\r\n Instruction En Mode Feature\r\n Support Flag\r\n 0F C5 /r ib1 RMI V/V SSE Extract the word specified by imm8 from mm\r\n PEXTRW reg, mm, imm8 and move it to reg, bits 15-0. The upper bits of\r\n r32 or r64 is zeroed.\r\n 66 0F C5 /r ib RMI V/V SSE2 Extract the word specified by imm8 from xmm\r\n PEXTRW reg, xmm, imm8 and move it to reg, bits 15-0. The upper bits of\r\n r32 or r64 is zeroed.\r\n 66 0F 3A 15 MRI V/V SSE4_1 Extract the word specified by imm8 from xmm\r\n /r ib and copy it to lowest 16 bits of reg or m16.\r\n PEXTRW reg/m16, xmm, imm8 Zero-extend the result in the destination, r32\r\n or r64.\r\n VEX.128.66.0F.W0 C5 /r ib RMI V2/V AVX Extract the word specified by imm8 from\r\n VPEXTRW reg, xmm1, imm8 xmm1 and move it to reg, bits 15:0. Zero-\r\n extend the result. The upper bits of r64/r32 is\r\n filled with zeros.\r\n VEX.128.66.0F3A.W0 15 /r ib MRI V/V AVX Extract a word integer value from xmm2 at\r\n VPEXTRW reg/m16, xmm2, imm8 the source word offset specified by imm8 into\r\n reg or m16. The upper bits of r64/r32 is filled\r\n with zeros.\r\n EVEX.128.66.0F.WIG C5 /r ib RMI V/V AVX512B Extract the word specified by imm8 from\r\n VPEXTRW reg, xmm1, imm8 W xmm1 and move it to reg, bits 15:0. Zero-\r\n extend the result. The upper bits of r64/r32 is\r\n filled with zeros.\r\n EVEX.128.66.0F3A.WIG 15 /r ib T1S- V/V AVX512B Extract a word integer value from xmm2 at\r\n VPEXTRW reg/m16, xmm2, imm8 MRI W the source word offset specified by imm8 into\r\n reg or m16. The upper bits of r64/r32 is filled\r\n with zeros.\r\n NOTES:\r\n 1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\n Developer's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\n in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n 2. In 64-bit mode, VEX.W1 is ignored for VPEXTRW (similar to legacy REX.W=1 prefix in PEXTRW).\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (w) ModRM:r/m (r) imm8 NA\r\n MRI ModRM:r/m (w) ModRM:reg (r) imm8 NA\r\n\r\n\r\nDescription\r\nCopies the word in the source operand (second operand) specified by the count operand (third operand) to the\r\ndestination operand (first operand). The source operand can be an MMX technology register or an XMM register.\r\nThe destination operand can be the low word of a general-purpose register or a 16-bit memory address. The count\r\noperand is an 8-bit immediate. When specifying a word location in an MMX technology register, the 2 least-signifi-\r\ncant bits of the count operand specify the location; for an XMM register, the 3 least-significant bits specify the loca-\r\ntion. The content of the destination register above bit 16 is cleared (set to all 0s).\r\nIn 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers\r\n(XMM8-XMM15, R8-15). If the destination operand is a general-purpose register, the default operand size is 64-bits\r\nin 64-bit mode.\r\n\r\n\r\n\r\nNote: In VEX.128 encoded versions, VEX.vvvv is reserved and must be 1111b, VEX.L must be 0, otherwise the\r\ninstruction will #UD. In EVEX.128 encoded versions, EVEX.vvvv is reserved and must be 1111b, EVEX.L must be 0,\r\notherwise the instruction will #UD. If the destination operand is a register, the default operand size in 64-bit mode\r\nfor VPEXTRW is 64 bits, the bits above the least significant byte/word/dword data are filled with zeros.\r\n\r\nOperation\r\nIF (DEST = Mem16)\r\nTHEN\r\n SEL <- COUNT[2:0];\r\n TEMP <- (Src >> SEL*16) AND FFFFH;\r\n Mem16 <- TEMP[15:0];\r\nELSE IF (64-Bit Mode and destination is a general-purpose register)\r\n THEN\r\n FOR (PEXTRW instruction with 64-bit source operand)\r\n { SEL <- COUNT[1:0];\r\n TEMP <- (SRC >> (SEL * 16)) AND FFFFH;\r\n r64[15:0] <- TEMP[15:0];\r\n r64[63:16] <- ZERO_FILL; };\r\n FOR (PEXTRW instruction with 128-bit source operand)\r\n { SEL <- COUNT[2:0];\r\n TEMP <- (SRC >> (SEL * 16)) AND FFFFH;\r\n r64[15:0] <- TEMP[15:0];\r\n r64[63:16] <- ZERO_FILL; }\r\n ELSE\r\n FOR (PEXTRW instruction with 64-bit source operand)\r\n { SEL <- COUNT[1:0];\r\n TEMP <- (SRC >> (SEL * 16)) AND FFFFH;\r\n r32[15:0] <- TEMP[15:0];\r\n r32[31:16] <- ZERO_FILL; };\r\n FOR (PEXTRW instruction with 128-bit source operand)\r\n { SEL <- COUNT[2:0];\r\n TEMP <- (SRC >> (SEL * 16)) AND FFFFH;\r\n r32[15:0] <- TEMP[15:0];\r\n r32[31:16] <- ZERO_FILL; };\r\n FI;\r\nFI;\r\n\r\nVPEXTRW ( dest=m16)\r\nSRC_Offset <- Imm8[2:0]\r\nMem16 <- (Src >> Src_Offset*16)\r\n\r\nVPEXTRW ( dest=reg)\r\nIF (64-Bit Mode )\r\nTHEN\r\n SRC_Offset <- Imm8[2:0]\r\n DEST[15:0] <- ((Src >> Src_Offset*16) AND 0FFFFh)\r\n DEST[63:16] <- ZERO_FILL;\r\nELSE\r\n SRC_Offset <- Imm8[2:0]\r\n DEST[15:0] <- ((Src >> Src_Offset*16) AND 0FFFFh)\r\n DEST[31:16] <- ZERO_FILL;\r\nFI\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nPEXTRW: int _mm_extract_pi16 (__m64 a, int n)\r\nPEXTRW: int _mm_extract_epi16 ( __m128i a, int imm)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nNumeric Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 5;\r\nEVEX-encoded instruction, see Exceptions Type E9NF.\r\n#UD If VEX.L = 1 or EVEX.L'L > 0.\r\n If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PEXTRW"
},
{
"description": "-R:PHADDW",
"mnem": "PHADDD"
},
{
"description": "PHADDSW - Packed Horizontal Add and Saturate\r\n Opcode/ Op/ 64/32 bit CPUID Description\r\n Instruction En Mode Feature\r\n Support Flag\r\n 0F 38 03 /r1 RM V/V SSSE3 Add 16-bit signed integers horizontally, pack\r\n PHADDSW mm1, mm2/m64 saturated integers to mm1.\r\n\r\n 66 0F 38 03 /r RM V/V SSSE3 Add 16-bit signed integers horizontally, pack\r\n PHADDSW xmm1, xmm2/m128 saturated integers to xmm1.\r\n\r\n VEX.NDS.128.66.0F38.WIG 03 /r RVM V/V AVX Add 16-bit signed integers horizontally, pack\r\n VPHADDSW xmm1, xmm2, xmm3/m128 saturated integers to xmm1.\r\n\r\n VEX.NDS.256.66.0F38.WIG 03 /r RVM V/V AVX2 Add 16-bit signed integers horizontally, pack\r\n VPHADDSW ymm1, ymm2, ymm3/m256 saturated integers to ymm1.\r\n\r\n NOTES:\r\n 1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\n Developer's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\n in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\n(V)PHADDSW adds two adjacent signed 16-bit integers horizontally from the source and destination operands and\r\nsaturates the signed results; packs the signed, saturated 16-bit results to the destination operand (first operand)\r\nWhen the source operand is a 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a\r\ngeneral-protection exception (#GP) will be generated.\r\nLegacy SSE version: Both operands can be MMX registers. The second source operand can be an MMX register or a\r\n64-bit memory location.\r\n128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destina-\r\ntion register remain unchanged.\r\nIn 64-bit mode, use the REX prefix to access additional registers.\r\nVEX.128 encoded version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are\r\nzeroed.\r\nVEX.256 encoded version: The first source and destination operands are YMM registers. The second source\r\noperand can be an YMM register or a 256-bit memory location.\r\nNote: VEX.L must be 0, otherwise the instruction will #UD.\r\n\r\nOperation\r\nPHADDSW (with 64-bit operands)\r\n mm1[15-0] = SaturateToSignedWord((mm1[31-16] + mm1[15-0]);\r\n mm1[31-16] = SaturateToSignedWord(mm1[63-48] + mm1[47-32]);\r\n mm1[47-32] = SaturateToSignedWord(mm2/m64[31-16] + mm2/m64[15-0]);\r\n mm1[63-48] = SaturateToSignedWord(mm2/m64[63-48] + mm2/m64[47-32]);\r\n\r\n\r\n\r\n\r\n\r\nPHADDSW (with 128-bit operands)\r\n xmm1[15-0]= SaturateToSignedWord(xmm1[31-16] + xmm1[15-0]);\r\n xmm1[31-16] = SaturateToSignedWord(xmm1[63-48] + xmm1[47-32]);\r\n xmm1[47-32] = SaturateToSignedWord(xmm1[95-80] + xmm1[79-64]);\r\n xmm1[63-48] = SaturateToSignedWord(xmm1[127-112] + xmm1[111-96]);\r\n xmm1[79-64] = SaturateToSignedWord(xmm2/m128[31-16] + xmm2/m128[15-0]);\r\n xmm1[95-80] = SaturateToSignedWord(xmm2/m128[63-48] + xmm2/m128[47-32]);\r\n xmm1[111-96] = SaturateToSignedWord(xmm2/m128[95-80] + xmm2/m128[79-64]);\r\n xmm1[127-112] = SaturateToSignedWord(xmm2/m128[127-112] + xmm2/m128[111-96]);\r\n\r\nVPHADDSW (VEX.128 encoded version)\r\nDEST[15:0]= SaturateToSignedWord(SRC1[31:16] + SRC1[15:0])\r\nDEST[31:16] = SaturateToSignedWord(SRC1[63:48] + SRC1[47:32])\r\nDEST[47:32] = SaturateToSignedWord(SRC1[95:80] + SRC1[79:64])\r\nDEST[63:48] = SaturateToSignedWord(SRC1[127:112] + SRC1[111:96])\r\nDEST[79:64] = SaturateToSignedWord(SRC2[31:16] + SRC2[15:0])\r\nDEST[95:80] = SaturateToSignedWord(SRC2[63:48] + SRC2[47:32])\r\nDEST[111:96] = SaturateToSignedWord(SRC2[95:80] + SRC2[79:64])\r\nDEST[127:112] = SaturateToSignedWord(SRC2[127:112] + SRC2[111:96])\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPHADDSW (VEX.256 encoded version)\r\nDEST[15:0]= SaturateToSignedWord(SRC1[31:16] + SRC1[15:0])\r\nDEST[31:16] = SaturateToSignedWord(SRC1[63:48] + SRC1[47:32])\r\nDEST[47:32] = SaturateToSignedWord(SRC1[95:80] + SRC1[79:64])\r\nDEST[63:48] = SaturateToSignedWord(SRC1[127:112] + SRC1[111:96])\r\nDEST[79:64] = SaturateToSignedWord(SRC2[31:16] + SRC2[15:0])\r\nDEST[95:80] = SaturateToSignedWord(SRC2[63:48] + SRC2[47:32])\r\nDEST[111:96] = SaturateToSignedWord(SRC2[95:80] + SRC2[79:64])\r\nDEST[127:112] = SaturateToSignedWord(SRC2[127:112] + SRC2[111:96])\r\nDEST[143:128]= SaturateToSignedWord(SRC1[159:144] + SRC1[143:128])\r\nDEST[159:144] = SaturateToSignedWord(SRC1[191:176] + SRC1[175:160])\r\nDEST[175:160] = SaturateToSignedWord( SRC1[223:208] + SRC1[207:192])\r\nDEST[191:176] = SaturateToSignedWord(SRC1[255:240] + SRC1[239:224])\r\nDEST[207:192] = SaturateToSignedWord(SRC2[127:112] + SRC2[143:128])\r\nDEST[223:208] = SaturateToSignedWord(SRC2[159:144] + SRC2[175:160])\r\nDEST[239:224] = SaturateToSignedWord(SRC2[191-160] + SRC2[159-128])\r\nDEST[255:240] = SaturateToSignedWord(SRC2[255:240] + SRC2[239:224])\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nPHADDSW: __m64 _mm_hadds_pi16 (__m64 a, __m64 b)\r\n(V)PHADDSW: __m128i _mm_hadds_epi16 (__m128i a, __m128i b)\r\nVPHADDSW: __m256i _mm256_hadds_epi16 (__m256i a, __m256i b)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4; additionally\r\n#UD If VEX.L = 1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PHADDSW"
},
{
"description": "PHADDW/PHADDD - Packed Horizontal Add\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F 38 01 /r1 RM V/V SSSE3 Add 16-bit integers horizontally, pack to mm1.\r\nPHADDW mm1, mm2/m64\r\n66 0F 38 01 /r RM V/V SSSE3 Add 16-bit integers horizontally, pack to\r\nPHADDW xmm1, xmm2/m128 xmm1.\r\n\r\n0F 38 02 /r RM V/V SSSE3 Add 32-bit integers horizontally, pack to mm1.\r\nPHADDD mm1, mm2/m64\r\n66 0F 38 02 /r RM V/V SSSE3 Add 32-bit integers horizontally, pack to\r\nPHADDD xmm1, xmm2/m128 xmm1.\r\n\r\nVEX.NDS.128.66.0F38.WIG 01 /r RVM V/V AVX Add 16-bit integers horizontally, pack to\r\nVPHADDW xmm1, xmm2, xmm3/m128 xmm1.\r\n\r\nVEX.NDS.128.66.0F38.WIG 02 /r RVM V/V AVX Add 32-bit integers horizontally, pack to\r\nVPHADDD xmm1, xmm2, xmm3/m128 xmm1.\r\n\r\nVEX.NDS.256.66.0F38.WIG 01 /r RVM V/V AVX2 Add 16-bit signed integers horizontally, pack\r\nVPHADDW ymm1, ymm2, ymm3/m256 to ymm1.\r\n\r\nVEX.NDS.256.66.0F38.WIG 02 /r RVM V/V AVX2 Add 32-bit signed integers horizontally, pack\r\nVPHADDD ymm1, ymm2, ymm3/m256 to ymm1.\r\n\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\n(V)PHADDW adds two adjacent 16-bit signed integers horizontally from the source and destination operands and\r\npacks the 16-bit signed results to the destination operand (first operand). (V)PHADDD adds two adjacent 32-bit\r\nsigned integers horizontally from the source and destination operands and packs the 32-bit signed results to the\r\ndestination operand (first operand). When the source operand is a 128-bit memory operand, the operand must be\r\naligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.\r\nNote that these instructions can operate on either unsigned or signed (two's complement notation) integers;\r\nhowever, it does not set bits in the EFLAGS register to indicate overflow and/or a carry. To prevent undetected over-\r\nflow conditions, software must control the ranges of the values operated on.\r\nLegacy SSE instructions: Both operands can be MMX registers. The second source operand can be an MMX register\r\nor a 64-bit memory location.\r\n128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source\r\noperand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM\r\ndestination register remain unchanged.\r\nIn 64-bit mode, use the REX prefix to access additional registers.\r\n\r\n\r\n\r\n\r\n\r\nVEX.128 encoded version: The first source and destination operands are XMM registers. The second source\r\noperand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM\r\nregister are zeroed.\r\nVEX.256 encoded version: Horizontal addition of two adjacent data elements of the low 16-bytes of the first and\r\nsecond source operands are packed into the low 16-bytes of the destination operand. Horizontal addition of two\r\nadjacent data elements of the high 16-bytes of the first and second source operands are packed into the high 16-\r\nbytes of the destination operand. The first source and destination operands are YMM registers. The second source\r\noperand can be an YMM register or a 256-bit memory location.\r\nNote: VEX.L must be 0, otherwise the instruction will #UD.\r\n\r\n\r\n\r\n SRC2 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X7 X6 X5 X4 X3 X2 X1 X0 SRC1\r\n\r\n\r\n\r\n\r\n S7 S3 S3 S4 S3 S2 S1 S0\r\n\r\n\r\n\r\n 255 0\r\n\r\n Dest\r\n\r\n\r\n\r\n\r\n Figure 4-10. 256-bit VPHADDD Instruction Operation\r\n\r\nOperation\r\nPHADDW (with 64-bit operands)\r\n mm1[15-0] = mm1[31-16] + mm1[15-0];\r\n mm1[31-16] = mm1[63-48] + mm1[47-32];\r\n mm1[47-32] = mm2/m64[31-16] + mm2/m64[15-0];\r\n mm1[63-48] = mm2/m64[63-48] + mm2/m64[47-32];\r\n\r\nPHADDW (with 128-bit operands)\r\n xmm1[15-0] = xmm1[31-16] + xmm1[15-0];\r\n xmm1[31-16] = xmm1[63-48] + xmm1[47-32];\r\n xmm1[47-32] = xmm1[95-80] + xmm1[79-64];\r\n xmm1[63-48] = xmm1[127-112] + xmm1[111-96];\r\n xmm1[79-64] = xmm2/m128[31-16] + xmm2/m128[15-0];\r\n xmm1[95-80] = xmm2/m128[63-48] + xmm2/m128[47-32];\r\n xmm1[111-96] = xmm2/m128[95-80] + xmm2/m128[79-64];\r\n xmm1[127-112] = xmm2/m128[127-112] + xmm2/m128[111-96];\r\n\r\nVPHADDW (VEX.128 encoded version)\r\nDEST[15:0] <- SRC1[31:16] + SRC1[15:0]\r\nDEST[31:16] <- SRC1[63:48] + SRC1[47:32]\r\nDEST[47:32] <- SRC1[95:80] + SRC1[79:64]\r\nDEST[63:48] <- SRC1[127:112] + SRC1[111:96]\r\nDEST[79:64] <- SRC2[31:16] + SRC2[15:0]\r\nDEST[95:80] <- SRC2[63:48] + SRC2[47:32]\r\nDEST[111:96] <- SRC2[95:80] + SRC2[79:64]\r\nDEST[127:112] <- SRC2[127:112] + SRC2[111:96]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\n\r\n\r\nVPHADDW (VEX.256 encoded version)\r\nDEST[15:0] <- SRC1[31:16] + SRC1[15:0]\r\nDEST[31:16] <- SRC1[63:48] + SRC1[47:32]\r\nDEST[47:32] <- SRC1[95:80] + SRC1[79:64]\r\nDEST[63:48] <- SRC1[127:112] + SRC1[111:96]\r\nDEST[79:64] <- SRC2[31:16] + SRC2[15:0]\r\nDEST[95:80] <- SRC2[63:48] + SRC2[47:32]\r\nDEST[111:96] <- SRC2[95:80] + SRC2[79:64]\r\nDEST[127:112] <- SRC2[127:112] + SRC2[111:96]\r\nDEST[143:128] <- SRC1[159:144] + SRC1[143:128]\r\nDEST[159:144] <- SRC1[191:176] + SRC1[175:160]\r\nDEST[175:160] <- SRC1[223:208] + SRC1[207:192]\r\nDEST[191:176] <- SRC1[255:240] + SRC1[239:224]\r\nDEST[207:192] <- SRC2[127:112] + SRC2[143:128]\r\nDEST[223:208] <- SRC2[159:144] + SRC2[175:160]\r\nDEST[239:224] <- SRC2[191:176] + SRC2[207:192]\r\nDEST[255:240] <- SRC2[223:208] + SRC2[239:224]\r\n\r\nPHADDD (with 64-bit operands)\r\n mm1[31-0] = mm1[63-32] + mm1[31-0];\r\n mm1[63-32] = mm2/m64[63-32] + mm2/m64[31-0];\r\n\r\nPHADDD (with 128-bit operands)\r\n xmm1[31-0] = xmm1[63-32] + xmm1[31-0];\r\n xmm1[63-32] = xmm1[127-96] + xmm1[95-64];\r\n xmm1[95-64] = xmm2/m128[63-32] + xmm2/m128[31-0];\r\n xmm1[127-96] = xmm2/m128[127-96] + xmm2/m128[95-64];\r\n\r\nVPHADDD (VEX.128 encoded version)\r\nDEST[31-0] <- SRC1[63-32] + SRC1[31-0]\r\nDEST[63-32] <- SRC1[127-96] + SRC1[95-64]\r\nDEST[95-64] <- SRC2[63-32] + SRC2[31-0]\r\nDEST[127-96] <- SRC2[127-96] + SRC2[95-64]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPHADDD (VEX.256 encoded version)\r\nDEST[31-0] <- SRC1[63-32] + SRC1[31-0]\r\nDEST[63-32] <- SRC1[127-96] + SRC1[95-64]\r\nDEST[95-64] <- SRC2[63-32] + SRC2[31-0]\r\nDEST[127-96] <- SRC2[127-96] + SRC2[95-64]\r\nDEST[159-128] <- SRC1[191-160] + SRC1[159-128]\r\nDEST[191-160] <- SRC1[255-224] + SRC1[223-192]\r\nDEST[223-192] <- SRC2[191-160] + SRC2[159-128]\r\nDEST[255-224] <- SRC2[255-224] + SRC2[223-192]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nPHADDW: __m64 _mm_hadd_pi16 (__m64 a, __m64 b)\r\nPHADDD: __m64 _mm_hadd_pi32 (__m64 a, __m64 b)\r\n(V)PHADDW: __m128i _mm_hadd_epi16 (__m128i a, __m128i b)\r\n(V)PHADDD: __m128i _mm_hadd_epi32 (__m128i a, __m128i b)\r\nVPHADDW: __m256i _mm256_hadd_epi16 (__m256i a, __m256i b)\r\nVPHADDD: __m256i _mm256_hadd_epi32 (__m256i a, __m256i b)\r\n\r\n\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4; additionally\r\n#UD If VEX.L = 1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PHADDW"
},
{
"description": "PHMINPOSUW - Packed Horizontal Word Minimum\r\n Opcode/ Op/ 64/32 bit CPUID Description\r\n Instruction En Mode Feature\r\n Support Flag\r\n 66 0F 38 41 /r RM V/V SSE4_1 Find the minimum unsigned word in\r\n PHMINPOSUW xmm1, xmm2/m128 xmm2/m128 and place its value in the low\r\n word of xmm1 and its index in the second-\r\n lowest word of xmm1.\r\n VEX.128.66.0F38.WIG 41 /r RM V/V AVX Find the minimum unsigned word in\r\n VPHMINPOSUW xmm1, xmm2/m128 xmm2/m128 and place its value in the low\r\n word of xmm1 and its index in the second-\r\n lowest word of xmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\n\r\nDescription\r\nDetermine the minimum unsigned word value in the source operand (second operand) and place the unsigned\r\nword in the low word (bits 0-15) of the destination operand (first operand). The word index of the minimum value\r\nis stored in bits 16-18 of the destination operand. The remaining upper bits of the destination are set to zero.\r\n128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain\r\nunchanged.\r\nVEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed. VEX.vvvv is reserved\r\nand must be 1111b, VEX.L must be 0, otherwise the instruction will #UD.\r\n\r\nOperation\r\nPHMINPOSUW (128-bit Legacy SSE version)\r\nINDEX <- 0;\r\nMIN <- SRC[15:0]\r\nIF (SRC[31:16] < MIN)\r\n THEN INDEX <- 1; MIN <- SRC[31:16]; FI;\r\nIF (SRC[47:32] < MIN)\r\n THEN INDEX <- 2; MIN <- SRC[47:32]; FI;\r\n* Repeat operation for words 3 through 6\r\nIF (SRC[127:112] < MIN)\r\n THEN INDEX <- 7; MIN <- SRC[127:112]; FI;\r\nDEST[15:0] <- MIN;\r\nDEST[18:16] <- INDEX;\r\nDEST[127:19] <- 0000000000000000000000000000H;\r\n\r\n\r\n\r\n\r\n\r\nVPHMINPOSUW (VEX.128 encoded version)\r\nINDEX <- 0\r\nMIN <- SRC[15:0]\r\nIF (SRC[31:16] < MIN) THEN INDEX <- 1; MIN <- SRC[31:16]\r\nIF (SRC[47:32] < MIN) THEN INDEX <- 2; MIN <- SRC[47:32]\r\n* Repeat operation for words 3 through 6\r\nIF (SRC[127:112] < MIN) THEN INDEX <- 7; MIN <- SRC[127:112]\r\nDEST[15:0] <- MIN\r\nDEST[18:16] <- INDEX\r\nDEST[127:19] <- 0000000000000000000000000000H\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nPHMINPOSUW: __m128i _mm_minpos_epu16( __m128i packed_words);\r\n\r\nFlags Affected\r\nNone.\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4; additionally\r\n#UD If VEX.L = 1.\r\n If VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PHMINPOSUW"
},
{
"description": "-R:PHSUBW",
"mnem": "PHSUBD"
},
{
"description": "PHSUBSW - Packed Horizontal Subtract and Saturate\r\n Opcode/ Op/ 64/32 bit CPUID Description\r\n Instruction En Mode Feature\r\n Support Flag\r\n 0F 38 07 /r1 RM V/V SSSE3 Subtract 16-bit signed integer horizontally,\r\n PHSUBSW mm1, mm2/m64 pack saturated integers to mm1.\r\n\r\n 66 0F 38 07 /r RM V/V SSSE3 Subtract 16-bit signed integer horizontally,\r\n PHSUBSW xmm1, xmm2/m128 pack saturated integers to xmm1.\r\n\r\n VEX.NDS.128.66.0F38.WIG 07 /r RVM V/V AVX Subtract 16-bit signed integer horizontally,\r\n VPHSUBSW xmm1, xmm2, xmm3/m128 pack saturated integers to xmm1.\r\n\r\n VEX.NDS.256.66.0F38.WIG 07 /r RVM V/V AVX2 Subtract 16-bit signed integer horizontally,\r\n VPHSUBSW ymm1, ymm2, ymm3/m256 pack saturated integers to ymm1.\r\n\r\n NOTES:\r\n 1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\n Developer's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\n in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\n(V)PHSUBSW performs horizontal subtraction on each adjacent pair of 16-bit signed integers by subtracting the\r\nmost significant word from the least significant word of each pair in the source and destination operands. The\r\nsigned, saturated 16-bit results are packed to the destination operand (first operand). When the source operand is\r\na 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception\r\n(#GP) will be generated.\r\nLegacy SSE version: Both operands can be MMX registers. The second source operand can be an MMX register or\r\na 64-bit memory location.\r\n128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destina-\r\ntion register remain unchanged.\r\nIn 64-bit mode, use the REX prefix to access additional registers.\r\nVEX.128 encoded version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are\r\nzeroed.\r\nVEX.256 encoded version: The first source and destination operands are YMM registers. The second source\r\noperand can be an YMM register or a 256-bit memory location.\r\nNote: VEX.L must be 0, otherwise the instruction will #UD.\r\n\r\nOperation\r\nPHSUBSW (with 64-bit operands)\r\n mm1[15-0] = SaturateToSignedWord(mm1[15-0] - mm1[31-16]);\r\n mm1[31-16] = SaturateToSignedWord(mm1[47-32] - mm1[63-48]);\r\n mm1[47-32] = SaturateToSignedWord(mm2/m64[15-0] - mm2/m64[31-16]);\r\n mm1[63-48] = SaturateToSignedWord(mm2/m64[47-32] - mm2/m64[63-48]);\r\n\r\n\r\n\r\n\r\nPHSUBSW (with 128-bit operands)\r\n xmm1[15-0] = SaturateToSignedWord(xmm1[15-0] - xmm1[31-16]);\r\n xmm1[31-16] = SaturateToSignedWord(xmm1[47-32] - xmm1[63-48]);\r\n xmm1[47-32] = SaturateToSignedWord(xmm1[79-64] - xmm1[95-80]);\r\n xmm1[63-48] = SaturateToSignedWord(xmm1[111-96] - xmm1[127-112]);\r\n xmm1[79-64] = SaturateToSignedWord(xmm2/m128[15-0] - xmm2/m128[31-16]);\r\n xmm1[95-80] =SaturateToSignedWord(xmm2/m128[47-32] - xmm2/m128[63-48]);\r\n xmm1[111-96] =SaturateToSignedWord(xmm2/m128[79-64] - xmm2/m128[95-80]);\r\n xmm1[127-112]= SaturateToSignedWord(xmm2/m128[111-96] - xmm2/m128[127-112]);\r\n\r\nVPHSUBSW (VEX.128 encoded version)\r\nDEST[15:0]= SaturateToSignedWord(SRC1[15:0] - SRC1[31:16])\r\nDEST[31:16] = SaturateToSignedWord(SRC1[47:32] - SRC1[63:48])\r\nDEST[47:32] = SaturateToSignedWord(SRC1[79:64] - SRC1[95:80])\r\nDEST[63:48] = SaturateToSignedWord(SRC1[111:96] - SRC1[127:112])\r\nDEST[79:64] = SaturateToSignedWord(SRC2[15:0] - SRC2[31:16])\r\nDEST[95:80] = SaturateToSignedWord(SRC2[47:32] - SRC2[63:48])\r\nDEST[111:96] = SaturateToSignedWord(SRC2[79:64] - SRC2[95:80])\r\nDEST[127:112] = SaturateToSignedWord(SRC2[111:96] - SRC2[127:112])\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPHSUBSW (VEX.256 encoded version)\r\nDEST[15:0]= SaturateToSignedWord(SRC1[15:0] - SRC1[31:16])\r\nDEST[31:16] = SaturateToSignedWord(SRC1[47:32] - SRC1[63:48])\r\nDEST[47:32] = SaturateToSignedWord(SRC1[79:64] - SRC1[95:80])\r\nDEST[63:48] = SaturateToSignedWord(SRC1[111:96] - SRC1[127:112])\r\nDEST[79:64] = SaturateToSignedWord(SRC2[15:0] - SRC2[31:16])\r\nDEST[95:80] = SaturateToSignedWord(SRC2[47:32] - SRC2[63:48])\r\nDEST[111:96] = SaturateToSignedWord(SRC2[79:64] - SRC2[95:80])\r\nDEST[127:112] = SaturateToSignedWord(SRC2[111:96] - SRC2[127:112])\r\nDEST[143:128]= SaturateToSignedWord(SRC1[143:128] - SRC1[159:144])\r\nDEST[159:144] = SaturateToSignedWord(SRC1[175:160] - SRC1[191:176])\r\nDEST[175:160] = SaturateToSignedWord(SRC1[207:192] - SRC1[223:208])\r\nDEST[191:176] = SaturateToSignedWord(SRC1[239:224] - SRC1[255:240])\r\nDEST[207:192] = SaturateToSignedWord(SRC2[143:128] - SRC2[159:144])\r\nDEST[223:208] = SaturateToSignedWord(SRC2[175:160] - SRC2[191:176])\r\nDEST[239:224] = SaturateToSignedWord(SRC2[207:192] - SRC2[223:208])\r\nDEST[255:240] = SaturateToSignedWord(SRC2[239:224] - SRC2[255:240])\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nPHSUBSW: __m64 _mm_hsubs_pi16 (__m64 a, __m64 b)\r\n(V)PHSUBSW: __m128i _mm_hsubs_epi16 (__m128i a, __m128i b)\r\nVPHSUBSW: __m256i _mm256_hsubs_epi16 (__m256i a, __m256i b)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4; additionally\r\n#UD If VEX.L = 1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PHSUBSW"
},
{
"description": "PHSUBW/PHSUBD - Packed Horizontal Subtract\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F 38 05 /r1 RM V/V SSSE3 Subtract 16-bit signed integers horizontally,\r\nPHSUBW mm1, mm2/m64 pack to mm1.\r\n\r\n66 0F 38 05 /r RM V/V SSSE3 Subtract 16-bit signed integers horizontally,\r\nPHSUBW xmm1, xmm2/m128 pack to xmm1.\r\n\r\n0F 38 06 /r RM V/V SSSE3 Subtract 32-bit signed integers horizontally,\r\nPHSUBD mm1, mm2/m64 pack to mm1.\r\n\r\n66 0F 38 06 /r RM V/V SSSE3 Subtract 32-bit signed integers horizontally,\r\nPHSUBD xmm1, xmm2/m128 pack to xmm1.\r\n\r\nVEX.NDS.128.66.0F38.WIG 05 /r RVM V/V AVX Subtract 16-bit signed integers horizontally,\r\nVPHSUBW xmm1, xmm2, xmm3/m128 pack to xmm1.\r\n\r\nVEX.NDS.128.66.0F38.WIG 06 /r RVM V/V AVX Subtract 32-bit signed integers horizontally,\r\nVPHSUBD xmm1, xmm2, xmm3/m128 pack to xmm1.\r\n\r\nVEX.NDS.256.66.0F38.WIG 05 /r RVM V/V AVX2 Subtract 16-bit signed integers horizontally,\r\nVPHSUBW ymm1, ymm2, ymm3/m256 pack to ymm1.\r\n\r\nVEX.NDS.256.66.0F38.WIG 06 /r RVM V/V AVX2 Subtract 32-bit signed integers horizontally,\r\nVPHSUBD ymm1, ymm2, ymm3/m256 pack to ymm1.\r\n\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\n(V)PHSUBW performs horizontal subtraction on each adjacent pair of 16-bit signed integers by subtracting the\r\nmost significant word from the least significant word of each pair in the source and destination operands, and packs\r\nthe signed 16-bit results to the destination operand (first operand). (V)PHSUBD performs horizontal subtraction on\r\neach adjacent pair of 32-bit signed integers by subtracting the most significant doubleword from the least signifi-\r\ncant doubleword of each pair, and packs the signed 32-bit result to the destination operand. When the source\r\noperand is a 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a general-protection\r\nexception (#GP) will be generated.\r\nLegacy SSE version: Both operands can be MMX registers. The second source operand can be an MMX register or a\r\n64-bit memory location.\r\n128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destina-\r\ntion register remain unchanged.\r\nIn 64-bit mode, use the REX prefix to access additional registers.\r\nVEX.128 encoded version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are\r\nzeroed.\r\n\r\n\r\n\r\n\r\nVEX.256 encoded version: The first source and destination operands are YMM registers. The second source\r\noperand can be an YMM register or a 256-bit memory location.\r\nNote: VEX.L must be 0, otherwise the instruction will #UD.\r\n\r\nOperation\r\nPHSUBW (with 64-bit operands)\r\n mm1[15-0] = mm1[15-0] - mm1[31-16];\r\n mm1[31-16] = mm1[47-32] - mm1[63-48];\r\n mm1[47-32] = mm2/m64[15-0] - mm2/m64[31-16];\r\n mm1[63-48] = mm2/m64[47-32] - mm2/m64[63-48];\r\n\r\nPHSUBW (with 128-bit operands)\r\n xmm1[15-0] = xmm1[15-0] - xmm1[31-16];\r\n xmm1[31-16] = xmm1[47-32] - xmm1[63-48];\r\n xmm1[47-32] = xmm1[79-64] - xmm1[95-80];\r\n xmm1[63-48] = xmm1[111-96] - xmm1[127-112];\r\n xmm1[79-64] = xmm2/m128[15-0] - xmm2/m128[31-16];\r\n xmm1[95-80] = xmm2/m128[47-32] - xmm2/m128[63-48];\r\n xmm1[111-96] = xmm2/m128[79-64] - xmm2/m128[95-80];\r\n xmm1[127-112] = xmm2/m128[111-96] - xmm2/m128[127-112];\r\n\r\nVPHSUBW (VEX.128 encoded version)\r\nDEST[15:0] <- SRC1[15:0] - SRC1[31:16]\r\nDEST[31:16] <- SRC1[47:32] - SRC1[63:48]\r\nDEST[47:32] <- SRC1[79:64] - SRC1[95:80]\r\nDEST[63:48] <- SRC1[111:96] - SRC1[127:112]\r\nDEST[79:64] <- SRC2[15:0] - SRC2[31:16]\r\nDEST[95:80] <- SRC2[47:32] - SRC2[63:48]\r\nDEST[111:96] <- SRC2[79:64] - SRC2[95:80]\r\nDEST[127:112] <- SRC2[111:96] - SRC2[127:112]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPHSUBW (VEX.256 encoded version)\r\nDEST[15:0] <- SRC1[15:0] - SRC1[31:16]\r\nDEST[31:16] <- SRC1[47:32] - SRC1[63:48]\r\nDEST[47:32] <- SRC1[79:64] - SRC1[95:80]\r\nDEST[63:48] <- SRC1[111:96] - SRC1[127:112]\r\nDEST[79:64] <- SRC2[15:0] - SRC2[31:16]\r\nDEST[95:80] <- SRC2[47:32] - SRC2[63:48]\r\nDEST[111:96] <- SRC2[79:64] - SRC2[95:80]\r\nDEST[127:112] <- SRC2[111:96] - SRC2[127:112]\r\nDEST[143:128] <- SRC1[143:128] - SRC1[159:144]\r\nDEST[159:144] <- SRC1[175:160] - SRC1[191:176]\r\nDEST[175:160] <- SRC1[207:192] - SRC1[223:208]\r\nDEST[191:176] <- SRC1[239:224] - SRC1[255:240]\r\nDEST[207:192] <- SRC2[143:128] - SRC2[159:144]\r\nDEST[223:208] <- SRC2[175:160] - SRC2[191:176]\r\nDEST[239:224] <- SRC2[207:192] - SRC2[223:208]\r\nDEST[255:240] <- SRC2[239:224] - SRC2[255:240]\r\n\r\nPHSUBD (with 64-bit operands)\r\n mm1[31-0] = mm1[31-0] - mm1[63-32];\r\n mm1[63-32] = mm2/m64[31-0] - mm2/m64[63-32];\r\n\r\n\r\n\r\n\r\nPHSUBD (with 128-bit operands)\r\n xmm1[31-0] = xmm1[31-0] - xmm1[63-32];\r\n xmm1[63-32] = xmm1[95-64] - xmm1[127-96];\r\n xmm1[95-64] = xmm2/m128[31-0] - xmm2/m128[63-32];\r\n xmm1[127-96] = xmm2/m128[95-64] - xmm2/m128[127-96];\r\n\r\nVPHSUBD (VEX.128 encoded version)\r\nDEST[31-0] <- SRC1[31-0] - SRC1[63-32]\r\nDEST[63-32] <- SRC1[95-64] - SRC1[127-96]\r\nDEST[95-64] <- SRC2[31-0] - SRC2[63-32]\r\nDEST[127-96] <- SRC2[95-64] - SRC2[127-96]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPHSUBD (VEX.256 encoded version)\r\nDEST[31:0] <- SRC1[31:0] - SRC1[63:32]\r\nDEST[63:32] <- SRC1[95:64] - SRC1[127:96]\r\nDEST[95:64] <- SRC2[31:0] - SRC2[63:32]\r\nDEST[127:96] <- SRC2[95:64] - SRC2[127:96]\r\nDEST[159:128] <- SRC1[159:128] - SRC1[191:160]\r\nDEST[191:160] <- SRC1[223:192] - SRC1[255:224]\r\nDEST[223:192] <- SRC2[159:128] - SRC2[191:160]\r\nDEST[255:224] <- SRC2[223:192] - SRC2[255:224]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nPHSUBW: __m64 _mm_hsub_pi16 (__m64 a, __m64 b)\r\nPHSUBD: __m64 _mm_hsub_pi32 (__m64 a, __m64 b)\r\n(V)PHSUBW: __m128i _mm_hsub_epi16 (__m128i a, __m128i b)\r\n(V)PHSUBD: __m128i _mm_hsub_epi32 (__m128i a, __m128i b)\r\nVPHSUBW: __m256i _mm256_hsub_epi16 (__m256i a, __m256i b)\r\nVPHSUBD: __m256i _mm256_hsub_epi32 (__m256i a, __m256i b)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4; additionally\r\n#UD If VEX.L = 1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PHSUBW"
},
{
"description": "PINSRB/PINSRD/PINSRQ - Insert Byte/Dword/Qword\r\nOpcode/ Op/ En 64/32 bit CPUID Description\r\nInstruction Mode Feature\r\n Support Flag\r\n66 0F 3A 20 /r ib RMI V/V SSE4_1 Insert a byte integer value from r32/m8 into\r\nPINSRB xmm1, r32/m8, imm8 xmm1 at the destination element in xmm1\r\n specified by imm8.\r\n66 0F 3A 22 /r ib RMI V/V SSE4_1 Insert a dword integer value from r/m32 into\r\nPINSRD xmm1, r/m32, imm8 the xmm1 at the destination element\r\n specified by imm8.\r\n66 REX.W 0F 3A 22 /r ib RMI V/N. E. SSE4_1 Insert a qword integer value from r/m64 into\r\nPINSRQ xmm1, r/m64, imm8 the xmm1 at the destination element\r\n specified by imm8.\r\nVEX.NDS.128.66.0F3A.W0 20 /r ib RVMI V1/V AVX Merge a byte integer value from r32/m8 and\r\nVPINSRB xmm1, xmm2, r32/m8, imm8 rest from xmm2 into xmm1 at the byte offset\r\n in imm8.\r\nVEX.NDS.128.66.0F3A.W0 22 /r ib RVMI V/V AVX Insert a dword integer value from r32/m32\r\nVPINSRD xmm1, xmm2, r/m32, imm8 and rest from xmm2 into xmm1 at the dword\r\n offset in imm8.\r\nVEX.NDS.128.66.0F3A.W1 22 /r ib RVMI V/I AVX Insert a qword integer value from r64/m64\r\nVPINSRQ xmm1, xmm2, r/m64, imm8 and rest from xmm2 into xmm1 at the qword\r\n offset in imm8.\r\nEVEX.NDS.128.66.0F3A.WIG 20 /r ib T1S- V/V AVX512BW Merge a byte integer value from r32/m8 and\r\nVPINSRB xmm1, xmm2, r32/m8, imm8 RVMI rest from xmm2 into xmm1 at the byte offset\r\n in imm8.\r\nEVEX.NDS.128.66.0F3A.W0 22 /r ib T1S- V/V AVX512DQ Insert a dword integer value from r32/m32\r\nVPINSRD xmm1, xmm2, r32/m32, imm8 RVMI and rest from xmm2 into xmm1 at the dword\r\n offset in imm8.\r\nEVEX.NDS.128.66.0F3A.W1 22 /r ib T1S- V/N.E.1 AVX512DQ Insert a qword integer value from r64/m64\r\nVPINSRQ xmm1, xmm2, r64/m64, imm8 RVMI and rest from xmm2 into xmm1 at the qword\r\n offset in imm8.\r\nNOTES:\r\n1. In 64-bit mode, VEX.W1 is ignored for VPINSRB (similar to legacy REX.W=1 prefix with PINSRB).\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (w) ModRM:r/m (r) imm8 NA\r\n RVMI ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8\r\n T1S-RVMI ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) Imm8\r\n\r\n\r\nDescription\r\nCopies a byte/dword/qword from the source operand (second operand) and inserts it in the destination operand\r\n(first operand) at the location specified with the count operand (third operand). (The other elements in the desti-\r\nnation register are left untouched.) The source operand can be a general-purpose register or a memory location.\r\n(When the source operand is a general-purpose register, PINSRB copies the low byte of the register.) The destina-\r\ntion operand is an XMM register. The count operand is an 8-bit immediate. When specifying a qword[dword, byte]\r\nlocation in an XMM register, the [2, 4] least-significant bit(s) of the count operand specify the location.\r\nIn 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to\r\naccess additional registers (XMM8-XMM15, R8-15). Use of REX.W permits the use of 64 bit general purpose regis-\r\nters.\r\n\r\n\r\n\r\n128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain\r\nunchanged.\r\nVEX.128 encoded version: Bits (VLMAX-1:128) of the destination register are zeroed. VEX.L must be 0, otherwise\r\nthe instruction will #UD. Attempt to execute VPINSRQ in non-64-bit mode will cause #UD.\r\nEVEX.128 encoded version: Bits (VLMAX-1:128) of the destination register are zeroed. EVEX.L'L must be 0, other-\r\nwise the instruction will #UD.\r\n\r\nOperation\r\nCASE OF\r\n PINSRB: SEL <- COUNT[3:0];\r\n MASK <- (0FFH << (SEL * 8));\r\n TEMP <- (((SRC[7:0] << (SEL *8)) AND MASK);\r\n PINSRD: SEL <- COUNT[1:0];\r\n MASK <- (0FFFFFFFFH << (SEL * 32));\r\n TEMP <- (((SRC << (SEL *32)) AND MASK) ;\r\n PINSRQ: SEL <- COUNT[0]\r\n MASK <- (0FFFFFFFFFFFFFFFFH << (SEL * 64));\r\n TEMP <- (((SRC << (SEL *64)) AND MASK) ;\r\nESAC;\r\n DEST <- ((DEST AND NOT MASK) OR TEMP);\r\n\r\nVPINSRB (VEX/EVEX encoded version)\r\nSEL <- imm8[3:0]\r\nDEST[127:0] <- write_b_element(SEL, SRC2, SRC1)\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPINSRD (VEX/EVEX encoded version)\r\nSEL <- imm8[1:0]\r\nDEST[127:0] <- write_d_element(SEL, SRC2, SRC1)\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPINSRQ (VEX/EVEX encoded version)\r\nSEL <- imm8[0]\r\nDEST[127:0] <- write_q_element(SEL, SRC2, SRC1)\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nPINSRB: __m128i _mm_insert_epi8 (__m128i s1, int s2, const int ndx);\r\nPINSRD: __m128i _mm_insert_epi32 (__m128i s2, int s, const int ndx);\r\nPINSRQ: __m128i _mm_insert_epi64(__m128i s2, __int64 s, const int ndx);\r\n\r\nFlags Affected\r\nNone.\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nEVEX-encoded instruction, see Exceptions Type 5;\r\nEVEX-encoded instruction, see Exceptions Type E9NF.\r\n\r\n\r\n\r\n\r\n#UD If VEX.L = 1 or EVEX.L'L > 0.\r\n If VPINSRQ in non-64-bit mode with VEX.W=1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PINSRB"
},
{
"description": "-R:PINSRB",
"mnem": "PINSRD"
},
{
"description": "-R:PINSRB",
"mnem": "PINSRQ"
},
{
"description": "PINSRW-Insert Word\r\nOpcode/ Op/ En 64/32 bit CPUID Description\r\nInstruction Mode Feature\r\n Support Flag\r\n0F C4 /r ib1 RMI V/V SSE Insert the low word from r32 or from m16\r\nPINSRW mm, r32/m16, imm8 into mm at the word position specified by\r\n imm8.\r\n66 0F C4 /r ib RMI V/V SSE2 Move the low word of r32 or from m16 into\r\nPINSRW xmm, r32/m16, imm8 xmm at the word position specified by imm8.\r\n\r\nVEX.NDS.128.66.0F.W0 C4 /r ib RVMI V2/V AVX Insert a word integer value from r32/m16\r\nVPINSRW xmm1, xmm2, r32/m16, imm8 and rest from xmm2 into xmm1 at the word\r\n offset in imm8.\r\nEVEX.NDS.128.66.0F.WIG C4 /r ib T1S- V/V AVX512BW Insert a word integer value from r32/m16 and\r\nVPINSRW xmm1, xmm2, r32/m16, imm8 RVMI rest from xmm2 into xmm1 at the word\r\n offset in imm8.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n2. In 64-bit mode, VEX.W1 is ignored for VPINSRW (similar to legacy REX.W=1 prefix in PINSRW).\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (w) ModRM:r/m (r) imm8 NA\r\n RVMI ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8\r\n T1S-RVMI ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) Imm8\r\n\r\n\r\nDescription\r\nCopies a word from the source operand (second operand) and inserts it in the destination operand (first operand)\r\nat the location specified with the count operand (third operand). (The other words in the destination register are\r\nleft untouched.) The source operand can be a general-purpose register or a 16-bit memory location. (When the\r\nsource operand is a general-purpose register, the low word of the register is copied.) The destination operand can\r\nbe an MMX technology register or an XMM register. The count operand is an 8-bit immediate. When specifying a\r\nword location in an MMX technology register, the 2 least-significant bits of the count operand specify the location;\r\nfor an XMM register, the 3 least-significant bits specify the location.\r\nIn 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to\r\naccess additional registers (XMM8-XMM15, R8-15).\r\n128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain\r\nunchanged.\r\nVEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed. VEX.L must be 0, other-\r\nwise the instruction will #UD.\r\nEVEX.128 encoded version: Bits (VLMAX-1:128) of the destination register are zeroed. EVEX.L'L must be 0, other-\r\nwise the instruction will #UD.\r\n\r\nOperation\r\nPINSRW (with 64-bit source operand)\r\n SEL <- COUNT AND 3H;\r\n CASE (Determine word position) OF\r\n SEL <- 0: MASK <- 000000000000FFFFH;\r\n\r\n\r\n\r\n SEL <- 1: MASK <- 00000000FFFF0000H;\r\n SEL <- 2: MASK <- 0000FFFF00000000H;\r\n SEL <- 3: MASK <- FFFF000000000000H;\r\n DEST <- (DEST AND NOT MASK) OR (((SRC << (SEL * 16)) AND MASK);\r\n\r\nPINSRW (with 128-bit source operand)\r\n SEL <- COUNT AND 7H;\r\n CASE (Determine word position) OF\r\n SEL <- 0: MASK <- 0000000000000000000000000000FFFFH;\r\n SEL <- 1: MASK <- 000000000000000000000000FFFF0000H;\r\n SEL <- 2: MASK <- 00000000000000000000FFFF00000000H;\r\n SEL <- 3: MASK <- 0000000000000000FFFF000000000000H;\r\n SEL <- 4: MASK <- 000000000000FFFF0000000000000000H;\r\n SEL <- 5: MASK <- 00000000FFFF00000000000000000000H;\r\n SEL <- 6: MASK <- 0000FFFF000000000000000000000000H;\r\n SEL <- 7: MASK <- FFFF0000000000000000000000000000H;\r\n DEST <- (DEST AND NOT MASK) OR (((SRC << (SEL * 16)) AND MASK);\r\n\r\nVPINSRW (VEX/EVEX encoded version)\r\nSEL <- imm8[2:0]\r\nDEST[127:0] <- write_w_element(SEL, SRC2, SRC1)\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nPINSRW: __m64 _mm_insert_pi16 (__m64 a, int d, int n)\r\nPINSRW: __m128i _mm_insert_epi16 ( __m128i a, int b, int imm)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nNumeric Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nEVEX-encoded instruction, see Exceptions Type 5;\r\nEVEX-encoded instruction, see Exceptions Type E9NF.\r\n#UD If VEX.L = 1 or EVEX.L'L > 0.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PINSRW"
},
{
"description": "PMADDUBSW - Multiply and Add Packed Signed and Unsigned Bytes\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F 38 04 /r1 RM V/V SSSE3 Multiply signed and unsigned bytes, add\r\nPMADDUBSW mm1, mm2/m64 horizontal pair of signed words, pack\r\n saturated signed-words to mm1.\r\n66 0F 38 04 /r RM V/V SSSE3 Multiply signed and unsigned bytes, add\r\nPMADDUBSW xmm1, xmm2/m128 horizontal pair of signed words, pack\r\n saturated signed-words to xmm1.\r\nVEX.NDS.128.66.0F38.WIG 04 /r RVM V/V AVX Multiply signed and unsigned bytes, add\r\nVPMADDUBSW xmm1, xmm2, xmm3/m128 horizontal pair of signed words, pack\r\n saturated signed-words to xmm1.\r\nVEX.NDS.256.66.0F38.WIG 04 /r RVM V/V AVX2 Multiply signed and unsigned bytes, add\r\nVPMADDUBSW ymm1, ymm2, ymm3/m256 horizontal pair of signed words, pack\r\n saturated signed-words to ymm1.\r\nEVEX.NDS.128.66.0F38.WIG 04 /r FVM V/V AVX512VL Multiply signed and unsigned bytes, add\r\nVPMADDUBSW xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512BW horizontal pair of signed words, pack\r\n saturated signed-words to xmm1 under\r\n writemask k1.\r\nEVEX.NDS.256.66.0F38.WIG 04 /r FVM V/V AVX512VL Multiply signed and unsigned bytes, add\r\nVPMADDUBSW ymm1 {k1}{z}, ymm2, ymm3/m256 AVX512BW horizontal pair of signed words, pack\r\n saturated signed-words to ymm1 under\r\n writemask k1.\r\nEVEX.NDS.512.66.0F38.WIG 04 /r FVM V/V AVX512BW Multiply signed and unsigned bytes, add\r\nVPMADDUBSW zmm1 {k1}{z}, zmm2, zmm3/m512 horizontal pair of signed words, pack\r\n saturated signed-words to zmm1 under\r\n writemask k1.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\n(V)PMADDUBSW multiplies vertically each unsigned byte of the destination operand (first operand) with the corre-\r\nsponding signed byte of the source operand (second operand), producing intermediate signed 16-bit integers. Each\r\nadjacent pair of signed words is added and the saturated result is packed to the destination operand. For example,\r\nthe lowest-order bytes (bits 7-0) in the source and destination operands are multiplied and the intermediate signed\r\nword result is added with the corresponding intermediate result from the 2nd lowest-order bytes (bits 15-8) of the\r\noperands; the sign-saturated result is stored in the lowest word of the destination register (15-0). The same oper-\r\nation is performed on the other pairs of adjacent bytes. Both operands can be MMX register or XMM registers. When\r\nthe source operand is a 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a\r\ngeneral-protection exception (#GP) will be generated.\r\nIn 64-bit mode and not encoded with VEX/EVEX, use the REX prefix to access XMM8-XMM15.\r\n\r\n\r\n\r\n\r\n128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination\r\nregister remain unchanged.\r\nVEX.128 and EVEX.128 encoded versions: The first source and destination operands are XMM registers. The\r\nsecond source operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corre-\r\nsponding destination register are zeroed.\r\nVEX.256 and EVEX.256 encoded versions: The second source operand can be an YMM register or a 256-bit memory\r\nlocation. The first source and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding\r\nZMM register are zeroed.\r\nEVEX.512 encoded version: The second source operand can be an ZMM register or a 512-bit memory location. The\r\nfirst source and destination operands are ZMM registers.\r\n\r\nOperation\r\nPMADDUBSW (with 64 bit operands)\r\n DEST[15-0] = SaturateToSignedWord(SRC[15-8]*DEST[15-8]+SRC[7-0]*DEST[7-0]);\r\n DEST[31-16] = SaturateToSignedWord(SRC[31-24]*DEST[31-24]+SRC[23-16]*DEST[23-16]);\r\n DEST[47-32] = SaturateToSignedWord(SRC[47-40]*DEST[47-40]+SRC[39-32]*DEST[39-32]);\r\n DEST[63-48] = SaturateToSignedWord(SRC[63-56]*DEST[63-56]+SRC[55-48]*DEST[55-48]);\r\nPMADDUBSW (with 128 bit operands)\r\n DEST[15-0] = SaturateToSignedWord(SRC[15-8]* DEST[15-8]+SRC[7-0]*DEST[7-0]);\r\n // Repeat operation for 2nd through 7th word\r\n SRC1/DEST[127-112] = SaturateToSignedWord(SRC[127-120]*DEST[127-120]+ SRC[119-112]* DEST[119-112]);\r\n\r\nVPMADDUBSW (VEX.128 encoded version)\r\nDEST[15:0] <- SaturateToSignedWord(SRC2[15:8]* SRC1[15:8]+SRC2[7:0]*SRC1[7:0])\r\n// Repeat operation for 2nd through 7th word\r\nDEST[127:112] <- SaturateToSignedWord(SRC2[127:120]*SRC1[127:120]+ SRC2[119:112]* SRC1[119:112])\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPMADDUBSW (VEX.256 encoded version)\r\nDEST[15:0] <- SaturateToSignedWord(SRC2[15:8]* SRC1[15:8]+SRC2[7:0]*SRC1[7:0])\r\n// Repeat operation for 2nd through 15th word\r\nDEST[255:240] <- SaturateToSignedWord(SRC2[255:248]*SRC1[255:248]+ SRC2[247:240]* SRC1[247:240])\r\nDEST[VLMAX-1:256] <- 0\r\n\r\nVPMADDUBSW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- SaturateToSignedWord(SRC2[i+15:i+8]* SRC1[i+15:i+8] + SRC2[i+7:i]*SRC1[i+7:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] = 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPMADDUBSW __m512i _mm512_mddubs_epi16( __m512i a, __m512i b);\r\nVPMADDUBSW __m512i _mm512_mask_mddubs_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);\r\nVPMADDUBSW __m512i _mm512_maskz_mddubs_epi16( __mmask32 k, __m512i a, __m512i b);\r\nVPMADDUBSW __m256i _mm256_mask_mddubs_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);\r\nVPMADDUBSW __m256i _mm256_maskz_mddubs_epi16( __mmask16 k, __m256i a, __m256i b);\r\nVPMADDUBSW __m128i _mm_mask_mddubs_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPMADDUBSW __m128i _mm_maskz_maddubs_epi16( __mmask8 k, __m128i a, __m128i b);\r\nPMADDUBSW: __m64 _mm_maddubs_pi16 (__m64 a, __m64 b)\r\n(V)PMADDUBSW: __m128i _mm_maddubs_epi16 (__m128i a, __m128i b)\r\nVPMADDUBSW: __m256i _mm256_maddubs_epi16 (__m256i a, __m256i b)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4NF.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PMADDUBSW"
},
{
"description": "PMADDWD-Multiply and Add Packed Integers\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F F5 /r1 RM V/V MMX Multiply the packed words in mm by the packed\r\nPMADDWD mm, mm/m64 words in mm/m64, add adjacent doubleword\r\n results, and store in mm.\r\n66 0F F5 /r RM V/V SSE2 Multiply the packed word integers in xmm1 by\r\nPMADDWD xmm1, xmm2/m128 the packed word integers in xmm2/m128, add\r\n adjacent doubleword results, and store in\r\n xmm1.\r\nVEX.NDS.128.66.0F.WIG F5 /r RVM V/V AVX Multiply the packed word integers in xmm2 by\r\nVPMADDWD xmm1, xmm2, xmm3/m128 the packed word integers in xmm3/m128, add\r\n adjacent doubleword results, and store in\r\n xmm1.\r\nVEX.NDS.256.66.0F.WIG F5 /r RVM V/V AVX2 Multiply the packed word integers in ymm2 by\r\nVPMADDWD ymm1, ymm2, ymm3/m256 the packed word integers in ymm3/m256, add\r\n adjacent doubleword results, and store in\r\n ymm1.\r\nEVEX.NDS.128.66.0F.WIG F5 /r FVM V/V AVX512VL Multiply the packed word integers in xmm2 by\r\nVPMADDWD xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512BW the packed word integers in xmm3/m128, add\r\n adjacent doubleword results, and store in\r\n xmm1 under writemask k1.\r\nEVEX.NDS.256.66.0F.WIG F5 /r FVM V/V AVX512VL Multiply the packed word integers in ymm2 by\r\nVPMADDWD ymm1 {k1}{z}, ymm2, ymm3/m256 AVX512BW the packed word integers in ymm3/m256, add\r\n adjacent doubleword results, and store in\r\n ymm1 under writemask k1.\r\nEVEX.NDS.512.66.0F.WIG F5 /r FVM V/V AVX512BW Multiply the packed word integers in zmm2 by\r\nVPMADDWD zmm1 {k1}{z}, zmm2, zmm3/m512 the packed word integers in zmm3/m512, add\r\n adjacent doubleword results, and store in\r\n zmm1 under writemask k1.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nMultiplies the individual signed words of the destination operand (first operand) by the corresponding signed words\r\nof the source operand (second operand), producing temporary signed, doubleword results. The adjacent double-\r\nword results are then summed and stored in the destination operand. For example, the corresponding low-order\r\nwords (15-0) and (31-16) in the source and destination operands are multiplied by one another and the double-\r\nword results are added together and stored in the low doubleword of the destination register (31-0). The same\r\noperation is performed on the other pairs of adjacent words. (Figure 4-11 shows this operation when using 64-bit\r\noperands).\r\n\r\n\r\n\r\n\r\n\r\nThe (V)PMADDWD instruction wraps around only in one situation: when the 2 pairs of words being operated on in\r\na group are all 8000H. In this case, the result wraps around to 80000000H.\r\nIn 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to\r\naccess additional registers (XMM8-XMM15).\r\nLegacy SSE version: The first source and destination operands are MMX registers. The second source operand is an\r\nMMX register or a 64-bit memory location.\r\n128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destina-\r\ntion register remain unchanged.\r\nVEX.128 encoded version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are\r\nzeroed.\r\nVEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The\r\nfirst source and destination operands are YMM registers.\r\nEVEX.512 encoded version: The second source operand can be an ZMM register or a 512-bit memory location. The\r\nfirst source and destination operands are ZMM registers.\r\n\r\n\r\n\r\n SRC X3 X2 X1 X0\r\n\r\n\r\n DEST Y3 Y2 Y1 Y0\r\n\r\n\r\n TEMP X3 * Y3 X2 * Y2 X1 * Y1 X0 * Y0\r\n\r\n\r\n DEST (X3*Y3) + (X2*Y2) (X1*Y1) + (X0*Y0)\r\n\r\n\r\n Figure 4-11. PMADDWD Execution Model Using 64-bit Operands\r\n\r\n\r\nOperation\r\nPMADDWD (with 64-bit operands)\r\n DEST[31:0] <- (DEST[15:0] * SRC[15:0]) + (DEST[31:16] * SRC[31:16]);\r\n DEST[63:32] <- (DEST[47:32] * SRC[47:32]) + (DEST[63:48] * SRC[63:48]);\r\n\r\nPMADDWD (with 128-bit operands)\r\n DEST[31:0] <- (DEST[15:0] * SRC[15:0]) + (DEST[31:16] * SRC[31:16]);\r\n DEST[63:32] <- (DEST[47:32] * SRC[47:32]) + (DEST[63:48] * SRC[63:48]);\r\n DEST[95:64] <- (DEST[79:64] * SRC[79:64]) + (DEST[95:80] * SRC[95:80]);\r\n DEST[127:96] <- (DEST[111:96] * SRC[111:96]) + (DEST[127:112] * SRC[127:112]);\r\n\r\nVPMADDWD (VEX.128 encoded version)\r\nDEST[31:0] <- (SRC1[15:0] * SRC2[15:0]) + (SRC1[31:16] * SRC2[31:16])\r\nDEST[63:32] <- (SRC1[47:32] * SRC2[47:32]) + (SRC1[63:48] * SRC2[63:48])\r\nDEST[95:64] <- (SRC1[79:64] * SRC2[79:64]) + (SRC1[95:80] * SRC2[95:80])\r\nDEST[127:96] <- (SRC1[111:96] * SRC2[111:96]) + (SRC1[127:112] * SRC2[127:112])\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPMADDWD (VEX.256 encoded version)\r\nDEST[31:0] <- (SRC1[15:0] * SRC2[15:0]) + (SRC1[31:16] * SRC2[31:16])\r\nDEST[63:32] <- (SRC1[47:32] * SRC2[47:32]) + (SRC1[63:48] * SRC2[63:48])\r\nDEST[95:64] <- (SRC1[79:64] * SRC2[79:64]) + (SRC1[95:80] * SRC2[95:80])\r\nDEST[127:96] <- (SRC1[111:96] * SRC2[111:96]) + (SRC1[127:112] * SRC2[127:112])\r\n\r\n\r\n\r\n\r\nDEST[159:128] <- (SRC1[143:128] * SRC2[143:128]) + (SRC1[159:144] * SRC2[159:144])\r\nDEST[191:160] <- (SRC1[175:160] * SRC2[175:160]) + (SRC1[191:176] * SRC2[191:176])\r\nDEST[223:192] <- (SRC1[207:192] * SRC2[207:192]) + (SRC1[223:208] * SRC2[223:208])\r\nDEST[255:224] <- (SRC1[239:224] * SRC2[239:224]) + (SRC1[255:240] * SRC2[255:240])\r\nDEST[VLMAX-1:256] <- 0\r\n\r\nVPMADDWD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- (SRC2[i+31:i+16]* SRC1[i+31:i+16]) + (SRC2[i+15:i]*SRC1[i+15:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] = 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPMADDWD __m512i _mm512_mdd_epi16( __m512i a, __m512i b);\r\nVPMADDWD __m512i _mm512_mask_mdd_epi16(__m512i s, __mmask16 k, __m512i a, __m512i b);\r\nVPMADDWD __m512i _mm512_maskz_mdd_epi16( __mmask16 k, __m512i a, __m512i b);\r\nVPMADDWD __m256i _mm256_mask_mdd_epi16(__m256i s, __mmask8 k, __m256i a, __m256i b);\r\nVPMADDWD __m256i _mm256_maskz_mdd_epi16( __mmask8 k, __m256i a, __m256i b);\r\nVPMADDWD __m128i _mm_mask_mdd_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPMADDWD __m128i _mm_maskz_madd_epi16( __mmask8 k, __m128i a, __m128i b);\r\nPMADDWD:__m64 _mm_madd_pi16(__m64 m1, __m64 m2)\r\n(V)PMADDWD:__m128i _mm_madd_epi16 ( __m128i a, __m128i b)\r\nVPMADDWD:__m256i _mm256_madd_epi16 ( __m256i a, __m256i b)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nNumeric Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4NF.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PMADDWD"
},
{
"description": "PMAXSB/PMAXSW/PMAXSD/PMAXSQ-Maximum of Packed Signed Integers\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 0F EE /r1 RM V/V SSE Compare signed word integers in mm2/m64 and\r\n PMAXSW mm1, mm2/m64 mm1 and return maximum values.\r\n 66 0F 38 3C /r RM V/V SSE4_1 Compare packed signed byte integers in xmm1 and\r\n PMAXSB xmm1, xmm2/m128 xmm2/m128 and store packed maximum values in\r\n xmm1.\r\n 66 0F EE /r RM V/V SSE2 Compare packed signed word integers in\r\n PMAXSW xmm1, xmm2/m128 xmm2/m128 and xmm1 and stores maximum\r\n packed values in xmm1.\r\n 66 0F 38 3D /r RM V/V SSE4_1 Compare packed signed dword integers in xmm1\r\n PMAXSD xmm1, xmm2/m128 and xmm2/m128 and store packed maximum values\r\n in xmm1.\r\n VEX.NDS.128.66.0F38.WIG 3C /r RVM V/V AVX Compare packed signed byte integers in xmm2 and\r\n VPMAXSB xmm1, xmm2, xmm3/m128 xmm3/m128 and store packed maximum values in\r\n xmm1.\r\n VEX.NDS.128.66.0F.WIG EE /r RVM V/V AVX Compare packed signed word integers in\r\n VPMAXSW xmm1, xmm2, xmm3/m128 xmm3/m128 and xmm2 and store packed maximum\r\n values in xmm1.\r\n VEX.NDS.128.66.0F38.WIG 3D /r RVM V/V AVX Compare packed signed dword integers in xmm2\r\n VPMAXSD xmm1, xmm2, xmm3/m128 and xmm3/m128 and store packed maximum values\r\n in xmm1.\r\n VEX.NDS.256.66.0F38.WIG 3C /r RVM V/V AVX2 Compare packed signed byte integers in ymm2 and\r\n VPMAXSB ymm1, ymm2, ymm3/m256 ymm3/m256 and store packed maximum values in\r\n ymm1.\r\n VEX.NDS.256.66.0F.WIG EE /r RVM V/V AVX2 Compare packed signed word integers in\r\n VPMAXSW ymm1, ymm2, ymm3/m256 ymm3/m256 and ymm2 and store packed maximum\r\n values in ymm1.\r\n VEX.NDS.256.66.0F38.WIG 3D /r RVM V/V AVX2 Compare packed signed dword integers in ymm2\r\n VPMAXSD ymm1, ymm2, ymm3/m256 and ymm3/m256 and store packed maximum values\r\n in ymm1.\r\n EVEX.NDS.128.66.0F38.WIG 3C /r FVM V/V AVX512VL Compare packed signed byte integers in xmm2 and\r\n VPMAXSB xmm1{k1}{z}, xmm2, AVX512BW xmm3/m128 and store packed maximum values in\r\n xmm3/m128 xmm1 under writemask k1.\r\n EVEX.NDS.256.66.0F38.WIG 3C /r FVM V/V AVX512VL Compare packed signed byte integers in ymm2 and\r\n VPMAXSB ymm1{k1}{z}, ymm2, AVX512BW ymm3/m256 and store packed maximum values in\r\n ymm3/m256 ymm1 under writemask k1.\r\n EVEX.NDS.512.66.0F38.WIG 3C /r FVM V/V AVX512BW Compare packed signed byte integers in zmm2 and\r\n VPMAXSB zmm1{k1}{z}, zmm2, zmm3/m512 and store packed maximum values in\r\n zmm3/m512 zmm1 under writemask k1.\r\n EVEX.NDS.128.66.0F.WIG EE /r FVM V/V AVX512VL Compare packed signed word integers in xmm2 and\r\n VPMAXSW xmm1{k1}{z}, xmm2, AVX512BW xmm3/m128 and store packed maximum values in\r\n xmm3/m128 xmm1 under writemask k1.\r\n EVEX.NDS.256.66.0F.WIG EE /r FVM V/V AVX512VL Compare packed signed word integers in ymm2 and\r\n VPMAXSW ymm1{k1}{z}, ymm2, AVX512BW ymm3/m256 and store packed maximum values in\r\n ymm3/m256 ymm1 under writemask k1.\r\n EVEX.NDS.512.66.0F.WIG EE /r FVM V/V AVX512BW Compare packed signed word integers in zmm2 and\r\n VPMAXSW zmm1{k1}{z}, zmm2, zmm3/m512 and store packed maximum values in\r\n zmm3/m512 zmm1 under writemask k1.\r\n EVEX.NDS.128.66.0F38.W0 3D /r FV V/V AVX512VL Compare packed signed dword integers in xmm2\r\n VPMAXSD xmm1 {k1}{z}, xmm2, AVX512F and xmm3/m128/m32bcst and store packed\r\n xmm3/m128/m32bcst maximum values in xmm1 using writemask k1.\r\n\r\n\r\n\r\n\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.256.66.0F38.W0 3D /r FV V/V AVX512VL Compare packed signed dword integers in ymm2\r\n VPMAXSD ymm1 {k1}{z}, ymm2, AVX512F and ymm3/m256/m32bcst and store packed\r\n ymm3/m256/m32bcst maximum values in ymm1 using writemask k1.\r\n EVEX.NDS.512.66.0F38.W0 3D /r FV V/V AVX512F Compare packed signed dword integers in zmm2 and\r\n VPMAXSD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst and store packed maximum\r\n zmm3/m512/m32bcst values in zmm1 using writemask k1.\r\n EVEX.NDS.128.66.0F38.W1 3D /r FV V/V AVX512VL Compare packed signed qword integers in xmm2\r\n VPMAXSQ xmm1 {k1}{z}, xmm2, AVX512F and xmm3/m128/m64bcst and store packed\r\n xmm3/m128/m64bcst maximum values in xmm1 using writemask k1.\r\n EVEX.NDS.256.66.0F38.W1 3D /r FV V/V AVX512VL Compare packed signed qword integers in ymm2\r\n VPMAXSQ ymm1 {k1}{z}, ymm2, AVX512F and ymm3/m256/m64bcst and store packed\r\n ymm3/m256/m64bcst maximum values in ymm1 using writemask k1.\r\n EVEX.NDS.512.66.0F38.W1 3D /r FV V/V AVX512F Compare packed signed qword integers in zmm2 and\r\n VPMAXSQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst and store packed maximum\r\n zmm3/m512/m64bcst values in zmm1 using writemask k1.\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a SIMD compare of the packed signed byte, word, dword or qword integers in the second source operand\r\nand the first source operand and returns the maximum value for each pair of integers to the destination operand.\r\nLegacy SSE version PMAXSW: The source operand can be an MMX technology register or a 64-bit memory location.\r\nThe destination operand can be an MMX technology register.\r\n128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding YMM destina-\r\ntion register remain unchanged.\r\nVEX.128 encoded version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination\r\nregister are zeroed.\r\nVEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The\r\nfirst source and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding destination\r\nregister are zeroed.\r\nEVEX encoded VPMAXSD/Q: The first source operand is a ZMM/YMM/XMM register; The second source operand is\r\na ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a\r\n32/64-bit memory location. The destination operand is conditionally updated based on writemask k1.\r\nEVEX encoded VPMAXSB/W: The first source operand is a ZMM/YMM/XMM register; The second source operand is\r\na ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand is conditionally updated\r\nbased on writemask k1.\r\n\r\nOperation\r\nPMAXSW (64-bit operands)\r\n IF DEST[15:0] > SRC[15:0]) THEN\r\n DEST[15:0] <- DEST[15:0];\r\n\r\n\r\n\r\n ELSE\r\n DEST[15:0] <- SRC[15:0]; FI;\r\n (* Repeat operation for 2nd and 3rd words in source and destination operands *)\r\n IF DEST[63:48] > SRC[63:48]) THEN\r\n DEST[63:48] <- DEST[63:48];\r\n ELSE\r\n DEST[63:48] <- SRC[63:48]; FI;\r\n\r\nPMAXSB (128-bit Legacy SSE version)\r\n IF DEST[7:0] >SRC[7:0] THEN\r\n DEST[7:0] <-DEST[7:0];\r\n ELSE\r\n DEST[7:0] <-SRC[7:0]; FI;\r\n (* Repeat operation for 2nd through 15th bytes in source and destination operands *)\r\n IF DEST[127:120] >SRC[127:120] THEN\r\n DEST[127:120] <-DEST[127:120];\r\n ELSE\r\n DEST[127:120] <-SRC[127:120]; FI;\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVPMAXSB (VEX.128 encoded version)\r\n IF SRC1[7:0] >SRC2[7:0] THEN\r\n DEST[7:0] <-SRC1[7:0];\r\n ELSE\r\n DEST[7:0] <-SRC2[7:0]; FI;\r\n (* Repeat operation for 2nd through 15th bytes in source and destination operands *)\r\n IF SRC1[127:120] >SRC2[127:120] THEN\r\n DEST[127:120] <-SRC1[127:120];\r\n ELSE\r\n DEST[127:120] <-SRC2[127:120]; FI;\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVPMAXSB (VEX.256 encoded version)\r\n IF SRC1[7:0] >SRC2[7:0] THEN\r\n DEST[7:0] <-SRC1[7:0];\r\n ELSE\r\n DEST[7:0] <-SRC2[7:0]; FI;\r\n (* Repeat operation for 2nd through 31st bytes in source and destination operands *)\r\n IF SRC1[255:248] >SRC2[255:248] THEN\r\n DEST[255:248] <-SRC1[255:248];\r\n ELSE\r\n DEST[255:248] <-SRC2[255:248]; FI;\r\nDEST[MAX_VL-1:256] <-0\r\n\r\nVPMAXSB (EVEX encoded versions)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\nFOR j <- 0 TO KL-1\r\n i<-j*8\r\n IF k1[j] OR *no writemask* THEN\r\n IF SRC1[i+7:i] > SRC2[i+7:i]\r\n THEN DEST[i+7:i] <- SRC1[i+7:i];\r\n ELSE DEST[i+7:i] <- SRC2[i+7:i];\r\n FI;\r\n ELSE\r\n\r\n\r\n\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+7:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nPMAXSW (128-bit Legacy SSE version)\r\n IF DEST[15:0] >SRC[15:0] THEN\r\n DEST[15:0] <-DEST[15:0];\r\n ELSE\r\n DEST[15:0] <-SRC[15:0]; FI;\r\n (* Repeat operation for 2nd through 7th words in source and destination operands *)\r\n IF DEST[127:112] >SRC[127:112] THEN\r\n DEST[127:112] <-DEST[127:112];\r\n ELSE\r\n DEST[127:112] <-SRC[127:112]; FI;\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVPMAXSW (VEX.128 encoded version)\r\n IF SRC1[15:0] > SRC2[15:0] THEN\r\n DEST[15:0] <-SRC1[15:0];\r\n ELSE\r\n DEST[15:0] <-SRC2[15:0]; FI;\r\n (* Repeat operation for 2nd through 7th words in source and destination operands *)\r\n IF SRC1[127:112] >SRC2[127:112] THEN\r\n DEST[127:112] <-SRC1[127:112];\r\n ELSE\r\n DEST[127:112] <-SRC2[127:112]; FI;\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVPMAXSW (VEX.256 encoded version)\r\n IF SRC1[15:0] > SRC2[15:0] THEN\r\n DEST[15:0] <-SRC1[15:0];\r\n ELSE\r\n DEST[15:0] <-SRC2[15:0]; FI;\r\n (* Repeat operation for 2nd through 15th words in source and destination operands *)\r\n IF SRC1[255:240] >SRC2[255:240] THEN\r\n DEST[255:240] <-SRC1[255:240];\r\n ELSE\r\n DEST[255:240] <-SRC2[255:240]; FI;\r\nDEST[MAX_VL-1:256] <-0\r\nVPMAXSW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask* THEN\r\n IF SRC1[i+15:i] > SRC2[i+15:i]\r\n THEN DEST[i+15:i] <- SRC1[i+15:i];\r\n ELSE DEST[i+15:i] <- SRC2[i+15:i];\r\n FI;\r\n ELSE\r\n\r\n\r\n\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nPMAXSD (128-bit Legacy SSE version)\r\n IF DEST[31:0] >SRC[31:0] THEN\r\n DEST[31:0] <-DEST[31:0];\r\n ELSE\r\n DEST[31:0] <-SRC[31:0]; FI;\r\n (* Repeat operation for 2nd through 7th words in source and destination operands *)\r\n IF DEST[127:96] >SRC[127:96] THEN\r\n DEST[127:96] <-DEST[127:96];\r\n ELSE\r\n DEST[127:96] <-SRC[127:96]; FI;\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVPMAXSD (VEX.128 encoded version)\r\n IF SRC1[31:0] > SRC2[31:0] THEN\r\n DEST[31:0] <-SRC1[31:0];\r\n ELSE\r\n DEST[31:0] <-SRC2[31:0]; FI;\r\n (* Repeat operation for 2nd through 3rd dwords in source and destination operands *)\r\n IF SRC1[127:96] > SRC2[127:96] THEN\r\n DEST[127:96] <-SRC1[127:96];\r\n ELSE\r\n DEST[127:96] <-SRC2[127:96]; FI;\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVPMAXSD (VEX.256 encoded version)\r\n IF SRC1[31:0] > SRC2[31:0] THEN\r\n DEST[31:0] <-SRC1[31:0];\r\n ELSE\r\n DEST[31:0] <-SRC2[31:0]; FI;\r\n (* Repeat operation for 2nd through 7th dwords in source and destination operands *)\r\n IF SRC1[255:224] > SRC2[255:224] THEN\r\n DEST[255:224] <-SRC1[255:224];\r\n ELSE\r\n DEST[255:224] <-SRC2[255:224]; FI;\r\nDEST[MAX_VL-1:256] <-0\r\n\r\nVPMAXSD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN\r\n IF SRC1[i+31:i] > SRC2[31:0]\r\n THEN DEST[i+31:i] <- SRC1[i+31:i];\r\n\r\n\r\n\r\n ELSE DEST[i+31:i] <- SRC2[31:0];\r\n FI;\r\n ELSE\r\n IF SRC1[i+31:i] > SRC2[i+31:i]\r\n THEN DEST[i+31:i] <- SRC1[i+31:i];\r\n ELSE DEST[i+31:i] <- SRC2[i+31:i];\r\n FI;\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE DEST[i+31:i] <- 0 ; zeroing-masking\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPMAXSQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN\r\n IF SRC1[i+63:i] > SRC2[63:0]\r\n THEN DEST[i+63:i] <- SRC1[i+63:i];\r\n ELSE DEST[i+63:i] <- SRC2[63:0];\r\n FI;\r\n ELSE\r\n IF SRC1[i+63:i] > SRC2[i+63:i]\r\n THEN DEST[i+63:i] <- SRC1[i+63:i];\r\n ELSE DEST[i+63:i] <- SRC2[i+63:i];\r\n FI;\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPMAXSB __m512i _mm512_max_epi8( __m512i a, __m512i b);\r\nVPMAXSB __m512i _mm512_mask_max_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);\r\nVPMAXSB __m512i _mm512_maskz_max_epi8( __mmask64 k, __m512i a, __m512i b);\r\nVPMAXSW __m512i _mm512_max_epi16( __m512i a, __m512i b);\r\nVPMAXSW __m512i _mm512_mask_max_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);\r\nVPMAXSW __m512i _mm512_maskz_max_epi16( __mmask32 k, __m512i a, __m512i b);\r\nVPMAXSB __m256i _mm256_mask_max_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);\r\nVPMAXSB __m256i _mm256_maskz_max_epi8( __mmask32 k, __m256i a, __m256i b);\r\nVPMAXSW __m256i _mm256_mask_max_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);\r\n\r\n\r\n\r\nVPMAXSW __m256i _mm256_maskz_max_epi16( __mmask16 k, __m256i a, __m256i b);\r\nVPMAXSB __m128i _mm_mask_max_epi8(__m128i s, __mmask16 k, __m128i a, __m128i b);\r\nVPMAXSB __m128i _mm_maskz_max_epi8( __mmask16 k, __m128i a, __m128i b);\r\nVPMAXSW __m128i _mm_mask_max_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPMAXSW __m128i _mm_maskz_max_epi16( __mmask8 k, __m128i a, __m128i b);\r\nVPMAXSD __m256i _mm256_mask_max_epi32(__m256i s, __mmask16 k, __m256i a, __m256i b);\r\nVPMAXSD __m256i _mm256_maskz_max_epi32( __mmask16 k, __m256i a, __m256i b);\r\nVPMAXSQ __m256i _mm256_mask_max_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);\r\nVPMAXSQ __m256i _mm256_maskz_max_epi64( __mmask8 k, __m256i a, __m256i b);\r\nVPMAXSD __m128i _mm_mask_max_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPMAXSD __m128i _mm_maskz_max_epi32( __mmask8 k, __m128i a, __m128i b);\r\nVPMAXSQ __m128i _mm_mask_max_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPMAXSQ __m128i _mm_maskz_max_epu64( __mmask8 k, __m128i a, __m128i b);\r\nVPMAXSD __m512i _mm512_max_epi32( __m512i a, __m512i b);\r\nVPMAXSD __m512i _mm512_mask_max_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);\r\nVPMAXSD __m512i _mm512_maskz_max_epi32( __mmask16 k, __m512i a, __m512i b);\r\nVPMAXSQ __m512i _mm512_max_epi64( __m512i a, __m512i b);\r\nVPMAXSQ __m512i _mm512_mask_max_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);\r\nVPMAXSQ __m512i _mm512_maskz_max_epi64( __mmask8 k, __m512i a, __m512i b);\r\n(V)PMAXSB __m128i _mm_max_epi8 ( __m128i a, __m128i b);\r\n(V)PMAXSW __m128i _mm_max_epi16 ( __m128i a, __m128i b)\r\n(V)PMAXSD __m128i _mm_max_epi32 ( __m128i a, __m128i b);\r\nVPMAXSB __m256i _mm256_max_epi8 ( __m256i a, __m256i b);\r\nVPMAXSW __m256i _mm256_max_epi16 ( __m256i a, __m256i b)\r\nVPMAXSD __m256i _mm256_max_epi32 ( __m256i a, __m256i b);\r\nPMAXSW:__m64 _mm_max_pi16(__m64 a, __m64 b)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded VPMAXSD/Q, see Exceptions Type E4.\r\nEVEX-encoded VPMAXSB/W, see Exceptions Type E4.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PMAXSB"
},
{
"description": "-R:PMAXSB",
"mnem": "PMAXSD"
},
{
"description": "-R:PMAXSB",
"mnem": "PMAXSQ"
},
{
"description": "-R:PMAXSB",
"mnem": "PMAXSW"
},
{
"description": "PMAXUB/PMAXUW-Maximum of Packed Unsigned Integers\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 0F DE /r1 RM V/V SSE Compare unsigned byte integers in mm2/m64 and\r\n PMAXUB mm1, mm2/m64 mm1 and returns maximum values.\r\n 66 0F DE /r RM V/V SSE2 Compare packed unsigned byte integers in xmm1\r\n PMAXUB xmm1, xmm2/m128 and xmm2/m128 and store packed maximum\r\n values in xmm1.\r\n 66 0F 38 3E/r RM V/V SSE4_1 Compare packed unsigned word integers in\r\n PMAXUW xmm1, xmm2/m128 xmm2/m128 and xmm1 and stores maximum\r\n packed values in xmm1.\r\n VEX.NDS.128.66.0F DE /r RVM V/V AVX Compare packed unsigned byte integers in xmm2\r\n VPMAXUB xmm1, xmm2, xmm3/m128 and xmm3/m128 and store packed maximum\r\n values in xmm1.\r\n VEX.NDS.128.66.0F38 3E/r RVM V/V AVX Compare packed unsigned word integers in\r\n VPMAXUW xmm1, xmm2, xmm3/m128 xmm3/m128 and xmm2 and store maximum\r\n packed values in xmm1.\r\n VEX.NDS.256.66.0F DE /r RVM V/V AVX2 Compare packed unsigned byte integers in ymm2\r\n VPMAXUB ymm1, ymm2, ymm3/m256 and ymm3/m256 and store packed maximum\r\n values in ymm1.\r\n VEX.NDS.256.66.0F38 3E/r RVM V/V AVX2 Compare packed unsigned word integers in\r\n VPMAXUW ymm1, ymm2, ymm3/m256 ymm3/m256 and ymm2 and store maximum\r\n packed values in ymm1.\r\n EVEX.NDS.128.66.0F.WIG DE /r FVM V/V AVX512VL Compare packed unsigned byte integers in xmm2\r\n VPMAXUB xmm1{k1}{z}, xmm2, AVX512BW and xmm3/m128 and store packed maximum\r\n xmm3/m128 values in xmm1 under writemask k1.\r\n EVEX.NDS.256.66.0F.WIG DE /r FVM V/V AVX512VL Compare packed unsigned byte integers in ymm2\r\n VPMAXUB ymm1{k1}{z}, ymm2, AVX512BW and ymm3/m256 and store packed maximum\r\n ymm3/m256 values in ymm1 under writemask k1.\r\n EVEX.NDS.512.66.0F.WIG DE /r FVM V/V AVX512BW Compare packed unsigned byte integers in zmm2\r\n VPMAXUB zmm1{k1}{z}, zmm2, and zmm3/m512 and store packed maximum\r\n zmm3/m512 values in zmm1 under writemask k1.\r\n EVEX.NDS.128.66.0F38.WIG 3E /r FVM V/V AVX512VL Compare packed unsigned word integers in xmm2\r\n VPMAXUW xmm1{k1}{z}, xmm2, AVX512BW and xmm3/m128 and store packed maximum\r\n xmm3/m128 values in xmm1 under writemask k1.\r\n EVEX.NDS.256.66.0F38.WIG 3E /r FVM V/V AVX512VL Compare packed unsigned word integers in ymm2\r\n VPMAXUW ymm1{k1}{z}, ymm2, AVX512BW and ymm3/m256 and store packed maximum\r\n ymm3/m256 values in ymm1 under writemask k1.\r\n EVEX.NDS.512.66.0F38.WIG 3E /r FVM V/V AVX512BW Compare packed unsigned word integers in zmm2\r\n VPMAXUW zmm1{k1}{z}, zmm2, and zmm3/m512 and store packed maximum\r\n zmm3/m512 values in zmm1 under writemask k1.\r\n NOTES:\r\n 1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\n Developer's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX\r\n Registers\" in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\n\r\n\r\nDescription\r\nPerforms a SIMD compare of the packed unsigned byte, word integers in the second source operand and the first\r\nsource operand and returns the maximum value for each pair of integers to the destination operand.\r\nLegacy SSE version PMAXUB: The source operand can be an MMX technology register or a 64-bit memory location.\r\nThe destination operand can be an MMX technology register.\r\n128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination\r\nregister remain unchanged.\r\nVEX.128 encoded version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination\r\nregister are zeroed.\r\nVEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The\r\nfirst source and destination operands are YMM registers.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register; The second source operand is a\r\nZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand is conditionally updated\r\nbased on writemask k1.\r\n\r\nOperation\r\nPMAXUB (64-bit operands)\r\n IF DEST[7:0] > SRC[17:0]) THEN\r\n DEST[7:0] <- DEST[7:0];\r\n ELSE\r\n DEST[7:0] <- SRC[7:0]; FI;\r\n (* Repeat operation for 2nd through 7th bytes in source and destination operands *)\r\n IF DEST[63:56] > SRC[63:56]) THEN\r\n DEST[63:56] <- DEST[63:56];\r\n ELSE\r\n DEST[63:56] <- SRC[63:56]; FI;\r\n\r\nPMAXUB (128-bit Legacy SSE version)\r\n IF DEST[7:0] >SRC[7:0] THEN\r\n DEST[7:0] <- DEST[7:0];\r\n ELSE\r\n DEST[15:0] <- SRC[7:0]; FI;\r\n (* Repeat operation for 2nd through 15th bytes in source and destination operands *)\r\n IF DEST[127:120] >SRC[127:120] THEN\r\n DEST[127:120] <- DEST[127:120];\r\n ELSE\r\n DEST[127:120] <- SRC[127:120]; FI;\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVPMAXUB (VEX.128 encoded version)\r\n IF SRC1[7:0] >SRC2[7:0] THEN\r\n DEST[7:0] <- SRC1[7:0];\r\n ELSE\r\n DEST[7:0] <- SRC2[7:0]; FI;\r\n (* Repeat operation for 2nd through 15th bytes in source and destination operands *)\r\n IF SRC1[127:120] >SRC2[127:120] THEN\r\n DEST[127:120] <- SRC1[127:120];\r\n ELSE\r\n DEST[127:120] <- SRC2[127:120]; FI;\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\nVPMAXUB (VEX.256 encoded version)\r\n IF SRC1[7:0] >SRC2[7:0] THEN\r\n DEST[7:0] <- SRC1[7:0];\r\n ELSE\r\n DEST[15:0] <- SRC2[7:0]; FI;\r\n (* Repeat operation for 2nd through 31st bytes in source and destination operands *)\r\n IF SRC1[255:248] >SRC2[255:248] THEN\r\n DEST[255:248] <- SRC1[255:248];\r\n ELSE\r\n DEST[255:248] <- SRC2[255:248]; FI;\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVPMAXUB (EVEX encoded versions)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\nFOR j <- 0 TO KL-1\r\n i<-j*8\r\n IF k1[j] OR *no writemask* THEN\r\n IF SRC1[i+7:i] > SRC2[i+7:i]\r\n THEN DEST[i+7:i] <- SRC1[i+7:i];\r\n ELSE DEST[i+7:i] <- SRC2[i+7:i];\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+7:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nPMAXUW (128-bit Legacy SSE version)\r\n IF DEST[15:0] >SRC[15:0] THEN\r\n DEST[15:0] <- DEST[15:0];\r\n ELSE\r\n DEST[15:0] <- SRC[15:0]; FI;\r\n (* Repeat operation for 2nd through 7th words in source and destination operands *)\r\n IF DEST[127:112] >SRC[127:112] THEN\r\n DEST[127:112] <- DEST[127:112];\r\n ELSE\r\n DEST[127:112] <- SRC[127:112]; FI;\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVPMAXUW (VEX.128 encoded version)\r\n IF SRC1[15:0] > SRC2[15:0] THEN\r\n DEST[15:0] <- SRC1[15:0];\r\n ELSE\r\n DEST[15:0] <- SRC2[15:0]; FI;\r\n (* Repeat operation for 2nd through 7th words in source and destination operands *)\r\n IF SRC1[127:112] >SRC2[127:112] THEN\r\n DEST[127:112] <- SRC1[127:112];\r\n ELSE\r\n DEST[127:112] <- SRC2[127:112]; FI;\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\nVPMAXUW (VEX.256 encoded version)\r\n IF SRC1[15:0] > SRC2[15:0] THEN\r\n DEST[15:0] <- SRC1[15:0];\r\n ELSE\r\n DEST[15:0] <- SRC2[15:0]; FI;\r\n (* Repeat operation for 2nd through 15th words in source and destination operands *)\r\n IF SRC1[255:240] >SRC2[255:240] THEN\r\n DEST[255:240] <- SRC1[255:240];\r\n ELSE\r\n DEST[255:240] <- SRC2[255:240]; FI;\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVPMAXUW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask* THEN\r\n IF SRC1[i+15:i] > SRC2[i+15:i]\r\n THEN DEST[i+15:i] <- SRC1[i+15:i];\r\n ELSE DEST[i+15:i] <- SRC2[i+15:i];\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPMAXUB __m512i _mm512_max_epu8( __m512i a, __m512i b);\r\nVPMAXUB __m512i _mm512_mask_max_epu8(__m512i s, __mmask64 k, __m512i a, __m512i b);\r\nVPMAXUB __m512i _mm512_maskz_max_epu8( __mmask64 k, __m512i a, __m512i b);\r\nVPMAXUW __m512i _mm512_max_epu16( __m512i a, __m512i b);\r\nVPMAXUW __m512i _mm512_mask_max_epu16(__m512i s, __mmask32 k, __m512i a, __m512i b);\r\nVPMAXUW __m512i _mm512_maskz_max_epu16( __mmask32 k, __m512i a, __m512i b);\r\nVPMAXUB __m256i _mm256_mask_max_epu8(__m256i s, __mmask32 k, __m256i a, __m256i b);\r\nVPMAXUB __m256i _mm256_maskz_max_epu8( __mmask32 k, __m256i a, __m256i b);\r\nVPMAXUW __m256i _mm256_mask_max_epu16(__m256i s, __mmask16 k, __m256i a, __m256i b);\r\nVPMAXUW __m256i _mm256_maskz_max_epu16( __mmask16 k, __m256i a, __m256i b);\r\nVPMAXUB __m128i _mm_mask_max_epu8(__m128i s, __mmask16 k, __m128i a, __m128i b);\r\nVPMAXUB __m128i _mm_maskz_max_epu8( __mmask16 k, __m128i a, __m128i b);\r\nVPMAXUW __m128i _mm_mask_max_epu16(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPMAXUW __m128i _mm_maskz_max_epu16( __mmask8 k, __m128i a, __m128i b);\r\n(V)PMAXUB __m128i _mm_max_epu8 ( __m128i a, __m128i b);\r\n(V)PMAXUW __m128i _mm_max_epu16 ( __m128i a, __m128i b)\r\nVPMAXUB __m256i _mm256_max_epu8 ( __m256i a, __m256i b);\r\nVPMAXUW __m256i _mm256_max_epu16 ( __m256i a, __m256i b);\r\nPMAXUB: __m64 _mm_max_pu8(__m64 a, __m64 b);\r\n\r\n\r\n\r\n\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PMAXUB"
},
{
"description": "PMAXUD/PMAXUQ-Maximum of Packed Unsigned Integers\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0F 38 3F /r RM V/V SSE4_1 Compare packed unsigned dword integers in xmm1\r\n PMAXUD xmm1, xmm2/m128 and xmm2/m128 and store packed maximum values in\r\n xmm1.\r\n VEX.NDS.128.66.0F38.WIG 3F /r RVM V/V AVX Compare packed unsigned dword integers in xmm2\r\n VPMAXUD xmm1, xmm2, xmm3/m128 and xmm3/m128 and store packed maximum values in\r\n xmm1.\r\n VEX.NDS.256.66.0F38.WIG 3F /r RVM V/V AVX2 Compare packed unsigned dword integers in ymm2\r\n VPMAXUD ymm1, ymm2, ymm3/m256 and ymm3/m256 and store packed maximum values in\r\n ymm1.\r\n EVEX.NDS.128.66.0F38.W0 3F /r FV V/V AVX512VL Compare packed unsigned dword integers in xmm2\r\n VPMAXUD xmm1 {k1}{z}, xmm2, AVX512F and xmm3/m128/m32bcst and store packed\r\n xmm3/m128/m32bcst maximum values in xmm1 under writemask k1.\r\n EVEX.NDS.256.66.0F38.W0 3F /r FV V/V AVX512VL Compare packed unsigned dword integers in ymm2\r\n VPMAXUD ymm1 {k1}{z}, ymm2, AVX512F and ymm3/m256/m32bcst and store packed\r\n ymm3/m256/m32bcst maximum values in ymm1 under writemask k1.\r\n EVEX.NDS.512.66.0F38.W0 3F /r FV V/V AVX512F Compare packed unsigned dword integers in zmm2\r\n VPMAXUD zmm1 {k1}{z}, zmm2, and zmm3/m512/m32bcst and store packed maximum\r\n zmm3/m512/m32bcst values in zmm1 under writemask k1.\r\n EVEX.NDS.128.66.0F38.W1 3F /r FV V/V AVX512VL Compare packed unsigned qword integers in xmm2\r\n VPMAXUQ xmm1 {k1}{z}, xmm2, AVX512F and xmm3/m128/m64bcst and store packed\r\n xmm3/m128/m64bcst maximum values in xmm1 under writemask k1.\r\n EVEX.NDS.256.66.0F38.W1 3F /r FV V/V AVX512VL Compare packed unsigned qword integers in ymm2\r\n VPMAXUQ ymm1 {k1}{z}, ymm2, AVX512F and ymm3/m256/m64bcst and store packed\r\n ymm3/m256/m64bcst maximum values in ymm1 under writemask k1.\r\n EVEX.NDS.512.66.0F38.W1 3F /r FV V/V AVX512F Compare packed unsigned qword integers in zmm2\r\n VPMAXUQ zmm1 {k1}{z}, zmm2, and zmm3/m512/m64bcst and store packed maximum\r\n zmm3/m512/m64bcst values in zmm1 under writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a SIMD compare of the packed unsigned dword or qword integers in the second source operand and the\r\nfirst source operand and returns the maximum value for each pair of integers to the destination operand.\r\n128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination\r\nregister remain unchanged.\r\nVEX.128 encoded version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination\r\nregister are zeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register; The second source operand is a YMM register\r\nor 256-bit memory location. Bits (MAX_VL-1:256) of the corresponding destination register are zeroed.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register; The second source operand is a\r\nZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a\r\n32/64-bit memory location. The destination operand is conditionally updated based on writemask k1.\r\n\r\n\r\n\r\nOperation\r\nPMAXUD (128-bit Legacy SSE version)\r\n IF DEST[31:0] >SRC[31:0] THEN\r\n DEST[31:0] <- DEST[31:0];\r\n ELSE\r\n DEST[31:0] <- SRC[31:0]; FI;\r\n (* Repeat operation for 2nd through 7th words in source and destination operands *)\r\n IF DEST[127:96] >SRC[127:96] THEN\r\n DEST[127:96] <- DEST[127:96];\r\n ELSE\r\n DEST[127:96] <- SRC[127:96]; FI;\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVPMAXUD (VEX.128 encoded version)\r\n IF SRC1[31:0] > SRC2[31:0] THEN\r\n DEST[31:0] <- SRC1[31:0];\r\n ELSE\r\n DEST[31:0] <- SRC2[31:0]; FI;\r\n (* Repeat operation for 2nd through 3rd dwords in source and destination operands *)\r\n IF SRC1[127:96] > SRC2[127:96] THEN\r\n DEST[127:96] <- SRC1[127:96];\r\n ELSE\r\n DEST[127:96] <- SRC2[127:96]; FI;\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVPMAXUD (VEX.256 encoded version)\r\n IF SRC1[31:0] > SRC2[31:0] THEN\r\n DEST[31:0] <- SRC1[31:0];\r\n ELSE\r\n DEST[31:0] <- SRC2[31:0]; FI;\r\n (* Repeat operation for 2nd through 7th dwords in source and destination operands *)\r\n IF SRC1[255:224] > SRC2[255:224] THEN\r\n DEST[255:224] <- SRC1[255:224];\r\n ELSE\r\n DEST[255:224] <- SRC2[255:224]; FI;\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVPMAXUD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN\r\n IF SRC1[i+31:i] > SRC2[31:0]\r\n THEN DEST[i+31:i] <- SRC1[i+31:i];\r\n ELSE DEST[i+31:i] <- SRC2[31:0];\r\n FI;\r\n ELSE\r\n IF SRC1[i+31:i] > SRC2[i+31:i]\r\n THEN DEST[i+31:i] <- SRC1[i+31:i];\r\n ELSE DEST[i+31:i] <- SRC2[i+31:i];\r\n FI;\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPMAXUQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN\r\n IF SRC1[i+63:i] > SRC2[63:0]\r\n THEN DEST[i+63:i] <- SRC1[i+63:i];\r\n ELSE DEST[i+63:i] <- SRC2[63:0];\r\n FI;\r\n ELSE\r\n IF SRC1[i+31:i] > SRC2[i+31:i]\r\n THEN DEST[i+63:i] <- SRC1[i+63:i];\r\n ELSE DEST[i+63:i] <- SRC2[i+63:i];\r\n FI;\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPMAXUD __m512i _mm512_max_epu32( __m512i a, __m512i b);\r\nVPMAXUD __m512i _mm512_mask_max_epu32(__m512i s, __mmask16 k, __m512i a, __m512i b);\r\nVPMAXUD __m512i _mm512_maskz_max_epu32( __mmask16 k, __m512i a, __m512i b);\r\nVPMAXUQ __m512i _mm512_max_epu64( __m512i a, __m512i b);\r\nVPMAXUQ __m512i _mm512_mask_max_epu64(__m512i s, __mmask8 k, __m512i a, __m512i b);\r\nVPMAXUQ __m512i _mm512_maskz_max_epu64( __mmask8 k, __m512i a, __m512i b);\r\nVPMAXUD __m256i _mm256_mask_max_epu32(__m256i s, __mmask16 k, __m256i a, __m256i b);\r\nVPMAXUD __m256i _mm256_maskz_max_epu32( __mmask16 k, __m256i a, __m256i b);\r\nVPMAXUQ __m256i _mm256_mask_max_epu64(__m256i s, __mmask8 k, __m256i a, __m256i b);\r\nVPMAXUQ __m256i _mm256_maskz_max_epu64( __mmask8 k, __m256i a, __m256i b);\r\nVPMAXUD __m128i _mm_mask_max_epu32(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPMAXUD __m128i _mm_maskz_max_epu32( __mmask8 k, __m128i a, __m128i b);\r\nVPMAXUQ __m128i _mm_mask_max_epu64(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPMAXUQ __m128i _mm_maskz_max_epu64( __mmask8 k, __m128i a, __m128i b);\r\n(V)PMAXUD __m128i _mm_max_epu32 ( __m128i a, __m128i b);\r\nVPMAXUD __m256i _mm256_max_epu32 ( __m256i a, __m256i b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PMAXUD"
},
{
"description": "-R:PMAXUD",
"mnem": "PMAXUQ"
},
{
"description": "-R:PMAXUB",
"mnem": "PMAXUW"
},
{
"description": "PMINSB/PMINSW-Minimum of Packed Signed Integers\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 0F EA /r1 RM V/V SSE Compare signed word integers in mm2/m64 and mm1\r\n PMINSW mm1, mm2/m64 and return minimum values.\r\n 66 0F 38 38 /r RM V/V SSE4_1 Compare packed signed byte integers in xmm1 and\r\n PMINSB xmm1, xmm2/m128 xmm2/m128 and store packed minimum values in\r\n xmm1.\r\n 66 0F EA /r RM V/V SSE2 Compare packed signed word integers in xmm2/m128\r\n PMINSW xmm1, xmm2/m128 and xmm1 and store packed minimum values in xmm1.\r\n VEX.NDS.128.66.0F38 38 /r RVM V/V AVX Compare packed signed byte integers in xmm2 and\r\n VPMINSB xmm1, xmm2, xmm3/m128 xmm3/m128 and store packed minimum values in\r\n xmm1.\r\n VEX.NDS.128.66.0F EA /r RVM V/V AVX Compare packed signed word integers in xmm3/m128\r\n VPMINSW xmm1, xmm2, xmm3/m128 and xmm2 and return packed minimum values in\r\n xmm1.\r\n VEX.NDS.256.66.0F38 38 /r RVM V/V AVX2 Compare packed signed byte integers in ymm2 and\r\n VPMINSB ymm1, ymm2, ymm3/m256 ymm3/m256 and store packed minimum values in\r\n ymm1.\r\n VEX.NDS.256.66.0F EA /r RVM V/V AVX2 Compare packed signed word integers in ymm3/m256\r\n VPMINSW ymm1, ymm2, ymm3/m256 and ymm2 and return packed minimum values in\r\n ymm1.\r\n EVEX.NDS.128.66.0F38.WIG 38 /r FVM V/V AVX512VL Compare packed signed byte integers in xmm2 and\r\n VPMINSB xmm1{k1}{z}, xmm2, AVX512BW xmm3/m128 and store packed minimum values in\r\n xmm3/m128 xmm1 under writemask k1.\r\n EVEX.NDS.256.66.0F38.WIG 38 /r FVM V/V AVX512VL Compare packed signed byte integers in ymm2 and\r\n VPMINSB ymm1{k1}{z}, ymm2, AVX512BW ymm3/m256 and store packed minimum values in\r\n ymm3/m256 ymm1 under writemask k1.\r\n EVEX.NDS.512.66.0F38.WIG 38 /r FVM V/V AVX512BW Compare packed signed byte integers in zmm2 and\r\n VPMINSB zmm1{k1}{z}, zmm2, zmm3/m512 and store packed minimum values in\r\n zmm3/m512 zmm1 under writemask k1.\r\n EVEX.NDS.128.66.0F.WIG EA /r FVM V/V AVX512VL Compare packed signed word integers in xmm2 and\r\n VPMINSW xmm1{k1}{z}, xmm2, AVX512BW xmm3/m128 and store packed minimum values in\r\n xmm3/m128 xmm1 under writemask k1.\r\n EVEX.NDS.256.66.0F.WIG EA /r FVM V/V AVX512VL Compare packed signed word integers in ymm2 and\r\n VPMINSW ymm1{k1}{z}, ymm2, AVX512BW ymm3/m256 and store packed minimum values in\r\n ymm3/m256 ymm1 under writemask k1.\r\n EVEX.NDS.512.66.0F.WIG EA /r FVM V/V AVX512BW Compare packed signed word integers in zmm2 and\r\n VPMINSW zmm1{k1}{z}, zmm2, zmm3/m512 and store packed minimum values in\r\n zmm3/m512 zmm1 under writemask k1.\r\n NOTES:\r\n 1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\n Developer's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX\r\n Registers\" in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\n\r\n\r\n\r\nDescription\r\nPerforms a SIMD compare of the packed signed byte, word, or dword integers in the second source operand and\r\nthe first source operand and returns the minimum value for each pair of integers to the destination operand.\r\nLegacy SSE version PMINSW: The source operand can be an MMX technology register or a 64-bit memory location.\r\nThe destination operand can be an MMX technology register.\r\n128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination\r\nregister remain unchanged.\r\nVEX.128 encoded version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination\r\nregister are zeroed.\r\nVEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The\r\nfirst source and destination operands are YMM registers.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register; The second source operand is a\r\nZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand is conditionally updated\r\nbased on writemask k1.\r\n\r\nOperation\r\nPMINSW (64-bit operands)\r\n IF DEST[15:0] < SRC[15:0] THEN\r\n DEST[15:0] <- DEST[15:0];\r\n ELSE\r\n DEST[15:0] <- SRC[15:0]; FI;\r\n (* Repeat operation for 2nd and 3rd words in source and destination operands *)\r\n IF DEST[63:48] < SRC[63:48] THEN\r\n DEST[63:48] <- DEST[63:48];\r\n ELSE\r\n DEST[63:48] <- SRC[63:48]; FI;\r\n\r\nPMINSB (128-bit Legacy SSE version)\r\n IF DEST[7:0] < SRC[7:0] THEN\r\n DEST[7:0] <- DEST[7:0];\r\n ELSE\r\n DEST[15:0] <- SRC[7:0]; FI;\r\n (* Repeat operation for 2nd through 15th bytes in source and destination operands *)\r\n IF DEST[127:120] < SRC[127:120] THEN\r\n DEST[127:120] <- DEST[127:120];\r\n ELSE\r\n DEST[127:120] <- SRC[127:120]; FI;\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVPMINSB (VEX.128 encoded version)\r\n IF SRC1[7:0] < SRC2[7:0] THEN\r\n DEST[7:0] <- SRC1[7:0];\r\n ELSE\r\n DEST[7:0] <- SRC2[7:0]; FI;\r\n (* Repeat operation for 2nd through 15th bytes in source and destination operands *)\r\n IF SRC1[127:120] < SRC2[127:120] THEN\r\n DEST[127:120] <- SRC1[127:120];\r\n ELSE\r\n DEST[127:120] <- SRC2[127:120]; FI;\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\nVPMINSB (VEX.256 encoded version)\r\n IF SRC1[7:0] < SRC2[7:0] THEN\r\n DEST[7:0] <- SRC1[7:0];\r\n ELSE\r\n DEST[15:0] <- SRC2[7:0]; FI;\r\n (* Repeat operation for 2nd through 31st bytes in source and destination operands *)\r\n IF SRC1[255:248] < SRC2[255:248] THEN\r\n DEST[255:248] <- SRC1[255:248];\r\n ELSE\r\n DEST[255:248] <- SRC2[255:248]; FI;\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVPMINSB (EVEX encoded versions)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\nFOR j <- 0 TO KL-1\r\n i<-j*8\r\n IF k1[j] OR *no writemask* THEN\r\n IF SRC1[i+7:i] < SRC2[i+7:i]\r\n THEN DEST[i+7:i] <- SRC1[i+7:i];\r\n ELSE DEST[i+7:i] <- SRC2[i+7:i];\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+7:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nPMINSW (128-bit Legacy SSE version)\r\n IF DEST[15:0] < SRC[15:0] THEN\r\n DEST[15:0] <- DEST[15:0];\r\n ELSE\r\n DEST[15:0] <- SRC[15:0]; FI;\r\n (* Repeat operation for 2nd through 7th words in source and destination operands *)\r\n IF DEST[127:112] < SRC[127:112] THEN\r\n DEST[127:112] <- DEST[127:112];\r\n ELSE\r\n DEST[127:112] <- SRC[127:112]; FI;\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVPMINSW (VEX.128 encoded version)\r\n IF SRC1[15:0] < SRC2[15:0] THEN\r\n DEST[15:0] <- SRC1[15:0];\r\n ELSE\r\n DEST[15:0] <- SRC2[15:0]; FI;\r\n (* Repeat operation for 2nd through 7th words in source and destination operands *)\r\n IF SRC1[127:112] < SRC2[127:112] THEN\r\n DEST[127:112] <- SRC1[127:112];\r\n ELSE\r\n DEST[127:112] <- SRC2[127:112]; FI;\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\nVPMINSW (VEX.256 encoded version)\r\n IF SRC1[15:0] < SRC2[15:0] THEN\r\n DEST[15:0] <- SRC1[15:0];\r\n ELSE\r\n DEST[15:0] <- SRC2[15:0]; FI;\r\n (* Repeat operation for 2nd through 15th words in source and destination operands *)\r\n IF SRC1[255:240] < SRC2[255:240] THEN\r\n DEST[255:240] <- SRC1[255:240];\r\n ELSE\r\n DEST[255:240] <- SRC2[255:240]; FI;\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVPMINSW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask* THEN\r\n IF SRC1[i+15:i] < SRC2[i+15:i]\r\n THEN DEST[i+15:i] <- SRC1[i+15:i];\r\n ELSE DEST[i+15:i] <- SRC2[i+15:i];\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPMINSB __m512i _mm512_min_epi8( __m512i a, __m512i b);\r\nVPMINSB __m512i _mm512_mask_min_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);\r\nVPMINSB __m512i _mm512_maskz_min_epi8( __mmask64 k, __m512i a, __m512i b);\r\nVPMINSW __m512i _mm512_min_epi16( __m512i a, __m512i b);\r\nVPMINSW __m512i _mm512_mask_min_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);\r\nVPMINSW __m512i _mm512_maskz_min_epi16( __mmask32 k, __m512i a, __m512i b);\r\nVPMINSB __m256i _mm256_mask_min_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);\r\nVPMINSB __m256i _mm256_maskz_min_epi8( __mmask32 k, __m256i a, __m256i b);\r\nVPMINSW __m256i _mm256_mask_min_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);\r\nVPMINSW __m256i _mm256_maskz_min_epi16( __mmask16 k, __m256i a, __m256i b);\r\nVPMINSB __m128i _mm_mask_min_epi8(__m128i s, __mmask16 k, __m128i a, __m128i b);\r\nVPMINSB __m128i _mm_maskz_min_epi8( __mmask16 k, __m128i a, __m128i b);\r\nVPMINSW __m128i _mm_mask_min_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPMINSW __m128i _mm_maskz_min_epi16( __mmask8 k, __m128i a, __m128i b);\r\n(V)PMINSB __m128i _mm_min_epi8 ( __m128i a, __m128i b);\r\n(V)PMINSW __m128i _mm_min_epi16 ( __m128i a, __m128i b)\r\nVPMINSB __m256i _mm256_min_epi8 ( __m256i a, __m256i b);\r\nVPMINSW __m256i _mm256_min_epi16 ( __m256i a, __m256i b)\r\nPMINSW:__m64 _mm_min_pi16 (__m64 a, __m64 b)\r\n\r\n\r\n\r\n\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.nb.\r\n#MF (64-bit operations only) If there is a pending x87 FPU exception.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PMINSB"
},
{
"description": "PMINSD/PMINSQ-Minimum of Packed Signed Integers\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0F 38 39 /r RM V/V SSE4_1 Compare packed signed dword integers in xmm1 and\r\n PMINSD xmm1, xmm2/m128 xmm2/m128 and store packed minimum values in\r\n xmm1.\r\n VEX.NDS.128.66.0F38.WIG 39 /r RVM V/V AVX Compare packed signed dword integers in xmm2 and\r\n VPMINSD xmm1, xmm2, xmm3/m128 xmm3/m128 and store packed minimum values in\r\n xmm1.\r\n VEX.NDS.256.66.0F38.WIG 39 /r RVM V/V AVX2 Compare packed signed dword integers in ymm2 and\r\n VPMINSD ymm1, ymm2, ymm3/m256 ymm3/m128 and store packed minimum values in\r\n ymm1.\r\n EVEX.NDS.128.66.0F38.W0 39 /r FV V/V AVX512VL Compare packed signed dword integers in xmm2 and\r\n VPMINSD xmm1 {k1}{z}, xmm2, AVX512F xmm3/m128 and store packed minimum values in\r\n xmm3/m128/m32bcst xmm1 under writemask k1.\r\n EVEX.NDS.256.66.0F38.W0 39 /r FV V/V AVX512VL Compare packed signed dword integers in ymm2 and\r\n VPMINSD ymm1 {k1}{z}, ymm2, AVX512F ymm3/m256 and store packed minimum values in\r\n ymm3/m256/m32bcst ymm1 under writemask k1.\r\n EVEX.NDS.512.66.0F38.W0 39 /r FV V/V AVX512F Compare packed signed dword integers in zmm2 and\r\n VPMINSD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst and store packed minimum\r\n zmm3/m512/m32bcst values in zmm1 under writemask k1.\r\n EVEX.NDS.128.66.0F38.W1 39 /r FV V/V AVX512VL Compare packed signed qword integers in xmm2 and\r\n VPMINSQ xmm1 {k1}{z}, xmm2, AVX512F xmm3/m128 and store packed minimum values in\r\n xmm3/m128/m64bcst xmm1 under writemask k1.\r\n EVEX.NDS.256.66.0F38.W1 39 /r FV V/V AVX512VL Compare packed signed qword integers in ymm2 and\r\n VPMINSQ ymm1 {k1}{z}, ymm2, AVX512F ymm3/m256 and store packed minimum values in\r\n ymm3/m256/m64bcst ymm1 under writemask k1.\r\n EVEX.NDS.512.66.0F38.W1 39 /r FV V/V AVX512F Compare packed signed qword integers in zmm2 and\r\n VPMINSQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst and store packed minimum\r\n zmm3/m512/m64bcst values in zmm1 under writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a SIMD compare of the packed signed dword or qword integers in the second source operand and the first\r\nsource operand and returns the minimum value for each pair of integers to the destination operand.\r\n128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination\r\nregister remain unchanged.\r\nVEX.128 encoded version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination\r\nregister are zeroed.\r\nVEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The\r\nfirst source and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding destination\r\nregister are zeroed.\r\n\r\n\r\n\r\n\r\n\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register; The second source operand is a\r\nZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a\r\n32/64-bit memory location. The destination operand is conditionally updated based on writemask k1.\r\n\r\nOperation\r\nPMINSD (128-bit Legacy SSE version)\r\n IF DEST[31:0] < SRC[31:0] THEN\r\n DEST[31:0] <- DEST[31:0];\r\n ELSE\r\n DEST[31:0] <- SRC[31:0]; FI;\r\n (* Repeat operation for 2nd through 7th words in source and destination operands *)\r\n IF DEST[127:96] < SRC[127:96] THEN\r\n DEST[127:96] <- DEST[127:96];\r\n ELSE\r\n DEST[127:96] <- SRC[127:96]; FI;\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVPMINSD (VEX.128 encoded version)\r\n IF SRC1[31:0] < SRC2[31:0] THEN\r\n DEST[31:0] <- SRC1[31:0];\r\n ELSE\r\n DEST[31:0] <- SRC2[31:0]; FI;\r\n (* Repeat operation for 2nd through 3rd dwords in source and destination operands *)\r\n IF SRC1[127:96] < SRC2[127:96] THEN\r\n DEST[127:96] <- SRC1[127:96];\r\n ELSE\r\n DEST[127:96] <- SRC2[127:96]; FI;\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVPMINSD (VEX.256 encoded version)\r\n IF SRC1[31:0] < SRC2[31:0] THEN\r\n DEST[31:0] <- SRC1[31:0];\r\n ELSE\r\n DEST[31:0] <- SRC2[31:0]; FI;\r\n (* Repeat operation for 2nd through 7th dwords in source and destination operands *)\r\n IF SRC1[255:224] < SRC2[255:224] THEN\r\n DEST[255:224] <- SRC1[255:224];\r\n ELSE\r\n DEST[255:224] <- SRC2[255:224]; FI;\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVPMINSD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN\r\n IF SRC1[i+31:i] < SRC2[31:0]\r\n THEN DEST[i+31:i] <- SRC1[i+31:i];\r\n ELSE DEST[i+31:i] <- SRC2[31:0];\r\n FI;\r\n ELSE\r\n IF SRC1[i+31:i] < SRC2[i+31:i]\r\n THEN DEST[i+31:i] <- SRC1[i+31:i];\r\n ELSE DEST[i+31:i] <- SRC2[i+31:i];\r\n FI;\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPMINSQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN\r\n IF SRC1[i+63:i] < SRC2[63:0]\r\n THEN DEST[i+63:i] <- SRC1[i+63:i];\r\n ELSE DEST[i+63:i] <- SRC2[63:0];\r\n FI;\r\n ELSE\r\n IF SRC1[i+63:i] < SRC2[i+63:i]\r\n THEN DEST[i+63:i] <- SRC1[i+63:i];\r\n ELSE DEST[i+63:i] <- SRC2[i+63:i];\r\n FI;\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPMINSD __m512i _mm512_min_epi32( __m512i a, __m512i b);\r\nVPMINSD __m512i _mm512_mask_min_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);\r\nVPMINSD __m512i _mm512_maskz_min_epi32( __mmask16 k, __m512i a, __m512i b);\r\nVPMINSQ __m512i _mm512_min_epi64( __m512i a, __m512i b);\r\nVPMINSQ __m512i _mm512_mask_min_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);\r\nVPMINSQ __m512i _mm512_maskz_min_epi64( __mmask8 k, __m512i a, __m512i b);\r\nVPMINSD __m256i _mm256_mask_min_epi32(__m256i s, __mmask16 k, __m256i a, __m256i b);\r\nVPMINSD __m256i _mm256_maskz_min_epi32( __mmask16 k, __m256i a, __m256i b);\r\nVPMINSQ __m256i _mm256_mask_min_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);\r\nVPMINSQ __m256i _mm256_maskz_min_epi64( __mmask8 k, __m256i a, __m256i b);\r\nVPMINSD __m128i _mm_mask_min_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPMINSD __m128i _mm_maskz_min_epi32( __mmask8 k, __m128i a, __m128i b);\r\nVPMINSQ __m128i _mm_mask_min_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPMINSQ __m128i _mm_maskz_min_epu64( __mmask8 k, __m128i a, __m128i b);\r\n(V)PMINSD __m128i _mm_min_epi32 ( __m128i a, __m128i b);\r\nVPMINSD __m256i _mm256_min_epi32 (__m256i a, __m256i b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PMINSD"
},
{
"description": "-R:PMINSD",
"mnem": "PMINSQ"
},
{
"description": "-R:PMINSB",
"mnem": "PMINSW"
},
{
"description": "PMINUB/PMINUW-Minimum of Packed Unsigned Integers\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 0F DA /r1 RM V/V SSE Compare unsigned byte integers in mm2/m64 and\r\n PMINUB mm1, mm2/m64 mm1 and returns minimum values.\r\n 66 0F DA /r RM V/V SSE2 Compare packed unsigned byte integers in xmm1\r\n PMINUB xmm1, xmm2/m128 and xmm2/m128 and store packed minimum values\r\n in xmm1.\r\n 66 0F 38 3A/r RM V/V SSE4_1 Compare packed unsigned word integers in\r\n PMINUW xmm1, xmm2/m128 xmm2/m128 and xmm1 and store packed minimum\r\n values in xmm1.\r\n VEX.NDS.128.66.0F DA /r RVM V/V AVX Compare packed unsigned byte integers in xmm2\r\n VPMINUB xmm1, xmm2, xmm3/m128 and xmm3/m128 and store packed minimum values\r\n in xmm1.\r\n VEX.NDS.128.66.0F38 3A/r RVM V/V AVX Compare packed unsigned word integers in\r\n VPMINUW xmm1, xmm2, xmm3/m128 xmm3/m128 and xmm2 and return packed\r\n minimum values in xmm1.\r\n VEX.NDS.256.66.0F DA /r RVM V/V AVX2 Compare packed unsigned byte integers in ymm2\r\n VPMINUB ymm1, ymm2, ymm3/m256 and ymm3/m256 and store packed minimum values\r\n in ymm1.\r\n VEX.NDS.256.66.0F38 3A/r RVM V/V AVX2 Compare packed unsigned word integers in\r\n VPMINUW ymm1, ymm2, ymm3/m256 ymm3/m256 and ymm2 and return packed\r\n minimum values in ymm1.\r\n EVEX.NDS.128.66.0F DA /r FVM V/V AVX512VL Compare packed unsigned byte integers in xmm2\r\n VPMINUB xmm1 {k1}{z}, xmm2, AVX512BW and xmm3/m128 and store packed minimum values\r\n xmm3/m128 in xmm1 under writemask k1.\r\n EVEX.NDS.256.66.0F DA /r FVM V/V AVX512VL Compare packed unsigned byte integers in ymm2\r\n VPMINUB ymm1 {k1}{z}, ymm2, AVX512BW and ymm3/m256 and store packed minimum values\r\n ymm3/m256 in ymm1 under writemask k1.\r\n EVEX.NDS.512.66.0F DA /r FVM V/V AVX512BW Compare packed unsigned byte integers in zmm2\r\n VPMINUB zmm1 {k1}{z}, zmm2, and zmm3/m512 and store packed minimum values\r\n zmm3/m512 in zmm1 under writemask k1.\r\n EVEX.NDS.128.66.0F38 3A/r FVM V/V AVX512VL Compare packed unsigned word integers in\r\n VPMINUW xmm1{k1}{z}, xmm2, AVX512BW xmm3/m128 and xmm2 and return packed\r\n xmm3/m128 minimum values in xmm1 under writemask k1.\r\n EVEX.NDS.256.66.0F38 3A/r FVM V/V AVX512VL Compare packed unsigned word integers in\r\n VPMINUW ymm1{k1}{z}, ymm2, AVX512BW ymm3/m256 and ymm2 and return packed\r\n ymm3/m256 minimum values in ymm1 under writemask k1.\r\n EVEX.NDS.512.66.0F38 3A/r FVM V/V AVX512BW Compare packed unsigned word integers in\r\n VPMINUW zmm1{k1}{z}, zmm2, zmm3/m512 and zmm2 and return packed\r\n zmm3/m512 minimum values in zmm1 under writemask k1.\r\n NOTES:\r\n 1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\n Developer's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX\r\n Registers\" in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\n\r\n\r\nDescription\r\nPerforms a SIMD compare of the packed unsigned byte or word integers in the second source operand and the first\r\nsource operand and returns the minimum value for each pair of integers to the destination operand.\r\nLegacy SSE version PMINUB: The source operand can be an MMX technology register or a 64-bit memory location.\r\nThe destination operand can be an MMX technology register.\r\n128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination\r\nregister remain unchanged.\r\nVEX.128 encoded version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination\r\nregister are zeroed.\r\nVEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The\r\nfirst source and destination operands are YMM registers.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register; The second source operand is a\r\nZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand is conditionally updated\r\nbased on writemask k1.\r\n\r\nOperation\r\nPMINUB (for 64-bit operands)\r\n IF DEST[7:0] < SRC[17:0] THEN\r\n DEST[7:0] <- DEST[7:0];\r\n ELSE\r\n DEST[7:0] <- SRC[7:0]; FI;\r\n (* Repeat operation for 2nd through 7th bytes in source and destination operands *)\r\n IF DEST[63:56] < SRC[63:56] THEN\r\n DEST[63:56] <- DEST[63:56];\r\n ELSE\r\n DEST[63:56] <- SRC[63:56]; FI;\r\n\r\nPMINUB instruction for 128-bit operands:\r\n IF DEST[7:0] < SRC[7:0] THEN\r\n DEST[7:0] <- DEST[7:0];\r\n ELSE\r\n DEST[15:0] <- SRC[7:0]; FI;\r\n (* Repeat operation for 2nd through 15th bytes in source and destination operands *)\r\n IF DEST[127:120] < SRC[127:120] THEN\r\n DEST[127:120] <- DEST[127:120];\r\n ELSE\r\n DEST[127:120] <- SRC[127:120]; FI;\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVPMINUB (VEX.128 encoded version)\r\n IF SRC1[7:0] < SRC2[7:0] THEN\r\n DEST[7:0] <- SRC1[7:0];\r\n ELSE\r\n DEST[7:0] <- SRC2[7:0]; FI;\r\n (* Repeat operation for 2nd through 15th bytes in source and destination operands *)\r\n IF SRC1[127:120] < SRC2[127:120] THEN\r\n DEST[127:120] <- SRC1[127:120];\r\n ELSE\r\n DEST[127:120] <- SRC2[127:120]; FI;\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\nVPMINUB (VEX.256 encoded version)\r\n IF SRC1[7:0] < SRC2[7:0] THEN\r\n DEST[7:0] <- SRC1[7:0];\r\n ELSE\r\n DEST[15:0] <- SRC2[7:0]; FI;\r\n (* Repeat operation for 2nd through 31st bytes in source and destination operands *)\r\n IF SRC1[255:248] < SRC2[255:248] THEN\r\n DEST[255:248] <- SRC1[255:248];\r\n ELSE\r\n DEST[255:248] <- SRC2[255:248]; FI;\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVPMINUB (EVEX encoded versions)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\nFOR j <- 0 TO KL-1\r\n i<-j*8\r\n IF k1[j] OR *no writemask* THEN\r\n IF SRC1[i+7:i] < SRC2[i+7:i]\r\n THEN DEST[i+7:i] <- SRC1[i+7:i];\r\n ELSE DEST[i+7:i] <- SRC2[i+7:i];\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+7:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nPMINUW instruction for 128-bit operands:\r\n IF DEST[15:0] < SRC[15:0] THEN\r\n DEST[15:0] <- DEST[15:0];\r\n ELSE\r\n DEST[15:0] <- SRC[15:0]; FI;\r\n (* Repeat operation for 2nd through 7th words in source and destination operands *)\r\n IF DEST[127:112] < SRC[127:112] THEN\r\n DEST[127:112] <- DEST[127:112];\r\n ELSE\r\n DEST[127:112] <- SRC[127:112]; FI;\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVPMINUW (VEX.128 encoded version)\r\n IF SRC1[15:0] < SRC2[15:0] THEN\r\n DEST[15:0] <- SRC1[15:0];\r\n ELSE\r\n DEST[15:0] <- SRC2[15:0]; FI;\r\n (* Repeat operation for 2nd through 7th words in source and destination operands *)\r\n IF SRC1[127:112] < SRC2[127:112] THEN\r\n DEST[127:112] <- SRC1[127:112];\r\n ELSE\r\n DEST[127:112] <- SRC2[127:112]; FI;\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\nVPMINUW (VEX.256 encoded version)\r\n IF SRC1[15:0] < SRC2[15:0] THEN\r\n DEST[15:0] <- SRC1[15:0];\r\n ELSE\r\n DEST[15:0] <- SRC2[15:0]; FI;\r\n (* Repeat operation for 2nd through 15th words in source and destination operands *)\r\n IF SRC1[255:240] < SRC2[255:240] THEN\r\n DEST[255:240] <- SRC1[255:240];\r\n ELSE\r\n DEST[255:240] <- SRC2[255:240]; FI;\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVPMINUW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask* THEN\r\n IF SRC1[i+15:i] < SRC2[i+15:i]\r\n THEN DEST[i+15:i] <- SRC1[i+15:i];\r\n ELSE DEST[i+15:i] <- SRC2[i+15:i];\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPMINUB __m512i _mm512_min_epu8( __m512i a, __m512i b);\r\nVPMINUB __m512i _mm512_mask_min_epu8(__m512i s, __mmask64 k, __m512i a, __m512i b);\r\nVPMINUB __m512i _mm512_maskz_min_epu8( __mmask64 k, __m512i a, __m512i b);\r\nVPMINUW __m512i _mm512_min_epu16( __m512i a, __m512i b);\r\nVPMINUW __m512i _mm512_mask_min_epu16(__m512i s, __mmask32 k, __m512i a, __m512i b);\r\nVPMINUW __m512i _mm512_maskz_min_epu16( __mmask32 k, __m512i a, __m512i b);\r\nVPMINUB __m256i _mm256_mask_min_epu8(__m256i s, __mmask32 k, __m256i a, __m256i b);\r\nVPMINUB __m256i _mm256_maskz_min_epu8( __mmask32 k, __m256i a, __m256i b);\r\nVPMINUW __m256i _mm256_mask_min_epu16(__m256i s, __mmask16 k, __m256i a, __m256i b);\r\nVPMINUW __m256i _mm256_maskz_min_epu16( __mmask16 k, __m256i a, __m256i b);\r\nVPMINUB __m128i _mm_mask_min_epu8(__m128i s, __mmask16 k, __m128i a, __m128i b);\r\nVPMINUB __m128i _mm_maskz_min_epu8( __mmask16 k, __m128i a, __m128i b);\r\nVPMINUW __m128i _mm_mask_min_epu16(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPMINUW __m128i _mm_maskz_min_epu16( __mmask8 k, __m128i a, __m128i b);\r\n(V)PMINUB __m128i _mm_min_epu8 ( __m128i a, __m128i b)\r\n(V)PMINUW __m128i _mm_min_epu16 ( __m128i a, __m128i b);\r\nVPMINUB __m256i _mm256_min_epu8 ( __m256i a, __m256i b)\r\nVPMINUW __m256i _mm256_min_epu16 ( __m256i a, __m256i b);\r\nPMINUB: __m64 _m_min_pu8 (__m64 a, __m64 b)\r\n\r\n\r\n\r\n\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PMINUB"
},
{
"description": "PMINUD/PMINUQ-Minimum of Packed Unsigned Integers\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0F 38 3B /r RM V/V SSE4_1 Compare packed unsigned dword integers in xmm1 and\r\n PMINUD xmm1, xmm2/m128 xmm2/m128 and store packed minimum values in xmm1.\r\n VEX.NDS.128.66.0F38.WIG 3B /r RVM V/V AVX Compare packed unsigned dword integers in xmm2 and\r\n VPMINUD xmm1, xmm2, xmm3/m128 and store packed minimum values in xmm1.\r\n xmm3/m128\r\n VEX.NDS.256.66.0F38.WIG 3B /r RVM V/V AVX2 Compare packed unsigned dword integers in ymm2 and\r\n VPMINUD ymm1, ymm2, ymm3/m256 and store packed minimum values in ymm1.\r\n ymm3/m256\r\n EVEX.NDS.128.66.0F38.W0 3B /r FV V/V AVX512VL Compare packed unsigned dword integers in xmm2 and\r\n VPMINUD xmm1 {k1}{z}, xmm2, AVX512F xmm3/m128/m32bcst and store packed minimum values\r\n xmm3/m128/m32bcst in xmm1 under writemask k1.\r\n EVEX.NDS.256.66.0F38.W0 3B /r FV V/V AVX512VL Compare packed unsigned dword integers in ymm2 and\r\n VPMINUD ymm1 {k1}{z}, ymm2, AVX512F ymm3/m256/m32bcst and store packed minimum values\r\n ymm3/m256/m32bcst in ymm1 under writemask k1.\r\n EVEX.NDS.512.66.0F38.W0 3B /r FV V/V AVX512F Compare packed unsigned dword integers in zmm2 and\r\n VPMINUD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst and store packed minimum values\r\n zmm3/m512/m32bcst in zmm1 under writemask k1.\r\n EVEX.NDS.128.66.0F38.W1 3B /r FV V/V AVX512VL Compare packed unsigned qword integers in xmm2 and\r\n VPMINUQ xmm1 {k1}{z}, xmm2, AVX512F xmm3/m128/m64bcst and store packed minimum values\r\n xmm3/m128/m64bcst in xmm1 under writemask k1.\r\n EVEX.NDS.256.66.0F38.W1 3B /r FV V/V AVX512VL Compare packed unsigned qword integers in ymm2 and\r\n VPMINUQ ymm1 {k1}{z}, ymm2, AVX512F ymm3/m256/m64bcst and store packed minimum values\r\n ymm3/m256/m64bcst in ymm1 under writemask k1.\r\n EVEX.NDS.512.66.0F38.W1 3B /r FV V/V AVX512F Compare packed unsigned qword integers in zmm2 and\r\n VPMINUQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst and store packed minimum values\r\n zmm3/m512/m64bcst in zmm1 under writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a SIMD compare of the packed unsigned dword/qword integers in the second source operand and the first\r\nsource operand and returns the minimum value for each pair of integers to the destination operand.\r\n128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination\r\nregister remain unchanged.\r\nVEX.128 encoded version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination\r\nregister are zeroed.\r\nVEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The\r\nfirst source and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding destination\r\nregister are zeroed.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register; The second source operand is a\r\nZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a\r\n32/64-bit memory location. The destination operand is conditionally updated based on writemask k1.\r\n\r\n\r\n\r\nOperation\r\nPMINUD (128-bit Legacy SSE version)\r\nPMINUD instruction for 128-bit operands:\r\n IF DEST[31:0] < SRC[31:0] THEN\r\n DEST[31:0] <- DEST[31:0];\r\n ELSE\r\n DEST[31:0] <- SRC[31:0]; FI;\r\n (* Repeat operation for 2nd through 7th words in source and destination operands *)\r\n IF DEST[127:96] < SRC[127:96] THEN\r\n DEST[127:96] <- DEST[127:96];\r\n ELSE\r\n DEST[127:96] <- SRC[127:96]; FI;\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVPMINUD (VEX.128 encoded version)\r\nVPMINUD instruction for 128-bit operands:\r\n IF SRC1[31:0] < SRC2[31:0] THEN\r\n DEST[31:0] <- SRC1[31:0];\r\n ELSE\r\n DEST[31:0] <- SRC2[31:0]; FI;\r\n (* Repeat operation for 2nd through 3rd dwords in source and destination operands *)\r\n IF SRC1[127:96] < SRC2[127:96] THEN\r\n DEST[127:96] <- SRC1[127:96];\r\n ELSE\r\n DEST[127:96] <- SRC2[127:96]; FI;\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVPMINUD (VEX.256 encoded version)\r\nVPMINUD instruction for 128-bit operands:\r\n IF SRC1[31:0] < SRC2[31:0] THEN\r\n DEST[31:0] <- SRC1[31:0];\r\n ELSE\r\n DEST[31:0] <- SRC2[31:0]; FI;\r\n (* Repeat operation for 2nd through 7th dwords in source and destination operands *)\r\n IF SRC1[255:224] < SRC2[255:224] THEN\r\n DEST[255:224] <- SRC1[255:224];\r\n ELSE\r\n DEST[255:224] <- SRC2[255:224]; FI;\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVPMINUD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN\r\n IF SRC1[i+31:i] < SRC2[31:0]\r\n THEN DEST[i+31:i] <- SRC1[i+31:i];\r\n ELSE DEST[i+31:i] <- SRC2[31:0];\r\n FI;\r\n ELSE\r\n IF SRC1[i+31:i] < SRC2[i+31:i]\r\n THEN DEST[i+31:i] <- SRC1[i+31:i];\r\n ELSE DEST[i+31:i] <- SRC2[i+31:i];\r\n FI;\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPMINUQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN\r\n IF SRC1[i+63:i] < SRC2[63:0]\r\n THEN DEST[i+63:i] <- SRC1[i+63:i];\r\n ELSE DEST[i+63:i] <- SRC2[63:0];\r\n FI;\r\n ELSE\r\n IF SRC1[i+63:i] < SRC2[i+63:i]\r\n THEN DEST[i+63:i] <- SRC1[i+63:i];\r\n ELSE DEST[i+63:i] <- SRC2[i+63:i];\r\n FI;\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPMINUD __m512i _mm512_min_epu32( __m512i a, __m512i b);\r\nVPMINUD __m512i _mm512_mask_min_epu32(__m512i s, __mmask16 k, __m512i a, __m512i b);\r\nVPMINUD __m512i _mm512_maskz_min_epu32( __mmask16 k, __m512i a, __m512i b);\r\nVPMINUQ __m512i _mm512_min_epu64( __m512i a, __m512i b);\r\nVPMINUQ __m512i _mm512_mask_min_epu64(__m512i s, __mmask8 k, __m512i a, __m512i b);\r\nVPMINUQ __m512i _mm512_maskz_min_epu64( __mmask8 k, __m512i a, __m512i b);\r\nVPMINUD __m256i _mm256_mask_min_epu32(__m256i s, __mmask16 k, __m256i a, __m256i b);\r\nVPMINUD __m256i _mm256_maskz_min_epu32( __mmask16 k, __m256i a, __m256i b);\r\nVPMINUQ __m256i _mm256_mask_min_epu64(__m256i s, __mmask8 k, __m256i a, __m256i b);\r\nVPMINUQ __m256i _mm256_maskz_min_epu64( __mmask8 k, __m256i a, __m256i b);\r\nVPMINUD __m128i _mm_mask_min_epu32(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPMINUD __m128i _mm_maskz_min_epu32( __mmask8 k, __m128i a, __m128i b);\r\nVPMINUQ __m128i _mm_mask_min_epu64(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPMINUQ __m128i _mm_maskz_min_epu64( __mmask8 k, __m128i a, __m128i b);\r\n(V)PMINUD __m128i _mm_min_epu32 ( __m128i a, __m128i b);\r\nVPMINUD __m256i _mm256_min_epu32 ( __m256i a, __m256i b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PMINUD"
},
{
"description": "-R:PMINUD",
"mnem": "PMINUQ"
},
{
"description": "-R:PMINUB",
"mnem": "PMINUW"
},
{
"description": "PMOVMSKB-Move Byte Mask\r\n Opcode/ Op/ 64/32 bit CPUID Description\r\n Instruction En Mode Feature\r\n Support Flag\r\n 0F D7 /r1 RM V/V SSE Move a byte mask of mm to reg. The upper\r\n PMOVMSKB reg, mm bits of r32 or r64 are zeroed\r\n\r\n 66 0F D7 /r RM V/V SSE2 Move a byte mask of xmm to reg. The upper\r\n PMOVMSKB reg, xmm bits of r32 or r64 are zeroed\r\n\r\n VEX.128.66.0F.WIG D7 /r RM V/V AVX Move a byte mask of xmm1 to reg. The upper\r\n VPMOVMSKB reg, xmm1 bits of r32 or r64 are filled with zeros.\r\n\r\n VEX.256.66.0F.WIG D7 /r RM V/V AVX2 Move a 32-bit mask of ymm1 to reg. The\r\n VPMOVMSKB reg, ymm1 upper bits of r64 are filled with zeros.\r\n\r\n NOTES:\r\n 1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\n Developer's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\n in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\n\r\nDescription\r\nCreates a mask made up of the most significant bit of each byte of the source operand (second operand) and stores\r\nthe result in the low byte or word of the destination operand (first operand).\r\nThe byte mask is 8 bits for 64-bit source operand, 16 bits for 128-bit source operand and 32 bits for 256-bit source\r\noperand. The destination operand is a general-purpose register.\r\nIn 64-bit mode, the instruction can access additional registers (XMM8-XMM15, R8-R15) when used with a REX.R\r\nprefix. The default operand size is 64-bit in 64-bit mode.\r\nLegacy SSE version: The source operand is an MMX technology register.\r\n128-bit Legacy SSE version: The source operand is an XMM register.\r\nVEX.128 encoded version: The source operand is an XMM register.\r\nVEX.256 encoded version: The source operand is a YMM register.\r\nNote: VEX.vvvv is reserved and must be 1111b.\r\n\r\nOperation\r\nPMOVMSKB (with 64-bit source operand and r32)\r\n r32[0] <- SRC[7];\r\n r32[1] <- SRC[15];\r\n (* Repeat operation for bytes 2 through 6 *)\r\n r32[7] <- SRC[63];\r\n r32[31:8] <- ZERO_FILL;\r\n\r\n(V)PMOVMSKB (with 128-bit source operand and r32)\r\n r32[0] <- SRC[7];\r\n r32[1] <- SRC[15];\r\n (* Repeat operation for bytes 2 through 14 *)\r\n r32[15] <- SRC[127];\r\n r32[31:16] <- ZERO_FILL;\r\n\r\n\r\n\r\nVPMOVMSKB (with 256-bit source operand and r32)\r\nr32[0] <- SRC[7];\r\nr32[1] <- SRC[15];\r\n(* Repeat operation for bytes 3rd through 31*)\r\nr32[31] <- SRC[255];\r\n\r\nPMOVMSKB (with 64-bit source operand and r64)\r\n r64[0] <- SRC[7];\r\n r64[1] <- SRC[15];\r\n (* Repeat operation for bytes 2 through 6 *)\r\n r64[7] <- SRC[63];\r\n r64[63:8] <- ZERO_FILL;\r\n\r\n(V)PMOVMSKB (with 128-bit source operand and r64)\r\n r64[0] <- SRC[7];\r\n r64[1] <- SRC[15];\r\n (* Repeat operation for bytes 2 through 14 *)\r\n r64[15] <- SRC[127];\r\n r64[63:16] <- ZERO_FILL;\r\n\r\nVPMOVMSKB (with 256-bit source operand and r64)\r\nr64[0] <- SRC[7];\r\nr64[1] <- SRC[15];\r\n(* Repeat operation for bytes 2 through 31*)\r\nr64[31] <- SRC[255];\r\nr64[63:32] <- ZERO_FILL;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nPMOVMSKB: int _mm_movemask_pi8(__m64 a)\r\n(V)PMOVMSKB: int _mm_movemask_epi8 ( __m128i a)\r\nVPMOVMSKB: int _mm256_movemask_epi8 ( __m256i a)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nNumeric Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 7; additionally\r\n#UD If VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PMOVMSKB"
},
{
"description": "PMOVSX-Packed Move with Sign Extend\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0f 38 20 /r RM V/V SSE4_1 Sign extend 8 packed 8-bit integers in the low 8 bytes\r\n PMOVSXBW xmm1, xmm2/m64 of xmm2/m64 to 8 packed 16-bit integers in xmm1.\r\n 66 0f 38 21 /r RM V/V SSE4_1 Sign extend 4 packed 8-bit integers in the low 4 bytes\r\n PMOVSXBD xmm1, xmm2/m32 of xmm2/m32 to 4 packed 32-bit integers in xmm1.\r\n 66 0f 38 22 /r RM V/V SSE4_1 Sign extend 2 packed 8-bit integers in the low 2 bytes\r\n PMOVSXBQ xmm1, xmm2/m16 of xmm2/m16 to 2 packed 64-bit integers in xmm1.\r\n 66 0f 38 23/r RM V/V SSE4_1 Sign extend 4 packed 16-bit integers in the low 8 bytes\r\n PMOVSXWD xmm1, xmm2/m64 of xmm2/m64 to 4 packed 32-bit integers in xmm1.\r\n 66 0f 38 24 /r RM V/V SSE4_1 Sign extend 2 packed 16-bit integers in the low 4 bytes\r\n PMOVSXWQ xmm1, xmm2/m32 of xmm2/m32 to 2 packed 64-bit integers in xmm1.\r\n 66 0f 38 25 /r RM V/V SSE4_1 Sign extend 2 packed 32-bit integers in the low 8 bytes\r\n PMOVSXDQ xmm1, xmm2/m64 of xmm2/m64 to 2 packed 64-bit integers in xmm1.\r\n VEX.128.66.0F38.WIG 20 /r RM V/V AVX Sign extend 8 packed 8-bit integers in the low 8 bytes\r\n VPMOVSXBW xmm1, xmm2/m64 of xmm2/m64 to 8 packed 16-bit integers in xmm1.\r\n VEX.128.66.0F38.WIG 21 /r RM V/V AVX Sign extend 4 packed 8-bit integers in the low 4 bytes\r\n VPMOVSXBD xmm1, xmm2/m32 of xmm2/m32 to 4 packed 32-bit integers in xmm1.\r\n VEX.128.66.0F38.WIG 22 /r RM V/V AVX Sign extend 2 packed 8-bit integers in the low 2 bytes\r\n VPMOVSXBQ xmm1, xmm2/m16 of xmm2/m16 to 2 packed 64-bit integers in xmm1.\r\n VEX.128.66.0F38.WIG 23 /r RM V/V AVX Sign extend 4 packed 16-bit integers in the low 8 bytes\r\n VPMOVSXWD xmm1, xmm2/m64 of xmm2/m64 to 4 packed 32-bit integers in xmm1.\r\n VEX.128.66.0F38.WIG 24 /r RM V/V AVX Sign extend 2 packed 16-bit integers in the low 4 bytes\r\n VPMOVSXWQ xmm1, xmm2/m32 of xmm2/m32 to 2 packed 64-bit integers in xmm1.\r\n VEX.128.66.0F38.WIG 25 /r RM V/V AVX Sign extend 2 packed 32-bit integers in the low 8 bytes\r\n VPMOVSXDQ xmm1, xmm2/m64 of xmm2/m64 to 2 packed 64-bit integers in xmm1.\r\n VEX.256.66.0F38.WIG 20 /r RM V/V AVX2 Sign extend 16 packed 8-bit integers in xmm2/m128 to\r\n VPMOVSXBW ymm1, xmm2/m128 16 packed 16-bit integers in ymm1.\r\n VEX.256.66.0F38.WIG 21 /r RM V/V AVX2 Sign extend 8 packed 8-bit integers in the low 8 bytes\r\n VPMOVSXBD ymm1, xmm2/m64 of xmm2/m64 to 8 packed 32-bit integers in ymm1.\r\n VEX.256.66.0F38.WIG 22 /r RM V/V AVX2 Sign extend 4 packed 8-bit integers in the low 4 bytes\r\n VPMOVSXBQ ymm1, xmm2/m32 of xmm2/m32 to 4 packed 64-bit integers in ymm1.\r\n VEX.256.66.0F38.WIG 23 /r RM V/V AVX2 Sign extend 8 packed 16-bit integers in the low 16\r\n VPMOVSXWD ymm1, xmm2/m128 bytes of xmm2/m128 to 8 packed 32-bit integers in\r\n ymm1.\r\n VEX.256.66.0F38.WIG 24 /r RM V/V AVX2 Sign extend 4 packed 16-bit integers in the low 8 bytes\r\n VPMOVSXWQ ymm1, xmm2/m64 of xmm2/m64 to 4 packed 64-bit integers in ymm1.\r\n VEX.256.66.0F38.WIG 25 /r RM V/V AVX2 Sign extend 4 packed 32-bit integers in the low 16\r\n VPMOVSXDQ ymm1, xmm2/m128 bytes of xmm2/m128 to 4 packed 64-bit integers in\r\n ymm1.\r\n EVEX.128.66.0F38.WIG 20 /r HVM V/V AVX512VL Sign extend 8 packed 8-bit integers in xmm2/m64 to 8\r\n VPMOVSXBW xmm1 {k1}{z}, AVX512BW packed 16-bit integers in zmm1.\r\n xmm2/m64\r\n EVEX.256.66.0F38.WIG 20 /r HVM V/V AVX512VL Sign extend 16 packed 8-bit integers in xmm2/m128 to\r\n VPMOVSXBW ymm1 {k1}{z}, AVX512BW 16 packed 16-bit integers in ymm1.\r\n xmm2/m128\r\n EVEX.512.66.0F38.WIG 20 /r HVM V/V AVX512BW Sign extend 32 packed 8-bit integers in ymm2/m256 to\r\n VPMOVSXBW zmm1 {k1}{z}, 32 packed 16-bit integers in zmm1.\r\n ymm2/m256\r\n EVEX.128.66.0F38.WIG 21 /r QVM V/V AVX512VL Sign extend 4 packed 8-bit integers in the low 4 bytes\r\n VPMOVSXBD xmm1 {k1}{z}, AVX512F of xmm2/m32 to 4 packed 32-bit integers in xmm1\r\n xmm2/m32 subject to writemask k1.\r\n\r\n\r\n\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.256.66.0F38.WIG 21 /r QVM V/V AVX512VL Sign extend 8 packed 8-bit integers in the low 8 bytes\r\n VPMOVSXBD ymm1 {k1}{z}, AVX512F of xmm2/m64 to 8 packed 32-bit integers in ymm1\r\n xmm2/m64 subject to writemask k1.\r\n EVEX.512.66.0F38.WIG 21 /r QVM V/V AVX512F Sign extend 16 packed 8-bit integers in the low 16\r\n VPMOVSXBD zmm1 {k1}{z}, bytes of xmm2/m128 to 16 packed 32-bit integers in\r\n xmm2/m128 zmm1 subject to writemask k1.\r\n EVEX.128.66.0F38.WIG 22 /r OVM V/V AVX512VL Sign extend 2 packed 8-bit integers in the low 2 bytes\r\n VPMOVSXBQ xmm1 {k1}{z}, AVX512F of xmm2/m16 to 2 packed 64-bit integers in xmm1\r\n xmm2/m16 subject to writemask k1.\r\n EVEX.256.66.0F38.WIG 22 /r OVM V/V AVX512VL Sign extend 4 packed 8-bit integers in the low 4 bytes\r\n VPMOVSXBQ ymm1 {k1}{z}, AVX512F of xmm2/m32 to 4 packed 64-bit integers in ymm1\r\n xmm2/m32 subject to writemask k1.\r\n EVEX.512.66.0F38.WIG 22 /r OVM V/V AVX512F Sign extend 8 packed 8-bit integers in the low 8 bytes\r\n VPMOVSXBQ zmm1 {k1}{z}, of xmm2/m64 to 8 packed 64-bit integers in zmm1\r\n xmm2/m64 subject to writemask k1.\r\n EVEX.128.66.0F38.WIG 23 /r HVM V/V AVX512VL Sign extend 4 packed 16-bit integers in the low 8 bytes\r\n VPMOVSXWD xmm1 {k1}{z}, AVX512F of ymm2/mem to 4 packed 32-bit integers in xmm1\r\n xmm2/m64 subject to writemask k1.\r\n EVEX.256.66.0F38.WIG 23 /r HVM V/V AVX512VL Sign extend 8 packed 16-bit integers in the low 16\r\n VPMOVSXWD ymm1 {k1}{z}, AVX512F bytes of ymm2/m128 to 8 packed 32-bit integers in\r\n xmm2/m128 ymm1 subject to writemask k1.\r\n EVEX.512.66.0F38.WIG 23 /r HVM V/V AVX512F Sign extend 16 packed 16-bit integers in the low 32\r\n VPMOVSXWD zmm1 {k1}{z}, bytes of ymm2/m256 to 16 packed 32-bit integers in\r\n ymm2/m256 zmm1 subject to writemask k1.\r\n EVEX.128.66.0F38.WIG 24 /r QVM V/V AVX512VL Sign extend 2 packed 16-bit integers in the low 4 bytes\r\n VPMOVSXWQ xmm1 {k1}{z}, AVX512F of xmm2/m32 to 2 packed 64-bit integers in xmm1\r\n xmm2/m32 subject to writemask k1.\r\n EVEX.256.66.0F38.WIG 24 /r QVM V/V AVX512VL Sign extend 4 packed 16-bit integers in the low 8 bytes\r\n VPMOVSXWQ ymm1 {k1}{z}, AVX512F of xmm2/m64 to 4 packed 64-bit integers in ymm1\r\n xmm2/m64 subject to writemask k1.\r\n EVEX.512.66.0F38.WIG 24 /r QVM V/V AVX512F Sign extend 8 packed 16-bit integers in the low 16\r\n VPMOVSXWQ zmm1 {k1}{z}, bytes of xmm2/m128 to 8 packed 64-bit integers in\r\n xmm2/m128 zmm1 subject to writemask k1.\r\n EVEX.128.66.0F38.W0 25 /r HVM V/V AVX512VL Sign extend 2 packed 32-bit integers in the low 8 bytes\r\n VPMOVSXDQ xmm1 {k1}{z}, AVX512F of xmm2/m64 to 2 packed 64-bit integers in zmm1\r\n xmm2/m64 using writemask k1.\r\n EVEX.256.66.0F38.W0 25 /r HVM V/V AVX512VL Sign extend 4 packed 32-bit integers in the low 16\r\n VPMOVSXDQ ymm1 {k1}{z}, AVX512F bytes of xmm2/m128 to 4 packed 64-bit integers in\r\n xmm2/m128 zmm1 using writemask k1.\r\n EVEX.512.66.0F38.W0 25 /r HVM V/V AVX512F Sign extend 8 packed 32-bit integers in the low 32\r\n VPMOVSXDQ zmm1 {k1}{z}, bytes of ymm2/m256 to 8 packed 64-bit integers in\r\n ymm2/m256 zmm1 using writemask k1.\r\n\r\n\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n HVM, QVM, OVM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nLegacy and VEX encoded versions: Packed byte, word, or dword integers in the low bytes of the source operand\r\n(second operand) are sign extended to word, dword, or quadword integers and stored in packed signed bytes the\r\ndestination operand.\r\n128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register remain unchanged.\r\nVEX.128 and EVEX.128 encoded versions: Bits (MAX_VL-1:128) of the corresponding destination register are\r\nzeroed.\r\nVEX.256 and EVEX.256 encoded versions: Bits (MAX_VL-1:256) of the corresponding destination register are\r\nzeroed.\r\nEVEX encoded versions: Packed byte, word or dword integers starting from the low bytes of the source operand\r\n(second operand) are sign extended to word, dword or quadword integers and stored to the destination operand\r\nunder the writemask. The destination register is XMM, YMM or ZMM Register.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nPacked_Sign_Extend_BYTE_to_WORD(DEST, SRC)\r\nDEST[15:0] <-SignExtend(SRC[7:0]);\r\nDEST[31:16] <-SignExtend(SRC[15:8]);\r\nDEST[47:32] <-SignExtend(SRC[23:16]);\r\nDEST[63:48] <-SignExtend(SRC[31:24]);\r\nDEST[79:64] <-SignExtend(SRC[39:32]);\r\nDEST[95:80] <-SignExtend(SRC[47:40]);\r\nDEST[111:96] <-SignExtend(SRC[55:48]);\r\nDEST[127:112] <-SignExtend(SRC[63:56]);\r\n\r\nPacked_Sign_Extend_BYTE_to_DWORD(DEST, SRC)\r\nDEST[31:0] <-SignExtend(SRC[7:0]);\r\nDEST[63:32] <-SignExtend(SRC[15:8]);\r\nDEST[95:64] <-SignExtend(SRC[23:16]);\r\nDEST[127:96] <-SignExtend(SRC[31:24]);\r\n\r\nPacked_Sign_Extend_BYTE_to_QWORD(DEST, SRC)\r\nDEST[63:0] <-SignExtend(SRC[7:0]);\r\nDEST[127:64] <-SignExtend(SRC[15:8]);\r\n\r\nPacked_Sign_Extend_WORD_to_DWORD(DEST, SRC)\r\nDEST[31:0] <-SignExtend(SRC[15:0]);\r\nDEST[63:32] <-SignExtend(SRC[31:16]);\r\nDEST[95:64] <-SignExtend(SRC[47:32]);\r\nDEST[127:96] <-SignExtend(SRC[63:48]);\r\n\r\nPacked_Sign_Extend_WORD_to_QWORD(DEST, SRC)\r\nDEST[63:0] <-SignExtend(SRC[15:0]);\r\nDEST[127:64] <-SignExtend(SRC[31:16]);\r\n\r\nPacked_Sign_Extend_DWORD_to_QWORD(DEST, SRC)\r\nDEST[63:0] <-SignExtend(SRC[31:0]);\r\nDEST[127:64] <-SignExtend(SRC[63:32]);\r\n\r\nVPMOVSXBW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nPacked_Sign_Extend_BYTE_to_WORD(TMP_DEST[127:0], SRC[63:0])\r\nIF VL >= 256\r\n Packed_Sign_Extend_BYTE_to_WORD(TMP_DEST[255:128], SRC[127:64])\r\nFI;\r\nIF VL >= 512\r\n Packed_Sign_Extend_BYTE_to_WORD(TMP_DEST[383:256], SRC[191:128])\r\n Packed_Sign_Extend_BYTE_to_WORD(TMP_DEST[511:384], SRC[255:192])\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- TEMP_DEST[i+15:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n\r\n\r\n\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPMOVSXBD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nPacked_Sign_Extend_BYTE_to_DWORD(TMP_DEST[127:0], SRC[31:0])\r\nIF VL >= 256\r\n Packed_Sign_Extend_BYTE_to_DWORD(TMP_DEST[255:128], SRC[63:32])\r\nFI;\r\nIF VL >= 512\r\n Packed_Sign_Extend_BYTE_to_DWORD(TMP_DEST[383:256], SRC[95:64])\r\n Packed_Sign_Extend_BYTE_to_DWORD(TMP_DEST[511:384], SRC[127:96])\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TEMP_DEST[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPMOVSXBQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nPacked_Sign_Extend_BYTE_to_QWORD(TMP_DEST[127:0], SRC[15:0])\r\nIF VL >= 256\r\n Packed_Sign_Extend_BYTE_to_QWORD(TMP_DEST[255:128], SRC[31:16])\r\nFI;\r\nIF VL >= 512\r\n Packed_Sign_Extend_BYTE_to_QWORD(TMP_DEST[383:256], SRC[47:32])\r\n Packed_Sign_Extend_BYTE_to_QWORD(TMP_DEST[511:384], SRC[63:48])\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TEMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVPMOVSXWD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nPacked_Sign_Extend_WORD_to_DWORD(TMP_DEST[127:0], SRC[63:0])\r\nIF VL >= 256\r\n Packed_Sign_Extend_WORD_to_DWORD(TMP_DEST[255:128], SRC[127:64])\r\nFI;\r\nIF VL >= 512\r\n Packed_Sign_Extend_WORD_to_DWORD(TMP_DEST[383:256], SRC[191:128])\r\n Packed_Sign_Extend_WORD_to_DWORD(TMP_DEST[511:384], SRC[256:192])\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TEMP_DEST[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPMOVSXWQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nPacked_Sign_Extend_WORD_to_QWORD(TMP_DEST[127:0], SRC[31:0])\r\nIF VL >= 256\r\n Packed_Sign_Extend_WORD_to_QWORD(TMP_DEST[255:128], SRC[63:32])\r\nFI;\r\nIF VL >= 512\r\n Packed_Sign_Extend_WORD_to_QWORD(TMP_DEST[383:256], SRC[95:64])\r\n Packed_Sign_Extend_WORD_to_QWORD(TMP_DEST[511:384], SRC[127:96])\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TEMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVPMOVSXDQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nPacked_Sign_Extend_DWORD_to_QWORD(TEMP_DEST[127:0], SRC[63:0])\r\nIF VL >= 256\r\n Packed_Sign_Extend_DWORD_to_QWORD(TEMP_DEST[255:128], SRC[127:64])\r\nFI;\r\nIF VL >= 512\r\n Packed_Sign_Extend_DWORD_to_QWORD(TEMP_DEST[383:256], SRC[191:128])\r\n Packed_Sign_Extend_DWORD_to_QWORD(TEMP_DEST[511:384], SRC[255:192])\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TEMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPMOVSXBW (VEX.256 encoded version)\r\nPacked_Sign_Extend_BYTE_to_WORD(DEST[127:0], SRC[63:0])\r\nPacked_Sign_Extend_BYTE_to_WORD(DEST[255:128], SRC[127:64])\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVPMOVSXBD (VEX.256 encoded version)\r\nPacked_Sign_Extend_BYTE_to_DWORD(DEST[127:0], SRC[31:0])\r\nPacked_Sign_Extend_BYTE_to_DWORD(DEST[255:128], SRC[63:32])\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVPMOVSXBQ (VEX.256 encoded version)\r\nPacked_Sign_Extend_BYTE_to_QWORD(DEST[127:0], SRC[15:0])\r\nPacked_Sign_Extend_BYTE_to_QWORD(DEST[255:128], SRC[31:16])\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVPMOVSXWD (VEX.256 encoded version)\r\nPacked_Sign_Extend_WORD_to_DWORD(DEST[127:0], SRC[63:0])\r\nPacked_Sign_Extend_WORD_to_DWORD(DEST[255:128], SRC[127:64])\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVPMOVSXWQ (VEX.256 encoded version)\r\nPacked_Sign_Extend_WORD_to_QWORD(DEST[127:0], SRC[31:0])\r\nPacked_Sign_Extend_WORD_to_QWORD(DEST[255:128], SRC[63:32])\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVPMOVSXDQ (VEX.256 encoded version)\r\nPacked_Sign_Extend_DWORD_to_QWORD(DEST[127:0], SRC[63:0])\r\nPacked_Sign_Extend_DWORD_to_QWORD(DEST[255:128], SRC[127:64])\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\n\r\n\r\n\r\nVPMOVSXBW (VEX.128 encoded version)\r\nPacked_Sign_Extend_BYTE_to_WORDDEST[127:0], SRC[127:0]()\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVPMOVSXBD (VEX.128 encoded version)\r\nPacked_Sign_Extend_BYTE_to_DWORD(DEST[127:0], SRC[127:0])\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVPMOVSXBQ (VEX.128 encoded version)\r\nPacked_Sign_Extend_BYTE_to_QWORD(DEST[127:0], SRC[127:0])\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVPMOVSXWD (VEX.128 encoded version)\r\nPacked_Sign_Extend_WORD_to_DWORD(DEST[127:0], SRC[127:0])\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVPMOVSXWQ (VEX.128 encoded version)\r\nPacked_Sign_Extend_WORD_to_QWORD(DEST[127:0], SRC[127:0])\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVPMOVSXDQ (VEX.128 encoded version)\r\nPacked_Sign_Extend_DWORD_to_QWORD(DEST[127:0], SRC[127:0])\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nPMOVSXBW\r\nPacked_Sign_Extend_BYTE_to_WORD(DEST[127:0], SRC[127:0])\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nPMOVSXBD\r\nPacked_Sign_Extend_BYTE_to_DWORD(DEST[127:0], SRC[127:0])\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nPMOVSXBQ\r\nPacked_Sign_Extend_BYTE_to_QWORD(DEST[127:0], SRC[127:0])\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nPMOVSXWD\r\nPacked_Sign_Extend_WORD_to_DWORD(DEST[127:0], SRC[127:0])\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nPMOVSXWQ\r\nPacked_Sign_Extend_WORD_to_QWORD(DEST[127:0], SRC[127:0])\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nPMOVSXDQ\r\nPacked_Sign_Extend_DWORD_to_QWORD(DEST[127:0], SRC[127:0])\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPMOVSXBW __m512i _mm512_cvtepi8_epi16(__m512i a);\r\nVPMOVSXBW __m512i _mm512_mask_cvtepi8_epi16(__m512i a, __mmask32 k, __m512i b);\r\nVPMOVSXBW __m512i _mm512_maskz_cvtepi8_epi16( __mmask32 k, __m512i b);\r\nVPMOVSXBD __m512i _mm512_cvtepi8_epi32(__m512i a);\r\nVPMOVSXBD __m512i _mm512_mask_cvtepi8_epi32(__m512i a, __mmask16 k, __m512i b);\r\n\r\n\r\n\r\nVPMOVSXBD __m512i _mm512_maskz_cvtepi8_epi32( __mmask16 k, __m512i b);\r\nVPMOVSXBQ __m512i _mm512_cvtepi8_epi64(__m512i a);\r\nVPMOVSXBQ __m512i _mm512_mask_cvtepi8_epi64(__m512i a, __mmask8 k, __m512i b);\r\nVPMOVSXBQ __m512i _mm512_maskz_cvtepi8_epi64( __mmask8 k, __m512i a);\r\nVPMOVSXDQ __m512i _mm512_cvtepi32_epi64(__m512i a);\r\nVPMOVSXDQ __m512i _mm512_mask_cvtepi32_epi64(__m512i a, __mmask8 k, __m512i b);\r\nVPMOVSXDQ __m512i _mm512_maskz_cvtepi32_epi64( __mmask8 k, __m512i a);\r\nVPMOVSXWD __m512i _mm512_cvtepi16_epi32(__m512i a);\r\nVPMOVSXWD __m512i _mm512_mask_cvtepi16_epi32(__m512i a, __mmask16 k, __m512i b);\r\nVPMOVSXWD __m512i _mm512_maskz_cvtepi16_epi32(__mmask16 k, __m512i a);\r\nVPMOVSXWQ __m512i _mm512_cvtepi16_epi64(__m512i a);\r\nVPMOVSXWQ __m512i _mm512_mask_cvtepi16_epi64(__m512i a, __mmask8 k, __m512i b);\r\nVPMOVSXWQ __m512i _mm512_maskz_cvtepi16_epi64( __mmask8 k, __m512i a);\r\nVPMOVSXBW __m256i _mm256_cvtepi8_epi16(__m256i a);\r\nVPMOVSXBW __m256i _mm256_mask_cvtepi8_epi16(__m256i a, __mmask16 k, __m256i b);\r\nVPMOVSXBW __m256i _mm256_maskz_cvtepi8_epi16( __mmask16 k, __m256i b);\r\nVPMOVSXBD __m256i _mm256_cvtepi8_epi32(__m256i a);\r\nVPMOVSXBD __m256i _mm256_mask_cvtepi8_epi32(__m256i a, __mmask8 k, __m256i b);\r\nVPMOVSXBD __m256i _mm256_maskz_cvtepi8_epi32( __mmask8 k, __m256i b);\r\nVPMOVSXBQ __m256i _mm256_cvtepi8_epi64(__m256i a);\r\nVPMOVSXBQ __m256i _mm256_mask_cvtepi8_epi64(__m256i a, __mmask8 k, __m256i b);\r\nVPMOVSXBQ __m256i _mm256_maskz_cvtepi8_epi64( __mmask8 k, __m256i a);\r\nVPMOVSXDQ __m256i _mm256_cvtepi32_epi64(__m256i a);\r\nVPMOVSXDQ __m256i _mm256_mask_cvtepi32_epi64(__m256i a, __mmask8 k, __m256i b);\r\nVPMOVSXDQ __m256i _mm256_maskz_cvtepi32_epi64( __mmask8 k, __m256i a);\r\nVPMOVSXWD __m256i _mm256_cvtepi16_epi32(__m256i a);\r\nVPMOVSXWD __m256i _mm256_mask_cvtepi16_epi32(__m256i a, __mmask16 k, __m256i b);\r\nVPMOVSXWD __m256i _mm256_maskz_cvtepi16_epi32(__mmask16 k, __m256i a);\r\nVPMOVSXWQ __m256i _mm256_cvtepi16_epi64(__m256i a);\r\nVPMOVSXWQ __m256i _mm256_mask_cvtepi16_epi64(__m256i a, __mmask8 k, __m256i b);\r\nVPMOVSXWQ __m256i _mm256_maskz_cvtepi16_epi64( __mmask8 k, __m256i a);\r\nVPMOVSXBW __m128i _mm_mask_cvtepi8_epi16(__m128i a, __mmask8 k, __m128i b);\r\nVPMOVSXBW __m128i _mm_maskz_cvtepi8_epi16( __mmask8 k, __m128i b);\r\nVPMOVSXBD __m128i _mm_mask_cvtepi8_epi32(__m128i a, __mmask8 k, __m128i b);\r\nVPMOVSXBD __m128i _mm_maskz_cvtepi8_epi32( __mmask8 k, __m128i b);\r\nVPMOVSXBQ __m128i _mm_mask_cvtepi8_epi64(__m128i a, __mmask8 k, __m128i b);\r\nVPMOVSXBQ __m128i _mm_maskz_cvtepi8_epi64( __mmask8 k, __m128i a);\r\nVPMOVSXDQ __m128i _mm_mask_cvtepi32_epi64(__m128i a, __mmask8 k, __m128i b);\r\nVPMOVSXDQ __m128i _mm_maskz_cvtepi32_epi64( __mmask8 k, __m128i a);\r\nVPMOVSXWD __m128i _mm_mask_cvtepi16_epi32(__m128i a, __mmask16 k, __m128i b);\r\nVPMOVSXWD __m128i _mm_maskz_cvtepi16_epi32(__mmask16 k, __m128i a);\r\nVPMOVSXWQ __m128i _mm_mask_cvtepi16_epi64(__m128i a, __mmask8 k, __m128i b);\r\nVPMOVSXWQ __m128i _mm_maskz_cvtepi16_epi64( __mmask8 k, __m128i a);\r\nPMOVSXBW __m128i _mm_ cvtepi8_epi16 ( __m128i a);\r\nPMOVSXBD __m128i _mm_ cvtepi8_epi32 ( __m128i a);\r\nPMOVSXBQ __m128i _mm_ cvtepi8_epi64 ( __m128i a);\r\nPMOVSXWD __m128i _mm_ cvtepi16_epi32 ( __m128i a);\r\nPMOVSXWQ __m128i _mm_ cvtepi16_epi64 ( __m128i a);\r\nPMOVSXDQ __m128i _mm_ cvtepi32_epi64 ( __m128i a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 5.\r\nEVEX-encoded instruction, see Exceptions Type E5.\r\n#UD If VEX.vvvv != 1111B, or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PMOVSX"
},
{
"description": "PMOVZX-Packed Move with Zero Extend\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0f 38 30 /r RM V/V SSE4_1 Zero extend 8 packed 8-bit integers in the low 8\r\n PMOVZXBW xmm1, xmm2/m64 bytes of xmm2/m64 to 8 packed 16-bit integers in\r\n xmm1.\r\n 66 0f 38 31 /r RM V/V SSE4_1 Zero extend 4 packed 8-bit integers in the low 4\r\n PMOVZXBD xmm1, xmm2/m32 bytes of xmm2/m32 to 4 packed 32-bit integers in\r\n xmm1.\r\n 66 0f 38 32 /r RM V/V SSE4_1 Zero extend 2 packed 8-bit integers in the low 2\r\n PMOVZXBQ xmm1, xmm2/m16 bytes of xmm2/m16 to 2 packed 64-bit integers in\r\n xmm1.\r\n 66 0f 38 33 /r RM V/V SSE4_1 Zero extend 4 packed 16-bit integers in the low 8\r\n PMOVZXWD xmm1, xmm2/m64 bytes of xmm2/m64 to 4 packed 32-bit integers in\r\n xmm1.\r\n 66 0f 38 34 /r RM V/V SSE4_1 Zero extend 2 packed 16-bit integers in the low 4\r\n PMOVZXWQ xmm1, xmm2/m32 bytes of xmm2/m32 to 2 packed 64-bit integers in\r\n xmm1.\r\n 66 0f 38 35 /r RM V/V SSE4_1 Zero extend 2 packed 32-bit integers in the low 8\r\n PMOVZXDQ xmm1, xmm2/m64 bytes of xmm2/m64 to 2 packed 64-bit integers in\r\n xmm1.\r\n VEX.128.66.0F38.WIG 30 /r RM V/V AVX Zero extend 8 packed 8-bit integers in the low 8\r\n VPMOVZXBW xmm1, xmm2/m64 bytes of xmm2/m64 to 8 packed 16-bit integers in\r\n xmm1.\r\n VEX.128.66.0F38.WIG 31 /r RM V/V AVX Zero extend 4 packed 8-bit integers in the low 4\r\n VPMOVZXBD xmm1, xmm2/m32 bytes of xmm2/m32 to 4 packed 32-bit integers in\r\n xmm1.\r\n VEX.128.66.0F38.WIG 32 /r RM V/V AVX Zero extend 2 packed 8-bit integers in the low 2\r\n VPMOVZXBQ xmm1, xmm2/m16 bytes of xmm2/m16 to 2 packed 64-bit integers in\r\n xmm1.\r\n VEX.128.66.0F38.WIG 33 /r RM V/V AVX Zero extend 4 packed 16-bit integers in the low 8\r\n VPMOVZXWD xmm1, xmm2/m64 bytes of xmm2/m64 to 4 packed 32-bit integers in\r\n xmm1.\r\n VEX.128.66.0F38.WIG 34 /r RM V/V AVX Zero extend 2 packed 16-bit integers in the low 4\r\n VPMOVZXWQ xmm1, xmm2/m32 bytes of xmm2/m32 to 2 packed 64-bit integers in\r\n xmm1.\r\n VEX.128.66.0F 38.WIG 35 /r RM V/V AVX Zero extend 2 packed 32-bit integers in the low 8\r\n VPMOVZXDQ xmm1, xmm2/m64 bytes of xmm2/m64 to 2 packed 64-bit integers in\r\n xmm1.\r\n VEX.256.66.0F38.WIG 30 /r RM V/V AVX2 Zero extend 16 packed 8-bit integers in\r\n VPMOVZXBW ymm1, xmm2/m128 xmm2/m128 to 16 packed 16-bit integers in ymm1.\r\n VEX.256.66.0F38.WIG 31 /r RM V/V AVX2 Zero extend 8 packed 8-bit integers in the low 8\r\n VPMOVZXBD ymm1, xmm2/m64 bytes of xmm2/m64 to 8 packed 32-bit integers in\r\n ymm1.\r\n VEX.256.66.0F38.WIG 32 /r RM V/V AVX2 Zero extend 4 packed 8-bit integers in the low 4\r\n VPMOVZXBQ ymm1, xmm2/m32 bytes of xmm2/m32 to 4 packed 64-bit integers in\r\n ymm1.\r\n VEX.256.66.0F38.WIG 33 /r RM V/V AVX2 Zero extend 8 packed 16-bit integers xmm2/m128\r\n VPMOVZXWD ymm1, xmm2/m128 to 8 packed 32-bit integers in ymm1.\r\n VEX.256.66.0F38.WIG 34 /r RM V/V AVX2 Zero extend 4 packed 16-bit integers in the low 8\r\n VPMOVZXWQ ymm1, xmm2/m64 bytes of xmm2/m64 to 4 packed 64-bit integers in\r\n xmm1.\r\n VEX.256.66.0F38.WIG 35 /r RM V/V AVX2 Zero extend 4 packed 32-bit integers in\r\n VPMOVZXDQ ymm1, xmm2/m128 xmm2/m128 to 4 packed 64-bit integers in ymm1.\r\n\r\n\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F38 30.WIG /r HVM V/V AVX512VL Zero extend 8 packed 8-bit integers in the low 8\r\n VPMOVZXBW xmm1 {k1}{z}, xmm2/m64 AVX512BW bytes of xmm2/m64 to 8 packed 16-bit integers in\r\n xmm1.\r\n EVEX.256.66.0F38.WIG 30 /r HVM V/V AVX512VL Zero extend 16 packed 8-bit integers in\r\n VPMOVZXBW ymm1 {k1}{z}, AVX512BW xmm2/m128 to 16 packed 16-bit integers in ymm1.\r\n xmm2/m128\r\n EVEX.512.66.0F38.WIG 30 /r HVM V/V AVX512BW Zero extend 32 packed 8-bit integers in\r\n VPMOVZXBW zmm1 {k1}{z}, ymm2/m256 to 32 packed 16-bit integers in zmm1.\r\n ymm2/m256\r\n EVEX.128.66.0F38.WIG 31 /r QVM V/V AVX512VL Zero extend 4 packed 8-bit integers in the low 4\r\n VPMOVZXBD xmm1 {k1}{z}, xmm2/m32 AVX512F bytes of xmm2/m32 to 4 packed 32-bit integers in\r\n xmm1 subject to writemask k1.\r\n EVEX.256.66.0F38.WIG 31 /r QVM V/V AVX512VL Zero extend 8 packed 8-bit integers in the low 8\r\n VPMOVZXBD ymm1 {k1}{z}, xmm2/m64 AVX512F bytes of xmm2/m64 to 8 packed 32-bit integers in\r\n ymm1 subject to writemask k1.\r\n EVEX.512.66.0F38.WIG 31 /r QVM V/V AVX512F Zero extend 16 packed 8-bit integers in\r\n VPMOVZXBD zmm1 {k1}{z}, xmm2/m128 to 16 packed 32-bit integers in zmm1\r\n xmm2/m128 subject to writemask k1.\r\n EVEX.128.66.0F38.WIG 32 /r OVM V/V AVX512VL Zero extend 2 packed 8-bit integers in the low 2\r\n VPMOVZXBQ xmm1 {k1}{z}, xmm2/m16 AVX512F bytes of xmm2/m16 to 2 packed 64-bit integers in\r\n xmm1 subject to writemask k1.\r\n EVEX.256.66.0F38.WIG 32 /r OVM V/V AVX512VL Zero extend 4 packed 8-bit integers in the low 4\r\n VPMOVZXBQ ymm1 {k1}{z}, xmm2/m32 AVX512F bytes of xmm2/m32 to 4 packed 64-bit integers in\r\n ymm1 subject to writemask k1.\r\n EVEX.512.66.0F38.WIG 32 /r OVM V/V AVX512F Zero extend 8 packed 8-bit integers in the low 8\r\n VPMOVZXBQ zmm1 {k1}{z}, xmm2/m64 bytes of xmm2/m64 to 8 packed 64-bit integers in\r\n zmm1 subject to writemask k1.\r\n EVEX.128.66.0F38.WIG 33 /r HVM V/V AVX512VL Zero extend 4 packed 16-bit integers in the low 8\r\n VPMOVZXWD xmm1 {k1}{z}, xmm2/m64 AVX512F bytes of xmm2/m64 to 4 packed 32-bit integers in\r\n xmm1 subject to writemask k1.\r\n EVEX.256.66.0F38.WIG 33 /r HVM V/V AVX512VL Zero extend 8 packed 16-bit integers in\r\n VPMOVZXWD ymm1 {k1}{z}, AVX512F xmm2/m128 to 8 packed 32-bit integers in zmm1\r\n xmm2/m128 subject to writemask k1.\r\n EVEX.512.66.0F38.WIG 33 /r HVM V/V AVX512F Zero extend 16 packed 16-bit integers in\r\n VPMOVZXWD zmm1 {k1}{z}, ymm2/m256 to 16 packed 32-bit integers in zmm1\r\n ymm2/m256 subject to writemask k1.\r\n EVEX.128.66.0F38.WIG 34 /r QVM V/V AVX512VL Zero extend 2 packed 16-bit integers in the low 4\r\n VPMOVZXWQ xmm1 {k1}{z}, xmm2/m32 AVX512F bytes of xmm2/m32 to 2 packed 64-bit integers in\r\n xmm1 subject to writemask k1.\r\n EVEX.256.66.0F38.WIG 34 /r QVM V/V AVX512VL Zero extend 4 packed 16-bit integers in the low 8\r\n VPMOVZXWQ ymm1 {k1}{z}, xmm2/m64 AVX512F bytes of xmm2/m64 to 4 packed 64-bit integers in\r\n ymm1 subject to writemask k1.\r\n EVEX.512.66.0F38.WIG 34 /r QVM V/V AVX512F Zero extend 8 packed 16-bit integers in\r\n VPMOVZXWQ zmm1 {k1}{z}, xmm2/m128 to 8 packed 64-bit integers in zmm1\r\n xmm2/m128 subject to writemask k1.\r\n\r\n\r\n\r\n\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F38.W0 35 /r HVM V/V AVX512VL Zero extend 2 packed 32-bit integers in the low 8\r\n VPMOVZXDQ xmm1 {k1}{z}, xmm2/m64 AVX512F bytes of xmm2/m64 to 2 packed 64-bit integers in\r\n zmm1 using writemask k1.\r\n EVEX.256.66.0F38.W0 35 /r HVM V/V AVX512VL Zero extend 4 packed 32-bit integers in\r\n VPMOVZXDQ ymm1 {k1}{z}, AVX512F xmm2/m128 to 4 packed 64-bit integers in zmm1\r\n xmm2/m128 using writemask k1.\r\n EVEX.512.66.0F38.W0 35 /r HVM V/V AVX512F Zero extend 8 packed 32-bit integers in\r\n VPMOVZXDQ zmm1 {k1}{z}, ymm2/m256 to 8 packed 64-bit integers in zmm1\r\n ymm2/m256 using writemask k1.\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n HVM, QVM, OVM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nLegacy, VEX and EVEX encoded versions: Packed byte, word, or dword integers starting from the low bytes of the\r\nsource operand (second operand) are zero extended to word, dword, or quadword integers and stored in packed\r\nsigned bytes the destination operand.\r\n128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register remain unchanged.\r\nVEX.128 encoded version: Bits (MAX_VL-1:128) of the corresponding destination register are zeroed.\r\nVEX.256 encoded version: Bits (MAX_VL-1:256) of the corresponding destination register are zeroed.\r\nEVEX encoded versions: Packed dword integers starting from the low bytes of the source operand (second\r\noperand) are zero extended to quadword integers and stored to the destination operand under the writemask.The\r\ndestination register is XMM, YMM or ZMM Register.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\n\r\nOperation\r\nPacked_Zero_Extend_BYTE_to_WORD(DEST, SRC)\r\nDEST[15:0] <-ZeroExtend(SRC[7:0]);\r\nDEST[31:16] <-ZeroExtend(SRC[15:8]);\r\nDEST[47:32] <-ZeroExtend(SRC[23:16]);\r\nDEST[63:48] <-ZeroExtend(SRC[31:24]);\r\nDEST[79:64] <-ZeroExtend(SRC[39:32]);\r\nDEST[95:80] <-ZeroExtend(SRC[47:40]);\r\nDEST[111:96] <-ZeroExtend(SRC[55:48]);\r\nDEST[127:112] <-ZeroExtend(SRC[63:56]);\r\n\r\nPacked_Zero_Extend_BYTE_to_DWORD(DEST, SRC)\r\nDEST[31:0] <-ZeroExtend(SRC[7:0]);\r\nDEST[63:32] <-ZeroExtend(SRC[15:8]);\r\nDEST[95:64] <-ZeroExtend(SRC[23:16]);\r\nDEST[127:96] <-ZeroExtend(SRC[31:24]);\r\n\r\nPacked_Zero_Extend_BYTE_to_QWORD(DEST, SRC)\r\nDEST[63:0] <-ZeroExtend(SRC[7:0]);\r\nDEST[127:64] <-ZeroExtend(SRC[15:8]);\r\n\r\n\r\n\r\n\r\n\r\nPacked_Zero_Extend_WORD_to_DWORD(DEST, SRC)\r\nDEST[31:0] <-ZeroExtend(SRC[15:0]);\r\nDEST[63:32] <-ZeroExtend(SRC[31:16]);\r\nDEST[95:64] <-ZeroExtend(SRC[47:32]);\r\nDEST[127:96] <-ZeroExtend(SRC[63:48]);\r\n\r\nPacked_Zero_Extend_WORD_to_QWORD(DEST, SRC)\r\nDEST[63:0] <-ZeroExtend(SRC[15:0]);\r\nDEST[127:64] <-ZeroExtend(SRC[31:16]);\r\n\r\nPacked_Zero_Extend_DWORD_to_QWORD(DEST, SRC)\r\nDEST[63:0] <-ZeroExtend(SRC[31:0]);\r\nDEST[127:64] <-ZeroExtend(SRC[63:32]);\r\n\r\nVPMOVZXBW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nPacked_Zero_Extend_BYTE_to_WORD(TMP_DEST[127:0], SRC[63:0])\r\nIF VL >= 256\r\n Packed_Zero_Extend_BYTE_to_WORD(TMP_DEST[255:128], SRC[127:64])\r\nFI;\r\nIF VL >= 512\r\n Packed_Zero_Extend_BYTE_to_WORD(TMP_DEST[383:256], SRC[191:128])\r\n Packed_Zero_Extend_BYTE_to_WORD(TMP_DEST[511:384], SRC[255:192])\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- TEMP_DEST[i+15:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPMOVZXBD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nPacked_Zero_Extend_BYTE_to_DWORD(TMP_DEST[127:0], SRC[31:0])\r\nIF VL >= 256\r\n Packed_Zero_Extend_BYTE_to_DWORD(TMP_DEST[255:128], SRC[63:32])\r\nFI;\r\nIF VL >= 512\r\n Packed_Zero_Extend_BYTE_to_DWORD(TMP_DEST[383:256], SRC[95:64])\r\n Packed_Zero_Extend_BYTE_to_DWORD(TMP_DEST[511:384], SRC[127:96])\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TEMP_DEST[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n\r\n\r\n\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPMOVZXBQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nPacked_Zero_Extend_BYTE_to_QWORD(TMP_DEST[127:0], SRC[15:0])\r\nIF VL >= 256\r\n Packed_Zero_Extend_BYTE_to_QWORD(TMP_DEST[255:128], SRC[31:16])\r\nFI;\r\nIF VL >= 512\r\n Packed_Zero_Extend_BYTE_to_QWORD(TMP_DEST[383:256], SRC[47:32])\r\n Packed_Zero_Extend_BYTE_to_QWORD(TMP_DEST[511:384], SRC[63:48])\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TEMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPMOVZXWD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nPacked_Zero_Extend_WORD_to_DWORD(TMP_DEST[127:0], SRC[63:0])\r\nIF VL >= 256\r\n Packed_Zero_Extend_WORD_to_DWORD(TMP_DEST[255:128], SRC[127:64])\r\nFI;\r\nIF VL >= 512\r\n Packed_Zero_Extend_WORD_to_DWORD(TMP_DEST[383:256], SRC[191:128])\r\n Packed_Zero_Extend_WORD_to_DWORD(TMP_DEST[511:384], SRC[256:192])\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TEMP_DEST[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\n\r\n\r\n\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPMOVZXWQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nPacked_Zero_Extend_WORD_to_QWORD(TMP_DEST[127:0], SRC[31:0])\r\nIF VL >= 256\r\n Packed_Zero_Extend_WORD_to_QWORD(TMP_DEST[255:128], SRC[63:32])\r\nFI;\r\nIF VL >= 512\r\n Packed_Zero_Extend_WORD_to_QWORD(TMP_DEST[383:256], SRC[95:64])\r\n Packed_Zero_Extend_WORD_to_QWORD(TMP_DEST[511:384], SRC[127:96])\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TEMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPMOVZXDQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nPacked_Zero_Extend_DWORD_to_QWORD(TEMP_DEST[127:0], SRC[63:0])\r\nIF VL >= 256\r\n Packed_Zero_Extend_DWORD_to_QWORD(TEMP_DEST[255:128], SRC[127:64])\r\nFI;\r\nIF VL >= 512\r\n Packed_Zero_Extend_DWORD_to_QWORD(TEMP_DEST[383:256], SRC[191:128])\r\n Packed_Zero_Extend_DWORD_to_QWORD(TEMP_DEST[511:384], SRC[255:192])\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TEMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPMOVZXBW (VEX.256 encoded version)\r\nPacked_Zero_Extend_BYTE_to_WORD(DEST[127:0], SRC[63:0])\r\nPacked_Zero_Extend_BYTE_to_WORD(DEST[255:128], SRC[127:64])\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\n\r\n\r\nVPMOVZXBD (VEX.256 encoded version)\r\nPacked_Zero_Extend_BYTE_to_DWORD(DEST[127:0], SRC[31:0])\r\nPacked_Zero_Extend_BYTE_to_DWORD(DEST[255:128], SRC[63:32])\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVPMOVZXBQ (VEX.256 encoded version)\r\nPacked_Zero_Extend_BYTE_to_QWORD(DEST[127:0], SRC[15:0])\r\nPacked_Zero_Extend_BYTE_to_QWORD(DEST[255:128], SRC[31:16])\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVPMOVZXWD (VEX.256 encoded version)\r\nPacked_Zero_Extend_WORD_to_DWORD(DEST[127:0], SRC[63:0])\r\nPacked_Zero_Extend_WORD_to_DWORD(DEST[255:128], SRC[127:64])\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVPMOVZXWQ (VEX.256 encoded version)\r\nPacked_Zero_Extend_WORD_to_QWORD(DEST[127:0], SRC[31:0])\r\nPacked_Zero_Extend_WORD_to_QWORD(DEST[255:128], SRC[63:32])\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVPMOVZXDQ (VEX.256 encoded version)\r\nPacked_Zero_Extend_DWORD_to_QWORD(DEST[127:0], SRC[63:0])\r\nPacked_Zero_Extend_DWORD_to_QWORD(DEST[255:128], SRC[127:64])\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVPMOVZXBW (VEX.128 encoded version)\r\nPacked_Zero_Extend_BYTE_to_WORD()\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVPMOVZXBD (VEX.128 encoded version)\r\nPacked_Zero_Extend_BYTE_to_DWORD()\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVPMOVZXBQ (VEX.128 encoded version)\r\nPacked_Zero_Extend_BYTE_to_QWORD()\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVPMOVZXWD (VEX.128 encoded version)\r\nPacked_Zero_Extend_WORD_to_DWORD()\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVPMOVZXWQ (VEX.128 encoded version)\r\nPacked_Zero_Extend_WORD_to_QWORD()\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVPMOVZXDQ (VEX.128 encoded version)\r\nPacked_Zero_Extend_DWORD_to_QWORD()\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nPMOVZXBW\r\nPacked_Zero_Extend_BYTE_to_WORD()\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\n\r\n\r\n\r\nPMOVZXBD\r\nPacked_Zero_Extend_BYTE_to_DWORD()\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nPMOVZXBQ\r\nPacked_Zero_Extend_BYTE_to_QWORD()\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nPMOVZXWD\r\nPacked_Zero_Extend_WORD_to_DWORD()\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nPMOVZXWQ\r\nPacked_Zero_Extend_WORD_to_QWORD()\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nPMOVZXDQ\r\nPacked_Zero_Extend_DWORD_to_QWORD()\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPMOVZXBW __m512i _mm512_cvtepu8_epi16(__m256i a);\r\nVPMOVZXBW __m512i _mm512_mask_cvtepu8_epi16(__m512i a, __mmask32 k, __m256i b);\r\nVPMOVZXBW __m512i _mm512_maskz_cvtepu8_epi16( __mmask32 k, __m256i b);\r\nVPMOVZXBD __m512i _mm512_cvtepu8_epi32(__m128i a);\r\nVPMOVZXBD __m512i _mm512_mask_cvtepu8_epi32(__m512i a, __mmask16 k, __m128i b);\r\nVPMOVZXBD __m512i _mm512_maskz_cvtepu8_epi32( __mmask16 k, __m128i b);\r\nVPMOVZXBQ __m512i _mm512_cvtepu8_epi64(__m128i a);\r\nVPMOVZXBQ __m512i _mm512_mask_cvtepu8_epi64(__m512i a, __mmask8 k, __m128i b);\r\nVPMOVZXBQ __m512i _mm512_maskz_cvtepu8_epi64( __mmask8 k, __m128i a);\r\nVPMOVZXDQ __m512i _mm512_cvtepu32_epi64(__m256i a);\r\nVPMOVZXDQ __m512i _mm512_mask_cvtepu32_epi64(__m512i a, __mmask8 k, __m256i b);\r\nVPMOVZXDQ __m512i _mm512_maskz_cvtepu32_epi64( __mmask8 k, __m256i a);\r\nVPMOVZXWD __m512i _mm512_cvtepu16_epi32(__m128i a);\r\nVPMOVZXWD __m512i _mm512_mask_cvtepu16_epi32(__m512i a, __mmask16 k, __m128i b);\r\nVPMOVZXWD __m512i _mm512_maskz_cvtepu16_epi32(__mmask16 k, __m128i a);\r\nVPMOVZXWQ __m512i _mm512_cvtepu16_epi64(__m256i a);\r\nVPMOVZXWQ __m512i _mm512_mask_cvtepu16_epi64(__m512i a, __mmask8 k, __m256i b);\r\nVPMOVZXWQ __m512i _mm512_maskz_cvtepu16_epi64( __mmask8 k, __m256i a);\r\nVPMOVZXBW __m256i _mm256_cvtepu8_epi16(__m256i a);\r\nVPMOVZXBW __m256i _mm256_mask_cvtepu8_epi16(__m256i a, __mmask16 k, __m128i b);\r\nVPMOVZXBW __m256i _mm256_maskz_cvtepu8_epi16( __mmask16 k, __m128i b);\r\nVPMOVZXBD __m256i _mm256_cvtepu8_epi32(__m128i a);\r\nVPMOVZXBD __m256i _mm256_mask_cvtepu8_epi32(__m256i a, __mmask8 k, __m128i b);\r\nVPMOVZXBD __m256i _mm256_maskz_cvtepu8_epi32( __mmask8 k, __m128i b);\r\nVPMOVZXBQ __m256i _mm256_cvtepu8_epi64(__m128i a);\r\nVPMOVZXBQ __m256i _mm256_mask_cvtepu8_epi64(__m256i a, __mmask8 k, __m128i b);\r\nVPMOVZXBQ __m256i _mm256_maskz_cvtepu8_epi64( __mmask8 k, __m128i a);\r\nVPMOVZXDQ __m256i _mm256_cvtepu32_epi64(__m128i a);\r\nVPMOVZXDQ __m256i _mm256_mask_cvtepu32_epi64(__m256i a, __mmask8 k, __m128i b);\r\nVPMOVZXDQ __m256i _mm256_maskz_cvtepu32_epi64( __mmask8 k, __m128i a);\r\nVPMOVZXWD __m256i _mm256_cvtepu16_epi32(__m128i a);\r\nVPMOVZXWD __m256i _mm256_mask_cvtepu16_epi32(__m256i a, __mmask16 k, __m128i b);\r\nVPMOVZXWD __m256i _mm256_maskz_cvtepu16_epi32(__mmask16 k, __m128i a);\r\n\r\n\r\n\r\nVPMOVZXWQ __m256i _mm256_cvtepu16_epi64(__m128i a);\r\nVPMOVZXWQ __m256i _mm256_mask_cvtepu16_epi64(__m256i a, __mmask8 k, __m128i b);\r\nVPMOVZXWQ __m256i _mm256_maskz_cvtepu16_epi64( __mmask8 k, __m128i a);\r\nVPMOVZXBW __m128i _mm_mask_cvtepu8_epi16(__m128i a, __mmask8 k, __m128i b);\r\nVPMOVZXBW __m128i _mm_maskz_cvtepu8_epi16( __mmask8 k, __m128i b);\r\nVPMOVZXBD __m128i _mm_mask_cvtepu8_epi32(__m128i a, __mmask8 k, __m128i b);\r\nVPMOVZXBD __m128i _mm_maskz_cvtepu8_epi32( __mmask8 k, __m128i b);\r\nVPMOVZXBQ __m128i _mm_mask_cvtepu8_epi64(__m128i a, __mmask8 k, __m128i b);\r\nVPMOVZXBQ __m128i _mm_maskz_cvtepu8_epi64( __mmask8 k, __m128i a);\r\nVPMOVZXDQ __m128i _mm_mask_cvtepu32_epi64(__m128i a, __mmask8 k, __m128i b);\r\nVPMOVZXDQ __m128i _mm_maskz_cvtepu32_epi64( __mmask8 k, __m128i a);\r\nVPMOVZXWD __m128i _mm_mask_cvtepu16_epi32(__m128i a, __mmask16 k, __m128i b);\r\nVPMOVZXWD __m128i _mm_maskz_cvtepu16_epi32(__mmask8 k, __m128i a);\r\nVPMOVZXWQ __m128i _mm_mask_cvtepu16_epi64(__m128i a, __mmask8 k, __m128i b);\r\nVPMOVZXWQ __m128i _mm_maskz_cvtepu16_epi64( __mmask8 k, __m128i a);\r\nPMOVZXBW __m128i _mm_ cvtepu8_epi16 ( __m128i a);\r\nPMOVZXBD __m128i _mm_ cvtepu8_epi32 ( __m128i a);\r\nPMOVZXBQ __m128i _mm_ cvtepu8_epi64 ( __m128i a);\r\nPMOVZXWD __m128i _mm_ cvtepu16_epi32 ( __m128i a);\r\nPMOVZXWQ __m128i _mm_ cvtepu16_epi64 ( __m128i a);\r\nPMOVZXDQ __m128i _mm_ cvtepu32_epi64 ( __m128i a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 5.\r\nEVEX-encoded instruction, see Exceptions Type E5.\r\n#UD If VEX.vvvv != 1111B, or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PMOVZX"
},
{
"description": "PMULDQ-Multiply Packed Doubleword Integers\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0F 38 28 /r RM V/V SSE4_1 Multiply packed signed doubleword integers in xmm1 by\r\n PMULDQ xmm1, xmm2/m128 packed signed doubleword integers in xmm2/m128, and\r\n store the quadword results in xmm1.\r\n VEX.NDS.128.66.0F38.WIG 28 /r RVM V/V AVX Multiply packed signed doubleword integers in xmm2 by\r\n VPMULDQ xmm1, xmm2, packed signed doubleword integers in xmm3/m128, and\r\n xmm3/m128 store the quadword results in xmm1.\r\n VEX.NDS.256.66.0F38.WIG 28 /r RVM V/V AVX2 Multiply packed signed doubleword integers in ymm2 by\r\n VPMULDQ ymm1, ymm2, packed signed doubleword integers in ymm3/m256, and\r\n ymm3/m256 store the quadword results in ymm1.\r\n EVEX.NDS.128.66.0F38.W1 28 /r FV V/V AVX512VL Multiply packed signed doubleword integers in xmm2 by\r\n VPMULDQ xmm1 {k1}{z}, xmm2, AVX512F packed signed doubleword integers in\r\n xmm3/m128/m64bcst xmm3/m128/m64bcst, and store the quadword results in\r\n xmm1 using writemask k1.\r\n EVEX.NDS.256.66.0F38.W1 28 /r FV V/V AVX512VL Multiply packed signed doubleword integers in ymm2 by\r\n VPMULDQ ymm1 {k1}{z}, ymm2, AVX512F packed signed doubleword integers in\r\n ymm3/m256/m64bcst ymm3/m256/m64bcst, and store the quadword results in\r\n ymm1 using writemask k1.\r\n EVEX.NDS.512.66.0F38.W1 28 /r FV V/V AVX512F Multiply packed signed doubleword integers in zmm2 by\r\n VPMULDQ zmm1 {k1}{z}, zmm2, packed signed doubleword integers in\r\n zmm3/m512/m64bcst zmm3/m512/m64bcst, and store the quadword results in\r\n zmm1 using writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nMultiplies packed signed doubleword integers in the even-numbered (zero-based reference) elements of the first\r\nsource operand with the packed signed doubleword integers in the corresponding elements of the second source\r\noperand and stores packed signed quadword results in the destination operand.\r\n128-bit Legacy SSE version: The input signed doubleword integers are taken from the even-numbered elements of\r\nthe source operands, i.e. the first (low) and third doubleword element. For 128-bit memory operands, 128 bits are\r\nfetched from memory, but only the first and third doublewords are used in the computation. The first source\r\noperand and the destination XMM operand is the same. The second source operand can be an XMM register or 128-\r\nbit memory location. Bits (MAX_VL-1:128) of the corresponding destination register remain unchanged.\r\nVEX.128 encoded version: The input signed doubleword integers are taken from the even-numbered elements of\r\nthe source operands, i.e., the first (low) and third doubleword element. For 128-bit memory operands, 128 bits are\r\nfetched from memory, but only the first and third doublewords are used in the computation.The first source\r\noperand and the destination operand are XMM registers. The second source operand can be an XMM register or\r\n128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination register are zeroed.\r\nVEX.256 encoded version: The input signed doubleword integers are taken from the even-numbered elements of\r\nthe source operands, i.e. the first, 3rd, 5th, 7th doubleword element. For 256-bit memory operands, 256 bits are\r\nfetched from memory, but only the four even-numbered doublewords are used in the computation. The first source\r\noperand and the destination operand are YMM registers. The second source operand can be a YMM register or 256-\r\nbit memory location. Bits (MAX_VL-1:256) of the corresponding destination ZMM register are zeroed.\r\n\r\n\r\n\r\n\r\n\r\nEVEX encoded version: The input signed doubleword integers are taken from the even-numbered elements of the\r\nsource operands. The first source operand is a ZMM/YMM/XMM registers. The second source operand can be an\r\nZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-\r\nbit memory location. The destination is a ZMM/YMM/XMM register, and updated according to the writemask at 64-\r\nbit granularity.\r\n\r\nOperation\r\nVPMULDQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN DEST[i+63:i] <- SignExtend64( SRC1[i+31:i]) * SignExtend64( SRC2[31:0])\r\n ELSE DEST[i+63:i] <- SignExtend64( SRC1[i+31:i]) * SignExtend64( SRC2[i+31:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPMULDQ (VEX.256 encoded version)\r\nDEST[63:0] <-SignExtend64( SRC1[31:0]) * SignExtend64( SRC2[31:0])\r\nDEST[127:64] <-SignExtend64( SRC1[95:64]) * SignExtend64( SRC2[95:64])\r\nDEST[191:128] <-SignExtend64( SRC1[159:128]) * SignExtend64( SRC2[159:128])\r\nDEST[255:192] <-SignExtend64( SRC1[223:192]) * SignExtend64( SRC2[223:192])\r\nDEST[MAX_VL-1:256] <-0\r\n\r\nVPMULDQ (VEX.128 encoded version)\r\nDEST[63:0] <-SignExtend64( SRC1[31:0]) * SignExtend64( SRC2[31:0])\r\nDEST[127:64] <-SignExtend64( SRC1[95:64]) * SignExtend64( SRC2[95:64])\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nPMULDQ (128-bit Legacy SSE version)\r\nDEST[63:0] <-SignExtend64( DEST[31:0]) * SignExtend64( SRC[31:0])\r\nDEST[127:64] <-SignExtend64( DEST[95:64]) * SignExtend64( SRC[95:64])\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPMULDQ __m512i _mm512_mul_epi32(__m512i a, __m512i b);\r\nVPMULDQ __m512i _mm512_mask_mul_epi32(__m512i s, __mmask8 k, __m512i a, __m512i b);\r\nVPMULDQ __m512i _mm512_maskz_mul_epi32( __mmask8 k, __m512i a, __m512i b);\r\nVPMULDQ __m256i _mm256_mask_mul_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);\r\nVPMULDQ __m256i _mm256_mask_mul_epi32( __mmask8 k, __m256i a, __m256i b);\r\nVPMULDQ __m128i _mm_mask_mul_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPMULDQ __m128i _mm_mask_mul_epi32( __mmask8 k, __m128i a, __m128i b);\r\n(V)PMULDQ __m128i _mm_mul_epi32( __m128i a, __m128i b);\r\nVPMULDQ __m256i _mm256_mul_epi32( __m256i a, __m256i b);\r\n\r\n\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PMULDQ"
},
{
"description": "PMULHRSW - Packed Multiply High with Round and Scale\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F 38 0B /r1 RM V/V SSSE3 Multiply 16-bit signed words, scale and round\r\nPMULHRSW mm1, mm2/m64 signed doublewords, pack high 16 bits to\r\n mm1.\r\n66 0F 38 0B /r RM V/V SSSE3 Multiply 16-bit signed words, scale and round\r\nPMULHRSW xmm1, xmm2/m128 signed doublewords, pack high 16 bits to\r\n xmm1.\r\nVEX.NDS.128.66.0F38.WIG 0B /r RVM V/V AVX Multiply 16-bit signed words, scale and round\r\nVPMULHRSW xmm1, xmm2, xmm3/m128 signed doublewords, pack high 16 bits to\r\n xmm1.\r\nVEX.NDS.256.66.0F38.WIG 0B /r RVM V/V AVX2 Multiply 16-bit signed words, scale and round\r\nVPMULHRSW ymm1, ymm2, ymm3/m256 signed doublewords, pack high 16 bits to\r\n ymm1.\r\nEVEX.NDS.128.66.0F38.WIG 0B /r FVM V/V AVX512VL Multiply 16-bit signed words, scale and round\r\nVPMULHRSW xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512BW signed doublewords, pack high 16 bits to\r\n xmm1 under writemask k1.\r\nEVEX.NDS.256.66.0F38.WIG 0B /r FVM V/V AVX512VL Multiply 16-bit signed words, scale and round\r\nVPMULHRSW ymm1 {k1}{z}, ymm2, ymm3/m256 AVX512BW signed doublewords, pack high 16 bits to\r\n ymm1 under writemask k1.\r\nEVEX.NDS.512.66.0F38.WIG 0B /r FVM V/V AVX512BW Multiply 16-bit signed words, scale and round\r\nVPMULHRSW zmm1 {k1}{z}, zmm2, zmm3/m512 signed doublewords, pack high 16 bits to\r\n zmm1 under writemask k1.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nPMULHRSW multiplies vertically each signed 16-bit integer from the destination operand (first operand) with the\r\ncorresponding signed 16-bit integer of the source operand (second operand), producing intermediate, signed 32-\r\nbit integers. Each intermediate 32-bit integer is truncated to the 18 most significant bits. Rounding is always\r\nperformed by adding 1 to the least significant bit of the 18-bit intermediate result. The final result is obtained by\r\nselecting the 16 bits immediately to the right of the most significant bit of each 18-bit intermediate result and\r\npacked to the destination operand.\r\nWhen the source operand is a 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a\r\ngeneral-protection exception (#GP) will be generated.\r\nIn 64-bit mode and not encoded with VEX/EVEX, use the REX prefix to access XMM8-XMM15 registers.\r\nLegacy SSE version 64-bit operand: Both operands can be MMX registers. The second source operand is an MMX\r\nregister or a 64-bit memory location.\r\n\r\n\r\n\r\n\r\n\r\n128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destina-\r\ntion register remain unchanged.\r\nVEX.128 encoded version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are\r\nzeroed.\r\nVEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The\r\nfirst source and destination operands are YMM registers.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be\r\na ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand is a ZMM/YMM/XMM\r\nregister conditionally updated with writemask k1.\r\n\r\nOperation\r\nPMULHRSW (with 64-bit operands)\r\n temp0[31:0] = INT32 ((DEST[15:0] * SRC[15:0]) >>14) + 1;\r\n temp1[31:0] = INT32 ((DEST[31:16] * SRC[31:16]) >>14) + 1;\r\n temp2[31:0] = INT32 ((DEST[47:32] * SRC[47:32]) >> 14) + 1;\r\n temp3[31:0] = INT32 ((DEST[63:48] * SRc[63:48]) >> 14) + 1;\r\n DEST[15:0] = temp0[16:1];\r\n DEST[31:16] = temp1[16:1];\r\n DEST[47:32] = temp2[16:1];\r\n DEST[63:48] = temp3[16:1];\r\n\r\nPMULHRSW (with 128-bit operand)\r\n temp0[31:0] = INT32 ((DEST[15:0] * SRC[15:0]) >>14) + 1;\r\n temp1[31:0] = INT32 ((DEST[31:16] * SRC[31:16]) >>14) + 1;\r\n temp2[31:0] = INT32 ((DEST[47:32] * SRC[47:32]) >>14) + 1;\r\n temp3[31:0] = INT32 ((DEST[63:48] * SRC[63:48]) >>14) + 1;\r\n temp4[31:0] = INT32 ((DEST[79:64] * SRC[79:64]) >>14) + 1;\r\n temp5[31:0] = INT32 ((DEST[95:80] * SRC[95:80]) >>14) + 1;\r\n temp6[31:0] = INT32 ((DEST[111:96] * SRC[111:96]) >>14) + 1;\r\n temp7[31:0] = INT32 ((DEST[127:112] * SRC[127:112) >>14) + 1;\r\n DEST[15:0] = temp0[16:1];\r\n DEST[31:16] = temp1[16:1];\r\n DEST[47:32] = temp2[16:1];\r\n DEST[63:48] = temp3[16:1];\r\n DEST[79:64] = temp4[16:1];\r\n DEST[95:80] = temp5[16:1];\r\n DEST[111:96] = temp6[16:1];\r\n DEST[127:112] = temp7[16:1];\r\n\r\nVPMULHRSW (VEX.128 encoded version)\r\ntemp0[31:0] <- INT32 ((SRC1[15:0] * SRC2[15:0]) >>14) + 1\r\ntemp1[31:0] <- INT32 ((SRC1[31:16] * SRC2[31:16]) >>14) + 1\r\ntemp2[31:0] <- INT32 ((SRC1[47:32] * SRC2[47:32]) >>14) + 1\r\ntemp3[31:0] <- INT32 ((SRC1[63:48] * SRC2[63:48]) >>14) + 1\r\ntemp4[31:0] <- INT32 ((SRC1[79:64] * SRC2[79:64]) >>14) + 1\r\ntemp5[31:0] <- INT32 ((SRC1[95:80] * SRC2[95:80]) >>14) + 1\r\ntemp6[31:0] <- INT32 ((SRC1[111:96] * SRC2[111:96]) >>14) + 1\r\ntemp7[31:0] <- INT32 ((SRC1[127:112] * SRC2[127:112) >>14) + 1\r\nDEST[15:0] <- temp0[16:1]\r\nDEST[31:16] <- temp1[16:1]\r\nDEST[47:32] <- temp2[16:1]\r\n\r\n\r\n\r\nDEST[63:48] <- temp3[16:1]\r\nDEST[79:64] <- temp4[16:1]\r\nDEST[95:80] <- temp5[16:1]\r\nDEST[111:96] <- temp6[16:1]\r\nDEST[127:112] <- temp7[16:1]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPMULHRSW (VEX.256 encoded version)\r\ntemp0[31:0] <- INT32 ((SRC1[15:0] * SRC2[15:0]) >>14) + 1\r\ntemp1[31:0] <- INT32 ((SRC1[31:16] * SRC2[31:16]) >>14) + 1\r\ntemp2[31:0] <- INT32 ((SRC1[47:32] * SRC2[47:32]) >>14) + 1\r\ntemp3[31:0] <- INT32 ((SRC1[63:48] * SRC2[63:48]) >>14) + 1\r\ntemp4[31:0] <- INT32 ((SRC1[79:64] * SRC2[79:64]) >>14) + 1\r\ntemp5[31:0] <- INT32 ((SRC1[95:80] * SRC2[95:80]) >>14) + 1\r\ntemp6[31:0] <- INT32 ((SRC1[111:96] * SRC2[111:96]) >>14) + 1\r\ntemp7[31:0] <- INT32 ((SRC1[127:112] * SRC2[127:112) >>14) + 1\r\ntemp8[31:0] <- INT32 ((SRC1[143:128] * SRC2[143:128]) >>14) + 1\r\ntemp9[31:0] <- INT32 ((SRC1[159:144] * SRC2[159:144]) >>14) + 1\r\ntemp10[31:0] <- INT32 ((SRC1[75:160] * SRC2[175:160]) >>14) + 1\r\ntemp11[31:0] <- INT32 ((SRC1[191:176] * SRC2[191:176]) >>14) + 1\r\ntemp12[31:0] <- INT32 ((SRC1[207:192] * SRC2[207:192]) >>14) + 1\r\ntemp13[31:0] <- INT32 ((SRC1[223:208] * SRC2[223:208]) >>14) + 1\r\ntemp14[31:0] <- INT32 ((SRC1[239:224] * SRC2[239:224]) >>14) + 1\r\ntemp15[31:0] <- INT32 ((SRC1[255:240] * SRC2[255:240) >>14) + 1\r\n\r\nDEST[15:0] <- temp0[16:1]\r\nDEST[31:16] <- temp1[16:1]\r\nDEST[47:32] <- temp2[16:1]\r\nDEST[63:48] <- temp3[16:1]\r\nDEST[79:64] <- temp4[16:1]\r\nDEST[95:80] <- temp5[16:1]\r\nDEST[111:96] <- temp6[16:1]\r\nDEST[127:112] <- temp7[16:1]\r\nDEST[143:128] <- temp8[16:1]\r\nDEST[159:144] <- temp9[16:1]\r\nDEST[175:160] <- temp10[16:1]\r\nDEST[191:176] <- temp11[16:1]\r\nDEST[207:192] <- temp12[16:1]\r\nDEST[223:208] <- temp13[16:1]\r\nDEST[239:224] <- temp14[16:1]\r\nDEST[255:240] <- temp15[16:1]\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVPMULHRSW (EVEX encoded version)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n temp[31:0] <- ((SRC1[i+15:i] * SRC2[i+15:i]) >>14) + 1\r\n DEST[i+15:i] <- tmp[16:1]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n\r\n\r\n\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPMULHRSW __m512i _mm512_mulhrs_epi16(__m512i a, __m512i b);\r\nVPMULHRSW __m512i _mm512_mask_mulhrs_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);\r\nVPMULHRSW __m512i _mm512_maskz_mulhrs_epi16( __mmask32 k, __m512i a, __m512i b);\r\nVPMULHRSW __m256i _mm256_mask_mulhrs_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);\r\nVPMULHRSW __m256i _mm256_maskz_mulhrs_epi16( __mmask16 k, __m256i a, __m256i b);\r\nVPMULHRSW __m128i _mm_mask_mulhrs_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPMULHRSW __m128i _mm_maskz_mulhrs_epi16( __mmask8 k, __m128i a, __m128i b);\r\nPMULHRSW: __m64 _mm_mulhrs_pi16 (__m64 a, __m64 b)\r\n(V)PMULHRSW: __m128i _mm_mulhrs_epi16 (__m128i a, __m128i b)\r\nVPMULHRSW:__m256i _mm256_mulhrs_epi16 (__m256i a, __m256i b)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PMULHRSW"
},
{
"description": "PMULHUW-Multiply Packed Unsigned Integers and Store High Result\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F E4 /r1 RM V/V SSE Multiply the packed unsigned word integers in\r\nPMULHUW mm1, mm2/m64 mm1 register and mm2/m64, and store the\r\n high 16 bits of the results in mm1.\r\n66 0F E4 /r RM V/V SSE2 Multiply the packed unsigned word integers in\r\nPMULHUW xmm1, xmm2/m128 xmm1 and xmm2/m128, and store the high\r\n 16 bits of the results in xmm1.\r\nVEX.NDS.128.66.0F.WIG E4 /r RVM V/V AVX Multiply the packed unsigned word integers in\r\nVPMULHUW xmm1, xmm2, xmm3/m128 xmm2 and xmm3/m128, and store the high\r\n 16 bits of the results in xmm1.\r\nVEX.NDS.256.66.0F.WIG E4 /r RVM V/V AVX2 Multiply the packed unsigned word integers in\r\nVPMULHUW ymm1, ymm2, ymm3/m256 ymm2 and ymm3/m256, and store the high\r\n 16 bits of the results in ymm1.\r\nEVEX.NDS.128.66.0F.WIG E4 /r FVM V/V AVX512VL Multiply the packed unsigned word integers in\r\nVPMULHUW xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512BW xmm2 and xmm3/m128, and store the high\r\n 16 bits of the results in xmm1 under\r\n writemask k1.\r\nEVEX.NDS.256.66.0F.WIG E4 /r FVM V/V AVX512VL Multiply the packed unsigned word integers in\r\nVPMULHUW ymm1 {k1}{z}, ymm2, ymm3/m256 AVX512BW ymm2 and ymm3/m256, and store the high\r\n 16 bits of the results in ymm1 under\r\n writemask k1.\r\nEVEX.NDS.512.66.0F.WIG E4 /r FVM V/V AVX512BW Multiply the packed unsigned word integers in\r\nVPMULHUW zmm1 {k1}{z}, zmm2, zmm3/m512 zmm2 and zmm3/m512, and store the high 16\r\n bits of the results in zmm1 under writemask\r\n k1.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nPerforms a SIMD unsigned multiply of the packed unsigned word integers in the destination operand (first operand)\r\nand the source operand (second operand), and stores the high 16 bits of each 32-bit intermediate results in the\r\ndestination operand. (Figure 4-12 shows this operation when using 64-bit operands.)\r\nIn 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to\r\naccess additional registers (XMM8-XMM15).\r\nLegacy SSE version 64-bit operand: The source operand can be an MMX technology register or a 64-bit memory\r\nlocation. The destination operand is an MMX technology register.\r\n128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destina-\r\ntion register remain unchanged.\r\n\r\n\r\n\r\nVEX.128 encoded version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are\r\nzeroed. VEX.L must be 0, otherwise the instruction will #UD.\r\nVEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The\r\nfirst source and destination operands are YMM registers.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be\r\na ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand is a ZMM/YMM/XMM\r\nregister conditionally updated with writemask k1.\r\n\r\n\r\n\r\n\r\n SRC X3 X2 X1 X0\r\n\r\n\r\n DEST Y3 Y2 Y1 Y0\r\n\r\n\r\n TEMP Z3 = X3 * Y3 Z2 = X2 * Y2 Z1 = X1 * Y1 Z0 = X0 * Y0\r\n\r\n\r\n DEST Z3[31:16] Z2[31:16] Z1[31:16] Z0[31:16]\r\n\r\n\r\n Figure 4-12. PMULHUW and PMULHW Instruction Operation Using 64-bit Operands\r\n\r\n\r\nOperation\r\nPMULHUW (with 64-bit operands)\r\n TEMP0[31:0] <- DEST[15:0] * SRC[15:0]; (* Unsigned multiplication *)\r\n TEMP1[31:0] <- DEST[31:16] * SRC[31:16];\r\n TEMP2[31:0] <- DEST[47:32] * SRC[47:32];\r\n TEMP3[31:0] <- DEST[63:48] * SRC[63:48];\r\n DEST[15:0] <- TEMP0[31:16];\r\n DEST[31:16] <- TEMP1[31:16];\r\n DEST[47:32] <- TEMP2[31:16];\r\n DEST[63:48] <- TEMP3[31:16];\r\n\r\nPMULHUW (with 128-bit operands)\r\n TEMP0[31:0] <- DEST[15:0] * SRC[15:0]; (* Unsigned multiplication *)\r\n TEMP1[31:0] <- DEST[31:16] * SRC[31:16];\r\n TEMP2[31:0] <- DEST[47:32] * SRC[47:32];\r\n TEMP3[31:0] <- DEST[63:48] * SRC[63:48];\r\n TEMP4[31:0] <- DEST[79:64] * SRC[79:64];\r\n TEMP5[31:0] <- DEST[95:80] * SRC[95:80];\r\n TEMP6[31:0] <- DEST[111:96] * SRC[111:96];\r\n TEMP7[31:0] <- DEST[127:112] * SRC[127:112];\r\n DEST[15:0] <- TEMP0[31:16];\r\n DEST[31:16] <- TEMP1[31:16];\r\n DEST[47:32] <- TEMP2[31:16];\r\n DEST[63:48] <- TEMP3[31:16];\r\n DEST[79:64] <- TEMP4[31:16];\r\n DEST[95:80] <- TEMP5[31:16];\r\n DEST[111:96] <- TEMP6[31:16];\r\n DEST[127:112] <- TEMP7[31:16];\r\n\r\nVPMULHUW (VEX.128 encoded version)\r\nTEMP0[31:0] <- SRC1[15:0] * SRC2[15:0]\r\n\r\n\r\n\r\nTEMP1[31:0] <- SRC1[31:16] * SRC2[31:16]\r\nTEMP2[31:0] <- SRC1[47:32] * SRC2[47:32]\r\nTEMP3[31:0] <- SRC1[63:48] * SRC2[63:48]\r\nTEMP4[31:0] <- SRC1[79:64] * SRC2[79:64]\r\nTEMP5[31:0] <- SRC1[95:80] * SRC2[95:80]\r\nTEMP6[31:0] <- SRC1[111:96] * SRC2[111:96]\r\nTEMP7[31:0] <- SRC1[127:112] * SRC2[127:112]\r\nDEST[15:0] <- TEMP0[31:16]\r\nDEST[31:16] <- TEMP1[31:16]\r\nDEST[47:32] <- TEMP2[31:16]\r\nDEST[63:48] <- TEMP3[31:16]\r\nDEST[79:64] <- TEMP4[31:16]\r\nDEST[95:80] <- TEMP5[31:16]\r\nDEST[111:96] <- TEMP6[31:16]\r\nDEST[127:112] <- TEMP7[31:16]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nPMULHUW (VEX.256 encoded version)\r\nTEMP0[31:0] <- SRC1[15:0] * SRC2[15:0]\r\nTEMP1[31:0] <- SRC1[31:16] * SRC2[31:16]\r\nTEMP2[31:0] <- SRC1[47:32] * SRC2[47:32]\r\nTEMP3[31:0] <- SRC1[63:48] * SRC2[63:48]\r\nTEMP4[31:0] <- SRC1[79:64] * SRC2[79:64]\r\nTEMP5[31:0] <- SRC1[95:80] * SRC2[95:80]\r\nTEMP6[31:0] <- SRC1[111:96] * SRC2[111:96]\r\nTEMP7[31:0] <- SRC1[127:112] * SRC2[127:112]\r\nTEMP8[31:0] <- SRC1[143:128] * SRC2[143:128]\r\nTEMP9[31:0] <- SRC1[159:144] * SRC2[159:144]\r\nTEMP10[31:0] <- SRC1[175:160] * SRC2[175:160]\r\nTEMP11[31:0] <- SRC1[191:176] * SRC2[191:176]\r\nTEMP12[31:0] <- SRC1[207:192] * SRC2[207:192]\r\nTEMP13[31:0] <- SRC1[223:208] * SRC2[223:208]\r\nTEMP14[31:0] <- SRC1[239:224] * SRC2[239:224]\r\nTEMP15[31:0] <- SRC1[255:240] * SRC2[255:240]\r\nDEST[15:0] <- TEMP0[31:16]\r\nDEST[31:16] <- TEMP1[31:16]\r\nDEST[47:32] <- TEMP2[31:16]\r\nDEST[63:48] <- TEMP3[31:16]\r\nDEST[79:64] <- TEMP4[31:16]\r\nDEST[95:80] <- TEMP5[31:16]\r\nDEST[111:96] <- TEMP6[31:16]\r\nDEST[127:112] <- TEMP7[31:16]\r\nDEST[143:128] <- TEMP8[31:16]\r\nDEST[159:144] <- TEMP9[31:16]\r\nDEST[175:160] <- TEMP10[31:16]\r\nDEST[191:176] <- TEMP11[31:16]\r\nDEST[207:192] <- TEMP12[31:16]\r\nDEST[223:208] <- TEMP13[31:16]\r\nDEST[239:224] <- TEMP14[31:16]\r\nDEST[255:240] <- TEMP15[31:16]\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nPMULHUW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\n\r\n\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n temp[31:0] <- SRC1[i+15:i] * SRC2[i+15:i]\r\n DEST[i+15:i] <- tmp[31:16]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPMULHUW __m512i _mm512_mulhi_epu16(__m512i a, __m512i b);\r\nVPMULHUW __m512i _mm512_mask_mulhi_epu16(__m512i s, __mmask32 k, __m512i a, __m512i b);\r\nVPMULHUW __m512i _mm512_maskz_mulhi_epu16( __mmask32 k, __m512i a, __m512i b);\r\nVPMULHUW __m256i _mm256_mask_mulhi_epu16(__m256i s, __mmask16 k, __m256i a, __m256i b);\r\nVPMULHUW __m256i _mm256_maskz_mulhi_epu16( __mmask16 k, __m256i a, __m256i b);\r\nVPMULHUW __m128i _mm_mask_mulhi_epu16(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPMULHUW __m128i _mm_maskz_mulhi_epu16( __mmask8 k, __m128i a, __m128i b);\r\nPMULHUW:__m64 _mm_mulhi_pu16(__m64 a, __m64 b)\r\n(V)PMULHUW:__m128i _mm_mulhi_epu16 ( __m128i a, __m128i b)\r\nVPMULHUW:__m256i _mm256_mulhi_epu16 ( __m256i a, __m256i b)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nNumeric Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PMULHUW"
},
{
"description": "PMULHW-Multiply Packed Signed Integers and Store High Result\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F E5 /r1 RM V/V MMX Multiply the packed signed word integers in mm1\r\nPMULHW mm, mm/m64 register and mm2/m64, and store the high 16\r\n bits of the results in mm1.\r\n66 0F E5 /r RM V/V SSE2 Multiply the packed signed word integers in\r\nPMULHW xmm1, xmm2/m128 xmm1 and xmm2/m128, and store the high 16\r\n bits of the results in xmm1.\r\nVEX.NDS.128.66.0F.WIG E5 /r RVM V/V AVX Multiply the packed signed word integers in\r\nVPMULHW xmm1, xmm2, xmm3/m128 xmm2 and xmm3/m128, and store the high 16\r\n bits of the results in xmm1.\r\nVEX.NDS.256.66.0F.WIG E5 /r RVM V/V AVX2 Multiply the packed signed word integers in\r\nVPMULHW ymm1, ymm2, ymm3/m256 ymm2 and ymm3/m256, and store the high 16\r\n bits of the results in ymm1.\r\nEVEX.NDS.128.66.0F.WIG E5 /r FVM V/V AVX512VL Multiply the packed signed word integers in\r\nVPMULHW xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512BW xmm2 and xmm3/m128, and store the high 16\r\n bits of the results in xmm1 under writemask k1.\r\nEVEX.NDS.256.66.0F.WIG E5 /r FVM V/V AVX512VL Multiply the packed signed word integers in\r\nVPMULHW ymm1 {k1}{z}, ymm2, ymm3/m256 AVX512BW ymm2 and ymm3/m256, and store the high 16\r\n bits of the results in ymm1 under writemask k1.\r\nEVEX.NDS.512.66.0F.WIG E5 /r FVM V/V AVX512BW Multiply the packed signed word integers in\r\nVPMULHW zmm1 {k1}{z}, zmm2, zmm3/m512 zmm2 and zmm3/m512, and store the high 16\r\n bits of the results in zmm1 under writemask k1.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nPerforms a SIMD signed multiply of the packed signed word integers in the destination operand (first operand) and\r\nthe source operand (second operand), and stores the high 16 bits of each intermediate 32-bit result in the destina-\r\ntion operand. (Figure 4-12 shows this operation when using 64-bit operands.)\r\nn 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to\r\naccess additional registers (XMM8-XMM15).\r\nLegacy SSE version 64-bit operand: The source operand can be an MMX technology register or a 64-bit memory\r\nlocation. The destination operand is an MMX technology register.\r\n128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destina-\r\ntion register remain unchanged.\r\nVEX.128 encoded version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are\r\nzeroed. VEX.L must be 0, otherwise the instruction will #UD.\r\n\r\n\r\n\r\nVEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The\r\nfirst source and destination operands are YMM registers.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be\r\na ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand is a ZMM/YMM/XMM\r\nregister conditionally updated with writemask k1.\r\n\r\nOperation\r\nPMULHW (with 64-bit operands)\r\n TEMP0[31:0] <- DEST[15:0] * SRC[15:0]; (* Signed multiplication *)\r\n TEMP1[31:0] <- DEST[31:16] * SRC[31:16];\r\n TEMP2[31:0] <- DEST[47:32] * SRC[47:32];\r\n TEMP3[31:0] <- DEST[63:48] * SRC[63:48];\r\n DEST[15:0] <- TEMP0[31:16];\r\n DEST[31:16] <- TEMP1[31:16];\r\n DEST[47:32] <- TEMP2[31:16];\r\n DEST[63:48] <- TEMP3[31:16];\r\n\r\nPMULHW (with 128-bit operands)\r\n TEMP0[31:0] <- DEST[15:0] * SRC[15:0]; (* Signed multiplication *)\r\n TEMP1[31:0] <- DEST[31:16] * SRC[31:16];\r\n TEMP2[31:0] <- DEST[47:32] * SRC[47:32];\r\n TEMP3[31:0] <- DEST[63:48] * SRC[63:48];\r\n TEMP4[31:0] <- DEST[79:64] * SRC[79:64];\r\n TEMP5[31:0] <- DEST[95:80] * SRC[95:80];\r\n TEMP6[31:0] <- DEST[111:96] * SRC[111:96];\r\n TEMP7[31:0] <- DEST[127:112] * SRC[127:112];\r\n DEST[15:0] <- TEMP0[31:16];\r\n DEST[31:16] <- TEMP1[31:16];\r\n DEST[47:32] <- TEMP2[31:16];\r\n DEST[63:48] <- TEMP3[31:16];\r\n DEST[79:64] <- TEMP4[31:16];\r\n DEST[95:80] <- TEMP5[31:16];\r\n DEST[111:96] <- TEMP6[31:16];\r\n DEST[127:112] <- TEMP7[31:16];\r\n\r\nVPMULHW (VEX.128 encoded version)\r\nTEMP0[31:0] <- SRC1[15:0] * SRC2[15:0] (*Signed Multiplication*)\r\nTEMP1[31:0] <- SRC1[31:16] * SRC2[31:16]\r\nTEMP2[31:0] <- SRC1[47:32] * SRC2[47:32]\r\nTEMP3[31:0] <- SRC1[63:48] * SRC2[63:48]\r\nTEMP4[31:0] <- SRC1[79:64] * SRC2[79:64]\r\nTEMP5[31:0] <- SRC1[95:80] * SRC2[95:80]\r\nTEMP6[31:0] <- SRC1[111:96] * SRC2[111:96]\r\nTEMP7[31:0] <- SRC1[127:112] * SRC2[127:112]\r\nDEST[15:0] <- TEMP0[31:16]\r\nDEST[31:16] <- TEMP1[31:16]\r\nDEST[47:32] <- TEMP2[31:16]\r\nDEST[63:48] <- TEMP3[31:16]\r\nDEST[79:64] <- TEMP4[31:16]\r\nDEST[95:80] <- TEMP5[31:16]\r\nDEST[111:96] <- TEMP6[31:16]\r\nDEST[127:112] <- TEMP7[31:16]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\n\r\n\r\n\r\nPMULHW (VEX.256 encoded version)\r\nTEMP0[31:0] <- SRC1[15:0] * SRC2[15:0] (*Signed Multiplication*)\r\nTEMP1[31:0] <- SRC1[31:16] * SRC2[31:16]\r\nTEMP2[31:0] <- SRC1[47:32] * SRC2[47:32]\r\nTEMP3[31:0] <- SRC1[63:48] * SRC2[63:48]\r\nTEMP4[31:0] <- SRC1[79:64] * SRC2[79:64]\r\nTEMP5[31:0] <- SRC1[95:80] * SRC2[95:80]\r\nTEMP6[31:0] <- SRC1[111:96] * SRC2[111:96]\r\nTEMP7[31:0] <- SRC1[127:112] * SRC2[127:112]\r\nTEMP8[31:0] <- SRC1[143:128] * SRC2[143:128]\r\nTEMP9[31:0] <- SRC1[159:144] * SRC2[159:144]\r\nTEMP10[31:0] <- SRC1[175:160] * SRC2[175:160]\r\nTEMP11[31:0] <- SRC1[191:176] * SRC2[191:176]\r\nTEMP12[31:0] <- SRC1[207:192] * SRC2[207:192]\r\nTEMP13[31:0] <- SRC1[223:208] * SRC2[223:208]\r\nTEMP14[31:0] <- SRC1[239:224] * SRC2[239:224]\r\nTEMP15[31:0] <- SRC1[255:240] * SRC2[255:240]\r\nDEST[15:0] <- TEMP0[31:16]\r\nDEST[31:16] <- TEMP1[31:16]\r\nDEST[47:32] <- TEMP2[31:16]\r\nDEST[63:48] <- TEMP3[31:16]\r\nDEST[79:64] <- TEMP4[31:16]\r\nDEST[95:80] <- TEMP5[31:16]\r\nDEST[111:96] <- TEMP6[31:16]\r\nDEST[127:112] <- TEMP7[31:16]\r\nDEST[143:128] <- TEMP8[31:16]\r\nDEST[159:144] <- TEMP9[31:16]\r\nDEST[175:160] <- TEMP10[31:16]\r\nDEST[191:176] <- TEMP11[31:16]\r\nDEST[207:192] <- TEMP12[31:16]\r\nDEST[223:208] <- TEMP13[31:16]\r\nDEST[239:224] <- TEMP14[31:16]\r\nDEST[255:240] <- TEMP15[31:16]\r\nDEST[VLMAX-1:256] <- 0\r\n\r\nPMULHW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n temp[31:0] <- SRC1[i+15:i] * SRC2[i+15:i]\r\n DEST[i+15:i] <- tmp[31:16]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPMULHW __m512i _mm512_mulhi_epi16(__m512i a, __m512i b);\r\nVPMULHW __m512i _mm512_mask_mulhi_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);\r\nVPMULHW __m512i _mm512_maskz_mulhi_epi16( __mmask32 k, __m512i a, __m512i b);\r\nVPMULHW __m256i _mm256_mask_mulhi_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);\r\nVPMULHW __m256i _mm256_maskz_mulhi_epi16( __mmask16 k, __m256i a, __m256i b);\r\nVPMULHW __m128i _mm_mask_mulhi_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPMULHW __m128i _mm_maskz_mulhi_epi16( __mmask8 k, __m128i a, __m128i b);\r\nPMULHW:__m64 _mm_mulhi_pi16 (__m64 m1, __m64 m2)\r\n(V)PMULHW:__m128i _mm_mulhi_epi16 ( __m128i a, __m128i b)\r\nVPMULHW:__m256i _mm256_mulhi_epi16 ( __m256i a, __m256i b)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PMULHW"
},
{
"description": "PMULLD/PMULLQ-Multiply Packed Integers and Store Low Result\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0F 38 40 /r RM V/V SSE4_1 Multiply the packed dword signed integers in xmm1 and\r\n PMULLD xmm1, xmm2/m128 xmm2/m128 and store the low 32 bits of each product in\r\n xmm1.\r\n VEX.NDS.128.66.0F38.WIG 40 /r RVM V/V AVX Multiply the packed dword signed integers in xmm2 and\r\n VPMULLD xmm1, xmm2, xmm3/m128 and store the low 32 bits of each product in\r\n xmm3/m128 xmm1.\r\n VEX.NDS.256.66.0F38.WIG 40 /r RVM V/V AVX2 Multiply the packed dword signed integers in ymm2 and\r\n VPMULLD ymm1, ymm2, ymm3/m256 and store the low 32 bits of each product in\r\n ymm3/m256 ymm1.\r\n EVEX.NDS.128.66.0F38.W0 40 /r FV V/V AVX512VL Multiply the packed dword signed integers in xmm2 and\r\n VPMULLD xmm1 {k1}{z}, xmm2, AVX512F xmm3/m128/m32bcst and store the low 32 bits of each\r\n xmm3/m128/m32bcst product in xmm1 under writemask k1.\r\n EVEX.NDS.256.66.0F38.W0 40 /r FV V/V AVX512VL Multiply the packed dword signed integers in ymm2 and\r\n VPMULLD ymm1 {k1}{z}, ymm2, AVX512F ymm3/m256/m32bcst and store the low 32 bits of each\r\n ymm3/m256/m32bcst product in ymm1 under writemask k1.\r\n EVEX.NDS.512.66.0F38.W0 40 /r FV V/V AVX512F Multiply the packed dword signed integers in zmm2 and\r\n VPMULLD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst and store the low 32 bits of each\r\n zmm3/m512/m32bcst product in zmm1 under writemask k1.\r\n EVEX.NDS.128.66.0F38.W1 40 /r FV V/V AVX512VL Multiply the packed qword signed integers in xmm2 and\r\n VPMULLQ xmm1 {k1}{z}, xmm2, AVX512DQ xmm3/m128/m64bcst and store the low 64 bits of each\r\n xmm3/m128/m64bcst product in xmm1 under writemask k1.\r\n EVEX.NDS.256.66.0F38.W1 40 /r FV V/V AVX512VL Multiply the packed qword signed integers in ymm2 and\r\n VPMULLQ ymm1 {k1}{z}, ymm2, AVX512DQ ymm3/m256/m64bcst and store the low 64 bits of each\r\n ymm3/m256/m64bcst product in ymm1 under writemask k1.\r\n EVEX.NDS.512.66.0F38.W1 40 /r FV V/V AVX512DQ Multiply the packed qword signed integers in zmm2 and\r\n VPMULLQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst and store the low 64 bits of each\r\n zmm3/m512/m64bcst product in zmm1 under writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a SIMD signed multiply of the packed signed dword/qword integers from each element of the first source\r\noperand with the corresponding element in the second source operand. The low 32/64 bits of each 64/128-bit\r\nintermediate results are stored to the destination operand.\r\n128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding ZMM destina-\r\ntion register remain unchanged.\r\nVEX.128 encoded version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding ZMM register\r\nare zeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register; The second source operand is a YMM register\r\nor 256-bit memory location. Bits (MAX_VL-1:256) of the corresponding destination ZMM register are zeroed.\r\n\r\n\r\n\r\n\r\n\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand is a\r\nZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a\r\n32/64-bit memory location. The destination operand is conditionally updated based on writemask k1.\r\n\r\nOperation\r\nVPMULLQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b == 1) AND (SRC2 *is memory*)\r\n THEN Temp[127:0] <- SRC1[i+63:i] * SRC2[63:0]\r\n ELSE Temp[127:0] <- SRC1[i+63:i] * SRC2[i+63:i]\r\n FI;\r\n DEST[i+63:i] <- Temp[63:0]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPMULLD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN Temp[63:0] <- SRC1[i+31:i] * SRC2[31:0]\r\n ELSE Temp[63:0] <- SRC1[i+31:i] * SRC2[i+31:i]\r\n FI;\r\n DEST[i+31:i] <- Temp[31:0]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVPMULLD (VEX.256 encoded version)\r\nTemp0[63:0] <- SRC1[31:0] * SRC2[31:0]\r\nTemp1[63:0] <- SRC1[63:32] * SRC2[63:32]\r\nTemp2[63:0] <- SRC1[95:64] * SRC2[95:64]\r\nTemp3[63:0] <- SRC1[127:96] * SRC2[127:96]\r\nTemp4[63:0] <- SRC1[159:128] * SRC2[159:128]\r\nTemp5[63:0] <- SRC1[191:160] * SRC2[191:160]\r\nTemp6[63:0] <- SRC1[223:192] * SRC2[223:192]\r\nTemp7[63:0] <- SRC1[255:224] * SRC2[255:224]\r\n\r\nDEST[31:0] <- Temp0[31:0]\r\nDEST[63:32] <- Temp1[31:0]\r\nDEST[95:64] <- Temp2[31:0]\r\nDEST[127:96] <- Temp3[31:0]\r\nDEST[159:128] <- Temp4[31:0]\r\nDEST[191:160] <- Temp5[31:0]\r\nDEST[223:192] <- Temp6[31:0]\r\nDEST[255:224] <- Temp7[31:0]\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVPMULLD (VEX.128 encoded version)\r\nTemp0[63:0] <- SRC1[31:0] * SRC2[31:0]\r\nTemp1[63:0] <- SRC1[63:32] * SRC2[63:32]\r\nTemp2[63:0] <- SRC1[95:64] * SRC2[95:64]\r\nTemp3[63:0] <- SRC1[127:96] * SRC2[127:96]\r\nDEST[31:0] <- Temp0[31:0]\r\nDEST[63:32] <- Temp1[31:0]\r\nDEST[95:64] <- Temp2[31:0]\r\nDEST[127:96] <- Temp3[31:0]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nPMULLD (128-bit Legacy SSE version)\r\nTemp0[63:0] <- DEST[31:0] * SRC[31:0]\r\nTemp1[63:0] <- DEST[63:32] * SRC[63:32]\r\nTemp2[63:0] <- DEST[95:64] * SRC[95:64]\r\nTemp3[63:0] <- DEST[127:96] * SRC[127:96]\r\nDEST[31:0] <- Temp0[31:0]\r\nDEST[63:32] <- Temp1[31:0]\r\nDEST[95:64] <- Temp2[31:0]\r\nDEST[127:96] <- Temp3[31:0]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPMULLD __m512i _mm512_mullo_epi32(__m512i a, __m512i b);\r\nVPMULLD __m512i _mm512_mask_mullo_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);\r\nVPMULLD __m512i _mm512_maskz_mullo_epi32( __mmask16 k, __m512i a, __m512i b);\r\nVPMULLD __m256i _mm256_mask_mullo_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);\r\nVPMULLD __m256i _mm256_maskz_mullo_epi32( __mmask8 k, __m256i a, __m256i b);\r\nVPMULLD __m128i _mm_mask_mullo_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPMULLD __m128i _mm_maskz_mullo_epi32( __mmask8 k, __m128i a, __m128i b);\r\nVPMULLD __m256i _mm256_mullo_epi32(__m256i a, __m256i b);\r\nPMULLD __m128i _mm_mullo_epi32(__m128i a, __m128i b);\r\nVPMULLQ __m512i _mm512_mullo_epi64(__m512i a, __m512i b);\r\nVPMULLQ __m512i _mm512_mask_mullo_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);\r\n\r\n\r\n\r\nVPMULLQ __m512i _mm512_maskz_mullo_epi64( __mmask8 k, __m512i a, __m512i b);\r\nVPMULLQ __m256i _mm256_mullo_epi64(__m256i a, __m256i b);\r\nVPMULLQ __m256i _mm256_mask_mullo_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);\r\nVPMULLQ __m256i _mm256_maskz_mullo_epi64( __mmask8 k, __m256i a, __m256i b);\r\nVPMULLQ __m128i _mm_mullo_epi64(__m128i a, __m128i b);\r\nVPMULLQ __m128i _mm_mask_mullo_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPMULLQ __m128i _mm_maskz_mullo_epi64( __mmask8 k, __m128i a, __m128i b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PMULLD"
},
{
"description": "-R:PMULLD",
"mnem": "PMULLQ"
},
{
"description": "PMULLW-Multiply Packed Signed Integers and Store Low Result\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F D5 /r1 RM V/V MMX Multiply the packed signed word integers in\r\nPMULLW mm, mm/m64 mm1 register and mm2/m64, and store the low\r\n 16 bits of the results in mm1.\r\n66 0F D5 /r RM V/V SSE2 Multiply the packed signed word integers in\r\nPMULLW xmm1, xmm2/m128 xmm1 and xmm2/m128, and store the low 16\r\n bits of the results in xmm1.\r\nVEX.NDS.128.66.0F.WIG D5 /r RVM V/V AVX Multiply the packed dword signed integers in\r\nVPMULLW xmm1, xmm2, xmm3/m128 xmm2 and xmm3/m128 and store the low 32\r\n bits of each product in xmm1.\r\nVEX.NDS.256.66.0F.WIG D5 /r RVM V/V AVX2 Multiply the packed signed word integers in\r\nVPMULLW ymm1, ymm2, ymm3/m256 ymm2 and ymm3/m256, and store the low 16\r\n bits of the results in ymm1.\r\nEVEX.NDS.128.66.0F.WIG D5 /r FVM V/V AVX512VL Multiply the packed signed word integers in\r\nVPMULLW xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512BW xmm2 and xmm3/m128, and store the low 16\r\n bits of the results in xmm1 under writemask k1.\r\nEVEX.NDS.256.66.0F.WIG D5 /r FVM V/V AVX512VL Multiply the packed signed word integers in\r\nVPMULLW ymm1 {k1}{z}, ymm2, ymm3/m256 AVX512BW ymm2 and ymm3/m256, and store the low 16\r\n bits of the results in ymm1 under writemask k1.\r\nEVEX.NDS.512.66.0F.WIG D5 /r FVM V/V AVX512BW Multiply the packed signed word integers in\r\nVPMULLW zmm1 {k1}{z}, zmm2, zmm3/m512 zmm2 and zmm3/m512, and store the low 16\r\n bits of the results in zmm1 under writemask k1.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nPerforms a SIMD signed multiply of the packed signed word integers in the destination operand (first operand) and\r\nthe source operand (second operand), and stores the low 16 bits of each intermediate 32-bit result in the destina-\r\ntion operand. (Figure 4-12 shows this operation when using 64-bit operands.)\r\nIn 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to\r\naccess additional registers (XMM8-XMM15).\r\nLegacy SSE version 64-bit operand: The source operand can be an MMX technology register or a 64-bit memory\r\nlocation. The destination operand is an MMX technology register.\r\n128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destina-\r\ntion register remain unchanged.\r\nVEX.128 encoded version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are\r\nzeroed. VEX.L must be 0, otherwise the instruction will #UD.\r\n\r\n\r\n\r\nVEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The\r\nfirst source and destination operands are YMM registers.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand is a\r\nZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand is conditionally updated\r\nbased on writemask k1.\r\n\r\n\r\n\r\n SRC X3 X2 X1 X0\r\n\r\n\r\n DEST Y3 Y2 Y1 Y0\r\n\r\n\r\n TEMP Z3 = X3 * Y3 Z2 = X2 * Y2 Z1 = X1 * Y1 Z0 = X0 * Y0\r\n\r\n\r\n DEST Z3[15:0] Z2[15:0] Z1[15:0] Z0[15:0]\r\n\r\n\r\n Figure 4-13. PMULLU Instruction Operation Using 64-bit Operands\r\n\r\n\r\nOperation\r\nPMULLW (with 64-bit operands)\r\n TEMP0[31:0] <- DEST[15:0] * SRC[15:0]; (* Signed multiplication *)\r\n TEMP1[31:0] <- DEST[31:16] * SRC[31:16];\r\n TEMP2[31:0] <- DEST[47:32] * SRC[47:32];\r\n TEMP3[31:0] <- DEST[63:48] * SRC[63:48];\r\n DEST[15:0] <- TEMP0[15:0];\r\n DEST[31:16] <- TEMP1[15:0];\r\n DEST[47:32] <- TEMP2[15:0];\r\n DEST[63:48] <- TEMP3[15:0];\r\n\r\nPMULLW (with 128-bit operands)\r\n TEMP0[31:0] <- DEST[15:0] * SRC[15:0]; (* Signed multiplication *)\r\n TEMP1[31:0] <- DEST[31:16] * SRC[31:16];\r\n TEMP2[31:0] <- DEST[47:32] * SRC[47:32];\r\n TEMP3[31:0] <- DEST[63:48] * SRC[63:48];\r\n TEMP4[31:0] <- DEST[79:64] * SRC[79:64];\r\n TEMP5[31:0] <- DEST[95:80] * SRC[95:80];\r\n TEMP6[31:0] <- DEST[111:96] * SRC[111:96];\r\n TEMP7[31:0] <- DEST[127:112] * SRC[127:112];\r\n DEST[15:0] <- TEMP0[15:0];\r\n DEST[31:16] <- TEMP1[15:0];\r\n DEST[47:32] <- TEMP2[15:0];\r\n DEST[63:48] <- TEMP3[15:0];\r\n DEST[79:64] <- TEMP4[15:0];\r\n DEST[95:80] <- TEMP5[15:0];\r\n DEST[111:96] <- TEMP6[15:0];\r\n DEST[127:112] <- TEMP7[15:0];\r\nDEST[VLMAX-1:256] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVPMULLW (VEX.128 encoded version)\r\nTemp0[31:0] <- SRC1[15:0] * SRC2[15:0]\r\nTemp1[31:0] <- SRC1[31:16] * SRC2[31:16]\r\nTemp2[31:0] <- SRC1[47:32] * SRC2[47:32]\r\nTemp3[31:0] <- SRC1[63:48] * SRC2[63:48]\r\nTemp4[31:0] <- SRC1[79:64] * SRC2[79:64]\r\nTemp5[31:0] <- SRC1[95:80] * SRC2[95:80]\r\nTemp6[31:0] <- SRC1[111:96] * SRC2[111:96]\r\nTemp7[31:0] <- SRC1[127:112] * SRC2[127:112]\r\nDEST[15:0] <- Temp0[15:0]\r\nDEST[31:16] <- Temp1[15:0]\r\nDEST[47:32] <- Temp2[15:0]\r\nDEST[63:48] <- Temp3[15:0]\r\nDEST[79:64] <- Temp4[15:0]\r\nDEST[95:80] <- Temp5[15:0]\r\nDEST[111:96] <- Temp6[15:0]\r\nDEST[127:112] <- Temp7[15:0]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nPMULLW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n temp[31:0] <- SRC1[i+15:i] * SRC2[i+15:i]\r\n DEST[i+15:i] <- temp[15:0]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPMULLW __m512i _mm512_mullo_epi16(__m512i a, __m512i b);\r\nVPMULLW __m512i _mm512_mask_mullo_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);\r\nVPMULLW __m512i _mm512_maskz_mullo_epi16( __mmask32 k, __m512i a, __m512i b);\r\nVPMULLW __m256i _mm256_mask_mullo_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);\r\nVPMULLW __m256i _mm256_maskz_mullo_epi16( __mmask16 k, __m256i a, __m256i b);\r\nVPMULLW __m128i _mm_mask_mullo_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPMULLW __m128i _mm_maskz_mullo_epi16( __mmask8 k, __m128i a, __m128i b);\r\nPMULLW: __m64 _mm_mullo_pi16(__m64 m1, __m64 m2)\r\n(V)PMULLW: __m128i _mm_mullo_epi16 ( __m128i a, __m128i b)\r\nVPMULLW:__m256i _mm256_mullo_epi16 ( __m256i a, __m256i b);\r\n\r\nFlags Affected\r\nNone.\r\n\r\n\r\n\r\n\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PMULLW"
},
{
"description": "PMULUDQ-Multiply Packed Unsigned Doubleword Integers\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F F4 /r1 RM V/V SSE2 Multiply unsigned doubleword integer in mm1 by\r\nPMULUDQ mm1, mm2/m64 unsigned doubleword integer in mm2/m64, and\r\n store the quadword result in mm1.\r\n66 0F F4 /r RM V/V SSE2 Multiply packed unsigned doubleword integers in\r\nPMULUDQ xmm1, xmm2/m128 xmm1 by packed unsigned doubleword integers\r\n in xmm2/m128, and store the quadword results\r\n in xmm1.\r\nVEX.NDS.128.66.0F.WIG F4 /r RVM V/V AVX Multiply packed unsigned doubleword integers in\r\nVPMULUDQ xmm1, xmm2, xmm3/m128 xmm2 by packed unsigned doubleword integers\r\n in xmm3/m128, and store the quadword results\r\n in xmm1.\r\nVEX.NDS.256.66.0F.WIG F4 /r RVM V/V AVX2 Multiply packed unsigned doubleword integers in\r\nVPMULUDQ ymm1, ymm2, ymm3/m256 ymm2 by packed unsigned doubleword integers\r\n in ymm3/m256, and store the quadword results\r\n in ymm1.\r\nEVEX.NDS.128.66.0F.W1 F4 /r FV V/V AVX512VL Multiply packed unsigned doubleword integers in\r\nVPMULUDQ xmm1 {k1}{z}, xmm2, AVX512F xmm2 by packed unsigned doubleword integers\r\nxmm3/m128/m64bcst in xmm3/m128/m64bcst, and store the\r\n quadword results in xmm1 under writemask k1.\r\nEVEX.NDS.256.66.0F.W1 F4 /r FV V/V AVX512VL Multiply packed unsigned doubleword integers in\r\nVPMULUDQ ymm1 {k1}{z}, ymm2, AVX512F ymm2 by packed unsigned doubleword integers\r\nymm3/m256/m64bcst in ymm3/m256/m64bcst, and store the\r\n quadword results in ymm1 under writemask k1.\r\nEVEX.NDS.512.66.0F.W1 F4 /r FV V/V AVX512F Multiply packed unsigned doubleword integers in\r\nVPMULUDQ zmm1 {k1}{z}, zmm2, zmm2 by packed unsigned doubleword integers\r\nzmm3/m512/m64bcst in zmm3/m512/m64bcst, and store the\r\n quadword results in zmm1 under writemask k1.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nMultiplies the first operand (destination operand) by the second operand (source operand) and stores the result in\r\nthe destination operand.\r\nIn 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to\r\naccess additional registers (XMM8-XMM15).\r\nLegacy SSE version 64-bit operand: The source operand can be an unsigned doubleword integer stored in the low\r\ndoubleword of an MMX technology register or a 64-bit memory location. The destination operand can be an\r\nunsigned doubleword integer stored in the low doubleword an MMX technology register. The result is an unsigned\r\n\r\n\r\n\r\nquadword integer stored in the destination an MMX technology register. When a quadword result is too large to be\r\nrepresented in 64 bits (overflow), the result is wrapped around and the low 64 bits are written to the destination\r\nelement (that is, the carry is ignored).\r\nFor 64-bit memory operands, 64 bits are fetched from memory, but only the low doubleword is used in the compu-\r\ntation.\r\n128-bit Legacy SSE version: The second source operand is two packed unsigned doubleword integers stored in the\r\nfirst (low) and third doublewords of an XMM register or a 128-bit memory location. For 128-bit memory operands,\r\n128 bits are fetched from memory, but only the first and third doublewords are used in the computation. The first\r\nsource operand is two packed unsigned doubleword integers stored in the first and third doublewords of an XMM\r\nregister. The destination contains two packed unsigned quadword integers stored in an XMM register. Bits (VLMAX-\r\n1:128) of the corresponding YMM destination register remain unchanged.\r\nVEX.128 encoded version: The second source operand is two packed unsigned doubleword integers stored in the\r\nfirst (low) and third doublewords of an XMM register or a 128-bit memory location. For 128-bit memory operands,\r\n128 bits are fetched from memory, but only the first and third doublewords are used in the computation. The first\r\nsource operand is two packed unsigned doubleword integers stored in the first and third doublewords of an XMM\r\nregister. The destination contains two packed unsigned quadword integers stored in an XMM register. Bits (VLMAX-\r\n1:128) of the destination YMM register are zeroed.\r\nVEX.256 encoded version: The second source operand is four packed unsigned doubleword integers stored in the\r\nfirst (low), third, fifth and seventh doublewords of a YMM register or a 256-bit memory location. For 256-bit\r\nmemory operands, 256 bits are fetched from memory, but only the first, third, fifth and seventh doublewords are\r\nused in the computation. The first source operand is four packed unsigned doubleword integers stored in the first,\r\nthird, fifth and seventh doublewords of an YMM register. The destination contains four packed unaligned quadword\r\nintegers stored in an YMM register.\r\nEVEX encoded version: The input unsigned doubleword integers are taken from the even-numbered elements of\r\nthe source operands. The first source operand is a ZMM/YMM/XMM registers. The second source operand can be an\r\nZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-\r\nbit memory location. The destination is a ZMM/YMM/XMM register, and updated according to the writemask at 64-\r\nbit granularity.\r\n\r\nOperation\r\nPMULUDQ (with 64-Bit operands)\r\n DEST[63:0] <- DEST[31:0] * SRC[31:0];\r\n\r\nPMULUDQ (with 128-Bit operands)\r\n DEST[63:0] <- DEST[31:0] * SRC[31:0];\r\n DEST[127:64] <- DEST[95:64] * SRC[95:64];\r\n\r\nVPMULUDQ (VEX.128 encoded version)\r\nDEST[63:0] <- SRC1[31:0] * SRC2[31:0]\r\nDEST[127:64] <- SRC1[95:64] * SRC2[95:64]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPMULUDQ (VEX.256 encoded version)\r\nDEST[63:0] <- SRC1[31:0] * SRC2[31:0]\r\nDEST[127:64] <- SRC1[95:64] * SRC2[95:64\r\nDEST[191:128] <- SRC1[159:128] * SRC2[159:128]\r\nDEST[255:192] <- SRC1[223:192] * SRC2[223:192]\r\nDEST[VLMAX-1:256] <- 0\r\n\r\nVPMULUDQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n\r\n\r\n THEN DEST[i+63:i] <- ZeroExtend64( SRC1[i+31:i]) * ZeroExtend64( SRC2[31:0] )\r\n ELSE DEST[i+63:i] <- ZeroExtend64( SRC1[i+31:i]) * ZeroExtend64( SRC2[i+31:i] )\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPMULUDQ __m512i _mm512_mul_epu32(__m512i a, __m512i b);\r\nVPMULUDQ __m512i _mm512_mask_mul_epu32(__m512i s, __mmask8 k, __m512i a, __m512i b);\r\nVPMULUDQ __m512i _mm512_maskz_mul_epu32( __mmask8 k, __m512i a, __m512i b);\r\nVPMULUDQ __m256i _mm256_mask_mul_epu32(__m256i s, __mmask8 k, __m256i a, __m256i b);\r\nVPMULUDQ __m256i _mm256_maskz_mul_epu32( __mmask8 k, __m256i a, __m256i b);\r\nVPMULUDQ __m128i _mm_mask_mul_epu32(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPMULUDQ __m128i _mm_maskz_mul_epu32( __mmask8 k, __m128i a, __m128i b);\r\nPMULUDQ:__m64 _mm_mul_su32 (__m64 a, __m64 b)\r\n(V)PMULUDQ:__m128i _mm_mul_epu32 ( __m128i a, __m128i b)\r\nVPMULUDQ:__m256i _mm256_mul_epu32( __m256i a, __m256i b);\r\n\r\nFlags Affected\r\nNone.\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PMULUDQ"
},
{
"description": "POP-Pop a Value from the Stack\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 8F /0 POP r/m16 M Valid Valid Pop top of stack into m16; increment stack\r\n pointer.\r\n 8F /0 POP r/m32 M N.E. Valid Pop top of stack into m32; increment stack\r\n pointer.\r\n 8F /0 POP r/m64 M Valid N.E. Pop top of stack into m64; increment stack\r\n pointer. Cannot encode 32-bit operand size.\r\n 58+ rw POP r16 O Valid Valid Pop top of stack into r16; increment stack\r\n pointer.\r\n 58+ rd POP r32 O N.E. Valid Pop top of stack into r32; increment stack\r\n pointer.\r\n 58+ rd POP r64 O Valid N.E. Pop top of stack into r64; increment stack\r\n pointer. Cannot encode 32-bit operand size.\r\n 1F POP DS NP Invalid Valid Pop top of stack into DS; increment stack\r\n pointer.\r\n 07 POP ES NP Invalid Valid Pop top of stack into ES; increment stack\r\n pointer.\r\n 17 POP SS NP Invalid Valid Pop top of stack into SS; increment stack\r\n pointer.\r\n 0F A1 POP FS NP Valid Valid Pop top of stack into FS; increment stack\r\n pointer by 16 bits.\r\n 0F A1 POP FS NP N.E. Valid Pop top of stack into FS; increment stack\r\n pointer by 32 bits.\r\n 0F A1 POP FS NP Valid N.E. Pop top of stack into FS; increment stack\r\n pointer by 64 bits.\r\n\r\n 0F A9 POP GS NP Valid Valid Pop top of stack into GS; increment stack\r\n pointer by 16 bits.\r\n 0F A9 POP GS NP N.E. Valid Pop top of stack into GS; increment stack\r\n pointer by 32 bits.\r\n 0F A9 POP GS NP Valid N.E. Pop top of stack into GS; increment stack\r\n pointer by 64 bits.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (w) NA NA NA\r\n O opcode + rd (w) NA NA NA\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nLoads the value from the top of the stack to the location specified with the destination operand (or explicit opcode)\r\nand then increments the stack pointer. The destination operand can be a general-purpose register, memory loca-\r\ntion, or segment register.\r\nAddress and operand sizes are determined and used as follows:\r\n. Address size. The D flag in the current code-segment descriptor determines the default address size; it may be\r\n overridden by an instruction prefix (67H).\r\n\r\n\r\n\r\n The address size is used only when writing to a destination operand in memory.\r\n. Operand size. The D flag in the current code-segment descriptor determines the default operand size; it may\r\n be overridden by instruction prefixes (66H or REX.W).\r\n The operand size (16, 32, or 64 bits) determines the amount by which the stack pointer is incremented (2, 4\r\n or 8).\r\n. Stack-address size. Outside of 64-bit mode, the B flag in the current stack-segment descriptor determines the\r\n size of the stack pointer (16 or 32 bits); in 64-bit mode, the size of the stack pointer is always 64 bits.\r\n The stack-address size determines the width of the stack pointer when reading from the stack in memory and\r\n when incrementing the stack pointer. (As stated above, the amount by which the stack pointer is incremented\r\n is determined by the operand size.)\r\nIf the destination operand is one of the segment registers DS, ES, FS, GS, or SS, the value loaded into the register\r\nmust be a valid segment selector. In protected mode, popping a segment selector into a segment register automat-\r\nically causes the descriptor information associated with that segment selector to be loaded into the hidden\r\n(shadow) part of the segment register and causes the selector and the descriptor information to be validated (see\r\nthe \"Operation\" section below).\r\nA NULL value (0000-0003) may be popped into the DS, ES, FS, or GS register without causing a general protection\r\nfault. However, any subsequent attempt to reference a segment whose corresponding segment register is loaded\r\nwith a NULL value causes a general protection exception (#GP). In this situation, no memory reference occurs and\r\nthe saved value of the segment register is NULL.\r\nThe POP instruction cannot pop a value into the CS register. To load the CS register from the stack, use the RET\r\ninstruction.\r\nIf the ESP register is used as a base register for addressing a destination operand in memory, the POP instruction\r\ncomputes the effective address of the operand after it increments the ESP register. For the case of a 16-bit stack\r\nwhere ESP wraps to 0H as a result of the POP instruction, the resulting location of the memory write is processor-\r\nfamily-specific.\r\nThe POP ESP instruction increments the stack pointer (ESP) before data at the old top of stack is written into the\r\ndestination.\r\nA POP SS instruction inhibits all interrupts, including the NMI interrupt, until after execution of the next instruction.\r\nThis action allows sequential execution of POP SS and MOV ESP, EBP instructions without the danger of having an\r\ninvalid stack during an interrupt1. However, use of the LSS instruction is the preferred method of loading the SS\r\nand ESP registers.\r\nIn 64-bit mode, using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). When in\r\n64-bit mode, POPs using 32-bit operands are not encodable and POPs to DS, ES, SS are not valid. See the summary\r\nchart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nIF StackAddrSize = 32\r\n THEN\r\n IF OperandSize = 32\r\n THEN\r\n DEST <- SS:ESP; (* Copy a doubleword *)\r\n ESP <- ESP + 4;\r\n ELSE (* OperandSize = 16*)\r\n DEST <- SS:ESP; (* Copy a word *)\r\n\r\n1. If a code instruction breakpoint (for debug) is placed on an instruction located immediately after a POP SS instruction, the breakpoint\r\n may not be triggered. However, in a sequence of instructions that POP the SS register, only the first instruction in the sequence is\r\n guaranteed to delay an interrupt.\r\n In the following sequence, interrupts may be recognized before POP ESP executes:\r\n POP SS\r\n POP SS\r\n POP ESP\r\n\r\n\r\n\r\n ESP <- ESP + 2;\r\n FI;\r\n ELSE IF StackAddrSize = 64\r\n THEN\r\n IF OperandSize = 64\r\n THEN\r\n DEST <- SS:RSP; (* Copy quadword *)\r\n RSP <- RSP + 8;\r\n ELSE (* OperandSize = 16*)\r\n DEST <- SS:RSP; (* Copy a word *)\r\n RSP <- RSP + 2;\r\n FI;\r\n FI;\r\n ELSE StackAddrSize = 16\r\n THEN\r\n IF OperandSize = 16\r\n THEN\r\n DEST <- SS:SP; (* Copy a word *)\r\n SP <- SP + 2;\r\n ELSE (* OperandSize = 32 *)\r\n DEST <- SS:SP; (* Copy a doubleword *)\r\n SP <- SP + 4;\r\n FI;\r\n\r\nFI;\r\n\r\n\r\nLoading a segment register while in protected mode results in special actions, as described in the following listing.\r\nThese checks are performed on the segment selector and the segment descriptor it points to.\r\n\r\n64-BIT_MODE\r\nIF FS, or GS is loaded with non-NULL selector;\r\n THEN\r\n IF segment selector index is outside descriptor table limits\r\n OR segment is not a data or readable code segment\r\n OR ((segment is a data or nonconforming code segment)\r\n AND (both RPL and CPL > DPL))\r\n THEN #GP(selector);\r\n IF segment not marked present\r\n THEN #NP(selector);\r\n ELSE\r\n SegmentRegister <- segment selector;\r\n SegmentRegister <- segment descriptor;\r\n FI;\r\nFI;\r\nIF FS, or GS is loaded with a NULL selector;\r\n THEN\r\n SegmentRegister <- segment selector;\r\n SegmentRegister <- segment descriptor;\r\nFI;\r\n\r\n\r\n\r\nPREOTECTED MODE OR COMPATIBILITY MODE;\r\n\r\nIF SS is loaded;\r\n\r\n\r\n\r\n THEN\r\n IF segment selector is NULL\r\n THEN #GP(0);\r\n FI;\r\n IF segment selector index is outside descriptor table limits\r\n or segment selector's RPL != CPL\r\n or segment is not a writable data segment\r\n or DPL != CPL\r\n THEN #GP(selector);\r\n FI;\r\n IF segment not marked present\r\n THEN #SS(selector);\r\n ELSE\r\n SS <- segment selector;\r\n SS <- segment descriptor;\r\n FI;\r\nFI;\r\n\r\nIF DS, ES, FS, or GS is loaded with non-NULL selector;\r\n THEN\r\n IF segment selector index is outside descriptor table limits\r\n or segment is not a data or readable code segment\r\n or ((segment is a data or nonconforming code segment)\r\n and (both RPL and CPL > DPL))\r\n THEN #GP(selector);\r\n FI;\r\n IF segment not marked present\r\n THEN #NP(selector);\r\n ELSE\r\n SegmentRegister <- segment selector;\r\n SegmentRegister <- segment descriptor;\r\n FI;\r\nFI;\r\n\r\nIF DS, ES, FS, or GS is loaded with a NULL selector\r\n THEN\r\n SegmentRegister <- segment selector;\r\n SegmentRegister <- segment descriptor;\r\nFI;\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If attempt is made to load SS register with NULL segment selector.\r\n If the destination operand is in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n#GP(selector) If segment selector index is outside descriptor table limits.\r\n If the SS register is being loaded and the segment selector's RPL and the segment descriptor's\r\n DPL are not equal to the CPL.\r\n\r\n\r\n\r\n\r\n If the SS register is being loaded and the segment pointed to is a\r\n non-writable data segment.\r\n If the DS, ES, FS, or GS register is being loaded and the segment pointed to is not a data or\r\n readable code segment.\r\n If the DS, ES, FS, or GS register is being loaded and the segment pointed to is a data or\r\n nonconforming code segment, but both the RPL and the CPL are greater than the DPL.\r\n#SS(0) If the current top of stack is not within the stack segment.\r\n If a memory operand effective address is outside the SS segment limit.\r\n#SS(selector) If the SS register is being loaded and the segment pointed to is marked not present.\r\n#NP If the DS, ES, FS, or GS register is being loaded and the segment pointed to is marked not\r\n present.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If an unaligned memory reference is made while the current privilege level is 3 and alignment\r\n checking is enabled.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If an unaligned memory reference is made while alignment checking is enabled.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame as for protected mode exceptions.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#SS(0) If the stack address is in a non-canonical form.\r\n#GP(selector) If the descriptor is outside the descriptor table limit.\r\n If the FS or GS register is being loaded and the segment pointed to is not a data or readable\r\n code segment.\r\n If the FS or GS register is being loaded and the segment pointed to is a data or nonconforming\r\n code segment, but both the RPL and the CPL are greater than the DPL.\r\n#AC(0) If an unaligned memory reference is made while alignment checking is enabled.\r\n#PF(fault-code) If a page fault occurs.\r\n#NP If the FS or GS register is being loaded and the segment pointed to is marked not present.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "POP"
},
{
"description": "POPA/POPAD-Pop All General-Purpose Registers\r\nOpcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n61 POPA NP Invalid Valid Pop DI, SI, BP, BX, DX, CX, and AX.\r\n61 POPAD NP Invalid Valid Pop EDI, ESI, EBP, EBX, EDX, ECX, and EAX.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nPops doublewords (POPAD) or words (POPA) from the stack into the general-purpose registers. The registers are\r\nloaded in the following order: EDI, ESI, EBP, EBX, EDX, ECX, and EAX (if the operand-size attribute is 32) and DI,\r\nSI, BP, BX, DX, CX, and AX (if the operand-size attribute is 16). (These instructions reverse the operation of the\r\nPUSHA/PUSHAD instructions.) The value on the stack for the ESP or SP register is ignored. Instead, the ESP or SP\r\nregister is incremented after each register is loaded.\r\nThe POPA (pop all) and POPAD (pop all double) mnemonics reference the same opcode. The POPA instruction is\r\nintended for use when the operand-size attribute is 16 and the POPAD instruction for when the operand-size attri-\r\nbute is 32. Some assemblers may force the operand size to 16 when POPA is used and to 32 when POPAD is used\r\n(using the operand-size override prefix [66H] if necessary). Others may treat these mnemonics as synonyms\r\n(POPA/POPAD) and use the current setting of the operand-size attribute to determine the size of values to be\r\npopped from the stack, regardless of the mnemonic used. (The D flag in the current code segment's segment\r\ndescriptor determines the operand-size attribute.)\r\nThis instruction executes as described in non-64-bit modes. It is not valid in 64-bit mode.\r\n\r\nOperation\r\nIF 64-Bit Mode\r\n THEN\r\n #UD;\r\nELSE\r\n IF OperandSize = 32 (* Instruction = POPAD *)\r\n THEN\r\n EDI <- Pop();\r\n ESI <- Pop();\r\n EBP <- Pop();\r\n Increment ESP by 4; (* Skip next 4 bytes of stack *)\r\n EBX <- Pop();\r\n EDX <- Pop();\r\n ECX <- Pop();\r\n EAX <- Pop();\r\n ELSE (* OperandSize = 16, instruction = POPA *)\r\n DI <- Pop();\r\n SI <- Pop();\r\n BP <- Pop();\r\n Increment ESP by 2; (* Skip next 2 bytes of stack *)\r\n BX <- Pop();\r\n DX <- Pop();\r\n CX <- Pop();\r\n AX <- Pop();\r\n FI;\r\nFI;\r\n\r\n\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#SS(0) If the starting or ending stack address is not within the stack segment.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If an unaligned memory reference is made while the current privilege level is 3 and alignment\r\n checking is enabled.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#SS If the starting or ending stack address is not within the stack segment.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#SS(0) If the starting or ending stack address is not within the stack segment.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If an unaligned memory reference is made while alignment checking is enabled.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame as for protected mode exceptions.\r\n\r\n64-Bit Mode Exceptions\r\n#UD If in 64-bit mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "POPA"
},
{
"description": "-R:POPA",
"mnem": "POPAD"
},
{
"description": "POPCNT - Return the Count of Number of Bits Set to 1\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n F3 0F B8 /r POPCNT r16, r/m16 RM Valid Valid POPCNT on r/m16\r\n F3 0F B8 /r POPCNT r32, r/m32 RM Valid Valid POPCNT on r/m32\r\n F3 REX.W 0F B8 /r POPCNT r64, r/m64 RM Valid N.E. POPCNT on r/m64\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\n\r\nDescription\r\nThis instruction calculates the number of bits set to 1 in the second operand (source) and returns the count in the\r\nfirst operand (a destination register).\r\n\r\nOperation\r\nCount = 0;\r\nFor (i=0; i < OperandSize; i++)\r\n{ IF (SRC[ i] = 1) // i'th bit\r\n THEN Count++; FI;\r\n}\r\nDEST <- Count;\r\n\r\nFlags Affected\r\nOF, SF, ZF, AF, CF, PF are all cleared. ZF is set if SRC = 0, otherwise ZF is cleared.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nPOPCNT: int _mm_popcnt_u32(unsigned int a);\r\nPOPCNT: int64_t _mm_popcnt_u64(unsigned __int64 a);\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS or GS segments.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF (fault-code) For a page fault.\r\n#AC(0) If an unaligned memory reference is made while the current privilege level is 3 and alignment\r\n checking is enabled.\r\n#UD If CPUID.01H:ECX.POPCNT [Bit 23] = 0.\r\n If LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP(0) If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#UD If CPUID.01H:ECX.POPCNT [Bit 23] = 0.\r\n If LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n\r\nVirtual 8086 Mode Exceptions\r\n#GP(0) If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF (fault-code) For a page fault.\r\n#AC(0) If an unaligned memory reference is made while alignment checking is enabled.\r\n#UD If CPUID.01H:ECX.POPCNT [Bit 23] = 0.\r\n If LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in Protected Mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#PF (fault-code) For a page fault.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If CPUID.01H:ECX.POPCNT [Bit 23] = 0.\r\n If LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "POPCNT"
},
{
"description": "POPF/POPFD/POPFQ-Pop Stack into EFLAGS Register\r\nOpcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n9D POPF NP Valid Valid Pop top of stack into lower 16 bits of EFLAGS.\r\n9D POPFD NP N.E. Valid Pop top of stack into EFLAGS.\r\n9D POPFQ NP Valid N.E. Pop top of stack and zero-extend into RFLAGS.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nPops a doubleword (POPFD) from the top of the stack (if the current operand-size attribute is 32) and stores the\r\nvalue in the EFLAGS register, or pops a word from the top of the stack (if the operand-size attribute is 16) and\r\nstores it in the lower 16 bits of the EFLAGS register (that is, the FLAGS register). These instructions reverse the\r\noperation of the PUSHF/PUSHFD instructions.\r\nThe POPF (pop flags) and POPFD (pop flags double) mnemonics reference the same opcode. The POPF instruction\r\nis intended for use when the operand-size attribute is 16; the POPFD instruction is intended for use when the\r\noperand-size attribute is 32. Some assemblers may force the operand size to 16 for POPF and to 32 for POPFD.\r\nOthers may treat the mnemonics as synonyms (POPF/POPFD) and use the setting of the operand-size attribute to\r\ndetermine the size of values to pop from the stack.\r\nThe effect of POPF/POPFD on the EFLAGS register changes, depending on the mode of operation. See the Table\r\n4-15 and key below for details.\r\nWhen operating in protected, compatibility, or 64-bit mode at privilege level 0 (or in real-address mode, the equiv-\r\nalent to privilege level 0), all non-reserved flags in the EFLAGS register except RF1, VIP, VIF, and VM may be modi-\r\nfied. VIP, VIF and VM remain unaffected.\r\nWhen operating in protected, compatibility, or 64-bit mode with a privilege level greater than 0, but less than or\r\nequal to IOPL, all flags can be modified except the IOPL field and RF1, IF, VIP, VIF, and VM; these remain unaffected.\r\nThe AC and ID flags can only be modified if the operand-size attribute is 32. The interrupt flag (IF) is altered only\r\nwhen executing at a level at least as privileged as the IOPL. If a POPF/POPFD instruction is executed with insuffi-\r\ncient privilege, an exception does not occur but privileged bits do not change.\r\nWhen operating in virtual-8086 mode (EFLAGS.VM = 1) without the virtual-8086 mode extensions (CR4.VME = 0),\r\nthe POPF/POPFD instructions can be used only if IOPL = 3; otherwise, a general-protection exception (#GP) occurs.\r\nIf the virtual-8086 mode extensions are enabled (CR4.VME = 1), POPF (but not POPFD) can be executed in virtual-\r\n8086 mode with IOPL < 3.\r\nIn 64-bit mode, the mnemonic assigned is POPFQ (note that the 32-bit operand is not encodable). POPFQ pops 64\r\nbits from the stack. Reserved bits of RFLAGS (including the upper 32 bits of RFLAGS) are not affected.\r\nSee Chapter 3 of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for more informa-\r\ntion about the EFLAGS registers.\r\n\r\n\r\n\r\n\r\n1. RF is always zero after the execution of POPF. This is because POPF, like all instructions, clears RF as it begins to execute.\r\n\r\n\r\n\r\n Table 4-15. Effect of POPF/POPFD on the EFLAGS Register\r\n Flags\r\n Mode Operand CPL IOPL Notes\r\n 21 20 19 18 17 16 14 13:12 11 10 9 8 7 6 4 2 0\r\n Size\r\n ID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CF\r\n Real-Address 16 0 0-3 N N N N N 0 S S S S S S S S S S S\r\n Mode (CR0.PE\r\n 32 0 0-3 S N N S N 0 S S S S S S S S S S S\r\n = 0)\r\n Protected, 16 0 0-3 N N N N N 0 S S S S S S S S S S S\r\n Compatibility,\r\n 16 1-3 <CPL N N N N N 0 S N S S N S S S S S S\r\n and 64-Bit\r\n Modes 16 1-3 >=CPL N N N N N 0 S N S S S S S S S S S\r\n 32, 64 0 0-3 S N N S N 0 S S S S S S S S S S S\r\n (CR0.PE = 1,\r\n EFLAGS.VM = 32, 64 1-3 <CPL S N N S N 0 S N S S N S S S S S S\r\n 0)\r\n 32, 64 1-3 >=CPL S N N S N 0 S N S S S S S S S S S\r\n 1\r\n Virtual-8086 16 3 0-2 X X X X X X X X X X X X X X X X X\r\n (CR0.PE = 1,\r\n 16 3 3 N N N N N 0 S N S S S S S S S S S\r\n EFLAGS.VM =\r\n 1\r\n 1, 32 3 0-2 X X X X X X X X X X X X X X X X X\r\n CR4.VME = 0)\r\n 32 3 3 S N N S N 0 S N S S S S S S S S S\r\n 2\r\n VME 16 3 0-2 N/ N/ SV/ N/ N/ 0/ S/ N/X S/ S/ N/ S/ S/ S/ S/ S/ S/\r\n (CR0.PE = 1, X X X X X X X X X X X X X X X X\r\n EFLAGS.VM =\r\n 16 3 3 N N N N N 0 S N S S S S S S S S S\r\n 1,\r\n CR4.VME = 1) 1\r\n 32 3 0-2 X X X X X X X X X X X X X X X X X\r\n 32 3 3 S N N S N 0 S N S S S S S S S S S\r\n\r\nNOTES:\r\n1. #GP fault - no flag update\r\n2. #GP fault with no flag update if VIP=1 in EFLAGS register and IF=1 in FLAGS value on stack\r\n\r\n\r\n Key\r\n S Updated from stack\r\n SV Updated from IF (bit 9) in FLAGS value on stack\r\n N No change in value\r\n X No EFLAGS update\r\n 0 Value is cleared\r\n\r\nOperation\r\nIF VM = 0 (* Not in Virtual-8086 Mode *)\r\n THEN IF CPL = 0\r\n THEN\r\n IF OperandSize = 32;\r\n THEN\r\n EFLAGS <- Pop(); (* 32-bit pop *)\r\n (* All non-reserved flags except RF, VIP, VIF, and VM can be modified;\r\n VIP, VIF, VM, and all reserved bits are unaffected. RF is cleared. *)\r\n ELSE IF (Operandsize = 64)\r\n RFLAGS = Pop(); (* 64-bit pop *)\r\n (* All non-reserved flags except RF, VIP, VIF, and VM can be modified;\r\n VIP, VIF, VM, and all reserved bits are unaffected. RF is cleared. *)\r\n ELSE (* OperandSize = 16 *)\r\n\r\n\r\n\r\n EFLAGS[15:0] <- Pop(); (* 16-bit pop *)\r\n (* All non-reserved flags can be modified. *)\r\n FI;\r\n ELSE (* CPL > 0 *)\r\n IF OperandSize = 32\r\n THEN\r\n IF CPL > IOPL\r\n THEN\r\n EFLAGS <- Pop(); (* 32-bit pop *)\r\n (* All non-reserved bits except IF, IOPL, VIP, VIF, VM and RF can be modified;\r\n IF, IOPL, VIP, VIF, VM and all reserved bits are unaffected; RF is cleared. *)\r\n ELSE\r\n EFLAGS <- Pop(); (* 32-bit pop *)\r\n (* All non-reserved bits except IOPL, VIP, VIF, VM and RF can be modified;\r\n IOPL, VIP, VIF, VM and all reserved bits are unaffected; RF is cleared. *)\r\n FI;\r\n ELSE IF (Operandsize = 64)\r\n IF CPL > IOPL\r\n THEN\r\n RFLAGS <- Pop(); (* 64-bit pop *)\r\n (* All non-reserved bits except IF, IOPL, VIP, VIF, VM and RF can be modified;\r\n IF, IOPL, VIP, VIF, VM and all reserved bits are unaffected; RF is cleared. *)\r\n ELSE\r\n RFLAGS <- Pop(); (* 64-bit pop *)\r\n (* All non-reserved bits except IOPL, VIP, VIF, VM and RF can be modified;\r\n IOPL, VIP, VIF, VM and all reserved bits are unaffected; RF is cleared. *)\r\n FI;\r\n ELSE (* OperandSize = 16 *)\r\n EFLAGS[15:0] <- Pop(); (* 16-bit pop *)\r\n (* All non-reserved bits except IOPL can be modified; IOPL and all\r\n reserved bits are unaffected. *)\r\n FI;\r\n FI;\r\n ELSE IF CR4.VME = 1 (* In Virtual-8086 Mode with VME Enabled *)\r\n IF IOPL = 3\r\n THEN IF OperandSize = 32\r\n THEN\r\n EFLAGS <- Pop();\r\n (* All non-reserved bits except IOPL, VIP, VIF, VM, and RF can be modified;\r\n VIP, VIF, VM, IOPL and all reserved bits are unaffected. RF is cleared. *)\r\n ELSE\r\n EFLAGS[15:0] <- Pop(); FI;\r\n (* All non-reserved bits except IOPL can be modified;\r\n IOPL and all reserved bits are unaffected. *)\r\n FI;\r\n ELSE (* IOPL < 3 *)\r\n IF (Operandsize = 32)\r\n THEN\r\n #GP(0); (* Trap to virtual-8086 monitor. *)\r\n ELSE (* Operandsize = 16 *)\r\n tempFLAGS <- Pop();\r\n IF EFLAGS.VIP = 1 AND tempFLAGS[9] = 1\r\n THEN #GP(0);\r\n ELSE\r\n\r\n\r\n\r\n EFLAGS.VIF <- tempFLAGS[9];\r\n EFLAGS[15:0] <- tempFLAGS;\r\n (* All non-reserved bits except IOPL and IF can be modified;\r\n IOPL, IF, and all reserved bits are unaffected. *)\r\n FI;\r\n FI;\r\n FI;\r\n ELSE (* In Virtual-8086 Mode *)\r\n IF IOPL = 3\r\n THEN IF OperandSize = 32\r\n THEN\r\n EFLAGS <- Pop();\r\n (* All non-reserved bits except IOPL, VIP, VIF, VM, and RF can be modified;\r\n VIP, VIF, VM, IOPL and all reserved bits are unaffected. RF is cleared. *)\r\n ELSE\r\n EFLAGS[15:0] <- Pop(); FI;\r\n (* All non-reserved bits except IOPL can be modified;\r\n IOPL and all reserved bits are unaffected. *)\r\n ELSE (* IOPL < 3 *)\r\n #GP(0); (* Trap to virtual-8086 monitor. *)\r\n FI;\r\n FI;\r\nFI;\r\n\r\nFlags Affected\r\nAll flags may be affected; see the Operation section for details.\r\n\r\nProtected Mode Exceptions\r\n#SS(0) If the top of stack is not within the stack segment.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If an unaligned memory reference is made while the current privilege level is 3 and alignment\r\n checking is enabled.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#SS If the top of stack is not within the stack segment.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If the I/O privilege level is less than 3.\r\n If an attempt is made to execute the POPF/POPFD instruction with an operand-size override\r\n prefix.\r\n#SS(0) If the top of stack is not within the stack segment.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If an unaligned memory reference is made while alignment checking is enabled.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame as for protected mode exceptions.\r\n\r\n\r\n\r\n\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#SS(0) If the stack address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "POPF"
},
{
"description": "-R:POPF",
"mnem": "POPFD"
},
{
"description": "-R:POPF",
"mnem": "POPFQ"
},
{
"description": "POR-Bitwise Logical OR\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F EB /r1 RM V/V MMX Bitwise OR of mm/m64 and mm.\r\nPOR mm, mm/m64\r\n66 0F EB /r RM V/V SSE2 Bitwise OR of xmm2/m128 and xmm1.\r\nPOR xmm1, xmm2/m128\r\nVEX.NDS.128.66.0F.WIG EB /r RVM V/V AVX Bitwise OR of xmm2/m128 and xmm3.\r\nVPOR xmm1, xmm2, xmm3/m128\r\nVEX.NDS.256.66.0F.WIG EB /r RVM V/V AVX2 Bitwise OR of ymm2/m256 and ymm3.\r\nVPOR ymm1, ymm2, ymm3/m256\r\nEVEX.NDS.128.66.0F.W0 EB /r FV V/V AVX512VL Bitwise OR of packed doubleword integers in\r\nVPORD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst AVX512F xmm2 and xmm3/m128/m32bcst using\r\n writemask k1.\r\nEVEX.NDS.256.66.0F.W0 EB /r FV V/V AVX512VL Bitwise OR of packed doubleword integers in\r\nVPORD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst AVX512F ymm2 and ymm3/m256/m32bcst using\r\n writemask k1.\r\nEVEX.NDS.512.66.0F.W0 EB /r FV V/V AVX512F Bitwise OR of packed doubleword integers in\r\nVPORD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst zmm2 and zmm3/m512/m32bcst using\r\n writemask k1.\r\nEVEX.NDS.128.66.0F.W1 EB /r FV V/V AVX512VL Bitwise OR of packed quadword integers in\r\nVPORQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst AVX512F xmm2 and xmm3/m128/m64bcst using\r\n writemask k1.\r\nEVEX.NDS.256.66.0F.W1 EB /r FV V/V AVX512VL Bitwise OR of packed quadword integers in\r\nVPORQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst AVX512F ymm2 and ymm3/m256/m64bcst using\r\n writemask k1.\r\nEVEX.NDS.512.66.0F.W1 EB /r FV V/V AVX512F Bitwise OR of packed quadword integers in\r\nVPORQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst zmm2 and zmm3/m512/m64bcst using\r\n writemask k1.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nPerforms a bitwise logical OR operation on the source operand (second operand) and the destination operand (first\r\noperand) and stores the result in the destination operand. Each bit of the result is set to 1 if either or both of the\r\ncorresponding bits of the first and second operands are 1; otherwise, it is set to 0.\r\nIn 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to\r\naccess additional registers (XMM8-XMM15).\r\n\r\n\r\n\r\n\r\n\r\nLegacy SSE version: The source operand can be an MMX technology register or a 64-bit memory location. The\r\ndestination operand is an MMX technology register.\r\n128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first\r\nsource and destination operands can be XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination\r\nregister remain unchanged.\r\nVEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first\r\nsource and destination operands can be XMM registers. Bits (VLMAX-1:128) of the destination YMM register are\r\nzeroed.\r\nVEX.256 encoded version: The second source operand is an YMM register or a 256-bit memory location. The first\r\nsource and destination operands can be YMM registers.\r\nEVEX encoded version: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a\r\nZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a\r\n32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with\r\nwritemask k1 at 32/64-bit granularity.\r\n\r\nOperation\r\nPOR (64-bit operand)\r\nDEST <- DEST OR SRC\r\n\r\n\r\nPOR (128-bit Legacy SSE version)\r\nDEST <- DEST OR SRC\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVPOR (VEX.128 encoded version)\r\nDEST <- SRC1 OR SRC2\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPOR (VEX.256 encoded version)\r\nDEST <- SRC1 OR SRC2\r\nDEST[VLMAX-1:256] <- 0\r\n\r\nVPORD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN DEST[i+31:i] <- SRC1[i+31:i] BITWISE OR SRC2[31:0]\r\n ELSE DEST[i+31:i] <- SRC1[i+31:i] BITWISE OR SRC2[i+31:i]\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI;\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPORD __m512i _mm512_or_epi32(__m512i a, __m512i b);\r\nVPORD __m512i _mm512_mask_or_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);\r\nVPORD __m512i _mm512_maskz_or_epi32( __mmask16 k, __m512i a, __m512i b);\r\nVPORD __m256i _mm256_or_epi32(__m256i a, __m256i b);\r\nVPORD __m256i _mm256_mask_or_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b,);\r\nVPORD __m256i _mm256_maskz_or_epi32( __mmask8 k, __m256i a, __m256i b);\r\nVPORD __m128i _mm_or_epi32(__m128i a, __m128i b);\r\nVPORD __m128i _mm_mask_or_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPORD __m128i _mm_maskz_or_epi32( __mmask8 k, __m128i a, __m128i b);\r\nVPORQ __m512i _mm512_or_epi64(__m512i a, __m512i b);\r\nVPORQ __m512i _mm512_mask_or_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);\r\nVPORQ __m512i _mm512_maskz_or_epi64(__mmask8 k, __m512i a, __m512i b);\r\nVPORQ __m256i _mm256_or_epi64(__m256i a, int imm);\r\nVPORQ __m256i _mm256_mask_or_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);\r\nVPORQ __m256i _mm256_maskz_or_epi64( __mmask8 k, __m256i a, __m256i b);\r\nVPORQ __m128i _mm_or_epi64(__m128i a, __m128i b);\r\nVPORQ __m128i _mm_mask_or_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPORQ __m128i _mm_maskz_or_epi64( __mmask8 k, __m128i a, __m128i b);\r\nPOR __m64 _mm_or_si64(__m64 m1, __m64 m2)\r\n(V)POR: __m128i _mm_or_si128(__m128i m1, __m128i m2)\r\nVPOR: __m256i _mm256_or_si256 ( __m256i a, __m256i b)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "POR"
},
{
"description": "PREFETCHW-Prefetch Data into Caches in Anticipation of a Write\r\n Opcode/ Op/ 64/32 bit CPUID Description\r\n Instruction En Mode Feature\r\n Support Flag\r\n 0F 0D /1 A V/V PRFCHW Move data from m8 closer to the processor in anticipation of a\r\n PREFETCHW m8 write.\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (r) NA NA NA\r\n\r\nDescription\r\nFetches the cache line of data from memory that contains the byte specified with the source operand to a location\r\nin the 1st or 2nd level cache and invalidates other cached instances of the line.\r\nThe source operand is a byte memory location. If the line selected is already present in the lowest level cache and\r\nis already in an exclusively owned state, no data movement occurs. Prefetches from non-writeback memory are\r\nignored.\r\nThe PREFETCHW instruction is merely a hint and does not affect program behavior. If executed, this instruction\r\nmoves data closer to the processor and invalidates other cached copies in anticipation of the line being written to\r\nin the future.\r\nThe characteristic of prefetch locality hints is implementation-dependent, and can be overloaded or ignored by a\r\nprocessor implementation. The amount of data prefetched is also processor implementation-dependent. It will,\r\nhowever, be a minimum of 32 bytes. Additional details of the implementation-dependent locality hints are\r\ndescribed in Section 7.4 of Intel 64 and IA-32 Architectures Optimization Reference Manual.\r\nIt should be noted that processors are free to speculatively fetch and cache data with exclusive ownership from\r\nsystem memory regions that permit such accesses (that is, the WB memory type). A PREFETCHW instruction is\r\nconsidered a hint to this speculative behavior. Because this speculative fetching can occur at any time and is not\r\ntied to instruction execution, a PREFETCHW instruction is not ordered with respect to the fence instructions\r\n(MFENCE, SFENCE, and LFENCE) or locked memory references. A PREFETCHW instruction is also unordered with\r\nrespect to CLFLUSH and CLFLUSHOPT instructions, other PREFETCHW instructions, or any other general instruction\r\nIt is ordered with respect to serializing instructions such as CPUID, WRMSR, OUT, and MOV CR.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nFETCH_WITH_EXCLUSIVE_OWNERSHIP (m8);\r\n\r\nFlags Affected\r\nAll flags are affected\r\n\r\nC/C++ Compiler Intrinsic Equivalent\r\nvoid _m_prefetchw( void * );\r\n\r\nProtected Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\n64-Bit Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PREFETCHW"
},
{
"description": "PREFETCHWT1-Prefetch Vector Data Into Caches with Intent to Write and T1 Hint\r\n Opcode/ Op/ 64/32 bit CPUID Feature Description\r\n Instruction En Mode Flag\r\n Support\r\n 0F 0D /2 M V/V PREFETCHWT1 Move data from m8 closer to the processor using T1 hint\r\n PREFETCHWT1 m8 with intent to write.\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (r) NA NA NA\r\n\r\nDescription\r\nFetches the line of data from memory that contains the byte specified with the source operand to a location in the\r\ncache hierarchy specified by an intent to write hint (so that data is brought into 'Exclusive' state via a request for\r\nownership) and a locality hint:\r\n. T1 (temporal data with respect to first level cache)-prefetch data into the second level cache.\r\nThe source operand is a byte memory location. (The locality hints are encoded into the machine level instruction\r\nusing bits 3 through 5 of the ModR/M byte. Use of any ModR/M value other than the specified ones will lead to\r\nunpredictable behavior.)\r\nIf the line selected is already present in the cache hierarchy at a level closer to the processor, no data movement\r\noccurs. Prefetches from uncacheable or WC memory are ignored.\r\nThe PREFETCHh instruction is merely a hint and does not affect program behavior. If executed, this instruction\r\nmoves data closer to the processor in anticipation of future use.\r\nThe implementation of prefetch locality hints is implementation-dependent, and can be overloaded or ignored by a\r\nprocessor implementation. The amount of data prefetched is also processor implementation-dependent. It will,\r\nhowever, be a minimum of 32 bytes.\r\nIt should be noted that processors are free to speculatively fetch and cache data from system memory regions that\r\nare assigned a memory-type that permits speculative reads (that is, the WB, WC, and WT memory types). A\r\nPREFETCHh instruction is considered a hint to this speculative behavior. Because this speculative fetching can occur\r\nat any time and is not tied to instruction execution, a PREFETCHh instruction is not ordered with respect to the\r\nfence instructions (MFENCE, SFENCE, and LFENCE) or locked memory references. A PREFETCHh instruction is also\r\nunordered with respect to CLFLUSH and CLFLUSHOPT instructions, other PREFETCHh instructions, or any other\r\ngeneral instruction. It is ordered with respect to serializing instructions such as CPUID, WRMSR, OUT, and MOV CR.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nPREFETCH(mem, Level, State) Prefetches a byte memory location pointed by 'mem' into the cache level specified by 'Level'; a request\r\nfor exclusive/ownership is done if 'State' is 1. Note that the memory location ignore cache line splits. This operation is considered a\r\nhint for the processor and may be skipped depending on implementation.\r\n\r\nPrefetch (m8, Level = 1, EXCLUSIVE=1);\r\n\r\nFlags Affected\r\nAll flags are affected\r\n\r\nC/C++ Compiler Intrinsic Equivalent\r\nvoid _mm_prefetch( char const *, int hint= _MM_HINT_ET1);\r\n\r\nProtected Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\n64-Bit Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PREFETCHWT1"
},
{
"description": "PREFETCHh-Prefetch Data Into Caches\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F 18 /1 PREFETCHT0 m8 M Valid Valid Move data from m8 closer to the processor\r\n using T0 hint.\r\n 0F 18 /2 PREFETCHT1 m8 M Valid Valid Move data from m8 closer to the processor\r\n using T1 hint.\r\n 0F 18 /3 PREFETCHT2 m8 M Valid Valid Move data from m8 closer to the processor\r\n using T2 hint.\r\n 0F 18 /0 PREFETCHNTA m8 M Valid Valid Move data from m8 closer to the processor\r\n using NTA hint.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (r) NA NA NA\r\n\r\n\r\nDescription\r\nFetches the line of data from memory that contains the byte specified with the source operand to a location in the\r\ncache hierarchy specified by a locality hint:\r\n. T0 (temporal data)-prefetch data into all levels of the cache hierarchy.\r\n. T1 (temporal data with respect to first level cache misses)-prefetch data into level 2 cache and higher.\r\n. T2 (temporal data with respect to second level cache misses)-prefetch data into level 3 cache and higher, or\r\n an implementation-specific choice.\r\n. NTA (non-temporal data with respect to all cache levels)-prefetch data into non-temporal cache structure and\r\n into a location close to the processor, minimizing cache pollution.\r\nThe source operand is a byte memory location. (The locality hints are encoded into the machine level instruction\r\nusing bits 3 through 5 of the ModR/M byte.)\r\nIf the line selected is already present in the cache hierarchy at a level closer to the processor, no data movement\r\noccurs. Prefetches from uncacheable or WC memory are ignored.\r\nThe PREFETCHh instruction is merely a hint and does not affect program behavior. If executed, this instruction\r\nmoves data closer to the processor in anticipation of future use.\r\nThe implementation of prefetch locality hints is implementation-dependent, and can be overloaded or ignored by a\r\nprocessor implementation. The amount of data prefetched is also processor implementation-dependent. It will,\r\nhowever, be a minimum of 32 bytes. Additional details of the implementation-dependent locality hints are\r\ndescribed in Section 7.4 of Intel 64 and IA-32 Architectures Optimization Reference Manual.\r\nIt should be noted that processors are free to speculatively fetch and cache data from system memory regions that\r\nare assigned a memory-type that permits speculative reads (that is, the WB, WC, and WT memory types). A\r\nPREFETCHh instruction is considered a hint to this speculative behavior. Because this speculative fetching can occur\r\nat any time and is not tied to instruction execution, a PREFETCHh instruction is not ordered with respect to the\r\nfence instructions (MFENCE, SFENCE, and LFENCE) or locked memory references. A PREFETCHh instruction is also\r\nunordered with respect to CLFLUSH and CLFLUSHOPT instructions, other PREFETCHh instructions, or any other\r\ngeneral instruction. It is ordered with respect to serializing instructions such as CPUID, WRMSR, OUT, and MOV CR.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nFETCH (m8);\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nvoid _mm_prefetch(char *p, int i)\r\nThe argument \"*p\" gives the address of the byte (and corresponding cache line) to be prefetched. The value \"i\"\r\ngives a constant (_MM_HINT_T0, _MM_HINT_T1, _MM_HINT_T2, or _MM_HINT_NTA) that specifies the type of\r\nprefetch operation to be performed.\r\n\r\nNumeric Exceptions\r\nNone.\r\n\r\nExceptions (All Operating Modes)\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PREFETCHh"
},
{
"description": "PROLD/PROLVD/PROLQ/PROLVQ-Bit Rotate Left\r\n Opcode/ Op / En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.128.66.0F38.W0 15 /r FV-RVM V/V AVX512VL Rotate doublewords in xmm2 left by count in the\r\n VPROLVD xmm1 {k1}{z}, xmm2, AVX512F corresponding element of xmm3/m128/m32bcst.\r\n xmm3/m128/m32bcst Result written to xmm1 under writemask k1.\r\n EVEX.NDD.128.66.0F.W0 72 /1 ib FV-VMI V/V AVX512VL Rotate doublewords in xmm2/m128/m32bcst left\r\n VPROLD xmm1 {k1}{z}, AVX512F by imm8. Result written to xmm1 using\r\n xmm2/m128/m32bcst, imm8 writemask k1.\r\n EVEX.NDS.128.66.0F38.W1 15 /r FV-RVM V/V AVX512VL Rotate quadwords in xmm2 left by count in the\r\n VPROLVQ xmm1 {k1}{z}, xmm2, AVX512F corresponding element of xmm3/m128/m64bcst.\r\n xmm3/m128/m64bcst Result written to xmm1 under writemask k1.\r\n EVEX.NDD.128.66.0F.W1 72 /1 ib FV-VMI V/V AVX512VL Rotate quadwords in xmm2/m128/m64bcst left\r\n VPROLQ xmm1 {k1}{z}, AVX512F by imm8. Result written to xmm1 using\r\n xmm2/m128/m64bcst, imm8 writemask k1.\r\n EVEX.NDS.256.66.0F38.W0 15 /r FV-RVM V/V AVX512VL Rotate doublewords in ymm2 left by count in the\r\n VPROLVD ymm1 {k1}{z}, ymm2, AVX512F corresponding element of ymm3/m256/m32bcst.\r\n ymm3/m256/m32bcst Result written to ymm1 under writemask k1.\r\n EVEX.NDD.256.66.0F.W0 72 /1 ib FV-VMI V/V AVX512VL Rotate doublewords in ymm2/m256/m32bcst left\r\n VPROLD ymm1 {k1}{z}, AVX512F by imm8. Result written to ymm1 using\r\n ymm2/m256/m32bcst, imm8 writemask k1.\r\n EVEX.NDS.256.66.0F38.W1 15 /r FV-RVM V/V AVX512VL Rotate quadwords in ymm2 left by count in the\r\n VPROLVQ ymm1 {k1}{z}, ymm2, AVX512F corresponding element of ymm3/m256/m64bcst.\r\n ymm3/m256/m64bcst Result written to ymm1 under writemask k1.\r\n EVEX.NDD.256.66.0F.W1 72 /1 ib FV-VMI V/V AVX512VL Rotate quadwords in ymm2/m256/m64bcst left\r\n VPROLQ ymm1 {k1}{z}, AVX512F by imm8. Result written to ymm1 using\r\n ymm2/m256/m64bcst, imm8 writemask k1.\r\n EVEX.NDS.512.66.0F38.W0 15 /r FV-RVM V/V AVX512F Rotate left of doublewords in zmm2 by count in\r\n VPROLVD zmm1 {k1}{z}, zmm2, the corresponding element of\r\n zmm3/m512/m32bcst zmm3/m512/m32bcst. Result written to zmm1\r\n using writemask k1.\r\n EVEX.NDD.512.66.0F.W0 72 /1 ib FV-VMI V/V AVX512F Rotate left of doublewords in\r\n VPROLD zmm1 {k1}{z}, zmm3/m512/m32bcst by imm8. Result written to\r\n zmm2/m512/m32bcst, imm8 zmm1 using writemask k1.\r\n EVEX.NDS.512.66.0F38.W1 15 /r FV-RVM V/V AVX512F Rotate quadwords in zmm2 left by count in the\r\n VPROLVQ zmm1 {k1}{z}, zmm2, corresponding element of zmm3/m512/m64bcst.\r\n zmm3/m512/m64bcst Result written to zmm1under writemask k1.\r\n EVEX.NDD.512.66.0F.W1 72 /1 ib FV-VMI V/V AVX512F Rotate quadwords in zmm2/m512/m64bcst left\r\n VPROLQ zmm1 {k1}{z}, by imm8. Result written to zmm1 using\r\n zmm2/m512/m64bcst, imm8 writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV-VMI VEX.vvvv (w) ModRM:r/m (R) Imm8 NA\r\n FV-RVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\n\r\n\r\n\r\nDescription\r\nRotates the bits in the individual data elements (doublewords, or quadword) in the first source operand to the left\r\nby the number of bits specified in the count operand. If the value specified by the count operand is greater than 31\r\n(for doublewords), or 63 (for a quadword), then the count operand modulo the data size (32 or 64) is used.\r\nEVEX.128 encoded version: The destination operand is a XMM register. The source operand is a XMM register or a\r\nmemory location (for immediate form). The count operand can come either from an XMM register or a memory\r\nlocation or an 8-bit immediate. Bits (MAX_VL-1:128) of the corresponding ZMM register are zeroed.\r\nEVEX.256 encoded version: The destination operand is a YMM register. The source operand is a YMM register or a\r\nmemory location (for immediate form). The count operand can come either from an XMM register or a memory\r\nlocation or an 8-bit immediate. Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed.\r\nEVEX.512 encoded version: The destination operand is a ZMM register updated according to the writemask. For the\r\ncount operand in immediate form, the source operand can be a ZMM register, a 512-bit memory location or a 512-\r\nbit vector broadcasted from a 32/64-bit memory location, the count operand is an 8-bit immediate. For the count\r\noperand in variable form, the first source operand (the second operand) is a ZMM register and the counter operand\r\n(the third operand) is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32/64-bit\r\nmemory location.\r\n\r\nOperation\r\nLEFT_ROTATE_DWORDS(SRC, COUNT_SRC)\r\nCOUNT <- COUNT_SRC modulo 32;\r\nDEST[31:0] <- (SRC << COUNT) | (SRC >> (32 - COUNT));\r\n\r\nLEFT_ROTATE_QWORDS(SRC, COUNT_SRC)\r\nCOUNT <- COUNT_SRC modulo 64;\r\nDEST[63:0] <- (SRC << COUNT) | (SRC >> (64 - COUNT));\r\n\r\nVPROLD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC1 *is memory*)\r\n THEN DEST[i+31:i] <- LEFT_ROTATE_DWORDS(SRC1[31:0], imm8)\r\n ELSE DEST[i+31:i] <- LEFT_ROTATE_DWORDS(SRC1[i+31:i], imm8)\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVPROLVD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN DEST[i+31:i] <- LEFT_ROTATE_DWORDS(SRC1[i+31:i], SRC2[31:0])\r\n ELSE DEST[i+31:i] <- LEFT_ROTATE_DWORDS(SRC1[i+31:i], SRC2[i+31:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPROLQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC1 *is memory*)\r\n THEN DEST[i+63:i] <- LEFT_ROTATE_QWORDS(SRC1[63:0], imm8)\r\n ELSE DEST[i+63:i] <- LEFT_ROTATE_QWORDS(SRC1[i+63:i], imm8)\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVPROLVQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN DEST[i+63:i] <- LEFT_ROTATE_QWORDS(SRC1[i+63:i], SRC2[63:0])\r\n ELSE DEST[i+63:i] <- LEFT_ROTATE_QWORDS(SRC1[i+63:i], SRC2[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPROLD __m512i _mm512_rol_epi32(__m512i a, int imm);\r\nVPROLD __m512i _mm512_mask_rol_epi32(__m512i a, __mmask16 k, __m512i b, int imm);\r\nVPROLD __m512i _mm512_maskz_rol_epi32( __mmask16 k, __m512i a, int imm);\r\nVPROLD __m256i _mm256_rol_epi32(__m256i a, int imm);\r\nVPROLD __m256i _mm256_mask_rol_epi32(__m256i a, __mmask8 k, __m256i b, int imm);\r\nVPROLD __m256i _mm256_maskz_rol_epi32( __mmask8 k, __m256i a, int imm);\r\nVPROLD __m128i _mm_rol_epi32(__m128i a, int imm);\r\nVPROLD __m128i _mm_mask_rol_epi32(__m128i a, __mmask8 k, __m128i b, int imm);\r\nVPROLD __m128i _mm_maskz_rol_epi32( __mmask8 k, __m128i a, int imm);\r\nVPROLQ __m512i _mm512_rol_epi64(__m512i a, int imm);\r\nVPROLQ __m512i _mm512_mask_rol_epi64(__m512i a, __mmask8 k, __m512i b, int imm);\r\nVPROLQ __m512i _mm512_maskz_rol_epi64(__mmask8 k, __m512i a, int imm);\r\nVPROLQ __m256i _mm256_rol_epi64(__m256i a, int imm);\r\nVPROLQ __m256i _mm256_mask_rol_epi64(__m256i a, __mmask8 k, __m256i b, int imm);\r\nVPROLQ __m256i _mm256_maskz_rol_epi64( __mmask8 k, __m256i a, int imm);\r\nVPROLQ __m128i _mm_rol_epi64(__m128i a, int imm);\r\nVPROLQ __m128i _mm_mask_rol_epi64(__m128i a, __mmask8 k, __m128i b, int imm);\r\nVPROLQ __m128i _mm_maskz_rol_epi64( __mmask8 k, __m128i a, int imm);\r\nVPROLVD __m512i _mm512_rolv_epi32(__m512i a, __m512i cnt);\r\nVPROLVD __m512i _mm512_mask_rolv_epi32(__m512i a, __mmask16 k, __m512i b, __m512i cnt);\r\nVPROLVD __m512i _mm512_maskz_rolv_epi32(__mmask16 k, __m512i a, __m512i cnt);\r\nVPROLVD __m256i _mm256_rolv_epi32(__m256i a, __m256i cnt);\r\nVPROLVD __m256i _mm256_mask_rolv_epi32(__m256i a, __mmask8 k, __m256i b, __m256i cnt);\r\nVPROLVD __m256i _mm256_maskz_rolv_epi32(__mmask8 k, __m256i a, __m256i cnt);\r\nVPROLVD __m128i _mm_rolv_epi32(__m128i a, __m128i cnt);\r\nVPROLVD __m128i _mm_mask_rolv_epi32(__m128i a, __mmask8 k, __m128i b, __m128i cnt);\r\nVPROLVD __m128i _mm_maskz_rolv_epi32(__mmask8 k, __m128i a, __m128i cnt);\r\nVPROLVQ __m512i _mm512_rolv_epi64(__m512i a, __m512i cnt);\r\nVPROLVQ __m512i _mm512_mask_rolv_epi64(__m512i a, __mmask8 k, __m512i b, __m512i cnt);\r\nVPROLVQ __m512i _mm512_maskz_rolv_epi64( __mmask8 k, __m512i a, __m512i cnt);\r\nVPROLVQ __m256i _mm256_rolv_epi64(__m256i a, __m256i cnt);\r\nVPROLVQ __m256i _mm256_mask_rolv_epi64(__m256i a, __mmask8 k, __m256i b, __m256i cnt);\r\nVPROLVQ __m256i _mm256_maskz_rolv_epi64(__mmask8 k, __m256i a, __m256i cnt);\r\nVPROLVQ __m128i _mm_rolv_epi64(__m128i a, __m128i cnt);\r\nVPROLVQ __m128i _mm_mask_rolv_epi64(__m128i a, __mmask8 k, __m128i b, __m128i cnt);\r\nVPROLVQ __m128i _mm_maskz_rolv_epi64(__mmask8 k, __m128i a, __m128i cnt);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PROLD"
},
{
"description": "-R:PROLD",
"mnem": "PROLQ"
},
{
"description": "-R:PROLD",
"mnem": "PROLVD"
},
{
"description": "-R:PROLD",
"mnem": "PROLVQ"
},
{
"description": "PRORD/PRORVD/PRORQ/PRORVQ-Bit Rotate Right\r\n Opcode/ Op / En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.128.66.0F38.W0 14 /r FV-RVM V/V AVX512VL Rotate doublewords in xmm2 right by count in\r\n VPRORVD xmm1 {k1}{z}, xmm2, AVX512F the corresponding element of\r\n xmm3/m128/m32bcst xmm3/m128/m32bcst, store result using\r\n writemask k1.\r\n EVEX.NDD.128.66.0F.W0 72 /0 ib FV-VMI V/V AVX512VL Rotate doublewords in xmm2/m128/m32bcst\r\n VPRORD xmm1 {k1}{z}, AVX512F right by imm8, store result using writemask k1.\r\n xmm2/m128/m32bcst, imm8\r\n EVEX.NDS.128.66.0F38.W1 14 /r FV-RVM V/V AVX512VL Rotate quadwords in xmm2 right by count in the\r\n VPRORVQ xmm1 {k1}{z}, xmm2, AVX512F corresponding element of xmm3/m128/m64bcst,\r\n xmm3/m128/m64bcst store result using writemask k1.\r\n EVEX.NDD.128.66.0F.W1 72 /0 ib FV-VMI V/V AVX512VL Rotate quadwords in xmm2/m128/m64bcst right\r\n VPRORQ xmm1 {k1}{z}, AVX512F by imm8, store result using writemask k1.\r\n xmm2/m128/m64bcst, imm8\r\n EVEX.NDS.256.66.0F38.W0 14 /r FV-RVM V/V AVX512VL Rotate doublewords in ymm2 right by count in\r\n VPRORVD ymm1 {k1}{z}, ymm2, AVX512F the corresponding element of\r\n ymm3/m256/m32bcst ymm3/m256/m32bcst, store using result\r\n writemask k1.\r\n EVEX.NDD.256.66.0F.W0 72 /0 ib FV-VMI V/V AVX512VL Rotate doublewords in ymm2/m256/m32bcst\r\n VPRORD ymm1 {k1}{z}, AVX512F right by imm8, store result using writemask k1.\r\n ymm2/m256/m32bcst, imm8\r\n EVEX.NDS.256.66.0F38.W1 14 /r FV-RVM V/V AVX512VL Rotate quadwords in ymm2 right by count in the\r\n VPRORVQ ymm1 {k1}{z}, ymm2, AVX512F corresponding element of ymm3/m256/m64bcst,\r\n ymm3/m256/m64bcst store result using writemask k1.\r\n EVEX.NDD.256.66.0F.W1 72 /0 ib FV-VMI V/V AVX512VL Rotate quadwords in ymm2/m256/m64bcst right\r\n VPRORQ ymm1 {k1}{z}, AVX512F by imm8, store result using writemask k1.\r\n ymm2/m256/m64bcst, imm8\r\n EVEX.NDS.512.66.0F38.W0 14 /r FV-RVM V/V AVX512F Rotate doublewords in zmm2 right by count in\r\n VPRORVD zmm1 {k1}{z}, zmm2, the corresponding element of\r\n zmm3/m512/m32bcst zmm3/m512/m32bcst, store result using\r\n writemask k1.\r\n EVEX.NDD.512.66.0F.W0 72 /0 ib FV-VMI V/V AVX512F Rotate doublewords in zmm2/m512/m32bcst\r\n VPRORD zmm1 {k1}{z}, right by imm8, store result using writemask k1.\r\n zmm2/m512/m32bcst, imm8\r\n EVEX.NDS.512.66.0F38.W1 14 /r FV-RVM V/V AVX512F Rotate quadwords in zmm2 right by count in the\r\n VPRORVQ zmm1 {k1}{z}, zmm2, corresponding element of zmm3/m512/m64bcst,\r\n zmm3/m512/m64bcst store result using writemask k1.\r\n EVEX.NDD.512.66.0F.W1 72 /0 ib FV-VMI V/V AVX512F Rotate quadwords in zmm2/m512/m64bcst right\r\n VPRORQ zmm1 {k1}{z}, by imm8, store result using writemask k1.\r\n zmm2/m512/m64bcst, imm8\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV-VMI VEX.vvvv (w) ModRM:r/m (R) Imm8 NA\r\n FV-RVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\n\r\n\r\n\r\nDescription\r\nRotates the bits in the individual data elements (doublewords, or quadword) in the first source operand to the right\r\nby the number of bits specified in the count operand. If the value specified by the count operand is greater than 31\r\n(for doublewords), or 63 (for a quadword), then the count operand modulo the data size (32 or 64) is used.\r\nEVEX.128 encoded version: The destination operand is a XMM register. The source operand is a XMM register or a\r\nmemory location (for immediate form). The count operand can come either from an XMM register or a memory\r\nlocation or an 8-bit immediate. Bits (MAX_VL-1:128) of the corresponding ZMM register are zeroed.\r\nEVEX.256 encoded version: The destination operand is a YMM register. The source operand is a YMM register or a\r\nmemory location (for immediate form). The count operand can come either from an XMM register or a memory\r\nlocation or an 8-bit immediate. Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed.\r\nEVEX.512 encoded version: The destination operand is a ZMM register updated according to the writemask. For the\r\ncount operand in immediate form, the source operand can be a ZMM register, a 512-bit memory location or a 512-\r\nbit vector broadcasted from a 32/64-bit memory location, the count operand is an 8-bit immediate. For the count\r\noperand in variable form, the first source operand (the second operand) is a ZMM register and the counter operand\r\n(the third operand) is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32/64-bit\r\nmemory location.\r\n\r\nOperation\r\nRIGHT_ROTATE_DWORDS(SRC, COUNT_SRC)\r\nCOUNT <- COUNT_SRC modulo 32;\r\nDEST[31:0] <- (SRC >> COUNT) | (SRC << (32 - COUNT));\r\n\r\nRIGHT_ROTATE_QWORDS(SRC, COUNT_SRC)\r\nCOUNT <- COUNT_SRC modulo 64;\r\nDEST[63:0] <- (SRC >> COUNT) | (SRC << (64 - COUNT));\r\n\r\nVPRORD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC1 *is memory*)\r\n THEN DEST[i+31:i] <- RIGHT_ROTATE_DWORDS( SRC1[31:0], imm8)\r\n ELSE DEST[i+31:i] <- RIGHT_ROTATE_DWORDS(SRC1[i+31:i], imm8)\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVPRORVD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN DEST[i+31:i] <- RIGHT_ROTATE_DWORDS(SRC1[i+31:i], SRC2[31:0])\r\n ELSE DEST[i+31:i] <- RIGHT_ROTATE_DWORDS(SRC1[i+31:i], SRC2[i+31:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPRORQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC1 *is memory*)\r\n THEN DEST[i+63:i] <- RIGHT_ROTATE_QWORDS(SRC1[63:0], imm8)\r\n ELSE DEST[i+63:i] <- RIGHT_ROTATE_QWORDS(SRC1[i+63:i], imm8])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVPRORVQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN DEST[i+63:i] <- RIGHT_ROTATE_QWORDS(SRC1[i+63:i], SRC2[63:0])\r\n ELSE DEST[i+63:i] <- RIGHT_ROTATE_QWORDS(SRC1[i+63:i], SRC2[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPRORD __m512i _mm512_ror_epi32(__m512i a, int imm);\r\nVPRORD __m512i _mm512_mask_ror_epi32(__m512i a, __mmask16 k, __m512i b, int imm);\r\nVPRORD __m512i _mm512_maskz_ror_epi32( __mmask16 k, __m512i a, int imm);\r\nVPRORD __m256i _mm256_ror_epi32(__m256i a, int imm);\r\nVPRORD __m256i _mm256_mask_ror_epi32(__m256i a, __mmask8 k, __m256i b, int imm);\r\nVPRORD __m256i _mm256_maskz_ror_epi32( __mmask8 k, __m256i a, int imm);\r\nVPRORD __m128i _mm_ror_epi32(__m128i a, int imm);\r\nVPRORD __m128i _mm_mask_ror_epi32(__m128i a, __mmask8 k, __m128i b, int imm);\r\nVPRORD __m128i _mm_maskz_ror_epi32( __mmask8 k, __m128i a, int imm);\r\nVPRORQ __m512i _mm512_ror_epi64(__m512i a, int imm);\r\nVPRORQ __m512i _mm512_mask_ror_epi64(__m512i a, __mmask8 k, __m512i b, int imm);\r\nVPRORQ __m512i _mm512_maskz_ror_epi64(__mmask8 k, __m512i a, int imm);\r\nVPRORQ __m256i _mm256_ror_epi64(__m256i a, int imm);\r\nVPRORQ __m256i _mm256_mask_ror_epi64(__m256i a, __mmask8 k, __m256i b, int imm);\r\nVPRORQ __m256i _mm256_maskz_ror_epi64( __mmask8 k, __m256i a, int imm);\r\nVPRORQ __m128i _mm_ror_epi64(__m128i a, int imm);\r\nVPRORQ __m128i _mm_mask_ror_epi64(__m128i a, __mmask8 k, __m128i b, int imm);\r\nVPRORQ __m128i _mm_maskz_ror_epi64( __mmask8 k, __m128i a, int imm);\r\nVPRORVD __m512i _mm512_rorv_epi32(__m512i a, __m512i cnt);\r\nVPRORVD __m512i _mm512_mask_rorv_epi32(__m512i a, __mmask16 k, __m512i b, __m512i cnt);\r\nVPRORVD __m512i _mm512_maskz_rorv_epi32(__mmask16 k, __m512i a, __m512i cnt);\r\nVPRORVD __m256i _mm256_rorv_epi32(__m256i a, __m256i cnt);\r\nVPRORVD __m256i _mm256_mask_rorv_epi32(__m256i a, __mmask8 k, __m256i b, __m256i cnt);\r\nVPRORVD __m256i _mm256_maskz_rorv_epi32(__mmask8 k, __m256i a, __m256i cnt);\r\nVPRORVD __m128i _mm_rorv_epi32(__m128i a, __m128i cnt);\r\nVPRORVD __m128i _mm_mask_rorv_epi32(__m128i a, __mmask8 k, __m128i b, __m128i cnt);\r\nVPRORVD __m128i _mm_maskz_rorv_epi32(__mmask8 k, __m128i a, __m128i cnt);\r\nVPRORVQ __m512i _mm512_rorv_epi64(__m512i a, __m512i cnt);\r\nVPRORVQ __m512i _mm512_mask_rorv_epi64(__m512i a, __mmask8 k, __m512i b, __m512i cnt);\r\nVPRORVQ __m512i _mm512_maskz_rorv_epi64( __mmask8 k, __m512i a, __m512i cnt);\r\nVPRORVQ __m256i _mm256_rorv_epi64(__m256i a, __m256i cnt);\r\nVPRORVQ __m256i _mm256_mask_rorv_epi64(__m256i a, __mmask8 k, __m256i b, __m256i cnt);\r\nVPRORVQ __m256i _mm256_maskz_rorv_epi64(__mmask8 k, __m256i a, __m256i cnt);\r\nVPRORVQ __m128i _mm_rorv_epi64(__m128i a, __m128i cnt);\r\nVPRORVQ __m128i _mm_mask_rorv_epi64(__m128i a, __mmask8 k, __m128i b, __m128i cnt);\r\nVPRORVQ __m128i _mm_maskz_rorv_epi64(__mmask8 k, __m128i a, __m128i cnt);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PRORD"
},
{
"description": "-R:PRORD",
"mnem": "PRORQ"
},
{
"description": "-R:PRORD",
"mnem": "PRORVD"
},
{
"description": "-R:PRORD",
"mnem": "PRORVQ"
},
{
"description": "PSADBW-Compute Sum of Absolute Differences\r\nOpcode/ Op/ 64/32 bit CPUID Feature Description\r\nInstruction En Mode Flag\r\n Support\r\n0F F6 /r1 RM V/V SSE Computes the absolute differences of the\r\nPSADBW mm1, mm2/m64 packed unsigned byte integers from mm2\r\n /m64 and mm1; differences are then summed\r\n to produce an unsigned word integer result.\r\n66 0F F6 /r RM V/V SSE2 Computes the absolute differences of the\r\nPSADBW xmm1, xmm2/m128 packed unsigned byte integers from xmm2\r\n /m128 and xmm1; the 8 low differences and 8\r\n high differences are then summed separately\r\n to produce two unsigned word integer results.\r\nVEX.NDS.128.66.0F.WIG F6 /r RVM V/V AVX Computes the absolute differences of the\r\nVPSADBW xmm1, xmm2, xmm3/m128 packed unsigned byte integers from xmm3\r\n /m128 and xmm2; the 8 low differences and 8\r\n high differences are then summed separately\r\n to produce two unsigned word integer results.\r\nVEX.NDS.256.66.0F.WIG F6 /r RVM V/V AVX2 Computes the absolute differences of the\r\nVPSADBW ymm1, ymm2, ymm3/m256 packed unsigned byte integers from ymm3\r\n /m256 and ymm2; then each consecutive 8\r\n differences are summed separately to produce\r\n four unsigned word integer results.\r\nEVEX.NDS.128.66.0F.WIG F6 /r FVM V/V AVX512VL Computes the absolute differences of the\r\nVPSADBW xmm1, xmm2, xmm3/m128 AVX512BW packed unsigned byte integers from xmm3\r\n /m128 and xmm2; then each consecutive 8\r\n differences are summed separately to produce\r\n four unsigned word integer results.\r\nEVEX.NDS.256.66.0F.WIG F6 /r FVM V/V AVX512VL Computes the absolute differences of the\r\nVPSADBW ymm1, ymm2, ymm3/m256 AVX512BW packed unsigned byte integers from ymm3\r\n /m256 and ymm2; then each consecutive 8\r\n differences are summed separately to produce\r\n four unsigned word integer results.\r\nEVEX.NDS.512.66.0F.WIG F6 /r FVM V/V AVX512BW Computes the absolute differences of the\r\nVPSADBW zmm1, zmm2, zmm3/m512 packed unsigned byte integers from zmm3\r\n /m512 and zmm2; then each consecutive 8\r\n differences are summed separately to produce\r\n four unsigned word integer results.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FVM ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nComputes the absolute value of the difference of 8 unsigned byte integers from the source operand (second\r\n\r\n\r\n\r\noperand) and from the destination operand (first operand). These 8 differences are then summed to produce an\r\nunsigned word integer result that is stored in the destination operand. Figure 4-14 shows the operation of the\r\nPSADBW instruction when using 64-bit operands.\r\nWhen operating on 64-bit operands, the word integer result is stored in the low word of the destination operand,\r\nand the remaining bytes in the destination operand are cleared to all 0s.\r\nWhen operating on 128-bit operands, two packed results are computed. Here, the 8 low-order bytes of the source\r\nand destination operands are operated on to produce a word result that is stored in the low word of the destination\r\noperand, and the 8 high-order bytes are operated on to produce a word result that is stored in bits 64 through 79\r\nof the destination operand. The remaining bytes of the destination operand are cleared.\r\nFor 256-bit version, the third group of 8 differences are summed to produce an unsigned word in bits[143:128] of\r\nthe destination register and the fourth group of 8 differences are summed to produce an unsigned word in\r\nbits[207:192] of the destination register. The remaining words of the destination are set to 0.\r\nFor 512-bit version, the fifth group result is stored in bits [271:256] of the destination. The result from the sixth\r\ngroup is stored in bits [335:320]. The results for the seventh and eighth group are stored respectively in bits\r\n[399:384] and bits [463:447], respectively. The remaining bits in the destination are set to 0.\r\nIn 64-bit mode and not encoded by VEX/EVEX prefix, using a REX prefix in the form of REX.R permits this instruc-\r\ntion to access additional registers (XMM8-XMM15).\r\nLegacy SSE version: The source operand can be an MMX technology register or a 64-bit memory location. The\r\ndestination operand is an MMX technology register.\r\n128-bit Legacy SSE version: The first source operand and destination register are XMM registers. The second\r\nsource operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding ZMM\r\ndestination register remain unchanged.\r\nVEX.128 and EVEX.128 encoded versions: The first source operand and destination register are XMM registers. The\r\nsecond source operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corre-\r\nsponding ZMM register are zeroed.\r\nVEX.256 and EVEX.256 encoded versions: The first source operand and destination register are YMM registers. The\r\nsecond source operand is an YMM register or a 256-bit memory location. Bits (MAX_VL-1:256) of the corre-\r\nsponding ZMM register are zeroed.\r\nEVEX.512 encoded version: The first source operand and destination register are ZMM registers. The second\r\nsource operand is a ZMM register or a 512-bit memory location.\r\n\r\n\r\n\r\n SRC X7 X6 X5 X4 X3 X2 X1 X0\r\n\r\n\r\n DEST Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0\r\n\r\n\r\n TEMP ABS(X7:Y7) ABS(X6:Y6) ABS(X5:Y5) ABS(X4:Y4) ABS(X3:Y3) ABS(X2:Y2) ABS(X1:Y1) ABS(X0:Y0)\r\n\r\n\r\n\r\n\r\n DEST 00H 00H 00H 00H 00H 00H SUM(TEMP7...TEMP0)\r\n\r\n\r\n\r\n Figure 4-14. PSADBW Instruction Operation Using 64-bit Operands\r\n\r\n\r\nOperation\r\nVPSADBW (EVEX encoded versions)\r\nVL = 128, 256, 512\r\nTEMP0 <- ABS(SRC1[7:0] - SRC2[7:0])\r\n(* Repeat operation for bytes 1 through 15 *)\r\nTEMP15 <- ABS(SRC1[127:120] - SRC2[127:120])\r\nDEST[15:0] <-SUM(TEMP0:TEMP7)\r\nDEST[63:16] <- 000000000000H\r\n\r\n\r\n\r\nDEST[79:64] <- SUM(TEMP8:TEMP15)\r\nDEST[127:80] <- 00000000000H\r\n\r\nIF VL >= 256\r\n (* Repeat operation for bytes 16 through 31*)\r\n TEMP31 <- ABS(SRC1[255:248] - SRC2[255:248])\r\n DEST[143:128] <-SUM(TEMP16:TEMP23)\r\n DEST[191:144] <- 000000000000H\r\n DEST[207:192] <- SUM(TEMP24:TEMP31)\r\n DEST[223:208] <- 00000000000H\r\nFI;\r\nIF VL >= 512\r\n(* Repeat operation for bytes 32 through 63*)\r\n TEMP63 <- ABS(SRC1[511:504] - SRC2[511:504])\r\n DEST[271:256] <-SUM(TEMP0:TEMP7)\r\n DEST[319:272] <- 000000000000H\r\n DEST[335:320] <- SUM(TEMP8:TEMP15)\r\n DEST[383:336] <- 00000000000H\r\n DEST[399:384] <-SUM(TEMP16:TEMP23)\r\n DEST[447:400] <- 000000000000H\r\n DEST[463:448] <- SUM(TEMP24:TEMP31)\r\n DEST[511:464] <- 00000000000H\r\nFI;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPSADBW (VEX.256 encoded version)\r\nTEMP0 <- ABS(SRC1[7:0] - SRC2[7:0])\r\n(* Repeat operation for bytes 2 through 30*)\r\nTEMP31 <- ABS(SRC1[255:248] - SRC2[255:248])\r\nDEST[15:0] <-SUM(TEMP0:TEMP7)\r\nDEST[63:16] <- 000000000000H\r\nDEST[79:64] <- SUM(TEMP8:TEMP15)\r\nDEST[127:80] <- 00000000000H\r\nDEST[143:128] <-SUM(TEMP16:TEMP23)\r\nDEST[191:144] <- 000000000000H\r\nDEST[207:192] <- SUM(TEMP24:TEMP31)\r\nDEST[223:208] <- 00000000000H\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVPSADBW (VEX.128 encoded version)\r\nTEMP0 <- ABS(SRC1[7:0] - SRC2[7:0])\r\n(* Repeat operation for bytes 2 through 14 *)\r\nTEMP15 <- ABS(SRC1[127:120] - SRC2[127:120])\r\nDEST[15:0] <-SUM(TEMP0:TEMP7)\r\nDEST[63:16] <- 000000000000H\r\nDEST[79:64] <- SUM(TEMP8:TEMP15)\r\nDEST[127:80] <- 00000000000H\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nPSADBW (128-bit Legacy SSE version)\r\nTEMP0 <- ABS(DEST[7:0] - SRC[7:0])\r\n(* Repeat operation for bytes 2 through 14 *)\r\nTEMP15 <- ABS(DEST[127:120] - SRC[127:120])\r\nDEST[15:0] <-SUM(TEMP0:TEMP7)\r\nDEST[63:16] <- 000000000000H\r\nDEST[79:64] <- SUM(TEMP8:TEMP15)\r\nDEST[127:80] <- 00000000000\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nPSADBW (64-bit operand)\r\nTEMP0 <- ABS(DEST[7:0] - SRC[7:0])\r\n(* Repeat operation for bytes 2 through 6 *)\r\nTEMP7 <- ABS(DEST[63:56] - SRC[63:56])\r\nDEST[15:0] <-SUM(TEMP0:TEMP7)\r\nDEST[63:16] <- 000000000000H\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPSADBW __m512i _mm512_sad_epu8( __m512i a, __m512i b)\r\nPSADBW:__m64 _mm_sad_pu8(__m64 a,__m64 b)\r\n(V)PSADBW:__m128i _mm_sad_epu8(__m128i a, __m128i b)\r\nVPSADBW:__m256i _mm256_sad_epu8( __m256i a, __m256i b)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4NF.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PSADBW"
},
{
"description": "PSHUFB - Packed Shuffle Bytes\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F 38 00 /r1 RM V/V SSSE3 Shuffle bytes in mm1 according to contents of\r\nPSHUFB mm1, mm2/m64 mm2/m64.\r\n\r\n66 0F 38 00 /r RM V/V SSSE3 Shuffle bytes in xmm1 according to contents of\r\nPSHUFB xmm1, xmm2/m128 xmm2/m128.\r\n\r\nVEX.NDS.128.66.0F38.WIG 00 /r RVM V/V AVX Shuffle bytes in xmm2 according to contents of\r\nVPSHUFB xmm1, xmm2, xmm3/m128 xmm3/m128.\r\n\r\nVEX.NDS.256.66.0F38.WIG 00 /r RVM V/V AVX2 Shuffle bytes in ymm2 according to contents of\r\nVPSHUFB ymm1, ymm2, ymm3/m256 ymm3/m256.\r\n\r\nEVEX.NDS.128.66.0F38.WIG 00 /r FVM V/V AVX512VL Shuffle bytes in xmm2 according to contents of\r\nVPSHUFB xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512BW xmm3/m128 under write mask k1.\r\nEVEX.NDS.256.66.0F38.WIG 00 /r FVM V/V AVX512VL Shuffle bytes in ymm2 according to contents of\r\nVPSHUFB ymm1 {k1}{z}, ymm2, ymm3/m256 AVX512BW ymm3/m256 under write mask k1.\r\nEVEX.NDS.512.66.0F38.WIG 00 /r FVM V/V AVX512BW Shuffle bytes in zmm2 according to contents of\r\nVPSHUFB zmm1 {k1}{z}, zmm2, zmm3/m512 zmm3/m512 under write mask k1.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nPSHUFB performs in-place shuffles of bytes in the destination operand (the first operand) according to the shuffle\r\ncontrol mask in the source operand (the second operand). The instruction permutes the data in the destination\r\noperand, leaving the shuffle mask unaffected. If the most significant bit (bit[7]) of each byte of the shuffle control\r\nmask is set, then constant zero is written in the result byte. Each byte in the shuffle control mask forms an index\r\nto permute the corresponding byte in the destination operand. The value of each index is the least significant 4 bits\r\n(128-bit operation) or 3 bits (64-bit operation) of the shuffle control byte. When the source operand is a 128-bit\r\nmemory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will\r\nbe generated.\r\nIn 64-bit mode and not encoded with VEX/EVEX, use the REX prefix to access XMM8-XMM15 registers.\r\nLegacy SSE version 64-bit operand: Both operands can be MMX registers.\r\n128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (VLMAX-\r\n1:128) of the corresponding YMM destination register remain unchanged.\r\nVEX.128 encoded version: The destination operand is the first operand, the first source operand is the second\r\noperand, the second source operand is the third operand. Bits (VLMAX-1:128) of the destination YMM register are\r\nzeroed.\r\nVEX.256 encoded version: Bits (255:128) of the destination YMM register stores the 16-byte shuffle result of the\r\nupper 16 bytes of the first source operand, using the upper 16-bytes of the second source operand as control mask.\r\n\r\n\r\n\r\n\r\nThe value of each index is for the high 128-bit lane is the least significant 4 bits of the respective shuffle control\r\nbyte. The index value selects a source data element within each 128-bit lane.\r\nEVEX encoded version: The second source operand is an ZMM/YMM/XMM register or an 512/256/128-bit memory\r\nlocation. The first source operand and destination operands are ZMM/YMM/XMM registers. The destination is condi-\r\ntionally updated with writemask k1.\r\nEVEX and VEX encoded version: Four/two in-lane 128-bit shuffles.\r\n\r\nOperation\r\nPSHUFB (with 64 bit operands)\r\nTEMP <- DEST\r\nfor i = 0 to 7 {\r\n if (SRC[(i * 8)+7] = 1 ) then\r\n DEST[(i*8)+7...(i*8)+0] <- 0;\r\n else\r\n index[2..0] <- SRC[(i*8)+2 .. (i*8)+0];\r\n DEST[(i*8)+7...(i*8)+0] <- TEMP[(index*8+7)..(index*8+0)];\r\n endif;\r\n}\r\n\r\nPSHUFB (with 128 bit operands)\r\nTEMP <- DEST\r\nfor i = 0 to 15 {\r\n if (SRC[(i * 8)+7] = 1 ) then\r\n DEST[(i*8)+7..(i*8)+0] <- 0;\r\n else\r\n index[3..0] <- SRC[(i*8)+3 .. (i*8)+0];\r\n DEST[(i*8)+7..(i*8)+0] <- TEMP[(index*8+7)..(index*8+0)];\r\n endif\r\n}\r\n\r\nVPSHUFB (VEX.128 encoded version)\r\nfor i = 0 to 15 {\r\n if (SRC2[(i * 8)+7] = 1) then\r\n DEST[(i*8)+7..(i*8)+0] <- 0;\r\n else\r\n index[3..0] <- SRC2[(i*8)+3 .. (i*8)+0];\r\n DEST[(i*8)+7..(i*8)+0] <- SRC1[(index*8+7)..(index*8+0)];\r\n endif\r\n}\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPSHUFB (VEX.256 encoded version)\r\nfor i = 0 to 15 {\r\n if (SRC2[(i * 8)+7] == 1 ) then\r\n DEST[(i*8)+7..(i*8)+0] <- 0;\r\n else\r\n index[3..0] <- SRC2[(i*8)+3 .. (i*8)+0];\r\n DEST[(i*8)+7..(i*8)+0] <- SRC1[(index*8+7)..(index*8+0)];\r\n endif\r\n if (SRC2[128 + (i * 8)+7] == 1 ) then\r\n DEST[128 + (i*8)+7..(i*8)+0] <- 0;\r\n else\r\n index[3..0] <- SRC2[128 + (i*8)+3 .. (i*8)+0];\r\n DEST[128 + (i*8)+7..(i*8)+0] <- SRC1[128 + (index*8+7)..(index*8+0)];\r\n\r\n\r\n\r\n endif\r\n}\r\nVPSHUFB (EVEX encoded versions)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\njmask <- (KL-1) & ~0xF // 0x00, 0x10, 0x30 depending on the VL\r\nFOR j = 0 TO KL-1 // dest\r\n IF kl[ i ] or no_masking\r\n index <- src.byte[ j ];\r\n IF index & 0x80\r\n Dest.byte[ j ] <- 0;\r\n ELSE\r\n index <- (index & 0xF) + (j & jmask); // 16-element in-lane lookup\r\n Dest.byte[ j ] <- src.byte[ index ];\r\n ELSE if zeroing\r\n Dest.byte[ j ] <- 0;\r\nDEST[MAX_VL-1:VL] <- 0;\r\n\r\n\r\n\r\n\r\n MM2\r\n\r\n 07H 07H FFH 80H 01H 00H 00H 00H\r\n\r\n MM1\r\n\r\n 04H 01H 07H 03H 02H 02H FFH 01H\r\n\r\n\r\n\r\n MM1\r\n 04H 04H 00H 00H FFH 01H 01H 01H\r\n\r\n\r\n\r\n\r\n Figure 4-15. PSHUFB with 64-Bit Operands\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPSHUFB __m512i _mm512_shuffle_epi8(__m512i a, __m512i b);\r\nVPSHUFB __m512i _mm512_mask_shuffle_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);\r\nVPSHUFB __m512i _mm512_maskz_shuffle_epi8( __mmask64 k, __m512i a, __m512i b);\r\nVPSHUFB __m256i _mm256_mask_shuffle_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);\r\nVPSHUFB __m256i _mm256_maskz_shuffle_epi8( __mmask32 k, __m256i a, __m256i b);\r\nVPSHUFB __m128i _mm_mask_shuffle_epi8(__m128i s, __mmask16 k, __m128i a, __m128i b);\r\nVPSHUFB __m128i _mm_maskz_shuffle_epi8( __mmask16 k, __m128i a, __m128i b);\r\nPSHUFB: __m64 _mm_shuffle_pi8 (__m64 a, __m64 b)\r\n(V)PSHUFB: __m128i _mm_shuffle_epi8 (__m128i a, __m128i b)\r\nVPSHUFB:__m256i _mm256_shuffle_epi8(__m256i a, __m256i b)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\n\r\n\r\n\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4NF.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PSHUFB"
},
{
"description": "PSHUFD-Shuffle Packed Doublewords\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n66 0F 70 /r ib RMI V/V SSE2 Shuffle the doublewords in xmm2/m128 based on\r\nPSHUFD xmm1, xmm2/m128, imm8 the encoding in imm8 and store the result in xmm1.\r\n\r\nVEX.128.66.0F.WIG 70 /r ib RMI V/V AVX Shuffle the doublewords in xmm2/m128 based on\r\nVPSHUFD xmm1, xmm2/m128, imm8 the encoding in imm8 and store the result in xmm1.\r\n\r\nVEX.256.66.0F.WIG 70 /r ib RMI V/V AVX2 Shuffle the doublewords in ymm2/m256 based on\r\nVPSHUFD ymm1, ymm2/m256, imm8 the encoding in imm8 and store the result in ymm1.\r\n\r\nEVEX.128.66.0F.W0 70 /r ib FV V/V AVX512VL Shuffle the doublewords in xmm2/m128/m32bcst\r\nVPSHUFD xmm1 {k1}{z}, xmm2/m128/m32bcst, AVX512F based on the encoding in imm8 and store the result\r\nimm8 in xmm1 using writemask k1.\r\nEVEX.256.66.0F.W0 70 /r ib FV V/V AVX512VL Shuffle the doublewords in ymm2/m256/m32bcst\r\nVPSHUFD ymm1 {k1}{z}, ymm2/m256/m32bcst, AVX512F based on the encoding in imm8 and store the result\r\nimm8 in ymm1 using writemask k1.\r\nEVEX.512.66.0F.W0 70 /r ib FV V/V AVX512F Shuffle the doublewords in zmm2/m512/m32bcst\r\nVPSHUFD zmm1 {k1}{z}, zmm2/m512/m32bcst, based on the encoding in imm8 and store the result\r\nimm8 in zmm1 using writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (w) ModRM:r/m (r) imm8 NA\r\n FV ModRM:reg (w) ModRM:r/m (r) Imm8 NA\r\n\r\n\r\nDescription\r\nCopies doublewords from source operand (second operand) and inserts them in the destination operand (first\r\noperand) at the locations selected with the order operand (third operand). Figure 4-16 shows the operation of the\r\n256-bit VPSHUFD instruction and the encoding of the order operand. Each 2-bit field in the order operand selects\r\nthe contents of one doubleword location within a 128-bit lane and copy to the target element in the destination\r\noperand. For example, bits 0 and 1 of the order operand targets the first doubleword element in the low and high\r\n128-bit lane of the destination operand for 256-bit VPSHUFD. The encoded value of bits 1:0 of the order operand\r\n(see the field encoding in Figure 4-16) determines which doubleword element (from the respective 128-bit lane) of\r\nthe source operand will be copied to doubleword 0 of the destination operand.\r\nFor 128-bit operation, only the low 128-bit lane are operative. The source operand can be an XMM register or a\r\n128-bit memory location. The destination operand is an XMM register. The order operand is an 8-bit immediate.\r\nNote that this instruction permits a doubleword in the source operand to be copied to more than one doubleword\r\nlocation in the destination operand.\r\n\r\n\r\n\r\n\r\n\r\n SRC X7 X6 X5 X4 X3 X2 X1 X0\r\n\r\n\r\n\r\n\r\n DEST Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0\r\n\r\n\r\n Encoding 00B - X4\r\n of Fields in 01B - X5 Encoding 00B - X0\r\n ORDER of Fields in 01B - X1\r\n ORDER 10B - X6\r\n Operand 11B - X7 7 6 5 4 3 2 1 0\r\n ORDER 10B - X2\r\n Operand 11B - X3\r\n\r\n\r\n Figure 4-16. 256-bit VPSHUFD Instruction Operation\r\n\r\nThe source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM\r\nregister. The order operand is an 8-bit immediate. Note that this instruction permits a doubleword in the source\r\noperand to be copied to more than one doubleword location in the destination operand.\r\nIn 64-bit mode and not encoded in VEX/EVEX, using REX.R permits this instruction to access XMM8-XMM15.\r\n128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain\r\nunchanged.\r\nVEX.128 encoded version: The source operand can be an XMM register or a 128-bit memory location. The destina-\r\ntion operand is an XMM register. Bits (MAX_VL-1:128) of the corresponding ZMM register are zeroed.\r\nVEX.256 encoded version: The source operand can be an YMM register or a 256-bit memory location. The destina-\r\ntion operand is an YMM register. Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed. Bits (255-\r\n1:128) of the destination stores the shuffled results of the upper 16 bytes of the source operand using the imme-\r\ndiate byte as the order operand.\r\nEVEX encoded version: The source operand can be an ZMM/YMM/XMM register, a 512/256/128-bit memory loca-\r\ntion, or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a\r\nZMM/YMM/XMM register updated according to the writemask.\r\nEach 128-bit lane of the destination stores the shuffled results of the respective lane of the source operand using\r\nthe immediate byte as the order operand.\r\nNote: EVEX.vvvv and VEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\n\r\nOperation\r\nPSHUFD (128-bit Legacy SSE version)\r\nDEST[31:0] <- (SRC >> (ORDER[1:0] * 32))[31:0];\r\nDEST[63:32] <- (SRC >> (ORDER[3:2] * 32))[31:0];\r\nDEST[95:64] <- (SRC >> (ORDER[5:4] * 32))[31:0];\r\nDEST[127:96] <- (SRC >> (ORDER[7:6] * 32))[31:0];\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVPSHUFD (VEX.128 encoded version)\r\nDEST[31:0] <- (SRC >> (ORDER[1:0] * 32))[31:0];\r\nDEST[63:32] <- (SRC >> (ORDER[3:2] * 32))[31:0];\r\nDEST[95:64] <- (SRC >> (ORDER[5:4] * 32))[31:0];\r\nDEST[127:96] <- (SRC >> (ORDER[7:6] * 32))[31:0];\r\nDEST[VLMAX-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVPSHUFD (VEX.256 encoded version)\r\nDEST[31:0] <- (SRC[127:0] >> (ORDER[1:0] * 32))[31:0];\r\nDEST[63:32] <- (SRC[127:0] >> (ORDER[3:2] * 32))[31:0];\r\nDEST[95:64] <- (SRC[127:0] >> (ORDER[5:4] * 32))[31:0];\r\nDEST[127:96] <- (SRC[127:0] >> (ORDER[7:6] * 32))[31:0];\r\nDEST[159:128] <- (SRC[255:128] >> (ORDER[1:0] * 32))[31:0];\r\nDEST[191:160] <- (SRC[255:128] >> (ORDER[3:2] * 32))[31:0];\r\nDEST[223:192] <- (SRC[255:128] >> (ORDER[5:4] * 32))[31:0];\r\nDEST[255:224] <- (SRC[255:128] >> (ORDER[7:6] * 32))[31:0];\r\nDEST[VLMAX-1:256] <- 0\r\n\r\nVPSHUFD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF (EVEX.b = 1) AND (SRC *is memory*)\r\n THEN TMP_SRC[i+31:i] <- SRC[31:0]\r\n ELSE TMP_SRC[i+31:i] <- SRC[i+31:i]\r\n FI;\r\nENDFOR;\r\nIF VL >= 128\r\n TMP_DEST[31:0] <- (TMP_SRC[127:0] >> (ORDER[1:0] * 32))[31:0];\r\n TMP_DEST[63:32] <- (TMP_SRC[127:0] >> (ORDER[3:2] * 32))[31:0];\r\n TMP_DEST[95:64] <- (TMP_SRC[127:0] >> (ORDER[5:4] * 32))[31:0];\r\n TMP_DEST[127:96] <- (TMP_SRC[127:0] >> (ORDER[7:6] * 32))[31:0];\r\nFI;\r\nIF VL >= 256\r\n TMP_DEST[159:128] <- (TMP_SRC[255:128] >> (ORDER[1:0] * 32))[31:0];\r\n TMP_DEST[191:160] <- (TMP_SRC[255:128] >> (ORDER[3:2] * 32))[31:0];\r\n TMP_DEST[223:192] <- (TMP_SRC[255:128] >> (ORDER[5:4] * 32))[31:0];\r\n TMP_DEST[255:224] <- (TMP_SRC[255:128] >> (ORDER[7:6] * 32))[31:0];\r\nFI;\r\nIF VL >= 512\r\n TMP_DEST[287:256] <- (TMP_SRC[383:256] >> (ORDER[1:0] * 32))[31:0];\r\n TMP_DEST[319:288] <- (TMP_SRC[383:256] >> (ORDER[3:2] * 32))[31:0];\r\n TMP_DEST[351:320] <- (TMP_SRC[383:256] >> (ORDER[5:4] * 32))[31:0];\r\n TMP_DEST[383:352] <- (TMP_SRC[383:256] >> (ORDER[7:6] * 32))[31:0];\r\n TMP_DEST[415:384] <- (TMP_SRC[511:384] >> (ORDER[1:0] * 32))[31:0];\r\n TMP_DEST[447:416] <- (TMP_SRC[511:384] >> (ORDER[3:2] * 32))[31:0];\r\n TMP_DEST[479:448] <-(TMP_SRC[511:384] >> (ORDER[5:4] * 32))[31:0];\r\n TMP_DEST[511:480] <- (TMP_SRC[511:384] >> (ORDER[7:6] * 32))[31:0];\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_DEST[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\n\r\n\r\n\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPSHUFD __m512i _mm512_shuffle_epi32(__m512i a, int n );\r\nVPSHUFD __m512i _mm512_mask_shuffle_epi32(__m512i s, __mmask16 k, __m512i a, int n );\r\nVPSHUFD __m512i _mm512_maskz_shuffle_epi32( __mmask16 k, __m512i a, int n );\r\nVPSHUFD __m256i _mm256_mask_shuffle_epi32(__m256i s, __mmask8 k, __m256i a, int n );\r\nVPSHUFD __m256i _mm256_maskz_shuffle_epi32( __mmask8 k, __m256i a, int n );\r\nVPSHUFD __m128i _mm_mask_shuffle_epi32(__m128i s, __mmask8 k, __m128i a, int n );\r\nVPSHUFD __m128i _mm_maskz_shuffle_epi32( __mmask8 k, __m128i a, int n );\r\n(V)PSHUFD:__m128i _mm_shuffle_epi32(__m128i a, int n)\r\nVPSHUFD:__m256i _mm256_shuffle_epi32(__m256i a, const int n)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4NF.\r\n#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PSHUFD"
},
{
"description": "PSHUFHW-Shuffle Packed High Words\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\nF3 0F 70 /r ib RMI V/V SSE2 Shuffle the high words in xmm2/m128 based\r\nPSHUFHW xmm1, xmm2/m128, imm8 on the encoding in imm8 and store the result in\r\n xmm1.\r\nVEX.128.F3.0F.WIG 70 /r ib RMI V/V AVX Shuffle the high words in xmm2/m128 based\r\nVPSHUFHW xmm1, xmm2/m128, imm8 on the encoding in imm8 and store the result in\r\n xmm1.\r\nVEX.256.F3.0F.WIG 70 /r ib RMI V/V AVX2 Shuffle the high words in ymm2/m256 based\r\nVPSHUFHW ymm1, ymm2/m256, imm8 on the encoding in imm8 and store the result in\r\n ymm1.\r\nEVEX.128.F3.0F.WIG 70 /r ib FVM V/V AVX512VL Shuffle the high words in xmm2/m128 based\r\nVPSHUFHW xmm1 {k1}{z}, xmm2/m128, imm8 AVX512BW on the encoding in imm8 and store the result in\r\n xmm1 under write mask k1.\r\nEVEX.256.F3.0F.WIG 70 /r ib FVM V/V AVX512VL Shuffle the high words in ymm2/m256 based\r\nVPSHUFHW ymm1 {k1}{z}, ymm2/m256, imm8 AVX512BW on the encoding in imm8 and store the result in\r\n ymm1 under write mask k1.\r\nEVEX.512.F3.0F.WIG 70 /r ib FVM V/V AVX512BW Shuffle the high words in zmm2/m512 based\r\nVPSHUFHW zmm1 {k1}{z}, zmm2/m512, imm8 on the encoding in imm8 and store the result in\r\n zmm1 under write mask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (w) ModRM:r/m (r) imm8 NA\r\n FVM ModRM:reg (w) ModRM:r/m (r) Imm8 NA\r\n\r\n\r\nDescription\r\nCopies words from the high quadword of a 128-bit lane of the source operand and inserts them in the high quad-\r\nword of the destination operand at word locations (of the respective lane) selected with the immediate operand.\r\nThis 256-bit operation is similar to the in-lane operation used by the 256-bit VPSHUFD instruction, which is illus-\r\ntrated in Figure 4-16. For 128-bit operation, only the low 128-bit lane is operative. Each 2-bit field in the immediate\r\noperand selects the contents of one word location in the high quadword of the destination operand. The binary\r\nencodings of the immediate operand fields select words (0, 1, 2 or 3, 4) from the high quadword of the source\r\noperand to be copied to the destination operand. The low quadword of the source operand is copied to the low\r\nquadword of the destination operand, for each 128-bit lane.\r\nNote that this instruction permits a word in the high quadword of the source operand to be copied to more than one\r\nword location in the high quadword of the destination operand.\r\nIn 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to\r\naccess additional registers (XMM8-XMM15).\r\n128-bit Legacy SSE version: The destination operand is an XMM register. The source operand can be an XMM\r\nregister or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain\r\nunchanged.\r\nVEX.128 encoded version: The destination operand is an XMM register. The source operand can be an XMM register\r\nor a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are zeroed. VEX.vvvv is\r\nreserved and must be 1111b, VEX.L must be 0, otherwise the instruction will #UD.\r\nVEX.256 encoded version: The destination operand is an YMM register. The source operand can be an YMM register\r\nor a 256-bit memory location.\r\n\r\n\r\n\r\n\r\n\r\nEVEX encoded version: The destination operand is a ZMM/YMM/XMM registers. The source operand can be a\r\nZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination is updated according to the\r\nwritemask.\r\nNote: In VEX encoded versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\nOperation\r\nPSHUFHW (128-bit Legacy SSE version)\r\nDEST[63:0] <- SRC[63:0]\r\nDEST[79:64] <- (SRC >> (imm[1:0] *16))[79:64]\r\nDEST[95:80] <- (SRC >> (imm[3:2] * 16))[79:64]\r\nDEST[111:96] <- (SRC >> (imm[5:4] * 16))[79:64]\r\nDEST[127:112] <- (SRC >> (imm[7:6] * 16))[79:64]\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVPSHUFHW (VEX.128 encoded version)\r\nDEST[63:0] <- SRC1[63:0]\r\nDEST[79:64] <- (SRC1 >> (imm[1:0] *16))[79:64]\r\nDEST[95:80] <- (SRC1 >> (imm[3:2] * 16))[79:64]\r\nDEST[111:96] <- (SRC1 >> (imm[5:4] * 16))[79:64]\r\nDEST[127:112] <- (SRC1 >> (imm[7:6] * 16))[79:64]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPSHUFHW (VEX.256 encoded version)\r\nDEST[63:0] <- SRC1[63:0]\r\nDEST[79:64] <- (SRC1 >> (imm[1:0] *16))[79:64]\r\nDEST[95:80] <- (SRC1 >> (imm[3:2] * 16))[79:64]\r\nDEST[111:96] <- (SRC1 >> (imm[5:4] * 16))[79:64]\r\nDEST[127:112] <- (SRC1 >> (imm[7:6] * 16))[79:64]\r\nDEST[191:128] <- SRC1[191:128]\r\nDEST[207192] <- (SRC1 >> (imm[1:0] *16))[207:192]\r\nDEST[223:208] <- (SRC1 >> (imm[3:2] * 16))[207:192]\r\nDEST[239:224] <- (SRC1 >> (imm[5:4] * 16))[207:192]\r\nDEST[255:240] <- (SRC1 >> (imm[7:6] * 16))[207:192]\r\nDEST[VLMAX-1:256] <- 0\r\n\r\nVPSHUFHW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nIF VL >= 128\r\n TMP_DEST[63:0] <- SRC1[63:0]\r\n TMP_DEST[79:64] <- (SRC1 >> (imm[1:0] *16))[79:64]\r\n TMP_DEST[95:80] <- (SRC1 >> (imm[3:2] * 16))[79:64]\r\n TMP_DEST[111:96] <- (SRC1 >> (imm[5:4] * 16))[79:64]\r\n TMP_DEST[127:112] <- (SRC1 >> (imm[7:6] * 16))[79:64]\r\nFI;\r\nIF VL >= 256\r\n TMP_DEST[191:128] <- SRC1[191:128]\r\n TMP_DEST[207:192] <- (SRC1 >> (imm[1:0] *16))[207:192]\r\n TMP_DEST[223:208] <- (SRC1 >> (imm[3:2] * 16))[207:192]\r\n TMP_DEST[239:224] <- (SRC1 >> (imm[5:4] * 16))[207:192]\r\n TMP_DEST[255:240] <- (SRC1 >> (imm[7:6] * 16))[207:192]\r\nFI;\r\nIF VL >= 512\r\n TMP_DEST[319:256] <- SRC1[319:256]\r\n TMP_DEST[335:320] <- (SRC1 >> (imm[1:0] *16))[335:320]\r\n\r\n\r\n\r\n TMP_DEST[351:336] <- (SRC1 >> (imm[3:2] * 16))[335:320]\r\n TMP_DEST[367:352] <- (SRC1 >> (imm[5:4] * 16))[335:320]\r\n TMP_DEST[383:368] <- (SRC1 >> (imm[7:6] * 16))[335:320]\r\n TMP_DEST[447:384] <- SRC1[447:384]\r\n TMP_DEST[463:448] <- (SRC1 >> (imm[1:0] *16))[463:448]\r\n TMP_DEST[479:464] <- (SRC1 >> (imm[3:2] * 16))[463:448]\r\n TMP_DEST[495:480] <- (SRC1 >> (imm[5:4] * 16))[463:448]\r\n TMP_DEST[511:496] <- (SRC1 >> (imm[7:6] * 16))[463:448]\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- TMP_DEST[i+15:i];\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPSHUFHW __m512i _mm512_shufflehi_epi16(__m512i a, int n);\r\nVPSHUFHW __m512i _mm512_mask_shufflehi_epi16(__m512i s, __mmask16 k, __m512i a, int n );\r\nVPSHUFHW __m512i _mm512_maskz_shufflehi_epi16( __mmask16 k, __m512i a, int n );\r\nVPSHUFHW __m256i _mm256_mask_shufflehi_epi16(__m256i s, __mmask8 k, __m256i a, int n );\r\nVPSHUFHW __m256i _mm256_maskz_shufflehi_epi16( __mmask8 k, __m256i a, int n );\r\nVPSHUFHW __m128i _mm_mask_shufflehi_epi16(__m128i s, __mmask8 k, __m128i a, int n );\r\nVPSHUFHW __m128i _mm_maskz_shufflehi_epi16( __mmask8 k, __m128i a, int n );\r\n(V)PSHUFHW:__m128i _mm_shufflehi_epi16(__m128i a, int n)\r\nVPSHUFHW:__m256i _mm256_shufflehi_epi16(__m256i a, const int n)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4;\r\nEVEX-encoded instruction, see Exceptions Type E4NF.nb\r\n#UD If VEX.vvvv != 1111B, or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PSHUFHW"
},
{
"description": "PSHUFLW-Shuffle Packed Low Words\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\nF2 0F 70 /r ib RMI V/V SSE2 Shuffle the low words in xmm2/m128 based on\r\nPSHUFLW xmm1, xmm2/m128, imm8 the encoding in imm8 and store the result in\r\n xmm1.\r\nVEX.128.F2.0F.WIG 70 /r ib RMI V/V AVX Shuffle the low words in xmm2/m128 based on\r\nVPSHUFLW xmm1, xmm2/m128, imm8 the encoding in imm8 and store the result in\r\n xmm1.\r\nVEX.256.F2.0F.WIG 70 /r ib RMI V/V AVX2 Shuffle the low words in ymm2/m256 based on\r\nVPSHUFLW ymm1, ymm2/m256, imm8 the encoding in imm8 and store the result in\r\n ymm1.\r\nEVEX.128.F2.0F.WIG 70 /r ib FVM V/V AVX512VL Shuffle the low words in xmm2/m128 based on\r\nVPSHUFLW xmm1 {k1}{z}, xmm2/m128, imm8 AVX512BW the encoding in imm8 and store the result in\r\n xmm1 under write mask k1.\r\nEVEX.256.F2.0F.WIG 70 /r ib FVM V/V AVX512VL Shuffle the low words in ymm2/m256 based on\r\nVPSHUFLW ymm1 {k1}{z}, ymm2/m256, imm8 AVX512BW the encoding in imm8 and store the result in\r\n ymm1 under write mask k1.\r\nEVEX.512.F2.0F.WIG 70 /r ib FVM V/V AVX512BW Shuffle the low words in zmm2/m512 based on\r\nVPSHUFLW zmm1 {k1}{z}, zmm2/m512, imm8 the encoding in imm8 and store the result in\r\n zmm1 under write mask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (w) ModRM:r/m (r) imm8 NA\r\n FVM ModRM:reg (w) ModRM:r/m (r) Imm8 NA\r\n\r\n\r\nDescription\r\nCopies words from the low quadword of a 128-bit lane of the source operand and inserts them in the low quadword\r\nof the destination operand at word locations (of the respective lane) selected with the immediate operand. The\r\n256-bit operation is similar to the in-lane operation used by the 256-bit VPSHUFD instruction, which is illustrated\r\nin Figure 4-16. For 128-bit operation, only the low 128-bit lane is operative. Each 2-bit field in the immediate\r\noperand selects the contents of one word location in the low quadword of the destination operand. The binary\r\nencodings of the immediate operand fields select words (0, 1, 2 or 3) from the low quadword of the source operand\r\nto be copied to the destination operand. The high quadword of the source operand is copied to the high quadword\r\nof the destination operand, for each 128-bit lane.\r\nNote that this instruction permits a word in the low quadword of the source operand to be copied to more than one\r\nword location in the low quadword of the destination operand.\r\nIn 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to\r\naccess additional registers (XMM8-XMM15).\r\n128-bit Legacy SSE version: The destination operand is an XMM register. The source operand can be an XMM\r\nregister or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain\r\nunchanged.\r\nVEX.128 encoded version: The destination operand is an XMM register. The source operand can be an XMM register\r\nor a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are zeroed.\r\nVEX.256 encoded version: The destination operand is an YMM register. The source operand can be an YMM register\r\nor a 256-bit memory location.\r\nEVEX encoded version: The destination operand is a ZMM/YMM/XMM registers. The source operand can be a\r\nZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination is updated according to the\r\nwritemask.\r\n\r\n\r\nNote: In VEX encoded versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\nOperation\r\nPSHUFLW (128-bit Legacy SSE version)\r\nDEST[15:0] <- (SRC >> (imm[1:0] *16))[15:0]\r\nDEST[31:16] <- (SRC >> (imm[3:2] * 16))[15:0]\r\nDEST[47:32] <- (SRC >> (imm[5:4] * 16))[15:0]\r\nDEST[63:48] <- (SRC >> (imm[7:6] * 16))[15:0]\r\nDEST[127:64] <- SRC[127:64]\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVPSHUFLW (VEX.128 encoded version)\r\nDEST[15:0] <- (SRC1 >> (imm[1:0] *16))[15:0]\r\nDEST[31:16] <- (SRC1 >> (imm[3:2] * 16))[15:0]\r\nDEST[47:32] <- (SRC1 >> (imm[5:4] * 16))[15:0]\r\nDEST[63:48] <- (SRC1 >> (imm[7:6] * 16))[15:0]\r\nDEST[127:64] <- SRC[127:64]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPSHUFLW (VEX.256 encoded version)\r\nDEST[15:0] <- (SRC1 >> (imm[1:0] *16))[15:0]\r\nDEST[31:16] <- (SRC1 >> (imm[3:2] * 16))[15:0]\r\nDEST[47:32] <- (SRC1 >> (imm[5:4] * 16))[15:0]\r\nDEST[63:48] <- (SRC1 >> (imm[7:6] * 16))[15:0]\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[143:128] <- (SRC1 >> (imm[1:0] *16))[143:128]\r\nDEST[159:144] <- (SRC1 >> (imm[3:2] * 16))[143:128]\r\nDEST[175:160] <- (SRC1 >> (imm[5:4] * 16))[143:128]\r\nDEST[191:176] <- (SRC1 >> (imm[7:6] * 16))[143:128]\r\nDEST[255:192] <- SRC1[255:192]\r\nDEST[VLMAX-1:256] <- 0\r\n\r\nVPSHUFLW (EVEX.U1.512 encoded version)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nIF VL >= 128\r\n TMP_DEST[15:0] <- (SRC1 >> (imm[1:0] *16))[15:0]\r\n TMP_DEST[31:16] <- (SRC1 >> (imm[3:2] * 16))[15:0]\r\n TMP_DEST[47:32] <- (SRC1 >> (imm[5:4] * 16))[15:0]\r\n TMP_DEST[63:48] <- (SRC1 >> (imm[7:6] * 16))[15:0]\r\n TMP_DEST[127:64] <- SRC1[127:64]\r\nFI;\r\nIF VL >= 256\r\n TMP_DEST[143:128] <- (SRC1 >> (imm[1:0] *16))[143:128]\r\n TMP_DEST[159:144] <- (SRC1 >> (imm[3:2] * 16))[143:128]\r\n TMP_DEST[175:160] <- (SRC1 >> (imm[5:4] * 16))[143:128]\r\n TMP_DEST[191:176] <- (SRC1 >> (imm[7:6] * 16))[143:128]\r\n TMP_DEST[255:192] <- SRC1[255:192]\r\nFI;\r\nIF VL >= 512\r\n TMP_DEST[271:256] <- (SRC1 >> (imm[1:0] *16))[271:256]\r\n TMP_DEST[287:272] <- (SRC1 >> (imm[3:2] * 16))[271:256]\r\n TMP_DEST[303:288] <- (SRC1 >> (imm[5:4] * 16))[271:256]\r\n TMP_DEST[319:304] <- (SRC1 >> (imm[7:6] * 16))[271:256]\r\n TMP_DEST[383:320] <- SRC1[383:320]\r\n\r\n\r\n\r\n TMP_DEST[399:384] <- (SRC1 >> (imm[1:0] *16))[399:384]\r\n TMP_DEST[415:400] <- (SRC1 >> (imm[3:2] * 16))[399:384]\r\n TMP_DEST[431:416] <- (SRC1 >> (imm[5:4] * 16))[399:384]\r\n TMP_DEST[447:432] <- (SRC1 >> (imm[7:6] * 16))[399:384]\r\n TMP_DEST[511:448] <- SRC1[511:448]\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- TMP_DEST[i+15:i];\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPSHUFLW __m512i _mm512_shufflelo_epi16(__m512i a, int n);\r\nVPSHUFLW __m512i _mm512_mask_shufflelo_epi16(__m512i s, __mmask16 k, __m512i a, int n );\r\nVPSHUFLW __m512i _mm512_maskz_shufflelo_epi16( __mmask16 k, __m512i a, int n );\r\nVPSHUFLW __m256i _mm256_mask_shufflelo_epi16(__m256i s, __mmask8 k, __m256i a, int n );\r\nVPSHUFLW __m256i _mm256_maskz_shufflelo_epi16( __mmask8 k, __m256i a, int n );\r\nVPSHUFLW __m128i _mm_mask_shufflelo_epi16(__m128i s, __mmask8 k, __m128i a, int n );\r\nVPSHUFLW __m128i _mm_maskz_shufflelo_epi16( __mmask8 k, __m128i a, int n );\r\n(V)PSHUFLW:__m128i _mm_shufflelo_epi16(__m128i a, int n)\r\nVPSHUFLW:__m256i _mm256_shufflelo_epi16(__m256i a, const int n)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4;\r\nEVEX-encoded instruction, see Exceptions Type E4NF.nb\r\n#UD If VEX.vvvv != 1111B, or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PSHUFLW"
},
{
"description": "PSHUFW-Shuffle Packed Words\r\nOpcode/ Op/ 64-Bit Compat/ Description\r\nInstruction En Mode Leg Mode\r\n0F 70 /r ib RMI Valid Valid Shuffle the words in mm2/m64 based on the\r\nPSHUFW mm1, mm2/m64, imm8 encoding in imm8 and store the result in mm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (w) ModRM:r/m (r) imm8 NA\r\n\r\n\r\nDescription\r\nCopies words from the source operand (second operand) and inserts them in the destination operand (first\r\noperand) at word locations selected with the order operand (third operand). This operation is similar to the opera-\r\ntion used by the PSHUFD instruction, which is illustrated in Figure 4-16. For the PSHUFW instruction, each 2-bit\r\nfield in the order operand selects the contents of one word location in the destination operand. The encodings of the\r\norder operand fields select words from the source operand to be copied to the destination operand.\r\nThe source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an\r\nMMX technology register. The order operand is an 8-bit immediate. Note that this instruction permits a word in the\r\nsource operand to be copied to more than one word location in the destination operand.\r\nIn 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers\r\n(XMM8-XMM15).\r\n\r\nOperation\r\nDEST[15:0] <- (SRC >> (ORDER[1:0] * 16))[15:0];\r\nDEST[31:16] <- (SRC >> (ORDER[3:2] * 16))[15:0];\r\nDEST[47:32] <- (SRC >> (ORDER[5:4] * 16))[15:0];\r\nDEST[63:48] <- (SRC >> (ORDER[7:6] * 16))[15:0];\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nPSHUFW: __m64 _mm_shuffle_pi16(__m64 a, int n)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nNumeric Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Table 22-7, \"Exception Conditions for SIMD/MMX Instructions with Memory Reference,\" in the Intel 64 and\r\nIA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PSHUFW"
},
{
"description": "PSIGNB/PSIGNW/PSIGND - Packed SIGN\r\n Opcode/ Op/ 64/32 bit CPUID Description\r\n Instruction En Mode Feature\r\n Support Flag\r\n 0F 38 08 /r1 RM V/V SSSE3 Negate/zero/preserve packed byte integers in\r\n PSIGNB mm1, mm2/m64 mm1 depending on the corresponding sign in\r\n mm2/m64.\r\n 66 0F 38 08 /r RM V/V SSSE3 Negate/zero/preserve packed byte integers in\r\n PSIGNB xmm1, xmm2/m128 xmm1 depending on the corresponding sign in\r\n xmm2/m128.\r\n 0F 38 09 /r1 RM V/V SSSE3 Negate/zero/preserve packed word integers\r\n PSIGNW mm1, mm2/m64 in mm1 depending on the corresponding sign\r\n in mm2/m128.\r\n 66 0F 38 09 /r RM V/V SSSE3 Negate/zero/preserve packed word integers\r\n PSIGNW xmm1, xmm2/m128 in xmm1 depending on the corresponding sign\r\n in xmm2/m128.\r\n 0F 38 0A /r1 RM V/V SSSE3 Negate/zero/preserve packed doubleword\r\n PSIGND mm1, mm2/m64 integers in mm1 depending on the\r\n corresponding sign in mm2/m128.\r\n 66 0F 38 0A /r RM V/V SSSE3 Negate/zero/preserve packed doubleword\r\n PSIGND xmm1, xmm2/m128 integers in xmm1 depending on the\r\n corresponding sign in xmm2/m128.\r\n VEX.NDS.128.66.0F38.WIG 08 /r RVM V/V AVX Negate/zero/preserve packed byte integers in\r\n VPSIGNB xmm1, xmm2, xmm3/m128 xmm2 depending on the corresponding sign in\r\n xmm3/m128.\r\n VEX.NDS.128.66.0F38.WIG 09 /r RVM V/V AVX Negate/zero/preserve packed word integers\r\n VPSIGNW xmm1, xmm2, xmm3/m128 in xmm2 depending on the corresponding sign\r\n in xmm3/m128.\r\n VEX.NDS.128.66.0F38.WIG 0A /r RVM V/V AVX Negate/zero/preserve packed doubleword\r\n VPSIGND xmm1, xmm2, xmm3/m128 integers in xmm2 depending on the\r\n corresponding sign in xmm3/m128.\r\n VEX.NDS.256.66.0F38.WIG 08 /r RVM V/V AVX2 Negate packed byte integers in ymm2 if the\r\n VPSIGNB ymm1, ymm2, ymm3/m256 corresponding sign in ymm3/m256 is less\r\n than zero.\r\n VEX.NDS.256.66.0F38.WIG 09 /r RVM V/V AVX2 Negate packed 16-bit integers in ymm2 if the\r\n VPSIGNW ymm1, ymm2, ymm3/m256 corresponding sign in ymm3/m256 is less\r\n than zero.\r\n VEX.NDS.256.66.0F38.WIG 0A /r RVM V/V AVX2 Negate packed doubleword integers in ymm2\r\n VPSIGND ymm1, ymm2, ymm3/m256 if the corresponding sign in ymm3/m256 is\r\n less than zero.\r\n NOTES:\r\n 1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\n Developer's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\n in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\n\r\n\r\n\r\nDescription\r\n(V)PSIGNB/(V)PSIGNW/(V)PSIGND negates each data element of the destination operand (the first operand) if the\r\nsigned integer value of the corresponding data element in the source operand (the second operand) is less than\r\nzero. If the signed integer value of a data element in the source operand is positive, the corresponding data\r\nelement in the destination operand is unchanged. If a data element in the source operand is zero, the corre-\r\nsponding data element in the destination operand is set to zero.\r\n(V)PSIGNB operates on signed bytes. (V)PSIGNW operates on 16-bit signed words. (V)PSIGND operates on signed\r\n32-bit integers. When the source operand is a 128bit memory operand, the operand must be aligned on a 16-byte\r\nboundary or a general-protection exception (#GP) will be generated.\r\nLegacy SSE instructions: Both operands can be MMX registers. In 64-bit mode, use the REX prefix to access addi-\r\ntional registers.\r\n128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destina-\r\ntion register remain unchanged.\r\nVEX.128 encoded version: The first source and destination operands are XMM registers. The second source\r\noperand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are\r\nzeroed. VEX.L must be 0, otherwise instructions will #UD.\r\nVEX.256 encoded version: The first source and destination operands are YMM registers. The second source\r\noperand is an YMM register or a 256-bit memory location.\r\n\r\nOperation\r\nPSIGNB (with 64 bit operands)\r\n IF (SRC[7:0] < 0 )\r\n DEST[7:0] <- Neg(DEST[7:0])\r\n ELSEIF (SRC[7:0] = 0 )\r\n DEST[7:0] <- 0\r\n ELSEIF (SRC[7:0] > 0 )\r\n DEST[7:0] <- DEST[7:0]\r\n Repeat operation for 2nd through 7th bytes\r\n\r\n IF (SRC[63:56] < 0 )\r\n DEST[63:56] <- Neg(DEST[63:56])\r\n ELSEIF (SRC[63:56] = 0 )\r\n DEST[63:56] <- 0\r\n ELSEIF (SRC[63:56] > 0 )\r\n DEST[63:56] <- DEST[63:56]\r\n\r\nPSIGNB (with 128 bit operands)\r\n IF (SRC[7:0] < 0 )\r\n DEST[7:0] <- Neg(DEST[7:0])\r\n ELSEIF (SRC[7:0] = 0 )\r\n DEST[7:0] <- 0\r\n ELSEIF (SRC[7:0] > 0 )\r\n DEST[7:0] <- DEST[7:0]\r\n Repeat operation for 2nd through 15th bytes\r\n IF (SRC[127:120] < 0 )\r\n DEST[127:120] <- Neg(DEST[127:120])\r\n ELSEIF (SRC[127:120] = 0 )\r\n DEST[127:120] <- 0\r\n ELSEIF (SRC[127:120] > 0 )\r\n DEST[127:120] <- DEST[127:120]\r\n\r\n\r\n\r\n\r\n\r\nVPSIGNB (VEX.128 encoded version)\r\nDEST[127:0] <-BYTE_SIGN(SRC1, SRC2)\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPSIGNB (VEX.256 encoded version)\r\nDEST[255:0] <-BYTE_SIGN_256b(SRC1, SRC2)\r\n\r\nPSIGNW (with 64 bit operands)\r\n IF (SRC[15:0] < 0 )\r\n DEST[15:0] <- Neg(DEST[15:0])\r\n ELSEIF (SRC[15:0] = 0 )\r\n DEST[15:0] <- 0\r\n ELSEIF (SRC[15:0] > 0 )\r\n DEST[15:0] <- DEST[15:0]\r\nRepeat operation for 2nd through 3rd words\r\n IF (SRC[63:48] < 0 )\r\n DEST[63:48] <- Neg(DEST[63:48])\r\n ELSEIF (SRC[63:48] = 0 )\r\n DEST[63:48] <- 0\r\n ELSEIF (SRC[63:48] > 0 )\r\n DEST[63:48] <- DEST[63:48]\r\n\r\nPSIGNW (with 128 bit operands)\r\n IF (SRC[15:0] < 0 )\r\n DEST[15:0] <- Neg(DEST[15:0])\r\n ELSEIF (SRC[15:0] = 0 )\r\n DEST[15:0] <- 0\r\n ELSEIF (SRC[15:0] > 0 )\r\n DEST[15:0] <- DEST[15:0]\r\n Repeat operation for 2nd through 7th words\r\n IF (SRC[127:112] < 0 )\r\n DEST[127:112] <- Neg(DEST[127:112])\r\n ELSEIF (SRC[127:112] = 0 )\r\n DEST[127:112] <- 0\r\n ELSEIF (SRC[127:112] > 0 )\r\n DEST[127:112] <- DEST[127:112]\r\n\r\nVPSIGNW (VEX.128 encoded version)\r\nDEST[127:0] <-WORD_SIGN(SRC1, SRC2)\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPSIGNW (VEX.256 encoded version)\r\nDEST[255:0] <-WORD_SIGN(SRC1, SRC2)\r\n\r\nPSIGND (with 64 bit operands)\r\n IF (SRC[31:0] < 0 )\r\n DEST[31:0] <- Neg(DEST[31:0])\r\n ELSEIF (SRC[31:0] = 0 )\r\n DEST[31:0] <- 0\r\n ELSEIF (SRC[31:0] > 0 )\r\n DEST[31:0] <- DEST[31:0]\r\n IF (SRC[63:32] < 0 )\r\n DEST[63:32] <- Neg(DEST[63:32])\r\n ELSEIF (SRC[63:32] = 0 )\r\n DEST[63:32] <- 0\r\n\r\n\r\n\r\n ELSEIF (SRC[63:32] > 0 )\r\n DEST[63:32] <- DEST[63:32]\r\n\r\nPSIGND (with 128 bit operands)\r\n IF (SRC[31:0] < 0 )\r\n DEST[31:0] <- Neg(DEST[31:0])\r\n ELSEIF (SRC[31:0] = 0 )\r\n DEST[31:0] <- 0\r\n ELSEIF (SRC[31:0] > 0 )\r\n DEST[31:0] <- DEST[31:0]\r\n Repeat operation for 2nd through 3rd double words\r\n IF (SRC[127:96] < 0 )\r\n DEST[127:96] <- Neg(DEST[127:96])\r\n ELSEIF (SRC[127:96] = 0 )\r\n DEST[127:96] <- 0\r\n ELSEIF (SRC[127:96] > 0 )\r\n DEST[127:96] <- DEST[127:96]\r\n\r\nVPSIGND (VEX.128 encoded version)\r\nDEST[127:0] <-DWORD_SIGN(SRC1, SRC2)\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPSIGND (VEX.256 encoded version)\r\nDEST[255:0] <-DWORD_SIGN(SRC1, SRC2)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nPSIGNB: __m64 _mm_sign_pi8 (__m64 a, __m64 b)\r\n(V)PSIGNB: __m128i _mm_sign_epi8 (__m128i a, __m128i b)\r\nVPSIGNB: __m256i _mm256_sign_epi8 (__m256i a, __m256i b)\r\nPSIGNW: __m64 _mm_sign_pi16 (__m64 a, __m64 b)\r\n(V)PSIGNW: __m128i _mm_sign_epi16 (__m128i a, __m128i b)\r\nVPSIGNW: __m256i _mm256_sign_epi16 (__m256i a, __m256i b)\r\nPSIGND: __m64 _mm_sign_pi32 (__m64 a, __m64 b)\r\n(V)PSIGND: __m128i _mm_sign_epi32 (__m128i a, __m128i b)\r\nVPSIGND: __m256i _mm256_sign_epi32 (__m256i a, __m256i b)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4; additionally\r\n#UD If VEX.L = 1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PSIGNB"
},
{
"description": "-R:PSIGNB",
"mnem": "PSIGND"
},
{
"description": "-R:PSIGNB",
"mnem": "PSIGNW"
},
{
"description": "-R:PSLLW",
"mnem": "PSLLD"
},
{
"description": "PSLLDQ-Shift Double Quadword Left Logical\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n66 0F 73 /7 ib MI V/V SSE2 Shift xmm1 left by imm8 bytes while shifting\r\nPSLLDQ xmm1, imm8 in 0s.\r\n\r\nVEX.NDD.128.66.0F.WIG 73 /7 ib VMI V/V AVX Shift xmm2 left by imm8 bytes while shifting\r\nVPSLLDQ xmm1, xmm2, imm8 in 0s and store result in xmm1.\r\n\r\nVEX.NDD.256.66.0F.WIG 73 /7 ib VMI V/V AVX2 Shift ymm2 left by imm8 bytes while shifting\r\nVPSLLDQ ymm1, ymm2, imm8 in 0s and store result in ymm1.\r\n\r\nEVEX.NDD.128.66.0F.WIG 73 /7 ib FVMI V/V AVX512VL Shift xmm2/m128 left by imm8 bytes while\r\nVPSLLDQ xmm1,xmm2/ m128, imm8 AVX512BW shifting in 0s and store result in xmm1.\r\nEVEX.NDD.256.66.0F.WIG 73 /7 ib FVMI V/V AVX512VL Shift ymm2/m256 left by imm8 bytes while\r\nVPSLLDQ ymm1, ymm2/m256, imm8 AVX512BW shifting in 0s and store result in ymm1.\r\nEVEX.NDD.512.66.0F.WIG 73 /7 ib FVMI V/V AVX512BW Shift zmm2/m512 left by imm8 bytes while\r\nVPSLLDQ zmm1, zmm2/m512, imm8 shifting in 0s and store result in zmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n MI ModRM:r/m (r, w) imm8 NA NA\r\n VMI VEX.vvvv (w) ModRM:r/m (r) imm8 NA\r\n FVMI EVEX.vvvv (w) ModRM:r/m (R) Imm8 NA\r\n\r\n\r\nDescription\r\nShifts the destination operand (first operand) to the left by the number of bytes specified in the count operand\r\n(second operand). The empty low-order bytes are cleared (set to all 0s). If the value specified by the count\r\noperand is greater than 15, the destination operand is set to all 0s. The count operand is an 8-bit immediate.\r\n128-bit Legacy SSE version: The source and destination operands are the same. Bits (VLMAX-1:128) of the corre-\r\nsponding YMM destination register remain unchanged.\r\nVEX.128 encoded version: The source and destination operands are XMM registers. Bits (VLMAX-1:128) of the\r\ndestination YMM register are zeroed.\r\nVEX.256 encoded version: The source operand is YMM register. The destination operand is an YMM register. Bits\r\n(MAX_VL-1:256) of the corresponding ZMM register are zeroed. The count operand applies to both the low and\r\nhigh 128-bit lanes.\r\nEVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location.\r\nThe destination operand is a ZMM/YMM/XMM register. The count operand applies to each 128-bit lanes.\r\n\r\nOperation\r\nVPSLLDQ (EVEX.U1.512 encoded version)\r\nTEMP <- COUNT\r\nIF (TEMP > 15) THEN TEMP <- 16; FI\r\nDEST[127:0] <- SRC[127:0] << (TEMP * 8)\r\nDEST[255:128] <- SRC[255:128] << (TEMP * 8)\r\nDEST[383:256] <- SRC[383:256] << (TEMP * 8)\r\nDEST[511:384] <- SRC[511:384] << (TEMP * 8)\r\nDEST[MAX_VL-1:512] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVPSLLDQ (VEX.256 and EVEX.256 encoded version)\r\nTEMP <- COUNT\r\nIF (TEMP > 15) THEN TEMP <- 16; FI\r\nDEST[127:0] <- SRC[127:0] << (TEMP * 8)\r\nDEST[255:128] <- SRC[255:128] << (TEMP * 8)\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVPSLLDQ (VEX.128 and EVEX.128 encoded version)\r\nTEMP <- COUNT\r\nIF (TEMP > 15) THEN TEMP <- 16; FI\r\nDEST <- SRC << (TEMP * 8)\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\nPSLLDQ(128-bit Legacy SSE version)\r\nTEMP <- COUNT\r\nIF (TEMP > 15) THEN TEMP <- 16; FI\r\nDEST <- DEST << (TEMP * 8)\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n(V)PSLLDQ:__m128i _mm_slli_si128 ( __m128i a, int imm)\r\nVPSLLDQ:__m256i _mm256_slli_si256 ( __m256i a, const int imm)\r\nVPSLLDQ __m512i _mm512_bslli_epi128 ( __m512i a, const int imm)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nNumeric Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 7.\r\nEVEX-encoded instruction, see Exceptions Type E4NF.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PSLLDQ"
},
{
"description": "-R:PSLLW",
"mnem": "PSLLQ"
},
{
"description": "PSLLW/PSLLD/PSLLQ-Shift Packed Data Left Logical\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F F1 /r1 RM V/V MMX Shift words in mm left mm/m64 while shifting in\r\nPSLLW mm, mm/m64 0s.\r\n\r\n66 0F F1 /r RM V/V SSE2 Shift words in xmm1 left by xmm2/m128 while\r\nPSLLW xmm1, xmm2/m128 shifting in 0s.\r\n\r\n0F 71 /6 ib MI V/V MMX Shift words in mm left by imm8 while shifting in\r\nPSLLW mm1, imm8 0s.\r\n\r\n66 0F 71 /6 ib MI V/V SSE2 Shift words in xmm1 left by imm8 while shifting\r\nPSLLW xmm1, imm8 in 0s.\r\n\r\n0F F2 /r1 RM V/V MMX Shift doublewords in mm left by mm/m64 while\r\nPSLLD mm, mm/m64 shifting in 0s.\r\n66 0F F2 /r RM V/V SSE2 Shift doublewords in xmm1 left by xmm2/m128\r\nPSLLD xmm1, xmm2/m128 while shifting in 0s.\r\n\r\n0F 72 /6 ib1 MI V/V MMX Shift doublewords in mm left by imm8 while\r\nPSLLD mm, imm8 shifting in 0s.\r\n\r\n66 0F 72 /6 ib MI V/V SSE2 Shift doublewords in xmm1 left by imm8 while\r\nPSLLD xmm1, imm8 shifting in 0s.\r\n\r\n0F F3 /r1 RM V/V MMX Shift quadword in mm left by mm/m64 while\r\nPSLLQ mm, mm/m64 shifting in 0s.\r\n\r\n66 0F F3 /r RM V/V SSE2 Shift quadwords in xmm1 left by xmm2/m128\r\nPSLLQ xmm1, xmm2/m128 while shifting in 0s.\r\n\r\n0F 73 /6 ib1 MI V/V MMX Shift quadword in mm left by imm8 while\r\nPSLLQ mm, imm8 shifting in 0s.\r\n\r\n66 0F 73 /6 ib MI V/V SSE2 Shift quadwords in xmm1 left by imm8 while\r\nPSLLQ xmm1, imm8 shifting in 0s.\r\n\r\nVEX.NDS.128.66.0F.WIG F1 /r RVM V/V AVX Shift words in xmm2 left by amount specified in\r\nVPSLLW xmm1, xmm2, xmm3/m128 xmm3/m128 while shifting in 0s.\r\n\r\nVEX.NDD.128.66.0F.WIG 71 /6 ib VMI V/V AVX Shift words in xmm2 left by imm8 while shifting\r\nVPSLLW xmm1, xmm2, imm8 in 0s.\r\n\r\nVEX.NDS.128.66.0F.WIG F2 /r RVM V/V AVX Shift doublewords in xmm2 left by amount\r\nVPSLLD xmm1, xmm2, xmm3/m128 specified in xmm3/m128 while shifting in 0s.\r\n\r\nVEX.NDD.128.66.0F.WIG 72 /6 ib VMI V/V AVX Shift doublewords in xmm2 left by imm8 while\r\nVPSLLD xmm1, xmm2, imm8 shifting in 0s.\r\n\r\nVEX.NDS.128.66.0F.WIG F3 /r RVM V/V AVX Shift quadwords in xmm2 left by amount\r\nVPSLLQ xmm1, xmm2, xmm3/m128 specified in xmm3/m128 while shifting in 0s.\r\n\r\nVEX.NDD.128.66.0F.WIG 73 /6 ib VMI V/V AVX Shift quadwords in xmm2 left by imm8 while\r\nVPSLLQ xmm1, xmm2, imm8 shifting in 0s.\r\n\r\nVEX.NDS.256.66.0F.WIG F1 /r RVM V/V AVX2 Shift words in ymm2 left by amount specified in\r\nVPSLLW ymm1, ymm2, xmm3/m128 xmm3/m128 while shifting in 0s.\r\n\r\nVEX.NDD.256.66.0F.WIG 71 /6 ib VMI V/V AVX2 Shift words in ymm2 left by imm8 while shifting\r\nVPSLLW ymm1, ymm2, imm8 in 0s.\r\n\r\n\r\n\r\n\r\n\r\nVEX.NDS.256.66.0F.WIG F2 /r RVM V/V AVX2 Shift doublewords in ymm2 left by amount\r\nVPSLLD ymm1, ymm2, xmm3/m128 specified in xmm3/m128 while shifting in 0s.\r\n\r\nVEX.NDD.256.66.0F.WIG 72 /6 ib VMI V/V AVX2 Shift doublewords in ymm2 left by imm8 while\r\nVPSLLD ymm1, ymm2, imm8 shifting in 0s.\r\n\r\nVEX.NDS.256.66.0F.WIG F3 /r RVM V/V AVX2 Shift quadwords in ymm2 left by amount\r\nVPSLLQ ymm1, ymm2, xmm3/m128 specified in xmm3/m128 while shifting in 0s.\r\n\r\nVEX.NDD.256.66.0F.WIG 73 /6 ib VMI V/V AVX2 Shift quadwords in ymm2 left by imm8 while\r\nVPSLLQ ymm1, ymm2, imm8 shifting in 0s.\r\n\r\nEVEX.NDS.128.66.0F.WIG F1 /r M128 V/V AVX512VL Shift words in xmm2 left by amount specified in\r\nVPSLLW xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512BW xmm3/m128 while shifting in 0s using\r\n writemask k1.\r\nEVEX.NDS.256.66.0F.WIG F1 /r M128 V/V AVX512VL Shift words in ymm2 left by amount specified in\r\nVPSLLW ymm1 {k1}{z}, ymm2, xmm3/m128 AVX512BW xmm3/m128 while shifting in 0s using\r\n writemask k1.\r\nEVEX.NDS.512.66.0F.WIG F1 /r M128 V/V AVX512BW Shift words in zmm2 left by amount specified in\r\nVPSLLW zmm1 {k1}{z}, zmm2, xmm3/m128 xmm3/m128 while shifting in 0s using\r\n writemask k1.\r\nEVEX.NDD.128.66.0F.WIG 71 /6 ib FVMI V/V AVX512VL Shift words in xmm2/m128 left by imm8 while\r\nVPSLLW xmm1 {k1}{z}, xmm2/m128, imm8 AVX512BW shifting in 0s using writemask k1.\r\nEVEX.NDD.256.66.0F.WIG 71 /6 ib FVMI V/V AVX512VL Shift words in ymm2/m256 left by imm8 while\r\nVPSLLW ymm1 {k1}{z}, ymm2/m256, imm8 AVX512BW shifting in 0s using writemask k1.\r\nEVEX.NDD.512.66.0F.WIG 71 /6 ib FVMI V/V AVX512BW Shift words in zmm2/m512 left by imm8 while\r\nVPSLLW zmm1 {k1}{z}, zmm2/m512, imm8 shifting in 0 using writemask k1.\r\nEVEX.NDS.128.66.0F.W0 F2 /r M128 V/V AVX512VL Shift doublewords in xmm2 left by amount\r\nVPSLLD xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512F specified in xmm3/m128 while shifting in 0s\r\n under writemask k1.\r\nEVEX.NDS.256.66.0F.W0 F2 /r M128 V/V AVX512VL Shift doublewords in ymm2 left by amount\r\nVPSLLD ymm1 {k1}{z}, ymm2, xmm3/m128 AVX512F specified in xmm3/m128 while shifting in 0s\r\n under writemask k1.\r\nEVEX.NDS.512.66.0F.W0 F2 /r M128 V/V AVX512F Shift doublewords in zmm2 left by amount\r\nVPSLLD zmm1 {k1}{z}, zmm2, xmm3/m128 specified in xmm3/m128 while shifting in 0s\r\n under writemask k1.\r\nEVEX.NDD.128.66.0F.W0 72 /6 ib FVI V/V AVX512VL Shift doublewords in xmm2/m128/m32bcst left\r\nVPSLLD xmm1 {k1}{z}, xmm2/m128/m32bcst, AVX512F by imm8 while shifting in 0s using writemask k1.\r\nimm8\r\nEVEX.NDD.256.66.0F.W0 72 /6 ib FVI V/V AVX512VL Shift doublewords in ymm2/m256/m32bcst left\r\nVPSLLD ymm1 {k1}{z}, ymm2/m256/m32bcst, AVX512F by imm8 while shifting in 0s using writemask k1.\r\nimm8\r\nEVEX.NDD.512.66.0F.W0 72 /6 ib FVI V/V AVX512F Shift doublewords in zmm2/m512/m32bcst left\r\nVPSLLD zmm1 {k1}{z}, zmm2/m512/m32bcst, by imm8 while shifting in 0s using writemask k1.\r\nimm8\r\nEVEX.NDS.128.66.0F.W1 F3 /r M128 V/V AVX512VL Shift quadwords in xmm2 left by amount\r\nVPSLLQ xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512F specified in xmm3/m128 while shifting in 0s\r\n using writemask k1.\r\nEVEX.NDS.256.66.0F.W1 F3 /r M128 V/V AVX512VL Shift quadwords in ymm2 left by amount\r\nVPSLLQ ymm1 {k1}{z}, ymm2, xmm3/m128 AVX512F specified in xmm3/m128 while shifting in 0s\r\n using writemask k1.\r\nEVEX.NDS.512.66.0F.W1 F3 /r M128 V/V AVX512F Shift quadwords in zmm2 left by amount\r\nVPSLLQ zmm1 {k1}{z}, zmm2, xmm3/m128 specified in xmm3/m128 while shifting in 0s\r\n using writemask k1.\r\n\r\n\r\n\r\n\r\nEVEX.NDD.128.66.0F.W1 73 /6 ib FVI V/V AVX512VL Shift quadwords in xmm2/m128/m64bcst left\r\nVPSLLQ xmm1 {k1}{z}, xmm2/m128/m64bcst, AVX512F by imm8 while shifting in 0s using writemask k1.\r\nimm8\r\nEVEX.NDD.256.66.0F.W1 73 /6 ib FVI V/V AVX512VL Shift quadwords in ymm2/m256/m64bcst left\r\nVPSLLQ ymm1 {k1}{z}, ymm2/m256/m64bcst, AVX512F by imm8 while shifting in 0s using writemask k1.\r\nimm8\r\nEVEX.NDD.512.66.0F.W1 73 /6 ib FVI V/V AVX512F Shift quadwords in zmm2/m512/m64bcst left\r\nVPSLLQ zmm1 {k1}{z}, zmm2/m512/m64bcst, by imm8 while shifting in 0s using writemask k1.\r\nimm8\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n MI ModRM:r/m (r, w) imm8 NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n VMI VEX.vvvv (w) ModRM:r/m (r) imm8 NA\r\n FVMI EVEX.vvvv (w) ModRM:r/m (R) Imm8 NA\r\n FVI EVEX.vvvv (w) ModRM:r/m (R) Imm8 NA\r\n M128 ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nShifts the bits in the individual data elements (words, doublewords, or quadword) in the destination operand (first\r\noperand) to the left by the number of bits specified in the count operand (second operand). As the bits in the data\r\nelements are shifted left, the empty low-order bits are cleared (set to 0). If the value specified by the count\r\noperand is greater than 15 (for words), 31 (for doublewords), or 63 (for a quadword), then the destination operand\r\nis set to all 0s. Figure 4-17 gives an example of shifting words in a 64-bit operand.\r\n\r\n\r\n Pre-Shift\r\n X3 X2 X1 X0\r\n DEST\r\n Shift Left\r\n with Zero\r\n Extension\r\n\r\n Post-Shift\r\n DEST X3 << COUNT X2 << COUNT X1 << COUNT X0 << COUNT\r\n\r\n Figure 4-17. PSLLW, PSLLD, and PSLLQ Instruction Operation Using 64-bit Operand\r\n\r\nThe (V)PSLLW instruction shifts each of the words in the destination operand to the left by the number of bits spec-\r\nified in the count operand; the (V)PSLLD instruction shifts each of the doublewords in the destination operand; and\r\nthe (V)PSLLQ instruction shifts the quadword (or quadwords) in the destination operand.\r\nIn 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to\r\naccess additional registers (XMM8-XMM15).\r\nLegacy SSE instructions 64-bit operand: The destination operand is an MMX technology register; the count\r\noperand can be either an MMX technology register or an 64-bit memory location.\r\n\r\n\r\n\r\n\r\n\r\n128-bit Legacy SSE version: The destination and first source operands are XMM registers. Bits (VLMAX-1:128) of\r\nthe corresponding YMM destination register remain unchanged. The count operand can be either an XMM register\r\nor a 128-bit memory location or an 8-bit immediate. If the count operand is a memory address, 128 bits are loaded\r\nbut the upper 64 bits are ignored.\r\nVEX.128 encoded version: The destination and first source operands are XMM registers. Bits (VLMAX-1:128) of the\r\ndestination YMM register are zeroed. The count operand can be either an XMM register or a 128-bit memory loca-\r\ntion or an 8-bit immediate. If the count operand is a memory address, 128 bits are loaded but the upper 64 bits are\r\nignored.\r\nVEX.256 encoded version: The destination operand is a YMM register. The source operand is a YMM register or a\r\nmemory location. The count operand can come either from an XMM register or a memory location or an 8-bit imme-\r\ndiate. Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed.\r\nEVEX encoded versions: The destination operand is a ZMM register updated according to the writemask. The count\r\noperand is either an 8-bit immediate (the immediate count version) or an 8-bit value from an XMM register or a\r\nmemory location (the variable count version). For the immediate count version, the source operand (the second\r\noperand) can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32/64-bit\r\nmemory location. For the variable count version, the first source operand (the second operand) is a ZMM register,\r\nthe second source operand (the third operand, 8-bit variable count) can be an XMM register or a memory location.\r\nNote: In VEX/EVEX encoded versions of shifts with an immediate count, vvvv of VEX/EVEX encode the destination\r\nregister, and VEX.B/EVEX.B + ModRM.r/m encodes the source register.\r\nNote: For shifts with an immediate count (VEX.128.66.0F 71-73 /6, or EVEX.128.66.0F 71-73 /6),\r\nVEX.vvvv/EVEX.vvvv encodes the destination register.\r\n\r\nOperation\r\nPSLLW (with 64-bit operand)\r\n IF (COUNT > 15)\r\n THEN\r\n DEST[64:0] <- 0000000000000000H;\r\n ELSE\r\n DEST[15:0] <- ZeroExtend(DEST[15:0] << COUNT);\r\n (* Repeat shift operation for 2nd and 3rd words *)\r\n DEST[63:48] <- ZeroExtend(DEST[63:48] << COUNT);\r\n FI;\r\n\r\nPSLLD (with 64-bit operand)\r\n IF (COUNT > 31)\r\n THEN\r\n DEST[64:0] <- 0000000000000000H;\r\n ELSE\r\n DEST[31:0] <- ZeroExtend(DEST[31:0] << COUNT);\r\n DEST[63:32] <- ZeroExtend(DEST[63:32] << COUNT);\r\n FI;\r\n\r\nPSLLQ (with 64-bit operand)\r\n IF (COUNT > 63)\r\n THEN\r\n DEST[64:0] <- 0000000000000000H;\r\n ELSE\r\n DEST <- ZeroExtend(DEST << COUNT);\r\n FI;\r\n\r\nLOGICAL_LEFT_SHIFT_WORDS(SRC, COUNT_SRC)\r\nCOUNT <-COUNT_SRC[63:0];\r\nIF (COUNT > 15)\r\nTHEN\r\n\r\n\r\n\r\n DEST[127:0] <-00000000000000000000000000000000H\r\nELSE\r\n DEST[15:0] <-ZeroExtend(SRC[15:0] << COUNT);\r\n (* Repeat shift operation for 2nd through 7th words *)\r\n DEST[127:112] <-ZeroExtend(SRC[127:112] << COUNT);\r\nFI;\r\n\r\nLOGICAL_LEFT_SHIFT_DWORDS1(SRC, COUNT_SRC)\r\nCOUNT <- COUNT_SRC[63:0];\r\nIF (COUNT > 31)\r\nTHEN\r\n DEST[31:0] <- 0\r\nELSE\r\n DEST[31:0] <- ZeroExtend(SRC[31:0] << COUNT);\r\nFI;\r\n\r\nLOGICAL_LEFT_SHIFT_DWORDS(SRC, COUNT_SRC)\r\nCOUNT <-COUNT_SRC[63:0];\r\nIF (COUNT > 31)\r\nTHEN\r\n DEST[127:0] <-00000000000000000000000000000000H\r\nELSE\r\n DEST[31:0] <-ZeroExtend(SRC[31:0] << COUNT);\r\n (* Repeat shift operation for 2nd through 3rd words *)\r\n DEST[127:96] <-ZeroExtend(SRC[127:96] << COUNT);\r\nFI;\r\n\r\nLOGICAL_LEFT_SHIFT_QWORDS1(SRC, COUNT_SRC)\r\nCOUNT <- COUNT_SRC[63:0];\r\nIF (COUNT > 63)\r\nTHEN\r\n DEST[63:0] <- 0\r\nELSE\r\n DEST[63:0] <- ZeroExtend(SRC[63:0] << COUNT);\r\nFI;\r\n\r\nLOGICAL_LEFT_SHIFT_QWORDS(SRC, COUNT_SRC)\r\nCOUNT <-COUNT_SRC[63:0];\r\nIF (COUNT > 63)\r\nTHEN\r\n DEST[127:0] <-00000000000000000000000000000000H\r\nELSE\r\n DEST[63:0] <-ZeroExtend(SRC[63:0] << COUNT);\r\n DEST[127:64] <-ZeroExtend(SRC[127:64] << COUNT);\r\nFI;\r\nLOGICAL_LEFT_SHIFT_WORDS_256b(SRC, COUNT_SRC)\r\nCOUNT <-COUNT_SRC[63:0];\r\nIF (COUNT > 15)\r\nTHEN\r\n DEST[127:0] <-00000000000000000000000000000000H\r\n DEST[255:128] <-00000000000000000000000000000000H\r\nELSE\r\n DEST[15:0] <-ZeroExtend(SRC[15:0] << COUNT);\r\n (* Repeat shift operation for 2nd through 15th words *)\r\n\r\n\r\n\r\n DEST[255:240] <-ZeroExtend(SRC[255:240] << COUNT);\r\nFI;\r\n\r\nLOGICAL_LEFT_SHIFT_DWORDS_256b(SRC, COUNT_SRC)\r\nCOUNT <-COUNT_SRC[63:0];\r\nIF (COUNT > 31)\r\nTHEN\r\n DEST[127:0] <-00000000000000000000000000000000H\r\n DEST[255:128] <-00000000000000000000000000000000H\r\nELSE\r\n DEST[31:0] <-ZeroExtend(SRC[31:0] << COUNT);\r\n (* Repeat shift operation for 2nd through 7th words *)\r\n DEST[255:224] <-ZeroExtend(SRC[255:224] << COUNT);\r\nFI;\r\n\r\nLOGICAL_LEFT_SHIFT_QWORDS_256b(SRC, COUNT_SRC)\r\nCOUNT <-COUNT_SRC[63:0];\r\nIF (COUNT > 63)\r\nTHEN\r\n DEST[127:0] <-00000000000000000000000000000000H\r\n DEST[255:128] <-00000000000000000000000000000000H\r\nELSE\r\n DEST[63:0] <-ZeroExtend(SRC[63:0] << COUNT);\r\n DEST[127:64] <-ZeroExtend(SRC[127:64] << COUNT)\r\n DEST[191:128] <-ZeroExtend(SRC[191:128] << COUNT);\r\n DEST[255:192] <-ZeroExtend(SRC[255:192] << COUNT);\r\nFI;\r\n\r\nVPSLLW (EVEX versions, xmm/m128)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nIF VL = 128\r\n TMP_DEST[127:0] <- LOGICAL_LEFT_SHIFT_WORDS_128b(SRC1[127:0], SRC2)\r\nFI;\r\nIF VL = 256\r\n TMP_DEST[255:0] <- LOGICAL_LEFT_SHIFT_WORDS_256b(SRC1[255:0], SRC2)\r\nFI;\r\nIF VL = 512\r\n TMP_DEST[255:0] <- LOGICAL_LEFT_SHIFT_WORDS_256b(SRC1[255:0], SRC2)\r\n TMP_DEST[511:256] <- LOGICAL_LEFT_SHIFT_WORDS_256b(SRC1[511:256], SRC2)\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- TMP_DEST[i+15:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] = 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\nVPSLLW (EVEX versions, imm8)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nIF VL = 128\r\n TMP_DEST[127:0] <- LOGICAL_LEFT_SHIFT_WORDS_128b(SRC1[127:0], imm8)\r\nFI;\r\nIF VL = 256\r\n TMP_DEST[255:0] <- LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], imm8)\r\nFI;\r\nIF VL = 512\r\n TMP_DEST[255:0] <- LOGICAL_LEFT_SHIFT_WORDS_256b(SRC1[255:0], imm8)\r\n TMP_DEST[511:256] <- LOGICAL_LEFT_SHIFT_WORDS_256b(SRC1[511:256], imm8)\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- TMP_DEST[i+15:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] = 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPSLLW (ymm, ymm, xmm/m128) - VEX.256 encoding\r\nDEST[255:0] <-LOGICAL_LEFT_SHIFT_WORDS_256b(SRC1, SRC2)\r\nDEST[MAX_VL-1:256] <-0;\r\n\r\nVPSLLW (ymm, imm8) - VEX.256 encoding\r\nDEST[255:0] <-LOGICAL_LEFT_SHIFT_WORD_256b(SRC1, imm8)\r\nDEST[MAX_VL-1:256] <-0;\r\n\r\nVPSLLW (xmm, xmm, xmm/m128) - VEX.128 encoding\r\nDEST[127:0] <-LOGICAL_LEFT_SHIFT_WORDS(SRC1, SRC2)\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVPSLLW (xmm, imm8) - VEX.128 encoding\r\nDEST[127:0] <-LOGICAL_LEFT_SHIFT_WORDS(SRC1, imm8)\r\nDEST[MAX_VL-1:128] <-0\r\n\r\n\r\n\r\n\r\n\r\nPSLLW (xmm, xmm, xmm/m128)\r\nDEST[127:0] <-LOGICAL_LEFT_SHIFT_WORDS(DEST, SRC)\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nPSLLW (xmm, imm8)\r\nDEST[127:0] <-LOGICAL_LEFT_SHIFT_WORDS(DEST, imm8)\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVPSLLD (EVEX versions, imm8)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC1 *is memory*)\r\n THEN DEST[i+31:i] <- LOGICAL_LEFT_SHIFT_DWORDS1(SRC1[31:0], imm8)\r\n ELSE DEST[i+31:i] <- LOGICAL_LEFT_SHIFT_DWORDS1(SRC1[i+31:i], imm8)\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPSLLD (EVEX versions, xmm/m128)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF VL = 128\r\n TMP_DEST[127:0] <- LOGICAL_LEFT_SHIFT_DWORDS_128b(SRC1[127:0], SRC2)\r\nFI;\r\nIF VL = 256\r\n TMP_DEST[255:0] <- LOGICAL_LEFT_SHIFT_DWORDS_256b(SRC1[255:0], SRC2)\r\nFI;\r\nIF VL = 512\r\n TMP_DEST[255:0] <- LOGICAL_LEFT_SHIFT_DWORDS_256b(SRC1[255:0], SRC2)\r\n TMP_DEST[511:256] <- LOGICAL_LEFT_SHIFT_DWORDS_256b(SRC1[511:256], SRC2)\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_DEST[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\nVPSLLD (ymm, ymm, xmm/m128) - VEX.256 encoding\r\nDEST[255:0] <-LOGICAL_LEFT_SHIFT_DWORDS_256b(SRC1, SRC2)\r\nDEST[MAX_VL-1:256] <-0;\r\n\r\nVPSLLD (ymm, imm8) - VEX.256 encoding\r\nDEST[255:0] <-LOGICAL_LEFT_SHIFT_DWORDS_256b(SRC1, imm8)\r\nDEST[MAX_VL-1:256] <-0;\r\n\r\nVPSLLD (xmm, xmm, xmm/m128) - VEX.128 encoding\r\nDEST[127:0] <-LOGICAL_LEFT_SHIFT_DWORDS(SRC1, SRC2)\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVPSLLD (xmm, imm8) - VEX.128 encoding\r\nDEST[127:0] <-LOGICAL_LEFT_SHIFT_DWORDS(SRC1, imm8)\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nPSLLD (xmm, xmm, xmm/m128)\r\nDEST[127:0] <-LOGICAL_LEFT_SHIFT_DWORDS(DEST, SRC)\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nPSLLD (xmm, imm8)\r\nDEST[127:0] <-LOGICAL_LEFT_SHIFT_DWORDS(DEST, imm8)\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVPSLLQ (EVEX versions, imm8)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC1 *is memory*)\r\n THEN DEST[i+63:i] <- LOGICAL_LEFT_SHIFT_QWORDS1(SRC1[63:0], imm8)\r\n ELSE DEST[i+63:i] <- LOGICAL_LEFT_SHIFT_QWORDS1(SRC1[i+63:i], imm8)\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\n\r\nVPSLLQ (EVEX versions, xmm/m128)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF VL = 128\r\n TMP_DEST[127:0] <- LOGICAL_LEFT_SHIFT_QWORDS_128b(SRC1[127:0], SRC2)\r\nFI;\r\nIF VL = 256\r\n TMP_DEST[255:0] <- LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC1[255:0], SRC2)\r\nFI;\r\nIF VL = 512\r\n TMP_DEST[255:0] <-LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC1[255:0], SRC2)\r\n TMP_DEST[511:256] <-LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC1[511:256], SRC2)\r\nFI;\r\n\r\n\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <-0\r\n\r\nVPSLLQ (ymm, ymm, xmm/m128) - VEX.256 encoding\r\nDEST[255:0] <-LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC1, SRC2)\r\nDEST[MAX_VL-1:256] <-0;\r\n\r\nVPSLLQ (ymm, imm8) - VEX.256 encoding\r\nDEST[255:0] <-LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC1, imm8)\r\nDEST[MAX_VL-1:256] <-0;\r\n\r\nVPSLLQ (xmm, xmm, xmm/m128) - VEX.128 encoding\r\nDEST[127:0] <-LOGICAL_LEFT_SHIFT_QWORDS(SRC1, SRC2)\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVPSLLQ (xmm, imm8) - VEX.128 encoding\r\nDEST[127:0] <-LOGICAL_LEFT_SHIFT_QWORDS(SRC1, imm8)\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nPSLLQ (xmm, xmm, xmm/m128)\r\nDEST[127:0] <-LOGICAL_LEFT_SHIFT_QWORDS(DEST, SRC)\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nPSLLQ (xmm, imm8)\r\nDEST[127:0] <-LOGICAL_LEFT_SHIFT_QWORDS(DEST, imm8)\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPSLLD __m512i _mm512_slli_epi32(__m512i a, unsigned int imm);\r\nVPSLLD __m512i _mm512_mask_slli_epi32(__m512i s, __mmask16 k, __m512i a, unsigned int imm);\r\nVPSLLD __m512i _mm512_maskz_slli_epi32( __mmask16 k, __m512i a, unsigned int imm);\r\nVPSLLD __m256i _mm256_mask_slli_epi32(__m256i s, __mmask8 k, __m256i a, unsigned int imm);\r\nVPSLLD __m256i _mm256_maskz_slli_epi32( __mmask8 k, __m256i a, unsigned int imm);\r\nVPSLLD __m128i _mm_mask_slli_epi32(__m128i s, __mmask8 k, __m128i a, unsigned int imm);\r\nVPSLLD __m128i _mm_maskz_slli_epi32( __mmask8 k, __m128i a, unsigned int imm);\r\nVPSLLD __m512i _mm512_sll_epi32(__m512i a, __m128i cnt);\r\nVPSLLD __m512i _mm512_mask_sll_epi32(__m512i s, __mmask16 k, __m512i a, __m128i cnt);\r\nVPSLLD __m512i _mm512_maskz_sll_epi32( __mmask16 k, __m512i a, __m128i cnt);\r\nVPSLLD __m256i _mm256_mask_sll_epi32(__m256i s, __mmask8 k, __m256i a, __m128i cnt);\r\nVPSLLD __m256i _mm256_maskz_sll_epi32( __mmask8 k, __m256i a, __m128i cnt);\r\nVPSLLD __m128i _mm_mask_sll_epi32(__m128i s, __mmask8 k, __m128i a, __m128i cnt);\r\nVPSLLD __m128i _mm_maskz_sll_epi32( __mmask8 k, __m128i a, __m128i cnt);\r\n\r\n\r\n\r\nVPSLLQ __m512i _mm512_mask_slli_epi64(__m512i a, unsigned int imm);\r\nVPSLLQ __m512i _mm512_mask_slli_epi64(__m512i s, __mmask8 k, __m512i a, unsigned int imm);\r\nVPSLLQ __m512i _mm512_maskz_slli_epi64( __mmask8 k, __m512i a, unsigned int imm);\r\nVPSLLQ __m256i _mm256_mask_slli_epi64(__m256i s, __mmask8 k, __m256i a, unsigned int imm);\r\nVPSLLQ __m256i _mm256_maskz_slli_epi64( __mmask8 k, __m256i a, unsigned int imm);\r\nVPSLLQ __m128i _mm_mask_slli_epi64(__m128i s, __mmask8 k, __m128i a, unsigned int imm);\r\nVPSLLQ __m128i _mm_maskz_slli_epi64( __mmask8 k, __m128i a, unsigned int imm);\r\nVPSLLQ __m512i _mm512_mask_sll_epi64(__m512i a, __m128i cnt);\r\nVPSLLQ __m512i _mm512_mask_sll_epi64(__m512i s, __mmask8 k, __m512i a, __m128i cnt);\r\nVPSLLQ __m512i _mm512_maskz_sll_epi64( __mmask8 k, __m512i a, __m128i cnt);\r\nVPSLLQ __m256i _mm256_mask_sll_epi64(__m256i s, __mmask8 k, __m256i a, __m128i cnt);\r\nVPSLLQ __m256i _mm256_maskz_sll_epi64( __mmask8 k, __m256i a, __m128i cnt);\r\nVPSLLQ __m128i _mm_mask_sll_epi64(__m128i s, __mmask8 k, __m128i a, __m128i cnt);\r\nVPSLLQ __m128i _mm_maskz_sll_epi64( __mmask8 k, __m128i a, __m128i cnt);\r\nVPSLLW __m512i _mm512_slli_epi16(__m512i a, unsigned int imm);\r\nVPSLLW __m512i _mm512_mask_slli_epi16(__m512i s, __mmask32 k, __m512i a, unsigned int imm);\r\nVPSLLW __m512i _mm512_maskz_slli_epi16( __mmask32 k, __m512i a, unsigned int imm);\r\nVPSLLW __m256i _mm256_mask_sllii_epi16(__m256i s, __mmask16 k, __m256i a, unsigned int imm);\r\nVPSLLW __m256i _mm256_maskz_slli_epi16( __mmask16 k, __m256i a, unsigned int imm);\r\nVPSLLW __m128i _mm_mask_slli_epi16(__m128i s, __mmask8 k, __m128i a, unsigned int imm);\r\nVPSLLW __m128i _mm_maskz_slli_epi16( __mmask8 k, __m128i a, unsigned int imm);\r\nVPSLLW __m512i _mm512_sll_epi16(__m512i a, __m128i cnt);\r\nVPSLLW __m512i _mm512_mask_sll_epi16(__m512i s, __mmask32 k, __m512i a, __m128i cnt);\r\nVPSLLW __m512i _mm512_maskz_sll_epi16( __mmask32 k, __m512i a, __m128i cnt);\r\nVPSLLW __m256i _mm256_mask_sll_epi16(__m256i s, __mmask16 k, __m256i a, __m128i cnt);\r\nVPSLLW __m256i _mm256_maskz_sll_epi16( __mmask16 k, __m256i a, __m128i cnt);\r\nVPSLLW __m128i _mm_mask_sll_epi16(__m128i s, __mmask8 k, __m128i a, __m128i cnt);\r\nVPSLLW __m128i _mm_maskz_sll_epi16( __mmask8 k, __m128i a, __m128i cnt);\r\nPSLLW:__m64 _mm_slli_pi16 (__m64 m, int count)\r\nPSLLW:__m64 _mm_sll_pi16(__m64 m, __m64 count)\r\n(V)PSLLW:__m128i _mm_slli_pi16(__m64 m, int count)\r\n(V)PSLLW:__m128i _mm_slli_pi16(__m128i m, __m128i count)\r\nVPSLLW:__m256i _mm256_slli_epi16 (__m256i m, int count)\r\nVPSLLW:__m256i _mm256_sll_epi16 (__m256i m, __m128i count)\r\nPSLLD:__m64 _mm_slli_pi32(__m64 m, int count)\r\nPSLLD:__m64 _mm_sll_pi32(__m64 m, __m64 count)\r\n(V)PSLLD:__m128i _mm_slli_epi32(__m128i m, int count)\r\n(V)PSLLD:__m128i _mm_sll_epi32(__m128i m, __m128i count)\r\nVPSLLD:__m256i _mm256_slli_epi32 (__m256i m, int count)\r\nVPSLLD:__m256i _mm256_sll_epi32 (__m256i m, __m128i count)\r\nPSLLQ:__m64 _mm_slli_si64(__m64 m, int count)\r\nPSLLQ:__m64 _mm_sll_si64(__m64 m, __m64 count)\r\n(V)PSLLQ:__m128i _mm_slli_epi64(__m128i m, int count)\r\n(V)PSLLQ:__m128i _mm_sll_epi64(__m128i m, __m128i count)\r\nVPSLLQ:__m256i _mm256_slli_epi64 (__m256i m, int count)\r\nVPSLLQ:__m256i _mm256_sll_epi64 (__m256i m, __m128i count)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nNumeric Exceptions\r\nNone.\r\n\r\n\r\n\r\n\r\nOther Exceptions\r\nVEX-encoded instructions:\r\n Syntax with RM/RVM operand encoding, see Exceptions Type 4.\r\n Syntax with MI/VMI operand encoding, see Exceptions Type 7.\r\n\r\n\r\nEVEX-encoded VPSLLW, see Exceptions Type E4NF.nb.\r\n\r\n\r\nEVEX-encoded VPSLLD/Q:\r\n Syntax with M128 operand encoding, see Exceptions Type E4NF.nb.\r\n Syntax with FVI operand encoding, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PSLLW"
},
{
"description": "-R:PSRAW",
"mnem": "PSRAD"
},
{
"description": "-R:PSRAW",
"mnem": "PSRAQ"
},
{
"description": "PSRAW/PSRAD/PSRAQ-Shift Packed Data Right Arithmetic\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F E1 /r1 RM V/V MMX Shift words in mm right by mm/m64 while shifting\r\nPSRAW mm, mm/m64 in sign bits.\r\n\r\n66 0F E1 /r RM V/V SSE2 Shift words in xmm1 right by xmm2/m128 while\r\nPSRAW xmm1, xmm2/m128 shifting in sign bits.\r\n\r\n0F 71 /4 ib1 MI V/V MMX Shift words in mm right by imm8 while shifting in\r\nPSRAW mm, imm8 sign bits\r\n\r\n66 0F 71 /4 ib MI V/V SSE2 Shift words in xmm1 right by imm8 while shifting\r\nPSRAW xmm1, imm8 in sign bits\r\n\r\n0F E2 /r1 RM V/V MMX Shift doublewords in mm right by mm/m64 while\r\nPSRAD mm, mm/m64 shifting in sign bits.\r\n\r\n66 0F E2 /r RM V/V SSE2 Shift doubleword in xmm1 right by xmm2 /m128\r\nPSRAD xmm1, xmm2/m128 while shifting in sign bits.\r\n\r\n0F 72 /4 ib1 MI V/V MMX Shift doublewords in mm right by imm8 while\r\nPSRAD mm, imm8 shifting in sign bits.\r\n\r\n66 0F 72 /4 ib MI V/V SSE2 Shift doublewords in xmm1 right by imm8 while\r\nPSRAD xmm1, imm8 shifting in sign bits.\r\n\r\nVEX.NDS.128.66.0F.WIG E1 /r RVM V/V AVX Shift words in xmm2 right by amount specified in\r\nVPSRAW xmm1, xmm2, xmm3/m128 xmm3/m128 while shifting in sign bits.\r\n\r\nVEX.NDD.128.66.0F.WIG 71 /4 ib VMI V/V AVX Shift words in xmm2 right by imm8 while shifting\r\nVPSRAW xmm1, xmm2, imm8 in sign bits.\r\n\r\nVEX.NDS.128.66.0F.WIG E2 /r RVM V/V AVX Shift doublewords in xmm2 right by amount\r\nVPSRAD xmm1, xmm2, xmm3/m128 specified in xmm3/m128 while shifting in sign\r\n bits.\r\nVEX.NDD.128.66.0F.WIG 72 /4 ib VMI V/V AVX Shift doublewords in xmm2 right by imm8 while\r\nVPSRAD xmm1, xmm2, imm8 shifting in sign bits.\r\n\r\nVEX.NDS.256.66.0F.WIG E1 /r RVM V/V AVX2 Shift words in ymm2 right by amount specified in\r\nVPSRAW ymm1, ymm2, xmm3/m128 xmm3/m128 while shifting in sign bits.\r\n\r\nVEX.NDD.256.66.0F.WIG 71 /4 ib VMI V/V AVX2 Shift words in ymm2 right by imm8 while shifting\r\nVPSRAW ymm1, ymm2, imm8 in sign bits.\r\nVEX.NDS.256.66.0F.WIG E2 /r RVM V/V AVX2 Shift doublewords in ymm2 right by amount\r\nVPSRAD ymm1, ymm2, xmm3/m128 specified in xmm3/m128 while shifting in sign\r\n bits.\r\nVEX.NDD.256.66.0F.WIG 72 /4 ib VMI V/V AVX2 Shift doublewords in ymm2 right by imm8 while\r\nVPSRAD ymm1, ymm2, imm8 shifting in sign bits.\r\n\r\nEVEX.NDS.128.66.0F.WIG E1 /r M128 V/V AVX512VL Shift words in xmm2 right by amount specified in\r\nVPSRAW xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512BW xmm3/m128 while shifting in sign bits using\r\n writemask k1.\r\nEVEX.NDS.256.66.0F.WIG E1 /r M128 V/V AVX512VL Shift words in ymm2 right by amount specified in\r\nVPSRAW ymm1 {k1}{z}, ymm2, xmm3/m128 AVX512BW xmm3/m128 while shifting in sign bits using\r\n writemask k1.\r\nEVEX.NDS.512.66.0F.WIG E1 /r M128 V/V AVX512BW Shift words in zmm2 right by amount specified in\r\nVPSRAW zmm1 {k1}{z}, zmm2, xmm3/m128 xmm3/m128 while shifting in sign bits using\r\n writemask k1.\r\n\r\n\r\n\r\n\r\nEVEX.NDD.128.66.0F.WIG 71 /4 ib FVMI V/V AVX512VL Shift words in xmm2/m128 right by imm8 while\r\nVPSRAW xmm1 {k1}{z}, xmm2/m128, imm8 AVX512BW shifting in sign bits using writemask k1.\r\nEVEX.NDD.256.66.0F.WIG 71 /4 ib FVMI V/V AVX512VL Shift words in ymm2/m256 right by imm8 while\r\nVPSRAW ymm1 {k1}{z}, ymm2/m256, imm8 AVX512BW shifting in sign bits using writemask k1.\r\nEVEX.NDD.512.66.0F.WIG 71 /4 ib FVMI V/V AVX512BW Shift words in zmm2/m512 right by imm8 while\r\nVPSRAW zmm1 {k1}{z}, zmm2/m512, imm8 shifting in sign bits using writemask k1.\r\nEVEX.NDS.128.66.0F.W0 E2 /r M128 V/V AVX512VL Shift doublewords in xmm2 right by amount\r\nVPSRAD xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512F specified in xmm3/m128 while shifting in sign bits\r\n using writemask k1.\r\nEVEX.NDS.256.66.0F.W0 E2 /r M128 V/V AVX512VL Shift doublewords in ymm2 right by amount\r\nVPSRAD ymm1 {k1}{z}, ymm2, xmm3/m128 AVX512F specified in xmm3/m128 while shifting in sign bits\r\n using writemask k1.\r\nEVEX.NDS.512.66.0F.W0 E2 /r M128 V/V AVX512F Shift doublewords in zmm2 right by amount\r\nVPSRAD zmm1 {k1}{z}, zmm2, xmm3/m128 specified in xmm3/m128 while shifting in sign bits\r\n using writemask k1.\r\nEVEX.NDD.128.66.0F.W0 72 /4 ib FVI V/V AVX512VL Shift doublewords in xmm2/m128/m32bcst right\r\nVPSRAD xmm1 {k1}{z}, xmm2/m128/m32bcst, AVX512F by imm8 while shifting in sign bits using\r\nimm8 writemask k1.\r\nEVEX.NDD.256.66.0F.W0 72 /4 ib FVI V/V AVX512VL Shift doublewords in ymm2/m256/m32bcst right\r\nVPSRAD ymm1 {k1}{z}, ymm2/m256/m32bcst, AVX512F by imm8 while shifting in sign bits using\r\nimm8 writemask k1.\r\nEVEX.NDD.512.66.0F.W0 72 /4 ib FVI V/V AVX512F Shift doublewords in zmm2/m512/m32bcst right\r\nVPSRAD zmm1 {k1}{z}, zmm2/m512/m32bcst, by imm8 while shifting in sign bits using\r\nimm8 writemask k1.\r\nEVEX.NDS.128.66.0F.W1 E2 /r M128 V/V AVX512VL Shift quadwords in xmm2 right by amount\r\nVPSRAQ xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512F specified in xmm3/m128 while shifting in sign bits\r\n using writemask k1.\r\nEVEX.NDS.256.66.0F.W1 E2 /r M128 V/V AVX512VL Shift quadwords in ymm2 right by amount\r\nVPSRAQ ymm1 {k1}{z}, ymm2, xmm3/m128 AVX512F specified in xmm3/m128 while shifting in sign bits\r\n using writemask k1.\r\nEVEX.NDS.512.66.0F.W1 E2 /r M128 V/V AVX512F Shift quadwords in zmm2 right by amount\r\nVPSRAQ zmm1 {k1}{z}, zmm2, xmm3/m128 specified in xmm3/m128 while shifting in sign bits\r\n using writemask k1.\r\nEVEX.NDD.128.66.0F.W1 72 /4 ib FVI V/V AVX512VL Shift quadwords in xmm2/m128/m64bcst right by\r\nVPSRAQ xmm1 {k1}{z}, xmm2/m128/m64bcst, AVX512F imm8 while shifting in sign bits using writemask\r\nimm8 k1.\r\nEVEX.NDD.256.66.0F.W1 72 /4 ib FVI V/V AVX512VL Shift quadwords in ymm2/m256/m64bcst right by\r\nVPSRAQ ymm1 {k1}{z}, ymm2/m256/m64bcst, AVX512F imm8 while shifting in sign bits using writemask\r\nimm8 k1.\r\nEVEX.NDD.512.66.0F.W1 72 /4 ib FVI V/V AVX512F Shift quadwords in zmm2/m512/m64bcst right by\r\nVPSRAQ zmm1 {k1}{z}, zmm2/m512/m64bcst, imm8 while shifting in sign bits using writemask\r\nimm8 k1.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\" in\r\nthe Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n MI ModRM:r/m (r, w) imm8 NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n VMI VEX.vvvv (w) ModRM:r/m (r) imm8 NA\r\n FVMI EVEX.vvvv (w) ModRM:r/m (R) Imm8 NA\r\n FVI EVEX.vvvv (w) ModRM:r/m (R) Imm8 NA\r\n M128 ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nShifts the bits in the individual data elements (words, doublewords or quadwords) in the destination operand (first\r\noperand) to the right by the number of bits specified in the count operand (second operand). As the bits in the data\r\nelements are shifted right, the empty high-order bits are filled with the initial value of the sign bit of the data\r\nelement. If the value specified by the count operand is greater than 15 (for words), 31 (for doublewords), or 63 (for\r\nquadwords), each destination data element is filled with the initial value of the sign bit of the element. (Figure 4-18\r\ngives an example of shifting words in a 64-bit operand.)\r\n\r\n\r\n\r\n Pre-Shift\r\n X3 X2 X1 X0\r\n DEST\r\n Shift Right\r\n with Sign\r\n Extension\r\n\r\n Post-Shift\r\n DEST X3 >> COUNT X2 >> COUNT X1 >> COUNT X0 >> COUNT\r\n\r\n\r\n\r\n\r\n Figure 4-18. PSRAW and PSRAD Instruction Operation Using a 64-bit Operand\r\n\r\n\r\nNote that only the first 64-bits of a 128-bit count operand are checked to compute the count. If the second source\r\noperand is a memory address, 128 bits are loaded.\r\nThe (V)PSRAW instruction shifts each of the words in the destination operand to the right by the number of bits\r\nspecified in the count operand, and the (V)PSRAD instruction shifts each of the doublewords in the destination\r\noperand.\r\nIn 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to\r\naccess additional registers (XMM8-XMM15).\r\nLegacy SSE instructions 64-bit operand: The destination operand is an MMX technology register; the count\r\noperand can be either an MMX technology register or an 64-bit memory location.\r\n128-bit Legacy SSE version: The destination and first source operands are XMM registers. Bits (VLMAX-1:128) of\r\nthe corresponding YMM destination register remain unchanged. The count operand can be either an XMM register\r\nor a 128-bit memory location or an 8-bit immediate. If the count operand is a memory address, 128 bits are loaded\r\nbut the upper 64 bits are ignored.\r\nVEX.128 encoded version: The destination and first source operands are XMM registers. Bits (VLMAX-1:128) of the\r\ndestination YMM register are zeroed. The count operand can be either an XMM register or a 128-bit memory loca-\r\ntion or an 8-bit immediate. If the count operand is a memory address, 128 bits are loaded but the upper 64 bits are\r\nignored.\r\nVEX.256 encoded version: The destination operand is a YMM register. The source operand is a YMM register or a\r\nmemory location. The count operand can come either from an XMM register or a memory location or an 8-bit\r\nimmediate. Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed.\r\n\r\n\r\n\r\nEVEX encoded versions: The destination operand is a ZMM register updated according to the writemask. The count\r\noperand is either an 8-bit immediate (the immediate count version) or an 8-bit value from an XMM register or a\r\nmemory location (the variable count version). For the immediate count version, the source operand (the second\r\noperand) can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32/64-bit\r\nmemory location. For the variable count version, the first source operand (the second operand) is a ZMM register,\r\nthe second source operand (the third operand, 8-bit variable count) can be an XMM register or a memory location.\r\nNote: In VEX/EVEX encoded versions of shifts with an immediate count, vvvv of VEX/EVEX encode the destination\r\nregister, and VEX.B/EVEX.B + ModRM.r/m encodes the source register.\r\nNote: For shifts with an immediate count (VEX.128.66.0F 71-73 /4, EVEX.128.66.0F 71-73 /4),\r\nVEX.vvvv/EVEX.vvvv encodes the destination register.\r\n\r\nOperation\r\nPSRAW (with 64-bit operand)\r\n IF (COUNT > 15)\r\n THEN COUNT <- 16;\r\n FI;\r\n DEST[15:0] <- SignExtend(DEST[15:0] >> COUNT);\r\n (* Repeat shift operation for 2nd and 3rd words *)\r\n DEST[63:48] <- SignExtend(DEST[63:48] >> COUNT);\r\n\r\n\r\nPSRAD (with 64-bit operand)\r\n IF (COUNT > 31)\r\n THEN COUNT <- 32;\r\n FI;\r\n DEST[31:0] <- SignExtend(DEST[31:0] >> COUNT);\r\n DEST[63:32] <- SignExtend(DEST[63:32] >> COUNT);\r\n\r\nARITHMETIC_RIGHT_SHIFT_DWORDS1(SRC, COUNT_SRC)\r\nCOUNT <- COUNT_SRC[63:0];\r\nIF (COUNT > 31)\r\nTHEN\r\n DEST[31:0] <- SignBit\r\nELSE\r\n DEST[31:0] <- SignExtend(SRC[31:0] >> COUNT);\r\nFI;\r\n\r\nARITHMETIC_RIGHT_SHIFT_QWORDS1(SRC, COUNT_SRC)\r\nCOUNT <- COUNT_SRC[63:0];\r\nIF (COUNT > 63)\r\nTHEN\r\n DEST[63:0] <- SignBit\r\nELSE\r\n DEST[63:0] <- SignExtend(SRC[63:0] >> COUNT);\r\nFI;\r\n\r\nARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC, COUNT_SRC)\r\nCOUNT <- COUNT_SRC[63:0];\r\nIF (COUNT > 15)\r\n THEN COUNT <- 16;\r\nFI;\r\nDEST[15:0] <- SignExtend(SRC[15:0] >> COUNT);\r\n (* Repeat shift operation for 2nd through 15th words *)\r\nDEST[255:240] <- SignExtend(SRC[255:240] >> COUNT);\r\n\r\n\r\n\r\nARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC, COUNT_SRC)\r\nCOUNT <- COUNT_SRC[63:0];\r\nIF (COUNT > 31)\r\n THEN COUNT <- 32;\r\nFI;\r\nDEST[31:0] <- SignExtend(SRC[31:0] >> COUNT);\r\n (* Repeat shift operation for 2nd through 7th words *)\r\nDEST[255:224] <- SignExtend(SRC[255:224] >> COUNT);\r\n\r\nARITHMETIC_RIGHT_SHIFT_QWORDS(SRC, COUNT_SRC, VL) ; VL: 128b, 256b or 512b\r\nCOUNT <- COUNT_SRC[63:0];\r\nIF (COUNT > 63)\r\n THEN COUNT <- 64;\r\nFI;\r\nDEST[63:0] <- SignExtend(SRC[63:0] >> COUNT);\r\n (* Repeat shift operation for 2nd through 7th words *)\r\nDEST[VL-1:VL-64] <- SignExtend(SRC[VL-1:VL-64] >> COUNT);\r\n\r\n\r\n\r\nARITHMETIC_RIGHT_SHIFT_WORDS(SRC, COUNT_SRC)\r\nCOUNT <- COUNT_SRC[63:0];\r\nIF (COUNT > 15)\r\n THEN COUNT <- 16;\r\nFI;\r\nDEST[15:0] <- SignExtend(SRC[15:0] >> COUNT);\r\n (* Repeat shift operation for 2nd through 7th words *)\r\nDEST[127:112] <- SignExtend(SRC[127:112] >> COUNT);\r\n\r\nARITHMETIC_RIGHT_SHIFT_DWORDS(SRC, COUNT_SRC)\r\nCOUNT <- COUNT_SRC[63:0];\r\nIF (COUNT > 31)\r\n THEN COUNT <- 32;\r\nFI;\r\nDEST[31:0] <- SignExtend(SRC[31:0] >> COUNT);\r\n (* Repeat shift operation for 2nd through 3rd words *)\r\nDEST[127:96] <- SignExtend(SRC[127:96] >> COUNT);\r\n\r\n\r\n\r\n\r\n\r\nVPSRAW (EVEX versions, xmm/m128)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nIF VL = 128\r\n TMP_DEST[127:0] <- ARITHMETIC_RIGHT_SHIFT_WORDS_128b(SRC1[127:0], SRC2)\r\nFI;\r\nIF VL = 256\r\n TMP_DEST[255:0] <- ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], SRC2)\r\nFI;\r\nIF VL = 512\r\n TMP_DEST[255:0] <- ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], SRC2)\r\n TMP_DEST[511:256] <- ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[511:256], SRC2)\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- TMP_DEST[i+15:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] = 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPSRAW (EVEX versions, imm8)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nIF VL = 128\r\n TMP_DEST[127:0] <- ARITHMETIC_RIGHT_SHIFT_WORDS_128b(SRC1[127:0], imm8)\r\nFI;\r\nIF VL = 256\r\n TMP_DEST[255:0] <- ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], imm8)\r\nFI;\r\nIF VL = 512\r\n TMP_DEST[255:0] <- ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], imm8)\r\n TMP_DEST[511:256] <- ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[511:256], imm8)\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- TMP_DEST[i+15:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] = 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\nVPSRAW (ymm, ymm, xmm/m128) - VEX\r\nDEST[255:0] <- ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1, SRC2)\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVPSRAW (ymm, imm8) - VEX\r\nDEST[255:0] <- ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1, imm8)\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVPSRAW (xmm, xmm, xmm/m128) - VEX\r\nDEST[127:0] <- ARITHMETIC_RIGHT_SHIFT_WORDS(SRC1, SRC2)\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVPSRAW (xmm, imm8) - VEX\r\nDEST[127:0] <- ARITHMETIC_RIGHT_SHIFT_WORDS(SRC1, imm8)\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nPSRAW (xmm, xmm, xmm/m128)\r\nDEST[127:0] <-ARITHMETIC_RIGHT_SHIFT_WORDS(DEST, SRC)\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nPSRAW (xmm, imm8)\r\nDEST[127:0] <-ARITHMETIC_RIGHT_SHIFT_WORDS(DEST, imm8)\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVPSRAD (EVEX versions, imm8)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC1 *is memory*)\r\n THEN DEST[i+31:i] <- ARITHMETIC_RIGHT_SHIFT_DWORDS1(SRC1[31:0], imm8)\r\n ELSE DEST[i+31:i] <- ARITHMETIC_RIGHT_SHIFT_DWORDS1(SRC1[i+31:i], imm8)\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPSRAD (EVEX versions, xmm/m128)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF VL = 128\r\n TMP_DEST[127:0] <- ARITHMETIC_RIGHT_SHIFT_DWORDS_128b(SRC1[127:0], SRC2)\r\nFI;\r\nIF VL = 256\r\n TMP_DEST[255:0] <- ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC1[255:0], SRC2)\r\nFI;\r\nIF VL = 512\r\n TMP_DEST[255:0] <- ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC1[255:0], SRC2)\r\n TMP_DEST[511:256] <- ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC1[511:256], SRC2)\r\n\r\n\r\n\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_DEST[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPSRAD (ymm, ymm, xmm/m128) - VEX\r\nDEST[255:0] <-ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC1, SRC2)\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVPSRAD (ymm, imm8) - VEX\r\nDEST[255:0] <-ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC1, imm8)\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVPSRAD (xmm, xmm, xmm/m128) - VEX\r\nDEST[127:0] <-ARITHMETIC_RIGHT_SHIFT_DWORDS(SRC1, SRC2)\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVPSRAD (xmm, imm8) - VEX\r\nDEST[127:0] <-ARITHMETIC_RIGHT_SHIFT_DWORDS(SRC1, imm8)\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nPSRAD (xmm, xmm, xmm/m128)\r\nDEST[127:0] <-ARITHMETIC_RIGHT_SHIFT_DWORDS(DEST, SRC)\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nPSRAD (xmm, imm8)\r\nDEST[127:0] <-ARITHMETIC_RIGHT_SHIFT_DWORDS(DEST, imm8)\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVPSRAQ (EVEX versions, imm8)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC1 *is memory*)\r\n THEN DEST[i+63:i] <- ARITHMETIC_RIGHT_SHIFT_QWORDS1(SRC1[63:0], imm8)\r\n ELSE DEST[i+63:i] <- ARITHMETIC_RIGHT_SHIFT_QWORDS1(SRC1[i+63:i], imm8)\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n\r\n\r\n\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPSRAQ (EVEX versions, xmm/m128)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nTMP_DEST[VL-1:0] <- ARITHMETIC_RIGHT_SHIFT_QWORDS(SRC1[VL-1:0], SRC2, VL)\r\n\r\nFOR j <- 0 TO 7\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPSRAD __m512i _mm512_srai_epi32(__m512i a, unsigned int imm);\r\nVPSRAD __m512i _mm512_mask_srai_epi32(__m512i s, __mmask16 k, __m512i a, unsigned int imm);\r\nVPSRAD __m512i _mm512_maskz_srai_epi32( __mmask16 k, __m512i a, unsigned int imm);\r\nVPSRAD __m256i _mm256_mask_srai_epi32(__m256i s, __mmask8 k, __m256i a, unsigned int imm);\r\nVPSRAD __m256i _mm256_maskz_srai_epi32( __mmask8 k, __m256i a, unsigned int imm);\r\nVPSRAD __m128i _mm_mask_srai_epi32(__m128i s, __mmask8 k, __m128i a, unsigned int imm);\r\nVPSRAD __m128i _mm_maskz_srai_epi32( __mmask8 k, __m128i a, unsigned int imm);\r\nVPSRAD __m512i _mm512_sra_epi32(__m512i a, __m128i cnt);\r\nVPSRAD __m512i _mm512_mask_sra_epi32(__m512i s, __mmask16 k, __m512i a, __m128i cnt);\r\nVPSRAD __m512i _mm512_maskz_sra_epi32( __mmask16 k, __m512i a, __m128i cnt);\r\nVPSRAD __m256i _mm256_mask_sra_epi32(__m256i s, __mmask8 k, __m256i a, __m128i cnt);\r\nVPSRAD __m256i _mm256_maskz_sra_epi32( __mmask8 k, __m256i a, __m128i cnt);\r\nVPSRAD __m128i _mm_mask_sra_epi32(__m128i s, __mmask8 k, __m128i a, __m128i cnt);\r\nVPSRAD __m128i _mm_maskz_sra_epi32( __mmask8 k, __m128i a, __m128i cnt);\r\nVPSRAQ __m512i _mm512_srai_epi64(__m512i a, unsigned int imm);\r\nVPSRAQ __m512i _mm512_mask_srai_epi64(__m512i s, __mmask8 k, __m512i a, unsigned int imm)\r\nVPSRAQ __m512i _mm512_maskz_srai_epi64( __mmask8 k, __m512i a, unsigned int imm)\r\nVPSRAQ __m256i _mm256_mask_srai_epi64(__m256i s, __mmask8 k, __m256i a, unsigned int imm);\r\nVPSRAQ __m256i _mm256_maskz_srai_epi64( __mmask8 k, __m256i a, unsigned int imm);\r\nVPSRAQ __m128i _mm_mask_srai_epi64(__m128i s, __mmask8 k, __m128i a, unsigned int imm);\r\nVPSRAQ __m128i _mm_maskz_srai_epi64( __mmask8 k, __m128i a, unsigned int imm);\r\nVPSRAQ __m512i _mm512_sra_epi64(__m512i a, __m128i cnt);\r\nVPSRAQ __m512i _mm512_mask_sra_epi64(__m512i s, __mmask8 k, __m512i a, __m128i cnt)\r\nVPSRAQ __m512i _mm512_maskz_sra_epi64( __mmask8 k, __m512i a, __m128i cnt)\r\nVPSRAQ __m256i _mm256_mask_sra_epi64(__m256i s, __mmask8 k, __m256i a, __m128i cnt);\r\nVPSRAQ __m256i _mm256_maskz_sra_epi64( __mmask8 k, __m256i a, __m128i cnt);\r\nVPSRAQ __m128i _mm_mask_sra_epi64(__m128i s, __mmask8 k, __m128i a, __m128i cnt);\r\nVPSRAQ __m128i _mm_maskz_sra_epi64( __mmask8 k, __m128i a, __m128i cnt);\r\nVPSRAW __m512i _mm512_srai_epi16(__m512i a, unsigned int imm);\r\nVPSRAW __m512i _mm512_mask_srai_epi16(__m512i s, __mmask32 k, __m512i a, unsigned int imm);\r\n\r\n\r\n\r\nVPSRAW __m512i _mm512_maskz_srai_epi16( __mmask32 k, __m512i a, unsigned int imm);\r\nVPSRAW __m256i _mm256_mask_srai_epi16(__m256i s, __mmask16 k, __m256i a, unsigned int imm);\r\nVPSRAW __m256i _mm256_maskz_srai_epi16( __mmask16 k, __m256i a, unsigned int imm);\r\nVPSRAW __m128i _mm_mask_srai_epi16(__m128i s, __mmask8 k, __m128i a, unsigned int imm);\r\nVPSRAW __m128i _mm_maskz_srai_epi16( __mmask8 k, __m128i a, unsigned int imm);\r\nVPSRAW __m512i _mm512_sra_epi16(__m512i a, __m128i cnt);\r\nVPSRAW __m512i _mm512_mask_sra_epi16(__m512i s, __mmask16 k, __m512i a, __m128i cnt);\r\nVPSRAW __m512i _mm512_maskz_sra_epi16( __mmask16 k, __m512i a, __m128i cnt);\r\nVPSRAW __m256i _mm256_mask_sra_epi16(__m256i s, __mmask8 k, __m256i a, __m128i cnt);\r\nVPSRAW __m256i _mm256_maskz_sra_epi16( __mmask8 k, __m256i a, __m128i cnt);\r\nVPSRAW __m128i _mm_mask_sra_epi16(__m128i s, __mmask8 k, __m128i a, __m128i cnt);\r\nVPSRAW __m128i _mm_maskz_sra_epi16( __mmask8 k, __m128i a, __m128i cnt);\r\nPSRAW:__m64 _mm_srai_pi16 (__m64 m, int count)\r\nPSRAW:__m64 _mm_sra_pi16 (__m64 m, __m64 count)\r\n(V)PSRAW:__m128i _mm_srai_epi16(__m128i m, int count)\r\n(V)PSRAW:__m128i _mm_sra_epi16(__m128i m, __m128i count)\r\nVPSRAW:__m256i _mm256_srai_epi16 (__m256i m, int count)\r\nVPSRAW:__m256i _mm256_sra_epi16 (__m256i m, __m128i count)\r\nPSRAD:__m64 _mm_srai_pi32 (__m64 m, int count)\r\nPSRAD:__m64 _mm_sra_pi32 (__m64 m, __m64 count)\r\n(V)PSRAD:__m128i _mm_srai_epi32 (__m128i m, int count)\r\n(V)PSRAD:__m128i _mm_sra_epi32 (__m128i m, __m128i count)\r\nVPSRAD:__m256i _mm256_srai_epi32 (__m256i m, int count)\r\nVPSRAD:__m256i _mm256_sra_epi32 (__m256i m, __m128i count)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nNumeric Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nVEX-encoded instructions:\r\n Syntax with RM/RVM operand encoding, see Exceptions Type 4.\r\n Syntax with MI/VMI operand encoding, see Exceptions Type 7.\r\n\r\n\r\nEVEX-encoded VPSRAW, see Exceptions Type E4NF.nb.\r\n\r\n\r\nEVEX-encoded VPSRAD/Q:\r\n Syntax with M128 operand encoding, see Exceptions Type E4NF.nb.\r\n Syntax with FVI operand encoding, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PSRAW"
},
{
"description": "-R:PSRLW",
"mnem": "PSRLD"
},
{
"description": "PSRLDQ-Shift Double Quadword Right Logical\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n66 0F 73 /3 ib MI V/V SSE2 Shift xmm1 right by imm8 while shifting in 0s.\r\nPSRLDQ xmm1, imm8\r\nVEX.NDD.128.66.0F.WIG 73 /3 ib VMI V/V AVX Shift xmm2 right by imm8 bytes while shifting in\r\nVPSRLDQ xmm1, xmm2, imm8 0s.\r\n\r\nVEX.NDD.256.66.0F.WIG 73 /3 ib VMI V/V AVX2 Shift ymm1 right by imm8 bytes while shifting in\r\nVPSRLDQ ymm1, ymm2, imm8 0s.\r\n\r\nEVEX.NDD.128.66.0F.WIG 73 /3 ib FVM V/V AVX512VL Shift xmm2/m128 right by imm8 bytes while\r\nVPSRLDQ xmm1, xmm2/m128, imm8 AVX512BW shifting in 0s and store result in xmm1.\r\nEVEX.NDD.256.66.0F.WIG 73 /3 ib FVM V/V AVX512VL Shift ymm2/m256 right by imm8 bytes while\r\nVPSRLDQ ymm1, ymm2/m256, imm8 AVX512BW shifting in 0s and store result in ymm1.\r\nEVEX.NDD.512.66.0F.WIG 73 /3 ib FVM V/V AVX512BW Shift zmm2/m512 right by imm8 bytes while\r\nVPSRLDQ zmm1, zmm2/m512, imm8 shifting in 0s and store result in zmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n MI ModRM:r/m (r, w) imm8 NA NA\r\n VMI VEX.vvvv (w) ModRM:r/m (r) imm8 NA\r\n FVM EVEX.vvvv (w) ModRM:r/m (R) Imm8 NA\r\n\r\n\r\nDescription\r\nShifts the destination operand (first operand) to the right by the number of bytes specified in the count operand\r\n(second operand). The empty high-order bytes are cleared (set to all 0s). If the value specified by the count\r\noperand is greater than 15, the destination operand is set to all 0s. The count operand is an 8-bit immediate.\r\nIn 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to\r\naccess additional registers (XMM8-XMM15).\r\n128-bit Legacy SSE version: The source and destination operands are the same. Bits (VLMAX-1:128) of the corre-\r\nsponding YMM destination register remain unchanged.\r\nVEX.128 encoded version: The source and destination operands are XMM registers. Bits (VLMAX-1:128) of the\r\ndestination YMM register are zeroed.\r\nVEX.256 encoded version: The source operand is a YMM register. The destination operand is a YMM register. The\r\ncount operand applies to both the low and high 128-bit lanes.\r\nVEX.256 encoded version: The source operand is YMM register. The destination operand is an YMM register. Bits\r\n(MAX_VL-1:256) of the corresponding ZMM register are zeroed. The count operand applies to both the low and\r\nhigh 128-bit lanes.\r\nEVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location.\r\nThe destination operand is a ZMM/YMM/XMM register. The count operand applies to each 128-bit lanes.\r\nNote: VEX.vvvv/EVEX.vvvv encodes the destination register.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVPSRLDQ (EVEX.512 encoded version)\r\nTEMP <- COUNT\r\nIF (TEMP > 15) THEN TEMP <- 16; FI\r\nDEST[127:0] <- SRC[127:0] >> (TEMP * 8)\r\nDEST[255:128] <- SRC[255:128] >> (TEMP * 8)\r\nDEST[383:256] <- SRC[383:256] >> (TEMP * 8)\r\nDEST[511:384] <- SRC[511:384] >> (TEMP * 8)\r\nDEST[MAX_VL-1:512] <- 0;\r\n\r\nVPSRLDQ (VEX.256 and EVEX.256 encoded version)\r\nTEMP <- COUNT\r\nIF (TEMP > 15) THEN TEMP <- 16; FI\r\nDEST[127:0] <- SRC[127:0] >> (TEMP * 8)\r\nDEST[255:128] <- SRC[255:128] >> (TEMP * 8)\r\nDEST[MAX_VL-1:256] <- 0;\r\n\r\nVPSRLDQ (VEX.128 and EVEX.128 encoded version)\r\nTEMP <- COUNT\r\nIF (TEMP > 15) THEN TEMP <- 16; FI\r\nDEST <- SRC >> (TEMP * 8)\r\nDEST[MAX_VL-1:128] <- 0;\r\n\r\nPSRLDQ(128-bit Legacy SSE version)\r\nTEMP <- COUNT\r\nIF (TEMP > 15) THEN TEMP <- 16; FI\r\nDEST <- DEST >> (TEMP * 8)\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\n(V)PSRLDQ __m128i _mm_srli_si128 ( __m128i a, int imm)\r\nVPSRLDQ __m256i _mm256_bsrli_epi128 ( __m256i, const int)\r\nVPSRLDQ __m512i _mm512_bsrli_epi128 ( __m512i, int)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nNumeric Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 7.\r\nEVEX-encoded instruction, see Exceptions Type E4NF.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PSRLDQ"
},
{
"description": "-R:PSRLW",
"mnem": "PSRLQ"
},
{
"description": "PSRLW/PSRLD/PSRLQ-Shift Packed Data Right Logical\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F D1 /r1 RM V/V MMX Shift words in mm right by amount specified in\r\nPSRLW mm, mm/m64 mm/m64 while shifting in 0s.\r\n\r\n66 0F D1 /r RM V/V SSE2 Shift words in xmm1 right by amount\r\nPSRLW xmm1, xmm2/m128 specified in xmm2/m128 while shifting in 0s.\r\n\r\n0F 71 /2 ib1 MI V/V MMX Shift words in mm right by imm8 while shifting\r\nPSRLW mm, imm8 in 0s.\r\n\r\n66 0F 71 /2 ib MI V/V SSE2 Shift words in xmm1 right by imm8 while\r\nPSRLW xmm1, imm8 shifting in 0s.\r\n\r\n0F D2 /r1 RM V/V MMX Shift doublewords in mm right by amount\r\nPSRLD mm, mm/m64 specified in mm/m64 while shifting in 0s.\r\n\r\n66 0F D2 /r RM V/V SSE2 Shift doublewords in xmm1 right by amount\r\nPSRLD xmm1, xmm2/m128 specified in xmm2 /m128 while shifting in 0s.\r\n\r\n0F 72 /2 ib1 MI V/V MMX Shift doublewords in mm right by imm8 while\r\nPSRLD mm, imm8 shifting in 0s.\r\n\r\n66 0F 72 /2 ib MI V/V SSE2 Shift doublewords in xmm1 right by imm8\r\nPSRLD xmm1, imm8 while shifting in 0s.\r\n\r\n0F D3 /r1 RM V/V MMX Shift mm right by amount specified in\r\nPSRLQ mm, mm/m64 mm/m64 while shifting in 0s.\r\n\r\n66 0F D3 /r RM V/V SSE2 Shift quadwords in xmm1 right by amount\r\nPSRLQ xmm1, xmm2/m128 specified in xmm2/m128 while shifting in 0s.\r\n\r\n0F 73 /2 ib1 MI V/V MMX Shift mm right by imm8 while shifting in 0s.\r\nPSRLQ mm, imm8\r\n66 0F 73 /2 ib MI V/V SSE2 Shift quadwords in xmm1 right by imm8 while\r\nPSRLQ xmm1, imm8 shifting in 0s.\r\n\r\nVEX.NDS.128.66.0F.WIG D1 /r RVM V/V AVX Shift words in xmm2 right by amount\r\nVPSRLW xmm1, xmm2, xmm3/m128 specified in xmm3/m128 while shifting in 0s.\r\n\r\nVEX.NDD.128.66.0F.WIG 71 /2 ib VMI V/V AVX Shift words in xmm2 right by imm8 while\r\nVPSRLW xmm1, xmm2, imm8 shifting in 0s.\r\n\r\nVEX.NDS.128.66.0F.WIG D2 /r RVM V/V AVX Shift doublewords in xmm2 right by amount\r\nVPSRLD xmm1, xmm2, xmm3/m128 specified in xmm3/m128 while shifting in 0s.\r\n\r\nVEX.NDD.128.66.0F.WIG 72 /2 ib VMI V/V AVX Shift doublewords in xmm2 right by imm8\r\nVPSRLD xmm1, xmm2, imm8 while shifting in 0s.\r\n\r\nVEX.NDS.128.66.0F.WIG D3 /r RVM V/V AVX Shift quadwords in xmm2 right by amount\r\nVPSRLQ xmm1, xmm2, xmm3/m128 specified in xmm3/m128 while shifting in 0s.\r\n\r\nVEX.NDD.128.66.0F.WIG 73 /2 ib VMI V/V AVX Shift quadwords in xmm2 right by imm8 while\r\nVPSRLQ xmm1, xmm2, imm8 shifting in 0s.\r\n\r\nVEX.NDS.256.66.0F.WIG D1 /r RVM V/V AVX2 Shift words in ymm2 right by amount specified\r\nVPSRLW ymm1, ymm2, xmm3/m128 in xmm3/m128 while shifting in 0s.\r\n\r\nVEX.NDD.256.66.0F.WIG 71 /2 ib VMI V/V AVX2 Shift words in ymm2 right by imm8 while\r\nVPSRLW ymm1, ymm2, imm8 shifting in 0s.\r\n\r\n\r\n\r\n\r\n\r\nVEX.NDS.256.66.0F.WIG D2 /r RVM V/V AVX2 Shift doublewords in ymm2 right by amount\r\nVPSRLD ymm1, ymm2, xmm3/m128 specified in xmm3/m128 while shifting in 0s.\r\n\r\nVEX.NDD.256.66.0F.WIG 72 /2 ib VMI V/V AVX2 Shift doublewords in ymm2 right by imm8\r\nVPSRLD ymm1, ymm2, imm8 while shifting in 0s.\r\n\r\nVEX.NDS.256.66.0F.WIG D3 /r RVM V/V AVX2 Shift quadwords in ymm2 right by amount\r\nVPSRLQ ymm1, ymm2, xmm3/m128 specified in xmm3/m128 while shifting in 0s.\r\n\r\nVEX.NDD.256.66.0F.WIG 73 /2 ib VMI V/V AVX2 Shift quadwords in ymm2 right by imm8 while\r\nVPSRLQ ymm1, ymm2, imm8 shifting in 0s.\r\n\r\nEVEX.NDS.128.66.0F.WIG D1 /r M128 V/V AVX512VL Shift words in xmm2 right by amount specified\r\nVPSRLW xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512BW in xmm3/m128 while shifting in 0s using\r\n writemask k1.\r\nEVEX.NDS.256.66.0F.WIG D1 /r M128 V/V AVX512VL Shift words in ymm2 right by amount specified\r\nVPSRLW ymm1 {k1}{z}, ymm2, xmm3/m128 AVX512BW in xmm3/m128 while shifting in 0s using\r\n writemask k1.\r\nEVEX.NDS.512.66.0F.WIG D1 /r M128 V/V AVX512BW Shift words in zmm2 right by amount specified\r\nVPSRLW zmm1 {k1}{z}, zmm2, xmm3/m128 in xmm3/m128 while shifting in 0s using\r\n writemask k1.\r\nEVEX.NDD.128.66.0F.WIG 71 /2 ib FVM V/V AVX512VL Shift words in xmm2/m128 right by imm8\r\nVPSRLW xmm1 {k1}{z}, xmm2/m128, imm8 AVX512BW while shifting in 0s using writemask k1.\r\nEVEX.NDD.256.66.0F.WIG 71 /2 ib FVM V/V AVX512VL Shift words in ymm2/m256 right by imm8\r\nVPSRLW ymm1 {k1}{z}, ymm2/m256, imm8 AVX512BW while shifting in 0s using writemask k1.\r\nEVEX.NDD.512.66.0F.WIG 71 /2 ib FVM V/V AVX512BW Shift words in zmm2/m512 right by imm8\r\nVPSRLW zmm1 {k1}{z}, zmm2/m512, imm8 while shifting in 0s using writemask k1.\r\nEVEX.NDS.128.66.0F.W0 D2 /r M128 V/V AVX512VL Shift doublewords in xmm2 right by amount\r\nVPSRLD xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512F specified in xmm3/m128 while shifting in 0s\r\n using writemask k1.\r\nEVEX.NDS.256.66.0F.W0 D2 /r M128 V/V AVX512VL Shift doublewords in ymm2 right by amount\r\nVPSRLD ymm1 {k1}{z}, ymm2, xmm3/m128 AVX512F specified in xmm3/m128 while shifting in 0s\r\n using writemask k1.\r\nEVEX.NDS.512.66.0F.W0 D2 /r M128 V/V AVX512F Shift doublewords in zmm2 right by amount\r\nVPSRLD zmm1 {k1}{z}, zmm2, xmm3/m128 specified in xmm3/m128 while shifting in 0s\r\n using writemask k1.\r\nEVEX.NDD.128.66.0F.W0 72 /2 ib FV V/V AVX512VL Shift doublewords in xmm2/m128/m32bcst\r\nVPSRLD xmm1 {k1}{z}, xmm2/m128/m32bcst, AVX512F right by imm8 while shifting in 0s using\r\nimm8 writemask k1.\r\nEVEX.NDD.256.66.0F.W0 72 /2 ib FV V/V AVX512VL Shift doublewords in ymm2/m256/m32bcst\r\nVPSRLD ymm1 {k1}{z}, ymm2/m256/m32bcst, AVX512F right by imm8 while shifting in 0s using\r\nimm8 writemask k1.\r\nEVEX.NDD.512.66.0F.W0 72 /2 ib FVI V/V AVX512F Shift doublewords in zmm2/m512/m32bcst\r\nVPSRLD zmm1 {k1}{z}, zmm2/m512/m32bcst, right by imm8 while shifting in 0s using\r\nimm8 writemask k1.\r\nEVEX.NDS.128.66.0F.W1 D3 /r M128 V/V AVX512VL Shift quadwords in xmm2 right by amount\r\nVPSRLQ xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512F specified in xmm3/m128 while shifting in 0s\r\n using writemask k1.\r\nEVEX.NDS.256.66.0F.W1 D3 /r M128 V/V AVX512VL Shift quadwords in ymm2 right by amount\r\nVPSRLQ ymm1 {k1}{z}, ymm2, xmm3/m128 AVX512F specified in xmm3/m128 while shifting in 0s\r\n using writemask k1.\r\nEVEX.NDS.512.66.0F.W1 D3 /r M128 V/V AVX512F Shift quadwords in zmm2 right by amount\r\nVPSRLQ zmm1 {k1}{z}, zmm2, xmm3/m128 specified in xmm3/m128 while shifting in 0s\r\n using writemask k1.\r\n\r\n\r\n\r\n\r\nEVEX.NDD.128.66.0F.W1 73 /2 ib FV V/V AVX512VL Shift quadwords in xmm2/m128/m64bcst\r\nVPSRLQ xmm1 {k1}{z}, xmm2/m128/m64bcst, AVX512F right by imm8 while shifting in 0s using\r\nimm8 writemask k1.\r\nEVEX.NDD.256.66.0F.W1 73 /2 ib FV V/V AVX512VL Shift quadwords in ymm2/m256/m64bcst\r\nVPSRLQ ymm1 {k1}{z}, ymm2/m256/m64bcst, AVX512F right by imm8 while shifting in 0s using\r\nimm8 writemask k1.\r\nEVEX.NDD.512.66.0F.W1 73 /2 ib FVI V/V AVX512F Shift quadwords in zmm2/m512/m64bcst\r\nVPSRLQ zmm1 {k1}{z}, zmm2/m512/m64bcst, right by imm8 while shifting in 0s using\r\nimm8 writemask k1.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n MI ModRM:r/m (r, w) imm8 NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n VMI VEX.vvvv (w) ModRM:r/m (r) imm8 NA\r\n FVM EVEX.vvvv (w) ModRM:r/m (R) Imm8 NA\r\n FVI EVEX.vvvv (w) ModRM:r/m (R) Imm8 NA\r\n M128 ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nShifts the bits in the individual data elements (words, doublewords, or quadword) in the destination operand (first\r\noperand) to the right by the number of bits specified in the count operand (second operand). As the bits in the data\r\nelements are shifted right, the empty high-order bits are cleared (set to 0). If the value specified by the count\r\noperand is greater than 15 (for words), 31 (for doublewords), or 63 (for a quadword), then the destination operand\r\nis set to all 0s. Figure 4-19 gives an example of shifting words in a 64-bit operand.\r\nNote that only the low 64-bits of a 128-bit count operand are checked to compute the count.\r\n\r\n\r\n Pre-Shift\r\n X3 X2 X1 X0\r\n DEST\r\n Shift Right\r\n with Zero\r\n Extension\r\n\r\n Post-Shift\r\n DEST X3 >> COUNT X2 >> COUNT X1 >> COUNT X0 >> COUNT\r\n\r\n Figure 4-19. PSRLW, PSRLD, and PSRLQ Instruction Operation Using 64-bit Operand\r\n\r\nThe (V)PSRLW instruction shifts each of the words in the destination operand to the right by the number of bits\r\nspecified in the count operand; the (V)PSRLD instruction shifts each of the doublewords in the destination operand;\r\nand the PSRLQ instruction shifts the quadword (or quadwords) in the destination operand.\r\nIn 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to\r\naccess additional registers (XMM8-XMM15).\r\nLegacy SSE instruction 64-bit operand: The destination operand is an MMX technology register; the count operand\r\ncan be either an MMX technology register or an 64-bit memory location.\r\n\r\n\r\n\r\n128-bit Legacy SSE version: The destination operand is an XMM register; the count operand can be either an XMM\r\nregister or a 128-bit memory location, or an 8-bit immediate. If the count operand is a memory address, 128 bits\r\nare loaded but the upper 64 bits are ignored. Bits (VLMAX-1:128) of the corresponding YMM destination register\r\nremain unchanged.\r\nVEX.128 encoded version: The destination operand is an XMM register; the count operand can be either an XMM\r\nregister or a 128-bit memory location, or an 8-bit immediate. If the count operand is a memory address, 128 bits\r\nare loaded but the upper 64 bits are ignored. Bits (VLMAX-1:128) of the destination YMM register are zeroed.\r\nVEX.256 encoded version: The destination operand is a YMM register. The source operand is a YMM register or a\r\nmemory location. The count operand can come either from an XMM register or a memory location or an 8-bit imme-\r\ndiate. Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed.\r\nEVEX encoded versions: The destination operand is a ZMM register updated according to the writemask. The count\r\noperand is either an 8-bit immediate (the immediate count version) or an 8-bit value from an XMM register or a\r\nmemory location (the variable count version). For the immediate count version, the source operand (the second\r\noperand) can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32/64-bit\r\nmemory location. For the variable count version, the first source operand (the second operand) is a ZMM register,\r\nthe second source operand (the third operand, 8-bit variable count) can be an XMM register or a memory location.\r\nNote: In VEX/EVEX encoded versions of shifts with an immediate count, vvvv of VEX/EVEX encode the destination\r\nregister, and VEX.B/EVEX.B + ModRM.r/m encodes the source register.\r\nNote: For shifts with an immediate count (VEX.128.66.0F 71-73 /2, or EVEX.128.66.0F 71-73 /2),\r\nVEX.vvvv/EVEX.vvvv encodes the destination register.\r\n\r\nOperation\r\n\r\nPSRLW (with 64-bit operand)\r\n IF (COUNT > 15)\r\n THEN\r\n DEST[64:0] <- 0000000000000000H\r\n ELSE\r\n DEST[15:0] <- ZeroExtend(DEST[15:0] >> COUNT);\r\n (* Repeat shift operation for 2nd and 3rd words *)\r\n DEST[63:48] <- ZeroExtend(DEST[63:48] >> COUNT);\r\n FI;\r\n\r\nPSRLD (with 64-bit operand)\r\n IF (COUNT > 31)\r\n THEN\r\n DEST[64:0] <- 0000000000000000H\r\n ELSE\r\n DEST[31:0] <- ZeroExtend(DEST[31:0] >> COUNT);\r\n DEST[63:32] <- ZeroExtend(DEST[63:32] >> COUNT);\r\n FI;\r\n\r\nPSRLQ (with 64-bit operand)\r\n IF (COUNT > 63)\r\n THEN\r\n DEST[64:0] <- 0000000000000000H\r\n ELSE\r\n DEST <- ZeroExtend(DEST >> COUNT);\r\n FI;\r\nLOGICAL_RIGHT_SHIFT_DWORDS1(SRC, COUNT_SRC)\r\nCOUNT <- COUNT_SRC[63:0];\r\nIF (COUNT > 31)\r\nTHEN\r\n DEST[31:0] <- 0\r\nELSE\r\n\r\n\r\n\r\n DEST[31:0] <- ZeroExtend(SRC[31:0] >> COUNT);\r\nFI;\r\n\r\nLOGICAL_RIGHT_SHIFT_QWORDS1(SRC, COUNT_SRC)\r\nCOUNT <- COUNT_SRC[63:0];\r\nIF (COUNT > 63)\r\nTHEN\r\n DEST[63:0] <- 0\r\nELSE\r\n DEST[63:0] <- ZeroExtend(SRC[63:0] >> COUNT);\r\nFI;\r\nLOGICAL_RIGHT_SHIFT_WORDS_256b(SRC, COUNT_SRC)\r\nCOUNT <-COUNT_SRC[63:0];\r\nIF (COUNT > 15)\r\nTHEN\r\n DEST[255:0] <-0\r\nELSE\r\n DEST[15:0] <-ZeroExtend(SRC[15:0] >> COUNT);\r\n (* Repeat shift operation for 2nd through 15th words *)\r\n DEST[255:240] <-ZeroExtend(SRC[255:240] >> COUNT);\r\nFI;\r\n\r\nLOGICAL_RIGHT_SHIFT_WORDS(SRC, COUNT_SRC)\r\nCOUNT <-COUNT_SRC[63:0];\r\nIF (COUNT > 15)\r\nTHEN\r\n DEST[127:0] <-00000000000000000000000000000000H\r\nELSE\r\n DEST[15:0] <-ZeroExtend(SRC[15:0] >> COUNT);\r\n (* Repeat shift operation for 2nd through 7th words *)\r\n DEST[127:112] <-ZeroExtend(SRC[127:112] >> COUNT);\r\nFI;\r\n\r\nLOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC, COUNT_SRC)\r\nCOUNT <-COUNT_SRC[63:0];\r\nIF (COUNT > 31)\r\nTHEN\r\n DEST[255:0] <-0\r\nELSE\r\n DEST[31:0] <-ZeroExtend(SRC[31:0] >> COUNT);\r\n (* Repeat shift operation for 2nd through 3rd words *)\r\n DEST[255:224] <-ZeroExtend(SRC[255:224] >> COUNT);\r\nFI;\r\n\r\nLOGICAL_RIGHT_SHIFT_DWORDS(SRC, COUNT_SRC)\r\nCOUNT <-COUNT_SRC[63:0];\r\nIF (COUNT > 31)\r\nTHEN\r\n DEST[127:0] <-00000000000000000000000000000000H\r\nELSE\r\n DEST[31:0] <-ZeroExtend(SRC[31:0] >> COUNT);\r\n (* Repeat shift operation for 2nd through 3rd words *)\r\n DEST[127:96] <-ZeroExtend(SRC[127:96] >> COUNT);\r\nFI;\r\n\r\n\r\n\r\nLOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC, COUNT_SRC)\r\nCOUNT <-COUNT_SRC[63:0];\r\nIF (COUNT > 63)\r\nTHEN\r\n DEST[255:0] <-0\r\nELSE\r\n DEST[63:0] <-ZeroExtend(SRC[63:0] >> COUNT);\r\n DEST[127:64] <-ZeroExtend(SRC[127:64] >> COUNT);\r\n DEST[191:128] <-ZeroExtend(SRC[191:128] >> COUNT);\r\n DEST[255:192] <-ZeroExtend(SRC[255:192] >> COUNT);\r\nFI;\r\n\r\nLOGICAL_RIGHT_SHIFT_QWORDS(SRC, COUNT_SRC)\r\nCOUNT <-COUNT_SRC[63:0];\r\nIF (COUNT > 63)\r\nTHEN\r\n DEST[127:0] <-00000000000000000000000000000000H\r\nELSE\r\n DEST[63:0] <-ZeroExtend(SRC[63:0] >> COUNT);\r\n DEST[127:64] <-ZeroExtend(SRC[127:64] >> COUNT);\r\nFI;\r\n\r\n\r\n\r\n\r\n\r\nVPSRLW (EVEX versions, xmm/m128)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nIF VL = 128\r\n TMP_DEST[127:0] <- LOGICAL_RIGHT_SHIFT_WORDS_128b(SRC1[127:0], SRC2)\r\nFI;\r\nIF VL = 256\r\n TMP_DEST[255:0] <- LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], SRC2)\r\nFI;\r\nIF VL = 512\r\n TMP_DEST[255:0] <- LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], SRC2)\r\n TMP_DEST[511:256] <- LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[511:256], SRC2)\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- TMP_DEST[i+15:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] = 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPSRLW (EVEX versions, imm8)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nIF VL = 128\r\n TMP_DEST[127:0] <- LOGICAL_RIGHT_SHIFT_WORDS_128b(SRC1[127:0], imm8)\r\nFI;\r\nIF VL = 256\r\n TMP_DEST[255:0] <- LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], imm8)\r\nFI;\r\nIF VL = 512\r\n TMP_DEST[255:0] <- LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], imm8)\r\n TMP_DEST[511:256] <- LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[511:256], imm8)\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- TMP_DEST[i+15:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] = 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\nVPSRLW (ymm, ymm, xmm/m128) - VEX.256 encoding\r\nDEST[255:0] <-LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1, SRC2)\r\nDEST[MAX_VL-1:256] <-0;\r\n\r\nVPSRLW (ymm, imm8) - VEX.256 encoding\r\nDEST[255:0] <-LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1, imm8)\r\nDEST[MAX_VL-1:256] <-0;\r\n\r\nVPSRLW (xmm, xmm, xmm/m128) - VEX.128 encoding\r\nDEST[127:0] <-LOGICAL_RIGHT_SHIFT_WORDS(SRC1, SRC2)\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVPSRLW (xmm, imm8) - VEX.128 encoding\r\nDEST[127:0] <-LOGICAL_RIGHT_SHIFT_WORDS(SRC1, imm8)\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nPSRLW (xmm, xmm, xmm/m128)\r\nDEST[127:0] <-LOGICAL_RIGHT_SHIFT_WORDS(DEST, SRC)\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nPSRLW (xmm, imm8)\r\nDEST[127:0] <-LOGICAL_RIGHT_SHIFT_WORDS(DEST, imm8)\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVPSRLD (EVEX versions, xmm/m128)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF VL = 128\r\n TMP_DEST[127:0] <- LOGICAL_RIGHT_SHIFT_DWORDS_128b(SRC1[127:0], SRC2)\r\nFI;\r\nIF VL = 256\r\n TMP_DEST[255:0] <- LOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC1[255:0], SRC2)\r\nFI;\r\nIF VL = 512\r\n TMP_DEST[255:0] <- LOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC1[255:0], SRC2)\r\n TMP_DEST[511:256] <- LOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC1[511:256], SRC2)\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_DEST[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVPSRLD (EVEX versions, imm8)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC1 *is memory*)\r\n THEN DEST[i+31:i] <- LOGICAL_RIGHT_SHIFT_DWORDS1(SRC1[31:0], imm8)\r\n ELSE DEST[i+31:i] <- LOGICAL_RIGHT_SHIFT_DWORDS1(SRC1[i+31:i], imm8)\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPSRLD (ymm, ymm, xmm/m128) - VEX.256 encoding\r\nDEST[255:0] <-LOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC1, SRC2)\r\nDEST[MAX_VL-1:256] <-0;\r\n\r\nVPSRLD (ymm, imm8) - VEX.256 encoding\r\nDEST[255:0] <-LOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC1, imm8)\r\nDEST[MAX_VL-1:256] <-0;\r\n\r\nVPSRLD (xmm, xmm, xmm/m128) - VEX.128 encoding\r\nDEST[127:0] <-LOGICAL_RIGHT_SHIFT_DWORDS(SRC1, SRC2)\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVPSRLD (xmm, imm8) - VEX.128 encoding\r\nDEST[127:0] <-LOGICAL_RIGHT_SHIFT_DWORDS(SRC1, imm8)\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nPSRLD (xmm, xmm, xmm/m128)\r\nDEST[127:0] <-LOGICAL_RIGHT_SHIFT_DWORDS(DEST, SRC)\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nPSRLD (xmm, imm8)\r\nDEST[127:0] <-LOGICAL_RIGHT_SHIFT_DWORDS(DEST, imm8)\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\n\r\n\r\n\r\n\r\nVPSRLQ (EVEX versions, xmm/m128)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nTMP_DEST[255:0] <- LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1[255:0], SRC2)\r\nTMP_DEST[511:256] <- LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1[511:256], SRC2)\r\nIF VL = 128\r\n TMP_DEST[127:0] <- LOGICAL_RIGHT_SHIFT_QWORDS_128b(SRC1[127:0], SRC2)\r\nFI;\r\nIF VL = 256\r\n TMP_DEST[255:0] <- LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1[255:0], SRC2)\r\nFI;\r\nIF VL = 512\r\n TMP_DEST[255:0] <- LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1[255:0], SRC2)\r\n TMP_DEST[511:256] <- LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1[511:256], SRC2)\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPSRLQ (EVEX versions, imm8)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC1 *is memory*)\r\n THEN DEST[i+63:i] <- LOGICAL_RIGHT_SHIFT_QWORDS1(SRC1[63:0], imm8)\r\n ELSE DEST[i+63:i] <- LOGICAL_RIGHT_SHIFT_QWORDS1(SRC1[i+63:i], imm8)\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPSRLQ (ymm, ymm, xmm/m128) - VEX.256 encoding\r\nDEST[255:0] <-LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1, SRC2)\r\nDEST[MAX_VL-1:256] <-0;\r\n\r\nVPSRLQ (ymm, imm8) - VEX.256 encoding\r\nDEST[255:0] <-LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1, imm8)\r\nDEST[MAX_VL-1:256] <-0;\r\n\r\n\r\n\r\nVPSRLQ (xmm, xmm, xmm/m128) - VEX.128 encoding\r\nDEST[127:0] <-LOGICAL_RIGHT_SHIFT_QWORDS(SRC1, SRC2)\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVPSRLQ (xmm, imm8) - VEX.128 encoding\r\nDEST[127:0] <-LOGICAL_RIGHT_SHIFT_QWORDS(SRC1, imm8)\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nPSRLQ (xmm, xmm, xmm/m128)\r\nDEST[127:0] <-LOGICAL_RIGHT_SHIFT_QWORDS(DEST, SRC)\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nPSRLQ (xmm, imm8)\r\nDEST[127:0] <-LOGICAL_RIGHT_SHIFT_QWORDS(DEST, imm8)\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPSRLD __m512i _mm512_srli_epi32(__m512i a, unsigned int imm);\r\nVPSRLD __m512i _mm512_mask_srli_epi32(__m512i s, __mmask16 k, __m512i a, unsigned int imm);\r\nVPSRLD __m512i _mm512_maskz_srli_epi32( __mmask16 k, __m512i a, unsigned int imm);\r\nVPSRLD __m256i _mm256_mask_srli_epi32(__m256i s, __mmask8 k, __m256i a, unsigned int imm);\r\nVPSRLD __m256i _mm256_maskz_srli_epi32( __mmask8 k, __m256i a, unsigned int imm);\r\nVPSRLD __m128i _mm_mask_srli_epi32(__m128i s, __mmask8 k, __m128i a, unsigned int imm);\r\nVPSRLD __m128i _mm_maskz_srli_epi32( __mmask8 k, __m128i a, unsigned int imm);\r\nVPSRLD __m512i _mm512_srl_epi32(__m512i a, __m128i cnt);\r\nVPSRLD __m512i _mm512_mask_srl_epi32(__m512i s, __mmask16 k, __m512i a, __m128i cnt);\r\nVPSRLD __m512i _mm512_maskz_srl_epi32( __mmask16 k, __m512i a, __m128i cnt);\r\nVPSRLD __m256i _mm256_mask_srl_epi32(__m256i s, __mmask8 k, __m256i a, __m128i cnt);\r\nVPSRLD __m256i _mm256_maskz_srl_epi32( __mmask8 k, __m256i a, __m128i cnt);\r\nVPSRLD __m128i _mm_mask_srl_epi32(__m128i s, __mmask8 k, __m128i a, __m128i cnt);\r\nVPSRLD __m128i _mm_maskz_srl_epi32( __mmask8 k, __m128i a, __m128i cnt);\r\nVPSRLQ __m512i _mm512_srli_epi64(__m512i a, unsigned int imm);\r\nVPSRLQ __m512i _mm512_mask_srli_epi64(__m512i s, __mmask8 k, __m512i a, unsigned int imm);\r\nVPSRLQ __m512i _mm512_mask_srli_epi64( __mmask8 k, __m512i a, unsigned int imm);\r\nVPSRLQ __m256i _mm256_mask_srli_epi64(__m256i s, __mmask8 k, __m256i a, unsigned int imm);\r\nVPSRLQ __m256i _mm256_maskz_srli_epi64( __mmask8 k, __m256i a, unsigned int imm);\r\nVPSRLQ __m128i _mm_mask_srli_epi64(__m128i s, __mmask8 k, __m128i a, unsigned int imm);\r\nVPSRLQ __m128i _mm_maskz_srli_epi64( __mmask8 k, __m128i a, unsigned int imm);\r\nVPSRLQ __m512i _mm512_srl_epi64(__m512i a, __m128i cnt);\r\nVPSRLQ __m512i _mm512_mask_srl_epi64(__m512i s, __mmask8 k, __m512i a, __m128i cnt);\r\nVPSRLQ __m512i _mm512_mask_srl_epi64( __mmask8 k, __m512i a, __m128i cnt);\r\nVPSRLQ __m256i _mm256_mask_srl_epi64(__m256i s, __mmask8 k, __m256i a, __m128i cnt);\r\nVPSRLQ __m256i _mm256_maskz_srl_epi64( __mmask8 k, __m256i a, __m128i cnt);\r\nVPSRLQ __m128i _mm_mask_srl_epi64(__m128i s, __mmask8 k, __m128i a, __m128i cnt);\r\nVPSRLQ __m128i _mm_maskz_srl_epi64( __mmask8 k, __m128i a, __m128i cnt);\r\nVPSRLW __m512i _mm512_srli_epi16(__m512i a, unsigned int imm);\r\nVPSRLW __m512i _mm512_mask_srli_epi16(__m512i s, __mmask32 k, __m512i a, unsigned int imm);\r\nVPSRLW __m512i _mm512_maskz_srli_epi16( __mmask32 k, __m512i a, unsigned int imm);\r\nVPSRLW __m256i _mm256_mask_srlii_epi16(__m256i s, __mmask16 k, __m256i a, unsigned int imm);\r\nVPSRLW __m256i _mm256_maskz_srli_epi16( __mmask16 k, __m256i a, unsigned int imm);\r\nVPSRLW __m128i _mm_mask_srli_epi16(__m128i s, __mmask8 k, __m128i a, unsigned int imm);\r\nVPSRLW __m128i _mm_maskz_srli_epi16( __mmask8 k, __m128i a, unsigned int imm);\r\nVPSRLW __m512i _mm512_srl_epi16(__m512i a, __m128i cnt);\r\nVPSRLW __m512i _mm512_mask_srl_epi16(__m512i s, __mmask32 k, __m512i a, __m128i cnt);\r\n\r\n\r\n\r\nVPSRLW __m512i _mm512_maskz_srl_epi16( __mmask32 k, __m512i a, __m128i cnt);\r\nVPSRLW __m256i _mm256_mask_srl_epi16(__m256i s, __mmask16 k, __m256i a, __m128i cnt);\r\nVPSRLW __m256i _mm256_maskz_srl_epi16( __mmask8 k, __mmask16 a, __m128i cnt);\r\nVPSRLW __m128i _mm_mask_srl_epi16(__m128i s, __mmask8 k, __m128i a, __m128i cnt);\r\nVPSRLW __m128i _mm_maskz_srl_epi16( __mmask8 k, __m128i a, __m128i cnt);\r\nPSRLW:__m64 _mm_srli_pi16(__m64 m, int count)\r\nPSRLW:__m64 _mm_srl_pi16 (__m64 m, __m64 count)\r\n(V)PSRLW:__m128i _mm_srli_epi16 (__m128i m, int count)\r\n(V)PSRLW:__m128i _mm_srl_epi16 (__m128i m, __m128i count)\r\nVPSRLW:__m256i _mm256_srli_epi16 (__m256i m, int count)\r\nVPSRLW:__m256i _mm256_srl_epi16 (__m256i m, __m128i count)\r\nPSRLD:__m64 _mm_srli_pi32 (__m64 m, int count)\r\nPSRLD:__m64 _mm_srl_pi32 (__m64 m, __m64 count)\r\n(V)PSRLD:__m128i _mm_srli_epi32 (__m128i m, int count)\r\n(V)PSRLD:__m128i _mm_srl_epi32 (__m128i m, __m128i count)\r\nVPSRLD:__m256i _mm256_srli_epi32 (__m256i m, int count)\r\nVPSRLD:__m256i _mm256_srl_epi32 (__m256i m, __m128i count)\r\nPSRLQ:__m64 _mm_srli_si64 (__m64 m, int count)\r\nPSRLQ:__m64 _mm_srl_si64 (__m64 m, __m64 count)\r\n(V)PSRLQ:__m128i _mm_srli_epi64 (__m128i m, int count)\r\n(V)PSRLQ:__m128i _mm_srl_epi64 (__m128i m, __m128i count)\r\nVPSRLQ:__m256i _mm256_srli_epi64 (__m256i m, int count)\r\nVPSRLQ:__m256i _mm256_srl_epi64 (__m256i m, __m128i count)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nNumeric Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nVEX-encoded instructions:\r\n Syntax with RM/RVM operand encoding, see Exceptions Type 4.\r\n Syntax with MI/VMI operand encoding, see Exceptions Type 7.\r\n\r\n\r\nEVEX-encoded VPSRLW, see Exceptions Type E4NF.nb.\r\n\r\n\r\nEVEX-encoded VPSRLD/Q:\r\n Syntax with M128 operand encoding, see Exceptions Type E4NF.nb.\r\n Syntax with FVI operand encoding, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PSRLW"
},
{
"description": "PSUBB/PSUBW/PSUBD-Subtract Packed Integers\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F F8 /r1 RM V/V MMX Subtract packed byte integers in mm/m64\r\nPSUBB mm, mm/m64 from packed byte integers in mm.\r\n\r\n66 0F F8 /r RM V/V SSE2 Subtract packed byte integers in xmm2/m128\r\nPSUBB xmm1, xmm2/m128 from packed byte integers in xmm1.\r\n\r\n0F F9 /r1 RM V/V MMX Subtract packed word integers in mm/m64\r\nPSUBW mm, mm/m64 from packed word integers in mm.\r\n\r\n66 0F F9 /r RM V/V SSE2 Subtract packed word integers in\r\nPSUBW xmm1, xmm2/m128 xmm2/m128 from packed word integers in\r\n xmm1.\r\n0F FA /r1 RM V/V MMX Subtract packed doubleword integers in\r\nPSUBD mm, mm/m64 mm/m64 from packed doubleword integers in\r\n mm.\r\n66 0F FA /r RM V/V SSE2 Subtract packed doubleword integers in\r\nPSUBD xmm1, xmm2/m128 xmm2/mem128 from packed doubleword\r\n integers in xmm1.\r\nVEX.NDS.128.66.0F.WIG F8 /r RVM V/V AVX Subtract packed byte integers in xmm3/m128\r\nVPSUBB xmm1, xmm2, xmm3/m128 from xmm2.\r\nVEX.NDS.128.66.0F.WIG F9 /r RVM V/V AVX Subtract packed word integers in\r\nVPSUBW xmm1, xmm2, xmm3/m128 xmm3/m128 from xmm2.\r\n\r\nVEX.NDS.128.66.0F.WIG FA /r RVM V/V AVX Subtract packed doubleword integers in\r\nVPSUBD xmm1, xmm2, xmm3/m128 xmm3/m128 from xmm2.\r\nVEX.NDS.256.66.0F.WIG F8 /r RVM V/V AVX2 Subtract packed byte integers in ymm3/m256\r\nVPSUBB ymm1, ymm2, ymm3/m256 from ymm2.\r\nVEX.NDS.256.66.0F.WIG F9 /r RVM V/V AVX2 Subtract packed word integers in\r\nVPSUBW ymm1, ymm2, ymm3/m256 ymm3/m256 from ymm2.\r\nVEX.NDS.256.66.0F.WIG FA /r RVM V/V AVX2 Subtract packed doubleword integers in\r\nVPSUBD ymm1, ymm2, ymm3/m256 ymm3/m256 from ymm2.\r\nEVEX.NDS.128.66.0F.WIG F8 /r FVM V/V AVX512VL Subtract packed byte integers in xmm3/m128\r\nVPSUBB xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512BW from xmm2 and store in xmm1 using\r\n writemask k1.\r\nEVEX.NDS.256.66.0F.WIG F8 /r FVM V/V AVX512VL Subtract packed byte integers in ymm3/m256\r\nVPSUBB ymm1 {k1}{z}, ymm2, ymm3/m256 AVX512BW from ymm2 and store in ymm1 using\r\n writemask k1.\r\nEVEX.NDS.512.66.0F.WIG F8 /r FVM V/V AVX512BW Subtract packed byte integers in zmm3/m512\r\nVPSUBB zmm1 {k1}{z}, zmm2, zmm3/m512 from zmm2 and store in zmm1 using\r\n writemask k1.\r\nEVEX.NDS.128.66.0F.WIG F9 /r FVM V/V AVX512VL Subtract packed word integers in\r\nVPSUBW xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512BW xmm3/m128 from xmm2 and store in xmm1\r\n using writemask k1.\r\nEVEX.NDS.256.66.0F.WIG F9 /r FVM V/V AVX512VL Subtract packed word integers in\r\nVPSUBW ymm1 {k1}{z}, ymm2, ymm3/m256 AVX512BW ymm3/m256 from ymm2 and store in ymm1\r\n using writemask k1.\r\nEVEX.NDS.512.66.0F.WIG F9 /r FVM V/V AVX512BW Subtract packed word integers in\r\nVPSUBW zmm1 {k1}{z}, zmm2, zmm3/m512 zmm3/m512 from zmm2 and store in zmm1\r\n using writemask k1.\r\n\r\n\r\n\r\n\r\n\r\nEVEX.NDS.128.66.0F.W0 FA /r FV V/V AVX512VL Subtract packed doubleword integers in\r\nVPSUBD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst AVX512F xmm3/m128/m32bcst from xmm2 and store\r\n in xmm1 using writemask k1.\r\nEVEX.NDS.256.66.0F.W0 FA /r FV V/V AVX512VL Subtract packed doubleword integers in\r\nVPSUBD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst AVX512F ymm3/m256/m32bcst from ymm2 and store\r\n in ymm1 using writemask k1.\r\nEVEX.NDS.512.66.0F.W0 FA /r FV V/V AVX512F Subtract packed doubleword integers in\r\nVPSUBD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst zmm3/m512/m32bcst from zmm2 and store\r\n in zmm1 using writemask k1\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\" in\r\nthe Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nPerforms a SIMD subtract of the packed integers of the source operand (second operand) from the packed integers\r\nof the destination operand (first operand), and stores the packed integer results in the destination operand. See\r\nFigure 9-4 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for an illustration of\r\na SIMD operation. Overflow is handled with wraparound, as described in the following paragraphs.\r\nThe (V)PSUBB instruction subtracts packed byte integers. When an individual result is too large or too small to be\r\nrepresented in a byte, the result is wrapped around and the low 8 bits are written to the destination element.\r\nThe (V)PSUBW instruction subtracts packed word integers. When an individual result is too large or too small to be\r\nrepresented in a word, the result is wrapped around and the low 16 bits are written to the destination element.\r\nThe (V)PSUBD instruction subtracts packed doubleword integers. When an individual result is too large or too small\r\nto be represented in a doubleword, the result is wrapped around and the low 32 bits are written to the destination\r\nelement.\r\nNote that the (V)PSUBB, (V)PSUBW, and (V)PSUBD instructions can operate on either unsigned or signed (two's\r\ncomplement notation) packed integers; however, it does not set bits in the EFLAGS register to indicate overflow\r\nand/or a carry. To prevent undetected overflow conditions, software must control the ranges of values upon which\r\nit operates.\r\nIn 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to\r\naccess additional registers (XMM8-XMM15).\r\nLegacy SSE version 64-bit operand: The destination operand must be an MMX technology register and the source\r\noperand can be either an MMX technology register or a 64-bit memory location.\r\n128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first\r\nsource operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM desti-\r\nnation register remain unchanged.\r\nVEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first\r\nsource operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the destination YMM register\r\nare zeroed.\r\n\r\n\r\n\r\n\r\n\r\nVEX.256 encoded versions: The second source operand is an YMM register or an 256-bit memory location. The first\r\nsource operand and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding ZMM\r\nregister are zeroed.\r\nEVEX encoded VPSUBD: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-\r\ntion or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The first source operand and\r\ndestination operands are ZMM/YMM/XMM registers. The destination is conditionally updated with writemask k1.\r\nEVEX encoded VPSUBB/W: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory\r\nlocation. The first source operand and destination operands are ZMM/YMM/XMM registers. The destination is condi-\r\ntionally updated with writemask k1.\r\n\r\nOperation\r\nPSUBB (with 64-bit operands)\r\n DEST[7:0] <- DEST[7:0] - SRC[7:0];\r\n (* Repeat subtract operation for 2nd through 7th byte *)\r\n DEST[63:56] <- DEST[63:56] - SRC[63:56];\r\n\r\nPSUBW (with 64-bit operands)\r\n DEST[15:0] <- DEST[15:0] - SRC[15:0];\r\n (* Repeat subtract operation for 2nd and 3rd word *)\r\n DEST[63:48] <- DEST[63:48] - SRC[63:48];\r\n\r\nPSUBD (with 64-bit operands)\r\n DEST[31:0] <- DEST[31:0] - SRC[31:0];\r\n DEST[63:32] <- DEST[63:32] - SRC[63:32];\r\n\r\nPSUBD (with 128-bit operands)\r\n DEST[31:0] <- DEST[31:0] - SRC[31:0];\r\n (* Repeat subtract operation for 2nd and 3rd doubleword *)\r\n DEST[127:96] <- DEST[127:96] - SRC[127:96];\r\n\r\nVPSUBB (EVEX encoded versions)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\nFOR j <- 0 TO KL-1\r\n i<-j*8\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- SRC1[i+7:i] - SRC2[i+7:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+7:i] = 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPSUBW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- SRC1[i+15:i] - SRC2[i+15:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n\r\n\r\n\r\n\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] = 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPSUBD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN DEST[i+31:i] <- SRC1[i+31:i] - SRC2[31:0]\r\n ELSE DEST[i+31:i] <- SRC1[i+31:i] - SRC2[i+31:i]\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPSUBB (VEX.256 encoded version)\r\nDEST[7:0] <-SRC1[7:0]-SRC2[7:0]\r\nDEST[15:8] <-SRC1[15:8]-SRC2[15:8]\r\nDEST[23:16] <-SRC1[23:16]-SRC2[23:16]\r\nDEST[31:24] <-SRC1[31:24]-SRC2[31:24]\r\nDEST[39:32] <-SRC1[39:32]-SRC2[39:32]\r\nDEST[47:40] <-SRC1[47:40]-SRC2[47:40]\r\nDEST[55:48] <-SRC1[55:48]-SRC2[55:48]\r\nDEST[63:56] <-SRC1[63:56]-SRC2[63:56]\r\nDEST[71:64] <-SRC1[71:64]-SRC2[71:64]\r\nDEST[79:72] <-SRC1[79:72]-SRC2[79:72]\r\nDEST[87:80] <-SRC1[87:80]-SRC2[87:80]\r\nDEST[95:88] <-SRC1[95:88]-SRC2[95:88]\r\nDEST[103:96] <-SRC1[103:96]-SRC2[103:96]\r\nDEST[111:104] <-SRC1[111:104]-SRC2[111:104]\r\nDEST[119:112] <-SRC1[119:112]-SRC2[119:112]\r\nDEST[127:120] <-SRC1[127:120]-SRC2[127:120]\r\nDEST[135:128] <-SRC1[135:128]-SRC2[135:128]\r\nDEST[143:136] <-SRC1[143:136]-SRC2[143:136]\r\nDEST[151:144] <-SRC1[151:144]-SRC2[151:144]\r\nDEST[159:152] <-SRC1[159:152]-SRC2[159:152]\r\nDEST[167:160] <-SRC1[167:160]-SRC2[167:160]\r\nDEST[175:168] <-SRC1[175:168]-SRC2[175:168]\r\nDEST[183:176] <-SRC1[183:176]-SRC2[183:176]\r\nDEST[191:184] <-SRC1[191:184]-SRC2[191:184]\r\nDEST[199:192] <-SRC1[199:192]-SRC2[199:192]\r\nDEST[207:200] <-SRC1[207:200]-SRC2[207:200]\r\n\r\n\r\n\r\nDEST[215:208] <-SRC1[215:208]-SRC2[215:208]\r\nDEST[223:216] <-SRC1[223:216]-SRC2[223:216]\r\nDEST[231:224] <-SRC1[231:224]-SRC2[231:224]\r\nDEST[239:232] <-SRC1[239:232]-SRC2[239:232]\r\nDEST[247:240] <-SRC1[247:240]-SRC2[247:240]\r\nDEST[255:248] <-SRC1[255:248]-SRC2[255:248]\r\nDEST[MAX_VL-1:256] <-0\r\n\r\nVPSUBB (VEX.128 encoded version)\r\nDEST[7:0] <-SRC1[7:0]-SRC2[7:0]\r\nDEST[15:8] <-SRC1[15:8]-SRC2[15:8]\r\nDEST[23:16] <-SRC1[23:16]-SRC2[23:16]\r\nDEST[31:24] <-SRC1[31:24]-SRC2[31:24]\r\nDEST[39:32] <-SRC1[39:32]-SRC2[39:32]\r\nDEST[47:40] <-SRC1[47:40]-SRC2[47:40]\r\nDEST[55:48] <-SRC1[55:48]-SRC2[55:48]\r\nDEST[63:56] <-SRC1[63:56]-SRC2[63:56]\r\nDEST[71:64] <-SRC1[71:64]-SRC2[71:64]\r\nDEST[79:72] <-SRC1[79:72]-SRC2[79:72]\r\nDEST[87:80] <-SRC1[87:80]-SRC2[87:80]\r\nDEST[95:88] <-SRC1[95:88]-SRC2[95:88]\r\nDEST[103:96] <-SRC1[103:96]-SRC2[103:96]\r\nDEST[111:104] <-SRC1[111:104]-SRC2[111:104]\r\nDEST[119:112] <-SRC1[119:112]-SRC2[119:112]\r\nDEST[127:120] <-SRC1[127:120]-SRC2[127:120]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nPSUBB (128-bit Legacy SSE version)\r\nDEST[7:0] <-DEST[7:0]-SRC[7:0]\r\nDEST[15:8] <-DEST[15:8]-SRC[15:8]\r\nDEST[23:16] <-DEST[23:16]-SRC[23:16]\r\nDEST[31:24] <-DEST[31:24]-SRC[31:24]\r\nDEST[39:32] <-DEST[39:32]-SRC[39:32]\r\nDEST[47:40] <-DEST[47:40]-SRC[47:40]\r\nDEST[55:48] <-DEST[55:48]-SRC[55:48]\r\nDEST[63:56] <-DEST[63:56]-SRC[63:56]\r\nDEST[71:64] <-DEST[71:64]-SRC[71:64]\r\nDEST[79:72] <-DEST[79:72]-SRC[79:72]\r\nDEST[87:80] <-DEST[87:80]-SRC[87:80]\r\nDEST[95:88] <-DEST[95:88]-SRC[95:88]\r\nDEST[103:96] <-DEST[103:96]-SRC[103:96]\r\nDEST[111:104] <-DEST[111:104]-SRC[111:104]\r\nDEST[119:112] <-DEST[119:112]-SRC[119:112]\r\nDEST[127:120] <-DEST[127:120]-SRC[127:120]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVPSUBW (VEX.256 encoded version)\r\nDEST[15:0] <-SRC1[15:0]-SRC2[15:0]\r\nDEST[31:16] <-SRC1[31:16]-SRC2[31:16]\r\nDEST[47:32] <-SRC1[47:32]-SRC2[47:32]\r\nDEST[63:48] <-SRC1[63:48]-SRC2[63:48]\r\nDEST[79:64] <-SRC1[79:64]-SRC2[79:64]\r\nDEST[95:80] <-SRC1[95:80]-SRC2[95:80]\r\nDEST[111:96] <-SRC1[111:96]-SRC2[111:96]\r\n\r\n\r\n\r\nDEST[127:112] <-SRC1[127:112]-SRC2[127:112]\r\nDEST[143:128] <-SRC1[143:128]-SRC2[143:128]\r\nDEST[159:144] <-SRC1[159:144]-SRC2[159:144]\r\nDEST[175:160] <-SRC1[175:160]-SRC2[175:160]\r\nDEST[191:176] <-SRC1[191:176]-SRC2[191:176]\r\nDEST[207:192] <-SRC1207:192]-SRC2[207:192]\r\nDEST[223:208] <-SRC1[223:208]-SRC2[223:208]\r\nDEST[239:224] <-SRC1[239:224]-SRC2[239:224]\r\nDEST[255:240] <-SRC1[255:240]-SRC2[255:240]\r\nDEST[MAX_VL-1:256] <-0\r\n\r\nVPSUBW (VEX.128 encoded version)\r\nDEST[15:0] <-SRC1[15:0]-SRC2[15:0]\r\nDEST[31:16] <-SRC1[31:16]-SRC2[31:16]\r\nDEST[47:32] <-SRC1[47:32]-SRC2[47:32]\r\nDEST[63:48] <-SRC1[63:48]-SRC2[63:48]\r\nDEST[79:64] <-SRC1[79:64]-SRC2[79:64]\r\nDEST[95:80] <-SRC1[95:80]-SRC2[95:80]\r\nDEST[111:96] <-SRC1[111:96]-SRC2[111:96]\r\nDEST[127:112] <-SRC1[127:112]-SRC2[127:112]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nPSUBW (128-bit Legacy SSE version)\r\nDEST[15:0] <-DEST[15:0]-SRC[15:0]\r\nDEST[31:16] <-DEST[31:16]-SRC[31:16]\r\nDEST[47:32] <-DEST[47:32]-SRC[47:32]\r\nDEST[63:48] <-DEST[63:48]-SRC[63:48]\r\nDEST[79:64] <-DEST[79:64]-SRC[79:64]\r\nDEST[95:80] <-DEST[95:80]-SRC[95:80]\r\nDEST[111:96] <-DEST[111:96]-SRC[111:96]\r\nDEST[127:112] <-DEST[127:112]-SRC[127:112]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVPSUBD (VEX.256 encoded version)\r\nDEST[31:0] <-SRC1[31:0]-SRC2[31:0]\r\nDEST[63:32] <-SRC1[63:32]-SRC2[63:32]\r\nDEST[95:64] <-SRC1[95:64]-SRC2[95:64]\r\nDEST[127:96] <-SRC1[127:96]-SRC2[127:96]\r\nDEST[159:128] <-SRC1[159:128]-SRC2[159:128]\r\nDEST[191:160] <-SRC1[191:160]-SRC2[191:160]\r\nDEST[223:192] <-SRC1[223:192]-SRC2[223:192]\r\nDEST[255:224] <-SRC1[255:224]-SRC2[255:224]\r\nDEST[MAX_VL-1:256] <-0\r\n\r\nVPSUBD (VEX.128 encoded version)\r\nDEST[31:0] <-SRC1[31:0]-SRC2[31:0]\r\nDEST[63:32] <-SRC1[63:32]-SRC2[63:32]\r\nDEST[95:64] <-SRC1[95:64]-SRC2[95:64]\r\nDEST[127:96] <-SRC1[127:96]-SRC2[127:96]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nPSUBD (128-bit Legacy SSE version)\r\nDEST[31:0] <-DEST[31:0]-SRC[31:0]\r\nDEST[63:32] <-DEST[63:32]-SRC[63:32]\r\n\r\n\r\n\r\nDEST[95:64] <-DEST[95:64]-SRC[95:64]\r\nDEST[127:96] <-DEST[127:96]-SRC[127:96]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPSUBB __m512i _mm512_sub_epi8(__m512i a, __m512i b);\r\nVPSUBB __m512i _mm512_mask_sub_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);\r\nVPSUBB __m512i _mm512_maskz_sub_epi8( __mmask64 k, __m512i a, __m512i b);\r\nVPSUBB __m256i _mm256_mask_sub_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);\r\nVPSUBB __m256i _mm256_maskz_sub_epi8( __mmask32 k, __m256i a, __m256i b);\r\nVPSUBB __m128i _mm_mask_sub_epi8(__m128i s, __mmask16 k, __m128i a, __m128i b);\r\nVPSUBB __m128i _mm_maskz_sub_epi8( __mmask16 k, __m128i a, __m128i b);\r\nVPSUBW __m512i _mm512_sub_epi16(__m512i a, __m512i b);\r\nVPSUBW __m512i _mm512_mask_sub_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);\r\nVPSUBW __m512i _mm512_maskz_sub_epi16( __mmask32 k, __m512i a, __m512i b);\r\nVPSUBW __m256i _mm256_mask_sub_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);\r\nVPSUBW __m256i _mm256_maskz_sub_epi16( __mmask16 k, __m256i a, __m256i b);\r\nVPSUBW __m128i _mm_mask_sub_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPSUBW __m128i _mm_maskz_sub_epi16( __mmask8 k, __m128i a, __m128i b);\r\nVPSUBD __m512i _mm512_sub_epi32(__m512i a, __m512i b);\r\nVPSUBD __m512i _mm512_mask_sub_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);\r\nVPSUBD __m512i _mm512_maskz_sub_epi32( __mmask16 k, __m512i a, __m512i b);\r\nVPSUBD __m256i _mm256_mask_sub_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);\r\nVPSUBD __m256i _mm256_maskz_sub_epi32( __mmask8 k, __m256i a, __m256i b);\r\nVPSUBD __m128i _mm_mask_sub_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPSUBD __m128i _mm_maskz_sub_epi32( __mmask8 k, __m128i a, __m128i b);\r\nPSUBB:__m64 _mm_sub_pi8(__m64 m1, __m64 m2)\r\n(V)PSUBB:__m128i _mm_sub_epi8 ( __m128i a, __m128i b)\r\nVPSUBB:__m256i _mm256_sub_epi8 ( __m256i a, __m256i b)\r\nPSUBW:__m64 _mm_sub_pi16(__m64 m1, __m64 m2)\r\n(V)PSUBW:__m128i _mm_sub_epi16 ( __m128i a, __m128i b)\r\nVPSUBW:__m256i _mm256_sub_epi16 ( __m256i a, __m256i b)\r\nPSUBD:__m64 _mm_sub_pi32(__m64 m1, __m64 m2)\r\n(V)PSUBD:__m128i _mm_sub_epi32 ( __m128i a, __m128i b)\r\nVPSUBD:__m256i _mm256_sub_epi32 ( __m256i a, __m256i b)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nNumeric Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded VPSUBD, see Exceptions Type E4.\r\nEVEX-encoded VPSUBB/W, see Exceptions Type E4.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PSUBB"
},
{
"description": "-R:PSUBB",
"mnem": "PSUBD"
},
{
"description": "PSUBQ-Subtract Packed Quadword Integers\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F FB /r1 RM V/V SSE2 Subtract quadword integer in mm1 from mm2\r\nPSUBQ mm1, mm2/m64 /m64.\r\n\r\n66 0F FB /r RM V/V SSE2 Subtract packed quadword integers in xmm1\r\nPSUBQ xmm1, xmm2/m128 from xmm2 /m128.\r\n\r\nVEX.NDS.128.66.0F.WIG FB/r RVM V/V AVX Subtract packed quadword integers in\r\nVPSUBQ xmm1, xmm2, xmm3/m128 xmm3/m128 from xmm2.\r\n\r\nVEX.NDS.256.66.0F.WIG FB /r RVM V/V AVX2 Subtract packed quadword integers in\r\nVPSUBQ ymm1, ymm2, ymm3/m256 ymm3/m256 from ymm2.\r\n\r\nEVEX.NDS.128.66.0F.W1 FB /r FV V/V AVX512VL Subtract packed quadword integers in\r\nVPSUBQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst AVX512F xmm3/m128/m64bcst from xmm2 and store\r\n in xmm1 using writemask k1.\r\nEVEX.NDS.256.66.0F.W1 FB /r FV V/V AVX512VL Subtract packed quadword integers in\r\nVPSUBQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst AVX512F ymm3/m256/m64bcst from ymm2 and store\r\n in ymm1 using writemask k1.\r\nEVEX.NDS.512.66.0F.W1 FB/r FV V/V AVX512F Subtract packed quadword integers in\r\nVPSUBQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst zmm3/m512/m64bcst from zmm2 and store\r\n in zmm1 using writemask k1.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nSubtracts the second operand (source operand) from the first operand (destination operand) and stores the result\r\nin the destination operand. When packed quadword operands are used, a SIMD subtract is performed. When a\r\nquadword result is too large to be represented in 64 bits (overflow), the result is wrapped around and the low 64\r\nbits are written to the destination element (that is, the carry is ignored).\r\nNote that the (V)PSUBQ instruction can operate on either unsigned or signed (two's complement notation) inte-\r\ngers; however, it does not set bits in the EFLAGS register to indicate overflow and/or a carry. To prevent undetected\r\noverflow conditions, software must control the ranges of the values upon which it operates.\r\nIn 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to\r\naccess additional registers (XMM8-XMM15).\r\nLegacy SSE version 64-bit operand: The source operand can be a quadword integer stored in an MMX technology\r\nregister or a 64-bit memory location.\r\n128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first\r\nsource operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM desti-\r\nnation register remain unchanged.\r\n\r\n\r\n\r\n\r\n\r\nVEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first\r\nsource operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the destination YMM register\r\nare zeroed.\r\nVEX.256 encoded versions: The second source operand is an YMM register or an 256-bit memory location. The first\r\nsource operand and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding ZMM\r\nregister are zeroed.\r\nEVEX encoded VPSUBQ: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-\r\ntion or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The first source operand and\r\ndestination operands are ZMM/YMM/XMM registers. The destination is conditionally updated with writemask k1.\r\n\r\nOperation\r\nPSUBQ (with 64-Bit operands)\r\n DEST[63:0] <- DEST[63:0] - SRC[63:0];\r\n\r\nPSUBQ (with 128-Bit operands)\r\n DEST[63:0] <- DEST[63:0] - SRC[63:0];\r\n DEST[127:64] <- DEST[127:64] - SRC[127:64];\r\n\r\nVPSUBQ (VEX.128 encoded version)\r\nDEST[63:0] <- SRC1[63:0]-SRC2[63:0]\r\nDEST[127:64] <- SRC1[127:64]-SRC2[127:64]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPSUBQ (VEX.256 encoded version)\r\nDEST[63:0] <- SRC1[63:0]-SRC2[63:0]\r\nDEST[127:64] <- SRC1[127:64]-SRC2[127:64]\r\nDEST[191:128] <- SRC1[191:128]-SRC2[191:128]\r\nDEST[255:192] <- SRC1[255:192]-SRC2[255:192]\r\nDEST[VLMAX-1:256] <- 0\r\n\r\nVPSUBQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN DEST[i+63:i] <- SRC1[i+63:i] - SRC2[63:0]\r\n ELSE DEST[i+63:i] <- SRC1[i+63:i] - SRC2[i+63:i]\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPSUBQ __m512i _mm512_sub_epi64(__m512i a, __m512i b);\r\nVPSUBQ __m512i _mm512_mask_sub_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);\r\nVPSUBQ __m512i _mm512_maskz_sub_epi64( __mmask8 k, __m512i a, __m512i b);\r\nVPSUBQ __m256i _mm256_mask_sub_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);\r\n\r\n\r\n\r\nVPSUBQ __m256i _mm256_maskz_sub_epi64( __mmask8 k, __m256i a, __m256i b);\r\nVPSUBQ __m128i _mm_mask_sub_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPSUBQ __m128i _mm_maskz_sub_epi64( __mmask8 k, __m128i a, __m128i b);\r\nPSUBQ:__m64 _mm_sub_si64(__m64 m1, __m64 m2)\r\n(V)PSUBQ:__m128i _mm_sub_epi64(__m128i m1, __m128i m2)\r\nVPSUBQ:__m256i _mm256_sub_epi64(__m256i m1, __m256i m2)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nNumeric Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded VPSUBQ, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PSUBQ"
},
{
"description": "PSUBSB/PSUBSW-Subtract Packed Signed Integers with Signed Saturation\r\n Opcode/ Op/ 64/32 bit CPUID Description\r\n Instruction En Mode Feature\r\n Support Flag\r\n 0F E8 /r1 RM V/V MMX Subtract signed packed bytes in mm/m64 from\r\n PSUBSB mm, mm/m64 signed packed bytes in mm and saturate results.\r\n\r\n 66 0F E8 /r RM V/V SSE2 Subtract packed signed byte integers in\r\n PSUBSB xmm1, xmm2/m128 xmm2/m128 from packed signed byte integers\r\n in xmm1 and saturate results.\r\n 0F E9 /r1 RM V/V MMX Subtract signed packed words in mm/m64 from\r\n PSUBSW mm, mm/m64 signed packed words in mm and saturate\r\n results.\r\n 66 0F E9 /r RM V/V SSE2 Subtract packed signed word integers in\r\n PSUBSW xmm1, xmm2/m128 xmm2/m128 from packed signed word integers\r\n in xmm1 and saturate results.\r\n VEX.NDS.128.66.0F.WIG E8 /r RVM V/V AVX Subtract packed signed byte integers in\r\n VPSUBSB xmm1, xmm2, xmm3/m128 xmm3/m128 from packed signed byte integers\r\n in xmm2 and saturate results.\r\n VEX.NDS.128.66.0F.WIG E9 /r RVM V/V AVX Subtract packed signed word integers in\r\n VPSUBSW xmm1, xmm2, xmm3/m128 xmm3/m128 from packed signed word integers\r\n in xmm2 and saturate results.\r\n VEX.NDS.256.66.0F.WIG E8 /r RVM V/V AVX2 Subtract packed signed byte integers in\r\n VPSUBSB ymm1, ymm2, ymm3/m256 ymm3/m256 from packed signed byte integers\r\n in ymm2 and saturate results.\r\n VEX.NDS.256.66.0F.WIG E9 /r RVM V/V AVX2 Subtract packed signed word integers in\r\n VPSUBSW ymm1, ymm2, ymm3/m256 ymm3/m256 from packed signed word integers\r\n in ymm2 and saturate results.\r\n EVEX.NDS.128.66.0F.WIG E8 /r FVM V/V AVX512VL Subtract packed signed byte integers in\r\n VPSUBSB xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512BW xmm3/m128 from packed signed byte integers\r\n in xmm2 and saturate results and store in\r\n xmm1 using writemask k1.\r\n EVEX.NDS.256.66.0F.WIG E8 /r FVM V/V AVX512VL Subtract packed signed byte integers in\r\n VPSUBSB ymm1 {k1}{z}, ymm2, ymm3/m256 AVX512BW ymm3/m256 from packed signed byte integers\r\n in ymm2 and saturate results and store in\r\n ymm1 using writemask k1.\r\n EVEX.NDS.512.66.0F.WIG E8 /r FVM V/V AVX512BW Subtract packed signed byte integers in\r\n VPSUBSB zmm1 {k1}{z}, zmm2, zmm3/m512 zmm3/m512 from packed signed byte integers\r\n in zmm2 and saturate results and store in zmm1\r\n using writemask k1.\r\n EVEX.NDS.128.66.0F.WIG E9 /r FVM V/V AVX512VL Subtract packed signed word integers in\r\n VPSUBSW xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512BW xmm3/m128 from packed signed word integers\r\n in xmm2 and saturate results and store in\r\n xmm1 using writemask k1.\r\n EVEX.NDS.256.66.0F.WIG E9 /r FVM V/V AVX512VL Subtract packed signed word integers in\r\n VPSUBSW ymm1 {k1}{z}, ymm2, ymm3/m256 AVX512BW ymm3/m256 from packed signed word integers\r\n in ymm2 and saturate results and store in\r\n ymm1 using writemask k1.\r\n\r\n\r\n\r\n\r\n\r\nEVEX.NDS.512.66.0F.WIG E9 /r FVM V/V AVX512BW Subtract packed signed word integers in\r\nVPSUBSW zmm1 {k1}{z}, zmm2, zmm3/m512 zmm3/m512 from packed signed word integers\r\n in zmm2 and saturate results and store in zmm1\r\n using writemask k1.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nPerforms a SIMD subtract of the packed signed integers of the source operand (second operand) from the packed\r\nsigned integers of the destination operand (first operand), and stores the packed integer results in the destination\r\noperand. See Figure 9-4 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for an\r\nillustration of a SIMD operation. Overflow is handled with signed saturation, as described in the following para-\r\ngraphs.\r\nThe (V)PSUBSB instruction subtracts packed signed byte integers. When an individual byte result is beyond the\r\nrange of a signed byte integer (that is, greater than 7FH or less than 80H), the saturated value of 7FH or 80H,\r\nrespectively, is written to the destination operand.\r\nThe (V)PSUBSW instruction subtracts packed signed word integers. When an individual word result is beyond the\r\nrange of a signed word integer (that is, greater than 7FFFH or less than 8000H), the saturated value of 7FFFH or\r\n8000H, respectively, is written to the destination operand.\r\nIn 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to\r\naccess additional registers (XMM8-XMM15).\r\nLegacy SSE version 64-bit operand: The destination operand must be an MMX technology register and the source\r\noperand can be either an MMX technology register or a 64-bit memory location.\r\n128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first\r\nsource operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM desti-\r\nnation register remain unchanged.\r\nVEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first\r\nsource operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the destination YMM register\r\nare zeroed.\r\nVEX.256 encoded versions: The second source operand is an YMM register or an 256-bit memory location. The first\r\nsource operand and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding ZMM\r\nregister are zeroed.\r\nEVEX encoded version: The second source operand is an ZMM/YMM/XMM register or an 512/256/128-bit memory\r\nlocation. The first source operand and destination operands are ZMM/YMM/XMM registers. The destination is condi-\r\ntionally updated with writemask k1.\r\n\r\nOperation\r\nPSUBSB (with 64-bit operands)\r\n DEST[7:0] <- SaturateToSignedByte (DEST[7:0] - SRC (7:0]);\r\n (* Repeat subtract operation for 2nd through 7th bytes *)\r\n DEST[63:56] <- SaturateToSignedByte (DEST[63:56] - SRC[63:56] );\r\n\r\n\r\n\r\n\r\nPSUBSW (with 64-bit operands)\r\n DEST[15:0] <- SaturateToSignedWord (DEST[15:0] - SRC[15:0] );\r\n (* Repeat subtract operation for 2nd and 7th words *)\r\n DEST[63:48] <- SaturateToSignedWord (DEST[63:48] - SRC[63:48] );\r\n\r\nVPSUBSB (EVEX encoded versions)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 8;\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- SaturateToSignedByte (SRC1[i+7:i] - SRC2[i+7:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+7:i] <- 0;\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPSUBSW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- SaturateToSignedWord (SRC1[i+15:i] - SRC2[i+15:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] <- 0;\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0;\r\n\r\nVPSUBSB (VEX.256 encoded version)\r\nDEST[7:0] <- SaturateToSignedByte (SRC1[7:0] - SRC2[7:0]);\r\n(* Repeat subtract operation for 2nd through 31th bytes *)\r\nDEST[255:248] <- SaturateToSignedByte (SRC1[255:248] - SRC2[255:248]);\r\nDEST[MAX_VL-1:256] <-0;\r\n\r\nVPSUBSB (VEX.128 encoded version)\r\nDEST[7:0] <- SaturateToSignedByte (SRC1[7:0] - SRC2[7:0]);\r\n(* Repeat subtract operation for 2nd through 14th bytes *)\r\nDEST[127:120] <- SaturateToSignedByte (SRC1[127:120] - SRC2[127:120]);\r\nDEST[MAX_VL-1:128] <- 0;\r\n\r\nPSUBSB (128-bit Legacy SSE Version)\r\nDEST[7:0] <- SaturateToSignedByte (DEST[7:0] - SRC[7:0]);\r\n(* Repeat subtract operation for 2nd through 14th bytes *)\r\nDEST[127:120] <- SaturateToSignedByte (DEST[127:120] - SRC[127:120]);\r\nDEST[MAX_VL-1:128] (Unmodified);\r\n\r\n\r\n\r\nVPSUBSW (VEX.256 encoded version)\r\nDEST[15:0] <- SaturateToSignedWord (SRC1[15:0] - SRC2[15:0]);\r\n(* Repeat subtract operation for 2nd through 15th words *)\r\nDEST[255:240] <- SaturateToSignedWord (SRC1[255:240] - SRC2[255:240]);\r\nDEST[MAX_VL-1:256] <- 0;\r\n\r\nVPSUBSW (VEX.128 encoded version)\r\nDEST[15:0] <- SaturateToSignedWord (SRC1[15:0] - SRC2[15:0]);\r\n(* Repeat subtract operation for 2nd through 7th words *)\r\nDEST[127:112] <- SaturateToSignedWord (SRC1[127:112] - SRC2[127:112]);\r\nDEST[MAX_VL-1:128] <- 0;\r\n\r\nPSUBSW (128-bit Legacy SSE Version)\r\nDEST[15:0] <- SaturateToSignedWord (DEST[15:0] - SRC[15:0]);\r\n(* Repeat subtract operation for 2nd through 7th words *)\r\nDEST[127:112] <- SaturateToSignedWord (DEST[127:112] - SRC[127:112]);\r\nDEST[MAX_VL-1:128] (Unmodified);\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPSUBSB __m512i _mm512_subs_epi8(__m512i a, __m512i b);\r\nVPSUBSB __m512i _mm512_mask_subs_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);\r\nVPSUBSB __m512i _mm512_maskz_subs_epi8( __mmask64 k, __m512i a, __m512i b);\r\nVPSUBSB __m256i _mm256_mask_subs_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);\r\nVPSUBSB __m256i _mm256_maskz_subs_epi8( __mmask32 k, __m256i a, __m256i b);\r\nVPSUBSB __m128i _mm_mask_subs_epi8(__m128i s, __mmask16 k, __m128i a, __m128i b);\r\nVPSUBSB __m128i _mm_maskz_subs_epi8( __mmask16 k, __m128i a, __m128i b);\r\nVPSUBSW __m512i _mm512_subs_epi16(__m512i a, __m512i b);\r\nVPSUBSW __m512i _mm512_mask_subs_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);\r\nVPSUBSW __m512i _mm512_maskz_subs_epi16( __mmask32 k, __m512i a, __m512i b);\r\nVPSUBSW __m256i _mm256_mask_subs_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);\r\nVPSUBSW __m256i _mm256_maskz_subs_epi16( __mmask16 k, __m256i a, __m256i b);\r\nVPSUBSW __m128i _mm_mask_subs_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPSUBSW __m128i _mm_maskz_subs_epi16( __mmask8 k, __m128i a, __m128i b);\r\nPSUBSB:__m64 _mm_subs_pi8(__m64 m1, __m64 m2)\r\n(V)PSUBSB:__m128i _mm_subs_epi8(__m128i m1, __m128i m2)\r\nVPSUBSB:__m256i _mm256_subs_epi8(__m256i m1, __m256i m2)\r\nPSUBSW:__m64 _mm_subs_pi16(__m64 m1, __m64 m2)\r\n(V)PSUBSW:__m128i _mm_subs_epi16(__m128i m1, __m128i m2)\r\nVPSUBSW:__m256i _mm256_subs_epi16(__m256i m1, __m256i m2)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nNumeric Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PSUBSB"
},
{
"description": "-R:PSUBSB",
"mnem": "PSUBSW"
},
{
"description": "PSUBUSB/PSUBUSW-Subtract Packed Unsigned Integers with Unsigned Saturation\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F D8 /r1 RM V/V MMX Subtract unsigned packed bytes in mm/m64\r\nPSUBUSB mm, mm/m64 from unsigned packed bytes in mm and\r\n saturate result.\r\n66 0F D8 /r RM V/V SSE2 Subtract packed unsigned byte integers in\r\nPSUBUSB xmm1, xmm2/m128 xmm2/m128 from packed unsigned byte\r\n integers in xmm1 and saturate result.\r\n0F D9 /r1 RM V/V MMX Subtract unsigned packed words in mm/m64\r\nPSUBUSW mm, mm/m64 from unsigned packed words in mm and\r\n saturate result.\r\n66 0F D9 /r RM V/V SSE2 Subtract packed unsigned word integers in\r\nPSUBUSW xmm1, xmm2/m128 xmm2/m128 from packed unsigned word\r\n integers in xmm1 and saturate result.\r\nVEX.NDS.128.66.0F.WIG D8 /r RVM V/V AVX Subtract packed unsigned byte integers in\r\nVPSUBUSB xmm1, xmm2, xmm3/m128 xmm3/m128 from packed unsigned byte\r\n integers in xmm2 and saturate result.\r\nVEX.NDS.128.66.0F.WIG D9 /r RVM V/V AVX Subtract packed unsigned word integers in\r\nVPSUBUSW xmm1, xmm2, xmm3/m128 xmm3/m128 from packed unsigned word\r\n integers in xmm2 and saturate result.\r\nVEX.NDS.256.66.0F.WIG D8 /r RVM V/V AVX2 Subtract packed unsigned byte integers in\r\nVPSUBUSB ymm1, ymm2, ymm3/m256 ymm3/m256 from packed unsigned byte\r\n integers in ymm2 and saturate result.\r\nVEX.NDS.256.66.0F.WIG D9 /r RVM V/V AVX2 Subtract packed unsigned word integers in\r\nVPSUBUSW ymm1, ymm2, ymm3/m256 ymm3/m256 from packed unsigned word\r\n integers in ymm2 and saturate result.\r\nEVEX.NDS.128.66.0F.WIG D8 /r FVM V/V AVX512VL Subtract packed unsigned byte integers in\r\nVPSUBUSB xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512BW xmm3/m128 from packed unsigned byte\r\n integers in xmm2, saturate results and store\r\n in xmm1 using writemask k1.\r\nEVEX.NDS.256.66.0F.WIG D8 /r FVM V/V AVX512VL Subtract packed unsigned byte integers in\r\nVPSUBUSB ymm1 {k1}{z}, ymm2, ymm3/m256 AVX512BW ymm3/m256 from packed unsigned byte\r\n integers in ymm2, saturate results and store\r\n in ymm1 using writemask k1.\r\nEVEX.NDS.512.66.0F.WIG D8 /r FVM V/V AVX512BW Subtract packed unsigned byte integers in\r\nVPSUBUSB zmm1 {k1}{z}, zmm2, zmm3/m512 zmm3/m512 from packed unsigned byte\r\n integers in zmm2, saturate results and store\r\n in zmm1 using writemask k1.\r\nEVEX.NDS.128.66.0F.WIG D9 /r FVM V/V AVX512VL Subtract packed unsigned word integers in\r\nVPSUBUSW xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512BW xmm3/m128 from packed unsigned word\r\n integers in xmm2 and saturate results and\r\n store in xmm1 using writemask k1.\r\nEVEX.NDS.256.66.0F.WIG D9 /r FVM V/V AVX512VL Subtract packed unsigned word integers in\r\nVPSUBUSW ymm1 {k1}{z}, ymm2, ymm3/m256 AVX512BW ymm3/m256 from packed unsigned word\r\n integers in ymm2, saturate results and store\r\n in ymm1 using writemask k1.\r\n\r\n\r\n\r\n\r\n\r\nEVEX.NDS.512.66.0F.WIG D9 /r FVM V/V AVX512BW Subtract packed unsigned word integers in\r\nVPSUBUSW zmm1 {k1}{z}, zmm2, zmm3/m512 zmm3/m512 from packed unsigned word\r\n integers in zmm2, saturate results and store\r\n in zmm1 using writemask k1.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nPerforms a SIMD subtract of the packed unsigned integers of the source operand (second operand) from the\r\npacked unsigned integers of the destination operand (first operand), and stores the packed unsigned integer\r\nresults in the destination operand. See Figure 9-4 in the Intel 64 and IA-32 Architectures Software Developer's\r\nManual, Volume 1, for an illustration of a SIMD operation. Overflow is handled with unsigned saturation, as\r\ndescribed in the following paragraphs.\r\nThese instructions can operate on either 64-bit or 128-bit operands.\r\nThe (V)PSUBUSB instruction subtracts packed unsigned byte integers. When an individual byte result is less than\r\nzero, the saturated value of 00H is written to the destination operand.\r\nThe (V)PSUBUSW instruction subtracts packed unsigned word integers. When an individual word result is less than\r\nzero, the saturated value of 0000H is written to the destination operand.\r\nIn 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to\r\naccess additional registers (XMM8-XMM15).\r\nLegacy SSE version 64-bit operand: The destination operand must be an MMX technology register and the source\r\noperand can be either an MMX technology register or a 64-bit memory location.\r\n128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first\r\nsource operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM desti-\r\nnation register remain unchanged.\r\nVEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first\r\nsource operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the destination YMM register\r\nare zeroed.\r\nVEX.256 encoded versions: The second source operand is an YMM register or an 256-bit memory location. The first\r\nsource operand and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding ZMM\r\nregister are zeroed.\r\nEVEX encoded version: The second source operand is an ZMM/YMM/XMM register or an 512/256/128-bit memory\r\nlocation. The first source operand and destination operands are ZMM/YMM/XMM registers. The destination is condi-\r\ntionally updated with writemask k1.\r\n\r\nOperation\r\nPSUBUSB (with 64-bit operands)\r\n DEST[7:0] <- SaturateToUnsignedByte (DEST[7:0] - SRC (7:0] );\r\n (* Repeat add operation for 2nd through 7th bytes *)\r\n DEST[63:56] <- SaturateToUnsignedByte (DEST[63:56] - SRC[63:56];\r\n\r\n\r\n\r\n\r\nPSUBUSW (with 64-bit operands)\r\n DEST[15:0] <- SaturateToUnsignedWord (DEST[15:0] - SRC[15:0] );\r\n (* Repeat add operation for 2nd and 3rd words *)\r\n DEST[63:48] <- SaturateToUnsignedWord (DEST[63:48] - SRC[63:48] );\r\n\r\nVPSUBUSB (EVEX encoded versions)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 8;\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- SaturateToUnsignedByte (SRC1[i+7:i] - SRC2[i+7:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+7:i] <- 0;\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0;\r\n\r\nVPSUBUSW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16;\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- SaturateToUnsignedWord (SRC1[i+15:i] - SRC2[i+15:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] <- 0;\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0;\r\n\r\nVPSUBUSB (VEX.256 encoded version)\r\nDEST[7:0] <- SaturateToUnsignedByte (SRC1[7:0] - SRC2[7:0]);\r\n(* Repeat subtract operation for 2nd through 31st bytes *)\r\nDEST[255:148] <- SaturateToUnsignedByte (SRC1[255:248] - SRC2[255:248]);\r\nDEST[MAX_VL-1:256] <- 0;\r\n\r\nVPSUBUSB (VEX.128 encoded version)\r\nDEST[7:0] <- SaturateToUnsignedByte (SRC1[7:0] - SRC2[7:0]);\r\n(* Repeat subtract operation for 2nd through 14th bytes *)\r\nDEST[127:120] <- SaturateToUnsignedByte (SRC1[127:120] - SRC2[127:120]);\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nPSUBUSB (128-bit Legacy SSE Version)\r\nDEST[7:0] <- SaturateToUnsignedByte (DEST[7:0] - SRC[7:0]);\r\n(* Repeat subtract operation for 2nd through 14th bytes *)\r\nDEST[127:120] <- SaturateToUnsignedByte (DEST[127:120] - SRC[127:120]);\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\n\r\n\r\nVPSUBUSW (VEX.256 encoded version)\r\nDEST[15:0] <- SaturateToUnsignedWord (SRC1[15:0] - SRC2[15:0]);\r\n(* Repeat subtract operation for 2nd through 15th words *)\r\nDEST[255:240] <- SaturateToUnsignedWord (SRC1[255:240] - SRC2[255:240]);\r\nDEST[MAX_VL-1:256] <- 0;\r\n\r\nVPSUBUSW (VEX.128 encoded version)\r\nDEST[15:0] <- SaturateToUnsignedWord (SRC1[15:0] - SRC2[15:0]);\r\n(* Repeat subtract operation for 2nd through 7th words *)\r\nDEST[127:112] <- SaturateToUnsignedWord (SRC1[127:112] - SRC2[127:112]);\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nPSUBUSW (128-bit Legacy SSE Version)\r\nDEST[15:0] <- SaturateToUnsignedWord (DEST[15:0] - SRC[15:0]);\r\n(* Repeat subtract operation for 2nd through 7th words *)\r\nDEST[127:112] <- SaturateToUnsignedWord (DEST[127:112] - SRC[127:112]);\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPSUBUSB __m512i _mm512_subs_epu8(__m512i a, __m512i b);\r\nVPSUBUSB __m512i _mm512_mask_subs_epu8(__m512i s, __mmask64 k, __m512i a, __m512i b);\r\nVPSUBUSB __m512i _mm512_maskz_subs_epu8( __mmask64 k, __m512i a, __m512i b);\r\nVPSUBUSB __m256i _mm256_mask_subs_epu8(__m256i s, __mmask32 k, __m256i a, __m256i b);\r\nVPSUBUSB __m256i _mm256_maskz_subs_epu8( __mmask32 k, __m256i a, __m256i b);\r\nVPSUBUSB __m128i _mm_mask_subs_epu8(__m128i s, __mmask16 k, __m128i a, __m128i b);\r\nVPSUBUSB __m128i _mm_maskz_subs_epu8( __mmask16 k, __m128i a, __m128i b);\r\nVPSUBUSW __m512i _mm512_subs_epu16(__m512i a, __m512i b);\r\nVPSUBUSW __m512i _mm512_mask_subs_epu16(__m512i s, __mmask32 k, __m512i a, __m512i b);\r\nVPSUBUSW __m512i _mm512_maskz_subs_epu16( __mmask32 k, __m512i a, __m512i b);\r\nVPSUBUSW __m256i _mm256_mask_subs_epu16(__m256i s, __mmask16 k, __m256i a, __m256i b);\r\nVPSUBUSW __m256i _mm256_maskz_subs_epu16( __mmask16 k, __m256i a, __m256i b);\r\nVPSUBUSW __m128i _mm_mask_subs_epu16(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPSUBUSW __m128i _mm_maskz_subs_epu16( __mmask8 k, __m128i a, __m128i b);\r\nPSUBUSB:__m64 _mm_subs_pu8(__m64 m1, __m64 m2)\r\n(V)PSUBUSB:__m128i _mm_subs_epu8(__m128i m1, __m128i m2)\r\nVPSUBUSB:__m256i _mm256_subs_epu8(__m256i m1, __m256i m2)\r\nPSUBUSW:__m64 _mm_subs_pu16(__m64 m1, __m64 m2)\r\n(V)PSUBUSW:__m128i _mm_subs_epu16(__m128i m1, __m128i m2)\r\nVPSUBUSW:__m256i _mm256_subs_epu16(__m256i m1, __m256i m2)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nNumeric Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PSUBUSB"
},
{
"description": "-R:PSUBUSB",
"mnem": "PSUBUSW"
},
{
"description": "-R:PSUBB",
"mnem": "PSUBW"
},
{
"description": "PTEST- Logical Compare\r\n Opcode/ Op/ 64/32 bit CPUID Description\r\n Instruction En Mode Feature\r\n Support Flag\r\n 66 0F 38 17 /r RM V/V SSE4_1 Set ZF if xmm2/m128 AND xmm1 result is all\r\n PTEST xmm1, xmm2/m128 0s. Set CF if xmm2/m128 AND NOT xmm1\r\n result is all 0s.\r\n VEX.128.66.0F38.WIG 17 /r RM V/V AVX Set ZF and CF depending on bitwise AND and\r\n VPTEST xmm1, xmm2/m128 ANDN of sources.\r\n VEX.256.66.0F38.WIG 17 /r RM V/V AVX Set ZF and CF depending on bitwise AND and\r\n VPTEST ymm1, ymm2/m256 ANDN of sources.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r) ModRM:r/m (r) NA NA\r\n\r\n\r\nDescription\r\nPTEST and VPTEST set the ZF flag if all bits in the result are 0 of the bitwise AND of the first source operand (first\r\noperand) and the second source operand (second operand). VPTEST sets the CF flag if all bits in the result are 0 of\r\nthe bitwise AND of the second source operand (second operand) and the logical NOT of the destination operand.\r\nThe first source register is specified by the ModR/M reg field.\r\n128-bit versions: The first source register is an XMM register. The second source register can be an XMM register\r\nor a 128-bit memory location. The destination register is not modified.\r\nVEX.256 encoded version: The first source register is a YMM register. The second source register can be a YMM\r\nregister or a 256-bit memory location. The destination register is not modified.\r\nNote: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\nOperation\r\n(V)PTEST (128-bit version)\r\nIF (SRC[127:0] BITWISE AND DEST[127:0] = 0)\r\n THEN ZF <- 1;\r\n ELSE ZF <- 0;\r\nIF (SRC[127:0] BITWISE AND NOT DEST[127:0] = 0)\r\n THEN CF <- 1;\r\n ELSE CF <- 0;\r\nDEST (unmodified)\r\nAF <- OF <- PF <- SF <- 0;\r\n\r\nVPTEST (VEX.256 encoded version)\r\nIF (SRC[255:0] BITWISE AND DEST[255:0] = 0) THEN ZF <- 1;\r\n ELSE ZF <- 0;\r\nIF (SRC[255:0] BITWISE AND NOT DEST[255:0] = 0) THEN CF <- 1;\r\n ELSE CF <- 0;\r\nDEST (unmodified)\r\nAF <- OF <- PF <- SF <- 0;\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n\r\nPTEST\r\nint _mm_testz_si128 (__m128i s1, __m128i s2);\r\nint _mm_testc_si128 (__m128i s1, __m128i s2);\r\nint _mm_testnzc_si128 (__m128i s1, __m128i s2);\r\n\r\n\r\nVPTEST\r\nint _mm256_testz_si256 (__m256i s1, __m256i s2);\r\nint _mm256_testc_si256 (__m256i s1, __m256i s2);\r\nint _mm256_testnzc_si256 (__m256i s1, __m256i s2);\r\nint _mm_testz_si128 (__m128i s1, __m128i s2);\r\nint _mm_testc_si128 (__m128i s1, __m128i s2);\r\nint _mm_testnzc_si128 (__m128i s1, __m128i s2);\r\n\r\nFlags Affected\r\nThe 0F, AF, PF, SF flags are cleared and the ZF, CF flags are set according to the operation.\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4; additionally\r\n#UD If VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PTEST"
},
{
"description": "PTWRITE - Write Data to a Processor Trace Packet\r\n Opcode/ Op/ 64/32 bit CPUID Description\r\n Instruction En Mode Feature\r\n Support Flag\r\n F3 REX.W 0F AE /4 RM V/N.E Reads the data from r64/m64 to encod into a\r\n PTWRITE r64/m64 PTW packet if dependencies are met (see\r\n details below).\r\n F3 0F AE /4 RM V/V Reads the data from r32/m32 to encode into a\r\n PTWRITE r32/m32 PTW packet if dependencies are met (see\r\n details below).\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:rm (r) NA NA NA\r\n\r\n\r\nDescription\r\nThis instruction reads data in the source operand and sends it to the Intel Processor Trace hardware to be encoded\r\nin a PTW packet if TriggerEn, ContextEn, FilterEn, and PTWEn are all set to 1. For more details on these values, see\r\nIntel 64 and IA-32 Architectures Software Developer's Manual, Volume 3C, Section 36.2.3, \"Power Event\r\nTracing\". The size of data is 64-bit if using REX.W in 64-bit mode, otherwise 32-bits of data are copied from the\r\nsource operand.\r\nNote: The instruction will #UD if prefix 66H is used.\r\n\r\nOperation\r\nIF (IA32_RTIT_STATUS.TriggerEn & IA32_RTIT_STATUS.ContextEn & IA32_RTIT_STATUS.FilterEn & IA32_RTIT_CTL.PTWEn) = 1\r\n PTW.PayloadBytes <- Encoded payload size;\r\n PTW.IP <- IA32_RTIT_CTL.FUPonPTW\r\n IF IA32_RTIT_CTL.FUPonPTW = 1\r\n Insert FUP packet with IP of PTWRITE;\r\n FI;\r\nFI;\r\n\r\nFlags Affected\r\nNone.\r\n\r\nOther Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS or GS segments.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF (fault-code) For a page fault.\r\n#AC(0) If an unaligned memory reference is made while the current privilege level is 3 and alignment\r\n checking is enabled.\r\n#UD If CPUID.(EAX=14H, ECX=0):EBX.PTWRITE [Bit 4] = 0.\r\n If LOCK prefix is used.\r\n If 66H prefix is used.\r\n\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#GP(0) If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#UD If CPUID.(EAX=14H, ECX=0):EBX.PTWRITE [Bit 4] = 0.\r\n If LOCK prefix is used.\r\n If 66H prefix is used.\r\n\r\nVirtual 8086 Mode Exceptions\r\n#GP(0) If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF (fault-code) For a page fault.\r\n#AC(0) If an unaligned memory reference is made while alignment checking is enabled.\r\n#UD If CPUID.(EAX=14H, ECX=0):EBX.PTWRITE [Bit 4] = 0.\r\n If LOCK prefix is used.\r\n If 66H prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in Protected Mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#PF (fault-code) For a page fault.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If CPUID.(EAX=14H, ECX=0):EBX.PTWRITE [Bit 4] = 0.\r\n If LOCK prefix is used.\r\n If 66H prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PTWRITE"
},
{
"description": "PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ- Unpack High Data\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F 68 /r1 RM V/V MMX Unpack and interleave high-order bytes from\r\nPUNPCKHBW mm, mm/m64 mm and mm/m64 into mm.\r\n\r\n66 0F 68 /r RM V/V SSE2 Unpack and interleave high-order bytes from\r\nPUNPCKHBW xmm1, xmm2/m128 xmm1 and xmm2/m128 into xmm1.\r\n\r\n0F 69 /r1 RM V/V MMX Unpack and interleave high-order words from\r\nPUNPCKHWD mm, mm/m64 mm and mm/m64 into mm.\r\n\r\n66 0F 69 /r RM V/V SSE2 Unpack and interleave high-order words from\r\nPUNPCKHWD xmm1, xmm2/m128 xmm1 and xmm2/m128 into xmm1.\r\n\r\n0F 6A /r1 RM V/V MMX Unpack and interleave high-order\r\nPUNPCKHDQ mm, mm/m64 doublewords from mm and mm/m64 into mm.\r\n\r\n66 0F 6A /r RM V/V SSE2 Unpack and interleave high-order\r\nPUNPCKHDQ xmm1, xmm2/m128 doublewords from xmm1 and xmm2/m128\r\n into xmm1.\r\n66 0F 6D /r RM V/V SSE2 Unpack and interleave high-order quadwords\r\nPUNPCKHQDQ xmm1, xmm2/m128 from xmm1 and xmm2/m128 into xmm1.\r\n\r\nVEX.NDS.128.66.0F.WIG 68/r RVM V/V AVX Interleave high-order bytes from xmm2 and\r\nVPUNPCKHBW xmm1,xmm2, xmm3/m128 xmm3/m128 into xmm1.\r\n\r\nVEX.NDS.128.66.0F.WIG 69/r RVM V/V AVX Interleave high-order words from xmm2 and\r\nVPUNPCKHWD xmm1,xmm2, xmm3/m128 xmm3/m128 into xmm1.\r\n\r\nVEX.NDS.128.66.0F.WIG 6A/r RVM V/V AVX Interleave high-order doublewords from\r\nVPUNPCKHDQ xmm1, xmm2, xmm3/m128 xmm2 and xmm3/m128 into xmm1.\r\n\r\nVEX.NDS.128.66.0F.WIG 6D/r RVM V/V AVX Interleave high-order quadword from xmm2\r\nVPUNPCKHQDQ xmm1, xmm2, xmm3/m128 and xmm3/m128 into xmm1 register.\r\nVEX.NDS.256.66.0F.WIG 68 /r RVM V/V AVX2 Interleave high-order bytes from ymm2 and\r\nVPUNPCKHBW ymm1, ymm2, ymm3/m256 ymm3/m256 into ymm1 register.\r\nVEX.NDS.256.66.0F.WIG 69 /r RVM V/V AVX2 Interleave high-order words from ymm2 and\r\nVPUNPCKHWD ymm1, ymm2, ymm3/m256 ymm3/m256 into ymm1 register.\r\nVEX.NDS.256.66.0F.WIG 6A /r RVM V/V AVX2 Interleave high-order doublewords from\r\nVPUNPCKHDQ ymm1, ymm2, ymm3/m256 ymm2 and ymm3/m256 into ymm1 register.\r\nVEX.NDS.256.66.0F.WIG 6D /r RVM V/V AVX2 Interleave high-order quadword from ymm2\r\nVPUNPCKHQDQ ymm1, ymm2, ymm3/m256 and ymm3/m256 into ymm1 register.\r\nEVEX.NDS.128.66.0F.WIG 68 /r FVM V/V AVX512VL Interleave high-order bytes from xmm2 and\r\nVPUNPCKHBW xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512BW xmm3/m128 into xmm1 register using k1\r\n write mask.\r\n\r\nEVEX.NDS.128.66.0F.WIG 69 /r FVM V/V AVX512VL Interleave high-order words from xmm2 and\r\nVPUNPCKHWD xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512BW xmm3/m128 into xmm1 register using k1\r\n write mask.\r\nEVEX.NDS.128.66.0F.W0 6A /r FV V/V AVX512VL Interleave high-order doublewords from\r\nVPUNPCKHDQ xmm1 {k1}{z}, xmm2, AVX512F xmm2 and xmm3/m128/m32bcst into xmm1\r\nxmm3/m128/m32bcst register using k1 write mask.\r\nEVEX.NDS.128.66.0F.W1 6D /r FV V/V AVX512VL Interleave high-order quadword from xmm2\r\nVPUNPCKHQDQ xmm1 {k1}{z}, xmm2, AVX512F and xmm3/m128/m64bcst into xmm1\r\nxmm3/m128/m64bcst register using k1 write mask.\r\n\r\n\r\n\r\n\r\n\r\nEVEX.NDS.256.66.0F.WIG 68 /r FVM V/V AVX512VL Interleave high-order bytes from ymm2 and\r\nVPUNPCKHBW ymm1 {k1}{z}, ymm2, ymm3/m256 AVX512BW ymm3/m256 into ymm1 register using k1\r\n write mask.\r\nEVEX.NDS.256.66.0F.WIG 69 /r FVM V/V AVX512VL Interleave high-order words from ymm2 and\r\nVPUNPCKHWD ymm1 {k1}{z}, ymm2, ymm3/m256 AVX512BW ymm3/m256 into ymm1 register using k1\r\n write mask.\r\nEVEX.NDS.256.66.0F.W0 6A /r FV V/V AVX512VL Interleave high-order doublewords from\r\nVPUNPCKHDQ ymm1 {k1}{z}, ymm2, AVX512F ymm2 and ymm3/m256/m32bcst into ymm1\r\nymm3/m256/m32bcst register using k1 write mask.\r\n\r\nEVEX.NDS.256.66.0F.W1 6D /r FV V/V AVX512VL Interleave high-order quadword from ymm2\r\nVPUNPCKHQDQ ymm1 {k1}{z}, ymm2, AVX512F and ymm3/m256/m64bcst into ymm1\r\nymm3/m256/m64bcst register using k1 write mask.\r\n\r\nEVEX.NDS.512.66.0F.WIG 68/r FVM V/V AVX512BW Interleave high-order bytes from zmm2 and\r\nVPUNPCKHBW zmm1 {k1}{z}, zmm2, zmm3/m512 zmm3/m512 into zmm1 register.\r\n\r\nEVEX.NDS.512.66.0F.WIG 69/r FVM V/V AVX512BW Interleave high-order words from zmm2 and\r\nVPUNPCKHWD zmm1 {k1}{z}, zmm2, zmm3/m512 zmm3/m512 into zmm1 register.\r\n\r\nEVEX.NDS.512.66.0F.W0 6A /r FV V/V AVX512F Interleave high-order doublewords from\r\nVPUNPCKHDQ zmm1 {k1}{z}, zmm2, zmm2 and zmm3/m512/m32bcst into zmm1\r\nzmm3/m512/m32bcst register using k1 write mask.\r\nEVEX.NDS.512.66.0F.W1 6D /r FV V/V AVX512F Interleave high-order quadword from zmm2\r\nVPUNPCKHQDQ zmm1 {k1}{z}, zmm2, and zmm3/m512/m64bcst into zmm1 register\r\nzmm3/m512/m64bcst using k1 write mask.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nUnpacks and interleaves the high-order data elements (bytes, words, doublewords, or quadwords) of the destina-\r\ntion operand (first operand) and source operand (second operand) into the destination operand. Figure 4-20 shows\r\nthe unpack operation for bytes in 64-bit operands. The low-order data elements are ignored.\r\n\r\n\r\n\r\n\r\n\r\n SRC Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X7 X6 X5 X4 X3 X2 X1 X0 DEST\r\n\r\n\r\n\r\n\r\n DEST Y7 X7 Y6 X6 Y5 X5 Y4 X4\r\n\r\n\r\n Figure 4-20. PUNPCKHBW Instruction Operation Using 64-bit Operands\r\n\r\n\r\n\r\n\r\n 255 31 0 255 31 0\r\n\r\n SRC Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X7 X6 X5 X4 X3 X2 X1 X0\r\n\r\n\r\n\r\n\r\n 255 0\r\n\r\n DEST Y7 X7 Y6 X6 Y3 X3 Y2 X2\r\n\r\n\r\n Figure 4-21. 256-bit VPUNPCKHDQ Instruction Operation\r\n\r\nWhen the source data comes from a 64-bit memory operand, the full 64-bit operand is accessed from memory, but\r\nthe instruction uses only the high-order 32 bits. When the source data comes from a 128-bit memory operand, an\r\nimplementation may fetch only the appropriate 64 bits; however, alignment to a 16-byte boundary and normal\r\nsegment checking will still be enforced.\r\nThe (V)PUNPCKHBW instruction interleaves the high-order bytes of the source and destination operands, the\r\n(V)PUNPCKHWD instruction interleaves the high-order words of the source and destination operands, the\r\n(V)PUNPCKHDQ instruction interleaves the high-order doubleword (or doublewords) of the source and destination\r\noperands, and the (V)PUNPCKHQDQ instruction interleaves the high-order quadwords of the source and destina-\r\ntion operands.\r\nThese instructions can be used to convert bytes to words, words to doublewords, doublewords to quadwords, and\r\nquadwords to double quadwords, respectively, by placing all 0s in the source operand. Here, if the source operand\r\ncontains all 0s, the result (stored in the destination operand) contains zero extensions of the high-order data\r\nelements from the original value in the destination operand. For example, with the (V)PUNPCKHBW instruction the\r\nhigh-order bytes are zero extended (that is, unpacked into unsigned word integers), and with the (V)PUNPCKHWD\r\ninstruction, the high-order words are zero extended (unpacked into unsigned doubleword integers).\r\nIn 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to\r\naccess additional registers (XMM8-XMM15).\r\nLegacy SSE versions 64-bit operand: The source operand can be an MMX technology register or a 64-bit memory\r\nlocation. The destination operand is an MMX technology register.\r\n128-bit Legacy SSE versions: The second source operand is an XMM register or a 128-bit memory location. The\r\nfirst source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM\r\ndestination register remain unchanged.\r\nVEX.128 encoded versions: The second source operand is an XMM register or a 128-bit memory location. The first\r\nsource operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the destination YMM register\r\nare zeroed.\r\nVEX.256 encoded version: The second source operand is an YMM register or an 256-bit memory location. The first\r\nsource operand and destination operands are YMM registers.\r\n\r\n\r\n\r\n\r\nEVEX encoded VPUNPCKHDQ/QDQ: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit\r\nmemory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The first source\r\noperand and destination operands are ZMM/YMM/XMM registers. The destination is conditionally updated with\r\nwritemask k1.\r\nEVEX encoded VPUNPCKHWD/BW: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit\r\nmemory location. The first source operand and destination operands are ZMM/YMM/XMM registers. The destination\r\nis conditionally updated with writemask k1.\r\n\r\nOperation\r\nPUNPCKHBW instruction with 64-bit operands:\r\n DEST[7:0] <- DEST[39:32];\r\n DEST[15:8] <- SRC[39:32];\r\n DEST[23:16] <- DEST[47:40];\r\n DEST[31:24] <- SRC[47:40];\r\n DEST[39:32] <- DEST[55:48];\r\n DEST[47:40] <- SRC[55:48];\r\n DEST[55:48] <- DEST[63:56];\r\n DEST[63:56] <- SRC[63:56];\r\n\r\nPUNPCKHW instruction with 64-bit operands:\r\n DEST[15:0] <- DEST[47:32];\r\n DEST[31:16] <- SRC[47:32];\r\n DEST[47:32] <- DEST[63:48];\r\n DEST[63:48] <- SRC[63:48];\r\n\r\nPUNPCKHDQ instruction with 64-bit operands:\r\n DEST[31:0] <- DEST[63:32];\r\n DEST[63:32] <- SRC[63:32];\r\n\r\nINTERLEAVE_HIGH_BYTES_512b (SRC1, SRC2)\r\nTMP_DEST[255:0] <- INTERLEAVE_HIGH_BYTES_256b(SRC1[255:0], SRC[255:0])\r\nTMP_DEST[511:256] <- INTERLEAVE_HIGH_BYTES_256b(SRC1[511:256], SRC[511:256])\r\n\r\nINTERLEAVE_HIGH_BYTES_256b (SRC1, SRC2)\r\nDEST[7:0] <- SRC1[71:64]\r\nDEST[15:8] <- SRC2[71:64]\r\nDEST[23:16] <- SRC1[79:72]\r\nDEST[31:24] <- SRC2[79:72]\r\nDEST[39:32] <- SRC1[87:80]\r\nDEST[47:40] <- SRC2[87:80]\r\nDEST[55:48] <- SRC1[95:88]\r\nDEST[63:56] <- SRC2[95:88]\r\nDEST[71:64] <- SRC1[103:96]\r\nDEST[79:72] <- SRC2[103:96]\r\nDEST[87:80] <- SRC1[111:104]\r\nDEST[95:88] <- SRC2[111:104]\r\nDEST[103:96] <- SRC1[119:112]\r\nDEST[111:104] <- SRC2[119:112]\r\nDEST[119:112] <- SRC1[127:120]\r\nDEST[127:120] <- SRC2[127:120]\r\nDEST[135:128] <- SRC1[199:192]\r\nDEST[143:136] <- SRC2[199:192]\r\nDEST[151:144] <- SRC1[207:200]\r\nDEST[159:152] <- SRC2[207:200]\r\n\r\n\r\n\r\nDEST[167:160] <- SRC1[215:208]\r\nDEST[175:168] <- SRC2[215:208]\r\nDEST[183:176] <- SRC1[223:216]\r\nDEST[191:184] <- SRC2[223:216]\r\nDEST[199:192] <- SRC1[231:224]\r\nDEST[207:200] <- SRC2[231:224]\r\nDEST[215:208] <- SRC1[239:232]\r\nDEST[223:216] <- SRC2[239:232]\r\nDEST[231:224] <- SRC1[247:240]\r\nDEST[239:232] <- SRC2[247:240]\r\nDEST[247:240] <- SRC1[255:248]\r\nDEST[255:248] <- SRC2[255:248]\r\n\r\nINTERLEAVE_HIGH_BYTES (SRC1, SRC2)\r\nDEST[7:0] <- SRC1[71:64]\r\nDEST[15:8] <- SRC2[71:64]\r\nDEST[23:16] <- SRC1[79:72]\r\nDEST[31:24] <- SRC2[79:72]\r\nDEST[39:32] <- SRC1[87:80]\r\nDEST[47:40] <- SRC2[87:80]\r\nDEST[55:48] <- SRC1[95:88]\r\nDEST[63:56] <- SRC2[95:88]\r\nDEST[71:64] <- SRC1[103:96]\r\nDEST[79:72] <- SRC2[103:96]\r\nDEST[87:80] <- SRC1[111:104]\r\nDEST[95:88] <- SRC2[111:104]\r\nDEST[103:96] <- SRC1[119:112]\r\nDEST[111:104] <- SRC2[119:112]\r\nDEST[119:112] <- SRC1[127:120]\r\nDEST[127:120] <- SRC2[127:120]\r\n\r\nINTERLEAVE_HIGH_WORDS_512b (SRC1, SRC2)\r\nTMP_DEST[255:0] <- INTERLEAVE_HIGH_WORDS_256b(SRC1[255:0], SRC[255:0])\r\nTMP_DEST[511:256] <- INTERLEAVE_HIGH_WORDS_256b(SRC1[511:256], SRC[511:256])\r\n\r\nINTERLEAVE_HIGH_WORDS_256b(SRC1, SRC2)\r\nDEST[15:0] <- SRC1[79:64]\r\nDEST[31:16] <- SRC2[79:64]\r\nDEST[47:32] <- SRC1[95:80]\r\nDEST[63:48] <- SRC2[95:80]\r\nDEST[79:64] <- SRC1[111:96]\r\nDEST[95:80] <- SRC2[111:96]\r\nDEST[111:96] <- SRC1[127:112]\r\nDEST[127:112] <- SRC2[127:112]\r\nDEST[143:128] <- SRC1[207:192]\r\nDEST[159:144] <- SRC2[207:192]\r\nDEST[175:160] <- SRC1[223:208]\r\nDEST[191:176] <- SRC2[223:208]\r\nDEST[207:192] <- SRC1[239:224]\r\nDEST[223:208] <- SRC2[239:224]\r\nDEST[239:224] <- SRC1[255:240]\r\nDEST[255:240] <- SRC2[255:240]\r\n\r\nINTERLEAVE_HIGH_WORDS (SRC1, SRC2)\r\n\r\n\r\n\r\nDEST[15:0] <- SRC1[79:64]\r\nDEST[31:16] <- SRC2[79:64]\r\nDEST[47:32] <- SRC1[95:80]\r\nDEST[63:48] <- SRC2[95:80]\r\nDEST[79:64] <- SRC1[111:96]\r\nDEST[95:80] <- SRC2[111:96]\r\nDEST[111:96] <- SRC1[127:112]\r\nDEST[127:112] <- SRC2[127:112]\r\n\r\nINTERLEAVE_HIGH_DWORDS_512b (SRC1, SRC2)\r\nTMP_DEST[255:0] <- INTERLEAVE_HIGH_DWORDS_256b(SRC1[255:0], SRC2[255:0])\r\nTMP_DEST[511:256] <- INTERLEAVE_HIGH_DWORDS_256b(SRC1[511:256], SRC2[511:256])\r\n\r\nINTERLEAVE_HIGH_DWORDS_256b(SRC1, SRC2)\r\nDEST[31:0] <- SRC1[95:64]\r\nDEST[63:32] <- SRC2[95:64]\r\nDEST[95:64] <- SRC1[127:96]\r\nDEST[127:96] <- SRC2[127:96]\r\nDEST[159:128] <- SRC1[223:192]\r\nDEST[191:160] <- SRC2[223:192]\r\nDEST[223:192] <- SRC1[255:224]\r\nDEST[255:224] <- SRC2[255:224]\r\n\r\nINTERLEAVE_HIGH_DWORDS(SRC1, SRC2)\r\nDEST[31:0] <- SRC1[95:64]\r\nDEST[63:32] <- SRC2[95:64]\r\nDEST[95:64] <- SRC1[127:96]\r\nDEST[127:96] <- SRC2[127:96]\r\n\r\nINTERLEAVE_HIGH_QWORDS_512b (SRC1, SRC2)\r\nTMP_DEST[255:0] <- INTERLEAVE_HIGH_QWORDS_256b(SRC1[255:0], SRC2[255:0])\r\nTMP_DEST[511:256] <- INTERLEAVE_HIGH_QWORDS_256b(SRC1[511:256], SRC2[511:256])\r\n\r\nINTERLEAVE_HIGH_QWORDS_256b(SRC1, SRC2)\r\nDEST[63:0] <- SRC1[127:64]\r\nDEST[127:64] <- SRC2[127:64]\r\nDEST[191:128] <- SRC1[255:192]\r\nDEST[255:192] <- SRC2[255:192]\r\n\r\nINTERLEAVE_HIGH_QWORDS(SRC1, SRC2)\r\nDEST[63:0] <- SRC1[127:64]\r\nDEST[127:64] <- SRC2[127:64]\r\n\r\nPUNPCKHBW (128-bit Legacy SSE Version)\r\nDEST[127:0] <-INTERLEAVE_HIGH_BYTES(DEST, SRC)\r\nDEST[255:127] (Unmodified)\r\nVPUNPCKHBW (VEX.128 encoded version)\r\nDEST[127:0] <-INTERLEAVE_HIGH_BYTES(SRC1, SRC2)\r\nDEST[511:127] <-0\r\n\r\nVPUNPCKHBW (VEX.256 encoded version)\r\nDEST[255:0] <-INTERLEAVE_HIGH_BYTES_256b(SRC1, SRC2)\r\nDEST[MAX_VL-1:256] <-0\r\n\r\n\r\n\r\n\r\nVPUNPCKHBW (EVEX encoded versions)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\nIF VL = 128\r\n TMP_DEST[VL-1:0] <- INTERLEAVE_HIGH_BYTES(SRC1[VL-1:0], SRC2[VL-1:0])\r\nFI;\r\nIF VL = 256\r\n TMP_DEST[VL-1:0] <- INTERLEAVE_HIGH_BYTES_256b(SRC1[VL-1:0], SRC2[VL-1:0])\r\nFI;\r\nIF VL = 512\r\n TMP_DEST[VL-1:0] <- INTERLEAVE_HIGH_BYTES_512b(SRC1[VL-1:0], SRC2[VL-1:0])\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i<-j*8\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- TMP_DEST[i+7:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+7:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nPUNPCKHWD (128-bit Legacy SSE Version)\r\nDEST[127:0] <-INTERLEAVE_HIGH_WORDS(DEST, SRC)\r\nDEST[255:127] (Unmodified)\r\n\r\nVPUNPCKHWD (VEX.128 encoded version)\r\nDEST[127:0] <-INTERLEAVE_HIGH_WORDS(SRC1, SRC2)\r\nDEST[511:127] <-0\r\n\r\nVPUNPCKHWD (VEX.256 encoded version)\r\nDEST[255:0] <-INTERLEAVE_HIGH_WORDS_256b(SRC1, SRC2)\r\nDEST[MAX_VL-1:256] <-0\r\n\r\nVPUNPCKHWD (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nIF VL = 128\r\n TMP_DEST[VL-1:0] <- INTERLEAVE_HIGH_WORDS(SRC1[VL-1:0], SRC2[VL-1:0])\r\nFI;\r\nIF VL = 256\r\n TMP_DEST[VL-1:0] <- INTERLEAVE_HIGH_WORDS_256b(SRC1[VL-1:0], SRC2[VL-1:0])\r\nFI;\r\nIF VL = 512\r\n TMP_DEST[VL-1:0] <- INTERLEAVE_HIGH_WORDS_512b(SRC1[VL-1:0], SRC2[VL-1:0])\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- TMP_DEST[i+15:i]\r\n\r\n\r\n\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nPUNPCKHDQ (128-bit Legacy SSE Version)\r\nDEST[127:0] <-INTERLEAVE_HIGH_DWORDS(DEST, SRC)\r\nDEST[255:127] (Unmodified)\r\n\r\nVPUNPCKHDQ (VEX.128 encoded version)\r\nDEST[127:0] <-INTERLEAVE_HIGH_DWORDS(SRC1, SRC2)\r\nDEST[511:127] <-0\r\n\r\nVPUNPCKHDQ (VEX.256 encoded version)\r\nDEST[255:0] <-INTERLEAVE_HIGH_DWORDS_256b(SRC1, SRC2)\r\nDEST[MAX_VL-1:256] <-0\r\n\r\nVPUNPCKHDQ (EVEX.512 encoded version)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN TMP_SRC2[i+31:i] <- SRC2[31:0]\r\n ELSE TMP_SRC2[i+31:i] <- SRC2[i+31:i]\r\n FI;\r\nENDFOR;\r\nIF VL = 128\r\n TMP_DEST[VL-1:0] <- INTERLEAVE_HIGH_DWORDS(SRC1[VL-1:0], TMP_SRC2[VL-1:0])\r\nFI;\r\nIF VL = 256\r\n TMP_DEST[VL-1:0] <- INTERLEAVE_HIGH_DWORDS_256b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])\r\nFI;\r\nIF VL = 512\r\n TMP_DEST[VL-1:0] <- INTERLEAVE_HIGH_DWORDS_512b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_DEST[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\nPUNPCKHQDQ (128-bit Legacy SSE Version)\r\nDEST[127:0] <-INTERLEAVE_HIGH_QWORDS(DEST, SRC)\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVPUNPCKHQDQ (VEX.128 encoded version)\r\nDEST[127:0] <-INTERLEAVE_HIGH_QWORDS(SRC1, SRC2)\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVPUNPCKHQDQ (VEX.256 encoded version)\r\nDEST[255:0] <-INTERLEAVE_HIGH_QWORDS_256b(SRC1, SRC2)\r\nDEST[MAX_VL-1:256] <-0\r\n\r\nVPUNPCKHQDQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN TMP_SRC2[i+63:i] <- SRC2[63:0]\r\n ELSE TMP_SRC2[i+63:i] <- SRC2[i+63:i]\r\n FI;\r\nENDFOR;\r\nIF VL = 128\r\n TMP_DEST[VL-1:0] <- INTERLEAVE_HIGH_QWORDS(SRC1[VL-1:0], TMP_SRC2[VL-1:0])\r\nFI;\r\nIF VL = 256\r\n TMP_DEST[VL-1:0] <- INTERLEAVE_HIGH_QWORDS_256b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])\r\nFI;\r\nIF VL = 512\r\n TMP_DEST[VL-1:0] <- INTERLEAVE_HIGH_QWORDS_512b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPUNPCKHBW __m512i _mm512_unpackhi_epi8(__m512i a, __m512i b);\r\nVPUNPCKHBW __m512i _mm512_mask_unpackhi_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);\r\nVPUNPCKHBW __m512i _mm512_maskz_unpackhi_epi8( __mmask64 k, __m512i a, __m512i b);\r\nVPUNPCKHBW __m256i _mm256_mask_unpackhi_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);\r\nVPUNPCKHBW __m256i _mm256_maskz_unpackhi_epi8( __mmask32 k, __m256i a, __m256i b);\r\nVPUNPCKHBW __m128i _mm_mask_unpackhi_epi8(v s, __mmask16 k, __m128i a, __m128i b);\r\nVPUNPCKHBW __m128i _mm_maskz_unpackhi_epi8( __mmask16 k, __m128i a, __m128i b);\r\n\r\n\r\n\r\nVPUNPCKHWD __m512i _mm512_unpackhi_epi16(__m512i a, __m512i b);\r\nVPUNPCKHWD __m512i _mm512_mask_unpackhi_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);\r\nVPUNPCKHWD __m512i _mm512_maskz_unpackhi_epi16( __mmask32 k, __m512i a, __m512i b);\r\nVPUNPCKHWD __m256i _mm256_mask_unpackhi_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);\r\nVPUNPCKHWD __m256i _mm256_maskz_unpackhi_epi16( __mmask16 k, __m256i a, __m256i b);\r\nVPUNPCKHWD __m128i _mm_mask_unpackhi_epi16(v s, __mmask8 k, __m128i a, __m128i b);\r\nVPUNPCKHWD __m128i _mm_maskz_unpackhi_epi16( __mmask8 k, __m128i a, __m128i b);\r\nVPUNPCKHDQ __m512i _mm512_unpackhi_epi32(__m512i a, __m512i b);\r\nVPUNPCKHDQ __m512i _mm512_mask_unpackhi_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);\r\nVPUNPCKHDQ __m512i _mm512_maskz_unpackhi_epi32( __mmask16 k, __m512i a, __m512i b);\r\nVPUNPCKHDQ __m256i _mm256_mask_unpackhi_epi32(__m512i s, __mmask8 k, __m512i a, __m512i b);\r\nVPUNPCKHDQ __m256i _mm256_maskz_unpackhi_epi32( __mmask8 k, __m512i a, __m512i b);\r\nVPUNPCKHDQ __m128i _mm_mask_unpackhi_epi32(__m512i s, __mmask8 k, __m512i a, __m512i b);\r\nVPUNPCKHDQ __m128i _mm_maskz_unpackhi_epi32( __mmask8 k, __m512i a, __m512i b);\r\nVPUNPCKHQDQ __m512i _mm512_unpackhi_epi64(__m512i a, __m512i b);\r\nVPUNPCKHQDQ __m512i _mm512_mask_unpackhi_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);\r\nVPUNPCKHQDQ __m512i _mm512_maskz_unpackhi_epi64( __mmask8 k, __m512i a, __m512i b);\r\nVPUNPCKHQDQ __m256i _mm256_mask_unpackhi_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);\r\nVPUNPCKHQDQ __m256i _mm256_maskz_unpackhi_epi64( __mmask8 k, __m512i a, __m512i b);\r\nVPUNPCKHQDQ __m128i _mm_mask_unpackhi_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);\r\nVPUNPCKHQDQ __m128i _mm_maskz_unpackhi_epi64( __mmask8 k, __m512i a, __m512i b);\r\nPUNPCKHBW:__m64 _mm_unpackhi_pi8(__m64 m1, __m64 m2)\r\n(V)PUNPCKHBW:__m128i _mm_unpackhi_epi8(__m128i m1, __m128i m2)\r\nVPUNPCKHBW:__m256i _mm256_unpackhi_epi8(__m256i m1, __m256i m2)\r\nPUNPCKHWD:__m64 _mm_unpackhi_pi16(__m64 m1,__m64 m2)\r\n(V)PUNPCKHWD:__m128i _mm_unpackhi_epi16(__m128i m1,__m128i m2)\r\nVPUNPCKHWD:__m256i _mm256_unpackhi_epi16(__m256i m1,__m256i m2)\r\nPUNPCKHDQ:__m64 _mm_unpackhi_pi32(__m64 m1, __m64 m2)\r\n(V)PUNPCKHDQ:__m128i _mm_unpackhi_epi32(__m128i m1, __m128i m2)\r\nVPUNPCKHDQ:__m256i _mm256_unpackhi_epi32(__m256i m1, __m256i m2)\r\n(V)PUNPCKHQDQ:__m128i _mm_unpackhi_epi64 ( __m128i a, __m128i b)\r\nVPUNPCKHQDQ:__m256i _mm256_unpackhi_epi64 ( __m256i a, __m256i b)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nNumeric Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded VPUNPCKHQDQ/QDQ, see Exceptions Type E4NF.\r\nEVEX-encoded VPUNPCKHBW/WD, see Exceptions Type E4NF.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PUNPCKHBW"
},
{
"description": "-R:PUNPCKHBW",
"mnem": "PUNPCKHDQ"
},
{
"description": "-R:PUNPCKHBW",
"mnem": "PUNPCKHQDQ"
},
{
"description": "-R:PUNPCKHBW",
"mnem": "PUNPCKHWD"
},
{
"description": "PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ-Unpack Low Data\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F 60 /r1 RM V/V MMX Interleave low-order bytes from mm and\r\nPUNPCKLBW mm, mm/m32 mm/m32 into mm.\r\n\r\n66 0F 60 /r RM V/V SSE2 Interleave low-order bytes from xmm1 and\r\nPUNPCKLBW xmm1, xmm2/m128 xmm2/m128 into xmm1.\r\n\r\n0F 61 /r1 RM V/V MMX Interleave low-order words from mm and\r\nPUNPCKLWD mm, mm/m32 mm/m32 into mm.\r\n\r\n66 0F 61 /r RM V/V SSE2 Interleave low-order words from xmm1 and\r\nPUNPCKLWD xmm1, xmm2/m128 xmm2/m128 into xmm1.\r\n\r\n0F 62 /r1 RM V/V MMX Interleave low-order doublewords from mm\r\nPUNPCKLDQ mm, mm/m32 and mm/m32 into mm.\r\n\r\n66 0F 62 /r RM V/V SSE2 Interleave low-order doublewords from xmm1\r\nPUNPCKLDQ xmm1, xmm2/m128 and xmm2/m128 into xmm1.\r\n\r\n66 0F 6C /r RM V/V SSE2 Interleave low-order quadword from xmm1\r\nPUNPCKLQDQ xmm1, xmm2/m128 and xmm2/m128 into xmm1 register.\r\n\r\nVEX.NDS.128.66.0F.WIG 60/r RVM V/V AVX Interleave low-order bytes from xmm2 and\r\nVPUNPCKLBW xmm1,xmm2, xmm3/m128 xmm3/m128 into xmm1.\r\n\r\nVEX.NDS.128.66.0F.WIG 61/r RVM V/V AVX Interleave low-order words from xmm2 and\r\nVPUNPCKLWD xmm1,xmm2, xmm3/m128 xmm3/m128 into xmm1.\r\n\r\nVEX.NDS.128.66.0F.WIG 62/r RVM V/V AVX Interleave low-order doublewords from xmm2\r\nVPUNPCKLDQ xmm1, xmm2, xmm3/m128 and xmm3/m128 into xmm1.\r\n\r\nVEX.NDS.128.66.0F.WIG 6C/r RVM V/V AVX Interleave low-order quadword from xmm2\r\nVPUNPCKLQDQ xmm1, xmm2, xmm3/m128 and xmm3/m128 into xmm1 register.\r\nVEX.NDS.256.66.0F.WIG 60 /r RVM V/V AVX2 Interleave low-order bytes from ymm2 and\r\nVPUNPCKLBW ymm1, ymm2, ymm3/m256 ymm3/m256 into ymm1 register.\r\n\r\nVEX.NDS.256.66.0F.WIG 61 /r RVM V/V AVX2 Interleave low-order words from ymm2 and\r\nVPUNPCKLWD ymm1, ymm2, ymm3/m256 ymm3/m256 into ymm1 register.\r\n\r\nVEX.NDS.256.66.0F.WIG 62 /r RVM V/V AVX2 Interleave low-order doublewords from ymm2\r\nVPUNPCKLDQ ymm1, ymm2, ymm3/m256 and ymm3/m256 into ymm1 register.\r\n\r\nVEX.NDS.256.66.0F.WIG 6C /r RVM V/V AVX2 Interleave low-order quadword from ymm2\r\nVPUNPCKLQDQ ymm1, ymm2, ymm3/m256 and ymm3/m256 into ymm1 register.\r\n\r\nEVEX.NDS.128.66.0F.WIG 60 /r FVM V/V AVX512VL Interleave low-order bytes from xmm2 and\r\nVPUNPCKLBW xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512BW xmm3/m128 into xmm1 register subject to\r\n write mask k1.\r\nEVEX.NDS.128.66.0F.WIG 61 /r FVM V/V AVX512VL Interleave low-order words from xmm2 and\r\nVPUNPCKLWD xmm1 {k1}{z}, xmm2, xmm3/m128 AVX512BW xmm3/m128 into xmm1 register subject to\r\n write mask k1.\r\nEVEX.NDS.128.66.0F.W0 62 /r FV V/V AVX512VL Interleave low-order doublewords from xmm2\r\nVPUNPCKLDQ xmm1 {k1}{z}, xmm2, AVX512F and xmm3/m128/m32bcst into xmm1\r\nxmm3/m128/m32bcst register subject to write mask k1.\r\nEVEX.NDS.128.66.0F.W1 6C /r FV V/V AVX512VL Interleave low-order quadword from zmm2\r\nVPUNPCKLQDQ xmm1 {k1}{z}, xmm2, AVX512F and zmm3/m512/m64bcst into zmm1\r\nxmm3/m128/m64bcst register subject to write mask k1.\r\n\r\n\r\n\r\n\r\n\r\nEVEX.NDS.256.66.0F.WIG 60 /r FVM V/V AVX512VL Interleave low-order bytes from ymm2 and\r\nVPUNPCKLBW ymm1 {k1}{z}, ymm2, ymm3/m256 AVX512BW ymm3/m256 into ymm1 register subject to\r\n write mask k1.\r\nEVEX.NDS.256.66.0F.WIG 61 /r FVM V/V AVX512VL Interleave low-order words from ymm2 and\r\nVPUNPCKLWD ymm1 {k1}{z}, ymm2, ymm3/m256 AVX512BW ymm3/m256 into ymm1 register subject to\r\n write mask k1.\r\nEVEX.NDS.256.66.0F.W0 62 /r FV V/V AVX512VL Interleave low-order doublewords from ymm2\r\nVPUNPCKLDQ ymm1 {k1}{z}, ymm2, AVX512F and ymm3/m256/m32bcst into ymm1\r\nymm3/m256/m32bcst register subject to write mask k1.\r\nEVEX.NDS.256.66.0F.W1 6C /r FV V/V AVX512VL Interleave low-order quadword from ymm2\r\nVPUNPCKLQDQ ymm1 {k1}{z}, ymm2, AVX512F and ymm3/m256/m64bcst into ymm1\r\nymm3/m256/m64bcst register subject to write mask k1.\r\nEVEX.NDS.512.66.0F.WIG 60/r FVM V/V AVX512BW Interleave low-order bytes from zmm2 and\r\nVPUNPCKLBW zmm1 {k1}{z}, zmm2, zmm3/m512 zmm3/m512 into zmm1 register subject to\r\n write mask k1.\r\nEVEX.NDS.512.66.0F.WIG 61/r FVM V/V AVX512BW Interleave low-order words from zmm2 and\r\nVPUNPCKLWD zmm1 {k1}{z}, zmm2, zmm3/m512 zmm3/m512 into zmm1 register subject to\r\n write mask k1.\r\nEVEX.NDS.512.66.0F.W0 62 /r FV V/V AVX512F Interleave low-order doublewords from zmm2\r\nVPUNPCKLDQ zmm1 {k1}{z}, zmm2, and zmm3/m512/m32bcst into zmm1\r\nzmm3/m512/m32bcst register subject to write mask k1.\r\nEVEX.NDS.512.66.0F.W1 6C /r FV V/V AVX512F Interleave low-order quadword from zmm2\r\nVPUNPCKLQDQ zmm1 {k1}{z}, zmm2, and zmm3/m512/m64bcst into zmm1\r\nzmm3/m512/m64bcst register subject to write mask k1.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nUnpacks and interleaves the low-order data elements (bytes, words, doublewords, and quadwords) of the destina-\r\ntion operand (first operand) and source operand (second operand) into the destination operand. (Figure 4-22\r\nshows the unpack operation for bytes in 64-bit operands.). The high-order data elements are ignored.\r\n\r\n\r\n\r\n\r\n\r\n SRC Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X7 X6 X5 X4 X3 X2 X1 X0 DEST\r\n\r\n\r\n\r\n\r\n DEST Y3 X3 Y2 X2 Y1 X1 Y0 X0\r\n\r\n\r\n Figure 4-22. PUNPCKLBW Instruction Operation Using 64-bit Operands\r\n\r\n\r\n\r\n\r\n 255 31 0 255 31 0\r\n\r\n SRC Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X7 X6 X5 X4 X3 X2 X1 X0\r\n\r\n\r\n\r\n\r\n 255 0\r\n\r\n DEST Y5 X5 Y4 X4 Y1 X1 Y0 X0\r\n\r\n\r\n Figure 4-23. 256-bit VPUNPCKLDQ Instruction Operation\r\n\r\n\r\n\r\nWhen the source data comes from a 128-bit memory operand, an implementation may fetch only the appropriate\r\n64 bits; however, alignment to a 16-byte boundary and normal segment checking will still be enforced.\r\nThe (V)PUNPCKLBW instruction interleaves the low-order bytes of the source and destination operands, the\r\n(V)PUNPCKLWD instruction interleaves the low-order words of the source and destination operands, the\r\n(V)PUNPCKLDQ instruction interleaves the low-order doubleword (or doublewords) of the source and destination\r\noperands, and the (V)PUNPCKLQDQ instruction interleaves the low-order quadwords of the source and destination\r\noperands.\r\nThese instructions can be used to convert bytes to words, words to doublewords, doublewords to quadwords, and\r\nquadwords to double quadwords, respectively, by placing all 0s in the source operand. Here, if the source operand\r\ncontains all 0s, the result (stored in the destination operand) contains zero extensions of the high-order data\r\nelements from the original value in the destination operand. For example, with the (V)PUNPCKLBW instruction the\r\nhigh-order bytes are zero extended (that is, unpacked into unsigned word integers), and with the (V)PUNPCKLWD\r\ninstruction, the high-order words are zero extended (unpacked into unsigned doubleword integers).\r\nIn 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to\r\naccess additional registers (XMM8-XMM15).\r\nLegacy SSE versions 64-bit operand: The source operand can be an MMX technology register or a 32-bit memory\r\nlocation. The destination operand is an MMX technology register.\r\n128-bit Legacy SSE versions: The second source operand is an XMM register or a 128-bit memory location. The\r\nfirst source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM\r\ndestination register remain unchanged.\r\nVEX.128 encoded versions: The second source operand is an XMM register or a 128-bit memory location. The first\r\nsource operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the destination YMM register\r\nare zeroed.\r\nVEX.256 encoded version: The second source operand is an YMM register or an 256-bit memory location. The first\r\nsource operand and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding ZMM\r\nregister are zeroed.\r\n\r\n\r\n\r\n\r\n\r\nEVEX encoded VPUNPCKLDQ/QDQ: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit\r\nmemory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The first source\r\noperand and destination operands are ZMM/YMM/XMM registers. The destination is conditionally updated with\r\nwritemask k1.\r\nEVEX encoded VPUNPCKLWD/BW: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit\r\nmemory location. The first source operand and destination operands are ZMM/YMM/XMM registers. The destination\r\nis conditionally updated with writemask k1.\r\n\r\nOperation\r\nPUNPCKLBW instruction with 64-bit operands:\r\n DEST[63:56] <- SRC[31:24];\r\n DEST[55:48] <- DEST[31:24];\r\n DEST[47:40] <- SRC[23:16];\r\n DEST[39:32] <- DEST[23:16];\r\n DEST[31:24] <- SRC[15:8];\r\n DEST[23:16] <- DEST[15:8];\r\n DEST[15:8] <- SRC[7:0];\r\n DEST[7:0] <- DEST[7:0];\r\n\r\nPUNPCKLWD instruction with 64-bit operands:\r\n DEST[63:48] <- SRC[31:16];\r\n DEST[47:32] <- DEST[31:16];\r\n DEST[31:16] <- SRC[15:0];\r\n DEST[15:0] <- DEST[15:0];\r\n\r\nPUNPCKLDQ instruction with 64-bit operands:\r\n DEST[63:32] <- SRC[31:0];\r\n DEST[31:0] <- DEST[31:0];\r\nINTERLEAVE_BYTES_512b (SRC1, SRC2)\r\nTMP_DEST[255:0] <- INTERLEAVE_BYTES_256b(SRC1[255:0], SRC[255:0])\r\nTMP_DEST[511:256] <- INTERLEAVE_BYTES_256b(SRC1[511:256], SRC[511:256])\r\n\r\nINTERLEAVE_BYTES_256b (SRC1, SRC2)\r\nDEST[7:0] <- SRC1[7:0]\r\nDEST[15:8] <- SRC2[7:0]\r\nDEST[23:16] <- SRC1[15:8]\r\nDEST[31:24] <- SRC2[15:8]\r\nDEST[39:32] <- SRC1[23:16]\r\nDEST[47:40] <- SRC2[23:16]\r\nDEST[55:48] <- SRC1[31:24]\r\nDEST[63:56] <- SRC2[31:24]\r\nDEST[71:64] <- SRC1[39:32]\r\nDEST[79:72] <- SRC2[39:32]\r\nDEST[87:80] <- SRC1[47:40]\r\nDEST[95:88] <- SRC2[47:40]\r\nDEST[103:96] <- SRC1[55:48]\r\nDEST[111:104] <- SRC2[55:48]\r\nDEST[119:112] <- SRC1[63:56]\r\nDEST[127:120] <- SRC2[63:56]\r\nDEST[135:128] <- SRC1[135:128]\r\nDEST[143:136] <- SRC2[135:128]\r\nDEST[151:144] <- SRC1[143:136]\r\nDEST[159:152] <- SRC2[143:136]\r\nDEST[167:160] <- SRC1[151:144]\r\n\r\n\r\n\r\nDEST[175:168] <- SRC2[151:144]\r\nDEST[183:176] <- SRC1[159:152]\r\nDEST[191:184] <- SRC2[159:152]\r\nDEST[199:192] <- SRC1[167:160]\r\nDEST[207:200] <- SRC2[167:160]\r\nDEST[215:208] <- SRC1[175:168]\r\nDEST[223:216] <- SRC2[175:168]\r\nDEST[231:224] <- SRC1[183:176]\r\nDEST[239:232] <- SRC2[183:176]\r\nDEST[247:240] <- SRC1[191:184]\r\nDEST[255:248] <- SRC2[191:184]\r\n\r\nINTERLEAVE_BYTES (SRC1, SRC2)\r\nDEST[7:0] <- SRC1[7:0]\r\nDEST[15:8] <- SRC2[7:0]\r\nDEST[23:16] <- SRC2[15:8]\r\nDEST[31:24] <- SRC2[15:8]\r\nDEST[39:32] <- SRC1[23:16]\r\nDEST[47:40] <- SRC2[23:16]\r\nDEST[55:48] <- SRC1[31:24]\r\nDEST[63:56] <- SRC2[31:24]\r\nDEST[71:64] <- SRC1[39:32]\r\nDEST[79:72] <- SRC2[39:32]\r\nDEST[87:80] <- SRC1[47:40]\r\nDEST[95:88] <- SRC2[47:40]\r\nDEST[103:96] <- SRC1[55:48]\r\nDEST[111:104] <- SRC2[55:48]\r\nDEST[119:112] <- SRC1[63:56]\r\nDEST[127:120] <- SRC2[63:56]\r\n\r\nINTERLEAVE_WORDS_512b (SRC1, SRC2)\r\nTMP_DEST[255:0] <- INTERLEAVE_WORDS_256b(SRC1[255:0], SRC[255:0])\r\nTMP_DEST[511:256] <- INTERLEAVE_WORDS_256b(SRC1[511:256], SRC[511:256])\r\n\r\nINTERLEAVE_WORDS_256b(SRC1, SRC2)\r\nDEST[15:0] <- SRC1[15:0]\r\nDEST[31:16] <- SRC2[15:0]\r\nDEST[47:32] <- SRC1[31:16]\r\nDEST[63:48] <- SRC2[31:16]\r\nDEST[79:64] <- SRC1[47:32]\r\nDEST[95:80] <- SRC2[47:32]\r\nDEST[111:96] <- SRC1[63:48]\r\nDEST[127:112] <- SRC2[63:48]\r\nDEST[143:128] <- SRC1[143:128]\r\nDEST[159:144] <- SRC2[143:128]\r\nDEST[175:160] <- SRC1[159:144]\r\nDEST[191:176] <- SRC2[159:144]\r\nDEST[207:192] <- SRC1[175:160]\r\nDEST[223:208] <- SRC2[175:160]\r\nDEST[239:224] <- SRC1[191:176]\r\nDEST[255:240] <- SRC2[191:176]\r\n\r\nINTERLEAVE_WORDS (SRC1, SRC2)\r\nDEST[15:0] <- SRC1[15:0]\r\n\r\n\r\n\r\nDEST[31:16] <- SRC2[15:0]\r\nDEST[47:32] <- SRC1[31:16]\r\nDEST[63:48] <- SRC2[31:16]\r\nDEST[79:64] <- SRC1[47:32]\r\nDEST[95:80] <- SRC2[47:32]\r\nDEST[111:96] <- SRC1[63:48]\r\nDEST[127:112] <- SRC2[63:48]\r\n\r\nINTERLEAVE_DWORDS_512b (SRC1, SRC2)\r\nTMP_DEST[255:0] <- INTERLEAVE_DWORDS_256b(SRC1[255:0], SRC2[255:0])\r\nTMP_DEST[511:256] <- INTERLEAVE_DWORDS_256b(SRC1[511:256], SRC2[511:256])\r\n\r\nINTERLEAVE_DWORDS_256b(SRC1, SRC2)\r\nDEST[31:0] <- SRC1[31:0]\r\nDEST[63:32] <- SRC2[31:0]\r\nDEST[95:64] <- SRC1[63:32]\r\nDEST[127:96] <- SRC2[63:32]\r\nDEST[159:128] <- SRC1[159:128]\r\nDEST[191:160] <- SRC2[159:128]\r\nDEST[223:192] <- SRC1[191:160]\r\nDEST[255:224] <- SRC2[191:160]\r\n\r\nINTERLEAVE_DWORDS(SRC1, SRC2)\r\nDEST[31:0] <- SRC1[31:0]\r\nDEST[63:32] <- SRC2[31:0]\r\nDEST[95:64] <- SRC1[63:32]\r\nDEST[127:96] <- SRC2[63:32]\r\nINTERLEAVE_QWORDS_512b (SRC1, SRC2)\r\nTMP_DEST[255:0] <- INTERLEAVE_QWORDS_256b(SRC1[255:0], SRC2[255:0])\r\nTMP_DEST[511:256] <- INTERLEAVE_QWORDS_256b(SRC1[511:256], SRC2[511:256])\r\n\r\nINTERLEAVE_QWORDS_256b(SRC1, SRC2)\r\nDEST[63:0] <- SRC1[63:0]\r\nDEST[127:64] <- SRC2[63:0]\r\nDEST[191:128] <- SRC1[191:128]\r\nDEST[255:192] <- SRC2[191:128]\r\n\r\nINTERLEAVE_QWORDS(SRC1, SRC2)\r\nDEST[63:0] <- SRC1[63:0]\r\nDEST[127:64] <- SRC2[63:0]\r\n\r\nPUNPCKLBW\r\nDEST[127:0] <-INTERLEAVE_BYTES(DEST, SRC)\r\nDEST[255:127] (Unmodified)\r\n\r\nVPUNPCKLBW (VEX.128 encoded instruction)\r\nDEST[127:0] <-INTERLEAVE_BYTES(SRC1, SRC2)\r\nDEST[511:127] <-0\r\n\r\nVPUNPCKLBW (VEX.256 encoded instruction)\r\nDEST[255:0] <-INTERLEAVE_BYTES_256b(SRC1, SRC2)\r\nDEST[MAX_VL-1:256] <-0\r\n\r\n\r\n\r\n\r\n\r\nVPUNPCKLBW (EVEX.512 encoded instruction)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\nIF VL = 128\r\n TMP_DEST[VL-1:0] <- INTERLEAVE_BYTES(SRC1[VL-1:0], SRC2[VL-1:0])\r\nFI;\r\nIF VL = 256\r\n TMP_DEST[VL-1:0] <- INTERLEAVE_BYTES_256b(SRC1[VL-1:0], SRC2[VL-1:0])\r\nFI;\r\nIF VL = 512\r\n TMP_DEST[VL-1:0] <- INTERLEAVE_BYTES_512b(SRC1[VL-1:0], SRC2[VL-1:0])\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i<-j*8\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- TMP_DEST[i+7:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+7:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\nDEST[511:0] <- INTERLEAVE_BYTES_512b(SRC1, SRC2)\r\n\r\nPUNPCKLWD\r\nDEST[127:0] <-INTERLEAVE_WORDS(DEST, SRC)\r\nDEST[255:127] (Unmodified)\r\n\r\nVPUNPCKLWD (VEX.128 encoded instruction)\r\nDEST[127:0] <-INTERLEAVE_WORDS(SRC1, SRC2)\r\nDEST[511:127] <-0\r\n\r\nVPUNPCKLWD (VEX.256 encoded instruction)\r\nDEST[255:0] <-INTERLEAVE_WORDS_256b(SRC1, SRC2)\r\nDEST[MAX_VL-1:256] <-0\r\n\r\nVPUNPCKLWD (EVEX.512 encoded instruction)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nIF VL = 128\r\n TMP_DEST[VL-1:0] <- INTERLEAVE_WORDS(SRC1[VL-1:0], SRC2[VL-1:0])\r\nFI;\r\nIF VL = 256\r\n TMP_DEST[VL-1:0] <- INTERLEAVE_WORDS_256b(SRC1[VL-1:0], SRC2[VL-1:0])\r\nFI;\r\nIF VL = 512\r\n TMP_DEST[VL-1:0] <- INTERLEAVE_WORDS_512b(SRC1[VL-1:0], SRC2[VL-1:0])\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n\r\n\r\n\r\n THEN DEST[i+15:i] <- TMP_DEST[i+15:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\nDEST[511:0] <- INTERLEAVE_WORDS_512b(SRC1, SRC2)\r\n\r\nPUNPCKLDQ\r\nDEST[127:0] <-INTERLEAVE_DWORDS(DEST, SRC)\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVPUNPCKLDQ (VEX.128 encoded instruction)\r\nDEST[127:0] <-INTERLEAVE_DWORDS(SRC1, SRC2)\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVPUNPCKLDQ (VEX.256 encoded instruction)\r\nDEST[255:0] <-INTERLEAVE_DWORDS_256b(SRC1, SRC2)\r\nDEST[MAX_VL-1:256] <-0\r\n\r\nVPUNPCKLDQ (EVEX encoded instructions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN TMP_SRC2[i+31:i] <- SRC2[31:0]\r\n ELSE TMP_SRC2[i+31:i] <- SRC2[i+31:i]\r\n FI;\r\nENDFOR;\r\nIF VL = 128\r\n TMP_DEST[VL-1:0] <- INTERLEAVE_DWORDS(SRC1[VL-1:0], TMP_SRC2[VL-1:0])\r\nFI;\r\nIF VL = 256\r\n TMP_DEST[VL-1:0] <- INTERLEAVE_DWORDS_256b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])\r\nFI;\r\nIF VL = 512\r\n TMP_DEST[VL-1:0] <- INTERLEAVE_DWORDS_512b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_DEST[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\n\r\n\r\n\r\nENDFOR\r\nDEST511:0] <-INTERLEAVE_DWORDS_512b(SRC1, SRC2)\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nPUNPCKLQDQ\r\nDEST[127:0] <-INTERLEAVE_QWORDS(DEST, SRC)\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nVPUNPCKLQDQ (VEX.128 encoded instruction)\r\nDEST[127:0] <-INTERLEAVE_QWORDS(SRC1, SRC2)\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVPUNPCKLQDQ (VEX.256 encoded instruction)\r\nDEST[255:0] <-INTERLEAVE_QWORDS_256b(SRC1, SRC2)\r\nDEST[MAX_VL-1:256] <-0\r\n\r\nVPUNPCKLQDQ (EVEX encoded instructions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN TMP_SRC2[i+63:i] <- SRC2[63:0]\r\n ELSE TMP_SRC2[i+63:i] <- SRC2[i+63:i]\r\n FI;\r\nENDFOR;\r\nIF VL = 128\r\n TMP_DEST[VL-1:0] <- INTERLEAVE_QWORDS(SRC1[VL-1:0], TMP_SRC2[VL-1:0])\r\nFI;\r\nIF VL = 256\r\n TMP_DEST[VL-1:0] <- INTERLEAVE_QWORDS_256b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])\r\nFI;\r\nIF VL = 512\r\n TMP_DEST[VL-1:0] <- INTERLEAVE_QWORDS_512b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPUNPCKLBW __m512i _mm512_unpacklo_epi8(__m512i a, __m512i b);\r\nVPUNPCKLBW __m512i _mm512_mask_unpacklo_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);\r\nVPUNPCKLBW __m512i _mm512_maskz_unpacklo_epi8( __mmask64 k, __m512i a, __m512i b);\r\nVPUNPCKLBW __m256i _mm256_mask_unpacklo_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);\r\n\r\n\r\n\r\nVPUNPCKLBW __m256i _mm256_maskz_unpacklo_epi8( __mmask32 k, __m256i a, __m256i b);\r\nVPUNPCKLBW __m128i _mm_mask_unpacklo_epi8(v s, __mmask16 k, __m128i a, __m128i b);\r\nVPUNPCKLBW __m128i _mm_maskz_unpacklo_epi8( __mmask16 k, __m128i a, __m128i b);\r\nVPUNPCKLWD __m512i _mm512_unpacklo_epi16(__m512i a, __m512i b);\r\nVPUNPCKLWD __m512i _mm512_mask_unpacklo_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);\r\nVPUNPCKLWD __m512i _mm512_maskz_unpacklo_epi16( __mmask32 k, __m512i a, __m512i b);\r\nVPUNPCKLWD __m256i _mm256_mask_unpacklo_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);\r\nVPUNPCKLWD __m256i _mm256_maskz_unpacklo_epi16( __mmask16 k, __m256i a, __m256i b);\r\nVPUNPCKLWD __m128i _mm_mask_unpacklo_epi16(v s, __mmask8 k, __m128i a, __m128i b);\r\nVPUNPCKLWD __m128i _mm_maskz_unpacklo_epi16( __mmask8 k, __m128i a, __m128i b);\r\nVPUNPCKLDQ __m512i _mm512_unpacklo_epi32(__m512i a, __m512i b);\r\nVPUNPCKLDQ __m512i _mm512_mask_unpacklo_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);\r\nVPUNPCKLDQ __m512i _mm512_maskz_unpacklo_epi32( __mmask16 k, __m512i a, __m512i b);\r\nVPUNPCKLDQ __m256i _mm256_mask_unpacklo_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);\r\nVPUNPCKLDQ __m256i _mm256_maskz_unpacklo_epi32( __mmask8 k, __m256i a, __m256i b);\r\nVPUNPCKLDQ __m128i _mm_mask_unpacklo_epi32(v s, __mmask8 k, __m128i a, __m128i b);\r\nVPUNPCKLDQ __m128i _mm_maskz_unpacklo_epi32( __mmask8 k, __m128i a, __m128i b);\r\nVPUNPCKLQDQ __m512i _mm512_unpacklo_epi64(__m512i a, __m512i b);\r\nVPUNPCKLQDQ __m512i _mm512_mask_unpacklo_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);\r\nVPUNPCKLQDQ __m512i _mm512_maskz_unpacklo_epi64( __mmask8 k, __m512i a, __m512i b);\r\nVPUNPCKLQDQ __m256i _mm256_mask_unpacklo_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);\r\nVPUNPCKLQDQ __m256i _mm256_maskz_unpacklo_epi64( __mmask8 k, __m256i a, __m256i b);\r\nVPUNPCKLQDQ __m128i _mm_mask_unpacklo_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);\r\nVPUNPCKLQDQ __m128i _mm_maskz_unpacklo_epi64( __mmask8 k, __m128i a, __m128i b);\r\nPUNPCKLBW:__m64 _mm_unpacklo_pi8 (__m64 m1, __m64 m2)\r\n(V)PUNPCKLBW:__m128i _mm_unpacklo_epi8 (__m128i m1, __m128i m2)\r\nVPUNPCKLBW:__m256i _mm256_unpacklo_epi8 (__m256i m1, __m256i m2)\r\nPUNPCKLWD:__m64 _mm_unpacklo_pi16 (__m64 m1, __m64 m2)\r\n(V)PUNPCKLWD:__m128i _mm_unpacklo_epi16 (__m128i m1, __m128i m2)\r\nVPUNPCKLWD:__m256i _mm256_unpacklo_epi16 (__m256i m1, __m256i m2)\r\nPUNPCKLDQ:__m64 _mm_unpacklo_pi32 (__m64 m1, __m64 m2)\r\n(V)PUNPCKLDQ:__m128i _mm_unpacklo_epi32 (__m128i m1, __m128i m2)\r\nVPUNPCKLDQ:__m256i _mm256_unpacklo_epi32 (__m256i m1, __m256i m2)\r\n(V)PUNPCKLQDQ:__m128i _mm_unpacklo_epi64 (__m128i m1, __m128i m2)\r\nVPUNPCKLQDQ:__m256i _mm256_unpacklo_epi64 (__m256i m1, __m256i m2)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nNumeric Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded VPUNPCKLDQ/QDQ, see Exceptions Type E4NF.\r\nEVEX-encoded VPUNPCKLBW/WD, see Exceptions Type E4NF.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PUNPCKLBW"
},
{
"description": "-R:PUNPCKLBW",
"mnem": "PUNPCKLDQ"
},
{
"description": "-R:PUNPCKLBW",
"mnem": "PUNPCKLQDQ"
},
{
"description": "-R:PUNPCKLBW",
"mnem": "PUNPCKLWD"
},
{
"description": "PUSH-Push Word, Doubleword or Quadword Onto the Stack\r\n Opcode* Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n FF /6 PUSH r/m16 M Valid Valid Push r/m16.\r\n FF /6 PUSH r/m32 M N.E. Valid Push r/m32.\r\n FF /6 PUSH r/m64 M Valid N.E. Push r/m64.\r\n 50+rw PUSH r16 O Valid Valid Push r16.\r\n 50+rd PUSH r32 O N.E. Valid Push r32.\r\n 50+rd PUSH r64 O Valid N.E. Push r64.\r\n 6A ib PUSH imm8 I Valid Valid Push imm8.\r\n 68 iw PUSH imm16 I Valid Valid Push imm16.\r\n 68 id PUSH imm32 I Valid Valid Push imm32.\r\n 0E PUSH CS NP Invalid Valid Push CS.\r\n 16 PUSH SS NP Invalid Valid Push SS.\r\n 1E PUSH DS NP Invalid Valid Push DS.\r\n 06 PUSH ES NP Invalid Valid Push ES.\r\n 0F A0 PUSH FS NP Valid Valid Push FS.\r\n 0F A8 PUSH GS NP Valid Valid Push GS.\r\n NOTES:\r\n * See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (r) NA NA NA\r\n O opcode + rd (r) NA NA NA\r\n I imm8/16/32 NA NA NA\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nDecrements the stack pointer and then stores the source operand on the top of the stack. Address and operand\r\nsizes are determined and used as follows:\r\n. Address size. The D flag in the current code-segment descriptor determines the default address size; it may be\r\n overridden by an instruction prefix (67H).\r\n The address size is used only when referencing a source operand in memory.\r\n. Operand size. The D flag in the current code-segment descriptor determines the default operand size; it may\r\n be overridden by instruction prefixes (66H or REX.W).\r\n The operand size (16, 32, or 64 bits) determines the amount by which the stack pointer is decremented (2, 4\r\n or 8).\r\n If the source operand is an immediate of size less than the operand size, a sign-extended value is pushed on\r\n the stack. If the source operand is a segment register (16 bits) and the operand size is 64-bits, a zero-\r\n extended value is pushed on the stack; if the operand size is 32-bits, either a zero-extended value is pushed\r\n on the stack or the segment selector is written on the stack using a 16-bit move. For the last case, all recent\r\n Core and Atom processors perform a 16-bit move, leaving the upper portion of the stack location unmodified.\r\n. Stack-address size. Outside of 64-bit mode, the B flag in the current stack-segment descriptor determines the\r\n size of the stack pointer (16 or 32 bits); in 64-bit mode, the size of the stack pointer is always 64 bits.\r\n\r\n\r\n\r\n The stack-address size determines the width of the stack pointer when writing to the stack in memory and\r\n when decrementing the stack pointer. (As stated above, the amount by which the stack pointer is\r\n decremented is determined by the operand size.)\r\n If the operand size is less than the stack-address size, the PUSH instruction may result in a misaligned stack\r\n pointer (a stack pointer that is not aligned on a doubleword or quadword boundary).\r\nThe PUSH ESP instruction pushes the value of the ESP register as it existed before the instruction was executed. If\r\na PUSH instruction uses a memory operand in which the ESP register is used for computing the operand address,\r\nthe address of the operand is computed before the ESP register is decremented.\r\nIf the ESP or SP register is 1 when the PUSH instruction is executed in real-address mode, a stack-fault exception\r\n(#SS) is generated (because the limit of the stack segment is violated). Its delivery encounters a second stack-\r\nfault exception (for the same reason), causing generation of a double-fault exception (#DF). Delivery of the\r\ndouble-fault exception encounters a third stack-fault exception, and the logical processor enters shutdown mode.\r\nSee the discussion of the double-fault exception in Chapter 6 of the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 3A.\r\n\r\nIA-32 Architecture Compatibility\r\nFor IA-32 processors from the Intel 286 on, the PUSH ESP instruction pushes the value of the ESP register as it\r\nexisted before the instruction was executed. (This is also true for Intel 64 architecture, real-address and virtual-\r\n8086 modes of IA-32 architecture.) For the Intel 8086 processor, the PUSH SP instruction pushes the new value\r\nof the SP register (that is the value after it has been decremented by 2).\r\n\r\nOperation\r\n(* See Description section for possible sign-extension or zero-extension of source operand and for *)\r\n(* a case in which the size of the memory store may be smaller than the instruction's operand size *)\r\nIF StackAddrSize = 64\r\n THEN\r\n IF OperandSize = 64\r\n THEN\r\n RSP <- RSP - 8;\r\n Memory[SS:RSP] <- SRC; (* push quadword *)\r\n ELSE IF OperandSize = 32\r\n THEN\r\n RSP <- RSP - 4;\r\n Memory[SS:RSP] <- SRC; (* push dword *)\r\n ELSE (* OperandSize = 16 *)\r\n RSP <- RSP - 2;\r\n Memory[SS:RSP] <- SRC; (* push word *)\r\n FI;\r\nELSE IF StackAddrSize = 32\r\n THEN\r\n IF OperandSize = 64\r\n THEN\r\n ESP <- ESP - 8;\r\n Memory[SS:ESP] <- SRC; (* push quadword *)\r\n ELSE IF OperandSize = 32\r\n THEN\r\n ESP <- ESP - 4;\r\n Memory[SS:ESP] <- SRC; (* push dword *)\r\n ELSE (* OperandSize = 16 *)\r\n ESP <- ESP - 2;\r\n Memory[SS:ESP] <- SRC; (* push word *)\r\n FI;\r\n ELSE (* StackAddrSize = 16 *)\r\n\r\n\r\n\r\n IF OperandSize = 32\r\n THEN\r\n SP <- SP - 4;\r\n Memory[SS:SP] <- SRC; (* push dword *)\r\n ELSE (* OperandSize = 16 *)\r\n SP <- SP - 2;\r\n Memory[SS:SP] <- SRC; (* push word *)\r\n FI;\r\nFI;\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n If the new value of the SP or ESP register is outside the stack segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#SS(0) If the stack address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n If the PUSH is of CS, SS, DS, or ES.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PUSH"
},
{
"description": "PUSHA/PUSHAD-Push All General-Purpose Registers\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 60 PUSHA NP Invalid Valid Push AX, CX, DX, BX, original SP, BP, SI, and DI.\r\n 60 PUSHAD NP Invalid Valid Push EAX, ECX, EDX, EBX, original ESP, EBP,\r\n ESI, and EDI.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nPushes the contents of the general-purpose registers onto the stack. The registers are stored on the stack in the\r\nfollowing order: EAX, ECX, EDX, EBX, ESP (original value), EBP, ESI, and EDI (if the current operand-size attribute\r\nis 32) and AX, CX, DX, BX, SP (original value), BP, SI, and DI (if the operand-size attribute is 16). These instruc-\r\ntions perform the reverse operation of the POPA/POPAD instructions. The value pushed for the ESP or SP register\r\nis its value before prior to pushing the first register (see the \"Operation\" section below).\r\nThe PUSHA (push all) and PUSHAD (push all double) mnemonics reference the same opcode. The PUSHA instruc-\r\ntion is intended for use when the operand-size attribute is 16 and the PUSHAD instruction for when the operand-\r\nsize attribute is 32. Some assemblers may force the operand size to 16 when PUSHA is used and to 32 when\r\nPUSHAD is used. Others may treat these mnemonics as synonyms (PUSHA/PUSHAD) and use the current setting\r\nof the operand-size attribute to determine the size of values to be pushed from the stack, regardless of the\r\nmnemonic used.\r\nIn the real-address mode, if the ESP or SP register is 1, 3, or 5 when PUSHA/PUSHAD executes: an #SS exception\r\nis generated but not delivered (the stack error reported prevents #SS delivery). Next, the processor generates a\r\n#DF exception and enters a shutdown state as described in the #DF discussion in Chapter 6 of the Intel 64 and\r\nIA-32 Architectures Software Developer's Manual, Volume 3A.\r\nThis instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.\r\n\r\nOperation\r\nIF 64-bit Mode\r\n\r\n THEN #UD\r\n\r\nFI;\r\n\r\nIF OperandSize = 32 (* PUSHAD instruction *)\r\n THEN\r\n Temp <- (ESP);\r\n Push(EAX);\r\n Push(ECX);\r\n Push(EDX);\r\n Push(EBX);\r\n Push(Temp);\r\n Push(EBP);\r\n Push(ESI);\r\n Push(EDI);\r\n ELSE (* OperandSize = 16, PUSHA instruction *)\r\n Temp <- (SP);\r\n Push(AX);\r\n Push(CX);\r\n Push(DX);\r\n\r\n\r\n Push(BX);\r\n Push(Temp);\r\n Push(BP);\r\n Push(SI);\r\n Push(DI);\r\nFI;\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#SS(0) If the starting or ending stack address is outside the stack segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If an unaligned memory reference is made while the current privilege level is 3 and alignment\r\n checking is enabled.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If the ESP or SP register contains 7, 9, 11, 13, or 15.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If the ESP or SP register contains 7, 9, 11, 13, or 15.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If an unaligned memory reference is made while alignment checking is enabled.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD If in 64-bit mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PUSHA"
},
{
"description": "-R:PUSHA",
"mnem": "PUSHAD"
},
{
"description": "PUSHF/PUSHFD-Push EFLAGS Register onto the Stack\r\n Opcode* Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 9C PUSHF NP Valid Valid Push lower 16 bits of EFLAGS.\r\n 9C PUSHFD NP N.E. Valid Push EFLAGS.\r\n 9C PUSHFQ NP Valid N.E. Push RFLAGS.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nDecrements the stack pointer by 4 (if the current operand-size attribute is 32) and pushes the entire contents of\r\nthe EFLAGS register onto the stack, or decrements the stack pointer by 2 (if the operand-size attribute is 16) and\r\npushes the lower 16 bits of the EFLAGS register (that is, the FLAGS register) onto the stack. These instructions\r\nreverse the operation of the POPF/POPFD instructions.\r\nWhen copying the entire EFLAGS register to the stack, the VM and RF flags (bits 16 and 17) are not copied; instead,\r\nthe values for these flags are cleared in the EFLAGS image stored on the stack. See Chapter 3 of the Intel 64 and\r\nIA-32 Architectures Software Developer's Manual, Volume 1, for more information about the EFLAGS register.\r\nThe PUSHF (push flags) and PUSHFD (push flags double) mnemonics reference the same opcode. The PUSHF\r\ninstruction is intended for use when the operand-size attribute is 16 and the PUSHFD instruction for when the\r\noperand-size attribute is 32. Some assemblers may force the operand size to 16 when PUSHF is used and to 32\r\nwhen PUSHFD is used. Others may treat these mnemonics as synonyms (PUSHF/PUSHFD) and use the current\r\nsetting of the operand-size attribute to determine the size of values to be pushed from the stack, regardless of the\r\nmnemonic used.\r\nIn 64-bit mode, the instruction's default operation is to decrement the stack pointer (RSP) by 8 and pushes RFLAGS\r\non the stack. 16-bit operation is supported using the operand size override prefix 66H. 32-bit operand size cannot\r\nbe encoded in this mode. When copying RFLAGS to the stack, the VM and RF flags (bits 16 and 17) are not copied;\r\ninstead, values for these flags are cleared in the RFLAGS image stored on the stack.\r\nWhen in virtual-8086 mode and the I/O privilege level (IOPL) is less than 3, the PUSHF/PUSHFD instruction causes\r\na general protection exception (#GP).\r\nIn the real-address mode, if the ESP or SP register is 1 when PUSHF/PUSHFD instruction executes: an #SS excep-\r\ntion is generated but not delivered (the stack error reported prevents #SS delivery). Next, the processor generates\r\na #DF exception and enters a shutdown state as described in the #DF discussion in Chapter 6 of the Intel 64 and\r\nIA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\nOperation\r\nIF (PE = 0) or (PE = 1 and ((VM = 0) or (VM = 1 and IOPL = 3)))\r\n(* Real-Address Mode, Protected mode, or Virtual-8086 mode with IOPL equal to 3 *)\r\n THEN\r\n IF OperandSize = 32\r\n THEN\r\n push (EFLAGS AND 00FCFFFFH);\r\n (* VM and RF EFLAG bits are cleared in image stored on the stack *)\r\n ELSE\r\n push (EFLAGS); (* Lower 16 bits only *)\r\n FI;\r\n\r\n ELSE IF 64-bit MODE (* In 64-bit Mode *)\r\n IF OperandSize = 64\r\n\r\n\r\n\r\n THEN\r\n push (RFLAGS AND 00000000_00FCFFFFH);\r\n (* VM and RF RFLAG bits are cleared in image stored on the stack; *)\r\n ELSE\r\n push (EFLAGS); (* Lower 16 bits only *)\r\n FI;\r\n\r\n ELSE (* In Virtual-8086 Mode with IOPL less than 3 *)\r\n #GP(0); (* Trap to virtual-8086 monitor *)\r\nFI;\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#SS(0) If the new value of the ESP register is outside the stack segment boundary.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If an unaligned memory reference is made while the current privilege level is 3 and alignment\r\n checking is enabled.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If the I/O privilege level is less than 3.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If an unaligned memory reference is made while alignment checking is enabled.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#SS(0) If the stack address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If an unaligned memory reference is made while the current privilege level is 3 and alignment\r\n checking is enabled.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PUSHF"
},
{
"description": "-R:PUSHF",
"mnem": "PUSHFD"
},
{
"description": "-R:PUSHF",
"mnem": "PUSHFQ"
},
{
"description": "PXOR-Logical Exclusive OR\r\nOpcode*/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F EF /r1 RM V/V MMX Bitwise XOR of mm/m64 and mm.\r\nPXOR mm, mm/m64\r\n66 0F EF /r RM V/V SSE2 Bitwise XOR of xmm2/m128 and xmm1.\r\nPXOR xmm1, xmm2/m128\r\nVEX.NDS.128.66.0F.WIG EF /r RVM V/V AVX Bitwise XOR of xmm3/m128 and xmm2.\r\nVPXOR xmm1, xmm2, xmm3/m128\r\nVEX.NDS.256.66.0F.WIG EF /r RVM V/V AVX2 Bitwise XOR of ymm3/m256 and ymm2.\r\nVPXOR ymm1, ymm2, ymm3/m256\r\nEVEX.NDS.128.66.0F.W0 EF /r FV V/V AVX512VL Bitwise XOR of packed doubleword integers in\r\nVPXORD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst AVX512F xmm2 and xmm3/m128 using writemask k1.\r\nEVEX.NDS.256.66.0F.W0 EF /r FV V/V AVX512VL Bitwise XOR of packed doubleword integers in\r\nVPXORD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst AVX512F ymm2 and ymm3/m256 using writemask k1.\r\nEVEX.NDS.512.66.0F.W0 EF /r FV V/V AVX512F Bitwise XOR of packed doubleword integers in\r\nVPXORD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst zmm2 and zmm3/m512/m32bcst using\r\n writemask k1.\r\nEVEX.NDS.128.66.0F.W1 EF /r FV V/V AVX512VL Bitwise XOR of packed quadword integers in\r\nVPXORQ xmm1 {k1}{z}, xmm2, AVX512F xmm2 and xmm3/m128 using writemask k1.\r\nxmm3/m128/m64bcst\r\nEVEX.NDS.256.66.0F.W1 EF /r FV V/V AVX512VL Bitwise XOR of packed quadword integers in\r\nVPXORQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst AVX512F ymm2 and ymm3/m256 using writemask k1.\r\nEVEX.NDS.512.66.0F.W1 EF /r FV V/V AVX512F Bitwise XOR of packed quadword integers in\r\nVPXORQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst zmm2 and zmm3/m512/m64bcst using\r\n writemask k1.\r\nNOTES:\r\n1. See note in Section 2.4, \"AVX and SSE Instruction Exception Specification\" in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 2A and Section 22.25.3, \"Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers\"\r\nin the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nPerforms a bitwise logical exclusive-OR (XOR) operation on the source operand (second operand) and the destina-\r\ntion operand (first operand) and stores the result in the destination operand. Each bit of the result is 1 if the corre-\r\nsponding bits of the two operands are different; each bit is 0 if the corresponding bits of the operands are the same.\r\nIn 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to\r\naccess additional registers (XMM8-XMM15).\r\nLegacy SSE instructions 64-bit operand: The source operand can be an MMX technology register or a 64-bit\r\nmemory location. The destination operand is an MMX technology register.\r\n\r\n\r\n\r\n\r\n\r\n128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first\r\nsource operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM desti-\r\nnation register remain unchanged.\r\nVEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first\r\nsource operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the destination YMM register\r\nare zeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register\r\nor a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the\r\ncorresponding register destination are zeroed.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be\r\na ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a\r\n32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with\r\nwritemask k1.\r\n\r\nOperation\r\nPXOR (64-bit operand)\r\nDEST <- DEST XOR SRC\r\nPXOR (128-bit Legacy SSE version)\r\nDEST <- DEST XOR SRC\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVPXOR (VEX.128 encoded version)\r\nDEST <- SRC1 XOR SRC2\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPXOR (VEX.256 encoded version)\r\nDEST <- SRC1 XOR SRC2\r\nDEST[VLMAX-1:256] <- 0\r\n\r\nVPXORD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN DEST[i+31:i] <- SRC1[i+31:i] BITWISE XOR SRC2[31:0]\r\n ELSE DEST[i+31:i] <- SRC1[i+31:i] BITWISE XOR SRC2[i+31:i]\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[31:0] <- 0\r\n FI;\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVPXORQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN DEST[i+63:i] <- SRC1[i+63:i] BITWISE XOR SRC2[63:0]\r\n ELSE DEST[i+63:i] <- SRC1[i+63:i] BITWISE XOR SRC2[i+63:i]\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[63:0] <- 0\r\n FI;\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPXORD __m512i _mm512_xor_epi32(__m512i a, __m512i b)\r\nVPXORD __m512i _mm512_mask_xor_epi32(__m512i s, __mmask16 m, __m512i a, __m512i b)\r\nVPXORD __m512i _mm512_maskz_xor_epi32( __mmask16 m, __m512i a, __m512i b)\r\nVPXORD __m256i _mm256_xor_epi32(__m256i a, __m256i b)\r\nVPXORD __m256i _mm256_mask_xor_epi32(__m256i s, __mmask8 m, __m256i a, __m256i b)\r\nVPXORD __m256i _mm256_maskz_xor_epi32( __mmask8 m, __m256i a, __m256i b)\r\nVPXORD __m128i _mm_xor_epi32(__m128i a, __m128i b)\r\nVPXORD __m128i _mm_mask_xor_epi32(__m128i s, __mmask8 m, __m128i a, __m128i b)\r\nVPXORD __m128i _mm_maskz_xor_epi32( __mmask16 m, __m128i a, __m128i b)\r\nVPXORQ __m512i _mm512_xor_epi64( __m512i a, __m512i b);\r\nVPXORQ __m512i _mm512_mask_xor_epi64(__m512i s, __mmask8 m, __m512i a, __m512i b);\r\nVPXORQ __m512i _mm512_maskz_xor_epi64(__mmask8 m, __m512i a, __m512i b);\r\nVPXORQ __m256i _mm256_xor_epi64( __m256i a, __m256i b);\r\nVPXORQ __m256i _mm256_mask_xor_epi64(__m256i s, __mmask8 m, __m256i a, __m256i b);\r\nVPXORQ __m256i _mm256_maskz_xor_epi64(__mmask8 m, __m256i a, __m256i b);\r\nVPXORQ __m128i _mm_xor_epi64( __m128i a, __m128i b);\r\nVPXORQ __m128i _mm_mask_xor_epi64(__m128i s, __mmask8 m, __m128i a, __m128i b);\r\nVPXORQ __m128i _mm_maskz_xor_epi64(__mmask8 m, __m128i a, __m128i b);\r\nPXOR:__m64 _mm_xor_si64 (__m64 m1, __m64 m2)\r\n(V)PXOR:__m128i _mm_xor_si128 ( __m128i a, __m128i b)\r\nVPXOR:__m256i _mm256_xor_si256 ( __m256i a, __m256i b)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nNumeric Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "PXOR"
},
{
"description": "RCL/RCR/ROL/ROR-Rotate\r\n Opcode** Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n D0 /2 RCL r/m8, 1 M1 Valid Valid Rotate 9 bits (CF, r/m8) left once.\r\n REX + D0 /2 RCL r/m8*, 1 M1 Valid N.E. Rotate 9 bits (CF, r/m8) left once.\r\n D2 /2 RCL r/m8, CL MC Valid Valid Rotate 9 bits (CF, r/m8) left CL times.\r\n REX + D2 /2 RCL r/m8*, CL MC Valid N.E. Rotate 9 bits (CF, r/m8) left CL times.\r\n C0 /2 ib RCL r/m8, imm8 MI Valid Valid Rotate 9 bits (CF, r/m8) left imm8 times.\r\n REX + C0 /2 ib RCL r/m8*, imm8 MI Valid N.E. Rotate 9 bits (CF, r/m8) left imm8 times.\r\n D1 /2 RCL r/m16, 1 M1 Valid Valid Rotate 17 bits (CF, r/m16) left once.\r\n D3 /2 RCL r/m16, CL MC Valid Valid Rotate 17 bits (CF, r/m16) left CL times.\r\n C1 /2 ib RCL r/m16, imm8 MI Valid Valid Rotate 17 bits (CF, r/m16) left imm8 times.\r\n D1 /2 RCL r/m32, 1 M1 Valid Valid Rotate 33 bits (CF, r/m32) left once.\r\n REX.W + D1 /2 RCL r/m64, 1 M1 Valid N.E. Rotate 65 bits (CF, r/m64) left once. Uses a 6\r\n bit count.\r\n D3 /2 RCL r/m32, CL MC Valid Valid Rotate 33 bits (CF, r/m32) left CL times.\r\n REX.W + D3 /2 RCL r/m64, CL MC Valid N.E. Rotate 65 bits (CF, r/m64) left CL times. Uses a\r\n 6 bit count.\r\n C1 /2 ib RCL r/m32, imm8 MI Valid Valid Rotate 33 bits (CF, r/m32) left imm8 times.\r\n REX.W + C1 /2 ib RCL r/m64, imm8 MI Valid N.E. Rotate 65 bits (CF, r/m64) left imm8 times.\r\n Uses a 6 bit count.\r\n D0 /3 RCR r/m8, 1 M1 Valid Valid Rotate 9 bits (CF, r/m8) right once.\r\n REX + D0 /3 RCR r/m8*, 1 M1 Valid N.E. Rotate 9 bits (CF, r/m8) right once.\r\n D2 /3 RCR r/m8, CL MC Valid Valid Rotate 9 bits (CF, r/m8) right CL times.\r\n REX + D2 /3 RCR r/m8*, CL MC Valid N.E. Rotate 9 bits (CF, r/m8) right CL times.\r\n C0 /3 ib RCR r/m8, imm8 MI Valid Valid Rotate 9 bits (CF, r/m8) right imm8 times.\r\n REX + C0 /3 ib RCR r/m8*, imm8 MI Valid N.E. Rotate 9 bits (CF, r/m8) right imm8 times.\r\n D1 /3 RCR r/m16, 1 M1 Valid Valid Rotate 17 bits (CF, r/m16) right once.\r\n D3 /3 RCR r/m16, CL MC Valid Valid Rotate 17 bits (CF, r/m16) right CL times.\r\n C1 /3 ib RCR r/m16, imm8 MI Valid Valid Rotate 17 bits (CF, r/m16) right imm8 times.\r\n D1 /3 RCR r/m32, 1 M1 Valid Valid Rotate 33 bits (CF, r/m32) right once. Uses a 6\r\n bit count.\r\n REX.W + D1 /3 RCR r/m64, 1 M1 Valid N.E. Rotate 65 bits (CF, r/m64) right once. Uses a 6\r\n bit count.\r\n D3 /3 RCR r/m32, CL MC Valid Valid Rotate 33 bits (CF, r/m32) right CL times.\r\n REX.W + D3 /3 RCR r/m64, CL MC Valid N.E. Rotate 65 bits (CF, r/m64) right CL times. Uses\r\n a 6 bit count.\r\n C1 /3 ib RCR r/m32, imm8 MI Valid Valid Rotate 33 bits (CF, r/m32) right imm8 times.\r\n REX.W + C1 /3 ib RCR r/m64, imm8 MI Valid N.E. Rotate 65 bits (CF, r/m64) right imm8 times.\r\n Uses a 6 bit count.\r\n D0 /0 ROL r/m8, 1 M1 Valid Valid Rotate 8 bits r/m8 left once.\r\n REX + D0 /0 ROL r/m8*, 1 M1 Valid N.E. Rotate 8 bits r/m8 left once\r\n D2 /0 ROL r/m8, CL MC Valid Valid Rotate 8 bits r/m8 left CL times.\r\n REX + D2 /0 ROL r/m8*, CL MC Valid N.E. Rotate 8 bits r/m8 left CL times.\r\n C0 /0 ib ROL r/m8, imm8 MI Valid Valid Rotate 8 bits r/m8 left imm8 times.\r\n\r\n\r\n Opcode** Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n REX + C0 /0 ib ROL r/m8*, imm8 MI Valid N.E. Rotate 8 bits r/m8 left imm8 times.\r\n D1 /0 ROL r/m16, 1 M1 Valid Valid Rotate 16 bits r/m16 left once.\r\n D3 /0 ROL r/m16, CL MC Valid Valid Rotate 16 bits r/m16 left CL times.\r\n C1 /0 ib ROL r/m16, imm8 MI Valid Valid Rotate 16 bits r/m16 left imm8 times.\r\n D1 /0 ROL r/m32, 1 M1 Valid Valid Rotate 32 bits r/m32 left once.\r\n\r\n\r\n\r\n REX.W + D1 /0 ROL r/m64, 1 M1 Valid N.E. Rotate 64 bits r/m64 left once. Uses a 6 bit\r\n count.\r\n D3 /0 ROL r/m32, CL MC Valid Valid Rotate 32 bits r/m32 left CL times.\r\n REX.W + D3 /0 ROL r/m64, CL MC Valid N.E. Rotate 64 bits r/m64 left CL times. Uses a 6\r\n bit count.\r\n C1 /0 ib ROL r/m32, imm8 MI Valid Valid Rotate 32 bits r/m32 left imm8 times.\r\n REX.W + C1 /0 ib ROL r/m64, imm8 MI Valid N.E. Rotate 64 bits r/m64 left imm8 times. Uses a\r\n 6 bit count.\r\n D0 /1 ROR r/m8, 1 M1 Valid Valid Rotate 8 bits r/m8 right once.\r\n REX + D0 /1 ROR r/m8*, 1 M1 Valid N.E. Rotate 8 bits r/m8 right once.\r\n D2 /1 ROR r/m8, CL MC Valid Valid Rotate 8 bits r/m8 right CL times.\r\n REX + D2 /1 ROR r/m8*, CL MC Valid N.E. Rotate 8 bits r/m8 right CL times.\r\n C0 /1 ib ROR r/m8, imm8 MI Valid Valid Rotate 8 bits r/m16 right imm8 times.\r\n REX + C0 /1 ib ROR r/m8*, imm8 MI Valid N.E. Rotate 8 bits r/m16 right imm8 times.\r\n D1 /1 ROR r/m16, 1 M1 Valid Valid Rotate 16 bits r/m16 right once.\r\n D3 /1 ROR r/m16, CL MC Valid Valid Rotate 16 bits r/m16 right CL times.\r\n C1 /1 ib ROR r/m16, imm8 MI Valid Valid Rotate 16 bits r/m16 right imm8 times.\r\n D1 /1 ROR r/m32, 1 M1 Valid Valid Rotate 32 bits r/m32 right once.\r\n REX.W + D1 /1 ROR r/m64, 1 M1 Valid N.E. Rotate 64 bits r/m64 right once. Uses a 6 bit\r\n count.\r\n D3 /1 ROR r/m32, CL MC Valid Valid Rotate 32 bits r/m32 right CL times.\r\n REX.W + D3 /1 ROR r/m64, CL MC Valid N.E. Rotate 64 bits r/m64 right CL times. Uses a 6\r\n bit count.\r\n C1 /1 ib ROR r/m32, imm8 MI Valid Valid Rotate 32 bits r/m32 right imm8 times.\r\n REX.W + C1 /1 ib ROR r/m64, imm8 MI Valid N.E. Rotate 64 bits r/m64 right imm8 times. Uses a\r\n 6 bit count.\r\n NOTES:\r\n * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n ** See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M1 ModRM:r/m (w) 1 NA NA\r\n MC ModRM:r/m (w) CL NA NA\r\n MI ModRM:r/m (w) imm8 NA NA\r\n\r\n\r\n\r\n\r\n\r\nDescription\r\nShifts (rotates) the bits of the first operand (destination operand) the number of bit positions specified in the\r\nsecond operand (count operand) and stores the result in the destination operand. The destination operand can be\r\na register or a memory location; the count operand is an unsigned integer that can be an immediate or a value in\r\nthe CL register. The count is masked to 5 bits (or 6 bits if in 64-bit mode and REX.W = 1).\r\nThe rotate left (ROL) and rotate through carry left (RCL) instructions shift all the bits toward more-significant bit\r\npositions, except for the most-significant bit, which is rotated to the least-significant bit location. The rotate right\r\n(ROR) and rotate through carry right (RCR) instructions shift all the bits toward less significant bit positions, except\r\nfor the least-significant bit, which is rotated to the most-significant bit location.\r\nThe RCL and RCR instructions include the CF flag in the rotation. The RCL instruction shifts the CF flag into the\r\nleast-significant bit and shifts the most-significant bit into the CF flag. The RCR instruction shifts the CF flag into\r\nthe most-significant bit and shifts the least-significant bit into the CF flag. For the ROL and ROR instructions, the\r\noriginal value of the CF flag is not a part of the result, but the CF flag receives a copy of the bit that was shifted from\r\none end to the other.\r\nThe OF flag is defined only for the 1-bit rotates; it is undefined in all other cases (except RCL and RCR instructions\r\nonly: a zero-bit rotate does nothing, that is affects no flags). For left rotates, the OF flag is set to the exclusive OR\r\nof the CF bit (after the rotate) and the most-significant bit of the result. For right rotates, the OF flag is set to the\r\nexclusive OR of the two most-significant bits of the result.\r\nIn 64-bit mode, using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Use of\r\nREX.W promotes the first operand to 64 bits and causes the count operand to become a 6-bit counter.\r\n\r\nIA-32 Architecture Compatibility\r\nThe 8086 does not mask the rotation count. However, all other IA-32 processors (starting with the Intel 286\r\nprocessor) do mask the rotation count to 5 bits, resulting in a maximum count of 31. This masking is done in all\r\noperating modes (including the virtual-8086 mode) to reduce the maximum execution time of the instructions.\r\n\r\nOperation\r\n(* RCL and RCR instructions *)\r\nSIZE <- OperandSize;\r\nCASE (determine count) OF\r\n SIZE <- 8: tempCOUNT <- (COUNT AND 1FH) MOD 9;\r\n SIZE <- 16: tempCOUNT <- (COUNT AND 1FH) MOD 17;\r\n SIZE <- 32: tempCOUNT <- COUNT AND 1FH;\r\n SIZE <- 64: tempCOUNT <- COUNT AND 3FH;\r\nESAC;\r\n\r\n(* RCL instruction operation *)\r\nWHILE (tempCOUNT != 0)\r\n DO\r\n tempCF <- MSB(DEST);\r\n DEST <- (DEST * 2) + CF;\r\n CF <- tempCF;\r\n tempCOUNT <- tempCOUNT - 1;\r\n OD;\r\nELIHW;\r\nIF (COUNT & COUNTMASK) = 1\r\n THEN OF <- MSB(DEST) XOR CF;\r\n ELSE OF is undefined;\r\nFI;\r\n\r\n\r\n\r\n\r\n\r\n(* RCR instruction operation *)\r\nIF (COUNT & COUNTMASK) = 1\r\n THEN OF <- MSB(DEST) XOR CF;\r\n ELSE OF is undefined;\r\nFI;\r\nWHILE (tempCOUNT != 0)\r\n DO\r\n tempCF <- LSB(SRC);\r\n DEST <- (DEST / 2) + (CF * 2SIZE);\r\n CF <- tempCF;\r\n tempCOUNT <- tempCOUNT - 1;\r\n OD;\r\n\r\n(* ROL and ROR instructions *)\r\nIF OperandSize = 64\r\n THEN COUNTMASK = 3FH;\r\n ELSE COUNTMASK = 1FH;\r\nFI;\r\n\r\n(* ROL instruction operation *)\r\ntempCOUNT <- (COUNT & COUNTMASK) MOD SIZE\r\n\r\nWHILE (tempCOUNT != 0)\r\n DO\r\n tempCF <- MSB(DEST);\r\n DEST <- (DEST * 2) + tempCF;\r\n tempCOUNT <- tempCOUNT - 1;\r\n OD;\r\nELIHW;\r\nIF (COUNT & COUNTMASK) != 0\r\n THEN CF <- LSB(DEST);\r\nFI;\r\nIF (COUNT & COUNTMASK) = 1\r\n THEN OF <- MSB(DEST) XOR CF;\r\n ELSE OF is undefined;\r\nFI;\r\n\r\n(* ROR instruction operation *)\r\ntempCOUNT <- (COUNT & COUNTMASK) MOD SIZE\r\nWHILE (tempCOUNT != 0)\r\n DO\r\n tempCF <- LSB(SRC);\r\n DEST <- (DEST / 2) + (tempCF * 2SIZE);\r\n tempCOUNT <- tempCOUNT - 1;\r\n OD;\r\nELIHW;\r\nIF (COUNT & COUNTMASK) != 0\r\n THEN CF <- MSB(DEST);\r\nFI;\r\nIF (COUNT & COUNTMASK) = 1\r\n THEN OF <- MSB(DEST) XOR MSB - 1(DEST);\r\n ELSE OF is undefined;\r\nFI;\r\n\r\n\r\n\r\n\r\nFlags Affected\r\nIf the masked count is 0, the flags are not affected. If the masked count is 1, then the OF flag is affected, otherwise\r\n(masked count is greater than 1) the OF flag is undefined. The CF flag is affected when the masked count is non-\r\nzero. The SF, ZF, AF, and PF flags are always unaffected.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the source operand is located in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the source operand is located in a nonwritable segment.\r\n If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "RCL"
},
{
"description": "RCPPS-Compute Reciprocals of Packed Single-Precision Floating-Point Values\r\n Opcode*/ Op/ 64/32 bit CPUID Description\r\n Instruction En Mode Feature\r\n Support Flag\r\n 0F 53 /r RM V/V SSE Computes the approximate reciprocals of the\r\n RCPPS xmm1, xmm2/m128 packed single-precision floating-point values\r\n in xmm2/m128 and stores the results in\r\n xmm1.\r\n VEX.128.0F.WIG 53 /r RM V/V AVX Computes the approximate reciprocals of\r\n VRCPPS xmm1, xmm2/m128 packed single-precision values in xmm2/mem\r\n and stores the results in xmm1.\r\n VEX.256.0F.WIG 53 /r RM V/V AVX Computes the approximate reciprocals of\r\n VRCPPS ymm1, ymm2/m256 packed single-precision values in ymm2/mem\r\n and stores the results in ymm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\n\r\nDescription\r\nPerforms a SIMD computation of the approximate reciprocals of the four packed single-precision floating-point\r\nvalues in the source operand (second operand) stores the packed single-precision floating-point results in the\r\ndestination operand. The source operand can be an XMM register or a 128-bit memory location. The destination\r\noperand is an XMM register. See Figure 10-5 in the Intel 64 and IA-32 Architectures Software Developer's\r\nManual, Volume 1, for an illustration of a SIMD single-precision floating-point operation.\r\nThe relative error for this approximation is:\r\n\r\n |Relative Error| <= 1.5 * 2-12\r\nThe RCPPS instruction is not affected by the rounding control bits in the MXCSR register. When a source value is a\r\n0.0, an inf of the sign of the source value is returned. A denormal source value is treated as a 0.0 (of the same sign).\r\nTiny results (see Section 4.9.1.5, \"Numeric Underflow Exception (#U)\" in Intel 64 and IA-32 Architectures Soft-\r\nware Developer's Manual, Volume 1) are always flushed to 0.0, with the sign of the operand. (Input values greater\r\nthan or equal to |1.11111111110100000000000B*2125| are guaranteed to not produce tiny results; input values\r\nless than or equal to |1.00000000000110000000001B*2126| are guaranteed to produce tiny results, which are in\r\nturn flushed to 0.0; and input values in between this range may or may not produce tiny results, depending on the\r\nimplementation.) When a source value is an SNaN or QNaN, the SNaN is converted to a QNaN or the source QNaN\r\nis returned.\r\nIn 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers\r\n(XMM8-XMM15).\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding\r\nYMM register destination are unmodified.\r\nVEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination\r\noperand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are\r\nzeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register.\r\nNote: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nRCPPS (128-bit Legacy SSE version)\r\nDEST[31:0] <- APPROXIMATE(1/SRC[31:0])\r\nDEST[63:32] <- APPROXIMATE(1/SRC[63:32])\r\nDEST[95:64] <- APPROXIMATE(1/SRC[95:64])\r\nDEST[127:96] <- APPROXIMATE(1/SRC[127:96])\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVRCPPS (VEX.128 encoded version)\r\nDEST[31:0] <- APPROXIMATE(1/SRC[31:0])\r\nDEST[63:32] <- APPROXIMATE(1/SRC[63:32])\r\nDEST[95:64] <- APPROXIMATE(1/SRC[95:64])\r\nDEST[127:96] <- APPROXIMATE(1/SRC[127:96])\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVRCPPS (VEX.256 encoded version)\r\nDEST[31:0] <- APPROXIMATE(1/SRC[31:0])\r\nDEST[63:32] <- APPROXIMATE(1/SRC[63:32])\r\nDEST[95:64] <- APPROXIMATE(1/SRC[95:64])\r\nDEST[127:96] <- APPROXIMATE(1/SRC[127:96])\r\nDEST[159:128] <- APPROXIMATE(1/SRC[159:128])\r\nDEST[191:160] <- APPROXIMATE(1/SRC[191:160])\r\nDEST[223:192] <- APPROXIMATE(1/SRC[223:192])\r\nDEST[255:224] <- APPROXIMATE(1/SRC[255:224])\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nRCCPS: __m128 _mm_rcp_ps(__m128 a)\r\nRCPPS: __m256 _mm256_rcp_ps (__m256 a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4; additionally\r\n#UD If VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "RCPPS"
},
{
"description": "RCPSS-Compute Reciprocal of Scalar Single-Precision Floating-Point Values\r\nOpcode*/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\nF3 0F 53 /r RM V/V SSE Computes the approximate reciprocal of the\r\nRCPSS xmm1, xmm2/m32 scalar single-precision floating-point value in\r\n xmm2/m32 and stores the result in xmm1.\r\nVEX.NDS.LIG.F3.0F.WIG 53 /r RVM V/V AVX Computes the approximate reciprocal of the\r\nVRCPSS xmm1, xmm2, xmm3/m32 scalar single-precision floating-point value in\r\n xmm3/m32 and stores the result in xmm1.\r\n Also, upper single precision floating-point\r\n values (bits[127:32]) from xmm2 are copied to\r\n xmm1[127:32].\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nComputes of an approximate reciprocal of the low single-precision floating-point value in the source operand\r\n(second operand) and stores the single-precision floating-point result in the destination operand. The source\r\noperand can be an XMM register or a 32-bit memory location. The destination operand is an XMM register. The\r\nthree high-order doublewords of the destination operand remain unchanged. See Figure 10-6 in the Intel 64 and\r\nIA-32 Architectures Software Developer's Manual, Volume 1, for an illustration of a scalar single-precision floating-\r\npoint operation.\r\nThe relative error for this approximation is:\r\n\r\n |Relative Error| <= 1.5 * 2-12\r\nThe RCPSS instruction is not affected by the rounding control bits in the MXCSR register. When a source value is a\r\n0.0, an inf of the sign of the source value is returned. A denormal source value is treated as a 0.0 (of the same sign).\r\nTiny results (see Section 4.9.1.5, \"Numeric Underflow Exception (#U)\" in Intel 64 and IA-32 Architectures Soft-\r\nware Developer's Manual, Volume 1) are always flushed to 0.0, with the sign of the operand. (Input values greater\r\nthan or equal to |1.11111111110100000000000B*2125| are guaranteed to not produce tiny results; input values\r\nless than or equal to |1.00000000000110000000001B*2126| are guaranteed to produce tiny results, which are in\r\nturn flushed to 0.0; and input values in between this range may or may not produce tiny results, depending on the\r\nimplementation.) When a source value is an SNaN or QNaN, the SNaN is converted to a QNaN or the source QNaN\r\nis returned.\r\nIn 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers\r\n(XMM8-XMM15).\r\n128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (VLMAX-\r\n1:32) of the corresponding YMM destination register remain unchanged.\r\nVEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.\r\n\r\nOperation\r\nRCPSS (128-bit Legacy SSE version)\r\nDEST[31:0] <- APPROXIMATE(1/SRC[31:0])\r\nDEST[VLMAX-1:32] (Unmodified)\r\n\r\n\r\n\r\n\r\n\r\nVRCPSS (VEX.128 encoded version)\r\nDEST[31:0] <- APPROXIMATE(1/SRC2[31:0])\r\nDEST[127:32] <- SRC1[127:32]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nRCPSS: __m128 _mm_rcp_ss(__m128 a)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 5.\r\n\r\n\r\n\r\n\r\n",
"mnem": "RCPSS"
},
{
"description": "-R:RCL",
"mnem": "RCR"
},
{
"description": "RDFSBASE/RDGSBASE-Read FS/GS Segment Base\r\nOpcode/ Op/ 64/32- CPUID Fea- Description\r\nInstruction En bit ture Flag\r\n Mode\r\nF3 0F AE /0 M V/I FSGSBASE Load the 32-bit destination register with the FS\r\nRDFSBASE r32 base address.\r\nF3 REX.W 0F AE /0 M V/I FSGSBASE Load the 64-bit destination register with the FS\r\nRDFSBASE r64 base address.\r\nF3 0F AE /1 M V/I FSGSBASE Load the 32-bit destination register with the GS\r\nRDGSBASE r32 base address.\r\nF3 REX.W 0F AE /1 M V/I FSGSBASE Load the 64-bit destination register with the GS\r\nRDGSBASE r64 base address.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (w) NA NA NA\r\n\r\n\r\nDescription\r\nLoads the general-purpose register indicated by the modR/M:r/m field with the FS or GS segment base address.\r\nThe destination operand may be either a 32-bit or a 64-bit general-purpose register. The REX.W prefix indicates the\r\noperand size is 64 bits. If no REX.W prefix is used, the operand size is 32 bits; the upper 32 bits of the source base\r\naddress (for FS or GS) are ignored and upper 32 bits of the destination register are cleared.\r\nThis instruction is supported only in 64-bit mode.\r\n\r\nOperation\r\nDEST <- FS/GS segment base address;\r\n\r\nFlags Affected\r\nNone\r\n\r\nC/C++ Compiler Intrinsic Equivalent\r\nRDFSBASE: unsigned int _readfsbase_u32(void );\r\nRDFSBASE: unsigned __int64 _readfsbase_u64(void );\r\nRDGSBASE: unsigned int _readgsbase_u32(void );\r\nRDGSBASE: unsigned __int64 _readgsbase_u64(void );\r\n\r\nProtected Mode Exceptions\r\n#UD The RDFSBASE and RDGSBASE instructions are not recognized in protected mode.\r\n\r\nReal-Address Mode Exceptions\r\n#UD The RDFSBASE and RDGSBASE instructions are not recognized in real-address mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD The RDFSBASE and RDGSBASE instructions are not recognized in virtual-8086 mode.\r\n\r\nCompatibility Mode Exceptions\r\n#UD The RDFSBASE and RDGSBASE instructions are not recognized in compatibility mode.\r\n\r\n\r\n\r\n64-Bit Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If CR4.FSGSBASE[bit 16] = 0.\r\n If CPUID.07H.0H:EBX.FSGSBASE[bit 0] = 0.\r\n\r\n\r\n\r\n\r\n",
"mnem": "RDFSBASE"
},
{
"description": "-R:RDFSBASE",
"mnem": "RDGSBASE"
},
{
"description": "RDMSR-Read from Model Specific Register\r\nOpcode* Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n0F 32 RDMSR NP Valid Valid Read MSR specified by ECX into EDX:EAX.\r\nNOTES:\r\n* See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nReads the contents of a 64-bit model specific register (MSR) specified in the ECX register into registers EDX:EAX.\r\n(On processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The EDX register\r\nis loaded with the high-order 32 bits of the MSR and the EAX register is loaded with the low-order 32 bits. (On\r\nprocessors that support the Intel 64 architecture, the high-order 32 bits of each of RAX and RDX are cleared.) If\r\nfewer than 64 bits are implemented in the MSR being read, the values returned to EDX:EAX in unimplemented bit\r\nlocations are undefined.\r\nThis instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection\r\nexception #GP(0) will be generated. Specifying a reserved or unimplemented MSR address in ECX will also cause a\r\ngeneral protection exception.\r\nThe MSRs control functions for testability, execution tracing, performance-monitoring, and machine check errors.\r\nChapter 35, \"Model-Specific Registers (MSRs),\" in the Intel 64 and IA-32 Architectures Software Developer's\r\nManual, Volume 3C, lists all the MSRs that can be read with this instruction and their addresses. Note that each\r\nprocessor family has its own set of MSRs.\r\nThe CPUID instruction should be used to determine whether MSRs are supported (CPUID.01H:EDX[5] = 1) before\r\nusing this instruction.\r\n\r\nIA-32 Architecture Compatibility\r\nThe MSRs and the ability to read them with the RDMSR instruction were introduced into the IA-32 Architecture with\r\nthe Pentium processor. Execution of this instruction by an IA-32 processor earlier than the Pentium processor\r\nresults in an invalid opcode exception #UD.\r\nSee \"Changes to Instruction Behavior in VMX Non-Root Operation\" in Chapter 25 of the Intel 64 and IA-32 Archi-\r\ntectures Software Developer's Manual, Volume 3C, for more information about the behavior of this instruction in\r\nVMX non-root operation.\r\n\r\nOperation\r\nEDX:EAX <- MSR[ECX];\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the current privilege level is not 0.\r\n If the value in ECX specifies a reserved or unimplemented MSR address.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#GP If the value in ECX specifies a reserved or unimplemented MSR address.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) The RDMSR instruction is not recognized in virtual-8086 mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "RDMSR"
},
{
"description": "RDPID-Read Processor ID\r\nOpcode/ Op/ 64/32- CPUID Description\r\nInstruction En bit Feature Flag\r\n Mode\r\nF3 0F C7 /7 M N.E./V RDPID Read IA32_TSC_AUX into r32.\r\nRDPID r32\r\nF3 0F C7 /7 M V/N.E. RDPID Read IA32_TSC_AUX into r64.\r\nRDPID r64\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (w) NA NA NA\r\n\r\n\r\nDescription\r\nReads the value of the IA32_TSC_AUX MSR (address C0000103H) into the destination register. The value of CS.D\r\nand operand-size prefixes (66H and REX.W) do not affect the behavior of the RDPID instruction.\r\n\r\nOperation\r\n\r\nDEST <- IA32_TSC_AUX\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If the F2 prefix is used.\r\n If CPUID.7H.0:ECX.RDPID[bit 22] = 0.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "RDPID"
},
{
"description": "RDPKRU-Read Protection Key Rights for User Pages\r\nOpcode* Instruction Op/ 64/32bit CPUID Description\r\n En Mode Feature\r\n Support Flag\r\n0F 01 EE RDPKRU NP V/V OSPKE Reads PKRU into EAX.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nReads the value of PKRU into EAX and clears EDX. ECX must be 0 when RDPKRU is executed; otherwise, a general-\r\nprotection exception (#GP) occurs.\r\nRDPKRU can be executed only if CR4.PKE = 1; otherwise, an invalid-opcode exception (#UD) occurs. Software can\r\ndiscover the value of CR4.PKE by examining CPUID.(EAX=07H,ECX=0H):ECX.OSPKE [bit 4].\r\nOn processors that support the Intel 64 Architecture, the high-order 32-bits of RCX are ignored and the high-order\r\n32-bits of RDX and RAX are cleared.\r\n\r\nOperation\r\n\r\nIF (ECX = 0)\r\n THEN\r\n EAX <- PKRU;\r\n EDX <- 0;\r\n ELSE #GP(0);\r\nFI;\r\n\r\nFlags Affected\r\nNone.\r\n\r\nC/C++ Compiler Intrinsic Equivalent\r\nRDPKRU: uint32_t _rdpkru_u32(void);\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If ECX !=0\r\n#UD If the LOCK prefix is used.\r\n If CR4.PKE = 0.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "RDPKRU"
},
{
"description": "RDPMC-Read Performance-Monitoring Counters\r\nOpcode* Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n0F 33 RDPMC NP Valid Valid Read performance-monitoring counter\r\n specified by ECX into EDX:EAX.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nThe EAX register is loaded with the low-order 32 bits. The EDX register is loaded with the supported high-order bits\r\nof the counter. The number of high-order bits loaded into EDX is implementation specific on processors that do no\r\nsupport architectural performance monitoring. The width of fixed-function and general-purpose performance coun-\r\nters on processors supporting architectural performance monitoring are reported by CPUID 0AH leaf. See below for\r\nthe treatment of the EDX register for \"fast\" reads.\r\nThe ECX register specifies the counter type (if the processor supports architectural performance monitoring) and\r\ncounter index. Counter type is specified in ECX[30] to select one of two type of performance counters. If the\r\nprocessor does not support architectural performance monitoring, ECX[30:0] specifies the counter index; other-\r\nwise ECX[29:0] specifies the index relative to the base of each counter type. ECX[31] selects \"fast\" read mode if\r\nsupported. The two counter types are:\r\n. General-purpose or special-purpose performance counters are specified with ECX[30] = 0: The number of\r\n general-purpose performance counters on processor supporting architectural performance monitoring are\r\n reported by CPUID 0AH leaf. The number of general-purpose counters is model specific if the processor does\r\n not support architectural performance monitoring, see Chapter 18, \"Performance Monitoring\" of Intel 64 and\r\n IA-32 Architectures Software Developer's Manual, Volume 3B. Special-purpose counters are available only in\r\n selected processor members, see Table 4-16.\r\n. Fixed-function performance counter are specified with ECX[30] = 1. The number fixed-function performance\r\n counters is enumerated by CPUID 0AH leaf. See Chapter 30 of Intel 64 and IA-32 Architectures Software\r\n Developer's Manual, Volume 3B. This counter type is selected if ECX[30] is set.\r\nThe width of fixed-function performance counters and general-purpose performance counters on processor\r\nsupporting architectural performance monitoring are reported by CPUID 0AH leaf. The width of general-purpose\r\nperformance counters are 40-bits for processors that do not support architectural performance monitoring coun-\r\nters. The width of special-purpose performance counters are implementation specific.\r\nTable 4-16 lists valid indices of the general-purpose and special-purpose performance counters according to the\r\nDisplayFamily_DisplayModel values of CPUID encoding for each processor family (see CPUID instruction in Chapter\r\n3, \"Instruction Set Reference, A-L\" in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume\r\n2A).\r\n\r\n\r\n Table 4-16. Valid General and Special Purpose Performance Counter Index Range for RDPMC\r\n Processor Family DisplayFamily_DisplayModel/ Valid PMC Index General-purpose\r\n Other Signatures Range Counters\r\n P6 06H_01H, 06H_03H, 06H_05H, 0, 1 0, 1\r\n 06H_06H, 06H_07H, 06H_08H,\r\n 06H_0AH, 06H_0BH\r\n Processors Based on Intel NetBurst 0FH_00H, 0FH_01H, 0FH_02H, >= 0 and <= 17 >= 0 and <= 17\r\n microarchitecture (No L3) 0FH_03H, 0FH_04H, 0FH_06H\r\n Pentium M processors 06H_09H, 06H_0DH 0, 1 0, 1\r\n Processors Based on Intel NetBurst 0FH_03H, 0FH_04H) and (L3 is >= 0 and <= 25 >= 0 and <= 17\r\n microarchitecture (No L3) present)\r\n\r\n\r\n\r\n\r\n Table 4-16. Valid General and Special Purpose Performance Counter Index Range for RDPMC (Contd.)\r\n Processor Family DisplayFamily_DisplayModel/ Valid PMC Index General-purpose\r\n Other Signatures Range Counters\r\n Intel Core Solo and Intel Core Duo 06H_0EH 0, 1 0, 1\r\n processors, Dual-core Intel Xeon\r\n processor LV\r\n Intel Core2 Duo processor, Intel Xeon 06H_0FH 0, 1 0, 1\r\n processor 3000, 5100, 5300, 7300 Series -\r\n general-purpose PMC\r\n Intel Core2 Duo processor family, Intel 06H_17H 0, 1 0, 1\r\n Xeon processor 3100, 3300, 5200, 5400\r\n series - general-purpose PMC\r\n Intel Xeon processors 7400 series (06H_1DH) >= 0 and <= 9 0, 1\r\n \r\n 45 nm and 32 nm Intel Atom processors 06H_1CH, 06_26H, 06_27H, 0, 1 0, 1\r\n 06_35H, 06_36H\r\n Intel Atom processors based on 06H_37H, 06_4AH, 06_4DH, 0, 1 0, 1\r\n Silvermont or Airmont microarchitectures 06_5AH, 06_5DH, 06_4CH\r\n Next Generation Intel Atom processors 06H_5CH, 06_5FH 0-3 0-3\r\n based on Goldmont microarchitecture\r\n Intel processors based on the Nehalem, 06H_1AH, 06H_1EH, 06H_1FH, 0-3 0-3\r\n Westmere microarchitectures 06_25H, 06_2CH, 06H_2EH,\r\n 06_2FH\r\n Intel processors based on the Sandy 06H_2AH, 06H_2DH, 06H_3AH, 0-3 (0-7 if 0-3 (0-7 if\r\n Bridge, Ivy Bridge microarchitecture 06H_3EH HyperThreading is off) HyperThreading is off)\r\n Intel processors based on the Haswell, 06H_3CH, 06H_45H, 06H_46H, 0-3 (0-7 if 0-3 (0-7 if\r\n Broadwell, SkyLake microarchitectures 06H_3FH, 06_3DH, 06_47H, HyperThreading is off) HyperThreading is off)\r\n 4FH, 06_56H, 06_4EH, 06_5EH\r\n\r\nProcessors based on Intel NetBurst microarchitecture support \"fast\" (32-bit) and \"slow\" (40-bit) reads on the first\r\n18 performance counters. Selected this option using ECX[31]. If bit 31 is set, RDPMC reads only the low 32 bits of\r\nthe selected performance counter. If bit 31 is clear, all 40 bits are read. A 32-bit result is returned in EAX and EDX\r\nis set to 0. A 32-bit read executes faster on these processors than a full 40-bit read.\r\nOn processors based on Intel NetBurst microarchitecture with L3, performance counters with indices 18-25 are 32-\r\nbit counters. EDX is cleared after executing RDPMC for these counters.\r\nIn Intel Core 2 processor family, Intel Xeon processor 3000, 5100, 5300 and 7400 series, the fixed-function perfor-\r\nmance counters are 40-bits wide; they can be accessed by RDMPC with ECX between from 4000_0000H and\r\n4000_0002H.\r\nOn Intel Xeon processor 7400 series, there are eight 32-bit special-purpose counters addressable with indices 2-9,\r\nECX[30]=0.\r\nWhen in protected or virtual 8086 mode, the performance-monitoring counters enabled (PCE) flag in register CR4\r\nrestricts the use of the RDPMC instruction as follows. When the PCE flag is set, the RDPMC instruction can be\r\nexecuted at any privilege level; when the flag is clear, the instruction can only be executed at privilege level 0.\r\n(When in real-address mode, the RDPMC instruction is always enabled.)\r\nThe performance-monitoring counters can also be read with the RDMSR instruction, when executing at privilege\r\nlevel 0.\r\nThe performance-monitoring counters are event counters that can be programmed to count events such as the\r\nnumber of instructions decoded, number of interrupts received, or number of cache loads. Chapter 19, \"Perfor-\r\nmance Monitoring Events,\" in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B, lists\r\nthe events that can be counted for various processors in the Intel 64 and IA-32 architecture families.\r\nThe RDPMC instruction is not a serializing instruction; that is, it does not imply that all the events caused by the\r\npreceding instructions have been completed or that events caused by subsequent instructions have not begun. If\r\n\r\n\r\n\r\n\r\nan exact event count is desired, software must insert a serializing instruction (such as the CPUID instruction)\r\nbefore and/or after the RDPMC instruction.\r\nPerforming back-to-back fast reads are not guaranteed to be monotonic. To guarantee monotonicity on back-to-\r\nback reads, a serializing instruction must be placed between the two RDPMC instructions.\r\nThe RDPMC instruction can execute in 16-bit addressing mode or virtual-8086 mode; however, the full contents of\r\nthe ECX register are used to select the counter, and the event count is stored in the full EAX and EDX registers. The\r\nRDPMC instruction was introduced into the IA-32 Architecture in the Pentium Pro processor and the Pentium\r\nprocessor with MMX technology. The earlier Pentium processors have performance-monitoring counters, but they\r\nmust be read with the RDMSR instruction.\r\n\r\nOperation\r\n(* Intel processors that support architectural performance monitoring *)\r\n\r\nMost significant counter bit (MSCB) = 47\r\n\r\nIF ((CR4.PCE = 1) or (CPL = 0) or (CR0.PE = 0))\r\n THEN IF (ECX[30] = 1 and ECX[29:0] in valid fixed-counter range)\r\n EAX <- IA32_FIXED_CTR(ECX)[30:0];\r\n EDX <- IA32_FIXED_CTR(ECX)[MSCB:32];\r\n ELSE IF (ECX[30] = 0 and ECX[29:0] in valid general-purpose counter range)\r\n EAX <- PMC(ECX[30:0])[31:0];\r\n EDX <- PMC(ECX[30:0])[MSCB:32];\r\n ELSE (* ECX is not valid or CR4.PCE is 0 and CPL is 1, 2, or 3 and CR0.PE is 1 *)\r\n #GP(0);\r\nFI;\r\n\r\n(* Intel Core 2 Duo processor family and Intel Xeon processor 3000, 5100, 5300, 7400 series*)\r\n\r\nMost significant counter bit (MSCB) = 39\r\n\r\nIF ((CR4.PCE = 1) or (CPL = 0) or (CR0.PE = 0))\r\n THEN IF (ECX[30] = 1 and ECX[29:0] in valid fixed-counter range)\r\n EAX <- IA32_FIXED_CTR(ECX)[30:0];\r\n EDX <- IA32_FIXED_CTR(ECX)[MSCB:32];\r\n ELSE IF (ECX[30] = 0 and ECX[29:0] in valid general-purpose counter range)\r\n EAX <- PMC(ECX[30:0])[31:0];\r\n EDX <- PMC(ECX[30:0])[MSCB:32];\r\n ELSE IF (ECX[30] = 0 and ECX[29:0] in valid special-purpose counter range)\r\n EAX <- PMC(ECX[30:0])[31:0]; (* 32-bit read *)\r\n ELSE (* ECX is not valid or CR4.PCE is 0 and CPL is 1, 2, or 3 and CR0.PE is 1 *)\r\n #GP(0);\r\nFI;\r\n\r\n(* P6 family processors and Pentium processor with MMX technology *)\r\n\r\nIF (ECX = 0 or 1) and ((CR4.PCE = 1) or (CPL = 0) or (CR0.PE = 0))\r\n THEN\r\n EAX <- PMC(ECX)[31:0];\r\n EDX <- PMC(ECX)[39:32];\r\n ELSE (* ECX is not 0 or 1 or CR4.PCE is 0 and CPL is 1, 2, or 3 and CR0.PE is 1 *)\r\n #GP(0);\r\nFI;\r\n(* Processors based on Intel NetBurst microarchitecture *)\r\nIF ((CR4.PCE = 1) or (CPL = 0) or (CR0.PE = 0))\r\n THEN IF (ECX[30:0] = 0:17)\r\n THEN IF ECX[31] = 0\r\n\r\n\r\n\r\n THEN\r\n EAX <- PMC(ECX[30:0])[31:0]; (* 40-bit read *)\r\n EDX <- PMC(ECX[30:0])[39:32];\r\n ELSE (* ECX[31] = 1*)\r\n THEN\r\n EAX <- PMC(ECX[30:0])[31:0]; (* 32-bit read *)\r\n EDX <- 0;\r\n FI;\r\n ELSE IF (*64-bit Intel processor based on Intel NetBurst microarchitecture with L3 *)\r\n THEN IF (ECX[30:0] = 18:25 )\r\n EAX <- PMC(ECX[30:0])[31:0]; (* 32-bit read *)\r\n EDX <- 0;\r\n FI;\r\n ELSE (* Invalid PMC index in ECX[30:0], see Table 4-19. *)\r\n GP(0);\r\n FI;\r\nELSE (* CR4.PCE = 0 and (CPL = 1, 2, or 3) and CR0.PE = 1 *)\r\n #GP(0);\r\nFI;\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the current privilege level is not 0 and the PCE flag in the CR4 register is clear.\r\n If an invalid performance counter index is specified (see Table 4-16).\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If an invalid performance counter index is specified (see Table 4-16).\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If the PCE flag in the CR4 register is clear.\r\n If an invalid performance counter index is specified (see Table 4-16).\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the current privilege level is not 0 and the PCE flag in the CR4 register is clear.\r\n If an invalid performance counter index is specified (see Table 4-16).\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "RDPMC"
},
{
"description": "RDRAND-Read Random Number\r\nOpcode*/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F C7 /6 M V/V RDRAND Read a 16-bit random number and store in the\r\nRDRAND r16 destination register.\r\n\r\n0F C7 /6 M V/V RDRAND Read a 32-bit random number and store in the\r\nRDRAND r32 destination register.\r\n\r\nREX.W + 0F C7 /6 M V/I RDRAND Read a 64-bit random number and store in the\r\nRDRAND r64 destination register.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (w) NA NA NA\r\n\r\n\r\nDescription\r\nLoads a hardware generated random value and store it in the destination register. The size of the random value is\r\ndetermined by the destination register size and operating mode. The Carry Flag indicates whether a random value\r\nis available at the time the instruction is executed. CF=1 indicates that the data in the destination is valid. Other-\r\nwise CF=0 and the data in the destination operand will be returned as zeros for the specified width. All other flags\r\nare forced to 0 in either situation. Software must check the state of CF=1 for determining if a valid random value\r\nhas been returned, otherwise it is expected to loop and retry execution of RDRAND (see Intel 64 and IA-32 Archi-\r\ntectures Software Developer's Manual, Volume 1, Section 7.3.17, \"Random Number Generator Instructions\").\r\nThis instruction is available at all privilege levels.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.B permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bit oper-\r\nands. See the summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nIF HW_RND_GEN.ready = 1\r\n THEN\r\n CASE of\r\n osize is 64: DEST[63:0] <- HW_RND_GEN.data;\r\n osize is 32: DEST[31:0] <- HW_RND_GEN.data;\r\n osize is 16: DEST[15:0] <- HW_RND_GEN.data;\r\n ESAC\r\n CF <- 1;\r\n ELSE\r\n CASE of\r\n osize is 64: DEST[63:0] <- 0;\r\n osize is 32: DEST[31:0] <- 0;\r\n osize is 16: DEST[15:0] <- 0;\r\n ESAC\r\n CF <- 0;\r\nFI\r\nOF, SF, ZF, AF, PF <- 0;\r\n\r\nFlags Affected\r\nThe CF flag is set according to the result (see the \"Operation\" section above). The OF, SF, ZF, AF, and PF flags are\r\nset to 0.\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nRDRAND: int _rdrand16_step( unsigned short * );\r\nRDRAND: int _rdrand32_step( unsigned int * );\r\nRDRAND: int _rdrand64_step( unsigned __int64 *);\r\n\r\nProtected Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If the F2H or F3H prefix is used.\r\n If CPUID.01H:ECX.RDRAND[bit 30] = 0.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "RDRAND"
},
{
"description": "RDSEED-Read Random SEED\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 0F C7 /7 M V/V RDSEED Read a 16-bit NIST SP800-90B & C compliant random value and\r\n RDSEED r16 store in the destination register.\r\n\r\n 0F C7 /7 M V/V RDSEED Read a 32-bit NIST SP800-90B & C compliant random value and\r\n RDSEED r32 store in the destination register.\r\n\r\n REX.W + 0F C7 /7 M V/I RDSEED Read a 64-bit NIST SP800-90B & C compliant random value and\r\n RDSEED r64 store in the destination register.\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (w) NA NA NA\r\n\r\nDescription\r\nLoads a hardware generated random value and store it in the destination register. The random value is generated\r\nfrom an Enhanced NRBG (Non Deterministic Random Bit Generator) that is compliant to NIST SP800-90B and NIST\r\nSP800-90C in the XOR construction mode. The size of the random value is determined by the destination register\r\nsize and operating mode. The Carry Flag indicates whether a random value is available at the time the instruction\r\nis executed. CF=1 indicates that the data in the destination is valid. Otherwise CF=0 and the data in the destination\r\noperand will be returned as zeros for the specified width. All other flags are forced to 0 in either situation. Software\r\nmust check the state of CF=1 for determining if a valid random seed value has been returned, otherwise it is\r\nexpected to loop and retry execution of RDSEED (see Section 1.2).\r\nThe RDSEED instruction is available at all privilege levels. The RDSEED instruction executes normally either inside\r\nor outside a transaction region.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.B permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bit oper-\r\nands. See the summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nIF HW_NRND_GEN.ready = 1\r\n THEN\r\n CASE of\r\n osize is 64: DEST[63:0] <- HW_NRND_GEN.data;\r\n osize is 32: DEST[31:0] <- HW_NRND_GEN.data;\r\n osize is 16: DEST[15:0] <- HW_NRND_GEN.data;\r\n ESAC;\r\n CF <- 1;\r\n ELSE\r\n CASE of\r\n osize is 64: DEST[63:0] <- 0;\r\n osize is 32: DEST[31:0] <- 0;\r\n osize is 16: DEST[15:0] <- 0;\r\n ESAC;\r\n CF <- 0;\r\nFI;\r\n\r\nOF, SF, ZF, AF, PF <- 0;\r\n\r\n\r\n\r\n\r\nFlags Affected\r\n\r\nThe CF flag is set according to the result (see the \"Operation\" section above). The OF, SF, ZF, AF, and PF flags\r\nare set to 0.\r\n\r\nC/C++ Compiler Intrinsic Equivalent\r\nRDSEED int _rdseed16_step( unsigned short * );\r\nRDSEED int _rdseed32_step( unsigned int * );\r\nRDSEED int _rdseed64_step( unsigned __int64 *);\r\n\r\nProtected Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If the F2H or F3H prefix is used.\r\n If CPUID.(EAX=07H, ECX=0H):EBX.RDSEED[bit 18] = 0.\r\n\r\nReal-Address Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If the F2H or F3H prefix is used.\r\n If CPUID.(EAX=07H, ECX=0H):EBX.RDSEED[bit 18] = 0.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If the F2H or F3H prefix is used.\r\n If CPUID.(EAX=07H, ECX=0H):EBX.RDSEED[bit 18] = 0.\r\n\r\nCompatibility Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If the F2H or F3H prefix is used.\r\n If CPUID.(EAX=07H, ECX=0H):EBX.RDSEED[bit 18] = 0.\r\n\r\n64-Bit Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If the F2H or F3H prefix is used.\r\n If CPUID.(EAX=07H, ECX=0H):EBX.RDSEED[bit 18] = 0.\r\n\r\n\r\n\r\n\r\n",
"mnem": "RDSEED"
},
{
"description": "RDTSC-Read Time-Stamp Counter\r\n Opcode* Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F 31 RDTSC NP Valid Valid Read time-stamp counter into EDX:EAX.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nReads the current value of the processor's time-stamp counter (a 64-bit MSR) into the EDX:EAX registers. The EDX\r\nregister is loaded with the high-order 32 bits of the MSR and the EAX register is loaded with the low-order 32 bits.\r\n(On processors that support the Intel 64 architecture, the high-order 32 bits of each of RAX and RDX are cleared.)\r\nThe processor monotonically increments the time-stamp counter MSR every clock cycle and resets it to 0 whenever\r\nthe processor is reset. See \"Time Stamp Counter\" in Chapter 17 of the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 3B, for specific details of the time stamp counter behavior.\r\nThe time stamp disable (TSD) flag in register CR4 restricts the use of the RDTSC instruction as follows. When the\r\nflag is clear, the RDTSC instruction can be executed at any privilege level; when the flag is set, the instruction can\r\nonly be executed at privilege level 0.\r\nThe time-stamp counter can also be read with the RDMSR instruction, when executing at privilege level 0.\r\nThe RDTSC instruction is not a serializing instruction. It does not necessarily wait until all previous instructions\r\nhave been executed before reading the counter. Similarly, subsequent instructions may begin execution before the\r\nread operation is performed. If software requires RDTSC to be executed only after all previous instructions have\r\ncompleted locally, it can either use RDTSCP (if the processor supports that instruction) or execute the sequence\r\nLFENCE;RDTSC.\r\nThis instruction was introduced by the Pentium processor.\r\nSee \"Changes to Instruction Behavior in VMX Non-Root Operation\" in Chapter 25 of the Intel 64 and IA-32 Archi-\r\ntectures Software Developer's Manual, Volume 3C, for more information about the behavior of this instruction in\r\nVMX non-root operation.\r\n\r\nOperation\r\nIF (CR4.TSD = 0) or (CPL = 0) or (CR0.PE = 0)\r\n THEN EDX:EAX <- TimeStampCounter;\r\n ELSE (* CR4.TSD = 1 and (CPL = 1, 2, or 3) and CR0.PE = 1 *)\r\n #GP(0);\r\nFI;\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the TSD flag in register CR4 is set and the CPL is greater than 0.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If the TSD flag in register CR4 is set.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "RDTSC"
},
{
"description": "RDTSCP-Read Time-Stamp Counter and Processor ID\r\nOpcode* Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n0F 01 F9 RDTSCP NP Valid Valid Read 64-bit time-stamp counter and\r\n IA32_TSC_AUX value into EDX:EAX and ECX.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nReads the current value of the processor's time-stamp counter (a 64-bit MSR) into the EDX:EAX registers and also\r\nreads the value of the IA32_TSC_AUX MSR (address C0000103H) into the ECX register. The EDX register is loaded\r\nwith the high-order 32 bits of the IA32_TSC MSR; the EAX register is loaded with the low-order 32 bits of the\r\nIA32_TSC MSR; and the ECX register is loaded with the low-order 32-bits of IA32_TSC_AUX MSR. On processors\r\nthat support the Intel 64 architecture, the high-order 32 bits of each of RAX, RDX, and RCX are cleared.\r\nThe processor monotonically increments the time-stamp counter MSR every clock cycle and resets it to 0 whenever\r\nthe processor is reset. See \"Time Stamp Counter\" in Chapter 17 of the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 3B, for specific details of the time stamp counter behavior.\r\nThe time stamp disable (TSD) flag in register CR4 restricts the use of the RDTSCP instruction as follows. When the\r\nflag is clear, the RDTSCP instruction can be executed at any privilege level; when the flag is set, the instruction can\r\nonly be executed at privilege level 0.\r\nThe RDTSCP instruction waits until all previous instructions have been executed before reading the counter.\r\nHowever, subsequent instructions may begin execution before the read operation is performed.\r\nSee \"Changes to Instruction Behavior in VMX Non-Root Operation\" in Chapter 25 of the Intel 64 and IA-32 Archi-\r\ntectures Software Developer's Manual, Volume 3C, for more information about the behavior of this instruction in\r\nVMX non-root operation.\r\n\r\nOperation\r\nIF (CR4.TSD = 0) or (CPL = 0) or (CR0.PE = 0)\r\n THEN\r\n EDX:EAX <- TimeStampCounter;\r\n ECX <- IA32_TSC_AUX[31:0];\r\n ELSE (* CR4.TSD = 1 and (CPL = 1, 2, or 3) and CR0.PE = 1 *)\r\n #GP(0);\r\nFI;\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the TSD flag in register CR4 is set and the CPL is greater than 0.\r\n#UD If the LOCK prefix is used.\r\n If CPUID.80000001H:EDX.RDTSCP[bit 27] = 0.\r\n\r\nReal-Address Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If CPUID.80000001H:EDX.RDTSCP[bit 27] = 0.\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If the TSD flag in register CR4 is set.\r\n#UD If the LOCK prefix is used.\r\n If CPUID.80000001H:EDX.RDTSCP[bit 27] = 0.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "RDTSCP"
},
{
"description": "REP/REPE/REPZ/REPNE/REPNZ-Repeat String Operation Prefix\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n F3 6C REP INS m8, DX NP Valid Valid Input (E)CX bytes from port DX into ES:[(E)DI].\r\n F3 6C REP INS m8, DX NP Valid N.E. Input RCX bytes from port DX into [RDI].\r\n F3 6D REP INS m16, DX NP Valid Valid Input (E)CX words from port DX into ES:[(E)DI.]\r\n F3 6D REP INS m32, DX NP Valid Valid Input (E)CX doublewords from port DX into\r\n ES:[(E)DI].\r\n F3 6D REP INS r/m32, DX NP Valid N.E. Input RCX default size from port DX into [RDI].\r\n F3 A4 REP MOVS m8, m8 NP Valid Valid Move (E)CX bytes from DS:[(E)SI] to ES:[(E)DI].\r\n F3 REX.W A4 REP MOVS m8, m8 NP Valid N.E. Move RCX bytes from [RSI] to [RDI].\r\n F3 A5 REP MOVS m16, m16 NP Valid Valid Move (E)CX words from DS:[(E)SI] to ES:[(E)DI].\r\n F3 A5 REP MOVS m32, m32 NP Valid Valid Move (E)CX doublewords from DS:[(E)SI] to\r\n ES:[(E)DI].\r\n F3 REX.W A5 REP MOVS m64, m64 NP Valid N.E. Move RCX quadwords from [RSI] to [RDI].\r\n F3 6E REP OUTS DX, r/m8 NP Valid Valid Output (E)CX bytes from DS:[(E)SI] to port DX.\r\n F3 REX.W 6E REP OUTS DX, r/m8* NP Valid N.E. Output RCX bytes from [RSI] to port DX.\r\n F3 6F REP OUTS DX, r/m16 NP Valid Valid Output (E)CX words from DS:[(E)SI] to port DX.\r\n F3 6F REP OUTS DX, r/m32 NP Valid Valid Output (E)CX doublewords from DS:[(E)SI] to\r\n port DX.\r\n F3 REX.W 6F REP OUTS DX, r/m32 NP Valid N.E. Output RCX default size from [RSI] to port DX.\r\n F3 AC REP LODS AL NP Valid Valid Load (E)CX bytes from DS:[(E)SI] to AL.\r\n F3 REX.W AC REP LODS AL NP Valid N.E. Load RCX bytes from [RSI] to AL.\r\n F3 AD REP LODS AX NP Valid Valid Load (E)CX words from DS:[(E)SI] to AX.\r\n F3 AD REP LODS EAX NP Valid Valid Load (E)CX doublewords from DS:[(E)SI] to\r\n EAX.\r\n F3 REX.W AD REP LODS RAX NP Valid N.E. Load RCX quadwords from [RSI] to RAX.\r\n F3 AA REP STOS m8 NP Valid Valid Fill (E)CX bytes at ES:[(E)DI] with AL.\r\n F3 REX.W AA REP STOS m8 NP Valid N.E. Fill RCX bytes at [RDI] with AL.\r\n F3 AB REP STOS m16 NP Valid Valid Fill (E)CX words at ES:[(E)DI] with AX.\r\n F3 AB REP STOS m32 NP Valid Valid Fill (E)CX doublewords at ES:[(E)DI] with EAX.\r\n F3 REX.W AB REP STOS m64 NP Valid N.E. Fill RCX quadwords at [RDI] with RAX.\r\n F3 A6 REPE CMPS m8, m8 NP Valid Valid Find nonmatching bytes in ES:[(E)DI] and\r\n DS:[(E)SI].\r\n F3 REX.W A6 REPE CMPS m8, m8 NP Valid N.E. Find non-matching bytes in [RDI] and [RSI].\r\n F3 A7 REPE CMPS m16, m16 NP Valid Valid Find nonmatching words in ES:[(E)DI] and\r\n DS:[(E)SI].\r\n F3 A7 REPE CMPS m32, m32 NP Valid Valid Find nonmatching doublewords in ES:[(E)DI]\r\n and DS:[(E)SI].\r\n F3 REX.W A7 REPE CMPS m64, m64 NP Valid N.E. Find non-matching quadwords in [RDI] and\r\n [RSI].\r\n F3 AE REPE SCAS m8 NP Valid Valid Find non-AL byte starting at ES:[(E)DI].\r\n F3 REX.W AE REPE SCAS m8 NP Valid N.E. Find non-AL byte starting at [RDI].\r\n F3 AF REPE SCAS m16 NP Valid Valid Find non-AX word starting at ES:[(E)DI].\r\n F3 AF REPE SCAS m32 NP Valid Valid Find non-EAX doubleword starting at\r\n ES:[(E)DI].\r\n\r\n\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n F3 REX.W AF REPE SCAS m64 NP Valid N.E. Find non-RAX quadword starting at [RDI].\r\n F2 A6 REPNE CMPS m8, m8 NP Valid Valid Find matching bytes in ES:[(E)DI] and DS:[(E)SI].\r\n F2 REX.W A6 REPNE CMPS m8, m8 NP Valid N.E. Find matching bytes in [RDI] and [RSI].\r\n F2 A7 REPNE CMPS m16, m16 NP Valid Valid Find matching words in ES:[(E)DI] and\r\n DS:[(E)SI].\r\n F2 A7 REPNE CMPS m32, m32 NP Valid Valid Find matching doublewords in ES:[(E)DI] and\r\n DS:[(E)SI].\r\n F2 REX.W A7 REPNE CMPS m64, m64 NP Valid N.E. Find matching doublewords in [RDI] and [RSI].\r\n F2 AE REPNE SCAS m8 NP Valid Valid Find AL, starting at ES:[(E)DI].\r\n F2 REX.W AE REPNE SCAS m8 NP Valid N.E. Find AL, starting at [RDI].\r\n F2 AF REPNE SCAS m16 NP Valid Valid Find AX, starting at ES:[(E)DI].\r\n F2 AF REPNE SCAS m32 NP Valid Valid Find EAX, starting at ES:[(E)DI].\r\n F2 REX.W AF REPNE SCAS m64 NP Valid N.E. Find RAX, starting at [RDI].\r\n NOTES:\r\n * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nRepeats a string instruction the number of times specified in the count register or until the indicated condition of\r\nthe ZF flag is no longer met. The REP (repeat), REPE (repeat while equal), REPNE (repeat while not equal), REPZ\r\n(repeat while zero), and REPNZ (repeat while not zero) mnemonics are prefixes that can be added to one of the\r\nstring instructions. The REP prefix can be added to the INS, OUTS, MOVS, LODS, and STOS instructions, and the\r\nREPE, REPNE, REPZ, and REPNZ prefixes can be added to the CMPS and SCAS instructions. (The REPZ and REPNZ\r\nprefixes are synonymous forms of the REPE and REPNE prefixes, respectively.) The F3H prefix is defined for the\r\nfollowing instructions and undefined for the rest:\r\n . F3H as REP/REPE/REPZ for string and input/output instruction.\r\n . F3H is a mandatory prefix for POPCNT, LZCNT, and ADOX.\r\nThe REP prefixes apply only to one string instruction at a time. To repeat a block of instructions, use the LOOP\r\ninstruction or another looping construct. All of these repeat prefixes cause the associated instruction to be repeated\r\nuntil the count in register is decremented to 0. See Table 4-17.\r\n\r\n\r\n Table 4-17. Repeat Prefixes\r\n Repeat Prefix Termination Condition 1* Termination Condition 2\r\n REP RCX or (E)CX = 0 None\r\n REPE/REPZ RCX or (E)CX = 0 ZF = 0\r\n REPNE/REPNZ RCX or (E)CX = 0 ZF = 1\r\n NOTES:\r\n * Count register is CX, ECX or RCX by default, depending on attributes of the operating modes.\r\n\r\n\r\n\r\n\r\n\r\nThe REPE, REPNE, REPZ, and REPNZ prefixes also check the state of the ZF flag after each iteration and terminate\r\nthe repeat loop if the ZF flag is not in the specified state. When both termination conditions are tested, the cause\r\nof a repeat termination can be determined either by testing the count register with a JECXZ instruction or by\r\ntesting the ZF flag (with a JZ, JNZ, or JNE instruction).\r\nWhen the REPE/REPZ and REPNE/REPNZ prefixes are used, the ZF flag does not require initialization because both\r\nthe CMPS and SCAS instructions affect the ZF flag according to the results of the comparisons they make.\r\nA repeating string operation can be suspended by an exception or interrupt. When this happens, the state of the\r\nregisters is preserved to allow the string operation to be resumed upon a return from the exception or interrupt\r\nhandler. The source and destination registers point to the next string elements to be operated on, the EIP register\r\npoints to the string instruction, and the ECX register has the value it held following the last successful iteration of\r\nthe instruction. This mechanism allows long string operations to proceed without affecting the interrupt response\r\ntime of the system.\r\nWhen a fault occurs during the execution of a CMPS or SCAS instruction that is prefixed with REPE or REPNE, the\r\nEFLAGS value is restored to the state prior to the execution of the instruction. Since the SCAS and CMPS instruc-\r\ntions do not use EFLAGS as an input, the processor can resume the instruction after the page fault handler.\r\nUse the REP INS and REP OUTS instructions with caution. Not all I/O ports can handle the rate at which these\r\ninstructions execute. Note that a REP STOS instruction is the fastest way to initialize a large block of memory.\r\nIn 64-bit mode, the operand size of the count register is associated with the address size attribute. Thus the default\r\ncount register is RCX; REX.W has no effect on the address size and the count register. In 64-bit mode, if 67H is\r\nused to override address size attribute, the count register is ECX and any implicit source/destination operand will\r\nuse the corresponding 32-bit index register. See the summary chart at the beginning of this section for encoding\r\ndata and limits.\r\nREP INS may read from the I/O port without writing to the memory location if an exception or VM exit occurs due\r\nto the write (e.g. #PF). If this would be problematic, for example because the I/O port read has side-effects, soft-\r\nware should ensure the write to the memory location does not cause an exception or VM exit.\r\n\r\nOperation\r\nIF AddressSize = 16\r\n THEN\r\n Use CX for CountReg;\r\n Implicit Source/Dest operand for memory use of SI/DI;\r\n ELSE IF AddressSize = 64\r\n THEN Use RCX for CountReg;\r\n Implicit Source/Dest operand for memory use of RSI/RDI;\r\n ELSE\r\n Use ECX for CountReg;\r\n Implicit Source/Dest operand for memory use of ESI/EDI;\r\nFI;\r\nWHILE CountReg != 0\r\n DO\r\n Service pending interrupts (if any);\r\n Execute associated string instruction;\r\n CountReg <- (CountReg - 1);\r\n IF CountReg = 0\r\n THEN exit WHILE loop; FI;\r\n IF (Repeat prefix is REPZ or REPE) and (ZF = 0)\r\n or (Repeat prefix is REPNZ or REPNE) and (ZF = 1)\r\n THEN exit WHILE loop; FI;\r\n OD;\r\n\r\nFlags Affected\r\nNone; however, the CMPS and SCAS instructions do set the status flags in the EFLAGS register.\r\n\r\n\r\n\r\n\r\nExceptions (All Operating Modes)\r\nExceptions may be generated by an instruction associated with the prefix.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the memory address is in a non-canonical form.\r\n\r\n\r\n\r\n\r\n",
"mnem": "REP"
},
{
"description": "-R:REP",
"mnem": "REPE"
},
{
"description": "-R:REP",
"mnem": "REPNE"
},
{
"description": "-R:REP",
"mnem": "REPNZ"
},
{
"description": "-R:REP",
"mnem": "REPZ"
},
{
"description": "RET/RETN/RETF-Return from Procedure\r\n Opcode* Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n C3 RET NP Valid Valid Near return to calling procedure.\r\n CB RET NP Valid Valid Far return to calling procedure.\r\n C2 iw RET imm16 I Valid Valid Near return to calling procedure and pop\r\n imm16 bytes from stack.\r\n CA iw RET imm16 I Valid Valid Far return to calling procedure and pop imm16\r\n bytes from stack.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n I imm16 NA NA NA\r\n\r\n\r\nDescription\r\nTransfers program control to a return address located on the top of the stack. The address is usually placed on the\r\nstack by a CALL instruction, and the return is made to the instruction that follows the CALL instruction.\r\nThe optional source operand specifies the number of stack bytes to be released after the return address is popped;\r\nthe default is none. This operand can be used to release parameters from the stack that were passed to the called\r\nprocedure and are no longer needed. It must be used when the CALL instruction used to switch to a new procedure\r\nuses a call gate with a non-zero word count to access the new procedure. Here, the source operand for the RET\r\ninstruction must specify the same number of bytes as is specified in the word count field of the call gate.\r\nThe RET instruction can be used to execute three different types of returns:\r\n. Near return - A return to a calling procedure within the current code segment (the segment currently pointed\r\n to by the CS register), sometimes referred to as an intrasegment return.\r\n. Far return - A return to a calling procedure located in a different segment than the current code segment,\r\n sometimes referred to as an intersegment return.\r\n. Inter-privilege-level far return - A far return to a different privilege level than that of the currently\r\n executing program or procedure.\r\nThe inter-privilege-level return type can only be executed in protected mode. See the section titled \"Calling Proce-\r\ndures Using Call and RET\" in Chapter 6 of the Intel 64 and IA-32 Architectures Software Developer's Manual,\r\nVolume 1, for detailed information on near, far, and inter-privilege-level returns.\r\nWhen executing a near return, the processor pops the return instruction pointer (offset) from the top of the stack\r\ninto the EIP register and begins program execution at the new instruction pointer. The CS register is unchanged.\r\nWhen executing a far return, the processor pops the return instruction pointer from the top of the stack into the EIP\r\nregister, then pops the segment selector from the top of the stack into the CS register. The processor then begins\r\nprogram execution in the new code segment at the new instruction pointer.\r\nThe mechanics of an inter-privilege-level far return are similar to an intersegment return, except that the\r\nprocessor examines the privilege levels and access rights of the code and stack segments being returned to deter-\r\nmine if the control transfer is allowed to be made. The DS, ES, FS, and GS segment registers are cleared by the RET\r\ninstruction during an inter-privilege-level return if they refer to segments that are not allowed to be accessed at the\r\nnew privilege level. Since a stack switch also occurs on an inter-privilege level return, the ESP and SS registers are\r\nloaded from the stack.\r\nIf parameters are passed to the called procedure during an inter-privilege level call, the optional source operand\r\nmust be used with the RET instruction to release the parameters on the return. Here, the parameters are released\r\nboth from the called procedure's stack and the calling procedure's stack (that is, the stack being returned to).\r\nIn 64-bit mode, the default operation size of this instruction is the stack-address size, i.e. 64 bits. This applies to\r\nnear returns, not far returns; the default operation size of far returns is 32 bits.\r\n\r\n\r\n\r\nOperation\r\n(* Near return *)\r\nIF instruction = near return\r\n THEN;\r\n IF OperandSize = 32\r\n THEN\r\n IF top 4 bytes of stack not within stack limits\r\n THEN #SS(0); FI;\r\n EIP <- Pop();\r\n ELSE\r\n IF OperandSize = 64\r\n THEN\r\n IF top 8 bytes of stack not within stack limits\r\n THEN #SS(0); FI;\r\n RIP <- Pop();\r\n ELSE (* OperandSize = 16 *)\r\n IF top 2 bytes of stack not within stack limits\r\n THEN #SS(0); FI;\r\n tempEIP <- Pop();\r\n tempEIP <- tempEIP AND 0000FFFFH;\r\n IF tempEIP not within code segment limits\r\n THEN #GP(0); FI;\r\n EIP <- tempEIP;\r\n FI;\r\n FI;\r\n\r\n IF instruction has immediate operand\r\n THEN (* Release parameters from stack *)\r\n IF StackAddressSize = 32\r\n THEN\r\n ESP <- ESP + SRC;\r\n ELSE\r\n IF StackAddressSize = 64\r\n THEN\r\n RSP <- RSP + SRC;\r\n ELSE (* StackAddressSize = 16 *)\r\n SP <- SP + SRC;\r\n FI;\r\n FI;\r\n FI;\r\nFI;\r\n\r\n(* Real-address mode or virtual-8086 mode *)\r\nIF ((PE = 0) or (PE = 1 AND VM = 1)) and instruction = far return\r\n THEN\r\n IF OperandSize = 32\r\n THEN\r\n IF top 8 bytes of stack not within stack limits\r\n THEN #SS(0); FI;\r\n EIP <- Pop();\r\n CS <- Pop(); (* 32-bit pop, high-order 16 bits discarded *)\r\n ELSE (* OperandSize = 16 *)\r\n IF top 4 bytes of stack not within stack limits\r\n THEN #SS(0); FI;\r\n\r\n\r\n\r\n tempEIP <- Pop();\r\n tempEIP <- tempEIP AND 0000FFFFH;\r\n IF tempEIP not within code segment limits\r\n THEN #GP(0); FI;\r\n EIP <- tempEIP;\r\n CS <- Pop(); (* 16-bit pop *)\r\n FI;\r\n IF instruction has immediate operand\r\n THEN (* Release parameters from stack *)\r\n SP <- SP + (SRC AND FFFFH);\r\n FI;\r\nFI;\r\n\r\n(* Protected mode, not virtual-8086 mode *)\r\nIF (PE = 1 and VM = 0 and IA32_EFER.LMA = 0) and instruction = far return\r\n THEN\r\n IF OperandSize = 32\r\n THEN\r\n IF second doubleword on stack is not within stack limits\r\n THEN #SS(0); FI;\r\n ELSE (* OperandSize = 16 *)\r\n IF second word on stack is not within stack limits\r\n THEN #SS(0); FI;\r\n FI;\r\n IF return code segment selector is NULL\r\n THEN #GP(0); FI;\r\n IF return code segment selector addresses descriptor beyond descriptor table limit\r\n THEN #GP(selector); FI;\r\n Obtain descriptor to which return code segment selector points from descriptor table;\r\n IF return code segment descriptor is not a code segment\r\n THEN #GP(selector); FI;\r\n IF return code segment selector RPL < CPL\r\n THEN #GP(selector); FI;\r\n IF return code segment descriptor is conforming\r\n and return code segment DPL > return code segment selector RPL\r\n THEN #GP(selector); FI;\r\n IF return code segment descriptor is non-conforming and return code\r\n segment DPL != return code segment selector RPL\r\n THEN #GP(selector); FI;\r\n IF return code segment descriptor is not present\r\n THEN #NP(selector); FI:\r\n IF return code segment selector RPL > CPL\r\n THEN GOTO RETURN-TO-OUTER-PRIVILEGE-LEVEL;\r\n ELSE GOTO RETURN-TO-SAME-PRIVILEGE-LEVEL;\r\n FI;\r\nFI;\r\n\r\nRETURN-SAME-PRIVILEGE-LEVEL:\r\n IF the return instruction pointer is not within the return code segment limit\r\n THEN #GP(0); FI;\r\n IF OperandSize = 32\r\n THEN\r\n EIP <- Pop();\r\n CS <- Pop(); (* 32-bit pop, high-order 16 bits discarded *)\r\n\r\n\r\n\r\n ELSE (* OperandSize = 16 *)\r\n EIP <- Pop();\r\n EIP <- EIP AND 0000FFFFH;\r\n CS <- Pop(); (* 16-bit pop *)\r\n FI;\r\n IF instruction has immediate operand\r\n THEN (* Release parameters from stack *)\r\n IF StackAddressSize = 32\r\n THEN\r\n ESP <- ESP + SRC;\r\n ELSE (* StackAddressSize = 16 *)\r\n SP <- SP + SRC;\r\n FI;\r\n FI;\r\n\r\nRETURN-TO-OUTER-PRIVILEGE-LEVEL:\r\n IF top (16 + SRC) bytes of stack are not within stack limits (OperandSize = 32)\r\n or top (8 + SRC) bytes of stack are not within stack limits (OperandSize = 16)\r\n THEN #SS(0); FI;\r\n Read return segment selector;\r\n IF stack segment selector is NULL\r\n THEN #GP(0); FI;\r\n IF return stack segment selector index is not within its descriptor table limits\r\n THEN #GP(selector); FI;\r\n Read segment descriptor pointed to by return segment selector;\r\n IF stack segment selector RPL != RPL of the return code segment selector\r\n or stack segment is not a writable data segment\r\n or stack segment descriptor DPL != RPL of the return code segment selector\r\n THEN #GP(selector); FI;\r\n IF stack segment not present\r\n THEN #SS(StackSegmentSelector); FI;\r\n IF the return instruction pointer is not within the return code segment limit\r\n THEN #GP(0); FI;\r\n CPL <- ReturnCodeSegmentSelector(RPL);\r\n IF OperandSize = 32\r\n THEN\r\n EIP <- Pop();\r\n CS <- Pop(); (* 32-bit pop, high-order 16 bits discarded; segment descriptor loaded *)\r\n CS(RPL) <- CPL;\r\n IF instruction has immediate operand\r\n THEN (* Release parameters from called procedure's stack *)\r\n IF StackAddressSize = 32\r\n THEN\r\n ESP <- ESP + SRC;\r\n ELSE (* StackAddressSize = 16 *)\r\n SP <- SP + SRC;\r\n FI;\r\n FI;\r\n tempESP <- Pop();\r\n tempSS <- Pop(); (* 32-bit pop, high-order 16 bits discarded; seg. descriptor loaded *)\r\n ESP <- tempESP;\r\n SS <- tempSS;\r\n ELSE (* OperandSize = 16 *)\r\n EIP <- Pop();\r\n\r\n\r\n\r\n EIP <- EIP AND 0000FFFFH;\r\n CS <- Pop(); (* 16-bit pop; segment descriptor loaded *)\r\n CS(RPL) <- CPL;\r\n IF instruction has immediate operand\r\n THEN (* Release parameters from called procedure's stack *)\r\n IF StackAddressSize = 32\r\n THEN\r\n ESP <- ESP + SRC;\r\n ELSE (* StackAddressSize = 16 *)\r\n SP <- SP + SRC;\r\n FI;\r\n FI;\r\n tempESP <- Pop();\r\n tempSS <- Pop(); (* 16-bit pop; segment descriptor loaded *)\r\n ESP <- tempESP;\r\n SS <- tempSS;\r\n FI;\r\n\r\n FOR each of segment register (ES, FS, GS, and DS)\r\n DO\r\n IF segment register points to data or non-conforming code segment\r\n and CPL > segment descriptor DPL (* DPL in hidden part of segment register *)\r\n THEN SegmentSelector <- 0; (* Segment selector invalid *)\r\n FI;\r\n OD;\r\n\r\n IF instruction has immediate operand\r\n THEN (* Release parameters from calling procedure's stack *)\r\n IF StackAddressSize = 32\r\n THEN\r\n ESP <- ESP + SRC;\r\n ELSE (* StackAddressSize = 16 *)\r\n SP <- SP + SRC;\r\n FI;\r\n FI;\r\n\r\n(* IA-32e Mode *)\r\n IF (PE = 1 and VM = 0 and IA32_EFER.LMA = 1) and instruction = far return\r\n THEN\r\n IF OperandSize = 32\r\n THEN\r\n IF second doubleword on stack is not within stack limits\r\n THEN #SS(0); FI;\r\n IF first or second doubleword on stack is not in canonical space\r\n THEN #SS(0); FI;\r\n ELSE\r\n IF OperandSize = 16\r\n THEN\r\n IF second word on stack is not within stack limits\r\n THEN #SS(0); FI;\r\n IF first or second word on stack is not in canonical space\r\n THEN #SS(0); FI;\r\n ELSE (* OperandSize = 64 *)\r\n IF first or second quadword on stack is not in canonical space\r\n\r\n\r\n\r\n THEN #SS(0); FI;\r\n FI\r\n FI;\r\n IF return code segment selector is NULL\r\n THEN GP(0); FI;\r\n IF return code segment selector addresses descriptor beyond descriptor table limit\r\n THEN GP(selector); FI;\r\n IF return code segment selector addresses descriptor in non-canonical space\r\n THEN GP(selector); FI;\r\n Obtain descriptor to which return code segment selector points from descriptor table;\r\n IF return code segment descriptor is not a code segment\r\n THEN #GP(selector); FI;\r\n IF return code segment descriptor has L-bit = 1 and D-bit = 1\r\n THEN #GP(selector); FI;\r\n IF return code segment selector RPL < CPL\r\n THEN #GP(selector); FI;\r\n IF return code segment descriptor is conforming\r\n and return code segment DPL > return code segment selector RPL\r\n THEN #GP(selector); FI;\r\n IF return code segment descriptor is non-conforming\r\n and return code segment DPL != return code segment selector RPL\r\n THEN #GP(selector); FI;\r\n IF return code segment descriptor is not present\r\n THEN #NP(selector); FI:\r\n IF return code segment selector RPL > CPL\r\n THEN GOTO IA-32E-MODE-RETURN-TO-OUTER-PRIVILEGE-LEVEL;\r\n ELSE GOTO IA-32E-MODE-RETURN-SAME-PRIVILEGE-LEVEL;\r\n FI;\r\n FI;\r\n\r\nIA-32E-MODE-RETURN-SAME-PRIVILEGE-LEVEL:\r\nIF the return instruction pointer is not within the return code segment limit\r\n THEN #GP(0); FI;\r\nIF the return instruction pointer is not within canonical address space\r\n THEN #GP(0); FI;\r\nIF OperandSize = 32\r\n THEN\r\n EIP <- Pop();\r\n CS <- Pop(); (* 32-bit pop, high-order 16 bits discarded *)\r\n ELSE\r\n IF OperandSize = 16\r\n THEN\r\n EIP <- Pop();\r\n EIP <- EIP AND 0000FFFFH;\r\n CS <- Pop(); (* 16-bit pop *)\r\n ELSE (* OperandSize = 64 *)\r\n RIP <- Pop();\r\n CS <- Pop(); (* 64-bit pop, high-order 48 bits discarded *)\r\n FI;\r\nFI;\r\nIF instruction has immediate operand\r\n THEN (* Release parameters from stack *)\r\n IF StackAddressSize = 32\r\n THEN\r\n\r\n\r\n\r\n ESP <- ESP + SRC;\r\n ELSE\r\n IF StackAddressSize = 16\r\n THEN\r\n SP <- SP + SRC;\r\n ELSE (* StackAddressSize = 64 *)\r\n RSP <- RSP + SRC;\r\n FI;\r\n FI;\r\nFI;\r\n\r\nIA-32E-MODE-RETURN-TO-OUTER-PRIVILEGE-LEVEL:\r\nIF top (16 + SRC) bytes of stack are not within stack limits (OperandSize = 32)\r\nor top (8 + SRC) bytes of stack are not within stack limits (OperandSize = 16)\r\n THEN #SS(0); FI;\r\nIF top (16 + SRC) bytes of stack are not in canonical address space (OperandSize = 32)\r\nor top (8 + SRC) bytes of stack are not in canonical address space (OperandSize = 16)\r\nor top (32 + SRC) bytes of stack are not in canonical address space (OperandSize = 64)\r\n THEN #SS(0); FI;\r\nRead return stack segment selector;\r\nIF stack segment selector is NULL\r\n THEN\r\n IF new CS descriptor L-bit = 0\r\n THEN #GP(selector);\r\n IF stack segment selector RPL = 3\r\n THEN #GP(selector);\r\nFI;\r\nIF return stack segment descriptor is not within descriptor table limits\r\n THEN #GP(selector); FI;\r\nIF return stack segment descriptor is in non-canonical address space\r\n THEN #GP(selector); FI;\r\nRead segment descriptor pointed to by return segment selector;\r\nIF stack segment selector RPL != RPL of the return code segment selector\r\nor stack segment is not a writable data segment\r\nor stack segment descriptor DPL != RPL of the return code segment selector\r\n THEN #GP(selector); FI;\r\nIF stack segment not present\r\n THEN #SS(StackSegmentSelector); FI;\r\nIF the return instruction pointer is not within the return code segment limit\r\n THEN #GP(0); FI:\r\nIF the return instruction pointer is not within canonical address space\r\n THEN #GP(0); FI;\r\nCPL <- ReturnCodeSegmentSelector(RPL);\r\nIF OperandSize = 32\r\n THEN\r\n EIP <- Pop();\r\n CS <- Pop(); (* 32-bit pop, high-order 16 bits discarded, segment descriptor loaded *)\r\n CS(RPL) <- CPL;\r\n IF instruction has immediate operand\r\n THEN (* Release parameters from called procedure's stack *)\r\n IF StackAddressSize = 32\r\n THEN\r\n ESP <- ESP + SRC;\r\n ELSE\r\n\r\n\r\n\r\n IF StackAddressSize = 16\r\n THEN\r\n SP <- SP + SRC;\r\n ELSE (* StackAddressSize = 64 *)\r\n RSP <- RSP + SRC;\r\n FI;\r\n FI;\r\n FI;\r\n tempESP <- Pop();\r\n tempSS <- Pop(); (* 32-bit pop, high-order 16 bits discarded, segment descriptor loaded *)\r\n ESP <- tempESP;\r\n SS <- tempSS;\r\n ELSE\r\n IF OperandSize = 16\r\n THEN\r\n EIP <- Pop();\r\n EIP <- EIP AND 0000FFFFH;\r\n CS <- Pop(); (* 16-bit pop; segment descriptor loaded *)\r\n CS(RPL) <- CPL;\r\n IF instruction has immediate operand\r\n THEN (* Release parameters from called procedure's stack *)\r\n IF StackAddressSize = 32\r\n THEN\r\n ESP <- ESP + SRC;\r\n ELSE\r\n IF StackAddressSize = 16\r\n THEN\r\n SP <- SP + SRC;\r\n ELSE (* StackAddressSize = 64 *)\r\n RSP <- RSP + SRC;\r\n FI;\r\n FI;\r\n FI;\r\n tempESP <- Pop();\r\n tempSS <- Pop(); (* 16-bit pop; segment descriptor loaded *)\r\n ESP <- tempESP;\r\n SS <- tempSS;\r\n ELSE (* OperandSize = 64 *)\r\n RIP <- Pop();\r\n CS <- Pop(); (* 64-bit pop; high-order 48 bits discarded; seg. descriptor loaded *)\r\n CS(RPL) <- CPL;\r\n IF instruction has immediate operand\r\n THEN (* Release parameters from called procedure's stack *)\r\n RSP <- RSP + SRC;\r\n FI;\r\n tempESP <- Pop();\r\n tempSS <- Pop(); (* 64-bit pop; high-order 48 bits discarded; seg. desc. loaded *)\r\n ESP <- tempESP;\r\n SS <- tempSS;\r\n FI;\r\nFI;\r\n\r\nFOR each of segment register (ES, FS, GS, and DS)\r\n DO\r\n\r\n\r\n\r\n IF segment register points to data or non-conforming code segment\r\n and CPL > segment descriptor DPL; (* DPL in hidden part of segment register *)\r\n THEN SegmentSelector <- 0; (* SegmentSelector invalid *)\r\n FI;\r\n OD;\r\n\r\nIF instruction has immediate operand\r\n THEN (* Release parameters from calling procedure's stack *)\r\n IF StackAddressSize = 32\r\n THEN\r\n ESP <- ESP + SRC;\r\n ELSE\r\n IF StackAddressSize = 16\r\n THEN\r\n SP <- SP + SRC;\r\n ELSE (* StackAddressSize = 64 *)\r\n RSP <- RSP + SRC;\r\n FI;\r\n FI;\r\nFI;\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the return code or stack segment selector NULL.\r\n If the return instruction pointer is not within the return code segment limit\r\n#GP(selector) If the RPL of the return code segment selector is less then the CPL.\r\n If the return code or stack segment selector index is not within its descriptor table limits.\r\n If the return code segment descriptor does not indicate a code segment.\r\n If the return code segment is non-conforming and the segment selector's DPL is not equal to\r\n the RPL of the code segment's segment selector\r\n If the return code segment is conforming and the segment selector's DPL greater than the RPL\r\n of the code segment's segment selector\r\n If the stack segment is not a writable data segment.\r\n If the stack segment selector RPL is not equal to the RPL of the return code segment selector.\r\n If the stack segment descriptor DPL is not equal to the RPL of the return code segment\r\n selector.\r\n#SS(0) If the top bytes of stack are not within stack limits.\r\n If the return stack segment is not present.\r\n#NP(selector) If the return code segment is not present.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If an unaligned memory access occurs when the CPL is 3 and alignment checking is enabled.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If the return instruction pointer is not within the return code segment limit\r\n#SS If the top bytes of stack are not within stack limits.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If the return instruction pointer is not within the return code segment limit\r\n\r\n\r\n\r\n#SS(0) If the top bytes of stack are not within stack limits.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If an unaligned memory access occurs when alignment checking is enabled.\r\n\r\nCompatibility Mode Exceptions\r\nSame as 64-bit mode exceptions.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the return instruction pointer is non-canonical.\r\n If the return instruction pointer is not within the return code segment limit.\r\n If the stack segment selector is NULL going back to compatibility mode.\r\n If the stack segment selector is NULL going back to CPL3 64-bit mode.\r\n If a NULL stack segment selector RPL is not equal to CPL going back to non-CPL3 64-bit mode.\r\n If the return code segment selector is NULL.\r\n#GP(selector) If the proposed segment descriptor for a code segment does not indicate it is a code segment.\r\n If the proposed new code segment descriptor has both the D-bit and L-bit set.\r\n If the DPL for a nonconforming-code segment is not equal to the RPL of the code segment\r\n selector.\r\n If CPL is greater than the RPL of the code segment selector.\r\n If the DPL of a conforming-code segment is greater than the return code segment selector\r\n RPL.\r\n If a segment selector index is outside its descriptor table limits.\r\n If a segment descriptor memory address is non-canonical.\r\n If the stack segment is not a writable data segment.\r\n If the stack segment descriptor DPL is not equal to the RPL of the return code segment\r\n selector.\r\n If the stack segment selector RPL is not equal to the RPL of the return code segment selector.\r\n#SS(0) If an attempt to pop a value off the stack violates the SS limit.\r\n If an attempt to pop a value off the stack causes a non-canonical address to be referenced.\r\n#NP(selector) If the return code or stack segment is not present.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "RET"
},
{
"description": "-R:RET",
"mnem": "RETF"
},
{
"description": "-R:RET",
"mnem": "RETN"
},
{
"description": "-R:RCL",
"mnem": "ROL"
},
{
"description": "-R:RCL",
"mnem": "ROR"
},
{
"description": "RORX - Rotate Right Logical Without Affecting Flags\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En -bit Feature\r\n Mode Flag\r\n VEX.LZ.F2.0F3A.W0 F0 /r ib RMI V/V BMI2 Rotate 32-bit r/m32 right imm8 times without affecting arithmetic\r\n RORX r32, r/m32, imm8 flags.\r\n VEX.LZ.F2.0F3A.W1 F0 /r ib RMI V/N.E. BMI2 Rotate 64-bit r/m64 right imm8 times without affecting arithmetic\r\n RORX r64, r/m64, imm8 flags.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (w) ModRM:r/m (r) Imm8 NA\r\n\r\n\r\nDescription\r\nRotates the bits of second operand right by the count value specified in imm8 without affecting arithmetic flags.\r\nThe RORX instruction does not read or write the arithmetic flags.\r\nThis instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in\r\n64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An\r\nattempt to execute this instruction with VEX.L not equal to 0 will cause #UD.\r\n\r\nOperation\r\nIF (OperandSize = 32)\r\n y <- imm8 AND 1FH;\r\n DEST <- (SRC >> y) | (SRC << (32-y));\r\nELSEIF (OperandSize = 64 )\r\n y <- imm8 AND 3FH;\r\n DEST <- (SRC >> y) | (SRC << (64-y));\r\nENDIF\r\n\r\nFlags Affected\r\nNone\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nAuto-generated from high-level language.\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Section 2.5.1, \"Exception Conditions for VEX-Encoded GPR Instructions\", Table 2-29; additionally\r\n#UD If VEX.W = 1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "RORX"
},
{
"description": "ROUNDPD - Round Packed Double Precision Floating-Point Values\r\n Opcode*/ Op/ 64/32 bit CPUID Description\r\n Instruction En Mode Feature\r\n Support Flag\r\n 66 0F 3A 09 /r ib RMI V/V SSE4_1 Round packed double precision floating-point\r\n ROUNDPD xmm1, xmm2/m128, imm8 values in xmm2/m128 and place the result in\r\n xmm1. The rounding mode is determined by\r\n imm8.\r\n VEX.128.66.0F3A.WIG 09 /r ib RMI V/V AVX Round packed double-precision floating-point\r\n VROUNDPD xmm1, xmm2/m128, imm8 values in xmm2/m128 and place the result in\r\n xmm1. The rounding mode is determined by\r\n imm8.\r\n VEX.256.66.0F3A.WIG 09 /r ib RMI V/V AVX Round packed double-precision floating-point\r\n VROUNDPD ymm1, ymm2/m256, imm8 values in ymm2/m256 and place the result in\r\n ymm1. The rounding mode is determined by\r\n imm8.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (w) ModRM:r/m (r) imm8 NA\r\n\r\n\r\nDescription\r\nRound the 2 double-precision floating-point values in the source operand (second operand) using the rounding\r\nmode specified in the immediate operand (third operand) and place the results in the destination operand (first\r\noperand). The rounding process rounds each input floating-point value to an integer value and returns the integer\r\nresult as a double-precision floating-point value.\r\nThe immediate operand specifies control fields for the rounding operation, three bit fields are defined and shown in\r\nFigure 4-24. Bit 3 of the immediate byte controls processor behavior for a precision exception, bit 2 selects the\r\nsource of rounding mode control. Bits 1:0 specify a non-sticky rounding-mode value (Table 4-18 lists the encoded\r\nvalues for rounding-mode field).\r\nThe Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an\r\nSNaN then it will be converted to a QNaN. If DAZ is set to '1 then denormals will be converted to zero before\r\nrounding.\r\n128-bit Legacy SSE version: The second source can be an XMM register or 128-bit memory location. The destina-\r\ntion is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding YMM\r\nregister destination are unmodified.\r\nVEX.128 encoded version: the source operand second source operand or a 128-bit memory location. The destina-\r\ntion operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are\r\nzeroed.\r\nVEX.256 encoded version: The source operand is a YMM register or a 256-bit memory location. The destination\r\noperand is a YMM register.\r\nNote: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\n 8 3 2 1 0\r\n\r\n Reserved\r\n\r\n\r\n\r\n P - Precision Mask; 0: normal, 1: inexact\r\n RS - Rounding select; 1: MXCSR.RC, 0: Imm8.RC\r\n RC - Rounding mode\r\n\r\n\r\n Figure 4-24. Bit Control Fields of Immediate Byte for ROUNDxx Instruction\r\n\r\n\r\n Table 4-18. Rounding Modes and Encoding of Rounding Control (RC) Field\r\n Rounding RC Field Description\r\n Mode Setting\r\n Round to 00B Rounded result is the closest to the infinitely precise result. If two values are equally close, the result is\r\n nearest (even) the even value (i.e., the integer value with the least-significant bit of zero).\r\n Round down 01B Rounded result is closest to but no greater than the infinitely precise result.\r\n (toward -inf)\r\n Round up 10B Rounded result is closest to but no less than the infinitely precise result.\r\n (toward +inf)\r\n Round toward 11B Rounded result is closest to but no greater in absolute value than the infinitely precise result.\r\n zero (Truncate)\r\n\r\nOperation\r\nIF (imm[2] = '1)\r\n THEN // rounding mode is determined by MXCSR.RC\r\n DEST[63:0] <- ConvertDPFPToInteger_M(SRC[63:0]);\r\n DEST[127:64] <- ConvertDPFPToInteger_M(SRC[127:64]);\r\n ELSE // rounding mode is determined by IMM8.RC\r\n DEST[63:0] <- ConvertDPFPToInteger_Imm(SRC[63:0]);\r\n DEST[127:64] <- ConvertDPFPToInteger_Imm(SRC[127:64]);\r\nFI\r\n\r\nROUNDPD (128-bit Legacy SSE version)\r\nDEST[63:0] <- RoundToInteger(SRC[63:0]], ROUND_CONTROL)\r\nDEST[127:64] <- RoundToInteger(SRC[127:64]], ROUND_CONTROL)\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVROUNDPD (VEX.128 encoded version)\r\nDEST[63:0] <- RoundToInteger(SRC[63:0]], ROUND_CONTROL)\r\nDEST[127:64] <- RoundToInteger(SRC[127:64]], ROUND_CONTROL)\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVROUNDPD (VEX.256 encoded version)\r\nDEST[63:0] <- RoundToInteger(SRC[63:0], ROUND_CONTROL)\r\nDEST[127:64] <- RoundToInteger(SRC[127:64]], ROUND_CONTROL)\r\nDEST[191:128] <- RoundToInteger(SRC[191:128]], ROUND_CONTROL)\r\nDEST[255:192] <- RoundToInteger(SRC[255:192] ], ROUND_CONTROL)\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n__m128 _mm_round_pd(__m128d s1, int iRoundMode);\r\n__m128 _mm_floor_pd(__m128d s1);\r\n__m128 _mm_ceil_pd(__m128d s1)\r\n__m256 _mm256_round_pd(__m256d s1, int iRoundMode);\r\n__m256 _mm256_floor_pd(__m256d s1);\r\n__m256 _mm256_ceil_pd(__m256d s1)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid (signaled only if SRC = SNaN)\r\nPrecision (signaled only if imm[3] = '0; if imm[3] = '1, then the Precision Mask in the MXSCSR is ignored and preci-\r\nsion exception is not signaled.)\r\nNote that Denormal is not signaled by ROUNDPD.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 2; additionally\r\n#UD If VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "ROUNDPD"
},
{
"description": "ROUNDPS - Round Packed Single Precision Floating-Point Values\r\nOpcode*/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n66 0F 3A 08 RMI V/V SSE4_1 Round packed single precision floating-point\r\n/r ib values in xmm2/m128 and place the result in\r\nROUNDPS xmm1, xmm2/m128, imm8 xmm1. The rounding mode is determined by\r\n imm8.\r\nVEX.128.66.0F3A.WIG 08 /r ib RMI V/V AVX Round packed single-precision floating-point\r\nVROUNDPS xmm1, xmm2/m128, imm8 values in xmm2/m128 and place the result in\r\n xmm1. The rounding mode is determined by\r\n imm8.\r\nVEX.256.66.0F3A.WIG 08 /r ib RMI V/V AVX Round packed single-precision floating-point\r\nVROUNDPS ymm1, ymm2/m256, imm8 values in ymm2/m256 and place the result in\r\n ymm1. The rounding mode is determined by\r\n imm8.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (w) ModRM:r/m (r) imm8 NA\r\n\r\n\r\nDescription\r\nRound the 4 single-precision floating-point values in the source operand (second operand) using the rounding\r\nmode specified in the immediate operand (third operand) and place the results in the destination operand (first\r\noperand). The rounding process rounds each input floating-point value to an integer value and returns the integer\r\nresult as a single-precision floating-point value.\r\nThe immediate operand specifies control fields for the rounding operation, three bit fields are defined and shown in\r\nFigure 4-24. Bit 3 of the immediate byte controls processor behavior for a precision exception, bit 2 selects the\r\nsource of rounding mode control. Bits 1:0 specify a non-sticky rounding-mode value (Table 4-18 lists the encoded\r\nvalues for rounding-mode field).\r\nThe Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an\r\nSNaN then it will be converted to a QNaN. If DAZ is set to '1 then denormals will be converted to zero before\r\nrounding.\r\n128-bit Legacy SSE version: The second source can be an XMM register or 128-bit memory location. The destina-\r\ntion is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding YMM\r\nregister destination are unmodified.\r\nVEX.128 encoded version: the source operand second source operand or a 128-bit memory location. The destina-\r\ntion operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are\r\nzeroed.\r\nVEX.256 encoded version: The source operand is a YMM register or a 256-bit memory location. The destination\r\noperand is a YMM register.\r\nNote: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIF (imm[2] = '1)\r\n THEN // rounding mode is determined by MXCSR.RC\r\n DEST[31:0] <- ConvertSPFPToInteger_M(SRC[31:0]);\r\n DEST[63:32] <- ConvertSPFPToInteger_M(SRC[63:32]);\r\n DEST[95:64] <- ConvertSPFPToInteger_M(SRC[95:64]);\r\n DEST[127:96] <- ConvertSPFPToInteger_M(SRC[127:96]);\r\n ELSE // rounding mode is determined by IMM8.RC\r\n DEST[31:0] <- ConvertSPFPToInteger_Imm(SRC[31:0]);\r\n DEST[63:32] <- ConvertSPFPToInteger_Imm(SRC[63:32]);\r\n DEST[95:64] <- ConvertSPFPToInteger_Imm(SRC[95:64]);\r\n DEST[127:96] <- ConvertSPFPToInteger_Imm(SRC[127:96]);\r\nFI;\r\n\r\nROUNDPS(128-bit Legacy SSE version)\r\nDEST[31:0] <- RoundToInteger(SRC[31:0], ROUND_CONTROL)\r\nDEST[63:32] <- RoundToInteger(SRC[63:32], ROUND_CONTROL)\r\nDEST[95:64] <- RoundToInteger(SRC[95:64]], ROUND_CONTROL)\r\nDEST[127:96] <- RoundToInteger(SRC[127:96]], ROUND_CONTROL)\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVROUNDPS (VEX.128 encoded version)\r\nDEST[31:0] <- RoundToInteger(SRC[31:0], ROUND_CONTROL)\r\nDEST[63:32] <- RoundToInteger(SRC[63:32], ROUND_CONTROL)\r\nDEST[95:64] <- RoundToInteger(SRC[95:64]], ROUND_CONTROL)\r\nDEST[127:96] <- RoundToInteger(SRC[127:96]], ROUND_CONTROL)\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVROUNDPS (VEX.256 encoded version)\r\nDEST[31:0] <- RoundToInteger(SRC[31:0], ROUND_CONTROL)\r\nDEST[63:32] <- RoundToInteger(SRC[63:32], ROUND_CONTROL)\r\nDEST[95:64] <- RoundToInteger(SRC[95:64]], ROUND_CONTROL)\r\nDEST[127:96] <- RoundToInteger(SRC[127:96]], ROUND_CONTROL)\r\nDEST[159:128] <- RoundToInteger(SRC[159:128]], ROUND_CONTROL)\r\nDEST[191:160] <- RoundToInteger(SRC[191:160]], ROUND_CONTROL)\r\nDEST[223:192] <- RoundToInteger(SRC[223:192] ], ROUND_CONTROL)\r\nDEST[255:224] <- RoundToInteger(SRC[255:224] ], ROUND_CONTROL)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n__m128 _mm_round_ps(__m128 s1, int iRoundMode);\r\n__m128 _mm_floor_ps(__m128 s1);\r\n__m128 _mm_ceil_ps(__m128 s1)\r\n__m256 _mm256_round_ps(__m256 s1, int iRoundMode);\r\n__m256 _mm256_floor_ps(__m256 s1);\r\n__m256 _mm256_ceil_ps(__m256 s1)\r\n\r\n\r\n\r\n\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid (signaled only if SRC = SNaN)\r\nPrecision (signaled only if imm[3] = '0; if imm[3] = '1, then the Precision Mask in the MXSCSR is ignored and preci-\r\nsion exception is not signaled.)\r\nNote that Denormal is not signaled by ROUNDPS.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 2; additionally\r\n#UD If VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "ROUNDPS"
},
{
"description": "ROUNDSD - Round Scalar Double Precision Floating-Point Values\r\n Opcode*/ Op/ 64/32 bit CPUID Description\r\n Instruction En Mode Feature\r\n Support Flag\r\n 66 0F 3A 0B /r ib RMI V/V SSE4_1 Round the low packed double precision\r\n ROUNDSD xmm1, xmm2/m64, imm8 floating-point value in xmm2/m64 and place\r\n the result in xmm1. The rounding mode is\r\n determined by imm8.\r\n VEX.NDS.LIG.66.0F3A.WIG 0B /r ib RVMI V/V AVX Round the low packed double precision\r\n VROUNDSD xmm1, xmm2, xmm3/m64, imm8 floating-point value in xmm3/m64 and place\r\n the result in xmm1. The rounding mode is\r\n determined by imm8. Upper packed double\r\n precision floating-point value (bits[127:64])\r\n from xmm2 is copied to xmm1[127:64].\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (w) ModRM:r/m (r) imm8 NA\r\n RVMI ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8\r\n\r\n\r\nDescription\r\nRound the DP FP value in the lower qword of the source operand (second operand) using the rounding mode spec-\r\nified in the immediate operand (third operand) and place the result in the destination operand (first operand). The\r\nrounding process rounds a double-precision floating-point input to an integer value and returns the integer result\r\nas a double precision floating-point value in the lowest position. The upper double precision floating-point value in\r\nthe destination is retained.\r\nThe immediate operand specifies control fields for the rounding operation, three bit fields are defined and shown in\r\nFigure 4-24. Bit 3 of the immediate byte controls processor behavior for a precision exception, bit 2 selects the\r\nsource of rounding mode control. Bits 1:0 specify a non-sticky rounding-mode value (Table 4-18 lists the encoded\r\nvalues for rounding-mode field).\r\nThe Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an\r\nSNaN then it will be converted to a QNaN. If DAZ is set to '1 then denormals will be converted to zero before\r\nrounding.\r\n128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (VLMAX-\r\n1:64) of the corresponding YMM destination register remain unchanged.\r\nVEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.\r\n\r\nOperation\r\nIF (imm[2] = '1)\r\n THEN // rounding mode is determined by MXCSR.RC\r\n DEST[63:0] <- ConvertDPFPToInteger_M(SRC[63:0]);\r\n ELSE // rounding mode is determined by IMM8.RC\r\n DEST[63:0] <- ConvertDPFPToInteger_Imm(SRC[63:0]);\r\nFI;\r\nDEST[127:63] remains unchanged ;\r\n\r\nROUNDSD (128-bit Legacy SSE version)\r\nDEST[63:0] <- RoundToInteger(SRC[63:0], ROUND_CONTROL)\r\nDEST[VLMAX-1:64] (Unmodified)\r\n\r\n\r\n\r\n\r\n\r\nVROUNDSD (VEX.128 encoded version)\r\nDEST[63:0] <- RoundToInteger(SRC2[63:0], ROUND_CONTROL)\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nROUNDSD: __m128d mm_round_sd(__m128d dst, __m128d s1, int iRoundMode);\r\n __m128d mm_floor_sd(__m128d dst, __m128d s1);\r\n __m128d mm_ceil_sd(__m128d dst, __m128d s1);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid (signaled only if SRC = SNaN)\r\nPrecision (signaled only if imm[3] = '0; if imm[3] = '1, then the Precision Mask in the MXSCSR is ignored and preci-\r\nsion exception is not signaled.)\r\nNote that Denormal is not signaled by ROUNDSD.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "ROUNDSD"
},
{
"description": "ROUNDSS - Round Scalar Single Precision Floating-Point Values\r\n Opcode*/ Op/ 64/32 bit CPUID Description\r\n Instruction En Mode Feature\r\n Support Flag\r\n 66 0F 3A 0A /r ib RMI V/V SSE4_1 Round the low packed single precision\r\n ROUNDSS xmm1, xmm2/m32, imm8 floating-point value in xmm2/m32 and place\r\n the result in xmm1. The rounding mode is\r\n determined by imm8.\r\n VEX.NDS.LIG.66.0F3A.WIG 0A /r ib RVMI V/V AVX Round the low packed single precision\r\n VROUNDSS xmm1, xmm2, xmm3/m32, imm8 floating-point value in xmm3/m32 and place\r\n the result in xmm1. The rounding mode is\r\n determined by imm8. Also, upper packed\r\n single precision floating-point values\r\n (bits[127:32]) from xmm2 are copied to\r\n xmm1[127:32].\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (w) ModRM:r/m (r) imm8 NA\r\n RVMI ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8\r\n\r\n\r\nDescription\r\nRound the single-precision floating-point value in the lowest dword of the source operand (second operand) using\r\nthe rounding mode specified in the immediate operand (third operand) and place the result in the destination\r\noperand (first operand). The rounding process rounds a single-precision floating-point input to an integer value and\r\nreturns the result as a single-precision floating-point value in the lowest position. The upper three single-precision\r\nfloating-point values in the destination are retained.\r\nThe immediate operand specifies control fields for the rounding operation, three bit fields are defined and shown in\r\nFigure 4-24. Bit 3 of the immediate byte controls processor behavior for a precision exception, bit 2 selects the\r\nsource of rounding mode control. Bits 1:0 specify a non-sticky rounding-mode value (Table 4-18 lists the encoded\r\nvalues for rounding-mode field).\r\nThe Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an\r\nSNaN then it will be converted to a QNaN. If DAZ is set to '1 then denormals will be converted to zero before\r\nrounding.\r\n128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (VLMAX-\r\n1:32) of the corresponding YMM destination register remain unchanged.\r\nVEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.\r\n\r\nOperation\r\nIF (imm[2] = '1)\r\n THEN // rounding mode is determined by MXCSR.RC\r\n DEST[31:0] <- ConvertSPFPToInteger_M(SRC[31:0]);\r\n ELSE // rounding mode is determined by IMM8.RC\r\n DEST[31:0] <- ConvertSPFPToInteger_Imm(SRC[31:0]);\r\nFI;\r\nDEST[127:32] remains unchanged ;\r\n\r\nROUNDSS (128-bit Legacy SSE version)\r\nDEST[31:0] <- RoundToInteger(SRC[31:0], ROUND_CONTROL)\r\nDEST[VLMAX-1:32] (Unmodified)\r\n\r\n\r\n\r\n\r\nVROUNDSS (VEX.128 encoded version)\r\nDEST[31:0] <- RoundToInteger(SRC2[31:0], ROUND_CONTROL)\r\nDEST[127:32] <- SRC1[127:32]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nROUNDSS: __m128 mm_round_ss(__m128 dst, __m128 s1, int iRoundMode);\r\n __m128 mm_floor_ss(__m128 dst, __m128 s1);\r\n __m128 mm_ceil_ss(__m128 dst, __m128 s1);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid (signaled only if SRC = SNaN)\r\nPrecision (signaled only if imm[3] = '0; if imm[3] = '1, then the Precision Mask in the MXSCSR is ignored and preci-\r\nsion exception is not signaled.)\r\nNote that Denormal is not signaled by ROUNDSS.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "ROUNDSS"
},
{
"description": "RSM-Resume from System Management Mode\r\n Opcode* Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F AA RSM NP Valid Valid Resume operation of interrupted program.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nReturns program control from system management mode (SMM) to the application program or operating-system\r\nprocedure that was interrupted when the processor received an SMM interrupt. The processor's state is restored\r\nfrom the dump created upon entering SMM. If the processor detects invalid state information during state restora-\r\ntion, it enters the shutdown state. The following invalid information can cause a shutdown:\r\n. Any reserved bit of CR4 is set to 1.\r\n. Any illegal combination of bits in CR0, such as (PG=1 and PE=0) or (NW=1 and CD=0).\r\n. (Intel Pentium and Intel486 processors only.) The value stored in the state dump base field is not a 32-KByte\r\n aligned address.\r\nThe contents of the model-specific registers are not affected by a return from SMM.\r\nThe SMM state map used by RSM supports resuming processor context for non-64-bit modes and 64-bit mode.\r\nSee Chapter 34, \"System Management Mode,\" in the Intel 64 and IA-32 Architectures Software Developer's\r\nManual, Volume 3C, for more information about SMM and the behavior of the RSM instruction.\r\n\r\nOperation\r\nReturnFromSMM;\r\nIF (IA-32e mode supported) or (CPUID DisplayFamily_DisplayModel = 06H_0CH )\r\n THEN\r\n ProcessorState <- Restore(SMMDump(IA-32e SMM STATE MAP));\r\n Else\r\n ProcessorState <- Restore(SMMDump(Non-32-Bit-Mode SMM STATE MAP));\r\nFI\r\n\r\nFlags Affected\r\nAll.\r\n\r\nProtected Mode Exceptions\r\n#UD If an attempt is made to execute this instruction when the processor is not in SMM.\r\n If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "RSM"
},
{
"description": "RSQRTPS-Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point\r\nValues\r\nOpcode*/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F 52 /r RM V/V SSE Computes the approximate reciprocals of the\r\nRSQRTPS xmm1, xmm2/m128 square roots of the packed single-precision\r\n floating-point values in xmm2/m128 and\r\n stores the results in xmm1.\r\nVEX.128.0F.WIG 52 /r RM V/V AVX Computes the approximate reciprocals of the\r\nVRSQRTPS xmm1, xmm2/m128 square roots of packed single-precision values\r\n in xmm2/mem and stores the results in xmm1.\r\nVEX.256.0F.WIG 52 /r RM V/V AVX Computes the approximate reciprocals of the\r\nVRSQRTPS ymm1, ymm2/m256 square roots of packed single-precision values\r\n in ymm2/mem and stores the results in ymm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\n\r\nDescription\r\nPerforms a SIMD computation of the approximate reciprocals of the square roots of the four packed single-preci-\r\nsion floating-point values in the source operand (second operand) and stores the packed single-precision floating-\r\npoint results in the destination operand. The source operand can be an XMM register or a 128-bit memory location.\r\nThe destination operand is an XMM register. See Figure 10-5 in the Intel 64 and IA-32 Architectures Software\r\nDeveloper's Manual, Volume 1, for an illustration of a SIMD single-precision floating-point operation.\r\nThe relative error for this approximation is:\r\n\r\n |Relative Error| <= 1.5 * 2-12\r\nThe RSQRTPS instruction is not affected by the rounding control bits in the MXCSR register. When a source value is\r\na 0.0, an inf of the sign of the source value is returned. A denormal source value is treated as a 0.0 (of the same\r\nsign). When a source value is a negative value (other than -0.0), a floating-point indefinite is returned. When a\r\nsource value is an SNaN or QNaN, the SNaN is converted to a QNaN or the source QNaN is returned.\r\nIn 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers\r\n(XMM8-XMM15).\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding\r\nYMM register destination are unmodified.\r\nVEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination\r\noperand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are\r\nzeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register.\r\nNote: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nRSQRTPS (128-bit Legacy SSE version)\r\nDEST[31:0] <- APPROXIMATE(1/SQRT(SRC[31:0]))\r\nDEST[63:32] <- APPROXIMATE(1/SQRT(SRC1[63:32]))\r\nDEST[95:64] <- APPROXIMATE(1/SQRT(SRC1[95:64]))\r\nDEST[127:96] <- APPROXIMATE(1/SQRT(SRC2[127:96]))\r\nDEST[VLMAX-1:128] (Unmodified)\r\n\r\nVRSQRTPS (VEX.128 encoded version)\r\nDEST[31:0] <- APPROXIMATE(1/SQRT(SRC[31:0]))\r\nDEST[63:32] <- APPROXIMATE(1/SQRT(SRC1[63:32]))\r\nDEST[95:64] <- APPROXIMATE(1/SQRT(SRC1[95:64]))\r\nDEST[127:96] <- APPROXIMATE(1/SQRT(SRC2[127:96]))\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVRSQRTPS (VEX.256 encoded version)\r\nDEST[31:0] <- APPROXIMATE(1/SQRT(SRC[31:0]))\r\nDEST[63:32] <- APPROXIMATE(1/SQRT(SRC1[63:32]))\r\nDEST[95:64] <- APPROXIMATE(1/SQRT(SRC1[95:64]))\r\nDEST[127:96] <- APPROXIMATE(1/SQRT(SRC2[127:96]))\r\nDEST[159:128] <- APPROXIMATE(1/SQRT(SRC2[159:128]))\r\nDEST[191:160] <- APPROXIMATE(1/SQRT(SRC2[191:160]))\r\nDEST[223:192] <- APPROXIMATE(1/SQRT(SRC2[223:192]))\r\nDEST[255:224] <- APPROXIMATE(1/SQRT(SRC2[255:224]))\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nRSQRTPS: __m128 _mm_rsqrt_ps(__m128 a)\r\nRSQRTPS: __m256 _mm256_rsqrt_ps (__m256 a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4; additionally\r\n#UD If VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "RSQRTPS"
},
{
"description": "RSQRTSS-Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value\r\n Opcode*/ Op/ 64/32 bit CPUID Description\r\n Instruction En Mode Feature\r\n Support Flag\r\n F3 0F 52 /r RM V/V SSE Computes the approximate reciprocal of the\r\n RSQRTSS xmm1, xmm2/m32 square root of the low single-precision\r\n floating-point value in xmm2/m32 and stores\r\n the results in xmm1.\r\n VEX.NDS.LIG.F3.0F.WIG 52 /r RVM V/V AVX Computes the approximate reciprocal of the\r\n VRSQRTSS xmm1, xmm2, xmm3/m32 square root of the low single precision\r\n floating-point value in xmm3/m32 and stores\r\n the results in xmm1. Also, upper single\r\n precision floating-point values (bits[127:32])\r\n from xmm2 are copied to xmm1[127:32].\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\nDescription\r\nComputes an approximate reciprocal of the square root of the low single-precision floating-point value in the\r\nsource operand (second operand) stores the single-precision floating-point result in the destination operand. The\r\nsource operand can be an XMM register or a 32-bit memory location. The destination operand is an XMM register.\r\nThe three high-order doublewords of the destination operand remain unchanged. See Figure 10-6 in the Intel 64\r\nand IA-32 Architectures Software Developer's Manual, Volume 1, for an illustration of a scalar single-precision\r\nfloating-point operation.\r\nThe relative error for this approximation is:\r\n\r\n |Relative Error| <= 1.5 * 2-12\r\nThe RSQRTSS instruction is not affected by the rounding control bits in the MXCSR register. When a source value is\r\na 0.0, an inf of the sign of the source value is returned. A denormal source value is treated as a 0.0 (of the same\r\nsign). When a source value is a negative value (other than -0.0), a floating-point indefinite is returned. When a\r\nsource value is an SNaN or QNaN, the SNaN is converted to a QNaN or the source QNaN is returned.\r\nIn 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers\r\n(XMM8-XMM15).\r\n128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (VLMAX-\r\n1:32) of the corresponding YMM destination register remain unchanged.\r\nVEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.\r\n\r\nOperation\r\nRSQRTSS (128-bit Legacy SSE version)\r\nDEST[31:0] <- APPROXIMATE(1/SQRT(SRC2[31:0]))\r\nDEST[VLMAX-1:32] (Unmodified)\r\n\r\nVRSQRTSS (VEX.128 encoded version)\r\nDEST[31:0] <- APPROXIMATE(1/SQRT(SRC2[31:0]))\r\nDEST[127:32] <- SRC1[127:32]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nRSQRTSS: __m128 _mm_rsqrt_ss(__m128 a)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 5.\r\n\r\n\r\n\r\n\r\n",
"mnem": "RSQRTSS"
},
{
"description": "SAHF-Store AH into Flags\r\n Opcode* Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 9E SAHF NP Invalid* Valid Loads SF, ZF, AF, PF, and CF from AH into\r\n EFLAGS register.\r\n NOTES:\r\n * Valid in specific steppings. See Description section.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nLoads the SF, ZF, AF, PF, and CF flags of the EFLAGS register with values from the corresponding bits in the AH\r\nregister (bits 7, 6, 4, 2, and 0, respectively). Bits 1, 3, and 5 of register AH are ignored; the corresponding reserved\r\nbits (1, 3, and 5) in the EFLAGS register remain as shown in the \"Operation\" section below.\r\nThis instruction executes as described above in compatibility mode and legacy mode. It is valid in 64-bit mode only\r\nif CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1.\r\n\r\nOperation\r\nIF IA-64 Mode\r\n THEN\r\n IF CPUID.80000001H.ECX[0] = 1;\r\n THEN\r\n RFLAGS(SF:ZF:0:AF:0:PF:1:CF) <- AH;\r\n ELSE\r\n #UD;\r\n FI\r\n ELSE\r\n EFLAGS(SF:ZF:0:AF:0:PF:1:CF) <- AH;\r\nFI;\r\n\r\nFlags Affected\r\nThe SF, ZF, AF, PF, and CF flags are loaded with values from the AH register. Bits 1, 3, and 5 of the EFLAGS register\r\nare unaffected, with the values remaining 1, 0, and 0, respectively.\r\n\r\nProtected Mode Exceptions\r\nNone.\r\n\r\nReal-Address Mode Exceptions\r\nNone.\r\n\r\nVirtual-8086 Mode Exceptions\r\nNone.\r\n\r\nCompatibility Mode Exceptions\r\nNone.\r\n\r\n\r\n\r\n\r\n\r\n64-Bit Mode Exceptions\r\n#UD If CPUID.80000001H.ECX[0] = 0.\r\n If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SAHF"
},
{
"description": "SAL/SAR/SHL/SHR-Shift\r\n Opcode*** Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n D0 /4 SAL r/m8, 1 M1 Valid Valid Multiply r/m8 by 2, once.\r\n REX + D0 /4 SAL r/m8**, 1 M1 Valid N.E. Multiply r/m8 by 2, once.\r\n D2 /4 SAL r/m8, CL MC Valid Valid Multiply r/m8 by 2, CL times.\r\n REX + D2 /4 SAL r/m8**, CL MC Valid N.E. Multiply r/m8 by 2, CL times.\r\n C0 /4 ib SAL r/m8, imm8 MI Valid Valid Multiply r/m8 by 2, imm8 times.\r\n REX + C0 /4 ib SAL r/m8**, imm8 MI Valid N.E. Multiply r/m8 by 2, imm8 times.\r\n D1 /4 SAL r/m16, 1 M1 Valid Valid Multiply r/m16 by 2, once.\r\n D3 /4 SAL r/m16, CL MC Valid Valid Multiply r/m16 by 2, CL times.\r\n C1 /4 ib SAL r/m16, imm8 MI Valid Valid Multiply r/m16 by 2, imm8 times.\r\n D1 /4 SAL r/m32, 1 M1 Valid Valid Multiply r/m32 by 2, once.\r\n REX.W + D1 /4 SAL r/m64, 1 M1 Valid N.E. Multiply r/m64 by 2, once.\r\n D3 /4 SAL r/m32, CL MC Valid Valid Multiply r/m32 by 2, CL times.\r\n REX.W + D3 /4 SAL r/m64, CL MC Valid N.E. Multiply r/m64 by 2, CL times.\r\n C1 /4 ib SAL r/m32, imm8 MI Valid Valid Multiply r/m32 by 2, imm8 times.\r\n REX.W + C1 /4 ib SAL r/m64, imm8 MI Valid N.E. Multiply r/m64 by 2, imm8 times.\r\n D0 /7 SAR r/m8, 1 M1 Valid Valid Signed divide* r/m8 by 2, once.\r\n REX + D0 /7 SAR r/m8**, 1 M1 Valid N.E. Signed divide* r/m8 by 2, once.\r\n D2 /7 SAR r/m8, CL MC Valid Valid Signed divide* r/m8 by 2, CL times.\r\n REX + D2 /7 SAR r/m8**, CL MC Valid N.E. Signed divide* r/m8 by 2, CL times.\r\n C0 /7 ib SAR r/m8, imm8 MI Valid Valid Signed divide* r/m8 by 2, imm8 time.\r\n REX + C0 /7 ib SAR r/m8**, imm8 MI Valid N.E. Signed divide* r/m8 by 2, imm8 times.\r\n D1 /7 SAR r/m16,1 M1 Valid Valid Signed divide* r/m16 by 2, once.\r\n D3 /7 SAR r/m16, CL MC Valid Valid Signed divide* r/m16 by 2, CL times.\r\n C1 /7 ib SAR r/m16, imm8 MI Valid Valid Signed divide* r/m16 by 2, imm8 times.\r\n D1 /7 SAR r/m32, 1 M1 Valid Valid Signed divide* r/m32 by 2, once.\r\n REX.W + D1 /7 SAR r/m64, 1 M1 Valid N.E. Signed divide* r/m64 by 2, once.\r\n D3 /7 SAR r/m32, CL MC Valid Valid Signed divide* r/m32 by 2, CL times.\r\n REX.W + D3 /7 SAR r/m64, CL MC Valid N.E. Signed divide* r/m64 by 2, CL times.\r\n C1 /7 ib SAR r/m32, imm8 MI Valid Valid Signed divide* r/m32 by 2, imm8 times.\r\n REX.W + C1 /7 ib SAR r/m64, imm8 MI Valid N.E. Signed divide* r/m64 by 2, imm8 times\r\n D0 /4 SHL r/m8, 1 M1 Valid Valid Multiply r/m8 by 2, once.\r\n REX + D0 /4 SHL r/m8**, 1 M1 Valid N.E. Multiply r/m8 by 2, once.\r\n D2 /4 SHL r/m8, CL MC Valid Valid Multiply r/m8 by 2, CL times.\r\n REX + D2 /4 SHL r/m8**, CL MC Valid N.E. Multiply r/m8 by 2, CL times.\r\n C0 /4 ib SHL r/m8, imm8 MI Valid Valid Multiply r/m8 by 2, imm8 times.\r\n REX + C0 /4 ib SHL r/m8**, imm8 MI Valid N.E. Multiply r/m8 by 2, imm8 times.\r\n D1 /4 SHL r/m16,1 M1 Valid Valid Multiply r/m16 by 2, once.\r\n D3 /4 SHL r/m16, CL MC Valid Valid Multiply r/m16 by 2, CL times.\r\n C1 /4 ib SHL r/m16, imm8 MI Valid Valid Multiply r/m16 by 2, imm8 times.\r\n D1 /4 SHL r/m32,1 M1 Valid Valid Multiply r/m32 by 2, once.\r\n\r\n\r\n\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n REX.W + D1 /4 SHL r/m64,1 M1 Valid N.E. Multiply r/m64 by 2, once.\r\n D3 /4 SHL r/m32, CL MC Valid Valid Multiply r/m32 by 2, CL times.\r\n REX.W + D3 /4 SHL r/m64, CL MC Valid N.E. Multiply r/m64 by 2, CL times.\r\n C1 /4 ib SHL r/m32, imm8 MI Valid Valid Multiply r/m32 by 2, imm8 times.\r\n REX.W + C1 /4 ib SHL r/m64, imm8 MI Valid N.E. Multiply r/m64 by 2, imm8 times.\r\n D0 /5 SHR r/m8,1 M1 Valid Valid Unsigned divide r/m8 by 2, once.\r\n REX + D0 /5 SHR r/m8**, 1 M1 Valid N.E. Unsigned divide r/m8 by 2, once.\r\n D2 /5 SHR r/m8, CL MC Valid Valid Unsigned divide r/m8 by 2, CL times.\r\n REX + D2 /5 SHR r/m8**, CL MC Valid N.E. Unsigned divide r/m8 by 2, CL times.\r\n C0 /5 ib SHR r/m8, imm8 MI Valid Valid Unsigned divide r/m8 by 2, imm8 times.\r\n REX + C0 /5 ib SHR r/m8**, imm8 MI Valid N.E. Unsigned divide r/m8 by 2, imm8 times.\r\n D1 /5 SHR r/m16, 1 M1 Valid Valid Unsigned divide r/m16 by 2, once.\r\n D3 /5 SHR r/m16, CL MC Valid Valid Unsigned divide r/m16 by 2, CL times\r\n C1 /5 ib SHR r/m16, imm8 MI Valid Valid Unsigned divide r/m16 by 2, imm8 times.\r\n D1 /5 SHR r/m32, 1 M1 Valid Valid Unsigned divide r/m32 by 2, once.\r\n REX.W + D1 /5 SHR r/m64, 1 M1 Valid N.E. Unsigned divide r/m64 by 2, once.\r\n D3 /5 SHR r/m32, CL MC Valid Valid Unsigned divide r/m32 by 2, CL times.\r\n REX.W + D3 /5 SHR r/m64, CL MC Valid N.E. Unsigned divide r/m64 by 2, CL times.\r\n C1 /5 ib SHR r/m32, imm8 MI Valid Valid Unsigned divide r/m32 by 2, imm8 times.\r\n REX.W + C1 /5 ib SHR r/m64, imm8 MI Valid N.E. Unsigned divide r/m64 by 2, imm8 times.\r\n NOTES:\r\n * Not the same form of division as IDIV; rounding is toward negative infinity.\r\n ** In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n ***See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M1 ModRM:r/m (r, w) 1 NA NA\r\n MC ModRM:r/m (r, w) CL NA NA\r\n MI ModRM:r/m (r, w) imm8 NA NA\r\n\r\n\r\nDescription\r\nShifts the bits in the first operand (destination operand) to the left or right by the number of bits specified in the\r\nsecond operand (count operand). Bits shifted beyond the destination operand boundary are first shifted into the CF\r\nflag, then discarded. At the end of the shift operation, the CF flag contains the last bit shifted out of the destination\r\noperand.\r\nThe destination operand can be a register or a memory location. The count operand can be an immediate value or\r\nthe CL register. The count is masked to 5 bits (or 6 bits if in 64-bit mode and REX.W is used). The count range is\r\nlimited to 0 to 31 (or 63 if 64-bit mode and REX.W is used). A special opcode encoding is provided for a count of 1.\r\nThe shift arithmetic left (SAL) and shift logical left (SHL) instructions perform the same operation; they shift the\r\nbits in the destination operand to the left (toward more significant bit locations). For each shift count, the most\r\nsignificant bit of the destination operand is shifted into the CF flag, and the least significant bit is cleared (see\r\nFigure 7-7 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1).\r\n\r\n\r\n\r\n\r\nThe shift arithmetic right (SAR) and shift logical right (SHR) instructions shift the bits of the destination operand to\r\nthe right (toward less significant bit locations). For each shift count, the least significant bit of the destination\r\noperand is shifted into the CF flag, and the most significant bit is either set or cleared depending on the instruction\r\ntype. The SHR instruction clears the most significant bit (see Figure 7-8 in the Intel 64 and IA-32 Architectures\r\nSoftware Developer's Manual, Volume 1); the SAR instruction sets or clears the most significant bit to correspond\r\nto the sign (most significant bit) of the original value in the destination operand. In effect, the SAR instruction fills\r\nthe empty bit position's shifted value with the sign of the unshifted value (see Figure 7-9 in the Intel 64 and IA-32\r\nArchitectures Software Developer's Manual, Volume 1).\r\nThe SAR and SHR instructions can be used to perform signed or unsigned division, respectively, of the destination\r\noperand by powers of 2. For example, using the SAR instruction to shift a signed integer 1 bit to the right divides\r\nthe value by 2.\r\nUsing the SAR instruction to perform a division operation does not produce the same result as the IDIV instruction.\r\nThe quotient from the IDIV instruction is rounded toward zero, whereas the \"quotient\" of the SAR instruction is\r\nrounded toward negative infinity. This difference is apparent only for negative numbers. For example, when the\r\nIDIV instruction is used to divide -9 by 4, the result is -2 with a remainder of -1. If the SAR instruction is used to\r\nshift -9 right by two bits, the result is -3 and the \"remainder\" is +3; however, the SAR instruction stores only the\r\nmost significant bit of the remainder (in the CF flag).\r\nThe OF flag is affected only on 1-bit shifts. For left shifts, the OF flag is set to 0 if the most-significant bit of the\r\nresult is the same as the CF flag (that is, the top two bits of the original operand were the same); otherwise, it is\r\nset to 1. For the SAR instruction, the OF flag is cleared for all 1-bit shifts. For the SHR instruction, the OF flag is set\r\nto the most-significant bit of the original operand.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits and the mask width for CL is 5 bits. Using a REX\r\nprefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W\r\npromotes operation to 64-bits and sets the mask width for CL to 6 bits. See the summary chart at the beginning of\r\nthis section for encoding data and limits.\r\n\r\nIA-32 Architecture Compatibility\r\nThe 8086 does not mask the shift count. However, all other IA-32 processors (starting with the Intel 286 processor)\r\ndo mask the shift count to 5 bits, resulting in a maximum count of 31. This masking is done in all operating modes\r\n(including the virtual-8086 mode) to reduce the maximum execution time of the instructions.\r\n\r\nOperation\r\nIF 64-Bit Mode and using REX.W\r\n THEN\r\n countMASK <- 3FH;\r\n ELSE\r\n countMASK <- 1FH;\r\nFI\r\n\r\ntempCOUNT <- (COUNT AND countMASK);\r\ntempDEST <- DEST;\r\nWHILE (tempCOUNT != 0)\r\nDO\r\n IF instruction is SAL or SHL\r\n THEN\r\n CF <- MSB(DEST);\r\n ELSE (* Instruction is SAR or SHR *)\r\n CF <- LSB(DEST);\r\n FI;\r\n IF instruction is SAL or SHL\r\n THEN\r\n DEST <- DEST * 2;\r\n ELSE\r\n IF instruction is SAR\r\n\r\n\r\n\r\n THEN\r\n DEST <- DEST / 2; (* Signed divide, rounding toward negative infinity *)\r\n ELSE (* Instruction is SHR *)\r\n DEST <- DEST / 2 ; (* Unsigned divide *)\r\n FI;\r\n FI;\r\n tempCOUNT <- tempCOUNT - 1;\r\nOD;\r\n\r\n(* Determine overflow for the various instructions *)\r\nIF (COUNT and countMASK) = 1\r\n THEN\r\n IF instruction is SAL or SHL\r\n THEN\r\n OF <- MSB(DEST) XOR CF;\r\n ELSE\r\n IF instruction is SAR\r\n THEN\r\n OF <- 0;\r\n ELSE (* Instruction is SHR *)\r\n OF <- MSB(tempDEST);\r\n FI;\r\n FI;\r\n ELSE IF (COUNT AND countMASK) = 0\r\n THEN\r\n All flags unchanged;\r\n ELSE (* COUNT not 1 or 0 *)\r\n OF <- undefined;\r\n FI;\r\nFI;\r\n\r\nFlags Affected\r\nThe CF flag contains the value of the last bit shifted out of the destination operand; it is undefined for SHL and SHR\r\ninstructions where the count is greater than or equal to the size (in bits) of the destination operand. The OF flag is\r\naffected only for 1-bit shifts (see \"Description\" above); otherwise, it is undefined. The SF, ZF, and PF flags are set\r\naccording to the result. If the count is 0, the flags are not affected. For a non-zero count, the AF flag is undefined.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination is located in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SAL"
},
{
"description": "-R:SAL",
"mnem": "SAR"
},
{
"description": "SARX/SHLX/SHRX - Shift Without Affecting Flags\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En -bit Feature\r\n Mode Flag\r\n VEX.NDS.LZ.F3.0F38.W0 F7 /r RMV V/V BMI2 Shift r/m32 arithmetically right with count specified in r32b.\r\n SARX r32a, r/m32, r32b\r\n VEX.NDS.LZ.66.0F38.W0 F7 /r RMV V/V BMI2 Shift r/m32 logically left with count specified in r32b.\r\n SHLX r32a, r/m32, r32b\r\n VEX.NDS.LZ.F2.0F38.W0 F7 /r RMV V/V BMI2 Shift r/m32 logically right with count specified in r32b.\r\n SHRX r32a, r/m32, r32b\r\n VEX.NDS.LZ.F3.0F38.W1 F7 /r RMV V/N.E. BMI2 Shift r/m64 arithmetically right with count specified in r64b.\r\n SARX r64a, r/m64, r64b\r\n VEX.NDS.LZ.66.0F38.W1 F7 /r RMV V/N.E. BMI2 Shift r/m64 logically left with count specified in r64b.\r\n SHLX r64a, r/m64, r64b\r\n VEX.NDS.LZ.F2.0F38.W1 F7 /r RMV V/N.E. BMI2 Shift r/m64 logically right with count specified in r64b.\r\n SHRX r64a, r/m64, r64b\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMV ModRM:reg (w) ModRM:r/m (r) VEX.vvvv (r) NA\r\n\r\n\r\nDescription\r\nShifts the bits of the first source operand (the second operand) to the left or right by a COUNT value specified in\r\nthe second source operand (the third operand). The result is written to the destination operand (the first operand).\r\nThe shift arithmetic right (SARX) and shift logical right (SHRX) instructions shift the bits of the destination operand\r\nto the right (toward less significant bit locations), SARX keeps and propagates the most significant bit (sign bit)\r\nwhile shifting.\r\nThe logical shift left (SHLX) shifts the bits of the destination operand to the left (toward more significant bit loca-\r\ntions).\r\nThis instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in\r\n64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An\r\nattempt to execute this instruction with VEX.L not equal to 0 will cause #UD.\r\nIf the value specified in the first source operand exceeds OperandSize -1, the COUNT value is masked.\r\nSARX,SHRX, and SHLX instructions do not update flags.\r\n\r\nOperation\r\nTEMP <- SRC1;\r\nIF VEX.W1 and CS.L = 1\r\nTHEN\r\n countMASK <-3FH;\r\nELSE\r\n countMASK <-1FH;\r\nFI\r\nCOUNT <- (SRC2 AND countMASK)\r\n\r\nDEST[OperandSize -1] = TEMP[OperandSize -1];\r\nDO WHILE (COUNT != 0)\r\n IF instruction is SHLX\r\n THEN\r\n DEST[] <- DEST *2;\r\n\r\n\r\n\r\n\r\n ELSE IF instruction is SHRX\r\n THEN\r\n DEST[] <- DEST /2; //unsigned divide\r\n ELSE // SARX\r\n DEST[] <- DEST /2; // signed divide, round toward negative infinity\r\n FI;\r\n COUNT <- COUNT - 1;\r\nOD\r\n\r\nFlags Affected\r\nNone.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nAuto-generated from high-level language.\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Section 2.5.1, \"Exception Conditions for VEX-Encoded GPR Instructions\", Table 2-29; additionally\r\n#UD If VEX.W = 1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SARX"
},
{
"description": "SBB-Integer Subtraction with Borrow\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 1C ib SBB AL, imm8 I Valid Valid Subtract with borrow imm8 from AL.\r\n 1D iw SBB AX, imm16 I Valid Valid Subtract with borrow imm16 from AX.\r\n 1D id SBB EAX, imm32 I Valid Valid Subtract with borrow imm32 from EAX.\r\n REX.W + 1D id SBB RAX, imm32 I Valid N.E. Subtract with borrow sign-extended imm.32\r\n to 64-bits from RAX.\r\n 80 /3 ib SBB r/m8, imm8 MI Valid Valid Subtract with borrow imm8 from r/m8.\r\n REX + 80 /3 ib SBB r/m8*, imm8 MI Valid N.E. Subtract with borrow imm8 from r/m8.\r\n 81 /3 iw SBB r/m16, imm16 MI Valid Valid Subtract with borrow imm16 from r/m16.\r\n 81 /3 id SBB r/m32, imm32 MI Valid Valid Subtract with borrow imm32 from r/m32.\r\n REX.W + 81 /3 id SBB r/m64, imm32 MI Valid N.E. Subtract with borrow sign-extended imm32 to\r\n 64-bits from r/m64.\r\n 83 /3 ib SBB r/m16, imm8 MI Valid Valid Subtract with borrow sign-extended imm8\r\n from r/m16.\r\n 83 /3 ib SBB r/m32, imm8 MI Valid Valid Subtract with borrow sign-extended imm8\r\n from r/m32.\r\n REX.W + 83 /3 ib SBB r/m64, imm8 MI Valid N.E. Subtract with borrow sign-extended imm8\r\n from r/m64.\r\n 18 /r SBB r/m8, r8 MR Valid Valid Subtract with borrow r8 from r/m8.\r\n REX + 18 /r SBB r/m8*, r8 MR Valid N.E. Subtract with borrow r8 from r/m8.\r\n 19 /r SBB r/m16, r16 MR Valid Valid Subtract with borrow r16 from r/m16.\r\n 19 /r SBB r/m32, r32 MR Valid Valid Subtract with borrow r32 from r/m32.\r\n REX.W + 19 /r SBB r/m64, r64 MR Valid N.E. Subtract with borrow r64 from r/m64.\r\n 1A /r SBB r8, r/m8 RM Valid Valid Subtract with borrow r/m8 from r8.\r\n REX + 1A /r SBB r8*, r/m8* RM Valid N.E. Subtract with borrow r/m8 from r8.\r\n 1B /r SBB r16, r/m16 RM Valid Valid Subtract with borrow r/m16 from r16.\r\n\r\n\r\n 1B /r SBB r32, r/m32 RM Valid Valid Subtract with borrow r/m32 from r32.\r\n REX.W + 1B /r SBB r64, r/m64 RM Valid N.E. Subtract with borrow r/m64 from r64.\r\n NOTES:\r\n * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n I AL/AX/EAX/RAX imm8/16/32 NA NA\r\n MI ModRM:r/m (w) imm8/16/32 NA NA\r\n MR ModRM:r/m (w) ModRM:reg (r) NA NA\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\n\r\n\r\n\r\n\r\nDescription\r\nAdds the source operand (second operand) and the carry (CF) flag, and subtracts the result from the destination\r\noperand (first operand). The result of the subtraction is stored in the destination operand. The destination operand\r\ncan be a register or a memory location; the source operand can be an immediate, a register, or a memory location.\r\n(However, two memory operands cannot be used in one instruction.) The state of the CF flag represents a borrow\r\nfrom a previous subtraction.\r\nWhen an immediate value is used as an operand, it is sign-extended to the length of the destination operand\r\nformat.\r\nThe SBB instruction does not distinguish between signed or unsigned operands. Instead, the processor evaluates\r\nthe result for both data types and sets the OF and CF flags to indicate a borrow in the signed or unsigned result,\r\nrespectively. The SF flag indicates the sign of the signed result.\r\nThe SBB instruction is usually executed as part of a multibyte or multiword subtraction in which a SUB instruction\r\nis followed by a SBB instruction.\r\nThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nDEST <- (DEST - (SRC + CF));\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nSBB: extern unsigned char _subborrow_u8(unsigned char c_in, unsigned char src1, unsigned char src2, unsigned char *diff_out);\r\nSBB: extern unsigned char _subborrow_u16(unsigned char c_in, unsigned short src1, unsigned short src2, unsigned short\r\n*diff_out);\r\nSBB: extern unsigned char _subborrow_u32(unsigned char c_in, unsigned int src1, unsigned char int, unsigned int *diff_out);\r\nSBB: extern unsigned char _subborrow_u64(unsigned char c_in, unsigned __int64 src1, unsigned __int64 src2, unsigned\r\n__int64 *diff_out);\r\n\r\nFlags Affected\r\nThe OF, SF, ZF, AF, PF, and CF flags are set according to the result.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination is located in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SBB"
},
{
"description": "SCAS/SCASB/SCASW/SCASD-Scan String\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n AE SCAS m8 NP Valid Valid Compare AL with byte at ES:(E)DI or RDI, then\r\n set status flags.*\r\n AF SCAS m16 NP Valid Valid Compare AX with word at ES:(E)DI or RDI, then\r\n set status flags.*\r\n AF SCAS m32 NP Valid Valid Compare EAX with doubleword at ES(E)DI or\r\n RDI then set status flags.*\r\n REX.W + AF SCAS m64 NP Valid N.E. Compare RAX with quadword at RDI or EDI\r\n then set status flags.\r\n AE SCASB NP Valid Valid Compare AL with byte at ES:(E)DI or RDI then\r\n set status flags.*\r\n AF SCASW NP Valid Valid Compare AX with word at ES:(E)DI or RDI then\r\n set status flags.*\r\n AF SCASD NP Valid Valid Compare EAX with doubleword at ES:(E)DI or\r\n RDI then set status flags.*\r\n REX.W + AF SCASQ NP Valid N.E. Compare RAX with quadword at RDI or EDI\r\n then set status flags.\r\n NOTES:\r\n * In 64-bit mode, only 64-bit (RDI) and 32-bit (EDI) address sizes are supported. In non-64-bit mode, only 32-bit (EDI) and 16-bit (DI)\r\n address sizes are supported.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nIn non-64-bit modes and in default 64-bit mode: this instruction compares a byte, word, doubleword or quadword\r\nspecified using a memory operand with the value in AL, AX, or EAX. It then sets status flags in EFLAGS recording\r\nthe results. The memory operand address is read from ES:(E)DI register (depending on the address-size attribute\r\nof the instruction and the current operational mode). Note that ES cannot be overridden with a segment override\r\nprefix.\r\nAt the assembly-code level, two forms of this instruction are allowed. The explicit-operand form and the no-oper-\r\nands form. The explicit-operand form (specified using the SCAS mnemonic) allows a memory operand to be speci-\r\nfied explicitly. The memory operand must be a symbol that indicates the size and location of the operand value. The\r\nregister operand is then automatically selected to match the size of the memory operand (AL register for byte\r\ncomparisons, AX for word comparisons, EAX for doubleword comparisons). The explicit-operand form is provided\r\nto allow documentation. Note that the documentation provided by this form can be misleading. That is, the\r\nmemory operand symbol must specify the correct type (size) of the operand (byte, word, or doubleword) but it\r\ndoes not have to specify the correct location. The location is always specified by ES:(E)DI.\r\nThe no-operands form of the instruction uses a short form of SCAS. Again, ES:(E)DI is assumed to be the memory\r\noperand and AL, AX, or EAX is assumed to be the register operand. The size of operands is selected by the\r\nmnemonic: SCASB (byte comparison), SCASW (word comparison), or SCASD (doubleword comparison).\r\nAfter the comparison, the (E)DI register is incremented or decremented automatically according to the setting of\r\nthe DF flag in the EFLAGS register. If the DF flag is 0, the (E)DI register is incremented; if the DF flag is 1, the (E)DI\r\nregister is decremented. The register is incremented or decremented by 1 for byte operations, by 2 for word oper-\r\nations, and by 4 for doubleword operations.\r\nSCAS, SCASB, SCASW, SCASD, and SCASQ can be preceded by the REP prefix for block comparisons of ECX bytes,\r\nwords, doublewords, or quadwords. Often, however, these instructions will be used in a LOOP construct that takes\r\n\r\n\r\n\r\nsome action based on the setting of status flags. See \"REP/REPE/REPZ /REPNE/REPNZ-Repeat String Operation\r\nPrefix\" in this chapter for a description of the REP prefix.\r\nIn 64-bit mode, the instruction's default address size is 64-bits, 32-bit address size is supported using the prefix\r\n67H. Using a REX prefix in the form of REX.W promotes operation on doubleword operand to 64 bits. The 64-bit no-\r\noperand mnemonic is SCASQ. Address of the memory operand is specified in either RDI or EDI, and\r\nAL/AX/EAX/RAX may be used as the register operand. After a comparison, the destination register is incremented\r\nor decremented by the current operand size (depending on the value of the DF flag). See the summary chart at the\r\nbeginning of this section for encoding data and limits.\r\n\r\nOperation\r\nNon-64-bit Mode:\r\n\r\nIF (Byte comparison)\r\n THEN\r\n temp <- AL - SRC;\r\n SetStatusFlags(temp);\r\n THEN IF DF = 0\r\n THEN (E)DI <- (E)DI + 1;\r\n ELSE (E)DI <- (E)DI - 1; FI;\r\n ELSE IF (Word comparison)\r\n THEN\r\n temp <- AX - SRC;\r\n SetStatusFlags(temp);\r\n IF DF = 0\r\n THEN (E)DI <- (E)DI + 2;\r\n ELSE (E)DI <- (E)DI - 2; FI;\r\n FI;\r\n ELSE IF (Doubleword comparison)\r\n THEN\r\n temp <- EAX - SRC;\r\n SetStatusFlags(temp);\r\n IF DF = 0\r\n THEN (E)DI <- (E)DI + 4;\r\n ELSE (E)DI <- (E)DI - 4; FI;\r\n FI;\r\nFI;\r\n\r\n64-bit Mode:\r\n\r\nIF (Byte cmparison)\r\n THEN\r\n temp <- AL - SRC;\r\n SetStatusFlags(temp);\r\n THEN IF DF = 0\r\n THEN (R|E)DI <- (R|E)DI + 1;\r\n ELSE (R|E)DI <- (R|E)DI - 1; FI;\r\n ELSE IF (Word comparison)\r\n THEN\r\n temp <- AX - SRC;\r\n SetStatusFlags(temp);\r\n IF DF = 0\r\n THEN (R|E)DI <- (R|E)DI + 2;\r\n ELSE (R|E)DI <- (R|E)DI - 2; FI;\r\n FI;\r\n\r\n\r\n\r\n ELSE IF (Doubleword comparison)\r\n THEN\r\n temp <- EAX - SRC;\r\n SetStatusFlags(temp);\r\n IF DF = 0\r\n THEN (R|E)DI <- (R|E)DI + 4;\r\n ELSE (R|E)DI <- (R|E)DI - 4; FI;\r\n FI;\r\n ELSE IF (Quadword comparison using REX.W )\r\n THEN\r\n temp <- RAX - SRC;\r\n SetStatusFlags(temp);\r\n IF DF = 0\r\n THEN (R|E)DI <- (R|E)DI + 8;\r\n ELSE (R|E)DI <- (R|E)DI - 8;\r\n FI;\r\n FI;\r\nF\r\n\r\nFlags Affected\r\nThe OF, SF, ZF, AF, PF, and CF flags are set according to the temporary result of the comparison.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the limit of the ES segment.\r\n If the ES register contains a NULL segment selector.\r\n If an illegal memory operand effective address in the ES segment is given.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SCAS"
},
{
"description": "-R:SCAS",
"mnem": "SCASB"
},
{
"description": "-R:SCAS",
"mnem": "SCASD"
},
{
"description": "-R:SCAS",
"mnem": "SCASW"
},
{
"description": "SETcc-Set Byte on Condition\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F 97 SETA r/m8 M Valid Valid Set byte if above (CF=0 and ZF=0).\r\n REX + 0F 97 SETA r/m8* M Valid N.E. Set byte if above (CF=0 and ZF=0).\r\n 0F 93 SETAE r/m8 M Valid Valid Set byte if above or equal (CF=0).\r\n REX + 0F 93 SETAE r/m8* M Valid N.E. Set byte if above or equal (CF=0).\r\n 0F 92 SETB r/m8 M Valid Valid Set byte if below (CF=1).\r\n REX + 0F 92 SETB r/m8* M Valid N.E. Set byte if below (CF=1).\r\n 0F 96 SETBE r/m8 M Valid Valid Set byte if below or equal (CF=1 or ZF=1).\r\n REX + 0F 96 SETBE r/m8* M Valid N.E. Set byte if below or equal (CF=1 or ZF=1).\r\n 0F 92 SETC r/m8 M Valid Valid Set byte if carry (CF=1).\r\n REX + 0F 92 SETC r/m8* M Valid N.E. Set byte if carry (CF=1).\r\n 0F 94 SETE r/m8 M Valid Valid Set byte if equal (ZF=1).\r\n REX + 0F 94 SETE r/m8* M Valid N.E. Set byte if equal (ZF=1).\r\n 0F 9F SETG r/m8 M Valid Valid Set byte if greater (ZF=0 and SF=OF).\r\n REX + 0F 9F SETG r/m8* M Valid N.E. Set byte if greater (ZF=0 and SF=OF).\r\n 0F 9D SETGE r/m8 M Valid Valid Set byte if greater or equal (SF=OF).\r\n REX + 0F 9D SETGE r/m8* M Valid N.E. Set byte if greater or equal (SF=OF).\r\n 0F 9C SETL r/m8 M Valid Valid Set byte if less (SF!= OF).\r\n REX + 0F 9C SETL r/m8* M Valid N.E. Set byte if less (SF!= OF).\r\n 0F 9E SETLE r/m8 M Valid Valid Set byte if less or equal (ZF=1 or SF!= OF).\r\n REX + 0F 9E SETLE r/m8* M Valid N.E. Set byte if less or equal (ZF=1 or SF!= OF).\r\n 0F 96 SETNA r/m8 M Valid Valid Set byte if not above (CF=1 or ZF=1).\r\n REX + 0F 96 SETNA r/m8* M Valid N.E. Set byte if not above (CF=1 or ZF=1).\r\n 0F 92 SETNAE r/m8 M Valid Valid Set byte if not above or equal (CF=1).\r\n REX + 0F 92 SETNAE r/m8* M Valid N.E. Set byte if not above or equal (CF=1).\r\n 0F 93 SETNB r/m8 M Valid Valid Set byte if not below (CF=0).\r\n REX + 0F 93 SETNB r/m8* M Valid N.E. Set byte if not below (CF=0).\r\n 0F 97 SETNBE r/m8 M Valid Valid Set byte if not below or equal (CF=0 and\r\n ZF=0).\r\n REX + 0F 97 SETNBE r/m8* M Valid N.E. Set byte if not below or equal (CF=0 and\r\n ZF=0).\r\n 0F 93 SETNC r/m8 M Valid Valid Set byte if not carry (CF=0).\r\n REX + 0F 93 SETNC r/m8* M Valid N.E. Set byte if not carry (CF=0).\r\n 0F 95 SETNE r/m8 M Valid Valid Set byte if not equal (ZF=0).\r\n REX + 0F 95 SETNE r/m8* M Valid N.E. Set byte if not equal (ZF=0).\r\n 0F 9E SETNG r/m8 M Valid Valid Set byte if not greater (ZF=1 or SF!= OF)\r\n REX + 0F 9E SETNG r/m8* M Valid N.E. Set byte if not greater (ZF=1 or SF!= OF).\r\n 0F 9C SETNGE r/m8 M Valid Valid Set byte if not greater or equal (SF!= OF).\r\n REX + 0F 9C SETNGE r/m8* M Valid N.E. Set byte if not greater or equal (SF!= OF).\r\n 0F 9D SETNL r/m8 M Valid Valid Set byte if not less (SF=OF).\r\n REX + 0F 9D SETNL r/m8* M Valid N.E. Set byte if not less (SF=OF).\r\n 0F 9F SETNLE r/m8 M Valid Valid Set byte if not less or equal (ZF=0 and SF=OF).\r\n\r\n\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n REX + 0F 9F SETNLE r/m8* M Valid N.E. Set byte if not less or equal (ZF=0 and SF=OF).\r\n 0F 91 SETNO r/m8 M Valid Valid Set byte if not overflow (OF=0).\r\n REX + 0F 91 SETNO r/m8* M Valid N.E. Set byte if not overflow (OF=0).\r\n 0F 9B SETNP r/m8 M Valid Valid Set byte if not parity (PF=0).\r\n\r\n\r\n REX + 0F 9B SETNP r/m8* M Valid N.E. Set byte if not parity (PF=0).\r\n 0F 99 SETNS r/m8 M Valid Valid Set byte if not sign (SF=0).\r\n REX + 0F 99 SETNS r/m8* M Valid N.E. Set byte if not sign (SF=0).\r\n 0F 95 SETNZ r/m8 M Valid Valid Set byte if not zero (ZF=0).\r\n REX + 0F 95 SETNZ r/m8* M Valid N.E. Set byte if not zero (ZF=0).\r\n 0F 90 SETO r/m8 M Valid Valid Set byte if overflow (OF=1)\r\n REX + 0F 90 SETO r/m8* M Valid N.E. Set byte if overflow (OF=1).\r\n 0F 9A SETP r/m8 M Valid Valid Set byte if parity (PF=1).\r\n REX + 0F 9A SETP r/m8* M Valid N.E. Set byte if parity (PF=1).\r\n 0F 9A SETPE r/m8 M Valid Valid Set byte if parity even (PF=1).\r\n REX + 0F 9A SETPE r/m8* M Valid N.E. Set byte if parity even (PF=1).\r\n 0F 9B SETPO r/m8 M Valid Valid Set byte if parity odd (PF=0).\r\n REX + 0F 9B SETPO r/m8* M Valid N.E. Set byte if parity odd (PF=0).\r\n 0F 98 SETS r/m8 M Valid Valid Set byte if sign (SF=1).\r\n REX + 0F 98 SETS r/m8* M Valid N.E. Set byte if sign (SF=1).\r\n 0F 94 SETZ r/m8 M Valid Valid Set byte if zero (ZF=1).\r\n REX + 0F 94 SETZ r/m8* M Valid N.E. Set byte if zero (ZF=1).\r\n NOTES:\r\n * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (r) NA NA NA\r\n\r\n\r\nDescription\r\nSets the destination operand to 0 or 1 depending on the settings of the status flags (CF, SF, OF, ZF, and PF) in the\r\nEFLAGS register. The destination operand points to a byte register or a byte in memory. The condition code suffix\r\n(cc) indicates the condition being tested for.\r\nThe terms \"above\" and \"below\" are associated with the CF flag and refer to the relationship between two unsigned\r\ninteger values. The terms \"greater\" and \"less\" are associated with the SF and OF flags and refer to the relationship\r\nbetween two signed integer values.\r\nMany of the SETcc instruction opcodes have alternate mnemonics. For example, SETG (set byte if greater) and\r\nSETNLE (set if not less or equal) have the same opcode and test for the same condition: ZF equals 0 and SF equals\r\nOF. These alternate mnemonics are provided to make code more intelligible. Appendix B, \"EFLAGS Condition\r\nCodes,\" in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, shows the alternate\r\nmnemonics for various test conditions.\r\nSome languages represent a logical one as an integer with all bits set. This representation can be obtained by\r\nchoosing the logically opposite condition for the SETcc instruction, then decrementing the result. For example, to\r\ntest for overflow, use the SETNO instruction, then decrement the result.\r\n\r\n\r\n\r\nIn IA-64 mode, the operand size is fixed at 8 bits. Use of REX prefix enable uniform addressing to additional byte\r\nregisters. Otherwise, this instruction's operation is the same as in legacy mode and compatibility mode.\r\n\r\nOperation\r\nIF condition\r\n THEN DEST <- 1;\r\n ELSE DEST <- 0;\r\nFI;\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination is located in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SETcc"
},
{
"description": "SFENCE-Store Fence\r\n Opcode* Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F AE F8 SFENCE NP Valid Valid Serializes store operations.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nPerforms a serializing operation on all store-to-memory instructions that were issued prior the SFENCE instruction.\r\nThis serializing operation guarantees that every store instruction that precedes the SFENCE instruction in program\r\norder becomes globally visible before any store instruction that follows the SFENCE instruction. The SFENCE\r\ninstruction is ordered with respect to store instructions, other SFENCE instructions, any LFENCE and MFENCE\r\ninstructions, and any serializing instructions (such as the CPUID instruction). It is not ordered with respect to load\r\ninstructions.\r\nWeakly ordered memory types can be used to achieve higher processor performance through such techniques as\r\nout-of-order issue, write-combining, and write-collapsing. The degree to which a consumer of data recognizes or\r\nknows that the data is weakly ordered varies among applications and may be unknown to the producer of this data.\r\nThe SFENCE instruction provides a performance-efficient way of ensuring store ordering between routines that\r\nproduce weakly-ordered results and routines that consume this data.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\nSpecification of the instruction's opcode above indicates a ModR/M byte of F8. For this instruction, the processor\r\nignores the r/m field of the ModR/M byte. Thus, SFENCE is encoded by any opcode of the form 0F AE Fx, where x\r\nis in the range 8-F.\r\n\r\nOperation\r\nWait_On_Following_Stores_Until(preceding_stores_globally_visible);\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nvoid _mm_sfence(void)\r\n\r\nExceptions (All Operating Modes)\r\n#UD If CPUID.01H:EDX.SSE[bit 25] = 0.\r\n If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SFENCE"
},
{
"description": "SGDT-Store Global Descriptor Table Register\r\n Opcode* Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F 01 /0 SGDT m M Valid Valid Store GDTR to m.\r\n NOTES:\r\n * See IA-32 Architecture Compatibility section below.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (w) NA NA NA\r\n\r\n\r\nDescription\r\nStores the content of the global descriptor table register (GDTR) in the destination operand. The destination\r\noperand specifies a memory location.\r\nIn legacy or compatibility mode, the destination operand is a 6-byte memory location. If the operand-size attribute\r\nis 16 bits, the limit is stored in the low 2 bytes and the 24-bit base address is stored in bytes 3-5, and byte 6 is zero-\r\nfilled. If the operand-size attribute is 32 bits, the 16-bit limit field of the register is stored in the low 2 bytes of the\r\nmemory location and the 32-bit base address is stored in the high 4 bytes.\r\nIn IA-32e mode, the operand size is fixed at 8+2 bytes. The instruction stores an 8-byte base and a 2-byte limit.\r\nSGDT is useful only by operating-system software. However, it can be used in application programs without causing\r\nan exception to be generated if CR4.UMIP = 0. See \"LGDT/LIDT-Load Global/Interrupt Descriptor Table Register\"\r\nin Chapter 3, Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2A, for information on\r\nloading the GDTR and IDTR.\r\n\r\nIA-32 Architecture Compatibility\r\nThe 16-bit form of the SGDT is compatible with the Intel 286 processor if the upper 8 bits are not referenced. The\r\nIntel 286 processor fills these bits with 1s; processor generations later than the Intel 286 processor fill these bits\r\nwith 0s.\r\n\r\nOperation\r\nIF instruction is SGDT\r\n IF OperandSize = 16\r\n THEN\r\n DEST[0:15] <- GDTR(Limit);\r\n DEST[16:39] <- GDTR(Base); (* 24 bits of base address stored *)\r\n DEST[40:47] <- 0;\r\n ELSE IF (32-bit Operand Size)\r\n DEST[0:15] <- GDTR(Limit);\r\n DEST[16:47] <- GDTR(Base); (* Full 32-bit base address stored *)\r\n FI;\r\n ELSE (* 64-bit Operand Size *)\r\n DEST[0:15] <- GDTR(Limit);\r\n DEST[16:79] <- GDTR(Base); (* Full 64-bit base address stored *)\r\n FI;\r\nFI;\r\n\r\nFlags Affected\r\nNone.\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#UD If the destination operand is a register.\r\n If the LOCK prefix is used.\r\n#GP(0) If the destination is located in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n If CR4.UMIP = 1 and CPL > 0.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while CPL = 3.\r\n\r\nReal-Address Mode Exceptions\r\n#UD If the destination operand is a register.\r\n If the LOCK prefix is used.\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD If the destination operand is a register.\r\n If the LOCK prefix is used.\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If CR4.UMIP = 1.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#UD If the destination operand is a register.\r\n If the LOCK prefix is used.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n If CR4.UMIP = 1 and CPL > 0.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while CPL = 3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SGDT"
},
{
"description": "SHA1MSG1-Perform an Intermediate Calculation for the Next Four SHA1 Message Dwords\r\n Opcode/ Op/En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n 0F 38 C9 /r RM V/V SHA Performs an intermediate calculation for the next four SHA1\r\n SHA1MSG1 xmm1, message dwords using previous message dwords from xmm1 and\r\n xmm2/m128 xmm2/m128, storing the result in xmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA\r\n\r\nDescription\r\nThe SHA1MSG1 instruction is one of two SHA1 message scheduling instructions. The instruction performs an inter-\r\nmediate calculation for the next four SHA1 message dwords.\r\n\r\nOperation\r\nSHA1MSG1\r\n\r\nW0 <- SRC1[127:96] ;\r\nW1 <- SRC1[95:64] ;\r\nW2 <- SRC1[63: 32] ;\r\nW3 <- SRC1[31: 0] ;\r\nW4 <- SRC2[127:96] ;\r\nW5 <- SRC2[95:64] ;\r\n\r\nDEST[127:96] <- W2 XOR W0;\r\nDEST[95:64] <- W3 XOR W1;\r\nDEST[63:32] <- W4 XOR W2;\r\nDEST[31:0] <- W5 XOR W3;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nSHA1MSG1: __m128i _mm_sha1msg1_epu32(__m128i, __m128i);\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SHA1MSG1"
},
{
"description": "SHA1MSG2-Perform a Final Calculation for the Next Four SHA1 Message Dwords\r\n Opcode/ Op/En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n 0F 38 CA /r RM V/V SHA Performs the final calculation for the next four SHA1 message\r\n SHA1MSG2 xmm1, dwords using intermediate results from xmm1 and the previous\r\n xmm2/m128 message dwords from xmm2/m128, storing the result in xmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA\r\n\r\nDescription\r\nThe SHA1MSG2 instruction is one of two SHA1 message scheduling instructions. The instruction performs the final\r\ncalculation to derive the next four SHA1 message dwords.\r\n\r\nOperation\r\nSHA1MSG2\r\n\r\nW13 <- SRC2[95:64] ;\r\nW14 <- SRC2[63: 32] ;\r\nW15 <- SRC2[31: 0] ;\r\nW16 <- (SRC1[127:96] XOR W13 ) ROL 1;\r\nW17 <- (SRC1[95:64] XOR W14) ROL 1;\r\nW18 <- (SRC1[63: 32] XOR W15) ROL 1;\r\nW19 <- (SRC1[31: 0] XOR W16) ROL 1;\r\n\r\nDEST[127:96] <- W16;\r\nDEST[95:64] <- W17;\r\nDEST[63:32] <- W18;\r\nDEST[31:0] <- W19;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n\r\nSHA1MSG2: __m128i _mm_sha1msg2_epu32(__m128i, __m128i);\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SHA1MSG2"
},
{
"description": "SHA1NEXTE-Calculate SHA1 State Variable E after Four Rounds\r\n Opcode/ Op/En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n 0F 38 C8 /r RM V/V SHA Calculates SHA1 state variable E after four rounds of operation\r\n SHA1NEXTE xmm1, from the current SHA1 state variable A in xmm1. The calculated\r\n xmm2/m128 value of the SHA1 state variable E is added to the scheduled\r\n dwords in xmm2/m128, and stored with some of the scheduled\r\n dwords in xmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA\r\n\r\nDescription\r\nThe SHA1NEXTE calculates the SHA1 state variable E after four rounds of operation from the current SHA1 state\r\nvariable A in the destination operand. The calculated value of the SHA1 state variable E is added to the source\r\noperand, which contains the scheduled dwords.\r\n\r\nOperation\r\nSHA1NEXTE\r\n\r\nTMP <- (SRC1[127:96] ROL 30);\r\n\r\nDEST[127:96] <- SRC2[127:96] + TMP;\r\nDEST[95:64] <- SRC2[95:64];\r\nDEST[63:32] <- SRC2[63:32];\r\nDEST[31:0] <- SRC2[31:0];\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nSHA1NEXTE: __m128i _mm_sha1nexte_epu32(__m128i, __m128i);\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SHA1NEXTE"
},
{
"description": "SHA1RNDS4-Perform Four Rounds of SHA1 Operation\r\n Opcode/ Op/En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n 0F 3A CC /r ib RMI V/V SHA Performs four rounds of SHA1 operation operating on SHA1 state\r\n SHA1RNDS4 xmm1, (A,B,C,D) from xmm1, with a pre-computed sum of the next 4\r\n xmm2/m128, imm8 round message dwords and state variable E from xmm2/m128.\r\n The immediate byte controls logic functions and round constants.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3\r\n RMI ModRM:reg (r, w) ModRM:r/m (r) Imm8\r\n\r\nDescription\r\nThe SHA1RNDS4 instruction performs four rounds of SHA1 operation using an initial SHA1 state (A,B,C,D) from the\r\nfirst operand (which is a source operand and the destination operand) and some pre-computed sum of the next 4\r\nround message dwords, and state variable E from the second operand (a source operand). The updated SHA1 state\r\n(A,B,C,D) after four rounds of processing is stored in the destination operand.\r\n\r\nOperation\r\nSHA1RNDS4\r\nThe function f() and Constant K are dependent on the value of the immediate.\r\n\r\nIF ( imm8[1:0] = 0 )\r\n THEN f() <- f0(), K <- K0;\r\nELSE IF ( imm8[1:0] = 1 )\r\n THEN f() <- f1(), K <- K1;\r\nELSE IF ( imm8[1:0] = 2 )\r\n THEN f() <- f2(), K <- K2;\r\nELSE IF ( imm8[1:0] = 3 )\r\n THEN f() <- f3(), K <- K3;\r\nFI;\r\n\r\nA <- SRC1[127:96];\r\nB <- SRC1[95:64];\r\nC <- SRC1[63:32];\r\nD <- SRC1[31:0];\r\nW0E <- SRC2[127:96];\r\nW1 <- SRC2[95:64];\r\nW2 <- SRC2[63:32];\r\nW3 <- SRC2[31:0];\r\n\r\nRound i = 0 operation:\r\nA_1 <- f (B, C, D) + (A ROL 5) +W0E +K;\r\nB_1 <- A;\r\nC_1 <- B ROL 30;\r\nD_1 <- C;\r\nE_1 <- D;\r\n\r\nFOR i = 1 to 3\r\n A_(i +1) <- f (B_i, C_i, D_i) + (A_i ROL 5) +Wi+ E_i +K;\r\n B_(i +1) <- A_i;\r\n\r\n\r\n\r\n C_(i +1) <- B_i ROL 30;\r\n D_(i +1) <- C_i;\r\n E_(i +1) <- D_i;\r\nENDFOR\r\n\r\nDEST[127:96] <- A_4;\r\nDEST[95:64] <- B_4;\r\nDEST[63:32] <- C_4;\r\nDEST[31:0] <- D_4;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nSHA1RNDS4: __m128i _mm_sha1rnds4_epu32(__m128i, __m128i, const int);\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SHA1RNDS4"
},
{
"description": "SHA256MSG1-Perform an Intermediate Calculation for the Next Four SHA256 Message\r\nDwords\r\n Opcode/ Op/En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n 0F 38 CC /r RM V/V SHA Performs an intermediate calculation for the next four SHA256\r\n SHA256MSG1 xmm1, message dwords using previous message dwords from xmm1 and\r\n xmm2/m128 xmm2/m128, storing the result in xmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA\r\n\r\nDescription\r\nThe SHA256MSG1 instruction is one of two SHA256 message scheduling instructions. The instruction performs an\r\nintermediate calculation for the next four SHA256 message dwords.\r\n\r\nOperation\r\nSHA256MSG1\r\n\r\nW4 <- SRC2[31: 0] ;\r\nW3 <- SRC1[127:96] ;\r\nW2 <- SRC1[95:64] ;\r\nW1 <- SRC1[63: 32] ;\r\nW0 <- SRC1[31: 0] ;\r\n\r\nDEST[127:96] <- W3 + o0( W4);\r\nDEST[95:64] <- W2 + o0( W3);\r\nDEST[63:32] <- W1 + o0( W2);\r\nDEST[31:0] <- W0 + o0( W1);\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nSHA256MSG1: __m128i _mm_sha256msg1_epu32(__m128i, __m128i);\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SHA256MSG1"
},
{
"description": "SHA256MSG2-Perform a Final Calculation for the Next Four SHA256 Message Dwords\r\n Opcode/ Op/En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n 0F 38 CD /r RM V/V SHA Performs the final calculation for the next four SHA256 message\r\n SHA256MSG2 xmm1, dwords using previous message dwords from xmm1 and\r\n xmm2/m128 xmm2/m128, storing the result in xmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA\r\n\r\nDescription\r\nThe SHA256MSG2 instruction is one of two SHA2 message scheduling instructions. The instruction performs the\r\nfinal calculation for the next four SHA256 message dwords.\r\n\r\nOperation\r\nSHA256MSG2\r\n\r\nW14 <- SRC2[95:64] ;\r\nW15 <- SRC2[127:96] ;\r\nW16 <- SRC1[31: 0] + o1( W14) ;\r\nW17 <- SRC1[63: 32] + o1( W15) ;\r\nW18 <- SRC1[95: 64] + o1( W16) ;\r\nW19 <- SRC1[127: 96] + o1( W17) ;\r\n\r\nDEST[127:96] <- W19 ;\r\nDEST[95:64] <- W18 ;\r\nDEST[63:32] <- W17 ;\r\nDEST[31:0] <- W16;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nSHA256MSG2 : __m128i _mm_sha256msg2_epu32(__m128i, __m128i);\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SHA256MSG2"
},
{
"description": "SHA256RNDS2-Perform Two Rounds of SHA256 Operation\r\n Opcode/ Op/En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n 0F 38 CB /r RM0 V/V SHA Perform 2 rounds of SHA256 operation using an initial SHA256\r\n SHA256RNDS2 xmm1, state (C,D,G,H) from xmm1, an initial SHA256 state (A,B,E,F) from\r\n xmm2/m128, <XMM0> xmm2/m128, and a pre-computed sum of the next 2 round mes-\r\n sage dwords and the corresponding round constants from the\r\n implicit operand XMM0, storing the updated SHA256 state\r\n (A,B,E,F) result in xmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3\r\n RMI ModRM:reg (r, w) ModRM:r/m (r) Implicit XMM0 (r)\r\n\r\nDescription\r\nThe SHA256RNDS2 instruction performs 2 rounds of SHA256 operation using an initial SHA256 state (C,D,G,H)\r\nfrom the first operand, an initial SHA256 state (A,B,E,F) from the second operand, and a pre-computed sum of the\r\nnext 2 round message dwords and the corresponding round constants from the implicit operand xmm0. Note that\r\nonly the two lower dwords of XMM0 are used by the instruction.\r\nThe updated SHA256 state (A,B,E,F) is written to the first operand, and the second operand can be used as the\r\nupdated state (C,D,G,H) in later rounds.\r\n\r\nOperation\r\nSHA256RNDS2\r\n\r\nA_0 <- SRC2[127:96];\r\nB_0 <- SRC2[95:64];\r\nC_0 <- SRC1[127:96];\r\nD_0 <- SRC1[95:64];\r\nE_0 <- SRC2[63:32];\r\nF_0 <- SRC2[31:0];\r\nG_0 <- SRC1[63:32];\r\nH_0 <- SRC1[31:0];\r\nWK0 <- XMM0[31: 0];\r\nWK1 <- XMM0[63: 32];\r\n\r\nFOR i = 0 to 1\r\n A_(i +1) <- Ch (E_i, F_i, G_i) +o1( E_i) +WKi+ H_i + Maj(A_i , B_i, C_i) +o0( A_i);\r\n B_(i +1) <- A_i;\r\n C_(i +1) <- B_i ;\r\n D_(i +1) <- C_i;\r\n E_(i +1) <- Ch (E_i, F_i, G_i) +o1( E_i) +WKi+ H_i + D_i;\r\n F_(i +1) <- E_i ;\r\n G_(i +1) <- F_i;\r\n H_(i +1) <- G_i;\r\nENDFOR\r\n\r\nDEST[127:96] <- A_2;\r\nDEST[95:64] <- B_2;\r\nDEST[63:32] <- E_2;\r\nDEST[31:0] <- F_2;\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nSHA256RNDS2: __m128i _mm_sha256rnds2_epu32(__m128i, __m128i, __m128i);\r\n\r\nFlags Affected\r\nNone\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SHA256RNDS2"
},
{
"description": "-R:SAL",
"mnem": "SHL"
},
{
"description": "SHLD-Double Precision Shift Left\r\n Opcode* Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F A4 /r ib SHLD r/m16, r16, imm8 MRI Valid Valid Shift r/m16 to left imm8 places while shifting\r\n bits from r16 in from the right.\r\n 0F A5 /r SHLD r/m16, r16, CL MRC Valid Valid Shift r/m16 to left CL places while shifting bits\r\n from r16 in from the right.\r\n 0F A4 /r ib SHLD r/m32, r32, imm8 MRI Valid Valid Shift r/m32 to left imm8 places while shifting\r\n bits from r32 in from the right.\r\n REX.W + 0F A4 /r ib SHLD r/m64, r64, imm8 MRI Valid N.E. Shift r/m64 to left imm8 places while shifting\r\n bits from r64 in from the right.\r\n 0F A5 /r SHLD r/m32, r32, CL MRC Valid Valid Shift r/m32 to left CL places while shifting bits\r\n from r32 in from the right.\r\n REX.W + 0F A5 /r SHLD r/m64, r64, CL MRC Valid N.E. Shift r/m64 to left CL places while shifting\r\n bits from r64 in from the right.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n MRI ModRM:r/m (w) ModRM:reg (r) imm8 NA\r\n MRC ModRM:r/m (w) ModRM:reg (r) CL NA\r\n\r\n\r\nDescription\r\nThe SHLD instruction is used for multi-precision shifts of 64 bits or more.\r\nThe instruction shifts the first operand (destination operand) to the left the number of bits specified by the third\r\noperand (count operand). The second operand (source operand) provides bits to shift in from the right (starting\r\nwith bit 0 of the destination operand).\r\nThe destination operand can be a register or a memory location; the source operand is a register. The count\r\noperand is an unsigned integer that can be stored in an immediate byte or in the CL register. If the count operand\r\nis CL, the shift count is the logical AND of CL and a count mask. In non-64-bit modes and default 64-bit mode; only\r\nbits 0 through 4 of the count are used. This masks the count to a value between 0 and 31. If a count is greater than\r\nthe operand size, the result is undefined.\r\nIf the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand. For a 1-bit\r\nshift, the OF flag is set if a sign change occurred; otherwise, it is cleared. If the count operand is 0, flags are not\r\naffected.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits\r\n(upgrading the count mask to 6 bits). See the summary chart at the beginning of this section for encoding data and\r\nlimits.\r\n\r\nOperation\r\nIF (In 64-Bit Mode and REX.W = 1)\r\n THEN COUNT <- COUNT MOD 64;\r\n ELSE COUNT <- COUNT MOD 32;\r\nFI\r\nSIZE <- OperandSize;\r\nIF COUNT = 0\r\n THEN\r\n No operation;\r\n ELSE\r\n\r\n\r\n\r\n IF COUNT > SIZE\r\n THEN (* Bad parameters *)\r\n DEST is undefined;\r\n CF, OF, SF, ZF, AF, PF are undefined;\r\n ELSE (* Perform the shift *)\r\n CF <- BIT[DEST, SIZE - COUNT];\r\n (* Last bit shifted out on exit *)\r\n FOR i <- SIZE - 1 DOWN TO COUNT\r\n DO\r\n Bit(DEST, i) <- Bit(DEST, i - COUNT);\r\n OD;\r\n FOR i <- COUNT - 1 DOWN TO 0\r\n DO\r\n BIT[DEST, i] <- BIT[SRC, i - COUNT + SIZE];\r\n OD;\r\n FI;\r\nFI;\r\n\r\nFlags Affected\r\nIf the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand and the SF, ZF,\r\nand PF flags are set according to the value of the result. For a 1-bit shift, the OF flag is set if a sign change occurred;\r\notherwise, it is cleared. For shifts greater than 1 bit, the OF flag is undefined. If a shift occurs, the AF flag is unde-\r\nfined. If the count operand is 0, the flags are not affected. If the count is greater than the operand size, the flags\r\nare undefined.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination is located in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SHLD"
},
{
"description": "-R:SARX",
"mnem": "SHLX"
},
{
"description": "-R:SAL",
"mnem": "SHR"
},
{
"description": "SHRD-Double Precision Shift Right\r\n Opcode* Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F AC /r ib SHRD r/m16, r16, imm8 MRI Valid Valid Shift r/m16 to right imm8 places while\r\n shifting bits from r16 in from the left.\r\n 0F AD /r SHRD r/m16, r16, CL MRC Valid Valid Shift r/m16 to right CL places while shifting\r\n bits from r16 in from the left.\r\n 0F AC /r ib SHRD r/m32, r32, imm8 MRI Valid Valid Shift r/m32 to right imm8 places while\r\n shifting bits from r32 in from the left.\r\n REX.W + 0F AC /r ib SHRD r/m64, r64, imm8 MRI Valid N.E. Shift r/m64 to right imm8 places while\r\n shifting bits from r64 in from the left.\r\n 0F AD /r SHRD r/m32, r32, CL MRC Valid Valid Shift r/m32 to right CL places while shifting\r\n bits from r32 in from the left.\r\n REX.W + 0F AD /r SHRD r/m64, r64, CL MRC Valid N.E. Shift r/m64 to right CL places while shifting\r\n bits from r64 in from the left.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n MRI ModRM:r/m (w) ModRM:reg (r) imm8 NA\r\n MRC ModRM:r/m (w) ModRM:reg (r) CL NA\r\n\r\n\r\nDescription\r\nThe SHRD instruction is useful for multi-precision shifts of 64 bits or more.\r\nThe instruction shifts the first operand (destination operand) to the right the number of bits specified by the third\r\noperand (count operand). The second operand (source operand) provides bits to shift in from the left (starting with\r\nthe most significant bit of the destination operand).\r\nThe destination operand can be a register or a memory location; the source operand is a register. The count\r\noperand is an unsigned integer that can be stored in an immediate byte or the CL register. If the count operand is\r\nCL, the shift count is the logical AND of CL and a count mask. In non-64-bit modes and default 64-bit mode, the\r\nwidth of the count mask is 5 bits. Only bits 0 through 4 of the count register are used (masking the count to a value\r\nbetween 0 and 31). If the count is greater than the operand size, the result is undefined.\r\nIf the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand. For a 1-bit\r\nshift, the OF flag is set if a sign change occurred; otherwise, it is cleared. If the count operand is 0, flags are not\r\naffected.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits\r\n(upgrading the count mask to 6 bits). See the summary chart at the beginning of this section for encoding data and\r\nlimits.\r\n\r\nOperation\r\nIF (In 64-Bit Mode and REX.W = 1)\r\n THEN COUNT <- COUNT MOD 64;\r\n ELSE COUNT <- COUNT MOD 32;\r\nFI\r\nSIZE <- OperandSize;\r\nIF COUNT = 0\r\n THEN\r\n No operation;\r\n ELSE\r\n\r\n\r\n\r\n IF COUNT > SIZE\r\n THEN (* Bad parameters *)\r\n DEST is undefined;\r\n CF, OF, SF, ZF, AF, PF are undefined;\r\n ELSE (* Perform the shift *)\r\n CF <- BIT[DEST, COUNT - 1]; (* Last bit shifted out on exit *)\r\n FOR i <- 0 TO SIZE - 1 - COUNT\r\n DO\r\n BIT[DEST, i] <- BIT[DEST, i + COUNT];\r\n OD;\r\n FOR i <- SIZE - COUNT TO SIZE - 1\r\n DO\r\n BIT[DEST,i] <- BIT[SRC, i + COUNT - SIZE];\r\n OD;\r\n FI;\r\nFI;\r\n\r\nFlags Affected\r\nIf the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand and the SF,\r\nZF, and PF flags are set according to the value of the result. For a 1-bit shift, the OF flag is set if a sign change\r\noccurred; otherwise, it is cleared. For shifts greater than 1 bit, the OF flag is undefined. If a shift occurs, the AF flag\r\nis undefined. If the count operand is 0, the flags are not affected. If the count is greater than the operand size, the\r\nflags are undefined.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination is located in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SHRD"
},
{
"description": "-R:SARX",
"mnem": "SHRX"
},
{
"description": "SHUFPD-Packed Interleave Shuffle of Pairs of Double-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0F C6 /r ib RMI V/V SSE2 Shuffle two pairs of double-precision floating-point\r\n SHUFPD xmm1, xmm2/m128, imm8 values from xmm1 and xmm2/m128 using imm8 to\r\n select from each pair, interleaved result is stored in\r\n xmm1.\r\n VEX.NDS.128.66.0F.WIG C6 /r ib RVMI V/V AVX Shuffle two pairs of double-precision floating-point\r\n VSHUFPD xmm1, xmm2, xmm3/m128, values from xmm2 and xmm3/m128 using imm8 to\r\n imm8 select from each pair, interleaved result is stored in\r\n xmm1.\r\n VEX.NDS.256.66.0F.WIG C6 /r ib RVMI V/V AVX Shuffle four pairs of double-precision floating-point\r\n VSHUFPD ymm1, ymm2, ymm3/m256, values from ymm2 and ymm3/m256 using imm8 to\r\n imm8 select from each pair, interleaved result is stored in\r\n xmm1.\r\n EVEX.NDS.128.66.0F.W1 C6 /r ib FV V/V AVX512VL Shuffle two paris of double-precision floating-point\r\n VSHUFPD xmm1{k1}{z}, xmm2, AVX512F values from xmm2 and xmm3/m128/m64bcst using\r\n xmm3/m128/m64bcst, imm8 imm8 to select from each pair. store interleaved\r\n results in xmm1 subject to writemask k1.\r\n EVEX.NDS.256.66.0F.W1 C6 /r ib FV V/V AVX512VL Shuffle four paris of double-precision floating-point\r\n VSHUFPD ymm1{k1}{z}, ymm2, AVX512F values from ymm2 and ymm3/m256/m64bcst using\r\n ymm3/m256/m64bcst, imm8 imm8 to select from each pair. store interleaved\r\n results in ymm1 subject to writemask k1.\r\n EVEX.NDS.512.66.0F.W1 C6 /r ib FV V/V AVX512F Shuffle eight paris of double-precision floating-point\r\n VSHUFPD zmm1{k1}{z}, zmm2, values from zmm2 and zmm3/m512/m64bcst using\r\n zmm3/m512/m64bcst, imm8 imm8 to select from each pair. store interleaved\r\n results in zmm1 subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (r, w) ModRM:r/m (r) Imm8 NA\r\n RVMI ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) Imm8\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) Imm8\r\n\r\nDescription\r\nSelects a double-precision floating-point value of an input pair using a bit control and move to a designated\r\nelement of the destination operand. The low-to-high order of double-precision element of the destination operand\r\nis interleaved between the first source operand and the second source operand at the granularity of input pair of\r\n128 bits. Each bit in the imm8 byte, starting from bit 0, is the select control of the corresponding element of the\r\ndestination to received the shuffled result of an input pair.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be\r\na ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a\r\n64-bit memory location The destination operand is a ZMM/YMM/XMM register updated according to the writemask.\r\nThe select controls are the lower 8/4/2 bits of the imm8 byte.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register. The select controls are the bit 3:0\r\nof the imm8 byte, imm8[7:4) are ignored.\r\nVEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM\r\nregister or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed. The select controls are the bit 1:0 of the imm8 byte,\r\nimm8[7:2) are ignored.\r\n\r\n\r\n\r\n\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation operand and the first source operand is the same and is an XMM register. The upper bits (MAX_VL-1:128) of\r\nthe corresponding ZMM register destination are unmodified. The select controls are the bit 1:0 of the imm8 byte,\r\nimm8[7:2) are ignored.\r\n\r\n\r\n\r\n\r\n SRC1 X3 X2 X1 X0\r\n\r\n\r\n\r\n SRC2 Y3 Y2 Y1 Y0\r\n\r\n\r\n\r\n DEST Y2 or Y3 X2 or X3 Y0 or Y1 X0 or X1\r\n\r\n\r\n\r\n Figure 4-25. 256-bit VSHUFPD Operation of Four Pairs of DP FP Values\r\n\r\n\r\nOperation\r\nVSHUFPD (EVEX encoded versions when SRC2 is a vector register)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF IMM0[0] = 0\r\n THEN TMP_DEST[63:0] <- SRC1[63:0]\r\n ELSE TMP_DEST[63:0] <- SRC1[127:64] FI;\r\nIF IMM0[1] = 0\r\n THEN TMP_DEST[127:64] <- SRC2[63:0]\r\n ELSE TMP_DEST[127:64] <- SRC2[127:64] FI;\r\nIF VL >= 256\r\n IF IMM0[2] = 0\r\n THEN TMP_DEST[191:128] <- SRC1[191:128]\r\n ELSE TMP_DEST[191:128] <- SRC1[255:192] FI;\r\n IF IMM0[3] = 0\r\n THEN TMP_DEST[255:192] <- SRC2[191:128]\r\n ELSE TMP_DEST[255:192] <- SRC2[255:192] FI;\r\nFI;\r\nIF VL >= 512\r\n IF IMM0[4] = 0\r\n THEN TMP_DEST[319:256] <- SRC1[319:256]\r\n ELSE TMP_DEST[319:256] <- SRC1[383:320] FI;\r\n IF IMM0[5] = 0\r\n THEN TMP_DEST[383:320] <- SRC2[319:256]\r\n ELSE TMP_DEST[383:320] <- SRC2[383:320] FI;\r\n IF IMM0[6] = 0\r\n THEN TMP_DEST[447:384] <- SRC1[447:384]\r\n ELSE TMP_DEST[447:384] <- SRC1[511:448] FI;\r\n IF IMM0[7] = 0\r\n THEN TMP_DEST[511:448] <- SRC2[447:384]\r\n ELSE TMP_DEST[511:448] <- SRC2[511:448] FI;\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE\r\n\r\n\r\n\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVSHUFPD (EVEX encoded versions when SRC2 is memory)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF (EVEX.b = 1)\r\n THEN TMP_SRC2[i+63:i] <- SRC2[63:0]\r\n ELSE TMP_SRC2[i+63:i] <- SRC2[i+63:i]\r\n FI;\r\nENDFOR;\r\nIF IMM0[0] = 0\r\n THEN TMP_DEST[63:0] <- SRC1[63:0]\r\n ELSE TMP_DEST[63:0] <- SRC1[127:64] FI;\r\nIF IMM0[1] = 0\r\n THEN TMP_DEST[127:64] <- TMP_SRC2[63:0]\r\n ELSE TMP_DEST[127:64] <- TMP_SRC2[127:64] FI;\r\nIF VL >= 256\r\n IF IMM0[2] = 0\r\n THEN TMP_DEST[191:128] <- SRC1[191:128]\r\n ELSE TMP_DEST[191:128] <- SRC1[255:192] FI;\r\n IF IMM0[3] = 0\r\n THEN TMP_DEST[255:192] <- TMP_SRC2[191:128]\r\n ELSE TMP_DEST[255:192] <- TMP_SRC2[255:192] FI;\r\nFI;\r\nIF VL >= 512\r\n IF IMM0[4] = 0\r\n THEN TMP_DEST[319:256] <- SRC1[319:256]\r\n ELSE TMP_DEST[319:256] <- SRC1[383:320] FI;\r\n IF IMM0[5] = 0\r\n THEN TMP_DEST[383:320] <- TMP_SRC2[319:256]\r\n ELSE TMP_DEST[383:320] <- TMP_SRC2[383:320] FI;\r\n IF IMM0[6] = 0\r\n THEN TMP_DEST[447:384] <- SRC1[447:384]\r\n ELSE TMP_DEST[447:384] <- SRC1[511:448] FI;\r\n IF IMM0[7] = 0\r\n THEN TMP_DEST[511:448] <- TMP_SRC2[447:384]\r\n ELSE TMP_DEST[511:448] <- TMP_SRC2[511:448] FI;\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n\r\n\r\n\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVSHUFPD (VEX.256 encoded version)\r\nIF IMM0[0] = 0\r\n THEN DEST[63:0] <-SRC1[63:0]\r\n ELSE DEST[63:0] <-SRC1[127:64] FI;\r\nIF IMM0[1] = 0\r\n THEN DEST[127:64] <-SRC2[63:0]\r\n ELSE DEST[127:64] <-SRC2[127:64] FI;\r\nIF IMM0[2] = 0\r\n THEN DEST[191:128] <-SRC1[191:128]\r\n ELSE DEST[191:128] <-SRC1[255:192] FI;\r\nIF IMM0[3] = 0\r\n THEN DEST[255:192] <-SRC2[191:128]\r\n ELSE DEST[255:192] <-SRC2[255:192] FI;\r\nDEST[MAX_VL-1:256] (Unmodified)\r\n\r\nVSHUFPD (VEX.128 encoded version)\r\nIF IMM0[0] = 0\r\n THEN DEST[63:0] <-SRC1[63:0]\r\n ELSE DEST[63:0] <-SRC1[127:64] FI;\r\nIF IMM0[1] = 0\r\n THEN DEST[127:64] <-SRC2[63:0]\r\n ELSE DEST[127:64] <-SRC2[127:64] FI;\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVSHUFPD (128-bit Legacy SSE version)\r\nIF IMM0[0] = 0\r\n THEN DEST[63:0] <-SRC1[63:0]\r\n ELSE DEST[63:0] <-SRC1[127:64] FI;\r\nIF IMM0[1] = 0\r\n THEN DEST[127:64] <-SRC2[63:0]\r\n ELSE DEST[127:64] <-SRC2[127:64] FI;\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVSHUFPD __m512d _mm512_shuffle_pd(__m512d a, __m512d b, int imm);\r\nVSHUFPD __m512d _mm512_mask_shuffle_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int imm);\r\nVSHUFPD __m512d _mm512_maskz_shuffle_pd( __mmask8 k, __m512d a, __m512d b, int imm);\r\nVSHUFPD __m256d _mm256_shuffle_pd (__m256d a, __m256d b, const int select);\r\nVSHUFPD __m256d _mm256_mask_shuffle_pd(__m256d s, __mmask8 k, __m256d a, __m256d b, int imm);\r\nVSHUFPD __m256d _mm256_maskz_shuffle_pd( __mmask8 k, __m256d a, __m256d b, int imm);\r\nSHUFPD __m128d _mm_shuffle_pd (__m128d a, __m128d b, const int select);\r\nVSHUFPD __m128d _mm_mask_shuffle_pd(__m128d s, __mmask8 k, __m128d a, __m128d b, int imm);\r\nVSHUFPD __m128d _mm_maskz_shuffle_pd( __mmask8 k, __m128d a, __m128d b, int imm);\r\n\r\n\r\n\r\n\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4NF.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SHUFPD"
},
{
"description": "SHUFPS-Packed Interleave Shuffle of Quadruplets of Single-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 0F C6 /r ib RMI V/V SSE Select from quadruplet of single-precision floating-\r\n SHUFPS xmm1, xmm3/m128, imm8 point values in xmm1 and xmm2/m128 using imm8,\r\n interleaved result pairs are stored in xmm1.\r\n VEX.NDS.128.0F.WIG C6 /r ib RVMI V/V AVX Select from quadruplet of single-precision floating-\r\n VSHUFPS xmm1, xmm2, point values in xmm1 and xmm2/m128 using imm8,\r\n xmm3/m128, imm8 interleaved result pairs are stored in xmm1.\r\n VEX.NDS.256.0F.WIG C6 /r ib RVMI V/V AVX Select from quadruplet of single-precision floating-\r\n VSHUFPS ymm1, ymm2, point values in ymm2 and ymm3/m256 using imm8,\r\n ymm3/m256, imm8 interleaved result pairs are stored in ymm1.\r\n EVEX.NDS.128.0F.W0 C6 /r ib FV V/V AVX512VL Select from quadruplet of single-precision floating-\r\n VSHUFPS xmm1{k1}{z}, xmm2, AVX512F point values in xmm1 and xmm2/m128 using imm8,\r\n xmm3/m128/m32bcst, imm8 interleaved result pairs are stored in xmm1, subject to\r\n writemask k1.\r\n EVEX.NDS.256.0F.W0 C6 /r ib FV V/V AVX512VL Select from quadruplet of single-precision floating-\r\n VSHUFPS ymm1{k1}{z}, ymm2, AVX512F point values in ymm2 and ymm3/m256 using imm8,\r\n ymm3/m256/m32bcst, imm8 interleaved result pairs are stored in ymm1, subject to\r\n writemask k1.\r\n EVEX.NDS.512.0F.W0 C6 /r ib FV V/V AVX512F Select from quadruplet of single-precision floating-\r\n VSHUFPS zmm1{k1}{z}, zmm2, point values in zmm2 and zmm3/m512 using imm8,\r\n zmm3/m512/m32bcst, imm8 interleaved result pairs are stored in zmm1, subject to\r\n writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (r, w) ModRM:r/m (r) Imm8 NA\r\n RVMI ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) Imm8\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) Imm8\r\n\r\nDescription\r\nSelects a single-precision floating-point value of an input quadruplet using a two-bit control and move to a desig-\r\nnated element of the destination operand. Each 64-bit element-pair of a 128-bit lane of the destination operand is\r\ninterleaved between the corresponding lane of the first source operand and the second source operand at the gran-\r\nularity 128 bits. Each two bits in the imm8 byte, starting from bit 0, is the select control of the corresponding\r\nelement of a 128-bit lane of the destination to received the shuffled result of an input quadruplet. The two lower\r\nelements of a 128-bit lane in the destination receives shuffle results from the quadruple of the first source operand.\r\nThe next two elements of the destination receives shuffle results from the quadruple of the second source operand.\r\nEVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be\r\na ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a\r\n32-bit memory location. The destination operand is a ZMM/YMM/XMM register updated according to the writemask.\r\nImm8[7:0] provides 4 select controls for each applicable 128-bit lane of the destination.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register. Imm8[7:0] provides 4 select\r\ncontrols for the high and low 128-bit of the destination.\r\nVEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM\r\nregister or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed. Imm8[7:0] provides 4 select controls for each element\r\nof the destination.\r\n\r\n\r\n\r\n\r\n\r\n128-bit Legacy SSE version: The source can be an XMM register or an 128-bit memory location. The destination is\r\nnot distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding ZMM\r\nregister destination are unmodified. Imm8[7:0] provides 4 select controls for each element of the destination.\r\n\r\n\r\n\r\n\r\n SRC1 X7 X6 X5 X4 X3 X2 X1 X0\r\n\r\n\r\n\r\n SRC2 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0\r\n\r\n\r\n\r\n DEST Y7 .. Y4 Y7 .. Y4 X7 .. X4 X7 .. X4 Y3 ..Y0 Y3 ..Y0 X3 .. X0 X3 .. X0\r\n\r\n\r\n\r\n\r\n Figure 4-26. 256-bit VSHUFPS Operation of Selection from Input Quadruplet and Pair-wise Interleaved Result\r\n\r\n\r\nOperation\r\nSelect4(SRC, control) {\r\nCASE (control[1:0]) OF\r\n 0: TMP <-SRC[31:0];\r\n 1: TMP <-SRC[63:32];\r\n 2: TMP <-SRC[95:64];\r\n 3: TMP <-SRC[127:96];\r\nESAC;\r\nRETURN TMP\r\n}\r\n\r\nVPSHUFPS (EVEX encoded versions when SRC2 is a vector register)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nTMP_DEST[31:0] <- Select4(SRC1[127:0], imm8[1:0]);\r\nTMP_DEST[63:32] <- Select4(SRC1[127:0], imm8[3:2]);\r\nTMP_DEST[95:64] <- Select4(SRC2[127:0], imm8[5:4]);\r\nTMP_DEST[127:96] <- Select4(SRC2[127:0], imm8[7:6]);\r\nIF VL >= 256\r\n TMP_DEST[159:128] <- Select4(SRC1[255:128], imm8[1:0]);\r\n TMP_DEST[191:160] <- Select4(SRC1[255:128], imm8[3:2]);\r\n TMP_DEST[223:192] <- Select4(SRC2[255:128], imm8[5:4]);\r\n TMP_DEST[255:224] <- Select4(SRC2[255:128], imm8[7:6]);\r\nFI;\r\nIF VL >= 512\r\n TMP_DEST[287:256] <- Select4(SRC1[383:256], imm8[1:0]);\r\n TMP_DEST[319:288] <- Select4(SRC1[383:256], imm8[3:2]);\r\n TMP_DEST[351:320] <- Select4(SRC2[383:256], imm8[5:4]);\r\n TMP_DEST[383:352] <- Select4(SRC2[383:256], imm8[7:6]);\r\n TMP_DEST[415:384] <- Select4(SRC1[511:384], imm8[1:0]);\r\n TMP_DEST[447:416] <- Select4(SRC1[511:384], imm8[3:2]);\r\n TMP_DEST[479:448] <-Select4(SRC2[511:384], imm8[5:4]);\r\n TMP_DEST[511:480] <- Select4(SRC2[511:384], imm8[7:6]);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n\r\n\r\n\r\n\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_DEST[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPSHUFPS (EVEX encoded versions when SRC2 is memory)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF (EVEX.b = 1)\r\n THEN TMP_SRC2[i+31:i] <- SRC2[31:0]\r\n ELSE TMP_SRC2[i+31:i] <- SRC2[i+31:i]\r\n FI;\r\nENDFOR;\r\nTMP_DEST[31:0] <- Select4(SRC1[127:0], imm8[1:0]);\r\nTMP_DEST[63:32] <- Select4(SRC1[127:0], imm8[3:2]);\r\nTMP_DEST[95:64] <- Select4(TMP_SRC2[127:0], imm8[5:4]);\r\nTMP_DEST[127:96] <- Select4(TMP_SRC2[127:0], imm8[7:6]);\r\nIF VL >= 256\r\n TMP_DEST[159:128] <- Select4(SRC1[255:128], imm8[1:0]);\r\n TMP_DEST[191:160] <- Select4(SRC1[255:128], imm8[3:2]);\r\n TMP_DEST[223:192] <- Select4(TMP_SRC2[255:128], imm8[5:4]);\r\n TMP_DEST[255:224] <- Select4(TMP_SRC2[255:128], imm8[7:6]);\r\nFI;\r\nIF VL >= 512\r\n TMP_DEST[287:256] <- Select4(SRC1[383:256], imm8[1:0]);\r\n TMP_DEST[319:288] <- Select4(SRC1[383:256], imm8[3:2]);\r\n TMP_DEST[351:320] <- Select4(TMP_SRC2[383:256], imm8[5:4]);\r\n TMP_DEST[383:352] <- Select4(TMP_SRC2[383:256], imm8[7:6]);\r\n TMP_DEST[415:384] <- Select4(SRC1[511:384], imm8[1:0]);\r\n TMP_DEST[447:416] <- Select4(SRC1[511:384], imm8[3:2]);\r\n TMP_DEST[479:448] <-Select4(TMP_SRC2[511:384], imm8[5:4]);\r\n TMP_DEST[511:480] <- Select4(TMP_SRC2[511:384], imm8[7:6]);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_DEST[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\n\r\n\r\n\r\nDEST[MAX_VL-1:VL] <- 0\r\nVSHUFPS (VEX.256 encoded version)\r\nDEST[31:0] <-Select4(SRC1[127:0], imm8[1:0]);\r\nDEST[63:32] <-Select4(SRC1[127:0], imm8[3:2]);\r\nDEST[95:64] <-Select4(SRC2[127:0], imm8[5:4]);\r\nDEST[127:96] <-Select4(SRC2[127:0], imm8[7:6]);\r\nDEST[159:128] <-Select4(SRC1[255:128], imm8[1:0]);\r\nDEST[191:160] <-Select4(SRC1[255:128], imm8[3:2]);\r\nDEST[223:192] <-Select4(SRC2[255:128], imm8[5:4]);\r\nDEST[255:224] <-Select4(SRC2[255:128], imm8[7:6]);\r\nDEST[MAX_VL-1:256] <-0\r\n\r\nVSHUFPS (VEX.128 encoded version)\r\nDEST[31:0] <-Select4(SRC1[127:0], imm8[1:0]);\r\nDEST[63:32] <-Select4(SRC1[127:0], imm8[3:2]);\r\nDEST[95:64] <-Select4(SRC2[127:0], imm8[5:4]);\r\nDEST[127:96] <-Select4(SRC2[127:0], imm8[7:6]);\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nSHUFPS (128-bit Legacy SSE version)\r\nDEST[31:0] <-Select4(SRC1[127:0], imm8[1:0]);\r\nDEST[63:32] <-Select4(SRC1[127:0], imm8[3:2]);\r\nDEST[95:64] <-Select4(SRC2[127:0], imm8[5:4]);\r\nDEST[127:96] <-Select4(SRC2[127:0], imm8[7:6]);\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVSHUFPS __m512 _mm512_shuffle_ps(__m512 a, __m512 b, int imm);\r\nVSHUFPS __m512 _mm512_mask_shuffle_ps(__m512 s, __mmask16 k, __m512 a, __m512 b, int imm);\r\nVSHUFPS __m512 _mm512_maskz_shuffle_ps(__mmask16 k, __m512 a, __m512 b, int imm);\r\nVSHUFPS __m256 _mm256_shuffle_ps (__m256 a, __m256 b, const int select);\r\nVSHUFPS __m256 _mm256_mask_shuffle_ps(__m256 s, __mmask8 k, __m256 a, __m256 b, int imm);\r\nVSHUFPS __m256 _mm256_maskz_shuffle_ps(__mmask8 k, __m256 a, __m256 b, int imm);\r\nSHUFPS __m128 _mm_shuffle_ps (__m128 a, __m128 b, const int select);\r\nVSHUFPS __m128 _mm_mask_shuffle_ps(__m128 s, __mmask8 k, __m128 a, __m128 b, int imm);\r\nVSHUFPS __m128 _mm_maskz_shuffle_ps(__mmask8 k, __m128 a, __m128 b, int imm);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4NF.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SHUFPS"
},
{
"description": "SIDT-Store Interrupt Descriptor Table Register\r\n Opcode* Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F 01 /1 SIDT m M Valid Valid Store IDTR to m.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (w) NA NA NA\r\n\r\n\r\nDescription\r\nStores the content the interrupt descriptor table register (IDTR) in the destination operand. The destination\r\noperand specifies a 6-byte memory location.\r\nIn non-64-bit modes, if the operand-size attribute is 32 bits, the 16-bit limit field of the register is stored in the low\r\n2 bytes of the memory location and the 32-bit base address is stored in the high 4 bytes. If the operand-size attri-\r\nbute is 16 bits, the limit is stored in the low 2 bytes and the 24-bit base address is stored in the third, fourth, and\r\nfifth byte, with the sixth byte filled with 0s.\r\nIn 64-bit mode, the operand size fixed at 8+2 bytes. The instruction stores 8-byte base and 2-byte limit values.\r\nSIDT is only useful in operating-system software; however, it can be used in application programs without causing\r\nan exception to be generated if CR4.UMIP = 0. See \"LGDT/LIDT-Load Global/Interrupt Descriptor Table Register\"\r\nin Chapter 3, Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2A, for information on\r\nloading the GDTR and IDTR.\r\n\r\nIA-32 Architecture Compatibility\r\nThe 16-bit form of SIDT is compatible with the Intel 286 processor if the upper 8 bits are not referenced. The Intel\r\n286 processor fills these bits with 1s; processor generations later than the Intel 286 processor fill these bits with\r\n0s.\r\n\r\nOperation\r\nIF instruction is SIDT\r\n THEN\r\n IF OperandSize = 16\r\n THEN\r\n DEST[0:15] <- IDTR(Limit);\r\n DEST[16:39] <- IDTR(Base); (* 24 bits of base address stored; *)\r\n DEST[40:47] <- 0;\r\n ELSE IF (32-bit Operand Size)\r\n DEST[0:15] <- IDTR(Limit);\r\n DEST[16:47] <- IDTR(Base); FI; (* Full 32-bit base address stored *)\r\n ELSE (* 64-bit Operand Size *)\r\n DEST[0:15] <- IDTR(Limit);\r\n DEST[16:79] <- IDTR(Base); (* Full 64-bit base address stored *)\r\n FI;\r\nFI;\r\n\r\nFlags Affected\r\nNone.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination is located in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n If CR4.UMIP = 1 and CPL > 0.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while CPL = 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If CR4.UMIP = 1.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#UD If the destination operand is a register.\r\n If the LOCK prefix is used.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n If CR4.UMIP = 1 and CPL > 0.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while CPL = 3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SIDT"
},
{
"description": "SLDT-Store Local Descriptor Table Register\r\n Opcode* Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F 00 /0 SLDT r/m16 M Valid Valid Stores segment selector from LDTR in r/m16.\r\n REX.W + 0F 00 /0 SLDT r64/m16 M Valid Valid Stores segment selector from LDTR in\r\n r64/m16.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (w) NA NA NA\r\n\r\n\r\nDescription\r\nStores the segment selector from the local descriptor table register (LDTR) in the destination operand. The desti-\r\nnation operand can be a general-purpose register or a memory location. The segment selector stored with this\r\ninstruction points to the segment descriptor (located in the GDT) for the current LDT. This instruction can only be\r\nexecuted in protected mode.\r\nOutside IA-32e mode, when the destination operand is a 32-bit register, the 16-bit segment selector is copied into\r\nthe low-order 16 bits of the register. The high-order 16 bits of the register are cleared for the Pentium 4, Intel Xeon,\r\nand P6 family processors. They are undefined for Pentium, Intel486, and Intel386 processors. When the destina-\r\ntion operand is a memory location, the segment selector is written to memory as a 16-bit quantity, regardless of\r\nthe operand size.\r\nIn compatibility mode, when the destination operand is a 32-bit register, the 16-bit segment selector is copied into\r\nthe low-order 16 bits of the register. The high-order 16 bits of the register are cleared. When the destination\r\noperand is a memory location, the segment selector is written to memory as a 16-bit quantity, regardless of the\r\noperand size.\r\nIn 64-bit mode, using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). The\r\nbehavior of SLDT with a 64-bit register is to zero-extend the 16-bit selector and store it in the register. If the desti-\r\nnation is memory and operand size is 64, SLDT will write the 16-bit selector to memory as a 16-bit quantity,\r\nregardless of the operand size.\r\n\r\nOperation\r\nDEST <- LDTR(SegmentSelector);\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination is located in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n If CR4.UMIP = 1 and CPL > 0.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while CPL = 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#UD The SLDT instruction is not recognized in real-address mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD The SLDT instruction is not recognized in virtual-8086 mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n If CR4.UMIP = 1 and CPL > 0.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while CPL = 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SLDT"
},
{
"description": "SMSW-Store Machine Status Word\r\n Opcode* Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F 01 /4 SMSW r/m16 M Valid Valid Store machine status word to r/m16.\r\n 0F 01 /4 SMSW r32/m16 M Valid Valid Store machine status word in low-order 16\r\n bits of r32/m16; high-order 16 bits of r32 are\r\n undefined.\r\n REX.W + 0F 01 /4 SMSW r64/m16 M Valid Valid Store machine status word in low-order 16\r\n bits of r64/m16; high-order 16 bits of r32 are\r\n undefined.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (w) NA NA NA\r\n\r\n\r\nDescription\r\nStores the machine status word (bits 0 through 15 of control register CR0) into the destination operand. The desti-\r\nnation operand can be a general-purpose register or a memory location.\r\nIn non-64-bit modes, when the destination operand is a 32-bit register, the low-order 16 bits of register CR0 are\r\ncopied into the low-order 16 bits of the register and the high-order 16 bits are undefined. When the destination\r\noperand is a memory location, the low-order 16 bits of register CR0 are written to memory as a 16-bit quantity,\r\nregardless of the operand size.\r\nIn 64-bit mode, the behavior of the SMSW instruction is defined by the following examples:\r\n. SMSW r16 operand size 16, store CR0[15:0] in r16\r\n. SMSW r32 operand size 32, zero-extend CR0[31:0], and store in r32\r\n. SMSW r64 operand size 64, zero-extend CR0[63:0], and store in r64\r\n. SMSW m16 operand size 16, store CR0[15:0] in m16\r\n. SMSW m16 operand size 32, store CR0[15:0] in m16 (not m32)\r\n. SMSW m16 operands size 64, store CR0[15:0] in m16 (not m64)\r\nSMSW is only useful in operating-system software. However, it is not a privileged instruction and can be used in\r\napplication programs if CR4.UMIP = 0. It is provided for compatibility with the Intel 286 processor. Programs and\r\nprocedures intended to run on IA-32 and Intel 64 processors beginning with the Intel386 processors should use the\r\nMOV CR instruction to load the machine status word.\r\nSee \"Changes to Instruction Behavior in VMX Non-Root Operation\" in Chapter 25 of the Intel 64 and IA-32 Archi-\r\ntectures Software Developer's Manual, Volume 3C, for more information about the behavior of this instruction in\r\nVMX non-root operation.\r\n\r\nOperation\r\nDEST <- CR0[15:0];\r\n(* Machine status word *)\r\n\r\nFlags Affected\r\nNone.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination is located in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n If CR4.UMIP = 1 and CPL > 0.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while CPL = 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If CR4.UMIP = 1.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n If CR4.UMIP = 1 and CPL > 0.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while CPL = 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SMSW"
},
{
"description": "SQRTPD-Square Root of Double-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0F 51 /r RM V/V SSE2 Computes Square Roots of the packed double-precision\r\n SQRTPD xmm1, xmm2/m128 floating-point values in xmm2/m128 and stores the result\r\n in xmm1.\r\n VEX.128.66.0F.WIG 51 /r RM V/V AVX Computes Square Roots of the packed double-precision\r\n VSQRTPD xmm1, xmm2/m128 floating-point values in xmm2/m128 and stores the result\r\n in xmm1.\r\n VEX.256.66.0F.WIG 51 /r RM V/V AVX Computes Square Roots of the packed double-precision\r\n VSQRTPD ymm1, ymm2/m256 floating-point values in ymm2/m256 and stores the result\r\n in ymm1.\r\n EVEX.128.66.0F.W1 51 /r FV V/V AVX512VL Computes Square Roots of the packed double-precision\r\n VSQRTPD xmm1 {k1}{z}, AVX512F floating-point values in xmm2/m128/m64bcst and stores\r\n xmm2/m128/m32bcst the result in xmm1 subject to writemask k1.\r\n EVEX.256.66.0F.W1 51 /r FV V/V AVX512VL Computes Square Roots of the packed double-precision\r\n VSQRTPD ymm1 {k1}{z}, AVX512F floating-point values in ymm2/m256/m64bcst and stores\r\n ymm2/m256/m32bcst the result in ymm1 subject to writemask k1.\r\n EVEX.512.66.0F.W1 51 /r FV V/V AVX512F Computes Square Roots of the packed double-precision\r\n VSQRTPD zmm1 {k1}{z}, floating-point values in zmm2/m512/m64bcst and stores\r\n zmm2/m512/m64bcst{er} the result in zmm1 subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nPerforms a SIMD computation of the square roots of the two, four or eight packed double-precision floating-point\r\nvalues in the source operand (the second operand) stores the packed double-precision floating-point results in the\r\ndestination operand (the first operand).\r\nEVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or\r\na 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a\r\nZMM/YMM/XMM register updated according to the writemask.\r\nVEX.256 encoded version: The source operand is a YMM register or a 256-bit memory location. The destination\r\noperand is a YMM register. The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination are\r\nzeroed.\r\nVEX.128 encoded version: the source operand second source operand or a 128-bit memory location. The destina-\r\ntion operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are\r\nzeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or 128-bit memory location. The destina-\r\ntion is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding ZMM\r\nregister destination are unmodified.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVSQRTPD (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1) AND (SRC *is register*)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC *is memory*)\r\n THEN DEST[i+63:i] <- SQRT(SRC[63:0])\r\n ELSE DEST[i+63:i] <- SQRT(SRC[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVSQRTPD (VEX.256 encoded version)\r\nDEST[63:0] <-SQRT(SRC[63:0])\r\nDEST[127:64] <-SQRT(SRC[127:64])\r\nDEST[191:128] <-SQRT(SRC[191:128])\r\nDEST[255:192] <-SQRT(SRC[255:192])\r\nDEST[MAX_VL-1:256] <- 0\r\n.\r\nVSQRTPD (VEX.128 encoded version)\r\nDEST[63:0] <-SQRT(SRC[63:0])\r\nDEST[127:64] <-SQRT(SRC[127:64])\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nSQRTPD (128-bit Legacy SSE version)\r\nDEST[63:0] <-SQRT(SRC[63:0])\r\nDEST[127:64] <-SQRT(SRC[127:64])\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVSQRTPD __m512d _mm512_sqrt_round_pd(__m512d a, int r);\r\nVSQRTPD __m512d _mm512_mask_sqrt_round_pd(__m512d s, __mmask8 k, __m512d a, int r);\r\nVSQRTPD __m512d _mm512_maskz_sqrt_round_pd( __mmask8 k, __m512d a, int r);\r\nVSQRTPD __m256d _mm256_sqrt_pd (__m256d a);\r\nVSQRTPD __m256d _mm256_mask_sqrt_pd(__m256d s, __mmask8 k, __m256d a, int r);\r\nVSQRTPD __m256d _mm256_maskz_sqrt_pd( __mmask8 k, __m256d a, int r);\r\nSQRTPD __m128d _mm_sqrt_pd (__m128d a);\r\nVSQRTPD __m128d _mm_mask_sqrt_pd(__m128d s, __mmask8 k, __m128d a, int r);\r\nVSQRTPD __m128d _mm_maskz_sqrt_pd( __mmask8 k, __m128d a, int r);\r\n\r\n\r\n\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 2; additionally\r\n#UD If VEX.vvvv != 1111B.\r\nEVEX-encoded instruction, see Exceptions Type E2.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SQRTPD"
},
{
"description": "SQRTPS-Square Root of Single-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 0F 51 /r RM V/V SSE Computes Square Roots of the packed single-precision\r\n SQRTPS xmm1, xmm2/m128 floating-point values in xmm2/m128 and stores the result in\r\n xmm1.\r\n VEX.128.0F.WIG 51 /r RM V/V AVX Computes Square Roots of the packed single-precision\r\n VSQRTPS xmm1, xmm2/m128 floating-point values in xmm2/m128 and stores the result in\r\n xmm1.\r\n VEX.256.0F.WIG 51/r RM V/V AVX Computes Square Roots of the packed single-precision\r\n VSQRTPS ymm1, ymm2/m256 floating-point values in ymm2/m256 and stores the result in\r\n ymm1.\r\n EVEX.128.0F.W0 51 /r FV V/V AVX512VL Computes Square Roots of the packed single-precision\r\n VSQRTPS xmm1 {k1}{z}, AVX512F floating-point values in xmm2/m128/m32bcst and stores\r\n xmm2/m128/m32bcst the result in xmm1 subject to writemask k1.\r\n EVEX.256.0F.W0 51 /r FV V/V AVX512VL Computes Square Roots of the packed single-precision\r\n VSQRTPS ymm1 {k1}{z}, AVX512F floating-point values in ymm2/m256/m32bcst and stores\r\n ymm2/m256/m32bcst the result in ymm1 subject to writemask k1.\r\n EVEX.512.0F.W0 51/r FV V/V AVX512F Computes Square Roots of the packed single-precision\r\n VSQRTPS zmm1 {k1}{z}, floating-point values in zmm2/m512/m32bcst and stores\r\n zmm2/m512/m32bcst{er} the result in zmm1 subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nPerforms a SIMD computation of the square roots of the four, eight or sixteen packed single-precision floating-point\r\nvalues in the source operand (second operand) stores the packed single-precision floating-point results in the\r\ndestination operand.\r\nEVEX.512 encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location\r\nor a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a\r\nZMM/YMM/XMM register updated according to the writemask.\r\nVEX.256 encoded version: The source operand is a YMM register or a 256-bit memory location. The destination\r\noperand is a YMM register. The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination are\r\nzeroed.\r\nVEX.128 encoded version: the source operand second source operand or a 128-bit memory location. The destina-\r\ntion operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are\r\nzeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or 128-bit memory location. The destina-\r\ntion is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding ZMM\r\nregister destination are unmodified.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVSQRTPS (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1) AND (SRC *is register*)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC *is memory*)\r\n THEN DEST[i+31:i] <- SQRT(SRC[31:0])\r\n ELSE DEST[i+31:i] <- SQRT(SRC[i+31:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVSQRTPS (VEX.256 encoded version)\r\nDEST[31:0] <-SQRT(SRC[31:0])\r\nDEST[63:32] <-SQRT(SRC[63:32])\r\nDEST[95:64] <-SQRT(SRC[95:64])\r\nDEST[127:96] <-SQRT(SRC[127:96])\r\nDEST[159:128] <-SQRT(SRC[159:128])\r\nDEST[191:160] <-SQRT(SRC[191:160])\r\nDEST[223:192] <-SQRT(SRC[223:192])\r\nDEST[255:224] <-SQRT(SRC[255:224])\r\n\r\nVSQRTPS (VEX.128 encoded version)\r\nDEST[31:0] <-SQRT(SRC[31:0])\r\nDEST[63:32] <-SQRT(SRC[63:32])\r\nDEST[95:64] <-SQRT(SRC[95:64])\r\nDEST[127:96] <-SQRT(SRC[127:96])\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nSQRTPS (128-bit Legacy SSE version)\r\nDEST[31:0] <-SQRT(SRC[31:0])\r\nDEST[63:32] <-SQRT(SRC[63:32])\r\nDEST[95:64] <-SQRT(SRC[95:64])\r\nDEST[127:96] <-SQRT(SRC[127:96])\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVSQRTPS __m512 _mm512_sqrt_round_ps(__m512 a, int r);\r\nVSQRTPS __m512 _mm512_mask_sqrt_round_ps(__m512 s, __mmask16 k, __m512 a, int r);\r\nVSQRTPS __m512 _mm512_maskz_sqrt_round_ps( __mmask16 k, __m512 a, int r);\r\nVSQRTPS __m256 _mm256_sqrt_ps (__m256 a);\r\nVSQRTPS __m256 _mm256_mask_sqrt_ps(__m256 s, __mmask8 k, __m256 a, int r);\r\nVSQRTPS __m256 _mm256_maskz_sqrt_ps( __mmask8 k, __m256 a, int r);\r\nSQRTPS __m128 _mm_sqrt_ps (__m128 a);\r\nVSQRTPS __m128 _mm_mask_sqrt_ps(__m128 s, __mmask8 k, __m128 a, int r);\r\nVSQRTPS __m128 _mm_maskz_sqrt_ps( __mmask8 k, __m128 a, int r);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 2; additionally\r\n#UD If VEX.vvvv != 1111B.\r\nEVEX-encoded instruction, see Exceptions Type E2.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SQRTPS"
},
{
"description": "SQRTSD-Compute Square Root of Scalar Double-Precision Floating-Point Value\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n F2 0F 51/r RM V/V SSE2 Computes square root of the low double-precision floating-\r\n SQRTSD xmm1,xmm2/m64 point value in xmm2/m64 and stores the results in xmm1.\r\n VEX.NDS.128.F2.0F.WIG 51/r RVM V/V AVX Computes square root of the low double-precision floating-\r\n VSQRTSD xmm1,xmm2, point value in xmm3/m64 and stores the results in xmm1.\r\n xmm3/m64 Also, upper double-precision floating-point value\r\n (bits[127:64]) from xmm2 is copied to xmm1[127:64].\r\n EVEX.NDS.LIG.F2.0F.W1 51/r T1S V/V AVX512F Computes square root of the low double-precision floating-\r\n VSQRTSD xmm1 {k1}{z}, xmm2, point value in xmm3/m64 and stores the results in xmm1\r\n xmm3/m64{er} under writemask k1. Also, upper double-precision floating-\r\n point value (bits[127:64]) from xmm2 is copied to\r\n xmm1[127:64].\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n T1S ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nComputes the square root of the low double-precision floating-point value in the second source operand and stores\r\nthe double-precision floating-point result in the destination operand. The second source operand can be an XMM\r\nregister or a 64-bit memory location. The first source and destination operands are XMM registers.\r\n128-bit Legacy SSE version: The first source operand and the destination operand are the same. The quadword at\r\nbits 127:64 of the destination operand remains unchanged. Bits (MAX_VL-1:64) of the corresponding destination\r\nregister remain unchanged.\r\nVEX.128 and EVEX encoded versions: Bits 127:64 of the destination operand are copied from the corresponding\r\nbits of the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.\r\nEVEX encoded version: The low quadword element of the destination operand is updated according to the\r\nwritemask.\r\nSoftware should ensure VSQRTSD is encoded with VEX.L=0. Encoding VSQRTSD with VEX.L=1 may encounter\r\nunpredictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVSQRTSD (EVEX encoded version)\r\nIF (EVEX.b = 1) AND (SRC2 *is register*)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[63:0] <- SQRT(SRC2[63:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[63:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVSQRTSD (VEX.128 encoded version)\r\nDEST[63:0] <-SQRT(SRC2[63:0])\r\nDEST[127:64] <-SRC1[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nSQRTSD (128-bit Legacy SSE version)\r\nDEST[63:0] <-SQRT(SRC[63:0])\r\nDEST[MAX_VL-1:64] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVSQRTSD __m128d _mm_sqrt_round_sd(__m128d a, __m128d b, int r);\r\nVSQRTSD __m128d _mm_mask_sqrt_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int r);\r\nVSQRTSD __m128d _mm_maskz_sqrt_round_sd(__mmask8 k, __m128d a, __m128d b, int r);\r\nSQRTSD __m128d _mm_sqrt_sd (__m128d a, __m128d b)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 3.\r\nEVEX-encoded instruction, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SQRTSD"
},
{
"description": "SQRTSS-Compute Square Root of Scalar Single-Precision Value\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n F3 0F 51 /r RM V/V SSE Computes square root of the low single-precision floating-point\r\n SQRTSS xmm1, xmm2/m32 value in xmm2/m32 and stores the results in xmm1.\r\n VEX.NDS.128.F3.0F.WIG 51 /r RVM V/V AVX Computes square root of the low single-precision floating-point\r\n VSQRTSS xmm1, xmm2, value in xmm3/m32 and stores the results in xmm1. Also,\r\n xmm3/m32 upper single-precision floating-point values (bits[127:32]) from\r\n xmm2 are copied to xmm1[127:32].\r\n EVEX.NDS.LIG.F3.0F.W0 51 /r T1S V/V AVX512F Computes square root of the low single-precision floating-point\r\n VSQRTSS xmm1 {k1}{z}, xmm2, value in xmm3/m32 and stores the results in xmm1 under\r\n xmm3/m32{er} writemask k1. Also, upper single-precision floating-point values\r\n (bits[127:32]) from xmm2 are copied to xmm1[127:32].\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n T1S ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nComputes the square root of the low single-precision floating-point value in the second source operand and stores\r\nthe single-precision floating-point result in the destination operand. The second source operand can be an XMM\r\nregister or a 32-bit memory location. The first source and destination operands is an XMM register.\r\n128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAX_VL-\r\n1:32) of the corresponding YMM destination register remain unchanged.\r\nVEX.128 and EVEX encoded versions: Bits 127:32 of the destination operand are copied from the corresponding\r\nbits of the first source operand. Bits (MAX_VL-1:128) of the destination ZMM register are zeroed.\r\nEVEX encoded version: The low doubleword element of the destination operand is updated according to the\r\nwritemask.\r\nSoftware should ensure VSQRTSS is encoded with VEX.L=0. Encoding VSQRTSS with VEX.L=1 may encounter\r\nunpredictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVSQRTSS (EVEX encoded version)\r\nIF (EVEX.b = 1) AND (SRC2 *is register*)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[31:0] <- SQRT(SRC2[31:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[31:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:31] <- SRC1[127:31]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVSQRTSS (VEX.128 encoded version)\r\nDEST[31:0] <-SQRT(SRC2[31:0])\r\nDEST[127:32] <-SRC1[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nSQRTSS (128-bit Legacy SSE version)\r\nDEST[31:0] <-SQRT(SRC2[31:0])\r\nDEST[MAX_VL-1:32] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVSQRTSS __m128 _mm_sqrt_round_ss(__m128 a, __m128 b, int r);\r\nVSQRTSS __m128 _mm_mask_sqrt_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int r);\r\nVSQRTSS __m128 _mm_maskz_sqrt_round_ss( __mmask8 k, __m128 a, __m128 b, int r);\r\nSQRTSS __m128 _mm_sqrt_ss(__m128 a)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 3.\r\nEVEX-encoded instruction, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SQRTSS"
},
{
"description": "STAC-Set AC Flag in EFLAGS Register\r\n Opcode/ Op / 64/32 bit CPUID Description\r\n Instruction En Mode Feature\r\n Support Flag\r\n 0F 01 CB NP V/V SMAP Set the AC flag in the EFLAGS register.\r\n STAC\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nSets the AC flag bit in EFLAGS register. This may enable alignment checking of user-mode data accesses. This\r\nallows explicit supervisor-mode data accesses to user-mode pages even if the SMAP bit is set in the CR4 register.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode. Attempts to execute STAC when\r\nCPL > 0 cause #UD.\r\n\r\nOperation\r\n\r\nEFLAGS.AC <- 1;\r\n\r\nFlags Affected\r\nAC set. Other flags are unaffected.\r\n\r\nProtected Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If the CPL > 0.\r\n If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.\r\n\r\nReal-Address Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD The STAC instruction is not recognized in virtual-8086 mode.\r\n\r\nCompatibility Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If the CPL > 0.\r\n If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.\r\n\r\n64-Bit Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If the CPL > 0.\r\n If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.\r\n\r\n\r\n\r\n\r\n",
"mnem": "STAC"
},
{
"description": "STC-Set Carry Flag\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n F9 STC NP Valid Valid Set CF flag.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nSets the CF flag in the EFLAGS register. Operation is the same in all modes.\r\n\r\nOperation\r\nCF <- 1;\r\n\r\nFlags Affected\r\nThe CF flag is set. The OF, ZF, SF, AF, and PF flags are unaffected.\r\n\r\nExceptions (All Operating Modes)\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "STC"
},
{
"description": "STD-Set Direction Flag\r\nOpcode Instruction Op/ 64-bit Compat/ Description\r\n En Mode Leg Mode\r\nFD STD NP Valid Valid Set DF flag.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nSets the DF flag in the EFLAGS register. When the DF flag is set to 1, string operations decrement the index regis-\r\nters (ESI and/or EDI). Operation is the same in all modes.\r\n\r\nOperation\r\nDF <- 1;\r\n\r\nFlags Affected\r\nThe DF flag is set. The CF, OF, ZF, SF, AF, and PF flags are unaffected.\r\n\r\nExceptions (All Operating Modes)\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "STD"
},
{
"description": "STI-Set Interrupt Flag\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n FB STI NP Valid Valid Set interrupt flag; external, maskable\r\n interrupts enabled at the end of the next\r\n instruction.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nIf protected-mode virtual interrupts are not enabled, STI sets the interrupt flag (IF) in the EFLAGS register. After\r\nthe IF flag is set, the processor begins responding to external, maskable interrupts after the next instruction is\r\nexecuted. The delayed effect of this instruction is provided to allow interrupts to be enabled just before returning\r\nfrom a procedure (or subroutine). For instance, if an STI instruction is followed by an RET instruction, the RET\r\ninstruction is allowed to execute before external interrupts are recognized1. If the STI instruction is followed by a\r\nCLI instruction (which clears the IF flag), the effect of the STI instruction is negated.\r\nThe IF flag and the STI and CLI instructions do not prohibit the generation of exceptions and NMI interrupts. NMI\r\ninterrupts (and SMIs) may be blocked for one macroinstruction following an STI.\r\nWhen protected-mode virtual interrupts are enabled, CPL is 3, and IOPL is less than 3; STI sets the VIF flag in the\r\nEFLAGS register, leaving IF unaffected.\r\nTable 4-19 indicates the action of the STI instruction depending on the processor's mode of operation and the\r\nCPL/IOPL settings of the running program or procedure.\r\nOperation is the same in all modes.\r\n\r\n Table 4-19. Decision Table for STI Results\r\n CR0.PE EFLAGS.VM EFLAGS.IOPL CS.CPL CR4.PVI EFLAGS.VIP CR4.VME STI Result\r\n 0 X X X X X X IF = 1\r\n 1 0 >= CPL X X X X IF = 1\r\n 1 0 < CPL 3 1 X X VIF = 1\r\n 1 0 < CPL <3 X X X GP Fault\r\n 1 0 < CPL X 0 X X GP Fault\r\n 1 0 < CPL X X 1 X GP Fault\r\n 1 1 3 X X X X IF = 1\r\n 1 1 <3 X X 0 1 VIF = 1\r\n 1 1 <3 X X 1 X GP Fault\r\n 1 1 <3 X X X 0 GP Fault\r\n NOTES:\r\n X = This setting has no impact.\r\n\r\n\r\n1. The STI instruction delays recognition of interrupts only if it is executed with EFLAGS.IF = 0. In a sequence of STI instructions, only\r\n the first instruction in the sequence is guaranteed to delay interrupts.\r\n In the following instruction sequence, interrupts may be recognized before RET executes:\r\n STI\r\n STI\r\n RET\r\n\r\n\r\n\r\n\r\nOperation\r\nIF PE = 0 (* Executing in real-address mode *)\r\n THEN\r\n IF <- 1; (* Set Interrupt Flag *)\r\n ELSE (* Executing in protected mode or virtual-8086 mode *)\r\n IF VM = 0 (* Executing in protected mode*)\r\n THEN\r\n IF IOPL >= CPL\r\n THEN\r\n IF <- 1; (* Set Interrupt Flag *)\r\n ELSE\r\n IF (IOPL < CPL) and (CPL = 3) and (PVI = 1)\r\n THEN\r\n VIF <- 1; (* Set Virtual Interrupt Flag *)\r\n ELSE\r\n #GP(0);\r\n FI;\r\n FI;\r\n ELSE (* Executing in Virtual-8086 mode *)\r\n IF IOPL = 3\r\n THEN\r\n IF <- 1; (* Set Interrupt Flag *)\r\n ELSE\r\n IF ((IOPL < 3) and (VIP = 0) and (VME = 1))\r\n THEN\r\n VIF <- 1; (* Set Virtual Interrupt Flag *)\r\n ELSE\r\n #GP(0); (* Trap to virtual-8086 monitor *)\r\n FI;)\r\n FI;\r\n FI;\r\nFI;\r\n\r\nFlags Affected\r\nThe IF flag is set to 1; or the VIF flag is set to 1. Other flags are unaffected.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the CPL is greater (has less privilege) than the IOPL of the current program or procedure.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n",
"mnem": "STI"
},
{
"description": "STMXCSR-Store MXCSR Register State\r\n Opcode*/ Op/ 64/32 bit CPUID Description\r\n Instruction En Mode Feature\r\n Support Flag\r\n 0F AE /3 M V/V SSE Store contents of MXCSR register to m32.\r\n STMXCSR m32\r\n VEX.LZ.0F.WIG AE /3 M V/V AVX Store contents of MXCSR register to m32.\r\n VSTMXCSR m32\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (w) NA NA NA\r\n\r\n\r\nDescription\r\nStores the contents of the MXCSR control and status register to the destination operand. The destination operand\r\nis a 32-bit memory location. The reserved bits in the MXCSR register are stored as 0s.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\nVEX.L must be 0, otherwise instructions will #UD.\r\nNote: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\nOperation\r\nm32 <- MXCSR;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n_mm_getcsr(void)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 5; additionally\r\n#UD If VEX.L= 1,\r\n If VEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "STMXCSR"
},
{
"description": "STOS/STOSB/STOSW/STOSD/STOSQ-Store String\r\nOpcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\nAA STOS m8 NA Valid Valid For legacy mode, store AL at address ES:(E)DI;\r\n For 64-bit mode store AL at address RDI or\r\n EDI.\r\nAB STOS m16 NA Valid Valid For legacy mode, store AX at address ES:(E)DI;\r\n For 64-bit mode store AX at address RDI or\r\n EDI.\r\nAB STOS m32 NA Valid Valid For legacy mode, store EAX at address\r\n ES:(E)DI; For 64-bit mode store EAX at address\r\n RDI or EDI.\r\nREX.W + AB STOS m64 NA Valid N.E. Store RAX at address RDI or EDI.\r\nAA STOSB NA Valid Valid For legacy mode, store AL at address ES:(E)DI;\r\n For 64-bit mode store AL at address RDI or\r\n EDI.\r\nAB STOSW NA Valid Valid For legacy mode, store AX at address ES:(E)DI;\r\n For 64-bit mode store AX at address RDI or\r\n EDI.\r\nAB STOSD NA Valid Valid For legacy mode, store EAX at address\r\n ES:(E)DI; For 64-bit mode store EAX at address\r\n RDI or EDI.\r\nREX.W + AB STOSQ NA Valid N.E. Store RAX at address RDI or EDI.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NA NA NA NA NA\r\n\r\n\r\nDescription\r\nIn non-64-bit and default 64-bit mode; stores a byte, word, or doubleword from the AL, AX, or EAX register\r\n(respectively) into the destination operand. The destination operand is a memory location, the address of which is\r\nread from either the ES:EDI or ES:DI register (depending on the address-size attribute of the instruction and the\r\nmode of operation). The ES segment cannot be overridden with a segment override prefix.\r\nAt the assembly-code level, two forms of the instruction are allowed: the \"explicit-operands\" form and the \"no-\r\noperands\" form. The explicit-operands form (specified with the STOS mnemonic) allows the destination operand to\r\nbe specified explicitly. Here, the destination operand should be a symbol that indicates the size and location of the\r\ndestination value. The source operand is then automatically selected to match the size of the destination operand\r\n(the AL register for byte operands, AX for word operands, EAX for doubleword operands). The explicit-operands\r\nform is provided to allow documentation; however, note that the documentation provided by this form can be\r\nmisleading. That is, the destination operand symbol must specify the correct type (size) of the operand (byte,\r\nword, or doubleword), but it does not have to specify the correct location. The location is always specified by the\r\nES:(E)DI register. These must be loaded correctly before the store string instruction is executed.\r\nThe no-operands form provides \"short forms\" of the byte, word, doubleword, and quadword versions of the STOS\r\ninstructions. Here also ES:(E)DI is assumed to be the destination operand and AL, AX, or EAX is assumed to be the\r\nsource operand. The size of the destination and source operands is selected by the mnemonic: STOSB (byte read\r\nfrom register AL), STOSW (word from AX), STOSD (doubleword from EAX).\r\nAfter the byte, word, or doubleword is transferred from the register to the memory location, the (E)DI register is\r\nincremented or decremented according to the setting of the DF flag in the EFLAGS register. If the DF flag is 0, the\r\nregister is incremented; if the DF flag is 1, the register is decremented (the register is incremented or decremented\r\nby 1 for byte operations, by 2 for word operations, by 4 for doubleword operations).\r\n\r\n\r\n\r\n\r\nNOTE: To improve performance, more recent processors support modifications to the processor's operation during\r\nthe string store operations initiated with STOS and STOSB. See Section 7.3.9.3 in the Intel 64 and IA-32 Archi-\r\ntectures Software Developer's Manual, Volume 1 for additional information on fast-string operation.\r\nIn 64-bit mode, the default address size is 64 bits, 32-bit address size is supported using the prefix 67H. Using a\r\nREX prefix in the form of REX.W promotes operation on doubleword operand to 64 bits. The promoted no-operand\r\nmnemonic is STOSQ. STOSQ (and its explicit operands variant) store a quadword from the RAX register into the\r\ndestination addressed by RDI or EDI. See the summary chart at the beginning of this section for encoding data and\r\nlimits.\r\nThe STOS, STOSB, STOSW, STOSD, STOSQ instructions can be preceded by the REP prefix for block loads of ECX\r\nbytes, words, or doublewords. More often, however, these instructions are used within a LOOP construct because\r\ndata needs to be moved into the AL, AX, or EAX register before it can be stored. See \"REP/REPE/REPZ\r\n/REPNE/REPNZ-Repeat String Operation Prefix\" in this chapter for a description of the REP prefix.\r\n\r\nOperation\r\nNon-64-bit Mode:\r\n\r\nIF (Byte store)\r\n THEN\r\n DEST <- AL;\r\n THEN IF DF = 0\r\n THEN (E)DI <- (E)DI + 1;\r\n ELSE (E)DI <- (E)DI - 1;\r\n FI;\r\n ELSE IF (Word store)\r\n THEN\r\n DEST <- AX;\r\n THEN IF DF = 0\r\n THEN (E)DI <- (E)DI + 2;\r\n ELSE (E)DI <- (E)DI - 2;\r\n FI;\r\n FI;\r\n ELSE IF (Doubleword store)\r\n THEN\r\n DEST <- EAX;\r\n THEN IF DF = 0\r\n THEN (E)DI <- (E)DI + 4;\r\n ELSE (E)DI <- (E)DI - 4;\r\n FI;\r\n FI;\r\nFI;\r\n\r\n64-bit Mode:\r\n\r\nIF (Byte store)\r\n THEN\r\n DEST <- AL;\r\n THEN IF DF = 0\r\n THEN (R|E)DI <- (R|E)DI + 1;\r\n ELSE (R|E)DI <- (R|E)DI - 1;\r\n FI;\r\n ELSE IF (Word store)\r\n THEN\r\n DEST <- AX;\r\n\r\n\r\n\r\n THEN IF DF = 0\r\n THEN (R|E)DI <- (R|E)DI + 2;\r\n ELSE (R|E)DI <- (R|E)DI - 2;\r\n FI;\r\n FI;\r\n ELSE IF (Doubleword store)\r\n THEN\r\n DEST <- EAX;\r\n THEN IF DF = 0\r\n THEN (R|E)DI <- (R|E)DI + 4;\r\n ELSE (R|E)DI <- (R|E)DI - 4;\r\n FI;\r\n FI;\r\n ELSE IF (Quadword store using REX.W )\r\n THEN\r\n DEST <- RAX;\r\n THEN IF DF = 0\r\n THEN (R|E)DI <- (R|E)DI + 8;\r\n ELSE (R|E)DI <- (R|E)DI - 8;\r\n FI;\r\n FI;\r\nFI;\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination is located in a non-writable segment.\r\n If a memory operand effective address is outside the limit of the ES segment.\r\n If the ES register contains a NULL segment selector.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the ES segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the ES segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the memory address is in a non-canonical form.\r\n\r\n\r\n\r\n\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "STOS"
},
{
"description": "-R:STOS",
"mnem": "STOSB"
},
{
"description": "-R:STOS",
"mnem": "STOSD"
},
{
"description": "-R:STOS",
"mnem": "STOSQ"
},
{
"description": "-R:STOS",
"mnem": "STOSW"
},
{
"description": "STR-Store Task Register\r\nOpcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n0F 00 /1 STR r/m16 M Valid Valid Stores segment selector from TR in r/m16.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (w) NA NA NA\r\n\r\n\r\nDescription\r\nStores the segment selector from the task register (TR) in the destination operand. The destination operand can be\r\na general-purpose register or a memory location. The segment selector stored with this instruction points to the\r\ntask state segment (TSS) for the currently running task.\r\nWhen the destination operand is a 32-bit register, the 16-bit segment selector is copied into the lower 16 bits of the\r\nregister and the upper 16 bits of the register are cleared. When the destination operand is a memory location, the\r\nsegment selector is written to memory as a 16-bit quantity, regardless of operand size.\r\nIn 64-bit mode, operation is the same. The size of the memory operand is fixed at 16 bits. In register stores, the 2-\r\nbyte TR is zero extended if stored to a 64-bit register.\r\nThe STR instruction is useful only in operating-system software. It can only be executed in protected mode.\r\n\r\nOperation\r\nDEST <- TR(SegmentSelector);\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination is a memory operand that is located in a non-writable segment or if the\r\n effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n If CR4.UMIP = 1 and CPL > 0.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD The STR instruction is not recognized in real-address mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD The STR instruction is not recognized in virtual-8086 mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the memory address is in a non-canonical form.\r\n If CR4.UMIP = 1 and CPL > 0.\r\n#SS(0) If the stack address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "STR"
},
{
"description": "SUB-Subtract\r\nOpcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n2C ib SUB AL, imm8 I Valid Valid Subtract imm8 from AL.\r\n2D iw SUB AX, imm16 I Valid Valid Subtract imm16 from AX.\r\n2D id SUB EAX, imm32 I Valid Valid Subtract imm32 from EAX.\r\nREX.W + 2D id SUB RAX, imm32 I Valid N.E. Subtract imm32 sign-extended to 64-bits\r\n from RAX.\r\n80 /5 ib SUB r/m8, imm8 MI Valid Valid Subtract imm8 from r/m8.\r\nREX + 80 /5 ib SUB r/m8*, imm8 MI Valid N.E. Subtract imm8 from r/m8.\r\n81 /5 iw SUB r/m16, imm16 MI Valid Valid Subtract imm16 from r/m16.\r\n81 /5 id SUB r/m32, imm32 MI Valid Valid Subtract imm32 from r/m32.\r\nREX.W + 81 /5 id SUB r/m64, imm32 MI Valid N.E. Subtract imm32 sign-extended to 64-bits\r\n from r/m64.\r\n83 /5 ib SUB r/m16, imm8 MI Valid Valid Subtract sign-extended imm8 from r/m16.\r\n83 /5 ib SUB r/m32, imm8 MI Valid Valid Subtract sign-extended imm8 from r/m32.\r\nREX.W + 83 /5 ib SUB r/m64, imm8 MI Valid N.E. Subtract sign-extended imm8 from r/m64.\r\n28 /r SUB r/m8, r8 MR Valid Valid Subtract r8 from r/m8.\r\nREX + 28 /r SUB r/m8*, r8* MR Valid N.E. Subtract r8 from r/m8.\r\n29 /r SUB r/m16, r16 MR Valid Valid Subtract r16 from r/m16.\r\n29 /r SUB r/m32, r32 MR Valid Valid Subtract r32 from r/m32.\r\nREX.W + 29 /r SUB r/m64, r64 MR Valid N.E. Subtract r64 from r/m64.\r\n2A /r SUB r8, r/m8 RM Valid Valid Subtract r/m8 from r8.\r\nREX + 2A /r SUB r8*, r/m8* RM Valid N.E. Subtract r/m8 from r8.\r\n2B /r SUB r16, r/m16 RM Valid Valid Subtract r/m16 from r16.\r\n2B /r SUB r32, r/m32 RM Valid Valid Subtract r/m32 from r32.\r\nREX.W + 2B /r SUB r64, r/m64 RM Valid N.E. Subtract r/m64 from r64.\r\nNOTES:\r\n* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n I AL/AX/EAX/RAX imm8/26/32 NA NA\r\n MI ModRM:r/m (r, w) imm8/26/32 NA NA\r\n MR ModRM:r/m (r, w) ModRM:reg (r) NA NA\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n\r\n\r\nDescription\r\nSubtracts the second operand (source operand) from the first operand (destination operand) and stores the result\r\nin the destination operand. The destination operand can be a register or a memory location; the source operand\r\ncan be an immediate, register, or memory location. (However, two memory operands cannot be used in one\r\ninstruction.) When an immediate value is used as an operand, it is sign-extended to the length of the destination\r\noperand format.\r\n\r\n\r\n\r\n\r\n\r\nThe SUB instruction performs integer subtraction. It evaluates the result for both signed and unsigned integer\r\noperands and sets the OF and CF flags to indicate an overflow in the signed or unsigned result, respectively. The SF\r\nflag indicates the sign of the signed result.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\nThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.\r\n\r\nOperation\r\nDEST <- (DEST - SRC);\r\n\r\nFlags Affected\r\nThe OF, SF, ZF, AF, PF, and CF flags are set according to the result.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination is located in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SUB"
},
{
"description": "SUBPD-Subtract Packed Double-Precision Floating-Point Values\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0F 5C /r RM V/V SSE2 Subtract packed double-precision floating-point values\r\n SUBPD xmm1, xmm2/m128 in xmm2/mem from xmm1 and store result in xmm1.\r\n VEX.NDS.128.66.0F.WIG 5C /r RVM V/V AVX Subtract packed double-precision floating-point values\r\n VSUBPD xmm1,xmm2, xmm3/m128 in xmm3/mem from xmm2 and store result in xmm1.\r\n VEX.NDS.256.66.0F.WIG 5C /r RVM V/V AVX Subtract packed double-precision floating-point values\r\n VSUBPD ymm1, ymm2, ymm3/m256 in ymm3/mem from ymm2 and store result in ymm1.\r\n EVEX.NDS.128.66.0F.W1 5C /r FV V/V AVX512VL Subtract packed double-precision floating-point values\r\n VSUBPD xmm1 {k1}{z}, xmm2, AVX512F from xmm3/m128/m64bcst to xmm2 and store result\r\n xmm3/m128/m64bcst in xmm1 with writemask k1.\r\n EVEX.NDS.256.66.0F.W1 5C /r FV V/V AVX512VL Subtract packed double-precision floating-point values\r\n VSUBPD ymm1 {k1}{z}, ymm2, AVX512F from ymm3/m256/m64bcst to ymm2 and store result\r\n ymm3/m256/m64bcst in ymm1 with writemask k1.\r\n EVEX.NDS.512.66.0F.W1 5C /r FV V/V AVX512F Subtract packed double-precision floating-point values\r\n VSUBPD zmm1 {k1}{z}, zmm2, from zmm3/m512/m64bcst to zmm2 and store result in\r\n zmm3/m512/m64bcst{er} zmm1 with writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a SIMD subtract of the two, four or eight packed double-precision floating-point values of the second\r\nSource operand from the first Source operand, and stores the packed double-precision floating-point results in the\r\ndestination operand.\r\nVEX.128 and EVEX.128 encoded versions: The second source operand is an XMM register or an 128-bit memory\r\nlocation. The first source operand and destination operands are XMM registers. Bits (MAX_VL-1:128) of the corre-\r\nsponding destination register are zeroed.\r\nVEX.256 and EVEX.256 encoded versions: The second source operand is an YMM register or an 256-bit memory\r\nlocation. The first source operand and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corre-\r\nsponding destination register are zeroed.\r\nEVEX.512 encoded version: The second source operand is a ZMM register, a 512-bit memory location or a 512-bit\r\nvector broadcasted from a 64-bit memory location. The first source operand and destination operands are ZMM\r\nregisters. The destination operand is conditionally updated according to the writemask.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper Bits (MAX_VL-1:128) of the corresponding\r\nregister destination are unmodified.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVSUBPD (EVEX encoded versions) when src2 operand is a vector register\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- SRC1[i+63:i] - SRC2[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[63:0] <- 0\r\n FI;\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVSUBPD (EVEX encoded versions) when src2 operand is a memory source\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1)\r\n THEN DEST[i+63:i] <- SRC1[i+63:i] - SRC2[63:0];\r\n ELSE EST[i+63:i] <- SRC1[i+63:i] - SRC2[i+63:i];\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[63:0] <- 0\r\n FI;\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVSUBPD (VEX.256 encoded version)\r\nDEST[63:0] <- SRC1[63:0] - SRC2[63:0]\r\nDEST[127:64] <- SRC1[127:64] - SRC2[127:64]\r\nDEST[191:128] <- SRC1[191:128] - SRC2[191:128]\r\nDEST[255:192] <- SRC1[255:192] - SRC2[255:192]\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVSUBPD (VEX.128 encoded version)\r\nDEST[63:0] <- SRC1[63:0] - SRC2[63:0]\r\nDEST[127:64] <- SRC1[127:64] - SRC2[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nSUBPD (128-bit Legacy SSE version)\r\nDEST[63:0] <- DEST[63:0] - SRC[63:0]\r\nDEST[127:64] <- DEST[127:64] - SRC[127:64]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVSUBPD __m512d _mm512_sub_pd (__m512d a, __m512d b);\r\nVSUBPD __m512d _mm512_mask_sub_pd (__m512d s, __mmask8 k, __m512d a, __m512d b);\r\nVSUBPD __m512d _mm512_maskz_sub_pd (__mmask8 k, __m512d a, __m512d b);\r\nVSUBPD __m512d _mm512_sub_round_pd (__m512d a, __m512d b, int);\r\nVSUBPD __m512d _mm512_mask_sub_round_pd (__m512d s, __mmask8 k, __m512d a, __m512d b, int);\r\nVSUBPD __m512d _mm512_maskz_sub_round_pd (__mmask8 k, __m512d a, __m512d b, int);\r\nVSUBPD __m256d _mm256_sub_pd (__m256d a, __m256d b);\r\nVSUBPD __m256d _mm256_mask_sub_pd (__m256d s, __mmask8 k, __m256d a, __m256d b);\r\nVSUBPD __m256d _mm256_maskz_sub_pd (__mmask8 k, __m256d a, __m256d b);\r\nSUBPD __m128d _mm_sub_pd (__m128d a, __m128d b);\r\nVSUBPD __m128d _mm_mask_sub_pd (__m128d s, __mmask8 k, __m128d a, __m128d b);\r\nVSUBPD __m128d _mm_maskz_sub_pd (__mmask8 k, __m128d a, __m128d b);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2.\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SUBPD"
},
{
"description": "SUBPS-Subtract Packed Single-Precision Floating-Point Values\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 0F 5C /r RM V/V SSE Subtract packed single-precision floating-point values\r\n SUBPS xmm1, xmm2/m128 in xmm2/mem from xmm1 and store result in xmm1.\r\n VEX.NDS.128.0F.WIG 5C /r RVM V/V AVX Subtract packed single-precision floating-point values\r\n VSUBPS xmm1,xmm2, xmm3/m128 in xmm3/mem from xmm2 and stores result in xmm1.\r\n VEX.NDS.256.0F.WIG 5C /r RVM V/V AVX Subtract packed single-precision floating-point values\r\n VSUBPS ymm1, ymm2, ymm3/m256 in ymm3/mem from ymm2 and stores result in ymm1.\r\n EVEX.NDS.128.0F.W0 5C /r FV V/V AVX512VL Subtract packed single-precision floating-point values\r\n VSUBPS xmm1 {k1}{z}, xmm2, AVX512F from xmm3/m128/m32bcst to xmm2 and stores\r\n xmm3/m128/m32bcst result in xmm1 with writemask k1.\r\n EVEX.NDS.256.0F.W0 5C /r FV V/V AVX512VL Subtract packed single-precision floating-point values\r\n VSUBPS ymm1 {k1}{z}, ymm2, AVX512F from ymm3/m256/m32bcst to ymm2 and stores\r\n ymm3/m256/m32bcst result in ymm1 with writemask k1.\r\n EVEX.NDS.512.0F.W0 5C /r FV V/V AVX512F Subtract packed single-precision floating-point values\r\n VSUBPS zmm1 {k1}{z}, zmm2, in zmm3/m512/m32bcst from zmm2 and stores result\r\n zmm3/m512/m32bcst{er} in zmm1 with writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a SIMD subtract of the packed single-precision floating-point values in the second Source operand from\r\nthe First Source operand, and stores the packed single-precision floating-point results in the destination operand.\r\nVEX.128 and EVEX.128 encoded versions: The second source operand is an XMM register or an 128-bit memory\r\nlocation. The first source operand and destination operands are XMM registers. Bits (MAX_VL-1:128) of the corre-\r\nsponding destination register are zeroed.\r\nVEX.256 and EVEX.256 encoded versions: The second source operand is an YMM register or an 256-bit memory\r\nlocation. The first source operand and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corre-\r\nsponding destination register are zeroed.\r\nEVEX.512 encoded version: The second source operand is a ZMM register, a 512-bit memory location or a 512-bit\r\nvector broadcasted from a 32-bit memory location. The first source operand and destination operands are ZMM\r\nregisters. The destination operand is conditionally updated according to the writemask.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper Bits (MAX_VL-1:128) of the corresponding\r\nregister destination are unmodified.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVSUBPS (EVEX encoded versions) when src2 operand is a vector register\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- SRC1[i+31:i] - SRC2[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[31:0] <- 0\r\n FI;\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVSUBPS (EVEX encoded versions) when src2 operand is a memory source\r\n(KL, VL) = (4, 128), (8, 256),(16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <-j * 32\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1)\r\n THEN DEST[i+31:i] <- SRC1[i+31:i] - SRC2[31:0];\r\n ELSE DEST[i+31:i] <- SRC1[i+31:i] - SRC2[i+31:i];\r\n FI;\r\n\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[31:0] <- 0\r\n FI;\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVSUBPS (VEX.256 encoded version)\r\nDEST[31:0] <- SRC1[31:0] - SRC2[31:0]\r\nDEST[63:32] <- SRC1[63:32] - SRC2[63:32]\r\nDEST[95:64] <- SRC1[95:64] - SRC2[95:64]\r\nDEST[127:96] <- SRC1[127:96] - SRC2[127:96]\r\nDEST[159:128] <- SRC1[159:128] - SRC2[159:128]\r\nDEST[191:160]<- SRC1[191:160] - SRC2[191:160]\r\nDEST[223:192] <- SRC1[223:192] - SRC2[223:192]\r\nDEST[255:224] <- SRC1[255:224] - SRC2[255:224].\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\n\r\n\r\nVSUBPS (VEX.128 encoded version)\r\nDEST[31:0] <- SRC1[31:0] - SRC2[31:0]\r\nDEST[63:32] <- SRC1[63:32] - SRC2[63:32]\r\nDEST[95:64] <- SRC1[95:64] - SRC2[95:64]\r\nDEST[127:96] <- SRC1[127:96] - SRC2[127:96]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nSUBPS (128-bit Legacy SSE version)\r\nDEST[31:0] <- SRC1[31:0] - SRC2[31:0]\r\nDEST[63:32] <- SRC1[63:32] - SRC2[63:32]\r\nDEST[95:64] <- SRC1[95:64] - SRC2[95:64]\r\nDEST[127:96] <- SRC1[127:96] - SRC2[127:96]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVSUBPS __m512 _mm512_sub_ps (__m512 a, __m512 b);\r\nVSUBPS __m512 _mm512_mask_sub_ps (__m512 s, __mmask16 k, __m512 a, __m512 b);\r\nVSUBPS __m512 _mm512_maskz_sub_ps (__mmask16 k, __m512 a, __m512 b);\r\nVSUBPS __m512 _mm512_sub_round_ps (__m512 a, __m512 b, int);\r\nVSUBPS __m512 _mm512_mask_sub_round_ps (__m512 s, __mmask16 k, __m512 a, __m512 b, int);\r\nVSUBPS __m512 _mm512_maskz_sub_round_ps (__mmask16 k, __m512 a, __m512 b, int);\r\nVSUBPS __m256 _mm256_sub_ps (__m256 a, __m256 b);\r\nVSUBPS __m256 _mm256_mask_sub_ps (__m256 s, __mmask8 k, __m256 a, __m256 b);\r\nVSUBPS __m256 _mm256_maskz_sub_ps (__mmask16 k, __m256 a, __m256 b);\r\nSUBPS __m128 _mm_sub_ps (__m128 a, __m128 b);\r\nVSUBPS __m128 _mm_mask_sub_ps (__m128 s, __mmask8 k, __m128 a, __m128 b);\r\nVSUBPS __m128 _mm_maskz_sub_ps (__mmask16 k, __m128 a, __m128 b);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2.\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SUBPS"
},
{
"description": "SUBSD-Subtract Scalar Double-Precision Floating-Point Value\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n F2 0F 5C /r RM V/V SSE2 Subtract the low double-precision floating-point value in\r\n SUBSD xmm1, xmm2/m64 xmm2/m64 from xmm1 and store the result in xmm1.\r\n VEX.NDS.128.F2.0F.WIG 5C /r RVM V/V AVX Subtract the low double-precision floating-point value in\r\n VSUBSD xmm1,xmm2, xmm3/m64 xmm3/m64 from xmm2 and store the result in xmm1.\r\n EVEX.NDS.LIG.F2.0F.W1 5C /r T1S V/V AVX512F Subtract the low double-precision floating-point value in\r\n VSUBSD xmm1 {k1}{z}, xmm2, xmm3/m64 from xmm2 and store the result in xmm1\r\n xmm3/m64{er} under writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n T1S ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nSubtract the low double-precision floating-point value in the second source operand from the first source operand\r\nand stores the double-precision floating-point result in the low quadword of the destination operand.\r\nThe second source operand can be an XMM register or a 64-bit memory location. The first source and destination\r\noperands are XMM registers.\r\n128-bit Legacy SSE version: The destination and first source operand are the same. Bits (MAX_VL-1:64) of the\r\ncorresponding destination register remain unchanged.\r\nVEX.128 and EVEX encoded versions: Bits (127:64) of the XMM register destination are copied from corresponding\r\nbits in the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.\r\nEVEX encoded version: The low quadword element of the destination operand is updated according to the\r\nwritemask.\r\nSoftware should ensure VSUBSD is encoded with VEX.L=0. Encoding VSUBSD with VEX.L=1 may encounter unpre-\r\ndictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVSUBSD (EVEX encoded version)\r\nIF (SRC2 *is register*) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[63:0] <- SRC1[63:0] - SRC2[63:0]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[63:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVSUBSD (VEX.128 encoded version)\r\nDEST[63:0] <-SRC1[63:0] - SRC2[63:0]\r\nDEST[127:64] <-SRC1[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nSUBSD (128-bit Legacy SSE version)\r\nDEST[63:0] <-DEST[63:0] - SRC[63:0]\r\nDEST[MAX_VL-1:64] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVSUBSD __m128d _mm_mask_sub_sd (__m128d s, __mmask8 k, __m128d a, __m128d b);\r\nVSUBSD __m128d _mm_maskz_sub_sd (__mmask8 k, __m128d a, __m128d b);\r\nVSUBSD __m128d _mm_sub_round_sd (__m128d a, __m128d b, int);\r\nVSUBSD __m128d _mm_mask_sub_round_sd (__m128d s, __mmask8 k, __m128d a, __m128d b, int);\r\nVSUBSD __m128d _mm_maskz_sub_round_sd (__mmask8 k, __m128d a, __m128d b, int);\r\nSUBSD __m128d _mm_sub_sd (__m128d a, __m128d b);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3.\r\nEVEX-encoded instructions, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SUBSD"
},
{
"description": "SUBSS-Subtract Scalar Single-Precision Floating-Point Value\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n F3 0F 5C /r RM V/V SSE Subtract the low single-precision floating-point value in\r\n SUBSS xmm1, xmm2/m32 xmm2/m32 from xmm1 and store the result in xmm1.\r\n VEX.NDS.128.F3.0F.WIG 5C /r RVM V/V AVX Subtract the low single-precision floating-point value in\r\n VSUBSS xmm1,xmm2, xmm3/m32 xmm3/m32 from xmm2 and store the result in xmm1.\r\n EVEX.NDS.LIG.F3.0F.W0 5C /r T1S V/V AVX512F Subtract the low single-precision floating-point value in\r\n VSUBSS xmm1 {k1}{z}, xmm2, xmm3/m32 from xmm2 and store the result in xmm1\r\n xmm3/m32{er} under writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n T1S ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nSubtract the low single-precision floating-point value from the second source operand and the first source operand\r\nand store the double-precision floating-point result in the low doubleword of the destination operand.\r\nThe second source operand can be an XMM register or a 32-bit memory location. The first source and destination\r\noperands are XMM registers.\r\n128-bit Legacy SSE version: The destination and first source operand are the same. Bits (MAX_VL-1:32) of the\r\ncorresponding destination register remain unchanged.\r\nVEX.128 and EVEX encoded versions: Bits (127:32) of the XMM register destination are copied from corresponding\r\nbits in the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.\r\nEVEX encoded version: The low doubleword element of the destination operand is updated according to the\r\nwritemask.\r\nSoftware should ensure VSUBSS is encoded with VEX.L=0. Encoding VSUBSD with VEX.L=1 may encounter unpre-\r\ndictable behavior across different processor generations.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVSUBSS (EVEX encoded version)\r\nIF (SRC2 *is register*) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[31:0] <- SRC1[31:0] - SRC2[31:0]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[31:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:32] <- SRC1[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVSUBSS (VEX.128 encoded version)\r\nDEST[31:0] <-SRC1[31:0] - SRC2[31:0]\r\nDEST[127:32] <-SRC1[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nSUBSS (128-bit Legacy SSE version)\r\nDEST[31:0] <-DEST[31:0] - SRC[31:0]\r\nDEST[MAX_VL-1:32] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVSUBSS __m128 _mm_mask_sub_ss (__m128 s, __mmask8 k, __m128 a, __m128 b);\r\nVSUBSS __m128 _mm_maskz_sub_ss (__mmask8 k, __m128 a, __m128 b);\r\nVSUBSS __m128 _mm_sub_round_ss (__m128 a, __m128 b, int);\r\nVSUBSS __m128 _mm_mask_sub_round_ss (__m128 s, __mmask8 k, __m128 a, __m128 b, int);\r\nVSUBSS __m128 _mm_maskz_sub_round_ss (__mmask8 k, __m128 a, __m128 b, int);\r\nSUBSS __m128 _mm_sub_ss (__m128 a, __m128 b);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3.\r\nEVEX-encoded instructions, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SUBSS"
},
{
"description": "SWAPGS-Swap GS Base Register\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F 01 F8 SWAPGS NP Valid Invalid Exchanges the current GS base register value\r\n with the value contained in MSR address\r\n C0000102H.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nSWAPGS exchanges the current GS base register value with the value contained in MSR address C0000102H\r\n(IA32_KERNEL_GS_BASE). The SWAPGS instruction is a privileged instruction intended for use by system soft-\r\nware.\r\nWhen using SYSCALL to implement system calls, there is no kernel stack at the OS entry point. Neither is there a\r\nstraightforward method to obtain a pointer to kernel structures from which the kernel stack pointer could be read.\r\nThus, the kernel cannot save general purpose registers or reference memory.\r\nBy design, SWAPGS does not require any general purpose registers or memory operands. No registers need to be\r\nsaved before using the instruction. SWAPGS exchanges the CPL 0 data pointer from the IA32_KERNEL_GS_BASE\r\nMSR with the GS base register. The kernel can then use the GS prefix on normal memory references to access\r\nkernel data structures. Similarly, when the OS kernel is entered using an interrupt or exception (where the kernel\r\nstack is already set up), SWAPGS can be used to quickly get a pointer to the kernel data structures.\r\nThe IA32_KERNEL_GS_BASE MSR itself is only accessible using RDMSR/WRMSR instructions. Those instructions\r\nare only accessible at privilege level 0. The WRMSR instruction ensures that the IA32_KERNEL_GS_BASE MSR\r\ncontains a canonical address.\r\n\r\nOperation\r\nIF CS.L != 1 (* Not in 64-Bit Mode *)\r\n THEN\r\n #UD; FI;\r\n\r\nIF CPL != 0\r\n THEN #GP(0); FI;\r\n\r\ntmp <- GS.base;\r\nGS.base <- IA32_KERNEL_GS_BASE;\r\nIA32_KERNEL_GS_BASE <- tmp;\r\n\r\nFlags Affected\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#UD If Mode != 64-Bit.\r\n\r\nReal-Address Mode Exceptions\r\n#UD If Mode != 64-Bit.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD If Mode != 64-Bit.\r\n\r\n\r\nCompatibility Mode Exceptions\r\n#UD If Mode != 64-Bit.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If CPL != 0.\r\n If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SWAPGS"
},
{
"description": "SYSCALL-Fast System Call\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F 05 SYSCALL NP Valid Invalid Fast call to privilege level 0 system\r\n procedures.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nSYSCALL invokes an OS system-call handler at privilege level 0. It does so by loading RIP from the IA32_LSTAR\r\nMSR (after saving the address of the instruction following SYSCALL into RCX). (The WRMSR instruction ensures\r\nthat the IA32_LSTAR MSR always contain a canonical address.)\r\nSYSCALL also saves RFLAGS into R11 and then masks RFLAGS using the IA32_FMASK MSR (MSR address\r\nC0000084H); specifically, the processor clears in RFLAGS every bit corresponding to a bit that is set in the\r\nIA32_FMASK MSR.\r\nSYSCALL loads the CS and SS selectors with values derived from bits 47:32 of the IA32_STAR MSR. However, the\r\nCS and SS descriptor caches are not loaded from the descriptors (in GDT or LDT) referenced by those selectors.\r\nInstead, the descriptor caches are loaded with fixed values. See the Operation section for details. It is the respon-\r\nsibility of OS software to ensure that the descriptors (in GDT or LDT) referenced by those selector values corre-\r\nspond to the fixed values loaded into the descriptor caches; the SYSCALL instruction does not ensure this\r\ncorrespondence.\r\nThe SYSCALL instruction does not save the stack pointer (RSP). If the OS system-call handler will change the stack\r\npointer, it is the responsibility of software to save the previous value of the stack pointer. This might be done prior\r\nto executing SYSCALL, with software restoring the stack pointer with the instruction following SYSCALL (which will\r\nbe executed after SYSRET). Alternatively, the OS system-call handler may save the stack pointer and restore it\r\nbefore executing SYSRET.\r\n\r\nOperation\r\nIF (CS.L != 1 ) or (IA32_EFER.LMA != 1) or (IA32_EFER.SCE != 1)\r\n(* Not in 64-Bit Mode or SYSCALL/SYSRET not enabled in IA32_EFER *)\r\n THEN #UD;\r\nFI;\r\n\r\nRCX <- RIP; (* Will contain address of next instruction *)\r\nRIP <- IA32_LSTAR;\r\nR11 <- RFLAGS;\r\nRFLAGS <- RFLAGS AND NOT(IA32_FMASK);\r\n\r\nCS.Selector <- IA32_STAR[47:32] AND FFFCH (* Operating system provides CS; RPL forced to 0 *)\r\n(* Set rest of CS to a fixed value *)\r\nCS.Base <- 0; (* Flat segment *)\r\nCS.Limit <- FFFFFH; (* With 4-KByte granularity, implies a 4-GByte limit *)\r\nCS.Type <- 11; (* Execute/read code, accessed *)\r\nCS.S <- 1;\r\nCS.DPL <- 0;\r\nCS.P <- 1;\r\nCS.L <- 1; (* Entry is to 64-bit mode *)\r\nCS.D <- 0; (* Required if CS.L = 1 *)\r\nCS.G <- 1; (* 4-KByte granularity *)\r\nCPL <- 0;\r\n\r\n\r\n\r\nSS.Selector <- IA32_STAR[47:32] + 8; (* SS just above CS *)\r\n(* Set rest of SS to a fixed value *)\r\nSS.Base <- 0; (* Flat segment *)\r\nSS.Limit <- FFFFFH; (* With 4-KByte granularity, implies a 4-GByte limit *)\r\nSS.Type <- 3; (* Read/write data, accessed *)\r\nSS.S <- 1;\r\nSS.DPL <- 0;\r\nSS.P <- 1;\r\nSS.B <- 1; (* 32-bit stack segment *)\r\nSS.G <- 1; (* 4-KByte granularity *)\r\n\r\nFlags Affected\r\nAll.\r\n\r\nProtected Mode Exceptions\r\n#UD The SYSCALL instruction is not recognized in protected mode.\r\n\r\nReal-Address Mode Exceptions\r\n#UD The SYSCALL instruction is not recognized in real-address mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD The SYSCALL instruction is not recognized in virtual-8086 mode.\r\n\r\nCompatibility Mode Exceptions\r\n#UD The SYSCALL instruction is not recognized in compatibility mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD If IA32_EFER.SCE = 0.\r\n If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SYSCALL"
},
{
"description": "SYSENTER-Fast System Call\r\nOpcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n0F 34 SYSENTER NP Valid Valid Fast call to privilege level 0 system\r\n procedures.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nExecutes a fast call to a level 0 system procedure or routine. SYSENTER is a companion instruction to SYSEXIT. The\r\ninstruction is optimized to provide the maximum performance for system calls from user code running at privilege\r\nlevel 3 to operating system or executive procedures running at privilege level 0.\r\nWhen executed in IA-32e mode, the SYSENTER instruction transitions the logical processor to 64-bit mode; other-\r\nwise, the logical processor remains in protected mode.\r\nPrior to executing the SYSENTER instruction, software must specify the privilege level 0 code segment and code\r\nentry point, and the privilege level 0 stack segment and stack pointer by writing values to the following MSRs:\r\n. IA32_SYSENTER_CS (MSR address 174H) - The lower 16 bits of this MSR are the segment selector for the\r\n privilege level 0 code segment. This value is also used to determine the segment selector of the privilege level\r\n 0 stack segment (see the Operation section). This value cannot indicate a null selector.\r\n. IA32_SYSENTER_EIP (MSR address 176H) - The value of this MSR is loaded into RIP (thus, this value\r\n references the first instruction of the selected operating procedure or routine). In protected mode, only\r\n bits 31:0 are loaded.\r\n. IA32_SYSENTER_ESP (MSR address 175H) - The value of this MSR is loaded into RSP (thus, this value\r\n contains the stack pointer for the privilege level 0 stack). This value cannot represent a non-canonical address.\r\n In protected mode, only bits 31:0 are loaded.\r\nThese MSRs can be read from and written to using RDMSR/WRMSR. The WRMSR instruction ensures that the\r\nIA32_SYSENTER_EIP and IA32_SYSENTER_ESP MSRs always contain canonical addresses.\r\nWhile SYSENTER loads the CS and SS selectors with values derived from the IA32_SYSENTER_CS MSR, the CS and\r\nSS descriptor caches are not loaded from the descriptors (in GDT or LDT) referenced by those selectors. Instead,\r\nthe descriptor caches are loaded with fixed values. See the Operation section for details. It is the responsibility of\r\nOS software to ensure that the descriptors (in GDT or LDT) referenced by those selector values correspond to the\r\nfixed values loaded into the descriptor caches; the SYSENTER instruction does not ensure this correspondence.\r\nThe SYSENTER instruction can be invoked from all operating modes except real-address mode.\r\nThe SYSENTER and SYSEXIT instructions are companion instructions, but they do not constitute a call/return pair.\r\nWhen executing a SYSENTER instruction, the processor does not save state information for the user code (e.g., the\r\ninstruction pointer), and neither the SYSENTER nor the SYSEXIT instruction supports passing parameters on the\r\nstack.\r\nTo use the SYSENTER and SYSEXIT instructions as companion instructions for transitions between privilege level 3\r\ncode and privilege level 0 operating system procedures, the following conventions must be followed:\r\n. The segment descriptors for the privilege level 0 code and stack segments and for the privilege level 3 code and\r\n stack segments must be contiguous in a descriptor table. This convention allows the processor to compute the\r\n segment selectors from the value entered in the SYSENTER_CS_MSR MSR.\r\n. The fast system call \"stub\" routines executed by user code (typically in shared libraries or DLLs) must save the\r\n required return IP and processor state information if a return to the calling procedure is required. Likewise, the\r\n operating system or executive procedures called with SYSENTER instructions must have access to and use this\r\n saved return and state information when returning to the user code.\r\n\r\n\r\n\r\n\r\n\r\nThe SYSENTER and SYSEXIT instructions were introduced into the IA-32 architecture in the Pentium II processor.\r\nThe availability of these instructions on a processor is indicated with the SYSENTER/SYSEXIT present (SEP) feature\r\nflag returned to the EDX register by the CPUID instruction. An operating system that qualifies the SEP flag must\r\nalso qualify the processor family and model to ensure that the SYSENTER/SYSEXIT instructions are actually\r\npresent. For example:\r\n\r\nIF CPUID SEP bit is set\r\n THEN IF (Family = 6) and (Model < 3) and (Stepping < 3)\r\n THEN\r\n SYSENTER/SYSEXIT_Not_Supported; FI;\r\n ELSE\r\n SYSENTER/SYSEXIT_Supported; FI;\r\nFI;\r\nWhen the CPUID instruction is executed on the Pentium Pro processor (model 1), the processor returns a the SEP\r\nflag as set, but does not support the SYSENTER/SYSEXIT instructions.\r\n\r\nOperation\r\nIF CR0.PE = 0 OR IA32_SYSENTER_CS[15:2] = 0 THEN #GP(0); FI;\r\n\r\nRFLAGS.VM <- 0; (* Ensures protected mode execution *)\r\nRFLAGS.IF <- 0; (* Mask interrupts *)\r\nIF in IA-32e mode\r\n THEN\r\n RSP <- IA32_SYSENTER_ESP;\r\n RIP <- IA32_SYSENTER_EIP;\r\nELSE\r\n ESP <- IA32_SYSENTER_ESP[31:0];\r\n EIP <- IA32_SYSENTER_EIP[31:0];\r\nFI;\r\n\r\nCS.Selector <- IA32_SYSENTER_CS[15:0] AND FFFCH;\r\n (* Operating system provides CS; RPL forced to 0 *)\r\n(* Set rest of CS to a fixed value *)\r\nCS.Base <- 0; (* Flat segment *)\r\nCS.Limit <- FFFFFH; (* With 4-KByte granularity, implies a 4-GByte limit *)\r\nCS.Type <- 11; (* Execute/read code, accessed *)\r\nCS.S <- 1;\r\nCS.DPL <- 0;\r\nCS.P <- 1;\r\nIF in IA-32e mode\r\n THEN\r\n CS.L <- 1; (* Entry is to 64-bit mode *)\r\n CS.D <- 0; (* Required if CS.L = 1 *)\r\n ELSE\r\n CS.L <- 0;\r\n CS.D <- 1; (* 32-bit code segment*)\r\nFI;\r\nCS.G <- 1; (* 4-KByte granularity *)\r\nCPL <- 0;\r\n\r\nSS.Selector <- CS.Selector + 8; (* SS just above CS *)\r\n(* Set rest of SS to a fixed value *)\r\nSS.Base <- 0; (* Flat segment *)\r\nSS.Limit <- FFFFFH; (* With 4-KByte granularity, implies a 4-GByte limit *)\r\nSS.Type <- 3; (* Read/write data, accessed *)\r\n\r\n\r\n\r\nSS.S <- 1;\r\nSS.DPL <- 0;\r\nSS.P <- 1;\r\nSS.B <- 1; (* 32-bit stack segment*)\r\nSS.G <- 1; (* 4-KByte granularity *)\r\n\r\nFlags Affected\r\nVM, IF (see Operation above)\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If IA32_SYSENTER_CS[15:2] = 0.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP The SYSENTER instruction is not recognized in real-address mode.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SYSENTER"
},
{
"description": "SYSEXIT-Fast Return from Fast System Call\r\nOpcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n0F 35 SYSEXIT NP Valid Valid Fast return to privilege level 3 user code.\r\nREX.W + 0F 35 SYSEXIT NP Valid Valid Fast return to 64-bit mode privilege level 3\r\n user code.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nExecutes a fast return to privilege level 3 user code. SYSEXIT is a companion instruction to the SYSENTER instruc-\r\ntion. The instruction is optimized to provide the maximum performance for returns from system procedures\r\nexecuting at protections levels 0 to user procedures executing at protection level 3. It must be executed from code\r\nexecuting at privilege level 0.\r\nWith a 64-bit operand size, SYSEXIT remains in 64-bit mode; otherwise, it either enters compatibility mode (if the\r\nlogical processor is in IA-32e mode) or remains in protected mode (if it is not).\r\nPrior to executing SYSEXIT, software must specify the privilege level 3 code segment and code entry point, and the\r\nprivilege level 3 stack segment and stack pointer by writing values into the following MSR and general-purpose\r\nregisters:\r\n. IA32_SYSENTER_CS (MSR address 174H) - Contains a 32-bit value that is used to determine the segment\r\n selectors for the privilege level 3 code and stack segments (see the Operation section)\r\n. RDX - The canonical address in this register is loaded into RIP (thus, this value references the first instruction\r\n to be executed in the user code). If the return is not to 64-bit mode, only bits 31:0 are loaded.\r\n. ECX - The canonical address in this register is loaded into RSP (thus, this value contains the stack pointer for\r\n the privilege level 3 stack). If the return is not to 64-bit mode, only bits 31:0 are loaded.\r\nThe IA32_SYSENTER_CS MSR can be read from and written to using RDMSR and WRMSR.\r\nWhile SYSEXIT loads the CS and SS selectors with values derived from the IA32_SYSENTER_CS MSR, the CS and\r\nSS descriptor caches are not loaded from the descriptors (in GDT or LDT) referenced by those selectors. Instead,\r\nthe descriptor caches are loaded with fixed values. See the Operation section for details. It is the responsibility of\r\nOS software to ensure that the descriptors (in GDT or LDT) referenced by those selector values correspond to the\r\nfixed values loaded into the descriptor caches; the SYSEXIT instruction does not ensure this correspondence.\r\nThe SYSEXIT instruction can be invoked from all operating modes except real-address mode and virtual-8086\r\nmode.\r\nThe SYSENTER and SYSEXIT instructions were introduced into the IA-32 architecture in the Pentium II processor.\r\nThe availability of these instructions on a processor is indicated with the SYSENTER/SYSEXIT present (SEP) feature\r\nflag returned to the EDX register by the CPUID instruction. An operating system that qualifies the SEP flag must\r\nalso qualify the processor family and model to ensure that the SYSENTER/SYSEXIT instructions are actually\r\npresent. For example:\r\n\r\nIF CPUID SEP bit is set\r\n THEN IF (Family = 6) and (Model < 3) and (Stepping < 3)\r\n THEN\r\n SYSENTER/SYSEXIT_Not_Supported; FI;\r\n ELSE\r\n SYSENTER/SYSEXIT_Supported; FI;\r\nFI;\r\nWhen the CPUID instruction is executed on the Pentium Pro processor (model 1), the processor returns a the SEP\r\nflag as set, but does not support the SYSENTER/SYSEXIT instructions.\r\n\r\n\r\n\r\nOperation\r\nIF IA32_SYSENTER_CS[15:2] = 0 OR CR0.PE = 0 OR CPL != 0 THEN #GP(0); FI;\r\n\r\nIF operand size is 64-bit\r\n THEN (* Return to 64-bit mode *)\r\n RSP <- RCX;\r\n RIP <- RDX;\r\n ELSE (* Return to protected mode or compatibility mode *)\r\n RSP <- ECX;\r\n RIP <- EDX;\r\nFI;\r\n\r\nIF operand size is 64-bit (* Operating system provides CS; RPL forced to 3 *)\r\n THEN CS.Selector <- IA32_SYSENTER_CS[15:0] + 32;\r\n ELSE CS.Selector <- IA32_SYSENTER_CS[15:0] + 16;\r\nFI;\r\nCS.Selector <- CS.Selector OR 3; (* RPL forced to 3 *)\r\n(* Set rest of CS to a fixed value *)\r\nCS.Base <- 0; (* Flat segment *)\r\nCS.Limit <- FFFFFH; (* With 4-KByte granularity, implies a 4-GByte limit *)\r\nCS.Type <- 11; (* Execute/read code, accessed *)\r\nCS.S <- 1;\r\nCS.DPL <- 3;\r\nCS.P <- 1;\r\nIF operand size is 64-bit\r\n THEN (* return to 64-bit mode *)\r\n CS.L <- 1; (* 64-bit code segment *)\r\n CS.D <- 0; (* Required if CS.L = 1 *)\r\n ELSE (* return to protected mode or compatibility mode *)\r\n CS.L <- 0;\r\n CS.D <- 1; (* 32-bit code segment*)\r\nFI;\r\nCS.G <- 1; (* 4-KByte granularity *)\r\nCPL <- 3;\r\n\r\nSS.Selector <- CS.Selector + 8; (* SS just above CS *)\r\n(* Set rest of SS to a fixed value *)\r\nSS.Base <- 0; (* Flat segment *)\r\nSS.Limit <- FFFFFH; (* With 4-KByte granularity, implies a 4-GByte limit *)\r\nSS.Type <- 3; (* Read/write data, accessed *)\r\nSS.S <- 1;\r\nSS.DPL <- 3;\r\nSS.P <- 1;\r\nSS.B <- 1; (* 32-bit stack segment*)\r\nSS.G <- 1; (* 4-KByte granularity *)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If IA32_SYSENTER_CS[15:2] = 0.\r\n If CPL != 0.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#GP The SYSEXIT instruction is not recognized in real-address mode.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) The SYSEXIT instruction is not recognized in virtual-8086 mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If IA32_SYSENTER_CS = 0.\r\n If CPL != 0.\r\n If RCX or RDX contains a non-canonical address.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SYSEXIT"
},
{
"description": "SYSRET-Return From Fast System Call\r\nOpcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n0F 07 SYSRET NP Valid Invalid Return to compatibility mode from fast\r\n system call\r\nREX.W + 0F 07 SYSRET NP Valid Invalid Return to 64-bit mode from fast system call\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nSYSRET is a companion instruction to the SYSCALL instruction. It returns from an OS system-call handler to user\r\ncode at privilege level 3. It does so by loading RIP from RCX and loading RFLAGS from R11.1 With a 64-bit operand\r\nsize, SYSRET remains in 64-bit mode; otherwise, it enters compatibility mode and only the low 32 bits of the regis-\r\nters are loaded.\r\nSYSRET loads the CS and SS selectors with values derived from bits 63:48 of the IA32_STAR MSR. However, the\r\nCS and SS descriptor caches are not loaded from the descriptors (in GDT or LDT) referenced by those selectors.\r\nInstead, the descriptor caches are loaded with fixed values. See the Operation section for details. It is the respon-\r\nsibility of OS software to ensure that the descriptors (in GDT or LDT) referenced by those selector values corre-\r\nspond to the fixed values loaded into the descriptor caches; the SYSRET instruction does not ensure this\r\ncorrespondence.\r\nThe SYSRET instruction does not modify the stack pointer (ESP or RSP). For that reason, it is necessary for software\r\nto switch to the user stack. The OS may load the user stack pointer (if it was saved after SYSCALL) before executing\r\nSYSRET; alternatively, user code may load the stack pointer (if it was saved before SYSCALL) after receiving control\r\nfrom SYSRET.\r\nIf the OS loads the stack pointer before executing SYSRET, it must ensure that the handler of any interrupt or\r\nexception delivered between restoring the stack pointer and successful execution of SYSRET is not invoked with the\r\nuser stack. It can do so using approaches such as the following:\r\n. External interrupts. The OS can prevent an external interrupt from being delivered by clearing EFLAGS.IF\r\n before loading the user stack pointer.\r\n. Nonmaskable interrupts (NMIs). The OS can ensure that the NMI handler is invoked with the correct stack by\r\n using the interrupt stack table (IST) mechanism for gate 2 (NMI) in the IDT (see Section 6.14.5, \"Interrupt\r\n Stack Table,\" in Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A).\r\n. General-protection exceptions (#GP). The SYSRET instruction generates #GP(0) if the value of RCX is not\r\n canonical. The OS can address this possibility using one or more of the following approaches:\r\n - Confirming that the value of RCX is canonical before executing SYSRET.\r\n - Using paging to ensure that the SYSCALL instruction will never save a non-canonical value into RCX.\r\n - Using the IST mechanism for gate 13 (#GP) in the IDT.\r\n\r\nOperation\r\nIF (CS.L != 1 ) or (IA32_EFER.LMA != 1) or (IA32_EFER.SCE != 1)\r\n(* Not in 64-Bit Mode or SYSCALL/SYSRET not enabled in IA32_EFER *)\r\n THEN #UD; FI;\r\nIF (CPL != 0) OR (RCX is not canonical) THEN #GP(0); FI;\r\n\r\n\r\n\r\n1. Regardless of the value of R11, the RF and VM flags are always 0 in RFLAGS after execution of SYSRET. In addition, all reserved bits\r\n in RFLAGS retain the fixed values.\r\n\r\n\r\n\r\nIF (operand size is 64-bit)\r\n THEN (* Return to 64-Bit Mode *)\r\n RIP <- RCX;\r\n ELSE (* Return to Compatibility Mode *)\r\n RIP <- ECX;\r\nFI;\r\nRFLAGS <- (R11 & 3C7FD7H) | 2; (* Clear RF, VM, reserved bits; set bit 2 *)\r\n\r\nIF (operand size is 64-bit)\r\n THEN CS.Selector <- IA32_STAR[63:48]+16;\r\n ELSE CS.Selector <- IA32_STAR[63:48];\r\nFI;\r\nCS.Selector <- CS.Selector OR 3; (* RPL forced to 3 *)\r\n(* Set rest of CS to a fixed value *)\r\nCS.Base <- 0; (* Flat segment *)\r\nCS.Limit <- FFFFFH; (* With 4-KByte granularity, implies a 4-GByte limit *)\r\nCS.Type <- 11; (* Execute/read code, accessed *)\r\nCS.S <- 1;\r\nCS.DPL <- 3;\r\nCS.P <- 1;\r\nIF (operand size is 64-bit)\r\n THEN (* Return to 64-Bit Mode *)\r\n CS.L <- 1; (* 64-bit code segment *)\r\n CS.D <- 0; (* Required if CS.L = 1 *)\r\n ELSE (* Return to Compatibility Mode *)\r\n CS.L <- 0; (* Compatibility mode *)\r\n CS.D <- 1; (* 32-bit code segment *)\r\nFI;\r\nCS.G <- 1; (* 4-KByte granularity *)\r\nCPL <- 3;\r\n\r\nSS.Selector <- (IA32_STAR[63:48]+8) OR 3; (* RPL forced to 3 *)\r\n(* Set rest of SS to a fixed value *)\r\nSS.Base <- 0; (* Flat segment *)\r\nSS.Limit <- FFFFFH; (* With 4-KByte granularity, implies a 4-GByte limit *)\r\nSS.Type <- 3; (* Read/write data, accessed *)\r\nSS.S <- 1;\r\nSS.DPL <- 3;\r\nSS.P <- 1;\r\nSS.B <- 1; (* 32-bit stack segment*)\r\nSS.G <- 1; (* 4-KByte granularity *)\r\n\r\nFlags Affected\r\nAll.\r\n\r\nProtected Mode Exceptions\r\n#UD The SYSRET instruction is not recognized in protected mode.\r\n\r\nReal-Address Mode Exceptions\r\n#UD The SYSRET instruction is not recognized in real-address mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD The SYSRET instruction is not recognized in virtual-8086 mode.\r\n\r\n\r\n\r\nCompatibility Mode Exceptions\r\n#UD The SYSRET instruction is not recognized in compatibility mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD If IA32_EFER.SCE = 0.\r\n If the LOCK prefix is used.\r\n#GP(0) If CPL != 0.\r\n If RCX contains a non-canonical address.\r\n\r\n\r\n\r\n\r\n",
"mnem": "SYSRET"
},
{
"description": "TEST-Logical Compare\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n A8 ib TEST AL, imm8 I Valid Valid AND imm8 with AL; set SF, ZF, PF according to\r\n result.\r\n A9 iw TEST AX, imm16 I Valid Valid AND imm16 with AX; set SF, ZF, PF according\r\n to result.\r\n A9 id TEST EAX, imm32 I Valid Valid AND imm32 with EAX; set SF, ZF, PF according\r\n to result.\r\n REX.W + A9 id TEST RAX, imm32 I Valid N.E. AND imm32 sign-extended to 64-bits with\r\n RAX; set SF, ZF, PF according to result.\r\n F6 /0 ib TEST r/m8, imm8 MI Valid Valid AND imm8 with r/m8; set SF, ZF, PF according\r\n to result.\r\n REX + F6 /0 ib TEST r/m8*, imm8 MI Valid N.E. AND imm8 with r/m8; set SF, ZF, PF according\r\n to result.\r\n F7 /0 iw TEST r/m16, imm16 MI Valid Valid AND imm16 with r/m16; set SF, ZF, PF\r\n according to result.\r\n F7 /0 id TEST r/m32, imm32 MI Valid Valid AND imm32 with r/m32; set SF, ZF, PF\r\n according to result.\r\n REX.W + F7 /0 id TEST r/m64, imm32 MI Valid N.E. AND imm32 sign-extended to 64-bits with\r\n r/m64; set SF, ZF, PF according to result.\r\n 84 /r TEST r/m8, r8 MR Valid Valid AND r8 with r/m8; set SF, ZF, PF according to\r\n result.\r\n REX + 84 /r TEST r/m8*, r8* MR Valid N.E. AND r8 with r/m8; set SF, ZF, PF according to\r\n result.\r\n 85 /r TEST r/m16, r16 MR Valid Valid AND r16 with r/m16; set SF, ZF, PF according\r\n to result.\r\n 85 /r TEST r/m32, r32 MR Valid Valid AND r32 with r/m32; set SF, ZF, PF according\r\n to result.\r\n REX.W + 85 /r TEST r/m64, r64 MR Valid N.E. AND r64 with r/m64; set SF, ZF, PF according\r\n to result.\r\n NOTES:\r\n * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n I AL/AX/EAX/RAX imm8/16/32 NA NA\r\n MI ModRM:r/m (r) imm8/16/32 NA NA\r\n MR ModRM:r/m (r) ModRM:reg (r) NA NA\r\n\r\n\r\nDescription\r\nComputes the bit-wise logical AND of first operand (source 1 operand) and the second operand (source 2 operand)\r\nand sets the SF, ZF, and PF status flags according to the result. The result is then discarded.\r\nIn 64-bit mode, using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a\r\nREX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this\r\nsection for encoding data and limits.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nTEMP <- SRC1 AND SRC2;\r\nSF <- MSB(TEMP);\r\n\r\nIF TEMP = 0\r\n THEN ZF <- 1;\r\n ELSE ZF <- 0;\r\nFI:\r\n\r\nPF <- BitwiseXNOR(TEMP[0:7]);\r\nCF <- 0;\r\nOF <- 0;\r\n(* AF is undefined *)\r\n\r\nFlags Affected\r\nThe OF and CF flags are set to 0. The SF, ZF, and PF flags are set according to the result (see the \"Operation\" section\r\nabove). The state of the AF flag is undefined.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n",
"mnem": "TEST"
},
{
"description": "TZCNT - Count the Number of Trailing Zero Bits\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En -bit Feature\r\n Mode Flag\r\n F3 0F BC /r RM V/V BMI1 Count the number of trailing zero bits in r/m16, return result in r16.\r\n TZCNT r16, r/m16\r\n F3 0F BC /r RM V/V BMI1 Count the number of trailing zero bits in r/m32, return result in r32.\r\n TZCNT r32, r/m32\r\n F3 REX.W 0F BC /r RM V/N.E. BMI1 Count the number of trailing zero bits in r/m64, return result in r64.\r\n TZCNT r64, r/m64\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n A ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\n\r\nDescription\r\nTZCNT counts the number of trailing least significant zero bits in source operand (second operand) and returns the\r\nresult in destination operand (first operand). TZCNT is an extension of the BSF instruction. The key difference\r\nbetween TZCNT and BSF instruction is that TZCNT provides operand size as output when source operand is zero\r\nwhile in the case of BSF instruction, if source operand is zero, the content of destination operand are undefined. On\r\nprocessors that do not support TZCNT, the instruction byte encoding is executed as BSF.\r\n\r\nOperation\r\ntemp <- 0\r\nDEST <- 0\r\nDO WHILE ( (temp < OperandSize) and (SRC[ temp] = 0) )\r\n\r\n temp <- temp +1\r\n DEST <- DEST+ 1\r\nOD\r\n\r\nIF DEST = OperandSize\r\n CF <- 1\r\nELSE\r\n CF <- 0\r\nFI\r\n\r\nIF DEST = 0\r\n ZF <- 1\r\nELSE\r\n ZF <- 0\r\nFI\r\n\r\nFlags Affected\r\nZF is set to 1 in case of zero output (least significant bit of the source is set), and to 0 otherwise, CF is set to 1 if\r\nthe input was zero and cleared otherwise. OF, SF, PF and AF flags are undefined.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nTZCNT: unsigned __int32 _tzcnt_u32(unsigned __int32 src);\r\nTZCNT: unsigned __int64 _tzcnt_u64(unsigned __int64 src);\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a null segment\r\n selector.\r\n#SS(0) For an illegal address in the SS segment.\r\n#PF (fault-code) For a page fault.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n\r\nReal-Address Mode Exceptions\r\n#GP(0) If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.\r\n#SS(0) For an illegal address in the SS segment.\r\n\r\nVirtual 8086 Mode Exceptions\r\n#GP(0) If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.\r\n#SS(0) For an illegal address in the SS segment.\r\n#PF (fault-code) For a page fault.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in Protected Mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#PF (fault-code) For a page fault.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "TZCNT"
},
{
"description": "UCOMISD-Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0F 2E /r RM V/V SSE2 Compare low double-precision floating-point values in\r\n UCOMISD xmm1, xmm2/m64 xmm1 and xmm2/mem64 and set the EFLAGS flags\r\n accordingly.\r\n VEX.128.66.0F.WIG 2E /r RM V/V AVX Compare low double-precision floating-point values in\r\n VUCOMISD xmm1, xmm2/m64 xmm1 and xmm2/mem64 and set the EFLAGS flags\r\n accordingly.\r\n EVEX.LIG.66.0F.W1 2E /r T1S V/V AVX512F Compare low double-precision floating-point values in\r\n VUCOMISD xmm1, xmm2/m64{sae} xmm1 and xmm2/m64 and set the EFLAGS flags\r\n accordingly.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r) ModRM:r/m (r) NA NA\r\n T1S ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nPerforms an unordered compare of the double-precision floating-point values in the low quadwords of operand 1\r\n(first operand) and operand 2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register according\r\nto the result (unordered, greater than, less than, or equal). The OF, SF and AF flags in the EFLAGS register are set\r\nto 0. The unordered result is returned if either source operand is a NaN (QNaN or SNaN).\r\nOperand 1 is an XMM register; operand 2 can be an XMM register or a 64 bit memory\r\nlocation.\r\nThe UCOMISD instruction differs from the COMISD instruction in that it signals a SIMD floating-point invalid oper-\r\nation exception (#I) only when a source operand is an SNaN. The COMISD instruction signals an invalid numeric\r\nexception only if a source operand is either an SNaN or a QNaN.\r\nThe EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.\r\nSoftware should ensure VCOMISD is encoded with VEX.L=0. Encoding VCOMISD with VEX.L=1 may encounter\r\nunpredictable behavior across different processor generations.\r\n\r\nOperation\r\n(V)UCOMISD (all versions)\r\nRESULT <- UnorderedCompare(DEST[63:0] <> SRC[63:0]) {\r\n(* Set EFLAGS *) CASE (RESULT) OF\r\n UNORDERED: ZF,PF,CF <- 111;\r\n GREATER_THAN: ZF,PF,CF <- 000;\r\n LESS_THAN: ZF,PF,CF <- 001;\r\n EQUAL: ZF,PF,CF <- 100;\r\nESAC;\r\nOF, AF, SF <- 0; }\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVUCOMISD int _mm_comi_round_sd(__m128d a, __m128d b, int imm, int sae);\r\nUCOMISD int _mm_ucomieq_sd(__m128d a, __m128d b)\r\nUCOMISD int _mm_ucomilt_sd(__m128d a, __m128d b)\r\nUCOMISD int _mm_ucomile_sd(__m128d a, __m128d b)\r\nUCOMISD int _mm_ucomigt_sd(__m128d a, __m128d b)\r\nUCOMISD int _mm_ucomige_sd(__m128d a, __m128d b)\r\nUCOMISD int _mm_ucomineq_sd(__m128d a, __m128d b)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid (if SNaN operands), Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3; additionally\r\n#UD If VEX.vvvv != 1111B.\r\nEVEX-encoded instructions, see Exceptions Type E3NF.\r\n\r\n\r\n\r\n\r\n",
"mnem": "UCOMISD"
},
{
"description": "UCOMISS-Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 0F 2E /r RM V/V SSE Compare low single-precision floating-point values in\r\n UCOMISS xmm1, xmm2/m32 xmm1 and xmm2/mem32 and set the EFLAGS flags\r\n accordingly.\r\n VEX.128.0F.WIG 2E /r RM V/V AVX Compare low single-precision floating-point values in\r\n VUCOMISS xmm1, xmm2/m32 xmm1 and xmm2/mem32 and set the EFLAGS flags\r\n accordingly.\r\n EVEX.LIG.0F.W0 2E /r T1S V/V AVX512F Compare low single-precision floating-point values in\r\n VUCOMISS xmm1, xmm2/m32{sae} xmm1 and xmm2/mem32 and set the EFLAGS flags\r\n accordingly.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r) ModRM:r/m (r) NA NA\r\n T1S ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nCompares the single-precision floating-point values in the low doublewords of operand 1 (first operand) and\r\noperand 2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unor-\r\ndered, greater than, less than, or equal). The OF, SF and AF flags in the EFLAGS register are set to 0. The unor-\r\ndered result is returned if either source operand is a NaN (QNaN or SNaN).\r\nOperand 1 is an XMM register; operand 2 can be an XMM register or a 32 bit memory location.\r\nThe UCOMISS instruction differs from the COMISS instruction in that it signals a SIMD floating-point invalid opera-\r\ntion exception (#I) only if a source operand is an SNaN. The COMISS instruction signals an invalid numeric excep-\r\ntion when a source operand is either a QNaN or SNaN.\r\nThe EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.\r\nSoftware should ensure VCOMISS is encoded with VEX.L=0. Encoding VCOMISS with VEX.L=1 may encounter\r\nunpredictable behavior across different processor generations.\r\n\r\nOperation\r\n(V)UCOMISS (all versions)\r\nRESULT <- UnorderedCompare(DEST[31:0] <> SRC[31:0]) {\r\n(* Set EFLAGS *) CASE (RESULT) OF\r\n UNORDERED: ZF,PF,CF <- 111;\r\n GREATER_THAN: ZF,PF,CF <- 000;\r\n LESS_THAN: ZF,PF,CF <- 001;\r\n EQUAL: ZF,PF,CF <- 100;\r\nESAC;\r\nOF, AF, SF <- 0; }\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVUCOMISS int _mm_comi_round_ss(__m128 a, __m128 b, int imm, int sae);\r\nUCOMISS int _mm_ucomieq_ss(__m128 a, __m128 b);\r\nUCOMISS int _mm_ucomilt_ss(__m128 a, __m128 b);\r\nUCOMISS int _mm_ucomile_ss(__m128 a, __m128 b);\r\nUCOMISS int _mm_ucomigt_ss(__m128 a, __m128 b);\r\nUCOMISS int _mm_ucomige_ss(__m128 a, __m128 b);\r\nUCOMISS int _mm_ucomineq_ss(__m128 a, __m128 b);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid (if SNaN Operands), Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3; additionally\r\n#UD If VEX.vvvv != 1111B.\r\nEVEX-encoded instructions, see Exceptions Type E3NF.\r\n\r\n\r\n\r\n\r\n",
"mnem": "UCOMISS"
},
{
"description": "UD2-Undefined Instruction\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F 0B UD2 NP Valid Valid Raise invalid opcode exception.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nGenerates an invalid opcode exception. This instruction is provided for software testing to explicitly generate an\r\ninvalid opcode exception. The opcode for this instruction is reserved for this purpose.\r\nOther than raising the invalid opcode exception, this instruction has no effect on processor state or memory.\r\nEven though it is the execution of the UD2 instruction that causes the invalid opcode exception, the instruction\r\npointer saved by delivery of the exception references the UD2 instruction (and not the following instruction).\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\n#UD (* Generates invalid opcode exception *);\r\n\r\nFlags Affected\r\nNone.\r\n\r\nExceptions (All Operating Modes)\r\n#UD Raises an invalid opcode exception in all operating modes.\r\n\r\n\r\n\r\n\r\n",
"mnem": "UD2"
},
{
"description": "UNPCKHPD-Unpack and Interleave High Packed Double-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0F 15 /r V/V SSE2 Unpacks and Interleaves double-precision floating-point\r\n UNPCKHPD xmm1, xmm2/m128 RM values from high quadwords of xmm1 and\r\n xmm2/m128.\r\n VEX.NDS.128.66.0F.WIG 15 /r V/V AVX Unpacks and Interleaves double-precision floating-point\r\n VUNPCKHPD xmm1,xmm2, RVM values from high quadwords of xmm2 and\r\n xmm3/m128 xmm3/m128.\r\n VEX.NDS.256.66.0F.WIG 15 /r RVM V/V AVX Unpacks and Interleaves double-precision floating-point\r\n VUNPCKHPD ymm1,ymm2, values from high quadwords of ymm2 and\r\n ymm3/m256 ymm3/m256.\r\n EVEX.NDS.128.66.0F.W1 15 /r FV V/V AVX512VL Unpacks and Interleaves double precision floating-point\r\n VUNPCKHPD xmm1 {k1}{z}, xmm2, AVX512F values from high quadwords of xmm2 and\r\n xmm3/m128/m64bcst xmm3/m128/m64bcst subject to writemask k1.\r\n EVEX.NDS.256.66.0F.W1 15 /r FV V/V AVX512VL Unpacks and Interleaves double precision floating-point\r\n VUNPCKHPD ymm1 {k1}{z}, ymm2, AVX512F values from high quadwords of ymm2 and\r\n ymm3/m256/m64bcst ymm3/m256/m64bcst subject to writemask k1.\r\n EVEX.NDS.512.66.0F.W1 15 /r FV V/V AVX512F Unpacks and Interleaves double-precision floating-point\r\n VUNPCKHPD zmm1 {k1}{z}, zmm2, values from high quadwords of zmm2 and\r\n zmm3/m512/m64bcst zmm3/m512/m64bcst subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms an interleaved unpack of the high double-precision floating-point values from the first source operand and\r\nthe second source operand. See Figure 4-15 in the Intel 64 and IA-32 Architectures Software Developer's\r\nManual, Volume 2B.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nZMM register destination are unmodified. When unpacking from a memory operand, an implementation may fetch\r\nonly the appropriate 64 bits; however, alignment to 16-byte boundary and normal segment checking will still be\r\nenforced.\r\nVEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM\r\nregister or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register.\r\nEVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM\r\nregister, a 512-bit memory location, or a 512-bit vector broadcasted from a 64-bit memory location. The destina-\r\ntion operand is a ZMM register, conditionally updated using writemask k1.\r\nEVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM\r\nregister, a 256-bit memory location, or a 256-bit vector broadcasted from a 64-bit memory location. The destina-\r\ntion operand is a YMM register, conditionally updated using writemask k1.\r\nEVEX.128 encoded version: The first source operand is a XMM register. The second source operand is a XMM\r\nregister, a 128-bit memory location, or a 128-bit vector broadcasted from a 64-bit memory location. The destina-\r\ntion operand is a XMM register, conditionally updated using writemask k1.\r\n\r\n\r\n\r\nOperation\r\nVUNPCKHPD (EVEX encoded versions when SRC2 is a register)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF VL >= 128\r\n TMP_DEST[63:0] <- SRC1[127:64]\r\n TMP_DEST[127:64] <- SRC2[127:64]\r\nFI;\r\nIF VL >= 256\r\n TMP_DEST[191:128] <- SRC1[255:192]\r\n TMP_DEST[255:192] <- SRC2[255:192]\r\nFI;\r\nIF VL >= 512\r\n TMP_DEST[319:256] <- SRC1[383:320]\r\n TMP_DEST[383:320] <- SRC2[383:320]\r\n TMP_DEST[447:384] <- SRC1[511:448]\r\n TMP_DEST[511:448] <- SRC2[511:448]\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVUNPCKHPD (EVEX encoded version when SRC2 is memory)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF (EVEX.b = 1)\r\n THEN TMP_SRC2[i+63:i] <- SRC2[63:0]\r\n ELSE TMP_SRC2[i+63:i] <- SRC2[i+63:i]\r\n FI;\r\nENDFOR;\r\nIF VL >= 128\r\n TMP_DEST[63:0] <- SRC1[127:64]\r\n TMP_DEST[127:64] <- TMP_SRC2[127:64]\r\nFI;\r\nIF VL >= 256\r\n TMP_DEST[191:128] <- SRC1[255:192]\r\n TMP_DEST[255:192] <- TMP_SRC2[255:192]\r\nFI;\r\nIF VL >= 512\r\n TMP_DEST[319:256] <- SRC1[383:320]\r\n TMP_DEST[383:320] <- TMP_SRC2[383:320]\r\n TMP_DEST[447:384] <- SRC1[511:448]\r\n TMP_DEST[511:448] <- TMP_SRC2[511:448]\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVUNPCKHPD (VEX.256 encoded version)\r\nDEST[63:0] <-SRC1[127:64]\r\nDEST[127:64] <-SRC2[127:64]\r\nDEST[191:128]<-SRC1[255:192]\r\nDEST[255:192]<-SRC2[255:192]\r\nDEST[MAX_VL-1:256] <-0\r\n\r\nVUNPCKHPD (VEX.128 encoded version)\r\nDEST[63:0] <-SRC1[127:64]\r\nDEST[127:64] <-SRC2[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nUNPCKHPD (128-bit Legacy SSE version)\r\nDEST[63:0] <-SRC1[127:64]\r\nDEST[127:64] <-SRC2[127:64]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVUNPCKHPD __m512d _mm512_unpackhi_pd( __m512d a, __m512d b);\r\nVUNPCKHPD __m512d _mm512_mask_unpackhi_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);\r\nVUNPCKHPD __m512d _mm512_maskz_unpackhi_pd(__mmask8 k, __m512d a, __m512d b);\r\nVUNPCKHPD __m256d _mm256_unpackhi_pd(__m256d a, __m256d b)\r\nVUNPCKHPD __m256d _mm256_mask_unpackhi_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);\r\nVUNPCKHPD __m256d _mm256_maskz_unpackhi_pd(__mmask8 k, __m256d a, __m256d b);\r\nUNPCKHPD __m128d _mm_unpackhi_pd(__m128d a, __m128d b)\r\nVUNPCKHPD __m128d _mm_mask_unpackhi_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);\r\nVUNPCKHPD __m128d _mm_maskz_unpackhi_pd(__mmask8 k, __m128d a, __m128d b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instructions, see Exceptions Type 4.\r\nEVEX-encoded instructions, see Exceptions Type E4NF.\r\n\r\n\r\n\r\n\r\n",
"mnem": "UNPCKHPD"
},
{
"description": "UNPCKHPS-Unpack and Interleave High Packed Single-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 0F 15 /r V/V SSE Unpacks and Interleaves single-precision floating-point\r\n RM\r\n UNPCKHPS xmm1, xmm2/m128 values from high quadwords of xmm1 and xmm2/m128.\r\n VEX.NDS.128.0F.WIG 15 /r V/V AVX Unpacks and Interleaves single-precision floating-point\r\n VUNPCKHPS xmm1, xmm2, RVM values from high quadwords of xmm2 and xmm3/m128.\r\n xmm3/m128\r\n VEX.NDS.256.0F.WIG 15 /r RVM V/V AVX Unpacks and Interleaves single-precision floating-point\r\n VUNPCKHPS ymm1, ymm2, values from high quadwords of ymm2 and ymm3/m256.\r\n ymm3/m256\r\n EVEX.NDS.128.0F.W0 15 /r FV V/V AVX512VL Unpacks and Interleaves single-precision floating-point\r\n VUNPCKHPS xmm1 {k1}{z}, xmm2, AVX512F values from high quadwords of xmm2 and\r\n xmm3/m128/m32bcst xmm3/m128/m32bcst and write result to xmm1 subject to\r\n writemask k1.\r\n EVEX.NDS.256.0F.W0 15 /r FV V/V AVX512VL Unpacks and Interleaves single-precision floating-point\r\n VUNPCKHPS ymm1 {k1}{z}, ymm2, AVX512F values from high quadwords of ymm2 and\r\n ymm3/m256/m32bcst ymm3/m256/m32bcst and write result to ymm1 subject to\r\n writemask k1.\r\n EVEX.NDS.512.0F.W0 15 /r FV V/V AVX512F Unpacks and Interleaves single-precision floating-point\r\n VUNPCKHPS zmm1 {k1}{z}, zmm2, values from high quadwords of zmm2 and\r\n zmm3/m512/m32bcst zmm3/m512/m32bcst and write result to zmm1 subject to\r\n writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms an interleaved unpack of the high single-precision floating-point values from the first source operand and\r\nthe second source operand.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nZMM register destination are unmodified. When unpacking from a memory operand, an implementation may fetch\r\nonly the appropriate 64 bits; however, alignment to 16-byte boundary and normal segment checking will still be\r\nenforced.\r\nVEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM\r\nregister or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\nVEX.256 encoded version: The second source operand is an YMM register or an 256-bit memory location. The first\r\nsource operand and destination operands are YMM registers.\r\n\r\n\r\n\r\n\r\n\r\n SRC1 X7 X6 X5 X4 X3 X2 X1 X0\r\n\r\n\r\n SRC2 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0\r\n\r\n\r\n\r\n\r\n DEST Y7 X7 Y6 X6 Y3 X3 Y2 X2\r\n\r\n\r\n\r\n\r\n Figure 4-27. VUNPCKHPS Operation\r\n\r\n\r\nEVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM\r\nregister, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit memory location. The destina-\r\ntion operand is a ZMM register, conditionally updated using writemask k1.\r\nEVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM\r\nregister, a 256-bit memory location, or a 256-bit vector broadcasted from a 32-bit memory location. The destina-\r\ntion operand is a YMM register, conditionally updated using writemask k1.\r\nEVEX.128 encoded version: The first source operand is a XMM register. The second source operand is a XMM\r\nregister, a 128-bit memory location, or a 128-bit vector broadcasted from a 32-bit memory location. The destina-\r\ntion operand is a XMM register, conditionally updated using writemask k1.\r\n\r\nOperation\r\nVUNPCKHPS (EVEX encoded version when SRC2 is a register)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF VL >= 128\r\n TMP_DEST[31:0] <- SRC1[95:64]\r\n TMP_DEST[63:32] <- SRC2[95:64]\r\n TMP_DEST[95:64] <- SRC1[127:96]\r\n TMP_DEST[127:96] <- SRC2[127:96]\r\nFI;\r\nIF VL >= 256\r\n TMP_DEST[159:128] <- SRC1[223:192]\r\n TMP_DEST[191:160] <- SRC2[223:192]\r\n TMP_DEST[223:192] <- SRC1[255:224]\r\n TMP_DEST[255:224] <- SRC2[255:224]\r\nFI;\r\nIF VL >= 512\r\n TMP_DEST[287:256] <- SRC1[351:320]\r\n TMP_DEST[319:288] <- SRC2[351:320]\r\n TMP_DEST[351:320] <- SRC1[383:352]\r\n TMP_DEST[383:352] <- SRC2[383:352]\r\n TMP_DEST[415:384] <- SRC1[479:448]\r\n TMP_DEST[447:416] <- SRC2[479:448]\r\n TMP_DEST[479:448] <- SRC1[511:480]\r\n TMP_DEST[511:480] <- SRC2[511:480]\r\nFI;\r\n\r\n\r\n\r\n\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_DEST[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVUNPCKHPS (EVEX encoded version when SRC2 is memory)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF (EVEX.b = 1)\r\n THEN TMP_SRC2[i+31:i] <- SRC2[31:0]\r\n ELSE TMP_SRC2[i+31:i] <- SRC2[i+31:i]\r\n FI;\r\nENDFOR;\r\nIF VL >= 128\r\n TMP_DEST[31:0] <- SRC1[95:64]\r\n TMP_DEST[63:32] <- TMP_SRC2[95:64]\r\n TMP_DEST[95:64] <- SRC1[127:96]\r\n TMP_DEST[127:96] <- TMP_SRC2[127:96]\r\nFI;\r\nIF VL >= 256\r\n TMP_DEST[159:128] <- SRC1[223:192]\r\n TMP_DEST[191:160] <- TMP_SRC2[223:192]\r\n TMP_DEST[223:192] <- SRC1[255:224]\r\n TMP_DEST[255:224] <- TMP_SRC2[255:224]\r\nFI;\r\nIF VL >= 512\r\n TMP_DEST[287:256] <- SRC1[351:320]\r\n TMP_DEST[319:288] <- TMP_SRC2[351:320]\r\n TMP_DEST[351:320] <- SRC1[383:352]\r\n TMP_DEST[383:352] <- TMP_SRC2[383:352]\r\n TMP_DEST[415:384] <- SRC1[479:448]\r\n TMP_DEST[447:416] <- TMP_SRC2[479:448]\r\n TMP_DEST[479:448] <- SRC1[511:480]\r\n TMP_DEST[511:480] <- TMP_SRC2[511:480]\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_DEST[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n\r\n\r\n\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVUNPCKHPS (VEX.256 encoded version)\r\nDEST[31:0] <-SRC1[95:64]\r\nDEST[63:32] <-SRC2[95:64]\r\nDEST[95:64] <-SRC1[127:96]\r\nDEST[127:96] <-SRC2[127:96]\r\nDEST[159:128] <-SRC1[223:192]\r\nDEST[191:160] <-SRC2[223:192]\r\nDEST[223:192] <-SRC1[255:224]\r\nDEST[255:224] <-SRC2[255:224]\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVUNPCKHPS (VEX.128 encoded version)\r\nDEST[31:0] <-SRC1[95:64]\r\nDEST[63:32] <-SRC2[95:64]\r\nDEST[95:64] <-SRC1[127:96]\r\nDEST[127:96] <-SRC2[127:96]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nUNPCKHPS (128-bit Legacy SSE version)\r\nDEST[31:0] <-SRC1[95:64]\r\nDEST[63:32] <-SRC2[95:64]\r\nDEST[95:64] <-SRC1[127:96]\r\nDEST[127:96] <-SRC2[127:96]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVUNPCKHPS __m512 _mm512_unpackhi_ps( __m512 a, __m512 b);\r\nVUNPCKHPS __m512 _mm512_mask_unpackhi_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);\r\nVUNPCKHPS __m512 _mm512_maskz_unpackhi_ps(__mmask16 k, __m512 a, __m512 b);\r\nVUNPCKHPS __m256 _mm256_unpackhi_ps (__m256 a, __m256 b);\r\nVUNPCKHPS __m256 _mm256_mask_unpackhi_ps(__m256 s, __mmask8 k, __m256 a, __m256 b);\r\nVUNPCKHPS __m256 _mm256_maskz_unpackhi_ps(__mmask8 k, __m256 a, __m256 b);\r\nUNPCKHPS __m128 _mm_unpackhi_ps (__m128 a, __m128 b);\r\nVUNPCKHPS __m128 _mm_mask_unpackhi_ps(__m128 s, __mmask8 k, __m128 a, __m128 b);\r\nVUNPCKHPS __m128 _mm_maskz_unpackhi_ps(__mmask8 k, __m128 a, __m128 b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instructions, see Exceptions Type 4.\r\nEVEX-encoded instructions, see Exceptions Type E4NF.\r\n\r\n\r\n\r\n\r\n",
"mnem": "UNPCKHPS"
},
{
"description": "UNPCKLPD-Unpack and Interleave Low Packed Double-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0F 14 /r V/V SSE2 Unpacks and Interleaves double-precision floating-point\r\n RM\r\n UNPCKLPD xmm1, xmm2/m128 values from low quadwords of xmm1 and xmm2/m128.\r\n VEX.NDS.128.66.0F.WIG 14 /r V/V AVX Unpacks and Interleaves double-precision floating-point\r\n VUNPCKLPD xmm1,xmm2, RVM values from low quadwords of xmm2 and xmm3/m128.\r\n xmm3/m128\r\n VEX.NDS.256.66.0F.WIG 14 /r RVM V/V AVX Unpacks and Interleaves double-precision floating-point\r\n VUNPCKLPD ymm1,ymm2, values from low quadwords of ymm2 and ymm3/m256.\r\n ymm3/m256\r\n EVEX.NDS.128.66.0F.W1 14 /r FV V/V AVX512VL Unpacks and Interleaves double precision floating-point\r\n VUNPCKLPD xmm1 {k1}{z}, xmm2, AVX512F values from low quadwords of xmm2 and\r\n xmm3/m128/m64bcst xmm3/m128/m64bcst subject to write mask k1.\r\n EVEX.NDS.256.66.0F.W1 14 /r FV V/V AVX512VL Unpacks and Interleaves double precision floating-point\r\n VUNPCKLPD ymm1 {k1}{z}, ymm2, AVX512F values from low quadwords of ymm2 and\r\n ymm3/m256/m64bcst ymm3/m256/m64bcst subject to write mask k1.\r\n EVEX.NDS.512.66.0F.W1 14 /r FV V/V AVX512F Unpacks and Interleaves double-precision floating-point\r\n VUNPCKLPD zmm1 {k1}{z}, zmm2, values from low quadwords of zmm2 and\r\n zmm3/m512/m64bcst zmm3/m512/m64bcst subject to write mask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms an interleaved unpack of the low double-precision floating-point values from the first source operand and\r\nthe second source operand.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nZMM register destination are unmodified. When unpacking from a memory operand, an implementation may fetch\r\nonly the appropriate 64 bits; however, alignment to 16-byte boundary and normal segment checking will still be\r\nenforced.\r\nVEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM\r\nregister or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register.\r\nEVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM\r\nregister, a 512-bit memory location, or a 512-bit vector broadcasted from a 64-bit memory location. The destina-\r\ntion operand is a ZMM register, conditionally updated using writemask k1.\r\nEVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM\r\nregister, a 256-bit memory location, or a 256-bit vector broadcasted from a 64-bit memory location. The destina-\r\ntion operand is a YMM register, conditionally updated using writemask k1.\r\nEVEX.128 encoded version: The first source operand is an XMM register. The second source operand is a XMM\r\nregister, a 128-bit memory location, or a 128-bit vector broadcasted from a 64-bit memory location. The destina-\r\ntion operand is a XMM register, conditionally updated using writemask k1.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVUNPCKLPD (EVEX encoded versions when SRC2 is a register)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF VL >= 128\r\n TMP_DEST[63:0] <- SRC1[63:0]\r\n TMP_DEST[127:64] <- SRC2[63:0]\r\nFI;\r\nIF VL >= 256\r\n TMP_DEST[191:128] <- SRC1[191:128]\r\n TMP_DEST[255:192] <- SRC2[191:128]\r\nFI;\r\nIF VL >= 512\r\n TMP_DEST[319:256] <- SRC1[319:256]\r\n TMP_DEST[383:320] <- SRC2[319:256]\r\n TMP_DEST[447:384] <- SRC1[447:384]\r\n TMP_DEST[511:448] <- SRC2[447:384]\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVUNPCKLPD (EVEX encoded version when SRC2 is memory)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF (EVEX.b = 1)\r\n THEN TMP_SRC2[i+63:i] <- SRC2[63:0]\r\n ELSE TMP_SRC2[i+63:i] <- SRC2[i+63:i]\r\n FI;\r\nENDFOR;\r\nIF VL >= 128\r\n TMP_DEST[63:0] <- SRC1[63:0]\r\n TMP_DEST[127:64] <- TMP_SRC2[63:0]\r\nFI;\r\nIF VL >= 256\r\n TMP_DEST[191:128] <- SRC1[191:128]\r\n TMP_DEST[255:192] <- TMP_SRC2[191:128]\r\nFI;\r\nIF VL >= 512\r\n TMP_DEST[319:256] <- SRC1[319:256]\r\n TMP_DEST[383:320] <- TMP_SRC2[319:256]\r\n TMP_DEST[447:384] <- SRC1[447:384]\r\n TMP_DEST[511:448] <- TMP_SRC2[447:384]\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVUNPCKLPD (VEX.256 encoded version)\r\nDEST[63:0] <-SRC1[63:0]\r\nDEST[127:64] <-SRC2[63:0]\r\nDEST[191:128] <-SRC1[191:128]\r\nDEST[255:192] <-SRC2[191:128]\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVUNPCKLPD (VEX.128 encoded version)\r\nDEST[63:0] <-SRC1[63:0]\r\nDEST[127:64] <-SRC2[63:0]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nUNPCKLPD (128-bit Legacy SSE version)\r\nDEST[63:0] <-SRC1[63:0]\r\nDEST[127:64] <-SRC2[63:0]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVUNPCKLPD __m512d _mm512_unpacklo_pd( __m512d a, __m512d b);\r\nVUNPCKLPD __m512d _mm512_mask_unpacklo_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);\r\nVUNPCKLPD __m512d _mm512_maskz_unpacklo_pd(__mmask8 k, __m512d a, __m512d b);\r\nVUNPCKLPD __m256d _mm256_unpacklo_pd(__m256d a, __m256d b)\r\nVUNPCKLPD __m256d _mm256_mask_unpacklo_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);\r\nVUNPCKLPD __m256d _mm256_maskz_unpacklo_pd(__mmask8 k, __m256d a, __m256d b);\r\nUNPCKLPD __m128d _mm_unpacklo_pd(__m128d a, __m128d b)\r\nVUNPCKLPD __m128d _mm_mask_unpacklo_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);\r\nVUNPCKLPD __m128d _mm_maskz_unpacklo_pd(__mmask8 k, __m128d a, __m128d b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instructions, see Exceptions Type 4.\r\nEVEX-encoded instructions, see Exceptions Type E4NF.\r\n\r\n\r\n\r\n\r\n",
"mnem": "UNPCKLPD"
},
{
"description": "UNPCKLPS-Unpack and Interleave Low Packed Single-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 0F 14 /r V/V SSE Unpacks and Interleaves single-precision floating-point\r\n RM\r\n UNPCKLPS xmm1, xmm2/m128 values from low quadwords of xmm1 and xmm2/m128.\r\n VEX.NDS.128.0F.WIG 14 /r V/V AVX Unpacks and Interleaves single-precision floating-point\r\n VUNPCKLPS xmm1,xmm2, RVM values from low quadwords of xmm2 and xmm3/m128.\r\n xmm3/m128\r\n VEX.NDS.256.0F.WIG 14 /r RVM V/V AVX Unpacks and Interleaves single-precision floating-point\r\n VUNPCKLPS values from low quadwords of ymm2 and ymm3/m256.\r\n ymm1,ymm2,ymm3/m256\r\n EVEX.NDS.128.0F.W0 14 /r FV V/V AVX512VL Unpacks and Interleaves single-precision floating-point\r\n VUNPCKLPS xmm1 {k1}{z}, xmm2, AVX512F values from low quadwords of xmm2 and xmm3/mem and\r\n xmm3/m128/m32bcst write result to xmm1 subject to write mask k1.\r\n EVEX.NDS.256.0F.W0 14 /r FV V/V AVX512VL Unpacks and Interleaves single-precision floating-point\r\n VUNPCKLPS ymm1 {k1}{z}, ymm2, AVX512F values from low quadwords of ymm2 and ymm3/mem and\r\n ymm3/m256/m32bcst write result to ymm1 subject to write mask k1.\r\n EVEX.NDS.512.0F.W0 14 /r FV V/V AVX512F Unpacks and Interleaves single-precision floating-point\r\n VUNPCKLPS zmm1 {k1}{z}, zmm2, values from low quadwords of zmm2 and\r\n zmm3/m512/m32bcst zmm3/m512/m32bcst and write result to zmm1 subject\r\n to write mask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms an interleaved unpack of the low single-precision floating-point values from the first source operand and\r\nthe second source operand.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nZMM register destination are unmodified. When unpacking from a memory operand, an implementation may fetch\r\nonly the appropriate 64 bits; however, alignment to 16-byte boundary and normal segment checking will still be\r\nenforced.\r\nVEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM\r\nregister or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)\r\nof the corresponding ZMM register destination are zeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM\r\nregister or a 256-bit memory location. The destination operand is a YMM register.\r\n\r\n\r\n\r\n\r\n\r\n SRC1 X7 X6 X5 X4 X3 X2 X1 X0\r\n\r\n\r\n SRC2 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0\r\n\r\n\r\n\r\n\r\n DEST Y5 X5 Y4 X4 Y1 X1 Y0 X0\r\n\r\n\r\n\r\n\r\n Figure 4-28. VUNPCKLPS Operation\r\n\r\n\r\nEVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM\r\nregister, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit memory location. The destina-\r\ntion operand is a ZMM register, conditionally updated using writemask k1.\r\nEVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM\r\nregister, a 256-bit memory location, or a 256-bit vector broadcasted from a 32-bit memory location. The destina-\r\ntion operand is a YMM register, conditionally updated using writemask k1.\r\nEVEX.128 encoded version: The first source operand is an XMM register. The second source operand is a XMM\r\nregister, a 128-bit memory location, or a 128-bit vector broadcasted from a 32-bit memory location. The destina-\r\ntion operand is a XMM register, conditionally updated using writemask k1.\r\n\r\nOperation\r\nVUNPCKLPS (EVEX encoded version when SRC2 is a ZMM register)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF VL >= 128\r\n TMP_DEST[31:0] <- SRC1[31:0]\r\n TMP_DEST[63:32] <- SRC2[31:0]\r\n TMP_DEST[95:64] <- SRC1[63:32]\r\n TMP_DEST[127:96] <- SRC2[63:32]\r\nFI;\r\nIF VL >= 256\r\n TMP_DEST[159:128] <- SRC1[159:128]\r\n TMP_DEST[191:160] <- SRC2[159:128]\r\n TMP_DEST[223:192] <- SRC1[191:160]\r\n TMP_DEST[255:224] <- SRC2[191:160]\r\nFI;\r\nIF VL >= 512\r\n TMP_DEST[287:256] <- SRC1[287:256]\r\n TMP_DEST[319:288] <- SRC2[287:256]\r\n TMP_DEST[351:320] <- SRC1[319:288]\r\n TMP_DEST[383:352] <- SRC2[319:288]\r\n TMP_DEST[415:384] <- SRC1[415:384]\r\n TMP_DEST[447:416] <- SRC2[415:384]\r\n TMP_DEST[479:448] <- SRC1[447:416]\r\n TMP_DEST[511:480] <- SRC2[447:416]\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n\r\n\r\n\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_DEST[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVUNPCKLPS (EVEX encoded version when SRC2 is memory)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 31\r\n IF (EVEX.b = 1)\r\n THEN TMP_SRC2[i+31:i] <- SRC2[31:0]\r\n ELSE TMP_SRC2[i+31:i] <- SRC2[i+31:i]\r\n FI;\r\nENDFOR;\r\nIF VL >= 128\r\nTMP_DEST[31:0] <- SRC1[31:0]\r\nTMP_DEST[63:32] <- TMP_SRC2[31:0]\r\nTMP_DEST[95:64] <- SRC1[63:32]\r\nTMP_DEST[127:96] <- TMP_SRC2[63:32]\r\nFI;\r\nIF VL >= 256\r\n TMP_DEST[159:128] <- SRC1[159:128]\r\n TMP_DEST[191:160] <- TMP_SRC2[159:128]\r\n TMP_DEST[223:192] <- SRC1[191:160]\r\n TMP_DEST[255:224] <- TMP_SRC2[191:160]\r\nFI;\r\nIF VL >= 512\r\n TMP_DEST[287:256] <- SRC1[287:256]\r\n TMP_DEST[319:288] <- TMP_SRC2[287:256]\r\n TMP_DEST[351:320] <- SRC1[319:288]\r\n TMP_DEST[383:352] <- TMP_SRC2[319:288]\r\n TMP_DEST[415:384] <- SRC1[415:384]\r\n TMP_DEST[447:416] <- TMP_SRC2[415:384]\r\n TMP_DEST[479:448] <- SRC1[447:416]\r\n TMP_DEST[511:480] <- TMP_SRC2[447:416]\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_DEST[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\n\r\n\r\n\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nUNPCKLPS (VEX.256 encoded version)\r\nDEST[31:0] <-SRC1[31:0]\r\nDEST[63:32] <-SRC2[31:0]\r\nDEST[95:64] <-SRC1[63:32]\r\nDEST[127:96] <-SRC2[63:32]\r\nDEST[159:128] <-SRC1[159:128]\r\nDEST[191:160] <-SRC2[159:128]\r\nDEST[223:192] <-SRC1[191:160]\r\nDEST[255:224] <-SRC2[191:160]\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVUNPCKLPS (VEX.128 encoded version)\r\nDEST[31:0] <-SRC1[31:0]\r\nDEST[63:32] <-SRC2[31:0]\r\nDEST[95:64] <-SRC1[63:32]\r\nDEST[127:96] <-SRC2[63:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nUNPCKLPS (128-bit Legacy SSE version)\r\nDEST[31:0] <-SRC1[31:0]\r\nDEST[63:32] <-SRC2[31:0]\r\nDEST[95:64] <-SRC1[63:32]\r\nDEST[127:96] <-SRC2[63:32]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVUNPCKLPS __m512 _mm512_unpacklo_ps(__m512 a, __m512 b);\r\nVUNPCKLPS __m512 _mm512_mask_unpacklo_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);\r\nVUNPCKLPS __m512 _mm512_maskz_unpacklo_ps(__mmask16 k, __m512 a, __m512 b);\r\nVUNPCKLPS __m256 _mm256_unpacklo_ps (__m256 a, __m256 b);\r\nVUNPCKLPS __m256 _mm256_mask_unpacklo_ps(__m256 s, __mmask8 k, __m256 a, __m256 b);\r\nVUNPCKLPS __m256 _mm256_maskz_unpacklo_ps(__mmask8 k, __m256 a, __m256 b);\r\nUNPCKLPS __m128 _mm_unpacklo_ps (__m128 a, __m128 b);\r\nVUNPCKLPS __m128 _mm_mask_unpacklo_ps(__m128 s, __mmask8 k, __m128 a, __m128 b);\r\nVUNPCKLPS __m128 _mm_maskz_unpacklo_ps(__mmask8 k, __m128 a, __m128 b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instructions, see Exceptions Type 4.\r\nEVEX-encoded instructions, see Exceptions Type E4NF.\r\n\r\n\r\n\r\n\r\n",
"mnem": "UNPCKLPS"
},
{
"description": "VALIGND/VALIGNQ-Align Doubleword/Quadword Vectors\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.128.66.0F3A.W0 03 /r ib FV V/V AVX512VL Shift right and merge vectors xmm2 and\r\n VALIGND xmm1 {k1}{z}, xmm2, AVX512F xmm3/m128/m32bcst with double-word granularity\r\n xmm3/m128/m32bcst, imm8 using imm8 as number of elements to shift, and store the\r\n final result in xmm1, under writemask.\r\n EVEX.NDS.128.66.0F3A.W1 03 /r ib FV V/V AVX512VL Shift right and merge vectors xmm2 and\r\n VALIGNQ xmm1 {k1}{z}, xmm2, AVX512F xmm3/m128/m64bcst with quad-word granularity using\r\n xmm3/m128/m64bcst, imm8 imm8 as number of elements to shift, and store the final\r\n result in xmm1, under writemask.\r\n EVEX.NDS.256.66.0F3A.W0 03 /r ib FV V/V AVX512VL Shift right and merge vectors ymm2 and\r\n VALIGND ymm1 {k1}{z}, ymm2, AVX512F ymm3/m256/m32bcst with double-word granularity\r\n ymm3/m256/m32bcst, imm8 using imm8 as number of elements to shift, and store the\r\n final result in ymm1, under writemask.\r\n EVEX.NDS.256.66.0F3A.W1 03 /r ib FV V/V AVX512VL Shift right and merge vectors ymm2 and\r\n VALIGNQ ymm1 {k1}{z}, ymm2, AVX512F ymm3/m256/m64bcst with quad-word granularity using\r\n ymm3/m256/m64bcst, imm8 imm8 as number of elements to shift, and store the final\r\n result in ymm1, under writemask.\r\n EVEX.NDS.512.66.0F3A.W0 03 /r ib FV V/V AVX512F Shift right and merge vectors zmm2 and\r\n VALIGND zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst with double-word granularity\r\n zmm3/m512/m32bcst, imm8 using imm8 as number of elements to shift, and store the\r\n final result in zmm1, under writemask.\r\n EVEX.NDS.512.66.0F3A.W1 03 /r ib FV V/V AVX512F Shift right and merge vectors zmm2 and\r\n VALIGNQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst with quad-word granularity using\r\n zmm3/m512/m64bcst, imm8 imm8 as number of elements to shift, and store the final\r\n result in zmm1, under writemask.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nConcatenates and shifts right doubleword/quadword elements of the first source operand (the second operand)\r\nand the second source operand (the third operand) into a 1024/512/256-bit intermediate vector. The low\r\n512/256/128-bit of the intermediate vector is written to the destination operand (the first operand) using the\r\nwritemask k1. The destination and first source operands are ZMM/YMM/XMM registers. The second source operand\r\ncan be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted\r\nfrom a 32/64-bit memory location.\r\nThis instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1\r\nare computed and stored into zmm1. Elements in zmm1 with the corresponding bit clear in k1 retain their previous\r\nvalues (merging-masking) or are set to 0 (zeroing-masking).\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVALIGND (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nIF (SRC2 *is memory*) (AND EVEX.b = 1)\r\n THEN\r\n FOR j <- 0 TO KL-1\r\n i <-j * 32\r\n src[i+31:i] <- SRC2[31:0]\r\n ENDFOR;\r\n ELSE src <- SRC2\r\nFI\r\n; Concatenate sources\r\ntmp[VL-1:0] <- src[VL-1:0]\r\ntmp[2VL-1:VL] <- SRC1[VL-1:0]\r\n; Shift right doubleword elements\r\nIF VL = 128\r\n THEN SHIFT = imm8[1:0]\r\n ELSE\r\n IF VL = 256\r\n THEN SHIFT = imm8[2:0]\r\n ELSE SHIFT = imm8[3:0]\r\n FI\r\nFI;\r\ntmp[2VL-1:0] <- tmp[2VL-1:0] >> (32*SHIFT)\r\n; Apply writemask\r\nFOR j <- 0 TO KL-1\r\n i <-j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- tmp[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVALIGNQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256),(8, 512)\r\nIF (SRC2 *is memory*) (AND EVEX.b = 1)\r\n THEN\r\n FOR j <- 0 TO KL-1\r\n i <-j * 64\r\n src[i+63:i] <- SRC2[63:0]\r\n ENDFOR;\r\n ELSE src <- SRC2\r\nFI\r\n; Concatenate sources\r\ntmp[VL-1:0] <- src[VL-1:0]\r\ntmp[2VL-1:VL] <- SRC1[VL-1:0]\r\n; Shift right quadword elements\r\nIF VL = 128\r\n THEN SHIFT = imm8[0]\r\n ELSE\r\n IF VL = 256\r\n THEN SHIFT = imm8[1:0]\r\n ELSE SHIFT = imm8[2:0]\r\n FI\r\nFI;\r\ntmp[2VL-1:0] <- tmp[2VL-1:0] >> (64*SHIFT)\r\n; Apply writemask\r\nFOR j <- 0 TO KL-1\r\n i <-j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- tmp[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVALIGND __m512i _mm512_alignr_epi32( __m512i a, __m512i b, int cnt);\r\nVALIGND __m512i _mm512_mask_alignr_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b, int cnt);\r\nVALIGND __m512i _mm512_maskz_alignr_epi32( __mmask16 k, __m512i a, __m512i b, int cnt);\r\nVALIGND __m256i _mm256_mask_alignr_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b, int cnt);\r\nVALIGND __m256i _mm256_maskz_alignr_epi32( __mmask8 k, __m256i a, __m256i b, int cnt);\r\nVALIGND __m128i _mm_mask_alignr_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b, int cnt);\r\nVALIGND __m128i _mm_maskz_alignr_epi32( __mmask8 k, __m128i a, __m128i b, int cnt);\r\nVALIGNQ __m512i _mm512_alignr_epi64( __m512i a, __m512i b, int cnt);\r\nVALIGNQ __m512i _mm512_mask_alignr_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b, int cnt);\r\nVALIGNQ __m512i _mm512_maskz_alignr_epi64( __mmask8 k, __m512i a, __m512i b, int cnt);\r\nVALIGNQ __m256i _mm256_mask_alignr_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b, int cnt);\r\nVALIGNQ __m256i _mm256_maskz_alignr_epi64( __mmask8 k, __m256i a, __m256i b, int cnt);\r\nVALIGNQ __m128i _mm_mask_alignr_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b, int cnt);\r\nVALIGNQ __m128i _mm_maskz_alignr_epi64( __mmask8 k, __m128i a, __m128i b, int cnt);\r\n\r\nExceptions\r\nSee Exceptions Type E4NF.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VALIGND"
},
{
"description": "-R:VALIGND",
"mnem": "VALIGNQ"
},
{
"description": "VBLENDMPD/VBLENDMPS-Blend Float64/Float32 Vectors Using an OpMask Control\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.128.66.0F38.W1 65 /r FV V/V AVX512VL Blend double-precision vector xmm2 and double-precision\r\n VBLENDMPD xmm1 {k1}{z}, AVX512F vector xmm3/m128/m64bcst and store the result in xmm1,\r\n xmm2, xmm3/m128/m64bcst under control mask.\r\n EVEX.NDS.256.66.0F38.W1 65 /r FV V/V AVX512VL Blend double-precision vector ymm2 and double-precision\r\n VBLENDMPD ymm1 {k1}{z}, AVX512F vector ymm3/m256/m64bcst and store the result in ymm1,\r\n ymm2, ymm3/m256/m64bcst under control mask.\r\n EVEX.NDS.512.66.0F38.W1 65 /r FV V/V AVX512F Blend double-precision vector zmm2 and double-precision\r\n VBLENDMPD zmm1 {k1}{z}, vector zmm3/m512/m64bcst and store the result in zmm1,\r\n zmm2, zmm3/m512/m64bcst under control mask.\r\n EVEX.NDS.128.66.0F38.W0 65 /r FV V/V AVX512VL Blend single-precision vector xmm2 and single-precision\r\n VBLENDMPS xmm1 {k1}{z}, AVX512F vector xmm3/m128/m32bcst and store the result in xmm1,\r\n xmm2, xmm3/m128/m32bcst under control mask.\r\n EVEX.NDS.256.66.0F38.W0 65 /r FV V/V AVX512VL Blend single-precision vector ymm2 and single-precision\r\n VBLENDMPS ymm1 {k1}{z}, AVX512F vector ymm3/m256/m32bcst and store the result in ymm1,\r\n ymm2, ymm3/m256/m32bcst under control mask.\r\n EVEX.NDS.512.66.0F38.W0 65 /r FV V/V AVX512F Blend single-precision vector zmm2 and single-precision\r\n VBLENDMPS zmm1 {k1}{z}, vector zmm3/m512/m32bcst using k1 as select control and\r\n zmm2, zmm3/m512/m32bcst store the result in zmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms an element-by-element blending between float64/float32 elements in the first source operand (the\r\nsecond operand) with the elements in the second source operand (the third operand) using an opmask register as\r\nselect control. The blended result is written to the destination register.\r\nThe destination and first source operands are ZMM/YMM/XMM registers. The second source operand can be a\r\nZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-\r\nbit memory location.\r\nThe opmask register is not used as a writemask for this instruction. Instead, the mask is used as an element\r\nselector: every element of the destination is conditionally selected between first source or second source using the\r\nvalue of the related mask bit (0 for first source operand, 1 for second source operand).\r\nIf EVEX.z is set, the elements with corresponding mask bit value of 0 in the destination operand are zeroed.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVBLENDMPD (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no controlmask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN\r\n DEST[i+63:i] <- SRC2[63:0]\r\n ELSE\r\n DEST[i+63:i] <- SRC2[i+63:i]\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN DEST[i+63:i] <- SRC1[i+63:i]\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI;\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\nVBLENDMPS (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no controlmask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN\r\n DEST[i+31:i] <- SRC2[31:0]\r\n ELSE\r\n DEST[i+31:i] <- SRC2[i+31:i]\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN DEST[i+31:i] <- SRC1[i+31:i]\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI;\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVBLENDMPD __m512d _mm512_mask_blend_pd(__mmask8 k, __m512d a, __m512d b);\r\nVBLENDMPD __m256d _mm256_mask_blend_pd(__mmask8 k, __m256d a, __m256d b);\r\nVBLENDMPD __m128d _mm_mask_blend_pd(__mmask8 k, __m128d a, __m128d b);\r\nVBLENDMPS __m512 _mm512_mask_blend_ps(__mmask16 k, __m512 a, __m512 b);\r\nVBLENDMPS __m256 _mm256_mask_blend_ps(__mmask8 k, __m256 a, __m256 b);\r\nVBLENDMPS __m128 _mm_mask_blend_ps(__mmask8 k, __m128 a, __m128 b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VBLENDMPD"
},
{
"description": "-R:VBLENDMPD",
"mnem": "VBLENDMPS"
},
{
"description": "VBROADCAST-Load with Broadcast Floating-Point Data\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Feature\r\n Mode Flag\r\n Support\r\n VEX.128.66.0F38.W0 18 /r RM V/V AVX Broadcast single-precision floating-point element in\r\n VBROADCASTSS xmm1, m32 mem to four locations in xmm1.\r\n VEX.256.66.0F38.W0 18 /r RM V/V AVX Broadcast single-precision floating-point element in\r\n VBROADCASTSS ymm1, m32 mem to eight locations in ymm1.\r\n VEX.256.66.0F38.W0 19 /r RM V/V AVX Broadcast double-precision floating-point element in\r\n VBROADCASTSD ymm1, m64 mem to four locations in ymm1.\r\n VEX.256.66.0F38.W0 1A /r RM V/V AVX Broadcast 128 bits of floating-point data in mem to\r\n VBROADCASTF128 ymm1, m128 low and high 128-bits in ymm1.\r\n EVEX.256.66.0F38.W1 19 /r T1S V/V AVX512VL Broadcast low double-precision floating-point element\r\n VBROADCASTSD ymm1 {k1}{z}, AVX512F in xmm2/m64 to four locations in ymm1 using\r\n xmm2/m64 writemask k1.\r\n EVEX.512.66.0F38.W1 19 /r T1S V/V AVX512F Broadcast low double-precision floating-point element\r\n VBROADCASTSD zmm1 {k1}{z}, in xmm2/m64 to eight locations in zmm1 using\r\n xmm2/m64 writemask k1.\r\n EVEX.256.66.0F38.W0 19 /r T2 V/V AVX512VL Broadcast two single-precision floating-point elements\r\n VBROADCASTF32X2 ymm1 {k1}{z}, AVX512DQ in xmm2/m64 to locations in ymm1 using writemask\r\n xmm2/m64 k1.\r\n EVEX.512.66.0F38.W0 19 /r T2 V/V AVX512DQ Broadcast two single-precision floating-point elements\r\n VBROADCASTF32X2 zmm1 {k1}{z}, in xmm2/m64 to locations in zmm1 using writemask\r\n xmm2/m64 k1.\r\n EVEX.128.66.0F38.W0 18 /r T1S V/V AVX512VL Broadcast low single-precision floating-point element\r\n VBROADCASTSS xmm1 {k1}{z}, AVX512F in xmm2/m32 to all locations in xmm1 using\r\n xmm2/m32 writemask k1.\r\n EVEX.256.66.0F38.W0 18 /r T1S V/V AVX512VL Broadcast low single-precision floating-point element\r\n VBROADCASTSS ymm1 {k1}{z}, AVX512F in xmm2/m32 to all locations in ymm1 using\r\n xmm2/m32 writemask k1.\r\n EVEX.512.66.0F38.W0 18 /r T1S V/V AVX512F Broadcast low single-precision floating-point element\r\n VBROADCASTSS zmm1 {k1}{z}, in xmm2/m32 to all locations in zmm1 using\r\n xmm2/m32 writemask k1.\r\n EVEX.256.66.0F38.W0 1A /r T4 V/V AVX512VL Broadcast 128 bits of 4 single-precision floating-point\r\n VBROADCASTF32X4 ymm1 {k1}{z}, AVX512F data in mem to locations in ymm1 using writemask k1.\r\n m128\r\n EVEX.512.66.0F38.W0 1A /r T4 V/V AVX512F Broadcast 128 bits of 4 single-precision floating-point\r\n VBROADCASTF32X4 zmm1 {k1}{z}, data in mem to locations in zmm1 using writemask k1.\r\n m128\r\n EVEX.256.66.0F38.W1 1A /r T2 V/V AVX512VL Broadcast 128 bits of 2 double-precision floating-point\r\n VBROADCASTF64X2 ymm1 {k1}{z}, AVX512DQ data in mem to locations in ymm1 using writemask k1.\r\n m128\r\n EVEX.512.66.0F38.W1 1A /r T2 V/V AVX512DQ Broadcast 128 bits of 2 double-precision floating-point\r\n VBROADCASTF64X2 zmm1 {k1}{z}, data in mem to locations in zmm1 using writemask k1.\r\n m128\r\n EVEX.512.66.0F38.W0 1B /r T8 V/V AVX512DQ Broadcast 256 bits of 8 single-precision floating-point\r\n VBROADCASTF32X8 zmm1 {k1}{z}, data in mem to locations in zmm1 using writemask k1.\r\n m256\r\n EVEX.512.66.0F38.W1 1B /r T4 V/V AVX512F Broadcast 256 bits of 4 double-precision floating-point\r\n VBROADCASTF64X4 zmm1 {k1}{z}, data in mem to locations in zmm1 using writemask k1.\r\n m256\r\n\r\n\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n T1S, T2, T4, T8 ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nVBROADCASTSD/VBROADCASTSS/VBROADCASTF128 load floating-point values as one tuple from the source\r\noperand (second operand) in memory and broadcast to all elements of the destination operand (first operand).\r\n VEX256-encoded versions: The destination operand is a YMM register. The source operand is either a 32-bit,\r\n 64-bit, or 128-bit memory location. Register source encodings are reserved and will #UD. Bits (MAX_VL-\r\n 1:256) of the destination register are zeroed.\r\n EVEX-encoded versions: The destination operand is a ZMM/YMM/XMM register and updated according to the\r\n writemask k1. The source operand is either a 32-bit, 64-bit memory location or the low\r\n doubleword/quadword element of an XMM register.\r\nVBROADCASTF32X2/VBROADCASTF32X4/VBROADCASTF64X2/VBROADCASTF32X8/VBROADCASTF64X4 load\r\nfloating-point values as tuples from the source operand (the second operand) in memory or register and broadcast\r\nto all elements of the destination operand (the first operand). The destination operand is a YMM/ZMM register\r\nupdated according to the writemask k1. The source operand is either a register or 64-bit/128-bit/256-bit memory\r\nlocation.\r\nVBROADCASTSD and VBROADCASTF128,F32x4 and F64x2 are only supported as 256-bit and 512-bit wide\r\nversions and up. VBROADCASTSS is supported in 128-bit, 256-bit and 512-bit wide versions. F32x8 and F64x4 are\r\nonly supported as 512-bit wide versions.\r\nVBROADCASTF32X2/VBROADCASTF32X4/VBROADCASTF32X8 have 32-bit granularity. VBROADCASTF64X2 and\r\nVBROADCASTF64X4 have 64-bit granularity.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\nIf VBROADCASTSD or VBROADCASTF128 is encoded with VEX.L= 0, an attempt to execute the instruction encoded\r\nwith VEX.L= 0 will cause an #UD exception.\r\n\r\n\r\n\r\n\r\n m32 X0\r\n\r\n\r\n\r\n\r\n DEST X0 X0 X0 X0 X0 X0 X0 X0\r\n\r\n\r\n Figure 5-1. VBROADCASTSS Operation (VEX.256 encoded version)\r\n\r\n\r\n\r\n\r\n m32 X0\r\n\r\n\r\n\r\n\r\n DEST 0 0 0 0 X0 X0 X0 X0\r\n\r\n\r\n Figure 5-2. VBROADCASTSS Operation (VEX.128-bit version)\r\n\r\n\r\n\r\n m64 X0\r\n\r\n\r\n\r\n\r\n DEST X0 X0 X0 X0\r\n\r\n\r\n Figure 5-3. VBROADCASTSD Operation (VEX.256-bit version)\r\n\r\n\r\n\r\n\r\n m128 X0\r\n\r\n\r\n\r\n\r\n DEST X0 X0\r\n\r\n\r\n Figure 5-4. VBROADCASTF128 Operation (VEX.256-bit version)\r\n\r\n\r\n\r\n\r\n m256 X0\r\n\r\n\r\n\r\n\r\n DEST X0 X0\r\n\r\n\r\n Figure 5-5. VBROADCASTF64X4 Operation (512-bit version with writemask all 1s)\r\n\r\n\r\nOperation\r\nVBROADCASTSS (128 bit version VEX and legacy)\r\ntemp <- SRC[31:0]\r\nDEST[31:0] <- temp\r\nDEST[63:32] <- temp\r\nDEST[95:64] <- temp\r\nDEST[127:96] <- temp\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVBROADCASTSS (VEX.256 encoded version)\r\ntemp <- SRC[31:0]\r\nDEST[31:0] <- temp\r\nDEST[63:32] <- temp\r\nDEST[95:64] <- temp\r\nDEST[127:96] <- temp\r\nDEST[159:128] <- temp\r\nDEST[191:160] <- temp\r\nDEST[223:192] <- temp\r\nDEST[255:224] <- temp\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVBROADCASTSS (EVEX encoded versions)\r\n(KL, VL) (4, 128), (8, 256),= (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <-j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- SRC[31:0]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVBROADCASTSD (VEX.256 encoded version)\r\ntemp <- SRC[63:0]\r\nDEST[63:0] <- temp\r\nDEST[127:64] <- temp\r\nDEST[191:128] <- temp\r\nDEST[255:192] <- temp\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVBROADCASTSD (EVEX encoded versions)\r\n(KL, VL) = (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <-j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- SRC[63:0]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVBROADCASTF32x2 (EVEX encoded versions)\r\n(KL, VL) = (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n n <- (j mod 2) * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- SRC[n+31:n]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVBROADCASTF128 (VEX.256 encoded version)\r\ntemp <- SRC[127:0]\r\nDEST[127:0] <- temp\r\nDEST[255:128] <- temp\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVBROADCASTF32X4 (EVEX encoded versions)\r\n(KL, VL) = (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j* 32\r\n n <- (j modulo 4) * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- SRC[n+31:n]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVBROADCASTF64X2 (EVEX encoded versions)\r\n(KL, VL) = (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n n <-(j modulo 2) * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- SRC[n+63:n]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] = 0\r\n FI\r\n FI;\r\nENDFOR;\r\n\r\nVBROADCASTF32X8 (EVEX.U1.512 encoded version)\r\nFOR j <- 0 TO 15\r\n i <- j * 32\r\n n <-(j modulo 8) * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- SRC[n+31:n]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVBROADCASTF64X4 (EVEX.512 encoded version)\r\nFOR j <- 0 TO 7\r\n i <- j * 64\r\n n <- (j modulo 4) * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- SRC[n+63:n]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVBROADCASTF32x2 __m512 _mm512_broadcast_f32x2( __m128 a);\r\nVBROADCASTF32x2 __m512 _mm512_mask_broadcast_f32x2(__m512 s, __mmask16 k, __m128 a);\r\nVBROADCASTF32x2 __m512 _mm512_maskz_broadcast_f32x2( __mmask16 k, __m128 a);\r\nVBROADCASTF32x2 __m256 _mm256_broadcast_f32x2( __m128 a);\r\nVBROADCASTF32x2 __m256 _mm256_mask_broadcast_f32x2(__m256 s, __mmask8 k, __m128 a);\r\nVBROADCASTF32x2 __m256 _mm256_maskz_broadcast_f32x2( __mmask8 k, __m128 a);\r\nVBROADCASTF32x4 __m512 _mm512_broadcast_f32x4( __m128 a);\r\nVBROADCASTF32x4 __m512 _mm512_mask_broadcast_f32x4(__m512 s, __mmask16 k, __m128 a);\r\nVBROADCASTF32x4 __m512 _mm512_maskz_broadcast_f32x4( __mmask16 k, __m128 a);\r\nVBROADCASTF32x4 __m256 _mm256_broadcast_f32x4( __m128 a);\r\nVBROADCASTF32x4 __m256 _mm256_mask_broadcast_f32x4(__m256 s, __mmask8 k, __m128 a);\r\nVBROADCASTF32x4 __m256 _mm256_maskz_broadcast_f32x4( __mmask8 k, __m128 a);\r\nVBROADCASTF32x8 __m512 _mm512_broadcast_f32x8( __m256 a);\r\nVBROADCASTF32x8 __m512 _mm512_mask_broadcast_f32x8(__m512 s, __mmask16 k, __m256 a);\r\nVBROADCASTF32x8 __m512 _mm512_maskz_broadcast_f32x8( __mmask16 k, __m256 a);\r\nVBROADCASTF64x2 __m512d _mm512_broadcast_f64x2( __m128d a);\r\nVBROADCASTF64x2 __m512d _mm512_mask_broadcast_f64x2(__m512d s, __mmask8 k, __m128d a);\r\nVBROADCASTF64x2 __m512d _mm512_maskz_broadcast_f64x2( __mmask8 k, __m128d a);\r\nVBROADCASTF64x2 __m256d _mm256_broadcast_f64x2( __m128d a);\r\nVBROADCASTF64x2 __m256d _mm256_mask_broadcast_f64x2(__m256d s, __mmask8 k, __m128d a);\r\nVBROADCASTF64x2 __m256d _mm256_maskz_broadcast_f64x2( __mmask8 k, __m128d a);\r\nVBROADCASTF64x4 __m512d _mm512_broadcast_f64x4( __m256d a);\r\nVBROADCASTF64x4 __m512d _mm512_mask_broadcast_f64x4(__m512d s, __mmask8 k, __m256d a);\r\nVBROADCASTF64x4 __m512d _mm512_maskz_broadcast_f64x4( __mmask8 k, __m256d a);\r\nVBROADCASTSD __m512d _mm512_broadcastsd_pd( __m128d a);\r\nVBROADCASTSD __m512d _mm512_mask_broadcastsd_pd(__m512d s, __mmask8 k, __m128d a);\r\nVBROADCASTSD __m512d _mm512_maskz_broadcastsd_pd(__mmask8 k, __m128d a);\r\nVBROADCASTSD __m256d _mm256_broadcastsd_pd(__m128d a);\r\nVBROADCASTSD __m256d _mm256_mask_broadcastsd_pd(__m256d s, __mmask8 k, __m128d a);\r\nVBROADCASTSD __m256d _mm256_maskz_broadcastsd_pd( __mmask8 k, __m128d a);\r\nVBROADCASTSD __m256d _mm256_broadcast_sd(double *a);\r\nVBROADCASTSS __m512 _mm512_broadcastss_ps( __m128 a);\r\nVBROADCASTSS __m512 _mm512_mask_broadcastss_ps(__m512 s, __mmask16 k, __m128 a);\r\nVBROADCASTSS __m512 _mm512_maskz_broadcastss_ps( __mmask16 k, __m128 a);\r\nVBROADCASTSS __m256 _mm256_broadcastss_ps(__m128 a);\r\nVBROADCASTSS __m256 _mm256_mask_broadcast_ss(__m256 s, __mmask8 k, __m128 a);\r\nVBROADCASTSS __m256 _mm256_maskz_broadcast_ss( __mmask8 k, __m128 a);\r\nVBROADCASTSS __m128 _mm_broadcastss_ps(__m128 a);\r\nVBROADCASTSS __m128 _mm_mask_broadcast_ss(__m128 s, __mmask8 k, __m128 a);\r\nVBROADCASTSS __m128 _mm_maskz_broadcast_ss( __mmask8 k, __m128 a);\r\nVBROADCASTSS __m128 _mm_broadcast_ss(float *a);\r\nVBROADCASTSS __m256 _mm256_broadcast_ss(float *a);\r\nVBROADCASTF128 __m256 _mm256_broadcast_ps(__m128 * a);\r\nVBROADCASTF128 __m256d _mm256_broadcast_pd(__m128d * a);\r\n\r\nExceptions\r\nVEX-encoded instructions, see Exceptions Type 6;\r\nEVEX-encoded instructions, see Exceptions Type E6.\r\n#UD If VEX.L = 0 for VBROADCASTSD or VBROADCASTF128.\r\n If EVEX.L'L = 0 for VBROADCASTSD/VBROADCASTF32X2/VBROADCASTF32X4/VBROADCASTF64X2.\r\n If EVEX.L'L < 10b for VBROADCASTF32X8/VBROADCASTF64X4.\r\n\r\n\r\n\r\n",
"mnem": "VBROADCAST"
},
{
"description": "VCOMPRESSPD-Store Sparse Packed Double-Precision Floating-Point Values into Dense\r\nMemory\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F38.W1 8A /r T1S V/V AVX512VL Compress packed double-precision floating-point\r\n VCOMPRESSPD xmm1/m128 {k1}{z}, AVX512F values from xmm2 to xmm1/m128 using writemask\r\n xmm2 k1.\r\n EVEX.256.66.0F38.W1 8A /r T1S V/V AVX512VL Compress packed double-precision floating-point\r\n VCOMPRESSPD ymm1/m256 {k1}{z}, AVX512F values from ymm2 to ymm1/m256 using writemask\r\n ymm2 k1.\r\n EVEX.512.66.0F38.W1 8A /r T1S V/V AVX512F Compress packed double-precision floating-point\r\n VCOMPRESSPD zmm1/m512 {k1}{z}, values from zmm2 using control mask k1 to\r\n zmm2 zmm1/m512.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\nDescription\r\nCompress (store) up to 8 double-precision floating-point values from the source operand (the second operand) as\r\na contiguous vector to the destination operand (the first operand) The source operand is a ZMM/YMM/XMM register,\r\nthe destination operand can be a ZMM/YMM/XMM register or a 512/256/128-bit memory location.\r\nThe opmask register k1 selects the active elements (partial vector or possibly non-contiguous if less than 8 active\r\nelements) from the source operand to compress into a contiguous vector. The contiguous vector is written to the\r\ndestination starting from the low element of the destination operand.\r\nMemory destination version: Only the contiguous vector is written to the destination memory location. EVEX.z\r\nmust be zero.\r\nRegister destination version: If the vector length of the contiguous vector is less than that of the input vector in the\r\nsource operand, the upper bits of the destination register are unmodified if EVEX.z is not set, otherwise the upper\r\nbits are zeroed.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\nNote that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element\r\ninstead of the size of the full vector.\r\n\r\nOperation\r\nVCOMPRESSPD (EVEX encoded versions) store form\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nSIZE <- 64\r\nk<-0\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n DEST[k+SIZE-1:k]<- SRC[i+63:i]\r\n k <- k + SIZE\r\n FI;\r\nENDFOR\r\n\r\n\r\n\r\n\r\n\r\nVCOMPRESSPD (EVEX encoded versions) reg-reg form\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nSIZE <- 64\r\nk<-0\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n DEST[k+SIZE-1:k]<- SRC[i+63:i]\r\n k <- k + SIZE\r\n FI;\r\nENDFOR\r\nIF *merging-masking*\r\n THEN *DEST[VL-1:k] remains unchanged*\r\n ELSE DEST[VL-1:k] <- 0\r\nFI\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCOMPRESSPD __m512d _mm512_mask_compress_pd( __m512d s, __mmask8 k, __m512d a);\r\nVCOMPRESSPD __m512d _mm512_maskz_compress_pd( __mmask8 k, __m512d a);\r\nVCOMPRESSPD void _mm512_mask_compressstoreu_pd( void * d, __mmask8 k, __m512d a);\r\nVCOMPRESSPD __m256d _mm256_mask_compress_pd( __m256d s, __mmask8 k, __m256d a);\r\nVCOMPRESSPD __m256d _mm256_maskz_compress_pd( __mmask8 k, __m256d a);\r\nVCOMPRESSPD void _mm256_mask_compressstoreu_pd( void * d, __mmask8 k, __m256d a);\r\nVCOMPRESSPD __m128d _mm_mask_compress_pd( __m128d s, __mmask8 k, __m128d a);\r\nVCOMPRESSPD __m128d _mm_maskz_compress_pd( __mmask8 k, __m128d a);\r\nVCOMPRESSPD void _mm_mask_compressstoreu_pd( void * d, __mmask8 k, __m128d a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nEVEX-encoded instructions, see Exceptions Type E4.nb.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VCOMPRESSPD"
},
{
"description": "VCOMPRESSPS-Store Sparse Packed Single-Precision Floating-Point Values into Dense Memory\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F38.W0 8A /r T1S V/V AVX512VL Compress packed single-precision floating-point\r\n VCOMPRESSPS xmm1/m128 {k1}{z}, AVX512F values from xmm2 to xmm1/m128 using writemask\r\n xmm2 k1.\r\n EVEX.256.66.0F38.W0 8A /r T1S V/V AVX512VL Compress packed single-precision floating-point\r\n VCOMPRESSPS ymm1/m256 {k1}{z}, AVX512F values from ymm2 to ymm1/m256 using writemask\r\n ymm2 k1.\r\n EVEX.512.66.0F38.W0 8A /r T1S V/V AVX512F Compress packed single-precision floating-point\r\n VCOMPRESSPS zmm1/m512 {k1}{z}, values from zmm2 using control mask k1 to\r\n zmm2 zmm1/m512.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\nDescription\r\nCompress (stores) up to 16 single-precision floating-point values from the source operand (the second operand) to\r\nthe destination operand (the first operand). The source operand is a ZMM/YMM/XMM register, the destination\r\noperand can be a ZMM/YMM/XMM register or a 512/256/128-bit memory location.\r\nThe opmask register k1 selects the active elements (a partial vector or possibly non-contiguous if less than 16\r\nactive elements) from the source operand to compress into a contiguous vector. The contiguous vector is written to\r\nthe destination starting from the low element of the destination operand.\r\nMemory destination version: Only the contiguous vector is written to the destination memory location. EVEX.z\r\nmust be zero.\r\nRegister destination version: If the vector length of the contiguous vector is less than that of the input vector in the\r\nsource operand, the upper bits of the destination register are unmodified if EVEX.z is not set, otherwise the upper\r\nbits are zeroed.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\nNote that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element\r\ninstead of the size of the full vector.\r\n\r\nOperation\r\nVCOMPRESSPS (EVEX encoded versions) store form\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nSIZE <- 32\r\nk<-0\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n DEST[k+SIZE-1:k]<- SRC[i+31:i]\r\n k <- k + SIZE\r\n FI;\r\nENDFOR;\r\n\r\n\r\n\r\n\r\n\r\nVCOMPRESSPS (EVEX encoded versions) reg-reg form\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nSIZE <- 32\r\nk<-0\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n DEST[k+SIZE-1:k]<- SRC[i+31:i]\r\n k <- k + SIZE\r\n FI;\r\nENDFOR\r\nIF *merging-masking*\r\n THEN *DEST[VL-1:k] remains unchanged*\r\n ELSE DEST[VL-1:k] <- 0\r\nFI\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCOMPRESSPS __m512 _mm512_mask_compress_ps( __m512 s, __mmask16 k, __m512 a);\r\nVCOMPRESSPS __m512 _mm512_maskz_compress_ps( __mmask16 k, __m512 a);\r\nVCOMPRESSPS void _mm512_mask_compressstoreu_ps( void * d, __mmask16 k, __m512 a);\r\nVCOMPRESSPS __m256 _mm256_mask_compress_ps( __m256 s, __mmask8 k, __m256 a);\r\nVCOMPRESSPS __m256 _mm256_maskz_compress_ps( __mmask8 k, __m256 a);\r\nVCOMPRESSPS void _mm256_mask_compressstoreu_ps( void * d, __mmask8 k, __m256 a);\r\nVCOMPRESSPS __m128 _mm_mask_compress_ps( __m128 s, __mmask8 k, __m128 a);\r\nVCOMPRESSPS __m128 _mm_maskz_compress_ps( __mmask8 k, __m128 a);\r\nVCOMPRESSPS void _mm_mask_compressstoreu_ps( void * d, __mmask8 k, __m128 a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nEVEX-encoded instructions, see Exceptions Type E4.nb.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VCOMPRESSPS"
},
{
"description": "VCVTPD2QQ-Convert Packed Double-Precision Floating-Point Values to Packed Quadword\r\nIntegers\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F.W1 7B /r FV V/V AVX512VL Convert two packed double-precision floating-point values from\r\n VCVTPD2QQ xmm1 {k1}{z}, AVX512DQ xmm2/m128/m64bcst to two packed quadword integers in\r\n xmm2/m128/m64bcst xmm1 with writemask k1.\r\n EVEX.256.66.0F.W1 7B /r FV V/V AVX512VL Convert four packed double-precision floating-point values from\r\n VCVTPD2QQ ymm1 {k1}{z}, AVX512DQ ymm2/m256/m64bcst to four packed quadword integers in\r\n ymm2/m256/m64bcst ymm1 with writemask k1.\r\n EVEX.512.66.0F.W1 7B /r FV V/V AVX512DQ Convert eight packed double-precision floating-point values\r\n VCVTPD2QQ zmm1 {k1}{z}, from zmm2/m512/m64bcst to eight packed quadword integers\r\n zmm2/m512/m64bcst{er} in zmm1 with writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts packed double-precision floating-point values in the source operand (second operand) to packed quad-\r\nword integers in the destination operand (first operand).\r\nEVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location.\r\nThe destination operation is a ZMM/YMM/XMM register conditionally updated with writemask k1.\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR\r\nregister or the embedded rounding control bits. If a converted result cannot be represented in the destination\r\nformat, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value\r\n(2w-1, where w represents the number of bits in the destination format) is returned.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVCVTPD2QQ (EVEX encoded version) when src operand is a register\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL == 512) AND (EVEX.b == 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <-\r\n Convert_Double_Precision_Floating_Point_To_QuadInteger(SRC[i+63:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVCVTPD2QQ (EVEX encoded version) when src operand is a memory source\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b == 1)\r\n THEN\r\n DEST[i+63:i] <- Convert_Double_Precision_Floating_Point_To_QuadInteger(SRC[63:0])\r\n ELSE\r\n DEST[i+63:i] <- Convert_Double_Precision_Floating_Point_To_QuadInteger(SRC[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTPD2QQ __m512i _mm512_cvtpd_epi64( __m512d a);\r\nVCVTPD2QQ __m512i _mm512_mask_cvtpd_epi64( __m512i s, __mmask8 k, __m512d a);\r\nVCVTPD2QQ __m512i _mm512_maskz_cvtpd_epi64( __mmask8 k, __m512d a);\r\nVCVTPD2QQ __m512i _mm512_cvt_roundpd_epi64( __m512d a, int r);\r\nVCVTPD2QQ __m512i _mm512_mask_cvt_roundpd_epi64( __m512i s, __mmask8 k, __m512d a, int r);\r\nVCVTPD2QQ __m512i _mm512_maskz_cvt_roundpd_epi64( __mmask8 k, __m512d a, int r);\r\nVCVTPD2QQ __m256i _mm256_mask_cvtpd_epi64( __m256i s, __mmask8 k, __m256d a);\r\nVCVTPD2QQ __m256i _mm256_maskz_cvtpd_epi64( __mmask8 k, __m256d a);\r\nVCVTPD2QQ __m128i _mm_mask_cvtpd_epi64( __m128i s, __mmask8 k, __m128d a);\r\nVCVTPD2QQ __m128i _mm_maskz_cvtpd_epi64( __mmask8 k, __m128d a);\r\nVCVTPD2QQ __m256i _mm256_cvtpd_epi64 (__m256d src)\r\nVCVTPD2QQ __m128i _mm_cvtpd_epi64 (__m128d src)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nEVEX-encoded instructions, see Exceptions Type E2\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VCVTPD2QQ"
},
{
"description": "VCVTPD2UDQ-Convert Packed Double-Precision Floating-Point Values to Packed Unsigned\r\nDoubleword Integers\r\n Opcode Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.0F.W1 79 /r FV V/V AVX512VL Convert two packed double-precision floating-point\r\n VCVTPD2UDQ xmm1 {k1}{z}, AVX512F values in xmm2/m128/m64bcst to two unsigned\r\n xmm2/m128/m64bcst doubleword integers in xmm1 subject to writemask k1.\r\n EVEX.256.0F.W1 79 /r FV V/V AVX512VL Convert four packed double-precision floating-point\r\n VCVTPD2UDQ xmm1 {k1}{z}, AVX512F values in ymm2/m256/m64bcst to four unsigned\r\n ymm2/m256/m64bcst doubleword integers in xmm1 subject to writemask k1.\r\n EVEX.512.0F.W1 79 /r FV V/V AVX512F Convert eight packed double-precision floating-point\r\n VCVTPD2UDQ ymm1 {k1}{z}, values in zmm2/m512/m64bcst to eight unsigned\r\n zmm2/m512/m64bcst{er} doubleword integers in ymm1 subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts packed double-precision floating-point values in the source operand (the second operand) to packed\r\nunsigned doubleword integers in the destination operand (the first operand).\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR\r\nregister or the embedded rounding control bits. If a converted result cannot be represented in the destination\r\nformat, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w - 1 is\r\nreturned, where w represents the number of bits in the destination format.\r\nThe source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector\r\nbroadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally\r\nupdated with writemask k1. The upper bits (MAX_VL-1:256) of the corresponding destination are zeroed.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVCVTPD2UDQ (EVEX encoded versions) when src2 operand is a register\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n k <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n DEST[i+31:i] <-\r\n Convert_Double_Precision_Floating_Point_To_UInteger(SRC[k+63:k])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL/2] <- 0\r\n\r\nVCVTPD2UDQ (EVEX encoded versions) when src operand is a memory source\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n k <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n Convert_Double_Precision_Floating_Point_To_UInteger(SRC[63:0])\r\n ELSE\r\n DEST[i+31:i] <-\r\n Convert_Double_Precision_Floating_Point_To_UInteger(SRC[k+63:k])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL/2] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTPD2UDQ __m256i _mm512_cvtpd_epu32( __m512d a);\r\nVCVTPD2UDQ __m256i _mm512_mask_cvtpd_epu32( __m256i s, __mmask8 k, __m512d a);\r\nVCVTPD2UDQ __m256i _mm512_maskz_cvtpd_epu32( __mmask8 k, __m512d a);\r\nVCVTPD2UDQ __m256i _mm512_cvt_roundpd_epu32( __m512d a, int r);\r\nVCVTPD2UDQ __m256i _mm512_mask_cvt_roundpd_epu32( __m256i s, __mmask8 k, __m512d a, int r);\r\nVCVTPD2UDQ __m256i _mm512_maskz_cvt_roundpd_epu32( __mmask8 k, __m512d a, int r);\r\nVCVTPD2UDQ __m128i _mm256_mask_cvtpd_epu32( __m128i s, __mmask8 k, __m256d a);\r\nVCVTPD2UDQ __m128i _mm256_maskz_cvtpd_epu32( __mmask8 k, __m256d a);\r\nVCVTPD2UDQ __m128i _mm_mask_cvtpd_epu32( __m128i s, __mmask8 k, __m128d a);\r\nVCVTPD2UDQ __m128i _mm_maskz_cvtpd_epu32( __mmask8 k, __m128d a);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VCVTPD2UDQ"
},
{
"description": "VCVTPD2UQQ-Convert Packed Double-Precision Floating-Point Values to Packed Unsigned\r\nQuadword Integers\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F.W1 79 /r FV V/V AVX512VL Convert two packed double-precision floating-point values from\r\n VCVTPD2UQQ xmm1 {k1}{z}, AVX512DQ xmm2/mem to two packed unsigned quadword integers in\r\n xmm2/m128/m64bcst xmm1 with writemask k1.\r\n EVEX.256.66.0F.W1 79 /r FV V/V AVX512VL Convert fourth packed double-precision floating-point values\r\n VCVTPD2UQQ ymm1 {k1}{z}, AVX512DQ from ymm2/mem to four packed unsigned quadword integers\r\n ymm2/m256/m64bcst in ymm1 with writemask k1.\r\n EVEX.512.66.0F.W1 79 /r FV V/V AVX512DQ Convert eight packed double-precision floating-point values\r\n VCVTPD2UQQ zmm1 {k1}{z}, from zmm2/mem to eight packed unsigned quadword integers\r\n zmm2/m512/m64bcst{er} in zmm1 with writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts packed double-precision floating-point values in the source operand (second operand) to packed\r\nunsigned quadword integers in the destination operand (first operand).\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR\r\nregister or the embedded rounding control bits. If a converted result cannot be represented in the destination\r\nformat, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w - 1 is\r\nreturned, where w represents the number of bits in the destination format.\r\nThe source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operation\r\nis a ZMM/YMM/XMM register conditionally updated with writemask k1.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVCVTPD2UQQ (EVEX encoded versions) when src operand is a register\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL == 512) AND (EVEX.b == 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <-\r\n Convert_Double_Precision_Floating_Point_To_UQuadInteger(SRC[i+63:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVCVTPD2UQQ (EVEX encoded versions) when src operand is a memory source\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b == 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n Convert_Double_Precision_Floating_Point_To_UQuadInteger(SRC[63:0])\r\n ELSE\r\n DEST[i+63:i] <-\r\n Convert_Double_Precision_Floating_Point_To_UQuadInteger(SRC[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTPD2UQQ __m512i _mm512_cvtpd_epu64( __m512d a);\r\nVCVTPD2UQQ __m512i _mm512_mask_cvtpd_epu64( __m512i s, __mmask8 k, __m512d a);\r\nVCVTPD2UQQ __m512i _mm512_maskz_cvtpd_epu64( __mmask8 k, __m512d a);\r\nVCVTPD2UQQ __m512i _mm512_cvt_roundpd_epu64( __m512d a, int r);\r\nVCVTPD2UQQ __m512i _mm512_mask_cvt_roundpd_epu64( __m512i s, __mmask8 k, __m512d a, int r);\r\nVCVTPD2UQQ __m512i _mm512_maskz_cvt_roundpd_epu64( __mmask8 k, __m512d a, int r);\r\nVCVTPD2UQQ __m256i _mm256_mask_cvtpd_epu64( __m256i s, __mmask8 k, __m256d a);\r\nVCVTPD2UQQ __m256i _mm256_maskz_cvtpd_epu64( __mmask8 k, __m256d a);\r\nVCVTPD2UQQ __m128i _mm_mask_cvtpd_epu64( __m128i s, __mmask8 k, __m128d a);\r\nVCVTPD2UQQ __m128i _mm_maskz_cvtpd_epu64( __mmask8 k, __m128d a);\r\nVCVTPD2UQQ __m256i _mm256_cvtpd_epu64 (__m256d src)\r\nVCVTPD2UQQ __m128i _mm_cvtpd_epu64 (__m128d src)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nEVEX-encoded instructions, see Exceptions Type E2\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VCVTPD2UQQ"
},
{
"description": "VCVTPH2PS-Convert 16-bit FP values to Single-Precision FP values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.128.66.0F38.W0 13 /r RM V/V F16C Convert four packed half precision (16-bit) floating-\r\n VCVTPH2PS xmm1, xmm2/m64 point values in xmm2/m64 to packed single-precision\r\n floating-point value in xmm1.\r\n VEX.256.66.0F38.W0 13 /r RM V/V F16C Convert eight packed half precision (16-bit) floating-\r\n VCVTPH2PS ymm1, xmm2/m128 point values in xmm2/m128 to packed single-\r\n precision floating-point value in ymm1.\r\n EVEX.128.66.0F38.W0 13 /r HVM V/V AVX512VL Convert four packed half precision (16-bit) floating-\r\n VCVTPH2PS xmm1 {k1}{z}, xmm2/m64 AVX512F point values in xmm2/m64 to packed single-precision\r\n floating-point values in xmm1.\r\n EVEX.256.66.0F38.W0 13 /r HVM V/V AVX512VL Convert eight packed half precision (16-bit) floating-\r\n VCVTPH2PS ymm1 {k1}{z}, AVX512F point values in xmm2/m128 to packed single-\r\n xmm2/m128 precision floating-point values in ymm1.\r\n EVEX.512.66.0F38.W0 13 /r HVM V/V AVX512F Convert sixteen packed half precision (16-bit)\r\n VCVTPH2PS zmm1 {k1}{z}, floating-point values in ymm2/m256 to packed\r\n ymm2/m256 {sae} single-precision floating-point values in zmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n HVM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts packed half precision (16-bits) floating-point values in the low-order bits of the source operand (the\r\nsecond operand) to packed single-precision floating-point values and writes the converted values into the destina-\r\ntion operand (the first operand).\r\nIf case of a denormal operand, the correct normal result is returned. MXCSR.DAZ is ignored and is treated as if it\r\n0. No denormal exception is reported on MXCSR.\r\nVEX.128 version: The source operand is a XMM register or 64-bit memory location. The destination operand is a\r\nXMM register. The upper bits (MAX_VL-1:128) of the corresponding destination register are zeroed.\r\nVEX.256 version: The source operand is a XMM register or 128-bit memory location. The destination operand is a\r\nYMM register. Bits (MAX_VL-1:256) of the corresponding destination register are zeroed.\r\nEVEX encoded versions: The source operand is a YMM/XMM/XMM (low 64-bits) register or a 256/128/64-bit\r\nmemory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.\r\nThe diagram below illustrates how data is converted from four packed half precision (in 64 bits) to four single preci-\r\nsion (in 128 bits) FP values.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved (must be 1111b).\r\n\r\n\r\n\r\n\r\n\r\n VCVTPH2PS xmm1, xmm2/mem64, imm8\r\n 127 96 95 64 63 48 47 32 31 16 15 0\r\n VH3 VH2 VH1 VH0 xmm2/mem64\r\n\r\n\r\n\r\n\r\n convert convert\r\n convert convert\r\n\r\n\r\n 127 96 95 64 63 32 31 0\r\n VS3 VS2 VS1 VS0 xmm1\r\n\r\n\r\n Figure 5-6. VCVTPH2PS (128-bit Version)\r\n\r\n\r\nOperation\r\nvCvt_h2s(SRC1[15:0])\r\n{\r\nRETURN Cvt_Half_Precision_To_Single_Precision(SRC1[15:0]);\r\n}\r\n\r\nVCVTPH2PS (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n k <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <-\r\n vCvt_h2s(SRC[k+15:k])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVCVTPH2PS (VEX.256 encoded version)\r\nDEST[31:0] <-vCvt_h2s(SRC1[15:0]);\r\nDEST[63:32] <-vCvt_h2s(SRC1[31:16]);\r\nDEST[95:64] <-vCvt_h2s(SRC1[47:32]);\r\nDEST[127:96] <-vCvt_h2s(SRC1[63:48]);\r\nDEST[159:128] <-vCvt_h2s(SRC1[79:64]);\r\nDEST[191:160] <-vCvt_h2s(SRC1[95:80]);\r\nDEST[223:192] <-vCvt_h2s(SRC1[111:96]);\r\nDEST[255:224] <-vCvt_h2s(SRC1[127:112]);\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVCVTPH2PS (VEX.128 encoded version)\r\nDEST[31:0] <-vCvt_h2s(SRC1[15:0]);\r\nDEST[63:32] <-vCvt_h2s(SRC1[31:16]);\r\nDEST[95:64] <-vCvt_h2s(SRC1[47:32]);\r\nDEST[127:96] <-vCvt_h2s(SRC1[63:48]);\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nFlags Affected\r\nNone\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTPH2PS __m512 _mm512_cvtph_ps( __m256i a);\r\nVCVTPH2PS __m512 _mm512_mask_cvtph_ps(__m512 s, __mmask16 k, __m256i a);\r\nVCVTPH2PS __m512 _mm512_maskz_cvtph_ps(__mmask16 k, __m256i a);\r\nVCVTPH2PS __m512 _mm512_cvt_roundph_ps( __m256i a, int sae);\r\nVCVTPH2PS __m512 _mm512_mask_cvt_roundph_ps(__m512 s, __mmask16 k, __m256i a, int sae);\r\nVCVTPH2PS __m512 _mm512_maskz_cvt_roundph_ps( __mmask16 k, __m256i a, int sae);\r\nVCVTPH2PS __m256 _mm256_mask_cvtph_ps(__m256 s, __mmask8 k, __m128i a);\r\nVCVTPH2PS __m256 _mm256_maskz_cvtph_ps(__mmask8 k, __m128i a);\r\nVCVTPH2PS __m128 _mm_mask_cvtph_ps(__m128 s, __mmask8 k, __m128i a);\r\nVCVTPH2PS __m128 _mm_maskz_cvtph_ps(__mmask8 k, __m128i a);\r\nVCVTPH2PS __m128 _mm_cvtph_ps ( __m128i m1);\r\nVCVTPH2PS __m256 _mm256_cvtph_ps ( __m128i m1)\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 11 (do not report #AC);\r\nEVEX-encoded instructions, see Exceptions Type E11.\r\n#UD If VEX.W=1.\r\n#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VCVTPH2PS"
},
{
"description": "VCVTPS2PH-Convert Single-Precision FP value to 16-bit FP value\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.128.66.0F3A.W0 1D /r ib MRI V/V F16C Convert four packed single-precision floating-point values\r\n VCVTPS2PH xmm1/m64, xmm2, in xmm2 to packed half-precision (16-bit) floating-point\r\n imm8 values in xmm1/m64. Imm8 provides rounding controls.\r\n VEX.256.66.0F3A.W0 1D /r ib MRI V/V F16C Convert eight packed single-precision floating-point values\r\n VCVTPS2PH xmm1/m128, ymm2, in ymm2 to packed half-precision (16-bit) floating-point\r\n imm8 values in xmm1/m128. Imm8 provides rounding controls.\r\n EVEX.128.66.0F3A.W0 1D /r ib HVM V/V AVX512VL Convert four packed single-precision floating-point values\r\n VCVTPS2PH xmm1/m64 {k1}{z}, AVX512F in xmm2 to packed half-precision (16-bit) floating-point\r\n xmm2, imm8 values in xmm1/m64. Imm8 provides rounding controls.\r\n EVEX.256.66.0F3A.W0 1D /r ib HVM V/V AVX512VL Convert eight packed single-precision floating-point values\r\n VCVTPS2PH xmm1/m128 {k1}{z}, AVX512F in ymm2 to packed half-precision (16-bit) floating-point\r\n ymm2, imm8 values in xmm1/m128. Imm8 provides rounding controls.\r\n EVEX.512.66.0F3A.W0 1D /r ib HVM V/V AVX512F Convert sixteen packed single-precision floating-point\r\n VCVTPS2PH ymm1/m256 {k1}{z}, values in zmm2 to packed half-precision (16-bit) floating-\r\n zmm2{sae}, imm8 point values in ymm1/m256. Imm8 provides rounding\r\n controls.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n MRI ModRM:r/m (w) ModRM:reg (r) Imm8 NA\r\n HVM ModRM:r/m (w) ModRM:reg (r) Imm8 NA\r\n\r\nDescription\r\nConvert packed single-precision floating values in the source operand to half-precision (16-bit) floating-point\r\nvalues and store to the destination operand. The rounding mode is specified using the immediate field (imm8).\r\nUnderflow results (i.e., tiny results) are converted to denormals. MXCSR.FTZ is ignored. If a source element is\r\ndenormal relative to the input format with DM masked and at least one of PM or UM unmasked; a SIMD exception\r\nwill be raised with DE, UE and PE set.\r\n\r\n\r\n\r\n VCVTPS2PH xmm1/mem64, xmm2, imm8\r\n 127 96 95 64 63 32 31 0\r\n VS3 VS2 VS1 VS0 xmm2\r\n\r\n convert convert convert\r\n convert\r\n\r\n\r\n\r\n\r\n 127 96 95 64 63 48 47 32 31 16 15 0\r\n VH3 VH2 VH1 VH0 xmm1/mem64\r\n\r\n\r\n Figure 5-7. VCVTPS2PH (128-bit Version)\r\n\r\n\r\nThe immediate byte defines several bit fields that control rounding operation. The effect and encoding of the RC\r\nfield are listed in Table 5-3.\r\n\r\n\r\n\r\n\r\n\r\n Table 5-3. Immediate Byte Encoding for 16-bit Floating-Point Conversion Instructions\r\n Bits Field Name/value Description Comment\r\n Imm[1:0] RC=00B Round to nearest even If Imm[2] = 0\r\n RC=01B Round down\r\n RC=10B Round up\r\n RC=11B Truncate\r\n Imm[2] MS1=0 Use imm[1:0] for rounding Ignore MXCSR.RC\r\n MS1=1 Use MXCSR.RC for rounding\r\n Imm[7:3] Ignored Ignored by processor\r\n\r\nVEX.128 version: The source operand is a XMM register. The destination operand is a XMM register or 64-bit\r\nmemory location. If the destination operand is a register then the upper bits (MAX_VL-1:64) of corresponding\r\nregister are zeroed.\r\nVEX.256 version: The source operand is a YMM register. The destination operand is a XMM register or 128-bit\r\nmemory location. If the destination operand is a register, the upper bits (MAX_VL-1:128) of the corresponding\r\ndestination register are zeroed.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved (must be 1111b).\r\nEVEX encoded versions: The source operand is a ZMM/YMM/XMM register. The destination operand is a\r\nYMM/XMM/XMM (low 64-bits) register or a 256/128/64-bit memory location, conditionally updated with writemask\r\nk1. Bits (MAX_VL-1:256/128/64) of the corresponding destination register are zeroed.\r\n\r\nOperation\r\nvCvt_s2h(SRC1[31:0])\r\n{\r\nIF Imm[2] = 0\r\nTHEN ; using Imm[1:0] for rounding control, see Table 5-3\r\n RETURN Cvt_Single_Precision_To_Half_Precision_FP_Imm(SRC1[31:0]);\r\nELSE ; using MXCSR.RC for rounding control\r\n RETURN Cvt_Single_Precision_To_Half_Precision_FP_Mxcsr(SRC1[31:0]);\r\nFI;\r\n}\r\n\r\nVCVTPS2PH (EVEX encoded versions) when dest is a register\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n k <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <-\r\n vCvt_s2h(SRC[k+31:k])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL/2] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVCVTPS2PH (EVEX encoded versions) when dest is memory\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n k <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <-\r\n vCvt_s2h(SRC[k+31:k])\r\n ELSE\r\n *DEST[i+15:i] remains unchanged* ; merging-masking\r\n FI;\r\nENDFOR\r\n\r\nVCVTPS2PH (VEX.256 encoded version)\r\nDEST[15:0] <-vCvt_s2h(SRC1[31:0]);\r\nDEST[31:16] <-vCvt_s2h(SRC1[63:32]);\r\nDEST[47:32] <-vCvt_s2h(SRC1[95:64]);\r\nDEST[63:48] <-vCvt_s2h(SRC1[127:96]);\r\nDEST[79:64] <-vCvt_s2h(SRC1[159:128]);\r\nDEST[95:80] <-vCvt_s2h(SRC1[191:160]);\r\nDEST[111:96] <-vCvt_s2h(SRC1[223:192]);\r\nDEST[127:112] <-vCvt_s2h(SRC1[255:224]);\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVCVTPS2PH (VEX.128 encoded version)\r\nDEST[15:0] <-vCvt_s2h(SRC1[31:0]);\r\nDEST[31:16] <-vCvt_s2h(SRC1[63:32]);\r\nDEST[47:32] <-vCvt_s2h(SRC1[95:64]);\r\nDEST[63:48] <-vCvt_s2h(SRC1[127:96]);\r\nDEST[MAX_VL-1:64] <- 0\r\n\r\nFlags Affected\r\nNone\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTPS2PH __m256i _mm512_cvtps_ph(__m512 a);\r\nVCVTPS2PH __m256i _mm512_mask_cvtps_ph(__m256i s, __mmask16 k,__m512 a);\r\nVCVTPS2PH __m256i _mm512_maskz_cvtps_ph(__mmask16 k,__m512 a);\r\nVCVTPS2PH __m256i _mm512_cvt_roundps_ph(__m512 a, const int imm);\r\nVCVTPS2PH __m256i _mm512_mask_cvt_roundps_ph(__m256i s, __mmask16 k,__m512 a, const int imm);\r\nVCVTPS2PH __m256i _mm512_maskz_cvt_roundps_ph(__mmask16 k,__m512 a, const int imm);\r\nVCVTPS2PH __m128i _mm256_mask_cvtps_ph(__m128i s, __mmask8 k,__m256 a);\r\nVCVTPS2PH __m128i _mm256_maskz_cvtps_ph(__mmask8 k,__m256 a);\r\nVCVTPS2PH __m128i _mm_mask_cvtps_ph(__m128i s, __mmask8 k,__m128 a);\r\nVCVTPS2PH __m128i _mm_maskz_cvtps_ph(__mmask8 k,__m128 a);\r\nVCVTPS2PH __m128i _mm_cvtps_ph ( __m128 m1, const int imm);\r\nVCVTPS2PH __m128i _mm256_cvtps_ph(__m256 m1, const int imm);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Underflow, Overflow, Precision, Denormal (if MXCSR.DAZ=0);\r\n\r\n\r\n\r\n\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 11 (do not report #AC);\r\nEVEX-encoded instructions, see Exceptions Type E11.\r\n#UD If VEX.W=1.\r\n#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VCVTPS2PH"
},
{
"description": "VCVTPS2QQ-Convert Packed Single Precision Floating-Point Values to Packed Singed\r\nQuadword Integer Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F.W0 7B /r HV V/V AVX512VL Convert two packed single precision floating-point values from\r\n VCVTPS2QQ xmm1 {k1}{z}, AVX512DQ xmm2/m64/m32bcst to two packed signed quadword values in\r\n xmm2/m64/m32bcst xmm1 subject to writemask k1.\r\n EVEX.256.66.0F.W0 7B /r HV V/V AVX512VL Convert four packed single precision floating-point values from\r\n VCVTPS2QQ ymm1 {k1}{z}, AVX512DQ xmm2/m128/m32bcst to four packed signed quadword values\r\n xmm2/m128/m32bcst in ymm1 subject to writemask k1.\r\n EVEX.512.66.0F.W0 7B /r HV V/V AVX512DQ Convert eight packed single precision floating-point values from\r\n VCVTPS2QQ zmm1 {k1}{z}, ymm2/m256/m32bcst to eight packed signed quadword values\r\n ymm2/m256/m32bcst{er} in zmm1 subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n HV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts eight packed single-precision floating-point values in the source operand to eight signed quadword inte-\r\ngers in the destination operand.\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR\r\nregister or the embedded rounding control bits. If a converted result cannot be represented in the destination\r\nformat, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value\r\n(2w-1, where w represents the number of bits in the destination format) is returned.\r\nThe source operand is a YMM/XMM/XMM (low 64- bits) register or a 256/128/64-bit memory location. The destina-\r\ntion operation is a ZMM/YMM/XMM register conditionally updated with writemask k1.\r\nNote: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVCVTPS2QQ (EVEX encoded versions) when src operand is a register\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL == 512) AND (EVEX.b == 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n k <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <-\r\n Convert_Single_Precision_To_QuadInteger(SRC[k+31:k])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVCVTPS2QQ (EVEX encoded versions) when src operand is a memory source\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n k <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b == 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n Convert_Single_Precision_To_QuadInteger(SRC[31:0])\r\n ELSE\r\n DEST[i+63:i] <-\r\n Convert_Single_Precision_To_QuadInteger(SRC[k+31:k])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTPS2QQ __m512i _mm512_cvtps_epi64( __m512 a);\r\nVCVTPS2QQ __m512i _mm512_mask_cvtps_epi64( __m512i s, __mmask16 k, __m512 a);\r\nVCVTPS2QQ __m512i _mm512_maskz_cvtps_epi64( __mmask16 k, __m512 a);\r\nVCVTPS2QQ __m512i _mm512_cvt_roundps_epi64( __m512 a, int r);\r\nVCVTPS2QQ __m512i _mm512_mask_cvt_roundps_epi64( __m512i s, __mmask16 k, __m512 a, int r);\r\nVCVTPS2QQ __m512i _mm512_maskz_cvt_roundps_epi64( __mmask16 k, __m512 a, int r);\r\nVCVTPS2QQ __m256i _mm256_cvtps_epi64( __m256 a);\r\nVCVTPS2QQ __m256i _mm256_mask_cvtps_epi64( __m256i s, __mmask8 k, __m256 a);\r\nVCVTPS2QQ __m256i _mm256_maskz_cvtps_epi64( __mmask8 k, __m256 a);\r\nVCVTPS2QQ __m128i _mm_cvtps_epi64( __m128 a);\r\nVCVTPS2QQ __m128i _mm_mask_cvtps_epi64( __m128i s, __mmask8 k, __m128 a);\r\nVCVTPS2QQ __m128i _mm_maskz_cvtps_epi64( __mmask8 k, __m128 a);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nEVEX-encoded instructions, see Exceptions Type E3\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VCVTPS2QQ"
},
{
"description": "VCVTPS2UDQ-Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.0F.W0 79 /r FV V/V AVX512VL Convert four packed single precision floating-point\r\n VCVTPS2UDQ xmm1 {k1}{z}, AVX512F values from xmm2/m128/m32bcst to four packed\r\n xmm2/m128/m32bcst unsigned doubleword values in xmm1 subject to\r\n writemask k1.\r\n EVEX.256.0F.W0 79 /r FV V/V AVX512VL Convert eight packed single precision floating-point\r\n VCVTPS2UDQ ymm1 {k1}{z}, AVX512F values from ymm2/m256/m32bcst to eight packed\r\n ymm2/m256/m32bcst unsigned doubleword values in ymm1 subject to\r\n writemask k1.\r\n EVEX.512.0F.W0 79 /r FV V/V AVX512F Convert sixteen packed single-precision floating-point\r\n VCVTPS2UDQ zmm1 {k1}{z}, values from zmm2/m512/m32bcst to sixteen packed\r\n zmm2/m512/m32bcst{er} unsigned doubleword values in zmm1 subject to\r\n writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts sixteen packed single-precision floating-point values in the source operand to sixteen unsigned double-\r\nword integers in the destination operand.\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR\r\nregister or the embedded rounding control bits. If a converted result cannot be represented in the destination\r\nformat, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w - 1 is\r\nreturned, where w represents the number of bits in the destination format.\r\nThe source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector\r\nbroadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally\r\nupdated with writemask k1.\r\nNote: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVCVTPS2UDQ (EVEX encoded versions) when src operand is a register\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <-\r\n Convert_Single_Precision_Floating_Point_To_UInteger(SRC[i+31:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVCVTPS2UDQ (EVEX encoded versions) when src operand is a memory source\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n Convert_Single_Precision_Floating_Point_To_UInteger(SRC[31:0])\r\n ELSE\r\n DEST[i+31:i] <-\r\n Convert_Single_Precision_Floating_Point_To_UInteger(SRC[i+31:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTPS2UDQ __m512i _mm512_cvtps_epu32( __m512 a);\r\nVCVTPS2UDQ __m512i _mm512_mask_cvtps_epu32( __m512i s, __mmask16 k, __m512 a);\r\nVCVTPS2UDQ __m512i _mm512_maskz_cvtps_epu32( __mmask16 k, __m512 a);\r\nVCVTPS2UDQ __m512i _mm512_cvt_roundps_epu32( __m512 a, int r);\r\nVCVTPS2UDQ __m512i _mm512_mask_cvt_roundps_epu32( __m512i s, __mmask16 k, __m512 a, int r);\r\nVCVTPS2UDQ __m512i _mm512_maskz_cvt_roundps_epu32( __mmask16 k, __m512 a, int r);\r\nVCVTPS2UDQ __m256i _mm256_cvtps_epu32( __m256d a);\r\nVCVTPS2UDQ __m256i _mm256_mask_cvtps_epu32( __m256i s, __mmask8 k, __m256 a);\r\nVCVTPS2UDQ __m256i _mm256_maskz_cvtps_epu32( __mmask8 k, __m256 a);\r\nVCVTPS2UDQ __m128i _mm_cvtps_epu32( __m128 a);\r\nVCVTPS2UDQ __m128i _mm_mask_cvtps_epu32( __m128i s, __mmask8 k, __m128 a);\r\nVCVTPS2UDQ __m128i _mm_maskz_cvtps_epu32( __mmask8 k, __m128 a);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VCVTPS2UDQ"
},
{
"description": "VCVTPS2UQQ-Convert Packed Single Precision Floating-Point Values to Packed Unsigned\r\nQuadword Integer Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F.W0 79 /r HV V/V AVX512VL Convert two packed single precision floating-point values from\r\n VCVTPS2UQQ xmm1 {k1}{z}, AVX512DQ zmm2/m64/m32bcst to two packed unsigned quadword values\r\n xmm2/m64/m32bcst in zmm1 subject to writemask k1.\r\n EVEX.256.66.0F.W0 79 /r HV V/V AVX512VL Convert four packed single precision floating-point values from\r\n VCVTPS2UQQ ymm1 {k1}{z}, AVX512DQ xmm2/m128/m32bcst to four packed unsigned quadword\r\n xmm2/m128/m32bcst values in ymm1 subject to writemask k1.\r\n EVEX.512.66.0F.W0 79 /r HV V/V AVX512DQ Convert eight packed single precision floating-point values from\r\n VCVTPS2UQQ zmm1 {k1}{z}, ymm2/m256/m32bcst to eight packed unsigned quadword\r\n ymm2/m256/m32bcst{er} values in zmm1 subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n HV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts up to eight packed single-precision floating-point values in the source operand to unsigned quadword\r\nintegers in the destination operand.\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR\r\nregister or the embedded rounding control bits. If a converted result cannot be represented in the destination\r\nformat, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w - 1 is\r\nreturned, where w represents the number of bits in the destination format.\r\nThe source operand is a YMM/XMM/XMM (low 64- bits) register or a 256/128/64-bit memory location. The destina-\r\ntion operation is a ZMM/YMM/XMM register conditionally updated with writemask k1.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVCVTPS2UQQ (EVEX encoded versions) when src operand is a register\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL == 512) AND (EVEX.b == 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n k <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <-\r\n Convert_Single_Precision_To_UQuadInteger(SRC[k+31:k])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVCVTPS2UQQ (EVEX encoded versions) when src operand is a memory source\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n k <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b == 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n Convert_Single_Precision_To_UQuadInteger(SRC[31:0])\r\n ELSE\r\n DEST[i+63:i] <-\r\n Convert_Single_Precision_To_UQuadInteger(SRC[k+31:k])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTPS2UQQ __m512i _mm512_cvtps_epu64( __m512 a);\r\nVCVTPS2UQQ __m512i _mm512_mask_cvtps_epu64( __m512i s, __mmask16 k, __m512 a);\r\nVCVTPS2UQQ __m512i _mm512_maskz_cvtps_epu64( __mmask16 k, __m512 a);\r\nVCVTPS2UQQ __m512i _mm512_cvt_roundps_epu64( __m512 a, int r);\r\nVCVTPS2UQQ __m512i _mm512_mask_cvt_roundps_epu64( __m512i s, __mmask16 k, __m512 a, int r);\r\nVCVTPS2UQQ __m512i _mm512_maskz_cvt_roundps_epu64( __mmask16 k, __m512 a, int r);\r\nVCVTPS2UQQ __m256i _mm256_cvtps_epu64( __m256 a);\r\nVCVTPS2UQQ __m256i _mm256_mask_cvtps_epu64( __m256i s, __mmask8 k, __m256 a);\r\nVCVTPS2UQQ __m256i _mm256_maskz_cvtps_epu64( __mmask8 k, __m256 a);\r\nVCVTPS2UQQ __m128i _mm_cvtps_epu64( __m128 a);\r\nVCVTPS2UQQ __m128i _mm_mask_cvtps_epu64( __m128i s, __mmask8 k, __m128 a);\r\nVCVTPS2UQQ __m128i _mm_maskz_cvtps_epu64( __mmask8 k, __m128 a);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nEVEX-encoded instructions, see Exceptions Type E3\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VCVTPS2UQQ"
},
{
"description": "VCVTQQ2PD-Convert Packed Quadword Integers to Packed Double-Precision Floating-Point\r\nValues\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.F3.0F.W1 E6 /r FV V/V AVX512VL Convert two packed quadword integers from\r\n VCVTQQ2PD xmm1 {k1}{z}, AVX512DQ xmm2/m128/m64bcst to packed double-precision floating-\r\n xmm2/m128/m64bcst point values in xmm1 with writemask k1.\r\n EVEX.256.F3.0F.W1 E6 /r FV V/V AVX512VL Convert four packed quadword integers from\r\n VCVTQQ2PD ymm1 {k1}{z}, AVX512DQ ymm2/m256/m64bcst to packed double-precision floating-\r\n ymm2/m256/m64bcst point values in ymm1 with writemask k1.\r\n EVEX.512.F3.0F.W1 E6 /r FV V/V AVX512DQ Convert eight packed quadword integers from\r\n VCVTQQ2PD zmm1 {k1}{z}, zmm2/m512/m64bcst to eight packed double-precision\r\n zmm2/m512/m64bcst{er} floating-point values in zmm1 with writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts packed quadword integers in the source operand (second operand) to packed double-precision floating-\r\npoint values in the destination operand (first operand).\r\nThe source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operation\r\nis a ZMM/YMM/XMM register conditionally updated with writemask k1.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\nOperation\r\nVCVTQQ2PD (EVEX2 encoded versions) when src operand is a register\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL == 512) AND (EVEX.b == 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <-\r\n Convert_QuadInteger_To_Double_Precision_Floating_Point(SRC[i+63:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVCVTQQ2PD (EVEX encoded versions) when src operand is a memory source\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b == 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n Convert_QuadInteger_To_Double_Precision_Floating_Point(SRC[63:0])\r\n ELSE\r\n DEST[i+63:i] <-\r\n Convert_QuadInteger_To_Double_Precision_Floating_Point(SRC[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTQQ2PD __m512d _mm512_cvtepi64_pd( __m512i a);\r\nVCVTQQ2PD __m512d _mm512_mask_cvtepi64_pd( __m512d s, __mmask16 k, __m512i a);\r\nVCVTQQ2PD __m512d _mm512_maskz_cvtepi64_pd( __mmask16 k, __m512i a);\r\nVCVTQQ2PD __m512d _mm512_cvt_roundepi64_pd( __m512i a, int r);\r\nVCVTQQ2PD __m512d _mm512_mask_cvt_roundepi_ps( __m512d s, __mmask8 k, __m512i a, int r);\r\nVCVTQQ2PD __m512d _mm512_maskz_cvt_roundepi64_pd( __mmask8 k, __m512i a, int r);\r\nVCVTQQ2PD __m256d _mm256_mask_cvtepi64_pd( __m256d s, __mmask8 k, __m256i a);\r\nVCVTQQ2PD __m256d _mm256_maskz_cvtepi64_pd( __mmask8 k, __m256i a);\r\nVCVTQQ2PD __m128d _mm_mask_cvtepi64_pd( __m128d s, __mmask8 k, __m128i a);\r\nVCVTQQ2PD __m128d _mm_maskz_cvtepi64_pd( __mmask8 k, __m128i a);\r\n\r\nSIMD Floating-Point Exceptions\r\nPrecision\r\n\r\nOther Exceptions\r\nEVEX-encoded instructions, see Exceptions Type E2\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VCVTQQ2PD"
},
{
"description": "VCVTQQ2PS-Convert Packed Quadword Integers to Packed Single-Precision Floating-Point\r\nValues\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.0F.W1 5B /r FV V/V AVX512VL Convert two packed quadword integers from xmm2/mem to\r\n VCVTQQ2PS xmm1 {k1}{z}, AVX512DQ packed single-precision floating-point values in xmm1 with\r\n xmm2/m128/m64bcst writemask k1.\r\n EVEX.256.0F.W1 5B /r FV V/V AVX512VL Convert four packed quadword integers from ymm2/mem to\r\n VCVTQQ2PS xmm1 {k1}{z}, AVX512DQ packed single-precision floating-point values in xmm1 with\r\n ymm2/m256/m64bcst writemask k1.\r\n EVEX.512.0F.W1 5B /r FV V/V AVX512DQ Convert eight packed quadword integers from zmm2/mem to\r\n VCVTQQ2PS ymm1 {k1}{z}, eight packed single-precision floating-point values in ymm1 with\r\n zmm2/m512/m64bcst{er} writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts packed quadword integers in the source operand (second operand) to packed single-precision floating-\r\npoint values in the destination operand (first operand).\r\nThe source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operation\r\nis a YMM/XMM/XMM (lower 64 bits) register conditionally updated with writemask k1.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\nOperation\r\nVCVTQQ2PS (EVEX encoded versions) when src operand is a register\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n k <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[k+31:k] <-\r\n Convert_QuadInteger_To_Single_Precision_Floating_Point(SRC[i+63:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[k+31:k] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[k+31:k] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL/2] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVCVTQQ2PS (EVEX encoded versions) when src operand is a memory source\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n k <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b == 1)\r\n THEN\r\n DEST[k+31:k] <-\r\n Convert_QuadInteger_To_Single_Precision_Floating_Point(SRC[63:0])\r\n ELSE\r\n DEST[k+31:k] <-\r\n Convert_QuadInteger_To_Single_Precision_Floating_Point(SRC[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[k+31:k] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[k+31:k] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL/2] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTQQ2PS __m256 _mm512_cvtepi64_ps( __m512i a);\r\nVCVTQQ2PS __m256 _mm512_mask_cvtepi64_ps( __m256 s, __mmask16 k, __m512i a);\r\nVCVTQQ2PS __m256 _mm512_maskz_cvtepi64_ps( __mmask16 k, __m512i a);\r\nVCVTQQ2PS __m256 _mm512_cvt_roundepi64_ps( __m512i a, int r);\r\nVCVTQQ2PS __m256 _mm512_mask_cvt_roundepi_ps( __m256 s, __mmask8 k, __m512i a, int r);\r\nVCVTQQ2PS __m256 _mm512_maskz_cvt_roundepi64_ps( __mmask8 k, __m512i a, int r);\r\nVCVTQQ2PS __m128 _mm256_cvtepi64_ps( __m256i a);\r\nVCVTQQ2PS __m128 _mm256_mask_cvtepi64_ps( __m128 s, __mmask8 k, __m256i a);\r\nVCVTQQ2PS __m128 _mm256_maskz_cvtepi64_ps( __mmask8 k, __m256i a);\r\nVCVTQQ2PS __m128 _mm_cvtepi64_ps( __m128i a);\r\nVCVTQQ2PS __m128 _mm_mask_cvtepi64_ps( __m128 s, __mmask8 k, __m128i a);\r\nVCVTQQ2PS __m128 _mm_maskz_cvtepi64_ps( __mmask8 k, __m128i a);\r\n\r\nSIMD Floating-Point Exceptions\r\nPrecision\r\n\r\nOther Exceptions\r\nEVEX-encoded instructions, see Exceptions Type E2\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VCVTQQ2PS"
},
{
"description": "VCVTSD2USI-Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword\r\nInteger\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.LIG.F2.0F.W0 79 /r T1F V/V AVX512F Convert one double-precision floating-point value from\r\n VCVTSD2USI r32, xmm1/m64{er} xmm1/m64 to one unsigned doubleword integer r32.\r\n EVEX.LIG.F2.0F.W1 79 /r T1F V/N.E.1 AVX512F Convert one double-precision floating-point value from\r\n VCVTSD2USI r64, xmm1/m64{er} xmm1/m64 to one unsigned quadword integer zero-\r\n extended into r64.\r\nNOTES:\r\n1. EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1F ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts a double-precision floating-point value in the source operand (the second operand) to an unsigned\r\ndoubleword integer in the destination operand (the first operand). The source operand can be an XMM register or\r\na 64-bit memory location. The destination operand is a general-purpose register. When the source operand is an\r\nXMM register, the double-precision floating-point value is contained in the low quadword of the register.\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR\r\nregister or the embedded rounding control bits. If a converted result cannot be represented in the destination\r\nformat, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w - 1 is\r\nreturned, where w represents the number of bits in the destination format.\r\n\r\nOperation\r\nVCVTSD2USI (EVEX encoded version)\r\nIF (SRC *is register*) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF 64-Bit Mode and OperandSize = 64\r\n THEN DEST[63:0] <- Convert_Double_Precision_Floating_Point_To_UInteger(SRC[63:0]);\r\n ELSE DEST[31:0] <- Convert_Double_Precision_Floating_Point_To_UInteger(SRC[63:0]);\r\nFI\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTSD2USI unsigned int _mm_cvtsd_u32(__m128d);\r\nVCVTSD2USI unsigned int _mm_cvt_roundsd_u32(__m128d, int r);\r\nVCVTSD2USI unsigned __int64 _mm_cvtsd_u64(__m128d);\r\nVCVTSD2USI unsigned __int64 _mm_cvt_roundsd_u64(__m128d, int r);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nEVEX-encoded instructions, see Exceptions Type E3NF.\r\n\r\n\r\n",
"mnem": "VCVTSD2USI"
},
{
"description": "VCVTSS2USI-Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword\r\nInteger\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.LIG.F3.0F.W0 79 /r T1F V/V AVX512F Convert one single-precision floating-point value from\r\n VCVTSS2USI r32, xmm1/m32{er} xmm1/m32 to one unsigned doubleword integer in r32.\r\n EVEX.LIG.F3.0F.W1 79 /r T1F V/N.E.1 AVX512F Convert one single-precision floating-point value from\r\n VCVTSS2USI r64, xmm1/m32{er} xmm1/m32 to one unsigned quadword integer in r64.\r\nNOTES:\r\n1. EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1F ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts a single-precision floating-point value in the source operand (the second operand) to an unsigned double-\r\nword integer (or unsigned quadword integer if operand size is 64 bits) in the destination operand (the first\r\noperand). The source operand can be an XMM register or a memory location. The destination operand is a general-\r\npurpose register. When the source operand is an XMM register, the single-precision floating-point value is\r\ncontained in the low doubleword of the register.\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR\r\nregister or the embedded rounding control bits. If a converted result cannot be represented in the destination\r\nformat, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w - 1 is\r\nreturned, where w represents the number of bits in the destination format.\r\nVEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.\r\nNote: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\nOperation\r\nVCVTSS2USI (EVEX encoded version)\r\nIF (SRC *is register*) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF 64-bit Mode and OperandSize = 64\r\nTHEN\r\n DEST[63:0] <- Convert_Single_Precision_Floating_Point_To_UInteger(SRC[31:0]);\r\nELSE\r\n DEST[31:0] <- Convert_Single_Precision_Floating_Point_To_UInteger(SRC[31:0]);\r\nFI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTSS2USI unsigned _mm_cvtss_u32( __m128 a);\r\nVCVTSS2USI unsigned _mm_cvt_roundss_u32( __m128 a, int r);\r\nVCVTSS2USI unsigned __int64 _mm_cvtss_u64( __m128 a);\r\nVCVTSS2USI unsigned __int64 _mm_cvt_roundss_u64( __m128 a, int r);\r\n\r\n\r\n\r\n\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nEVEX-encoded instructions, see Exceptions Type E3NF.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VCVTSS2USI"
},
{
"description": "VCVTTPD2QQ-Convert with Truncation Packed Double-Precision Floating-Point Values to\r\nPacked Quadword Integers\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F.W1 7A /r FV V/V AVX512VL Convert two packed double-precision floating-point values from\r\n VCVTTPD2QQ xmm1 {k1}{z}, AVX512DQ zmm2/m128/m64bcst to two packed quadword integers in\r\n xmm2/m128/m64bcst zmm1 using truncation with writemask k1.\r\n EVEX.256.66.0F.W1 7A /r FV V/V AVX512VL Convert four packed double-precision floating-point values\r\n VCVTTPD2QQ ymm1 {k1}{z}, AVX512DQ from ymm2/m256/m64bcst to four packed quadword integers\r\n ymm2/m256/m64bcst in ymm1 using truncation with writemask k1.\r\n EVEX.512.66.0F.W1 7A /r FV V/V AVX512DQ Convert eight packed double-precision floating-point values\r\n VCVTTPD2QQ zmm1 {k1}{z}, from zmm2/m512 to eight packed quadword integers in zmm1\r\n zmm2/m512/m64bcst{sae} using truncation with writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts with truncation packed double-precision floating-point values in the source operand (second operand) to\r\npacked quadword integers in the destination operand (first operand).\r\nEVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location.\r\nThe destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR\r\nregister. If a converted result cannot be represented in the destination format, the floating-point invalid exception\r\nis raised, and if this exception is masked, the indefinite integer value (2w-1, where w represents the number of bits\r\nin the destination format) is returned.\r\nNote: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\nOperation\r\nVCVTTPD2QQ (EVEX encoded version) when src operand is a register\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <-\r\n Convert_Double_Precision_Floating_Point_To_QuadInteger_Truncate(SRC[i+63:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVCVTTPD2QQ (EVEX encoded version) when src operand is a memory source\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b == 1)\r\n THEN\r\n DEST[i+63:i] <- Convert_Double_Precision_Floating_Point_To_QuadInteger_Truncate(SRC[63:0])\r\n ELSE\r\n DEST[i+63:i] <- Convert_Double_Precision_Floating_Point_To_QuadInteger_Truncate(SRC[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTTPD2QQ __m512i _mm512_cvttpd_epi64( __m512d a);\r\nVCVTTPD2QQ __m512i _mm512_mask_cvttpd_epi64( __m512i s, __mmask8 k, __m512d a);\r\nVCVTTPD2QQ __m512i _mm512_maskz_cvttpd_epi64( __mmask8 k, __m512d a);\r\nVCVTTPD2QQ __m512i _mm512_cvtt_roundpd_epi64( __m512d a, int sae);\r\nVCVTTPD2QQ __m512i _mm512_mask_cvtt_roundpd_epi64( __m512i s, __mmask8 k, __m512d a, int sae);\r\nVCVTTPD2QQ __m512i _mm512_maskz_cvtt_roundpd_epi64( __mmask8 k, __m512d a, int sae);\r\nVCVTTPD2QQ __m256i _mm256_mask_cvttpd_epi64( __m256i s, __mmask8 k, __m256d a);\r\nVCVTTPD2QQ __m256i _mm256_maskz_cvttpd_epi64( __mmask8 k, __m256d a);\r\nVCVTTPD2QQ __m128i _mm_mask_cvttpd_epi64( __m128i s, __mmask8 k, __m128d a);\r\nVCVTTPD2QQ __m128i _mm_maskz_cvttpd_epi64( __mmask8 k, __m128d a);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VCVTTPD2QQ"
},
{
"description": "VCVTTPD2UDQ-Convert with Truncation Packed Double-Precision Floating-Point Values to\r\nPacked Unsigned Doubleword Integers\r\n Opcode Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.0F.W1 78 /r FV V/V AVX512VL Convert two packed double-precision floating-point values\r\n VCVTTPD2UDQ xmm1 {k1}{z}, AVX512F in xmm2/m128/m64bcst to two unsigned doubleword\r\n xmm2/m128/m64bcst integers in xmm1 using truncation subject to writemask\r\n k1.\r\n EVEX.256.0F.W1 78 02 /r FV V/V AVX512VL Convert four packed double-precision floating-point\r\n VCVTTPD2UDQ xmm1 {k1}{z}, AVX512F values in ymm2/m256/m64bcst to four unsigned\r\n ymm2/m256/m64bcst doubleword integers in xmm1 using truncation subject to\r\n writemask k1.\r\n EVEX.512.0F.W1 78 /r FV V/V AVX512F Convert eight packed double-precision floating-point\r\n VCVTTPD2UDQ ymm1 {k1}{z}, values in zmm2/m512/m64bcst to eight unsigned\r\n zmm2/m512/m64bcst{sae} doubleword integers in ymm1 using truncation subject to\r\n writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts with truncation packed double-precision floating-point values in the source operand (the second operand)\r\nto packed unsigned doubleword integers in the destination operand (the first operand).\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR\r\nregister. If a converted result cannot be represented in the destination format, the floating-point invalid exception\r\nis raised, and if this exception is masked, the integer value 2w - 1 is returned, where w represents the number of\r\nbits in the destination format.\r\nThe source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector\r\nbroadcasted from a 64-bit memory location. The destination operand is a YMM/XMM/XMM (low 64 bits) register\r\nconditionally updated with writemask k1. The upper bits (MAX_VL-1:256) of the corresponding destination are\r\nzeroed.\r\nNote: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVCVTTPD2UDQ (EVEX encoded versions) when src2 operand is a register\r\n(KL, VL) = (2, 128), (4, 256),(8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n k <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n DEST[i+31:i] <-\r\n Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[k+63:k])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL/2] <- 0\r\n\r\nVCVTTPD2UDQ (EVEX encoded versions) when src operand is a memory source\r\n(KL, VL) = (2, 128), (4, 256),(8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n k <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[63:0])\r\n ELSE\r\n DEST[i+31:i] <-\r\n Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[k+63:k])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL/2] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTTPD2UDQ __m256i _mm512_cvttpd_epu32( __m512d a);\r\nVCVTTPD2UDQ __m256i _mm512_mask_cvttpd_epu32( __m256i s, __mmask8 k, __m512d a);\r\nVCVTTPD2UDQ __m256i _mm512_maskz_cvttpd_epu32( __mmask8 k, __m512d a);\r\nVCVTTPD2UDQ __m256i _mm512_cvtt_roundpd_epu32( __m512d a, int sae);\r\nVCVTTPD2UDQ __m256i _mm512_mask_cvtt_roundpd_epu32( __m256i s, __mmask8 k, __m512d a, int sae);\r\nVCVTTPD2UDQ __m256i _mm512_maskz_cvtt_roundpd_epu32( __mmask8 k, __m512d a, int sae);\r\nVCVTTPD2UDQ __m128i _mm256_mask_cvttpd_epu32( __m128i s, __mmask8 k, __m256d a);\r\nVCVTTPD2UDQ __m128i _mm256_maskz_cvttpd_epu32( __mmask8 k, __m256d a);\r\nVCVTTPD2UDQ __m128i _mm_mask_cvttpd_epu32( __m128i s, __mmask8 k, __m128d a);\r\nVCVTTPD2UDQ __m128i _mm_maskz_cvttpd_epu32( __mmask8 k, __m128d a);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VCVTTPD2UDQ"
},
{
"description": "VCVTTPD2UQQ-Convert with Truncation Packed Double-Precision Floating-Point Values to\r\nPacked Unsigned Quadword Integers\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F.W1 78 /r FV V/V AVX512VL Convert two packed double-precision floating-point values\r\n VCVTTPD2UQQ xmm1 {k1}{z}, AVX512DQ from xmm2/m128/m64bcst to two packed unsigned\r\n xmm2/m128/m64bcst quadword integers in xmm1 using truncation with\r\n writemask k1.\r\n EVEX.256.66.0F.W1 78 /r FV V/V AVX512VL Convert four packed double-precision floating-point values\r\n VCVTTPD2UQQ ymm1 {k1}{z}, AVX512DQ from ymm2/m256/m64bcst to four packed unsigned\r\n ymm2/m256/m64bcst quadword integers in ymm1 using truncation with\r\n writemask k1.\r\n EVEX.512.66.0F.W1 78 /r FV V/V AVX512DQ Convert eight packed double-precision floating-point values\r\n VCVTTPD2UQQ zmm1 {k1}{z}, from zmm2/mem to eight packed unsigned quadword\r\n zmm2/m512/m64bcst{sae} integers in zmm1 using truncation with writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts with truncation packed double-precision floating-point values in the source operand (second operand) to\r\npacked unsigned quadword integers in the destination operand (first operand).\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR\r\nregister. If a converted result cannot be represented in the destination format, the floating-point invalid exception\r\nis raised, and if this exception is masked, the integer value 2w - 1 is returned, where w represents the number of\r\nbits in the destination format.\r\nEVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location.\r\nThe destination operation is a ZMM/YMM/XMM register conditionally updated with writemask k1.\r\nNote: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\nOperation\r\nVCVTTPD2UQQ (EVEX encoded versions) when src operand is a register\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <-\r\n Convert_Double_Precision_Floating_Point_To_UQuadInteger_Truncate(SRC[i+63:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVCVTTPD2UQQ (EVEX encoded versions) when src operand is a memory source\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b == 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n Convert_Double_Precision_Floating_Point_To_UQuadInteger_Truncate(SRC[63:0])\r\n ELSE\r\n DEST[i+63:i] <-\r\n Convert_Double_Precision_Floating_Point_To_UQuadInteger_Truncate(SRC[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n\r\nVCVTTPD2UQQ _mm<size>[_mask[z]]_cvtt[_round]pd_epu64\r\nVCVTTPD2UQQ __m512i _mm512_cvttpd_epu64( __m512d a);\r\nVCVTTPD2UQQ __m512i _mm512_mask_cvttpd_epu64( __m512i s, __mmask8 k, __m512d a);\r\nVCVTTPD2UQQ __m512i _mm512_maskz_cvttpd_epu64( __mmask8 k, __m512d a);\r\nVCVTTPD2UQQ __m512i _mm512_cvtt_roundpd_epu64( __m512d a, int sae);\r\nVCVTTPD2UQQ __m512i _mm512_mask_cvtt_roundpd_epu64( __m512i s, __mmask8 k, __m512d a, int sae);\r\nVCVTTPD2UQQ __m512i _mm512_maskz_cvtt_roundpd_epu64( __mmask8 k, __m512d a, int sae);\r\nVCVTTPD2UQQ __m256i _mm256_mask_cvttpd_epu64( __m256i s, __mmask8 k, __m256d a);\r\nVCVTTPD2UQQ __m256i _mm256_maskz_cvttpd_epu64( __mmask8 k, __m256d a);\r\nVCVTTPD2UQQ __m128i _mm_mask_cvttpd_epu64( __m128i s, __mmask8 k, __m128d a);\r\nVCVTTPD2UQQ __m128i _mm_maskz_cvttpd_epu64( __mmask8 k, __m128d a);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VCVTTPD2UQQ"
},
{
"description": "VCVTTPS2QQ-Convert with Truncation Packed Single Precision Floating-Point Values to\r\nPacked Singed Quadword Integer Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F.W0 7A /r HV V/V AVX512VL Convert two packed single precision floating-point values from\r\n VCVTTPS2QQ xmm1 {k1}{z}, AVX512DQ xmm2/m64/m32bcst to two packed signed quadword values in\r\n xmm2/m64/m32bcst xmm1 using truncation subject to writemask k1.\r\n EVEX.256.66.0F.W0 7A /r HV V/V AVX512VL Convert four packed single precision floating-point values from\r\n VCVTTPS2QQ ymm1 {k1}{z}, AVX512DQ xmm2/m128/m32bcst to four packed signed quadword values\r\n xmm2/m128/m32bcst in ymm1 using truncation subject to writemask k1.\r\n EVEX.512.66.0F.W0 7A /r HV V/V AVX512DQ Convert eight packed single precision floating-point values from\r\n VCVTTPS2QQ zmm1 {k1}{z}, ymm2/m256/m32bcst to eight packed signed quadword values\r\n ymm2/m256/m32bcst{sae} in zmm1 using truncation subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n HV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts with truncation packed single-precision floating-point values in the source operand to eight signed quad-\r\nword integers in the destination operand.\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR\r\nregister. If a converted result cannot be represented in the destination format, the floating-point invalid exception\r\nis raised, and if this exception is masked, the indefinite integer value (2w-1, where w represents the number of bits\r\nin the destination format) is returned.\r\nEVEX encoded versions: The source operand is a YMM/XMM/XMM (low 64 bits) register or a 256/128/64-bit\r\nmemory location. The destination operation is a vector register conditionally updated with writemask k1.\r\nNote: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\nOperation\r\nVCVTTPS2QQ (EVEX encoded versions) when src operand is a register\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n k <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <-\r\n Convert_Single_Precision_To_QuadInteger_Truncate(SRC[k+31:k])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVCVTTPS2QQ (EVEX encoded versions) when src operand is a memory source\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n k <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b == 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n Convert_Single_Precision_To_QuadInteger_Truncate(SRC[31:0])\r\n ELSE\r\n DEST[i+63:i] <-\r\n Convert_Single_Precision_To_QuadInteger_Truncate(SRC[k+31:k])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTTPS2QQ __m512i _mm512_cvttps_epi64( __m256 a);\r\nVCVTTPS2QQ __m512i _mm512_mask_cvttps_epi64( __m512i s, __mmask16 k, __m256 a);\r\nVCVTTPS2QQ __m512i _mm512_maskz_cvttps_epi64( __mmask16 k, __m256 a);\r\nVCVTTPS2QQ __m512i _mm512_cvtt_roundps_epi64( __m256 a, int sae);\r\nVCVTTPS2QQ __m512i _mm512_mask_cvtt_roundps_epi64( __m512i s, __mmask16 k, __m256 a, int sae);\r\nVCVTTPS2QQ __m512i _mm512_maskz_cvtt_roundps_epi64( __mmask16 k, __m256 a, int sae);\r\nVCVTTPS2QQ __m256i _mm256_mask_cvttps_epi64( __m256i s, __mmask8 k, __m128 a);\r\nVCVTTPS2QQ __m256i _mm256_maskz_cvttps_epi64( __mmask8 k, __m128 a);\r\nVCVTTPS2QQ __m128i _mm_mask_cvttps_epi64( __m128i s, __mmask8 k, __m128 a);\r\nVCVTTPS2QQ __m128i _mm_maskz_cvttps_epi64( __mmask8 k, __m128 a);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nEVEX-encoded instructions, see Exceptions Type E3.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VCVTTPS2QQ"
},
{
"description": "VCVTTPS2UDQ-Convert with Truncation Packed Single-Precision Floating-Point Values to\r\nPacked Unsigned Doubleword Integer Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.0F.W0 78 /r FV V/V AVX512VL Convert four packed single precision floating-point\r\n VCVTTPS2UDQ xmm1 {k1}{z}, AVX512F values from xmm2/m128/m32bcst to four packed\r\n xmm2/m128/m32bcst unsigned doubleword values in xmm1 using\r\n truncation subject to writemask k1.\r\n EVEX.256.0F.W0 78 /r FV V/V AVX512VL Convert eight packed single precision floating-point\r\n VCVTTPS2UDQ ymm1 {k1}{z}, AVX512F values from ymm2/m256/m32bcst to eight packed\r\n ymm2/m256/m32bcst unsigned doubleword values in ymm1 using\r\n truncation subject to writemask k1.\r\n EVEX.512.0F.W0 78 /r FV V/V AVX512F Convert sixteen packed single-precision floating-\r\n VCVTTPS2UDQ zmm1 {k1}{z}, point values from zmm2/m512/m32bcst to sixteen\r\n zmm2/m512/m32bcst{sae} packed unsigned doubleword values in zmm1 using\r\n truncation subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts with truncation packed single-precision floating-point values in the source operand to sixteen unsigned\r\ndoubleword integers in the destination operand.\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR.\r\nIf a converted result cannot be represented in the destination format, the floating-point invalid exception is raised,\r\nand if this exception is masked, the integer value 2w - 1 is returned, where w represents the number of bits in the\r\ndestination format.\r\nEVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or\r\na 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a\r\nZMM/YMM/XMM register conditionally updated with writemask k1.\r\nNote: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\nOperation\r\nVCVTTPS2UDQ (EVEX encoded versions) when src operand is a register\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <-\r\n Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[i+31:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\nVCVTTPS2UDQ (EVEX encoded versions) when src operand is a memory source\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[31:0])\r\n ELSE\r\n DEST[i+31:i] <-\r\n Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[i+31:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTTPS2UDQ __m512i _mm512_cvttps_epu32( __m512 a);\r\nVCVTTPS2UDQ __m512i _mm512_mask_cvttps_epu32( __m512i s, __mmask16 k, __m512 a);\r\nVCVTTPS2UDQ __m512i _mm512_maskz_cvttps_epu32( __mmask16 k, __m512 a);\r\nVCVTTPS2UDQ __m512i _mm512_cvtt_roundps_epu32( __m512 a, int sae);\r\nVCVTTPS2UDQ __m512i _mm512_mask_cvtt_roundps_epu32( __m512i s, __mmask16 k, __m512 a, int sae);\r\nVCVTTPS2UDQ __m512i _mm512_maskz_cvtt_roundps_epu32( __mmask16 k, __m512 a, int sae);\r\nVCVTTPS2UDQ __m256i _mm256_mask_cvttps_epu32( __m256i s, __mmask8 k, __m256 a);\r\nVCVTTPS2UDQ __m256i _mm256_maskz_cvttps_epu32( __mmask8 k, __m256 a);\r\nVCVTTPS2UDQ __m128i _mm_mask_cvttps_epu32( __m128i s, __mmask8 k, __m128 a);\r\nVCVTTPS2UDQ __m128i _mm_maskz_cvttps_epu32( __mmask8 k, __m128 a);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VCVTTPS2UDQ"
},
{
"description": "VCVTTPS2UQQ-Convert with Truncation Packed Single Precision Floating-Point Values to\r\nPacked Unsigned Quadword Integer Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F.W0 78 /r HV V/V AVX512VL Convert two packed single precision floating-point values\r\n VCVTTPS2UQQ xmm1 {k1}{z}, AVX512DQ from xmm2/m64/m32bcst to two packed unsigned quadword\r\n xmm2/m64/m32bcst values in xmm1 using truncation subject to writemask k1.\r\n EVEX.256.66.0F.W0 78 /r HV V/V AVX512VL Convert four packed single precision floating-point values\r\n VCVTTPS2UQQ ymm1 {k1}{z}, AVX512DQ from xmm2/m128/m32bcst to four packed unsigned\r\n xmm2/m128/m32bcst quadword values in ymm1 using truncation subject to\r\n writemask k1.\r\n EVEX.512.66.0F.W0 78 /r HV V/V AVX512DQ Convert eight packed single precision floating-point values\r\n VCVTTPS2UQQ zmm1 {k1}{z}, from ymm2/m256/m32bcst to eight packed unsigned\r\n ymm2/m256/m32bcst{sae} quadword values in zmm1 using truncation subject to\r\n writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n HV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts with truncation up to eight packed single-precision floating-point values in the source operand to\r\nunsigned quadword integers in the destination operand.\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR\r\nregister. If a converted result cannot be represented in the destination format, the floating-point invalid exception\r\nis raised, and if this exception is masked, the integer value 2w - 1 is returned, where w represents the number of\r\nbits in the destination format.\r\nEVEX encoded versions: The source operand is a YMM/XMM/XMM (low 64 bits) register or a 256/128/64-bit\r\nmemory location. The destination operation is a vector register conditionally updated with writemask k1.\r\nNote: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\nOperation\r\nVCVTTPS2UQQ (EVEX encoded versions) when src operand is a register\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n k <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <-\r\n Convert_Single_Precision_To_UQuadInteger_Truncate(SRC[k+31:k])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVCVTTPS2UQQ (EVEX encoded versions) when src operand is a memory source\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n k <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b == 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n Convert_Single_Precision_To_UQuadInteger_Truncate(SRC[31:0])\r\n ELSE\r\n DEST[i+63:i] <-\r\n Convert_Single_Precision_To_UQuadInteger_Truncate(SRC[k+31:k])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTTPS2UQQ _mm<size>[_mask[z]]_cvtt[_round]ps_epu64\r\nVCVTTPS2UQQ __m512i _mm512_cvttps_epu64( __m256 a);\r\nVCVTTPS2UQQ __m512i _mm512_mask_cvttps_epu64( __m512i s, __mmask16 k, __m256 a);\r\nVCVTTPS2UQQ __m512i _mm512_maskz_cvttps_epu64( __mmask16 k, __m256 a);\r\nVCVTTPS2UQQ __m512i _mm512_cvtt_roundps_epu64( __m256 a, int sae);\r\nVCVTTPS2UQQ __m512i _mm512_mask_cvtt_roundps_epu64( __m512i s, __mmask16 k, __m256 a, int sae);\r\nVCVTTPS2UQQ __m512i _mm512_maskz_cvtt_roundps_epu64( __mmask16 k, __m256 a, int sae);\r\nVCVTTPS2UQQ __m256i _mm256_mask_cvttps_epu64( __m256i s, __mmask8 k, __m128 a);\r\nVCVTTPS2UQQ __m256i _mm256_maskz_cvttps_epu64( __mmask8 k, __m128 a);\r\nVCVTTPS2UQQ __m128i _mm_mask_cvttps_epu64( __m128i s, __mmask8 k, __m128 a);\r\nVCVTTPS2UQQ __m128i _mm_maskz_cvttps_epu64( __mmask8 k, __m128 a);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nEVEX-encoded instructions, see Exceptions Type E3.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VCVTTPS2UQQ"
},
{
"description": "VCVTTSD2USI-Convert with Truncation Scalar Double-Precision Floating-Point Value to\r\nUnsigned Integer\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.LIG.F2.0F.W0 78 /r T1F V/V AVX512F Convert one double-precision floating-point value from\r\n VCVTTSD2USI r32, xmm1/m64{sae} xmm1/m64 to one unsigned doubleword integer r32\r\n using truncation.\r\n EVEX.LIG.F2.0F.W1 78 /r T1F V/N.E.1 AVX512F Convert one double-precision floating-point value from\r\n VCVTTSD2USI r64, xmm1/m64{sae} xmm1/m64 to one unsigned quadword integer zero-\r\n extended into r64 using truncation.\r\nNOTES:\r\n1. For this specific instruction, EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is\r\n used.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1F ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts with truncation a double-precision floating-point value in the source operand (the second operand) to an\r\nunsigned doubleword integer (or unsigned quadword integer if operand size is 64 bits) in the destination operand\r\n(the first operand). The source operand can be an XMM register or a 64-bit memory location. The destination\r\noperand is a general-purpose register. When the source operand is an XMM register, the double-precision floating-\r\npoint value is contained in the low quadword of the register.\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR\r\nregister. If a converted result cannot be represented in the destination format, the floating-point invalid exception\r\nis raised, and if this exception is masked, the integer value 2w - 1 is returned, where w represents the number of\r\nbits in the destination format.\r\nEVEX.W1 version: promotes the instruction to produce 64-bit data in 64-bit mode.\r\n\r\nOperation\r\nVCVTTSD2USI (EVEX encoded version)\r\nIF 64-Bit Mode and OperandSize = 64\r\n THEN DEST[63:0] <- Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[63:0]);\r\n ELSE DEST[31:0] <- Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[63:0]);\r\nFI\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTTSD2USI unsigned int _mm_cvttsd_u32(__m128d);\r\nVCVTTSD2USI unsigned int _mm_cvtt_roundsd_u32(__m128d, int sae);\r\nVCVTTSD2USI unsigned __int64 _mm_cvttsd_u64(__m128d);\r\nVCVTTSD2USI unsigned __int64 _mm_cvtt_roundsd_u64(__m128d, int sae);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nEVEX-encoded instructions, see Exceptions Type E3NF.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VCVTTSD2USI"
},
{
"description": "VCVTTSS2USI-Convert with Truncation Scalar Single-Precision Floating-Point Value to\r\nUnsigned Integer\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.LIG.F3.0F.W0 78 /r T1F V/V AVX512F Convert one single-precision floating-point value from\r\n VCVTTSS2USI r32, xmm1/m32{sae} xmm1/m32 to one unsigned doubleword integer in\r\n r32 using truncation.\r\n EVEX.LIG.F3.0F.W1 78 /r T1F V/N.E.1 AVX512F Convert one single-precision floating-point value from\r\n VCVTTSS2USI r64, xmm1/m32{sae} xmm1/m32 to one unsigned quadword integer in r64\r\n using truncation.\r\nNOTES:\r\n1. For this specific instruction, EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is\r\n used.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1F ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts with truncation a single-precision floating-point value in the source operand (the second operand) to an\r\nunsigned doubleword integer (or unsigned quadword integer if operand size is 64 bits) in the destination operand\r\n(the first operand). The source operand can be an XMM register or a memory location. The destination operand is\r\na general-purpose register. When the source operand is an XMM register, the single-precision floating-point value\r\nis contained in the low doubleword of the register.\r\nWhen a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR\r\nregister. If a converted result cannot be represented in the destination format, the floating-point invalid exception\r\nis raised, and if this exception is masked, the integer value 2w - 1 is returned, where w represents the number of\r\nbits in the destination format.\r\nEVEX.W1 version: promotes the instruction to produce 64-bit data in 64-bit mode.\r\nNote: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVCVTTSS2USI (EVEX encoded version)\r\nIF 64-bit Mode and OperandSize = 64\r\nTHEN\r\n DEST[63:0] <- Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[31:0]);\r\nELSE\r\n DEST[31:0] <- Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[31:0]);\r\nFI;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTTSS2USI unsigned int _mm_cvttss_u32( __m128 a);\r\nVCVTTSS2USI unsigned int _mm_cvtt_roundss_u32( __m128 a, int sae);\r\nVCVTTSS2USI unsigned __int64 _mm_cvttss_u64( __m128 a);\r\nVCVTTSS2USI unsigned __int64 _mm_cvtt_roundss_u64( __m128 a, int sae);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\n\r\nOther Exceptions\r\nEVEX-encoded instructions, see Exceptions Type E3NF.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VCVTTSS2USI"
},
{
"description": "VCVTUDQ2PD-Convert Packed Unsigned Doubleword Integers to Packed Double-Precision\r\nFloating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.F3.0F.W0 7A /r HV V/V AVX512VL Convert two packed unsigned doubleword integers\r\n VCVTUDQ2PD xmm1 {k1}{z}, AVX512F from ymm2/m64/m32bcst to packed double-precision\r\n xmm2/m64/m32bcst floating-point values in zmm1 with writemask k1.\r\n EVEX.256.F3.0F.W0 7A /r HV V/V AVX512VL Convert four packed unsigned doubleword integers\r\n VCVTUDQ2PD ymm1 {k1}{z}, AVX512F from xmm2/m128/m32bcst to packed double-\r\n xmm2/m128/m32bcst precision floating-point values in zmm1 with\r\n writemask k1.\r\n EVEX.512.F3.0F.W0 7A /r HV V/V AVX512F Convert eight packed unsigned doubleword integers\r\n VCVTUDQ2PD zmm1 {k1}{z}, from ymm2/m256/m32bcst to eight packed double-\r\n ymm2/m256/m32bcst precision floating-point values in zmm1 with\r\n writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n HV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts packed unsigned doubleword integers in the source operand (second operand) to packed double-preci-\r\nsion floating-point values in the destination operand (first operand).\r\nThe source operand is a YMM/XMM/XMM (low 64 bits) register, a 256/128/64-bit memory location or a\r\n256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM\r\nregister conditionally updated with writemask k1.\r\nAttempt to encode this instruction with EVEX embedded rounding is ignored.\r\nNote: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\nOperation\r\nVCVTUDQ2PD (EVEX encoded versions) when src operand is a register\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n k <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <-\r\n Convert_UInteger_To_Double_Precision_Floating_Point(SRC[k+31:k])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVCVTUDQ2PD (EVEX encoded versions) when src operand is a memory source\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n k <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n Convert_UInteger_To_Double_Precision_Floating_Point(SRC[31:0])\r\n ELSE\r\n DEST[i+63:i] <-\r\n Convert_UInteger_To_Double_Precision_Floating_Point(SRC[k+31:k])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTUDQ2PD __m512d _mm512_cvtepu32_pd( __m256i a);\r\nVCVTUDQ2PD __m512d _mm512_mask_cvtepu32_pd( __m512d s, __mmask8 k, __m256i a);\r\nVCVTUDQ2PD __m512d _mm512_maskz_cvtepu32_pd( __mmask8 k, __m256i a);\r\nVCVTUDQ2PD __m256d _mm256_cvtepu32_pd( __m128i a);\r\nVCVTUDQ2PD __m256d _mm256_mask_cvtepu32_pd( __m256d s, __mmask8 k, __m128i a);\r\nVCVTUDQ2PD __m256d _mm256_maskz_cvtepu32_pd( __mmask8 k, __m128i a);\r\nVCVTUDQ2PD __m128d _mm_cvtepu32_pd( __m128i a);\r\nVCVTUDQ2PD __m128d _mm_mask_cvtepu32_pd( __m128d s, __mmask8 k, __m128i a);\r\nVCVTUDQ2PD __m128d _mm_maskz_cvtepu32_pd( __mmask8 k, __m128i a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nEVEX-encoded instructions, see Exceptions Type E5.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VCVTUDQ2PD"
},
{
"description": "VCVTUDQ2PS-Convert Packed Unsigned Doubleword Integers to Packed Single-Precision\r\nFloating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.F2.0F.W0 7A /r FV V/V AVX512VL Convert four packed unsigned doubleword integers from\r\n VCVTUDQ2PS xmm1 {k1}{z}, AVX512F xmm2/m128/m32bcst to packed single-precision\r\n xmm2/m128/m32bcst floating-point values in xmm1 with writemask k1.\r\n EVEX.256.F2.0F.W0 7A /r FV V/V AVX512VL Convert eight packed unsigned doubleword integers\r\n VCVTUDQ2PS ymm1 {k1}{z}, AVX512F from ymm2/m256/m32bcst to packed single-precision\r\n ymm2/m256/m32bcst floating-point values in zmm1 with writemask k1.\r\n EVEX.512.F2.0F.W0 7A /r FV V/V AVX512F Convert sixteen packed unsigned doubleword integers\r\n VCVTUDQ2PS zmm1 {k1}{z}, from zmm2/m512/m32bcst to sixteen packed single-\r\n zmm2/m512/m32bcst{er} precision floating-point values in zmm1 with writemask\r\n k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts packed unsigned doubleword integers in the source operand (second operand) to single-precision\r\nfloating-point values in the destination operand (first operand).\r\nThe source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector\r\nbroadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally\r\nupdated with writemask k1.\r\nNote: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\nOperation\r\nVCVTUDQ2PS (EVEX encoded version) when src operand is a register\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <-\r\n Convert_UInteger_To_Single_Precision_Floating_Point(SRC[i+31:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\nVCVTUDQ2PS (EVEX encoded version) when src operand is a memory source\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n Convert_UInteger_To_Single_Precision_Floating_Point(SRC[31:0])\r\n ELSE\r\n DEST[i+31:i] <-\r\n Convert_UInteger_To_Single_Precision_Floating_Point(SRC[i+31:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTUDQ2PS __m512 _mm512_cvtepu32_ps( __m512i a);\r\nVCVTUDQ2PS __m512 _mm512_mask_cvtepu32_ps( __m512 s, __mmask16 k, __m512i a);\r\nVCVTUDQ2PS __m512 _mm512_maskz_cvtepu32_ps( __mmask16 k, __m512i a);\r\nVCVTUDQ2PS __m512 _mm512_cvt_roundepu32_ps( __m512i a, int r);\r\nVCVTUDQ2PS __m512 _mm512_mask_cvt_roundepu32_ps( __m512 s, __mmask16 k, __m512i a, int r);\r\nVCVTUDQ2PS __m512 _mm512_maskz_cvt_roundepu32_ps( __mmask16 k, __m512i a, int r);\r\nVCVTUDQ2PS __m256 _mm256_cvtepu32_ps( __m256i a);\r\nVCVTUDQ2PS __m256 _mm256_mask_cvtepu32_ps( __m256 s, __mmask8 k, __m256i a);\r\nVCVTUDQ2PS __m256 _mm256_maskz_cvtepu32_ps( __mmask8 k, __m256i a);\r\nVCVTUDQ2PS __m128 _mm_cvtepu32_ps( __m128i a);\r\nVCVTUDQ2PS __m128 _mm_mask_cvtepu32_ps( __m128 s, __mmask8 k, __m128i a);\r\nVCVTUDQ2PS __m128 _mm_maskz_cvtepu32_ps( __mmask8 k, __m128i a);\r\n\r\nSIMD Floating-Point Exceptions\r\nPrecision\r\n\r\nOther Exceptions\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VCVTUDQ2PS"
},
{
"description": "VCVTUQQ2PD-Convert Packed Unsigned Quadword Integers to Packed Double-Precision\r\nFloating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.F3.0F.W1 7A /r FV V/V AVX512VL Convert two packed unsigned quadword integers from\r\n VCVTUQQ2PD xmm1 {k1}{z}, AVX512DQ xmm2/m128/m64bcst to two packed double-precision\r\n xmm2/m128/m64bcst floating-point values in xmm1 with writemask k1.\r\n EVEX.256.F3.0F.W1 7A /r FV V/V AVX512VL Convert four packed unsigned quadword integers from\r\n VCVTUQQ2PD ymm1 {k1}{z}, AVX512DQ ymm2/m256/m64bcst to packed double-precision floating-\r\n ymm2/m256/m64bcst point values in ymm1 with writemask k1.\r\n EVEX.512.F3.0F.W1 7A /r FV V/V AVX512DQ Convert eight packed unsigned quadword integers from\r\n VCVTUQQ2PD zmm1 {k1}{z}, zmm2/m512/m64bcst to eight packed double-precision\r\n zmm2/m512/m64bcst{er} floating-point values in zmm1 with writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts packed unsigned quadword integers in the source operand (second operand) to packed double-precision\r\nfloating-point values in the destination operand (first operand).\r\nThe source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector\r\nbroadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally\r\nupdated with writemask k1.\r\nNote: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\nOperation\r\nVCVTUQQ2PD (EVEX encoded version) when src operand is a register\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL == 512) AND (EVEX.b == 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <-\r\n Convert_UQuadInteger_To_Double_Precision_Floating_Point(SRC[i+63:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\nVCVTUQQ2PD (EVEX encoded version) when src operand is a memory source\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b == 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n Convert_UQuadInteger_To_Double_Precision_Floating_Point(SRC[63:0])\r\n ELSE\r\n DEST[i+63:i] <-\r\n Convert_UQuadInteger_To_Double_Precision_Floating_Point(SRC[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTUQQ2PD __m512d _mm512_cvtepu64_ps( __m512i a);\r\nVCVTUQQ2PD __m512d _mm512_mask_cvtepu64_ps( __m512d s, __mmask8 k, __m512i a);\r\nVCVTUQQ2PD __m512d _mm512_maskz_cvtepu64_ps( __mmask8 k, __m512i a);\r\nVCVTUQQ2PD __m512d _mm512_cvt_roundepu64_ps( __m512i a, int r);\r\nVCVTUQQ2PD __m512d _mm512_mask_cvt_roundepu64_ps( __m512d s, __mmask8 k, __m512i a, int r);\r\nVCVTUQQ2PD __m512d _mm512_maskz_cvt_roundepu64_ps( __mmask8 k, __m512i a, int r);\r\nVCVTUQQ2PD __m256d _mm256_cvtepu64_ps( __m256i a);\r\nVCVTUQQ2PD __m256d _mm256_mask_cvtepu64_ps( __m256d s, __mmask8 k, __m256i a);\r\nVCVTUQQ2PD __m256d _mm256_maskz_cvtepu64_ps( __mmask8 k, __m256i a);\r\nVCVTUQQ2PD __m128d _mm_cvtepu64_ps( __m128i a);\r\nVCVTUQQ2PD __m128d _mm_mask_cvtepu64_ps( __m128d s, __mmask8 k, __m128i a);\r\nVCVTUQQ2PD __m128d _mm_maskz_cvtepu64_ps( __mmask8 k, __m128i a);\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nPrecision\r\n\r\nOther Exceptions\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VCVTUQQ2PD"
},
{
"description": "VCVTUQQ2PS-Convert Packed Unsigned Quadword Integers to Packed Single-Precision\r\nFloating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.F2.0F.W1 7A /r FV V/V AVX512VL Convert two packed unsigned quadword integers from\r\n VCVTUQQ2PS xmm1 {k1}{z}, AVX512DQ xmm2/m128/m64bcst to packed single-precision floating-\r\n xmm2/m128/m64bcst point values in zmm1 with writemask k1.\r\n EVEX.256.F2.0F.W1 7A /r FV V/V AVX512VL Convert four packed unsigned quadword integers from\r\n VCVTUQQ2PS xmm1 {k1}{z}, AVX512DQ ymm2/m256/m64bcst to packed single-precision floating-\r\n ymm2/m256/m64bcst point values in xmm1 with writemask k1.\r\n EVEX.512.F2.0F.W1 7A /r FV V/V AVX512DQ Convert eight packed unsigned quadword integers from\r\n VCVTUQQ2PS ymm1 {k1}{z}, zmm2/m512/m64bcst to eight packed single-precision\r\n zmm2/m512/m64bcst{er} floating-point values in zmm1 with writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts packed unsigned quadword integers in the source operand (second operand) to single-precision floating-\r\npoint values in the destination operand (first operand).\r\nEVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location.\r\nThe destination operand is a YMM/XMM/XMM (low 64 bits) register conditionally updated with writemask k1.\r\nNote: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\nOperation\r\nVCVTUQQ2PS (EVEX encoded version) when src operand is a register\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n k <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <-\r\n Convert_UQuadInteger_To_Single_Precision_Floating_Point(SRC[k+63:k])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL/2] <- 0\r\n\r\n\r\n\r\n\r\nVCVTUQQ2PS (EVEX encoded version) when src operand is a memory source\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n k <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n Convert_UQuadInteger_To_Single_Precision_Floating_Point(SRC[63:0])\r\n ELSE\r\n DEST[i+31:i] <-\r\n Convert_UQuadInteger_To_Single_Precision_Floating_Point(SRC[k+63:k])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL/2] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTUQQ2PS __m256 _mm512_cvtepu64_ps( __m512i a);\r\nVCVTUQQ2PS __m256 _mm512_mask_cvtepu64_ps( __m256 s, __mmask8 k, __m512i a);\r\nVCVTUQQ2PS __m256 _mm512_maskz_cvtepu64_ps( __mmask8 k, __m512i a);\r\nVCVTUQQ2PS __m256 _mm512_cvt_roundepu64_ps( __m512i a, int r);\r\nVCVTUQQ2PS __m256 _mm512_mask_cvt_roundepu64_ps( __m256 s, __mmask8 k, __m512i a, int r);\r\nVCVTUQQ2PS __m256 _mm512_maskz_cvt_roundepu64_ps( __mmask8 k, __m512i a, int r);\r\nVCVTUQQ2PS __m128 _mm256_cvtepu64_ps( __m256i a);\r\nVCVTUQQ2PS __m128 _mm256_mask_cvtepu64_ps( __m128 s, __mmask8 k, __m256i a);\r\nVCVTUQQ2PS __m128 _mm256_maskz_cvtepu64_ps( __mmask8 k, __m256i a);\r\nVCVTUQQ2PS __m128 _mm_cvtepu64_ps( __m128i a);\r\nVCVTUQQ2PS __m128 _mm_mask_cvtepu64_ps( __m128 s, __mmask8 k, __m128i a);\r\nVCVTUQQ2PS __m128 _mm_maskz_cvtepu64_ps( __mmask8 k, __m128i a);\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nPrecision\r\n\r\nOther Exceptions\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VCVTUQQ2PS"
},
{
"description": "VCVTUSI2SD-Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.LIG.F2.0F.W0 7B /r T1S V/V AVX512F Convert one unsigned doubleword integer from\r\n VCVTUSI2SD xmm1, xmm2, r/m32 r/m32 to one double-precision floating-point value in\r\n xmm1.\r\n EVEX.NDS.LIG.F2.0F.W1 7B /r T1S V/N.E.1 AVX512F Convert one unsigned quadword integer from r/m64\r\n VCVTUSI2SD xmm1, xmm2, r/m64{er} to one double-precision floating-point value in xmm1.\r\nNOTES:\r\n1. For this specific instruction, EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is\r\n used.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nConverts an unsigned doubleword integer (or unsigned quadword integer if operand size is 64 bits) in the second\r\nsource operand to a double-precision floating-point value in the destination operand. The result is stored in the low\r\nquadword of the destination operand. When conversion is inexact, the value returned is rounded according to the\r\nrounding control bits in the MXCSR register.\r\nThe second source operand can be a general-purpose register or a 32/64-bit memory location. The first source and\r\ndestination operands are XMM registers. Bits (127:64) of the XMM register destination are copied from corre-\r\nsponding bits in the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.\r\nEVEX.W1 version: promotes the instruction to use 64-bit input value in 64-bit mode.\r\nEVEX.W0 version: attempt to encode this instruction with EVEX embedded rounding is ignored.\r\n\r\nOperation\r\nVCVTUSI2SD (EVEX encoded version)\r\nIF (SRC2 *is register*) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF 64-Bit Mode And OperandSize = 64\r\nTHEN\r\n DEST[63:0] <- Convert_UInteger_To_Double_Precision_Floating_Point(SRC2[63:0]);\r\nELSE\r\n DEST[63:0] <- Convert_UInteger_To_Double_Precision_Floating_Point(SRC2[31:0]);\r\nFI;\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTUSI2SD __m128d _mm_cvtu32_sd( __m128d s, unsigned a);\r\nVCVTUSI2SD __m128d _mm_cvtu64_sd( __m128d s, unsigned __int64 a);\r\nVCVTUSI2SD __m128d _mm_cvt_roundu64_sd( __m128d s, unsigned __int64 a, int r);\r\n\r\nSIMD Floating-Point Exceptions\r\nPrecision\r\n\r\nOther Exceptions\r\nSee Exceptions Type E3NF if W1, else type E10NF.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VCVTUSI2SD"
},
{
"description": "VCVTUSI2SS-Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.LIG.F3.0F.W0 7B /r T1S V/V AVX512F Convert one signed doubleword integer from r/m32 to\r\n VCVTUSI2SS xmm1, xmm2, r/m32{er} one single-precision floating-point value in xmm1.\r\n EVEX.NDS.LIG.F3.0F.W1 7B /r T1S V/N.E.1 AVX512F Convert one signed quadword integer from r/m64 to\r\n VCVTUSI2SS xmm1, xmm2, r/m64{er} one single-precision floating-point value in xmm1.\r\nNOTES:\r\n1. For this specific instruction, EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is\r\n used.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nConverts a unsigned doubleword integer (or unsigned quadword integer if operand size is 64 bits) in the source\r\noperand (second operand) to a single-precision floating-point value in the destination operand (first operand). The\r\nsource operand can be a general-purpose register or a memory location. The destination operand is an XMM\r\nregister. The result is stored in the low doubleword of the destination operand. When a conversion is inexact, the\r\nvalue returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding\r\ncontrol bits.\r\nThe second source operand can be a general-purpose register or a 32/64-bit memory location. The first source and\r\ndestination operands are XMM registers. Bits (127:32) of the XMM register destination are copied from corre-\r\nsponding bits in the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.\r\nEVEX.W1 version: promotes the instruction to use 64-bit input value in 64-bit mode.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVCVTUSI2SS (EVEX encoded version)\r\nIF (SRC2 *is register*) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF 64-Bit Mode And OperandSize = 64\r\nTHEN\r\n DEST[31:0] <- Convert_UInteger_To_Single_Precision_Floating_Point(SRC[63:0]);\r\nELSE\r\n DEST[31:0] <- Convert_UInteger_To_Single_Precision_Floating_Point(SRC[31:0]);\r\nFI;\r\nDEST[127:32] <- SRC1[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVCVTUSI2SS __m128 _mm_cvtu32_ss( __m128 s, unsigned a);\r\nVCVTUSI2SS __m128 _mm_cvt_roundu32_ss( __m128 s, unsigned a, int r);\r\nVCVTUSI2SS __m128 _mm_cvtu64_ss( __m128 s, unsigned __int64 a);\r\nVCVTUSI2SS __m128 _mm_cvt_roundu64_ss( __m128 s, unsigned __int64 a, int r);\r\n\r\nSIMD Floating-Point Exceptions\r\nPrecision\r\n\r\nOther Exceptions\r\nSee Exceptions Type E3NF.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VCVTUSI2SS"
},
{
"description": "VDBPSADBW-Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned Bytes\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.128.66.0F3A.W0 42 /r ib FVM V/V AVX512VL Compute packed SAD word results of unsigned bytes in\r\n VDBPSADBW xmm1 {k1}{z}, xmm2, AVX512BW dword block from xmm2 with unsigned bytes of dword\r\n xmm3/m128, imm8 blocks transformed from xmm3/m128 using the shuffle\r\n controls in imm8. Results are written to xmm1 under the\r\n writemask k1.\r\n EVEX.NDS.256.66.0F3A.W0 42 /r ib FVM V/V AVX512VL Compute packed SAD word results of unsigned bytes in\r\n VDBPSADBW ymm1 {k1}{z}, ymm2, AVX512BW dword block from ymm2 with unsigned bytes of dword\r\n ymm3/m256, imm8 blocks transformed from ymm3/m256 using the shuffle\r\n controls in imm8. Results are written to ymm1 under the\r\n writemask k1.\r\n EVEX.NDS.512.66.0F3A.W0 42 /r ib FVM V/V AVX512BW Compute packed SAD word results of unsigned bytes in\r\n VDBPSADBW zmm1 {k1}{z}, zmm2, dword block from zmm2 with unsigned bytes of dword\r\n zmm3/m512, imm8 blocks transformed from zmm3/m512 using the shuffle\r\n controls in imm8. Results are written to zmm1 under the\r\n writemask k1.\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FVM ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) Imm8\r\n\r\nDescription\r\nCompute packed SAD (sum of absolute differences) word results of unsigned bytes from two 32-bit dword\r\nelements. Packed SAD word results are calculated in multiples of qword superblocks, producing 4 SAD word results\r\nin each 64-bit superblock of the destination register.\r\nWithin each super block of packed word results, the SAD results from two 32-bit dword elements are calculated as\r\nfollows:\r\n. The lower two word results are calculated each from the SAD operation between a sliding dword element within\r\n a qword superblock from an intermediate vector with a stationary dword element in the corresponding qword\r\n superblock of the first source operand. The intermediate vector, see \"Tmp1\" in Figure 5-8, is constructed from\r\n the second source operand the imm8 byte as shuffle control to select dword elements within a 128-bit lane of\r\n the second source operand. The two sliding dword elements in a qword superblock of Tmp1 are located at byte\r\n offset 0 and 1 within the superblock, respectively. The stationary dword element in the qword superblock from\r\n the first source operand is located at byte offset 0.\r\n. The next two word results are calculated each from the SAD operation between a sliding dword element within\r\n a qword superblock from the intermediate vector Tmp1 with a second stationary dword element in the corre-\r\n sponding qword superblock of the first source operand. The two sliding dword elements in a qword superblock\r\n of Tmp1 are located at byte offset 2and 3 within the superblock, respectively. The stationary dword element in\r\n the qword superblock from the first source operand is located at byte offset 4.\r\n. The intermediate vector is constructed in 128-bits lanes. Within each 128-bit lane, each dword element of the\r\n intermediate vector is selected by a two-bit field within the imm8 byte on the corresponding 128-bits of the\r\n second source operand. The imm8 byte serves as dword shuffle control within each 128-bit lanes of the inter-\r\n mediate vector and the second source operand, similarly to PSHUFD.\r\nThe first source operand is a ZMM/YMM/XMM register. The second source operand is a ZMM/YMM/XMM register, or\r\na 512/256/128-bit memory location. The destination operand is conditionally updated based on writemask k1 at\r\n16-bit word granularity.\r\n\r\n\r\n\r\n\r\n\r\n 127+128*n 95+128*n 63+128*n 31+128*n 128*n\r\n 128-bit Lane of Src2 DW3 DW2 DW1 DW0\r\n\r\n\r\n 00B: DW0\r\n 01B: DW1\r\n imm8 shuffle control 10B: DW2\r\n 11B: DW3\r\n 7 5 3 1 0\r\n\r\n\r\n\r\n 127+128*n 95+128*n 63+128*n 31+128*n 128*n\r\n 128-bit Lane of Tmp1\r\n\r\n Tmp1 qword superblock\r\n\r\n\r\n\r\n\r\n 55 47 39 31 24 39 31 23 15 8\r\n Tmp1 sliding dword Tmp1 sliding dword\r\n\r\n 63 55 47 39 32 31 23 15 7 0\r\n Src1 stationary dword 0\r\n Src1 stationary dword 1\r\n _ _ _ _ _ _ _ _\r\n abs abs abs abs abs abs abs abs\r\n\r\n\r\n\r\n\r\n + 47 39 31 23 16 +\r\n 31 23 15 7 0\r\n Tmp1 sliding dword\r\n Tmp1 sliding dword\r\n 63 55 47 39 32\r\n 31 23 15 7 0\r\n Src1 stationary dword 1\r\n Src1 stationary dword 0\r\n _ _ _ _\r\n _ _ _ _\r\n abs abs abs abs\r\n abs abs abs abs\r\n\r\n\r\n\r\n\r\n +\r\n +\r\n 63 47 31 15 0\r\n Destination qword superblock\r\n\r\n\r\n\r\n\r\n Figure 5-8. 64-bit Super Block of SAD Operation in VDBPSADBW\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVDBPSADBW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nSelection of quadruplets:\r\nFOR I = 0 to VL step 128\r\n TMP1[I+31:I] <- select (SRC2[I+127: I], imm8[1:0])\r\n TMP1[I+63: I+32] <- select (SRC2[I+127: I], imm8[3:2])\r\n TMP1[I+95: I+64] <- select (SRC2[I+127: I], imm8[5:4])\r\n TMP1[I+127: I+96]<- select (SRC2[I+127: I], imm8[7:6])\r\nEND FOR\r\n\r\nSAD of quadruplets:\r\n\r\nFOR I =0 to VL step 64\r\n TMP_DEST[I+15:I] <- ABS(SRC1[I+7: I] - TMP1[I+7: I]) +\r\n ABS(SRC1[I+15: I+8]- TMP1[I+15: I+8]) +\r\n ABS(SRC1[I+23: I+16]- TMP1[I+23: I+16]) +\r\n ABS(SRC1[I+31: I+24]- TMP1[I+31: I+24])\r\n\r\n TMP_DEST[I+31: I+16] <-ABS(SRC1[I+7: I] - TMP1[I+15: I+8]) +\r\n ABS(SRC1[I+15: I+8]- TMP1[I+23: I+16]) +\r\n ABS(SRC1[I+23: I+16]- TMP1[I+31: I+24]) +\r\n ABS(SRC1[I+31: I+24]- TMP1[I+39: I+32])\r\n TMP_DEST[I+47: I+32] <-ABS(SRC1[I+39: I+32] - TMP1[I+23: I+16]) +\r\n ABS(SRC1[I+47: I+40]- TMP1[I+31: I+24]) +\r\n ABS(SRC1[I+55: I+48]- TMP1[I+39: I+32]) +\r\n ABS(SRC1[I+63: I+56]- TMP1[I+47: I+40])\r\n\r\n TMP_DEST[I+63: I+48] <-ABS(SRC1[I+39: I+32] - TMP1[I+31: I+24]) +\r\n ABS(SRC1[I+47: I+40] - TMP1[I+39: I+32]) +\r\n ABS(SRC1[I+55: I+48] - TMP1[I+47: I+40]) +\r\n ABS(SRC1[I+63: I+56] - TMP1[I+55: I+48])\r\nENDFOR\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- TMP_DEST[i+15:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVDBPSADBW __m512i _mm512_dbsad_epu8(__m512i a, __m512i b);\r\nVDBPSADBW __m512i _mm512_mask_dbsad_epu8(__m512i s, __mmask32 m, __m512i a, __m512i b);\r\nVDBPSADBW __m512i _mm512_maskz_dbsad_epu8(__mmask32 m, __m512i a, __m512i b);\r\nVDBPSADBW __m256i _mm256_dbsad_epu8(__m256i a, __m256i b);\r\nVDBPSADBW __m256i _mm256_mask_dbsad_epu8(__m256i s, __mmask16 m, __m256i a, __m256i b);\r\nVDBPSADBW __m256i _mm256_maskz_dbsad_epu8(__mmask16 m, __m256i a, __m256i b);\r\nVDBPSADBW __m128i _mm_dbsad_epu8(__m128i a, __m128i b);\r\nVDBPSADBW __m128i _mm_mask_dbsad_epu8(__m128i s, __mmask8 m, __m128i a, __m128i b);\r\nVDBPSADBW __m128i _mm_maskz_dbsad_epu8(__mmask8 m, __m128i a, __m128i b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type E4NF.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VDBPSADBW"
},
{
"description": "VERR/VERW-Verify a Segment for Reading or Writing\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F 00 /4 VERR r/m16 M Valid Valid Set ZF=1 if segment specified with r/m16 can\r\n be read.\r\n 0F 00 /5 VERW r/m16 M Valid Valid Set ZF=1 if segment specified with r/m16 can\r\n be written.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (r) NA NA NA\r\n\r\n\r\nDescription\r\nVerifies whether the code or data segment specified with the source operand is readable (VERR) or writable\r\n(VERW) from the current privilege level (CPL). The source operand is a 16-bit register or a memory location that\r\ncontains the segment selector for the segment to be verified. If the segment is accessible and readable (VERR) or\r\nwritable (VERW), the ZF flag is set; otherwise, the ZF flag is cleared. Code segments are never verified as writable.\r\nThis check cannot be performed on system segments.\r\nTo set the ZF flag, the following conditions must be met:\r\n. The segment selector is not NULL.\r\n. The selector must denote a descriptor within the bounds of the descriptor table (GDT or LDT).\r\n. The selector must denote the descriptor of a code or data segment (not that of a system segment or gate).\r\n. For the VERR instruction, the segment must be readable.\r\n. For the VERW instruction, the segment must be a writable data segment.\r\n. If the segment is not a conforming code segment, the segment's DPL must be greater than or equal to (have\r\n less or the same privilege as) both the CPL and the segment selector's RPL.\r\nThe validation performed is the same as is performed when a segment selector is loaded into the DS, ES, FS, or GS\r\nregister, and the indicated access (read or write) is performed. The segment selector's value cannot result in a\r\nprotection exception, enabling the software to anticipate possible segment access problems.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode. The operand size is fixed at 16 bits.\r\n\r\nOperation\r\nIF SRC(Offset) > (GDTR(Limit) or (LDTR(Limit))\r\n THEN ZF <- 0; FI;\r\n\r\nRead segment descriptor;\r\n\r\nIF SegmentDescriptor(DescriptorType) = 0 (* System segment *)\r\nor (SegmentDescriptor(Type) != conforming code segment)\r\nand (CPL > DPL) or (RPL > DPL)\r\n THEN\r\n ZF <- 0;\r\n ELSE\r\n IF ((Instruction = VERR) and (Segment readable))\r\n or ((Instruction = VERW) and (Segment writable))\r\n THEN\r\n ZF <- 1;\r\n FI;\r\nFI;\r\n\r\n\r\n\r\n\r\nFlags Affected\r\nThe ZF flag is set to 1 if the segment is accessible and readable (VERR) or writable (VERW); otherwise, it is set to 0.\r\n\r\nProtected Mode Exceptions\r\nThe only exceptions generated for these instructions are those related to illegal addressing of the source operand.\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment\r\n selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#UD The VERR and VERW instructions are not recognized in real-address mode.\r\n If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD The VERR and VERW instructions are not recognized in virtual-8086 mode.\r\n If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VERR"
},
{
"description": "-R:VERR",
"mnem": "VERW"
},
{
"description": "VEXP2PD-Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point\r\nValues with Less Than 2^-23 Relative Error\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.512.66.0F38.W1 C8 /r FV V/V AVX512ER Computes approximations to the exponential 2^x (with less\r\n VEXP2PD zmm1 {k1}{z}, than 2^-23 of maximum relative error) of the packed double-\r\n zmm2/m512/m64bcst {sae} precision floating-point values from zmm2/m512/m64bcst and\r\n stores the floating-point result in zmm1with writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nComputes the approximate base-2 exponential evaluation of the double-precision floating-point values in the\r\nsource operand (the second operand) and stores the results to the destination operand (the first operand) using\r\nthe writemask k1. The approximate base-2 exponential is evaluated with less than 2^-23 of relative error.\r\nDenormal input values are treated as zeros and do not signal #DE, irrespective of MXCSR.DAZ. Denormal results\r\nare flushed to zeros and do not signal #UE, irrespective of MXCSR.FZ.\r\nThe source operand is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit\r\nmemory location. The destination operand is a ZMM register, conditionally updated using writemask k1.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\nA numerically exact implementation of VEXP2xx can be found at https://software.intel.com/en-us/articles/refer-\r\nence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.\r\n\r\nOperation\r\nVEXP2PD\r\n(KL, VL) = (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC *is memory*)\r\n THEN DEST[i+63:i] <- EXP2_23_DP(SRC[63:0])\r\n ELSE DEST[i+63:i] <- EXP2_23_DP(SRC[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI;\r\n FI;\r\nENDFOR;\r\n\r\n\r\n\r\n\r\n\r\n Table 5-4. Special Values Behavior\r\n Source Input Result Comments\r\n NaN QNaN(src) If (SRC = SNaN) then #I\r\n +inf +inf\r\n +/-0 1.0f Exact result\r\n -inf +0.0f\r\n Integral value N 2^ (N) Exact result\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVEXP2PD __m512d _mm512_exp2a23_round_pd (__m512d a, int sae);\r\nVEXP2PD __m512d _mm512_mask_exp2a23_round_pd (__m512d a, __mmask8 m, __m512d b, int sae);\r\nVEXP2PD __m512d _mm512_maskz_exp2a23_round_pd ( __mmask8 m, __m512d b, int sae);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid (if SNaN input), Overflow\r\n\r\nOther Exceptions\r\nSee Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VEXP2PD"
},
{
"description": "VEXP2PS-Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point\r\nValues with Less Than 2^-23 Relative Error\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.512.66.0F38.W0 C8 /r FV V/V AVX512ER Computes approximations to the exponential 2^x (with less\r\n VEXP2PS zmm1 {k1}{z}, than 2^-23 of maximum relative error) of the packed single-\r\n zmm2/m512/m32bcst {sae} precision floating-point values from zmm2/m512/m32bcst and\r\n stores the floating-point result in zmm1with writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nComputes the approximate base-2 exponential evaluation of the single-precision floating-point values in the\r\nsource operand (the second operand) and store the results in the destination operand (the first operand) using the\r\nwritemask k1. The approximate base-2 exponential is evaluated with less than 2^-23 of relative error.\r\nDenormal input values are treated as zeros and do not signal #DE, irrespective of MXCSR.DAZ. Denormal results\r\nare flushed to zeros and do not signal #UE, irrespective of MXCSR.FZ.\r\nThe source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit\r\nmemory location. The destination operand is a ZMM register, conditionally updated using writemask k1.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\nA numerically exact implementation of VEXP2xx can be found at https://software.intel.com/en-us/articles/refer-\r\nence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.\r\n\r\nOperation\r\nVEXP2PS\r\n(KL, VL) = (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC *is memory*)\r\n THEN DEST[i+31:i] <- EXP2_23_SP(SRC[31:0])\r\n ELSE DEST[i+31:i] <- EXP2_23_SP(SRC[i+31:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI;\r\n FI;\r\nENDFOR;\r\n\r\n\r\n\r\n\r\n\r\n Table 5-5. Special Values Behavior\r\n Source Input Result Comments\r\n NaN QNaN(src) If (SRC = SNaN) then #I\r\n +inf +inf\r\n +/-0 1.0f Exact result\r\n -inf +0.0f\r\n Integral value N 2^ (N) Exact result\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVEXP2PS __m512 _mm512_exp2a23_round_ps (__m512 a, int sae);\r\nVEXP2PS __m512 _mm512_mask_exp2a23_round_ps (__m512 a, __mmask16 m, __m512 b, int sae);\r\nVEXP2PS __m512 _mm512_maskz_exp2a23_round_ps (__mmask16 m, __m512 b, int sae);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid (if SNaN input), Overflow\r\n\r\nOther Exceptions\r\nSee Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VEXP2PS"
},
{
"description": "VEXPANDPD-Load Sparse Packed Double-Precision Floating-Point Values from Dense Memory\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F38.W1 88 /r T1S V/V AVX512VL Expand packed double-precision floating-point values\r\n VEXPANDPD xmm1 {k1}{z}, AVX512F from xmm2/m128 to xmm1 using writemask k1.\r\n xmm2/m128\r\n EVEX.256.66.0F38.W1 88 /r T1S V/V AVX512VL Expand packed double-precision floating-point values\r\n VEXPANDPD ymm1 {k1}{z}, ymm2/m256 AVX512F from ymm2/m256 to ymm1 using writemask k1.\r\n EVEX.512.66.0F38.W1 88 /r T1S V/V AVX512F Expand packed double-precision floating-point values\r\n VEXPANDPD zmm1 {k1}{z}, zmm2/m512 from zmm2/m512 to zmm1 using writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nExpand (load) up to 8/4/2, contiguous, double-precision floating-point values of the input vector in the source\r\noperand (the second operand) to sparse elements in the destination operand (the first operand) selected by the\r\nwritemask k1.\r\nThe destination operand is a ZMM/YMM/XMM register, the source operand can be a ZMM/YMM/XMM register or a\r\n512/256/128-bit memory location.\r\nThe input vector starts from the lowest element in the source operand. The writemask register k1 selects the desti-\r\nnation elements (a partial vector or sparse elements if less than 8 elements) to be replaced by the ascending\r\nelements in the input vector. Destination elements not selected by the writemask k1 are either unmodified or\r\nzeroed, depending on EVEX.z.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\nNote that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element\r\ninstead of the size of the full vector.\r\n\r\nOperation\r\nVEXPANDPD (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nk<-0\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n DEST[i+63:i] <- SRC[k+63:k];\r\n k <- k + 64\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVEXPANDPD __m512d _mm512_mask_expand_pd( __m512d s, __mmask8 k, __m512d a);\r\nVEXPANDPD __m512d _mm512_maskz_expand_pd( __mmask8 k, __m512d a);\r\nVEXPANDPD __m512d _mm512_mask_expandloadu_pd( __m512d s, __mmask8 k, void * a);\r\nVEXPANDPD __m512d _mm512_maskz_expandloadu_pd( __mmask8 k, void * a);\r\nVEXPANDPD __m256d _mm256_mask_expand_pd( __m256d s, __mmask8 k, __m256d a);\r\nVEXPANDPD __m256d _mm256_maskz_expand_pd( __mmask8 k, __m256d a);\r\nVEXPANDPD __m256d _mm256_mask_expandloadu_pd( __m256d s, __mmask8 k, void * a);\r\nVEXPANDPD __m256d _mm256_maskz_expandloadu_pd( __mmask8 k, void * a);\r\nVEXPANDPD __m128d _mm_mask_expand_pd( __m128d s, __mmask8 k, __m128d a);\r\nVEXPANDPD __m128d _mm_maskz_expand_pd( __mmask8 k, __m128d a);\r\nVEXPANDPD __m128d _mm_mask_expandloadu_pd( __m128d s, __mmask8 k, void * a);\r\nVEXPANDPD __m128d _mm_maskz_expandloadu_pd( __mmask8 k, void * a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type E4.nb.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VEXPANDPD"
},
{
"description": "VEXPANDPS-Load Sparse Packed Single-Precision Floating-Point Values from Dense Memory\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F38.W0 88 /r T1S V/V AVX512VL Expand packed single-precision floating-point values\r\n VEXPANDPS xmm1 {k1}{z}, xmm2/m128 AVX512F from xmm2/m128 to xmm1 using writemask k1.\r\n EVEX.256.66.0F38.W0 88 /r T1S V/V AVX512VL Expand packed single-precision floating-point values\r\n VEXPANDPS ymm1 {k1}{z}, ymm2/m256 AVX512F from ymm2/m256 to ymm1 using writemask k1.\r\n EVEX.512.66.0F38.W0 88 /r T1S V/V AVX512F Expand packed single-precision floating-point values\r\n VEXPANDPS zmm1 {k1}{z}, zmm2/m512 from zmm2/m512 to zmm1 using writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nExpand (load) up to 16/8/4, contiguous, single-precision floating-point values of the input vector in the source\r\noperand (the second operand) to sparse elements of the destination operand (the first operand) selected by the\r\nwritemask k1.\r\nThe destination operand is a ZMM/YMM/XMM register, the source operand can be a ZMM/YMM/XMM register or a\r\n512/256/128-bit memory location.\r\nThe input vector starts from the lowest element in the source operand. The writemask k1 selects the destination\r\nelements (a partial vector or sparse elements if less than 16 elements) to be replaced by the ascending elements\r\nin the input vector. Destination elements not selected by the writemask k1 are either unmodified or zeroed,\r\ndepending on EVEX.z.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\nNote that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element\r\ninstead of the size of the full vector.\r\n\r\nOperation\r\nVEXPANDPS (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nk<-0\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n DEST[i+31:i] <- SRC[k+31:k];\r\n k <- k + 32\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVEXPANDPS __m512 _mm512_mask_expand_ps( __m512 s, __mmask16 k, __m512 a);\r\nVEXPANDPS __m512 _mm512_maskz_expand_ps( __mmask16 k, __m512 a);\r\nVEXPANDPS __m512 _mm512_mask_expandloadu_ps( __m512 s, __mmask16 k, void * a);\r\nVEXPANDPS __m512 _mm512_maskz_expandloadu_ps( __mmask16 k, void * a);\r\nVEXPANDPD __m256 _mm256_mask_expand_ps( __m256 s, __mmask8 k, __m256 a);\r\nVEXPANDPD __m256 _mm256_maskz_expand_ps( __mmask8 k, __m256 a);\r\nVEXPANDPD __m256 _mm256_mask_expandloadu_ps( __m256 s, __mmask8 k, void * a);\r\nVEXPANDPD __m256 _mm256_maskz_expandloadu_ps( __mmask8 k, void * a);\r\nVEXPANDPD __m128 _mm_mask_expand_ps( __m128 s, __mmask8 k, __m128 a);\r\nVEXPANDPD __m128 _mm_maskz_expand_ps( __mmask8 k, __m128 a);\r\nVEXPANDPD __m128 _mm_mask_expandloadu_ps( __m128 s, __mmask8 k, void * a);\r\nVEXPANDPD __m128 _mm_maskz_expandloadu_ps( __mmask8 k, void * a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type E4.nb.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VEXPANDPS"
},
{
"description": "VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4-Extr\r\nact Packed Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.256.66.0F3A.W0 19 /r ib RMI V/V AVX Extract 128 bits of packed floating-point values\r\n VEXTRACTF128 xmm1/m128, ymm2, from ymm2 and store results in xmm1/m128.\r\n imm8\r\n EVEX.256.66.0F3A.W0 19 /r ib T4 V/V AVX512VL Extract 128 bits of packed single-precision floating-\r\n VEXTRACTF32X4 xmm1/m128 {k1}{z}, AVX512F point values from ymm2 and store results in\r\n ymm2, imm8 xmm1/m128 subject to writemask k1.\r\n EVEX.512.66.0F3A.W0 19 /r ib T4 V/V AVX512F Extract 128 bits of packed single-precision floating-\r\n VEXTRACTF32x4 xmm1/m128 {k1}{z}, point values from zmm2 and store results in\r\n zmm2, imm8 xmm1/m128 subject to writemask k1.\r\n EVEX.256.66.0F3A.W1 19 /r ib T2 V/V AVX512VL Extract 128 bits of packed double-precision\r\n VEXTRACTF64X2 xmm1/m128 {k1}{z}, AVX512DQ floating-point values from ymm2 and store results\r\n ymm2, imm8 in xmm1/m128 subject to writemask k1.\r\n EVEX.512.66.0F3A.W1 19 /r ib T2 V/V AVX512DQ Extract 128 bits of packed double-precision\r\n VEXTRACTF64X2 xmm1/m128 {k1}{z}, floating-point values from zmm2 and store results\r\n zmm2, imm8 in xmm1/m128 subject to writemask k1.\r\n EVEX.512.66.0F3A.W0 1B /r ib T8 V/V AVX512DQ Extract 256 bits of packed single-precision floating-\r\n VEXTRACTF32X8 ymm1/m256 {k1}{z}, point values from zmm2 and store results in\r\n zmm2, imm8 ymm1/m256 subject to writemask k1.\r\n EVEX.512.66.0F3A.W1 1B /r ib T4 V/V AVX512F Extract 256 bits of packed double-precision\r\n VEXTRACTF64x4 ymm1/m256 {k1}{z}, floating-point values from zmm2 and store results\r\n zmm2, imm8 in ymm1/m256 subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:r/m (w) ModRM:reg (r) Imm8 NA\r\n T2, T4, T8 ModRM:r/m (w) ModRM:reg (r) Imm8 NA\r\n\r\nDescription\r\nVEXTRACTF128/VEXTRACTF32x4 and VEXTRACTF64x2 extract 128-bits of single-precision floating-point values\r\nfrom the source operand (the second operand) and store to the low 128-bit of the destination operand (the first\r\noperand). The 128-bit data extraction occurs at an 128-bit granular offset specified by imm8[0] (256-bit) or\r\nimm8[1:0] as the multiply factor. The destination may be either a vector register or an 128-bit memory location.\r\nVEXTRACTF32x4: The low 128-bit of the destination operand is updated at 32-bit granularity according to the\r\nwritemask.\r\nVEXTRACTF32x8 and VEXTRACTF64x4 extract 256-bits of double-precision floating-point values from the source\r\noperand (second operand) and store to the low 256-bit of the destination operand (the first operand). The 256-bit\r\ndata extraction occurs at an 256-bit granular offset specified by imm8[0] (256-bit) or imm8[0] as the multiply\r\nfactor The destination may be either a vector register or a 256-bit memory location.\r\nVEXTRACTF64x4: The low 256-bit of the destination operand is updated at 64-bit granularity according to the\r\nwritemask.\r\nVEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\nThe high 6 bits of the immediate are ignored.\r\nIf VEXTRACTF128 is encoded with VEX.L= 0, an attempt to execute the instruction encoded with VEX.L= 0 will\r\ncause an #UD exception.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVEXTRACTF32x4 (EVEX encoded versions) when destination is a register\r\nVL = 256, 512\r\nIF VL = 256\r\n CASE (imm8[0]) OF\r\n 0: TMP_DEST[127:0] <- SRC1[127:0]\r\n 1: TMP_DEST[127:0] <- SRC1[255:128]\r\n ESAC.\r\nFI;\r\nIF VL = 512\r\n CASE (imm8[1:0]) OF\r\n 00: TMP_DEST[127:0] <- SRC1[127:0]\r\n 01: TMP_DEST[127:0] <- SRC1[255:128]\r\n 10: TMP_DEST[127:0] <- SRC1[383:256]\r\n 11: TMP_DEST[127:0] <- SRC1[511:384]\r\n ESAC.\r\nFI;\r\nFOR j <- 0 TO 3\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_DEST[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVEXTRACTF32x4 (EVEX encoded versions) when destination is memory\r\nVL = 256, 512\r\nIF VL = 256\r\n CASE (imm8[0]) OF\r\n 0: TMP_DEST[127:0] <- SRC1[127:0]\r\n 1: TMP_DEST[127:0] <- SRC1[255:128]\r\n ESAC.\r\nFI;\r\nIF VL = 512\r\n CASE (imm8[1:0]) OF\r\n 00: TMP_DEST[127:0] <- SRC1[127:0]\r\n 01: TMP_DEST[127:0] <- SRC1[255:128]\r\n 10: TMP_DEST[127:0] <- SRC1[383:256]\r\n 11: TMP_DEST[127:0] <- SRC1[511:384]\r\n ESAC.\r\nFI;\r\n\r\nFOR j <- 0 TO 3\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_DEST[i+31:i]\r\n ELSE *DEST[i+31:i] remains unchanged* ; merging-masking\r\n FI;\r\nENDFOR\r\n\r\n\r\n\r\n\r\n\r\nVEXTRACTF64x2 (EVEX encoded versions) when destination is a register\r\nVL = 256, 512\r\nIF VL = 256\r\n CASE (imm8[0]) OF\r\n 0: TMP_DEST[127:0] <- SRC1[127:0]\r\n 1: TMP_DEST[127:0] <- SRC1[255:128]\r\n ESAC.\r\nFI;\r\nIF VL = 512\r\n CASE (imm8[1:0]) OF\r\n 00: TMP_DEST[127:0] <- SRC1[127:0]\r\n 01: TMP_DEST[127:0] <- SRC1[255:128]\r\n 10: TMP_DEST[127:0] <- SRC1[383:256]\r\n 11: TMP_DEST[127:0] <- SRC1[511:384]\r\n ESAC.\r\nFI;\r\n\r\nFOR j <- 0 TO 1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVEXTRACTF64x2 (EVEX encoded versions) when destination is memory\r\nVL = 256, 512\r\nIF VL = 256\r\n CASE (imm8[0]) OF\r\n 0: TMP_DEST[127:0] <- SRC1[127:0]\r\n 1: TMP_DEST[127:0] <- SRC1[255:128]\r\n ESAC.\r\nFI;\r\nIF VL = 512\r\n CASE (imm8[1:0]) OF\r\n 00: TMP_DEST[127:0] <- SRC1[127:0]\r\n 01: TMP_DEST[127:0] <- SRC1[255:128]\r\n 10: TMP_DEST[127:0] <- SRC1[383:256]\r\n 11: TMP_DEST[127:0] <- SRC1[511:384]\r\n ESAC.\r\nFI;\r\n\r\nFOR j <- 0 TO 1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE *DEST[i+63:i] remains unchanged* ; merging-masking\r\n FI;\r\nENDFOR\r\n\r\nVEXTRACTF32x8 (EVEX.U1.512 encoded version) when destination is a register\r\nVL = 512\r\nCASE (imm8[0]) OF\r\n 0: TMP_DEST[255:0] <- SRC1[255:0]\r\n 1: TMP_DEST[255:0] <- SRC1[511:256]\r\nESAC.\r\n\r\nFOR j <- 0 TO 7\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_DEST[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVEXTRACTF32x8 (EVEX.U1.512 encoded version) when destination is memory\r\nCASE (imm8[0]) OF\r\n 0: TMP_DEST[255:0] <- SRC1[255:0]\r\n 1: TMP_DEST[255:0] <- SRC1[511:256]\r\nESAC.\r\n\r\nFOR j <- 0 TO 7\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_DEST[i+31:i]\r\n ELSE *DEST[i+31:i] remains unchanged* ; merging-masking\r\n FI;\r\nENDFOR\r\n\r\nVEXTRACTF64x4 (EVEX.512 encoded version) when destination is a register\r\nVL = 512\r\nCASE (imm8[0]) OF\r\n 0: TMP_DEST[255:0] <- SRC1[255:0]\r\n 1: TMP_DEST[255:0] <- SRC1[511:256]\r\nESAC.\r\n\r\nFOR j <- 0 TO 3\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVEXTRACTF64x4 (EVEX.512 encoded version) when destination is memory\r\nCASE (imm8[0]) OF\r\n 0: TMP_DEST[255:0] <- SRC1[255:0]\r\n 1: TMP_DEST[255:0] <- SRC1[511:256]\r\nESAC.\r\n\r\nFOR j <- 0 TO 3\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE ; merging-masking\r\n *DEST[i+63:i] remains unchanged*\r\n FI;\r\nENDFOR\r\n\r\n\r\n\r\n\r\n\r\nVEXTRACTF128 (memory destination form)\r\nCASE (imm8[0]) OF\r\n 0: DEST[127:0] <-SRC1[127:0]\r\n 1: DEST[127:0] <-SRC1[255:128]\r\nESAC.\r\n\r\nVEXTRACTF128 (register destination form)\r\nCASE (imm8[0]) OF\r\n 0: DEST[127:0] <-SRC1[127:0]\r\n 1: DEST[127:0] <-SRC1[255:128]\r\nESAC.\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVEXTRACTF32x4 __m128 _mm512_extractf32x4_ps(__m512 a, const int nidx);\r\nVEXTRACTF32x4 __m128 _mm512_mask_extractf32x4_ps(__m128 s, __mmask8 k, __m512 a, const int nidx);\r\nVEXTRACTF32x4 __m128 _mm512_maskz_extractf32x4_ps( __mmask8 k, __m512 a, const int nidx);\r\nVEXTRACTF32x4 __m128 _mm256_extractf32x4_ps(__m256 a, const int nidx);\r\nVEXTRACTF32x4 __m128 _mm256_mask_extractf32x4_ps(__m128 s, __mmask8 k, __m256 a, const int nidx);\r\nVEXTRACTF32x4 __m128 _mm256_maskz_extractf32x4_ps( __mmask8 k, __m256 a, const int nidx);\r\nVEXTRACTF32x8 __m256 _mm512_extractf32x8_ps(__m512 a, const int nidx);\r\nVEXTRACTF32x8 __m256 _mm512_mask_extractf32x8_ps(__m256 s, __mmask8 k, __m512 a, const int nidx);\r\nVEXTRACTF32x8 __m256 _mm512_maskz_extractf32x8_ps( __mmask8 k, __m512 a, const int nidx);\r\nVEXTRACTF64x2 __m128d _mm512_extractf64x2_pd(__m512d a, const int nidx);\r\nVEXTRACTF64x2 __m128d _mm512_mask_extractf64x2_pd(__m128d s, __mmask8 k, __m512d a, const int nidx);\r\nVEXTRACTF64x2 __m128d _mm512_maskz_extractf64x2_pd( __mmask8 k, __m512d a, const int nidx);\r\nVEXTRACTF64x2 __m128d _mm256_extractf64x2_pd(__m256d a, const int nidx);\r\nVEXTRACTF64x2 __m128d _mm256_mask_extractf64x2_pd(__m128d s, __mmask8 k, __m256d a, const int nidx);\r\nVEXTRACTF64x2 __m128d _mm256_maskz_extractf64x2_pd( __mmask8 k, __m256d a, const int nidx);\r\nVEXTRACTF64x4 __m256d _mm512_extractf64x4_pd( __m512d a, const int nidx);\r\nVEXTRACTF64x4 __m256d _mm512_mask_extractf64x4_pd(__m256d s, __mmask8 k, __m512d a, const int nidx);\r\nVEXTRACTF64x4 __m256d _mm512_maskz_extractf64x4_pd( __mmask8 k, __m512d a, const int nidx);\r\nVEXTRACTF128 __m128 _mm256_extractf128_ps (__m256 a, int offset);\r\nVEXTRACTF128 __m128d _mm256_extractf128_pd (__m256d a, int offset);\r\nVEXTRACTF128 __m128i_mm256_extractf128_si256(__m256i a, int offset);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 6;\r\nEVEX-encoded instructions, see Exceptions Type E6NF.\r\n#UD IF VEX.L = 0.\r\n#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VEXTRACTF128"
},
{
"description": "-R:VEXTRACTF128",
"mnem": "VEXTRACTF32x4"
},
{
"description": "-R:VEXTRACTF128",
"mnem": "VEXTRACTF32x8"
},
{
"description": "-R:VEXTRACTF128",
"mnem": "VEXTRACTF64x2"
},
{
"description": "-R:VEXTRACTF128",
"mnem": "VEXTRACTF64x4"
},
{
"description": "VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4-Extract\r\npacked Integer Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.256.66.0F3A.W0 39 /r ib RMI V/V AVX2 Extract 128 bits of integer data from ymm2 and\r\n VEXTRACTI128 xmm1/m128, ymm2, store results in xmm1/m128.\r\n imm8\r\n EVEX.256.66.0F3A.W0 39 /r ib T4 V/V AVX512VL Extract 128 bits of double-word integer values\r\n VEXTRACTI32X4 xmm1/m128 {k1}{z}, AVX512F from ymm2 and store results in xmm1/m128\r\n ymm2, imm8 subject to writemask k1.\r\n EVEX.512.66.0F3A.W0 39 /r ib T4 V/V AVX512F Extract 128 bits of double-word integer values\r\n VEXTRACTI32x4 xmm1/m128 {k1}{z}, from zmm2 and store results in xmm1/m128\r\n zmm2, imm8 subject to writemask k1.\r\n EVEX.256.66.0F3A.W1 39 /r ib T2 V/V AVX512VL Extract 128 bits of quad-word integer values from\r\n VEXTRACTI64X2 xmm1/m128 {k1}{z}, AVX512DQ ymm2 and store results in xmm1/m128 subject to\r\n ymm2, imm8 writemask k1.\r\n EVEX.512.66.0F3A.W1 39 /r ib T2 V/V AVX512DQ Extract 128 bits of quad-word integer values from\r\n VEXTRACTI64X2 xmm1/m128 {k1}{z}, zmm2 and store results in xmm1/m128 subject to\r\n zmm2, imm8 writemask k1.\r\n EVEX.512.66.0F3A.W0 3B /r ib T8 V/V AVX512DQ Extract 256 bits of double-word integer values\r\n VEXTRACTI32X8 ymm1/m256 {k1}{z}, from zmm2 and store results in ymm1/m256\r\n zmm2, imm8 subject to writemask k1.\r\n EVEX.512.66.0F3A.W1 3B /r ib T4 V/V AVX512F Extract 256 bits of quad-word integer values from\r\n VEXTRACTI64x4 ymm1/m256 {k1}{z}, zmm2 and store results in ymm1/m256 subject to\r\n zmm2, imm8 writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:r/m (w) ModRM:reg (r) Imm8 NA\r\n T2, T4, T8 ModRM:r/m (w) ModRM:reg (r) Imm8 NA\r\n\r\nDescription\r\nVEXTRACTI128/VEXTRACTI32x4 and VEXTRACTI64x2 extract 128-bits of doubleword integer values from the\r\nsource operand (the second operand) and store to the low 128-bit of the destination operand (the first operand).\r\nThe 128-bit data extraction occurs at an 128-bit granular offset specified by imm8[0] (256-bit) or imm8[1:0] as\r\nthe multiply factor. The destination may be either a vector register or an 128-bit memory location.\r\nVEXTRACTI32x4: The low 128-bit of the destination operand is updated at 32-bit granularity according to the\r\nwritemask.\r\nVEXTRACTI64x2: The low 128-bit of the destination operand is updated at 64-bit granularity according to the\r\nwritemask.\r\nVEXTRACTI32x8 and VEXTRACTI64x4 extract 256-bits of quadword integer values from the source operand (the\r\nsecond operand) and store to the low 256-bit of the destination operand (the first operand). The 256-bit data\r\nextraction occurs at an 256-bit granular offset specified by imm8[0] (256-bit) or imm8[0] as the multiply factor\r\nThe destination may be either a vector register or a 256-bit memory location.\r\nVEXTRACTI32x8: The low 256-bit of the destination operand is updated at 32-bit granularity according to the\r\nwritemask.\r\n\r\n\r\n\r\n\r\n\r\nVEXTRACTI64x4: The low 256-bit of the destination operand is updated at 64-bit granularity according to the\r\nwritemask.\r\nVEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\nThe high 7 bits (6 bits in EVEX.512) of the immediate are ignored.\r\nIf VEXTRACTI128 is encoded with VEX.L= 0, an attempt to execute the instruction encoded with VEX.L= 0 will\r\ncause an #UD exception.\r\n\r\nOperation\r\nVEXTRACTI32x4 (EVEX encoded versions) when destination is a register\r\nVL = 256, 512\r\nIF VL = 256\r\n CASE (imm8[0]) OF\r\n 0: TMP_DEST[127:0] <- SRC1[127:0]\r\n 1: TMP_DEST[127:0] <- SRC1[255:128]\r\n ESAC.\r\nFI;\r\nIF VL = 512\r\n CASE (imm8[1:0]) OF\r\n 00: TMP_DEST[127:0] <- SRC1[127:0]\r\n 01: TMP_DEST[127:0] <- SRC1[255:128]\r\n 10: TMP_DEST[127:0] <- SRC1[383:256]\r\n 11: TMP_DEST[127:0] <- SRC1[511:384]\r\n ESAC.\r\nFI;\r\nFOR j <- 0 TO 3\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_DEST[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVEXTRACTI32x4 (EVEX encoded versions) when destination is memory\r\nVL = 256, 512\r\nIF VL = 256\r\n CASE (imm8[0]) OF\r\n 0: TMP_DEST[127:0] <- SRC1[127:0]\r\n 1: TMP_DEST[127:0] <- SRC1[255:128]\r\n ESAC.\r\nFI;\r\nIF VL = 512\r\n CASE (imm8[1:0]) OF\r\n 00: TMP_DEST[127:0] <- SRC1[127:0]\r\n 01: TMP_DEST[127:0] <- SRC1[255:128]\r\n 10: TMP_DEST[127:0] <- SRC1[383:256]\r\n 11: TMP_DEST[127:0] <- SRC1[511:384]\r\n ESAC.\r\n\r\n\r\n\r\nFI;\r\n\r\nFOR j <- 0 TO 3\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_DEST[i+31:i]\r\n ELSE *DEST[i+31:i] remains unchanged* ; merging-masking\r\n FI;\r\nENDFOR\r\n\r\nVEXTRACTI64x2 (EVEX encoded versions) when destination is a register\r\nVL = 256, 512\r\nIF VL = 256\r\n CASE (imm8[0]) OF\r\n 0: TMP_DEST[127:0] <- SRC1[127:0]\r\n 1: TMP_DEST[127:0] <- SRC1[255:128]\r\n ESAC.\r\nFI;\r\nIF VL = 512\r\n CASE (imm8[1:0]) OF\r\n 00: TMP_DEST[127:0] <- SRC1[127:0]\r\n 01: TMP_DEST[127:0] <- SRC1[255:128]\r\n 10: TMP_DEST[127:0] <- SRC1[383:256]\r\n 11: TMP_DEST[127:0] <- SRC1[511:384]\r\n ESAC.\r\nFI;\r\n\r\nFOR j <- 0 TO 1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVEXTRACTI64x2 (EVEX encoded versions) when destination is memory\r\nVL = 256, 512\r\nIF VL = 256\r\n CASE (imm8[0]) OF\r\n 0: TMP_DEST[127:0] <- SRC1[127:0]\r\n 1: TMP_DEST[127:0] <- SRC1[255:128]\r\n ESAC.\r\nFI;\r\nIF VL = 512\r\n CASE (imm8[1:0]) OF\r\n 00: TMP_DEST[127:0] <- SRC1[127:0]\r\n 01: TMP_DEST[127:0] <- SRC1[255:128]\r\n 10: TMP_DEST[127:0] <- SRC1[383:256]\r\n 11: TMP_DEST[127:0] <- SRC1[511:384]\r\n ESAC.\r\nFI;\r\n\r\nFOR j <- 0 TO 1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE *DEST[i+63:i] remains unchanged* ; merging-masking\r\n FI;\r\nENDFOR\r\n\r\nVEXTRACTI32x8 (EVEX.U1.512 encoded version) when destination is a register\r\nVL = 512\r\nCASE (imm8[0]) OF\r\n 0: TMP_DEST[255:0] <- SRC1[255:0]\r\n 1: TMP_DEST[255:0] <- SRC1[511:256]\r\nESAC.\r\n\r\nFOR j <- 0 TO 7\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_DEST[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVEXTRACTI32x8 (EVEX.U1.512 encoded version) when destination is memory\r\nCASE (imm8[0]) OF\r\n 0: TMP_DEST[255:0] <- SRC1[255:0]\r\n 1: TMP_DEST[255:0] <- SRC1[511:256]\r\nESAC.\r\n\r\nFOR j <- 0 TO 7\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_DEST[i+31:i]\r\n ELSE *DEST[i+31:i] remains unchanged* ; merging-masking\r\n FI;\r\nENDFOR\r\n\r\nVEXTRACTI64x4 (EVEX.512 encoded version) when destination is a register\r\nVL = 512\r\nCASE (imm8[0]) OF\r\n 0: TMP_DEST[255:0] <- SRC1[255:0]\r\n 1: TMP_DEST[255:0] <- SRC1[511:256]\r\nESAC.\r\n\r\nFOR j <- 0 TO 3\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVEXTRACTI64x4 (EVEX.512 encoded version) when destination is memory\r\nCASE (imm8[0]) OF\r\n 0: TMP_DEST[255:0] <- SRC1[255:0]\r\n 1: TMP_DEST[255:0] <- SRC1[511:256]\r\nESAC.\r\nFOR j <- 0 TO 3\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE *DEST[i+63:i] remains unchanged* ; merging-masking\r\n FI;\r\nENDFOR\r\n\r\n\r\n\r\n\r\n\r\nVEXTRACTI128 (memory destination form)\r\nCASE (imm8[0]) OF\r\n 0: DEST[127:0] <-SRC1[127:0]\r\n 1: DEST[127:0] <-SRC1[255:128]\r\nESAC.\r\n\r\nVEXTRACTI128 (register destination form)\r\nCASE (imm8[0]) OF\r\n 0: DEST[127:0] <-SRC1[127:0]\r\n 1: DEST[127:0] <-SRC1[255:128]\r\nESAC.\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVEXTRACTI32x4 __m128i _mm512_extracti32x4_epi32(__m512i a, const int nidx);\r\nVEXTRACTI32x4 __m128i _mm512_mask_extracti32x4_epi32(__m128i s, __mmask8 k, __m512i a, const int nidx);\r\nVEXTRACTI32x4 __m128i _mm512_maskz_extracti32x4_epi32( __mmask8 k, __m512i a, const int nidx);\r\nVEXTRACTI32x4 __m128i _mm256_extracti32x4_epi32(__m256i a, const int nidx);\r\nVEXTRACTI32x4 __m128i _mm256_mask_extracti32x4_epi32(__m128i s, __mmask8 k, __m256i a, const int nidx);\r\nVEXTRACTI32x4 __m128i _mm256_maskz_extracti32x4_epi32( __mmask8 k, __m256i a, const int nidx);\r\nVEXTRACTI32x8 __m256i _mm512_extracti32x8_epi32(__m512i a, const int nidx);\r\nVEXTRACTI32x8 __m256i _mm512_mask_extracti32x8_epi32(__m256i s, __mmask8 k, __m512i a, const int nidx);\r\nVEXTRACTI32x8 __m256i _mm512_maskz_extracti32x8_epi32( __mmask8 k, __m512i a, const int nidx);\r\nVEXTRACTI64x2 __m128i _mm512_extracti64x2_epi64(__m512i a, const int nidx);\r\nVEXTRACTI64x2 __m128i _mm512_mask_extracti64x2_epi64(__m128i s, __mmask8 k, __m512i a, const int nidx);\r\nVEXTRACTI64x2 __m128i _mm512_maskz_extracti64x2_epi64( __mmask8 k, __m512i a, const int nidx);\r\nVEXTRACTI64x2 __m128i _mm256_extracti64x2_epi64(__m256i a, const int nidx);\r\nVEXTRACTI64x2 __m128i _mm256_mask_extracti64x2_epi64(__m128i s, __mmask8 k, __m256i a, const int nidx);\r\nVEXTRACTI64x2 __m128i _mm256_maskz_extracti64x2_epi64( __mmask8 k, __m256i a, const int nidx);\r\nVEXTRACTI64x4 __m256i _mm512_extracti64x4_epi64(__m512i a, const int nidx);\r\nVEXTRACTI64x4 __m256i _mm512_mask_extracti64x4_epi64(__m256i s, __mmask8 k, __m512i a, const int nidx);\r\nVEXTRACTI64x4 __m256i _mm512_maskz_extracti64x4_epi64( __mmask8 k, __m512i a, const int nidx);\r\nVEXTRACTI128 __m128i _mm256_extracti128_si256(__m256i a, int offset);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 6;\r\nEVEX-encoded instructions, see Exceptions Type E6NF.\r\n#UD IF VEX.L = 0.\r\n#UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VEXTRACTI128"
},
{
"description": "-R:VEXTRACTI128",
"mnem": "VEXTRACTI32x4"
},
{
"description": "-R:VEXTRACTI128",
"mnem": "VEXTRACTI32x8"
},
{
"description": "-R:VEXTRACTI128",
"mnem": "VEXTRACTI64x2"
},
{
"description": "-R:VEXTRACTI128",
"mnem": "VEXTRACTI64x4"
},
{
"description": "VFIXUPIMMPD-Fix Up Special Packed Float64 Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.128.66.0F3A.W1 54 /r ib FV V/V AVX512VL Fix up special numbers in float64 vector xmm1, float64\r\n VFIXUPIMMPD xmm1 {k1}{z}, xmm2, AVX512F vector xmm2 and int64 vector xmm3/m128/m64bcst\r\n xmm3/m128/m64bcst, imm8 and store the result in xmm1, under writemask.\r\n EVEX.NDS.256.66.0F3A.W1 54 /r ib FV V/V AVX512VL Fix up special numbers in float64 vector ymm1, float64\r\n VFIXUPIMMPD ymm1 {k1}{z}, ymm2, AVX512F vector ymm2 and int64 vector ymm3/m256/m64bcst\r\n ymm3/m256/m64bcst, imm8 and store the result in ymm1, under writemask.\r\n EVEX.NDS.512.66.0F3A.W1 54 /r ib FV V/V AVX512F Fix up elements of float64 vector in zmm2 using int64\r\n VFIXUPIMMPD zmm1 {k1}{z}, zmm2, vector table in zmm3/m512/m64bcst, combine with\r\n zmm3/m512/m64bcst{sae}, imm8 preserved elements from zmm1, and store the result in\r\n zmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (r, w) EVEX.vvvv ModRM:r/m (r) Imm8\r\n\r\nDescription\r\nPerform fix-up of quad-word elements encoded in double-precision floating-point format in the first source operand\r\n(the second operand) using a 32-bit, two-level look-up table specified in the corresponding quadword element of\r\nthe second source operand (the third operand) with exception reporting specifier imm8. The elements that are\r\nfixed-up are selected by mask bits of 1 specified in the opmask k1. Mask bits of 0 in the opmask k1 or table\r\nresponse action of 0000b preserves the corresponding element of the first operand. The fixed-up elements from\r\nthe first source operand and the preserved element in the first operand are combined as the final results in the\r\ndestination operand (the first operand).\r\nThe destination and the first source operands are ZMM/YMM/XMM registers. The second source operand can be a\r\nZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-\r\nbit memory location.\r\nThe two-level look-up table perform a fix-up of each DP FP input data in the first source operand by decoding the\r\ninput data encoding into 8 token types. A response table is defined for each token type that converts the input\r\nencoding in the first source operand with one of 16 response actions.\r\nThis instruction is specifically intended for use in fixing up the results of arithmetic calculations involving one source\r\nso that they match the spec, although it is generally useful for fixing up the results of multiple-instruction\r\nsequences to reflect special-number inputs. For example, consider rcp(0). Input 0 to rcp, and you should get INF\r\naccording to the DX10 spec. However, evaluating rcp via Newton-Raphson, where x=approx(1/0), yields an incor-\r\nrect result. To deal with this, VFIXUPIMMPD can be used after the N-R reciprocal sequence to set the result to the\r\ncorrect value (i.e. INF when the input is 0).\r\nIf MXCSR.DAZ is not set, denormal input elements in the first source operand are considered as normal inputs and\r\ndo not trigger any fixup nor fault reporting.\r\nImm8 is used to set the required flags reporting. It supports #ZE and #IE fault reporting (see details below).\r\nMXCSR mask bits are ignored and are treated as if all mask bits are set to masked response). If any of the imm8\r\nbits is set and the condition met for fault reporting, MXCSR.IE or MXCSR.ZE might be updated.\r\nThis instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1\r\nare computed and stored into zmm1. Elements in the destination with the corresponding bit clear in k1 retain their\r\nprevious values or are set to 0.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nenum TOKEN_TYPE\r\n{\r\n QNAN_TOKEN <- 0,\r\n SNAN_TOKEN <- 1,\r\n ZERO_VALUE_TOKEN <- 2,\r\n POS_ONE_VALUE_TOKEN <- 3,\r\n NEG_INF_TOKEN <- 4,\r\n POS_INF_TOKEN <- 5,\r\n NEG_VALUE_TOKEN <- 6,\r\n POS_VALUE_TOKEN <- 7\r\n}\r\n\r\nFIXUPIMM_DP (dest[63:0], src1[63:0],tbl3[63:0], imm8 [7:0]){\r\n tsrc[63:0] <- ((src1[62:52] = 0) AND (MXCSR.DAZ =1)) ? 0.0 : src1[63:0]\r\n CASE(tsrc[63:0] of TOKEN_TYPE) {\r\n QNAN_TOKEN: j <- 0;\r\n SNAN_TOKEN: j <- 1;\r\n ZERO_VALUE_TOKEN: j <- 2;\r\n POS_ONE_VALUE_TOKEN: j <- 3;\r\n NEG_INF_TOKEN: j <- 4;\r\n POS_INF_TOKEN: j <- 5;\r\n NEG_VALUE_TOKEN: j <- 6;\r\n POS_VALUE_TOKEN: j <- 7;\r\n } ; end source special CASE(tsrc...)\r\n\r\n ; The required response from src3 table is extracted\r\n token_response[3:0] = tbl3[3+4*j:4*j];\r\n\r\n CASE(token_response[3:0]) {\r\n 0000: dest[63:0] <- dest[63:0] ; ; preserve content of DEST\r\n 0001: dest[63:0] <- tsrc[63:0]; ; pass through src1 normal input value, denormal as zero\r\n 0010: dest[63:0] <- QNaN(tsrc[63:0]);\r\n 0011: dest[63:0] <- QNAN_Indefinite;\r\n 0100: dest[63:0] <- -INF;\r\n 0101: dest[63:0] <- +INF;\r\n 0110: dest[63:0] <- tsrc.sign? -INF : +INF;\r\n 0111: dest[63:0] <- -0;\r\n 1000: dest[63:0] <- +0;\r\n 1001: dest[63:0] <- -1;\r\n 1010: dest[63:0] <- +1;\r\n 1011: dest[63:0] <- 1/2;\r\n 1100: dest[63:0] <- 90.0;\r\n 1101: dest[63:0] <- PI/2;\r\n 1110: dest[63:0] <- MAX_FLOAT;\r\n 1111: dest[63:0] <- -MAX_FLOAT;\r\n } ; end of token_response CASE\r\n\r\n\r\n\r\n\r\n\r\n ; The required fault reporting from imm8 is extracted\r\n ; TOKENs are mutually exclusive and TOKENs priority defines the order.\r\n ; Multiple faults related to a single token can occur simultaneously.\r\n IF (tsrc[63:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[0] then set #ZE;\r\n IF (tsrc[63:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[1] then set #IE;\r\n IF (tsrc[63:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[2] then set #ZE;\r\n IF (tsrc[63:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[3] then set #IE;\r\n IF (tsrc[63:0] of TOKEN_TYPE: SNAN_TOKEN) AND imm8[4] then set #IE;\r\n IF (tsrc[63:0] of TOKEN_TYPE: NEG_INF_TOKEN) AND imm8[5] then set #IE;\r\n IF (tsrc[63:0] of TOKEN_TYPE: NEG_VALUE_TOKEN) AND imm8[6] then set #IE;\r\n IF (tsrc[63:0] of TOKEN_TYPE: POS_INF_TOKEN) AND imm8[7] then set #IE;\r\n ; end fault reporting\r\n return dest[63:0];\r\n} ; end of FIXUPIMM_DP()\r\n\r\nVFIXUPIMMPD\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN\r\n DEST[i+63:i] <- FIXUPIMM_DP(DEST[i+63:i], SRC1[i+63:i], SRC2[63:0], imm8 [7:0])\r\n ELSE\r\n DEST[i+63:i] <- FIXUPIMM_DP(DEST[i+63:i], SRC1[i+63:i], SRC2[i+63:i], imm8 [7:0])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE DEST[i+63:i] <- 0 ; zeroing-masking\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nImmediate Control Description:\r\n\r\n\r\n\r\n\r\n 7 6 5 4 3 2 1 0\r\n | | | | | | | |\r\n + INF -> #IE----+ | | | | | | |\r\n - VE -> #IE------+ | | | | | |\r\n - INF -> #IE--------+ | | | | |\r\n SNaN -> #IE----------+ | | | |\r\n ONE -> #IE------------+ | | |\r\n ONE -> #ZE--------------+ | |\r\n ZERO -> #IE----------------+ |\r\n ZERO -> #ZE------------------+\r\n\r\n Figure 5-9. VFIXUPIMMPD Immediate Control Description\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVFIXUPIMMPD __m512d _mm512_fixupimm_pd( __m512d a, __m512i tbl, int imm);\r\nVFIXUPIMMPD __m512d _mm512_mask_fixupimm_pd(__m512d s, __mmask8 k, __m512d a, __m512i tbl, int imm);\r\nVFIXUPIMMPD __m512d _mm512_maskz_fixupimm_pd( __mmask8 k, __m512d a, __m512i tbl, int imm);\r\nVFIXUPIMMPD __m512d _mm512_fixupimm_round_pd( __m512d a, __m512i tbl, int imm, int sae);\r\nVFIXUPIMMPD __m512d _mm512_mask_fixupimm_round_pd(__m512d s, __mmask8 k, __m512d a, __m512i tbl, int imm, int sae);\r\nVFIXUPIMMPD __m512d _mm512_maskz_fixupimm_round_pd( __mmask8 k, __m512d a, __m512i tbl, int imm, int sae);\r\nVFIXUPIMMPD __m256d _mm256_fixupimm_pd( __m256d a, __m256i tbl, int imm);\r\nVFIXUPIMMPD __m256d _mm256_mask_fixupimm_pd(__m256d s, __mmask8 k, __m256d a, __m256i tbl, int imm);\r\nVFIXUPIMMPD __m256d _mm256_maskz_fixupimm_pd( __mmask8 k, __m256d a, __m256i tbl, int imm);\r\nVFIXUPIMMPD __m128d _mm_fixupimm_pd( __m128d a, __m128i tbl, int imm);\r\nVFIXUPIMMPD __m128d _mm_mask_fixupimm_pd(__m128d s, __mmask8 k, __m128d a, __m128i tbl, int imm);\r\nVFIXUPIMMPD __m128d _mm_maskz_fixupimm_pd( __mmask8 k, __m128d a, __m128i tbl, int imm);\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nZero, Invalid\r\n\r\nOther Exceptions\r\nSee Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VFIXUPIMMPD"
},
{
"description": "VFIXUPIMMPS-Fix Up Special Packed Float32 Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.128.66.0F3A.W0 54 /r FV V/V AVX512VL Fix up special numbers in float32 vector xmm1, float32\r\n VFIXUPIMMPS xmm1 {k1}{z}, xmm2, AVX512F vector xmm2 and int32 vector xmm3/m128/m32bcst\r\n xmm3/m128/m32bcst, imm8 and store the result in xmm1, under writemask.\r\n EVEX.NDS.256.66.0F3A.W0 54 /r FV V/V AVX512VL Fix up special numbers in float32 vector ymm1, float32\r\n VFIXUPIMMPS ymm1 {k1}{z}, ymm2, AVX512F vector ymm2 and int32 vector ymm3/m256/m32bcst\r\n ymm3/m256/m32bcst, imm8 and store the result in ymm1, under writemask.\r\n EVEX.NDS.512.66.0F3A.W0 54 /r ib FV V/V AVX512F Fix up elements of float32 vector in zmm2 using int32\r\n VFIXUPIMMPS zmm1 {k1}{z}, zmm2, vector table in zmm3/m512/m32bcst, combine with\r\n zmm3/m512/m32bcst{sae}, imm8 preserved elements from zmm1, and store the result in\r\n zmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (r, w) EVEX.vvvv ModRM:r/m (r) Imm8\r\n\r\nDescription\r\nPerform fix-up of doubleword elements encoded in single-precision floating-point format in the first source operand\r\n(the second operand) using a 32-bit, two-level look-up table specified in the corresponding doubleword element of\r\nthe second source operand (the third operand) with exception reporting specifier imm8. The elements that are\r\nfixed-up are selected by mask bits of 1 specified in the opmask k1. Mask bits of 0 in the opmask k1 or table\r\nresponse action of 0000b preserves the corresponding element of the first operand. The fixed-up elements from\r\nthe first source operand and the preserved element in the first operand are combined as the final results in the\r\ndestination operand (the first operand).\r\nThe destination and the first source operands are ZMM/YMM/XMM registers. The second source operand can be a\r\nZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-\r\nbit memory location.\r\nThe two-level look-up table perform a fix-up of each SP FP input data in the first source operand by decoding the\r\ninput data encoding into 8 token types. A response table is defined for each token type that converts the input\r\nencoding in the first source operand with one of 16 response actions.\r\nThis instruction is specifically intended for use in fixing up the results of arithmetic calculations involving one source\r\nso that they match the spec, although it is generally useful for fixing up the results of multiple-instruction\r\nsequences to reflect special-number inputs. For example, consider rcp(0). Input 0 to rcp, and you should get INF\r\naccording to the DX10 spec. However, evaluating rcp via Newton-Raphson, where x=approx(1/0), yields an incor-\r\nrect result. To deal with this, VFIXUPIMMPS can be used after the N-R reciprocal sequence to set the result to the\r\ncorrect value (i.e. INF when the input is 0).\r\nIf MXCSR.DAZ is not set, denormal input elements in the first source operand are considered as normal inputs and\r\ndo not trigger any fixup nor fault reporting.\r\nImm8 is used to set the required flags reporting. It supports #ZE and #IE fault reporting (see details below).\r\nMXCSR.DAZ is used and refer to zmm2 only (i.e. zmm1 is not considered as zero in case MXCSR.DAZ is set).\r\nMXCSR mask bits are ignored and are treated as if all mask bits are set to masked response). If any of the imm8\r\nbits is set and the condition met for fault reporting, MXCSR.IE or MXCSR.ZE might be updated.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nenum TOKEN_TYPE\r\n{\r\n QNAN_TOKEN <- 0,\r\n SNAN_TOKEN <- 1,\r\n ZERO_VALUE_TOKEN <- 2,\r\n POS_ONE_VALUE_TOKEN <- 3,\r\n NEG_INF_TOKEN <- 4,\r\n POS_INF_TOKEN <- 5,\r\n NEG_VALUE_TOKEN <- 6,\r\n POS_VALUE_TOKEN <- 7\r\n}\r\n\r\nFIXUPIMM_SP ( dest[31:0], src1[31:0],tbl3[31:0], imm8 [7:0]){\r\n tsrc[31:0] <- ((src1[30:23] = 0) AND (MXCSR.DAZ =1)) ? 0.0 : src1[31:0]\r\n CASE(tsrc[63:0] of TOKEN_TYPE) {\r\n QNAN_TOKEN: j <- 0;\r\n SNAN_TOKEN: j <- 1;\r\n ZERO_VALUE_TOKEN: j <- 2;\r\n POS_ONE_VALUE_TOKEN: j <- 3;\r\n NEG_INF_TOKEN: j <- 4;\r\n POS_INF_TOKEN: j <- 5;\r\n NEG_VALUE_TOKEN: j <- 6;\r\n POS_VALUE_TOKEN: j <- 7;\r\n } ; end source special CASE(tsrc...)\r\n\r\n ; The required response from src3 table is extracted\r\n token_response[3:0] = tbl3[3+4*j:4*j];\r\n\r\n CASE(token_response[3:0]) {\r\n 0000: dest[31:0] <- dest[31:0]; ; preserve content of DEST\r\n 0001: dest[31:0] <- tsrc[31:0]; ; pass through src1 normal input value, denormal as zero\r\n 0010: dest[31:0] <- QNaN(tsrc[31:0]);\r\n 0011: dest[31:0] <- QNAN_Indefinite;\r\n 0100: dest[31:0] <- -INF;\r\n 0101: dest[31:0] <- +INF;\r\n 0110: dest[31:0] <- tsrc.sign? -INF : +INF;\r\n 0111: dest[31:0] <- -0;\r\n 1000: dest[31:0] <- +0;\r\n 1001: dest[31:0] <- -1;\r\n 1010: dest[31:0] <- +1;\r\n 1011: dest[31:0] <- 1/2;\r\n 1100: dest[31:0] <- 90.0;\r\n 1101: dest[31:0] <- PI/2;\r\n 1110: dest[31:0] <- MAX_FLOAT;\r\n 1111: dest[31:0] <- -MAX_FLOAT;\r\n } ; end of token_response CASE\r\n\r\n\r\n\r\n\r\n\r\n ; The required fault reporting from imm8 is extracted\r\n ; TOKENs are mutually exclusive and TOKENs priority defines the order.\r\n ; Multiple faults related to a single token can occur simultaneously.\r\n IF (tsrc[31:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[0] then set #ZE;\r\n IF (tsrc[31:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[1] then set #IE;\r\n IF (tsrc[31:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[2] then set #ZE;\r\n IF (tsrc[31:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[3] then set #IE;\r\n IF (tsrc[31:0] of TOKEN_TYPE: SNAN_TOKEN) AND imm8[4] then set #IE;\r\n IF (tsrc[31:0] of TOKEN_TYPE: NEG_INF_TOKEN) AND imm8[5] then set #IE;\r\n IF (tsrc[31:0] of TOKEN_TYPE: NEG_VALUE_TOKEN) AND imm8[6] then set #IE;\r\n IF (tsrc[31:0] of TOKEN_TYPE: POS_INF_TOKEN) AND imm8[7] then set #IE;\r\n ; end fault reporting\r\n return dest[31:0];\r\n} ; end of FIXUPIMM_SP()\r\n\r\nVFIXUPIMMPS (EVEX)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN\r\n DEST[i+31:i] <- FIXUPIMM_SP(DEST[i+31:i], SRC1[i+31:i], SRC2[31:0], imm8 [7:0])\r\n ELSE\r\n DEST[i+31:i] <- FIXUPIMM_SP(DEST[i+31:i], SRC1[i+31:i], SRC2[i+31:i], imm8 [7:0])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE DEST[i+31:i] <- 0 ; zeroing-masking\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nImmediate Control Description:\r\n\r\n\r\n\r\n\r\n 7 6 5 4 3 2 1 0\r\n\r\n + INF -> #IE\r\n - VE -> #IE\r\n - INF -> #IE\r\n SNaN -> #IE\r\n ONE -> #IE\r\n ONE -> #ZE\r\n ZERO -> #IE\r\n ZERO -> #ZE\r\n\r\n Figure 5-10. VFIXUPIMMPS Immediate Control Description\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVFIXUPIMMPS __m512 _mm512_fixupimm_ps( __m512 a, __m512i tbl, int imm);\r\nVFIXUPIMMPS __m512 _mm512_mask_fixupimm_ps(__m512 s, __mmask16 k, __m512 a, __m512i tbl, int imm);\r\nVFIXUPIMMPS __m512 _mm512_maskz_fixupimm_ps( __mmask16 k, __m512 a, __m512i tbl, int imm);\r\nVFIXUPIMMPS __m512 _mm512_fixupimm_round_ps( __m512 a, __m512i tbl, int imm, int sae);\r\nVFIXUPIMMPS __m512 _mm512_mask_fixupimm_round_ps(__m512 s, __mmask16 k, __m512 a, __m512i tbl, int imm, int sae);\r\nVFIXUPIMMPS __m512 _mm512_maskz_fixupimm_round_ps( __mmask16 k, __m512 a, __m512i tbl, int imm, int sae);\r\nVFIXUPIMMPS __m256 _mm256_fixupimm_ps( __m256 a, __m256i tbl, int imm);\r\nVFIXUPIMMPS __m256 _mm256_mask_fixupimm_ps(__m256 s, __mmask8 k, __m256 a, __m256i tbl, int imm);\r\nVFIXUPIMMPS __m256 _mm256_maskz_fixupimm_ps( __mmask8 k, __m256 a, __m256i tbl, int imm);\r\nVFIXUPIMMPS __m128 _mm_fixupimm_ps( __m128 a, __m128i tbl, int imm);\r\nVFIXUPIMMPS __m128 _mm_mask_fixupimm_ps(__m128 s, __mmask8 k, __m128 a, __m128i tbl, int imm);\r\nVFIXUPIMMPS __m128 _mm_maskz_fixupimm_ps( __mmask8 k, __m128 a, __m128i tbl, int imm);\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nZero, Invalid\r\n\r\nOther Exceptions\r\nSee Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VFIXUPIMMPS"
},
{
"description": "VFIXUPIMMSD-Fix Up Special Scalar Float64 Value\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.LIG.66.0F3A.W1 55 /r ib T1S V/V AVX512F Fix up a float64 number in the low quadword element of\r\n VFIXUPIMMSD xmm1 {k1}{z}, xmm2 using scalar int32 table in xmm3/m64 and store the\r\n xmm2, xmm3/m64{sae}, imm8 result in xmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (r, w) EVEX.vvvv ModRM:r/m (r) Imm8\r\n\r\nDescription\r\nPerform a fix-up of the low quadword element encoded in double-precision floating-point format in the first source\r\noperand (the second operand) using a 32-bit, two-level look-up table specified in the low quadword element of the\r\nsecond source operand (the third operand) with exception reporting specifier imm8. The element that is fixed-up is\r\nselected by mask bit of 1 specified in the opmask k1. Mask bit of 0 in the opmask k1 or table response action of\r\n0000b preserves the corresponding element of the first operand. The fixed-up element from the first source\r\noperand or the preserved element in the first operand becomes the low quadword element of the destination\r\noperand (the first operand). Bits 127:64 of the destination operand is copied from the corresponding bits of the first\r\nsource operand. The destination and first source operands are XMM registers. The second source operand can be a\r\nXMM register or a 64- bit memory location.\r\nThe two-level look-up table perform a fix-up of each DP FP input data in the first source operand by decoding the\r\ninput data encoding into 8 token types. A response table is defined for each token type that converts the input\r\nencoding in the first source operand with one of 16 response actions.\r\nThis instruction is specifically intended for use in fixing up the results of arithmetic calculations involving one source\r\nso that they match the spec, although it is generally useful for fixing up the results of multiple-instruction\r\nsequences to reflect special-number inputs. For example, consider rcp(0). Input 0 to rcp, and you should get INF\r\naccording to the DX10 spec. However, evaluating rcp via Newton-Raphson, where x=approx(1/0), yields an incor-\r\nrect result. To deal with this, VFIXUPIMMPD can be used after the N-R reciprocal sequence to set the result to the\r\ncorrect value (i.e. INF when the input is 0).\r\nIf MXCSR.DAZ is not set, denormal input elements in the first source operand are considered as normal inputs and\r\ndo not trigger any fixup nor fault reporting.\r\nImm8 is used to set the required flags reporting. It supports #ZE and #IE fault reporting (see details below).\r\nMXCSR.DAZ is used and refer to zmm2 only (i.e. zmm1 is not considered as zero in case MXCSR.DAZ is set).\r\nMXCSR mask bits are ignored and are treated as if all mask bits are set to masked response). If any of the imm8\r\nbits is set and the condition met for fault reporting, MXCSR.IE or MXCSR.ZE might be updated.\r\n\r\nOperation\r\nenum TOKEN_TYPE\r\n{\r\n QNAN_TOKEN <- 0,\r\n SNAN_TOKEN <- 1,\r\n ZERO_VALUE_TOKEN <- 2,\r\n POS_ONE_VALUE_TOKEN <- 3,\r\n NEG_INF_TOKEN <- 4,\r\n POS_INF_TOKEN <- 5,\r\n NEG_VALUE_TOKEN <- 6,\r\n POS_VALUE_TOKEN <- 7\r\n}\r\n\r\n\r\n\r\n\r\n\r\nFIXUPIMM_DP (dest[63:0], src1[63:0],tbl3[63:0], imm8 [7:0]){\r\n tsrc[63:0] <- ((src1[62:52] = 0) AND (MXCSR.DAZ =1)) ? 0.0 : src1[63:0]\r\n CASE(tsrc[63:0] of TOKEN_TYPE) {\r\n QNAN_TOKEN: j <- 0;\r\n SNAN_TOKEN: j <- 1;\r\n ZERO_VALUE_TOKEN: j <- 2;\r\n POS_ONE_VALUE_TOKEN: j <- 3;\r\n NEG_INF_TOKEN: j <- 4;\r\n POS_INF_TOKEN: j <- 5;\r\n NEG_VALUE_TOKEN: j <- 6;\r\n POS_VALUE_TOKEN: j <- 7;\r\n } ; end source special CASE(tsrc...)\r\n\r\n ; The required response from src3 table is extracted\r\n token_response[3:0] = tbl3[3+4*j:4*j];\r\n\r\n CASE(token_response[3:0]) {\r\n 0000: dest[63:0] <- dest[63:0] ; preserve content of DEST\r\n 0001: dest[63:0] <- tsrc[63:0]; ; pass through src1 normal input value, denormal as zero\r\n 0010: dest[63:0] <- QNaN(tsrc[63:0]);\r\n 0011: dest[63:0] <- QNAN_Indefinite;\r\n 0100:dest[63:0] <- -INF;\r\n 0101: dest[63:0] <- +INF;\r\n 0110: dest[63:0] <- tsrc.sign? -INF : +INF;\r\n 0111: dest[63:0] <- -0;\r\n 1000: dest[63:0] <- +0;\r\n 1001: dest[63:0] <- -1;\r\n 1010: dest[63:0] <- +1;\r\n 1011: dest[63:0] <- 1/2;\r\n 1100: dest[63:0] <- 90.0;\r\n 1101: dest[63:0] <- PI/2;\r\n 1110: dest[63:0] <- MAX_FLOAT;\r\n 1111: dest[63:0] <- -MAX_FLOAT;\r\n } ; end of token_response CASE\r\n\r\n ; The required fault reporting from imm8 is extracted\r\n ; TOKENs are mutually exclusive and TOKENs priority defines the order.\r\n ; Multiple faults related to a single token can occur simultaneously.\r\n IF (tsrc[63:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[0] then set #ZE;\r\n IF (tsrc[63:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[1] then set #IE;\r\n IF (tsrc[63:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[2] then set #ZE;\r\n IF (tsrc[63:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[3] then set #IE;\r\n IF (tsrc[63:0] of TOKEN_TYPE: SNAN_TOKEN) AND imm8[4] then set #IE;\r\n IF (tsrc[63:0] of TOKEN_TYPE: NEG_INF_TOKEN) AND imm8[5] then set #IE;\r\n IF (tsrc[63:0] of TOKEN_TYPE: NEG_VALUE_TOKEN) AND imm8[6] then set #IE;\r\n IF (tsrc[63:0] of TOKEN_TYPE: POS_INF_TOKEN) AND imm8[7] then set #IE;\r\n ; end fault reporting\r\n return dest[63:0];\r\n} ; end of FIXUPIMM_DP()\r\n\r\n\r\n\r\n\r\n\r\nVFIXUPIMMSD (EVEX encoded version)\r\nIF k1[0] OR *no writemask*\r\n THEN DEST[63:0] <- FIXUPIMM_DP(DEST[63:0], SRC1[63:0], SRC2[63:0], imm8 [7:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE DEST[63:0] <- 0 ; zeroing-masking\r\n FI\r\nFI;\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\nImmediate Control Description:\r\n\r\n\r\n\r\n\r\n 7 6 5 4 3 2 1 0\r\n\r\n + INF -> #IE\r\n - VE -> #IE\r\n - INF -> #IE\r\n SNaN -> #IE\r\n ONE -> #IE\r\n ONE -> #ZE\r\n ZERO -> #IE\r\n ZERO -> #ZE\r\n\r\n Figure 5-11. VFIXUPIMMSD Immediate Control Description\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVFIXUPIMMSD __m128d _mm_fixupimm_sd( __m128d a, __m128i tbl, int imm);\r\nVFIXUPIMMSD __m128d _mm_mask_fixupimm_sd(__m128d s, __mmask8 k, __m128d a, __m128i tbl, int imm);\r\nVFIXUPIMMSD __m128d _mm_maskz_fixupimm_sd( __mmask8 k, __m128d a, __m128i tbl, int imm);\r\nVFIXUPIMMSD __m128d _mm_fixupimm_round_sd( __m128d a, __m128i tbl, int imm, int sae);\r\nVFIXUPIMMSD __m128d _mm_mask_fixupimm_round_sd(__m128d s, __mmask8 k, __m128d a, __m128i tbl, int imm, int sae);\r\nVFIXUPIMMSD __m128d _mm_maskz_fixupimm_round_sd( __mmask8 k, __m128d a, __m128i tbl, int imm, int sae);\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nZero, Invalid\r\n\r\nOther Exceptions\r\nSee Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VFIXUPIMMSD"
},
{
"description": "VFIXUPIMMSS-Fix Up Special Scalar Float32 Value\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.LIG.66.0F3A.W0 55 /r ib T1S V/V AVX512F Fix up a float32 number in the low doubleword element\r\n VFIXUPIMMSS xmm1 {k1}{z}, xmm2, in xmm2 using scalar int32 table in xmm3/m32 and store\r\n xmm3/m32{sae}, imm8 the result in xmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (r, w) EVEX.vvvv ModRM:r/m (r) Imm8\r\n\r\nDescription\r\nPerform a fix-up of the low doubleword element encoded in single-precision floating-point format in the first source\r\noperand (the second operand) using a 32-bit, two-level look-up table specified in the low doubleword element of\r\nthe second source operand (the third operand) with exception reporting specifier imm8. The element that is fixed-\r\nup is selected by mask bit of 1 specified in the opmask k1. Mask bit of 0 in the opmask k1 or table response action\r\nof 0000b preserves the corresponding element of the first operand. The fixed-up element from the first source\r\noperand or the preserved element in the first operand becomes the low doubleword element of the destination\r\noperand (the first operand) Bits 127:32 of the destination operand is copied from the corresponding bits of the first\r\nsource operand. The destination and first source operands are XMM registers. The second source operand can be a\r\nXMM register or a 32-bit memory location.\r\nThe two-level look-up table perform a fix-up of each SP FP input data in the first source operand by decoding the\r\ninput data encoding into 8 token types. A response table is defined for each token type that converts the input\r\nencoding in the first source operand with one of 16 response actions.\r\nThis instruction is specifically intended for use in fixing up the results of arithmetic calculations involving one\r\nsource so that they match the spec, although it is generally useful for fixing up the results of multiple-instruction\r\nsequences to reflect special-number inputs. For example, consider rcp(0). Input 0 to rcp, and you should get INF\r\naccording to the DX10 spec. However, evaluating rcp via Newton-Raphson, where x=approx(1/0), yields an incor-\r\nrect result. To deal with this, VFIXUPIMMPD can be used after the N-R reciprocal sequence to set the result to the\r\ncorrect value (i.e. INF when the input is 0).\r\nIf MXCSR.DAZ is not set, denormal input elements in the first source operand are considered as normal inputs and\r\ndo not trigger any fixup nor fault reporting.\r\nImm8 is used to set the required flags reporting. It supports #ZE and #IE fault reporting (see details below).\r\nMXCSR.DAZ is used and refer to zmm2 only (i.e. zmm1 is not considered as zero in case MXCSR.DAZ is set).\r\nMXCSR mask bits are ignored and are treated as if all mask bits are set to masked response). If any of the imm8\r\nbits is set and the condition met for fault reporting, MXCSR.IE or MXCSR.ZE might be updated.\r\n\r\nOperation\r\nenum TOKEN_TYPE\r\n{\r\n QNAN_TOKEN <- 0,\r\n SNAN_TOKEN <- 1,\r\n ZERO_VALUE_TOKEN <- 2,\r\n POS_ONE_VALUE_TOKEN <- 3,\r\n NEG_INF_TOKEN <- 4,\r\n POS_INF_TOKEN <- 5,\r\n NEG_VALUE_TOKEN <- 6,\r\n POS_VALUE_TOKEN <- 7\r\n}\r\n\r\n\r\n\r\n\r\n\r\nFIXUPIMM_SP (dest[31:0], src1[31:0],tbl3[31:0], imm8 [7:0]){\r\n tsrc[31:0] <- ((src1[30:23] = 0) AND (MXCSR.DAZ =1)) ? 0.0 : src1[31:0]\r\n CASE(tsrc[63:0] of TOKEN_TYPE) {\r\n QNAN_TOKEN: j <- 0;\r\n SNAN_TOKEN: j <- 1;\r\n ZERO_VALUE_TOKEN: j <- 2;\r\n POS_ONE_VALUE_TOKEN: j <- 3;\r\n NEG_INF_TOKEN: j <- 4;\r\n POS_INF_TOKEN: j <- 5;\r\n NEG_VALUE_TOKEN: j <- 6;\r\n POS_VALUE_TOKEN: j = 7;\r\n } ; end source special CASE(tsrc...)\r\n\r\n ; The required response from src3 table is extracted\r\n token_response[3:0] = tbl3[3+4*j:4*j];\r\n\r\n CASE(token_response[3:0]) {\r\n 0000: dest[31:0] <- dest[31:0]; ; preserve content of DEST\r\n 0001: dest[31:0] <- tsrc[31:0]; ; pass through src1 normal input value, denormal as zero\r\n 0010: dest[31:0] <- QNaN(tsrc[31:0]);\r\n 0011: dest[31:0] <- QNAN_Indefinite;\r\n 0100: dest[31:0] <- -INF;\r\n 0101: dest[31:0] <- +INF;\r\n 0110: dest[31:0] <- tsrc.sign? -INF : +INF;\r\n 0111: dest[31:0] <- -0;\r\n 1000: dest[31:0] <- +0;\r\n 1001: dest[31:0] <- -1;\r\n 1010: dest[31:0] <- +1;\r\n 1011: dest[31:0] <- 1/2;\r\n 1100: dest[31:0] <- 90.0;\r\n 1101: dest[31:0] <- PI/2;\r\n 1110: dest[31:0] <- MAX_FLOAT;\r\n 1111: dest[31:0] <- -MAX_FLOAT;\r\n } ; end of token_response CASE\r\n\r\n ; The required fault reporting from imm8 is extracted\r\n ; TOKENs are mutually exclusive and TOKENs priority defines the order.\r\n ; Multiple faults related to a single token can occur simultaneously.\r\n IF (tsrc[31:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[0] then set #ZE;\r\n IF (tsrc[31:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[1] then set #IE;\r\n IF (tsrc[31:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[2] then set #ZE;\r\n IF (tsrc[31:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[3] then set #IE;\r\n IF (tsrc[31:0] of TOKEN_TYPE: SNAN_TOKEN) AND imm8[4] then set #IE;\r\n IF (tsrc[31:0] of TOKEN_TYPE: NEG_INF_TOKEN) AND imm8[5] then set #IE;\r\n IF (tsrc[31:0] of TOKEN_TYPE: NEG_VALUE_TOKEN) AND imm8[6] then set #IE;\r\n IF (tsrc[31:0] of TOKEN_TYPE: POS_INF_TOKEN) AND imm8[7] then set #IE;\r\n ; end fault reporting\r\n return dest[31:0];\r\n} ; end of FIXUPIMM_SP()\r\n\r\n\r\n\r\n\r\n\r\nVFIXUPIMMSS (EVEX encoded version)\r\nIF k1[0] OR *no writemask*\r\n THEN DEST[31:0] <- FIXUPIMM_SP(DEST[31:0], SRC1[31:0], SRC2[31:0], imm8 [7:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE DEST[31:0] <- 0 ; zeroing-masking\r\n FI\r\nFI;\r\nDEST[127:32] <- SRC1[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\nImmediate Control Description:\r\n\r\n\r\n\r\n\r\n 7 6 5 4 3 2 1 0\r\n\r\n + INF -> #IE\r\n - VE -> #IE\r\n - INF -> #IE\r\n SNaN -> #IE\r\n ONE -> #IE\r\n ONE -> #ZE\r\n ZERO -> #IE\r\n ZERO -> #ZE\r\n\r\n Figure 5-12. VFIXUPIMMSS Immediate Control Description\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVFIXUPIMMSS __m128 _mm_fixupimm_ss( __m128 a, __m128i tbl, int imm);\r\nVFIXUPIMMSS __m128 _mm_mask_fixupimm_ss(__m128 s, __mmask8 k, __m128 a, __m128i tbl, int imm);\r\nVFIXUPIMMSS __m128 _mm_maskz_fixupimm_ss( __mmask8 k, __m128 a, __m128i tbl, int imm);\r\nVFIXUPIMMSS __m128 _mm_fixupimm_round_ss( __m128 a, __m128i tbl, int imm, int sae);\r\nVFIXUPIMMSS __m128 _mm_mask_fixupimm_round_ss(__m128 s, __mmask8 k, __m128 a, __m128i tbl, int imm, int sae);\r\nVFIXUPIMMSS __m128 _mm_maskz_fixupimm_round_ss( __mmask8 k, __m128 a, __m128i tbl, int imm, int sae);\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nZero, Invalid\r\n\r\nOther Exceptions\r\nSee Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VFIXUPIMMSS"
},
{
"description": "VFMADD132PD/VFMADD213PD/VFMADD231PD-Fused Multiply-Add of Packed Double-\r\nPrecision Floating-Point Values\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.NDS.128.66.0F38.W1 98 /r RVM V/V FMA Multiply packed double-precision floating-point\r\n VFMADD132PD xmm1, xmm2, values from xmm1 and xmm3/mem, add to xmm2\r\n xmm3/m128 and put result in xmm1.\r\n VEX.NDS.128.66.0F38.W1 A8 /r RVM V/V FMA Multiply packed double-precision floating-point\r\n VFMADD213PD xmm1, xmm2, values from xmm1 and xmm2, add to xmm3/mem\r\n xmm3/m128 and put result in xmm1.\r\n VEX.NDS.128.66.0F38.W1 B8 /r RVM V/V FMA Multiply packed double-precision floating-point\r\n VFMADD231PD xmm1, xmm2, values from xmm2 and xmm3/mem, add to xmm1\r\n xmm3/m128 and put result in xmm1.\r\n VEX.NDS.256.66.0F38.W1 98 /r RVM V/V FMA Multiply packed double-precision floating-point\r\n VFMADD132PD ymm1, ymm2, values from ymm1 and ymm3/mem, add to ymm2\r\n ymm3/m256 and put result in ymm1.\r\n VEX.NDS.256.66.0F38.W1 A8 /r RVM V/V FMA Multiply packed double-precision floating-point\r\n VFMADD213PD ymm1, ymm2, values from ymm1 and ymm2, add to ymm3/mem\r\n ymm3/m256 and put result in ymm1.\r\n VEX.NDS.256.66.0F38.W1 B8 /r RVM V/V FMA Multiply packed double-precision floating-point\r\n VFMADD231PD ymm1, ymm2, values from ymm2 and ymm3/mem, add to ymm1\r\n ymm3/m256 and put result in ymm1.\r\n EVEX.NDS.128.66.0F38.W1 98 /r RVM V/V AVX512VL Multiply packed double-precision floating-point\r\n VFMADD132PD xmm1 {k1}{z}, xmm2, AVX512F values from xmm1 and xmm3/m128/m64bcst, add\r\n xmm3/m128/m64bcst to xmm2 and put result in xmm1.\r\n EVEX.NDS.128.66.0F38.W1 A8 /r FV V/V AVX512VL Multiply packed double-precision floating-point\r\n VFMADD213PD xmm1 {k1}{z}, xmm2, AVX512F values from xmm1 and xmm2, add to\r\n xmm3/m128/m64bcst xmm3/m128/m64bcst and put result in xmm1.\r\n EVEX.NDS.128.66.0F38.W1 B8 /r FV V/V AVX512VL Multiply packed double-precision floating-point\r\n VFMADD231PD xmm1 {k1}{z}, xmm2, AVX512F values from xmm2 and xmm3/m128/m64bcst, add\r\n xmm3/m128/m64bcst to xmm1 and put result in xmm1.\r\n EVEX.NDS.256.66.0F38.W1 98 /r FV V/V AVX512VL Multiply packed double-precision floating-point\r\n VFMADD132PD ymm1 {k1}{z}, ymm2, AVX512F values from ymm1 and ymm3/m256/m64bcst, add\r\n ymm3/m256/m64bcst to ymm2 and put result in ymm1.\r\n EVEX.NDS.256.66.0F38.W1 A8 /r FV V/V AVX512VL Multiply packed double-precision floating-point\r\n VFMADD213PD ymm1 {k1}{z}, ymm2, AVX512F values from ymm1 and ymm2, add to\r\n ymm3/m256/m64bcst ymm3/m256/m64bcst and put result in ymm1.\r\n EVEX.NDS.256.66.0F38.W1 B8 /r FV V/V AVX512VL Multiply packed double-precision floating-point\r\n VFMADD231PD ymm1 {k1}{z}, ymm2, AVX512F values from ymm2 and ymm3/m256/m64bcst, add\r\n ymm3/m256/m64bcst to ymm1 and put result in ymm1.\r\n EVEX.NDS.512.66.0F38.W1 98 /r FV V/V AVX512F Multiply packed double-precision floating-point\r\n VFMADD132PD zmm1 {k1}{z}, zmm2, values from zmm1 and zmm3/m512/m64bcst, add\r\n zmm3/m512/m64bcst{er} to zmm2 and put result in zmm1.\r\n EVEX.NDS.512.66.0F38.W1 A8 /r FV V/V AVX512F Multiply packed double-precision floating-point\r\n VFMADD213PD zmm1 {k1}{z}, zmm2, values from zmm1 and zmm2, add to\r\n zmm3/m512/m64bcst{er} zmm3/m512/m64bcst and put result in zmm1.\r\n EVEX.NDS.512.66.0F38.W1 B8 /r FV V/V AVX512F Multiply packed double-precision floating-point\r\n VFMADD231PD zmm1 {k1}{z}, zmm2, values from zmm2 and zmm3/m512/m64bcst, add\r\n zmm3/m512/m64bcst{er} to zmm1 and put result in zmm1.\r\n\r\n\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a set of SIMD multiply-add computation on packed double-precision floating-point values using three\r\nsource operands and writes the multiply-add results in the destination operand. The destination operand is also the\r\nfirst source operand. The second operand must be a SIMD register. The third source operand can be a SIMD\r\nregister or a memory location.\r\nVFMADD132PD: Multiplies the two, four or eight packed double-precision floating-point values from the first source\r\noperand to the two, four or eight packed double-precision floating-point values in the third source operand, adds\r\nthe infinite precision intermediate result to the two, four or eight packed double-precision floating-point values in\r\nthe second source operand, performs rounding and stores the resulting two, four or eight packed double-precision\r\nfloating-point values to the destination operand (first source operand).\r\nVFMADD213PD: Multiplies the two, four or eight packed double-precision floating-point values from the second\r\nsource operand to the two, four or eight packed double-precision floating-point values in the first source operand,\r\nadds the infinite precision intermediate result to the two, four or eight packed double-precision floating-point\r\nvalues in the third source operand, performs rounding and stores the resulting two, four or eight packed double-\r\nprecision floating-point values to the destination operand (first source operand).\r\nVFMADD231PD: Multiplies the two, four or eight packed double-precision floating-point values from the second\r\nsource to the two, four or eight packed double-precision floating-point values in the third source operand, adds the\r\ninfinite precision intermediate result to the two, four or eight packed double-precision floating-point values in the\r\nfirst source operand, performs rounding and stores the resulting two, four or eight packed double-precision\r\nfloating-point values to the destination operand (first source operand).\r\nEVEX encoded versions: The destination operand (also first source operand) is a ZMM register and encoded in\r\nreg_field. The second source operand is a ZMM register and encoded in EVEX.vvvv. The third source operand is a\r\nZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 64-bit memory location. The\r\ndestination operand is conditionally updated with write mask k1.\r\nVEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in\r\nreg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a\r\nYMM register or a 256-bit memory location and encoded in rm_field.\r\nVEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in\r\nreg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a\r\nXMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination\r\nregister are zeroed.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIn the operations below, \"*\" and \"+\" symbols represent multiplication and addition with infinite precision inputs and outputs (no\r\nrounding).\r\n\r\nVFMADD132PD DEST, SRC2, SRC3 (VEX encoded version)\r\nIF (VEX.128) THEN\r\n MAXNUM <-2\r\nELSEIF (VEX.256)\r\n MAXNUM <- 4\r\nFI\r\nFor i = 0 to MAXNUM-1 {\r\n n <- 64*i;\r\n DEST[n+63:n] <- RoundFPControl_MXCSR(DEST[n+63:n]*SRC3[n+63:n] + SRC2[n+63:n])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <- 0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\nVFMADD213PD DEST, SRC2, SRC3 (VEX encoded version)\r\nIF (VEX.128) THEN\r\n MAXNUM <-2\r\nELSEIF (VEX.256)\r\n MAXNUM <- 4\r\nFI\r\nFor i = 0 to MAXNUM-1 {\r\n n <- 64*i;\r\n DEST[n+63:n] <- RoundFPControl_MXCSR(SRC2[n+63:n]*DEST[n+63:n] + SRC3[n+63:n])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <- 0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\nVFMADD231PD DEST, SRC2, SRC3 (VEX encoded version)\r\nIF (VEX.128) THEN\r\n MAXNUM <-2\r\nELSEIF (VEX.256)\r\n MAXNUM <- 4\r\nFI\r\nFor i = 0 to MAXNUM-1 {\r\n n <- 64*i;\r\n DEST[n+63:n] <- RoundFPControl_MXCSR(SRC2[n+63:n]*SRC3[n+63:n] + DEST[n+63:n])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <- 0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\n\r\n\r\n\r\n\r\nVFMADD132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <-\r\n RoundFPControl(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVFMADD132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[63:0] + SRC2[i+63:i])\r\n ELSE\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMADD213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a is a register)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <-\r\n RoundFPControl(SRC2[i+63:i]*DEST[i+63:i] + SRC3[i+63:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMADD213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] + SRC3[63:0])\r\n ELSE\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] + SRC3[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVFMADD231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <-\r\n RoundFPControl(SRC2[i+63:i]*SRC3[i+63:i] + DEST[i+63:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMADD231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[63:0] + DEST[i+63:i])\r\n ELSE\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[i+63:i] + DEST[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVFMADDxxxPD __m512d _mm512_fmadd_pd(__m512d a, __m512d b, __m512d c);\r\nVFMADDxxxPD __m512d _mm512_fmadd_round_pd(__m512d a, __m512d b, __m512d c, int r);\r\nVFMADDxxxPD __m512d _mm512_mask_fmadd_pd(__m512d a, __mmask8 k, __m512d b, __m512d c);\r\nVFMADDxxxPD __m512d _mm512_maskz_fmadd_pd(__mmask8 k, __m512d a, __m512d b, __m512d c);\r\nVFMADDxxxPD __m512d _mm512_mask3_fmadd_pd(__m512d a, __m512d b, __m512d c, __mmask8 k);\r\nVFMADDxxxPD __m512d _mm512_mask_fmadd_round_pd(__m512d a, __mmask8 k, __m512d b, __m512d c, int r);\r\nVFMADDxxxPD __m512d _mm512_maskz_fmadd_round_pd(__mmask8 k, __m512d a, __m512d b, __m512d c, int r);\r\nVFMADDxxxPD __m512d _mm512_mask3_fmadd_round_pd(__m512d a, __m512d b, __m512d c, __mmask8 k, int r);\r\nVFMADDxxxPD __m256d _mm256_mask_fmadd_pd(__m256d a, __mmask8 k, __m256d b, __m256d c);\r\nVFMADDxxxPD __m256d _mm256_maskz_fmadd_pd(__mmask8 k, __m256d a, __m256d b, __m256d c);\r\nVFMADDxxxPD __m256d _mm256_mask3_fmadd_pd(__m256d a, __m256d b, __m256d c, __mmask8 k);\r\nVFMADDxxxPD __m128d _mm_mask_fmadd_pd(__m128d a, __mmask8 k, __m128d b, __m128d c);\r\nVFMADDxxxPD __m128d _mm_maskz_fmadd_pd(__mmask8 k, __m128d a, __m128d b, __m128d c);\r\nVFMADDxxxPD __m128d _mm_mask3_fmadd_pd(__m128d a, __m128d b, __m128d c, __mmask8 k);\r\nVFMADDxxxPD __m128d _mm_fmadd_pd (__m128d a, __m128d b, __m128d c);\r\nVFMADDxxxPD __m256d _mm256_fmadd_pd (__m256d a, __m256d b, __m256d c);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2.\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VFMADD132PD"
},
{
"description": "VFMADD132PS/VFMADD213PS/VFMADD231PS-Fused Multiply-Add of Packed Single-\r\nPrecision Floating-Point Values\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.NDS.128.66.0F38.W0 98 /r RVM V/V FMA Multiply packed single-precision floating-point values\r\n VFMADD132PS xmm1, xmm2, from xmm1 and xmm3/mem, add to xmm2 and put\r\n xmm3/m128 result in xmm1.\r\n VEX.NDS.128.66.0F38.W0 A8 /r RVM V/V FMA Multiply packed single-precision floating-point values\r\n VFMADD213PS xmm1, xmm2, from xmm1 and xmm2, add to xmm3/mem and put\r\n xmm3/m128 result in xmm1.\r\n VEX.NDS.128.66.0F38.W0 B8 /r RVM V/V FMA Multiply packed single-precision floating-point values\r\n VFMADD231PS xmm1, xmm2, from xmm2 and xmm3/mem, add to xmm1 and put\r\n xmm3/m128 result in xmm1.\r\n VEX.NDS.256.66.0F38.W0 98 /r RVM V/V FMA Multiply packed single-precision floating-point values\r\n VFMADD132PS ymm1, ymm2, from ymm1 and ymm3/mem, add to ymm2 and put\r\n ymm3/m256 result in ymm1.\r\n VEX.NDS.256.66.0F38.W0 A8 /r RVM V/V FMA Multiply packed single-precision floating-point values\r\n VFMADD213PS ymm1, ymm2, from ymm1 and ymm2, add to ymm3/mem and put\r\n ymm3/m256 result in ymm1.\r\n VEX.NDS.256.66.0F38.0 B8 /r RVM V/V FMA Multiply packed single-precision floating-point values\r\n VFMADD231PS ymm1, ymm2, from ymm2 and ymm3/mem, add to ymm1 and put\r\n ymm3/m256 result in ymm1.\r\n EVEX.NDS.128.66.0F38.W0 98 /r FV V/V AVX512VL Multiply packed single-precision floating-point values\r\n VFMADD132PS xmm1 {k1}{z}, xmm2, AVX512F from xmm1 and xmm3/m128/m32bcst, add to\r\n xmm3/m128/m32bcst xmm2 and put result in xmm1.\r\n EVEX.NDS.128.66.0F38.W0 A8 /r FV V/V AVX512VL Multiply packed single-precision floating-point values\r\n VFMADD213PS xmm1 {k1}{z}, xmm2, AVX512F from xmm1 and xmm2, add to\r\n xmm3/m128/m32bcst xmm3/m128/m32bcst and put result in xmm1.\r\n EVEX.NDS.128.66.0F38.W0 B8 /r FV V/V AVX512VL Multiply packed single-precision floating-point values\r\n VFMADD231PS xmm1 {k1}{z}, xmm2, AVX512F from xmm2 and xmm3/m128/m32bcst, add to\r\n xmm3/m128/m32bcst xmm1 and put result in xmm1.\r\n EVEX.NDS.256.66.0F38.W0 98 /r FV V/V AVX512VL Multiply packed single-precision floating-point values\r\n VFMADD132PS ymm1 {k1}{z}, ymm2, AVX512F from ymm1 and ymm3/m256/m32bcst, add to\r\n ymm3/m256/m32bcst ymm2 and put result in ymm1.\r\n EVEX.NDS.256.66.0F38.W0 A8 /r FV V/V AVX512VL Multiply packed single-precision floating-point values\r\n VFMADD213PS ymm1 {k1}{z}, ymm2, AVX512F from ymm1 and ymm2, add to\r\n ymm3/m256/m32bcst ymm3/m256/m32bcst and put result in ymm1.\r\n EVEX.NDS.256.66.0F38.W0 B8 /r FV V/V AVX512VL Multiply packed single-precision floating-point values\r\n VFMADD231PS ymm1 {k1}{z}, ymm2, AVX512F from ymm2 and ymm3/m256/m32bcst, add to\r\n ymm3/m256/m32bcst ymm1 and put result in ymm1.\r\n EVEX.NDS.512.66.0F38.W0 98 /r FV V/V AVX512F Multiply packed single-precision floating-point values\r\n VFMADD132PS zmm1 {k1}{z}, zmm2, from zmm1 and zmm3/m512/m32bcst, add to\r\n zmm3/m512/m32bcst{er} zmm2 and put result in zmm1.\r\n EVEX.NDS.512.66.0F38.W0 A8 /r FV V/V AVX512F Multiply packed single-precision floating-point values\r\n VFMADD213PS zmm1 {k1}{z}, zmm2, from zmm1 and zmm2, add to\r\n zmm3/m512/m32bcst{er} zmm3/m512/m32bcst and put result in zmm1.\r\n EVEX.NDS.512.66.0F38.W0 B8 /r FV V/V AVX512F Multiply packed single-precision floating-point values\r\n VFMADD231PS zmm1 {k1}{z}, zmm2, from zmm2 and zmm3/m512/m32bcst, add to\r\n zmm3/m512/m32bcst{er} zmm1 and put result in zmm1.\r\n\r\n\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a set of SIMD multiply-add computation on packed single-precision floating-point values using three\r\nsource operands and writes the multiply-add results in the destination operand. The destination operand is also the\r\nfirst source operand. The second operand must be a SIMD register. The third source operand can be a SIMD\r\nregister or a memory location.\r\nVFMADD132PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the first\r\nsource operand to the four, eight or sixteen packed single-precision floating-point values in the third source\r\noperand, adds the infinite precision intermediate result to the four, eight or sixteen packed single-precision\r\nfloating-point values in the second source operand, performs rounding and stores the resulting four, eight or\r\nsixteen packed single-precision floating-point values to the destination operand (first source operand).\r\nVFMADD213PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second\r\nsource operand to the four, eight or sixteen packed single-precision floating-point values in the first source\r\noperand, adds the infinite precision intermediate result to the four, eight or sixteen packed single-precision\r\nfloating-point values in the third source operand, performs rounding and stores the resulting the four, eight or\r\nsixteen packed single-precision floating-point values to the destination operand (first source operand).\r\nVFMADD231PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second\r\nsource operand to the four, eight or sixteen packed single-precision floating-point values in the third source\r\noperand, adds the infinite precision intermediate result to the four, eight or sixteen packed single-precision\r\nfloating-point values in the first source operand, performs rounding and stores the resulting four, eight or sixteen\r\npacked single-precision floating-point values to the destination operand (first source operand).\r\nEVEX encoded versions: The destination operand (also first source operand) is a ZMM register and encoded in\r\nreg_field. The second source operand is a ZMM register and encoded in EVEX.vvvv. The third source operand is a\r\nZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit memory location. The\r\ndestination operand is conditionally updated with write mask k1.\r\nVEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in\r\nreg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a\r\nYMM register or a 256-bit memory location and encoded in rm_field.\r\nVEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in\r\nreg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a\r\nXMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination\r\nregister are zeroed.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIn the operations below, \"*\" and \"+\" symbols represent multiplication and addition with infinite precision inputs and outputs (no\r\nrounding).\r\n\r\nVFMADD132PS DEST, SRC2, SRC3\r\nIF (VEX.128) THEN\r\n MAXNUM <-4\r\nELSEIF (VEX.256)\r\n MAXNUM <- 8\r\nFI\r\nFor i = 0 to MAXNUM-1 {\r\n n <- 32*i;\r\n DEST[n+31:n] <- RoundFPControl_MXCSR(DEST[n+31:n]*SRC3[n+31:n] + SRC2[n+31:n])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <- 0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\nVFMADD213PS DEST, SRC2, SRC3\r\nIF (VEX.128) THEN\r\n MAXNUM <-4\r\nELSEIF (VEX.256)\r\n MAXNUM <- 8\r\nFI\r\nFor i = 0 to MAXNUM-1 {\r\n n <- 32*i;\r\n DEST[n+31:n] <- RoundFPControl_MXCSR(SRC2[n+31:n]*DEST[n+31:n] + SRC3[n+31:n])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <- 0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\nVFMADD231PS DEST, SRC2, SRC3\r\nIF (VEX.128) THEN\r\n MAXNUM <-4\r\nELSEIF (VEX.256)\r\n MAXNUM <- 8\r\nFI\r\nFor i = 0 to MAXNUM-1 {\r\n n <- 32*i;\r\n DEST[n+31:n] <- RoundFPControl_MXCSR(SRC2[n+31:n]*SRC3[n+31:n] + DEST[n+31:n])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <- 0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\n\r\n\r\n\r\n\r\nVFMADD132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <-\r\n RoundFPControl(DEST[i+31:i]*SRC3[i+31:i] + SRC2[i+31:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVFMADD132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[31:0] + SRC2[i+31:i])\r\n ELSE\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] + SRC2[i+31:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMADD213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <-\r\n RoundFPControl(SRC2[i+31:i]*DEST[i+31:i] + SRC3[i+31:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMADD213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] + SRC3[31:0])\r\n ELSE\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] + SRC3[i+31:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVFMADD231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <-\r\n RoundFPControl(SRC2[i+31:i]*SRC3[i+31:i] + DEST[i+31:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMADD231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[31:0] + DEST[i+31:i])\r\n ELSE\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] + DEST[i+31:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVFMADDxxxPS __m512 _mm512_fmadd_ps(__m512 a, __m512 b, __m512 c);\r\nVFMADDxxxPS __m512 _mm512_fmadd_round_ps(__m512 a, __m512 b, __m512 c, int r);\r\nVFMADDxxxPS __m512 _mm512_mask_fmadd_ps(__m512 a, __mmask16 k, __m512 b, __m512 c);\r\nVFMADDxxxPS __m512 _mm512_maskz_fmadd_ps(__mmask16 k, __m512 a, __m512 b, __m512 c);\r\nVFMADDxxxPS __m512 _mm512_mask3_fmadd_ps(__m512 a, __m512 b, __m512 c, __mmask16 k);\r\nVFMADDxxxPS __m512 _mm512_mask_fmadd_round_ps(__m512 a, __mmask16 k, __m512 b, __m512 c, int r);\r\nVFMADDxxxPS __m512 _mm512_maskz_fmadd_round_ps(__mmask16 k, __m512 a, __m512 b, __m512 c, int r);\r\nVFMADDxxxPS __m512 _mm512_mask3_fmadd_round_ps(__m512 a, __m512 b, __m512 c, __mmask16 k, int r);\r\nVFMADDxxxPS __m256 _mm256_mask_fmadd_ps(__m256 a, __mmask8 k, __m256 b, __m256 c);\r\nVFMADDxxxPS __m256 _mm256_maskz_fmadd_ps(__mmask8 k, __m256 a, __m256 b, __m256 c);\r\nVFMADDxxxPS __m256 _mm256_mask3_fmadd_ps(__m256 a, __m256 b, __m256 c, __mmask8 k);\r\nVFMADDxxxPS __m128 _mm_mask_fmadd_ps(__m128 a, __mmask8 k, __m128 b, __m128 c);\r\nVFMADDxxxPS __m128 _mm_maskz_fmadd_ps(__mmask8 k, __m128 a, __m128 b, __m128 c);\r\nVFMADDxxxPS __m128 _mm_mask3_fmadd_ps(__m128 a, __m128 b, __m128 c, __mmask8 k);\r\nVFMADDxxxPS __m128 _mm_fmadd_ps (__m128 a, __m128 b, __m128 c);\r\nVFMADDxxxPS __m256 _mm256_fmadd_ps (__m256 a, __m256 b, __m256 c);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2.\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VFMADD132PS"
},
{
"description": "VFMADD132SD/VFMADD213SD/VFMADD231SD-Fused Multiply-Add of Scalar Double-\r\nPrecision Floating-Point Values\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.DDS.LIG.66.0F38.W1 99 /r RVM V/V FMA Multiply scalar double-precision floating-point value\r\n VFMADD132SD xmm1, xmm2, from xmm1 and xmm3/m64, add to xmm2 and put\r\n xmm3/m64 result in xmm1.\r\n VEX.DDS.LIG.66.0F38.W1 A9 /r RVM V/V FMA Multiply scalar double-precision floating-point value\r\n VFMADD213SD xmm1, xmm2, from xmm1 and xmm2, add to xmm3/m64 and put\r\n xmm3/m64 result in xmm1.\r\n VEX.DDS.LIG.66.0F38.W1 B9 /r RVM V/V FMA Multiply scalar double-precision floating-point value\r\n VFMADD231SD xmm1, xmm2, from xmm2 and xmm3/m64, add to xmm1 and put\r\n xmm3/m64 result in xmm1.\r\n EVEX.DDS.LIG.66.0F38.W1 99 /r T1S V/V AVX512F Multiply scalar double-precision floating-point value\r\n VFMADD132SD xmm1 {k1}{z}, xmm2, from xmm1 and xmm3/m64, add to xmm2 and put\r\n xmm3/m64{er} result in xmm1.\r\n EVEX.DDS.LIG.66.0F38.W1 A9 /r T1S V/V AVX512F Multiply scalar double-precision floating-point value\r\n VFMADD213SD xmm1 {k1}{z}, xmm2, from xmm1 and xmm2, add to xmm3/m64 and put\r\n xmm3/m64{er} result in xmm1.\r\n EVEX.DDS.LIG.66.0F38.W1 B9 /r T1S V/V AVX512F Multiply scalar double-precision floating-point value\r\n VFMADD231SD xmm1 {k1}{z}, xmm2, from xmm2 and xmm3/m64, add to xmm1 and put\r\n xmm3/m64{er} result in xmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n T1S ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a SIMD multiply-add computation on the low double-precision floating-point values using three source\r\noperands and writes the multiply-add result in the destination operand. The destination operand is also the first\r\nsource operand. The first and second operand are XMM registers. The third source operand can be an XMM register\r\nor a 64-bit memory location.\r\nVFMADD132SD: Multiplies the low double-precision floating-point value from the first source operand to the low\r\ndouble-precision floating-point value in the third source operand, adds the infinite precision intermediate result to\r\nthe low double-precision floating-point values in the second source operand, performs rounding and stores the\r\nresulting double-precision floating-point value to the destination operand (first source operand).\r\nVFMADD213SD: Multiplies the low double-precision floating-point value from the second source operand to the low\r\ndouble-precision floating-point value in the first source operand, adds the infinite precision intermediate result to\r\nthe low double-precision floating-point value in the third source operand, performs rounding and stores the\r\nresulting double-precision floating-point value to the destination operand (first source operand).\r\nVFMADD231SD: Multiplies the low double-precision floating-point value from the second source to the low double-\r\nprecision floating-point value in the third source operand, adds the infinite precision intermediate result to the low\r\ndouble-precision floating-point value in the first source operand, performs rounding and stores the resulting\r\ndouble-precision floating-point value to the destination operand (first source operand).\r\nVEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field.\r\nThe second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field.\r\nBits 127:64 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.\r\nEVEX encoded version: The low quadword element of the destination is updated according to the writemask.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIn the operations below, \"*\" and \"+\" symbols represent multiplication and addition with infinite precision inputs and outputs (no\r\nrounding).\r\n\r\nVFMADD132SD DEST, SRC2, SRC3 (EVEX encoded version)\r\nIF (EVEX.b = 1) and SRC3 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[63:0] <- RoundFPControl(DEST[63:0]*SRC3[63:0] + SRC2[63:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[63:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:64] <- DEST[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVFMADD213SD DEST, SRC2, SRC3 (EVEX encoded version)\r\nIF (EVEX.b = 1) and SRC3 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[63:0] <- RoundFPControl(SRC2[63:0]*DEST[63:0] + SRC3[63:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[63:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:64] <- DEST[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMADD231SD DEST, SRC2, SRC3 (EVEX encoded version)\r\nIF (EVEX.b = 1) and SRC3 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[63:0] <- RoundFPControl(SRC2[63:0]*SRC3[63:0] + DEST[63:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[63:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:64] <- DEST[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVFMADD132SD DEST, SRC2, SRC3 (VEX encoded version)\r\nDEST[63:0] <- MAX_VL-1:128RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] + SRC2[63:0])\r\nDEST[127:63] <- DEST[127:63]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVFMADD213SD DEST, SRC2, SRC3 (VEX encoded version)\r\nDEST[63:0] <- RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] + SRC3[63:0])\r\nDEST[127:63] <- DEST[127:63]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVFMADD231SD DEST, SRC2, SRC3 (VEX encoded version)\r\nDEST[63:0] <- RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] + DEST[63:0])\r\nDEST[127:63] <- DEST[127:63]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVFMADDxxxSD __m128d _mm_fmadd_round_sd(__m128d a, __m128d b, __m128d c, int r);\r\nVFMADDxxxSD __m128d _mm_mask_fmadd_sd(__m128d a, __mmask8 k, __m128d b, __m128d c);\r\nVFMADDxxxSD __m128d _mm_maskz_fmadd_sd(__mmask8 k, __m128d a, __m128d b, __m128d c);\r\nVFMADDxxxSD __m128d _mm_mask3_fmadd_sd(__m128d a, __m128d b, __m128d c, __mmask8 k);\r\nVFMADDxxxSD __m128d _mm_mask_fmadd_round_sd(__m128d a, __mmask8 k, __m128d b, __m128d c, int r);\r\nVFMADDxxxSD __m128d _mm_maskz_fmadd_round_sd(__mmask8 k, __m128d a, __m128d b, __m128d c, int r);\r\nVFMADDxxxSD __m128d _mm_mask3_fmadd_round_sd(__m128d a, __m128d b, __m128d c, __mmask8 k, int r);\r\nVFMADDxxxSD __m128d _mm_fmadd_sd (__m128d a, __m128d b, __m128d c);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3.\r\nEVEX-encoded instructions, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VFMADD132SD"
},
{
"description": "VFMADD132SS/VFMADD213SS/VFMADD231SS-Fused Multiply-Add of Scalar Single-Precision\r\nFloating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.DDS.LIG.66.0F38.W0 99 /r RVM V/V FMA Multiply scalar single-precision floating-point value\r\n VFMADD132SS xmm1, xmm2, from xmm1 and xmm3/m32, add to xmm2 and put\r\n xmm3/m32 result in xmm1.\r\n VEX.DDS.LIG.66.0F38.W0 A9 /r RVM V/V FMA Multiply scalar single-precision floating-point value\r\n VFMADD213SS xmm1, xmm2, from xmm1 and xmm2, add to xmm3/m32 and put\r\n xmm3/m32 result in xmm1.\r\n VEX.DDS.LIG.66.0F38.W0 B9 /r RVM V/V FMA Multiply scalar single-precision floating-point value\r\n VFMADD231SS xmm1, xmm2, from xmm2 and xmm3/m32, add to xmm1 and put\r\n xmm3/m32 result in xmm1.\r\n EVEX.DDS.LIG.66.0F38.W0 99 /r T1S V/V AVX512F Multiply scalar single-precision floating-point value\r\n VFMADD132SS xmm1 {k1}{z}, xmm2, from xmm1 and xmm3/m32, add to xmm2 and put\r\n xmm3/m32{er} result in xmm1.\r\n EVEX.DDS.LIG.66.0F38.W0 A9 /r T1S V/V AVX512F Multiply scalar single-precision floating-point value\r\n VFMADD213SS xmm1 {k1}{z}, xmm2, from xmm1 and xmm2, add to xmm3/m32 and put\r\n xmm3/m32{er} result in xmm1.\r\n EVEX.DDS.LIG.66.0F38.W0 B9 /r T1S V/V AVX512F Multiply scalar single-precision floating-point value\r\n VFMADD231SS xmm1 {k1}{z}, xmm2, from xmm2 and xmm3/m32, add to xmm1 and put\r\n xmm3/m32{er} result in xmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n T1S ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a SIMD multiply-add computation on single-precision floating-point values using three source operands\r\nand writes the multiply-add results in the destination operand. The destination operand is also the first source\r\noperand. The first and second operands are XMM registers. The third source operand can be a XMM register or a\r\n32-bit memory location.\r\nVFMADD132SS: Multiplies the low single-precision floating-point value from the first source operand to the low\r\nsingle-precision floating-point value in the third source operand, adds the infinite precision intermediate result to\r\nthe low single-precision floating-point value in the second source operand, performs rounding and stores the\r\nresulting single-precision floating-point value to the destination operand (first source operand).\r\nVFMADD213SS: Multiplies the low single-precision floating-point value from the second source operand to the low\r\nsingle-precision floating-point value in the first source operand, adds the infinite precision intermediate result to\r\nthe low single-precision floating-point value in the third source operand, performs rounding and stores the\r\nresulting single-precision floating-point value to the destination operand (first source operand).\r\nVFMADD231SS: Multiplies the low single-precision floating-point value from the second source operand to the low\r\nsingle-precision floating-point value in the third source operand, adds the infinite precision intermediate result to\r\nthe low single-precision floating-point value in the first source operand, performs rounding and stores the resulting\r\nsingle-precision floating-point value to the destination operand (first source operand).\r\nVEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field.\r\nThe second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field.\r\nBits 127:32 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.\r\n\r\n\r\n\r\n\r\n\r\nEVEX encoded version: The low doubleword element of the destination is updated according to the writemask.\r\nCompiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the\r\nopcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations\r\ninvolving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction\r\ncolumn.\r\n\r\nOperation\r\nIn the operations below, \"*\" and \"+\" symbols represent multiplication and addition with infinite precision inputs and outputs (no\r\nrounding).\r\n\r\nVFMADD132SS DEST, SRC2, SRC3 (EVEX encoded version)\r\nIF (EVEX.b = 1) and SRC3 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[31:0] <- RoundFPControl(DEST[31:0]*SRC3[31:0] + SRC2[31:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[31:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:32] <- DEST[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVFMADD213SS DEST, SRC2, SRC3 (EVEX encoded version)\r\nIF (EVEX.b = 1) and SRC3 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[31:0] <- RoundFPControl(SRC2[31:0]*DEST[31:0] + SRC3[31:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[31:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:32] <- DEST[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMADD231SS DEST, SRC2, SRC3 (EVEX encoded version)\r\nIF (EVEX.b = 1) and SRC3 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[31:0] <- RoundFPControl(SRC2[31:0]*SRC3[31:0] + DEST[31:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0]] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[31:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:32] <- DEST[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVFMADD132SS DEST, SRC2, SRC3 (VEX encoded version)\r\nDEST[31:0] <-RoundFPControl_MXCSR(DEST[31:0]*SRC3[31:0] + SRC2[31:0])\r\nDEST[127:32] <-DEST[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVFMADD213SS DEST, SRC2, SRC3 (VEX encoded version)\r\nDEST[31:0] <-RoundFPControl_MXCSR(SRC2[31:0]*DEST[31:0] + SRC3[31:0])\r\nDEST[127:32] <-DEST[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVFMADD231SS DEST, SRC2, SRC3 (VEX encoded version)\r\nDEST[31:0] <-RoundFPControl_MXCSR(SRC2[31:0]*SRC3[31:0] + DEST[31:0])\r\nDEST[127:32] <-DEST[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVFMADDxxxSS __m128 _mm_fmadd_round_ss(__m128 a, __m128 b, __m128 c, int r);\r\nVFMADDxxxSS __m128 _mm_mask_fmadd_ss(__m128 a, __mmask8 k, __m128 b, __m128 c);\r\nVFMADDxxxSS __m128 _mm_maskz_fmadd_ss(__mmask8 k, __m128 a, __m128 b, __m128 c);\r\nVFMADDxxxSS __m128 _mm_mask3_fmadd_ss(__m128 a, __m128 b, __m128 c, __mmask8 k);\r\nVFMADDxxxSS __m128 _mm_mask_fmadd_round_ss(__m128 a, __mmask8 k, __m128 b, __m128 c, int r);\r\nVFMADDxxxSS __m128 _mm_maskz_fmadd_round_ss(__mmask8 k, __m128 a, __m128 b, __m128 c, int r);\r\nVFMADDxxxSS __m128 _mm_mask3_fmadd_round_ss(__m128 a, __m128 b, __m128 c, __mmask8 k, int r);\r\nVFMADDxxxSS __m128 _mm_fmadd_ss (__m128 a, __m128 b, __m128 c);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3.\r\nEVEX-encoded instructions, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VFMADD132SS"
},
{
"description": "-R:VFMADD132PD",
"mnem": "VFMADD213PD"
},
{
"description": "-R:VFMADD132PS",
"mnem": "VFMADD213PS"
},
{
"description": "-R:VFMADD132SD",
"mnem": "VFMADD213SD"
},
{
"description": "-R:VFMADD132SS",
"mnem": "VFMADD213SS"
},
{
"description": "-R:VFMADD132PD",
"mnem": "VFMADD231PD"
},
{
"description": "-R:VFMADD132PS",
"mnem": "VFMADD231PS"
},
{
"description": "-R:VFMADD132SD",
"mnem": "VFMADD231SD"
},
{
"description": "-R:VFMADD132SS",
"mnem": "VFMADD231SS"
},
{
"description": "VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD-Fused Multiply-Alternating\r\nAdd/Subtract of Packed Double-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.DDS.128.66.0F38.W1 96 /r RVM V/V FMA Multiply packed double-precision floating-point values\r\n VFMADDSUB132PD xmm1, xmm2, from xmm1 and xmm3/mem, add/subtract elements in\r\n xmm3/m128 xmm2 and put result in xmm1.\r\n VEX.DDS.128.66.0F38.W1 A6 /r RVM V/V FMA Multiply packed double-precision floating-point values\r\n VFMADDSUB213PD xmm1, xmm2, from xmm1 and xmm2, add/subtract elements in\r\n xmm3/m128 xmm3/mem and put result in xmm1.\r\n VEX.DDS.128.66.0F38.W1 B6 /r RVM V/V FMA Multiply packed double-precision floating-point values\r\n VFMADDSUB231PD xmm1, xmm2, from xmm2 and xmm3/mem, add/subtract elements in\r\n xmm3/m128 xmm1 and put result in xmm1.\r\n VEX.DDS.256.66.0F38.W1 96 /r RVM V/V FMA Multiply packed double-precision floating-point values\r\n VFMADDSUB132PD ymm1, ymm2, from ymm1 and ymm3/mem, add/subtract elements in\r\n ymm3/m256 ymm2 and put result in ymm1.\r\n VEX.DDS.256.66.0F38.W1 A6 /r RVM V/V FMA Multiply packed double-precision floating-point values\r\n VFMADDSUB213PD ymm1, ymm2, from ymm1 and ymm2, add/subtract elements in\r\n ymm3/m256 ymm3/mem and put result in ymm1.\r\n VEX.DDS.256.66.0F38.W1 B6 /r RVM V/V FMA Multiply packed double-precision floating-point values\r\n VFMADDSUB231PD ymm1, ymm2, from ymm2 and ymm3/mem, add/subtract elements in\r\n ymm3/m256 ymm1 and put result in ymm1.\r\n EVEX.DDS.128.66.0F38.W1 A6 /r FV V/V AVX512VL Multiply packed double-precision floating-point values\r\n VFMADDSUB213PD xmm1 {k1}{z}, AVX512F from xmm1 and xmm2, add/subtract elements in\r\n xmm2, xmm3/m128/m64bcst xmm3/m128/m64bcst and put result in xmm1 subject to\r\n writemask k1.\r\n EVEX.DDS.128.66.0F38.W1 B6 /r FV V/V AVX512VL Multiply packed double-precision floating-point values\r\n VFMADDSUB231PD xmm1 {k1}{z}, AVX512F from xmm2 and xmm3/m128/m64bcst, add/subtract\r\n xmm2, xmm3/m128/m64bcst elements in xmm1 and put result in xmm1 subject to\r\n writemask k1.\r\n EVEX.DDS.128.66.0F38.W1 96 /r FV V/V AVX512VL Multiply packed double-precision floating-point values\r\n VFMADDSUB132PD xmm1 {k1}{z}, AVX512F from xmm1 and xmm3/m128/m64bcst, add/subtract\r\n xmm2, xmm3/m128/m64bcst elements in xmm2 and put result in xmm1 subject to\r\n writemask k1.\r\n EVEX.DDS.256.66.0F38.W1 A6 /r FV V/V AVX512VL Multiply packed double-precision floating-point values\r\n VFMADDSUB213PD ymm1 {k1}{z}, AVX512F from ymm1 and ymm2, add/subtract elements in\r\n ymm2, ymm3/m256/m64bcst ymm3/m256/m64bcst and put result in ymm1 subject to\r\n writemask k1.\r\n EVEX.DDS.256.66.0F38.W1 B6 /r FV V/V AVX512VL Multiply packed double-precision floating-point values\r\n VFMADDSUB231PD ymm1 {k1}{z}, AVX512F from ymm2 and ymm3/m256/m64bcst, add/subtract\r\n ymm2, ymm3/m256/m64bcst elements in ymm1 and put result in ymm1 subject to\r\n writemask k1.\r\n EVEX.DDS.256.66.0F38.W1 96 /r FV V/V AVX512VL Multiply packed double-precision floating-point values\r\n VFMADDSUB132PD ymm1 {k1}{z}, AVX512F from ymm1 and ymm3/m256/m64bcst, add/subtract\r\n ymm2, ymm3/m256/m64bcst elements in ymm2 and put result in ymm1 subject to\r\n writemask k1.\r\n\r\n\r\n\r\n\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.DDS.512.66.0F38.W1 A6 /r FV V/V AVX512F Multiply packed double-precision floating-point values\r\n VFMADDSUB213PD zmm1 {k1}{z}, from zmm1and zmm2, add/subtract elements in\r\n zmm2, zmm3/m512/m64bcst{er} zmm3/m512/m64bcst and put result in zmm1 subject to\r\n writemask k1.\r\n EVEX.DDS.512.66.0F38.W1 B6 /r FV V/V AVX512F Multiply packed double-precision floating-point values\r\n VFMADDSUB231PD zmm1 {k1}{z}, from zmm2 and zmm3/m512/m64bcst, add/subtract\r\n zmm2, zmm3/m512/m64bcst{er} elements in zmm1 and put result in zmm1 subject to\r\n writemask k1.\r\n EVEX.DDS.512.66.0F38.W1 96 /r FV V/V AVX512F Multiply packed double-precision floating-point values\r\n VFMADDSUB132PD zmm1 {k1}{z}, from zmm1 and zmm3/m512/m64bcst, add/subtract\r\n zmm2, zmm3/m512/m64bcst{er} elements in zmm2 and put result in zmm1 subject to\r\n writemask k1.\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nVFMADDSUB132PD: Multiplies the two, four, or eight packed double-precision floating-point values from the first\r\nsource operand to the two or four packed double-precision floating-point values in the third source operand. From\r\nthe infinite precision intermediate result, adds the odd double-precision floating-point elements and subtracts the\r\neven double-precision floating-point values in the second source operand, performs rounding and stores the\r\nresulting two or four packed double-precision floating-point values to the destination operand (first source\r\noperand).\r\nVFMADDSUB213PD: Multiplies the two, four, or eight packed double-precision floating-point values from the\r\nsecond source operand to the two or four packed double-precision floating-point values in the first source operand.\r\nFrom the infinite precision intermediate result, adds the odd double-precision floating-point elements and\r\nsubtracts the even double-precision floating-point values in the third source operand, performs rounding and\r\nstores the resulting two or four packed double-precision floating-point values to the destination operand (first\r\nsource operand).\r\nVFMADDSUB231PD: Multiplies the two, four, or eight packed double-precision floating-point values from the\r\nsecond source operand to the two or four packed double-precision floating-point values in the third source\r\noperand. From the infinite precision intermediate result, adds the odd double-precision floating-point elements and\r\nsubtracts the even double-precision floating-point values in the first source operand, performs rounding and stores\r\nthe resulting two or four packed double-precision floating-point values to the destination operand (first source\r\noperand).\r\nEVEX encoded versions: The destination operand (also first source operand) and the second source operand are\r\nZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-\r\ntion or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is condition-\r\nally updated with write mask k1.\r\nVEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in\r\nreg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a\r\nYMM register or a 256-bit memory location and encoded in rm_field.\r\n\r\n\r\n\r\n\r\n\r\nVEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in\r\nreg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a\r\nXMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination\r\nregister are zeroed.\r\nCompiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the\r\nopcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations\r\ninvolving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction\r\ncolumn.\r\n\r\nOperation\r\nIn the operations below, \"*\" and \"-\" symbols represent multiplication and subtraction with infinite precision inputs and outputs (no\r\nrounding).\r\n\r\nVFMADDSUB132PD DEST, SRC2, SRC3\r\nIF (VEX.128) THEN\r\n DEST[63:0] <-RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] - SRC2[63:0])\r\n DEST[127:64] <-RoundFPControl_MXCSR(DEST[127:64]*SRC3[127:64] + SRC2[127:64])\r\n DEST[MAX_VL-1:128] <-0\r\nELSEIF (VEX.256)\r\n DEST[63:0] <-RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] - SRC2[63:0])\r\n DEST[127:64] <-RoundFPControl_MXCSR(DEST[127:64]*SRC3[127:64] + SRC2[127:64])\r\n DEST[191:128] <-RoundFPControl_MXCSR(DEST[191:128]*SRC3[191:128] - SRC2[191:128])\r\n DEST[255:192] <-RoundFPControl_MXCSR(DEST[255:192]*SRC3[255:192] + SRC2[255:192]\r\nFI\r\n\r\nVFMADDSUB213PD DEST, SRC2, SRC3\r\nIF (VEX.128) THEN\r\n DEST[63:0] <-RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] - SRC3[63:0])\r\n DEST[127:64] <-RoundFPControl_MXCSR(SRC2[127:64]*DEST[127:64] + SRC3[127:64])\r\n DEST[MAX_VL-1:128] <-0\r\nELSEIF (VEX.256)\r\n DEST[63:0] <-RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] - SRC3[63:0])\r\n DEST[127:64] <-RoundFPControl_MXCSR(SRC2[127:64]*DEST[127:64] + SRC3[127:64])\r\n DEST[191:128] <-RoundFPControl_MXCSR(SRC2[191:128]*DEST[191:128] - SRC3[191:128])\r\n DEST[255:192] <-RoundFPControl_MXCSR(SRC2[255:192]*DEST[255:192] + SRC3[255:192]\r\nFI\r\n\r\nVFMADDSUB231PD DEST, SRC2, SRC3\r\nIF (VEX.128) THEN\r\n DEST[63:0] <-RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] - DEST[63:0])\r\n DEST[127:64] <-RoundFPControl_MXCSR(SRC2[127:64]*SRC3[127:64] + DEST[127:64])\r\n DEST[MAX_VL-1:128] <-0\r\nELSEIF (VEX.256)\r\n DEST[63:0] <-RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] - DEST[63:0])\r\n DEST[127:64] <-RoundFPControl_MXCSR(SRC2[127:64]*SRC3[127:64] + DEST[127:64])\r\n DEST[191:128] <-RoundFPControl_MXCSR(SRC2[191:128]*SRC3[191:128] - DEST[191:128])\r\n DEST[255:192] <-RoundFPControl_MXCSR(SRC2[255:192]*SRC3[255:192] + DEST[255:192]\r\nFI\r\n\r\n\r\n\r\n\r\n\r\nVFMADDSUB132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF j *is even*\r\n THEN DEST[i+63:i] <-\r\n RoundFPControl(DEST[i+63:i]*SRC3[i+63:i] - SRC2[i+63:i])\r\n ELSE DEST[i+63:i] <-\r\n RoundFPControl(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i])\r\n FI\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMADDSUB132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF j *is even*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[63:0] - SRC2[i+63:i])\r\n ELSE\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] - SRC2[i+63:i])\r\n FI;\r\n ELSE\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[63:0] + SRC2[i+63:i])\r\n ELSE\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i])\r\n FI;\r\n FI\r\n\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMADDSUB213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF j *is even*\r\n THEN DEST[i+63:i] <-\r\n RoundFPControl(SRC2[i+63:i]*DEST[i+63:i] - SRC3[i+63:i])\r\n ELSE DEST[i+63:i] <-\r\n RoundFPControl(SRC2[i+63:i]*DEST[i+63:i] + SRC3[i+63:i])\r\n FI\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMADDSUB213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF j *is even*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] - SRC3[63:0])\r\n ELSE\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] - SRC3[i+63:i])\r\n FI;\r\n ELSE\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] + SRC3[63:0])\r\n ELSE\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] + SRC3[i+63:i])\r\n FI;\r\n FI\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMADDSUB231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF j *is even*\r\n THEN DEST[i+63:i] <-\r\n RoundFPControl(SRC2[i+63:i]*SRC3[i+63:i] - DEST[i+63:i])\r\n ELSE DEST[i+63:i] <-\r\n RoundFPControl(SRC2[i+63:i]*SRC3[i+63:i] + DEST[i+63:i])\r\n FI\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMADDSUB231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF j *is even*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[63:0] - DEST[i+63:i])\r\n ELSE\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[i+63:i] - DEST[i+63:i])\r\n FI;\r\n ELSE\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[63:0] + DEST[i+63:i])\r\n ELSE\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[i+63:i] + DEST[i+63:i])\r\n FI;\r\n FI\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVFMADDSUBxxxPD __m512d _mm512_fmaddsub_pd(__m512d a, __m512d b, __m512d c);\r\nVFMADDSUBxxxPD __m512d _mm512_fmaddsub_round_pd(__m512d a, __m512d b, __m512d c, int r);\r\nVFMADDSUBxxxPD __m512d _mm512_mask_fmaddsub_pd(__m512d a, __mmask8 k, __m512d b, __m512d c);\r\nVFMADDSUBxxxPD __m512d _mm512_maskz_fmaddsub_pd(__mmask8 k, __m512d a, __m512d b, __m512d c);\r\nVFMADDSUBxxxPD __m512d _mm512_mask3_fmaddsub_pd(__m512d a, __m512d b, __m512d c, __mmask8 k);\r\nVFMADDSUBxxxPD __m512d _mm512_mask_fmaddsub_round_pd(__m512d a, __mmask8 k, __m512d b, __m512d c, int r);\r\nVFMADDSUBxxxPD __m512d _mm512_maskz_fmaddsub_round_pd(__mmask8 k, __m512d a, __m512d b, __m512d c, int r);\r\nVFMADDSUBxxxPD __m512d _mm512_mask3_fmaddsub_round_pd(__m512d a, __m512d b, __m512d c, __mmask8 k, int r);\r\nVFMADDSUBxxxPD __m256d _mm256_mask_fmaddsub_pd(__m256d a, __mmask8 k, __m256d b, __m256d c);\r\nVFMADDSUBxxxPD __m256d _mm256_maskz_fmaddsub_pd(__mmask8 k, __m256d a, __m256d b, __m256d c);\r\nVFMADDSUBxxxPD __m256d _mm256_mask3_fmaddsub_pd(__m256d a, __m256d b, __m256d c, __mmask8 k);\r\nVFMADDSUBxxxPD __m128d _mm_mask_fmaddsub_pd(__m128d a, __mmask8 k, __m128d b, __m128d c);\r\nVFMADDSUBxxxPD __m128d _mm_maskz_fmaddsub_pd(__mmask8 k, __m128d a, __m128d b, __m128d c);\r\nVFMADDSUBxxxPD __m128d _mm_mask3_fmaddsub_pd(__m128d a, __m128d b, __m128d c, __mmask8 k);\r\nVFMADDSUBxxxPD __m128d _mm_fmaddsub_pd (__m128d a, __m128d b, __m128d c);\r\nVFMADDSUBxxxPD __m256d _mm256_fmaddsub_pd (__m256d a, __m256d b, __m256d c);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2.\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VFMADDSUB132PD"
},
{
"description": "VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS-Fused Multiply-Alternating\r\nAdd/Subtract of Packed Single-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.DDS.128.66.0F38.W0 96 /r RVM V/V FMA Multiply packed single-precision floating-point values from\r\n VFMADDSUB132PS xmm1, xmm2, xmm1 and xmm3/mem, add/subtract elements in xmm2\r\n xmm3/m128 and put result in xmm1.\r\n VEX.DDS.128.66.0F38.W0 A6 /r RVM V/V FMA Multiply packed single-precision floating-point values from\r\n VFMADDSUB213PS xmm1, xmm2, xmm1 and xmm2, add/subtract elements in xmm3/mem\r\n xmm3/m128 and put result in xmm1.\r\n VEX.DDS.128.66.0F38.W0 B6 /r RVM V/V FMA Multiply packed single-precision floating-point values from\r\n VFMADDSUB231PS xmm1, xmm2, xmm2 and xmm3/mem, add/subtract elements in xmm1\r\n xmm3/m128 and put result in xmm1.\r\n VEX.DDS.256.66.0F38.W0 96 /r RVM V/V FMA Multiply packed single-precision floating-point values from\r\n VFMADDSUB132PS ymm1, ymm2, ymm1 and ymm3/mem, add/subtract elements in ymm2\r\n ymm3/m256 and put result in ymm1.\r\n VEX.DDS.256.66.0F38.W0 A6 /r RVM V/V FMA Multiply packed single-precision floating-point values from\r\n VFMADDSUB213PS ymm1, ymm2, ymm1 and ymm2, add/subtract elements in ymm3/mem\r\n ymm3/m256 and put result in ymm1.\r\n VEX.DDS.256.66.0F38.W0 B6 /r RVM V/V FMA Multiply packed single-precision floating-point values from\r\n VFMADDSUB231PS ymm1, ymm2, ymm2 and ymm3/mem, add/subtract elements in ymm1\r\n ymm3/m256 and put result in ymm1.\r\n EVEX.DDS.128.66.0F38.W0 A6 /r FV V/V AVX512VL Multiply packed single-precision floating-point values from\r\n VFMADDSUB213PS xmm1 {k1}{z}, AVX512F xmm1 and xmm2, add/subtract elements in\r\n xmm2, xmm3/m128/m32bcst xmm3/m128/m32bcst and put result in xmm1 subject to\r\n writemask k1.\r\n EVEX.DDS.128.66.0F38.W0 B6 /r FV V/V AVX512VL Multiply packed single-precision floating-point values from\r\n VFMADDSUB231PS xmm1 {k1}{z}, AVX512F xmm2 and xmm3/m128/m32bcst, add/subtract elements\r\n xmm2, xmm3/m128/m32bcst in xmm1 and put result in xmm1 subject to writemask k1.\r\n EVEX.DDS.128.66.0F38.W0 96 /r FV V/V AVX512VL Multiply packed single-precision floating-point values from\r\n VFMADDSUB132PS xmm1 {k1}{z}, AVX512F xmm1 and xmm3/m128/m32bcst, add/subtract elements\r\n xmm2, xmm3/m128/m32bcst in zmm2 and put result in xmm1 subject to writemask k1.\r\n EVEX.DDS.256.66.0F38.W0 A6 /r FV V/V AVX512VL Multiply packed single-precision floating-point values from\r\n VFMADDSUB213PS ymm1 {k1}{z}, AVX512F ymm1 and ymm2, add/subtract elements in\r\n ymm2, ymm3/m256/m32bcst ymm3/m256/m32bcst and put result in ymm1 subject to\r\n writemask k1.\r\n EVEX.DDS.256.66.0F38.W0 B6 /r FV V/V AVX512VL Multiply packed single-precision floating-point values from\r\n VFMADDSUB231PS ymm1 {k1}{z}, AVX512F ymm2 and ymm3/m256/m32bcst, add/subtract elements\r\n ymm2, ymm3/m256/m32bcst in ymm1 and put result in ymm1 subject to writemask k1.\r\n EVEX.DDS.256.66.0F38.W0 96 /r FV V/V AVX512VL Multiply packed single-precision floating-point values from\r\n VFMADDSUB132PS ymm1 {k1}{z}, AVX512F ymm1 and ymm3/m256/m32bcst, add/subtract elements\r\n ymm2, ymm3/m256/m32bcst in ymm2 and put result in ymm1 subject to writemask k1.\r\n EVEX.DDS.512.66.0F38.W0 A6 /r FV V/V AVX512F Multiply packed single-precision floating-point values from\r\n VFMADDSUB213PS zmm1 {k1}{z}, zmm1 and zmm2, add/subtract elements in\r\n zmm2, zmm3/m512/m32bcst{er} zmm3/m512/m32bcst and put result in zmm1 subject to\r\n writemask k1.\r\n EVEX.DDS.512.66.0F38.W0 B6 /r FV V/V AVX512F Multiply packed single-precision floating-point values from\r\n VFMADDSUB231PS zmm1 {k1}{z}, zmm2 and zmm3/m512/m32bcst, add/subtract elements\r\n zmm2, zmm3/m512/m32bcst{er} in zmm1 and put result in zmm1 subject to writemask k1.\r\n EVEX.DDS.512.66.0F38.W0 96 /r FV V/V AVX512F Multiply packed single-precision floating-point values from\r\n VFMADDSUB132PS zmm1 {k1}{z}, zmm1 and zmm3/m512/m32bcst, add/subtract elements\r\n zmm2, zmm3/m512/m32bcst{er} in zmm2 and put result in zmm1 subject to writemask k1.\r\n\r\n\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nVFMADDSUB132PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the first\r\nsource operand to the corresponding packed single-precision floating-point values in the third source operand.\r\nFrom the infinite precision intermediate result, adds the odd single-precision floating-point elements and subtracts\r\nthe even single-precision floating-point values in the second source operand, performs rounding and stores the\r\nresulting packed single-precision floating-point values to the destination operand (first source operand).\r\nVFMADDSUB213PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the\r\nsecond source operand to the corresponding packed single-precision floating-point values in the first source\r\noperand. From the infinite precision intermediate result, adds the odd single-precision floating-point elements and\r\nsubtracts the even single-precision floating-point values in the third source operand, performs rounding and stores\r\nthe resulting packed single-precision floating-point values to the destination operand (first source operand).\r\nVFMADDSUB231PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the\r\nsecond source operand to the corresponding packed single-precision floating-point values in the third source\r\noperand. From the infinite precision intermediate result, adds the odd single-precision floating-point elements and\r\nsubtracts the even single-precision floating-point values in the first source operand, performs rounding and stores\r\nthe resulting packed single-precision floating-point values to the destination operand (first source operand).\r\nEVEX encoded versions: The destination operand (also first source operand) and the second source operand are\r\nZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-\r\ntion or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is condition-\r\nally updated with write mask k1.\r\nVEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in\r\nreg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a\r\nYMM register or a 256-bit memory location and encoded in rm_field.\r\nVEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in\r\nreg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a\r\nXMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination\r\nregister are zeroed.\r\nCompiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the\r\nopcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations\r\ninvolving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction\r\ncolumn.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIn the operations below, \"*\" and \"+\" symbols represent multiplication and addition with infinite precision inputs and outputs (no\r\nrounding).\r\n\r\nVFMADDSUB132PS DEST, SRC2, SRC3\r\nIF (VEX.128) THEN\r\n MAXNUM <-2\r\nELSEIF (VEX.256)\r\n MAXNUM <- 4\r\nFI\r\nFor i = 0 to MAXNUM -1{\r\n n <- 64*i;\r\n DEST[n+31:n] <-RoundFPControl_MXCSR(DEST[n+31:n]*SRC3[n+31:n] - SRC2[n+31:n])\r\n DEST[n+63:n+32] <-RoundFPControl_MXCSR(DEST[n+63:n+32]*SRC3[n+63:n+32] + SRC2[n+63:n+32])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <-0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\nVFMADDSUB213PS DEST, SRC2, SRC3\r\nIF (VEX.128) THEN\r\n MAXNUM <-2\r\nELSEIF (VEX.256)\r\n MAXNUM <- 4\r\nFI\r\nFor i = 0 to MAXNUM -1{\r\n n <- 64*i;\r\n DEST[n+31:n] <-RoundFPControl_MXCSR(SRC2[n+31:n]*DEST[n+31:n] - SRC3[n+31:n])\r\n DEST[n+63:n+32] <-RoundFPControl_MXCSR(SRC2[n+63:n+32]*DEST[n+63:n+32] + SRC3[n+63:n+32])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <-0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\n\r\n\r\n\r\n\r\nVFMADDSUB231PS DEST, SRC2, SRC3\r\nIF (VEX.128) THEN\r\n MAXNUM <-2\r\nELSEIF (VEX.256)\r\n MAXNUM <- 4\r\nFI\r\nFor i = 0 to MAXNUM -1{\r\n n <- 64*i;\r\n DEST[n+31:n] <-RoundFPControl_MXCSR(SRC2[n+31:n]*SRC3[n+31:n] - DEST[n+31:n])\r\n DEST[n+63:n+32] <-RoundFPControl_MXCSR(SRC2[n+63:n+32]*SRC3[n+63:n+32] + DEST[n+63:n+32])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <-0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\nVFMADDSUB132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) (4, 128), (8, 256),= (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF j *is even*\r\n THEN DEST[i+31:i] <-\r\n RoundFPControl(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i])\r\n ELSE DEST[i+31:i] <-\r\n RoundFPControl(DEST[i+31:i]*SRC3[i+31:i] + SRC2[i+31:i])\r\n FI\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMADDSUB132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF j *is even*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[31:0] - SRC2[i+31:i])\r\n ELSE\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i])\r\n FI;\r\n ELSE\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[31:0] + SRC2[i+31:i])\r\n ELSE\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] + SRC2[i+31:i])\r\n FI;\r\n FI\r\n\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMADDSUB213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF j *is even*\r\n THEN DEST[i+31:i] <-\r\n RoundFPControl(SRC2[i+31:i]*DEST[i+31:i] - SRC3[i+31:i])\r\n ELSE DEST[i+31:i] <-\r\n RoundFPControl(SRC2[i+31:i]*DEST[i+31:i] + SRC3[i+31:i])\r\n FI\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVFMADDSUB213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF j *is even*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[31:0])\r\n ELSE\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[i+31:i])\r\n FI;\r\n ELSE\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] + SRC3[31:0])\r\n ELSE\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] + SRC3[i+31:i])\r\n FI;\r\n\r\n\r\n\r\n FI\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVFMADDSUB231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF j *is even*\r\n THEN DEST[i+31:i] <-\r\n RoundFPControl(SRC2[i+31:i]*SRC3[i+31:i] - DEST[i+31:i])\r\n ELSE DEST[i+31:i] <-\r\n RoundFPControl(SRC2[i+31:i]*SRC3[i+31:i] + DEST[i+31:i])\r\n FI\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMADDSUB231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF j *is even*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[31:0] - DEST[i+31:i])\r\n ELSE\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] - DEST[i+31:i])\r\n FI;\r\n ELSE\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[31:0] + DEST[i+31:i])\r\n ELSE\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] + DEST[i+31:i])\r\n FI;\r\n FI\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVFMADDSUBxxxPS __m512 _mm512_fmaddsub_ps(__m512 a, __m512 b, __m512 c);\r\nVFMADDSUBxxxPS __m512 _mm512_fmaddsub_round_ps(__m512 a, __m512 b, __m512 c, int r);\r\nVFMADDSUBxxxPS __m512 _mm512_mask_fmaddsub_ps(__m512 a, __mmask16 k, __m512 b, __m512 c);\r\nVFMADDSUBxxxPS __m512 _mm512_maskz_fmaddsub_ps(__mmask16 k, __m512 a, __m512 b, __m512 c);\r\nVFMADDSUBxxxPS __m512 _mm512_mask3_fmaddsub_ps(__m512 a, __m512 b, __m512 c, __mmask16 k);\r\nVFMADDSUBxxxPS __m512 _mm512_mask_fmaddsub_round_ps(__m512 a, __mmask16 k, __m512 b, __m512 c, int r);\r\nVFMADDSUBxxxPS __m512 _mm512_maskz_fmaddsub_round_ps(__mmask16 k, __m512 a, __m512 b, __m512 c, int r);\r\nVFMADDSUBxxxPS __m512 _mm512_mask3_fmaddsub_round_ps(__m512 a, __m512 b, __m512 c, __mmask16 k, int r);\r\nVFMADDSUBxxxPS __m256 _mm256_mask_fmaddsub_ps(__m256 a, __mmask8 k, __m256 b, __m256 c);\r\nVFMADDSUBxxxPS __m256 _mm256_maskz_fmaddsub_ps(__mmask8 k, __m256 a, __m256 b, __m256 c);\r\nVFMADDSUBxxxPS __m256 _mm256_mask3_fmaddsub_ps(__m256 a, __m256 b, __m256 c, __mmask8 k);\r\nVFMADDSUBxxxPS __m128 _mm_mask_fmaddsub_ps(__m128 a, __mmask8 k, __m128 b, __m128 c);\r\nVFMADDSUBxxxPS __m128 _mm_maskz_fmaddsub_ps(__mmask8 k, __m128 a, __m128 b, __m128 c);\r\nVFMADDSUBxxxPS __m128 _mm_mask3_fmaddsub_ps(__m128 a, __m128 b, __m128 c, __mmask8 k);\r\nVFMADDSUBxxxPS __m128 _mm_fmaddsub_ps (__m128 a, __m128 b, __m128 c);\r\nVFMADDSUBxxxPS __m256 _mm256_fmaddsub_ps (__m256 a, __m256 b, __m256 c);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2.\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VFMADDSUB132PS"
},
{
"description": "-R:VFMADDSUB132PD",
"mnem": "VFMADDSUB213PD"
},
{
"description": "-R:VFMADDSUB132PS",
"mnem": "VFMADDSUB213PS"
},
{
"description": "-R:VFMADDSUB132PD",
"mnem": "VFMADDSUB231PD"
},
{
"description": "-R:VFMADDSUB132PS",
"mnem": "VFMADDSUB231PS"
},
{
"description": "VFMSUB132PD/VFMSUB213PD/VFMSUB231PD-Fused Multiply-Subtract of Packed Double-\r\nPrecision Floating-Point Values\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.NDS.128.66.0F38.W1 9A /r RVM V/V FMA Multiply packed double-precision floating-point values\r\n VFMSUB132PD xmm1, xmm2, from xmm1 and xmm3/mem, subtract xmm2 and put\r\n xmm3/m128 result in xmm1.\r\n VEX.NDS.128.66.0F38.W1 AA /r RVM V/V FMA Multiply packed double-precision floating-point values\r\n VFMSUB213PD xmm1, xmm2, from xmm1 and xmm2, subtract xmm3/mem and put\r\n xmm3/m128 result in xmm1.\r\n VEX.NDS.128.66.0F38.W1 BA /r RVM V/V FMA Multiply packed double-precision floating-point values\r\n VFMSUB231PD xmm1, xmm2, from xmm2 and xmm3/mem, subtract xmm1 and put\r\n xmm3/m128 result in xmm1.\r\n VEX.NDS.256.66.0F38.W1 9A /r RVM V/V FMA Multiply packed double-precision floating-point values\r\n VFMSUB132PD ymm1, ymm2, from ymm1 and ymm3/mem, subtract ymm2 and put\r\n ymm3/m256 result in ymm1.\r\n VEX.NDS.256.66.0F38.W1 AA /r RVM V/V FMA Multiply packed double-precision floating-point values\r\n VFMSUB213PD ymm1, ymm2, from ymm1 and ymm2, subtract ymm3/mem and put\r\n ymm3/m256 result in ymm1.\r\n VEX.NDS.256.66.0F38.W1 BA /r RVM V/V FMA Multiply packed double-precision floating-point values\r\n VFMSUB231PD ymm1, ymm2, from ymm2 and ymm3/mem, subtract ymm1 and put\r\n ymm3/m256 result in ymm1.S\r\n EVEX.NDS.128.66.0F38.W1 9A /r FV V/V AVX512VL Multiply packed double-precision floating-point values\r\n VFMSUB132PD xmm1 {k1}{z}, AVX512F from xmm1 and xmm3/m128/m64bcst, subtract xmm2\r\n xmm2, xmm3/m128/m64bcst and put result in xmm1 subject to writemask k1.\r\n EVEX.NDS.128.66.0F38.W1 AA /r FV V/V AVX512VL Multiply packed double-precision floating-point values\r\n VFMSUB213PD xmm1 {k1}{z}, AVX512F from xmm1 and xmm2, subtract xmm3/m128/m64bcst\r\n xmm2, xmm3/m128/m64bcst and put result in xmm1 subject to writemask k1.\r\n EVEX.NDS.128.66.0F38.W1 BA /r FV V/V AVX512VL Multiply packed double-precision floating-point values\r\n VFMSUB231PD xmm1 {k1}{z}, AVX512F from xmm2 and xmm3/m128/m64bcst, subtract xmm1\r\n xmm2, xmm3/m128/m64bcst and put result in xmm1 subject to writemask k1.\r\n EVEX.NDS.256.66.0F38.W1 9A /r FV V/V AVX512VL Multiply packed double-precision floating-point values\r\n VFMSUB132PD ymm1 {k1}{z}, AVX512F from ymm1 and ymm3/m256/m64bcst, subtract ymm2\r\n ymm2, ymm3/m256/m64bcst and put result in ymm1 subject to writemask k1.\r\n EVEX.NDS.256.66.0F38.W1 AA /r FV V/V AVX512VL Multiply packed double-precision floating-point values\r\n VFMSUB213PD ymm1 {k1}{z}, AVX512F from ymm1 and ymm2, subtract ymm3/m256/m64bcst\r\n ymm2, ymm3/m256/m64bcst and put result in ymm1 subject to writemask k1.\r\n EVEX.NDS.256.66.0F38.W1 BA /r FV V/V AVX512VL Multiply packed double-precision floating-point values\r\n VFMSUB231PD ymm1 {k1}{z}, AVX512F from ymm2 and ymm3/m256/m64bcst, subtract ymm1\r\n ymm2, ymm3/m256/m64bcst and put result in ymm1 subject to writemask k1.\r\n EVEX.NDS.512.66.0F38.W1 9A /r FV V/V AVX512F Multiply packed double-precision floating-point values\r\n VFMSUB132PD zmm1 {k1}{z}, from zmm1 and zmm3/m512/m64bcst, subtract zmm2\r\n zmm2, zmm3/m512/m64bcst{er} and put result in zmm1 subject to writemask k1.\r\n EVEX.NDS.512.66.0F38.W1 AA /r FV V/V AVX512F Multiply packed double-precision floating-point values\r\n VFMSUB213PD zmm1 {k1}{z}, from zmm1 and zmm2, subtract zmm3/m512/m64bcst\r\n zmm2, zmm3/m512/m64bcst{er} and put result in zmm1 subject to writemask k1.\r\n EVEX.NDS.512.66.0F38.W1 BA /r FV V/V AVX512F Multiply packed double-precision floating-point values\r\n VFMSUB231PD zmm1 {k1}{z}, from zmm2 and zmm3/m512/m64bcst, subtract zmm1\r\n zmm2, zmm3/m512/m64bcst{er} and put result in zmm1 subject to writemask k1.\r\n\r\n\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a set of SIMD multiply-subtract computation on packed double-precision floating-point values using three\r\nsource operands and writes the multiply-subtract results in the destination operand. The destination operand is\r\nalso the first source operand. The second operand must be a SIMD register. The third source operand can be a\r\nSIMD register or a memory location.\r\nVFMSUB132PD: Multiplies the two, four or eight packed double-precision floating-point values from the first source\r\noperand to the two, four or eight packed double-precision floating-point values in the third source operand. From\r\nthe infinite precision intermediate result, subtracts the two, four or eight packed double-precision floating-point\r\nvalues in the second source operand, performs rounding and stores the resulting two, four or eight packed double-\r\nprecision floating-point values to the destination operand (first source operand).\r\nVFMSUB213PD: Multiplies the two, four or eight packed double-precision floating-point values from the second\r\nsource operand to the two, four or eight packed double-precision floating-point values in the first source operand.\r\nFrom the infinite precision intermediate result, subtracts the two, four or eight packed double-precision floating-\r\npoint values in the third source operand, performs rounding and stores the resulting two, four or eight packed\r\ndouble-precision floating-point values to the destination operand (first source operand).\r\nVFMSUB231PD: Multiplies the two, four or eight packed double-precision floating-point values from the second\r\nsource to the two, four or eight packed double-precision floating-point values in the third source operand. From the\r\ninfinite precision intermediate result, subtracts the two, four or eight packed double-precision floating-point values\r\nin the first source operand, performs rounding and stores the resulting two, four or eight packed double-precision\r\nfloating-point values to the destination operand (first source operand).\r\nEVEX encoded versions: The destination operand (also first source operand) and the second source operand are\r\nZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-\r\ntion or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is condition-\r\nally updated with write mask k1.\r\nVEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in\r\nreg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a\r\nYMM register or a 256-bit memory location and encoded in rm_field.\r\nVEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in\r\nreg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a\r\nXMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination\r\nregister are zeroed.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIn the operations below, \"*\" and \"-\" symbols represent multiplication and subtraction with infinite precision inputs and outputs (no\r\nrounding).\r\n\r\nVFMSUB132PD DEST, SRC2, SRC3 (VEX encoded versions)\r\nIF (VEX.128) THEN\r\n MAXNUM <-2\r\nELSEIF (VEX.256)\r\n MAXNUM <- 4\r\nFI\r\nFor i = 0 to MAXNUM-1 {\r\n n <- 64*i;\r\n DEST[n+63:n] <- RoundFPControl_MXCSR(DEST[n+63:n]*SRC3[n+63:n] - SRC2[n+63:n])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <- 0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\nVFMSUB213PD DEST, SRC2, SRC3 (VEX encoded versions)\r\nIF (VEX.128) THEN\r\n MAXNUM <-2\r\nELSEIF (VEX.256)\r\n MAXNUM <- 4\r\nFI\r\nFor i = 0 to MAXNUM-1 {\r\n n <- 64*i;\r\n DEST[n+63:n] <- RoundFPControl_MXCSR(SRC2[n+63:n]*DEST[n+63:n] - SRC3[n+63:n])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <- 0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\nVFMSUB231PD DEST, SRC2, SRC3 (VEX encoded versions)\r\nIF (VEX.128) THEN\r\n MAXNUM <-2\r\nELSEIF (VEX.256)\r\n MAXNUM <- 4\r\nFI\r\nFor i = 0 to MAXNUM-1 {\r\n n <- 64*i;\r\n DEST[n+63:n] <- RoundFPControl_MXCSR(SRC2[n+63:n]*SRC3[n+63:n] - DEST[n+63:n])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <- 0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\n\r\n\r\n\r\n\r\nVFMSUB132PD DEST, SRC2, SRC3 (EVEX encoded versions, when src3 operand is a register)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <-\r\n RoundFPControl(DEST[i+63:i]*SRC3[i+63:i] - SRC2[i+63:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVFMSUB132PD DEST, SRC2, SRC3 (EVEX encoded versions, when src3 operand is a memory source)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[63:0] - SRC2[i+63:i])\r\n ELSE\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] - SRC2[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMSUB213PD DEST, SRC2, SRC3 (EVEX encoded versions, when src3 operand is a register)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <-\r\n RoundFPControl(SRC2[i+63:i]*DEST[i+63:i] - SRC3[i+63:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMSUB213PD DEST, SRC2, SRC3 (EVEX encoded versions, when src3 operand is a memory source)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] - SRC3[63:0])\r\n+31:i])\r\n ELSE\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] - SRC3[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVFMSUB231PD DEST, SRC2, SRC3 (EVEX encoded versions, when src3 operand is a register)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <-\r\n RoundFPControl(SRC2[i+63:i]*SRC3[i+63:i] - DEST[i+63:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMSUB231PD DEST, SRC2, SRC3 (EVEX encoded versions, when src3 operand is a memory source)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[63:0] - DEST[i+63:i])\r\n ELSE\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[i+63:i] - DEST[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVFMSUBxxxPD __m512d _mm512_fmsub_pd(__m512d a, __m512d b, __m512d c);\r\nVFMSUBxxxPD __m512d _mm512_fmsub_round_pd(__m512d a, __m512d b, __m512d c, int r);\r\nVFMSUBxxxPD __m512d _mm512_mask_fmsub_pd(__m512d a, __mmask8 k, __m512d b, __m512d c);\r\nVFMSUBxxxPD __m512d _mm512_maskz_fmsub_pd(__mmask8 k, __m512d a, __m512d b, __m512d c);\r\nVFMSUBxxxPD __m512d _mm512_mask3_fmsub_pd(__m512d a, __m512d b, __m512d c, __mmask8 k);\r\nVFMSUBxxxPD __m512d _mm512_mask_fmsub_round_pd(__m512d a, __mmask8 k, __m512d b, __m512d c, int r);\r\nVFMSUBxxxPD __m512d _mm512_maskz_fmsub_round_pd(__mmask8 k, __m512d a, __m512d b, __m512d c, int r);\r\nVFMSUBxxxPD __m512d _mm512_mask3_fmsub_round_pd(__m512d a, __m512d b, __m512d c, __mmask8 k, int r);\r\nVFMSUBxxxPD __m256d _mm256_mask_fmsub_pd(__m256d a, __mmask8 k, __m256d b, __m256d c);\r\nVFMSUBxxxPD __m256d _mm256_maskz_fmsub_pd(__mmask8 k, __m256d a, __m256d b, __m256d c);\r\nVFMSUBxxxPD __m256d _mm256_mask3_fmsub_pd(__m256d a, __m256d b, __m256d c, __mmask8 k);\r\nVFMSUBxxxPD __m128d _mm_mask_fmsub_pd(__m128d a, __mmask8 k, __m128d b, __m128d c);\r\nVFMSUBxxxPD __m128d _mm_maskz_fmsub_pd(__mmask8 k, __m128d a, __m128d b, __m128d c);\r\nVFMSUBxxxPD __m128d _mm_mask3_fmsub_pd(__m128d a, __m128d b, __m128d c, __mmask8 k);\r\nVFMSUBxxxPD __m128d _mm_fmsub_pd (__m128d a, __m128d b, __m128d c);\r\nVFMSUBxxxPD __m256d _mm256_fmsub_pd (__m256d a, __m256d b, __m256d c);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2.\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VFMSUB132PD"
},
{
"description": "VFMSUB132PS/VFMSUB213PS/VFMSUB231PS-Fused Multiply-Subtract of Packed Single-\r\nPrecision Floating-Point Values\r\n Opcode/ Op/E 64/32 CPUID Description\r\n Instruction n bit Mode Feature\r\n Support Flag\r\n VEX.NDS.128.66.0F38.W0 9A /r RVM V/V FMA Multiply packed single-precision floating-point values\r\n VFMSUB132PS xmm1, xmm2, from xmm1 and xmm3/mem, subtract xmm2 and put\r\n xmm3/m128 result in xmm1.\r\n VEX.NDS.128.66.0F38.W0 AA /r RVM V/V FMA Multiply packed single-precision floating-point values\r\n VFMSUB213PS xmm1, xmm2, from xmm1 and xmm2, subtract xmm3/mem and put\r\n xmm3/m128 result in xmm1.\r\n VEX.NDS.128.66.0F38.W0 BA /r RVM V/V FMA Multiply packed single-precision floating-point values\r\n VFMSUB231PS xmm1, xmm2, from xmm2 and xmm3/mem, subtract xmm1 and put\r\n xmm3/m128 result in xmm1.\r\n VEX.NDS.256.66.0F38.W0 9A /r RVM V/V FMA Multiply packed single-precision floating-point values\r\n VFMSUB132PS ymm1, ymm2, from ymm1 and ymm3/mem, subtract ymm2 and put\r\n ymm3/m256 result in ymm1.\r\n VEX.NDS.256.66.0F38.W0 AA /r RVM V/V FMA Multiply packed single-precision floating-point values\r\n VFMSUB213PS ymm1, ymm2, from ymm1 and ymm2, subtract ymm3/mem and put\r\n ymm3/m256 result in ymm1.\r\n VEX.NDS.256.66.0F38.0 BA /r RVM V/V FMA Multiply packed single-precision floating-point values\r\n VFMSUB231PS ymm1, ymm2, from ymm2 and ymm3/mem, subtract ymm1 and put\r\n ymm3/m256 result in ymm1.\r\n EVEX.NDS.128.66.0F38.W0 9A /r FV V/V AVX512VL Multiply packed single-precision floating-point values\r\n VFMSUB132PS xmm1 {k1}{z}, AVX512F from xmm1 and xmm3/m128/m32bcst, subtract\r\n xmm2, xmm3/m128/m32bcst xmm2 and put result in xmm1.\r\n EVEX.NDS.128.66.0F38.W0 AA /r FV V/V AVX512VL Multiply packed single-precision floating-point values\r\n VFMSUB213PS xmm1 {k1}{z}, AVX512F from xmm1 and xmm2, subtract\r\n xmm2, xmm3/m128/m32bcst xmm3/m128/m32bcst and put result in xmm1.\r\n EVEX.NDS.128.66.0F38.W0 BA /r FV V/V AVX512VL Multiply packed single-precision floating-point values\r\n VFMSUB231PS xmm1 {k1}{z}, AVX512F from xmm2 and xmm3/m128/m32bcst, subtract\r\n xmm2, xmm3/m128/m32bcst xmm1 and put result in xmm1.\r\n EVEX.NDS.256.66.0F38.W0 9A /r FV V/V AVX512VL Multiply packed single-precision floating-point values\r\n VFMSUB132PS ymm1 {k1}{z}, AVX512F from ymm1 and ymm3/m256/m32bcst, subtract\r\n ymm2, ymm3/m256/m32bcst ymm2 and put result in ymm1.\r\n EVEX.NDS.256.66.0F38.W0 AA /r FV V/V AVX512VL Multiply packed single-precision floating-point values\r\n VFMSUB213PS ymm1 {k1}{z}, AVX512F from ymm1 and ymm2, subtract\r\n ymm2, ymm3/m256/m32bcst ymm3/m256/m32bcst and put result in ymm1.\r\n EVEX.NDS.256.66.0F38.W0 BA /r FV V/V AVX512VL Multiply packed single-precision floating-point values\r\n VFMSUB231PS ymm1 {k1}{z}, AVX512F from ymm2 and ymm3/m256/m32bcst, subtract\r\n ymm2, ymm3/m256/m32bcst ymm1 and put result in ymm1.\r\n EVEX.NDS.512.66.0F38.W0 9A /r FV V/V AVX512F Multiply packed single-precision floating-point values\r\n VFMSUB132PS zmm1 {k1}{z}, from zmm1 and zmm3/m512/m32bcst, subtract zmm2\r\n zmm2, zmm3/m512/m32bcst{er} and put result in zmm1.\r\n EVEX.NDS.512.66.0F38.W0 AA /r FV V/V AVX512F Multiply packed single-precision floating-point values\r\n VFMSUB213PS zmm1 {k1}{z}, from zmm1 and zmm2, subtract zmm3/m512/m32bcst\r\n zmm2, zmm3/m512/m32bcst{er} and put result in zmm1.\r\n EVEX.NDS.512.66.0F38.W0 BA /r FV V/V AVX512F Multiply packed single-precision floating-point values\r\n VFMSUB231PS zmm1 {k1}{z}, from zmm2 and zmm3/m512/m32bcst, subtract zmm1\r\n zmm2, zmm3/m512/m32bcst{er} and put result in zmm1.\r\n\r\n\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a set of SIMD multiply-subtract computation on packed single-precision floating-point values using three\r\nsource operands and writes the multiply-subtract results in the destination operand. The destination operand is\r\nalso the first source operand. The second operand must be a SIMD register. The third source operand can be a\r\nSIMD register or a memory location.\r\nVFMSUB132PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the first\r\nsource operand to the four, eight or sixteen packed single-precision floating-point values in the third source\r\noperand. From the infinite precision intermediate result, subtracts the four, eight or sixteen packed single-precision\r\nfloating-point values in the second source operand, performs rounding and stores the resulting four, eight or\r\nsixteen packed single-precision floating-point values to the destination operand (first source operand).\r\nVFMSUB213PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second\r\nsource operand to the four, eight or sixteen packed single-precision floating-point values in the first source\r\noperand. From the infinite precision intermediate result, subtracts the four, eight or sixteen packed single-precision\r\nfloating-point values in the third source operand, performs rounding and stores the resulting four, eight or sixteen\r\npacked single-precision floating-point values to the destination operand (first source operand).\r\nVFMSUB231PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second\r\nsource to the four, eight or sixteen packed single-precision floating-point values in the third source operand. From\r\nthe infinite precision intermediate result, subtracts the four, eight or sixteen packed single-precision floating-point\r\nvalues in the first source operand, performs rounding and stores the resulting four, eight or sixteen packed single-\r\nprecision floating-point values to the destination operand (first source operand).\r\nEVEX encoded versions: The destination operand (also first source operand) and the second source operand are\r\nZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-\r\ntion or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is condition-\r\nally updated with write mask k1.\r\nVEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in\r\nreg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a\r\nYMM register or a 256-bit memory location and encoded in rm_field.\r\nVEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in\r\nreg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a\r\nXMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination\r\nregister are zeroed.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIn the operations below, \"*\" and \"-\" symbols represent multiplication and subtraction with infinite precision inputs and outputs (no\r\nrounding).\r\n\r\nVFMSUB132PS DEST, SRC2, SRC3 (VEX encoded version)\r\nIF (VEX.128) THEN\r\n MAXNUM <-2\r\nELSEIF (VEX.256)\r\n MAXNUM <- 4\r\nFI\r\nFor i = 0 to MAXNUM-1 {\r\n n <- 32*i;\r\n DEST[n+31:n] <- RoundFPControl_MXCSR(DEST[n+31:n]*SRC3[n+31:n] - SRC2[n+31:n])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <- 0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\nVFMSUB213PS DEST, SRC2, SRC3 (VEX encoded version)\r\nIF (VEX.128) THEN\r\n MAXNUM <-2\r\nELSEIF (VEX.256)\r\n MAXNUM <- 4\r\nFI\r\nFor i = 0 to MAXNUM-1 {\r\n n <- 32*i;\r\n DEST[n+31:n] <- RoundFPControl_MXCSR(SRC2[n+31:n]*DEST[n+31:n] - SRC3[n+31:n])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <- 0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\nVFMSUB231PS DEST, SRC2, SRC3 (VEX encoded version)\r\nIF (VEX.128) THEN\r\n MAXNUM <-2\r\nELSEIF (VEX.256)\r\n MAXNUM <- 4\r\nFI\r\nFor i = 0 to MAXNUM-1 {\r\n n <- 32*i;\r\n DEST[n+31:n] <- RoundFPControl_MXCSR(SRC2[n+31:n]*SRC3[n+31:n] - DEST[n+31:n])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <- 0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\n\r\n\r\n\r\n\r\nVFMSUB132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <-\r\n RoundFPControl(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVFMSUB132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[31:0] - SRC2[i+31:i])\r\n ELSE\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMSUB213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[i+31:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMSUB213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[31:0])\r\n ELSE\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[i+31:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVFMSUB231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] - DEST[i+31:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMSUB231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[31:0] - DEST[i+31:i])\r\n ELSE\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] - DEST[i+31:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVFMSUBxxxPS __m512 _mm512_fmsub_ps(__m512 a, __m512 b, __m512 c);\r\nVFMSUBxxxPS __m512 _mm512_fmsub_round_ps(__m512 a, __m512 b, __m512 c, int r);\r\nVFMSUBxxxPS __m512 _mm512_mask_fmsub_ps(__m512 a, __mmask16 k, __m512 b, __m512 c);\r\nVFMSUBxxxPS __m512 _mm512_maskz_fmsub_ps(__mmask16 k, __m512 a, __m512 b, __m512 c);\r\nVFMSUBxxxPS __m512 _mm512_mask3_fmsub_ps(__m512 a, __m512 b, __m512 c, __mmask16 k);\r\nVFMSUBxxxPS __m512 _mm512_mask_fmsub_round_ps(__m512 a, __mmask16 k, __m512 b, __m512 c, int r);\r\nVFMSUBxxxPS __m512 _mm512_maskz_fmsub_round_ps(__mmask16 k, __m512 a, __m512 b, __m512 c, int r);\r\nVFMSUBxxxPS __m512 _mm512_mask3_fmsub_round_ps(__m512 a, __m512 b, __m512 c, __mmask16 k, int r);\r\nVFMSUBxxxPS __m256 _mm256_mask_fmsub_ps(__m256 a, __mmask8 k, __m256 b, __m256 c);\r\nVFMSUBxxxPS __m256 _mm256_maskz_fmsub_ps(__mmask8 k, __m256 a, __m256 b, __m256 c);\r\nVFMSUBxxxPS __m256 _mm256_mask3_fmsub_ps(__m256 a, __m256 b, __m256 c, __mmask8 k);\r\nVFMSUBxxxPS __m128 _mm_mask_fmsub_ps(__m128 a, __mmask8 k, __m128 b, __m128 c);\r\nVFMSUBxxxPS __m128 _mm_maskz_fmsub_ps(__mmask8 k, __m128 a, __m128 b, __m128 c);\r\nVFMSUBxxxPS __m128 _mm_mask3_fmsub_ps(__m128 a, __m128 b, __m128 c, __mmask8 k);\r\nVFMSUBxxxPS __m128 _mm_fmsub_ps (__m128 a, __m128 b, __m128 c);\r\nVFMSUBxxxPS __m256 _mm256_fmsub_ps (__m256 a, __m256 b, __m256 c);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2.\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VFMSUB132PS"
},
{
"description": "VFMSUB132SD/VFMSUB213SD/VFMSUB231SD-Fused Multiply-Subtract of Scalar Double-\r\nPrecision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.DDS.LIG.66.0F38.W1 9B /r RVM V/V FMA Multiply scalar double-precision floating-point value from\r\n VFMSUB132SD xmm1, xmm2, xmm1 and xmm3/m64, subtract xmm2 and put result in\r\n xmm3/m64 xmm1.\r\n VEX.DDS.LIG.66.0F38.W1 AB /r RVM V/V FMA Multiply scalar double-precision floating-point value from\r\n VFMSUB213SD xmm1, xmm2, xmm1 and xmm2, subtract xmm3/m64 and put result in\r\n xmm3/m64 xmm1.\r\n VEX.DDS.LIG.66.0F38.W1 BB /r RVM V/V FMA Multiply scalar double-precision floating-point value from\r\n VFMSUB231SD xmm1, xmm2, xmm2 and xmm3/m64, subtract xmm1 and put result in\r\n xmm3/m64 xmm1.\r\n EVEX.DDS.LIG.66.0F38.W1 9B /r T1S V/V AVX512F Multiply scalar double-precision floating-point value from\r\n VFMSUB132SD xmm1 {k1}{z}, xmm1 and xmm3/m64, subtract xmm2 and put result in\r\n xmm2, xmm3/m64{er} xmm1.\r\n EVEX.DDS.LIG.66.0F38.W1 AB /r T1S V/V AVX512F Multiply scalar double-precision floating-point value from\r\n VFMSUB213SD xmm1 {k1}{z}, xmm1 and xmm2, subtract xmm3/m64 and put result in\r\n xmm2, xmm3/m64{er} xmm1.\r\n EVEX.DDS.LIG.66.0F38.W1 BB /r T1S V/V AVX512F Multiply scalar double-precision floating-point value from\r\n VFMSUB231SD xmm1 {k1}{z}, xmm2 and xmm3/m64, subtract xmm1 and put result in\r\n xmm2, xmm3/m64{er} xmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n T1S ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a SIMD multiply-subtract computation on the low packed double-precision floating-point values using\r\nthree source operands and writes the multiply-subtract result in the destination operand. The destination operand\r\nis also the first source operand. The second operand must be a XMM register. The third source operand can be a\r\nXMM register or a 64-bit memory location.\r\nVFMSUB132SD: Multiplies the low packed double-precision floating-point value from the first source operand to\r\nthe low packed double-precision floating-point value in the third source operand. From the infinite precision inter-\r\nmediate result, subtracts the low packed double-precision floating-point values in the second source operand,\r\nperforms rounding and stores the resulting packed double-precision floating-point value to the destination operand\r\n(first source operand).\r\nVFMSUB213SD: Multiplies the low packed double-precision floating-point value from the second source operand to\r\nthe low packed double-precision floating-point value in the first source operand. From the infinite precision inter-\r\nmediate result, subtracts the low packed double-precision floating-point value in the third source operand,\r\nperforms rounding and stores the resulting packed double-precision floating-point value to the destination operand\r\n(first source operand).\r\nVFMSUB231SD: Multiplies the low packed double-precision floating-point value from the second source to the low\r\npacked double-precision floating-point value in the third source operand. From the infinite precision intermediate\r\nresult, subtracts the low packed double-precision floating-point value in the first source operand, performs\r\nrounding and stores the resulting packed double-precision floating-point value to the destination operand (first\r\nsource operand).\r\nVEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field.\r\nThe second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field.\r\nBits 127:64 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.\r\n\r\n\r\n\r\n\r\nEVEX encoded version: The low quadword element of the destination is updated according to the writemask.\r\nCompiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the\r\nopcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations\r\ninvolving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction\r\ncolumn.\r\n\r\nOperation\r\nIn the operations below, \"*\" and \"-\" symbols represent multiplication and subtraction with infinite precision inputs and outputs (no\r\nrounding).\r\n\r\nVFMSUB132SD DEST, SRC2, SRC3 (EVEX encoded version)\r\nIF (EVEX.b = 1) and SRC3 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[63:0] <- RoundFPControl(DEST[63:0]*SRC3[63:0] - SRC2[63:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[63:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:64] <- DEST[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVFMSUB213SD DEST, SRC2, SRC3 (EVEX encoded version)\r\nIF (EVEX.b = 1) and SRC3 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[63:0] <- RoundFPControl(SRC2[63:0]*DEST[63:0] - SRC3[63:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[63:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:64] <- DEST[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMSUB231SD DEST, SRC2, SRC3 (EVEX encoded version)\r\nIF (EVEX.b = 1) and SRC3 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[63:0] <- RoundFPControl(SRC2[63:0]*SRC3[63:0] - DEST[63:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[63:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:64] <- DEST[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVFMSUB132SD DEST, SRC2, SRC3 (VEX encoded version)\r\nDEST[63:0] <-RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] - SRC2[63:0])\r\nDEST[127:64] <-DEST[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVFMSUB213SD DEST, SRC2, SRC3 (VEX encoded version)\r\nDEST[63:0] <-RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] - SRC3[63:0])\r\nDEST[127:64] <-DEST[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVFMSUB231SD DEST, SRC2, SRC3 (VEX encoded version)\r\nDEST[63:0] <-RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] - DEST[63:0])\r\nDEST[127:64] <-DEST[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVFMSUBxxxSD __m128d _mm_fmsub_round_sd(__m128d a, __m128d b, __m128d c, int r);\r\nVFMSUBxxxSD __m128d _mm_mask_fmsub_sd(__m128d a, __mmask8 k, __m128d b, __m128d c);\r\nVFMSUBxxxSD __m128d _mm_maskz_fmsub_sd(__mmask8 k, __m128d a, __m128d b, __m128d c);\r\nVFMSUBxxxSD __m128d _mm_mask3_fmsub_sd(__m128d a, __m128d b, __m128d c, __mmask8 k);\r\nVFMSUBxxxSD __m128d _mm_mask_fmsub_round_sd(__m128d a, __mmask8 k, __m128d b, __m128d c, int r);\r\nVFMSUBxxxSD __m128d _mm_maskz_fmsub_round_sd(__mmask8 k, __m128d a, __m128d b, __m128d c, int r);\r\nVFMSUBxxxSD __m128d _mm_mask3_fmsub_round_sd(__m128d a, __m128d b, __m128d c, __mmask8 k, int r);\r\nVFMSUBxxxSD __m128d _mm_fmsub_sd (__m128d a, __m128d b, __m128d c);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3.\r\nEVEX-encoded instructions, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VFMSUB132SD"
},
{
"description": "VFMSUB132SS/VFMSUB213SS/VFMSUB231SS-Fused Multiply-Subtract of Scalar Single-\r\nPrecision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.DDS.LIG.66.0F38.W0 9B /r RVM V/V FMA Multiply scalar single-precision floating-point value from\r\n VFMSUB132SS xmm1, xmm2, xmm1 and xmm3/m32, subtract xmm2 and put result in\r\n xmm3/m32 xmm1.\r\n VEX.DDS.LIG.66.0F38.W0 AB /r RVM V/V FMA Multiply scalar single-precision floating-point value from\r\n VFMSUB213SS xmm1, xmm2, xmm1 and xmm2, subtract xmm3/m32 and put result in\r\n xmm3/m32 xmm1.\r\n VEX.DDS.LIG.66.0F38.W0 BB /r RVM V/V FMA Multiply scalar single-precision floating-point value from\r\n VFMSUB231SS xmm1, xmm2, xmm2 and xmm3/m32, subtract xmm1 and put result in\r\n xmm3/m32 xmm1.\r\n EVEX.DDS.LIG.66.0F38.W0 9B /r T1S V/V AVX512F Multiply scalar single-precision floating-point value from\r\n VFMSUB132SS xmm1 {k1}{z}, xmm1 and xmm3/m32, subtract xmm2 and put result in\r\n xmm2, xmm3/m32{er} xmm1.\r\n EVEX.DDS.LIG.66.0F38.W0 AB /r T1S V/V AVX512F Multiply scalar single-precision floating-point value from\r\n VFMSUB213SS xmm1 {k1}{z}, xmm1 and xmm2, subtract xmm3/m32 and put result in\r\n xmm2, xmm3/m32{er} xmm1.\r\n EVEX.DDS.LIG.66.0F38.W0 BB /r T1S V/V AVX512F Multiply scalar single-precision floating-point value from\r\n VFMSUB231SS xmm1 {k1}{z}, xmm2 and xmm3/m32, subtract xmm1 and put result in\r\n xmm2, xmm3/m32{er} xmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n T1S ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a SIMD multiply-subtract computation on the low packed single-precision floating-point values using\r\nthree source operands and writes the multiply-subtract result in the destination operand. The destination operand\r\nis also the first source operand. The second operand must be a XMM register. The third source operand can be a\r\nXMM register or a 32-bit memory location.\r\nVFMSUB132SS: Multiplies the low packed single-precision floating-point value from the first source operand to the\r\nlow packed single-precision floating-point value in the third source operand. From the infinite precision interme-\r\ndiate result, subtracts the low packed single-precision floating-point values in the second source operand, performs\r\nrounding and stores the resulting packed single-precision floating-point value to the destination operand (first\r\nsource operand).\r\nVFMSUB213SS: Multiplies the low packed single-precision floating-point value from the second source operand to\r\nthe low packed single-precision floating-point value in the first source operand. From the infinite precision interme-\r\ndiate result, subtracts the low packed single-precision floating-point value in the third source operand, performs\r\nrounding and stores the resulting packed single-precision floating-point value to the destination operand (first\r\nsource operand).\r\nVFMSUB231SS: Multiplies the low packed single-precision floating-point value from the second source to the low\r\npacked single-precision floating-point value in the third source operand. From the infinite precision intermediate\r\nresult, subtracts the low packed single-precision floating-point value in the first source operand, performs rounding\r\nand stores the resulting packed single-precision floating-point value to the destination operand (first source\r\noperand).\r\nVEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field.\r\nThe second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field.\r\nBits 127:32 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.\r\n\r\n\r\n\r\n\r\nEVEX encoded version: The low doubleword element of the destination is updated according to the writemask.\r\nCompiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the\r\nopcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations\r\ninvolving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction\r\ncolumn.\r\n\r\nOperation\r\nIn the operations below, \"*\" and \"-\" symbols represent multiplication and subtraction with infinite precision inputs and outputs (no\r\nrounding).\r\n\r\nVFMSUB132SS DEST, SRC2, SRC3 (EVEX encoded version)\r\nIF (EVEX.b = 1) and SRC3 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[31:0] <- RoundFPControl(DEST[31:0]*SRC3[31:0] - SRC2[31:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[31:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:32] <- DEST[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVFMSUB213SS DEST, SRC2, SRC3 (EVEX encoded version)\r\nIF (EVEX.b = 1) and SRC3 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[31:0] <- RoundFPControl(SRC2[31:0]*DEST[31:0] - SRC3[31:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[31:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:32] <- DEST[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMSUB231SS DEST, SRC2, SRC3 (EVEX encoded version)\r\nIF (EVEX.b = 1) and SRC3 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[31:0] <- RoundFPControl(SRC2[31:0]*SRC3[63:0] - DEST[31:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[31:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:32] <- DEST[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVFMSUB132SS DEST, SRC2, SRC3 (VEX encoded version)\r\nDEST[31:0] <-RoundFPControl_MXCSR(DEST[31:0]*SRC3[31:0] - SRC2[31:0])\r\nDEST[127:32] <-DEST[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVFMSUB213SS DEST, SRC2, SRC3 (VEX encoded version)\r\nDEST[31:0] <-RoundFPControl_MXCSR(SRC2[31:0]*DEST[31:0] - SRC3[31:0])\r\nDEST[127:32] <-DEST[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVFMSUB231SS DEST, SRC2, SRC3 (VEX encoded version)\r\nDEST[31:0] <-RoundFPControl_MXCSR(SRC2[31:0]*SRC3[31:0] - DEST[31:0])\r\nDEST[127:32] <-DEST[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVFMSUBxxxSS __m128 _mm_fmsub_round_ss(__m128 a, __m128 b, __m128 c, int r);\r\nVFMSUBxxxSS __m128 _mm_mask_fmsub_ss(__m128 a, __mmask8 k, __m128 b, __m128 c);\r\nVFMSUBxxxSS __m128 _mm_maskz_fmsub_ss(__mmask8 k, __m128 a, __m128 b, __m128 c);\r\nVFMSUBxxxSS __m128 _mm_mask3_fmsub_ss(__m128 a, __m128 b, __m128 c, __mmask8 k);\r\nVFMSUBxxxSS __m128 _mm_mask_fmsub_round_ss(__m128 a, __mmask8 k, __m128 b, __m128 c, int r);\r\nVFMSUBxxxSS __m128 _mm_maskz_fmsub_round_ss(__mmask8 k, __m128 a, __m128 b, __m128 c, int r);\r\nVFMSUBxxxSS __m128 _mm_mask3_fmsub_round_ss(__m128 a, __m128 b, __m128 c, __mmask8 k, int r);\r\nVFMSUBxxxSS __m128 _mm_fmsub_ss (__m128 a, __m128 b, __m128 c);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3.\r\nEVEX-encoded instructions, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VFMSUB132SS"
},
{
"description": "-R:VFMSUB132PD",
"mnem": "VFMSUB213PD"
},
{
"description": "-R:VFMSUB132PS",
"mnem": "VFMSUB213PS"
},
{
"description": "-R:VFMSUB132SD",
"mnem": "VFMSUB213SD"
},
{
"description": "-R:VFMSUB132SS",
"mnem": "VFMSUB213SS"
},
{
"description": "-R:VFMSUB132PD",
"mnem": "VFMSUB231PD"
},
{
"description": "-R:VFMSUB132PS",
"mnem": "VFMSUB231PS"
},
{
"description": "-R:VFMSUB132SD",
"mnem": "VFMSUB231SD"
},
{
"description": "-R:VFMSUB132SS",
"mnem": "VFMSUB231SS"
},
{
"description": "VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD-Fused Multiply-Alternating\r\nSubtract/Add of Packed Double-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.DDS.128.66.0F38.W1 97 /r RVM V/V FMA Multiply packed double-precision floating-point values\r\n VFMSUBADD132PD xmm1, xmm2, from xmm1 and xmm3/mem, subtract/add elements\r\n xmm3/m128 in xmm2 and put result in xmm1.\r\n VEX.DDS.128.66.0F38.W1 A7 /r RVM V/V FMA Multiply packed double-precision floating-point values\r\n VFMSUBADD213PD xmm1, xmm2, from xmm1 and xmm2, subtract/add elements in\r\n xmm3/m128 xmm3/mem and put result in xmm1.\r\n VEX.DDS.128.66.0F38.W1 B7 /r RVM V/V FMA Multiply packed double-precision floating-point values\r\n VFMSUBADD231PD xmm1, xmm2, from xmm2 and xmm3/mem, subtract/add elements\r\n xmm3/m128 in xmm1 and put result in xmm1.\r\n VEX.DDS.256.66.0F38.W1 97 /r RVM V/V FMA Multiply packed double-precision floating-point values\r\n VFMSUBADD132PD ymm1, ymm2, from ymm1 and ymm3/mem, subtract/add elements\r\n ymm3/m256 in ymm2 and put result in ymm1.\r\n VEX.DDS.256.66.0F38.W1 A7 /r RVM V/V FMA Multiply packed double-precision floating-point values\r\n VFMSUBADD213PD ymm1, ymm2, from ymm1 and ymm2, subtract/add elements in\r\n ymm3/m256 ymm3/mem and put result in ymm1.\r\n VEX.DDS.256.66.0F38.W1 B7 /r RVM V/V FMA Multiply packed double-precision floating-point values\r\n VFMSUBADD231PD ymm1, ymm2, from ymm2 and ymm3/mem, subtract/add elements\r\n ymm3/m256 in ymm1 and put result in ymm1.\r\n EVEX.DDS.128.66.0F38.W1 97 /r FV V/V AVX512VL Multiply packed double-precision floating-point values\r\n VFMSUBADD132PD xmm1 {k1}{z}, AVX512F from xmm1 and xmm3/m128/m64bcst, subtract/add\r\n xmm2, xmm3/m128/m64bcst elements in xmm2 and put result in xmm1 subject to\r\n writemask k1.\r\n EVEX.DDS.128.66.0F38.W1 A7 /r FV V/V AVX512VL Multiply packed double-precision floating-point values\r\n VFMSUBADD213PD xmm1 {k1}{z}, AVX512F from xmm1 and xmm2, subtract/add elements in\r\n xmm2, xmm3/m128/m64bcst xmm3/m128/m64bcst and put result in xmm1\r\n subject to writemask k1.\r\n EVEX.DDS.128.66.0F38.W1 B7 /r FV V/V AVX512VL Multiply packed double-precision floating-point values\r\n VFMSUBADD231PD xmm1 {k1}{z}, AVX512F from xmm2 and xmm3/m128/m64bcst, subtract/add\r\n xmm2, xmm3/m128/m64bcst elements in xmm1 and put result in xmm1 subject to\r\n writemask k1.\r\n EVEX.DDS.256.66.0F38.W1 97 /r FV V/V AVX512VL Multiply packed double-precision floating-point values\r\n VFMSUBADD132PD ymm1 {k1}{z}, AVX512F from ymm1 and ymm3/m256/m64bcst, subtract/add\r\n ymm2, ymm3/m256/m64bcst elements in ymm2 and put result in ymm1 subject to\r\n writemask k1.\r\n EVEX.DDS.256.66.0F38.W1 A7 /r FV V/V AVX512VL Multiply packed double-precision floating-point values\r\n VFMSUBADD213PD ymm1 {k1}{z}, AVX512F from ymm1 and ymm2, subtract/add elements in\r\n ymm2, ymm3/m256/m64bcst ymm3/m256/m64bcst and put result in ymm1\r\n subject to writemask k1.\r\n EVEX.DDS.256.66.0F38.W1 B7 /r FV V/V AVX512VL Multiply packed double-precision floating-point values\r\n VFMSUBADD231PD ymm1 {k1}{z}, AVX512F from ymm2 and ymm3/m256/m64bcst, subtract/add\r\n ymm2, ymm3/m256/m64bcst elements in ymm1 and put result in ymm1 subject to\r\n writemask k1.\r\n\r\n\r\n\r\n\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.DDS.512.66.0F38.W1 97 /r FV V/V AVX512F Multiply packed double-precision floating-point values\r\n VFMSUBADD132PD zmm1 {k1}{z}, from zmm1 and zmm3/m512/m64bcst, subtract/add\r\n zmm2, zmm3/m512/m64bcst{er} elements in zmm2 and put result in zmm1 subject to\r\n writemask k1.\r\n EVEX.DDS.512.66.0F38.W1 A7 /r FV V/V AVX512F Multiply packed double-precision floating-point values\r\n VFMSUBADD213PD zmm1 {k1}{z}, from zmm1 and zmm2, subtract/add elements in\r\n zmm2, zmm3/m512/m64bcst{er} zmm3/m512/m64bcst and put result in zmm1 subject\r\n to writemask k1.\r\n EVEX.DDS.512.66.0F38.W1 B7 /r FV V/V AVX512F Multiply packed double-precision floating-point values\r\n VFMSUBADD231PD zmm1 {k1}{z}, from zmm2 and zmm3/m512/m64bcst, subtract/add\r\n zmm2, zmm3/m512/m64bcst{er} elements in zmm1 and put result in zmm1 subject to\r\n writemask k1.\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nVFMSUBADD132PD: Multiplies the two, four, or eight packed double-precision floating-point values from the first\r\nsource operand to the two or four packed double-precision floating-point values in the third source operand. From\r\nthe infinite precision intermediate result, subtracts the odd double-precision floating-point elements and adds the\r\neven double-precision floating-point values in the second source operand, performs rounding and stores the\r\nresulting two or four packed double-precision floating-point values to the destination operand (first source\r\noperand).\r\nVFMSUBADD213PD: Multiplies the two, four, or eight packed double-precision floating-point values from the\r\nsecond source operand to the two or four packed double-precision floating-point values in the first source operand.\r\nFrom the infinite precision intermediate result, subtracts the odd double-precision floating-point elements and\r\nadds the even double-precision floating-point values in the third source operand, performs rounding and stores the\r\nresulting two or four packed double-precision floating-point values to the destination operand (first source\r\noperand).\r\nVFMSUBADD231PD: Multiplies the two, four, or eight packed double-precision floating-point values from the\r\nsecond source operand to the two or four packed double-precision floating-point values in the third source operand.\r\nFrom the infinite precision intermediate result, subtracts the odd double-precision floating-point elements and\r\nadds the even double-precision floating-point values in the first source operand, performs rounding and stores the\r\nresulting two or four packed double-precision floating-point values to the destination operand (first source\r\noperand).\r\nEVEX encoded versions: The destination operand (also first source operand) and the second source operand are\r\nZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-\r\ntion or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is condition-\r\nally updated with write mask k1.\r\n\r\n\r\n\r\n\r\n\r\nVEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in\r\nreg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a\r\nYMM register or a 256-bit memory location and encoded in rm_field.\r\nVEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in\r\nreg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a\r\nXMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination\r\nregister are zeroed.\r\nCompiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the\r\nopcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations\r\ninvolving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction\r\ncolumn.\r\n\r\nOperation\r\nIn the operations below, \"*\" and \"+\" symbols represent multiplication and addition with infinite precision inputs and outputs (no\r\nrounding).\r\n\r\nVFMSUBADD132PD DEST, SRC2, SRC3\r\nIF (VEX.128) THEN\r\n DEST[63:0] <-RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] + SRC2[63:0])\r\n DEST[127:64] <-RoundFPControl_MXCSR(DEST[127:64]*SRC3[127:64] - SRC2[127:64])\r\n DEST[MAX_VL-1:128] <-0\r\nELSEIF (VEX.256)\r\n DEST[63:0] <-RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] + SRC2[63:0])\r\n DEST[127:64] <-RoundFPControl_MXCSR(DEST[127:64]*SRC3[127:64] - SRC2[127:64])\r\n DEST[191:128] <-RoundFPControl_MXCSR(DEST[191:128]*SRC3[191:128] + SRC2[191:128])\r\n DEST[255:192] <-RoundFPControl_MXCSR(DEST[255:192]*SRC3[255:192] - SRC2[255:192]\r\nFI\r\n\r\nVFMSUBADD213PD DEST, SRC2, SRC3\r\nIF (VEX.128) THEN\r\n DEST[63:0] <-RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] + SRC3[63:0])\r\n DEST[127:64] <-RoundFPControl_MXCSR(SRC2[127:64]*DEST[127:64] - SRC3[127:64])\r\n DEST[MAX_VL-1:128] <-0\r\nELSEIF (VEX.256)\r\n DEST[63:0] <-RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] + SRC3[63:0])\r\n DEST[127:64] <-RoundFPControl_MXCSR(SRC2[127:64]*DEST[127:64] - SRC3[127:64])\r\n DEST[191:128] <-RoundFPControl_MXCSR(SRC2[191:128]*DEST[191:128] + SRC3[191:128])\r\n DEST[255:192] <-RoundFPControl_MXCSR(SRC2[255:192]*DEST[255:192] - SRC3[255:192]\r\nFI\r\n\r\nVFMSUBADD231PD DEST, SRC2, SRC3\r\nIF (VEX.128) THEN\r\n DEST[63:0] <-RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] + DEST[63:0])\r\n DEST[127:64] <-RoundFPControl_MXCSR(SRC2[127:64]*SRC3[127:64] - DEST[127:64])\r\n DEST[MAX_VL-1:128] <-0\r\nELSEIF (VEX.256)\r\n DEST[63:0] <-RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] + DEST[63:0])\r\n DEST[127:64] <-RoundFPControl_MXCSR(SRC2[127:64]*SRC3[127:64] - DEST[127:64])\r\n DEST[191:128] <-RoundFPControl_MXCSR(SRC2[191:128]*SRC3[191:128] + DEST[191:128])\r\n DEST[255:192] <-RoundFPControl_MXCSR(SRC2[255:192]*SRC3[255:192] - DEST[255:192]\r\nFI\r\n\r\n\r\n\r\n\r\n\r\nVFMSUBADD132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF j *is even*\r\n THEN DEST[i+63:i] <-\r\n RoundFPControl(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i])\r\n ELSE DEST[i+63:i] <-\r\n RoundFPControl(DEST[i+63:i]*SRC3[i+63:i] - SRC2[i+63:i])\r\n FI\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMSUBADD132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF j *is even*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[63:0] + SRC2[i+63:i])\r\n ELSE\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i])\r\n FI;\r\n ELSE\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[63:0] - SRC2[i+63:i])\r\n ELSE\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] - SRC2[i+63:i])\r\n FI;\r\n FI\r\n\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMSUBADD213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF j *is even*\r\n THEN DEST[i+63:i] <-\r\n RoundFPControl(SRC2[i+63:i]*DEST[i+63:i] + SRC3[i+63:i])\r\n ELSE DEST[i+63:i] <-\r\n RoundFPControl(SRC2[i+63:i]*DEST[i+63:i] - SRC3[i+63:i])\r\n FI\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMSUBADD213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF j *is even*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] + SRC3[63:0])\r\n ELSE\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] + SRC3[i+63:i])\r\n FI;\r\n ELSE\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] - SRC3[63:0])\r\n ELSE\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] - SRC3[i+63:i])\r\n FI;\r\n FI\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMSUBADD231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF j *is even*\r\n THEN DEST[i+63:i] <-\r\n RoundFPControl(SRC2[i+63:i]*SRC3[i+63:i] + DEST[i+63:i])\r\n ELSE DEST[i+63:i] <-\r\n RoundFPControl(SRC2[i+63:i]*SRC3[i+63:i] - DEST[i+63:i])\r\n FI\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMSUBADD231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF j *is even*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[63:0] + DEST[i+63:i])\r\n ELSE\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[i+63:i] + DEST[i+63:i])\r\n FI;\r\n ELSE\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[63:0] - DEST[i+63:i])\r\n\r\n ELSE\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[i+63:i] - DEST[i+63:i])\r\n FI;\r\n FI\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVFMSUBADDxxxPD __m512d _mm512_fmsubadd_pd(__m512d a, __m512d b, __m512d c);\r\nVFMSUBADDxxxPD __m512d _mm512_fmsubadd_round_pd(__m512d a, __m512d b, __m512d c, int r);\r\nVFMSUBADDxxxPD __m512d _mm512_mask_fmsubadd_pd(__m512d a, __mmask8 k, __m512d b, __m512d c);\r\nVFMSUBADDxxxPD __m512d _mm512_maskz_fmsubadd_pd(__mmask8 k, __m512d a, __m512d b, __m512d c);\r\nVFMSUBADDxxxPD __m512d _mm512_mask3_fmsubadd_pd(__m512d a, __m512d b, __m512d c, __mmask8 k);\r\nVFMSUBADDxxxPD __m512d _mm512_mask_fmsubadd_round_pd(__m512d a, __mmask8 k, __m512d b, __m512d c, int r);\r\nVFMSUBADDxxxPD __m512d _mm512_maskz_fmsubadd_round_pd(__mmask8 k, __m512d a, __m512d b, __m512d c, int r);\r\nVFMSUBADDxxxPD __m512d _mm512_mask3_fmsubadd_round_pd(__m512d a, __m512d b, __m512d c, __mmask8 k, int r);\r\nVFMSUBADDxxxPD __m256d _mm256_mask_fmsubadd_pd(__m256d a, __mmask8 k, __m256d b, __m256d c);\r\nVFMSUBADDxxxPD __m256d _mm256_maskz_fmsubadd_pd(__mmask8 k, __m256d a, __m256d b, __m256d c);\r\nVFMSUBADDxxxPD __m256d _mm256_mask3_fmsubadd_pd(__m256d a, __m256d b, __m256d c, __mmask8 k);\r\nVFMSUBADDxxxPD __m128d _mm_mask_fmsubadd_pd(__m128d a, __mmask8 k, __m128d b, __m128d c);\r\nVFMSUBADDxxxPD __m128d _mm_maskz_fmsubadd_pd(__mmask8 k, __m128d a, __m128d b, __m128d c);\r\nVFMSUBADDxxxPD __m128d _mm_mask3_fmsubadd_pd(__m128d a, __m128d b, __m128d c, __mmask8 k);\r\nVFMSUBADDxxxPD __m128d _mm_fmsubadd_pd (__m128d a, __m128d b, __m128d c);\r\nVFMSUBADDxxxPD __m256d _mm256_fmsubadd_pd (__m256d a, __m256d b, __m256d c);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2.\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VFMSUBADD132PD"
},
{
"description": "VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS-Fused Multiply-Alternating\r\nSubtract/Add of Packed Single-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.DDS.128.66.0F38.W0 97 /r RVM V/V FMA Multiply packed single-precision floating-point values from\r\n VFMSUBADD132PS xmm1, xmm2, xmm1 and xmm3/mem, subtract/add elements in xmm2\r\n xmm3/m128 and put result in xmm1.\r\n VEX.DDS.128.66.0F38.W0 A7 /r RVM V/V FMA Multiply packed single-precision floating-point values from\r\n VFMSUBADD213PS xmm1, xmm2, xmm1 and xmm2, subtract/add elements in xmm3/mem\r\n xmm3/m128 and put result in xmm1.\r\n VEX.DDS.128.66.0F38.W0 B7 /r RVM V/V FMA Multiply packed single-precision floating-point values from\r\n VFMSUBADD231PS xmm1, xmm2, xmm2 and xmm3/mem, subtract/add elements in xmm1\r\n xmm3/m128 and put result in xmm1.\r\n VEX.DDS.256.66.0F38.W0 97 /r RVM V/V FMA Multiply packed single-precision floating-point values from\r\n VFMSUBADD132PS ymm1, ymm2, ymm1 and ymm3/mem, subtract/add elements in ymm2\r\n ymm3/m256 and put result in ymm1.\r\n VEX.DDS.256.66.0F38.W0 A7 /r RVM V/V FMA Multiply packed single-precision floating-point values from\r\n VFMSUBADD213PS ymm1, ymm2, ymm1 and ymm2, subtract/add elements in ymm3/mem\r\n ymm3/m256 and put result in ymm1.\r\n VEX.DDS.256.66.0F38.W0 B7 /r RVM V/V FMA Multiply packed single-precision floating-point values from\r\n VFMSUBADD231PS ymm1, ymm2, ymm2 and ymm3/mem, subtract/add elements in ymm1\r\n ymm3/m256 and put result in ymm1.\r\n EVEX.DDS.128.66.0F38.W0 97 /r FV V/V AVX512VL Multiply packed single-precision floating-point values from\r\n VFMSUBADD132PS xmm1 {k1}{z}, AVX512F xmm1 and xmm3/m128/m32bcst, subtract/add elements\r\n xmm2, xmm3/m128/m32bcst in xmm2 and put result in xmm1 subject to writemask k1.\r\n EVEX.DDS.128.66.0F38.W0 A7 /r FV V/V AVX512VL Multiply packed single-precision floating-point values from\r\n VFMSUBADD213PS xmm1 {k1}{z}, AVX512F xmm1 and xmm2, subtract/add elements in\r\n xmm2, xmm3/m128/m32bcst xmm3/m128/m32bcst and put result in xmm1 subject to\r\n writemask k1.\r\n EVEX.DDS.128.66.0F38.W0 B7 /r FV V/V AVX512VL Multiply packed single-precision floating-point values from\r\n VFMSUBADD231PS xmm1 {k1}{z}, AVX512F xmm2 and xmm3/m128/m32bcst, subtract/add elements\r\n xmm2, xmm3/m128/m32bcst in xmm1 and put result in xmm1 subject to writemask k1.\r\n EVEX.DDS.256.66.0F38.W0 97 /r FV V/V AVX512VL Multiply packed single-precision floating-point values from\r\n VFMSUBADD132PS ymm1 {k1}{z}, AVX512F ymm1 and ymm3/m256/m32bcst, subtract/add elements\r\n ymm2, ymm3/m256/m32bcst in ymm2 and put result in ymm1 subject to writemask k1.\r\n EVEX.DDS.256.66.0F38.W0 A7 /r FV V/V AVX512VL Multiply packed single-precision floating-point values from\r\n VFMSUBADD213PS ymm1 {k1}{z}, AVX512F ymm1 and ymm2, subtract/add elements in\r\n ymm2, ymm3/m256/m32bcst ymm3/m256/m32bcst and put result in ymm1 subject to\r\n writemask k1.\r\n EVEX.DDS.256.66.0F38.W0 B7 /r FV V/V AVX512VL Multiply packed single-precision floating-point values from\r\n VFMSUBADD231PS ymm1 {k1}{z}, AVX512F ymm2 and ymm3/m256/m32bcst, subtract/add elements\r\n ymm2, ymm3/m256/m32bcst in ymm1 and put result in ymm1 subject to writemask k1.\r\n EVEX.DDS.512.66.0F38.W0 97 /r FV V/V AVX512F Multiply packed single-precision floating-point values from\r\n VFMSUBADD132PS zmm1 {k1}{z}, zmm1 and zmm3/m512/m32bcst, subtract/add elements\r\n zmm2, zmm3/m512/m32bcst{er} in zmm2 and put result in zmm1 subject to writemask k1.\r\n EVEX.DDS.512.66.0F38.W0 A7 /r FV V/V AVX512F Multiply packed single-precision floating-point values from\r\n VFMSUBADD213PS zmm1 {k1}{z}, zmm1 and zmm2, subtract/add elements in\r\n zmm2, zmm3/m512/m32bcst{er} zmm3/m512/m32bcst and put result in zmm1 subject to\r\n writemask k1.\r\n EVEX.DDS.512.66.0F38.W0 B7 /r FV V/V AVX512F Multiply packed single-precision floating-point values from\r\n VFMSUBADD231PS zmm1 {k1}{z}, zmm2 and zmm3/m512/m32bcst, subtract/add elements\r\n zmm2, zmm3/m512/m32bcst{er} in zmm1 and put result in zmm1 subject to writemask k1.\r\n\r\n\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nVFMSUBADD132PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the first\r\nsource operand to the corresponding packed single-precision floating-point values in the third source operand.\r\nFrom the infinite precision intermediate result, subtracts the odd single-precision floating-point elements and adds\r\nthe even single-precision floating-point values in the second source operand, performs rounding and stores the\r\nresulting packed single-precision floating-point values to the destination operand (first source operand).\r\nVFMSUBADD213PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the\r\nsecond source operand to the corresponding packed single-precision floating-point values in the first source\r\noperand. From the infinite precision intermediate result, subtracts the odd single-precision floating-point elements\r\nand adds the even single-precision floating-point values in the third source operand, performs rounding and stores\r\nthe resulting packed single-precision floating-point values to the destination operand (first source operand).\r\nVFMSUBADD231PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the\r\nsecond source operand to the corresponding packed single-precision floating-point values in the third source\r\noperand. From the infinite precision intermediate result, subtracts the odd single-precision floating-point elements\r\nand adds the even single-precision floating-point values in the first source operand, performs rounding and stores\r\nthe resulting packed single-precision floating-point values to the destination operand (first source operand).\r\nEVEX encoded versions: The destination operand (also first source operand) and the second source operand are\r\nZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-\r\ntion or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is condition-\r\nally updated with write mask k1.\r\nVEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in\r\nreg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a\r\nYMM register or a 256-bit memory location and encoded in rm_field.\r\nVEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in\r\nreg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a\r\nXMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination\r\nregister are zeroed.\r\nCompiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the\r\nopcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations\r\ninvolving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction\r\ncolumn.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nIn the operations below, \"*\" and \"+\" symbols represent multiplication and addition with infinite precision inputs and outputs (no\r\nrounding).\r\n\r\nVFMSUBADD132PS DEST, SRC2, SRC3\r\nIF (VEX.128) THEN\r\n MAXNUM <-2\r\nELSEIF (VEX.256)\r\n MAXNUM <- 4\r\nFI\r\nFor i = 0 to MAXNUM -1{\r\n n <- 64*i;\r\n DEST[n+31:n] <-RoundFPControl_MXCSR(DEST[n+31:n]*SRC3[n+31:n] + SRC2[n+31:n])\r\n DEST[n+63:n+32] <-RoundFPControl_MXCSR(DEST[n+63:n+32]*SRC3[n+63:n+32] -SRC2[n+63:n+32])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <-0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\nVFMSUBADD213PS DEST, SRC2, SRC3\r\nIF (VEX.128) THEN\r\n MAXNUM <-2\r\nELSEIF (VEX.256)\r\n MAXNUM <- 4\r\nFI\r\nFor i = 0 to MAXNUM -1{\r\n n <- 64*i;\r\n DEST[n+31:n] <-RoundFPControl_MXCSR(SRC2[n+31:n]*DEST[n+31:n] +SRC3[n+31:n])\r\n DEST[n+63:n+32] <-RoundFPControl_MXCSR(SRC2[n+63:n+32]*DEST[n+63:n+32] -SRC3[n+63:n+32])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <-0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\nVFMSUBADD231PS DEST, SRC2, SRC3\r\nIF (VEX.128) THEN\r\n MAXNUM <-2\r\nELSEIF (VEX.256)\r\n MAXNUM <- 4\r\nFI\r\nFor i = 0 to MAXNUM -1{\r\n n <- 64*i;\r\n DEST[n+31:n] <-RoundFPControl_MXCSR(SRC2[n+31:n]*SRC3[n+31:n] + DEST[n+31:n])\r\n DEST[n+63:n+32] <-RoundFPControl_MXCSR(SRC2[n+63:n+32]*SRC3[n+63:n+32] -DEST[n+63:n+32])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <-0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\n\r\n\r\nVFMSUBADD132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF j *is even*\r\n THEN DEST[i+31:i] <-\r\n RoundFPControl(DEST[i+31:i]*SRC3[i+31:i] + SRC2[i+31:i])\r\n ELSE DEST[i+31:i] <-\r\n RoundFPControl(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i])\r\n FI\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMSUBADD132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF j *is even*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[31:0] + SRC2[i+31:i])\r\n ELSE\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] + SRC2[i+31:i])\r\n FI;\r\n ELSE\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[31:0] - SRC2[i+31:i])\r\n ELSE\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i])\r\n FI;\r\n FI\r\n\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMSUBADD213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF j *is even*\r\n THEN DEST[i+31:i] <-\r\n RoundFPControl(SRC2[i+31:i]*DEST[i+31:i] + SRC3[i+31:i])\r\n ELSE DEST[i+31:i] <-\r\n RoundFPControl(SRC2[i+31:i]*DEST[i+31:i] - SRC3[i+31:i])\r\n FI\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMSUBADD213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF j *is even*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] + SRC3[31:0])\r\n ELSE\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] + SRC3[i+31:i])\r\n FI;\r\n ELSE\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[i+31:i])\r\n ELSE\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[31:0])\r\n FI;\r\n FI\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMSUBADD231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF j *is even*\r\n THEN DEST[i+31:i] <-\r\n RoundFPControl(SRC2[i+31:i]*SRC3[i+31:i] + DEST[i+31:i])\r\n ELSE DEST[i+31:i] <-\r\n RoundFPControl(SRC2[i+31:i]*SRC3[i+31:i] - DEST[i+31:i])\r\n FI\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFMSUBADD231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF j *is even*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[31:0] + DEST[i+31:i])\r\n ELSE\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] + DEST[i+31:i])\r\n FI;\r\n ELSE\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[31:0] - DEST[i+31:i])\r\n ELSE\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] - DEST[i+31:i])\r\n FI;\r\n FI\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVFMSUBADDxxxPS __m512 _mm512_fmsubadd_ps(__m512 a, __m512 b, __m512 c);\r\nVFMSUBADDxxxPS __m512 _mm512_fmsubadd_round_ps(__m512 a, __m512 b, __m512 c, int r);\r\nVFMSUBADDxxxPS __m512 _mm512_mask_fmsubadd_ps(__m512 a, __mmask16 k, __m512 b, __m512 c);\r\nVFMSUBADDxxxPS __m512 _mm512_maskz_fmsubadd_ps(__mmask16 k, __m512 a, __m512 b, __m512 c);\r\nVFMSUBADDxxxPS __m512 _mm512_mask3_fmsubadd_ps(__m512 a, __m512 b, __m512 c, __mmask16 k);\r\nVFMSUBADDxxxPS __m512 _mm512_mask_fmsubadd_round_ps(__m512 a, __mmask16 k, __m512 b, __m512 c, int r);\r\nVFMSUBADDxxxPS __m512 _mm512_maskz_fmsubadd_round_ps(__mmask16 k, __m512 a, __m512 b, __m512 c, int r);\r\nVFMSUBADDxxxPS __m512 _mm512_mask3_fmsubadd_round_ps(__m512 a, __m512 b, __m512 c, __mmask16 k, int r);\r\nVFMSUBADDxxxPS __m256 _mm256_mask_fmsubadd_ps(__m256 a, __mmask8 k, __m256 b, __m256 c);\r\nVFMSUBADDxxxPS __m256 _mm256_maskz_fmsubadd_ps(__mmask8 k, __m256 a, __m256 b, __m256 c);\r\nVFMSUBADDxxxPS __m256 _mm256_mask3_fmsubadd_ps(__m256 a, __m256 b, __m256 c, __mmask8 k);\r\nVFMSUBADDxxxPS __m128 _mm_mask_fmsubadd_ps(__m128 a, __mmask8 k, __m128 b, __m128 c);\r\nVFMSUBADDxxxPS __m128 _mm_maskz_fmsubadd_ps(__mmask8 k, __m128 a, __m128 b, __m128 c);\r\nVFMSUBADDxxxPS __m128 _mm_mask3_fmsubadd_ps(__m128 a, __m128 b, __m128 c, __mmask8 k);\r\nVFMSUBADDxxxPS __m128 _mm_fmsubadd_ps (__m128 a, __m128 b, __m128 c);\r\nVFMSUBADDxxxPS __m256 _mm256_fmsubadd_ps (__m256 a, __m256 b, __m256 c);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2.\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VFMSUBADD132PS"
},
{
"description": "-R:VFMSUBADD132PD",
"mnem": "VFMSUBADD213PD"
},
{
"description": "-R:VFMSUBADD132PS",
"mnem": "VFMSUBADD213PS"
},
{
"description": "-R:VFMSUBADD132PD",
"mnem": "VFMSUBADD231PD"
},
{
"description": "-R:VFMSUBADD132PS",
"mnem": "VFMSUBADD231PS"
},
{
"description": "VFNMADD132PD/VFNMADD213PD/VFNMADD231PD-Fused Negative Multiply-Add of Packed\r\nDouble-Precision Floating-Point Values\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.NDS.128.66.0F38.W1 9C /r RVM V/V FMA Multiply packed double-precision floating-point values from\r\n VFNMADD132PD xmm1, xmm2, xmm1 and xmm3/mem, negate the multiplication result\r\n xmm3/m128 and add to xmm2 and put result in xmm1.\r\n VEX.NDS.128.66.0F38.W1 AC /r RVM V/V FMA Multiply packed double-precision floating-point values from\r\n VFNMADD213PD xmm1, xmm2, xmm1 and xmm2, negate the multiplication result and add\r\n xmm3/m128 to xmm3/mem and put result in xmm1.\r\n VEX.NDS.128.66.0F38.W1 BC /r RVM V/V FMA Multiply packed double-precision floating-point values from\r\n VFNMADD231PD xmm1, xmm2, xmm2 and xmm3/mem, negate the multiplication result\r\n xmm3/m128 and add to xmm1 and put result in xmm1.\r\n VEX.NDS.256.66.0F38.W1 9C /r RVM V/V FMA Multiply packed double-precision floating-point values from\r\n VFNMADD132PD ymm1, ymm2, ymm1 and ymm3/mem, negate the multiplication result and\r\n ymm3/m256 add to ymm2 and put result in ymm1.\r\n VEX.NDS.256.66.0F38.W1 AC /r RVM V/V FMA Multiply packed double-precision floating-point values from\r\n VFNMADD213PD ymm1, ymm2, ymm1 and ymm2, negate the multiplication result and add\r\n ymm3/m256 to ymm3/mem and put result in ymm1.\r\n VEX.NDS.256.66.0F38.W1 BC /r RVM V/V FMA Multiply packed double-precision floating-point values from\r\n VFNMADD231PD ymm1, ymm2, ymm2 and ymm3/mem, negate the multiplication result and\r\n ymm3/m256 add to ymm1 and put result in ymm1.\r\n EVEX.NDS.128.66.0F38.W1 9C /r FV V/V AVX512VL Multiply packed double-precision floating-point values from\r\n VFNMADD132PD xmm0 {k1}{z}, AVX512F xmm1 and xmm3/m128/m64bcst, negate the\r\n xmm1, xmm2/m128/m64bcst multiplication result and add to xmm2 and put result in\r\n xmm1.\r\n EVEX.NDS.128.66.0F38.W1 AC /r FV V/V AVX512VL Multiply packed double-precision floating-point values from\r\n VFNMADD213PD xmm1 {k1}{z}, AVX512F xmm1 and xmm2, negate the multiplication result and add\r\n xmm2, xmm3/m128/m64bcst to xmm3/m128/m64bcst and put result in xmm1.\r\n EVEX.NDS.128.66.0F38.W1 BC /r FV V/V AVX512VL Multiply packed double-precision floating-point values from\r\n VFNMADD231PD xmm1 {k1}{z}, AVX512F xmm2 and xmm3/m128/m64bcst, negate the\r\n xmm2, xmm3/m128/m64bcst multiplication result and add to xmm1 and put result in\r\n xmm1.\r\n EVEX.NDS.256.66.0F38.W1 9C /r FV V/V AVX512VL Multiply packed double-precision floating-point values from\r\n VFNMADD132PD ymm1 {k1}{z}, AVX512F ymm1 and ymm3/m256/m64bcst, negate the\r\n ymm2, ymm3/m256/m64bcst multiplication result and add to ymm2 and put result in\r\n ymm1.\r\n EVEX.NDS.256.66.0F38.W1 AC /r FV V/V AVX512VL Multiply packed double-precision floating-point values from\r\n VFNMADD213PD ymm1 {k1}{z}, AVX512F ymm1 and ymm2, negate the multiplication result and add\r\n ymm2, ymm3/m256/m64bcst to ymm3/m256/m64bcst and put result in ymm1.\r\n EVEX.NDS.256.66.0F38.W1 BC /r FV V/V AVX512VL Multiply packed double-precision floating-point values from\r\n VFNMADD231PD ymm1 {k1}{z}, AVX512F ymm2 and ymm3/m256/m64bcst, negate the\r\n ymm2, ymm3/m256/m64bcst multiplication result and add to ymm1 and put result in\r\n ymm1.\r\n EVEX.NDS.512.66.0F38.W1 9C /r FV V/V AVX512F Multiply packed double-precision floating-point values from\r\n VFNMADD132PD zmm1 {k1}{z}, zmm1 and zmm3/m512/m64bcst, negate the multiplication\r\n zmm2, zmm3/m512/m64bcst{er} result and add to zmm2 and put result in zmm1.\r\n EVEX.NDS.512.66.0F38.W1 AC /r FV V/V AVX512F Multiply packed double-precision floating-point values from\r\n VFNMADD213PD zmm1 {k1}{z}, zmm1 and zmm2, negate the multiplication result and add\r\n zmm2, zmm3/m512/m64bcst{er} to zmm3/m512/m64bcst and put result in zmm1.\r\n EVEX.NDS.512.66.0F38.W1 BC /r FV V/V AVX512F Multiply packed double-precision floating-point values from\r\n VFNMADD231PD zmm1 {k1}{z}, zmm2 and zmm3/m512/m64bcst, negate the multiplication\r\n zmm2, zmm3/m512/m64bcst{er} result and add to zmm1 and put result in zmm1.\r\n\r\n\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nVFNMADD132PD: Multiplies the two, four or eight packed double-precision floating-point values from the first\r\nsource operand to the two, four or eight packed double-precision floating-point values in the third source operand,\r\nadds the negated infinite precision intermediate result to the two, four or eight packed double-precision floating-\r\npoint values in the second source operand, performs rounding and stores the resulting two, four or eight packed\r\ndouble-precision floating-point values to the destination operand (first source operand).\r\nVFNMADD213PD: Multiplies the two, four or eight packed double-precision floating-point values from the second\r\nsource operand to the two, four or eight packed double-precision floating-point values in the first source operand,\r\nadds the negated infinite precision intermediate result to the two, four or eight packed double-precision floating-\r\npoint values in the third source operand, performs rounding and stores the resulting two, four or eight packed\r\ndouble-precision floating-point values to the destination operand (first source operand).\r\nVFNMADD231PD: Multiplies the two, four or eight packed double-precision floating-point values from the second\r\nsource to the two, four or eight packed double-precision floating-point values in the third source operand, the\r\nnegated infinite precision intermediate result to the two, four or eight packed double-precision floating-point values\r\nin the first source operand, performs rounding and stores the resulting two, four or eight packed double-precision\r\nfloating-point values to the destination operand (first source operand).\r\nEVEX encoded versions: The destination operand (also first source operand) and the second source operand are\r\nZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-\r\ntion or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is condition-\r\nally updated with write mask k1.\r\nVEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in\r\nreg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a\r\nYMM register or a 256-bit memory location and encoded in rm_field.\r\nVEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in\r\nreg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a\r\nXMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination\r\nregister are zeroed.\r\n\r\nOperation\r\nIn the operations below, \"*\" and \"-\" symbols represent multiplication and subtraction with infinite precision inputs and outputs (no\r\nrounding).\r\n\r\n\r\n\r\n\r\n\r\nVFNMADD132PD DEST, SRC2, SRC3 (VEX encoded version)\r\nIF (VEX.128) THEN\r\n MAXNUM <-2\r\nELSEIF (VEX.256)\r\n MAXNUM <- 4\r\nFI\r\nFor i = 0 to MAXNUM-1 {\r\n n <- 64*i;\r\n DEST[n+63:n] <- RoundFPControl_MXCSR(-(DEST[n+63:n]*SRC3[n+63:n]) + SRC2[n+63:n])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <- 0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\nVFNMADD213PD DEST, SRC2, SRC3 (VEX encoded version)\r\nIF (VEX.128) THEN\r\n MAXNUM <-2\r\nELSEIF (VEX.256)\r\n MAXNUM <- 4\r\nFI\r\nFor i = 0 to MAXNUM-1 {\r\n n <- 64*i;\r\n DEST[n+63:n] <- RoundFPControl_MXCSR(-(SRC2[n+63:n]*DEST[n+63:n]) + SRC3[n+63:n])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <- 0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\nVFNMADD231PD DEST, SRC2, SRC3 (VEX encoded version)\r\nIF (VEX.128) THEN\r\n MAXNUM <-2\r\nELSEIF (VEX.256)\r\n MAXNUM <- 4\r\nFI\r\nFor i = 0 to MAXNUM-1 {\r\n n <- 64*i;\r\n DEST[n+63:n] <- RoundFPControl_MXCSR(-(SRC2[n+63:n]*SRC3[n+63:n]) + DEST[n+63:n])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <- 0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\n\r\n\r\n\r\n\r\nVFNMADD132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <-\r\n RoundFPControl(-(DEST[i+63:i]*SRC3[i+63:i]) + SRC2[i+63:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVFNMADD132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(-(DEST[i+63:i]*SRC3[63:0]) + SRC2[i+63:i])\r\n ELSE\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(-(DEST[i+63:i]*SRC3[i+63:i]) + SRC2[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFNMADD213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <-\r\n RoundFPControl(-(SRC2[i+63:i]*DEST[i+63:i]) + SRC3[i+63:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVFNMADD213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(-(SRC2[i+63:i]*DEST[i+63:i]) + SRC3[63:0])\r\n ELSE\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(-(SRC2[i+63:i]*DEST[i+63:i]) + SRC3[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFNMADD231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <-\r\n RoundFPControl(-(SRC2[i+63:i]*SRC3[i+63:i]) + DEST[i+63:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVFNMADD231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(-(SRC2[i+63:i]*SRC3[63:0]) + DEST[i+63:i])\r\n ELSE\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(-(SRC2[i+63:i]*SRC3[i+63:i]) + DEST[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVFNMADDxxxPD __m512d _mm512_fnmadd_pd(__m512d a, __m512d b, __m512d c);\r\nVFNMADDxxxPD __m512d _mm512_fnmadd_round_pd(__m512d a, __m512d b, __m512d c, int r);\r\nVFNMADDxxxPD __m512d _mm512_mask_fnmadd_pd(__m512d a, __mmask8 k, __m512d b, __m512d c);\r\nVFNMADDxxxPD __m512d _mm512_maskz_fnmadd_pd(__mmask8 k, __m512d a, __m512d b, __m512d c);\r\nVFNMADDxxxPD __m512d _mm512_mask3_fnmadd_pd(__m512d a, __m512d b, __m512d c, __mmask8 k);\r\nVFNMADDxxxPD __m512d _mm512_mask_fnmadd_round_pd(__m512d a, __mmask8 k, __m512d b, __m512d c, int r);\r\nVFNMADDxxxPD __m512d _mm512_maskz_fnmadd_round_pd(__mmask8 k, __m512d a, __m512d b, __m512d c, int r);\r\nVFNMADDxxxPD __m512d _mm512_mask3_fnmadd_round_pd(__m512d a, __m512d b, __m512d c, __mmask8 k, int r);\r\nVFNMADDxxxPD __m256d _mm256_mask_fnmadd_pd(__m256d a, __mmask8 k, __m256d b, __m256d c);\r\nVFNMADDxxxPD __m256d _mm256_maskz_fnmadd_pd(__mmask8 k, __m256d a, __m256d b, __m256d c);\r\nVFNMADDxxxPD __m256d _mm256_mask3_fnmadd_pd(__m256d a, __m256d b, __m256d c, __mmask8 k);\r\nVFNMADDxxxPD __m128d _mm_mask_fnmadd_pd(__m128d a, __mmask8 k, __m128d b, __m128d c);\r\nVFNMADDxxxPD __m128d _mm_maskz_fnmadd_pd(__mmask8 k, __m128d a, __m128d b, __m128d c);\r\nVFNMADDxxxPD __m128d _mm_mask3_fnmadd_pd(__m128d a, __m128d b, __m128d c, __mmask8 k);\r\nVFNMADDxxxPD __m128d _mm_fnmadd_pd (__m128d a, __m128d b, __m128d c);\r\nVFNMADDxxxPD __m256d _mm256_fnmadd_pd (__m256d a, __m256d b, __m256d c);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2.\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VFNMADD132PD"
},
{
"description": "VFNMADD132PS/VFNMADD213PS/VFNMADD231PS-Fused Negative Multiply-Add of Packed\r\nSingle-Precision Floating-Point Values\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.NDS.128.66.0F38.W0 9C /r RVM V/V FMA Multiply packed single-precision floating-point values from\r\n VFNMADD132PS xmm1, xmm2, xmm1 and xmm3/mem, negate the multiplication result\r\n xmm3/m128 and add to xmm2 and put result in xmm1.\r\n VEX.NDS.128.66.0F38.W0 AC /r RVM V/V FMA Multiply packed single-precision floating-point values from\r\n VFNMADD213PS xmm1, xmm2, xmm1 and xmm2, negate the multiplication result and add\r\n xmm3/m128 to xmm3/mem and put result in xmm1.\r\n VEX.NDS.128.66.0F38.W0 BC /r RVM V/V FMA Multiply packed single-precision floating-point values from\r\n VFNMADD231PS xmm1, xmm2, xmm2 and xmm3/mem, negate the multiplication result\r\n xmm3/m128 and add to xmm1 and put result in xmm1.\r\n VEX.NDS.256.66.0F38.W0 9C /r RVM V/V FMA Multiply packed single-precision floating-point values from\r\n VFNMADD132PS ymm1, ymm2, ymm1 and ymm3/mem, negate the multiplication result\r\n ymm3/m256 and add to ymm2 and put result in ymm1.\r\n VEX.NDS.256.66.0F38.W0 AC /r RVM V/V FMA Multiply packed single-precision floating-point values from\r\n VFNMADD213PS ymm1, ymm2, ymm1 and ymm2, negate the multiplication result and add\r\n ymm3/m256 to ymm3/mem and put result in ymm1.\r\n VEX.NDS.256.66.0F38.0 BC /r RVM V/V FMA Multiply packed single-precision floating-point values from\r\n VFNMADD231PS ymm1, ymm2, ymm2 and ymm3/mem, negate the multiplication result and\r\n ymm3/m256 add to ymm1 and put result in ymm1.\r\n EVEX.NDS.128.66.0F38.W0 9C /r FV V/V AVX512VL Multiply packed single-precision floating-point values from\r\n VFNMADD132PS xmm1 {k1}{z}, AVX512F xmm1 and xmm3/m128/m32bcst, negate the multiplication\r\n xmm2, xmm3/m128/m32bcst result and add to xmm2 and put result in xmm1.\r\n EVEX.NDS.128.66.0F38.W0 AC /r FV V/V AVX512VL Multiply packed single-precision floating-point values from\r\n VFNMADD213PS xmm1 {k1}{z}, AVX512F xmm1 and xmm2, negate the multiplication result and add\r\n xmm2, xmm3/m128/m32bcst to xmm3/m128/m32bcst and put result in xmm1.\r\n EVEX.NDS.128.66.0F38.W0 BC /r FV V/V AVX512VL Multiply packed single-precision floating-point values from\r\n VFNMADD231PS xmm1 {k1}{z}, AVX512F xmm2 and xmm3/m128/m32bcst, negate the multiplication\r\n xmm2, xmm3/m128/m32bcst result and add to xmm1 and put result in xmm1.\r\n EVEX.NDS.256.66.0F38.W0 9C /r FV V/V AVX512VL Multiply packed single-precision floating-point values from\r\n VFNMADD132PS ymm1 {k1}{z}, AVX512F ymm1 and ymm3/m256/m32bcst, negate the multiplication\r\n ymm2, ymm3/m256/m32bcst result and add to ymm2 and put result in ymm1.\r\n EVEX.NDS.256.66.0F38.W0 AC /r FV V/V AVX512VL Multiply packed single-precision floating-point values from\r\n VFNMADD213PS ymm1 {k1}{z}, AVX512F ymm1 and ymm2, negate the multiplication result and add\r\n ymm2, ymm3/m256/m32bcst to ymm3/m256/m32bcst and put result in ymm1.\r\n EVEX.NDS.256.66.0F38.W0 BC /r FV V/V AVX512VL Multiply packed single-precision floating-point values from\r\n VFNMADD231PS ymm1 {k1}{z}, AVX512F ymm2 and ymm3/m256/m32bcst, negate the multiplication\r\n ymm2, ymm3/m256/m32bcst result and add to ymm1 and put result in ymm1.\r\n EVEX.NDS.512.66.0F38.W0 9C /r FV V/V AVX512VL Multiply packed single-precision floating-point values from\r\n VFNMADD132PS zmm1 {k1}{z}, AVX512F zmm1 and zmm3/m512/m32bcst, negate the multiplication\r\n zmm2, zmm3/m512/m32bcst{er} result and add to zmm2 and put result in zmm1.\r\n EVEX.NDS.512.66.0F38.W0 AC /r FV V/V AVX512F Multiply packed single-precision floating-point values from\r\n VFNMADD213PS zmm1 {k1}{z}, zmm1 and zmm2, negate the multiplication result and add\r\n zmm2, zmm3/m512/m32bcst{er} to zmm3/m512/m32bcst and put result in zmm1.\r\n EVEX.NDS.512.66.0F38.W0 BC /r FV V/V AVX512F Multiply packed single-precision floating-point values from\r\n VFNMADD231PS zmm1 {k1}{z}, zmm2 and zmm3/m512/m32bcst, negate the multiplication\r\n zmm2, zmm3/m512/m32bcst{er} result and add to zmm1 and put result in zmm1.\r\n\r\n\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nVFNMADD132PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the first\r\nsource operand to the four, eight or sixteen packed single-precision floating-point values in the third source\r\noperand, adds the negated infinite precision intermediate result to the four, eight or sixteen packed single-preci-\r\nsion floating-point values in the second source operand, performs rounding and stores the resulting four, eight or\r\nsixteen packed single-precision floating-point values to the destination operand (first source operand).\r\nVFNMADD213PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second\r\nsource operand to the four, eight or sixteen packed single-precision floating-point values in the first source\r\noperand, adds the negated infinite precision intermediate result to the four, eight or sixteen packed single-preci-\r\nsion floating-point values in the third source operand, performs rounding and stores the resulting the four, eight or\r\nsixteen packed single-precision floating-point values to the destination operand (first source operand).\r\nVFNMADD231PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second\r\nsource operand to the four, eight or sixteen packed single-precision floating-point values in the third source\r\noperand, adds the negated infinite precision intermediate result to the four, eight or sixteen packed single-preci-\r\nsion floating-point values in the first source operand, performs rounding and stores the resulting four, eight or\r\nsixteen packed single-precision floating-point values to the destination operand (first source operand).\r\nEVEX encoded versions: The destination operand (also first source operand) and the second source operand are\r\nZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-\r\ntion or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is condition-\r\nally updated with write mask k1.\r\nVEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in\r\nreg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a\r\nYMM register or a 256-bit memory location and encoded in rm_field.\r\nVEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in\r\nreg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a\r\nXMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination\r\nregister are zeroed.\r\n\r\nOperation\r\nIn the operations below, \"*\" and \"+\" symbols represent multiplication and addition with infinite precision inputs and outputs (no\r\nrounding).\r\n\r\nVFNMADD132PS DEST, SRC2, SRC3 (VEX encoded version)\r\nIF (VEX.128) THEN\r\n MAXNUM <-2\r\nELSEIF (VEX.256)\r\n MAXNUM <- 4\r\nFI\r\nFor i = 0 to MAXNUM-1 {\r\n n <- 32*i;\r\n DEST[n+31:n] <- RoundFPControl_MXCSR(- (DEST[n+31:n]*SRC3[n+31:n]) + SRC2[n+31:n])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <- 0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\n\r\n\r\n\r\nVFNMADD213PS DEST, SRC2, SRC3 (VEX encoded version)\r\nIF (VEX.128) THEN\r\n MAXNUM <-2\r\nELSEIF (VEX.256)\r\n MAXNUM <- 4\r\nFI\r\nFor i = 0 to MAXNUM-1 {\r\n n <- 32*i;\r\n DEST[n+31:n] <- RoundFPControl_MXCSR(- (SRC2[n+31:n]*DEST[n+31:n]) + SRC3[n+31:n])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <- 0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\nVFNMADD231PS DEST, SRC2, SRC3 (VEX encoded version)\r\nIF (VEX.128) THEN\r\n MAXNUM <-2\r\nELSEIF (VEX.256)\r\n MAXNUM <- 4\r\nFI\r\nFor i = 0 to MAXNUM-1 {\r\n n <- 32*i;\r\n DEST[n+31:n] <- RoundFPControl_MXCSR(- (SRC2[n+31:n]*SRC3[n+31:n]) + DEST[n+31:n])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <- 0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\nVFNMADD132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <-\r\n RoundFPControl(-(DEST[i+31:i]*SRC3[i+31:i]) + SRC2[i+31:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\nVFNMADD132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(-(DEST[i+31:i]*SRC3[31:0]) + SRC2[i+31:i])\r\n ELSE\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(-(DEST[i+31:i]*SRC3[i+31:i]) + SRC2[i+31:i])\r\n FI;\r\n\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVFNMADD213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <-\r\n RoundFPControl(-(SRC2[i+31:i]*DEST[i+31:i]) + SRC3[i+31:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFNMADD213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(-(SRC2[i+31:i]*DEST[i+31:i]) + SRC3[31:0])\r\n\r\n ELSE\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(-(SRC2[i+31:i]*DEST[i+31:i]) + SRC3[i+31:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVFNMADD231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <-\r\n RoundFPControl(-(SRC2[i+31:i]*SRC3[i+31:i]) + DEST[i+31:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFNMADD231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(-(SRC2[i+31:i]*SRC3[31:0]) + DEST[i+31:i])\r\n ELSE\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(-(SRC2[i+31:i]*SRC3[i+31:i]) + DEST[i+31:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVFNMADDxxxPS __m512 _mm512_fnmadd_ps(__m512 a, __m512 b, __m512 c);\r\nVFNMADDxxxPS __m512 _mm512_fnmadd_round_ps(__m512 a, __m512 b, __m512 c, int r);\r\nVFNMADDxxxPS __m512 _mm512_mask_fnmadd_ps(__m512 a, __mmask16 k, __m512 b, __m512 c);\r\nVFNMADDxxxPS __m512 _mm512_maskz_fnmadd_ps(__mmask16 k, __m512 a, __m512 b, __m512 c);\r\nVFNMADDxxxPS __m512 _mm512_mask3_fnmadd_ps(__m512 a, __m512 b, __m512 c, __mmask16 k);\r\nVFNMADDxxxPS __m512 _mm512_mask_fnmadd_round_ps(__m512 a, __mmask16 k, __m512 b, __m512 c, int r);\r\nVFNMADDxxxPS __m512 _mm512_maskz_fnmadd_round_ps(__mmask16 k, __m512 a, __m512 b, __m512 c, int r);\r\nVFNMADDxxxPS __m512 _mm512_mask3_fnmadd_round_ps(__m512 a, __m512 b, __m512 c, __mmask16 k, int r);\r\nVFNMADDxxxPS __m256 _mm256_mask_fnmadd_ps(__m256 a, __mmask8 k, __m256 b, __m256 c);\r\nVFNMADDxxxPS __m256 _mm256_maskz_fnmadd_ps(__mmask8 k, __m256 a, __m256 b, __m256 c);\r\nVFNMADDxxxPS __m256 _mm256_mask3_fnmadd_ps(__m256 a, __m256 b, __m256 c, __mmask8 k);\r\nVFNMADDxxxPS __m128 _mm_mask_fnmadd_ps(__m128 a, __mmask8 k, __m128 b, __m128 c);\r\nVFNMADDxxxPS __m128 _mm_maskz_fnmadd_ps(__mmask8 k, __m128 a, __m128 b, __m128 c);\r\nVFNMADDxxxPS __m128 _mm_mask3_fnmadd_ps(__m128 a, __m128 b, __m128 c, __mmask8 k);\r\nVFNMADDxxxPS __m128 _mm_fnmadd_ps (__m128 a, __m128 b, __m128 c);\r\nVFNMADDxxxPS __m256 _mm256_fnmadd_ps (__m256 a, __m256 b, __m256 c);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2.\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VFNMADD132PS"
},
{
"description": "VFNMADD132SD/VFNMADD213SD/VFNMADD231SD-Fused Negative Multiply-Add of Scalar\r\nDouble-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.DDS.LIG.66.0F38.W1 9D /r RVM V/V FMA Multiply scalar double-precision floating-point value from\r\n VFNMADD132SD xmm1, xmm2, xmm1 and xmm3/mem, negate the multiplication result and\r\n xmm3/m64 add to xmm2 and put result in xmm1.\r\n VEX.DDS.LIG.66.0F38.W1 AD /r RVM V/V FMA Multiply scalar double-precision floating-point value from\r\n VFNMADD213SD xmm1, xmm2, xmm1 and xmm2, negate the multiplication result and add to\r\n xmm3/m64 xmm3/mem and put result in xmm1.\r\n VEX.DDS.LIG.66.0F38.W1 BD /r RVM V/V FMA Multiply scalar double-precision floating-point value from\r\n VFNMADD231SD xmm1, xmm2, xmm2 and xmm3/mem, negate the multiplication result and\r\n xmm3/m64 add to xmm1 and put result in xmm1.\r\n EVEX.DDS.LIG.66.0F38.W1 9D /r T1S V/V AVX512F Multiply scalar double-precision floating-point value from\r\n VFNMADD132SD xmm1 {k1}{z}, xmm1 and xmm3/m64, negate the multiplication result and\r\n xmm2, xmm3/m64{er} add to xmm2 and put result in xmm1.\r\n EVEX.DDS.LIG.66.0F38.W1 AD /r T1S V/V AVX512F Multiply scalar double-precision floating-point value from\r\n VFNMADD213SD xmm1 {k1}{z}, xmm1 and xmm2, negate the multiplication result and add to\r\n xmm2, xmm3/m64{er} xmm3/m64 and put result in xmm1.\r\n EVEX.DDS.LIG.66.0F38.W1 BD /r T1S V/V AVX512F Multiply scalar double-precision floating-point value from\r\n VFNMADD231SD xmm1 {k1}{z}, xmm2 and xmm3/m64, negate the multiplication result and\r\n xmm2, xmm3/m64{er} add to xmm1 and put result in xmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n T1S ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nVFNMADD132SD: Multiplies the low packed double-precision floating-point value from the first source operand to\r\nthe low packed double-precision floating-point value in the third source operand, adds the negated infinite preci-\r\nsion intermediate result to the low packed double-precision floating-point values in the second source operand,\r\nperforms rounding and stores the resulting packed double-precision floating-point value to the destination operand\r\n(first source operand).\r\nVFNMADD213SD: Multiplies the low packed double-precision floating-point value from the second source operand\r\nto the low packed double-precision floating-point value in the first source operand, adds the negated infinite preci-\r\nsion intermediate result to the low packed double-precision floating-point value in the third source operand,\r\nperforms rounding and stores the resulting packed double-precision floating-point value to the destination operand\r\n(first source operand).\r\nVFNMADD231SD: Multiplies the low packed double-precision floating-point value from the second source to the low\r\npacked double-precision floating-point value in the third source operand, adds the negated infinite precision inter-\r\nmediate result to the low packed double-precision floating-point value in the first source operand, performs\r\nrounding and stores the resulting packed double-precision floating-point value to the destination operand (first\r\nsource operand).\r\nVEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field.\r\nThe second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field.\r\nBits 127:64 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.\r\n\r\n\r\n\r\n\r\n\r\nEVEX encoded version: The low quadword element of the destination is updated according to the writemask.\r\nCompiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the\r\nopcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations\r\ninvolving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction\r\ncolumn.\r\n\r\nOperation\r\nIn the operations below, \"*\" and \"+\" symbols represent multiplication and addition with infinite precision inputs and outputs (no\r\nrounding).\r\n\r\nVFNMADD132SD DEST, SRC2, SRC3 (EVEX encoded version)\r\nIF (EVEX.b = 1) and SRC3 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[63:0] <- RoundFPControl(-(DEST[63:0]*SRC3[63:0]) + SRC2[63:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[63:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:64] <- DEST[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVFNMADD213SD DEST, SRC2, SRC3 (EVEX encoded version)\r\nIF (EVEX.b = 1) and SRC3 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[63:0] <- RoundFPControl(-(SRC2[63:0]*DEST[63:0]) + SRC3[63:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[63:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:64] <- DEST[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFNMADD231SD DEST, SRC2, SRC3 (EVEX encoded version)\r\nIF (EVEX.b = 1) and SRC3 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[63:0] <- RoundFPControl(-(SRC2[63:0]*SRC3[63:0]) + DEST[63:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[63:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:64] <- DEST[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVFNMADD132SD DEST, SRC2, SRC3 (VEX encoded version)\r\nDEST[63:0] <-RoundFPControl_MXCSR(- (DEST[63:0]*SRC3[63:0]) + SRC2[63:0])\r\nDEST[127:64] <-DEST[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVFNMADD213SD DEST, SRC2, SRC3 (VEX encoded version)\r\nDEST[63:0] <-RoundFPControl_MXCSR(- (SRC2[63:0]*DEST[63:0]) + SRC3[63:0])\r\nDEST[127:64] <-DEST[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVFNMADD231SD DEST, SRC2, SRC3 (VEX encoded version)\r\nDEST[63:0] <-RoundFPControl_MXCSR(- (SRC2[63:0]*SRC3[63:0]) + DEST[63:0])\r\nDEST[127:64] <-DEST[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVFNMADDxxxSD __m128d _mm_fnmadd_round_sd(__m128d a, __m128d b, __m128d c, int r);\r\nVFNMADDxxxSD __m128d _mm_mask_fnmadd_sd(__m128d a, __mmask8 k, __m128d b, __m128d c);\r\nVFNMADDxxxSD __m128d _mm_maskz_fnmadd_sd(__mmask8 k, __m128d a, __m128d b, __m128d c);\r\nVFNMADDxxxSD __m128d _mm_mask3_fnmadd_sd(__m128d a, __m128d b, __m128d c, __mmask8 k);\r\nVFNMADDxxxSD __m128d _mm_mask_fnmadd_round_sd(__m128d a, __mmask8 k, __m128d b, __m128d c, int r);\r\nVFNMADDxxxSD __m128d _mm_maskz_fnmadd_round_sd(__mmask8 k, __m128d a, __m128d b, __m128d c, int r);\r\nVFNMADDxxxSD __m128d _mm_mask3_fnmadd_round_sd(__m128d a, __m128d b, __m128d c, __mmask8 k, int r);\r\nVFNMADDxxxSD __m128d _mm_fnmadd_sd (__m128d a, __m128d b, __m128d c);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3.\r\nEVEX-encoded instructions, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VFNMADD132SD"
},
{
"description": "VFNMADD132SS/VFNMADD213SS/VFNMADD231SS-Fused Negative Multiply-Add of Scalar\r\nSingle-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.DDS.LIG.66.0F38.W0 9D /r RVM V/V FMA Multiply scalar single-precision floating-point value from\r\n VFNMADD132SS xmm1, xmm2, xmm1 and xmm3/m32, negate the multiplication result\r\n xmm3/m32 and add to xmm2 and put result in xmm1.\r\n VEX.DDS.LIG.66.0F38.W0 AD /r RVM V/V FMA Multiply scalar single-precision floating-point value from\r\n VFNMADD213SS xmm1, xmm2, xmm1 and xmm2, negate the multiplication result and\r\n xmm3/m32 add to xmm3/m32 and put result in xmm1.\r\n VEX.DDS.LIG.66.0F38.W0 BD /r RVM V/V FMA Multiply scalar single-precision floating-point value from\r\n VFNMADD231SS xmm1, xmm2, xmm2 and xmm3/m32, negate the multiplication result\r\n xmm3/m32 and add to xmm1 and put result in xmm1.\r\n EVEX.DDS.LIG.66.0F38.W0 9D /r T1S V/V AVX512F Multiply scalar single-precision floating-point value from\r\n VFNMADD132SS xmm1 {k1}{z}, xmm1 and xmm3/m32, negate the multiplication result\r\n xmm2, xmm3/m32{er} and add to xmm2 and put result in xmm1.\r\n EVEX.DDS.LIG.66.0F38.W0 AD /r T1S V/V AVX512F Multiply scalar single-precision floating-point value from\r\n VFNMADD213SS xmm1 {k1}{z}, xmm1 and xmm2, negate the multiplication result and\r\n xmm2, xmm3/m32{er} add to xmm3/m32 and put result in xmm1.\r\n EVEX.DDS.LIG.66.0F38.W0 BD /r T1S V/V AVX512F Multiply scalar single-precision floating-point value from\r\n VFNMADD231SS xmm1 {k1}{z}, xmm2 and xmm3/m32, negate the multiplication result\r\n xmm2, xmm3/m32{er} and add to xmm1 and put result in xmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n T1S ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nVFNMADD132SS: Multiplies the low packed single-precision floating-point value from the first source operand to\r\nthe low packed single-precision floating-point value in the third source operand, adds the negated infinite precision\r\nintermediate result to the low packed single-precision floating-point value in the second source operand, performs\r\nrounding and stores the resulting packed single-precision floating-point value to the destination operand (first\r\nsource operand).\r\nVFNMADD213SS: Multiplies the low packed single-precision floating-point value from the second source operand\r\nto the low packed single-precision floating-point value in the first source operand, adds the negated infinite preci-\r\nsion intermediate result to the low packed single-precision floating-point value in the third source operand,\r\nperforms rounding and stores the resulting packed single-precision floating-point value to the destination operand\r\n(first source operand).\r\nVFNMADD231SS: Multiplies the low packed single-precision floating-point value from the second source operand\r\nto the low packed single-precision floating-point value in the third source operand, adds the negated infinite preci-\r\nsion intermediate result to the low packed single-precision floating-point value in the first source operand,\r\nperforms rounding and stores the resulting packed single-precision floating-point value to the destination operand\r\n(first source operand).\r\nVEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field.\r\nThe second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field.\r\nBits 127:32 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.\r\n\r\n\r\n\r\n\r\n\r\nEVEX encoded version: The low doubleword element of the destination is updated according to the writemask.\r\nCompiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the\r\nopcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations\r\ninvolving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction\r\ncolumn.\r\n\r\nOperation\r\nIn the operations below, \"*\" and \"+\" symbols represent multiplication and addition with infinite precision inputs and outputs (no\r\nrounding).\r\n\r\nVFNMADD132SS DEST, SRC2, SRC3 (EVEX encoded version)\r\nIF (EVEX.b = 1) and SRC3 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[31:0] <- RoundFPControl(-(DEST[31:0]*SRC3[31:0]) + SRC2[31:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[31:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:32] <- DEST[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVFNMADD213SS DEST, SRC2, SRC3 (EVEX encoded version)\r\nIF (EVEX.b = 1) and SRC3 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[31:0] <- RoundFPControl(-(SRC2[31:0]*DEST[31:0]) + SRC3[31:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[31:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:32] <- DEST[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFNMADD231SS DEST, SRC2, SRC3 (EVEX encoded version)\r\nIF (EVEX.b = 1) and SRC3 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[31:0] <- RoundFPControl(-(SRC2[31:0]*SRC3[63:0]) + DEST[31:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[31:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:32] <- DEST[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVFNMADD132SS DEST, SRC2, SRC3 (VEX encoded version)\r\nDEST[31:0] <-RoundFPControl_MXCSR(- (DEST[31:0]*SRC3[31:0]) + SRC2[31:0])\r\nDEST[127:32] <-DEST[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVFNMADD213SS DEST, SRC2, SRC3 (VEX encoded version)\r\nDEST[31:0] <-RoundFPControl_MXCSR(- (SRC2[31:0]*DEST[31:0]) + SRC3[31:0])\r\nDEST[127:32] <-DEST[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVFNMADD231SS DEST, SRC2, SRC3 (VEX encoded version)\r\nDEST[31:0] <-RoundFPControl_MXCSR(- (SRC2[31:0]*SRC3[31:0]) + DEST[31:0])\r\nDEST[127:32] <-DEST[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVFNMADDxxxSS __m128 _mm_fnmadd_round_ss(__m128 a, __m128 b, __m128 c, int r);\r\nVFNMADDxxxSS __m128 _mm_mask_fnmadd_ss(__m128 a, __mmask8 k, __m128 b, __m128 c);\r\nVFNMADDxxxSS __m128 _mm_maskz_fnmadd_ss(__mmask8 k, __m128 a, __m128 b, __m128 c);\r\nVFNMADDxxxSS __m128 _mm_mask3_fnmadd_ss(__m128 a, __m128 b, __m128 c, __mmask8 k);\r\nVFNMADDxxxSS __m128 _mm_mask_fnmadd_round_ss(__m128 a, __mmask8 k, __m128 b, __m128 c, int r);\r\nVFNMADDxxxSS __m128 _mm_maskz_fnmadd_round_ss(__mmask8 k, __m128 a, __m128 b, __m128 c, int r);\r\nVFNMADDxxxSS __m128 _mm_mask3_fnmadd_round_ss(__m128 a, __m128 b, __m128 c, __mmask8 k, int r);\r\nVFNMADDxxxSS __m128 _mm_fnmadd_ss (__m128 a, __m128 b, __m128 c);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3.\r\nEVEX-encoded instructions, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VFNMADD132SS"
},
{
"description": "-R:VFNMADD132PD",
"mnem": "VFNMADD213PD"
},
{
"description": "-R:VFNMADD132PS",
"mnem": "VFNMADD213PS"
},
{
"description": "-R:VFNMADD132SD",
"mnem": "VFNMADD213SD"
},
{
"description": "-R:VFNMADD132SS",
"mnem": "VFNMADD213SS"
},
{
"description": "-R:VFNMADD132PD",
"mnem": "VFNMADD231PD"
},
{
"description": "-R:VFNMADD132PS",
"mnem": "VFNMADD231PS"
},
{
"description": "-R:VFNMADD132SD",
"mnem": "VFNMADD231SD"
},
{
"description": "-R:VFNMADD132SS",
"mnem": "VFNMADD231SS"
},
{
"description": "VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD-Fused Negative Multiply-Subtract of\r\nPacked Double-Precision Floating-Point Values\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.NDS.128.66.0F38.W1 9E /r RVM V/V FMA Multiply packed double-precision floating-point values from\r\n VFNMSUB132PD xmm1, xmm2, xmm1 and xmm3/mem, negate the multiplication result\r\n xmm3/m128 and subtract xmm2 and put result in xmm1.\r\n VEX.NDS.128.66.0F38.W1 AE /r RVM V/V FMA Multiply packed double-precision floating-point values from\r\n VFNMSUB213PD xmm1, xmm2, xmm1 and xmm2, negate the multiplication result and\r\n xmm3/m128 subtract xmm3/mem and put result in xmm1.\r\n VEX.NDS.128.66.0F38.W1 BE /r RVM V/V FMA Multiply packed double-precision floating-point values from\r\n VFNMSUB231PD xmm1, xmm2, xmm2 and xmm3/mem, negate the multiplication result\r\n xmm3/m128 and subtract xmm1 and put result in xmm1.\r\n VEX.NDS.256.66.0F38.W1 9E /r RVM V/V FMA Multiply packed double-precision floating-point values from\r\n VFNMSUB132PD ymm1, ymm2, ymm1 and ymm3/mem, negate the multiplication result and\r\n ymm3/m256 subtract ymm2 and put result in ymm1.\r\n VEX.NDS.256.66.0F38.W1 AE /r RVM V/V FMA Multiply packed double-precision floating-point values from\r\n VFNMSUB213PD ymm1, ymm2, ymm1 and ymm2, negate the multiplication result and\r\n ymm3/m256 subtract ymm3/mem and put result in ymm1.\r\n VEX.NDS.256.66.0F38.W1 BE /r RVM V/V FMA Multiply packed double-precision floating-point values from\r\n VFNMSUB231PD ymm1, ymm2, ymm2 and ymm3/mem, negate the multiplication result and\r\n ymm3/m256 subtract ymm1 and put result in ymm1.\r\n EVEX.NDS.128.66.0F38.W1 9E /r FV V/V AVX512VL Multiply packed double-precision floating-point values from\r\n VFNMSUB132PD xmm1 {k1}{z}, AVX512F xmm1 and xmm3/m128/m64bcst, negate the\r\n xmm2, xmm3/m128/m64bcst multiplication result and subtract xmm2 and put result in\r\n xmm1.\r\n EVEX.NDS.128.66.0F38.W1 AE /r FV V/V AVX512VL Multiply packed double-precision floating-point values from\r\n VFNMSUB213PD xmm1 {k1}{z}, AVX512F xmm1 and xmm2, negate the multiplication result and\r\n xmm2, xmm3/m128/m64bcst subtract xmm3/m128/m64bcst and put result in xmm1.\r\n EVEX.NDS.128.66.0F38.W1 BE /r FV V/V AVX512VL Multiply packed double-precision floating-point values from\r\n VFNMSUB231PD xmm1 {k1}{z}, AVX512F xmm2 and xmm3/m128/m64bcst, negate the\r\n xmm2, xmm3/m128/m64bcst multiplication result and subtract xmm1 and put result in\r\n xmm1.\r\n EVEX.NDS.256.66.0F38.W1 9E /r FV V/V AVX512VL Multiply packed double-precision floating-point values from\r\n VFNMSUB132PD ymm1 {k1}{z}, AVX512F ymm1 and ymm3/m256/m64bcst, negate the\r\n ymm2, ymm3/m256/m64bcst multiplication result and subtract ymm2 and put result in\r\n ymm1.\r\n EVEX.NDS.256.66.0F38.W1 AE /r FV V/V AVX512VL Multiply packed double-precision floating-point values from\r\n VFNMSUB213PD ymm1 {k1}{z}, AVX512F ymm1 and ymm2, negate the multiplication result and\r\n ymm2, ymm3/m256/m64bcst subtract ymm3/m256/m64bcst and put result in ymm1.\r\n EVEX.NDS.256.66.0F38.W1 BE /r FV V/V AVX512VL Multiply packed double-precision floating-point values from\r\n VFNMSUB231PD ymm1 {k1}{z}, AVX512F ymm2 and ymm3/m256/m64bcst, negate the\r\n ymm2, ymm3/m256/m64bcst multiplication result and subtract ymm1 and put result in\r\n ymm1.\r\n EVEX.NDS.512.66.0F38.W1 9E /r FV V/V AVX512F Multiply packed double-precision floating-point values from\r\n VFNMSUB132PD zmm1 {k1}{z}, zmm1 and zmm3/m512/m64bcst, negate the multiplication\r\n zmm2, zmm3/m512/m64bcst{er} result and subtract zmm2 and put result in zmm1.\r\n EVEX.NDS.512.66.0F38.W1 AE /r FV V/V AVX512F Multiply packed double-precision floating-point values from\r\n VFNMSUB213PD zmm1 {k1}{z}, zmm1 and zmm2, negate the multiplication result and\r\n zmm2, zmm3/m512/m64bcst{er} subtract zmm3/m512/m64bcst and put result in zmm1.\r\n EVEX.NDS.512.66.0F38.W1 BE /r FV V/V AVX512F Multiply packed double-precision floating-point values from\r\n VFNMSUB231PD zmm1 {k1}{z}, zmm2 and zmm3/m512/m64bcst, negate the multiplication\r\n zmm2, zmm3/m512/m64bcst{er} result and subtract zmm1 and put result in zmm1.\r\n\r\n\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nVFNMSUB132PD: Multiplies the two, four or eight packed double-precision floating-point values from the first\r\nsource operand to the two, four or eight packed double-precision floating-point values in the third source operand.\r\nFrom negated infinite precision intermediate results, subtracts the two, four or eight packed double-precision\r\nfloating-point values in the second source operand, performs rounding and stores the resulting two, four or eight\r\npacked double-precision floating-point values to the destination operand (first source operand).\r\nVFNMSUB213PD: Multiplies the two, four or eight packed double-precision floating-point values from the second\r\nsource operand to the two, four or eight packed double-precision floating-point values in the first source operand.\r\nFrom negated infinite precision intermediate results, subtracts the two, four or eight packed double-precision\r\nfloating-point values in the third source operand, performs rounding and stores the resulting two, four or eight\r\npacked double-precision floating-point values to the destination operand (first source operand).\r\nVFNMSUB231PD: Multiplies the two, four or eight packed double-precision floating-point values from the second\r\nsource to the two, four or eight packed double-precision floating-point values in the third source operand. From\r\nnegated infinite precision intermediate results, subtracts the two, four or eight packed double-precision floating-\r\npoint values in the first source operand, performs rounding and stores the resulting two, four or eight packed\r\ndouble-precision floating-point values to the destination operand (first source operand).\r\nEVEX encoded versions: The destination operand (also first source operand) and the second source operand are\r\nZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-\r\ntion or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is condition-\r\nally updated with write mask k1.\r\nVEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in\r\nreg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a\r\nYMM register or a 256-bit memory location and encoded in rm_field.\r\nVEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in\r\nreg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a\r\nXMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination\r\nregister are zeroed.\r\n\r\nOperation\r\nIn the operations below, \"*\" and \"-\" symbols represent multiplication and subtraction with infinite precision inputs and outputs (no\r\nrounding).\r\n\r\nVFNMSUB132PD DEST, SRC2, SRC3 (VEX encoded version)\r\nIF (VEX.128) THEN\r\n MAXNUM <-2\r\nELSEIF (VEX.256)\r\n MAXNUM <- 4\r\nFI\r\nFor i = 0 to MAXNUM-1 {\r\n n <- 64*i;\r\n DEST[n+63:n] <- RoundFPControl_MXCSR( - (DEST[n+63:n]*SRC3[n+63:n]) - SRC2[n+63:n])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <- 0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\n\r\n\r\n\r\nVFNMSUB213PD DEST, SRC2, SRC3 (VEX encoded version)\r\nIF (VEX.128) THEN\r\n MAXNUM <-2\r\nELSEIF (VEX.256)\r\n MAXNUM <- 4\r\nFI\r\nFor i = 0 to MAXNUM-1 {\r\n n <- 64*i;\r\n DEST[n+63:n] <- RoundFPControl_MXCSR( - (SRC2[n+63:n]*DEST[n+63:n]) - SRC3[n+63:n])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <- 0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\nVFNMSUB231PD DEST, SRC2, SRC3 (VEX encoded version)\r\nIF (VEX.128) THEN\r\n MAXNUM <-2\r\nELSEIF (VEX.256)\r\n MAXNUM <- 4\r\nFI\r\nFor i = 0 to MAXNUM-1 {\r\n n <- 64*i;\r\n DEST[n+63:n] <- RoundFPControl_MXCSR( - (SRC2[n+63:n]*SRC3[n+63:n]) - DEST[n+63:n])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <- 0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\nVFNMSUB132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <-\r\n RoundFPControl(-(DEST[i+63:i]*SRC3[i+63:i]) - SRC2[i+63:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\nVFNMSUB132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(-(DEST[i+63:i]*SRC3[63:0]) - SRC2[i+63:i])\r\n ELSE\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(-(DEST[i+63:i]*SRC3[i+63:i]) - SRC2[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVFNMSUB213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <-\r\n RoundFPControl(-(SRC2[i+63:i]*DEST[i+63:i]) - SRC3[i+63:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFNMSUB213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(-(SRC2[i+63:i]*DEST[i+63:i]) - SRC3[63:0])\r\n ELSE\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(-(SRC2[i+63:i]*DEST[i+63:i]) - SRC3[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVFNMSUB231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <-\r\n RoundFPControl(-(SRC2[i+63:i]*SRC3[i+63:i]) - DEST[i+63:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFNMSUB231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(-(SRC2[i+63:i]*SRC3[63:0]) - DEST[i+63:i])\r\n ELSE\r\n DEST[i+63:i] <-\r\n RoundFPControl_MXCSR(-(SRC2[i+63:i]*SRC3[i+63:i]) - DEST[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVFNMSUBxxxPD __m512d _mm512_fnmsub_pd(__m512d a, __m512d b, __m512d c);\r\nVFNMSUBxxxPD __m512d _mm512_fnmsub_round_pd(__m512d a, __m512d b, __m512d c, int r);\r\nVFNMSUBxxxPD __m512d _mm512_mask_fnmsub_pd(__m512d a, __mmask8 k, __m512d b, __m512d c);\r\nVFNMSUBxxxPD __m512d _mm512_maskz_fnmsub_pd(__mmask8 k, __m512d a, __m512d b, __m512d c);\r\nVFNMSUBxxxPD __m512d _mm512_mask3_fnmsub_pd(__m512d a, __m512d b, __m512d c, __mmask8 k);\r\nVFNMSUBxxxPD __m512d _mm512_mask_fnmsub_round_pd(__m512d a, __mmask8 k, __m512d b, __m512d c, int r);\r\nVFNMSUBxxxPD __m512d _mm512_maskz_fnmsub_round_pd(__mmask8 k, __m512d a, __m512d b, __m512d c, int r);\r\nVFNMSUBxxxPD __m512d _mm512_mask3_fnmsub_round_pd(__m512d a, __m512d b, __m512d c, __mmask8 k, int r);\r\nVFNMSUBxxxPD __m256d _mm256_mask_fnmsub_pd(__m256d a, __mmask8 k, __m256d b, __m256d c);\r\nVFNMSUBxxxPD __m256d _mm256_maskz_fnmsub_pd(__mmask8 k, __m256d a, __m256d b, __m256d c);\r\nVFNMSUBxxxPD __m256d _mm256_mask3_fnmsub_pd(__m256d a, __m256d b, __m256d c, __mmask8 k);\r\nVFNMSUBxxxPD __m128d _mm_mask_fnmsub_pd(__m128d a, __mmask8 k, __m128d b, __m128d c);\r\nVFNMSUBxxxPD __m128d _mm_maskz_fnmsub_pd(__mmask8 k, __m128d a, __m128d b, __m128d c);\r\nVFNMSUBxxxPD __m128d _mm_mask3_fnmsub_pd(__m128d a, __m128d b, __m128d c, __mmask8 k);\r\nVFNMSUBxxxPD __m128d _mm_fnmsub_pd (__m128d a, __m128d b, __m128d c);\r\nVFNMSUBxxxPD __m256d _mm256_fnmsub_pd (__m256d a, __m256d b, __m256d c);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2.\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VFNMSUB132PD"
},
{
"description": "VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS-Fused Negative Multiply-Subtract of\r\nPacked Single-Precision Floating-Point Values\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.NDS.128.66.0F38.W0 9E /r RVM V/V FMA Multiply packed single-precision floating-point values from\r\n VFNMSUB132PS xmm1, xmm2, xmm1 and xmm3/mem, negate the multiplication result and\r\n xmm3/m128 subtract xmm2 and put result in xmm1.\r\n VEX.NDS.128.66.0F38.W0 AE /r RVM V/V FMA Multiply packed single-precision floating-point values from\r\n VFNMSUB213PS xmm1, xmm2, xmm1 and xmm2, negate the multiplication result and\r\n xmm3/m128 subtract xmm3/mem and put result in xmm1.\r\n VEX.NDS.128.66.0F38.W0 BE /r RVM V/V FMA Multiply packed single-precision floating-point values from\r\n VFNMSUB231PS xmm1, xmm2, xmm2 and xmm3/mem, negate the multiplication result and\r\n xmm3/m128 subtract xmm1 and put result in xmm1.\r\n VEX.NDS.256.66.0F38.W0 9E /r RVM V/V FMA Multiply packed single-precision floating-point values from\r\n VFNMSUB132PS ymm1, ymm2, ymm1 and ymm3/mem, negate the multiplication result and\r\n ymm3/m256 subtract ymm2 and put result in ymm1.\r\n VEX.NDS.256.66.0F38.W0 AE /r RVM V/V FMA Multiply packed single-precision floating-point values from\r\n VFNMSUB213PS ymm1, ymm2, ymm1 and ymm2, negate the multiplication result and\r\n ymm3/m256 subtract ymm3/mem and put result in ymm1.\r\n VEX.NDS.256.66.0F38.0 BE /r RVM V/V FMA Multiply packed single-precision floating-point values from\r\n VFNMSUB231PS ymm1, ymm2, ymm2 and ymm3/mem, negate the multiplication result and\r\n ymm3/m256 subtract ymm1 and put result in ymm1.\r\n EVEX.NDS.128.66.0F38.W0 9E /r FV V/V AVX512VL Multiply packed single-precision floating-point values from\r\n VFNMSUB132PS xmm1 {k1}{z}, AVX512F xmm1 and xmm3/m128/m32bcst, negate the multiplication\r\n xmm2, xmm3/m128/m32bcst result and subtract xmm2 and put result in xmm1.\r\n EVEX.NDS.128.66.0F38.W0 AE /r FV V/V AVX512VL Multiply packed single-precision floating-point values from\r\n VFNMSUB213PS xmm1 {k1}{z}, AVX512F xmm1 and xmm2, negate the multiplication result and\r\n xmm2, xmm3/m128/m32bcst subtract xmm3/m128/m32bcst and put result in xmm1.\r\n EVEX.NDS.128.66.0F38.W0 BE /r FV V/V AVX512VL Multiply packed single-precision floating-point values from\r\n VFNMSUB231PS xmm1 {k1}{z}, AVX512F xmm2 and xmm3/m128/m32bcst, negate the multiplication\r\n xmm2, xmm3/m128/m32bcst result subtract add to xmm1 and put result in xmm1.\r\n EVEX.NDS.256.66.0F38.W0 9E /r FV V/V AVX512VL Multiply packed single-precision floating-point values from\r\n VFNMSUB132PS ymm1 {k1}{z}, AVX512F ymm1 and ymm3/m256/m32bcst, negate the multiplication\r\n ymm2, ymm3/m256/m32bcst result and subtract ymm2 and put result in ymm1.\r\n EVEX.NDS.256.66.0F38.W0 AE /r FV V/V AVX512VL Multiply packed single-precision floating-point values from\r\n VFNMSUB213PS ymm1 {k1}{z}, AVX512F ymm1 and ymm2, negate the multiplication result and\r\n ymm2, ymm3/m256/m32bcst subtract ymm3/m256/m32bcst and put result in ymm1.\r\n EVEX.NDS.256.66.0F38.W0 BE /r FV V/V AVX512VL Multiply packed single-precision floating-point values from\r\n VFNMSUB231PS ymm1 {k1}{z}, AVX512F ymm2 and ymm3/m256/m32bcst, negate the multiplication\r\n ymm2, ymm3/m256/m32bcst result subtract add to ymm1 and put result in ymm1.\r\n EVEX.NDS.512.66.0F38.W0 9E /r FV V/V AVX512F Multiply packed single-precision floating-point values from\r\n VFNMSUB132PS zmm1 {k1}{z}, zmm1 and zmm3/m512/m32bcst, negate the multiplication\r\n zmm2, zmm3/m512/m32bcst{er} result and subtract zmm2 and put result in zmm1.\r\n EVEX.NDS.512.66.0F38.W0 AE /r FV V/V AVX512F Multiply packed single-precision floating-point values from\r\n VFNMSUB213PS zmm1 {k1}{z}, zmm1 and zmm2, negate the multiplication result and\r\n zmm2, zmm3/m512/m32bcst{er} subtract zmm3/m512/m32bcst and put result in zmm1.\r\n EVEX.NDS.512.66.0F38.W0 BE /r FV V/V AVX512F Multiply packed single-precision floating-point values from\r\n VFNMSUB231PS zmm1 {k1}{z}, zmm2 and zmm3/m512/m32bcst, negate the multiplication\r\n zmm2, zmm3/m512/m32bcst{er} result subtract add to zmm1 and put result in zmm1.\r\n\r\n\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nVFNMSUB132PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the first\r\nsource operand to the four, eight or sixteen packed single-precision floating-point values in the third source\r\noperand. From negated infinite precision intermediate results, subtracts the four, eight or sixteen packed single-\r\nprecision floating-point values in the second source operand, performs rounding and stores the resulting four, eight\r\nor sixteen packed single-precision floating-point values to the destination operand (first source operand).\r\nVFNMSUB213PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second\r\nsource operand to the four, eight or sixteen packed single-precision floating-point values in the first source\r\noperand. From negated infinite precision intermediate results, subtracts the four, eight or sixteen packed single-\r\nprecision floating-point values in the third source operand, performs rounding and stores the resulting four, eight\r\nor sixteen packed single-precision floating-point values to the destination operand (first source operand).\r\nVFNMSUB231PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second\r\nsource to the four, eight or sixteen packed single-precision floating-point values in the third source operand. From\r\nnegated infinite precision intermediate results, subtracts the four, eight or sixteen packed single-precision floating-\r\npoint values in the first source operand, performs rounding and stores the resulting four, eight or sixteen packed\r\nsingle-precision floating-point values to the destination operand (first source operand).\r\nEVEX encoded versions: The destination operand (also first source operand) and the second source operand are\r\nZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-\r\ntion or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is condition-\r\nally updated with write mask k1.\r\nVEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in\r\nreg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a\r\nYMM register or a 256-bit memory location and encoded in rm_field.\r\nVEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in\r\nreg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a\r\nXMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination\r\nregister are zeroed.\r\n\r\nOperation\r\nIn the operations below, \"*\" and \"-\" symbols represent multiplication and subtraction with infinite precision inputs and outputs (no\r\nrounding).\r\n\r\nVFNMSUB132PS DEST, SRC2, SRC3 (VEX encoded version)\r\nIF (VEX.128) THEN\r\n MAXNUM <-2\r\nELSEIF (VEX.256)\r\n MAXNUM <- 4\r\nFI\r\nFor i = 0 to MAXNUM-1 {\r\n n <- 32*i;\r\n DEST[n+31:n] <- RoundFPControl_MXCSR( - (DEST[n+31:n]*SRC3[n+31:n]) - SRC2[n+31:n])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <- 0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\n\r\n\r\n\r\nVFNMSUB213PS DEST, SRC2, SRC3 (VEX encoded version)\r\nIF (VEX.128) THEN\r\n MAXNUM <-2\r\nELSEIF (VEX.256)\r\n MAXNUM <- 4\r\nFI\r\nFor i = 0 to MAXNUM-1 {\r\n n <- 32*i;\r\n DEST[n+31:n] <- RoundFPControl_MXCSR( - (SRC2[n+31:n]*DEST[n+31:n]) - SRC3[n+31:n])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <- 0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\nVFNMSUB231PS DEST, SRC2, SRC3 (VEX encoded version)\r\nIF (VEX.128) THEN\r\n MAXNUM <-2\r\nELSEIF (VEX.256)\r\n MAXNUM <- 4\r\nFI\r\nFor i = 0 to MAXNUM-1 {\r\n n <- 32*i;\r\n DEST[n+31:n] <- RoundFPControl_MXCSR( - (SRC2[n+31:n]*SRC3[n+31:n]) - DEST[n+31:n])\r\n}\r\nIF (VEX.128) THEN\r\n DEST[MAX_VL-1:128] <- 0\r\nELSEIF (VEX.256)\r\n DEST[MAX_VL-1:256] <- 0\r\nFI\r\n\r\nVFNMSUB132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <-\r\n RoundFPControl(-(DEST[i+31:i]*SRC3[i+31:i]) - SRC2[i+31:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\nVFNMSUB132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(-(DEST[i+31:i]*SRC3[31:0]) - SRC2[i+31:i])\r\n ELSE\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(-(DEST[i+31:i]*SRC3[i+31:i]) - SRC2[i+31:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVFNMSUB213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(-(SRC2[i+31:i]*DEST[i+31:i]) - SRC3[i+31:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFNMSUB213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(-(SRC2[i+31:i]*DEST[i+31:i]) - SRC3[31:0])\r\n ELSE\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(-(SRC2[i+31:i]*DEST[i+31:i]) - SRC3[i+31:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVFNMSUB231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(-(SRC2[i+31:i]*SRC3[i+31:i]) - DEST[i+31:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVFNMSUB231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n\r\n\r\n\r\n THEN\r\n IF (EVEX.b = 1)\r\n THEN\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(-(SRC2[i+31:i]*SRC3[31:0]) - DEST[i+31:i])\r\n ELSE\r\n DEST[i+31:i] <-\r\n RoundFPControl_MXCSR(-(SRC2[i+31:i]*SRC3[i+31:i]) - DEST[i+31:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVFNMSUBxxxPS __m512 _mm512_fnmsub_ps(__m512 a, __m512 b, __m512 c);\r\nVFNMSUBxxxPS __m512 _mm512_fnmsub_round_ps(__m512 a, __m512 b, __m512 c, int r);\r\nVFNMSUBxxxPS __m512 _mm512_mask_fnmsub_ps(__m512 a, __mmask16 k, __m512 b, __m512 c);\r\nVFNMSUBxxxPS __m512 _mm512_maskz_fnmsub_ps(__mmask16 k, __m512 a, __m512 b, __m512 c);\r\nVFNMSUBxxxPS __m512 _mm512_mask3_fnmsub_ps(__m512 a, __m512 b, __m512 c, __mmask16 k);\r\nVFNMSUBxxxPS __m512 _mm512_mask_fnmsub_round_ps(__m512 a, __mmask16 k, __m512 b, __m512 c, int r);\r\nVFNMSUBxxxPS __m512 _mm512_maskz_fnmsub_round_ps(__mmask16 k, __m512 a, __m512 b, __m512 c, int r);\r\nVFNMSUBxxxPS __m512 _mm512_mask3_fnmsub_round_ps(__m512 a, __m512 b, __m512 c, __mmask16 k, int r);\r\nVFNMSUBxxxPS __m256 _mm256_mask_fnmsub_ps(__m256 a, __mmask8 k, __m256 b, __m256 c);\r\nVFNMSUBxxxPS __m256 _mm256_maskz_fnmsub_ps(__mmask8 k, __m256 a, __m256 b, __m256 c);\r\nVFNMSUBxxxPS __m256 _mm256_mask3_fnmsub_ps(__m256 a, __m256 b, __m256 c, __mmask8 k);\r\nVFNMSUBxxxPS __m128 _mm_mask_fnmsub_ps(__m128 a, __mmask8 k, __m128 b, __m128 c);\r\nVFNMSUBxxxPS __m128 _mm_maskz_fnmsub_ps(__mmask8 k, __m128 a, __m128 b, __m128 c);\r\nVFNMSUBxxxPS __m128 _mm_mask3_fnmsub_ps(__m128 a, __m128 b, __m128 c, __mmask8 k);\r\nVFNMSUBxxxPS __m128 _mm_fnmsub_ps (__m128 a, __m128 b, __m128 c);\r\nVFNMSUBxxxPS __m256 _mm256_fnmsub_ps (__m256 a, __m256 b, __m256 c);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 2.\r\nEVEX-encoded instructions, see Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VFNMSUB132PS"
},
{
"description": "VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD-Fused Negative Multiply-Subtract of\r\nScalar Double-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.DDS.LIG.66.0F38.W1 9F /r RVM V/V FMA Multiply scalar double-precision floating-point value from\r\n VFNMSUB132SD xmm1, xmm2, xmm1 and xmm3/mem, negate the multiplication result and\r\n xmm3/m64 subtract xmm2 and put result in xmm1.\r\n VEX.DDS.LIG.66.0F38.W1 AF /r RVM V/V FMA Multiply scalar double-precision floating-point value from\r\n VFNMSUB213SD xmm1, xmm2, xmm1 and xmm2, negate the multiplication result and\r\n xmm3/m64 subtract xmm3/mem and put result in xmm1.\r\n VEX.DDS.LIG.66.0F38.W1 BF /r RVM V/V FMA Multiply scalar double-precision floating-point value from\r\n VFNMSUB231SD xmm1, xmm2, xmm2 and xmm3/mem, negate the multiplication result and\r\n xmm3/m64 subtract xmm1 and put result in xmm1.\r\n EVEX.DDS.LIG.66.0F38.W1 9F /r T1S V/V AVX512F Multiply scalar double-precision floating-point value from\r\n VFNMSUB132SD xmm1 {k1}{z}, xmm1 and xmm3/m64, negate the multiplication result and\r\n xmm2, xmm3/m64{er} subtract xmm2 and put result in xmm1.\r\n EVEX.DDS.LIG.66.0F38.W1 AF /r T1S V/V AVX512F Multiply scalar double-precision floating-point value from\r\n VFNMSUB213SD xmm1 {k1}{z}, xmm1 and xmm2, negate the multiplication result and\r\n xmm2, xmm3/m64{er} subtract xmm3/m64 and put result in xmm1.\r\n EVEX.DDS.LIG.66.0F38.W1 BF /r T1S V/V AVX512F Multiply scalar double-precision floating-point value from\r\n VFNMSUB231SD xmm1 {k1}{z}, xmm2 and xmm3/m64, negate the multiplication result and\r\n xmm2, xmm3/m64{er} subtract xmm1 and put result in xmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n T1S ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nVFNMSUB132SD: Multiplies the low packed double-precision floating-point value from the first source operand to\r\nthe low packed double-precision floating-point value in the third source operand. From negated infinite precision\r\nintermediate result, subtracts the low double-precision floating-point value in the second source operand, performs\r\nrounding and stores the resulting packed double-precision floating-point value to the destination operand (first\r\nsource operand).\r\nVFNMSUB213SD: Multiplies the low packed double-precision floating-point value from the second source operand\r\nto the low packed double-precision floating-point value in the first source operand. From negated infinite precision\r\nintermediate result, subtracts the low double-precision floating-point value in the third source operand, performs\r\nrounding and stores the resulting packed double-precision floating-point value to the destination operand (first\r\nsource operand).\r\nVFNMSUB231SD: Multiplies the low packed double-precision floating-point value from the second source to the low\r\npacked double-precision floating-point value in the third source operand. From negated infinite precision interme-\r\ndiate result, subtracts the low double-precision floating-point value in the first source operand, performs rounding\r\nand stores the resulting packed double-precision floating-point value to the destination operand (first source\r\noperand).\r\nVEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field.\r\nThe second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field.\r\nBits 127:64 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.\r\n\r\n\r\n\r\n\r\n\r\nEVEX encoded version: The low quadword element of the destination is updated according to the writemask.\r\nCompiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the\r\nopcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations\r\ninvolving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction\r\ncolumn.\r\n\r\nOperation\r\nIn the operations below, \"*\" and \"-\" symbols represent multiplication and subtraction with infinite precision inputs and outputs (no\r\nrounding).\r\n\r\nVFNMSUB132SD DEST, SRC2, SRC3 (EVEX encoded version)\r\nIF (EVEX.b = 1) and SRC3 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[63:0] <- RoundFPControl(-(DEST[63:0]*SRC3[63:0]) - SRC2[63:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[63:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:64] <- DEST[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVFNMSUB213SD DEST, SRC2, SRC3 (EVEX encoded version)\r\nIF (EVEX.b = 1) and SRC3 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[63:0] <- RoundFPControl(-(SRC2[63:0]*DEST[63:0]) - SRC3[63:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[63:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:64] <- DEST[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFNMSUB231SD DEST, SRC2, SRC3 (EVEX encoded version)\r\nIF (EVEX.b = 1) and SRC3 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[63:0] <- RoundFPControl(-(SRC2[63:0]*SRC3[63:0]) - DEST[63:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[63:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:64] <- DEST[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVFNMSUB132SD DEST, SRC2, SRC3 (VEX encoded version)\r\nDEST[63:0] <-RoundFPControl_MXCSR(- (DEST[63:0]*SRC3[63:0]) - SRC2[63:0])\r\nDEST[127:64] <-DEST[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVFNMSUB213SD DEST, SRC2, SRC3 (VEX encoded version)\r\nDEST[63:0] <-RoundFPControl_MXCSR(- (SRC2[63:0]*DEST[63:0]) - SRC3[63:0])\r\nDEST[127:64] <-DEST[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVFNMSUB231SD DEST, SRC2, SRC3 (VEX encoded version)\r\nDEST[63:0] <-RoundFPControl_MXCSR(- (SRC2[63:0]*SRC3[63:0]) - DEST[63:0])\r\nDEST[127:64] <-DEST[127:64]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVFNMSUBxxxSD __m128d _mm_fnmsub_round_sd(__m128d a, __m128d b, __m128d c, int r);\r\nVFNMSUBxxxSD __m128d _mm_mask_fnmsub_sd(__m128d a, __mmask8 k, __m128d b, __m128d c);\r\nVFNMSUBxxxSD __m128d _mm_maskz_fnmsub_sd(__mmask8 k, __m128d a, __m128d b, __m128d c);\r\nVFNMSUBxxxSD __m128d _mm_mask3_fnmsub_sd(__m128d a, __m128d b, __m128d c, __mmask8 k);\r\nVFNMSUBxxxSD __m128d _mm_mask_fnmsub_round_sd(__m128d a, __mmask8 k, __m128d b, __m128d c, int r);\r\nVFNMSUBxxxSD __m128d _mm_maskz_fnmsub_round_sd(__mmask8 k, __m128d a, __m128d b, __m128d c, int r);\r\nVFNMSUBxxxSD __m128d _mm_mask3_fnmsub_round_sd(__m128d a, __m128d b, __m128d c, __mmask8 k, int r);\r\nVFNMSUBxxxSD __m128d _mm_fnmsub_sd (__m128d a, __m128d b, __m128d c);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3.\r\nEVEX-encoded instructions, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VFNMSUB132SD"
},
{
"description": "VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS-Fused Negative Multiply-Subtract of\r\nScalar Single-Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.DDS.LIG.66.0F38.W0 9F /r RVM V/V FMA Multiply scalar single-precision floating-point value from\r\n VFNMSUB132SS xmm1, xmm2, xmm1 and xmm3/m32, negate the multiplication result and\r\n xmm3/m32 subtract xmm2 and put result in xmm1.\r\n VEX.DDS.LIG.66.0F38.W0 AF /r RVM V/V FMA Multiply scalar single-precision floating-point value from\r\n VFNMSUB213SS xmm1, xmm2, xmm1 and xmm2, negate the multiplication result and\r\n xmm3/m32 subtract xmm3/m32 and put result in xmm1.\r\n VEX.DDS.LIG.66.0F38.W0 BF /r RVM V/V FMA Multiply scalar single-precision floating-point value from\r\n VFNMSUB231SS xmm1, xmm2, xmm2 and xmm3/m32, negate the multiplication result and\r\n xmm3/m32 subtract xmm1 and put result in xmm1.\r\n EVEX.DDS.LIG.66.0F38.W0 9F /r T1S V/V AVX512F Multiply scalar single-precision floating-point value from\r\n VFNMSUB132SS xmm1 {k1}{z}, xmm1 and xmm3/m32, negate the multiplication result and\r\n xmm2, xmm3/m32{er} subtract xmm2 and put result in xmm1.\r\n EVEX.DDS.LIG.66.0F38.W0 AF /r T1S V/V AVX512F Multiply scalar single-precision floating-point value from\r\n VFNMSUB213SS xmm1 {k1}{z}, xmm1 and xmm2, negate the multiplication result and\r\n xmm2, xmm3/m32{er} subtract xmm3/m32 and put result in xmm1.\r\n EVEX.DDS.LIG.66.0F38.W0 BF /r T1S V/V AVX512F Multiply scalar single-precision floating-point value from\r\n VFNMSUB231SS xmm1 {k1}{z}, xmm2 and xmm3/m32, negate the multiplication result and\r\n xmm2, xmm3/m32{er} subtract xmm1 and put result in xmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n T1S ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nVFNMSUB132SS: Multiplies the low packed single-precision floating-point value from the first source operand to\r\nthe low packed single-precision floating-point value in the third source operand. From negated infinite precision\r\nintermediate result, the low single-precision floating-point value in the second source operand, performs rounding\r\nand stores the resulting packed single-precision floating-point value to the destination operand (first source\r\noperand).\r\nVFNMSUB213SS: Multiplies the low packed single-precision floating-point value from the second source operand to\r\nthe low packed single-precision floating-point value in the first source operand. From negated infinite precision\r\nintermediate result, the low single-precision floating-point value in the third source operand, performs rounding\r\nand stores the resulting packed single-precision floating-point value to the destination operand (first source\r\noperand).\r\nVFNMSUB231SS: Multiplies the low packed single-precision floating-point value from the second source to the low\r\npacked single-precision floating-point value in the third source operand. From negated infinite precision interme-\r\ndiate result, the low single-precision floating-point value in the first source operand, performs rounding and stores\r\nthe resulting packed single-precision floating-point value to the destination operand (first source operand).\r\nVEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field.\r\nThe second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field.\r\nBits 127:32 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.\r\nEVEX encoded version: The low doubleword element of the destination is updated according to the writemask.\r\nCompiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the\r\nopcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations\r\ninvolving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction\r\ncolumn.\r\n\r\n\r\n\r\nOperation\r\nIn the operations below, \"*\" and \"-\" symbols represent multiplication and subtraction with infinite precision inputs and outputs (no\r\nrounding).\r\n\r\nVFNMSUB132SS DEST, SRC2, SRC3 (EVEX encoded version)\r\nIF (EVEX.b = 1) and SRC3 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[31:0] <- RoundFPControl(-(DEST[31:0]*SRC3[31:0]) - SRC2[31:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[31:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:32] <- DEST[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVFNMSUB213SS DEST, SRC2, SRC3 (EVEX encoded version)\r\nIF (EVEX.b = 1) and SRC3 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[31:0] <- RoundFPControl(-(SRC2[31:0]*DEST[31:0]) - SRC3[31:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[31:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:32] <- DEST[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVFNMSUB231SS DEST, SRC2, SRC3 (EVEX encoded version)\r\nIF (EVEX.b = 1) and SRC3 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] or *no writemask*\r\n THEN DEST[31:0] <- RoundFPControl(-(SRC2[31:0]*SRC3[63:0]) - DEST[31:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[31:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:32] <- DEST[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nVFNMSUB132SS DEST, SRC2, SRC3 (VEX encoded version)\r\nDEST[31:0] <-RoundFPControl_MXCSR(- (DEST[31:0]*SRC3[31:0]) - SRC2[31:0])\r\nDEST[127:32] <-DEST[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVFNMSUB213SS DEST, SRC2, SRC3 (VEX encoded version)\r\nDEST[31:0] <-RoundFPControl_MXCSR(- (SRC2[31:0]*DEST[31:0]) - SRC3[31:0])\r\nDEST[127:32] <-DEST[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nVFNMSUB231SS DEST, SRC2, SRC3 (VEX encoded version)\r\nDEST[31:0] <-RoundFPControl_MXCSR(- (SRC2[31:0]*SRC3[31:0]) - DEST[31:0])\r\nDEST[127:32] <-DEST[127:32]\r\nDEST[MAX_VL-1:128] <-0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVFNMSUBxxxSS __m128 _mm_fnmsub_round_ss(__m128 a, __m128 b, __m128 c, int r);\r\nVFNMSUBxxxSS __m128 _mm_mask_fnmsub_ss(__m128 a, __mmask8 k, __m128 b, __m128 c);\r\nVFNMSUBxxxSS __m128 _mm_maskz_fnmsub_ss(__mmask8 k, __m128 a, __m128 b, __m128 c);\r\nVFNMSUBxxxSS __m128 _mm_mask3_fnmsub_ss(__m128 a, __m128 b, __m128 c, __mmask8 k);\r\nVFNMSUBxxxSS __m128 _mm_mask_fnmsub_round_ss(__m128 a, __mmask8 k, __m128 b, __m128 c, int r);\r\nVFNMSUBxxxSS __m128 _mm_maskz_fnmsub_round_ss(__mmask8 k, __m128 a, __m128 b, __m128 c, int r);\r\nVFNMSUBxxxSS __m128 _mm_mask3_fnmsub_round_ss(__m128 a, __m128 b, __m128 c, __mmask8 k, int r);\r\nVFNMSUBxxxSS __m128 _mm_fnmsub_ss (__m128 a, __m128 b, __m128 c);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 3.\r\n\r\nEVEX-encoded instructions, see Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VFNMSUB132SS"
},
{
"description": "-R:VFNMSUB132PD",
"mnem": "VFNMSUB213PD"
},
{
"description": "-R:VFNMSUB132PS",
"mnem": "VFNMSUB213PS"
},
{
"description": "-R:VFNMSUB132SD",
"mnem": "VFNMSUB213SD"
},
{
"description": "-R:VFNMSUB132SS",
"mnem": "VFNMSUB213SS"
},
{
"description": "-R:VFNMSUB132PD",
"mnem": "VFNMSUB231PD"
},
{
"description": "-R:VFNMSUB132PS",
"mnem": "VFNMSUB231PS"
},
{
"description": "-R:VFNMSUB132SD",
"mnem": "VFNMSUB231SD"
},
{
"description": "-R:VFNMSUB132SS",
"mnem": "VFNMSUB231SS"
},
{
"description": "VFPCLASSPD-Tests Types Of a Packed Float64 Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F3A.W1 66 /r ib FV V/V AVX512VL Tests the input for the following categories: NaN, +0, -0,\r\n VFPCLASSPD k2 {k1}, AVX512DQ +Infinity, -Infinity, denormal, finite negative. The immediate\r\n xmm2/m128/m64bcst, imm8 field provides a mask bit for each of these category tests. The\r\n masked test results are OR-ed together to form a mask result.\r\n EVEX.256.66.0F3A.W1 66 /r ib FV V/V AVX512VL Tests the input for the following categories: NaN, +0, -0,\r\n VFPCLASSPD k2 {k1}, AVX512DQ +Infinity, -Infinity, denormal, finite negative. The immediate\r\n ymm2/m256/m64bcst, imm8 field provides a mask bit for each of these category tests. The\r\n masked test results are OR-ed together to form a mask result.\r\n EVEX.512.66.0F3A.W1 66 /r ib FV V/V AVX512DQ Tests the input for the following categories: NaN, +0, -0,\r\n VFPCLASSPD k2 {k1}, +Infinity, -Infinity, denormal, finite negative. The immediate\r\n zmm2/m512/m64bcst, imm8 field provides a mask bit for each of these category tests. The\r\n masked test results are OR-ed together to form a mask result.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nThe FPCLASSPD instruction checks the packed double precision floating point values for special categories, speci-\r\nfied by the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point values that the\r\ninput data element is classified against. The classified results of all specified categories of an input value are ORed\r\ntogether to form the final boolean result for the input element. The result of each element is written to the corre-\r\nsponding bit in a mask register k2 according to the writemask k1. Bits [MAX_KL-1:8/4/2] of the destination are\r\ncleared.\r\nThe classification categories specified by imm8 are shown in Figure 5-13. The classification test for each category\r\nis listed in Table 5-6.\r\n\r\n\r\n\r\n 7 6 5 4 3 2 1 0\r\n\r\n SNaN Neg. Finite Denormal Neg. INF +INF Neg. 0 +0 QNaN\r\n\r\n\r\n\r\n\r\n Figure 5-13. Imm8 Byte Specifier of Special Case FP Values for VFPCLASSPD/SD/PS/SS\r\n\r\n\r\n\r\n Table 5-6. Classifier Operations for VFPCLASSPD/SD/PS/SS\r\nBits Imm8[0] Imm8[1] Imm8[2] Imm8[3] Imm8[4] Imm8[5] Imm8[6] Imm8[7]\r\nCategory QNAN PosZero NegZero PosINF NegINF Denormal Negative SNAN\r\nClassifier Checks for Checks for Checks for - Checks for Checks for - Checks for Checks for Checks for\r\n QNaN +0 0 +INF INF Denormal Negative finite SNaN\r\n\r\nThe source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector\r\nbroadcasted from a 64-bit memory location.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nCheckFPClassDP (tsrc[63:0], imm8[7:0]){\r\n\r\n //* Start checking the source operand for special type *//\r\n NegNum <- tsrc[63];\r\n IF (tsrc[62:52]=07FFh) Then ExpAllOnes <- 1; FI;\r\n IF (tsrc[62:52]=0h) Then ExpAllZeros <- 1;\r\n IF (ExpAllZeros AND MXCSR.DAZ) Then\r\n MantAllZeros <- 1;\r\n ELSIF (tsrc[51:0]=0h) Then\r\n MantAllZeros <- 1;\r\n FI;\r\n ZeroNumber <- ExpAllZeros AND MantAllZeros\r\n SignalingBit <- tsrc[51];\r\n\r\n sNaN_res <- ExpAllOnes AND NOT(MantAllZeros) AND NOT(SignalingBit) ; // sNaN\r\n qNaN_res <- ExpAllOnes AND NOT(MantAllZeros) AND SignalingBit;; // qNaN\r\n Pzero_res <- NOT(NegNum) AND ExpAllZeros AND MantAllZeros;; // +0\r\n Nzero_res <- NegNum AND ExpAllZeros AND MantAllZeros;; // -0\r\n PInf_res <- NOT(NegNum) AND ExpAllOnes AND MantAllZeros;; // +Inf\r\n NInf_res <- NegNum AND ExpAllOnes AND MantAllZeros;; // -Inf\r\n Denorm_res <- ExpAllZeros AND NOT(MantAllZeros);; // denorm\r\n FinNeg_res <- NegNum AND NOT(ExpAllOnes) AND NOT(ZeroNumber);; // -finite\r\n\r\n bResult = ( imm8[0] AND qNaN_res ) OR (imm8[1] AND Pzero_res ) OR\r\n ( imm8[2] AND Nzero_res ) OR ( imm8[3] AND PInf_res ) OR\r\n ( imm8[4] AND NInf_res ) OR ( imm8[5] AND Denorm_res ) OR\r\n ( imm8[6] AND FinNeg_res ) OR ( imm8[7] AND sNaN_res ) ;\r\n Return bResult;\r\n} //* end of CheckFPClassDP() *//\r\n\r\nVFPCLASSPD (EVEX Encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b == 1) AND (SRC *is memory*)\r\n THEN\r\n DEST[j] <- CheckFPClassDP(SRC1[63:0], imm8[7:0]);\r\n ELSE\r\n DEST[j] <- CheckFPClassDP(SRC1[i+63:i], imm8[7:0]);\r\n FI;\r\n ELSE DEST[j] <- 0 ; zeroing-masking only\r\n FI;\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVFPCLASSPD __mmask8 _mm512_fpclass_pd_mask( __m512d a, int c);\r\nVFPCLASSPD __mmask8 _mm512_mask_fpclass_pd_mask( __mmask8 m, __m512d a, int c)\r\nVFPCLASSPD __mmask8 _mm256_fpclass_pd_mask( __m256d a, int c)\r\nVFPCLASSPD __mmask8 _mm256_mask_fpclass_pd_mask( __mmask8 m, __m256d a, int c)\r\nVFPCLASSPD __mmask8 _mm_fpclass_pd_mask( __m128d a, int c)\r\nVFPCLASSPD __mmask8 _mm_mask_fpclass_pd_mask( __mmask8 m, __m128d a, int c)\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type E4\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VFPCLASSPD"
},
{
"description": "VFPCLASSPS-Tests Types Of a Packed Float32 Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F3A.W0 66 /r ib FV V/V AVX512VL Tests the input for the following categories: NaN, +0, -0,\r\n VFPCLASSPS k2 {k1}, AVX512DQ +Infinity, -Infinity, denormal, finite negative. The immediate\r\n xmm2/m128/m32bcst, imm8 field provides a mask bit for each of these category tests. The\r\n masked test results are OR-ed together to form a mask result.\r\n EVEX.256.66.0F3A.W0 66 /r ib FV V/V AVX512VL Tests the input for the following categories: NaN, +0, -0,\r\n VFPCLASSPS k2 {k1}, AVX512DQ +Infinity, -Infinity, denormal, finite negative. The immediate\r\n ymm2/m256/m32bcst, imm8 field provides a mask bit for each of these category tests. The\r\n masked test results are OR-ed together to form a mask result.\r\n EVEX.512.66.0F3A.W0 66 /r ib FV V/V AVX512DQ Tests the input for the following categories: NaN, +0, -0,\r\n VFPCLASSPS k2 {k1}, +Infinity, -Infinity, denormal, finite negative. The immediate\r\n zmm2/m512/m32bcst, imm8 field provides a mask bit for each of these category tests. The\r\n masked test results are OR-ed together to form a mask result.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nThe FPCLASSPS instruction checks the packed single-precision floating point values for special categories, specified\r\nby the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point values that the input\r\ndata element is classified against. The classified results of all specified categories of an input value are ORed\r\ntogether to form the final boolean result for the input element. The result of each element is written to the corre-\r\nsponding bit in a mask register k2 according to the writemask k1. Bits [MAX_KL-1:16/8/4] of the destination are\r\ncleared.\r\nThe classification categories specified by imm8 are shown in Figure 5-13. The classification test for each category\r\nis listed in Table 5-6.\r\nThe source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector\r\nbroadcasted from a 32-bit memory location.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\nOperation\r\nCheckFPClassSP (tsrc[31:0], imm8[7:0]){\r\n\r\n //* Start checking the source operand for special type *//\r\n NegNum <- tsrc[31];\r\n IF (tsrc[30:23]=0FFh) Then ExpAllOnes <- 1; FI;\r\n IF (tsrc[30:23]=0h) Then ExpAllZeros <- 1;\r\n IF (ExpAllZeros AND MXCSR.DAZ) Then\r\n MantAllZeros <- 1;\r\n ELSIF (tsrc[22:0]=0h) Then\r\n MantAllZeros <- 1;\r\n FI;\r\n ZeroNumber= ExpAllZeros AND MantAllZeros\r\n SignalingBit= tsrc[22];\r\n\r\n sNaN_res <- ExpAllOnes AND NOT(MantAllZeros) AND NOT(SignalingBit) ; // sNaN\r\n qNaN_res <- ExpAllOnes AND NOT(MantAllZeros) AND SignalingBit;; // qNaN\r\n Pzero_res <- NOT(NegNum) AND ExpAllZeros AND MantAllZeros;; // +0\r\n\r\n\r\n\r\n Nzero_res <- NegNum AND ExpAllZeros AND MantAllZeros;; // -0\r\n PInf_res <- NOT(NegNum) AND ExpAllOnes AND MantAllZeros;; // +Inf\r\n NInf_res <- NegNum AND ExpAllOnes AND MantAllZeros;; // -Inf\r\n Denorm_res <- ExpAllZeros AND NOT(MantAllZeros);; // denorm\r\n FinNeg_res <- NegNum AND NOT(ExpAllOnes) AND NOT(ZeroNumber);; // -finite\r\n\r\n bResult = ( imm8[0] AND qNaN_res ) OR (imm8[1] AND Pzero_res ) OR\r\n ( imm8[2] AND Nzero_res ) OR ( imm8[3] AND PInf_res ) OR\r\n ( imm8[4] AND NInf_res ) OR ( imm8[5] AND Denorm_res ) OR\r\n ( imm8[6] AND FinNeg_res ) OR ( imm8[7] AND sNaN_res ) ;\r\n Return bResult;\r\n} //* end of CheckSPClassSP() *//\r\n\r\nVFPCLASSPS (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b == 1) AND (SRC *is memory*)\r\n THEN\r\n DEST[j] <- CheckFPClassDP(SRC1[31:0], imm8[7:0]);\r\n ELSE\r\n DEST[j] <- CheckFPClassDP(SRC1[i+31:i], imm8[7:0]);\r\n FI;\r\n ELSE DEST[j] <- 0 ; zeroing-masking only\r\n FI;\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVFPCLASSPS __mmask16 _mm512_fpclass_ps_mask( __m512 a, int c);\r\nVFPCLASSPS __mmask16 _mm512_mask_fpclass_ps_mask( __mmask16 m, __m512 a, int c)\r\nVFPCLASSPS __mmask8 _mm256_fpclass_ps_mask( __m256 a, int c)\r\nVFPCLASSPS __mmask8 _mm256_mask_fpclass_ps_mask( __mmask8 m, __m256 a, int c)\r\nVFPCLASSPS __mmask8 _mm_fpclass_ps_mask( __m128 a, int c)\r\nVFPCLASSPS __mmask8 _mm_mask_fpclass_ps_mask( __mmask8 m, __m128 a, int c)\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type E4\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VFPCLASSPS"
},
{
"description": "VFPCLASSSD-Tests Types Of a Scalar Float64 Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.LIG.66.0F3A.W1 67 /r ib T1S V/V AVX512DQ Tests the input for the following categories: NaN, +0, -0,\r\n VFPCLASSSD k2 {k1}, +Infinity, -Infinity, denormal, finite negative. The immediate\r\n xmm2/m64, imm8 field provides a mask bit for each of these category tests. The\r\n masked test results are OR-ed together to form a mask result.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nThe FPCLASSSD instruction checks the low double precision floating point value in the source operand for special\r\ncategories, specified by the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point\r\nvalues that the input data element is classified against. The classified results of all specified categories of an input\r\nvalue are ORed together to form the final boolean result for the input element. The result is written to the low bit\r\nin a mask register k2 according to the writemask k1. Bits MAX_KL-1: 1 of the destination are cleared.\r\nThe classification categories specified by imm8 are shown in Figure 5-13. The classification test for each category\r\nis listed in Table 5-6.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\nOperation\r\nCheckFPClassDP (tsrc[63:0], imm8[7:0]){\r\n\r\n NegNum <- tsrc[63];\r\n IF (tsrc[62:52]=07FFh) Then ExpAllOnes <- 1; FI;\r\n IF (tsrc[62:52]=0h) Then ExpAllZeros <- 1;\r\n IF (ExpAllZeros AND MXCSR.DAZ) Then\r\n MantAllZeros <- 1;\r\n ELSIF (tsrc[51:0]=0h) Then\r\n MantAllZeros <- 1;\r\n FI;\r\n ZeroNumber <- ExpAllZeros AND MantAllZeros\r\n SignalingBit <- tsrc[51];\r\n\r\n sNaN_res <- ExpAllOnes AND NOT(MantAllZeros) AND NOT(SignalingBit) ; // sNaN\r\n qNaN_res <- ExpAllOnes AND NOT(MantAllZeros) AND SignalingBit;; // qNaN\r\n Pzero_res <- NOT(NegNum) AND ExpAllZeros AND MantAllZeros;; // +0\r\n Nzero_res <- NegNum AND ExpAllZeros AND MantAllZeros;; // -0\r\n PInf_res <- NOT(NegNum) AND ExpAllOnes AND MantAllZeros;; // +Inf\r\n NInf_res <- NegNum AND ExpAllOnes AND MantAllZeros;; // -Inf\r\n Denorm_res <- ExpAllZeros AND NOT(MantAllZeros);; // denorm\r\n FinNeg_res <- NegNum AND NOT(ExpAllOnes) AND NOT(ZeroNumber);; // -finite\r\n\r\n bResult = ( imm8[0] AND qNaN_res ) OR (imm8[1] AND Pzero_res ) OR\r\n ( imm8[2] AND Nzero_res ) OR ( imm8[3] AND PInf_res ) OR\r\n ( imm8[4] AND NInf_res ) OR ( imm8[5] AND Denorm_res ) OR\r\n ( imm8[6] AND FinNeg_res ) OR ( imm8[7] AND sNaN_res ) ;\r\n Return bResult;\r\n} //* end of CheckFPClassDP() *//\r\n\r\n\r\n\r\nVFPCLASSSD (EVEX encoded version)\r\nIF k1[0] OR *no writemask*\r\n THEN DEST[0] <-\r\n CheckFPClassDP(SRC1[63:0], imm8[7:0])\r\n ELSE DEST[0] <- 0 ; zeroing-masking only\r\nFI;\r\nDEST[MAX_KL-1:1] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVFPCLASSSD __mmask8 _mm_fpclass_sd_mask( __m128d a, int c)\r\nVFPCLASSSD __mmask8 _mm_mask_fpclass_sd_mask( __mmask8 m, __m128d a, int c)\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type E6\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VFPCLASSSD"
},
{
"description": "VFPCLASSSS-Tests Types Of a Scalar Float32 Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.LIG.66.0F3A.W0 67 /r T1S V/V AVX512DQ Tests the input for the following categories: NaN, +0, -0,\r\n VFPCLASSSS k2 {k1}, +Infinity, -Infinity, denormal, finite negative. The immediate\r\n xmm2/m32, imm8 field provides a mask bit for each of these category tests. The\r\n masked test results are OR-ed together to form a mask result.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nThe FPCLASSSS instruction checks the low single-precision floating point value in the source operand for special\r\ncategories, specified by the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point\r\nvalues that the input data element is classified against. The classified results of all specified categories of an input\r\nvalue are ORed together to form the final boolean result for the input element. The result is written to the low bit\r\nin a mask register k2 according to the writemask k1. Bits MAX_KL-1: 1 of the destination are cleared.\r\nThe classification categories specified by imm8 are shown in Figure 5-13. The classification test for each category\r\nis listed in Table 5-6.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nCheckFPClassSP (tsrc[31:0], imm8[7:0]){\r\n\r\n //* Start checking the source operand for special type *//\r\n NegNum <- tsrc[31];\r\n IF (tsrc[30:23]=0FFh) Then ExpAllOnes <- 1; FI;\r\n IF (tsrc[30:23]=0h) Then ExpAllZeros <- 1;\r\n IF (ExpAllZeros AND MXCSR.DAZ) Then\r\n MantAllZeros <- 1;\r\n ELSIF (tsrc[22:0]=0h) Then\r\n MantAllZeros <- 1;\r\n FI;\r\n ZeroNumber= ExpAllZeros AND MantAllZeros\r\n SignalingBit= tsrc[22];\r\n\r\n sNaN_res <- ExpAllOnes AND NOT(MantAllZeros) AND NOT(SignalingBit) ; // sNaN\r\n qNaN_res <- ExpAllOnes AND NOT(MantAllZeros) AND SignalingBit;; // qNaN\r\n Pzero_res <- NOT(NegNum) AND ExpAllZeros AND MantAllZeros;; // +0\r\n Nzero_res <- NegNum AND ExpAllZeros AND MantAllZeros;; // -0\r\n PInf_res <- NOT(NegNum) AND ExpAllOnes AND MantAllZeros;; // +Inf\r\n NInf_res <- NegNum AND ExpAllOnes AND MantAllZeros;; // -Inf\r\n Denorm_res <- ExpAllZeros AND NOT(MantAllZeros);; // denorm\r\n FinNeg_res <- NegNum AND NOT(ExpAllOnes) AND NOT(ZeroNumber);; // -finite\r\n\r\n bResult = ( imm8[0] AND qNaN_res ) OR (imm8[1] AND Pzero_res ) OR\r\n ( imm8[2] AND Nzero_res ) OR ( imm8[3] AND PInf_res ) OR\r\n ( imm8[4] AND NInf_res ) OR ( imm8[5] AND Denorm_res ) OR\r\n ( imm8[6] AND FinNeg_res ) OR ( imm8[7] AND sNaN_res ) ;\r\n Return bResult;\r\n} //* end of CheckSPClassSP() *//\r\n\r\nVFPCLASSSS (EVEX encoded version)\r\nIF k1[0] OR *no writemask*\r\n THEN DEST[0] <-\r\n CheckFPClassSP(SRC1[31:0], imm8[7:0])\r\n ELSE DEST[0] <- 0 ; zeroing-masking only\r\nFI;\r\nDEST[MAX_KL-1:1] <- 0\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVFPCLASSSS __mmask8 _mm_fpclass_ss_mask( __m128 a, int c)\r\nVFPCLASSSS __mmask8 _mm_mask_fpclass_ss_mask( __mmask8 m, __m128 a, int c)\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type E6\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VFPCLASSSS"
},
{
"description": "VGATHERDPD/VGATHERQPD - Gather Packed DP FP Values Using Signed Dword/Qword Indices\r\n Opcode/ Op/ 64/3 CPUID Description\r\n Instruction En 2-bit Feature\r\n Mode Flag\r\n VEX.DDS.128.66.0F38.W1 92 /r RMV V/V AVX2 Using dword indices specified in vm32x, gather double-pre-\r\n VGATHERDPD xmm1, vm32x, xmm2 cision FP values from memory conditioned on mask speci-\r\n fied by xmm2. Conditionally gathered elements are merged\r\n into xmm1.\r\n\r\n VEX.DDS.128.66.0F38.W1 93 /r RMV V/V AVX2 Using qword indices specified in vm64x, gather double-pre-\r\n VGATHERQPD xmm1, vm64x, xmm2 cision FP values from memory conditioned on mask speci-\r\n fied by xmm2. Conditionally gathered elements are merged\r\n into xmm1.\r\n\r\n VEX.DDS.256.66.0F38.W1 92 /r RMV V/V AVX2 Using dword indices specified in vm32x, gather double-pre-\r\n VGATHERDPD ymm1, vm32x, ymm2 cision FP values from memory conditioned on mask speci-\r\n fied by ymm2. Conditionally gathered elements are merged\r\n into ymm1.\r\n\r\n VEX.DDS.256.66.0F38.W1 93 /r RMV V/V AVX2 Using qword indices specified in vm64y, gather double-pre-\r\n VGATHERQPD ymm1, vm64y, ymm2 cision FP values from memory conditioned on mask speci-\r\n fied by ymm2. Conditionally gathered elements are merged\r\n into ymm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMV ModRM:reg (r,w) BaseReg (R): VSIB:base, VEX.vvvv (r, w) NA\r\n VectorReg(R): VSIB:index\r\n\r\nDescription\r\nThe instruction conditionally loads up to 2 or 4 double-precision floating-point values from memory addresses\r\nspecified by the memory operand (the second operand) and using qword indices. The memory operand uses the\r\nVSIB form of the SIB byte to specify a general purpose register operand as the common base, a vector register for\r\nan array of indices relative to the base and a constant scale factor.\r\nThe mask operand (the third operand) specifies the conditional load operation from each memory address and the\r\ncorresponding update of each data element of the destination operand (the first operand). Conditionality is speci-\r\nfied by the most significant bit of each data element of the mask register. If an element's mask bit is not set, the\r\ncorresponding element of the destination register is left unchanged. The width of data element in the destination\r\nregister and mask register are identical. The entire mask register will be set to zero by this instruction unless the\r\ninstruction causes an exception.\r\nUsing dword indices in the lower half of the mask register, the instruction conditionally loads up to 2 or 4 double-\r\nprecision floating-point values from the VSIB addressing memory operand, and updates the destination register.\r\nThis instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception\r\nis triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination\r\nregister and the mask operand are partially updated; those elements that have been gathered are placed into the\r\ndestination register and have their mask bits set to zero. If any traps or interrupts are pending from already gath-\r\nered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction\r\nbreakpoint is not re-triggered when the instruction is continued.\r\nIf the data size and index size are different, part of the destination register and part of the mask register do not\r\ncorrespond to any elements being gathered. This instruction sets those parts to zero. It may do this to one or both\r\nof those registers even if the instruction triggers an exception, and even if the instruction triggers the exception\r\nbefore gathering any elements.\r\n\r\n\r\n\r\n\r\n\r\nVEX.128 version: The instruction will gather two double-precision floating-point values. For dword indices, only the\r\nlower two indices in the vector index register are used.\r\nVEX.256 version: The instruction will gather four double-precision floating-point values. For dword indices, only\r\nthe lower four indices in the vector index register are used.\r\nNote that:\r\n. If any pair of the index, mask, or destination registers are the same, this instruction results a #UD fault.\r\n. The values may be read from memory in any order. Memory ordering with other instructions follows the Intel-\r\n 64 memory-ordering model.\r\n. Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all\r\n elements closer to the LSB of the destination will be completed (and non-faulting). Individual elements closer\r\n to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered in the\r\n conventional order.\r\n. Elements may be gathered in any order, but faults must be delivered in a right-to-left order; thus, elements to\r\n the left of a faulting one may be gathered before the fault is delivered. A given implementation of this\r\n instruction is repeatable - given the same input values and architectural state, the same set of elements to the\r\n left of the faulting one will be gathered.\r\n. This instruction does not perform AC checks, and so will never deliver an AC fault.\r\n. This instruction will cause a #UD if the address size attribute is 16-bit.\r\n. This instruction will cause a #UD if the memory operand is encoded without the SIB byte.\r\n. This instruction should not be used to access memory mapped I/O as the ordering of the individual loads it does\r\n is implementation specific, and some implementations may use loads larger than the data element size or load\r\n elements an indeterminate number of times.\r\n. The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-\r\n bit mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address\r\n bits are ignored.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nDEST <- SRC1;\r\nBASE_ADDR: base register encoded in VSIB addressing;\r\nVINDEX: the vector index register encoded by VSIB addressing;\r\nSCALE: scale factor encoded by SIB:[7:6];\r\nDISP: optional 1, 4 byte displacement;\r\nMASK <- SRC3;\r\n\r\nVGATHERDPD (VEX.128 version)\r\nFOR j<- 0 to 1\r\n i <- j * 64;\r\n IF MASK[63+i] THEN\r\n MASK[i +63:i] <- FFFFFFFF_FFFFFFFFH; // extend from most significant bit\r\n ELSE\r\n MASK[i +63:i] <- 0;\r\n FI;\r\nENDFOR\r\nFOR j<- 0 to 1\r\n k <- j * 32;\r\n i <- j * 64;\r\n DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX[k+31:k])*SCALE + DISP;\r\n IF MASK[63+i] THEN\r\n DEST[i +63:i] <- FETCH_64BITS(DATA_ADDR); // a fault exits the instruction\r\n FI;\r\n MASK[i +63: i] <- 0;\r\nENDFOR\r\nMASK[VLMAX-1:128] <- 0;\r\nDEST[VLMAX-1:128] <- 0;\r\n(non-masked elements of the mask register have the content of respective element cleared)\r\n\r\nVGATHERQPD (VEX.128 version)\r\nFOR j<- 0 to 1\r\n i <- j * 64;\r\n IF MASK[63+i] THEN\r\n MASK[i +63:i] <- FFFFFFFF_FFFFFFFFH; // extend from most significant bit\r\n ELSE\r\n MASK[i +63:i] <- 0;\r\n FI;\r\nENDFOR\r\nFOR j<- 0 to 1\r\n i <- j * 64;\r\n DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[i+63:i])*SCALE + DISP;\r\n IF MASK[63+i] THEN\r\n DEST[i +63:i] <- FETCH_64BITS(DATA_ADDR); // a fault exits this instruction\r\n FI;\r\n MASK[i +63: i] <- 0;\r\nENDFOR\r\nMASK[VLMAX-1:128] <- 0;\r\nDEST[VLMAX-1:128] <- 0;\r\n(non-masked elements of the mask register have the content of respective element cleared)\r\n\r\n\r\n\r\n\r\n\r\nVGATHERQPD (VEX.256 version)\r\nFOR j<- 0 to 3\r\n i <- j * 64;\r\n IF MASK[63+i] THEN\r\n MASK[i +63:i] <- FFFFFFFF_FFFFFFFFH; // extend from most significant bit\r\n ELSE\r\n MASK[i +63:i] <- 0;\r\n FI;\r\nENDFOR\r\nFOR j<- 0 to 3\r\n i <- j * 64;\r\n DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[i+63:i])*SCALE + DISP;\r\n IF MASK[63+i] THEN\r\n DEST[i +63:i] <- FETCH_64BITS(DATA_ADDR); // a fault exits the instruction\r\n FI;\r\n MASK[i +63: i] <- 0;\r\nENDFOR\r\n(non-masked elements of the mask register have the content of respective element cleared)\r\n\r\nVGATHERDPD (VEX.256 version)\r\nFOR j<- 0 to 3\r\n i <- j * 64;\r\n IF MASK[63+i] THEN\r\n MASK[i +63:i] <- FFFFFFFF_FFFFFFFFH; // extend from most significant bit\r\n ELSE\r\n MASK[i +63:i] <- 0;\r\n FI;\r\nENDFOR\r\nFOR j<- 0 to 3\r\n k <- j * 32;\r\n i <- j * 64;\r\n DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[k+31:k])*SCALE + DISP;\r\n IF MASK[63+i] THEN\r\n DEST[i +63:i] <- FETCH_64BITS(DATA_ADDR); // a fault exits the instruction\r\n FI;\r\n MASK[i +63:i] <- 0;\r\nENDFOR\r\n(non-masked elements of the mask register have the content of respective element cleared)\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVGATHERDPD: __m128d _mm_i32gather_pd (double const * base, __m128i index, const int scale);\r\nVGATHERDPD: __m128d _mm_mask_i32gather_pd (__m128d src, double const * base, __m128i index, __m128d mask, const int\r\nscale);\r\nVGATHERDPD: __m256d _mm256_i32gather_pd (double const * base, __m128i index, const int scale);\r\nVGATHERDPD: __m256d _mm256_mask_i32gather_pd (__m256d src, double const * base, __m128i index, __m256d mask, const int\r\nscale);\r\nVGATHERQPD: __m128d _mm_i64gather_pd (double const * base, __m128i index, const int scale);\r\nVGATHERQPD: __m128d _mm_mask_i64gather_pd (__m128d src, double const * base, __m128i index, __m128d mask, const int\r\nscale);\r\nVGATHERQPD: __m256d _mm256_i64gather_pd (double const * base, __m256i index, const int scale);\r\nVGATHERQPD: __m256d _mm256_mask_i64gather_pd (__m256d src, double const * base, __m256i index, __m256d mask, const int\r\nscale);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 12.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VGATHERDPD"
},
{
"description": "-R:VGATHERDPS",
"mnem": "VGATHERDPD"
},
{
"description": "VGATHERDPS/VGATHERQPS - Gather Packed SP FP values Using Signed Dword/Qword Indices\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En -bit Feature\r\n Mode Flag\r\n VEX.DDS.128.66.0F38.W0 92 /r RMV V/V AVX2 Using dword indices specified in vm32x, gather single-preci-\r\n VGATHERDPS xmm1, vm32x, xmm2 sion FP values from memory conditioned on mask specified\r\n by xmm2. Conditionally gathered elements are merged into\r\n xmm1.\r\n\r\n VEX.DDS.128.66.0F38.W0 93 /r RMV V/V AVX2 Using qword indices specified in vm64x, gather single-preci-\r\n VGATHERQPS xmm1, vm64x, xmm2 sion FP values from memory conditioned on mask specified\r\n by xmm2. Conditionally gathered elements are merged into\r\n xmm1.\r\n\r\n VEX.DDS.256.66.0F38.W0 92 /r RMV V/V AVX2 Using dword indices specified in vm32y, gather single-preci-\r\n VGATHERDPS ymm1, vm32y, ymm2 sion FP values from memory conditioned on mask specified\r\n by ymm2. Conditionally gathered elements are merged into\r\n ymm1.\r\n\r\n VEX.DDS.256.66.0F38.W0 93 /r RMV V/V AVX2 Using qword indices specified in vm64y, gather single-preci-\r\n VGATHERQPS xmm1, vm64y, xmm2 sion FP values from memory conditioned on mask specified\r\n by xmm2. Conditionally gathered elements are merged into\r\n xmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n A ModRM:reg (r,w) BaseReg (R): VSIB:base, VEX.vvvv (r, w) NA\r\n VectorReg(R): VSIB:index\r\n\r\nDescription\r\nThe instruction conditionally loads up to 4 or 8 single-precision floating-point values from memory addresses spec-\r\nified by the memory operand (the second operand) and using dword indices. The memory operand uses the VSIB\r\nform of the SIB byte to specify a general purpose register operand as the common base, a vector register for an\r\narray of indices relative to the base and a constant scale factor.\r\nThe mask operand (the third operand) specifies the conditional load operation from each memory address and the\r\ncorresponding update of each data element of the destination operand (the first operand). Conditionality is speci-\r\nfied by the most significant bit of each data element of the mask register. If an element's mask bit is not set, the\r\ncorresponding element of the destination register is left unchanged. The width of data element in the destination\r\nregister and mask register are identical. The entire mask register will be set to zero by this instruction unless the\r\ninstruction causes an exception.\r\nUsing qword indices, the instruction conditionally loads up to 2 or 4 single-precision floating-point values from the\r\nVSIB addressing memory operand, and updates the lower half of the destination register. The upper 128 or 256 bits\r\nof the destination register are zero'ed with qword indices.\r\nThis instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception\r\nis triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination\r\nregister and the mask operand are partially updated; those elements that have been gathered are placed into the\r\ndestination register and have their mask bits set to zero. If any traps or interrupts are pending from already gath-\r\nered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction\r\nbreakpoint is not re-triggered when the instruction is continued.\r\nIf the data size and index size are different, part of the destination register and part of the mask register do not\r\ncorrespond to any elements being gathered. This instruction sets those parts to zero. It may do this to one or both\r\nof those registers even if the instruction triggers an exception, and even if the instruction triggers the exception\r\nbefore gathering any elements.\r\n\r\n\r\n\r\nVEX.128 version: For dword indices, the instruction will gather four single-precision floating-point values. For\r\nqword indices, the instruction will gather two values and zeroes the upper 64 bits of the destination.\r\nVEX.256 version: For dword indices, the instruction will gather eight single-precision floating-point values. For\r\nqword indices, the instruction will gather four values and zeroes the upper 128 bits of the destination.\r\nNote that:\r\n. If any pair of the index, mask, or destination registers are the same, this instruction results a UD fault.\r\n. The values may be read from memory in any order. Memory ordering with other instructions follows the Intel-\r\n 64 memory-ordering model.\r\n. Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all\r\n elements closer to the LSB of the destination will be completed (and non-faulting). Individual elements closer\r\n to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered in the\r\n conventional order.\r\n. Elements may be gathered in any order, but faults must be delivered in a right-to-left order; thus, elements to\r\n the left of a faulting one may be gathered before the fault is delivered. A given implementation of this\r\n instruction is repeatable - given the same input values and architectural state, the same set of elements to the\r\n left of the faulting one will be gathered.\r\n. This instruction does not perform AC checks, and so will never deliver an AC fault.\r\n. This instruction will cause a #UD if the address size attribute is 16-bit.\r\n. This instruction will cause a #UD if the memory operand is encoded without the SIB byte.\r\n. This instruction should not be used to access memory mapped I/O as the ordering of the individual loads it does\r\n is implementation specific, and some implementations may use loads larger than the data element size or load\r\n elements an indeterminate number of times.\r\n. The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-\r\n bit mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address\r\n bits are ignored.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nDEST <- SRC1;\r\nBASE_ADDR: base register encoded in VSIB addressing;\r\nVINDEX: the vector index register encoded by VSIB addressing;\r\nSCALE: scale factor encoded by SIB:[7:6];\r\nDISP: optional 1, 4 byte displacement;\r\nMASK <- SRC3;\r\n\r\nVGATHERDPS (VEX.128 version)\r\nFOR j<- 0 to 3\r\n i <- j * 32;\r\n IF MASK[31+i] THEN\r\n MASK[i +31:i] <- FFFFFFFFH; // extend from most significant bit\r\n ELSE\r\n MASK[i +31:i] <- 0;\r\n FI;\r\nENDFOR\r\nMASK[VLMAX-1:128] <- 0;\r\nFOR j<- 0 to 3\r\n i <- j * 32;\r\n DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX[i+31:i])*SCALE + DISP;\r\n IF MASK[31+i] THEN\r\n DEST[i +31:i] <- FETCH_32BITS(DATA_ADDR); // a fault exits the instruction\r\n FI;\r\n MASK[i +31:i] <- 0;\r\nENDFOR\r\nDEST[VLMAX-1:128] <- 0;\r\n(non-masked elements of the mask register have the content of respective element cleared)\r\n\r\nVGATHERQPS (VEX.128 version)\r\nFOR j<- 0 to 3\r\n i <- j * 32;\r\n IF MASK[31+i] THEN\r\n MASK[i +31:i] <- FFFFFFFFH; // extend from most significant bit\r\n ELSE\r\n MASK[i +31:i] <- 0;\r\n FI;\r\nENDFOR\r\nMASK[VLMAX-1:128] <- 0;\r\nFOR j<- 0 to 1\r\n k <- j * 64;\r\n i <- j * 32;\r\n DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[k+63:k])*SCALE + DISP;\r\n IF MASK[31+i] THEN\r\n DEST[i +31:i] <- FETCH_32BITS(DATA_ADDR); // a fault exits the instruction\r\n FI;\r\n MASK[i +31:i] <- 0;\r\nENDFOR\r\nMASK[127:64] <- 0;\r\nDEST[VLMAX-1:64] <- 0;\r\n(non-masked elements of the mask register have the content of respective element cleared)\r\n\r\n\r\n\r\n\r\n\r\nVGATHERDPS (VEX.256 version)\r\nFOR j<- 0 to 7\r\n i <- j * 32;\r\n IF MASK[31+i] THEN\r\n MASK[i +31:i] <- FFFFFFFFH; // extend from most significant bit\r\n ELSE\r\n MASK[i +31:i] <- 0;\r\n FI;\r\nENDFOR\r\nFOR j<- 0 to 7\r\n i <- j * 32;\r\n DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[i+31:i])*SCALE + DISP;\r\n IF MASK[31+i] THEN\r\n DEST[i +31:i] <- FETCH_32BITS(DATA_ADDR); // a fault exits the instruction\r\n FI;\r\n MASK[i +31:i] <- 0;\r\nENDFOR\r\n(non-masked elements of the mask register have the content of respective element cleared)\r\n\r\nVGATHERQPS (VEX.256 version)\r\nFOR j<- 0 to 7\r\n i <- j * 32;\r\n IF MASK[31+i] THEN\r\n MASK[i +31:i] <- FFFFFFFFH; // extend from most significant bit\r\n ELSE\r\n MASK[i +31:i] <- 0;\r\n FI;\r\nENDFOR\r\nFOR j<- 0 to 3\r\n k <- j * 64;\r\n i <- j * 32;\r\n DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[k+63:k])*SCALE + DISP;\r\n IF MASK[31+i] THEN\r\n DEST[i +31:i] <- FETCH_32BITS(DATA_ADDR); // a fault exits the instruction\r\n FI;\r\n MASK[i +31:i] <- 0;\r\nENDFOR\r\nMASK[VLMAX-1:128] <- 0;\r\nDEST[VLMAX-1:128] <- 0;\r\n(non-masked elements of the mask register have the content of respective element cleared)\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVGATHERDPS: __m128 _mm_i32gather_ps (float const * base, __m128i index, const int scale);\r\nVGATHERDPS: __m128 _mm_mask_i32gather_ps (__m128 src, float const * base, __m128i index, __m128 mask, const int scale);\r\nVGATHERDPS: __m256 _mm256_i32gather_ps (float const * base, __m256i index, const int scale);\r\nVGATHERDPS: __m256 _mm256_mask_i32gather_ps (__m256 src, float const * base, __m256i index, __m256 mask, const int\r\nscale);\r\nVGATHERQPS: __m128 _mm_i64gather_ps (float const * base, __m128i index, const int scale);\r\nVGATHERQPS: __m128 _mm_mask_i64gather_ps (__m128 src, float const * base, __m128i index, __m128 mask, const int scale);\r\nVGATHERQPS: __m128 _mm256_i64gather_ps (float const * base, __m256i index, const int scale);\r\nVGATHERQPS: __m128 _mm256_mask_i64gather_ps (__m128 src, float const * base, __m256i index, __m128 mask, const int\r\nscale);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 12\r\n\r\n\r\n\r\n\r\n",
"mnem": "VGATHERDPS"
},
{
"description": "VGATHERDPS/VGATHERDPD-Gather Packed Single, Packed Double with Signed Dword\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F38.W0 92 /vsib T1S V/V AVX512VL Using signed dword indices, gather single-precision floating-\r\n VGATHERDPS xmm1 {k1}, vm32x AVX512F point values from memory using k1 as completion mask.\r\n EVEX.256.66.0F38.W0 92 /vsib T1S V/V AVX512VL Using signed dword indices, gather single-precision floating-\r\n VGATHERDPS ymm1 {k1}, vm32y AVX512F point values from memory using k1 as completion mask.\r\n EVEX.512.66.0F38.W0 92 /vsib T1S V/V AVX512F Using signed dword indices, gather single-precision floating-\r\n VGATHERDPS zmm1 {k1}, vm32z point values from memory using k1 as completion mask.\r\n EVEX.128.66.0F38.W1 92 /vsib T1S V/V AVX512VL Using signed dword indices, gather float64 vector into\r\n VGATHERDPD xmm1 {k1}, AVX512F float64 vector xmm1 using k1 as completion mask.\r\n vm32x\r\n EVEX.256.66.0F38.W1 92 /vsib T1S V/V AVX512VL Using signed dword indices, gather float64 vector into\r\n VGATHERDPD ymm1 {k1}, AVX512F float64 vector ymm1 using k1 as completion mask.\r\n vm32x\r\n EVEX.512.66.0F38.W1 92 /vsib T1S V/V AVX512F Using signed dword indices, gather float64 vector into\r\n VGATHERDPD zmm1 {k1}, vm32y float64 vector zmm1 using k1 as completion mask.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n BaseReg (R): VSIB:base,\r\n T1S ModRM:reg (w) NA NA\r\n VectorReg(R): VSIB:index\r\n\r\nDescription\r\nA set of single-precision/double-precision faulting-point memory locations pointed by base address BASE_ADDR\r\nand index vector V_INDEX with scale SCALE are gathered. The result is written into a vector register. The elements\r\nare specified via the VSIB (i.e., the index register is a vector register, holding packed indices). Elements will only\r\nbe loaded if their corresponding mask bit is one. If an element's mask bit is not set, the corresponding element of\r\nthe destination register is left unchanged. The entire mask register will be set to zero by this instruction unless it\r\ntriggers an exception.\r\nThis instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception\r\nis triggered by an element other than the right most one with its mask bit set). When this happens, the destination\r\nregister and the mask register (k1) are partially updated; those elements that have been gathered are placed into\r\nthe destination register and have their mask bits set to zero. If any traps or interrupts are pending from already\r\ngathered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruc-\r\ntion breakpoint is not re-triggered when the instruction is continued.\r\nIf the data element size is less than the index element size, the higher part of the destination register and the mask\r\nregister do not correspond to any elements being gathered. This instruction sets those higher parts to zero. It may\r\nupdate these unused elements to one or both of those registers even if the instruction triggers an exception, and\r\neven if the instruction triggers the exception before gathering any elements.\r\nNote that:\r\n. The values may be read from memory in any order. Memory ordering with other instructions follows the Intel-\r\n 64 memory-ordering model.\r\n. Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all\r\n elements closer to the LSB of the destination zmm will be completed (and non-faulting). Individual elements\r\n closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered\r\n in the conventional order.\r\n. Elements may be gathered in any order, but faults must be delivered in a right-to left order; thus, elements to\r\n the left of a faulting one may be gathered before the fault is delivered. A given implementation of this\r\n instruction is repeatable - given the same input values and architectural state, the same set of elements to the\r\n left of the faulting one will be gathered.\r\n\r\n\r\n\r\n\r\n. This instruction does not perform AC checks, and so will never deliver an AC fault.\r\n. Not valid with 16-bit effective addresses. Will deliver a #UD fault.\r\nNote that the presence of VSIB byte is enforced in this instruction. Hence, the instruction will #UD fault if\r\nModRM.rm is different than 100b.\r\nThis instruction has special disp8*N and alignment rules. N is considered to be the size of a single vector element.\r\nThe scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-bit\r\nmode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits are\r\nignored.\r\nThe instruction will #UD fault if the destination vector zmm1 is the same as index vector VINDEX. The instruction\r\nwill #UD fault if the k0 mask register is specified.\r\n\r\nOperation\r\nBASE_ADDR stands for the memory operand base address (a GPR); may not exist\r\nVINDEX stands for the memory operand vector of indices (a vector register)\r\nSCALE stands for the memory operand scalar (1, 2, 4 or 8)\r\nDISP is the optional 1, 2 or 4 byte displacement\r\n\r\nVGATHERDPS (EVEX encoded version)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j]\r\n THEN DEST[i+31:i] <-\r\n MEM[BASE_ADDR +\r\n SignExtend(VINDEX[i+31:i]) * SCALE + DISP]\r\n k1[j] <- 0\r\n ELSE *DEST[i+31:i] <- remains unchanged*\r\n FI;\r\nENDFOR\r\nk1[MAX_KL-1:KL] <- 0\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVGATHERDPD (EVEX encoded version)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n k <- j * 32\r\n IF k1[j]\r\n THEN DEST[i+63:i] <- MEM[BASE_ADDR +\r\n SignExtend(VINDEX[k+31:k]) * SCALE + DISP]\r\n k1[j] <- 0\r\n ELSE *DEST[i+63:i] <- remains unchanged*\r\n FI;\r\nENDFOR\r\nk1[MAX_KL-1:KL] <- 0\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVGATHERDPD __m512d _mm512_i32gather_pd( __m256i vdx, void * base, int scale);\r\nVGATHERDPD __m512d _mm512_mask_i32gather_pd(__m512d s, __mmask8 k, __m256i vdx, void * base, int scale);\r\nVGATHERDPD __m256d _mm256_mmask_i32gather_pd(__m256d s, __mmask8 k, __m128i vdx, void * base, int scale);\r\nVGATHERDPD __m128d _mm_mmask_i32gather_pd(__m128d s, __mmask8 k, __m128i vdx, void * base, int scale);\r\nVGATHERDPS __m512 _mm512_i32gather_ps( __m512i vdx, void * base, int scale);\r\nVGATHERDPS __m512 _mm512_mask_i32gather_ps(__m512 s, __mmask16 k, __m512i vdx, void * base, int scale);\r\nVGATHERDPS __m256 _mm256_mmask_i32gather_ps(__m256 s, __mmask8 k, __m256i vdx, void * base, int scale);\r\nGATHERDPS __m128 _mm_mmask_i32gather_ps(__m128 s, __mmask8 k, __m128i vdx, void * base, int scale);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type E12.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VGATHERDPS"
},
{
"description": "-R:VGATHERPF0DPS",
"mnem": "VGATHERPF0DPD"
},
{
"description": "VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD-Sparse Prefetch\r\nPacked SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.512.66.0F38.W0 C6 /1 /vsib T1S V/V AVX512PF Using signed dword indices, prefetch sparse byte\r\n VGATHERPF0DPS vm32z {k1} memory locations containing single-precision data\r\n using opmask k1 and T0 hint.\r\n EVEX.512.66.0F38.W0 C7 /1 /vsib T1S V/V AVX512PF Using signed qword indices, prefetch sparse byte\r\n VGATHERPF0QPS vm64z {k1} memory locations containing single-precision data\r\n using opmask k1 and T0 hint.\r\n EVEX.512.66.0F38.W1 C6 /1 /vsib T1S V/V AVX512PF Using signed dword indices, prefetch sparse byte\r\n VGATHERPF0DPD vm32y {k1} memory locations containing double-precision data\r\n using opmask k1 and T0 hint.\r\n EVEX.512.66.0F38.W1 C7 /1 /vsib T1S V/V AVX512PF Using signed qword indices, prefetch sparse byte\r\n VGATHERPF0QPD vm64z {k1} memory locations containing double-precision data\r\n using opmask k1 and T0 hint.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S BaseReg (R): VSIB:base, NA NA NA\r\n VectorReg(R): VSIB:index\r\n\r\nDescription\r\nThe instruction conditionally prefetches up to sixteen 32-bit or eight 64-bit integer byte data elements. The\r\nelements are specified via the VSIB (i.e., the index register is an zmm, holding packed indices). Elements will only\r\nbe prefetched if their corresponding mask bit is one.\r\nLines prefetched are loaded into to a location in the cache hierarchy specified by a locality hint (T0):\r\n. T0 (temporal data)-prefetch data into the first level cache.\r\n[PS data] For dword indices, the instruction will prefetch sixteen memory locations. For qword indices, the instruc-\r\ntion will prefetch eight values.\r\n[PD data] For dword and qword indices, the instruction will prefetch eight memory locations.\r\nNote that:\r\n(1) The prefetches may happen in any order (or not at all). The instruction is a hint.\r\n(2) The mask is left unchanged.\r\n(3) Not valid with 16-bit effective addresses. Will deliver a #UD fault.\r\n(4) No FP nor memory faults may be produced by this instruction.\r\n(5) Prefetches do not handle cache line splits\r\n(6) A #UD is signaled if the memory operand is encoded without the SIB byte.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nBASE_ADDR stands for the memory operand base address (a GPR); may not exist\r\nVINDEX stands for the memory operand vector of indices (a vector register)\r\nSCALE stands for the memory operand scalar (1, 2, 4 or 8)\r\nDISP is the optional 1, 2 or 4 byte displacement\r\nPREFETCH(mem, Level, State) Prefetches a byte memory location pointed by 'mem' into the cache level specified by 'Level'; a request\r\nfor exclusive/ownership is done if 'State' is 1. Note that the memory location ignore cache line splits. This operation is considered a\r\nhint for the processor and may be skipped depending on implementation.\r\n\r\nVGATHERPF0DPS (EVEX encoded version)\r\n(KL, VL) = (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j]\r\n Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+31:i]) * SCALE + DISP], Level=0, RFO = 0)\r\n FI;\r\nENDFOR\r\n\r\nVGATHERPF0DPD (EVEX encoded version)\r\n(KL, VL) = (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n k <- j * 32\r\n IF k1[j]\r\n Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+31:k]) * SCALE + DISP], Level=0, RFO = 0)\r\n FI;\r\nENDFOR\r\n\r\nVGATHERPF0QPS (EVEX encoded version)\r\n(KL, VL) = (8, 256)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j]\r\n Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+63:i]) * SCALE + DISP], Level=0, RFO = 0)\r\n FI;\r\nENDFOR\r\n\r\nVGATHERPF0QPD (EVEX encoded version)\r\n(KL, VL) = (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n k <- j * 64\r\n IF k1[j]\r\n Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+63:k]) * SCALE + DISP], Level=0, RFO = 0)\r\n FI;\r\nENDFOR\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVGATHERPF0DPD void _mm512_mask_prefetch_i32gather_pd(__m256i vdx, __mmask8 m, void * base, int scale, int hint);\r\nVGATHERPF0DPS void _mm512_mask_prefetch_i32gather_ps(__m512i vdx, __mmask16 m, void * base, int scale, int hint);\r\nVGATHERPF0QPD void _mm512_mask_prefetch_i64gather_pd(__m512i vdx, __mmask8 m, void * base, int scale, int hint);\r\nVGATHERPF0QPS void _mm512_mask_prefetch_i64gather_ps(__m512i vdx, __mmask8 m, void * base, int scale, int hint);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type E12NP.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VGATHERPF0DPS"
},
{
"description": "-R:VGATHERPF0DPS",
"mnem": "VGATHERPF0QPD"
},
{
"description": "-R:VGATHERPF0DPS",
"mnem": "VGATHERPF0QPS"
},
{
"description": "-R:VGATHERPF1DPS",
"mnem": "VGATHERPF1DPD"
},
{
"description": "VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD-Sparse Prefetch\r\nPacked SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.512.66.0F38.W0 C6 /2 /vsib T1S V/V AVX512PF Using signed dword indices, prefetch sparse byte\r\n VGATHERPF1DPS vm32z {k1} memory locations containing single-precision data using\r\n opmask k1 and T1 hint.\r\n EVEX.512.66.0F38.W0 C7 /2 /vsib T1S V/V AVX512PF Using signed qword indices, prefetch sparse byte\r\n VGATHERPF1QPS vm64z {k1} memory locations containing single-precision data using\r\n opmask k1 and T1 hint.\r\n EVEX.512.66.0F38.W1 C6 /2 /vsib T1S V/V AVX512PF Using signed dword indices, prefetch sparse byte\r\n VGATHERPF1DPD vm32y {k1} memory locations containing double-precision data using\r\n opmask k1 and T1 hint.\r\n EVEX.512.66.0F38.W1 C7 /2 /vsib T1S V/V AVX512PF Using signed qword indices, prefetch sparse byte\r\n VGATHERPF1QPD vm64z {k1} memory locations containing double-precision data using\r\n opmask k1 and T1 hint.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S BaseReg (R): VSIB:base, NA NA NA\r\n VectorReg(R): VSIB:index\r\n\r\nDescription\r\nThe instruction conditionally prefetches up to sixteen 32-bit or eight 64-bit integer byte data elements. The\r\nelements are specified via the VSIB (i.e., the index register is an zmm, holding packed indices). Elements will only\r\nbe prefetched if their corresponding mask bit is one.\r\nLines prefetched are loaded into to a location in the cache hierarchy specified by a locality hint (T1):\r\n. T1 (temporal data)-prefetch data into the second level cache.\r\n[PS data] For dword indices, the instruction will prefetch sixteen memory locations. For qword indices, the instruc-\r\ntion will prefetch eight values.\r\n[PD data] For dword and qword indices, the instruction will prefetch eight memory locations.\r\nNote that:\r\n(1) The prefetches may happen in any order (or not at all). The instruction is a hint.\r\n(2) The mask is left unchanged.\r\n(3) Not valid with 16-bit effective addresses. Will deliver a #UD fault.\r\n(4) No FP nor memory faults may be produced by this instruction.\r\n(5) Prefetches do not handle cache line splits\r\n(6) A #UD is signaled if the memory operand is encoded without the SIB byte.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nBASE_ADDR stands for the memory operand base address (a GPR); may not exist\r\nVINDEX stands for the memory operand vector of indices (a vector register)\r\nSCALE stands for the memory operand scalar (1, 2, 4 or 8)\r\nDISP is the optional 1, 2 or 4 byte displacement\r\nPREFETCH(mem, Level, State) Prefetches a byte memory location pointed by 'mem' into the cache level specified by 'Level'; a request\r\nfor exclusive/ownership is done if 'State' is 1. Note that the memory location ignore cache line splits. This operation is considered a\r\nhint for the processor and may be skipped depending on implementation.\r\n\r\nVGATHERPF1DPS (EVEX encoded version)\r\n(KL, VL) = (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j]\r\n Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+31:i]) * SCALE + DISP], Level=1, RFO = 0)\r\n FI;\r\nENDFOR\r\n\r\nVGATHERPF1DPD (EVEX encoded version)\r\n(KL, VL) = (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n k <- j * 32\r\n IF k1[j]\r\n Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+31:k]) * SCALE + DISP], Level=1, RFO = 0)\r\n FI;\r\nENDFOR\r\n\r\nVGATHERPF1QPS (EVEX encoded version)\r\n(KL, VL) = (8, 256)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j]\r\n Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+63:i]) * SCALE + DISP], Level=1, RFO = 0)\r\n FI;\r\nENDFOR\r\n\r\nVGATHERPF1QPD (EVEX encoded version)\r\n(KL, VL) = (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n k <- j * 64\r\n IF k1[j]\r\n Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+63:k]) * SCALE + DISP], Level=1, RFO = 0)\r\n FI;\r\nENDFOR\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVGATHERPF1DPD void _mm512_mask_prefetch_i32gather_pd(__m256i vdx, __mmask8 m, void * base, int scale, int hint);\r\nVGATHERPF1DPS void _mm512_mask_prefetch_i32gather_ps(__m512i vdx, __mmask16 m, void * base, int scale, int hint);\r\nVGATHERPF1QPD void _mm512_mask_prefetch_i64gather_pd(__m512i vdx, __mmask8 m, void * base, int scale, int hint);\r\nVGATHERPF1QPS void _mm512_mask_prefetch_i64gather_ps(__m512i vdx, __mmask8 m, void * base, int scale, int hint);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type E12NP.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VGATHERPF1DPS"
},
{
"description": "-R:VGATHERPF1DPS",
"mnem": "VGATHERPF1QPD"
},
{
"description": "-R:VGATHERPF1DPS",
"mnem": "VGATHERPF1QPS"
},
{
"description": "-R:VGATHERDPD",
"mnem": "VGATHERQPD"
},
{
"description": "-R:VGATHERQPS",
"mnem": "VGATHERQPD"
},
{
"description": "-R:VGATHERDPS",
"mnem": "VGATHERQPS"
},
{
"description": "VGATHERQPS/VGATHERQPD-Gather Packed Single, Packed Double with Signed Qword Indices\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F38.W0 93 /vsib T1S V/V AVX512VL Using signed qword indices, gather single-precision\r\n VGATHERQPS xmm1 {k1}, vm64x AVX512F floating-point values from memory using k1 as completion\r\n mask.\r\n EVEX.256.66.0F38.W0 93 /vsib T1S V/V AVX512VL Using signed qword indices, gather single-precision\r\n VGATHERQPS xmm1 {k1}, vm64y AVX512F floating-point values from memory using k1 as completion\r\n mask.\r\n EVEX.512.66.0F38.W0 93 /vsib T1S V/V AVX512F Using signed qword indices, gather single-precision\r\n VGATHERQPS ymm1 {k1}, vm64z floating-point values from memory using k1 as completion\r\n mask.\r\n EVEX.128.66.0F38.W1 93 /vsib T1S V/V AVX512VL Using signed qword indices, gather float64 vector into\r\n VGATHERQPD xmm1 {k1}, vm64x AVX512F float64 vector xmm1 using k1 as completion mask.\r\n EVEX.256.66.0F38.W1 93 /vsib T1S V/V AVX512VL Using signed qword indices, gather float64 vector into\r\n VGATHERQPD ymm1 {k1}, vm64y AVX512F float64 vector ymm1 using k1 as completion mask.\r\n EVEX.512.66.0F38.W1 93 /vsib T1S V/V AVX512F Using signed qword indices, gather float64 vector into\r\n VGATHERQPD zmm1 {k1}, vm64z float64 vector zmm1 using k1 as completion mask.\r\n\r\n\r\n\r\nInstruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n BaseReg (R): VSIB:base,\r\n T1S ModRM:reg (w) NA NA\r\n VectorReg(R): VSIB:index\r\n\r\nDescription\r\nA set of 8 single-precision/double-precision faulting-point memory locations pointed by base address BASE_ADDR\r\nand index vector V_INDEX with scale SCALE are gathered. The result is written into vector a register. The elements\r\nare specified via the VSIB (i.e., the index register is a vector register, holding packed indices). Elements will only be\r\nloaded if their corresponding mask bit is one. If an element's mask bit is not set, the corresponding element of the\r\ndestination register is left unchanged. The entire mask register will be set to zero by this instruction unless it trig-\r\ngers an exception.\r\nThis instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception\r\nis triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination\r\nregister and the mask register (k1) are partially updated; those elements that have been gathered are placed into\r\nthe destination register and have their mask bits set to zero. If any traps or interrupts are pending from already\r\ngathered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruc-\r\ntion breakpoint is not re-triggered when the instruction is continued.\r\nIf the data element size is less than the index element size, the higher part of the destination register and the mask\r\nregister do not correspond to any elements being gathered. This instruction sets those higher parts to zero. It may\r\nupdate these unused elements to one or both of those registers even if the instruction triggers an exception, and\r\neven if the instruction triggers the exception before gathering any elements.\r\nNote that:\r\n. The values may be read from memory in any order. Memory ordering with other instructions follows the Intel-\r\n 64 memory-ordering model.\r\n. Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all\r\n elements closer to the LSB of the destination zmm will be completed (and non-faulting). Individual elements\r\n closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered\r\n in the conventional order.\r\n\r\n\r\n\r\n\r\n\r\n. Elements may be gathered in any order, but faults must be delivered in a right-to left order; thus, elements to\r\n the left of a faulting one may be gathered before the fault is delivered. A given implementation of this\r\n instruction is repeatable - given the same input values and architectural state, the same set of elements to the\r\n left of the faulting one will be gathered.\r\n. This instruction does not perform AC checks, and so will never deliver an AC fault.\r\n. Not valid with 16-bit effective addresses. Will deliver a #UD fault.\r\nNote that the presence of VSIB byte is enforced in this instruction. Hence, the instruction will #UD fault if\r\nModRM.rm is different than 100b.\r\nThis instruction has special disp8*N and alignment rules. N is considered to be the size of a single vector element.\r\nThe scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-bit\r\nmode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits\r\nare ignored.\r\nThe instruction will #UD fault if the destination vector zmm1 is the same as index vector VINDEX. The instruction\r\nwill #UD fault if the k0 mask register is specified.\r\n\r\nOperation\r\nBASE_ADDR stands for the memory operand base address (a GPR); may not exist\r\nVINDEX stands for the memory operand vector of indices (a ZMM register)\r\nSCALE stands for the memory operand scalar (1, 2, 4 or 8)\r\nDISP is the optional 1, 2 or 4 byte displacement\r\n\r\nVGATHERQPS (EVEX encoded version)\r\n(KL, VL) = (2, 64), (4, 128), (8, 256)\r\nFOR j <- 0 TO KL-1\r\n\r\n i <- j * 32\r\n k <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <-\r\n MEM[BASE_ADDR + (VINDEX[k+63:k]) * SCALE + DISP]\r\n k1[j] <- 0\r\n ELSE *DEST[i+31:i] <- remains unchanged*\r\n FI;\r\nENDFOR\r\nk1[MAX_KL-1:KL] <- 0\r\nDEST[MAX_VL-1:VL/2] <- 0\r\n\r\nVGATHERQPD (EVEX encoded version)\r\n\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- MEM[BASE_ADDR + (VINDEX[i+63:i]) * SCALE + DISP]\r\n k1[j] <- 0\r\n ELSE *DEST[i+63:i] <- remains unchanged*\r\n FI;\r\nENDFOR\r\nk1[MAX_KL-1:KL] <- 0\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVGATHERQPD __m512d _mm512_i64gather_pd( __m512i vdx, void * base, int scale);\r\nVGATHERQPD __m512d _mm512_mask_i64gather_pd(__m512d s, __mmask8 k, __m512i vdx, void * base, int scale);\r\nVGATHERQPD __m256d _mm256_mask_i64gather_pd(__m256d s, __mmask8 k, __m256i vdx, void * base, int scale);\r\nVGATHERQPD __m128d _mm_mask_i64gather_pd(__m128d s, __mmask8 k, __m128i vdx, void * base, int scale);\r\nVGATHERQPS __m256 _mm512_i64gather_ps( __m512i vdx, void * base, int scale);\r\nVGATHERQPS __m256 _mm512_mask_i64gather_ps(__m256 s, __mmask16 k, __m512i vdx, void * base, int scale);\r\nVGATHERQPS __m128 _mm256_mask_i64gather_ps(__m128 s, __mmask8 k, __m256i vdx, void * base, int scale);\r\nVGATHERQPS __m128 _mm_mask_i64gather_ps(__m128 s, __mmask8 k, __m128i vdx, void * base, int scale);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type E12.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VGATHERQPS"
},
{
"description": "VGETEXPPD-Convert Exponents of Packed DP FP Values to DP FP Values\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F38.W1 42 /r FV V/V AVX512VL Convert the exponent of packed double-precision floating-point\r\n VGETEXPPD xmm1 {k1}{z}, AVX512F values in the source operand to DP FP results representing\r\n xmm2/m128/m64bcst unbiased integer exponents and stores the results in the\r\n destination register.\r\n EVEX.256.66.0F38.W1 42 /r FV V/V AVX512VL Convert the exponent of packed double-precision floating-point\r\n VGETEXPPD ymm1 {k1}{z}, AVX512F values in the source operand to DP FP results representing\r\n ymm2/m256/m64bcst unbiased integer exponents and stores the results in the\r\n destination register.\r\n EVEX.512.66.0F38.W1 42 /r FV V/V AVX512F Convert the exponent of packed double-precision floating-point\r\n VGETEXPPD zmm1 {k1}{z}, values in the source operand to DP FP results representing\r\n zmm2/m512/m64bcst{sae} unbiased integer exponents and stores the results in the\r\n destination under writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nExtracts the biased exponents from the normalized DP FP representation of each qword data element of the source\r\noperand (the second operand) as unbiased signed integer value, or convert the denormal representation of input\r\ndata to unbiased negative integer values. Each integer value of the unbiased exponent is converted to double-\r\nprecision FP value and written to the corresponding qword elements of the destination operand (the first operand)\r\nas DP FP numbers.\r\nThe destination operand is a ZMM/YMM/XMM register and updated under the writemask. The source operand can\r\nbe a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from\r\na 64-bit memory location.\r\nEVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\nEach GETEXP operation converts the exponent value into a FP number (permitting input value in denormal repre-\r\nsentation). Special cases of input values are listed in Table 5-7.\r\nThe formula is:\r\nGETEXP(x) = floor(log2(|x|))\r\nNotation floor(x) stands for the greatest integer not exceeding real number x.\r\n\r\n Table 5-7. VGETEXPPD/SD Special Cases\r\n Input Operand Result Comments\r\n src1 = NaN QNaN(src1) No Exceptions\r\n 0 < |src1| < INF floor(log2(|src1|))\r\n | src1| = +INF +INF\r\n | src1| = 0 -INF\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nNormalizeExpTinyDPFP(SRC[63:0])\r\n{\r\n // Jbit is the hidden integral bit of a FP number. In case of denormal number it has the value of ZERO.\r\n Src.Jbit <- 0;\r\n Dst.exp <- 1;\r\n Dst.fraction <- SRC[51:0];\r\n WHILE(Src.Jbit = 0)\r\n {\r\n Src.Jbit <- Dst.fraction[51]; // Get the fraction MSB\r\n Dst.fraction <- Dst.fraction << 1 ; // One bit shift left\r\n Dst.exp-- ; // Decrement the exponent\r\n }\r\n Dst.fraction <- 0; // zero out fraction bits\r\n Dst.sign <- 1; // Return negative sign\r\n TMP[63:0] <- MXCSR.DAZ? 0 : (Dst.sign << 63) OR (Dst.exp << 52) OR (Dst.fraction) ;\r\n Return (TMP[63:0]);\r\n}\r\n\r\nConvertExpDPFP(SRC[63:0])\r\n{\r\n Src.sign <- 0; // Zero out sign bit\r\n Src.exp <- SRC[62:52];\r\n Src.fraction <- SRC[51:0];\r\n // Check for NaN\r\n IF (SRC = NaN)\r\n {\r\n IF ( SRC = SNAN ) SET IE;\r\n Return QNAN(SRC);\r\n }\r\n // Check for +INF\r\n IF (SRC = +INF) Return (SRC);\r\n\r\n // check if zero operand\r\n IF ((Src.exp = 0) AND ((Src.fraction = 0) OR (MXCSR.DAZ = 1))) Return (-INF);\r\n }\r\n ELSE // check if denormal operand (notice that MXCSR.DAZ = 0)\r\n {\r\n IF ((Src.exp = 0) AND (Src.fraction != 0))\r\n {\r\n TMP[63:0] <- NormalizeExpTinyDPFP(SRC[63:0]) ; // Get Normalized Exponent\r\n Set #DE\r\n }\r\n ELSE // exponent value is correct\r\n {\r\n Dst.fraction <- 0; // zero out fraction bits\r\n TMP[63:0] <- (Src.sign << 63) OR (Src.exp << 52) OR (Src.fraction) ;\r\n }\r\n TMP <- SAR(TMP, 52) ; // Shift Arithmetic Right\r\n TMP <- TMP - 1023; // Subtract Bias\r\n Return CvtI2D(TMP) ; // Convert INT to Double-Precision FP number\r\n }\r\n}\r\n\r\n\r\n\r\n\r\nVGETEXPPD (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC *is memory*)\r\n THEN\r\n DEST[i+63:i] <-\r\n ConvertExpDPFP(SRC[63:0])\r\n ELSE\r\n DEST[i+63:i] <-\r\n ConvertExpDPFP(SRC[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVGETEXPPD __m512d _mm512_getexp_pd(__m512d a);\r\nVGETEXPPD __m512d _mm512_mask_getexp_pd(__m512d s, __mmask8 k, __m512d a);\r\nVGETEXPPD __m512d _mm512_maskz_getexp_pd( __mmask8 k, __m512d a);\r\nVGETEXPPD __m512d _mm512_getexp_round_pd(__m512d a, int sae);\r\nVGETEXPPD __m512d _mm512_mask_getexp_round_pd(__m512d s, __mmask8 k, __m512d a, int sae);\r\nVGETEXPPD __m512d _mm512_maskz_getexp_round_pd( __mmask8 k, __m512d a, int sae);\r\nVGETEXPPD __m256d _mm256_getexp_pd(__m256d a);\r\nVGETEXPPD __m256d _mm256_mask_getexp_pd(__m256d s, __mmask8 k, __m256d a);\r\nVGETEXPPD __m256d _mm256_maskz_getexp_pd( __mmask8 k, __m256d a);\r\nVGETEXPPD __m128d _mm_getexp_pd(__m128d a);\r\nVGETEXPPD __m128d _mm_mask_getexp_pd(__m128d s, __mmask8 k, __m128d a);\r\nVGETEXPPD __m128d _mm_maskz_getexp_pd( __mmask8 k, __m128d a);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Denormal\r\n\r\nOther Exceptions\r\nSee Exceptions Type E2.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VGETEXPPD"
},
{
"description": "VGETEXPPS-Convert Exponents of Packed SP FP Values to SP FP Values\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F38.W0 42 /r FV V/V AVX512VL Convert the exponent of packed single-precision floating-point\r\n VGETEXPPS xmm1 {k1}{z}, AVX512F values in the source operand to SP FP results representing\r\n xmm2/m128/m32bcst unbiased integer exponents and stores the results in the\r\n destination register.\r\n EVEX.256.66.0F38.W0 42 /r FV V/V AVX512VL Convert the exponent of packed single-precision floating-point\r\n VGETEXPPS ymm1 {k1}{z}, AVX512F values in the source operand to SP FP results representing\r\n ymm2/m256/m32bcst unbiased integer exponents and stores the results in the\r\n destination register.\r\n EVEX.512.66.0F38.W0 42 /r FV V/V AVX512F Convert the exponent of packed single-precision floating-point\r\n VGETEXPPS zmm1 {k1}{z}, values in the source operand to SP FP results representing\r\n zmm2/m512/m32bcst{sae} unbiased integer exponents and stores the results in the\r\n destination register.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nExtracts the biased exponents from the normalized SP FP representation of each dword element of the source\r\noperand (the second operand) as unbiased signed integer value, or convert the denormal representation of input\r\ndata to unbiased negative integer values. Each integer value of the unbiased exponent is converted to single-preci-\r\nsion FP value and written to the corresponding dword elements of the destination operand (the first operand) as SP\r\nFP numbers.\r\nThe destination operand is a ZMM/YMM/XMM register and updated under the writemask. The source operand can\r\nbe a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from\r\na 32-bit memory location.\r\nEVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\nEach GETEXP operation converts the exponent value into a FP number (permitting input value in denormal repre-\r\nsentation). Special cases of input values are listed in Table 5-8.\r\nThe formula is:\r\nGETEXP(x) = floor(log2(|x|))\r\nNotation floor(x) stands for maximal integer not exceeding real number x.\r\nSoftware usage of VGETEXPxx and VGETMANTxx instructions generally involve a combination of GETEXP operation\r\nand GETMANT operation (see VGETMANTPD). Thus VGETEXPxx instruction do not require software to handle SIMD\r\nFP exceptions.\r\n\r\n Table 5-8. VGETEXPPS/SS Special Cases\r\n Input Operand Result Comments\r\n src1 = NaN QNaN(src1) No Exceptions\r\n 0 < |src1| < INF floor(log2(|src1|))\r\n | src1| = +INF +INF\r\n | src1| = 0 -INF\r\n\r\n\r\n\r\n\r\n\r\nFigure 5-14 illustrates the VGETEXPPS functionality on input values with normalized representation.\r\n\r\n\r\n\r\n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0\r\n s exp Fraction\r\n Src = 2^1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\r\n\r\n SAR Src, 23 = 080h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0\r\n\r\n -Bias 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1\r\n\r\n Tmp - Bias = 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1\r\n\r\n Cvt_PI2PS(01h) = 2^0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\r\n\r\n\r\n\r\n\r\n Figure 5-14. VGETEXPPS Functionality On Normal Input values\r\n\r\n\r\nOperation\r\nNormalizeExpTinySPFP(SRC[31:0])\r\n{\r\n // Jbit is the hidden integral bit of a FP number. In case of denormal number it has the value of ZERO.\r\n Src.Jbit <- 0;\r\n Dst.exp <- 1;\r\n Dst.fraction <- SRC[22:0];\r\n WHILE(Src.Jbit = 0)\r\n {\r\n Src.Jbit <- Dst.fraction[22]; // Get the fraction MSB\r\n Dst.fraction <- Dst.fraction << 1 ; // One bit shift left\r\n Dst.exp-- ; // Decrement the exponent\r\n }\r\n Dst.fraction <- 0; // zero out fraction bits\r\n Dst.sign <- 1; // Return negative sign\r\n TMP[31:0] <- MXCSR.DAZ? 0 : (Dst.sign << 31) OR (Dst.exp << 23) OR (Dst.fraction) ;\r\n Return (TMP[31:0]);\r\n}\r\nConvertExpSPFP(SRC[31:0])\r\n{\r\n Src.sign <- 0; // Zero out sign bit\r\n Src.exp <- SRC[30:23];\r\n Src.fraction <- SRC[22:0];\r\n // Check for NaN\r\n IF (SRC = NaN)\r\n {\r\n IF ( SRC = SNAN ) SET IE;\r\n Return QNAN(SRC);\r\n }\r\n // Check for +INF\r\n IF (SRC = +INF) Return (SRC);\r\n\r\n // check if zero operand\r\n IF ((Src.exp = 0) AND ((Src.fraction = 0) OR (MXCSR.DAZ = 1))) Return (-INF);\r\n }\r\n ELSE // check if denormal operand (notice that MXCSR.DAZ = 0)\r\n {\r\n\r\n\r\n\r\n IF ((Src.exp = 0) AND (Src.fraction != 0))\r\n {\r\n TMP[31:0] <- NormalizeExpTinySPFP(SRC[31:0]) ; // Get Normalized Exponent\r\n Set #DE\r\n }\r\n ELSE // exponent value is correct\r\n {\r\n Dst.fraction <- 0; // zero out fraction bits\r\n TMP[31:0] <- (Src.sign << 31) OR (Src.exp << 23) OR (Src.fraction) ;\r\n }\r\n TMP <- SAR(TMP, 23) ; // Shift Arithmetic Right\r\n TMP <- TMP - 127; // Subtract Bias\r\n Return CvtI2D(TMP) ; // Convert INT to Single-Precision FP number\r\n }\r\n}\r\n\r\nVGETEXPPS (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC *is memory*)\r\n THEN\r\n DEST[i+31:i] <-\r\n ConvertExpSPFP(SRC[31:0])\r\n ELSE\r\n DEST[i+31:i] <-\r\n ConvertExpSPFP(SRC[i+31:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVGETEXPPS __m512 _mm512_getexp_ps( __m512 a);\r\nVGETEXPPS __m512 _mm512_mask_getexp_ps(__m512 s, __mmask16 k, __m512 a);\r\nVGETEXPPS __m512 _mm512_maskz_getexp_ps( __mmask16 k, __m512 a);\r\nVGETEXPPS __m512 _mm512_getexp_round_ps( __m512 a, int sae);\r\nVGETEXPPS __m512 _mm512_mask_getexp_round_ps(__m512 s, __mmask16 k, __m512 a, int sae);\r\nVGETEXPPS __m512 _mm512_maskz_getexp_round_ps( __mmask16 k, __m512 a, int sae);\r\nVGETEXPPS __m256 _mm256_getexp_ps(__m256 a);\r\nVGETEXPPS __m256 _mm256_mask_getexp_ps(__m256 s, __mmask8 k, __m256 a);\r\nVGETEXPPS __m256 _mm256_maskz_getexp_ps( __mmask8 k, __m256 a);\r\nVGETEXPPS __m128 _mm_getexp_ps(__m128 a);\r\nVGETEXPPS __m128 _mm_mask_getexp_ps(__m128 s, __mmask8 k, __m128 a);\r\nVGETEXPPS __m128 _mm_maskz_getexp_ps( __mmask8 k, __m128 a);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Denormal\r\n\r\nOther Exceptions\r\nSee Exceptions Type E2.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VGETEXPPS"
},
{
"description": "VGETEXPSD-Convert Exponents of Scalar DP FP Values to DP FP Value\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.LIG.66.0F38.W1 43 /r T1S V/V AVX512F Convert the biased exponent (bits 62:52) of the low double-\r\n VGETEXPSD xmm1 {k1}{z}, precision floating-point value in xmm3/m64 to a DP FP value\r\n xmm2, xmm3/m64{sae} representing unbiased integer exponent. Stores the result to\r\n the low 64-bit of xmm1 under the writemask k1 and merge\r\n with the other elements of xmm2.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nExtracts the biased exponent from the normalized DP FP representation of the low qword data element of the\r\nsource operand (the third operand) as unbiased signed integer value, or convert the denormal representation of\r\ninput data to unbiased negative integer values. The integer value of the unbiased exponent is converted to double-\r\nprecision FP value and written to the destination operand (the first operand) as DP FP numbers. Bits (127:64) of\r\nthe XMM register destination are copied from corresponding bits in the first source operand.\r\nThe destination must be a XMM register, the source operand can be a XMM register or a float64 memory location.\r\nThe low quadword element of the destination operand is conditionally updated with writemask k1.\r\nEach GETEXP operation converts the exponent value into a FP number (permitting input value in denormal repre-\r\nsentation). Special cases of input values are listed in Table 5-7.\r\nThe formula is:\r\nGETEXP(x) = floor(log2(|x|))\r\nNotation floor(x) stands for maximal integer not exceeding real number x.\r\n\r\nOperation\r\n// NormalizeExpTinyDPFP(SRC[63:0]) is defined in the Operation section of VGETEXPPD\r\n\r\n// ConvertExpDPFP(SRC[63:0]) is defined in the Operation section of VGETEXPPD\r\n\r\nVGETEXPSD (EVEX encoded version)\r\nIF k1[0] OR *no writemask*\r\n THEN DEST[63:0] <-\r\n ConvertExpDPFP(SRC2[63:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[63:0] <- 0\r\n FI\r\nFI;\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVGETEXPSD __m128d _mm_getexp_sd( __m128d a, __m128d b);\r\nVGETEXPSD __m128d _mm_mask_getexp_sd(__m128d s, __mmask8 k, __m128d a, __m128d b);\r\nVGETEXPSD __m128d _mm_maskz_getexp_sd( __mmask8 k, __m128d a, __m128d b);\r\nVGETEXPSD __m128d _mm_getexp_round_sd( __m128d a, __m128d b, int sae);\r\nVGETEXPSD __m128d _mm_mask_getexp_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int sae);\r\nVGETEXPSD __m128d _mm_maskz_getexp_round_sd( __mmask8 k, __m128d a, __m128d b, int sae);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Denormal\r\n\r\nOther Exceptions\r\nSee Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VGETEXPSD"
},
{
"description": "VGETEXPSS-Convert Exponents of Scalar SP FP Values to SP FP Value\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.LIG.66.0F38.W0 43 /r T1S V/V AVX512F Convert the biased exponent (bits 30:23) of the low single-\r\n VGETEXPSS xmm1 {k1}{z}, xmm2, precision floating-point value in xmm3/m32 to a SP FP\r\n xmm3/m32{sae} value representing unbiased integer exponent. Stores the\r\n result to xmm1 under the writemask k1 and merge with the\r\n other elements of xmm2.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nExtracts the biased exponent from the normalized SP FP representation of the low doubleword data element of the\r\nsource operand (the third operand) as unbiased signed integer value, or convert the denormal representation of\r\ninput data to unbiased negative integer values. The integer value of the unbiased exponent is converted to single-\r\nprecision FP value and written to the destination operand (the first operand) as SP FP numbers. Bits (127:32) of\r\nthe XMM register destination are copied from corresponding bits in the first source operand.\r\nThe destination must be a XMM register, the source operand can be a XMM register or a float32 memory location.\r\nThe the low doubleword element of the destination operand is conditionally updated with writemask k1.\r\nEach GETEXP operation converts the exponent value into a FP number (permitting input value in denormal repre-\r\nsentation). Special cases of input values are listed in Table 5-8.\r\nThe formula is:\r\nGETEXP(x) = floor(log2(|x|))\r\nNotation floor(x) stands for maximal integer not exceeding real number x.\r\nSoftware usage of VGETEXPxx and VGETMANTxx instructions generally involve a combination of GETEXP operation\r\nand GETMANT operation (see VGETMANTPD). Thus VGETEXPxx instruction do not require software to handle SIMD\r\nFP exceptions.\r\n\r\nOperation\r\n// NormalizeExpTinySPFP(SRC[31:0]) is defined in the Operation section of VGETEXPPS\r\n\r\n// ConvertExpSPFP(SRC[31:0]) is defined in the Operation section of VGETEXPPS\r\n\r\nVGETEXPSS (EVEX encoded version)\r\nIF k1[0] OR *no writemask*\r\n THEN DEST[31:0] <-\r\n ConvertExpDPFP(SRC2[31:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[31:0]<- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[127:32] <- SRC1[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVGETEXPSS __m128 _mm_getexp_ss( __m128 a, __m128 b);\r\nVGETEXPSS __m128 _mm_mask_getexp_ss(__m128 s, __mmask8 k, __m128 a, __m128 b);\r\nVGETEXPSS __m128 _mm_maskz_getexp_ss( __mmask8 k, __m128 a, __m128 b);\r\nVGETEXPSS __m128 _mm_getexp_round_ss( __m128 a, __m128 b, int sae);\r\nVGETEXPSS __m128 _mm_mask_getexp_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int sae);\r\nVGETEXPSS __m128 _mm_maskz_getexp_round_ss( __mmask8 k, __m128 a, __m128 b, int sae);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Denormal\r\n\r\nOther Exceptions\r\nSee Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VGETEXPSS"
},
{
"description": "VGETMANTPD-Extract Float64 Vector of Normalized Mantissas from Float64 Vector\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F3A.W1 26 /r ib FV V/V AVX512VL Get Normalized Mantissa from float64 vector\r\n VGETMANTPD xmm1 {k1}{z}, AVX512F xmm2/m128/m64bcst and store the result in xmm1, using\r\n xmm2/m128/m64bcst, imm8 imm8 for sign control and mantissa interval normalization,\r\n under writemask.\r\n EVEX.256.66.0F3A.W1 26 /r ib FV V/V AVX512VL Get Normalized Mantissa from float64 vector\r\n VGETMANTPD ymm1 {k1}{z}, AVX512F ymm2/m256/m64bcst and store the result in ymm1, using\r\n ymm2/m256/m64bcst, imm8 imm8 for sign control and mantissa interval normalization,\r\n under writemask.\r\n EVEX.512.66.0F3A.W1 26 /r ib FV V/V AVX512F Get Normalized Mantissa from float64 vector\r\n VGETMANTPD zmm1 {k1}{z}, zmm2/m512/m64bcst and store the result in zmm1, using\r\n zmm2/m512/m64bcst{sae}, imm8 for sign control and mantissa interval normalization,\r\n imm8 under writemask.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FVI ModRM:reg (w) ModRM:r/m (r) Imm8 NA\r\n\r\nDescription\r\nConvert double-precision floating values in the source operand (the second operand) to DP FP values with the\r\nmantissa normalization and sign control specified by the imm8 byte, see Figure 5-15. The converted results are\r\nwritten to the destination operand (the first operand) using writemask k1. The normalized mantissa is specified by\r\ninterv (imm8[1:0]) and the sign control (sc) is specified by bits 3:2 of the immediate byte.\r\nThe destination operand is a ZMM/YMM/XMM register updated under the writemask. The source operand can be a\r\nZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 64-\r\nbit memory location.\r\n\r\n\r\n\r\n\r\n 7 6 5 4 3 2 1 0\r\n\r\n imm8 Must Be Zero Sign Control (SC) Normaiization Interval\r\n\r\n\r\n\r\n Imm8[1:0] = 00b : Interval is [ 1, 2)\r\n Imm8[3:2] = 00b : sign(SRC) Imm8[1:0] = 01b : Interval is [1/2, 2)\r\n Imm8[3:2] = 01b : 0 Imm8[1:0] = 10b : Interval is [ 1/2, 1)\r\n Imm8[3] = 1b : qNan_Indefinite if sign(SRC) != 0, regardless of imm8[2]. Imm8[1:0] = 11b : Interval is [3/4, 3/2)\r\n\r\n\r\n\r\n Figure 5-15. Imm8 Controls for VGETMANTPD/SD/PS/SS\r\n\r\n\r\nFor each input DP FP value x, The conversion operation is:\r\n\r\n GetMant(x) = +-2k|x.significand|\r\nwhere:\r\n\r\n 1 <= |x.significand| < 2\r\n\r\n\r\nUnbiased exponent k depends on the interval range defined by interv and whether the exponent of the source is\r\neven or odd. The sign of the final result is determined by sc and the source sign.\r\n\r\n\r\n\r\n\r\nIf interv != 0 then k = -1, otherwise K = 0. The encoded value of imm8[1:0] and sign control are shown in\r\nFigure 5-15.\r\nEach converted DP FP result is encoded according to the sign control, the unbiased exponent k (adding bias) and a\r\nmantissa normalized to the range specified by interv.\r\nThe GetMant() function follows Table 5-9 when dealing with floating-point special numbers.\r\nThis instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1\r\nare computed and stored into the destination. Elements in zmm1 with the corresponding bit clear in k1 retain their\r\nprevious values.\r\nNote: EVEX.vvvv is reserved and must be 1111b; otherwise instructions will #UD.\r\n\r\n Table 5-9. GetMant() Special Float Values Behavior\r\n Input Result Exceptions / Comments\r\n NaN QNaN(SRC) Ignore interv\r\n If (SRC = SNaN) then #IE\r\n +inf 1.0 Ignore interv\r\n +0 1.0 Ignore interv\r\n -0 IF (SC[0]) THEN +1.0 Ignore interv\r\n ELSE -1.0\r\n -inf IF (SC[1]) THEN {QNaN_Indefinite} Ignore interv\r\n ELSE { If (SC[1]) then #IE\r\n IF (SC[0]) THEN +1.0\r\n ELSE -1.0\r\n negative SC[1] ? QNaN_Indefinite : Getmant(SRC) If (SC[1]) then #IE\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nGetNormalizeMantissaDP(SRC[63:0], SignCtrl[1:0], Interv[1:0])\r\n{\r\n // Extracting the SRC sign, exponent and mantissa fields\r\n Dst.sign <- SignCtrl[0] ? 0 : Src[63]; // Get sign bit\r\n Dst.exp <- SRC[62:52]; ; Get original exponent value\r\n Dst.fraction <- SRC[51:0];; Get original fraction value\r\n ZeroOperand <- (Dst.exp = 0) AND (Dst.fraction = 0);\r\n DenormOperand <- (Dst.exp = 0h) AND (Dst.fraction != 0);\r\n InfiniteOperand <- (Dst.exp = 07FFh) AND (Dst.fraction = 0);\r\n NaNOperand <- (Dst.exp = 07FFh) AND (Dst.fraction != 0);\r\n // Check for NAN operand\r\n IF (NaNOperand)\r\n { IF (SRC = SNaN) {Set #IE;}\r\n Return QNAN(SRC);\r\n }\r\n // Check for Zero and Infinite operands\r\n IF ((ZeroOperand) OR (InfiniteOperand)\r\n { Dst.exp <- 03FFh; // Override exponent with BIAS\r\n Return ((Dst.sign<<63) | (Dst.exp<<52) | (Dst.fraction));\r\n }\r\n // Check for negative operand (including -0.0)\r\n IF ((Src[63] = 1) AND SignCtrl[1])\r\n { Set #IE;\r\n Return QNaN_Indefinite;\r\n }\r\n // Checking for denormal operands\r\n IF (DenormOperand)\r\n { IF (MXCSR.DAZ=1) Dst.fraction <- 0;// Zero out fraction\r\n ELSE\r\n { // Jbit is the hidden integral bit. Zero in case of denormal operand.\r\n Src.Jbit <- 0; // Zero Src Jbit\r\n Dst.exp <- 03FFh; // Override exponent with BIAS\r\n WHILE (Src.Jbit = 0) { // normalize mantissa\r\n Src.Jbit <- Dst.fraction[51]; // Get the fraction MSB\r\n Dst.fraction <- (Dst.fraction << 1); // Start normalizing the mantissa\r\n Dst.exp-- ; // Adjust the exponent\r\n }\r\n SET #DE; // Set DE bit\r\n }\r\n } // At this point, Dst.fraction is normalized.\r\n // Checking for exponent response\r\n Unbiased.exp <- Dst.exp - 03FFh; // subtract the bias from exponent\r\n IsOddExp <- Unbiased.exp[0]; // recognized unbiased ODD exponent\r\n SignalingBit <- Dst.fraction[51];\r\n CASE (interv[1:0])\r\n 00: Dst.exp <- 03FFh; // This is the bias\r\n 01: Dst.exp <- (IsOddExp) ? 03FEh : 03FFh; // either bias-1, or bias\r\n 10: Dst.exp <- 03FEh; // bias-1\r\n 11: Dst.exp <- (SignalingBit) ? 03FEh : 03FFh; // either bias-1, or bias\r\n ESCA\r\n // At this point Dst.exp has the correct result. Form the final destination\r\n DEST[63:0] <- (Dst.sign << 63) OR (Dst.exp << 52) OR (Dst.fraction);\r\n Return (DEST);\r\n\r\n\r\n\r\n}\r\n\r\nSignCtrl[1:0] <- IMM8[3:2];\r\nInterv[1:0] <- IMM8[1:0];\r\n\r\nVGETMANTPD (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC *is memory*)\r\n THEN\r\n DEST[i+63:i] <- GetNormalizedMantissaDP(SRC[63:0], sc, interv)\r\n ELSE\r\n DEST[i+63:i] <- GetNormalizedMantissaDP(SRC[i+63:i], sc, interv)\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVGETMANTPD __m512d _mm512_getmant_pd( __m512d a, enum intv, enum sgn);\r\nVGETMANTPD __m512d _mm512_mask_getmant_pd(__m512d s, __mmask8 k, __m512d a, enum intv, enum sgn);\r\nVGETMANTPD __m512d _mm512_maskz_getmant_pd( __mmask8 k, __m512d a, enum intv, enum sgn);\r\nVGETMANTPD __m512d _mm512_getmant_round_pd( __m512d a, enum intv, enum sgn, int r);\r\nVGETMANTPD __m512d _mm512_mask_getmant_round_pd(__m512d s, __mmask8 k, __m512d a, enum intv, enum sgn, int r);\r\nVGETMANTPD __m512d _mm512_maskz_getmant_round_pd( __mmask8 k, __m512d a, enum intv, enum sgn, int r);\r\nVGETMANTPD __m256d _mm256_getmant_pd( __m256d a, enum intv, enum sgn);\r\nVGETMANTPD __m256d _mm256_mask_getmant_pd(__m256d s, __mmask8 k, __m256d a, enum intv, enum sgn);\r\nVGETMANTPD __m256d _mm256_maskz_getmant_pd( __mmask8 k, __m256d a, enum intv, enum sgn);\r\nVGETMANTPD __m128d _mm_getmant_pd( __m128d a, enum intv, enum sgn);\r\nVGETMANTPD __m128d _mm_mask_getmant_pd(__m128d s, __mmask8 k, __m128d a, enum intv, enum sgn);\r\nVGETMANTPD __m128d _mm_maskz_getmant_pd( __mmask8 k, __m128d a, enum intv, enum sgn);\r\n\r\nSIMD Floating-Point Exceptions\r\nDenormal, Invalid\r\n\r\nOther Exceptions\r\nSee Exceptions Type E2.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VGETMANTPD"
},
{
"description": "VGETMANTPS-Extract Float32 Vector of Normalized Mantissas from Float32 Vector\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F3A.W0 26 /r ib FV V/V AVX512VL Get normalized mantissa from float32 vector\r\n VGETMANTPS xmm1 {k1}{z}, AVX512F xmm2/m128/m32bcst and store the result in xmm1, using\r\n xmm2/m128/m32bcst, imm8 imm8 for sign control and mantissa interval normalization,\r\n under writemask.\r\n EVEX.256.66.0F3A.W0 26 /r ib FV V/V AVX512VL Get normalized mantissa from float32 vector\r\n VGETMANTPS ymm1 {k1}{z}, AVX512F ymm2/m256/m32bcst and store the result in ymm1, using\r\n ymm2/m256/m32bcst, imm8 imm8 for sign control and mantissa interval normalization,\r\n under writemask.\r\n EVEX.512.66.0F3A.W0 26 /r ib FV V/V AVX512F Get normalized mantissa from float32 vector\r\n VGETMANTPS zmm1 {k1}{z}, zmm2/m512/m32bcst and store the result in zmm1, using\r\n zmm2/m512/m32bcst{sae}, imm8 for sign control and mantissa interval normalization,\r\n imm8 under writemask.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FVI ModRM:reg (w) ModRM:r/m (r) Imm8 NA\r\n\r\nDescription\r\nConvert single-precision floating values in the source operand (the second operand) to SP FP values with the\r\nmantissa normalization and sign control specified by the imm8 byte, see Figure 5-15. The converted results are\r\nwritten to the destination operand (the first operand) using writemask k1. The normalized mantissa is specified by\r\ninterv (imm8[1:0]) and the sign control (sc) is specified by bits 3:2 of the immediate byte.\r\nThe destination operand is a ZMM/YMM/XMM register updated under the writemask. The source operand can be a\r\nZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32-\r\nbit memory location.\r\nFor each input SP FP value x, The conversion operation is:\r\n\r\n GetMant(x) = +-2k|x.significand|\r\nwhere:\r\n\r\n 1 <= |x.significand| < 2\r\n\r\n\r\nUnbiased exponent k depends on the interval range defined by interv and whether the exponent of the source is\r\neven or odd. The sign of the final result is determined by sc and the source sign.\r\n\r\nif interv != 0 then k = -1, otherwise K = 0. The encoded value of imm8[1:0] and sign control are shown\r\nin Figure 5-15.\r\nEach converted SP FP result is encoded according to the sign control, the unbiased exponent k (adding bias) and a\r\nmantissa normalized to the range specified by interv.\r\nThe GetMant() function follows Table 5-9 when dealing with floating-point special numbers.\r\nThis instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1\r\nare computed and stored into the destination. Elements in zmm1 with the corresponding bit clear in k1 retain their\r\nprevious values.\r\nNote: EVEX.vvvv is reserved and must be 1111b, VEX.L must be 0; otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nGetNormalizeMantissaSP(SRC[31:0] , SignCtrl[1:0], Interv[1:0])\r\n{\r\n // Extracting the SRC sign, exponent and mantissa fields\r\n Dst.sign <- SignCtrl[0] ? 0 : Src[31]; // Get sign bit\r\n Dst.exp <- SRC[30:23]; ; Get original exponent value\r\n Dst.fraction <- SRC[22:0];; Get original fraction value\r\n ZeroOperand <- (Dst.exp = 0) AND (Dst.fraction = 0);\r\n DenormOperand <- (Dst.exp = 0h) AND (Dst.fraction != 0);\r\n InfiniteOperand <- (Dst.exp = 0FFh) AND (Dst.fraction = 0);\r\n NaNOperand <- (Dst.exp = 0FFh) AND (Dst.fraction != 0);\r\n // Check for NAN operand\r\n IF (NaNOperand)\r\n { IF (SRC = SNaN) {Set #IE;}\r\n Return QNAN(SRC);\r\n }\r\n // Check for Zero and Infinite operands\r\n IF ((ZeroOperand) OR (InfiniteOperand)\r\n { Dst.exp <- 07Fh; // Override exponent with BIAS\r\n Return ((Dst.sign<<31) | (Dst.exp<<23) | (Dst.fraction));\r\n }\r\n // Check for negative operand (including -0.0)\r\n IF ((Src[31] = 1) AND SignCtrl[1])\r\n { Set #IE;\r\n Return QNaN_Indefinite;\r\n }\r\n // Checking for denormal operands\r\n IF (DenormOperand)\r\n { IF (MXCSR.DAZ=1) Dst.fraction <- 0;// Zero out fraction\r\n ELSE\r\n { // Jbit is the hidden integral bit. Zero in case of denormal operand.\r\n Src.Jbit <- 0; // Zero Src Jbit\r\n Dst.exp <- 07Fh; // Override exponent with BIAS\r\n WHILE (Src.Jbit = 0) { // normalize mantissa\r\n Src.Jbit <- Dst.fraction[22]; // Get the fraction MSB\r\n Dst.fraction <- (Dst.fraction << 1); // Start normalizing the mantissa\r\n Dst.exp-- ; // Adjust the exponent\r\n }\r\n SET #DE; // Set DE bit\r\n }\r\n } // At this point, Dst.fraction is normalized.\r\n // Checking for exponent response\r\n Unbiased.exp <- Dst.exp - 07Fh; // subtract the bias from exponent\r\n IsOddExp <- Unbiased.exp[0]; // recognized unbiased ODD exponent\r\n SignalingBit <- Dst.fraction[22];\r\n CASE (interv[1:0])\r\n 00: Dst.exp <- 07Fh; // This is the bias\r\n 01: Dst.exp <- (IsOddExp) ? 07Eh : 07Fh; // either bias-1, or bias\r\n 10: Dst.exp <- 07Eh; // bias-1\r\n 11: Dst.exp <- (SignalingBit) ? 07Eh : 07Fh; // either bias-1, or bias\r\n ESCA\r\n\r\n // Form the final destination\r\n DEST[31:0] <- (Dst.sign << 31) OR (Dst.exp << 23) OR (Dst.fraction);\r\n\r\n\r\n\r\n Return (DEST);\r\n}\r\n\r\nSignCtrl[1:0] <- IMM8[3:2];\r\nInterv[1:0] <- IMM8[1:0];\r\n\r\nVGETMANTPS (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC *is memory*)\r\n THEN\r\n DEST[i+31:i] <- GetNormalizedMantissaSP(SRC[31:0], sc, interv)\r\n ELSE\r\n DEST[i+31:i] <- GetNormalizedMantissaSP(SRC[i+31:i], sc, interv)\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVGETMANTPS __m512 _mm512_getmant_ps( __m512 a, enum intv, enum sgn);\r\nVGETMANTPS __m512 _mm512_mask_getmant_ps(__m512 s, __mmask16 k, __m512 a, enum intv, enum sgn;\r\nVGETMANTPS __m512 _mm512_maskz_getmant_ps(__mmask16 k, __m512 a, enum intv, enum sgn);\r\nVGETMANTPS __m512 _mm512_getmant_round_ps( __m512 a, enum intv, enum sgn, int r);\r\nVGETMANTPS __m512 _mm512_mask_getmant_round_ps(__m512 s, __mmask16 k, __m512 a, enum intv, enum sgn, int r);\r\nVGETMANTPS __m512 _mm512_maskz_getmant_round_ps(__mmask16 k, __m512 a, enum intv, enum sgn, int r);\r\nVGETMANTPS __m256 _mm256_getmant_ps( __m256 a, enum intv, enum sgn);\r\nVGETMANTPS __m256 _mm256_mask_getmant_ps(__m256 s, __mmask8 k, __m256 a, enum intv, enum sgn);\r\nVGETMANTPS __m256 _mm256_maskz_getmant_ps( __mmask8 k, __m256 a, enum intv, enum sgn);\r\nVGETMANTPS __m128 _mm_getmant_ps( __m128 a, enum intv, enum sgn);\r\nVGETMANTPS __m128 _mm_mask_getmant_ps(__m128 s, __mmask8 k, __m128 a, enum intv, enum sgn);\r\nVGETMANTPS __m128 _mm_maskz_getmant_ps( __mmask8 k, __m128 a, enum intv, enum sgn);\r\n\r\nSIMD Floating-Point Exceptions\r\nDenormal, Invalid\r\n\r\nOther Exceptions\r\nSee Exceptions Type E2.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VGETMANTPS"
},
{
"description": "VGETMANTSD-Extract Float64 of Normalized Mantissas from Float64 Scalar\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.LIG.66.0F3A.W1 27 /r ib T1S V/V AVX512F Extract the normalized mantissa of the low float64\r\n VGETMANTSD xmm1 {k1}{z}, xmm2, element in xmm3/m64 using imm8 for sign control and\r\n xmm3/m64{sae}, imm8 mantissa interval normalization. Store the mantissa to\r\n xmm1 under the writemask k1 and merge with the\r\n other elements of xmm2.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nConvert the double-precision floating values in the low quadword element of the second source operand (the third\r\noperand) to DP FP value with the mantissa normalization and sign control specified by the imm8 byte, see\r\nFigure 5-15. The converted result is written to the low quadword element of the destination operand (the first\r\noperand) using writemask k1. Bits (127:64) of the XMM register destination are copied from corresponding\r\nbits in the first source operand. The normalized mantissa is specified by interv (imm8[1:0]) and the sign control\r\n(sc) is specified by bits 3:2 of the immediate byte.\r\nThe conversion operation is:\r\n\r\n GetMant(x) = +-2k|x.significand|\r\nwhere:\r\n\r\n 1 <= |x.significand| < 2\r\n\r\n\r\nUnbiased exponent k depends on the interval range defined by interv and whether the exponent of the source is\r\neven or odd. The sign of the final result is determined by sc and the source sign.\r\nIf interv != 0 then k = -1, otherwise K = 0. The encoded value of imm8[1:0] and sign control are shown in\r\nFigure 5-15.\r\nThe converted DP FP result is encoded according to the sign control, the unbiased exponent k (adding bias) and a\r\nmantissa normalized to the range specified by interv.\r\nThe GetMant() function follows Table 5-9 when dealing with floating-point special numbers.\r\nThis instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1\r\nare computed and stored into zmm1. Elements in zmm1 with the corresponding bit clear in k1 retain their previous\r\nvalues.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\n// GetNormalizeMantissaDP(SRC[63:0], SignCtrl[1:0], Interv[1:0]) is defined in the operation section of VGETMANTPD\r\n\r\nSignCtrl[1:0] <- IMM8[3:2];\r\nInterv[1:0] <- IMM8[1:0];\r\n\r\nVGETMANTSD (EVEX encoded version)\r\nIF k1[0] OR *no writemask*\r\n THEN DEST[63:0] <-\r\n GetNormalizedMantissaDP(SRC2[63:0], sc, interv)\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[63:0] <- 0\r\n FI\r\nFI;\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVGETMANTSD __m128d _mm_getmant_sd( __m128d a, __m128 b, enum intv, enum sgn);\r\nVGETMANTSD __m128d _mm_mask_getmant_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, enum intv, enum sgn);\r\nVGETMANTSD __m128d _mm_maskz_getmant_sd( __mmask8 k, __m128 a, __m128d b, enum intv, enum sgn);\r\nVGETMANTSD __m128d _mm_getmant_round_sd( __m128d a, __m128 b, enum intv, enum sgn, int r);\r\nVGETMANTSD __m128d _mm_mask_getmant_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, enum intv, enum sgn, int r);\r\nVGETMANTSD __m128d _mm_maskz_getmant_round_sd( __mmask8 k, __m128d a, __m128d b, enum intv, enum sgn, int r);\r\n\r\nSIMD Floating-Point Exceptions\r\nDenormal, Invalid\r\n\r\nOther Exceptions\r\nSee Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VGETMANTSD"
},
{
"description": "VGETMANTSS-Extract Float32 Vector of Normalized Mantissa from Float32 Vector\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.LIG.66.0F3A.W0 27 /r ib T1S V/V AVX512F Extract the normalized mantissa from the low float32\r\n VGETMANTSS xmm1 {k1}{z}, xmm2, element of xmm3/m32 using imm8 for sign control and\r\n xmm3/m32{sae}, imm8 mantissa interval normalization, store the mantissa to\r\n xmm1 under the writemask k1 and merge with the\r\n other elements of xmm2.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nConvert the single-precision floating values in the low doubleword element of the second source operand (the third\r\noperand) to SP FP value with the mantissa normalization and sign control specified by the imm8 byte, see\r\nFigure 5-15. The converted result is written to the low doubleword element of the destination operand (the first\r\noperand) using writemask k1. Bits (127:32) of the XMM register destination are copied from corresponding\r\nbits in the first source operand. The normalized mantissa is specified by interv (imm8[1:0]) and the sign control\r\n(sc) is specified by bits 3:2 of the immediate byte.\r\nThe conversion operation is:\r\n\r\n GetMant(x) = +-2k|x.significand|\r\nwhere:\r\n\r\n 1 <= |x.significand| < 2\r\n\r\n\r\nUnbiased exponent k depends on the interval range defined by interv and whether the exponent of the source is\r\neven or odd. The sign of the final result is determined by sc and the source sign.\r\n\r\nif interv != 0 then k = -1, otherwise K = 0. The encoded value of imm8[1:0] and sign control are shown\r\nin Figure 5-15.\r\nThe converted SP FP result is encoded according to the sign control, the unbiased exponent k (adding bias) and a\r\nmantissa normalized to the range specified by interv.\r\nThe GetMant() function follows Table 5-9 when dealing with floating-point special numbers.\r\nThis instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1\r\nare computed and stored into zmm1. Elements in zmm1 with the corresponding bit clear in k1 retain their previous\r\nvalues.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\n// GetNormalizeMantissaSP(SRC[31:0], SignCtrl[1:0], Interv[1:0]) is defined in the operation section of VGETMANTPD\r\n\r\nSignCtrl[1:0] <- IMM8[3:2];\r\nInterv[1:0] <- IMM8[1:0];\r\n\r\nVGETMANTSS (EVEX encoded version)\r\nIF k1[0] OR *no writemask*\r\n THEN DEST[31:0] <-\r\n GetNormalizedMantissaSP(SRC2[31:0], sc, interv)\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[31:0] <- 0\r\n FI\r\nFI;\r\nDEST[127:32] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVGETMANTSS __m128 _mm_getmant_ss( __m128 a, __m128 b, enum intv, enum sgn);\r\nVGETMANTSS __m128 _mm_mask_getmant_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn);\r\nVGETMANTSS __m128 _mm_maskz_getmant_ss( __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn);\r\nVGETMANTSS __m128 _mm_getmant_round_ss( __m128 a, __m128 b, enum intv, enum sgn, int r);\r\nVGETMANTSS __m128 _mm_mask_getmant_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn, int r);\r\nVGETMANTSS __m128 _mm_maskz_getmant_round_ss( __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn, int r);\r\n\r\nSIMD Floating-Point Exceptions\r\nDenormal, Invalid\r\n\r\nOther Exceptions\r\nSee Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VGETMANTSS"
},
{
"description": "VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4-Insert Packed\r\nFloating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.NDS.256.66.0F3A.W0 18 /r ib RVMI V/V AVX Insert 128 bits of packed floating-point values from\r\n VINSERTF128 ymm1, ymm2, xmm3/m128 and the remaining values from ymm2\r\n xmm3/m128, imm8 into ymm1.\r\n EVEX.NDS.256.66.0F3A.W0 18 /r ib T4 V/V AVX512VL Insert 128 bits of packed single-precision floating-\r\n VINSERTF32X4 ymm1 {k1}{z}, ymm2, AVX512F point values from xmm3/m128 and the remaining\r\n xmm3/m128, imm8 values from ymm2 into ymm1 under writemask k1.\r\n EVEX.NDS.512.66.0F3A.W0 18 /r ib T4 V/V AVX512F Insert 128 bits of packed single-precision floating-\r\n VINSERTF32X4 zmm1 {k1}{z}, zmm2, point values from xmm3/m128 and the remaining\r\n xmm3/m128, imm8 values from zmm2 into zmm1 under writemask k1.\r\n EVEX.NDS.256.66.0F3A.W1 18 /r ib T2 V/V AVX512VL Insert 128 bits of packed double-precision floating-\r\n VINSERTF64X2 ymm1 {k1}{z}, ymm2, AVX512DQ point values from xmm3/m128 and the remaining\r\n xmm3/m128, imm8 values from ymm2 into ymm1 under writemask k1.\r\n EVEX.NDS.512.66.0F3A.W1 18 /r ib T2 V/V AVX512DQ Insert 128 bits of packed double-precision floating-\r\n VINSERTF64X2 zmm1 {k1}{z}, zmm2, point values from xmm3/m128 and the remaining\r\n xmm3/m128, imm8 values from zmm2 into zmm1 under writemask k1.\r\n EVEX.NDS.512.66.0F3A.W0 1A /r ib T8 V/V AVX512DQ Insert 256 bits of packed single-precision floating-\r\n VINSERTF32X8 zmm1 {k1}{z}, zmm2, point values from ymm3/m256 and the remaining\r\n ymm3/m256, imm8 values from zmm2 into zmm1 under writemask k1.\r\n EVEX.NDS.512.66.0F3A.W1 1A /r ib T4 V/V AVX512F Insert 256 bits of packed double-precision floating-\r\n VINSERTF64X4 zmm1 {k1}{z}, zmm2, point values from ymm3/m256 and the remaining\r\n ymm3/m256, imm8 values from zmm2 into zmm1 under writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVMI ModRM:reg (w) VEX.vvvv ModRM:r/m (r) Imm8\r\n T2, T4, T8 ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) Imm8\r\n\r\nDescription\r\nVINSERTF128/VINSERTF32x4 and VINSERTF64x2 insert 128-bits of packed floating-point values from the second\r\nsource operand (the third operand) into the destination operand (the first operand) at an 128-bit granularity offset\r\nmultiplied by imm8[0] (256-bit) or imm8[1:0]. The remaining portions of the destination operand are copied from\r\nthe corresponding fields of the first source operand (the second operand). The second source operand can be either\r\nan XMM register or a 128-bit memory location. The destination and first source operands are vector registers.\r\nVINSERTF32x4: The destination operand is a ZMM/YMM register and updated at 32-bit granularity according to the\r\nwritemask. The high 6/7 bits of the immediate are ignored.\r\nVINSERTF64x2: The destination operand is a ZMM/YMM register and updated at 64-bit granularity according to the\r\nwritemask. The high 6/7 bits of the immediate are ignored.\r\nVINSERTF32x8 and VINSERTF64x4 inserts 256-bits of packed floating-point values from the second source operand\r\n(the third operand) into the destination operand (the first operand) at a 256-bit granular offset multiplied by\r\nimm8[0]. The remaining portions of the destination are copied from the corresponding fields of the first source\r\noperand (the second operand). The second source operand can be either an YMM register or a 256-bit memory\r\nlocation. The high 7 bits of the immediate are ignored. The destination operand is a ZMM register and updated at\r\n32/64-bit granularity according to the writemask.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVINSERTF32x4 (EVEX encoded versions)\r\n(KL, VL) = (8, 256), (16, 512)\r\nTEMP_DEST[VL-1:0] <- SRC1[VL-1:0]\r\nIF VL = 256\r\n CASE (imm8[0]) OF\r\n 0: TMP_DEST[127:0] <- SRC2[127:0]\r\n 1: TMP_DEST[255:128] <- SRC2[127:0]\r\n ESAC.\r\nFI;\r\nIF VL = 512\r\n CASE (imm8[1:0]) OF\r\n 00: TMP_DEST[127:0] <- SRC2[127:0]\r\n 01: TMP_DEST[255:128] <- SRC2[127:0]\r\n 10: TMP_DEST[383:256] <- SRC2[127:0]\r\n 11: TMP_DEST[511:384] <- SRC2[127:0]\r\n ESAC.\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_DEST[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVINSERTF64x2 (EVEX encoded versions)\r\n(KL, VL) = (4, 256), (8, 512)\r\nTEMP_DEST[VL-1:0] <- SRC1[VL-1:0]\r\nIF VL = 256\r\n CASE (imm8[0]) OF\r\n 0: TMP_DEST[127:0] <- SRC2[127:0]\r\n 1: TMP_DEST[255:128] <- SRC2[127:0]\r\n ESAC.\r\nFI;\r\nIF VL = 512\r\n CASE (imm8[1:0]) OF\r\n 00: TMP_DEST[127:0] <- SRC2[127:0]\r\n 01: TMP_DEST[255:128] <- SRC2[127:0]\r\n 10: TMP_DEST[383:256] <- SRC2[127:0]\r\n 11: TMP_DEST[511:384] <- SRC2[127:0]\r\n ESAC.\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE\r\n\r\n\r\n\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVINSERTF32x8 (EVEX.U1.512 encoded version)\r\nTEMP_DEST[VL-1:0] <- SRC1[VL-1:0]\r\nCASE (imm8[0]) OF\r\n 0: TMP_DEST[255:0] <- SRC2[255:0]\r\n 1: TMP_DEST[511:256] <- SRC2[255:0]\r\nESAC.\r\n\r\nFOR j <- 0 TO 15\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_DEST[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVINSERTF64x4 (EVEX.512 encoded version)\r\nVL = 512\r\nTEMP_DEST[VL-1:0] <- SRC1[VL-1:0]\r\nCASE (imm8[0]) OF\r\n 0: TMP_DEST[255:0] <- SRC2[255:0]\r\n 1: TMP_DEST[511:256] <- SRC2[255:0]\r\nESAC.\r\n\r\nFOR j <- 0 TO 7\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVINSERTF128 (VEX encoded version)\r\nTEMP[255:0] <-SRC1[255:0]\r\nCASE (imm8[0]) OF\r\n 0: TEMP[127:0] <-SRC2[127:0]\r\n 1: TEMP[255:128] <-SRC2[127:0]\r\nESAC\r\nDEST <-TEMP\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVINSERTF32x4 __m512 _mm512_insertf32x4( __m512 a, __m128 b, int imm);\r\nVINSERTF32x4 __m512 _mm512_mask_insertf32x4(__m512 s, __mmask16 k, __m512 a, __m128 b, int imm);\r\nVINSERTF32x4 __m512 _mm512_maskz_insertf32x4( __mmask16 k, __m512 a, __m128 b, int imm);\r\nVINSERTF32x4 __m256 _mm256_insertf32x4( __m256 a, __m128 b, int imm);\r\nVINSERTF32x4 __m256 _mm256_mask_insertf32x4(__m256 s, __mmask8 k, __m256 a, __m128 b, int imm);\r\nVINSERTF32x4 __m256 _mm256_maskz_insertf32x4( __mmask8 k, __m256 a, __m128 b, int imm);\r\nVINSERTF32x8 __m512 _mm512_insertf32x8( __m512 a, __m256 b, int imm);\r\nVINSERTF32x8 __m512 _mm512_mask_insertf32x8(__m512 s, __mmask16 k, __m512 a, __m256 b, int imm);\r\nVINSERTF32x8 __m512 _mm512_maskz_insertf32x8( __mmask16 k, __m512 a, __m256 b, int imm);\r\nVINSERTF64x2 __m512d _mm512_insertf64x2( __m512d a, __m128d b, int imm);\r\nVINSERTF64x2 __m512d _mm512_mask_insertf64x2(__m512d s, __mmask8 k, __m512d a, __m128d b, int imm);\r\nVINSERTF64x2 __m512d _mm512_maskz_insertf64x2( __mmask8 k, __m512d a, __m128d b, int imm);\r\nVINSERTF64x2 __m256d _mm256_insertf64x2( __m256d a, __m128d b, int imm);\r\nVINSERTF64x2 __m256d _mm256_mask_insertf64x2(__m256d s, __mmask8 k, __m256d a, __m128d b, int imm);\r\nVINSERTF64x2 __m256d _mm256_maskz_insertf64x2( __mmask8 k, __m256d a, __m128d b, int imm);\r\nVINSERTF64x4 __m512d _mm512_insertf64x4( __m512d a, __m256d b, int imm);\r\nVINSERTF64x4 __m512d _mm512_mask_insertf64x4(__m512d s, __mmask8 k, __m512d a, __m256d b, int imm);\r\nVINSERTF64x4 __m512d _mm512_maskz_insertf64x4( __mmask8 k, __m512d a, __m256d b, int imm);\r\nVINSERTF128 __m256 _mm256_insertf128_ps (__m256 a, __m128 b, int offset);\r\nVINSERTF128 __m256d _mm256_insertf128_pd (__m256d a, __m128d b, int offset);\r\nVINSERTF128 __m256i _mm256_insertf128_si256 (__m256i a, __m128i b, int offset);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nVEX-encoded instruction, see Exceptions Type 6; additionally\r\n#UD If VEX.L = 0.\r\nEVEX-encoded instruction, see Exceptions Type E6NF.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VINSERTF128"
},
{
"description": "-R:VINSERTF128",
"mnem": "VINSERTF32x4"
},
{
"description": "-R:VINSERTF128",
"mnem": "VINSERTF32x8"
},
{
"description": "-R:VINSERTF128",
"mnem": "VINSERTF64x2"
},
{
"description": "-R:VINSERTF128",
"mnem": "VINSERTF64x4"
},
{
"description": "VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4-Insert Packed\r\nInteger Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.NDS.256.66.0F3A.W0 38 /r ib RVMI V/V AVX2 Insert 128 bits of integer data from xmm3/m128 and\r\n VINSERTI128 ymm1, ymm2, the remaining values from ymm2 into ymm1.\r\n xmm3/m128, imm8\r\n EVEX.NDS.256.66.0F3A.W0 38 /r ib T4 V/V AVX512VL Insert 128 bits of packed doubleword integer values\r\n VINSERTI32X4 ymm1 {k1}{z}, ymm2, AVX512F from xmm3/m128 and the remaining values from\r\n xmm3/m128, imm8 ymm2 into ymm1 under writemask k1.\r\n EVEX.NDS.512.66.0F3A.W0 38 /r ib T4 V/V AVX512F Insert 128 bits of packed doubleword integer values\r\n VINSERTI32X4 zmm1 {k1}{z}, zmm2, from xmm3/m128 and the remaining values from\r\n xmm3/m128, imm8 zmm2 into zmm1 under writemask k1.\r\n EVEX.NDS.256.66.0F3A.W1 38 /r ib T2 V/V AVX512VL Insert 128 bits of packed quadword integer values\r\n VINSERTI64X2 ymm1 {k1}{z}, ymm2, AVX512DQ from xmm3/m128 and the remaining values from\r\n xmm3/m128, imm8 ymm2 into ymm1 under writemask k1.\r\n EVEX.NDS.512.66.0F3A.W1 38 /r ib T2 V/V AVX512DQ Insert 128 bits of packed quadword integer values\r\n VINSERTI64X2 zmm1 {k1}{z}, zmm2, from xmm3/m128 and the remaining values from\r\n xmm3/m128, imm8 zmm2 into zmm1 under writemask k1.\r\n EVEX.NDS.512.66.0F3A.W0 3A /r ib T8 V/V AVX512DQ Insert 256 bits of packed doubleword integer values\r\n VINSERTI32X8 zmm1 {k1}{z}, zmm2, from ymm3/m256 and the remaining values from\r\n ymm3/m256, imm8 zmm2 into zmm1 under writemask k1.\r\n EVEX.NDS.512.66.0F3A.W1 3A /r ib T4 V/V AVX512F Insert 256 bits of packed quadword integer values\r\n VINSERTI64X4 zmm1 {k1}{z}, zmm2, from ymm3/m256 and the remaining values from\r\n ymm3/m256, imm8 zmm2 into zmm1 under writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVMI ModRM:reg (w) VEX.vvvv ModRM:r/m (r) Imm8\r\n T2, T4, T8 ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) Imm8\r\n\r\nDescription\r\nVINSERTI32x4 and VINSERTI64x2 inserts 128-bits of packed integer values from the second source operand (the\r\nthird operand) into the destination operand (the first operand) at an 128-bit granular offset multiplied by imm8[0]\r\n(256-bit) or imm8[1:0]. The remaining portions of the destination are copied from the corresponding fields of the\r\nfirst source operand (the second operand). The second source operand can be either an XMM register or a 128-bit\r\nmemory location. The high 6/7bits of the immediate are ignored. The destination operand is a ZMM/YMM register\r\nand updated at 32 and 64-bit granularity according to the writemask.\r\nVINSERTI32x8 and VINSERTI64x4 inserts 256-bits of packed integer values from the second source operand (the\r\nthird operand) into the destination operand (the first operand) at a 256-bit granular offset multiplied by imm8[0].\r\nThe remaining portions of the destination are copied from the corresponding fields of the first source operand (the\r\nsecond operand). The second source operand can be either an YMM register or a 256-bit memory location. The\r\nupper bits of the immediate are ignored. The destination operand is a ZMM register and updated at 32 and 64-bit\r\ngranularity according to the writemask.\r\nVINSERTI128 inserts 128-bits of packed integer data from the second source operand (the third operand) into the\r\ndestination operand (the first operand) at a 128-bit granular offset multiplied by imm8[0]. The remaining portions\r\nof the destination are copied from the corresponding fields of the first source operand (the second operand). The\r\nsecond source operand can be either an XMM register or a 128-bit memory location. The high 7 bits of the imme-\r\ndiate are ignored. VEX.L must be 1, otherwise attempt to execute this instruction with VEX.L=0 will cause #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVINSERTI32x4 (EVEX encoded versions)\r\n(KL, VL) = (8, 256), (16, 512)\r\nTEMP_DEST[VL-1:0] <- SRC1[VL-1:0]\r\nIF VL = 256\r\n CASE (imm8[0]) OF\r\n 0: TMP_DEST[127:0] <- SRC2[127:0]\r\n 1: TMP_DEST[255:128] <- SRC2[127:0]\r\n ESAC.\r\nFI;\r\nIF VL = 512\r\n CASE (imm8[1:0]) OF\r\n 00: TMP_DEST[127:0] <- SRC2[127:0]\r\n 01: TMP_DEST[255:128] <- SRC2[127:0]\r\n 10: TMP_DEST[383:256] <- SRC2[127:0]\r\n 11: TMP_DEST[511:384] <- SRC2[127:0]\r\n ESAC.\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_DEST[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVINSERTI64x2 (EVEX encoded versions)\r\n(KL, VL) = (4, 256), (8, 512)\r\nTEMP_DEST[VL-1:0] <- SRC1[VL-1:0]\r\nIF VL = 256\r\n CASE (imm8[0]) OF\r\n 0: TMP_DEST[127:0] <- SRC2[127:0]\r\n 1: TMP_DEST[255:128] <- SRC2[127:0]\r\n ESAC.\r\nFI;\r\nIF VL = 512\r\n CASE (imm8[1:0]) OF\r\n 00: TMP_DEST[127:0] <- SRC2[127:0]\r\n 01: TMP_DEST[255:128] <- SRC2[127:0]\r\n 10: TMP_DEST[383:256] <- SRC2[127:0]\r\n 11: TMP_DEST[511:384] <- SRC2[127:0]\r\n ESAC.\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE\r\n\r\n\r\n\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVINSERTI32x8 (EVEX.U1.512 encoded version)\r\nTEMP_DEST[VL-1:0] <- SRC1[VL-1:0]\r\nCASE (imm8[0]) OF\r\n 0: TMP_DEST[255:0] <- SRC2[255:0]\r\n 1: TMP_DEST[511:256] <- SRC2[255:0]\r\nESAC.\r\n\r\nFOR j <- 0 TO 15\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_DEST[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVINSERTI64x4 (EVEX.512 encoded version)\r\nVL = 512\r\nTEMP_DEST[VL-1:0] <- SRC1[VL-1:0]\r\nCASE (imm8[0]) OF\r\n 0: TMP_DEST[255:0] <- SRC2[255:0]\r\n 1: TMP_DEST[511:256] <- SRC2[255:0]\r\nESAC.\r\n\r\nFOR j <- 0 TO 7\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVINSERTI128\r\nTEMP[255:0] <-SRC1[255:0]\r\nCASE (imm8[0]) OF\r\n 0: TEMP[127:0] <-SRC2[127:0]\r\n 1: TEMP[255:128] <-SRC2[127:0]\r\nESAC\r\nDEST <-TEMP\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVINSERTI32x4 _mm512i _inserti32x4( __m512i a, __m128i b, int imm);\r\nVINSERTI32x4 _mm512i _mask_inserti32x4(__m512i s, __mmask16 k, __m512i a, __m128i b, int imm);\r\nVINSERTI32x4 _mm512i _maskz_inserti32x4( __mmask16 k, __m512i a, __m128i b, int imm);\r\nVINSERTI32x4 __m256i _mm256_inserti32x4( __m256i a, __m128i b, int imm);\r\nVINSERTI32x4 __m256i _mm256_mask_inserti32x4(__m256i s, __mmask8 k, __m256i a, __m128i b, int imm);\r\nVINSERTI32x4 __m256i _mm256_maskz_inserti32x4( __mmask8 k, __m256i a, __m128i b, int imm);\r\nVINSERTI32x8 __m512i _mm512_inserti32x8( __m512i a, __m256i b, int imm);\r\nVINSERTI32x8 __m512i _mm512_mask_inserti32x8(__m512i s, __mmask16 k, __m512i a, __m256i b, int imm);\r\nVINSERTI32x8 __m512i _mm512_maskz_inserti32x8( __mmask16 k, __m512i a, __m256i b, int imm);\r\nVINSERTI64x2 __m512i _mm512_inserti64x2( __m512i a, __m128i b, int imm);\r\nVINSERTI64x2 __m512i _mm512_mask_inserti64x2(__m512i s, __mmask8 k, __m512i a, __m128i b, int imm);\r\nVINSERTI64x2 __m512i _mm512_maskz_inserti64x2( __mmask8 k, __m512i a, __m128i b, int imm);\r\nVINSERTI64x2 __m256i _mm256_inserti64x2( __m256i a, __m128i b, int imm);\r\nVINSERTI64x2 __m256i _mm256_mask_inserti64x2(__m256i s, __mmask8 k, __m256i a, __m128i b, int imm);\r\nVINSERTI64x2 __m256i _mm256_maskz_inserti64x2( __mmask8 k, __m256i a, __m128i b, int imm);\r\nVINSERTI64x4 _mm512_inserti64x4( __m512i a, __m256i b, int imm);\r\nVINSERTI64x4 _mm512_mask_inserti64x4(__m512i s, __mmask8 k, __m512i a, __m256i b, int imm);\r\nVINSERTI64x4 _mm512_maskz_inserti64x4( __mmask m, __m512i a, __m256i b, int imm);\r\nVINSERTI128 __m256i _mm256_insertf128_si256 (__m256i a, __m128i b, int offset);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nVEX-encoded instruction, see Exceptions Type 6; additionally\r\n#UD If VEX.L = 0.\r\nEVEX-encoded instruction, see Exceptions Type E6NF.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VINSERTI128"
},
{
"description": "-R:VINSERTI128",
"mnem": "VINSERTI32x4"
},
{
"description": "-R:VINSERTI128",
"mnem": "VINSERTI32x8"
},
{
"description": "-R:VINSERTI128",
"mnem": "VINSERTI64x2"
},
{
"description": "-R:VINSERTI128",
"mnem": "VINSERTI64x4"
},
{
"description": "VMASKMOV-Conditional SIMD Packed Loads and Stores\r\nOpcode/ Op/ 64/32-bit CPUID Description\r\nInstruction En Mode Feature\r\n Flag\r\nVEX.NDS.128.66.0F38.W0 2C /r RVM V/V AVX Conditionally load packed single-precision values from\r\nVMASKMOVPS xmm1, xmm2, m128 m128 using mask in xmm2 and store in xmm1.\r\nVEX.NDS.256.66.0F38.W0 2C /r RVM V/V AVX Conditionally load packed single-precision values from\r\nVMASKMOVPS ymm1, ymm2, m256 m256 using mask in ymm2 and store in ymm1.\r\n\r\nVEX.NDS.128.66.0F38.W0 2D /r RVM V/V AVX Conditionally load packed double-precision values from\r\nVMASKMOVPD xmm1, xmm2, m128 m128 using mask in xmm2 and store in xmm1.\r\n\r\nVEX.NDS.256.66.0F38.W0 2D /r RVM V/V AVX Conditionally load packed double-precision values from\r\nVMASKMOVPD ymm1, ymm2, m256 m256 using mask in ymm2 and store in ymm1.\r\n\r\nVEX.NDS.128.66.0F38.W0 2E /r MVR V/V AVX Conditionally store packed single-precision values from\r\nVMASKMOVPS m128, xmm1, xmm2 xmm2 using mask in xmm1.\r\n\r\nVEX.NDS.256.66.0F38.W0 2E /r MVR V/V AVX Conditionally store packed single-precision values from\r\nVMASKMOVPS m256, ymm1, ymm2 ymm2 using mask in ymm1.\r\nVEX.NDS.128.66.0F38.W0 2F /r MVR V/V AVX Conditionally store packed double-precision values from\r\nVMASKMOVPD m128, xmm1, xmm2 xmm2 using mask in xmm1.\r\n\r\nVEX.NDS.256.66.0F38.W0 2F /r MVR V/V AVX Conditionally store packed double-precision values from\r\nVMASKMOVPD m256, ymm1, ymm2 ymm2 using mask in ymm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n MVR ModRM:r/m (w) VEX.vvvv (r) ModRM:reg (r) NA\r\n\r\n\r\nDescription\r\nConditionally moves packed data elements from the second source operand into the corresponding data element of\r\nthe destination operand, depending on the mask bits associated with each data element. The mask bits are speci-\r\nfied in the first source operand.\r\nThe mask bit for each data element is the most significant bit of that element in the first source operand. If a mask\r\nis 1, the corresponding data element is copied from the second source operand to the destination operand. If the\r\nmask is 0, the corresponding data element is set to zero in the load form of these instructions, and unmodified in\r\nthe store form.\r\nThe second source operand is a memory address for the load form of these instruction. The destination operand is\r\na memory address for the store form of these instructions. The other operands are both XMM registers (for\r\nVEX.128 version) or YMM registers (for VEX.256 version).\r\nFaults occur only due to mask-bit required memory accesses that caused the faults. Faults will not occur due to\r\nreferencing any memory location if the corresponding mask bit for that memory location is 0. For example, no\r\nfaults will be detected if the mask bits are all zero.\r\nUnlike previous MASKMOV instructions (MASKMOVQ and MASKMOVDQU), a nontemporal hint is not applied to\r\nthese instructions.\r\nInstruction behavior on alignment check reporting with mask bits of less than all 1s are the same as with mask bits\r\nof all 1s.\r\nVMASKMOV should not be used to access memory mapped I/O and un-cached memory as the access and the\r\nordering of the individual loads or stores it does is implementation specific.\r\n\r\n\r\n\r\n\r\n\r\nIn cases where mask bits indicate data should not be loaded or stored paging A and D bits will be set in an imple-\r\nmentation dependent way. However, A and D bits are always set for pages where data is actually loaded/stored.\r\nNote: for load forms, the first source (the mask) is encoded in VEX.vvvv; the second source is encoded in rm_field,\r\nand the destination register is encoded in reg_field.\r\nNote: for store forms, the first source (the mask) is encoded in VEX.vvvv; the second source register is encoded in\r\nreg_field, and the destination memory location is encoded in rm_field.\r\n\r\nOperation\r\nVMASKMOVPS -128-bit load\r\nDEST[31:0] <- IF (SRC1[31]) Load_32(mem) ELSE 0\r\nDEST[63:32] <- IF (SRC1[63]) Load_32(mem + 4) ELSE 0\r\nDEST[95:64] <- IF (SRC1[95]) Load_32(mem + 8) ELSE 0\r\nDEST[127:97] <- IF (SRC1[127]) Load_32(mem + 12) ELSE 0\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVMASKMOVPS - 256-bit load\r\nDEST[31:0] <- IF (SRC1[31]) Load_32(mem) ELSE 0\r\nDEST[63:32] <- IF (SRC1[63]) Load_32(mem + 4) ELSE 0\r\nDEST[95:64] <- IF (SRC1[95]) Load_32(mem + 8) ELSE 0\r\nDEST[127:96] <- IF (SRC1[127]) Load_32(mem + 12) ELSE 0\r\nDEST[159:128] <- IF (SRC1[159]) Load_32(mem + 16) ELSE 0\r\nDEST[191:160] <- IF (SRC1[191]) Load_32(mem + 20) ELSE 0\r\nDEST[223:192] <- IF (SRC1[223]) Load_32(mem + 24) ELSE 0\r\nDEST[255:224] <- IF (SRC1[255]) Load_32(mem + 28) ELSE 0\r\n\r\nVMASKMOVPD - 128-bit load\r\nDEST[63:0] <- IF (SRC1[63]) Load_64(mem) ELSE 0\r\nDEST[127:64] <- IF (SRC1[127]) Load_64(mem + 16) ELSE 0\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVMASKMOVPD - 256-bit load\r\nDEST[63:0] <- IF (SRC1[63]) Load_64(mem) ELSE 0\r\nDEST[127:64] <- IF (SRC1[127]) Load_64(mem + 8) ELSE 0\r\nDEST[195:128] <- IF (SRC1[191]) Load_64(mem + 16) ELSE 0\r\nDEST[255:196] <- IF (SRC1[255]) Load_64(mem + 24) ELSE 0\r\n\r\nVMASKMOVPS - 128-bit store\r\nIF (SRC1[31]) DEST[31:0] <- SRC2[31:0]\r\nIF (SRC1[63]) DEST[63:32] <- SRC2[63:32]\r\nIF (SRC1[95]) DEST[95:64] <- SRC2[95:64]\r\nIF (SRC1[127]) DEST[127:96] <- SRC2[127:96]\r\n\r\nVMASKMOVPS - 256-bit store\r\nIF (SRC1[31]) DEST[31:0] <- SRC2[31:0]\r\nIF (SRC1[63]) DEST[63:32] <- SRC2[63:32]\r\nIF (SRC1[95]) DEST[95:64] <- SRC2[95:64]\r\nIF (SRC1[127]) DEST[127:96] <- SRC2[127:96]\r\nIF (SRC1[159]) DEST[159:128] <-SRC2[159:128]\r\nIF (SRC1[191]) DEST[191:160] <- SRC2[191:160]\r\nIF (SRC1[223]) DEST[223:192] <- SRC2[223:192]\r\nIF (SRC1[255]) DEST[255:224] <- SRC2[255:224]\r\n\r\n\r\n\r\n\r\n\r\nVMASKMOVPD - 128-bit store\r\nIF (SRC1[63]) DEST[63:0] <- SRC2[63:0]\r\nIF (SRC1[127]) DEST[127:64] <-SRC2[127:64]\r\n\r\nVMASKMOVPD - 256-bit store\r\nIF (SRC1[63]) DEST[63:0] <- SRC2[63:0]\r\nIF (SRC1[127]) DEST[127:64] <-SRC2[127:64]\r\nIF (SRC1[191]) DEST[191:128] <- SRC2[191:128]\r\nIF (SRC1[255]) DEST[255:192] <- SRC2[255:192]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n__m256 _mm256_maskload_ps(float const *a, __m256i mask)\r\nvoid _mm256_maskstore_ps(float *a, __m256i mask, __m256 b)\r\n__m256d _mm256_maskload_pd(double *a, __m256i mask);\r\nvoid _mm256_maskstore_pd(double *a, __m256i mask, __m256d b);\r\n__m128 _mm128_maskload_ps(float const *a, __m128i mask)\r\nvoid _mm128_maskstore_ps(float *a, __m128i mask, __m128 b)\r\n__m128d _mm128_maskload_pd(double *a, __m128i mask);\r\nvoid _mm128_maskstore_pd(double *a, __m128i mask, __m128d b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 6 (No AC# reported for any mask bit combinations);\r\nadditionally\r\n#UD If VEX.W = 1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VMASKMOV"
},
{
"description": "-R:MOVDQA",
"mnem": "VMOVDQA"
},
{
"description": "-R:MOVDQA",
"mnem": "VMOVDQA32"
},
{
"description": "-R:MOVDQA",
"mnem": "VMOVDQA64"
},
{
"description": "-R:MOVDQU",
"mnem": "VMOVDQU"
},
{
"description": "-R:MOVDQU",
"mnem": "VMOVDQU16"
},
{
"description": "-R:MOVDQU",
"mnem": "VMOVDQU32"
},
{
"description": "-R:MOVDQU",
"mnem": "VMOVDQU64"
},
{
"description": "-R:MOVDQU",
"mnem": "VMOVDQU8"
},
{
"description": "VPBLENDD - Blend Packed Dwords\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En -bit Feature\r\n Mode Flag\r\n VEX.NDS.128.66.0F3A.W0 02 /r ib RVMI V/V AVX2 Select dwords from xmm2 and xmm3/m128 from\r\n VPBLENDD xmm1, xmm2, xmm3/m128, imm8 mask specified in imm8 and store the values into\r\n xmm1.\r\n VEX.NDS.256.66.0F3A.W0 02 /r ib RVMI V/V AVX2 Select dwords from ymm2 and ymm3/m256 from\r\n VPBLENDD ymm1, ymm2, ymm3/m256, imm8 mask specified in imm8 and store the values into\r\n ymm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVMI ModRM:reg (w) VEX.vvvv ModRM:r/m (r) Imm8\r\n\r\nDescription\r\nDword elements from the source operand (second operand) are conditionally written to the destination operand\r\n(first operand) depending on bits in the immediate operand (third operand). The immediate bits (bits 7:0) form a\r\nmask that determines whether the corresponding word in the destination is copied from the source. If a bit in the\r\nmask, corresponding to a word, is \"1\", then the word is copied, else the word is unchanged.\r\nVEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The\r\nfirst source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM register\r\nare zeroed.\r\nVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register\r\nor a 256-bit memory location. The destination operand is a YMM register.\r\n\r\nOperation\r\nVPBLENDD (VEX.256 encoded version)\r\nIF (imm8[0] == 1) THEN DEST[31:0] <- SRC2[31:0]\r\nELSE DEST[31:0] <- SRC1[31:0]\r\nIF (imm8[1] == 1) THEN DEST[63:32] <- SRC2[63:32]\r\nELSE DEST[63:32] <- SRC1[63:32]\r\nIF (imm8[2] == 1) THEN DEST[95:64] <- SRC2[95:64]\r\nELSE DEST[95:64] <- SRC1[95:64]\r\nIF (imm8[3] == 1) THEN DEST[127:96] <- SRC2[127:96]\r\nELSE DEST[127:96] <- SRC1[127:96]\r\nIF (imm8[4] == 1) THEN DEST[159:128] <- SRC2[159:128]\r\nELSE DEST[159:128] <- SRC1[159:128]\r\nIF (imm8[5] == 1) THEN DEST[191:160] <- SRC2[191:160]\r\nELSE DEST[191:160] <- SRC1[191:160]\r\nIF (imm8[6] == 1) THEN DEST[223:192] <- SRC2[223:192]\r\nELSE DEST[223:192] <- SRC1[223:192]\r\nIF (imm8[7] == 1) THEN DEST[255:224] <- SRC2[255:224]\r\nELSE DEST[255:224] <- SRC1[255:224]\r\n\r\n\r\n\r\n\r\n\r\nVPBLENDD (VEX.128 encoded version)\r\nIF (imm8[0] == 1) THEN DEST[31:0] <- SRC2[31:0]\r\nELSE DEST[31:0] <- SRC1[31:0]\r\nIF (imm8[1] == 1) THEN DEST[63:32] <- SRC2[63:32]\r\nELSE DEST[63:32] <- SRC1[63:32]\r\nIF (imm8[2] == 1) THEN DEST[95:64] <- SRC2[95:64]\r\nELSE DEST[95:64] <- SRC1[95:64]\r\nIF (imm8[3] == 1) THEN DEST[127:96] <- SRC2[127:96]\r\nELSE DEST[127:96] <- SRC1[127:96]\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPBLENDD: __m128i _mm_blend_epi32 (__m128i v1, __m128i v2, const int mask)\r\nVPBLENDD: __m256i _mm256_blend_epi32 (__m256i v1, __m256i v2, const int mask)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4; additionally\r\n#UD If VEX.W = 1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPBLENDD"
},
{
"description": "VPBLENDMB/VPBLENDMW-Blend Byte/Word Vectors Using an Opmask Control\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.128.66.0F38.W0 66 /r FVM V/V AVX512VL Blend byte integer vector xmm2 and byte vector\r\n VPBLENDMB xmm1 {k1}{z}, AVX512BW xmm3/m128 and store the result in xmm1, under control\r\n xmm2, xmm3/m128 mask.\r\n EVEX.NDS.256.66.0F38.W0 66 /r FVM V/V AVX512VL Blend byte integer vector ymm2 and byte vector\r\n VPBLENDMB ymm1 {k1}{z}, AVX512BW ymm3/m256 and store the result in ymm1, under control\r\n ymm2, ymm3/m256 mask.\r\n EVEX.NDS.512.66.0F38.W0 66 /r FVM V/V AVX512BW Blend byte integer vector zmm2 and byte vector\r\n VPBLENDMB zmm1 {k1}{z}, zmm3/m512 and store the result in zmm1, under control\r\n zmm2, zmm3/m512 mask.\r\n EVEX.NDS.128.66.0F38.W1 66 /r FVM V/V AVX512VL Blend word integer vector xmm2 and word vector\r\n VPBLENDMW xmm1 {k1}{z}, AVX512BW xmm3/m128 and store the result in xmm1, under control\r\n xmm2, xmm3/m128 mask.\r\n EVEX.NDS.256.66.0F38.W1 66 /r FVM V/V AVX512VL Blend word integer vector ymm2 and word vector\r\n VPBLENDMW ymm1 {k1}{z}, AVX512BW ymm3/m256 and store the result in ymm1, under control\r\n ymm2, ymm3/m256 mask.\r\n EVEX.NDS.512.66.0F38.W1 66 /r FVM V/V AVX512BW Blend word integer vector zmm2 and word vector\r\n VPBLENDMW zmm1 {k1}{z}, zmm3/m512 and store the result in zmm1, under control\r\n zmm2, zmm3/m512 mask.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FVM ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms an element-by-element blending of byte/word elements between the first source operand byte vector\r\nregister and the second source operand byte vector from memory or register, using the instruction mask as\r\nselector. The result is written into the destination byte vector register.\r\nThe destination and first source operands are ZMM/YMM/XMM registers. The second source operand can be a\r\nZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit memory location.\r\nThe mask is not used as a writemask for this instruction. Instead, the mask is used as an element selector: every\r\nelement of the destination is conditionally selected between first source or second source using the value of the\r\nrelated mask bit (0 for first source, 1 for second source).\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVPBLENDMB (EVEX encoded versions)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i<-j*8\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- SRC2[i+7:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN DEST[i+7:i] <- SRC1[i+7:i]\r\n ELSE ; zeroing-masking\r\n DEST[i+7:i] <- 0\r\n FI;\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0;\r\n\r\nVPBLENDMW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- SRC2[i+15:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN DEST[i+15:i] <- SRC1[i+15:i]\r\n ELSE ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI;\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPBLENDMB __m512i _mm512_mask_blend_epi8(__mmask64 m, __m512i a, __m512i b);\r\nVPBLENDMB __m256i _mm256_mask_blend_epi8(__mmask32 m, __m256i a, __m256i b);\r\nVPBLENDMB __m128i _mm_mask_blend_epi8(__mmask16 m, __m128i a, __m128i b);\r\nVPBLENDMW __m512i _mm512_mask_blend_epi16(__mmask32 m, __m512i a, __m512i b);\r\nVPBLENDMW __m256i _mm256_mask_blend_epi16(__mmask16 m, __m256i a, __m256i b);\r\nVPBLENDMW __m128i _mm_mask_blend_epi16(__mmask8 m, __m128i a, __m128i b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPBLENDMB"
},
{
"description": "VPBLENDMD/VPBLENDMQ-Blend Int32/Int64 Vectors Using an OpMask Control\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.128.66.0F38.W0 64 /r FV V/V AVX512VL Blend doubleword integer vector xmm2 and doubleword\r\n VPBLENDMD xmm1 {k1}{z}, AVX512F vector xmm3/m128/m32bcst and store the result in\r\n xmm2, xmm3/m128/m32bcst xmm1, under control mask.\r\n EVEX.NDS.256.66.0F38.W0 64 /r FV V/V AVX512VL Blend doubleword integer vector ymm2 and doubleword\r\n VPBLENDMD ymm1 {k1}{z}, ymm2, AVX512F vector ymm3/m256/m32bcst and store the result in\r\n ymm3/m256/m32bcst ymm1, under control mask.\r\n EVEX.NDS.512.66.0F38.W0 64 /r FV V/V AVX512F Blend doubleword integer vector zmm2 and doubleword\r\n VPBLENDMD zmm1 {k1}{z}, zmm2, vector zmm3/m512/m32bcst and store the result in\r\n zmm3/m512/m32bcst zmm1, under control mask.\r\n EVEX.NDS.128.66.0F38.W1 64 /r FV V/V AVX512VL Blend quadword integer vector xmm2 and quadword\r\n VPBLENDMQ xmm1 {k1}{z}, AVX512F vector xmm3/m128/m64bcst and store the result in\r\n xmm2, xmm3/m128/m64bcst xmm1, under control mask.\r\n EVEX.NDS.256.66.0F38.W1 64 /r FV V/V AVX512VL Blend quadword integer vector ymm2 and quadword\r\n VPBLENDMQ ymm1 {k1}{z}, AVX512F vector ymm3/m256/m64bcst and store the result in\r\n ymm2, ymm3/m256/m64bcst ymm1, under control mask.\r\n EVEX.NDS.512.66.0F38.W1 64 /r FV V/V AVX512F Blend quadword integer vector zmm2 and quadword\r\n VPBLENDMQ zmm1 {k1}{z}, zmm2, vector zmm3/m512/m64bcst and store the result in\r\n zmm3/m512/m64bcst zmm1, under control mask.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms an element-by-element blending of dword/qword elements between the first source operand (the second\r\noperand) and the elements of the second source operand (the third operand) using an opmask register as select\r\ncontrol. The blended result is written into the destination.\r\nThe destination and first source operands are ZMM registers. The second source operand can be a ZMM register, a\r\n512-bit memory location or a 512-bit vector broadcasted from a 32-bit memory location.\r\nThe opmask register is not used as a writemask for this instruction. Instead, the mask is used as an element\r\nselector: every element of the destination is conditionally selected between first source or second source using the\r\nvalue of the related mask bit (0 for the first source operand, 1 for the second source operand).\r\nIf EVEX.z is set, the elements with corresponding mask bit value of 0 in the destination operand are zeroed.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVPBLENDMD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no controlmask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN\r\n DEST[i+31:i] <- SRC2[31:0]\r\n ELSE\r\n DEST[i+31:i] <- SRC2[i+31:i]\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN DEST[i+31:i] <- SRC1[i+31:i]\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI;\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0;\r\n\r\nVPBLENDMD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no controlmask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN\r\n DEST[i+31:i] <- SRC2[31:0]\r\n ELSE\r\n DEST[i+31:i] <- SRC2[i+31:i]\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN DEST[i+31:i] <- SRC1[i+31:i]\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI;\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPBLENDMD __m512i _mm512_mask_blend_epi32(__mmask16 k, __m512i a, __m512i b);\r\nVPBLENDMD __m256i _mm256_mask_blend_epi32(__mmask8 m, __m256i a, __m256i b);\r\nVPBLENDMD __m128i _mm_mask_blend_epi32(__mmask8 m, __m128i a, __m128i b);\r\nVPBLENDMQ __m512i _mm512_mask_blend_epi64(__mmask8 k, __m512i a, __m512i b);\r\nVPBLENDMQ __m256i _mm256_mask_blend_epi64(__mmask8 m, __m256i a, __m256i b);\r\nVPBLENDMQ __m128i _mm_mask_blend_epi64(__mmask8 m, __m128i a, __m128i b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPBLENDMD"
},
{
"description": "-R:VPBLENDMD",
"mnem": "VPBLENDMQ"
},
{
"description": "-R:VPBLENDMB",
"mnem": "VPBLENDMW"
},
{
"description": "VPBROADCAST-Load Integer and Broadcast\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.128.66.0F38.W0 78 /r RM V/V AVX2 Broadcast a byte integer in the source operand\r\n VPBROADCASTB xmm1, xmm2/m8 to sixteen locations in xmm1.\r\n VEX.256.66.0F38.W0 78 /r RM V/V AVX2 Broadcast a byte integer in the source operand\r\n VPBROADCASTB ymm1, xmm2/m8 to thirty-two locations in ymm1.\r\n EVEX.128.66.0F38.W0 78 /r T1S V/V AVX512VL Broadcast a byte integer in the source operand\r\n VPBROADCASTB xmm1{k1}{z}, xmm2/m8 AVX512BW to locations in xmm1 subject to writemask k1.\r\n EVEX.256.66.0F38.W0 78 /r T1S V/V AVX512VL Broadcast a byte integer in the source operand\r\n VPBROADCASTB ymm1{k1}{z}, xmm2/m8 AVX512BW to locations in ymm1 subject to writemask k1.\r\n EVEX.512.66.0F38.W0 78 /r T1S V/V AVX512BW Broadcast a byte integer in the source operand\r\n VPBROADCASTB zmm1{k1}{z}, xmm2/m8 to 64 locations in zmm1 subject to writemask\r\n k1.\r\n VEX.128.66.0F38.W0 79 /r RM V/V AVX2 Broadcast a word integer in the source\r\n VPBROADCASTW xmm1, xmm2/m16 operand to eight locations in xmm1.\r\n VEX.256.66.0F38.W0 79 /r RM V/V AVX2 Broadcast a word integer in the source\r\n VPBROADCASTW ymm1, xmm2/m16 operand to sixteen locations in ymm1.\r\n EVEX.128.66.0F38.W0 79 /r T1S V/V AVX512VL Broadcast a word integer in the source\r\n VPBROADCASTW xmm1{k1}{z}, xmm2/m16 AVX512BW operand to locations in xmm1 subject to\r\n writemask k1.\r\n EVEX.256.66.0F38.W0 79 /r T1S V/V AVX512VL Broadcast a word integer in the source\r\n VPBROADCASTW ymm1{k1}{z}, xmm2/m16 AVX512BW operand to locations in ymm1 subject to\r\n writemask k1.\r\n EVEX.512.66.0F38.W0 79 /r T1S V/V AVX512BW Broadcast a word integer in the source\r\n VPBROADCASTW zmm1{k1}{z}, xmm2/m16 operand to 32 locations in zmm1 subject to\r\n writemask k1.\r\n VEX.128.66.0F38.W0 58 /r RM V/V AVX2 Broadcast a dword integer in the source\r\n VPBROADCASTD xmm1, xmm2/m32 operand to four locations in xmm1.\r\n VEX.256.66.0F38.W0 58 /r RM V/V AVX2 Broadcast a dword integer in the source\r\n VPBROADCASTD ymm1, xmm2/m32 operand to eight locations in ymm1.\r\n EVEX.128.66.0F38.W0 58 /r T1S V/V AVX512VL Broadcast a dword integer in the source\r\n VPBROADCASTD xmm1 {k1}{z}, xmm2/m32 AVX512F operand to locations in xmm1 subject to\r\n writemask k1.\r\n EVEX.256.66.0F38.W0 58 /r T1S V/V AVX512VL Broadcast a dword integer in the source\r\n VPBROADCASTD ymm1 {k1}{z}, xmm2/m32 AVX512F operand to locations in ymm1 subject to\r\n writemask k1.\r\n EVEX.512.66.0F38.W0 58 /r T1S V/V AVX512F Broadcast a dword integer in the source\r\n VPBROADCASTD zmm1 {k1}{z}, xmm2/m32 operand to locations in zmm1 subject to\r\n writemask k1.\r\n VEX.128.66.0F38.W0 59 /r RM V/V AVX2 Broadcast a qword element in source operand\r\n VPBROADCASTQ xmm1, xmm2/m64 to two locations in xmm1.\r\n VEX.256.66.0F38.W0 59 /r RM V/V AVX2 Broadcast a qword element in source operand\r\n VPBROADCASTQ ymm1, xmm2/m64 to four locations in ymm1.\r\n EVEX.128.66.0F38.W1 59 /r T1S V/V AVX512VL Broadcast a qword element in source operand\r\n VPBROADCASTQ xmm1 {k1}{z}, xmm2/m64 AVX512F to locations in xmm1 subject to writemask k1.\r\n EVEX.256.66.0F38.W1 59 /r T1S V/V AVX512VL Broadcast a qword element in source operand\r\n VPBROADCASTQ ymm1 {k1}{z}, xmm2/m64 AVX512F to locations in ymm1 subject to writemask k1.\r\n EVEX.512.66.0F38.W1 59 /r T1S V/V AVX512F Broadcast a qword element in source operand\r\n VPBROADCASTQ zmm1 {k1}{z}, xmm2/m64 to locations in zmm1 subject to writemask k1.\r\n EVEX.128.66.0F38.W0 59 /r T2 V/V AVX512VL Broadcast two dword elements in source\r\n VBROADCASTI32x2 xmm1 {k1}{z}, xmm2/m64 AVX512DQ operand to locations in xmm1 subject to\r\n writemask k1.\r\n\r\n\r\n\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.256.66.0F38.W0 59 /r T2 V/V AVX512VL Broadcast two dword elements in source\r\n VBROADCASTI32x2 ymm1 {k1}{z}, xmm2/m64 AVX512DQ operand to locations in ymm1 subject to\r\n writemask k1.\r\n EVEX.512.66.0F38.W0 59 /r T2 V/V AVX512DQ Broadcast two dword elements in source\r\n VBROADCASTI32x2 zmm1 {k1}{z}, xmm2/m64 operand to locations in zmm1 subject to\r\n writemask k1.\r\n VEX.256.66.0F38.W0 5A /r RM V/V AVX2 Broadcast 128 bits of integer data in mem to\r\n VBROADCASTI128 ymm1, m128 low and high 128-bits in ymm1.\r\n EVEX.256.66.0F38.W0 5A /r T4 V/V AVX512VL Broadcast 128 bits of 4 doubleword integer\r\n VBROADCASTI32X4 ymm1 {k1}{z}, m128 AVX512F data in mem to locations in ymm1 using\r\n writemask k1.\r\n EVEX.512.66.0F38.W0 5A /r T4 V/V AVX512F Broadcast 128 bits of 4 doubleword integer\r\n VBROADCASTI32X4 zmm1 {k1}{z}, m128 data in mem to locations in zmm1 using\r\n writemask k1.\r\n EVEX.256.66.0F38.W1 5A /r T2 V/V AVX512VL Broadcast 128 bits of 2 quadword integer data\r\n VBROADCASTI64X2 ymm1 {k1}{z}, m128 AVX512DQ in mem to locations in ymm1 using writemask\r\n k1.\r\n EVEX.512.66.0F38.W1 5A /r T2 V/V AVX512DQ Broadcast 128 bits of 2 quadword integer data\r\n VBROADCASTI64X2 zmm1 {k1}{z}, m128 in mem to locations in zmm1 using writemask\r\n k1.\r\n EVEX.512.66.0F38.W0 5B /r T8 V/V AVX512DQ Broadcast 256 bits of 8 doubleword integer\r\n VBROADCASTI32X8 zmm1 {k1}{z}, m256 data in mem to locations in zmm1 using\r\n writemask k1.\r\n EVEX.512.66.0F38.W1 5B /r T4 V/V AVX512F Broadcast 256 bits of 4 quadword integer data\r\n VBROADCASTI64X4 zmm1 {k1}{z}, m256 in mem to locations in zmm1 using writemask\r\n k1.\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n T1S, T2, T4, T8 ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nLoad integer data from the source operand (the second operand) and broadcast to all elements of the destination\r\noperand (the first operand).\r\nVEX256-encoded VPBROADCASTB/W/D/Q: The source operand is 8-bit, 16-bit, 32-bit, 64-bit memory location or\r\nthe low 8-bit, 16-bit 32-bit, 64-bit data in an XMM register. The destination operand is a YMM register.\r\nVPBROADCASTI128 support the source operand of 128-bit memory location. Register source encodings for\r\nVPBROADCASTI128 is reserved and will #UD. Bits (MAX_VL-1:256) of the destination register are zeroed.\r\nEVEX-encoded VPBROADCASTD/Q: The source operand is a 32-bit, 64-bit memory location or the low 32-bit, 64-\r\nbit data in an XMM register. The destination operand is a ZMM/YMM/XMM register and updated according to the\r\nwritemask k1.\r\nVPBROADCASTI32X4 and VPBROADCASTI64X4: The destination operand is a ZMM register and updated according\r\nto the writemask k1. The source operand is 128-bit or 256-bit memory location. Register source encodings for\r\nVBROADCASTI32X4 and VBROADCASTI64X4 are reserved and will #UD.\r\nNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\nIf VPBROADCASTI128 is encoded with VEX.L= 0, an attempt to execute the instruction encoded with VEX.L= 0 will\r\ncause an #UD exception.\r\n\r\n\r\n\r\n\r\n\r\n m32 X0\r\n\r\n\r\n\r\n\r\n DEST X0 X0 X0 X0 X0 X0 X0 X0\r\n\r\n\r\n\r\n Figure 5-16. VPBROADCASTD Operation (VEX.256 encoded version)\r\n\r\n\r\n\r\n\r\n m32 X0\r\n\r\n\r\n\r\n\r\n DEST 0 0 0 0 X0 X0 X0 X0\r\n\r\n\r\n\r\n Figure 5-17. VPBROADCASTD Operation (128-bit version)\r\n\r\n\r\n\r\n\r\n m64 X0\r\n\r\n\r\n\r\n\r\n DEST X0 X0 X0 X0\r\n\r\n\r\n\r\n Figure 5-18. VPBROADCASTQ Operation (256-bit version)\r\n\r\n\r\n\r\n\r\n m128 X0\r\n\r\n\r\n\r\n\r\n DEST X0 X0\r\n\r\n\r\n\r\n Figure 5-19. VBROADCASTI128 Operation (256-bit version)\r\n\r\n\r\n m256 X0\r\n\r\n\r\n\r\n\r\n DEST X0 X0\r\n\r\n\r\n\r\n Figure 5-20. VBROADCASTI256 Operation (512-bit version)\r\n\r\n\r\nOperation\r\nVPBROADCASTB (EVEX encoded versions)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\nFOR j <- 0 TO KL-1\r\n i <-j * 8\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- SRC[7:0]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+7:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPBROADCASTW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nFOR j <- 0 TO KL-1\r\n i <-j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- SRC[15:0]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPBROADCASTD (128 bit version)\r\ntemp <- SRC[31:0]\r\nDEST[31:0] <- temp\r\nDEST[63:32] <- temp\r\nDEST[95:64] <- temp\r\nDEST[127:96] <- temp\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\nVPBROADCASTD (VEX.256 encoded version)\r\ntemp <- SRC[31:0]\r\nDEST[31:0] <- temp\r\nDEST[63:32] <- temp\r\nDEST[95:64] <- temp\r\nDEST[127:96] <- temp\r\nDEST[159:128] <- temp\r\nDEST[191:160] <- temp\r\nDEST[223:192] <- temp\r\nDEST[255:224] <- temp\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVPBROADCASTD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <-j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- SRC[31:0]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPBROADCASTQ (VEX.256 encoded version)\r\ntemp <- SRC[63:0]\r\nDEST[63:0] <- temp\r\nDEST[127:64] <- temp\r\nDEST[191:128] <- temp\r\nDEST[255:192] <- temp\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVPBROADCASTQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <-j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- SRC[63:0]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\nVBROADCASTI32x2 (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\n\r\n\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n n <- (j mod 2) * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- SRC[n+31:n]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVBROADCASTI128 (VEX.256 encoded version)\r\ntemp <- SRC[127:0]\r\nDEST[127:0] <- temp\r\nDEST[255:128] <- temp\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVBROADCASTI32X4 (EVEX encoded versions)\r\n(KL, VL) = (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j* 32\r\n n <- (j modulo 4) * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- SRC[n+31:n]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVBROADCASTI64X2 (EVEX encoded versions)\r\n(KL, VL) = (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n n <-(j modulo 2) * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- SRC[n+63:n]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] = 0\r\n FI\r\n FI;\r\nENDFOR;\r\n\r\n\r\n\r\n\r\nVBROADCASTI32X8 (EVEX.U1.512 encoded version)\r\nFOR j <- 0 TO 15\r\n i <- j * 32\r\n n <-(j modulo 8) * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- SRC[n+31:n]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVBROADCASTI64X4 (EVEX.512 encoded version)\r\nFOR j <- 0 TO 7\r\n i <- j * 64\r\n n <- (j modulo 4) * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- SRC[n+63:n]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPBROADCASTB __m512i _mm512_broadcastb_epi8( __m128i a);\r\nVPBROADCASTB __m512i _mm512_mask_broadcastb_epi8(__m512i s, __mmask64 k, __m128i a);\r\nVPBROADCASTB __m512i _mm512_maskz_broadcastb_epi8( __mmask64 k, __m128i a);\r\nVPBROADCASTB __m256i _mm256_broadcastb_epi8(__m128i a);\r\nVPBROADCASTB __m256i _mm256_mask_broadcastb_epi8(__m256i s, __mmask32 k, __m128i a);\r\nVPBROADCASTB __m256i _mm256_maskz_broadcastb_epi8( __mmask32 k, __m128i a);\r\nVPBROADCASTB __m128i _mm_mask_broadcastb_epi8(__m128i s, __mmask16 k, __m128i a);\r\nVPBROADCASTB __m128i _mm_maskz_broadcastb_epi8( __mmask16 k, __m128i a);\r\nVPBROADCASTB __m128i _mm_broadcastb_epi8(__m128i a);\r\nVPBROADCASTD __m512i _mm512_broadcastd_epi32( __m128i a);\r\nVPBROADCASTD __m512i _mm512_mask_broadcastd_epi32(__m512i s, __mmask16 k, __m128i a);\r\nVPBROADCASTD __m512i _mm512_maskz_broadcastd_epi32( __mmask16 k, __m128i a);\r\nVPBROADCASTD __m256i _mm256_broadcastd_epi32( __m128i a);\r\nVPBROADCASTD __m256i _mm256_mask_broadcastd_epi32(__m256i s, __mmask8 k, __m128i a);\r\nVPBROADCASTD __m256i _mm256_maskz_broadcastd_epi32( __mmask8 k, __m128i a);\r\nVPBROADCASTD __m128i _mm_broadcastd_epi32(__m128i a);\r\nVPBROADCASTD __m128i _mm_mask_broadcastd_epi32(__m128i s, __mmask8 k, __m128i a);\r\nVPBROADCASTD __m128i _mm_maskz_broadcastd_epi32( __mmask8 k, __m128i a);\r\nVPBROADCASTQ __m512i _mm512_broadcastq_epi64( __m128i a);\r\nVPBROADCASTQ __m512i _mm512_mask_broadcastq_epi64(__m512i s, __mmask8 k, __m128i a);\r\nVPBROADCASTQ __m512i _mm512_maskz_broadcastq_epi64( __mmask8 k, __m128i a);\r\n\r\n\r\n\r\nVPBROADCASTQ __m256i _mm256_broadcastq_epi64(__m128i a);\r\nVPBROADCASTQ __m256i _mm256_mask_broadcastq_epi64(__m256i s, __mmask8 k, __m128i a);\r\nVPBROADCASTQ __m256i _mm256_maskz_broadcastq_epi64( __mmask8 k, __m128i a);\r\nVPBROADCASTQ __m128i _mm_broadcastq_epi64(__m128i a);\r\nVPBROADCASTQ __m128i _mm_mask_broadcastq_epi64(__m128i s, __mmask8 k, __m128i a);\r\nVPBROADCASTQ __m128i _mm_maskz_broadcastq_epi64( __mmask8 k, __m128i a);\r\nVPBROADCASTW __m512i _mm512_broadcastw_epi16(__m128i a);\r\nVPBROADCASTW __m512i _mm512_mask_broadcastw_epi16(__m512i s, __mmask32 k, __m128i a);\r\nVPBROADCASTW __m512i _mm512_maskz_broadcastw_epi16( __mmask32 k, __m128i a);\r\nVPBROADCASTW __m256i _mm256_broadcastw_epi16(__m128i a);\r\nVPBROADCASTW __m256i _mm256_mask_broadcastw_epi16(__m256i s, __mmask16 k, __m128i a);\r\nVPBROADCASTW __m256i _mm256_maskz_broadcastw_epi16( __mmask16 k, __m128i a);\r\nVPBROADCASTW __m128i _mm_broadcastw_epi16(__m128i a);\r\nVPBROADCASTW __m128i _mm_mask_broadcastw_epi16(__m128i s, __mmask8 k, __m128i a);\r\nVPBROADCASTW __m128i _mm_maskz_broadcastw_epi16( __mmask8 k, __m128i a);\r\nVBROADCASTI32x2 __m512i _mm512_broadcast_i32x2( __m128i a);\r\nVBROADCASTI32x2 __m512i _mm512_mask_broadcast_i32x2(__m512i s, __mmask16 k, __m128i a);\r\nVBROADCASTI32x2 __m512i _mm512_maskz_broadcast_i32x2( __mmask16 k, __m128i a);\r\nVBROADCASTI32x2 __m256i _mm256_broadcast_i32x2( __m128i a);\r\nVBROADCASTI32x2 __m256i _mm256_mask_broadcast_i32x2(__m256i s, __mmask8 k, __m128i a);\r\nVBROADCASTI32x2 __m256i _mm256_maskz_broadcast_i32x2( __mmask8 k, __m128i a);\r\nVBROADCASTI32x2 __m128i _mm_broadcastq_i32x2(__m128i a);\r\nVBROADCASTI32x2 __m128i _mm_mask_broadcastq_i32x2(__m128i s, __mmask8 k, __m128i a);\r\nVBROADCASTI32x2 __m128i _mm_maskz_broadcastq_i32x2( __mmask8 k, __m128i a);\r\nVBROADCASTI32x4 __m512i _mm512_broadcast_i32x4( __m128i a);\r\nVBROADCASTI32x4 __m512i _mm512_mask_broadcast_i32x4(__m512i s, __mmask16 k, __m128i a);\r\nVBROADCASTI32x4 __m512i _mm512_maskz_broadcast_i32x4( __mmask16 k, __m128i a);\r\nVBROADCASTI32x4 __m256i _mm256_broadcast_i32x4( __m128i a);\r\nVBROADCASTI32x4 __m256i _mm256_mask_broadcast_i32x4(__m256i s, __mmask8 k, __m128i a);\r\nVBROADCASTI32x4 __m256i _mm256_maskz_broadcast_i32x4( __mmask8 k, __m128i a);\r\nVBROADCASTI32x8 __m512i _mm512_broadcast_i32x8( __m256i a);\r\nVBROADCASTI32x8 __m512i _mm512_mask_broadcast_i32x8(__m512i s, __mmask16 k, __m256i a);\r\nVBROADCASTI32x8 __m512i _mm512_maskz_broadcast_i32x8( __mmask16 k, __m256i a);\r\nVBROADCASTI64x2 __m512i _mm512_broadcast_i64x2( __m128i a);\r\nVBROADCASTI64x2 __m512i _mm512_mask_broadcast_i64x2(__m512i s, __mmask8 k, __m128i a);\r\nVBROADCASTI64x2 __m512i _mm512_maskz_broadcast_i64x2( __mmask8 k, __m128i a);\r\nVBROADCASTI64x2 __m256i _mm256_broadcast_i64x2( __m128i a);\r\nVBROADCASTI64x2 __m256i _mm256_mask_broadcast_i64x2(__m256i s, __mmask8 k, __m128i a);\r\nVBROADCASTI64x2 __m256i _mm256_maskz_broadcast_i64x2( __mmask8 k, __m128i a);\r\nVBROADCASTI64x4 __m512i _mm512_broadcast_i64x4( __m256i a);\r\nVBROADCASTI64x4 __m512i _mm512_mask_broadcast_i64x4(__m512i s, __mmask8 k, __m256i a);\r\nVBROADCASTI64x4 __m512i _mm512_maskz_broadcast_i64x4( __mmask8 k, __m256i a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nEVEX-encoded instructions, see Exceptions Type 6;\r\nEVEX-encoded instructions, syntax with reg/mem operand, see Exceptions Type E6.\r\n#UD If VEX.L = 0 for VPBROADCASTQ, VPBROADCASTI128.\r\n If EVEX.L'L = 0 for VBROADCASTI32X4/VBROADCASTI64X2.\r\n If EVEX.L'L < 10b for VBROADCASTI32X8/VBROADCASTI64X4.\r\n\r\n\r\n\r\n",
"mnem": "VPBROADCAST"
},
{
"description": "VPBROADCASTB/VPBROADCASTW/VPBROADCASTD/VPBROADCASTQ - Load with Broadcast Integer Data from General Purpose Register\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Feature\r\n Mode Flag\r\n Support\r\n EVEX.128.66.0F38.W0 7A /r T1S V/V AVX512VL Broadcast an 8-bit value from a GPR to all bytes in the\r\n VPBROADCASTB xmm1 {k1}{z}, reg AVX512BW 128-bit destination subject to writemask k1.\r\n EVEX.256.66.0F38.W0 7A /r T1S V/V AVX512VL Broadcast an 8-bit value from a GPR to all bytes in the\r\n VPBROADCASTB ymm1 {k1}{z}, reg AVX512BW 256-bit destination subject to writemask k1.\r\n EVEX.512.66.0F38.W0 7A /r T1S V/V AVX512BW Broadcast an 8-bit value from a GPR to all bytes in the\r\n VPBROADCASTB zmm1 {k1}{z}, reg 512-bit destination subject to writemask k1.\r\n EVEX.128.66.0F38.W0 7B /r T1S V/V AVX512VL Broadcast a 16-bit value from a GPR to all words in the\r\n VPBROADCASTW xmm1 {k1}{z}, reg AVX512BW 128-bit destination subject to writemask k1.\r\n EVEX.256.66.0F38.W0 7B /r T1S V/V AVX512VL Broadcast a 16-bit value from a GPR to all words in the\r\n VPBROADCASTW ymm1 {k1}{z}, reg AVX512BW 256-bit destination subject to writemask k1.\r\n EVEX.512.66.0F38.W0 7B /r T1S V/V AVX512BW Broadcast a 16-bit value from a GPR to all words in the\r\n VPBROADCASTW zmm1 {k1}{z}, reg 512-bit destination subject to writemask k1.\r\n EVEX.128.66.0F38.W0 7C /r T1S V/V AVX512VL Broadcast a 32-bit value from a GPR to all double-words\r\n VPBROADCASTD xmm1 {k1}{z}, r32 AVX512F in the 128-bit destination subject to writemask k1.\r\n EVEX.256.66.0F38.W0 7C /r T1S V/V AVX512VL Broadcast a 32-bit value from a GPR to all double-words\r\n VPBROADCASTD ymm1 {k1}{z}, r32 AVX512F in the 256-bit destination subject to writemask k1.\r\n EVEX.512.66.0F38.W0 7C /r T1S V/V AVX512F Broadcast a 32-bit value from a GPR to all double-words\r\n VPBROADCASTD zmm1 {k1}{z}, r32 in the 512-bit destination subject to writemask k1.\r\n EVEX.128.66.0F38.W1 7C /r T1S V/N.E.1 AVX512VL Broadcast a 64-bit value from a GPR to all quad-words in\r\n VPBROADCASTQ xmm1 {k1}{z}, r64 AVX512F the 128-bit destination subject to writemask k1.\r\n EVEX.256.66.0F38.W1 7C /r T1S V/N.E.1 AVX512VL Broadcast a 64-bit value from a GPR to all quad-words in\r\n VPBROADCASTQ ymm1 {k1}{z}, r64 AVX512F the 256-bit destination subject to writemask k1.\r\n EVEX.512.66.0F38.W1 7C /r T1S V/N.E.1 AVX512F Broadcast a 64-bit value from a GPR to all quad-words in\r\n VPBROADCASTQ zmm1 {k1}{z}, r64 the 512-bit destination subject to writemask k1.\r\nNOTES:\r\n1. EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is used.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nBroadcasts a 8-bit, 16-bit, 32-bit or 64-bit value from a general-purpose register (the second operand) to all the\r\nlocations in the destination vector register (the first operand) using the writemask k1.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVPBROADCASTB (EVEX encoded versions)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\nFOR j <- 0 TO KL-1\r\n i <-j * 8\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- SRC[7:0]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+7:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPBROADCASTW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nFOR j <- 0 TO KL-1\r\n i <-j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- SRC[15:0]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPBROADCASTD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <-j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- SRC[31:0]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVPBROADCASTQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <-j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- SRC[63:0]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPBROADCASTB __m512i _mm512_mask_set1_epi8(__m512i s, __mmask64 k, int a);\r\nVPBROADCASTB __m512i _mm512_maskz_set1_epi8( __mmask64 k, int a);\r\nVPBROADCASTB __m256i _mm256_mask_set1_epi8(__m256i s, __mmask32 k, int a);\r\nVPBROADCASTB __m256i _mm256_maskz_set1_epi8( __mmask32 k, int a);\r\nVPBROADCASTB __m128i _mm_mask_set1_epi8(__m128i s, __mmask16 k, int a);\r\nVPBROADCASTB __m128i _mm_maskz_set1_epi8( __mmask16 k, int a);\r\nVPBROADCASTD __m512i _mm512_mask_set1_epi32(__m512i s, __mmask16 k, int a);\r\nVPBROADCASTD __m512i _mm512_maskz_set1_epi32( __mmask16 k, int a);\r\nVPBROADCASTD __m256i _mm256_mask_set1_epi32(__m256i s, __mmask8 k, int a);\r\nVPBROADCASTD __m256i _mm256_maskz_set1_epi32( __mmask8 k, int a);\r\nVPBROADCASTD __m128i _mm_mask_set1_epi32(__m128i s, __mmask8 k, int a);\r\nVPBROADCASTD __m128i _mm_maskz_set1_epi32( __mmask8 k, int a);\r\nVPBROADCASTQ __m512i _mm512_mask_set1_epi64(__m512i s, __mmask8 k, __int64 a);\r\nVPBROADCASTQ __m512i _mm512_maskz_set1_epi64( __mmask8 k, __int64 a);\r\nVPBROADCASTQ __m256i _mm256_mask_set1_epi64(__m256i s, __mmask8 k, __int64 a);\r\nVPBROADCASTQ __m256i _mm256_maskz_set1_epi64( __mmask8 k, __int64 a);\r\nVPBROADCASTQ __m128i _mm_mask_set1_epi64(__m128i s, __mmask8 k, __int64 a);\r\nVPBROADCASTQ __m128i _mm_maskz_set1_epi64( __mmask8 k, __int64 a);\r\nVPBROADCASTW __m512i _mm512_mask_set1_epi16(__m512i s, __mmask32 k, int a);\r\nVPBROADCASTW __m512i _mm512_maskz_set1_epi16( __mmask32 k, int a);\r\nVPBROADCASTW __m256i _mm256_mask_set1_epi16(__m256i s, __mmask16 k, int a);\r\nVPBROADCASTW __m256i _mm256_maskz_set1_epi16( __mmask16 k, int a);\r\nVPBROADCASTW __m128i _mm_mask_set1_epi16(__m128i s, __mmask8 k, int a);\r\nVPBROADCASTW __m128i _mm_maskz_set1_epi16( __mmask8 k, int a);\r\n\r\nExceptions\r\nEVEX-encoded instructions, see Exceptions Type E7NM.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPBROADCASTB"
},
{
"description": "-R:VPBROADCASTB",
"mnem": "VPBROADCASTD"
},
{
"description": "VPBROADCASTM-Broadcast Mask to Vector Register\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.F3.0F38.W1 2A /r RM V/V AVX512VL Broadcast low byte value in k1 to two locations in xmm1.\r\n VPBROADCASTMB2Q xmm1, k1 AVX512CD\r\n EVEX.256.F3.0F38.W1 2A /r RM V/V AVX512VL Broadcast low byte value in k1 to four locations in ymm1.\r\n VPBROADCASTMB2Q ymm1, k1 AVX512CD\r\n EVEX.512.F3.0F38.W1 2A /r RM V/V AVX512CD Broadcast low byte value in k1 to eight locations in zmm1.\r\n VPBROADCASTMB2Q zmm1, k1\r\n EVEX.128.F3.0F38.W0 3A /r RM V/V AVX512VL Broadcast low word value in k1 to four locations in xmm1.\r\n VPBROADCASTMW2D xmm1, k1 AVX512CD\r\n EVEX.256.F3.0F38.W0 3A /r RM V/V AVX512VL Broadcast low word value in k1 to eight locations in ymm1.\r\n VPBROADCASTMW2D ymm1, k1 AVX512CD\r\n EVEX.512.F3.0F38.W0 3A /r RM V/V AVX512CD Broadcast low word value in k1 to sixteen locations in\r\n VPBROADCASTMW2D zmm1, k1 zmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nBroadcasts the zero-extended 64/32 bit value of the low byte/word of the source operand (the second operand) to\r\neach 64/32 bit element of the destination operand (the first operand). The source operand is an opmask register.\r\nThe destination operand is a ZMM register (EVEX.512), YMM register (EVEX.256), or XMM register (EVEX.128).\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\nOperation\r\nVPBROADCASTMB2Q\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j*64\r\n DEST[i+63:i] <- ZeroExtend(SRC[7:0])\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPBROADCASTMW2D\r\n(KL, VL) = (4, 128), (8, 256),(16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j*32\r\n DEST[i+31:i] <- ZeroExtend(SRC[15:0])\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n\r\nVPBROADCASTMB2Q __m512i _mm512_broadcastmb_epi64( __mmask8);\r\nVPBROADCASTMW2D __m512i _mm512_broadcastmw_epi32( __mmask16);\r\nVPBROADCASTMB2Q __m256i _mm256_broadcastmb_epi64( __mmask8);\r\nVPBROADCASTMW2D __m256i _mm256_broadcastmw_epi32( __mmask8);\r\nVPBROADCASTMB2Q __m128i _mm_broadcastmb_epi64( __mmask8);\r\nVPBROADCASTMW2D __m128i _mm_broadcastmw_epi32( __mmask8);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nEVEX-encoded instruction, see Exceptions Type E6NF.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPBROADCASTM"
},
{
"description": "-R:VPBROADCASTB",
"mnem": "VPBROADCASTQ"
},
{
"description": "-R:VPBROADCASTB",
"mnem": "VPBROADCASTW"
},
{
"description": "VPCMPB/VPCMPUB-Compare Packed Byte Values Into Mask\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.128.66.0F3A.W0 3F /r ib FVM V/V AVX512VL Compare packed signed byte values in xmm3/m128 and\r\n AVX512BW xmm2 using bits 2:0 of imm8 as a comparison predicate\r\n VPCMPB k1 {k2}, xmm2, with writemask k2 and leave the result in mask register\r\n xmm3/m128, imm8 k1.\r\n EVEX.NDS.256.66.0F3A.W0 3F /r ib FVM V/V AVX512VL Compare packed signed byte values in ymm3/m256 and\r\n AVX512BW ymm2 using bits 2:0 of imm8 as a comparison predicate\r\n VPCMPB k1 {k2}, ymm2, with writemask k2 and leave the result in mask register\r\n ymm3/m256, imm8 k1.\r\n EVEX.NDS.512.66.0F3A.W0 3F /r ib FVM V/V AVX512BW Compare packed signed byte values in zmm3/m512 and\r\n VPCMPB k1 {k2}, zmm2, zmm2 using bits 2:0 of imm8 as a comparison predicate\r\n zmm3/m512, imm8 with writemask k2 and leave the result in mask register\r\n k1.\r\n EVEX.NDS.128.66.0F3A.W0 3E /r ib FVM V/V AVX512VL Compare packed unsigned byte values in xmm3/m128\r\n AVX512BW and xmm2 using bits 2:0 of imm8 as a comparison\r\n VPCMPUB k1 {k2}, xmm2, predicate with writemask k2 and leave the result in mask\r\n xmm3/m128, imm8 register k1.\r\n EVEX.NDS.256.66.0F3A.W0 3E /r ib FVM V/V AVX512VL Compare packed unsigned byte values in ymm3/m256\r\n AVX512BW and ymm2 using bits 2:0 of imm8 as a comparison\r\n VPCMPUB k1 {k2}, ymm2, predicate with writemask k2 and leave the result in mask\r\n ymm3/m256, imm8 register k1.\r\n EVEX.NDS.512.66.0F3A.W0 3E /r ib FVM V/V AVX512BW Compare packed unsigned byte values in zmm3/m512\r\n VPCMPUB k1 {k2}, zmm2, and zmm2 using bits 2:0 of imm8 as a comparison\r\n zmm3/m512, imm8 predicate with writemask k2 and leave the result in mask\r\n register k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FVM ModRM:reg (w) vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a SIMD compare of the packed byte values in the second source operand and the first source operand and\r\nreturns the results of the comparison to the mask destination operand. The comparison predicate operand (imme-\r\ndiate byte) specifies the type of comparison performed on each pair of packed values in the two source operands.\r\nThe result of each comparison is a single mask bit result of 1 (comparison true) or 0 (comparison false).\r\nVPCMPB performs a comparison between pairs of signed byte values.\r\nVPCMPUB performs a comparison between pairs of unsigned byte values.\r\nThe first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a\r\nZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand (first operand) is a mask\r\nregister k1. Up to 64/32/16 comparisons are performed with results written to the destination operand under the\r\nwritemask k2.\r\n\r\n\r\n\r\n\r\n\r\nThe comparison predicate operand is an 8-bit immediate: bits 2:0 define the type of comparison to be performed.\r\nBits 3 through 7 of the immediate are reserved. Compiler can implement the pseudo-op mnemonic listed in Table\r\n5-10.\r\n\r\n\r\n Table 5-10. Pseudo-Op and VPCMP* Implementation\r\n:\r\n\r\n\r\n\r\n\r\n Pseudo-Op PCMPM Implementation\r\n VPCMPEQ* reg1, reg2, reg3 VPCMP* reg1, reg2, reg3, 0\r\n VPCMPLT* reg1, reg2, reg3 VPCMP*reg1, reg2, reg3, 1\r\n VPCMPLE* reg1, reg2, reg3 VPCMP* reg1, reg2, reg3, 2\r\n VPCMPNEQ* reg1, reg2, reg3 VPCMP* reg1, reg2, reg3, 4\r\n VPPCMPNLT* reg1, reg2, reg3 VPCMP* reg1, reg2, reg3, 5\r\n VPCMPNLE* reg1, reg2, reg3 VPCMP* reg1, reg2, reg3, 6\r\n\r\nOperation\r\nCASE (COMPARISON PREDICATE) OF\r\n 0: OP <- EQ;\r\n 1: OP <- LT;\r\n 2: OP <- LE;\r\n 3: OP <- FALSE;\r\n 4: OP <- NEQ ;\r\n 5: OP <- NLT;\r\n 6: OP <- NLE;\r\n 7: OP <- TRUE;\r\nESAC;\r\n\r\nVPCMPB (EVEX encoded versions)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\nFOR j <- 0 TO KL-1\r\n i<-j*8\r\n IF k2[j] OR *no writemask*\r\n THEN\r\n CMP <- SRC1[i+7:i] OP SRC2[i+7:i];\r\n IF CMP = TRUE\r\n THEN DEST[j] <- 1;\r\n ELSE DEST[j] <- 0; FI;\r\n ELSE DEST[j] = 0 ; zeroing-masking onlyFI;\r\n FI;\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVPCMPUB (EVEX encoded versions)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\nFOR j <- 0 TO KL-1\r\n i<-j*8\r\n IF k2[j] OR *no writemask*\r\n THEN\r\n CMP <- SRC1[i+7:i] OP SRC2[i+7:i];\r\n IF CMP = TRUE\r\n THEN DEST[j] <- 1;\r\n ELSE DEST[j] <- 0; FI;\r\n ELSE DEST[j] = 0 ; zeroing-masking onlyFI;\r\n FI;\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPCMPB __mmask64 _mm512_cmp_epi8_mask( __m512i a, __m512i b, int cmp);\r\nVPCMPB __mmask64 _mm512_mask_cmp_epi8_mask( __mmask64 m, __m512i a, __m512i b, int cmp);\r\nVPCMPB __mmask32 _mm256_cmp_epi8_mask( __m256i a, __m256i b, int cmp);\r\nVPCMPB __mmask32 _mm256_mask_cmp_epi8_mask( __mmask32 m, __m256i a, __m256i b, int cmp);\r\nVPCMPB __mmask16 _mm_cmp_epi8_mask( __m128i a, __m128i b, int cmp);\r\nVPCMPB __mmask16 _mm_mask_cmp_epi8_mask( __mmask16 m, __m128i a, __m128i b, int cmp);\r\nVPCMPB __mmask64 _mm512_cmp[eq|ge|gt|le|lt|neq]_epi8_mask( __m512i a, __m512i b);\r\nVPCMPB __mmask64 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epi8_mask( __mmask64 m, __m512i a, __m512i b);\r\nVPCMPB __mmask32 _mm256_cmp[eq|ge|gt|le|lt|neq]_epi8_mask( __m256i a, __m256i b);\r\nVPCMPB __mmask32 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epi8_mask( __mmask32 m, __m256i a, __m256i b);\r\nVPCMPB __mmask16 _mm_cmp[eq|ge|gt|le|lt|neq]_epi8_mask( __m128i a, __m128i b);\r\nVPCMPB __mmask16 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epi8_mask( __mmask16 m, __m128i a, __m128i b);\r\nVPCMPUB __mmask64 _mm512_cmp_epu8_mask( __m512i a, __m512i b, int cmp);\r\nVPCMPUB __mmask64 _mm512_mask_cmp_epu8_mask( __mmask64 m, __m512i a, __m512i b, int cmp);\r\nVPCMPUB __mmask32 _mm256_cmp_epu8_mask( __m256i a, __m256i b, int cmp);\r\nVPCMPUB __mmask32 _mm256_mask_cmp_epu8_mask( __mmask32 m, __m256i a, __m256i b, int cmp);\r\nVPCMPUB __mmask16 _mm_cmp_epu8_mask( __m128i a, __m128i b, int cmp);\r\nVPCMPUB __mmask16 _mm_mask_cmp_epu8_mask( __mmask16 m, __m128i a, __m128i b, int cmp);\r\nVPCMPUB __mmask64 _mm512_cmp[eq|ge|gt|le|lt|neq]_epu8_mask( __m512i a, __m512i b, int cmp);\r\nVPCMPUB __mmask64 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epu8_mask( __mmask64 m, __m512i a, __m512i b, int cmp);\r\nVPCMPUB __mmask32 _mm256_cmp[eq|ge|gt|le|lt|neq]_epu8_mask( __m256i a, __m256i b, int cmp);\r\nVPCMPUB __mmask32 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epu8_mask( __mmask32 m, __m256i a, __m256i b, int cmp);\r\nVPCMPUB __mmask16 _mm_cmp[eq|ge|gt|le|lt|neq]_epu8_mask( __m128i a, __m128i b, int cmp);\r\nVPCMPUB __mmask16 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epu8_mask( __mmask16 m, __m128i a, __m128i b, int cmp);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nEVEX-encoded instruction, see Exceptions Type E4.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPCMPB"
},
{
"description": "VPCMPD/VPCMPUD-Compare Packed Integer Values into Mask\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.128.66.0F3A.W0 1F /r ib FV V/V AVX512VL Compare packed signed doubleword integer values in\r\n VPCMPD k1 {k2}, xmm2, AVX512F xmm3/m128/m32bcst and xmm2 using bits 2:0 of imm8\r\n xmm3/m128/m32bcst, imm8 as a comparison predicate with writemask k2 and leave\r\n the result in mask register k1.\r\n EVEX.NDS.256.66.0F3A.W0 1F /r ib FV V/V AVX512VL Compare packed signed doubleword integer values in\r\n VPCMPD k1 {k2}, ymm2, AVX512F ymm3/m256/m32bcst and ymm2 using bits 2:0 of imm8\r\n ymm3/m256/m32bcst, imm8 as a comparison predicate with writemask k2 and leave\r\n the result in mask register k1.\r\n EVEX.NDS.512.66.0F3A.W0 1F /r ib FV V/V AVX512F Compare packed signed doubleword integer values in\r\n VPCMPD k1 {k2}, zmm2, zmm2 and zmm3/m512/m32bcst using bits 2:0 of imm8\r\n zmm3/m512/m32bcst, imm8 as a comparison predicate. The comparison results are\r\n written to the destination k1 under writemask k2.\r\n EVEX.NDS.128.66.0F3A.W0 1E /r ib FV V/V AVX512VL Compare packed unsigned doubleword integer values in\r\n VPCMPUD k1 {k2}, xmm2, AVX512F xmm3/m128/m32bcst and xmm2 using bits 2:0 of imm8\r\n xmm3/m128/m32bcst, imm8 as a comparison predicate with writemask k2 and leave\r\n the result in mask register k1.\r\n EVEX.NDS.256.66.0F3A.W0 1E /r ib FV V/V AVX512VL Compare packed unsigned doubleword integer values in\r\n VPCMPUD k1 {k2}, ymm2, AVX512F ymm3/m256/m32bcst and ymm2 using bits 2:0 of imm8\r\n ymm3/m256/m32bcst, imm8 as a comparison predicate with writemask k2 and leave\r\n the result in mask register k1.\r\n EVEX.NDS.512.66.0F3A.W0 1E /r ib FV V/V AVX512F Compare packed unsigned doubleword integer values in\r\n VPCMPUD k1 {k2}, zmm2, zmm2 and zmm3/m512/m32bcst using bits 2:0 of imm8\r\n zmm3/m512/m32bcst, imm8 as a comparison predicate. The comparison results are\r\n written to the destination k1 under writemask k2.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) Imm8\r\n\r\nDescription\r\nPerforms a SIMD compare of the packed integer values in the second source operand and the first source operand\r\nand returns the results of the comparison to the mask destination operand. The comparison predicate operand\r\n(immediate byte) specifies the type of comparison performed on each pair of packed values in the two source oper-\r\nands. The result of each comparison is a single mask bit result of 1 (comparison true) or 0 (comparison false).\r\nVPCMPD/VPCMPUD performs a comparison between pairs of signed/unsigned doubleword integer values.\r\nThe first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a\r\nZMM/YMM/XMM register or a 512/256/128-bit memory location or a 512-bit vector broadcasted from a 32-bit\r\nmemory location. The destination operand (first operand) is a mask register k1. Up to 16/8/4 comparisons are\r\nperformed with results written to the destination operand under the writemask k2.\r\nThe comparison predicate operand is an 8-bit immediate: bits 2:0 define the type of comparison to be performed.\r\nBits 3 through 7 of the immediate are reserved. Compiler can implement the pseudo-op mnemonic listed in Table\r\n5-10.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nCASE (COMPARISON PREDICATE) OF\r\n 0: OP <- EQ;\r\n 1: OP <- LT;\r\n 2: OP <- LE;\r\n 3: OP <- FALSE;\r\n 4: OP <- NEQ;\r\n 5: OP <- NLT;\r\n 6: OP <- NLE;\r\n 7: OP <- TRUE;\r\nESAC;\r\n\r\nVPCMPD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k2[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN CMP <- SRC1[i+31:i] OP SRC2[31:0];\r\n ELSE CMP <- SRC1[i+31:i] OP SRC2[i+31:i];\r\n FI;\r\n IF CMP = TRUE\r\n THEN DEST[j] <- 1;\r\n ELSE DEST[j] <- 0; FI;\r\n ELSE DEST[j] <- 0 ; zeroing-masking onlyFI;\r\n FI;\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\nVPCMPUD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k2[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN CMP <- SRC1[i+31:i] OP SRC2[31:0];\r\n ELSE CMP <- SRC1[i+31:i] OP SRC2[i+31:i];\r\n FI;\r\n IF CMP = TRUE\r\n THEN DEST[j] <- 1;\r\n ELSE DEST[j] <- 0; FI;\r\n ELSE DEST[j] <- 0 ; zeroing-masking onlyFI;\r\n FI;\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPCMPD __mmask16 _mm512_cmp_epi32_mask( __m512i a, __m512i b, int imm);\r\nVPCMPD __mmask16 _mm512_mask_cmp_epi32_mask(__mmask16 k, __m512i a, __m512i b, int imm);\r\nVPCMPD __mmask16 _mm512_cmp[eq|ge|gt|le|lt|neq]_epi32_mask( __m512i a, __m512i b);\r\nVPCMPD __mmask16 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epi32_mask(__mmask16 k, __m512i a, __m512i b);\r\nVPCMPUD __mmask16 _mm512_cmp_epu32_mask( __m512i a, __m512i b, int imm);\r\nVPCMPUD __mmask16 _mm512_mask_cmp_epu32_mask(__mmask16 k, __m512i a, __m512i b, int imm);\r\nVPCMPUD __mmask16 _mm512_cmp[eq|ge|gt|le|lt|neq]_epu32_mask( __m512i a, __m512i b);\r\nVPCMPUD __mmask16 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epu32_mask(__mmask16 k, __m512i a, __m512i b);\r\nVPCMPD __mmask8 _mm256_cmp_epi32_mask( __m256i a, __m256i b, int imm);\r\nVPCMPD __mmask8 _mm256_mask_cmp_epi32_mask(__mmask8 k, __m256i a, __m256i b, int imm);\r\nVPCMPD __mmask8 _mm256_cmp[eq|ge|gt|le|lt|neq]_epi32_mask( __m256i a, __m256i b);\r\nVPCMPD __mmask8 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epi32_mask(__mmask8 k, __m256i a, __m256i b);\r\nVPCMPUD __mmask8 _mm256_cmp_epu32_mask( __m256i a, __m256i b, int imm);\r\nVPCMPUD __mmask8 _mm256_mask_cmp_epu32_mask(__mmask8 k, __m256i a, __m256i b, int imm);\r\nVPCMPUD __mmask8 _mm256_cmp[eq|ge|gt|le|lt|neq]_epu32_mask( __m256i a, __m256i b);\r\nVPCMPUD __mmask8 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epu32_mask(__mmask8 k, __m256i a, __m256i b);\r\nVPCMPD __mmask8 _mm_cmp_epi32_mask( __m128i a, __m128i b, int imm);\r\nVPCMPD __mmask8 _mm_mask_cmp_epi32_mask(__mmask8 k, __m128i a, __m128i b, int imm);\r\nVPCMPD __mmask8 _mm_cmp[eq|ge|gt|le|lt|neq]_epi32_mask( __m128i a, __m128i b);\r\nVPCMPD __mmask8 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epi32_mask(__mmask8 k, __m128i a, __m128i b);\r\nVPCMPUD __mmask8 _mm_cmp_epu32_mask( __m128i a, __m128i b, int imm);\r\nVPCMPUD __mmask8 _mm_mask_cmp_epu32_mask(__mmask8 k, __m128i a, __m128i b, int imm);\r\nVPCMPUD __mmask8 _mm_cmp[eq|ge|gt|le|lt|neq]_epu32_mask( __m128i a, __m128i b);\r\nVPCMPUD __mmask8 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epu32_mask(__mmask8 k, __m128i a, __m128i b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPCMPD"
},
{
"description": "VPCMPQ/VPCMPUQ-Compare Packed Integer Values into Mask\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.128.66.0F3A.W1 1F /r ib FV V/V AVX512VL Compare packed signed quadword integer values in\r\n VPCMPQ k1 {k2}, xmm2, AVX512F xmm3/m128/m64bcst and xmm2 using bits 2:0 of imm8\r\n xmm3/m128/m64bcst, imm8 as a comparison predicate with writemask k2 and leave\r\n the result in mask register k1.\r\n EVEX.NDS.256.66.0F3A.W1 1F /r ib FV V/V AVX512VL Compare packed signed quadword integer values in\r\n VPCMPQ k1 {k2}, ymm2, AVX512F ymm3/m256/m64bcst and ymm2 using bits 2:0 of imm8\r\n ymm3/m256/m64bcst, imm8 as a comparison predicate with writemask k2 and leave\r\n the result in mask register k1.\r\n EVEX.NDS.512.66.0F3A.W1 1F /r ib FV V/V AVX512F Compare packed signed quadword integer values in\r\n VPCMPQ k1 {k2}, zmm2, zmm3/m512/m64bcst and zmm2 using bits 2:0 of imm8\r\n zmm3/m512/m64bcst, imm8 as a comparison predicate with writemask k2 and leave\r\n the result in mask register k1.\r\n EVEX.NDS.128.66.0F3A.W1 1E /r ib FV V/V AVX512VL Compare packed unsigned quadword integer values in\r\n VPCMPUQ k1 {k2}, xmm2, AVX512F xmm3/m128/m64bcst and xmm2 using bits 2:0 of imm8\r\n xmm3/m128/m64bcst, imm8 as a comparison predicate with writemask k2 and leave\r\n the result in mask register k1.\r\n EVEX.NDS.256.66.0F3A.W1 1E /r ib FV V/V AVX512VL Compare packed unsigned quadword integer values in\r\n VPCMPUQ k1 {k2}, ymm2, AVX512F ymm3/m256/m64bcst and ymm2 using bits 2:0 of imm8\r\n ymm3/m256/m64bcst, imm8 as a comparison predicate with writemask k2 and leave\r\n the result in mask register k1.\r\n EVEX.NDS.512.66.0F3A.W1 1E /r ib FV V/V AVX512F Compare packed unsigned quadword integer values in\r\n VPCMPUQ k1 {k2}, zmm2, zmm3/m512/m64bcst and zmm2 using bits 2:0 of imm8\r\n zmm3/m512/m64bcst, imm8 as a comparison predicate with writemask k2 and leave\r\n the result in mask register k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) Imm8\r\n\r\nDescription\r\nPerforms a SIMD compare of the packed integer values in the second source operand and the first source operand\r\nand returns the results of the comparison to the mask destination operand. The comparison predicate operand\r\n(immediate byte) specifies the type of comparison performed on each pair of packed values in the two source oper-\r\nands. The result of each comparison is a single mask bit result of 1 (comparison true) or 0 (comparison false).\r\nVPCMPQ/VPCMPUQ performs a comparison between pairs of signed/unsigned quadword integer values.\r\nThe first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a\r\nZMM/YMM/XMM register or a 512/256/128-bit memory location or a 512-bit vector broadcasted from a 64-bit\r\nmemory location. The destination operand (first operand) is a mask register k1. Up to 8/4/2 comparisons are\r\nperformed with results written to the destination operand under the writemask k2.\r\nThe comparison predicate operand is an 8-bit immediate: bits 2:0 define the type of comparison to be performed.\r\nBits 3 through 7 of the immediate are reserved. Compiler can implement the pseudo-op mnemonic listed in Table\r\n5-10.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nCASE (COMPARISON PREDICATE) OF\r\n 0: OP <- EQ;\r\n 1: OP <- LT;\r\n 2: OP <- LE;\r\n 3: OP <- FALSE;\r\n 4: OP <- NEQ;\r\n 5: OP <- NLT;\r\n 6: OP <- NLE;\r\n 7: OP <- TRUE;\r\nESAC;\r\n\r\nVPCMPQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k2[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN CMP <- SRC1[i+63:i] OP SRC2[63:0];\r\n ELSE CMP <- SRC1[i+63:i] OP SRC2[i+63:i];\r\n FI;\r\n IF CMP = TRUE\r\n THEN DEST[j] <- 1;\r\n ELSE DEST[j] <- 0; FI;\r\n ELSE DEST[j] <- 0 ; zeroing-masking only\r\n FI;\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\nVPCMPUQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k2[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN CMP <- SRC1[i+63:i] OP SRC2[63:0];\r\n ELSE CMP <- SRC1[i+63:i] OP SRC2[i+63:i];\r\n FI;\r\n IF CMP = TRUE\r\n THEN DEST[j] <- 1;\r\n ELSE DEST[j] <- 0; FI;\r\n ELSE DEST[j] <- 0 ; zeroing-masking only\r\n FI;\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPCMPQ __mmask8 _mm512_cmp_epi64_mask( __m512i a, __m512i b, int imm);\r\nVPCMPQ __mmask8 _mm512_mask_cmp_epi64_mask(__mmask8 k, __m512i a, __m512i b, int imm);\r\nVPCMPQ __mmask8 _mm512_cmp[eq|ge|gt|le|lt|neq]_epi64_mask( __m512i a, __m512i b);\r\nVPCMPQ __mmask8 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epi64_mask(__mmask8 k, __m512i a, __m512i b);\r\nVPCMPUQ __mmask8 _mm512_cmp_epu64_mask( __m512i a, __m512i b, int imm);\r\nVPCMPUQ __mmask8 _mm512_mask_cmp_epu64_mask(__mmask8 k, __m512i a, __m512i b, int imm);\r\nVPCMPUQ __mmask8 _mm512_cmp[eq|ge|gt|le|lt|neq]_epu64_mask( __m512i a, __m512i b);\r\nVPCMPUQ __mmask8 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epu64_mask(__mmask8 k, __m512i a, __m512i b);\r\nVPCMPQ __mmask8 _mm256_cmp_epi64_mask( __m256i a, __m256i b, int imm);\r\nVPCMPQ __mmask8 _mm256_mask_cmp_epi64_mask(__mmask8 k, __m256i a, __m256i b, int imm);\r\nVPCMPQ __mmask8 _mm256_cmp[eq|ge|gt|le|lt|neq]_epi64_mask( __m256i a, __m256i b);\r\nVPCMPQ __mmask8 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epi64_mask(__mmask8 k, __m256i a, __m256i b);\r\nVPCMPUQ __mmask8 _mm256_cmp_epu64_mask( __m256i a, __m256i b, int imm);\r\nVPCMPUQ __mmask8 _mm256_mask_cmp_epu64_mask(__mmask8 k, __m256i a, __m256i b, int imm);\r\nVPCMPUQ __mmask8 _mm256_cmp[eq|ge|gt|le|lt|neq]_epu64_mask( __m256i a, __m256i b);\r\nVPCMPUQ __mmask8 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epu64_mask(__mmask8 k, __m256i a, __m256i b);\r\nVPCMPQ __mmask8 _mm_cmp_epi64_mask( __m128i a, __m128i b, int imm);\r\nVPCMPQ __mmask8 _mm_mask_cmp_epi64_mask(__mmask8 k, __m128i a, __m128i b, int imm);\r\nVPCMPQ __mmask8 _mm_cmp[eq|ge|gt|le|lt|neq]_epi64_mask( __m128i a, __m128i b);\r\nVPCMPQ __mmask8 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epi64_mask(__mmask8 k, __m128i a, __m128i b);\r\nVPCMPUQ __mmask8 _mm_cmp_epu64_mask( __m128i a, __m128i b, int imm);\r\nVPCMPUQ __mmask8 _mm_mask_cmp_epu64_mask(__mmask8 k, __m128i a, __m128i b, int imm);\r\nVPCMPUQ __mmask8 _mm_cmp[eq|ge|gt|le|lt|neq]_epu64_mask( __m128i a, __m128i b);\r\nVPCMPUQ __mmask8 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epu64_mask(__mmask8 k, __m128i a, __m128i b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPCMPQ"
},
{
"description": "-R:VPCMPB",
"mnem": "VPCMPUB"
},
{
"description": "-R:VPCMPD",
"mnem": "VPCMPUD"
},
{
"description": "-R:VPCMPQ",
"mnem": "VPCMPUQ"
},
{
"description": "-R:VPCMPW",
"mnem": "VPCMPUW"
},
{
"description": "VPCMPW/VPCMPUW-Compare Packed Word Values Into Mask\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.128.66.0F3A.W1 3F /r ib FVM V/V AVX512VL Compare packed signed word integers in xmm3/m128\r\n AVX512BW and xmm2 using bits 2:0 of imm8 as a comparison\r\n VPCMPW k1 {k2}, xmm2, predicate with writemask k2 and leave the result in\r\n xmm3/m128, imm8 mask register k1.\r\n EVEX.NDS.256.66.0F3A.W1 3F /r ib FVM V/V AVX512VL Compare packed signed word integers in ymm3/m256\r\n AVX512BW and ymm2 using bits 2:0 of imm8 as a comparison\r\n VPCMPW k1 {k2}, ymm2, predicate with writemask k2 and leave the result in\r\n ymm3/m256, imm8 mask register k1.\r\n EVEX.NDS.512.66.0F3A.W1 3F /r ib FVM V/V AVX512BW Compare packed signed word integers in zmm3/m512\r\n VPCMPW k1 {k2}, zmm2, and zmm2 using bits 2:0 of imm8 as a comparison\r\n zmm3/m512, imm8 predicate with writemask k2 and leave the result in\r\n mask register k1.\r\n EVEX.NDS.128.66.0F3A.W1 3E /r ib FVM V/V AVX512VL Compare packed unsigned word integers in xmm3/m128\r\n AVX512BW and xmm2 using bits 2:0 of imm8 as a comparison\r\n VPCMPUW k1 {k2}, xmm2, predicate with writemask k2 and leave the result in\r\n xmm3/m128, imm8 mask register k1.\r\n EVEX.NDS.256.66.0F3A.W1 3E /r ib FVM V/V AVX512VL Compare packed unsigned word integers in ymm3/m256\r\n AVX512BW and ymm2 using bits 2:0 of imm8 as a comparison\r\n VPCMPUW k1 {k2}, ymm2, predicate with writemask k2 and leave the result in\r\n ymm3/m256, imm8 mask register k1.\r\n VPCMPUW k1 {k2}, zmm2, FVM V/V AVX512BW Compare packed unsigned word integers in zmm3/m512\r\n zmm3/m512, imm8 and zmm2 using bits 2:0 of imm8 as a comparison\r\n predicate with writemask k2 and leave the result in\r\n mask register k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FVM ModRM:reg (w) vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a SIMD compare of the packed integer word in the second source operand and the first source operand\r\nand returns the results of the comparison to the mask destination operand. The comparison predicate operand\r\n(immediate byte) specifies the type of comparison performed on each pair of packed values in the two source oper-\r\nands. The result of each comparison is a single mask bit result of 1 (comparison true) or 0 (comparison false).\r\nVPCMPW performs a comparison between pairs of signed word values.\r\nVPCMPUW performs a comparison between pairs of unsigned word values.\r\nThe first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a\r\nZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand (first operand) is a mask\r\nregister k1. Up to 32/16/8 comparisons are performed with results written to the destination operand under the\r\nwritemask k2.\r\nThe comparison predicate operand is an 8-bit immediate: bits 2:0 define the type of comparison to be performed.\r\nBits 3 through 7 of the immediate are reserved. Compiler can implement the pseudo-op mnemonic listed in Table\r\n5-10.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nCASE (COMPARISON PREDICATE) OF\r\n 0: OP <- EQ;\r\n 1: OP <- LT;\r\n 2: OP <- LE;\r\n 3: OP <- FALSE;\r\n 4: OP <- NEQ ;\r\n 5: OP <- NLT;\r\n 6: OP <- NLE;\r\n 7: OP <- TRUE;\r\nESAC;\r\n\r\nVPCMPW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k2[j] OR *no writemask*\r\n THEN\r\n ICMP <- SRC1[i+15:i] OP SRC2[i+15:i];\r\n IF CMP = TRUE\r\n THEN DEST[j] <- 1;\r\n ELSE DEST[j] <- 0; FI;\r\n ELSE DEST[j] = 0 ; zeroing-masking only\r\n FI;\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\nVPCMPUW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k2[j] OR *no writemask*\r\n THEN\r\n CMP <- SRC1[i+15:i] OP SRC2[i+15:i];\r\n IF CMP = TRUE\r\n THEN DEST[j] <- 1;\r\n ELSE DEST[j] <- 0; FI;\r\n ELSE DEST[j] = 0 ; zeroing-masking only\r\n FI;\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPCMPW __mmask32 _mm512_cmp_epi16_mask( __m512i a, __m512i b, int cmp);\r\nVPCMPW __mmask32 _mm512_mask_cmp_epi16_mask( __mmask32 m, __m512i a, __m512i b, int cmp);\r\nVPCMPW __mmask16 _mm256_cmp_epi16_mask( __m256i a, __m256i b, int cmp);\r\nVPCMPW __mmask16 _mm256_mask_cmp_epi16_mask( __mmask16 m, __m256i a, __m256i b, int cmp);\r\nVPCMPW __mmask8 _mm_cmp_epi16_mask( __m128i a, __m128i b, int cmp);\r\nVPCMPW __mmask8 _mm_mask_cmp_epi16_mask( __mmask8 m, __m128i a, __m128i b, int cmp);\r\nVPCMPW __mmask32 _mm512_cmp[eq|ge|gt|le|lt|neq]_epi16_mask( __m512i a, __m512i b);\r\nVPCMPW __mmask32 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epi16_mask( __mmask32 m, __m512i a, __m512i b);\r\nVPCMPW __mmask16 _mm256_cmp[eq|ge|gt|le|lt|neq]_epi16_mask( __m256i a, __m256i b);\r\nVPCMPW __mmask16 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epi16_mask( __mmask16 m, __m256i a, __m256i b);\r\nVPCMPW __mmask8 _mm_cmp[eq|ge|gt|le|lt|neq]_epi16_mask( __m128i a, __m128i b);\r\nVPCMPW __mmask8 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epi16_mask( __mmask8 m, __m128i a, __m128i b);\r\nVPCMPUW __mmask32 _mm512_cmp_epu16_mask( __m512i a, __m512i b, int cmp);\r\nVPCMPUW __mmask32 _mm512_mask_cmp_epu16_mask( __mmask32 m, __m512i a, __m512i b, int cmp);\r\nVPCMPUW __mmask16 _mm256_cmp_epu16_mask( __m256i a, __m256i b, int cmp);\r\nVPCMPUW __mmask16 _mm256_mask_cmp_epu16_mask( __mmask16 m, __m256i a, __m256i b, int cmp);\r\nVPCMPUW __mmask8 _mm_cmp_epu16_mask( __m128i a, __m128i b, int cmp);\r\nVPCMPUW __mmask8 _mm_mask_cmp_epu16_mask( __mmask8 m, __m128i a, __m128i b, int cmp);\r\nVPCMPUW __mmask32 _mm512_cmp[eq|ge|gt|le|lt|neq]_epu16_mask( __m512i a, __m512i b, int cmp);\r\nVPCMPUW __mmask32 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epu16_mask( __mmask32 m, __m512i a, __m512i b, int cmp);\r\nVPCMPUW __mmask16 _mm256_cmp[eq|ge|gt|le|lt|neq]_epu16_mask( __m256i a, __m256i b, int cmp);\r\nVPCMPUW __mmask16 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epu16_mask( __mmask16 m, __m256i a, __m256i b, int cmp);\r\nVPCMPUW __mmask8 _mm_cmp[eq|ge|gt|le|lt|neq]_epu16_mask( __m128i a, __m128i b, int cmp);\r\nVPCMPUW __mmask8 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epu16_mask( __mmask8 m, __m128i a, __m128i b, int cmp);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nEVEX-encoded instruction, see Exceptions Type E4.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPCMPW"
},
{
"description": "VPCOMPRESSD-Store Sparse Packed Doubleword Integer Values into Dense Memory/Register\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F38.W0 8B /r T1S V/V AVX512VL Compress packed doubleword integer values from\r\n VPCOMPRESSD xmm1/m128 {k1}{z}, xmm2 AVX512F xmm2 to xmm1/m128 using controlmask k1.\r\n EVEX.256.66.0F38.W0 8B /r T1S V/V AVX512VL Compress packed doubleword integer values from\r\n VPCOMPRESSD ymm1/m256 {k1}{z}, ymm2 AVX512F ymm2 to ymm1/m256 using controlmask k1.\r\n EVEX.512.66.0F38.W0 8B /r T1S V/V AVX512F Compress packed doubleword integer values from\r\n VPCOMPRESSD zmm1/m512 {k1}{z}, zmm2 zmm2 to zmm1/m512 using controlmask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\nDescription\r\nCompress (store) up to 16/8/4 doubleword integer values from the source operand (second operand) to the desti-\r\nnation operand (first operand). The source operand is a ZMM/YMM/XMM register, the destination operand can be a\r\nZMM/YMM/XMM register or a 512/256/128-bit memory location.\r\nThe opmask register k1 selects the active elements (partial vector or possibly non-contiguous if less than 16 active\r\nelements) from the source operand to compress into a contiguous vector. The contiguous vector is written to the\r\ndestination starting from the low element of the destination operand.\r\nMemory destination version: Only the contiguous vector is written to the destination memory location. EVEX.z\r\nmust be zero.\r\nRegister destination version: If the vector length of the contiguous vector is less than that of the input vector in the\r\nsource operand, the upper bits of the destination register are unmodified if EVEX.z is not set, otherwise the upper\r\nbits are zeroed.\r\nNote: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\nNote that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element\r\ninstead of the size of the full vector.\r\n\r\nOperation\r\nVPCOMPRESSD (EVEX encoded versions) store form\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nSIZE <- 32\r\nk<-0\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no controlmask*\r\n THEN\r\n DEST[k+SIZE-1:k]<- SRC[i+31:i]\r\n k <- k + SIZE\r\n FI;\r\nENDFOR;\r\n\r\n\r\n\r\n\r\n\r\nVPCOMPRESSD (EVEX encoded versions) reg-reg form\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nSIZE <- 32\r\nk<-0\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no controlmask*\r\n THEN\r\n DEST[k+SIZE-1:k]<- SRC[i+31:i]\r\n k <- k + SIZE\r\n FI;\r\nENDFOR\r\nIF *merging-masking*\r\n THEN *DEST[VL-1:k] remains unchanged*\r\n ELSE DEST[VL-1:k] <- 0\r\nFI\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPCOMPRESSD __m512i _mm512_mask_compress_epi32(__m512i s, __mmask16 c, __m512i a);\r\nVPCOMPRESSD __m512i _mm512_maskz_compress_epi32( __mmask16 c, __m512i a);\r\nVPCOMPRESSD void _mm512_mask_compressstoreu_epi32(void * a, __mmask16 c, __m512i s);\r\nVPCOMPRESSD __m256i _mm256_mask_compress_epi32(__m256i s, __mmask8 c, __m256i a);\r\nVPCOMPRESSD __m256i _mm256_maskz_compress_epi32( __mmask8 c, __m256i a);\r\nVPCOMPRESSD void _mm256_mask_compressstoreu_epi32(void * a, __mmask8 c, __m256i s);\r\nVPCOMPRESSD __m128i _mm_mask_compress_epi32(__m128i s, __mmask8 c, __m128i a);\r\nVPCOMPRESSD __m128i _mm_maskz_compress_epi32( __mmask8 c, __m128i a);\r\nVPCOMPRESSD void _mm_mask_compressstoreu_epi32(void * a, __mmask8 c, __m128i s);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nEVEX-encoded instruction, see Exceptions Type E4.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPCOMPRESSD"
},
{
"description": "VPCOMPRESSQ-Store Sparse Packed Quadword Integer Values into Dense Memory/Register\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F38.W1 8B /r T1S V/V AVX512VL Compress packed quadword integer values from\r\n VPCOMPRESSQ xmm1/m128 {k1}{z}, xmm2 AVX512F xmm2 to xmm1/m128 using controlmask k1.\r\n EVEX.256.66.0F38.W1 8B /r T1S V/V AVX512VL Compress packed quadword integer values from\r\n VPCOMPRESSQ ymm1/m256 {k1}{z}, ymm2 AVX512F ymm2 to ymm1/m256 using controlmask k1.\r\n EVEX.512.66.0F38.W1 8B /r T1S V/V AVX512F Compress packed quadword integer values from\r\n VPCOMPRESSQ zmm1/m512 {k1}{z}, zmm2 zmm2 to zmm1/m512 using controlmask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\nDescription\r\nCompress (stores) up to 8/4/2 quadword integer values from the source operand (second operand) to the destina-\r\ntion operand (first operand). The source operand is a ZMM/YMM/XMM register, the destination operand can be a\r\nZMM/YMM/XMM register or a 512/256/128-bit memory location.\r\nThe opmask register k1 selects the active elements (partial vector or possibly non-contiguous if less than 8 active\r\nelements) from the source operand to compress into a contiguous vector. The contiguous vector is written to the\r\ndestination starting from the low element of the destination operand.\r\nMemory destination version: Only the contiguous vector is written to the destination memory location. EVEX.z\r\nmust be zero.\r\nRegister destination version: If the vector length of the contiguous vector is less than that of the input vector in the\r\nsource operand, the upper bits of the destination register are unmodified if EVEX.z is not set, otherwise the upper\r\nbits are zeroed.\r\nNote: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\nNote that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element\r\ninstead of the size of the full vector.\r\n\r\nOperation\r\nVPCOMPRESSQ (EVEX encoded versions) store form\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nSIZE <- 64\r\nk<-0\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no controlmask*\r\n THEN\r\n DEST[k+SIZE-1:k]<- SRC[i+63:i]\r\n k <- k + SIZE\r\n FI;\r\nENFOR\r\n\r\n\r\n\r\n\r\n\r\nVPCOMPRESSQ (EVEX encoded versions) reg-reg form\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nSIZE <- 64\r\nk<-0\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no controlmask*\r\n THEN\r\n DEST[k+SIZE-1:k]<- SRC[i+63:i]\r\n k <- k + SIZE\r\n FI;\r\nENDFOR\r\nIF *merging-masking*\r\n THEN *DEST[VL-1:k] remains unchanged*\r\n ELSE DEST[VL-1:k] <- 0\r\nFI\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPCOMPRESSQ __m512i _mm512_mask_compress_epi64(__m512i s, __mmask8 c, __m512i a);\r\nVPCOMPRESSQ __m512i _mm512_maskz_compress_epi64( __mmask8 c, __m512i a);\r\nVPCOMPRESSQ void _mm512_mask_compressstoreu_epi64(void * a, __mmask8 c, __m512i s);\r\nVPCOMPRESSQ __m256i _mm256_mask_compress_epi64(__m256i s, __mmask8 c, __m256i a);\r\nVPCOMPRESSQ __m256i _mm256_maskz_compress_epi64( __mmask8 c, __m256i a);\r\nVPCOMPRESSQ void _mm256_mask_compressstoreu_epi64(void * a, __mmask8 c, __m256i s);\r\nVPCOMPRESSQ __m128i _mm_mask_compress_epi64(__m128i s, __mmask8 c, __m128i a);\r\nVPCOMPRESSQ __m128i _mm_maskz_compress_epi64( __mmask8 c, __m128i a);\r\nVPCOMPRESSQ void _mm_mask_compressstoreu_epi64(void * a, __mmask8 c, __m128i s);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nEVEX-encoded instruction, see Exceptions Type E4.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPCOMPRESSQ"
},
{
"description": "VPCONFLICTD/VPCONFLICTQ-Detect Conflicts Within a Vector of Packed Dword/Qword Values into Dense\r\nMemory/ Register\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F38.W0 C4 /r FV V/V AVX512VL Detect duplicate double-word values in\r\n VPCONFLICTD xmm1 {k1}{z}, AVX512CD xmm2/m128/m32bcst using writemask k1.\r\n xmm2/m128/m32bcst\r\n\r\n EVEX.256.66.0F38.W0 C4 /r FV V/V AVX512VL Detect duplicate double-word values in\r\n VPCONFLICTD ymm1 {k1}{z}, AVX512CD ymm2/m256/m32bcst using writemask k1.\r\n ymm2/m256/m32bcst\r\n\r\n EVEX.512.66.0F38.W0 C4 /r FV V/V AVX512CD Detect duplicate double-word values in\r\n VPCONFLICTD zmm1 {k1}{z}, zmm2/m512/m32bcst using writemask k1.\r\n zmm2/m512/m32bcst\r\n\r\n EVEX.128.66.0F38.W1 C4 /r FV V/V AVX512VL Detect duplicate quad-word values in\r\n VPCONFLICTQ xmm1 {k1}{z}, AVX512CD xmm2/m128/m64bcst using writemask k1.\r\n xmm2/m128/m64bcst\r\n\r\n EVEX.256.66.0F38.W1 C4 /r FV V/V AVX512VL Detect duplicate quad-word values in\r\n VPCONFLICTQ ymm1 {k1}{z}, AVX512CD ymm2/m256/m64bcst using writemask k1.\r\n ymm2/m256/m64bcst\r\n\r\n EVEX.512.66.0F38.W1 C4 /r FV V/V AVX512CD Detect duplicate quad-word values in\r\n VPCONFLICTQ zmm1 {k1}{z}, zmm2/m512/m64bcst using writemask k1.\r\n zmm2/m512/m64bcst\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nTest each dword/qword element of the source operand (the second operand) for equality with all other elements in\r\nthe source operand closer to the least significant element. Each element's comparison results form a bit vector,\r\nwhich is then zero extended and written to the destination according to the writemask.\r\nEVEX.512 encoded version: The source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector\r\nbroadcasted from a 32/64-bit memory location. The destination operand is a ZMM register, conditionally updated\r\nusing writemask k1.\r\nEVEX.256 encoded version: The source operand is a YMM register, a 256-bit memory location, or a 256-bit vector\r\nbroadcasted from a 32/64-bit memory location. The destination operand is a YMM register, conditionally updated\r\nusing writemask k1.\r\nEVEX.128 encoded version: The source operand is a XMM register, a 128-bit memory location, or a 128-bit vector\r\nbroadcasted from a 32/64-bit memory location. The destination operand is a XMM register, conditionally updated\r\nusing writemask k1.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVPCONFLICTD\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j*32\r\n IF MaskBit(j) OR *no writemask*THEN\r\n FOR k <- 0 TO j-1\r\n m <- k*32\r\n IF ((SRC[i+31:i] = SRC[m+31:m])) THEN\r\n DEST[i+k] <- 1\r\n ELSE\r\n DEST[i+k] <- 0\r\n FI\r\n ENDFOR\r\n DEST[i+31:i+j] <- 0\r\n ELSE\r\n IF *merging-masking* THEN\r\n *DEST[i+31:i] remains unchanged*\r\n ELSE\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPCONFLICTQ\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j*64\r\n IF MaskBit(j) OR *no writemask*THEN\r\n FOR k <- 0 TO j-1\r\n m <- k*64\r\n IF ((SRC[i+63:i] = SRC[m+63:m])) THEN\r\n DEST[i+k] <- 1\r\n ELSE\r\n DEST[i+k] <- 0\r\n FI\r\n ENDFOR\r\n DEST[i+63:i+j] <- 0\r\n ELSE\r\n IF *merging-masking* THEN\r\n *DEST[i+63:i] remains unchanged*\r\n ELSE\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n\r\nVPCONFLICTD __m512i _mm512_conflict_epi32( __m512i a);\r\nVPCONFLICTD __m512i _mm512_mask_conflict_epi32(__m512i s, __mmask16 m, __m512i a);\r\nVPCONFLICTD __m512i _mm512_maskz_conflict_epi32(__mmask16 m, __m512i a);\r\nVPCONFLICTQ __m512i _mm512_conflict_epi64( __m512i a);\r\nVPCONFLICTQ __m512i _mm512_mask_conflict_epi64(__m512i s, __mmask8 m, __m512i a);\r\nVPCONFLICTQ __m512i _mm512_maskz_conflict_epi64(__mmask8 m, __m512i a);\r\nVPCONFLICTD __m256i _mm256_conflict_epi32( __m256i a);\r\nVPCONFLICTD __m256i _mm256_mask_conflict_epi32(__m256i s, __mmask8 m, __m256i a);\r\nVPCONFLICTD __m256i _mm256_maskz_conflict_epi32(__mmask8 m, __m256i a);\r\nVPCONFLICTQ __m256i _mm256_conflict_epi64( __m256i a);\r\nVPCONFLICTQ __m256i _mm256_mask_conflict_epi64(__m256i s, __mmask8 m, __m256i a);\r\nVPCONFLICTQ __m256i _mm256_maskz_conflict_epi64(__mmask8 m, __m256i a);\r\nVPCONFLICTD __m128i _mm_conflict_epi32( __m128i a);\r\nVPCONFLICTD __m128i _mm_mask_conflict_epi32(__m128i s, __mmask8 m, __m128i a);\r\nVPCONFLICTD __m128i _mm_maskz_conflict_epi32(__mmask8 m, __m128i a);\r\nVPCONFLICTQ __m128i _mm_conflict_epi64( __m128i a);\r\nVPCONFLICTQ __m128i _mm_mask_conflict_epi64(__m128i s, __mmask8 m, __m128i a);\r\nVPCONFLICTQ __m128i _mm_maskz_conflict_epi64(__mmask8 m, __m128i a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPCONFLICTD"
},
{
"description": "-R:VPCONFLICTD",
"mnem": "VPCONFLICTQ"
},
{
"description": "VPERM2F128 - Permute Floating-Point Values\r\n Opcode/ Op/ 64/32 bit CPUID Description\r\n Instruction En Mode Feature\r\n Support Flag\r\n VEX.NDS.256.66.0F3A.W0 06 /r ib RVMI V/V AVX Permute 128-bit floating-point fields in ymm2\r\n VPERM2F128 ymm1, ymm2, ymm3/m256, imm8 and ymm3/mem using controls from imm8 and\r\n store result in ymm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVMI ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8\r\n\r\n\r\nDescription\r\nPermute 128 bit floating-point-containing fields from the first source operand (second operand) and second source\r\noperand (third operand) using bits in the 8-bit immediate and store results in the destination operand (first\r\noperand). The first source operand is a YMM register, the second source operand is a YMM register or a 256-bit\r\nmemory location, and the destination operand is a YMM register.\r\n\r\n\r\n\r\n\r\n SRC2 Y1 Y0\r\n\r\n\r\n\r\n\r\n SRC1 X1 X0\r\n\r\n\r\n\r\n\r\n DEST X0, X1, Y0, or Y1 X0, X1, Y0, or Y1\r\n\r\n\r\n\r\n\r\n Figure 5-21. VPERM2F128 Operation\r\n\r\nImm8[1:0] select the source for the first destination 128-bit field, imm8[5:4] select the source for the second\r\ndestination field. If imm8[3] is set, the low 128-bit field is zeroed. If imm8[7] is set, the high 128-bit field is zeroed.\r\nVEX.L must be 1, otherwise the instruction will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVPERM2F128\r\nCASE IMM8[1:0] of\r\n0: DEST[127:0] <- SRC1[127:0]\r\n1: DEST[127:0] <- SRC1[255:128]\r\n2: DEST[127:0] <- SRC2[127:0]\r\n3: DEST[127:0] <- SRC2[255:128]\r\nESAC\r\n\r\nCASE IMM8[5:4] of\r\n0: DEST[255:128] <- SRC1[127:0]\r\n1: DEST[255:128] <- SRC1[255:128]\r\n2: DEST[255:128] <- SRC2[127:0]\r\n3: DEST[255:128] <- SRC2[255:128]\r\nESAC\r\nIF (imm8[3])\r\nDEST[127:0] <- 0\r\nFI\r\n\r\nIF (imm8[7])\r\nDEST[VLMAX-1:128] <- 0\r\nFI\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPERM2F128: __m256 _mm256_permute2f128_ps (__m256 a, __m256 b, int control)\r\nVPERM2F128: __m256d _mm256_permute2f128_pd (__m256d a, __m256d b, int control)\r\nVPERM2F128: __m256i _mm256_permute2f128_si256 (__m256i a, __m256i b, int control)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 6; additionally\r\n#UD If VEX.L = 0\r\n If VEX.W = 1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPERM2F128"
},
{
"description": "VPERM2I128 - Permute Integer Values\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En -bit Feature\r\n Mode Flag\r\n VEX.NDS.256.66.0F3A.W0 46 /r ib RVMI V/V AVX2 Permute 128-bit integer data in ymm2 and\r\n VPERM2I128 ymm1, ymm2, ymm3/m256, imm8 ymm3/mem using controls from imm8 and\r\n store result in ymm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVMI ModRM:reg (w) VEX.vvvv ModRM:r/m (r) Imm8\r\n\r\nDescription\r\nPermute 128 bit integer data from the first source operand (second operand) and second source operand (third\r\noperand) using bits in the 8-bit immediate and store results in the destination operand (first operand). The first\r\nsource operand is a YMM register, the second source operand is a YMM register or a 256-bit memory location, and\r\nthe destination operand is a YMM register.\r\n\r\n\r\n\r\n\r\n SRC2 Y1 Y0\r\n\r\n\r\n\r\n\r\n SRC1 X1 X0\r\n\r\n\r\n\r\n\r\n DEST X0, X1, Y0, or Y1 X0, X1, Y0, or Y1\r\n\r\n\r\n\r\n\r\n Figure 5-22. VPERM2I128 Operation\r\n\r\nImm8[1:0] select the source for the first destination 128-bit field, imm8[5:4] select the source for the second\r\ndestination field. If imm8[3] is set, the low 128-bit field is zeroed. If imm8[7] is set, the high 128-bit field is zeroed.\r\nVEX.L must be 1, otherwise the instruction will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVPERM2I128\r\nCASE IMM8[1:0] of\r\n0: DEST[127:0] <- SRC1[127:0]\r\n1: DEST[127:0] <- SRC1[255:128]\r\n2: DEST[127:0] <- SRC2[127:0]\r\n3: DEST[127:0] <- SRC2[255:128]\r\nESAC\r\nCASE IMM8[5:4] of\r\n0: DEST[255:128] <- SRC1[127:0]\r\n1: DEST[255:128] <- SRC1[255:128]\r\n2: DEST[255:128] <- SRC2[127:0]\r\n3: DEST[255:128] <- SRC2[255:128]\r\nESAC\r\nIF (imm8[3])\r\nDEST[127:0] <- 0\r\nFI\r\n\r\nIF (imm8[7])\r\nDEST[255:128] <- 0\r\nFI\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPERM2I128: __m256i _mm256_permute2x128_si256 (__m256i a, __m256i b, int control)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 6; additionally\r\n#UD If VEX.L = 0,\r\n If VEX.W = 1.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPERM2I128"
},
{
"description": "VPERMD/VPERMW-Permute Packed Doublewords/Words Elements\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.NDS.256.66.0F38.W0 36 /r RVM V/V AVX2 Permute doublewords in ymm3/m256 using indices in\r\n VPERMD ymm1, ymm2, ymm3/m256 ymm2 and store the result in ymm1.\r\n EVEX.NDS.256.66.0F38.W0 36 /r FV V/V AVX512VL Permute doublewords in ymm3/m256/m32bcst using\r\n VPERMD ymm1 {k1}{z}, ymm2, AVX512F indexes in ymm2 and store the result in ymm1 using\r\n ymm3/m256/m32bcst writemask k1.\r\n EVEX.NDS.512.66.0F38.W0 36 /r FV V/V AVX512F Permute doublewords in zmm3/m512/m32bcst using\r\n VPERMD zmm1 {k1}{z}, zmm2, indices in zmm2 and store the result in zmm1 using\r\n zmm3/m512/m32bcst writemask k1.\r\n EVEX.NDS.128.66.0F38.W1 8D /r FVM V/V AVX512VL Permute word integers in xmm3/m128 using indexes\r\n AVX512BW in xmm2 and store the result in xmm1 using writemask\r\n VPERMW xmm1 {k1}{z}, xmm2, k1.\r\n xmm3/m128\r\n EVEX.NDS.256.66.0F38.W1 8D /r FVM V/V AVX512VL Permute word integers in ymm3/m256 using indexes\r\n AVX512BW in ymm2 and store the result in ymm1 using writemask\r\n VPERMW ymm1 {k1}{z}, ymm2, k1.\r\n ymm3/m256\r\n EVEX.NDS.512.66.0F38.W1 8D /r FVM V/V AVX512BW Permute word integers in zmm3/m512 using indexes\r\n VPERMW zmm1 {k1}{z}, zmm2, in zmm2 and store the result in zmm1 using writemask\r\n zmm3/m512 k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n FVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nCopies doublewords (or words) from the second source operand (the third operand) to the destination operand (the\r\nfirst operand) according to the indices in the first source operand (the second operand). Note that this instruction\r\npermits a doubleword (word) in the source operand to be copied to more than one location in the destination\r\noperand.\r\nVEX.256 encoded VPERMD: The first and second operands are YMM registers, the third operand can be a YMM\r\nregister or memory location. Bits (MAX_VL-1:256) of the corresponding destination register are zeroed.\r\nEVEX encoded VPERMD: The first and second operands are ZMM/YMM registers, the third operand can be a\r\nZMM/YMM register, a 512/256-bit memory location or a 512/256-bit vector broadcasted from a 32-bit memory\r\nlocation. The elements in the destination are updated using the writemask k1.\r\nVPERMW: first and second operands are ZMM/YMM/XMM registers, the third operand can be a ZMM/YMM/XMM\r\nregister, or a 512/256/128-bit memory location. The destination is updated using the writemask k1.\r\nEVEX.128 encoded versions: Bits (MAX_VL-1:128) of the corresponding ZMM register are zeroed.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVPERMD (EVEX encoded versions)\r\n(KL, VL) = (8, 256), (16, 512)\r\nIF VL = 256 THEN n <- 2; FI;\r\nIF VL = 512 THEN n <- 3; FI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n id <- 32*SRC1[i+n:i]\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN DEST[i+31:i] <- SRC2[31:0];\r\n ELSE DEST[i+31:i] <- SRC2[id+31:id];\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPERMD (VEX.256 encoded version)\r\nDEST[31:0] <- (SRC2[255:0] >> (SRC1[2:0] * 32))[31:0];\r\nDEST[63:32] <- (SRC2[255:0] >> (SRC1[34:32] * 32))[31:0];\r\nDEST[95:64] <- (SRC2[255:0] >> (SRC1[66:64] * 32))[31:0];\r\nDEST[127:96] <- (SRC2[255:0] >> (SRC1[98:96] * 32))[31:0];\r\nDEST[159:128] <- (SRC2[255:0] >> (SRC1[130:128] * 32))[31:0];\r\nDEST[191:160] <- (SRC2[255:0] >> (SRC1[162:160] * 32))[31:0];\r\nDEST[223:192] <- (SRC2[255:0] >> (SRC1[194:192] * 32))[31:0];\r\nDEST[255:224] <- (SRC2[255:0] >> (SRC1[226:224] * 32))[31:0];\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVPERMW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nIF VL = 128 THEN n <- 2; FI;\r\nIF VL = 256 THEN n <- 3; FI;\r\nIF VL = 512 THEN n <- 4; FI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n id <- 16*SRC1[i+n:i]\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- SRC2[id+15:id]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPERMD __m512i _mm512_permutexvar_epi32( __m512i idx, __m512i a);\r\nVPERMD __m512i _mm512_mask_permutexvar_epi32(__m512i s, __mmask16 k, __m512i idx, __m512i a);\r\nVPERMD __m512i _mm512_maskz_permutexvar_epi32( __mmask16 k, __m512i idx, __m512i a);\r\nVPERMD __m256i _mm256_permutexvar_epi32( __m256i idx, __m256i a);\r\nVPERMD __m256i _mm256_mask_permutexvar_epi32(__m256i s, __mmask8 k, __m256i idx, __m256i a);\r\nVPERMD __m256i _mm256_maskz_permutexvar_epi32( __mmask8 k, __m256i idx, __m256i a);\r\nVPERMW __m512i _mm512_permutexvar_epi16( __m512i idx, __m512i a);\r\nVPERMW __m512i _mm512_mask_permutexvar_epi16(__m512i s, __mmask32 k, __m512i idx, __m512i a);\r\nVPERMW __m512i _mm512_maskz_permutexvar_epi16( __mmask32 k, __m512i idx, __m512i a);\r\nVPERMW __m256i _mm256_permutexvar_epi16( __m256i idx, __m256i a);\r\nVPERMW __m256i _mm256_mask_permutexvar_epi16(__m256i s, __mmask16 k, __m256i idx, __m256i a);\r\nVPERMW __m256i _mm256_maskz_permutexvar_epi16( __mmask16 k, __m256i idx, __m256i a);\r\nVPERMW __m128i _mm_permutexvar_epi16( __m128i idx, __m128i a);\r\nVPERMW __m128i _mm_mask_permutexvar_epi16(__m128i s, __mmask8 k, __m128i idx, __m128i a);\r\nVPERMW __m128i _mm_maskz_permutexvar_epi16( __mmask8 k, __m128i idx, __m128i a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded VPERMD, see Exceptions Type E4NF.\r\nEVEX-encoded VPERMW, see Exceptions Type E4NF.nb.\r\n#UD If VEX.L = 0.\r\n If EVEX.L'L = 0 for VPERMD.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPERMD"
},
{
"description": "-R:VPERMI2W",
"mnem": "VPERMI2D"
},
{
"description": "-R:VPERMI2W",
"mnem": "VPERMI2PD"
},
{
"description": "-R:VPERMI2W",
"mnem": "VPERMI2PS"
},
{
"description": "-R:VPERMI2W",
"mnem": "VPERMI2Q"
},
{
"description": "VPERMI2W/VPERMI2D/VPERMI2Q/VPERMI2PS/VPERMI2PD-Full Permute From Two Tables Overwriting the Index\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.DDS.128.66.0F38.W1 75 /r FVM V/V AVX512VL Permute word integers from two tables in\r\n VPERMI2W xmm1 {k1}{z}, xmm2, AVX512BW xmm3/m128 and xmm2 using indexes in xmm1 and\r\n xmm3/m128 store the result in xmm1 using writemask k1.\r\n EVEX.DDS.256.66.0F38.W1 75 /r FVM V/V AVX512VL Permute word integers from two tables in\r\n VPERMI2W ymm1 {k1}{z}, ymm2, AVX512BW ymm3/m256 and ymm2 using indexes in ymm1 and\r\n ymm3/m256 store the result in ymm1 using writemask k1.\r\n EVEX.DDS.512.66.0F38.W1 75 /r FVM V/V AVX512BW Permute word integers from two tables in\r\n VPERMI2W zmm1 {k1}{z}, zmm2, zmm3/m512 and zmm2 using indexes in zmm1 and\r\n zmm3/m512 store the result in zmm1 using writemask k1.\r\n EVEX.DDS.128.66.0F38.W0 76 /r FV V/V AVX512VL Permute double-words from two tables in\r\n VPERMI2D xmm1 {k1}{z}, xmm2, AVX512F xmm3/m128/m32bcst and xmm2 using indexes in\r\n xmm3/m128/m32bcst xmm1 and store the result in xmm1 using writemask\r\n k1.\r\n EVEX.DDS.256.66.0F38.W0 76 /r FV V/V AVX512VL Permute double-words from two tables in\r\n VPERMI2D ymm1 {k1}{z}, ymm2, AVX512F ymm3/m256/m32bcst and ymm2 using indexes in\r\n ymm3/m256/m32bcst ymm1 and store the result in ymm1 using writemask\r\n k1.\r\n EVEX.DDS.512.66.0F38.W0 76 /r FV V/V AVX512F Permute double-words from two tables in\r\n VPERMI2D zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst and zmm2 using indices in\r\n zmm3/m512/m32bcst zmm1 and store the result in zmm1 using writemask\r\n k1.\r\n EVEX.DDS.128.66.0F38.W1 76 /r FV V/V AVX512VL Permute quad-words from two tables in\r\n VPERMI2Q xmm1 {k1}{z}, xmm2, AVX512F xmm3/m128/m64bcst and xmm2 using indexes in\r\n xmm3/m128/m64bcst xmm1 and store the result in xmm1 using writemask\r\n k1.\r\n EVEX.DDS.256.66.0F38.W1 76 /r FV V/V AVX512VL Permute quad-words from two tables in\r\n VPERMI2Q ymm1 {k1}{z}, ymm2, AVX512F ymm3/m256/m64bcst and ymm2 using indexes in\r\n ymm3/m256/m64bcst ymm1 and store the result in ymm1 using writemask\r\n k1.\r\n EVEX.DDS.512.66.0F38.W1 76 /r FV V/V AVX512F Permute quad-words from two tables in\r\n VPERMI2Q zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst and zmm2 using indices in\r\n zmm3/m512/m64bcst zmm1 and store the result in zmm1 using writemask\r\n k1.\r\n EVEX.DDS.128.66.0F38.W0 77 /r FV V/V AVX512VL Permute single-precision FP values from two tables in\r\n VPERMI2PS xmm1 {k1}{z}, xmm2, AVX512F xmm3/m128/m32bcst and xmm2 using indexes in\r\n xmm3/m128/m32bcst xmm1 and store the result in xmm1 using writemask\r\n k1.\r\n EVEX.DDS.256.66.0F38.W0 77 /r FV V/V AVX512VL Permute single-precision FP values from two tables in\r\n VPERMI2PS ymm1 {k1}{z}, ymm2, AVX512F ymm3/m256/m32bcst and ymm2 using indexes in\r\n ymm3/m256/m32bcst ymm1 and store the result in ymm1 using writemask\r\n k1.\r\n EVEX.DDS.512.66.0F38.W0 77 /r FV V/V AVX512F Permute single-precision FP values from two tables in\r\n VPERMI2PS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst and zmm2 using indices in\r\n zmm3/m512/m32bcst zmm1 and store the result in zmm1 using writemask\r\n k1.\r\n\r\n\r\n\r\n\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.DDS.128.66.0F38.W1 77 /r FV V/V AVX512VL Permute double-precision FP values from two tables in\r\n VPERMI2PD xmm1 {k1}{z}, xmm2, AVX512F xmm3/m128/m64bcst and xmm2 using indexes in\r\n xmm3/m128/m64bcst xmm1 and store the result in xmm1 using writemask\r\n k1.\r\n EVEX.DDS.256.66.0F38.W1 77 /r FV V/V AVX512VL Permute double-precision FP values from two tables in\r\n VPERMI2PD ymm1 {k1}{z}, ymm2, AVX512F ymm3/m256/m64bcst and ymm2 using indexes in\r\n ymm3/m256/m64bcst ymm1 and store the result in ymm1 using writemask\r\n k1.\r\n EVEX.DDS.512.66.0F38.W1 77 /r FV V/V AVX512F Permute double-precision FP values from two tables in\r\n VPERMI2PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst and zmm2 using indices in\r\n zmm3/m512/m64bcst zmm1 and store the result in zmm1 using writemask\r\n k1.\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FVM ModRM:reg (r,w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPermutes 16-bit/32-bit/64-bit values in the second operand (the first source operand) and the third operand (the\r\nsecond source operand) using indices in the first operand to select elements from the second and third operands.\r\nThe selected elements are written to the destination operand (the first operand) according to the writemask k1.\r\nThe first and second operands are ZMM/YMM/XMM registers. The first operand contains input indices to select\r\nelements from the two input tables in the 2nd and 3rd operands. The first operand is also the destination of the\r\nresult.\r\nD/Q/PS/PD element versions: The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit\r\nmemory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. Broadcast from the\r\nlow 32/64-bit memory location is performed if EVEX.b and the id bit for table selection are set (selecting table_2).\r\nDword/PS versions: The id bit for table selection is bit 4/3/2, depending on VL=512, 256, 128. Bits\r\n[3:0]/[2:0]/[1:0] of each element in the input index vector select an element within the two source operands, If\r\nthe id bit is 0, table_1 (the first source) is selected; otherwise the second source operand is selected.\r\nQword/PD versions: The id bit for table selection is bit 3/2/1, and bits [2:0]/[1:0] /bit 0 selects element within each\r\ninput table.\r\nWord element versions: The second source operand can be a ZMM/YMM/XMM register, or a 512/256/128-bit\r\nmemory location. The id bit for table selection is bit 5/4/3, and bits [4:0]/[3:0]/[2:0] selects element within each\r\ninput table.\r\nNote that these instructions permit a 16-bit/32-bit/64-bit value in the source operands to be copied to more than\r\none location in the destination operand. Note also that in this case, the same table can be reused for example for a\r\nsecond iteration, while the index elements are overwritten.\r\nBits (MAX_VL-1:256/128) of the destination are zeroed for VL=256,128.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVPERMI2W (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nIF VL = 128\r\n id <- 2\r\nFI;\r\nIF VL = 256\r\n id <- 3\r\nFI;\r\nIF VL = 512\r\n id <- 4\r\nFI;\r\nTMP_DEST<- DEST\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n off <- 16*TMP_DEST[i+id:i]\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n DEST[i+15:i]=TMP_DEST[i+id+1] ? SRC2[off+15:off]\r\n : SRC1[off+15:off]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPERMI2D/VPERMI2PS (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF VL = 128\r\n id <- 1\r\nFI;\r\nIF VL = 256\r\n id <- 2\r\nFI;\r\nIF VL = 512\r\n id <- 3\r\nFI;\r\nTMP_DEST<- DEST\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n off <- 32*TMP_DEST[i+id:i]\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN\r\n DEST[i+31:i] <- TMP_DEST[i+id+1] ? SRC2[31:0]\r\n : SRC1[off+31:off]\r\n ELSE\r\n DEST[i+31:i] <- TMP_DEST[i+id+1] ? SRC2[off+31:off]\r\n : SRC1[off+31:off]\r\n\r\n\r\n\r\n FI\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPERMI2Q/VPERMI2PD (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8 512)\r\nIF VL = 128\r\n id <- 0\r\nFI;\r\nIF VL = 256\r\n id <- 1\r\nFI;\r\nIF VL = 512\r\n id <- 2\r\nFI;\r\nTMP_DEST<- DEST\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n off <- 64*TMP_DEST[i+id:i]\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN\r\n DEST[i+63:i] <- TMP_DEST[i+id+1] ? SRC2[63:0]\r\n : SRC1[off+63:off]\r\n ELSE\r\n DEST[i+63:i] <- TMP_DEST[i+id+1] ? SRC2[off+63:off]\r\n : SRC1[off+63:off]\r\n FI\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n\r\nVPERMI2D __m512i _mm512_permutex2var_epi32(__m512i a, __m512i idx, __m512i b);\r\nVPERMI2D __m512i _mm512_mask_permutex2var_epi32(__m512i a, __mmask16 k, __m512i idx, __m512i b);\r\nVPERMI2D __m512i _mm512_mask2_permutex2var_epi32(__m512i a, __m512i idx, __mmask16 k, __m512i b);\r\nVPERMI2D __m512i _mm512_maskz_permutex2var_epi32(__mmask16 k, __m512i a, __m512i idx, __m512i b);\r\nVPERMI __m256i _mm256_permutex2var_epi32(__m256i a, __m256i idx, __m256i b);\r\nVPERMI2D __m256i _mm256_mask_permutex2var_epi32(__m256i a, __mmask8 k, __m256i idx, __m256i b);\r\nVPERMI2D __m256i _mm256_mask2_permutex2var_epi32(__m256i a, __m256i idx, __mmask8 k, __m256i b);\r\nVPERMI2D __m256i _mm256_maskz_permutex2var_epi32(__mmask8 k, __m256i a, __m256i idx, __m256i b);\r\nVPERMI2D __m128i _mm_permutex2var_epi32(__m128i a, __m128i idx, __m128i b);\r\nVPERMI2D __m128i _mm_mask_permutex2var_epi32(__m128i a, __mmask8 k, __m128i idx, __m128i b);\r\nVPERMI2D __m128i _mm_mask2_permutex2var_epi32(__m128i a, __m128i idx, __mmask8 k, __m128i b);\r\nVPERMI2D __m128i _mm_maskz_permutex2var_epi32(__mmask8 k, __m128i a, __m128i idx, __m128i b);\r\nVPERMI2PD __m512d _mm512_permutex2var_pd(__m512d a, __m512i idx, __m512d b);\r\nVPERMI2PD __m512d _mm512_mask_permutex2var_pd(__m512d a, __mmask8 k, __m512i idx, __m512d b);\r\nVPERMI2PD __m512d _mm512_mask2_permutex2var_pd(__m512d a, __m512i idx, __mmask8 k, __m512d b);\r\nVPERMI2PD __m512d _mm512_maskz_permutex2var_pd(__mmask8 k, __m512d a, __m512i idx, __m512d b);\r\nVPERMI2PD __m256d _mm256_permutex2var_pd(__m256d a, __m256i idx, __m256d b);\r\nVPERMI2PD __m256d _mm256_mask_permutex2var_pd(__m256d a, __mmask8 k, __m256i idx, __m256d b);\r\nVPERMI2PD __m256d _mm256_mask2_permutex2var_pd(__m256d a, __m256i idx, __mmask8 k, __m256d b);\r\nVPERMI2PD __m256d _mm256_maskz_permutex2var_pd(__mmask8 k, __m256d a, __m256i idx, __m256d b);\r\nVPERMI2PD __m128d _mm_permutex2var_pd(__m128d a, __m128i idx, __m128d b);\r\nVPERMI2PD __m128d _mm_mask_permutex2var_pd(__m128d a, __mmask8 k, __m128i idx, __m128d b);\r\nVPERMI2PD __m128d _mm_mask2_permutex2var_pd(__m128d a, __m128i idx, __mmask8 k, __m128d b);\r\nVPERMI2PD __m128d _mm_maskz_permutex2var_pd(__mmask8 k, __m128d a, __m128i idx, __m128d b);\r\nVPERMI2PS __m512 _mm512_permutex2var_ps(__m512 a, __m512i idx, __m512 b);\r\nVPERMI2PS __m512 _mm512_mask_permutex2var_ps(__m512 a, __mmask16 k, __m512i idx, __m512 b);\r\nVPERMI2PS __m512 _mm512_mask2_permutex2var_ps(__m512 a, __m512i idx, __mmask16 k, __m512 b);\r\nVPERMI2PS __m512 _mm512_maskz_permutex2var_ps(__mmask16 k, __m512 a, __m512i idx, __m512 b);\r\nVPERMI2PS __m256 _mm256_permutex2var_ps(__m256 a, __m256i idx, __m256 b);\r\nVPERMI2PS __m256 _mm256_mask_permutex2var_ps(__m256 a, __mmask8 k, __m256i idx, __m256 b);\r\nVPERMI2PS __m256 _mm256_mask2_permutex2var_ps(__m256 a, __m256i idx, __mmask8 k, __m256 b);\r\nVPERMI2PS __m256 _mm256_maskz_permutex2var_ps(__mmask8 k, __m256 a, __m256i idx, __m256 b);\r\nVPERMI2PS __m128 _mm_permutex2var_ps(__m128 a, __m128i idx, __m128 b);\r\nVPERMI2PS __m128 _mm_mask_permutex2var_ps(__m128 a, __mmask8 k, __m128i idx, __m128 b);\r\nVPERMI2PS __m128 _mm_mask2_permutex2var_ps(__m128 a, __m128i idx, __mmask8 k, __m128 b);\r\nVPERMI2PS __m128 _mm_maskz_permutex2var_ps(__mmask8 k, __m128 a, __m128i idx, __m128 b);\r\nVPERMI2Q __m512i _mm512_permutex2var_epi64(__m512i a, __m512i idx, __m512i b);\r\nVPERMI2Q __m512i _mm512_mask_permutex2var_epi64(__m512i a, __mmask8 k, __m512i idx, __m512i b);\r\nVPERMI2Q __m512i _mm512_mask2_permutex2var_epi64(__m512i a, __m512i idx, __mmask8 k, __m512i b);\r\nVPERMI2Q __m512i _mm512_maskz_permutex2var_epi64(__mmask8 k, __m512i a, __m512i idx, __m512i b);\r\nVPERMI2Q __m256i _mm256_permutex2var_epi64(__m256i a, __m256i idx, __m256i b);\r\nVPERMI2Q __m256i _mm256_mask_permutex2var_epi64(__m256i a, __mmask8 k, __m256i idx, __m256i b);\r\nVPERMI2Q __m256i _mm256_mask2_permutex2var_epi64(__m256i a, __m256i idx, __mmask8 k, __m256i b);\r\nVPERMI2Q __m256i _mm256_maskz_permutex2var_epi64(__mmask8 k, __m256i a, __m256i idx, __m256i b);\r\nVPERMI2Q __m128i _mm_permutex2var_epi64(__m128i a, __m128i idx, __m128i b);\r\nVPERMI2Q __m128i _mm_mask_permutex2var_epi64(__m128i a, __mmask8 k, __m128i idx, __m128i b);\r\nVPERMI2Q __m128i _mm_mask2_permutex2var_epi64(__m128i a, __m128i idx, __mmask8 k, __m128i b);\r\nVPERMI2Q __m128i _mm_maskz_permutex2var_epi64(__mmask8 k, __m128i a, __m128i idx, __m128i b);\r\n\r\n\r\nVPERMI2W __m512i _mm512_permutex2var_epi16(__m512i a, __m512i idx, __m512i b);\r\nVPERMI2W __m512i _mm512_mask_permutex2var_epi16(__m512i a, __mmask32 k, __m512i idx, __m512i b);\r\nVPERMI2W __m512i _mm512_mask2_permutex2var_epi16(__m512i a, __m512i idx, __mmask32 k, __m512i b);\r\nVPERMI2W __m512i _mm512_maskz_permutex2var_epi16(__mmask32 k, __m512i a, __m512i idx, __m512i b);\r\nVPERMI2W __m256i _mm256_permutex2var_epi16(__m256i a, __m256i idx, __m256i b);\r\nVPERMI2W __m256i _mm256_mask_permutex2var_epi16(__m256i a, __mmask16 k, __m256i idx, __m256i b);\r\nVPERMI2W __m256i _mm256_mask2_permutex2var_epi16(__m256i a, __m256i idx, __mmask16 k, __m256i b);\r\nVPERMI2W __m256i _mm256_maskz_permutex2var_epi16(__mmask16 k, __m256i a, __m256i idx, __m256i b);\r\nVPERMI2W __m128i _mm_permutex2var_epi16(__m128i a, __m128i idx, __m128i b);\r\nVPERMI2W __m128i _mm_mask_permutex2var_epi16(__m128i a, __mmask8 k, __m128i idx, __m128i b);\r\nVPERMI2W __m128i _mm_mask2_permutex2var_epi16(__m128i a, __m128i idx, __mmask8 k, __m128i b);\r\nVPERMI2W __m128i _mm_maskz_permutex2var_epi16(__mmask8 k, __m128i a, __m128i idx, __m128i b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nVPERMI2D/Q/PS/PD: See Exceptions Type E4NF.\r\nVPERMI2W: See Exceptions Type E4NF.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPERMI2W"
},
{
"description": "VPERMILPD-Permute In-Lane of Pairs of Double-Precision Floating-Point Values\r\n Opcode/ Op / En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n VEX.NDS.128.66.0F38.W0 0D /r RVM V/V AVX Permute double-precision floating-point values in\r\n VPERMILPD xmm1, xmm2, xmm3/m128 xmm2 using controls from xmm3/m128 and store\r\n result in xmm1.\r\n VEX.NDS.256.66.0F38.W0 0D /r RVM V/V AVX Permute double-precision floating-point values in\r\n VPERMILPD ymm1, ymm2, ymm3/m256 ymm2 using controls from ymm3/m256 and store\r\n result in ymm1.\r\n EVEX.NDS.128.66.0F38.W1 0D /r FV-RVM V/V AVX512VL Permute double-precision floating-point values in\r\n VPERMILPD xmm1 {k1}{z}, xmm2, AVX512F xmm2 using control from xmm3/m128/m64bcst\r\n xmm3/m128/m64bcst and store the result in xmm1 using writemask k1.\r\n EVEX.NDS.256.66.0F38.W1 0D /r FV-RVM V/V AVX512VL Permute double-precision floating-point values in\r\n VPERMILPD ymm1 {k1}{z}, ymm2, AVX512F ymm2 using control from ymm3/m256/m64bcst\r\n ymm3/m256/m64bcst and store the result in ymm1 using writemask k1.\r\n EVEX.NDS.512.66.0F38.W1 0D /r FV-RVM V/V AVX512F Permute double-precision floating-point values in\r\n VPERMILPD zmm1 {k1}{z}, zmm2, zmm2 using control from zmm3/m512/m64bcst\r\n zmm3/m512/m64bcst and store the result in zmm1 using writemask k1.\r\n VEX.128.66.0F3A.W0 05 /r ib RM V/V AVX Permute double-precision floating-point values in\r\n VPERMILPD xmm1, xmm2/m128, imm8 xmm2/m128 using controls from imm8.\r\n VEX.256.66.0F3A.W0 05 /r ib RM V/V AVX Permute double-precision floating-point values in\r\n VPERMILPD ymm1, ymm2/m256, imm8 ymm2/m256 using controls from imm8.\r\n EVEX.128.66.0F3A.W1 05 /r ib FV-RM V/V AVX512VL Permute double-precision floating-point values in\r\n VPERMILPD xmm1 {k1}{z}, AVX512F xmm2/m128/m64bcst using controls from imm8\r\n xmm2/m128/m64bcst, imm8 and store the result in xmm1 using writemask k1.\r\n EVEX.256.66.0F3A.W1 05 /r ib FV-RM V/V AVX512VL Permute double-precision floating-point values in\r\n VPERMILPD ymm1 {k1}{z}, AVX512F ymm2/m256/m64bcst using controls from imm8\r\n ymm2/m256/m64bcst, imm8 and store the result in ymm1 using writemask k1.\r\n EVEX.512.66.0F3A.W1 05 /r ib FV-RM V/V AVX512F Permute double-precision floating-point values in\r\n VPERMILPD zmm1 {k1}{z}, zmm2/m512/m64bcst using controls from imm8\r\n zmm2/m512/m64bcst, imm8 and store the result in zmm1 using writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n FV-RVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n FV-RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\n\r\n\r\n\r\n\r\nDescription\r\n(variable control version)\r\nPermute pairs of double-precision floating-point values in the first source operand (second operand), each using a\r\n1-bit control field residing in the corresponding quadword element of the second source operand (third operand).\r\nPermuted results are stored in the destination operand (first operand).\r\nThe control bits are located at bit 0 of each quadword element (see Figure 5-24). Each control determines which of\r\nthe source element in an input pair is selected for the destination element. Each pair of source elements must lie in\r\nthe same 128-bit region as the destination.\r\nEVEX version: The second source operand (third operand) is a ZMM/YMM/XMM register, a 512/256/128-bit\r\nmemory location or a 512/256/128-bit vector broadcasted from a 64-bit memory location. Permuted results are\r\nwritten to the destination under the writemask.\r\n\r\n\r\n\r\n\r\n SRC1 X3 X2 X1 X0\r\n\r\n\r\n\r\n\r\n DEST X2..X3 X2..X3 X0..X1 X0..X1\r\n\r\n\r\n\r\n Figure 5-23. VPERMILPD Operation\r\n\r\n\r\nVEX.256 encoded version: Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed.\r\n\r\n\r\n\r\n Bit\r\n 255 194 193 127 66 65 63 2 1\r\n ignored\r\n\r\n\r\n\r\n\r\n ignored\r\n\r\n\r\n\r\n\r\n ignored\r\n ignored sel ... ignored sel ignored sel\r\n\r\n\r\n Control Field 4 Control Field 2 Control Field1\r\n\r\n Figure 5-24. VPERMILPD Shuffle Control\r\n\r\n\r\n(immediate control version)\r\nPermute pairs of double-precision floating-point values in the first source operand (second operand), each pair\r\nusing a 1-bit control field in the imm8 byte. Each element in the destination operand (first operand) use a separate\r\ncontrol bit of the imm8 byte.\r\nVEX version: The source operand is a YMM/XMM register or a 256/128-bit memory location and the destination\r\noperand is a YMM/XMM register. Imm8 byte provides the lower 4/2 bit as permute control fields.\r\nEVEX version: The source operand (second operand) is a ZMM/YMM/XMM register, a 512/256/128-bit memory\r\nlocation or a 512/256/128-bit vector broadcasted from a 64-bit memory location. Permuted results are written to\r\nthe destination under the writemask. Imm8 byte provides the lower 8/4/2 bit as permute control fields.\r\nNote: For the imm8 versions, VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will\r\n#UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVPERMILPD (EVEX immediate versions)\r\n(KL, VL) = (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF (EVEX.b = 1) AND (SRC1 *is memory*)\r\n THEN TMP_SRC1[i+63:i] <- SRC1[63:0];\r\n ELSE TMP_SRC1[i+63:i] <- SRC1[i+63:i];\r\n FI;\r\nENDFOR;\r\nIF (imm8[0] = 0) THEN TMP_DEST[63:0] <- SRC1[63:0]; FI;\r\nIF (imm8[0] = 1) THEN TMP_DEST[63:0] <- TMP_SRC1[127:64]; FI;\r\nIF (imm8[1] = 0) THEN TMP_DEST[127:64] <- TMP_SRC1[63:0]; FI;\r\nIF (imm8[1] = 1) THEN TMP_DEST[127:64] <- TMP_SRC1[127:64]; FI;\r\nIF VL >= 256\r\n IF (imm8[2] = 0) THEN TMP_DEST[191:128] <- TMP_SRC1[191:128]; FI;\r\n IF (imm8[2] = 1) THEN TMP_DEST[191:128] <- TMP_SRC1[255:192]; FI;\r\n IF (imm8[3] = 0) THEN TMP_DEST[255:192] <- TMP_SRC1[191:128]; FI;\r\n IF (imm8[3] = 1) THEN TMP_DEST[255:192] <- TMP_SRC1[255:192]; FI;\r\nFI;\r\nIF VL >= 512\r\n IF (imm8[4] = 0) THEN TMP_DEST[319:256] <- TMP_SRC1[319:256]; FI;\r\n IF (imm8[4] = 1) THEN TMP_DEST[319:256] <- TMP_SRC1[383:320]; FI;\r\n IF (imm8[5] = 0) THEN TMP_DEST[383:320] <- TMP_SRC1[319:256]; FI;\r\n IF (imm8[5] = 1) THEN TMP_DEST[383:320] <- TMP_SRC1[383:320]; FI;\r\n IF (imm8[6] = 0) THEN TMP_DEST[447:384] <- TMP_SRC1[447:384]; FI;\r\n IF (imm8[6] = 1) THEN TMP_DEST[447:384] <- TMP_SRC1[511:448]; FI;\r\n IF (imm8[7] = 0) THEN TMP_DEST[511:448] <- TMP_SRC1[447:384]; FI;\r\n IF (imm8[7] = 1) THEN TMP_DEST[511:448] <- TMP_SRC1[511:448]; FI;\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPERMILPD (256-bit immediate version)\r\nIF (imm8[0] = 0) THEN DEST[63:0]<-SRC1[63:0]\r\nIF (imm8[0] = 1) THEN DEST[63:0]<-SRC1[127:64]\r\nIF (imm8[1] = 0) THEN DEST[127:64]<-SRC1[63:0]\r\nIF (imm8[1] = 1) THEN DEST[127:64]<-SRC1[127:64]\r\nIF (imm8[2] = 0) THEN DEST[191:128]<-SRC1[191:128]\r\nIF (imm8[2] = 1) THEN DEST[191:128]<-SRC1[255:192]\r\nIF (imm8[3] = 0) THEN DEST[255:192]<-SRC1[191:128]\r\nIF (imm8[3] = 1) THEN DEST[255:192]<-SRC1[255:192]\r\nDEST[MAX_VL-1:256]<-0\r\n\r\n\r\n\r\nVPERMILPD (128-bit immediate version)\r\nIF (imm8[0] = 0) THEN DEST[63:0]<-SRC1[63:0]\r\nIF (imm8[0] = 1) THEN DEST[63:0]<-SRC1[127:64]\r\nIF (imm8[1] = 0) THEN DEST[127:64]<-SRC1[63:0]\r\nIF (imm8[1] = 1) THEN DEST[127:64]<-SRC1[127:64]\r\nDEST[MAX_VL-1:128]<-0\r\n\r\nVPERMILPD (EVEX variable versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN TMP_SRC2[i+63:i] <- SRC2[63:0];\r\n ELSE TMP_SRC2[i+63:i] <- SRC2[i+63:i];\r\n FI;\r\nENDFOR;\r\n\r\nIF (TMP_SRC2[1] = 0) THEN TMP_DEST[63:0] <- SRC1[63:0]; FI;\r\nIF (TMP_SRC2[1] = 1) THEN TMP_DEST[63:0] <- SRC1[127:64]; FI;\r\nIF (TMP_SRC2[65] = 0) THEN TMP_DEST[127:64] <- SRC1[63:0]; FI;\r\nIF (TMP_SRC2[65] = 1) THEN TMP_DEST[127:64] <- SRC1[127:64]; FI;\r\nIF VL >= 256\r\n IF (TMP_SRC2[129] = 0) THEN TMP_DEST[191:128] <- SRC1[191:128]; FI;\r\n IF (TMP_SRC2[129] = 1) THEN TMP_DEST[191:128] <- SRC1[255:192]; FI;\r\n IF (TMP_SRC2[193] = 0) THEN TMP_DEST[255:192] <- SRC1[191:128]; FI;\r\n IF (TMP_SRC2[193] = 1) THEN TMP_DEST[255:192] <- SRC1[255:192]; FI;\r\nFI;\r\nIF VL >= 512\r\n IF (TMP_SRC2[257] = 0) THEN TMP_DEST[319:256] <- SRC1[319:256]; FI;\r\n IF (TMP_SRC2[257] = 1) THEN TMP_DEST[319:256] <- SRC1[383:320]; FI;\r\n IF (TMP_SRC2[321] = 0) THEN TMP_DEST[383:320] <- SRC1[319:256]; FI;\r\n IF (TMP_SRC2[321] = 1) THEN TMP_DEST[383:320] <- SRC1[383:320]; FI;\r\n IF (TMP_SRC2[385] = 0) THEN TMP_DEST[447:384] <- SRC1[447:384]; FI;\r\n IF (TMP_SRC2[385] = 1) THEN TMP_DEST[447:384] <- SRC1[511:448]; FI;\r\n IF (TMP_SRC2[449] = 0) THEN TMP_DEST[511:448] <- SRC1[447:384]; FI;\r\n IF (TMP_SRC2[449] = 1) THEN TMP_DEST[511:448] <- SRC1[511:448]; FI;\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVPERMILPD (256-bit variable version)\r\nIF (SRC2[1] = 0) THEN DEST[63:0]<-SRC1[63:0]\r\nIF (SRC2[1] = 1) THEN DEST[63:0]<-SRC1[127:64]\r\nIF (SRC2[65] = 0) THEN DEST[127:64]<-SRC1[63:0]\r\nIF (SRC2[65] = 1) THEN DEST[127:64]<-SRC1[127:64]\r\nIF (SRC2[129] = 0) THEN DEST[191:128]<-SRC1[191:128]\r\nIF (SRC2[129] = 1) THEN DEST[191:128]<-SRC1[255:192]\r\nIF (SRC2[193] = 0) THEN DEST[255:192]<-SRC1[191:128]\r\nIF (SRC2[193] = 1) THEN DEST[255:192]<-SRC1[255:192]\r\nDEST[MAX_VL-1:256]<-0\r\n\r\nVPERMILPD (128-bit variable version)\r\nIF (SRC2[1] = 0) THEN DEST[63:0]<-SRC1[63:0]\r\nIF (SRC2[1] = 1) THEN DEST[63:0]<-SRC1[127:64]\r\nIF (SRC2[65] = 0) THEN DEST[127:64]<-SRC1[63:0]\r\nIF (SRC2[65] = 1) THEN DEST[127:64]<-SRC1[127:64]\r\nDEST[MAX_VL-1:128]<-0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPERMILPD __m512d _mm512_permute_pd( __m512d a, int imm);\r\nVPERMILPD __m512d _mm512_mask_permute_pd(__m512d s, __mmask8 k, __m512d a, int imm);\r\nVPERMILPD __m512d _mm512_maskz_permute_pd( __mmask8 k, __m512d a, int imm);\r\nVPERMILPD __m256d _mm256_mask_permute_pd(__m256d s, __mmask8 k, __m256d a, int imm);\r\nVPERMILPD __m256d _mm256_maskz_permute_pd( __mmask8 k, __m256d a, int imm);\r\nVPERMILPD __m128d _mm_mask_permute_pd(__m128d s, __mmask8 k, __m128d a, int imm);\r\nVPERMILPD __m128d _mm_maskz_permute_pd( __mmask8 k, __m128d a, int imm);\r\nVPERMILPD __m512d _mm512_permutevar_pd( __m512i i, __m512d a);\r\nVPERMILPD __m512d _mm512_mask_permutevar_pd(__m512d s, __mmask8 k, __m512i i, __m512d a);\r\nVPERMILPD __m512d _mm512_maskz_permutevar_pd( __mmask8 k, __m512i i, __m512d a);\r\nVPERMILPD __m256d _mm256_mask_permutevar_pd(__m256d s, __mmask8 k, __m256d i, __m256d a);\r\nVPERMILPD __m256d _mm256_maskz_permutevar_pd( __mmask8 k, __m256d i, __m256d a);\r\nVPERMILPD __m128d _mm_mask_permutevar_pd(__m128d s, __mmask8 k, __m128d i, __m128d a);\r\nVPERMILPD __m128d _mm_maskz_permutevar_pd( __mmask8 k, __m128d i, __m128d a);\r\nVPERMILPD __m128d _mm_permute_pd (__m128d a, int control)\r\nVPERMILPD __m256d _mm256_permute_pd (__m256d a, int control)\r\nVPERMILPD __m128d _mm_permutevar_pd (__m128d a, __m128i control);\r\nVPERMILPD __m256d _mm256_permutevar_pd (__m256d a, __m256i control);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4; additionally\r\n#UD If VEX.W = 1.\r\nEVEX-encoded instruction, see Exceptions Type E4NF.\r\n#UD If either (E)VEX.vvvv != 1111B and with imm8.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPERMILPD"
},
{
"description": "VPERMILPS-Permute In-Lane of Quadruples of Single-Precision Floating-Point Values\r\n Opcode/ Op / En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n VEX.NDS.128.66.0F38.W0 0C /r RVM V/V AVX Permute single-precision floating-point values in\r\n VPERMILPS xmm1, xmm2, xmm3/m128 xmm2 using controls from xmm3/m128 and\r\n store result in xmm1.\r\n VEX.128.66.0F3A.W0 04 /r ib RM V/V AVX Permute single-precision floating-point values in\r\n VPERMILPS xmm1, xmm2/m128, imm8 xmm2/m128 using controls from imm8 and store\r\n result in xmm1.\r\n VEX.NDS.256.66.0F38.W0 0C /r RVM V/V AVX Permute single-precision floating-point values in\r\n VPERMILPS ymm1, ymm2, ymm3/m256 ymm2 using controls from ymm3/m256 and\r\n store result in ymm1.\r\n VEX.256.66.0F3A.W0 04 /r ib RM V/V AVX Permute single-precision floating-point values in\r\n VPERMILPS ymm1, ymm2/m256, imm8 ymm2/m256 using controls from imm8 and store\r\n result in ymm1.\r\n EVEX.NDS.128.66.0F38.W0 0C /r FV-RVM V/V AVX512VL Permute single-precision floating-point values\r\n VPERMILPS xmm1 {k1}{z}, xmm2, AVX512F xmm2 using control from xmm3/m128/m32bcst\r\n xmm3/m128/m32bcst and store the result in xmm1 using writemask k1.\r\n EVEX.NDS.256.66.0F38.W0 0C /r FV-RVM V/V AVX512VL Permute single-precision floating-point values\r\n VPERMILPS ymm1 {k1}{z}, ymm2, AVX512F ymm2 using control from ymm3/m256/m32bcst\r\n ymm3/m256/m32bcst and store the result in ymm1 using writemask k1.\r\n EVEX.NDS.512.66.0F38.W0 0C /r FV-RVM V/V AVX512F Permute single-precision floating-point values\r\n VPERMILPS zmm1 {k1}{z}, zmm2, zmm2 using control from zmm3/m512/m32bcst\r\n zmm3/m512/m32bcst and store the result in zmm1 using writemask k1.\r\n EVEX.128.66.0F3A.W0 04 /r ib FV-RM V/V AVX512VL Permute single-precision floating-point values\r\n VPERMILPS xmm1 {k1}{z}, AVX512F xmm2/m128/m32bcst using controls from imm8\r\n xmm2/m128/m32bcst, imm8 and store the result in xmm1 using writemask k1.\r\n EVEX.256.66.0F3A.W0 04 /r ib FV-RM V/V AVX512VL Permute single-precision floating-point values\r\n VPERMILPS ymm1 {k1}{z}, AVX512F ymm2/m256/m32bcst using controls from imm8\r\n ymm2/m256/m32bcst, imm8 and store the result in ymm1 using writemask k1.\r\n EVEX.512.66.0F3A.W0 04 /r FV-RM V/V AVX512F Permute single-precision floating-point values\r\n ibVPERMILPS zmm1 {k1}{z}, zmm2/m512/m32bcst using controls from imm8\r\n zmm2/m512/m32bcst, imm8 and store the result in zmm1 using writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n FV-RVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n FV-RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\n\r\n\r\n\r\n\r\nDescription\r\n(variable control version)\r\nPermute quadruples of single-precision floating-point values in the first source operand (second operand), each\r\nquadruplet using a 2-bit control field in the corresponding dword element of the second source operand. Permuted\r\nresults are stored in the destination operand (first operand).\r\nThe 2-bit control fields are located at the low two bits of each dword element (see Figure 5-26). Each control deter-\r\nmines which of the source element in an input quadruple is selected for the destination element. Each quadruple of\r\nsource elements must lie in the same 128-bit region as the destination.\r\nEVEX version: The second source operand (third operand) is a ZMM/YMM/XMM register, a 512/256/128-bit\r\nmemory location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. Permuted results are\r\nwritten to the destination under the writemask.\r\n\r\n\r\n\r\n\r\n SRC1 X7 X6 X5 X4 X3 X2 X1 X0\r\n\r\n\r\n\r\n\r\n DEST X7 .. X4 X7 .. X4 X7 .. X4 X7 .. X4 X3 ..X0 X3 ..X0 X3 .. X0 X3 .. X0\r\n\r\n\r\n\r\n\r\n Figure 5-25. VPERMILPS Operation\r\n\r\n\r\n\r\n\r\n Bit\r\n 255 226 225 224 63 34 33 32 31 1 0\r\n\r\n\r\n ignored sel ... ignored sel ignored sel\r\n\r\n\r\n Control Field 7 Control Field 2 Control Field 1\r\n\r\n Figure 5-26. VPERMILPS Shuffle Control\r\n\r\n\r\n(immediate control version)\r\nPermute quadruples of single-precision floating-point values in the first source operand (second operand), each\r\nquadruplet using a 2-bit control field in the imm8 byte. Each 128-bit lane in the destination operand (first operand)\r\nuse the four control fields of the same imm8 byte.\r\nVEX version: The source operand is a YMM/XMM register or a 256/128-bit memory location and the destination\r\noperand is a YMM/XMM register.\r\nEVEX version: The source operand (second operand) is a ZMM/YMM/XMM register, a 512/256/128-bit memory\r\nlocation or a 512/256/128-bit vector broadcasted from a 32-bit memory location. Permuted results are written to\r\nthe destination under the writemask.\r\nNote: For the imm8 version, VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will\r\n#UD.\r\n\r\n\r\n\r\n\r\nOperation\r\nSelect4(SRC, control) {\r\nCASE (control[1:0]) OF\r\n 0: TMP <-SRC[31:0];\r\n 1: TMP <-SRC[63:32];\r\n 2: TMP <-SRC[95:64];\r\n 3: TMP <-SRC[127:96];\r\nESAC;\r\nRETURN TMP\r\n}\r\n\r\nVPERMILPS (EVEX immediate versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF (EVEX.b = 1) AND (SRC1 *is memory*)\r\n THEN TMP_SRC1[i+31:i] <- SRC1[31:0];\r\n ELSE TMP_SRC1[i+31:i] <- SRC1[i+31:i];\r\n FI;\r\nENDFOR;\r\n\r\nTMP_DEST[31:0] <- Select4(TMP_SRC1[127:0], imm8[1:0]);\r\nTMP_DEST[63:32] <- Select4(TMP_SRC1[127:0], imm8[3:2]);\r\nTMP_DEST[95:64] <- Select4(TMP_SRC1[127:0], imm8[5:4]);\r\nTMP_DEST[127:96] <- Select4(TMP_SRC1[127:0], imm8[7:6]); FI;\r\nIF VL >= 256\r\n TMP_DEST[159:128] <- Select4(TMP_SRC1[255:128], imm8[1:0]); FI;\r\n TMP_DEST[191:160] <- Select4(TMP_SRC1[255:128], imm8[3:2]); FI;\r\n TMP_DEST[223:192] <- Select4(TMP_SRC1[255:128], imm8[5:4]); FI;\r\n TMP_DEST[255:224] <- Select4(TMP_SRC1[255:128], imm8[7:6]); FI;\r\nFI;\r\nIF VL >= 512\r\n TMP_DEST[287:256] <- Select4(TMP_SRC1[383:256], imm8[1:0]); FI;\r\n TMP_DEST[319:288] <- Select4(TMP_SRC1[383:256], imm8[3:2]); FI;\r\n TMP_DEST[351:320] <- Select4(TMP_SRC1[383:256], imm8[5:4]); FI;\r\n TMP_DEST[383:352] <- Select4(TMP_SRC1[383:256], imm8[7:6]); FI;\r\n TMP_DEST[415:384] <- Select4(TMP_SRC1[511:384], imm8[1:0]); FI;\r\n TMP_DEST[447:416] <- Select4(TMP_SRC1[511:384], imm8[3:2]); FI;\r\n TMP_DEST[479:448] <- Select4(TMP_SRC1[511:384], imm8[5:4]); FI;\r\n TMP_DEST[511:480] <- Select4(TMP_SRC1[511:384], imm8[7:6]); FI;\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_DEST[i+31:i]\r\n ELSE\r\n IF *merging-masking*\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE DEST[i+31:i] <- 0 ;zeroing-masking\r\n FI;\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\nVPERMILPS (256-bit immediate version)\r\nDEST[31:0] <-Select4(SRC1[127:0], imm8[1:0]);\r\nDEST[63:32] <-Select4(SRC1[127:0], imm8[3:2]);\r\nDEST[95:64] <-Select4(SRC1[127:0], imm8[5:4]);\r\nDEST[127:96] <-Select4(SRC1[127:0], imm8[7:6]);\r\nDEST[159:128] <-Select4(SRC1[255:128], imm8[1:0]);\r\nDEST[191:160] <-Select4(SRC1[255:128], imm8[3:2]);\r\nDEST[223:192] <-Select4(SRC1[255:128], imm8[5:4]);\r\nDEST[255:224] <-Select4(SRC1[255:128], imm8[7:6]);\r\n\r\nVPERMILPS (128-bit immediate version)\r\nDEST[31:0] <-Select4(SRC1[127:0], imm8[1:0]);\r\nDEST[63:32] <-Select4(SRC1[127:0], imm8[3:2]);\r\nDEST[95:64] <-Select4(SRC1[127:0], imm8[5:4]);\r\nDEST[127:96] <-Select4(SRC1[127:0], imm8[7:6]);\r\nDEST[MAX_VL-1:128]<-0\r\n\r\nVPERMILPS (EVEX variable versions)\r\n(KL, VL) = (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN TMP_SRC2[i+31:i] <- SRC2[31:0];\r\n ELSE TMP_SRC2[i+31:i] <- SRC2[i+31:i];\r\n FI;\r\nENDFOR;\r\nTMP_DEST[31:0] <- Select4(SRC1[127:0], TMP_SRC2[1:0]);\r\nTMP_DEST[63:32] <- Select4(SRC1[127:0], TMP_SRC2[33:32]);\r\nTMP_DEST[95:64] <- Select4(SRC1[127:0], TMP_SRC2[65:64]);\r\nTMP_DEST[127:96] <- Select4(SRC1[127:0], TMP_SRC2[97:96]);\r\nIF VL >= 256\r\n TMP_DEST[159:128] <- Select4(SRC1[255:128], TMP_SRC2[129:128]);\r\n TMP_DEST[191:160] <- Select4(SRC1[255:128], TMP_SRC2[161:160]);\r\n TMP_DEST[223:192] <- Select4(SRC1[255:128], TMP_SRC2[193:192]);\r\n TMP_DEST[255:224] <- Select4(SRC1[255:128], TMP_SRC2[225:224]);\r\nFI;\r\nIF VL >= 512\r\n TMP_DEST[287:256] <- Select4(SRC1[383:256], TMP_SRC2[257:256]);\r\n TMP_DEST[319:288] <- Select4(SRC1[383:256], TMP_SRC2[289:288]);\r\n TMP_DEST[351:320] <- Select4(SRC1[383:256], TMP_SRC2[321:320]);\r\n TMP_DEST[383:352] <- Select4(SRC1[383:256], TMP_SRC2[353:352]);\r\n TMP_DEST[415:384] <- Select4(SRC1[511:384], TMP_SRC2[385:384]);\r\n TMP_DEST[447:416] <- Select4(SRC1[511:384], TMP_SRC2[417:416]);\r\n TMP_DEST[479:448] <- Select4(SRC1[511:384], TMP_SRC2[449:448]);\r\n TMP_DEST[511:480] <- Select4(SRC1[511:384], TMP_SRC2[481:480]);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_DEST[i+31:i]\r\n ELSE\r\n IF *merging-masking*\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE DEST[i+31:i] <- 0 ;zeroing-masking\r\n\r\n\r\n\r\n FI;\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPERMILPS (256-bit variable version)\r\nDEST[31:0] <-Select4(SRC1[127:0], SRC2[1:0]);\r\nDEST[63:32] <-Select4(SRC1[127:0], SRC2[33:32]);\r\nDEST[95:64] <-Select4(SRC1[127:0], SRC2[65:64]);\r\nDEST[127:96] <-Select4(SRC1[127:0], SRC2[97:96]);\r\nDEST[159:128] <-Select4(SRC1[255:128], SRC2[129:128]);\r\nDEST[191:160] <-Select4(SRC1[255:128], SRC2[161:160]);\r\nDEST[223:192] <-Select4(SRC1[255:128], SRC2[193:192]);\r\nDEST[255:224] <-Select4(SRC1[255:128], SRC2[225:224]);\r\nDEST[MAX_VL-1:256]<-0\r\n\r\nVPERMILPS (128-bit variable version)\r\nDEST[31:0] <-Select4(SRC1[127:0], SRC2[1:0]);\r\nDEST[63:32] <-Select4(SRC1[127:0], SRC2[33:32]);\r\nDEST[95:64] <-Select4(SRC1[127:0], SRC2[65:64]);\r\nDEST[127:96] <-Select4(SRC1[127:0], SRC2[97:96]);\r\nDEST[MAX_VL-1:128]<-0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPERMILPS __m512 _mm512_permute_ps( __m512 a, int imm);\r\nVPERMILPS __m512 _mm512_mask_permute_ps(__m512 s, __mmask16 k, __m512 a, int imm);\r\nVPERMILPS __m512 _mm512_maskz_permute_ps( __mmask16 k, __m512 a, int imm);\r\nVPERMILPS __m256 _mm256_mask_permute_ps(__m256 s, __mmask8 k, __m256 a, int imm);\r\nVPERMILPS __m256 _mm256_maskz_permute_ps( __mmask8 k, __m256 a, int imm);\r\nVPERMILPS __m128 _mm_mask_permute_ps(__m128 s, __mmask8 k, __m128 a, int imm);\r\nVPERMILPS __m128 _mm_maskz_permute_ps( __mmask8 k, __m128 a, int imm);\r\nVPERMILPS __m512 _mm512_permutevar_ps( __m512i i, __m512 a);\r\nVPERMILPS __m512 _mm512_mask_permutevar_ps(__m512 s, __mmask16 k, __m512i i, __m512 a);\r\nVPERMILPS __m512 _mm512_maskz_permutevar_ps( __mmask16 k, __m512i i, __m512 a);\r\nVPERMILPS __m256 _mm256_mask_permutevar_ps(__m256 s, __mmask8 k, __m256 i, __m256 a);\r\nVPERMILPS __m256 _mm256_maskz_permutevar_ps( __mmask8 k, __m256 i, __m256 a);\r\nVPERMILPS __m128 _mm_mask_permutevar_ps(__m128 s, __mmask8 k, __m128 i, __m128 a);\r\nVPERMILPS __m128 _mm_maskz_permutevar_ps( __mmask8 k, __m128 i, __m128 a);\r\nVPERMILPS __m128 _mm_permute_ps (__m128 a, int control);\r\nVPERMILPS __m256 _mm256_permute_ps (__m256 a, int control);\r\nVPERMILPS __m128 _mm_permutevar_ps (__m128 a, __m128i control);\r\nVPERMILPS __m256 _mm256_permutevar_ps (__m256 a, __m256i control);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4;\r\n#UD If VEX.W = 1.\r\nEVEX-encoded instruction, see Exceptions Type E4NF.\r\n#UD If either (E)VEX.vvvv != 1111B and with imm8.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPERMILPS"
},
{
"description": "VPERMPD-Permute Double-Precision Floating-Point Elements\r\n Opcode/ Op / En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n VEX.256.66.0F3A.W1 01 /r ib RMI V/V AVX2 Permute double-precision floating-point elements in\r\n VPERMPD ymm1, ymm2/m256, imm8 ymm2/m256 using indices in imm8 and store the\r\n result in ymm1.\r\n EVEX.256.66.0F3A.W1 01 /r ib FV-RM V/V AVX512VL Permute double-precision floating-point elements in\r\n VPERMPD ymm1 {k1}{z}, AVX512F ymm2/m256/m64bcst using indexes in imm8 and\r\n ymm2/m256/m64bcst, imm8 store the result in ymm1 subject to writemask k1.\r\n EVEX.512.66.0F3A.W1 01 /r ib FV-RMI V/V AVX512F Permute double-precision floating-point elements in\r\n VPERMPD zmm1 {k1}{z}, zmm2/m512/m64bcst using indices in imm8 and\r\n zmm2/m512/m64bcst, imm8 store the result in zmm1 subject to writemask k1.\r\n EVEX.NDS.256.66.0F38.W1 16 /r FV-RVM V/V AVX512VL Permute double-precision floating-point elements in\r\n VPERMPD ymm1 {k1}{z}, ymm2, AVX512F ymm3/m256/m64bcst using indexes in ymm2 and\r\n ymm3/m256/m64bcst store the result in ymm1 subject to writemask k1.\r\n EVEX.NDS.512.66.0F38.W1 16 /r FV-RVM V/V AVX512F Permute double-precision floating-point elements in\r\n VPERMPD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst using indices in zmm2 and\r\n zmm3/m512/m64bcst store the result in zmm1 subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (w) ModRM:r/m (r) Imm8 NA\r\n FV-RMI ModRM:reg (w) ModRM:r/m (r) Imm8 NA\r\n FV-RVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nThe imm8 version: Copies quadword elements of double-precision floating-point values from the source operand\r\n(the second operand) to the destination operand (the first operand) according to the indices specified by the imme-\r\ndiate operand (the third operand). Each two-bit value in the immediate byte selects a qword element in the source\r\noperand.\r\nVEX version: The source operand can be a YMM register or a memory location. Bits (MAX_VL-1:256) of the corre-\r\nsponding destination register are zeroed.\r\nIn EVEX.512 encoded version, The elements in the destination are updated using the writemask k1 and the imm8\r\nbits are reused as control bits for the upper 256-bit half when the control bits are coming from immediate. The\r\nsource operand can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit\r\nmemory location.\r\nThe imm8 versions: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.\r\nThe vector control version: Copies quadword elements of double-precision floating-point values from the second\r\nsource operand (the third operand) to the destination operand (the first operand) according to the indices in the\r\nfirst source operand (the second operand). The first 3 bits of each 64 bit element in the index operand selects\r\nwhich quadword in the second source operand to copy. The first and second operands are ZMM registers, the third\r\noperand can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit memory\r\nlocation. The elements in the destination are updated using the writemask k1.\r\nNote that this instruction permits a qword in the source operand to be copied to multiple locations in the destina-\r\ntion operand.\r\nIf VPERMPD is encoded with VEX.L= 0, an attempt to execute the instruction encoded with VEX.L= 0 will cause an\r\n#UD exception.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVPERMPD (EVEX - imm8 control forms)\r\n(KL, VL) = (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF (EVEX.b = 1) AND (SRC *is memory*)\r\n THEN TMP_SRC[i+63:i] <- SRC[63:0];\r\n ELSE TMP_SRC[i+63:i] <- SRC[i+63:i];\r\n FI;\r\nENDFOR;\r\n\r\nTMP_DEST[63:0] <- (TMP_SRC[256:0] >> (IMM8[1:0] * 64))[63:0];\r\nTMP_DEST[127:64] <- (TMP_SRC[256:0] >> (IMM8[3:2] * 64))[63:0];\r\nTMP_DEST[191:128] <- (TMP_SRC[256:0] >> (IMM8[5:4] * 64))[63:0];\r\nTMP_DEST[255:192] <- (TMP_SRC[256:0] >> (IMM8[7:6] * 64))[63:0];\r\nIF VL >= 512\r\n TMP_DEST[319:256] <- (TMP_SRC[511:256] >> (IMM8[1:0] * 64))[63:0];\r\n TMP_DEST[383:320] <- (TMP_SRC[511:256] >> (IMM8[3:2] * 64))[63:0];\r\n TMP_DEST[447:384] <- (TMP_SRC[511:256] >> (IMM8[5:4] * 64))[63:0];\r\n TMP_DEST[511:448] <- (TMP_SRC[511:256] >> (IMM8[7:6] * 64))[63:0];\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0 ;zeroing-masking\r\n FI;\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\nVPERMPD (EVEX - vector control forms)\r\n(KL, VL) = (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN TMP_SRC2[i+63:i] <- SRC2[63:0];\r\n ELSE TMP_SRC2[i+63:i] <- SRC2[i+63:i];\r\n FI;\r\nENDFOR;\r\n\r\nIF VL = 256\r\n TMP_DEST[63:0] <- (TMP_SRC2[255:0] >> (SRC1[1:0] * 64))[63:0];\r\n TMP_DEST[127:64] <- (TMP_SRC2[255:0] >> (SRC1[65:64] * 64))[63:0];\r\n TMP_DEST[191:128] <- (TMP_SRC2[255:0] >> (SRC1[129:128] * 64))[63:0];\r\n TMP_DEST[255:192] <- (TMP_SRC2[255:0] >> (SRC1[193:192] * 64))[63:0];\r\nFI;\r\nIF VL = 512\r\n TMP_DEST[63:0] <- (TMP_SRC2[511:0] >> (SRC1[2:0] * 64))[63:0];\r\n\r\n\r\n\r\n\r\n TMP_DEST[127:64] <- (TMP_SRC2[511:0] >> (SRC1[66:64] * 64))[63:0];\r\n TMP_DEST[191:128] <- (TMP_SRC2[511:0] >> (SRC1[130:128] * 64))[63:0];\r\n TMP_DEST[255:192] <- (TMP_SRC2[511:0] >> (SRC1[194:192] * 64))[63:0];\r\n TMP_DEST[319:256] <- (TMP_SRC2[511:0] >> (SRC1[258:256] * 64))[63:0];\r\n TMP_DEST[383:320] <- (TMP_SRC2[511:0] >> (SRC1[322:320] * 64))[63:0];\r\n TMP_DEST[447:384] <- (TMP_SRC2[511:0] >> (SRC1[386:384] * 64))[63:0];\r\n TMP_DEST[511:448] <- (TMP_SRC2[511:0] >> (SRC1[450:448] * 64))[63:0];\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0 ;zeroing-masking\r\n FI;\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPERMPD (VEX.256 encoded version)\r\nDEST[63:0] <-(SRC[255:0] >> (IMM8[1:0] * 64))[63:0];\r\nDEST[127:64] <-(SRC[255:0] >> (IMM8[3:2] * 64))[63:0];\r\nDEST[191:128] <-(SRC[255:0] >> (IMM8[5:4] * 64))[63:0];\r\nDEST[255:192] <-(SRC[255:0] >> (IMM8[7:6] * 64))[63:0];\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPERMPD __m512d _mm512_permutex_pd( __m512d a, int imm);\r\nVPERMPD __m512d _mm512_mask_permutex_pd(__m512d s, __mmask16 k, __m512d a, int imm);\r\nVPERMPD __m512d _mm512_maskz_permutex_pd( __mmask16 k, __m512d a, int imm);\r\nVPERMPD __m512d _mm512_permutexvar_pd( __m512i i, __m512d a);\r\nVPERMPD __m512d _mm512_mask_permutexvar_pd(__m512d s, __mmask16 k, __m512i i, __m512d a);\r\nVPERMPD __m512d _mm512_maskz_permutexvar_pd( __mmask16 k, __m512i i, __m512d a);\r\nVPERMPD __m256d _mm256_permutex_epi64( __m256d a, int imm);\r\nVPERMPD __m256d _mm256_mask_permutex_epi64(__m256i s, __mmask8 k, __m256d a, int imm);\r\nVPERMPD __m256d _mm256_maskz_permutex_epi64( __mmask8 k, __m256d a, int imm);\r\nVPERMPD __m256d _mm256_permutexvar_epi64( __m256i i, __m256d a);\r\nVPERMPD __m256d _mm256_mask_permutexvar_epi64(__m256i s, __mmask8 k, __m256i i, __m256d a);\r\nVPERMPD __m256d _mm256_maskz_permutexvar_epi64( __mmask8 k, __m256i i, __m256d a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4; additionally\r\n#UD If VEX.L = 0.\r\n If VEX.vvvv != 1111B.\r\nEVEX-encoded instruction, see Exceptions Type E4NF.\r\n#UD If encoded with EVEX.128.\r\n If EVEX.vvvv != 1111B and with imm8.\r\n\r\n\r\n",
"mnem": "VPERMPD"
},
{
"description": "VPERMPS-Permute Single-Precision Floating-Point Elements\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.256.66.0F38.W0 16 /r RVM V/V AVX2 Permute single-precision floating-point elements in\r\n VPERMPS ymm1, ymm2, ymm3/m256 using indices in ymm2 and store the result in\r\n ymm3/m256 ymm1.\r\n EVEX.NDS.256.66.0F38.W0 16 /r FV V/V AVX512VL Permute single-precision floating-point elements in\r\n VPERMPS ymm1 {k1}{z}, ymm2, AVX512F ymm3/m256/m32bcst using indexes in ymm2 and store\r\n ymm3/m256/m32bcst the result in ymm1 subject to write mask k1.\r\n EVEX.NDS.512.66.0F38.W0 16 /r FV V/V AVX512F Permute single-precision floating-point values in\r\n VPERMPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst using indices in zmm2 and store the\r\n zmm3/m512/m32bcst result in zmm1 subject to write mask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nCopies doubleword elements of single-precision floating-point values from the second source operand (the third\r\noperand) to the destination operand (the first operand) according to the indices in the first source operand (the\r\nsecond operand). Note that this instruction permits a doubleword in the source operand to be copied to more than\r\none location in the destination operand.\r\nVEX.256 versions: The first and second operands are YMM registers, the third operand can be a YMM register or\r\nmemory location. Bits (MAX_VL-1:256) of the corresponding destination register are zeroed.\r\nEVEX encoded version: The first and second operands are ZMM registers, the third operand can be a ZMM register,\r\na 512-bit memory location or a 512-bit vector broadcasted from a 32-bit memory location. The elements in the\r\ndestination are updated using the writemask k1.\r\nIf VPERMPS is encoded with VEX.L= 0, an attempt to execute the instruction encoded with VEX.L= 0 will cause an\r\n#UD exception.\r\n\r\nOperation\r\nVPERMPS (EVEX forms)\r\n(KL, VL) (8, 256),= (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN TMP_SRC2[i+31:i] <- SRC2[31:0];\r\n ELSE TMP_SRC2[i+31:i] <- SRC2[i+31:i];\r\n FI;\r\nENDFOR;\r\n\r\nIF VL = 256\r\n TMP_DEST[31:0] <- (TMP_SRC2[255:0] >> (SRC1[2:0] * 32))[31:0];\r\n TMP_DEST[63:32] <- (TMP_SRC2[255:0] >> (SRC1[34:32] * 32))[31:0];\r\n TMP_DEST[95:64] <- (TMP_SRC2[255:0] >> (SRC1[66:64] * 32))[31:0];\r\n TMP_DEST[127:96] <- (TMP_SRC2[255:0] >> (SRC1[98:96] * 32))[31:0];\r\n TMP_DEST[159:128] <- (TMP_SRC2[255:0] >> (SRC1[130:128] * 32))[31:0];\r\n TMP_DEST[191:160] <- (TMP_SRC2[255:0] >> (SRC1[162:160] * 32))[31:0];\r\n TMP_DEST[223:192] <- (TMP_SRC2[255:0] >> (SRC1[193:192] * 32))[31:0];\r\n TMP_DEST[255:224] <- (TMP_SRC2[255:0] >> (SRC1[226:224] * 32))[31:0];\r\n\r\n\r\n\r\nFI;\r\nIF VL = 512\r\n TMP_DEST[31:0] <- (TMP_SRC2[511:0] >> (SRC1[3:0] * 32))[31:0];\r\n TMP_DEST[63:32] <- (TMP_SRC2[511:0] >> (SRC1[35:32] * 32))[31:0];\r\n TMP_DEST[95:64] <- (TMP_SRC2[511:0] >> (SRC1[67:64] * 32))[31:0];\r\n TMP_DEST[127:96] <- (TMP_SRC2[511:0] >> (SRC1[99:96] * 32))[31:0];\r\n TMP_DEST[159:128] <- (TMP_SRC2[511:0] >> (SRC1[131:128] * 32))[31:0];\r\n TMP_DEST[191:160] <- (TMP_SRC2[511:0] >> (SRC1[163:160] * 32))[31:0];\r\n TMP_DEST[223:192] <- (TMP_SRC2[511:0] >> (SRC1[195:192] * 32))[31:0];\r\n TMP_DEST[255:224] <- (TMP_SRC2[511:0] >> (SRC1[227:224] * 32))[31:0];\r\n TMP_DEST[287:256] <- (TMP_SRC2[511:0] >> (SRC1[259:256] * 32))[31:0];\r\n TMP_DEST[319:288] <- (TMP_SRC2[511:0] >> (SRC1[291:288] * 32))[31:0];\r\n TMP_DEST[351:320] <- (TMP_SRC2[511:0] >> (SRC1[323:320] * 32))[31:0];\r\n TMP_DEST[383:352] <- (TMP_SRC2[511:0] >> (SRC1[355:352] * 32))[31:0];\r\n TMP_DEST[415:384] <- (TMP_SRC2[511:0] >> (SRC1[387:384] * 32))[31:0];\r\n TMP_DEST[447:416] <- (TMP_SRC2[511:0] >> (SRC1[419:416] * 32))[31:0];\r\n TMP_DEST[479:448] <-(TMP_SRC2[511:0] >> (SRC1[451:448] * 32))[31:0];\r\n TMP_DEST[511:480] <- (TMP_SRC2[511:0] >> (SRC1[483:480] * 32))[31:0];\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_DEST[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0 ;zeroing-masking\r\n FI;\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPERMPS (VEX.256 encoded version)\r\nDEST[31:0] <-(SRC2[255:0] >> (SRC1[2:0] * 32))[31:0];\r\nDEST[63:32] <-(SRC2[255:0] >> (SRC1[34:32] * 32))[31:0];\r\nDEST[95:64] <-(SRC2[255:0] >> (SRC1[66:64] * 32))[31:0];\r\nDEST[127:96] <-(SRC2[255:0] >> (SRC1[98:96] * 32))[31:0];\r\nDEST[159:128] <-(SRC2[255:0] >> (SRC1[130:128] * 32))[31:0];\r\nDEST[191:160] <-(SRC2[255:0] >> (SRC1[162:160] * 32))[31:0];\r\nDEST[223:192] <-(SRC2[255:0] >> (SRC1[194:192] * 32))[31:0];\r\nDEST[255:224] <-(SRC2[255:0] >> (SRC1[226:224] * 32))[31:0];\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPERMPS __m512 _mm512_permutexvar_ps(__m512i i, __m512 a);\r\nVPERMPS __m512 _mm512_mask_permutexvar_ps(__m512 s, __mmask16 k, __m512i i, __m512 a);\r\nVPERMPS __m512 _mm512_maskz_permutexvar_ps( __mmask16 k, __m512i i, __m512 a);\r\nVPERMPS __m256 _mm256_permutexvar_ps(__m256 i, __m256 a);\r\nVPERMPS __m256 _mm256_mask_permutexvar_ps(__m256 s, __mmask8 k, __m256 i, __m256 a);\r\nVPERMPS __m256 _mm256_maskz_permutexvar_ps( __mmask8 k, __m256 i, __m256 a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4; additionally\r\n#UD If VEX.L = 0.\r\nEVEX-encoded instruction, see Exceptions Type E4NF.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPERMPS"
},
{
"description": "VPERMQ-Qwords Element Permutation\r\n Opcode/ Op / En 64/32 CPUID Description\r\n Instruction bit Mode Feature\r\n Support Flag\r\n VEX.256.66.0F3A.W1 00 /r ib RMI V/V AVX2 Permute qwords in ymm2/m256 using indices in\r\n VPERMQ ymm1, ymm2/m256, imm8 imm8 and store the result in ymm1.\r\n EVEX.256.66.0F3A.W1 00 /r ib FV-RM V/V AVX512VL Permute qwords in ymm2/m256/m64bcst using\r\n VPERMQ ymm1 {k1}{z}, AVX512F indexes in imm8 and store the result in ymm1.\r\n ymm2/m256/m64bcst, imm8\r\n EVEX.512.66.0F3A.W1 00 /r ib FV-RMI V/V AVX512F Permute qwords in zmm2/m512/m64bcst using\r\n VPERMQ zmm1 {k1}{z}, indices in imm8 and store the result in zmm1.\r\n zmm2/m512/m64bcst, imm8\r\n EVEX.NDS.256.66.0F38.W1 36 /r FV-RVM V/V AVX512VL Permute qwords in ymm3/m256/m64bcst using\r\n VPERMQ ymm1 {k1}{z}, ymm2, AVX512F indexes in ymm2 and store the result in ymm1.\r\n ymm3/m256/m64bcst\r\n EVEX.NDS.512.66.0F38.W1 36 /r FV-RVM V/V AVX512F Permute qwords in zmm3/m512/m64bcst using\r\n VPERMQ zmm1 {k1}{z}, zmm2, indices in zmm2 and store the result in zmm1.\r\n zmm3/m512/m64bcst\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMI ModRM:reg (w) ModRM:r/m (r) Imm8 NA\r\n FV-RMI ModRM:reg (w) ModRM:r/m (r) Imm8 NA\r\n FV-RVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nThe imm8 version: Copies quadwords from the source operand (the second operand) to the destination operand\r\n(the first operand) according to the indices specified by the immediate operand (the third operand). Each two-bit\r\nvalue in the immediate byte selects a qword element in the source operand.\r\nVEX version: The source operand can be a YMM register or a memory location. Bits (MAX_VL-1:256) of the corre-\r\nsponding destination register are zeroed.\r\nIn EVEX.512 encoded version, The elements in the destination are updated using the writemask k1 and the imm8\r\nbits are reused as control bits for the upper 256-bit half when the control bits are coming from immediate. The\r\nsource operand can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit\r\nmemory location.\r\nImmediate control versions: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will\r\n#UD.\r\nThe vector control version: Copies quadwords from the second source operand (the third operand) to the destina-\r\ntion operand (the first operand) according to the indices in the first source operand (the second operand). The first\r\n3 bits of each 64 bit element in the index operand selects which quadword in the second source operand to copy.\r\nThe first and second operands are ZMM registers, the third operand can be a ZMM register, a 512-bit memory loca-\r\ntion or a 512-bit vector broadcasted from a 64-bit memory location. The elements in the destination are updated\r\nusing the writemask k1.\r\nNote that this instruction permits a qword in the source operand to be copied to multiple locations in the destina-\r\ntion operand.\r\nIf VPERMPQ is encoded with VEX.L= 0 or EVEX.128, an attempt to execute the instruction will cause an #UD excep-\r\ntion.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVPERMQ (EVEX - imm8 control forms)\r\n(KL, VL) = (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF (EVEX.b = 1) AND (SRC *is memory*)\r\n THEN TMP_SRC[i+63:i] <- SRC[63:0];\r\n ELSE TMP_SRC[i+63:i] <- SRC[i+63:i];\r\n FI;\r\nENDFOR;\r\n TMP_DEST[63:0] <- (TMP_SRC[255:0] >> (IMM8[1:0] * 64))[63:0];\r\n TMP_DEST[127:64] <- (TMP_SRC[255:0] >> (IMM8[3:2] * 64))[63:0];\r\n TMP_DEST[191:128] <- (TMP_SRC[255:0] >> (IMM8[5:4] * 64))[63:0];\r\n TMP_DEST[255:192] <- (TMP_SRC[255:0] >> (IMM8[7:6] * 64))[63:0];\r\nIF VL >= 512\r\n TMP_DEST[319:256] <- (TMP_SRC[511:256] >> (IMM8[1:0] * 64))[63:0];\r\n TMP_DEST[383:320] <- (TMP_SRC[511:256] >> (IMM8[3:2] * 64))[63:0];\r\n TMP_DEST[447:384] <- (TMP_SRC[511:256] >> (IMM8[5:4] * 64))[63:0];\r\n TMP_DEST[511:448] <- (TMP_SRC[511:256] >> (IMM8[7:6] * 64))[63:0];\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0 ;zeroing-masking\r\n FI;\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPERMQ (EVEX - vector control forms)\r\n(KL, VL) = (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN TMP_SRC2[i+63:i] <- SRC2[63:0];\r\n ELSE TMP_SRC2[i+63:i] <- SRC2[i+63:i];\r\n FI;\r\nENDFOR;\r\nIF VL = 256\r\n TMP_DEST[63:0] <- (TMP_SRC2[255:0] >> (SRC1[1:0] * 64))[63:0];\r\n TMP_DEST[127:64] <- (TMP_SRC2[255:0] >> (SRC1[65:64] * 64))[63:0];\r\n TMP_DEST[191:128] <- (TMP_SRC2[255:0] >> (SRC1[129:128] * 64))[63:0];\r\n TMP_DEST[255:192] <- (TMP_SRC2[255:0] >> (SRC1[193:192] * 64))[63:0];\r\nFI;\r\nIF VL = 512\r\n TMP_DEST[63:0] <- (TMP_SRC2[511:0] >> (SRC1[2:0] * 64))[63:0];\r\n TMP_DEST[127:64] <- (TMP_SRC2[511:0] >> (SRC1[66:64] * 64))[63:0];\r\n TMP_DEST[191:128] <- (TMP_SRC2[511:0] >> (SRC1[130:128] * 64))[63:0];\r\n TMP_DEST[255:192] <- (TMP_SRC2[511:0] >> (SRC1[194:192] * 64))[63:0];\r\n\r\n\r\n\r\n TMP_DEST[319:256] <- (TMP_SRC2[511:0] >> (SRC1[258:256] * 64))[63:0];\r\n TMP_DEST[383:320] <- (TMP_SRC2[511:0] >> (SRC1[322:320] * 64))[63:0];\r\n TMP_DEST[447:384] <- (TMP_SRC2[511:0] >> (SRC1[386:384] * 64))[63:0];\r\n TMP_DEST[511:448] <- (TMP_SRC2[511:0] >> (SRC1[450:448] * 64))[63:0];\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0 ;zeroing-masking\r\n FI;\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPERMQ (VEX.256 encoded version)\r\nDEST[63:0] <-(SRC[255:0] >> (IMM8[1:0] * 64))[63:0];\r\nDEST[127:64] <-(SRC[255:0] >> (IMM8[3:2] * 64))[63:0];\r\nDEST[191:128] <-(SRC[255:0] >> (IMM8[5:4] * 64))[63:0];\r\nDEST[255:192] <-(SRC[255:0] >> (IMM8[7:6] * 64))[63:0];\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPERMQ __m512i _mm512_permutex_epi64( __m512i a, int imm);\r\nVPERMQ __m512i _mm512_mask_permutex_epi64(__m512i s, __mmask8 k, __m512i a, int imm);\r\nVPERMQ __m512i _mm512_maskz_permutex_epi64( __mmask8 k, __m512i a, int imm);\r\nVPERMQ __m512i _mm512_permutexvar_epi64( __m512i a, __m512i b);\r\nVPERMQ __m512i _mm512_mask_permutexvar_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);\r\nVPERMQ __m512i _mm512_maskz_permutexvar_epi64( __mmask8 k, __m512i a, __m512i b);\r\nVPERMQ __m256i _mm256_permutex_epi64( __m256i a, int imm);\r\nVPERMQ __m256i _mm256_mask_permutex_epi64(__m256i s, __mmask8 k, __m256i a, int imm);\r\nVPERMQ __m256i _mm256_maskz_permutex_epi64( __mmask8 k, __m256i a, int imm);\r\nVPERMQ __m256i _mm256_permutexvar_epi64( __m256i a, __m256i b);\r\nVPERMQ __m256i _mm256_mask_permutexvar_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);\r\nVPERMQ __m256i _mm256_maskz_permutexvar_epi64( __mmask8 k, __m256i a, __m256i b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4; additionally\r\n#UD If VEX.L = 0.\r\n If VEX.vvvv != 1111B.\r\nEVEX-encoded instruction, see Exceptions Type E4NF.\r\n#UD If encoded with EVEX.128.\r\n If EVEX.vvvv != 1111B and with imm8.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPERMQ"
},
{
"description": "-R:VPERMD",
"mnem": "VPERMW"
},
{
"description": "VPEXPANDD-Load Sparse Packed Doubleword Integer Values from Dense Memory / Register\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F38.W0 89 /r T1S V/V AVX512VL Expand packed double-word integer values from\r\n VPEXPANDD xmm1 {k1}{z}, AVX512F xmm2/m128 to xmm1 using writemask k1.\r\n xmm2/m128\r\n EVEX.256.66.0F38.W0 89 /r T1S V/V AVX512VL Expand packed double-word integer values from\r\n VPEXPANDD ymm1 {k1}{z}, AVX512F ymm2/m256 to ymm1 using writemask k1.\r\n ymm2/m256\r\n EVEX.512.66.0F38.W0 89 /r T1S V/V AVX512F Expand packed double-word integer values from\r\n VPEXPANDD zmm1 {k1}{z}, zmm2/m512 to zmm1 using writemask k1.\r\n zmm2/m512\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nExpand (load) up to 16 contiguous doubleword integer values of the input vector in the source operand (the second\r\noperand) to sparse elements in the destination operand (the first operand), selected by the writemask k1. The\r\ndestination operand is a ZMM register, the source operand can be a ZMM register or memory location.\r\nThe input vector starts from the lowest element in the source operand. The opmask register k1 selects the destina-\r\ntion elements (a partial vector or sparse elements if less than 8 elements) to be replaced by the ascending\r\nelements in the input vector. Destination elements not selected by the writemask k1 are either unmodified or\r\nzeroed, depending on EVEX.z.\r\nNote: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\nNote that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element\r\ninstead of the size of the full vector.\r\n\r\nOperation\r\nVPEXPANDD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nk<-0\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n DEST[i+31:i] <- SRC[k+31:k];\r\n k <- k + 32\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPEXPANDD __m512i _mm512_mask_expandloadu_epi32(__m512i s, __mmask16 k, void * a);\r\nVPEXPANDD __m512i _mm512_maskz_expandloadu_epi32( __mmask16 k, void * a);\r\nVPEXPANDD __m512i _mm512_mask_expand_epi32(__m512i s, __mmask16 k, __m512i a);\r\nVPEXPANDD __m512i _mm512_maskz_expand_epi32( __mmask16 k, __m512i a);\r\nVPEXPANDD __m256i _mm256_mask_expandloadu_epi32(__m256i s, __mmask8 k, void * a);\r\nVPEXPANDD __m256i _mm256_maskz_expandloadu_epi32( __mmask8 k, void * a);\r\nVPEXPANDD __m256i _mm256_mask_expand_epi32(__m256i s, __mmask8 k, __m256i a);\r\nVPEXPANDD __m256i _mm256_maskz_expand_epi32( __mmask8 k, __m256i a);\r\nVPEXPANDD __m128i _mm_mask_expandloadu_epi32(__m128i s, __mmask8 k, void * a);\r\nVPEXPANDD __m128i _mm_maskz_expandloadu_epi32( __mmask8 k, void * a);\r\nVPEXPANDD __m128i _mm_mask_expand_epi32(__m128i s, __mmask8 k, __m128i a);\r\nVPEXPANDD __m128i _mm_maskz_expand_epi32( __mmask8 k, __m128i a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nEVEX-encoded instruction, see Exceptions Type E4.nb.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPEXPANDD"
},
{
"description": "VPEXPANDQ-Load Sparse Packed Quadword Integer Values from Dense Memory / Register\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F38.W1 89 /r T1S V/V AVX512VL Expand packed quad-word integer values from\r\n VPEXPANDQ xmm1 {k1}{z}, xmm2/m128 AVX512F xmm2/m128 to xmm1 using writemask k1.\r\n EVEX.256.66.0F38.W1 89 /r T1S V/V AVX512VL Expand packed quad-word integer values from\r\n VPEXPANDQ ymm1 {k1}{z}, ymm2/m256 AVX512F ymm2/m256 to ymm1 using writemask k1.\r\n EVEX.512.66.0F38.W1 89 /r T1S V/V AVX512F Expand packed quad-word integer values from\r\n VPEXPANDQ zmm1 {k1}{z}, zmm2/m512 zmm2/m512 to zmm1 using writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nExpand (load) up to 8 quadword integer values from the source operand (the second operand) to sparse elements\r\nin the destination operand (the first operand), selected by the writemask k1. The destination operand is a ZMM\r\nregister, the source operand can be a ZMM register or memory location.\r\nThe input vector starts from the lowest element in the source operand. The opmask register k1 selects the destina-\r\ntion elements (a partial vector or sparse elements if less than 8 elements) to be replaced by the ascending\r\nelements in the input vector. Destination elements not selected by the writemask k1 are either unmodified or\r\nzeroed, depending on EVEX.z.\r\nNote: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\nNote that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element\r\ninstead of the size of the full vector.\r\n\r\nOperation\r\nVPEXPANDQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nk<-0\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n DEST[i+63:i] <- SRC[k+63:k];\r\n k <- k + 64\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPEXPANDQ __m512i _mm512_mask_expandloadu_epi64(__m512i s, __mmask8 k, void * a);\r\nVPEXPANDQ __m512i _mm512_maskz_expandloadu_epi64( __mmask8 k, void * a);\r\nVPEXPANDQ __m512i _mm512_mask_expand_epi64(__m512i s, __mmask8 k, __m512i a);\r\nVPEXPANDQ __m512i _mm512_maskz_expand_epi64( __mmask8 k, __m512i a);\r\nVPEXPANDQ __m256i _mm256_mask_expandloadu_epi64(__m256i s, __mmask8 k, void * a);\r\nVPEXPANDQ __m256i _mm256_maskz_expandloadu_epi64( __mmask8 k, void * a);\r\nVPEXPANDQ __m256i _mm256_mask_expand_epi64(__m256i s, __mmask8 k, __m256i a);\r\nVPEXPANDQ __m256i _mm256_maskz_expand_epi64( __mmask8 k, __m256i a);\r\nVPEXPANDQ __m128i _mm_mask_expandloadu_epi64(__m128i s, __mmask8 k, void * a);\r\nVPEXPANDQ __m128i _mm_maskz_expandloadu_epi64( __mmask8 k, void * a);\r\nVPEXPANDQ __m128i _mm_mask_expand_epi64(__m128i s, __mmask8 k, __m128i a);\r\nVPEXPANDQ __m128i _mm_maskz_expand_epi64( __mmask8 k, __m128i a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nEVEX-encoded instruction, see Exceptions Type E4.nb.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPEXPANDQ"
},
{
"description": "VPGATHERDD/VPGATHERQD - Gather Packed Dword Values Using Signed Dword/Qword\r\nIndices\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En -bit Feature\r\n Mode Flag\r\n VEX.DDS.128.66.0F38.W0 90 /r RMV V/V AVX2 Using dword indices specified in vm32x, gather dword val-\r\n VPGATHERDD xmm1, vm32x, xmm2 ues from memory conditioned on mask specified by\r\n xmm2. Conditionally gathered elements are merged into\r\n xmm1.\r\n VEX.DDS.128.66.0F38.W0 91 /r RMV V/V AVX2 Using qword indices specified in vm64x, gather dword val-\r\n VPGATHERQD xmm1, vm64x, xmm2 ues from memory conditioned on mask specified by\r\n xmm2. Conditionally gathered elements are merged into\r\n xmm1.\r\n VEX.DDS.256.66.0F38.W0 90 /r RMV V/V AVX2 Using dword indices specified in vm32y, gather dword\r\n VPGATHERDD ymm1, vm32y, ymm2 from memory conditioned on mask specified by ymm2.\r\n Conditionally gathered elements are merged into ymm1.\r\n\r\n VEX.DDS.256.66.0F38.W0 91 /r RMV V/V AVX2 Using qword indices specified in vm64y, gather dword val-\r\n VPGATHERQD xmm1, vm64y, xmm2 ues from memory conditioned on mask specified by\r\n xmm2. Conditionally gathered elements are merged into\r\n xmm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RMV ModRM:reg (r,w) BaseReg (R): VSIB:base, VEX.vvvv (r, w) NA\r\n VectorReg(R): VSIB:index\r\n\r\nDescription\r\nThe instruction conditionally loads up to 4 or 8 dword values from memory addresses specified by the memory\r\noperand (the second operand) and using dword indices. The memory operand uses the VSIB form of the SIB byte\r\nto specify a general purpose register operand as the common base, a vector register for an array of indices relative\r\nto the base and a constant scale factor.\r\nThe mask operand (the third operand) specifies the conditional load operation from each memory address and the\r\ncorresponding update of each data element of the destination operand (the first operand). Conditionality is speci-\r\nfied by the most significant bit of each data element of the mask register. If an element's mask bit is not set, the\r\ncorresponding element of the destination register is left unchanged. The width of data element in the destination\r\nregister and mask register are identical. The entire mask register will be set to zero by this instruction unless the\r\ninstruction causes an exception.\r\nUsing qword indices, the instruction conditionally loads up to 2 or 4 qword values from the VSIB addressing\r\nmemory operand, and updates the lower half of the destination register. The upper 128 or 256 bits of the destina-\r\ntion register are zero'ed with qword indices.\r\nThis instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception\r\nis triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination\r\nregister and the mask operand are partially updated; those elements that have been gathered are placed into the\r\ndestination register and have their mask bits set to zero. If any traps or interrupts are pending from already gath-\r\nered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction\r\nbreakpoint is not re-triggered when the instruction is continued.\r\nIf the data size and index size are different, part of the destination register and part of the mask register do not\r\ncorrespond to any elements being gathered. This instruction sets those parts to zero. It may do this to one or both\r\nof those registers even if the instruction triggers an exception, and even if the instruction triggers the exception\r\nbefore gathering any elements.\r\nVEX.128 version: For dword indices, the instruction will gather four dword values. For qword indices, the instruc-\r\ntion will gather two values and zeroes the upper 64 bits of the destination.\r\n\r\n\r\n\r\nVEX.256 version: For dword indices, the instruction will gather eight dword values. For qword indices, the instruc-\r\ntion will gather four values and zeroes the upper 128 bits of the destination.\r\nNote that:\r\n. If any pair of the index, mask, or destination registers are the same, this instruction results a UD fault.\r\n. The values may be read from memory in any order. Memory ordering with other instructions follows the Intel-\r\n 64 memory-ordering model.\r\n. Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all\r\n elements closer to the LSB of the destination will be completed (and non-faulting). Individual elements closer\r\n to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered in the\r\n conventional order.\r\n. Elements may be gathered in any order, but faults must be delivered in a right-to-left order; thus, elements to\r\n the left of a faulting one may be gathered before the fault is delivered. A given implementation of this\r\n instruction is repeatable - given the same input values and architectural state, the same set of elements to the\r\n left of the faulting one will be gathered.\r\n. This instruction does not perform AC checks, and so will never deliver an AC fault.\r\n. This instruction will cause a #UD if the address size attribute is 16-bit.\r\n. This instruction will cause a #UD if the memory operand is encoded without the SIB byte.\r\n. This instruction should not be used to access memory mapped I/O as the ordering of the individual loads it does\r\n is implementation specific, and some implementations may use loads larger than the data element size or load\r\n elements an indeterminate number of times.\r\n. The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-\r\n bit mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address\r\n bits are ignored.\r\n\r\nOperation\r\nDEST <- SRC1;\r\nBASE_ADDR: base register encoded in VSIB addressing;\r\nVINDEX: the vector index register encoded by VSIB addressing;\r\nSCALE: scale factor encoded by SIB:[7:6];\r\nDISP: optional 1, 4 byte displacement;\r\nMASK <- SRC3;\r\n\r\nVPGATHERDD (VEX.128 version)\r\nFOR j<- 0 to 3\r\n i <- j * 32;\r\n IF MASK[31+i] THEN\r\n MASK[i +31:i] <- FFFFFFFFH; // extend from most significant bit\r\n ELSE\r\n MASK[i +31:i] <- 0;\r\n FI;\r\nENDFOR\r\nMASK[VLMAX-1:128] <- 0;\r\nFOR j<- 0 to 3\r\n i <- j * 32;\r\n DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX[i+31:i])*SCALE + DISP;\r\n IF MASK[31+i] THEN\r\n DEST[i +31:i] <- FETCH_32BITS(DATA_ADDR); // a fault exits the instruction\r\n FI;\r\n MASK[i +31:i] <- 0;\r\nENDFOR\r\nDEST[VLMAX-1:128] <- 0;\r\n(non-masked elements of the mask register have the content of respective element cleared)\r\n\r\n\r\n\r\nVPGATHERQD (VEX.128 version)\r\nFOR j<- 0 to 3\r\n i <- j * 32;\r\n IF MASK[31+i] THEN\r\n MASK[i +31:i] <- FFFFFFFFH; // extend from most significant bit\r\n ELSE\r\n MASK[i +31:i] <- 0;\r\n FI;\r\nENDFOR\r\nMASK[VLMAX-1:128] <- 0;\r\nFOR j<- 0 to 1\r\n k <- j * 64;\r\n i <- j * 32;\r\n DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[k+63:k])*SCALE + DISP;\r\n IF MASK[31+i] THEN\r\n DEST[i +31:i] <- FETCH_32BITS(DATA_ADDR); // a fault exits the instruction\r\n FI;\r\n MASK[i +31:i] <- 0;\r\nENDFOR\r\nMASK[127:64] <- 0;\r\nDEST[VLMAX-1:64] <- 0;\r\n(non-masked elements of the mask register have the content of respective element cleared)\r\n\r\nVPGATHERDD (VEX.256 version)\r\nFOR j<- 0 to 7\r\n i <- j * 32;\r\n IF MASK[31+i] THEN\r\n MASK[i +31:i] <- FFFFFFFFH; // extend from most significant bit\r\n ELSE\r\n MASK[i +31:i] <- 0;\r\n FI;\r\nENDFOR\r\nFOR j<- 0 to 7\r\n i <- j * 32;\r\n DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[i+31:i])*SCALE + DISP;\r\n IF MASK[31+i] THEN\r\n DEST[i +31:i] <- FETCH_32BITS(DATA_ADDR); // a fault exits the instruction\r\n FI;\r\n MASK[i +31:i] <- 0;\r\nENDFOR\r\n(non-masked elements of the mask register have the content of respective element cleared)\r\n\r\n\r\n\r\n\r\n\r\nVPGATHERQD (VEX.256 version)\r\nFOR j<- 0 to 7\r\n i <- j * 32;\r\n IF MASK[31+i] THEN\r\n MASK[i +31:i] <- FFFFFFFFH; // extend from most significant bit\r\n ELSE\r\n MASK[i +31:i] <- 0;\r\n FI;\r\nENDFOR\r\nFOR j<- 0 to 3\r\n k <- j * 64;\r\n i <- j * 32;\r\n DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[k+63:k])*SCALE + DISP;\r\n IF MASK[31+i] THEN\r\n DEST[i +31:i] <- FETCH_32BITS(DATA_ADDR); // a fault exits the instruction\r\n FI;\r\n MASK[i +31:i] <- 0;\r\nENDFOR\r\nMASK[VLMAX-1:128] <- 0;\r\nDEST[VLMAX-1:128] <- 0;\r\n(non-masked elements of the mask register have the content of respective element cleared)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPGATHERDD: __m128i _mm_i32gather_epi32 (int const * base, __m128i index, const int scale);\r\nVPGATHERDD: __m128i _mm_mask_i32gather_epi32 (__m128i src, int const * base, __m128i index, __m128i mask, const int scale);\r\nVPGATHERDD: __m256i _mm256_i32gather_epi32 ( int const * base, __m256i index, const int scale);\r\nVPGATHERDD: __m256i _mm256_mask_i32gather_epi32 (__m256i src, int const * base, __m256i index, __m256i mask, const int\r\nscale);\r\nVPGATHERQD: __m128i _mm_i64gather_epi32 (int const * base, __m128i index, const int scale);\r\nVPGATHERQD: __m128i _mm_mask_i64gather_epi32 (__m128i src, int const * base, __m128i index, __m128i mask, const int scale);\r\nVPGATHERQD: __m128i _mm256_i64gather_epi32 (int const * base, __m256i index, const int scale);\r\nVPGATHERQD: __m128i _mm256_mask_i64gather_epi32 (__m128i src, int const * base, __m256i index, __m128i mask, const int\r\nscale);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 12.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPGATHERDD"
},
{
"description": "VPGATHERDD/VPGATHERDQ-Gather Packed Dword, Packed Qword with Signed Dword Indices\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F38.W0 90 /vsib T1S V/V AVX512VL Using signed dword indices, gather dword values from\r\n VPGATHERDD xmm1 {k1}, vm32x AVX512F memory using writemask k1 for merging-masking.\r\n EVEX.256.66.0F38.W0 90 /vsib T1S V/V AVX512VL Using signed dword indices, gather dword values from\r\n VPGATHERDD ymm1 {k1}, vm32y AVX512F memory using writemask k1 for merging-masking.\r\n EVEX.512.66.0F38.W0 90 /vsib T1S V/V AVX512F Using signed dword indices, gather dword values from\r\n VPGATHERDD zmm1 {k1}, vm32z memory using writemask k1 for merging-masking.\r\n EVEX.128.66.0F38.W1 90 /vsib T1S V/V AVX512VL Using signed dword indices, gather quadword values from\r\n VPGATHERDQ xmm1 {k1}, vm32x AVX512F memory using writemask k1 for merging-masking.\r\n EVEX.256.66.0F38.W1 90 /vsib T1S V/V AVX512VL Using signed dword indices, gather quadword values from\r\n VPGATHERDQ ymm1 {k1}, vm32x AVX512F memory using writemask k1 for merging-masking.\r\n EVEX.512.66.0F38.W1 90 /vsib T1S V/V AVX512F Using signed dword indices, gather quadword values from\r\n VPGATHERDQ zmm1 {k1}, vm32y memory using writemask k1 for merging-masking.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n BaseReg (R): VSIB:base,\r\n T1S ModRM:reg (w) NA NA\r\n VectorReg(R): VSIB:index\r\n\r\nDescription\r\nA set of 16 or 8 doubleword/quadword memory locations pointed to by base address BASE_ADDR and index vector\r\nVINDEX with scale SCALE are gathered. The result is written into vector zmm1. The elements are specified via the\r\nVSIB (i.e., the index register is a zmm, holding packed indices). Elements will only be loaded if their corresponding\r\nmask bit is one. If an element's mask bit is not set, the corresponding element of the destination register (zmm1)\r\nis left unchanged. The entire mask register will be set to zero by this instruction unless it triggers an exception.\r\nThis instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception\r\nis triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination\r\nregister and the mask register (k1) are partially updated; those elements that have been gathered are placed into\r\nthe destination register and have their mask bits set to zero. If any traps or interrupts are pending from already\r\ngathered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruc-\r\ntion breakpoint is not re-triggered when the instruction is continued.\r\nIf the data element size is less than the index element size, the higher part of the destination register and the mask\r\nregister do not correspond to any elements being gathered. This instruction sets those higher parts to zero. It may\r\nupdate these unused elements to one or both of those registers even if the instruction triggers an exception, and\r\neven if the instruction triggers the exception before gathering any elements.\r\nNote that:\r\n. The values may be read from memory in any order. Memory ordering with other instructions follows the Intel-\r\n 64 memory-ordering model.\r\n. Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all\r\n elements closer to the LSB of the destination zmm will be completed (and non-faulting). Individual elements\r\n closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered\r\n in the conventional order.\r\n. Elements may be gathered in any order, but faults must be delivered in a right-to-left order; thus, elements to\r\n the left of a faulting one may be gathered before the fault is delivered. A given implementation of this\r\n instruction is repeatable - given the same input values and architectural state, the same set of elements to the\r\n left of the faulting one will be gathered.\r\n. This instruction does not perform AC checks, and so will never deliver an AC fault.\r\n. Not valid with 16-bit effective addresses. Will deliver a #UD fault.\r\n. These instructions do not accept zeroing-masking since the 0 values in k1 are used to determine completion.\r\n\r\n\r\nNote that the presence of VSIB byte is enforced in this instruction. Hence, the instruction will #UD fault if\r\nModRM.rm is different than 100b.\r\nThis instruction has the same disp8*N and alignment rules as for scalar instructions (Tuple 1).\r\nThe instruction will #UD fault if the destination vector zmm1 is the same as index vector VINDEX. The instruction\r\nwill #UD fault if the k0 mask register is specified.\r\nThe scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-bit\r\nmode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits are\r\nignored.\r\n\r\nOperation\r\nBASE_ADDR stands for the memory operand base address (a GPR); may not exist\r\nVINDEX stands for the memory operand vector of indices (a ZMM register)\r\nSCALE stands for the memory operand scalar (1, 2, 4 or 8)\r\nDISP is the optional 1, 2 or 4 byte displacement\r\n\r\nVPGATHERDD (EVEX encoded version)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j]\r\n THEN DEST[i+31:i] <- MEM[BASE_ADDR +\r\n SignExtend(VINDEX[i+31:i]) * SCALE + DISP]), 1)\r\n k1[j] <- 0\r\n ELSE *DEST[i+31:i] <- remains unchanged* ; Only merging masking is allowed\r\n FI;\r\nENDFOR\r\nk1[MAX_KL-1:KL] <- 0\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPGATHERDQ (EVEX encoded version)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n k <- j * 32\r\n IF k1[j]\r\n THEN DEST[i+63:i] <-\r\n MEM[BASE_ADDR + SignExtend(VINDEX[k+31:k]) * SCALE + DISP])\r\n k1[j] <- 0\r\n ELSE *DEST[i+63:i] <- remains unchanged* ; Only merging masking is allowed\r\n FI;\r\nENDFOR\r\nk1[MAX_KL-1:KL] <- 0\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPGATHERDD __m512i _mm512_i32gather_epi32( __m512i vdx, void * base, int scale);\r\nVPGATHERDD __m512i _mm512_mask_i32gather_epi32(__m512i s, __mmask16 k, __m512i vdx, void * base, int scale);\r\nVPGATHERDD __m256i _mm256_mmask_i32gather_epi32(__m256i s, __mmask8 k, __m256i vdx, void * base, int scale);\r\nVPGATHERDD __m128i _mm_mmask_i32gather_epi32(__m128i s, __mmask8 k, __m128i vdx, void * base, int scale);\r\nVPGATHERDQ __m512i _mm512_i32logather_epi64( __m256i vdx, void * base, int scale);\r\nVPGATHERDQ __m512i _mm512_mask_i32logather_epi64(__m512i s, __mmask8 k, __m256i vdx, void * base, int scale);\r\nVPGATHERDQ __m256i _mm256_mmask_i32logather_epi64(__m256i s, __mmask8 k, __m128i vdx, void * base, int scale);\r\nVPGATHERDQ __m128i _mm_mmask_i32gather_epi64(__m128i s, __mmask8 k, __m128i vdx, void * base, int scale);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type E12.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPGATHERDD"
},
{
"description": "-R:VPGATHERDD",
"mnem": "VPGATHERDQ"
},
{
"description": "VPGATHERDQ/VPGATHERQQ - Gather Packed Qword Values Using Signed Dword/Qword\r\nIndices\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En -bit Feature\r\n Mode Flag\r\n VEX.DDS.128.66.0F38.W1 90 /r RMV V/V AVX2 Using dword indices specified in vm32x, gather qword val-\r\n VPGATHERDQ xmm1, vm32x, xmm2 ues from memory conditioned on mask specified by\r\n xmm2. Conditionally gathered elements are merged into\r\n xmm1.\r\n VEX.DDS.128.66.0F38.W1 91 /r RMV V/V AVX2 Using qword indices specified in vm64x, gather qword val-\r\n VPGATHERQQ xmm1, vm64x, xmm2 ues from memory conditioned on mask specified by\r\n xmm2. Conditionally gathered elements are merged into\r\n xmm1.\r\n VEX.DDS.256.66.0F38.W1 90 /r RMV V/V AVX2 Using dword indices specified in vm32x, gather qword val-\r\n VPGATHERDQ ymm1, vm32x, ymm2 ues from memory conditioned on mask specified by\r\n ymm2. Conditionally gathered elements are merged into\r\n ymm1.\r\n VEX.DDS.256.66.0F38.W1 91 /r RMV V/V AVX2 Using qword indices specified in vm64y, gather qword val-\r\n VPGATHERQQ ymm1, vm64y, ymm2 ues from memory conditioned on mask specified by\r\n ymm2. Conditionally gathered elements are merged into\r\n ymm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n A ModRM:reg (r,w) BaseReg (R): VSIB:base, VEX.vvvv (r, w) NA\r\n VectorReg(R): VSIB:index\r\n\r\nDescription\r\nThe instruction conditionally loads up to 2 or 4 qword values from memory addresses specified by the memory\r\noperand (the second operand) and using qword indices. The memory operand uses the VSIB form of the SIB byte\r\nto specify a general purpose register operand as the common base, a vector register for an array of indices relative\r\nto the base and a constant scale factor.\r\nThe mask operand (the third operand) specifies the conditional load operation from each memory address and the\r\ncorresponding update of each data element of the destination operand (the first operand). Conditionality is speci-\r\nfied by the most significant bit of each data element of the mask register. If an element's mask bit is not set, the\r\ncorresponding element of the destination register is left unchanged. The width of data element in the destination\r\nregister and mask register are identical. The entire mask register will be set to zero by this instruction unless the\r\ninstruction causes an exception.\r\nUsing dword indices in the lower half of the mask register, the instruction conditionally loads up to 2 or 4 qword\r\nvalues from the VSIB addressing memory operand, and updates the destination register.\r\nThis instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception\r\nis triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination\r\nregister and the mask operand are partially updated; those elements that have been gathered are placed into the\r\ndestination register and have their mask bits set to zero. If any traps or interrupts are pending from already gath-\r\nered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction\r\nbreakpoint is not re-triggered when the instruction is continued.\r\nIf the data size and index size are different, part of the destination register and part of the mask register do not\r\ncorrespond to any elements being gathered. This instruction sets those parts to zero. It may do this to one or both\r\nof those registers even if the instruction triggers an exception, and even if the instruction triggers the exception\r\nbefore gathering any elements.\r\nVEX.128 version: The instruction will gather two qword values. For dword indices, only the lower two indices in the\r\nvector index register are used.\r\n\r\n\r\n\r\n\r\nVEX.256 version: The instruction will gather four qword values. For dword indices, only the lower four indices in\r\nthe vector index register are used.\r\nNote that:\r\n. If any pair of the index, mask, or destination registers are the same, this instruction results a UD fault.\r\n. The values may be read from memory in any order. Memory ordering with other instructions follows the Intel-\r\n 64 memory-ordering model.\r\n. Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all\r\n elements closer to the LSB of the destination will be completed (and non-faulting). Individual elements closer\r\n to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered in the\r\n conventional order.\r\n. Elements may be gathered in any order, but faults must be delivered in a right-to-left order; thus, elements to\r\n the left of a faulting one may be gathered before the fault is delivered. A given implementation of this\r\n instruction is repeatable - given the same input values and architectural state, the same set of elements to the\r\n left of the faulting one will be gathered.\r\n. This instruction does not perform AC checks, and so will never deliver an AC fault.\r\n. This instruction will cause a #UD if the address size attribute is 16-bit.\r\n. This instruction will cause a #UD if the memory operand is encoded without the SIB byte.\r\n. This instruction should not be used to access memory mapped I/O as the ordering of the individual loads it does\r\n is implementation specific, and some implementations may use loads larger than the data element size or load\r\n elements an indeterminate number of times.\r\n. The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-\r\n bit mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address\r\n bits are ignored.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nDEST <- SRC1;\r\nBASE_ADDR: base register encoded in VSIB addressing;\r\nVINDEX: the vector index register encoded by VSIB addressing;\r\nSCALE: scale factor encoded by SIB:[7:6];\r\nDISP: optional 1, 4 byte displacement;\r\nMASK <- SRC3;\r\n\r\nVPGATHERDQ (VEX.128 version)\r\nFOR j<- 0 to 1\r\n i <- j * 64;\r\n IF MASK[63+i] THEN\r\n MASK[i +63:i] <- FFFFFFFF_FFFFFFFFH; // extend from most significant bit\r\n ELSE\r\n MASK[i +63:i] <- 0;\r\n FI;\r\nENDFOR\r\nFOR j<- 0 to 1\r\n k <- j * 32;\r\n i <- j * 64;\r\n DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX[k+31:k])*SCALE + DISP;\r\n IF MASK[63+i] THEN\r\n DEST[i +63:i] <- FETCH_64BITS(DATA_ADDR); // a fault exits the instruction\r\n FI;\r\n MASK[i +63:i] <- 0;\r\nENDFOR\r\nMASK[VLMAX-1:128] <- 0;\r\nDEST[VLMAX-1:128] <- 0;\r\n(non-masked elements of the mask register have the content of respective element cleared)\r\n\r\nVPGATHERQQ (VEX.128 version)\r\nFOR j<- 0 to 1\r\n i <- j * 64;\r\n IF MASK[63+i] THEN\r\n MASK[i +63:i] <- FFFFFFFF_FFFFFFFFH; // extend from most significant bit\r\n ELSE\r\n MASK[i +63:i] <- 0;\r\n FI;\r\nENDFOR\r\nFOR j<- 0 to 1\r\n i <-j * 64;\r\n DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[i+63:i])*SCALE + DISP;\r\n IF MASK[63+i] THEN\r\n DEST[i +63:i] <- FETCH_64BITS(DATA_ADDR); // a fault exits the instruction\r\n FI;\r\n MASK[i +63:i] <- 0;\r\nENDFOR\r\nMASK[VLMAX-1:128] <- 0;\r\nDEST[VLMAX-1:128] <- 0;\r\n(non-masked elements of the mask register have the content of respective element cleared)\r\n\r\n\r\n\r\n\r\n\r\nVPGATHERQQ (VEX.256 version)\r\nFOR j<- 0 to 3\r\n i <- j * 64;\r\n IF MASK[63+i] THEN\r\n MASK[i +63:i] <- FFFFFFFF_FFFFFFFFH; // extend from most significant bit\r\n ELSE\r\n MASK[i +63:i] <- 0;\r\n FI;\r\nENDFOR\r\nFOR j<- 0 to 3\r\n i <- j * 64;\r\n DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[i+63:i])*SCALE + DISP;\r\n IF MASK[63+i] THEN\r\n DEST[i +63:i] <- FETCH_64BITS(DATA_ADDR); // a fault exits the instruction\r\n FI;\r\n MASK[i +63:i] <- 0;\r\nENDFOR\r\n(non-masked elements of the mask register have the content of respective element cleared)\r\n\r\nVPGATHERDQ (VEX.256 version)\r\nFOR j<- 0 to 3\r\n i <- j * 64;\r\n IF MASK[63+i] THEN\r\n MASK[i +63:i] <- FFFFFFFF_FFFFFFFFH; // extend from most significant bit\r\n ELSE\r\n MASK[i +63:i] <- 0;\r\n FI;\r\nENDFOR\r\nFOR j<- 0 to 3\r\n k <- j * 32;\r\n i <- j * 64;\r\n DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[k+31:k])*SCALE + DISP;\r\n IF MASK[63+i] THEN\r\n DEST[i +63:i] <- FETCH_64BITS(DATA_ADDR); // a fault exits the instruction\r\n FI;\r\n MASK[i +63:i] <- 0;\r\nENDFOR\r\n(non-masked elements of the mask register have the content of respective element cleared)\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPGATHERDQ: __m128i _mm_i32gather_epi64 (__int64 const * base, __m128i index, const int scale);\r\nVPGATHERDQ: __m128i _mm_mask_i32gather_epi64 (__m128i src, __int64 const * base, __m128i index, __m128i mask, const int\r\nscale);\r\nVPGATHERDQ: __m256i _mm256_i32gather_epi64 (__int64 const * base, __m128i index, const int scale);\r\nVPGATHERDQ: __m256i _mm256_mask_i32gather_epi64 (__m256i src, __int64 const * base, __m128i index, __m256i mask, const\r\nint scale);\r\nVPGATHERQQ: __m128i _mm_i64gather_epi64 (__int64 const * base, __m128i index, const int scale);\r\nVPGATHERQQ: __m128i _mm_mask_i64gather_epi64 (__m128i src, __int64 const * base, __m128i index, __m128i mask, const int\r\nscale);\r\nVPGATHERQQ: __m256i _mm256_i64gather_epi64 __(int64 const * base, __m256i index, const int scale);\r\nVPGATHERQQ: __m256i _mm256_mask_i64gather_epi64 (__m256i src, __int64 const * base, __m256i index, __m256i mask, const\r\nint scale);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 12.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPGATHERDQ"
},
{
"description": "-R:VPGATHERDD",
"mnem": "VPGATHERQD"
},
{
"description": "VPGATHERQD/VPGATHERQQ-Gather Packed Dword, Packed Qword with Signed Qword Indices\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F38.W0 91 /vsib T1S V/V AVX512VL Using signed qword indices, gather dword values from\r\n VPGATHERQD xmm1 {k1}, vm64x AVX512F memory using writemask k1 for merging-masking.\r\n EVEX.256.66.0F38.W0 91 /vsib T1S V/V AVX512VL Using signed qword indices, gather dword values from\r\n VPGATHERQD xmm1 {k1}, vm64y AVX512F memory using writemask k1 for merging-masking.\r\n EVEX.512.66.0F38.W0 91 /vsib T1S V/V AVX512F Using signed qword indices, gather dword values from\r\n VPGATHERQD ymm1 {k1}, vm64z memory using writemask k1 for merging-masking.\r\n EVEX.128.66.0F38.W1 91 /vsib T1S V/V AVX512VL Using signed qword indices, gather quadword values from\r\n VPGATHERQQ xmm1 {k1}, vm64x AVX512F memory using writemask k1 for merging-masking.\r\n EVEX.256.66.0F38.W1 91 /vsib T1S V/V AVX512VL Using signed qword indices, gather quadword values from\r\n VPGATHERQQ ymm1 {k1}, vm64y AVX512F memory using writemask k1 for merging-masking.\r\n EVEX.512.66.0F38.W1 91 /vsib T1S V/V AVX512F Using signed qword indices, gather quadword values from\r\n VPGATHERQQ zmm1 {k1}, vm64z memory using writemask k1 for merging-masking.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n BaseReg (R): VSIB:base,\r\n T1S ModRM:reg (w) NA NA\r\n VectorReg(R): VSIB:index\r\n\r\nDescription\r\nA set of 8 doubleword/quadword memory locations pointed to by base address BASE_ADDR and index vector\r\nVINDEX with scale SCALE are gathered. The result is written into a vector register. The elements are specified via\r\nthe VSIB (i.e., the index register is a vector register, holding packed indices). Elements will only be loaded if their\r\ncorresponding mask bit is one. If an element's mask bit is not set, the corresponding element of the destination\r\nregister is left unchanged. The entire mask register will be set to zero by this instruction unless it triggers an excep-\r\ntion.\r\nThis instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception\r\nis triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination\r\nregister and the mask register (k1) are partially updated; those elements that have been gathered are placed into\r\nthe destination register and have their mask bits set to zero. If any traps or interrupts are pending from already\r\ngathered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruc-\r\ntion breakpoint is not re-triggered when the instruction is continued.\r\nIf the data element size is less than the index element size, the higher part of the destination register and the mask\r\nregister do not correspond to any elements being gathered. This instruction sets those higher parts to zero. It may\r\nupdate these unused elements to one or both of those registers even if the instruction triggers an exception, and\r\neven if the instruction triggers the exception before gathering any elements.\r\nNote that:\r\n. The values may be read from memory in any order. Memory ordering with other instructions follows the Intel-\r\n 64 memory-ordering model.\r\n. Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all\r\n elements closer to the LSB of the destination zmm will be completed (and non-faulting). Individual elements\r\n closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered\r\n in the conventional order.\r\n. Elements may be gathered in any order, but faults must be delivered in a right-to-left order; thus, elements to\r\n the left of a faulting one may be gathered before the fault is delivered. A given implementation of this\r\n instruction is repeatable - given the same input values and architectural state, the same set of elements to the\r\n left of the faulting one will be gathered.\r\n\r\n\r\n\r\n\r\n\r\n. This instruction does not perform AC checks, and so will never deliver an AC fault.\r\n. Not valid with 16-bit effective addresses. Will deliver a #UD fault.\r\n. These instructions do not accept zeroing-masking since the 0 values in k1 are used to determine completion.\r\nNote that the presence of VSIB byte is enforced in this instruction. Hence, the instruction will #UD fault if\r\nModRM.rm is different than 100b.\r\nThis instruction has the same disp8*N and alignment rules as for scalar instructions (Tuple 1).\r\nThe instruction will #UD fault if the destination vector zmm1 is the same as index vector VINDEX. The instruction\r\nwill #UD fault if the k0 mask register is specified.\r\nThe scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-bit\r\nmode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits are\r\nignored.\r\n\r\nOperation\r\nBASE_ADDR stands for the memory operand base address (a GPR); may not exist\r\nVINDEX stands for the memory operand vector of indices (a ZMM register)\r\nSCALE stands for the memory operand scalar (1, 2, 4 or 8)\r\nDISP is the optional 1, 2 or 4 byte displacement\r\n\r\nVPGATHERQD (EVEX encoded version)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n k <- j * 64\r\n IF k1[j]\r\n THEN DEST[i+31:i] <- MEM[BASE_ADDR + (VINDEX[k+63:k]) * SCALE + DISP]), 1)\r\n k1[j] <- 0\r\n ELSE *DEST[i+31:i] <- remains unchanged* ; Only merging masking is allowed\r\n FI;\r\nENDFOR\r\nk1[MAX_KL-1:KL] <- 0\r\nDEST[MAX_VL-1:VL/2] <- 0\r\n\r\nVPGATHERQQ (EVEX encoded version)\r\n(KL, VL) = (2, 64), (4, 128), (8, 256)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j]\r\n THEN DEST[i+63:i] <-\r\n MEM[BASE_ADDR + (VINDEX[i+63:i]) * SCALE + DISP])\r\n k1[j] <- 0\r\n ELSE *DEST[i+63:i] <- remains unchanged* ; Only merging masking is allowed\r\n FI;\r\nENDFOR\r\nk1[MAX_KL-1:KL] <- 0\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPGATHERQD __m256i _mm512_i64gather_epi32(__m512i vdx, void * base, int scale);\r\nVPGATHERQD __m256i _mm512_mask_i64gather_epi32lo(__m256i s, __mmask8 k, __m512i vdx, void * base, int scale);\r\nVPGATHERQD __m128i _mm256_mask_i64gather_epi32lo(__m128i s, __mmask8 k, __m256i vdx, void * base, int scale);\r\nVPGATHERQD __m128i _mm_mask_i64gather_epi32(__m128i s, __mmask8 k, __m128i vdx, void * base, int scale);\r\nVPGATHERQQ __m512i _mm512_i64gather_epi64( __m512i vdx, void * base, int scale);\r\nVPGATHERQQ __m512i _mm512_mask_i64gather_epi64(__m512i s, __mmask8 k, __m512i vdx, void * base, int scale);\r\nVPGATHERQQ __m256i _mm256_mask_i64gather_epi64(__m256i s, __mmask8 k, __m256i vdx, void * base, int scale);\r\nVPGATHERQQ __m128i _mm_mask_i64gather_epi64(__m128i s, __mmask8 k, __m128i vdx, void * base, int scale);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type E12.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPGATHERQD"
},
{
"description": "-R:VPGATHERDQ",
"mnem": "VPGATHERQQ"
},
{
"description": "-R:VPGATHERQD",
"mnem": "VPGATHERQQ"
},
{
"description": "VPLZCNTD/VPLZCNTQ-Count the Number of Leading Zero Bits for Packed Dword, Packed Qword Values\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F38.W0 44 /r FV V/V AVX512VL Count the number of leading zero bits in each dword\r\n VPLZCNTD xmm1 {k1}{z}, AVX512CD element of xmm2/m128/m32bcst using writemask k1.\r\n xmm2/m128/m32bcst\r\n\r\n EVEX.256.66.0F38.W0 44 /r FV V/V AVX512VL Count the number of leading zero bits in each dword\r\n VPLZCNTD ymm1 {k1}{z}, AVX512CD element of ymm2/m256/m32bcst using writemask k1.\r\n ymm2/m256/m32bcst\r\n\r\n EVEX.512.66.0F38.W0 44 /r FV V/V AVX512CD Count the number of leading zero bits in each dword\r\n VPLZCNTD zmm1 {k1}{z}, element of zmm2/m512/m32bcst using writemask k1.\r\n zmm2/m512/m32bcst\r\n\r\n EVEX.128.66.0F38.W1 44 /r FV V/V AVX512VL Count the number of leading zero bits in each qword\r\n VPLZCNTQ xmm1 {k1}{z}, AVX512CD element of xmm2/m128/m64bcst using writemask k1.\r\n xmm2/m128/m64bcst\r\n\r\n EVEX.256.66.0F38.W1 44 /r FV V/V AVX512VL Count the number of leading zero bits in each qword\r\n VPLZCNTQ ymm1 {k1}{z}, AVX512CD element of ymm2/m256/m64bcst using writemask k1.\r\n ymm2/m256/m64bcst\r\n\r\n EVEX.512.66.0F38.W1 44 /r FV V/V AVX512CD Count the number of leading zero bits in each qword\r\n VPLZCNTQ zmm1 {k1}{z}, element of zmm2/m512/m64bcst using writemask k1.\r\n zmm2/m512/m64bcst\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nCounts the number of leading most significant zero bits in each dword or qword element of the source operand (the\r\nsecond operand) and stores the results in the destination register (the first operand) according to the writemask.\r\nIf an element is zero, the result for that element is the operand size of the element.\r\nEVEX.512 encoded version: The source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector\r\nbroadcasted from a 32/64-bit memory location. The destination operand is a ZMM register, conditionally updated\r\nusing writemask k1.\r\nEVEX.256 encoded version: The source operand is a YMM register, a 256-bit memory location, or a 256-bit vector\r\nbroadcasted from a 32/64-bit memory location. The destination operand is a YMM register, conditionally updated\r\nusing writemask k1.\r\nEVEX.128 encoded version: The source operand is a XMM register, a 128-bit memory location, or a 128-bit vector\r\nbroadcasted from a 32/64-bit memory location. The destination operand is a XMM register, conditionally updated\r\nusing writemask k1.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVPLZCNTD\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j*32\r\n IF MaskBit(j) OR *no writemask*\r\n THEN\r\n temp <- 32\r\n DEST[i+31:i] <- 0\r\n WHILE (temp > 0) AND (SRC[i+temp-1] = 0)\r\n DO\r\n temp <- temp - 1\r\n DEST[i+31:i] <- DEST[i+31:i] + 1\r\n OD\r\n ELSE\r\n IF *merging-masking*\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE DEST[i+31:i] <- 0\r\n FI\r\n FI\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPLZCNTQ\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j*64\r\n IF MaskBit(j) OR *no writemask*\r\n THEN\r\n temp <- 64\r\n DEST[i+63:i] <- 0\r\n WHILE (temp > 0) AND (SRC[i+temp-1] = 0)\r\n DO\r\n temp <- temp - 1\r\n DEST[i+63:i] <- DEST[i+63:i] + 1\r\n OD\r\n ELSE\r\n IF *merging-masking*\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE DEST[i+63:i] <- 0\r\n FI\r\n FI\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n\r\nVPLZCNTD __m512i _mm512_lzcnt_epi32(__m512i a);\r\nVPLZCNTD __m512i _mm512_mask_lzcnt_epi32(__m512i s, __mmask16 m, __m512i a);\r\nVPLZCNTD __m512i _mm512_maskz_lzcnt_epi32( __mmask16 m, __m512i a);\r\nVPLZCNTQ __m512i _mm512_lzcnt_epi64(__m512i a);\r\nVPLZCNTQ __m512i _mm512_mask_lzcnt_epi64(__m512i s, __mmask8 m, __m512i a);\r\nVPLZCNTQ __m512i _mm512_maskz_lzcnt_epi64(__mmask8 m, __m512i a);\r\nVPLZCNTD __m256i _mm256_lzcnt_epi32(__m256i a);\r\nVPLZCNTD __m256i _mm256_mask_lzcnt_epi32(__m256i s, __mmask8 m, __m256i a);\r\nVPLZCNTD __m256i _mm256_maskz_lzcnt_epi32( __mmask8 m, __m256i a);\r\nVPLZCNTQ __m256i _mm256_lzcnt_epi64(__m256i a);\r\nVPLZCNTQ __m256i _mm256_mask_lzcnt_epi64(__m256i s, __mmask8 m, __m256i a);\r\nVPLZCNTQ __m256i _mm256_maskz_lzcnt_epi64(__mmask8 m, __m256i a);\r\nVPLZCNTD __m128i _mm_lzcnt_epi32(__m128i a);\r\nVPLZCNTD __m128i _mm_mask_lzcnt_epi32(__m128i s, __mmask8 m, __m128i a);\r\nVPLZCNTD __m128i _mm_maskz_lzcnt_epi32( __mmask8 m, __m128i a);\r\nVPLZCNTQ __m128i _mm_lzcnt_epi64(__m128i a);\r\nVPLZCNTQ __m128i _mm_mask_lzcnt_epi64(__m128i s, __mmask8 m, __m128i a);\r\nVPLZCNTQ __m128i _mm_maskz_lzcnt_epi64(__mmask8 m, __m128i a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPLZCNTD"
},
{
"description": "-R:VPLZCNTD",
"mnem": "VPLZCNTQ"
},
{
"description": "VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En -bit Feature\r\n Mode Flag\r\n VEX.NDS.128.66.0F38.W0 8C /rVPMASK- RVM V/V AVX2 Conditionally load dword values from m128 using mask\r\n MOVD xmm1, xmm2, m128 in xmm2 and store in xmm1.\r\n VEX.NDS.256.66.0F38.W0 8C /r RVM V/V AVX2 Conditionally load dword values from m256 using mask\r\n VPMASKMOVD ymm1, ymm2, m256 in ymm2 and store in ymm1.\r\n VEX.NDS.128.66.0F38.W1 8C /r RVM V/V AVX2 Conditionally load qword values from m128 using mask\r\n VPMASKMOVQ xmm1, xmm2, m128 in xmm2 and store in xmm1.\r\n VEX.NDS.256.66.0F38.W1 8C /r RVM V/V AVX2 Conditionally load qword values from m256 using mask\r\n VPMASKMOVQ ymm1, ymm2, m256 in ymm2 and store in ymm1.\r\n VEX.NDS.128.66.0F38.W0 8E /r MVR V/V AVX2 Conditionally store dword values from xmm2 using\r\n VPMASKMOVD m128, xmm1, xmm2 mask in xmm1.\r\n VEX.NDS.256.66.0F38.W0 8E /r MVR V/V AVX2 Conditionally store dword values from ymm2 using\r\n VPMASKMOVD m256, ymm1, ymm2 mask in ymm1.\r\n VEX.NDS.128.66.0F38.W1 8E /r MVR V/V AVX2 Conditionally store qword values from xmm2 using\r\n VPMASKMOVQ m128, xmm1, xmm2 mask in xmm1.\r\n VEX.NDS.256.66.0F38.W1 8E /r MVR V/V AVX2 Conditionally store qword values from ymm2 using\r\n VPMASKMOVQ m256, ymm1, ymm2 mask in ymm1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n MVR ModRM:r/m (w) VEX.vvvv ModRM:reg (r) NA\r\n\r\nDescription\r\nConditionally moves packed data elements from the second source operand into the corresponding data element\r\nof the destination operand, depending on the mask bits associated with each data element. The mask bits are\r\nspecified in the first source operand.\r\nThe mask bit for each data element is the most significant bit of that element in the first source operand. If a mask\r\nis 1, the corresponding data element is copied from the second source operand to the destination operand. If the\r\nmask is 0, the corresponding data element is set to zero in the load form of these instructions, and unmodified in\r\nthe store form.\r\nThe second source operand is a memory address for the load form of these instructions. The destination operand\r\nis a memory address for the store form of these instructions. The other operands are either XMM registers (for\r\nVEX.128 version) or YMM registers (for VEX.256 version).\r\nFaults occur only due to mask-bit required memory accesses that caused the faults. Faults will not occur due to\r\nreferencing any memory location if the corresponding mask bit for that memory location is 0. For example, no\r\nfaults will be detected if the mask bits are all zero.\r\nUnlike previous MASKMOV instructions (MASKMOVQ and MASKMOVDQU), a nontemporal hint is not applied to\r\nthese instructions.\r\nInstruction behavior on alignment check reporting with mask bits of less than all 1s are the same as with mask bits\r\nof all 1s.\r\n\r\n\r\n\r\n\r\n\r\nVMASKMOV should not be used to access memory mapped I/O as the ordering of the individual loads or stores it\r\ndoes is implementation specific.\r\nIn cases where mask bits indicate data should not be loaded or stored paging A and D bits will be set in an imple-\r\nmentation dependent way. However, A and D bits are always set for pages where data is actually loaded/stored.\r\nNote: for load forms, the first source (the mask) is encoded in VEX.vvvv; the second source is encoded in rm_field,\r\nand the destination register is encoded in reg_field.\r\nNote: for store forms, the first source (the mask) is encoded in VEX.vvvv; the second source register is encoded in\r\nreg_field, and the destination memory location is encoded in rm_field.\r\n\r\nOperation\r\nVPMASKMOVD - 256-bit load\r\nDEST[31:0] <- IF (SRC1[31]) Load_32(mem) ELSE 0\r\nDEST[63:32] <- IF (SRC1[63]) Load_32(mem + 4) ELSE 0\r\nDEST[95:64] <- IF (SRC1[95]) Load_32(mem + 8) ELSE 0\r\nDEST[127:96] <- IF (SRC1[127]) Load_32(mem + 12) ELSE 0\r\nDEST[159:128] <- IF (SRC1[159]) Load_32(mem + 16) ELSE 0\r\nDEST[191:160] <- IF (SRC1[191]) Load_32(mem + 20) ELSE 0\r\nDEST[223:192] <- IF (SRC1[223]) Load_32(mem + 24) ELSE 0\r\nDEST[255:224] <- IF (SRC1[255]) Load_32(mem + 28) ELSE 0\r\n\r\nVPMASKMOVD -128-bit load\r\nDEST[31:0] <- IF (SRC1[31]) Load_32(mem) ELSE 0\r\nDEST[63:32] <- IF (SRC1[63]) Load_32(mem + 4) ELSE 0\r\nDEST[95:64] <- IF (SRC1[95]) Load_32(mem + 8) ELSE 0\r\nDEST[127:97] <- IF (SRC1[127]) Load_32(mem + 12) ELSE 0\r\nDEST[VLMAX-1:128] <- 0\r\n\r\nVPMASKMOVQ - 256-bit load\r\nDEST[63:0] <- IF (SRC1[63]) Load_64(mem) ELSE 0\r\nDEST[127:64] <- IF (SRC1[127]) Load_64(mem + 8) ELSE 0\r\nDEST[195:128] <- IF (SRC1[191]) Load_64(mem + 16) ELSE 0\r\nDEST[255:196] <- IF (SRC1[255]) Load_64(mem + 24) ELSE 0\r\n\r\nVPMASKMOVQ - 128-bit load\r\nDEST[63:0] <- IF (SRC1[63]) Load_64(mem) ELSE 0\r\nDEST[127:64] <- IF (SRC1[127]) Load_64(mem + 16) ELSE 0\r\nDEST[VLMAX-1:128] <- 0\r\n\r\n\r\nVPMASKMOVD - 256-bit store\r\nIF (SRC1[31]) DEST[31:0] <- SRC2[31:0]\r\nIF (SRC1[63]) DEST[63:32] <- SRC2[63:32]\r\nIF (SRC1[95]) DEST[95:64] <- SRC2[95:64]\r\nIF (SRC1[127]) DEST[127:96] <- SRC2[127:96]\r\nIF (SRC1[159]) DEST[159:128] <-SRC2[159:128]\r\nIF (SRC1[191]) DEST[191:160] <- SRC2[191:160]\r\nIF (SRC1[223]) DEST[223:192] <- SRC2[223:192]\r\nIF (SRC1[255]) DEST[255:224] <- SRC2[255:224]\r\n\r\n\r\n\r\n\r\n\r\nVPMASKMOVD - 128-bit store\r\nIF (SRC1[31]) DEST[31:0] <- SRC2[31:0]\r\nIF (SRC1[63]) DEST[63:32] <- SRC2[63:32]\r\nIF (SRC1[95]) DEST[95:64] <- SRC2[95:64]\r\nIF (SRC1[127]) DEST[127:96] <- SRC2[127:96]\r\n\r\nVPMASKMOVQ - 256-bit store\r\nIF (SRC1[63]) DEST[63:0] <- SRC2[63:0]\r\nIF (SRC1[127]) DEST[127:64] <-SRC2[127:64]\r\nIF (SRC1[191]) DEST[191:128] <- SRC2[191:128]\r\nIF (SRC1[255]) DEST[255:192] <- SRC2[255:192]\r\n\r\nVPMASKMOVQ - 128-bit store\r\nIF (SRC1[63]) DEST[63:0] <- SRC2[63:0]\r\nIF (SRC1[127]) DEST[127:64] <-SRC2[127:64]\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPMASKMOVD: __m256i _mm256_maskload_epi32(int const *a, __m256i mask)\r\nVPMASKMOVD: void _mm256_maskstore_epi32(int *a, __m256i mask, __m256i b)\r\nVPMASKMOVQ: __m256i _mm256_maskload_epi64(__int64 const *a, __m256i mask);\r\nVPMASKMOVQ: void _mm256_maskstore_epi64(__int64 *a, __m256i mask, __m256d b);\r\nVPMASKMOVD: __m128i _mm_maskload_epi32(int const *a, __m128i mask)\r\nVPMASKMOVD: void _mm_maskstore_epi32(int *a, __m128i mask, __m128 b)\r\nVPMASKMOVQ: __m128i _mm_maskload_epi64(__int cont *a, __m128i mask);\r\nVPMASKMOVQ: void _mm_maskstore_epi64(__int64 *a, __m128i mask, __m128i b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 6 (No AC# reported for any mask bit combinations).\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPMASKMOV"
},
{
"description": "VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M-Convert a Vector Register to a Mask\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.F3.0F38.W0 29 /r RM V/V AVX512VL Sets each bit in k1 to 1 or 0 based on the value of the most\r\n VPMOVB2M k1, xmm1 AVX512BW significant bit of the corresponding byte in XMM1.\r\n EVEX.256.F3.0F38.W0 29 /r RM V/V AVX512VL Sets each bit in k1 to 1 or 0 based on the value of the most\r\n VPMOVB2M k1, ymm1 AVX512BW significant bit of the corresponding byte in YMM1.\r\n EVEX.512.F3.0F38.W0 29 /r RM V/V AVX512BW Sets each bit in k1 to 1 or 0 based on the value of the most\r\n VPMOVB2M k1, zmm1 significant bit of the corresponding byte in ZMM1.\r\n EVEX.128.F3.0F38.W1 29 /r RM V/V AVX512VL Sets each bit in k1 to 1 or 0 based on the value of the most\r\n VPMOVW2M k1, xmm1 AVX512BW significant bit of the corresponding word in XMM1.\r\n EVEX.256.F3.0F38.W1 29 /r RM V/V AVX512VL Sets each bit in k1 to 1 or 0 based on the value of the most\r\n VPMOVW2M k1, ymm1 AVX512BW significant bit of the corresponding word in YMM1.\r\n EVEX.512.F3.0F38.W1 29 /r RM V/V AVX512BW Sets each bit in k1 to 1 or 0 based on the value of the most\r\n VPMOVW2M k1, zmm1 significant bit of the corresponding word in ZMM1.\r\n EVEX.128.F3.0F38.W0 39 /r RM V/V AVX512VL Sets each bit in k1 to 1 or 0 based on the value of the most\r\n VPMOVD2M k1, xmm1 AVX512DQ significant bit of the corresponding doubleword in XMM1.\r\n EVEX.256.F3.0F38.W0 39 /r RM V/V AVX512VL Sets each bit in k1 to 1 or 0 based on the value of the most\r\n VPMOVD2M k1, ymm1 AVX512DQ significant bit of the corresponding doubleword in YMM1.\r\n EVEX.512.F3.0F38.W0 39 /r RM V/V AVX512DQ Sets each bit in k1 to 1 or 0 based on the value of the most\r\n VPMOVD2M k1, zmm1 significant bit of the corresponding doubleword in ZMM1.\r\n EVEX.128.F3.0F38.W1 39 /r RM V/V AVX512VL Sets each bit in k1 to 1 or 0 based on the value of the most\r\n VPMOVQ2M k1, xmm1 AVX512DQ significant bit of the corresponding quadword in XMM1.\r\n EVEX.256.F3.0F38.W1 39 /r RM V/V AVX512VL Sets each bit in k1 to 1 or 0 based on the value of the most\r\n VPMOVQ2M k1, ymm1 AVX512DQ significant bit of the corresponding quadword in YMM1.\r\n EVEX.512.F3.0F38.W1 39 /r RM V/V AVX512DQ Sets each bit in k1 to 1 or 0 based on the value of the most\r\n VPMOVQ2M k1, zmm1 significant bit of the corresponding quadword in ZMM1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts a vector register to a mask register. Each element in the destination register is set to 1 or 0 depending on\r\nthe value of most significant bit of the corresponding element in the source register.\r\nThe source operand is a ZMM/YMM/XMM register. The destination operand is a mask register.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVPMOVB2M (EVEX encoded versions)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\nFOR j <- 0 TO KL-1\r\n i<-j*8\r\n IF SRC[i+7]\r\n THEN DEST[j] <- 1\r\n ELSE DEST[j] <- 0\r\n FI;\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\nVPMOVW2M (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF SRC[i+15]\r\n THEN DEST[j] <- 1\r\n ELSE DEST[j] <- 0\r\n FI;\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\nVPMOVD2M (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF SRC[i+31]\r\n THEN DEST[j] <- 1\r\n ELSE DEST[j] <- 0\r\n FI;\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\nVPMOVQ2M (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF SRC[i+63]\r\n THEN DEST[j] <- 1\r\n ELSE DEST[j] <- 0\r\n FI;\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPMPOVB2M __mmask64 _mm512_movepi8_mask( __m512i );\r\nVPMPOVD2M __mmask16 _mm512_movepi32_mask( __m512i );\r\nVPMPOVQ2M __mmask8 _mm512_movepi64_mask( __m512i );\r\nVPMPOVW2M __mmask32 _mm512_movepi16_mask( __m512i );\r\nVPMPOVB2M __mmask32 _mm256_movepi8_mask( __m256i );\r\nVPMPOVD2M __mmask8 _mm256_movepi32_mask( __m256i );\r\nVPMPOVQ2M __mmask8 _mm256_movepi64_mask( __m256i );\r\nVPMPOVW2M __mmask16 _mm256_movepi16_mask( __m256i );\r\nVPMPOVB2M __mmask16 _mm_movepi8_mask( __m128i );\r\nVPMPOVD2M __mmask8 _mm_movepi32_mask( __m128i );\r\nVPMPOVQ2M __mmask8 _mm_movepi64_mask( __m128i );\r\nVPMPOVW2M __mmask8 _mm_movepi16_mask( __m128i );\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nEVEX-encoded instruction, see Exceptions Type E7NM\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPMOVB2M"
},
{
"description": "-R:VPMOVB2M",
"mnem": "VPMOVD2M"
},
{
"description": "VPMOVDB/VPMOVSDB/VPMOVUSDB-Down Convert DWord to Byte\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.F3.0F38.W0 31 /r QVM V/V AVX512VL Converts 4 packed double-word integers from xmm2\r\n VPMOVDB xmm1/m32 {k1}{z}, xmm2 AVX512F into 4 packed byte integers in xmm1/m32 with\r\n truncation under writemask k1.\r\n EVEX.128.F3.0F38.W0 21 /r QVM V/V AVX512VL Converts 4 packed signed double-word integers from\r\n VPMOVSDB xmm1/m32 {k1}{z}, xmm2 AVX512F xmm2 into 4 packed signed byte integers in\r\n xmm1/m32 using signed saturation under writemask\r\n k1.\r\n EVEX.128.F3.0F38.W0 11 /r QVM V/V AVX512VL Converts 4 packed unsigned double-word integers\r\n VPMOVUSDB xmm1/m32 {k1}{z}, AVX512F from xmm2 into 4 packed unsigned byte integers in\r\n xmm2 xmm1/m32 using unsigned saturation under\r\n writemask k1.\r\n EVEX.256.F3.0F38.W0 31 /r QVM V/V AVX512VL Converts 8 packed double-word integers from ymm2\r\n VPMOVDB xmm1/m64 {k1}{z}, ymm2 AVX512F into 8 packed byte integers in xmm1/m64 with\r\n truncation under writemask k1.\r\n EVEX.256.F3.0F38.W0 21 /r QVM V/V AVX512VL Converts 8 packed signed double-word integers from\r\n VPMOVSDB xmm1/m64 {k1}{z}, ymm2 AVX512F ymm2 into 8 packed signed byte integers in\r\n xmm1/m64 using signed saturation under writemask\r\n k1.\r\n EVEX.256.F3.0F38.W0 11 /r QVM V/V AVX512VL Converts 8 packed unsigned double-word integers\r\n VPMOVUSDB xmm1/m64 {k1}{z}, ymm2 AVX512F from ymm2 into 8 packed unsigned byte integers in\r\n xmm1/m64 using unsigned saturation under\r\n writemask k1.\r\n EVEX.512.F3.0F38.W0 31 /r QVM V/V AVX512F Converts 16 packed double-word integers from zmm2\r\n VPMOVDB xmm1/m128 {k1}{z}, zmm2 into 16 packed byte integers in xmm1/m128 with\r\n truncation under writemask k1.\r\n EVEX.512.F3.0F38.W0 21 /r QVM V/V AVX512F Converts 16 packed signed double-word integers\r\n VPMOVSDB xmm1/m128 {k1}{z}, zmm2 from zmm2 into 16 packed signed byte integers in\r\n xmm1/m128 using signed saturation under\r\n writemask k1.\r\n EVEX.512.F3.0F38.W0 11 /r QVM V/V AVX512F Converts 16 packed unsigned double-word integers\r\n VPMOVUSDB xmm1/m128 {k1}{z}, from zmm2 into 16 packed unsigned byte integers in\r\n zmm2 xmm1/m128 using unsigned saturation under\r\n writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n QVM ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\nDescription\r\nVPMOVDB down converts 32-bit integer elements in the source operand (the second operand) into packed bytes\r\nusing truncation. VPMOVSDB converts signed 32-bit integers into packed signed bytes using signed saturation.\r\nVPMOVUSDB convert unsigned double-word values into unsigned byte values using unsigned saturation.\r\nThe source operand is a ZMM/YMM/XMM register. The destination operand is a XMM register or a 128/64/32-bit\r\nmemory location.\r\nDown-converted byte elements are written to the destination operand (the first operand) from the least-significant\r\nbyte. Byte elements of the destination operand are updated according to the writemask. Bits (MAX_VL-\r\n1:128/64/32) of the register destination are zeroed.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\nOperation\r\nVPMOVDB instruction (EVEX encoded versions) when dest is a register\r\n (KL, VL) = (4, 128), (8, 256), (16, 512)\r\n FOR j <- 0 TO KL-1\r\n i<-j*8\r\n m <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- TruncateDoubleWordToByte (SRC[m+31:m])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+7:i] <- 0\r\n FI\r\n FI;\r\n ENDFOR\r\n DEST[MAX_VL-1:VL/4] <- 0;\r\n\r\nVPMOVDB instruction (EVEX encoded versions) when dest is memory\r\n (KL, VL) = (4, 128), (8, 256), (16, 512)\r\n FOR j <- 0 TO KL-1\r\n i<-j*8\r\n m <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- TruncateDoubleWordToByte (SRC[m+31:m])\r\n ELSE *DEST[i+7:i] remains unchanged* ; merging-masking\r\n FI;\r\n ENDFOR\r\n\r\nVPMOVSDB instruction (EVEX encoded versions) when dest is a register\r\n (KL, VL) = (4, 128), (8, 256), (16, 512)\r\n FOR j <- 0 TO KL-1\r\n i<-j*8\r\n m <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- SaturateSignedDoubleWordToByte (SRC[m+31:m])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+7:i] <- 0\r\n FI\r\n FI;\r\n ENDFOR\r\n DEST[MAX_VL-1:VL/4] <- 0;\r\n\r\n\r\n\r\n\r\n\r\nVPMOVSDB instruction (EVEX encoded versions) when dest is memory\r\n (KL, VL) = (4, 128), (8, 256), (16, 512)\r\n FOR j <- 0 TO KL-1\r\n i<-j*8\r\n m <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- SaturateSignedDoubleWordToByte (SRC[m+31:m])\r\n ELSE *DEST[i+7:i] remains unchanged* ; merging-masking\r\n FI;\r\n ENDFOR\r\n\r\nVPMOVUSDB instruction (EVEX encoded versions) when dest is a register\r\n (KL, VL) = (4, 128), (8, 256), (16, 512)\r\n FOR j <- 0 TO KL-1\r\n i<-j*8\r\n m <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- SaturateUnsignedDoubleWordToByte (SRC[m+31:m])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+7:i] <- 0\r\n FI\r\n FI;\r\n ENDFOR\r\n DEST[MAX_VL-1:VL/4] <- 0;\r\n\r\nVPMOVUSDB instruction (EVEX encoded versions) when dest is memory\r\n (KL, VL) = (4, 128), (8, 256), (16, 512)\r\n FOR j <- 0 TO KL-1\r\n i<-j*8\r\n m <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- SaturateUnsignedDoubleWordToByte (SRC[m+31:m])\r\n ELSE *DEST[i+7:i] remains unchanged* ; merging-masking\r\n FI;\r\n ENDFOR\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPMOVDB __m128i _mm512_cvtepi32_epi8( __m512i a);\r\nVPMOVDB __m128i _mm512_mask_cvtepi32_epi8(__m128i s, __mmask16 k, __m512i a);\r\nVPMOVDB __m128i _mm512_maskz_cvtepi32_epi8( __mmask16 k, __m512i a);\r\nVPMOVDB void _mm512_mask_cvtepi32_storeu_epi8(void * d, __mmask16 k, __m512i a);\r\nVPMOVSDB __m128i _mm512_cvtsepi32_epi8( __m512i a);\r\nVPMOVSDB __m128i _mm512_mask_cvtsepi32_epi8(__m128i s, __mmask16 k, __m512i a);\r\nVPMOVSDB __m128i _mm512_maskz_cvtsepi32_epi8( __mmask16 k, __m512i a);\r\nVPMOVSDB void _mm512_mask_cvtsepi32_storeu_epi8(void * d, __mmask16 k, __m512i a);\r\nVPMOVUSDB __m128i _mm512_cvtusepi32_epi8( __m512i a);\r\nVPMOVUSDB __m128i _mm512_mask_cvtusepi32_epi8(__m128i s, __mmask16 k, __m512i a);\r\nVPMOVUSDB __m128i _mm512_maskz_cvtusepi32_epi8( __mmask16 k, __m512i a);\r\nVPMOVUSDB void _mm512_mask_cvtusepi32_storeu_epi8(void * d, __mmask16 k, __m512i a);\r\nVPMOVUSDB __m128i _mm256_cvtusepi32_epi8(__m256i a);\r\nVPMOVUSDB __m128i _mm256_mask_cvtusepi32_epi8(__m128i a, __mmask8 k, __m256i b);\r\nVPMOVUSDB __m128i _mm256_maskz_cvtusepi32_epi8( __mmask8 k, __m256i b);\r\nVPMOVUSDB void _mm256_mask_cvtusepi32_storeu_epi8(void * , __mmask8 k, __m256i b);\r\nVPMOVUSDB __m128i _mm_cvtusepi32_epi8(__m128i a);\r\nVPMOVUSDB __m128i _mm_mask_cvtusepi32_epi8(__m128i a, __mmask8 k, __m128i b);\r\nVPMOVUSDB __m128i _mm_maskz_cvtusepi32_epi8( __mmask8 k, __m128i b);\r\nVPMOVUSDB void _mm_mask_cvtusepi32_storeu_epi8(void * , __mmask8 k, __m128i b);\r\nVPMOVSDB __m128i _mm256_cvtsepi32_epi8(__m256i a);\r\nVPMOVSDB __m128i _mm256_mask_cvtsepi32_epi8(__m128i a, __mmask8 k, __m256i b);\r\nVPMOVSDB __m128i _mm256_maskz_cvtsepi32_epi8( __mmask8 k, __m256i b);\r\nVPMOVSDB void _mm256_mask_cvtsepi32_storeu_epi8(void * , __mmask8 k, __m256i b);\r\nVPMOVSDB __m128i _mm_cvtsepi32_epi8(__m128i a);\r\nVPMOVSDB __m128i _mm_mask_cvtsepi32_epi8(__m128i a, __mmask8 k, __m128i b);\r\nVPMOVSDB __m128i _mm_maskz_cvtsepi32_epi8( __mmask8 k, __m128i b);\r\nVPMOVSDB void _mm_mask_cvtsepi32_storeu_epi8(void * , __mmask8 k, __m128i b);\r\nVPMOVDB __m128i _mm256_cvtepi32_epi8(__m256i a);\r\nVPMOVDB __m128i _mm256_mask_cvtepi32_epi8(__m128i a, __mmask8 k, __m256i b);\r\nVPMOVDB __m128i _mm256_maskz_cvtepi32_epi8( __mmask8 k, __m256i b);\r\nVPMOVDB void _mm256_mask_cvtepi32_storeu_epi8(void * , __mmask8 k, __m256i b);\r\nVPMOVDB __m128i _mm_cvtepi32_epi8(__m128i a);\r\nVPMOVDB __m128i _mm_mask_cvtepi32_epi8(__m128i a, __mmask8 k, __m128i b);\r\nVPMOVDB __m128i _mm_maskz_cvtepi32_epi8( __mmask8 k, __m128i b);\r\nVPMOVDB void _mm_mask_cvtepi32_storeu_epi8(void * , __mmask8 k, __m128i b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nEVEX-encoded instruction, see Exceptions Type E6.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPMOVDB"
},
{
"description": "VPMOVDW/VPMOVSDW/VPMOVUSDW-Down Convert DWord to Word\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.F3.0F38.W0 33 /r HVM V/V AVX512VL Converts 4 packed double-word integers from\r\n VPMOVDW xmm1/m64 {k1}{z}, xmm2 AVX512F xmm2 into 4 packed word integers in xmm1/m64\r\n with truncation under writemask k1.\r\n EVEX.128.F3.0F38.W0 23 /r HVM V/V AVX512VL Converts 4 packed signed double-word integers\r\n VPMOVSDW xmm1/m64 {k1}{z}, xmm2 AVX512F from xmm2 into 4 packed signed word integers in\r\n ymm1/m64 using signed saturation under\r\n writemask k1.\r\n EVEX.128.F3.0F38.W0 13 /r HVM V/V AVX512VL Converts 4 packed unsigned double-word integers\r\n VPMOVUSDW xmm1/m64 {k1}{z}, xmm2 AVX512F from xmm2 into 4 packed unsigned word integers\r\n in xmm1/m64 using unsigned saturation under\r\n writemask k1.\r\n EVEX.256.F3.0F38.W0 33 /r HVM V/V AVX512VL Converts 8 packed double-word integers from\r\n VPMOVDW xmm1/m128 {k1}{z}, ymm2 AVX512F ymm2 into 8 packed word integers in xmm1/m128\r\n with truncation under writemask k1.\r\n EVEX.256.F3.0F38.W0 23 /r HVM V/V AVX512VL Converts 8 packed signed double-word integers\r\n VPMOVSDW xmm1/m128 {k1}{z}, ymm2 AVX512F from ymm2 into 8 packed signed word integers in\r\n xmm1/m128 using signed saturation under\r\n writemask k1.\r\n EVEX.256.F3.0F38.W0 13 /r HVM V/V AVX512VL Converts 8 packed unsigned double-word integers\r\n VPMOVUSDW xmm1/m128 {k1}{z}, AVX512F from ymm2 into 8 packed unsigned word integers\r\n ymm2 in xmm1/m128 using unsigned saturation under\r\n writemask k1.\r\n EVEX.512.F3.0F38.W0 33 /r HVM V/V AVX512F Converts 16 packed double-word integers from\r\n VPMOVDW ymm1/m256 {k1}{z}, zmm2 zmm2 into 16 packed word integers in\r\n ymm1/m256 with truncation under writemask k1.\r\n EVEX.512.F3.0F38.W0 23 /r HVM V/V AVX512F Converts 16 packed signed double-word integers\r\n VPMOVSDW ymm1/m256 {k1}{z}, zmm2 from zmm2 into 16 packed signed word integers in\r\n ymm1/m256 using signed saturation under\r\n writemask k1.\r\n EVEX.512.F3.0F38.W0 13 /r HVM V/V AVX512F Converts 16 packed unsigned double-word integers\r\n VPMOVUSDW ymm1/m256 {k1}{z}, from zmm2 into 16 packed unsigned word integers\r\n zmm2 in ymm1/m256 using unsigned saturation under\r\n writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n HVM ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\nDescription\r\nVPMOVDW down converts 32-bit integer elements in the source operand (the second operand) into packed words\r\nusing truncation. VPMOVSDW converts signed 32-bit integers into packed signed words using signed saturation.\r\nVPMOVUSDW convert unsigned double-word values into unsigned word values using unsigned saturation.\r\nThe source operand is a ZMM/YMM/XMM register. The destination operand is a YMM/XMM/XMM register or a\r\n256/128/64-bit memory location.\r\nDown-converted word elements are written to the destination operand (the first operand) from the least-significant\r\nword. Word elements of the destination operand are updated according to the writemask. Bits (MAX_VL-\r\n1:256/128/64) of the register destination are zeroed.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\nOperation\r\nVPMOVDW instruction (EVEX encoded versions) when dest is a register\r\n (KL, VL) = (4, 128), (8, 256), (16, 512)\r\n FOR j <- 0 TO KL-1\r\n i <- j * 16\r\n m <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- TruncateDoubleWordToWord (SRC[m+31:m])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\n ENDFOR\r\n DEST[MAX_VL-1:VL/2] <- 0;\r\n\r\nVPMOVDW instruction (EVEX encoded versions) when dest is memory\r\n (KL, VL) = (4, 128), (8, 256), (16, 512)\r\n FOR j <- 0 TO KL-1\r\n i <- j * 16\r\n m <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- TruncateDoubleWordToWord (SRC[m+31:m])\r\n ELSE\r\n *DEST[i+15:i] remains unchanged* ; merging-masking\r\n FI;\r\n ENDFOR\r\n\r\nVPMOVSDW instruction (EVEX encoded versions) when dest is a register\r\n (KL, VL) = (4, 128), (8, 256), (16, 512)\r\n FOR j <- 0 TO KL-1\r\n i <- j * 16\r\n m <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- SaturateSignedDoubleWordToWord (SRC[m+31:m])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\n ENDFOR\r\n DEST[MAX_VL-1:VL/2] <- 0;\r\n\r\n\r\n\r\n\r\n\r\nVPMOVSDW instruction (EVEX encoded versions) when dest is memory\r\n (KL, VL) = (4, 128), (8, 256), (16, 512)\r\n FOR j <- 0 TO KL-1\r\n i <- j * 16\r\n m <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- SaturateSignedDoubleWordToWord (SRC[m+31:m])\r\n ELSE\r\n *DEST[i+15:i] remains unchanged* ; merging-masking\r\n FI;\r\n ENDFOR\r\n\r\nVPMOVUSDW instruction (EVEX encoded versions) when dest is a register\r\n (KL, VL) = (4, 128), (8, 256), (16, 512)\r\n FOR j <- 0 TO KL-1\r\n i <- j * 16\r\n m <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- SaturateUnsignedDoubleWordToWord (SRC[m+31:m])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\n ENDFOR\r\n DEST[MAX_VL-1:VL/2] <- 0;\r\n\r\nVPMOVUSDW instruction (EVEX encoded versions) when dest is memory\r\n (KL, VL) = (4, 128), (8, 256), (16, 512)\r\n FOR j <- 0 TO KL-1\r\n i <- j * 16\r\n m <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- SaturateUnsignedDoubleWordToWord (SRC[m+31:m])\r\n ELSE\r\n *DEST[i+15:i] remains unchanged* ; merging-masking\r\n FI;\r\n ENDFOR\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPMOVDW __m256i _mm512_cvtepi32_epi16( __m512i a);\r\nVPMOVDW __m256i _mm512_mask_cvtepi32_epi16(__m256i s, __mmask16 k, __m512i a);\r\nVPMOVDW __m256i _mm512_maskz_cvtepi32_epi16( __mmask16 k, __m512i a);\r\nVPMOVDW void _mm512_mask_cvtepi32_storeu_epi16(void * d, __mmask16 k, __m512i a);\r\nVPMOVSDW __m256i _mm512_cvtsepi32_epi16( __m512i a);\r\nVPMOVSDW __m256i _mm512_mask_cvtsepi32_epi16(__m256i s, __mmask16 k, __m512i a);\r\nVPMOVSDW __m256i _mm512_maskz_cvtsepi32_epi16( __mmask16 k, __m512i a);\r\nVPMOVSDW void _mm512_mask_cvtsepi32_storeu_epi16(void * d, __mmask16 k, __m512i a);\r\nVPMOVUSDW __m256i _mm512_cvtusepi32_epi16 __m512i a);\r\nVPMOVUSDW __m256i _mm512_mask_cvtusepi32_epi16(__m256i s, __mmask16 k, __m512i a);\r\nVPMOVUSDW __m256i _mm512_maskz_cvtusepi32_epi16( __mmask16 k, __m512i a);\r\nVPMOVUSDW void _mm512_mask_cvtusepi32_storeu_epi16(void * d, __mmask16 k, __m512i a);\r\nVPMOVUSDW __m128i _mm256_cvtusepi32_epi16(__m256i a);\r\nVPMOVUSDW __m128i _mm256_mask_cvtusepi32_epi16(__m128i a, __mmask8 k, __m256i b);\r\nVPMOVUSDW __m128i _mm256_maskz_cvtusepi32_epi16( __mmask8 k, __m256i b);\r\nVPMOVUSDW void _mm256_mask_cvtusepi32_storeu_epi16(void * , __mmask8 k, __m256i b);\r\nVPMOVUSDW __m128i _mm_cvtusepi32_epi16(__m128i a);\r\nVPMOVUSDW __m128i _mm_mask_cvtusepi32_epi16(__m128i a, __mmask8 k, __m128i b);\r\nVPMOVUSDW __m128i _mm_maskz_cvtusepi32_epi16( __mmask8 k, __m128i b);\r\nVPMOVUSDW void _mm_mask_cvtusepi32_storeu_epi16(void * , __mmask8 k, __m128i b);\r\nVPMOVSDW __m128i _mm256_cvtsepi32_epi16(__m256i a);\r\nVPMOVSDW __m128i _mm256_mask_cvtsepi32_epi16(__m128i a, __mmask8 k, __m256i b);\r\nVPMOVSDW __m128i _mm256_maskz_cvtsepi32_epi16( __mmask8 k, __m256i b);\r\nVPMOVSDW void _mm256_mask_cvtsepi32_storeu_epi16(void * , __mmask8 k, __m256i b);\r\nVPMOVSDW __m128i _mm_cvtsepi32_epi16(__m128i a);\r\nVPMOVSDW __m128i _mm_mask_cvtsepi32_epi16(__m128i a, __mmask8 k, __m128i b);\r\nVPMOVSDW __m128i _mm_maskz_cvtsepi32_epi16( __mmask8 k, __m128i b);\r\nVPMOVSDW void _mm_mask_cvtsepi32_storeu_epi16(void * , __mmask8 k, __m128i b);\r\nVPMOVDW __m128i _mm256_cvtepi32_epi16(__m256i a);\r\nVPMOVDW __m128i _mm256_mask_cvtepi32_epi16(__m128i a, __mmask8 k, __m256i b);\r\nVPMOVDW __m128i _mm256_maskz_cvtepi32_epi16( __mmask8 k, __m256i b);\r\nVPMOVDW void _mm256_mask_cvtepi32_storeu_epi16(void * , __mmask8 k, __m256i b);\r\nVPMOVDW __m128i _mm_cvtepi32_epi16(__m128i a);\r\nVPMOVDW __m128i _mm_mask_cvtepi32_epi16(__m128i a, __mmask8 k, __m128i b);\r\nVPMOVDW __m128i _mm_maskz_cvtepi32_epi16( __mmask8 k, __m128i b);\r\nVPMOVDW void _mm_mask_cvtepi32_storeu_epi16(void * , __mmask8 k, __m128i b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nEVEX-encoded instruction, see Exceptions Type E6.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPMOVDW"
},
{
"description": "VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q-Convert a Mask Register to a Vector\r\nRegister\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.F3.0F38.W0 28 /r RM V/V AVX512VL Sets each byte in XMM1 to all 1's or all 0's based on the value\r\n VPMOVM2B xmm1, k1 AVX512BW of the corresponding bit in k1.\r\n EVEX.256.F3.0F38.W0 28 /r RM V/V AVX512VL Sets each byte in YMM1 to all 1's or all 0's based on the value\r\n VPMOVM2B ymm1, k1 AVX512BW of the corresponding bit in k1.\r\n EVEX.512.F3.0F38.W0 28 /r RM V/V AVX512BW Sets each byte in ZMM1 to all 1's or all 0's based on the value\r\n VPMOVM2B zmm1, k1 of the corresponding bit in k1.\r\n EVEX.128.F3.0F38.W1 28 /r RM V/V AVX512VL Sets each word in XMM1 to all 1's or all 0's based on the value\r\n VPMOVM2W xmm1, k1 AVX512BW of the corresponding bit in k1.\r\n EVEX.256.F3.0F38.W1 28 /r RM V/V AVX512VL Sets each word in YMM1 to all 1's or all 0's based on the value\r\n VPMOVM2W ymm1, k1 AVX512BW of the corresponding bit in k1.\r\n EVEX.512.F3.0F38.W1 28 /r RM V/V AVX512BW Sets each word in ZMM1 to all 1's or all 0's based on the value\r\n VPMOVM2W zmm1, k1 of the corresponding bit in k1.\r\n EVEX.128.F3.0F38.W0 38 /r RM V/V AVX512VL Sets each doubleword in XMM1 to all 1's or all 0's based on the\r\n VPMOVM2D xmm1, k1 AVX512DQ value of the corresponding bit in k1.\r\n EVEX.256.F3.0F38.W0 38 /r RM V/V AVX512VL Sets each doubleword in YMM1 to all 1's or all 0's based on the\r\n VPMOVM2D ymm1, k1 AVX512DQ value of the corresponding bit in k1.\r\n EVEX.512.F3.0F38.W0 38 /r RM V/V AVX512DQ Sets each doubleword in ZMM1 to all 1's or all 0's based on the\r\n VPMOVM2D zmm1, k1 value of the corresponding bit in k1.\r\n EVEX.128.F3.0F38.W1 38 /r RM V/V AVX512VL Sets each quadword in XMM1 to all 1's or all 0's based on the\r\n VPMOVM2Q xmm1, k1 AVX512DQ value of the corresponding bit in k1.\r\n EVEX.256.F3.0F38.W1 38 /r RM V/V AVX512VL Sets each quadword in YMM1 to all 1's or all 0's based on the\r\n VPMOVM2Q ymm1, k1 AVX512DQ value of the corresponding bit in k1.\r\n EVEX.512.F3.0F38.W1 38 /r RM V/V AVX512DQ Sets each quadword in ZMM1 to all 1's or all 0's based on the\r\n VPMOVM2Q zmm1, k1 value of the corresponding bit in k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nConverts a mask register to a vector register. Each element in the destination register is set to all 1's or all 0's\r\ndepending on the value of the corresponding bit in the source mask register.\r\nThe source operand is a mask register. The destination operand is a ZMM/YMM/XMM register.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVPMOVM2B (EVEX encoded versions)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\nFOR j <- 0 TO KL-1\r\n i<-j*8\r\n IF SRC[j]\r\n THEN DEST[i+7:i] <- -1\r\n ELSE DEST[i+7:i] <- 0\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPMOVM2W (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF SRC[j]\r\n THEN DEST[i+15:i] <- -1\r\n ELSE DEST[i+15:i] <- 0\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPMOVM2D (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF SRC[j]\r\n THEN DEST[i+31:i] <- -1\r\n ELSE DEST[i+31:i] <- 0\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVPMOVM2Q (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF SRC[j]\r\n THEN DEST[i+63:i] <- -1\r\n ELSE DEST[i+63:i] <- 0\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPMOVM2B __m512i _mm512_movm_epi8(__mmask64 );\r\nVPMOVM2D __m512i _mm512_movm_epi32(__mmask8 );\r\nVPMOVM2Q __m512i _mm512_movm_epi64(__mmask16 );\r\nVPMOVM2W __m512i _mm512_movm_epi16(__mmask32 );\r\nVPMOVM2B __m256i _mm256_movm_epi8(__mmask32 );\r\nVPMOVM2D __m256i _mm256_movm_epi32(__mmask8 );\r\nVPMOVM2Q __m256i _mm256_movm_epi64(__mmask8 );\r\nVPMOVM2W __m256i _mm256_movm_epi16(__mmask16 );\r\nVPMOVM2B __m128i _mm_movm_epi8(__mmask16 );\r\nVPMOVM2D __m128i _mm_movm_epi32(__mmask8 );\r\nVPMOVM2Q __m128i _mm_movm_epi64(__mmask8 );\r\nVPMOVM2W __m128i _mm_movm_epi16(__mmask8 );\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nEVEX-encoded instruction, see Exceptions Type E7NM\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPMOVM2B"
},
{
"description": "-R:VPMOVM2B",
"mnem": "VPMOVM2D"
},
{
"description": "-R:VPMOVM2B",
"mnem": "VPMOVM2Q"
},
{
"description": "-R:VPMOVM2B",
"mnem": "VPMOVM2W"
},
{
"description": "-R:VPMOVB2M",
"mnem": "VPMOVQ2M"
},
{
"description": "VPMOVQB/VPMOVSQB/VPMOVUSQB-Down Convert QWord to Byte\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.F3.0F38.W0 32 /r OVM V/V AVX512VL Converts 2 packed quad-word integers from xmm2\r\n VPMOVQB xmm1/m16 {k1}{z}, xmm2 AVX512F into 2 packed byte integers in xmm1/m16 with\r\n truncation under writemask k1.\r\n EVEX.128.F3.0F38.W0 22 /r OVM V/V AVX512VL Converts 2 packed signed quad-word integers from\r\n VPMOVSQB xmm1/m16 {k1}{z}, xmm2 AVX512F xmm2 into 2 packed signed byte integers in\r\n xmm1/m16 using signed saturation under writemask\r\n k1.\r\n EVEX.128.F3.0F38.W0 12 /r OVM V/V AVX512VL Converts 2 packed unsigned quad-word integers\r\n VPMOVUSQB xmm1/m16 {k1}{z}, xmm2 AVX512F from xmm2 into 2 packed unsigned byte integers in\r\n xmm1/m16 using unsigned saturation under\r\n writemask k1.\r\n EVEX.256.F3.0F38.W0 32 /r OVM V/V AVX512VL Converts 4 packed quad-word integers from ymm2\r\n VPMOVQB xmm1/m32 {k1}{z}, ymm2 AVX512F into 4 packed byte integers in xmm1/m32 with\r\n truncation under writemask k1.\r\n EVEX.256.F3.0F38.W0 22 /r OVM V/V AVX512VL Converts 4 packed signed quad-word integers from\r\n VPMOVSQB xmm1/m32 {k1}{z}, ymm2 AVX512F ymm2 into 4 packed signed byte integers in\r\n xmm1/m32 using signed saturation under writemask\r\n k1.\r\n EVEX.256.F3.0F38.W0 12 /r OVM V/V AVX512VL Converts 4 packed unsigned quad-word integers\r\n VPMOVUSQB xmm1/m32 {k1}{z}, ymm2 AVX512F from ymm2 into 4 packed unsigned byte integers in\r\n xmm1/m32 using unsigned saturation under\r\n writemask k1.\r\n EVEX.512.F3.0F38.W0 32 /r OVM V/V AVX512F Converts 8 packed quad-word integers from zmm2\r\n VPMOVQB xmm1/m64 {k1}{z}, zmm2 into 8 packed byte integers in xmm1/m64 with\r\n truncation under writemask k1.\r\n EVEX.512.F3.0F38.W0 22 /r OVM V/V AVX512F Converts 8 packed signed quad-word integers from\r\n VPMOVSQB xmm1/m64 {k1}{z}, zmm2 zmm2 into 8 packed signed byte integers in\r\n xmm1/m64 using signed saturation under writemask\r\n k1.\r\n EVEX.512.F3.0F38.W0 12 /r OVM V/V AVX512F Converts 8 packed unsigned quad-word integers\r\n VPMOVUSQB xmm1/m64 {k1}{z}, zmm2 from zmm2 into 8 packed unsigned byte integers in\r\n xmm1/m64 using unsigned saturation under\r\n writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n OVM ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\nDescription\r\nVPMOVQB down converts 64-bit integer elements in the source operand (the second operand) into packed byte\r\nelements using truncation. VPMOVSQB converts signed 64-bit integers into packed signed bytes using signed satu-\r\nration. VPMOVUSQB convert unsigned quad-word values into unsigned byte values using unsigned saturation. The\r\nsource operand is a vector register. The destination operand is an XMM register or a memory location.\r\nDown-converted byte elements are written to the destination operand (the first operand) from the least-significant\r\nbyte. Byte elements of the destination operand are updated according to the writemask. Bits (MAX_VL-1:64) of the\r\ndestination are zeroed.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVPMOVQB instruction (EVEX encoded versions) when dest is a register\r\n (KL, VL) = (2, 128), (4, 256), (8, 512)\r\n FOR j <- 0 TO KL-1\r\n i<-j*8\r\n m <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- TruncateQuadWordToByte (SRC[m+63:m])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+7:i] <- 0\r\n FI\r\n FI;\r\n ENDFOR\r\n DEST[MAX_VL-1:VL/8] <- 0;\r\n\r\nVPMOVQB instruction (EVEX encoded versions) when dest is memory\r\n (KL, VL) = (2, 128), (4, 256), (8, 512)\r\n FOR j <- 0 TO KL-1\r\n i<-j*8\r\n m <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- TruncateQuadWordToByte (SRC[m+63:m])\r\n ELSE\r\n *DEST[i+7:i] remains unchanged* ; merging-masking\r\n FI;\r\n ENDFOR\r\n\r\nVPMOVSQB instruction (EVEX encoded versions) when dest is a register\r\n (KL, VL) = (2, 128), (4, 256), (8, 512)\r\n FOR j <- 0 TO KL-1\r\n i<-j*8\r\n m <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- SaturateSignedQuadWordToByte (SRC[m+63:m])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+7:i] <- 0\r\n FI\r\n FI;\r\n ENDFOR\r\n DEST[MAX_VL-1:VL/8] <- 0;\r\n\r\n\r\n\r\n\r\n\r\nVPMOVSQB instruction (EVEX encoded versions) when dest is memory\r\n (KL, VL) = (2, 128), (4, 256), (8, 512)\r\n FOR j <- 0 TO KL-1\r\n i<-j*8\r\n m <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- SaturateSignedQuadWordToByte (SRC[m+63:m])\r\n ELSE\r\n *DEST[i+7:i] remains unchanged* ; merging-masking\r\n FI;\r\n ENDFOR\r\n\r\nVPMOVUSQB instruction (EVEX encoded versions) when dest is a register\r\n (KL, VL) = (2, 128), (4, 256), (8, 512)\r\n FOR j <- 0 TO KL-1\r\n i<-j*8\r\n m <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- SaturateUnsignedQuadWordToByte (SRC[m+63:m])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+7:i] <- 0\r\n FI\r\n FI;\r\n ENDFOR\r\n DEST[MAX_VL-1:VL/8] <- 0;\r\n\r\nVPMOVUSQB instruction (EVEX encoded versions) when dest is memory\r\n (KL, VL) = (2, 128), (4, 256), (8, 512)\r\n FOR j <- 0 TO KL-1\r\n i<-j*8\r\n m <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- SaturateUnsignedQuadWordToByte (SRC[m+63:m])\r\n ELSE\r\n *DEST[i+7:i] remains unchanged* ; merging-masking\r\n FI;\r\n ENDFOR\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPMOVQB __m128i _mm512_cvtepi64_epi8( __m512i a);\r\nVPMOVQB __m128i _mm512_mask_cvtepi64_epi8(__m128i s, __mmask8 k, __m512i a);\r\nVPMOVQB __m128i _mm512_maskz_cvtepi64_epi8( __mmask8 k, __m512i a);\r\nVPMOVQB void _mm512_mask_cvtepi64_storeu_epi8(void * d, __mmask8 k, __m512i a);\r\nVPMOVSQB __m128i _mm512_cvtsepi64_epi8( __m512i a);\r\nVPMOVSQB __m128i _mm512_mask_cvtsepi64_epi8(__m128i s, __mmask8 k, __m512i a);\r\nVPMOVSQB __m128i _mm512_maskz_cvtsepi64_epi8( __mmask8 k, __m512i a);\r\nVPMOVSQB void _mm512_mask_cvtsepi64_storeu_epi8(void * d, __mmask8 k, __m512i a);\r\nVPMOVUSQB __m128i _mm512_cvtusepi64_epi8( __m512i a);\r\nVPMOVUSQB __m128i _mm512_mask_cvtusepi64_epi8(__m128i s, __mmask8 k, __m512i a);\r\nVPMOVUSQB __m128i _mm512_maskz_cvtusepi64_epi8( __mmask8 k, __m512i a);\r\nVPMOVUSQB void _mm512_mask_cvtusepi64_storeu_epi8(void * d, __mmask8 k, __m512i a);\r\nVPMOVUSQB __m128i _mm256_cvtusepi64_epi8(__m256i a);\r\nVPMOVUSQB __m128i _mm256_mask_cvtusepi64_epi8(__m128i a, __mmask8 k, __m256i b);\r\nVPMOVUSQB __m128i _mm256_maskz_cvtusepi64_epi8( __mmask8 k, __m256i b);\r\nVPMOVUSQB void _mm256_mask_cvtusepi64_storeu_epi8(void * , __mmask8 k, __m256i b);\r\nVPMOVUSQB __m128i _mm_cvtusepi64_epi8(__m128i a);\r\nVPMOVUSQB __m128i _mm_mask_cvtusepi64_epi8(__m128i a, __mmask8 k, __m128i b);\r\nVPMOVUSQB __m128i _mm_maskz_cvtusepi64_epi8( __mmask8 k, __m128i b);\r\nVPMOVUSQB void _mm_mask_cvtusepi64_storeu_epi8(void * , __mmask8 k, __m128i b);\r\nVPMOVSQB __m128i _mm256_cvtsepi64_epi8(__m256i a);\r\nVPMOVSQB __m128i _mm256_mask_cvtsepi64_epi8(__m128i a, __mmask8 k, __m256i b);\r\nVPMOVSQB __m128i _mm256_maskz_cvtsepi64_epi8( __mmask8 k, __m256i b);\r\nVPMOVSQB void _mm256_mask_cvtsepi64_storeu_epi8(void * , __mmask8 k, __m256i b);\r\nVPMOVSQB __m128i _mm_cvtsepi64_epi8(__m128i a);\r\nVPMOVSQB __m128i _mm_mask_cvtsepi64_epi8(__m128i a, __mmask8 k, __m128i b);\r\nVPMOVSQB __m128i _mm_maskz_cvtsepi64_epi8( __mmask8 k, __m128i b);\r\nVPMOVSQB void _mm_mask_cvtsepi64_storeu_epi8(void * , __mmask8 k, __m128i b);\r\nVPMOVQB __m128i _mm256_cvtepi64_epi8(__m256i a);\r\nVPMOVQB __m128i _mm256_mask_cvtepi64_epi8(__m128i a, __mmask8 k, __m256i b);\r\nVPMOVQB __m128i _mm256_maskz_cvtepi64_epi8( __mmask8 k, __m256i b);\r\nVPMOVQB void _mm256_mask_cvtepi64_storeu_epi8(void * , __mmask8 k, __m256i b);\r\nVPMOVQB __m128i _mm_cvtepi64_epi8(__m128i a);\r\nVPMOVQB __m128i _mm_mask_cvtepi64_epi8(__m128i a, __mmask8 k, __m128i b);\r\nVPMOVQB __m128i _mm_maskz_cvtepi64_epi8( __mmask8 k, __m128i b);\r\nVPMOVQB void _mm_mask_cvtepi64_storeu_epi8(void * , __mmask8 k, __m128i b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nEVEX-encoded instruction, see Exceptions Type E6.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPMOVQB"
},
{
"description": "VPMOVQD/VPMOVSQD/VPMOVUSQD-Down Convert QWord to DWord\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.F3.0F38.W0 35 /r A V/V AVX512VL Converts 2 packed quad-word integers from xmm2\r\n VPMOVQD xmm1/m128 {k1}{z}, xmm2 AVX512F into 2 packed double-word integers in xmm1/m128\r\n with truncation subject to writemask k1.\r\n EVEX.128.F3.0F38.W0 25 /r A V/V AVX512VL Converts 2 packed signed quad-word integers from\r\n VPMOVSQD xmm1/m64 {k1}{z}, xmm2 AVX512F xmm2 into 2 packed signed double-word integers\r\n in xmm1/m64 using signed saturation subject to\r\n writemask k1.\r\n EVEX.128.F3.0F38.W0 15 /r A V/V AVX512VL Converts 2 packed unsigned quad-word integers\r\n VPMOVUSQD xmm1/m64 {k1}{z}, xmm2 AVX512F from xmm2 into 2 packed unsigned double-word\r\n integers in xmm1/m64 using unsigned saturation\r\n subject to writemask k1.\r\n EVEX.256.F3.0F38.W0 35 /r A V/V AVX512VL Converts 4 packed quad-word integers from ymm2\r\n VPMOVQD xmm1/m128 {k1}{z}, ymm2 AVX512F into 4 packed double-word integers in xmm1/m128\r\n with truncation subject to writemask k1.\r\n EVEX.256.F3.0F38.W0 25 /r A V/V AVX512VL Converts 4 packed signed quad-word integers from\r\n VPMOVSQD xmm1/m128 {k1}{z}, ymm2 AVX512F ymm2 into 4 packed signed double-word integers in\r\n xmm1/m128 using signed saturation subject to\r\n writemask k1.\r\n EVEX.256.F3.0F38.W0 15 /r A V/V AVX512VL Converts 4 packed unsigned quad-word integers\r\n VPMOVUSQD xmm1/m128 {k1}{z}, ymm2 AVX512F from ymm2 into 4 packed unsigned double-word\r\n integers in xmm1/m128 using unsigned saturation\r\n subject to writemask k1.\r\n EVEX.512.F3.0F38.W0 35 /r HVM V/V AVX512F Converts 8 packed quad-word integers from zmm2\r\n VPMOVQD ymm1/m256 {k1}{z}, zmm2 into 8 packed double-word integers in ymm1/m256\r\n with truncation subject to writemask k1.\r\n EVEX.512.F3.0F38.W0 25 /r HVM V/V AVX512F Converts 8 packed signed quad-word integers from\r\n VPMOVSQD ymm1/m256 {k1}{z}, zmm2 zmm2 into 8 packed signed double-word integers in\r\n ymm1/m256 using signed saturation subject to\r\n writemask k1.\r\n EVEX.512.F3.0F38.W0 15 /r HVM V/V AVX512F Converts 8 packed unsigned quad-word integers\r\n VPMOVUSQD ymm1/m256 {k1}{z}, zmm2 from zmm2 into 8 packed unsigned double-word\r\n integers in ymm1/m256 using unsigned saturation\r\n subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n HVM ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\nDescription\r\nVPMOVQW down converts 64-bit integer elements in the source operand (the second operand) into packed double-\r\nwords using truncation. VPMOVSQW converts signed 64-bit integers into packed signed doublewords using signed\r\nsaturation. VPMOVUSQW convert unsigned quad-word values into unsigned double-word values using unsigned\r\nsaturation.\r\nThe source operand is a ZMM/YMM/XMM register. The destination operand is a YMM/XMM/XMM register or a\r\n256/128/64-bit memory location.\r\nDown-converted doubleword elements are written to the destination operand (the first operand) from the least-\r\nsignificant doubleword. Doubleword elements of the destination operand are updated according to the writemask.\r\nBits (MAX_VL-1:256/128/64) of the register destination are zeroed.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\nOperation\r\nVPMOVQD instruction (EVEX encoded version) reg-reg form\r\n (KL, VL) = (2, 128), (4, 256), (8, 512)\r\n FOR j <- 0 TO KL-1\r\n i <- j * 32\r\n m <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TruncateQuadWordToDWord (SRC[m+63:m])\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\n ENDFOR\r\n DEST[MAX_VL-1:VL/2] <- 0;\r\n\r\nVPMOVQD instruction (EVEX encoded version) memory form\r\n (KL, VL) = (2, 128), (4, 256), (8, 512)\r\n FOR j <- 0 TO KL-1\r\n i <- j * 32\r\n m <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TruncateQuadWordToDWord (SRC[m+63:m])\r\n ELSE *DEST[i+31:i] remains unchanged* ; merging-masking\r\n FI;\r\n ENDFOR\r\n\r\nVPMOVSQD instruction (EVEX encoded version) reg-reg form\r\n (KL, VL) = (2, 128), (4, 256), (8, 512)\r\n FOR j <- 0 TO KL-1\r\n i <- j * 32\r\n m <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- SaturateSignedQuadWordToDWord (SRC[m+63:m])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\n ENDFOR\r\n DEST[MAX_VL-1:VL/2] <- 0;\r\n\r\n\r\n\r\n\r\n\r\nVPMOVSQD instruction (EVEX encoded version) memory form\r\n (KL, VL) = (2, 128), (4, 256), (8, 512)\r\n FOR j <- 0 TO KL-1\r\n i <- j * 32\r\n m <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- SaturateSignedQuadWordToDWord (SRC[m+63:m])\r\n ELSE *DEST[i+31:i] remains unchanged* ; merging-masking\r\n FI;\r\n ENDFOR\r\n\r\nVPMOVUSQD instruction (EVEX encoded version) reg-reg form\r\n (KL, VL) = (2, 128), (4, 256), (8, 512)\r\n FOR j <- 0 TO KL-1\r\n i <- j * 32\r\n m <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- SaturateUnsignedQuadWordToDWord (SRC[m+63:m])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\n ENDFOR\r\n DEST[MAX_VL-1:VL/2] <- 0;\r\n\r\nVPMOVUSQD instruction (EVEX encoded version) memory form\r\n (KL, VL) = (2, 128), (4, 256), (8, 512)\r\n FOR j <- 0 TO KL-1\r\n i <- j * 32\r\n m <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- SaturateUnsignedQuadWordToDWord (SRC[m+63:m])\r\n ELSE *DEST[i+31:i] remains unchanged* ; merging-masking\r\n FI;\r\n ENDFOR\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPMOVQD __m256i _mm512_cvtepi64_epi32( __m512i a);\r\nVPMOVQD __m256i _mm512_mask_cvtepi64_epi32(__m256i s, __mmask8 k, __m512i a);\r\nVPMOVQD __m256i _mm512_maskz_cvtepi64_epi32( __mmask8 k, __m512i a);\r\nVPMOVQD void _mm512_mask_cvtepi64_storeu_epi32(void * d, __mmask8 k, __m512i a);\r\nVPMOVSQD __m256i _mm512_cvtsepi64_epi32( __m512i a);\r\nVPMOVSQD __m256i _mm512_mask_cvtsepi64_epi32(__m256i s, __mmask8 k, __m512i a);\r\nVPMOVSQD __m256i _mm512_maskz_cvtsepi64_epi32( __mmask8 k, __m512i a);\r\nVPMOVSQD void _mm512_mask_cvtsepi64_storeu_epi32(void * d, __mmask8 k, __m512i a);\r\nVPMOVUSQD __m256i _mm512_cvtusepi64_epi32( __m512i a);\r\nVPMOVUSQD __m256i _mm512_mask_cvtusepi64_epi32(__m256i s, __mmask8 k, __m512i a);\r\nVPMOVUSQD __m256i _mm512_maskz_cvtusepi64_epi32( __mmask8 k, __m512i a);\r\nVPMOVUSQD void _mm512_mask_cvtusepi64_storeu_epi32(void * d, __mmask8 k, __m512i a);\r\nVPMOVUSQD __m128i _mm256_cvtusepi64_epi32(__m256i a);\r\nVPMOVUSQD __m128i _mm256_mask_cvtusepi64_epi32(__m128i a, __mmask8 k, __m256i b);\r\nVPMOVUSQD __m128i _mm256_maskz_cvtusepi64_epi32( __mmask8 k, __m256i b);\r\nVPMOVUSQD void _mm256_mask_cvtusepi64_storeu_epi32(void * , __mmask8 k, __m256i b);\r\nVPMOVUSQD __m128i _mm_cvtusepi64_epi32(__m128i a);\r\nVPMOVUSQD __m128i _mm_mask_cvtusepi64_epi32(__m128i a, __mmask8 k, __m128i b);\r\nVPMOVUSQD __m128i _mm_maskz_cvtusepi64_epi32( __mmask8 k, __m128i b);\r\nVPMOVUSQD void _mm_mask_cvtusepi64_storeu_epi32(void * , __mmask8 k, __m128i b);\r\nVPMOVSQD __m128i _mm256_cvtsepi64_epi32(__m256i a);\r\nVPMOVSQD __m128i _mm256_mask_cvtsepi64_epi32(__m128i a, __mmask8 k, __m256i b);\r\nVPMOVSQD __m128i _mm256_maskz_cvtsepi64_epi32( __mmask8 k, __m256i b);\r\nVPMOVSQD void _mm256_mask_cvtsepi64_storeu_epi32(void * , __mmask8 k, __m256i b);\r\nVPMOVSQD __m128i _mm_cvtsepi64_epi32(__m128i a);\r\nVPMOVSQD __m128i _mm_mask_cvtsepi64_epi32(__m128i a, __mmask8 k, __m128i b);\r\nVPMOVSQD __m128i _mm_maskz_cvtsepi64_epi32( __mmask8 k, __m128i b);\r\nVPMOVSQD void _mm_mask_cvtsepi64_storeu_epi32(void * , __mmask8 k, __m128i b);\r\nVPMOVQD __m128i _mm256_cvtepi64_epi32(__m256i a);\r\nVPMOVQD __m128i _mm256_mask_cvtepi64_epi32(__m128i a, __mmask8 k, __m256i b);\r\nVPMOVQD __m128i _mm256_maskz_cvtepi64_epi32( __mmask8 k, __m256i b);\r\nVPMOVQD void _mm256_mask_cvtepi64_storeu_epi32(void * , __mmask8 k, __m256i b);\r\nVPMOVQD __m128i _mm_cvtepi64_epi32(__m128i a);\r\nVPMOVQD __m128i _mm_mask_cvtepi64_epi32(__m128i a, __mmask8 k, __m128i b);\r\nVPMOVQD __m128i _mm_maskz_cvtepi64_epi32( __mmask8 k, __m128i b);\r\nVPMOVQD void _mm_mask_cvtepi64_storeu_epi32(void * , __mmask8 k, __m128i b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nEVEX-encoded instruction, see Exceptions Type E6.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPMOVQD"
},
{
"description": "VPMOVQW/VPMOVSQW/VPMOVUSQW-Down Convert QWord to Word\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.F3.0F38.W0 34 /r QVM V/V AVX512VL Converts 2 packed quad-word integers from xmm2\r\n VPMOVQW xmm1/m32 {k1}{z}, xmm2 AVX512F into 2 packed word integers in xmm1/m32 with\r\n truncation under writemask k1.\r\n EVEX.128.F3.0F38.W0 24 /r QVM V/V AVX512VL Converts 8 packed signed quad-word integers from\r\n VPMOVSQW xmm1/m32 {k1}{z}, xmm2 AVX512F zmm2 into 8 packed signed word integers in\r\n xmm1/m32 using signed saturation under writemask\r\n k1.\r\n EVEX.128.F3.0F38.W0 14 /r QVM V/V AVX512VL Converts 2 packed unsigned quad-word integers from\r\n VPMOVUSQW xmm1/m32 {k1}{z}, xmm2 AVX512F xmm2 into 2 packed unsigned word integers in\r\n xmm1/m32 using unsigned saturation under\r\n writemask k1.\r\n EVEX.256.F3.0F38.W0 34 /r QVM V/V AVX512VL Converts 4 packed quad-word integers from ymm2\r\n VPMOVQW xmm1/m64 {k1}{z}, ymm2 AVX512F into 4 packed word integers in xmm1/m64 with\r\n truncation under writemask k1.\r\n EVEX.256.F3.0F38.W0 24 /r QVM V/V AVX512VL Converts 4 packed signed quad-word integers from\r\n VPMOVSQW xmm1/m64 {k1}{z}, ymm2 AVX512F ymm2 into 4 packed signed word integers in\r\n xmm1/m64 using signed saturation under writemask\r\n k1.\r\n EVEX.256.F3.0F38.W0 14 /r QVM V/V AVX512VL Converts 4 packed unsigned quad-word integers from\r\n VPMOVUSQW xmm1/m64 {k1}{z}, ymm2 AVX512F ymm2 into 4 packed unsigned word integers in\r\n xmm1/m64 using unsigned saturation under\r\n writemask k1.\r\n EVEX.512.F3.0F38.W0 34 /r QVM V/V AVX512F Converts 8 packed quad-word integers from zmm2\r\n VPMOVQW xmm1/m128 {k1}{z}, zmm2 into 8 packed word integers in xmm1/m128 with\r\n truncation under writemask k1.\r\n EVEX.512.F3.0F38.W0 24 /r QVM V/V AVX512F Converts 8 packed signed quad-word integers from\r\n VPMOVSQW xmm1/m128 {k1}{z}, zmm2 zmm2 into 8 packed signed word integers in\r\n xmm1/m128 using signed saturation under\r\n writemask k1.\r\n EVEX.512.F3.0F38.W0 14 /r QVM V/V AVX512F Converts 8 packed unsigned quad-word integers from\r\n VPMOVUSQW xmm1/m128 {k1}{z}, zmm2 into 8 packed unsigned word integers in\r\n zmm2 xmm1/m128 using unsigned saturation under\r\n writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n QVM ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\nDescription\r\nVPMOVQW down converts 64-bit integer elements in the source operand (the second operand) into packed words\r\nusing truncation. VPMOVSQW converts signed 64-bit integers into packed signed words using signed saturation.\r\nVPMOVUSQW convert unsigned quad-word values into unsigned word values using unsigned saturation.\r\nThe source operand is a ZMM/YMM/XMM register. The destination operand is a XMM register or a 128/64/32-bit\r\nmemory location.\r\nDown-converted word elements are written to the destination operand (the first operand) from the least-significant\r\nword. Word elements of the destination operand are updated according to the writemask. Bits (MAX_VL-\r\n1:128/64/32) of the register destination are zeroed.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\nOperation\r\nVPMOVQW instruction (EVEX encoded versions) when dest is a register\r\n (KL, VL) = (2, 128), (4, 256), (8, 512)\r\n FOR j <- 0 TO KL-1\r\n i <- j * 16\r\n m <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- TruncateQuadWordToWord (SRC[m+63:m])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\n ENDFOR\r\n DEST[MAX_VL-1:VL/4] <- 0;\r\n\r\nVPMOVQW instruction (EVEX encoded versions) when dest is memory\r\n (KL, VL) = (2, 128), (4, 256), (8, 512)\r\n FOR j <- 0 TO KL-1\r\n i <- j * 16\r\n m <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- TruncateQuadWordToWord (SRC[m+63:m])\r\n ELSE\r\n *DEST[i+15:i] remains unchanged* ; merging-masking\r\n FI;\r\n ENDFOR\r\n\r\nVPMOVSQW instruction (EVEX encoded versions) when dest is a register\r\n (KL, VL) = (2, 128), (4, 256), (8, 512)\r\n FOR j <- 0 TO KL-1\r\n i <- j * 16\r\n m <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- SaturateSignedQuadWordToWord (SRC[m+63:m])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\n ENDFOR\r\n DEST[MAX_VL-1:VL/4] <- 0;\r\n\r\n\r\n\r\n\r\n\r\nVPMOVSQW instruction (EVEX encoded versions) when dest is memory\r\n (KL, VL) = (2, 128), (4, 256), (8, 512)\r\n FOR j <- 0 TO KL-1\r\n i <- j * 16\r\n m <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- SaturateSignedQuadWordToWord (SRC[m+63:m])\r\n ELSE\r\n *DEST[i+15:i] remains unchanged* ; merging-masking\r\n FI;\r\n ENDFOR\r\n\r\nVPMOVUSQW instruction (EVEX encoded versions) when dest is a register\r\n (KL, VL) = (2, 128), (4, 256), (8, 512)\r\n FOR j <- 0 TO KL-1\r\n i <- j * 16\r\n m <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- SaturateUnsignedQuadWordToWord (SRC[m+63:m])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\n ENDFOR\r\n DEST[MAX_VL-1:VL/4] <- 0;\r\n\r\nVPMOVUSQW instruction (EVEX encoded versions) when dest is memory\r\n (KL, VL) = (2, 128), (4, 256), (8, 512)\r\n FOR j <- 0 TO KL-1\r\n i <- j * 16\r\n m <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- SaturateUnsignedQuadWordToWord (SRC[m+63:m])\r\n ELSE\r\n *DEST[i+15:i] remains unchanged* ; merging-masking\r\n FI;\r\n ENDFOR\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPMOVQW __m128i _mm512_cvtepi64_epi16( __m512i a);\r\nVPMOVQW __m128i _mm512_mask_cvtepi64_epi16(__m128i s, __mmask8 k, __m512i a);\r\nVPMOVQW __m128i _mm512_maskz_cvtepi64_epi16( __mmask8 k, __m512i a);\r\nVPMOVQW void _mm512_mask_cvtepi64_storeu_epi16(void * d, __mmask8 k, __m512i a);\r\nVPMOVSQW __m128i _mm512_cvtsepi64_epi16( __m512i a);\r\nVPMOVSQW __m128i _mm512_mask_cvtsepi64_epi16(__m128i s, __mmask8 k, __m512i a);\r\nVPMOVSQW __m128i _mm512_maskz_cvtsepi64_epi16( __mmask8 k, __m512i a);\r\nVPMOVSQW void _mm512_mask_cvtsepi64_storeu_epi16(void * d, __mmask8 k, __m512i a);\r\nVPMOVUSQW __m128i _mm512_cvtusepi64_epi16( __m512i a);\r\nVPMOVUSQW __m128i _mm512_mask_cvtusepi64_epi16(__m128i s, __mmask8 k, __m512i a);\r\nVPMOVUSQW __m128i _mm512_maskz_cvtusepi64_epi16( __mmask8 k, __m512i a);\r\nVPMOVUSQW void _mm512_mask_cvtusepi64_storeu_epi16(void * d, __mmask8 k, __m512i a);\r\nVPMOVUSQD __m128i _mm256_cvtusepi64_epi32(__m256i a);\r\nVPMOVUSQD __m128i _mm256_mask_cvtusepi64_epi32(__m128i a, __mmask8 k, __m256i b);\r\nVPMOVUSQD __m128i _mm256_maskz_cvtusepi64_epi32( __mmask8 k, __m256i b);\r\nVPMOVUSQD void _mm256_mask_cvtusepi64_storeu_epi32(void * , __mmask8 k, __m256i b);\r\nVPMOVUSQD __m128i _mm_cvtusepi64_epi32(__m128i a);\r\nVPMOVUSQD __m128i _mm_mask_cvtusepi64_epi32(__m128i a, __mmask8 k, __m128i b);\r\nVPMOVUSQD __m128i _mm_maskz_cvtusepi64_epi32( __mmask8 k, __m128i b);\r\nVPMOVUSQD void _mm_mask_cvtusepi64_storeu_epi32(void * , __mmask8 k, __m128i b);\r\nVPMOVSQD __m128i _mm256_cvtsepi64_epi32(__m256i a);\r\nVPMOVSQD __m128i _mm256_mask_cvtsepi64_epi32(__m128i a, __mmask8 k, __m256i b);\r\nVPMOVSQD __m128i _mm256_maskz_cvtsepi64_epi32( __mmask8 k, __m256i b);\r\nVPMOVSQD void _mm256_mask_cvtsepi64_storeu_epi32(void * , __mmask8 k, __m256i b);\r\nVPMOVSQD __m128i _mm_cvtsepi64_epi32(__m128i a);\r\nVPMOVSQD __m128i _mm_mask_cvtsepi64_epi32(__m128i a, __mmask8 k, __m128i b);\r\nVPMOVSQD __m128i _mm_maskz_cvtsepi64_epi32( __mmask8 k, __m128i b);\r\nVPMOVSQD void _mm_mask_cvtsepi64_storeu_epi32(void * , __mmask8 k, __m128i b);\r\nVPMOVQD __m128i _mm256_cvtepi64_epi32(__m256i a);\r\nVPMOVQD __m128i _mm256_mask_cvtepi64_epi32(__m128i a, __mmask8 k, __m256i b);\r\nVPMOVQD __m128i _mm256_maskz_cvtepi64_epi32( __mmask8 k, __m256i b);\r\nVPMOVQD void _mm256_mask_cvtepi64_storeu_epi32(void * , __mmask8 k, __m256i b);\r\nVPMOVQD __m128i _mm_cvtepi64_epi32(__m128i a);\r\nVPMOVQD __m128i _mm_mask_cvtepi64_epi32(__m128i a, __mmask8 k, __m128i b);\r\nVPMOVQD __m128i _mm_maskz_cvtepi64_epi32( __mmask8 k, __m128i b);\r\nVPMOVQD void _mm_mask_cvtepi64_storeu_epi32(void * , __mmask8 k, __m128i b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nEVEX-encoded instruction, see Exceptions Type E6.\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPMOVQW"
},
{
"description": "-R:VPMOVDB",
"mnem": "VPMOVSDB"
},
{
"description": "-R:VPMOVDW",
"mnem": "VPMOVSDW"
},
{
"description": "-R:VPMOVQB",
"mnem": "VPMOVSQB"
},
{
"description": "-R:VPMOVQD",
"mnem": "VPMOVSQD"
},
{
"description": "-R:VPMOVQW",
"mnem": "VPMOVSQW"
},
{
"description": "-R:VPMOVWB",
"mnem": "VPMOVSWB"
},
{
"description": "-R:VPMOVDB",
"mnem": "VPMOVUSDB"
},
{
"description": "-R:VPMOVDW",
"mnem": "VPMOVUSDW"
},
{
"description": "-R:VPMOVQB",
"mnem": "VPMOVUSQB"
},
{
"description": "-R:VPMOVQD",
"mnem": "VPMOVUSQD"
},
{
"description": "-R:VPMOVQW",
"mnem": "VPMOVUSQW"
},
{
"description": "-R:VPMOVWB",
"mnem": "VPMOVUSWB"
},
{
"description": "-R:VPMOVB2M",
"mnem": "VPMOVW2M"
},
{
"description": "VPMOVWB/VPMOVSWB/VPMOVUSWB-Down Convert Word to Byte\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.F3.0F38.W0 30 /r HVM V/V AVX512VL Converts 8 packed word integers from xmm2 into 8\r\n VPMOVWB xmm1/m64 {k1}{z}, xmm2 AVX512BW packed bytes in xmm1/m64 with truncation under\r\n writemask k1.\r\n EVEX.128.F3.0F38.W0 20 /r HVM V/V AVX512VL Converts 8 packed signed word integers from xmm2\r\n VPMOVSWB xmm1/m64 {k1}{z}, AVX512BW into 8 packed signed bytes in xmm1/m64 using\r\n xmm2 signed saturation under writemask k1.\r\n EVEX.128.F3.0F38.W0 10 /r HVM V/V AVX512VL Converts 8 packed unsigned word integers from\r\n VPMOVUSWB xmm1/m64 {k1}{z}, AVX512BW xmm2 into 8 packed unsigned bytes in 8mm1/m64\r\n xmm2 using unsigned saturation under writemask k1.\r\n EVEX.256.F3.0F38.W0 30 /r HVM V/V AVX512VL Converts 16 packed word integers from ymm2 into\r\n VPMOVWB xmm1/m128 {k1}{z}, AVX512BW 16 packed bytes in xmm1/m128 with truncation\r\n ymm2 under writemask k1.\r\n EVEX.256.F3.0F38.W0 20 /r HVM V/V AVX512VL Converts 16 packed signed word integers from ymm2\r\n VPMOVSWB xmm1/m128 {k1}{z}, AVX512BW into 16 packed signed bytes in xmm1/m128 using\r\n ymm2 signed saturation under writemask k1.\r\n EVEX.256.F3.0F38.W0 10 /r HVM V/V AVX512VL Converts 16 packed unsigned word integers from\r\n VPMOVUSWB xmm1/m128 {k1}{z}, AVX512BW ymm2 into 16 packed unsigned bytes in xmm1/m128\r\n ymm2 using unsigned saturation under writemask k1.\r\n EVEX.512.F3.0F38.W0 30 /r HVM V/V AVX512BW Converts 32 packed word integers from zmm2 into\r\n VPMOVWB ymm1/m256 {k1}{z}, 32 packed bytes in ymm1/m256 with truncation\r\n zmm2 under writemask k1.\r\n EVEX.512.F3.0F38.W0 20 /r HVM V/V AVX512BW Converts 32 packed signed word integers from zmm2\r\n VPMOVSWB ymm1/m256 {k1}{z}, into 32 packed signed bytes in ymm1/m256 using\r\n zmm2 signed saturation under writemask k1.\r\n EVEX.512.F3.0F38.W0 10 /r HVM V/V AVX512BW Converts 32 packed unsigned word integers from\r\n VPMOVUSWB ymm1/m256 {k1}{z}, zmm2 into 32 packed unsigned bytes in ymm1/m256\r\n zmm2 using unsigned saturation under writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n HVM ModRM:r/m (w) ModRM:reg (r) NA NA\r\n\r\nDescription\r\nVPMOVWB down converts 16-bit integers into packed bytes using truncation. VPMOVSWB converts signed 16-bit\r\nintegers into packed signed bytes using signed saturation. VPMOVUSWB convert unsigned word values into\r\nunsigned byte values using unsigned saturation.\r\nThe source operand is a ZMM/YMM/XMM register. The destination operand is a YMM/XMM/XMM register or a\r\n256/128/64-bit memory location.\r\nDown-converted byte elements are written to the destination operand (the first operand) from the least-significant\r\nbyte. Byte elements of the destination operand are updated according to the writemask. Bits (MAX_VL-\r\n1:256/128/64) of the register destination are zeroed.\r\nNote: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVPMOVWB instruction (EVEX encoded versions) when dest is a register\r\n (KL, VL) = (8, 128), (16, 256), (32, 512)\r\n FOR j <- 0 TO Kl-1\r\n i<-j*8\r\n m <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- TruncateWordToByte (SRC[m+15:m])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+7:i] = 0\r\n FI\r\n FI;\r\n ENDFOR\r\n DEST[MAX_VL-1:VL/2] <- 0;\r\n\r\nVPMOVWB instruction (EVEX encoded versions) when dest is memory\r\n (KL, VL) = (8, 128), (16, 256), (32, 512)\r\n FOR j <- 0 TO Kl-1\r\n i<-j*8\r\n m <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- TruncateWordToByte (SRC[m+15:m])\r\n ELSE\r\n *DEST[i+7:i] remains unchanged* ; merging-masking\r\n FI;\r\n ENDFOR\r\n\r\nVPMOVSWB instruction (EVEX encoded versions) when dest is a register\r\n (KL, VL) = (8, 128), (16, 256), (32, 512)\r\n FOR j <- 0 TO Kl-1\r\n i<-j*8\r\n m <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- SaturateSignedWordToByte (SRC[m+15:m])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+7:i] = 0\r\n FI\r\n FI;\r\n ENDFOR\r\n DEST[MAX_VL-1:VL/2] <- 0;\r\n\r\n\r\n\r\n\r\n\r\nVPMOVSWB instruction (EVEX encoded versions) when dest is memory\r\n (KL, VL) = (8, 128), (16, 256), (32, 512)\r\n FOR j <- 0 TO Kl-1\r\n i<-j*8\r\n m <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- SaturateSignedWordToByte (SRC[m+15:m])\r\n ELSE\r\n *DEST[i+7:i] remains unchanged* ; merging-masking\r\n FI;\r\n ENDFOR\r\n\r\nVPMOVUSWB instruction (EVEX encoded versions) when dest is a register\r\n (KL, VL) = (8, 128), (16, 256), (32, 512)\r\n FOR j <- 0 TO Kl-1\r\n i<-j*8\r\n m <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- SaturateUnsignedWordToByte (SRC[m+15:m])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+7:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+7:i] = 0\r\n FI\r\n FI;\r\n ENDFOR\r\n DEST[MAX_VL-1:VL/2] <- 0;\r\n\r\nVPMOVUSWB instruction (EVEX encoded versions) when dest is memory\r\n (KL, VL) = (8, 128), (16, 256), (32, 512)\r\n FOR j <- 0 TO Kl-1\r\n i<-j*8\r\n m <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+7:i] <- SaturateUnsignedWordToByte (SRC[m+15:m])\r\n ELSE\r\n *DEST[i+7:i] remains unchanged* ; merging-masking\r\n FI;\r\n ENDFOR\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPMOVUSWB __m256i _mm512_cvtusepi16_epi8(__m512i a);\r\nVPMOVUSWB __m256i _mm512_mask_cvtusepi16_epi8(__m256i a, __mmask32 k, __m512i b);\r\nVPMOVUSWB __m256i _mm512_maskz_cvtusepi16_epi8( __mmask32 k, __m512i b);\r\nVPMOVUSWB void _mm512_mask_cvtusepi16_storeu_epi8(void * , __mmask32 k, __m512i b);\r\nVPMOVSWB __m256i _mm512_cvtsepi16_epi8(__m512i a);\r\nVPMOVSWB __m256i _mm512_mask_cvtsepi16_epi8(__m256i a, __mmask32 k, __m512i b);\r\nVPMOVSWB __m256i _mm512_maskz_cvtsepi16_epi8( __mmask32 k, __m512i b);\r\nVPMOVSWB void _mm512_mask_cvtsepi16_storeu_epi8(void * , __mmask32 k, __m512i b);\r\nVPMOVWB __m256i _mm512_cvtepi16_epi8(__m512i a);\r\nVPMOVWB __m256i _mm512_mask_cvtepi16_epi8(__m256i a, __mmask32 k, __m512i b);\r\nVPMOVWB __m256i _mm512_maskz_cvtepi16_epi8( __mmask32 k, __m512i b);\r\nVPMOVWB void _mm512_mask_cvtepi16_storeu_epi8(void * , __mmask32 k, __m512i b);\r\nVPMOVUSWB __m128i _mm256_cvtusepi16_epi8(__m256i a);\r\nVPMOVUSWB __m128i _mm256_mask_cvtusepi16_epi8(__m128i a, __mmask16 k, __m256i b);\r\nVPMOVUSWB __m128i _mm256_maskz_cvtusepi16_epi8( __mmask16 k, __m256i b);\r\nVPMOVUSWB void _mm256_mask_cvtusepi16_storeu_epi8(void * , __mmask16 k, __m256i b);\r\nVPMOVUSWB __m128i _mm_cvtusepi16_epi8(__m128i a);\r\nVPMOVUSWB __m128i _mm_mask_cvtusepi16_epi8(__m128i a, __mmask8 k, __m128i b);\r\nVPMOVUSWB __m128i _mm_maskz_cvtusepi16_epi8( __mmask8 k, __m128i b);\r\nVPMOVUSWB void _mm_mask_cvtusepi16_storeu_epi8(void * , __mmask8 k, __m128i b);\r\nVPMOVSWB __m128i _mm256_cvtsepi16_epi8(__m256i a);\r\nVPMOVSWB __m128i _mm256_mask_cvtsepi16_epi8(__m128i a, __mmask16 k, __m256i b);\r\nVPMOVSWB __m128i _mm256_maskz_cvtsepi16_epi8( __mmask16 k, __m256i b);\r\nVPMOVSWB void _mm256_mask_cvtsepi16_storeu_epi8(void * , __mmask16 k, __m256i b);\r\nVPMOVSWB __m128i _mm_cvtsepi16_epi8(__m128i a);\r\nVPMOVSWB __m128i _mm_mask_cvtsepi16_epi8(__m128i a, __mmask8 k, __m128i b);\r\nVPMOVSWB __m128i _mm_maskz_cvtsepi16_epi8( __mmask8 k, __m128i b);\r\nVPMOVSWB void _mm_mask_cvtsepi16_storeu_epi8(void * , __mmask8 k, __m128i b);\r\nVPMOVWB __m128i _mm256_cvtepi16_epi8(__m256i a);\r\nVPMOVWB __m128i _mm256_mask_cvtepi16_epi8(__m128i a, __mmask16 k, __m256i b);\r\nVPMOVWB __m128i _mm256_maskz_cvtepi16_epi8( __mmask16 k, __m256i b);\r\nVPMOVWB void _mm256_mask_cvtepi16_storeu_epi8(void * , __mmask16 k, __m256i b);\r\nVPMOVWB __m128i _mm_cvtepi16_epi8(__m128i a);\r\nVPMOVWB __m128i _mm_mask_cvtepi16_epi8(__m128i a, __mmask8 k, __m128i b);\r\nVPMOVWB __m128i _mm_maskz_cvtepi16_epi8( __mmask8 k, __m128i b);\r\nVPMOVWB void _mm_mask_cvtepi16_storeu_epi8(void * , __mmask8 k, __m128i b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nEVEX-encoded instruction, see Exceptions Type E6NF\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPMOVWB"
},
{
"description": "VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ-Scatter Packed Dword, Packed\r\nQword with Signed Dword, Signed Qword Indices\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F38.W0 A0 /vsib T1S V/V AVX512VL Using signed dword indices, scatter dword values to\r\n VPSCATTERDD vm32x {k1}, xmm1 AVX512F memory using writemask k1.\r\n EVEX.256.66.0F38.W0 A0 /vsib T1S V/V AVX512VL Using signed dword indices, scatter dword values to\r\n VPSCATTERDD vm32y {k1}, ymm1 AVX512F memory using writemask k1.\r\n EVEX.512.66.0F38.W0 A0 /vsib T1S V/V AVX512F Using signed dword indices, scatter dword values to\r\n VPSCATTERDD vm32z {k1}, zmm1 memory using writemask k1.\r\n EVEX.128.66.0F38.W1 A0 /vsib T1S V/V AVX512VL Using signed dword indices, scatter qword values to\r\n VPSCATTERDQ vm32x {k1}, xmm1 AVX512F memory using writemask k1.\r\n EVEX.256.66.0F38.W1 A0 /vsib T1S V/V AVX512VL Using signed dword indices, scatter qword values to\r\n VPSCATTERDQ vm32x {k1}, ymm1 AVX512F memory using writemask k1.\r\n EVEX.512.66.0F38.W1 A0 /vsib T1S V/V AVX512F Using signed dword indices, scatter qword values to\r\n VPSCATTERDQ vm32y {k1}, zmm1 memory using writemask k1.\r\n EVEX.128.66.0F38.W0 A1 /vsib T1S V/V AVX512VL Using signed qword indices, scatter dword values to\r\n VPSCATTERQD vm64x {k1}, xmm1 AVX512F memory using writemask k1.\r\n EVEX.256.66.0F38.W0 A1 /vsib T1S V/V AVX512VL Using signed qword indices, scatter dword values to\r\n VPSCATTERQD vm64y {k1}, xmm1 AVX512F memory using writemask k1.\r\n EVEX.512.66.0F38.W0 A1 /vsib T1S V/V AVX512F Using signed qword indices, scatter dword values to\r\n VPSCATTERQD vm64z {k1}, ymm1 memory using writemask k1.\r\n EVEX.128.66.0F38.W1 A1 /vsib T1S V/V AVX512VL Using signed qword indices, scatter qword values to\r\n VPSCATTERQQ vm64x {k1}, xmm1 AVX512F memory using writemask k1.\r\n EVEX.256.66.0F38.W1 A1 /vsib T1S V/V AVX512VL Using signed qword indices, scatter qword values to\r\n VPSCATTERQQ vm64y {k1}, ymm1 AVX512F memory using writemask k1.\r\n EVEX.512.66.0F38.W1 A1 /vsib T1S V/V AVX512F Using signed qword indices, scatter qword values to\r\n VPSCATTERQQ vm64z {k1}, zmm1 memory using writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n BaseReg (R): VSIB:base,\r\n T1S ModRM:reg (r) NA NA\r\n VectorReg(R): VSIB:index\r\n\r\nDescription\r\nStores up to 16 elements (8 elements for qword indices) in doubleword vector or 8 elements in quadword vector to\r\nthe memory locations pointed by base address BASE_ADDR and index vector VINDEX, with scale SCALE. The\r\nelements are specified via the VSIB (i.e., the index register is a vector register, holding packed indices). Elements\r\nwill only be stored if their corresponding mask bit is one. The entire mask register will be set to zero by this instruc-\r\ntion unless it triggers an exception.\r\nThis instruction can be suspended by an exception if at least one element is already scattered (i.e., if the exception\r\nis triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination\r\nregister and the mask register are partially updated. If any traps or interrupts are pending from already scattered\r\nelements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction break-\r\npoint is not re-triggered when the instruction is continued.\r\nNote that:\r\n. Only writes to overlapping vector indices are guaranteed to be ordered with respect to each other (from LSB to\r\n MSB of the source registers). Note that this also include partially overlapping vector indices. Writes that are not\r\n overlapped may happen in any order. Memory ordering with other instructions follows the Intel-64 memory\r\n ordering model. Note that this does not account for non-overlapping indices that map into the same physical\r\n address locations.\r\n\r\n\r\n\r\n. If two or more destination indices completely overlap, the \"earlier\" write(s) may be skipped.\r\n. Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all\r\n elements closer to the LSB of the destination ZMM will be completed (and non-faulting). Individual elements\r\n closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered\r\n in the conventional order.\r\n. Elements may be scattered in any order, but faults must be delivered in a right-to left order; thus, elements to\r\n the left of a faulting one may be gathered before the fault is delivered. A given implementation of this\r\n instruction is repeatable - given the same input values and architectural state, the same set of elements to the\r\n left of the faulting one will be gathered.\r\n. This instruction does not perform AC checks, and so will never deliver an AC fault.\r\n. Not valid with 16-bit effective addresses. Will deliver a #UD fault.\r\n. If this instruction overwrites itself and then takes a fault, only a subset of elements may be completed before\r\n the fault is delivered (as described above). If the fault handler completes and attempts to re-execute this\r\n instruction, the new instruction will be executed, and the scatter will not complete.\r\nNote that the presence of VSIB byte is enforced in this instruction. Hence, the instruction will #UD fault if\r\nModRM.rm is different than 100b.\r\nThis instruction has special disp8*N and alignment rules. N is considered to be the size of a single vector element.\r\nThe scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-bit\r\nmode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits\r\nare ignored.\r\nThe instruction will #UD fault if the k0 mask register is specified.\r\nThe instruction will #UD fault if EVEX.Z = 1.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nBASE_ADDR stands for the memory operand base address (a GPR); may not exist\r\nVINDEX stands for the memory operand vector of indices (a ZMM register)\r\nSCALE stands for the memory operand scalar (1, 2, 4 or 8)\r\nDISP is the optional 1, 2 or 4 byte displacement\r\n\r\n\r\n\r\n\r\n\r\nVPSCATTERDD (EVEX encoded versions)\r\n(KL, VL)= (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN MEM[BASE_ADDR +SignExtend(VINDEX[i+31:i]) * SCALE + DISP] <- SRC[i+31:i]\r\n k1[j] <- 0\r\n\r\n FI;\r\nENDFOR\r\nk1[MAX_KL-1:KL] <- 0\r\n\r\nVPSCATTERDQ (EVEX encoded versions)\r\n(KL, VL)= (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n k <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN MEM[BASE_ADDR +SignExtend(VINDEX[k+31:k]) * SCALE + DISP] <- SRC[i+63:i]\r\n k1[j] <- 0\r\n FI;\r\nENDFOR\r\nk1[MAX_KL-1:KL] <- 0\r\n\r\nVPSCATTERQD (EVEX encoded versions)\r\n(KL, VL)= (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n k <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN MEM[BASE_ADDR + (VINDEX[k+63:k]) * SCALE + DISP] <- SRC[i+31:i]\r\n k1[j] <- 0\r\n\r\n FI;\r\nENDFOR\r\nk1[MAX_KL-1:KL] <- 0\r\n\r\nVPSCATTERQQ (EVEX encoded versions)\r\n(KL, VL)= (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN MEM[BASE_ADDR + (VINDEX[j+63:j]) * SCALE + DISP] <- SRC[i+63:i]\r\n FI;\r\nENDFOR\r\nk1[MAX_KL-1:KL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPSCATTERDD void _mm512_i32scatter_epi32(void * base, __m512i vdx, __m512i a, int scale);\r\nVPSCATTERDD void _mm256_i32scatter_epi32(void * base, __m256i vdx, __m256i a, int scale);\r\nVPSCATTERDD void _mm_i32scatter_epi32(void * base, __m128i vdx, __m128i a, int scale);\r\nVPSCATTERDD void _mm512_mask_i32scatter_epi32(void * base, __mmask16 k, __m512i vdx, __m512i a, int scale);\r\nVPSCATTERDD void _mm256_mask_i32scatter_epi32(void * base, __mmask8 k, __m256i vdx, __m256i a, int scale);\r\nVPSCATTERDD void _mm_mask_i32scatter_epi32(void * base, __mmask8 k, __m128i vdx, __m128i a, int scale);\r\nVPSCATTERDQ void _mm512_i32scatter_epi64(void * base, __m256i vdx, __m512i a, int scale);\r\nVPSCATTERDQ void _mm256_i32scatter_epi64(void * base, __m128i vdx, __m256i a, int scale);\r\nVPSCATTERDQ void _mm_i32scatter_epi64(void * base, __m128i vdx, __m128i a, int scale);\r\nVPSCATTERDQ void _mm512_mask_i32scatter_epi64(void * base, __mmask8 k, __m256i vdx, __m512i a, int scale);\r\nVPSCATTERDQ void _mm256_mask_i32scatter_epi64(void * base, __mmask8 k, __m128i vdx, __m256i a, int scale);\r\nVPSCATTERDQ void _mm_mask_i32scatter_epi64(void * base, __mmask8 k, __m128i vdx, __m128i a, int scale);\r\nVPSCATTERQD void _mm512_i64scatter_epi32(void * base, __m512i vdx, __m256i a, int scale);\r\nVPSCATTERQD void _mm256_i64scatter_epi32(void * base, __m256i vdx, __m128i a, int scale);\r\nVPSCATTERQD void _mm_i64scatter_epi32(void * base, __m128i vdx, __m128i a, int scale);\r\nVPSCATTERQD void _mm512_mask_i64scatter_epi32(void * base, __mmask8 k, __m512i vdx, __m256i a, int scale);\r\nVPSCATTERQD void _mm256_mask_i64scatter_epi32(void * base, __mmask8 k, __m256i vdx, __m128i a, int scale);\r\nVPSCATTERQD void _mm_mask_i64scatter_epi32(void * base, __mmask8 k, __m128i vdx, __m128i a, int scale);\r\nVPSCATTERQQ void _mm512_i64scatter_epi64(void * base, __m512i vdx, __m512i a, int scale);\r\nVPSCATTERQQ void _mm256_i64scatter_epi64(void * base, __m256i vdx, __m256i a, int scale);\r\nVPSCATTERQQ void _mm_i64scatter_epi64(void * base, __m128i vdx, __m128i a, int scale);\r\nVPSCATTERQQ void _mm512_mask_i64scatter_epi64(void * base, __mmask8 k, __m512i vdx, __m512i a, int scale);\r\nVPSCATTERQQ void _mm256_mask_i64scatter_epi64(void * base, __mmask8 k, __m256i vdx, __m256i a, int scale);\r\nVPSCATTERQQ void _mm_mask_i64scatter_epi64(void * base, __mmask8 k, __m128i vdx, __m128i a, int scale);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type E12.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPSCATTERDD"
},
{
"description": "-R:VPSCATTERDD",
"mnem": "VPSCATTERDQ"
},
{
"description": "-R:VPSCATTERDD",
"mnem": "VPSCATTERQD"
},
{
"description": "-R:VPSCATTERDD",
"mnem": "VPSCATTERQQ"
},
{
"description": "-R:VPSLLVW",
"mnem": "VPSLLVD"
},
{
"description": "-R:VPSLLVW",
"mnem": "VPSLLVQ"
},
{
"description": "VPSLLVW/VPSLLVD/VPSLLVQ-Variable Bit Shift Left Logical\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.NDS.128.66.0F38.W0 47 /r RVM V/V AVX2 Shift doublewords in xmm2 left by amount specified in\r\n VPSLLVD xmm1, xmm2, xmm3/m128 the corresponding element of xmm3/m128 while\r\n shifting in 0s.\r\n VEX.NDS.128.66.0F38.W1 47 /r RVM V/V AVX2 Shift quadwords in xmm2 left by amount specified in\r\n VPSLLVQ xmm1, xmm2, xmm3/m128 the corresponding element of xmm3/m128 while\r\n shifting in 0s.\r\n VEX.NDS.256.66.0F38.W0 47 /r RVM V/V AVX2 Shift doublewords in ymm2 left by amount specified in\r\n VPSLLVD ymm1, ymm2, ymm3/m256 the corresponding element of ymm3/m256 while\r\n shifting in 0s.\r\n VEX.NDS.256.66.0F38.W1 47 /r RVM V/V AVX2 Shift quadwords in ymm2 left by amount specified in\r\n VPSLLVQ ymm1, ymm2, ymm3/m256 the corresponding element of ymm3/m256 while\r\n shifting in 0s.\r\n EVEX.NDS.128.66.0F38.W1 12 /r FVM V/V AVX512VL Shift words in xmm2 left by amount specified in the\r\n VPSLLVW xmm1 {k1}{z}, xmm2, AVX512BW corresponding element of xmm3/m128 while shifting\r\n xmm3/m128 in 0s using writemask k1.\r\n EVEX.NDS.256.66.0F38.W1 12 /r FVM V/V AVX512VL Shift words in ymm2 left by amount specified in the\r\n VPSLLVW ymm1 {k1}{z}, ymm2, AVX512BW corresponding element of ymm3/m256 while shifting\r\n ymm3/m256 in 0s using writemask k1.\r\n EVEX.NDS.512.66.0F38.W1 12 /r FVM V/V AVX512BW Shift words in zmm2 left by amount specified in the\r\n VPSLLVW zmm1 {k1}{z}, zmm2, corresponding element of zmm3/m512 while shifting\r\n zmm3/m512 in 0s using writemask k1.\r\n EVEX.NDS.128.66.0F38.W0 47 /r FV V/V AVX512VL Shift doublewords in xmm2 left by amount specified in\r\n VPSLLVD xmm1 {k1}{z}, xmm2, AVX512F the corresponding element of xmm3/m128/m32bcst\r\n xmm3/m128/m32bcst while shifting in 0s using writemask k1.\r\n EVEX.NDS.256.66.0F38.W0 47 /r FV V/V AVX512VL Shift doublewords in ymm2 left by amount specified in\r\n VPSLLVD ymm1 {k1}{z}, ymm2, AVX512F the corresponding element of ymm3/m256/m32bcst\r\n ymm3/m256/m32bcst while shifting in 0s using writemask k1.\r\n EVEX.NDS.512.66.0F38.W0 47 /r FV V/V AVX512F Shift doublewords in zmm2 left by amount specified in\r\n VPSLLVD zmm1 {k1}{z}, zmm2, the corresponding element of zmm3/m512/m32bcst\r\n zmm3/m512/m32bcst while shifting in 0s using writemask k1.\r\n EVEX.NDS.128.66.0F38.W1 47 /r FV V/V AVX512VL Shift quadwords in xmm2 left by amount specified in\r\n VPSLLVQ xmm1 {k1}{z}, xmm2, AVX512F the corresponding element of xmm3/m128/m64bcst\r\n xmm3/m128/m64bcst while shifting in 0s using writemask k1.\r\n EVEX.NDS.256.66.0F38.W1 47 /r FV V/V AVX512VL Shift quadwords in ymm2 left by amount specified in\r\n VPSLLVQ ymm1 {k1}{z}, ymm2, AVX512F the corresponding element of ymm3/m256/m64bcst\r\n ymm3/m256/m64bcst while shifting in 0s using writemask k1.\r\n EVEX.NDS.512.66.0F38.W1 47 /r FV V/V AVX512F Shift quadwords in zmm2 left by amount specified in\r\n VPSLLVQ zmm1 {k1}{z}, zmm2, the corresponding element of zmm3/m512/m64bcst\r\n zmm3/m512/m64bcst while shifting in 0s using writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\n\r\n\r\n\r\nDescription\r\nShifts the bits in the individual data elements (words, doublewords or quadword) in the first source operand to the\r\nleft by the count value of respective data elements in the second source operand. As the bits in the data elements\r\nare shifted left, the empty low-order bits are cleared (set to 0).\r\nThe count values are specified individually in each data element of the second source operand. If the unsigned\r\ninteger value specified in the respective data element of the second source operand is greater than 15 (for word),\r\n31 (for doublewords), or 63 (for a quadword), then the destination data element are written with 0.\r\nVEX.128 encoded version: The destination and first source operands are XMM registers. The count operand can be\r\neither an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination\r\nregister are zeroed.\r\nVEX.256 encoded version: The destination and first source operands are YMM registers. The count operand can be\r\neither an YMM register or a 256-bit memory. Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed.\r\nEVEX encoded VPSLLVD/Q: The destination and first source operands are ZMM/YMM/XMM registers. The count\r\noperand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512-bit vector broad-\r\ncasted from a 32/64-bit memory location. The destination is conditionally updated with writemask k1.\r\nEVEX encoded VPSLLVW: The destination and first source operands are ZMM/YMM/XMM registers. The count\r\noperand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination is condition-\r\nally updated with writemask k1.\r\n\r\nOperation\r\nVPSLLVW (EVEX encoded version)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- ZeroExtend(SRC1[i+15:i] << SRC2[i+15:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0;\r\n\r\n\r\n\r\n\r\n\r\nVPSLLVD (VEX.128 version)\r\nCOUNT_0 <-SRC2[31 : 0]\r\n (* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)\r\nCOUNT_3 <-SRC2[100 : 96];\r\nIF COUNT_0 < 32 THEN\r\nDEST[31:0] <-ZeroExtend(SRC1[31:0] << COUNT_0);\r\nELSE\r\nDEST[31:0] <-0;\r\n (* Repeat shift operation for 2nd through 4th dwords *)\r\nIF COUNT_3 < 32 THEN\r\nDEST[127:96] <-ZeroExtend(SRC1[127:96] << COUNT_3);\r\nELSE\r\nDEST[127:96] <-0;\r\nDEST[MAX_VL-1:128] <-0;\r\n\r\nVPSLLVD (VEX.256 version)\r\nCOUNT_0 <-SRC2[31 : 0];\r\n (* Repeat Each COUNT_i for the 2nd through 7th dwords of SRC2*)\r\nCOUNT_7 <-SRC2[228 : 224];\r\nIF COUNT_0 < 32 THEN\r\nDEST[31:0] <-ZeroExtend(SRC1[31:0] << COUNT_0);\r\nELSE\r\nDEST[31:0] <-0;\r\n (* Repeat shift operation for 2nd through 7th dwords *)\r\nIF COUNT_7 < 32 THEN\r\nDEST[255:224] <-ZeroExtend(SRC1[255:224] << COUNT_7);\r\nELSE\r\nDEST[255:224] <-0;\r\nDEST[MAX_VL-1:256] <- 0;\r\n\r\nVPSLLVD (EVEX encoded version)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN DEST[i+31:i] <- ZeroExtend(SRC1[i+31:i] << SRC2[31:0])\r\n ELSE DEST[i+31:i] <- ZeroExtend(SRC1[i+31:i] << SRC2[i+31:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0;\r\n\r\n\r\n\r\n\r\n\r\nVPSLLVQ (VEX.128 version)\r\nCOUNT_0 <-SRC2[63 : 0];\r\nCOUNT_1 <-SRC2[127 : 64];\r\nIF COUNT_0 < 64THEN\r\nDEST[63:0] <-ZeroExtend(SRC1[63:0] << COUNT_0);\r\nELSE\r\nDEST[63:0] <-0;\r\nIF COUNT_1 < 64 THEN\r\nDEST[127:64] <-ZeroExtend(SRC1[127:64] << COUNT_1);\r\nELSE\r\nDEST[127:96] <-0;\r\nDEST[MAX_VL-1:128] <-0;\r\n\r\nVPSLLVQ (VEX.256 version)\r\nCOUNT_0 <-SRC2[63 : 0];\r\n (* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)\r\nCOUNT_3 <-SRC2[197 : 192];\r\nIF COUNT_0 < 64THEN\r\nDEST[63:0] <-ZeroExtend(SRC1[63:0] << COUNT_0);\r\nELSE\r\nDEST[63:0] <-0;\r\n (* Repeat shift operation for 2nd through 4th dwords *)\r\nIF COUNT_3 < 64 THEN\r\nDEST[255:192] <-ZeroExtend(SRC1[255:192] << COUNT_3);\r\nELSE\r\nDEST[255:192] <-0;\r\nDEST[MAX_VL-1:256] <- 0;\r\n\r\nVPSLLVQ (EVEX encoded version)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN DEST[i+63:i] <- ZeroExtend(SRC1[i+63:i] << SRC2[63:0])\r\n ELSE DEST[i+63:i] <- ZeroExtend(SRC1[i+63:i] << SRC2[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0;\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPSLLVW __m512i _mm512_sllv_epi16(__m512i a, __m512i cnt);\r\nVPSLLVW __m512i _mm512_mask_sllv_epi16(__m512i s, __mmask32 k, __m512i a, __m512i cnt);\r\nVPSLLVW __m512i _mm512_maskz_sllv_epi16( __mmask32 k, __m512i a, __m512i cnt);\r\nVPSLLVW __m256i _mm256_mask_sllv_epi16(__m256i s, __mmask16 k, __m256i a, __m256i cnt);\r\nVPSLLVW __m256i _mm256_maskz_sllv_epi16( __mmask16 k, __m256i a, __m256i cnt);\r\nVPSLLVW __m128i _mm_mask_sllv_epi16(__m128i s, __mmask8 k, __m128i a, __m128i cnt);\r\nVPSLLVW __m128i _mm_maskz_sllv_epi16( __mmask8 k, __m128i a, __m128i cnt);\r\nVPSLLVD __m512i _mm512_sllv_epi32(__m512i a, __m512i cnt);\r\nVPSLLVD __m512i _mm512_mask_sllv_epi32(__m512i s, __mmask16 k, __m512i a, __m512i cnt);\r\nVPSLLVD __m512i _mm512_maskz_sllv_epi32( __mmask16 k, __m512i a, __m512i cnt);\r\nVPSLLVD __m256i _mm256_mask_sllv_epi32(__m256i s, __mmask8 k, __m256i a, __m256i cnt);\r\nVPSLLVD __m256i _mm256_maskz_sllv_epi32( __mmask8 k, __m256i a, __m256i cnt);\r\nVPSLLVD __m128i _mm_mask_sllv_epi32(__m128i s, __mmask8 k, __m128i a, __m128i cnt);\r\nVPSLLVD __m128i _mm_maskz_sllv_epi32( __mmask8 k, __m128i a, __m128i cnt);\r\nVPSLLVQ __m512i _mm512_sllv_epi64(__m512i a, __m512i cnt);\r\nVPSLLVQ __m512i _mm512_mask_sllv_epi64(__m512i s, __mmask8 k, __m512i a, __m512i cnt);\r\nVPSLLVQ __m512i _mm512_maskz_sllv_epi64( __mmask8 k, __m512i a, __m512i cnt);\r\nVPSLLVD __m256i _mm256_mask_sllv_epi64(__m256i s, __mmask8 k, __m256i a, __m256i cnt);\r\nVPSLLVD __m256i _mm256_maskz_sllv_epi64( __mmask8 k, __m256i a, __m256i cnt);\r\nVPSLLVD __m128i _mm_mask_sllv_epi64(__m128i s, __mmask8 k, __m128i a, __m128i cnt);\r\nVPSLLVD __m128i _mm_maskz_sllv_epi64( __mmask8 k, __m128i a, __m128i cnt);\r\nVPSLLVD __m256i _mm256_sllv_epi32 (__m256i m, __m256i count)\r\nVPSLLVQ __m256i _mm256_sllv_epi64 (__m256i m, __m256i count)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 4.\r\nEVEX-encoded VPSLLVD/VPSLLVQ, see Exceptions Type E4.\r\nEVEX-encoded VPSLLVW, see Exceptions Type E4.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPSLLVW"
},
{
"description": "-R:VPSRAVW",
"mnem": "VPSRAVD"
},
{
"description": "-R:VPSRAVW",
"mnem": "VPSRAVQ"
},
{
"description": "VPSRAVW/VPSRAVD/VPSRAVQ-Variable Bit Shift Right Arithmetic\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.NDS.128.66.0F38.W0 46 /r RVM V/V AVX2 Shift doublewords in xmm2 right by amount specified\r\n VPSRAVD xmm1, xmm2, xmm3/m128 in the corresponding element of xmm3/m128 while\r\n shifting in sign bits.\r\n VEX.NDS.256.66.0F38.W0 46 /r RVM V/V AVX2 Shift doublewords in ymm2 right by amount specified\r\n VPSRAVD ymm1, ymm2, ymm3/m256 in the corresponding element of ymm3/m256 while\r\n shifting in sign bits.\r\n EVEX.NDS.128.66.0F38.W1 11 /r FVM V/V AVX512VL Shift words in xmm2 right by amount specified in the\r\n VPSRAVW xmm1 {k1}{z}, xmm2, AVX512BW corresponding element of xmm3/m128 while shifting\r\n xmm3/m128 in sign bits using writemask k1.\r\n EVEX.NDS.256.66.0F38.W1 11 /r FVM V/V AVX512VL Shift words in ymm2 right by amount specified in the\r\n VPSRAVW ymm1 {k1}{z}, ymm2, AVX512BW corresponding element of ymm3/m256 while shifting\r\n ymm3/m256 in sign bits using writemask k1.\r\n EVEX.NDS.512.66.0F38.W1 11 /r FVM V/V AVX512BW Shift words in zmm2 right by amount specified in the\r\n VPSRAVW zmm1 {k1}{z}, zmm2, corresponding element of zmm3/m512 while shifting\r\n zmm3/m512 in sign bits using writemask k1.\r\n EVEX.NDS.128.66.0F38.W0 46 /r FV V/V AVX512VL Shift doublewords in xmm2 right by amount specified\r\n VPSRAVD xmm1 {k1}{z}, xmm2, AVX512F in the corresponding element of\r\n xmm3/m128/m32bcst xmm3/m128/m32bcst while shifting in sign bits\r\n using writemask k1.\r\n EVEX.NDS.256.66.0F38.W0 46 /r FV V/V AVX512VL Shift doublewords in ymm2 right by amount specified\r\n VPSRAVD ymm1 {k1}{z}, ymm2, AVX512F in the corresponding element of\r\n ymm3/m256/m32bcst ymm3/m256/m32bcst while shifting in sign bits\r\n using writemask k1.\r\n EVEX.NDS.512.66.0F38.W0 46 /r FV V/V AVX512F Shift doublewords in zmm2 right by amount specified\r\n VPSRAVD zmm1 {k1}{z}, zmm2, in the corresponding element of\r\n zmm3/m512/m32bcst zmm3/m512/m32bcst while shifting in sign bits using\r\n writemask k1.\r\n EVEX.NDS.128.66.0F38.W1 46 /r FV V/V AVX512VL Shift quadwords in xmm2 right by amount specified\r\n VPSRAVQ xmm1 {k1}{z}, xmm2, AVX512F in the corresponding element of\r\n xmm3/m128/m64bcst xmm3/m128/m64bcst while shifting in sign bits\r\n using writemask k1.\r\n EVEX.NDS.256.66.0F38.W1 46 /r FV V/V AVX512VL Shift quadwords in ymm2 right by amount specified\r\n VPSRAVQ ymm1 {k1}{z}, ymm2, AVX512F in the corresponding element of\r\n ymm3/m256/m64bcst ymm3/m256/m64bcst while shifting in sign bits\r\n using writemask k1.\r\n\r\n EVEX.NDS.512.66.0F38.W1 46 /r FV V/V AVX512F Shift quadwords in zmm2 right by amount specified in\r\n VPSRAVQ zmm1 {k1}{z}, zmm2, the corresponding element of zmm3/m512/m64bcst\r\n zmm3/m512/m64bcst while shifting in sign bits using writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\n\r\n\r\n\r\nDescription\r\nShifts the bits in the individual data elements (word/doublewords/quadword) in the first source operand (the\r\nsecond operand) to the right by the number of bits specified in the count value of respective data elements in the\r\nsecond source operand (the third operand). As the bits in the data elements are shifted right, the empty high-order\r\nbits are set to the MSB (sign extension).\r\nThe count values are specified individually in each data element of the second source operand. If the unsigned\r\ninteger value specified in the respective data element of the second source operand is greater than 15 (for words),\r\n31 (for doublewords), or 63 (for a quadword), then the destination data element are filled with the corresponding\r\nsign bit of the source element.\r\nThe count values are specified individually in each data element of the second source operand. If the unsigned\r\ninteger value specified in the respective data element of the second source operand is greater than 16 (for word),\r\n31 (for doublewords), or 63 (for a quadword), then the destination data element are written with 0.\r\nVEX.128 encoded version: The destination and first source operands are XMM registers. The count operand can be\r\neither an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination\r\nregister are zeroed.\r\nVEX.256 encoded version: The destination and first source operands are YMM registers. The count operand can be\r\neither an YMM register or a 256-bit memory. Bits (MAX_VL-1:256) of the corresponding destination register are\r\nzeroed.\r\nEVEX.512/256/128 encoded VPSRAVD/W: The destination and first source operands are ZMM/YMM/XMM registers.\r\nThe count operand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a\r\n512/256/128-bit vector broadcasted from a 32/64-bit memory location. The destination is conditionally updated\r\nwith writemask k1.\r\nEVEX.512/256/128 encoded VPSRAVQ: The destination and first source operands are ZMM/YMM/XMM registers.\r\nThe count operand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination\r\nis conditionally updated with writemask k1.\r\n\r\nOperation\r\nVPSRAVW (EVEX encoded version)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n COUNT <- SRC2[i+3:i]\r\n IF COUNT < 16\r\n THEN DEST[i+15:i] <- SignExtend(SRC1[i+15:i] >> COUNT)\r\n ELSE\r\n FOR k<- 0 TO 15\r\n DEST[i+k] <- SRC1[i+15]\r\n ENDFOR;\r\n FI\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0;\r\n\r\n\r\n\r\n\r\n\r\nVPSRAVD (VEX.128 version)\r\nCOUNT_0 <- SRC2[31 : 0]\r\n (* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)\r\nCOUNT_3 <- SRC2[100 : 96];\r\nDEST[31:0] <- SignExtend(SRC1[31:0] >> COUNT_0);\r\n (* Repeat shift operation for 2nd through 4th dwords *)\r\nDEST[127:96] <- SignExtend(SRC1[127:96] >> COUNT_3);\r\nDEST[MAX_VL-1:128] <- 0;\r\n\r\nVPSRAVD (VEX.256 version)\r\nCOUNT_0 <- SRC2[31 : 0];\r\n (* Repeat Each COUNT_i for the 2nd through 8th dwords of SRC2*)\r\nCOUNT_7 <- SRC2[228 : 224];\r\nDEST[31:0] <- SignExtend(SRC1[31:0] >> COUNT_0);\r\n (* Repeat shift operation for 2nd through 7th dwords *)\r\nDEST[255:224] <- SignExtend(SRC1[255:224] >> COUNT_7);\r\nDEST[MAX_VL-1:256] <- 0;\r\n\r\nVPSRAVD (EVEX encoded version)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN\r\n COUNT <- SRC2[4:0]\r\n IF COUNT < 32\r\n THEN DEST[i+31:i] <- SignExtend(SRC1[i+31:i] >> COUNT)\r\n ELSE\r\n FOR k<- 0 TO 31\r\n DEST[i+k] <- SRC1[i+31]\r\n ENDFOR;\r\n FI\r\n ELSE\r\n COUNT <- SRC2[i+4:i]\r\n IF COUNT < 32\r\n THEN DEST[i+31:i] <- SignExtend(SRC1[i+31:i] >> COUNT)\r\n ELSE\r\n FOR k<- 0 TO 31\r\n DEST[i+k] <- SRC1[i+31]\r\n ENDFOR;\r\n FI\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[31:0] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0;\r\n\r\n\r\n\r\n\r\n\r\nVPSRAVQ (EVEX encoded version)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN\r\n COUNT <- SRC2[5:0]\r\n IF COUNT < 64\r\n THEN DEST[i+63:i] <- SignExtend(SRC1[i+63:i] >> COUNT)\r\n ELSE\r\n FOR k<- 0 TO 63\r\n DEST[i+k] <- SRC1[i+63]\r\n ENDFOR;\r\n FI\r\n ELSE\r\n COUNT <- SRC2[i+5:i]\r\n IF COUNT < 64\r\n THEN DEST[i+63:i] <- SignExtend(SRC1[i+63:i] >> COUNT)\r\n ELSE\r\n FOR k<- 0 TO 63\r\n DEST[i+k] <- SRC1[i+63]\r\n ENDFOR;\r\n FI\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[63:0] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0;\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPSRAVD __m512i _mm512_srav_epi32(__m512i a, __m512i cnt);\r\nVPSRAVD __m512i _mm512_mask_srav_epi32(__m512i s, __mmask16 m, __m512i a, __m512i cnt);\r\nVPSRAVD __m512i _mm512_maskz_srav_epi32(__mmask16 m, __m512i a, __m512i cnt);\r\nVPSRAVD __m256i _mm256_srav_epi32(__m256i a, __m256i cnt);\r\nVPSRAVD __m256i _mm256_mask_srav_epi32(__m256i s, __mmask8 m, __m256i a, __m256i cnt);\r\nVPSRAVD __m256i _mm256_maskz_srav_epi32(__mmask8 m, __m256i a, __m256i cnt);\r\nVPSRAVD __m128i _mm_srav_epi32(__m128i a, __m128i cnt);\r\nVPSRAVD __m128i _mm_mask_srav_epi32(__m128i s, __mmask8 m, __m128i a, __m128i cnt);\r\nVPSRAVD __m128i _mm_maskz_srav_epi32(__mmask8 m, __m128i a, __m128i cnt);\r\nVPSRAVQ __m512i _mm512_srav_epi64(__m512i a, __m512i cnt);\r\nVPSRAVQ __m512i _mm512_mask_srav_epi64(__m512i s, __mmask8 m, __m512i a, __m512i cnt);\r\nVPSRAVQ __m512i _mm512_maskz_srav_epi64( __mmask8 m, __m512i a, __m512i cnt);\r\nVPSRAVQ __m256i _mm256_srav_epi64(__m256i a, __m256i cnt);\r\nVPSRAVQ __m256i _mm256_mask_srav_epi64(__m256i s, __mmask8 m, __m256i a, __m256i cnt);\r\nVPSRAVQ __m256i _mm256_maskz_srav_epi64( __mmask8 m, __m256i a, __m256i cnt);\r\nVPSRAVQ __m128i _mm_srav_epi64(__m128i a, __m128i cnt);\r\nVPSRAVQ __m128i _mm_mask_srav_epi64(__m128i s, __mmask8 m, __m128i a, __m128i cnt);\r\nVPSRAVQ __m128i _mm_maskz_srav_epi64( __mmask8 m, __m128i a, __m128i cnt);\r\nVPSRAVW __m512i _mm512_srav_epi16(__m512i a, __m512i cnt);\r\nVPSRAVW __m512i _mm512_mask_srav_epi16(__m512i s, __mmask32 m, __m512i a, __m512i cnt);\r\nVPSRAVW __m512i _mm512_maskz_srav_epi16(__mmask32 m, __m512i a, __m512i cnt);\r\nVPSRAVW __m256i _mm256_srav_epi16(__m256i a, __m256i cnt);\r\nVPSRAVW __m256i _mm256_mask_srav_epi16(__m256i s, __mmask16 m, __m256i a, __m256i cnt);\r\nVPSRAVW __m256i _mm256_maskz_srav_epi16(__mmask16 m, __m256i a, __m256i cnt);\r\nVPSRAVW __m128i _mm_srav_epi16(__m128i a, __m128i cnt);\r\nVPSRAVW __m128i _mm_mask_srav_epi16(__m128i s, __mmask8 m, __m128i a, __m128i cnt);\r\nVPSRAVW __m128i _mm_maskz_srav_epi32(__mmask8 m, __m128i a, __m128i cnt);\r\nVPSRAVD __m256i _mm256_srav_epi32 (__m256i m, __m256i count)\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instruction, see Exceptions Type 4.\r\nEVEX-encoded instruction, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPSRAVW"
},
{
"description": "-R:VPSRLVW",
"mnem": "VPSRLVD"
},
{
"description": "-R:VPSRLVW",
"mnem": "VPSRLVQ"
},
{
"description": "VPSRLVW/VPSRLVD/VPSRLVQ-Variable Bit Shift Right Logical\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n VEX.NDS.128.66.0F38.W0 45 /r RVM V/V AVX2 Shift doublewords in xmm2 right by amount specified\r\n VPSRLVD xmm1, xmm2, xmm3/m128 in the corresponding element of xmm3/m128 while\r\n shifting in 0s.\r\n VEX.NDS.128.66.0F38.W1 45 /r RVM V/V AVX2 Shift quadwords in xmm2 right by amount specified in\r\n VPSRLVQ xmm1, xmm2, xmm3/m128 the corresponding element of xmm3/m128 while\r\n shifting in 0s.\r\n VEX.NDS.256.66.0F38.W0 45 /r RVM V/V AVX2 Shift doublewords in ymm2 right by amount specified\r\n VPSRLVD ymm1, ymm2, ymm3/m256 in the corresponding element of ymm3/m256 while\r\n shifting in 0s.\r\n VEX.NDS.256.66.0F38.W1 45 /r RVM V/V AVX2 Shift quadwords in ymm2 right by amount specified in\r\n VPSRLVQ ymm1, ymm2, ymm3/m256 the corresponding element of ymm3/m256 while\r\n shifting in 0s.\r\n EVEX.NDS.128.66.0F38.W1 10 /r FVM V/V AVX512VL Shift words in xmm2 right by amount specified in the\r\n VPSRLVW xmm1 {k1}{z}, xmm2, AVX512BW corresponding element of xmm3/m128 while shifting\r\n xmm3/m128 in 0s using writemask k1.\r\n EVEX.NDS.256.66.0F38.W1 10 /r FVM V/V AVX512VL Shift words in ymm2 right by amount specified in the\r\n VPSRLVW ymm1 {k1}{z}, ymm2, AVX512BW corresponding element of ymm3/m256 while shifting\r\n ymm3/m256 in 0s using writemask k1.\r\n EVEX.NDS.512.66.0F38.W1 10 /r FVM V/V AVX512BW Shift words in zmm2 right by amount specified in the\r\n VPSRLVW zmm1 {k1}{z}, zmm2, corresponding element of zmm3/m512 while shifting\r\n zmm3/m512 in 0s using writemask k1.\r\n EVEX.NDS.128.66.0F38.W0 45 /r FV V/V AVX512VL Shift doublewords in xmm2 right by amount specified\r\n VPSRLVD xmm1 {k1}{z}, xmm2, AVX512F in the corresponding element of xmm3/m128/m32bcst\r\n xmm3/m128/m32bcst while shifting in 0s using writemask k1.\r\n EVEX.NDS.256.66.0F38.W0 45 /r FV V/V AVX512VL Shift doublewords in ymm2 right by amount specified\r\n VPSRLVD ymm1 {k1}{z}, ymm2, AVX512F in the corresponding element of ymm3/m256/m32bcst\r\n ymm3/m256/m32bcst while shifting in 0s using writemask k1.\r\n EVEX.NDS.512.66.0F38.W0 45 /r FV V/V AVX512F Shift doublewords in zmm2 right by amount specified\r\n VPSRLVD zmm1 {k1}{z}, zmm2, in the corresponding element of zmm3/m512/m32bcst\r\n zmm3/m512/m32bcst while shifting in 0s using writemask k1.\r\n EVEX.NDS.128.66.0F38.W1 45 /r FV V/V AVX512VL Shift quadwords in xmm2 right by amount specified in\r\n VPSRLVQ xmm1 {k1}{z}, xmm2, AVX512F the corresponding element of xmm3/m128/m64bcst\r\n xmm3/m128/m64bcst while shifting in 0s using writemask k1.\r\n EVEX.NDS.256.66.0F38.W1 45 /r FV V/V AVX512VL Shift quadwords in ymm2 right by amount specified in\r\n VPSRLVQ ymm1 {k1}{z}, ymm2, AVX512F the corresponding element of ymm3/m256/m64bcst\r\n ymm3/m256/m64bcst while shifting in 0s using writemask k1.\r\n EVEX.NDS.512.66.0F38.W1 45 /r FV V/V AVX512F Shift quadwords in zmm2 right by amount specified in\r\n VPSRLVQ zmm1 {k1}{z}, zmm2, the corresponding element of zmm3/m512/m64bcst\r\n zmm3/m512/m64bcst while shifting in 0s using writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\n\r\n\r\n\r\nDescription\r\nShifts the bits in the individual data elements (words, doublewords or quadword) in the first source operand to the\r\nright by the count value of respective data elements in the second source operand. As the bits in the data elements\r\nare shifted right, the empty high-order bits are cleared (set to 0).\r\nThe count values are specified individually in each data element of the second source operand. If the unsigned\r\ninteger value specified in the respective data element of the second source operand is greater than 15 (for word),\r\n31 (for doublewords), or 63 (for a quadword), then the destination data element are written with 0.\r\nVEX.128 encoded version: The destination and first source operands are XMM registers. The count operand can be\r\neither an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination\r\nregister are zeroed.\r\nVEX.256 encoded version: The destination and first source operands are YMM registers. The count operand can be\r\neither an YMM register or a 256-bit memory. Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed.\r\nEVEX encoded VPSRLVD/Q: The destination and first source operands are ZMM/YMM/XMM registers. The count\r\noperand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512-bit vector broad-\r\ncasted from a 32/64-bit memory location. The destination is conditionally updated with writemask k1.\r\nEVEX encoded VPSRLVW: The destination and first source operands are ZMM/YMM/XMM registers. The count\r\noperand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination is condition-\r\nally updated with writemask k1.\r\n\r\nOperation\r\nVPSRLVW (EVEX encoded version)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+15:i] <- ZeroExtend(SRC1[i+15:i] >> SRC2[i+15:i])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+15:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+15:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0;\r\n\r\n\r\n\r\n\r\n\r\nVPSRLVD (VEX.128 version)\r\nCOUNT_0 <-SRC2[31 : 0]\r\n (* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)\r\nCOUNT_3 <-SRC2[127 : 96];\r\nIF COUNT_0 < 32 THEN\r\n DEST[31:0] <-ZeroExtend(SRC1[31:0] >> COUNT_0);\r\nELSE\r\n DEST[31:0] <-0;\r\n (* Repeat shift operation for 2nd through 4th dwords *)\r\nIF COUNT_3 < 32 THEN\r\n DEST[127:96] <-ZeroExtend(SRC1[127:96] >> COUNT_3);\r\nELSE\r\n DEST[127:96] <-0;\r\nDEST[MAX_VL-1:128] <-0;\r\n\r\nVPSRLVD (VEX.256 version)\r\nCOUNT_0 <-SRC2[31 : 0];\r\n (* Repeat Each COUNT_i for the 2nd through 7th dwords of SRC2*)\r\nCOUNT_7 <-SRC2[255 : 224];\r\nIF COUNT_0 < 32 THEN\r\nDEST[31:0] <-ZeroExtend(SRC1[31:0] >> COUNT_0);\r\nELSE\r\nDEST[31:0] <-0;\r\n (* Repeat shift operation for 2nd through 7th dwords *)\r\nIF COUNT_7 < 32 THEN\r\n DEST[255:224] <-ZeroExtend(SRC1[255:224] >> COUNT_7);\r\nELSE\r\n DEST[255:224] <-0;\r\nDEST[MAX_VL-1:256] <-0;\r\n\r\nVPSRLVD (EVEX encoded version)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN DEST[i+31:i] <- ZeroExtend(SRC1[i+31:i] >> SRC2[31:0])\r\n ELSE DEST[i+31:i] <- ZeroExtend(SRC1[i+31:i] >> SRC2[i+31:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0;\r\n\r\n\r\n\r\n\r\n\r\nVPSRLVQ (VEX.128 version)\r\nCOUNT_0 <-SRC2[63 : 0];\r\nCOUNT_1 <-SRC2[127 : 64];\r\nIF COUNT_0 < 64 THEN\r\n DEST[63:0] <-ZeroExtend(SRC1[63:0] >> COUNT_0);\r\nELSE\r\n DEST[63:0] <-0;\r\nIF COUNT_1 < 64 THEN\r\n DEST[127:64] <-ZeroExtend(SRC1[127:64] >> COUNT_1);\r\nELSE\r\n DEST[127:64] <-0;\r\nDEST[MAX_VL-1:128] <-0;\r\n\r\nVPSRLVQ (VEX.256 version)\r\nCOUNT_0 <-SRC2[63 : 0];\r\n (* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)\r\nCOUNT_3 <-SRC2[255 : 192];\r\nIF COUNT_0 < 64 THEN\r\nDEST[63:0] <-ZeroExtend(SRC1[63:0] >> COUNT_0);\r\nELSE\r\nDEST[63:0] <-0;\r\n (* Repeat shift operation for 2nd through 4th dwords *)\r\nIF COUNT_3 < 64 THEN\r\n DEST[255:192] <-ZeroExtend(SRC1[255:192] >> COUNT_3);\r\nELSE\r\n DEST[255:192] <-0;\r\nDEST[MAX_VL-1:256] <-0;\r\n\r\nVPSRLVQ (EVEX encoded version)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN DEST[i+63:i] <- ZeroExtend(SRC1[i+63:i] >> SRC2[63:0])\r\n ELSE DEST[i+63:i] <- ZeroExtend(SRC1[i+63:i] >> SRC2[i+63:i])\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0;\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPSRLVW __m512i _mm512_srlv_epi16(__m512i a, __m512i cnt);\r\nVPSRLVW __m512i _mm512_mask_srlv_epi16(__m512i s, __mmask32 k, __m512i a, __m512i cnt);\r\nVPSRLVW __m512i _mm512_maskz_srlv_epi16( __mmask32 k, __m512i a, __m512i cnt);\r\nVPSRLVW __m256i _mm256_mask_srlv_epi16(__m256i s, __mmask16 k, __m256i a, __m256i cnt);\r\nVPSRLVW __m256i _mm256_maskz_srlv_epi16( __mmask16 k, __m256i a, __m256i cnt);\r\nVPSRLVW __m128i _mm_mask_srlv_epi16(__m128i s, __mmask8 k, __m128i a, __m128i cnt);\r\nVPSRLVW __m128i _mm_maskz_srlv_epi16( __mmask8 k, __m128i a, __m128i cnt);\r\nVPSRLVW __m256i _mm256_srlv_epi32 (__m256i m, __m256i count)\r\nVPSRLVD __m512i _mm512_srlv_epi32(__m512i a, __m512i cnt);\r\nVPSRLVD __m512i _mm512_mask_srlv_epi32(__m512i s, __mmask16 k, __m512i a, __m512i cnt);\r\nVPSRLVD __m512i _mm512_maskz_srlv_epi32( __mmask16 k, __m512i a, __m512i cnt);\r\nVPSRLVD __m256i _mm256_mask_srlv_epi32(__m256i s, __mmask8 k, __m256i a, __m256i cnt);\r\nVPSRLVD __m256i _mm256_maskz_srlv_epi32( __mmask8 k, __m256i a, __m256i cnt);\r\nVPSRLVD __m128i _mm_mask_srlv_epi32(__m128i s, __mmask8 k, __m128i a, __m128i cnt);\r\nVPSRLVD __m128i _mm_maskz_srlv_epi32( __mmask8 k, __m128i a, __m128i cnt);\r\nVPSRLVQ __m512i _mm512_srlv_epi64(__m512i a, __m512i cnt);\r\nVPSRLVQ __m512i _mm512_mask_srlv_epi64(__m512i s, __mmask8 k, __m512i a, __m512i cnt);\r\nVPSRLVQ __m512i _mm512_maskz_srlv_epi64( __mmask8 k, __m512i a, __m512i cnt);\r\nVPSRLVQ __m256i _mm256_mask_srlv_epi64(__m256i s, __mmask8 k, __m256i a, __m256i cnt);\r\nVPSRLVQ __m256i _mm256_maskz_srlv_epi64( __mmask8 k, __m256i a, __m256i cnt);\r\nVPSRLVQ __m128i _mm_mask_srlv_epi64(__m128i s, __mmask8 k, __m128i a, __m128i cnt);\r\nVPSRLVQ __m128i _mm_maskz_srlv_epi64( __mmask8 k, __m128i a, __m128i cnt);\r\nVPSRLVQ __m256i _mm256_srlv_epi64 (__m256i m, __m256i count)\r\nVPSRLVD __m128i _mm_srlv_epi32( __m128i a, __m128i cnt);\r\nVPSRLVQ __m128i _mm_srlv_epi64( __m128i a, __m128i cnt);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nVEX-encoded instructions, see Exceptions Type 4.\r\nEVEX-encoded VPSRLVD/Q, see Exceptions Type E4.\r\nEVEX-encoded VPSRLVW, see Exceptions Type E4.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPSRLVW"
},
{
"description": "VPTERNLOGD/VPTERNLOGQ-Bitwise Ternary Logic\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.DDS.128.66.0F3A.W0 25 /r ib FV V/V AVX512VL Bitwise ternary logic taking xmm1, xmm2 and\r\n VPTERNLOGD xmm1 {k1}{z}, xmm2, AVX512F xmm3/m128/m32bcst as source operands and writing\r\n xmm3/m128/m32bcst, imm8 the result to xmm1 under writemask k1 with dword\r\n granularity. The immediate value determines the specific\r\n binary function being implemented.\r\n EVEX.DDS.256.66.0F3A.W0 25 /r ib FV V/V AVX512VL Bitwise ternary logic taking ymm1, ymm2 and\r\n VPTERNLOGD ymm1 {k1}{z}, ymm2, AVX512F ymm3/m256/m32bcst as source operands and writing\r\n ymm3/m256/m32bcst, imm8 the result to ymm1 under writemask k1 with dword\r\n granularity. The immediate value determines the specific\r\n binary function being implemented.\r\n EVEX.DDS.512.66.0F3A.W0 25 /r ib FV V/V AVX512F Bitwise ternary logic taking zmm1, zmm2 and\r\n VPTERNLOGD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst as source operands and writing\r\n zmm3/m512/m32bcst, imm8 the result to zmm1 under writemask k1 with dword\r\n granularity. The immediate value determines the specific\r\n binary function being implemented.\r\n EVEX.DDS.128.66.0F3A.W1 25 /r ib FV V/V AVX512VL Bitwise ternary logic taking xmm1, xmm2 and\r\n VPTERNLOGQ xmm1 {k1}{z}, xmm2, AVX512F xmm3/m128/m64bcst as source operands and writing\r\n xmm3/m128/m64bcst, imm8 the result to xmm1 under writemask k1 with qword\r\n granularity. The immediate value determines the specific\r\n binary function being implemented.\r\n EVEX.DDS.256.66.0F3A.W1 25 /r ib FV V/V AVX512VL Bitwise ternary logic taking ymm1, ymm2 and\r\n VPTERNLOGQ ymm1 {k1}{z}, ymm2, AVX512F ymm3/m256/m64bcst as source operands and writing\r\n ymm3/m256/m64bcst, imm8 the result to ymm1 under writemask k1 with qword\r\n granularity. The immediate value determines the specific\r\n binary function being implemented.\r\n EVEX.DDS.512.66.0F3A.W1 25 /r ib FV V/V AVX512F Bitwise ternary logic taking zmm1, zmm2 and\r\n VPTERNLOGQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst as source operands and writing\r\n zmm3/m512/m64bcst, imm8 the result to zmm1 under writemask k1 with qword\r\n granularity. The immediate value determines the specific\r\n binary function being implemented.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) Imm8\r\n\r\nDescription\r\nVPTERNLOGD/Q takes three bit vectors of 512-bit length (in the first, second and third operand) as input data to\r\nform a set of 512 indices, each index is comprised of one bit from each input vector. The imm8 byte specifies a\r\nboolean logic table producing a binary value for each 3-bit index value. The final 512-bit boolean result is written\r\nto the destination operand (the first operand) using the writemask k1 with the granularity of doubleword element\r\nor quadword element into the destination.\r\nThe destination operand is a ZMM (EVEX.512)/YMM (EVEX.256)/XMM (EVEX.128) register. The first source operand\r\nis a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit\r\nmemory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location The destination\r\noperand is a ZMM register conditionally updated with writemask k1.\r\n\r\n\r\n\r\n\r\n\r\nTable 5-11 shows two examples of Boolean functions specified by immediate values 0xE2 and 0xE4, with the look\r\nup result listed in the fourth column following the three columns containing all possible values of the 3-bit index.\r\n\r\n Table 5-11. Examples of VPTERNLOGD/Q Imm8 Boolean Function and Input Index Values\r\n VPTERNLOGD reg1, reg2, src3, 0xE2 Bit Result with VPTERNLOGD reg1, reg2, src3, 0xE4 Bit Result with\r\n Imm8=0xE2 Imm8=0xE4\r\n Bit(reg1) Bit(reg2) Bit(src3) Bit(reg1) Bit(reg2) Bit(src3)\r\n 0 0 0 0 0 0 0 0\r\n 0 0 1 1 0 0 1 0\r\n 0 1 0 0 0 1 0 1\r\n 0 1 1 0 0 1 1 0\r\n 1 0 0 0 1 0 0 0\r\n 1 0 1 1 1 0 1 1\r\n 1 1 0 1 1 1 0 1\r\n 1 1 1 1 1 1 1 1\r\n\r\nSpecifying different values in imm8 will allow any arbitrary three-input Boolean functions to be implemented in\r\nsoftware using VPTERNLOGD/Q. Table 5-1 and Table 5-2 provide a mapping of all 256 possible imm8 values to\r\nvarious Boolean expressions.\r\n\r\nOperation\r\nVPTERNLOGD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n FOR k <- 0 TO 31\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN DEST[j][k] <- imm[(DEST[i+k] << 2) + (SRC1[ i+k ] << 1) + SRC2[ k ]]\r\n ELSE DEST[j][k] <- imm[(DEST[i+k] << 2) + (SRC1[ i+k ] << 1) + SRC2[ i+k ]]\r\n FI;\r\n ; table lookup of immediate bellow;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31+i:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[31+i:i] <- 0\r\n FI;\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVPTERNLOGQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n FOR k <- 0 TO 63\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN DEST[j][k] <- imm[(DEST[i+k] << 2) + (SRC1[ i+k ] << 1) + SRC2[ k ]]\r\n ELSE DEST[j][k] <- imm[(DEST[i+k] << 2) + (SRC1[ i+k ] << 1) + SRC2[ i+k ]]\r\n FI; ; table lookup of immediate bellow;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63+i:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[63+i:i] <- 0\r\n FI;\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPTERNLOGD __m512i _mm512_ternarylogic_epi32(__m512i a, __m512i b, int imm);\r\nVPTERNLOGD __m512i _mm512_mask_ternarylogic_epi32(__m512i s, __mmask16 m, __m512i a, __m512i b, int imm);\r\nVPTERNLOGD __m512i _mm512_maskz_ternarylogic_epi32(__mmask m, __m512i a, __m512i b, int imm);\r\nVPTERNLOGD __m256i _mm256_ternarylogic_epi32(__m256i a, __m256i b, int imm);\r\nVPTERNLOGD __m256i _mm256_mask_ternarylogic_epi32(__m256i s, __mmask8 m, __m256i a, __m256i b, int imm);\r\nVPTERNLOGD __m256i _mm256_maskz_ternarylogic_epi32( __mmask8 m, __m256i a, __m256i b, int imm);\r\nVPTERNLOGD __m128i _mm_ternarylogic_epi32(__m128i a, __m128i b, int imm);\r\nVPTERNLOGD __m128i _mm_mask_ternarylogic_epi32(__m128i s, __mmask8 m, __m128i a, __m128i b, int imm);\r\nVPTERNLOGD __m128i _mm_maskz_ternarylogic_epi32( __mmask8 m, __m128i a, __m128i b, int imm);\r\nVPTERNLOGQ __m512i _mm512_ternarylogic_epi64(__m512i a, __m512i b, int imm);\r\nVPTERNLOGQ __m512i _mm512_mask_ternarylogic_epi64(__m512i s, __mmask8 m, __m512i a, __m512i b, int imm);\r\nVPTERNLOGQ __m512i _mm512_maskz_ternarylogic_epi64( __mmask8 m, __m512i a, __m512i b, int imm);\r\nVPTERNLOGQ __m256i _mm256_ternarylogic_epi64(__m256i a, __m256i b, int imm);\r\nVPTERNLOGQ __m256i _mm256_mask_ternarylogic_epi64(__m256i s, __mmask8 m, __m256i a, __m256i b, int imm);\r\nVPTERNLOGQ __m256i _mm256_maskz_ternarylogic_epi64( __mmask8 m, __m256i a, __m256i b, int imm);\r\nVPTERNLOGQ __m128i _mm_ternarylogic_epi64(__m128i a, __m128i b, int imm);\r\nVPTERNLOGQ __m128i _mm_mask_ternarylogic_epi64(__m128i s, __mmask8 m, __m128i a, __m128i b, int imm);\r\nVPTERNLOGQ __m128i _mm_maskz_ternarylogic_epi64( __mmask8 m, __m128i a, __m128i b, int imm);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPTERNLOGD"
},
{
"description": "-R:VPTERNLOGD",
"mnem": "VPTERNLOGQ"
},
{
"description": "VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ-Logical AND and Set Mask\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.128.66.0F38.W0 26 /r FVM V/V AVX512VL Bitwise AND of packed byte integers in xmm2 and\r\n VPTESTMB k2 {k1}, xmm2, AVX512BW xmm3/m128 and set mask k2 to reflect the zero/non-zero\r\n xmm3/m128 status of each element of the result, under writemask k1.\r\n EVEX.NDS.256.66.0F38.W0 26 /r FVM V/V AVX512VL Bitwise AND of packed byte integers in ymm2 and\r\n VPTESTMB k2 {k1}, ymm2, AVX512BW ymm3/m256 and set mask k2 to reflect the zero/non-zero\r\n ymm3/m256 status of each element of the result, under writemask k1.\r\n EVEX.NDS.512.66.0F38.W0 26 /r FVM V/V AVX512BW Bitwise AND of packed byte integers in zmm2 and\r\n VPTESTMB k2 {k1}, zmm2, zmm3/m512 and set mask k2 to reflect the zero/non-zero\r\n zmm3/m512 status of each element of the result, under writemask k1.\r\n EVEX.NDS.128.66.0F38.W1 26 /r FVM V/V AVX512VL Bitwise AND of packed word integers in xmm2 and\r\n VPTESTMW k2 {k1}, xmm2, AVX512BW xmm3/m128 and set mask k2 to reflect the zero/non-zero\r\n xmm3/m128 status of each element of the result, under writemask k1.\r\n EVEX.NDS.256.66.0F38.W1 26 /r FVM V/V AVX512VL Bitwise AND of packed word integers in ymm2 and\r\n VPTESTMW k2 {k1}, ymm2, AVX512BW ymm3/m256 and set mask k2 to reflect the zero/non-zero\r\n ymm3/m256 status of each element of the result, under writemask k1.\r\n EVEX.NDS.512.66.0F38.W1 26 /r FVM V/V AVX512BW Bitwise AND of packed word integers in zmm2 and\r\n VPTESTMW k2 {k1}, zmm2, zmm3/m512 and set mask k2 to reflect the zero/non-zero\r\n zmm3/m512 status of each element of the result, under writemask k1.\r\n EVEX.NDS.128.66.0F38.W0 27 /r FV V/V AVX512VL Bitwise AND of packed doubleword integers in xmm2 and\r\n VPTESTMD k2 {k1}, xmm2, AVX512F xmm3/m128/m32bcst and set mask k2 to reflect the\r\n xmm3/m128/m32bcst zero/non-zero status of each element of the result, under\r\n writemask k1.\r\n EVEX.NDS.256.66.0F38.W0 27 /r FV V/V AVX512VL Bitwise AND of packed doubleword integers in ymm2 and\r\n VPTESTMD k2 {k1}, ymm2, AVX512F ymm3/m256/m32bcst and set mask k2 to reflect the\r\n ymm3/m256/m32bcst zero/non-zero status of each element of the result, under\r\n writemask k1.\r\n EVEX.NDS.512.66.0F38.W0 27 /r FV V/V AVX512F Bitwise AND of packed doubleword integers in zmm2 and\r\n VPTESTMD k2 {k1}, zmm2, zmm3/m512/m32bcst and set mask k2 to reflect the\r\n zmm3/m512/m32bcst zero/non-zero status of each element of the result, under\r\n writemask k1.\r\n EVEX.NDS.128.66.0F38.W1 27 /r FV V/V AVX512VL Bitwise AND of packed quadword integers in xmm2 and\r\n VPTESTMQ k2 {k1}, xmm2, AVX512F xmm3/m128/m64bcst and set mask k2 to reflect the\r\n xmm3/m128/m64bcst zero/non-zero status of each element of the result, under\r\n writemask k1.\r\n EVEX.NDS.256.66.0F38.W1 27 /r FV V/V AVX512VL Bitwise AND of packed quadword integers in ymm2 and\r\n VPTESTMQ k2 {k1}, ymm2, AVX512F ymm3/m256/m64bcst and set mask k2 to reflect the\r\n ymm3/m256/m64bcst zero/non-zero status of each element of the result, under\r\n writemask k1.\r\n EVEX.NDS.512.66.0F38.W1 27 /r FV V/V AVX512F Bitwise AND of packed quadword integers in zmm2 and\r\n VPTESTMQ k2 {k1}, zmm2, zmm3/m512/m64bcst and set mask k2 to reflect the\r\n zmm3/m512/m64bcst zero/non-zero status of each element of the result, under\r\n writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\n\r\n\r\n\r\n\r\nDescription\r\nPerforms a bitwise logical AND operation on the first source operand (the second operand) and second source\r\noperand (the third operand) and stores the result in the destination operand (the first operand) under the\r\nwritemask. Each bit of the result is set to 1 if the bitwise AND of the corresponding elements of the first and second\r\nsrc operands is non-zero; otherwise it is set to 0.\r\nVPTESTMD/VPTESTMQ: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a\r\nZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a\r\n32/64-bit memory location. The destination operand is a mask register updated under the writemask.\r\nVPTESTMB/VPTESTMW: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a\r\nZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand is a mask register\r\nupdated under the writemask.\r\n\r\nOperation\r\nVPTESTMB (EVEX encoded versions)\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\nFOR j <- 0 TO KL-1\r\n i<-j*8\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[j] <- (SRC1[i+7:i] BITWISE AND SRC2[i+7:i] != 0)? 1 : 0;\r\n ELSE DEST[j] = 0 ; zeroing-masking only\r\n FI;\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\nVPTESTMW (EVEX encoded versions)\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 16\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[j] <- (SRC1[i+15:i] BITWISE AND SRC2[i+15:i] != 0)? 1 : 0;\r\n ELSE DEST[j] = 0 ; zeroing-masking only\r\n FI;\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\nVPTESTMD (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN DEST[j] <- (SRC1[i+31:i] BITWISE AND SRC2[31:0] != 0)? 1 : 0;\r\n ELSE DEST[j] <- (SRC1[i+31:i] BITWISE AND SRC2[i+31:i] != 0)? 1 : 0;\r\n FI;\r\n ELSE DEST[j] <- 0 ; zeroing-masking only\r\n FI;\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVPTESTMQ (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN DEST[j] <- (SRC1[i+63:i] BITWISE AND SRC2[63:0] != 0)? 1 : 0;\r\n ELSE DEST[j] <- (SRC1[i+63:i] BITWISE AND SRC2[i+63:i] != 0)? 1 : 0;\r\n FI;\r\n ELSE DEST[j] <- 0 ; zeroing-masking only\r\n FI;\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalents\r\nVPTESTMB __mmask64 _mm512_test_epi8_mask( __m512i a, __m512i b);\r\nVPTESTMB __mmask64 _mm512_mask_test_epi8_mask(__mmask64, __m512i a, __m512i b);\r\nVPTESTMW __mmask32 _mm512_test_epi16_mask( __m512i a, __m512i b);\r\nVPTESTMW __mmask32 _mm512_mask_test_epi16_mask(__mmask32, __m512i a, __m512i b);\r\nVPTESTMD __mmask16 _mm512_test_epi32_mask( __m512i a, __m512i b);\r\nVPTESTMD __mmask16 _mm512_mask_test_epi32_mask(__mmask16, __m512i a, __m512i b);\r\nVPTESTMQ __mmask8 _mm512_test_epi64_mask(__m512i a, __m512i b);\r\nVPTESTMQ __mmask8 _mm512_mask_test_epi64_mask(__mmask8, __m512i a, __m512i b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nVPTESTMD/Q: See Exceptions Type E4.\r\nVPTESTMB/W: See Exceptions Type E4.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPTESTMB"
},
{
"description": "-R:VPTESTMB",
"mnem": "VPTESTMD"
},
{
"description": "-R:VPTESTMB",
"mnem": "VPTESTMQ"
},
{
"description": "-R:VPTESTMB",
"mnem": "VPTESTMW"
},
{
"description": "VPTESTNMB/VPTESTNMW/VPTESTNMD/VPTESTNMQ-Logical NAND and Set\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode\r\n Support\r\n EVEX.NDS.128.F3.0F38.W0 26 /r FVM V/V AVX512VL Bitwise NAND of packed byte integers in xmm2 and\r\n VPTESTNMB k2 {k1}, xmm2, AVX512BW xmm3/m128 and set mask k2 to reflect the zero/non-zero\r\n xmm3/m128 status of each element of the result, under writemask k1.\r\n\r\n EVEX.NDS.256.F3.0F38.W0 26 /r FVM V/V AVX512VL Bitwise NAND of packed byte integers in ymm2 and\r\n VPTESTNMB k2 {k1}, ymm2, AVX512BW ymm3/m256 and set mask k2 to reflect the zero/non-zero\r\n ymm3/m256 status of each element of the result, under writemask k1.\r\n\r\n EVEX.NDS.512.F3.0F38.W0 26 /r FVM V/V AVX512F Bitwise NAND of packed byte integers in zmm2 and\r\n VPTESTNMB k2 {k1}, zmm2, AVX512BW zmm3/m512 and set mask k2 to reflect the zero/non-zero\r\n zmm3/m512 status of each element of the result, under writemask k1.\r\n\r\n EVEX.NDS.128.F3.0F38.W1 26 /r FVM V/V AVX512VL Bitwise NAND of packed word integers in xmm2 and\r\n VPTESTNMW k2 {k1}, xmm2, AVX512BW xmm3/m128 and set mask k2 to reflect the zero/non-zero\r\n xmm3/m128 status of each element of the result, under writemask k1.\r\n\r\n EVEX.NDS.256.F3.0F38.W1 26 /r FVM V/V AVX512VL Bitwise NAND of packed word integers in ymm2 and\r\n VPTESTNMW k2 {k1}, ymm2, AVX512BW ymm3/m256 and set mask k2 to reflect the zero/non-zero\r\n ymm3/m256 status of each element of the result, under writemask k1.\r\n\r\n EVEX.NDS.512.F3.0F38.W1 26 /r FVM V/V AVX512F Bitwise NAND of packed word integers in zmm2 and\r\n VPTESTNMW k2 {k1}, zmm2, AVX512BW zmm3/m512 and set mask k2 to reflect the zero/non-zero\r\n zmm3/m512 status of each element of the result, under writemask k1.\r\n\r\n EVEX.NDS.128.F3.0F38.W0 27 /r FV V/V AVX512VL Bitwise NAND of packed doubleword integers in xmm2 and\r\n VPTESTNMD k2 {k1}, xmm2, AVX512F xmm3/m128/m32bcst and set mask k2 to reflect the\r\n xmm3/m128/m32bcst zero/non-zero status of each element of the result, under\r\n writemask k1.\r\n EVEX.NDS.256.F3.0F38.W0 27 /r FV V/V AVX512VL Bitwise NAND of packed doubleword integers in ymm2 and\r\n VPTESTNMD k2 {k1}, ymm2, AVX512F ymm3/m256/m32bcst and set mask k2 to reflect the\r\n ymm3/m256/m32bcst zero/non-zero status of each element of the result, under\r\n writemask k1.\r\n EVEX.NDS.512.F3.0F38.W0 27 /r FV V/V AVX512F Bitwise NAND of packed doubleword integers in zmm2 and\r\n VPTESTNMD k2 {k1}, zmm2, zmm3/m512/m32bcst and set mask k2 to reflect the\r\n zmm3/m512/m32bcst zero/non-zero status of each element of the result, under\r\n writemask k1.\r\n EVEX.NDS.128.F3.0F38.W1 27 /r FV V/V AVX512VL Bitwise NAND of packed quadword integers in xmm2 and\r\n VPTESTNMQ k2 {k1}, xmm2, AVX512F xmm3/m128/m64bcst and set mask k2 to reflect the\r\n xmm3/m128/m64bcst zero/non-zero status of each element of the result, under\r\n writemask k1.\r\n EVEX.NDS.256.F3.0F38.W1 27 /r FV V/V AVX512VL Bitwise NAND of packed quadword integers in ymm2 and\r\n VPTESTNMQ k2 {k1}, ymm2, AVX512F ymm3/m256/m64bcst and set mask k2 to reflect the\r\n ymm3/m256/m64bcst zero/non-zero status of each element of the result, under\r\n writemask k1.\r\n EVEX.NDS.512.F3.0F38.W1 27 /r FV V/V AVX512F Bitwise NAND of packed quadword integers in zmm2 and\r\n VPTESTNMQ k2 {k1}, zmm2, zmm3/m512/m64bcst and set mask k2 to reflect the\r\n zmm3/m512/m64bcst zero/non-zero status of each element of the result, under\r\n writemask k1.\r\n\r\n\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a bitwise logical NAND operation on the byte/word/doubleword/quadword element of the first source\r\noperand (the second operand) with the corresponding element of the second source operand (the third operand)\r\nand stores the logical comparison result into each bit of the destination operand (the first operand) according to the\r\nwritemask k1. Each bit of the result is set to 1 if the bitwise AND of the corresponding elements of the first and\r\nsecond src operands is zero; otherwise it is set to 0.\r\nEVEX encoded VPTESTNMD/Q: The first source operand is a ZMM/YMM/XMM registers. The second source operand\r\ncan be a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted\r\nfrom a 32/64-bit memory location. The destination is updated according to the writemask.\r\nEVEX encoded VPTESTNMB/W: The first source operand is a ZMM/YMM/XMM registers. The second source operand\r\ncan be a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination is updated according to the\r\nwritemask.\r\n\r\nOperation\r\nVPTESTNMB\r\n(KL, VL) = (16, 128), (32, 256), (64, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j*8\r\n IF MaskBit(j) OR *no writemask*\r\n THEN\r\n DEST[j] <- (SRC1[i+7:i] BITWISE AND SRC2[i+7:i] == 0)? 1 : 0\r\n ELSE DEST[j] <- 0; zeroing masking only\r\n FI\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\nVPTESTNMW\r\n(KL, VL) = (8, 128), (16, 256), (32, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j*16\r\n IF MaskBit(j) OR *no writemask*\r\n THEN\r\n DEST[j] <- (SRC1[i+15:i] BITWISE AND SRC2[i+15:i] == 0)? 1 : 0\r\n ELSE DEST[j] <- 0; zeroing masking only\r\n FI\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVPTESTNMD\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j*32\r\n IF MaskBit(j) OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN DEST[i+31:i] <- (SRC1[i+31:i] BITWISE AND SRC2[31:0] == 0)? 1 : 0\r\n ELSE DEST[j] <- (SRC1[i+31:i] BITWISE AND SRC2[i+31:i] == 0)? 1 : 0\r\n FI\r\n ELSE DEST[j] <- 0; zeroing masking only\r\n FI\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\nVPTESTNMQ\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j*64\r\n IF MaskBit(j) OR *no writemask*\r\n THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN DEST[j] <- (SRC1[i+63:i] BITWISE AND SRC2[63:0] != 0)? 1 : 0;\r\n ELSE DEST[j] <- (SRC1[i+63:i] BITWISE AND SRC2[i+63:i] != 0)? 1 : 0;\r\n FI;\r\n ELSE DEST[j] <- 0; zeroing masking only\r\n FI\r\nENDFOR\r\nDEST[MAX_KL-1:KL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVPTESTNMB __mmask64 _mm512_testn_epi8_mask( __m512i a, __m512i b);\r\nVPTESTNMB __mmask64 _mm512_mask_testn_epi8_mask(__mmask64, __m512i a, __m512i b);\r\nVPTESTNMB __mmask32 _mm256_testn_epi8_mask(__m256i a, __m256i b);\r\nVPTESTNMB __mmask32 _mm256_mask_testn_epi8_mask(__mmask32, __m256i a, __m256i b);\r\nVPTESTNMB __mmask16 _mm_testn_epi8_mask(__m128i a, __m128i b);\r\nVPTESTNMB __mmask16 _mm_mask_testn_epi8_mask(__mmask16, __m128i a, __m128i b);\r\nVPTESTNMW __mmask32 _mm512_testn_epi16_mask( __m512i a, __m512i b);\r\nVPTESTNMW __mmask32 _mm512_mask_testn_epi16_mask(__mmask32, __m512i a, __m512i b);\r\nVPTESTNMW __mmask16 _mm256_testn_epi16_mask(__m256i a, __m256i b);\r\nVPTESTNMW __mmask16 _mm256_mask_testn_epi16_mask(__mmask16, __m256i a, __m256i b);\r\nVPTESTNMW __mmask8 _mm_testn_epi16_mask(__m128i a, __m128i b);\r\nVPTESTNMW __mmask8 _mm_mask_testn_epi16_mask(__mmask8, __m128i a, __m128i b);\r\nVPTESTNMD __mmask16 _mm512_testn_epi32_mask( __m512i a, __m512i b);\r\nVPTESTNMD __mmask16 _mm512_mask_testn_epi32_mask(__mmask16, __m512i a, __m512i b);\r\nVPTESTNMD __mmask8 _mm256_testn_epi32_mask(__m256i a, __m256i b);\r\nVPTESTNMD __mmask8 _mm256_mask_testn_epi32_mask(__mmask8, __m256i a, __m256i b);\r\nVPTESTNMD __mmask8 _mm_testn_epi32_mask(__m128i a, __m128i b);\r\nVPTESTNMD __mmask8 _mm_mask_testn_epi32_mask(__mmask8, __m128i a, __m128i b);\r\nVPTESTNMQ __mmask8 _mm512_testn_epi64_mask(__m512i a, __m512i b);\r\nVPTESTNMQ __mmask8 _mm512_mask_testn_epi64_mask(__mmask8, __m512i a, __m512i b);\r\nVPTESTNMQ __mmask8 _mm256_testn_epi64_mask(__m256i a, __m256i b);\r\nVPTESTNMQ __mmask8 _mm256_mask_testn_epi64_mask(__mmask8, __m256i a, __m256i b);\r\nVPTESTNMQ __mmask8 _mm_testn_epi64_mask(__m128i a, __m128i b);\r\nVPTESTNMQ __mmask8 _mm_mask_testn_epi64_mask(__mmask8, __m128i a, __m128i b);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nVPTESTNMD/VPTESTNMQ: See Exceptions Type E4.\r\nVPTESTNMB/VPTESTNMW: See Exceptions Type E4.nb.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VPTESTNMB"
},
{
"description": "-R:VPTESTNMB",
"mnem": "VPTESTNMD"
},
{
"description": "-R:VPTESTNMB",
"mnem": "VPTESTNMQ"
},
{
"description": "-R:VPTESTNMB",
"mnem": "VPTESTNMW"
},
{
"description": "VRANGEPD-Range Restriction Calculation For Packed Pairs of Float64 Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.128.66.0F3A.W1 50 /r ib FV V/V AVX512VL Calculate two RANGE operation output value from 2 pairs\r\n VRANGEPD xmm1 {k1}{z}, xmm2, AVX512DQ of double-precision floating-point values in xmm2 and\r\n xmm3/m128/m64bcst, imm8 xmm3/m128/m32bcst, store the results to xmm1 under\r\n the writemask k1. Imm8 specifies the comparison and sign\r\n of the range operation.\r\n EVEX.NDS.256.66.0F3A.W1 50 /r ib FV V/V AVX512VL Calculate four RANGE operation output value from 4pairs\r\n VRANGEPD ymm1 {k1}{z}, ymm2, AVX512DQ of double-precision floating-point values in ymm2 and\r\n ymm3/m256/m64bcst, imm8 ymm3/m256/m32bcst, store the results to ymm1 under\r\n the writemask k1. Imm8 specifies the comparison and sign\r\n of the range operation.\r\n EVEX.NDS.512.66.0F3A.W1 50 /r ib FV V/V AVX512DQ Calculate eight RANGE operation output value from 8\r\n VRANGEPD zmm1 {k1}{z}, zmm2, pairs of double-precision floating-point values in zmm2\r\n zmm3/m512/m64bcst{sae}, imm8 and zmm3/m512/m32bcst, store the results to zmm1\r\n under the writemask k1. Imm8 specifies the comparison\r\n and sign of the range operation.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) Imm8\r\n\r\nDescription\r\nThis instruction calculates 2/4/8 range operation outputs from two sets of packed input double-precision FP values\r\nin the first source operand (the second operand) and the second source operand (the third operand). The range\r\noutputs are written to the destination operand (the first operand) under the writemask k1.\r\nBits7:4 of imm8 byte must be zero. The range operation output is performed in two parts, each configured by a\r\ntwo-bit control field within imm8[3:0]:\r\n. Imm8[1:0] specifies the initial comparison operation to be one of max, min, max absolute value or min\r\n absolute value of the input value pair. Each comparison of two input values produces an intermediate result that\r\n combines with the sign selection control (Imm8[3:2]) to determine the final range operation output.\r\n. Imm8[3:2] specifies the sign of the range operation output to be one of the following: from the first input\r\n value, from the comparison result, set or clear.\r\nThe encodings of Imm8[1:0] and Imm8[3:2] are shown in Figure 5-27.\r\n\r\n\r\n\r\n 7 6 5 4 3 2 1 0\r\n\r\n imm8 Must Be Zero Sign Control (SC) Compare Operation Select\r\n\r\n\r\n\r\n Imm8[1:0] = 00b : Select Min value\r\n Imm8[3:2] = 00b : Select sign(SRC1) Imm8[1:0] = 01b : Select Max value\r\n Imm8[3:2] = 01b : Select sign(Compare_Result) Imm8[1:0] = 10b : Select Min-Abs value\r\n Imm8[3:2] = 10b : Set sign to 0 Imm8[1:0] = 11b : Select Max-Abs value\r\n Imm8[3:2] = 11b : Set sign to 1\r\n\r\n\r\n Figure 5-27. Imm8 Controls for VRANGEPD/SD/PS/SS\r\n\r\n\r\n\r\n\r\n\r\nWhen one or more of the input value is a NAN, the comparison operation may signal invalid exception (IE). Details\r\nwith one of more input value is NAN is listed in Table 5-12. If the comparison raises an IE, the sign select control\r\n(Imm8[3:2] has no effect to the range operation output, this is indicated also in Table 5-12.\r\nWhen both input values are zeros of opposite signs, the comparison operation of MIN/MAX in the range compare\r\noperation is slightly different from the conceptually similar FP MIN/MAX operation that are found in the instructions\r\nVMAXPD/VMINPD. The details of MIN/MAX/MIN_ABS/MAX_ABS operation for VRANGEPD/PS/SD/SS for magni-\r\ntude-0, opposite-signed input cases are listed in Table 5-13.\r\nAdditionally, non-zero, equal-magnitude with opposite-sign input values perform MIN_ABS or MAX_ABS compar-\r\nison operation with result listed in Table 5-14.\r\n\r\n Table 5-12. Signaling of Comparison Operation of One or More NaN Input Values and Effect of Imm8[3:2]\r\n Src1 Src2 Result IE Signaling Due to Comparison Imm8[3:2] Effect to Range Output\r\n sNaN1 sNaN2 Quiet(sNaN1) Yes Ignored\r\n sNaN1 qNaN2 Quiet(sNaN1) Yes Ignored\r\n sNaN1 Norm2 Quiet(sNaN1) Yes Ignored\r\n qNaN1 sNaN2 Quiet(sNaN2) Yes Ignored\r\n qNaN1 qNaN2 qNaN1 No Applicable\r\n qNaN1 Norm2 Norm2 No Applicable\r\n Norm1 sNaN2 Quiet(sNaN2) Yes Ignored\r\n Norm1 qNaN2 Norm1 No Applicable\r\n\r\n\r\n\r\n Table 5-13. Comparison Result for Opposite-Signed Zero Cases for MIN, MIN_ABS and MAX, MAX_ABS\r\n MIN and MIN_ABS MAX and MAX_ABS\r\n Src1 Src2 Result Src1 Src2 Result\r\n +0 -0 -0 +0 -0 +0\r\n -0 +0 -0 -0 +0 +0\r\n\r\n\r\n\r\n Table 5-14. Comparison Result of Equal-Magnitude Input Cases for MIN_ABS and MAX_ABS, (|a| = |b|, a>0, b<0)\r\n MIN_ABS (|a| = |b|, a>0, b<0) MAX_ABS (|a| = |b|, a>0, b<0)\r\n Src1 Src2 Result Src1 Src2 Result\r\n a b b a b a\r\n b a b b a a\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nRangeDP(SRC1[63:0], SRC2[63:0], CmpOpCtl[1:0], SignSelCtl[1:0])\r\n{\r\n // Check if SNAN and report IE, see also Table 5-12\r\n IF (SRC1 = SNAN) THEN RETURN (QNAN(SRC1), set IE);\r\n IF (SRC2 = SNAN) THEN RETURN (QNAN(SRC2), set IE);\r\n\r\n Src1.exp <- SRC1[62:52];\r\n Src1.fraction <- SRC1[51:0];\r\n IF ((Src1.exp = 0 ) and (Src1.fraction != 0)) THEN// Src1 is a denormal number\r\n IF DAZ THEN Src1.fraction <- 0;\r\n ELSE IF (SRC2 <> QNAN) Set DE; FI;\r\n FI;\r\n\r\n Src2.exp <- SRC2[62:52];\r\n Src2.fraction <- SRC2[51:0];\r\n IF ((Src2.exp = 0) and (Src2.fraction !=0 )) THEN// Src2 is a denormal number\r\n IF DAZ THEN Src2.fraction <- 0;\r\n ELSE IF (SRC1 <> QNAN) Set DE; FI;\r\n FI;\r\n\r\n IF (SRC2 = QNAN) THEN{TMP[63:0] <- SRC1[63:0]}\r\n ELSE IF(SRC1 = QNAN) THEN{TMP[63:0] <- SRC2[63:0]}\r\n ELSE IF (Both SRC1, SRC2 are magnitude-0 and opposite-signed) TMP[63:0] <- from Table 5-13\r\n ELSE IF (Both SRC1, SRC2 are magnitude-equal and opposite-signed and CmpOpCtl[1:0] > 01) TMP[63:0] <- from Table 5-14\r\n ELSE\r\n Case(CmpOpCtl[1:0])\r\n 00: TMP[63:0] <- (SRC1[63:0] <= SRC2[63:0]) ? SRC1[63:0] : SRC2[63:0];\r\n 01: TMP[63:0] <- (SRC1[63:0] <= SRC2[63:0]) ? SRC2[63:0] : SRC1[63:0];\r\n 10: TMP[63:0] <- (ABS(SRC1[63:0]) <= ABS(SRC2[63:0])) ? SRC1[63:0] : SRC2[63:0];\r\n 11: TMP[63:0] <- (ABS(SRC1[63:0]) <= ABS(SRC2[63:0])) ? SRC2[63:0] : SRC1[63:0];\r\n ESAC;\r\n FI;\r\n\r\n Case(SignSelCtl[1:0])\r\n 00: dest <- (SRC1[63] << 63) OR (TMP[62:0]);// Preserve Src1 sign bit\r\n 01: dest <- TMP[63:0];// Preserve sign of compare result\r\n 10: dest <- (0 << 63) OR (TMP[62:0]);// Zero out sign bit\r\n 11: dest <- (1 << 63) OR (TMP[62:0]);// Set the sign bit\r\n ESAC;\r\n RETURN dest[63:0];\r\n}\r\n\r\nCmpOpCtl[1:0]= imm8[1:0];\r\nSignSelCtl[1:0]=imm8[3:2];\r\n\r\n\r\n\r\n\r\n\r\nVRANGEPD (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b == 1) AND (SRC2 *is memory*)\r\n THEN DEST[i+63:i] <- RangeDP (SRC1[i+63:i], SRC2[63:0], CmpOpCtl[1:0], SignSelCtl[1:0]);\r\n ELSE DEST[i+63:i] <- RangeDP (SRC1[i+63:i], SRC2[i+63:i], DAZ, CmpOpCtl[1:0], SignSelCtl[1:0]);\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] = 0\r\n FI;\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nThe following example describes a common usage of this instruction for checking that the input operand is\r\nbounded between +-1023.\r\n\r\nVRANGEPD zmm_dst, zmm_src, zmm_1023, 02h;\r\n\r\nWhere:\r\n zmm_dst is the destination operand.\r\n zmm_src is the input operand to compare against +-1023 (this is SRC1).\r\n zmm_1023 is the reference operand, contains the value of 1023 (and this is SRC2).\r\n IMM=02(imm8[1:0]='10) selects the Min Absolute value operation with selection of SRC1.sign.\r\n\r\nIn case |zmm_src| < 1023 (i.e. SRC1 is smaller than 1023 in magnitude), then its value will be written into\r\nzmm_dst. Otherwise, the value stored in zmm_dst will get the value of 1023 (received on zmm_1023, which is\r\nSRC2).\r\nHowever, the sign control (imm8[3:2]='00) instructs to select the sign of SRC1 received from zmm_src. So, even\r\nin the case of |zmm_src| >= 1023, the selected sign of SRC1 is kept.\r\nThus, if zmm_src < -1023, the result of VRANGEPD will be the minimal value of -1023 while if zmm_src > +1023,\r\nthe result of VRANGE will be the maximal value of +1023.\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVRANGEPD __m512d _mm512_range_pd ( __m512d a, __m512d b, int imm);\r\nVRANGEPD __m512d _mm512_range_round_pd ( __m512d a, __m512d b, int imm, int sae);\r\nVRANGEPD __m512d _mm512_mask_range_pd (__m512 ds, __mmask8 k, __m512d a, __m512d b, int imm);\r\nVRANGEPD __m512d _mm512_mask_range_round_pd (__m512d s, __mmask8 k, __m512d a, __m512d b, int imm, int sae);\r\nVRANGEPD __m512d _mm512_maskz_range_pd ( __mmask8 k, __m512d a, __m512d b, int imm);\r\nVRANGEPD __m512d _mm512_maskz_range_round_pd ( __mmask8 k, __m512d a, __m512d b, int imm, int sae);\r\nVRANGEPD __m256d _mm256_range_pd ( __m256d a, __m256d b, int imm);\r\nVRANGEPD __m256d _mm256_mask_range_pd (__m256d s, __mmask8 k, __m256d a, __m256d b, int imm);\r\nVRANGEPD __m256d _mm256_maskz_range_pd ( __mmask8 k, __m256d a, __m256d b, int imm);\r\nVRANGEPD __m128d _mm_range_pd ( __m128 a, __m128d b, int imm);\r\nVRANGEPD __m128d _mm_mask_range_pd (__m128 s, __mmask8 k, __m128d a, __m128d b, int imm);\r\nVRANGEPD __m128d _mm_maskz_range_pd ( __mmask8 k, __m128d a, __m128d b, int imm);\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nInvalid, Denormal\r\n\r\nOther Exceptions\r\nSee Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VRANGEPD"
},
{
"description": " VRANGEPS-Range Restriction Calculation For Packed Pairs of Float32 Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.128.66.0F3A.W0 50 /r ib FV V/V AVX512VL Calculate four RANGE operation output value from 4 pairs\r\n VRANGEPS xmm1 {k1}{z}, xmm2, AVX512DQ of single-precision floating-point values in xmm2 and\r\n xmm3/m128/m32bcst, imm8 xmm3/m128/m32bcst, store the results to xmm1 under\r\n the writemask k1. Imm8 specifies the comparison and sign\r\n of the range operation.\r\n EVEX.NDS.256.66.0F3A.W0 50 /r ib FV V/V AVX512VL Calculate eight RANGE operation output value from 8 pairs\r\n VRANGEPS ymm1 {k1}{z}, ymm2, AVX512DQ of single-precision floating-point values in ymm2 and\r\n ymm3/m256/m32bcst, imm8 ymm3/m256/m32bcst, store the results to ymm1 under\r\n the writemask k1. Imm8 specifies the comparison and sign\r\n of the range operation.\r\n EVEX.NDS.512.66.0F3A.W0 50 /r ib FV V/V AVX512DQ Calculate 16 RANGE operation output value from 16 pairs\r\n VRANGEPS zmm1 {k1}{z}, zmm2, of single-precision floating-point values in zmm2 and\r\n zmm3/m512/m32bcst{sae}, imm8 zmm3/m512/m32bcst, store the results to zmm1 under\r\n the writemask k1. Imm8 specifies the comparison and sign\r\n of the range operation.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) Imm8\r\n\r\nDescription\r\nThis instruction calculates 4/8/16 range operation outputs from two sets of packed input single-precision FP values\r\nin the first source operand (the second operand) and the second source operand (the third operand). The range\r\noutputs are written to the destination operand (the first operand) under the writemask k1.\r\nBits7:4 of imm8 byte must be zero. The range operation output is performed in two parts, each configured by a\r\ntwo-bit control field within imm8[3:0]:\r\n. Imm8[1:0] specifies the initial comparison operation to be one of max, min, max absolute value or min\r\n absolute value of the input value pair. Each comparison of two input values produces an intermediate result\r\n that combines with the sign selection control (Imm8[3:2]) to determine the final range operation output.\r\n. Imm8[3:2] specifies the sign of the range operation output to be one of the following: from the first input\r\n value, from the comparison result, set or clear.\r\nThe encodings of Imm8[1:0] and Imm8[3:2] are shown in Figure 5-27.\r\nWhen one or more of the input value is a NAN, the comparison operation may signal invalid exception (IE). Details\r\nwith one of more input value is NAN is listed in Table 5-12. If the comparison raises an IE, the sign select control\r\n(Imm8[3:2]) has no effect to the range operation output, this is indicated also in Table 5-12.\r\nWhen both input values are zeros of opposite signs, the comparison operation of MIN/MAX in the range compare\r\noperation is slightly different from the conceptually similar FP MIN/MAX operation that are found in the instructions\r\nVMAXPD/VMINPD. The details of MIN/MAX/MIN_ABS/MAX_ABS operation for VRANGEPD/PS/SD/SS for magni-\r\ntude-0, opposite-signed input cases are listed in Table 5-13.\r\nAdditionally, non-zero, equal-magnitude with opposite-sign input values perform MIN_ABS or MAX_ABS compar-\r\nison operation with result listed in Table 5-14.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nRangeSP(SRC1[31:0], SRC2[31:0], CmpOpCtl[1:0], SignSelCtl[1:0])\r\n{\r\n // Check if SNAN and report IE, see also Table 5-12\r\n IF (SRC1=SNAN) THEN RETURN (QNAN(SRC1), set IE);\r\n IF (SRC2=SNAN) THEN RETURN (QNAN(SRC2), set IE);\r\n\r\n Src1.exp <- SRC1[30:23];\r\n Src1.fraction <- SRC1[22:0];\r\n IF ((Src1.exp = 0 ) and (Src1.fraction != 0 )) THEN// Src1 is a denormal number\r\n IF DAZ THEN Src1.fraction <- 0;\r\n ELSE IF (SRC2 <> QNAN) Set DE; FI;\r\n FI;\r\n Src2.exp <- SRC2[30:23];\r\n Src2.fraction <- SRC2[22:0];\r\n IF ((Src2.exp = 0 ) and (Src2.fraction != 0 )) THEN// Src2 is a denormal number\r\n IF DAZ THEN Src2.fraction <- 0;\r\n ELSE IF (SRC1 <> QNAN) Set DE; FI;\r\n FI;\r\n\r\n IF (SRC2 = QNAN) THEN{TMP[31:0] <- SRC1[31:0]}\r\n ELSE IF(SRC1 = QNAN) THEN{TMP[31:0] <- SRC2[31:0]}\r\n ELSE IF (Both SRC1, SRC2 are magnitude-0 and opposite-signed) TMP[31:0] <- from Table 5-13\r\n ELSE IF (Both SRC1, SRC2 are magnitude-equal and opposite-signed and CmpOpCtl[1:0] > 01) TMP[31:0] <- from Table 5-14\r\n ELSE\r\n Case(CmpOpCtl[1:0])\r\n 00: TMP[31:0] <- (SRC1[31:0] <= SRC2[31:0]) ? SRC1[31:0] : SRC2[31:0];\r\n 01: TMP[31:0] <- (SRC1[31:0] <= SRC2[31:0]) ? SRC2[31:0] : SRC1[31:0];\r\n 10: TMP[31:0] <- (ABS(SRC1[31:0]) <= ABS(SRC2[31:0])) ? SRC1[31:0] : SRC2[31:0];\r\n 11: TMP[31:0] <- (ABS(SRC1[31:0]) <= ABS(SRC2[31:0])) ? SRC2[31:0] : SRC1[31:0];\r\n ESAC;\r\n FI;\r\n Case(SignSelCtl[1:0])\r\n 00: dest <- (SRC1[31] << 31) OR (TMP[30:0]);// Preserve Src1 sign bit\r\n 01: dest <- TMP[31:0];// Preserve sign of compare result\r\n 10: dest <- (0 << 31) OR (TMP[30:0]);// Zero out sign bit\r\n 11: dest <- (1 << 31) OR (TMP[30:0]);// Set the sign bit\r\n ESAC;\r\n RETURN dest[31:0];\r\n}\r\n\r\nCmpOpCtl[1:0]= imm8[1:0];\r\nSignSelCtl[1:0]=imm8[3:2];\r\n\r\n\r\n\r\n\r\n\r\nVRANGEPS\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b == 1) AND (SRC2 *is memory*)\r\n THEN DEST[i+31:i] <- RangeSP (SRC1[i+31:i], SRC2[31:0], CmpOpCtl[1:0], SignSelCtl[1:0]);\r\n ELSE DEST[i+31:i] <- RangeSP (SRC1[i+31:i], SRC2[i+31:i], DAZ, CmpOpCtl[1:0], SignSelCtl[1:0]);\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] = 0\r\n FI;\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nThe following example describes a common usage of this instruction for checking that the input operand is\r\nbounded between +-150.\r\n\r\nVRANGEPS zmm_dst, zmm_src, zmm_150, 02h;\r\n\r\nWhere:\r\nzmm_dst is the destination operand.\r\nzmm_src is the input operand to compare against +-150.\r\nzmm_150 is the reference operand, contains the value of 150.\r\nIMM=02(imm8[1:0]='10) selects the Min Absolute value operation with selection of src1.sign.\r\n\r\nIn case |zmm_src| < 150, then its value will be written into zmm_dst. Otherwise, the value stored in zmm_dst\r\nwill get the value of 150 (received on zmm_150).\r\nHowever, the sign control (imm8[3:2]='00) instructs to select the sign of SRC1 received from zmm_src. So, even\r\nin the case of |zmm_src| >= 150, the selected sign of SRC1 is kept.\r\nThus, if zmm_src < -150, the result of VRANGEPS will be the minimal value of -150 while if zmm_src > +150,\r\nthe result of VRANGE will be the maximal value of +150.\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVRANGEPS __m512 _mm512_range_ps ( __m512 a, __m512 b, int imm);\r\nVRANGEPS __m512 _mm512_range_round_ps ( __m512 a, __m512 b, int imm, int sae);\r\nVRANGEPS __m512 _mm512_mask_range_ps (__m512 s, __mmask16 k, __m512 a, __m512 b, int imm);\r\nVRANGEPS __m512 _mm512_mask_range_round_ps (__m512 s, __mmask16 k, __m512 a, __m512 b, int imm, int sae);\r\nVRANGEPS __m512 _mm512_maskz_range_ps ( __mmask16 k, __m512 a, __m512 b, int imm);\r\nVRANGEPS __m512 _mm512_maskz_range_round_ps ( __mmask16 k, __m512 a, __m512 b, int imm, int sae);\r\nVRANGEPS __m256 _mm256_range_ps ( __m256 a, __m256 b, int imm);\r\nVRANGEPS __m256 _mm256_mask_range_ps (__m256 s, __mmask8 k, __m256 a, __m256 b, int imm);\r\nVRANGEPS __m256 _mm256_maskz_range_ps ( __mmask8 k, __m256 a, __m256 b, int imm);\r\nVRANGEPS __m128 _mm_range_ps ( __m128 a, __m128 b, int imm);\r\nVRANGEPS __m128 _mm_mask_range_ps (__m128 s, __mmask8 k, __m128 a, __m128 b, int imm);\r\nVRANGEPS __m128 _mm_maskz_range_ps ( __mmask8 k, __m128 a, __m128 b, int imm);\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nInvalid, Denormal\r\n\r\nOther Exceptions\r\nSee Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VRANGEPS"
},
{
"description": "VRANGESD-Range Restriction Calculation From a pair of Scalar Float64 Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.LIG.66.0F3A.W1 51 /r T1S V/V AVX512DQ Calculate a RANGE operation output value from 2 double-\r\n VRANGESD xmm1 {k1}{z}, precision floating-point values in xmm2 and xmm3/m64,\r\n xmm2, xmm3/m64{sae}, imm8 store the output to xmm1 under writemask. Imm8 specifies\r\n the comparison and sign of the range operation.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) Imm8\r\n\r\nDescription\r\nThis instruction calculates a range operation output from two input double-precision FP values in the low qword\r\nelement of the first source operand (the second operand) and second source operand (the third operand). The\r\nrange output is written to the low qword element of the destination operand (the first operand) under the\r\nwritemask k1.\r\nBits7:4 of imm8 byte must be zero. The range operation output is performed in two parts, each configured by a\r\ntwo-bit control field within imm8[3:0]:\r\n. Imm8[1:0] specifies the initial comparison operation to be one of max, min, max absolute value or min\r\n absolute value of the input value pair. Each comparison of two input values produces an intermediate result\r\n that combines with the sign selection control (Imm8[3:2]) to determine the final range operation output.\r\n. Imm8[3:2] specifies the sign of the range operation output to be one of the following: from the first input\r\n value, from the comparison result, set or clear.\r\nThe encodings of Imm8[1:0] and Imm8[3:2] are shown in Figure 5-27.\r\nBits 128:63 of the destination operand are copied from the respective element of the first source operand.\r\nWhen one or more of the input value is a NAN, the comparison operation may signal invalid exception (IE). Details\r\nwith one of more input value is NAN is listed in Table 5-12. If the comparison raises an IE, the sign select control\r\n(Imm8[3:2] has no effect to the range operation output, this is indicated also in Table 5-12.\r\nWhen both input values are zeros of opposite signs, the comparison operation of MIN/MAX in the range compare\r\noperation is slightly different from the conceptually similar FP MIN/MAX operation that are found in the instructions\r\nVMAXPD/VMINPD. The details of MIN/MAX/MIN_ABS/MAX_ABS operation for VRANGEPD/PS/SD/SS for magni-\r\ntude-0, opposite-signed input cases are listed in Table 5-13.\r\nAdditionally, non-zero, equal-magnitude with opposite-sign input values perform MIN_ABS or MAX_ABS compar-\r\nison operation with result listed in Table 5-14.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nRangeDP(SRC1[63:0], SRC2[63:0], CmpOpCtl[1:0], SignSelCtl[1:0])\r\n{\r\n // Check if SNAN and report IE, see also Table 5-12\r\n IF (SRC1 = SNAN) THEN RETURN (QNAN(SRC1), set IE);\r\n IF (SRC2 = SNAN) THEN RETURN (QNAN(SRC2), set IE);\r\n\r\n Src1.exp <- SRC1[62:52];\r\n Src1.fraction <- SRC1[51:0];\r\n IF ((Src1.exp = 0 ) and (Src1.fraction != 0)) THEN// Src1 is a denormal number\r\n IF DAZ THEN Src1.fraction <- 0;\r\n ELSE IF (SRC2 <> QNAN) Set DE; FI;\r\n FI;\r\n\r\n Src2.exp <- SRC2[62:52];\r\n Src2.fraction <- SRC2[51:0];\r\n IF ((Src2.exp = 0) and (Src2.fraction !=0 )) THEN// Src2 is a denormal number\r\n IF DAZ THEN Src2.fraction <- 0;\r\n ELSE IF (SRC1 <> QNAN) Set DE; FI;\r\n FI;\r\n\r\n IF (SRC2 = QNAN) THEN{TMP[63:0] <- SRC1[63:0]}\r\n ELSE IF(SRC1 = QNAN) THEN{TMP[63:0] <- SRC2[63:0]}\r\n ELSE IF (Both SRC1, SRC2 are magnitude-0 and opposite-signed) TMP[63:0] <- from Table 5-13\r\n ELSE IF (Both SRC1, SRC2 are magnitude-equal and opposite-signed and CmpOpCtl[1:0] > 01) TMP[63:0] <- from Table 5-14\r\n ELSE\r\n Case(CmpOpCtl[1:0])\r\n 00: TMP[63:0] <- (SRC1[63:0] <= SRC2[63:0]) ? SRC1[63:0] : SRC2[63:0];\r\n 01: TMP[63:0] <- (SRC1[63:0] <= SRC2[63:0]) ? SRC2[63:0] : SRC1[63:0];\r\n 10: TMP[63:0] <- (ABS(SRC1[63:0]) <= ABS(SRC2[63:0])) ? SRC1[63:0] : SRC2[63:0];\r\n 11: TMP[63:0] <- (ABS(SRC1[63:0]) <= ABS(SRC2[63:0])) ? SRC2[63:0] : SRC1[63:0];\r\n ESAC;\r\n FI;\r\n\r\n Case(SignSelCtl[1:0])\r\n 00: dest <- (SRC1[63] << 63) OR (TMP[62:0]);// Preserve Src1 sign bit\r\n 01: dest <- TMP[63:0];// Preserve sign of compare result\r\n 10: dest <- (0 << 63) OR (TMP[62:0]);// Zero out sign bit\r\n 11: dest <- (1 << 63) OR (TMP[62:0]);// Set the sign bit\r\n ESAC;\r\n RETURN dest[63:0];\r\n}\r\n\r\nCmpOpCtl[1:0]= imm8[1:0];\r\nSignSelCtl[1:0]=imm8[3:2];\r\n\r\n\r\n\r\n\r\n\r\nVRANGESD\r\nIF k1[0] OR *no writemask*\r\n THEN DEST[63:0] <- RangeDP (SRC1[63:0], SRC2[63:0], CmpOpCtl[1:0], SignSelCtl[1:0]);\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[63:0] = 0\r\n FI;\r\nFI;\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nThe following example describes a common usage of this instruction for checking that the input operand is\r\nbounded between +-1023.\r\n\r\nVRANGESD xmm_dst, xmm_src, xmm_1023, 02h;\r\n\r\nWhere:\r\nxmm_dst is the destination operand.\r\nxmm_src is the input operand to compare against +-1023.\r\nxmm_1023 is the reference operand, contains the value of 1023.\r\nIMM=02(imm8[1:0]='10) selects the Min Absolute value operation with selection of src1.sign.\r\n\r\nIn case |xmm_src| < 1023, then its value will be written into xmm_dst. Otherwise, the value stored in xmm_dst\r\nwill get the value of 1023 (received on xmm_1023).\r\nHowever, the sign control (imm8[3:2]='00) instructs to select the sign of SRC1 received from xmm_src. So, even\r\nin the case of |xmm_src| >= 1023, the selected sign of SRC1 is kept.\r\nThus, if xmm_src < -1023, the result of VRANGEPD will be the minimal value of -1023while if xmm_src > +1023,\r\nthe result of VRANGE will be the maximal value of +1023.\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVRANGESD __m128d _mm_range_sd ( __m128d a, __m128d b, int imm);\r\nVRANGESD __m128d _mm_range_round_sd ( __m128d a, __m128d b, int imm, int sae);\r\nVRANGESD __m128d _mm_mask_range_sd (__m128d s, __mmask8 k, __m128d a, __m128d b, int imm);\r\nVRANGESD __m128d _mm_mask_range_round_sd (__m128d s, __mmask8 k, __m128d a, __m128d b, int imm, int sae);\r\nVRANGESD __m128d _mm_maskz_range_sd ( __mmask8 k, __m128d a, __m128d b, int imm);\r\nVRANGESD __m128d _mm_maskz_range_round_sd ( __mmask8 k, __m128d a, __m128d b, int imm, int sae);\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nInvalid, Denormal\r\n\r\nOther Exceptions\r\nSee Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VRANGESD"
},
{
"description": "VRANGESS-Range Restriction Calculation From a Pair of Scalar Float32 Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.LIG.66.0F3A.W0 51 /r T1S V/V AVX512DQ Calculate a RANGE operation output value from 2 single-\r\n VRANGESS xmm1 {k1}{z}, precision floating-point values in xmm2 and xmm3/m32,\r\n xmm2, xmm3/m32{sae}, imm8 store the output to xmm1 under writemask. Imm8 specifies\r\n the comparison and sign of the range operation.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nThis instruction calculates a range operation output from two input single-precision FP values in the low dword\r\nelement of the first source operand (the second operand) and second source operand (the third operand). The\r\nrange output is written to the low dword element of the destination operand (the first operand) under the\r\nwritemask k1.\r\nBits7:4 of imm8 byte must be zero. The range operation output is performed in two parts, each configured by a\r\ntwo-bit control field within imm8[3:0]:\r\n. Imm8[1:0] specifies the initial comparison operation to be one of max, min, max absolute value or min\r\n absolute value of the input value pair. Each comparison of two input values produces an intermediate result that\r\n combines with the sign selection control (Imm8[3:2]) to determine the final range operation output.\r\n. Imm8[3:2] specifies the sign of the range operation output to be one of the following: from the first input\r\n value, from the comparison result, set or clear.\r\nThe encodings of Imm8[1:0] and Imm8[3:2] are shown in Figure 5-27.\r\nBits 128:31 of the destination operand are copied from the respective elements of the first source operand.\r\nWhen one or more of the input value is a NAN, the comparison operation may signal invalid exception (IE). Details\r\nwith one of more input value is NAN is listed in Table 5-12. If the comparison raises an IE, the sign select control\r\n(Imm8[3:2]) has no effect to the range operation output, this is indicated also in Table 5-12.\r\nWhen both input values are zeros of opposite signs, the comparison operation of MIN/MAX in the range compare\r\noperation is slightly different from the conceptually similar FP MIN/MAX operation that are found in the instructions\r\nVMAXPD/VMINPD. The details of MIN/MAX/MIN_ABS/MAX_ABS operation for VRANGEPD/PS/SD/SS for magni-\r\ntude-0, opposite-signed input cases are listed in Table 5-13.\r\nAdditionally, non-zero, equal-magnitude with opposite-sign input values perform MIN_ABS or MAX_ABS compar-\r\nison operation with result listed in Table 5-14.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nRangeSP(SRC1[31:0], SRC2[31:0], CmpOpCtl[1:0], SignSelCtl[1:0])\r\n{\r\n // Check if SNAN and report IE, see also Table 5-12\r\n IF (SRC1=SNAN) THEN RETURN (QNAN(SRC1), set IE);\r\n IF (SRC2=SNAN) THEN RETURN (QNAN(SRC2), set IE);\r\n\r\n Src1.exp <- SRC1[30:23];\r\n Src1.fraction <- SRC1[22:0];\r\n IF ((Src1.exp = 0 ) and (Src1.fraction != 0 )) THEN// Src1 is a denormal number\r\n IF DAZ THEN Src1.fraction <- 0;\r\n ELSE IF (SRC2 <> QNAN) Set DE; FI;\r\n FI;\r\n Src2.exp <- SRC2[30:23];\r\n Src2.fraction <- SRC2[22:0];\r\n IF ((Src2.exp = 0 ) and (Src2.fraction != 0 )) THEN// Src2 is a denormal number\r\n IF DAZ THEN Src2.fraction <- 0;\r\n ELSE IF (SRC1 <> QNAN) Set DE; FI;\r\n FI;\r\n\r\n IF (SRC2 = QNAN) THEN{TMP[31:0] <- SRC1[31:0]}\r\n ELSE IF(SRC1 = QNAN) THEN{TMP[31:0] <- SRC2[31:0]}\r\n ELSE IF (Both SRC1, SRC2 are magnitude-0 and opposite-signed) TMP[31:0] <- from Table 5-13\r\n ELSE IF (Both SRC1, SRC2 are magnitude-equal and opposite-signed and CmpOpCtl[1:0] > 01) TMP[31:0] <- from Table 5-14\r\n ELSE\r\n Case(CmpOpCtl[1:0])\r\n 00: TMP[31:0] <- (SRC1[31:0] <= SRC2[31:0]) ? SRC1[31:0] : SRC2[31:0];\r\n 01: TMP[31:0] <- (SRC1[31:0] <= SRC2[31:0]) ? SRC2[31:0] : SRC1[31:0];\r\n 10: TMP[31:0] <- (ABS(SRC1[31:0]) <= ABS(SRC2[31:0])) ? SRC1[31:0] : SRC2[31:0];\r\n 11: TMP[31:0] <- (ABS(SRC1[31:0]) <= ABS(SRC2[31:0])) ? SRC2[31:0] : SRC1[31:0];\r\n ESAC;\r\n FI;\r\n Case(SignSelCtl[1:0])\r\n 00: dest <- (SRC1[31] << 31) OR (TMP[30:0]);// Preserve Src1 sign bit\r\n 01: dest <- TMP[31:0];// Preserve sign of compare result\r\n 10: dest <- (0 << 31) OR (TMP[30:0]);// Zero out sign bit\r\n 11: dest <- (1 << 31) OR (TMP[30:0]);// Set the sign bit\r\n ESAC;\r\n RETURN dest[31:0];\r\n}\r\n\r\nCmpOpCtl[1:0]= imm8[1:0];\r\nSignSelCtl[1:0]=imm8[3:2];\r\n\r\n\r\n\r\n\r\n\r\nVRANGESS\r\nIF k1[0] OR *no writemask*\r\n THEN DEST[31:0] <- RangeSP (SRC1[31:0], SRC2[31:0], CmpOpCtl[1:0], SignSelCtl[1:0]);\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[31:0] = 0\r\n FI;\r\nFI;\r\nDEST[127:32] <- SRC1[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nThe following example describes a common usage of this instruction for checking that the input operand is bound-\r\ned between +-150.\r\n\r\nVRANGESS zmm_dst, zmm_src, zmm_150, 02h;\r\n\r\nWhere:\r\nxmm_dst is the destination operand.\r\nxmm_src is the input operand to compare against +-150.\r\nxmm_150 is the reference operand, contains the value of 150.\r\nIMM=02(imm8[1:0]='10) selects the Min Absolute value operation with selection of src1.sign.\r\n\r\nIn case |xmm_src| < 150, then its value will be written into zmm_dst. Otherwise, the value stored in xmm_dst\r\nwill get the value of 150 (received on zmm_150).\r\nHowever, the sign control (imm8[3:2]='00) instructs to select the sign of SRC1 received from xmm_src. So, even\r\nin the case of |xmm_src| >= 150, the selected sign of SRC1 is kept.\r\nThus, if xmm_src < -150, the result of VRANGESS will be the minimal value of -150 while if xmm_src > +150,\r\nthe result of VRANGE will be the maximal value of +150.\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVRANGESS __m128 _mm_range_ss ( __m128 a, __m128 b, int imm);\r\nVRANGESS __m128 _mm_range_round_ss ( __m128 a, __m128 b, int imm, int sae);\r\nVRANGESS __m128 _mm_mask_range_ss (__m128 s, __mmask8 k, __m128 a, __m128 b, int imm);\r\nVRANGESS __m128 _mm_mask_range_round_ss (__m128 s, __mmask8 k, __m128 a, __m128 b, int imm, int sae);\r\nVRANGESS __m128 _mm_maskz_range_ss ( __mmask8 k, __m128 a, __m128 b, int imm);\r\nVRANGESS __m128 _mm_maskz_range_round_ss ( __mmask8 k, __m128 a, __m128 b, int imm, int sae);\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nInvalid, Denormal\r\n\r\nOther Exceptions\r\nSee Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VRANGESS"
},
{
"description": "VRCP14PD-Compute Approximate Reciprocals of Packed Float64 Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F38.W1 4C /r FV V/V AVX512VL Computes the approximate reciprocals of the packed double-\r\n VRCP14PD xmm1 {k1}{z}, AVX512F precision floating-point values in xmm2/m128/m64bcst and\r\n xmm2/m128/m64bcst stores the results in xmm1. Under writemask.\r\n EVEX.256.66.0F38.W1 4C /r FV V/V AVX512VL Computes the approximate reciprocals of the packed double-\r\n VRCP14PD ymm1 {k1}{z}, AVX512F precision floating-point values in ymm2/m256/m64bcst and\r\n ymm2/m256/m64bcst stores the results in ymm1. Under writemask.\r\n EVEX.512.66.0F38.W1 4C /r FV V/V AVX512F Computes the approximate reciprocals of the packed double-\r\n VRCP14PD zmm1 {k1}{z}, precision floating-point values in zmm2/m512/m64bcst and\r\n zmm2/m512/m64bcst stores the results in zmm1. Under writemask.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nThis instruction performs a SIMD computation of the approximate reciprocals of eight/four/two packed double-\r\nprecision floating-point values in the source operand (the second operand) and stores the packed double-precision\r\nfloating-point results in the destination operand. The maximum relative error for this approximation is less than 2-\r\n14\r\n .\r\nThe source operand can be a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 64-\r\nbit memory location. The destination operand is a ZMM register conditionally updated according to the writemask.\r\nThe VRCP14PD instruction is not affected by the rounding control bits in the MXCSR register. When a source value\r\nis a 0.0, an inf with the sign of the source value is returned. A denormal source value will be treated as zero only in\r\ncase of DAZ bit set in MXCSR. Otherwise it is treated correctly (i.e. not as a 0.0). Underflow results are flushed to\r\nzero only in case of FTZ bit set in MXCSR. Otherwise it will be treated correctly (i.e. correct underflow result is\r\nwritten) with the sign of the operand. When a source value is a SNaN or QNaN, the SNaN is converted to a QNaN\r\nor the source QNaN is returned.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\nMXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.\r\n\r\n Table 5-15. VRCP14PD/VRCP14SD Special Cases\r\n Input value Result value Comments\r\n 0 <= X <= 2-1024 INF Very small denormal\r\n -1024 <=\r\n -2 X <= -0 -INF Very small denormal\r\n 1022\r\n X>2 Underflow Up to 18 bits of fractions are returned*\r\n X < -21022 -Underflow Up to 18 bits of fractions are returned*\r\n -n 2n\r\n X=2\r\n X = -2-n -2n\r\n\r\n* in this case the mantissa is shifted right by one or two bits\r\n\r\n\r\nA numerically exact implementation of VRCP14xx can be found at https://software.intel.com/en-us/articles/refer-\r\nence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVRCP14PD ((EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC *is memory*)\r\n THEN DEST[i+63:i] <- APPROXIMATE(1.0/SRC[63:0]);\r\n ELSE DEST[i+63:i] <- APPROXIMATE(1.0/SRC[i+63:i]);\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI;\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVRCP14PD __m512d _mm512_rcp14_pd( __m512d a);\r\nVRCP14PD __m512d _mm512_mask_rcp14_pd(__m512d s, __mmask8 k, __m512d a);\r\nVRCP14PD __m512d _mm512_maskz_rcp14_pd( __mmask8 k, __m512d a);\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VRCP14PD"
},
{
"description": "VRCP14PS-Compute Approximate Reciprocals of Packed Float32 Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F38.W0 4C /r FV V/V AVX512VL Computes the approximate reciprocals of the packed single-\r\n VRCP14PS xmm1 {k1}{z}, AVX512F precision floating-point values in xmm2/m128/m32bcst and\r\n xmm2/m128/m32bcst stores the results in xmm1. Under writemask.\r\n EVEX.256.66.0F38.W0 4C /r FV V/V AVX512VL Computes the approximate reciprocals of the packed single-\r\n VRCP14PS ymm1 {k1}{z}, AVX512F precision floating-point values in ymm2/m256/m32bcst and\r\n ymm2/m256/m32bcst stores the results in ymm1. Under writemask.\r\n EVEX.512.66.0F38.W0 4C /r FV V/V AVX512F Computes the approximate reciprocals of the packed single-\r\n VRCP14PS zmm1 {k1}{z}, precision floating-point values in zmm2/m512/m32bcst and\r\n zmm2/m512/m32bcst stores the results in zmm1. Under writemask.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nThis instruction performs a SIMD computation of the approximate reciprocals of the packed single-precision\r\nfloating-point values in the source operand (the second operand) and stores the packed single-precision floating-\r\npoint results in the destination operand (the first operand). The maximum relative error for this approximation is\r\nless than 2-14.\r\nThe source operand can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32-\r\nbit memory location. The destination operand is a ZMM register conditionally updated according to the writemask.\r\nThe VRCP14PS instruction is not affected by the rounding control bits in the MXCSR register. When a source value\r\nis a 0.0, an inf with the sign of the source value is returned. A denormal source value will be treated as zero only in\r\ncase of DAZ bit set in MXCSR. Otherwise it is treated correctly (i.e. not as a 0.0). Underflow results are flushed to\r\nzero only in case of FTZ bit set in MXCSR. Otherwise it will be treated correctly (i.e. correct underflow result is\r\nwritten) with the sign of the operand. When a source value is a SNaN or QNaN, the SNaN is converted to a QNaN\r\nor the source QNaN is returned.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\nMXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.\r\n\r\n Table 5-16. VRCP14PS/VRCP14SS Special Cases\r\n Input value Result value Comments\r\n 0 <= X <= 2-128 INF Very small denormal\r\n -128 <=\r\n -2 X <= -0 -INF Very small denormal\r\n 126\r\n X>2 Underflow Up to 18 bits of fractions are returned*\r\n X < -2126 -Underflow Up to 18 bits of fractions are returned*\r\n -n 2n\r\n X=2\r\n X = -2-n -2n\r\n\r\n* in this case the mantissa is shifted right by one or two bits\r\n\r\n\r\nA numerically exact implementation of VRCP14xx can be found at https://software.intel.com/en-us/articles/refer-\r\nence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVRCP14PS (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC *is memory*)\r\n THEN DEST[i+31:i] <- APPROXIMATE(1.0/SRC[31:0]);\r\n ELSE DEST[i+31:i] <- APPROXIMATE(1.0/SRC[i+31:i]);\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI;\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVRCP14PS __m512 _mm512_rcp14_ps( __m512 a);\r\nVRCP14PS __m512 _mm512_mask_rcp14_ps(__m512 s, __mmask16 k, __m512 a);\r\nVRCP14PS __m512 _mm512_maskz_rcp14_ps( __mmask16 k, __m512 a);\r\nVRCP14PS __m256 _mm256_rcp14_ps( __m256 a);\r\nVRCP14PS __m256 _mm512_mask_rcp14_ps(__m256 s, __mmask8 k, __m256 a);\r\nVRCP14PS __m256 _mm512_maskz_rcp14_ps( __mmask8 k, __m256 a);\r\nVRCP14PS __m128 _mm_rcp14_ps( __m128 a);\r\nVRCP14PS __m128 _mm_mask_rcp14_ps(__m128 s, __mmask8 k, __m128 a);\r\nVRCP14PS __m128 _mm_maskz_rcp14_ps( __mmask8 k, __m128 a);\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VRCP14PS"
},
{
"description": "VRCP14SD-Compute Approximate Reciprocal of Scalar Float64 Value\r\n Opcode/ Op 64/32 CPUID Description\r\n Instruction / En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.LIG.66.0F38.W1 4D /r T1S V/V AVX512F Computes the approximate reciprocal of the scalar double-\r\n VRCP14SD xmm1 {k1}{z}, xmm2, precision floating-point value in xmm3/m64 and stores the\r\n xmm3/m64 result in xmm1 using writemask k1. Also, upper double-precision\r\n floating-point value (bits[127:64]) from xmm2 is copied to\r\n xmm1[127:64].\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nThis instruction performs a SIMD computation of the approximate reciprocal of the low double-precision floating-\r\npoint value in the second source operand (the third operand) stores the result in the low quadword element of the\r\ndestination operand (the first operand) according to the writemask k1. Bits (127:64) of the XMM register destina-\r\ntion are copied from corresponding bits in the first source operand (the second operand). The maximum relative\r\nerror for this approximation is less than 2-14. The source operand can be an XMM register or a 64-bit memory loca-\r\ntion. The destination operand is an XMM register.\r\nThe VRCP14SD instruction is not affected by the rounding control bits in the MXCSR register. When a source value\r\nis a 0.0, an inf with the sign of the source value is returned. A denormal source value will be treated as zero only in\r\ncase of DAZ bit set in MXCSR. Otherwise it is treated correctly (i.e. not as a 0.0). Underflow results are flushed to\r\nzero only in case of FTZ bit set in MXCSR. Otherwise it will be treated correctly (i.e. correct underflow result is\r\nwritten) with the sign of the operand. When a source value is a SNaN or QNaN, the SNaN is converted to a QNaN\r\nor the source QNaN is returned. See Table 5-15 for special-case input values.\r\nMXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.\r\nA numerically exact implementation of VRCP14xx can be found at https://software.intel.com/en-us/articles/refer-\r\nence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.\r\n\r\nOperation\r\nVRCP14SD (EVEX version)\r\nIF k1[0] OR *no writemask*\r\n THEN DEST[63:0] <- APPROXIMATE(1.0/SRC2[63:0]);\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[63:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVRCP14SD __m128d _mm_rcp14_sd( __m128d a, __m128d b);\r\nVRCP14SD __m128d _mm_mask_rcp14_sd(__m128d s, __mmask8 k, __m128d a, __m128d b);\r\nVRCP14SD __m128d _mm_maskz_rcp14_sd( __mmask8 k, __m128d a, __m128d b);\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type E5.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VRCP14SD"
},
{
"description": "VRCP14SS-Compute Approximate Reciprocal of Scalar Float32 Value\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.LIG.66.0F38.W0 4D /r T1S V/V AVX512F Computes the approximate reciprocal of the scalar single-\r\n VRCP14SS xmm1 {k1}{z}, xmm2, precision floating-point value in xmm3/m32 and stores the\r\n xmm3/m32 results in xmm1 using writemask k1. Also, upper double-\r\n precision floating-point value (bits[127:32]) from xmm2 is\r\n copied to xmm1[127:32].\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nThis instruction performs a SIMD computation of the approximate reciprocal of the low single-precision floating-\r\npoint value in the second source operand (the third operand) and stores the result in the low quadword element of\r\nthe destination operand (the first operand) according to the writemask k1. Bits (127:32) of the XMM register desti-\r\nnation are copied from corresponding bits in the first source operand (the second operand). The maximum relative\r\nerror for this approximation is less than 2-14. The source operand can be an XMM register or a 32-bit memory loca-\r\ntion. The destination operand is an XMM register.\r\nThe VRCP14SS instruction is not affected by the rounding control bits in the MXCSR register. When a source value\r\nis a 0.0, an inf with the sign of the source value is returned. A denormal source value will be treated as zero only in\r\ncase of DAZ bit set in MXCSR. Otherwise it is treated correctly (i.e. not as a 0.0). Underflow results are flushed to\r\nzero only in case of FTZ bit set in MXCSR. Otherwise it will be treated correctly (i.e. correct underflow result is\r\nwritten) with the sign of the operand. When a source value is a SNaN or QNaN, the SNaN is converted to a QNaN\r\nor the source QNaN is returned. See Table 5-16 for special-case input values.\r\nMXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.\r\nA numerically exact implementation of VRCP14xx can be found at https://software.intel.com/en-us/articles/refer-\r\nence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.\r\n\r\nOperation\r\nVRCP14SS (EVEX version)\r\nIF k1[0] OR *no writemask*\r\n THEN DEST[31:0] <- APPROXIMATE(1.0/SRC2[31:0]);\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[31:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:32] <- SRC1[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVRCP14SS __m128 _mm_rcp14_ss( __m128 a, __m128 b);\r\nVRCP14SS __m128 _mm_mask_rcp14_ss(__m128 s, __mmask8 k, __m128 a, __m128 b);\r\nVRCP14SS __m128 _mm_maskz_rcp14_ss( __mmask8 k, __m128 a, __m128 b);\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type E5.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VRCP14SS"
},
{
"description": "VRCP28PD-Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values\r\nwith Less Than 2^-28 Relative Error\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.512.66.0F38.W1 CA /r FV V/V AVX512ER Computes the approximate reciprocals ( < 2^-28 relative error)\r\n VRCP28PD zmm1 {k1}{z}, of the packed double-precision floating-point values in\r\n zmm2/m512/m64bcst {sae} zmm2/m512/m64bcst and stores the results in zmm1. Under\r\n writemask.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nComputes the reciprocal approximation of the float64 values in the source operand (the second operand) and store\r\nthe results to the destination operand (the first operand). The approximate reciprocal is evaluated with less than\r\n2^-28 of maximum relative error.\r\nDenormal input values are treated as zeros and do not signal #DE, irrespective of MXCSR.DAZ. Denormal results\r\nare flushed to zeros and do not signal #UE, irrespective of MXCSR.FZ.\r\nIf any source element is NaN, the quietized NaN source value is returned for that element. If any source element is\r\n+-inf, +-0.0 is returned for that element. Also, if any source element is +-0.0, +-inf is returned for that element.\r\nThe source operand is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit\r\nmemory location. The destination operand is a ZMM register, conditionally updated using writemask k1.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\nA numerically exact implementation of VRCP28xx can be found at https://software.intel.com/en-us/articles/refer-\r\nence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.\r\n\r\nOperation\r\nVRCP28PD (EVEX encoded versions)\r\n(KL, VL) = (8, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC *is memory*)\r\n THEN DEST[i+63:i] <- RCP_28_DP(1.0/SRC[63:0]);\r\n ELSE DEST[i+63:i] <- RCP_28_DP(1.0/SRC[i+63:i]);\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI;\r\n FI;\r\nENDFOR;\r\n\r\n\r\n\r\n\r\n\r\n Table 5-17. VRCP28PD Special Cases\r\n Input value Result value Comments\r\n NAN QNAN(input) If (SRC = SNaN) then #I\r\n 0<=X< 2-1022 INF Positive input denormal or zero; #Z\r\n -1022\r\n -2 < X <= -0 -INF Negative input denormal or zero; #Z\r\n X> 21022 +0.0f\r\n 1022\r\n X < -2 -0.0f\r\n X = +inf +0.0f\r\n X = -inf -0.0f\r\n X= 2-n 2n Exact result (unless input/output is a denormal)\r\n -n n\r\n X = -2 -2 Exact result (unless input/output is a denormal)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVRCP28PD __m512d _mm512_rcp28_round_pd ( __m512d a, int sae);\r\nVRCP28PD __m512d _mm512_mask_rcp28_round_pd(__m512d a, __mmask8 m, __m512d b, int sae);\r\nVRCP28PD __m512d _mm512_maskz_rcp28_round_pd( __mmask8 m, __m512d b, int sae);\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nInvalid (if SNaN input), Divide-by-zero\r\n\r\nOther Exceptions\r\n\r\nSee Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VRCP28PD"
},
{
"description": "VRCP28PS-Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values\r\nwith Less Than 2^-28 Relative Error\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.512.66.0F38.W0 CA /r FV V/V AVX512ER Computes the approximate reciprocals ( < 2^-28 relative\r\n VRCP28PS zmm1 {k1}{z}, error) of the packed single-precision floating-point values in\r\n zmm2/m512/m32bcst {sae} zmm2/m512/m32bcst and stores the results in zmm1. Under\r\n writemask.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nComputes the reciprocal approximation of the float32 values in the source operand (the second operand) and store\r\nthe results to the destination operand (the first operand) using the writemask k1. The approximate reciprocal is\r\nevaluated with less than 2^-28 of maximum relative error prior to final rounding. The final results are rounded to\r\n< 2^-23 relative error before written to the destination.\r\nDenormal input values are treated as zeros and do not signal #DE, irrespective of MXCSR.DAZ. Denormal results\r\nare flushed to zeros and do not signal #UE, irrespective of MXCSR.FZ.\r\nIf any source element is NaN, the quietized NaN source value is returned for that element. If any source element is\r\n+-inf, +-0.0 is returned for that element. Also, if any source element is +-0.0, +-inf is returned for that element.\r\nThe source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit\r\nmemory location. The destination operand is a ZMM register, conditionally updated using writemask k1.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\nA numerically exact implementation of VRCP28xx can be found at https://software.intel.com/en-us/articles/refer-\r\nence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.\r\n\r\nOperation\r\nVRCP28PS (EVEX encoded versions)\r\n(KL, VL) = (16, 512)\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC *is memory*)\r\n THEN DEST[i+31:i] <- RCP_28_SP(1.0/SRC[31:0]);\r\n ELSE DEST[i+31:i] <- RCP_28_SP(1.0/SRC[i+31:i]);\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI;\r\n FI;\r\nENDFOR;\r\n\r\n\r\n\r\n\r\n\r\n Table 5-19. VRCP28PS Special Cases\r\n Input value Result value Comments\r\n NAN QNAN(input) If (SRC = SNaN) then #I\r\n 0<=X< 2-126 INF Positive input denormal or zero; #Z\r\n -126\r\n -2 < X <= -0 -INF Negative input denormal or zero; #Z\r\n X> 2126 +0.0f\r\n 126\r\n X < -2 -0.0f\r\n X = +inf +0.0f\r\n X = -inf -0.0f\r\n X= 2-n 2n Exact result (unless input/output is a denormal)\r\n -n n\r\n X = -2 -2 Exact result (unless input/output is a denormal)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVRCP28PS _mm512_rcp28_round_ps ( __m512 a, int sae);\r\nVRCP28PS __m512 _mm512_mask_rcp28_round_ps(__m512 s, __mmask16 m, __m512 a, int sae);\r\nVRCP28PS __m512 _mm512_maskz_rcp28_round_ps( __mmask16 m, __m512 a, int sae);\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nInvalid (if SNaN input), Divide-by-zero\r\n\r\nOther Exceptions\r\n\r\nSee Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VRCP28PS"
},
{
"description": "VRCP28SD-Approximation to the Reciprocal of Scalar Double-Precision Floating-Point Value\r\nwith Less Than 2^-28 Relative Error\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.LIG.66.0F38.W1 CB /r T1S V/V AVX512ER Computes the approximate reciprocal ( < 2^-28 relative\r\n VRCP28SD xmm1 {k1}{z}, xmm2, error) of the scalar double-precision floating-point value\r\n xmm3/m64 {sae} in xmm3/m64 and stores the results in xmm1. Under\r\n writemask. Also, upper double-precision floating-point\r\n value (bits[127:64]) from xmm2 is copied to\r\n xmm1[127:64].\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nComputes the reciprocal approximation of the low float64 value in the second source operand (the third operand)\r\nand store the result to the destination operand (the first operand). The approximate reciprocal is evaluated with\r\nless than 2^-28 of maximum relative error. The result is written into the low float64 element of the destination\r\noperand according to the writemask k1. Bits 127:64 of the destination is copied from the corresponding bits of the\r\nfirst source operand (the second operand).\r\nA denormal input value is treated as zero and does not signal #DE, irrespective of MXCSR.DAZ. A denormal result\r\nis flushed to zero and does not signal #UE, irrespective of MXCSR.FZ.\r\nIf any source element is NaN, the quietized NaN source value is returned for that element. If any source element is\r\n+-inf, +-0.0 is returned for that element. Also, if any source element is +-0.0, +-inf is returned for that element.\r\nThe first source operand is an XMM register. The second source operand is an XMM register or a 64-bit memory\r\nlocation. The destination operand is a XMM register, conditionally updated using writemask k1.\r\nA numerically exact implementation of VRCP28xx can be found at https://software.intel.com/en-us/articles/refer-\r\nence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.\r\n\r\nOperation\r\nVRCP28SD ((EVEX encoded versions)\r\nIF k1[0] OR *no writemask* THEN\r\n DEST[63: 0] <- RCP_28_DP(1.0/SRC2[63: 0]);\r\nELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63: 0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[63: 0] <- 0\r\n FI;\r\nFI;\r\nENDFOR;\r\nDEST[127:64] <- SRC1[127: 64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\n Table 5-18. VRCP28SD Special Cases\r\n Input value Result value Comments\r\n NAN QNAN(input) If (SRC = SNaN) then #I\r\n 0<=X< 2-1022 INF Positive input denormal or zero; #Z\r\n -1022\r\n -2 < X <= -0 -INF Negative input denormal or zero; #Z\r\n X> 21022 +0.0f\r\n 1022\r\n X < -2 -0.0f\r\n X = +inf +0.0f\r\n X = -inf -0.0f\r\n X= 2-n 2n Exact result (unless input/output is a denormal)\r\n -n n\r\n X = -2 -2 Exact result (unless input/output is a denormal)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVRCP28SD __m128d _mm_rcp28_round_sd ( __m128d a, __m128d b, int sae);\r\nVRCP28SD __m128d _mm_mask_rcp28_round_sd(__m128d s, __mmask8 m, __m128d a, __m128d b, int sae);\r\nVRCP28SD __m128d _mm_maskz_rcp28_round_sd(__mmask8 m, __m128d a, __m128d b, int sae);\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nInvalid (if SNaN input), Divide-by-zero\r\n\r\nOther Exceptions\r\n\r\nSee Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VRCP28SD"
},
{
"description": "VRCP28SS-Approximation to the Reciprocal of Scalar Single-Precision Floating-Point Value\r\nwith Less Than 2^-28 Relative Error\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.LIG.66.0F38.W0 CB /r T1S V/V AVX512ER Computes the approximate reciprocal ( < 2^-28 relative\r\n VRCP28SS xmm1 {k1}{z}, error) of the scalar single-precision floating-point value in\r\n xmm2, xmm3/m32 {sae} xmm3/m32 and stores the results in xmm1. Under\r\n writemask. Also, upper 3 single-precision floating-point\r\n values (bits[127:32]) from xmm2 is copied to\r\n xmm1[127:32].\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nComputes the reciprocal approximation of the low float32 value in the second source operand (the third operand)\r\nand store the result to the destination operand (the first operand). The approximate reciprocal is evaluated with\r\nless than 2^-28 of maximum relative error prior to final rounding. The final result is rounded to < 2^-23 relative\r\nerror before written into the low float32 element of the destination according to writemask k1. Bits 127:32 of the\r\ndestination is copied from the corresponding bits of the first source operand (the second operand).\r\nA denormal input value is treated as zero and does not signal #DE, irrespective of MXCSR.DAZ. A denormal result\r\nis flushed to zero and does not signal #UE, irrespective of MXCSR.FZ.\r\nIf any source element is NaN, the quietized NaN source value is returned for that element. If any source element is\r\n+-inf, +-0.0 is returned for that element. Also, if any source element is +-0.0, +-inf is returned for that element.\r\nThe first source operand is an XMM register. The second source operand is an XMM register or a 32-bit memory\r\nlocation. The destination operand is a XMM register, conditionally updated using writemask k1.\r\nA numerically exact implementation of VRCP28xx can be found at https://software.intel.com/en-us/articles/refer-\r\nence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.\r\n\r\nOperation\r\nVRCP28SS ((EVEX encoded versions)\r\nIF k1[0] OR *no writemask* THEN\r\n DEST[31: 0] <- RCP_28_SP(1.0/SRC2[31: 0]);\r\nELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31: 0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[31: 0] <- 0\r\n FI;\r\nFI;\r\nENDFOR;\r\nDEST[127:32] <- SRC1[127: 32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\n Table 5-20. VRCP28SS Special Cases\r\n Input value Result value Comments\r\n NAN QNAN(input) If (SRC = SNaN) then #I\r\n 0<=X< 2-126 INF Positive input denormal or zero; #Z\r\n -126\r\n -2 < X <= -0 -INF Negative input denormal or zero; #Z\r\n X> 2126 +0.0f\r\n 126\r\n X < -2 -0.0f\r\n X = +inf +0.0f\r\n X = -inf -0.0f\r\n X= 2-n 2n Exact result (unless input/output is a denormal)\r\n -n n\r\n X = -2 -2 Exact result (unless input/output is a denormal)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n\r\nVRCP28SS __m128 _mm_rcp28_round_ss ( __m128 a, __m128 b, int sae);\r\nVRCP28SS __m128 _mm_mask_rcp28_round_ss(__m128 s, __mmask8 m, __m128 a, __m128 b, int sae);\r\nVRCP28SS __m128 _mm_maskz_rcp28_round_ss(__mmask8 m, __m128 a, __m128 b, int sae);\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nInvalid (if SNaN input), Divide-by-zero\r\n\r\nOther Exceptions\r\n\r\nSee Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VRCP28SS"
},
{
"description": "VREDUCEPD-Perform Reduction Transformation on Packed Float64 Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F3A.W1 56 /r ib FV V/V AVX512VL Perform reduction transformation on packed double-precision\r\n VREDUCEPD xmm1 {k1}{z}, AVX512DQ floating point values in xmm2/m128/m32bcst by subtracting\r\n xmm2/m128/m64bcst, imm8 a number of fraction bits specified by the imm8 field. Stores\r\n the result in xmm1 register under writemask k1.\r\n EVEX.256.66.0F3A.W1 56 /r ib FV V/V AVX512VL Perform reduction transformation on packed double-precision\r\n VREDUCEPD ymm1 {k1}{z}, AVX512DQ floating point values in ymm2/m256/m32bcst by subtracting\r\n ymm2/m256/m64bcst, imm8 a number of fraction bits specified by the imm8 field. Stores\r\n the result in ymm1 register under writemask k1.\r\n EVEX.512.66.0F3A.W1 56 /r ib FV V/V AVX512DQ Perform reduction transformation on double-precision floating\r\n VREDUCEPD zmm1 {k1}{z}, point values in zmm2/m512/m32bcst by subtracting a\r\n zmm2/m512/m64bcst{sae}, number of fraction bits specified by the imm8 field. Stores the\r\n imm8 result in zmm1 register under writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) Imm8 NA\r\n\r\nDescription\r\nPerform reduction transformation of the packed binary encoded double-precision FP values in the source operand\r\n(the second operand) and store the reduced results in binary FP format to the destination operand (the first\r\noperand) under the writemask k1.\r\nThe reduction transformation subtracts the integer part and the leading M fractional bits from the binary FP source\r\nvalue, where M is a unsigned integer specified by imm8[7:4], see Figure 5-28. Specifically, the reduction transfor-\r\nmation can be expressed as:\r\ndest = src - (ROUND(2M*src))*2-M;\r\nwhere \"Round()\" treats \"src\", \"2M\", and their product as binary FP numbers with normalized significand and bi-\r\nased exponents.\r\nThe magnitude of the reduced result can be expressed by considering src= 2p*man2,\r\nwhere 'man2' is the normalized significand and 'p' is the unbiased exponent\r\nThen if RC = RNE: 0<=|Reduced Result|<=2p-M-1\r\nThen if RC != RNE: 0<=|Reduced Result|<2p-M\r\nThis instruction might end up with a precision exception set. However, in case of SPE set (i.e. Suppress Precision\r\nException, which is imm8[3]=1), no precision exception is reported.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\n\r\n\r\n\r\n 7 6 5 4 3 2 1 0\r\n\r\n imm8 Fixed point length SPE RS Round Control Override\r\n\r\n\r\n\r\n Suppress Precision Exception: Imm8[3] Imm8[1:0] = 00b : Round nearest even\r\n Imm8[3] = 0b : Use MXCSR exception mask Round Select: Imm8[2]\r\n Imm8[7:4] : Number of fixed points to subtract Imm8[1:0] = 01b : Round down\r\n Imm8[3] = 1b : Suppress Imm8[2] = 0b : Use Imm8[1:0]\r\n Imm8[1:0] = 10b : Round up\r\n Imm8[2] = 1b : Use MXCSR\r\n Imm8[1:0] = 11b : Truncate\r\n\r\n\r\n\r\n Figure 5-28. Imm8 Controls for VREDUCEPD/SD/PS/SS\r\n\r\n\r\n\r\n\r\nHandling of special case of input values are listed in Table 5-21.\r\n\r\n Table 5-21. VREDUCEPD/SD/PS/SS Special Cases\r\n Round Mode Returned value\r\n |Src1| < 2-M-1 RNE Src1\r\n RPI, Src1 > 0 Round (Src1-2-M) *\r\n RPI, Src1 <= 0 Src1\r\n RNI, Src1 >= 0 Src1\r\n |Src1| < 2-M RNI, Src1 < 0 Round (Src1+2-M) *\r\n NOT RNI +0.0\r\n Src1 = +-0, or\r\n Dest = +-0 (Src1!=INF) RNI -0.0\r\n Src1 = +-INF any +0.0\r\n Src1= +-NAN n/a QNaN(Src1)\r\n\r\n * Round control = (imm8.MS1)? MXCSR.RC: imm8.RC\r\n\r\nOperation\r\nReduceArgumentDP(SRC[63:0], imm8[7:0])\r\n{\r\n // Check for NaN\r\n IF (SRC [63:0] = NAN) THEN\r\n RETURN (Convert SRC[63:0] to QNaN); FI;\r\n M <- imm8[7:4]; // Number of fraction bits of the normalized significand to be subtracted\r\n RC <- imm8[1:0];// Round Control for ROUND() operation\r\n RC source <- imm[2];\r\n SPE <- 0;// Suppress Precision Exception\r\n TMP[63:0] <- 2-M *{ROUND(2M*SRC[63:0], SPE, RC_source, RC)}; // ROUND() treats SRC and 2M as standard binary FP values\r\n TMP[63:0] <- SRC[63:0] - TMP[63:0]; // subtraction under the same RC,SPE controls\r\n RETURN TMP[63:0]; // binary encoded FP with biased exponent and normalized significand\r\n}\r\n\r\nVREDUCEPD\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b == 1) AND (SRC *is memory*)\r\n THEN DEST[i+63:i] <- ReduceArgumentDP(SRC[63:0], imm8[7:0]);\r\n ELSE DEST[i+63:i] <- ReduceArgumentDP(SRC[i+63:i], imm8[7:0]);\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] = 0\r\n FI;\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVREDUCEPD __m512d _mm512_mask_reduce_pd( __m512d a, int imm, int sae)\r\nVREDUCEPD __m512d _mm512_mask_reduce_pd(__m512d s, __mmask8 k, __m512d a, int imm, int sae)\r\nVREDUCEPD __m512d _mm512_maskz_reduce_pd(__mmask8 k, __m512d a, int imm, int sae)\r\nVREDUCEPD __m256d _mm256_mask_reduce_pd( __m256d a, int imm)\r\nVREDUCEPD __m256d _mm256_mask_reduce_pd(__m256d s, __mmask8 k, __m256d a, int imm)\r\nVREDUCEPD __m256d _mm256_maskz_reduce_pd(__mmask8 k, __m256d a, int imm)\r\nVREDUCEPD __m128d _mm_mask_reduce_pd( __m128d a, int imm)\r\nVREDUCEPD __m128d _mm_mask_reduce_pd(__m128d s, __mmask8 k, __m128d a, int imm)\r\nVREDUCEPD __m128d _mm_maskz_reduce_pd(__mmask8 k, __m128d a, int imm)\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nInvalid, Precision\r\nIf SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).\r\n\r\nOther Exceptions\r\nSee Exceptions Type E2, additionally\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VREDUCEPD"
},
{
"description": "VREDUCEPS-Perform Reduction Transformation on Packed Float32 Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F3A.W0 56 /r ib FV V/V AVX512VL Perform reduction transformation on packed single-precision\r\n VREDUCEPS xmm1 {k1}{z}, AVX512DQ floating point values in xmm2/m128/m32bcst by subtracting\r\n xmm2/m128/m32bcst, imm8 a number of fraction bits specified by the imm8 field. Stores\r\n the result in xmm1 register under writemask k1.\r\n EVEX.256.66.0F3A.W0 56 /r ib FV V/V AVX512VL Perform reduction transformation on packed single-precision\r\n VREDUCEPS ymm1 {k1}{z}, AVX512DQ floating point values in ymm2/m256/m32bcst by subtracting\r\n ymm2/m256/m32bcst, imm8 a number of fraction bits specified by the imm8 field. Stores\r\n the result in ymm1 register under writemask k1.\r\n EVEX.512.66.0F3A.W0 56 /r ib FV V/V AVX512DQ Perform reduction transformation on packed single-precision\r\n VREDUCEPS zmm1 {k1}{z}, floating point values in zmm2/m512/m32bcst by subtracting\r\n zmm2/m512/m32bcst{sae}, a number of fraction bits specified by the imm8 field. Stores\r\n imm8 the result in zmm1 register under writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) Imm8 NA\r\n\r\nDescription\r\nPerform reduction transformation of the packed binary encoded single-precision FP values in the source operand\r\n(the second operand) and store the reduced results in binary FP format to the destination operand (the first\r\noperand) under the writemask k1.\r\nThe reduction transformation subtracts the integer part and the leading M fractional bits from the binary FP source\r\nvalue, where M is a unsigned integer specified by imm8[7:4], see Figure 5-28. Specifically, the reduction transfor-\r\nmation can be expressed as:\r\ndest = src - (ROUND(2M*src))*2-M;\r\nwhere \"Round()\" treats \"src\", \"2M\", and their product as binary FP numbers with normalized significand and bi-\r\nased exponents.\r\nThe magnitude of the reduced result can be expressed by considering src= 2p*man2,\r\nwhere 'man2' is the normalized significand and 'p' is the unbiased exponent\r\nThen if RC = RNE: 0<=|Reduced Result|<=2p-M-1\r\nThen if RC != RNE: 0<=|Reduced Result|<2p-M\r\n\r\n\r\nThis instruction might end up with a precision exception set. However, in case of SPE set (i.e. Suppress Precision\r\nException, which is imm8[3]=1), no precision exception is reported.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\nHandling of special case of input values are listed in Table 5-21.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nReduceArgumentSP(SRC[31:0], imm8[7:0])\r\n{\r\n // Check for NaN\r\n IF (SRC [31:0] = NAN) THEN\r\n RETURN (Convert SRC[31:0] to QNaN); FI\r\n M <- imm8[7:4]; // Number of fraction bits of the normalized significand to be subtracted\r\n RC <- imm8[1:0];// Round Control for ROUND() operation\r\n RC source <- imm[2];\r\n SPE <- 0;// Suppress Precision Exception\r\n TMP[31:0] <- 2-M *{ROUND(2M*SRC[31:0], SPE, RC_source, RC)}; // ROUND() treats SRC and 2M as standard binary FP values\r\n TMP[31:0] <- SRC[31:0] - TMP[31:0]; // subtraction under the same RC,SPE controls\r\nRETURN TMP[31:0]; // binary encoded FP with biased exponent and normalized significand\r\n}\r\n\r\nVREDUCEPS\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b == 1) AND (SRC *is memory*)\r\n THEN DEST[i+31:i] <- ReduceArgumentSP(SRC[31:0], imm8[7:0]);\r\n ELSE DEST[i+31:i] <- ReduceArgumentSP(SRC[i+31:i], imm8[7:0]);\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] = 0\r\n FI;\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVREDUCEPS __m512 _mm512_mask_reduce_ps( __m512 a, int imm, int sae)\r\nVREDUCEPS __m512 _mm512_mask_reduce_ps(__m512 s, __mmask16 k, __m512 a, int imm, int sae)\r\nVREDUCEPS __m512 _mm512_maskz_reduce_ps(__mmask16 k, __m512 a, int imm, int sae)\r\nVREDUCEPS __m256 _mm256_mask_reduce_ps( __m256 a, int imm)\r\nVREDUCEPS __m256 _mm256_mask_reduce_ps(__m256 s, __mmask8 k, __m256 a, int imm)\r\nVREDUCEPS __m256 _mm256_maskz_reduce_ps(__mmask8 k, __m256 a, int imm)\r\nVREDUCEPS __m128 _mm_mask_reduce_ps( __m128 a, int imm)\r\nVREDUCEPS __m128 _mm_mask_reduce_ps(__m128 s, __mmask8 k, __m128 a, int imm)\r\nVREDUCEPS __m128 _mm_maskz_reduce_ps(__mmask8 k, __m128 a, int imm)\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nInvalid, Precision\r\nIf SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).\r\n\r\nOther Exceptions\r\nSee Exceptions Type E2, additionally\r\n#UD If EVEX.vvvv != 1111B.\r\n\r\n\r\n\r\n",
"mnem": "VREDUCEPS"
},
{
"description": "VREDUCESD-Perform a Reduction Transformation on a Scalar Float64 Value\r\n Opcode/ Op / 64/32 bit CPUID Description\r\n Instruction En Mode Feature\r\n Support Flag\r\n EVEX.NDS.LIG.66.0F3A.W1 57 T1S V/V AVX512D Perform a reduction transformation on a scalar double-precision\r\n VREDUCESD xmm1 {k1}{z}, Q floating point value in xmm3/m64 by subtracting a number of\r\n xmm2, xmm3/m64{sae}, fraction bits specified by the imm8 field. Also, upper double\r\n imm8/r precision floating-point value (bits[127:64]) from xmm2 are\r\n copied to xmm1[127:64]. Stores the result in xmm1 register.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerform a reduction transformation of the binary encoded double-precision FP value in the low qword element of\r\nthe second source operand (the third operand) and store the reduced result in binary FP format to the low qword\r\nelement of the destination operand (the first operand) under the writemask k1. Bits 127:64 of the destination\r\noperand are copied from respective qword elements of the first source operand (the second operand).\r\nThe reduction transformation subtracts the integer part and the leading M fractional bits from the binary FP source\r\nvalue, where M is a unsigned integer specified by imm8[7:4], see Figure 5-28. Specifically, the reduction transfor-\r\nmation can be expressed as:\r\ndest = src - (ROUND(2M*src))*2-M;\r\nwhere \"Round()\" treats \"src\", \"2M\", and their product as binary FP numbers with normalized significand and bi-\r\nased exponents.\r\nThe magnitude of the reduced result can be expressed by considering src= 2p*man2,\r\nwhere 'man2' is the normalized significand and 'p' is the unbiased exponent\r\nThen if RC = RNE: 0<=|Reduced Result|<=2p-M-1\r\nThen if RC != RNE: 0<=|Reduced Result|<2p-M\r\nThis instruction might end up with a precision exception set. However, in case of SPE set (i.e. Suppress Precision\r\nException, which is imm8[3]=1), no precision exception is reported.\r\nThe operation is write masked.\r\nHandling of special case of input values are listed in Table 5-21.\r\n\r\nOperation\r\nReduceArgumentDP(SRC[63:0], imm8[7:0])\r\n{\r\n // Check for NaN\r\n IF (SRC [63:0] = NAN) THEN\r\n RETURN (Convert SRC[63:0] to QNaN); FI;\r\n M <- imm8[7:4]; // Number of fraction bits of the normalized significand to be subtracted\r\n RC <- imm8[1:0];// Round Control for ROUND() operation\r\n RC source <- imm[2];\r\n SPE <- 0;// Suppress Precision Exception\r\n TMP[63:0] <- 2-M *{ROUND(2M*SRC[63:0], SPE, RC_source, RC)}; // ROUND() treats SRC and 2M as standard binary FP values\r\n TMP[63:0] <- SRC[63:0] - TMP[63:0]; // subtraction under the same RC,SPE controls\r\n RETURN TMP[63:0]; // binary encoded FP with biased exponent and normalized significand\r\n}\r\n\r\n\r\n\r\n\r\n\r\nVREDUCESD\r\nIF k1[0] or *no writemask*\r\n THEN DEST[63:0] <- ReduceArgumentDP(SRC2[63:0], imm8[7:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[63:0] = 0\r\n FI;\r\nFI;\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVREDUCESD __m128d _mm_mask_reduce_sd( __m128d a, __m128d b, int imm, int sae)\r\nVREDUCESD __m128d _mm_mask_reduce_sd(__m128d s, __mmask16 k, __m128d a, __m128d b, int imm, int sae)\r\nVREDUCESD __m128d _mm_maskz_reduce_sd(__mmask16 k, __m128d a, __m128d b, int imm, int sae)\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nInvalid, Precision\r\nIf SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).\r\n\r\nOther Exceptions\r\nSee Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VREDUCESD"
},
{
"description": "VREDUCESS-Perform a Reduction Transformation on a Scalar Float32 Value\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.LIG.66.0F3A.W0 57 T1S V/V AVX512DQ Perform a reduction transformation on a scalar single-precision\r\n /r /ib floating point value in xmm3/m32 by subtracting a number of\r\n VREDUCESS xmm1 {k1}{z}, fraction bits specified by the imm8 field. Also, upper single\r\n xmm2, xmm3/m32{sae}, precision floating-point values (bits[127:32]) from xmm2 are\r\n imm8 copied to xmm1[127:32]. Stores the result in xmm1 register.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerform a reduction transformation of the binary encoded single-precision FP value in the low dword element of the\r\nsecond source operand (the third operand) and store the reduced result in binary FP format to the low dword\r\nelement of the destination operand (the first operand) under the writemask k1. Bits 127:32 of the destination\r\noperand are copied from respective dword elements of the first source operand (the second operand).\r\nThe reduction transformation subtracts the integer part and the leading M fractional bits from the binary FP source\r\nvalue, where M is a unsigned integer specified by imm8[7:4], see Figure 5-28. Specifically, the reduction transfor-\r\nmation can be expressed as:\r\ndest = src - (ROUND(2M*src))*2-M;\r\nwhere \"Round()\" treats \"src\", \"2M\", and their product as binary FP numbers with normalized significand and bi-\r\nased exponents.\r\nThe magnitude of the reduced result can be expressed by considering src= 2p*man2,\r\nwhere 'man2' is the normalized significand and 'p' is the unbiased exponent\r\nThen if RC = RNE: 0<=|Reduced Result|<=2p-M-1\r\nThen if RC != RNE: 0<=|Reduced Result|<2p-M\r\n\r\n\r\nThis instruction might end up with a precision exception set. However, in case of SPE set (i.e. Suppress Precision\r\nException, which is imm8[3]=1), no precision exception is reported.\r\nHandling of special case of input values are listed in Table 5-21.\r\n\r\nOperation\r\nReduceArgumentSP(SRC[31:0], imm8[7:0])\r\n{\r\n // Check for NaN\r\n IF (SRC [31:0] = NAN) THEN\r\n RETURN (Convert SRC[31:0] to QNaN); FI\r\n M <- imm8[7:4]; // Number of fraction bits of the normalized significand to be subtracted\r\n RC <- imm8[1:0];// Round Control for ROUND() operation\r\n RC source <- imm[2];\r\n SPE <- 0;// Suppress Precision Exception\r\n TMP[31:0] <- 2-M *{ROUND(2M*SRC[31:0], SPE, RC_source, RC)}; // ROUND() treats SRC and 2M as standard binary FP values\r\n TMP[31:0] <- SRC[31:0] - TMP[31:0]; // subtraction under the same RC,SPE controls\r\nRETURN TMP[31:0]; // binary encoded FP with biased exponent and normalized significand\r\n}\r\n\r\n\r\n\r\n\r\n\r\nVREDUCESS\r\nIF k1[0] or *no writemask*\r\n THEN DEST[31:0] <- ReduceArgumentSP(SRC2[31:0], imm8[7:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[31:0] = 0\r\n FI;\r\nFI;\r\nDEST[127:32] <- SRC1[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVREDUCESS __m128 _mm_mask_reduce_ss( __m128 a, __m128 b, int imm, int sae)\r\nVREDUCESS __m128 _mm_mask_reduce_ss(__m128 s, __mmask16 k, __m128 a, __m128 b, int imm, int sae)\r\nVREDUCESS __m128 _mm_maskz_reduce_ss(__mmask16 k, __m128 a, __m128 b, int imm, int sae)\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nInvalid, Precision\r\nIf SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).\r\n\r\nOther Exceptions\r\nSee Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VREDUCESS"
},
{
"description": "VRNDSCALEPD-Round Packed Float64 Values To Include A Given Number Of Fraction Bits\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F3A.W1 09 /r ib FV V/V AVX512VL Rounds packed double-precision floating point values in\r\n VRNDSCALEPD xmm1 {k1}{z}, AVX512F xmm2/m128/m64bcst to a number of fraction bits\r\n xmm2/m128/m64bcst, imm8 specified by the imm8 field. Stores the result in xmm1\r\n register. Under writemask.\r\n EVEX.256.66.0F3A.W1 09 /r ib FV V/V AVX512VL Rounds packed double-precision floating point values in\r\n VRNDSCALEPD ymm1 {k1}{z}, AVX512F ymm2/m256/m64bcst to a number of fraction bits\r\n ymm2/m256/m64bcst, imm8 specified by the imm8 field. Stores the result in ymm1\r\n register. Under writemask.\r\n EVEX.512.66.0F3A.W1 09 /r ib FV V/V AVX512F Rounds packed double-precision floating-point values in\r\n VRNDSCALEPD zmm1 {k1}{z}, zmm2/m512/m64bcst to a number of fraction bits\r\n zmm2/m512/m64bcst{sae}, imm8 specified by the imm8 field. Stores the result in zmm1\r\n register using writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) Imm8 NA\r\n\r\nDescription\r\nRound the double-precision floating-point values in the source operand by the rounding mode specified in the\r\nimmediate operand (see Figure 5-29) and places the result in the destination operand.\r\nThe destination operand (the first operand) is a ZMM/YMM/XMM register conditionally updated according to the\r\nwritemask. The source operand (the second operand) can be a ZMM/YMM/XMM register, a 512/256/128-bit\r\nmemory location, or a 512/256/128-bit vector broadcasted from a 64-bit memory location.\r\nThe rounding process rounds the input to an integral value, plus number bits of fraction that are specified by\r\nimm8[7:4] (to be included in the result) and returns the result as a double-precision floating-point value.\r\nIt should be noticed that no overflow is induced while executing this instruction (although the source is scaled by\r\nthe imm8[7:4] value).\r\nThe immediate operand also specifies control fields for the rounding operation, three bit fields are defined and\r\nshown in the \"Immediate Control Description\" figure below. Bit 3 of the immediate byte controls the processor\r\nbehavior for a precision exception, bit 2 selects the source of rounding mode control. Bits 1:0 specify a non-sticky\r\nrounding-mode value (Immediate control table below lists the encoded values for rounding-mode field).\r\nThe Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an\r\nSNaN then it will be converted to a QNaN. If DAZ is set to '1 then denormals will be converted to zero before\r\nrounding.\r\nThe sign of the result of this instruction is preserved, including the sign of zero.\r\nThe formula of the operation on each data element for VRNDSCALEPD is\r\n ROUND(x) = 2-M*Round_to_INT(x*2M, round_ctrl),\r\n round_ctrl = imm[3:0];\r\n M=imm[7:4];\r\nThe operation of x*2M is computed as if the exponent range is unlimited (i.e. no overflow ever occurs).\r\n\r\n\r\n\r\n\r\n\r\nVRNDSCALEPD is a more general form of the VEX-encoded VROUNDPD instruction. In VROUNDPD, the formula of\r\nthe operation on each element is\r\n ROUND(x) = Round_to_INT(x, round_ctrl),\r\n round_ctrl = imm[3:0];\r\n\r\n\r\nNote: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\n\r\n\r\n 7 6 5 4 3 2 1 0\r\n\r\n imm8 Fixed point length SPE RS Round Control Override\r\n\r\n\r\n\r\n Suppress Precision Exception: Imm8[3] Imm8[1:0] = 00b : Round nearest even\r\n Imm8[3] = 0b : Use MXCSR exception mask Round Select: Imm8[2]\r\n Imm8[7:4] : Number of fixed points to preserve Imm8[1:0] = 01b : Round down\r\n Imm8[3] = 1b : Suppress Imm8[2] = 0b : Use Imm8[1:0]\r\n Imm8[1:0] = 10b : Round up\r\n Imm8[2] = 1b : Use MXCSR\r\n Imm8[1:0] = 11b : Truncate\r\n\r\n\r\n\r\n Figure 5-29. Imm8 Controls for VRNDSCALEPD/SD/PS/SS\r\n\r\n\r\nHandling of special case of input values are listed in Table 5-22.\r\n\r\n Table 5-22. VRNDSCALEPD/SD/PS/SS Special Cases\r\n Returned value\r\nSrc1=+-inf Src1\r\nSrc1=+-NAN Src1 converted to QNAN\r\nSrc1=+-0 Src1\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nRoundToIntegerDP(SRC[63:0], imm8[7:0]) {\r\n if (imm8[2] = 1)\r\n rounding_direction <- MXCSR:RC ; get round control from MXCSR\r\n else\r\n rounding_direction <- imm8[1:0] ; get round control from imm8[1:0]\r\n FI\r\n M <- imm8[7:4] ; get the scaling factor\r\n\r\n case (rounding_direction)\r\n 00: TMP[63:0] <- round_to_nearest_even_integer(2M*SRC[63:0])\r\n 01: TMP[63:0] <- round_to_equal_or_smaller_integer(2M*SRC[63:0])\r\n 10: TMP[63:0] <- round_to_equal_or_larger_integer(2M*SRC[63:0])\r\n 11: TMP[63:0] <- round_to_nearest_smallest_magnitude_integer(2M*SRC[63:0])\r\n ESAC\r\n\r\n Dest[63:0] <- 2-M* TMP[63:0] ; scale down back to 2-M\r\n\r\n if (imm8[3] = 0) Then ; check SPE\r\n if (SRC[63:0] != Dest[63:0]) Then ; check precision lost\r\n set_precision() ; set #PE\r\n FI;\r\n FI;\r\n return(Dest[63:0])\r\n}\r\n\r\n\r\n\r\n\r\n\r\nVRNDSCALEPD (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF *src is a memory operand*\r\n THEN TMP_SRC <- BROADCAST64(SRC, VL, k1)\r\n ELSE TMP_SRC <- SRC\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- RoundToIntegerDP((TMP_SRC[i+63:i], imm8[7:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI;\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVRNDSCALEPD __m512d _mm512_roundscale_pd( __m512d a, int imm);\r\nVRNDSCALEPD __m512d _mm512_roundscale_round_pd( __m512d a, int imm, int sae);\r\nVRNDSCALEPD __m512d _mm512_mask_roundscale_pd(__m512d s, __mmask8 k, __m512d a, int imm);\r\nVRNDSCALEPD __m512d _mm512_mask_roundscale_round_pd(__m512d s, __mmask8 k, __m512d a, int imm, int sae);\r\nVRNDSCALEPD __m512d _mm512_maskz_roundscale_pd( __mmask8 k, __m512d a, int imm);\r\nVRNDSCALEPD __m512d _mm512_maskz_roundscale_round_pd( __mmask8 k, __m512d a, int imm, int sae);\r\nVRNDSCALEPD __m256d _mm256_roundscale_pd( __m256d a, int imm);\r\nVRNDSCALEPD __m256d _mm256_mask_roundscale_pd(__m256d s, __mmask8 k, __m256d a, int imm);\r\nVRNDSCALEPD __m256d _mm256_maskz_roundscale_pd( __mmask8 k, __m256d a, int imm);\r\nVRNDSCALEPD __m128d _mm_roundscale_pd( __m128d a, int imm);\r\nVRNDSCALEPD __m128d _mm_mask_roundscale_pd(__m128d s, __mmask8 k, __m128d a, int imm);\r\nVRNDSCALEPD __m128d _mm_maskz_roundscale_pd( __mmask8 k, __m128d a, int imm);\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nInvalid, Precision\r\nIf SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).\r\n\r\nOther Exceptions\r\nSee Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VRNDSCALEPD"
},
{
"description": "VRNDSCALEPS-Round Packed Float32 Values To Include A Given Number Of Fraction Bits\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F3A.W0 08 /r ib FV V/V AVX512VL Rounds packed single-precision floating point values in\r\n VRNDSCALEPS xmm1 {k1}{z}, AVX512F xmm2/m128/m32bcst to a number of fraction bits\r\n xmm2/m128/m32bcst, imm8 specified by the imm8 field. Stores the result in xmm1\r\n register. Under writemask.\r\n EVEX.256.66.0F3A.W0 08 /r ib FV V/V AVX512VL Rounds packed single-precision floating point values in\r\n VRNDSCALEPS ymm1 {k1}{z}, AVX512F ymm2/m256/m32bcst to a number of fraction bits\r\n ymm2/m256/m32bcst, imm8 specified by the imm8 field. Stores the result in ymm1\r\n register. Under writemask.\r\n EVEX.512.66.0F3A.W0 08 /r ib FV V/V AVX512F Rounds packed single-precision floating-point values in\r\n VRNDSCALEPS zmm1 {k1}{z}, zmm2/m512/m32bcst to a number of fraction bits\r\n zmm2/m512/m32bcst{sae}, imm8 specified by the imm8 field. Stores the result in zmm1\r\n register using writemask.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) Imm8 NA\r\n\r\nDescription\r\nRound the single-precision floating-point values in the source operand by the rounding mode specified in the imme-\r\ndiate operand (see Figure 5-29) and places the result in the destination operand.\r\nThe destination operand (the first operand) is a ZMM register conditionally updated according to the writemask.\r\nThe source operand (the second operand) can be a ZMM register, a 512-bit memory location, or a 512-bit vector\r\nbroadcasted from a 32-bit memory location.\r\nThe rounding process rounds the input to an integral value, plus number bits of fraction that are specified by\r\nimm8[7:4] (to be included in the result) and returns the result as a single-precision floating-point value.\r\nIt should be noticed that no overflow is induced while executing this instruction (although the source is scaled by\r\nthe imm8[7:4] value).\r\nThe immediate operand also specifies control fields for the rounding operation, three bit fields are defined and\r\nshown in the \"Immediate Control Description\" figure below. Bit 3 of the immediate byte controls the processor\r\nbehavior for a precision exception, bit 2 selects the source of rounding mode control. Bits 1:0 specify a non-sticky\r\nrounding-mode value (Immediate control table below lists the encoded values for rounding-mode field).\r\nThe Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an\r\nSNaN then it will be converted to a QNaN. If DAZ is set to '1 then denormals will be converted to zero before\r\nrounding.\r\nThe sign of the result of this instruction is preserved, including the sign of zero.\r\n\r\n\r\nThe formula of the operation on each data element for VRNDSCALEPS is\r\n ROUND(x) = 2-M*Round_to_INT(x*2M, round_ctrl),\r\n round_ctrl = imm[3:0];\r\n M=imm[7:4];\r\nThe operation of x*2M is computed as if the exponent range is unlimited (i.e. no overflow ever occurs).\r\nVRNDSCALEPS is a more general form of the VEX-encoded VROUNDPS instruction. In VROUNDPS, the formula of\r\nthe operation on each element is\r\n ROUND(x) = Round_to_INT(x, round_ctrl),\r\n round_ctrl = imm[3:0];\r\n\r\n\r\n\r\n\r\nNote: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\nHandling of special case of input values are listed in Table 5-22.\r\n\r\n\r\n\r\nOperation\r\nRoundToIntegerSP(SRC[31:0], imm8[7:0]) {\r\n if (imm8[2] = 1)\r\n rounding_direction <- MXCSR:RC ; get round control from MXCSR\r\n else\r\n rounding_direction <- imm8[1:0] ; get round control from imm8[1:0]\r\n FI\r\n M <- imm8[7:4] ; get the scaling factor\r\n\r\n case (rounding_direction)\r\n 00: TMP[31:0] <- round_to_nearest_even_integer(2M*SRC[31:0])\r\n 01: TMP[31:0] <- round_to_equal_or_smaller_integer(2M*SRC[31:0])\r\n 10: TMP[31:0] <- round_to_equal_or_larger_integer(2M*SRC[31:0])\r\n 11: TMP[31:0] <- round_to_nearest_smallest_magnitude_integer(2M*SRC[31:0])\r\n ESAC;\r\n\r\n Dest[31:0] <- 2-M* TMP[31:0] ; scale down back to 2-M\r\n if (imm8[3] = 0) Then ; check SPE\r\n if (SRC[31:0] != Dest[31:0]) Then ; check precision lost\r\n set_precision() ; set #PE\r\n FI;\r\n FI;\r\n return(Dest[31:0])\r\n}\r\n\r\nVRNDSCALEPS (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF *src is a memory operand*\r\n THEN TMP_SRC <- BROADCAST32(SRC, VL, k1)\r\n ELSE TMP_SRC <- SRC\r\nFI;\r\n\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- RoundToIntegerSP(TMP_SRC[i+31:i]), imm8[7:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI;\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVRNDSCALEPS __m512 _mm512_roundscale_ps( __m512 a, int imm);\r\nVRNDSCALEPS __m512 _mm512_roundscale_round_ps( __m512 a, int imm, int sae);\r\nVRNDSCALEPS __m512 _mm512_mask_roundscale_ps(__m512 s, __mmask16 k, __m512 a, int imm);\r\nVRNDSCALEPS __m512 _mm512_mask_roundscale_round_ps(__m512 s, __mmask16 k, __m512 a, int imm, int sae);\r\nVRNDSCALEPS __m512 _mm512_maskz_roundscale_ps( __mmask16 k, __m512 a, int imm);\r\nVRNDSCALEPS __m512 _mm512_maskz_roundscale_round_ps( __mmask16 k, __m512 a, int imm, int sae);\r\nVRNDSCALEPS __m256 _mm256_roundscale_ps( __m256 a, int imm);\r\nVRNDSCALEPS __m256 _mm256_mask_roundscale_ps(__m256 s, __mmask8 k, __m256 a, int imm);\r\nVRNDSCALEPS __m256 _mm256_maskz_roundscale_ps( __mmask8 k, __m256 a, int imm);\r\nVRNDSCALEPS __m128 _mm_roundscale_ps( __m256 a, int imm);\r\nVRNDSCALEPS __m128 _mm_mask_roundscale_ps(__m128 s, __mmask8 k, __m128 a, int imm);\r\nVRNDSCALEPS __m128 _mm_maskz_roundscale_ps( __mmask8 k, __m128 a, int imm);\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nInvalid, Precision\r\nIf SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).\r\n\r\nOther Exceptions\r\nSee Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VRNDSCALEPS"
},
{
"description": "VRNDSCALESD-Round Scalar Float64 Value To Include A Given Number Of Fraction Bits\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.LIG.66.0F3A.W1 0B /r ib T1S V/V AVX512F Rounds scalar double-precision floating-point value in\r\n VRNDSCALESD xmm1 {k1}{z}, xmm2, xmm3/m64 to a number of fraction bits specified by the\r\n xmm3/m64{sae}, imm8 imm8 field. Stores the result in xmm1 register.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) Imm8\r\n\r\nDescription\r\nRounds a double-precision floating-point value in the low quadword (see Figure 5-29) element the second source\r\noperand (the third operand) by the rounding mode specified in the immediate operand and places the result in the\r\ncorresponding element of the destination operand (the third operand) according to the writemask. The quadword\r\nelement at bits 127:64 of the destination is copied from the first source operand (the second operand).\r\nThe destination and first source operands are XMM registers, the 2nd source operand can be an XMM register or\r\nmemory location. Bits MAX_VL-1:128 of the destination register are cleared.\r\nThe rounding process rounds the input to an integral value, plus number bits of fraction that are specified by\r\nimm8[7:4] (to be included in the result) and returns the result as a double-precision floating-point value.\r\nIt should be noticed that no overflow is induced while executing this instruction (although the source is scaled by\r\nthe imm8[7:4] value).\r\nThe immediate operand also specifies control fields for the rounding operation, three bit fields are defined and\r\nshown in the \"Immediate Control Description\" figure below. Bit 3 of the immediate byte controls the processor\r\nbehavior for a precision exception, bit 2 selects the source of rounding mode control. Bits 1:0 specify a non-sticky\r\nrounding-mode value (Immediate control table below lists the encoded values for rounding-mode field).\r\nThe Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an\r\nSNaN then it will be converted to a QNaN. If DAZ is set to '1 then denormals will be converted to zero before\r\nrounding.\r\nThe sign of the result of this instruction is preserved, including the sign of zero.\r\n\r\n\r\nThe formula of the operation for VRNDSCALESD is\r\n ROUND(x) = 2-M*Round_to_INT(x*2M, round_ctrl),\r\n round_ctrl = imm[3:0];\r\n M=imm[7:4];\r\nThe operation of x*2M is computed as if the exponent range is unlimited (i.e. no overflow ever occurs).\r\nVRNDSCALESD is a more general form of the VEX-encoded VROUNDSD instruction. In VROUNDSD, the formula of\r\nthe operation is\r\n ROUND(x) = Round_to_INT(x, round_ctrl),\r\n round_ctrl = imm[3:0];\r\n\r\n\r\nEVEX encoded version: The source operand is a XMM register or a 64-bit memory location. The destination operand\r\nis a XMM register.\r\nHandling of special case of input values are listed in Table 5-22.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nRoundToIntegerDP(SRC[63:0], imm8[7:0]) {\r\n if (imm8[2] = 1)\r\n rounding_direction <- MXCSR:RC ; get round control from MXCSR\r\n else\r\n rounding_direction <- imm8[1:0] ; get round control from imm8[1:0]\r\n FI\r\n M <- imm8[7:4] ; get the scaling factor\r\n\r\n case (rounding_direction)\r\n 00: TMP[63:0] <- round_to_nearest_even_integer(2M*SRC[63:0])\r\n 01: TMP[63:0] <- round_to_equal_or_smaller_integer(2M*SRC[63:0])\r\n 10: TMP[63:0] <- round_to_equal_or_larger_integer(2M*SRC[63:0])\r\n 11: TMP[63:0] <- round_to_nearest_smallest_magnitude_integer(2M*SRC[63:0])\r\n ESAC\r\n\r\n Dest[63:0] <- 2-M* TMP[63:0] ; scale down back to 2-M\r\n\r\n if (imm8[3] = 0) Then ; check SPE\r\n if (SRC[63:0] != Dest[63:0]) Then ; check precision lost\r\n set_precision() ; set #PE\r\n FI;\r\n FI;\r\n return(Dest[63:0])\r\n}\r\n\r\nVRNDSCALESD (EVEX encoded version)\r\nIF k1[0] or *no writemask*\r\n THEN DEST[63:0] <- RoundToIntegerDP(SRC2[63:0], Zero_upper_imm[7:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[63:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVRNDSCALESD __m128d _mm_roundscale_sd ( __m128d a, __m128d b, int imm);\r\nVRNDSCALESD __m128d _mm_roundscale_round_sd ( __m128d a, __m128d b, int imm, int sae);\r\nVRNDSCALESD __m128d _mm_mask_roundscale_sd (__m128d s, __mmask8 k, __m128d a, __m128d b, int imm);\r\nVRNDSCALESD __m128d _mm_mask_roundscale_round_sd (__m128d s, __mmask8 k, __m128d a, __m128d b, int imm, int sae);\r\nVRNDSCALESD __m128d _mm_maskz_roundscale_sd ( __mmask8 k, __m128d a, __m128d b, int imm);\r\nVRNDSCALESD __m128d _mm_maskz_roundscale_round_sd ( __mmask8 k, __m128d a, __m128d b, int imm, int sae);\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nInvalid, Precision\r\nIf SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).\r\n\r\nOther Exceptions\r\nSee Exceptions Type E3.\r\n\r\n\r\n",
"mnem": "VRNDSCALESD"
},
{
"description": "VRNDSCALESS-Round Scalar Float32 Value To Include A Given Number Of Fraction Bits\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.LIG.66.0F3A.W0 0A /r ib T1S V/V AVX512F Rounds scalar single-precision floating-point value in\r\n VRNDSCALESS xmm1 {k1}{z}, xmm2, xmm3/m32 to a number of fraction bits specified by the\r\n xmm3/m32{sae}, imm8 imm8 field. Stores the result in xmm1 register under\r\n writemask.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nRounds the single-precision floating-point value in the low doubleword element of the second source operand (the\r\nthird operand) by the rounding mode specified in the immediate operand (see Figure 5-29) and places the result in\r\nthe corresponding element of the destination operand (the first operand) according to the writemask. The double-\r\nword elements at bits 127:32 of the destination are copied from the first source operand (the second operand).\r\nThe destination and first source operands are XMM registers, the 2nd source operand can be an XMM register or\r\nmemory location. Bits MAX_VL-1:128 of the destination register are cleared.\r\nThe rounding process rounds the input to an integral value, plus number bits of fraction that are specified by\r\nimm8[7:4] (to be included in the result) and returns the result as a single-precision floating-point value.\r\nIt should be noticed that no overflow is induced while executing this instruction (although the source is scaled by\r\nthe imm8[7:4] value).\r\nThe immediate operand also specifies control fields for the rounding operation, three bit fields are defined and\r\nshown in the \"Immediate Control Description\" figure below. Bit 3 of the immediate byte controls the processor\r\nbehavior for a precision exception, bit 2 selects the source of rounding mode control. Bits 1:0 specify a non-sticky\r\nrounding-mode value (Immediate control tables below lists the encoded values for rounding-mode field).\r\nThe Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an\r\nSNaN then it will be converted to a QNaN. If DAZ is set to '1 then denormals will be converted to zero before\r\nrounding.\r\nThe sign of the result of this instruction is preserved, including the sign of zero.\r\n\r\n\r\nThe formula of the operation for VRNDSCALESS is\r\n ROUND(x) = 2-M*Round_to_INT(x*2M, round_ctrl),\r\n round_ctrl = imm[3:0];\r\n M=imm[7:4];\r\nThe operation of x*2M is computed as if the exponent range is unlimited (i.e. no overflow ever occurs).\r\nVRNDSCALESS is a more general form of the VEX-encoded VROUNDSS instruction. In VROUNDSS, the formula of\r\nthe operation on each element is\r\n ROUND(x) = Round_to_INT(x, round_ctrl),\r\n round_ctrl = imm[3:0];\r\n\r\n\r\nEVEX encoded version: The source operand is a XMM register or a 32-bit memory location. The destination operand\r\nis a XMM register.\r\nHandling of special case of input values are listed in Table 5-22.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nRoundToIntegerSP(SRC[31:0], imm8[7:0]) {\r\n if (imm8[2] = 1)\r\n rounding_direction <- MXCSR:RC ; get round control from MXCSR\r\n else\r\n rounding_direction <- imm8[1:0] ; get round control from imm8[1:0]\r\n FI\r\n M <- imm8[7:4] ; get the scaling factor\r\n\r\n case (rounding_direction)\r\n 00: TMP[31:0] <- round_to_nearest_even_integer(2M*SRC[31:0])\r\n 01: TMP[31:0] <- round_to_equal_or_smaller_integer(2M*SRC[31:0])\r\n 10: TMP[31:0] <- round_to_equal_or_larger_integer(2M*SRC[31:0])\r\n 11: TMP[31:0] <- round_to_nearest_smallest_magnitude_integer(2M*SRC[31:0])\r\n ESAC;\r\n\r\n Dest[31:0] <- 2-M* TMP[31:0] ; scale down back to 2-M\r\n if (imm8[3] = 0) Then ; check SPE\r\n if (SRC[31:0] != Dest[31:0]) Then ; check precision lost\r\n set_precision() ; set #PE\r\n FI;\r\n FI;\r\n return(Dest[31:0])\r\n}\r\n\r\nVRNDSCALESS (EVEX encoded version)\r\nIF k1[0] or *no writemask*\r\n THEN DEST[31:0] <- RoundToIntegerSP(SRC2[31:0], Zero_upper_imm[7:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[31:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:32] <- SRC1[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVRNDSCALESS __m128 _mm_roundscale_ss ( __m128 a, __m128 b, int imm);\r\nVRNDSCALESS __m128 _mm_roundscale_round_ss ( __m128 a, __m128 b, int imm, int sae);\r\nVRNDSCALESS __m128 _mm_mask_roundscale_ss (__m128 s, __mmask8 k, __m128 a, __m128 b, int imm);\r\nVRNDSCALESS __m128 _mm_mask_roundscale_round_ss (__m128 s, __mmask8 k, __m128 a, __m128 b, int imm, int sae);\r\nVRNDSCALESS __m128 _mm_maskz_roundscale_ss ( __mmask8 k, __m128 a, __m128 b, int imm);\r\nVRNDSCALESS __m128 _mm_maskz_roundscale_round_ss ( __mmask8 k, __m128 a, __m128 b, int imm, int sae);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Precision\r\nIf SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).\r\n\r\nOther Exceptions\r\nSee Exceptions Type E3.\r\n\r\n\r\n\r\n",
"mnem": "VRNDSCALESS"
},
{
"description": "VRSQRT14PD-Compute Approximate Reciprocals of Square Roots of Packed Float64 Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F38.W1 4E /r FV V/V AVX512VL Computes the approximate reciprocal square roots of the\r\n VRSQRT14PD xmm1 {k1}{z}, AVX512F packed double-precision floating-point values in\r\n xmm2/m128/m64bcst xmm2/m128/m64bcst and stores the results in xmm1.\r\n Under writemask.\r\n EVEX.256.66.0F38.W1 4E /r FV V/V AVX512VL Computes the approximate reciprocal square roots of the\r\n VRSQRT14PD ymm1 {k1}{z}, AVX512F packed double-precision floating-point values in\r\n ymm2/m256/m64bcst ymm2/m256/m64bcst and stores the results in ymm1.\r\n Under writemask.\r\n EVEX.512.66.0F38.W1 4E /r FV V/V AVX512F Computes the approximate reciprocal square roots of the\r\n VRSQRT14PD zmm1 {k1}{z}, packed double-precision floating-point values in\r\n zmm2/m512/m64bcst zmm2/m512/m64bcst and stores the results in zmm1\r\n under writemask.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nThis instruction performs a SIMD computation of the approximate reciprocals of the square roots of the eight\r\npacked double-precision floating-point values in the source operand (the second operand) and stores the packed\r\ndouble-precision floating-point results in the destination operand (the first operand) according to the writemask.\r\nThe maximum relative error for this approximation is less than 2-14.\r\nEVEX.512 encoded version: The source operand can be a ZMM register, a 512-bit memory location, or a 512-bit\r\nvector broadcasted from a 64-bit memory location. The destination operand is a ZMM register, conditionally\r\nupdated using writemask k1.\r\nEVEX.256 encoded version: The source operand is a YMM register, a 256-bit memory location, or a 256-bit vector\r\nbroadcasted from a 64-bit memory location. The destination operand is a YMM register, conditionally updated using\r\nwritemask k1.\r\nEVEX.128 encoded version: The source operand is a XMM register, a 128-bit memory location, or a 128-bit vector\r\nbroadcasted from a 64-bit memory location. The destination operand is a XMM register, conditionally updated using\r\nwritemask k1.\r\nThe VRSQRT14PD instruction is not affected by the rounding control bits in the MXCSR register. When a source\r\nvalue is a 0.0, an inf with the sign of the source value is returned. When the source operand is an +inf then +ZERO\r\nvalue is returned. A denormal source value is treated as zero only if DAZ bit is set in MXCSR. Otherwise it is treated\r\ncorrectly and performs the approximation with the specified masked response. When a source value is a negative\r\nvalue (other than 0.0) a floating-point QNaN_indefinite is returned. When a source value is an SNaN or QNaN, the\r\nSNaN is converted to a QNaN or the source QNaN is returned.\r\nMXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.\r\nNote: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\nA numerically exact implementation of VRSQRT14xx can be found at https://software.intel.com/en-us/arti-\r\ncles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVRSQRT14PD (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC *is memory*)\r\n THEN DEST[i+63:i] <- APPROXIMATE(1.0/ SQRT(SRC[63:0]));\r\n ELSE DEST[i+63:i] <- APPROXIMATE(1.0/ SQRT(SRC[i+63:i]));\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI;\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n Table 5-23. VRSQRT14PD Special Cases\r\n Input value Result value Comments\r\n Any denormal Normal Cannot generate overflow\r\n -2n n\r\n X=2 2\r\n X<0 QNaN_Indefinite Including -INF\r\n X = -0 -INF\r\n X = +0 +INF\r\n X = +INF +0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVRSQRT14PD __m512d _mm512_rsqrt14_pd( __m512d a);\r\nVRSQRT14PD __m512d _mm512_mask_rsqrt14_pd(__m512d s, __mmask8 k, __m512d a);\r\nVRSQRT14PD __m512d _mm512_maskz_rsqrt14_pd( __mmask8 k, __m512d a);\r\nVRSQRT14PD __m256d _mm256_rsqrt14_pd( __m256d a);\r\nVRSQRT14PD __m256d _mm512_mask_rsqrt14_pd(__m256d s, __mmask8 k, __m256d a);\r\nVRSQRT14PD __m256d _mm512_maskz_rsqrt14_pd( __mmask8 k, __m256d a);\r\nVRSQRT14PD __m128d _mm_rsqrt14_pd( __m128d a);\r\nVRSQRT14PD __m128d _mm_mask_rsqrt14_pd(__m128d s, __mmask8 k, __m128d a);\r\nVRSQRT14PD __m128d _mm_maskz_rsqrt14_pd( __mmask8 k, __m128d a);\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VRSQRT14PD"
},
{
"description": "VRSQRT14PS-Compute Approximate Reciprocals of Square Roots of Packed Float32 Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F38.W0 4E /r FV V/V AVX512VL Computes the approximate reciprocal square roots of the\r\n VRSQRT14PS xmm1 {k1}{z}, AVX512F packed single-precision floating-point values in\r\n xmm2/m128/m32bcst xmm2/m128/m32bcst and stores the results in xmm1.\r\n Under writemask.\r\n EVEX.256.66.0F38.W0 4E /r FV V/V AVX512VL Computes the approximate reciprocal square roots of the\r\n VRSQRT14PS ymm1 {k1}{z}, AVX512F packed single-precision floating-point values in\r\n ymm2/m256/m32bcst ymm2/m256/m32bcst and stores the results in ymm1.\r\n Under writemask.\r\n EVEX.512.66.0F38.W0 4E /r FV V/V AVX512F Computes the approximate reciprocal square roots of the\r\n VRSQRT14PS zmm1 {k1}{z}, packed single-precision floating-point values in\r\n zmm2/m512/m32bcst zmm2/m512/m32bcst and stores the results in zmm1. Under\r\n writemask.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nThis instruction performs a SIMD computation of the approximate reciprocals of the square roots of 16 packed\r\nsingle-precision floating-point values in the source operand (the second operand) and stores the packed single-\r\nprecision floating-point results in the destination operand (the first operand) according to the writemask. The\r\nmaximum relative error for this approximation is less than 2-14.\r\nEVEX.512 encoded version: The source operand can be a ZMM register, a 512-bit memory location or a 512-bit\r\nvector broadcasted from a 32-bit memory location. The destination operand is a ZMM register, conditionally\r\nupdated using writemask k1.\r\nEVEX.256 encoded version: The source operand is a YMM register, a 256-bit memory location, or a 256-bit vector\r\nbroadcasted from a 32-bit memory location. The destination operand is a YMM register, conditionally updated using\r\nwritemask k1.\r\nEVEX.128 encoded version: The source operand is a XMM register, a 128-bit memory location, or a 128-bit vector\r\nbroadcasted from a 32-bit memory location. The destination operand is a XMM register, conditionally updated using\r\nwritemask k1.\r\nThe VRSQRT14PS instruction is not affected by the rounding control bits in the MXCSR register. When a source\r\nvalue is a 0.0, an inf with the sign of the source value is returned. When the source operand is an +inf then +ZERO\r\nvalue is returned. A denormal source value is treated as zero only if DAZ bit is set in MXCSR. Otherwise it is treated\r\ncorrectly and performs the approximation with the specified masked response. When a source value is a negative\r\nvalue (other than 0.0) a floating-point QNaN_indefinite is returned. When a source value is an SNaN or QNaN, the\r\nSNaN is converted to a QNaN or the source QNaN is returned.\r\nMXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.\r\nNote: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\nA numerically exact implementation of VRSQRT14xx can be found at https://software.intel.com/en-us/arti-\r\ncles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVRSQRT14PS (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC *is memory*)\r\n THEN DEST[i+31:i] <- APPROXIMATE(1.0/ SQRT(SRC[31:0]));\r\n ELSE DEST[i+31:i] <- APPROXIMATE(1.0/ SQRT(SRC[i+31:i]));\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI;\r\n FI;\r\nENDFOR;\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n Table 5-25. VRSQRT14PS Special Cases\r\n Input value Result value Comments\r\n Any denormal Normal Cannot generate overflow\r\n -2n n\r\n X=2 2\r\n X<0 QNaN_Indefinite Including -INF\r\n X = -0 -INF\r\n X = +0 +INF\r\n X = +INF +0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVRSQRT14PS __m512 _mm512_rsqrt14_ps( __m512 a);\r\nVRSQRT14PS __m512 _mm512_mask_rsqrt14_ps(__m512 s, __mmask16 k, __m512 a);\r\nVRSQRT14PS __m512 _mm512_maskz_rsqrt14_ps( __mmask16 k, __m512 a);\r\nVRSQRT14PS __m256 _mm256_rsqrt14_ps( __m256 a);\r\nVRSQRT14PS __m256 _mm256_mask_rsqrt14_ps(__m256 s, __mmask8 k, __m256 a);\r\nVRSQRT14PS __m256 _mm256_maskz_rsqrt14_ps( __mmask8 k, __m256 a);\r\nVRSQRT14PS __m128 _mm_rsqrt14_ps( __m128 a);\r\nVRSQRT14PS __m128 _mm_mask_rsqrt14_ps(__m128 s, __mmask8 k, __m128 a);\r\nVRSQRT14PS __m128 _mm_maskz_rsqrt14_ps( __mmask8 k, __m128 a);\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VRSQRT14PS"
},
{
"description": "VRSQRT14SD-Compute Approximate Reciprocal of Square Root of Scalar Float64 Value\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.LIG.66.0F38.W1 4F /r T1S V/V AVX512F Computes the approximate reciprocal square root of the\r\n VRSQRT14SD xmm1 {k1}{z}, scalar double-precision floating-point value in xmm3/m64\r\n xmm2, xmm3/m64 and stores the result in the low quadword element of xmm1\r\n using writemask k1. Bits[127:64] of xmm2 is copied to\r\n xmm1[127:64].\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nComputes the approximate reciprocal of the square roots of the scalar double-precision floating-point value in the\r\nlow quadword element of the source operand (the second operand) and stores the result in the low quadword\r\nelement of the destination operand (the first operand) according to the writemask. The maximum relative error for\r\nthis approximation is less than 2-14. The source operand can be an XMM register or a 32-bit memory location. The\r\ndestination operand is an XMM register.\r\nBits (127:64) of the XMM register destination are copied from corresponding bits in the first source operand. Bits\r\n(MAX_VL-1:128) of the destination register are zeroed.\r\nThe VRSQRT14SD instruction is not affected by the rounding control bits in the MXCSR register. When a source\r\nvalue is a 0.0, an inf with the sign of the source value is returned. When the source operand is an +inf then +ZERO\r\nvalue is returned. A denormal source value is treated as zero only if DAZ bit is set in MXCSR. Otherwise it is treated\r\ncorrectly and performs the approximation with the specified masked response. When a source value is a negative\r\nvalue (other than 0.0) a floating-point QNaN_indefinite is returned. When a source value is an SNaN or QNaN, the\r\nSNaN is converted to a QNaN or the source QNaN is returned.\r\nMXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.\r\nA numerically exact implementation of VRSQRT14xx can be found at https://software.intel.com/en-us/arti-\r\ncles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.\r\n\r\nOperation\r\nVRSQRT14SD (EVEX version)\r\nIF k1[0] or *no writemask*\r\n THEN DEST[63:0] <- APPROXIMATE(1.0/ SQRT(SRC2[63:0]))\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[63:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\n Table 5-24. VRSQRT14SD Special Cases\r\n Input value Result value Comments\r\n Any denormal Normal Cannot generate overflow\r\n X= 2-2n 2 n\r\n\r\n X<0 QNaN_Indefinite Including -INF\r\n X = -0 -INF\r\n X = +0 +INF\r\n X = +INF +0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVRSQRT14SD __m128d _mm_rsqrt14_sd( __m128d a, __m128d b);\r\nVRSQRT14SD __m128d _mm_mask_rsqrt14_sd(__m128d s, __mmask8 k, __m128d a, __m128d b);\r\nVRSQRT14SD __m128d _mm_maskz_rsqrt14_sd( __mmask8d m, __m128d a, __m128d b);\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type E5.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VRSQRT14SD"
},
{
"description": "VRSQRT14SS-Compute Approximate Reciprocal of Square Root of Scalar Float32 Value\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.LIG.66.0F38.W0 4F /r T1S V/V AVX512F Computes the approximate reciprocal square root of the\r\n VRSQRT14SS xmm1 {k1}{z}, scalar single-precision floating-point value in xmm3/m32\r\n xmm2, xmm3/m32 and stores the result in the low doubleword element of\r\n xmm1 using writemask k1. Bits[127:32] of xmm2 is copied\r\n to xmm1[127:32].\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nComputes of the approximate reciprocal of the square root of the scalar single-precision floating-point value in the\r\nlow doubleword element of the source operand (the second operand) and stores the result in the low doubleword\r\nelement of the destination operand (the first operand) according to the writemask. The maximum relative error for\r\nthis approximation is less than 2-14. The source operand can be an XMM register or a 32-bit memory location. The\r\ndestination operand is an XMM register.\r\nBits (127:32) of the XMM register destination are copied from corresponding bits in the first source operand. Bits\r\n(MAX_VL-1:128) of the destination register are zeroed.\r\nThe VRSQRT14SS instruction is not affected by the rounding control bits in the MXCSR register. When a source\r\nvalue is a 0.0, an inf with the sign of the source value is returned. When the source operand is an inf, zero with the\r\nsign of the source value is returned. A denormal source value is treated as zero only if DAZ bit is set in MXCSR.\r\nOtherwise it is treated correctly and performs the approximation with the specified masked response. When a\r\nsource value is a negative value (other than 0.0) a floating-point indefinite is returned. When a source value is an\r\nSNaN or QNaN, the SNaN is converted to a QNaN or the source QNaN is returned.\r\nMXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.\r\nA numerically exact implementation of VRSQRT14xx can be found at https://software.intel.com/en-us/arti-\r\ncles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.\r\n\r\nOperation\r\nVRSQRT14SS (EVEX version)\r\nIF k1[0] or *no writemask*\r\n THEN DEST[31:0] <- APPROXIMATE(1.0/ SQRT(SRC2[31:0]))\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n THEN DEST[31:0] <- 0\r\n FI;\r\nFI;\r\nDEST[127:32] <- SRC1[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\n Table 5-26. VRSQRT14SS Special Cases\r\n Input value Result value Comments\r\n Any denormal Normal Cannot generate overflow\r\n X= 2-2n 2 n\r\n\r\n X<0 QNaN_Indefinite Including -INF\r\n X = -0 -INF\r\n X = +0 +INF\r\n X = +INF +0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVRSQRT14SS __m128 _mm_rsqrt14_ss( __m128 a, __m128 b);\r\nVRSQRT14SS __m128 _mm_mask_rsqrt14_ss(__m128 s, __mmask8 k, __m128 a, __m128 b);\r\nVRSQRT14SS __m128 _mm_maskz_rsqrt14_ss( __mmask8 k, __m128 a, __m128 b);\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type E5.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VRSQRT14SS"
},
{
"description": "VRSQRT28PD-Approximation to the Reciprocal Square Root of Packed Double-Precision\r\nFloating-Point Values with Less Than 2^-28 Relative Error\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.512.66.0F38.W1 CC /r FV V/V AVX512ER Computes approximations to the Reciprocal square root (<2^-\r\n VRSQRT28PD zmm1 {k1}{z}, 28 relative error) of the packed double-precision floating-point\r\n zmm2/m512/m64bcst {sae} values from zmm2/m512/m64bcst and stores result in\r\n zmm1with writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nComputes the reciprocal square root of the float64 values in the source operand (the second operand) and store\r\nthe results to the destination operand (the first operand). The approximate reciprocal is evaluated with less than\r\n2^-28 of maximum relative error.\r\nIf any source element is NaN, the quietized NaN source value is returned for that element. Negative (non-zero)\r\nsource numbers, as well as -inf, return the canonical NaN and set the Invalid Flag (#I).\r\nA value of -0 must return -inf and set the DivByZero flags (#Z). Negative numbers should return NaN and set the\r\nInvalid flag (#I). Note however that the instruction flush input denormals to zero of the same sign, so negative\r\ndenormals return -inf and set the DivByZero flag.\r\nThe source operand is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit\r\nmemory location. The destination operand is a ZMM register, conditionally updated using writemask k1.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\nA numerically exact implementation of VRSQRT28xx can be found at https://software.intel.com/en-us/arti-\r\ncles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.\r\n\r\nOperation\r\nVRSQRT28PD (EVEX encoded versions)\r\n(KL, VL) = (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC *is memory*)\r\n THEN DEST[i+63:i] <- (1.0/ SQRT(SRC[63:0]));\r\n ELSE DEST[i+63:i] <- (1.0/ SQRT(SRC[i+63:i]));\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI;\r\n FI;\r\nENDFOR;\r\n\r\n\r\n\r\n\r\n\r\n Table 5-27. VRSQRT28PD Special Cases\r\n Input value Result value Comments\r\n NAN QNAN(input) If (SRC = SNaN) then #I\r\n X= 2-2n 2n\r\n\r\n X<0 QNaN_Indefinite Including -INF\r\n X = -0 or negative denormal -INF #Z\r\n X = +0 or positive denormal +INF #Z\r\n X = +INF +0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n\r\nVRSQRT28PD __m512d _mm512_rsqrt28_round_pd(__m512d a, int sae);\r\nVRSQRT28PD __m512d _mm512_mask_rsqrt28_round_pd(__m512d s, __mmask8 m,__m512d a, int sae);\r\nVRSQRT28PD __m512d _mm512_maskz_rsqrt28_round_pd(__mmask8 m,__m512d a, int sae);\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nInvalid (if SNaN input), Divide-by-zero\r\n\r\nOther Exceptions\r\n\r\nSee Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VRSQRT28PD"
},
{
"description": "VRSQRT28PS-Approximation to the Reciprocal Square Root of Packed Single-Precision\r\nFloating-Point Values with Less Than 2^-28 Relative Error\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.512.66.0F38.W0 CC /r FV V/V AVX512ER Computes approximations to the Reciprocal square root\r\n VRSQRT28PS zmm1 {k1}{z}, (<2^-28 relative error) of the packed single-precision\r\n zmm2/m512/m32bcst {sae} floating-point values from zmm2/m512/m32bcst and stores\r\n result in zmm1with writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\nDescription\r\nComputes the reciprocal square root of the float32 values in the source operand (the second operand) and store\r\nthe results to the destination operand (the first operand). The approximate reciprocal is evaluated with less than\r\n2^-28 of maximum relative error prior to final rounding. The final results is rounded to < 2^-23 relative error\r\nbefore written to the destination.\r\nIf any source element is NaN, the quietized NaN source value is returned for that element. Negative (non-zero)\r\nsource numbers, as well as -inf, return the canonical NaN and set the Invalid Flag (#I).\r\nA value of -0 must return -inf and set the DivByZero flags (#Z). Negative numbers should return NaN and set the\r\nInvalid flag (#I). Note however that the instruction flush input denormals to zero of the same sign, so negative\r\ndenormals return -inf and set the DivByZero flag.\r\nThe source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit\r\nmemory location. The destination operand is a ZMM register, conditionally updated using writemask k1.\r\nEVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.\r\nA numerically exact implementation of VRSQRT28xx can be found at https://software.intel.com/en-us/arti-\r\ncles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.\r\n\r\nOperation\r\nVRSQRT28PS (EVEX encoded versions)\r\n(KL, VL) = (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC *is memory*)\r\n THEN DEST[i+31:i] <- (1.0/ SQRT(SRC[31:0]));\r\n ELSE DEST[i+31:i] <- (1.0/ SQRT(SRC[i+31:i]));\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI;\r\n FI;\r\nENDFOR;\r\n\r\n\r\n\r\n\r\n\r\n Table 5-29. VRSQRT28PS Special Cases\r\n Input value Result value Comments\r\n NAN QNAN(input) If (SRC = SNaN) then #I\r\n X= 2-2n 2 n\r\n\r\n X<0 QNaN_Indefinite Including -INF\r\n X = -0 or negative denormal -INF #Z\r\n X = +0 or positive denormal +INF #Z\r\n X = +INF +0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n\r\nVRSQRT28PS __m512 _mm512_rsqrt28_round_ps(__m512 a, int sae);\r\nVRSQRT28PS __m512 _mm512_mask_rsqrt28_round_ps(__m512 s, __mmask16 m,__m512 a, int sae);\r\nVRSQRT28PS __m512 _mm512_maskz_rsqrt28_round_ps(__mmask16 m,__m512 a, int sae);\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nInvalid (if SNaN input), Divide-by-zero\r\n\r\nOther Exceptions\r\n\r\nSee Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VRSQRT28PS"
},
{
"description": "VRSQRT28SD-Approximation to the Reciprocal Square Root of Scalar Double-Precision\r\nFloating-Point Value with Less Than 2^-28 Relative Error\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.LIG.66.0F38.W1 CD /r T1S V/V AVX512ER Computes approximate reciprocal square root (<2^-28\r\n VRSQRT28SD xmm1 {k1}{z}, relative error) of the scalar double-precision floating-point\r\n xmm2, xmm3/m64 {sae} value from xmm3/m64 and stores result in xmm1with\r\n writemask k1. Also, upper double-precision floating-point\r\n value (bits[127:64]) from xmm2 is copied to\r\n xmm1[127:64].\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nComputes the reciprocal square root of the low float64 value in the second source operand (the third operand) and\r\nstore the result to the destination operand (the first operand). The approximate reciprocal square root is evaluated\r\nwith less than 2^-28 of maximum relative error. The result is written into the low float64 element of xmm1\r\naccording to the writemask k1. Bits 127:64 of the destination is copied from the corresponding bits of the first source operand\r\n(the second operand).\r\nIf any source element is NaN, the quietized NaN source value is returned for that element. Negative (non-zero)\r\nsource numbers, as well as -inf, return the canonical NaN and set the Invalid Flag (#I).\r\nA value of -0 must return -inf and set the DivByZero flags (#Z). Negative numbers should return NaN and set the\r\nInvalid flag (#I). Note however that the instruction flush input denormals to zero of the same sign, so negative\r\ndenormals return -inf and set the DivByZero flag.\r\nThe first source operand is an XMM register. The second source operand is an XMM register or a 64-bit memory\r\nlocation. The destination operand is a XMM register.\r\nA numerically exact implementation of VRSQRT28xx can be found at https://software.intel.com/en-us/arti-\r\ncles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.\r\n\r\nOperation\r\nVRSQRT28SD (EVEX encoded versions)\r\n IF k1[0] OR *no writemask* THEN\r\n DEST[63: 0] <- (1.0/ SQRT(SRC[63: 0]));\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63: 0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[63: 0] <- 0\r\n FI;\r\n FI;\r\nENDFOR;\r\nDEST[127:64] <- SRC1[127: 64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\n Table 5-28. VRSQRT28SD Special Cases\r\n Input value Result value Comments\r\n NAN QNAN(input) If (SRC = SNaN) then #I\r\n X= 2-2n 2n\r\n\r\n X<0 QNaN_Indefinite Including -INF\r\n X = -0 or negative denormal -INF #Z\r\n X = +0 or positive denormal +INF #Z\r\n X = +INF +0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n\r\nVRSQRT28SD __m128d _mm_rsqrt28_round_sd(__m128d a, __m128b b, int sae);\r\nVRSQRT28SD __m128d _mm_mask_rsqrt28_round_pd(__m128d s, __mmask8 m,__m128d a, __m128d b, int sae);\r\nVRSQRT28SD __m128d _mm_maskz_rsqrt28_round_pd( __mmask8 m,__m128d a, __m128d b, int sae);\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nInvalid (if SNaN input), Divide-by-zero\r\n\r\nOther Exceptions\r\n\r\nSee Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VRSQRT28SD"
},
{
"description": "VRSQRT28SS-Approximation to the Reciprocal Square Root of Scalar Single-Precision Floating-\r\nPoint Value with Less Than 2^-28 Relative Error\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.LIG.66.0F38.W0 CD /r T1S V/V AVX512ER Computes approximate reciprocal square root (<2^-28\r\n VRSQRT28SS xmm1 {k1}{z}, relative error) of the scalar single-precision floating-point\r\n xmm2, xmm3/m32 {sae} value from xmm3/m32 and stores result in xmm1with\r\n writemask k1. Also, upper 3 single-precision floating-point\r\n value (bits[127:32]) from xmm2 is copied to\r\n xmm1[127:32].\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nComputes the reciprocal square root of the low float32 value in the second source operand (the third operand) and\r\nstore the result to the destination operand (the first operand). The approximate reciprocal square root is evaluated\r\nwith less than 2^-28 of maximum relative error prior to final rounding. The final result is rounded to < 2^-23 rela-\r\ntive error before written to the low float32 element of the destination according to the writemask k1. Bits 127:32 of\r\nthe destination is copied from the corresponding bits of the first source operand (the second operand).\r\nIf any source element is NaN, the quietized NaN source value is returned for that element. Negative (non-zero)\r\nsource numbers, as well as -inf, return the canonical NaN and set the Invalid Flag (#I).\r\nA value of -0 must return -inf and set the DivByZero flags (#Z). Negative numbers should return NaN and set the\r\nInvalid flag (#I). Note however that the instruction flush input denormals to zero of the same sign, so negative\r\ndenormals return -inf and set the DivByZero flag.\r\nThe first source operand is an XMM register. The second source operand is an XMM register or a 32-bit memory\r\nlocation. The destination operand is a XMM register.\r\nA numerically exact implementation of VRSQRT28xx can be found at https://software.intel.com/en-us/arti-\r\ncles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.\r\n\r\nOperation\r\nVRSQRT28SS (EVEX encoded versions)\r\n IF k1[0] OR *no writemask* THEN\r\n DEST[31: 0] <- (1.0/ SQRT(SRC[31: 0]));\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31: 0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[31: 0] <- 0\r\n FI;\r\n FI;\r\nENDFOR;\r\nDEST[127:32] <- SRC1[127: 32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\n\r\n\r\n\r\n\r\n Table 5-30. VRSQRT28SS Special Cases\r\n Input value Result value Comments\r\n NAN QNAN(input) If (SRC = SNaN) then #I\r\n X= 2-2n 2 n\r\n\r\n X<0 QNaN_Indefinite Including -INF\r\n X = -0 or negative denormal -INF #Z\r\n X = +0 or positive denormal +INF #Z\r\n X = +INF +0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n\r\nVRSQRT28SS __m128 _mm_rsqrt28_round_ss(__m128 a, __m128 b, int sae);\r\nVRSQRT28SS __m128 _mm512_mask_rsqrt28_round_ss(__m128 s, __mmask8 m,__m128 a,__m128 b, int sae);\r\nVRSQRT28SS __m128 _mm512_maskz_rsqrt28_round_ss(__mmask8 m,__m128 a,__m128 b, int sae);\r\n\r\nSIMD Floating-Point Exceptions\r\n\r\nInvalid (if SNaN input), Divide-by-zero\r\n\r\nOther Exceptions\r\n\r\nSee Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VRSQRT28SS"
},
{
"description": "VSCALEFPD-Scale Packed Float64 Values With Float64 Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.128.66.0F38.W1 2C /r FV V/V AVX512VL Scale the packed double-precision floating-point values in\r\n VSCALEFPD xmm1 {k1}{z}, xmm2, AVX512F xmm2 using values from xmm3/m128/m64bcst. Under\r\n xmm3/m128/m64bcst writemask k1.\r\n EVEX.NDS.256.66.0F38.W1 2C /r FV V/V AVX512VL Scale the packed double-precision floating-point values in\r\n VSCALEFPD ymm1 {k1}{z}, ymm2, AVX512F ymm2 using values from ymm3/m256/m64bcst. Under\r\n ymm3/m256/m64bcst writemask k1.\r\n EVEX.NDS.512.66.0F38.W1 2C /r FV V/V AVX512F Scale the packed double-precision floating-point values in\r\n VSCALEFPD zmm1 {k1}{z}, zmm2, zmm2 using values from zmm3/m512/m64bcst. Under\r\n zmm3/m512/m64bcst{er} writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a floating-point scale of the packed double-precision floating-point values in the first source operand by\r\nmultiplying it by 2 power of the double-precision floating-point values in second source operand.\r\nThe equation of this operation is given by:\r\nzmm1 := zmm2*2floor(zmm3).\r\nFloor(zmm3) means maximum integer value <= zmm3.\r\nIf the result cannot be represented in double precision, then the proper overflow response (for positive scaling\r\noperand), or the proper underflow response (for negative scaling operand) is issued. The overflow and underflow\r\nresponses are dependent on the rounding mode (for IEEE-compliant rounding), as well as on other settings in\r\nMXCSR (exception mask bits, FTZ bit), and on the SAE bit.\r\nThe first source operand is a ZMM/YMM/XMM register. The second source operand is a ZMM/YMM/XMM register, a\r\n512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The\r\ndestination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.\r\nHandling of special-case input values are listed in Table 5-31 and Table 5-32.\r\n\r\n\r\n Table 5-31. \\VSCALEFPD/SD/PS/SS Special Cases\r\n\r\n Src2 Set IE\r\n +-NaN +Inf -Inf 0/Denorm/Norm\r\n Src1 +-QNaN QNaN(Src1) +INF +0 QNaN(Src1) IF either source is SNAN\r\n +-SNaN QNaN(Src1) QNaN(Src1) QNaN(Src1) QNaN(Src1) YES\r\n +-Inf QNaN(Src2) Src1 QNaN_Indefinite Src1 IF Src2 is SNAN or -INF\r\n +-0 QNaN(Src2) QNaN_Indefinite Src1 Src1 IF Src2 is SNAN or +INF\r\n Denorm/Norm QNaN(Src2) +-INF (Src1 sign) +-0 (Src1 sign) Compute Result IF Src2 is SNAN\r\n\r\n\r\n\r\n\r\n\r\n Table 5-32. Additional VSCALEFPD/SD Special Cases\r\n Special Case Returned value Faults\r\n |result| < 2-1074 +-0 or +-Min-Denormal (Src1 sign) Underflow\r\n 1024\r\n |result| >= 2 +-INF (Src1 sign) or +-Max-normal (Src1 sign) Overflow\r\n\r\nOperation\r\nSCALE(SRC1, SRC2)\r\n{\r\nTMP_SRC2 <- SRC2\r\nTMP_SRC1 <- SRC1\r\nIF (SRC2 is denormal AND MXCSR.DAZ) THEN TMP_SRC2=0\r\nIF (SRC1 is denormal AND MXCSR.DAZ) THEN TMP_SRC1=0\r\n /* SRC2 is a 64 bits floating-point value */\r\n DEST[63:0] <- TMP_SRC1[63:0] * POW(2, Floor(TMP_SRC2[63:0]))\r\n}\r\nVSCALEFPD (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nIF (VL = 512) AND (EVEX.b = 1) AND (SRC2 *is register*)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN DEST[i+63:i] <- SCALE(SRC1[i+63:i], SRC2[63:0]);\r\n ELSE DEST[i+63:i] <- SCALE(SRC1[i+63:i], SRC2[i+63:i]);\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVSCALEFPD __m512d _mm512_scalef_round_pd(__m512d a, __m512d b, int);\r\nVSCALEFPD __m512d _mm512_mask_scalef_round_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int);\r\nVSCALEFPD __m512d _mm512_maskz_scalef_round_pd(__mmask8 k, __m512d a, __m512d b, int);\r\nVSCALEFPD __m256d _mm256_scalef_round_pd(__m256d a, __m256d b, int);\r\nVSCALEFPD __m256d _mm256_mask_scalef_round_pd(__m256d s, __mmask8 k, __m256d a, __m256d b, int);\r\nVSCALEFPD __m256d _mm256_maskz_scalef_round_pd(__mmask8 k, __m256d a, __m256d b, int);\r\nVSCALEFPD __m128d _mm_scalef_round_pd(__m128d a, __m128d b, int);\r\nVSCALEFPD __m128d _mm_mask_scalef_round_pd(__m128d s, __mmask8 k, __m128d a, __m128d b, int);\r\nVSCALEFPD __m128d _mm_maskz_scalef_round_pd(__mmask8 k, __m128d a, __m128d b, int);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal (for Src1).\r\nDenormal is not reported for Src2.\r\n\r\nOther Exceptions\r\nSee Exceptions Type E2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VSCALEFPD"
},
{
"description": "VSCALEFPS-Scale Packed Float32 Values With Float32 Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.128.66.0F38.W0 2C /r FV V/V AVX512VL Scale the packed single-precision floating-point values in\r\n VSCALEFPS xmm1 {k1}{z}, xmm2, AVX512F xmm2 using values from xmm3/m128/m32bcst. Under\r\n xmm3/m128/m32bcst writemask k1.\r\n EVEX.NDS.256.66.0F38.W0 2C /r FV V/V AVX512VL Scale the packed single-precision values in ymm2 using\r\n VSCALEFPS ymm1 {k1}{z}, ymm2, AVX512F floating point values from ymm3/m256/m32bcst. Under\r\n ymm3/m256/m32bcst writemask k1.\r\n EVEX.NDS.512.66.0F38.W0 2C /r FV V/V AVX512F Scale the packed single-precision floating-point values in\r\n VSCALEFPS zmm1 {k1}{z}, zmm2, zmm2 using floating-point values from\r\n zmm3/m512/m32bcst{er} zmm3/m512/m32bcst. Under writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a floating-point scale of the packed single-precision floating-point values in the first source operand by\r\nmultiplying it by 2 power of the float32 values in second source operand.\r\nThe equation of this operation is given by:\r\nzmm1 := zmm2*2floor(zmm3).\r\nFloor(zmm3) means maximum integer value <= zmm3.\r\n\r\n\r\nIf the result cannot be represented in single precision, then the proper overflow response (for positive scaling\r\noperand), or the proper underflow response (for negative scaling operand) is issued. The overflow and underflow\r\nresponses are dependent on the rounding mode (for IEEE-compliant rounding), as well as on other settings in\r\nMXCSR (exception mask bits, FTZ bit), and on the SAE bit.\r\nEVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM\r\nregister, a 512-bit memory location or a 512-bit vector broadcasted from a 32-bit memory location. The destination\r\noperand is a ZMM register conditionally updated with writemask k1.\r\nEVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM\r\nregister, a 256-bit memory location, or a 256-bit vector broadcasted from a 32-bit memory location. The destina-\r\ntion operand is a YMM register, conditionally updated using writemask k1.\r\nEVEX.128 encoded version: The first source operand is an XMM register. The second source operand is a XMM\r\nregister, a 128-bit memory location, or a 128-bit vector broadcasted from a 32-bit memory location. The destina-\r\ntion operand is a XMM register, conditionally updated using writemask k1.\r\nHandling of special-case input values are listed in Table 5-31 and Table 5-33.\r\n\r\n Table 5-33. Additional VSCALEFPS/SS Special Cases\r\n Special Case Returned value Faults\r\n -149\r\n |result| < 2 +-0 or +-Min-Denormal (Src1 sign) Underflow\r\n |result| >= 2128 +-INF (Src1 sign) or +-Max-normal (Src1 sign) Overflow\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nSCALE(SRC1, SRC2)\r\n{ ; Check for denormal operands\r\nTMP_SRC2 <- SRC2\r\nTMP_SRC1 <- SRC1\r\nIF (SRC2 is denormal AND MXCSR.DAZ) THEN TMP_SRC2=0\r\nIF (SRC1 is denormal AND MXCSR.DAZ) THEN TMP_SRC1=0\r\n /* SRC2 is a 32 bits floating-point value */\r\n DEST[31:0] <- TMP_SRC1[31:0] * POW(2, Floor(TMP_SRC2[31:0]))\r\n}\r\n\r\nVSCALEFPS (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nIF (VL = 512) AND (EVEX.b = 1) AND (SRC2 *is register*)\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN DEST[i+31:i] <- SCALE(SRC1[i+31:i], SRC2[31:0]);\r\n ELSE DEST[i+31:i] <- SCALE(SRC1[i+31:i], SRC2[i+31:i]);\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0;\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVSCALEFPS __m512 _mm512_scalef_round_ps(__m512 a, __m512 b, int);\r\nVSCALEFPS __m512 _mm512_mask_scalef_round_ps(__m512 s, __mmask16 k, __m512 a, __m512 b, int);\r\nVSCALEFPS __m512 _mm512_maskz_scalef_round_ps(__mmask16 k, __m512 a, __m512 b, int);\r\nVSCALEFPS __m256 _mm256_scalef_round_ps(__m256 a, __m256 b, int);\r\nVSCALEFPS __m256 _mm256_mask_scalef_round_ps(__m256 s, __mmask8 k, __m256 a, __m256 b, int);\r\nVSCALEFPS __m256 _mm256_maskz_scalef_round_ps(__mmask8 k, __m256 a, __m256 b, int);\r\nVSCALEFPS __m128 _mm_scalef_round_ps(__m128 a, __m128 b, int);\r\nVSCALEFPS __m128 _mm_mask_scalef_round_ps(__m128 s, __mmask8 k, __m128 a, __m128 b, int);\r\nVSCALEFPS __m128 _mm_maskz_scalef_round_ps(__mmask8 k, __m128 a, __m128 b, int);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal (for Src1).\r\nDenormal is not reported for Src2.\r\n\r\nOther Exceptions\r\nSee Exceptions Type E2.\r\n\r\n\r\n",
"mnem": "VSCALEFPS"
},
{
"description": "VSCALEFSD-Scale Scalar Float64 Values With Float64 Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.LIG.66.0F38.W1 2D /r T1S V/V AVX512F Scale the scalar double-precision floating-point values in\r\n VSCALEFSD xmm1 {k1}{z}, xmm2, xmm2 using the value from xmm3/m64. Under writemask\r\n xmm3/m64{er} k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a floating-point scale of the packed double-precision floating-point value in the first source operand by\r\nmultiplying it by 2 power of the double-precision floating-point value in second source operand.\r\nThe equation of this operation is given by:\r\nxmm1 := xmm2*2floor(xmm3).\r\nFloor(xmm3) means maximum integer value <= xmm3.\r\nIf the result cannot be represented in double precision, then the proper overflow response (for positive scaling\r\noperand), or the proper underflow response (for negative scaling operand) is issued. The overflow and underflow\r\nresponses are dependent on the rounding mode (for IEEE-compliant rounding), as well as on other settings in\r\nMXCSR (exception mask bits, FTZ bit), and on the SAE bit.\r\nEVEX encoded version: The first source operand is an XMM register. The second source operand is an XMM register\r\nor a memory location. The destination operand is an XMM register conditionally updated with writemask k1.\r\nHandling of special-case input values are listed in Table 5-31 and Table 5-32.\r\n\r\nOperation\r\nSCALE(SRC1, SRC2)\r\n{\r\n ; Check for denormal operands\r\nTMP_SRC2 <- SRC2\r\nTMP_SRC1 <- SRC1\r\nIF (SRC2 is denormal AND MXCSR.DAZ) THEN TMP_SRC2=0\r\nIF (SRC1 is denormal AND MXCSR.DAZ) THEN TMP_SRC1=0\r\n /* SRC2 is a 64 bits floating-point value */\r\n DEST[63:0] <- TMP_SRC1[63:0] * POW(2, Floor(TMP_SRC2[63:0]))\r\n}\r\n\r\n\r\n\r\n\r\n\r\nVSCALEFSD (EVEX encoded version)\r\nIF (EVEX.b= 1) and SRC2 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] OR *no writemask*\r\n THEN DEST[63:0] <- SCALE(SRC1[63:0], SRC2[63:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[63:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[63:0] <- 0\r\n FI\r\nFI;\r\nDEST[127:64] <- SRC1[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVSCALEFSD __m128d _mm_scalef_round_sd(__m128d a, __m128d b, int);\r\nVSCALEFSD __m128d _mm_mask_scalef_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int);\r\nVSCALEFSD __m128d _mm_maskz_scalef_round_sd(__mmask8 k, __m128d a, __m128d b, int);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal (for Src1).\r\nDenormal is not reported for Src2.\r\n\r\nOther Exceptions\r\nSee Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VSCALEFSD"
},
{
"description": "VSCALEFSS-Scale Scalar Float32 Value With Float32 Value\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.LIG.66.0F38.W0 2D /r T1S V/V AVX512F Scale the scalar single-precision floating-point value in\r\n VSCALEFSS xmm1 {k1}{z}, xmm2, xmm2 using floating-point value from xmm3/m32. Under\r\n xmm3/m32{er} writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a floating-point scale of the scalar single-precision floating-point value in the first source operand by\r\nmultiplying it by 2 power of the float32 value in second source operand.\r\nThe equation of this operation is given by:\r\nxmm1 := xmm2*2floor(xmm3).\r\nFloor(xmm3) means maximum integer value <= xmm3.\r\n\r\n\r\nIf the result cannot be represented in single precision, then the proper overflow response (for positive scaling\r\noperand), or the proper underflow response (for negative scaling operand) is issued. The overflow and underflow\r\nresponses are dependent on the rounding mode (for IEEE-compliant rounding), as well as on other settings in\r\nMXCSR (exception mask bits, FTZ bit), and on the SAE bit.\r\nEVEX encoded version: The first source operand is an XMM register. The second source operand is an XMM register\r\nor a memory location. The destination operand is an XMM register conditionally updated with writemask k1.\r\nHandling of special-case input values are listed in Table 5-31 and Table 5-33.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nSCALE(SRC1, SRC2)\r\n{\r\n ; Check for denormal operands\r\nTMP_SRC2 <- SRC2\r\nTMP_SRC1 <- SRC1\r\nIF (SRC2 is denormal AND MXCSR.DAZ) THEN TMP_SRC2=0\r\nIF (SRC1 is denormal AND MXCSR.DAZ) THEN TMP_SRC1=0\r\n /* SRC2 is a 32 bits floating-point value */\r\n DEST[31:0] <- TMP_SRC1[31:0] * POW(2, Floor(TMP_SRC2[31:0]))\r\n}\r\n\r\nVSCALEFSS (EVEX encoded version)\r\nIF (EVEX.b= 1) and SRC2 *is a register*\r\n THEN\r\n SET_RM(EVEX.RC);\r\n ELSE\r\n SET_RM(MXCSR.RM);\r\nFI;\r\nIF k1[0] OR *no writemask*\r\n THEN DEST[31:0] <- SCALE(SRC1[31:0], SRC2[31:0])\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[31:0] remains unchanged*\r\n ELSE ; zeroing-masking\r\n DEST[31:0] <- 0\r\n FI\r\nFI;\r\nDEST[127:32] <- SRC1[127:32]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVSCALEFSS __m128 _mm_scalef_round_ss(__m128 a, __m128 b, int);\r\nVSCALEFSS __m128 _mm_mask_scalef_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int);\r\nVSCALEFSS __m128 _mm_maskz_scalef_round_ss(__mmask8 k, __m128 a, __m128 b, int);\r\n\r\nSIMD Floating-Point Exceptions\r\nOverflow, Underflow, Invalid, Precision, Denormal (for Src1).\r\nDenormal is not reported for Src2.\r\n\r\nOther Exceptions\r\nSee Exceptions Type E3.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VSCALEFSS"
},
{
"description": "-R:VSCATTERDPS",
"mnem": "VSCATTERDPD"
},
{
"description": "VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD-Scatter Packed Single, Packed\r\nDouble with Signed Dword and Qword Indices\r\n Opcode/ Op/E 64/32 CPUID Description\r\n Instruction n bit Mode Feature\r\n Support Flag\r\n EVEX.128.66.0F38.W0 A2 /vsib T1S V/V AVX512VL Using signed dword indices, scatter single-precision\r\n VSCATTERDPS vm32x {k1}, xmm1 AVX512F floating-point values to memory using writemask k1.\r\n EVEX.256.66.0F38.W0 A2 /vsib T1S V/V AVX512VL Using signed dword indices, scatter single-precision\r\n VSCATTERDPS vm32y {k1}, ymm1 AVX512F floating-point values to memory using writemask k1.\r\n EVEX.512.66.0F38.W0 A2 /vsib T1S V/V AVX512F Using signed dword indices, scatter single-precision\r\n VSCATTERDPS vm32z {k1}, zmm1 floating-point values to memory using writemask k1.\r\n EVEX.128.66.0F38.W1 A2 /vsib T1S V/V AVX512VL Using signed dword indices, scatter double-precision\r\n VSCATTERDPD vm32x {k1}, xmm1 AVX512F floating-point values to memory using writemask k1.\r\n EVEX.256.66.0F38.W1 A2 /vsib T1S V/V AVX512VL Using signed dword indices, scatter double-precision\r\n VSCATTERDPD vm32x {k1}, ymm1 AVX512F floating-point values to memory using writemask k1.\r\n EVEX.512.66.0F38.W1 A2 /vsib T1S V/V AVX512F Using signed dword indices, scatter double-precision\r\n VSCATTERDPD vm32y {k1}, zmm1 floating-point values to memory using writemask k1.\r\n EVEX.128.66.0F38.W0 A3 /vsib T1S V/V AVX512VL Using signed qword indices, scatter single-precision\r\n VSCATTERQPS vm64x {k1}, xmm1 AVX512F floating-point values to memory using writemask k1.\r\n EVEX.256.66.0F38.W0 A3 /vsib T1S V/V AVX512VL Using signed qword indices, scatter single-precision\r\n VSCATTERQPS vm64y {k1}, xmm1 AVX512F floating-point values to memory using writemask k1.\r\n EVEX.512.66.0F38.W0 A3 /vsib T1S V/V AVX512F Using signed qword indices, scatter single-precision\r\n VSCATTERQPS vm64z {k1}, ymm1 floating-point values to memory using writemask k1.\r\n EVEX.128.66.0F38.W1 A3 /vsib T1S V/V AVX512VL Using signed qword indices, scatter double-precision\r\n VSCATTERQPD vm64x {k1}, xmm1 AVX512F floating-point values to memory using writemask k1.\r\n EVEX.256.66.0F38.W1 A3 /vsib T1S V/V AVX512VL Using signed qword indices, scatter double-precision\r\n VSCATTERQPD vm64y {k1}, ymm1 AVX512F floating-point values to memory using writemask k1.\r\n EVEX.512.66.0F38.W1 A3 /vsib T1S V/V AVX512F Using signed qword indices, scatter double-precision\r\n VSCATTERQPD vm64z {k1}, zmm1 floating-point values to memory using writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n BaseReg (R): VSIB:base,\r\n T1S ModRM:reg (r) NA NA\r\n VectorReg(R): VSIB:index\r\n\r\nDescription\r\nStores up to 16 elements (or 8 elements) in doubleword/quadword vector zmm1 to the memory locations pointed\r\nby base address BASE_ADDR and index vector VINDEX, with scale SCALE. The elements are specified via the VSIB\r\n(i.e., the index register is a vector register, holding packed indices). Elements will only be stored if their corre-\r\nsponding mask bit is one. The entire mask register will be set to zero by this instruction unless it triggers an excep-\r\ntion.\r\nThis instruction can be suspended by an exception if at least one element is already scattered (i.e., if the exception\r\nis triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination\r\nregister and the mask register (k1) are partially updated. If any traps or interrupts are pending from already scat-\r\ntered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction\r\nbreakpoint is not re-triggered when the instruction is continued.\r\nNote that:\r\n. Only writes to overlapping vector indices are guaranteed to be ordered with respect to each other (from LSB to\r\n MSB of the source registers). Note that this also include partially overlapping vector indices. Writes that are not\r\n overlapped may happen in any order. Memory ordering with other instructions follows the Intel-64 memory\r\n ordering model. Note that this does not account for non-overlapping indices that map into the same physical\r\n address locations.\r\n\r\n\r\n\r\n. If two or more destination indices completely overlap, the \"earlier\" write(s) may be skipped.\r\n. Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all\r\n elements closer to the LSB of the destination zmm will be completed (and non-faulting). Individual elements\r\n closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered\r\n in the conventional order.\r\n. Elements may be scattered in any order, but faults must be delivered in a right-to left order; thus, elements to\r\n the left of a faulting one may be gathered before the fault is delivered. A given implementation of this\r\n instruction is repeatable - given the same input values and architectural state, the same set of elements to the\r\n left of the faulting one will be gathered.\r\n. This instruction does not perform AC checks, and so will never deliver an AC fault.\r\n. Not valid with 16-bit effective addresses. Will deliver a #UD fault.\r\n. If this instruction overwrites itself and then takes a fault, only a subset of elements may be completed before\r\n the fault is delivered (as described above). If the fault handler completes and attempts to re-execute this\r\n instruction, the new instruction will be executed, and the scatter will not complete.\r\nNote that the presence of VSIB byte is enforced in this instruction. Hence, the instruction will #UD fault if\r\nModRM.rm is different than 100b.\r\nThis instruction has special disp8*N and alignment rules. N is considered to be the size of a single vector element.\r\nThe scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-bit\r\nmode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits\r\nare ignored.\r\nThe instruction will #UD fault if the k0 mask register is specified\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nBASE_ADDR stands for the memory operand base address (a GPR); may not exist\r\nVINDEX stands for the memory operand vector of indices (a ZMM register)\r\nSCALE stands for the memory operand scalar (1, 2, 4 or 8)\r\nDISP is the optional 1, 2 or 4 byte displacement\r\n\r\n\r\n\r\n\r\n\r\nVSCATTERDPS (EVEX encoded versions)\r\n(KL, VL)= (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN MEM[BASE_ADDR +SignExtend(VINDEX[i+31:i]) * SCALE + DISP] <-\r\n SRC[i+31:i]\r\n k1[j] <- 0\r\n FI;\r\nENDFOR\r\nk1[MAX_KL-1:KL] <- 0\r\n\r\nVSCATTERDPD (EVEX encoded versions)\r\n(KL, VL)= (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n k <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN MEM[BASE_ADDR +SignExtend(VINDEX[k+31:k]) * SCALE + DISP] <-\r\n SRC[i+63:i]\r\n k1[j] <- 0\r\n FI;\r\nENDFOR\r\nk1[MAX_KL-1:KL] <- 0\r\n\r\nVSCATTERQPS (EVEX encoded versions)\r\n(KL, VL)= (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n k <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN MEM[BASE_ADDR + (VINDEX[k+63:k]) * SCALE + DISP] <-\r\n SRC[i+31:i]\r\n k1[j] <- 0\r\n FI;\r\nENDFOR\r\nk1[MAX_KL-1:KL] <- 0\r\n\r\nVSCATTERQPD (EVEX encoded versions)\r\n(KL, VL)= (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN MEM[BASE_ADDR + (VINDEX[i+63:i]) * SCALE + DISP] <-\r\n SRC[i+63:i]\r\n k1[j] <- 0\r\n FI;\r\nENDFOR\r\nk1[MAX_KL-1:KL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVSCATTERDPD void _mm512_i32scatter_pd(void * base, __m256i vdx, __m512d a, int scale);\r\nVSCATTERDPD void _mm512_mask_i32scatter_pd(void * base, __mmask8 k, __m256i vdx, __m512d a, int scale);\r\nVSCATTERDPS void _mm512_i32scatter_ps(void * base, __m512i vdx, __m512 a, int scale);\r\nVSCATTERDPS void _mm512_mask_i32scatter_ps(void * base, __mmask16 k, __m512i vdx, __m512 a, int scale);\r\nVSCATTERQPD void _mm512_i64scatter_pd(void * base, __m512i vdx, __m512d a, int scale);\r\nVSCATTERQPD void _mm512_mask_i64scatter_pd(void * base, __mmask8 k, __m512i vdx, __m512d a, int scale);\r\nVSCATTERQPS void _mm512_i64scatter_ps(void * base, __m512i vdx, __m256 a, int scale);\r\nVSCATTERQPS void _mm512_mask_i64scatter_ps(void * base, __mmask8 k, __m512i vdx, __m256 a, int scale);\r\nVSCATTERDPD void _mm256_i32scatter_pd(void * base, __m128i vdx, __m256d a, int scale);\r\nVSCATTERDPD void _mm256_mask_i32scatter_pd(void * base, __mmask8 k, __m128i vdx, __m256d a, int scale);\r\nVSCATTERDPS void _mm256_i32scatter_ps(void * base, __m256i vdx, __m256 a, int scale);\r\nVSCATTERDPS void _mm256_mask_i32scatter_ps(void * base, __mmask8 k, __m256i vdx, __m256 a, int scale);\r\nVSCATTERQPD void _mm256_i64scatter_pd(void * base, __m256i vdx, __m256d a, int scale);\r\nVSCATTERQPD void _mm256_mask_i64scatter_pd(void * base, __mmask8 k, __m256i vdx, __m256d a, int scale);\r\nVSCATTERQPS void _mm256_i64scatter_ps(void * base, __m256i vdx, __m128 a, int scale);\r\nVSCATTERQPS void _mm256_mask_i64scatter_ps(void * base, __mmask8 k, __m256i vdx, __m128 a, int scale);\r\nVSCATTERDPD void _mm_i32scatter_pd(void * base, __m128i vdx, __m128d a, int scale);\r\nVSCATTERDPD void _mm_mask_i32scatter_pd(void * base, __mmask8 k, __m128i vdx, __m128d a, int scale);\r\nVSCATTERDPS void _mm_i32scatter_ps(void * base, __m128i vdx, __m128 a, int scale);\r\nVSCATTERDPS void _mm_mask_i32scatter_ps(void * base, __mmask8 k, __m128i vdx, __m128 a, int scale);\r\nVSCATTERQPD void _mm_i64scatter_pd(void * base, __m128i vdx, __m128d a, int scale);\r\nVSCATTERQPD void _mm_mask_i64scatter_pd(void * base, __mmask8 k, __m128i vdx, __m128d a, int scale);\r\nVSCATTERQPS void _mm_i64scatter_ps(void * base, __m128i vdx, __m128 a, int scale);\r\nVSCATTERQPS void _mm_mask_i64scatter_ps(void * base, __mmask8 k, __m128i vdx, __m128 a, int scale);\r\n\r\nSIMD Floating-Point Exceptions\r\nInvalid, Overflow, Underflow, Precision, Denormal\r\n\r\nOther Exceptions\r\nSee Exceptions Type E12.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VSCATTERDPS"
},
{
"description": "-R:VSCATTERPF0DPS",
"mnem": "VSCATTERPF0DPD"
},
{
"description": "VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0QPD-Sparse Prefetch\r\nPacked SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint with Intent\r\nto Write\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.512.66.0F38.W0 C6 /5 /vsib T1S V/V AVX512PF Using signed dword indices, prefetch sparse byte\r\n VSCATTERPF0DPS vm32z {k1} memory locations containing single-precision data using\r\n writemask k1 and T0 hint with intent to write.\r\n EVEX.512.66.0F38.W0 C7 /5 /vsib T1S V/V AVX512PF Using signed qword indices, prefetch sparse byte\r\n VSCATTERPF0QPS vm64z {k1} memory locations containing single-precision data using\r\n writemask k1 and T0 hint with intent to write.\r\n EVEX.512.66.0F38.W1 C6 /5 /vsib T1S V/V AVX512PF Using signed dword indices, prefetch sparse byte\r\n VSCATTERPF0DPD vm32y {k1} memory locations containing double-precision data\r\n using writemask k1 and T0 hint with intent to write.\r\n EVEX.512.66.0F38.W1 C7 /5 /vsib T1S V/V AVX512PF Using signed qword indices, prefetch sparse byte\r\n VSCATTERPF0QPD vm64z {k1} memory locations containing double-precision data\r\n using writemask k1 and T0 hint with intent to write.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S BaseReg (R): VSIB:base, NA NA NA\r\n VectorReg(R): VSIB:index\r\n\r\nDescription\r\nThe instruction conditionally prefetches up to sixteen 32-bit or eight 64-bit integer byte data elements. The\r\nelements are specified via the VSIB (i.e., the index register is an zmm, holding packed indices). Elements will only\r\nbe prefetched if their corresponding mask bit is one.\r\ncache lines will be brought into exclusive state (RFO) specified by a locality hint (T0):\r\n. T0 (temporal data)-prefetch data into the first level cache.\r\n[PS data] For dword indices, the instruction will prefetch sixteen memory locations. For qword indices, the instruc-\r\ntion will prefetch eight values.\r\n[PD data] For dword and qword indices, the instruction will prefetch eight memory locations.\r\nNote that:\r\n(1) The prefetches may happen in any order (or not at all). The instruction is a hint.\r\n(2) The mask is left unchanged.\r\n(3) Not valid with 16-bit effective addresses. Will deliver a #UD fault.\r\n(4) No FP nor memory faults may be produced by this instruction.\r\n(5) Prefetches do not handle cache line splits\r\n(6) A #UD is signaled if the memory operand is encoded without the SIB byte.\r\n\r\nOperation\r\nBASE_ADDR stands for the memory operand base address (a GPR); may not exist\r\nVINDEX stands for the memory operand vector of indices (a vector register)\r\nSCALE stands for the memory operand scalar (1, 2, 4 or 8)\r\nDISP is the optional 1, 2 or 4 byte displacement\r\nPREFETCH(mem, Level, State) Prefetches a byte memory location pointed by 'mem' into the cache level specified by 'Level'; a request\r\nfor exclusive/ownership is done if 'State' is 1. Note that the memory location ignore cache line splits. This operation is considered a\r\nhint for the processor and may be skipped depending on implementation.\r\n\r\n\r\n\r\nVSCATTERPF0DPS (EVEX encoded version)\r\n(KL, VL) = (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j]\r\n Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+31:i]) * SCALE + DISP], Level=0, RFO = 1)\r\n FI;\r\nENDFOR\r\n\r\nVSCATTERPF0DPD (EVEX encoded version)\r\n(KL, VL) = (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n k <- j * 32\r\n IF k1[j]\r\n Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+31:k]) * SCALE + DISP], Level=0, RFO = 1)\r\n FI;\r\nENDFOR\r\n\r\nVSCATTERPF0QPS (EVEX encoded version)\r\n(KL, VL) = (8, 256)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j]\r\n Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+63:i]) * SCALE + DISP], Level=0, RFO = 1)\r\n FI;\r\nENDFOR\r\n\r\nVSCATTERPF0QPD (EVEX encoded version)\r\n(KL, VL) = (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n k <- j * 64\r\n IF k1[j]\r\n Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+63:k]) * SCALE + DISP], Level=0, RFO = 1)\r\n FI;\r\nENDFOR\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVSCATTERPF0DPD void _mm512_prefetch_i32scatter_pd(void *base, __m256i vdx, int scale, int hint);\r\nVSCATTERPF0DPD void _mm512_mask_prefetch_i32scatter_pd(void *base, __mmask8 m, __m256i vdx, int scale, int hint);\r\nVSCATTERPF0DPS void _mm512_prefetch_i32scatter_ps(void *base, __m512i vdx, int scale, int hint);\r\nVSCATTERPF0DPS void _mm512_mask_prefetch_i32scatter_ps(void *base, __mmask16 m, __m512i vdx, int scale, int hint);\r\nVSCATTERPF0QPD void _mm512_prefetch_i64scatter_pd(void * base, __m512i vdx, int scale, int hint);\r\nVSCATTERPF0QPD void _mm512_mask_prefetch_i64scatter_pd(void * base, __mmask8 m, __m512i vdx, int scale, int hint);\r\nVSCATTERPF0QPS void _mm512_prefetch_i64scatter_ps(void * base, __m512i vdx, int scale, int hint);\r\nVSCATTERPF0QPS void _mm512_mask_prefetch_i64scatter_ps(void * base, __mmask8 m, __m512i vdx, int scale, int hint);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type E12NP.\r\n\r\n\r\n\r\n",
"mnem": "VSCATTERPF0DPS"
},
{
"description": "-R:VSCATTERPF0DPS",
"mnem": "VSCATTERPF0QPD"
},
{
"description": "-R:VSCATTERPF0DPS",
"mnem": "VSCATTERPF0QPS"
},
{
"description": "-R:VSCATTERPF1DPS",
"mnem": "VSCATTERPF1DPD"
},
{
"description": "VSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERPF1DPD/VSCATTERPF1QPD-Sparse Prefetch\r\nPacked SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint with Intent\r\nto Write\r\n Opcode/ Op/ 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.512.66.0F38.W0 C6 /6 /vsib T1S V/V AVX512PF Using signed dword indices, prefetch sparse byte memory\r\n VSCATTERPF1DPS vm32z {k1} locations containing single-precision data using writemask\r\n k1 and T1 hint with intent to write.\r\n EVEX.512.66.0F38.W0 C7 /6 /vsib T1S V/V AVX512PF Using signed qword indices, prefetch sparse byte memory\r\n VSCATTERPF1QPS vm64z {k1} locations containing single-precision data using writemask\r\n k1 and T1 hint with intent to write.\r\n EVEX.512.66.0F38.W1 C6 /6 /vsib T1S V/V AVX512PF Using signed dword indices, prefetch sparse byte memory\r\n VSCATTERPF1DPD vm32y {k1} locations containing double-precision data using\r\n writemask k1 and T1 hint with intent to write.\r\n EVEX.512.66.0F38.W1 C7 /6 /vsib T1S V/V AVX512PF Using signed qword indices, prefetch sparse byte memory\r\n VSCATTERPF1QPD vm64z {k1} locations containing double-precision data using\r\n writemask k1 and T1 hint with intent to write.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n T1S BaseReg (R): VSIB:base, NA NA NA\r\n VectorReg(R): VSIB:index\r\n\r\nDescription\r\nThe instruction conditionally prefetches up to sixteen 32-bit or eight 64-bit integer byte data elements. The\r\nelements are specified via the VSIB (i.e., the index register is an zmm, holding packed indices). Elements will only\r\nbe prefetched if their corresponding mask bit is one.\r\ncache lines will be brought into exclusive state (RFO) specified by a locality hint (T1):\r\n. T1 (temporal data)-prefetch data into the second level cache.\r\n[PS data] For dword indices, the instruction will prefetch sixteen memory locations. For qword indices, the instruc-\r\ntion will prefetch eight values.\r\n[PD data] For dword and qword indices, the instruction will prefetch eight memory locations.\r\nNote that:\r\n(1) The prefetches may happen in any order (or not at all). The instruction is a hint.\r\n(2) The mask is left unchanged.\r\n(3) Not valid with 16-bit effective addresses. Will deliver a #UD fault.\r\n(4) No FP nor memory faults may be produced by this instruction.\r\n(5) Prefetches do not handle cache line splits\r\n(6) A #UD is signaled if the memory operand is encoded without the SIB byte.\r\n\r\nOperation\r\nBASE_ADDR stands for the memory operand base address (a GPR); may not exist\r\nVINDEX stands for the memory operand vector of indices (a vector register)\r\nSCALE stands for the memory operand scalar (1, 2, 4 or 8)\r\nDISP is the optional 1, 2 or 4 byte displacement\r\nPREFETCH(mem, Level, State) Prefetches a byte memory location pointed by 'mem' into the cache level specified by 'Level'; a request\r\nfor exclusive/ownership is done if 'State' is 1. Note that the memory location ignore cache line splits. This operation is considered a\r\nhint for the processor and may be skipped depending on implementation.\r\n\r\n\r\n\r\nVSCATTERPF1DPS (EVEX encoded version)\r\n(KL, VL) = (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j]\r\n Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+31:i]) * SCALE + DISP], Level=1, RFO = 1)\r\n FI;\r\nENDFOR\r\n\r\nVSCATTERPF1DPD (EVEX encoded version)\r\n(KL, VL) = (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n k <- j * 32\r\n IF k1[j]\r\n Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+31:k]) * SCALE + DISP], Level=1, RFO = 1)\r\n FI;\r\nENDFOR\r\n\r\nVSCATTERPF1QPS (EVEX encoded version)\r\n(KL, VL) = (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j]\r\n Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+63:i]) * SCALE + DISP], Level=1, RFO = 1)\r\n FI;\r\nENDFOR\r\n\r\nVSCATTERPF1QPD (EVEX encoded version)\r\n(KL, VL) = (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n k <- j * 64\r\n IF k1[j]\r\n Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+63:k]) * SCALE + DISP], Level=1, RFO = 1)\r\n FI;\r\nENDFOR\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVSCATTERPF1DPD void _mm512_prefetch_i32scatter_pd(void *base, __m256i vdx, int scale, int hint);\r\nVSCATTERPF1DPD void _mm512_mask_prefetch_i32scatter_pd(void *base, __mmask8 m, __m256i vdx, int scale, int hint);\r\nVSCATTERPF1DPS void _mm512_prefetch_i32scatter_ps(void *base, __m512i vdx, int scale, int hint);\r\nVSCATTERPF1DPS void _mm512_mask_prefetch_i32scatter_ps(void *base, __mmask16 m, __m512i vdx, int scale, int hint);\r\nVSCATTERPF1QPD void _mm512_prefetch_i64scatter_pd(void * base, __m512i vdx, int scale, int hint);\r\nVSCATTERPF1QPD void _mm512_mask_prefetch_i64scatter_pd(void * base, __mmask8 m, __m512i vdx, int scale, int hint);\r\nVSCATTERPF1QPS void _mm512_prefetch_i64scatter_ps(void *base, __m512i vdx, int scale, int hint);\r\nVSCATTERPF1QPS void _mm512_mask_prefetch_i64scatter_ps(void *base, __mmask8 m, __m512i vdx, int scale, int hint);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type E12NP.\r\n\r\n\r\n\r\n",
"mnem": "VSCATTERPF1DPS"
},
{
"description": "-R:VSCATTERPF1DPS",
"mnem": "VSCATTERPF1QPD"
},
{
"description": "-R:VSCATTERPF1DPS",
"mnem": "VSCATTERPF1QPS"
},
{
"description": "-R:VSCATTERDPS",
"mnem": "VSCATTERQPD"
},
{
"description": "-R:VSCATTERDPS",
"mnem": "VSCATTERQPS"
},
{
"description": "VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2-Shuffle Packed Values at 128-bit\r\nGranularity\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n EVEX.NDS.256.66.0F3A.W0 23 /r ib FV V/V AVX512VL Shuffle 128-bit packed single-precision floating-point\r\n VSHUFF32X4 ymm1{k1}{z}, ymm2, AVX512F values selected by imm8 from ymm2 and\r\n ymm3/m256/m32bcst, imm8 ymm3/m256/m32bcst and place results in ymm1\r\n subject to writemask k1.\r\n EVEX.NDS.512.66.0F3A.W0 23 /r ib FV V/V AVX512F Shuffle 128-bit packed single-precision floating-point\r\n VSHUFF32x4 zmm1{k1}{z}, zmm2, values selected by imm8 from zmm2 and\r\n zmm3/m512/m32bcst, imm8 zmm3/m512/m32bcst and place results in zmm1\r\n subject to writemask k1.\r\n EVEX.NDS.256.66.0F3A.W1 23 /r ib FV V/V AVX512VL Shuffle 128-bit packed double-precision floating-point\r\n VSHUFF64X2 ymm1{k1}{z}, ymm2, AVX512F values selected by imm8 from ymm2 and\r\n ymm3/m256/m64bcst, imm8 ymm3/m256/m64bcst and place results in ymm1\r\n subject to writemask k1.\r\n EVEX.NDS.512.66.0F3A.W1 23 /r ib FV V/V AVX512F Shuffle 128-bit packed double-precision floating-point\r\n VSHUFF64x2 zmm1{k1}{z}, zmm2, values selected by imm8 from zmm2 and\r\n zmm3/m512/m64bcst, imm8 zmm3/m512/m64bcst and place results in zmm1\r\n subject to writemask k1.\r\n EVEX.NDS.256.66.0F3A.W0 43 /r ib FV V/V AVX512VL Shuffle 128-bit packed double-word values selected by\r\n VSHUFI32X4 ymm1{k1}{z}, ymm2, AVX512F imm8 from ymm2 and ymm3/m256/m32bcst and place\r\n ymm3/m256/m32bcst, imm8 results in ymm1 subject to writemask k1.\r\n EVEX.NDS.512.66.0F3A.W0 43 /r ib FV V/V AVX512F Shuffle 128-bit packed double-word values selected by\r\n VSHUFI32x4 zmm1{k1}{z}, zmm2, imm8 from zmm2 and zmm3/m512/m32bcst and place\r\n zmm3/m512/m32bcst, imm8 results in zmm1 subject to writemask k1.\r\n EVEX.NDS.256.66.0F3A.W1 43 /r ib FV V/V AVX512VL Shuffle 128-bit packed quad-word values selected by\r\n VSHUFI64X2 ymm1{k1}{z}, ymm2, AVX512F imm8 from ymm2 and ymm3/m256/m64bcst and place\r\n ymm3/m256/m64bcst, imm8 results in ymm1 subject to writemask k1.\r\n EVEX.NDS.512.66.0F3A.W1 43 /r ib FV V/V AVX512F Shuffle 128-bit packed quad-word values selected by\r\n VSHUFI64x2 zmm1{k1}{z}, zmm2, imm8 from zmm2 and zmm3/m512/m64bcst and place\r\n zmm3/m512/m64bcst, imm8 results in zmm1 subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\n256-bit Version: Moves one of the two 128-bit packed single-precision floating-point values from the first source\r\noperand (second operand) into the low 128-bit of the destination operand (first operand); moves one of the two\r\npacked 128-bit floating-point values from the second source operand (third operand) into the high 128-bit of the\r\ndestination operand. The selector operand (third operand) determines which values are moved to the destination\r\noperand.\r\n512-bit Version: Moves two of the four 128-bit packed single-precision floating-point values from the first source\r\noperand (second operand) into the low 256-bit of each double qword of the destination operand (first operand);\r\nmoves two of the four packed 128-bit floating-point values from the second source operand (third operand) into\r\nthe high 256-bit of the destination operand. The selector operand (third operand) determines which values are\r\nmoved to the destination operand.\r\nThe first source operand is a vector register. The second source operand can be a ZMM register, a 512-bit memory\r\nlocation or a 512-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a vector\r\nregister.\r\nThe writemask updates the destination operand with the granularity of 32/64-bit data elements.\r\n\r\n\r\n\r\nOperation\r\nSelect2(SRC, control) {\r\nCASE (control[0]) OF\r\n 0: TMP <- SRC[127:0];\r\n 1: TMP <- SRC[255:128];\r\nESAC;\r\nRETURN TMP\r\n}\r\n\r\nSelect4(SRC, control) {\r\nCASE (control[1:0]) OF\r\n 0: TMP <- SRC[127:0];\r\n 1: TMP <- SRC[255:128];\r\n 2: TMP <- SRC[383:256];\r\n 3: TMP <- SRC[511:384];\r\nESAC;\r\nRETURN TMP\r\n}\r\n\r\nVSHUFF32x4 (EVEX versions)\r\n(KL, VL) = (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN TMP_SRC2[i+31:i] <- SRC2[31:0]\r\n ELSE TMP_SRC2[i+31:i] <- SRC2[i+31:i]\r\n FI;\r\nENDFOR;\r\nIF VL = 256\r\n TMP_DEST[127:0] <- Select2(SRC1[255:0], imm8[0]);\r\n TMP_DEST[255:128] <- Select2(SRC2[255:0], imm8[1]);\r\nFI;\r\nIF VL = 512\r\n TMP_DEST[127:0] <- Select4(SRC1[511:0], imm8[1:0]);\r\n TMP_DEST[255:128] <- Select4(SRC1[511:0], imm8[3:2]);\r\n TMP_DEST[383:256] <- Select4(TMP_SRC2[511:0], imm8[5:4]);\r\n TMP_DEST[511:384] <- Select4(TMP_SRC2[511:0], imm8[7:6]);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_DEST[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n THEN DEST[i+31:i] <- 0\r\n FI;\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nVSHUFF64x2 (EVEX 512-bit version)\r\n(KL, VL) = (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN TMP_SRC2[i+63:i] <- SRC2[63:0]\r\n ELSE TMP_SRC2[i+63:i] <- SRC2[i+63:i]\r\n FI;\r\nENDFOR;\r\nIF VL = 256\r\n TMP_DEST[127:0] <- Select2(SRC1[255:0], imm8[0]);\r\n TMP_DEST[255:128] <- Select2(SRC2[255:0], imm8[1]);\r\nFI;\r\nIF VL = 512\r\n TMP_DEST[127:0] <- Select4(SRC1[511:0], imm8[1:0]);\r\n TMP_DEST[255:128] <- Select4(SRC1[511:0], imm8[3:2]);\r\n TMP_DEST[383:256] <- Select4(TMP_SRC2[511:0], imm8[5:4]);\r\n TMP_DEST[511:384] <- Select4(TMP_SRC2[511:0], imm8[7:6]);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n THEN DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVSHUFI32x4 (EVEX 512-bit version)\r\n(KL, VL) = (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN TMP_SRC2[i+31:i] <- SRC2[31:0]\r\n ELSE TMP_SRC2[i+31:i] <- SRC2[i+31:i]\r\n FI;\r\nENDFOR;\r\nIF VL = 256\r\n TMP_DEST[127:0] <- Select2(SRC1[255:0], imm8[0]);\r\n TMP_DEST[255:128] <- Select2(SRC2[255:0], imm8[1]);\r\nFI;\r\nIF VL = 512\r\n TMP_DEST[127:0] <- Select4(SRC1[511:0], imm8[1:0]);\r\n TMP_DEST[255:128] <- Select4(SRC1[511:0], imm8[3:2]);\r\n TMP_DEST[383:256] <- Select4(TMP_SRC2[511:0], imm8[5:4]);\r\n TMP_DEST[511:384] <- Select4(TMP_SRC2[511:0], imm8[7:6]);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n\r\n\r\n\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+31:i] <- TMP_DEST[i+31:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n THEN DEST[i+31:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVSHUFI64x2 (EVEX 512-bit version)\r\n(KL, VL) = (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF (EVEX.b = 1) AND (SRC2 *is memory*)\r\n THEN TMP_SRC2[i+63:i] <- SRC2[63:0]\r\n ELSE TMP_SRC2[i+63:i] <- SRC2[i+63:i]\r\n FI;\r\nENDFOR;\r\nIF VL = 256\r\n TMP_DEST[127:0] <- Select2(SRC1[255:0], imm8[0]);\r\n TMP_DEST[255:128] <- Select2(SRC2[255:0], imm8[1]);\r\nFI;\r\nIF VL = 512\r\n TMP_DEST[127:0] <- Select4(SRC1[511:0], imm8[1:0]);\r\n TMP_DEST[255:128] <- Select4(SRC1[511:0], imm8[3:2]);\r\n TMP_DEST[383:256] <- Select4(TMP_SRC2[511:0], imm8[5:4]);\r\n TMP_DEST[511:384] <- Select4(TMP_SRC2[511:0], imm8[7:6]);\r\nFI;\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask*\r\n THEN DEST[i+63:i] <- TMP_DEST[i+63:i]\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n THEN DEST[i+63:i] <- 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVSHUFI32x4 __m512i _mm512_shuffle_i32x4(__m512i a, __m512i b, int imm);\r\nVSHUFI32x4 __m512i _mm512_mask_shuffle_i32x4(__m512i s, __mmask16 k, __m512i a, __m512i b, int imm);\r\nVSHUFI32x4 __m512i _mm512_maskz_shuffle_i32x4( __mmask16 k, __m512i a, __m512i b, int imm);\r\nVSHUFI32x4 __m256i _mm256_shuffle_i32x4(__m256i a, __m256i b, int imm);\r\nVSHUFI32x4 __m256i _mm256_mask_shuffle_i32x4(__m256i s, __mmask8 k, __m256i a, __m256i b, int imm);\r\nVSHUFI32x4 __m256i _mm256_maskz_shuffle_i32x4( __mmask8 k, __m256i a, __m256i b, int imm);\r\nVSHUFF32x4 __m512 _mm512_shuffle_f32x4(__m512 a, __m512 b, int imm);\r\nVSHUFF32x4 __m512 _mm512_mask_shuffle_f32x4(__m512 s, __mmask16 k, __m512 a, __m512 b, int imm);\r\nVSHUFF32x4 __m512 _mm512_maskz_shuffle_f32x4( __mmask16 k, __m512 a, __m512 b, int imm);\r\nVSHUFI64x2 __m512i _mm512_shuffle_i64x2(__m512i a, __m512i b, int imm);\r\nVSHUFI64x2 __m512i _mm512_mask_shuffle_i64x2(__m512i s, __mmask8 k, __m512i b, __m512i b, int imm);\r\nVSHUFI64x2 __m512i _mm512_maskz_shuffle_i64x2( __mmask8 k, __m512i a, __m512i b, int imm);\r\nVSHUFF64x2 __m512d _mm512_shuffle_f64x2(__m512d a, __m512d b, int imm);\r\nVSHUFF64x2 __m512d _mm512_mask_shuffle_f64x2(__m512d s, __mmask8 k, __m512d a, __m512d b, int imm);\r\nVSHUFF64x2 __m512d _mm512_maskz_shuffle_f64x2( __mmask8 k, __m512d a, __m512d b, int imm);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nSee Exceptions Type E4NF.\r\n#UD If EVEX.L'L = 0 for VSHUFF32x4/VSHUFF64x2.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VSHUFF32x4"
},
{
"description": "-R:VSHUFF32x4",
"mnem": "VSHUFF64x2"
},
{
"description": "-R:VSHUFF32x4",
"mnem": "VSHUFI32x4"
},
{
"description": "-R:VSHUFF32x4",
"mnem": "VSHUFI64x2"
},
{
"description": "VTESTPD/VTESTPS-Packed Bit Test\r\n Opcode/ Op/ 64/32 bit CPUID Description\r\n Instruction En Mode Feature\r\n Support Flag\r\n VEX.128.66.0F38.W0 0E /r RM V/V AVX Set ZF and CF depending on sign bit AND and\r\n VTESTPS xmm1, xmm2/m128 ANDN of packed single-precision floating-point\r\n sources.\r\n VEX.256.66.0F38.W0 0E /r RM V/V AVX Set ZF and CF depending on sign bit AND and\r\n VTESTPS ymm1, ymm2/m256 ANDN of packed single-precision floating-point\r\n sources.\r\n VEX.128.66.0F38.W0 0F /r RM V/V AVX Set ZF and CF depending on sign bit AND and\r\n VTESTPD xmm1, xmm2/m128 ANDN of packed double-precision floating-point\r\n sources.\r\n VEX.256.66.0F38.W0 0F /r RM V/V AVX Set ZF and CF depending on sign bit AND and\r\n VTESTPD ymm1, ymm2/m256 ANDN of packed double-precision floating-point\r\n sources.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r) ModRM:r/m (r) NA NA\r\n\r\n\r\nDescription\r\nVTESTPS performs a bitwise comparison of all the sign bits of the packed single-precision elements in the first\r\nsource operation and corresponding sign bits in the second source operand. If the AND of the source sign bits with\r\nthe dest sign bits produces all zeros, the ZF is set else the ZF is clear. If the AND of the source sign bits with the\r\ninverted dest sign bits produces all zeros the CF is set else the CF is clear. An attempt to execute VTESTPS with\r\nVEX.W=1 will cause #UD.\r\nVTESTPD performs a bitwise comparison of all the sign bits of the double-precision elements in the first source\r\noperation and corresponding sign bits in the second source operand. If the AND of the source sign bits with the dest\r\nsign bits produces all zeros, the ZF is set else the ZF is clear. If the AND the source sign bits with the inverted dest\r\nsign bits produces all zeros the CF is set else the CF is clear. An attempt to execute VTESTPS with VEX.W=1 will\r\ncause #UD.\r\nThe first source register is specified by the ModR/M reg field.\r\n128-bit version: The first source register is an XMM register. The second source register can be an XMM register or\r\na 128-bit memory location. The destination register is not modified.\r\nVEX.256 encoded version: The first source register is a YMM register. The second source register can be a YMM\r\nregister or a 256-bit memory location. The destination register is not modified.\r\nNote: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVTESTPS (128-bit version)\r\nTEMP[127:0] <- SRC[127:0] AND DEST[127:0]\r\nIF (TEMP[31] = TEMP[63] = TEMP[95] = TEMP[127] = 0)\r\n THEN ZF <-1;\r\n ELSE ZF <- 0;\r\n\r\nTEMP[127:0] <- SRC[127:0] AND NOT DEST[127:0]\r\nIF (TEMP[31] = TEMP[63] = TEMP[95] = TEMP[127] = 0)\r\n THEN CF <-1;\r\n ELSE CF <- 0;\r\nDEST (unmodified)\r\nAF <- OF <- PF <- SF <- 0;\r\n\r\nVTESTPS (VEX.256 encoded version)\r\nTEMP[255:0] <- SRC[255:0] AND DEST[255:0]\r\nIF (TEMP[31] = TEMP[63] = TEMP[95] = TEMP[127]= TEMP[160] =TEMP[191] = TEMP[224] = TEMP[255] = 0)\r\n THEN ZF <-1;\r\n ELSE ZF <- 0;\r\n\r\nTEMP[255:0] <- SRC[255:0] AND NOT DEST[255:0]\r\nIF (TEMP[31] = TEMP[63] = TEMP[95] = TEMP[127]= TEMP[160] =TEMP[191] = TEMP[224] = TEMP[255] = 0)\r\n THEN CF <-1;\r\n ELSE CF <- 0;\r\nDEST (unmodified)\r\nAF <- OF <- PF <- SF <- 0;\r\n\r\nVTESTPD (128-bit version)\r\nTEMP[127:0] <- SRC[127:0] AND DEST[127:0]\r\nIF ( TEMP[63] = TEMP[127] = 0)\r\n THEN ZF <-1;\r\n ELSE ZF <- 0;\r\n\r\nTEMP[127:0] <- SRC[127:0] AND NOT DEST[127:0]\r\nIF ( TEMP[63] = TEMP[127] = 0)\r\n THEN CF <-1;\r\n ELSE CF <- 0;\r\nDEST (unmodified)\r\nAF <- OF <- PF <- SF <- 0;\r\n\r\nVTESTPD (VEX.256 encoded version)\r\nTEMP[255:0] <- SRC[255:0] AND DEST[255:0]\r\nIF (TEMP[63] = TEMP[127] = TEMP[191] = TEMP[255] = 0)\r\n THEN ZF <-1;\r\n ELSE ZF <- 0;\r\n\r\nTEMP[255:0] <- SRC[255:0] AND NOT DEST[255:0]\r\nIF (TEMP[63] = TEMP[127] = TEMP[191] = TEMP[255] = 0)\r\n THEN CF <-1;\r\n ELSE CF <- 0;\r\nDEST (unmodified)\r\nAF <- OF <- PF <- SF <- 0;\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\n\r\nVTESTPS\r\n int _mm256_testz_ps (__m256 s1, __m256 s2);\r\n int _mm256_testc_ps (__m256 s1, __m256 s2);\r\n int _mm256_testnzc_ps (__m256 s1, __m128 s2);\r\n int _mm_testz_ps (__m128 s1, __m128 s2);\r\n int _mm_testc_ps (__m128 s1, __m128 s2);\r\n int _mm_testnzc_ps (__m128 s1, __m128 s2);\r\n\r\n\r\n\r\nVTESTPD\r\n int _mm256_testz_pd (__m256d s1, __m256d s2);\r\n int _mm256_testc_pd (__m256d s1, __m256d s2);\r\n int _mm256_testnzc_pd (__m256d s1, __m256d s2);\r\n int _mm_testz_pd (__m128d s1, __m128d s2);\r\n int _mm_testc_pd (__m128d s1, __m128d s2);\r\n int _mm_testnzc_pd (__m128d s1, __m128d s2);\r\n\r\nFlags Affected\r\nThe 0F, AF, PF, SF flags are cleared and the ZF, CF flags are set according to the operation.\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 4; additionally\r\n#UD If VEX.vvvv != 1111B.\r\n If VEX.W = 1 for VTESTPS or VTESTPD.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VTESTPD"
},
{
"description": "-R:VTESTPD",
"mnem": "VTESTPS"
},
{
"description": "VZEROALL-Zero All YMM Registers\r\n Opcode/ Op/ 64/32 bit CPUID Description\r\n Instruction En Mode Feature\r\n Support Flag\r\n VEX.256.0F.WIG 77 NP V/V AVX Zero all YMM registers.\r\n VZEROALL\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nThe instruction zeros contents of all XMM or YMM registers.\r\nNote: VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD. In Compatibility and legacy 32-\r\nbit mode only the lower 8 registers are modified.\r\n\r\nOperation\r\nVZEROALL (VEX.256 encoded version)\r\nIF (64-bit mode)\r\n YMM0[VLMAX-1:0] <- 0\r\n YMM1[VLMAX-1:0] <- 0\r\n YMM2[VLMAX-1:0] <- 0\r\n YMM3[VLMAX-1:0] <- 0\r\n YMM4[VLMAX-1:0] <- 0\r\n YMM5[VLMAX-1:0] <- 0\r\n YMM6[VLMAX-1:0] <- 0\r\n YMM7[VLMAX-1:0] <- 0\r\n YMM8[VLMAX-1:0] <- 0\r\n YMM9[VLMAX-1:0] <- 0\r\n YMM10[VLMAX-1:0] <- 0\r\n YMM11[VLMAX-1:0] <- 0\r\n YMM12[VLMAX-1:0] <- 0\r\n YMM13[VLMAX-1:0] <- 0\r\n YMM14[VLMAX-1:0] <- 0\r\n YMM15[VLMAX-1:0] <- 0\r\nELSE\r\n YMM0[VLMAX-1:0] <- 0\r\n YMM1[VLMAX-1:0] <- 0\r\n YMM2[VLMAX-1:0] <- 0\r\n YMM3[VLMAX-1:0] <- 0\r\n YMM4[VLMAX-1:0] <- 0\r\n YMM5[VLMAX-1:0] <- 0\r\n YMM6[VLMAX-1:0] <- 0\r\n YMM7[VLMAX-1:0] <- 0\r\n YMM8-15: Unmodified\r\nFI\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVZEROALL: _mm256_zeroall()\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 8.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VZEROALL"
},
{
"description": "VZEROUPPER-Zero Upper Bits of YMM Registers\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\nVEX.128.0F.WIG 77 NP V/V AVX Zero upper 128 bits of all YMM registers.\r\nVZEROUPPER\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nThe instruction zeros the bits in position 128 and higher of all YMM registers. The lower 128-bits of the registers\r\n(the corresponding XMM registers) are unmodified.\r\nThis instruction is recommended when transitioning between AVX and legacy SSE code - it will eliminate perfor-\r\nmance penalties caused by false dependencies.\r\nNote: VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD. In Compatibility and legacy 32-bit\r\nmode only the lower 8 registers are modified.\r\n\r\nOperation\r\nVZEROUPPER\r\nIF (64-bit mode)\r\n YMM0[VLMAX-1:128] <- 0\r\n YMM1[VLMAX-1:128] <- 0\r\n YMM2[VLMAX-1:128] <- 0\r\n YMM3[VLMAX-1:128] <- 0\r\n YMM4[VLMAX-1:128] <- 0\r\n YMM5[VLMAX-1:128] <- 0\r\n YMM6[VLMAX-1:128] <- 0\r\n YMM7[VLMAX-1:128] <- 0\r\n YMM8[VLMAX-1:128] <- 0\r\n YMM9[VLMAX-1:128] <- 0\r\n YMM10[VLMAX-1:128] <- 0\r\n YMM11[VLMAX-1:128] <- 0\r\n YMM12[VLMAX-1:128] <- 0\r\n YMM13[VLMAX-1:128] <- 0\r\n YMM14[VLMAX-1:128] <- 0\r\n YMM15[VLMAX-1:128] <- 0\r\nELSE\r\n YMM0[VLMAX-1:128] <- 0\r\n YMM1[VLMAX-1:128] <- 0\r\n YMM2[VLMAX-1:128] <- 0\r\n YMM3[VLMAX-1:128] <- 0\r\n YMM4[VLMAX-1:128] <- 0\r\n YMM5[VLMAX-1:128] <- 0\r\n YMM6[VLMAX-1:128] <- 0\r\n YMM7[VLMAX-1:128] <- 0\r\n YMM8-15: unmodified\r\nFI\r\n\r\n\r\n\r\n\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVZEROUPPER: _mm256_zeroupper()\r\n\r\nSIMD Floating-Point Exceptions\r\nNone.\r\n\r\nOther Exceptions\r\nSee Exceptions Type 8.\r\n\r\n\r\n\r\n\r\n",
"mnem": "VZEROUPPER"
},
{
"description": "WAIT/FWAIT-Wait\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 9B WAIT NP Valid Valid Check pending unmasked floating-point\r\n exceptions.\r\n 9B FWAIT NP Valid Valid Check pending unmasked floating-point\r\n exceptions.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nCauses the processor to check for and handle pending, unmasked, floating-point exceptions before proceeding.\r\n(FWAIT is an alternate mnemonic for WAIT.)\r\nThis instruction is useful for synchronizing exceptions in critical sections of code. Coding a WAIT instruction after a\r\nfloating-point instruction ensures that any unmasked floating-point exceptions the instruction may raise are\r\nhandled before the processor can modify the instruction's results. See the section titled \"Floating-Point Exception\r\nSynchronization\" in Chapter 8 of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1,\r\nfor more information on using the WAIT/FWAIT instruction.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nOperation\r\nCheckForPendingUnmaskedFloatingPointExceptions;\r\n\r\nFPU Flags Affected\r\nThe C0, C1, C2, and C3 flags are undefined.\r\n\r\nFloating-Point Exceptions\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#NM If CR0.MP[bit 1] = 1 and CR0.TS[bit 3] = 1.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "WAIT"
},
{
"description": "WBINVD-Write Back and Invalidate Cache\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F 09 WBINVD NP Valid Valid Write back and flush Internal caches; initiate\r\n writing-back and flushing of external caches.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nWrites back all modified cache lines in the processor's internal cache to main memory and invalidates (flushes) the\r\ninternal caches. The instruction then issues a special-function bus cycle that directs external caches to also write\r\nback modified data and another bus cycle to indicate that the external caches should be invalidated.\r\nAfter executing this instruction, the processor does not wait for the external caches to complete their write-back\r\nand flushing operations before proceeding with instruction execution. It is the responsibility of hardware to respond\r\nto the cache write-back and flush signals. The amount of time or cycles for WBINVD to complete will vary due to\r\nsize and other factors of different cache hierarchies. As a consequence, the use of the WBINVD instruction can have\r\nan impact on logical processor interrupt/event response time. Additional information of WBINVD behavior in a\r\ncache hierarchy with hierarchical sharing topology can be found in Chapter 2 of the Intel 64 and IA-32 Architec-\r\ntures Software Developer's Manual, Volume 3A.\r\nThe WBINVD instruction is a privileged instruction. When the processor is running in protected mode, the CPL of a\r\nprogram or procedure must be 0 to execute this instruction. This instruction is also a serializing instruction (see\r\n\"Serializing Instructions\" in Chapter 8 of the Intel 64 and IA-32 Architectures Software Developer's Manual,\r\nVolume 3A).\r\nIn situations where cache coherency with main memory is not a concern, software can use the INVD instruction.\r\nThis instruction's operation is the same in non-64-bit modes and 64-bit mode.\r\n\r\nIA-32 Architecture Compatibility\r\nThe WBINVD instruction is implementation dependent, and its function may be implemented differently on future\r\nIntel 64 and IA-32 processors. The instruction is not supported on IA-32 processors earlier than the Intel486\r\nprocessor.\r\n\r\nOperation\r\nWriteBack(InternalCaches);\r\nFlush(InternalCaches);\r\nSignalWriteBack(ExternalCaches);\r\nSignalFlush(ExternalCaches);\r\nContinue; (* Continue execution *)\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the current privilege level is not 0.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) WBINVD cannot be executed at the virtual-8086 mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "WBINVD"
},
{
"description": "WRFSBASE/WRGSBASE-Write FS/GS Segment Base\r\nOpcode/ Op/ 64/32- CPUID Fea- Description\r\nInstruction En bit ture Flag\r\n Mode\r\nF3 0F AE /2 M V/I FSGSBASE Load the FS base address with the 32-bit value in\r\nWRFSBASE r32 the source register.\r\nF3 REX.W 0F AE /2 M V/I FSGSBASE Load the FS base address with the 64-bit value in\r\nWRFSBASE r64 the source register.\r\nF3 0F AE /3 M V/I FSGSBASE Load the GS base address with the 32-bit value in\r\nWRGSBASE r32 the source register.\r\nF3 REX.W 0F AE /3 M V/I FSGSBASE Load the GS base address with the 64-bit value in\r\nWRGSBASE r64 the source register.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (r) NA NA NA\r\n\r\n\r\nDescription\r\nLoads the FS or GS segment base address with the general-purpose register indicated by the modR/M:r/m field.\r\nThe source operand may be either a 32-bit or a 64-bit general-purpose register. The REX.W prefix indicates the\r\noperand size is 64 bits. If no REX.W prefix is used, the operand size is 32 bits; the upper 32 bits of the source\r\nregister are ignored and upper 32 bits of the base address (for FS or GS) are cleared.\r\nThis instruction is supported only in 64-bit mode.\r\n\r\nOperation\r\nFS/GS segment base address <- SRC;\r\n\r\nFlags Affected\r\nNone\r\n\r\nC/C++ Compiler Intrinsic Equivalent\r\nWRFSBASE: void _writefsbase_u32( unsigned int );\r\nWRFSBASE: _writefsbase_u64( unsigned __int64 );\r\nWRGSBASE: void _writegsbase_u32( unsigned int );\r\nWRGSBASE: _writegsbase_u64( unsigned __int64 );\r\n\r\nProtected Mode Exceptions\r\n#UD The WRFSBASE and WRGSBASE instructions are not recognized in protected mode.\r\n\r\nReal-Address Mode Exceptions\r\n#UD The WRFSBASE and WRGSBASE instructions are not recognized in real-address mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#UD The WRFSBASE and WRGSBASE instructions are not recognized in virtual-8086 mode.\r\n\r\nCompatibility Mode Exceptions\r\n#UD The WRFSBASE and WRGSBASE instructions are not recognized in compatibility mode.\r\n\r\n\r\n\r\n64-Bit Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n If CR4.FSGSBASE[bit 16] = 0.\r\n If CPUID.07H.0H:EBX.FSGSBASE[bit 0] = 0\r\n#GP(0) If the source register contains a non-canonical address.\r\n\r\n\r\n\r\n\r\n",
"mnem": "WRFSBASE"
},
{
"description": "-R:WRFSBASE",
"mnem": "WRGSBASE"
},
{
"description": "WRMSR-Write to Model Specific Register\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F 30 WRMSR NP Valid Valid Write the value in EDX:EAX to MSR specified\r\n by ECX.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nWrites the contents of registers EDX:EAX into the 64-bit model specific register (MSR) specified in the ECX register.\r\n(On processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The contents of\r\nthe EDX register are copied to high-order 32 bits of the selected MSR and the contents of the EAX register are\r\ncopied to low-order 32 bits of the MSR. (On processors that support the Intel 64 architecture, the high-order 32\r\nbits of each of RAX and RDX are ignored.) Undefined or reserved bits in an MSR should be set to values previously\r\nread.\r\nThis instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection\r\nexception #GP(0) is generated. Specifying a reserved or unimplemented MSR address in ECX will also cause a\r\ngeneral protection exception. The processor will also generate a general protection exception if software attempts\r\nto write to bits in a reserved MSR.\r\nWhen the WRMSR instruction is used to write to an MTRR, the TLBs are invalidated. This includes global entries (see\r\n\"Translation Lookaside Buffers (TLBs)\" in Chapter 3 of the Intel 64 and IA-32 Architectures Software Developer's\r\nManual, Volume 3A).\r\nMSRs control functions for testability, execution tracing, performance-monitoring and machine check errors.\r\nChapter 35, \"Model-Specific Registers (MSRs)\", in the Intel 64 and IA-32 Architectures Software Developer's\r\nManual, Volume 3C, lists all MSRs that can be written with this instruction and their addresses. Note that each\r\nprocessor family has its own set of MSRs.\r\nThe WRMSR instruction is a serializing instruction (see \"Serializing Instructions\" in Chapter 8 of the Intel 64 and\r\nIA-32 Architectures Software Developer's Manual, Volume 3A). Note that WRMSR to the IA32_TSC_DEADLINE\r\nMSR (MSR index 6E0H) and the X2APIC MSRs (MSR indices 802H to 83FH) are not serializing.\r\nThe CPUID instruction should be used to determine whether MSRs are supported (CPUID.01H:EDX[5] = 1) before\r\nusing this instruction.\r\n\r\nIA-32 Architecture Compatibility\r\nThe MSRs and the ability to read them with the WRMSR instruction were introduced into the IA-32 architecture with\r\nthe Pentium processor. Execution of this instruction by an IA-32 processor earlier than the Pentium processor\r\nresults in an invalid opcode exception #UD.\r\n\r\nOperation\r\nMSR[ECX] <- EDX:EAX;\r\n\r\nFlags Affected\r\nNone.\r\n\r\n\r\n\r\n\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the current privilege level is not 0.\r\n If the value in ECX specifies a reserved or unimplemented MSR address.\r\n If the value in EDX:EAX sets bits that are reserved in the MSR specified by ECX.\r\n If the source register contains a non-canonical address and ECX specifies one of the following\r\n MSRs: IA32_DS_AREA, IA32_FS_BASE, IA32_GS_BASE, IA32_KERNEL_GS_BASE,\r\n IA32_LSTAR, IA32_SYSENTER_EIP, IA32_SYSENTER_ESP.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If the value in ECX specifies a reserved or unimplemented MSR address.\r\n If the value in EDX:EAX sets bits that are reserved in the MSR specified by ECX.\r\n If the source register contains a non-canonical address and ECX specifies one of the following\r\n MSRs: IA32_DS_AREA, IA32_FS_BASE, IA32_GS_BASE, IA32_KERNEL_GS_BASE,\r\n IA32_LSTAR, IA32_SYSENTER_EIP, IA32_SYSENTER_ESP.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) The WRMSR instruction is not recognized in virtual-8086 mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "WRMSR"
},
{
"description": "WRPKRU-Write Data to User Page Key Register\r\nOpcode* Instruction Op/ 64/32bit CPUID Description\r\n En Mode Feature\r\n Support Flag\r\n0F 01 EF WRPKRU NP V/V OSPKE Writes EAX into PKRU.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nWrites the value of EAX into PKRU. ECX and EDX must be 0 when WRPKRU is executed; otherwise, a general-\r\nprotection exception (#GP) occurs.\r\nWRPKRU can be executed only if CR4.PKE = 1; otherwise, an invalid-opcode exception (#UD) occurs. Software can\r\ndiscover the value of CR4.PKE by examining CPUID.(EAX=07H,ECX=0H):ECX.OSPKE [bit 4].\r\nOn processors that support the Intel 64 Architecture, the high-order 32-bits of RCX, RDX and RAX are ignored.\r\n\r\nOperation\r\n\r\nIF (ECX = 0 AND EDX = 0)\r\n THEN PKRU <- EAX;\r\n ELSE #GP(0);\r\nFI;\r\n\r\nFlags Affected\r\nNone.\r\n\r\nC/C++ Compiler Intrinsic Equivalent\r\nWRPKRU: void _wrpkru(uint32_t);\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If ECX != 0.\r\n If EDX != 0.\r\n#UD If the LOCK prefix is used.\r\n If CR4.PKE = 0.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n",
"mnem": "WRPKRU"
},
{
"description": "XABORT - Transactional Abort\r\n Opcode/Instruction Op/ 64/32bit CPUID Description\r\n En Mode Feature\r\n Support Flag\r\n C6 F8 ib A V/V RTM Causes an RTM abort if in RTM execution\r\n XABORT imm8\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand2 Operand3 Operand4\r\n A imm8 NA NA NA\r\n\r\n\r\nDescription\r\nXABORT forces an RTM abort. Following an RTM abort, the logical processor resumes execution at the fallback\r\naddress computed through the outermost XBEGIN instruction. The EAX register is updated to reflect an XABORT\r\ninstruction caused the abort, and the imm8 argument will be provided in bits 31:24 of EAX.\r\n\r\nOperation\r\nXABORT\r\nIF RTM_ACTIVE = 0\r\n THEN\r\n Treat as NOP;\r\n ELSE\r\n GOTO RTM_ABORT_PROCESSING;\r\nFI;\r\n\r\n(* For any RTM abort condition encountered during RTM execution *)\r\nRTM_ABORT_PROCESSING:\r\n Restore architectural register state;\r\n Discard memory updates performed in transaction;\r\n Update EAX with status and XABORT argument;\r\n RTM_NEST_COUNT <- 0;\r\n RTM_ACTIVE <- 0;\r\n IF 64-bit Mode\r\n THEN\r\n RIP <- fallbackRIP;\r\n ELSE\r\n EIP <- fallbackEIP;\r\n FI;\r\nEND\r\n\r\nFlags Affected\r\nNone\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nXABORT: void _xabort( unsigned int);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nOther Exceptions\r\n#UD CPUID.(EAX=7, ECX=0):EBX.RTM[bit 11] = 0.\r\n If LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "XABORT"
},
{
"description": "XACQUIRE/XRELEASE - Hardware Lock Elision Prefix Hints\r\n Opcode/Instruction 64/32bit CPUID Description\r\n Mode Feature\r\n Support Flag\r\n F2 V/V HLE1 A hint used with an \"XACQUIRE-enabled\" instruction to start lock\r\n XACQUIRE elision on the instruction memory operand address.\r\n F3 V/V HLE A hint used with an \"XRELEASE-enabled\" instruction to end lock\r\n XRELEASE elision on the instruction memory operand address.\r\nNOTES:\r\n1. Software is not required to check the HLE feature flag to use XACQUIRE or XRELEASE, as they are treated as regular prefix if HLE\r\n feature flag reports 0.\r\n\r\n\r\n\r\nDescription\r\nThe XACQUIRE prefix is a hint to start lock elision on the memory address specified by the instruction and the\r\nXRELEASE prefix is a hint to end lock elision on the memory address specified by the instruction.\r\nThe XACQUIRE prefix hint can only be used with the following instructions (these instructions are also referred to\r\nas XACQUIRE-enabled when used with the XACQUIRE prefix):\r\n. Instructions with an explicit LOCK prefix (F0H) prepended to forms of the instruction where the destination\r\n operand is a memory operand: ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG, CMPXCHG8B, DEC, INC, NEG, NOT,\r\n OR, SBB, SUB, XOR, XADD, and XCHG.\r\n. The XCHG instruction either with or without the presence of the LOCK prefix.\r\nThe XRELEASE prefix hint can only be used with the following instructions (also referred to as XRELEASE-enabled\r\nwhen used with the XRELEASE prefix):\r\n. Instructions with an explicit LOCK prefix (F0H) prepended to forms of the instruction where the destination\r\n operand is a memory operand: ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG, CMPXCHG8B, DEC, INC, NEG, NOT,\r\n OR, SBB, SUB, XOR, XADD, and XCHG.\r\n. The XCHG instruction either with or without the presence of the LOCK prefix.\r\n. The \"MOV mem, reg\" (Opcode 88H/89H) and \"MOV mem, imm\" (Opcode C6H/C7H) instructions. In these\r\n cases, the XRELEASE is recognized without the presence of the LOCK prefix.\r\nThe lock variables must satisfy the guidelines described in Intel 64 and IA-32 Architectures Software Developer's\r\nManual, Volume 1, Section 16.3.3, for elision to be successful, otherwise an HLE abort may be signaled.\r\nIf an encoded byte sequence that meets XACQUIRE/XRELEASE requirements includes both prefixes, then the HLE\r\nsemantic is determined by the prefix byte that is placed closest to the instruction opcode. For example, an F3F2C6\r\nwill not be treated as a XRELEASE-enabled instruction since the F2H (XACQUIRE) is closest to the instruction\r\nopcode C6. Similarly, an F2F3F0 prefixed instruction will be treated as a XRELEASE-enabled instruction since F3H\r\n(XRELEASE) is closest to the instruction opcode.\r\n\r\n\r\n\r\n\r\n\r\nIntel 64 and IA-32 Compatibility\r\nThe effect of the XACQUIRE/XRELEASE prefix hint is the same in non-64-bit modes and in 64-bit mode.\r\nFor instructions that do not support the XACQUIRE hint, the presence of the F2H prefix behaves the same way as\r\nprior hardware, according to\r\n. REPNE/REPNZ semantics for string instructions,\r\n. Serve as SIMD prefix for legacy SIMD instructions operating on XMM register\r\n. Cause #UD if prepending the VEX prefix.\r\n. Undefined for non-string instructions or other situations.\r\nFor instructions that do not support the XRELEASE hint, the presence of the F3H prefix behaves the same way as in\r\nprior hardware, according to\r\n. REP/REPE/REPZ semantics for string instructions,\r\n. Serve as SIMD prefix for legacy SIMD instructions operating on XMM register\r\n. Cause #UD if prepending the VEX prefix.\r\n. Undefined for non-string instructions or other situations.\r\n\r\nOperation\r\nXACQUIRE\r\nIF XACQUIRE-enabled instruction\r\n THEN\r\n IF (HLE_NEST_COUNT < MAX_HLE_NEST_COUNT) THEN\r\n HLE_NEST_COUNT++\r\n IF (HLE_NEST_COUNT = 1) THEN\r\n HLE_ACTIVE <- 1\r\n IF 64-bit mode\r\n THEN\r\n restartRIP <- instruction pointer of the XACQUIRE-enabled instruction\r\n ELSE\r\n restartEIP <- instruction pointer of the XACQUIRE-enabled instruction\r\n FI;\r\n Enter HLE Execution (* record register state, start tracking memory state *)\r\n FI; (* HLE_NEST_COUNT = 1*)\r\n IF ElisionBufferAvailable\r\n THEN\r\n Allocate elision buffer\r\n Record address and data for forwarding and commit checking\r\n Perform elision\r\n ELSE\r\n Perform lock acquire operation transactionally but without elision\r\n FI;\r\n ELSE (* HLE_NEST_COUNT = MAX_HLE_NEST_COUNT *)\r\n GOTO HLE_ABORT_PROCESSING\r\n FI;\r\n ELSE\r\n Treat instruction as non-XACQUIRE F2H prefixed legacy instruction\r\nFI;\r\n\r\n\r\n\r\n\r\n\r\nXRELEASE\r\n\r\nIF XRELEASE-enabled instruction\r\n THEN\r\n IF (HLE_NEST_COUNT > 0)\r\n THEN\r\n HLE_NEST_COUNT--\r\n IF lock address matches in elision buffer THEN\r\n IF lock satisfies address and value requirements THEN\r\n Deallocate elision buffer\r\n ELSE\r\n GOTO HLE_ABORT_PROCESSING\r\n FI;\r\n FI;\r\n IF (HLE_NEST_COUNT = 0)\r\n THEN\r\n IF NoAllocatedElisionBuffer\r\n THEN\r\n Try to commit transactional execution\r\n IF fail to commit transactional execution\r\n THEN\r\n GOTO HLE_ABORT_PROCESSING;\r\n ELSE (* commit success *)\r\n HLE_ACTIVE <- 0\r\n FI;\r\n ELSE\r\n GOTO HLE_ABORT_PROCESSING\r\n FI;\r\n FI;\r\n FI; (* HLE_NEST_COUNT > 0 *)\r\n ELSE\r\n Treat instruction as non-XRELEASE F3H prefixed legacy instruction\r\nFI;\r\n\r\n(* For any HLE abort condition encountered during HLE execution *)\r\nHLE_ABORT_PROCESSING:\r\n HLE_ACTIVE <- 0\r\n HLE_NEST_COUNT <- 0\r\n Restore architectural register state\r\n Discard memory updates performed in transaction\r\n Free any allocated lock elision buffers\r\n IF 64-bit mode\r\n THEN\r\n RIP <- restartRIP\r\n ELSE\r\n EIP <- restartEIP\r\n FI;\r\n Execute and retire instruction at RIP (or EIP) and ignore any HLE hint\r\nEND\r\n\r\n\r\n\r\n\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\n#GP(0) If the use of prefix causes instruction length to exceed 15 bytes.\r\n\r\n\r\n\r\n\r\n",
"mnem": "XACQUIRE"
},
{
"description": "XADD-Exchange and Add\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F C0 /r XADD r/m8, r8 MR Valid Valid Exchange r8 and r/m8; load sum into r/m8.\r\n REX + 0F C0 /r XADD r/m8*, r8* MR Valid N.E. Exchange r8 and r/m8; load sum into r/m8.\r\n 0F C1 /r XADD r/m16, r16 MR Valid Valid Exchange r16 and r/m16; load sum into r/m16.\r\n 0F C1 /r XADD r/m32, r32 MR Valid Valid Exchange r32 and r/m32; load sum into r/m32.\r\n REX.W + 0F C1 /r XADD r/m64, r64 MR Valid N.E. Exchange r64 and r/m64; load sum into r/m64.\r\n NOTES:\r\n * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n MR ModRM:r/m (r, w) ModRM:reg (r, w) NA NA\r\n\r\n\r\nDescription\r\nExchanges the first operand (destination operand) with the second operand (source operand), then loads the sum\r\nof the two values into the destination operand. The destination operand can be a register or a memory location; the\r\nsource operand is a register.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\nThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.\r\n\r\nIA-32 Architecture Compatibility\r\nIA-32 processors earlier than the Intel486 processor do not recognize this instruction. If this instruction is used,\r\nyou should provide an equivalent code sequence that runs on earlier processors.\r\n\r\nOperation\r\nTEMP <- SRC + DEST;\r\nSRC <- DEST;\r\nDEST <- TEMP;\r\n\r\nFlags Affected\r\nThe CF, PF, AF, SF, ZF, and OF flags are set according to the result of the addition, which is stored in the destination\r\noperand.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination is located in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n",
"mnem": "XADD"
},
{
"description": "XBEGIN - Transactional Begin\r\n Opcode/Instruction Op/ 64/32bit CPUID Description\r\n En Mode Feature\r\n Support Flag\r\n C7 F8 A V/V RTM Specifies the start of an RTM region. Provides a 16-bit relative\r\n XBEGIN rel16 offset to compute the address of the fallback instruction address at\r\n which execution resumes following an RTM abort.\r\n C7 F8 A V/V RTM Specifies the start of an RTM region. Provides a 32-bit relative\r\n XBEGIN rel32 offset to compute the address of the fallback instruction address at\r\n which execution resumes following an RTM abort.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand2 Operand3 Operand4\r\n A Offset NA NA NA\r\n\r\n\r\nDescription\r\nThe XBEGIN instruction specifies the start of an RTM code region. If the logical processor was not already in trans-\r\nactional execution, then the XBEGIN instruction causes the logical processor to transition into transactional execu-\r\ntion. The XBEGIN instruction that transitions the logical processor into transactional execution is referred to as the\r\noutermost XBEGIN instruction. The instruction also specifies a relative offset to compute the address of the fallback\r\ncode path following a transactional abort.\r\nOn an RTM abort, the logical processor discards all architectural register and memory updates performed during\r\nthe RTM execution and restores architectural state to that corresponding to the outermost XBEGIN instruction. The\r\nfallback address following an abort is computed from the outermost XBEGIN instruction.\r\n\r\nOperation\r\nXBEGIN\r\nIF RTM_NEST_COUNT < MAX_RTM_NEST_COUNT\r\n THEN\r\n RTM_NEST_COUNT++\r\n IF RTM_NEST_COUNT = 1 THEN\r\n IF 64-bit Mode\r\n THEN\r\n fallbackRIP <- RIP + SignExtend64(IMM)\r\n (* RIP is instruction following XBEGIN instruction *)\r\n ELSE\r\n fallbackEIP <- EIP + SignExtend32(IMM)\r\n (* EIP is instruction following XBEGIN instruction *)\r\n FI;\r\n\r\n IF (64-bit mode)\r\n THEN IF (fallbackRIP is not canonical)\r\n THEN #GP(0)\r\n FI;\r\n ELSE IF (fallbackEIP outside code segment limit)\r\n THEN #GP(0)\r\n FI;\r\n FI;\r\n\r\n RTM_ACTIVE <- 1\r\n Enter RTM Execution (* record register state, start tracking memory state*)\r\n FI; (* RTM_NEST_COUNT = 1 *)\r\n\r\n\r\n\r\n ELSE (* RTM_NEST_COUNT = MAX_RTM_NEST_COUNT *)\r\n GOTO RTM_ABORT_PROCESSING\r\nFI;\r\n\r\n(* For any RTM abort condition encountered during RTM execution *)\r\nRTM_ABORT_PROCESSING:\r\n Restore architectural register state\r\n Discard memory updates performed in transaction\r\n Update EAX with status\r\n RTM_NEST_COUNT <- 0\r\n RTM_ACTIVE <- 0\r\n IF 64-bit mode\r\n THEN\r\n RIP <- fallbackRIP\r\n ELSE\r\n EIP <- fallbackEIP\r\n FI;\r\nEND\r\n\r\nFlags Affected\r\nNone\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nXBEGIN: unsigned int _xbegin( void );\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nProtected Mode Exceptions\r\n#UD CPUID.(EAX=7, ECX=0):EBX.RTM[bit 11]=0.\r\n If LOCK prefix is used.\r\n#GP(0) If the fallback address is outside the CS segment.\r\n\r\nReal-Address Mode Exceptions\r\n#GP(0) If the fallback address is outside the address space 0000H and FFFFH.\r\n#UD CPUID.(EAX=7, ECX=0):EBX.RTM[bit 11]=0.\r\n If LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If the fallback address is outside the address space 0000H and FFFFH.\r\n#UD CPUID.(EAX=7, ECX=0):EBX.RTM[bit 11]=0.\r\n If LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n\r\n64-bit Mode Exceptions\r\n#UD CPUID.(EAX=7, ECX=0):EBX.RTM[bit 11] = 0.\r\n If LOCK prefix is used.\r\n#GP(0) If the fallback address is non-canonical.\r\n\r\n\r\n\r\n\r\n",
"mnem": "XBEGIN"
},
{
"description": "XCHG - Exchange Register/Memory with Register\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 90+rw XCHG AX, r16 O Valid Valid Exchange r16 with AX.\r\n 90+rw XCHG r16, AX O Valid Valid Exchange AX with r16.\r\n 90+rd XCHG EAX, r32 O Valid Valid Exchange r32 with EAX.\r\n REX.W + 90+rd XCHG RAX, r64 O Valid N.E. Exchange r64 with RAX.\r\n 90+rd XCHG r32, EAX O Valid Valid Exchange EAX with r32.\r\n REX.W + 90+rd XCHG r64, RAX O Valid N.E. Exchange RAX with r64.\r\n 86 /r XCHG r/m8, r8 MR Valid Valid Exchange r8 (byte register) with byte from\r\n r/m8.\r\n REX + 86 /r XCHG r/m8*, r8* MR Valid N.E. Exchange r8 (byte register) with byte from\r\n r/m8.\r\n 86 /r XCHG r8, r/m8 RM Valid Valid Exchange byte from r/m8 with r8 (byte\r\n register).\r\n REX + 86 /r XCHG r8*, r/m8* RM Valid N.E. Exchange byte from r/m8 with r8 (byte\r\n register).\r\n 87 /r XCHG r/m16, r16 MR Valid Valid Exchange r16 with word from r/m16.\r\n 87 /r XCHG r16, r/m16 RM Valid Valid Exchange word from r/m16 with r16.\r\n 87 /r XCHG r/m32, r32 MR Valid Valid Exchange r32 with doubleword from r/m32.\r\n REX.W + 87 /r XCHG r/m64, r64 MR Valid N.E. Exchange r64 with quadword from r/m64.\r\n 87 /r XCHG r32, r/m32 RM Valid Valid Exchange doubleword from r/m32 with r32.\r\n REX.W + 87 /r XCHG r64, r/m64 RM Valid N.E. Exchange quadword from r/m64 with r64.\r\n NOTES:\r\n * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n O AX/EAX/RAX (r, w) opcode + rd (r, w) NA NA\r\n O opcode + rd (r, w) AX/EAX/RAX (r, w) NA NA\r\n MR ModRM:r/m (r, w) ModRM:reg (r) NA NA\r\n RM ModRM:reg (w) ModRM:r/m (r) NA NA\r\n\r\n\r\nDescription\r\nExchanges the contents of the destination (first) and source (second) operands. The operands can be two general-\r\npurpose registers or a register and a memory location. If a memory operand is referenced, the processor's locking\r\nprotocol is automatically implemented for the duration of the exchange operation, regardless of the presence or\r\nabsence of the LOCK prefix or of the value of the IOPL. (See the LOCK prefix description in this chapter for more\r\ninformation on the locking protocol.)\r\nThis instruction is useful for implementing semaphores or similar data structures for process synchronization. (See\r\n\"Bus Locking\" in Chapter 8 of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, for\r\nmore information on bus locking.)\r\nThe XCHG instruction can also be used instead of the BSWAP instruction for 16-bit operands.\r\nIn 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits\r\naccess to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See\r\nthe summary chart at the beginning of this section for encoding data and limits.\r\n\r\n\r\n\r\n NOTE\r\n XCHG (E)AX, (E)AX (encoded instruction byte is 90H) is an alias for NOP regardless of data size\r\n prefixes, including REX.W.\r\n\r\nOperation\r\nTEMP <- DEST;\r\nDEST <- SRC;\r\nSRC <- TEMP;\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If either operand is in a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n",
"mnem": "XCHG"
},
{
"description": "XEND - Transactional End\r\n Opcode/Instruction Op/ 64/32bit CPUID Description\r\n En Mode Feature\r\n Support Flag\r\n 0F 01 D5 A V/V RTM Specifies the end of an RTM code region.\r\n XEND\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand2 Operand3 Operand4\r\n A NA NA NA NA\r\n\r\n\r\nDescription\r\nThe instruction marks the end of an RTM code region. If this corresponds to the outermost scope (that is, including\r\nthis XEND instruction, the number of XBEGIN instructions is the same as number of XEND instructions), the logical\r\nprocessor will attempt to commit the logical processor state atomically. If the commit fails, the logical processor will\r\nrollback all architectural register and memory updates performed during the RTM execution. The logical processor\r\nwill resume execution at the fallback address computed from the outermost XBEGIN instruction. The EAX register\r\nis updated to reflect RTM abort information.\r\nXEND executed outside a transactional region will cause a #GP (General Protection Fault).\r\n\r\nOperation\r\nXEND\r\nIF (RTM_ACTIVE = 0) THEN\r\n SIGNAL #GP\r\nELSE\r\n RTM_NEST_COUNT--\r\n IF (RTM_NEST_COUNT = 0) THEN\r\n Try to commit transaction\r\n IF fail to commit transactional execution\r\n THEN\r\n GOTO RTM_ABORT_PROCESSING;\r\n ELSE (* commit success *)\r\n RTM_ACTIVE <- 0\r\n FI;\r\n FI;\r\nFI;\r\n\r\n(* For any RTM abort condition encountered during RTM execution *)\r\nRTM_ABORT_PROCESSING:\r\n Restore architectural register state\r\n Discard memory updates performed in transaction\r\n Update EAX with status\r\n RTM_NEST_COUNT <- 0\r\n RTM_ACTIVE <- 0\r\n IF 64-bit Mode\r\n THEN\r\n RIP <- fallbackRIP\r\n ELSE\r\n EIP <- fallbackEIP\r\n FI;\r\nEND\r\n\r\n\r\n\r\n\r\nFlags Affected\r\nNone\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nXEND: void _xend( void );\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\n#UD CPUID.(EAX=7, ECX=0):EBX.RTM[bit 11] = 0.\r\n If LOCK or 66H or F2H or F3H prefix is used.\r\n#GP(0) If RTM_ACTIVE = 0.\r\n\r\n\r\n\r\n\r\n",
"mnem": "XEND"
},
{
"description": "XGETBV-Get Value of Extended Control Register\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F 01 D0 XGETBV NP Valid Valid Reads an XCR specified by ECX into EDX:EAX.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nReads the contents of the extended control register (XCR) specified in the ECX register into registers EDX:EAX. (On\r\nprocessors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The EDX register is\r\nloaded with the high-order 32 bits of the XCR and the EAX register is loaded with the low-order 32 bits. (On proces-\r\nsors that support the Intel 64 architecture, the high-order 32 bits of each of RAX and RDX are cleared.) If fewer\r\nthan 64 bits are implemented in the XCR being read, the values returned to EDX:EAX in unimplemented bit loca-\r\ntions are undefined.\r\nXCR0 is supported on any processor that supports the XGETBV instruction. If\r\nCPUID.(EAX=0DH,ECX=1):EAX.XG1[bit 2] = 1, executing XGETBV with ECX = 1 returns in EDX:EAX the logical-\r\nAND of XCR0 and the current value of the XINUSE state-component bitmap. This allows software to discover the\r\nstate of the init optimization used by XSAVEOPT and XSAVES. See Chapter 13, \"Managing State Using the XSAVE\r\nFeature Set,\" in Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1.\r\nUse of any other value for ECX results in a general-protection (#GP) exception.\r\n\r\nOperation\r\nEDX:EAX <- XCR[ECX];\r\n\r\nFlags Affected\r\nNone.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nXGETBV: unsigned __int64 _xgetbv( unsigned int);\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If an invalid XCR is specified in ECX (includes ECX = 1 if\r\n CPUID.(EAX=0DH,ECX=1):EAX.XG1[bit 2] = 0).\r\n#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0.\r\n If CR4.OSXSAVE[bit 18] = 0.\r\n If the LOCK prefix is used.\r\n If 66H, F3H or F2H prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP(0) If an invalid XCR is specified in ECX (includes ECX = 1 if\r\n CPUID.(EAX=0DH,ECX=1):EAX.XG1[bit 2] = 0).\r\n#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0.\r\n If CR4.OSXSAVE[bit 18] = 0.\r\n If the LOCK prefix is used.\r\n If 66H, F3H or F2H prefix is used.\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "XGETBV"
},
{
"description": "XLAT/XLATB-Table Look-up Translation\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n D7 XLAT m8 NP Valid Valid Set AL to memory byte DS:[(E)BX + unsigned\r\n AL].\r\n D7 XLATB NP Valid Valid Set AL to memory byte DS:[(E)BX + unsigned\r\n AL].\r\n REX.W + D7 XLATB NP Valid N.E. Set AL to memory byte [RBX + unsigned AL].\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nLocates a byte entry in a table in memory, using the contents of the AL register as a table index, then copies the\r\ncontents of the table entry back into the AL register. The index in the AL register is treated as an unsigned integer.\r\nThe XLAT and XLATB instructions get the base address of the table in memory from either the DS:EBX or the DS:BX\r\nregisters (depending on the address-size attribute of the instruction, 32 or 16, respectively). (The DS segment may\r\nbe overridden with a segment override prefix.)\r\nAt the assembly-code level, two forms of this instruction are allowed: the \"explicit-operand\" form and the \"no-\r\noperand\" form. The explicit-operand form (specified with the XLAT mnemonic) allows the base address of the table\r\nto be specified explicitly with a symbol. This explicit-operands form is provided to allow documentation; however,\r\nnote that the documentation provided by this form can be misleading. That is, the symbol does not have to specify\r\nthe correct base address. The base address is always specified by the DS:(E)BX registers, which must be loaded\r\ncorrectly before the XLAT instruction is executed.\r\nThe no-operands form (XLATB) provides a \"short form\" of the XLAT instructions. Here also the processor assumes\r\nthat the DS:(E)BX registers contain the base address of the table.\r\nIn 64-bit mode, operation is similar to that in legacy or compatibility mode. AL is used to specify the table index\r\n(the operand size is fixed at 8 bits). RBX, however, is used to specify the table's base address. See the summary\r\nchart at the beginning of this section for encoding data and limits.\r\n\r\nOperation\r\nIF AddressSize = 16\r\n THEN\r\n AL <- (DS:BX + ZeroExtend(AL));\r\n ELSE IF (AddressSize = 32)\r\n AL <- (DS:EBX + ZeroExtend(AL)); FI;\r\n ELSE (AddressSize = 64)\r\n AL <- (RBX + ZeroExtend(AL));\r\nFI;\r\n\r\nFlags Affected\r\nNone.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n\r\n\r\n\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#UD If the LOCK prefix is used.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#UD If the LOCK prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "XLAT"
},
{
"description": "-R:XLAT",
"mnem": "XLATB"
},
{
"description": "XOR-Logical Exclusive OR\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 34 ib XOR AL, imm8 I Valid Valid AL XOR imm8.\r\n 35 iw XOR AX, imm16 I Valid Valid AX XOR imm16.\r\n 35 id XOR EAX, imm32 I Valid Valid EAX XOR imm32.\r\n REX.W + 35 id XOR RAX, imm32 I Valid N.E. RAX XOR imm32 (sign-extended).\r\n 80 /6 ib XOR r/m8, imm8 MI Valid Valid r/m8 XOR imm8.\r\n REX + 80 /6 ib XOR r/m8*, imm8 MI Valid N.E. r/m8 XOR imm8.\r\n 81 /6 iw XOR r/m16, imm16 MI Valid Valid r/m16 XOR imm16.\r\n 81 /6 id XOR r/m32, imm32 MI Valid Valid r/m32 XOR imm32.\r\n REX.W + 81 /6 id XOR r/m64, imm32 MI Valid N.E. r/m64 XOR imm32 (sign-extended).\r\n 83 /6 ib XOR r/m16, imm8 MI Valid Valid r/m16 XOR imm8 (sign-extended).\r\n 83 /6 ib XOR r/m32, imm8 MI Valid Valid r/m32 XOR imm8 (sign-extended).\r\n REX.W + 83 /6 ib XOR r/m64, imm8 MI Valid N.E. r/m64 XOR imm8 (sign-extended).\r\n 30 /r XOR r/m8, r8 MR Valid Valid r/m8 XOR r8.\r\n REX + 30 /r XOR r/m8*, r8* MR Valid N.E. r/m8 XOR r8.\r\n 31 /r XOR r/m16, r16 MR Valid Valid r/m16 XOR r16.\r\n 31 /r XOR r/m32, r32 MR Valid Valid r/m32 XOR r32.\r\n REX.W + 31 /r XOR r/m64, r64 MR Valid N.E. r/m64 XOR r64.\r\n 32 /r XOR r8, r/m8 RM Valid Valid r8 XOR r/m8.\r\n REX + 32 /r XOR r8*, r/m8* RM Valid N.E. r8 XOR r/m8.\r\n 33 /r XOR r16, r/m16 RM Valid Valid r16 XOR r/m16.\r\n 33 /r XOR r32, r/m32 RM Valid Valid r32 XOR r/m32.\r\n REX.W + 33 /r XOR r64, r/m64 RM Valid N.E. r64 XOR r/m64.\r\n NOTES:\r\n * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n I AL/AX/EAX/RAX imm8/16/32 NA NA\r\n MI ModRM:r/m (r, w) imm8/16/32 NA NA\r\n MR ModRM:r/m (r, w) ModRM:reg (r) NA NA\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n\r\n\r\nDescription\r\nPerforms a bitwise exclusive OR (XOR) operation on the destination (first) and source (second) operands and\r\nstores the result in the destination operand location. The source operand can be an immediate, a register, or a\r\nmemory location; the destination operand can be a register or a memory location. (However, two memory oper-\r\nands cannot be used in one instruction.) Each bit of the result is 1 if the corresponding bits of the operands are\r\ndifferent; each bit is 0 if the corresponding bits are the same.\r\nThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.\r\n\r\n\r\n\r\n\r\n\r\nIn 64-bit mode, using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a\r\nREX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this\r\nsection for encoding data and limits.\r\n\r\nOperation\r\nDEST <- DEST XOR SRC;\r\n\r\nFlags Affected\r\nThe OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is\r\nundefined.\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the destination operand points to a non-writable segment.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If the DS, ES, FS, or GS register contains a NULL segment selector.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS If a memory operand effective address is outside the SS segment limit.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the\r\n current privilege level is 3.\r\n#UD If the LOCK prefix is used but the destination is not a memory operand.\r\n\r\n\r\n\r\n\r\n",
"mnem": "XOR"
},
{
"description": "XORPD-Bitwise Logical XOR of Packed Double Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 66 0F 57/r V/V SSE2 Return the bitwise logical XOR of packed double-\r\n RM\r\n XORPD xmm1, xmm2/m128 precision floating-point values in xmm1 and xmm2/mem.\r\n VEX.NDS.128.66.0F.WIG 57 /r V/V AVX Return the bitwise logical XOR of packed double-\r\n VXORPD xmm1,xmm2, RVM precision floating-point values in xmm2 and xmm3/mem.\r\n xmm3/m128\r\n VEX.NDS.256.66.0F.WIG 57 /r RVM V/V AVX Return the bitwise logical XOR of packed double-\r\n VXORPD ymm1, ymm2, precision floating-point values in ymm2 and ymm3/mem.\r\n ymm3/m256\r\n EVEX.NDS.128.66.0F.W1 57 /r FV V/V AVX512VL Return the bitwise logical XOR of packed double-\r\n VXORPD xmm1 {k1}{z}, xmm2, AVX512DQ precision floating-point values in xmm2 and\r\n xmm3/m128/m64bcst xmm3/m128/m64bcst subject to writemask k1.\r\n EVEX.NDS.256.66.0F.W1 57 /r FV V/V AVX512VL Return the bitwise logical XOR of packed double-\r\n VXORPD ymm1 {k1}{z}, ymm2, AVX512DQ precision floating-point values in ymm2 and\r\n ymm3/m256/m64bcst ymm3/m256/m64bcst subject to writemask k1.\r\n EVEX.NDS.512.66.0F.W1 57 /r FV V/V AVX512DQ Return the bitwise logical XOR of packed double-\r\n VXORPD zmm1 {k1}{z}, zmm2, precision floating-point values in zmm2 and\r\n zmm3/m512/m64bcst zmm3/m512/m64bcst subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a bitwise logical XOR of the two, four or eight packed double-precision floating-point values from the first\r\nsource operand and the second source operand, and stores the result in the destination operand\r\nEVEX.512 encoded version: The first source operand is a ZMM register. The second source operand can be a ZMM\r\nregister or a vector memory location. The destination operand is a ZMM register conditionally updated with\r\nwritemask k1.\r\nVEX.256 and EVEX.256 encoded versions: The first source operand is a YMM register. The second source operand\r\nis a YMM register or a 256-bit memory location. The destination operand is a YMM register (conditionally updated\r\nwith writemask k1 in case of EVEX). The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination\r\nare zeroed.\r\nVEX.128 and EVEX.128 encoded versions: The first source operand is an XMM register. The second source operand\r\nis an XMM register or 128-bit memory location. The destination operand is an XMM register (conditionally updated\r\nwith writemask k1 in case of EVEX). The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination\r\nare zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nregister destination are unmodified.\r\n\r\nOperation\r\nVXORPD (EVEX encoded versions)\r\n(KL, VL) = (2, 128), (4, 256), (8, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 64\r\n IF k1[j] OR *no writemask* THEN\r\n\r\n\r\n\r\n IF (EVEX.b == 1) AND (SRC2 *is memory*)\r\n THEN DEST[i+63:i] <- SRC1[i+63:i] BITWISE XOR SRC2[63:0];\r\n ELSE DEST[i+63:i] <- SRC1[i+63:i] BITWISE XOR SRC2[i+63:i];\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+63:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+63:i] = 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVXORPD (VEX.256 encoded version)\r\nDEST[63:0] <- SRC1[63:0] BITWISE XOR SRC2[63:0]\r\nDEST[127:64] <- SRC1[127:64] BITWISE XOR SRC2[127:64]\r\nDEST[191:128] <- SRC1[191:128] BITWISE XOR SRC2[191:128]\r\nDEST[255:192] <- SRC1[255:192] BITWISE XOR SRC2[255:192]\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVXORPD (VEX.128 encoded version)\r\nDEST[63:0] <- SRC1[63:0] BITWISE XOR SRC2[63:0]\r\nDEST[127:64] <- SRC1[127:64] BITWISE XOR SRC2[127:64]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nXORPD (128-bit Legacy SSE version)\r\nDEST[63:0] <- DEST[63:0] BITWISE XOR SRC[63:0]\r\nDEST[127:64] <- DEST[127:64] BITWISE XOR SRC[127:64]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVXORPD __m512d _mm512_xor_pd (__m512d a, __m512d b);\r\nVXORPD __m512d _mm512_mask_xor_pd (__m512d a, __mmask8 m, __m512d b);\r\nVXORPD __m512d _mm512_maskz_xor_pd (__mmask8 m, __m512d a);\r\nVXORPD __m256d _mm256_xor_pd (__m256d a, __m256d b);\r\nVXORPD __m256d _mm256_mask_xor_pd (__m256d a, __mmask8 m, __m256d b);\r\nVXORPD __m256d _mm256_maskz_xor_pd (__mmask8 m, __m256d a);\r\nXORPD __m128d _mm_xor_pd (__m128d a, __m128d b);\r\nVXORPD __m128d _mm_mask_xor_pd (__m128d a, __mmask8 m, __m128d b);\r\nVXORPD __m128d _mm_maskz_xor_pd (__mmask8 m, __m128d a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\n\r\n\r\n\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instructions, see Exceptions Type 4.\r\nEVEX-encoded instructions, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "XORPD"
},
{
"description": "XORPS-Bitwise Logical XOR of Packed Single Precision Floating-Point Values\r\n Opcode/ Op / 64/32 CPUID Description\r\n Instruction En bit Mode Feature\r\n Support Flag\r\n 0F 57 /r RM V/V SSE Return the bitwise logical XOR of packed single-\r\n XORPS xmm1, xmm2/m128 precision floating-point values in xmm1 and\r\n xmm2/mem.\r\n VEX.NDS.128.0F.WIG 57 /r RVM V/V AVX Return the bitwise logical XOR of packed single-\r\n VXORPS xmm1,xmm2, xmm3/m128 precision floating-point values in xmm2 and\r\n xmm3/mem.\r\n VEX.NDS.256.0F.WIG 57 /r RVM V/V AVX Return the bitwise logical XOR of packed single-\r\n VXORPS ymm1, ymm2, ymm3/m256 precision floating-point values in ymm2 and\r\n ymm3/mem.\r\n EVEX.NDS.128.0F.W0 57 /r FV V/V AVX512VL Return the bitwise logical XOR of packed single-\r\n VXORPS xmm1 {k1}{z}, xmm2, AVX512DQ precision floating-point values in xmm2 and\r\n xmm3/m128/m32bcst xmm3/m128/m32bcst subject to writemask k1.\r\n EVEX.NDS.256.0F.W0 57 /r FV V/V AVX512VL Return the bitwise logical XOR of packed single-\r\n VXORPS ymm1 {k1}{z}, ymm2, AVX512DQ precision floating-point values in ymm2 and\r\n ymm3/m256/m32bcst ymm3/m256/m32bcst subject to writemask k1.\r\n EVEX.NDS.512.0F.W0 57 /r FV V/V AVX512DQ Return the bitwise logical XOR of packed single-\r\n VXORPS zmm1 {k1}{z}, zmm2, precision floating-point values in zmm2 and\r\n zmm3/m512/m32bcst zmm3/m512/m32bcst subject to writemask k1.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n RM ModRM:reg (r, w) ModRM:r/m (r) NA NA\r\n RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA\r\n FV ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA\r\n\r\nDescription\r\nPerforms a bitwise logical XOR of the four, eight or sixteen packed single-precision floating-point values from the\r\nfirst source operand and the second source operand, and stores the result in the destination operand\r\nEVEX.512 encoded version: The first source operand is a ZMM register. The second source operand can be a ZMM\r\nregister or a vector memory location. The destination operand is a ZMM register conditionally updated with\r\nwritemask k1.\r\nVEX.256 and EVEX.256 encoded versions: The first source operand is a YMM register. The second source operand\r\nis a YMM register or a 256-bit memory location. The destination operand is a YMM register (conditionally updated\r\nwith writemask k1 in case of EVEX). The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination\r\nare zeroed.\r\nVEX.128 and EVEX.128 encoded versions: The first source operand is an XMM register. The second source operand\r\nis an XMM register or 128-bit memory location. The destination operand is an XMM register (conditionally updated\r\nwith writemask k1 in case of EVEX). The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination\r\nare zeroed.\r\n128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-\r\nnation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding\r\nregister destination are unmodified.\r\n\r\n\r\n\r\n\r\n\r\nOperation\r\nVXORPS (EVEX encoded versions)\r\n(KL, VL) = (4, 128), (8, 256), (16, 512)\r\nFOR j <- 0 TO KL-1\r\n i <- j * 32\r\n IF k1[j] OR *no writemask* THEN\r\n IF (EVEX.b == 1) AND (SRC2 *is memory*)\r\n THEN DEST[i+31:i] <- SRC1[i+31:i] BITWISE XOR SRC2[31:0];\r\n ELSE DEST[i+31:i] <- SRC1[i+31:i] BITWISE XOR SRC2[i+31:i];\r\n FI;\r\n ELSE\r\n IF *merging-masking* ; merging-masking\r\n THEN *DEST[i+31:i] remains unchanged*\r\n ELSE *zeroing-masking* ; zeroing-masking\r\n DEST[i+31:i] = 0\r\n FI\r\n FI;\r\nENDFOR\r\nDEST[MAX_VL-1:VL] <- 0\r\n\r\nVXORPS (VEX.256 encoded version)\r\nDEST[31:0] <- SRC1[31:0] BITWISE XOR SRC2[31:0]\r\nDEST[63:32] <- SRC1[63:32] BITWISE XOR SRC2[63:32]\r\nDEST[95:64] <- SRC1[95:64] BITWISE XOR SRC2[95:64]\r\nDEST[127:96] <- SRC1[127:96] BITWISE XOR SRC2[127:96]\r\nDEST[159:128] <- SRC1[159:128] BITWISE XOR SRC2[159:128]\r\nDEST[191:160] <- SRC1[191:160] BITWISE XOR SRC2[191:160]\r\nDEST[223:192] <- SRC1[223:192] BITWISE XOR SRC2[223:192]\r\nDEST[255:224] <- SRC1[255:224] BITWISE XOR SRC2[255:224].\r\nDEST[MAX_VL-1:256] <- 0\r\n\r\nVXORPS (VEX.128 encoded version)\r\nDEST[31:0] <- SRC1[31:0] BITWISE XOR SRC2[31:0]\r\nDEST[63:32] <- SRC1[63:32] BITWISE XOR SRC2[63:32]\r\nDEST[95:64] <- SRC1[95:64] BITWISE XOR SRC2[95:64]\r\nDEST[127:96] <- SRC1[127:96] BITWISE XOR SRC2[127:96]\r\nDEST[MAX_VL-1:128] <- 0\r\n\r\nXORPS (128-bit Legacy SSE version)\r\nDEST[31:0] <- SRC1[31:0] BITWISE XOR SRC2[31:0]\r\nDEST[63:32] <- SRC1[63:32] BITWISE XOR SRC2[63:32]\r\nDEST[95:64] <- SRC1[95:64] BITWISE XOR SRC2[95:64]\r\nDEST[127:96] <- SRC1[127:96] BITWISE XOR SRC2[127:96]\r\nDEST[MAX_VL-1:128] (Unmodified)\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nVXORPS __m512 _mm512_xor_ps (__m512 a, __m512 b);\r\nVXORPS __m512 _mm512_mask_xor_ps (__m512 a, __mmask16 m, __m512 b);\r\nVXORPS __m512 _mm512_maskz_xor_ps (__mmask16 m, __m512 a);\r\nVXORPS __m256 _mm256_xor_ps (__m256 a, __m256 b);\r\nVXORPS __m256 _mm256_mask_xor_ps (__m256 a, __mmask8 m, __m256 b);\r\nVXORPS __m256 _mm256_maskz_xor_ps (__mmask8 m, __m256 a);\r\nXORPS __m128 _mm_xor_ps (__m128 a, __m128 b);\r\nVXORPS __m128 _mm_mask_xor_ps (__m128 a, __mmask8 m, __m128 b);\r\n\r\n\r\nVXORPS __m128 _mm_maskz_xor_ps (__mmask8 m, __m128 a);\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\nNon-EVEX-encoded instructions, see Exceptions Type 4.\r\nEVEX-encoded instructions, see Exceptions Type E4.\r\n\r\n\r\n\r\n\r\n",
"mnem": "XORPS"
},
{
"description": "-R:XACQUIRE",
"mnem": "XRELEASE"
},
{
"description": "XRSTOR-Restore Processor Extended States\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F AE /5 XRSTOR mem M Valid Valid Restore state components specified by\r\n EDX:EAX from mem.\r\n REX.W+ 0F AE /5 XRSTOR64 mem M Valid N.E. Restore state components specified by\r\n EDX:EAX from mem.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (r) NA NA NA\r\n\r\n\r\nDescription\r\nPerforms a full or partial restore of processor state components from the XSAVE area located at the memory\r\naddress specified by the source operand. The implicit EDX:EAX register pair specifies a 64-bit instruction mask. The\r\nspecific state components restored correspond to the bits set in the requested-feature bitmap (RFBM), which is the\r\nlogical-AND of EDX:EAX and XCR0.\r\nThe format of the XSAVE area is detailed in Section 13.4, \"XSAVE Area,\" of Intel 64 and IA-32 Architectures Soft-\r\nware Developer's Manual, Volume 1.\r\nSection 13.8, \"Operation of XRSTOR,\" of Intel 64 and IA-32 Architectures Software Developer's Manual, Volume\r\n1 provides a detailed description of the operation of the XRSTOR instruction. The following items provide a high-\r\nlevel outline:\r\n. Execution of XRSTOR may take one of two forms: standard and compacted. Bit 63 of the XCOMP_BV field in the\r\n XSAVE header determines which form is used: value 0 specifies the standard form, while value 1 specifies the\r\n compacted form.\r\n. If RFBM[i] = 0, XRSTOR does not update state component i.1\r\n. If RFBM[i] = 1 and bit i is clear in the XSTATE_BV field in the XSAVE header, XRSTOR initializes state\r\n component i.\r\n. If RFBM[i] = 1 and XSTATE_BV[i] = 1, XRSTOR loads state component i from the XSAVE area.\r\n. The standard form of XRSTOR treats MXCSR (which is part of state component 1 - SSE) differently from the\r\n XMM registers. If either form attempts to load MXCSR with an illegal value, a general-protection exception\r\n (#GP) occurs.\r\n. XRSTOR loads the internal value XRSTOR_INFO, which may be used to optimize a subsequent execution of\r\n XSAVEOPT or XSAVES.\r\n. Immediately following an execution of XRSTOR, the processor tracks as in-use (not in initial configuration) any\r\n state component i for which RFBM[i] = 1 and XSTATE_BV[i] = 1; it tracks as modified any state component\r\n i for which RFBM[i] = 0.\r\nUse of a source operand not aligned to 64-byte boundary (for 64-bit and 32-bit modes) results in a general-protec-\r\ntion (#GP) exception. In 64-bit mode, the upper 32 bits of RDX and RAX are ignored.\r\n\r\nOperation\r\n\r\nRFBM <- XCR0 AND EDX:EAX; /* bitwise logical AND */\r\nCOMPMASK <- XCOMP_BV field from XSAVE header;\r\nRSTORMASK <- XSTATE_BV field from XSAVE header;\r\nIF in VMX non-root operation\r\n THEN VMXNR <- 1;\r\n\r\n1. There is an exception if RFBM[1] = 0 and RFBM[2] = 1. In this case, the standard form of XRSTOR will load MXCSR from memory,\r\n even though MXCSR is part of state component 1 - SSE. The compacted form of XRSTOR does not make this exception.\r\n\r\n\r\n\r\n ELSE VMXNR <- 0;\r\nFI;\r\nLAXA <- linear address of XSAVE area;\r\n\r\nIF COMPMASK[63] = 0\r\n THEN\r\n /* Standard form of XRSTOR */\r\n If RFBM[0] = 1\r\n THEN\r\n IF RSTORMASK[0] = 1\r\n THEN load x87 state from legacy region of XSAVE area;\r\n ELSE initialize x87 state;\r\n FI;\r\n FI;\r\n If RFBM[1] = 1\r\n THEN\r\n IF RSTORMASK[1] = 1\r\n THEN load XMM registers from legacy region of XSAVE area;\r\n ELSE set all XMM registers to 0;\r\n FI;\r\n FI;\r\n If RFBM[2] = 1\r\n THEN\r\n IF RSTORMASK[2] = 1\r\n THEN load AVX state from extended region (standard format) of XSAVE area;\r\n ELSE initialize AVX state;\r\n FI;\r\n FI;\r\n If RFBM[1] = 1 or RFBM[2] = 1\r\n THEN load MXCSR from legacy region of XSAVE area;\r\n FI;\r\nFI;\r\n ELSE\r\n /* Compacted form of XRSTOR */\r\n IF CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit 1] = 0\r\n THEN /* compacted form not supported */\r\n #GP(0);\r\n FI;\r\n If RFBM[0] = 1\r\n THEN\r\n IF RSTORMASK[0] = 1\r\n THEN load x87 state from legacy region of XSAVE area;\r\n ELSE initialize x87 state;\r\n FI;\r\n FI;\r\n If RFBM[1] = 1\r\n THEN\r\n IF RSTORMASK[1] = 1\r\n THEN load SSE state from legacy region of XSAVE area;\r\n ELSE initialize SSE state;\r\n FI;\r\n FI;\r\n If RFBM[2] = 1\r\n THEN\r\n\r\n\r\n\r\n IF RSTORMASK[2] = 1\r\n THEN load AVX state from extended region (compacted format) of XSAVE area;\r\n ELSE initialize AVX state;\r\n FI;\r\n FI;\r\nFI;\r\nXRSTOR_INFO <- (CPL,VMXNR,LAXA,COMPMASK);\r\n\r\nFlags Affected\r\nNone.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nXRSTOR: void _xrstor( void * , unsigned __int64);\r\nXRSTOR: void _xrstor64( void * , unsigned __int64);\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If a memory operand is not aligned on a 64-byte boundary, regardless of segment.\r\n If bit 63 of the XCOMP_BV field of the XSAVE header is 1 and\r\n CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit 1] = 0.\r\n If the standard form is executed and a bit in XCR0 is 0 and the corresponding bit in the\r\n XSTATE_BV field of the XSAVE header is 1.\r\n If the standard form is executed and bytes 23:8 of the XSAVE header are not all zero.\r\n If the compacted form is executed and a bit in XCR0 is 0 and the corresponding bit in the\r\n XCOMP_BV field of the XSAVE header is 1.\r\n If the compacted form is executed and a bit in the XCOMP_BV field in the XSAVE header is 0\r\n and the corresponding bit in the XSTATE_BV field is 1.\r\n If the compacted form is executed and bytes 63:16 of the XSAVE header are not all zero.\r\n If attempting to write any reserved bits of the MXCSR register with 1.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#NM If CR0.TS[bit 3] = 1.\r\n#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0.\r\n If CR4.OSXSAVE[bit 18] = 0.\r\n If any of the LOCK, 66H, F3H or F2H prefixes is used.\r\n#AC If this exception is disabled a general protection exception (#GP) is signaled if the memory\r\n operand is not aligned on a 16-byte boundary, as described above. If the alignment check\r\n exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may\r\n vary with implementation, as follows. In all implementations where #AC is not signaled, a\r\n general protection exception is signaled in its place. In addition, the width of the alignment\r\n check may also vary with implementation. For instance, for a given implementation, an align-\r\n ment check exception might be signaled for a 2-byte misalignment, whereas a general protec-\r\n tion exception might be signaled for all other misalignments (4-, 8-, or 16-byte\r\n misalignments).\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand is not aligned on a 64-byte boundary, regardless of segment.\r\n If any part of the operand lies outside the effective address space from 0 to FFFFH.\r\n If bit 63 of the XCOMP_BV field of the XSAVE header is 1 and\r\n CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit 1] = 0.\r\n\r\n\r\n\r\n\r\n If the standard form is executed and a bit in XCR0 is 0 and the corresponding bit in the\r\n XSTATE_BV field of the XSAVE header is 1.\r\n If the standard form is executed and bytes 23:8 of the XSAVE header are not all zero.\r\n If the compacted form is executed and a bit in XCR0 is 0 and the corresponding bit in the\r\n XCOMP_BV field of the XSAVE header is 1.\r\n If the compacted form is executed and a bit in the XCOMP_BV field in the XSAVE header is 0\r\n and the corresponding bit in the XSTATE_BV field is 1.\r\n If the compacted form is executed and bytes 63:16 of the XSAVE header are not all zero.\r\n If attempting to write any reserved bits of the MXCSR register with 1.\r\n#NM If CR0.TS[bit 3] = 1.\r\n#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0.\r\n If CR4.OSXSAVE[bit 18] = 0.\r\n If any of the LOCK, 66H, F3H or F2H prefixes is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If a memory address is in a non-canonical form.\r\n If a memory operand is not aligned on a 64-byte boundary, regardless of segment.\r\n If bit 63 of the XCOMP_BV field of the XSAVE header is 1 and\r\n CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit 1] = 0.\r\n If the standard form is executed and a bit in XCR0 is 0 and the corresponding bit in the\r\n XSTATE_BV field of the XSAVE header is 1.\r\n If the standard form is executed and bytes 23:8 of the XSAVE header are not all zero.\r\n If the compacted form is executed and a bit in XCR0 is 0 and the corresponding bit in the\r\n XCOMP_BV field of the XSAVE header is 1.\r\n If the compacted form is executed and a bit in the XCOMP_BV field in the XSAVE header is 0\r\n and the corresponding bit in the XSTATE_BV field is 1.\r\n If the compacted form is executed and bytes 63:16 of the XSAVE header are not all zero.\r\n If attempting to write any reserved bits of the MXCSR register with 1.\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#NM If CR0.TS[bit 3] = 1.\r\n#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0.\r\n If CR4.OSXSAVE[bit 18] = 0.\r\n If any of the LOCK, 66H, F3H or F2H prefixes is used.\r\n#AC If this exception is disabled a general protection exception (#GP) is signaled if the memory\r\n operand is not aligned on a 16-byte boundary, as described above. If the alignment check\r\n exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may\r\n vary with implementation, as follows. In all implementations where #AC is not signaled, a\r\n general protection exception is signaled in its place. In addition, the width of the alignment\r\n check may also vary with implementation. For instance, for a given implementation, an align-\r\n ment check exception might be signaled for a 2-byte misalignment, whereas a general protec-\r\n tion exception might be signaled for all other misalignments (4-, 8-, or 16-byte\r\n misalignments).\r\n\r\n\r\n\r\n\r\n",
"mnem": "XRSTOR"
},
{
"description": "XRSTORS-Restore Processor Extended States Supervisor\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F C7 /3 XRSTORS mem M Valid Valid Restore state components specified by\r\n EDX:EAX from mem.\r\n REX.W+ 0F C7 /3 XRSTORS64 mem M Valid N.E. Restore state components specified by\r\n EDX:EAX from mem.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (r) NA NA NA\r\n\r\n\r\nDescription\r\nPerforms a full or partial restore of processor state components from the XSAVE area located at the memory\r\naddress specified by the source operand. The implicit EDX:EAX register pair specifies a 64-bit instruction mask. The\r\nspecific state components restored correspond to the bits set in the requested-feature bitmap (RFBM), which is the\r\nlogical-AND of EDX:EAX and the logical-OR of XCR0 with the IA32_XSS MSR. XRSTORS may be executed only if\r\nCPL = 0.\r\nThe format of the XSAVE area is detailed in Section 13.4, \"XSAVE Area,\" of Intel 64 and IA-32 Architectures Soft-\r\nware Developer's Manual, Volume 1.\r\nSection 13.12, \"Operation of XRSTORS,\" of Intel 64 and IA-32 Architectures Software Developer's Manual,\r\nVolume 1 provides a detailed description of the operation of the XRSTOR instruction. The following items provide a\r\nhigh-level outline:\r\n. Execution of XRSTORS is similar to that of the compacted form of XRSTOR; XRSTORS cannot restore from an\r\n XSAVE area in which the extended region is in the standard format (see Section 13.4.3, \"Extended Region of an\r\n XSAVE Area\").\r\n. XRSTORS differs from XRSTOR in that it can restore state components corresponding to bits set in the\r\n IA32_XSS MSR.\r\n. If RFBM[i] = 0, XRSTORS does not update state component i.\r\n. If RFBM[i] = 1 and bit i is clear in the XSTATE_BV field in the XSAVE header, XRSTORS initializes state\r\n component i.\r\n. If RFBM[i] = 1 and XSTATE_BV[i] = 1, XRSTORS loads state component i from the XSAVE area.\r\n. If XRSTORS attempts to load MXCSR with an illegal value, a general-protection exception (#GP) occurs.\r\n. XRSTORS loads the internal value XRSTOR_INFO, which may be used to optimize a subsequent execution of\r\n XSAVEOPT or XSAVES.\r\n. Immediately following an execution of XRSTORS, the processor tracks as in-use (not in initial configuration)\r\n any state component i for which RFBM[i] = 1 and XSTATE_BV[i] = 1; it tracks as modified any state component\r\n i for which RFBM[i] = 0.\r\nUse of a source operand not aligned to 64-byte boundary (for 64-bit and 32-bit modes) results in a general-protec-\r\ntion (#GP) exception. In 64-bit mode, the upper 32 bits of RDX and RAX are ignored.\r\n\r\nOperation\r\n\r\nRFBM <- (XCR0 OR IA32_XSS) AND EDX:EAX; /* bitwise logical OR and AND */\r\nCOMPMASK <- XCOMP_BV field from XSAVE header;\r\nRSTORMASK <- XSTATE_BV field from XSAVE header;\r\nIF in VMX non-root operation\r\n THEN VMXNR <- 1;\r\n ELSE VMXNR <- 0;\r\nFI;\r\n\r\n\r\nLAXA <- linear address of XSAVE area;\r\n\r\nIf RFBM[0] = 1\r\n THEN\r\n IF RSTORMASK[0] = 1\r\n THEN load x87 state from legacy region of XSAVE area;\r\n ELSE initialize x87 state;\r\n FI;\r\nFI;\r\nIf RFBM[1] = 1\r\n THEN\r\n IF RSTORMASK[1] = 1\r\n THEN load SSE state from legacy region of XSAVE area;\r\n ELSE initialize SSE state;\r\n FI;\r\nFI;\r\nIf RFBM[2] = 1\r\n THEN\r\n IF RSTORMASK[2] = 1\r\n THEN load AVX state from extended region (compacted format) of XSAVE area;\r\n ELSE initialize AVX state;\r\n FI;\r\nFI;\r\nXRSTOR_INFO <- (CPL,VMXNR,LAXA,COMPMASK);\r\n\r\nFlags Affected\r\nNone.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nXRSTORS: void _xrstors( void * , unsigned __int64);\r\nXRSTORS64: void _xrstors64( void * , unsigned __int64);\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If CPL > 0.\r\n If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If a memory operand is not aligned on a 64-byte boundary, regardless of segment.\r\n If bit 63 of the XCOMP_BV field of the XSAVE header is 0.\r\n If a bit in XCR0 is 0 and the corresponding bit in the XCOMP_BV field of the XSAVE header is 1.\r\n If a bit in the XCOMP_BV field in the XSAVE header is 0 and the corresponding bit in the\r\n XSTATE_BV field is 1.\r\n If bytes 63:16 of the XSAVE header are not all zero.\r\n If attempting to write any reserved bits of the MXCSR register with 1.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#NM If CR0.TS[bit 3] = 1.\r\n#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSS[bit 3] = 0.\r\n If CR4.OSXSAVE[bit 18] = 0.\r\n If any of the LOCK, 66H, F3H or F2H prefixes is used.\r\n#AC If this exception is disabled a general protection exception (#GP) is signaled if the memory\r\n operand is not aligned on a 16-byte boundary, as described above. If the alignment check\r\n\r\n\r\n\r\n exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may\r\n vary with implementation, as follows. In all implementations where #AC is not signaled, a #GP\r\n is signaled in its place. In addition, the width of the alignment check may also vary with imple-\r\n mentation. For instance, for a given implementation, an alignment check exception might be\r\n signaled for a 2-byte misalignment, whereas a #GP might be signaled for all other misalign-\r\n ments (4-, 8-, or 16-byte misalignments).\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand is not aligned on a 64-byte boundary, regardless of segment.\r\n If any part of the operand lies outside the effective address space from 0 to FFFFH.\r\n If bit 63 of the XCOMP_BV field of the XSAVE header is 0.\r\n If a bit in XCR0 is 0 and the corresponding bit in the XCOMP_BV field of the XSAVE header is 1.\r\n If a bit in the XCOMP_BV field in the XSAVE header is 0 and the corresponding bit in the\r\n XSTATE_BV field is 1.\r\n If bytes 63:16 of the XSAVE header are not all zero.\r\n If attempting to write any reserved bits of the MXCSR register with 1.\r\n#NM If CR0.TS[bit 3] = 1.\r\n#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSS[bit 3] = 0.\r\n If CR4.OSXSAVE[bit 18] = 0.\r\n If any of the LOCK, 66H, F3H or F2H prefixes is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If CPL > 0.\r\n If a memory address is in a non-canonical form.\r\n If a memory operand is not aligned on a 64-byte boundary, regardless of segment.\r\n If bit 63 of the XCOMP_BV field of the XSAVE header is 0.\r\n If a bit in XCR0 is 0 and the corresponding bit in the XCOMP_BV field of the XSAVE header is 1.\r\n If a bit in the XCOMP_BV field in the XSAVE header is 0 and the corresponding bit in the\r\n XSTATE_BV field is 1.\r\n If bytes 63:16 of the XSAVE header are not all zero.\r\n If attempting to write any reserved bits of the MXCSR register with 1.\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#NM If CR0.TS[bit 3] = 1.\r\n#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSS[bit 3] = 0.\r\n If CR4.OSXSAVE[bit 18] = 0.\r\n If any of the LOCK, 66H, F3H or F2H prefixes is used.\r\n#AC If this exception is disabled a general protection exception (#GP) is signaled if the memory\r\n operand is not aligned on a 16-byte boundary, as described above. If the alignment check\r\n exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may\r\n vary with implementation, as follows. In all implementations where #AC is not signaled, a\r\n general protection exception is signaled in its place. In addition, the width of the alignment\r\n check may also vary with implementation. For instance, for a given implementation, an align-\r\n ment check exception might be signaled for a 2-byte misalignment, whereas a general protec-\r\n\r\n\r\n\r\n tion exception might be signaled for all other misalignments (4-, 8-, or 16-byte\r\n misalignments).\r\n\r\n\r\n\r\n\r\n",
"mnem": "XRSTORS"
},
{
"description": "XSAVE-Save Processor Extended States\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F AE /4 XSAVE mem M Valid Valid Save state components specified by EDX:EAX\r\n to mem.\r\n REX.W+ 0F AE /4 XSAVE64 mem M Valid N.E. Save state components specified by EDX:EAX\r\n to mem.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (w) NA NA NA\r\n\r\n\r\nDescription\r\nPerforms a full or partial save of processor state components to the XSAVE area located at the memory address\r\nspecified by the destination operand. The implicit EDX:EAX register pair specifies a 64-bit instruction mask. The\r\nspecific state components saved correspond to the bits set in the requested-feature bitmap (RFBM), which is the\r\nlogical-AND of EDX:EAX and XCR0.\r\nThe format of the XSAVE area is detailed in Section 13.4, \"XSAVE Area,\" of Intel 64 and IA-32 Architectures Soft-\r\nware Developer's Manual, Volume 1.\r\nSection 13.7, \"Operation of XSAVE,\" of Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1\r\nprovides a detailed description of the operation of the XSAVE instruction. The following items provide a high-level\r\noutline:\r\n. XSAVE saves state component i if and only if RFBM[i] = 1.1\r\n. XSAVE does not modify bytes 511:464 of the legacy region of the XSAVE area (see Section 13.4.1, \"Legacy\r\n Region of an XSAVE Area\").\r\n. XSAVE reads the XSTATE_BV field of the XSAVE header (see Section 13.4.2, \"XSAVE Header\") and writes a\r\n modified value back to memory as follows. If RFBM[i] = 1, XSAVE writes XSTATE_BV[i] with the value of\r\n XINUSE[i]. (XINUSE is a bitmap by which the processor tracks the status of various state components. See\r\n Section 13.6, \"Processor Tracking of XSAVE-Managed State.\") If RFBM[i] = 0, XSAVE writes XSTATE_BV[i] with\r\n the value that it read from memory (it does not modify the bit). XSAVE does not write to any part of the XSAVE\r\n header other than the XSTATE_BV field.\r\n. XSAVE always uses the standard format of the extended region of the XSAVE area (see Section 13.4.3,\r\n \"Extended Region of an XSAVE Area\").\r\nUse of a destination operand not aligned to 64-byte boundary (in either 64-bit or 32-bit modes) results in a\r\ngeneral-protection (#GP) exception. In 64-bit mode, the upper 32 bits of RDX and RAX are ignored.\r\n\r\nOperation\r\n\r\nRFBM <- XCR0 AND EDX:EAX; /* bitwise logical AND */\r\nOLD_BV <- XSTATE_BV field from XSAVE header;\r\n\r\nIF RFBM[0] = 1\r\n THEN store x87 state into legacy region of XSAVE area;\r\nFI;\r\nIF RFBM[1] = 1\r\n THEN store XMM registers into legacy region of XSAVE area;\r\nFI;\r\n\r\n\r\n1. An exception is made for MXCSR and MXCSR_MASK, which belong to state component 1 - SSE. XSAVE saves these values to mem-\r\n ory if either RFBM[1] or RFBM[2] is 1.\r\n\r\n\r\n\r\nIF RFBM[2] = 1\r\n THEN store AVX state into extended region of XSAVE area;\r\nFI;\r\nIF RFBM[1] = 1 or RFBM[2] = 1\r\n THEN store MXCSR and MXCSR_MASK into legacy region of XSAVE area;\r\nFI;\r\n\r\nXSTATE_BV field in XSAVE header <- (OLD_BV AND ~RFBM) OR (XINUSE AND RFBM);\r\n\r\nFlags Affected\r\nNone.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nXSAVE: void _xsave( void * , unsigned __int64);\r\nXSAVE: void _xsave64( void * , unsigned __int64);\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If a memory operand is not aligned on a 64-byte boundary, regardless of segment.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#NM If CR0.TS[bit 3] = 1.\r\n#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0.\r\n If CR4.OSXSAVE[bit 18] = 0.\r\n If any of the LOCK, 66H, F3H or F2H prefixes is used.\r\n#AC If this exception is disabled a general protection exception (#GP) is signaled if the memory\r\n operand is not aligned on a 16-byte boundary, as described above. If the alignment check\r\n exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may\r\n vary with implementation, as follows. In all implementations where #AC is not signaled, a\r\n general protection exception is signaled in its place. In addition, the width of the alignment\r\n check may also vary with implementation. For instance, for a given implementation, an align-\r\n ment check exception might be signaled for a 2-byte misalignment, whereas a general protec-\r\n tion exception might be signaled for all other misalignments (4-, 8-, or 16-byte\r\n misalignments).\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand is not aligned on a 64-byte boundary, regardless of segment.\r\n If any part of the operand lies outside the effective address space from 0 to FFFFH.\r\n#NM If CR0.TS[bit 3] = 1.\r\n#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0.\r\n If CR4.OSXSAVE[bit 18] = 0.\r\n If any of the LOCK, 66H, F3H or F2H prefixes is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the memory address is in a non-canonical form.\r\n If a memory operand is not aligned on a 64-byte boundary, regardless of segment.\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#NM If CR0.TS[bit 3] = 1.\r\n#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0.\r\n If CR4.OSXSAVE[bit 18] = 0.\r\n If any of the LOCK, 66H, F3H or F2H prefixes is used.\r\n#AC If this exception is disabled a general protection exception (#GP) is signaled if the memory\r\n operand is not aligned on a 16-byte boundary, as described above. If the alignment check\r\n exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may\r\n vary with implementation, as follows. In all implementations where #AC is not signaled, a\r\n general protection exception is signaled in its place. In addition, the width of the alignment\r\n check may also vary with implementation. For instance, for a given implementation, an align-\r\n ment check exception might be signaled for a 2-byte misalignment, whereas a general protec-\r\n tion exception might be signaled for all other misalignments (4-, 8-, or 16-byte\r\n misalignments).\r\n\r\n\r\n\r\n\r\n",
"mnem": "XSAVE"
},
{
"description": "XSAVEC-Save Processor Extended States with Compaction\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F C7 /4 XSAVEC mem M Valid Valid Save state components specified by EDX:EAX\r\n to mem with compaction.\r\n REX.W+ 0F C7 /4 XSAVEC64 mem M Valid N.E. Save state components specified by EDX:EAX\r\n to mem with compaction.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (w) NA NA NA\r\n\r\n\r\nDescription\r\nPerforms a full or partial save of processor state components to the XSAVE area located at the memory address\r\nspecified by the destination operand. The implicit EDX:EAX register pair specifies a 64-bit instruction mask. The\r\nspecific state components saved correspond to the bits set in the requested-feature bitmap (RFBM), which is the\r\nlogical-AND of EDX:EAX and XCR0.\r\nThe format of the XSAVE area is detailed in Section 13.4, \"XSAVE Area,\" of Intel 64 and IA-32 Architectures Soft-\r\nware Developer's Manual, Volume 1.\r\nSection 13.10, \"Operation of XSAVEC,\" of Intel 64 and IA-32 Architectures Software Developer's Manual, Volume\r\n1 provides a detailed description of the operation of the XSAVEC instruction. The following items provide a high-\r\nlevel outline:\r\n. Execution of XSAVEC is similar to that of XSAVE. XSAVEC differs from XSAVE in that it uses compaction and that\r\n it may use the init optimization.\r\n. XSAVEC saves state component i if and only if RFBM[i] = 1 and XINUSE[i] = 1.1 (XINUSE is a bitmap by which\r\n the processor tracks the status of various state components. See Section 13.6, \"Processor Tracking of XSAVE-\r\n Managed State.\")\r\n. XSAVEC does not modify bytes 511:464 of the legacy region of the XSAVE area (see Section 13.4.1, \"Legacy\r\n Region of an XSAVE Area\").\r\n. XSAVEC writes the logical AND of RFBM and XINUSE to the XSTATE_BV field of the XSAVE header.2,3 (See\r\n Section 13.4.2, \"XSAVE Header.\") XSAVEC sets bit 63 of the XCOMP_BV field and sets bits 62:0 of that field to\r\n RFBM[62:0]. XSAVEC does not write to any parts of the XSAVE header other than the XSTATE_BV and\r\n XCOMP_BV fields.\r\n. XSAVEC always uses the compacted format of the extended region of the XSAVE area (see Section 13.4.3,\r\n \"Extended Region of an XSAVE Area\").\r\nUse of a destination operand not aligned to 64-byte boundary (in either 64-bit or 32-bit modes) results in a\r\ngeneral-protection (#GP) exception. In 64-bit mode, the upper 32 bits of RDX and RAX are ignored.\r\n\r\nOperation\r\n\r\nRFBM <- XCR0 AND EDX:EAX; /* bitwise logical AND */\r\nCOMPMASK <- RFBM OR 80000000_00000000H;\r\n\r\nIF RFBM[0] = 1 and XINUSE[0] = 1\r\n\r\n1. There is an exception for state component 1 (SSE). MXCSR is part of SSE state, but XINUSE[1] may be 0 even if MXCSR does not\r\n have its initial value of 1F80H. In this case, XSAVEC saves SSE state as long as RFBM[1] = 1.\r\n2. Unlike XSAVE and XSAVEOPT, XSAVEC clears bits in the XSTATE_BV field that correspond to bits that are clear in RFBM.\r\n3. There is an exception for state component 1 (SSE). MXCSR is part of SSE state, but XINUSE[1] may be 0 even if MXCSR does not\r\n have its initial value of 1F80H. In this case, XSAVEC sets XSTATE_BV[1] to 1 as long as RFBM[1] = 1.\r\n\r\n\r\n\r\n THEN store x87 state into legacy region of XSAVE area;\r\nFI;\r\nIF RFBM[1] = 1 and (XINUSE[1] = 1 or MXCSR != 1F80H)\r\n THEN store SSE state into legacy region of XSAVE area;\r\nFI;\r\nIF RFBM[2] = 1 AND XINUSE[2] = 1\r\n THEN store AVX state into extended region of XSAVE area;\r\nFI;\r\n\r\nXSTATE_BV field in XSAVE header <- XINUSE AND RFBM;1\r\nXCOMP_BV field in XSAVE header <- COMPMASK;\r\n\r\nFlags Affected\r\nNone.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nXSAVEC: void _xsavec( void * , unsigned __int64);\r\nXSAVEC64: void _xsavec64( void * , unsigned __int64);\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If a memory operand is not aligned on a 64-byte boundary, regardless of segment.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#NM If CR0.TS[bit 3] = 1.\r\n#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit 1] = 0.\r\n If CR4.OSXSAVE[bit 18] = 0.\r\n If any of the LOCK, 66H, F3H or F2H prefixes is used.\r\n#AC If this exception is disabled a general protection exception (#GP) is signaled if the memory\r\n operand is not aligned on a 16-byte boundary, as described above. If the alignment check\r\n exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may\r\n vary with implementation, as follows. In all implementations where #AC is not signaled, a\r\n general protection exception is signaled in its place. In addition, the width of the alignment\r\n check may also vary with implementation. For instance, for a given implementation, an align-\r\n ment check exception might be signaled for a 2-byte misalignment, whereas a general protec-\r\n tion exception might be signaled for all other misalignments (4-, 8-, or 16-byte\r\n misalignments).\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand is not aligned on a 64-byte boundary, regardless of segment.\r\n If any part of the operand lies outside the effective address space from 0 to FFFFH.\r\n#NM If CR0.TS[bit 3] = 1.\r\n#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit 1] = 0.\r\n If CR4.OSXSAVE[bit 18] = 0.\r\n If any of the LOCK, 66H, F3H or F2H prefixes is used.\r\n\r\n\r\n\r\n\r\n1. If MXCSR does not have its initial value of 1F80H, XSAVEC sets XSTATE_BV[1] to 1 as long as RFBM[1] = 1, regardless of the value\r\n of XINUSE[1].\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the memory address is in a non-canonical form.\r\n If a memory operand is not aligned on a 64-byte boundary, regardless of segment.\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#NM If CR0.TS[bit 3] = 1.\r\n#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit 1] = 0.\r\n If CR4.OSXSAVE[bit 18] = 0.\r\n If any of the LOCK, 66H, F3H or F2H prefixes is used.\r\n#AC If this exception is disabled a general protection exception (#GP) is signaled if the memory\r\n operand is not aligned on a 16-byte boundary, as described above. If the alignment check\r\n exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may\r\n vary with implementation, as follows. In all implementations where #AC is not signaled, a\r\n general protection exception is signaled in its place. In addition, the width of the alignment\r\n check may also vary with implementation. For instance, for a given implementation, an align-\r\n ment check exception might be signaled for a 2-byte misalignment, whereas a general protec-\r\n tion exception might be signaled for all other misalignments (4-, 8-, or 16-byte\r\n misalignments).\r\n\r\n\r\n\r\n\r\n",
"mnem": "XSAVEC"
},
{
"description": "XSAVEOPT-Save Processor Extended States Optimized\r\nOpcode/ Op/ 64/32 bit CPUID Description\r\nInstruction En Mode Feature\r\n Support Flag\r\n0F AE /6 M V/V XSAVEOPT Save state components specified by EDX:EAX\r\nXSAVEOPT mem to mem, optimizing if possible.\r\n\r\nREX.W + 0F AE /6 M V/V XSAVEOPT Save state components specified by EDX:EAX\r\nXSAVEOPT64 mem to mem, optimizing if possible.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (w) NA NA NA\r\n\r\n\r\nDescription\r\nPerforms a full or partial save of processor state components to the XSAVE area located at the memory address\r\nspecified by the destination operand. The implicit EDX:EAX register pair specifies a 64-bit instruction mask. The\r\nspecific state components saved correspond to the bits set in the requested-feature bitmap (RFBM), which is the\r\nlogical-AND of EDX:EAX and XCR0.\r\nThe format of the XSAVE area is detailed in Section 13.4, \"XSAVE Area,\" of Intel 64 and IA-32 Architectures Soft-\r\nware Developer's Manual, Volume 1.\r\nSection 13.9, \"Operation of XSAVEOPT,\" of Intel 64 and IA-32 Architectures Software Developer's Manual,\r\nVolume 1 provides a detailed description of the operation of the XSAVEOPT instruction. The following items provide\r\na high-level outline:\r\n. Execution of XSAVEOPT is similar to that of XSAVE. XSAVEOPT differs from XSAVE in that it uses compaction\r\n and that it may use the init and modified optimizations. The performance of XSAVEOPT will be equal to or better\r\n than that of XSAVE.\r\n. XSAVEOPT saves state component i only if RFBM[i] = 1 and XINUSE[i] = 1.1 (XINUSE is a bitmap by which the\r\n processor tracks the status of various state components. See Section 13.6, \"Processor Tracking of XSAVE-\r\n Managed State.\") Even if both bits are 1, XSAVEOPT may optimize and not save state component i if (1) state\r\n component i has not been modified since the last execution of XRTOR or XRSTORS; and (2) this execution of\r\n XSAVES corresponds to that last execution of XRTOR or XRSTORS as determined by the internal value\r\n XRSTOR_INFO (see the Operation section below).\r\n. XSAVEOPT does not modify bytes 511:464 of the legacy region of the XSAVE area (see Section 13.4.1, \"Legacy\r\n Region of an XSAVE Area\").\r\n. XSAVEOPT reads the XSTATE_BV field of the XSAVE header (see Section 13.4.2, \"XSAVE Header\") and writes a\r\n modified value back to memory as follows. If RFBM[i] = 1, XSAVEOPT writes XSTATE_BV[i] with the value of\r\n XINUSE[i]. If RFBM[i] = 0, XSAVEOPT writes XSTATE_BV[i] with the value that it read from memory (it does\r\n not modify the bit). XSAVEOPT does not write to any part of the XSAVE header other than the XSTATE_BV field.\r\n. XSAVEOPT always uses the standard format of the extended region of the XSAVE area (see Section 13.4.3,\r\n \"Extended Region of an XSAVE Area\").\r\nUse of a destination operand not aligned to 64-byte boundary (in either 64-bit or 32-bit modes) will result in a\r\ngeneral-protection (#GP) exception. In 64-bit mode, the upper 32 bits of RDX and RAX are ignored.\r\n\r\nOperation\r\n\r\nRFBM <- XCR0 AND EDX:EAX; /* bitwise logical AND */\r\nOLD_BV <- XSTATE_BV field from XSAVE header;\r\n\r\n\r\n1. There is an exception made for MXCSR and MXCSR_MASK, which belong to state component 1 - SSE. XSAVEOPT always saves\r\n these to memory if RFBM[1] = 1 or RFBM[2] = 1, regardless of the value of XINUSE.\r\n\r\n\r\n\r\nIF in VMX non-root operation\r\n THEN VMXNR <- 1;\r\n ELSE VMXNR <- 0;\r\nFI;\r\nLAXA <- linear address of XSAVE area;\r\nCOMPMASK <- 00000000_00000000H;\r\nIF XRSTOR_INFO = (CPL,VMXNR,LAXA,COMPMASK)\r\n THEN MODOPT <- 1;\r\n ELSE MODOPT <- 0;\r\nFI;\r\n\r\nIF RFBM[0] = 1 and XINUSE[0] = 1\r\n THEN store x87 state into legacy region of XSAVE area;\r\n /* might avoid saving if x87 state is not modified and MODOPT = 1 */\r\nFI;\r\nIF RFBM[1] = 1 and XINUSE[1]\r\n THEN store XMM registers into legacy region of XSAVE area;\r\n /* might avoid saving if XMM registers are not modified and MODOPT = 1 */\r\nFI;\r\nIF RFBM[2] = 1 AND XINUSE[2] = 1\r\n THEN store AVX state into extended region of XSAVE area;\r\n /* might avoid saving if AVX state is not modified and MODOPT = 1 */\r\nFI;\r\nIF RFBM[1] = 1 or RFBM[2] = 1\r\n THEN store MXCSR and MXCSR_MASK into legacy region of XSAVE area;\r\nFI;\r\n\r\nXSTATE_BV field in XSAVE header <- (OLD_BV AND ~RFBM) OR (XINUSE AND RFBM);\r\n\r\nFlags Affected\r\nNone.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nXSAVEOPT: void _xsaveopt( void * , unsigned __int64);\r\nXSAVEOPT: void _xsaveopt64( void * , unsigned __int64);\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If a memory operand is not aligned on a 64-byte boundary, regardless of segment.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#NM If CR0.TS[bit 3] = 1.\r\n#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSAVEOPT[bit 0] =\r\n 0.\r\n If CR4.OSXSAVE[bit 18] = 0.\r\n If the LOCK prefix is used.\r\n If 66H, F3H or F2H prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand is not aligned on a 64-byte boundary, regardless of segment.\r\n If any part of the operand lies outside the effective address space from 0 to FFFFH.\r\n\r\n\r\n\r\n#NM If CR0.TS[bit 3] = 1.\r\n#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSAVEOPT[bit 0] =\r\n 0.\r\n If CR4.OSXSAVE[bit 18] = 0.\r\n If the LOCK prefix is used.\r\n If 66H, F3H or F2H prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#GP(0) If the memory address is in a non-canonical form.\r\n If a memory operand is not aligned on a 64-byte boundary, regardless of segment.\r\n#PF(fault-code) If a page fault occurs.\r\n#NM If CR0.TS[bit 3] = 1.\r\n#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSAVEOPT[bit 0] =\r\n 0.\r\n If CR4.OSXSAVE[bit 18] = 0.\r\n If the LOCK prefix is used.\r\n If 66H, F3H or F2H prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "XSAVEOPT"
},
{
"description": "XSAVES-Save Processor Extended States Supervisor\r\n Opcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n 0F C7 /5 XSAVES mem M Valid Valid Save state components specified by EDX:EAX\r\n to mem with compaction, optimizing if\r\n possible.\r\n REX.W+ 0F C7 /5 XSAVES64 mem M Valid N.E. Save state components specified by EDX:EAX\r\n to mem with compaction, optimizing if\r\n possible.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n M ModRM:r/m (w) NA NA NA\r\n\r\n\r\nDescription\r\nPerforms a full or partial save of processor state components to the XSAVE area located at the memory address\r\nspecified by the destination operand. The implicit EDX:EAX register pair specifies a 64-bit instruction mask. The\r\nspecific state components saved correspond to the bits set in the requested-feature bitmap (RFBM), the logical-\r\nAND of EDX:EAX and the logical-OR of XCR0 with the IA32_XSS MSR. XSAVES may be executed only if CPL = 0.\r\nThe format of the XSAVE area is detailed in Section 13.4, \"XSAVE Area,\" of Intel 64 and IA-32 Architectures Soft-\r\nware Developer's Manual, Volume 1.\r\nSection 13.11, \"Operation of XSAVES,\" of Intel 64 and IA-32 Architectures Software Developer's Manual, Volume\r\n1 provides a detailed description of the operation of the XSAVES instruction. The following items provide a high-\r\nlevel outline:\r\n. Execution of XSAVES is similar to that of XSAVEC. XSAVES differs from XSAVEC in that it can save state\r\n components corresponding to bits set in the IA32_XSS MSR and that it may use the modified optimization.\r\n. XSAVES saves state component i only if RFBM[i] = 1 and XINUSE[i] = 1.1 (XINUSE is a bitmap by which the\r\n processor tracks the status of various state components. See Section 13.6, \"Processor Tracking of XSAVE-\r\n Managed State.\") Even if both bits are 1, XSAVES may optimize and not save state component i if (1) state\r\n component i has not been modified since the last execution of XRTOR or XRSTORS; and (2) this execution of\r\n XSAVES correspond to that last execution of XRTOR or XRSTORS as determined by XRSTOR_INFO (see the\r\n Operation section below).\r\n. XSAVES does not modify bytes 511:464 of the legacy region of the XSAVE area (see Section 13.4.1, \"Legacy\r\n Region of an XSAVE Area\").\r\n. XSAVES writes the logical AND of RFBM and XINUSE to the XSTATE_BV field of the XSAVE header.2 (See Section\r\n 13.4.2, \"XSAVE Header.\") XSAVES sets bit 63 of the XCOMP_BV field and sets bits 62:0 of that field to\r\n RFBM[62:0]. XSAVES does not write to any parts of the XSAVE header other than the XSTATE_BV and\r\n XCOMP_BV fields.\r\n. XSAVES always uses the compacted format of the extended region of the XSAVE area (see Section 13.4.3,\r\n \"Extended Region of an XSAVE Area\").\r\nUse of a destination operand not aligned to 64-byte boundary (in either 64-bit or 32-bit modes) results in a\r\ngeneral-protection (#GP) exception. In 64-bit mode, the upper 32 bits of RDX and RAX are ignored.\r\n\r\n\r\n\r\n\r\n1. There is an exception for state component 1 (SSE). MXCSR is part of SSE state, but XINUSE[1] may be 0 even if MXCSR does not\r\n have its initial value of 1F80H. In this case, the init optimization does not apply and XSAVEC will save SSE state as long as RFBM[1] =\r\n 1 and the modified optimization is not being applied.\r\n2. There is an exception for state component 1 (SSE). MXCSR is part of SSE state, but XINUSE[1] may be 0 even if MXCSR does not\r\n have its initial value of 1F80H. In this case, XSAVES sets XSTATE_BV[1] to 1 as long as RFBM[1] = 1.\r\n\r\n\r\n\r\nOperation\r\n\r\nRFBM <- (XCR0 OR IA32_XSS) AND EDX:EAX; /* bitwise logical OR and AND */\r\nIF in VMX non-root operation\r\n THEN VMXNR <- 1;\r\n ELSE VMXNR <- 0;\r\nFI;\r\nLAXA <- linear address of XSAVE area;\r\nCOMPMASK <- RFBM OR 80000000_00000000H;\r\nIF XRSTOR_INFO = (CPL,VMXNR,LAXA,COMPMASK)\r\n THEN MODOPT <- 1;\r\n ELSE MODOPT <- 0;\r\nFI;\r\n\r\nIF RFBM[0] = 1 and XINUSE[0] = 1\r\n THEN store x87 state into legacy region of XSAVE area;\r\n /* might avoid saving if x87 state is not modified and MODOPT = 1 */\r\nFI;\r\nIF RFBM[1] = 1 and (XINUSE[1] = 1 or MXCSR != 1F80H)\r\n THEN store SSE state into legacy region of XSAVE area;\r\n /* might avoid saving if SSE state is not modified and MODOPT = 1 */\r\nFI;\r\nIF RFBM[2] = 1 AND XINUSE[2] = 1\r\n THEN store AVX state into extended region of XSAVE area;\r\n /* might avoid saving if AVX state is not modified and MODOPT = 1 */\r\nFI;\r\n\r\nXSTATE_BV field in XSAVE header <- XINUSE AND RFBM;1\r\nXCOMP_BV field in XSAVE header <- COMPMASK;\r\n\r\nFlags Affected\r\nNone.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nXSAVES: void _xsaves( void * , unsigned __int64);\r\nXSAVES64: void _xsaves64( void * , unsigned __int64);\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.\r\n If a memory operand is not aligned on a 64-byte boundary, regardless of segment.\r\n#SS(0) If a memory operand effective address is outside the SS segment limit.\r\n#PF(fault-code) If a page fault occurs.\r\n#NM If CR0.TS[bit 3] = 1.\r\n#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSS[bit 3] = 0.\r\n If CR4.OSXSAVE[bit 18] = 0.\r\n If any of the LOCK, 66H, F3H or F2H prefixes is used.\r\n#AC If this exception is disabled a general protection exception (#GP) is signaled if the memory\r\n operand is not aligned on a 16-byte boundary, as described above. If the alignment check\r\n\r\n\r\n1. If MXCSR does not have its initial value of 1F80H, XSAVES sets XSTATE_BV[1] to 1 as long as RFBM[1] = 1, regardless of the value\r\n of XINUSE[1].\r\n\r\n\r\n\r\n exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may\r\n vary with implementation, as follows. In all implementations where #AC is not signaled, a\r\n general protection exception is signaled in its place. In addition, the width of the alignment\r\n check may also vary with implementation. For instance, for a given implementation, an align-\r\n ment check exception might be signaled for a 2-byte misalignment, whereas a general protec-\r\n tion exception might be signaled for all other misalignments (4-, 8-, or 16-byte\r\n misalignments).\r\n\r\nReal-Address Mode Exceptions\r\n#GP If a memory operand is not aligned on a 64-byte boundary, regardless of segment.\r\n If any part of the operand lies outside the effective address space from 0 to FFFFH.\r\n#NM If CR0.TS[bit 3] = 1.\r\n#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSS[bit 3] = 0.\r\n If CR4.OSXSAVE[bit 18] = 0.\r\n If any of the LOCK, 66H, F3H or F2H prefixes is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#GP(0) If the memory address is in a non-canonical form.\r\n If a memory operand is not aligned on a 64-byte boundary, regardless of segment.\r\n#SS(0) If a memory address referencing the SS segment is in a non-canonical form.\r\n#PF(fault-code) If a page fault occurs.\r\n#NM If CR0.TS[bit 3] = 1.\r\n#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSS[bit 3] = 0.\r\n If CR4.OSXSAVE[bit 18] = 0.\r\n If any of the LOCK, 66H, F3H or F2H prefixes is used.\r\n#AC If this exception is disabled a general protection exception (#GP) is signaled if the memory\r\n operand is not aligned on a 16-byte boundary, as described above. If the alignment check\r\n exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may\r\n vary with implementation, as follows. In all implementations where #AC is not signaled, a\r\n general protection exception is signaled in its place. In addition, the width of the alignment\r\n check may also vary with implementation. For instance, for a given implementation, an align-\r\n ment check exception might be signaled for a 2-byte misalignment, whereas a general protec-\r\n tion exception might be signaled for all other misalignments (4-, 8-, or 16-byte\r\n misalignments).\r\n\r\n\r\n\r\n\r\n",
"mnem": "XSAVES"
},
{
"description": "XSETBV-Set Extended Control Register\r\nOpcode Instruction Op/ 64-Bit Compat/ Description\r\n En Mode Leg Mode\r\n0F 01 D1 XSETBV NP Valid Valid Write the value in EDX:EAX to the XCR\r\n specified by ECX.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\n\r\nDescription\r\nWrites the contents of registers EDX:EAX into the 64-bit extended control register (XCR) specified in the ECX\r\nregister. (On processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The\r\ncontents of the EDX register are copied to high-order 32 bits of the selected XCR and the contents of the EAX\r\nregister are copied to low-order 32 bits of the XCR. (On processors that support the Intel 64 architecture, the high-\r\norder 32 bits of each of RAX and RDX are ignored.) Undefined or reserved bits in an XCR should be set to values\r\npreviously read.\r\nThis instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection\r\nexception #GP(0) is generated. Specifying a reserved or unimplemented XCR in ECX will also cause a general\r\nprotection exception. The processor will also generate a general protection exception if software attempts to write\r\nto reserved bits in an XCR.\r\nCurrently, only XCR0 is supported. Thus, all other values of ECX are reserved and will cause a #GP(0). Note that\r\nbit 0 of XCR0 (corresponding to x87 state) must be set to 1; the instruction will cause a #GP(0) if an attempt is\r\nmade to clear this bit. In addition, the instruction causes a #GP(0) if an attempt is made to set XCR0[2] (AVX state)\r\nwhile clearing XCR0[1] (SSE state); it is necessary to set both bits to use AVX instructions; Section 13.3, \"Enabling\r\nthe XSAVE Feature Set and XSAVE-Enabled Features,\" of Intel 64 and IA-32 Architectures Software Developer's\r\nManual, Volume 1.\r\n\r\nOperation\r\nXCR[ECX] <- EDX:EAX;\r\n\r\nFlags Affected\r\nNone.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nXSETBV: void _xsetbv( unsigned int, unsigned __int64);\r\n\r\nProtected Mode Exceptions\r\n#GP(0) If the current privilege level is not 0.\r\n If an invalid XCR is specified in ECX.\r\n If the value in EDX:EAX sets bits that are reserved in the XCR specified by ECX.\r\n If an attempt is made to clear bit 0 of XCR0.\r\n If an attempt is made to set XCR0[2:1] to 10b.\r\n#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0.\r\n If CR4.OSXSAVE[bit 18] = 0.\r\n If the LOCK prefix is used.\r\n If 66H, F3H or F2H prefix is used.\r\n\r\n\r\n\r\n\r\n\r\nReal-Address Mode Exceptions\r\n#GP If an invalid XCR is specified in ECX.\r\n If the value in EDX:EAX sets bits that are reserved in the XCR specified by ECX.\r\n If an attempt is made to clear bit 0 of XCR0.\r\n If an attempt is made to set XCR0[2:1] to 10b.\r\n#UD If CPUID.01H:ECX.XSAVE[bit 26] = 0.\r\n If CR4.OSXSAVE[bit 18] = 0.\r\n If the LOCK prefix is used.\r\n If 66H, F3H or F2H prefix is used.\r\n\r\nVirtual-8086 Mode Exceptions\r\n#GP(0) The XSETBV instruction is not recognized in virtual-8086 mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n64-Bit Mode Exceptions\r\nSame exceptions as in protected mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "XSETBV"
},
{
"description": "XTEST - Test If In Transactional Execution\r\n Opcode/Instruction Op/ 64/32bit CPUID Description\r\n En Mode Feature\r\n Support Flag\r\n 0F 01 D6 A V/V HLE or Test if executing in a transactional region\r\n XTEST RTM\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand2 Operand3 Operand4\r\n A NA NA NA NA\r\n\r\n\r\nDescription\r\nThe XTEST instruction queries the transactional execution status. If the instruction executes inside a transaction-\r\nally executing RTM region or a transactionally executing HLE region, then the ZF flag is cleared, else it is set.\r\n\r\nOperation\r\nXTEST\r\nIF (RTM_ACTIVE = 1 OR HLE_ACTIVE = 1)\r\n THEN\r\n ZF <- 0\r\n ELSE\r\n ZF <- 1\r\nFI;\r\n\r\nFlags Affected\r\nThe ZF flag is cleared if the instruction is executed transactionally; otherwise it is set to 1. The CF, OF, SF, PF, and\r\nAF, flags are cleared.\r\n\r\nIntel C/C++ Compiler Intrinsic Equivalent\r\nXTEST: int _xtest( void );\r\n\r\nSIMD Floating-Point Exceptions\r\nNone\r\n\r\nOther Exceptions\r\n#UD CPUID.(EAX=7, ECX=0):HLE[bit 4] = 0 and CPUID.(EAX=7, ECX=0):RTM[bit 11] = 0.\r\n If LOCK or 66H or F2H or F3H prefix is used.\r\n\r\n\r\n\r\n\r\n",
"mnem": "XTEST"
}
],
"x86-64-brief": [
{
"description": "ascii adjust after addition",
"mnem": "aaa"
},
{
"description": "ascii adjust ax before division",
"mnem": "aad"
},
{
"description": "ascii adjust ax after multiply",
"mnem": "aam"
},
{
"description": "ascii adjust al after subtraction",
"mnem": "aas"
},
{
"description": "add with carry",
"mnem": "adc"
},
{
"description": "unsigned integer addition of two operands with carry flag",
"mnem": "adcx"
},
{
"description": "adds src and dst, stores result on dst",
"mnem": "add"
},
{
"description": "add packed double-fp values",
"mnem": "addpd"
},
{
"description": "add packed single-fp values",
"mnem": "addps"
},
{
"description": "add scalar double-fp values",
"mnem": "addsd"
},
{
"description": "add scalar single-fp values",
"mnem": "addss"
},
{
"description": "packed double-fp add/subtract",
"mnem": "addsubpd"
},
{
"description": "packed single-fp add/subtract",
"mnem": "addsubps"
},
{
"description": "unsigned integer addition of two operands with overflow flag",
"mnem": "adox"
},
{
"description": "perform one round of an AES decryption flow",
"mnem": "aesdec"
},
{
"description": "perform the last round of an AES decryption flow",
"mnem": "aesdeclast"
},
{
"description": "perform one round of an AES encryption flow",
"mnem": "aesenc"
},
{
"description": "perform the last round of an AES encryption flow",
"mnem": "aesenclast"
},
{
"description": "assist in aes Inverse Mix Columns",
"mnem": "aesimc"
},
{
"description": "assist in AES round key generation",
"mnem": "aeskeygenassist"
},
{
"description": "binary and operation between src and dst, stores result on dst",
"mnem": "and"
},
{
"description": "logical and not",
"mnem": "andn"
},
{
"description": "bitwise logical and not of packed double-fp values",
"mnem": "andnpd"
},
{
"description": "bitwise logical and not of packed single-fp values",
"mnem": "andnps"
},
{
"description": "bitwise logical and of packed double-fp values",
"mnem": "andpd"
},
{
"description": "bitwise logical and of packed single-fp values",
"mnem": "andps"
},
{
"description": "adjust rpl field of segment selector",
"mnem": "arpl"
},
{
"description": "bit field extract",
"mnem": "bextr"
},
{
"description": "blend packed double-fp values",
"mnem": "blendpd"
},
{
"description": "blend packed single-fp values",
"mnem": "blendps"
},
{
"description": "variable blend packed double-fp values",
"mnem": "blendvpd"
},
{
"description": "variable blend packed single-fp values",
"mnem": "blendvps"
},
{
"description": "extract lowest set isolated bit",
"mnem": "blsi"
},
{
"description": "get mask up to lowest set bit",
"mnem": "blsmsk"
},
{
"description": "reset lowest set bit",
"mnem": "blsr"
},
{
"description": "check lower bound",
"mnem": "bndcl"
},
{
"description": "check upper bound",
"mnem": "bndcn"
},
{
"description": "check upper bound",
"mnem": "bndcu"
},
{
"description": "load extended bounds using address translation",
"mnem": "bndldx"
},
{
"description": "make bounds",
"mnem": "bndmk"
},
{
"description": "move bounds",
"mnem": "bndmov"
},
{
"description": "store extended bounds using address translation",
"mnem": "bndstx"
},
{
"description": "check array index against bounds",
"mnem": "bound"
},
{
"description": "bit scan forward",
"mnem": "bsf"
},
{
"description": "bit scan reverse",
"mnem": "bsr"
},
{
"description": "byte swap",
"mnem": "bswap"
},
{
"description": "bit test",
"mnem": "bt"
},
{
"description": "bit test and complement",
"mnem": "btc"
},
{
"description": "bit test and reset",
"mnem": "btr"
},
{
"description": "bit test and set",
"mnem": "bts"
},
{
"description": "zero high bits starting with specified bit position",
"mnem": "bzhi"
},
{
"description": "calls a subroutine, push eip into the stack (esp)",
"mnem": "call"
},
{
"description": "call procedure",
"mnem": "callf"
},
{
"description": "convert byte to word",
"mnem": "cbw"
},
{
"description": "sign extends eax into edx (convert doubleword to quadword)",
"mnem": "cdq"
},
{
"description": "sign extend eax into rax",
"mnem": "cdqe"
},
{
"description": "clear ac flag in eflags register",
"mnem": "clac"
},
{
"description": "clear carry flag",
"mnem": "clc"
},
{
"description": "clear direction flag",
"mnem": "cld"
},
{
"description": "flush cache line",
"mnem": "clflush"
},
{
"description": "flush cache line optimized",
"mnem": "clflushopt"
},
{
"description": "clear interrupt flag",
"mnem": "cli"
},
{
"description": "clear task-switched flag in cr0",
"mnem": "clts"
},
{
"description": "complement carry flag",
"mnem": "cmc"
},
{
"description": "conditional move - above/not below nor equal (cf=0 and zf=0)",
"mnem": "cmova"
},
{
"description": "conditional move - above or equal/not below/not carry (cf=0)",
"mnem": "cmovae"
},
{
"description": "conditional move - below/not above nor equal/carry (cf=1)",
"mnem": "cmovb"
},
{
"description": "conditional move - below or equal/not above (cf=1 or zf=1)",
"mnem": "cmovbe"
},
{
"description": "conditional move - carry/below/not above or equal (cf=1)",
"mnem": "cmovc"
},
{
"description": "conditional move - equal/zero (zf=1)",
"mnem": "cmove"
},
{
"description": "conditional move - greater/not less nor equal (zf=0 and sf=of)",
"mnem": "cmovg"
},
{
"description": "conditional move - greater or equal/not less (sf=of)",
"mnem": "cmovge"
},
{
"description": "conditional move - less/not greater nor equal (sf!=of)",
"mnem": "cmovl"
},
{
"description": "conditional move - less or equal/not greater (zf=1 or sf!=of)",
"mnem": "cmovle"
},
{
"description": "conditional move - not above/below or equal (cf=1 or zf=1)",
"mnem": "cmovna"
},
{
"description": "conditional move - not above nor equal/below/carry (cf=1)",
"mnem": "cmovnae"
},
{
"description": "conditional move - not below/above or equal/not carry (cf=0)",
"mnem": "cmovnb"
},
{
"description": "conditional move - not below nor equal/above (cf=0 and zf=0)",
"mnem": "cmovnbe"
},
{
"description": "conditional move - not carry/above or equal/not below (cf=0)",
"mnem": "cmovnc"
},
{
"description": "conditional move - not equal/not zero (zf=0)",
"mnem": "cmovne"
},
{
"description": "conditional move - not greater/less or equal (zf=1 or sf!=of)",
"mnem": "cmovng"
},
{
"description": "conditional move - not greater nor equal/less (sf!=of)",
"mnem": "cmovnge"
},
{
"description": "conditional move - not less/greater or equal (sf=of)",
"mnem": "cmovnl"
},
{
"description": "conditional move - not less nor equal/greater (zf=0 and sf=of)",
"mnem": "cmovnle"
},
{
"description": "conditional move - not overflow (of=0)",
"mnem": "cmovno"
},
{
"description": "conditional move - not parity/parity odd (pf=0)",
"mnem": "cmovnp"
},
{
"description": "conditional move - not sign (sf=0)",
"mnem": "cmovns"
},
{
"description": "conditional move - not zero/not equal (zf=0)",
"mnem": "cmovnz"
},
{
"description": "conditional move - overflow (of=1)",
"mnem": "cmovo"
},
{
"description": "conditional move - parity/parity even (pf=1)",
"mnem": "cmovp"
},
{
"description": "conditional move - parity even/parity (pf=1)",
"mnem": "cmovpe"
},
{
"description": "conditional move - parity odd/not parity (pf=0)",
"mnem": "cmovpo"
},
{
"description": "conditional move - sign (sf=1)",
"mnem": "cmovs"
},
{
"description": "conditional move - zero/equal (zf=1)",
"mnem": "cmovz"
},
{
"description": "compare two operands",
"mnem": "cmp"
},
{
"description": "compare packed double-fp values",
"mnem": "cmppd"
},
{
"description": "compare packed single-fp values",
"mnem": "cmpps"
},
{
"description": "compare string operands",
"mnem": "cmps"
},
{
"description": "cmp DS:[esi], (byte)ES:[edi] (esi++, edi++)",
"mnem": "cmpsb"
},
{
"description": "cmp DS:[esi], (dword)ES:[edi] (esi+=4, edi+=4)/compare scalar double-fp values",
"mnem": "cmpsd"
},
{
"description": "cmp DS:[rsi], (qword)ES:[rdi] (rsi+=8, rdi+=8)",
"mnem": "cmpsq"
},
{
"description": "compare scalar single-fp values",
"mnem": "cmpss"
},
{
"description": "cmp DS:[esi], (word)ES:[edi] (esi+=2, edi+=2)",
"mnem": "cmpsw"
},
{
"description": "compare and exchange",
"mnem": "cmpxchg"
},
{
"description": "compare and exchange bytes",
"mnem": "cmpxchg16b"
},
{
"description": "compare and exchange bytes",
"mnem": "cmpxchg8b"
},
{
"description": "compare scalar ordered double-fp values and set eflags",
"mnem": "comisd"
},
{
"description": "compare scalar ordered single-fp values and set eflags",
"mnem": "comiss"
},
{
"description": "cpu identification",
"mnem": "cpuid"
},
{
"description": "sign extends rax into rdx (convert quadword to double-quadword)",
"mnem": "cqo"
},
{
"description": "accumulate crc32 value",
"mnem": "crc32"
},
{
"description": "cs segment override prefix",
"mnem": "cs"
},
{
"description": "convert packed dw integers to double-fp values",
"mnem": "cvtdq2pd"
},
{
"description": "convert packed dw integers to single-fp values",
"mnem": "cvtdq2ps"
},
{
"description": "convert packed double-fp values to dw integers",
"mnem": "cvtpd2dq"
},
{
"description": "convert packed double-fp values to dw integers",
"mnem": "cvtpd2pi"
},
{
"description": "convert packed double-fp values to single-fp values",
"mnem": "cvtpd2ps"
},
{
"description": "convert packed dw integers to double-fp values",
"mnem": "cvtpi2pd"
},
{
"description": "convert packed dw integers to single-fp values",
"mnem": "cvtpi2ps"
},
{
"description": "convert packed single-fp values to dw integers",
"mnem": "cvtps2dq"
},
{
"description": "convert packed single-fp values to double-fp values",
"mnem": "cvtps2pd"
},
{
"description": "convert packed single-fp values to dw integers",
"mnem": "cvtps2pi"
},
{
"description": "convert scalar double-fp value to dw integer",
"mnem": "cvtsd2si"
},
{
"description": "convert scalar double-fp value to scalar single-fp value",
"mnem": "cvtsd2ss"
},
{
"description": "convert dw integer to scalar double-fp value",
"mnem": "cvtsi2sd"
},
{
"description": "convert dw integer to scalar single-fp value",
"mnem": "cvtsi2ss"
},
{
"description": "convert scalar single-fp value to scalar double-fp value",
"mnem": "cvtss2sd"
},
{
"description": "convert scalar single-fp value to dw integer",
"mnem": "cvtss2si"
},
{
"description": "convert with trunc. packed double-fp values to dw integers",
"mnem": "cvttpd2dq"
},
{
"description": "convert with trunc. packed double-fp values to dw integers",
"mnem": "cvttpd2pi"
},
{
"description": "convert with trunc. packed single-fp values to dw integers",
"mnem": "cvttps2dq"
},
{
"description": "convert with trunc. packed single-fp values to dw integers",
"mnem": "cvttps2pi"
},
{
"description": "conv. with trunc. scalar double-fp value to signed dw int",
"mnem": "cvttsd2si"
},
{
"description": "convert with trunc. scalar single-fp value to dw integer",
"mnem": "cvttss2si"
},
{
"description": "convert word to doubleword",
"mnem": "cwd"
},
{
"description": "convert word to doubleword",
"mnem": "cwde"
},
{
"description": "decimal adjust al after addition",
"mnem": "daa"
},
{
"description": "decimal adjust al after subtraction",
"mnem": "das"
},
{
"description": "decrement by 1",
"mnem": "dec"
},
{
"description": "unsigned divide",
"mnem": "div"
},
{
"description": "divide packed double-fp values",
"mnem": "divpd"
},
{
"description": "divide packed single-fp values",
"mnem": "divps"
},
{
"description": "divide scalar double-fp values",
"mnem": "divsd"
},
{
"description": "divide scalar single-fp values",
"mnem": "divss"
},
{
"description": "dot product of packed double-fp values",
"mnem": "dppd"
},
{
"description": "dot product of packed single-fp values",
"mnem": "dpps"
},
{
"description": "ds segment override prefix",
"mnem": "ds"
},
{
"description": "empty mmx technology state",
"mnem": "emms"
},
{
"description": "alias for push ebp; mov ebp, esp",
"mnem": "enter"
},
{
"description": "es segment override prefix",
"mnem": "es"
},
{
"description": "extract packed single-fp value",
"mnem": "extractps"
},
{
"description": "compute pow(2,x) - 1",
"mnem": "f2xm1"
},
{
"description": "absolute value",
"mnem": "fabs"
},
{
"description": "floating point add",
"mnem": "fadd"
},
{
"description": "floating point add and pop",
"mnem": "faddp"
},
{
"description": "load binary coded decimal",
"mnem": "fbld"
},
{
"description": "store binary coded decimal integer and pop",
"mnem": "fbstp"
},
{
"description": "change sign",
"mnem": "fchs"
},
{
"description": "clear exceptions",
"mnem": "fclex"
},
{
"description": "fp conditional move - below (cf=1)",
"mnem": "fcmovb"
},
{
"description": "fp conditional move - below or equal (cf=1 or zf=1)",
"mnem": "fcmovbe"
},
{
"description": "fp conditional move - equal (zf=1)",
"mnem": "fcmove"
},
{
"description": "fp conditional move - not below (cf=0)",
"mnem": "fcmovnb"
},
{
"description": "fp conditional move - not below or equal (cf=0 and zf=0)",
"mnem": "fcmovnbe"
},
{
"description": "fp conditional move - not equal (zf=0)",
"mnem": "fcmovne"
},
{
"description": "fp conditional move - not unordered (pf=0)",
"mnem": "fcmovnu"
},
{
"description": "fp conditional move - unordered (pf=1)",
"mnem": "fcmovu"
},
{
"description": "floating point compare",
"mnem": "fcom"
},
{
"description": "compare floating point values and set eflags",
"mnem": "fcomi"
},
{
"description": "compare floating point values and set eflags and pop",
"mnem": "fcomip"
},
{
"description": "floating point compare and pop",
"mnem": "fcomp"
},
{
"description": "floating point compare and pop twice",
"mnem": "fcompp"
},
{
"description": "floating point cosine",
"mnem": "fcos"
},
{
"description": "decrement floating point stack pointer",
"mnem": "fdecstp"
},
{
"description": "disable npx (numeric coprocessor extension) interrupt",
"mnem": "fdisi"
},
{
"description": "floating point divide",
"mnem": "fdiv"
},
{
"description": "floting point divide and pop",
"mnem": "fdivp"
},
{
"description": "floating point divide reversed",
"mnem": "fdivr"
},
{
"description": "floating point reverse divide and pop",
"mnem": "fdivrp"
},
{
"description": "enable npx (numeric coprocessor extension) interrupt",
"mnem": "feni"
},
{
"description": "free floating-point register",
"mnem": "ffree"
},
{
"description": "free floating-point register and pop (undocumented)",
"mnem": "ffreep"
},
{
"description": "integer add",
"mnem": "fiadd"
},
{
"description": "integer compare",
"mnem": "ficom"
},
{
"description": "integer compare and pop",
"mnem": "ficomp"
},
{
"description": "integer divide",
"mnem": "fidiv"
},
{
"description": "integer divide reserved",
"mnem": "fidivr"
},
{
"description": "load integer",
"mnem": "fild"
},
{
"description": "integer multiply",
"mnem": "fimul"
},
{
"description": "increment floating-point stack pointer",
"mnem": "fincstp"
},
{
"description": "initialize fpu (floating-point unit)",
"mnem": "finit"
},
{
"description": "store integer",
"mnem": "fist"
},
{
"description": "store integer and pop",
"mnem": "fistp"
},
{
"description": "store integer with truncation and pop",
"mnem": "fisttp"
},
{
"description": "integer substract",
"mnem": "fisub"
},
{
"description": "integer susbtract reversed",
"mnem": "fisubr"
},
{
"description": "load floating point value",
"mnem": "fld"
},
{
"description": "load constant onto stack +1.0f",
"mnem": "fld1"
},
{
"description": "load x87 fpu control word",
"mnem": "fldcw"
},
{
"description": "load x87 fpu environment",
"mnem": "fldenv"
},
{
"description": "load constant onto stack: logarithm base 2 (e)",
"mnem": "fldl2e"
},
{
"description": "load constant onto stack: logarithm base 2 (10)",
"mnem": "fldl2t"
},
{
"description": "load constant onto stack: logarithm base 10 (2)",
"mnem": "fldlg2"
},
{
"description": "load constant onto stack: natural logarithm (2)",
"mnem": "fldln2"
},
{
"description": "load constant onto stack: pi (3.141592...)",
"mnem": "fldpi"
},
{
"description": "load constant onto stack 0.0f",
"mnem": "fldz"
},
{
"description": "floating point multiply",
"mnem": "fmul"
},
{
"description": "floating point multiply and pop",
"mnem": "fmulp"
},
{
"description": "clear exceptions",
"mnem": "fnclex"
},
{
"description": "disable npx (numeric coprocessor extension) interrupts (8087 only, otherwise, FNOP)",
"mnem": "fndisi"
},
{
"description": "enable npx (numeric coprocessor extension) interrupts (8087 only, otherwise, FNOP)",
"mnem": "fneni"
},
{
"description": "initialize fpu (floating-point unit)",
"mnem": "fninit"
},
{
"description": "no operation",
"mnem": "fnop"
},
{
"description": "store x87 fpu state",
"mnem": "fnsave"
},
{
"description": "set protected mode (8087 only, otherwise FNOP)",
"mnem": "fnsetpm"
},
{
"description": "store x87 fpu control word",
"mnem": "fnstcw"
},
{
"description": "store x87 fpu environment",
"mnem": "fnstenv"
},
{
"description": "store x87 fpu status word",
"mnem": "fnstsw"
},
{
"description": "partial arctangent and pop",
"mnem": "fpatan"
},
{
"description": "partial remainder (for compatibility with i8087 and i287)",
"mnem": "fprem"
},
{
"description": "ieee partial remainder",
"mnem": "fprem1"
},
{
"description": "partial tangent",
"mnem": "fptan"
},
{
"description": "round to integer",
"mnem": "frndint"
},
{
"description": "restore x87 fpu state",
"mnem": "frstor"
},
{
"description": "fs segment override prefix",
"mnem": "fs"
},
{
"description": "store x87 fpu state",
"mnem": "fsave"
},
{
"description": "scale",
"mnem": "fscale"
},
{
"description": "set protected mode",
"mnem": "fsetpm"
},
{
"description": "sine",
"mnem": "fsin"
},
{
"description": "sine and cosine",
"mnem": "fsincos"
},
{
"description": "square root",
"mnem": "fsqrt"
},
{
"description": "store floating point value",
"mnem": "fst"
},
{
"description": "store x87 fpu control word",
"mnem": "fstcw"
},
{
"description": "store x87 fpu environment",
"mnem": "fstenv"
},
{
"description": "store floating point value and pop",
"mnem": "fstp"
},
{
"description": "store floating point value and pop (undocumented)",
"mnem": "fstpnce"
},
{
"description": "store x87 fpu status word",
"mnem": "fstsw"
},
{
"description": "floating point subtract",
"mnem": "fsub"
},
{
"description": "subtract and pop",
"mnem": "fsubp"
},
{
"description": "reverse subtract",
"mnem": "fsubr"
},
{
"description": "reverse subtract and pop",
"mnem": "fsubrp"
},
{
"description": "test",
"mnem": "ftst"
},
{
"description": "unordered compare floating point values",
"mnem": "fucom"
},
{
"description": "unordered compare floating point values and set eflags",
"mnem": "fucomi"
},
{
"description": "unordered compare floating point values and set eflags and pop",
"mnem": "fucomip"
},
{
"description": "unordered compare floating point values and pop",
"mnem": "fucomp"
},
{
"description": "unordered compare floating point values and pop twice",
"mnem": "fucompp"
},
{
"description": "check pending unmasked floating-point exceptions",
"mnem": "fwait"
},
{
"description": "examine",
"mnem": "fxam"
},
{
"description": "exchange register contents",
"mnem": "fxch"
},
{
"description": "restore x87 fpu, mmx, xmm, and mxcsr state",
"mnem": "fxrstor"
},
{
"description": "save x87 fpu, mmx, xmm, and mxcsr state",
"mnem": "fxsave"
},
{
"description": "extract exponent and significand",
"mnem": "fxtract"
},
{
"description": "compute y times log2(x) and pop",
"mnem": "fyl2x"
},
{
"description": "compute y times log2(x+1) and pop",
"mnem": "fyl2xp1"
},
{
"description": "getsec leaf functions",
"mnem": "getsec"
},
{
"description": "gs segment override prefix",
"mnem": "gs"
},
{
"description": "packed double-fp horizontal add",
"mnem": "haddpd"
},
{
"description": "packed single-fp horizontal add",
"mnem": "haddps"
},
{
"description": "hintable nop",
"mnem": "hint_nop"
},
{
"description": "stop process until external interrupt received",
"mnem": "hlt"
},
{
"description": "packed double-fp horizontal subtract",
"mnem": "hsubpd"
},
{
"description": "packed single-fp horizontal subtract",
"mnem": "hsubps"
},
{
"description": "Single byte single-step exception / Invoke ICE",
"mnem": "icebp"
},
{
"description": "signed divide",
"mnem": "idiv"
},
{
"description": "signed multiply",
"mnem": "imul"
},
{
"description": "input from port",
"mnem": "in"
},
{
"description": "increment by 1",
"mnem": "inc"
},
{
"description": "input from port to string",
"mnem": "ins"
},
{
"description": "input from port to string",
"mnem": "insb"
},
{
"description": "input from port to string",
"mnem": "insd"
},
{
"description": "insert scalar single-precision floating-point value",
"mnem": "insertps"
},
{
"description": "input from port to string",
"mnem": "insw"
},
{
"description": "call to interrupt procedure",
"mnem": "int"
},
{
"description": "call to interrupt procedure",
"mnem": "int 3"
},
{
"description": "call to interrupt procedure",
"mnem": "int1"
},
{
"description": "int 3, software breakpoint",
"mnem": "int3"
},
{
"description": "call to interrupt if overflow",
"mnem": "into"
},
{
"description": "invalidate internal caches",
"mnem": "invd"
},
{
"description": "invalidate translations derived from ept",
"mnem": "invept"
},
{
"description": "invalidate tlb entry",
"mnem": "invlpg"
},
{
"description": "invalidate process-context identifier",
"mnem": "invpcid"
},
{
"description": "invalidate translations based on vpid",
"mnem": "invvpid"
},
{
"description": "return from interrupt",
"mnem": "iret"
},
{
"description": "interrupt return",
"mnem": "iretd"
},
{
"description": "interrupt return (64 bit)",
"mnem": "iretq"
},
{
"description": "jump short if above (cf=0 and zf=0)",
"mnem": "ja"
},
{
"description": "jump short if above or equal (cf=0)",
"mnem": "jae"
},
{
"description": "jump short if below/not above nor equal/carry (cf=1)",
"mnem": "jb"
},
{
"description": "jump short if below or equal/not above (cf=1 or zf=1)",
"mnem": "jbe"
},
{
"description": "jump short if carry (cf=1)",
"mnem": "jc"
},
{
"description": "jump short if ecx register is 0",
"mnem": "jcxz"
},
{
"description": "jump short if equal (zf=1)",
"mnem": "je"
},
{
"description": "jump short if ecx is 0",
"mnem": "jecxz"
},
{
"description": "jump short if greater (zf=0 and sf=of)",
"mnem": "jg"
},
{
"description": "jump short if greater or equal (sf=of)",
"mnem": "jge"
},
{
"description": "jump short if less/not greater (sf!=of)",
"mnem": "jl"
},
{
"description": "jump short if less or equal/not greater (zf=1 or sf!=of)",
"mnem": "jle"
},
{
"description": "jump",
"mnem": "jmp"
},
{
"description": "jump to ia-64 instruction set",
"mnem": "jmpe"
},
{
"description": "jump",
"mnem": "jmpf"
},
{
"description": "jump short if not above/equal (cf=1 or zf=1)",
"mnem": "jna"
},
{
"description": "jump short if not above nor equal/below (cf=1)",
"mnem": "jnae"
},
{
"description": "jump short if not below/above or equal/not carry (cf=0)",
"mnem": "jnb"
},
{
"description": "jump short if not below or equal/above (cf=0 and zf=0)",
"mnem": "jnbe"
},
{
"description": "jump short if not carry (cf=0)",
"mnem": "jnc"
},
{
"description": "jump short if not equal/not zero (zf=0)",
"mnem": "jne"
},
{
"description": "jump short if not greater/less or equal (zf=1 or sf!=of)",
"mnem": "jng"
},
{
"description": "jump short if not greater/less (sf!=of)",
"mnem": "jnge"
},
{
"description": "jump short if not less/greater or equal (sf=of)",
"mnem": "jnl"
},
{
"description": "jump short if not less nor equal/greater (zf=0 and sf=of)",
"mnem": "jnle"
},
{
"description": "jump short if not overflow (of=0)",
"mnem": "jno"
},
{
"description": "jump short if not parity/parity odd (pf=0)",
"mnem": "jnp"
},
{
"description": "jump short if not sign (sf=0)",
"mnem": "jns"
},
{
"description": "jump short if not zero/not equal (zf=0)",
"mnem": "jnz"
},
{
"description": "jump short if overflow (of=1)",
"mnem": "jo"
},
{
"description": "jump short if parity/parity even (pf=1)",
"mnem": "jp"
},
{
"description": "jump short if parity even/parity (pf=1)",
"mnem": "jpe"
},
{
"description": "jump short if parity odd/not parity (pf=0)",
"mnem": "jpo"
},
{
"description": "jump short if rcx register is 0",
"mnem": "jrcxz"
},
{
"description": "jump short if sign (sf=1)",
"mnem": "js"
},
{
"description": "jump short if zero/equal (zf=1)",
"mnem": "jz"
},
{
"description": "add two masks",
"mnem": "kaddb"
},
{
"description": "add two masks",
"mnem": "kaddd"
},
{
"description": "add two masks",
"mnem": "kaddq"
},
{
"description": "add two masks",
"mnem": "kaddw"
},
{
"description": "bitwise logical and masks",
"mnem": "kandb"
},
{
"description": "bitwise logical and masks",
"mnem": "kandd"
},
{
"description": "bitwise logical and not masks",
"mnem": "kandnb"
},
{
"description": "bitwise logical and not masks",
"mnem": "kandnd"
},
{
"description": "bitwise logical and not masks",
"mnem": "kandnq"
},
{
"description": "bitwise logical and not masks",
"mnem": "kandnw"
},
{
"description": "bitwise logical and masks",
"mnem": "kandq"
},
{
"description": "bitwise logical and masks",
"mnem": "kandw"
},
{
"description": "move from and to mask registers",
"mnem": "kmovb"
},
{
"description": "move from and to mask registers",
"mnem": "kmovd"
},
{
"description": "move from and to mask registers",
"mnem": "kmovq"
},
{
"description": "move from and to mask registers",
"mnem": "kmovw"
},
{
"description": "not mask register",
"mnem": "knotb"
},
{
"description": "not mask register",
"mnem": "knotd"
},
{
"description": "not mask register",
"mnem": "knotq"
},
{
"description": "not mask register",
"mnem": "knotw"
},
{
"description": "bitwise logical or masks",
"mnem": "korb"
},
{
"description": "bitwise logical or masks",
"mnem": "kord"
},
{
"description": "bitwise logical or masks",
"mnem": "korq"
},
{
"description": "or masks and set flags",
"mnem": "kortestb"
},
{
"description": "or masks and set flags",
"mnem": "kortestd"
},
{
"description": "or masks and set flags",
"mnem": "kortestq"
},
{
"description": "or masks and set flags",
"mnem": "kortestw"
},
{
"description": "bitwise logical or masks",
"mnem": "korw"
},
{
"description": "shift left mask registers",
"mnem": "kshiftlb"
},
{
"description": "shift left mask registers",
"mnem": "kshiftld"
},
{
"description": "shift left mask registers",
"mnem": "kshiftlq"
},
{
"description": "shift left mask registers",
"mnem": "kshiftlw"
},
{
"description": "shift right mask registers",
"mnem": "kshiftrb"
},
{
"description": "shift right mask registers",
"mnem": "kshiftrd"
},
{
"description": "shift right mask registers",
"mnem": "kshiftrq"
},
{
"description": "shift right mask registers",
"mnem": "kshiftrw"
},
{
"description": "packed bit test masks and set flags",
"mnem": "ktestb"
},
{
"description": "packed bit test masks and set flags",
"mnem": "ktestd"
},
{
"description": "packed bit test masks and set flags",
"mnem": "ktestq"
},
{
"description": "packed bit test masks and set flags",
"mnem": "ktestw"
},
{
"description": "unpack for mask registers",
"mnem": "kunpckbw"
},
{
"description": "unpack for mask registers",
"mnem": "kunpckdq"
},
{
"description": "unpack for mask registers",
"mnem": "kunpckwd"
},
{
"description": "bitwise logical xnor masks",
"mnem": "kxnorb"
},
{
"description": "bitwise logical xnor masks",
"mnem": "kxnord"
},
{
"description": "bitwise logical xnor masks",
"mnem": "kxnorq"
},
{
"description": "bitwise logical xnor masks",
"mnem": "kxnorw"
},
{
"description": "bitwise logical xor masks",
"mnem": "kxorb"
},
{
"description": "bitwise logical xor masks",
"mnem": "kxord"
},
{
"description": "bitwise logical xor masks",
"mnem": "kxorq"
},
{
"description": "bitwise logical xor masks",
"mnem": "kxorw"
},
{
"description": "load status flags into ah register",
"mnem": "lahf"
},
{
"description": "load acces right byte",
"mnem": "lar"
},
{
"description": "load unaligned integer 128 bits",
"mnem": "lddqu"
},
{
"description": "load mxcsr register",
"mnem": "ldmxcsr"
},
{
"description": "load far pointer",
"mnem": "lds"
},
{
"description": "load effective address",
"mnem": "lea"
},
{
"description": "one byte alias for mov esp, ebp ; pop ebp",
"mnem": "leave"
},
{
"description": "load far pointer",
"mnem": "les"
},
{
"description": "load fence",
"mnem": "lfence"
},
{
"description": "load far pointer",
"mnem": "lfs"
},
{
"description": "load global descriptor table register",
"mnem": "lgdt"
},
{
"description": "load far pointer",
"mnem": "lgs"
},
{
"description": "load interrupt descriptor table register",
"mnem": "lidt"
},
{
"description": "load local descriptor table register",
"mnem": "lldt"
},
{
"description": "load machine status word",
"mnem": "lmsw"
},
{
"description": "load all of the cpu registers",
"mnem": "loadall"
},
{
"description": "loads All Registers from memory address es:edi",
"mnem": "loadalld"
},
{
"description": "instruction prefix to setup the LOCK pin",
"mnem": "lock"
},
{
"description": "load string",
"mnem": "lods"
},
{
"description": "Load string byte",
"mnem": "lodsb"
},
{
"description": "Load string doubleword",
"mnem": "lodsd"
},
{
"description": "Load string quadword",
"mnem": "lodsq"
},
{
"description": "Load string word",
"mnem": "lodsw"
},
{
"description": "decrement count; jump short if ecx!=0",
"mnem": "loop"
},
{
"description": "decrement count; jump short if ecx!=0 and zf=1",
"mnem": "loope"
},
{
"description": "decrement count; jump short if ecx!=0 and zf=0",
"mnem": "loopne"
},
{
"description": "decrement count; jump short if ecx!=0 and zf=0",
"mnem": "loopnz"
},
{
"description": "decrement count; jump short if ecx!=0 and zf=1",
"mnem": "loopz"
},
{
"description": "load segment limit",
"mnem": "lsl"
},
{
"description": "load far pointer",
"mnem": "lss"
},
{
"description": "load task register",
"mnem": "ltr"
},
{
"description": "count the number of leading zero bits",
"mnem": "lzcnt"
},
{
"description": "store selected bytes of double quadword",
"mnem": "maskmovdqu"
},
{
"description": "store selected bytes of quadword",
"mnem": "maskmovq"
},
{
"description": "return maximum packed double-fp values",
"mnem": "maxpd"
},
{
"description": "return maximum packed single-fp values",
"mnem": "maxps"
},
{
"description": "return maximum scalar double-fp value",
"mnem": "maxsd"
},
{
"description": "return maximum scalar single-fp value",
"mnem": "maxss"
},
{
"description": "memory fence",
"mnem": "mfence"
},
{
"description": "return minimum packed double-fp values",
"mnem": "minpd"
},
{
"description": "return minimum packed single-fp values",
"mnem": "minps"
},
{
"description": "return minimum scalar double-fp value",
"mnem": "minsd"
},
{
"description": "return minimum scalar single-fp value",
"mnem": "minss"
},
{
"description": "set up monitor address",
"mnem": "monitor"
},
{
"description": "moves data from src to dst",
"mnem": "mov"
},
{
"description": "absolute data moves",
"mnem": "movabs"
},
{
"description": "move aligned packed double-fp values",
"mnem": "movapd"
},
{
"description": "move aligned packed single-fp values",
"mnem": "movaps"
},
{
"description": "move data after swapping bytes",
"mnem": "movbe"
},
{
"description": "move doubleword",
"mnem": "movd"
},
{
"description": "move one double-fp and duplicate",
"mnem": "movddup"
},
{
"description": "move quadword from xmm to mmx technology register",
"mnem": "movdq2q"
},
{
"description": "move aligned double quadword",
"mnem": "movdqa"
},
{
"description": "move unaligned double quadword",
"mnem": "movdqu"
},
{
"description": "move packed single-fp values high to low",
"mnem": "movhlps"
},
{
"description": "move high packed double-fp value",
"mnem": "movhpd"
},
{
"description": "move high packed single-fp values",
"mnem": "movhps"
},
{
"description": "move packed single-fp values low to high",
"mnem": "movlhps"
},
{
"description": "move low packed double-fp value",
"mnem": "movlpd"
},
{
"description": "move low packed single-fp values",
"mnem": "movlps"
},
{
"description": "extract packed double-fp sign mask",
"mnem": "movmskpd"
},
{
"description": "extract packed single-fp sign mask",
"mnem": "movmskps"
},
{
"description": "store double quadword using non-temporal hint",
"mnem": "movntdq"
},
{
"description": "load double quadword non-temporal aligned hint",
"mnem": "movntdqa"
},
{
"description": "store doubleword using non-temporal hint",
"mnem": "movnti"
},
{
"description": "store packed double-fp values using non-temporal hint",
"mnem": "movntpd"
},
{
"description": "store packed single-fp values using non-temporal hint",
"mnem": "movntps"
},
{
"description": "store of quadword using non-temporal hint",
"mnem": "movntq"
},
{
"description": "move quadword",
"mnem": "movq"
},
{
"description": "move quadword from mmx technology to xmm register",
"mnem": "movq2dq"
},
{
"description": "move data from string to string",
"mnem": "movs"
},
{
"description": "ES:[edi] = (byte)DS:[esi] (esi++, edi++)",
"mnem": "movsb"
},
{
"description": "ES:[edi] = (dword)DS:[esi] (esi+=4, edi+=4)/move scalar double-fp value",
"mnem": "movsd"
},
{
"description": "move packed single-fp high and duplicate",
"mnem": "movshdup"
},
{
"description": "move packed single-fp low and duplicate",
"mnem": "movsldup"
},
{
"description": "ES:[rdi] = (qword)DS:[rsi] (rsi+=8, rdi+=8)",
"mnem": "movsq"
},
{
"description": "move scalar single-fp values",
"mnem": "movss"
},
{
"description": "ES:[edi] = (word)DS:[esi] (esi+=2, edi+=2)",
"mnem": "movsw"
},
{
"description": "move with sign-extension",
"mnem": "movsx"
},
{
"description": "move with sign-extension",
"mnem": "movsxd"
},
{
"description": "move unaligned packed double-fp values",
"mnem": "movupd"
},
{
"description": "move unaligned packed single-fp values",
"mnem": "movups"
},
{
"description": "move dst register size padding with zeroes",
"mnem": "movzx"
},
{
"description": "compute multiple packed sums of absolute difference",
"mnem": "mpsadbw"
},
{
"description": "unsigned multiply",
"mnem": "mul"
},
{
"description": "multiply packed double-fp values",
"mnem": "mulpd"
},
{
"description": "multiply packed single-fp values",
"mnem": "mulps"
},
{
"description": "multiply scalar double-fp values",
"mnem": "mulsd"
},
{
"description": "multiply scalar single-fp value",
"mnem": "mulss"
},
{
"description": "unsigned multiply without affecting flags",
"mnem": "mulx"
},
{
"description": "monitor wait",
"mnem": "mwait"
},
{
"description": "two's complement negation",
"mnem": "neg"
},
{
"description": "no operation",
"mnem": "nop"
},
{
"description": "one's complement negation",
"mnem": "not"
},
{
"description": "logical inclusive or",
"mnem": "or"
},
{
"description": "bitwise logical or of double-fp values",
"mnem": "orpd"
},
{
"description": "bitwise logical or of single-fp values",
"mnem": "orps"
},
{
"description": "output to port",
"mnem": "out"
},
{
"description": "output string to port",
"mnem": "outs"
},
{
"description": "Output string byte to port",
"mnem": "outsb"
},
{
"description": "Output string doubleword to port",
"mnem": "outsd"
},
{
"description": "Output string word to port",
"mnem": "outsw"
},
{
"description": "packed absolute value",
"mnem": "pabsb"
},
{
"description": "packed absolute value",
"mnem": "pabsd"
},
{
"description": "packed absolute value",
"mnem": "pabsq"
},
{
"description": "packed absolute value",
"mnem": "pabsw"
},
{
"description": "pack with signed saturation",
"mnem": "packssdw"
},
{
"description": "pack with signed saturation",
"mnem": "packsswb"
},
{
"description": "pack with unsigned saturation",
"mnem": "packusdw"
},
{
"description": "pack with unsigned saturation",
"mnem": "packuswb"
},
{
"description": "add packed integers",
"mnem": "paddb"
},
{
"description": "add packed integers",
"mnem": "paddd"
},
{
"description": "add packed quadword integers",
"mnem": "paddq"
},
{
"description": "add packed signed integers with signed saturation",
"mnem": "paddsb"
},
{
"description": "add packed signed integers with signed saturation",
"mnem": "paddsw"
},
{
"description": "add packed unsigned integers with unsigned saturation",
"mnem": "paddusb"
},
{
"description": "add packed unsigned integers with unsigned saturation",
"mnem": "paddusw"
},
{
"description": "add packed integers",
"mnem": "paddw"
},
{
"description": "packed align right",
"mnem": "palignr"
},
{
"description": "logical and",
"mnem": "pand"
},
{
"description": "logical and not",
"mnem": "pandn"
},
{
"description": "spin loop hint",
"mnem": "pause"
},
{
"description": "average packed integers",
"mnem": "pavgb"
},
{
"description": "average packed integers",
"mnem": "pavgw"
},
{
"description": "variable blend packed bytes",
"mnem": "pblendvb"
},
{
"description": "blend packed words",
"mnem": "pblendw"
},
{
"description": "performs a carry-less multiplication of two 64-bit polynomials over the finite field GF(2).",
"mnem": "pclmulqdq"
},
{
"description": "compare packed data for equal",
"mnem": "pcmpeqb"
},
{
"description": "compare packed data for equal",
"mnem": "pcmpeqd"
},
{
"description": "compare packed qword data for equal",
"mnem": "pcmpeqq"
},
{
"description": "compare packed data for equal",
"mnem": "pcmpeqw"
},
{
"description": "packed compare explicit length strings, return index",
"mnem": "pcmpestri"
},
{
"description": "packed compare explicit length strings, return mask",
"mnem": "pcmpestrm"
},
{
"description": "compare packed signed integers for greater than",
"mnem": "pcmpgtb"
},
{
"description": "compare packed signed integers for greater than",
"mnem": "pcmpgtd"
},
{
"description": "compare packed data for greater than",
"mnem": "pcmpgtq"
},
{
"description": "compare packed signed integers for greater than",
"mnem": "pcmpgtw"
},
{
"description": "packed compare implicit length strings, return index",
"mnem": "pcmpistri"
},
{
"description": "packed compare implicit length strings, return mask",
"mnem": "pcmpistrm"
},
{
"description": "parallel bits deposit",
"mnem": "pdep"
},
{
"description": "parallel bits extract",
"mnem": "pext"
},
{
"description": "extract a byte from an XMM register and insert the value into a general-purpose register or memory",
"mnem": "pextrb"
},
{
"description": "extract a dword from an XMM register and insert the value into a general-purpose register or memory",
"mnem": "pextrd"
},
{
"description": "extract a qword from an XMM register and insert the value into a general-purpose register or memory",
"mnem": "pextrq"
},
{
"description": "extract a word from an XMM register and insert the value into a general-purpose register or memory",
"mnem": "pextrw"
},
{
"description": "packed horizontal add",
"mnem": "phaddd"
},
{
"description": "packed horizontal add and saturate",
"mnem": "phaddsw"
},
{
"description": "packed horizontal add",
"mnem": "phaddw"
},
{
"description": "packed horizontal word minimum",
"mnem": "phminposuw"
},
{
"description": "packed horizontal subtract",
"mnem": "phsubd"
},
{
"description": "packed horizontal subtract and saturate",
"mnem": "phsubsw"
},
{
"description": "packed horizontal subtract",
"mnem": "phsubw"
},
{
"description": "insert a byte value from a register or memory into an XMM register",
"mnem": "pinsrb"
},
{
"description": "insert a dword value from a register or memory into an XMM register",
"mnem": "pinsrd"
},
{
"description": "insert a qword value from a register or memory into an XMM register",
"mnem": "pinsrq"
},
{
"description": "insert a word value from a register or memory into an XMM register",
"mnem": "pinsrw"
},
{
"description": "multiply and add packed signed and unsigned bytes",
"mnem": "pmaddubsw"
},
{
"description": "multiply and add packed integers",
"mnem": "pmaddwd"
},
{
"description": "maximum of packed signed byte integers",
"mnem": "pmaxsb"
},
{
"description": "maximum of packed signed dword integers",
"mnem": "pmaxsd"
},
{
"description": "maximum of packed signed integers",
"mnem": "pmaxsq"
},
{
"description": "maximum of packed signed word integers",
"mnem": "pmaxsw"
},
{
"description": "maximum of packed unsigned byte integers",
"mnem": "pmaxub"
},
{
"description": "maximum of packed unsigned dword integers",
"mnem": "pmaxud"
},
{
"description": "maximum of packed unsigned integers",
"mnem": "pmaxuq"
},
{
"description": "maximum of packed unsigned word integers",
"mnem": "pmaxuw"
},
{
"description": "minimum of packed signed byte integers",
"mnem": "pminsb"
},
{
"description": "minimum of packed signed dword integers",
"mnem": "pminsd"
},
{
"description": "minimum of packed signed integers",
"mnem": "pminsq"
},
{
"description": "minimum of packed signed word integers",
"mnem": "pminsw"
},
{
"description": "minimum of packed unsigned byte integers",
"mnem": "pminub"
},
{
"description": "minimum of packed unsigned dword integers",
"mnem": "pminud"
},
{
"description": "minimum of packed unsigned integers",
"mnem": "pminuq"
},
{
"description": "minimum of packed unsigned word integers",
"mnem": "pminuw"
},
{
"description": "move byte mask",
"mnem": "pmovmskb"
},
{
"description": "sign extend the lower 8-bit integer of each packed dword element into packed signed dword integers",
"mnem": "pmovsxbd"
},
{
"description": "sign extend the lower 8-bit integer of each packed qword element into packed signed qword integers",
"mnem": "pmovsxbq"
},
{
"description": "sign extend the lower 8-bit integer of each packed word element into packed signed word integers",
"mnem": "pmovsxbw"
},
{
"description": "sign extend the lower 32-bit integer of each packed qword element into packed signed qword integers",
"mnem": "pmovsxdq"
},
{
"description": "sign extend the lower 16-bit integer of each packed dword element into packed signed dword integers",
"mnem": "pmovsxwd"
},
{
"description": "sign extend the lower 16-bit integer of each packed qword element into packed signed qword integers",
"mnem": "pmovsxwq"
},
{
"description": "zero extend the lower 8-bit integer of each packed dword element into packed signed dword integers",
"mnem": "pmovzxbd"
},
{
"description": "zero extend the lower 8-bit integer of each packed qword element into packed signed qword integers",
"mnem": "pmovzxbq"
},
{
"description": "zero extend the lower 8-bit integer of each packed word element into packed signed word integers",
"mnem": "pmovzxbw"
},
{
"description": "zero extend the lower 32-bit integer of each packed qword element into packed signed qword integers",
"mnem": "pmovzxdq"
},
{
"description": "zero extend the lower 16-bit integer of each packed dword element into packed signed dword integers",
"mnem": "pmovzxwd"
},
{
"description": "zero extend the lower 16-bit integer of each packed qword element into packed signed qword integers",
"mnem": "pmovzxwq"
},
{
"description": "multiply packed doubleword integers",
"mnem": "pmuldq"
},
{
"description": "packed multiply high with round and scale",
"mnem": "pmulhrsw"
},
{
"description": "multiply packed unsigned integers and store high result",
"mnem": "pmulhuw"
},
{
"description": "multiply packed signed integers and store high result",
"mnem": "pmulhw"
},
{
"description": "multiply packed signed dword integers and store low result",
"mnem": "pmulld"
},
{
"description": "multiply packed integers and store low result",
"mnem": "pmullq"
},
{
"description": "multiply packed signed integers and store low result",
"mnem": "pmullw"
},
{
"description": "multiply packed unsigned dw integers",
"mnem": "pmuludq"
},
{
"description": "pops last element of stack and stores the result in argument",
"mnem": "pop"
},
{
"description": "pop all general-purpose registers",
"mnem": "popa"
},
{
"description": "pop all general-purpose registers",
"mnem": "popad"
},
{
"description": "pop all general-purpose registers",
"mnem": "popal"
},
{
"description": "bit population count",
"mnem": "popcnt"
},
{
"description": "pop stack into flags register",
"mnem": "popf"
},
{
"description": "pop stack into eflags register",
"mnem": "popfd"
},
{
"description": "pop stack into rflags register",
"mnem": "popfq"
},
{
"description": "bitwise logical or",
"mnem": "por"
},
{
"description": "prefetch data into caches",
"mnem": "prefetchnta"
},
{
"description": "prefetch data into caches",
"mnem": "prefetcht0"
},
{
"description": "prefetch data into caches",
"mnem": "prefetcht1"
},
{
"description": "prefetch data into caches",
"mnem": "prefetcht2"
},
{
"description": "prefetch data into caches",
"mnem": "prefetchw"
},
{
"description": "prefetch vector data into caches with intent to write and t1 hint",
"mnem": "prefetchwt1"
},
{
"description": "bit rotate left",
"mnem": "prold"
},
{
"description": "bit rotate left",
"mnem": "prolq"
},
{
"description": "bit rotate left",
"mnem": "prolvd"
},
{
"description": "bit rotate left",
"mnem": "prolvq"
},
{
"description": "bit rotate right",
"mnem": "prord"
},
{
"description": "bit rotate right",
"mnem": "prorq"
},
{
"description": "bit rotate right",
"mnem": "prorvd"
},
{
"description": "bit rotate right",
"mnem": "prorvq"
},
{
"description": "compute sum of absolute differences",
"mnem": "psadbw"
},
{
"description": "packed shuffle bytes",
"mnem": "pshufb"
},
{
"description": "shuffle packed doublewords",
"mnem": "pshufd"
},
{
"description": "shuffle packed high words",
"mnem": "pshufhw"
},
{
"description": "shuffle packed low words",
"mnem": "pshuflw"
},
{
"description": "shuffle packed words",
"mnem": "pshufw"
},
{
"description": "packed sign",
"mnem": "psignb"
},
{
"description": "packed sign",
"mnem": "psignd"
},
{
"description": "packed sign",
"mnem": "psignw"
},
{
"description": "shift packed data left logical",
"mnem": "pslld"
},
{
"description": "shift double quadword left logical",
"mnem": "pslldq"
},
{
"description": "shift packed data left logical",
"mnem": "psllq"
},
{
"description": "shift packed data left logical",
"mnem": "psllw"
},
{
"description": "shift packed data right arithmetic",
"mnem": "psrad"
},
{
"description": "shift packed data right arithmetic",
"mnem": "psraq"
},
{
"description": "shift packed data right arithmetic",
"mnem": "psraw"
},
{
"description": "shift packed data right logical",
"mnem": "psrld"
},
{
"description": "shift double quadword right logical",
"mnem": "psrldq"
},
{
"description": "shift packed data right logical",
"mnem": "psrlq"
},
{
"description": "shift packed data right logical",
"mnem": "psrlw"
},
{
"description": "subtract packed integers",
"mnem": "psubb"
},
{
"description": "subtract packed integers",
"mnem": "psubd"
},
{
"description": "subtract packed quadword integers",
"mnem": "psubq"
},
{
"description": "subtract packed signed integers with signed saturation",
"mnem": "psubsb"
},
{
"description": "subtract packed signed integers with signed saturation",
"mnem": "psubsw"
},
{
"description": "subtract packed unsigned integers with unsigned saturation",
"mnem": "psubusb"
},
{
"description": "subtract packed unsigned integers with unsigned saturation",
"mnem": "psubusw"
},
{
"description": "subtract packed integers",
"mnem": "psubw"
},
{
"description": "logical compare",
"mnem": "ptest"
},
{
"description": "ptwrite - write data to a processor trace packet",
"mnem": "ptwrite"
},
{
"description": "unpack high data",
"mnem": "punpckhbw"
},
{
"description": "unpack high data",
"mnem": "punpckhdq"
},
{
"description": "unpack high data",
"mnem": "punpckhqdq"
},
{
"description": "unpack high data",
"mnem": "punpckhwd"
},
{
"description": "unpack low data",
"mnem": "punpcklbw"
},
{
"description": "unpack low data",
"mnem": "punpckldq"
},
{
"description": "unpack low data",
"mnem": "punpcklqdq"
},
{
"description": "unpack low data",
"mnem": "punpcklwd"
},
{
"description": "push word, doubleword or quadword onto the stack",
"mnem": "push"
},
{
"description": "push all general-purpose registers",
"mnem": "pusha"
},
{
"description": "push all general-purpose registers",
"mnem": "pushad"
},
{
"description": "push all general-purpose registers",
"mnem": "pushal"
},
{
"description": "push flags register onto the stack",
"mnem": "pushf"
},
{
"description": "push eflags register onto the stack",
"mnem": "pushfd"
},
{
"description": "push rflags register onto the stack",
"mnem": "pushfq"
},
{
"description": "logical exclusive or",
"mnem": "pxor"
},
{
"description": "rotate bits left (with CF)",
"mnem": "rcl"
},
{
"description": "compute reciprocals of packed single-fp values",
"mnem": "rcpps"
},
{
"description": "compute reciprocal of scalar single-fp values",
"mnem": "rcpss"
},
{
"description": "rotate bits right (with CF)",
"mnem": "rcr"
},
{
"description": "read fs/gs segment base",
"mnem": "rdfsbase"
},
{
"description": "read fs/gs segment base",
"mnem": "rdgsbase"
},
{
"description": "read from model specific register",
"mnem": "rdmsr"
},
{
"description": "read processor id",
"mnem": "rdpid"
},
{
"description": "read protection key rights for user pages",
"mnem": "rdpkru"
},
{
"description": "read performance-monitoring counters",
"mnem": "rdpmc"
},
{
"description": "read random number",
"mnem": "rdrand"
},
{
"description": "read random seed",
"mnem": "rdseed"
},
{
"description": "read time-stamp counter",
"mnem": "rdtsc"
},
{
"description": "read time-stamp counter and processor id",
"mnem": "rdtscp"
},
{
"description": "repeats next instruction ECX times",
"mnem": "rep"
},
{
"description": "repeat string operation prefix",
"mnem": "rep ins"
},
{
"description": "repeat string operation prefix",
"mnem": "rep lods"
},
{
"description": "repeat string operation prefix",
"mnem": "rep movs"
},
{
"description": "repeat string operation prefix",
"mnem": "rep outs"
},
{
"description": "repeat string operation prefix",
"mnem": "rep stos"
},
{
"description": "repeat string",
"mnem": "repe"
},
{
"description": "repeat string operation prefix",
"mnem": "repe cmps"
},
{
"description": "repeat string operation prefix",
"mnem": "repe scas"
},
{
"description": "repeat string operation prefix",
"mnem": "repne"
},
{
"description": "repeat string operation prefix",
"mnem": "repne cmps"
},
{
"description": "repeat string operation prefix",
"mnem": "repne scas"
},
{
"description": "repeat string operation prefix",
"mnem": "repnz"
},
{
"description": "repeat string operation prefix",
"mnem": "repz"
},
{
"description": "return from subroutine. pop 4 bytes from esp and jump there.",
"mnem": "ret"
},
{
"description": "return from procedure",
"mnem": "retf"
},
{
"description": "return from procedure",
"mnem": "retn"
},
{
"description": "access to new 8-bit registers",
"mnem": "rex"
},
{
"description": "extension of r/m field, base field, or opcode reg field",
"mnem": "rex.b"
},
{
"description": "extension of modr/m reg field",
"mnem": "rex.r"
},
{
"description": "rex.r and rex.b combination",
"mnem": "rex.rb"
},
{
"description": "rex.r and rex.x combination",
"mnem": "rex.rx"
},
{
"description": "rex.r, rex.x and rex.b combination",
"mnem": "rex.rxb"
},
{
"description": "64 bit operand size",
"mnem": "rex.w"
},
{
"description": "rex.w and rex.b combination",
"mnem": "rex.wb"
},
{
"description": "rex.w and rex.r combination",
"mnem": "rex.wr"
},
{
"description": "rex.w, rex.r and rex.b combination",
"mnem": "rex.wrb"
},
{
"description": "rex.w, rex.r and rex.x combination",
"mnem": "rex.wrx"
},
{
"description": "rex.w, rex.r, rex.x and rex.b combination",
"mnem": "rex.wrxb"
},
{
"description": "rex.w and rex.x combination",
"mnem": "rex.wx"
},
{
"description": "rex.w, rex.x and rex.b combination",
"mnem": "rex.wxb"
},
{
"description": "extension of sib index field",
"mnem": "rex.x"
},
{
"description": "rex.x and rex.b combination",
"mnem": "rex.xb"
},
{
"description": "rotate bits left",
"mnem": "rol"
},
{
"description": "rotate bits right",
"mnem": "ror"
},
{
"description": "rotate right logical without affecting flags",
"mnem": "rorx"
},
{
"description": "round packed double-fp values",
"mnem": "roundpd"
},
{
"description": "round packed single-fp values",
"mnem": "roundps"
},
{
"description": "round scalar double-fp values",
"mnem": "roundsd"
},
{
"description": "round scalar single-fp values",
"mnem": "roundss"
},
{
"description": "resume from system management mode",
"mnem": "rsm"
},
{
"description": "compute recipr. of square roots of packed single-fp values",
"mnem": "rsqrtps"
},
{
"description": "compute recipr. of square root of scalar single-fp value",
"mnem": "rsqrtss"
},
{
"description": "read time-stamp counter into edx:eax",
"mnem": "rtdsc"
},
{
"description": "store ah into flags",
"mnem": "sahf"
},
{
"description": "arithmetic left shift",
"mnem": "sal"
},
{
"description": "set al if carry",
"mnem": "salc"
},
{
"description": "arithmetic right shift",
"mnem": "sar"
},
{
"description": "shift without affecting flags",
"mnem": "sarx"
},
{
"description": "integer subtraction with borrow",
"mnem": "sbb"
},
{
"description": "scan string",
"mnem": "scas"
},
{
"description": "cmp al, ES:[edi++]",
"mnem": "scasb"
},
{
"description": "cmp eax, ES:[edi+=4]",
"mnem": "scasd"
},
{
"description": "cmp rax, ES:[rdi+=8]",
"mnem": "scasq"
},
{
"description": "cmp ax, ES:[edi+=2]",
"mnem": "scasw"
},
{
"description": "set byte on condition - above/not below nor equal (cf=0 and zf=0)",
"mnem": "seta"
},
{
"description": "set byte on condition - above or equal/not below/not carry (cf=0)",
"mnem": "setae"
},
{
"description": "set byte on condition - below/not above nor equal/carry (cf=1)",
"mnem": "setb"
},
{
"description": "set byte on condition - below or equal/not above (cf=1 or zf=1)",
"mnem": "setbe"
},
{
"description": "set byte on condition - carry/below/not above nor equal (cf=1)",
"mnem": "setc"
},
{
"description": "set byte on condition - equal/zero (zf=1)",
"mnem": "sete"
},
{
"description": "set byte on condition - greater/not less nor equal (zf=0 and sf=of)",
"mnem": "setg"
},
{
"description": "set byte on condition - greater or equal/not less (sf=of)",
"mnem": "setge"
},
{
"description": "set byte on condition - less/not greater nor equal (sf!=of)",
"mnem": "setl"
},
{
"description": "set byte on condition - less or equal/not greater (zf=1 or sf!=of)",
"mnem": "setle"
},
{
"description": "set byte on condition - not above/below or equal (cf=1 or zf=1)",
"mnem": "setna"
},
{
"description": "set byte on condition - not above nor equal/below/carry (cf=1)",
"mnem": "setnae"
},
{
"description": "set byte on condition - not below/above or equal/not carry (cf=0)",
"mnem": "setnb"
},
{
"description": "set byte on condition - not below nor equal/above (cf=0 and zf=0)",
"mnem": "setnbe"
},
{
"description": "set byte on condition - not carry/above or equal/not below (cf=0)",
"mnem": "setnc"
},
{
"description": "set byte on condition - not equal/not zero (zf=0)",
"mnem": "setne"
},
{
"description": "set byte on condition - not greater/less or equal (zf=1 or sf!=of)",
"mnem": "setng"
},
{
"description": "set byte on condition - not greater nor equal/less (sf!=of)",
"mnem": "setnge"
},
{
"description": "set byte on condition - not less/greater or equal (sf=of)",
"mnem": "setnl"
},
{
"description": "set byte on condition - not less nor equal/greater (zf=0 and sf=of)",
"mnem": "setnle"
},
{
"description": "set byte on condition - not overflow (of=0)",
"mnem": "setno"
},
{
"description": "set byte on condition - not parity/parity odd (pf=0)",
"mnem": "setnp"
},
{
"description": "set byte on condition - not sign (sf=0)",
"mnem": "setns"
},
{
"description": "set byte on condition - not zero/not equal (zf=0)",
"mnem": "setnz"
},
{
"description": "set byte on condition - overflow (of=1)",
"mnem": "seto"
},
{
"description": "set byte on condition - parity/parity even (pf=1)",
"mnem": "setp"
},
{
"description": "set byte on condition - parity even/parity (pf=1)",
"mnem": "setpe"
},
{
"description": "set byte on condition - parity odd/not parity (pf=0)",
"mnem": "setpo"
},
{
"description": "set byte on condition - sign (sf=1)",
"mnem": "sets"
},
{
"description": "set byte on condition - zero/equal (zf=1)",
"mnem": "setz"
},
{
"description": "store fence",
"mnem": "sfence"
},
{
"description": "store global descriptor table register",
"mnem": "sgdt"
},
{
"description": "perform an intermediate calculation for the next four sha1 message dwords",
"mnem": "sha1msg1"
},
{
"description": "perform a final calculation for the next four sha1 message dwords",
"mnem": "sha1msg2"
},
{
"description": "calculate sha1 state variable e after four rounds",
"mnem": "sha1nexte"
},
{
"description": "perform four rounds of sha1 operation",
"mnem": "sha1rnds4"
},
{
"description": "perform an intermediate calculation for the next four sha256 message dwords",
"mnem": "sha256msg1"
},
{
"description": "perform a final calculation for the next four sha256 message dwords",
"mnem": "sha256msg2"
},
{
"description": "perform two rounds of sha256 operation",
"mnem": "sha256rnds2"
},
{
"description": "logic left shift (0 padding)",
"mnem": "shl"
},
{
"description": "double precision shift left",
"mnem": "shld"
},
{
"description": "shift without affecting flags",
"mnem": "shlx"
},
{
"description": "logic right shift (0 padding)",
"mnem": "shr"
},
{
"description": "double precision shift right",
"mnem": "shrd"
},
{
"description": "shift without affecting flags",
"mnem": "shrx"
},
{
"description": "shuffle packed double-fp values",
"mnem": "shufpd"
},
{
"description": "shuffle packed single-fp values",
"mnem": "shufps"
},
{
"description": "store interrupt descriptor table register",
"mnem": "sidt"
},
{
"description": "store local descriptor table register.",
"mnem": "sldt"
},
{
"description": "store machine status word",
"mnem": "smsw"
},
{
"description": "compute square roots of packed double-fp values",
"mnem": "sqrtpd"
},
{
"description": "compute square roots of packed single-fp values",
"mnem": "sqrtps"
},
{
"description": "compute square root of scalar double-fp value",
"mnem": "sqrtsd"
},
{
"description": "compute square root of scalar single-fp value",
"mnem": "sqrtss"
},
{
"description": "ss segment override prefix",
"mnem": "ss"
},
{
"description": "set ac flag in eflags register",
"mnem": "stac"
},
{
"description": "set carry flag",
"mnem": "stc"
},
{
"description": "set direction flag",
"mnem": "std"
},
{
"description": "set interrupt flag",
"mnem": "sti"
},
{
"description": "store mxcsr register state",
"mnem": "stmxcsr"
},
{
"description": "store string",
"mnem": "stos"
},
{
"description": "store string byte",
"mnem": "stosb"
},
{
"description": "store string dword",
"mnem": "stosd"
},
{
"description": "store string quadword",
"mnem": "stosq"
},
{
"description": "store string word",
"mnem": "stosw"
},
{
"description": "store task register",
"mnem": "str"
},
{
"description": "substract src and dst, stores result on dst",
"mnem": "sub"
},
{
"description": "subtract packed double-fp values",
"mnem": "subpd"
},
{
"description": "subtract packed single-fp values",
"mnem": "subps"
},
{
"description": "subtract scalar double-fp values",
"mnem": "subsd"
},
{
"description": "subtract scalar single-fp values",
"mnem": "subss"
},
{
"description": "swap gs base register",
"mnem": "swapgs"
},
{
"description": "fast system call",
"mnem": "syscall"
},
{
"description": "fast system call",
"mnem": "sysenter"
},
{
"description": "fast return from fast system call",
"mnem": "sysexit"
},
{
"description": "return from fast system call",
"mnem": "sysret"
},
{
"description": "set eflags after comparing two registers (AF, CF, OF, PF, SF, ZF)",
"mnem": "test"
},
{
"description": "count the number of trailing zero bits",
"mnem": "tzcnt"
},
{
"description": "unordered compare scalar double-fp values and set eflags",
"mnem": "ucomisd"
},
{
"description": "unordered compare scalar single-fp values and set eflags",
"mnem": "ucomiss"
},
{
"description": "undefined instruction",
"mnem": "ud1"
},
{
"description": "undefined instruction",
"mnem": "ud2"
},
{
"description": "unpack and interleave high packed double-fp values",
"mnem": "unpckhpd"
},
{
"description": "unpack and interleave high packed single-fp values",
"mnem": "unpckhps"
},
{
"description": "unpack and interleave low packed double-fp values",
"mnem": "unpcklpd"
},
{
"description": "unpack and interleave low packed single-fp values",
"mnem": "unpcklps"
},
{
"description": "add packed double-precision floating-point values",
"mnem": "vaddpd"
},
{
"description": "add packed single-precision floating-point values",
"mnem": "vaddps"
},
{
"description": "add scalar double-precision floating-point values",
"mnem": "vaddsd"
},
{
"description": "add scalar single-precision floating-point values",
"mnem": "vaddss"
},
{
"description": "packed double-fp add/subtract",
"mnem": "vaddsubpd"
},
{
"description": "packed single-fp add/subtract",
"mnem": "vaddsubps"
},
{
"description": "perform one round of an aes decryption flow",
"mnem": "vaesdec"
},
{
"description": "perform last round of an aes decryption flow",
"mnem": "vaesdeclast"
},
{
"description": "perform one round of an aes encryption flow",
"mnem": "vaesenc"
},
{
"description": "perform last round of an aes encryption flow",
"mnem": "vaesenclast"
},
{
"description": "perform the aes invmixcolumn transformation",
"mnem": "vaesimc"
},
{
"description": "aes round key generation assist",
"mnem": "vaeskeygenassist"
},
{
"description": "align doubleword/quadword vectors",
"mnem": "valignd"
},
{
"description": "align doubleword/quadword vectors",
"mnem": "valignq"
},
{
"description": "bitwise logical and not of packed double precision floating-point values",
"mnem": "vandnpd"
},
{
"description": "bitwise logical and not of packed single precision floating-point values",
"mnem": "vandnps"
},
{
"description": "bitwise logical and of packed double precision floating-point values",
"mnem": "vandpd"
},
{
"description": "bitwise logical and of packed single precision floating-point values",
"mnem": "vandps"
},
{
"description": "blend float64/float32 vectors using an opmask control",
"mnem": "vblendmpd"
},
{
"description": "blend float64/float32 vectors using an opmask control",
"mnem": "vblendmps"
},
{
"description": "blend packed double precision floating-point values",
"mnem": "vblendpd"
},
{
"description": "blend packed single precision floating-point values",
"mnem": "vblendps"
},
{
"description": "variable blend packed double precision floating-point values",
"mnem": "vblendvpd"
},
{
"description": "variable blend packed single precision floating-point values",
"mnem": "vblendvps"
},
{
"description": "load with broadcast floating-point data",
"mnem": "vbroadcastf128"
},
{
"description": "load with broadcast floating-point data",
"mnem": "vbroadcastf32x2"
},
{
"description": "load with broadcast floating-point data",
"mnem": "vbroadcastf32x4"
},
{
"description": "load with broadcast floating-point data",
"mnem": "vbroadcastf32x8"
},
{
"description": "load with broadcast floating-point data",
"mnem": "vbroadcastf64x2"
},
{
"description": "load with broadcast floating-point data",
"mnem": "vbroadcastf64x4"
},
{
"description": "load integer and broadcast",
"mnem": "vbroadcasti32x2"
},
{
"description": "load integer and broadcast",
"mnem": "vbroadcasti32x8"
},
{
"description": "load integer and broadcast",
"mnem": "vbroadcasti64x4"
},
{
"description": "load with broadcast floating-point data",
"mnem": "vbroadcastsd"
},
{
"description": "load with broadcast floating-point data",
"mnem": "vbroadcastss"
},
{
"description": "compare packed double-precision floating-point values",
"mnem": "vcmppd"
},
{
"description": "compare packed single-precision floating-point values",
"mnem": "vcmpps"
},
{
"description": "compare scalar double-precision floating-point value",
"mnem": "vcmpsd"
},
{
"description": "compare scalar single-precision floating-point value",
"mnem": "vcmpss"
},
{
"description": "compare scalar ordered double-precision floating-point values and set eflags",
"mnem": "vcomisd"
},
{
"description": "compare scalar ordered single-precision floating-point values and set eflags",
"mnem": "vcomiss"
},
{
"description": "store sparse packed double-precision floating-point values into dense memory",
"mnem": "vcompresspd"
},
{
"description": "store sparse packed single-precision floating-point values into dense memory",
"mnem": "vcompressps"
},
{
"description": "convert packed doubleword integers to packed double-precision floating-point values",
"mnem": "vcvtdq2pd"
},
{
"description": "convert packed doubleword integers to packed single-precision floating-point values",
"mnem": "vcvtdq2ps"
},
{
"description": "convert packed double-precision floating-point values to packed doubleword integers",
"mnem": "vcvtpd2dq"
},
{
"description": "convert packed double-precision floating-point values to packed single-precision floating-point values",
"mnem": "vcvtpd2ps"
},
{
"description": "convert packed double-precision floating-point values to packed quadword integers",
"mnem": "vcvtpd2qq"
},
{
"description": "convert packed double-precision floating-point values to packed unsigned doubleword integers",
"mnem": "vcvtpd2udq"
},
{
"description": "convert packed double-precision floating-point values to packed unsigned quadword integers",
"mnem": "vcvtpd2uqq"
},
{
"description": "convert 16-bit fp values to single-precision fp values",
"mnem": "vcvtph2ps"
},
{
"description": "convert packed single-precision floating-point values to packed signed doubleword integer values",
"mnem": "vcvtps2dq"
},
{
"description": "convert packed single-precision floating-point values to packed double-precision floating-point values",
"mnem": "vcvtps2pd"
},
{
"description": "convert single-precision fp value to 16-bit fp value",
"mnem": "vcvtps2ph"
},
{
"description": "convert packed single precision floating-point values to packed singed quadword integer values",
"mnem": "vcvtps2qq"
},
{
"description": "convert packed single-precision floating-point values to packed unsigned doubleword integer values",
"mnem": "vcvtps2udq"
},
{
"description": "convert packed single precision floating-point values to packed unsigned quadword integer values",
"mnem": "vcvtps2uqq"
},
{
"description": "convert packed quadword integers to packed double-precision floating-point values",
"mnem": "vcvtqq2pd"
},
{
"description": "convert packed quadword integers to packed single-precision floating-point values",
"mnem": "vcvtqq2ps"
},
{
"description": "convert scalar double-precision floating-point value to doubleword integer",
"mnem": "vcvtsd2si"
},
{
"description": "convert scalar double-precision floating-point value to scalar single-precision floating-point value",
"mnem": "vcvtsd2ss"
},
{
"description": "convert scalar double-precision floating-point value to unsigned doubleword integer",
"mnem": "vcvtsd2usi"
},
{
"description": "convert doubleword integer to scalar double-precision floating-point value",
"mnem": "vcvtsi2sd"
},
{
"description": "convert doubleword integer to scalar single-precision floating-point value",
"mnem": "vcvtsi2ss"
},
{
"description": "convert scalar single-precision floating-point value to scalar double-precision floating-point value",
"mnem": "vcvtss2sd"
},
{
"description": "convert scalar single-precision floating-point value to doubleword integer",
"mnem": "vcvtss2si"
},
{
"description": "convert scalar single-precision floating-point value to unsigned doubleword integer",
"mnem": "vcvtss2usi"
},
{
"description": "convert with truncation packed double-precision floating-point values to packed doubleword integers",
"mnem": "vcvttpd2dq"
},
{
"description": "convert with truncation packed double-precision floating-point values to packed quadword integers",
"mnem": "vcvttpd2qq"
},
{
"description": "convert with truncation packed double-precision floating-point values to packed unsigned doubleword integers",
"mnem": "vcvttpd2udq"
},
{
"description": "convert with truncation packed double-precision floating-point values to packed unsigned quadword integers",
"mnem": "vcvttpd2uqq"
},
{
"description": "convert with truncation packed single-precision floating-point values to packed signed doubleword integer values",
"mnem": "vcvttps2dq"
},
{
"description": "convert with truncation packed single precision floating-point values to packed singed quadword integer values",
"mnem": "vcvttps2qq"
},
{
"description": "convert with truncation packed single-precision floating-point values to packed unsigned doubleword integer values",
"mnem": "vcvttps2udq"
},
{
"description": "convert with truncation packed single precision floating-point values to packed unsigned quadword integer values",
"mnem": "vcvttps2uqq"
},
{
"description": "convert with truncation scalar double-precision floating-point value to signed integer",
"mnem": "vcvttsd2si"
},
{
"description": "convert with truncation scalar double-precision floating-point value to unsigned integer",
"mnem": "vcvttsd2usi"
},
{
"description": "convert with truncation scalar single-precision floating-point value to integer",
"mnem": "vcvttss2si"
},
{
"description": "convert with truncation scalar single-precision floating-point value to unsigned integer",
"mnem": "vcvttss2usi"
},
{
"description": "convert packed unsigned doubleword integers to packed double-precision floating-point values",
"mnem": "vcvtudq2pd"
},
{
"description": "convert packed unsigned doubleword integers to packed single-precision floating-point values",
"mnem": "vcvtudq2ps"
},
{
"description": "convert packed unsigned quadword integers to packed double-precision floating-point values",
"mnem": "vcvtuqq2pd"
},
{
"description": "convert packed unsigned quadword integers to packed single-precision floating-point values",
"mnem": "vcvtuqq2ps"
},
{
"description": "convert unsigned integer to scalar double-precision floating-point value",
"mnem": "vcvtusi2sd"
},
{
"description": "convert unsigned integer to scalar single-precision floating-point value",
"mnem": "vcvtusi2ss"
},
{
"description": "double block packed sum-absolute-differences (sad) on unsigned bytes",
"mnem": "vdbpsadbw"
},
{
"description": "divide packed double-precision floating-point values",
"mnem": "vdivpd"
},
{
"description": "divide packed single-precision floating-point values",
"mnem": "vdivps"
},
{
"description": "divide scalar double-precision floating-point value",
"mnem": "vdivsd"
},
{
"description": "divide scalar single-precision floating-point values",
"mnem": "vdivss"
},
{
"description": "dot product of packed double precision floating-point values",
"mnem": "vdppd"
},
{
"description": "dot product of packed single precision floating-point values",
"mnem": "vdpps"
},
{
"description": "verify a segment for reading",
"mnem": "verr"
},
{
"description": "verify a segment for writing",
"mnem": "verw"
},
{
"description": "approximation to the exponential 2^x of packed double-precision floating-point values with less than 2^-23 relative error",
"mnem": "vexp2pd"
},
{
"description": "approximation to the exponential 2^x of packed single-precision floating-point values with less than 2^-23 relative error",
"mnem": "vexp2ps"
},
{
"description": "load sparse packed double-precision floating-point values from dense memory",
"mnem": "vexpandpd"
},
{
"description": "load sparse packed single-precision floating-point values from dense memory",
"mnem": "vexpandps"
},
{
"description": "extra ct packed floating-point values",
"mnem": "vextractf128"
},
{
"description": "extra ct packed floating-point values",
"mnem": "vextractf32x4"
},
{
"description": "extra ct packed floating-point values",
"mnem": "vextractf32x8"
},
{
"description": "extra ct packed floating-point values",
"mnem": "vextractf64x2"
},
{
"description": "extra ct packed floating-point values",
"mnem": "vextractf64x4"
},
{
"description": "extract packed integer values",
"mnem": "vextracti128"
},
{
"description": "extract packed integer values",
"mnem": "vextracti32x4"
},
{
"description": "extract packed integer values",
"mnem": "vextracti32x8"
},
{
"description": "extract packed integer values",
"mnem": "vextracti64x2"
},
{
"description": "extract packed integer values",
"mnem": "vextracti64x4"
},
{
"description": "extract packed floating-point values",
"mnem": "vextractps"
},
{
"description": "fix up special packed float64 values",
"mnem": "vfixupimmpd"
},
{
"description": "fix up special packed float32 values",
"mnem": "vfixupimmps"
},
{
"description": "fix up special scalar float64 value",
"mnem": "vfixupimmsd"
},
{
"description": "fix up special scalar float32 value",
"mnem": "vfixupimmss"
},
{
"description": "fused multiply-add of packed double-precision floating-point values",
"mnem": "vfmadd132pd"
},
{
"description": "fused multiply-add of packed single-precision floating-point values",
"mnem": "vfmadd132ps"
},
{
"description": "fused multiply-add of scalar double-precision floating-point values",
"mnem": "vfmadd132sd"
},
{
"description": "fused multiply-add of scalar single-precision floating-point values",
"mnem": "vfmadd132ss"
},
{
"description": "fused multiply-add of packed double-precision floating-point values",
"mnem": "vfmadd213pd"
},
{
"description": "fused multiply-add of packed single-precision floating-point values",
"mnem": "vfmadd213ps"
},
{
"description": "fused multiply-add of scalar double-precision floating-point values",
"mnem": "vfmadd213sd"
},
{
"description": "fused multiply-add of scalar single-precision floating-point values",
"mnem": "vfmadd213ss"
},
{
"description": "fused multiply-add of packed double-precision floating-point values",
"mnem": "vfmadd231pd"
},
{
"description": "fused multiply-add of packed single-precision floating-point values",
"mnem": "vfmadd231ps"
},
{
"description": "fused multiply-add of scalar double-precision floating-point values",
"mnem": "vfmadd231sd"
},
{
"description": "fused multiply-add of scalar single-precision floating-point values",
"mnem": "vfmadd231ss"
},
{
"description": "fused multiply-alternating add/subtract of packed double-precision floating-point values",
"mnem": "vfmaddsub132pd"
},
{
"description": "fused multiply-alternating add/subtract of packed single-precision floating-point values",
"mnem": "vfmaddsub132ps"
},
{
"description": "fused multiply-alternating add/subtract of packed double-precision floating-point values",
"mnem": "vfmaddsub213pd"
},
{
"description": "fused multiply-alternating add/subtract of packed single-precision floating-point values",
"mnem": "vfmaddsub213ps"
},
{
"description": "fused multiply-alternating add/subtract of packed double-precision floating-point values",
"mnem": "vfmaddsub231pd"
},
{
"description": "fused multiply-alternating add/subtract of packed single-precision floating-point values",
"mnem": "vfmaddsub231ps"
},
{
"description": "fused multiply-subtract of packed double-precision floating-point values",
"mnem": "vfmsub132pd"
},
{
"description": "fused multiply-subtract of packed single-precision floating-point values",
"mnem": "vfmsub132ps"
},
{
"description": "fused multiply-subtract of scalar double-precision floating-point values",
"mnem": "vfmsub132sd"
},
{
"description": "fused multiply-subtract of scalar single-precision floating-point values",
"mnem": "vfmsub132ss"
},
{
"description": "fused multiply-subtract of packed double-precision floating-point values",
"mnem": "vfmsub213pd"
},
{
"description": "fused multiply-subtract of packed single-precision floating-point values",
"mnem": "vfmsub213ps"
},
{
"description": "fused multiply-subtract of scalar double-precision floating-point values",
"mnem": "vfmsub213sd"
},
{
"description": "fused multiply-subtract of scalar single-precision floating-point values",
"mnem": "vfmsub213ss"
},
{
"description": "fused multiply-subtract of packed double-precision floating-point values",
"mnem": "vfmsub231pd"
},
{
"description": "fused multiply-subtract of packed single-precision floating-point values",
"mnem": "vfmsub231ps"
},
{
"description": "fused multiply-subtract of scalar double-precision floating-point values",
"mnem": "vfmsub231sd"
},
{
"description": "fused multiply-subtract of scalar single-precision floating-point values",
"mnem": "vfmsub231ss"
},
{
"description": "fused multiply-alternating subtract/add of packed double-precision floating-point values",
"mnem": "vfmsubadd132pd"
},
{
"description": "fused multiply-alternating subtract/add of packed single-precision floating-point values",
"mnem": "vfmsubadd132ps"
},
{
"description": "fused multiply-alternating subtract/add of packed double-precision floating-point values",
"mnem": "vfmsubadd213pd"
},
{
"description": "fused multiply-alternating subtract/add of packed single-precision floating-point values",
"mnem": "vfmsubadd213ps"
},
{
"description": "fused multiply-alternating subtract/add of packed double-precision floating-point values",
"mnem": "vfmsubadd231pd"
},
{
"description": "fused multiply-alternating subtract/add of packed single-precision floating-point values",
"mnem": "vfmsubadd231ps"
},
{
"description": "fused negative multiply-add of packed double-precision floating-point values",
"mnem": "vfnmadd132pd"
},
{
"description": "fused negative multiply-add of packed single-precision floating-point values",
"mnem": "vfnmadd132ps"
},
{
"description": "fused negative multiply-add of scalar double-precision floating-point values",
"mnem": "vfnmadd132sd"
},
{
"description": "fused negative multiply-add of scalar single-precision floating-point values",
"mnem": "vfnmadd132ss"
},
{
"description": "fused negative multiply-add of packed double-precision floating-point values",
"mnem": "vfnmadd213pd"
},
{
"description": "fused negative multiply-add of packed single-precision floating-point values",
"mnem": "vfnmadd213ps"
},
{
"description": "fused negative multiply-add of scalar double-precision floating-point values",
"mnem": "vfnmadd213sd"
},
{
"description": "fused negative multiply-add of scalar single-precision floating-point values",
"mnem": "vfnmadd213ss"
},
{
"description": "fused negative multiply-add of packed double-precision floating-point values",
"mnem": "vfnmadd231pd"
},
{
"description": "fused negative multiply-add of packed single-precision floating-point values",
"mnem": "vfnmadd231ps"
},
{
"description": "fused negative multiply-add of scalar double-precision floating-point values",
"mnem": "vfnmadd231sd"
},
{
"description": "fused negative multiply-add of scalar single-precision floating-point values",
"mnem": "vfnmadd231ss"
},
{
"description": "fused negative multiply-subtract of packed double-precision floating-point values",
"mnem": "vfnmsub132pd"
},
{
"description": "fused negative multiply-subtract of packed single-precision floating-point values",
"mnem": "vfnmsub132ps"
},
{
"description": "fused negative multiply-subtract of scalar double-precision floating-point values",
"mnem": "vfnmsub132sd"
},
{
"description": "fused negative multiply-subtract of scalar single-precision floating-point values",
"mnem": "vfnmsub132ss"
},
{
"description": "fused negative multiply-subtract of packed double-precision floating-point values",
"mnem": "vfnmsub213pd"
},
{
"description": "fused negative multiply-subtract of packed single-precision floating-point values",
"mnem": "vfnmsub213ps"
},
{
"description": "fused negative multiply-subtract of scalar double-precision floating-point values",
"mnem": "vfnmsub213sd"
},
{
"description": "fused negative multiply-subtract of scalar single-precision floating-point values",
"mnem": "vfnmsub213ss"
},
{
"description": "fused negative multiply-subtract of packed double-precision floating-point values",
"mnem": "vfnmsub231pd"
},
{
"description": "fused negative multiply-subtract of packed single-precision floating-point values",
"mnem": "vfnmsub231ps"
},
{
"description": "fused negative multiply-subtract of scalar double-precision floating-point values",
"mnem": "vfnmsub231sd"
},
{
"description": "fused negative multiply-subtract of scalar single-precision floating-point values",
"mnem": "vfnmsub231ss"
},
{
"description": "tests types of a packed float64 values",
"mnem": "vfpclasspd"
},
{
"description": "tests types of a packed float32 values",
"mnem": "vfpclassps"
},
{
"description": "tests types of a scalar float64 values",
"mnem": "vfpclasssd"
},
{
"description": "tests types of a scalar float32 values",
"mnem": "vfpclassss"
},
{
"description": "gather packed single, packed double with signed dword",
"mnem": "vgatherdpd"
},
{
"description": "gather packed sp fp values using signed dword/qword indices",
"mnem": "vgatherdps"
},
{
"description": "sparse prefetch packed sp/dp data values with signed dword, signed qword indices using t0 hint",
"mnem": "vgatherpf0dpd"
},
{
"description": "sparse prefetch packed sp/dp data values with signed dword, signed qword indices using t0 hint",
"mnem": "vgatherpf0dps"
},
{
"description": "sparse prefetch packed sp/dp data values with signed dword, signed qword indices using t0 hint",
"mnem": "vgatherpf0qpd"
},
{
"description": "sparse prefetch packed sp/dp data values with signed dword, signed qword indices using t0 hint",
"mnem": "vgatherpf0qps"
},
{
"description": "sparse prefetch packed sp/dp data values with signed dword, signed qword indices using t1 hint",
"mnem": "vgatherpf1dpd"
},
{
"description": "sparse prefetch packed sp/dp data values with signed dword, signed qword indices using t1 hint",
"mnem": "vgatherpf1dps"
},
{
"description": "sparse prefetch packed sp/dp data values with signed dword, signed qword indices using t1 hint",
"mnem": "vgatherpf1qpd"
},
{
"description": "sparse prefetch packed sp/dp data values with signed dword, signed qword indices using t1 hint",
"mnem": "vgatherpf1qps"
},
{
"description": "gather packed single, packed double with signed qword indices",
"mnem": "vgatherqpd"
},
{
"description": "gather packed single, packed double with signed qword indices",
"mnem": "vgatherqps"
},
{
"description": "convert exponents of packed dp fp values to dp fp values",
"mnem": "vgetexppd"
},
{
"description": "convert exponents of packed sp fp values to sp fp values",
"mnem": "vgetexpps"
},
{
"description": "convert exponents of scalar dp fp values to dp fp value",
"mnem": "vgetexpsd"
},
{
"description": "convert exponents of scalar sp fp values to sp fp value",
"mnem": "vgetexpss"
},
{
"description": "extract float64 vector of normalized mantissas from float64 vector",
"mnem": "vgetmantpd"
},
{
"description": "extract float32 vector of normalized mantissas from float32 vector",
"mnem": "vgetmantps"
},
{
"description": "extract float64 of normalized mantissas from float64 scalar",
"mnem": "vgetmantsd"
},
{
"description": "extract float32 vector of normalized mantissa from float32 vector",
"mnem": "vgetmantss"
},
{
"description": "packed double-fp horizontal add",
"mnem": "vhaddpd"
},
{
"description": "packed single-fp horizontal add",
"mnem": "vhaddps"
},
{
"description": "packed double-fp horizontal subtract",
"mnem": "vhsubpd"
},
{
"description": "packed single-fp horizontal subtract",
"mnem": "vhsubps"
},
{
"description": "insert packed floating-point values",
"mnem": "vinsertf128"
},
{
"description": "insert packed floating-point values",
"mnem": "vinsertf32x4"
},
{
"description": "insert packed floating-point values",
"mnem": "vinsertf32x8"
},
{
"description": "insert packed floating-point values",
"mnem": "vinsertf64x2"
},
{
"description": "insert packed floating-point values",
"mnem": "vinsertf64x4"
},
{
"description": "insert packed integer values",
"mnem": "vinserti128"
},
{
"description": "insert packed integer values",
"mnem": "vinserti32x4"
},
{
"description": "insert packed integer values",
"mnem": "vinserti32x8"
},
{
"description": "insert packed integer values",
"mnem": "vinserti64x2"
},
{
"description": "insert packed integer values",
"mnem": "vinserti64x4"
},
{
"description": "insert scalar single-precision floating-point value",
"mnem": "vinsertps"
},
{
"description": "load unaligned integer 128 bits",
"mnem": "vlddqu"
},
{
"description": "load mxcsr register",
"mnem": "vldmxcsr"
},
{
"description": "store selected bytes of double quadword",
"mnem": "vmaskmovdqu"
},
{
"description": "conditional simd packed loads and stores",
"mnem": "vmaskmovpd"
},
{
"description": "conditional simd packed loads and stores",
"mnem": "vmaskmovps"
},
{
"description": "maximum of packed double-precision floating-point values",
"mnem": "vmaxpd"
},
{
"description": "maximum of packed single-precision floating-point values",
"mnem": "vmaxps"
},
{
"description": "return maximum scalar double-precision floating-point value",
"mnem": "vmaxsd"
},
{
"description": "return maximum scalar single-precision floating-point value",
"mnem": "vmaxss"
},
{
"description": "call to vm monitor",
"mnem": "vmcall"
},
{
"description": "clear virtual-machine control structure",
"mnem": "vmclear"
},
{
"description": "minimum of packed double-precision floating-point values",
"mnem": "vminpd"
},
{
"description": "minimum of packed single-precision floating-point values",
"mnem": "vminps"
},
{
"description": "return minimum scalar double-precision floating-point value",
"mnem": "vminsd"
},
{
"description": "return minimum scalar single-precision floating-point value",
"mnem": "vminss"
},
{
"description": "launch virtual machine",
"mnem": "vmlaunch"
},
{
"description": "move aligned packed double-precision floating-point values",
"mnem": "vmovapd"
},
{
"description": "move aligned packed single-precision floating-point values",
"mnem": "vmovaps"
},
{
"description": "move doubleword/move quadword",
"mnem": "vmovd"
},
{
"description": "replicate double fp values",
"mnem": "vmovddup"
},
{
"description": "move aligned packed integer values",
"mnem": "vmovdqa"
},
{
"description": "move aligned packed integer values",
"mnem": "vmovdqa32"
},
{
"description": "move aligned packed integer values",
"mnem": "vmovdqa64"
},
{
"description": "move unaligned packed integer values",
"mnem": "vmovdqu"
},
{
"description": "move unaligned packed integer values",
"mnem": "vmovdqu16"
},
{
"description": "move unaligned packed integer values",
"mnem": "vmovdqu32"
},
{
"description": "move unaligned packed integer values",
"mnem": "vmovdqu64"
},
{
"description": "move unaligned packed integer values",
"mnem": "vmovdqu8"
},
{
"description": "move packed single-precision floating-point values high to low",
"mnem": "vmovhlps"
},
{
"description": "move high packed double-precision floating-point value",
"mnem": "vmovhpd"
},
{
"description": "move high packed single-precision floating-point values",
"mnem": "vmovhps"
},
{
"description": "move packed single-precision floating-point values low to high",
"mnem": "vmovlhps"
},
{
"description": "move low packed double-precision floating-point value",
"mnem": "vmovlpd"
},
{
"description": "move low packed single-precision floating-point values",
"mnem": "vmovlps"
},
{
"description": "extract packed double-precision floating-point sign mask",
"mnem": "vmovmskpd"
},
{
"description": "extract packed single-precision floating-point sign mask",
"mnem": "vmovmskps"
},
{
"description": "store packed integers using non-temporal hint",
"mnem": "vmovntdq"
},
{
"description": "load double quadword non-temporal aligned hint",
"mnem": "vmovntdqa"
},
{
"description": "store packed double-precision floating-point values using non-temporal hint",
"mnem": "vmovntpd"
},
{
"description": "store packed single-precision floating-point values using non-temporal hint",
"mnem": "vmovntps"
},
{
"description": "move quadword",
"mnem": "vmovq"
},
{
"description": "move or merge scalar double-precision floating-point value",
"mnem": "vmovsd"
},
{
"description": "replicate single fp values",
"mnem": "vmovshdup"
},
{
"description": "replicate single fp values",
"mnem": "vmovsldup"
},
{
"description": "move or merge scalar single-precision floating-point value",
"mnem": "vmovss"
},
{
"description": "move unaligned packed double-precision floating-point values",
"mnem": "vmovupd"
},
{
"description": "move unaligned packed single-precision floating-point values",
"mnem": "vmovups"
},
{
"description": "compute multiple packed sums of absolute difference",
"mnem": "vmpsadbw"
},
{
"description": "load pointer to virtual-machine control structure",
"mnem": "vmptrld"
},
{
"description": "store pointer to virtual-machine control structure",
"mnem": "vmptrst"
},
{
"description": "read field from virtual-machine control structure",
"mnem": "vmread"
},
{
"description": "resume virtual machine",
"mnem": "vmresume"
},
{
"description": "multiply packed double-precision floating-point values",
"mnem": "vmulpd"
},
{
"description": "multiply packed single-precision floating-point values",
"mnem": "vmulps"
},
{
"description": "multiply scalar double-precision floating-point value",
"mnem": "vmulsd"
},
{
"description": "multiply scalar single-precision floating-point values",
"mnem": "vmulss"
},
{
"description": "write field to virtual-machine control structure",
"mnem": "vmwrite"
},
{
"description": "leave vmx operation",
"mnem": "vmxoff"
},
{
"description": "enter vmx operation",
"mnem": "vmxon"
},
{
"description": "bitwise logical or of packed double precision floating-point values",
"mnem": "vorpd"
},
{
"description": "bitwise logical or of packed single precision floating-point values",
"mnem": "vorps"
},
{
"description": "packed absolute value",
"mnem": "vpabsb"
},
{
"description": "packed absolute value",
"mnem": "vpabsd"
},
{
"description": "packed absolute value",
"mnem": "vpabsq"
},
{
"description": "packed absolute value",
"mnem": "vpabsw"
},
{
"description": "pack with signed saturation",
"mnem": "vpackssdw"
},
{
"description": "pack with signed saturation",
"mnem": "vpacksswb"
},
{
"description": "pack with unsigned saturation",
"mnem": "vpackusdw"
},
{
"description": "pack with unsigned saturation",
"mnem": "vpackuswb"
},
{
"description": "add packed integers",
"mnem": "vpaddb"
},
{
"description": "add packed integers",
"mnem": "vpaddd"
},
{
"description": "add packed integers",
"mnem": "vpaddq"
},
{
"description": "add packed signed integers with signed saturation",
"mnem": "vpaddsb"
},
{
"description": "add packed signed integers with signed saturation",
"mnem": "vpaddsw"
},
{
"description": "add packed unsigned integers with unsigned saturation",
"mnem": "vpaddusb"
},
{
"description": "add packed unsigned integers with unsigned saturation",
"mnem": "vpaddusw"
},
{
"description": "add packed integers",
"mnem": "vpaddw"
},
{
"description": "packed align right",
"mnem": "vpalignr"
},
{
"description": "logical and",
"mnem": "vpand"
},
{
"description": "logical and",
"mnem": "vpandd"
},
{
"description": "logical and not",
"mnem": "vpandn"
},
{
"description": "logical and not",
"mnem": "vpandnd"
},
{
"description": "logical and not",
"mnem": "vpandnq"
},
{
"description": "logical and",
"mnem": "vpandq"
},
{
"description": "average packed integers",
"mnem": "vpavgb"
},
{
"description": "average packed integers",
"mnem": "vpavgw"
},
{
"description": "blend packed dwords",
"mnem": "vpblendd"
},
{
"description": "blend byte/word vectors using an opmask control",
"mnem": "vpblendmb"
},
{
"description": "blend int32/int64 vectors using an opmask control",
"mnem": "vpblendmd"
},
{
"description": "blend int32/int64 vectors using an opmask control",
"mnem": "vpblendmq"
},
{
"description": "blend byte/word vectors using an opmask control",
"mnem": "vpblendmw"
},
{
"description": "variable blend packed bytes",
"mnem": "vpblendvb"
},
{
"description": "blend packed words",
"mnem": "vpblendw"
},
{
"description": "load with broadcast integer data from general purpose register",
"mnem": "vpbroadcastb"
},
{
"description": "load with broadcast integer data from general purpose register",
"mnem": "vpbroadcastd"
},
{
"description": "broadcast mask to vector register",
"mnem": "vpbroadcastmb2q"
},
{
"description": "broadcast mask to vector register",
"mnem": "vpbroadcastmw2d"
},
{
"description": "load with broadcast integer data from general purpose register",
"mnem": "vpbroadcastq"
},
{
"description": "load with broadcast integer data from general purpose register",
"mnem": "vpbroadcastw"
},
{
"description": "pclmulqdq - carry-less multiplication quadword",
"mnem": "vpclmulqdq"
},
{
"description": "compare packed byte values into mask",
"mnem": "vpcmpb"
},
{
"description": "compare packed integer values into mask",
"mnem": "vpcmpd"
},
{
"description": "compare packed data for equal",
"mnem": "vpcmpeqb"
},
{
"description": "compare packed data for equal",
"mnem": "vpcmpeqd"
},
{
"description": "compare packed qword data for equal",
"mnem": "vpcmpeqq"
},
{
"description": "compare packed data for equal",
"mnem": "vpcmpeqw"
},
{
"description": "packed compare explicit length strings, return index",
"mnem": "vpcmpestri"
},
{
"description": "packed compare explicit length strings, return mask",
"mnem": "vpcmpestrm"
},
{
"description": "compare packed signed integers for greater than",
"mnem": "vpcmpgtb"
},
{
"description": "compare packed signed integers for greater than",
"mnem": "vpcmpgtd"
},
{
"description": "compare packed data for greater than",
"mnem": "vpcmpgtq"
},
{
"description": "compare packed signed integers for greater than",
"mnem": "vpcmpgtw"
},
{
"description": "packed compare implicit length strings, return index",
"mnem": "vpcmpistri"
},
{
"description": "packed compare implicit length strings, return mask",
"mnem": "vpcmpistrm"
},
{
"description": "compare packed integer values into mask",
"mnem": "vpcmpq"
},
{
"description": "compare packed byte values into mask",
"mnem": "vpcmpub"
},
{
"description": "compare packed integer values into mask",
"mnem": "vpcmpud"
},
{
"description": "compare packed integer values into mask",
"mnem": "vpcmpuq"
},
{
"description": "compare packed word values into mask",
"mnem": "vpcmpuw"
},
{
"description": "compare packed word values into mask",
"mnem": "vpcmpw"
},
{
"description": "store sparse packed doubleword integer values into dense memory/register",
"mnem": "vpcompressd"
},
{
"description": "store sparse packed quadword integer values into dense memory/register",
"mnem": "vpcompressq"
},
{
"description": "detect conflicts within a vector of packed dword/qword values into dense memory/ register",
"mnem": "vpconflictd"
},
{
"description": "detect conflicts within a vector of packed dword/qword values into dense memory/ register",
"mnem": "vpconflictq"
},
{
"description": "permute floating-point values",
"mnem": "vperm2f128"
},
{
"description": "permute integer values",
"mnem": "vperm2i128"
},
{
"description": "permute packed doublewords/words elements",
"mnem": "vpermd"
},
{
"description": "full permute from two tables overwriting the index",
"mnem": "vpermi2d"
},
{
"description": "full permute from two tables overwriting the index",
"mnem": "vpermi2pd"
},
{
"description": "full permute from two tables overwriting the index",
"mnem": "vpermi2ps"
},
{
"description": "full permute from two tables overwriting the index",
"mnem": "vpermi2q"
},
{
"description": "full permute from two tables overwriting the index",
"mnem": "vpermi2w"
},
{
"description": "permute in-lane of pairs of double-precision floating-point values",
"mnem": "vpermilpd"
},
{
"description": "permute in-lane of quadruples of single-precision floating-point values",
"mnem": "vpermilps"
},
{
"description": "permute double-precision floating-point elements",
"mnem": "vpermpd"
},
{
"description": "permute single-precision floating-point elements",
"mnem": "vpermps"
},
{
"description": "qwords element permutation",
"mnem": "vpermq"
},
{
"description": "permute packed doublewords/words elements",
"mnem": "vpermw"
},
{
"description": "load sparse packed doubleword integer values from dense memory / register",
"mnem": "vpexpandd"
},
{
"description": "load sparse packed quadword integer values from dense memory / register",
"mnem": "vpexpandq"
},
{
"description": "extract byte/dword/qword",
"mnem": "vpextrb"
},
{
"description": "extract byte/dword/qword",
"mnem": "vpextrd"
},
{
"description": "extract byte/dword/qword",
"mnem": "vpextrq"
},
{
"description": "extract word",
"mnem": "vpextrw"
},
{
"description": "gather packed dword values using signed dword/qword indices",
"mnem": "vpgatherdd"
},
{
"description": "gather packed qword values using signed dword/qword indices",
"mnem": "vpgatherdq"
},
{
"description": "gather packed dword, packed qword with signed qword indices",
"mnem": "vpgatherqd"
},
{
"description": "gather packed dword, packed qword with signed qword indices",
"mnem": "vpgatherqq"
},
{
"description": "packed horizontal add",
"mnem": "vphaddd"
},
{
"description": "packed horizontal add and saturate",
"mnem": "vphaddsw"
},
{
"description": "packed horizontal add",
"mnem": "vphaddw"
},
{
"description": "packed horizontal word minimum",
"mnem": "vphminposuw"
},
{
"description": "packed horizontal subtract",
"mnem": "vphsubd"
},
{
"description": "packed horizontal subtract and saturate",
"mnem": "vphsubsw"
},
{
"description": "packed horizontal subtract",
"mnem": "vphsubw"
},
{
"description": "insert byte/dword/qword",
"mnem": "vpinsrb"
},
{
"description": "insert byte/dword/qword",
"mnem": "vpinsrd"
},
{
"description": "insert byte/dword/qword",
"mnem": "vpinsrq"
},
{
"description": "insert word",
"mnem": "vpinsrw"
},
{
"description": "count the number of leading zero bits for packed dword, packed qword values",
"mnem": "vplzcntd"
},
{
"description": "count the number of leading zero bits for packed dword, packed qword values",
"mnem": "vplzcntq"
},
{
"description": "multiply and add packed signed and unsigned bytes",
"mnem": "vpmaddubsw"
},
{
"description": "multiply and add packed integers",
"mnem": "vpmaddwd"
},
{
"description": "conditional simd integer packed loads and stores",
"mnem": "vpmaskmovd"
},
{
"description": "conditional simd integer packed loads and stores",
"mnem": "vpmaskmovq"
},
{
"description": "maximum of packed signed integers",
"mnem": "vpmaxsb"
},
{
"description": "maximum of packed signed integers",
"mnem": "vpmaxsd"
},
{
"description": "maximum of packed signed integers",
"mnem": "vpmaxsq"
},
{
"description": "maximum of packed signed integers",
"mnem": "vpmaxsw"
},
{
"description": "maximum of packed unsigned integers",
"mnem": "vpmaxub"
},
{
"description": "maximum of packed unsigned integers",
"mnem": "vpmaxud"
},
{
"description": "maximum of packed unsigned integers",
"mnem": "vpmaxuq"
},
{
"description": "maximum of packed unsigned integers",
"mnem": "vpmaxuw"
},
{
"description": "minimum of packed signed integers",
"mnem": "vpminsb"
},
{
"description": "minimum of packed signed integers",
"mnem": "vpminsd"
},
{
"description": "minimum of packed signed integers",
"mnem": "vpminsq"
},
{
"description": "minimum of packed signed integers",
"mnem": "vpminsw"
},
{
"description": "minimum of packed unsigned integers",
"mnem": "vpminub"
},
{
"description": "minimum of packed unsigned integers",
"mnem": "vpminud"
},
{
"description": "minimum of packed unsigned integers",
"mnem": "vpminuq"
},
{
"description": "minimum of packed unsigned integers",
"mnem": "vpminuw"
},
{
"description": "convert a vector register to a mask",
"mnem": "vpmovb2m"
},
{
"description": "convert a vector register to a mask",
"mnem": "vpmovd2m"
},
{
"description": "down convert dword to byte",
"mnem": "vpmovdb"
},
{
"description": "down convert dword to word",
"mnem": "vpmovdw"
},
{
"description": "convert a mask register to a vector register",
"mnem": "vpmovm2b"
},
{
"description": "convert a mask register to a vector register",
"mnem": "vpmovm2d"
},
{
"description": "convert a mask register to a vector register",
"mnem": "vpmovm2q"
},
{
"description": "convert a mask register to a vector register",
"mnem": "vpmovm2w"
},
{
"description": "move byte mask",
"mnem": "vpmovmskb"
},
{
"description": "convert a vector register to a mask",
"mnem": "vpmovq2m"
},
{
"description": "down convert qword to byte",
"mnem": "vpmovqb"
},
{
"description": "down convert qword to dword",
"mnem": "vpmovqd"
},
{
"description": "down convert qword to word",
"mnem": "vpmovqw"
},
{
"description": "down convert dword to byte",
"mnem": "vpmovsdb"
},
{
"description": "down convert dword to word",
"mnem": "vpmovsdw"
},
{
"description": "down convert qword to byte",
"mnem": "vpmovsqb"
},
{
"description": "down convert qword to dword",
"mnem": "vpmovsqd"
},
{
"description": "down convert qword to word",
"mnem": "vpmovsqw"
},
{
"description": "down convert word to byte",
"mnem": "vpmovswb"
},
{
"description": "packed move with sign extend",
"mnem": "vpmovsxbd"
},
{
"description": "packed move with sign extend",
"mnem": "vpmovsxbq"
},
{
"description": "packed move with sign extend",
"mnem": "vpmovsxbw"
},
{
"description": "packed move with sign extend",
"mnem": "vpmovsxdq"
},
{
"description": "packed move with sign extend",
"mnem": "vpmovsxwd"
},
{
"description": "packed move with sign extend",
"mnem": "vpmovsxwq"
},
{
"description": "down convert dword to byte",
"mnem": "vpmovusdb"
},
{
"description": "down convert dword to word",
"mnem": "vpmovusdw"
},
{
"description": "down convert qword to byte",
"mnem": "vpmovusqb"
},
{
"description": "down convert qword to dword",
"mnem": "vpmovusqd"
},
{
"description": "down convert qword to word",
"mnem": "vpmovusqw"
},
{
"description": "down convert word to byte",
"mnem": "vpmovuswb"
},
{
"description": "convert a vector register to a mask",
"mnem": "vpmovw2m"
},
{
"description": "down convert word to byte",
"mnem": "vpmovwb"
},
{
"description": "packed move with zero extend",
"mnem": "vpmovzxbd"
},
{
"description": "packed move with zero extend",
"mnem": "vpmovzxbq"
},
{
"description": "packed move with zero extend",
"mnem": "vpmovzxbw"
},
{
"description": "packed move with zero extend",
"mnem": "vpmovzxdq"
},
{
"description": "packed move with zero extend",
"mnem": "vpmovzxwd"
},
{
"description": "packed move with zero extend",
"mnem": "vpmovzxwq"
},
{
"description": "multiply packed doubleword integers",
"mnem": "vpmuldq"
},
{
"description": "packed multiply high with round and scale",
"mnem": "vpmulhrsw"
},
{
"description": "multiply packed unsigned integers and store high result",
"mnem": "vpmulhuw"
},
{
"description": "multiply packed signed integers and store high result",
"mnem": "vpmulhw"
},
{
"description": "multiply packed integers and store low result",
"mnem": "vpmulld"
},
{
"description": "multiply packed integers and store low result",
"mnem": "vpmullq"
},
{
"description": "multiply packed signed integers and store low result",
"mnem": "vpmullw"
},
{
"description": "multiply packed unsigned doubleword integers",
"mnem": "vpmuludq"
},
{
"description": "bitwise logical or",
"mnem": "vpor"
},
{
"description": "bitwise logical or",
"mnem": "vpord"
},
{
"description": "bitwise logical or",
"mnem": "vporq"
},
{
"description": "bit rotate left",
"mnem": "vprold"
},
{
"description": "bit rotate left",
"mnem": "vprolq"
},
{
"description": "bit rotate left",
"mnem": "vprolvd"
},
{
"description": "bit rotate left",
"mnem": "vprolvq"
},
{
"description": "bit rotate right",
"mnem": "vprord"
},
{
"description": "bit rotate right",
"mnem": "vprorq"
},
{
"description": "bit rotate right",
"mnem": "vprorvd"
},
{
"description": "bit rotate right",
"mnem": "vprorvq"
},
{
"description": "compute sum of absolute differences",
"mnem": "vpsadbw"
},
{
"description": "scatter packed dword, packed qword with signed dword, signed qword indices",
"mnem": "vpscatterdd"
},
{
"description": "scatter packed dword, packed qword with signed dword, signed qword indices",
"mnem": "vpscatterdq"
},
{
"description": "scatter packed dword, packed qword with signed dword, signed qword indices",
"mnem": "vpscatterqd"
},
{
"description": "scatter packed dword, packed qword with signed dword, signed qword indices",
"mnem": "vpscatterqq"
},
{
"description": "packed shuffle bytes",
"mnem": "vpshufb"
},
{
"description": "shuffle packed doublewords",
"mnem": "vpshufd"
},
{
"description": "shuffle packed high words",
"mnem": "vpshufhw"
},
{
"description": "shuffle packed low words",
"mnem": "vpshuflw"
},
{
"description": "packed sign",
"mnem": "vpsignb"
},
{
"description": "packed sign",
"mnem": "vpsignd"
},
{
"description": "packed sign",
"mnem": "vpsignw"
},
{
"description": "shift packed data left logical",
"mnem": "vpslld"
},
{
"description": "shift double quadword left logical",
"mnem": "vpslldq"
},
{
"description": "shift packed data left logical",
"mnem": "vpsllq"
},
{
"description": "variable bit shift left logical",
"mnem": "vpsllvd"
},
{
"description": "variable bit shift left logical",
"mnem": "vpsllvq"
},
{
"description": "variable bit shift left logical",
"mnem": "vpsllvw"
},
{
"description": "shift packed data left logical",
"mnem": "vpsllw"
},
{
"description": "shift packed data right arithmetic",
"mnem": "vpsrad"
},
{
"description": "shift packed data right arithmetic",
"mnem": "vpsraq"
},
{
"description": "variable bit shift right arithmetic",
"mnem": "vpsravd"
},
{
"description": "variable bit shift right arithmetic",
"mnem": "vpsravq"
},
{
"description": "variable bit shift right arithmetic",
"mnem": "vpsravw"
},
{
"description": "shift packed data right arithmetic",
"mnem": "vpsraw"
},
{
"description": "shift packed data right logical",
"mnem": "vpsrld"
},
{
"description": "shift double quadword right logical",
"mnem": "vpsrldq"
},
{
"description": "shift packed data right logical",
"mnem": "vpsrlq"
},
{
"description": "variable bit shift right logical",
"mnem": "vpsrlvd"
},
{
"description": "variable bit shift right logical",
"mnem": "vpsrlvq"
},
{
"description": "variable bit shift right logical",
"mnem": "vpsrlvw"
},
{
"description": "shift packed data right logical",
"mnem": "vpsrlw"
},
{
"description": "subtract packed integers",
"mnem": "vpsubb"
},
{
"description": "subtract packed integers",
"mnem": "vpsubd"
},
{
"description": "subtract packed quadword integers",
"mnem": "vpsubq"
},
{
"description": "subtract packed signed integers with signed saturation",
"mnem": "vpsubsb"
},
{
"description": "subtract packed signed integers with signed saturation",
"mnem": "vpsubsw"
},
{
"description": "subtract packed unsigned integers with unsigned saturation",
"mnem": "vpsubusb"
},
{
"description": "subtract packed unsigned integers with unsigned saturation",
"mnem": "vpsubusw"
},
{
"description": "subtract packed integers",
"mnem": "vpsubw"
},
{
"description": "bitwise ternary logic",
"mnem": "vpternlogd"
},
{
"description": "bitwise ternary logic",
"mnem": "vpternlogq"
},
{
"description": "ptest- logical compare",
"mnem": "vptest"
},
{
"description": "logical and and set mask",
"mnem": "vptestmb"
},
{
"description": "logical and and set mask",
"mnem": "vptestmd"
},
{
"description": "logical and and set mask",
"mnem": "vptestmq"
},
{
"description": "logical and and set mask",
"mnem": "vptestmw"
},
{
"description": "logical nand and set",
"mnem": "vptestnmb"
},
{
"description": "logical nand and set",
"mnem": "vptestnmd"
},
{
"description": "logical nand and set",
"mnem": "vptestnmq"
},
{
"description": "logical nand and set",
"mnem": "vptestnmw"
},
{
"description": "unpack high data",
"mnem": "vpunpckhbw"
},
{
"description": "unpack high data",
"mnem": "vpunpckhdq"
},
{
"description": "unpack high data",
"mnem": "vpunpckhqdq"
},
{
"description": "unpack high data",
"mnem": "vpunpckhwd"
},
{
"description": "unpack low data",
"mnem": "vpunpcklbw"
},
{
"description": "unpack low data",
"mnem": "vpunpckldq"
},
{
"description": "unpack low data",
"mnem": "vpunpcklqdq"
},
{
"description": "unpack low data",
"mnem": "vpunpcklwd"
},
{
"description": "logical exclusive or",
"mnem": "vpxor"
},
{
"description": "logical exclusive or",
"mnem": "vpxord"
},
{
"description": "logical exclusive or",
"mnem": "vpxorq"
},
{
"description": "range restriction calculation for packed pairs of float64 values",
"mnem": "vrangepd"
},
{
"description": "range restriction calculation for packed pairs of float32 values",
"mnem": "vrangeps"
},
{
"description": "range restriction calculation from a pair of scalar float64 values",
"mnem": "vrangesd"
},
{
"description": "range restriction calculation from a pair of scalar float32 values",
"mnem": "vrangess"
},
{
"description": "compute approximate reciprocals of packed float64 values",
"mnem": "vrcp14pd"
},
{
"description": "compute approximate reciprocals of packed float32 values",
"mnem": "vrcp14ps"
},
{
"description": "compute approximate reciprocal of scalar float64 value",
"mnem": "vrcp14sd"
},
{
"description": "compute approximate reciprocal of scalar float32 value",
"mnem": "vrcp14ss"
},
{
"description": "approximation to the reciprocal of packed double-precision floating-point values with less than 2^-28 relative error",
"mnem": "vrcp28pd"
},
{
"description": "approximation to the reciprocal of packed single-precision floating-point values with less than 2^-28 relative error",
"mnem": "vrcp28ps"
},
{
"description": "approximation to the reciprocal of scalar double-precision floating-point value with less than 2^-28 relative error",
"mnem": "vrcp28sd"
},
{
"description": "approximation to the reciprocal of scalar single-precision floating-point value with less than 2^-28 relative error",
"mnem": "vrcp28ss"
},
{
"description": "compute reciprocals of packed single-precision floating-point values",
"mnem": "vrcpps"
},
{
"description": "compute reciprocal of scalar single-precision floating-point values",
"mnem": "vrcpss"
},
{
"description": "perform reduction transformation on packed float64 values",
"mnem": "vreducepd"
},
{
"description": "perform reduction transformation on packed float32 values",
"mnem": "vreduceps"
},
{
"description": "perform a reduction transformation on a scalar float64 value",
"mnem": "vreducesd"
},
{
"description": "perform a reduction transformation on a scalar float32 value",
"mnem": "vreducess"
},
{
"description": "round packed float64 values to include a given number of fraction bits",
"mnem": "vrndscalepd"
},
{
"description": "round packed float32 values to include a given number of fraction bits",
"mnem": "vrndscaleps"
},
{
"description": "round scalar float64 value to include a given number of fraction bits",
"mnem": "vrndscalesd"
},
{
"description": "round scalar float32 value to include a given number of fraction bits",
"mnem": "vrndscaless"
},
{
"description": "round packed double precision floating-point values",
"mnem": "vroundpd"
},
{
"description": "round packed single precision floating-point values",
"mnem": "vroundps"
},
{
"description": "round scalar double precision floating-point values",
"mnem": "vroundsd"
},
{
"description": "round scalar single precision floating-point values",
"mnem": "vroundss"
},
{
"description": "compute approximate reciprocals of square roots of packed float64 values",
"mnem": "vrsqrt14pd"
},
{
"description": "compute approximate reciprocals of square roots of packed float32 values",
"mnem": "vrsqrt14ps"
},
{
"description": "compute approximate reciprocal of square root of scalar float64 value",
"mnem": "vrsqrt14sd"
},
{
"description": "compute approximate reciprocal of square root of scalar float32 value",
"mnem": "vrsqrt14ss"
},
{
"description": "approximation to the reciprocal square root of packed double-precision floating-point values with less than 2^-28 relative error",
"mnem": "vrsqrt28pd"
},
{
"description": "approximation to the reciprocal square root of packed single-precision floating-point values with less than 2^-28 relative error",
"mnem": "vrsqrt28ps"
},
{
"description": "approximation to the reciprocal square root of scalar double-precision floating-point value with less than 2^-28 relative error",
"mnem": "vrsqrt28sd"
},
{
"description": "approximation to the reciprocal square root of scalar single-precision floating-point value with less than 2^-28 relative error",
"mnem": "vrsqrt28ss"
},
{
"description": "compute reciprocals of square roots of packed single-precision floating-point values",
"mnem": "vrsqrtps"
},
{
"description": "compute reciprocal of square root of scalar single-precision floating-point value",
"mnem": "vrsqrtss"
},
{
"description": "scale packed float64 values with float64 values",
"mnem": "vscalefpd"
},
{
"description": "scale packed float32 values with float32 values",
"mnem": "vscalefps"
},
{
"description": "scale scalar float64 values with float64 values",
"mnem": "vscalefsd"
},
{
"description": "scale scalar float32 value with float32 value",
"mnem": "vscalefss"
},
{
"description": "scatter packed single, packed double with signed dword and qword indices",
"mnem": "vscatterdpd"
},
{
"description": "scatter packed single, packed double with signed dword and qword indices",
"mnem": "vscatterdps"
},
{
"description": "sparse prefetch packed sp/dp data values with signed dword, signed qword indices using t0 hint with intent to write",
"mnem": "vscatterpf0dpd"
},
{
"description": "sparse prefetch packed sp/dp data values with signed dword, signed qword indices using t0 hint with intent to write",
"mnem": "vscatterpf0dps"
},
{
"description": "sparse prefetch packed sp/dp data values with signed dword, signed qword indices using t0 hint with intent to write",
"mnem": "vscatterpf0qpd"
},
{
"description": "sparse prefetch packed sp/dp data values with signed dword, signed qword indices using t0 hint with intent to write",
"mnem": "vscatterpf0qps"
},
{
"description": "sparse prefetch packed sp/dp data values with signed dword, signed qword indices using t1 hint with intent to write",
"mnem": "vscatterpf1dpd"
},
{
"description": "sparse prefetch packed sp/dp data values with signed dword, signed qword indices using t1 hint with intent to write",
"mnem": "vscatterpf1dps"
},
{
"description": "sparse prefetch packed sp/dp data values with signed dword, signed qword indices using t1 hint with intent to write",
"mnem": "vscatterpf1qpd"
},
{
"description": "sparse prefetch packed sp/dp data values with signed dword, signed qword indices using t1 hint with intent to write",
"mnem": "vscatterpf1qps"
},
{
"description": "scatter packed single, packed double with signed dword and qword indices",
"mnem": "vscatterqpd"
},
{
"description": "scatter packed single, packed double with signed dword and qword indices",
"mnem": "vscatterqps"
},
{
"description": "shuffle packed values at 128-bit granularity",
"mnem": "vshuff32x4"
},
{
"description": "shuffle packed values at 128-bit granularity",
"mnem": "vshuff64x2"
},
{
"description": "shuffle packed values at 128-bit granularity",
"mnem": "vshufi32x4"
},
{
"description": "shuffle packed values at 128-bit granularity",
"mnem": "vshufi64x2"
},
{
"description": "packed interleave shuffle of pairs of double-precision floating-point values",
"mnem": "vshufpd"
},
{
"description": "packed interleave shuffle of quadruplets of single-precision floating-point values",
"mnem": "vshufps"
},
{
"description": "square root of double-precision floating-point values",
"mnem": "vsqrtpd"
},
{
"description": "square root of single-precision floating-point values",
"mnem": "vsqrtps"
},
{
"description": "compute square root of scalar double-precision floating-point value",
"mnem": "vsqrtsd"
},
{
"description": "compute square root of scalar single-precision value",
"mnem": "vsqrtss"
},
{
"description": "store mxcsr register state",
"mnem": "vstmxcsr"
},
{
"description": "subtract packed double-precision floating-point values",
"mnem": "vsubpd"
},
{
"description": "subtract packed single-precision floating-point values",
"mnem": "vsubps"
},
{
"description": "subtract scalar double-precision floating-point value",
"mnem": "vsubsd"
},
{
"description": "subtract scalar single-precision floating-point value",
"mnem": "vsubss"
},
{
"description": "packed bit test",
"mnem": "vtestpd"
},
{
"description": "packed bit test",
"mnem": "vtestps"
},
{
"description": "unordered compare scalar double-precision floating-point values and set eflags",
"mnem": "vucomisd"
},
{
"description": "unordered compare scalar single-precision floating-point values and set eflags",
"mnem": "vucomiss"
},
{
"description": "unpack and interleave high packed double-precision floating-point values",
"mnem": "vunpckhpd"
},
{
"description": "unpack and interleave high packed single-precision floating-point values",
"mnem": "vunpckhps"
},
{
"description": "unpack and interleave low packed double-precision floating-point values",
"mnem": "vunpcklpd"
},
{
"description": "unpack and interleave low packed single-precision floating-point values",
"mnem": "vunpcklps"
},
{
"description": "bitwise logical xor of packed double precision floating-point values",
"mnem": "vxorpd"
},
{
"description": "bitwise logical xor of packed single precision floating-point values",
"mnem": "vxorps"
},
{
"description": "zero all ymm registers",
"mnem": "vzeroall"
},
{
"description": "zero upper bits of ymm registers",
"mnem": "vzeroupper"
},
{
"description": "stop process execution until TEST pin activated",
"mnem": "wait"
},
{
"description": "write back and invalidate cache",
"mnem": "wbinvd"
},
{
"description": "write fs/gs segment base",
"mnem": "wrfsbase"
},
{
"description": "write fs/gs segment base",
"mnem": "wrgsbase"
},
{
"description": "write to model specific register",
"mnem": "wrmsr"
},
{
"description": "write data to user page key register",
"mnem": "wrpkru"
},
{
"description": "transactional abort",
"mnem": "xabort"
},
{
"description": "hardware lock elision prefix hints",
"mnem": "xacquire"
},
{
"description": "exchange and add",
"mnem": "xadd"
},
{
"description": "transactional begin",
"mnem": "xbegin"
},
{
"description": "exchange register/memory with register",
"mnem": "xchg"
},
{
"description": "transactional end",
"mnem": "xend"
},
{
"description": "get value of extended control register",
"mnem": "xgetbv"
},
{
"description": "table look-up translation",
"mnem": "xlat"
},
{
"description": "table look-up translation",
"mnem": "xlatb"
},
{
"description": "logical exclusive or",
"mnem": "xor"
},
{
"description": "bitwise logical xor for double-fp values",
"mnem": "xorpd"
},
{
"description": "bitwise logical xor for single-fp values",
"mnem": "xorps"
},
{
"description": "hardware lock elision prefix hints",
"mnem": "xrelease"
},
{
"description": "restore processor extended states",
"mnem": "xrstor"
},
{
"description": "restore processor extended states supervisor",
"mnem": "xrstors"
},
{
"description": "save processor extended states",
"mnem": "xsave"
},
{
"description": "save processor extended states with compaction",
"mnem": "xsavec"
},
{
"description": "save processor extended states optimized",
"mnem": "xsaveopt"
},
{
"description": "save processor extended states supervisor",
"mnem": "xsaves"
},
{
"description": "set extended control register",
"mnem": "xsetbv"
},
{
"description": "test if in transactional execution",
"mnem": "xtest"
}
]
} |
Text | x64dbg-development/bin/ntstatusdb.txt | 0x00000000 STATUS_SUCCESS
0x00000001 STATUS_WAIT_1
0x00000002 STATUS_WAIT_2
0x00000003 STATUS_WAIT_3
0x0000003F STATUS_WAIT_63
0x00000080 STATUS_ABANDONED
0x000000BF STATUS_ABANDONED_WAIT_63
0x000000C0 STATUS_USER_APC
0x000000FF STATUS_ALREADY_COMPLETE
0x00000100 STATUS_KERNEL_APC
0x00000101 STATUS_ALERTED
0x00000102 STATUS_TIMEOUT
0x00000103 STATUS_PENDING
0x00000104 STATUS_REPARSE
0x00000105 STATUS_MORE_ENTRIES
0x00000106 STATUS_NOT_ALL_ASSIGNED
0x00000107 STATUS_SOME_NOT_MAPPED
0x00000108 STATUS_OPLOCK_BREAK_IN_PROGRESS
0x00000109 STATUS_VOLUME_MOUNTED
0x0000010A STATUS_RXACT_COMMITTED
0x0000010B STATUS_NOTIFY_CLEANUP
0x0000010C STATUS_NOTIFY_ENUM_DIR
0x0000010D STATUS_NO_QUOTAS_FOR_ACCOUNT
0x0000010E STATUS_PRIMARY_TRANSPORT_CONNECT_FAILED
0x00000110 STATUS_PAGE_FAULT_TRANSITION
0x00000111 STATUS_PAGE_FAULT_DEMAND_ZERO
0x00000112 STATUS_PAGE_FAULT_COPY_ON_WRITE
0x00000113 STATUS_PAGE_FAULT_GUARD_PAGE
0x00000114 STATUS_PAGE_FAULT_PAGING_FILE
0x00000115 STATUS_CACHE_PAGE_LOCKED
0x00000116 STATUS_CRASH_DUMP
0x00000117 STATUS_BUFFER_ALL_ZEROS
0x00000118 STATUS_REPARSE_OBJECT
0x00000119 STATUS_RESOURCE_REQUIREMENTS_CHANGED
0x00000120 STATUS_TRANSLATION_COMPLETE
0x00000121 STATUS_DS_MEMBERSHIP_EVALUATED_LOCALLY
0x00000122 STATUS_NOTHING_TO_TERMINATE
0x00000123 STATUS_PROCESS_NOT_IN_JOB
0x00000124 STATUS_PROCESS_IN_JOB
0x00000125 STATUS_VOLSNAP_HIBERNATE_READY
0x00000126 STATUS_FSFILTER_OP_COMPLETED_SUCCESSFULLY
0x00000127 STATUS_INTERRUPT_VECTOR_ALREADY_CONNECTED
0x00000128 STATUS_INTERRUPT_STILL_CONNECTED
0x00000129 STATUS_PROCESS_CLONED
0x0000012A STATUS_FILE_LOCKED_WITH_ONLY_READERS
0x0000012B STATUS_FILE_LOCKED_WITH_WRITERS
0x0000012C STATUS_VALID_IMAGE_HASH
0x0000012D STATUS_VALID_CATALOG_HASH
0x0000012E STATUS_VALID_STRONG_CODE_HASH
0x0000012F STATUS_GHOSTED
0x00000202 STATUS_RESOURCEMANAGER_READ_ONLY
0x00000210 STATUS_RING_PREVIOUSLY_EMPTY
0x00000211 STATUS_RING_PREVIOUSLY_FULL
0x00000212 STATUS_RING_PREVIOUSLY_ABOVE_QUOTA
0x00000213 STATUS_RING_NEWLY_EMPTY
0x00000214 STATUS_RING_SIGNAL_OPPOSITE_ENDPOINT
0x00000215 STATUS_OPLOCK_SWITCHED_TO_NEW_HANDLE
0x00000216 STATUS_OPLOCK_HANDLE_CLOSED
0x00000367 STATUS_WAIT_FOR_OPLOCK
0x00000368 STATUS_REPARSE_GLOBAL
0x00010001 DBG_EXCEPTION_HANDLED
0x00010002 DBG_CONTINUE
0x001C0001 STATUS_FLT_IO_COMPLETE
0x00293000 STATUS_RTPM_CONTEXT_CONTINUE
0x00293001 STATUS_RTPM_CONTEXT_COMPLETE
0x00350059 STATUS_HV_PENDING_PAGE_REQUESTS
0x00E70000 STATUS_SPACES_REPAIRED
0x00E70001 STATUS_SPACES_PAUSE
0x00E70002 STATUS_SPACES_COMPLETE
0x00E70003 STATUS_SPACES_REDIRECT
0x40000000 STATUS_OBJECT_NAME_EXISTS
0x40000001 STATUS_THREAD_WAS_SUSPENDED
0x40000002 STATUS_WORKING_SET_LIMIT_RANGE
0x40000003 STATUS_IMAGE_NOT_AT_BASE
0x40000004 STATUS_RXACT_STATE_CREATED
0x40000005 STATUS_SEGMENT_NOTIFICATION
0x40000006 STATUS_LOCAL_USER_SESSION_KEY
0x40000007 STATUS_BAD_CURRENT_DIRECTORY
0x40000008 STATUS_SERIAL_MORE_WRITES
0x40000009 STATUS_REGISTRY_RECOVERED
0x4000000A STATUS_FT_READ_RECOVERY_FROM_BACKUP
0x4000000B STATUS_FT_WRITE_RECOVERY
0x4000000C STATUS_SERIAL_COUNTER_TIMEOUT
0x4000000D STATUS_NULL_LM_PASSWORD
0x4000000E STATUS_IMAGE_MACHINE_TYPE_MISMATCH
0x4000000F STATUS_RECEIVE_PARTIAL
0x40000010 STATUS_RECEIVE_EXPEDITED
0x40000011 STATUS_RECEIVE_PARTIAL_EXPEDITED
0x40000012 STATUS_EVENT_DONE
0x40000013 STATUS_EVENT_PENDING
0x40000014 STATUS_CHECKING_FILE_SYSTEM
0x40000015 STATUS_FATAL_APP_EXIT
0x40000016 STATUS_PREDEFINED_HANDLE
0x40000017 STATUS_WAS_UNLOCKED
0x40000018 STATUS_SERVICE_NOTIFICATION
0x40000019 STATUS_WAS_LOCKED
0x4000001A STATUS_LOG_HARD_ERROR
0x4000001B STATUS_ALREADY_WIN32
0x4000001C STATUS_WX86_UNSIMULATE
0x4000001D STATUS_WX86_CONTINUE
0x4000001E STATUS_WX86_SINGLE_STEP
0x4000001F STATUS_WX86_BREAKPOINT
0x40000020 STATUS_WX86_EXCEPTION_CONTINUE
0x40000021 STATUS_WX86_EXCEPTION_LASTCHANCE
0x40000022 STATUS_WX86_EXCEPTION_CHAIN
0x40000023 STATUS_IMAGE_MACHINE_TYPE_MISMATCH_EXE
0x40000024 STATUS_NO_YIELD_PERFORMED
0x40000025 STATUS_TIMER_RESUME_IGNORED
0x40000026 STATUS_ARBITRATION_UNHANDLED
0x40000027 STATUS_CARDBUS_NOT_SUPPORTED
0x40000028 STATUS_WX86_CREATEWX86TIB
0x40000029 STATUS_MP_PROCESSOR_MISMATCH
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0xC000015B STATUS_LOGON_TYPE_NOT_GRANTED
0xC000015C STATUS_NOT_REGISTRY_FILE
0xC000015D STATUS_NT_CROSS_ENCRYPTION_REQUIRED
0xC000015E STATUS_DOMAIN_CTRLR_CONFIG_ERROR
0xC000015F STATUS_FT_MISSING_MEMBER
0xC0000160 STATUS_ILL_FORMED_SERVICE_ENTRY
0xC0000161 STATUS_ILLEGAL_CHARACTER
0xC0000162 STATUS_UNMAPPABLE_CHARACTER
0xC0000163 STATUS_UNDEFINED_CHARACTER
0xC0000164 STATUS_FLOPPY_VOLUME
0xC0000165 STATUS_FLOPPY_ID_MARK_NOT_FOUND
0xC0000166 STATUS_FLOPPY_WRONG_CYLINDER
0xC0000167 STATUS_FLOPPY_UNKNOWN_ERROR
0xC0000168 STATUS_FLOPPY_BAD_REGISTERS
0xC0000169 STATUS_DISK_RECALIBRATE_FAILED
0xC000016A STATUS_DISK_OPERATION_FAILED
0xC000016B STATUS_DISK_RESET_FAILED
0xC000016C STATUS_SHARED_IRQ_BUSY
0xC000016D STATUS_FT_ORPHANING
0xC000016E STATUS_BIOS_FAILED_TO_CONNECT_INTERRUPT
0xC0000172 STATUS_PARTITION_FAILURE
0xC0000173 STATUS_INVALID_BLOCK_LENGTH
0xC0000174 STATUS_DEVICE_NOT_PARTITIONED
0xC0000175 STATUS_UNABLE_TO_LOCK_MEDIA
0xC0000176 STATUS_UNABLE_TO_UNLOAD_MEDIA
0xC0000177 STATUS_EOM_OVERFLOW
0xC0000178 STATUS_NO_MEDIA
0xC000017A STATUS_NO_SUCH_MEMBER
0xC000017B STATUS_INVALID_MEMBER
0xC000017C STATUS_KEY_DELETED
0xC000017D STATUS_NO_LOG_SPACE
0xC000017E STATUS_TOO_MANY_SIDS
0xC000017F STATUS_LM_CROSS_ENCRYPTION_REQUIRED
0xC0000180 STATUS_KEY_HAS_CHILDREN
0xC0000181 STATUS_CHILD_MUST_BE_VOLATILE
0xC0000182 STATUS_DEVICE_CONFIGURATION_ERROR
0xC0000183 STATUS_DRIVER_INTERNAL_ERROR
0xC0000184 STATUS_INVALID_DEVICE_STATE
0xC0000185 STATUS_IO_DEVICE_ERROR
0xC0000186 STATUS_DEVICE_PROTOCOL_ERROR
0xC0000187 STATUS_BACKUP_CONTROLLER
0xC0000188 STATUS_LOG_FILE_FULL
0xC0000189 STATUS_TOO_LATE
0xC000018A STATUS_NO_TRUST_LSA_SECRET
0xC000018B STATUS_NO_TRUST_SAM_ACCOUNT
0xC000018C STATUS_TRUSTED_DOMAIN_FAILURE
0xC000018D STATUS_TRUSTED_RELATIONSHIP_FAILURE
0xC000018E STATUS_EVENTLOG_FILE_CORRUPT
0xC000018F STATUS_EVENTLOG_CANT_START
0xC0000190 STATUS_TRUST_FAILURE
0xC0000191 STATUS_MUTANT_LIMIT_EXCEEDED
0xC0000192 STATUS_NETLOGON_NOT_STARTED
0xC0000193 STATUS_ACCOUNT_EXPIRED
0xC0000194 STATUS_POSSIBLE_DEADLOCK
0xC0000195 STATUS_NETWORK_CREDENTIAL_CONFLICT
0xC0000196 STATUS_REMOTE_SESSION_LIMIT
0xC0000197 STATUS_EVENTLOG_FILE_CHANGED
0xC0000198 STATUS_NOLOGON_INTERDOMAIN_TRUST_ACCOUNT
0xC0000199 STATUS_NOLOGON_WORKSTATION_TRUST_ACCOUNT
0xC000019A STATUS_NOLOGON_SERVER_TRUST_ACCOUNT
0xC000019B STATUS_DOMAIN_TRUST_INCONSISTENT
0xC000019C STATUS_FS_DRIVER_REQUIRED
0xC000019D STATUS_IMAGE_ALREADY_LOADED_AS_DLL
0xC000019E STATUS_INCOMPATIBLE_WITH_GLOBAL_SHORT_NAME_REGISTRY_SETTING
0xC000019F STATUS_SHORT_NAMES_NOT_ENABLED_ON_VOLUME
0xC00001A0 STATUS_SECURITY_STREAM_IS_INCONSISTENT
0xC00001A1 STATUS_INVALID_LOCK_RANGE
0xC00001A2 STATUS_INVALID_ACE_CONDITION
0xC00001A3 STATUS_IMAGE_SUBSYSTEM_NOT_PRESENT
0xC00001A4 STATUS_NOTIFICATION_GUID_ALREADY_DEFINED
0xC00001A5 STATUS_INVALID_EXCEPTION_HANDLER
0xC00001A6 STATUS_DUPLICATE_PRIVILEGES
0xC00001A7 STATUS_NOT_ALLOWED_ON_SYSTEM_FILE
0xC00001A8 STATUS_REPAIR_NEEDED
0xC00001A9 STATUS_QUOTA_NOT_ENABLED
0xC00001AA STATUS_NO_APPLICATION_PACKAGE
0xC00001AB STATUS_FILE_METADATA_OPTIMIZATION_IN_PROGRESS
0xC00001AC STATUS_NOT_SAME_OBJECT
0xC00001AD STATUS_FATAL_MEMORY_EXHAUSTION
0xC00001AE STATUS_ERROR_PROCESS_NOT_IN_JOB
0xC00001AF STATUS_CPU_SET_INVALID
0xC0000201 STATUS_NETWORK_OPEN_RESTRICTION
0xC0000202 STATUS_NO_USER_SESSION_KEY
0xC0000203 STATUS_USER_SESSION_DELETED
0xC0000204 STATUS_RESOURCE_LANG_NOT_FOUND
0xC0000205 STATUS_INSUFF_SERVER_RESOURCES
0xC0000206 STATUS_INVALID_BUFFER_SIZE
0xC0000207 STATUS_INVALID_ADDRESS_COMPONENT
0xC0000208 STATUS_INVALID_ADDRESS_WILDCARD
0xC0000209 STATUS_TOO_MANY_ADDRESSES
0xC000020A STATUS_ADDRESS_ALREADY_EXISTS
0xC000020B STATUS_ADDRESS_CLOSED
0xC000020C STATUS_CONNECTION_DISCONNECTED
0xC000020D STATUS_CONNECTION_RESET
0xC000020E STATUS_TOO_MANY_NODES
0xC000020F STATUS_TRANSACTION_ABORTED
0xC0000210 STATUS_TRANSACTION_TIMED_OUT
0xC0000211 STATUS_TRANSACTION_NO_RELEASE
0xC0000212 STATUS_TRANSACTION_NO_MATCH
0xC0000213 STATUS_TRANSACTION_RESPONDED
0xC0000214 STATUS_TRANSACTION_INVALID_ID
0xC0000215 STATUS_TRANSACTION_INVALID_TYPE
0xC0000216 STATUS_NOT_SERVER_SESSION
0xC0000217 STATUS_NOT_CLIENT_SESSION
0xC0000218 STATUS_CANNOT_LOAD_REGISTRY_FILE
0xC0000219 STATUS_DEBUG_ATTACH_FAILED
0xC000021A STATUS_SYSTEM_PROCESS_TERMINATED
0xC000021B STATUS_DATA_NOT_ACCEPTED
0xC000021C STATUS_NO_BROWSER_SERVERS_FOUND
0xC000021D STATUS_VDM_HARD_ERROR
0xC000021E STATUS_DRIVER_CANCEL_TIMEOUT
0xC000021F STATUS_REPLY_MESSAGE_MISMATCH
0xC0000220 STATUS_MAPPED_ALIGNMENT
0xC0000221 STATUS_IMAGE_CHECKSUM_MISMATCH
0xC0000222 STATUS_LOST_WRITEBEHIND_DATA
0xC0000223 STATUS_CLIENT_SERVER_PARAMETERS_INVALID
0xC0000224 STATUS_PASSWORD_MUST_CHANGE
0xC0000225 STATUS_NOT_FOUND
0xC0000226 STATUS_NOT_TINY_STREAM
0xC0000227 STATUS_RECOVERY_FAILURE
0xC0000228 STATUS_STACK_OVERFLOW_READ
0xC0000229 STATUS_FAIL_CHECK
0xC000022A STATUS_DUPLICATE_OBJECTID
0xC000022B STATUS_OBJECTID_EXISTS
0xC000022C STATUS_CONVERT_TO_LARGE
0xC000022D STATUS_RETRY
0xC000022E STATUS_FOUND_OUT_OF_SCOPE
0xC000022F STATUS_ALLOCATE_BUCKET
0xC0000230 STATUS_PROPSET_NOT_FOUND
0xC0000231 STATUS_MARSHALL_OVERFLOW
0xC0000232 STATUS_INVALID_VARIANT
0xC0000233 STATUS_DOMAIN_CONTROLLER_NOT_FOUND
0xC0000234 STATUS_ACCOUNT_LOCKED_OUT
0xC0000235 STATUS_HANDLE_NOT_CLOSABLE
0xC0000236 STATUS_CONNECTION_REFUSED
0xC0000237 STATUS_GRACEFUL_DISCONNECT
0xC0000238 STATUS_ADDRESS_ALREADY_ASSOCIATED
0xC0000239 STATUS_ADDRESS_NOT_ASSOCIATED
0xC000023A STATUS_CONNECTION_INVALID
0xC000023B STATUS_CONNECTION_ACTIVE
0xC000023C STATUS_NETWORK_UNREACHABLE
0xC000023D STATUS_HOST_UNREACHABLE
0xC000023E STATUS_PROTOCOL_UNREACHABLE
0xC000023F STATUS_PORT_UNREACHABLE
0xC0000240 STATUS_REQUEST_ABORTED
0xC0000241 STATUS_CONNECTION_ABORTED
0xC0000242 STATUS_BAD_COMPRESSION_BUFFER
0xC0000243 STATUS_USER_MAPPED_FILE
0xC0000244 STATUS_AUDIT_FAILED
0xC0000245 STATUS_TIMER_RESOLUTION_NOT_SET
0xC0000246 STATUS_CONNECTION_COUNT_LIMIT
0xC0000247 STATUS_LOGIN_TIME_RESTRICTION
0xC0000248 STATUS_LOGIN_WKSTA_RESTRICTION
0xC0000249 STATUS_IMAGE_MP_UP_MISMATCH
0xC0000250 STATUS_INSUFFICIENT_LOGON_INFO
0xC0000251 STATUS_BAD_DLL_ENTRYPOINT
0xC0000252 STATUS_BAD_SERVICE_ENTRYPOINT
0xC0000253 STATUS_LPC_REPLY_LOST
0xC0000254 STATUS_IP_ADDRESS_CONFLICT1
0xC0000255 STATUS_IP_ADDRESS_CONFLICT2
0xC0000256 STATUS_REGISTRY_QUOTA_LIMIT
0xC0000257 STATUS_PATH_NOT_COVERED
0xC0000258 STATUS_NO_CALLBACK_ACTIVE
0xC0000259 STATUS_LICENSE_QUOTA_EXCEEDED
0xC000025A STATUS_PWD_TOO_SHORT
0xC000025B STATUS_PWD_TOO_RECENT
0xC000025C STATUS_PWD_HISTORY_CONFLICT
0xC000025E STATUS_PLUGPLAY_NO_DEVICE
0xC000025F STATUS_UNSUPPORTED_COMPRESSION
0xC0000260 STATUS_INVALID_HW_PROFILE
0xC0000261 STATUS_INVALID_PLUGPLAY_DEVICE_PATH
0xC0000262 STATUS_DRIVER_ORDINAL_NOT_FOUND
0xC0000263 STATUS_DRIVER_ENTRYPOINT_NOT_FOUND
0xC0000264 STATUS_RESOURCE_NOT_OWNED
0xC0000265 STATUS_TOO_MANY_LINKS
0xC0000266 STATUS_QUOTA_LIST_INCONSISTENT
0xC0000267 STATUS_FILE_IS_OFFLINE
0xC0000268 STATUS_EVALUATION_EXPIRATION
0xC0000269 STATUS_ILLEGAL_DLL_RELOCATION
0xC000026A STATUS_LICENSE_VIOLATION
0xC000026B STATUS_DLL_INIT_FAILED_LOGOFF
0xC000026C STATUS_DRIVER_UNABLE_TO_LOAD
0xC000026D STATUS_DFS_UNAVAILABLE
0xC000026E STATUS_VOLUME_DISMOUNTED
0xC000026F STATUS_WX86_INTERNAL_ERROR
0xC0000270 STATUS_WX86_FLOAT_STACK_CHECK
0xC0000271 STATUS_VALIDATE_CONTINUE
0xC0000272 STATUS_NO_MATCH
0xC0000273 STATUS_NO_MORE_MATCHES
0xC0000275 STATUS_NOT_A_REPARSE_POINT
0xC0000276 STATUS_IO_REPARSE_TAG_INVALID
0xC0000277 STATUS_IO_REPARSE_TAG_MISMATCH
0xC0000278 STATUS_IO_REPARSE_DATA_INVALID
0xC0000279 STATUS_IO_REPARSE_TAG_NOT_HANDLED
0xC000027A STATUS_PWD_TOO_LONG
0xC000027B STATUS_STOWED_EXCEPTION
0xC000027C STATUS_CONTEXT_STOWED_EXCEPTION
0xC0000280 STATUS_REPARSE_POINT_NOT_RESOLVED
0xC0000281 STATUS_DIRECTORY_IS_A_REPARSE_POINT
0xC0000282 STATUS_RANGE_LIST_CONFLICT
0xC0000283 STATUS_SOURCE_ELEMENT_EMPTY
0xC0000284 STATUS_DESTINATION_ELEMENT_FULL
0xC0000285 STATUS_ILLEGAL_ELEMENT_ADDRESS
0xC0000286 STATUS_MAGAZINE_NOT_PRESENT
0xC0000287 STATUS_REINITIALIZATION_NEEDED
0xC000028A STATUS_ENCRYPTION_FAILED
0xC000028B STATUS_DECRYPTION_FAILED
0xC000028C STATUS_RANGE_NOT_FOUND
0xC000028D STATUS_NO_RECOVERY_POLICY
0xC000028E STATUS_NO_EFS
0xC000028F STATUS_WRONG_EFS
0xC0000290 STATUS_NO_USER_KEYS
0xC0000291 STATUS_FILE_NOT_ENCRYPTED
0xC0000292 STATUS_NOT_EXPORT_FORMAT
0xC0000293 STATUS_FILE_ENCRYPTED
0xC0000295 STATUS_WMI_GUID_NOT_FOUND
0xC0000296 STATUS_WMI_INSTANCE_NOT_FOUND
0xC0000297 STATUS_WMI_ITEMID_NOT_FOUND
0xC0000298 STATUS_WMI_TRY_AGAIN
0xC0000299 STATUS_SHARED_POLICY
0xC000029A STATUS_POLICY_OBJECT_NOT_FOUND
0xC000029B STATUS_POLICY_ONLY_IN_DS
0xC000029C STATUS_VOLUME_NOT_UPGRADED
0xC000029D STATUS_REMOTE_STORAGE_NOT_ACTIVE
0xC000029E STATUS_REMOTE_STORAGE_MEDIA_ERROR
0xC000029F STATUS_NO_TRACKING_SERVICE
0xC00002A0 STATUS_SERVER_SID_MISMATCH
0xC00002A1 STATUS_DS_NO_ATTRIBUTE_OR_VALUE
0xC00002A2 STATUS_DS_INVALID_ATTRIBUTE_SYNTAX
0xC00002A3 STATUS_DS_ATTRIBUTE_TYPE_UNDEFINED
0xC00002A4 STATUS_DS_ATTRIBUTE_OR_VALUE_EXISTS
0xC00002A5 STATUS_DS_BUSY
0xC00002A6 STATUS_DS_UNAVAILABLE
0xC00002A7 STATUS_DS_NO_RIDS_ALLOCATED
0xC00002A8 STATUS_DS_NO_MORE_RIDS
0xC00002A9 STATUS_DS_INCORRECT_ROLE_OWNER
0xC00002AA STATUS_DS_RIDMGR_INIT_ERROR
0xC00002AB STATUS_DS_OBJ_CLASS_VIOLATION
0xC00002AC STATUS_DS_CANT_ON_NON_LEAF
0xC00002AD STATUS_DS_CANT_ON_RDN
0xC00002AE STATUS_DS_CANT_MOD_OBJ_CLASS
0xC00002AF STATUS_DS_CROSS_DOM_MOVE_FAILED
0xC00002B0 STATUS_DS_GC_NOT_AVAILABLE
0xC00002B1 STATUS_DIRECTORY_SERVICE_REQUIRED
0xC00002B2 STATUS_REPARSE_ATTRIBUTE_CONFLICT
0xC00002B3 STATUS_CANT_ENABLE_DENY_ONLY
0xC00002B4 STATUS_FLOAT_MULTIPLE_FAULTS
0xC00002B5 STATUS_FLOAT_MULTIPLE_TRAPS
0xC00002B6 STATUS_DEVICE_REMOVED
0xC00002B7 STATUS_JOURNAL_DELETE_IN_PROGRESS
0xC00002B8 STATUS_JOURNAL_NOT_ACTIVE
0xC00002B9 STATUS_NOINTERFACE
0xC00002BA STATUS_DS_RIDMGR_DISABLED
0xC00002C1 STATUS_DS_ADMIN_LIMIT_EXCEEDED
0xC00002C2 STATUS_DRIVER_FAILED_SLEEP
0xC00002C3 STATUS_MUTUAL_AUTHENTICATION_FAILED
0xC00002C4 STATUS_CORRUPT_SYSTEM_FILE
0xC00002C5 STATUS_DATATYPE_MISALIGNMENT_ERROR
0xC00002C6 STATUS_WMI_READ_ONLY
0xC00002C7 STATUS_WMI_SET_FAILURE
0xC00002C8 STATUS_COMMITMENT_MINIMUM
0xC00002C9 STATUS_REG_NAT_CONSUMPTION
0xC00002CA STATUS_TRANSPORT_FULL
0xC00002CB STATUS_DS_SAM_INIT_FAILURE
0xC00002CC STATUS_ONLY_IF_CONNECTED
0xC00002CD STATUS_DS_SENSITIVE_GROUP_VIOLATION
0xC00002CE STATUS_PNP_RESTART_ENUMERATION
0xC00002CF STATUS_JOURNAL_ENTRY_DELETED
0xC00002D0 STATUS_DS_CANT_MOD_PRIMARYGROUPID
0xC00002D1 STATUS_SYSTEM_IMAGE_BAD_SIGNATURE
0xC00002D2 STATUS_PNP_REBOOT_REQUIRED
0xC00002D3 STATUS_POWER_STATE_INVALID
0xC00002D4 STATUS_DS_INVALID_GROUP_TYPE
0xC00002D5 STATUS_DS_NO_NEST_GLOBALGROUP_IN_MIXEDDOMAIN
0xC00002D6 STATUS_DS_NO_NEST_LOCALGROUP_IN_MIXEDDOMAIN
0xC00002D7 STATUS_DS_GLOBAL_CANT_HAVE_LOCAL_MEMBER
0xC00002D8 STATUS_DS_GLOBAL_CANT_HAVE_UNIVERSAL_MEMBER
0xC00002D9 STATUS_DS_UNIVERSAL_CANT_HAVE_LOCAL_MEMBER
0xC00002DA STATUS_DS_GLOBAL_CANT_HAVE_CROSSDOMAIN_MEMBER
0xC00002DB STATUS_DS_LOCAL_CANT_HAVE_CROSSDOMAIN_LOCAL_MEMBER
0xC00002DC STATUS_DS_HAVE_PRIMARY_MEMBERS
0xC00002DD STATUS_WMI_NOT_SUPPORTED
0xC00002DE STATUS_INSUFFICIENT_POWER
0xC00002DF STATUS_SAM_NEED_BOOTKEY_PASSWORD
0xC00002E0 STATUS_SAM_NEED_BOOTKEY_FLOPPY
0xC00002E1 STATUS_DS_CANT_START
0xC00002E2 STATUS_DS_INIT_FAILURE
0xC00002E3 STATUS_SAM_INIT_FAILURE
0xC00002E4 STATUS_DS_GC_REQUIRED
0xC00002E5 STATUS_DS_LOCAL_MEMBER_OF_LOCAL_ONLY
0xC00002E6 STATUS_DS_NO_FPO_IN_UNIVERSAL_GROUPS
0xC00002E7 STATUS_DS_MACHINE_ACCOUNT_QUOTA_EXCEEDED
0xC00002E8 STATUS_MULTIPLE_FAULT_VIOLATION
0xC00002E9 STATUS_CURRENT_DOMAIN_NOT_ALLOWED
0xC00002EA STATUS_CANNOT_MAKE
0xC00002EB STATUS_SYSTEM_SHUTDOWN
0xC00002EC STATUS_DS_INIT_FAILURE_CONSOLE
0xC00002ED STATUS_DS_SAM_INIT_FAILURE_CONSOLE
0xC00002EE STATUS_UNFINISHED_CONTEXT_DELETED
0xC00002EF STATUS_NO_TGT_REPLY
0xC00002F0 STATUS_OBJECTID_NOT_FOUND
0xC00002F1 STATUS_NO_IP_ADDRESSES
0xC00002F2 STATUS_WRONG_CREDENTIAL_HANDLE
0xC00002F3 STATUS_CRYPTO_SYSTEM_INVALID
0xC00002F4 STATUS_MAX_REFERRALS_EXCEEDED
0xC00002F5 STATUS_MUST_BE_KDC
0xC00002F6 STATUS_STRONG_CRYPTO_NOT_SUPPORTED
0xC00002F7 STATUS_TOO_MANY_PRINCIPALS
0xC00002F8 STATUS_NO_PA_DATA
0xC00002F9 STATUS_PKINIT_NAME_MISMATCH
0xC00002FA STATUS_SMARTCARD_LOGON_REQUIRED
0xC00002FB STATUS_KDC_INVALID_REQUEST
0xC00002FC STATUS_KDC_UNABLE_TO_REFER
0xC00002FD STATUS_KDC_UNKNOWN_ETYPE
0xC00002FE STATUS_SHUTDOWN_IN_PROGRESS
0xC00002FF STATUS_SERVER_SHUTDOWN_IN_PROGRESS
0xC0000300 STATUS_NOT_SUPPORTED_ON_SBS
0xC0000301 STATUS_WMI_GUID_DISCONNECTED
0xC0000302 STATUS_WMI_ALREADY_DISABLED
0xC0000303 STATUS_WMI_ALREADY_ENABLED
0xC0000304 STATUS_MFT_TOO_FRAGMENTED
0xC0000305 STATUS_COPY_PROTECTION_FAILURE
0xC0000306 STATUS_CSS_AUTHENTICATION_FAILURE
0xC0000307 STATUS_CSS_KEY_NOT_PRESENT
0xC0000308 STATUS_CSS_KEY_NOT_ESTABLISHED
0xC0000309 STATUS_CSS_SCRAMBLED_SECTOR
0xC000030A STATUS_CSS_REGION_MISMATCH
0xC000030B STATUS_CSS_RESETS_EXHAUSTED
0xC000030C STATUS_PASSWORD_CHANGE_REQUIRED
0xC000030D STATUS_LOST_MODE_LOGON_RESTRICTION
0xC0000320 STATUS_PKINIT_FAILURE
0xC0000321 STATUS_SMARTCARD_SUBSYSTEM_FAILURE
0xC0000322 STATUS_NO_KERB_KEY
0xC0000350 STATUS_HOST_DOWN
0xC0000351 STATUS_UNSUPPORTED_PREAUTH
0xC0000352 STATUS_EFS_ALG_BLOB_TOO_BIG
0xC0000353 STATUS_PORT_NOT_SET
0xC0000354 STATUS_DEBUGGER_INACTIVE
0xC0000355 STATUS_DS_VERSION_CHECK_FAILURE
0xC0000356 STATUS_AUDITING_DISABLED
0xC0000357 STATUS_PRENT4_MACHINE_ACCOUNT
0xC0000358 STATUS_DS_AG_CANT_HAVE_UNIVERSAL_MEMBER
0xC0000359 STATUS_INVALID_IMAGE_WIN_32
0xC000035A STATUS_INVALID_IMAGE_WIN_64
0xC000035B STATUS_BAD_BINDINGS
0xC000035C STATUS_NETWORK_SESSION_EXPIRED
0xC000035D STATUS_APPHELP_BLOCK
0xC000035E STATUS_ALL_SIDS_FILTERED
0xC000035F STATUS_NOT_SAFE_MODE_DRIVER
0xC0000361 STATUS_ACCESS_DISABLED_BY_POLICY_DEFAULT
0xC0000362 STATUS_ACCESS_DISABLED_BY_POLICY_PATH
0xC0000363 STATUS_ACCESS_DISABLED_BY_POLICY_PUBLISHER
0xC0000364 STATUS_ACCESS_DISABLED_BY_POLICY_OTHER
0xC0000365 STATUS_FAILED_DRIVER_ENTRY
0xC0000366 STATUS_DEVICE_ENUMERATION_ERROR
0xC0000368 STATUS_MOUNT_POINT_NOT_RESOLVED
0xC0000369 STATUS_INVALID_DEVICE_OBJECT_PARAMETER
0xC000036A STATUS_MCA_OCCURED
0xC000036B STATUS_DRIVER_BLOCKED_CRITICAL
0xC000036C STATUS_DRIVER_BLOCKED
0xC000036D STATUS_DRIVER_DATABASE_ERROR
0xC000036E STATUS_SYSTEM_HIVE_TOO_LARGE
0xC000036F STATUS_INVALID_IMPORT_OF_NON_DLL
0xC0000371 STATUS_NO_SECRETS
0xC0000372 STATUS_ACCESS_DISABLED_NO_SAFER_UI_BY_POLICY
0xC0000373 STATUS_FAILED_STACK_SWITCH
0xC0000374 STATUS_HEAP_CORRUPTION
0xC0000380 STATUS_SMARTCARD_WRONG_PIN
0xC0000381 STATUS_SMARTCARD_CARD_BLOCKED
0xC0000382 STATUS_SMARTCARD_CARD_NOT_AUTHENTICATED
0xC0000383 STATUS_SMARTCARD_NO_CARD
0xC0000384 STATUS_SMARTCARD_NO_KEY_CONTAINER
0xC0000385 STATUS_SMARTCARD_NO_CERTIFICATE
0xC0000386 STATUS_SMARTCARD_NO_KEYSET
0xC0000387 STATUS_SMARTCARD_IO_ERROR
0xC0000388 STATUS_DOWNGRADE_DETECTED
0xC0000389 STATUS_SMARTCARD_CERT_REVOKED
0xC000038A STATUS_ISSUING_CA_UNTRUSTED
0xC000038B STATUS_REVOCATION_OFFLINE_C
0xC000038C STATUS_PKINIT_CLIENT_FAILURE
0xC000038D STATUS_SMARTCARD_CERT_EXPIRED
0xC000038E STATUS_DRIVER_FAILED_PRIOR_UNLOAD
0xC000038F STATUS_SMARTCARD_SILENT_CONTEXT
0xC0000401 STATUS_PER_USER_TRUST_QUOTA_EXCEEDED
0xC0000402 STATUS_ALL_USER_TRUST_QUOTA_EXCEEDED
0xC0000403 STATUS_USER_DELETE_TRUST_QUOTA_EXCEEDED
0xC0000404 STATUS_DS_NAME_NOT_UNIQUE
0xC0000405 STATUS_DS_DUPLICATE_ID_FOUND
0xC0000406 STATUS_DS_GROUP_CONVERSION_ERROR
0xC0000407 STATUS_VOLSNAP_PREPARE_HIBERNATE
0xC0000408 STATUS_USER2USER_REQUIRED
0xC0000409 STATUS_STACK_BUFFER_OVERRUN
0xC000040A STATUS_NO_S4U_PROT_SUPPORT
0xC000040B STATUS_CROSSREALM_DELEGATION_FAILURE
0xC000040C STATUS_REVOCATION_OFFLINE_KDC
0xC000040D STATUS_ISSUING_CA_UNTRUSTED_KDC
0xC000040E STATUS_KDC_CERT_EXPIRED
0xC000040F STATUS_KDC_CERT_REVOKED
0xC0000410 STATUS_PARAMETER_QUOTA_EXCEEDED
0xC0000411 STATUS_HIBERNATION_FAILURE
0xC0000412 STATUS_DELAY_LOAD_FAILED
0xC0000413 STATUS_AUTHENTICATION_FIREWALL_FAILED
0xC0000414 STATUS_VDM_DISALLOWED
0xC0000415 STATUS_HUNG_DISPLAY_DRIVER_THREAD
0xC0000416 STATUS_INSUFFICIENT_RESOURCE_FOR_SPECIFIED_SHARED_SECTION_SIZE
0xC0000417 STATUS_INVALID_CRUNTIME_PARAMETER
0xC0000418 STATUS_NTLM_BLOCKED
0xC0000419 STATUS_DS_SRC_SID_EXISTS_IN_FOREST
0xC000041A STATUS_DS_DOMAIN_NAME_EXISTS_IN_FOREST
0xC000041B STATUS_DS_FLAT_NAME_EXISTS_IN_FOREST
0xC000041C STATUS_INVALID_USER_PRINCIPAL_NAME
0xC000041D STATUS_FATAL_USER_CALLBACK_EXCEPTION
0xC0000420 STATUS_ASSERTION_FAILURE
0xC0000421 STATUS_VERIFIER_STOP
0xC0000423 STATUS_CALLBACK_POP_STACK
0xC0000424 STATUS_INCOMPATIBLE_DRIVER_BLOCKED
0xC0000425 STATUS_HIVE_UNLOADED
0xC0000426 STATUS_COMPRESSION_DISABLED
0xC0000427 STATUS_FILE_SYSTEM_LIMITATION
0xC0000428 STATUS_INVALID_IMAGE_HASH
0xC0000429 STATUS_NOT_CAPABLE
0xC000042A STATUS_REQUEST_OUT_OF_SEQUENCE
0xC000042B STATUS_IMPLEMENTATION_LIMIT
0xC000042C STATUS_ELEVATION_REQUIRED
0xC000042D STATUS_NO_SECURITY_CONTEXT
0xC000042F STATUS_PKU2U_CERT_FAILURE
0xC0000432 STATUS_BEYOND_VDL
0xC0000433 STATUS_ENCOUNTERED_WRITE_IN_PROGRESS
0xC0000434 STATUS_PTE_CHANGED
0xC0000435 STATUS_PURGE_FAILED
0xC0000440 STATUS_CRED_REQUIRES_CONFIRMATION
0xC0000441 STATUS_CS_ENCRYPTION_INVALID_SERVER_RESPONSE
0xC0000442 STATUS_CS_ENCRYPTION_UNSUPPORTED_SERVER
0xC0000443 STATUS_CS_ENCRYPTION_EXISTING_ENCRYPTED_FILE
0xC0000444 STATUS_CS_ENCRYPTION_NEW_ENCRYPTED_FILE
0xC0000445 STATUS_CS_ENCRYPTION_FILE_NOT_CSE
0xC0000446 STATUS_INVALID_LABEL
0xC0000450 STATUS_DRIVER_PROCESS_TERMINATED
0xC0000451 STATUS_AMBIGUOUS_SYSTEM_DEVICE
0xC0000452 STATUS_SYSTEM_DEVICE_NOT_FOUND
0xC0000453 STATUS_RESTART_BOOT_APPLICATION
0xC0000454 STATUS_INSUFFICIENT_NVRAM_RESOURCES
0xC0000455 STATUS_INVALID_SESSION
0xC0000456 STATUS_THREAD_ALREADY_IN_SESSION
0xC0000457 STATUS_THREAD_NOT_IN_SESSION
0xC0000458 STATUS_INVALID_WEIGHT
0xC0000459 STATUS_REQUEST_PAUSED
0xC0000460 STATUS_NO_RANGES_PROCESSED
0xC0000461 STATUS_DISK_RESOURCES_EXHAUSTED
0xC0000462 STATUS_NEEDS_REMEDIATION
0xC0000463 STATUS_DEVICE_FEATURE_NOT_SUPPORTED
0xC0000464 STATUS_DEVICE_UNREACHABLE
0xC0000465 STATUS_INVALID_TOKEN
0xC0000466 STATUS_SERVER_UNAVAILABLE
0xC0000467 STATUS_FILE_NOT_AVAILABLE
0xC0000468 STATUS_DEVICE_INSUFFICIENT_RESOURCES
0xC0000469 STATUS_PACKAGE_UPDATING
0xC000046A STATUS_NOT_READ_FROM_COPY
0xC000046B STATUS_FT_WRITE_FAILURE
0xC000046C STATUS_FT_DI_SCAN_REQUIRED
0xC000046D STATUS_OBJECT_NOT_EXTERNALLY_BACKED
0xC000046E STATUS_EXTERNAL_BACKING_PROVIDER_UNKNOWN
0xC000046F STATUS_COMPRESSION_NOT_BENEFICIAL
0xC0000470 STATUS_DATA_CHECKSUM_ERROR
0xC0000471 STATUS_INTERMIXED_KERNEL_EA_OPERATION
0xC0000472 STATUS_TRIM_READ_ZERO_NOT_SUPPORTED
0xC0000473 STATUS_TOO_MANY_SEGMENT_DESCRIPTORS
0xC0000474 STATUS_INVALID_OFFSET_ALIGNMENT
0xC0000475 STATUS_INVALID_FIELD_IN_PARAMETER_LIST
0xC0000476 STATUS_OPERATION_IN_PROGRESS
0xC0000477 STATUS_INVALID_INITIATOR_TARGET_PATH
0xC0000478 STATUS_SCRUB_DATA_DISABLED
0xC0000479 STATUS_NOT_REDUNDANT_STORAGE
0xC000047A STATUS_RESIDENT_FILE_NOT_SUPPORTED
0xC000047B STATUS_COMPRESSED_FILE_NOT_SUPPORTED
0xC000047C STATUS_DIRECTORY_NOT_SUPPORTED
0xC000047D STATUS_IO_OPERATION_TIMEOUT
0xC000047E STATUS_SYSTEM_NEEDS_REMEDIATION
0xC000047F STATUS_APPX_INTEGRITY_FAILURE_CLR_NGEN
0xC0000480 STATUS_SHARE_UNAVAILABLE
0xC0000481 STATUS_APISET_NOT_HOSTED
0xC0000482 STATUS_APISET_NOT_PRESENT
0xC0000483 STATUS_DEVICE_HARDWARE_ERROR
0xC0000484 STATUS_FIRMWARE_SLOT_INVALID
0xC0000485 STATUS_FIRMWARE_IMAGE_INVALID
0xC0000486 STATUS_STORAGE_TOPOLOGY_ID_MISMATCH
0xC0000487 STATUS_WIM_NOT_BOOTABLE
0xC0000488 STATUS_BLOCKED_BY_PARENTAL_CONTROLS
0xC0000489 STATUS_NEEDS_REGISTRATION
0xC000048A STATUS_QUOTA_ACTIVITY
0xC000048B STATUS_CALLBACK_INVOKE_INLINE
0xC000048C STATUS_BLOCK_TOO_MANY_REFERENCES
0xC000048D STATUS_MARKED_TO_DISALLOW_WRITES
0xC000048E STATUS_NETWORK_ACCESS_DENIED_EDP
0xC000048F STATUS_ENCLAVE_FAILURE
0xC0000490 STATUS_PNP_NO_COMPAT_DRIVERS
0xC0000491 STATUS_PNP_DRIVER_PACKAGE_NOT_FOUND
0xC0000492 STATUS_PNP_DRIVER_CONFIGURATION_NOT_FOUND
0xC0000493 STATUS_PNP_DRIVER_CONFIGURATION_INCOMPLETE
0xC0000494 STATUS_PNP_FUNCTION_DRIVER_REQUIRED
0xC0000495 STATUS_PNP_DEVICE_CONFIGURATION_PENDING
0xC0000496 STATUS_DEVICE_HINT_NAME_BUFFER_TOO_SMALL
0xC0000497 STATUS_PACKAGE_NOT_AVAILABLE
0xC0000499 STATUS_DEVICE_IN_MAINTENANCE
0xC000049A STATUS_NOT_SUPPORTED_ON_DAX
0xC000049B STATUS_FREE_SPACE_TOO_FRAGMENTED
0xC000049C STATUS_DAX_MAPPING_EXISTS
0xC000049D STATUS_CHILD_PROCESS_BLOCKED
0xC000049E STATUS_STORAGE_LOST_DATA_PERSISTENCE
0xC000049F STATUS_VRF_CFG_ENABLED
0xC00004A0 STATUS_PARTITION_TERMINATING
0xC00004A1 STATUS_EXTERNAL_SYSKEY_NOT_SUPPORTED
0xC0000500 STATUS_INVALID_TASK_NAME
0xC0000501 STATUS_INVALID_TASK_INDEX
0xC0000502 STATUS_THREAD_ALREADY_IN_TASK
0xC0000503 STATUS_CALLBACK_BYPASS
0xC0000504 STATUS_UNDEFINED_SCOPE
0xC0000505 STATUS_INVALID_CAP
0xC0000506 STATUS_NOT_GUI_PROCESS
0xC0000507 STATUS_DEVICE_HUNG
0xC0000508 STATUS_CONTAINER_ASSIGNED
0xC0000509 STATUS_JOB_NO_CONTAINER
0xC000050A STATUS_DEVICE_UNRESPONSIVE
0xC000050B STATUS_REPARSE_POINT_ENCOUNTERED
0xC000050C STATUS_ATTRIBUTE_NOT_PRESENT
0xC000050D STATUS_NOT_A_TIERED_VOLUME
0xC000050E STATUS_ALREADY_HAS_STREAM_ID
0xC000050F STATUS_JOB_NOT_EMPTY
0xC0000510 STATUS_ALREADY_INITIALIZED
0xC0000511 STATUS_ENCLAVE_NOT_TERMINATED
0xC0000512 STATUS_ENCLAVE_IS_TERMINATING
0xC0000513 STATUS_SMB1_NOT_AVAILABLE
0xC0000514 STATUS_SMR_GARBAGE_COLLECTION_REQUIRED
0xC0000602 STATUS_FAIL_FAST_EXCEPTION
0xC0000603 STATUS_IMAGE_CERT_REVOKED
0xC0000604 STATUS_DYNAMIC_CODE_BLOCKED
0xC0000605 STATUS_IMAGE_CERT_EXPIRED
0xC0000606 STATUS_STRICT_CFG_VIOLATION
0xC000060A STATUS_SET_CONTEXT_DENIED
0xC000060B STATUS_CROSS_PARTITION_VIOLATION
0xC0000700 STATUS_PORT_CLOSED
0xC0000701 STATUS_MESSAGE_LOST
0xC0000702 STATUS_INVALID_MESSAGE
0xC0000703 STATUS_REQUEST_CANCELED
0xC0000704 STATUS_RECURSIVE_DISPATCH
0xC0000705 STATUS_LPC_RECEIVE_BUFFER_EXPECTED
0xC0000706 STATUS_LPC_INVALID_CONNECTION_USAGE
0xC0000707 STATUS_LPC_REQUESTS_NOT_ALLOWED
0xC0000708 STATUS_RESOURCE_IN_USE
0xC0000709 STATUS_HARDWARE_MEMORY_ERROR
0xC000070A STATUS_THREADPOOL_HANDLE_EXCEPTION
0xC000070B STATUS_THREADPOOL_SET_EVENT_ON_COMPLETION_FAILED
0xC000070C STATUS_THREADPOOL_RELEASE_SEMAPHORE_ON_COMPLETION_FAILED
0xC000070D STATUS_THREADPOOL_RELEASE_MUTEX_ON_COMPLETION_FAILED
0xC000070E STATUS_THREADPOOL_FREE_LIBRARY_ON_COMPLETION_FAILED
0xC000070F STATUS_THREADPOOL_RELEASED_DURING_OPERATION
0xC0000710 STATUS_CALLBACK_RETURNED_WHILE_IMPERSONATING
0xC0000711 STATUS_APC_RETURNED_WHILE_IMPERSONATING
0xC0000712 STATUS_PROCESS_IS_PROTECTED
0xC0000713 STATUS_MCA_EXCEPTION
0xC0000714 STATUS_CERTIFICATE_MAPPING_NOT_UNIQUE
0xC0000715 STATUS_SYMLINK_CLASS_DISABLED
0xC0000716 STATUS_INVALID_IDN_NORMALIZATION
0xC0000717 STATUS_NO_UNICODE_TRANSLATION
0xC0000718 STATUS_ALREADY_REGISTERED
0xC0000719 STATUS_CONTEXT_MISMATCH
0xC000071A STATUS_PORT_ALREADY_HAS_COMPLETION_LIST
0xC000071B STATUS_CALLBACK_RETURNED_THREAD_PRIORITY
0xC000071C STATUS_INVALID_THREAD
0xC000071D STATUS_CALLBACK_RETURNED_TRANSACTION
0xC000071E STATUS_CALLBACK_RETURNED_LDR_LOCK
0xC000071F STATUS_CALLBACK_RETURNED_LANG
0xC0000720 STATUS_CALLBACK_RETURNED_PRI_BACK
0xC0000721 STATUS_CALLBACK_RETURNED_THREAD_AFFINITY
0xC0000722 STATUS_LPC_HANDLE_COUNT_EXCEEDED
0xC0000723 STATUS_EXECUTABLE_MEMORY_WRITE
0xC0000724 STATUS_KERNEL_EXECUTABLE_MEMORY_WRITE
0xC0000725 STATUS_ATTACHED_EXECUTABLE_MEMORY_WRITE
0xC0000726 STATUS_TRIGGERED_EXECUTABLE_MEMORY_WRITE
0xC0000800 STATUS_DISK_REPAIR_DISABLED
0xC0000801 STATUS_DS_DOMAIN_RENAME_IN_PROGRESS
0xC0000802 STATUS_DISK_QUOTA_EXCEEDED
0xC0000804 STATUS_CONTENT_BLOCKED
0xC0000805 STATUS_BAD_CLUSTERS
0xC0000806 STATUS_VOLUME_DIRTY
0xC0000808 STATUS_DISK_REPAIR_UNSUCCESSFUL
0xC0000809 STATUS_CORRUPT_LOG_OVERFULL
0xC000080A STATUS_CORRUPT_LOG_CORRUPTED
0xC000080B STATUS_CORRUPT_LOG_UNAVAILABLE
0xC000080C STATUS_CORRUPT_LOG_DELETED_FULL
0xC000080D STATUS_CORRUPT_LOG_CLEARED
0xC000080E STATUS_ORPHAN_NAME_EXHAUSTED
0xC000080F STATUS_PROACTIVE_SCAN_IN_PROGRESS
0xC0000810 STATUS_ENCRYPTED_IO_NOT_POSSIBLE
0xC0000811 STATUS_CORRUPT_LOG_UPLEVEL_RECORDS
0xC0000901 STATUS_FILE_CHECKED_OUT
0xC0000902 STATUS_CHECKOUT_REQUIRED
0xC0000903 STATUS_BAD_FILE_TYPE
0xC0000904 STATUS_FILE_TOO_LARGE
0xC0000905 STATUS_FORMS_AUTH_REQUIRED
0xC0000906 STATUS_VIRUS_INFECTED
0xC0000907 STATUS_VIRUS_DELETED
0xC0000908 STATUS_BAD_MCFG_TABLE
0xC0000909 STATUS_CANNOT_BREAK_OPLOCK
0xC000090A STATUS_BAD_KEY
0xC000090B STATUS_BAD_DATA
0xC000090C STATUS_NO_KEY
0xC0000910 STATUS_FILE_HANDLE_REVOKED
0xC0009898 STATUS_WOW_ASSERTION
0xC000A000 STATUS_INVALID_SIGNATURE
0xC000A001 STATUS_HMAC_NOT_SUPPORTED
0xC000A002 STATUS_AUTH_TAG_MISMATCH
0xC000A003 STATUS_INVALID_STATE_TRANSITION
0xC000A004 STATUS_INVALID_KERNEL_INFO_VERSION
0xC000A005 STATUS_INVALID_PEP_INFO_VERSION
0xC000A006 STATUS_HANDLE_REVOKED
0xC000A007 STATUS_EOF_ON_GHOSTED_RANGE
0xC000A010 STATUS_IPSEC_QUEUE_OVERFLOW
0xC000A011 STATUS_ND_QUEUE_OVERFLOW
0xC000A012 STATUS_HOPLIMIT_EXCEEDED
0xC000A013 STATUS_PROTOCOL_NOT_SUPPORTED
0xC000A014 STATUS_FASTPATH_REJECTED
0xC000A080 STATUS_LOST_WRITEBEHIND_DATA_NETWORK_DISCONNECTED
0xC000A081 STATUS_LOST_WRITEBEHIND_DATA_NETWORK_SERVER_ERROR
0xC000A082 STATUS_LOST_WRITEBEHIND_DATA_LOCAL_DISK_ERROR
0xC000A083 STATUS_XML_PARSE_ERROR
0xC000A084 STATUS_XMLDSIG_ERROR
0xC000A085 STATUS_WRONG_COMPARTMENT
0xC000A086 STATUS_AUTHIP_FAILURE
0xC000A087 STATUS_DS_OID_MAPPED_GROUP_CANT_HAVE_MEMBERS
0xC000A088 STATUS_DS_OID_NOT_FOUND
0xC000A089 STATUS_INCORRECT_ACCOUNT_TYPE
0xC000A100 STATUS_HASH_NOT_SUPPORTED
0xC000A101 STATUS_HASH_NOT_PRESENT
0xC000A121 STATUS_SECONDARY_IC_PROVIDER_NOT_REGISTERED
0xC000A122 STATUS_GPIO_CLIENT_INFORMATION_INVALID
0xC000A123 STATUS_GPIO_VERSION_NOT_SUPPORTED
0xC000A124 STATUS_GPIO_INVALID_REGISTRATION_PACKET
0xC000A125 STATUS_GPIO_OPERATION_DENIED
0xC000A126 STATUS_GPIO_INCOMPATIBLE_CONNECT_MODE
0xC000A141 STATUS_CANNOT_SWITCH_RUNLEVEL
0xC000A142 STATUS_INVALID_RUNLEVEL_SETTING
0xC000A143 STATUS_RUNLEVEL_SWITCH_TIMEOUT
0xC000A145 STATUS_RUNLEVEL_SWITCH_AGENT_TIMEOUT
0xC000A146 STATUS_RUNLEVEL_SWITCH_IN_PROGRESS
0xC000A200 STATUS_NOT_APPCONTAINER
0xC000A201 STATUS_NOT_SUPPORTED_IN_APPCONTAINER
0xC000A202 STATUS_INVALID_PACKAGE_SID_LENGTH
0xC000A203 STATUS_LPAC_ACCESS_DENIED
0xC000A281 STATUS_APP_DATA_NOT_FOUND
0xC000A282 STATUS_APP_DATA_EXPIRED
0xC000A283 STATUS_APP_DATA_CORRUPT
0xC000A284 STATUS_APP_DATA_LIMIT_EXCEEDED
0xC000A285 STATUS_APP_DATA_REBOOT_REQUIRED
0xC000A2A1 STATUS_OFFLOAD_READ_FLT_NOT_SUPPORTED
0xC000A2A2 STATUS_OFFLOAD_WRITE_FLT_NOT_SUPPORTED
0xC000A2A3 STATUS_OFFLOAD_READ_FILE_NOT_SUPPORTED
0xC000A2A4 STATUS_OFFLOAD_WRITE_FILE_NOT_SUPPORTED
0xC000CE01 STATUS_FILE_SYSTEM_VIRTUALIZATION_UNAVAILABLE
0xC000CE02 STATUS_FILE_SYSTEM_VIRTUALIZATION_METADATA_CORRUPT
0xC000CE03 STATUS_FILE_SYSTEM_VIRTUALIZATION_BUSY
0xC000CE04 STATUS_FILE_SYSTEM_VIRTUALIZATION_PROVIDER_UNKNOWN
0xC000CE05 STATUS_FILE_SYSTEM_VIRTUALIZATION_INVALID_OPERATION
0xC000CF00 STATUS_CLOUD_FILE_SYNC_ROOT_METADATA_CORRUPT
0xC000CF01 STATUS_CLOUD_FILE_PROVIDER_NOT_RUNNING
0xC000CF02 STATUS_CLOUD_FILE_METADATA_CORRUPT
0xC000CF03 STATUS_CLOUD_FILE_METADATA_TOO_LARGE
0xC000CF06 STATUS_CLOUD_FILE_PROPERTY_VERSION_NOT_SUPPORTED
0xC000CF07 STATUS_NOT_A_CLOUD_FILE
0xC000CF08 STATUS_CLOUD_FILE_NOT_IN_SYNC
0xC000CF09 STATUS_CLOUD_FILE_ALREADY_CONNECTED
0xC000CF0A STATUS_CLOUD_FILE_NOT_SUPPORTED
0xC000CF0B STATUS_CLOUD_FILE_INVALID_REQUEST
0xC000CF0C STATUS_CLOUD_FILE_READ_ONLY_VOLUME
0xC000CF0D STATUS_CLOUD_FILE_CONNECTED_PROVIDER_ONLY
0xC000CF0E STATUS_CLOUD_FILE_VALIDATION_FAILED
0xC000CF0F STATUS_CLOUD_FILE_AUTHENTICATION_FAILED
0xC000CF10 STATUS_CLOUD_FILE_INSUFFICIENT_RESOURCES
0xC000CF11 STATUS_CLOUD_FILE_NETWORK_UNAVAILABLE
0xC000CF12 STATUS_CLOUD_FILE_UNSUCCESSFUL
0xC000CF13 STATUS_CLOUD_FILE_NOT_UNDER_SYNC_ROOT
0xC000CF14 STATUS_CLOUD_FILE_IN_USE
0xC000CF15 STATUS_CLOUD_FILE_PINNED
0xC000CF16 STATUS_CLOUD_FILE_REQUEST_ABORTED
0xC000CF17 STATUS_CLOUD_FILE_PROPERTY_CORRUPT
0xC000CF18 STATUS_CLOUD_FILE_ACCESS_DENIED
0xC000CF19 STATUS_CLOUD_FILE_INCOMPATIBLE_HARDLINKS
0xC000CF1A STATUS_CLOUD_FILE_PROPERTY_LOCK_CONFLICT
0xC000CF1B STATUS_CLOUD_FILE_REQUEST_CANCELED
0xC0010001 DBG_NO_STATE_CHANGE
0xC0010002 DBG_APP_NOT_IDLE
0xC0020001 RPC_NT_INVALID_STRING_BINDING
0xC0020002 RPC_NT_WRONG_KIND_OF_BINDING
0xC0020003 RPC_NT_INVALID_BINDING
0xC0020004 RPC_NT_PROTSEQ_NOT_SUPPORTED
0xC0020005 RPC_NT_INVALID_RPC_PROTSEQ
0xC0020006 RPC_NT_INVALID_STRING_UUID
0xC0020007 RPC_NT_INVALID_ENDPOINT_FORMAT
0xC0020008 RPC_NT_INVALID_NET_ADDR
0xC0020009 RPC_NT_NO_ENDPOINT_FOUND
0xC002000A RPC_NT_INVALID_TIMEOUT
0xC002000B RPC_NT_OBJECT_NOT_FOUND
0xC002000C RPC_NT_ALREADY_REGISTERED
0xC002000D RPC_NT_TYPE_ALREADY_REGISTERED
0xC002000E RPC_NT_ALREADY_LISTENING
0xC002000F RPC_NT_NO_PROTSEQS_REGISTERED
0xC0020010 RPC_NT_NOT_LISTENING
0xC0020011 RPC_NT_UNKNOWN_MGR_TYPE
0xC0020012 RPC_NT_UNKNOWN_IF
0xC0020013 RPC_NT_NO_BINDINGS
0xC0020014 RPC_NT_NO_PROTSEQS
0xC0020015 RPC_NT_CANT_CREATE_ENDPOINT
0xC0020016 RPC_NT_OUT_OF_RESOURCES
0xC0020017 RPC_NT_SERVER_UNAVAILABLE
0xC0020018 RPC_NT_SERVER_TOO_BUSY
0xC0020019 RPC_NT_INVALID_NETWORK_OPTIONS
0xC002001A RPC_NT_NO_CALL_ACTIVE
0xC002001B RPC_NT_CALL_FAILED
0xC002001C RPC_NT_CALL_FAILED_DNE
0xC002001D RPC_NT_PROTOCOL_ERROR
0xC002001F RPC_NT_UNSUPPORTED_TRANS_SYN
0xC0020021 RPC_NT_UNSUPPORTED_TYPE
0xC0020022 RPC_NT_INVALID_TAG
0xC0020023 RPC_NT_INVALID_BOUND
0xC0020024 RPC_NT_NO_ENTRY_NAME
0xC0020025 RPC_NT_INVALID_NAME_SYNTAX
0xC0020026 RPC_NT_UNSUPPORTED_NAME_SYNTAX
0xC0020028 RPC_NT_UUID_NO_ADDRESS
0xC0020029 RPC_NT_DUPLICATE_ENDPOINT
0xC002002A RPC_NT_UNKNOWN_AUTHN_TYPE
0xC002002B RPC_NT_MAX_CALLS_TOO_SMALL
0xC002002C RPC_NT_STRING_TOO_LONG
0xC002002D RPC_NT_PROTSEQ_NOT_FOUND
0xC002002E RPC_NT_PROCNUM_OUT_OF_RANGE
0xC002002F RPC_NT_BINDING_HAS_NO_AUTH
0xC0020030 RPC_NT_UNKNOWN_AUTHN_SERVICE
0xC0020031 RPC_NT_UNKNOWN_AUTHN_LEVEL
0xC0020032 RPC_NT_INVALID_AUTH_IDENTITY
0xC0020033 RPC_NT_UNKNOWN_AUTHZ_SERVICE
0xC0020034 EPT_NT_INVALID_ENTRY
0xC0020035 EPT_NT_CANT_PERFORM_OP
0xC0020036 EPT_NT_NOT_REGISTERED
0xC0020037 RPC_NT_NOTHING_TO_EXPORT
0xC0020038 RPC_NT_INCOMPLETE_NAME
0xC0020039 RPC_NT_INVALID_VERS_OPTION
0xC002003A RPC_NT_NO_MORE_MEMBERS
0xC002003B RPC_NT_NOT_ALL_OBJS_UNEXPORTED
0xC002003C RPC_NT_INTERFACE_NOT_FOUND
0xC002003D RPC_NT_ENTRY_ALREADY_EXISTS
0xC002003E RPC_NT_ENTRY_NOT_FOUND
0xC002003F RPC_NT_NAME_SERVICE_UNAVAILABLE
0xC0020040 RPC_NT_INVALID_NAF_ID
0xC0020041 RPC_NT_CANNOT_SUPPORT
0xC0020042 RPC_NT_NO_CONTEXT_AVAILABLE
0xC0020043 RPC_NT_INTERNAL_ERROR
0xC0020044 RPC_NT_ZERO_DIVIDE
0xC0020045 RPC_NT_ADDRESS_ERROR
0xC0020046 RPC_NT_FP_DIV_ZERO
0xC0020047 RPC_NT_FP_UNDERFLOW
0xC0020048 RPC_NT_FP_OVERFLOW
0xC0020049 RPC_NT_CALL_IN_PROGRESS
0xC002004A RPC_NT_NO_MORE_BINDINGS
0xC002004B RPC_NT_GROUP_MEMBER_NOT_FOUND
0xC002004C EPT_NT_CANT_CREATE
0xC002004D RPC_NT_INVALID_OBJECT
0xC002004F RPC_NT_NO_INTERFACES
0xC0020050 RPC_NT_CALL_CANCELLED
0xC0020051 RPC_NT_BINDING_INCOMPLETE
0xC0020052 RPC_NT_COMM_FAILURE
0xC0020053 RPC_NT_UNSUPPORTED_AUTHN_LEVEL
0xC0020054 RPC_NT_NO_PRINC_NAME
0xC0020055 RPC_NT_NOT_RPC_ERROR
0xC0020057 RPC_NT_SEC_PKG_ERROR
0xC0020058 RPC_NT_NOT_CANCELLED
0xC0020062 RPC_NT_INVALID_ASYNC_HANDLE
0xC0020063 RPC_NT_INVALID_ASYNC_CALL
0xC0020064 RPC_NT_PROXY_ACCESS_DENIED
0xC0020065 RPC_NT_COOKIE_AUTH_FAILED
0xC0030001 RPC_NT_NO_MORE_ENTRIES
0xC0030002 RPC_NT_SS_CHAR_TRANS_OPEN_FAIL
0xC0030003 RPC_NT_SS_CHAR_TRANS_SHORT_FILE
0xC0030004 RPC_NT_SS_IN_NULL_CONTEXT
0xC0030005 RPC_NT_SS_CONTEXT_MISMATCH
0xC0030006 RPC_NT_SS_CONTEXT_DAMAGED
0xC0030007 RPC_NT_SS_HANDLES_MISMATCH
0xC0030008 RPC_NT_SS_CANNOT_GET_CALL_HANDLE
0xC0030009 RPC_NT_NULL_REF_POINTER
0xC003000A RPC_NT_ENUM_VALUE_OUT_OF_RANGE
0xC003000B RPC_NT_BYTE_COUNT_TOO_SMALL
0xC003000C RPC_NT_BAD_STUB_DATA
0xC0030059 RPC_NT_INVALID_ES_ACTION
0xC003005A RPC_NT_WRONG_ES_VERSION
0xC003005B RPC_NT_WRONG_STUB_VERSION
0xC003005C RPC_NT_INVALID_PIPE_OBJECT
0xC003005D RPC_NT_INVALID_PIPE_OPERATION
0xC003005E RPC_NT_WRONG_PIPE_VERSION
0xC003005F RPC_NT_PIPE_CLOSED
0xC0030060 RPC_NT_PIPE_DISCIPLINE_ERROR
0xC0030061 RPC_NT_PIPE_EMPTY
0xC0040035 STATUS_PNP_BAD_MPS_TABLE
0xC0040036 STATUS_PNP_TRANSLATION_FAILED
0xC0040037 STATUS_PNP_IRQ_TRANSLATION_FAILED
0xC0040038 STATUS_PNP_INVALID_ID
0xC0040039 STATUS_IO_REISSUE_AS_CACHED
0xC00A0001 STATUS_CTX_WINSTATION_NAME_INVALID
0xC00A0002 STATUS_CTX_INVALID_PD
0xC00A0003 STATUS_CTX_PD_NOT_FOUND
0xC00A0006 STATUS_CTX_CLOSE_PENDING
0xC00A0007 STATUS_CTX_NO_OUTBUF
0xC00A0008 STATUS_CTX_MODEM_INF_NOT_FOUND
0xC00A0009 STATUS_CTX_INVALID_MODEMNAME
0xC00A000A STATUS_CTX_RESPONSE_ERROR
0xC00A000B STATUS_CTX_MODEM_RESPONSE_TIMEOUT
0xC00A000C STATUS_CTX_MODEM_RESPONSE_NO_CARRIER
0xC00A000D STATUS_CTX_MODEM_RESPONSE_NO_DIALTONE
0xC00A000E STATUS_CTX_MODEM_RESPONSE_BUSY
0xC00A000F STATUS_CTX_MODEM_RESPONSE_VOICE
0xC00A0010 STATUS_CTX_TD_ERROR
0xC00A0012 STATUS_CTX_LICENSE_CLIENT_INVALID
0xC00A0013 STATUS_CTX_LICENSE_NOT_AVAILABLE
0xC00A0014 STATUS_CTX_LICENSE_EXPIRED
0xC00A0015 STATUS_CTX_WINSTATION_NOT_FOUND
0xC00A0016 STATUS_CTX_WINSTATION_NAME_COLLISION
0xC00A0017 STATUS_CTX_WINSTATION_BUSY
0xC00A0018 STATUS_CTX_BAD_VIDEO_MODE
0xC00A0022 STATUS_CTX_GRAPHICS_INVALID
0xC00A0024 STATUS_CTX_NOT_CONSOLE
0xC00A0026 STATUS_CTX_CLIENT_QUERY_TIMEOUT
0xC00A0027 STATUS_CTX_CONSOLE_DISCONNECT
0xC00A0028 STATUS_CTX_CONSOLE_CONNECT
0xC00A002A STATUS_CTX_SHADOW_DENIED
0xC00A002B STATUS_CTX_WINSTATION_ACCESS_DENIED
0xC00A002E STATUS_CTX_INVALID_WD
0xC00A002F STATUS_CTX_WD_NOT_FOUND
0xC00A0030 STATUS_CTX_SHADOW_INVALID
0xC00A0031 STATUS_CTX_SHADOW_DISABLED
0xC00A0032 STATUS_RDP_PROTOCOL_ERROR
0xC00A0033 STATUS_CTX_CLIENT_LICENSE_NOT_SET
0xC00A0034 STATUS_CTX_CLIENT_LICENSE_IN_USE
0xC00A0035 STATUS_CTX_SHADOW_ENDED_BY_MODE_CHANGE
0xC00A0036 STATUS_CTX_SHADOW_NOT_RUNNING
0xC00A0037 STATUS_CTX_LOGON_DISABLED
0xC00A0038 STATUS_CTX_SECURITY_LAYER_ERROR
0xC00A0039 STATUS_TS_INCOMPATIBLE_SESSIONS
0xC00A003A STATUS_TS_VIDEO_SUBSYSTEM_ERROR
0xC00B0001 STATUS_MUI_FILE_NOT_FOUND
0xC00B0002 STATUS_MUI_INVALID_FILE
0xC00B0003 STATUS_MUI_INVALID_RC_CONFIG
0xC00B0004 STATUS_MUI_INVALID_LOCALE_NAME
0xC00B0005 STATUS_MUI_INVALID_ULTIMATEFALLBACK_NAME
0xC00B0006 STATUS_MUI_FILE_NOT_LOADED
0xC00B0007 STATUS_RESOURCE_ENUM_USER_STOP
0xC0130001 STATUS_CLUSTER_INVALID_NODE
0xC0130002 STATUS_CLUSTER_NODE_EXISTS
0xC0130003 STATUS_CLUSTER_JOIN_IN_PROGRESS
0xC0130004 STATUS_CLUSTER_NODE_NOT_FOUND
0xC0130005 STATUS_CLUSTER_LOCAL_NODE_NOT_FOUND
0xC0130006 STATUS_CLUSTER_NETWORK_EXISTS
0xC0130007 STATUS_CLUSTER_NETWORK_NOT_FOUND
0xC0130008 STATUS_CLUSTER_NETINTERFACE_EXISTS
0xC0130009 STATUS_CLUSTER_NETINTERFACE_NOT_FOUND
0xC013000A STATUS_CLUSTER_INVALID_REQUEST
0xC013000B STATUS_CLUSTER_INVALID_NETWORK_PROVIDER
0xC013000C STATUS_CLUSTER_NODE_DOWN
0xC013000D STATUS_CLUSTER_NODE_UNREACHABLE
0xC013000E STATUS_CLUSTER_NODE_NOT_MEMBER
0xC013000F STATUS_CLUSTER_JOIN_NOT_IN_PROGRESS
0xC0130010 STATUS_CLUSTER_INVALID_NETWORK
0xC0130011 STATUS_CLUSTER_NO_NET_ADAPTERS
0xC0130012 STATUS_CLUSTER_NODE_UP
0xC0130013 STATUS_CLUSTER_NODE_PAUSED
0xC0130014 STATUS_CLUSTER_NODE_NOT_PAUSED
0xC0130015 STATUS_CLUSTER_NO_SECURITY_CONTEXT
0xC0130016 STATUS_CLUSTER_NETWORK_NOT_INTERNAL
0xC0130017 STATUS_CLUSTER_POISONED
0xC0130018 STATUS_CLUSTER_NON_CSV_PATH
0xC0130019 STATUS_CLUSTER_CSV_VOLUME_NOT_LOCAL
0xC0130020 STATUS_CLUSTER_CSV_READ_OPLOCK_BREAK_IN_PROGRESS
0xC0130021 STATUS_CLUSTER_CSV_AUTO_PAUSE_ERROR
0xC0130022 STATUS_CLUSTER_CSV_REDIRECTED
0xC0130023 STATUS_CLUSTER_CSV_NOT_REDIRECTED
0xC0130024 STATUS_CLUSTER_CSV_VOLUME_DRAINING
0xC0130025 STATUS_CLUSTER_CSV_SNAPSHOT_CREATION_IN_PROGRESS
0xC0130026 STATUS_CLUSTER_CSV_VOLUME_DRAINING_SUCCEEDED_DOWNLEVEL
0xC0130027 STATUS_CLUSTER_CSV_NO_SNAPSHOTS
0xC0130028 STATUS_CSV_IO_PAUSE_TIMEOUT
0xC0130029 STATUS_CLUSTER_CSV_INVALID_HANDLE
0xC0130030 STATUS_CLUSTER_CSV_SUPPORTED_ONLY_ON_COORDINATOR
0xC0130031 STATUS_CLUSTER_CAM_TICKET_REPLAY_DETECTED
0xC0140001 STATUS_ACPI_INVALID_OPCODE
0xC0140002 STATUS_ACPI_STACK_OVERFLOW
0xC0140003 STATUS_ACPI_ASSERT_FAILED
0xC0140004 STATUS_ACPI_INVALID_INDEX
0xC0140005 STATUS_ACPI_INVALID_ARGUMENT
0xC0140006 STATUS_ACPI_FATAL
0xC0140007 STATUS_ACPI_INVALID_SUPERNAME
0xC0140008 STATUS_ACPI_INVALID_ARGTYPE
0xC0140009 STATUS_ACPI_INVALID_OBJTYPE
0xC014000A STATUS_ACPI_INVALID_TARGETTYPE
0xC014000B STATUS_ACPI_INCORRECT_ARGUMENT_COUNT
0xC014000C STATUS_ACPI_ADDRESS_NOT_MAPPED
0xC014000D STATUS_ACPI_INVALID_EVENTTYPE
0xC014000E STATUS_ACPI_HANDLER_COLLISION
0xC014000F STATUS_ACPI_INVALID_DATA
0xC0140010 STATUS_ACPI_INVALID_REGION
0xC0140011 STATUS_ACPI_INVALID_ACCESS_SIZE
0xC0140012 STATUS_ACPI_ACQUIRE_GLOBAL_LOCK
0xC0140013 STATUS_ACPI_ALREADY_INITIALIZED
0xC0140014 STATUS_ACPI_NOT_INITIALIZED
0xC0140015 STATUS_ACPI_INVALID_MUTEX_LEVEL
0xC0140016 STATUS_ACPI_MUTEX_NOT_OWNED
0xC0140017 STATUS_ACPI_MUTEX_NOT_OWNER
0xC0140018 STATUS_ACPI_RS_ACCESS
0xC0140019 STATUS_ACPI_INVALID_TABLE
0xC0140020 STATUS_ACPI_REG_HANDLER_FAILED
0xC0140021 STATUS_ACPI_POWER_REQUEST_FAILED
0xC0150001 STATUS_SXS_SECTION_NOT_FOUND
0xC0150002 STATUS_SXS_CANT_GEN_ACTCTX
0xC0150003 STATUS_SXS_INVALID_ACTCTXDATA_FORMAT
0xC0150004 STATUS_SXS_ASSEMBLY_NOT_FOUND
0xC0150005 STATUS_SXS_MANIFEST_FORMAT_ERROR
0xC0150006 STATUS_SXS_MANIFEST_PARSE_ERROR
0xC0150007 STATUS_SXS_ACTIVATION_CONTEXT_DISABLED
0xC0150008 STATUS_SXS_KEY_NOT_FOUND
0xC0150009 STATUS_SXS_VERSION_CONFLICT
0xC015000A STATUS_SXS_WRONG_SECTION_TYPE
0xC015000B STATUS_SXS_THREAD_QUERIES_DISABLED
0xC015000C STATUS_SXS_ASSEMBLY_MISSING
0xC015000E STATUS_SXS_PROCESS_DEFAULT_ALREADY_SET
0xC015000F STATUS_SXS_EARLY_DEACTIVATION
0xC0150010 STATUS_SXS_INVALID_DEACTIVATION
0xC0150011 STATUS_SXS_MULTIPLE_DEACTIVATION
0xC0150012 STATUS_SXS_SYSTEM_DEFAULT_ACTIVATION_CONTEXT_EMPTY
0xC0150013 STATUS_SXS_PROCESS_TERMINATION_REQUESTED
0xC0150014 STATUS_SXS_CORRUPT_ACTIVATION_STACK
0xC0150015 STATUS_SXS_CORRUPTION
0xC0150016 STATUS_SXS_INVALID_IDENTITY_ATTRIBUTE_VALUE
0xC0150017 STATUS_SXS_INVALID_IDENTITY_ATTRIBUTE_NAME
0xC0150018 STATUS_SXS_IDENTITY_DUPLICATE_ATTRIBUTE
0xC0150019 STATUS_SXS_IDENTITY_PARSE_ERROR
0xC015001A STATUS_SXS_COMPONENT_STORE_CORRUPT
0xC015001B STATUS_SXS_FILE_HASH_MISMATCH
0xC015001C STATUS_SXS_MANIFEST_IDENTITY_SAME_BUT_CONTENTS_DIFFERENT
0xC015001D STATUS_SXS_IDENTITIES_DIFFERENT
0xC015001E STATUS_SXS_ASSEMBLY_IS_NOT_A_DEPLOYMENT
0xC015001F STATUS_SXS_FILE_NOT_PART_OF_ASSEMBLY
0xC0150020 STATUS_ADVANCED_INSTALLER_FAILED
0xC0150021 STATUS_XML_ENCODING_MISMATCH
0xC0150022 STATUS_SXS_MANIFEST_TOO_BIG
0xC0150023 STATUS_SXS_SETTING_NOT_REGISTERED
0xC0150024 STATUS_SXS_TRANSACTION_CLOSURE_INCOMPLETE
0xC0150025 STATUS_SMI_PRIMITIVE_INSTALLER_FAILED
0xC0150026 STATUS_GENERIC_COMMAND_FAILED
0xC0150027 STATUS_SXS_FILE_HASH_MISSING
0xC0190001 STATUS_TRANSACTIONAL_CONFLICT
0xC0190002 STATUS_INVALID_TRANSACTION
0xC0190003 STATUS_TRANSACTION_NOT_ACTIVE
0xC0190004 STATUS_TM_INITIALIZATION_FAILED
0xC0190005 STATUS_RM_NOT_ACTIVE
0xC0190006 STATUS_RM_METADATA_CORRUPT
0xC0190007 STATUS_TRANSACTION_NOT_JOINED
0xC0190008 STATUS_DIRECTORY_NOT_RM
0xC019000A STATUS_TRANSACTIONS_UNSUPPORTED_REMOTE
0xC019000B STATUS_LOG_RESIZE_INVALID_SIZE
0xC019000C STATUS_REMOTE_FILE_VERSION_MISMATCH
0xC019000F STATUS_CRM_PROTOCOL_ALREADY_EXISTS
0xC0190010 STATUS_TRANSACTION_PROPAGATION_FAILED
0xC0190011 STATUS_CRM_PROTOCOL_NOT_FOUND
0xC0190012 STATUS_TRANSACTION_SUPERIOR_EXISTS
0xC0190013 STATUS_TRANSACTION_REQUEST_NOT_VALID
0xC0190014 STATUS_TRANSACTION_NOT_REQUESTED
0xC0190015 STATUS_TRANSACTION_ALREADY_ABORTED
0xC0190016 STATUS_TRANSACTION_ALREADY_COMMITTED
0xC0190017 STATUS_TRANSACTION_INVALID_MARSHALL_BUFFER
0xC0190018 STATUS_CURRENT_TRANSACTION_NOT_VALID
0xC0190019 STATUS_LOG_GROWTH_FAILED
0xC0190021 STATUS_OBJECT_NO_LONGER_EXISTS
0xC0190022 STATUS_STREAM_MINIVERSION_NOT_FOUND
0xC0190023 STATUS_STREAM_MINIVERSION_NOT_VALID
0xC0190024 STATUS_MINIVERSION_INACCESSIBLE_FROM_SPECIFIED_TRANSACTION
0xC0190025 STATUS_CANT_OPEN_MINIVERSION_WITH_MODIFY_INTENT
0xC0190026 STATUS_CANT_CREATE_MORE_STREAM_MINIVERSIONS
0xC0190028 STATUS_HANDLE_NO_LONGER_VALID
0xC0190030 STATUS_LOG_CORRUPTION_DETECTED
0xC0190032 STATUS_RM_DISCONNECTED
0xC0190033 STATUS_ENLISTMENT_NOT_SUPERIOR
0xC0190036 STATUS_FILE_IDENTITY_NOT_PERSISTENT
0xC0190037 STATUS_CANT_BREAK_TRANSACTIONAL_DEPENDENCY
0xC0190038 STATUS_CANT_CROSS_RM_BOUNDARY
0xC0190039 STATUS_TXF_DIR_NOT_EMPTY
0xC019003A STATUS_INDOUBT_TRANSACTIONS_EXIST
0xC019003B STATUS_TM_VOLATILE
0xC019003C STATUS_ROLLBACK_TIMER_EXPIRED
0xC019003D STATUS_TXF_ATTRIBUTE_CORRUPT
0xC019003E STATUS_EFS_NOT_ALLOWED_IN_TRANSACTION
0xC019003F STATUS_TRANSACTIONAL_OPEN_NOT_ALLOWED
0xC0190040 STATUS_TRANSACTED_MAPPING_UNSUPPORTED_REMOTE
0xC0190043 STATUS_TRANSACTION_REQUIRED_PROMOTION
0xC0190044 STATUS_CANNOT_EXECUTE_FILE_IN_TRANSACTION
0xC0190045 STATUS_TRANSACTIONS_NOT_FROZEN
0xC0190046 STATUS_TRANSACTION_FREEZE_IN_PROGRESS
0xC0190047 STATUS_NOT_SNAPSHOT_VOLUME
0xC0190048 STATUS_NO_SAVEPOINT_WITH_OPEN_FILES
0xC0190049 STATUS_SPARSE_NOT_ALLOWED_IN_TRANSACTION
0xC019004A STATUS_TM_IDENTITY_MISMATCH
0xC019004B STATUS_FLOATED_SECTION
0xC019004C STATUS_CANNOT_ACCEPT_TRANSACTED_WORK
0xC019004D STATUS_CANNOT_ABORT_TRANSACTIONS
0xC019004E STATUS_TRANSACTION_NOT_FOUND
0xC019004F STATUS_RESOURCEMANAGER_NOT_FOUND
0xC0190050 STATUS_ENLISTMENT_NOT_FOUND
0xC0190051 STATUS_TRANSACTIONMANAGER_NOT_FOUND
0xC0190052 STATUS_TRANSACTIONMANAGER_NOT_ONLINE
0xC0190053 STATUS_TRANSACTIONMANAGER_RECOVERY_NAME_COLLISION
0xC0190054 STATUS_TRANSACTION_NOT_ROOT
0xC0190055 STATUS_TRANSACTION_OBJECT_EXPIRED
0xC0190056 STATUS_COMPRESSION_NOT_ALLOWED_IN_TRANSACTION
0xC0190057 STATUS_TRANSACTION_RESPONSE_NOT_ENLISTED
0xC0190058 STATUS_TRANSACTION_RECORD_TOO_LONG
0xC0190059 STATUS_NO_LINK_TRACKING_IN_TRANSACTION
0xC019005A STATUS_OPERATION_NOT_SUPPORTED_IN_TRANSACTION
0xC019005B STATUS_TRANSACTION_INTEGRITY_VIOLATED
0xC019005C STATUS_TRANSACTIONMANAGER_IDENTITY_MISMATCH
0xC019005D STATUS_RM_CANNOT_BE_FROZEN_FOR_SNAPSHOT
0xC019005E STATUS_TRANSACTION_MUST_WRITETHROUGH
0xC019005F STATUS_TRANSACTION_NO_SUPERIOR
0xC0190060 STATUS_EXPIRED_HANDLE
0xC0190061 STATUS_TRANSACTION_NOT_ENLISTED
0xC01A0001 STATUS_LOG_SECTOR_INVALID
0xC01A0002 STATUS_LOG_SECTOR_PARITY_INVALID
0xC01A0003 STATUS_LOG_SECTOR_REMAPPED
0xC01A0004 STATUS_LOG_BLOCK_INCOMPLETE
0xC01A0005 STATUS_LOG_INVALID_RANGE
0xC01A0006 STATUS_LOG_BLOCKS_EXHAUSTED
0xC01A0007 STATUS_LOG_READ_CONTEXT_INVALID
0xC01A0008 STATUS_LOG_RESTART_INVALID
0xC01A0009 STATUS_LOG_BLOCK_VERSION
0xC01A000A STATUS_LOG_BLOCK_INVALID
0xC01A000B STATUS_LOG_READ_MODE_INVALID
0xC01A000D STATUS_LOG_METADATA_CORRUPT
0xC01A000E STATUS_LOG_METADATA_INVALID
0xC01A000F STATUS_LOG_METADATA_INCONSISTENT
0xC01A0010 STATUS_LOG_RESERVATION_INVALID
0xC01A0011 STATUS_LOG_CANT_DELETE
0xC01A0012 STATUS_LOG_CONTAINER_LIMIT_EXCEEDED
0xC01A0013 STATUS_LOG_START_OF_LOG
0xC01A0014 STATUS_LOG_POLICY_ALREADY_INSTALLED
0xC01A0015 STATUS_LOG_POLICY_NOT_INSTALLED
0xC01A0016 STATUS_LOG_POLICY_INVALID
0xC01A0017 STATUS_LOG_POLICY_CONFLICT
0xC01A0018 STATUS_LOG_PINNED_ARCHIVE_TAIL
0xC01A0019 STATUS_LOG_RECORD_NONEXISTENT
0xC01A001A STATUS_LOG_RECORDS_RESERVED_INVALID
0xC01A001B STATUS_LOG_SPACE_RESERVED_INVALID
0xC01A001C STATUS_LOG_TAIL_INVALID
0xC01A001D STATUS_LOG_FULL
0xC01A001E STATUS_LOG_MULTIPLEXED
0xC01A001F STATUS_LOG_DEDICATED
0xC01A0020 STATUS_LOG_ARCHIVE_NOT_IN_PROGRESS
0xC01A0021 STATUS_LOG_ARCHIVE_IN_PROGRESS
0xC01A0022 STATUS_LOG_EPHEMERAL
0xC01A0023 STATUS_LOG_NOT_ENOUGH_CONTAINERS
0xC01A0024 STATUS_LOG_CLIENT_ALREADY_REGISTERED
0xC01A0025 STATUS_LOG_CLIENT_NOT_REGISTERED
0xC01A0026 STATUS_LOG_FULL_HANDLER_IN_PROGRESS
0xC01A0027 STATUS_LOG_CONTAINER_READ_FAILED
0xC01A0028 STATUS_LOG_CONTAINER_WRITE_FAILED
0xC01A0029 STATUS_LOG_CONTAINER_OPEN_FAILED
0xC01A002A STATUS_LOG_CONTAINER_STATE_INVALID
0xC01A002B STATUS_LOG_STATE_INVALID
0xC01A002C STATUS_LOG_PINNED
0xC01A002D STATUS_LOG_METADATA_FLUSH_FAILED
0xC01A002E STATUS_LOG_INCONSISTENT_SECURITY
0xC01A002F STATUS_LOG_APPENDED_FLUSH_FAILED
0xC01A0030 STATUS_LOG_PINNED_RESERVATION
0xC01B00EA STATUS_VIDEO_HUNG_DISPLAY_DRIVER_THREAD
0xC01C0001 STATUS_FLT_NO_HANDLER_DEFINED
0xC01C0002 STATUS_FLT_CONTEXT_ALREADY_DEFINED
0xC01C0003 STATUS_FLT_INVALID_ASYNCHRONOUS_REQUEST
0xC01C0004 STATUS_FLT_DISALLOW_FAST_IO
0xC01C0005 STATUS_FLT_INVALID_NAME_REQUEST
0xC01C0006 STATUS_FLT_NOT_SAFE_TO_POST_OPERATION
0xC01C0007 STATUS_FLT_NOT_INITIALIZED
0xC01C0008 STATUS_FLT_FILTER_NOT_READY
0xC01C0009 STATUS_FLT_POST_OPERATION_CLEANUP
0xC01C000A STATUS_FLT_INTERNAL_ERROR
0xC01C000B STATUS_FLT_DELETING_OBJECT
0xC01C000C STATUS_FLT_MUST_BE_NONPAGED_POOL
0xC01C000D STATUS_FLT_DUPLICATE_ENTRY
0xC01C000E STATUS_FLT_CBDQ_DISABLED
0xC01C000F STATUS_FLT_DO_NOT_ATTACH
0xC01C0010 STATUS_FLT_DO_NOT_DETACH
0xC01C0011 STATUS_FLT_INSTANCE_ALTITUDE_COLLISION
0xC01C0012 STATUS_FLT_INSTANCE_NAME_COLLISION
0xC01C0013 STATUS_FLT_FILTER_NOT_FOUND
0xC01C0014 STATUS_FLT_VOLUME_NOT_FOUND
0xC01C0015 STATUS_FLT_INSTANCE_NOT_FOUND
0xC01C0016 STATUS_FLT_CONTEXT_ALLOCATION_NOT_FOUND
0xC01C0017 STATUS_FLT_INVALID_CONTEXT_REGISTRATION
0xC01C0018 STATUS_FLT_NAME_CACHE_MISS
0xC01C0019 STATUS_FLT_NO_DEVICE_OBJECT
0xC01C001A STATUS_FLT_VOLUME_ALREADY_MOUNTED
0xC01C001B STATUS_FLT_ALREADY_ENLISTED
0xC01C001C STATUS_FLT_CONTEXT_ALREADY_LINKED
0xC01C0020 STATUS_FLT_NO_WAITER_FOR_REPLY
0xC01C0023 STATUS_FLT_REGISTRATION_BUSY
0xC01D0001 STATUS_MONITOR_NO_DESCRIPTOR
0xC01D0002 STATUS_MONITOR_UNKNOWN_DESCRIPTOR_FORMAT
0xC01D0003 STATUS_MONITOR_INVALID_DESCRIPTOR_CHECKSUM
0xC01D0004 STATUS_MONITOR_INVALID_STANDARD_TIMING_BLOCK
0xC01D0005 STATUS_MONITOR_WMI_DATABLOCK_REGISTRATION_FAILED
0xC01D0006 STATUS_MONITOR_INVALID_SERIAL_NUMBER_MONDSC_BLOCK
0xC01D0007 STATUS_MONITOR_INVALID_USER_FRIENDLY_MONDSC_BLOCK
0xC01D0008 STATUS_MONITOR_NO_MORE_DESCRIPTOR_DATA
0xC01D0009 STATUS_MONITOR_INVALID_DETAILED_TIMING_BLOCK
0xC01D000A STATUS_MONITOR_INVALID_MANUFACTURE_DATE
0xC01E0000 STATUS_GRAPHICS_NOT_EXCLUSIVE_MODE_OWNER
0xC01E0001 STATUS_GRAPHICS_INSUFFICIENT_DMA_BUFFER
0xC01E0002 STATUS_GRAPHICS_INVALID_DISPLAY_ADAPTER
0xC01E0003 STATUS_GRAPHICS_ADAPTER_WAS_RESET
0xC01E0004 STATUS_GRAPHICS_INVALID_DRIVER_MODEL
0xC01E0005 STATUS_GRAPHICS_PRESENT_MODE_CHANGED
0xC01E0006 STATUS_GRAPHICS_PRESENT_OCCLUDED
0xC01E0007 STATUS_GRAPHICS_PRESENT_DENIED
0xC01E0008 STATUS_GRAPHICS_CANNOTCOLORCONVERT
0xC01E0009 STATUS_GRAPHICS_DRIVER_MISMATCH
0xC01E000B STATUS_GRAPHICS_PRESENT_REDIRECTION_DISABLED
0xC01E000C STATUS_GRAPHICS_PRESENT_UNOCCLUDED
0xC01E000D STATUS_GRAPHICS_WINDOWDC_NOT_AVAILABLE
0xC01E000E STATUS_GRAPHICS_WINDOWLESS_PRESENT_DISABLED
0xC01E0100 STATUS_GRAPHICS_NO_VIDEO_MEMORY
0xC01E0101 STATUS_GRAPHICS_CANT_LOCK_MEMORY
0xC01E0102 STATUS_GRAPHICS_ALLOCATION_BUSY
0xC01E0103 STATUS_GRAPHICS_TOO_MANY_REFERENCES
0xC01E0104 STATUS_GRAPHICS_TRY_AGAIN_LATER
0xC01E0105 STATUS_GRAPHICS_TRY_AGAIN_NOW
0xC01E0106 STATUS_GRAPHICS_ALLOCATION_INVALID
0xC01E0107 STATUS_GRAPHICS_UNSWIZZLING_APERTURE_UNAVAILABLE
0xC01E0108 STATUS_GRAPHICS_UNSWIZZLING_APERTURE_UNSUPPORTED
0xC01E0109 STATUS_GRAPHICS_CANT_EVICT_PINNED_ALLOCATION
0xC01E0110 STATUS_GRAPHICS_INVALID_ALLOCATION_USAGE
0xC01E0111 STATUS_GRAPHICS_CANT_RENDER_LOCKED_ALLOCATION
0xC01E0112 STATUS_GRAPHICS_ALLOCATION_CLOSED
0xC01E0113 STATUS_GRAPHICS_INVALID_ALLOCATION_INSTANCE
0xC01E0114 STATUS_GRAPHICS_INVALID_ALLOCATION_HANDLE
0xC01E0115 STATUS_GRAPHICS_WRONG_ALLOCATION_DEVICE
0xC01E0116 STATUS_GRAPHICS_ALLOCATION_CONTENT_LOST
0xC01E0200 STATUS_GRAPHICS_GPU_EXCEPTION_ON_DEVICE
0xC01E0300 STATUS_GRAPHICS_INVALID_VIDPN_TOPOLOGY
0xC01E0301 STATUS_GRAPHICS_VIDPN_TOPOLOGY_NOT_SUPPORTED
0xC01E0302 STATUS_GRAPHICS_VIDPN_TOPOLOGY_CURRENTLY_NOT_SUPPORTED
0xC01E0303 STATUS_GRAPHICS_INVALID_VIDPN
0xC01E0304 STATUS_GRAPHICS_INVALID_VIDEO_PRESENT_SOURCE
0xC01E0305 STATUS_GRAPHICS_INVALID_VIDEO_PRESENT_TARGET
0xC01E0306 STATUS_GRAPHICS_VIDPN_MODALITY_NOT_SUPPORTED
0xC01E0308 STATUS_GRAPHICS_INVALID_VIDPN_SOURCEMODESET
0xC01E0309 STATUS_GRAPHICS_INVALID_VIDPN_TARGETMODESET
0xC01E030A STATUS_GRAPHICS_INVALID_FREQUENCY
0xC01E030B STATUS_GRAPHICS_INVALID_ACTIVE_REGION
0xC01E030C STATUS_GRAPHICS_INVALID_TOTAL_REGION
0xC01E0310 STATUS_GRAPHICS_INVALID_VIDEO_PRESENT_SOURCE_MODE
0xC01E0311 STATUS_GRAPHICS_INVALID_VIDEO_PRESENT_TARGET_MODE
0xC01E0312 STATUS_GRAPHICS_PINNED_MODE_MUST_REMAIN_IN_SET
0xC01E0313 STATUS_GRAPHICS_PATH_ALREADY_IN_TOPOLOGY
0xC01E0314 STATUS_GRAPHICS_MODE_ALREADY_IN_MODESET
0xC01E0315 STATUS_GRAPHICS_INVALID_VIDEOPRESENTSOURCESET
0xC01E0316 STATUS_GRAPHICS_INVALID_VIDEOPRESENTTARGETSET
0xC01E0317 STATUS_GRAPHICS_SOURCE_ALREADY_IN_SET
0xC01E0318 STATUS_GRAPHICS_TARGET_ALREADY_IN_SET
0xC01E0319 STATUS_GRAPHICS_INVALID_VIDPN_PRESENT_PATH
0xC01E031A STATUS_GRAPHICS_NO_RECOMMENDED_VIDPN_TOPOLOGY
0xC01E031B STATUS_GRAPHICS_INVALID_MONITOR_FREQUENCYRANGESET
0xC01E031C STATUS_GRAPHICS_INVALID_MONITOR_FREQUENCYRANGE
0xC01E031D STATUS_GRAPHICS_FREQUENCYRANGE_NOT_IN_SET
0xC01E031F STATUS_GRAPHICS_FREQUENCYRANGE_ALREADY_IN_SET
0xC01E0320 STATUS_GRAPHICS_STALE_MODESET
0xC01E0321 STATUS_GRAPHICS_INVALID_MONITOR_SOURCEMODESET
0xC01E0322 STATUS_GRAPHICS_INVALID_MONITOR_SOURCE_MODE
0xC01E0323 STATUS_GRAPHICS_NO_RECOMMENDED_FUNCTIONAL_VIDPN
0xC01E0324 STATUS_GRAPHICS_MODE_ID_MUST_BE_UNIQUE
0xC01E0325 STATUS_GRAPHICS_EMPTY_ADAPTER_MONITOR_MODE_SUPPORT_INTERSECTION
0xC01E0326 STATUS_GRAPHICS_VIDEO_PRESENT_TARGETS_LESS_THAN_SOURCES
0xC01E0327 STATUS_GRAPHICS_PATH_NOT_IN_TOPOLOGY
0xC01E0328 STATUS_GRAPHICS_ADAPTER_MUST_HAVE_AT_LEAST_ONE_SOURCE
0xC01E0329 STATUS_GRAPHICS_ADAPTER_MUST_HAVE_AT_LEAST_ONE_TARGET
0xC01E032A STATUS_GRAPHICS_INVALID_MONITORDESCRIPTORSET
0xC01E032B STATUS_GRAPHICS_INVALID_MONITORDESCRIPTOR
0xC01E032C STATUS_GRAPHICS_MONITORDESCRIPTOR_NOT_IN_SET
0xC01E032D STATUS_GRAPHICS_MONITORDESCRIPTOR_ALREADY_IN_SET
0xC01E032E STATUS_GRAPHICS_MONITORDESCRIPTOR_ID_MUST_BE_UNIQUE
0xC01E032F STATUS_GRAPHICS_INVALID_VIDPN_TARGET_SUBSET_TYPE
0xC01E0330 STATUS_GRAPHICS_RESOURCES_NOT_RELATED
0xC01E0331 STATUS_GRAPHICS_SOURCE_ID_MUST_BE_UNIQUE
0xC01E0332 STATUS_GRAPHICS_TARGET_ID_MUST_BE_UNIQUE
0xC01E0333 STATUS_GRAPHICS_NO_AVAILABLE_VIDPN_TARGET
0xC01E0334 STATUS_GRAPHICS_MONITOR_COULD_NOT_BE_ASSOCIATED_WITH_ADAPTER
0xC01E0335 STATUS_GRAPHICS_NO_VIDPNMGR
0xC01E0336 STATUS_GRAPHICS_NO_ACTIVE_VIDPN
0xC01E0337 STATUS_GRAPHICS_STALE_VIDPN_TOPOLOGY
0xC01E0338 STATUS_GRAPHICS_MONITOR_NOT_CONNECTED
0xC01E0339 STATUS_GRAPHICS_SOURCE_NOT_IN_TOPOLOGY
0xC01E033A STATUS_GRAPHICS_INVALID_PRIMARYSURFACE_SIZE
0xC01E033B STATUS_GRAPHICS_INVALID_VISIBLEREGION_SIZE
0xC01E033C STATUS_GRAPHICS_INVALID_STRIDE
0xC01E033D STATUS_GRAPHICS_INVALID_PIXELFORMAT
0xC01E033E STATUS_GRAPHICS_INVALID_COLORBASIS
0xC01E033F STATUS_GRAPHICS_INVALID_PIXELVALUEACCESSMODE
0xC01E0340 STATUS_GRAPHICS_TARGET_NOT_IN_TOPOLOGY
0xC01E0341 STATUS_GRAPHICS_NO_DISPLAY_MODE_MANAGEMENT_SUPPORT
0xC01E0342 STATUS_GRAPHICS_VIDPN_SOURCE_IN_USE
0xC01E0343 STATUS_GRAPHICS_CANT_ACCESS_ACTIVE_VIDPN
0xC01E0344 STATUS_GRAPHICS_INVALID_PATH_IMPORTANCE_ORDINAL
0xC01E0345 STATUS_GRAPHICS_INVALID_PATH_CONTENT_GEOMETRY_TRANSFORMATION
0xC01E0346 STATUS_GRAPHICS_PATH_CONTENT_GEOMETRY_TRANSFORMATION_NOT_SUPPORTED
0xC01E0347 STATUS_GRAPHICS_INVALID_GAMMA_RAMP
0xC01E0348 STATUS_GRAPHICS_GAMMA_RAMP_NOT_SUPPORTED
0xC01E0349 STATUS_GRAPHICS_MULTISAMPLING_NOT_SUPPORTED
0xC01E034A STATUS_GRAPHICS_MODE_NOT_IN_MODESET
0xC01E034D STATUS_GRAPHICS_INVALID_VIDPN_TOPOLOGY_RECOMMENDATION_REASON
0xC01E034E STATUS_GRAPHICS_INVALID_PATH_CONTENT_TYPE
0xC01E034F STATUS_GRAPHICS_INVALID_COPYPROTECTION_TYPE
0xC01E0350 STATUS_GRAPHICS_UNASSIGNED_MODESET_ALREADY_EXISTS
0xC01E0352 STATUS_GRAPHICS_INVALID_SCANLINE_ORDERING
0xC01E0353 STATUS_GRAPHICS_TOPOLOGY_CHANGES_NOT_ALLOWED
0xC01E0354 STATUS_GRAPHICS_NO_AVAILABLE_IMPORTANCE_ORDINALS
0xC01E0355 STATUS_GRAPHICS_INCOMPATIBLE_PRIVATE_FORMAT
0xC01E0356 STATUS_GRAPHICS_INVALID_MODE_PRUNING_ALGORITHM
0xC01E0357 STATUS_GRAPHICS_INVALID_MONITOR_CAPABILITY_ORIGIN
0xC01E0358 STATUS_GRAPHICS_INVALID_MONITOR_FREQUENCYRANGE_CONSTRAINT
0xC01E0359 STATUS_GRAPHICS_MAX_NUM_PATHS_REACHED
0xC01E035A STATUS_GRAPHICS_CANCEL_VIDPN_TOPOLOGY_AUGMENTATION
0xC01E035B STATUS_GRAPHICS_INVALID_CLIENT_TYPE
0xC01E035C STATUS_GRAPHICS_CLIENTVIDPN_NOT_SET
0xC01E0400 STATUS_GRAPHICS_SPECIFIED_CHILD_ALREADY_CONNECTED
0xC01E0401 STATUS_GRAPHICS_CHILD_DESCRIPTOR_NOT_SUPPORTED
0xC01E0430 STATUS_GRAPHICS_NOT_A_LINKED_ADAPTER
0xC01E0431 STATUS_GRAPHICS_LEADLINK_NOT_ENUMERATED
0xC01E0432 STATUS_GRAPHICS_CHAINLINKS_NOT_ENUMERATED
0xC01E0433 STATUS_GRAPHICS_ADAPTER_CHAIN_NOT_READY
0xC01E0434 STATUS_GRAPHICS_CHAINLINKS_NOT_STARTED
0xC01E0435 STATUS_GRAPHICS_CHAINLINKS_NOT_POWERED_ON
0xC01E0436 STATUS_GRAPHICS_INCONSISTENT_DEVICE_LINK_STATE
0xC01E0438 STATUS_GRAPHICS_NOT_POST_DEVICE_DRIVER
0xC01E043B STATUS_GRAPHICS_ADAPTER_ACCESS_NOT_EXCLUDED
0xC01E0500 STATUS_GRAPHICS_OPM_NOT_SUPPORTED
0xC01E0501 STATUS_GRAPHICS_COPP_NOT_SUPPORTED
0xC01E0502 STATUS_GRAPHICS_UAB_NOT_SUPPORTED
0xC01E0503 STATUS_GRAPHICS_OPM_INVALID_ENCRYPTED_PARAMETERS
0xC01E0505 STATUS_GRAPHICS_OPM_NO_PROTECTED_OUTPUTS_EXIST
0xC01E050B STATUS_GRAPHICS_OPM_INTERNAL_ERROR
0xC01E050C STATUS_GRAPHICS_OPM_INVALID_HANDLE
0xC01E050E STATUS_GRAPHICS_PVP_INVALID_CERTIFICATE_LENGTH
0xC01E050F STATUS_GRAPHICS_OPM_SPANNING_MODE_ENABLED
0xC01E0510 STATUS_GRAPHICS_OPM_THEATER_MODE_ENABLED
0xC01E0511 STATUS_GRAPHICS_PVP_HFS_FAILED
0xC01E0512 STATUS_GRAPHICS_OPM_INVALID_SRM
0xC01E0513 STATUS_GRAPHICS_OPM_OUTPUT_DOES_NOT_SUPPORT_HDCP
0xC01E0514 STATUS_GRAPHICS_OPM_OUTPUT_DOES_NOT_SUPPORT_ACP
0xC01E0515 STATUS_GRAPHICS_OPM_OUTPUT_DOES_NOT_SUPPORT_CGMSA
0xC01E0516 STATUS_GRAPHICS_OPM_HDCP_SRM_NEVER_SET
0xC01E0517 STATUS_GRAPHICS_OPM_RESOLUTION_TOO_HIGH
0xC01E0518 STATUS_GRAPHICS_OPM_ALL_HDCP_HARDWARE_ALREADY_IN_USE
0xC01E051A STATUS_GRAPHICS_OPM_PROTECTED_OUTPUT_NO_LONGER_EXISTS
0xC01E051C STATUS_GRAPHICS_OPM_PROTECTED_OUTPUT_DOES_NOT_HAVE_COPP_SEMANTICS
0xC01E051D STATUS_GRAPHICS_OPM_INVALID_INFORMATION_REQUEST
0xC01E051E STATUS_GRAPHICS_OPM_DRIVER_INTERNAL_ERROR
0xC01E051F STATUS_GRAPHICS_OPM_PROTECTED_OUTPUT_DOES_NOT_HAVE_OPM_SEMANTICS
0xC01E0520 STATUS_GRAPHICS_OPM_SIGNALING_NOT_SUPPORTED
0xC01E0521 STATUS_GRAPHICS_OPM_INVALID_CONFIGURATION_REQUEST
0xC01E0580 STATUS_GRAPHICS_I2C_NOT_SUPPORTED
0xC01E0581 STATUS_GRAPHICS_I2C_DEVICE_DOES_NOT_EXIST
0xC01E0582 STATUS_GRAPHICS_I2C_ERROR_TRANSMITTING_DATA
0xC01E0583 STATUS_GRAPHICS_I2C_ERROR_RECEIVING_DATA
0xC01E0584 STATUS_GRAPHICS_DDCCI_VCP_NOT_SUPPORTED
0xC01E0585 STATUS_GRAPHICS_DDCCI_INVALID_DATA
0xC01E0586 STATUS_GRAPHICS_DDCCI_MONITOR_RETURNED_INVALID_TIMING_STATUS_BYTE
0xC01E0587 STATUS_GRAPHICS_DDCCI_INVALID_CAPABILITIES_STRING
0xC01E0588 STATUS_GRAPHICS_MCA_INTERNAL_ERROR
0xC01E0589 STATUS_GRAPHICS_DDCCI_INVALID_MESSAGE_COMMAND
0xC01E058A STATUS_GRAPHICS_DDCCI_INVALID_MESSAGE_LENGTH
0xC01E058B STATUS_GRAPHICS_DDCCI_INVALID_MESSAGE_CHECKSUM
0xC01E058C STATUS_GRAPHICS_INVALID_PHYSICAL_MONITOR_HANDLE
0xC01E058D STATUS_GRAPHICS_MONITOR_NO_LONGER_EXISTS
0xC01E05E0 STATUS_GRAPHICS_ONLY_CONSOLE_SESSION_SUPPORTED
0xC01E05E1 STATUS_GRAPHICS_NO_DISPLAY_DEVICE_CORRESPONDS_TO_NAME
0xC01E05E2 STATUS_GRAPHICS_DISPLAY_DEVICE_NOT_ATTACHED_TO_DESKTOP
0xC01E05E3 STATUS_GRAPHICS_MIRRORING_DEVICES_NOT_SUPPORTED
0xC01E05E4 STATUS_GRAPHICS_INVALID_POINTER
0xC01E05E5 STATUS_GRAPHICS_NO_MONITORS_CORRESPOND_TO_DISPLAY_DEVICE
0xC01E05E6 STATUS_GRAPHICS_PARAMETER_ARRAY_TOO_SMALL
0xC01E05E7 STATUS_GRAPHICS_INTERNAL_ERROR
0xC01E05E8 STATUS_GRAPHICS_SESSION_TYPE_CHANGE_IN_PROGRESS
0xC0210000 STATUS_FVE_LOCKED_VOLUME
0xC0210001 STATUS_FVE_NOT_ENCRYPTED
0xC0210002 STATUS_FVE_BAD_INFORMATION
0xC0210003 STATUS_FVE_TOO_SMALL
0xC0210004 STATUS_FVE_FAILED_WRONG_FS
0xC0210005 STATUS_FVE_BAD_PARTITION_SIZE
0xC0210006 STATUS_FVE_FS_NOT_EXTENDED
0xC0210007 STATUS_FVE_FS_MOUNTED
0xC0210008 STATUS_FVE_NO_LICENSE
0xC0210009 STATUS_FVE_ACTION_NOT_ALLOWED
0xC021000A STATUS_FVE_BAD_DATA
0xC021000B STATUS_FVE_VOLUME_NOT_BOUND
0xC021000C STATUS_FVE_NOT_DATA_VOLUME
0xC021000D STATUS_FVE_CONV_READ_ERROR
0xC021000E STATUS_FVE_CONV_WRITE_ERROR
0xC021000F STATUS_FVE_OVERLAPPED_UPDATE
0xC0210010 STATUS_FVE_FAILED_SECTOR_SIZE
0xC0210011 STATUS_FVE_FAILED_AUTHENTICATION
0xC0210012 STATUS_FVE_NOT_OS_VOLUME
0xC0210013 STATUS_FVE_KEYFILE_NOT_FOUND
0xC0210014 STATUS_FVE_KEYFILE_INVALID
0xC0210015 STATUS_FVE_KEYFILE_NO_VMK
0xC0210016 STATUS_FVE_TPM_DISABLED
0xC0210017 STATUS_FVE_TPM_SRK_AUTH_NOT_ZERO
0xC0210018 STATUS_FVE_TPM_INVALID_PCR
0xC0210019 STATUS_FVE_TPM_NO_VMK
0xC021001A STATUS_FVE_PIN_INVALID
0xC021001B STATUS_FVE_AUTH_INVALID_APPLICATION
0xC021001C STATUS_FVE_AUTH_INVALID_CONFIG
0xC021001D STATUS_FVE_DEBUGGER_ENABLED
0xC021001E STATUS_FVE_DRY_RUN_FAILED
0xC021001F STATUS_FVE_BAD_METADATA_POINTER
0xC0210020 STATUS_FVE_OLD_METADATA_COPY
0xC0210021 STATUS_FVE_REBOOT_REQUIRED
0xC0210022 STATUS_FVE_RAW_ACCESS
0xC0210023 STATUS_FVE_RAW_BLOCKED
0xC0210024 STATUS_FVE_NO_AUTOUNLOCK_MASTER_KEY
0xC0210025 STATUS_FVE_MOR_FAILED
0xC0210026 STATUS_FVE_NO_FEATURE_LICENSE
0xC0210027 STATUS_FVE_POLICY_USER_DISABLE_RDV_NOT_ALLOWED
0xC0210028 STATUS_FVE_CONV_RECOVERY_FAILED
0xC0210029 STATUS_FVE_VIRTUALIZED_SPACE_TOO_BIG
0xC021002A STATUS_FVE_INVALID_DATUM_TYPE
0xC0210030 STATUS_FVE_VOLUME_TOO_SMALL
0xC0210031 STATUS_FVE_ENH_PIN_INVALID
0xC0210032 STATUS_FVE_FULL_ENCRYPTION_NOT_ALLOWED_ON_TP_STORAGE
0xC0210033 STATUS_FVE_WIPE_NOT_ALLOWED_ON_TP_STORAGE
0xC0210034 STATUS_FVE_NOT_ALLOWED_ON_CSV_STACK
0xC0210035 STATUS_FVE_NOT_ALLOWED_ON_CLUSTER
0xC0210036 STATUS_FVE_NOT_ALLOWED_TO_UPGRADE_WHILE_CONVERTING
0xC0210037 STATUS_FVE_WIPE_CANCEL_NOT_APPLICABLE
0xC0210038 STATUS_FVE_EDRIVE_DRY_RUN_FAILED
0xC0210039 STATUS_FVE_SECUREBOOT_DISABLED
0xC021003A STATUS_FVE_SECUREBOOT_CONFIG_CHANGE
0xC021003B STATUS_FVE_DEVICE_LOCKEDOUT
0xC021003C STATUS_FVE_VOLUME_EXTEND_PREVENTS_EOW_DECRYPT
0xC021003D STATUS_FVE_NOT_DE_VOLUME
0xC021003E STATUS_FVE_PROTECTION_DISABLED
0xC021003F STATUS_FVE_PROTECTION_CANNOT_BE_DISABLED
0xC0210040 STATUS_FVE_OSV_KSR_NOT_ALLOWED
0xC0220001 STATUS_FWP_CALLOUT_NOT_FOUND
0xC0220002 STATUS_FWP_CONDITION_NOT_FOUND
0xC0220003 STATUS_FWP_FILTER_NOT_FOUND
0xC0220004 STATUS_FWP_LAYER_NOT_FOUND
0xC0220005 STATUS_FWP_PROVIDER_NOT_FOUND
0xC0220006 STATUS_FWP_PROVIDER_CONTEXT_NOT_FOUND
0xC0220007 STATUS_FWP_SUBLAYER_NOT_FOUND
0xC0220008 STATUS_FWP_NOT_FOUND
0xC0220009 STATUS_FWP_ALREADY_EXISTS
0xC022000A STATUS_FWP_IN_USE
0xC022000B STATUS_FWP_DYNAMIC_SESSION_IN_PROGRESS
0xC022000C STATUS_FWP_WRONG_SESSION
0xC022000D STATUS_FWP_NO_TXN_IN_PROGRESS
0xC022000E STATUS_FWP_TXN_IN_PROGRESS
0xC022000F STATUS_FWP_TXN_ABORTED
0xC0220010 STATUS_FWP_SESSION_ABORTED
0xC0220011 STATUS_FWP_INCOMPATIBLE_TXN
0xC0220012 STATUS_FWP_TIMEOUT
0xC0220013 STATUS_FWP_NET_EVENTS_DISABLED
0xC0220014 STATUS_FWP_INCOMPATIBLE_LAYER
0xC0220015 STATUS_FWP_KM_CLIENTS_ONLY
0xC0220016 STATUS_FWP_LIFETIME_MISMATCH
0xC0220017 STATUS_FWP_BUILTIN_OBJECT
0xC0220018 STATUS_FWP_TOO_MANY_CALLOUTS
0xC0220019 STATUS_FWP_NOTIFICATION_DROPPED
0xC022001A STATUS_FWP_TRAFFIC_MISMATCH
0xC022001B STATUS_FWP_INCOMPATIBLE_SA_STATE
0xC022001C STATUS_FWP_NULL_POINTER
0xC022001D STATUS_FWP_INVALID_ENUMERATOR
0xC022001E STATUS_FWP_INVALID_FLAGS
0xC022001F STATUS_FWP_INVALID_NET_MASK
0xC0220020 STATUS_FWP_INVALID_RANGE
0xC0220021 STATUS_FWP_INVALID_INTERVAL
0xC0220022 STATUS_FWP_ZERO_LENGTH_ARRAY
0xC0220023 STATUS_FWP_NULL_DISPLAY_NAME
0xC0220024 STATUS_FWP_INVALID_ACTION_TYPE
0xC0220025 STATUS_FWP_INVALID_WEIGHT
0xC0220026 STATUS_FWP_MATCH_TYPE_MISMATCH
0xC0220027 STATUS_FWP_TYPE_MISMATCH
0xC0220028 STATUS_FWP_OUT_OF_BOUNDS
0xC0220029 STATUS_FWP_RESERVED
0xC022002A STATUS_FWP_DUPLICATE_CONDITION
0xC022002B STATUS_FWP_DUPLICATE_KEYMOD
0xC022002C STATUS_FWP_ACTION_INCOMPATIBLE_WITH_LAYER
0xC022002D STATUS_FWP_ACTION_INCOMPATIBLE_WITH_SUBLAYER
0xC022002E STATUS_FWP_CONTEXT_INCOMPATIBLE_WITH_LAYER
0xC022002F STATUS_FWP_CONTEXT_INCOMPATIBLE_WITH_CALLOUT
0xC0220030 STATUS_FWP_INCOMPATIBLE_AUTH_METHOD
0xC0220031 STATUS_FWP_INCOMPATIBLE_DH_GROUP
0xC0220032 STATUS_FWP_EM_NOT_SUPPORTED
0xC0220033 STATUS_FWP_NEVER_MATCH
0xC0220034 STATUS_FWP_PROVIDER_CONTEXT_MISMATCH
0xC0220035 STATUS_FWP_INVALID_PARAMETER
0xC0220036 STATUS_FWP_TOO_MANY_SUBLAYERS
0xC0220037 STATUS_FWP_CALLOUT_NOTIFICATION_FAILED
0xC0220038 STATUS_FWP_INVALID_AUTH_TRANSFORM
0xC0220039 STATUS_FWP_INVALID_CIPHER_TRANSFORM
0xC022003A STATUS_FWP_INCOMPATIBLE_CIPHER_TRANSFORM
0xC022003B STATUS_FWP_INVALID_TRANSFORM_COMBINATION
0xC022003C STATUS_FWP_DUPLICATE_AUTH_METHOD
0xC022003D STATUS_FWP_INVALID_TUNNEL_ENDPOINT
0xC022003E STATUS_FWP_L2_DRIVER_NOT_READY
0xC022003F STATUS_FWP_KEY_DICTATOR_ALREADY_REGISTERED
0xC0220040 STATUS_FWP_KEY_DICTATION_INVALID_KEYING_MATERIAL
0xC0220041 STATUS_FWP_CONNECTIONS_DISABLED
0xC0220042 STATUS_FWP_INVALID_DNS_NAME
0xC0220043 STATUS_FWP_STILL_ON
0xC0220044 STATUS_FWP_IKEEXT_NOT_RUNNING
0xC0220100 STATUS_FWP_TCPIP_NOT_READY
0xC0220101 STATUS_FWP_INJECT_HANDLE_CLOSING
0xC0220102 STATUS_FWP_INJECT_HANDLE_STALE
0xC0220103 STATUS_FWP_CANNOT_PEND
0xC0220104 STATUS_FWP_DROP_NOICMP
0xC0230002 STATUS_NDIS_CLOSING
0xC0230004 STATUS_NDIS_BAD_VERSION
0xC0230005 STATUS_NDIS_BAD_CHARACTERISTICS
0xC0230006 STATUS_NDIS_ADAPTER_NOT_FOUND
0xC0230007 STATUS_NDIS_OPEN_FAILED
0xC0230008 STATUS_NDIS_DEVICE_FAILED
0xC0230009 STATUS_NDIS_MULTICAST_FULL
0xC023000A STATUS_NDIS_MULTICAST_EXISTS
0xC023000B STATUS_NDIS_MULTICAST_NOT_FOUND
0xC023000C STATUS_NDIS_REQUEST_ABORTED
0xC023000D STATUS_NDIS_RESET_IN_PROGRESS
0xC023000F STATUS_NDIS_INVALID_PACKET
0xC0230010 STATUS_NDIS_INVALID_DEVICE_REQUEST
0xC0230011 STATUS_NDIS_ADAPTER_NOT_READY
0xC0230014 STATUS_NDIS_INVALID_LENGTH
0xC0230015 STATUS_NDIS_INVALID_DATA
0xC0230016 STATUS_NDIS_BUFFER_TOO_SHORT
0xC0230017 STATUS_NDIS_INVALID_OID
0xC0230018 STATUS_NDIS_ADAPTER_REMOVED
0xC0230019 STATUS_NDIS_UNSUPPORTED_MEDIA
0xC023001A STATUS_NDIS_GROUP_ADDRESS_IN_USE
0xC023001B STATUS_NDIS_FILE_NOT_FOUND
0xC023001C STATUS_NDIS_ERROR_READING_FILE
0xC023001D STATUS_NDIS_ALREADY_MAPPED
0xC023001E STATUS_NDIS_RESOURCE_CONFLICT
0xC023001F STATUS_NDIS_MEDIA_DISCONNECTED
0xC0230022 STATUS_NDIS_INVALID_ADDRESS
0xC023002A STATUS_NDIS_PAUSED
0xC023002B STATUS_NDIS_INTERFACE_NOT_FOUND
0xC023002C STATUS_NDIS_UNSUPPORTED_REVISION
0xC023002D STATUS_NDIS_INVALID_PORT
0xC023002E STATUS_NDIS_INVALID_PORT_STATE
0xC023002F STATUS_NDIS_LOW_POWER_STATE
0xC0230030 STATUS_NDIS_REINIT_REQUIRED
0xC02300BB STATUS_NDIS_NOT_SUPPORTED
0xC023100F STATUS_NDIS_OFFLOAD_POLICY
0xC0231012 STATUS_NDIS_OFFLOAD_CONNECTION_REJECTED
0xC0231013 STATUS_NDIS_OFFLOAD_PATH_REJECTED
0xC0232000 STATUS_NDIS_DOT11_AUTO_CONFIG_ENABLED
0xC0232001 STATUS_NDIS_DOT11_MEDIA_IN_USE
0xC0232002 STATUS_NDIS_DOT11_POWER_STATE_INVALID
0xC0232003 STATUS_NDIS_PM_WOL_PATTERN_LIST_FULL
0xC0232004 STATUS_NDIS_PM_PROTOCOL_OFFLOAD_LIST_FULL
0xC0232005 STATUS_NDIS_DOT11_AP_CHANNEL_CURRENTLY_NOT_AVAILABLE
0xC0232006 STATUS_NDIS_DOT11_AP_BAND_CURRENTLY_NOT_AVAILABLE
0xC0232007 STATUS_NDIS_DOT11_AP_CHANNEL_NOT_ALLOWED
0xC0232008 STATUS_NDIS_DOT11_AP_BAND_NOT_ALLOWED
0xC0290000 STATUS_TPM_ERROR_MASK
0xC0290001 STATUS_TPM_AUTHFAIL
0xC0290002 STATUS_TPM_BADINDEX
0xC0290003 STATUS_TPM_BAD_PARAMETER
0xC0290004 STATUS_TPM_AUDITFAILURE
0xC0290005 STATUS_TPM_CLEAR_DISABLED
0xC0290006 STATUS_TPM_DEACTIVATED
0xC0290007 STATUS_TPM_DISABLED
0xC0290008 STATUS_TPM_DISABLED_CMD
0xC0290009 STATUS_TPM_FAIL
0xC029000A STATUS_TPM_BAD_ORDINAL
0xC029000B STATUS_TPM_INSTALL_DISABLED
0xC029000C STATUS_TPM_INVALID_KEYHANDLE
0xC029000D STATUS_TPM_KEYNOTFOUND
0xC029000E STATUS_TPM_INAPPROPRIATE_ENC
0xC029000F STATUS_TPM_MIGRATEFAIL
0xC0290010 STATUS_TPM_INVALID_PCR_INFO
0xC0290011 STATUS_TPM_NOSPACE
0xC0290012 STATUS_TPM_NOSRK
0xC0290013 STATUS_TPM_NOTSEALED_BLOB
0xC0290014 STATUS_TPM_OWNER_SET
0xC0290015 STATUS_TPM_RESOURCES
0xC0290016 STATUS_TPM_SHORTRANDOM
0xC0290017 STATUS_TPM_SIZE
0xC0290018 STATUS_TPM_WRONGPCRVAL
0xC0290019 STATUS_TPM_BAD_PARAM_SIZE
0xC029001A STATUS_TPM_SHA_THREAD
0xC029001B STATUS_TPM_SHA_ERROR
0xC029001C STATUS_TPM_FAILEDSELFTEST
0xC029001D STATUS_TPM_AUTH2FAIL
0xC029001E STATUS_TPM_BADTAG
0xC029001F STATUS_TPM_IOERROR
0xC0290020 STATUS_TPM_ENCRYPT_ERROR
0xC0290021 STATUS_TPM_DECRYPT_ERROR
0xC0290022 STATUS_TPM_INVALID_AUTHHANDLE
0xC0290023 STATUS_TPM_NO_ENDORSEMENT
0xC0290024 STATUS_TPM_INVALID_KEYUSAGE
0xC0290025 STATUS_TPM_WRONG_ENTITYTYPE
0xC0290026 STATUS_TPM_INVALID_POSTINIT
0xC0290027 STATUS_TPM_INAPPROPRIATE_SIG
0xC0290028 STATUS_TPM_BAD_KEY_PROPERTY
0xC0290029 STATUS_TPM_BAD_MIGRATION
0xC029002A STATUS_TPM_BAD_SCHEME
0xC029002B STATUS_TPM_BAD_DATASIZE
0xC029002C STATUS_TPM_BAD_MODE
0xC029002D STATUS_TPM_BAD_PRESENCE
0xC029002E STATUS_TPM_BAD_VERSION
0xC029002F STATUS_TPM_NO_WRAP_TRANSPORT
0xC0290030 STATUS_TPM_AUDITFAIL_UNSUCCESSFUL
0xC0290031 STATUS_TPM_AUDITFAIL_SUCCESSFUL
0xC0290032 STATUS_TPM_NOTRESETABLE
0xC0290033 STATUS_TPM_NOTLOCAL
0xC0290034 STATUS_TPM_BAD_TYPE
0xC0290035 STATUS_TPM_INVALID_RESOURCE
0xC0290036 STATUS_TPM_NOTFIPS
0xC0290037 STATUS_TPM_INVALID_FAMILY
0xC0290038 STATUS_TPM_NO_NV_PERMISSION
0xC0290039 STATUS_TPM_REQUIRES_SIGN
0xC029003A STATUS_TPM_KEY_NOTSUPPORTED
0xC029003B STATUS_TPM_AUTH_CONFLICT
0xC029003C STATUS_TPM_AREA_LOCKED
0xC029003D STATUS_TPM_BAD_LOCALITY
0xC029003E STATUS_TPM_READ_ONLY
0xC029003F STATUS_TPM_PER_NOWRITE
0xC0290040 STATUS_TPM_FAMILYCOUNT
0xC0290041 STATUS_TPM_WRITE_LOCKED
0xC0290042 STATUS_TPM_BAD_ATTRIBUTES
0xC0290043 STATUS_TPM_INVALID_STRUCTURE
0xC0290044 STATUS_TPM_KEY_OWNER_CONTROL
0xC0290045 STATUS_TPM_BAD_COUNTER
0xC0290046 STATUS_TPM_NOT_FULLWRITE
0xC0290047 STATUS_TPM_CONTEXT_GAP
0xC0290048 STATUS_TPM_MAXNVWRITES
0xC0290049 STATUS_TPM_NOOPERATOR
0xC029004A STATUS_TPM_RESOURCEMISSING
0xC029004B STATUS_TPM_DELEGATE_LOCK
0xC029004C STATUS_TPM_DELEGATE_FAMILY
0xC029004D STATUS_TPM_DELEGATE_ADMIN
0xC029004E STATUS_TPM_TRANSPORT_NOTEXCLUSIVE
0xC029004F STATUS_TPM_OWNER_CONTROL
0xC0290050 STATUS_TPM_DAA_RESOURCES
0xC0290051 STATUS_TPM_DAA_INPUT_DATA0
0xC0290052 STATUS_TPM_DAA_INPUT_DATA1
0xC0290053 STATUS_TPM_DAA_ISSUER_SETTINGS
0xC0290054 STATUS_TPM_DAA_TPM_SETTINGS
0xC0290055 STATUS_TPM_DAA_STAGE
0xC0290056 STATUS_TPM_DAA_ISSUER_VALIDITY
0xC0290057 STATUS_TPM_DAA_WRONG_W
0xC0290058 STATUS_TPM_BAD_HANDLE
0xC0290059 STATUS_TPM_BAD_DELEGATE
0xC029005A STATUS_TPM_BADCONTEXT
0xC029005B STATUS_TPM_TOOMANYCONTEXTS
0xC029005C STATUS_TPM_MA_TICKET_SIGNATURE
0xC029005D STATUS_TPM_MA_DESTINATION
0xC029005E STATUS_TPM_MA_SOURCE
0xC029005F STATUS_TPM_MA_AUTHORITY
0xC0290061 STATUS_TPM_PERMANENTEK
0xC0290062 STATUS_TPM_BAD_SIGNATURE
0xC0290063 STATUS_TPM_NOCONTEXTSPACE
0xC0290400 STATUS_TPM_COMMAND_BLOCKED
0xC0290401 STATUS_TPM_INVALID_HANDLE
0xC0290402 STATUS_TPM_DUPLICATE_VHANDLE
0xC0290403 STATUS_TPM_EMBEDDED_COMMAND_BLOCKED
0xC0290404 STATUS_TPM_EMBEDDED_COMMAND_UNSUPPORTED
0xC0290800 STATUS_TPM_RETRY
0xC0290801 STATUS_TPM_NEEDS_SELFTEST
0xC0290802 STATUS_TPM_DOING_SELFTEST
0xC0290803 STATUS_TPM_DEFEND_LOCK_RUNNING
0xC0291001 STATUS_TPM_COMMAND_CANCELED
0xC0291002 STATUS_TPM_TOO_MANY_CONTEXTS
0xC0291003 STATUS_TPM_NOT_FOUND
0xC0291004 STATUS_TPM_ACCESS_DENIED
0xC0291005 STATUS_TPM_INSUFFICIENT_BUFFER
0xC0291006 STATUS_TPM_PPI_FUNCTION_UNSUPPORTED
0xC0292000 STATUS_PCP_ERROR_MASK
0xC0292001 STATUS_PCP_DEVICE_NOT_READY
0xC0292002 STATUS_PCP_INVALID_HANDLE
0xC0292003 STATUS_PCP_INVALID_PARAMETER
0xC0292004 STATUS_PCP_FLAG_NOT_SUPPORTED
0xC0292005 STATUS_PCP_NOT_SUPPORTED
0xC0292006 STATUS_PCP_BUFFER_TOO_SMALL
0xC0292007 STATUS_PCP_INTERNAL_ERROR
0xC0292008 STATUS_PCP_AUTHENTICATION_FAILED
0xC0292009 STATUS_PCP_AUTHENTICATION_IGNORED
0xC029200A STATUS_PCP_POLICY_NOT_FOUND
0xC029200B STATUS_PCP_PROFILE_NOT_FOUND
0xC029200C STATUS_PCP_VALIDATION_FAILED
0xC029200D STATUS_PCP_DEVICE_NOT_FOUND
0xC029200E STATUS_PCP_WRONG_PARENT
0xC029200F STATUS_PCP_KEY_NOT_LOADED
0xC0292010 STATUS_PCP_NO_KEY_CERTIFICATION
0xC0292011 STATUS_PCP_KEY_NOT_FINALIZED
0xC0292012 STATUS_PCP_ATTESTATION_CHALLENGE_NOT_SET
0xC0292013 STATUS_PCP_NOT_PCR_BOUND
0xC0292014 STATUS_PCP_KEY_ALREADY_FINALIZED
0xC0292015 STATUS_PCP_KEY_USAGE_POLICY_NOT_SUPPORTED
0xC0292016 STATUS_PCP_KEY_USAGE_POLICY_INVALID
0xC0292017 STATUS_PCP_SOFT_KEY_ERROR
0xC0292018 STATUS_PCP_KEY_NOT_AUTHENTICATED
0xC0292019 STATUS_PCP_KEY_NOT_AIK
0xC029201A STATUS_PCP_KEY_NOT_SIGNING_KEY
0xC029201B STATUS_PCP_LOCKED_OUT
0xC029201C STATUS_PCP_CLAIM_TYPE_NOT_SUPPORTED
0xC029201D STATUS_PCP_TPM_VERSION_NOT_SUPPORTED
0xC029201E STATUS_PCP_BUFFER_LENGTH_MISMATCH
0xC029201F STATUS_PCP_IFX_RSA_KEY_CREATION_BLOCKED
0xC0293002 STATUS_RTPM_NO_RESULT
0xC0293003 STATUS_RTPM_PCR_READ_INCOMPLETE
0xC0293004 STATUS_RTPM_INVALID_CONTEXT
0xC0293005 STATUS_RTPM_UNSUPPORTED_CMD
0xC0294000 STATUS_TPM_ZERO_EXHAUST_ENABLED
0xC0350002 STATUS_HV_INVALID_HYPERCALL_CODE
0xC0350003 STATUS_HV_INVALID_HYPERCALL_INPUT
0xC0350004 STATUS_HV_INVALID_ALIGNMENT
0xC0350005 STATUS_HV_INVALID_PARAMETER
0xC0350006 STATUS_HV_ACCESS_DENIED
0xC0350007 STATUS_HV_INVALID_PARTITION_STATE
0xC0350008 STATUS_HV_OPERATION_DENIED
0xC0350009 STATUS_HV_UNKNOWN_PROPERTY
0xC035000A STATUS_HV_PROPERTY_VALUE_OUT_OF_RANGE
0xC035000B STATUS_HV_INSUFFICIENT_MEMORY
0xC035000C STATUS_HV_PARTITION_TOO_DEEP
0xC035000D STATUS_HV_INVALID_PARTITION_ID
0xC035000E STATUS_HV_INVALID_VP_INDEX
0xC0350011 STATUS_HV_INVALID_PORT_ID
0xC0350012 STATUS_HV_INVALID_CONNECTION_ID
0xC0350013 STATUS_HV_INSUFFICIENT_BUFFERS
0xC0350014 STATUS_HV_NOT_ACKNOWLEDGED
0xC0350015 STATUS_HV_INVALID_VP_STATE
0xC0350016 STATUS_HV_ACKNOWLEDGED
0xC0350017 STATUS_HV_INVALID_SAVE_RESTORE_STATE
0xC0350018 STATUS_HV_INVALID_SYNIC_STATE
0xC0350019 STATUS_HV_OBJECT_IN_USE
0xC035001A STATUS_HV_INVALID_PROXIMITY_DOMAIN_INFO
0xC035001B STATUS_HV_NO_DATA
0xC035001C STATUS_HV_INACTIVE
0xC035001D STATUS_HV_NO_RESOURCES
0xC035001E STATUS_HV_FEATURE_UNAVAILABLE
0xC0350033 STATUS_HV_INSUFFICIENT_BUFFER
0xC0350038 STATUS_HV_INSUFFICIENT_DEVICE_DOMAINS
0xC035003C STATUS_HV_CPUID_FEATURE_VALIDATION_ERROR
0xC035003D STATUS_HV_CPUID_XSAVE_FEATURE_VALIDATION_ERROR
0xC035003E STATUS_HV_PROCESSOR_STARTUP_TIMEOUT
0xC035003F STATUS_HV_SMX_ENABLED
0xC0350041 STATUS_HV_INVALID_LP_INDEX
0xC0350050 STATUS_HV_INVALID_REGISTER_VALUE
0xC0350051 STATUS_HV_INVALID_VTL_STATE
0xC0350055 STATUS_HV_NX_NOT_DETECTED
0xC0350057 STATUS_HV_INVALID_DEVICE_ID
0xC0350058 STATUS_HV_INVALID_DEVICE_STATE
0xC0350060 STATUS_HV_PAGE_REQUEST_INVALID
0xC035006F STATUS_HV_INVALID_CPU_GROUP_ID
0xC0350070 STATUS_HV_INVALID_CPU_GROUP_STATE
0xC0350071 STATUS_HV_OPERATION_FAILED
0xC0350072 STATUS_HV_NOT_ALLOWED_WITH_NESTED_VIRT_ACTIVE
0xC0351000 STATUS_HV_NOT_PRESENT
0xC0360001 STATUS_IPSEC_BAD_SPI
0xC0360002 STATUS_IPSEC_SA_LIFETIME_EXPIRED
0xC0360003 STATUS_IPSEC_WRONG_SA
0xC0360004 STATUS_IPSEC_REPLAY_CHECK_FAILED
0xC0360005 STATUS_IPSEC_INVALID_PACKET
0xC0360006 STATUS_IPSEC_INTEGRITY_CHECK_FAILED
0xC0360007 STATUS_IPSEC_CLEAR_TEXT_DROP
0xC0360008 STATUS_IPSEC_AUTH_FIREWALL_DROP
0xC0360009 STATUS_IPSEC_THROTTLE_DROP
0xC0368000 STATUS_IPSEC_DOSP_BLOCK
0xC0368001 STATUS_IPSEC_DOSP_RECEIVED_MULTICAST
0xC0368002 STATUS_IPSEC_DOSP_INVALID_PACKET
0xC0368003 STATUS_IPSEC_DOSP_STATE_LOOKUP_FAILED
0xC0368004 STATUS_IPSEC_DOSP_MAX_ENTRIES
0xC0368005 STATUS_IPSEC_DOSP_KEYMOD_NOT_ALLOWED
0xC0368006 STATUS_IPSEC_DOSP_MAX_PER_IP_RATELIMIT_QUEUES
0xC0370001 STATUS_VID_DUPLICATE_HANDLER
0xC0370002 STATUS_VID_TOO_MANY_HANDLERS
0xC0370003 STATUS_VID_QUEUE_FULL
0xC0370004 STATUS_VID_HANDLER_NOT_PRESENT
0xC0370005 STATUS_VID_INVALID_OBJECT_NAME
0xC0370006 STATUS_VID_PARTITION_NAME_TOO_LONG
0xC0370007 STATUS_VID_MESSAGE_QUEUE_NAME_TOO_LONG
0xC0370008 STATUS_VID_PARTITION_ALREADY_EXISTS
0xC0370009 STATUS_VID_PARTITION_DOES_NOT_EXIST
0xC037000A STATUS_VID_PARTITION_NAME_NOT_FOUND
0xC037000B STATUS_VID_MESSAGE_QUEUE_ALREADY_EXISTS
0xC037000C STATUS_VID_EXCEEDED_MBP_ENTRY_MAP_LIMIT
0xC037000D STATUS_VID_MB_STILL_REFERENCED
0xC037000E STATUS_VID_CHILD_GPA_PAGE_SET_CORRUPTED
0xC037000F STATUS_VID_INVALID_NUMA_SETTINGS
0xC0370010 STATUS_VID_INVALID_NUMA_NODE_INDEX
0xC0370011 STATUS_VID_NOTIFICATION_QUEUE_ALREADY_ASSOCIATED
0xC0370012 STATUS_VID_INVALID_MEMORY_BLOCK_HANDLE
0xC0370013 STATUS_VID_PAGE_RANGE_OVERFLOW
0xC0370014 STATUS_VID_INVALID_MESSAGE_QUEUE_HANDLE
0xC0370015 STATUS_VID_INVALID_GPA_RANGE_HANDLE
0xC0370016 STATUS_VID_NO_MEMORY_BLOCK_NOTIFICATION_QUEUE
0xC0370017 STATUS_VID_MEMORY_BLOCK_LOCK_COUNT_EXCEEDED
0xC0370018 STATUS_VID_INVALID_PPM_HANDLE
0xC0370019 STATUS_VID_MBPS_ARE_LOCKED
0xC037001A STATUS_VID_MESSAGE_QUEUE_CLOSED
0xC037001B STATUS_VID_VIRTUAL_PROCESSOR_LIMIT_EXCEEDED
0xC037001C STATUS_VID_STOP_PENDING
0xC037001D STATUS_VID_INVALID_PROCESSOR_STATE
0xC037001E STATUS_VID_EXCEEDED_KM_CONTEXT_COUNT_LIMIT
0xC037001F STATUS_VID_KM_INTERFACE_ALREADY_INITIALIZED
0xC0370020 STATUS_VID_MB_PROPERTY_ALREADY_SET_RESET
0xC0370021 STATUS_VID_MMIO_RANGE_DESTROYED
0xC0370022 STATUS_VID_INVALID_CHILD_GPA_PAGE_SET
0xC0370023 STATUS_VID_RESERVE_PAGE_SET_IS_BEING_USED
0xC0370024 STATUS_VID_RESERVE_PAGE_SET_TOO_SMALL
0xC0370025 STATUS_VID_MBP_ALREADY_LOCKED_USING_RESERVED_PAGE
0xC0370026 STATUS_VID_MBP_COUNT_EXCEEDED_LIMIT
0xC0370027 STATUS_VID_SAVED_STATE_CORRUPT
0xC0370028 STATUS_VID_SAVED_STATE_UNRECOGNIZED_ITEM
0xC0370029 STATUS_VID_SAVED_STATE_INCOMPATIBLE
0xC037002A STATUS_VID_VTL_ACCESS_DENIED
0xC0380001 STATUS_VOLMGR_DATABASE_FULL
0xC0380002 STATUS_VOLMGR_DISK_CONFIGURATION_CORRUPTED
0xC0380003 STATUS_VOLMGR_DISK_CONFIGURATION_NOT_IN_SYNC
0xC0380004 STATUS_VOLMGR_PACK_CONFIG_UPDATE_FAILED
0xC0380005 STATUS_VOLMGR_DISK_CONTAINS_NON_SIMPLE_VOLUME
0xC0380006 STATUS_VOLMGR_DISK_DUPLICATE
0xC0380007 STATUS_VOLMGR_DISK_DYNAMIC
0xC0380008 STATUS_VOLMGR_DISK_ID_INVALID
0xC0380009 STATUS_VOLMGR_DISK_INVALID
0xC038000A STATUS_VOLMGR_DISK_LAST_VOTER
0xC038000B STATUS_VOLMGR_DISK_LAYOUT_INVALID
0xC038000C STATUS_VOLMGR_DISK_LAYOUT_NON_BASIC_BETWEEN_BASIC_PARTITIONS
0xC038000D STATUS_VOLMGR_DISK_LAYOUT_NOT_CYLINDER_ALIGNED
0xC038000E STATUS_VOLMGR_DISK_LAYOUT_PARTITIONS_TOO_SMALL
0xC038000F STATUS_VOLMGR_DISK_LAYOUT_PRIMARY_BETWEEN_LOGICAL_PARTITIONS
0xC0380010 STATUS_VOLMGR_DISK_LAYOUT_TOO_MANY_PARTITIONS
0xC0380011 STATUS_VOLMGR_DISK_MISSING
0xC0380012 STATUS_VOLMGR_DISK_NOT_EMPTY
0xC0380013 STATUS_VOLMGR_DISK_NOT_ENOUGH_SPACE
0xC0380014 STATUS_VOLMGR_DISK_REVECTORING_FAILED
0xC0380015 STATUS_VOLMGR_DISK_SECTOR_SIZE_INVALID
0xC0380016 STATUS_VOLMGR_DISK_SET_NOT_CONTAINED
0xC0380017 STATUS_VOLMGR_DISK_USED_BY_MULTIPLE_MEMBERS
0xC0380018 STATUS_VOLMGR_DISK_USED_BY_MULTIPLE_PLEXES
0xC0380019 STATUS_VOLMGR_DYNAMIC_DISK_NOT_SUPPORTED
0xC038001A STATUS_VOLMGR_EXTENT_ALREADY_USED
0xC038001B STATUS_VOLMGR_EXTENT_NOT_CONTIGUOUS
0xC038001C STATUS_VOLMGR_EXTENT_NOT_IN_PUBLIC_REGION
0xC038001D STATUS_VOLMGR_EXTENT_NOT_SECTOR_ALIGNED
0xC038001E STATUS_VOLMGR_EXTENT_OVERLAPS_EBR_PARTITION
0xC038001F STATUS_VOLMGR_EXTENT_VOLUME_LENGTHS_DO_NOT_MATCH
0xC0380020 STATUS_VOLMGR_FAULT_TOLERANT_NOT_SUPPORTED
0xC0380021 STATUS_VOLMGR_INTERLEAVE_LENGTH_INVALID
0xC0380022 STATUS_VOLMGR_MAXIMUM_REGISTERED_USERS
0xC0380023 STATUS_VOLMGR_MEMBER_IN_SYNC
0xC0380024 STATUS_VOLMGR_MEMBER_INDEX_DUPLICATE
0xC0380025 STATUS_VOLMGR_MEMBER_INDEX_INVALID
0xC0380026 STATUS_VOLMGR_MEMBER_MISSING
0xC0380027 STATUS_VOLMGR_MEMBER_NOT_DETACHED
0xC0380028 STATUS_VOLMGR_MEMBER_REGENERATING
0xC0380029 STATUS_VOLMGR_ALL_DISKS_FAILED
0xC038002A STATUS_VOLMGR_NO_REGISTERED_USERS
0xC038002B STATUS_VOLMGR_NO_SUCH_USER
0xC038002C STATUS_VOLMGR_NOTIFICATION_RESET
0xC038002D STATUS_VOLMGR_NUMBER_OF_MEMBERS_INVALID
0xC038002E STATUS_VOLMGR_NUMBER_OF_PLEXES_INVALID
0xC038002F STATUS_VOLMGR_PACK_DUPLICATE
0xC0380030 STATUS_VOLMGR_PACK_ID_INVALID
0xC0380031 STATUS_VOLMGR_PACK_INVALID
0xC0380032 STATUS_VOLMGR_PACK_NAME_INVALID
0xC0380033 STATUS_VOLMGR_PACK_OFFLINE
0xC0380034 STATUS_VOLMGR_PACK_HAS_QUORUM
0xC0380035 STATUS_VOLMGR_PACK_WITHOUT_QUORUM
0xC0380036 STATUS_VOLMGR_PARTITION_STYLE_INVALID
0xC0380037 STATUS_VOLMGR_PARTITION_UPDATE_FAILED
0xC0380038 STATUS_VOLMGR_PLEX_IN_SYNC
0xC0380039 STATUS_VOLMGR_PLEX_INDEX_DUPLICATE
0xC038003A STATUS_VOLMGR_PLEX_INDEX_INVALID
0xC038003B STATUS_VOLMGR_PLEX_LAST_ACTIVE
0xC038003C STATUS_VOLMGR_PLEX_MISSING
0xC038003D STATUS_VOLMGR_PLEX_REGENERATING
0xC038003E STATUS_VOLMGR_PLEX_TYPE_INVALID
0xC038003F STATUS_VOLMGR_PLEX_NOT_RAID5
0xC0380040 STATUS_VOLMGR_PLEX_NOT_SIMPLE
0xC0380041 STATUS_VOLMGR_STRUCTURE_SIZE_INVALID
0xC0380042 STATUS_VOLMGR_TOO_MANY_NOTIFICATION_REQUESTS
0xC0380043 STATUS_VOLMGR_TRANSACTION_IN_PROGRESS
0xC0380044 STATUS_VOLMGR_UNEXPECTED_DISK_LAYOUT_CHANGE
0xC0380045 STATUS_VOLMGR_VOLUME_CONTAINS_MISSING_DISK
0xC0380046 STATUS_VOLMGR_VOLUME_ID_INVALID
0xC0380047 STATUS_VOLMGR_VOLUME_LENGTH_INVALID
0xC0380048 STATUS_VOLMGR_VOLUME_LENGTH_NOT_SECTOR_SIZE_MULTIPLE
0xC0380049 STATUS_VOLMGR_VOLUME_NOT_MIRRORED
0xC038004A STATUS_VOLMGR_VOLUME_NOT_RETAINED
0xC038004B STATUS_VOLMGR_VOLUME_OFFLINE
0xC038004C STATUS_VOLMGR_VOLUME_RETAINED
0xC038004D STATUS_VOLMGR_NUMBER_OF_EXTENTS_INVALID
0xC038004E STATUS_VOLMGR_DIFFERENT_SECTOR_SIZE
0xC038004F STATUS_VOLMGR_BAD_BOOT_DISK
0xC0380050 STATUS_VOLMGR_PACK_CONFIG_OFFLINE
0xC0380051 STATUS_VOLMGR_PACK_CONFIG_ONLINE
0xC0380052 STATUS_VOLMGR_NOT_PRIMARY_PACK
0xC0380053 STATUS_VOLMGR_PACK_LOG_UPDATE_FAILED
0xC0380054 STATUS_VOLMGR_NUMBER_OF_DISKS_IN_PLEX_INVALID
0xC0380055 STATUS_VOLMGR_NUMBER_OF_DISKS_IN_MEMBER_INVALID
0xC0380056 STATUS_VOLMGR_VOLUME_MIRRORED
0xC0380057 STATUS_VOLMGR_PLEX_NOT_SIMPLE_SPANNED
0xC0380058 STATUS_VOLMGR_NO_VALID_LOG_COPIES
0xC0380059 STATUS_VOLMGR_PRIMARY_PACK_PRESENT
0xC038005A STATUS_VOLMGR_NUMBER_OF_DISKS_INVALID
0xC038005B STATUS_VOLMGR_MIRROR_NOT_SUPPORTED
0xC038005C STATUS_VOLMGR_RAID5_NOT_SUPPORTED
0xC0390002 STATUS_BCD_TOO_MANY_ELEMENTS
0xC03A0001 STATUS_VHD_DRIVE_FOOTER_MISSING
0xC03A0002 STATUS_VHD_DRIVE_FOOTER_CHECKSUM_MISMATCH
0xC03A0003 STATUS_VHD_DRIVE_FOOTER_CORRUPT
0xC03A0004 STATUS_VHD_FORMAT_UNKNOWN
0xC03A0005 STATUS_VHD_FORMAT_UNSUPPORTED_VERSION
0xC03A0006 STATUS_VHD_SPARSE_HEADER_CHECKSUM_MISMATCH
0xC03A0007 STATUS_VHD_SPARSE_HEADER_UNSUPPORTED_VERSION
0xC03A0008 STATUS_VHD_SPARSE_HEADER_CORRUPT
0xC03A0009 STATUS_VHD_BLOCK_ALLOCATION_FAILURE
0xC03A000A STATUS_VHD_BLOCK_ALLOCATION_TABLE_CORRUPT
0xC03A000B STATUS_VHD_INVALID_BLOCK_SIZE
0xC03A000C STATUS_VHD_BITMAP_MISMATCH
0xC03A000D STATUS_VHD_PARENT_VHD_NOT_FOUND
0xC03A000E STATUS_VHD_CHILD_PARENT_ID_MISMATCH
0xC03A000F STATUS_VHD_CHILD_PARENT_TIMESTAMP_MISMATCH
0xC03A0010 STATUS_VHD_METADATA_READ_FAILURE
0xC03A0011 STATUS_VHD_METADATA_WRITE_FAILURE
0xC03A0012 STATUS_VHD_INVALID_SIZE
0xC03A0013 STATUS_VHD_INVALID_FILE_SIZE
0xC03A0014 STATUS_VIRTDISK_PROVIDER_NOT_FOUND
0xC03A0015 STATUS_VIRTDISK_NOT_VIRTUAL_DISK
0xC03A0016 STATUS_VHD_PARENT_VHD_ACCESS_DENIED
0xC03A0017 STATUS_VHD_CHILD_PARENT_SIZE_MISMATCH
0xC03A0018 STATUS_VHD_DIFFERENCING_CHAIN_CYCLE_DETECTED
0xC03A0019 STATUS_VHD_DIFFERENCING_CHAIN_ERROR_IN_PARENT
0xC03A001A STATUS_VIRTUAL_DISK_LIMITATION
0xC03A001B STATUS_VHD_INVALID_TYPE
0xC03A001C STATUS_VHD_INVALID_STATE
0xC03A001D STATUS_VIRTDISK_UNSUPPORTED_DISK_SECTOR_SIZE
0xC03A001E STATUS_VIRTDISK_DISK_ALREADY_OWNED
0xC03A001F STATUS_VIRTDISK_DISK_ONLINE_AND_WRITABLE
0xC03A0020 STATUS_CTLOG_TRACKING_NOT_INITIALIZED
0xC03A0021 STATUS_CTLOG_LOGFILE_SIZE_EXCEEDED_MAXSIZE
0xC03A0022 STATUS_CTLOG_VHD_CHANGED_OFFLINE
0xC03A0023 STATUS_CTLOG_INVALID_TRACKING_STATE
0xC03A0024 STATUS_CTLOG_INCONSISTENT_TRACKING_FILE
0xC03A0028 STATUS_VHD_METADATA_FULL
0xC03A0029 STATUS_VHD_INVALID_CHANGE_TRACKING_ID
0xC03A002A STATUS_VHD_CHANGE_TRACKING_DISABLED
0xC03A0030 STATUS_VHD_MISSING_CHANGE_TRACKING_INFORMATION
0xC03A0031 STATUS_VHD_RESIZE_WOULD_TRUNCATE_DATA
0xC03A0032 STATUS_VHD_COULD_NOT_COMPUTE_MINIMUM_VIRTUAL_SIZE
0xC03A0033 STATUS_VHD_ALREADY_AT_OR_BELOW_MINIMUM_VIRTUAL_SIZE
0xC0400001 STATUS_RKF_KEY_NOT_FOUND
0xC0400002 STATUS_RKF_DUPLICATE_KEY
0xC0400003 STATUS_RKF_BLOB_FULL
0xC0400004 STATUS_RKF_STORE_FULL
0xC0400005 STATUS_RKF_FILE_BLOCKED
0xC0400006 STATUS_RKF_ACTIVE_KEY
0xC0410001 STATUS_RDBSS_RESTART_OPERATION
0xC0410002 STATUS_RDBSS_CONTINUE_OPERATION
0xC0410003 STATUS_RDBSS_POST_OPERATION
0xC0420001 STATUS_BTH_ATT_INVALID_HANDLE
0xC0420002 STATUS_BTH_ATT_READ_NOT_PERMITTED
0xC0420003 STATUS_BTH_ATT_WRITE_NOT_PERMITTED
0xC0420004 STATUS_BTH_ATT_INVALID_PDU
0xC0420005 STATUS_BTH_ATT_INSUFFICIENT_AUTHENTICATION
0xC0420006 STATUS_BTH_ATT_REQUEST_NOT_SUPPORTED
0xC0420007 STATUS_BTH_ATT_INVALID_OFFSET
0xC0420008 STATUS_BTH_ATT_INSUFFICIENT_AUTHORIZATION
0xC0420009 STATUS_BTH_ATT_PREPARE_QUEUE_FULL
0xC042000A STATUS_BTH_ATT_ATTRIBUTE_NOT_FOUND
0xC042000B STATUS_BTH_ATT_ATTRIBUTE_NOT_LONG
0xC042000C STATUS_BTH_ATT_INSUFFICIENT_ENCRYPTION_KEY_SIZE
0xC042000D STATUS_BTH_ATT_INVALID_ATTRIBUTE_VALUE_LENGTH
0xC042000E STATUS_BTH_ATT_UNLIKELY
0xC042000F STATUS_BTH_ATT_INSUFFICIENT_ENCRYPTION
0xC0420010 STATUS_BTH_ATT_UNSUPPORTED_GROUP_TYPE
0xC0420011 STATUS_BTH_ATT_INSUFFICIENT_RESOURCES
0xC0421000 STATUS_BTH_ATT_UNKNOWN_ERROR
0xC0430001 STATUS_SECUREBOOT_ROLLBACK_DETECTED
0xC0430002 STATUS_SECUREBOOT_POLICY_VIOLATION
0xC0430003 STATUS_SECUREBOOT_INVALID_POLICY
0xC0430004 STATUS_SECUREBOOT_POLICY_PUBLISHER_NOT_FOUND
0xC0430005 STATUS_SECUREBOOT_POLICY_NOT_SIGNED
0xC0430007 STATUS_SECUREBOOT_FILE_REPLACED
0xC0430008 STATUS_SECUREBOOT_POLICY_NOT_AUTHORIZED
0xC0430009 STATUS_SECUREBOOT_POLICY_UNKNOWN
0xC043000A STATUS_SECUREBOOT_POLICY_MISSING_ANTIROLLBACKVERSION
0xC043000B STATUS_SECUREBOOT_PLATFORM_ID_MISMATCH
0xC043000C STATUS_SECUREBOOT_POLICY_ROLLBACK_DETECTED
0xC043000D STATUS_SECUREBOOT_POLICY_UPGRADE_MISMATCH
0xC043000E STATUS_SECUREBOOT_REQUIRED_POLICY_FILE_MISSING
0xC043000F STATUS_SECUREBOOT_NOT_BASE_POLICY
0xC0430010 STATUS_SECUREBOOT_NOT_SUPPLEMENTAL_POLICY
0xC0440001 STATUS_AUDIO_ENGINE_NODE_NOT_FOUND
0xC0440002 STATUS_HDAUDIO_EMPTY_CONNECTION_LIST
0xC0440003 STATUS_HDAUDIO_CONNECTION_LIST_NOT_SUPPORTED
0xC0440004 STATUS_HDAUDIO_NO_LOGICAL_DEVICES_CREATED
0xC0440005 STATUS_HDAUDIO_NULL_LINKED_LIST_ENTRY
0xC0450000 STATUS_VSM_NOT_INITIALIZED
0xC0450001 STATUS_VSM_DMA_PROTECTION_NOT_IN_USE
0xC0500003 STATUS_VOLSNAP_BOOTFILE_NOT_VALID
0xC0500004 STATUS_VOLSNAP_ACTIVATION_TIMEOUT
0xC0510001 STATUS_IO_PREEMPTED
0xC05C0000 STATUS_SVHDX_ERROR_STORED
0xC05CFF00 STATUS_SVHDX_ERROR_NOT_AVAILABLE
0xC05CFF01 STATUS_SVHDX_UNIT_ATTENTION_AVAILABLE
0xC05CFF02 STATUS_SVHDX_UNIT_ATTENTION_CAPACITY_DATA_CHANGED
0xC05CFF03 STATUS_SVHDX_UNIT_ATTENTION_RESERVATIONS_PREEMPTED
0xC05CFF04 STATUS_SVHDX_UNIT_ATTENTION_RESERVATIONS_RELEASED
0xC05CFF05 STATUS_SVHDX_UNIT_ATTENTION_REGISTRATIONS_PREEMPTED
0xC05CFF06 STATUS_SVHDX_UNIT_ATTENTION_OPERATING_DEFINITION_CHANGED
0xC05CFF07 STATUS_SVHDX_RESERVATION_CONFLICT
0xC05CFF08 STATUS_SVHDX_WRONG_FILE_TYPE
0xC05CFF09 STATUS_SVHDX_VERSION_MISMATCH
0xC05CFF0A STATUS_VHD_SHARED
0xC05CFF0B STATUS_SVHDX_NO_INITIATOR
0xC05CFF0C STATUS_VHDSET_BACKING_STORAGE_NOT_FOUND
0xC05D0000 STATUS_SMB_NO_PREAUTH_INTEGRITY_HASH_OVERLAP
0xC05D0001 STATUS_SMB_BAD_CLUSTER_DIALECT
0xC05D0002 STATUS_SMB_GUEST_LOGON_BLOCKED
0xC0E70001 STATUS_SPACES_FAULT_DOMAIN_TYPE_INVALID
0xC0E70003 STATUS_SPACES_RESILIENCY_TYPE_INVALID
0xC0E70004 STATUS_SPACES_DRIVE_SECTOR_SIZE_INVALID
0xC0E70006 STATUS_SPACES_DRIVE_REDUNDANCY_INVALID
0xC0E70007 STATUS_SPACES_NUMBER_OF_DATA_COPIES_INVALID
0xC0E70009 STATUS_SPACES_INTERLEAVE_LENGTH_INVALID
0xC0E7000A STATUS_SPACES_NUMBER_OF_COLUMNS_INVALID
0xC0E7000B STATUS_SPACES_NOT_ENOUGH_DRIVES
0xC0E7000C STATUS_SPACES_EXTENDED_ERROR
0xC0E7000D STATUS_SPACES_PROVISIONING_TYPE_INVALID
0xC0E7000E STATUS_SPACES_ALLOCATION_SIZE_INVALID
0xC0E7000F STATUS_SPACES_ENCLOSURE_AWARE_INVALID
0xC0E70010 STATUS_SPACES_WRITE_CACHE_SIZE_INVALID
0xC0E70011 STATUS_SPACES_NUMBER_OF_GROUPS_INVALID
0xC0E70012 STATUS_SPACES_DRIVE_OPERATIONAL_STATE_INVALID
0xC0E70013 STATUS_SPACES_UPDATE_COLUMN_STATE
0xC0E70014 STATUS_SPACES_MAP_REQUIRED
0xC0E70015 STATUS_SPACES_UNSUPPORTED_VERSION
0xC0E70016 STATUS_SPACES_CORRUPT_METADATA
0xC0E70017 STATUS_SPACES_DRT_FULL
0xC0E70018 STATUS_SPACES_INCONSISTENCY
0xC0E70019 STATUS_SPACES_LOG_NOT_READY
0xC0E7001A STATUS_SPACES_NO_REDUNDANCY
0xC0E7001B STATUS_SPACES_DRIVE_NOT_READY
0xC0E7001C STATUS_SPACES_DRIVE_SPLIT
0xC0E7001D STATUS_SPACES_DRIVE_LOST_DATA
0xC0E80000 STATUS_SECCORE_INVALID_COMMAND
0xC0E90001 STATUS_SYSTEM_INTEGRITY_ROLLBACK_DETECTED
0xC0E90002 STATUS_SYSTEM_INTEGRITY_POLICY_VIOLATION
0xC0E90003 STATUS_SYSTEM_INTEGRITY_INVALID_POLICY
0xC0E90004 STATUS_SYSTEM_INTEGRITY_POLICY_NOT_SIGNED
0xC0EA0001 STATUS_NO_APPLICABLE_APP_LICENSES_FOUND
0xC0EA0002 STATUS_CLIP_LICENSE_NOT_FOUND
0xC0EA0003 STATUS_CLIP_DEVICE_LICENSE_MISSING
0xC0EA0004 STATUS_CLIP_LICENSE_INVALID_SIGNATURE
0xC0EA0005 STATUS_CLIP_KEYHOLDER_LICENSE_MISSING_OR_INVALID
0xC0EA0006 STATUS_CLIP_LICENSE_EXPIRED
0xC0EA0007 STATUS_CLIP_LICENSE_SIGNED_BY_UNKNOWN_SOURCE
0xC0EA0008 STATUS_CLIP_LICENSE_NOT_SIGNED
0xC0EA0009 STATUS_CLIP_LICENSE_HARDWARE_ID_OUT_OF_TOLERANCE
0xC0EA000A STATUS_CLIP_LICENSE_DEVICE_ID_MISMATCH
0xC0EB0001 STATUS_PLATFORM_MANIFEST_NOT_AUTHORIZED
0xC0EB0002 STATUS_PLATFORM_MANIFEST_INVALID
0xC0EB0003 STATUS_PLATFORM_MANIFEST_FILE_NOT_AUTHORIZED
0xC0EB0004 STATUS_PLATFORM_MANIFEST_CATALOG_NOT_AUTHORIZED
0xC0EB0005 STATUS_PLATFORM_MANIFEST_BINARY_ID_NOT_FOUND
0xC0EB0006 STATUS_PLATFORM_MANIFEST_NOT_ACTIVE
0xC0EB0007 STATUS_PLATFORM_MANIFEST_NOT_SIGNED |
Text | x64dbg-development/bin/winconstants.txt | 0x0000 WM_NULL
0x0001 WM_CREATE
0x0002 WM_DESTROY
0x0003 WM_MOVE
0x0005 WM_SIZE
0x0006 WM_ACTIVATE
0x0007 WM_SETFOCUS
0x0008 WM_KILLFOCUS
0x000A WM_ENABLE
0x000B WM_SETREDRAW
0x000C WM_SETTEXT
0x000D WM_GETTEXT
0x000E WM_GETTEXTLENGTH
0x000F WM_PAINT
0x0010 WM_CLOSE
0x0011 WM_QUERYENDSESSION
0x0012 WM_QUIT
0x0013 WM_QUERYOPEN
0x0014 WM_ERASEBKGND
0x0015 WM_SYSCOLORCHANGE
0x0016 WM_ENDSESSION
0x0018 WM_SHOWWINDOW
0x0019 WM_CTLCOLOR
0x001A WM_SETTINGCHANGE
0x001A WM_WININICHANGE
0x001B WM_DEVMODECHANGE
0x001C WM_ACTIVATEAPP
0x001D WM_FONTCHANGE
0x001E WM_TIMECHANGE
0x001F WM_CANCELMODE
0x0020 WM_SETCURSOR
0x0021 WM_MOUSEACTIVATE
0x0022 WM_CHILDACTIVATE
0x0023 WM_QUEUESYNC
0x0024 WM_GETMINMAXINFO
0x0026 WM_PAINTICON
0x0027 WM_ICONERASEBKGND
0x0028 WM_NEXTDLGCTL
0x002A WM_SPOOLERSTATUS
0x002B WM_DRAWITEM
0x002C WM_MEASUREITEM
0x002D WM_DELETEITEM
0x002E WM_VKEYTOITEM
0x002F WM_CHARTOITEM
0x0030 WM_SETFONT
0x0031 WM_GETFONT
0x0032 WM_SETHOTKEY
0x0033 WM_GETHOTKEY
0x0037 WM_QUERYDRAGICON
0x0039 WM_COMPAREITEM
0x003D WM_GETOBJECT
0x0041 WM_COMPACTING
0x0044 WM_COMMNOTIFY
0x0046 WM_WINDOWPOSCHANGING
0x0047 WM_WINDOWPOSCHANGED
0x0048 WM_POWER
0x0049 WM_COPYGLOBALDATA
0x004A WM_COPYDATA
0x004B WM_CANCELJOURNAL
0x004E WM_NOTIFY
0x0050 WM_INPUTLANGCHANGEREQUEST
0x0051 WM_INPUTLANGCHANGE
0x0052 WM_TCARD
0x0053 WM_HELP
0x0054 WM_USERCHANGED
0x0055 WM_NOTIFYFORMAT
0x007B WM_CONTEXTMENU
0x007C WM_STYLECHANGING
0x007D WM_STYLECHANGED
0x007E WM_DISPLAYCHANGE
0x007F WM_GETICON
0x0080 WM_SETICON
0x0081 WM_NCCREATE
0x0082 WM_NCDESTROY
0x0083 WM_NCCALCSIZE
0x0084 WM_NCHITTEST
0x0085 WM_NCPAINT
0x0086 WM_NCACTIVATE
0x0087 WM_GETDLGCODE
0x0088 WM_SYNCPAINT
0x00A0 WM_NCMOUSEMOVE
0x00A1 WM_NCLBUTTONDOWN
0x00A2 WM_NCLBUTTONUP
0x00A3 WM_NCLBUTTONDBLCLK
0x00A4 WM_NCRBUTTONDOWN
0x00A5 WM_NCRBUTTONUP
0x00A6 WM_NCRBUTTONDBLCLK
0x00A7 WM_NCMBUTTONDOWN
0x00A8 WM_NCMBUTTONUP
0x00A9 WM_NCMBUTTONDBLCLK
0x00AB WM_NCXBUTTONDOWN
0x00AC WM_NCXBUTTONUP
0x00AD WM_NCXBUTTONDBLCLK
0x00B0 EM_GETSEL
0x00B1 EM_SETSEL
0x00B2 EM_GETRECT
0x00B3 EM_SETRECT
0x00B4 EM_SETRECTNP
0x00B5 EM_SCROLL
0x00B6 EM_LINESCROLL
0x00B7 EM_SCROLLCARET
0x00B8 EM_GETMODIFY
0x00B9 EM_SETMODIFY
0x00BA EM_GETLINECOUNT
0x00BB EM_LINEINDEX
0x00BC EM_SETHANDLE
0x00BD EM_GETHANDLE
0x00BE EM_GETTHUMB
0x00C1 EM_LINELENGTH
0x00C2 EM_REPLACESEL
0x00C3 EM_SETFONT
0x00C4 EM_GETLINE
0x00C5 EM_LIMITTEXT
0x00C5 EM_SETLIMITTEXT
0x00C6 EM_CANUNDO
0x00C7 EM_UNDO
0x00C8 EM_FMTLINES
0x00C9 EM_LINEFROMCHAR
0x00CA EM_SETWORDBREAK
0x00CB EM_SETTABSTOPS
0x00CC EM_SETPASSWORDCHAR
0x00CD EM_EMPTYUNDOBUFFER
0x00CE EM_GETFIRSTVISIBLELINE
0x00CF EM_SETREADONLY
0x00D0 EM_SETWORDBREAKPROC
0x00D1 EM_GETWORDBREAKPROC
0x00D2 EM_GETPASSWORDCHAR
0x00D3 EM_SETMARGINS
0x00D4 EM_GETMARGINS
0x00D5 EM_GETLIMITTEXT
0x00D6 EM_POSFROMCHAR
0x00D7 EM_CHARFROMPOS
0x00D8 EM_SETIMESTATUS
0x00D9 EM_GETIMESTATUS
0x00E0 SBM_SETPOS
0x00E1 SBM_GETPOS
0x00E2 SBM_SETRANGE
0x00E3 SBM_GETRANGE
0x00E4 SBM_ENABLE_ARROWS
0x00E6 SBM_SETRANGEREDRAW
0x00E9 SBM_SETSCROLLINFO
0x00EA SBM_GETSCROLLINFO
0x00EB SBM_GETSCROLLBARINFO
0x00F0 BM_GETCHECK
0x00F1 BM_SETCHECK
0x00F2 BM_GETSTATE
0x00F3 BM_SETSTATE
0x00F4 BM_SETSTYLE
0x00F5 BM_CLICK
0x00F6 BM_GETIMAGE
0x00F7 BM_SETIMAGE
0x00F8 BM_SETDONTCLICK
0x00FE WM_INPUT_DEVICE_CHANGE
0x00FF WM_INPUT
0x0100 WM_KEYDOWN
0x0100 WM_KEYFIRST
0x0101 WM_KEYUP
0x0102 WM_CHAR
0x0103 WM_DEADCHAR
0x0104 WM_SYSKEYDOWN
0x0105 WM_SYSKEYUP
0x0106 WM_SYSCHAR
0x0107 WM_SYSDEADCHAR
0x0108 WM_KEYLAST
0x0109 WM_UNICHAR
0x0109 WM_WNT_CONVERTREQUESTEX
0x010A WM_CONVERTREQUEST
0x010B WM_CONVERTRESULT
0x010C WM_INTERIM
0x010D WM_IME_STARTCOMPOSITION
0x010E WM_IME_ENDCOMPOSITION
0x010F WM_IME_COMPOSITION
0x010F WM_IME_KEYLAST
0x0110 WM_INITDIALOG
0x0111 WM_COMMAND
0x0112 WM_SYSCOMMAND
0x0113 WM_TIMER
0x0114 WM_HSCROLL
0x0115 WM_VSCROLL
0x0116 WM_INITMENU
0x0117 WM_INITMENUPOPUP
0x0118 WM_SYSTIMER
0x0119 WM_GESTURE
0x011A WM_GESTURENOTIFY
0x011F WM_MENUSELECT
0x0120 WM_MENUCHAR
0x0121 WM_ENTERIDLE
0x0122 WM_MENURBUTTONUP
0x0123 WM_MENUDRAG
0x0124 WM_MENUGETOBJECT
0x0125 WM_UNINITMENUPOPUP
0x0126 WM_MENUCOMMAND
0x0127 WM_CHANGEUISTATE
0x0128 WM_UPDATEUISTATE
0x0129 WM_QUERYUISTATE
0x0132 WM_CTLCOLORMSGBOX
0x0133 WM_CTLCOLOREDIT
0x0134 WM_CTLCOLORLISTBOX
0x0135 WM_CTLCOLORBTN
0x0136 WM_CTLCOLORDLG
0x0137 WM_CTLCOLORSCROLLBAR
0x0138 WM_CTLCOLORSTATIC
0x0140 CB_GETEDITSEL
0x0141 CB_LIMITTEXT
0x0142 CB_SETEDITSEL
0x0143 CB_ADDSTRING
0x0144 CB_DELETESTRING
0x0144 CBEM_DELETEITEM
0x0145 CB_DIR
0x0146 CB_GETCOUNT
0x0147 CB_GETCURSEL
0x0148 CB_GETLBTEXT
0x0149 CB_GETLBTEXTLEN
0x014A CB_INSERTSTRING
0x014B CB_RESETCONTENT
0x014C CB_FINDSTRING
0x014D CB_SELECTSTRING
0x014E CB_SETCURSEL
0x014F CB_SHOWDROPDOWN
0x0150 CB_GETITEMDATA
0x0151 CB_SETITEMDATA
0x0152 CB_GETDROPPEDCONTROLRECT
0x0153 CB_SETITEMHEIGHT
0x0154 CB_GETITEMHEIGHT
0x0155 CB_SETEXTENDEDUI
0x0156 CB_GETEXTENDEDUI
0x0157 CB_GETDROPPEDSTATE
0x0158 CB_FINDSTRINGEXACT
0x0159 CB_SETLOCALE
0x015A CB_GETLOCALE
0x015B CB_GETTOPINDEX
0x015C CB_SETTOPINDEX
0x015D CB_GETHORIZONTALEXTENT
0x015E CB_SETHORIZONTALEXTENT
0x015F CB_GETDROPPEDWIDTH
0x0160 CB_SETDROPPEDWIDTH
0x0161 CB_INITSTORAGE
0x0163 CB_MULTIPLEADDSTRING
0x0164 CB_GETCOMBOBOXINFO
0x0170 STM_SETICON
0x0171 STM_GETICON
0x0172 STM_SETIMAGE
0x0173 STM_GETIMAGE
0x0180 LB_ADDSTRING
0x0181 LB_INSERTSTRING
0x0182 LB_DELETESTRING
0x0183 LB_SELITEMRANGEEX
0x0184 LB_RESETCONTENT
0x0185 LB_SETSEL
0x0186 LB_SETCURSEL
0x0187 LB_GETSEL
0x0188 LB_GETCURSEL
0x0189 LB_GETTEXT
0x018A LB_GETTEXTLEN
0x018B LB_GETCOUNT
0x018C LB_SELECTSTRING
0x018D LB_DIR
0x018E LB_GETTOPINDEX
0x018F LB_FINDSTRING
0x0190 LB_GETSELCOUNT
0x0191 LB_GETSELITEMS
0x0192 LB_SETTABSTOPS
0x0193 LB_GETHORIZONTALEXTENT
0x0194 LB_SETHORIZONTALEXTENT
0x0195 LB_SETCOLUMNWIDTH
0x0196 LB_ADDFILE
0x0197 LB_SETTOPINDEX
0x0198 LB_GETITEMRECT
0x0199 LB_GETITEMDATA
0x019A LB_SETITEMDATA
0x019B LB_SELITEMRANGE
0x019C LB_SETANCHORINDEX
0x019D LB_GETANCHORINDEX
0x019E LB_SETCARETINDEX
0x019F LB_GETCARETINDEX
0x01A0 LB_SETITEMHEIGHT
0x01A1 LB_GETITEMHEIGHT
0x01A2 LB_FINDSTRINGEXACT
0x01A5 LB_SETLOCALE
0x01A6 LB_GETLOCALE
0x01A7 LB_SETCOUNT
0x01A8 LB_INITSTORAGE
0x01A9 LB_ITEMFROMPOINT
0x01B1 LB_MULTIPLEADDSTRING
0x01B2 LB_GETLISTBOXINFO
0x01E1 MN_GETHMENU
0x0200 WM_MOUSEFIRST
0x0200 WM_MOUSEMOVE
0x0201 WM_LBUTTONDOWN
0x0202 WM_LBUTTONUP
0x0203 WM_LBUTTONDBLCLK
0x0204 WM_RBUTTONDOWN
0x0205 WM_RBUTTONUP
0x0206 WM_RBUTTONDBLCLK
0x0207 WM_MBUTTONDOWN
0x0208 WM_MBUTTONUP
0x0209 WM_MBUTTONDBLCLK
0x0209 WM_MOUSELAST
0x020A WM_MOUSEWHEEL
0x020B WM_XBUTTONDOWN
0x020C WM_XBUTTONUP
0x020D WM_XBUTTONDBLCLK
0x020E WM_MOUSEHWHEEL
0x0210 WM_PARENTNOTIFY
0x0211 WM_ENTERMENULOOP
0x0212 WM_EXITMENULOOP
0x0213 WM_NEXTMENU
0x0214 WM_SIZING
0x0215 WM_CAPTURECHANGED
0x0216 WM_MOVING
0x0218 WM_POWERBROADCAST
0x0219 WM_DEVICECHANGE
0x0220 WM_MDICREATE
0x0221 WM_MDIDESTROY
0x0222 WM_MDIACTIVATE
0x0223 WM_MDIRESTORE
0x0224 WM_MDINEXT
0x0225 WM_MDIMAXIMIZE
0x0226 WM_MDITILE
0x0227 WM_MDICASCADE
0x0228 WM_MDIICONARRANGE
0x0229 WM_MDIGETACTIVE
0x0230 WM_MDISETMENU
0x0231 WM_ENTERSIZEMOVE
0x0232 WM_EXITSIZEMOVE
0x0233 WM_DROPFILES
0x0234 WM_MDIREFRESHMENU
0x0238 WM_POINTERDEVICECHANGE
0x0239 WM_POINTERDEVICEINRANGE
0x023A WM_POINTERDEVICEOUTOFRANGE
0x0240 WM_TOUCH
0x0241 WM_NCPOINTERUPDATE
0x0242 WM_NCPOINTERDOWN
0x0243 WM_NCPOINTERUP
0x0245 WM_POINTERUPDATE
0x0246 WM_POINTERDOWN
0x0247 WM_POINTERUP
0x0249 WM_POINTERENTER
0x024A WM_POINTERLEAVE
0x024B WM_POINTERACTIVATE
0x024C WM_POINTERCAPTURECHANGED
0x024D WM_TOUCHHITTESTING
0x024E WM_POINTERWHEEL
0x024F WM_POINTERHWHEEL
0x0250 DM_POINTERHITTEST
0x0251 WM_POINTERROUTEDTO
0x0252 WM_POINTERROUTEDAWAY
0x0253 WM_POINTERROUTEDRELEASED
0x0280 WM_IME_REPORT
0x0281 WM_IME_SETCONTEXT
0x0282 WM_IME_NOTIFY
0x0283 WM_IME_CONTROL
0x0284 WM_IME_COMPOSITIONFULL
0x0285 WM_IME_SELECT
0x0286 WM_IME_CHAR
0x0288 WM_IME_REQUEST
0x0290 WM_IME_KEYDOWN
0x0290 WM_IMEKEYDOWN
0x0291 WM_IME_KEYUP
0x0291 WM_IMEKEYUP
0x02A0 WM_NCMOUSEHOVER
0x02A1 WM_MOUSEHOVER
0x02A2 WM_NCMOUSELEAVE
0x02A3 WM_MOUSELEAVE
0x02B1 WM_WTSSESSION_CHANGE
0x02C0 WM_TABLET_FIRST
0x02DF WM_TABLET_LAST
0x02E0 WM_DPICHANGED
0x0300 WM_CUT
0x0301 WM_COPY
0x0302 WM_PASTE
0x0303 WM_CLEAR
0x80085 BOOBS
0x0304 WM_UNDO
0x0305 WM_RENDERFORMAT
0x0306 WM_RENDERALLFORMATS
0x0307 WM_DESTROYCLIPBOARD
0x0308 WM_DRAWCLIPBOARD
0x0309 WM_PAINTCLIPBOARD
0x030A WM_VSCROLLCLIPBOARD
0x030B WM_SIZECLIPBOARD
0x030C WM_ASKCBFORMATNAME
0x030D WM_CHANGECBCHAIN
0x030E WM_HSCROLLCLIPBOARD
0x030F WM_QUERYNEWPALETTE
0x0310 WM_PALETTEISCHANGING
0x0311 WM_PALETTECHANGED
0x0312 WM_HOTKEY
0x0317 WM_PRINT
0x0318 WM_PRINTCLIENT
0x0319 WM_APPCOMMAND
0x031A WM_THEMECHANGED
0x031D WM_CLIPBOARDUPDATE
0x031E WM_DWMCOMPOSITIONCHANGED
0x031F WM_DWMNCRENDERINGCHANGED
0x0320 WM_DWMCOLORIZATIONCOLORCHANGED
0x0321 WM_DWMWINDOWMAXIMIZEDCHANGE
0x0323 WM_DWMSENDICONICTHUMBNAIL
0x0326 WM_DWMSENDICONICLIVEPREVIEWBITMAP
0x033F WM_GETTITLEBARINFOEX
0x0358 WM_HANDHELDFIRST
0x035F WM_HANDHELDLAST
0x0360 WM_AFXFIRST
0x037F WM_AFXLAST
0x0380 WM_PENWINFIRST
0x0381 WM_RCRESULT
0x0382 WM_HOOKRCRESULT
0x0383 WM_GLOBALRCCHANGE
0x0383 WM_PENMISCINFO
0x0384 WM_SKB
0x0385 WM_HEDITCTL
0x0385 WM_PENCTL
0x0386 WM_PENMISC
0x0387 WM_CTLINIT
0x0388 WM_PENEVENT
0x038F WM_PENWINLAST
0x0400 DDM_SETFMT
0x0400 DM_GETDEFID
0x0400 NIN_SELECT
0x0400 TBM_GETPOS
0x0400 WM_PSD_PAGESETUPDLG
0x0400 WM_USER
0x0401 CBEM_INSERTITEMA
0x0401 DDM_DRAW
0x0401 DM_SETDEFID
0x0401 HKM_SETHOTKEY
0x0401 PBM_SETRANGE
0x0401 RB_INSERTBANDA
0x0401 SB_SETTEXTA
0x0401 TB_ENABLEBUTTON
0x0401 TBM_GETRANGEMIN
0x0401 TTM_ACTIVATE
0x0401 WM_CHOOSEFONT_GETLOGFONT
0x0401 WM_PSD_FULLPAGERECT
0x0402 CBEM_SETIMAGELIST
0x0402 DDM_CLOSE
0x0402 DM_REPOSITION
0x0402 HKM_GETHOTKEY
0x0402 PBM_SETPOS
0x0402 RB_DELETEBAND
0x0402 SB_GETTEXTA
0x0402 TB_CHECKBUTTON
0x0402 TBM_GETRANGEMAX
0x0402 WM_PSD_MINMARGINRECT
0x0403 CBEM_GETIMAGELIST
0x0403 DDM_BEGIN
0x0403 HKM_SETRULES
0x0403 PBM_DELTAPOS
0x0403 RB_GETBARINFO
0x0403 SB_GETTEXTLENGTHA
0x0403 TB_PRESSBUTTON
0x0403 TBM_GETTIC
0x0403 TTM_SETDELAYTIME
0x0403 WM_PSD_MARGINRECT
0x0404 CBEM_GETITEMA
0x0404 DDM_END
0x0404 PBM_SETSTEP
0x0404 RB_SETBARINFO
0x0404 SB_SETPARTS
0x0404 TB_HIDEBUTTON
0x0404 TBM_SETTIC
0x0404 TTM_ADDTOOLA
0x0404 WM_PSD_GREEKTEXTRECT
0x0405 CBEM_SETITEMA
0x0405 PBM_STEPIT
0x0405 TB_INDETERMINATE
0x0405 TBM_SETPOS
0x0405 TTM_DELTOOLA
0x0405 WM_PSD_ENVSTAMPRECT
0x0406 CBEM_GETCOMBOCONTROL
0x0406 PBM_SETRANGE32
0x0406 RB_SETBANDINFOA
0x0406 SB_GETPARTS
0x0406 TB_MARKBUTTON
0x0406 TBM_SETRANGE
0x0406 TTM_NEWTOOLRECTA
0x0406 WM_PSD_YAFULLPAGERECT
0x0407 CBEM_GETEDITCONTROL
0x0407 PBM_GETRANGE
0x0407 RB_SETPARENT
0x0407 SB_GETBORDERS
0x0407 TBM_SETRANGEMIN
0x0407 TTM_RELAYEVENT
0x0408 CBEM_SETEXSTYLE
0x0408 PBM_GETPOS
0x0408 RB_HITTEST
0x0408 SB_SETMINHEIGHT
0x0408 TBM_SETRANGEMAX
0x0408 TTM_GETTOOLINFOA
0x0409 CBEM_GETEXSTYLE
0x0409 CBEM_GETEXTENDEDSTYLE
0x0409 PBM_SETBARCOLOR
0x0409 RB_GETRECT
0x0409 SB_SIMPLE
0x0409 TB_ISBUTTONENABLED
0x0409 TBM_CLEARTICS
0x0409 TTM_SETTOOLINFOA
0x040A CBEM_HASEDITCHANGED
0x040A RB_INSERTBANDW
0x040A SB_GETRECT
0x040A TB_ISBUTTONCHECKED
0x040A TBM_SETSEL
0x040A TTM_HITTESTA
0x040A WIZ_QUERYNUMPAGES
0x040B CBEM_INSERTITEMW
0x040B RB_SETBANDINFOW
0x040B SB_SETTEXTW
0x040B TB_ISBUTTONPRESSED
0x040B TBM_SETSELSTART
0x040B TTM_GETTEXTA
0x040B WIZ_NEXT
0x040C CBEM_SETITEMW
0x040C RB_GETBANDCOUNT
0x040C SB_GETTEXTLENGTHW
0x040C TB_ISBUTTONHIDDEN
0x040C TBM_SETSELEND
0x040C TTM_UPDATETIPTEXTA
0x040C WIZ_PREV
0x040D CBEM_GETITEMW
0x040D RB_GETROWCOUNT
0x040D SB_GETTEXTW
0x040D TB_ISBUTTONINDETERMINATE
0x040D TTM_GETTOOLCOUNT
0x040E CBEM_SETEXTENDEDSTYLE
0x040E RB_GETROWHEIGHT
0x040E SB_ISSIMPLE
0x040E TB_ISBUTTONHIGHLIGHTED
0x040E TBM_GETPTICS
0x040E TTM_ENUMTOOLSA
0x040F SB_SETICON
0x040F TBM_GETTICPOS
0x040F TTM_GETCURRENTTOOLA
0x0410 RB_IDTOINDEX
0x0410 SB_SETTIPTEXTA
0x0410 TBM_GETNUMTICS
0x0410 TTM_WINDOWFROMPOINT
0x0411 RB_GETTOOLTIPS
0x0411 SB_SETTIPTEXTW
0x0411 TB_SETSTATE
0x0411 TBM_GETSELSTART
0x0411 TTM_TRACKACTIVATE
0x0412 RB_SETTOOLTIPS
0x0412 SB_GETTIPTEXTA
0x0412 TB_GETSTATE
0x0412 TBM_GETSELEND
0x0412 TTM_TRACKPOSITION
0x0413 RB_SETBKCOLOR
0x0413 SB_GETTIPTEXTW
0x0413 TB_ADDBITMAP
0x0413 TBM_CLEARSEL
0x0413 TTM_SETTIPBKCOLOR
0x0414 RB_GETBKCOLOR
0x0414 SB_GETICON
0x0414 TB_ADDBUTTONSA
0x0414 TBM_SETTICFREQ
0x0414 TTM_SETTIPTEXTCOLOR
0x0415 RB_SETTEXTCOLOR
0x0415 TB_INSERTBUTTONA
0x0415 TBM_SETPAGESIZE
0x0415 TTM_GETDELAYTIME
0x0416 RB_GETTEXTCOLOR
0x0416 TB_DELETEBUTTON
0x0416 TBM_GETPAGESIZE
0x0416 TTM_GETTIPBKCOLOR
0x0417 RB_SIZETORECT
0x0417 TB_GETBUTTON
0x0417 TBM_SETLINESIZE
0x0417 TTM_GETTIPTEXTCOLOR
0x0418 RB_BEGINDRAG
0x0418 TB_BUTTONCOUNT
0x0418 TBM_GETLINESIZE
0x0418 TTM_SETMAXTIPWIDTH
0x0419 RB_ENDDRAG
0x0419 TB_COMMANDTOINDEX
0x0419 TBM_GETTHUMBRECT
0x0419 TTM_GETMAXTIPWIDTH
0x041A RB_DRAGMOVE
0x041A TB_SAVERESTOREA
0x041A TBM_GETCHANNELRECT
0x041A TTM_SETMARGIN
0x041B RB_GETBARHEIGHT
0x041B TB_CUSTOMIZE
0x041B TBM_SETTHUMBLENGTH
0x041B TTM_GETMARGIN
0x041C RB_GETBANDINFOW
0x041C TB_ADDSTRINGA
0x041C TBM_GETTHUMBLENGTH
0x041C TTM_POP
0x041D RB_GETBANDINFOA
0x041D TB_GETITEMRECT
0x041D TBM_SETTOOLTIPS
0x041D TTM_UPDATE
0x041E RB_MINIMIZEBAND
0x041E TB_BUTTONSTRUCTSIZE
0x041E TBM_GETTOOLTIPS
0x041E TTM_GETBUBBLESIZE
0x041F RB_MAXIMIZEBAND
0x041F TB_SETBUTTONSIZE
0x041F TBM_SETTIPSIDE
0x041F TTM_ADJUSTRECT
0x0420 TB_SETBITMAPSIZE
0x0420 TBM_SETBUDDY
0x0420 TTM_SETTITLEA
0x0421 MSG_FTS_JUMP_VA
0x0421 TB_AUTOSIZE
0x0421 TBM_GETBUDDY
0x0421 TTM_SETTITLEW
0x0422 RB_GETBANDBORDERS
0x0422 TBM_SETPOSNOTIFY
0x0422 TTM_POPUP
0x0423 MSG_FTS_JUMP_QWORD
0x0423 RB_SHOWBAND
0x0423 TB_GETTOOLTIPS
0x0423 TTM_GETTITLE
0x0424 MSG_REINDEX_REQUEST
0x0424 TB_SETTOOLTIPS
0x0425 MSG_FTS_WHERE_IS_IT
0x0425 RB_SETPALETTE
0x0425 TB_SETPARENT
0x0426 RB_GETPALETTE
0x0427 RB_MOVEBAND
0x0427 TB_SETROWS
0x0428 RB_GETBANDMARGINS
0x0428 TB_GETROWS
0x0429 RB_SETEXTENDEDSTYLE
0x0429 TB_GETBITMAPFLAGS
0x042A RB_GETEXTENDEDSTYLE
0x042A TB_SETCMDID
0x042B RB_PUSHCHEVRON
0x042B TB_CHANGEBITMAP
0x042C RB_SETBANDWIDTH
0x042C TB_GETBITMAP
0x042D MSG_GET_DEFFONT
0x042D TB_GETBUTTONTEXTA
0x042E TB_REPLACEBITMAP
0x042F TB_SETINDENT
0x0430 TB_SETIMAGELIST
0x0431 TB_GETIMAGELIST
0x0432 EM_CANPASTE
0x0432 TB_LOADIMAGES
0x0432 TTM_ADDTOOLW
0x0433 EM_DISPLAYBAND
0x0433 TB_GETRECT
0x0433 TTM_DELTOOLW
0x0434 EM_EXGETSEL
0x0434 TB_SETHOTIMAGELIST
0x0434 TTM_NEWTOOLRECTW
0x0435 EM_EXLIMITTEXT
0x0435 TB_GETHOTIMAGELIST
0x0435 TTM_GETTOOLINFOW
0x0436 EM_EXLINEFROMCHAR
0x0436 TB_SETDISABLEDIMAGELIST
0x0436 TTM_SETTOOLINFOW
0x0437 EM_EXSETSEL
0x0437 TB_GETDISABLEDIMAGELIST
0x0437 TTM_HITTESTW
0x0438 EM_FINDTEXT
0x0438 TB_SETSTYLE
0x0438 TTM_GETTEXTW
0x0439 EM_FORMATRANGE
0x0439 TB_GETSTYLE
0x0439 TTM_UPDATETIPTEXTW
0x043A EM_GETCHARFORMAT
0x043A TB_GETBUTTONSIZE
0x043A TTM_ENUMTOOLSW
0x043B EM_GETEVENTMASK
0x043B TB_SETBUTTONWIDTH
0x043B TTM_GETCURRENTTOOLW
0x043C EM_GETOLEINTERFACE
0x043C TB_SETMAXTEXTROWS
0x043D EM_GETPARAFORMAT
0x043D TB_GETTEXTROWS
0x043E EM_GETSELTEXT
0x043E TB_GETOBJECT
0x043F EM_HIDESELECTION
0x043F TB_GETBUTTONINFOW
0x0440 EM_PASTESPECIAL
0x0440 TB_SETBUTTONINFOW
0x0441 EM_REQUESTRESIZE
0x0441 TB_GETBUTTONINFOA
0x0442 EM_SELECTIONTYPE
0x0442 TB_SETBUTTONINFOA
0x0443 EM_SETBKGNDCOLOR
0x0443 TB_INSERTBUTTONW
0x0444 EM_SETCHARFORMAT
0x0444 TB_ADDBUTTONSW
0x0445 EM_SETEVENTMASK
0x0445 TB_HITTEST
0x0446 EM_SETOLECALLBACK
0x0446 TB_SETDRAWTEXTFLAGS
0x0447 EM_SETPARAFORMAT
0x0447 TB_GETHOTITEM
0x0448 EM_SETTARGETDEVICE
0x0448 TB_SETHOTITEM
0x0449 EM_STREAMIN
0x0449 TB_SETANCHORHIGHLIGHT
0x044A EM_STREAMOUT
0x044A TB_GETANCHORHIGHLIGHT
0x044B EM_GETTEXTRANGE
0x044B TB_GETBUTTONTEXTW
0x044C EM_FINDWORDBREAK
0x044C TB_SAVERESTOREW
0x044D EM_SETOPTIONS
0x044D TB_ADDSTRINGW
0x044E EM_GETOPTIONS
0x044E TB_MAPACCELERATORA
0x044F EM_FINDTEXTEX
0x044F TB_GETINSERTMARK
0x0450 EM_GETWORDBREAKPROCEX
0x0450 TB_SETINSERTMARK
0x0451 EM_SETWORDBREAKPROCEX
0x0451 TB_INSERTMARKHITTEST
0x0452 EM_SETUNDOLIMIT
0x0452 TB_MOVEBUTTON
0x0453 TB_GETMAXSIZE
0x0454 EM_REDO
0x0454 TB_SETEXTENDEDSTYLE
0x0455 EM_CANREDO
0x0455 TB_GETEXTENDEDSTYLE
0x0456 EM_GETUNDONAME
0x0456 TB_GETPADDING
0x0457 EM_GETREDONAME
0x0457 TB_SETPADDING
0x0458 EM_STOPGROUPTYPING
0x0458 TB_SETINSERTMARKCOLOR
0x0459 EM_SETTEXTMODE
0x0459 TB_GETINSERTMARKCOLOR
0x045A EM_GETTEXTMODE
0x045A TB_MAPACCELERATORW
0x045B EM_AUTOURLDETECT
0x045B TB_GETSTRINGW
0x045C EM_GETAUTOURLDETECT
0x045C TB_GETSTRINGA
0x045D EM_SETPALETTE
0x045D TB_SETBOUNDINGSIZE
0x045E EM_GETTEXTEX
0x045E TB_SETHOTITEM2
0x045F EM_GETTEXTLENGTHEX
0x045F TB_HASACCELERATOR
0x0460 EM_SHOWSCROLLBAR
0x0460 TB_SETLISTGAP
0x0461 CCM_TRANSLATEACCELERATOR
0x0461 EM_SETTEXTEX
0x0461 HDM_TRANSLATEACCELERATOR
0x0461 TB_TRANSLATEACCELERATOR
0x0462 TB_GETIMAGELISTCOUNT
0x0463 TAPI_REPLY
0x0463 TB_GETIDEALSIZE
0x0464 ACM_OPENA
0x0464 BFFM_SETSTATUSTEXTA
0x0464 CDM_FIRST
0x0464 CDM_GETSPEC
0x0464 EM_SETPUNCTUATION
0x0464 IPM_CLEARADDRESS
0x0464 WM_CAP_UNICODE_START
0x0465 ACM_PLAY
0x0465 BFFM_ENABLEOK
0x0465 CDM_GETFILEPATH
0x0465 EM_GETPUNCTUATION
0x0465 IPM_SETADDRESS
0x0465 PSM_SETCURSEL
0x0465 TB_GETMETRICS
0x0465 UDM_SETRANGE
0x0465 WM_CHOOSEFONT_SETLOGFONT
0x0466 ACM_STOP
0x0466 BFFM_SETSELECTIONA
0x0466 CDM_GETFOLDERPATH
0x0466 EM_SETWORDWRAPMODE
0x0466 IPM_GETADDRESS
0x0466 PSM_REMOVEPAGE
0x0466 TB_SETMETRICS
0x0466 UDM_GETRANGE
0x0466 WM_CAP_SET_CALLBACK_ERRORW
0x0466 WM_CHOOSEFONT_SETFLAGS
0x0467 ACM_OPENW
0x0467 BFFM_SETSELECTIONW
0x0467 CDM_GETFOLDERIDLIST
0x0467 EM_GETWORDWRAPMODE
0x0467 IPM_SETRANGE
0x0467 PSM_ADDPAGE
0x0467 TB_GETITEMDROPDOWNRECT
0x0467 UDM_SETPOS
0x0467 WM_CAP_SET_CALLBACK_STATUSW
0x0468 ACM_ISPLAYING
0x0468 BFFM_SETSTATUSTEXTW
0x0468 CDM_SETCONTROLTEXT
0x0468 EM_SETIMECOLOR
0x0468 IPM_SETFOCUS
0x0468 PSM_CHANGED
0x0468 TB_SETPRESSEDIMAGELIST
0x0468 UDM_GETPOS
0x0469 CDM_HIDECONTROL
0x0469 EM_GETIMECOLOR
0x0469 IPM_ISBLANK
0x0469 PSM_RESTARTWINDOWS
0x0469 TB_GETPRESSEDIMAGELIST
0x0469 UDM_SETBUDDY
0x046A CDM_SETDEFEXT
0x046A EM_SETIMEOPTIONS
0x046A PSM_REBOOTSYSTEM
0x046A UDM_GETBUDDY
0x046B EM_GETIMEOPTIONS
0x046B PSM_CANCELTOCLOSE
0x046B UDM_SETACCEL
0x046C EM_CONVPOSITION
0x046C EM_CONVPOSITION
0x046C PSM_QUERYSIBLINGS
0x046C UDM_GETACCEL
0x046D MCIWNDM_GETZOOM
0x046D PSM_UNCHANGED
0x046D UDM_SETBASE
0x046E PSM_APPLY
0x046E UDM_GETBASE
0x046F PSM_SETTITLEA
0x046F UDM_SETRANGE32
0x0470 PSM_SETWIZBUTTONS
0x0470 UDM_GETRANGE32
0x0470 WM_CAP_DRIVER_GET_NAMEW
0x0471 PSM_PRESSBUTTON
0x0471 UDM_SETPOS32
0x0471 WM_CAP_DRIVER_GET_VERSIONW
0x0472 PSM_SETCURSELID
0x0472 UDM_GETPOS32
0x0473 PSM_SETFINISHTEXTA
0x0474 PSM_GETTABCONTROL
0x0475 PSM_ISDIALOGMESSAGE
0x0476 MCIWNDM_REALIZE
0x0476 PSM_GETCURRENTPAGEHWND
0x0477 MCIWNDM_SETTIMEFORMATA
0x0477 PSM_INSERTPAGE
0x0478 EM_SETLANGOPTIONS
0x0478 MCIWNDM_GETTIMEFORMATA
0x0478 PSM_SETTITLEW
0x0478 WM_CAP_FILE_SET_CAPTURE_FILEW
0x0479 EM_GETLANGOPTIONS
0x0479 MCIWNDM_VALIDATEMEDIA
0x0479 PSM_SETFINISHTEXTW
0x0479 WM_CAP_FILE_GET_CAPTURE_FILEW
0x047A EM_GETIMECOMPMODE
0x047B EM_FINDTEXTW
0x047B MCIWNDM_PLAYTO
0x047B WM_CAP_FILE_SAVEASW
0x047C EM_FINDTEXTEXW
0x047C MCIWNDM_GETFILENAMEA
0x047D EM_RECONVERSION
0x047D MCIWNDM_GETDEVICEA
0x047D PSM_SETHEADERTITLEA
0x047D WM_CAP_FILE_SAVEDIBW
0x047E EM_SETIMEMODEBIAS
0x047E MCIWNDM_GETPALETTE
0x047E PSM_SETHEADERTITLEW
0x047F EM_GETIMEMODEBIAS
0x047F MCIWNDM_SETPALETTE
0x047F PSM_SETHEADERSUBTITLEA
0x0480 MCIWNDM_GETERRORA
0x0480 PSM_SETHEADERSUBTITLEW
0x0481 PSM_HWNDTOINDEX
0x0482 PSM_INDEXTOHWND
0x0483 MCIWNDM_SETINACTIVETIMER
0x0483 PSM_PAGETOINDEX
0x0484 PSM_INDEXTOPAGE
0x0485 DL_BEGINDRAG
0x0485 MCIWNDM_GETINACTIVETIMER
0x0485 PSM_IDTOINDEX
0x0486 DL_DRAGGING
0x0486 PSM_INDEXTOID
0x0487 DL_DROPPED
0x0487 PSM_GETRESULT
0x0488 DL_CANCELDRAG
0x0488 PSM_RECALCPAGESIZES
0x048C MCIWNDM_GET_SOURCE
0x048D MCIWNDM_PUT_SOURCE
0x048E MCIWNDM_GET_DEST
0x048F MCIWNDM_PUT_DEST
0x0490 MCIWNDM_CAN_PLAY
0x0491 MCIWNDM_CAN_WINDOW
0x0492 MCIWNDM_CAN_RECORD
0x0493 MCIWNDM_CAN_SAVE
0x0494 MCIWNDM_CAN_EJECT
0x0495 MCIWNDM_CAN_CONFIG
0x0496 IE_GETINK
0x0496 IE_MSGFIRST
0x0496 MCIWNDM_PALETTEKICK
0x0497 IE_SETINK
0x0498 IE_GETPENTIP
0x0499 IE_SETPENTIP
0x049A IE_GETERASERTIP
0x049B IE_SETERASERTIP
0x049C IE_GETBKGND
0x049D IE_SETBKGND
0x049E IE_GETGRIDORIGIN
0x049F IE_SETGRIDORIGIN
0x04A0 IE_GETGRIDPEN
0x04A1 IE_SETGRIDPEN
0x04A2 IE_GETGRIDSIZE
0x04A3 IE_SETGRIDSIZE
0x04A4 IE_GETMODE
0x04A5 IE_SETMODE
0x04A6 IE_GETINKRECT
0x04A6 WM_CAP_SET_MCI_DEVICEW
0x04A7 WM_CAP_GET_MCI_DEVICEW
0x04B4 WM_CAP_PAL_OPENW
0x04B5 WM_CAP_PAL_SAVEW
0x04B8 IE_GETAPPDATA
0x04B9 IE_SETAPPDATA
0x04BA IE_GETDRAWOPTS
0x04BB IE_SETDRAWOPTS
0x04BC IE_GETFORMAT
0x04BD IE_SETFORMAT
0x04BE IE_GETINKINPUT
0x04BF IE_SETINKINPUT
0x04C0 IE_GETNOTIFY
0x04C1 IE_SETNOTIFY
0x04C2 IE_GETRECOG
0x04C3 IE_SETRECOG
0x04C4 IE_GETSECURITY
0x04C5 IE_SETSECURITY
0x04C6 IE_GETSEL
0x04C7 IE_SETSEL
0x04C8 CDM_LAST
0x04C8 EM_SETBIDIOPTIONS
0x04C8 IE_DOCOMMAND
0x04C8 MCIWNDM_NOTIFYMODE
0x04C9 EM_GETBIDIOPTIONS
0x04C9 IE_GETCOMMAND
0x04CA EM_SETTYPOGRAPHYOPTIONS
0x04CA IE_GETCOUNT
0x04CB EM_GETTYPOGRAPHYOPTIONS
0x04CB IE_GETGESTURE
0x04CB MCIWNDM_NOTIFYMEDIA
0x04CC EM_SETEDITSTYLE
0x04CC IE_GETMENU
0x04CD EM_GETEDITSTYLE
0x04CD IE_GETPAINTDC
0x04CD MCIWNDM_NOTIFYERROR
0x04CE IE_GETPDEVENT
0x04CF IE_GETSELCOUNT
0x04D0 IE_GETSELITEMS
0x04D1 IE_GETSTYLE
0x04DB MCIWNDM_SETTIMEFORMATW
0x04DC EM_OUTLINE
0x04DC EM_OUTLINE
0x04DC MCIWNDM_GETTIMEFORMATW
0x04DD EM_GETSCROLLPOS
0x04DE EM_SETSCROLLPOS
0x04DF EM_SETFONTSIZE
0x04E0 EM_GETZOOM
0x04E0 MCIWNDM_GETFILENAMEW
0x04E1 EM_SETZOOM
0x04E1 MCIWNDM_GETDEVICEW
0x04E2 EM_GETVIEWKIND
0x04E3 EM_SETVIEWKIND
0x04E4 EM_GETPAGE
0x04E4 MCIWNDM_GETERRORW
0x04E5 EM_SETPAGE
0x04E6 EM_GETHYPHENATEINFO
0x04E7 EM_SETHYPHENATEINFO
0x04EB EM_GETPAGEROTATE
0x04EC EM_SETPAGEROTATE
0x04ED EM_GETCTFMODEBIAS
0x04EE EM_SETCTFMODEBIAS
0x04F0 EM_GETCTFOPENSTATUS
0x04F1 EM_SETCTFOPENSTATUS
0x04F2 EM_GETIMECOMPTEXT
0x04F3 EM_ISIME
0x04F4 EM_GETIMEPROPERTY
0x050D EM_GETQUERYRTFOBJ
0x050E EM_SETQUERYRTFOBJ
0x0600 FM_GETFOCUS
0x0601 FM_GETDRIVEINFOA
0x0602 FM_GETSELCOUNT
0x0603 FM_GETSELCOUNTLFN
0x0604 FM_GETFILESELA
0x0605 FM_GETFILESELLFNA
0x0606 FM_REFRESH_WINDOWS
0x0607 FM_RELOAD_EXTENSIONS
0x0611 FM_GETDRIVEINFOW
0x0614 FM_GETFILESELW
0x0615 FM_GETFILESELLFNW
0x0659 WLX_WM_SAS
0x07E8 SM_GETSELCOUNT
0x07E8 UM_GETSELCOUNT
0x07E8 WM_CPL_LAUNCH
0x07E9 SM_GETSERVERSELA
0x07E9 UM_GETUSERSELA
0x07E9 WM_CPL_LAUNCHED
0x07EA SM_GETSERVERSELW
0x07EA UM_GETUSERSELW
0x07EB SM_GETCURFOCUSA
0x07EB UM_GETGROUPSELA
0x07EC SM_GETCURFOCUSW
0x07EC UM_GETGROUPSELW
0x07ED SM_GETOPTIONS
0x07ED UM_GETCURFOCUSA
0x07EE UM_GETCURFOCUSW
0x07EF UM_GETOPTIONS
0x07F0 UM_GETOPTIONS2
0x1000 DTM_FIRST
0x1000 LVM_FIRST
0x1000 LVM_GETBKCOLOR
0x1000 MCM_FIRST
0x1001 DTM_GETSYSTEMTIME
0x1001 LVM_SETBKCOLOR
0x1001 MCM_GETCURSEL
0x1002 DTM_SETSYSTEMTIME
0x1002 LVM_GETIMAGELIST
0x1002 MCM_SETCURSEL
0x1003 DTM_GETRANGE
0x1003 LVM_SETIMAGELIST
0x1003 MCM_GETMAXSELCOUNT
0x1004 DTM_SETRANGE
0x1004 LVM_GETITEMCOUNT
0x1004 MCM_SETMAXSELCOUNT
0x1005 DTM_SETFORMATA
0x1005 LVM_GETITEMA
0x1005 MCM_GETSELRANGE
0x1006 DTM_SETMCCOLOR
0x1006 LVM_SETITEMA
0x1006 MCM_SETSELRANGE
0x1007 DTM_GETMCCOLOR
0x1007 LVM_INSERTITEMA
0x1007 MCM_GETMONTHRANGE
0x1008 DTM_GETMONTHCAL
0x1008 LVM_DELETEITEM
0x1008 MCM_SETDAYSTATE
0x1009 DTM_SETMCFONT
0x1009 LVM_DELETEALLITEMS
0x1009 MCM_GETMINREQRECT
0x100A DTM_GETMCFONT
0x100A LVM_GETCALLBACKMASK
0x100A MCM_SETCOLOR
0x100B DTM_SETMCSTYLE
0x100B LVM_SETCALLBACKMASK
0x100B MCM_GETCOLOR
0x100C DTM_GETMCSTYLE
0x100C LVM_GETNEXTITEM
0x100D DTM_CLOSEMONTHCAL
0x100D LVM_FINDITEMA
0x100E DTM_GETDATETIMEPICKERINFO
0x100E LVM_GETITEMRECT
0x100F DTM_GETIDEALSIZE
0x100F LVM_SETITEMPOSITION
0x1010 LVM_GETITEMPOSITION
0x1011 LVM_GETSTRINGWIDTHA
0x1012 LVM_HITTEST
0x1013 LVM_ENSUREVISIBLE
0x1014 LVM_SCROLL
0x1015 LVM_REDRAWITEMS
0x1016 LVM_ARRANGE
0x1017 LVM_EDITLABELA
0x1018 LVM_GETEDITCONTROL
0x1019 LVM_GETCOLUMNA
0x101A LVM_SETCOLUMNA
0x101B LVM_INSERTCOLUMNA
0x101C LVM_DELETECOLUMN
0x101D LVM_GETCOLUMNWIDTH
0x101E LVM_SETCOLUMNWIDTH
0x101F LVM_GETHEADER
0x1021 LVM_CREATEDRAGIMAGE
0x1022 LVM_GETVIEWRECT
0x1023 LVM_GETTEXTCOLOR
0x1024 LVM_SETTEXTCOLOR
0x1025 LVM_GETTEXTBKCOLOR
0x1026 LVM_SETTEXTBKCOLOR
0x1027 LVM_GETTOPINDEX
0x1028 LVM_GETCOUNTPERPAGE
0x1029 LVM_GETORIGIN
0x102A LVM_UPDATE
0x102B LVM_SETITEMSTATE
0x102C LVM_GETITEMSTATE
0x102D LVM_GETITEMTEXTA
0x102E LVM_SETITEMTEXTA
0x102F LVM_SETITEMCOUNT
0x1030 LVM_SORTITEMS
0x1031 LVM_SETITEMPOSITION32
0x1032 DTM_SETFORMATW
0x1032 LVM_GETSELECTEDCOUNT
0x1033 LVM_GETITEMSPACING
0x1034 LVM_GETISEARCHSTRINGA
0x1035 LVM_SETICONSPACING
0x1036 LVM_SETEXTENDEDLISTVIEWSTYLE
0x1037 LVM_GETEXTENDEDLISTVIEWSTYLE
0x1038 LVM_GETSUBITEMRECT
0x1039 LVM_SUBITEMHITTEST
0x103A LVM_SETCOLUMNORDERARRAY
0x103B LVM_GETCOLUMNORDERARRAY
0x103C LVM_SETHOTITEM
0x103D LVM_GETHOTITEM
0x103E LVM_SETHOTCURSOR
0x103F LVM_GETHOTCURSOR
0x1040 LVM_APPROXIMATEVIEWRECT
0x1041 LVM_SETWORKAREAS
0x1042 LVM_GETSELECTIONMARK
0x1043 LVM_SETSELECTIONMARK
0x1044 LVM_SETBKIMAGEA
0x1045 LVM_GETBKIMAGEA
0x1046 LVM_GETWORKAREAS
0x1047 LVM_SETHOVERTIME
0x1048 LVM_GETHOVERTIME
0x1049 LVM_GETNUMBEROFWORKAREAS
0x104A LVM_SETTOOLTIPS
0x104B LVM_GETITEMW
0x104C LVM_SETITEMW
0x104D LVM_INSERTITEMW
0x104E LVM_GETTOOLTIPS
0x1051 LVM_SORTITEMSEX
0x1053 LVM_FINDITEMW
0x1057 LVM_GETSTRINGWIDTHW
0x105C LVM_GETGROUPSTATE
0x105D LVM_GETFOCUSEDGROUP
0x105F LVM_GETCOLUMNW
0x1060 LVM_SETCOLUMNW
0x1061 LVM_INSERTCOLUMNW
0x1073 LVM_GETITEMTEXTW
0x1074 LVM_SETITEMTEXTW
0x1075 LVM_GETISEARCHSTRINGW
0x1076 LVM_EDITLABELW
0x108A LVM_SETBKIMAGEW
0x108B LVM_GETBKIMAGEW
0x108C LVM_SETSELECTEDCOLUMN
0x108D LVM_SETTILEWIDTH
0x108E LVM_SETVIEW
0x108F LVM_GETVIEW
0x1091 LVM_INSERTGROUP
0x1093 LVM_SETGROUPINFO
0x1095 LVM_GETGROUPINFO
0x1096 LVM_REMOVEGROUP
0x1097 LVM_MOVEGROUP
0x1098 LVM_GETGROUPCOUNT
0x1099 LVM_GETGROUPINFOBYINDEX
0x109A LVM_MOVEITEMTOGROUP
0x109B LVM_SETGROUPMETRICS
0x109C LVM_GETGROUPMETRICS
0x109D LVM_ENABLEGROUPVIEW
0x109E LVM_SORTGROUPS
0x109F LVM_INSERTGROUPSORTED
0x10A0 LVM_REMOVEALLGROUPS
0x10A1 LVM_HASGROUP
0x10A2 LVM_SETTILEVIEWINFO
0x10A3 LVM_GETTILEVIEWINFO
0x10A4 LVM_SETTILEINFO
0x10A5 LVM_GETTILEINFO
0x10A6 LVM_SETINSERTMARK
0x10A7 LVM_GETINSERTMARK
0x10A8 LVM_INSERTMARKHITTEST
0x10A9 LVM_GETINSERTMARKRECT
0x10AA LVM_SETINSERTMARKCOLOR
0x10AB LVM_GETINSERTMARKCOLOR
0x10AD LVM_SETINFOTIP
0x10AE LVM_GETSELECTEDCOLUMN
0x10AF LVM_ISGROUPVIEWENABLED
0x10B0 LVM_GETOUTLINECOLOR
0x10B1 LVM_SETOUTLINECOLOR
0x10B3 LVM_CANCELEDITLABEL
0x10B4 LVM_MAPINDEXTOID
0x10B5 LVM_MAPIDTOINDEX
0x10B6 LVM_ISITEMVISIBLE
0x10CC LVM_GETEMPTYTEXT
0x10CD LVM_GETFOOTERRECT
0x10CE LVM_GETFOOTERINFO
0x10CF LVM_GETFOOTERITEMRECT
0x10D0 LVM_GETFOOTERITEM
0x10D1 LVM_GETITEMINDEXRECT
0x10D2 LVM_SETITEMINDEXSTATE
0x10D3 LVM_GETNEXTITEMINDEX
0x1100 TV_FIRST
0x1100 TVM_INSERTITEMA
0x1101 TVM_DELETEITEM
0x1102 TVM_EXPAND
0x1104 TVM_GETITEMRECT
0x1105 TVM_GETCOUNT
0x1106 TVM_GETINDENT
0x1107 TVM_SETINDENT
0x1108 TVM_GETIMAGELIST
0x1109 TVM_SETIMAGELIST
0x110A TVM_GETNEXTITEM
0x110B TVM_SELECTITEM
0x110C TVM_GETITEMA
0x110D TVM_SETITEMA
0x110E TVM_EDITLABELA
0x110F TVM_GETEDITCONTROL
0x1110 TVM_GETVISIBLECOUNT
0x1111 TVM_HITTEST
0x1112 TVM_CREATEDRAGIMAGE
0x1113 TVM_SORTCHILDREN
0x1114 TVM_ENSUREVISIBLE
0x1115 TVM_SORTCHILDRENCB
0x1116 TVM_ENDEDITLABELNOW
0x1117 TVM_GETISEARCHSTRINGA
0x1118 TVM_SETTOOLTIPS
0x1119 TVM_GETTOOLTIPS
0x111A TVM_SETINSERTMARK
0x111B TVM_SETITEMHEIGHT
0x111C TVM_GETITEMHEIGHT
0x111D TVM_SETBKCOLOR
0x111E TVM_SETTEXTCOLOR
0x111F TVM_GETBKCOLOR
0x1120 TVM_GETTEXTCOLOR
0x1121 TVM_SETSCROLLTIME
0x1122 TVM_GETSCROLLTIME
0x1123 TVM_SETBORDER
0x1125 TVM_SETINSERTMARKCOLOR
0x1126 TVM_GETINSERTMARKCOLOR
0x1127 TVM_GETITEMSTATE
0x1128 TVM_SETLINECOLOR
0x1129 TVM_GETLINECOLOR
0x112A TVM_MAPACCIDTOHTREEITEM
0x112B TVM_MAPHTREEITEMTOACCID
0x112C TVM_SETEXTENDEDSTYLE
0x112D TVM_GETEXTENDEDSTYLE
0x1132 TVM_INSERTITEMW
0x113A TVM_SETHOT
0x113B TVM_SETAUTOSCROLLINFO
0x113E TVM_GETITEMW
0x113F TVM_SETITEMW
0x1140 TVM_GETISEARCHSTRINGW
0x1141 TVM_EDITLABELW
0x1146 TVM_GETSELECTEDCOUNT
0x1147 TVM_SHOWINFOTIP
0x1148 TVM_GETITEMPARTRECT
0x11F1 CTL3D_CTLCOLORMSGBOX
0x11F1 CTL3D_FIRST
0x11F2 CTL3D_CTLCOLOREDIT
0x11F3 CTL3D_CTLCOLORLISTBOX
0x11F4 CTL3D_CTLCOLORBTN
0x11F5 CTL3D_CTLCOLORSCROLLBAR
0x11F6 CTL3D_CTLCOLORSTATIC
0x11F7 CTL3D_CTLCOLORDLG
0x1200 HDM_FIRST
0x1200 HDM_GETITEMCOUNT
0x1201 HDM_INSERTITEMA
0x1202 HDM_DELETEITEM
0x1203 HDM_GETITEMA
0x1204 HDM_SETITEMA
0x1205 HDM_LAYOUT
0x1206 HDM_HITTEST
0x1207 HDM_GETITEMRECT
0x1208 HDM_SETIMAGELIST
0x1209 HDM_GETIMAGELIST
0x120A HDM_INSERTITEMW
0x120B HDM_GETITEMW
0x120C HDM_SETITEMW
0x120F HDM_ORDERTOINDEX
0x1210 HDM_CREATEDRAGIMAGE
0x1211 HDM_GETORDERARRAY
0x1212 HDM_SETORDERARRAY
0x1213 HDM_SETHOTDIVIDER
0x1214 HDM_SETBITMAPMARGIN
0x1215 HDM_GETBITMAPMARGIN
0x1216 HDM_SETFILTERCHANGETIMEOUT
0x1217 HDM_EDITFILTER
0x1218 HDM_CLEARFILTER
0x1219 HDM_GETITEMDROPDOWNRECT
0x121A HDM_GETOVERFLOWRECT
0x121B HDM_GETFOCUSEDITEM
0x121C HDM_SETFOCUSEDITEM
0x1300 TCM_FIRST
0x1302 TCM_GETIMAGELIST
0x1303 TCM_SETIMAGELIST
0x1304 TCM_GETITEMCOUNT
0x1305 TCM_GETITEMA
0x1306 TCM_SETITEMA
0x1307 TCM_INSERTITEMA
0x1308 TCM_DELETEITEM
0x1309 TCM_DELETEALLITEMS
0x130A TCM_GETITEMRECT
0x130B TCM_GETCURSEL
0x130C TCM_SETCURSEL
0x130D TCM_HITTEST
0x130E TCM_SETITEMEXTRA
0x1328 TCM_ADJUSTRECT
0x1329 TCM_SETITEMSIZE
0x132A TCM_REMOVEIMAGE
0x132B TCM_SETPADDING
0x132C TCM_GETROWCOUNT
0x132D TCM_GETTOOLTIPS
0x132E TCM_SETTOOLTIPS
0x132F TCM_GETCURFOCUS
0x1330 TCM_SETCURFOCUS
0x1331 TCM_SETMINTABWIDTH
0x1332 TCM_DESELECTALL
0x1333 TCM_HIGHLIGHTITEM
0x1334 TCM_SETEXTENDEDSTYLE
0x1335 TCM_GETEXTENDEDSTYLE
0x133C TCM_GETITEMW
0x133D TCM_SETITEMW
0x133E TCM_INSERTITEMW
0x1400 PGM_FIRST
0x1401 PGM_SETCHILD
0x1402 PGM_RECALCSIZE
0x1403 PGM_FORWARDMOUSE
0x1404 PGM_SETBKCOLOR
0x1405 PGM_GETBKCOLOR
0x1406 PGM_SETBORDER
0x1407 PGM_GETBORDER
0x1408 PGM_SETPOS
0x1409 PGM_GETPOS
0x140A PGM_SETBUTTONSIZE
0x140B PGM_GETBUTTONSIZE
0x140C PGM_GETBUTTONSTATE
0x140D PGM_SETSCROLLINFO
0x2000 CCM_FIRST
0x2000 OCM_BASE
0x2001 CCM_SETBKCOLOR
0x2001 PBM_SETBKCOLOR
0x2002 CCM_SETCOLORSCHEME
0x2002 RB_SETCOLORSCHEME
0x2002 TB_SETCOLORSCHEME
0x2003 CCM_GETCOLORSCHEME
0x2003 RB_GETCOLORSCHEME
0x2003 TB_GETCOLORSCHEME
0x2004 CCM_GETDROPTARGET
0x2004 PGM_GETDROPTARGET
0x2004 RB_GETDROPTARGET
0x2005 CBEM_SETUNICODEFORMAT
0x2005 CCM_SETUNICODEFORMAT
0x2005 HDM_SETUNICODEFORMAT
0x2005 LVM_SETUNICODEFORMAT
0x2005 RB_SETUNICODEFORMAT
0x2005 SB_SETUNICODEFORMAT
0x2005 TB_SETUNICODEFORMAT
0x2005 TBM_SETUNICODEFORMAT
0x2005 TCM_SETUNICODEFORMAT
0x2005 TVM_SETUNICODEFORMAT
0x2005 UDM_SETUNICODEFORMAT
0x2006 CBEM_GETUNICODEFORMAT
0x2006 CCM_GETUNICODEFORMAT
0x2006 HDM_GETUNICODEFORMAT
0x2006 LVM_GETUNICODEFORMAT
0x2006 RB_GETUNICODEFORMAT
0x2006 SB_GETUNICODEFORMAT
0x2006 TB_GETUNICODEFORMAT
0x2006 TBM_GETUNICODEFORMAT
0x2006 TCM_GETUNICODEFORMAT
0x2006 TVM_GETUNICODEFORMAT
0x2006 UDM_GETUNICODEFORMAT
0x2007 CCM_SETVERSION
0x2008 CCM_GETVERSION
0x2009 CCM_SETNOTIFYWINDOW
0x200B CBEM_SETWINDOWTHEME
0x200B CCM_SETWINDOWTHEME
0x200B RB_SETWINDOWTHEME
0x200B TB_SETWINDOWTHEME
0x200B TTM_SETWINDOWTHEME
0x200C CCM_DPISCALE
0x2019 OCM_CTLCOLOR
0x202B OCM_DRAWITEM
0x202C OCM_MEASUREITEM
0x202D OCM_DELETEITEM
0x202E OCM_VKEYTOITEM
0x202F OCM_CHARTOITEM
0x2039 OCM_COMPAREITEM
0x204E OCM_NOTIFY
0x2111 OCM_COMMAND
0x2114 OCM_HSCROLL
0x2115 OCM_VSCROLL
0x2132 OCM_CTLCOLORMSGBOX
0x2133 OCM_CTLCOLOREDIT
0x2134 OCM_CTLCOLORLISTBOX
0x2135 OCM_CTLCOLORBTN
0x2136 OCM_CTLCOLORDLG
0x2137 OCM_CTLCOLORSCROLLBAR
0x2138 OCM_CTLCOLORSTATIC
0x2200 CCM_LAST
0x2210 OCM_PARENTNOTIFY
0x8000 WM_APP
0xCCCD WM_RASDIALEVENT |
x64dbg-development/bin/x64dbg_shell_remove.reg | Windows Registry Editor Version 5.00
[-HKEY_CLASSES_ROOT\exefile\shell\Debug with x64_dbg]
[-HKEY_CLASSES_ROOT\dllfile\shell\Debug with x64_dbg]
[-HKEY_CLASSES_ROOT\exefile\shell\Debug with x64dbg]
[-HKEY_CLASSES_ROOT\dllfile\shell\Debug with x64dbg] |
|
x64dbg-development/bin/themes/Dark/index.theme | [Icon Theme]
Name=Dark
Comment=Dark icon theme
Directories=icons
Inherits=Default
[icons]
Size=16
Type=Scalable |
|
x64dbg-development/bin/themes/Dark/style.css | /* Based on: https://github.com/radareorg/cutter/blob/48b84bfa5c7fd7c7aa8595b8f742c9d8081d09fc/src/themes/qdarkstyle/style.qss */
/* Modified for x64dbg by JustMagic: https://github.com/JustasMasiulis */
/* Use 'url(./xxxx)' for resources, it will be replaced with the right path at runtime */
ShortcutEdit[error="true"] {
color: #EF5350;
}
QTabWidget::pane {
border: 0px;
}
QTabBar::tear {
width: 0px;
border: none;
}
QToolTip {
border: 1px solid #111111;
background-color: #414141;
color: white;
padding: 0px; /*remove padding, for fix combobox tooltip.*/
/*opacity: 200;*/
}
QWidget {
color: #e0e0e0;
background-color: #212121;
selection-background-color: #89a2f6;
selection-color: #000000;
background-clip: border;
border-image: none;
border: 0px transparent black;
outline: 0;
}
/*noinspection ALL*/
QWidget:item:hover {
background-color: #414141;
color: #e0e0e0;
}
QWidget:item:selected {
background-color: #414141;
}
QCheckBox {
spacing: 5px;
outline: none;
color: #e0e0e0;
margin-bottom: 2px;
}
QCheckBox:disabled {
color: #313131;
}
QCheckBox::indicator,
QGroupBox::indicator {
width: 18px;
height: 18px;
}
QGroupBox::indicator {
margin-left: 2px;
}
QCheckBox::indicator:unchecked {
image: url(./rc/checkbox_unchecked.png);
}
QCheckBox::indicator:unchecked:hover,
QCheckBox::indicator:unchecked:focus,
QCheckBox::indicator:unchecked:pressed,
QGroupBox::indicator:unchecked:hover,
QGroupBox::indicator:unchecked:focus,
QGroupBox::indicator:unchecked:pressed {
border: none;
image: url(./rc/checkbox_unchecked_focus.png);
}
QCheckBox::indicator:checked {
image: url(./rc/checkbox_checked.png);
}
QCheckBox::indicator:checked:hover,
QCheckBox::indicator:checked:focus,
QCheckBox::indicator:checked:pressed,
QGroupBox::indicator:checked:hover,
QGroupBox::indicator:checked:focus,
QGroupBox::indicator:checked:pressed {
border: none;
image: url(./rc/checkbox_checked_focus.png);
}
QCheckBox::indicator:indeterminate {
image: url(./rc/checkbox_indeterminate.png);
}
QCheckBox::indicator:indeterminate:focus,
QCheckBox::indicator:indeterminate:hover,
QCheckBox::indicator:indeterminate:pressed {
image: url(./rc/checkbox_indeterminate_focus.png);
}
QCheckBox::indicator:checked:disabled,
QGroupBox::indicator:checked:disabled {
image: url(./rc/checkbox_checked_disabled.png);
}
QCheckBox::indicator:unchecked:disabled,
QGroupBox::indicator:unchecked:disabled {
image: url(./rc/checkbox_unchecked_disabled.png);
}
QRadioButton {
spacing: 5px;
outline: none;
color: #e0e0e0;
margin-bottom: 2px;
}
QRadioButton:disabled {
color: #2a2b2f;
}
QRadioButton::indicator {
width: 21px;
height: 21px;
}
QRadioButton::indicator:unchecked {
image: url(./rc/radio_unchecked.png);
}
QRadioButton::indicator:unchecked:hover,
QRadioButton::indicator:unchecked:focus,
QRadioButton::indicator:unchecked:pressed {
border: none;
outline: none;
image: url(./rc/radio_unchecked_focus.png);
}
QRadioButton::indicator:checked {
border: none;
outline: none;
image: url(./rc/radio_checked.png);
}
QRadioButton::indicator:checked:hover,
QRadioButton::indicator:checked:focus,
QRadioButton::indicator:checked:pressed {
border: none;
outline: none;
image: url(./rc/radio_checked_focus.png);
}
QRadioButton::indicator:checked:disabled {
outline: none;
image: url(./rc/radio_checked_disabled.png);
}
QRadioButton::indicator:unchecked:disabled {
image: url(./rc/radio_unchecked_disabled.png);
}
QMenuBar {
background-color: #212121;
color: #e0e0e0;
}
QMenuBar::item {
background: transparent;
}
QMenuBar::item:selected {
background: #414141;
border: 1px solid #212121;
}
QMenuBar::item:pressed {
border: 1px solid #212121;
background-color: #414141;
color: #e0e0e0;
margin-bottom: -1px;
padding-bottom: 1px;
}
QMenuBar::item:disabled {
color: grey;
}
QMenuBar::item:disabled:selected {
background: transparent;
color: grey;
}
QMenu {
border: 1px solid #212121;
color: #e0e0e0;
margin: 2px;
}
QMenu::icon {
margin: 5px;
}
QMenu::icon:checked { /* appearance of a 'checked' icon */
background: #383838;
border: 1px inset #878787;
position: absolute;
margin: 1px;
padding: 3px;
}
QMenu::item {
padding: 5px 30px 5px 30px;
border: 1px solid transparent;
/* reserve space for selection border */
}
QMenu::item:selected {
color: #e0e0e0;
}
QMenu::separator {
height: 2px;
background: lightblue;
margin-left: 10px;
margin-right: 5px;
}
QMenu::indicator {
width: 18px;
height: 18px;
padding-left: 4px;
}
/* non-exclusive indicator = check box style indicator
(see QActionGroup::setExclusive) */
QMenu::indicator:non-exclusive:unchecked {
image: url(./rc/checkbox_unchecked.png);
}
QMenu::indicator:non-exclusive:unchecked:selected {
image: url(./rc/checkbox_unchecked_disabled.png);
}
QMenu::indicator:non-exclusive:checked {
image: url(./rc/checkbox_checked.png);
}
QMenu::indicator:non-exclusive:checked:selected {
image: url(./rc/checkbox_checked_disabled.png);
}
/* exclusive indicator = radio button style indicator (see QActionGroup::setExclusive) */
QMenu::indicator:exclusive:unchecked {
image: url(./rc/radio_unchecked.png);
}
QMenu::indicator:exclusive:unchecked:selected {
image: url(./rc/radio_unchecked_disabled.png);
}
QMenu::indicator:exclusive:checked {
image: url(./rc/radio_checked.png);
}
QMenu::indicator:exclusive:checked:selected {
image: url(./rc/radio_checked_disabled.png);
}
QMenu::right-arrow {
margin: 5px;
image: url(./rc/right_arrow.png)
}
QWidget:disabled {
color: #454545;
background-color: #212121;
}
QAbstractItemView {
alternate-background-color: #212121;
color: #e0e0e0;
border: 1px solid #212121;
border-radius: 2px;
}
QWidget:focus,
QMenuBar:focus {
border: 1px solid #414141;
}
QTabWidget:focus,
QCheckBox:focus,
QRadioButton:focus,
QSlider:focus {
border: none;
}
QLineEdit {
background-color: #313131;
padding: 1px;
border-style: solid;
border: 1px solid #212121;
border-radius: 2px;
color: #e0e0e0;
}
QAbstractItemView QLineEdit {
padding: 0;
}
QGroupBox {
border: 1px solid #212121;
border-radius: 2px;
margin-top: 20px;
}
QGroupBox::title {
subcontrol-origin: margin;
subcontrol-position: top center;
padding-left: 5px;
padding-right: 5px;
padding-top: 5px;
}
QAbstractScrollArea {
border-radius: 2px;
border: 1px solid #212121;
background-color: transparent;
}
QScrollBar:horizontal {
height: 18px;
margin: 4px 16px 4px 16px;
border: 0;
border-radius: 4px;
background-color: #414141;
}
QScrollBar::handle:horizontal {
background-color: #717171;
min-width: 5px;
border-radius: 4px;
}
QScrollBar::add-line:horizontal {
margin: 0px 3px 0px 3px;
border-image: url(./rc/right_arrow_disabled.png);
width: 10px;
height: 10px;
subcontrol-position: right;
subcontrol-origin: margin;
}
QScrollBar::sub-line:horizontal {
margin: 0px 3px 0px 3px;
border-image: url(./rc/left_arrow_disabled.png);
height: 10px;
width: 10px;
subcontrol-position: left;
subcontrol-origin: margin;
}
QScrollBar::add-line:horizontal:hover,
QScrollBar::add-line:horizontal:on {
border-image: url(./rc/right_arrow.png);
height: 10px;
width: 10px;
subcontrol-position: right;
subcontrol-origin: margin;
}
QScrollBar::sub-line:horizontal:hover,
QScrollBar::sub-line:horizontal:on {
border-image: url(./rc/left_arrow.png);
height: 10px;
width: 10px;
subcontrol-position: left;
subcontrol-origin: margin;
}
QScrollBar::up-arrow:horizontal,
QScrollBar::down-arrow:horizontal {
background: none;
}
QScrollBar::add-page:horizontal,
QScrollBar::sub-page:horizontal {
background: none;
}
QScrollBar:vertical {
background-color: #414141;
width: 18px;
margin: 16px 4px 16px 4px;
border-radius: 4px;
}
QScrollBar::handle:vertical {
background-color: #717171;
min-height: 24px;
border-radius: 4px;
}
QScrollBar::sub-line:vertical {
margin: 3px 0px 3px 0px;
border-image: url(./rc/up_arrow_disabled.png);
height: 10px;
width: 10px;
subcontrol-position: top;
subcontrol-origin: margin;
}
QScrollBar::add-line:vertical {
margin: 3px 0px 3px 0px;
border-image: url(./rc/down_arrow_disabled.png);
height: 10px;
width: 10px;
subcontrol-position: bottom;
subcontrol-origin: margin;
}
QScrollBar::sub-line:vertical:hover,
QScrollBar::sub-line:vertical:on {
border-image: url(./rc/up_arrow.png);
height: 10px;
width: 10px;
subcontrol-position: top;
subcontrol-origin: margin;
}
QScrollBar::add-line:vertical:hover,
QScrollBar::add-line:vertical:on {
border-image: url(./rc/down_arrow.png);
height: 10px;
width: 10px;
subcontrol-position: bottom;
subcontrol-origin: margin;
}
QScrollBar::up-arrow:vertical,
QScrollBar::down-arrow:vertical {
background: none;
}
QScrollBar::add-page:vertical,
QScrollBar::sub-page:vertical {
background: none;
}
QTextEdit {
background-color: #313131;
color: #e0e0e0;
border: 1px solid #212121;
}
QPlainTextEdit {
background-color: #313131;
;
color: #e0e0e0;
border-radius: 2px;
border: 1px solid #212121;
}
QHeaderView::section {
background-color: #2a2b2f;
color: #e0e0e0;
padding: 5px;
border: 1px solid #212121;
}
QSizeGrip {
image: url(./rc/sizegrip.png);
width: 12px;
height: 12px;
}
QMainWindow::separator {
background-color: #212121;
color: white;
padding-left: 4px;
spacing: 2px;
/*border: 1px dashed #2a2b2f;*/
}
QMainWindow::separator:hover {
background-color: #787876;
color: white;
padding-left: 4px;
border: 1px solid #212121;
spacing: 2px;
}
QMenu::separator {
height: 1px;
background-color: #2a2b2f;
color: white;
padding-left: 4px;
margin-left: 10px;
margin-right: 5px;
}
QFrame {
border: 1px solid #212121;
}
QFrame[frameShape="0"] {
border: 1px transparent #2a2b2f;
}
QStackedWidget {
border: 1px transparent black;
}
QToolBar {
border: 1px transparent #2a2b2f;
background: 1px solid #212121;
font-weight: bold;
}
QToolBar::handle:horizontal {
image: url(./rc/Hmovetoolbar.png);
}
QToolBar::handle:vertical {
image: url(./rc/Vmovetoolbar.png);
}
QToolBar::separator:horizontal {
image: url(./rc/Hsepartoolbar.png);
}
QToolBar::separator:vertical {
image: url(./rc/Vsepartoolbar.png);
}
QToolButton#qt_toolbar_ext_button {
background: #58595a
}
QPushButton {
color: #e0e0e0;
background-color: #212121;
border-width: 1px;
border-color: #2a2b2f;
border-style: solid;
padding: 5px;
border-radius: 2px;
outline: none;
}
QPushButton:disabled {
background-color: #212121;
border-width: 1px;
border-color: #454545;
border-style: solid;
padding-top: 5px;
padding-bottom: 5px;
padding-left: 10px;
padding-right: 10px;
border-radius: 2px;
color: #454545;
}
QPushButton:focus {
background-color: #414141;
color: white;
}
QPushButton:pressed {
background-color: #414141;
padding-top: -15px;
padding-bottom: -17px;
}
QComboBox {
selection-background-color: #89a2f6;
selection-color: #000000;
border-style: solid;
border: 1px solid #212121;
border-radius: 2px;
padding: 5px;
min-width: 75px;
}
QPushButton:checked {
background-color: #2a2b2f;
border-color: #2a2b2f;
}
QComboBox:hover,
QPushButton:hover,
QAbstractSpinBox:hover,
QLineEdit:hover,
QTextEdit:hover,
QPlainTextEdit:hover,
QAbstractView:hover,
QTreeView:hover {
border: 1px solid #414141;
color: #e0e0e0;
}
QComboBox:on {
padding-top: 3px;
padding-left: 4px;
selection-background-color: #4a4a4a;
}
QComboBox QAbstractItemView {
background-color: #313131;
border-radius: 2px;
border: 1px solid #212121;
selection-background-color: #414141;
}
QComboBox::drop-down {
subcontrol-origin: padding;
subcontrol-position: top right;
width: 15px;
border-left-width: 0px;
border-left-color: darkgray;
border-left-style: solid;
border-top-right-radius: 3px;
border-bottom-right-radius: 3px;
}
QComboBox::down-arrow {
image: url(./rc/down_arrow_disabled.png);
}
QComboBox::down-arrow:on,
QComboBox::down-arrow:hover,
QComboBox::down-arrow:focus {
image: url(./rc/down_arrow.png);
}
QAbstractSpinBox {
padding: 5px;
border: 0;
background-color: #313131;
color: #e0e0e0;
border-radius: 2px;
min-width: 75px;
}
QAbstractSpinBox:up-button {
background-color: transparent;
subcontrol-origin: border;
subcontrol-position: center right;
}
QAbstractSpinBox:down-button {
background-color: transparent;
subcontrol-origin: border;
subcontrol-position: center left;
}
QAbstractSpinBox::up-arrow,
QAbstractSpinBox::up-arrow:disabled,
QAbstractSpinBox::up-arrow:off {
image: url(./rc/up_arrow_disabled.png);
width: 10px;
height: 10px;
}
QAbstractSpinBox::up-arrow:hover {
image: url(./rc/up_arrow.png);
}
QAbstractSpinBox::down-arrow,
QAbstractSpinBox::down-arrow:disabled,
QAbstractSpinBox::down-arrow:off {
image: url(./rc/down_arrow_disabled.png);
width: 10px;
height: 10px;
}
QAbstractSpinBox::down-arrow:hover {
image: url(./rc/down_arrow.png);
}
QLabel {
border: 0px solid black;
}
QTabWidget {
border: 0px transparent black;
}
QTabWidget::pane {
border: 1px solid #212121;
padding: 1px;
margin: 0px;
}
QTabWidget::tab-bar {
/* left: 5px; move to the right by 5px */
}
QTabBar {
qproperty-drawBase: 0;
}
QTabBar:focus {
}
QTabBar::close-button {
image: url(./rc/close.png);
background: transparent;
}
QTabBar::close-button:hover {
image: url(./rc/close-hover.png);
background: transparent;
}
QTabBar::close-button:pressed {
image: url(./rc/close-pressed.png);
background: transparent;
}
QTabBar::tab {
color: #e0e0e0;
background-color: #313131;
padding: 3px;
/*min-width: 50px;*/
padding: 4px 10px;
border: 1px solid #212121;
border-top-left-radius: 3px;
border-top-right-radius: 3px;
}
QTabBar::tab:selected {
background-color: #414141;
color: #89A2F6;
border-bottom: 2px solid #89A2F6;
}
QTabBar::tab:hover {
background-color: #414141;
}
/* Attempt at fixing an ugly bug: https://stackoverflow.com/a/55097717/1806760 */
QTabBar QToolButton {
border-width: 1px;
border-color: #515151;
border-style: solid;
border-radius: 2px;
background: #212121;
padding: 0px;
margin: 0px;
margin-top: 2px;
margin-bottom: 2px;
}
QTabBar QToolButton::hover {
background: #212121;
border: 1px solid #717171;
}
QTabBar::scroller {
width: 15px;
}
QTabBar QToolButton::right-arrow:enabled {
image: url(./rc/right_arrow.png);
}
QTabBar QToolButton::left-arrow:enabled {
image: url(./rc/left_arrow.png);
}
QTabBar QToolButton::right-arrow:disabled {
image: url(./rc/right_arrow_disabled.png);
}
QTabBar QToolButton::left-arrow:disabled {
image: url(./rc/left_arrow_disabled.png);
}
QDockWidget {
background: #212121;
border: 1px solid #212121;
titlebar-close-icon: url(./rc/close.png);
titlebar-normal-icon: url(./rc/undock.png);
}
QDockWidget::close-button,
QDockWidget::float-button {
border: 1px solid transparent;
border-radius: 2px;
background: transparent;
}
QDockWidget::close-button:hover,
QDockWidget::float-button:hover {
background: rgba(255, 255, 255, 10);
}
QDockWidget::close-button:pressed,
QDockWidget::float-button:pressed {
padding: 1px -1px -1px 1px;
background: rgba(255, 255, 255, 10);
}
QTreeView,
QListView {
background-color: #313131;
}
QTreeView:branch:selected,
QTreeView:branch:hover {
background: url(./rc/transparent.png);
}
QTreeView::branch:has-siblings:!adjoins-item {
border-image: url(./rc/transparent.png);
}
QTreeView::branch:has-siblings:adjoins-item {
border-image: url(./rc/transparent.png);
}
QTreeView::branch:!has-children:!has-siblings:adjoins-item {
border-image: url(./rc/transparent.png);
}
QTreeView::branch:has-children:!has-siblings:closed,
QTreeView::branch:closed:has-children:has-siblings {
image: url(./rc/branch_closed.png);
}
QTreeView::branch:open:has-children:!has-siblings,
QTreeView::branch:open:has-children:has-siblings {
image: url(./rc/branch_open.png);
}
QTreeView::branch:has-children:!has-siblings:closed:hover,
QTreeView::branch:closed:has-children:has-siblings:hover {
image: url(./rc/branch_closed-on.png);
}
QTreeView::branch:open:has-children:!has-siblings:hover,
QTreeView::branch:open:has-children:has-siblings:hover {
image: url(./rc/branch_open-on.png);
}
QListView::item:!selected:hover,
QTreeView::item:!selected:hover {
background: #414141;
outline: 0;
color: #e0e0e0
}
QListView::item:selected:hover,
QTreeView::item:selected:hover {
background: #414141;
color: #e0e0e0;
}
QTreeView::indicator:checked,
QListView::indicator:checked {
image: url(./rc/checkbox_checked.png);
}
QTreeView::indicator:unchecked,
QListView::indicator:unchecked {
image: url(./rc/checkbox_unchecked.png);
}
QTreeView::indicator:checked:hover,
QTreeView::indicator:checked:focus,
QTreeView::indicator:checked:pressed,
QListView::indicator:checked:hover,
QListView::indicator:checked:focus,
QListView::indicator:checked:pressed {
image: url(./rc/checkbox_checked_focus.png);
}
QTreeView::indicator:unchecked:hover,
QTreeView::indicator:unchecked:focus,
QTreeView::indicator:unchecked:pressed,
QListView::indicator:unchecked:hover,
QListView::indicator:unchecked:focus,
QListView::indicator:unchecked:pressed {
image: url(./rc/checkbox_unchecked_focus.png);
}
QSlider::groove:horizontal {
border: 1px solid #212121;
height: 4px;
background: #2a2b2f;
margin: 0px;
border-radius: 2px;
}
QSlider::handle:horizontal {
background: #313131;
border: 1px solid #212121;
width: 16px;
height: 16px;
margin: -8px 0;
border-radius: 9px;
}
QSlider::groove:vertical {
border: 1px solid #212121;
width: 4px;
background: #2a2b2f;
margin: 0px;
border-radius: 3px;
}
QSlider::handle:vertical {
background: #313131;
border: 1px solid #212121;
width: 16px;
height: 16px;
margin: 0 -8px;
border-radius: 9px;
}
QToolButton {
background-color: transparent;
border: 1px transparent #2a2b2f;
border-radius: 2px;
margin: 3px;
padding: 3px;
}
QToolButton:hover {
background-color: transparent;
border: 1px solid #414141;
}
QToolButton:checked,
QToolButton:pressed {
background-color: #414141;
border: 1px solid #414141;
}
QHeaderView {
border-radius: 0px;
}
QListView::item:pressed,
QTreeView::item:pressed {
background: #414141;
color: #e0e0e0;
}
QTreeView::item:selected:active,
QListView::item:selected:active {
background: #414141;
color: #e0e0e0;
}
QHeaderView {
background-color: #212121;
margin: 0px;
padding: 0px;
}
QHeaderView::section {
background-color: #313131;
color: #e0e0e0;
padding: 0 3px 0 3px;
border: none;
text-align: center;
}
QHeaderView::section::vertical::first,
QHeaderView::section::vertical::only-one {
border-top: 1px solid #313131;
}
QHeaderView::section::vertical {
border-top: transparent;
}
QHeaderView::section::horizontal::first,
QHeaderView::section::horizontal::only-one {
border-left: 1px solid #313131;
}
QHeaderView::section::horizontal {
border-left: transparent;
}
QHeaderView::section:checked {
color: white;
background-color: #414141;
}
QHeaderView::down-arrow {
image: url(./rc/down_arrow.png);
}
QHeaderView::up-arrow {
image: url(./rc/up_arrow.png);
}
QStatusBar::item {
border: none;
}
QSplitter::handle {
background-color: #515151;
}
QSplitter::handle:hover {
background-color: #808080;
}
QProgressBar {
border: 1px solid #212121;
border-radius: 4px;
text-align: center;
}
QProgressBar::chunk {
background-color: #89A2F6;
}
/* QStatusBar == DebugStatusLabel, LogStatusLabel, TimeWastedCounter */
/*QStatusBar QLabel {
background-color: #c0c0c0;
}*/
QStatusBar QFrame {
qproperty-frameShape: Panel;
qproperty-frameShadow: Sunken;
}
QStatusBar::item {
border: none;
}
/*QStatusBar {
background-color: #c0c0c0;
}*/
DebugStatusLabel[state="initialized"] {
color: #00dd00;
/*background-color: #c0c0c0;*/
}
DebugStatusLabel[state="paused"] {
color: #828229;
/*background-color: #ffff00;*/
}
DebugStatusLabel[state="running"] {
color: #000000;
/*background-color: #c0c0c0;*/
}
DebugStatusLabel[state="stopped"] {
color: #ff0000;
/*background-color: #c0c0c0;*/
}
/*QPushButton#AbstractTableViewHeader {
background-color: rgb(192, 192, 192);
border-style: outset;
border-width: 2px;
border-color: rgb(128, 128, 128);
}*/
QPushButton#AbstractTableViewHeader QPushButton:pressed {
background-color: rgb(192, 192, 192);
border-style: inset;
}
ShortcutEdit {
color: #222222;
}
ShortcutEdit[error="true"] {
color: #dd0000;
}
QTabWidget::pane {
border: 0px;
}
QTabBar::tear {
width: 0px;
border: none;
} |
|
INI Configuration | x64dbg-development/bin/themes/Dark/style.ini | [Colors]
AbstractTableViewBackgroundColor=#212121
AbstractTableViewHeaderTextColor=#E0E0E0
AbstractTableViewSelectionColor=#414141
AbstractTableViewSeparatorColor=#717171
AbstractTableViewTextColor=#E0E0E0
BackgroundFlickerColor=#EF5350
BreakpointSummaryKeywordColor=#89A2F6
BreakpointSummaryParenColor=#E0E0E0
BreakpointSummaryStringColor=#B794F6
CustomColor0=#212121
CustomColor1=#313131
CustomColor10=#F55F86
CustomColor11=#F88478
CustomColor12=#E0E0E0
CustomColor13=#414141
CustomColor14=#5F5F5F
CustomColor15=#717171
CustomColor2=#89A2F6
CustomColor3=#B3F575
CustomColor4=#B794F6
CustomColor5=#E1EA76
CustomColor6=#E6E976
CustomColor7=#111111
CustomColor8=#EF5350
CustomColor9=#969600
CustomColorCount=10
DisassemblyAddressBackgroundColor=#XXXXXX
DisassemblyAddressColor=#A0A0A0
DisassemblyAutoCommentBackgroundColor=#XXXXXX
DisassemblyAutoCommentColor=#A0A0A0
DisassemblyBackgroundColor=#212121
DisassemblyBookmarkBackgroundColor=#E6E976
DisassemblyBookmarkColor=#212121
DisassemblyBreakpointBackgroundColor=#EF5350
DisassemblyBreakpointColor=#000000
DisassemblyByte00BackgroundColor=#XXXXXX
DisassemblyByte00Color=#E0E0E0
DisassemblyByte7FBackgroundColor=#XXXXXX
DisassemblyByte7FColor=#E0E0E0
DisassemblyByteFFBackgroundColor=#XXXXXX
DisassemblyByteFFColor=#E0E0E0
DisassemblyByteIsPrintBackgroundColor=#XXXXXX
DisassemblyByteIsPrintColor=#E0E0E0
DisassemblyBytesBackgroundColor=#XXXXXX
DisassemblyBytesColor=#E0E0E0
DisassemblyCipBackgroundColor=#93EE62
DisassemblyCipColor=#000000
DisassemblyCommentBackgroundColor=#XXXXXX
DisassemblyCommentColor=#E0E0E0
DisassemblyConditionalJumpLineFalseColor=#808080
DisassemblyConditionalJumpLineTrueColor=#AA0000
DisassemblyFunctionColor=#F88478
DisassemblyHardwareBreakpointBackgroundColor=#XXXXXX
DisassemblyHardwareBreakpointColor=#E6E976
DisassemblyLabelBackgroundColor=#XXXXXX
DisassemblyLabelColor=#B794F6
DisassemblyLoopColor=#F88478
DisassemblyMnemonicBriefBackgroundColor=#XXXXXX
DisassemblyMnemonicBriefColor=#A0A0A0
DisassemblyModifiedBytesBackgroundColor=#XXXXXX
DisassemblyModifiedBytesColor=#EF5350
DisassemblyRelocationUnderlineColor=#EF5350
DisassemblyRestoredBytesBackgroundColor=#XXXXXX
DisassemblyRestoredBytesColor=#B3F575
DisassemblySelectedAddressBackgroundColor=#XXXXXX
DisassemblySelectedAddressColor=#E0E0E0
DisassemblySelectionColor=#414141
DisassemblyTracedBackgroundColor=#2C2C38
DisassemblyUnconditionalJumpLineColor=#A0A0A0
GraphBackgroundColor=#212121
GraphBreakpointColor=#EF5350
GraphBrfalseColor=#EF5350
GraphBrtrueColor=#88B857
GraphCipColor=#A6F93E
GraphCurrentShadowColor=#B3F575
GraphDisabledBreakpointColor=#C54441
GraphIndirectcallShadowColor=#89A2F6
GraphJmpColor=#88B857
GraphNodeBackgroundColor=#XXXXXX
GraphNodeColor=#909090
GraphRetShadowColor=#913230
HexDumpAddressBackgroundColor=#XXXXXX
HexDumpAddressColor=#A0A0A0
HexDumpBackgroundColor=#212121
HexDumpByte00BackgroundColor=#XXXXXX
HexDumpByte00Color=#E0E0E0
HexDumpByte7FBackgroundColor=#XXXXXX
HexDumpByte7FColor=#E0E0E0
HexDumpByteFFBackgroundColor=#XXXXXX
HexDumpByteFFColor=#E0E0E0
HexDumpByteIsPrintBackgroundColor=#XXXXXX
HexDumpByteIsPrintColor=#E0E0E0
HexDumpLabelBackgroundColor=#XXXXXX
HexDumpLabelColor=#B794F6
HexDumpModifiedBytesBackgroundColor=#XXXXXX
HexDumpModifiedBytesColor=#EF5350
HexDumpRestoredBytesBackgroundColor=#XXXXXX
HexDumpRestoredBytesColor=#A6F93E
HexDumpSelectionColor=#414141
HexDumpSystemModuleCodePointerHighlightColor=#EF5350
HexDumpSystemModuleDataPointerHighlightColor=#B794F6
HexDumpTextColor=#E0E0E0
HexDumpUnknownCodePointerHighlightColor=#0000FF
HexDumpUnknownDataPointerHighlightColor=#89A2F6
HexDumpUserModuleCodePointerHighlightColor=#00FF00
HexDumpUserModuleDataPointerHighlightColor=#008000
HexEditBackgroundColor=#212121
HexEditSelectionColor=#414141
HexEditTextColor=#E0E0E0
HexEditWildcardColor=#C60000
InstructionAddressBackgroundColor=#XXXXXX
InstructionAddressColor=#F88478
InstructionCallBackgroundColor=#XXXXXX
InstructionCallColor=#F55F86
InstructionCommaBackgroundColor=#XXXXXX
InstructionCommaColor=#E0E0E0
InstructionConditionalJumpBackgroundColor=#XXXXXX
InstructionConditionalJumpColor=#F55F86
InstructionFarBackgroundColor=#XXXXXX
InstructionFarColor=#F55F86
InstructionFpuRegisterBackgroundColor=#XXXXXX
InstructionFpuRegisterColor=#B794F6
InstructionGeneralRegisterBackgroundColor=#XXXXXX
InstructionGeneralRegisterColor=#B794F6
InstructionHighlightBackgroundColor=#e6e976
InstructionHighlightColor=#000000
InstructionInt3BackgroundColor=#XXXXXX
InstructionInt3Color=#5F5F5F
InstructionMemoryBaseRegisterBackgroundColor=#XXXXXX
InstructionMemoryBaseRegisterColor=#B794F6
InstructionMemoryBracketsBackgroundColor=#XXXXXX
InstructionMemoryBracketsColor=#E0E0E0
InstructionMemoryIndexRegisterBackgroundColor=#XXXXXX
InstructionMemoryIndexRegisterColor=#B794F6
InstructionMemoryOperatorBackgroundColor=#XXXXXX
InstructionMemoryOperatorColor=#E0E0E0
InstructionMemoryScaleBackgroundColor=#XXXXXX
InstructionMemoryScaleColor=#F88478
InstructionMemorySegmentBackgroundColor=#XXXXXX
InstructionMemorySegmentColor=#B794F6
InstructionMemorySizeBackgroundColor=#XXXXXX
InstructionMemorySizeColor=#E0E0E0
InstructionMemoryStackBracketsBackgroundColor=#XXXXXX
InstructionMemoryStackBracketsColor=#E0E0E0
InstructionMmxRegisterBackgroundColor=#XXXXXX
InstructionMmxRegisterColor=#B794F6
InstructionMnemonicBackgroundColor=#XXXXXX
InstructionMnemonicColor=#89A2F6
InstructionNopBackgroundColor=#XXXXXX
InstructionNopColor=#A8A8A8
InstructionPrefixBackgroundColor=#XXXXXX
InstructionPrefixColor=#89A2F6
InstructionPushPopBackgroundColor=#XXXXXX
InstructionPushPopColor=#89A2F6
InstructionRetBackgroundColor=#XXXXXX
InstructionRetColor=#F55F86
InstructionSseRegisterBackgroundColor=#XXXXXX
InstructionSseRegisterColor=#000080
InstructionUncategorizedBackgroundColor=#XXXXXX
InstructionUncategorizedColor=#E0E0E0
InstructionUnconditionalJumpBackgroundColor=#XXXXXX
InstructionUnconditionalJumpColor=#F55F86
InstructionUnusualBackgroundColor=#ef5350
InstructionUnusualColor=#000000
InstructionValueBackgroundColor=#XXXXXX
InstructionValueColor=#F88478
InstructionXmmRegisterBackgroundColor=#XXXXXX
InstructionXmmRegisterColor=#B794F6
InstructionYmmRegisterBackgroundColor=#XXXXXX
InstructionYmmRegisterColor=#B794F6
InstructionZmmRegisterBackgroundColor=#XXXXXX
InstructionZmmRegisterColor=#B794F6
LogBackgroundColor=#212121
LogColor=#E0E0E0
LogLinkBackgroundColor=#XXXXXX
LogLinkColor=#89A2F6
MemoryMapBreakpointBackgroundColor=#EF5350
MemoryMapBreakpointColor=#212121
MemoryMapCipBackgroundColor=#212121
MemoryMapCipColor=#A6F93E
MemoryMapSectionTextColor=#89A2F6
PatchRelocatedByteHighlightColor=#EF5350
RegistersArgumentLabelColor=#89A2F6
RegistersBackgroundColor=#212121
RegistersColor=#E0E0E0
RegistersExtraInfoColor=#F55F86
RegistersHighlightReadColor=#A6F93E
RegistersHighlightReadWriteColor=#EF5350
RegistersHighlightWriteColor=#E1EA76
RegistersLabelColor=#B794F6
RegistersModifiedColor=#F88478
RegistersSelectionColor=#414141
SearchListViewHighlightBackgroundColor=#XXXXXX
SearchListViewHighlightColor=#C60000
SideBarBackgroundColor=#212121
SideBarBulletBookmarkColor=#E1EA76
SideBarBulletBreakpointColor=#EF5350
SideBarBulletColor=#414141
SideBarBulletDisabledBreakpointColor=#AA3A38
SideBarCheckBoxBackColor=#414141
SideBarCheckBoxForeColor=#E0E0E0
SideBarCipLabelBackgroundColor=#414141
SideBarCipLabelColor=#93EE62
SideBarConditionalJumpLineFalseBackwardsColor=#808080
SideBarConditionalJumpLineFalseColor=#808080
SideBarConditionalJumpLineTrueBackwardsColor=#A0A0A0
SideBarConditionalJumpLineTrueColor=#A0A0A0
SideBarUnconditionalJumpLineFalseBackwardsColor=#808080
SideBarUnconditionalJumpLineFalseColor=#808080
SideBarUnconditionalJumpLineTrueBackwardsColor=#A0A0A0
SideBarUnconditionalJumpLineTrueColor=#A0A0A0
StackAddressBackgroundColor=#XXXXXX
StackAddressColor=#A0A0A0
StackBackgroundColor=#212121
StackCspBackgroundColor=#XXXXXX
StackCspColor=#A6F93E
StackFrameColor=#F88478
StackFrameSystemColor=#F88478
StackInactiveTextColor=#A0A0A0
StackLabelBackgroundColor=#XXXXXX
StackLabelColor=#B794F6
StackReturnToColor=#F55F86
StackSEHChainColor=#F55F86
StackSelectedAddressBackgroundColor=#XXXXXX
StackSelectedAddressColor=#E0E0E0
StackSelectionColor=#414141
StackTextColor=#E0E0E0
StructAlternateBackgroundColor=#313131
StructBackgroundColor=#212121
StructTextColor=#E0E0E0
SymbolUserTextColor=#E0E0E0
SymbolSystemTextColor=#E0E0E0
SymbolLoadedTextColor=#E0E0E0
SymbolLoadingTextColor=#E1EA76
SymbolUnloadedTextColor=#A0A0A0
ThreadCurrentBackgroundColor=#C24000
ThreadCurrentColor=#FFFFFF
WatchTriggeredBackgroundColor=#XXXXXX
WatchTriggeredColor=#EF5350
LinkColor=#89A2F6
DarkTitleBar=1 |
x64dbg-development/hooks/AStyleHelper.exe.config | <?xml version="1.0"?>
<configuration>
<configSections>
<sectionGroup name="applicationSettings" type="System.Configuration.ApplicationSettingsGroup, System, Version=4.0.0.0, Culture=neutral, PublicKeyToken=b77a5c561934e089" >
<section name="AStyleHelper.Properties.Settings" type="System.Configuration.ClientSettingsSection, System, Version=4.0.0.0, Culture=neutral, PublicKeyToken=b77a5c561934e089" requirePermission="false" />
</sectionGroup>
</configSections>
<startup><supportedRuntime version="v4.0" sku=".NETFramework,Version=v4.0"/></startup>
<applicationSettings>
<AStyleHelper.Properties.Settings>
<setting name="Pattern" serializeAs="String">
<value>*.c;*.h;*.cpp;*.hpp</value>
</setting>
<setting name="Options" serializeAs="String">
<value>style=allman, convert-tabs, align-pointer=type, align-reference=middle, indent=spaces, indent-namespaces, indent-col1-comments, pad-oper, unpad-paren, keep-one-line-blocks, close-templates</value>
</setting>
<setting name="Ignore" serializeAs="String">
<value />
</setting>
<setting name="License" serializeAs="String">
<value />
</setting>
</AStyleHelper.Properties.Settings>
</applicationSettings>
</configuration> |
|
x64dbg-development/hooks/pre-commit | #!/bin/sh
#
# Simple script to auto-format every source file before committing.
#
#check if the formatter is present
if [ ! -f ./hooks/AStyleHelper.exe ]; then
echo "AStyleHelper not found!"
exit 0
fi
#format the code
"./hooks/AStyleHelper.exe" Silent
#exit when nothing needs to be done
if [ $? == 0 ]; then
exit 0
fi
#stage the formatted files (when staged in this commit)
gitFiles=$(git diff-index --name-only --cached HEAD)
if [[ -n "${gitFiles}" ]]; then
for fname in $gitFiles; do
git add --all -- "${fname}"
done
fi
#cancel commit if the changes were undone by the formatting
gitFiles=$(git diff-index --name-only --cached HEAD)
if [ -z "$gitFiles" ]; then
"./hooks/AStyleHelper.exe" "After formatting, no files were staged..."
exit 1
fi |
|
Markdown | x64dbg-development/hooks/README.md | # Hooks
This contains two binaries `AStyleHelper.exe` and `AStyle.dll` to format any code before you commit.
If you are unsure about the integrity of the files, don't hesitate to contact me (mrexodia). The source code is available [here](https://github.com/mrexodia/AStyleHelper). The version of `AStyle.dll` is compiled from `AStyle_2.06_windows.zip` which came from [Sourceforge](https://sourceforge.net/projects/astyle/files/astyle/astyle%202.06/AStyle_2.06_windows.zip/download). |
C/C++ | x64dbg-development/src/dbg_assert.h | /**
* Code originally from:
*
* (c) 2015 Alexandro Sanchez Bach. All rights reserved.
* https://github.com/AlexAltea/nucleus/blob/9103d7eb52cc861cb6e317f0007246bd03d663a2/nucleus/assert.h
* https://github.com/AlexAltea/nucleus/blob/9103d7eb52cc861cb6e317f0007246bd03d663a2/LICENSE
* Released under GPL v2 license. Read LICENSE for more details.
*
*/
#pragma once
#include <cassert>
// Count arguments
#define __DBG_ARGUMENT_EXPAND(x) x
#define __DBG_ARGUMENT_COUNT(...) \
__DBG_ARGUMENT_EXPAND(__DBG_ARGUMENT_EXTRACT(__VA_ARGS__, 8, 7, 6, 5, 4, 3, 2, 1, 0))
#define __DBG_ARGUMENT_EXTRACT(a1, a2, a3, a4, a5, a6, a7, a8, N, ...) N
// Dispatching macros
#define __DBG_MACRO_DISPATCH(function, ...) \
__DBG_MACRO_SELECT(function, __DBG_ARGUMENT_COUNT(__VA_ARGS__))
#define __DBG_MACRO_SELECT(function, argc) \
__DBG_MACRO_CONCAT(function, argc)
#define __DBG_MACRO_CONCAT(a, b) a##b
// Trigger an exception if the debugger is not currently active
#define ASSERT_DEBUGGING(message) ASSERT_TRUE(IsFileBeingDebugged(), message)
// Trigger an exception if expression is false
#define ASSERT_TRUE(...) \
__DBG_MACRO_DISPATCH(ASSERT_TRUE, __VA_ARGS__)(__VA_ARGS__)
#define ASSERT_TRUE1(expr) assert(expr)
#define ASSERT_TRUE2(expr, message) assert((expr) && (message))
// Trigger an exception if expression is true
#define ASSERT_FALSE(...) \
__DBG_MACRO_DISPATCH(ASSERT_FALSE, __VA_ARGS__)(__VA_ARGS__)
#define ASSERT_FALSE1(expr) assert(!(expr))
#define ASSERT_FALSE2(expr, message) assert(!(expr) && (message))
// Trigger an exception if expression is zero
#define ASSERT_ZERO(...) \
__DBG_MACRO_DISPATCH(ASSERT_ZERO, __VA_ARGS__)(__VA_ARGS__)
#define ASSERT_ZERO1(expr) assert(expr)
#define ASSERT_ZERO2(expr, message) assert(((expr) == 0) && (message))
// Trigger an exception if expression is non-zero
#define ASSERT_NONZERO(...) \
__DBG_MACRO_DISPATCH(ASSERT_TRUE, __VA_ARGS__)(__VA_ARGS__)
#define ASSERT_NONZERO1(expr) ASSERT_NONZERO(expr)
#define ASSERT_NONZERO2(expr, message) assert(((expr) != 0) && (message))
// Trigger an exception if expression is a nullptr
#define ASSERT_NULL(...) \
__DBG_MACRO_DISPATCH(ASSERT_NULL, __VA_ARGS__)(__VA_ARGS__)
#define ASSERT_NULL1(expr) assert(expr)
#define ASSERT_NULL2(expr, message) assert(((expr) == nullptr) && (message))
// Trigger an exception if expression is not a nullptr
#define ASSERT_NONNULL(...) \
__DBG_MACRO_DISPATCH(ASSERT_NONNULL, __VA_ARGS__)(__VA_ARGS__)
#define ASSERT_NONNULL1(expr) assert(expr)
#define ASSERT_NONNULL2(expr, message) assert(((expr) != nullptr) && (message))
// Trigger an exception
#define ASSERT_ALWAYS(...) \
__DBG_MACRO_DISPATCH(ASSERT_ALWAYS, __VA_ARGS__)(__VA_ARGS__)
#define ASSERT_ALWAYS0(...) assert(0)
#define ASSERT_ALWAYS1(message) assert(0 && (message)) |
C/C++ | x64dbg-development/src/dbg_types.h | #ifndef _DBG_TYPES_H_
#define _DBG_TYPES_H_
/***************************************************************/
//
// This file declares common types to be used
// throughout the project. Originally duint, int_t,
// or size_t were used to represent pointers and addresses.
//
// The purpose is to use a single type as the representation.
//
/***************************************************************/
#undef COMPILE_X64
#undef COMPILE_X32
#ifdef _WIN64
#define COMPILE_X64 1 // Program is being compiled as 64-bit
#else
#define COMPILE_X32 1 // Program is being compiled as 32-bit
#endif // _WIN64
//
// Define types
//
#ifdef COMPILE_X64
typedef unsigned long long duint;
typedef signed long long dsint;
#else
typedef unsigned long __w64 duint;
typedef signed long __w64 dsint;
#endif // COMPILE_X64
typedef short int16;
typedef unsigned short uint16;
typedef int int32;
typedef unsigned int uint32;
typedef long long int64;
typedef unsigned long long uint64;
typedef unsigned char byte_t;
#endif //_DBG_TYPES_H_ |
x64dbg-development/src/x64dbg_translations.pro | #-------------------------------------------------
# This file is for lupdate to update the translations only.
# DO NOT compile this file.
# If you add new files in the project, remember to add them here too.
#-------------------------------------------------
SOURCES += \
gui/Src/Gui/AppearanceDialog.cpp \
gui/Src/Gui/AssembleDialog.cpp \
gui/Src/Gui/AttachDialog.cpp \
gui/Src/Gui/BreakpointsView.cpp \
gui/Src/Gui/BrowseDialog.cpp \
gui/Src/Gui/CalculatorDialog.cpp \
gui/Src/Gui/CallStackView.cpp \
gui/Src/Gui/CloseDialog.cpp \
gui/Src/Gui/CodepageSelectionDialog.cpp \
gui/Src/Gui/ColumnReorderDialog.cpp \
gui/Src/Gui/CommandLineEdit.cpp \
gui/Src/Gui/CPUArgumentWidget.cpp \
gui/Src/Gui/CPUDisassembly.cpp \
gui/Src/Gui/CPUDump.cpp \
gui/Src/Gui/CPUInfoBox.cpp \
gui/Src/Gui/CPUMultiDump.cpp \
gui/Src/Gui/CPUSideBar.cpp \
gui/Src/Gui/CPUStack.cpp \
gui/Src/Gui/CPUWidget.cpp \
gui/Src/Gui/DataCopyDialog.cpp \
gui/Src/Gui/DisassemblerGraphView.cpp \
gui/Src/Gui/DisassemblyPopup.cpp \
gui/Src/Gui/EditBreakpointDialog.cpp \
gui/Src/Gui/EditFloatRegister.cpp \
gui/Src/Gui/EntropyDialog.cpp \
gui/Src/Gui/ExceptionRangeDialog.cpp \
gui/Src/Gui/FavouriteTools.cpp \
gui/Src/Gui/GotoDialog.cpp \
gui/Src/Gui/HandlesView.cpp \
gui/Src/Gui/HexEditDialog.cpp \
gui/Src/Gui/HexLineEdit.cpp \
gui/Src/Gui/LineEditDialog.cpp \
gui/Src/Gui/LogView.cpp \
gui/Src/Gui/MainWindow.cpp \
gui/Src/Gui/MemoryMapView.cpp \
gui/Src/Gui/NotepadView.cpp \
gui/Src/Gui/NotesManager.cpp \
gui/Src/Gui/PageMemoryRights.cpp \
gui/Src/Gui/PatchDialog.cpp \
gui/Src/Gui/PatchDialogGroupSelector.cpp \
gui/Src/Gui/ReferenceManager.cpp \
gui/Src/Gui/RegistersView.cpp \
gui/Src/Gui/ScriptView.cpp \
gui/Src/Gui/SEHChainView.cpp \
gui/Src/Gui/SelectFields.cpp \
gui/Src/Gui/SettingsDialog.cpp \
gui/Src/Gui/ShortcutsDialog.cpp \
gui/Src/Gui/SourceView.cpp \
gui/Src/Gui/SourceViewerManager.cpp \
gui/Src/Gui/DebugStatusLabel.cpp \
gui/Src/Gui/LogStatusLabel.cpp \
gui/Src/Gui/SymbolView.cpp \
gui/Src/Gui/TabBar.cpp \
gui/Src/Gui/TabWidget.cpp \
gui/Src/Gui/ThreadView.cpp \
gui/Src/Gui/TimeWastedCounter.cpp \
gui/Src/Gui/VirtualModDialog.cpp \
gui/Src/Gui/WatchView.cpp \
gui/Src/Gui/WordEditDialog.cpp \
gui/Src/Gui/XrefBrowseDialog.cpp \
gui/Src/Gui/YaraRuleSelectionDialog.cpp \
gui/Src/main.cpp \
gui/Src/Disassembler/ZydisTokenizer.cpp \
gui/Src/Disassembler/QBeaEngine.cpp \
dbg/_dbgfunctions.cpp \
dbg/_exports.cpp \
dbg/_global.cpp \
dbg/_plugins.cpp \
dbg/_scriptapi_argument.cpp \
dbg/_scriptapi_assembler.cpp \
dbg/_scriptapi_bookmark.cpp \
dbg/_scriptapi_comment.cpp \
dbg/_scriptapi_debug.cpp \
dbg/_scriptapi_flag.cpp \
dbg/_scriptapi_function.cpp \
dbg/_scriptapi_gui.cpp \
dbg/_scriptapi_label.cpp \
dbg/_scriptapi_memory.cpp \
dbg/_scriptapi_misc.cpp \
dbg/_scriptapi_module.cpp \
dbg/_scriptapi_pattern.cpp \
dbg/_scriptapi_register.cpp \
dbg/_scriptapi_stack.cpp \
dbg/_scriptapi_symbol.cpp \
dbg/addrinfo.cpp \
dbg/argument.cpp \
dbg/assemble.cpp \
dbg/bookmark.cpp \
dbg/breakpoint.cpp \
dbg/command.cpp \
dbg/commandline.cpp \
dbg/commandparser.cpp \
dbg/comment.cpp \
dbg/console.cpp \
dbg/database.cpp \
dbg/datainst_helper.cpp \
dbg/dbghelp_safe.cpp \
dbg/debugger.cpp \
dbg/disasm_fast.cpp \
dbg/disasm_helper.cpp \
dbg/encodemap.cpp \
dbg/exception.cpp \
dbg/exhandlerinfo.cpp \
dbg/expressionfunctions.cpp \
dbg/expressionparser.cpp \
dbg/exprfunc.cpp \
dbg/filehelper.cpp \
dbg/function.cpp \
dbg/handles.cpp \
dbg/historycontext.cpp \
dbg/jit.cpp \
dbg/label.cpp \
dbg/log.cpp \
dbg/loop.cpp \
dbg/main.cpp \
dbg/memory.cpp \
dbg/mnemonichelp.cpp \
dbg/module.cpp \
dbg/msgqueue.cpp \
dbg/murmurhash.cpp \
dbg/patches.cpp \
dbg/patternfind.cpp \
dbg/plugin_loader.cpp \
dbg/reference.cpp \
dbg/simplescript.cpp \
dbg/stackinfo.cpp \
dbg/stringformat.cpp \
dbg/stringutils.cpp \
dbg/symbolinfo.cpp \
dbg/tcpconnections.cpp \
dbg/thread.cpp \
dbg/threading.cpp \
dbg/TraceRecord.cpp \
dbg/value.cpp \
dbg/variable.cpp \
dbg/watch.cpp \
dbg/x64dbg.cpp \
dbg/xrefs.cpp \
gui/Src/Bridge/Bridge.cpp \
gui/Src/Bridge/BridgeResult.cpp \
gui/Src/Utils/Breakpoints.cpp \
gui/Src/Utils/CodeFolding.cpp \
gui/Src/Utils/Configuration.cpp \
gui/Src/Utils/EncodeMap.cpp \
gui/Src/Utils/FlickerThread.cpp \
gui/Src/Utils/HexValidator.cpp \
gui/Src/Utils/LongLongValidator.cpp \
gui/Src/Utils/MainWindowCloseThread.cpp \
gui/Src/Utils/MiscUtil.cpp \
gui/Src/Utils/RichTextPainter.cpp \
gui/Src/Utils/StringUtil.cpp \
gui/Src/Utils/UpdateChecker.cpp \
gui/Src/Utils/ValidateExpressionThread.cpp \
gui/Src/QHexEdit/ArrayCommand.cpp \
gui/Src/QHexEdit/QHexEdit.cpp \
gui/Src/QHexEdit/QHexEditPrivate.cpp \
gui/Src/QHexEdit/XByteArray.cpp \
gui/Src/BasicView/AbstractTableView.cpp \
gui/Src/BasicView/Disassembly.cpp \
gui/Src/BasicView/HexDump.cpp \
gui/Src/BasicView/HistoryLineEdit.cpp \
gui/Src/BasicView/ReferenceView.cpp \
gui/Src/BasicView/SearchListView.cpp \
gui/Src/BasicView/ShortcutEdit.cpp \
gui/Src/BasicView/StdTable.cpp \
gui/Src/Memory/MemoryPage.cpp \
gui/Src/QEntropyView/QEntropyView.cpp \
dbg/analysis/advancedanalysis.cpp \
dbg/analysis/analysis.cpp \
dbg/analysis/analysis_nukem.cpp \
dbg/analysis/AnalysisPass.cpp \
dbg/analysis/CodeFollowPass.cpp \
dbg/analysis/controlflowanalysis.cpp \
dbg/analysis/exceptiondirectoryanalysis.cpp \
dbg/analysis/FunctionPass.cpp \
dbg/analysis/linearanalysis.cpp \
dbg/analysis/LinearPass.cpp \
dbg/analysis/recursiveanalysis.cpp \
dbg/analysis/xrefsanalysis.cpp \
dbg/animate.cpp \
gui/Src/BasicView/LabeledSplitter.cpp \
dbg/breakpoint_commands.cpp \
dbg/symcache.cpp \
dbg/commands/cmd-breakpoint-control.cpp \
dbg/commands/cmd-conditional-breakpoint-control.cpp \
dbg/commands/cmd-searching.cpp \
dbg/commands/cmd-debug-control.cpp \
dbg/commands/cmd-general-purpose.cpp \
dbg/commands/cmd-gui.cpp \
dbg/commands/cmd-memory-operations.cpp \
dbg/commands/cmd-misc.cpp \
dbg/commands/cmd-operating-system-control.cpp \
dbg/commands/cmd-plugins.cpp \
dbg/commands/cmd-script.cpp \
dbg/commands/cmd-thread-control.cpp \
dbg/commands/cmd-tracing.cpp \
dbg/commands/cmd-types.cpp \
dbg/commands/cmd-undocumented.cpp \
dbg/commands/cmd-user-database.cpp \
dbg/commands/cmd-variables.cpp \
dbg/commands/cmd-watch-control.cpp \
gui/Src/Gui/CustomizeMenuDialog.cpp \
gui/Src/Utils/MenuBuilder.cpp \
gui/Src/Gui/SimpleTraceDialog.cpp \
gui/Src/Gui/StructWidget.cpp \
dbg/formatfunctions.cpp \
dbg/types.cpp \
dbg/typesparser.cpp \
gui/Src/Utils/MRUList.cpp \
gui/Src/Gui/LocalVarsView.cpp \
gui/Src/Gui/MessagesBreakpoints.cpp \
gui/Src/Gui/AboutDialog.cpp \
gui/Src/Utils/CommonActions.cpp \
gui/Src/Utils/SymbolAutoCompleteModel.cpp \
gui/Src/Tracer/TraceBrowser.cpp \
gui/Src/Tracer/TraceFileReader.cpp \
gui/Src/Tracer/TraceFileSearch.cpp \
gui/Src/Gui/MultiItemsSelectWindow.cpp \
gui/Src/BasicView/AbstractStdTable.cpp \
gui/Src/Gui/ZehSymbolTable.cpp \
gui/Src/BasicView/StdSearchListView.cpp \
gui/Src/Gui/CPURegistersView.cpp \
gui/Src/Tracer/TraceRegisters.cpp \
gui/Src/Tracer/TraceWidget.cpp \
gui/Src/Gui/SystemBreakpointScriptDialog.cpp \
gui/Src/Tracer/TraceInfoBox.cpp
HEADERS += \
gui/Src/Exports.h \
gui/Src/Imports.h \
gui/Src/main.h \
gui/Src/Gui/AppearanceDialog.h \
gui/Src/Gui/AssembleDialog.h \
gui/Src/Gui/AttachDialog.h \
gui/Src/Gui/BreakpointsView.h \
gui/Src/Gui/BrowseDialog.h \
gui/Src/Gui/CalculatorDialog.h \
gui/Src/Gui/CallStackView.h \
gui/Src/Gui/CloseDialog.h \
gui/Src/Gui/CodepageSelectionDialog.h \
gui/Src/Gui/ColumnReorderDialog.h \
gui/Src/Gui/CommandLineEdit.h \
gui/Src/Gui/CPUArgumentWidget.h \
gui/Src/Gui/CPUDisassembly.h \
gui/Src/Gui/CPUDump.h \
gui/Src/Gui/CPUInfoBox.h \
gui/Src/Gui/CPUMultiDump.h \
gui/Src/Gui/CPUSideBar.h \
gui/Src/Gui/CPUStack.h \
gui/Src/Gui/CPUWidget.h \
gui/Src/Gui/DataCopyDialog.h \
gui/Src/Gui/DisassemblerGraphView.h \
gui/Src/Gui/DisassemblyPopup.cpp.orig \
gui/Src/Gui/DisassemblyPopup.h \
gui/Src/Gui/EditBreakpointDialog.h \
gui/Src/Gui/EditFloatRegister.h \
gui/Src/Gui/EntropyDialog.h \
gui/Src/Gui/ExceptionRangeDialog.h \
gui/Src/Gui/FavouriteTools.h \
gui/Src/Gui/GotoDialog.h \
gui/Src/Gui/HandlesView.h \
gui/Src/Gui/HexEditDialog.h \
gui/Src/Gui/HexLineEdit.h \
gui/Src/Gui/LineEditDialog.h \
gui/Src/Gui/LogView.h \
gui/Src/Gui/MainWindow.h \
gui/Src/Gui/MemoryMapView.h \
gui/Src/Gui/NotepadView.h \
gui/Src/Gui/NotesManager.h \
gui/Src/Gui/PageMemoryRights.h \
gui/Src/Gui/PatchDialog.h \
gui/Src/Gui/PatchDialogGroupSelector.h \
gui/Src/Gui/ReferenceManager.h \
gui/Src/Gui/RegistersView.h \
gui/Src/Gui/ScriptView.h \
gui/Src/Gui/SEHChainView.h \
gui/Src/Gui/SelectFields.h \
gui/Src/Gui/SettingsDialog.h \
gui/Src/Gui/ShortcutsDialog.h \
gui/Src/Gui/SourceView.h \
gui/Src/Gui/SourceViewerManager.h \
gui/Src/Gui/DebugStatusLabel.h \
gui/Src/Gui/LogStatusLabel.h \
gui/Src/Gui/SymbolView.h \
gui/Src/Gui/TabBar.h \
gui/Src/Gui/TabWidget.h \
gui/Src/Gui/ThreadView.h \
gui/Src/Gui/TimeWastedCounter.h \
gui/Src/Gui/VirtualModDialog.h \
gui/Src/Gui/WatchView.h \
gui/Src/Gui/WordEditDialog.h \
gui/Src/Gui/XrefBrowseDialog.h \
gui/Src/Gui/YaraRuleSelectionDialog.h \
gui/Src/Disassembler/ZydisTokenizer.h \
gui/Src/Disassembler/QBeaEngine.h \
gui/Src/Gui/StructWidget.h \
dbg/_dbgfunctions.h \
dbg/_exports.h \
dbg/_global.h \
dbg/_plugin_types.h \
dbg/_plugins.h \
dbg/_scriptapi.h \
dbg/_scriptapi_argument.h \
dbg/_scriptapi_assembler.h \
dbg/_scriptapi_bookmark.h \
dbg/_scriptapi_comment.h \
dbg/_scriptapi_debug.h \
dbg/_scriptapi_flag.h \
dbg/_scriptapi_function.h \
dbg/_scriptapi_gui.h \
dbg/_scriptapi_label.h \
dbg/_scriptapi_memory.h \
dbg/_scriptapi_misc.h \
dbg/_scriptapi_module.h \
dbg/_scriptapi_pattern.h \
dbg/_scriptapi_register.h \
dbg/_scriptapi_stack.h \
dbg/_scriptapi_symbol.h \
dbg/addrinfo.h \
dbg/argument.h \
dbg/assemble.h \
dbg/bookmark.h \
dbg/breakpoint.h \
dbg/command.h \
dbg/commandline.h \
dbg/commandparser.h \
dbg/comment.h \
dbg/console.h \
dbg/database.h \
dbg/datainst_helper.h \
dbg/dbghelp_safe.h \
dbg/debugger.h \
dbg/disasm_fast.h \
dbg/disasm_helper.h \
dbg/dynamicmem.h \
dbg/encodemap.h \
dbg/exception.h \
dbg/exhandlerinfo.h \
dbg/expressionfunctions.h \
dbg/expressionparser.h \
dbg/exprfunc.h \
dbg/filehelper.h \
dbg/function.h \
dbg/handle.h \
dbg/handles.h \
dbg/historycontext.h \
dbg/jit.h \
dbg/label.h \
dbg/loop.h \
dbg/memory.h \
dbg/mnemonichelp.h \
dbg/module.h \
dbg/msgqueue.h \
dbg/murmurhash.h \
dbg/patches.h \
dbg/patternfind.h \
dbg/plugin_loader.h \
dbg/reference.h \
dbg/serializablemap.h \
dbg/simplescript.h \
dbg/stackinfo.h \
dbg/stringformat.h \
dbg/stringutils.h \
dbg/symbolinfo.h \
dbg/taskthread.h \
dbg/tcpconnections.h \
dbg/thread.h \
dbg/threading.h \
dbg/TraceRecord.h \
dbg/ntdll/ntdll.h \
dbg/value.h \
dbg/variable.h \
dbg/watch.h \
dbg/x64dbg.h \
dbg/xrefs.h \
gui/Src/Bridge/Bridge.h \
gui/Src/Bridge/BridgeResult.h \
gui/Src/Utils/ActionHelpers.h \
gui/Src/Utils/Breakpoints.h \
gui/Src/Utils/CachedFontMetrics.h \
gui/Src/Utils/CodeFolding.h \
gui/Src/Utils/Configuration.h \
gui/Src/Utils/EncodeMap.h \
gui/Src/Utils/FlickerThread.h \
gui/Src/Utils/HexValidator.h \
gui/Src/Utils/LongLongValidator.h \
gui/Src/Utils/MainWindowCloseThread.h \
gui/Src/Utils/MenuBuilder.h \
gui/Src/Utils/MiscUtil.h \
gui/Src/Utils/RichTextPainter.h \
gui/Src/Utils/StringUtil.h \
gui/Src/Utils/UpdateChecker.h \
gui/Src/Utils/ValidateExpressionThread.h \
gui/Src/QHexEdit/ArrayCommand.h \
gui/Src/QHexEdit/QHexEdit.h \
gui/Src/QHexEdit/QHexEditPrivate.h \
gui/Src/QHexEdit/XByteArray.h \
gui/Src/BasicView/AbstractTableView.h \
gui/Src/BasicView/Disassembly.h \
gui/Src/BasicView/HeaderButton.h \
gui/Src/BasicView/HexDump.h \
gui/Src/BasicView/HistoryLineEdit.h \
gui/Src/BasicView/ReferenceView.h \
gui/Src/BasicView/SearchListView.h \
gui/Src/BasicView/ShortcutEdit.h \
gui/Src/BasicView/StdTable.h \
gui/Src/Memory/MemoryPage.h \
gui/Src/QEntropyView/Entropy.h \
gui/Src/QEntropyView/QEntropyView.h \
gui/Src/ThirdPartyLibs/snowman/SnowmanView.h \
dbg/analysis/advancedanalysis.h \
dbg/analysis/analysis.h \
dbg/analysis/analysis_nukem.h \
dbg/analysis/AnalysisPass.h \
dbg/analysis/BasicBlock.h \
dbg/analysis/CodeFollowPass.h \
dbg/analysis/controlflowanalysis.h \
dbg/analysis/exceptiondirectoryanalysis.h \
dbg/analysis/FunctionPass.h \
dbg/analysis/linearanalysis.h \
dbg/analysis/LinearPass.h \
dbg/analysis/recursiveanalysis.h \
dbg/analysis/xrefsanalysis.h \
dbg/animate.h \
gui/Src/BasicView/LabeledSplitter.h \
dbg/symcache.h \
dbg/commands/cmd-breakpoint-control.h \
dbg/commands/cmd-conditional-breakpoint-control.h \
dbg/commands/cmd-searching.h \
dbg/commands/cmd-debug-control.h \
dbg/commands/cmd-general-purpose.h \
dbg/commands/cmd-gui.h \
dbg/commands/cmd-memory-operations.h \
dbg/commands/cmd-misc.h \
dbg/commands/cmd-operating-system-control.h \
dbg/commands/cmd-plugins.h \
dbg/commands/cmd-script.h \
dbg/commands/cmd-thread-control.h \
dbg/commands/cmd-tracing.h \
dbg/commands/cmd-types.h \
dbg/commands/cmd-undocumented.h \
dbg/commands/cmd-user-database.h \
dbg/commands/cmd-variables.h \
dbg/commands/cmd-watch-control.h \
gui/Src/Gui/CustomizeMenuDialog.h \
gui/Src/Gui/SimpleTraceDialog.h \
dbg/filemap.h \
dbg/formatfunctions.h \
dbg/types.h \
gui/Src/Utils/MRUList.h \
gui/Src/Gui/LocalVarsView.h \
gui/Src/Gui/MessagesBreakpoints.h \
gui/Src/Gui/AboutDialog.h \
gui/Src/Utils/CommonActions.h \
gui/Src/Utils/SymbolAutoCompleteModel.h \
gui/Src/Tracer/TraceBrowser.h \
gui/Src/Tracer/TraceFileReader.h \
gui/Src/Tracer/TraceFileReaderInternal.h \
gui/Src/Tracer/TraceFileSearch.h \
gui/Src/Gui/MultiItemsSelectWindow.h \
gui/Src/BasicView/AbstractStdTable.h \
gui/Src/Gui/ZehSymbolTable.h \
gui/Src/BasicView/StdSearchListView.h \
gui/Src/Gui/CPURegistersView.h \
gui/Src/Tracer/TraceRegisters.h \
gui/Src/Tracer/TraceWidget.h \
gui/Src/Gui/SystemBreakpointScriptDialog.h \
gui/Src/Tracer/TraceInfoBox.h
FORMS += \
gui/Src/Gui/AppearanceDialog.ui \
gui/Src/Gui/AssembleDialog.ui \
gui/Src/Gui/AttachDialog.ui \
gui/Src/Gui/BrowseDialog.ui \
gui/Src/Gui/CalculatorDialog.ui \
gui/Src/Gui/CloseDialog.ui \
gui/Src/Gui/CodepageSelectionDialog.ui \
gui/Src/Gui/ColumnReorderDialog.ui \
gui/Src/Gui/CPUArgumentWidget.ui \
gui/Src/Gui/CPUWidget.ui \
gui/Src/Gui/DataCopyDialog.ui \
gui/Src/Gui/EditBreakpointDialog.ui \
gui/Src/Gui/EditFloatRegister.ui \
gui/Src/Gui/EntropyDialog.ui \
gui/Src/Gui/ExceptionRangeDialog.ui \
gui/Src/Gui/FavouriteTools.ui \
gui/Src/Gui/GotoDialog.ui \
gui/Src/Gui/HexEditDialog.ui \
gui/Src/Gui/HexLineEdit.ui \
gui/Src/Gui/LineEditDialog.ui \
gui/Src/Gui/MainWindow.ui \
gui/Src/Gui/PageMemoryRights.ui \
gui/Src/Gui/PatchDialog.ui \
gui/Src/Gui/PatchDialogGroupSelector.ui \
gui/Src/Gui/SelectFields.ui \
gui/Src/Gui/SettingsDialog.ui \
gui/Src/Gui/ShortcutsDialog.ui \
gui/Src/Gui/SymbolView.ui \
gui/Src/Gui/VirtualModDialog.ui \
gui/Src/Gui/WordEditDialog.ui \
gui/Src/Gui/XrefBrowseDialog.ui \
gui/Src/Gui/YaraRuleSelectionDialog.ui \
gui/Src/Gui/CustomizeMenuDialog.ui \
gui/Src/Gui/SimpleTraceDialog.ui \
gui/Src/Gui/StructWidget.ui \
gui/Src/Gui/MessagesBreakpoints.ui \
gui/Src/Gui/AboutDialog.ui \
gui/Src/Tracer/TraceWidget.ui \
gui/Src/Gui/SystemBreakpointScriptDialog.ui
TRANSLATIONS += \
gui/Translations/x64dbg.ts |
|
C/C++ | x64dbg-development/src/bridge/bridgegraph.h | #ifndef _GRAPH_H
#define _GRAPH_H
typedef struct
{
duint addr; //virtual address of the instruction
unsigned char data[15]; //instruction bytes
} BridgeCFInstruction;
typedef struct
{
duint parentGraph; //function of which this node is a part
duint start; //start of the block
duint end; //end of the block (inclusive)
duint brtrue; //destination if condition is true
duint brfalse; //destination if condition is false
duint icount; //number of instructions in node
bool terminal; //node is a RET
bool split; //node is a split (brtrue points to the next node)
bool indirectcall; //node contains indirect calls (call reg, call [reg+X])
void* userdata; //user data
ListInfo exits; //exits (including brtrue and brfalse, duint)
ListInfo instrs; //block instructions
} BridgeCFNodeList;
typedef struct
{
duint entryPoint; //graph entry point
void* userdata; //user data
ListInfo nodes; //graph nodes (BridgeCFNodeList)
} BridgeCFGraphList;
#ifdef __cplusplus
#if _MSC_VER >= 1700 && !defined(NO_CPP11)
#include <unordered_map>
#include <unordered_set>
#include <vector>
#include <utility>
struct BridgeCFNode
{
duint parentGraph = 0; //function of which this node is a part
duint start = 0; //va of the first instruction in the block
duint end = 0; //va of the last instruction in the block (inclusive)
duint brtrue = 0; //destination if condition is true
duint brfalse = 0; //destination if condition is false
duint icount = 0; //number of instructions in node
bool terminal = false; //node is a RET
bool split = false; //node is a split (brtrue points to the next node)
bool indirectcall = false; //node contains indirect calls (call reg, call [reg+X])
void* userdata = nullptr; //user data
std::vector<duint> exits; //exits (including brtrue and brfalse)
std::vector<BridgeCFInstruction> instrs; //block instructions
static void Free(const BridgeCFNodeList* nodeList)
{
if(!BridgeList<duint>::Free(&nodeList->exits))
__debugbreak();
if(!BridgeList<BridgeCFInstruction>::Free(&nodeList->instrs))
__debugbreak();
}
BridgeCFNode() = default;
BridgeCFNode(const BridgeCFNodeList* nodeList, bool freedata)
{
if(!nodeList)
__debugbreak();
parentGraph = nodeList->parentGraph;
start = nodeList->start;
end = nodeList->end;
brtrue = nodeList->brtrue;
brfalse = nodeList->brfalse;
icount = nodeList->icount;
terminal = nodeList->terminal;
indirectcall = nodeList->indirectcall;
split = nodeList->split;
userdata = nodeList->userdata;
if(!BridgeList<duint>::ToVector(&nodeList->exits, exits, freedata))
__debugbreak();
if(!BridgeList<BridgeCFInstruction>::ToVector(&nodeList->instrs, instrs, freedata))
__debugbreak();
}
BridgeCFNode(duint parentGraph, duint start, duint end)
: parentGraph(parentGraph),
start(start),
end(end)
{
}
BridgeCFNodeList ToNodeList() const
{
BridgeCFNodeList out;
out.parentGraph = parentGraph;
out.start = start;
out.end = end;
out.brtrue = brtrue;
out.brfalse = brfalse;
out.icount = icount;
out.terminal = terminal;
out.indirectcall = indirectcall;
out.split = split;
out.userdata = userdata;
BridgeList<duint>::CopyData(&out.exits, exits);
BridgeList<BridgeCFInstruction>::CopyData(&out.instrs, instrs);
return std::move(out);
}
};
struct BridgeCFGraph
{
duint entryPoint; //graph entry point
void* userdata; //user data
std::unordered_map<duint, BridgeCFNode> nodes; //CFNode.start -> CFNode
std::unordered_map<duint, std::unordered_set<duint>> parents; //CFNode.start -> parents
static void Free(const BridgeCFGraphList* graphList)
{
if(!graphList || graphList->nodes.size != graphList->nodes.count * sizeof(BridgeCFNodeList))
__debugbreak();
auto data = (BridgeCFNodeList*)graphList->nodes.data;
for(int i = 0; i < graphList->nodes.count; i++)
BridgeCFNode::Free(&data[i]);
BridgeFree(data);
}
explicit BridgeCFGraph(const BridgeCFGraphList* graphList, bool freedata)
{
if(!graphList || graphList->nodes.size != graphList->nodes.count * sizeof(BridgeCFNodeList))
__debugbreak();
entryPoint = graphList->entryPoint;
userdata = graphList->userdata;
auto data = (BridgeCFNodeList*)graphList->nodes.data;
for(int i = 0; i < graphList->nodes.count; i++)
AddNode(BridgeCFNode(&data[i], freedata));
if(freedata && data)
BridgeFree(data);
}
explicit BridgeCFGraph(duint entryPoint)
: entryPoint(entryPoint),
userdata(nullptr)
{
}
void AddNode(const BridgeCFNode & node)
{
nodes[node.start] = node;
AddParent(node.start, node.brtrue);
AddParent(node.start, node.brfalse);
}
void AddParent(duint child, duint parent)
{
if(!child || !parent)
return;
auto found = parents.find(child);
if(found == parents.end())
{
parents[child] = std::unordered_set<duint>();
parents[child].insert(parent);
}
else
found->second.insert(parent);
}
BridgeCFGraphList ToGraphList() const
{
BridgeCFGraphList out;
out.entryPoint = entryPoint;
out.userdata = userdata;
std::vector<BridgeCFNodeList> nodeList;
nodeList.reserve(nodes.size());
for(const auto & nodeIt : nodes)
nodeList.push_back(nodeIt.second.ToNodeList());
BridgeList<BridgeCFNodeList>::CopyData(&out.nodes, nodeList);
return std::move(out);
}
};
#endif //_MSC_VER
#endif //__cplusplus
#endif //_GRAPH_H |
C/C++ | x64dbg-development/src/bridge/bridgelist.h | #ifndef _LIST_H
#define _LIST_H
typedef struct
{
int count; //Number of element in the list.
size_t size; //Size of list in bytes (used for type checking).
void* data; //Pointer to the list contents. Must be deleted by the caller using BridgeFree (or BridgeList::Free).
} ListInfo;
#define ListOf(Type) ListInfo*
#ifdef __cplusplus
#include <vector>
/**
\brief A list object. This object is NOT thread safe.
\tparam Type BridgeList contents type.
*/
template<typename Type>
class BridgeList
{
public:
/**
\brief BridgeList constructor.
\param _freeData (Optional) the free function.
*/
explicit BridgeList()
{
memset(&_listInfo, 0, sizeof(_listInfo));
}
/**
\brief BridgeList destructor.
*/
~BridgeList()
{
Cleanup();
}
/**
\brief Gets the list data.
\return Returns ListInfo->data. Can be null if the list was never initialized. Will be destroyed once this object goes out of scope!
*/
Type* Data() const
{
return reinterpret_cast<Type*>(_listInfo.data);
}
/**
\brief Gets the number of elements in the list. This will crash the program if the data is not consistent with the specified template argument.
\return The number of elements in the list.
*/
int Count() const
{
if(_listInfo.size != _listInfo.count * sizeof(Type)) //make sure the user is using the correct type.
__debugbreak();
return _listInfo.count;
}
/**
\brief Cleans up the list, freeing the list data when it is not null.
*/
void Cleanup()
{
if(_listInfo.data)
{
BridgeFree(_listInfo.data);
_listInfo.data = nullptr;
}
}
/**
\brief Reference operator (cleans up the previous list)
\return Pointer to the ListInfo.
*/
ListInfo* operator&()
{
Cleanup();
return &_listInfo;
}
/**
\brief Array indexer operator. This will crash if you try to access out-of-bounds.
\param index Zero-based index of the item you want to get.
\return Reference to a value at that index.
*/
Type & operator[](size_t index) const
{
if(index >= size_t(Count())) //make sure the out-of-bounds access is caught as soon as possible.
__debugbreak();
return Data()[index];
}
/**
\brief Copies data to a ListInfo structure..
\param [out] listInfo If non-null, information describing the list.
\param listData Data to copy in the ListInfo structure.
\return true if it succeeds, false if it fails.
*/
static bool CopyData(ListInfo* listInfo, const std::vector<Type> & listData)
{
if(!listInfo)
return false;
listInfo->count = int(listData.size());
listInfo->size = listInfo->count * sizeof(Type);
if(listInfo->count)
{
listInfo->data = BridgeAlloc(listInfo->size);
Type* curItem = reinterpret_cast<Type*>(listInfo->data);
for(const auto & item : listData)
{
*curItem = item;
++curItem;
}
}
else
listInfo->data = nullptr;
return true;
}
static bool Free(const ListInfo* listInfo)
{
if(!listInfo || listInfo->size != listInfo->count * sizeof(Type) || (listInfo->count && !listInfo->data))
return false;
BridgeFree(listInfo->data);
return true;
}
static bool ToVector(const ListInfo* listInfo, std::vector<Type> & listData, bool freedata = true)
{
if(!listInfo || listInfo->size != listInfo->count * sizeof(Type) || (listInfo->count && !listInfo->data))
return false;
listData.resize(listInfo->count);
for(int i = 0; i < listInfo->count; i++)
listData[i] = ((Type*)listInfo->data)[i];
if(freedata && listInfo->data)
BridgeFree(listInfo->data);
return true;
}
private:
ListInfo _listInfo;
};
#endif //__cplusplus
#endif //_LIST_H |
C++ | x64dbg-development/src/bridge/bridgemain.cpp | /**
* \file bridgemain.cpp
*
* \brief Defines functions to initialize and start the Bridge and
* to interface with the GUI and the DBG.
*/
#include "_global.h"
#include "bridgemain.h"
#include <stdio.h>
#include <ShlObj.h>
#include "Utf8Ini.h"
static HINSTANCE hInst;
static Utf8Ini settings;
static wchar_t szUserDirectory[MAX_PATH] = L"";
static wchar_t szIniFile[MAX_PATH] = L"";
static CRITICAL_SECTION csIni;
static CRITICAL_SECTION csTranslate;
static bool bDisableGUIUpdate;
#define CHECK_GUI_UPDATE_DISABLED \
if (bDisableGUIUpdate) \
return;
#ifdef _WIN64
#define dbg_lib L"x64dbg.dll"
#define gui_lib L"x64gui.dll"
#else
#define dbg_lib L"x32dbg.dll"
#define gui_lib L"x32gui.dll"
#endif // _WIN64
#define LOADLIBRARY(name) \
szLib=name; \
hInst=BridgeLoadLibraryCheckedW(name, false);
#define LOADEXPORT(name) \
*((FARPROC*)&name)=GetProcAddress(hInst, #name); \
if(!name) \
{ \
wsprintfW(szError, L"Export %s:%S could not be found!", szLib, #name); \
return szError; \
}
static std::wstring Utf8ToUtf16(const char* str)
{
std::wstring convertedString;
if(!str || !*str)
return convertedString;
int requiredSize = MultiByteToWideChar(CP_UTF8, 0, str, -1, nullptr, 0);
if(requiredSize > 0)
{
convertedString.resize(requiredSize - 1);
if(!MultiByteToWideChar(CP_UTF8, 0, str, -1, (wchar_t*)convertedString.c_str(), requiredSize))
convertedString.clear();
}
return convertedString;
}
static bool DirExists(const wchar_t* dir)
{
DWORD attrib = GetFileAttributesW(dir);
return (attrib != INVALID_FILE_ATTRIBUTES && (attrib & FILE_ATTRIBUTE_DIRECTORY) != 0);
}
static decltype(&BridgeLoadLibraryCheckedW) pLoadLibraryCheckedW;
static decltype(&BridgeLoadLibraryCheckedA) pLoadLibraryCheckedA;
static const wchar_t* InitializeUserDirectory()
{
// Handle user directory
if(!GetModuleFileNameW(0, szUserDirectory, _countof(szUserDirectory)))
return L"Error getting module path!";
auto backslash = wcsrchr(szUserDirectory, L'\\');
if(backslash == nullptr)
return L"Error getting module directory!";
*backslash = L'\0';
// Set the current directory to the application directory
SetCurrentDirectoryW(szUserDirectory);
// Extract the file name of the x64dbg executable (without extension)
auto fileNameWithoutExtension = backslash + 1;
auto period = wcschr(fileNameWithoutExtension, L'.');
if(period != nullptr)
{
*period = L'\0';
}
wchar_t szFolderRedirect[MAX_PATH];
wcscpy_s(szFolderRedirect, szUserDirectory);
wcscat_s(szFolderRedirect, L"\\userdir");
std::wstring userDirUtf16;
{
std::vector<char> userDirUtf8;
auto hFile = CreateFileW(szFolderRedirect, GENERIC_READ, FILE_SHARE_READ, nullptr, OPEN_EXISTING, 0, nullptr);
if(hFile != INVALID_HANDLE_VALUE)
{
auto size = GetFileSize(hFile, nullptr);
userDirUtf8.resize(size + 1);
DWORD read = 0;
if(!ReadFile(hFile, userDirUtf8.data(), size, &read, nullptr))
userDirUtf8.clear();
CloseHandle(hFile);
userDirUtf16 = Utf8ToUtf16(userDirUtf8.data());
}
else
{
userDirUtf16 = szUserDirectory;
}
}
if(userDirUtf16.empty())
{
wchar_t szAppData[MAX_PATH] = L"";
if(!SUCCEEDED(SHGetFolderPathW(nullptr, CSIDL_APPDATA, nullptr, 0, szAppData)))
return L"Error getting AppData path";
userDirUtf16 = szAppData;
if(userDirUtf16.back() != L'\\')
userDirUtf16 += L'\\';
userDirUtf16 += fileNameWithoutExtension;
CreateDirectoryW(userDirUtf16.c_str(), nullptr);
}
else
{
if(userDirUtf16.back() == L'\\')
userDirUtf16.pop_back();
}
if(!DirExists(userDirUtf16.c_str()))
return L"Specified user directory doesn't exist";
// Read the settings from the INI
wcscpy_s(szIniFile, userDirUtf16.c_str());
wcscat_s(szIniFile, L"\\");
wcscat_s(szIniFile, fileNameWithoutExtension);
wcscat_s(szIniFile, L".ini");
BridgeSettingRead(nullptr);
wcscpy_s(szUserDirectory, userDirUtf16.c_str());
return nullptr;
}
BRIDGE_IMPEXP const wchar_t* BridgeInit()
{
//Initialize critial section
InitializeCriticalSection(&csIni);
InitializeCriticalSection(&csTranslate);
// Signature checking functions
auto hMainModule = GetModuleHandleW(nullptr);
pLoadLibraryCheckedW = (decltype(pLoadLibraryCheckedW))GetProcAddress(hMainModule, "LoadLibraryCheckedW");
pLoadLibraryCheckedA = (decltype(pLoadLibraryCheckedA))GetProcAddress(hMainModule, "LoadLibraryCheckedA");
if(pLoadLibraryCheckedW == nullptr || pLoadLibraryCheckedA == nullptr)
return L"Error finding safe library loading functions!";
auto userDirectoryError = InitializeUserDirectory();
if(userDirectoryError != nullptr)
return userDirectoryError;
// Variables used by the macros below
HINSTANCE hInst;
const wchar_t* szLib;
static wchar_t szError[256] = L"";
auto titanEngineDll = []()
{
switch(DbgGetDebugEngine())
{
case DebugEngineGleeBug:
return L"GleeBug\\TitanEngine.dll";
case DebugEngineStaticEngine:
return L"StaticEngine\\TitanEngine.dll";
default:
return L"TitanEngine.dll";
}
}();
auto loadIfExists = [&](const wchar_t* szDll)
{
BridgeLoadLibraryCheckedW(szDll, true);
};
// Imported DLLs (DBG)
LOADLIBRARY(titanEngineDll);
LOADLIBRARY(L"LLVMDemangle.dll");
LOADLIBRARY(L"lz4.dll");
LOADLIBRARY(L"jansson.dll");
LOADLIBRARY(L"DeviceNameResolver.dll");
LOADLIBRARY(L"XEDParse.dll");
//loadIfExists(L"asmjit.dll"); // only loaded with user interaction
//loadIfExists(L"Scylla.dll"); // only loaded with user interaction
loadIfExists(L"msdia140.dll");
// DBG
LOADLIBRARY(dbg_lib);
LOADEXPORT(_dbg_dbginit);
LOADEXPORT(_dbg_memfindbaseaddr);
LOADEXPORT(_dbg_memread);
LOADEXPORT(_dbg_memwrite);
LOADEXPORT(_dbg_dbgcmdexec);
LOADEXPORT(_dbg_memmap);
LOADEXPORT(_dbg_dbgexitsignal);
LOADEXPORT(_dbg_valfromstring);
LOADEXPORT(_dbg_isdebugging);
LOADEXPORT(_dbg_isjumpgoingtoexecute);
LOADEXPORT(_dbg_addrinfoget);
LOADEXPORT(_dbg_addrinfoset);
LOADEXPORT(_dbg_encodetypeset);
LOADEXPORT(_dbg_bpgettypeat);
LOADEXPORT(_dbg_getregdump);
LOADEXPORT(_dbg_valtostring);
LOADEXPORT(_dbg_memisvalidreadptr);
LOADEXPORT(_dbg_getbplist);
LOADEXPORT(_dbg_dbgcmddirectexec);
LOADEXPORT(_dbg_getbranchdestination);
LOADEXPORT(_dbg_sendmessage);
// Imported DLLs (GUI)
LOADLIBRARY(L"ldconvert.dll");
loadIfExists(L"Qt5Core.dll");
loadIfExists(L"Qt5Gui.dll");
loadIfExists(L"Qt5WinExtras.dll");
loadIfExists(L"Qt5Widgets.dll");
loadIfExists(L"Qt5Network.dll");
loadIfExists(L"platforms\\qwindows.dll");
loadIfExists(L"imageformats\\qgif.dll");
loadIfExists(L"imageformats\\qicns.dll");
loadIfExists(L"imageformats\\qico.dll");
loadIfExists(L"imageformats\\qjpeg.dll");
loadIfExists(L"Qt5Svg.dll");
loadIfExists(L"imageformats\\qsvg.dll");
loadIfExists(L"imageformats\\qtga.dll");
loadIfExists(L"imageformats\\qtiff.dll");
loadIfExists(L"imageformats\\qwbmp.dll");
loadIfExists(L"imageformats\\qwebp.dll");
loadIfExists(L"bearer\\qgenericbearer.dll");
loadIfExists(L"bearer\\qnativewifibearer.dll");
loadIfExists(L"iconengines\\qsvgicon.dll");
loadIfExists(L"libeay32.dll");
loadIfExists(L"ssleay32.dll");
// GUI
LOADLIBRARY(gui_lib);
LOADEXPORT(_gui_guiinit);
LOADEXPORT(_gui_sendmessage);
LOADEXPORT(_gui_translate_text);
// Backwards compatibility
BridgeLoadLibraryCheckedW(L"x64_bridge.dll", true);
BridgeLoadLibraryCheckedW(L"x64_dbg.dll", true);
return 0;
}
BRIDGE_IMPEXP HMODULE WINAPI BridgeLoadLibraryCheckedW(const wchar_t* szDll, bool allowFailure)
{
return pLoadLibraryCheckedW(szDll, allowFailure);
}
BRIDGE_IMPEXP HMODULE WINAPI BridgeLoadLibraryCheckedA(const char* szDll, bool allowFailure)
{
return pLoadLibraryCheckedA(szDll, allowFailure);
}
BRIDGE_IMPEXP const wchar_t* BridgeStart()
{
if(!_dbg_dbginit || !_gui_guiinit)
return L"\"_dbg_dbginit\" || \"_gui_guiinit\" was not loaded yet, call BridgeInit!";
_dbg_sendmessage(DBG_INITIALIZE_LOCKS, nullptr, nullptr); //initialize locks before any other thread than the main thread are started
_gui_guiinit(0, 0); //remove arguments
if(!BridgeSettingFlush())
return L"Failed to save settings!";
_dbg_sendmessage(DBG_DEINITIALIZE_LOCKS, nullptr, nullptr); //deinitialize locks when only one thread is left (hopefully)
DeleteCriticalSection(&csIni);
DeleteCriticalSection(&csTranslate);
return 0;
}
BRIDGE_IMPEXP void* BridgeAlloc(size_t size)
{
unsigned char* ptr = (unsigned char*)GlobalAlloc(GMEM_FIXED, size);
if(!ptr)
{
MessageBoxW(0, L"Could not allocate memory", L"Error", MB_ICONERROR);
ExitProcess(1);
}
memset(ptr, 0, size);
return ptr;
}
BRIDGE_IMPEXP void BridgeFree(void* ptr)
{
if(ptr != nullptr)
GlobalFree(ptr);
}
BRIDGE_IMPEXP bool BridgeSettingGet(const char* section, const char* key, char* value)
{
if(!section || !key || !value)
return false;
EnterCriticalSection(&csIni);
auto foundValue = settings.GetValue(section, key);
bool result = foundValue.length() > 0;
if(result)
strcpy_s(value, MAX_SETTING_SIZE, foundValue.c_str());
LeaveCriticalSection(&csIni);
return result;
}
BRIDGE_IMPEXP bool BridgeSettingGetUint(const char* section, const char* key, duint* value)
{
if(!section || !key || !value)
return false;
char newvalue[MAX_SETTING_SIZE] = "";
if(!BridgeSettingGet(section, key, newvalue))
return false;
#ifdef _WIN64
int ret = sscanf_s(newvalue, "%llX", value);
#else
int ret = sscanf_s(newvalue, "%X", value);
#endif //_WIN64
if(ret)
return true;
return false;
}
BRIDGE_IMPEXP bool BridgeSettingSet(const char* section, const char* key, const char* value)
{
bool success = false;
if(section)
{
EnterCriticalSection(&csIni);
if(!key)
success = settings.ClearSection(section);
else if(!value)
success = settings.SetValue(section, key, "");
else
success = settings.SetValue(section, key, value);
LeaveCriticalSection(&csIni);
}
return success;
}
BRIDGE_IMPEXP bool BridgeSettingSetUint(const char* section, const char* key, duint value)
{
if(!section || !key)
return false;
char newvalue[32] = "";
#ifdef _WIN64
sprintf_s(newvalue, "%llX", value);
#else
sprintf_s(newvalue, "%X", value);
#endif //_WIN64
return BridgeSettingSet(section, key, newvalue);
}
BRIDGE_IMPEXP bool BridgeSettingFlush()
{
EnterCriticalSection(&csIni);
std::string iniData = settings.Serialize();
LeaveCriticalSection(&csIni);
bool success = false;
HANDLE hFile = CreateFileW(szIniFile, GENERIC_WRITE, 0, nullptr, CREATE_ALWAYS, FILE_ATTRIBUTE_NORMAL, nullptr);
if(hFile != INVALID_HANDLE_VALUE)
{
SetEndOfFile(hFile);
DWORD written = 0;
if(WriteFile(hFile, iniData.c_str(), (DWORD)iniData.length(), &written, nullptr))
success = true;
CloseHandle(hFile);
}
return success;
}
BRIDGE_IMPEXP bool BridgeSettingRead(int* errorLine)
{
if(errorLine)
*errorLine = 0;
bool success = false;
std::string iniData;
HANDLE hFile = CreateFileW(szIniFile, GENERIC_READ, FILE_SHARE_READ, nullptr, OPEN_EXISTING, 0, nullptr);
if(hFile != INVALID_HANDLE_VALUE)
{
DWORD fileSize = GetFileSize(hFile, nullptr);
if(fileSize)
{
unsigned char utf8bom[] = { 0xEF, 0xBB, 0xBF };
char* fileData = (char*)BridgeAlloc(sizeof(utf8bom) + fileSize + 1);
DWORD read = 0;
if(ReadFile(hFile, fileData, fileSize, &read, nullptr))
{
success = true;
if(!memcmp(fileData, utf8bom, sizeof(utf8bom)))
iniData.assign(fileData + sizeof(utf8bom));
else
iniData.assign(fileData);
}
BridgeFree(fileData);
}
CloseHandle(hFile);
}
if(success) //if we failed to read the file, the current settings are better than none at all
{
EnterCriticalSection(&csIni);
int errline = 0;
success = settings.Deserialize(iniData, errline);
if(errorLine)
*errorLine = errline;
LeaveCriticalSection(&csIni);
}
return success;
}
BRIDGE_IMPEXP int BridgeGetDbgVersion()
{
return DBG_VERSION;
}
BRIDGE_IMPEXP bool BridgeIsProcessElevated()
{
SID_IDENTIFIER_AUTHORITY NtAuthority = SECURITY_NT_AUTHORITY;
PSID SecurityIdentifier;
if(!AllocateAndInitializeSid(&NtAuthority, 2, SECURITY_BUILTIN_DOMAIN_RID, DOMAIN_ALIAS_RID_ADMINS, 0, 0, 0, 0, 0, 0, &SecurityIdentifier))
return 0;
BOOL IsAdminMember;
if(!CheckTokenMembership(NULL, SecurityIdentifier, &IsAdminMember))
IsAdminMember = FALSE;
FreeSid(SecurityIdentifier);
return !!IsAdminMember;
}
static DWORD BridgeGetNtBuildNumberWindows7()
{
auto p_RtlGetVersion = (NTSTATUS(WINAPI*)(PRTL_OSVERSIONINFOW))GetProcAddress(GetModuleHandleW(L"ntdll.dll"), "RtlGetVersion");
RTL_OSVERSIONINFOW info = { sizeof(info) };
if(p_RtlGetVersion && p_RtlGetVersion(&info) == 0)
return info.dwBuildNumber;
else
return 0;
}
BRIDGE_IMPEXP unsigned int BridgeGetNtBuildNumber()
{
// https://www.vergiliusproject.com/kernels/x64/Windows%2010%20%7C%202016/1507%20Threshold%201/_KUSER_SHARED_DATA
auto NtBuildNumber = *(DWORD*)(0x7FFE0000 + 0x260);
if(NtBuildNumber == 0)
{
// Older versions of Windows
static DWORD NtBuildNumber7 = BridgeGetNtBuildNumberWindows7();
NtBuildNumber = NtBuildNumber7;
}
return NtBuildNumber;
}
BRIDGE_IMPEXP const wchar_t* BridgeUserDirectory()
{
return szUserDirectory;
}
BRIDGE_IMPEXP bool DbgMemRead(duint va, void* dest, duint size)
{
#ifdef _DEBUG
if(IsBadWritePtr(dest, size))
{
GuiAddLogMessage("DbgMemRead with invalid boundaries!\n");
__debugbreak();
return false;
}
#endif //_DEBUG
if(!_dbg_memread(va, dest, size, 0))
{
// Zero the buffer on failure
memset(dest, 0, size);
return false;
}
return true;
}
BRIDGE_IMPEXP bool DbgMemWrite(duint va, const void* src, duint size)
{
#ifdef _DEBUG
if(IsBadReadPtr(src, size))
{
GuiAddLogMessage("DbgMemWrite with invalid boundaries!\n");
__debugbreak();
return false;
}
#endif //_DEBUG
return _dbg_memwrite(va, src, size, 0);
}
// FIXME, not exactly base if it still does a find?
BRIDGE_IMPEXP duint DbgMemGetPageSize(duint base)
{
duint size = 0;
_dbg_memfindbaseaddr(base, &size);
return size;
}
BRIDGE_IMPEXP duint DbgMemFindBaseAddr(duint addr, duint* size)
{
return _dbg_memfindbaseaddr(addr, size);
}
BRIDGE_IMPEXP bool DbgCmdExec(const char* cmd)
{
return _dbg_dbgcmdexec(cmd);
}
// FIXME
BRIDGE_IMPEXP bool DbgMemMap(MEMMAP* memmap)
{
return _dbg_memmap(memmap);
}
BRIDGE_IMPEXP bool DbgIsValidExpression(const char* expression)
{
duint value = 0;
return _dbg_valfromstring(expression, &value);
}
BRIDGE_IMPEXP bool DbgIsDebugging()
{
return _dbg_isdebugging();
}
BRIDGE_IMPEXP bool DbgIsJumpGoingToExecute(duint addr)
{
return _dbg_isjumpgoingtoexecute(addr);
}
// FIXME required size of arg _text_?
BRIDGE_IMPEXP bool DbgGetLabelAt(duint addr, SEGMENTREG segment, char* text) //(module.)+label
{
if(!text || !addr)
return false;
BRIDGE_ADDRINFO info;
memset(&info, 0, sizeof(info));
info.flags = flaglabel | flagNoFuncOffset;
if(!_dbg_addrinfoget(addr, segment, &info))
{
duint addr_ = 0;
if(!DbgMemIsValidReadPtr(addr))
return false;
DbgMemRead(addr, (unsigned char*)&addr_, sizeof(duint));
BRIDGE_ADDRINFO ptrinfo = info;
if(!_dbg_addrinfoget(addr_, SEG_DEFAULT, &ptrinfo))
return false;
_snprintf_s(info.label, _TRUNCATE, "&%s", ptrinfo.label);
}
strcpy_s(text, MAX_LABEL_SIZE, info.label);
return true;
}
BRIDGE_IMPEXP bool DbgSetLabelAt(duint addr, const char* text)
{
if(!text || strlen(text) >= MAX_LABEL_SIZE || !addr)
return false;
BRIDGE_ADDRINFO info;
memset(&info, 0, sizeof(info));
info.flags = flaglabel;
strcpy_s(info.label, text);
if(!_dbg_addrinfoset(addr, &info))
return false;
return true;
}
BRIDGE_IMPEXP void DbgClearLabelRange(duint start, duint end)
{
_dbg_sendmessage(DBG_DELETE_LABEL_RANGE, (void*)start, (void*)end);
}
// FIXME required size of arg _text_?
BRIDGE_IMPEXP bool DbgGetCommentAt(duint addr, char* text) //comment (not live)
{
if(!text || !addr)
return false;
BRIDGE_ADDRINFO info;
memset(&info, 0, sizeof(info));
info.flags = flagcomment;
if(!_dbg_addrinfoget(addr, SEG_DEFAULT, &info))
return false;
strcpy_s(text, MAX_COMMENT_SIZE, info.comment);
return true;
}
BRIDGE_IMPEXP bool DbgSetCommentAt(duint addr, const char* text)
{
if(!text || strlen(text) >= MAX_COMMENT_SIZE || !addr)
return false;
BRIDGE_ADDRINFO info;
memset(&info, 0, sizeof(info));
info.flags = flagcomment;
strcpy_s(info.comment, MAX_COMMENT_SIZE, text);
if(!_dbg_addrinfoset(addr, &info))
return false;
return true;
}
BRIDGE_IMPEXP void DbgClearCommentRange(duint start, duint end)
{
_dbg_sendmessage(DBG_DELETE_COMMENT_RANGE, (void*)start, (void*)end);
}
// FIXME required size of arg _text_?
BRIDGE_IMPEXP bool DbgGetModuleAt(duint addr, char* text)
{
if(!text || !addr)
return false;
BRIDGE_ADDRINFO info;
memset(&info, 0, sizeof(info));
info.flags = flagmodule;
if(!_dbg_addrinfoget(addr, SEG_DEFAULT, &info))
return false;
strcpy_s(text, MAX_MODULE_SIZE, info.module);
return true;
}
BRIDGE_IMPEXP bool DbgGetBookmarkAt(duint addr)
{
if(!addr)
return false;
BRIDGE_ADDRINFO info;
memset(&info, 0, sizeof(info));
info.flags = flagbookmark;
if(!_dbg_addrinfoget(addr, SEG_DEFAULT, &info))
return false;
return info.isbookmark;
}
BRIDGE_IMPEXP bool DbgSetBookmarkAt(duint addr, bool isbookmark)
{
if(!addr)
return false;
BRIDGE_ADDRINFO info;
memset(&info, 0, sizeof(info));
info.flags = flagbookmark;
info.isbookmark = isbookmark;
return _dbg_addrinfoset(addr, &info);
}
BRIDGE_IMPEXP void DbgClearBookmarkRange(duint start, duint end)
{
_dbg_sendmessage(DBG_DELETE_BOOKMARK_RANGE, (void*)start, (void*)end);
}
// FIXME return on success?
BRIDGE_IMPEXP const char* DbgInit()
{
return _dbg_dbginit();
}
BRIDGE_IMPEXP void DbgExit()
{
_dbg_dbgexitsignal(); //send exit signal to debugger
}
BRIDGE_IMPEXP BPXTYPE DbgGetBpxTypeAt(duint addr)
{
return _dbg_bpgettypeat(addr);
}
BRIDGE_IMPEXP duint DbgValFromString(const char* string)
{
duint value = 0;
_dbg_valfromstring(string, &value);
return value;
}
//deprecated api, only provided for binary compatibility
extern "C" __declspec(dllexport) bool DbgGetRegDump(REGDUMP* regdump)
{
typedef struct
{
REGISTERCONTEXT regcontext;
FLAGS flags;
X87FPUREGISTER x87FPURegisters[8];
unsigned long long mmx[8];
MXCSRFIELDS MxCsrFields;
X87STATUSWORDFIELDS x87StatusWordFields;
X87CONTROLWORDFIELDS x87ControlWordFields;
LASTERROR lastError;
} REGDUMP_OLD;
return DbgGetRegDumpEx(regdump, sizeof(REGDUMP_OLD));
}
BRIDGE_IMPEXP bool DbgGetRegDumpEx(REGDUMP* regdump, size_t size)
{
if(size == sizeof(REGDUMP))
return _dbg_getregdump(regdump);
if(size > sizeof(REGDUMP))
__debugbreak();
REGDUMP temp;
if(!_dbg_getregdump(&temp))
{
memset(regdump, 0, size);
return false;
}
memcpy(regdump, &temp, size);
return true;
}
// FIXME all
BRIDGE_IMPEXP bool DbgValToString(const char* string, duint value)
{
return _dbg_valtostring(string, value);
}
BRIDGE_IMPEXP bool DbgMemIsValidReadPtr(duint addr)
{
return _dbg_memisvalidreadptr(addr);
}
// FIXME return
BRIDGE_IMPEXP int DbgGetBpList(BPXTYPE type, BPMAP* list)
{
return _dbg_getbplist(type, list);
}
// FIXME all
BRIDGE_IMPEXP bool DbgCmdExecDirect(const char* cmd)
{
return _dbg_dbgcmddirectexec(cmd);
}
BRIDGE_IMPEXP FUNCTYPE DbgGetFunctionTypeAt(duint addr)
{
BRIDGE_ADDRINFO info;
memset(&info, 0, sizeof(info));
info.flags = flagfunction;
if(!_dbg_addrinfoget(addr, SEG_DEFAULT, &info))
return FUNC_NONE;
duint start = info.function.start;
duint end = info.function.end;
if(start == end || info.function.instrcount == 1)
return FUNC_SINGLE;
else if(addr == start)
return FUNC_BEGIN;
else if(addr == end)
return FUNC_END;
return FUNC_MIDDLE;
}
// FIXME depth
BRIDGE_IMPEXP LOOPTYPE DbgGetLoopTypeAt(duint addr, int depth)
{
BRIDGE_ADDRINFO info;
memset(&info, 0, sizeof(info));
info.flags = flagloop;
info.loop.depth = depth;
if(!_dbg_addrinfoget(addr, SEG_DEFAULT, &info))
return LOOP_NONE;
duint start = info.loop.start;
duint end = info.loop.end;
if(start == end || info.loop.instrcount == 1)
return LOOP_SINGLE;
else if(addr == start)
return LOOP_BEGIN;
else if(addr == end)
return LOOP_END;
return LOOP_MIDDLE;
}
BRIDGE_IMPEXP duint DbgGetBranchDestination(duint addr)
{
return _dbg_getbranchdestination(addr);
}
BRIDGE_IMPEXP void DbgScriptLoad(const char* filename)
{
_dbg_sendmessage(DBG_SCRIPT_LOAD, (void*)filename, 0);
}
// FIXME every?
BRIDGE_IMPEXP void DbgScriptUnload()
{
_dbg_sendmessage(DBG_SCRIPT_UNLOAD, 0, 0);
}
// FIXME "the script?"; destline
BRIDGE_IMPEXP void DbgScriptRun(int destline)
{
_dbg_sendmessage(DBG_SCRIPT_RUN, (void*)(duint)destline, 0);
}
BRIDGE_IMPEXP void DbgScriptStep()
{
_dbg_sendmessage(DBG_SCRIPT_STEP, 0, 0);
}
BRIDGE_IMPEXP bool DbgScriptBpToggle(int line)
{
if(_dbg_sendmessage(DBG_SCRIPT_BPTOGGLE, (void*)(duint)line, 0))
return true;
return false;
}
BRIDGE_IMPEXP bool DbgScriptBpGet(int line)
{
if(_dbg_sendmessage(DBG_SCRIPT_BPGET, (void*)(duint)line, 0))
return true;
return false;
}
BRIDGE_IMPEXP bool DbgScriptCmdExec(const char* command)
{
if(_dbg_sendmessage(DBG_SCRIPT_CMDEXEC, (void*)command, 0))
return true;
return false;
}
BRIDGE_IMPEXP void DbgScriptAbort()
{
_dbg_sendmessage(DBG_SCRIPT_ABORT, 0, 0);
}
BRIDGE_IMPEXP SCRIPTLINETYPE DbgScriptGetLineType(int line)
{
return (SCRIPTLINETYPE)_dbg_sendmessage(DBG_SCRIPT_GETLINETYPE, (void*)(duint)line, 0);
}
BRIDGE_IMPEXP void DbgScriptSetIp(int line)
{
_dbg_sendmessage(DBG_SCRIPT_SETIP, (void*)(duint)line, 0);
}
// FIXME non-null?
BRIDGE_IMPEXP bool DbgScriptGetBranchInfo(int line, SCRIPTBRANCH* info)
{
return !!_dbg_sendmessage(DBG_SCRIPT_GETBRANCHINFO, (void*)(duint)line, info);
}
// FIXME all
BRIDGE_IMPEXP bool DbgSymbolEnum(duint base, CBSYMBOLENUM cbSymbolEnum, void* user)
{
SYMBOLCBINFO cbInfo;
cbInfo.base = base;
cbInfo.cbSymbolEnum = cbSymbolEnum;
cbInfo.user = user;
// These fields are ignored if base != -1, but set them anyway to be safe
cbInfo.start = 0;
cbInfo.end = -1;
cbInfo.symbolMask = SYMBOL_MASK_ALL;
return !!_dbg_sendmessage(DBG_SYMBOL_ENUM, &cbInfo, 0);
}
// FIXME all
BRIDGE_IMPEXP bool DbgSymbolEnumFromCache(duint base, CBSYMBOLENUM cbSymbolEnum, void* user)
{
return DbgSymbolEnum(base, cbSymbolEnum, user);
}
BRIDGE_IMPEXP bool DbgSymbolEnumRange(duint start, duint end, unsigned int symbolMask, CBSYMBOLENUM cbSymbolEnum, void* user)
{
SYMBOLCBINFO cbInfo;
cbInfo.base = -1; // This indicates that start/end/mask is used
cbInfo.cbSymbolEnum = cbSymbolEnum;
cbInfo.user = user;
cbInfo.start = start;
cbInfo.end = end;
cbInfo.symbolMask = symbolMask;
return !!_dbg_sendmessage(DBG_SYMBOL_ENUM, &cbInfo, 0);
}
BRIDGE_IMPEXP bool DbgAssembleAt(duint addr, const char* instruction)
{
if(_dbg_sendmessage(DBG_ASSEMBLE_AT, (void*)addr, (void*)instruction))
return true;
return false;
}
BRIDGE_IMPEXP duint DbgModBaseFromName(const char* name)
{
return _dbg_sendmessage(DBG_MODBASE_FROM_NAME, (void*)name, 0);
}
BRIDGE_IMPEXP void DbgDisasmAt(duint addr, DISASM_INSTR* instr)
{
_dbg_sendmessage(DBG_DISASM_AT, (void*)addr, instr);
}
BRIDGE_IMPEXP bool DbgStackCommentGet(duint addr, STACK_COMMENT* comment)
{
return !!_dbg_sendmessage(DBG_STACK_COMMENT_GET, (void*)addr, comment);
}
BRIDGE_IMPEXP void DbgGetThreadList(THREADLIST* list)
{
_dbg_sendmessage(DBG_GET_THREAD_LIST, list, 0);
}
BRIDGE_IMPEXP void DbgSettingsUpdated()
{
_dbg_sendmessage(DBG_SETTINGS_UPDATED, 0, 0);
}
BRIDGE_IMPEXP void DbgDisasmFastAt(duint addr, BASIC_INSTRUCTION_INFO* basicinfo)
{
_dbg_sendmessage(DBG_DISASM_FAST_AT, (void*)addr, basicinfo);
}
BRIDGE_IMPEXP void DbgMenuEntryClicked(int hEntry)
{
_dbg_sendmessage(DBG_MENU_ENTRY_CLICKED, (void*)(duint)hEntry, 0);
}
// FIXME not sure
BRIDGE_IMPEXP bool DbgFunctionGet(duint addr, duint* start, duint* end)
{
FUNCTION_LOOP_INFO info;
info.addr = addr;
if(!_dbg_sendmessage(DBG_FUNCTION_GET, &info, 0))
return false;
if(start)
*start = info.start;
if(end)
*end = info.end;
return true;
}
// FIXME brief, return
BRIDGE_IMPEXP bool DbgFunctionOverlaps(duint start, duint end)
{
FUNCTION_LOOP_INFO info;
info.start = start;
info.end = end;
if(!_dbg_sendmessage(DBG_FUNCTION_OVERLAPS, &info, 0))
return false;
return true;
}
// FIXME brief, return
BRIDGE_IMPEXP bool DbgFunctionAdd(duint start, duint end)
{
FUNCTION_LOOP_INFO info;
info.start = start;
info.end = end;
info.manual = false;
if(!_dbg_sendmessage(DBG_FUNCTION_ADD, &info, 0))
return false;
return true;
}
// FIXME brief, return
BRIDGE_IMPEXP bool DbgFunctionDel(duint addr)
{
FUNCTION_LOOP_INFO info;
info.addr = addr;
if(!_dbg_sendmessage(DBG_FUNCTION_DEL, &info, 0))
return false;
return true;
}
BRIDGE_IMPEXP bool DbgArgumentGet(duint addr, duint* start, duint* end)
{
FUNCTION_LOOP_INFO info;
info.addr = addr;
if(!_dbg_sendmessage(DBG_ARGUMENT_GET, &info, 0))
return false;
if(start)
*start = info.start;
if(end)
*end = info.end;
return true;
}
BRIDGE_IMPEXP bool DbgArgumentOverlaps(duint start, duint end)
{
FUNCTION_LOOP_INFO info;
info.start = start;
info.end = end;
if(!_dbg_sendmessage(DBG_ARGUMENT_OVERLAPS, &info, 0))
return false;
return true;
}
BRIDGE_IMPEXP bool DbgArgumentAdd(duint start, duint end)
{
FUNCTION_LOOP_INFO info;
info.start = start;
info.end = end;
info.manual = false;
if(!_dbg_sendmessage(DBG_ARGUMENT_ADD, &info, 0))
return false;
return true;
}
BRIDGE_IMPEXP bool DbgArgumentDel(duint addr)
{
FUNCTION_LOOP_INFO info;
info.addr = addr;
if(!_dbg_sendmessage(DBG_ARGUMENT_DEL, &info, 0))
return false;
return true;
}
// FIXME depth
BRIDGE_IMPEXP bool DbgLoopGet(int depth, duint addr, duint* start, duint* end)
{
FUNCTION_LOOP_INFO info;
info.addr = addr;
info.depth = depth;
if(!_dbg_sendmessage(DBG_LOOP_GET, &info, 0))
return false;
if(start)
*start = info.start;
if(end)
*end = info.end;
return true;
}
// FIXME brief, depth, return
BRIDGE_IMPEXP bool DbgLoopOverlaps(int depth, duint start, duint end)
{
FUNCTION_LOOP_INFO info;
info.start = start;
info.end = end;
info.depth = depth;
if(!_dbg_sendmessage(DBG_LOOP_OVERLAPS, &info, 0))
return false;
return true;
}
// FIXME brief, return
BRIDGE_IMPEXP bool DbgLoopAdd(duint start, duint end)
{
FUNCTION_LOOP_INFO info;
info.start = start;
info.end = end;
info.manual = false;
if(!_dbg_sendmessage(DBG_LOOP_ADD, &info, 0))
return false;
return true;
}
// FIXME brief, brief
BRIDGE_IMPEXP bool DbgLoopDel(int depth, duint addr)
{
FUNCTION_LOOP_INFO info;
info.addr = addr;
info.depth = depth;
if(!_dbg_sendmessage(DBG_LOOP_DEL, &info, 0))
return false;
return true;
}
BRIDGE_IMPEXP size_t DbgGetXrefCountAt(duint addr)
{
return _dbg_sendmessage(DBG_GET_XREF_COUNT_AT, (void*)addr, 0);
}
BRIDGE_IMPEXP XREFTYPE DbgGetXrefTypeAt(duint addr)
{
return (XREFTYPE)_dbg_sendmessage(DBG_GET_XREF_TYPE_AT, (void*)addr, 0);
}
BRIDGE_IMPEXP bool DbgXrefAdd(duint addr, duint from)
{
if(!_dbg_sendmessage(DBG_XREF_ADD, (void*)addr, (void*)from))
return false;
return true;
}
BRIDGE_IMPEXP bool DbgXrefDelAll(duint addr)
{
if(!_dbg_sendmessage(DBG_XREF_DEL_ALL, (void*)addr, 0))
return false;
return true;
}
BRIDGE_IMPEXP bool DbgXrefGet(duint addr, XREF_INFO* info)
{
if(!_dbg_sendmessage(DBG_XREF_GET, (void*)addr, info))
return false;
return true;
}
BRIDGE_IMPEXP bool DbgGetWatchList(ListOf(WATCHINFO) list)
{
return !!_dbg_sendmessage(DBG_GET_WATCH_LIST, list, nullptr);
}
// FIXME all
BRIDGE_IMPEXP bool DbgIsRunLocked()
{
if(_dbg_sendmessage(DBG_IS_RUN_LOCKED, 0, 0))
return true;
return false;
}
BRIDGE_IMPEXP bool DbgIsBpDisabled(duint addr)
{
if(_dbg_sendmessage(DBG_IS_BP_DISABLED, (void*)addr, 0))
return true;
return false;
}
BRIDGE_IMPEXP bool DbgSetAutoCommentAt(duint addr, const char* text)
{
if(_dbg_sendmessage(DBG_SET_AUTO_COMMENT_AT, (void*)addr, (void*)text))
return true;
return false;
}
// FIXME brief
BRIDGE_IMPEXP void DbgClearAutoCommentRange(duint start, duint end)
{
_dbg_sendmessage(DBG_DELETE_AUTO_COMMENT_RANGE, (void*)start, (void*)end);
}
BRIDGE_IMPEXP bool DbgSetAutoLabelAt(duint addr, const char* text)
{
if(_dbg_sendmessage(DBG_SET_AUTO_LABEL_AT, (void*)addr, (void*)text))
return true;
return false;
}
// FIXME brief
BRIDGE_IMPEXP void DbgClearAutoLabelRange(duint start, duint end)
{
_dbg_sendmessage(DBG_DELETE_AUTO_LABEL_RANGE, (void*)start, (void*)end);
}
BRIDGE_IMPEXP bool DbgSetAutoBookmarkAt(duint addr)
{
if(_dbg_sendmessage(DBG_SET_AUTO_BOOKMARK_AT, (void*)addr, 0))
return true;
return false;
}
// FIXME brief
BRIDGE_IMPEXP void DbgClearAutoBookmarkRange(duint start, duint end)
{
_dbg_sendmessage(DBG_DELETE_AUTO_BOOKMARK_RANGE, (void*)start, (void*)end);
}
BRIDGE_IMPEXP bool DbgSetAutoFunctionAt(duint start, duint end)
{
if(_dbg_sendmessage(DBG_SET_AUTO_FUNCTION_AT, (void*)start, (void*)end))
return true;
return false;
}
// FIXME brief
BRIDGE_IMPEXP void DbgClearAutoFunctionRange(duint start, duint end)
{
_dbg_sendmessage(DBG_DELETE_AUTO_FUNCTION_RANGE, (void*)start, (void*)end);
}
// FIXME size of the buffer?
BRIDGE_IMPEXP bool DbgGetStringAt(duint addr, char* text)
{
if(_dbg_sendmessage(DBG_GET_STRING_AT, (void*)addr, text))
return true;
return false;
}
BRIDGE_IMPEXP const DBGFUNCTIONS* DbgFunctions()
{
return (const DBGFUNCTIONS*)_dbg_sendmessage(DBG_GET_FUNCTIONS, 0, 0);
}
BRIDGE_IMPEXP bool DbgWinEvent(MSG* message, long* result)
{
if(_dbg_sendmessage(DBG_WIN_EVENT, message, result))
return true;
return false;
}
BRIDGE_IMPEXP bool DbgWinEventGlobal(MSG* message)
{
if(_dbg_sendmessage(DBG_WIN_EVENT_GLOBAL, message, 0))
return true;
return false;
}
BRIDGE_IMPEXP bool DbgIsRunning()
{
return !DbgIsRunLocked();
}
BRIDGE_IMPEXP duint DbgGetTimeWastedCounter()
{
return _dbg_sendmessage(DBG_GET_TIME_WASTED_COUNTER, nullptr, nullptr);
}
BRIDGE_IMPEXP ARGTYPE DbgGetArgTypeAt(duint addr)
{
BRIDGE_ADDRINFO info;
memset(&info, 0, sizeof(info));
info.flags = flagargs;
if(!_dbg_addrinfoget(addr, SEG_DEFAULT, &info))
return ARG_NONE;
duint start = info.args.start;
duint end = info.args.end;
if(start == end || info.args.instrcount == 1)
return ARG_SINGLE;
else if(addr == start)
return ARG_BEGIN;
else if(addr == end)
return ARG_END;
return ARG_MIDDLE;
}
BRIDGE_IMPEXP void* DbgGetEncodeTypeBuffer(duint addr, duint* size)
{
return (void*)_dbg_sendmessage(DBG_GET_ENCODE_TYPE_BUFFER, (void*)addr, size);
}
BRIDGE_IMPEXP void DbgReleaseEncodeTypeBuffer(void* buffer)
{
_dbg_sendmessage(DBG_RELEASE_ENCODE_TYPE_BUFFER, buffer, nullptr);
}
BRIDGE_IMPEXP ENCODETYPE DbgGetEncodeTypeAt(duint addr, duint size)
{
return (ENCODETYPE)_dbg_sendmessage(DBG_ENCODE_TYPE_GET, (void*)addr, (void*)size);
}
BRIDGE_IMPEXP duint DbgGetEncodeSizeAt(duint addr, duint codesize)
{
return _dbg_sendmessage(DBG_ENCODE_SIZE_GET, (void*)addr, (void*)codesize);
}
BRIDGE_IMPEXP bool DbgSetEncodeType(duint addr, duint size, ENCODETYPE type)
{
return _dbg_encodetypeset(addr, size, type);
}
BRIDGE_IMPEXP void DbgDelEncodeTypeRange(duint start, duint end)
{
_dbg_sendmessage(DBG_DELETE_ENCODE_TYPE_RANGE, (void*)start, (void*)end);
}
BRIDGE_IMPEXP void DbgDelEncodeTypeSegment(duint start)
{
_dbg_sendmessage(DBG_DELETE_ENCODE_TYPE_SEG, (void*)start, 0);
}
BRIDGE_IMPEXP void DbgSelChanged(int hWindow, duint VA)
{
_dbg_sendmessage(DBG_SELCHANGED, (void*)hWindow, (void*)VA);
}
BRIDGE_IMPEXP HANDLE DbgGetProcessHandle()
{
return (HANDLE)_dbg_sendmessage(DBG_GET_PROCESS_HANDLE, nullptr, nullptr);
}
BRIDGE_IMPEXP HANDLE DbgGetThreadHandle()
{
return (HANDLE)_dbg_sendmessage(DBG_GET_THREAD_HANDLE, nullptr, nullptr);
}
BRIDGE_IMPEXP DWORD DbgGetProcessId()
{
return (DWORD)_dbg_sendmessage(DBG_GET_PROCESS_ID, nullptr, nullptr);
}
BRIDGE_IMPEXP DWORD DbgGetThreadId()
{
return (DWORD)_dbg_sendmessage(DBG_GET_THREAD_ID, nullptr, nullptr);
}
BRIDGE_IMPEXP duint DbgGetPebAddress(DWORD ProcessId)
{
return (duint)_dbg_sendmessage(DBG_GET_PEB_ADDRESS, (void*)ProcessId, nullptr);
}
BRIDGE_IMPEXP duint DbgGetTebAddress(DWORD ThreadId)
{
return (duint)_dbg_sendmessage(DBG_GET_TEB_ADDRESS, (void*)ThreadId, nullptr);
}
BRIDGE_IMPEXP bool DbgAnalyzeFunction(duint entry, BridgeCFGraphList* graph)
{
return !!_dbg_sendmessage(DBG_ANALYZE_FUNCTION, (void*)entry, graph);
}
BRIDGE_IMPEXP duint DbgEval(const char* expression, bool* success)
{
duint value = 0;
auto res = _dbg_valfromstring(expression, &value);
if(success)
*success = res;
return value;
}
BRIDGE_IMPEXP void DbgMenuPrepare(GUIMENUTYPE hMenu)
{
_dbg_sendmessage(DBG_MENU_PREPARE, (void*)hMenu, nullptr);
}
BRIDGE_IMPEXP void DbgGetSymbolInfo(const SYMBOLPTR* symbolptr, SYMBOLINFO* info)
{
_dbg_sendmessage(DBG_GET_SYMBOL_INFO, (void*)symbolptr, info);
}
BRIDGE_IMPEXP DEBUG_ENGINE DbgGetDebugEngine()
{
duint setting = DebugEngineTitanEngine;
if(!BridgeSettingGetUint("Engine", "DebugEngine", &setting))
{
BridgeSettingSetUint("Engine", "DebugEngine", setting);
}
return (DEBUG_ENGINE)setting;
}
BRIDGE_IMPEXP bool DbgGetSymbolInfoAt(duint addr, SYMBOLINFO* info)
{
return !!_dbg_sendmessage(DBG_GET_SYMBOL_INFO_AT, (void*)addr, info);
}
BRIDGE_IMPEXP duint DbgXrefAddMulti(const XREF_EDGE* edges, duint count)
{
return (duint)_dbg_sendmessage(DBG_XREF_ADD_MULTI, (void*)edges, (void*)count);
}
BRIDGE_IMPEXP const char* GuiTranslateText(const char* Source)
{
EnterCriticalSection(&csTranslate);
const char* text = _gui_translate_text(Source);
LeaveCriticalSection(&csTranslate);
return text;
}
BRIDGE_IMPEXP void GuiDisasmAt(duint addr, duint cip)
{
_gui_sendmessage(GUI_DISASSEMBLE_AT, (void*)addr, (void*)cip);
}
BRIDGE_IMPEXP void GuiSetDebugState(DBGSTATE state)
{
_gui_sendmessage(GUI_SET_DEBUG_STATE, (void*)state, (void*)false);
}
BRIDGE_IMPEXP void GuiSetDebugStateFast(DBGSTATE state)
{
_gui_sendmessage(GUI_SET_DEBUG_STATE, (void*)state, (void*)true);
}
BRIDGE_IMPEXP void GuiAddLogMessage(const char* msg)
{
_gui_sendmessage(GUI_ADD_MSG_TO_LOG, (void*)msg, 0);
}
BRIDGE_IMPEXP void GuiAddLogMessageHtml(const char* msg)
{
_gui_sendmessage(GUI_ADD_MSG_TO_LOG_HTML, (void*)msg, 0);
}
BRIDGE_IMPEXP void GuiLogClear()
{
_gui_sendmessage(GUI_CLEAR_LOG, 0, 0);
}
BRIDGE_IMPEXP void GuiLogSave(const char* filename)
{
_gui_sendmessage(GUI_SAVE_LOG, (void*)filename, 0);
}
BRIDGE_IMPEXP void GuiLogRedirect(const char* filename)
{
_gui_sendmessage(GUI_REDIRECT_LOG, (void*)filename, 0);
}
BRIDGE_IMPEXP void GuiLogRedirectStop()
{
_gui_sendmessage(GUI_STOP_REDIRECT_LOG, 0, 0);
}
BRIDGE_IMPEXP void GuiUpdateEnable(bool updateNow)
{
bDisableGUIUpdate = false;
if(updateNow)
GuiUpdateAllViews();
}
BRIDGE_IMPEXP void GuiUpdateDisable()
{
bDisableGUIUpdate = true;
}
BRIDGE_IMPEXP bool GuiIsUpdateDisabled()
{
return bDisableGUIUpdate;
}
BRIDGE_IMPEXP void GuiUpdateAllViews()
{
CHECK_GUI_UPDATE_DISABLED
GuiUpdateRegisterView();
GuiUpdateDisassemblyView();
GuiUpdateBreakpointsView();
GuiUpdateDumpView();
GuiUpdateWatchView();
GuiUpdateThreadView();
GuiUpdateSideBar();
//Patches are not refreshed here, see #1407
GuiUpdateCallStack();
GuiRepaintTableView();
GuiUpdateSEHChain();
GuiUpdateArgumentWidget();
GuiUpdateMemoryView();
GuiUpdateGraphView();
GuiUpdateTypeWidget();
GuiUpdateTraceBrowser();
}
BRIDGE_IMPEXP void GuiUpdateRegisterView()
{
CHECK_GUI_UPDATE_DISABLED
_gui_sendmessage(GUI_UPDATE_REGISTER_VIEW, 0, 0);
}
BRIDGE_IMPEXP void GuiUpdateDisassemblyView()
{
CHECK_GUI_UPDATE_DISABLED
_gui_sendmessage(GUI_UPDATE_DISASSEMBLY_VIEW, 0, 0);
}
BRIDGE_IMPEXP void GuiUpdateBreakpointsView()
{
CHECK_GUI_UPDATE_DISABLED
_gui_sendmessage(GUI_UPDATE_BREAKPOINTS_VIEW, 0, 0);
}
BRIDGE_IMPEXP void GuiUpdateWindowTitle(const char* filename)
{
CHECK_GUI_UPDATE_DISABLED
_gui_sendmessage(GUI_UPDATE_WINDOW_TITLE, (void*)filename, 0);
}
BRIDGE_IMPEXP HWND GuiGetWindowHandle()
{
return (HWND)_gui_sendmessage(GUI_GET_WINDOW_HANDLE, 0, 0);
}
BRIDGE_IMPEXP void GuiDumpAt(duint va)
{
_gui_sendmessage(GUI_DUMP_AT, (void*)va, 0);
}
BRIDGE_IMPEXP void GuiScriptAdd(int count, const char** lines)
{
_gui_sendmessage(GUI_SCRIPT_ADD, (void*)(duint)count, (void*)lines);
}
BRIDGE_IMPEXP void GuiScriptClear()
{
_gui_sendmessage(GUI_SCRIPT_CLEAR, 0, 0);
}
BRIDGE_IMPEXP void GuiScriptSetIp(int line)
{
_gui_sendmessage(GUI_SCRIPT_SETIP, (void*)(duint)line, 0);
}
BRIDGE_IMPEXP void GuiScriptError(int line, const char* message)
{
_gui_sendmessage(GUI_SCRIPT_ERROR, (void*)(duint)line, (void*)message);
}
BRIDGE_IMPEXP void GuiScriptSetTitle(const char* title)
{
_gui_sendmessage(GUI_SCRIPT_SETTITLE, (void*)title, 0);
}
BRIDGE_IMPEXP void GuiScriptSetInfoLine(int line, const char* info)
{
_gui_sendmessage(GUI_SCRIPT_SETINFOLINE, (void*)(duint)line, (void*)info);
}
BRIDGE_IMPEXP void GuiScriptMessage(const char* message)
{
_gui_sendmessage(GUI_SCRIPT_MESSAGE, (void*)message, 0);
}
BRIDGE_IMPEXP int GuiScriptMsgyn(const char* message)
{
return (int)(duint)_gui_sendmessage(GUI_SCRIPT_MSGYN, (void*)message, 0);
}
BRIDGE_IMPEXP void GuiScriptEnableHighlighting(bool enable)
{
_gui_sendmessage(GUI_SCRIPT_ENABLEHIGHLIGHTING, (void*)(duint)enable, 0);
}
BRIDGE_IMPEXP void GuiSymbolLogAdd(const char* message)
{
_gui_sendmessage(GUI_SYMBOL_LOG_ADD, (void*)message, 0);
}
BRIDGE_IMPEXP void GuiSymbolLogClear()
{
_gui_sendmessage(GUI_SYMBOL_LOG_CLEAR, 0, 0);
}
BRIDGE_IMPEXP void GuiSymbolSetProgress(int percent)
{
_gui_sendmessage(GUI_SYMBOL_SET_PROGRESS, (void*)(duint)percent, 0);
}
BRIDGE_IMPEXP void GuiSymbolUpdateModuleList(int count, SYMBOLMODULEINFO* modules)
{
_gui_sendmessage(GUI_SYMBOL_UPDATE_MODULE_LIST, (void*)(duint)count, (void*)modules);
}
BRIDGE_IMPEXP void GuiReferenceAddColumn(int width, const char* title)
{
_gui_sendmessage(GUI_REF_ADDCOLUMN, (void*)(duint)width, (void*)title);
}
BRIDGE_IMPEXP void GuiSymbolRefreshCurrent()
{
_gui_sendmessage(GUI_SYMBOL_REFRESH_CURRENT, 0, 0);
}
BRIDGE_IMPEXP void GuiReferenceSetRowCount(int count)
{
_gui_sendmessage(GUI_REF_SETROWCOUNT, (void*)(duint)count, 0);
}
BRIDGE_IMPEXP int GuiReferenceGetRowCount()
{
return (int)(duint)_gui_sendmessage(GUI_REF_GETROWCOUNT, 0, 0);
}
BRIDGE_IMPEXP int GuiReferenceSearchGetRowCount()
{
return int(_gui_sendmessage(GUI_REF_SEARCH_GETROWCOUNT, 0, 0));
}
BRIDGE_IMPEXP void GuiReferenceDeleteAllColumns()
{
_gui_sendmessage(GUI_REF_DELETEALLCOLUMNS, 0, 0);
}
BRIDGE_IMPEXP void GuiReferenceInitialize(const char* name)
{
_gui_sendmessage(GUI_REF_INITIALIZE, (void*)name, 0);
}
BRIDGE_IMPEXP void GuiReferenceSetCellContent(int row, int col, const char* str)
{
CELLINFO info;
info.row = row;
info.col = col;
info.str = str;
_gui_sendmessage(GUI_REF_SETCELLCONTENT, &info, 0);
}
BRIDGE_IMPEXP char* GuiReferenceGetCellContent(int row, int col)
{
return (char*)_gui_sendmessage(GUI_REF_GETCELLCONTENT, (void*)(duint)row, (void*)(duint)col);
}
BRIDGE_IMPEXP char* GuiReferenceSearchGetCellContent(int row, int col)
{
return (char*)_gui_sendmessage(GUI_REF_SEARCH_GETCELLCONTENT, (void*)row, (void*)col);
}
BRIDGE_IMPEXP void GuiReferenceReloadData()
{
_gui_sendmessage(GUI_REF_RELOADDATA, 0, 0);
}
BRIDGE_IMPEXP void GuiReferenceSetSingleSelection(int index, bool scroll)
{
_gui_sendmessage(GUI_REF_SETSINGLESELECTION, (void*)(duint)index, (void*)(duint)scroll);
}
BRIDGE_IMPEXP void GuiReferenceSetProgress(int progress)
{
_gui_sendmessage(GUI_REF_SETPROGRESS, (void*)(duint)progress, 0);
}
BRIDGE_IMPEXP void GuiReferenceSetCurrentTaskProgress(int progress, const char* taskTitle)
{
_gui_sendmessage(GUI_REF_SETCURRENTTASKPROGRESS, (void*)(duint)progress, (void*)taskTitle);
}
BRIDGE_IMPEXP void GuiReferenceSetSearchStartCol(int col)
{
_gui_sendmessage(GUI_REF_SETSEARCHSTARTCOL, (void*)(duint)col, 0);
}
BRIDGE_IMPEXP void GuiStackDumpAt(duint addr, duint csp)
{
_gui_sendmessage(GUI_STACK_DUMP_AT, (void*)addr, (void*)csp);
}
BRIDGE_IMPEXP void GuiUpdateDumpView()
{
CHECK_GUI_UPDATE_DISABLED
_gui_sendmessage(GUI_UPDATE_DUMP_VIEW, 0, 0);
}
BRIDGE_IMPEXP void GuiUpdateWatchView()
{
CHECK_GUI_UPDATE_DISABLED
_gui_sendmessage(GUI_UPDATE_WATCH_VIEW, 0, 0);
}
BRIDGE_IMPEXP void GuiUpdateMemoryView()
{
CHECK_GUI_UPDATE_DISABLED
_gui_sendmessage(GUI_UPDATE_MEMORY_VIEW, 0, 0);
}
BRIDGE_IMPEXP void GuiUpdateThreadView()
{
CHECK_GUI_UPDATE_DISABLED
_gui_sendmessage(GUI_UPDATE_THREAD_VIEW, 0, 0);
}
BRIDGE_IMPEXP void GuiAddRecentFile(const char* file)
{
_gui_sendmessage(GUI_ADD_RECENT_FILE, (void*)file, 0);
}
BRIDGE_IMPEXP void GuiSetLastException(unsigned int exception)
{
_gui_sendmessage(GUI_SET_LAST_EXCEPTION, (void*)(duint)exception, 0);
}
BRIDGE_IMPEXP bool GuiGetDisassembly(duint addr, char* text)
{
return !!_gui_sendmessage(GUI_GET_DISASSEMBLY, (void*)addr, text);
}
BRIDGE_IMPEXP int GuiMenuAdd(int hMenu, const char* title)
{
return (int)(duint)_gui_sendmessage(GUI_MENU_ADD, (void*)(duint)hMenu, (void*)title);
}
BRIDGE_IMPEXP int GuiMenuAddEntry(int hMenu, const char* title)
{
return (int)(duint)_gui_sendmessage(GUI_MENU_ADD_ENTRY, (void*)(duint)hMenu, (void*)title);
}
BRIDGE_IMPEXP void GuiMenuAddSeparator(int hMenu)
{
_gui_sendmessage(GUI_MENU_ADD_SEPARATOR, (void*)(duint)hMenu, 0);
}
BRIDGE_IMPEXP void GuiMenuClear(int hMenu)
{
_gui_sendmessage(GUI_MENU_CLEAR, (void*)(duint)hMenu, 0);
}
BRIDGE_IMPEXP void GuiMenuRemove(int hEntryMenu)
{
_gui_sendmessage(GUI_MENU_REMOVE, (void*)(duint)hEntryMenu, 0);
}
BRIDGE_IMPEXP bool GuiSelectionGet(GUISELECTIONTYPE hWindow, SELECTIONDATA* selection)
{
return !!_gui_sendmessage(GUI_SELECTION_GET, (void*)(duint)hWindow, selection);
}
BRIDGE_IMPEXP bool GuiSelectionSet(GUISELECTIONTYPE hWindow, const SELECTIONDATA* selection)
{
return !!_gui_sendmessage(GUI_SELECTION_SET, (void*)(duint)hWindow, (void*)selection);
}
BRIDGE_IMPEXP bool GuiGetLineWindow(const char* title, char* text)
{
return !!_gui_sendmessage(GUI_GETLINE_WINDOW, (void*)title, text);
}
BRIDGE_IMPEXP void GuiAutoCompleteAddCmd(const char* cmd)
{
_gui_sendmessage(GUI_AUTOCOMPLETE_ADDCMD, (void*)cmd, 0);
}
BRIDGE_IMPEXP void GuiAutoCompleteDelCmd(const char* cmd)
{
_gui_sendmessage(GUI_AUTOCOMPLETE_DELCMD, (void*)cmd, 0);
}
BRIDGE_IMPEXP void GuiAutoCompleteClearAll()
{
_gui_sendmessage(GUI_AUTOCOMPLETE_CLEARALL, 0, 0);
}
BRIDGE_IMPEXP void GuiAddStatusBarMessage(const char* msg)
{
_gui_sendmessage(GUI_ADD_MSG_TO_STATUSBAR, (void*)msg, 0);
}
BRIDGE_IMPEXP void GuiUpdateSideBar()
{
CHECK_GUI_UPDATE_DISABLED
_gui_sendmessage(GUI_UPDATE_SIDEBAR, 0, 0);
}
BRIDGE_IMPEXP void GuiRepaintTableView()
{
CHECK_GUI_UPDATE_DISABLED
_gui_sendmessage(GUI_REPAINT_TABLE_VIEW, 0, 0);
}
BRIDGE_IMPEXP void GuiUpdatePatches()
{
CHECK_GUI_UPDATE_DISABLED
_gui_sendmessage(GUI_UPDATE_PATCHES, 0, 0);
}
BRIDGE_IMPEXP void GuiUpdateCallStack()
{
CHECK_GUI_UPDATE_DISABLED
_gui_sendmessage(GUI_UPDATE_CALLSTACK, 0, 0);
}
BRIDGE_IMPEXP void GuiUpdateSEHChain()
{
CHECK_GUI_UPDATE_DISABLED
_gui_sendmessage(GUI_UPDATE_SEHCHAIN, 0, 0);
}
extern "C" __declspec(dllexport) void GuiLoadSourceFile(const char* path, int line)
{
return;
}
BRIDGE_IMPEXP void GuiLoadSourceFileEx(const char* path, duint addr)
{
_gui_sendmessage(GUI_LOAD_SOURCE_FILE, (void*)path, (void*)addr);
}
BRIDGE_IMPEXP void GuiMenuSetIcon(int hMenu, const ICONDATA* icon)
{
_gui_sendmessage(GUI_MENU_SET_ICON, (void*)hMenu, (void*)icon);
}
BRIDGE_IMPEXP void GuiMenuSetEntryIcon(int hEntry, const ICONDATA* icon)
{
_gui_sendmessage(GUI_MENU_SET_ENTRY_ICON, (void*)hEntry, (void*)icon);
}
BRIDGE_IMPEXP void GuiMenuSetEntryChecked(int hEntry, bool checked)
{
_gui_sendmessage(GUI_MENU_SET_ENTRY_CHECKED, (void*)hEntry, (void*)checked);
}
BRIDGE_IMPEXP void GuiMenuSetVisible(int hMenu, bool visible)
{
_gui_sendmessage(GUI_MENU_SET_VISIBLE, (void*)hMenu, (void*)visible);
}
BRIDGE_IMPEXP void GuiMenuSetEntryVisible(int hEntry, bool visible)
{
_gui_sendmessage(GUI_MENU_SET_ENTRY_VISIBLE, (void*)hEntry, (void*)visible);
}
BRIDGE_IMPEXP void GuiMenuSetName(int hMenu, const char* name)
{
_gui_sendmessage(GUI_MENU_SET_NAME, (void*)hMenu, (void*)name);
}
BRIDGE_IMPEXP void GuiMenuSetEntryName(int hEntry, const char* name)
{
_gui_sendmessage(GUI_MENU_SET_ENTRY_NAME, (void*)hEntry, (void*)name);
}
BRIDGE_IMPEXP void GuiMenuSetEntryHotkey(int hEntry, const char* hack)
{
_gui_sendmessage(GUI_MENU_SET_ENTRY_HOTKEY, (void*)hEntry, (void*)hack);
}
BRIDGE_IMPEXP void GuiShowCpu()
{
_gui_sendmessage(GUI_SHOW_CPU, 0, 0);
}
BRIDGE_IMPEXP void GuiAddQWidgetTab(void* qWidget)
{
_gui_sendmessage(GUI_ADD_QWIDGET_TAB, qWidget, nullptr);
}
BRIDGE_IMPEXP void GuiShowQWidgetTab(void* qWidget)
{
_gui_sendmessage(GUI_SHOW_QWIDGET_TAB, qWidget, nullptr);
}
BRIDGE_IMPEXP void GuiCloseQWidgetTab(void* qWidget)
{
_gui_sendmessage(GUI_CLOSE_QWIDGET_TAB, qWidget, nullptr);
}
BRIDGE_IMPEXP void GuiExecuteOnGuiThread(GUICALLBACK cbGuiThread)
{
GuiExecuteOnGuiThreadEx([](void* cb)
{
((GUICALLBACK)cb)();
}, cbGuiThread);
}
BRIDGE_IMPEXP void GuiUpdateTimeWastedCounter()
{
_gui_sendmessage(GUI_UPDATE_TIME_WASTED_COUNTER, nullptr, nullptr);
}
BRIDGE_IMPEXP void GuiSetGlobalNotes(const char* text)
{
_gui_sendmessage(GUI_SET_GLOBAL_NOTES, (void*)text, nullptr);
}
BRIDGE_IMPEXP void GuiGetGlobalNotes(char** text)
{
_gui_sendmessage(GUI_GET_GLOBAL_NOTES, text, nullptr);
}
BRIDGE_IMPEXP void GuiSetDebuggeeNotes(const char* text)
{
_gui_sendmessage(GUI_SET_DEBUGGEE_NOTES, (void*)text, nullptr);
}
BRIDGE_IMPEXP void GuiGetDebuggeeNotes(char** text)
{
_gui_sendmessage(GUI_GET_DEBUGGEE_NOTES, text, nullptr);
}
BRIDGE_IMPEXP void GuiDumpAtN(duint va, int index)
{
_gui_sendmessage(GUI_DUMP_AT_N, (void*)va, (void*)index);
}
BRIDGE_IMPEXP void GuiDisplayWarning(const char* title, const char* text)
{
_gui_sendmessage(GUI_DISPLAY_WARNING, (void*)title, (void*)text);
}
BRIDGE_IMPEXP void GuiRegisterScriptLanguage(SCRIPTTYPEINFO* info)
{
_gui_sendmessage(GUI_REGISTER_SCRIPT_LANG, (void*)info, nullptr);
}
BRIDGE_IMPEXP void GuiUnregisterScriptLanguage(int id)
{
_gui_sendmessage(GUI_UNREGISTER_SCRIPT_LANG, (void*)id, nullptr);
}
BRIDGE_IMPEXP void GuiUpdateArgumentWidget()
{
CHECK_GUI_UPDATE_DISABLED
_gui_sendmessage(GUI_UPDATE_ARGUMENT_VIEW, nullptr, nullptr);
}
BRIDGE_IMPEXP void GuiFocusView(int hWindow)
{
_gui_sendmessage(GUI_FOCUS_VIEW, (void*)hWindow, nullptr);
}
BRIDGE_IMPEXP bool GuiLoadGraph(BridgeCFGraphList* graph, duint addr)
{
return !!_gui_sendmessage(GUI_LOAD_GRAPH, graph, (void*)addr);
}
BRIDGE_IMPEXP duint GuiGraphAt(duint addr)
{
return (duint)_gui_sendmessage(GUI_GRAPH_AT, (void*)addr, nullptr);
}
BRIDGE_IMPEXP void GuiUpdateGraphView()
{
CHECK_GUI_UPDATE_DISABLED
_gui_sendmessage(GUI_UPDATE_GRAPH_VIEW, nullptr, nullptr);
}
BRIDGE_IMPEXP void GuiDisableLog()
{
_gui_sendmessage(GUI_SET_LOG_ENABLED, (void*)0, nullptr);
}
BRIDGE_IMPEXP void GuiEnableLog()
{
_gui_sendmessage(GUI_SET_LOG_ENABLED, (void*)1, nullptr);
}
BRIDGE_IMPEXP bool GuiIsLogEnabled()
{
return !!_gui_sendmessage(GUI_IS_LOG_ENABLED, nullptr, nullptr);
}
BRIDGE_IMPEXP void GuiAddFavouriteTool(const char* name, const char* description)
{
_gui_sendmessage(GUI_ADD_FAVOURITE_TOOL, (void*)name, (void*)description);
}
BRIDGE_IMPEXP void GuiAddFavouriteCommand(const char* name, const char* shortcut)
{
_gui_sendmessage(GUI_ADD_FAVOURITE_COMMAND, (void*)name, (void*)shortcut);
}
BRIDGE_IMPEXP void GuiSetFavouriteToolShortcut(const char* name, const char* shortcut)
{
_gui_sendmessage(GUI_SET_FAVOURITE_TOOL_SHORTCUT, (void*)name, (void*)shortcut);
}
BRIDGE_IMPEXP void GuiFoldDisassembly(duint startAddress, duint length)
{
_gui_sendmessage(GUI_FOLD_DISASSEMBLY, (void*)startAddress, (void*)length);
}
BRIDGE_IMPEXP void GuiSelectInMemoryMap(duint addr)
{
_gui_sendmessage(GUI_SELECT_IN_MEMORY_MAP, (void*)addr, nullptr);
}
BRIDGE_IMPEXP void GuiGetActiveView(ACTIVEVIEW* activeView)
{
_gui_sendmessage(GUI_GET_ACTIVE_VIEW, activeView, nullptr);
}
BRIDGE_IMPEXP void GuiAddInfoLine(const char* infoLine)
{
_gui_sendmessage(GUI_ADD_INFO_LINE, (void*)infoLine, nullptr);
}
BRIDGE_IMPEXP void GuiProcessEvents()
{
_gui_sendmessage(GUI_PROCESS_EVENTS, nullptr, nullptr);
}
BRIDGE_IMPEXP void* GuiTypeAddNode(void* parent, const TYPEDESCRIPTOR* type)
{
return _gui_sendmessage(GUI_TYPE_ADDNODE, parent, (void*)type);
}
BRIDGE_IMPEXP bool GuiTypeClear()
{
return !!_gui_sendmessage(GUI_TYPE_CLEAR, nullptr, nullptr);
}
BRIDGE_IMPEXP void GuiUpdateTypeWidget()
{
_gui_sendmessage(GUI_UPDATE_TYPE_WIDGET, nullptr, nullptr);
}
BRIDGE_IMPEXP void GuiCloseApplication()
{
_gui_sendmessage(GUI_CLOSE_APPLICATION, nullptr, nullptr);
}
BRIDGE_IMPEXP void GuiFlushLog()
{
_gui_sendmessage(GUI_FLUSH_LOG, nullptr, nullptr);
}
BRIDGE_IMPEXP void GuiReferenceAddCommand(const char* title, const char* command)
{
_gui_sendmessage(GUI_REF_ADDCOMMAND, (void*)title, (void*)command);
}
BRIDGE_IMPEXP void GuiUpdateTraceBrowser()
{
CHECK_GUI_UPDATE_DISABLED
_gui_sendmessage(GUI_UPDATE_TRACE_BROWSER, nullptr, nullptr);
}
BRIDGE_IMPEXP void GuiOpenTraceFile(const char* fileName)
{
_gui_sendmessage(GUI_OPEN_TRACE_FILE, (void*)fileName, nullptr);
}
BRIDGE_IMPEXP void GuiInvalidateSymbolSource(duint base)
{
_gui_sendmessage(GUI_INVALIDATE_SYMBOL_SOURCE, (void*)base, nullptr);
}
BRIDGE_IMPEXP void GuiExecuteOnGuiThreadEx(GUICALLBACKEX cbGuiThread, void* userdata)
{
_gui_sendmessage(GUI_EXECUTE_ON_GUI_THREAD, (void*)cbGuiThread, userdata);
}
BRIDGE_IMPEXP void GuiGetCurrentGraph(BridgeCFGraphList* graphList)
{
_gui_sendmessage(GUI_GET_CURRENT_GRAPH, graphList, nullptr);
}
BRIDGE_IMPEXP void GuiShowReferences()
{
_gui_sendmessage(GUI_SHOW_REF, 0, 0);
}
BRIDGE_IMPEXP void GuiSelectInSymbolsTab(duint addr)
{
_gui_sendmessage(GUI_SELECT_IN_SYMBOLS_TAB, (void*)addr, nullptr);
}
BRIDGE_IMPEXP void GuiGotoTrace(duint index)
{
_gui_sendmessage(GUI_GOTO_TRACE, (void*)index, nullptr);
}
BRIDGE_IMPEXP void GuiShowTrace()
{
_gui_sendmessage(GUI_SHOW_TRACE, nullptr, nullptr);
}
BRIDGE_IMPEXP DWORD GuiGetMainThreadId()
{
return (DWORD)(duint)_gui_sendmessage(GUI_GET_MAIN_THREAD_ID, nullptr, nullptr);
}
BOOL WINAPI DllMain(HINSTANCE hinstDLL, DWORD fdwReason, LPVOID lpvReserved)
{
hInst = hinstDLL;
return TRUE;
} |
C/C++ | x64dbg-development/src/bridge/bridgemain.h | #ifndef _BRIDGEMAIN_H_
#define _BRIDGEMAIN_H_
#include <windows.h>
#ifndef __cplusplus
#include <stdbool.h>
#define DEFAULT_PARAM(name, value) name
#else
#define DEFAULT_PARAM(name, value) name = value
#endif
//default structure alignments forced
#ifdef _WIN64
#pragma pack(push, 16)
#else //x86
#pragma pack(push, 8)
#endif //_WIN64
#ifdef _WIN64
typedef unsigned long long duint;
typedef signed long long dsint;
#else
typedef unsigned long duint;
typedef signed long dsint;
#endif //_WIN64
#ifndef BRIDGE_IMPEXP
#ifdef BUILD_BRIDGE
#define BRIDGE_IMPEXP __declspec(dllexport)
#else
#define BRIDGE_IMPEXP __declspec(dllimport)
#endif //BUILD_BRIDGE
#endif //BRIDGE_IMPEXP
#ifdef __cplusplus
extern "C"
{
#endif
//Bridge defines
#define MAX_SETTING_SIZE 65536
#define DBG_VERSION 25
//Bridge functions
/// <summary>
/// Initialize the bridge.
/// </summary>
/// <returns>On error it returns a non-null error message.</returns>
BRIDGE_IMPEXP const wchar_t* BridgeInit();
BRIDGE_IMPEXP HMODULE WINAPI BridgeLoadLibraryCheckedW(const wchar_t* szDll, bool allowFailure);
BRIDGE_IMPEXP HMODULE WINAPI BridgeLoadLibraryCheckedA(const char* szDll, bool allowFailure);
/// <summary>
/// Start the bridge.
/// </summary>
/// <returns>On error it returns a non-null error message.</returns>
BRIDGE_IMPEXP const wchar_t* BridgeStart();
/// <summary>
/// Allocate buffer. Use BridgeFree to free the buffer.
/// </summary>
/// <param name="size">Size in bytes of the buffer to allocate.</param>
/// <returns>A pointer to the allocated buffer. This function will trigger a crash dump if unsuccessful.</returns>
BRIDGE_IMPEXP void* BridgeAlloc(size_t size);
/// <summary>
/// Free buffer allocated by BridgeAlloc.
/// </summary>
/// <param name="ptr">Buffer to free.</param>
BRIDGE_IMPEXP void BridgeFree(void* ptr);
/// <summary>
/// Get a string setting from the in-memory setting store.
/// </summary>
/// <param name="section">Section the setting is in. Cannot be null.</param>
/// <param name="key">Setting key (name). Cannot be null.</param>
/// <param name="value">Output buffer for the value. Should be of MAX_SETTING_SIZE. Cannot be null.</param>
/// <returns>True if the setting was found and copied in the value parameter.</returns>
BRIDGE_IMPEXP bool BridgeSettingGet(const char* section, const char* key, char* value);
/// <summary>
/// Get an integer setting from the in-memory setting store.
/// </summary>
/// <param name="section">Section the setting is in. Cannot be null.</param>
/// <param name="key">Setting key (name). Cannot be null.</param>
/// <param name="value">Output value.</param>
/// <returns>True if the setting was found and successfully converted to an integer.</returns>
BRIDGE_IMPEXP bool BridgeSettingGetUint(const char* section, const char* key, duint* value);
/// <summary>
/// Set a string setting in the in-memory setting store.
/// </summary>
/// <param name="section">Section the setting is in. Cannot be null.</param>
/// <param name="key">Setting key (name). Set to null to clear the whole section.</param>
/// <param name="value">New setting value. Set to null to remove the key from the section.</param>
/// <returns>True if the operation was successful.</returns>
BRIDGE_IMPEXP bool BridgeSettingSet(const char* section, const char* key, const char* value);
/// <summary>
/// Set an integer setting in the in-memory setting store.
/// </summary>
/// <param name="section">Section the setting is in. Cannot be null.</param>
/// <param name="key">Setting key (name). Set to null to clear the whole section.</param>
/// <param name="value">New setting value.</param>
/// <returns>True if the operation was successful.</returns>
BRIDGE_IMPEXP bool BridgeSettingSetUint(const char* section, const char* key, duint value);
/// <summary>
/// Flush the in-memory setting store to disk.
/// </summary>
/// <returns></returns>
BRIDGE_IMPEXP bool BridgeSettingFlush();
/// <summary>
/// Read the in-memory setting store from disk.
/// </summary>
/// <param name="errorLine">Line where the error occurred. Set to null to ignore this.</param>
/// <returns>True if the setting were read and parsed correctly.</returns>
BRIDGE_IMPEXP bool BridgeSettingRead(int* errorLine);
/// <summary>
/// Get the debugger version.
/// </summary>
/// <returns>25</returns>
BRIDGE_IMPEXP int BridgeGetDbgVersion();
/// <summary>
/// Checks if the current process is elevated.
/// </summary>
/// <returns>true if the process is elevated, false otherwise.</returns>
BRIDGE_IMPEXP bool BridgeIsProcessElevated();
/// <summary>
/// Gets the NT build number from the operating system.
/// </summary>
/// <returns>NtBuildNumber</returns>
BRIDGE_IMPEXP unsigned int BridgeGetNtBuildNumber();
/// <summary>
/// Returns the user directory (without trailing backslash).
/// </summary>
BRIDGE_IMPEXP const wchar_t* BridgeUserDirectory();
#ifdef __cplusplus
}
#endif
//list structure (and C++ wrapper)
#include "bridgelist.h"
#include "bridgegraph.h"
#ifdef __cplusplus
extern "C"
{
#endif
//Debugger defines
#define MAX_LABEL_SIZE 256
#define MAX_COMMENT_SIZE 512
#define MAX_MODULE_SIZE 256
#define MAX_IMPORT_SIZE 65536
#define MAX_BREAKPOINT_SIZE 256
#define MAX_CONDITIONAL_EXPR_SIZE 256
#define MAX_CONDITIONAL_TEXT_SIZE 256
#define MAX_SCRIPT_LINE_SIZE 2048
#define MAX_THREAD_NAME_SIZE 256
#define MAX_WATCH_NAME_SIZE 256
#define MAX_STRING_SIZE 512
#define MAX_ERROR_SIZE 512
#define RIGHTS_STRING_SIZE (sizeof("ERWCG"))
#define MAX_SECTION_SIZE 10
#define MAX_COMMAND_LINE_SIZE 256
#define MAX_MNEMONIC_SIZE 64
#define PAGE_SIZE 0x1000
//Debugger enums
typedef enum
{
initialized,
paused,
running,
stopped
} DBGSTATE;
typedef enum
{
SEG_DEFAULT,
SEG_ES,
SEG_DS,
SEG_FS,
SEG_GS,
SEG_CS,
SEG_SS
} SEGMENTREG;
typedef enum
{
flagmodule = 0x1,
flaglabel = 0x2,
flagcomment = 0x4,
flagbookmark = 0x8,
flagfunction = 0x10,
flagloop = 0x20,
flagargs = 0x40,
flagNoFuncOffset = 0x80
} ADDRINFOFLAGS;
typedef enum
{
bp_none = 0,
bp_normal = 1,
bp_hardware = 2,
bp_memory = 4,
bp_dll = 8,
bp_exception = 16
} BPXTYPE;
typedef enum
{
FUNC_NONE,
FUNC_BEGIN,
FUNC_MIDDLE,
FUNC_END,
FUNC_SINGLE
} FUNCTYPE;
typedef enum
{
LOOP_NONE,
LOOP_BEGIN,
LOOP_MIDDLE,
LOOP_ENTRY,
LOOP_END,
LOOP_SINGLE
} LOOPTYPE;
//order by most important type last
typedef enum
{
XREF_NONE,
XREF_DATA,
XREF_JMP,
XREF_CALL
} XREFTYPE;
typedef enum
{
ARG_NONE,
ARG_BEGIN,
ARG_MIDDLE,
ARG_END,
ARG_SINGLE
} ARGTYPE;
typedef enum
{
DBG_SCRIPT_LOAD, // param1=const char* filename, param2=unused
DBG_SCRIPT_UNLOAD, // param1=unused, param2=unused
DBG_SCRIPT_RUN, // param1=int destline, param2=unused
DBG_SCRIPT_STEP, // param1=unused, param2=unused
DBG_SCRIPT_BPTOGGLE, // param1=int line, param2=unused
DBG_SCRIPT_BPGET, // param1=int line, param2=unused
DBG_SCRIPT_CMDEXEC, // param1=const char* command, param2=unused
DBG_SCRIPT_ABORT, // param1=unused, param2=unused
DBG_SCRIPT_GETLINETYPE, // param1=int line, param2=unused
DBG_SCRIPT_SETIP, // param1=int line, param2=unused
DBG_SCRIPT_GETBRANCHINFO, // param1=int line, param2=SCRIPTBRANCH* info
DBG_SYMBOL_ENUM, // param1=SYMBOLCBINFO* cbInfo, param2=unused
DBG_ASSEMBLE_AT, // param1=duint addr, param2=const char* instruction
DBG_MODBASE_FROM_NAME, // param1=const char* modname, param2=unused
DBG_DISASM_AT, // param1=duint addr, param2=DISASM_INSTR* instr
DBG_STACK_COMMENT_GET, // param1=duint addr, param2=STACK_COMMENT* comment
DBG_GET_THREAD_LIST, // param1=THREADALLINFO* list, param2=unused
DBG_SETTINGS_UPDATED, // param1=unused, param2=unused
DBG_DISASM_FAST_AT, // param1=duint addr, param2=BASIC_INSTRUCTION_INFO* basicinfo
DBG_MENU_ENTRY_CLICKED, // param1=int hEntry, param2=unused
DBG_FUNCTION_GET, // param1=FUNCTION_LOOP_INFO* info, param2=unused
DBG_FUNCTION_OVERLAPS, // param1=FUNCTION_LOOP_INFO* info, param2=unused
DBG_FUNCTION_ADD, // param1=FUNCTION_LOOP_INFO* info, param2=unused
DBG_FUNCTION_DEL, // param1=FUNCTION_LOOP_INFO* info, param2=unused
DBG_LOOP_GET, // param1=FUNCTION_LOOP_INFO* info, param2=unused
DBG_LOOP_OVERLAPS, // param1=FUNCTION_LOOP_INFO* info, param2=unused
DBG_LOOP_ADD, // param1=FUNCTION_LOOP_INFO* info, param2=unused
DBG_LOOP_DEL, // param1=FUNCTION_LOOP_INFO* info, param2=unused
DBG_IS_RUN_LOCKED, // param1=unused, param2=unused
DBG_IS_BP_DISABLED, // param1=duint addr, param2=unused
DBG_SET_AUTO_COMMENT_AT, // param1=duint addr, param2=const char* text
DBG_DELETE_AUTO_COMMENT_RANGE, // param1=duint start, param2=duint end
DBG_SET_AUTO_LABEL_AT, // param1=duint addr, param2=const char* text
DBG_DELETE_AUTO_LABEL_RANGE, // param1=duint start, param2=duint end
DBG_SET_AUTO_BOOKMARK_AT, // param1=duint addr, param2=const char* text
DBG_DELETE_AUTO_BOOKMARK_RANGE, // param1=duint start, param2=duint end
DBG_SET_AUTO_FUNCTION_AT, // param1=duint addr, param2=const char* text
DBG_DELETE_AUTO_FUNCTION_RANGE, // param1=duint start, param2=duint end
DBG_GET_STRING_AT, // param1=duint addr, param2=unused
DBG_GET_FUNCTIONS, // param1=unused, param2=unused
DBG_WIN_EVENT, // param1=MSG* message, param2=long* result
DBG_WIN_EVENT_GLOBAL, // param1=MSG* message, param2=unused
DBG_INITIALIZE_LOCKS, // param1=unused, param2=unused
DBG_DEINITIALIZE_LOCKS, // param1=unused, param2=unused
DBG_GET_TIME_WASTED_COUNTER, // param1=unused, param2=unused
DBG_SYMBOL_ENUM_FROMCACHE, // param1=SYMBOLCBINFO* cbInfo, param2=unused
DBG_DELETE_COMMENT_RANGE, // param1=duint start, param2=duint end
DBG_DELETE_LABEL_RANGE, // param1=duint start, param2=duint end
DBG_DELETE_BOOKMARK_RANGE, // param1=duint start, param2=duint end
DBG_GET_XREF_COUNT_AT, // param1=duint addr, param2=unused
DBG_GET_XREF_TYPE_AT, // param1=duint addr, param2=unused
DBG_XREF_ADD, // param1=duint addr, param2=duint from
DBG_XREF_DEL_ALL, // param1=duint addr, param2=unused
DBG_XREF_GET, // param1=duint addr, param2=XREF_INFO* info
DBG_GET_ENCODE_TYPE_BUFFER, // param1=duint addr, param2=unused
DBG_ENCODE_TYPE_GET, // param1=duint addr, param2=duint size
DBG_DELETE_ENCODE_TYPE_RANGE, // param1=duint start, param2=duint end
DBG_ENCODE_SIZE_GET, // param1=duint addr, param2=duint codesize
DBG_DELETE_ENCODE_TYPE_SEG, // param1=duint addr, param2=unused
DBG_RELEASE_ENCODE_TYPE_BUFFER, // param1=void* buffer, param2=unused
DBG_ARGUMENT_GET, // param1=FUNCTION* info, param2=unused
DBG_ARGUMENT_OVERLAPS, // param1=FUNCTION* info, param2=unused
DBG_ARGUMENT_ADD, // param1=FUNCTION* info, param2=unused
DBG_ARGUMENT_DEL, // param1=FUNCTION* info, param2=unused
DBG_GET_WATCH_LIST, // param1=ListOf(WATCHINFO), param2=unused
DBG_SELCHANGED, // param1=hWindow, param2=VA
DBG_GET_PROCESS_HANDLE, // param1=unused, param2=unused
DBG_GET_THREAD_HANDLE, // param1=unused, param2=unused
DBG_GET_PROCESS_ID, // param1=unused, param2=unused
DBG_GET_THREAD_ID, // param1=unused, param2=unused
DBG_GET_PEB_ADDRESS, // param1=DWORD ProcessId, param2=unused
DBG_GET_TEB_ADDRESS, // param1=DWORD ThreadId, param2=unused
DBG_ANALYZE_FUNCTION, // param1=BridgeCFGraphList* graph, param2=duint entry
DBG_MENU_PREPARE, // param1=int hMenu, param2=unused
DBG_GET_SYMBOL_INFO, // param1=void* symbol, param2=SYMBOLINFO* info
DBG_GET_DEBUG_ENGINE, // param1=unused, param2-unused
DBG_GET_SYMBOL_INFO_AT, // param1=duint addr, param2=SYMBOLINFO* info
DBG_XREF_ADD_MULTI, // param1=const XREF_EDGE* edges, param2=duint count
} DBGMSG;
typedef enum
{
linecommand,
linebranch,
linelabel,
linecomment,
lineempty,
} SCRIPTLINETYPE;
typedef enum
{
scriptnobranch,
scriptjmp,
scriptjnejnz,
scriptjejz,
scriptjbjl,
scriptjajg,
scriptjbejle,
scriptjaejge,
scriptcall
} SCRIPTBRANCHTYPE;
typedef enum
{
instr_normal,
instr_branch,
instr_stack
} DISASM_INSTRTYPE;
typedef enum
{
arg_normal,
arg_memory
} DISASM_ARGTYPE;
typedef enum
{
str_none,
str_ascii,
str_unicode
} STRING_TYPE;
typedef enum
{
_PriorityIdle = -15,
_PriorityAboveNormal = 1,
_PriorityBelowNormal = -1,
_PriorityHighest = 2,
_PriorityLowest = -2,
_PriorityNormal = 0,
_PriorityTimeCritical = 15,
_PriorityUnknown = 0x7FFFFFFF
} THREADPRIORITY;
typedef enum
{
_Executive = 0,
_FreePage = 1,
_PageIn = 2,
_PoolAllocation = 3,
_DelayExecution = 4,
_Suspended = 5,
_UserRequest = 6,
_WrExecutive = 7,
_WrFreePage = 8,
_WrPageIn = 9,
_WrPoolAllocation = 10,
_WrDelayExecution = 11,
_WrSuspended = 12,
_WrUserRequest = 13,
_WrEventPair = 14,
_WrQueue = 15,
_WrLpcReceive = 16,
_WrLpcReply = 17,
_WrVirtualMemory = 18,
_WrPageOut = 19,
_WrRendezvous = 20,
_Spare2 = 21,
_Spare3 = 22,
_Spare4 = 23,
_Spare5 = 24,
_WrCalloutStack = 25,
_WrKernel = 26,
_WrResource = 27,
_WrPushLock = 28,
_WrMutex = 29,
_WrQuantumEnd = 30,
_WrDispatchInt = 31,
_WrPreempted = 32,
_WrYieldExecution = 33,
_WrFastMutex = 34,
_WrGuardedMutex = 35,
_WrRundown = 36,
} THREADWAITREASON;
typedef enum
{
size_byte = 1,
size_word = 2,
size_dword = 4,
size_qword = 8,
size_xmmword = 16,
size_ymmword = 32
} MEMORY_SIZE;
typedef enum
{
enc_unknown, //must be 0
enc_byte, //1 byte
enc_word, //2 bytes
enc_dword, //4 bytes
enc_fword, //6 bytes
enc_qword, //8 bytes
enc_tbyte, //10 bytes
enc_oword, //16 bytes
enc_mmword, //8 bytes
enc_xmmword, //16 bytes
enc_ymmword, //32 bytes
enc_zmmword, //64 bytes avx512 not supported
enc_real4, //4 byte float
enc_real8, //8 byte double
enc_real10, //10 byte decimal
enc_ascii, //ascii sequence
enc_unicode, //unicode sequence
enc_code, //start of code
enc_junk, //junk code
enc_middle //middle of data
} ENCODETYPE;
typedef enum
{
TYPE_UINT, // unsigned integer
TYPE_INT, // signed integer
TYPE_FLOAT,// single precision floating point value
TYPE_ASCII, // ascii string
TYPE_UNICODE, // unicode string
TYPE_INVALID // invalid watch expression or data type
} WATCHVARTYPE;
typedef enum
{
MODE_DISABLED, // watchdog is disabled
MODE_ISTRUE, // alert if expression is not 0
MODE_ISFALSE, // alert if expression is 0
MODE_CHANGED, // alert if expression is changed
MODE_UNCHANGED // alert if expression is not changed
} WATCHDOGMODE;
typedef enum
{
hw_access,
hw_write,
hw_execute
} BPHWTYPE;
typedef enum
{
mem_access,
mem_read,
mem_write,
mem_execute
} BPMEMTYPE;
typedef enum
{
dll_load = 1,
dll_unload,
dll_all
} BPDLLTYPE;
typedef enum
{
ex_firstchance = 1,
ex_secondchance,
ex_all
} BPEXTYPE;
typedef enum
{
hw_byte,
hw_word,
hw_dword,
hw_qword
} BPHWSIZE;
typedef enum
{
sym_import,
sym_export,
sym_symbol
} SYMBOLTYPE;
#define SYMBOL_MASK_IMPORT (1u << sym_import)
#define SYMBOL_MASK_EXPORT (1u << sym_export)
#define SYMBOL_MASK_SYMBOL (1u << sym_symbol)
#define SYMBOL_MASK_ALL (SYMBOL_MASK_IMPORT | SYMBOL_MASK_EXPORT | SYMBOL_MASK_SYMBOL)
typedef enum
{
mod_user,
mod_system
} MODULEPARTY;
typedef enum
{
DebugEngineTitanEngine,
DebugEngineGleeBug,
DebugEngineStaticEngine,
} DEBUG_ENGINE;
//Debugger typedefs
typedef MEMORY_SIZE VALUE_SIZE;
typedef struct DBGFUNCTIONS_ DBGFUNCTIONS;
// Callback declaration:
// bool cbSymbolEnum(const SYMBOLPTR* symbol, void* user);
// To get the data from the opaque pointer:
// SYMBOLINFO info;
// DbgGetSymbolInfo(symbol, &info);
// The SYMBOLPTR* becomes invalid when the module is unloaded
// DO NOT STORE unless you are absolutely certain you handle it correctly
typedef bool (*CBSYMBOLENUM)(const struct SYMBOLPTR_* symbol, void* user);
//Debugger structs
typedef struct
{
MEMORY_BASIC_INFORMATION mbi;
char info[MAX_MODULE_SIZE];
} MEMPAGE;
typedef struct
{
int count;
MEMPAGE* page;
} MEMMAP;
typedef struct
{
BPXTYPE type;
duint addr;
bool enabled;
bool singleshoot;
bool active;
char name[MAX_BREAKPOINT_SIZE];
char mod[MAX_MODULE_SIZE];
unsigned short slot;
// extended part
unsigned char typeEx; //BPHWTYPE/BPMEMTYPE/BPDLLTYPE/BPEXTYPE
unsigned char hwSize; //BPHWSIZE
unsigned int hitCount;
bool fastResume;
bool silent;
char breakCondition[MAX_CONDITIONAL_EXPR_SIZE];
char logText[MAX_CONDITIONAL_TEXT_SIZE];
char logCondition[MAX_CONDITIONAL_EXPR_SIZE];
char commandText[MAX_CONDITIONAL_TEXT_SIZE];
char commandCondition[MAX_CONDITIONAL_EXPR_SIZE];
} BRIDGEBP;
typedef struct
{
int count;
BRIDGEBP* bp;
} BPMAP;
typedef struct
{
char WatchName[MAX_WATCH_NAME_SIZE];
char Expression[MAX_CONDITIONAL_EXPR_SIZE];
unsigned int window;
unsigned int id;
WATCHVARTYPE varType;
WATCHDOGMODE watchdogMode;
duint value;
bool watchdogTriggered;
} WATCHINFO;
typedef struct
{
duint start; //OUT
duint end; //OUT
duint instrcount; //OUT
} FUNCTION;
typedef struct
{
int depth; //IN
duint start; //OUT
duint end; //OUT
duint instrcount; //OUT
} LOOP;
typedef struct
{
int flags; //ADDRINFOFLAGS (IN)
char module[MAX_MODULE_SIZE]; //module the address is in
char label[MAX_LABEL_SIZE];
char comment[MAX_COMMENT_SIZE];
bool isbookmark;
FUNCTION function;
LOOP loop;
FUNCTION args;
} BRIDGE_ADDRINFO;
typedef struct SYMBOLINFO_
{
duint addr;
char* decoratedSymbol;
char* undecoratedSymbol;
SYMBOLTYPE type;
// If true: Use BridgeFree(decoratedSymbol) to deallocate
// Else: The decoratedSymbol pointer is valid until the module unloads
bool freeDecorated;
// If true: Use BridgeFree(undecoratedSymbol) to deallcoate
// Else: The undecoratedSymbol pointer is valid until the module unloads
bool freeUndecorated;
// The entry point pseudo-export has ordinal == 0 (invalid ordinal value)
DWORD ordinal;
} SYMBOLINFO;
#ifdef __cplusplus
struct SYMBOLINFOCPP : SYMBOLINFO
{
SYMBOLINFOCPP(const SYMBOLINFOCPP &) = delete;
SYMBOLINFOCPP(SYMBOLINFOCPP &&) = delete;
SYMBOLINFOCPP()
{
memset(this, 0, sizeof(SYMBOLINFO));
}
~SYMBOLINFOCPP()
{
if(freeDecorated)
BridgeFree(decoratedSymbol);
if(freeUndecorated)
BridgeFree(undecoratedSymbol);
}
};
static_assert(sizeof(SYMBOLINFOCPP) == sizeof(SYMBOLINFO), "");
#endif // __cplusplus
typedef struct
{
duint base;
char name[MAX_MODULE_SIZE];
} SYMBOLMODULEINFO;
typedef struct
{
duint base;
CBSYMBOLENUM cbSymbolEnum;
void* user;
duint start;
duint end;
unsigned int symbolMask;
} SYMBOLCBINFO;
typedef struct
{
bool c;
bool p;
bool a;
bool z;
bool s;
bool t;
bool i;
bool d;
bool o;
} FLAGS;
typedef struct
{
bool FZ;
bool PM;
bool UM;
bool OM;
bool ZM;
bool IM;
bool DM;
bool DAZ;
bool PE;
bool UE;
bool OE;
bool ZE;
bool DE;
bool IE;
unsigned short RC;
} MXCSRFIELDS;
typedef struct
{
bool B;
bool C3;
bool C2;
bool C1;
bool C0;
bool ES;
bool SF;
bool P;
bool U;
bool O;
bool Z;
bool D;
bool I;
unsigned short TOP;
} X87STATUSWORDFIELDS;
typedef struct
{
bool IC;
bool IEM;
bool PM;
bool UM;
bool OM;
bool ZM;
bool DM;
bool IM;
unsigned short RC;
unsigned short PC;
} X87CONTROLWORDFIELDS;
typedef struct DECLSPEC_ALIGN(16) _XMMREGISTER
{
ULONGLONG Low;
LONGLONG High;
} XMMREGISTER;
typedef struct
{
XMMREGISTER Low; //XMM/SSE part
XMMREGISTER High; //AVX part
} YMMREGISTER;
typedef struct
{
BYTE data[10];
int st_value;
int tag;
} X87FPUREGISTER;
typedef struct
{
WORD ControlWord;
WORD StatusWord;
WORD TagWord;
DWORD ErrorOffset;
DWORD ErrorSelector;
DWORD DataOffset;
DWORD DataSelector;
DWORD Cr0NpxState;
} X87FPU;
typedef struct
{
ULONG_PTR cax;
ULONG_PTR ccx;
ULONG_PTR cdx;
ULONG_PTR cbx;
ULONG_PTR csp;
ULONG_PTR cbp;
ULONG_PTR csi;
ULONG_PTR cdi;
#ifdef _WIN64
ULONG_PTR r8;
ULONG_PTR r9;
ULONG_PTR r10;
ULONG_PTR r11;
ULONG_PTR r12;
ULONG_PTR r13;
ULONG_PTR r14;
ULONG_PTR r15;
#endif //_WIN64
ULONG_PTR cip;
ULONG_PTR eflags;
unsigned short gs;
unsigned short fs;
unsigned short es;
unsigned short ds;
unsigned short cs;
unsigned short ss;
ULONG_PTR dr0;
ULONG_PTR dr1;
ULONG_PTR dr2;
ULONG_PTR dr3;
ULONG_PTR dr6;
ULONG_PTR dr7;
BYTE RegisterArea[80];
X87FPU x87fpu;
DWORD MxCsr;
#ifdef _WIN64
XMMREGISTER XmmRegisters[16];
YMMREGISTER YmmRegisters[16];
#else // x86
XMMREGISTER XmmRegisters[8];
YMMREGISTER YmmRegisters[8];
#endif
} REGISTERCONTEXT;
typedef struct
{
DWORD code;
char name[128];
} LASTERROR;
typedef struct
{
DWORD code;
char name[128];
} LASTSTATUS;
typedef struct
{
REGISTERCONTEXT regcontext;
FLAGS flags;
X87FPUREGISTER x87FPURegisters[8];
unsigned long long mmx[8];
MXCSRFIELDS MxCsrFields;
X87STATUSWORDFIELDS x87StatusWordFields;
X87CONTROLWORDFIELDS x87ControlWordFields;
LASTERROR lastError;
LASTSTATUS lastStatus;
} REGDUMP;
typedef struct
{
DISASM_ARGTYPE type; //normal/memory
SEGMENTREG segment;
char mnemonic[64];
duint constant; //constant in the instruction (imm/disp)
duint value; //equal to constant or equal to the register value
duint memvalue; //memsize:[value]
} DISASM_ARG;
typedef struct
{
char instruction[64];
DISASM_INSTRTYPE type;
int argcount;
int instr_size;
DISASM_ARG arg[3];
} DISASM_INSTR;
typedef struct
{
char color[8]; //hex color-code
char comment[MAX_COMMENT_SIZE];
} STACK_COMMENT;
typedef struct
{
int ThreadNumber;
HANDLE Handle;
DWORD ThreadId;
duint ThreadStartAddress;
duint ThreadLocalBase;
char threadName[MAX_THREAD_NAME_SIZE];
} THREADINFO;
typedef struct
{
THREADINFO BasicInfo;
duint ThreadCip;
DWORD SuspendCount;
THREADPRIORITY Priority;
THREADWAITREASON WaitReason;
DWORD LastError;
FILETIME UserTime;
FILETIME KernelTime;
FILETIME CreationTime;
ULONG64 Cycles; // Windows Vista or greater
} THREADALLINFO;
typedef struct
{
int count;
THREADALLINFO* list;
int CurrentThread;
} THREADLIST;
typedef struct
{
duint value; //displacement / addrvalue (rip-relative)
MEMORY_SIZE size; //byte/word/dword/qword
char mnemonic[MAX_MNEMONIC_SIZE];
} MEMORY_INFO;
typedef struct
{
duint value;
VALUE_SIZE size;
} VALUE_INFO;
//definitions for BASIC_INSTRUCTION_INFO.type
#define TYPE_VALUE 1
#define TYPE_MEMORY 2
#define TYPE_ADDR 4
typedef struct
{
DWORD type; //value|memory|addr
VALUE_INFO value; //immediat
MEMORY_INFO memory;
duint addr; //addrvalue (jumps + calls)
bool branch; //jumps/calls
bool call; //instruction is a call
int size;
char instruction[MAX_MNEMONIC_SIZE * 4];
} BASIC_INSTRUCTION_INFO;
typedef struct
{
SCRIPTBRANCHTYPE type;
int dest;
char branchlabel[256];
} SCRIPTBRANCH;
typedef struct
{
duint addr;
duint start;
duint end;
bool manual;
int depth;
} FUNCTION_LOOP_INFO;
typedef struct
{
duint addr;
XREFTYPE type;
} XREF_RECORD;
typedef struct
{
duint refcount;
XREF_RECORD* references;
} XREF_INFO;
typedef struct
{
duint address;
duint from;
} XREF_EDGE;
typedef struct SYMBOLPTR_
{
duint modbase;
const void* symbol;
} SYMBOLPTR;
//Debugger functions
BRIDGE_IMPEXP const char* DbgInit();
BRIDGE_IMPEXP void DbgExit();
BRIDGE_IMPEXP bool DbgMemRead(duint va, void* dest, duint size);
BRIDGE_IMPEXP bool DbgMemWrite(duint va, const void* src, duint size);
BRIDGE_IMPEXP duint DbgMemGetPageSize(duint base);
BRIDGE_IMPEXP duint DbgMemFindBaseAddr(duint addr, duint* size);
/// <summary>
/// Asynchronously execute a debugger command by adding it to the command queue.
/// Note: the command may not have completed before this call returns. Use this
/// function if you don't care when the command gets executed.
///
/// Example: DbgCmdExec("ClearLog")
/// </summary>
/// <param name="cmd">The command to execute.</param>
/// <returns>True if the command was successfully submitted to the command queue. False if the submission failed.</returns>
BRIDGE_IMPEXP bool DbgCmdExec(const char* cmd);
/// <summary>
/// Performs synchronous execution of a debugger command. This function call only
/// returns after the command has completed.
///
/// Example: DbgCmdExecDirect("loadlib advapi32.dll")
/// </summary>
/// <param name="cmd">The command to execute.</param>
/// <returns>True if the command executed successfully, False if there was a problem.</returns>
BRIDGE_IMPEXP bool DbgCmdExecDirect(const char* cmd);
BRIDGE_IMPEXP bool DbgMemMap(MEMMAP* memmap);
BRIDGE_IMPEXP bool DbgIsValidExpression(const char* expression);
BRIDGE_IMPEXP bool DbgIsDebugging();
BRIDGE_IMPEXP bool DbgIsJumpGoingToExecute(duint addr);
BRIDGE_IMPEXP bool DbgGetLabelAt(duint addr, SEGMENTREG segment, char* text);
BRIDGE_IMPEXP bool DbgSetLabelAt(duint addr, const char* text);
BRIDGE_IMPEXP void DbgClearLabelRange(duint start, duint end);
BRIDGE_IMPEXP bool DbgGetCommentAt(duint addr, char* text);
BRIDGE_IMPEXP bool DbgSetCommentAt(duint addr, const char* text);
BRIDGE_IMPEXP void DbgClearCommentRange(duint start, duint end);
BRIDGE_IMPEXP bool DbgGetBookmarkAt(duint addr);
BRIDGE_IMPEXP bool DbgSetBookmarkAt(duint addr, bool isbookmark);
BRIDGE_IMPEXP void DbgClearBookmarkRange(duint start, duint end);
BRIDGE_IMPEXP bool DbgGetModuleAt(duint addr, char* text);
BRIDGE_IMPEXP BPXTYPE DbgGetBpxTypeAt(duint addr);
BRIDGE_IMPEXP duint DbgValFromString(const char* string);
BRIDGE_IMPEXP bool DbgGetRegDumpEx(REGDUMP* regdump, size_t size);
BRIDGE_IMPEXP bool DbgValToString(const char* string, duint value);
BRIDGE_IMPEXP bool DbgMemIsValidReadPtr(duint addr);
BRIDGE_IMPEXP int DbgGetBpList(BPXTYPE type, BPMAP* list);
BRIDGE_IMPEXP FUNCTYPE DbgGetFunctionTypeAt(duint addr);
BRIDGE_IMPEXP LOOPTYPE DbgGetLoopTypeAt(duint addr, int depth);
BRIDGE_IMPEXP duint DbgGetBranchDestination(duint addr);
BRIDGE_IMPEXP void DbgScriptLoad(const char* filename);
BRIDGE_IMPEXP void DbgScriptUnload();
BRIDGE_IMPEXP void DbgScriptRun(int destline);
BRIDGE_IMPEXP void DbgScriptStep();
BRIDGE_IMPEXP bool DbgScriptBpToggle(int line);
BRIDGE_IMPEXP bool DbgScriptBpGet(int line);
BRIDGE_IMPEXP bool DbgScriptCmdExec(const char* command);
BRIDGE_IMPEXP void DbgScriptAbort();
BRIDGE_IMPEXP SCRIPTLINETYPE DbgScriptGetLineType(int line);
BRIDGE_IMPEXP void DbgScriptSetIp(int line);
BRIDGE_IMPEXP bool DbgScriptGetBranchInfo(int line, SCRIPTBRANCH* info);
BRIDGE_IMPEXP bool DbgSymbolEnum(duint base, CBSYMBOLENUM cbSymbolEnum, void* user);
BRIDGE_IMPEXP bool DbgSymbolEnumFromCache(duint base, CBSYMBOLENUM cbSymbolEnum, void* user);
BRIDGE_IMPEXP bool DbgSymbolEnumRange(duint start, duint end, unsigned int symbolMask, CBSYMBOLENUM cbSymbolEnum, void* user);
BRIDGE_IMPEXP bool DbgAssembleAt(duint addr, const char* instruction);
BRIDGE_IMPEXP duint DbgModBaseFromName(const char* name);
BRIDGE_IMPEXP void DbgDisasmAt(duint addr, DISASM_INSTR* instr);
BRIDGE_IMPEXP bool DbgStackCommentGet(duint addr, STACK_COMMENT* comment);
BRIDGE_IMPEXP void DbgGetThreadList(THREADLIST* list);
BRIDGE_IMPEXP void DbgSettingsUpdated();
BRIDGE_IMPEXP void DbgDisasmFastAt(duint addr, BASIC_INSTRUCTION_INFO* basicinfo);
BRIDGE_IMPEXP void DbgMenuEntryClicked(int hEntry);
BRIDGE_IMPEXP bool DbgFunctionGet(duint addr, duint* start, duint* end);
BRIDGE_IMPEXP bool DbgFunctionOverlaps(duint start, duint end);
BRIDGE_IMPEXP bool DbgFunctionAdd(duint start, duint end);
BRIDGE_IMPEXP bool DbgFunctionDel(duint addr);
BRIDGE_IMPEXP bool DbgArgumentGet(duint addr, duint* start, duint* end);
BRIDGE_IMPEXP bool DbgArgumentOverlaps(duint start, duint end);
BRIDGE_IMPEXP bool DbgArgumentAdd(duint start, duint end);
BRIDGE_IMPEXP bool DbgArgumentDel(duint addr);
BRIDGE_IMPEXP bool DbgLoopGet(int depth, duint addr, duint* start, duint* end);
BRIDGE_IMPEXP bool DbgLoopOverlaps(int depth, duint start, duint end);
BRIDGE_IMPEXP bool DbgLoopAdd(duint start, duint end);
BRIDGE_IMPEXP bool DbgLoopDel(int depth, duint addr);
BRIDGE_IMPEXP bool DbgXrefAdd(duint addr, duint from);
BRIDGE_IMPEXP bool DbgXrefDelAll(duint addr);
BRIDGE_IMPEXP bool DbgXrefGet(duint addr, XREF_INFO* info);
BRIDGE_IMPEXP size_t DbgGetXrefCountAt(duint addr);
BRIDGE_IMPEXP XREFTYPE DbgGetXrefTypeAt(duint addr);
BRIDGE_IMPEXP bool DbgIsRunLocked();
BRIDGE_IMPEXP bool DbgIsBpDisabled(duint addr);
BRIDGE_IMPEXP bool DbgSetAutoCommentAt(duint addr, const char* text);
BRIDGE_IMPEXP void DbgClearAutoCommentRange(duint start, duint end);
BRIDGE_IMPEXP bool DbgSetAutoLabelAt(duint addr, const char* text);
BRIDGE_IMPEXP void DbgClearAutoLabelRange(duint start, duint end);
BRIDGE_IMPEXP bool DbgSetAutoBookmarkAt(duint addr);
BRIDGE_IMPEXP void DbgClearAutoBookmarkRange(duint start, duint end);
BRIDGE_IMPEXP bool DbgSetAutoFunctionAt(duint start, duint end);
BRIDGE_IMPEXP void DbgClearAutoFunctionRange(duint start, duint end);
BRIDGE_IMPEXP bool DbgGetStringAt(duint addr, char* text);
BRIDGE_IMPEXP const DBGFUNCTIONS* DbgFunctions();
BRIDGE_IMPEXP bool DbgWinEvent(MSG* message, long* result);
BRIDGE_IMPEXP bool DbgWinEventGlobal(MSG* message);
BRIDGE_IMPEXP bool DbgIsRunning();
BRIDGE_IMPEXP duint DbgGetTimeWastedCounter();
BRIDGE_IMPEXP ARGTYPE DbgGetArgTypeAt(duint addr);
BRIDGE_IMPEXP void* DbgGetEncodeTypeBuffer(duint addr, duint* size);
BRIDGE_IMPEXP void DbgReleaseEncodeTypeBuffer(void* buffer);
BRIDGE_IMPEXP ENCODETYPE DbgGetEncodeTypeAt(duint addr, duint size);
BRIDGE_IMPEXP duint DbgGetEncodeSizeAt(duint addr, duint codesize);
BRIDGE_IMPEXP bool DbgSetEncodeType(duint addr, duint size, ENCODETYPE type);
BRIDGE_IMPEXP void DbgDelEncodeTypeRange(duint start, duint end);
BRIDGE_IMPEXP void DbgDelEncodeTypeSegment(duint start);
BRIDGE_IMPEXP bool DbgGetWatchList(ListOf(WATCHINFO) list);
BRIDGE_IMPEXP void DbgSelChanged(int hWindow, duint VA);
BRIDGE_IMPEXP HANDLE DbgGetProcessHandle();
BRIDGE_IMPEXP HANDLE DbgGetThreadHandle();
BRIDGE_IMPEXP DWORD DbgGetProcessId();
BRIDGE_IMPEXP DWORD DbgGetThreadId();
BRIDGE_IMPEXP duint DbgGetPebAddress(DWORD ProcessId);
BRIDGE_IMPEXP duint DbgGetTebAddress(DWORD ThreadId);
BRIDGE_IMPEXP bool DbgAnalyzeFunction(duint entry, BridgeCFGraphList* graph);
BRIDGE_IMPEXP duint DbgEval(const char* expression, bool* DEFAULT_PARAM(success, nullptr));
BRIDGE_IMPEXP void DbgGetSymbolInfo(const SYMBOLPTR* symbolptr, SYMBOLINFO* info);
BRIDGE_IMPEXP DEBUG_ENGINE DbgGetDebugEngine();
BRIDGE_IMPEXP bool DbgGetSymbolInfoAt(duint addr, SYMBOLINFO* info);
BRIDGE_IMPEXP duint DbgXrefAddMulti(const XREF_EDGE* edges, duint count);
//Gui defines
typedef enum
{
GUI_PLUGIN_MENU,
GUI_DISASM_MENU,
GUI_DUMP_MENU,
GUI_STACK_MENU,
GUI_GRAPH_MENU,
GUI_MEMMAP_MENU,
GUI_SYMMOD_MENU,
} GUIMENUTYPE;
BRIDGE_IMPEXP void DbgMenuPrepare(GUIMENUTYPE hMenu);
typedef enum
{
GUI_DISASSEMBLY,
GUI_DUMP,
GUI_STACK,
GUI_GRAPH,
GUI_MEMMAP,
GUI_SYMMOD,
} GUISELECTIONTYPE;
#define GUI_MAX_LINE_SIZE 65536
#define GUI_MAX_DISASSEMBLY_SIZE 2048
//Gui enums
typedef enum
{
GUI_DISASSEMBLE_AT, // param1=(duint)va, param2=(duint)cip
GUI_SET_DEBUG_STATE, // param1=(DBGSTATE)state, param2=unused
GUI_ADD_MSG_TO_LOG, // param1=(const char*)msg, param2=unused
GUI_CLEAR_LOG, // param1=unused, param2=unused
GUI_UPDATE_REGISTER_VIEW, // param1=unused, param2=unused
GUI_UPDATE_DISASSEMBLY_VIEW, // param1=unused, param2=unused
GUI_UPDATE_BREAKPOINTS_VIEW, // param1=unused, param2=unused
GUI_UPDATE_WINDOW_TITLE, // param1=(const char*)file, param2=unused
GUI_GET_WINDOW_HANDLE, // param1=unused, param2=unused
GUI_DUMP_AT, // param1=(duint)va param2=unused
GUI_SCRIPT_ADD, // param1=int count, param2=const char** lines
GUI_SCRIPT_CLEAR, // param1=unused, param2=unused
GUI_SCRIPT_SETIP, // param1=int line, param2=unused
GUI_SCRIPT_ERROR, // param1=int line, param2=const char* message
GUI_SCRIPT_SETTITLE, // param1=const char* title, param2=unused
GUI_SCRIPT_SETINFOLINE, // param1=int line, param2=const char* info
GUI_SCRIPT_MESSAGE, // param1=const char* message, param2=unused
GUI_SCRIPT_MSGYN, // param1=const char* message, param2=unused
GUI_SYMBOL_LOG_ADD, // param1(const char*)msg, param2=unused
GUI_SYMBOL_LOG_CLEAR, // param1=unused, param2=unused
GUI_SYMBOL_SET_PROGRESS, // param1=int percent param2=unused
GUI_SYMBOL_UPDATE_MODULE_LIST, // param1=int count, param2=SYMBOLMODULEINFO* modules
GUI_REF_ADDCOLUMN, // param1=int width, param2=(const char*)title
GUI_REF_SETROWCOUNT, // param1=int rows, param2=unused
GUI_REF_GETROWCOUNT, // param1=unused, param2=unused
GUI_REF_DELETEALLCOLUMNS, // param1=unused, param2=unused
GUI_REF_SETCELLCONTENT, // param1=(CELLINFO*)info, param2=unused
GUI_REF_GETCELLCONTENT, // param1=int row, param2=int col
GUI_REF_RELOADDATA, // param1=unused, param2=unused
GUI_REF_SETSINGLESELECTION, // param1=int index, param2=bool scroll
GUI_REF_SETPROGRESS, // param1=int progress, param2=unused
GUI_REF_SETCURRENTTASKPROGRESS, // param1=int progress, param2=const char* taskTitle
GUI_REF_SETSEARCHSTARTCOL, // param1=int col param2=unused
GUI_STACK_DUMP_AT, // param1=duint addr, param2=duint csp
GUI_UPDATE_DUMP_VIEW, // param1=unused, param2=unused
GUI_UPDATE_THREAD_VIEW, // param1=unused, param2=unused
GUI_ADD_RECENT_FILE, // param1=(const char*)file, param2=unused
GUI_SET_LAST_EXCEPTION, // param1=unsigned int code, param2=unused
GUI_GET_DISASSEMBLY, // param1=duint addr, param2=char* text
GUI_MENU_ADD, // param1=int hMenu, param2=const char* title
GUI_MENU_ADD_ENTRY, // param1=int hMenu, param2=const char* title
GUI_MENU_ADD_SEPARATOR, // param1=int hMenu, param2=unused
GUI_MENU_CLEAR, // param1=int hMenu, param2=unused
GUI_SELECTION_GET, // param1=GUISELECTIONTYPE, param2=SELECTIONDATA* selection
GUI_SELECTION_SET, // param1=GUISELECTIONTYPE, param2=const SELECTIONDATA* selection
GUI_GETLINE_WINDOW, // param1=const char* title, param2=char* text
GUI_AUTOCOMPLETE_ADDCMD, // param1=const char* cmd, param2=ununsed
GUI_AUTOCOMPLETE_DELCMD, // param1=const char* cmd, param2=ununsed
GUI_AUTOCOMPLETE_CLEARALL, // param1=unused, param2=unused
GUI_SCRIPT_ENABLEHIGHLIGHTING, // param1=bool enable, param2=unused
GUI_ADD_MSG_TO_STATUSBAR, // param1=const char* msg, param2=unused
GUI_UPDATE_SIDEBAR, // param1=unused, param2=unused
GUI_REPAINT_TABLE_VIEW, // param1=unused, param2=unused
GUI_UPDATE_PATCHES, // param1=unused, param2=unused
GUI_UPDATE_CALLSTACK, // param1=unused, param2=unused
GUI_UPDATE_SEHCHAIN, // param1=unused, param2=unused
GUI_SYMBOL_REFRESH_CURRENT, // param1=unused, param2=unused
GUI_UPDATE_MEMORY_VIEW, // param1=unused, param2=unused
GUI_REF_INITIALIZE, // param1=const char* name, param2=unused
GUI_LOAD_SOURCE_FILE, // param1=const char* path, param2=duint addr
GUI_MENU_SET_ICON, // param1=int hMenu, param2=ICONINFO*
GUI_MENU_SET_ENTRY_ICON, // param1=int hEntry, param2=ICONINFO*
GUI_SHOW_CPU, // param1=unused, param2=unused
GUI_ADD_QWIDGET_TAB, // param1=QWidget*, param2=unused
GUI_SHOW_QWIDGET_TAB, // param1=QWidget*, param2=unused
GUI_CLOSE_QWIDGET_TAB, // param1=QWidget*, param2=unused
GUI_EXECUTE_ON_GUI_THREAD, // param1=GUICALLBACKEX cb, param2=void* userdata
GUI_UPDATE_TIME_WASTED_COUNTER, // param1=unused, param2=unused
GUI_SET_GLOBAL_NOTES, // param1=const char* text, param2=unused
GUI_GET_GLOBAL_NOTES, // param1=char** text, param2=unused
GUI_SET_DEBUGGEE_NOTES, // param1=const char* text, param2=unused
GUI_GET_DEBUGGEE_NOTES, // param1=char** text, param2=unused
GUI_DUMP_AT_N, // param1=int index, param2=duint va
GUI_DISPLAY_WARNING, // param1=const char *text, param2=unused
GUI_REGISTER_SCRIPT_LANG, // param1=SCRIPTTYPEINFO* info, param2=unused
GUI_UNREGISTER_SCRIPT_LANG, // param1=int id, param2=unused
GUI_UPDATE_ARGUMENT_VIEW, // param1=unused, param2=unused
GUI_FOCUS_VIEW, // param1=int hWindow, param2=unused
GUI_UPDATE_WATCH_VIEW, // param1=unused, param2=unused
GUI_LOAD_GRAPH, // param1=BridgeCFGraphList* param2=unused
GUI_GRAPH_AT, // param1=duint addr param2=unused
GUI_UPDATE_GRAPH_VIEW, // param1=unused, param2=unused
GUI_SET_LOG_ENABLED, // param1=bool isEnabled param2=unused
GUI_ADD_FAVOURITE_TOOL, // param1=const char* name param2=const char* description
GUI_ADD_FAVOURITE_COMMAND, // param1=const char* command param2=const char* shortcut
GUI_SET_FAVOURITE_TOOL_SHORTCUT,// param1=const char* name param2=const char* shortcut
GUI_FOLD_DISASSEMBLY, // param1=duint startAddress param2=duint length
GUI_SELECT_IN_MEMORY_MAP, // param1=duint addr, param2=unused
GUI_GET_ACTIVE_VIEW, // param1=ACTIVEVIEW*, param2=unused
GUI_MENU_SET_ENTRY_CHECKED, // param1=int hEntry, param2=bool checked
GUI_ADD_INFO_LINE, // param1=const char* infoline, param2=unused
GUI_PROCESS_EVENTS, // param1=unused, param2=unused
GUI_TYPE_ADDNODE, // param1=void* parent, param2=TYPEDESCRIPTOR* type
GUI_TYPE_CLEAR, // param1=unused, param2=unused
GUI_UPDATE_TYPE_WIDGET, // param1=unused, param2=unused
GUI_CLOSE_APPLICATION, // param1=unused, param2=unused
GUI_MENU_SET_VISIBLE, // param1=int hMenu, param2=bool visible
GUI_MENU_SET_ENTRY_VISIBLE, // param1=int hEntry, param2=bool visible
GUI_MENU_SET_NAME, // param1=int hMenu, param2=const char* name
GUI_MENU_SET_ENTRY_NAME, // param1=int hEntry, param2=const char* name
GUI_FLUSH_LOG, // param1=unused, param2=unused
GUI_MENU_SET_ENTRY_HOTKEY, // param1=int hEntry, param2=const char* hack
GUI_REF_SEARCH_GETROWCOUNT, // param1=unused, param2=unused
GUI_REF_SEARCH_GETCELLCONTENT, // param1=int row, param2=int col
GUI_MENU_REMOVE, // param1=int hEntryMenu, param2=unused
GUI_REF_ADDCOMMAND, // param1=const char* title, param2=const char* command
GUI_OPEN_TRACE_FILE, // param1=const char* file name,param2=unused
GUI_UPDATE_TRACE_BROWSER, // param1=unused, param2=unused
GUI_INVALIDATE_SYMBOL_SOURCE, // param1=duint base, param2=unused
GUI_GET_CURRENT_GRAPH, // param1=BridgeCFGraphList*, param2=unused
GUI_SHOW_REF, // param1=unused, param2=unused
GUI_SELECT_IN_SYMBOLS_TAB, // param1=duint addr, param2=unused
GUI_GOTO_TRACE, // param1=duint index, param2=unused
GUI_SHOW_TRACE, // param1=unused, param2=unused
GUI_GET_MAIN_THREAD_ID, // param1=unused, param2=unused
GUI_ADD_MSG_TO_LOG_HTML, // param1=(const char*)msg, param2=unused
GUI_IS_LOG_ENABLED, // param1=unused, param2=unused
GUI_IS_DEBUGGER_FOCUSED_UNUSED, // This message is removed, could be used for future purposes
GUI_SAVE_LOG, // param1=const char* file name,param2=unused
GUI_REDIRECT_LOG, // param1=const char* file name,param2=unused
GUI_STOP_REDIRECT_LOG, // param1=unused, param2=unused
} GUIMSG;
//GUI Typedefs
struct _TYPEDESCRIPTOR;
typedef void (*GUICALLBACK)();
typedef void (*GUICALLBACKEX)(void*);
typedef bool (*GUISCRIPTEXECUTE)(const char* text);
typedef void (*GUISCRIPTCOMPLETER)(const char* text, char** entries, int* entryCount);
typedef bool (*TYPETOSTRING)(const struct _TYPEDESCRIPTOR* type, char* dest, size_t* destCount); //don't change destCount for final failure
//GUI structures
typedef struct
{
int row;
int col;
const char* str;
} CELLINFO;
typedef struct
{
duint start;
duint end;
} SELECTIONDATA;
typedef struct
{
const void* data;
duint size;
} ICONDATA;
typedef struct
{
char name[64];
int id;
GUISCRIPTEXECUTE execute;
GUISCRIPTCOMPLETER completeCommand;
} SCRIPTTYPEINFO;
typedef struct
{
void* titleHwnd;
void* classHwnd;
char title[MAX_STRING_SIZE];
char className[MAX_STRING_SIZE];
} ACTIVEVIEW;
typedef struct _TYPEDESCRIPTOR
{
bool expanded; //is the type node expanded?
bool reverse; //big endian?
const char* name; //type name (int b)
duint addr; //virtual address
duint offset; //offset to addr for the actual location
int id; //type id
int size; //sizeof(type)
TYPETOSTRING callback; //convert to string
void* userdata; //user data
} TYPEDESCRIPTOR;
//GUI functions
//code page is utf8
BRIDGE_IMPEXP const char* GuiTranslateText(const char* Source);
BRIDGE_IMPEXP void GuiDisasmAt(duint addr, duint cip);
BRIDGE_IMPEXP void GuiSetDebugState(DBGSTATE state);
BRIDGE_IMPEXP void GuiSetDebugStateFast(DBGSTATE state);
BRIDGE_IMPEXP void GuiAddLogMessage(const char* msg);
BRIDGE_IMPEXP void GuiAddLogMessageHtml(const char* msg);
BRIDGE_IMPEXP void GuiLogClear();
BRIDGE_IMPEXP void GuiLogSave(const char* filename);
BRIDGE_IMPEXP void GuiLogRedirect(const char* filename);
BRIDGE_IMPEXP void GuiLogRedirectStop();
BRIDGE_IMPEXP void GuiUpdateAllViews();
BRIDGE_IMPEXP void GuiUpdateRegisterView();
BRIDGE_IMPEXP void GuiUpdateDisassemblyView();
BRIDGE_IMPEXP void GuiUpdateBreakpointsView();
BRIDGE_IMPEXP void GuiUpdateWindowTitle(const char* filename);
BRIDGE_IMPEXP HWND GuiGetWindowHandle();
BRIDGE_IMPEXP void GuiDumpAt(duint va);
BRIDGE_IMPEXP void GuiScriptAdd(int count, const char** lines);
BRIDGE_IMPEXP void GuiScriptClear();
BRIDGE_IMPEXP void GuiScriptSetIp(int line);
BRIDGE_IMPEXP void GuiScriptError(int line, const char* message);
BRIDGE_IMPEXP void GuiScriptSetTitle(const char* title);
BRIDGE_IMPEXP void GuiScriptSetInfoLine(int line, const char* info);
BRIDGE_IMPEXP void GuiScriptMessage(const char* message);
BRIDGE_IMPEXP int GuiScriptMsgyn(const char* message);
BRIDGE_IMPEXP void GuiScriptEnableHighlighting(bool enable);
BRIDGE_IMPEXP void GuiSymbolLogAdd(const char* message);
BRIDGE_IMPEXP void GuiSymbolLogClear();
BRIDGE_IMPEXP void GuiSymbolSetProgress(int percent);
BRIDGE_IMPEXP void GuiSymbolUpdateModuleList(int count, SYMBOLMODULEINFO* modules);
BRIDGE_IMPEXP void GuiSymbolRefreshCurrent();
BRIDGE_IMPEXP void GuiReferenceAddColumn(int width, const char* title);
BRIDGE_IMPEXP void GuiReferenceSetRowCount(int count);
BRIDGE_IMPEXP int GuiReferenceGetRowCount();
BRIDGE_IMPEXP int GuiReferenceSearchGetRowCount();
BRIDGE_IMPEXP void GuiReferenceDeleteAllColumns();
BRIDGE_IMPEXP void GuiReferenceInitialize(const char* name);
BRIDGE_IMPEXP void GuiReferenceSetCellContent(int row, int col, const char* str);
BRIDGE_IMPEXP char* GuiReferenceGetCellContent(int row, int col);
BRIDGE_IMPEXP char* GuiReferenceSearchGetCellContent(int row, int col);
BRIDGE_IMPEXP void GuiReferenceReloadData();
BRIDGE_IMPEXP void GuiReferenceSetSingleSelection(int index, bool scroll);
BRIDGE_IMPEXP void GuiReferenceSetProgress(int progress);
BRIDGE_IMPEXP void GuiReferenceSetCurrentTaskProgress(int progress, const char* taskTitle);
BRIDGE_IMPEXP void GuiReferenceSetSearchStartCol(int col);
BRIDGE_IMPEXP void GuiStackDumpAt(duint addr, duint csp);
BRIDGE_IMPEXP void GuiUpdateDumpView();
BRIDGE_IMPEXP void GuiUpdateWatchView();
BRIDGE_IMPEXP void GuiUpdateThreadView();
BRIDGE_IMPEXP void GuiUpdateMemoryView();
BRIDGE_IMPEXP void GuiAddRecentFile(const char* file);
BRIDGE_IMPEXP void GuiSetLastException(unsigned int exception);
BRIDGE_IMPEXP bool GuiGetDisassembly(duint addr, char* text);
BRIDGE_IMPEXP int GuiMenuAdd(int hMenu, const char* title);
BRIDGE_IMPEXP int GuiMenuAddEntry(int hMenu, const char* title);
BRIDGE_IMPEXP void GuiMenuAddSeparator(int hMenu);
BRIDGE_IMPEXP void GuiMenuClear(int hMenu);
BRIDGE_IMPEXP void GuiMenuRemove(int hEntryMenu);
BRIDGE_IMPEXP bool GuiSelectionGet(GUISELECTIONTYPE hWindow, SELECTIONDATA* selection);
BRIDGE_IMPEXP bool GuiSelectionSet(GUISELECTIONTYPE hWindow, const SELECTIONDATA* selection);
BRIDGE_IMPEXP bool GuiGetLineWindow(const char* title, char* text);
BRIDGE_IMPEXP void GuiAutoCompleteAddCmd(const char* cmd);
BRIDGE_IMPEXP void GuiAutoCompleteDelCmd(const char* cmd);
BRIDGE_IMPEXP void GuiAutoCompleteClearAll();
BRIDGE_IMPEXP void GuiAddStatusBarMessage(const char* msg);
BRIDGE_IMPEXP void GuiUpdateSideBar();
BRIDGE_IMPEXP void GuiRepaintTableView();
BRIDGE_IMPEXP void GuiUpdatePatches();
BRIDGE_IMPEXP void GuiUpdateCallStack();
BRIDGE_IMPEXP void GuiUpdateSEHChain();
BRIDGE_IMPEXP void GuiLoadSourceFileEx(const char* path, duint addr);
BRIDGE_IMPEXP void GuiMenuSetIcon(int hMenu, const ICONDATA* icon);
BRIDGE_IMPEXP void GuiMenuSetEntryIcon(int hEntry, const ICONDATA* icon);
BRIDGE_IMPEXP void GuiMenuSetEntryChecked(int hEntry, bool checked);
BRIDGE_IMPEXP void GuiMenuSetVisible(int hMenu, bool visible);
BRIDGE_IMPEXP void GuiMenuSetEntryVisible(int hEntry, bool visible);
BRIDGE_IMPEXP void GuiMenuSetName(int hMenu, const char* name);
BRIDGE_IMPEXP void GuiMenuSetEntryName(int hEntry, const char* name);
BRIDGE_IMPEXP void GuiMenuSetEntryHotkey(int hEntry, const char* hack);
BRIDGE_IMPEXP void GuiShowCpu();
BRIDGE_IMPEXP void GuiAddQWidgetTab(void* qWidget);
BRIDGE_IMPEXP void GuiShowQWidgetTab(void* qWidget);
BRIDGE_IMPEXP void GuiCloseQWidgetTab(void* qWidget);
BRIDGE_IMPEXP void GuiExecuteOnGuiThread(GUICALLBACK cbGuiThread);
BRIDGE_IMPEXP void GuiUpdateTimeWastedCounter();
BRIDGE_IMPEXP void GuiSetGlobalNotes(const char* text);
BRIDGE_IMPEXP void GuiGetGlobalNotes(char** text);
BRIDGE_IMPEXP void GuiSetDebuggeeNotes(const char* text);
BRIDGE_IMPEXP void GuiGetDebuggeeNotes(char** text);
BRIDGE_IMPEXP void GuiDumpAtN(duint va, int index);
BRIDGE_IMPEXP void GuiDisplayWarning(const char* title, const char* text);
BRIDGE_IMPEXP void GuiRegisterScriptLanguage(SCRIPTTYPEINFO* info);
BRIDGE_IMPEXP void GuiUnregisterScriptLanguage(int id);
BRIDGE_IMPEXP void GuiUpdateArgumentWidget();
BRIDGE_IMPEXP void GuiFocusView(int hWindow);
BRIDGE_IMPEXP bool GuiIsUpdateDisabled();
BRIDGE_IMPEXP void GuiUpdateEnable(bool updateNow);
BRIDGE_IMPEXP void GuiUpdateDisable();
BRIDGE_IMPEXP bool GuiLoadGraph(BridgeCFGraphList* graph, duint addr);
BRIDGE_IMPEXP duint GuiGraphAt(duint addr);
BRIDGE_IMPEXP void GuiUpdateGraphView();
BRIDGE_IMPEXP void GuiDisableLog();
BRIDGE_IMPEXP void GuiEnableLog();
BRIDGE_IMPEXP bool GuiIsLogEnabled();
BRIDGE_IMPEXP void GuiAddFavouriteTool(const char* name, const char* description);
BRIDGE_IMPEXP void GuiAddFavouriteCommand(const char* name, const char* shortcut);
BRIDGE_IMPEXP void GuiSetFavouriteToolShortcut(const char* name, const char* shortcut);
BRIDGE_IMPEXP void GuiFoldDisassembly(duint startAddress, duint length);
BRIDGE_IMPEXP void GuiSelectInMemoryMap(duint addr);
BRIDGE_IMPEXP void GuiGetActiveView(ACTIVEVIEW* activeView);
BRIDGE_IMPEXP void GuiAddInfoLine(const char* infoLine);
BRIDGE_IMPEXP void GuiProcessEvents();
BRIDGE_IMPEXP void* GuiTypeAddNode(void* parent, const TYPEDESCRIPTOR* type);
BRIDGE_IMPEXP bool GuiTypeClear();
BRIDGE_IMPEXP void GuiUpdateTypeWidget();
BRIDGE_IMPEXP void GuiCloseApplication();
BRIDGE_IMPEXP void GuiFlushLog();
BRIDGE_IMPEXP void GuiReferenceAddCommand(const char* title, const char* command);
BRIDGE_IMPEXP void GuiUpdateTraceBrowser();
BRIDGE_IMPEXP void GuiOpenTraceFile(const char* fileName);
BRIDGE_IMPEXP void GuiInvalidateSymbolSource(duint base);
BRIDGE_IMPEXP void GuiExecuteOnGuiThreadEx(GUICALLBACKEX cbGuiThread, void* userdata);
BRIDGE_IMPEXP void GuiGetCurrentGraph(BridgeCFGraphList* graphList);
BRIDGE_IMPEXP void GuiShowReferences();
BRIDGE_IMPEXP void GuiSelectInSymbolsTab(duint addr);
BRIDGE_IMPEXP void GuiGotoTrace(duint index);
BRIDGE_IMPEXP void GuiShowTrace();
BRIDGE_IMPEXP DWORD GuiGetMainThreadId();
#ifdef __cplusplus
}
#endif
// Some useful C++ wrapper classes
#ifdef __cplusplus
class GuiDisableLogScope
{
bool wasEnabled;
public:
GuiDisableLogScope(const GuiDisableLogScope &) = delete;
GuiDisableLogScope()
{
wasEnabled = GuiIsLogEnabled();
if(wasEnabled)
GuiDisableLog();
}
~GuiDisableLogScope()
{
if(wasEnabled)
GuiEnableLog();
}
};
class GuiDisableUpdateScope
{
bool updateAfter;
bool wasEnabled;
public:
GuiDisableUpdateScope(const GuiDisableUpdateScope &) = delete;
explicit GuiDisableUpdateScope(bool updateAfter = true)
: updateAfter(updateAfter)
{
wasEnabled = !GuiIsUpdateDisabled();
if(wasEnabled)
GuiUpdateDisable();
}
~GuiDisableUpdateScope()
{
if(wasEnabled)
GuiUpdateEnable(updateAfter);
}
};
class GuiDisableScope : GuiDisableUpdateScope, GuiDisableLogScope { };
#endif // __cplusplus
#pragma pack(pop)
#endif // _BRIDGEMAIN_H_ |
C/C++ | x64dbg-development/src/bridge/Utf8Ini.h | #ifndef UTF8INI_H
#define UTF8INI_H
#include <string>
#include <map>
#include <vector>
class Utf8Ini
{
public:
/**
\brief Serialize to the INI file format.
*/
inline std::string Serialize() const
{
std::string output;
for(const auto & section : mSections)
{
if(output.length())
appendLine(output, "");
appendLine(output, makeSectionText(section.first));
for(const auto & keyvalue : section.second)
if(keyvalue.first.length())
appendLine(output, makeKeyValueText(keyvalue.first, keyvalue.second));
}
return output;
}
/**
\brief Deserialize from the INI file format.
\param data The INI data.
\param [out] errorLine The error line (only has a meaning when this function failed).
\return true if it succeeds, false if it fails.
*/
inline bool Deserialize(const std::string & data, int & errorLine)
{
//initialize
errorLine = 0;
Clear();
//read lines
std::vector<std::string> lines;
std::string curLine;
for(auto ch : data)
{
switch(ch)
{
case '\r':
break;
case '\n':
lines.push_back(trim(curLine));
curLine.clear();
break;
default:
curLine += ch;
}
}
if(curLine.length())
lines.push_back(trim(curLine));
//parse lines
std::string section = "";
for(const auto & line : lines)
{
errorLine++;
switch(getLineType(line))
{
case LineType::Invalid:
return false;
case LineType::Comment:
case LineType::Empty:
continue;
case LineType::KeyValue:
{
std::string key;
std::string value;
if(!section.length() ||
!parseKeyValueLine(line, key, value) ||
!SetValue(section, key, value))
return false;
}
break;
case LineType::Section:
{
if(!parseSectionLine(line, section))
return false;
}
break;
default:
return false;
}
}
return true;
}
/**
\brief Sets a value. This will overwrite older values.
\param section The section. Must have a length greater than one.
\param key The key. Must have a length greater than one.
\param value The value. Can be empty (effectively removing the value).
\return true if the value was set successfully, false otherwise.
*/
inline bool SetValue(const std::string & section, const std::string & key, const std::string & value)
{
auto trimmedSection = trim(section);
auto trimmedKey = trim(key);
if(!trimmedSection.length() || !trimmedKey.length())
return false;
auto found = mSections.find(trimmedSection);
if(found != mSections.end())
found->second[std::move(trimmedKey)] = value;
else
{
KeyValueMap keyValueMap;
keyValueMap.emplace(std::move(trimmedKey), value);
mSections.emplace(std::move(trimmedSection), std::move(keyValueMap));
}
return true;
}
/**
\brief Removes all key/value pairs from a section.
\param section The section to clear.
\return true if it succeeds, false otherwise.
*/
inline bool ClearSection(const std::string & section)
{
auto trimmedSection = trim(section);
if(!trimmedSection.length())
return false;
auto found = mSections.find(trimmedSection);
if(found == mSections.end())
return false;
mSections.erase(found);
return true;
}
/**
\brief Removes all sections.
*/
inline void Clear()
{
mSections.clear();
}
/**
\brief Gets a value.
\param section The section.
\param key The key.
\return The value. Empty string when the value was not found or empty.
*/
inline std::string GetValue(const std::string & section, const std::string & key) const
{
auto trimmedSection = trim(section);
auto trimmedKey = trim(key);
if(!trimmedSection.length() || !trimmedKey.length())
return "";
auto sectionFound = mSections.find(trimmedSection);
if(sectionFound == mSections.end())
return "";
const auto & keyValueMap = sectionFound->second;
auto keyFound = keyValueMap.find(trimmedKey);
if(keyFound == keyValueMap.end())
return "";
return keyFound->second;
}
/**
\brief Gets the section names.
\return List of section names.
*/
inline std::vector<std::string> Sections() const
{
std::vector<std::string> sections;
sections.reserve(mSections.size());
for(const auto & section : mSections)
sections.push_back(section.first);
return sections;
}
/**
\brief Gets keys in a given section.
\param section The section.
\return List of keys in the section. Empty if the section is not found or empty.
*/
inline std::vector<std::string> Keys(const std::string & section) const
{
std::vector<std::string> keys;
auto trimmedSection = trim(section);
if(trimmedSection.length())
{
auto found = mSections.find(trimmedSection);
if(found != mSections.end())
{
keys.reserve(found->second.size());
for(const auto & key : found->second)
keys.push_back(key.first);
}
}
return keys;
}
private:
typedef std::map<std::string, std::string> KeyValueMap;
std::map<std::string, KeyValueMap> mSections;
enum class LineType
{
Invalid,
Empty,
Section,
KeyValue,
Comment
};
static inline LineType getLineType(const std::string & line)
{
auto len = line.length();
if(!len)
return LineType::Empty;
if(line[0] == '[' && line[len - 1] == ']')
return LineType::Section;
if(line[0] == ';')
return LineType::Comment;
if(line.find('=') != std::string::npos)
return LineType::KeyValue;
return LineType::Invalid;
}
static inline std::string trim(const std::string & str)
{
auto len = str.length();
if(!len)
return "";
size_t pre = 0;
while(str[pre] == ' ')
pre++;
size_t post = 0;
while(str[len - post - 1] == ' ' && post < len)
post++;
auto sublen = len - post - pre;
return sublen > 0 ? str.substr(pre, len - post - pre) : "";
}
static inline bool parseKeyValueLine(const std::string & line, std::string & key, std::string & value)
{
auto pos = line.find('=');
key = trim(line.substr(0, pos));
value = trim(line.substr(pos + 1));
auto len = value.length();
if(len && value[0] == '\"' && value[len - 1] == '\"')
value = unescapeValue(value);
return true;
}
static inline bool parseSectionLine(const std::string & line, std::string & section)
{
section = trim(line.substr(1, line.length() - 2));
return section.length() > 0;
}
static inline void appendLine(std::string & output, const std::string & line)
{
if(output.length())
output += "\r\n";
output += line;
}
static inline std::string makeSectionText(const std::string & section)
{
return "[" + section + "]";
}
static inline std::string makeKeyValueText(const std::string & key, const std::string & value)
{
return key + "=" + escapeValue(value);
}
static inline bool needsEscaping(const std::string & value)
{
auto len = value.length();
return len && (value[0] == ' ' || value[len - 1] == ' ' ||
value.find('\n') != std::string::npos ||
value.find('\"') != std::string::npos);
}
static inline std::string escapeValue(const std::string & value)
{
if(!needsEscaping(value))
return value;
std::string escaped = "\"";
for(auto ch : value)
{
switch(ch)
{
case '\"':
escaped += "\\\"";
break;
case '\\':
escaped += "\\\\";
break;
case '\r':
escaped += "\\r";
break;
case '\n':
escaped += "\\n";
break;
case '\t':
escaped += "\\t";
break;
default:
escaped += ch;
}
}
escaped += "\"";
return escaped;
}
static inline std::string unescapeValue(const std::string & str)
{
std::string result;
auto bEscaped = false;
for(auto ch : str)
{
if(!bEscaped)
{
switch(ch)
{
case '\"':
break;
case '\\':
bEscaped = true;
break;
default:
result += ch;
}
}
else
{
switch(ch)
{
case 'r':
result += '\r';
break;
case 'n':
result += '\n';
break;
case 't':
result += '\t';
break;
default:
result += ch;
}
bEscaped = false;
}
}
if(bEscaped)
result += '\\';
return result;
}
};
#endif //UTF8INI_H |
Visual C++ Project | x64dbg-development/src/bridge/x64dbg_bridge.vcxproj | <?xml version="1.0" encoding="utf-8"?>
<Project DefaultTargets="Build" ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
<ItemGroup Label="ProjectConfigurations">
<ProjectConfiguration Include="Debug|Win32">
<Configuration>Debug</Configuration>
<Platform>Win32</Platform>
</ProjectConfiguration>
<ProjectConfiguration Include="Debug|x64">
<Configuration>Debug</Configuration>
<Platform>x64</Platform>
</ProjectConfiguration>
<ProjectConfiguration Include="Release|Win32">
<Configuration>Release</Configuration>
<Platform>Win32</Platform>
</ProjectConfiguration>
<ProjectConfiguration Include="Release|x64">
<Configuration>Release</Configuration>
<Platform>x64</Platform>
</ProjectConfiguration>
</ItemGroup>
<ItemGroup>
<ClCompile Include="bridgemain.cpp" />
<ClCompile Include="bridgemain_checker.c" />
<ClCompile Include="_global.cpp" />
</ItemGroup>
<ItemGroup>
<ClInclude Include="bridgegraph.h" />
<ClInclude Include="bridgemain.h" />
<ClInclude Include="bridgelist.h" />
<ClInclude Include="Utf8Ini.h" />
<ClInclude Include="_global.h" />
</ItemGroup>
<PropertyGroup Label="Globals">
<ProjectGuid>{944D9923-CB1A-6F6C-BCBC-9E00A71954C1}</ProjectGuid>
<Keyword>Win32Proj</Keyword>
</PropertyGroup>
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.Default.props" />
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'" Label="Configuration">
<ConfigurationType>DynamicLibrary</ConfigurationType>
<UseDebugLibraries>false</UseDebugLibraries>
<PlatformToolset>v120_xp</PlatformToolset>
</PropertyGroup>
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'" Label="Configuration">
<ConfigurationType>DynamicLibrary</ConfigurationType>
<UseDebugLibraries>false</UseDebugLibraries>
<PlatformToolset>v120_xp</PlatformToolset>
</PropertyGroup>
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<ConfigurationType>DynamicLibrary</ConfigurationType>
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<ImportGroup Label="ExtensionSettings">
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x64dbg-development/src/bridge/x64dbg_bridge.vcxproj.filters | <?xml version="1.0" encoding="utf-8"?>
<Project ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
<ItemGroup>
<Filter Include="Source Files">
<UniqueIdentifier>{4FC737F1-C7A5-4376-A066-2A32D752A2FF}</UniqueIdentifier>
<Extensions>cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx</Extensions>
</Filter>
<Filter Include="Header Files">
<UniqueIdentifier>{93995380-89BD-4b04-88EB-625FBE52EBFB}</UniqueIdentifier>
<Extensions>h;hpp;hxx;hm;inl;inc;xsd</Extensions>
</Filter>
</ItemGroup>
<ItemGroup>
<ClCompile Include="_global.cpp">
<Filter>Source Files</Filter>
</ClCompile>
<ClCompile Include="bridgemain.cpp">
<Filter>Source Files</Filter>
</ClCompile>
<ClCompile Include="bridgemain_checker.c">
<Filter>Source Files</Filter>
</ClCompile>
</ItemGroup>
<ItemGroup>
<ClInclude Include="_global.h">
<Filter>Header Files</Filter>
</ClInclude>
<ClInclude Include="bridgemain.h">
<Filter>Header Files</Filter>
</ClInclude>
<ClInclude Include="Utf8Ini.h">
<Filter>Header Files</Filter>
</ClInclude>
<ClInclude Include="bridgelist.h">
<Filter>Header Files</Filter>
</ClInclude>
<ClInclude Include="bridgegraph.h">
<Filter>Header Files</Filter>
</ClInclude>
</ItemGroup>
</Project> |
|
C++ | x64dbg-development/src/bridge/_global.cpp | #include "_global.h"
GUIGUIINIT _gui_guiinit;
GUISENDMESSAGE _gui_sendmessage;
GUITRANSLATETEXT _gui_translate_text;
DBGDBGINIT _dbg_dbginit;
DBGMEMFINDBASEADDR _dbg_memfindbaseaddr;
DBGMEMREAD _dbg_memread;
DBGMEMWRITE _dbg_memwrite;
DBGDBGCMDEXEC _dbg_dbgcmdexec;
DBGMEMMAP _dbg_memmap;
DBGDBGEXITSIGNAL _dbg_dbgexitsignal;
DBGVALFROMSTRING _dbg_valfromstring;
DBGISDEBUGGING _dbg_isdebugging;
DBGISJUMPGOINGTOEXECUTE _dbg_isjumpgoingtoexecute;
DBGADDRINFOGET _dbg_addrinfoget;
DBGADDRINFOSET _dbg_addrinfoset;
DBGENCODETYPESET _dbg_encodetypeset;
DBGBPGETTYPEAT _dbg_bpgettypeat;
DBGGETREGDUMP _dbg_getregdump;
DBGVALTOSTRING _dbg_valtostring;
DBGMEMISVALIDREADPTR _dbg_memisvalidreadptr;
DBGGETBPLIST _dbg_getbplist;
DBGDBGCMDEXECDIRECT _dbg_dbgcmddirectexec;
DBGGETBRANCHDESTINATION _dbg_getbranchdestination;
DBGSENDMESSAGE _dbg_sendmessage; |
C/C++ | x64dbg-development/src/bridge/_global.h | #ifndef _GLOBAL_H
#define _GLOBAL_H
#include <windows.h>
#include "bridgemain.h"
//GUI typedefs
typedef int (*GUIGUIINIT)(int, char**);
typedef void* (*GUISENDMESSAGE)(GUIMSG type, void* param1, void* param2);
typedef const char* (*GUITRANSLATETEXT)(const char* source);
//GUI functions
extern GUIGUIINIT _gui_guiinit;
extern GUISENDMESSAGE _gui_sendmessage;
extern GUITRANSLATETEXT _gui_translate_text;
//DBG typedefs
typedef const char* (*DBGDBGINIT)();
typedef duint(*DBGMEMFINDBASEADDR)(duint addr, duint* size);
typedef bool (*DBGMEMREAD)(duint addr, void* dest, duint size, duint* read);
typedef bool (*DBGMEMWRITE)(duint addr, const void* src, duint size, duint* written);
typedef bool (*DBGDBGCMDEXEC)(const char* cmd);
typedef bool (*DBGMEMMAP)(MEMMAP* memmap);
typedef void (*DBGDBGEXITSIGNAL)();
typedef bool (*DBGVALFROMSTRING)(const char* string, duint* value);
typedef bool (*DBGISDEBUGGING)();
typedef bool (*DBGISJUMPGOINGTOEXECUTE)(duint addr);
typedef bool (*DBGADDRINFOGET)(duint addr, SEGMENTREG segment, BRIDGE_ADDRINFO* addrinfo);
typedef bool (*DBGADDRINFOSET)(duint addr, BRIDGE_ADDRINFO* addrinfo);
typedef bool(*DBGENCODETYPESET)(duint addr, duint size, ENCODETYPE type);
typedef BPXTYPE(*DBGBPGETTYPEAT)(duint addr);
typedef bool (*DBGGETREGDUMP)(REGDUMP* regdump);
typedef bool (*DBGVALTOSTRING)(const char* string, duint value);
typedef bool (*DBGMEMISVALIDREADPTR)(duint addr);
typedef int (*DBGGETBPLIST)(BPXTYPE type, BPMAP* bplist);
typedef bool (*DBGDBGCMDEXECDIRECT)(const char* cmd);
typedef duint(*DBGGETBRANCHDESTINATION)(duint addr);
typedef duint(*DBGSENDMESSAGE)(DBGMSG type, void* param1, void* param2);
//DBG functions
extern DBGDBGINIT _dbg_dbginit;
extern DBGMEMFINDBASEADDR _dbg_memfindbaseaddr;
extern DBGMEMREAD _dbg_memread;
extern DBGMEMWRITE _dbg_memwrite;
extern DBGDBGCMDEXEC _dbg_dbgcmdexec;
extern DBGMEMMAP _dbg_memmap;
extern DBGDBGEXITSIGNAL _dbg_dbgexitsignal;
extern DBGVALFROMSTRING _dbg_valfromstring;
extern DBGISDEBUGGING _dbg_isdebugging;
extern DBGISJUMPGOINGTOEXECUTE _dbg_isjumpgoingtoexecute;
extern DBGADDRINFOGET _dbg_addrinfoget;
extern DBGADDRINFOSET _dbg_addrinfoset;
extern DBGENCODETYPESET _dbg_encodetypeset;
extern DBGBPGETTYPEAT _dbg_bpgettypeat;
extern DBGGETREGDUMP _dbg_getregdump;
extern DBGVALTOSTRING _dbg_valtostring;
extern DBGMEMISVALIDREADPTR _dbg_memisvalidreadptr;
extern DBGGETBPLIST _dbg_getbplist;
extern DBGDBGCMDEXECDIRECT _dbg_dbgcmddirectexec;
extern DBGGETBRANCHDESTINATION _dbg_getbranchdestination;
extern DBGSENDMESSAGE _dbg_sendmessage;
#endif // _GLOBAL_H |
C++ | x64dbg-development/src/dbg/addrinfo.cpp | /**
@file addrinfo.cpp
@brief Implements the addrinfo class.
*/
#include "addrinfo.h"
#include "debugger.h"
#include "memory.h"
#include "module.h"
#include "value.h"
///api functions
bool apienumexports(duint base, const EXPORTENUMCALLBACK & cbEnum)
{
SHARED_ACQUIRE(LockModules);
auto modinfo = ModInfoFromAddr(base);
if(!modinfo)
return false;
char modname[MAX_MODULE_SIZE] = "";
sprintf_s(modname, "%s%s", modinfo->name, modinfo->extension);
for(auto & modExport : modinfo->exports)
{
if(modExport.forwarded)
{
duint remote_addr;
if(valfromstring(modExport.forwardName.c_str(), &remote_addr))
cbEnum(base, modname, modExport.name.c_str(), remote_addr);
}
else
{
cbEnum(base, modname, modExport.name.c_str(), modExport.rva + base);
}
}
return true;
}
bool apienumimports(duint base, const IMPORTENUMCALLBACK & cbEnum)
{
SHARED_ACQUIRE(LockModules);
auto modinfo = ModInfoFromAddr(base);
if(!modinfo)
return false;
char modname[MAX_MODULE_SIZE] = "";
sprintf_s(modname, "%s%s", modinfo->name, modinfo->extension);
for(auto & modImport : modinfo->imports)
{
cbEnum(base, modImport.iatRva + base, modImport.name.c_str(), modinfo->importModules.at(modImport.moduleIndex).c_str());
}
return true;
} |
C/C++ | x64dbg-development/src/dbg/addrinfo.h | #ifndef _ADDRINFO_H
#define _ADDRINFO_H
#include "_global.h"
#include <functional>
#include <map>
#include <unordered_map>
//ranges
typedef std::pair<duint, duint> Range;
typedef std::pair<duint, Range> ModuleRange; //modhash + RVA range
typedef std::pair<int, ModuleRange> DepthModuleRange; //depth + modulerange
struct RangeCompare
{
bool operator()(const Range & a, const Range & b) const //a before b?
{
return a.second < b.first;
}
};
struct OverlappingRangeCompare
{
bool operator()(const Range & a, const Range & b) const //a before b?
{
return a.second < b.first || a.second < b.second;
}
};
struct ModuleRangeCompare
{
bool operator()(const ModuleRange & a, const ModuleRange & b) const
{
if(a.first != b.first)
return a.first < b.first; //module hash is smaller
return a.second.second < b.second.first; //a.second is before b.second
}
};
struct DepthModuleRangeCompare
{
bool operator()(const DepthModuleRange & a, const DepthModuleRange & b) const
{
if(a.first != b.first)
return a.first < b.first; //module depth is smaller
if(a.second.first != b.second.first)
return a.second.first < b.second.first; //module hash is smaller
return a.second.second.second < b.second.second.first; //range is smaller
}
};
#include "serializablemap.h"
//typedefs
typedef std::function<void (duint base, const char* mod, const char* name, duint addr)> EXPORTENUMCALLBACK;
typedef std::function<void (duint base, duint addr, const char* name, const char* moduleName)> IMPORTENUMCALLBACK;
bool apienumexports(duint base, const EXPORTENUMCALLBACK & cbEnum);
bool apienumimports(duint base, const IMPORTENUMCALLBACK & cbEnum);
#endif // _ADDRINFO_H |
C++ | x64dbg-development/src/dbg/animate.cpp | #include "animate.h"
#include "x64dbg.h"
#include "command.h"
char animate_command[deflen];
static unsigned int animate_interval = 50;
HANDLE hAnimateThread = nullptr;
static DWORD WINAPI animateThread(void* arg1)
{
auto ignoreError = settingboolget("Misc", "AnimateIgnoreError");
while(animate_command[0] != 0)
{
auto beforeTime = GetTickCount();
if(!cmddirectexec(animate_command) && !ignoreError)
break;
auto currentTime = GetTickCount();
if(currentTime < (beforeTime + animate_interval))
{
Sleep(beforeTime + animate_interval - currentTime);
}
}
// Close the handle itself
HANDLE hAnimateThread2 = hAnimateThread;
hAnimateThread = nullptr;
CloseHandle(hAnimateThread2);
return 0;
}
bool _dbg_animatecommand(const char* command)
{
if(command) // Animate command
{
GuiAddStatusBarMessage(GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Animation started. Use the \"pause\" command to stop animation.")));
strcpy_s(animate_command, command);
if(hAnimateThread == nullptr)
{
hAnimateThread = CreateThread(NULL, 0, animateThread, nullptr, 0, nullptr);
}
}
else // command = null : stop animating
{
animate_command[0] = 0;
}
return true;
}
void _dbg_setanimateinterval(unsigned int milliseconds)
{
animate_interval = milliseconds;
}
bool _dbg_isanimating()
{
return hAnimateThread != nullptr;
} |
C/C++ | x64dbg-development/src/dbg/animate.h | #ifndef ANIMATE_H
#define ANIMATE_H
bool _dbg_animatecommand(const char* command);
void _dbg_setanimateinterval(unsigned int milliseconds);
bool _dbg_isanimating();
inline void _dbg_animatestop()
{
_dbg_animatecommand(nullptr);
}
#endif //ANIMATE_H |
C++ | x64dbg-development/src/dbg/argument.cpp | #include "argument.h"
#include "module.h"
#include "memory.h"
#include "threading.h"
struct ArgumentSerializer : JSONWrapper<ARGUMENTSINFO>
{
bool Save(const ARGUMENTSINFO & value) override
{
setString("module", value.mod());
setHex("start", value.start);
setHex("end", value.end);
setHex("icount", value.instructioncount);
setBool("manual", value.manual);
return true;
}
bool Load(ARGUMENTSINFO & value) override
{
std::string mod;
if(!getString("module", mod))
return false;
value.modhash = ModHashFromName(mod.c_str());
return getHex("start", value.start) &&
getHex("end", value.end) &&
getBool("manual", value.manual) &&
getHex("icount", value.instructioncount) &&
value.end >= value.start;
}
};
struct Arguments : SerializableModuleRangeMap<LockArguments, ARGUMENTSINFO, ArgumentSerializer>
{
void AdjustValue(ARGUMENTSINFO & value) const override
{
auto base = ModBaseFromName(value.mod().c_str());
value.start += base;
value.end += base;
}
protected:
const char* jsonKey() const override
{
return "arguments";
}
ModuleRange makeKey(const ARGUMENTSINFO & value) const override
{
return ModuleRange(value.modhash, Range(value.start, value.end));
}
};
static Arguments arguments;
bool ArgumentAdd(duint Start, duint End, bool Manual, duint InstructionCount)
{
// Make sure memory is readable
if(!MemIsValidReadPtr(Start))
return false;
// Fail if boundary exceeds module size
auto moduleBase = ModBaseFromAddr(Start);
if(moduleBase != ModBaseFromAddr(End))
return false;
// Fail if 'Start' and 'End' are incompatible
if(Start > End || ArgumentOverlaps(Start, End))
return false;
ARGUMENTSINFO argument;
argument.modhash = ModHashFromAddr(moduleBase);
argument.start = Start - moduleBase;
argument.end = End - moduleBase;
argument.manual = Manual;
argument.instructioncount = InstructionCount;
return arguments.Add(argument);
}
bool ArgumentGet(duint Address, duint* Start, duint* End, duint* InstrCount)
{
ARGUMENTSINFO argument;
if(!arguments.Get(Arguments::VaKey(Address, Address), argument))
return false;
arguments.AdjustValue(argument);
if(Start)
*Start = argument.start;
if(End)
*End = argument.end;
if(InstrCount)
*InstrCount = argument.instructioncount;
return true;
}
bool ArgumentOverlaps(duint Start, duint End)
{
// A argument can't end before it begins
if(Start > End)
return false;
return arguments.Contains(Arguments::VaKey(Start, End));
}
bool ArgumentDelete(duint Address)
{
return arguments.Delete(Arguments::VaKey(Address, Address));
}
void ArgumentDelRange(duint Start, duint End, bool DeleteManual)
{
// Should all arguments be deleted?
// 0x00000000 - 0xFFFFFFFF
if(Start == 0 && End == ~0)
{
ArgumentClear();
}
else
{
// The start and end address must be in the same module
auto moduleBase = ModBaseFromAddr(Start);
if(moduleBase != ModBaseFromAddr(End))
return;
// Convert these to a relative offset
Start -= moduleBase;
End -= moduleBase;
arguments.DeleteWhere([ = ](const ARGUMENTSINFO & value)
{
if(!DeleteManual && value.manual)
return false;
return value.end >= Start && value.start <= End;
});
}
}
void ArgumentCacheSave(JSON Root)
{
arguments.CacheSave(Root);
}
void ArgumentCacheLoad(JSON Root)
{
arguments.CacheLoad(Root);
}
void ArgumentClear()
{
arguments.Clear();
}
void ArgumentGetList(std::vector<ARGUMENTSINFO> & list)
{
arguments.GetList(list);
}
bool ArgumentGetInfo(duint Address, ARGUMENTSINFO & info)
{
return arguments.Get(Arguments::VaKey(Address, Address), info);
}
bool ArgumentEnum(ARGUMENTSINFO* List, size_t* Size)
{
return arguments.Enum(List, Size);
} |
C/C++ | x64dbg-development/src/dbg/argument.h | #ifndef _ARGUMENT_H
#define _ARGUMENT_H
#include "addrinfo.h"
struct ARGUMENTSINFO
{
duint modhash;
duint start;
duint end;
bool manual;
duint instructioncount;
std::string mod() const
{
return ModNameFromHash(modhash);
}
};
bool ArgumentAdd(duint Start, duint End, bool Manual, duint InstructionCount = 0);
bool ArgumentGet(duint Address, duint* Start = nullptr, duint* End = nullptr, duint* InstrCount = nullptr);
bool ArgumentOverlaps(duint Start, duint End);
bool ArgumentDelete(duint Address);
void ArgumentDelRange(duint Start, duint End, bool DeleteManual = false);
void ArgumentCacheSave(JSON Root);
void ArgumentCacheLoad(JSON Root);
void ArgumentClear();
void ArgumentGetList(std::vector<ARGUMENTSINFO> & list);
bool ArgumentGetInfo(duint Address, ARGUMENTSINFO & info);
bool ArgumentEnum(ARGUMENTSINFO* List, size_t* Size);
#endif // _ARGUMENT_H |
C++ | x64dbg-development/src/dbg/assemble.cpp | /**
@file assemble.cpp
@brief Implements the assemble class.
*/
#include "assemble.h"
#include "memory.h"
#include "XEDParse/XEDParse.h"
#include "value.h"
#include "disasm_fast.h"
#include "disasm_helper.h"
#include "datainst_helper.h"
#include "debugger.h"
AssemblerEngine assemblerEngine = AssemblerEngine::XEDParse;
namespace asmjit
{
static XEDPARSE_STATUS XEDParseAssemble(XEDPARSE* XEDParse)
{
static auto asmjitAssemble = (XEDPARSE_STATUS(*)(XEDPARSE*))GetProcAddress(LoadLibraryW(L"asmjit.dll"), "XEDParseAssemble");
if(asmjitAssemble)
return asmjitAssemble(XEDParse);
strcpy_s(XEDParse->error, "asmjit not found!");
return XEDPARSE_ERROR;
}
}
static bool cbUnknown(const char* text, ULONGLONG* value)
{
if(!text || !value)
return false;
duint val;
if(!valfromstring(text, &val))
return false;
*value = val;
return true;
}
bool assemble(duint addr, unsigned char* dest, int destsize, int* size, const char* instruction, char* error)
{
if(isdatainstruction(instruction))
{
return tryassembledata(addr, dest, destsize, size, instruction, error);
}
if(strlen(instruction) >= XEDPARSE_MAXBUFSIZE)
return false;
XEDPARSE parse;
memset(&parse, 0, sizeof(parse));
#ifdef _WIN64
parse.x64 = true;
#else //x86
parse.x64 = false;
#endif
parse.cbUnknown = cbUnknown;
parse.cip = addr;
strcpy_s(parse.instr, instruction);
auto DoAssemble = XEDParseAssemble;
if(assemblerEngine == AssemblerEngine::asmjit || assemblerEngine == AssemblerEngine::Keystone)
DoAssemble = asmjit::XEDParseAssemble;
if(DoAssemble(&parse) == XEDPARSE_ERROR)
{
if(error)
strcpy_s(error, MAX_ERROR_SIZE, parse.error);
return false;
}
if(dest)
memcpy(dest, parse.dest, parse.dest_size);
if(size)
*size = parse.dest_size;
return true;
}
bool assemble(duint addr, unsigned char* dest, int* size, const char* instruction, char* error)
{
return assemble(addr, dest, 16, size, instruction, error);
}
static bool isInstructionPointingToExMemory(duint addr, const unsigned char* dest)
{
BASIC_INSTRUCTION_INFO basicinfo;
// Check if the instruction changes CIP and if it does not pretent it does point to valid executable memory.
if(!disasmfast(dest, addr, &basicinfo) || !basicinfo.branch || (basicinfo.type & TYPE_ADDR) == 0)
return true;
// An instruction pointing to invalid memory does not point to executable memory.
if(!MemIsValidReadPtr(basicinfo.addr))
return false;
// Check if memory region is marked as executable
if(MemIsCodePage(basicinfo.addr, false))
return true;
// Check if DEP is disabled
return !dbgisdepenabled();
}
bool assembleat(duint addr, const char* instruction, int* size, char* error, bool fillnop)
{
int destSize = 0;
Memory<unsigned char*> dest(16 * sizeof(unsigned char), "AssembleBuffer");
unsigned char* newbuffer = nullptr;
if(!assemble(addr, dest(), 16, &destSize, instruction, error))
{
if(destSize > 16)
{
dest.realloc(destSize);
if(!assemble(addr, dest(), destSize, &destSize, instruction, error))
return false;
}
else
return false;
}
//calculate the number of NOPs to insert
int origLen = disasmgetsize(addr);
while(origLen < destSize)
origLen += disasmgetsize(addr + origLen);
int nopsize = origLen - destSize;
unsigned char nops[16];
memset(nops, 0x90, sizeof(nops));
if(size)
*size = destSize;
// Check if the instruction doesn't set IP to non-executable memory
if(!isInstructionPointingToExMemory(addr, dest()))
{
String Title;
String Text;
Title = GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Non-executable memory region"));
Text = GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Assembled branch does not point to an executable memory region!"));
GuiDisplayWarning(Title.c_str(), Text.c_str());
}
bool ret = MemPatch(addr, dest(), destSize);
if(ret)
{
if(fillnop && nopsize)
{
if(size)
*size += nopsize;
// Ignored if the memory patch for NOPs fail (although it should not)
MemPatch(addr + destSize, nops, nopsize);
}
// Update GUI if any patching succeeded
GuiUpdatePatches();
}
else
{
// Tell the user writing is blocked
strcpy_s(error, MAX_ERROR_SIZE, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Error while writing process memory")));
}
return ret;
} |
C/C++ | x64dbg-development/src/dbg/assemble.h | #ifndef _ASSEMBLE_H
#define _ASSEMBLE_H
#include "_global.h"
enum class AssemblerEngine
{
XEDParse = 0,
Keystone = 1,
asmjit = 2
};
extern AssemblerEngine assemblerEngine;
bool assemble(duint addr, unsigned char* dest, int* size, const char* instruction, char* error);
bool assembleat(duint addr, const char* instruction, int* size, char* error, bool fillnop);
#endif // _ASSEMBLE_H |
C++ | x64dbg-development/src/dbg/bookmark.cpp | #include "bookmark.h"
struct BookmarkSerializer : AddrInfoSerializer<BOOKMARKSINFO>
{
};
struct Bookmarks : AddrInfoHashMap<LockBookmarks, BOOKMARKSINFO, BookmarkSerializer>
{
const char* jsonKey() const override
{
return "bookmarks";
}
};
static Bookmarks bookmarks;
bool BookmarkSet(duint Address, bool Manual)
{
BOOKMARKSINFO bookmark;
if(!bookmarks.PrepareValue(bookmark, Address, Manual))
return false;
auto key = Bookmarks::VaKey(Address);
if(bookmarks.Contains(key))
return bookmarks.Delete(key);
return bookmarks.Add(bookmark);
}
bool BookmarkGet(duint Address)
{
return bookmarks.Contains(Bookmarks::VaKey(Address));
}
bool BookmarkDelete(duint Address)
{
return bookmarks.Delete(Bookmarks::VaKey(Address));
}
void BookmarkDelRange(duint Start, duint End, bool Manual)
{
bookmarks.DeleteRange(Start, End, Manual);
}
void BookmarkCacheSave(JSON Root)
{
bookmarks.CacheSave(Root);
}
void BookmarkCacheLoad(JSON Root)
{
bookmarks.CacheLoad(Root);
bookmarks.CacheLoad(Root, "auto"); //legacy support
}
bool BookmarkEnum(BOOKMARKSINFO* List, size_t* Size)
{
return bookmarks.Enum(List, Size);
}
void BookmarkClear()
{
bookmarks.Clear();
}
void BookmarkGetList(std::vector<BOOKMARKSINFO> & list)
{
bookmarks.GetList(list);
}
bool BookmarkGetInfo(duint Address, BOOKMARKSINFO* info)
{
return bookmarks.GetInfo(Bookmarks::VaKey(Address), info);
} |
C/C++ | x64dbg-development/src/dbg/bookmark.h | #ifndef _BOOKMARK_H
#define _BOOKMARK_H
#include "_global.h"
#include "addrinfo.h"
struct BOOKMARKSINFO : AddrInfo
{
};
bool BookmarkSet(duint Address, bool Manual);
bool BookmarkGet(duint Address);
bool BookmarkDelete(duint Address);
void BookmarkDelRange(duint Start, duint End, bool Manual);
void BookmarkCacheSave(JSON Root);
void BookmarkCacheLoad(JSON Root);
bool BookmarkEnum(BOOKMARKSINFO* List, size_t* Size);
void BookmarkClear();
void BookmarkGetList(std::vector<BOOKMARKSINFO> & list);
bool BookmarkGetInfo(duint Address, BOOKMARKSINFO* info);
#endif // _BOOKMARK_H |
C++ | x64dbg-development/src/dbg/breakpoint.cpp | /**
@file breakpoint.cpp
@brief Implements the breakpoint class.
*/
#include "breakpoint.h"
#include "memory.h"
#include "threading.h"
#include "module.h"
#include "value.h"
#include "debugger.h"
#include "exception.h"
#include <algorithm>
typedef std::pair<BP_TYPE, duint> BreakpointKey;
std::map<BreakpointKey, BREAKPOINT> breakpoints;
static void setBpActive(BREAKPOINT & bp)
{
// DLL/Exception breakpoints are always enabled
if(bp.type == BPDLL || bp.type == BPEXCEPTION)
{
bp.active = true;
return;
}
// Breakpoints without modules need a valid address
if(!*bp.mod)
{
bp.active = MemIsValidReadPtr(bp.addr);
return;
}
else
{
auto modLoaded = ModBaseFromName(bp.mod) != 0;
if(bp.type == BPHARDWARE)
bp.active = modLoaded;
else
bp.active = modLoaded && MemIsValidReadPtr(bp.addr);
}
}
BREAKPOINT* BpInfoFromAddr(BP_TYPE Type, duint Address)
{
//
// NOTE: THIS DOES _NOT_ USE LOCKS
//
std::map<BreakpointKey, BREAKPOINT>::iterator found;
if(Type != BPDLL && Type != BPEXCEPTION)
found = breakpoints.find(BreakpointKey(Type, ModHashFromAddr(Address)));
else
found = breakpoints.find(BreakpointKey(Type, Address)); // Address = ModHashFromName(ModuleName)
// Was the module found with this address?
if(found == breakpoints.end())
return nullptr;
return &found->second;
}
int BpGetList(std::vector<BREAKPOINT>* List)
{
SHARED_ACQUIRE(LockBreakpoints);
// Did the caller request an output?
if(List)
{
// Enumerate all breakpoints in the global list, fixing the relative
// offset to a virtual address
for(auto & i : breakpoints)
{
BREAKPOINT currentBp = i.second;
if(currentBp.type != BPDLL && currentBp.type != BPEXCEPTION)
currentBp.addr += ModBaseFromName(currentBp.mod);
setBpActive(currentBp);
List->push_back(currentBp);
}
std::sort(List->begin(), List->end(), [](const BREAKPOINT & a, const BREAKPOINT & b)
{
return std::make_pair(a.type, a.addr) < std::make_pair(b.type, b.addr);
});
}
return (int)breakpoints.size();
}
bool BpNew(duint Address, bool Enable, bool Singleshot, short OldBytes, BP_TYPE Type, DWORD TitanType, const char* Name, duint memsize)
{
ASSERT_DEBUGGING("Export call");
// Fail if the address is a bad memory region
if(Type != BPDLL && Type != BPEXCEPTION)
{
if(!MemIsValidReadPtr(Address))
return false;
}
// Fail if the breakpoint already exists
if(BpGet(Address, Type, Name, nullptr))
return false;
// Default to an empty name if one wasn't supplied
if(!Name)
Name = "";
BREAKPOINT bp;
memset(&bp, 0, sizeof(BREAKPOINT));
if(Type != BPDLL && Type != BPEXCEPTION)
{
ModNameFromAddr(Address, bp.mod, true);
}
strncpy_s(bp.name, Name, _TRUNCATE);
bp.active = true;
if(Type != BPDLL && Type != BPEXCEPTION)
bp.addr = Address - ModBaseFromAddr(Address);
else
bp.addr = Address;
bp.enabled = Enable;
bp.oldbytes = OldBytes;
bp.singleshoot = Singleshot;
bp.titantype = TitanType;
bp.type = Type;
bp.memsize = memsize;
// Insert new entry to the global list
EXCLUSIVE_ACQUIRE(LockBreakpoints);
if(Type != BPDLL && Type != BPEXCEPTION)
{
return breakpoints.insert(std::make_pair(BreakpointKey(Type, ModHashFromAddr(Address)), bp)).second;
}
else
{
return breakpoints.insert(std::make_pair(BreakpointKey(Type, Address), bp)).second;
}
}
bool BpNewDll(const char* module, bool Enable, bool Singleshot, DWORD TitanType, const char* Name)
{
// Default to an empty name if one wasn't supplied
if(!Name)
Name = "";
BREAKPOINT bp;
memset(&bp, 0, sizeof(BREAKPOINT));
strcpy_s(bp.mod, module);
strcpy_s(bp.name, Name);
bp.active = true;
bp.enabled = Enable;
bp.singleshoot = Singleshot;
bp.titantype = TitanType;
bp.type = BPDLL;
bp.addr = BpGetDLLBpAddr(module);
// Insert new entry to the global list
EXCLUSIVE_ACQUIRE(LockBreakpoints);
return breakpoints.insert(std::make_pair(BreakpointKey(BPDLL, bp.addr), bp)).second;
}
bool BpGet(duint Address, BP_TYPE Type, const char* Name, BREAKPOINT* Bp)
{
if(!DbgIsDebugging())
return false;
SHARED_ACQUIRE(LockBreakpoints);
// Name is optional
if(!Name || Name[0] == '\0')
{
// Perform a lookup by address only
BREAKPOINT* bpInfo = BpInfoFromAddr(Type, Address);
if(!bpInfo)
return false;
// Succeed even if the user didn't request anything
if(!Bp)
return true;
*Bp = *bpInfo;
if(bpInfo->type != BPDLL && bpInfo->type != BPEXCEPTION)
Bp->addr += ModBaseFromAddr(Address);
setBpActive(*Bp);
return true;
}
// If name in a special format "libwinpthread-1.dll":$7792, find the breakpoint even if the DLL might not be loaded yet.
const char* separatorPos;
separatorPos = strstr(Name, ":$"); //DLL file names cannot contain ":" char anyway, so ignoring the quotes is fine. The following part of RVA expression might contain ":$"?
if(separatorPos && Type != BPDLL && Type != BPEXCEPTION)
{
char* DLLName = _strdup(Name);
char* RVAPos = DLLName + (separatorPos - Name);
RVAPos[0] = RVAPos[1] = '\0';
RVAPos = RVAPos + 2; //Now 2 strings separated by NULs
duint Rva;
if(valfromstring(RVAPos, &Rva))
{
if(separatorPos != Name) //Check if DLL name is surrounded by quotes. Don't be out of bounds!
{
if(DLLName[0] == '"' && RVAPos[-3] == '"')
{
RVAPos[-3] = '\0';
DLLName[0] = '\0';
}
}
if(DLLName[0] != '\0')
{
duint base = ModBaseFromName(DLLName); //Is the DLL actually loaded?
Rva += base ? base : ModHashFromName(DLLName);
}
else
{
duint base = ModBaseFromName(DLLName + 1);
Rva += base ? base : ModHashFromName(DLLName + 1);
}
free(DLLName);
// Perform a lookup by address only
BREAKPOINT* bpInfo = BpInfoFromAddr(Type, Rva);
if(!bpInfo)
return false;
// Succeed even if the user didn't request anything
if(!Bp)
return true;
*Bp = *bpInfo;
Bp->addr = Rva;
setBpActive(*Bp);
return true;
}
else
{
free(DLLName);
}
}
// Do a lookup by breakpoint name
for(auto & i : breakpoints)
{
// Breakpoint name match
if(_stricmp(Name, i.second.name) != 0)
// Module name match in case of DLL Breakpoints
if(i.second.type != BPDLL || _stricmp(Name, i.second.mod) != 0)
continue;
// Fill out the optional user buffer
if(Bp)
{
*Bp = i.second;
if(i.second.type != BPDLL && i.second.type != BPEXCEPTION)
Bp->addr += ModBaseFromAddr(Address);
setBpActive(*Bp);
}
// Return true if the name was found at all
return true;
}
return false;
}
bool BpGetAny(BP_TYPE Type, const char* Name, BREAKPOINT* Bp)
{
if(BpGet(0, Type, Name, Bp))
return true;
if(Type != BPDLL)
{
duint addr;
if(valfromstring(Name, &addr))
if(BpGet(addr, Type, 0, Bp))
return true;
if(Type == BPEXCEPTION)
{
addr = 0;
if(ExceptionNameToCode(Name, reinterpret_cast<unsigned int*>(&addr)))
if(BpGet(addr, BPEXCEPTION, 0, Bp))
return true;
}
}
else
{
if(BpGet(BpGetDLLBpAddr(Name), Type, 0, Bp))
return true;
}
return false;
}
bool BpUpdateDllPath(const char* module1, BREAKPOINT** newBpInfo)
{
const char* dashPos1 = max(strrchr(module1, '\\'), strrchr(module1, '/'));
EXCLUSIVE_ACQUIRE(LockBreakpoints);
for(auto & i : breakpoints)
{
BREAKPOINT & bpRef = i.second;
if(bpRef.type == BPDLL && bpRef.enabled)
{
if(_stricmp(bpRef.mod, module1) == 0)
{
BREAKPOINT temp;
temp = bpRef;
strcpy_s(temp.mod, module1);
_strlwr_s(temp.mod, strlen(temp.mod) + 1);
temp.addr = ModHashFromName(module1);
breakpoints.erase(i.first);
auto newItem = breakpoints.insert(std::make_pair(BreakpointKey(BPDLL, temp.addr), temp));
*newBpInfo = &newItem.first->second;
return true;
}
const char* dashPos = max(strrchr(bpRef.mod, '\\'), strrchr(bpRef.mod, '/'));
if(dashPos == nullptr)
dashPos = bpRef.mod;
else
dashPos += 1;
if(dashPos1 != nullptr && _stricmp(dashPos, dashPos1 + 1) == 0) // filename matches
{
BREAKPOINT temp;
temp = bpRef;
strcpy_s(temp.mod, dashPos1 + 1);
_strlwr_s(temp.mod, strlen(temp.mod) + 1);
temp.addr = ModHashFromName(dashPos1 + 1);
breakpoints.erase(i.first);
auto newItem = breakpoints.insert(std::make_pair(BreakpointKey(BPDLL, temp.addr), temp));
*newBpInfo = &newItem.first->second;
return true;
}
}
}
*newBpInfo = nullptr;
return false;
}
duint BpGetDLLBpAddr(const char* fileName)
{
const char* dashPos1 = max(strrchr(fileName, '\\'), strrchr(fileName, '/'));
if(dashPos1 == nullptr)
dashPos1 = fileName;
else
dashPos1++;
return ModHashFromName(dashPos1);
}
bool BpDelete(duint Address, BP_TYPE Type)
{
ASSERT_DEBUGGING("Command function call");
EXCLUSIVE_ACQUIRE(LockBreakpoints);
// Erase the index from the global list
if(Type != BPDLL && Type != BPEXCEPTION)
return breakpoints.erase(BreakpointKey(Type, ModHashFromAddr(Address))) > 0;
else
return breakpoints.erase(BreakpointKey(Type, Address)) > 0;
}
bool BpDelete(const BREAKPOINT & Bp)
{
// Breakpoints without a module can be deleted without special logic
if(Bp.type == BPDLL || Bp.type == BPEXCEPTION || Bp.mod[0] == '\0')
return breakpoints.erase(BreakpointKey(Bp.type, Bp.addr)) > 0;
// Extract the RVA from the breakpoint
auto rva = Bp.addr;
auto loadedBase = ModBaseFromName(Bp.mod);
if(loadedBase != 0 && Bp.addr > loadedBase)
rva -= loadedBase;
// Calculate the breakpoint key with the module hash and rva
auto modHash = ModHashFromName(Bp.mod);
return breakpoints.erase(BreakpointKey(Bp.type, modHash + rva)) > 0;
}
bool BpEnable(duint Address, BP_TYPE Type, bool Enable)
{
ASSERT_DEBUGGING("Command function call");
EXCLUSIVE_ACQUIRE(LockBreakpoints);
// Check if the breakpoint exists first
BREAKPOINT* bpInfo = BpInfoFromAddr(Type, Address);
if(!bpInfo)
return false;
bpInfo->enabled = Enable;
//Re-read oldbytes
if(Enable && Type == BPNORMAL)
{
if(!MemRead(Address, &bpInfo->oldbytes, sizeof(bpInfo->oldbytes)))
return false;
}
return true;
}
bool BpSetName(duint Address, BP_TYPE Type, const char* Name)
{
ASSERT_DEBUGGING("Future(?): This is not used anywhere");
EXCLUSIVE_ACQUIRE(LockBreakpoints);
// If a name wasn't supplied, set to nothing
if(!Name)
Name = "";
// Check if the breakpoint exists first
BREAKPOINT* bpInfo = BpInfoFromAddr(Type, Address);
if(!bpInfo)
return false;
strncpy_s(bpInfo->name, Name, _TRUNCATE);
return true;
}
bool BpSetTitanType(duint Address, BP_TYPE Type, int TitanType)
{
ASSERT_DEBUGGING("Command function call");
EXCLUSIVE_ACQUIRE(LockBreakpoints);
// Set the TitanEngine type, separate from BP_TYPE
BREAKPOINT* bpInfo = BpInfoFromAddr(Type, Address);
if(!bpInfo)
return false;
bpInfo->titantype = TitanType;
return true;
}
bool BpSetBreakCondition(duint Address, BP_TYPE Type, const char* Condition)
{
ASSERT_DEBUGGING("Command function call");
EXCLUSIVE_ACQUIRE(LockBreakpoints);
// Set breakpoint breakCondition
BREAKPOINT* bpInfo = BpInfoFromAddr(Type, Address);
if(!bpInfo)
return false;
strncpy_s(bpInfo->breakCondition, Condition, _TRUNCATE);
return true;
}
bool BpSetLogText(duint Address, BP_TYPE Type, const char* Log)
{
ASSERT_DEBUGGING("Command function call");
EXCLUSIVE_ACQUIRE(LockBreakpoints);
// Set breakpoint logText
BREAKPOINT* bpInfo = BpInfoFromAddr(Type, Address);
if(!bpInfo)
return false;
strncpy_s(bpInfo->logText, Log, _TRUNCATE);
// Make log breakpoints silent (meaning they don't output the default log).
bpInfo->silent = *Log != '\0';
return true;
}
bool BpSetLogCondition(duint Address, BP_TYPE Type, const char* Condition)
{
ASSERT_DEBUGGING("Command function call");
EXCLUSIVE_ACQUIRE(LockBreakpoints);
// Set breakpoint logText
BREAKPOINT* bpInfo = BpInfoFromAddr(Type, Address);
if(!bpInfo)
return false;
strncpy_s(bpInfo->logCondition, Condition, _TRUNCATE);
return true;
}
bool BpSetCommandText(duint Address, BP_TYPE Type, const char* Cmd)
{
ASSERT_DEBUGGING("Command function call");
EXCLUSIVE_ACQUIRE(LockBreakpoints);
// Set breakpoint hit command
BREAKPOINT* bpInfo = BpInfoFromAddr(Type, Address);
if(!bpInfo)
return false;
strncpy_s(bpInfo->commandText, Cmd, _TRUNCATE);
return true;
}
bool BpSetCommandCondition(duint Address, BP_TYPE Type, const char* Condition)
{
ASSERT_DEBUGGING("Command function call");
EXCLUSIVE_ACQUIRE(LockBreakpoints);
// Set breakpoint hit command
BREAKPOINT* bpInfo = BpInfoFromAddr(Type, Address);
if(!bpInfo)
return false;
strncpy_s(bpInfo->commandCondition, Condition, _TRUNCATE);
return true;
}
bool BpSetFastResume(duint Address, BP_TYPE Type, bool fastResume)
{
ASSERT_DEBUGGING("Command function call");
EXCLUSIVE_ACQUIRE(LockBreakpoints);
// Set breakpoint fast resume
BREAKPOINT* bpInfo = BpInfoFromAddr(Type, Address);
if(!bpInfo)
return false;
bpInfo->fastResume = fastResume;
return true;
}
bool BpSetSingleshoot(duint Address, BP_TYPE Type, bool singleshoot)
{
ASSERT_DEBUGGING("Command function call");
EXCLUSIVE_ACQUIRE(LockBreakpoints);
// Set breakpoint singleshoot
BREAKPOINT* bpInfo = BpInfoFromAddr(Type, Address);
if(!bpInfo)
return false;
bpInfo->singleshoot = singleshoot;
// Update singleshoot information in TitanEngine
switch(Type)
{
case BPNORMAL:
bpInfo->titantype = (bpInfo->titantype & ~UE_SINGLESHOOT) | (singleshoot ? UE_SINGLESHOOT : 0);
if(IsBPXEnabled(Address) && bpInfo->enabled)
{
if(!DeleteBPX(Address))
dprintf(QT_TRANSLATE_NOOP("DBG", "Delete breakpoint failed (DeleteBPX): %p\n"), Address);
if(!SetBPX(Address, bpInfo->titantype, cbUserBreakpoint))
dprintf(QT_TRANSLATE_NOOP("DBG", "Error setting breakpoint at %p! (SetBPX)\n"), Address);
}
break;
case BPMEMORY:
if(bpInfo->enabled)
{
if(!RemoveMemoryBPX(Address, bpInfo->memsize))
dprintf(QT_TRANSLATE_NOOP("DBG", "Delete memory breakpoint failed (RemoveMemoryBPX): %p\n"), Address);
if(!SetMemoryBPXEx(Address, bpInfo->memsize, bpInfo->titantype, !singleshoot, cbMemoryBreakpoint))
dprintf(QT_TRANSLATE_NOOP("DBG", "Could not enable memory breakpoint %p (SetMemoryBPXEx)\n"), Address);
}
break;
}
return true;
}
bool BpSetSilent(duint Address, BP_TYPE Type, bool silent)
{
ASSERT_DEBUGGING("Command function call");
EXCLUSIVE_ACQUIRE(LockBreakpoints);
// Set breakpoint fast resume
BREAKPOINT* bpInfo = BpInfoFromAddr(Type, Address);
if(!bpInfo)
return false;
bpInfo->silent = silent;
return true;
}
bool BpEnumAll(BPENUMCALLBACK EnumCallback, const char* Module, duint base)
{
ASSERT_DEBUGGING("Export call");
SHARED_ACQUIRE(LockBreakpoints);
// Loop each entry, executing the user's callback
bool callbackStatus = true;
for(auto i = breakpoints.begin(); i != breakpoints.end();)
{
auto j = i;
++i; // Increment here, because the callback might remove the current entry
// If a module name was sent, check it
if(Module)
{
if(strcmp(j->second.mod, Module) != 0)
continue;
}
BREAKPOINT bpInfo = j->second;
if(bpInfo.type != BPDLL && bpInfo.type != BPEXCEPTION)
{
if(base) //workaround for some Windows bullshit with compatibility mode
bpInfo.addr += base;
else
bpInfo.addr += ModBaseFromName(bpInfo.mod);
}
setBpActive(bpInfo);
// Lock must be released due to callback sub-locks
SHARED_RELEASE();
// Execute the callback
if(!EnumCallback(&bpInfo))
callbackStatus = false;
// Restore the breakpoint map lock
SHARED_REACQUIRE();
}
return callbackStatus;
}
bool BpEnumAll(BPENUMCALLBACK EnumCallback)
{
return BpEnumAll(EnumCallback, nullptr);
}
int BpGetCount(BP_TYPE Type, bool EnabledOnly)
{
SHARED_ACQUIRE(LockBreakpoints);
// Count the number of enabled/disabled breakpoint types
int count = 0;
for(auto & i : breakpoints)
{
// Check if the type matches
if(i.first.first != Type)
continue;
// If it's not enabled, skip it
if(EnabledOnly && !i.second.enabled)
continue;
count++;
}
return count;
}
uint32 BpGetHitCount(duint Address, BP_TYPE Type)
{
SHARED_ACQUIRE(LockBreakpoints);
BREAKPOINT* bpInfo = BpInfoFromAddr(Type, Address);
if(!bpInfo)
return 0;
return bpInfo->hitcount;
}
bool BpResetHitCount(duint Address, BP_TYPE Type, uint32 newHitCount)
{
EXCLUSIVE_ACQUIRE(LockBreakpoints);
BREAKPOINT* bpInfo = BpInfoFromAddr(Type, Address);
if(!bpInfo)
return false;
bpInfo->hitcount = newHitCount;
return true;
}
void BpToBridge(const BREAKPOINT* Bp, BRIDGEBP* BridgeBp)
{
//
// Convert a debugger breakpoint to an open/exported
// bridge breakpoint
//
ASSERT_NONNULL(Bp);
ASSERT_NONNULL(BridgeBp);
memset(BridgeBp, 0, sizeof(BRIDGEBP));
strncpy_s(BridgeBp->mod, Bp->mod, _TRUNCATE);
strncpy_s(BridgeBp->name, Bp->name, _TRUNCATE);
strncpy_s(BridgeBp->breakCondition, Bp->breakCondition, _TRUNCATE);
strncpy_s(BridgeBp->logText, Bp->logText, _TRUNCATE);
strncpy_s(BridgeBp->logCondition, Bp->logCondition, _TRUNCATE);
strncpy_s(BridgeBp->commandText, Bp->commandText, _TRUNCATE);
strncpy_s(BridgeBp->commandCondition, Bp->commandCondition, _TRUNCATE);
BridgeBp->active = Bp->active;
BridgeBp->addr = Bp->addr;
BridgeBp->enabled = Bp->enabled;
BridgeBp->singleshoot = Bp->singleshoot;
BridgeBp->fastResume = Bp->fastResume;
BridgeBp->silent = Bp->silent;
BridgeBp->hitCount = Bp->hitcount;
switch(Bp->type)
{
case BPNORMAL:
BridgeBp->type = bp_normal;
break;
case BPHARDWARE:
BridgeBp->type = bp_hardware;
switch(TITANGETDRX(Bp->titantype))
{
case UE_DR0:
BridgeBp->slot = 0;
break;
case UE_DR1:
BridgeBp->slot = 1;
break;
case UE_DR2:
BridgeBp->slot = 2;
break;
case UE_DR3:
BridgeBp->slot = 3;
break;
}
switch(TITANGETSIZE(Bp->titantype))
{
case UE_HARDWARE_SIZE_1:
BridgeBp->hwSize = hw_byte;
break;
case UE_HARDWARE_SIZE_2:
BridgeBp->hwSize = hw_word;
break;
case UE_HARDWARE_SIZE_4:
BridgeBp->hwSize = hw_dword;
break;
case UE_HARDWARE_SIZE_8:
BridgeBp->hwSize = hw_qword;
break;
}
switch(TITANGETTYPE(Bp->titantype))
{
case UE_HARDWARE_READWRITE:
BridgeBp->typeEx = hw_access;
break;
case UE_HARDWARE_WRITE:
BridgeBp->typeEx = hw_write;
break;
case UE_HARDWARE_EXECUTE:
BridgeBp->typeEx = hw_execute;
break;
}
break;
case BPMEMORY:
BridgeBp->type = bp_memory;
switch(Bp->titantype)
{
case UE_MEMORY_READ:
BridgeBp->typeEx = mem_read;
break;
case UE_MEMORY_WRITE:
BridgeBp->typeEx = mem_write;
break;
case UE_MEMORY_EXECUTE:
BridgeBp->typeEx = mem_execute;
break;
case UE_MEMORY:
BridgeBp->typeEx = mem_access;
break;
}
break;
case BPDLL:
BridgeBp->type = bp_dll;
switch(Bp->titantype)
{
case UE_ON_LIB_LOAD:
BridgeBp->typeEx = dll_load;
break;
case UE_ON_LIB_UNLOAD:
BridgeBp->typeEx = dll_unload;
break;
case UE_ON_LIB_ALL:
BridgeBp->typeEx = dll_all;
break;
}
break;
case BPEXCEPTION:
BridgeBp->type = bp_exception;
switch(Bp->titantype) //1:First-chance, 2:Second-chance, 3:Both
{
case 1:
BridgeBp->typeEx = ex_firstchance;
break;
case 2:
BridgeBp->typeEx = ex_secondchance;
break;
case 3:
BridgeBp->typeEx = ex_all;
break;
default:
dprintf_untranslated("Invalid titantype for exception breakpoint %u\n", Bp->titantype);
}
break;
default:
BridgeBp->type = bp_none;
break;
}
}
void BpCacheSave(JSON Root)
{
EXCLUSIVE_ACQUIRE(LockBreakpoints);
// Create a JSON array to store each sub-object with a breakpoint
const JSON jsonBreakpoints = json_array();
// Loop all breakpoints
for(const auto & i : breakpoints)
{
const auto & breakpoint = i.second;
// Ignore single-shot breakpoints
if(breakpoint.singleshoot)
continue;
JSON jsonObj = json_object();
json_object_set_new(jsonObj, "address", json_hex(breakpoint.addr));
json_object_set_new(jsonObj, "enabled", json_boolean(breakpoint.enabled));
if(breakpoint.type == BPNORMAL) // "Normal" breakpoints save the old data
json_object_set_new(jsonObj, "oldbytes", json_hex(breakpoint.oldbytes));
else if(breakpoint.type == BPMEMORY) // Memory breakpoints save the memory size
json_object_set_new(jsonObj, "memsize", json_hex(breakpoint.memsize));
json_object_set_new(jsonObj, "type", json_integer(breakpoint.type));
json_object_set_new(jsonObj, "titantype", json_hex(breakpoint.titantype));
json_object_set_new(jsonObj, "name", json_string(breakpoint.name));
if(breakpoint.type != BPEXCEPTION)
json_object_set_new(jsonObj, "module", json_string(breakpoint.mod));
json_object_set_new(jsonObj, "breakCondition", json_string(breakpoint.breakCondition));
json_object_set_new(jsonObj, "logText", json_string(breakpoint.logText));
json_object_set_new(jsonObj, "logCondition", json_string(breakpoint.logCondition));
json_object_set_new(jsonObj, "commandText", json_string(breakpoint.commandText));
json_object_set_new(jsonObj, "commandCondition", json_string(breakpoint.commandCondition));
json_object_set_new(jsonObj, "fastResume", json_boolean(breakpoint.fastResume));
json_object_set_new(jsonObj, "silent", json_boolean(breakpoint.silent));
json_array_append_new(jsonBreakpoints, jsonObj);
}
if(json_array_size(jsonBreakpoints))
json_object_set(Root, "breakpoints", jsonBreakpoints);
// Notify garbage collector
json_decref(jsonBreakpoints);
}
template<typename T>
static void loadStringValue(JSON value, T & dest, const char* key)
{
auto text = json_string_value(json_object_get(value, key));
if(text)
strncpy_s(dest, text, _TRUNCATE);
}
void BpCacheLoad(JSON Root, bool migrateCommandCondition)
{
EXCLUSIVE_ACQUIRE(LockBreakpoints);
// Get a handle to the root object -> breakpoints subtree
const JSON jsonBreakpoints = json_object_get(Root, "breakpoints");
// Return if there was nothing to load
if(!jsonBreakpoints)
return;
size_t i;
JSON value;
json_array_foreach(jsonBreakpoints, i, value)
{
BREAKPOINT breakpoint;
memset(&breakpoint, 0, sizeof(BREAKPOINT));
breakpoint.type = (BP_TYPE)json_integer_value(json_object_get(value, "type"));
if(breakpoint.type == BPNORMAL)
breakpoint.oldbytes = (unsigned short)(json_hex_value(json_object_get(value, "oldbytes")) & 0xFFFF);
else if(breakpoint.type == BPMEMORY)
breakpoint.memsize = (duint)json_hex_value(json_object_get(value, "memsize"));
breakpoint.addr = (duint)json_hex_value(json_object_get(value, "address"));
breakpoint.enabled = json_boolean_value(json_object_get(value, "enabled"));
breakpoint.titantype = (DWORD)json_hex_value(json_object_get(value, "titantype"));
if(breakpoint.type == BPHARDWARE)
TITANSETDRX(breakpoint.titantype, UE_DR7); // DR7 is used as a sentinel value to prevent wrongful deletion
// String values
loadStringValue(value, breakpoint.name, "name");
if(breakpoint.type != BPEXCEPTION)
loadStringValue(value, breakpoint.mod, "module");
loadStringValue(value, breakpoint.breakCondition, "breakCondition");
loadStringValue(value, breakpoint.logText, "logText");
loadStringValue(value, breakpoint.logCondition, "logCondition");
loadStringValue(value, breakpoint.commandText, "commandText");
loadStringValue(value, breakpoint.commandCondition, "commandCondition");
// On 2023-06-10 the default of the command condition was changed from $breakpointcondition to 1
// If we detect an older database, try to preserve the old behavior.
if(migrateCommandCondition && *breakpoint.commandText != '\0' && *breakpoint.commandCondition == '\0')
{
strcpy_s(breakpoint.commandCondition, "$breakpointcondition");
}
// Fast resume
breakpoint.fastResume = json_boolean_value(json_object_get(value, "fastResume"));
breakpoint.silent = json_boolean_value(json_object_get(value, "silent"));
// Build the hash map key: MOD_HASH + ADDRESS
duint key;
if(breakpoint.type != BPDLL)
{
key = ModHashFromName(breakpoint.mod) + breakpoint.addr;
}
else
{
key = BpGetDLLBpAddr(breakpoint.mod);
}
breakpoints[BreakpointKey(breakpoint.type, key)] = breakpoint;
}
}
void BpClear()
{
EXCLUSIVE_ACQUIRE(LockBreakpoints);
breakpoints.clear();
} |
C/C++ | x64dbg-development/src/dbg/breakpoint.h | #ifndef _BREAKPOINT_H
#define _BREAKPOINT_H
#include "_global.h"
#include "jansson/jansson_x64dbg.h"
#define TITANSETDRX(titantype, drx) titantype &= 0x0FF, titantype |= (((drx - UE_DR0) & 0xF) << 8)
#define TITANGETDRX(titantype) UE_DR0 + ((titantype >> 8) & 0xF)
#define TITANDRXVALID(titantype) TITANGETDRX(titantype) != UE_DR7
#define TITANSETTYPE(titantype, type) titantype &= 0xF0F, titantype |= ((type & 0xF) << 4)
#define TITANGETTYPE(titantype) (titantype >> 4) & 0xF
#define TITANSETSIZE(titantype, size) titantype &= 0xFF0, titantype |= (size & 0xF);
#define TITANGETSIZE(titantype) titantype & 0xF
enum BP_TYPE
{
BPNORMAL = 0,
BPHARDWARE = 1,
BPMEMORY = 2,
BPDLL = 3,
BPEXCEPTION = 4
};
struct BREAKPOINT
{
duint addr; // address of the breakpoint (rva relative to base of mod)
bool enabled; // whether the breakpoint is enabled
bool singleshoot; // whether the breakpoint should be deleted on first hit
bool active; // whether the breakpoint is active or not
bool silent; // whether the breakpoint diplays a default message when hit
unsigned short oldbytes; // original bytes (for software breakpoitns)
BP_TYPE type; // breakpoint type
DWORD titantype; // type passed to titanengine
char name[MAX_BREAKPOINT_SIZE]; // breakpoint name
char mod[MAX_MODULE_SIZE]; // module name
char breakCondition[MAX_CONDITIONAL_EXPR_SIZE]; // condition to stop. If true, debugger halts.
char logText[MAX_CONDITIONAL_TEXT_SIZE]; // text to log.
char logCondition[MAX_CONDITIONAL_EXPR_SIZE]; // condition to log
char commandText[MAX_CONDITIONAL_TEXT_SIZE]; // script command to execute.
char commandCondition[MAX_CONDITIONAL_EXPR_SIZE]; // condition to execute the command
uint32 hitcount; // hit counter
bool fastResume; // if true, debugger resumes without any GUI/Script/Plugin interaction.
duint memsize; // memory breakpoint size (not implemented)
};
// Breakpoint enumeration callback
typedef bool (*BPENUMCALLBACK)(const BREAKPOINT* bp);
BREAKPOINT* BpInfoFromAddr(BP_TYPE Type, duint Address);
int BpGetList(std::vector<BREAKPOINT>* List);
bool BpNew(duint Address, bool Enable, bool Singleshot, short OldBytes, BP_TYPE Type, DWORD TitanType, const char* Name, duint memsize = 0);
bool BpNewDll(const char* module, bool Enable, bool Singleshot, DWORD TitanType, const char* Name);
bool BpGet(duint Address, BP_TYPE Type, const char* Name, BREAKPOINT* Bp);
bool BpGetAny(BP_TYPE Type, const char* Name, BREAKPOINT* Bp);
bool BpDelete(duint Address, BP_TYPE Type);
bool BpDelete(const BREAKPOINT & Bp);
bool BpEnable(duint Address, BP_TYPE Type, bool Enable);
bool BpSetName(duint Address, BP_TYPE Type, const char* Name);
bool BpSetTitanType(duint Address, BP_TYPE Type, int TitanType);
bool BpSetBreakCondition(duint Address, BP_TYPE Type, const char* Condition);
bool BpSetLogText(duint Address, BP_TYPE Type, const char* Log);
bool BpSetLogCondition(duint Address, BP_TYPE Type, const char* Condition);
bool BpSetCommandText(duint Address, BP_TYPE Type, const char* Cmd);
bool BpSetCommandCondition(duint Address, BP_TYPE Type, const char* Condition);
bool BpSetFastResume(duint Address, BP_TYPE Type, bool fastResume);
bool BpSetSingleshoot(duint Address, BP_TYPE Type, bool singleshoot);
bool BpEnumAll(BPENUMCALLBACK EnumCallback, const char* Module, duint base = 0);
bool BpSetSilent(duint Address, BP_TYPE Type, bool silent);
duint BpGetDLLBpAddr(const char* fileName);
bool BpEnumAll(BPENUMCALLBACK EnumCallback);
int BpGetCount(BP_TYPE Type, bool EnabledOnly = false);
uint32 BpGetHitCount(duint Address, BP_TYPE Type);
bool BpResetHitCount(duint Address, BP_TYPE Type, uint32 newHitCount);
void BpToBridge(const BREAKPOINT* Bp, BRIDGEBP* BridgeBp);
void BpCacheSave(JSON Root);
void BpCacheLoad(JSON Root, bool migrateCommandCondition);
void BpClear();
bool BpUpdateDllPath(const char* module1, BREAKPOINT** newBpInfo);
#endif // _BREAKPOINT_H |
C++ | x64dbg-development/src/dbg/command.cpp | /**
@file command.cpp
@brief Implements the command class.
*/
#include "command.h"
#include "value.h"
#include "console.h"
#include "commandparser.h"
#include "expressionparser.h"
#include "variable.h"
#include "cmd-undocumented.h"
COMMAND* cmd_list = 0;
static bool vecContains(std::vector<String>* names, const char* name)
{
for(const auto & cmd : *names)
if(!_stricmp(cmd.c_str(), name))
return true;
return false;
}
/**
\brief Finds a ::COMMAND in a command list.
\param [in] command list.
\param name The name of the command to find.
\param [out] Link to the command.
\return null if it fails, else a ::COMMAND*.
*/
COMMAND* cmdfind(const char* name, COMMAND** link)
{
COMMAND* cur = cmd_list;
if(!cur->names)
return 0;
COMMAND* prev = 0;
while(cur)
{
if(vecContains(cur->names, name))
{
if(link)
*link = prev;
return cur;
}
prev = cur;
cur = cur->next;
}
return 0;
}
bool IsArgumentsLessThan(int argc, int minimumCount)
{
if(argc < minimumCount)
{
dprintf(QT_TRANSLATE_NOOP("DBG", "Not enough arguments! At least %d arguments must be specified.\n"), minimumCount - 1);
return true;
}
return false;
}
/**
\brief Initialize a command list.
\return a ::COMMAND*
*/
COMMAND* cmdinit()
{
cmd_list = (COMMAND*)emalloc(sizeof(COMMAND), "cmdinit:cmd");
memset(cmd_list, 0, sizeof(COMMAND));
return cmd_list;
}
/**
\brief Clear a command list.
\param [in] cmd_list Command list to clear.
*/
void cmdfree()
{
COMMAND* cur = cmd_list;
while(cur)
{
delete cur->names;
COMMAND* next = cur->next;
efree(cur, "cmdfree:cur");
cur = next;
}
}
/**
\brief Creates a new command and adds it to the list.
\param [in,out] command_list Command list. Cannot be null.
\param name The command name.
\param cbCommand The command callback.
\param debugonly true if the command can only be executed in a debugging context.
\return true if the command was successfully added to the list.
*/
bool cmdnew(const char* name, CBCOMMAND cbCommand, bool debugonly)
{
if(!cmd_list || !cbCommand || !name || !*name || cmdfind(name, 0))
return false;
COMMAND* cmd;
bool nonext = false;
if(!cmd_list->names)
{
cmd = cmd_list;
nonext = true;
}
else
cmd = (COMMAND*)emalloc(sizeof(COMMAND), "cmdnew:cmd");
memset(cmd, 0, sizeof(COMMAND));
cmd->names = new std::vector<String>;
auto split = StringUtils::Split(name, ',');
for(const auto & s : split)
{
auto trimmed = StringUtils::Trim(s);
if(trimmed.length())
cmd->names->push_back(trimmed);
}
cmd->cbCommand = cbCommand;
cmd->debugonly = debugonly;
COMMAND* cur = cmd_list;
if(!nonext)
{
while(cur->next)
cur = cur->next;
cur->next = cmd;
}
return true;
}
/**
\brief Gets a ::COMMAND from the command list.
\param [in] command_list Command list.
\param cmd The command to get from the list.
\return null if the command was not found. Otherwise a ::COMMAND*.
*/
COMMAND* cmdget(const char* cmd)
{
char new_cmd[deflen] = "";
strcpy_s(new_cmd, deflen, cmd);
int len = (int)strlen(new_cmd);
int start = 0;
while(start < len && new_cmd[start] != ' ')
start++;
new_cmd[start] = 0;
COMMAND* found = cmdfind(new_cmd, 0);
if(!found)
return 0;
return found;
}
/**
\brief Sets a new command callback and debugonly property in a command list.
\param [in] command_list Command list.
\param name The name of the command to change.
\param cbCommand The new command callback.
\param debugonly The new debugonly value.
\return The old command callback.
*/
CBCOMMAND cmdset(const char* name, CBCOMMAND cbCommand, bool debugonly)
{
if(!cbCommand)
return 0;
COMMAND* found = cmdfind(name, 0);
if(!found)
return 0;
CBCOMMAND old = found->cbCommand;
found->cbCommand = cbCommand;
found->debugonly = debugonly;
return old;
}
/**
\brief Deletes a command from a command list.
\param [in] command_list Command list.
\param name The name of the command to delete.
\return true if the command was deleted.
*/
bool cmddel(const char* name)
{
COMMAND* prev = 0;
COMMAND* found = cmdfind(name, &prev);
if(!found)
return false;
delete found->names;
if(found == cmd_list)
{
COMMAND* next = cmd_list->next;
if(next)
{
memcpy(cmd_list, cmd_list->next, sizeof(COMMAND));
cmd_list->next = next->next;
efree(next, "cmddel:next");
}
else
memset(cmd_list, 0, sizeof(COMMAND));
}
else
{
prev->next = found->next;
efree(found, "cmddel:found");
}
return true;
}
bool cbCommandProvider(char* cmd, int maxlen);
void cmdsplit(const char* cmd, StringList & commands)
{
commands.clear();
auto len = strlen(cmd);
auto inquote = false;
auto inescape = false;
std::string split;
split.reserve(len);
for(size_t i = 0; i < len; i++)
{
auto ch = cmd[i];
switch(ch) //simple state machine to determine if the ';' separator is in quotes
{
case '\"':
if(!inescape)
inquote = !inquote;
inescape = false;
break;
case '\\':
inescape = !inescape;
break;
default:
inescape = false;
}
if(ch == ';' && !inquote)
{
if(!split.empty())
commands.push_back(split);
split.clear();
}
else
split.push_back(ch);
}
if(!split.empty())
commands.push_back(split);
}
bool cmdexeccallback(COMMAND* cmd, const std::string & command)
{
Command commandParsed(command);
int argcount = commandParsed.GetArgCount();
char** argv = (char**)emalloc((argcount + 1) * sizeof(char*), "cmdloop:argv");
argv[0] = (char*)command.c_str();
for(int i = 0; i < argcount; i++)
{
argv[i + 1] = (char*)emalloc(deflen, "cmdloop:argv[i+1]");
*argv[i + 1] = 0;
strcpy_s(argv[i + 1], deflen, commandParsed.GetArg(i).c_str());
}
auto res = cmd->cbCommand(argcount + 1, argv);
for(int i = 0; i < argcount; i++)
efree(argv[i + 1], "cmdloop:argv[i+1]");
efree(argv, "cmdloop:argv");
return res;
}
/**
\brief Initiates the command loop. This function will not return until a command returns ::STATUS_EXIT.
\return A bool, will always be ::STATUS_EXIT.
*/
void cmdloop()
{
char command_[deflen] = "";
StringList commands;
commands.reserve(100);
while(true)
{
if(!cbCommandProvider(command_, deflen))
break;
cmdsplit(command_, commands);
for(auto & command : commands)
{
command = StringUtils::Trim(command);
if(command.empty()) //skip empty commands
continue;
COMMAND* found = cmdget(command.c_str());
if(!found || !found->cbCommand) //unknown command
{
char* argv[1];
*argv = (char*)command.c_str();
if(!cbBadCmd(1, argv)) //stop processing on non-value commands
break;
continue;
}
if(found->debugonly && !DbgIsDebugging()) //stop processing on debug-only commands
{
dprintf(QT_TRANSLATE_NOOP("DBG", "The command \"%s\" is debug-only\n"), command.c_str());
break;
}
//execute command callback
if(!cmdexeccallback(found, command))
break;
}
}
}
/**
\brief Directly execute a command.
\param [in,out] cmd_list Command list.
\param cmd The command to execute.
\return A bool.
*/
bool cmddirectexec(const char* cmd)
{
// Don't allow anyone to send in empty strings
if(!cmd)
return false;
StringList commands;
cmdsplit(cmd, commands);
for(auto & command : commands)
{
command = StringUtils::Trim(command);
if(command.empty()) //skip empty commands
continue;
COMMAND* found = cmdget(command.c_str());
if(!found || !found->cbCommand) //unknown command
{
ExpressionParser parser(command);
duint result;
if(!parser.Calculate(result, valuesignedcalc(), true, false)) //stop processing on non-value commands
return false;
varset("$ans", result, true);
continue;
}
if(found->debugonly && !DbgIsDebugging()) //stop processing on debug-only commands
{
dprintf(QT_TRANSLATE_NOOP("DBG", "The command \"%s\" is debug-only\n"), command.c_str());
return false;
}
//execute command callback
if(!cmdexeccallback(found, command))
return false;
}
return true;
} |
C/C++ | x64dbg-development/src/dbg/command.h | #ifndef _COMMAND_H
#define _COMMAND_H
#include "_global.h"
#include "console.h"
bool IsArgumentsLessThan(int argc, int minimumCount);
//typedefs
struct COMMAND;
typedef bool(*CBCOMMAND)(int, char**);
typedef bool (*CBCOMMANDPROVIDER)(char*, int);
typedef COMMAND* (*CBCOMMANDFINDER)(char*);
struct COMMAND
{
std::vector<String>* names;
CBCOMMAND cbCommand;
bool debugonly;
COMMAND* next;
};
//functions
COMMAND* cmdinit();
void cmdfree();
COMMAND* cmdfind(const char* name, COMMAND** link);
bool cmdnew(const char* name, CBCOMMAND cbCommand, bool debugonly);
COMMAND* cmdget(const char* cmd);
CBCOMMAND cmdset(const char* name, CBCOMMAND cbCommand, bool debugonly);
bool cmddel(const char* name);
void cmdloop();
bool cmddirectexec(const char* cmd);
#endif // _COMMAND_H |
C++ | x64dbg-development/src/dbg/commandline.cpp | #include "commandline.h"
#include "threading.h"
#include "memory.h"
#include "debugger.h"
#include "console.h"
#include "filehelper.h"
char commandLine[MAX_SETTING_SIZE];
void showcommandlineerror(cmdline_error_t* cmdline_error)
{
bool unkown = false;
switch(cmdline_error->type)
{
case CMDL_ERR_ALLOC:
dputs(QT_TRANSLATE_NOOP("DBG", "Error allocating memory for cmdline"));
break;
case CMDL_ERR_CONVERTUNICODE:
dputs(QT_TRANSLATE_NOOP("DBG", "Error converting UNICODE cmdline"));
break;
case CMDL_ERR_READ_PEBBASE:
dputs(QT_TRANSLATE_NOOP("DBG", "Error reading PEB base addres"));
break;
case CMDL_ERR_READ_PROCPARM_CMDLINE:
dputs(QT_TRANSLATE_NOOP("DBG", "Error reading PEB -> ProcessParameters -> CommandLine UNICODE_STRING"));
break;
case CMDL_ERR_READ_PROCPARM_PTR:
dputs(QT_TRANSLATE_NOOP("DBG", "Error reading PEB -> ProcessParameters pointer address"));
break;
case CMDL_ERR_GET_PEB:
dputs(QT_TRANSLATE_NOOP("DBG", "Error Getting remote PEB address"));
break;
case CMDL_ERR_READ_GETCOMMANDLINEBASE:
dputs(QT_TRANSLATE_NOOP("DBG", "Error Getting command line base address"));
break;
case CMDL_ERR_CHECK_GETCOMMANDLINESTORED:
dputs(QT_TRANSLATE_NOOP("DBG", "Error checking the pattern of the commandline stored"));
break;
case CMDL_ERR_WRITE_GETCOMMANDLINESTORED:
dputs(QT_TRANSLATE_NOOP("DBG", "Error writing the new command line stored"));
break;
case CMDL_ERR_GET_GETCOMMANDLINE:
dputs(QT_TRANSLATE_NOOP("DBG", "Error getting getcommandline"));
break;
case CMDL_ERR_ALLOC_UNICODEANSI_COMMANDLINE:
dputs(QT_TRANSLATE_NOOP("DBG", "Error allocating the page with UNICODE and ANSI command lines"));
break;
case CMDL_ERR_WRITE_ANSI_COMMANDLINE:
dputs(QT_TRANSLATE_NOOP("DBG", "Error writing the ANSI command line in the page"));
break;
case CMDL_ERR_WRITE_UNICODE_COMMANDLINE:
dputs(QT_TRANSLATE_NOOP("DBG", "Error writing the UNICODE command line in the page"));
break;
case CMDL_ERR_WRITE_PEBUNICODE_COMMANDLINE:
dputs(QT_TRANSLATE_NOOP("DBG", "Error writing command line UNICODE in PEB"));
break;
default:
unkown = true;
dputs(QT_TRANSLATE_NOOP("DBG", "Error getting cmdline"));
break;
}
if(!unkown)
{
if(cmdline_error->addr != 0)
dprintf(QT_TRANSLATE_NOOP("DBG", " (Address: %p)"), cmdline_error->addr);
dputs(QT_TRANSLATE_NOOP("DBG", ""));
}
}
bool isCmdLineEmpty()
{
return !strlen(commandLine);
}
char* getCommandLineArgs()
{
auto args = *commandLine == '\"' ? strchr(commandLine + 1, '\"') : nullptr;
args = strchr(args ? args : commandLine, ' ');
return args ? args + 1 : nullptr;
}
void CmdLineCacheSave(JSON Root, const String & cacheFile)
{
EXCLUSIVE_ACQUIRE(LockCmdLine);
// Write the (possibly empty) command line to a cache file
FileHelper::WriteAllText(cacheFile, commandLine);
// return if command line is empty
if(!strlen(commandLine))
return;
// Create a JSON array to store each sub-object with a breakpoint
const JSON jsonCmdLine = json_object();
json_object_set_new(jsonCmdLine, "cmdLine", json_string(commandLine));
json_object_set_new(Root, "commandLine", jsonCmdLine);
}
void CmdLineCacheLoad(JSON Root)
{
EXCLUSIVE_ACQUIRE(LockCmdLine);
// Clear command line
memset(commandLine, 0, sizeof(commandLine));
// Get a handle to the root object -> commandLine
const JSON jsonCmdLine = json_object_get(Root, "commandLine");
// Return if there was nothing to load
if(!jsonCmdLine)
return;
const char* cmdLine = json_string_value(json_object_get(jsonCmdLine, "cmdLine"));
copyCommandLine(cmdLine);
json_decref(jsonCmdLine);
}
void copyCommandLine(const char* cmdLine)
{
strncpy_s(commandLine, cmdLine, _TRUNCATE);
}
bool SetCommandLine()
{
cmdline_error_t cmdline_error = { (cmdline_error_type_t)0, 0 };
if(!dbgsetcmdline(commandLine, &cmdline_error))
{
showcommandlineerror(&cmdline_error);
return false;
}
//update the memory map
MemUpdateMap();
GuiUpdateMemoryView();
return true;
} |
C/C++ | x64dbg-development/src/dbg/commandline.h | #ifndef _COMMANDLINE_H
#define _COMMANDLINE_H
#include "_global.h"
#include "command.h"
#include "jansson/jansson_x64dbg.h"
typedef enum
{
CMDL_ERR_READ_PEBBASE = 0,
CMDL_ERR_READ_PROCPARM_PTR,
CMDL_ERR_READ_PROCPARM_CMDLINE,
CMDL_ERR_CONVERTUNICODE,
CMDL_ERR_ALLOC,
CMDL_ERR_GET_PEB,
CMDL_ERR_READ_GETCOMMANDLINEBASE,
CMDL_ERR_CHECK_GETCOMMANDLINESTORED,
CMDL_ERR_WRITE_GETCOMMANDLINESTORED,
CMDL_ERR_GET_GETCOMMANDLINE,
CMDL_ERR_ALLOC_UNICODEANSI_COMMANDLINE,
CMDL_ERR_WRITE_ANSI_COMMANDLINE,
CMDL_ERR_WRITE_UNICODE_COMMANDLINE,
CMDL_ERR_WRITE_PEBUNICODE_COMMANDLINE
} cmdline_error_type_t;
typedef enum
{
NO_QOUTES = 0,
QOUTES_AROUND_EXE,
QOUTES_AT_BEGIN_AND_END,
NO_CLOSE_QUOTE_FOUND
} cmdline_qoutes_placement_t_enum;
typedef struct
{
cmdline_qoutes_placement_t_enum posEnum;
size_t firstPos;
size_t secondPos;
} cmdline_qoutes_placement_t;
typedef struct
{
cmdline_error_type_t type;
duint addr;
} cmdline_error_t;
void showcommandlineerror(cmdline_error_t* cmdline_error);
bool isCmdLineEmpty();
char* getCommandLineArgs();
void CmdLineCacheSave(JSON Root, const String & cacheFile);
void CmdLineCacheLoad(JSON Root);
void copyCommandLine(const char* cmdLine);
bool setCommandLine();
#endif // _COMMANDLINE_H |
C++ | x64dbg-development/src/dbg/commandparser.cpp | #include "commandparser.h"
Command::Command(const String & command)
{
ParseState state = Default;
int len = (int)command.length();
for(int i = 0; i < len; i++)
{
char ch = command[i];
switch(state)
{
case Default:
switch(ch)
{
case '\t':
case ' ':
if(!_tokens.size())
dataFinish();
break;
case ',':
dataFinish();
break;
case '\\':
state = Escaped;
break;
case '\"':
state = Text;
break;
default:
dataAppend(ch);
break;
}
break;
case Escaped:
switch(ch)
{
case '\t':
case ' ':
dataAppend(' ');
break;
case ',':
dataAppend(ch);
break;
case '\"':
dataAppend(ch);
break;
default:
dataAppend('\\');
dataAppend(ch);
break;
}
state = Default;
break;
case Text:
switch(ch)
{
case '\\':
state = TextEscaped;
break;
case '\"':
state = Default;
break;
case '{':
state = StringFormat;
dataAppend(ch);
break;
default:
dataAppend(ch);
break;
}
break;
case TextEscaped:
switch(ch)
{
case '\"':
dataAppend(ch);
break;
case '{':
dataAppend(ch);
break;
case '\\':
dataAppend(ch);
break;
default:
dataAppend('\\');
dataAppend(ch);
break;
}
state = Text;
break;
case StringFormat:
{
auto nextch = i + 1 < len ? command[i + 1] : '\0';
switch(ch)
{
case '{':
if(nextch == '{')
{
dataAppend(ch);
dataAppend(nextch);
i++;
}
else
{
dataAppend(ch);
}
break;
case '}':
if(nextch == '}')
{
dataAppend(ch);
dataAppend(nextch);
i++;
}
else
{
dataAppend(ch);
state = Text;
}
break;
case '\\':
switch(nextch)
{
case '\"':
case '\\':
dataAppend(nextch);
i++;
break;
default:
dataAppend(ch);
break;
}
break;
default:
dataAppend(ch);
break;
}
}
break;
}
}
if(state == Escaped || state == TextEscaped)
dataAppend('\\');
dataFinish();
}
const String Command::GetText()
{
return _tokens.size() ? _tokens[0] : String();
}
const int Command::GetArgCount()
{
return _tokens.size() ? (int)_tokens.size() - 1 : 0;
}
const String Command::GetArg(int argnum)
{
return (int)_tokens.size() < argnum + 1 ? String() : _tokens[argnum + 1];
}
void Command::dataAppend(const char ch)
{
_data += ch;
}
void Command::dataFinish()
{
_tokens.push_back(_data);
_data.clear();
} |
C/C++ | x64dbg-development/src/dbg/commandparser.h | #ifndef _COMMANDPARSER_H
#define _COMMANDPARSER_H
#include "_global.h"
class Command
{
public:
Command(const String & command);
const String GetText();
const String GetArg(const int argnum);
const int GetArgCount();
private:
String _data;
std::vector<String> _tokens;
enum ParseState
{
Default,
Escaped,
Text,
TextEscaped,
StringFormat,
};
void dataFinish();
void dataAppend(const char ch);
};
#endif // _COMMANDPARSER_H |
C++ | x64dbg-development/src/dbg/comment.cpp | #include "comment.h"
struct CommentSerializer : AddrInfoSerializer<COMMENTSINFO>
{
bool Save(const COMMENTSINFO & value) override
{
AddrInfoSerializer::Save(value);
setString("text", value.text);
return true;
}
bool Load(COMMENTSINFO & value) override
{
return AddrInfoSerializer::Load(value) &&
getString("text", value.text);
}
};
struct Comments : AddrInfoHashMap<LockComments, COMMENTSINFO, CommentSerializer>
{
const char* jsonKey() const override
{
return "comments";
}
};
static Comments comments;
bool CommentSet(duint Address, const char* Text, bool Manual)
{
// Make sure the string is supplied, within bounds, and not a special delimiter
if(!Text || Text[0] == '\1' || strlen(Text) >= MAX_COMMENT_SIZE - 1)
return false;
// Delete the comment if no text was supplied
if(Text[0] == '\0')
{
CommentDelete(Address);
return true;
}
// Fill in the structure + add to database
COMMENTSINFO comment;
if(!comments.PrepareValue(comment, Address, Manual))
return false;
comment.text = Text;
return comments.Add(comment);
}
bool CommentGet(duint Address, char* Text)
{
COMMENTSINFO comment;
if(!comments.Get(Comments::VaKey(Address), comment))
return false;
if(comment.manual)
strncpy_s(Text, MAX_COMMENT_SIZE, comment.text.c_str(), _TRUNCATE);
else
_snprintf_s(Text, MAX_COMMENT_SIZE, _TRUNCATE, "\1%s", comment.text.c_str());
return true;
}
bool CommentDelete(duint Address)
{
return comments.Delete(Comments::VaKey(Address));
}
void CommentDelRange(duint Start, duint End, bool Manual)
{
comments.DeleteRange(Start, End, Manual);
}
void CommentCacheSave(JSON Root)
{
comments.CacheSave(Root);
}
void CommentCacheLoad(JSON Root)
{
comments.CacheLoad(Root);
comments.CacheLoad(Root, "auto"); //legacy support
}
bool CommentEnum(COMMENTSINFO* List, size_t* Size)
{
return comments.Enum(List, Size);
}
void CommentClear()
{
comments.Clear();
}
void CommentGetList(std::vector<COMMENTSINFO> & list)
{
comments.GetList(list);
}
bool CommentGetInfo(duint Address, COMMENTSINFO* info)
{
return comments.GetInfo(Comments::VaKey(Address), info);
} |
C/C++ | x64dbg-development/src/dbg/comment.h | #ifndef _COMMENT_H
#define _COMMENT_H
#include "_global.h"
#include "addrinfo.h"
struct COMMENTSINFO : AddrInfo
{
std::string text;
};
bool CommentSet(duint Address, const char* Text, bool Manual);
bool CommentGet(duint Address, char* Text);
bool CommentDelete(duint Address);
void CommentDelRange(duint Start, duint End, bool Manual);
void CommentCacheSave(JSON Root);
void CommentCacheLoad(JSON Root);
bool CommentEnum(COMMENTSINFO* List, size_t* Size);
void CommentClear();
void CommentGetList(std::vector<COMMENTSINFO> & list);
bool CommentGetInfo(duint Address, COMMENTSINFO* info);
#endif // _COMMENT_H |
C++ | x64dbg-development/src/dbg/console.cpp | /**
\file console.cpp
\brief Implements the console class.
*/
#include "console.h"
#include "taskthread.h"
static void GuiAddLogMessageAsync(_In_z_ const char* msg)
{
static StringConcatTaskThread_<void(*)(const std::string &)> task([](const std::string & msg)
{
GuiAddLogMessage(msg.c_str());
});
task.WakeUp(msg);
}
static void GuiAddLogMessageHtmlAsync(_In_z_ const char* msg)
{
static StringConcatTaskThread_<void(*)(const std::string &)> task([](const std::string & msg)
{
GuiAddLogMessageHtml(msg.c_str());
});
task.WakeUp(msg);
}
/**
\brief Print a line with text, terminated with a newline to the console.
\param text The text to print.
*/
void dputs(_In_z_ const char* Text)
{
// Only append the newline if the caller didn't
const char* TranslatedText = GuiTranslateText(Text);
size_t textlen = strlen(TranslatedText);
if(TranslatedText[textlen - 1] != '\n')
{
Memory<char*> buffer(textlen + 2, "dputs");
memcpy(buffer(), TranslatedText, textlen);
buffer()[textlen] = '\n';
buffer()[textlen + 1] = '\0';
GuiAddLogMessageAsync(buffer());
}
else
GuiAddLogMessageAsync(TranslatedText);
}
/**
\brief Print a formatted string to the console.
\param format The printf format to use (see documentation of printf for more information).
*/
void dprintf(_In_z_ _Printf_format_string_ const char* Format, ...)
{
va_list args;
va_start(args, Format);
dprintf_args(Format, args);
va_end(args);
}
void dprintf_untranslated(_In_z_ _Printf_format_string_ const char* Format, ...)
{
va_list args;
va_start(args, Format);
dprintf_args_untranslated(Format, args);
va_end(args);
}
/**
\brief Print a formatted string to the console.
\param format The printf format to use (see documentation of printf for more information).
\param Args The argument buffer passed to the string parser.
*/
void dprintf_args(_In_z_ _Printf_format_string_ const char* Format, va_list Args)
{
char buffer[16384];
vsnprintf_s(buffer, _TRUNCATE, GuiTranslateText(Format), Args);
GuiAddLogMessageAsync(buffer);
}
/**
\brief Print a line with text, terminated with a newline to the console.
\param text The text to print.
*/
void dputs_untranslated(_In_z_ const char* Text)
{
// Only append the newline if the caller didn't
size_t textlen = strlen(Text);
if(Text[textlen - 1] != '\n')
{
Memory<char*> buffer(textlen + 2, "dputs");
memcpy(buffer(), Text, textlen);
buffer()[textlen] = '\n';
buffer()[textlen + 1] = '\0';
GuiAddLogMessageAsync(buffer());
}
else
GuiAddLogMessageAsync(Text);
}
/**
\brief Print a formatted string to the console.
\param format The printf format to use (see documentation of printf for more information).
\param Args The argument buffer passed to the string parser.
*/
void dprintf_args_untranslated(_In_z_ _Printf_format_string_ const char* Format, va_list Args)
{
char buffer[16384];
vsnprintf_s(buffer, _TRUNCATE, Format, Args);
GuiAddLogMessageAsync(buffer);
}
/**
\brief Print a html string to the console.
\param Text The message to use.
*/
void dprint_untranslated_html(_In_z_ _Printf_format_string_ const char* Text)
{
GuiAddLogMessageHtmlAsync(Text);
} |
C/C++ | x64dbg-development/src/dbg/console.h | #ifndef _CONSOLE_H
#define _CONSOLE_H
#include "_global.h"
void dputs(_In_z_ const char* Text);
void dprintf(_In_z_ _Printf_format_string_ const char* Format, ...);
void dprintf_args(_In_z_ _Printf_format_string_ const char* Format, va_list Args);
void dputs_untranslated(_In_z_ const char* Text);
void dprintf_untranslated(_In_z_ _Printf_format_string_ const char* Format, ...);
void dprintf_args_untranslated(_In_z_ _Printf_format_string_ const char* Format, va_list Args);
void dprint_untranslated_html(_In_z_ _Printf_format_string_ const char* Text);
#endif // _CONSOLE_H |
C++ | x64dbg-development/src/dbg/database.cpp | /**
@file database.cpp
@brief Implements runtime database saving and loading.
*/
#include "lz4/lz4file.h"
#include "console.h"
#include "breakpoint.h"
#include "patches.h"
#include "comment.h"
#include "label.h"
#include "bookmark.h"
#include "function.h"
#include "loop.h"
#include "watch.h"
#include "commandline.h"
#include "database.h"
#include "threading.h"
#include "filehelper.h"
#include "xrefs.h"
#include "TraceRecord.h"
#include "encodemap.h"
#include "plugin_loader.h"
#include "argument.h"
#include "filemap.h"
#include "debugger.h"
#include "stringformat.h"
/**
\brief Directory where program databases are stored (usually in \db). UTF-8 encoding.
*/
char dbbasepath[deflen];
/**
\brief The hash of the debuggee stored in the database
*/
duint dbhash = 0;
/**
\brief Path of the current program database. UTF-8 encoding.
*/
char dbpath[deflen];
void DbSave(DbLoadSaveType saveType, const char* dbfile, bool disablecompression)
{
EXCLUSIVE_ACQUIRE(LockDatabase);
auto file = dbfile ? dbfile : dbpath;
auto filename = strrchr(file, '\\');
auto cmdlinepath = filename ? StringUtils::sprintf("%s%s.cmdline", dbbasepath, filename) : file + String(".cmdline");
dprintf(QT_TRANSLATE_NOOP("DBG", "Saving database to %s "), file);
DWORD ticks = GetTickCount();
JSON root = json_object();
// Save only command line
if(saveType == DbLoadSaveType::CommandLine || saveType == DbLoadSaveType::All)
{
CmdLineCacheSave(root, cmdlinepath);
}
if(saveType == DbLoadSaveType::DebugData || saveType == DbLoadSaveType::All)
{
CommentCacheSave(root);
LabelCacheSave(root);
BookmarkCacheSave(root);
FunctionCacheSave(root);
ArgumentCacheSave(root);
LoopCacheSave(root);
XrefCacheSave(root);
EncodeMapCacheSave(root);
TraceRecord.saveToDb(root);
BpCacheSave(root);
WatchCacheSave(root);
//save notes
char* text = nullptr;
GuiGetDebuggeeNotes(&text);
if(text)
{
json_object_set_new(root, "notes", json_string(text));
BridgeFree(text);
}
//save initialization script
const char* initscript = dbggetdebuggeeinitscript();
if(initscript[0] != 0)
{
json_object_set_new(root, "initscript", json_string(initscript));
}
//plugin data
PLUG_CB_LOADSAVEDB pluginSaveDb;
// Some plugins may wish to change this value so that all plugins after his or her plugin will save data into plugin-supplied storage instead of the system's.
// We back up this value so that the debugger is not fooled by such plugins.
JSON pluginRoot = json_object();
pluginSaveDb.root = pluginRoot;
switch(saveType)
{
case DbLoadSaveType::DebugData:
pluginSaveDb.loadSaveType = PLUG_DB_LOADSAVE_DATA;
break;
case DbLoadSaveType::All:
pluginSaveDb.loadSaveType = PLUG_DB_LOADSAVE_ALL;
break;
default:
pluginSaveDb.loadSaveType = 0;
break;
}
plugincbcall(CBTYPE::CB_SAVEDB, &pluginSaveDb);
if(json_object_size(pluginRoot))
json_object_set(root, "plugins", pluginRoot);
json_decref(pluginRoot);
//store the file hash only if other data is saved in the database
if(dbhash != 0 && json_object_size(root))
{
json_object_set_new(root, "hashAlgorithm", json_string("murmurhash"));
json_object_set_new(root, "hash", json_hex(dbhash));
}
}
auto wdbpath = StringUtils::Utf8ToUtf16(file);
if(!dbfile)
CopyFileW(wdbpath.c_str(), (wdbpath + L".bak").c_str(), FALSE); //make a backup
if(json_object_size(root))
{
auto dumpSuccess = false;
auto hFile = CreateFileW(wdbpath.c_str(), GENERIC_WRITE, 0, nullptr, CREATE_ALWAYS, 0, nullptr);
if(hFile != INVALID_HANDLE_VALUE)
{
BufferedWriter bufWriter(hFile);
dumpSuccess = !json_dump_callback(root, [](const char* buffer, size_t size, void* data) -> int
{
return ((BufferedWriter*)data)->Write(buffer, size) ? 0 : -1;
}, &bufWriter, JSON_INDENT(1));
}
if(!dumpSuccess)
{
String error = stringformatinline(StringUtils::sprintf("{winerror@%x}", GetLastError()));
dprintf(QT_TRANSLATE_NOOP("DBG", "\nFailed to write database file !(GetLastError() = %s)\n"), error.c_str());
json_decref(root);
return;
}
if(!disablecompression && !settingboolget("Engine", "DisableDatabaseCompression"))
LZ4_compress_fileW(wdbpath.c_str(), wdbpath.c_str());
}
else //remove database when nothing is in there
{
DeleteFileW(wdbpath.c_str());
DeleteFileW(StringUtils::Utf8ToUtf16(cmdlinepath).c_str());
}
dprintf(QT_TRANSLATE_NOOP("DBG", "%ums\n"), GetTickCount() - ticks);
json_decref(root); //free root
}
void DbLoad(DbLoadSaveType loadType, const char* dbfile)
{
EXCLUSIVE_ACQUIRE(LockDatabase);
auto file = dbfile ? dbfile : dbpath;
// If the file is "bak", load from database backup instead
if(_stricmp(file, "bak") == 0)
{
String dbpath_backup(dbpath);
dbpath_backup.append(".bak");
DbLoad(loadType, dbpath_backup.c_str());
return;
}
// If the file doesn't exist, there is no DB to load
if(!FileExists(file))
return;
if(loadType == DbLoadSaveType::CommandLine)
{
dputs(QT_TRANSLATE_NOOP("DBG", "Loading commandline..."));
String content;
if(FileHelper::ReadAllText(file + String(".cmdline"), content))
{
copyCommandLine(content.c_str());
return;
}
}
else
dprintf(QT_TRANSLATE_NOOP("DBG", "Loading database from %s "), file);
DWORD ticks = GetTickCount();
// Multi-byte (UTF8) file path converted to UTF16
WString databasePathW = StringUtils::Utf8ToUtf16(file);
// Check if we should migrate the breakpoints
bool migrateBreakpoints = false;
{
HANDLE hFile = CreateFileW(databasePathW.c_str(), GENERIC_READ, FILE_SHARE_READ, nullptr, OPEN_EXISTING, 0, 0);
if(hFile != INVALID_HANDLE_VALUE)
{
FILETIME written;
if(GetFileTime(hFile, nullptr, nullptr, &written))
{
// On 2023-06-10 the default of the command condition was changed
SYSTEMTIME smigration = {};
smigration.wYear = 2023;
smigration.wMonth = 6;
smigration.wDay = 10;
FILETIME migration = {};
if(SystemTimeToFileTime(&smigration, &migration))
{
if(CompareFileTime(&written, &migration) < 0)
{
dprintf(QT_TRANSLATE_NOOP("DBG", "(migrating breakpoints) "));
migrateBreakpoints = true;
}
}
}
CloseHandle(hFile);
}
}
// Decompress the file if compression was enabled
bool useCompression = !settingboolget("Engine", "DisableDatabaseCompression");
LZ4_STATUS lzmaStatus = LZ4_INVALID_ARCHIVE;
{
lzmaStatus = LZ4_decompress_fileW(databasePathW.c_str(), databasePathW.c_str());
// Check return code
if(useCompression && lzmaStatus != LZ4_SUCCESS && lzmaStatus != LZ4_INVALID_ARCHIVE)
{
dputs(QT_TRANSLATE_NOOP("DBG", "\nInvalid database file!"));
return;
}
}
// Map the database file
FileMap<char> dbMap;
if(!dbMap.Map(databasePathW.c_str()))
{
String error = stringformatinline(StringUtils::sprintf("{winerror@%x}", GetLastError()));
dprintf(QT_TRANSLATE_NOOP("DBG", "\nFailed to read database file !(GetLastError() = %s)\n"), error.c_str());
return;
}
// Deserialize JSON and validate
JSON root = json_loadb(dbMap.Data(), dbMap.Size(), 0, 0);
// Unmap the database file
dbMap.Unmap();
// Restore the old, compressed file
if(lzmaStatus != LZ4_INVALID_ARCHIVE && useCompression)
LZ4_compress_fileW(databasePathW.c_str(), databasePathW.c_str());
if(!root)
{
dputs(QT_TRANSLATE_NOOP("DBG", "\nInvalid database file (JSON)!"));
return;
}
// Load only command line
if(loadType == DbLoadSaveType::CommandLine || loadType == DbLoadSaveType::All)
{
CmdLineCacheLoad(root);
}
if(loadType == DbLoadSaveType::DebugData || loadType == DbLoadSaveType::All)
{
auto hashalgo = json_string_value(json_object_get(root, "hashAlgorithm"));
if(hashalgo && strcmp(hashalgo, "murmurhash") == 0) //Checking checksum of the debuggee.
dbhash = duint(json_hex_value(json_object_get(root, "hash")));
else
dbhash = 0;
// Finally load all structures
CommentCacheLoad(root);
LabelCacheLoad(root);
BookmarkCacheLoad(root);
FunctionCacheLoad(root);
ArgumentCacheLoad(root);
LoopCacheLoad(root);
XrefCacheLoad(root);
EncodeMapCacheLoad(root);
TraceRecord.loadFromDb(root);
BpCacheLoad(root, migrateBreakpoints);
WatchCacheLoad(root);
// Load notes
const char* text = json_string_value(json_object_get(root, "notes"));
GuiSetDebuggeeNotes(text);
// Initialization script
text = json_string_value(json_object_get(root, "initscript"));
dbgsetdebuggeeinitscript(text);
// Plugins
JSON pluginRoot = json_object_get(root, "plugins");
if(pluginRoot)
{
PLUG_CB_LOADSAVEDB pluginLoadDb;
pluginLoadDb.root = pluginRoot;
switch(loadType)
{
case DbLoadSaveType::DebugData:
pluginLoadDb.loadSaveType = PLUG_DB_LOADSAVE_DATA;
break;
case DbLoadSaveType::All:
pluginLoadDb.loadSaveType = PLUG_DB_LOADSAVE_ALL;
break;
default:
pluginLoadDb.loadSaveType = 0;
break;
}
plugincbcall(CB_LOADDB, &pluginLoadDb);
}
}
// Free root
json_decref(root);
if(loadType != DbLoadSaveType::CommandLine)
dprintf(QT_TRANSLATE_NOOP("DBG", "%ums\n"), GetTickCount() - ticks);
}
void DbClose()
{
DbSave(DbLoadSaveType::All);
DbClear(true);
}
void DbClear(bool terminating)
{
CommentClear();
LabelClear();
BookmarkClear();
FunctionClear();
ArgumentClear();
LoopClear();
XrefClear();
EncodeMapClear();
TraceRecord.clear();
BpClear();
WatchClear();
GuiSetDebuggeeNotes("");
if(terminating)
{
PatchClear();
dbhash = 0;
}
}
void DbSetPath(const char* Directory, const char* ModulePath)
{
EXCLUSIVE_ACQUIRE(LockDatabase);
// Initialize directory only if it was supplied
if(Directory)
{
ASSERT_TRUE(strlen(Directory) > 0);
// Copy to global
strcpy_s(dbbasepath, Directory);
// Create directory
if(!CreateDirectoryW(StringUtils::Utf8ToUtf16(Directory).c_str(), nullptr))
{
if(GetLastError() != ERROR_ALREADY_EXISTS)
{
String error = stringformatinline(StringUtils::sprintf("{winerror@%x}", GetLastError()));
dprintf(QT_TRANSLATE_NOOP("DBG", "Warning: Failed to create database folder '%s'. GetLastError() = %s\n"), Directory, error.c_str());
}
}
}
// The database file path may be relative (dbbasepath) or a full path
if(ModulePath)
{
ASSERT_TRUE(strlen(ModulePath) > 0);
#ifdef _WIN64
const char* dbType = "dd64";
#else
const char* dbType = "dd32";
#endif // _WIN64
// Get the module name and directory
char dbName[deflen];
char fileDir[deflen];
{
// Dir <- file path
strcpy_s(fileDir, ModulePath);
// Find the last instance of a path delimiter (slash)
char* fileStart = strrchr(fileDir, '\\');
if(fileStart)
{
strcpy_s(dbName, fileStart + 1);
fileStart[0] = '\0';
}
else
{
// Directory or file with no extension
strcpy_s(dbName, fileDir);
}
}
auto checkWritable = [](const char* fileDir)
{
auto testfile = StringUtils::Utf8ToUtf16(StringUtils::sprintf("%s\\%X.x64dbg", fileDir, GetTickCount()));
auto hFile = CreateFileW(testfile.c_str(), GENERIC_WRITE, 0, nullptr, CREATE_ALWAYS, 0, nullptr);
if(hFile == INVALID_HANDLE_VALUE)
{
String error = stringformatinline(StringUtils::sprintf("{winerror@%x}", GetLastError()));
dprintf(QT_TRANSLATE_NOOP("DBG", "Cannot write to the program directory (GetLastError() = %s), try running x64dbg as admin...\n"), error.c_str());
return false;
}
CloseHandle(hFile);
DeleteFileW(testfile.c_str());
return true;
};
if(settingboolget("Engine", "SaveDatabaseInProgramDirectory") && checkWritable(fileDir))
{
// Absolute path in the program directory
sprintf_s(dbpath, "%s\\%s.%s", fileDir, dbName, dbType);
}
else
{
// Relative path in debugger directory
sprintf_s(dbpath, "%s\\%s.%s", dbbasepath, dbName, dbType);
}
dprintf(QT_TRANSLATE_NOOP("DBG", "Database file: %s\n"), dbpath);
}
}
/**
\brief Warn the user if the hash in the database and the executable mismatch.
*/
bool DbCheckHash(duint currentHash)
{
if(dbhash != 0 && currentHash != 0 && dbhash != currentHash)
{
dputs(QT_TRANSLATE_NOOP("DBG", "WARNING: The database has a checksum that is different from the module you are debugging. It is possible that your debuggee has been modified since last session. The content of this database may be incorrect."));
dbhash = currentHash;
return false;
}
else
{
dbhash = currentHash;
return true;
}
}
duint DbGetHash()
{
return dbhash;
} |
C/C++ | x64dbg-development/src/dbg/database.h | #ifndef _DATABASE_H
#define _DATABASE_H
#include "_global.h"
enum class DbLoadSaveType
{
CommandLine,
DebugData,
All
};
void DbSave(DbLoadSaveType saveType, const char* dbfile = nullptr, bool disablecompression = false);
void DbLoad(DbLoadSaveType loadType, const char* dbfile = nullptr);
void DbClose();
void DbClear(bool terminating = false);
void DbSetPath(const char* Directory, const char* ModulePath);
bool DbCheckHash(duint currentHash);
duint DbGetHash();
#endif // _DATABASE_H |
C++ | x64dbg-development/src/dbg/datainst_helper.cpp | #include "datainst_helper.h"
#include "encodemap.h"
#include "stringutils.h"
#include "value.h"
#include <zydis_wrapper.h>
#include <algorithm>
std::unordered_map<ENCODETYPE, std::string> disasmMap;
std::unordered_map<std::string, ENCODETYPE> assembleMap;
void initDataInstMap()
{
disasmMap.clear();
assembleMap.clear();
#define INSTRUCTION_MAP(type, desc) disasmMap[type] = desc; \
assembleMap[desc] = type;
INSTRUCTION_MAP(enc_byte, "byte")
INSTRUCTION_MAP(enc_word, "word")
INSTRUCTION_MAP(enc_dword, "dword")
INSTRUCTION_MAP(enc_fword, "fword")
INSTRUCTION_MAP(enc_qword, "qword")
INSTRUCTION_MAP(enc_tbyte, "tbyte")
INSTRUCTION_MAP(enc_oword, "oword")
INSTRUCTION_MAP(enc_real4, "real4")
INSTRUCTION_MAP(enc_real8, "real8")
INSTRUCTION_MAP(enc_real10, "real10")
INSTRUCTION_MAP(enc_mmword, "mmword")
INSTRUCTION_MAP(enc_xmmword, "xmmword")
INSTRUCTION_MAP(enc_ymmword, "ymmword")
INSTRUCTION_MAP(enc_ascii, "ascii")
INSTRUCTION_MAP(enc_unicode, "unicode")
#undef INSTRUCTION_MAP
#define INSTRUCTION_ASSEMBLE_MAP(type, desc) assembleMap[desc] = type;
INSTRUCTION_ASSEMBLE_MAP(enc_byte, "db")
INSTRUCTION_ASSEMBLE_MAP(enc_word, "dw")
INSTRUCTION_ASSEMBLE_MAP(enc_dword, "dd")
INSTRUCTION_ASSEMBLE_MAP(enc_qword, "dq")
#undef INSTRUCTION_ASSEMBLE_MAP
}
String GetDataTypeString(void* buffer, duint size, ENCODETYPE type)
{
switch(type)
{
case enc_byte:
return StringUtils::ToIntegralString<unsigned char>(buffer);
case enc_word:
return StringUtils::ToIntegralString<unsigned short>(buffer);
case enc_dword:
return StringUtils::ToIntegralString<unsigned int>(buffer);
case enc_fword:
return StringUtils::ToHex((unsigned char*)buffer, 6, true);
case enc_qword:
return StringUtils::ToIntegralString<unsigned long long int>(buffer);
case enc_tbyte:
return StringUtils::ToHex((unsigned char*)buffer, 10, true);
case enc_oword:
return StringUtils::ToHex((unsigned char*)buffer, 16, true);
case enc_mmword:
case enc_xmmword:
case enc_ymmword:
return StringUtils::ToHex((unsigned char*)buffer, size, false);
case enc_real4:
return StringUtils::ToFloatingString<float>(buffer);
case enc_real8:
return StringUtils::ToFloatingString<double>(buffer);
case enc_real10:
return StringUtils::ToHex((unsigned char*)buffer, 10, true);
//return ToLongDoubleString(buffer);
case enc_ascii:
return String((const char*)buffer, size);
case enc_unicode:
return StringUtils::Utf16ToUtf8(WString((const wchar_t*)buffer, size / sizeof(wchar_t)));
default:
return StringUtils::ToIntegralString<unsigned char>(buffer);
}
}
String GetDataInstMnemonic(ENCODETYPE type)
{
if(disasmMap.find(type) == disasmMap.end())
type = enc_byte;
if(disasmMap.find(type) == disasmMap.end())
return "???";
return disasmMap[type];
}
String GetDataInstString(void* buffer, duint size, ENCODETYPE type)
{
return GetDataInstMnemonic(type) + " " + GetDataTypeString(buffer, size, type);
}
duint decodesimpledata(const unsigned char* buffer, ENCODETYPE type)
{
switch(type)
{
case enc_byte:
return *((unsigned char*)buffer);
case enc_word:
return *((unsigned short*)buffer);
case enc_dword:
return *((unsigned int*)buffer);
#ifdef _WIN64
case enc_qword:
return *((unsigned long long int*)buffer);
#endif // _WIN64
}
return 0;
}
struct DataInstruction
{
ENCODETYPE type = enc_unknown;
String operand;
};
bool parsedatainstruction(const char* instruction, DataInstruction & di)
{
String instStr = StringUtils::Trim(String(instruction));
size_t pos = instStr.find_first_of(" \t");
String opcode = instStr.substr(0, pos);
std::transform(opcode.begin(), opcode.end(), opcode.begin(), ::tolower);
if(assembleMap.find(opcode) == assembleMap.end())
return false;
di.type = assembleMap[opcode];
pos = instStr.find_first_not_of(" \t", pos);
if(pos == String::npos)
return false;
di.operand = instStr.substr(pos);
return true;
}
bool isdatainstruction(const char* instruction)
{
DataInstruction di;
parsedatainstruction(instruction, di);
return di.type != enc_unknown;
}
bool tryassembledata(duint addr, unsigned char* dest, int destsize, int* size, const char* instruction, char* error)
{
DataInstruction di;
if(!parsedatainstruction(instruction, di))
{
if(di.operand.empty())
strcpy_s(error, MAX_ERROR_SIZE, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Missing operand")));
return false;
}
duint retsize = GetEncodeTypeSize(di.type);
String buffer;
switch(di.type)
{
case enc_byte:
case enc_word:
case enc_dword:
case enc_fword:
case enc_qword:
{
unsigned long long result = 0;
if(!convertLongLongNumber(di.operand.c_str(), result, 16))
{
strcpy_s(error, MAX_ERROR_SIZE, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Failed to convert operand")));
return false;
}
auto buf = (char*)&result;
for(auto i = retsize; i < sizeof(result); i++)
if(buf[i])
{
strcpy_s(error, MAX_ERROR_SIZE, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Operand value too big")));
return false;
}
buffer = String(buf, retsize);
}
break;
case enc_tbyte:
case enc_oword:
{
std::vector<unsigned char> data;
if(!StringUtils::FromHex(StringUtils::PadLeft(di.operand, retsize * 2, '0'), data, true))
{
strcpy_s(error, MAX_ERROR_SIZE, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Invalid operand (FromHex failed)")));
return false;
}
if(data.size() != retsize)
{
#ifdef _WIN64
sprintf_s(error, MAX_ERROR_SIZE, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Invalid size (expected %llu, got %llu)")), retsize, data.size());
#else //x86
sprintf_s(error, MAX_ERROR_SIZE, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Invalid size (expected %u, got %u)")), retsize, data.size());
#endif //_WIN64
return false;
}
buffer = String((char*)data.data(), data.size());
}
break;
case enc_mmword:
case enc_xmmword:
case enc_ymmword:
{
std::vector<unsigned char> data;
if(!StringUtils::FromHex(StringUtils::PadLeft(di.operand, retsize * 2, '0'), data, false))
{
strcpy_s(error, MAX_ERROR_SIZE, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Invalid operand (FromHex failed)")));
return false;
}
if(data.size() != retsize)
{
#ifdef _WIN64
sprintf_s(error, MAX_ERROR_SIZE, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Invalid size (expected %llu, got %llu)")), retsize, data.size());
#else //x86
sprintf_s(error, MAX_ERROR_SIZE, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Invalid size (expected %u, got %u)")), retsize, data.size());
#endif //_WIN64
return false;
}
buffer = String((char*)data.data(), data.size());
}
break;
case enc_real4:
{
retsize = 4;
float f = std::stof(di.operand);
buffer = String((char*)&f, 4);
break;
}
case enc_real8:
{
retsize = 8;
double d = std::stod(di.operand);
buffer = String((char*)&d, 8);
break;
}
case enc_real10:
strcpy_s(error, MAX_ERROR_SIZE, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "80bit extended float is not supported")));
return false; //80 bit float is not supported in MSVC, need to add other library
case enc_ascii:
{
String unescaped;
if(!StringUtils::Unescape(di.operand, unescaped))
{
strcpy_s(error, MAX_ERROR_SIZE, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Invalid string literal")));
return false;
}
if(unescaped.size() > size_t(destsize))
{
strcpy_s(error, MAX_ERROR_SIZE, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "String too long")));
if(size)
{
*size = int(unescaped.size()); //return correct size
return dest == nullptr;
}
return false;
}
retsize = unescaped.size();
buffer = unescaped;
}
break;
case enc_unicode:
{
String unescaped;
if(!StringUtils::Unescape(di.operand, unescaped))
{
strcpy_s(error, MAX_ERROR_SIZE, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Invalid string literal")));
return false;
}
WString unicode = StringUtils::Utf8ToUtf16(unescaped);
if(unicode.size()*sizeof(wchar_t) > size_t(destsize))
{
strcpy_s(error, MAX_ERROR_SIZE, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "String too long")));
if(size)
{
retsize = unicode.size() * 2; //return correct size
return dest == nullptr;
}
return false;
}
retsize = unicode.size() * 2;
buffer = String((char*)unicode.c_str(), retsize);
}
break;
default:
return false;
}
if(retsize > size_t(destsize))
{
strcpy_s(error, MAX_ERROR_SIZE, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Dest buffer too small")));
return false;
}
if(size)
*size = int(retsize);
if(dest)
memcpy_s((char*)dest, retsize, buffer.c_str(), retsize);
return true;
}
bool trydisasm(const unsigned char* buffer, duint addr, DISASM_INSTR* instr, duint codesize)
{
ENCODETYPE type = EncodeMapGetType(addr, codesize);
duint size = EncodeMapGetSize(addr, codesize);
if(type == enc_unknown || type == enc_code)
return false;
memset(instr, 0, sizeof(DISASM_INSTR));
instr->argcount = 1;
instr->type = instr_normal;
instr->arg[0].type = arg_normal;
instr->arg[0].value = decodesimpledata(buffer, type);
strncpy_s(instr->arg[0].mnemonic, GetDataTypeString((void*)buffer, size, type).c_str(), _TRUNCATE);
instr->instr_size = int(size);
String str = GetDataInstString((void*)buffer, MAX_DISASM_BUFFER, type);
strncpy_s(instr->instruction, str.c_str(), _TRUNCATE);
return true;
}
bool trydisasmfast(const unsigned char* data, duint addr, BASIC_INSTRUCTION_INFO* basicinfo, duint codesize)
{
ENCODETYPE type = EncodeMapGetType(addr, codesize);
duint size = EncodeMapGetSize(addr, codesize);
if(type == enc_unknown || type == enc_code)
return false;
memset(basicinfo, 0, sizeof(BASIC_INSTRUCTION_INFO));
basicinfo->type = TYPE_VALUE;
basicinfo->size = int(size);
String str = GetDataInstString((void*)data, MAX_DISASM_BUFFER, type);
strncpy_s(basicinfo->instruction, str.c_str(), _TRUNCATE);
basicinfo->value.size = VALUE_SIZE(size);
basicinfo->value.value = decodesimpledata(data, type);
return true;
} |
C/C++ | x64dbg-development/src/dbg/datainst_helper.h | #pragma once
#include "_global.h"
void initDataInstMap();
bool isdatainstruction(const char* instruction);
bool tryassembledata(duint addr, unsigned char* dest, int destsize, int* size, const char* instruction, char* error);
bool trydisasm(const unsigned char* buffer, duint addr, DISASM_INSTR* instr, duint codesize);
bool trydisasmfast(const unsigned char* buffer, duint addr, BASIC_INSTRUCTION_INFO* basicinfo, duint codesize); |
C++ | x64dbg-development/src/dbg/dbghelp_safe.cpp | #include "_global.h"
#include "dbghelp_safe.h"
static CRITICAL_SECTION criticalSection;
struct Lock
{
explicit Lock(bool weak)
{
if(weak)
success = !!TryEnterCriticalSection(&criticalSection);
else
{
EnterCriticalSection(&criticalSection);
success = true;
}
}
~Lock()
{
if(success)
LeaveCriticalSection(&criticalSection);
}
bool success;
};
#define WEAK_ACQUIRE() Lock __lock(true); if(!__lock.success) return 0;
#define STRONG_ACQUIRE() Lock __lock(false);
void SafeDbghelpInitialize()
{
InitializeCriticalSection(&criticalSection);
}
void SafeDbghelpDeinitialize()
{
DeleteCriticalSection(&criticalSection);
}
DWORD
SafeUnDecorateSymbolName(
__in PCSTR name,
__out_ecount(maxStringLength) PSTR outputString,
__in DWORD maxStringLength,
__in DWORD flags
)
{
STRONG_ACQUIRE();
return UnDecorateSymbolName(name, outputString, maxStringLength, flags);
}
BOOL
SafeSymUnloadModule64(
__in HANDLE hProcess,
__in DWORD64 BaseOfDll
)
{
STRONG_ACQUIRE();
return SymUnloadModule64(hProcess, BaseOfDll);
}
BOOL
SafeSymSetSearchPathW(
__in HANDLE hProcess,
__in_opt PCWSTR SearchPath
)
{
STRONG_ACQUIRE();
return SymSetSearchPathW(hProcess, SearchPath);
}
DWORD
SafeSymSetOptions(
__in DWORD SymOptions
)
{
STRONG_ACQUIRE();
return SymSetOptions(SymOptions);
}
DWORD
SafeSymGetOptions(
)
{
STRONG_ACQUIRE();
return SymGetOptions();
}
/*BOOL
SafeSymInitializeW(
__in HANDLE hProcess,
__in_opt PCWSTR UserSearchPath,
__in BOOL fInvadeProcess
)
{
STRONG_ACQUIRE();
return SymInitializeW(hProcess, UserSearchPath, fInvadeProcess);
}*/
/*BOOL
SafeSymRegisterCallbackW64(
__in HANDLE hProcess,
__in PSYMBOL_REGISTERED_CALLBACK64 CallbackFunction,
__in ULONG64 UserContext
)
{
STRONG_ACQUIRE();
return SymRegisterCallbackW64(hProcess, CallbackFunction, UserContext);
}*/
DWORD64
SafeSymLoadModuleExW(
__in HANDLE hProcess,
__in_opt HANDLE hFile,
__in_opt PCWSTR ImageName,
__in_opt PCWSTR ModuleName,
__in DWORD64 BaseOfDll,
__in DWORD DllSize,
__in_opt PMODLOAD_DATA Data,
__in_opt DWORD Flags
)
{
STRONG_ACQUIRE();
return SymLoadModuleExW(hProcess, hFile, ImageName, ModuleName, BaseOfDll, DllSize, Data, Flags);
}
BOOL
SafeSymGetModuleInfoW64(
__in HANDLE hProcess,
__in DWORD64 qwAddr,
__out PIMAGEHLP_MODULEW64 ModuleInfo
)
{
STRONG_ACQUIRE();
return SymGetModuleInfoW64(hProcess, qwAddr, ModuleInfo);
}
BOOL
SafeSymGetSearchPathW(
__in HANDLE hProcess,
__out_ecount(SearchPathLength) PWSTR SearchPath,
__in DWORD SearchPathLength
)
{
STRONG_ACQUIRE();
return SymGetSearchPathW(hProcess, SearchPath, SearchPathLength);
}
/*BOOL
SafeSymEnumSymbols(
__in HANDLE hProcess,
__in ULONG64 BaseOfDll,
__in_opt PCSTR Mask,
__in PSYM_ENUMERATESYMBOLS_CALLBACK EnumSymbolsCallback,
__in_opt PVOID UserContext
)
{
STRONG_ACQUIRE();
return SymEnumSymbols(hProcess, BaseOfDll, Mask, EnumSymbolsCallback, UserContext);
}*/
/*BOOL
SafeSymGetLineFromAddrW64(
__in HANDLE hProcess,
__in DWORD64 qwAddr,
__out PDWORD pdwDisplacement,
__out PIMAGEHLP_LINEW64 Line64
)
{
STRONG_ACQUIRE();
return SymGetLineFromAddrW64(hProcess, qwAddr, pdwDisplacement, Line64);
}*/
/*BOOL
SafeSymFromName(
__in HANDLE hProcess,
__in PCSTR Name,
__inout PSYMBOL_INFO Symbol
)
{
STRONG_ACQUIRE();
return SymFromName(hProcess, Name, Symbol);
}*/
/*BOOL
SafeSymFromAddr(
__in HANDLE hProcess,
__in DWORD64 Address,
__out_opt PDWORD64 Displacement,
__inout PSYMBOL_INFO Symbol
)
{
STRONG_ACQUIRE();
return SymFromAddr(hProcess, Address, Displacement, Symbol);
}*/
/*BOOL
SafeSymCleanup(
__in HANDLE hProcess
)
{
STRONG_ACQUIRE();
return SymCleanup(hProcess);
}*/
BOOL
SafeStackWalk64(
__in DWORD MachineType,
__in HANDLE hProcess,
__in HANDLE hThread,
__inout LPSTACKFRAME64 StackFrame,
__inout PVOID ContextRecord,
__in_opt PREAD_PROCESS_MEMORY_ROUTINE64 ReadMemoryRoutine,
__in_opt PFUNCTION_TABLE_ACCESS_ROUTINE64 FunctionTableAccessRoutine,
__in_opt PGET_MODULE_BASE_ROUTINE64 GetModuleBaseRoutine,
__in_opt PTRANSLATE_ADDRESS_ROUTINE64 TranslateAddress
)
{
STRONG_ACQUIRE();
return StackWalk64(MachineType, hProcess, hThread, StackFrame, ContextRecord, ReadMemoryRoutine, FunctionTableAccessRoutine, GetModuleBaseRoutine, TranslateAddress);
} |
C/C++ | x64dbg-development/src/dbg/dbghelp_safe.h | #ifndef _DBGHELP_SAFE_H
#define _DBGHELP_SAFE_H
#ifdef __GNUC__
#include "dbghelp\dbghelp.h"
#else
#pragma warning(push)
#pragma warning(disable:4091)
#include <dbghelp.h>
#pragma warning(pop)
#endif //__GNUC__
void SafeDbghelpInitialize();
void SafeDbghelpDeinitialize();
/*DWORD
SafeUnDecorateSymbolName(
__in PCSTR name,
__out_ecount(maxStringLength) PSTR outputString,
__in DWORD maxStringLength,
__in DWORD flags
);*/
BOOL
SafeSymUnloadModule64(
__in HANDLE hProcess,
__in DWORD64 BaseOfDll
);
BOOL
SafeSymSetSearchPathW(
__in HANDLE hProcess,
__in_opt PCWSTR SearchPath
);
DWORD
SafeSymSetOptions(
__in DWORD SymOptions
);
DWORD
SafeSymGetOptions(
);
/*BOOL
SafeSymInitializeW(
__in HANDLE hProcess,
__in_opt PCWSTR UserSearchPath,
__in BOOL fInvadeProcess
);*/
/*BOOL
SafeSymRegisterCallbackW64(
__in HANDLE hProcess,
__in PSYMBOL_REGISTERED_CALLBACK64 CallbackFunction,
__in ULONG64 UserContext
);*/
DWORD64
SafeSymLoadModuleExW(
__in HANDLE hProcess,
__in_opt HANDLE hFile,
__in_opt PCWSTR ImageName,
__in_opt PCWSTR ModuleName,
__in DWORD64 BaseOfDll,
__in DWORD DllSize,
__in_opt PMODLOAD_DATA Data,
__in_opt DWORD Flags
);
BOOL
SafeSymGetModuleInfoW64(
__in HANDLE hProcess,
__in DWORD64 qwAddr,
__out PIMAGEHLP_MODULEW64 ModuleInfo
);
BOOL
SafeSymGetSearchPathW(
__in HANDLE hProcess,
__out_ecount(SearchPathLength) PWSTR SearchPath,
__in DWORD SearchPathLength
);
/*BOOL
SafeSymEnumSymbols(
__in HANDLE hProcess,
__in ULONG64 BaseOfDll,
__in_opt PCSTR Mask,
__in PSYM_ENUMERATESYMBOLS_CALLBACK EnumSymbolsCallback,
__in_opt PVOID UserContext
);*/
/*BOOL
SafeSymGetLineFromAddrW64(
__in HANDLE hProcess,
__in DWORD64 qwAddr,
__out PDWORD pdwDisplacement,
__out PIMAGEHLP_LINEW64 Line64
);*/
/*BOOL
SafeSymFromName(
__in HANDLE hProcess,
__in PCSTR Name,
__inout PSYMBOL_INFO Symbol
);*/
/*BOOL
SafeSymFromAddr(
__in HANDLE hProcess,
__in DWORD64 Address,
__out_opt PDWORD64 Displacement,
__inout PSYMBOL_INFO Symbol
);*/
/*BOOL
SafeSymCleanup(
__in HANDLE hProcess
);*/
BOOL
SafeStackWalk64(
__in DWORD MachineType,
__in HANDLE hProcess,
__in HANDLE hThread,
__inout LPSTACKFRAME64 StackFrame,
__inout PVOID ContextRecord,
__in_opt PREAD_PROCESS_MEMORY_ROUTINE64 ReadMemoryRoutine,
__in_opt PFUNCTION_TABLE_ACCESS_ROUTINE64 FunctionTableAccessRoutine,
__in_opt PGET_MODULE_BASE_ROUTINE64 GetModuleBaseRoutine,
__in_opt PTRANSLATE_ADDRESS_ROUTINE64 TranslateAddress
);
#endif //_DBGHELP_SAFE_H |
C++ | x64dbg-development/src/dbg/debugger.cpp | /**
@file debugger.cpp
@brief Implements the debugger class.
*/
#include "debugger.h"
#include "console.h"
#include "memory.h"
#include "threading.h"
#include "command.h"
#include "database.h"
#include "watch.h"
#include "thread.h"
#include "plugin_loader.h"
#include "breakpoint.h"
#include "symbolinfo.h"
#include "variable.h"
#include "x64dbg.h"
#include "exception.h"
#include "module.h"
#include "commandline.h"
#include "stackinfo.h"
#include "stringformat.h"
#include "TraceRecord.h"
#include "historycontext.h"
#include "taskthread.h"
#include "animate.h"
#include "simplescript.h"
#include "zydis_wrapper.h"
#include "cmd-watch-control.h"
#include "filemap.h"
#include "jit.h"
#include "handle.h"
#include "dbghelp_safe.h"
#include "exprfunc.h"
#include "debugger_cookie.h"
#include "debugger_tracing.h"
#include "handles.h"
// Debugging variables
static PROCESS_INFORMATION g_pi = {0, 0, 0, 0};
static char szBaseFileName[MAX_PATH] = "";
static TraceState traceState;
static bool bFileIsDll = false;
static bool bEntryIsInMzHeader = false;
static duint pDebuggedBase = 0;
static duint pDebuggedEntry = 0;
static bool bRepeatIn = false;
static duint stepRepeat = 0;
static bool bIsAttached = false;
static bool bSkipExceptions = false;
static duint skipExceptionCount = 0;
static bool bFreezeStack = false;
static std::vector<ExceptionFilter> exceptionFilters;
static HANDLE hEvent = 0;
static duint tidToResume = 0;
static HANDLE hMemMapThread = 0;
static bool bStopMemMapThread = false;
static HANDLE hTimeWastedCounterThread = 0;
static bool bStopTimeWastedCounterThread = false;
static HANDLE hDumpRefreshThread = 0;
static bool bStopDumpRefreshThread = false;
static String lastDebugText;
static duint timeWastedDebugging = 0;
static EXCEPTION_DEBUG_INFO lastExceptionInfo = { 0 };
static char szDebuggeeInitializationScript[MAX_PATH] = "";
static WString gInitExe, gInitCmd, gInitDir, gDllLoader;
static CookieQuery cookie;
static duint exceptionDispatchAddr = 0;
static bool bPausedOnException = false;
static HANDLE DebugDLLFileMapping = 0;
static DWORD nextContinueStatus = DBG_EXCEPTION_NOT_HANDLED;
char szProgramDir[MAX_PATH] = "";
char szUserDir[MAX_PATH] = "";
char szDebuggeePath[MAX_PATH] = "";
char szDllLoaderPath[MAX_PATH] = "";
char szSymbolCachePath[MAX_PATH] = "";
std::vector<std::pair<duint, duint>> RunToUserCodeBreakpoints;
PROCESS_INFORMATION* fdProcessInfo = &g_pi;
HANDLE hActiveThread;
HANDLE hProcessToken;
bool bUndecorateSymbolNames = true;
bool bEnableSourceDebugging = false;
bool bSkipInt3Stepping = false;
bool bIgnoreInconsistentBreakpoints = false;
bool bNoForegroundWindow = true;
bool bVerboseExceptionLogging = true;
bool bNoWow64SingleStepWorkaround = false;
bool bTraceBrowserNeedsUpdate = false;
bool bForceLoadSymbols = false;
bool bNewStringAlgorithm = false;
bool bPidTidInHex = false;
bool bWindowLongPath = false;
duint DbgEvents = 0;
duint maxSkipExceptionCount = 0;
HANDLE mProcHandle;
HANDLE mForegroundHandle;
duint gRtrPreviousCSP = 0;
static bool bAbortStepping = false;
static TITANCBSTEP gStepIntoPartyCallback;
HANDLE hDebugLoopThread = nullptr;
DWORD dwDebugFlags = 0;
static duint dbgcleartracestate()
{
auto steps = traceState.StepCount();
traceState.Clear();
return steps;
}
static void dbgClearRtuBreakpoints()
{
EXCLUSIVE_ACQUIRE(LockRunToUserCode);
for(auto & i : RunToUserCodeBreakpoints)
{
BREAKPOINT bp;
if(!BpGet(i.first, BPMEMORY, nullptr, &bp))
RemoveMemoryBPX(i.first, i.second);
}
RunToUserCodeBreakpoints.clear();
}
bool dbgsettracecondition(const String & expression, duint maxSteps)
{
if(dbgtraceactive())
return false;
if(!traceState.InitTraceCondition(expression, maxSteps))
return false;
if(traceState.InitLogFile())
return true;
dbgcleartracestate();
return false;
}
bool dbgsettracelog(const String & expression, const String & text)
{
if(dbgtraceactive())
return false;
return traceState.InitLogCondition(expression, text);
}
bool dbgsettracecmd(const String & expression, const String & text)
{
if(dbgtraceactive())
return false;
return traceState.InitCmdCondition(expression, text);
}
bool dbgtraceactive()
{
return traceState.IsActive();
}
void dbgforcebreaktrace()
{
if(traceState.IsActive())
traceState.SetForceBreakTrace();
}
bool dbgstepactive()
{
return stepRepeat > 1 || gRtrPreviousCSP != 0 || gStepIntoPartyCallback != nullptr;
}
void dbgforcebreakstep()
{
if(dbgstepactive())
{
bAbortStepping = true;
}
}
bool dbgsettracelogfile(const char* fileName)
{
traceState.SetLogFile(fileName);
return true;
}
static DWORD WINAPI memMapThread(void* ptr)
{
while(!bStopMemMapThread)
{
while(!DbgIsDebugging())
{
if(bStopMemMapThread)
break;
Sleep(10);
}
if(bStopMemMapThread)
break;
MemUpdateMapAsync();
ThreadUpdateWaitReasons();
GuiUpdateThreadView();
Sleep(2000);
}
return 0;
}
static bool isUserIdle()
{
LASTINPUTINFO lii;
lii.cbSize = sizeof(LASTINPUTINFO);
GetLastInputInfo(&lii);
return GetTickCount() - lii.dwTime > 1000 * 60; //60 seconds without input is considered idle
}
static DWORD WINAPI timeWastedCounterThread(void* ptr)
{
if(!BridgeSettingGetUint("Engine", "TimeWastedDebugging", &timeWastedDebugging))
timeWastedDebugging = 0;
GuiUpdateTimeWastedCounter();
while(!bStopTimeWastedCounterThread)
{
while(!DbgIsDebugging() || isUserIdle())
{
if(bStopTimeWastedCounterThread)
break;
Sleep(10);
}
if(bStopTimeWastedCounterThread)
break;
timeWastedDebugging++;
GuiUpdateTimeWastedCounter();
Sleep(1000);
}
BridgeSettingSetUint("Engine", "TimeWastedDebugging", timeWastedDebugging);
return 0;
}
static DWORD WINAPI dumpRefreshThread(void* ptr)
{
while(!bStopDumpRefreshThread)
{
while(!DbgIsDebugging())
{
if(bStopDumpRefreshThread)
break;
Sleep(100);
}
if(bStopDumpRefreshThread)
break;
GuiUpdateDumpView();
GuiUpdateWatchView();
if(bTraceBrowserNeedsUpdate)
{
bTraceBrowserNeedsUpdate = false;
GuiUpdateTraceBrowser();
}
Sleep(400);
}
return 0;
}
/**
\brief Called when the debugger pauses.
*/
void cbDebuggerPaused()
{
// Clear tracing conditions
dbgcleartracestate();
dbgClearRtuBreakpoints();
bAbortStepping = false;
stepRepeat = 0;
// Trace record is not handled by this function currently.
// Signal thread switch warning
if(settingboolget("Engine", "HardcoreThreadSwitchWarning"))
{
static DWORD PrevThreadId = 0;
if(PrevThreadId == 0)
PrevThreadId = fdProcessInfo->dwThreadId; // Initialize to Main Thread
DWORD currentThreadId = ThreadGetId(hActiveThread);
if(currentThreadId != PrevThreadId && PrevThreadId != 0)
{
dprintf(QT_TRANSLATE_NOOP("DBG", "Thread switched from %X to %X !\n"), PrevThreadId, currentThreadId);
PrevThreadId = currentThreadId;
}
}
// Watchdog
cbCheckWatchdog(0, nullptr);
}
void dbginit()
{
hTimeWastedCounterThread = CreateThread(nullptr, 0, timeWastedCounterThread, nullptr, 0, nullptr);
hMemMapThread = CreateThread(nullptr, 0, memMapThread, nullptr, 0, nullptr);
hDumpRefreshThread = CreateThread(nullptr, 0, dumpRefreshThread, nullptr, 0, nullptr);
}
void dbgstop()
{
bStopTimeWastedCounterThread = true;
bStopMemMapThread = true;
bStopDumpRefreshThread = true;
HANDLE hThreads[] = { hTimeWastedCounterThread, hMemMapThread, hDumpRefreshThread };
WaitForMultipleThreadsTermination(hThreads, _countof(hThreads), 10000); // Total time out is 10 seconds.
}
duint dbgdebuggedbase()
{
return pDebuggedBase;
}
duint dbggettimewastedcounter()
{
return timeWastedDebugging;
}
bool dbgisrunning()
{
return !waitislocked(WAITID_RUN);
}
bool dbgisdll()
{
return bFileIsDll;
}
void dbgsetattachevent(HANDLE handle)
{
hEvent = handle;
}
void dbgsetresumetid(duint tid)
{
tidToResume = tid;
}
void dbgsetskipexceptions(bool skip)
{
bSkipExceptions = skip;
skipExceptionCount = 0;
}
void dbgsetsteprepeat(bool steppingIn, duint repeat)
{
bRepeatIn = steppingIn;
stepRepeat = repeat;
}
void dbgsetfreezestack(bool freeze)
{
bFreezeStack = freeze;
}
void dbgclearexceptionfilters()
{
exceptionFilters.clear();
}
void dbgaddexceptionfilter(ExceptionFilter filter)
{
exceptionFilters.push_back(filter);
}
const ExceptionFilter & dbggetexceptionfilter(unsigned int exception)
{
for(unsigned int i = 0; i < exceptionFilters.size(); i++)
{
const ExceptionFilter & filter = exceptionFilters.at(i);
unsigned int curStart = filter.range.start;
unsigned int curEnd = filter.range.end;
if(exception >= curStart && exception <= curEnd)
return filter;
}
// no filter found, return the catch-all filter for unknown exceptions
for(unsigned int i = 0; i < exceptionFilters.size(); i++)
{
const ExceptionFilter & filter = exceptionFilters.at(i);
if(filter.range.start == 0 && filter.range.start == filter.range.end)
return filter;
}
// the unknown exceptions filter is not yet present in settings, add it now
ExceptionFilter unknownExceptionsFilter;
unknownExceptionsFilter.range.start = unknownExceptionsFilter.range.end = 0;
unknownExceptionsFilter.breakOn = ExceptionBreakOn::FirstChance;
unknownExceptionsFilter.logException = true;
unknownExceptionsFilter.handledBy = ExceptionHandledBy::Debuggee;
exceptionFilters.push_back(unknownExceptionsFilter);
return exceptionFilters.back();
}
bool dbgcmdnew(const char* name, CBCOMMAND cbCommand, bool debugonly)
{
if(!cmdnew(name, cbCommand, debugonly))
return false;
GuiAutoCompleteAddCmd(name);
return true;
}
bool dbgcmddel(const char* name)
{
if(!cmddel(name))
return false;
GuiAutoCompleteDelCmd(name);
return true;
}
duint dbggetdbgevents()
{
return InterlockedExchange((volatile long*)&DbgEvents, 0);
}
void dbgtracebrowserneedsupdate()
{
bTraceBrowserNeedsUpdate = true;
}
static std::unordered_map<std::string, std::pair<DWORD, bool>> dllBreakpoints;
bool dbgsetdllbreakpoint(const char* mod, DWORD type, bool singleshoot)
{
EXCLUSIVE_ACQUIRE(LockDllBreakpoints);
return dllBreakpoints.insert({ mod, { type, singleshoot } }).second;
}
bool dbgdeletedllbreakpoint(const char* mod, DWORD type)
{
EXCLUSIVE_ACQUIRE(LockDllBreakpoints);
auto found = dllBreakpoints.find(mod);
if(found == dllBreakpoints.end())
return false;
dllBreakpoints.erase(found);
return true;
}
void dbgsetdebugflags(DWORD flags)
{
dwDebugFlags = flags;
}
bool dbghandledllbreakpoint(const char* mod, bool loadDll)
{
EXCLUSIVE_ACQUIRE(LockDllBreakpoints);
auto shouldBreak = false;
auto found = dllBreakpoints.find(mod);
if(found != dllBreakpoints.end())
{
if(found->second.first == UE_ON_LIB_ALL || found->second.first == (loadDll ? UE_ON_LIB_LOAD : UE_ON_LIB_UNLOAD))
shouldBreak = true;
if(found->second.second)
dllBreakpoints.erase(found);
}
return shouldBreak;
}
static DWORD WINAPI updateCallStackThread(duint ptr)
{
stackupdatecallstack(ptr);
GuiUpdateCallStack();
return 0;
}
void updateCallStackAsync(duint ptr)
{
static TaskThread_<decltype(&updateCallStackThread), duint> updateCallStackTask(&updateCallStackThread);
updateCallStackTask.WakeUp(ptr);
}
DWORD WINAPI updateSEHChainThread()
{
GuiUpdateSEHChain();
stackupdateseh();
GuiUpdateDumpView();
return 0;
}
void updateSEHChainAsync()
{
static TaskThread_<decltype(&updateSEHChainThread)> updateSEHChainTask(&updateSEHChainThread);
updateSEHChainTask.WakeUp();
}
static void DebugUpdateTitle(duint disasm_addr, bool analyzeThreadSwitch)
{
if(GuiIsUpdateDisabled() || !DbgIsDebugging())
return;
char modname[MAX_MODULE_SIZE] = "";
char modtext[MAX_MODULE_SIZE * 2] = "";
if(!ModNameFromAddr(disasm_addr, modname, true))
*modname = 0;
else
_snprintf_s(modtext, _TRUNCATE, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Module: %s - ")), modname);
char threadswitch[256] = "";
DWORD currentThreadId = ThreadGetId(hActiveThread);
if(analyzeThreadSwitch)
{
static DWORD PrevThreadId = 0;
if(PrevThreadId == 0)
PrevThreadId = fdProcessInfo->dwThreadId; // Initialize to Main Thread
if(currentThreadId != PrevThreadId && PrevThreadId != 0)
{
char threadName2[MAX_THREAD_NAME_SIZE] = "";
if(!ThreadGetName(PrevThreadId, threadName2) || threadName2[0] == 0)
strcpy_s(threadName2, formatpidtid(PrevThreadId).c_str());
_snprintf_s(threadswitch, _TRUNCATE, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", " (switched from %s)")), threadName2);
PrevThreadId = currentThreadId;
}
}
char title[deflen] = "";
char threadName[MAX_THREAD_NAME_SIZE + 1] = "";
if(ThreadGetName(currentThreadId, threadName) && *threadName)
strcat_s(threadName, " ");
// choose between title here
auto debugeeName = bWindowLongPath ? szDebuggeePath : szBaseFileName;
_snprintf_s(title, _TRUNCATE, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "%s - PID: %s - %sThread: %s%s%s")), debugeeName, formatpidtid(fdProcessInfo->dwProcessId).c_str(), modtext, threadName, formatpidtid(currentThreadId).c_str(), threadswitch);
GuiUpdateWindowTitle(title);
}
void DebugUpdateGui(duint disasm_addr, bool stack)
{
if(GuiIsUpdateDisabled())
return;
duint cip = GetContextDataEx(hActiveThread, UE_CIP);
//Check if the addresses are in the memory map and force update if they are not
if(!MemIsValidReadPtr(disasm_addr, true) || !MemIsValidReadPtr(cip, true))
MemUpdateMap();
else
MemUpdateMapAsync();
if(MemIsValidReadPtr(disasm_addr))
{
if(bEnableSourceDebugging)
{
char szSourceFile[MAX_STRING_SIZE] = "";
int line = 0;
if(SymGetSourceLine(cip, szSourceFile, &line))
GuiLoadSourceFileEx(szSourceFile, cip);
}
GuiDisasmAt(disasm_addr, cip);
}
duint csp = GetContextDataEx(hActiveThread, UE_CSP);
if(stack)
DebugUpdateStack(csp, csp);
static volatile duint cacheCsp = 0;
if(csp != cacheCsp)
{
#ifdef _WIN64
InterlockedExchange((volatile unsigned long long*)&cacheCsp, csp);
#else
InterlockedExchange((volatile unsigned long*)&cacheCsp, csp);
#endif //_WIN64
updateCallStackAsync(csp);
updateSEHChainAsync();
}
DebugUpdateTitle(disasm_addr, true);
GuiUpdateRegisterView();
GuiUpdateDisassemblyView();
GuiUpdateThreadView();
GuiUpdateSideBar();
}
void GuiSetDebugStateAsync(DBGSTATE state)
{
GuiSetDebugStateFast(state);
static TaskThread_<decltype(&GuiSetDebugState), DBGSTATE> GuiSetDebugStateTask(&GuiSetDebugState, 300);
GuiSetDebugStateTask.WakeUp(state);
}
void DebugUpdateGuiAsync(duint disasm_addr, bool stack)
{
static TaskThread_<decltype(&DebugUpdateGui), duint, bool> DebugUpdateGuiTask(&DebugUpdateGui);
DebugUpdateGuiTask.WakeUp(disasm_addr, stack);
}
void DebugUpdateTitleAsync(duint disasm_addr, bool analyzeThreadSwitch)
{
static TaskThread_<decltype(&DebugUpdateTitle), duint, bool> DebugUpdateTitleTask(&DebugUpdateTitle);
DebugUpdateTitleTask.WakeUp(disasm_addr, analyzeThreadSwitch);
}
void DebugUpdateGuiSetStateAsync(duint disasm_addr, DBGSTATE state)
{
// call paused routine to clean up various tracing states.
if(state == paused)
cbDebuggerPaused();
GuiSetDebugStateAsync(state);
DebugUpdateGuiAsync(disasm_addr, true);
}
void DebugUpdateBreakpointsViewAsync()
{
static TaskThread_<decltype(&GuiUpdateBreakpointsView)> BreakpointsUpdateGuiTask(&GuiUpdateBreakpointsView);
BreakpointsUpdateGuiTask.WakeUp();
}
void DebugUpdateStack(duint dumpAddr, duint csp, bool forceDump)
{
if(GuiIsUpdateDisabled())
return;
if(!forceDump && bFreezeStack)
dumpAddr = 0;
GuiStackDumpAt(dumpAddr, csp);
GuiUpdateArgumentWidget();
}
static void printSoftBpInfo(const BREAKPOINT & bp)
{
auto bptype = "INT3";
int titantype = bp.titantype;
if((titantype & UE_BREAKPOINT_TYPE_UD2) == UE_BREAKPOINT_TYPE_UD2)
bptype = "UD2";
else if((titantype & UE_BREAKPOINT_TYPE_LONG_INT3) == UE_BREAKPOINT_TYPE_LONG_INT3)
bptype = "LONG INT3";
auto symbolicname = SymGetSymbolicName(bp.addr);
if(*bp.name)
dprintf(QT_TRANSLATE_NOOP("DBG", "%s breakpoint \"%s\" at %s!\n"), bptype, bp.name, symbolicname.c_str());
else
dprintf(QT_TRANSLATE_NOOP("DBG", "%s breakpoint at %s!\n"), bptype, symbolicname.c_str());
}
static void printHwBpInfo(const BREAKPOINT & bp)
{
const char* bpsize = "";
switch(TITANGETSIZE(bp.titantype)) //size
{
case UE_HARDWARE_SIZE_1:
bpsize = "byte, ";
break;
case UE_HARDWARE_SIZE_2:
bpsize = "word, ";
break;
case UE_HARDWARE_SIZE_4:
bpsize = "dword, ";
break;
#ifdef _WIN64
case UE_HARDWARE_SIZE_8:
bpsize = "qword, ";
break;
#endif //_WIN64
}
char* bptype;
switch(TITANGETTYPE(bp.titantype)) //type
{
case UE_HARDWARE_EXECUTE:
bptype = _strdup(GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "execute")));
bpsize = "";
break;
case UE_HARDWARE_READWRITE:
bptype = _strdup(GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "read/write")));
break;
case UE_HARDWARE_WRITE:
bptype = _strdup(GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "write")));
break;
default:
bptype = _strdup(" ");
}
auto symbolicname = SymGetSymbolicName(bp.addr);
if(*bp.name)
dprintf(QT_TRANSLATE_NOOP("DBG", "Hardware breakpoint (%s%s) \"%s\" at %s!\n"), bpsize, bptype, bp.name, symbolicname.c_str());
else
dprintf(QT_TRANSLATE_NOOP("DBG", "Hardware breakpoint (%s%s) at %s!\n"), bpsize, bptype, symbolicname.c_str());
free(bptype);
}
static void printMemBpInfo(const BREAKPOINT & bp, const void* ExceptionAddress)
{
char* bptype;
switch(bp.titantype)
{
case UE_MEMORY_READ:
bptype = _strdup(GuiTranslateText(QT_TRANSLATE_NOOP("DBG", " (read)")));
break;
case UE_MEMORY_WRITE:
bptype = _strdup(GuiTranslateText(QT_TRANSLATE_NOOP("DBG", " (write)")));
break;
case UE_MEMORY_EXECUTE:
bptype = _strdup(GuiTranslateText(QT_TRANSLATE_NOOP("DBG", " (execute)")));
break;
case UE_MEMORY:
bptype = _strdup(GuiTranslateText(QT_TRANSLATE_NOOP("DBG", " (read/write/execute)")));
break;
default:
bptype = _strdup("");
}
auto symbolicname = SymGetSymbolicName(bp.addr);
if(*bp.name)
{
dprintf(QT_TRANSLATE_NOOP("DBG", "Memory breakpoint%s \"%s\" at %s, exception address: %s!\n"),
bptype,
bp.name,
symbolicname.c_str(),
SymGetSymbolicName(duint(ExceptionAddress)).c_str()
);
}
else
{
dprintf(QT_TRANSLATE_NOOP("DBG", "Memory breakpoint%s at %s, exception address: %s!\n"),
bptype,
symbolicname.c_str(),
SymGetSymbolicName(duint(ExceptionAddress)).c_str()
);
}
free(bptype);
}
static void printDllBpInfo(const BREAKPOINT & bp)
{
char* bptype;
switch(bp.titantype)
{
case UE_ON_LIB_LOAD:
bptype = _strdup(GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "DLL Load")));
break;
case UE_ON_LIB_UNLOAD:
bptype = _strdup(GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "DLL Unload")));
break;
case UE_ON_LIB_ALL:
bptype = _strdup(GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "DLL Load and unload")));
break;
default:
bptype = _strdup("");
}
if(*bp.name)
dprintf(QT_TRANSLATE_NOOP("DBG", "DLL Breakpoint %s (%s): Module %s\n"), bp.name, bptype, bp.mod);
else
dprintf(QT_TRANSLATE_NOOP("DBG", "DLL Breakpoint (%s): Module %s\n"), bptype, bp.mod);
free(bptype);
}
static void printExceptionBpInfo(const BREAKPOINT & bp, duint CIP)
{
if(*bp.name != 0)
dprintf(QT_TRANSLATE_NOOP("DBG", "Exception Breakpoint %s (%p) at %p!\n"), bp.name, bp.addr, CIP);
else
dprintf(QT_TRANSLATE_NOOP("DBG", "Exception Breakpoint %s (%p) at %p!\n"), ExceptionCodeToName((unsigned int)bp.addr).c_str(), bp.addr, CIP);
}
// Return value: 0:False, 1:True, -1:Error
static char getConditionValue(const char* expression)
{
auto word = *(uint16*)expression;
if(word == '0') // short circuit for condition "0\0"
return 0; //False
if(word == '1') //short circuit for condition "1\0"
return 1; //True
duint value;
if(valfromstring(expression, &value))
return value != 0 ? 1 : 0;
else
return -1; // Error
}
void cbPauseBreakpoint()
{
dputs(QT_TRANSLATE_NOOP("DBG", "paused!"));
hActiveThread = ThreadGetHandle(((DEBUG_EVENT*)GetDebugData())->dwThreadId);
auto CIP = GetContextDataEx(hActiveThread, UE_CIP);
DeleteBPX(CIP);
DebugUpdateGuiSetStateAsync(CIP, paused);
_dbg_animatestop(); // Stop animating when paused
// Trace record
dbgtraceexecute(CIP);
//lock
lock(WAITID_RUN);
// Plugin callback
PLUG_CB_PAUSEDEBUG pauseInfo = { nullptr };
plugincbcall(CB_PAUSEDEBUG, &pauseInfo);
dbgsetforeground();
dbgsetskipexceptions(false);
wait(WAITID_RUN);
}
static void handleBreakCondition(const BREAKPOINT & bp, const void* ExceptionAddress, duint CIP)
{
if(bp.singleshoot)
{
BpDelete(bp.addr, bp.type);
if(bp.type == BPHARDWARE) // Remove this singleshoot hardware breakpoint
{
if(TITANDRXVALID(bp.titantype) && !DeleteHardwareBreakPoint(TITANGETDRX(bp.titantype)))
dprintf(QT_TRANSLATE_NOOP("DBG", "Delete hardware breakpoint failed: %p (DeleteHardwareBreakPoint)\n"), bp.addr);
}
}
if(!bp.silent)
{
switch(bp.type)
{
case BPNORMAL:
printSoftBpInfo(bp);
break;
case BPHARDWARE:
printHwBpInfo(bp);
break;
case BPMEMORY:
printMemBpInfo(bp, ExceptionAddress);
break;
case BPDLL:
printDllBpInfo(bp);
break;
case BPEXCEPTION:
printExceptionBpInfo(bp, CIP);
break;
default:
break;
}
}
DebugUpdateGuiSetStateAsync(CIP, paused);
// Plugin callback
PLUG_CB_PAUSEDEBUG pauseInfo = { nullptr };
plugincbcall(CB_PAUSEDEBUG, &pauseInfo);
_dbg_animatestop(); // Stop animating when a breakpoint is hit
}
static void cbGenericBreakpoint(BP_TYPE bptype, const void* ExceptionAddress = nullptr)
{
hActiveThread = ThreadGetHandle(((DEBUG_EVENT*)GetDebugData())->dwThreadId);
auto CIP = GetContextDataEx(hActiveThread, UE_CIP);
//handle process cookie retrieval
if(bptype == BPNORMAL && cookie.HandleBreakpoint(CIP))
return;
BREAKPOINT* bpPtr = nullptr;
//NOTE: this locking is very tricky, make sure you understand it before modifying anything
EXCLUSIVE_ACQUIRE(LockBreakpoints);
duint breakpointExceptionAddress = 0;
switch(bptype)
{
case BPNORMAL:
bpPtr = BpInfoFromAddr(BPNORMAL, CIP);
breakpointExceptionAddress = CIP;
break;
case BPHARDWARE:
bpPtr = BpInfoFromAddr(BPHARDWARE, duint(ExceptionAddress));
breakpointExceptionAddress = duint(ExceptionAddress);
break;
case BPMEMORY:
bpPtr = BpInfoFromAddr(BPMEMORY, MemFindBaseAddr(duint(ExceptionAddress), nullptr, true));
breakpointExceptionAddress = duint(ExceptionAddress);
break;
case BPDLL:
bpPtr = BpInfoFromAddr(BPDLL, BpGetDLLBpAddr(reinterpret_cast<const char*>(ExceptionAddress)));
breakpointExceptionAddress = 0; //makes no sense
break;
case BPEXCEPTION:
bpPtr = BpInfoFromAddr(BPEXCEPTION, ((EXCEPTION_DEBUG_INFO*)ExceptionAddress)->ExceptionRecord.ExceptionCode);
breakpointExceptionAddress = (duint)((EXCEPTION_DEBUG_INFO*)ExceptionAddress)->ExceptionRecord.ExceptionAddress;
break;
default:
break;
}
varset("$breakpointexceptionaddress", breakpointExceptionAddress, true);
if(!(bpPtr && bpPtr->enabled)) //invalid / disabled breakpoint hit (most likely a bug)
{
if(bptype != BPDLL || !BpUpdateDllPath(reinterpret_cast<const char*>(ExceptionAddress), &bpPtr))
{
// release the breakpoint lock to prevent deadlocks during the wait
EXCLUSIVE_RELEASE();
dputs(QT_TRANSLATE_NOOP("DBG", "Breakpoint reached not in list!"));
DebugUpdateGuiSetStateAsync(GetContextDataEx(hActiveThread, UE_CIP), paused);
//lock
lock(WAITID_RUN);
// Plugin callback
PLUG_CB_PAUSEDEBUG pauseInfo = { nullptr };
plugincbcall(CB_PAUSEDEBUG, &pauseInfo);
dbgsetforeground();
dbgsetskipexceptions(false);
wait(WAITID_RUN);
return;
}
}
// increment hit count
InterlockedIncrement((volatile long*)&bpPtr->hitcount);
// copy the breakpoint structure and release the breakpoint lock to prevent deadlocks during the wait
auto bp = *bpPtr;
EXCLUSIVE_RELEASE();
if(bptype != BPDLL && bptype != BPEXCEPTION)
bp.addr += ModBaseFromName(bp.mod);
bp.active = true; //a breakpoint that has been hit is active
varset("$breakpointcounter", bp.hitcount, true); //save the breakpoint counter as a variable
//get condition values
char breakCondition;
char logCondition;
char commandCondition;
if(*bp.breakCondition)
{
breakCondition = getConditionValue(bp.breakCondition);
if(breakCondition == -1)
dputs(QT_TRANSLATE_NOOP("DBG", "Error when evaluating break condition."));
}
else
breakCondition = 1; //break if no condition is set
if(bp.fastResume && breakCondition == 0) // fast resume: ignore GUI/Script/Plugin/Other if the debugger would not break
return;
if(*bp.logCondition)
{
logCondition = getConditionValue(bp.logCondition);
if(logCondition == -1)
{
dprintf_untranslated("%s\n", stringformatinline(bp.logText).c_str()); // Always log when an error occurs, and log before the error message
dputs(QT_TRANSLATE_NOOP("DBG", "Error when evaluating log condition.")); // Then an error message is printed
breakCondition = -1; // Force breaking when an error occurs
logCondition = 0; // No need to log twice
}
}
else
logCondition = 1; //log if no condition is set
if(*bp.commandCondition)
{
commandCondition = getConditionValue(bp.commandCondition);
if(commandCondition == -1)
{
dputs(QT_TRANSLATE_NOOP("DBG", "Error when evaluating command condition."));
breakCondition = -1; // Force breaking when an error occurs
commandCondition = 0; // Don't execute any command if an error occurs
}
}
else
{
// NOTE: This behavior was changed in a breaking way, but too many people were confused
if(breakCondition != -1)
commandCondition = 1; // If no condition is set, always execute the command
else
commandCondition = 0; // Don't execute any command if an error occurs
}
lock(WAITID_RUN);
PLUG_CB_BREAKPOINT bpInfo;
BRIDGEBP bridgebp;
memset(&bridgebp, 0, sizeof(bridgebp));
bpInfo.breakpoint = &bridgebp;
BpToBridge(&bp, &bridgebp);
plugincbcall(CB_BREAKPOINT, &bpInfo);
// Trace record
dbgtraceexecute(CIP);
// Watchdog
cbCheckWatchdog(0, nullptr);
// Update breakpoint view
DebugUpdateBreakpointsViewAsync();
if(*bp.logText && logCondition == 1) //log
{
dprintf_untranslated("%s\n", stringformatinline(bp.logText).c_str());
}
if(*bp.commandText && commandCondition) //command
{
//TODO: commands like run/step etc will fuck up your shit
varset("$breakpointcondition", (breakCondition != 0) ? 1 : 0, false);
varset("$breakpointlogcondition", (logCondition != 0) ? 1 : 0, true);
duint script_breakcondition;
if(!cmddirectexec(bp.commandText))
{
breakCondition = -1; // Error executing the command (The error message is probably already printed)
}
else if(varget("$breakpointcondition", &script_breakcondition, nullptr, nullptr))
{
if(script_breakcondition != 0)
breakCondition = 1;
else
breakCondition = 0; // It is safe to clear break condition here because when an error occurs, no command can be executed
}
}
if(breakCondition != 0) //break the debugger
{
handleBreakCondition(bp, ExceptionAddress, CIP);
dbgsetforeground();
dbgsetskipexceptions(false);
}
else //resume immediately
unlock(WAITID_RUN);
//wait until the user resumes
wait(WAITID_RUN);
}
void cbUserBreakpoint()
{
lastExceptionInfo = ((DEBUG_EVENT*)GetDebugData())->u.Exception;
cbGenericBreakpoint(BPNORMAL);
}
void cbHardwareBreakpoint(const void* ExceptionAddress)
{
lastExceptionInfo = ((DEBUG_EVENT*)GetDebugData())->u.Exception;
cbGenericBreakpoint(BPHARDWARE, ExceptionAddress);
}
void cbMemoryBreakpoint(const void* ExceptionAddress)
{
lastExceptionInfo = ((DEBUG_EVENT*)GetDebugData())->u.Exception;
cbGenericBreakpoint(BPMEMORY, ExceptionAddress);
}
void cbRunToUserCodeBreakpoint(const void* ExceptionAddress)
{
hActiveThread = ThreadGetHandle(((DEBUG_EVENT*)GetDebugData())->dwThreadId);
auto CIP = GetContextDataEx(hActiveThread, UE_CIP);
dprintf(QT_TRANSLATE_NOOP("DBG", "User code reached at %s"), SymGetSymbolicName(CIP).c_str());
// lock
lock(WAITID_RUN);
// Trace record
dbgtraceexecute(CIP);
// Update GUI
DebugUpdateGuiSetStateAsync(GetContextDataEx(hActiveThread, UE_CIP), paused);
// Plugin callback
PLUG_CB_PAUSEDEBUG pauseInfo = { nullptr };
plugincbcall(CB_PAUSEDEBUG, &pauseInfo);
dbgsetforeground();
dbgsetskipexceptions(false);
wait(WAITID_RUN);
}
static BOOL CALLBACK SymRegisterCallbackProc64(HANDLE, ULONG ActionCode, ULONG64 CallbackData, ULONG64)
{
PIMAGEHLP_CBA_EVENT evt;
switch(ActionCode)
{
case CBA_EVENT:
{
evt = (PIMAGEHLP_CBA_EVENT)CallbackData;
auto strText = StringUtils::Utf16ToUtf8((const wchar_t*)evt->desc);
const char* text = strText.c_str();
if(strstr(text, "Successfully received a response from the server."))
break;
if(strstr(text, "Waiting for the server to respond to a request."))
break;
int len = (int)strlen(text);
bool suspress = false;
for(int i = 0; i < len; i++)
if(text[i] == 0x08)
{
suspress = true;
break;
}
int percent = 0;
static bool zerobar = false;
if(zerobar)
{
zerobar = false;
GuiSymbolSetProgress(0);
}
if(strstr(text, " bytes - "))
{
Memory<char*> newtext(len + 1, "SymRegisterCallbackProc64:newtext");
strcpy_s(newtext(), len + 1, text);
strstr(newtext(), " bytes - ")[8] = 0;
GuiSymbolLogAdd(newtext());
suspress = true;
}
else if(strstr(text, " copied "))
{
GuiSymbolSetProgress(100);
GuiSymbolLogAdd(" downloaded!\n");
suspress = true;
zerobar = true;
}
else if(sscanf_s(text, "%*s %d percent", &percent) == 1 || sscanf_s(text, "%d percent", &percent) == 1)
{
GuiSymbolSetProgress(percent);
suspress = true;
}
if(!suspress)
GuiSymbolLogAdd(text);
}
break;
case CBA_DEBUG_INFO:
{
GuiSymbolLogAdd((const char*)CallbackData);
}
break;
default:
{
return FALSE;
}
}
return TRUE;
}
bool cbSetModuleBreakpoints(const BREAKPOINT* bp)
{
if(!bp->enabled)
return true;
switch(bp->type)
{
case BPNORMAL:
{
unsigned short oldbytes;
if(MemRead(bp->addr, &oldbytes, sizeof(oldbytes)))
{
if(oldbytes != bp->oldbytes && !bIgnoreInconsistentBreakpoints)
{
dprintf(QT_TRANSLATE_NOOP("DBG", "Breakpoint %p has been disabled because the bytes don't match! Expected: %02X %02X, Found: %02X %02X\n"),
bp->addr,
((unsigned char*)&bp->oldbytes)[0], ((unsigned char*)&bp->oldbytes)[1],
((unsigned char*)&oldbytes)[0], ((unsigned char*)&oldbytes)[1]);
BpEnable(bp->addr, BPNORMAL, false);
}
else if(!SetBPX(bp->addr, bp->titantype, cbUserBreakpoint))
dprintf(QT_TRANSLATE_NOOP("DBG", "Could not set breakpoint %p! (SetBPX)\n"), bp->addr);
}
else
dprintf(QT_TRANSLATE_NOOP("DBG", "MemRead failed on breakpoint address %p!\n"), bp->addr);
}
break;
case BPMEMORY:
{
duint size = 0;
MemFindBaseAddr(bp->addr, &size);
if(!SetMemoryBPXEx(bp->addr, size, bp->titantype, !bp->singleshoot, cbMemoryBreakpoint))
dprintf(QT_TRANSLATE_NOOP("DBG", "Could not set memory breakpoint %p! (SetMemoryBPXEx)\n"), bp->addr);
}
break;
case BPHARDWARE:
{
DWORD drx = 0;
if(!GetUnusedHardwareBreakPointRegister(&drx))
{
dputs(QT_TRANSLATE_NOOP("DBG", "You can only set 4 hardware breakpoints"));
return false;
}
int titantype = bp->titantype;
TITANSETDRX(titantype, drx);
BpSetTitanType(bp->addr, BPHARDWARE, titantype);
if(!SetHardwareBreakPoint(bp->addr, drx, TITANGETTYPE(bp->titantype), TITANGETSIZE(bp->titantype), cbHardwareBreakpoint))
dprintf(QT_TRANSLATE_NOOP("DBG", "Could not set hardware breakpoint %p! (SetHardwareBreakPoint)\n"), bp->addr);
else
dprintf(QT_TRANSLATE_NOOP("DBG", "Set hardware breakpoint on %p!\n"), bp->addr);
}
break;
default:
break;
}
return true;
}
bool cbSetDLLBreakpoints(const BREAKPOINT* bp)
{
if(!bp->enabled)
return true;
if(bp->type != BPDLL)
return true;
dbgsetdllbreakpoint(bp->mod, bp->titantype, bp->singleshoot);
return true;
}
EXCEPTION_DEBUG_INFO & getLastExceptionInfo()
{
return lastExceptionInfo;
}
static bool cbRemoveModuleBreakpoints(const BREAKPOINT* bp)
{
if(!bp->enabled)
return true;
switch(bp->type)
{
case BPNORMAL:
if(!DeleteBPX(bp->addr))
dprintf(QT_TRANSLATE_NOOP("DBG", "Could not delete breakpoint %p! (DeleteBPX)\n"), bp->addr);
break;
case BPMEMORY:
if(!RemoveMemoryBPX(bp->addr, 0))
dprintf(QT_TRANSLATE_NOOP("DBG", "Could not delete memory breakpoint %p! (RemoveMemoryBPX)\n"), bp->addr);
break;
case BPHARDWARE:
if(TITANDRXVALID(bp->titantype) && !DeleteHardwareBreakPoint(TITANGETDRX(bp->titantype)))
dprintf(QT_TRANSLATE_NOOP("DBG", "Could not delete hardware breakpoint %p! (DeleteHardwareBreakPoint)\n"), bp->addr);
break;
default:
break;
}
return true;
}
void DebugRemoveBreakpoints()
{
BpEnumAll(cbRemoveModuleBreakpoints);
}
void DebugSetBreakpoints()
{
BpEnumAll(cbSetModuleBreakpoints);
}
void cbStep()
{
hActiveThread = ThreadGetHandle(((DEBUG_EVENT*)GetDebugData())->dwThreadId);
duint CIP = GetContextDataEx(hActiveThread, UE_CIP);
if(bAbortStepping || !stepRepeat || !--stepRepeat)
{
DebugUpdateGuiSetStateAsync(CIP, paused);
// Trace record
dbgtraceexecute(CIP);
// Plugin interaction
PLUG_CB_STEPPED stepInfo;
stepInfo.reserved = 0;
//lock
lock(WAITID_RUN);
// Plugin callback
PLUG_CB_PAUSEDEBUG pauseInfo = { nullptr };
plugincbcall(CB_PAUSEDEBUG, &pauseInfo);
dbgsetforeground();
dbgsetskipexceptions(false);
plugincbcall(CB_STEPPED, &stepInfo);
wait(WAITID_RUN);
}
else
{
dbgtraceexecute(CIP);
(bRepeatIn ? StepIntoWow64 : StepOverWrapper)(cbStep);
}
}
static void cbRtrFinalStep(bool checkRepeat)
{
if(bAbortStepping || !checkRepeat || !stepRepeat || !--stepRepeat)
{
hActiveThread = ThreadGetHandle(((DEBUG_EVENT*)GetDebugData())->dwThreadId);
duint CIP = GetContextDataEx(hActiveThread, UE_CIP);
// Trace record
dbgtraceexecute(CIP);
DebugUpdateGuiSetStateAsync(CIP, paused);
//lock
lock(WAITID_RUN);
// Plugin callback
PLUG_CB_PAUSEDEBUG pauseInfo = { nullptr };
plugincbcall(CB_PAUSEDEBUG, &pauseInfo);
dbgsetforeground();
dbgsetskipexceptions(false);
wait(WAITID_RUN);
}
else
StepOverWrapper(cbRtrStep);
}
void cbRtrStep()
{
hActiveThread = ThreadGetHandle(((DEBUG_EVENT*)GetDebugData())->dwThreadId);
unsigned char data[MAX_DISASM_BUFFER];
memset(data, 0x90, sizeof(data));
duint cip = GetContextDataEx(hActiveThread, UE_CIP);
duint csp = GetContextDataEx(hActiveThread, UE_CSP);
MemRead(cip, data, sizeof(data));
dbgtraceexecute(cip);
bool reachedReturn = false;
if(gRtrPreviousCSP <= csp) //"Run until return" should break only if RSP is bigger than or equal to current value
{
if(data[0] == 0xC3 || data[0] == 0xC2) //retn instruction
reachedReturn = true;
else if(data[0] == 0x26 || data[0] == 0x36 || data[0] == 0x2e || data[0] == 0x3e || (data[0] >= 0x64 && data[0] <= 0x67) || data[0] == 0xf2 || data[0] == 0xf3 //instruction prefixes
#ifdef _WIN64
|| (data[0] >= 0x40 && data[0] <= 0x4f)
#endif //_WIN64
)
{
Zydis cp;
if(cp.Disassemble(cip, data) && cp.IsRet())
reachedReturn = true;
}
}
if(reachedReturn || bAbortStepping)
{
// Clean up internal state
gRtrPreviousCSP = 0;
cbRtrFinalStep(true);
}
else
{
StepOverWrapper(cbRtrStep);
}
}
static void __forceinline cbTraceUniversalConditionalStep(duint cip, STEPFUNCTION stepFunction, TITANCBSTEP callback, bool forceBreakTrace)
{
PLUG_CB_TRACEEXECUTE info;
info.cip = cip;
auto breakCondition = traceState.BreakTrace();
if(forceBreakTrace && breakCondition == 0)
breakCondition = 1;
if(breakCondition == -1)
{
dputs(QT_TRANSLATE_NOOP("DBG", "Error when evaluating break condition."));
}
info.stop = (breakCondition != 0);
if(traceState.IsExtended()) //only set when needed
varset("$tracecounter", traceState.StepCount(), true);
plugincbcall(CB_TRACEEXECUTE, &info);
breakCondition = info.stop;
auto logCondition = traceState.EvaluateLog(); //true
auto cmdCondition = traceState.EvaluateCmd(breakCondition == 1 ? 1 : 0); //breakCondition
if(logCondition != 0) //log
{
traceState.LogWrite(stringformatinline(traceState.LogText()));
}
if(logCondition == -1)
{
dputs(QT_TRANSLATE_NOOP("DBG", "Error when evaluating log condition."));
logCondition = 1;
breakCondition = -1;
}
if(cmdCondition == -1)
{
dputs(QT_TRANSLATE_NOOP("DBG", "Error when evaluating command condition."));
cmdCondition = 0;
breakCondition = -1;
}
else if(cmdCondition == 1 && breakCondition != -1) //command
{
//TODO: commands like run/step etc will fuck up your shit
varset("$tracecondition", breakCondition ? 1 : 0, false);
varset("$tracelogcondition", logCondition ? 1 : 0, true);
duint script_breakcondition;
if(cmddirectexec(traceState.CmdText().c_str()))
{
if(varget("$tracecondition", &script_breakcondition, nullptr, nullptr))
breakCondition = script_breakcondition != 0;
}
else
{
breakCondition = -1; //Error when executing the command
}
}
if(breakCondition != 0 || traceState.ForceBreakTrace()) //break the debugger
{
auto steps = dbgcleartracestate();
varset("$tracecounter", steps, true);
#ifdef _WIN64
dprintf(QT_TRANSLATE_NOOP("DBG", "Trace finished after %llu steps!\n"), steps);
#else //x86
dprintf(QT_TRANSLATE_NOOP("DBG", "Trace finished after %u steps!\n"), steps);
#endif //_WIN64
cbRtrFinalStep(false); // TODO: replace with generic pause function
}
else //continue tracing
{
dbgtraceexecute(cip);
stepFunction(callback);
}
}
void cbTraceXConditionalStep(STEPFUNCTION stepFunction, TITANCBSTEP callback)
{
hActiveThread = ThreadGetHandle(((DEBUG_EVENT*)GetDebugData())->dwThreadId);
cbTraceUniversalConditionalStep(GetContextDataEx(hActiveThread, UE_CIP), stepFunction, callback, false);
}
static void cbTraceXXTraceRecordStep(STEPFUNCTION stepFunction, bool bInto, TITANCBSTEP callback)
{
hActiveThread = ThreadGetHandle(((DEBUG_EVENT*)GetDebugData())->dwThreadId);
auto cip = GetContextDataEx(hActiveThread, UE_CIP);
auto forceBreakTrace = TraceRecord.getTraceRecordType(cip) != TraceRecordManager::TraceRecordNone && (TraceRecord.getHitCount(cip) == 0) ^ bInto;
cbTraceUniversalConditionalStep(cip, stepFunction, callback, forceBreakTrace);
}
#define STEP_FUNCTION(into) (into ? StepIntoWow64 : StepOverWrapper)
void cbTraceOverConditionalStep()
{
cbTraceXConditionalStep(STEP_FUNCTION(false), cbTraceOverConditionalStep);
}
void cbTraceIntoConditionalStep()
{
cbTraceXConditionalStep(STEP_FUNCTION(true), cbTraceIntoConditionalStep);
}
void cbTraceIntoBeyondTraceRecordStep()
{
cbTraceXXTraceRecordStep(STEP_FUNCTION(true), false, cbTraceIntoBeyondTraceRecordStep);
}
void cbTraceOverBeyondTraceRecordStep()
{
cbTraceXXTraceRecordStep(STEP_FUNCTION(false), false, cbTraceOverBeyondTraceRecordStep);
}
void cbTraceIntoIntoTraceRecordStep()
{
cbTraceXXTraceRecordStep(STEP_FUNCTION(true), true, cbTraceIntoIntoTraceRecordStep);
}
void cbTraceOverIntoTraceRecordStep()
{
cbTraceXXTraceRecordStep(STEP_FUNCTION(false), true, cbTraceOverIntoTraceRecordStep);
}
static void cbCreateProcess(CREATE_PROCESS_DEBUG_INFO* CreateProcessInfo)
{
hActiveThread = CreateProcessInfo->hThread;
fdProcessInfo->hProcess = CreateProcessInfo->hProcess;
fdProcessInfo->hThread = CreateProcessInfo->hThread;
varset("$hp", (duint)fdProcessInfo->hProcess, true);
auto base = (duint)CreateProcessInfo->lpBaseOfImage;
pDebuggedBase = base; //debugged base = executable
char DebugFileName[MAX_PATH] = "";
if(!GetFileNameFromHandle(CreateProcessInfo->hFile, DebugFileName, _countof(DebugFileName)))
{
if(!GetFileNameFromProcessHandle(CreateProcessInfo->hProcess, DebugFileName, _countof(DebugFileName)))
strcpy_s(DebugFileName, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "??? (GetFileNameFromHandle failed)")));
}
dprintf(QT_TRANSLATE_NOOP("DBG", "Process Started: %p %s\n"), base, DebugFileName);
char* cmdline = nullptr;
if(dbggetcmdline(&cmdline, nullptr, fdProcessInfo->hProcess))
{
// Parse the command line from the debuggee
int argc = 0;
wchar_t** argv = CommandLineToArgvW(StringUtils::Utf8ToUtf16(cmdline).c_str(), &argc);
// Print the command line to the log
dprintf_untranslated(" %s\n", cmdline);
for(int i = 0; i < argc; i++)
dprintf_untranslated(" argv[%i]: %s\n", i, StringUtils::Utf16ToUtf8(argv[i]).c_str());
LocalFree(argv);
efree(cmdline);
}
//update memory map
MemUpdateMap();
GuiUpdateMemoryView();
//dump/disassemble somewhere
DebugUpdateGui(pDebuggedBase + pDebuggedEntry, true);
GuiDumpAt(pDebuggedBase);
ModLoad(base, 1, DebugFileName);
char modname[MAX_MODULE_SIZE] = "";
if(ModNameFromAddr(base, modname, true))
BpEnumAll(cbSetModuleBreakpoints, modname, base);
BpEnumAll(cbSetDLLBreakpoints);
BpEnumAll(cbSetModuleBreakpoints, "");
DbCheckHash(ModContentHashFromAddr(pDebuggedBase)); //Check hash mismatch
if(!bFileIsDll && !bIsAttached) //Set entry breakpoint
{
char command[deflen] = "";
if(settingboolget("Events", "TlsCallbacks"))
{
SHARED_ACQUIRE(LockModules);
auto modInfo = ModInfoFromAddr(base);
int invalidCount = 0;
for(size_t i = 0; i < modInfo->tlsCallbacks.size(); i++)
{
auto callbackVA = modInfo->tlsCallbacks.at(i);
if(MemIsValidReadPtr(callbackVA))
{
String breakpointname = StringUtils::sprintf(GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "TLS Callback %d")), i + 1);
sprintf_s(command, "bp %p,\"%s\",ss", callbackVA, breakpointname.c_str());
cmddirectexec(command);
}
else
invalidCount++;
}
if(invalidCount)
dprintf(QT_TRANSLATE_NOOP("DBG", "%d invalid TLS callback addresses...\n"), invalidCount);
}
if(settingboolget("Events", "EntryBreakpoint") && !bEntryIsInMzHeader)
{
sprintf_s(command, "bp %p,\"%s\",ss", pDebuggedBase + pDebuggedEntry, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "entry breakpoint")));
cmddirectexec(command);
}
}
else if(bFileIsDll && strstr(DebugFileName, "DLLLoader" ArchValue("32", "64"))) //DLL Loader
gDllLoader = StringUtils::Utf8ToUtf16(DebugFileName);
DebugUpdateBreakpointsViewAsync();
//update thread list
CREATE_THREAD_DEBUG_INFO threadInfo;
threadInfo.hThread = CreateProcessInfo->hThread;
threadInfo.lpStartAddress = CreateProcessInfo->lpStartAddress;
threadInfo.lpThreadLocalBase = CreateProcessInfo->lpThreadLocalBase;
ThreadCreate(&threadInfo);
hActiveThread = ThreadGetHandle(((DEBUG_EVENT*)GetDebugData())->dwThreadId);
//call plugin callback
PLUG_CB_CREATEPROCESS callbackInfo;
callbackInfo.CreateProcessInfo = CreateProcessInfo;
IMAGEHLP_MODULE64 modInfoUtf8;
memset(&modInfoUtf8, 0, sizeof(modInfoUtf8));
modInfoUtf8.SizeOfStruct = sizeof(modInfoUtf8);
modInfoUtf8.BaseOfImage = base;
modInfoUtf8.ImageSize = 0;
modInfoUtf8.TimeDateStamp = 0;
modInfoUtf8.CheckSum = 0;
modInfoUtf8.NumSyms = 1;
modInfoUtf8.SymType = SymDia;
strncpy_s(modInfoUtf8.ModuleName, DebugFileName, _TRUNCATE);
strncpy_s(modInfoUtf8.ImageName, DebugFileName, _TRUNCATE);
strncpy_s(modInfoUtf8.LoadedImageName, "", _TRUNCATE);
strncpy_s(modInfoUtf8.LoadedPdbName, "", _TRUNCATE);
modInfoUtf8.CVSig = 0;
strncpy_s(modInfoUtf8.CVData, "", _TRUNCATE);
modInfoUtf8.PdbSig = 0;
modInfoUtf8.PdbAge = 0;
modInfoUtf8.PdbUnmatched = FALSE;
modInfoUtf8.DbgUnmatched = FALSE;
modInfoUtf8.LineNumbers = TRUE;
modInfoUtf8.GlobalSymbols = 0;
modInfoUtf8.TypeInfo = TRUE;
modInfoUtf8.SourceIndexed = TRUE;
modInfoUtf8.Publics = TRUE;
callbackInfo.modInfo = &modInfoUtf8;
callbackInfo.DebugFileName = DebugFileName;
callbackInfo.fdProcessInfo = fdProcessInfo;
plugincbcall(CB_CREATEPROCESS, &callbackInfo);
}
static void cbExitProcess(EXIT_PROCESS_DEBUG_INFO* ExitProcess)
{
{
auto exitCode = ExitProcess->dwExitCode;
auto exitDescription = StringUtils::sprintf("0x%X (%d)", exitCode, exitCode);
if((exitCode & 0x80000000) != 0)
{
auto statusName = NtStatusCodeToName(exitCode);
if(!statusName.empty())
exitDescription = StringUtils::sprintf("0x%X (%s)", exitCode, statusName.c_str());
}
dprintf(QT_TRANSLATE_NOOP("DBG", "Process stopped with exit code %s\n"), exitDescription.c_str());
}
const bool breakHere = settingboolget("Events", "NtTerminateProcess");
if(breakHere)
{
// lock
DebugUpdateGuiSetStateAsync(GetContextDataEx(hActiveThread, UE_CIP), paused);
lock(WAITID_RUN);
}
// plugin callback
PLUG_CB_EXITPROCESS callbackInfo;
callbackInfo.ExitProcess = ExitProcess;
plugincbcall(CB_EXITPROCESS, &callbackInfo);
_dbg_animatestop(); // Stop animating
//history
dbgcleartracestate();
dbgClearRtuBreakpoints();
HistoryClear();
if(breakHere)
{
dbgsetforeground();
dbgsetskipexceptions(false);
wait(WAITID_RUN);
}
}
static void cbCreateThread(CREATE_THREAD_DEBUG_INFO* CreateThread)
{
ThreadCreate(CreateThread); //update thread list
DWORD dwThreadId = ((DEBUG_EVENT*)GetDebugData())->dwThreadId;
hActiveThread = ThreadGetHandle(dwThreadId);
PLUG_CB_CREATETHREAD callbackInfo;
callbackInfo.CreateThread = CreateThread;
callbackInfo.dwThreadId = dwThreadId;
plugincbcall(CB_CREATETHREAD, &callbackInfo);
auto entry = duint(CreateThread->lpStartAddress);
auto parameter = GetContextDataEx(hActiveThread, ArchValue(UE_EBX, UE_RDX));
dprintf(QT_TRANSLATE_NOOP("DBG", "Thread %s created, Entry: %s, Parameter: %s\n"),
formatpidtid(dwThreadId).c_str(),
SymGetSymbolicName(entry).c_str(),
SymGetSymbolicName(parameter).c_str()
);
if(settingboolget("Events", "ThreadEntry"))
{
String command;
command = StringUtils::sprintf("bp %p,\"%s %X\",ss", entry, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Thread Entry")), dwThreadId);
cmddirectexec(command.c_str());
}
if(settingboolget("Events", "ThreadStart"))
{
HistoryClear();
//update memory map
MemUpdateMap();
//update GUI
DebugUpdateGuiSetStateAsync(GetContextDataEx(hActiveThread, UE_CIP), paused);
//lock
lock(WAITID_RUN);
// Plugin callback
PLUG_CB_PAUSEDEBUG pauseInfo = { nullptr };
plugincbcall(CB_PAUSEDEBUG, &pauseInfo);
dbgsetforeground();
dbgsetskipexceptions(false);
wait(WAITID_RUN);
}
else
{
//insert the thread stack as a dummy page to prevent cache misses (issue #1475)
NT_TIB tib;
if(ThreadGetTib(ThreadGetLocalBase(dwThreadId), &tib))
{
MEMPAGE page;
auto limit = duint(tib.StackLimit);
auto base = duint(tib.StackBase);
sprintf_s(page.info, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Thread %s Stack")), formatpidtid(dwThreadId).c_str());
page.mbi.BaseAddress = page.mbi.AllocationBase = tib.StackLimit;
page.mbi.Protect = page.mbi.AllocationProtect = PAGE_READWRITE;
page.mbi.RegionSize = base - limit;
page.mbi.State = MEM_COMMIT;
page.mbi.Type = MEM_PRIVATE;
EXCLUSIVE_ACQUIRE(LockMemoryPages);
memoryPages.insert({ Range(limit, base - 1), page });
}
}
}
static void cbExitThread(EXIT_THREAD_DEBUG_INFO* ExitThread)
{
// Not called when the main (last) thread exits. Instead
// EXIT_PROCESS_DEBUG_EVENT is signalled.
// Switch to the main thread (because the thread is terminated).
hActiveThread = ThreadGetHandle(fdProcessInfo->dwThreadId);
if(!hActiveThread)
{
std::vector<THREADINFO> threads;
ThreadGetList(threads);
if(threads.size())
hActiveThread = threads[0].Handle;
else
dputs(QT_TRANSLATE_NOOP("DBG", "No threads left to switch to (bug?)"));
}
DWORD dwThreadId = ((DEBUG_EVENT*)GetDebugData())->dwThreadId;
PLUG_CB_EXITTHREAD callbackInfo;
callbackInfo.ExitThread = ExitThread;
callbackInfo.dwThreadId = dwThreadId;
plugincbcall(CB_EXITTHREAD, &callbackInfo);
HistoryClear();
ThreadExit(dwThreadId);
dprintf(QT_TRANSLATE_NOOP("DBG", "Thread %s exit\n"), formatpidtid(dwThreadId).c_str());
if(settingboolget("Events", "ThreadEnd"))
{
//update GUI
DebugUpdateGuiSetStateAsync(GetContextDataEx(hActiveThread, UE_CIP), paused);
//lock
lock(WAITID_RUN);
// Plugin callback
PLUG_CB_PAUSEDEBUG pauseInfo = { nullptr };
plugincbcall(CB_PAUSEDEBUG, &pauseInfo);
dbgsetforeground();
dbgsetskipexceptions(false);
wait(WAITID_RUN);
}
}
static DWORD WINAPI cbInitializationScriptThread(void*)
{
Memory<char*> script(MAX_SETTING_SIZE + 1);
if(BridgeSettingGet("Engine", "InitializeScript", script())) // Global script file
{
if(scriptLoadSync(script()))
{
if(scriptRunSync(0, true))
scriptunload();
}
else
dputs(QT_TRANSLATE_NOOP("DBG", "Error: Cannot load global initialization script."));
}
if(szDebuggeeInitializationScript[0] != 0)
{
if(scriptLoadSync(szDebuggeeInitializationScript))
{
if(scriptRunSync(0, true))
scriptunload();
}
else
dputs(QT_TRANSLATE_NOOP("DBG", "Error: Cannot load debuggee initialization script."));
}
return 0;
}
static void cbSystemBreakpoint(const void* ExceptionData) // TODO: System breakpoint event shouldn't be dropped
{
hActiveThread = ThreadGetHandle(((DEBUG_EVENT*)GetDebugData())->dwThreadId);
//Get on top of things
SetForegroundWindow(GuiGetWindowHandle());
// Update GUI (this should be the first triggered event)
duint cip = GetContextDataEx(hActiveThread, UE_CIP);
GuiDumpAt(MemFindBaseAddr(cip, 0, true)); //dump somewhere
DebugUpdateGuiSetStateAsync(cip, running);
MemInitRemoteProcessCookie(cookie.cookie);
GuiUpdateAllViews();
//log message
dputs(QT_TRANSLATE_NOOP("DBG", "System breakpoint reached!"));
dbgsetskipexceptions(false); //we are not skipping first-chance exceptions
//plugin callbacks
PLUG_CB_SYSTEMBREAKPOINT callbackInfo;
callbackInfo.reserved = 0;
plugincbcall(CB_SYSTEMBREAKPOINT, &callbackInfo);
lock(WAITID_RUN); // Allow the user to run a script file now
bool systemBreakpoint = settingboolget("Events", "SystemBreakpoint");
if(!systemBreakpoint && bEntryIsInMzHeader)
{
dputs(QT_TRANSLATE_NOOP("DBG", "It has been detected that the debuggee entry point is in the MZ header of the executable. This will cause strange behavior, so the system breakpoint has been enabled regardless of your setting. Be careful!"));
systemBreakpoint = true;
}
if(systemBreakpoint)
{
//lock
GuiSetDebugStateAsync(paused);
// Plugin callback
PLUG_CB_PAUSEDEBUG pauseInfo = { nullptr };
plugincbcall(CB_PAUSEDEBUG, &pauseInfo);
dbgsetforeground();
CloseHandle(CreateThread(NULL, 0, cbInitializationScriptThread, NULL, 0, NULL));
}
else
{
CloseHandle(CreateThread(NULL, 0, cbInitializationScriptThread, NULL, 0, NULL));
unlock(WAITID_RUN);
}
wait(WAITID_RUN);
}
static void cbLoadDll(LOAD_DLL_DEBUG_INFO* LoadDll)
{
hActiveThread = ThreadGetHandle(((DEBUG_EVENT*)GetDebugData())->dwThreadId);
void* base = LoadDll->lpBaseOfDll;
char DLLDebugFileName[MAX_PATH] = "";
if(!GetFileNameFromHandle(LoadDll->hFile, DLLDebugFileName, _countof(DLLDebugFileName)))
{
if(!GetFileNameFromModuleHandle(fdProcessInfo->hProcess, HMODULE(base), DLLDebugFileName, _countof(DLLDebugFileName)))
strcpy_s(DLLDebugFileName, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "??? (GetFileNameFromHandle failed)")));
}
ModLoad((duint)base, 1, DLLDebugFileName);
// Update memory map
MemUpdateMapAsync();
char modname[MAX_MODULE_SIZE] = "";
if(ModNameFromAddr(duint(base), modname, true))
BpEnumAll(cbSetModuleBreakpoints, modname, duint(base));
DebugUpdateBreakpointsViewAsync();
bool bAlreadySetEntry = false;
char command[MAX_PATH * 2] = "";
bool bIsDebuggingThis = false;
if(bFileIsDll && !_stricmp(DLLDebugFileName, szDebuggeePath) && !bIsAttached) //Set entry breakpoint
{
CloseHandle(DebugDLLFileMapping);
DebugDLLFileMapping = 0;
bIsDebuggingThis = true;
pDebuggedBase = (duint)base;
DbCheckHash(ModContentHashFromAddr(pDebuggedBase)); //Check hash mismatch
if(settingboolget("Events", "EntryBreakpoint"))
{
bAlreadySetEntry = true;
sprintf_s(command, "bp %p,\"%s\",ss", pDebuggedBase + pDebuggedEntry, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "entry breakpoint")));
cmddirectexec(command);
}
}
DebugUpdateBreakpointsViewAsync();
int party = ModGetParty(duint(base));
if(settingboolget("Events", "TlsCallbacks") && party != mod_system || settingboolget("Events", "TlsCallbacksSystem") && party == mod_system)
{
SHARED_ACQUIRE(LockModules);
auto modInfo = ModInfoFromAddr(duint(base));
int invalidCount = 0;
for(size_t i = 0; i < modInfo->tlsCallbacks.size(); i++)
{
auto callbackVA = modInfo->tlsCallbacks.at(i);
if(MemIsValidReadPtr(callbackVA))
{
if(bIsDebuggingThis)
sprintf_s(command, "bp %p,\"%s %u\",ss", callbackVA, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "TLS Callback")), i + 1);
else
sprintf_s(command, "bp %p,\"%s %u (%s)\",ss", callbackVA, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "TLS Callback")), i + 1, modname);
cmddirectexec(command);
}
else
invalidCount++;
}
if(invalidCount)
dprintf(QT_TRANSLATE_NOOP("DBG", "%d invalid TLS callback addresses...\n"), invalidCount);
}
auto shouldBreakOnDll = dbghandledllbreakpoint(modname, true);
auto dllEntrySetting = party == mod_system ? "DllEntrySystem" : "DllEntry";
if(!bAlreadySetEntry && (shouldBreakOnDll || settingboolget("Events", dllEntrySetting)))
{
auto entry = ModEntryFromAddr(duint(base));
if(entry)
{
sprintf_s(command, "bp %p,\"DllMain (%s)\",ss", entry, modname);
cmddirectexec(command);
}
}
auto isNtdll = ModNameFromAddr(duint(base), modname, true) && scmp(modname, "ntdll.dll");
if(isNtdll)
{
if(settingboolget("Misc", "QueryProcessCookie"))
cookie.HandleNtdllLoad(bIsAttached);
if(settingboolget("Misc", "TransparentExceptionStepping"))
exceptionDispatchAddr = DbgValFromString("ntdll:KiUserExceptionDispatcher");
//set debug flags
if(dwDebugFlags != 0)
{
SHARED_ACQUIRE(LockModules);
auto info = ModInfoFromAddr(duint(base));
if(info->symbols->isOpen())
{
dprintf(QT_TRANSLATE_NOOP("DBG", "Waiting until ntdll.dll symbols are loaded...\n"));
info->symbols->waitUntilLoaded();
SymbolInfo LdrpDebugFlags;
if(info->symbols->findSymbolByName("LdrpDebugFlags", LdrpDebugFlags, true))
{
if(MemWrite(info->base + LdrpDebugFlags.rva, &dwDebugFlags, sizeof(dwDebugFlags)))
dprintf(QT_TRANSLATE_NOOP("DBG", "Set LdrpDebugFlags to 0x%08X successfully!\n"), dwDebugFlags);
else
dprintf(QT_TRANSLATE_NOOP("DBG", "Failed to write to LdrpDebugFlags\n"));
}
else
{
dprintf(QT_TRANSLATE_NOOP("DBG", "Symbol 'LdrpDebugFlags' not found!\n"));
}
}
else
{
dprintf(QT_TRANSLATE_NOOP("DBG", "Failed to find LdrpDebugFlags (you need to load symbols for ntdll.dll)\n"));
}
}
}
dprintf(QT_TRANSLATE_NOOP("DBG", "DLL Loaded: %p %s\n"), base, DLLDebugFileName);
//plugin callback
PLUG_CB_LOADDLL callbackInfo;
callbackInfo.LoadDll = LoadDll;
IMAGEHLP_MODULE64 modInfoUtf8;
memset(&modInfoUtf8, 0, sizeof(modInfoUtf8));
modInfoUtf8.SizeOfStruct = sizeof(modInfoUtf8);
modInfoUtf8.BaseOfImage = (DWORD64)base;
modInfoUtf8.ImageSize = 0;
modInfoUtf8.TimeDateStamp = 0;
modInfoUtf8.CheckSum = 0;
modInfoUtf8.NumSyms = 0;
modInfoUtf8.SymType = SymDia;
strncpy_s(modInfoUtf8.ModuleName, DLLDebugFileName, _TRUNCATE);
strncpy_s(modInfoUtf8.ImageName, DLLDebugFileName, _TRUNCATE);
strncpy_s(modInfoUtf8.LoadedImageName, "", _TRUNCATE);
strncpy_s(modInfoUtf8.LoadedPdbName, "", _TRUNCATE);
modInfoUtf8.CVSig = 0;
strncpy_s(modInfoUtf8.CVData, "", _TRUNCATE);
modInfoUtf8.PdbSig = 0;
modInfoUtf8.PdbAge = 0;
modInfoUtf8.PdbUnmatched = FALSE;
modInfoUtf8.DbgUnmatched = FALSE;
modInfoUtf8.LineNumbers = 0;
modInfoUtf8.GlobalSymbols = TRUE;
modInfoUtf8.TypeInfo = TRUE;
modInfoUtf8.SourceIndexed = TRUE;
modInfoUtf8.Publics = TRUE;
callbackInfo.modInfo = &modInfoUtf8;
callbackInfo.modname = modname;
plugincbcall(CB_LOADDLL, &callbackInfo);
auto dllLoadSetting = party == mod_system ? "DllLoadSystem" : "DllLoad";
if(shouldBreakOnDll)
{
cbGenericBreakpoint(BPDLL, DLLDebugFileName);
}
else if(!isNtdll && settingboolget("Events", dllLoadSetting))
{
//update GUI
DebugUpdateGuiSetStateAsync(GetContextDataEx(hActiveThread, UE_CIP), paused);
//lock
lock(WAITID_RUN);
// Plugin callback
PLUG_CB_PAUSEDEBUG pauseInfo = { nullptr };
plugincbcall(CB_PAUSEDEBUG, &pauseInfo);
dbgsetforeground();
dbgsetskipexceptions(false);
wait(WAITID_RUN);
}
}
static void cbUnloadDll(UNLOAD_DLL_DEBUG_INFO* UnloadDll)
{
hActiveThread = ThreadGetHandle(((DEBUG_EVENT*)GetDebugData())->dwThreadId);
PLUG_CB_UNLOADDLL callbackInfo;
callbackInfo.UnloadDll = UnloadDll;
plugincbcall(CB_UNLOADDLL, &callbackInfo);
void* base = UnloadDll->lpBaseOfDll;
char modname[MAX_MODULE_SIZE] = "???";
if(ModNameFromAddr((duint)base, modname, true))
BpEnumAll(cbRemoveModuleBreakpoints, modname, duint(base));
int party = ModGetParty(duint(base));
DebugUpdateBreakpointsViewAsync();
dprintf(QT_TRANSLATE_NOOP("DBG", "DLL Unloaded: %p %s\n"), base, modname);
auto dllUnloadSetting = party == mod_system ? "DllUnloadSystem" : "DllUnload";
if(dbghandledllbreakpoint(modname, false))
{
cbGenericBreakpoint(BPDLL, modname);
}
else if(settingboolget("Events", dllUnloadSetting))
{
//update GUI
DebugUpdateGuiSetStateAsync(GetContextDataEx(hActiveThread, UE_CIP), paused);
//lock
lock(WAITID_RUN);
// Plugin callback
PLUG_CB_PAUSEDEBUG pauseInfo = { nullptr };
plugincbcall(CB_PAUSEDEBUG, &pauseInfo);
dbgsetforeground();
dbgsetskipexceptions(false);
wait(WAITID_RUN);
}
ModUnload((duint)base);
//update memory map
MemUpdateMapAsync();
}
static void cbOutputDebugString(OUTPUT_DEBUG_STRING_INFO* DebugString)
{
hActiveThread = ThreadGetHandle(((DEBUG_EVENT*)GetDebugData())->dwThreadId);
PLUG_CB_OUTPUTDEBUGSTRING callbackInfo;
callbackInfo.DebugString = DebugString;
plugincbcall(CB_OUTPUTDEBUGSTRING, &callbackInfo);
if(!DebugString->fUnicode) //ASCII
{
Memory<char*> DebugText(DebugString->nDebugStringLength + 1, "cbOutputDebugString:DebugText");
if(MemRead((duint)DebugString->lpDebugStringData, DebugText(), DebugString->nDebugStringLength))
{
String str = String(DebugText());
if(str != lastDebugText) //fix for every string being printed twice
{
if(str != "\n")
dprintf(QT_TRANSLATE_NOOP("DBG", "DebugString: \"%s\"\n"), StringUtils::Trim(StringUtils::Escape(str, false)).c_str());
lastDebugText = str;
}
else
lastDebugText.clear();
}
}
else
{
//TODO: implement Windows 10 unicode debug string
}
if(settingboolget("Events", "DebugStrings"))
{
//update GUI
DebugUpdateGuiSetStateAsync(GetContextDataEx(hActiveThread, UE_CIP), paused);
//lock
lock(WAITID_RUN);
// Plugin callback
PLUG_CB_PAUSEDEBUG pauseInfo = { nullptr };
plugincbcall(CB_PAUSEDEBUG, &pauseInfo);
dbgsetforeground();
dbgsetskipexceptions(false);
wait(WAITID_RUN);
}
}
static bool dbgdetachDisableAllBreakpoints(const BREAKPOINT* bp)
{
if(bp->enabled)
{
if(bp->type == BPNORMAL)
DeleteBPX(bp->addr);
else if(bp->type == BPMEMORY)
RemoveMemoryBPX(bp->addr, 0);
else if(bp->type == BPHARDWARE && TITANDRXVALID(bp->titantype))
DeleteHardwareBreakPoint(TITANGETDRX(bp->titantype));
}
return true;
}
static void cbException(EXCEPTION_DEBUG_INFO* ExceptionData)
{
hActiveThread = ThreadGetHandle(((DEBUG_EVENT*)GetDebugData())->dwThreadId);
PLUG_CB_EXCEPTION callbackInfo;
callbackInfo.Exception = ExceptionData;
unsigned int ExceptionCode = ExceptionData->ExceptionRecord.ExceptionCode;
GuiSetLastException(ExceptionCode);
lastExceptionInfo = *ExceptionData;
duint addr = (duint)ExceptionData->ExceptionRecord.ExceptionAddress;
{
BREAKPOINT bp;
if(BpGet(ExceptionCode, BPEXCEPTION, nullptr, &bp) && bp.enabled && ((bp.titantype == 1 && ExceptionData->dwFirstChance) || (bp.titantype == 2 && !ExceptionData->dwFirstChance) || bp.titantype == 3))
{
bPausedOnException = true;
cbGenericBreakpoint(BPEXCEPTION, ExceptionData);
bPausedOnException = false;
return;
}
}
if(ExceptionData->ExceptionRecord.ExceptionCode == MS_VC_EXCEPTION) //SetThreadName exception
{
THREADNAME_INFO nameInfo; //has no valid local pointers
memcpy(&nameInfo, ExceptionData->ExceptionRecord.ExceptionInformation, sizeof(THREADNAME_INFO));
if(nameInfo.dwThreadID == -1) //current thread
nameInfo.dwThreadID = ((DEBUG_EVENT*)GetDebugData())->dwThreadId;
if(nameInfo.dwType == 0x1000 && nameInfo.dwFlags == 0 && ThreadIsValid(nameInfo.dwThreadID)) //passed basic checks
{
Memory<char*> ThreadName(MAX_THREAD_NAME_SIZE, "cbException:ThreadName");
if(MemRead((duint)nameInfo.szName, ThreadName(), MAX_THREAD_NAME_SIZE - 1))
{
String ThreadNameEscaped = StringUtils::Escape(ThreadName());
dprintf(QT_TRANSLATE_NOOP("DBG", "SetThreadName exception on %p (%X, \"%s\")\n"), addr, nameInfo.dwThreadID, ThreadNameEscaped.c_str());
ThreadSetName(nameInfo.dwThreadID, ThreadNameEscaped.c_str());
if(!settingboolget("Events", "ThreadNameSet"))
return;
}
}
}
const ExceptionFilter & filter = dbggetexceptionfilter(ExceptionCode);
if(bVerboseExceptionLogging && filter.logException)
DbgCmdExecDirect("exinfo"); //show extended exception information
auto exceptionName = ExceptionCodeToName(ExceptionCode);
if(!exceptionName.size()) //if no exception was found, try the error codes (RPC_S_*)
exceptionName = ErrorCodeToName(ExceptionCode);
if(ExceptionData->dwFirstChance) //first chance exception
{
if(filter.logException)
{
if(exceptionName.size())
dprintf(QT_TRANSLATE_NOOP("DBG", "First chance exception on %p (%.8X, %s)!\n"), addr, ExceptionCode, exceptionName.c_str());
else
dprintf(QT_TRANSLATE_NOOP("DBG", "First chance exception on %p (%.8X)!\n"), addr, ExceptionCode);
}
dbgsetcontinuestatus(filter.handledBy == ExceptionHandledBy::Debuggee ? DBG_EXCEPTION_NOT_HANDLED : DBG_CONTINUE);
if((bSkipExceptions || filter.breakOn != ExceptionBreakOn::FirstChance) && (!maxSkipExceptionCount || ++skipExceptionCount < maxSkipExceptionCount))
return;
}
else //lock the exception
{
if(filter.logException)
{
if(exceptionName.size())
dprintf(QT_TRANSLATE_NOOP("DBG", "Last chance exception on %p (%.8X, %s)!\n"), addr, ExceptionCode, exceptionName.c_str());
else
dprintf(QT_TRANSLATE_NOOP("DBG", "Last chance exception on %p (%.8X)!\n"), addr, ExceptionCode);
}
// DBG_EXCEPTION_NOT_HANDLED kills the process on a last chance exception, so only pass this if the user really asked for it
dbgsetcontinuestatus(filter.breakOn == ExceptionBreakOn::DoNotBreak && filter.handledBy == ExceptionHandledBy::Debuggee ? DBG_EXCEPTION_NOT_HANDLED : DBG_CONTINUE);
}
if(filter.breakOn == ExceptionBreakOn::DoNotBreak)
return;
DebugUpdateGuiSetStateAsync(GetContextDataEx(hActiveThread, UE_CIP), paused);
//lock
lock(WAITID_RUN);
bPausedOnException = true;
// Plugin callback
PLUG_CB_PAUSEDEBUG pauseInfo = { nullptr };
plugincbcall(CB_PAUSEDEBUG, &pauseInfo);
dbgsetforeground();
dbgsetskipexceptions(false);
plugincbcall(CB_EXCEPTION, &callbackInfo);
wait(WAITID_RUN);
bPausedOnException = false;
}
static void cbDebugEvent(DEBUG_EVENT* DebugEvent)
{
nextContinueStatus = DBG_EXCEPTION_NOT_HANDLED;
hActiveThread = ThreadGetHandle(((DEBUG_EVENT*)GetDebugData())->dwThreadId);
InterlockedIncrement((volatile long*)&DbgEvents);
PLUG_CB_DEBUGEVENT debugEventInfo;
debugEventInfo.DebugEvent = DebugEvent;
plugincbcall(CB_DEBUGEVENT, &debugEventInfo);
}
static void cbAttachDebugger()
{
if(hEvent) //Signal the AeDebug event
{
SetEvent(hEvent);
CloseHandle(hEvent);
hEvent = 0;
}
if(tidToResume) //Resume a thread
{
cmddirectexec(StringUtils::sprintf("resumethread %p", tidToResume).c_str());
tidToResume = 0;
}
varset("$pid", fdProcessInfo->dwProcessId, true);
//Get on top of things
SetForegroundWindow(GuiGetWindowHandle());
// Update GUI (this should be the first triggered event)
duint cip = GetContextDataEx(hActiveThread, UE_CIP);
GuiDumpAt(MemFindBaseAddr(cip, 0, true)); //dump somewhere
DebugUpdateGuiSetStateAsync(cip, running);
MemInitRemoteProcessCookie(cookie.cookie);
GuiUpdateAllViews();
dputs(QT_TRANSLATE_NOOP("DBG", "Attached to process!"));
dbgsetskipexceptions(false); //we are not skipping first-chance exceptions
}
cmdline_qoutes_placement_t getqoutesplacement(const char* cmdline)
{
cmdline_qoutes_placement_t quotesPos;
quotesPos.firstPos = quotesPos.secondPos = 0;
auto len = strlen(cmdline);
char quoteSymb = cmdline[0];
if(quoteSymb == '"' || quoteSymb == '\'')
{
for(size_t i = 1; i < len; i++)
{
if(cmdline[i] == quoteSymb)
{
quotesPos.posEnum = i == len - 1 ? QOUTES_AT_BEGIN_AND_END : QOUTES_AROUND_EXE;
quotesPos.secondPos = i;
break;
}
}
if(!quotesPos.secondPos)
quotesPos.posEnum = NO_CLOSE_QUOTE_FOUND;
}
else
{
quotesPos.posEnum = NO_QOUTES;
//try to locate first quote
for(size_t i = 1; i < len; i++)
if(cmdline[i] == '"' || cmdline[i] == '\'')
quotesPos.secondPos = i;
}
return quotesPos;
}
BOOL ismainwindow(HWND handle)
{
// using only OWNER condition allows getting titles of hidden "main windows"
return !GetWindow(handle, GW_OWNER) && IsWindowVisible(handle);
}
BOOL CALLBACK chkWindowPidCallback(HWND hWnd, LPARAM lParam)
{
DWORD procId = (DWORD)lParam;
DWORD hwndPid = 0;
GetWindowThreadProcessId(hWnd, &hwndPid);
if(hwndPid == procId)
{
if(!mForegroundHandle) // get the foreground if no owner visible
mForegroundHandle = hWnd;
if(ismainwindow(hWnd))
{
mProcHandle = hWnd;
return FALSE;
}
}
return TRUE;
}
bool dbggetwintext(std::vector<std::string>* winTextList, const DWORD dwProcessId)
{
mProcHandle = NULL;
mForegroundHandle = NULL;
EnumWindows(chkWindowPidCallback, dwProcessId);
if(!mProcHandle && !mForegroundHandle)
return false;
wchar_t limitedbuffer[256];
limitedbuffer[255] = 0;
if(mProcHandle) // get info from the "main window" (GW_OWNER + visible)
{
if(!GetWindowTextW((HWND)mProcHandle, limitedbuffer, 256))
GetClassNameW((HWND)mProcHandle, limitedbuffer, 256); // go for the class name if none of the above
}
else if(mForegroundHandle) // get info from the foreground window
{
if(!GetWindowTextW((HWND)mForegroundHandle, limitedbuffer, 256))
GetClassNameW((HWND)mForegroundHandle, limitedbuffer, 256); // go for the class name if none of the above
}
if(limitedbuffer[255] != 0) //Window title too long. Add "..." to the end of buffer.
{
if(limitedbuffer[252] < 0xDC00 || limitedbuffer[252] > 0xDFFF) //protect the last surrogate of UTF-16 surrogate pair
limitedbuffer[252] = L'.';
limitedbuffer[253] = L'.';
limitedbuffer[254] = L'.';
limitedbuffer[255] = 0;
}
auto UTF8WindowTitle = StringUtils::Utf16ToUtf8(limitedbuffer);
winTextList->push_back(UTF8WindowTitle);
return true;
}
bool dbglistprocesses(std::vector<PROCESSENTRY32>* infoList, std::vector<std::string>* commandList, std::vector<std::string>* winTextList)
{
infoList->clear();
Handle hProcessSnap = CreateToolhelp32Snapshot(TH32CS_SNAPPROCESS, 0);
if(!hProcessSnap)
return false;
PROCESSENTRY32 pe32;
pe32.dwSize = sizeof(PROCESSENTRY32);
if(!Process32First(hProcessSnap, &pe32))
return false;
do
{
if(pe32.th32ProcessID == GetCurrentProcessId())
continue;
if(pe32.th32ProcessID == 0 || pe32.th32ProcessID == 4) // System process and Idle process have special PID.
continue;
Handle hProcess = TitanOpenProcess(PROCESS_QUERY_INFORMATION | PROCESS_VM_READ, false, pe32.th32ProcessID);
if(!hProcess)
continue;
BOOL wow64 = false, mewow64 = false;
if(!IsWow64Process(hProcess, &wow64) || !IsWow64Process(GetCurrentProcess(), &mewow64))
continue;
if((mewow64 && !wow64) || (!mewow64 && wow64))
continue;
char szExePath[MAX_PATH] = "";
if(GetFileNameFromProcessHandle(hProcess, szExePath, _countof(szExePath)))
strcpy_s(pe32.szExeFile, szExePath);
infoList->push_back(pe32);
if(!dbggetwintext(winTextList, pe32.th32ProcessID))
winTextList->push_back("");
cmdline_error_t err = {};
char* cmdline = nullptr;
if(!dbggetcmdline(&cmdline, &err, hProcess))
commandList->push_back(StringUtils::sprintf("ARG_GET_ERROR:%d:%p", err.type, err.addr));
else
{
cmdline_qoutes_placement_t posEnum = getqoutesplacement(cmdline);
char* cmdLineExe = strstr(cmdline, pe32.szExeFile);
size_t cmdLineExeSize = cmdLineExe ? strlen(pe32.szExeFile) : 0;
if(!cmdLineExe)
{
char* exeName = strrchr(pe32.szExeFile, '\\') ? strrchr(pe32.szExeFile, '\\') + 1 :
strrchr(pe32.szExeFile, '/') ? strrchr(pe32.szExeFile, '/') + 1 : pe32.szExeFile;
size_t exeNameLen = strlen(exeName);
char* peNameInCmd = strstr(cmdline, exeName);
//check for exe name is used in path to exe
for(char* exeNameInCmdTmp = peNameInCmd; exeNameInCmdTmp;)
{
exeNameInCmdTmp = strstr(exeNameInCmdTmp + exeNameLen, exeName);
if(!exeNameInCmdTmp)
break;
char* nextSlash = strchr(exeNameInCmdTmp, '\\') ? strchr(exeNameInCmdTmp, '\\') :
strchr(exeNameInCmdTmp, '/') ? strchr(exeNameInCmdTmp, '/') : NULL;
if(nextSlash && posEnum.posEnum == NO_QOUTES) //if there NO_QOUTES, then the path to PE in cmdline can't contain spaces
{
if(strchr(exeNameInCmdTmp, ' ') < nextSlash) //slash is in arguments
{
peNameInCmd = exeNameInCmdTmp;
break;
}
else
continue;
}
else if(nextSlash && posEnum.posEnum == QOUTES_AROUND_EXE)
{
if((cmdline + posEnum.secondPos) < nextSlash) //slash is in arguments
{
peNameInCmd = exeNameInCmdTmp;
break;
}
else
continue;
}
else
{
peNameInCmd = exeNameInCmdTmp;
break;
}
}
if(peNameInCmd)
cmdLineExeSize = (size_t)(((LPBYTE)peNameInCmd - (LPBYTE)cmdline) + exeNameLen);
else
{
//try to locate basic name, without extension
Memory<char*> basicName(strlen(exeName) + 1, "dbglistprocesses:basicName");
strncpy_s(basicName(), sizeof(char) * strlen(exeName) + 1, exeName, _TRUNCATE);
char* dotInName = strrchr(basicName(), '.');
if(dotInName != nullptr)
dotInName[0] = '\0';
size_t basicNameLen = strlen(basicName());
peNameInCmd = strstr(cmdline, basicName());
//check for basic name is used in path to exe
for(char* basicNameInCmdTmp = peNameInCmd; basicNameInCmdTmp;)
{
basicNameInCmdTmp = strstr(basicNameInCmdTmp + basicNameLen, basicName());
if(!basicNameInCmdTmp)
break;
char* nextSlash = strchr(basicNameInCmdTmp, '\\') ? strchr(basicNameInCmdTmp, '\\') :
strchr(basicNameInCmdTmp, '/') ? strchr(basicNameInCmdTmp, '/') : NULL;
if(nextSlash && posEnum.posEnum == NO_QOUTES) //if there NO_QOUTES, then the path to PE in cmdline can't contain spaces
{
if(strchr(basicNameInCmdTmp, ' ') < nextSlash) //slash is in arguments
{
peNameInCmd = basicNameInCmdTmp;
break;
}
else
continue;
}
else if(nextSlash && posEnum.posEnum == QOUTES_AROUND_EXE)
{
if((cmdline + posEnum.secondPos) < nextSlash) //slash is in arguments
{
peNameInCmd = basicNameInCmdTmp;
break;
}
else
continue;
}
else
{
peNameInCmd = basicNameInCmdTmp;
break;
}
}
if(peNameInCmd)
cmdLineExeSize = (size_t)(((LPBYTE)peNameInCmd - (LPBYTE)cmdline) + basicNameLen);
}
}
switch(posEnum.posEnum)
{
case NO_CLOSE_QUOTE_FOUND:
commandList->push_back(cmdline + cmdLineExeSize + 1);
break;
case NO_QOUTES:
if(!posEnum.secondPos)
commandList->push_back(cmdline + cmdLineExeSize);
else
commandList->push_back(cmdline + (cmdLineExeSize > posEnum.secondPos + 1 ? cmdLineExeSize : posEnum.secondPos + 1));
break;
case QOUTES_AROUND_EXE:
commandList->push_back(cmdline + cmdLineExeSize + 2);
break;
case QOUTES_AT_BEGIN_AND_END:
cmdline[strlen(cmdline) - 1] = '\0';
commandList->push_back(cmdline + cmdLineExeSize + 1);
break;
}
if(!commandList->empty())
commandList->back() = StringUtils::Trim(commandList->back());
efree(cmdline);
}
}
while(Process32Next(hProcessSnap, &pe32));
return true;
}
static bool getcommandlineaddr(duint* addr, cmdline_error_t* cmd_line_error, HANDLE hProcess)
{
duint pprocess_parameters;
cmd_line_error->addr = (duint)GetPEBLocation(hProcess ? hProcess : fdProcessInfo->hProcess);
if(cmd_line_error->addr == 0)
{
cmd_line_error->type = CMDL_ERR_GET_PEB;
return false;
}
if(hProcess)
{
duint NumberOfBytesRead;
if(!MemoryReadSafe(hProcess, (LPVOID)((cmd_line_error->addr) + offsetof(PEB, ProcessParameters)),
&pprocess_parameters, sizeof(duint), &NumberOfBytesRead))
{
cmd_line_error->type = CMDL_ERR_READ_PROCPARM_PTR;
return false;
}
*addr = (pprocess_parameters) + offsetof(RTL_USER_PROCESS_PARAMETERS, CommandLine);
}
else
{
//cast-trick to calculate the address of the remote peb field ProcessParameters
cmd_line_error->addr = (duint) & (((PPEB)cmd_line_error->addr)->ProcessParameters);
if(!MemRead(cmd_line_error->addr, &pprocess_parameters, sizeof(pprocess_parameters)))
{
cmd_line_error->type = CMDL_ERR_READ_PEBBASE;
return false;
}
*addr = (duint) & (((RTL_USER_PROCESS_PARAMETERS*)pprocess_parameters)->CommandLine);
}
return true;
}
static bool patchcmdline(duint getcommandline, duint new_command_line, cmdline_error_t* cmd_line_error)
{
duint command_line_stored = 0;
unsigned char data[100];
cmd_line_error->addr = getcommandline;
if(!MemRead(cmd_line_error->addr, & data, sizeof(data)))
{
cmd_line_error->type = CMDL_ERR_READ_GETCOMMANDLINEBASE;
return false;
}
#ifdef _WIN64
/*
00007FFC5B91E3C8 | 48 8B 05 19 1D 0E 00 | mov rax,qword ptr ds:[7FFC5BA000E8]
00007FFC5B91E3CF | C3 | ret |
This is a relative offset then to get the symbol: next instruction of getmodulehandle (+7 bytes) + offset to symbol
(the last 4 bytes of the instruction)
*/
if(data[0] != 0x48 || data[1] != 0x8B || data[2] != 0x05 || data[7] != 0xC3)
{
cmd_line_error->type = CMDL_ERR_CHECK_GETCOMMANDLINESTORED;
return false;
}
DWORD offset = * ((DWORD*) & data[3]);
command_line_stored = getcommandline + 7 + offset;
#else //x86
/*
750FE9CA | A1 CC DB 1A 75 | mov eax,dword ptr ds:[751ADBCC] |
750FE9CF | C3 | ret |
*/
if(data[0] != 0xA1 || data[5] != 0xC3)
{
cmd_line_error->type = CMDL_ERR_CHECK_GETCOMMANDLINESTORED;
return false;
}
command_line_stored = * ((duint*) & data[1]);
#endif
//update the pointer in the debuggee
if(!MemWrite(command_line_stored, &new_command_line, sizeof(new_command_line)))
{
cmd_line_error->addr = command_line_stored;
cmd_line_error->type = CMDL_ERR_WRITE_GETCOMMANDLINESTORED;
return false;
}
return true;
}
static bool fixgetcommandlinesbase(duint new_command_line_unicode, duint new_command_line_ascii, cmdline_error_t* cmd_line_error)
{
duint getcommandline;
if(!valfromstring("kernelBase:GetCommandLineA", &getcommandline))
{
if(!valfromstring("kernel32:GetCommandLineA", &getcommandline))
{
cmd_line_error->type = CMDL_ERR_GET_GETCOMMANDLINE;
return false;
}
}
if(!patchcmdline(getcommandline, new_command_line_ascii, cmd_line_error))
return false;
if(!valfromstring("kernelbase:GetCommandLineW", &getcommandline))
{
if(!valfromstring("kernel32:GetCommandLineW", &getcommandline))
{
cmd_line_error->type = CMDL_ERR_GET_GETCOMMANDLINE;
return false;
}
}
if(!patchcmdline(getcommandline, new_command_line_unicode, cmd_line_error))
return false;
return true;
}
static std::vector<char> Utf16ToAnsi(const wchar_t* wstr)
{
std::vector<char> buffer;
auto requiredSize = WideCharToMultiByte(CP_ACP, 0, wstr, -1, nullptr, 0, nullptr, nullptr);
if(requiredSize > 0)
{
buffer.resize(requiredSize);
WideCharToMultiByte(CP_ACP, 0, wstr, -1, &buffer[0], requiredSize, nullptr, nullptr);
}
return buffer;
}
bool dbgsetcmdline(const char* cmd_line, cmdline_error_t* cmd_line_error)
{
// Make sure cmd_line_error is a valid pointer
cmdline_error_t cmd_line_error_aux;
if(cmd_line_error == NULL)
cmd_line_error = &cmd_line_error_aux;
// Get the command line address
if(!getcommandlineaddr(&cmd_line_error->addr, cmd_line_error, fdProcessInfo->hProcess))
return false;
auto command_line_addr = cmd_line_error->addr;
// Convert the string to UTF-16
auto command_linewstr = StringUtils::Utf8ToUtf16(cmd_line);
if(command_linewstr.length() >= 32766) //32766 is maximum character count for a null-terminated UNICODE_STRING
command_linewstr.resize(32766);
// Convert the UTF-16 string to ANSI
auto command_linestr = Utf16ToAnsi(command_linewstr.c_str());
// Fill the UNICODE_STRING to be set in the debuggee
UNICODE_STRING new_command_line;
new_command_line.Length = USHORT(command_linewstr.length() * sizeof(WCHAR)); //max value: 32766 * 2 = 65532
new_command_line.MaximumLength = new_command_line.Length + sizeof(WCHAR); //max value: 65532 + 2 = 65534
new_command_line.Buffer = PWSTR(command_linewstr.c_str()); //allow cast from const because the UNICODE_STRING will not be used locally
// Allocate remote memory for both the UNICODE_STRING.Buffer and the (null terminated) ANSI buffer
duint mem = MemAllocRemote(0, new_command_line.MaximumLength + command_linestr.size());
if(!mem)
{
cmd_line_error->type = CMDL_ERR_ALLOC_UNICODEANSI_COMMANDLINE;
return false;
}
// Write the UNICODE_STRING.Buffer to the debuggee (UNICODE_STRING.Length is used because the remote memory is zeroed)
if(!MemWrite(mem, new_command_line.Buffer, new_command_line.Length))
{
cmd_line_error->addr = mem;
cmd_line_error->type = CMDL_ERR_WRITE_UNICODE_COMMANDLINE;
return false;
}
// Write the (null-terminated) ANSI buffer to the debuggee
if(!MemWrite(mem + new_command_line.MaximumLength, command_linestr.data(), command_linestr.size()))
{
cmd_line_error->addr = mem + new_command_line.MaximumLength;
cmd_line_error->type = CMDL_ERR_WRITE_ANSI_COMMANDLINE;
return false;
}
// Change the pointers to the command line
if(!fixgetcommandlinesbase(mem, mem + new_command_line.MaximumLength, cmd_line_error))
return false;
// Put the remote buffer address in the UNICODE_STRING and write it to the PEB
new_command_line.Buffer = PWSTR(mem);
if(!MemWrite(command_line_addr, &new_command_line, sizeof(new_command_line)))
{
cmd_line_error->addr = command_line_addr;
cmd_line_error->type = CMDL_ERR_WRITE_PEBUNICODE_COMMANDLINE;
return false;
}
// Copy command line
copyCommandLine(cmd_line);
return true;
}
bool dbggetcmdline(char** cmd_line, cmdline_error_t* cmd_line_error, HANDLE hProcess)
{
UNICODE_STRING CommandLine;
Memory<wchar_t*> wstr_cmd;
cmdline_error_t cmd_line_error_aux;
if(!cmd_line_error)
cmd_line_error = &cmd_line_error_aux;
if(!getcommandlineaddr(&cmd_line_error->addr, cmd_line_error, hProcess))
return false;
if(hProcess)
{
duint NumberOfBytesRead;
if(!MemoryReadSafe(hProcess, (LPVOID)cmd_line_error->addr, &CommandLine, sizeof(UNICODE_STRING), &NumberOfBytesRead))
{
cmd_line_error->type = CMDL_ERR_READ_GETCOMMANDLINEBASE;
return false;
}
wstr_cmd.realloc(CommandLine.Length + sizeof(wchar_t));
cmd_line_error->addr = (duint)CommandLine.Buffer;
if(!MemoryReadSafe(hProcess, (LPVOID)cmd_line_error->addr, wstr_cmd(), CommandLine.Length, &NumberOfBytesRead))
{
cmd_line_error->type = CMDL_ERR_GET_GETCOMMANDLINE;
return false;
}
}
else
{
if(!MemRead(cmd_line_error->addr, &CommandLine, sizeof(CommandLine)))
{
cmd_line_error->type = CMDL_ERR_READ_PROCPARM_PTR;
return false;
}
wstr_cmd.realloc(CommandLine.Length + sizeof(wchar_t));
cmd_line_error->addr = (duint)CommandLine.Buffer;
if(!MemRead(cmd_line_error->addr, wstr_cmd(), CommandLine.Length))
{
cmd_line_error->type = CMDL_ERR_READ_PROCPARM_CMDLINE;
return false;
}
}
SIZE_T wstr_cmd_size = wcslen(wstr_cmd()) + 1;
SIZE_T cmd_line_size = wstr_cmd_size * 2;
*cmd_line = (char*)emalloc(cmd_line_size, "dbggetcmdline:cmd_line");
if(cmd_line_size <= 2)
{
*cmd_line[0] = '\0';
return true;
}
//Convert TO UTF-8
if(!WideCharToMultiByte(CP_UTF8, 0, wstr_cmd(), (int)wstr_cmd_size, *cmd_line, (int)cmd_line_size, NULL, NULL))
{
efree(*cmd_line);
*cmd_line = nullptr;
cmd_line_error->type = CMDL_ERR_CONVERTUNICODE;
return false;
}
return true;
}
static DWORD WINAPI scriptThread(void* data)
{
CBPLUGINSCRIPT cbScript = (CBPLUGINSCRIPT)data;
cbScript();
return 0;
}
void dbgstartscriptthread(CBPLUGINSCRIPT cbScript)
{
CloseHandle(CreateThread(0, 0, scriptThread, (LPVOID)cbScript, 0, 0));
}
static void* InitDLLDebugW(const wchar_t* szFileName, const wchar_t* szCommandLine, const wchar_t* szCurrentFolder)
{
WString loaderFilename = StringUtils::sprintf(L"\\DLLLoader" ArchValue(L"32", L"64") L"_%04X.exe", GetTickCount() & 0xFFFF);
WString debuggeeLoaderPath = szFileName;
{
auto backslashIdx = debuggeeLoaderPath.rfind('\\');
if(backslashIdx != WString::npos)
debuggeeLoaderPath.resize(backslashIdx);
}
debuggeeLoaderPath += loaderFilename;
WString loaderPath = StringUtils::Utf8ToUtf16(szDllLoaderPath);
if(!CopyFileW(loaderPath.c_str(), debuggeeLoaderPath.c_str(), FALSE))
{
debuggeeLoaderPath = StringUtils::Utf8ToUtf16(szUserDir);
debuggeeLoaderPath += loaderFilename;
if(!CopyFileW(loaderPath.c_str(), debuggeeLoaderPath.c_str(), FALSE))
{
dprintf(QT_TRANSLATE_NOOP("DBG", "Error debugging DLL (failed to copy loader)\n"));
return nullptr;
}
}
PPROCESS_INFORMATION ReturnValue = (PPROCESS_INFORMATION)InitDebugW(debuggeeLoaderPath.c_str(), szCommandLine, szCurrentFolder);
WString mappingName = StringUtils::sprintf(L"Local\\szLibraryName%X", ReturnValue->dwProcessId);
const auto mappingSize = 512;
DebugDLLFileMapping = CreateFileMappingW(INVALID_HANDLE_VALUE, 0, PAGE_READWRITE, 0, mappingSize * sizeof(wchar_t), mappingName.c_str());
if(DebugDLLFileMapping)
{
wchar_t* szLibraryPathMapping = (wchar_t*)MapViewOfFile(DebugDLLFileMapping, FILE_MAP_ALL_ACCESS, 0, 0, mappingSize * sizeof(wchar_t));
if(szLibraryPathMapping)
{
wcscpy_s(szLibraryPathMapping, mappingSize, szFileName);
UnmapViewOfFile(szLibraryPathMapping);
}
}
return ReturnValue;
}
static void debugLoopFunction(INIT_STRUCT* init)
{
//initialize variables
bIsAttached = init->attach;
dbgsetskipexceptions(false);
bFreezeStack = false;
//prepare attach/createprocess
if(init->attach)
{
gInitExe = StringUtils::Utf8ToUtf16(szDebuggeePath);
static PROCESS_INFORMATION pi_attached;
memset(&pi_attached, 0, sizeof(pi_attached));
fdProcessInfo = &pi_attached;
}
else
{
gInitExe = StringUtils::Utf8ToUtf16(init->exe);
strncpy_s(szDebuggeePath, init->exe.c_str(), _TRUNCATE);
}
pDebuggedEntry = GetPE32DataW(gInitExe.c_str(), 0, UE_OEP);
bEntryIsInMzHeader = pDebuggedEntry == 0 || pDebuggedEntry == 1;
bFileIsDll = IsFileDLLW(StringUtils::Utf8ToUtf16(szDebuggeePath).c_str(), 0);
if(bFileIsDll && !FileExists(szDllLoaderPath))
{
dprintf(QT_TRANSLATE_NOOP("DBG", "Error debugging DLL (loaddll.exe not found)\n"));
return;
}
DbSetPath(nullptr, szDebuggeePath);
if(!init->attach)
{
// Load command line if it exists in DB
DbLoad(DbLoadSaveType::CommandLine);
if(!isCmdLineEmpty())
{
char* commandLineArguments = NULL;
commandLineArguments = getCommandLineArgs();
if(commandLineArguments && *commandLineArguments)
init->commandline = commandLineArguments;
}
gInitCmd = StringUtils::Utf8ToUtf16(init->commandline);
gInitDir = StringUtils::Utf8ToUtf16(init->currentfolder);
//start the process
if(bFileIsDll)
fdProcessInfo = (PROCESS_INFORMATION*)InitDLLDebugW(gInitExe.c_str(), gInitCmd.c_str(), gInitDir.c_str());
else
fdProcessInfo = (PROCESS_INFORMATION*)InitDebugW(gInitExe.c_str(), gInitCmd.c_str(), gInitDir.c_str());
if(!fdProcessInfo)
{
auto lastError = GetLastError();
auto isElevated = BridgeIsProcessElevated();
String error = stringformatinline(StringUtils::sprintf("{winerror@%x}", lastError));
if(lastError == ERROR_ELEVATION_REQUIRED && !isElevated)
{
auto msg = StringUtils::Utf8ToUtf16(GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "The executable you are trying to debug requires elevation. Restart as admin?")));
auto title = StringUtils::Utf8ToUtf16(GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Elevation")));
auto answer = MessageBoxW(GuiGetWindowHandle(), msg.c_str(), title.c_str(), MB_ICONQUESTION | MB_YESNO);
wchar_t wszProgramPath[MAX_PATH] = L"";
if(answer == IDYES && dbgrestartadmin())
{
fdProcessInfo = &g_pi;
GuiCloseApplication();
return;
}
}
else if(isElevated)
{
//This is most likely an application with uiAccess="true"
//https://github.com/x64dbg/x64dbg/issues/1501
//https://blogs.techsmith.com/inside-techsmith/devcorner-debug-uiaccess
error += ", uiAccess=\"true\"";
}
fdProcessInfo = &g_pi;
dprintf(QT_TRANSLATE_NOOP("DBG", "Error starting process (CreateProcess, %s)!\n"), error.c_str());
return;
}
//check for WOW64
BOOL wow64 = false, mewow64 = false;
if(!IsWow64Process(fdProcessInfo->hProcess, &wow64) || !IsWow64Process(GetCurrentProcess(), &mewow64))
{
dputs(QT_TRANSLATE_NOOP("DBG", "IsWow64Process failed!"));
StopDebug();
return;
}
if((mewow64 && !wow64) || (!mewow64 && wow64))
{
#ifdef _WIN64
dputs(QT_TRANSLATE_NOOP("DBG", "Use x32dbg to debug this process!"));
#else
dputs(QT_TRANSLATE_NOOP("DBG", "Use x64dbg to debug this process!"));
#endif // _WIN64
return;
}
//set script variables
varset("$pid", fdProcessInfo->dwProcessId, true);
if(!OpenProcessToken(fdProcessInfo->hProcess, TOKEN_ALL_ACCESS, &hProcessToken))
hProcessToken = 0;
}
else //attach
{
gInitCmd.clear();
gInitDir.clear();
}
// signal that fdProcessInfo has been set
SetEvent(init->event);
init->event = nullptr;
//set custom handlers
SetCustomHandler(UE_CH_CREATEPROCESS, (TITANCBCH)cbCreateProcess);
SetCustomHandler(UE_CH_EXITPROCESS, (TITANCBCH)cbExitProcess);
SetCustomHandler(UE_CH_CREATETHREAD, (TITANCBCH)cbCreateThread);
SetCustomHandler(UE_CH_EXITTHREAD, (TITANCBCH)cbExitThread);
SetCustomHandler(UE_CH_SYSTEMBREAKPOINT, (TITANCBCH)cbSystemBreakpoint);
SetCustomHandler(UE_CH_LOADDLL, (TITANCBCH)cbLoadDll);
SetCustomHandler(UE_CH_UNLOADDLL, (TITANCBCH)cbUnloadDll);
SetCustomHandler(UE_CH_OUTPUTDEBUGSTRING, (TITANCBCH)cbOutputDebugString);
SetCustomHandler(UE_CH_UNHANDLEDEXCEPTION, (TITANCBCH)cbException);
SetCustomHandler(UE_CH_DEBUGEVENT, (TITANCBCH)cbDebugEvent);
//inform GUI we started without problems
GuiSetDebugState(initialized);
GuiFocusView(GUI_DISASSEMBLY);
GuiAddRecentFile(szDebuggeePath);
//set GUI title
strcpy_s(szBaseFileName, szDebuggeePath);
int len = (int)strlen(szBaseFileName);
while(szBaseFileName[len] != '\\' && len)
len--;
if(len)
strcpy_s(szBaseFileName, szBaseFileName + len + 1);
GuiUpdateWindowTitle(szBaseFileName);
//call plugin callback
PLUG_CB_INITDEBUG initInfo;
initInfo.szFileName = szDebuggeePath;
plugincbcall(CB_INITDEBUG, &initInfo);
//call plugin callback (attach)
if(init->attach)
{
PLUG_CB_ATTACH attachInfo;
attachInfo.dwProcessId = init->pid;
plugincbcall(CB_ATTACH, &attachInfo);
}
// Init program database
DbLoad(DbLoadSaveType::DebugData);
//run debug loop (returns when process debugging is stopped)
if(init->attach)
{
if(!AttachDebugger(init->pid, true, fdProcessInfo, cbAttachDebugger))
{
auto status = NtCurrentTeb()->LastStatusValue;
auto error = stringformatinline(StringUtils::sprintf("{ntstatus@%X}", status));
if(status == STATUS_PORT_ALREADY_SET)
{
error = GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Process is already being debugged!"));
}
dprintf(QT_TRANSLATE_NOOP("DBG", "Attach to process failed: %s\n"), error.c_str());
}
}
else
{
//close the process and thread handles we got back from CreateProcess, to prevent duplicating the ones we will receive in cbCreateProcess
CloseHandle(fdProcessInfo->hProcess);
CloseHandle(fdProcessInfo->hThread);
fdProcessInfo->hProcess = fdProcessInfo->hThread = nullptr;
DebugLoop();
}
//fixes data loss when attach failed (https://github.com/x64dbg/x64dbg/issues/1899)
DbClose();
//call plugin callback
PLUG_CB_STOPDEBUG stopInfo;
stopInfo.reserved = 0;
plugincbcall(CB_STOPDEBUG, &stopInfo);
//message the user/do final stuff
RemoveAllBreakPoints(UE_OPTION_REMOVEALL); //remove all breakpoints
{
EXCLUSIVE_ACQUIRE(LockDllBreakpoints);
dllBreakpoints.clear(); //RemoveAllBreakPoints doesn't remove librarian breakpoints
}
//cleanup
dbgcleartracestate();
dbgClearRtuBreakpoints();
ModClear();
ThreadClear();
WatchClear();
TraceRecord.clear();
TraceRecord.enableTraceRecording(false, nullptr); // Stop trace recording
GuiSetDebugState(stopped);
GuiUpdateAllViews();
dputs(QT_TRANSLATE_NOOP("DBG", "Debugging stopped!"));
fdProcessInfo->hProcess = fdProcessInfo->hThread = nullptr;
varset("$hp", (duint)0, true);
varset("$pid", (duint)0, true);
if(hProcessToken)
{
CloseHandle(hProcessToken);
hProcessToken = 0;
}
if(DebugDLLFileMapping)
{
CloseHandle(DebugDLLFileMapping);
DebugDLLFileMapping = 0;
}
pDebuggedEntry = 0;
pDebuggedBase = 0;
hActiveThread = nullptr;
if(!gDllLoader.empty()) //Delete the DLL loader (#1496)
{
DeleteFileW(gDllLoader.c_str());
gDllLoader.clear();
}
}
void dbgsetdebuggeeinitscript(const char* fileName)
{
if(fileName)
strcpy_s(szDebuggeeInitializationScript, fileName);
else
szDebuggeeInitializationScript[0] = 0;
}
const char* dbggetdebuggeeinitscript()
{
return szDebuggeeInitializationScript;
}
void dbgsetforeground()
{
if(!bNoForegroundWindow)
SetForegroundWindow(GuiGetWindowHandle());
}
void dbgcreatedebugthread(INIT_STRUCT* init)
{
if(settingboolget("Misc", "CheckForAntiCheatDrivers"))
{
auto loadedDrivers = LoadedAntiCheatDrivers();
if(!loadedDrivers.empty())
{
auto translatedFormat = GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Drivers known to interfere with x64dbg's operation have been detected.\n\nList of drivers:\n%s\n\nDo you want to continue debugging?"));
auto message = StringUtils::sprintf(translatedFormat, loadedDrivers.c_str());
auto continueDebugging = GuiScriptMsgyn(message.c_str());
if(!continueDebugging)
return;
}
}
auto event = init->event = CreateEventW(nullptr, false, false, nullptr);
hDebugLoopThread = CreateThread(nullptr, 0, [](LPVOID lpParameter) -> DWORD
{
auto init = (INIT_STRUCT*)lpParameter;
debugLoopFunction(init);
// Set the event in case debugLoopFunction returned early to prevent a deadlock
if(init->event)
{
SetEvent(init->event);
init->event = nullptr;
}
return 0;
}, init, 0, nullptr);
WaitForSingleObject(event, INFINITE);
CloseHandle(event);
}
String formatpidtid(DWORD pidtid)
{
if(bPidTidInHex)
return StringUtils::sprintf("%X", pidtid);
else
return StringUtils::sprintf("%u", pidtid);
}
void dbgsetcontinuestatus(DWORD status)
{
nextContinueStatus = status;
SetNextDbgContinueStatus(status);
}
DWORD dbggetcontinuestatus()
{
return nextContinueStatus;
}
bool dbgrestartadmin()
{
wchar_t wszProgramPath[MAX_PATH] = L"";
if(GetModuleFileNameW(GetModuleHandleW(nullptr), wszProgramPath, _countof(wszProgramPath)))
{
std::wstring file = wszProgramPath;
auto last = wcsrchr(wszProgramPath, L'\\');
if(last)
*last = L'\0';
//TODO: possibly escape characters in gInitCmd
std::wstring params = L"\"" + gInitExe + L"\" \"" + gInitCmd + L"\" \"" + gInitDir + L"\"";
auto result = ShellExecuteW(NULL, L"runas", file.c_str(), params.c_str(), wszProgramPath, SW_SHOWDEFAULT);
return int(result) > 32 && GetLastError() == ERROR_SUCCESS;
}
return false;
}
void StepIntoWow64(TITANCBSTEP callback)
{
#ifndef _WIN64
//NOTE: this workaround has the potential of detecting x64dbg while tracing, disable it if that happens
if(!bNoWow64SingleStepWorkaround)
{
unsigned char data[7];
auto cip = GetContextDataEx(hActiveThread, UE_CIP);
if(MemRead(cip, data, sizeof(data)) && data[0] == 0xEA && data[5] == 0x33 && data[6] == 0x00) //ljmp 33,XXXXXXXX
{
auto csp = GetContextDataEx(hActiveThread, UE_CSP);
duint ret;
if(MemRead(csp, &ret, sizeof(ret)))
{
SetBPX(ret, UE_SINGLESHOOT, callback);
return;
}
}
}
#endif //_WIN64
if(bPausedOnException && dbggetcontinuestatus() == DBG_EXCEPTION_NOT_HANDLED && exceptionDispatchAddr && !IsBPXEnabled(exceptionDispatchAddr))
{
SetBPX(exceptionDispatchAddr, UE_SINGLESHOOT, callback);
}
else
{
StepInto(callback);
}
}
void StepOverWrapper(TITANCBSTEP callback)
{
if(bPausedOnException && dbggetcontinuestatus() == DBG_EXCEPTION_NOT_HANDLED && exceptionDispatchAddr && !IsBPXEnabled(exceptionDispatchAddr))
{
SetBPX(exceptionDispatchAddr, UE_SINGLESHOOT, callback);
}
else
{
StepOver(callback);
}
}
template<MODULEPARTY StopParty>
static void cbStepIntoParty()
{
if(bAbortStepping || ModGetParty(GetContextDataEx(hActiveThread, UE_CIP)) == StopParty)
{
bAbortStepping = false;
gStepIntoPartyCallback();
}
else
{
StepIntoWow64(cbStepIntoParty<StopParty>);
}
}
void StepIntoUser(TITANCBSTEP callback)
{
gStepIntoPartyCallback = callback;
StepIntoWow64(cbStepIntoParty<mod_user>);
}
void StepIntoSystem(TITANCBSTEP callback)
{
gStepIntoPartyCallback = callback;
StepIntoWow64(cbStepIntoParty<mod_system>);
}
bool dbgisdepenabled()
{
auto depEnabled = false;
#ifndef _WIN64
typedef BOOL(WINAPI * GETPROCESSDEPPOLICY)(
_In_ HANDLE /*hProcess*/,
_Out_ LPDWORD /*lpFlags*/,
_Out_ PBOOL /*lpPermanent*/
);
static auto GPDP = GETPROCESSDEPPOLICY(GetProcAddress(GetModuleHandleW(L"kernel32.dll"), "GetProcessDEPPolicy"));
if(GPDP)
{
//If you use fdProcessInfo->hProcess GetProcessDEPPolicy will put garbage in bPermanent.
auto hProcess = TitanOpenProcess(PROCESS_QUERY_INFORMATION, false, fdProcessInfo->dwProcessId);
DWORD lpFlags;
BOOL bPermanent;
if(GPDP(hProcess, &lpFlags, &bPermanent))
depEnabled = lpFlags != 0;
CloseHandle(hProcess);
}
#else
depEnabled = true;
#endif //_WIN64
return depEnabled;
} |
C/C++ | x64dbg-development/src/dbg/debugger.h | #ifndef _DEBUGGER_H
#define _DEBUGGER_H
#include "_global.h"
#include "TitanEngine/TitanEngine.h"
#include "command.h"
#include "breakpoint.h"
#include "_plugins.h"
#include "commandline.h"
#include <tlhelp32.h>
#include <psapi.h>
//enums
enum class ExceptionBreakOn
{
FirstChance,
SecondChance,
DoNotBreak
};
enum class ExceptionHandledBy
{
Debugger,
Debuggee
};
//structures
struct INIT_STRUCT
{
HANDLE event = nullptr;
std::string exe;
std::string commandline;
std::string currentfolder;
DWORD pid = 0;
bool attach = false;
};
struct ExceptionRange
{
unsigned int start;
unsigned int end;
};
struct ExceptionFilter
{
ExceptionRange range;
ExceptionBreakOn breakOn;
bool logException;
ExceptionHandledBy handledBy;
};
#pragma pack(push,8)
typedef struct _THREADNAME_INFO
{
DWORD dwType; // Must be 0x1000.
LPCSTR szName; // Pointer to name (in user addr space).
DWORD dwThreadID; // Thread ID (-1=caller thread).
DWORD dwFlags; // Reserved for future use, must be zero.
} THREADNAME_INFO;
#pragma pack(pop)
//functions
void dbginit();
void dbgstop();
duint dbgdebuggedbase();
duint dbggettimewastedcounter();
bool dbgisrunning();
bool dbgisdll();
void dbgsetattachevent(HANDLE handle);
void dbgsetresumetid(duint tid);
void DebugUpdateGui(duint disasm_addr, bool stack);
void DebugUpdateGuiAsync(duint disasm_addr, bool stack);
void DebugUpdateTitleAsync(duint disasm_addr, bool analyzeThreadSwitch);
void DebugUpdateGuiSetStateAsync(duint disasm_addr, DBGSTATE state);
void DebugUpdateBreakpointsViewAsync();
void DebugUpdateStack(duint dumpAddr, duint csp, bool forceDump = false);
void DebugRemoveBreakpoints();
void DebugSetBreakpoints();
void GuiSetDebugStateAsync(DBGSTATE state);
void dbgsetskipexceptions(bool skip);
void dbgsetsteprepeat(bool steppingIn, duint repeat);
void dbgsetfreezestack(bool freeze);
void dbgclearexceptionfilters();
void dbgaddexceptionfilter(ExceptionFilter filter);
const ExceptionFilter & dbggetexceptionfilter(unsigned int exception);
bool dbgcmdnew(const char* name, CBCOMMAND cbCommand, bool debugonly);
bool dbgcmddel(const char* name);
bool dbglistprocesses(std::vector<PROCESSENTRY32>* infoList, std::vector<std::string>* commandList, std::vector<std::string>* winTextList);
bool dbgsetcmdline(const char* cmd_line, cmdline_error_t* cmd_line_error);
bool dbggetcmdline(char** cmd_line, cmdline_error_t* cmd_line_error, HANDLE hProcess);
cmdline_qoutes_placement_t getqoutesplacement(const char* cmdline);
void dbgstartscriptthread(CBPLUGINSCRIPT cbScript);
duint dbggetdbgevents();
bool dbgsettracecondition(const String & expression, duint maxCount);
bool dbgsettracelog(const String & expression, const String & text);
bool dbgsettracecmd(const String & expression, const String & text);
bool dbgtraceactive();
void dbgforcebreaktrace();
bool dbgstepactive();
void dbgforcebreakstep();
bool dbgsettracelogfile(const char* fileName);
void dbgsetdebuggeeinitscript(const char* fileName);
const char* dbggetdebuggeeinitscript();
void dbgsetforeground();
bool dbggetwintext(std::vector<std::string>* winTextList, const DWORD dwProcessId);
void dbgtracebrowserneedsupdate();
bool dbgsetdllbreakpoint(const char* mod, DWORD type, bool singleshoot);
bool dbgdeletedllbreakpoint(const char* mod, DWORD type);
void dbgsetdebugflags(DWORD flags);
void dbgcreatedebugthread(INIT_STRUCT* init);
String formatpidtid(DWORD pidtid);
void dbgsetcontinuestatus(DWORD status);
DWORD dbggetcontinuestatus();
void cbStep();
void cbRtrStep();
void cbPauseBreakpoint();
void cbMemoryBreakpoint(const void* ExceptionAddress);
void cbHardwareBreakpoint(const void* ExceptionAddress);
void cbUserBreakpoint();
void cbDebugLoadLibBPX();
void cbTraceOverConditionalStep();
void cbTraceIntoConditionalStep();
void cbTraceIntoBeyondTraceRecordStep();
void cbTraceOverBeyondTraceRecordStep();
void cbTraceIntoIntoTraceRecordStep();
void cbTraceOverIntoTraceRecordStep();
typedef void(*STEPFUNCTION)(TITANCBSTEP);
void cbTraceXConditionalStep(STEPFUNCTION stepFunction, TITANCBSTEP callback);
void cbRunToUserCodeBreakpoint(const void* ExceptionAddress);
bool cbSetModuleBreakpoints(const BREAKPOINT* bp);
EXCEPTION_DEBUG_INFO & getLastExceptionInfo();
bool dbgrestartadmin();
void StepIntoWow64(TITANCBSTEP callback);
void StepOverWrapper(TITANCBSTEP callback);
void StepIntoUser(TITANCBSTEP callback);
void StepIntoSystem(TITANCBSTEP callback);
bool dbgisdepenabled();
BOOL CALLBACK chkWindowPidCallback(HWND hWnd, LPARAM lParam);
BOOL ismainwindow(HWND handle);
//variables
extern PROCESS_INFORMATION* fdProcessInfo;
extern HANDLE hActiveThread;
extern HANDLE hProcessToken;
extern char szProgramDir[MAX_PATH];
extern char szUserDir[MAX_PATH];
extern char szDebuggeePath[MAX_PATH];
extern char szDllLoaderPath[MAX_PATH];
extern char szSymbolCachePath[MAX_PATH];
extern bool bUndecorateSymbolNames;
extern bool bEnableSourceDebugging;
extern bool bSkipInt3Stepping;
extern bool bIgnoreInconsistentBreakpoints;
extern bool bNoForegroundWindow;
extern bool bVerboseExceptionLogging;
extern bool bNoWow64SingleStepWorkaround;
extern bool bForceLoadSymbols;
extern bool bNewStringAlgorithm;
extern bool bPidTidInHex;
extern bool bWindowLongPath;
extern duint maxSkipExceptionCount;
extern HANDLE mProcHandle;
extern HANDLE mForegroundHandle;
extern duint gRtrPreviousCSP;
extern HANDLE hDebugLoopThread;
#endif // _DEBUGGER_H |
C/C++ | x64dbg-development/src/dbg/debugger_cookie.h | #pragma once
struct CookieQuery
{
duint addr = 0;
duint ret = 0;
duint cookieptr = 0;
ULONG cookie = 0;
bool removeAddrBp = false;
bool removeRetBp = false;
void HandleNtdllLoad(bool isAttached)
{
*this = CookieQuery();
ULONG returnSize = 0;
NTSTATUS status = NtQueryInformationProcess(fdProcessInfo->hProcess, ProcessCookie, &cookie, sizeof(cookie), &returnSize);
if(!NT_SUCCESS(status))
{
if(!isAttached && valfromstring("ntdll.dll:NtQueryInformationProcess", &addr))
{
if(!BpGet(addr, BPNORMAL, nullptr, nullptr))
{
if(SetBPX(addr, UE_BREAKPOINT, cbUserBreakpoint))
removeAddrBp = true;
else
addr = 0;
}
}
}
}
bool HandleBreakpoint(duint cip)
{
if(addr && addr == cip && Exprfunc::argget(1) == ProcessCookie)
{
if(valfromstring("[csp]", &ret))
{
cookieptr = Exprfunc::argget(2);
if(!BpGet(ret, BPNORMAL, nullptr, nullptr))
{
if(SetBPX(ret, UE_BREAKPOINT, cbUserBreakpoint))
removeRetBp = true;
else
ret = 0;
}
else
removeRetBp = false;
}
if(removeAddrBp)
{
DeleteBPX(addr);
BpDelete(addr, BPNORMAL);
return true;
}
}
else if(ret && ret == cip)
{
if(!MemRead(cookieptr, &cookie, sizeof(cookie)))
cookie = 0, cookieptr = 0;
if(removeRetBp)
{
DeleteBPX(ret);
BpDelete(ret, BPNORMAL);
return true;
}
}
return false;
}
}; |
C/C++ | x64dbg-development/src/dbg/debugger_tracing.h | #pragma once
/**
\brief Conditional tracing structures
*/
struct TraceCondition
{
ExpressionParser condition;
duint steps;
duint maxSteps;
explicit TraceCondition(const String & expression, duint maxCount)
: condition(expression), steps(0), maxSteps(maxCount) {}
// Return value: 0:Continue, 1:Break, -1:Error (Break)
char BreakTrace()
{
steps++;
if(steps >= maxSteps)
return 1;
duint value;
if(condition.Calculate(value, valuesignedcalc(), true))
return value != 0;
else
return -1;
}
};
struct TextCondition
{
ExpressionParser condition;
String text;
explicit TextCondition(const String & expression, const String & text)
: condition(expression), text(text) {}
char Evaluate() const
{
duint value;
if(condition.Calculate(value, valuesignedcalc(), true))
return !!value;
return -1;
}
};
struct TraceState
{
bool InitTraceCondition(const String & expression, duint maxSteps)
{
delete traceCondition;
traceCondition = new TraceCondition(expression, maxSteps);
bool temp = traceCondition->condition.IsValidExpression();
if(!temp)
{
delete traceCondition;
traceCondition = nullptr;
}
return temp;
}
bool InitLogFile()
{
if(logFile.empty())
return true;
auto hFile = CreateFileW(logFile.c_str(), GENERIC_WRITE, FILE_SHARE_READ, nullptr, CREATE_ALWAYS, FILE_ATTRIBUTE_NORMAL, nullptr);
if(hFile == INVALID_HANDLE_VALUE)
return false;
logWriter = new BufferedWriter(hFile);
duint setting;
if(BridgeSettingGetUint("Misc", "Utf16LogRedirect", &setting))
writeUtf16 = !!setting;
return true;
}
void LogWrite(String text)
{
if(logWriter)
{
if(writeUtf16)
{
auto textUtf16 = StringUtils::Utf8ToUtf16(text);
logWriter->Write(textUtf16.c_str(), textUtf16.size() * 2);
logWriter->Write(L"\r\n", 4);
}
else
{
logWriter->Write(text.c_str(), text.size());
logWriter->Write("\n", 1);
}
}
else
dprintf_untranslated("%s\n", text.c_str());
}
bool IsActive() const
{
return traceCondition != nullptr;
}
bool IsExtended() const
{
return logCondition || cmdCondition;
}
char BreakTrace() const
{
return traceCondition ? traceCondition->BreakTrace() : 1;
}
duint StepCount() const
{
return traceCondition ? traceCondition->steps : 0;
}
bool InitLogCondition(const String & expression, const String & text)
{
delete logCondition;
logCondition = nullptr;
if(text.empty())
return true;
if(expression.empty())
logCondition = new TextCondition("1", text);
else
logCondition = new TextCondition(expression, text);
return logCondition->condition.IsValidExpression();
}
char EvaluateLog() const
{
return logCondition ? logCondition->Evaluate() : 0;
}
const String & LogText() const
{
return logCondition ? logCondition->text : emptyString;
}
bool InitCmdCondition(const String & expression, const String & text)
{
delete cmdCondition;
cmdCondition = nullptr;
if(text.empty())
return true;
if(expression.empty())
{
cmdCondition = new TextCondition(traceCondition->condition.GetExpression(), text);
}
else
cmdCondition = new TextCondition(expression, text);
return cmdCondition->condition.IsValidExpression();
}
char EvaluateCmd(char defaultValue) const
{
return cmdCondition ? cmdCondition->Evaluate() : defaultValue;
}
const String & CmdText() const
{
return cmdCondition ? cmdCondition->text : emptyString;
}
void SetLogFile(const char* fileName)
{
logFile = StringUtils::Utf8ToUtf16(fileName);
}
bool ForceBreakTrace()
{
return forceBreakTrace;
}
void SetForceBreakTrace()
{
forceBreakTrace = true;
}
void Clear()
{
delete traceCondition;
traceCondition = nullptr;
delete logCondition;
logCondition = nullptr;
delete cmdCondition;
cmdCondition = nullptr;
logFile.clear();
delete logWriter;
logWriter = nullptr;
writeUtf16 = false;
forceBreakTrace = false;
}
private:
TraceCondition* traceCondition = nullptr;
TextCondition* logCondition = nullptr;
TextCondition* cmdCondition = nullptr;
String emptyString;
WString logFile;
BufferedWriter* logWriter = nullptr;
bool writeUtf16 = false;
bool forceBreakTrace = false;
}; |
C++ | x64dbg-development/src/dbg/disasm_fast.cpp | /**
@file disasm_fast.cpp
@brief Implements the disasm fast class.
*/
#include "disasm_fast.h"
#include "memory.h"
#include "datainst_helper.h"
void fillbasicinfo(Zydis* cp, BASIC_INSTRUCTION_INFO* basicinfo, bool instrText)
{
//zero basicinfo
memset(basicinfo, 0, sizeof(BASIC_INSTRUCTION_INFO));
//copy instruction text
if(instrText)
strcpy_s(basicinfo->instruction, cp->InstructionText().c_str());
//instruction size
basicinfo->size = cp->Size();
//branch/call info
if(cp->IsCall())
{
basicinfo->branch = true;
basicinfo->call = true;
}
else if(cp->IsJump() || cp->IsLoop())
{
basicinfo->branch = true;
}
//handle operands
for(int i = 0; i < cp->OpCount(); i++)
{
const auto & op = (*cp)[i];
switch(op.type)
{
case ZYDIS_OPERAND_TYPE_IMMEDIATE:
{
if(basicinfo->branch)
{
basicinfo->type |= TYPE_ADDR;
basicinfo->addr = duint(op.imm.value.u);
basicinfo->value.value = duint(op.imm.value.u);
}
else
{
basicinfo->type |= TYPE_VALUE;
basicinfo->value.size = VALUE_SIZE(op.size / 8);
basicinfo->value.value = duint(op.imm.value.u);
}
}
break;
case ZYDIS_OPERAND_TYPE_MEMORY:
{
const auto & mem = op.mem;
if(instrText)
{
auto opText = cp->OperandText(i);
StringUtils::ReplaceAll(opText, "0x", "");
strcpy_s(basicinfo->memory.mnemonic, opText.c_str());
}
basicinfo->memory.size = MEMORY_SIZE(op.size / 8);
if(op.mem.base == ZYDIS_REGISTER_RIP) //rip-relative
{
basicinfo->memory.value = ULONG_PTR(cp->Address() + op.mem.disp.value + basicinfo->size);
basicinfo->type |= TYPE_MEMORY;
}
else if(mem.disp.value)
{
basicinfo->type |= TYPE_MEMORY;
basicinfo->memory.value = ULONG_PTR(mem.disp.value);
}
}
break;
default:
break;
}
}
}
bool disasmfast(const unsigned char* data, duint addr, BASIC_INSTRUCTION_INFO* basicinfo)
{
if(!data || !basicinfo)
return false;
Zydis cp;
cp.Disassemble(addr, data, MAX_DISASM_BUFFER);
if(trydisasmfast(data, addr, basicinfo, cp.Success() ? cp.Size() : 1))
return true;
if(!cp.Success())
{
strcpy_s(basicinfo->instruction, "???");
basicinfo->size = 1;
return false;
}
fillbasicinfo(&cp, basicinfo);
return true;
}
void disasm(Zydis & zydis, duint addr)
{
unsigned char data[MAX_DISASM_BUFFER];
if(MemRead(addr, data, sizeof(data)))
zydis.Disassemble(addr, data);
}
bool disasmfast(duint addr, BASIC_INSTRUCTION_INFO* basicinfo, bool cache)
{
// unsigned int because of data encoding (likely could be a bit smaller though, this is 4*16=64 bytes)
unsigned int data[16];
if(!MemRead(addr, data, sizeof(data), nullptr, cache))
return false;
return disasmfast((unsigned char*)data, addr, basicinfo);
} |
C/C++ | x64dbg-development/src/dbg/disasm_fast.h | #ifndef _DISASM_FAST_H
#define _DISASM_FAST_H
#include "_global.h"
#include <zydis_wrapper.h>
void fillbasicinfo(Zydis* disasm, BASIC_INSTRUCTION_INFO* basicinfo, bool instrText = true);
bool disasmfast(duint addr, BASIC_INSTRUCTION_INFO* basicinfo, bool cache = false);
bool disasmfast(const unsigned char* data, duint addr, BASIC_INSTRUCTION_INFO* basicinfo);
void disasm(Zydis & zydis, duint addr);
#endif //_DISASM_FAST_H |
C++ | x64dbg-development/src/dbg/disasm_helper.cpp | /**
@file disasm_helper.cpp
@brief Implements the disasm helper class.
*/
#include "disasm_helper.h"
#include "thread.h"
#include "console.h"
#include "memory.h"
#include "debugger.h"
#include "value.h"
#include "encodemap.h"
#include <zydis_wrapper.h>
#include "datainst_helper.h"
duint disasmback(unsigned char* data, duint base, duint size, duint ip, int n)
{
int i;
duint abuf[131], addr, back, cmdsize;
memset(abuf, 0, sizeof(abuf));
unsigned char* pdata;
// Reset Disasm Structure
Zydis cp;
// Check if the pointer is not null
if(data == NULL)
return 0;
// Round the number of back instructions to 127
if(n < 0)
n = 0;
else if(n > 127)
n = 127;
// Check if the instruction pointer ip is not outside the memory range
if(ip >= size)
ip = size - 1;
// Obvious answer
if(n == 0)
return ip;
if(ip < (duint)n)
return ip;
back = MAX_DISASM_BUFFER * (n + 3); // Instruction length limited to 16
if(ip < back)
back = ip;
addr = ip - back;
pdata = data + addr;
for(i = 0; addr < ip; i++)
{
abuf[i % 128] = addr;
if(!cp.Disassemble(0, pdata, (int)size))
cmdsize = 1;
else
cmdsize = cp.Size();
pdata += cmdsize;
addr += cmdsize;
back -= cmdsize;
size -= cmdsize;
}
if(i < n)
return abuf[0];
else
return abuf[(i - n + 128) % 128];
}
duint disasmnext(unsigned char* data, duint base, duint size, duint ip, int n)
{
int i;
duint cmdsize;
unsigned char* pdata;
// Reset Disasm Structure
Zydis cp;
if(data == NULL)
return 0;
if(ip >= size)
ip = size - 1;
if(n <= 0)
return ip;
pdata = data + ip;
size -= ip;
for(i = 0; i < n && size > 0; i++)
{
if(!cp.Disassemble(0, pdata, (int)size))
cmdsize = 1;
else
cmdsize = cp.Size();
pdata += cmdsize;
ip += cmdsize;
size -= cmdsize;
}
return ip;
}
static void HandleZydisOperand(Zydis & cp, int opindex, DISASM_ARG* arg, bool getregs)
{
auto value = cp.ResolveOpValue(opindex, [&cp, getregs](ZydisRegister reg)
{
auto regName = getregs ? cp.RegName(reg) : nullptr;
return regName ? getregister(nullptr, regName) : 0; //TODO: temporary needs enums + caching
});
const auto & op = cp[opindex];
arg->segment = SEG_DEFAULT;
auto opText = cp.OperandText(opindex);
StringUtils::ReplaceAll(opText, "0x", "");
strcpy_s(arg->mnemonic, opText.c_str());
switch(op.type)
{
case ZYDIS_OPERAND_TYPE_REGISTER:
{
arg->type = arg_normal;
arg->value = value;
}
break;
case ZYDIS_OPERAND_TYPE_IMMEDIATE:
{
arg->type = arg_normal;
arg->constant = arg->value = value;
}
break;
case ZYDIS_OPERAND_TYPE_MEMORY:
{
arg->type = arg_memory;
const auto & mem = op.mem;
if(mem.base == ZYDIS_REGISTER_RIP) //rip-relative
arg->constant = cp.Address() + duint(mem.disp.value) + cp.Size();
else
arg->constant = duint(mem.disp.value);
if(mem.segment == ArchValue(ZYDIS_REGISTER_FS, ZYDIS_REGISTER_GS))
{
arg->segment = ArchValue(SEG_FS, SEG_GS);
value += ThreadGetLocalBase(ThreadGetId(hActiveThread));
}
else
{
switch(mem.segment)
{
case ZYDIS_REGISTER_CS:
arg->segment = SEG_CS;
break;
case ZYDIS_REGISTER_DS:
arg->segment = SEG_DS;
break;
case ZYDIS_REGISTER_ES:
arg->segment = SEG_ES;
break;
case ZYDIS_REGISTER_FS:
arg->segment = SEG_FS;
break;
case ZYDIS_REGISTER_GS:
arg->segment = SEG_GS;
break;
case ZYDIS_REGISTER_SS:
arg->segment = SEG_SS;
break;
}
}
arg->value = value;
if(DbgMemIsValidReadPtr(value))
{
switch(op.size)
{
case 8:
MemRead(value, (unsigned char*)&arg->memvalue, 1);
break;
case 16:
MemRead(value, (unsigned char*)&arg->memvalue, 2);
break;
case 32:
MemRead(value, (unsigned char*)&arg->memvalue, 4);
break;
#ifdef _WIN64
case 48:
MemRead(value, (unsigned char*)&arg->memvalue, 6);
break;
case 64:
MemRead(value, (unsigned char*)&arg->memvalue, 8);
break;
default:
//TODO: not supported
break;
#endif //_WIN64
}
}
}
break;
case ZYDIS_OPERAND_TYPE_POINTER:
arg->type = arg_normal;
arg->value = op.ptr.offset;
break;
default:
break;
}
}
void disasmget(Zydis & cp, unsigned char* buffer, duint addr, DISASM_INSTR* instr, bool getregs)
{
memset(instr, 0, sizeof(DISASM_INSTR));
cp.Disassemble(addr, buffer, MAX_DISASM_BUFFER);
if(trydisasm(buffer, addr, instr, cp.Success() ? cp.Size() : 1))
return;
if(!cp.Success())
{
strcpy_s(instr->instruction, "???");
instr->instr_size = 1;
instr->type = instr_normal;
instr->argcount = 0;
return;
}
auto cpInstr = cp.GetInstr();
strncpy_s(instr->instruction, cp.InstructionText().c_str(), _TRUNCATE);
instr->instr_size = cpInstr->length;
if(cp.IsBranchType(Zydis::BTJmp | Zydis::BTLoop | Zydis::BTRet | Zydis::BTCall))
instr->type = instr_branch;
else if(strstr(instr->instruction, "sp") || strstr(instr->instruction, "bp"))
instr->type = instr_stack;
else
instr->type = instr_normal;
instr->argcount = cp.OpCount() <= 3 ? cp.OpCount() : 3;
for(int i = 0; i < instr->argcount; i++)
HandleZydisOperand(cp, i, &instr->arg[i], getregs);
}
void disasmget(Zydis & cp, duint addr, DISASM_INSTR* instr, bool getregs)
{
if(!DbgIsDebugging())
{
if(instr)
instr->argcount = 0;
return;
}
unsigned char buffer[MAX_DISASM_BUFFER] = "";
if(MemRead(addr, buffer, sizeof(buffer)))
disasmget(cp, buffer, addr, instr, getregs);
else
memset(instr, 0, sizeof(DISASM_INSTR)); // Buffer overflow
}
void disasmget(unsigned char* buffer, duint addr, DISASM_INSTR* instr, bool getregs)
{
Zydis cp;
disasmget(cp, buffer, addr, instr, getregs);
}
void disasmget(duint addr, DISASM_INSTR* instr, bool getregs)
{
if(!DbgIsDebugging())
{
if(instr)
instr->argcount = 0;
return;
}
unsigned char buffer[MAX_DISASM_BUFFER] = "";
if(MemRead(addr, buffer, sizeof(buffer)))
disasmget(buffer, addr, instr, getregs);
else
memset(instr, 0, sizeof(DISASM_INSTR)); // Buffer overflow
}
bool isunicodestring(const WString & data)
{
if(data.size() < 2)
return false;
for(auto & i : data)
{
// No specials
if(i >= 0xFFF0)
return false;
// No ANSI control chars
if(i < 0x80 && !isprint(i) && !isspace(i))
return false;
// No C1 control chars
if(i >= 0x80 && i < 0xA0)
return false;
// No 0xFF char
if(i == 0xFF)
return false;
// No surrogates and private use chars
if(i >= 0xD800 && i <= 0xF8FF)
return false;
}
return true;
}
// These functions are exported so that plugins can use this to detect a string, or replace with a plugin-developed string dection algorithm through hooking
extern "C" __declspec(dllexport) bool isasciistring(const unsigned char* data, int maxlen)
{
if(bNewStringAlgorithm)
{
int len = 0;
char* safebuffer = new char[maxlen];
if(!safebuffer)
return false;
for(const char* p = (const char*)data; *p && len < maxlen - 1; len++, p++)
{
safebuffer[p - (const char*)data] = *p;
}
if(len < 2)
{
delete[] safebuffer;
return false;
}
safebuffer[len] = 0; // Mark the end of string
if(len >= maxlen - 1 && (maxlen % 2) == 0 && (safebuffer[maxlen - 2] & 0x80))
safebuffer[maxlen - 2] = 0; // Keep DBCS strings from being chopped in the middle
String data2;
WString wdata2;
// Convert to and from Unicode
wdata2 = StringUtils::LocalCpToUtf16(safebuffer);
delete[] safebuffer;
if(wdata2.size() < 2)
return false;
data2 = StringUtils::Utf16ToLocalCp(wdata2);
if(data2.size() < 2)
return false;
// Is the data exactly representable in both ANSI and Unicode?
if(memcmp(data2.c_str(), data, data2.size()) != 0)
return false;
// Filter out bad chars
if(!isunicodestring(wdata2))
return false;
return true;
}
else
{
int len = 0;
for(const char* p = (const char*)data; *p; len++, p++)
{
if(len >= maxlen)
break;
}
if(len < 2)
return false;
for(int i = 0; i < len; i++)
if(!isprint(data[i]) && !isspace(data[i]))
return false;
return true;
}
}
extern "C" __declspec(dllexport) bool isunicodestring(const unsigned char* data, int maxlen)
{
int len = 0;
wchar_t* safebuffer = new wchar_t[maxlen];
if(!safebuffer)
return false;
for(const wchar_t* p = (const wchar_t*)data; *p && len < maxlen - 1; len += sizeof(wchar_t), p++)
{
safebuffer[p - (const wchar_t*)data] = *p;
}
if(len < 2 * sizeof(wchar_t))
{
delete[] safebuffer;
return false;
}
safebuffer[len / sizeof(wchar_t)] = 0; // Mark the end of string
String data2;
WString wdata2;
// Convert to and from ANSI
data2 = StringUtils::Utf16ToLocalCp(safebuffer);
delete[] safebuffer;
if(data2.size() < 2)
return false;
wdata2 = StringUtils::LocalCpToUtf16(data2);
if(wdata2.size() < 2)
return false;
// Is the data exactly representable in both ANSI and Unicode?
if(memcmp(wdata2.c_str(), data, wdata2.size() * sizeof(wchar_t)) != 0)
return false;
// Filter out bad chars
if(!isunicodestring(wdata2))
return false;
return true;
}
bool disasmispossiblestring(duint addr, STRING_TYPE* type)
{
unsigned char data[60];
memset(data, 0, sizeof(data));
duint bytesRead = 0;
if(!MemReadUnsafe(addr, data, sizeof(data), &bytesRead) && bytesRead < 2)
return false;
if(isasciistring(data, sizeof(data)))
{
if(type)
*type = str_ascii;
return true;
}
if(isunicodestring(data, sizeof(data) / 2))
{
if(type)
*type = str_unicode;
return true;
}
if(type)
*type = str_none;
return false;
}
bool disasmgetstringat(duint addr, STRING_TYPE* type, char* ascii, char* unicode, int maxlen)
{
if(type)
*type = str_none;
if(!MemIsValidReadPtrUnsafe(addr, true) || !disasmispossiblestring(addr))
return false;
Memory<unsigned char*> data((maxlen + 1) * 2, "disasmgetstringat:data");
MemReadUnsafe(addr, data(), (maxlen + 1) * 2); //TODO: use safe version?
// Save a few pointer casts
auto asciiData = (char*)data();
// First check if this was an ASCII only string
if(isasciistring(data(), maxlen))
{
if(type)
*type = str_ascii;
// Convert ANSI string to UTF-8
std::string asciiData2 = StringUtils::LocalCpToUtf8((const char*)data());
memcpy(asciiData, asciiData2.c_str(), min((size_t(maxlen) + 1) * 2, asciiData2.size() + 1));
// Escape the string
String escaped = StringUtils::Escape(asciiData);
// Copy data back to outgoing parameter
strncpy_s(ascii, min(int(escaped.length()) + 1, maxlen), escaped.c_str(), _TRUNCATE);
return true;
}
if(isunicodestring(data(), maxlen))
{
if(type)
*type = str_unicode;
// Convert UTF-16 string to UTF-8
std::string asciiData2 = StringUtils::Utf16ToUtf8((const wchar_t*)data());
memcpy(asciiData, asciiData2.c_str(), min((size_t(maxlen) + 1) * 2, asciiData2.size() + 1));
// Escape the string
String escaped = StringUtils::Escape(asciiData);
// Copy data back to outgoing parameter
strncpy_s(unicode, min(int(escaped.length()) + 1, maxlen), escaped.c_str(), _TRUNCATE);
return true;
}
return false;
}
bool disasmgetstringatwrapper(duint addr, char* dest, bool cache)
{
if(!MemIsValidReadPtrUnsafe(addr, cache))
return false;
auto readValidPtr = [cache](duint addr) -> duint
{
duint addrPtr;
if(MemReadUnsafe(addr, &addrPtr, sizeof(addrPtr)) && MemIsValidReadPtrUnsafe(addrPtr, cache))
return addrPtr;
return 0;
};
*dest = '\0';
char string[MAX_STRING_SIZE];
duint addrPtr = readValidPtr(addr);
STRING_TYPE strtype;
auto possibleUnicode = disasmispossiblestring(addr, &strtype) && strtype == str_unicode;
if(addrPtr && !possibleUnicode)
{
if(disasmgetstringat(addrPtr, &strtype, string, string, MAX_STRING_SIZE - 5))
{
if(int(strlen(string)) <= (strtype == str_ascii ? 3 : 2) && readValidPtr(addrPtr))
return false;
if(strtype == str_ascii)
sprintf_s(dest, MAX_STRING_SIZE, "&\"%s\"", string);
else //unicode
sprintf_s(dest, MAX_STRING_SIZE, "&L\"%s\"", string);
return true;
}
}
if(disasmgetstringat(addr, &strtype, string, string, MAX_STRING_SIZE - 4))
{
if(strtype == str_ascii)
sprintf_s(dest, MAX_STRING_SIZE, "\"%s\"", string);
else //unicode
sprintf_s(dest, MAX_STRING_SIZE, "L\"%s\"", string);
return true;
}
return false;
}
int disasmgetsize(duint addr, unsigned char* data)
{
Zydis cp;
if(!cp.Disassemble(addr, data, MAX_DISASM_BUFFER))
return 1;
return int(EncodeMapGetSize(addr, cp.Size()));
}
int disasmgetsize(duint addr)
{
char data[MAX_DISASM_BUFFER];
if(!MemRead(addr, data, sizeof(data)))
return 1;
return disasmgetsize(addr, (unsigned char*)data);
} |
C/C++ | x64dbg-development/src/dbg/disasm_helper.h | #ifndef _DISASM_HELPER_H
#define _DISASM_HELPER_H
#include "_global.h"
#include "zydis_wrapper.h"
//functions
duint disasmback(unsigned char* data, duint base, duint size, duint ip, int n);
duint disasmnext(unsigned char* data, duint base, duint size, duint ip, int n);
void disasmget(Zydis & cp, unsigned char* buffer, duint addr, DISASM_INSTR* instr, bool getregs = true);
void disasmget(Zydis & cp, duint addr, DISASM_INSTR* instr, bool getregs = true);
void disasmget(unsigned char* buffer, duint addr, DISASM_INSTR* instr, bool getregs = true);
void disasmget(duint addr, DISASM_INSTR* instr, bool getregs = true);
bool disasmispossiblestring(duint addr, STRING_TYPE* type = nullptr);
bool disasmgetstringat(duint addr, STRING_TYPE* type, char* ascii, char* unicode, int maxlen);
bool disasmgetstringatwrapper(duint addr, char* text, bool cache = true);
int disasmgetsize(duint addr, unsigned char* data);
int disasmgetsize(duint addr);
#endif // _DISASM_HELPER_H |
C/C++ | x64dbg-development/src/dbg/dynamicmem.h | #pragma once
template<typename T>
class Memory
{
public:
//
// This class guarantees that the returned allocated memory
// will always be zeroed
//
explicit Memory(const char* Reason = "Memory:???")
{
m_Ptr = nullptr;
m_Size = 0;
#ifdef ENABLE_MEM_TRACE
m_Reason = Reason;
#endif //ENABLE_MEM_TRACE
}
explicit Memory(size_t Size, const char* Reason = "Memory:???")
{
m_Ptr = reinterpret_cast<T>(emalloc(Size, Reason));
m_Size = Size;
#ifdef ENABLE_MEM_TRACE
m_Reason = Reason;
#endif //ENABLE_MEM_TRACE
memset(m_Ptr, 0, Size);
}
~Memory()
{
if(m_Ptr)
#ifdef ENABLE_MEM_TRACE
efree(m_Ptr, m_Reason);
#else
efree(m_Ptr);
#endif //ENABLE_MEM_TRACE
}
T realloc(size_t Size, const char* Reason = "Memory:???")
{
m_Ptr = reinterpret_cast<T>(erealloc(m_Ptr, Size, Reason));
m_Size = Size;
#ifdef ENABLE_MEM_TRACE
m_Reason = Reason;
#endif //ENABLE_MEM_TRACE
return (T)memset(m_Ptr, 0, m_Size);
}
size_t size() const
{
return m_Size;
}
T operator()()
{
return m_Ptr;
}
private:
T m_Ptr;
size_t m_Size;
#ifdef ENABLE_MEM_TRACE
const char* m_Reason;
#endif //ENABLE_MEM_TRACE
}; |
C++ | x64dbg-development/src/dbg/encodemap.cpp | #include "encodemap.h"
#include <unordered_map>
#include "addrinfo.h"
#include <zydis_wrapper.h>
struct ENCODEMAP : AddrInfo
{
duint size;
byte* data;
};
std::unordered_map<duint, duint> referenceCount;
void IncreaseReferenceCount(void* buffer, bool lock = true)
{
if(lock)
{
EXCLUSIVE_ACQUIRE(LockEncodeMaps);
}
auto iter = referenceCount.find((duint)buffer);
if(iter == referenceCount.end())
referenceCount[(duint)buffer] = 1;
else
referenceCount[(duint)buffer]++;
}
duint DecreaseReferenceCount(void* buffer, bool lock = true)
{
if(lock)
{
EXCLUSIVE_ACQUIRE(LockEncodeMaps);
}
auto iter = referenceCount.find((duint)buffer);
if(iter == referenceCount.end())
return -1;
if(iter->second == 1)
{
referenceCount.erase(iter->first);
return 0;
}
else
referenceCount[iter->first]--;
return iter->second;
}
struct EncodeMapSerializer : AddrInfoSerializer<ENCODEMAP>
{
bool Save(const ENCODEMAP & value) override
{
AddrInfoSerializer::Save(value);
setString("data", StringUtils::ToCompressedHex(value.data, value.size));
return true;
}
bool Load(ENCODEMAP & value) override
{
if(!AddrInfoSerializer::Load(value))
return false;
auto dataJson = get("data");
if(!dataJson)
return false;
std::vector<unsigned char> data;
if(!StringUtils::FromCompressedHex(json_string_value(dataJson), data))
return false;
value.size = data.size();
value.data = (byte*)VirtualAlloc(NULL, value.size, MEM_COMMIT | MEM_RESERVE, PAGE_READWRITE);
if(!value.data)
return false;
memcpy(value.data, data.data(), data.size());
IncreaseReferenceCount(value.data, false);
return true;
}
};
struct EncodeMap : AddrInfoHashMap<LockEncodeMaps, ENCODEMAP, EncodeMapSerializer>
{
const char* jsonKey() const override
{
return "encodemaps";
}
};
static EncodeMap encmaps;
static bool EncodeMapValidateModuleInfo(duint key, ENCODEMAP & map, duint segsize)
{
// The map size might be smaller if it was loaded from cache for another
// version of the module. Adjust the size in this case.
if(map.size < segsize)
{
byte* newData = (byte*)VirtualAlloc(NULL, segsize, MEM_COMMIT | MEM_RESERVE, PAGE_READWRITE);
if(newData == NULL) return false;
memcpy(newData, map.data, map.size);
DecreaseReferenceCount(map.data);
VirtualFree(map.data, 0, MEM_RELEASE);
encmaps.Delete(key);
map.size = segsize;
map.data = newData;
IncreaseReferenceCount(map.data);
encmaps.Add(map);
}
return true;
}
static bool EncodeMapGet(duint addr, ENCODEMAP & map, duint* baseOut = nullptr)
{
duint base, segsize;
base = MemFindBaseAddr(addr, &segsize);
if(!base)
return false;
if(baseOut)
*baseOut = base;
duint key = EncodeMap::VaKey(base);
if(!encmaps.Get(key, map))
return false;
if(!EncodeMapValidateModuleInfo(key, map, segsize))
return false;
return true;
}
static bool EncodeMapGetorCreate(duint addr, ENCODEMAP & map, duint* baseOut = nullptr, bool* created = nullptr)
{
duint base, segsize;
base = MemFindBaseAddr(addr, &segsize);
if(!base)
return false;
if(baseOut)
*baseOut = base;
duint key = EncodeMap::VaKey(base);
if(!encmaps.Get(key, map))
{
if(created)
*created = true;
map.size = segsize;
map.data = (byte*)VirtualAlloc(NULL, segsize, MEM_COMMIT | MEM_RESERVE, PAGE_READWRITE);
if(map.data == NULL) return false;
IncreaseReferenceCount(map.data);
encmaps.PrepareValue(map, base, false);
encmaps.Add(map);
}
else
{
if(created)
*created = false;
if(!EncodeMapValidateModuleInfo(key, map, segsize))
return false;
}
return true;
}
void* EncodeMapGetBuffer(duint addr, duint* size, bool create)
{
ENCODEMAP map;
duint base;
if(create ? EncodeMapGetorCreate(addr, map, &base) : EncodeMapGet(addr, map, &base))
{
auto offset = addr - base;
if(offset < map.size)
{
IncreaseReferenceCount(map.data);
if(size)
*size = map.size;
return map.data;
}
}
if(size)
*size = 0;
return nullptr;
}
void EncodeMapReleaseBuffer(void* buffer, bool lock)
{
if(DecreaseReferenceCount(buffer, lock) == 0)
VirtualFree(buffer, 0, MEM_RELEASE);
}
void EncodeMapReleaseBuffer(void* buffer)
{
EncodeMapReleaseBuffer(buffer, true);
}
duint GetEncodeTypeSize(ENCODETYPE type)
{
switch(type)
{
case enc_byte:
return 1;
case enc_word:
return 2;
case enc_dword:
return 4;
case enc_fword:
return 6;
case enc_qword:
return 8;
case enc_tbyte:
return 10;
case enc_oword:
return 16;
case enc_mmword:
return 8;
case enc_xmmword:
return 16;
case enc_ymmword:
return 32;
case enc_real4:
return 4;
case enc_real8:
return 8;
case enc_real10:
return 10;
case enc_ascii:
return 1;
case enc_unicode:
return 2;
default:
return 1;
}
}
static bool IsCodeType(ENCODETYPE type)
{
return type == enc_code || type == enc_junk;
}
ENCODETYPE EncodeMapGetType(duint addr, duint codesize)
{
ENCODEMAP map;
duint base;
if(EncodeMapGet(addr, map, &base))
{
auto offset = addr - base;
if(offset >= map.size)
return enc_unknown;
return ENCODETYPE(map.data[offset]);
}
return enc_unknown;
}
duint EncodeMapGetSize(duint addr, duint codesize)
{
ENCODEMAP map;
duint base;
if(EncodeMapGet(addr, map, &base))
{
auto offset = addr - base;
if(offset >= map.size)
return 1;
auto type = ENCODETYPE(map.data[offset]);
auto datasize = GetEncodeTypeSize(type);
if(!IsCodeType(type))
return datasize;
}
return codesize;
}
bool EncodeMapSetType(duint addr, duint size, ENCODETYPE type, bool* created)
{
ENCODEMAP map;
duint base;
if(!EncodeMapGetorCreate(addr, map, &base, created))
return false;
auto offset = addr - base;
size = min(map.size - offset, size);
auto datasize = GetEncodeTypeSize(type);
if(datasize == 1 && !IsCodeType(type))
{
memset(map.data + offset, (byte)type, size);
}
else
{
memset(map.data + offset, (byte)enc_middle, size);
if(IsCodeType(type) && size > 1)
{
Zydis cp;
Memory<unsigned char*> buffer(size);
if(!MemRead(addr, buffer(), size))
return false;
duint buffersize = size, bufferoffset = 0, cmdsize;
for(auto i = offset; i < offset + size;)
{
map.data[i] = (byte)type;
cp.Disassemble(base + i, buffer() + bufferoffset, int(buffersize - bufferoffset));
cmdsize = cp.Success() ? cp.Size() : 1;
i += cmdsize;
bufferoffset += cmdsize;
buffersize -= cmdsize;
}
}
else
{
for(auto i = offset; i < offset + size; i += datasize)
map.data[i] = (byte)type;
}
}
for(auto i = offset + size + 1; i < map.size; i++)
{
if(map.data[i] == enc_middle)
map.data[i] = (byte)enc_unknown;
else
break;
}
return true;
}
void EncodeMapDelSegment(duint Start)
{
duint base = MemFindBaseAddr(Start, 0);
if(!base)
return;
duint key = EncodeMap::VaKey(base);
ENCODEMAP map;
if(encmaps.Contains(key))
{
encmaps.Get(key, map);
EncodeMapReleaseBuffer(map.data);
}
encmaps.Delete(key);
}
void EncodeMapDelRange(duint Start, duint End)
{
EncodeMapSetType(Start, End - Start + 1, enc_unknown);
}
void EncodeMapCacheSave(JSON Root)
{
encmaps.CacheSave(Root);
}
void EncodeMapCacheLoad(JSON Root)
{
encmaps.CacheLoad(Root);
}
void EncodeMapClear()
{
EXCLUSIVE_ACQUIRE(LockEncodeMaps);
for(auto & encmap : encmaps.GetDataUnsafe())
EncodeMapReleaseBuffer(encmap.second.data, false);
EXCLUSIVE_RELEASE();
encmaps.Clear();
} |
C/C++ | x64dbg-development/src/dbg/encodemap.h | #pragma once
#include "_global.h"
#include "jansson/jansson_x64dbg.h"
void* EncodeMapGetBuffer(duint addr, duint* size, bool create = false);
void EncodeMapReleaseBuffer(void* buffer);
ENCODETYPE EncodeMapGetType(duint addr, duint codesize);
duint EncodeMapGetSize(duint addr, duint codesize);
void EncodeMapDelSegment(duint addr);
void EncodeMapDelRange(duint addr, duint size);
bool EncodeMapSetType(duint addr, duint size, ENCODETYPE type, bool* created = nullptr);
void EncodeMapDelRange(duint Start, duint End);
void EncodeMapCacheSave(JSON Root);
void EncodeMapCacheLoad(JSON Root);
void EncodeMapClear();
duint GetEncodeTypeSize(ENCODETYPE type); |
C++ | x64dbg-development/src/dbg/exception.cpp | #include <unordered_map>
#include <algorithm>
#include "exception.h"
#include "filehelper.h"
#include "value.h"
#include "console.h"
#include "threading.h"
#include "module.h"
#include "syscalls.h"
static std::unordered_map<unsigned int, String> ExceptionNames;
static std::unordered_map<unsigned int, String> NtStatusNames;
static std::unordered_map<unsigned int, String> ErrorNames;
static std::unordered_map<String, unsigned int> Constants;
static std::unordered_map<unsigned int, String> SyscallIndices;
static bool UniversalCodeInit(const String & file, std::unordered_map<unsigned int, String> & names, unsigned char radix)
{
names.clear();
std::vector<String> lines;
if(!FileHelper::ReadAllLines(file, lines))
return false;
auto result = true;
for(const auto & line : lines)
{
auto split = StringUtils::Split(line, ' ');
if(split.size() < 2)
{
dprintf(QT_TRANSLATE_NOOP("DBG", "Invalid line in exception database: \"%s\"\n"), line.c_str());
result = false;
break;
}
duint code;
if(!convertNumber(split[0].c_str(), code, radix))
{
dprintf(QT_TRANSLATE_NOOP("DBG", "Failed to convert number in exception database \"%s\"\n"), split[0].c_str());
result = false;
break;
}
names.insert({ (unsigned int)code, split[1] });
}
return result;
}
bool ErrorCodeInit(const String & errorFile)
{
return UniversalCodeInit(errorFile, ErrorNames, 10);
}
bool ExceptionCodeInit(const String & exceptionFile)
{
return UniversalCodeInit(exceptionFile, ExceptionNames, 16);
}
bool ConstantCodeInit(const String & constantFile)
{
std::unordered_map<unsigned int, String> names;
if(!UniversalCodeInit(constantFile, names, 0))
return false;
for(const auto & it : names)
Constants.insert({ it.second, it.first });
return true;
}
bool ConstantFromName(const String & name, duint & value)
{
auto found = Constants.find(name);
if(found == Constants.end())
return false;
value = found->second;
return true;
}
std::vector<CONSTANTINFO> ConstantList()
{
std::vector<CONSTANTINFO> result;
for(auto it = Constants.begin(); it != Constants.end(); ++it)
{
CONSTANTINFO info;
info.name = it->first.c_str();
info.value = it->second;
result.push_back(info);
}
std::sort(result.begin(), result.end(), [](const CONSTANTINFO & a, const CONSTANTINFO & b)
{
return strcmp(a.name, b.name) < 0;
});
return result;
}
static bool ExceptionDatabaseNameToCode(const std::unordered_map<unsigned int, String>* db, const char* Name, unsigned int* ErrorCode)
{
for(const auto & i : *db)
{
if(i.second.compare(Name) == 0)
{
*ErrorCode = i.first;
return true;
}
}
return false;
}
bool ExceptionNameToCode(const char* Name, unsigned int* ErrorCode)
{
if(!ExceptionDatabaseNameToCode(&ExceptionNames, Name, ErrorCode))
return ExceptionDatabaseNameToCode(&NtStatusNames, Name, ErrorCode);
return true;
}
bool NtStatusCodeInit(const String & ntStatusFile)
{
return UniversalCodeInit(ntStatusFile, NtStatusNames, 16);
}
static const String emptyString("");
static const String & ExceptionDatabaseCodeToName(std::unordered_map<unsigned int, String>* db, unsigned int ErrorCode, bool* success)
{
auto i = db->find(ErrorCode);
if(i == db->end())
{
*success = false;
return emptyString;
}
*success = true;
return i->second;
}
const String & ExceptionCodeToName(unsigned int ExceptionCode)
{
bool success;
const String & name = ExceptionDatabaseCodeToName(&ExceptionNames, ExceptionCode, &success);
if(!success)
return ExceptionDatabaseCodeToName(&NtStatusNames, ExceptionCode, &success);
else
return name;
}
std::vector<CONSTANTINFO> ExceptionList()
{
std::vector<CONSTANTINFO> result;
for(auto it = ExceptionNames.begin(); it != ExceptionNames.end(); ++it)
{
CONSTANTINFO info;
info.name = it->second.c_str();
info.value = it->first;
result.push_back(info);
}
for(auto it = NtStatusNames.begin(); it != NtStatusNames.end(); ++it)
{
CONSTANTINFO info;
info.name = it->second.c_str();
info.value = it->first;
result.push_back(info);
}
return result;
}
const String & NtStatusCodeToName(unsigned int NtStatusCode)
{
bool success;
return ExceptionDatabaseCodeToName(&NtStatusNames, NtStatusCode, &success);
}
const String & ErrorCodeToName(unsigned int ErrorCode)
{
bool success;
return ExceptionDatabaseCodeToName(&ErrorNames, ErrorCode, &success);
}
std::vector<CONSTANTINFO> ErrorCodeList()
{
std::vector<CONSTANTINFO> result;
for(auto it = ErrorNames.begin(); it != ErrorNames.end(); ++it)
{
CONSTANTINFO info;
info.name = it->second.c_str();
info.value = it->first;
result.push_back(info);
}
std::sort(result.begin(), result.end(), [](const CONSTANTINFO & a, const CONSTANTINFO & b)
{
return strcmp(a.name, b.name) < 0;
});
return result;
}
bool SyscallInit()
{
auto retrieveSyscalls = [](const char* moduleName)
{
auto moduleHandle = GetModuleHandleA(moduleName);
if(!moduleHandle)
return false;
char szModulePath[MAX_PATH];
if(!GetModuleFileNameA(moduleHandle, szModulePath, _countof(szModulePath)))
return false;
if(!ModLoad((duint)moduleHandle, 1, szModulePath, false))
return false;
auto info = ModInfoFromAddr((duint)moduleHandle);
if(info)
{
for(const MODEXPORT & exportEntry : info->exports)
{
if(strncmp(exportEntry.name.c_str(), "Nt", 2) != 0)
continue;
auto exportData = (const unsigned char*)ModRvaToOffset(info->fileMapVA, info->headers, exportEntry.rva);
if(!exportData)
continue;
// https://github.com/mrexodia/TitanHide/blob/1c6ba9796e320f399f998b23fba2729122597e87/TitanHide/ntdll.cpp#L75
DWORD index = -1;
for(int i = 0; i < 32; i++)
{
if(exportData[i] == 0xC2 || exportData[i] == 0xC3) //RET
{
break;
}
if(exportData[i] == 0xB8) //mov eax,X
{
index = *(DWORD*)(exportData + i + 1);
break;
}
}
if(index != -1)
SyscallIndices.emplace(index, exportEntry.name);
}
}
else
{
return false;
}
return true;
};
// See: https://github.com/x64dbg/ScyllaHide/blob/6817d32581b7a420322f34e36b1a1c8c3e4b434c/Scylla/Win32kSyscalls.h
auto result = retrieveSyscalls("ntdll.dll");
OSVERSIONINFOW versionInfo = { sizeof(OSVERSIONINFOW) };
GetVersionExW(&versionInfo);
if(versionInfo.dwBuildNumber >= 14393)
{
result = result && retrieveSyscalls("win32u.dll");
}
else
{
for(auto & syscall : Win32kSyscalls)
{
auto index = syscall.GetSyscallIndex((USHORT)versionInfo.dwBuildNumber, ArchValue(true, false));
if(index != -1)
SyscallIndices.insert({ index, syscall.Name });
}
}
ModClear(false);
return result;
}
const String & SyscallToName(unsigned int index)
{
auto found = SyscallIndices.find(index);
return found != SyscallIndices.end() ? found->second : emptyString;
} |
C/C++ | x64dbg-development/src/dbg/exception.h | #ifndef _EXCEPTION_H
#define _EXCEPTION_H
#define MS_VC_EXCEPTION 0x406D1388
#include "_global.h"
#include "_dbgfunctions.h"
#include "stringutils.h"
bool ExceptionCodeInit(const String & exceptionFile);
const String & ExceptionCodeToName(unsigned int ExceptionCode);
std::vector<CONSTANTINFO> ExceptionList();
bool NtStatusCodeInit(const String & ntStatusFile);
const String & NtStatusCodeToName(unsigned int NtStatusCode);
bool ErrorCodeInit(const String & errorFile);
const String & ErrorCodeToName(unsigned int ErrorCode);
std::vector<CONSTANTINFO> ErrorCodeList();
bool ExceptionNameToCode(const char* Name, unsigned int* ErrorCode);
bool ConstantCodeInit(const String & constantFile);
bool ConstantFromName(const String & name, duint & value);
std::vector<CONSTANTINFO> ConstantList();
// To use this function, use EXCLUSIVE_ACQUIRE(LockModules)
bool SyscallInit();
const String & SyscallToName(unsigned int index);
#endif // _EXCEPTION_H |
C++ | x64dbg-development/src/dbg/exhandlerinfo.cpp | /**
@file exhandlerinfo.cpp
@brief ???
*/
#include "exhandlerinfo.h"
#include "memory.h"
#include "thread.h"
#include "value.h"
#include "debugger.h"
bool IsVistaOrLater()
{
static bool vistaOrLater = []()
{
OSVERSIONINFOEXW osvi = { 0 };
osvi.dwOSVersionInfoSize = sizeof(osvi);
return GetVersionExW((LPOSVERSIONINFOW)&osvi) && osvi.dwMajorVersion > 5;
}();
return vistaOrLater;
}
bool Is19042OrLater()
{
static bool is19042OrLater = []()
{
auto userSharedData = SharedUserData;
return userSharedData->NtBuildNumber >= 19042;
}();
return is19042OrLater;
}
bool ExHandlerGetInfo(EX_HANDLER_TYPE Type, std::vector<duint> & Entries)
{
Entries.clear();
switch(Type)
{
case EX_HANDLER_SEH:
return ExHandlerGetSEH(Entries);
case EX_HANDLER_VEH:
return ExHandlerGetVEH(Entries);
case EX_HANDLER_VCH:
return ExHandlerGetVCH(Entries, false);
case EX_HANDLER_UNHANDLED:
return ExHandlerGetUnhandled(Entries);
}
return false;
}
bool ExHandlerGetInfo(EX_HANDLER_TYPE Type, EX_HANDLER_INFO* Info)
{
std::vector<duint> handlerEntries;
if(!ExHandlerGetInfo(Type, handlerEntries))
{
Info->count = 0;
Info->addresses = nullptr;
return false;
}
// Convert vector to C-style array
Info->count = (int)handlerEntries.size();
Info->addresses = (duint*)BridgeAlloc(Info->count * sizeof(duint));
memcpy(Info->addresses, handlerEntries.data(), Info->count * sizeof(duint));
return true;
}
#define MAX_HANDLER_DEPTH 10
bool ExHandlerGetSEH(std::vector<duint> & Entries)
{
#ifdef _WIN64
return false; // TODO: 64-bit
#endif
static duint nextSEH = 0;
NT_TIB tib;
if(ThreadGetTib((duint)GetTEBLocation(hActiveThread), &tib))
{
EXCEPTION_REGISTRATION_RECORD sehr;
duint addr_ExRegRecord = (duint)tib.ExceptionList;
int MAX_DEPTH = MAX_HANDLER_DEPTH;
while(addr_ExRegRecord != 0xFFFFFFFF && MAX_DEPTH)
{
Entries.push_back(addr_ExRegRecord);
if(!MemRead(addr_ExRegRecord, &sehr, sizeof(EXCEPTION_REGISTRATION_RECORD)))
break;
addr_ExRegRecord = (duint)sehr.Next;
MAX_DEPTH--;
}
}
return true;
}
#pragma pack(8)
struct VEH_ENTRY_XP
{
duint Flink;
duint Blink;
duint VectoredHandler;
};
bool ExHandlerGetVEH(std::vector<duint> & Entries)
{
// Try the address for Windows XP first (or older)
//
// VECTORED_EXCEPTION_NODE RtlpCalloutEntryList;
static duint addr_RtlpCalloutEntryList = 0;
#ifdef _WIN64
auto symbol = "RtlpCalloutEntryList";
#else
auto symbol = "_RtlpCalloutEntryList";
#endif
if(addr_RtlpCalloutEntryList || valfromstring(symbol, &addr_RtlpCalloutEntryList))
{
// Read head entry
auto list_head = addr_RtlpCalloutEntryList;
duint cur_entry;
if(!MemRead(list_head, &cur_entry, sizeof(cur_entry)))
return false;
auto count = 0;
while(cur_entry != list_head && count++ < MAX_HANDLER_DEPTH)
{
VEH_ENTRY_XP entry;
if(!MemRead(cur_entry, &entry, sizeof(entry)))
return false;
auto handler = entry.VectoredHandler;
MemDecodePointer(&handler, false);
Entries.push_back(handler);
if(!MemRead(cur_entry, &cur_entry, sizeof(cur_entry)))
return false;
}
return true;
}
// Otherwise try the Windows Vista or newer version
return ExHandlerGetVCH(Entries, true);
}
#pragma pack(8)
struct VEH_ENTRY_VISTA
{
duint Flink;
duint Blink;
duint PtrRefCount;
duint VectoredHandler; // unclear when this changed
duint VectoredHandler2;
};
bool ExHandlerGetVCH(std::vector<duint> & Entries, bool GetVEH)
{
// VECTORED_HANDLER_LIST LdrpVectorHandlerList[2];
static duint addr_LdrpVectorHandlerList = 0;
duint addrInc = sizeof(duint); //Vista+ has an extra ULONG_PTR in front of the structure
#ifdef _WIN64
auto symbol = "LdrpVectorHandlerList";
#else
auto symbol = "_LdrpVectorHandlerList";
#endif
if(!addr_LdrpVectorHandlerList && !valfromstring(symbol, &addr_LdrpVectorHandlerList))
return false;
// Increase array index when using continue handlers
if(!GetVEH)
addrInc += sizeof(duint) + sizeof(LIST_ENTRY); //Vista+ has an extra ULONG_PTR
// Read head entry
auto list_head = addr_LdrpVectorHandlerList + addrInc;
duint cur_entry;
if(!MemRead(list_head, &cur_entry, sizeof(cur_entry)))
return false;
auto count = 0;
while(cur_entry != list_head && count++ < MAX_HANDLER_DEPTH)
{
VEH_ENTRY_VISTA entry;
if(!MemRead(cur_entry, &entry, sizeof(entry)))
return false;
auto handler = entry.VectoredHandler;
// At some point Windows updated the structure
if(Is19042OrLater())
handler = entry.VectoredHandler2;
if(!MemDecodePointer(&handler, true))
return false;
Entries.push_back(handler);
if(!MemRead(cur_entry, &cur_entry, sizeof(cur_entry)))
return false;
}
return true;
}
bool ExHandlerGetUnhandled(std::vector<duint> & Entries)
{
static duint addr_BasepCurrentTopLevelFilter = 0;
auto symbol = ArchValue("_BasepCurrentTopLevelFilter", "BasepCurrentTopLevelFilter");
if(addr_BasepCurrentTopLevelFilter || valfromstring(symbol, &addr_BasepCurrentTopLevelFilter))
{
// Read external pointer
duint handlerValue = 0;
if(!MemRead(addr_BasepCurrentTopLevelFilter, &handlerValue, sizeof(duint)))
return false;
// Decode with remote process cookie
if(!MemDecodePointer(&handlerValue, IsVistaOrLater()))
return false;
Entries.push_back(handlerValue);
return true;
}
return false;
} |
C/C++ | x64dbg-development/src/dbg/exhandlerinfo.h | #ifndef _EXHANDLERINFO_H
#define _EXHANDLERINFO_H
#include "_global.h"
enum EX_HANDLER_TYPE
{
EX_HANDLER_SEH, // Structured
EX_HANDLER_VEH, // Vectored
EX_HANDLER_VCH, // Vectored continue (Vista+)
EX_HANDLER_UNHANDLED, // Unhandled
};
struct EX_HANDLER_INFO
{
int count;
duint* addresses;
};
bool IsVistaOrLater();
bool Is19042OrLater();
bool ExHandlerGetInfo(EX_HANDLER_TYPE Type, std::vector<duint> & Entries);
bool ExHandlerGetInfo(EX_HANDLER_TYPE Type, EX_HANDLER_INFO* Info);
bool ExHandlerGetSEH(std::vector<duint> & Entries);
bool ExHandlerGetVEH(std::vector<duint> & Entries);
bool ExHandlerGetVCH(std::vector<duint> & Entries, bool GetVEH);
bool ExHandlerGetUnhandled(std::vector<duint> & Entries);
#endif //_EXHANDLERINFO_H |
C++ | x64dbg-development/src/dbg/expressionfunctions.cpp | #include "expressionfunctions.h"
#include "threading.h"
#include "exprfunc.h"
#include "module.h"
#include "debugger.h"
#include "value.h"
std::unordered_map<String, ExpressionFunctions::Function> ExpressionFunctions::mFunctions;
//Copied from https://stackoverflow.com/a/7858971/1806760
template<int...>
struct seq {};
template<int N, int... S>
struct gens : gens < N - 1, N - 1, S... > {};
template<int... S>
struct gens<0, S...>
{
typedef seq<S...> type;
};
template<typename T, int ...S, typename... Ts>
static duint callFunc(const T* argv, duint(*cbFunction)(Ts...), seq<S...>)
{
return cbFunction(argv[S].number...);
}
template<typename... Ts>
static bool RegisterEasy(const String & name, duint(*cbFunction)(Ts...))
{
auto tempFunc = [cbFunction](ExpressionValue * result, int argc, const ExpressionValue * argv, void* userdata) -> bool
{
result->type = ValueTypeNumber;
result->number = callFunc(argv, cbFunction, typename gens<sizeof...(Ts)>::type());
return true;
};
std::vector<ValueType> args(sizeof...(Ts));
for(auto & arg : args)
arg = ValueTypeNumber;
return ExpressionFunctions::Register(name, ValueTypeNumber, args, tempFunc);
}
void ExpressionFunctions::Init()
{
//TODO: register more functions
using namespace Exprfunc;
//GUI interaction
RegisterEasy("disasm.sel,dis.sel", disasmsel);
RegisterEasy("dump.sel", dumpsel);
RegisterEasy("stack.sel", stacksel);
//Source
RegisterEasy("src.line", srcline);
RegisterEasy("src.disp", srcdisp);
//Modules
RegisterEasy("mod.party", modparty);
RegisterEasy("mod.base", ModBaseFromAddr);
RegisterEasy("mod.size", ModSizeFromAddr);
RegisterEasy("mod.hash", ModHashFromAddr);
RegisterEasy("mod.entry", ModEntryFromAddr);
RegisterEasy("mod.system,mod.issystem", modsystem);
RegisterEasy("mod.user,mod.isuser", moduser);
RegisterEasy("mod.main,mod.mainbase", dbgdebuggedbase);
RegisterEasy("mod.rva", modrva);
RegisterEasy("mod.offset,mod.fileoffset", valvatofileoffset);
RegisterEasy("mod.headerva", modheaderva);
RegisterEasy("mod.isexport", modisexport);
ExpressionFunctions::Register("mod.fromname", ValueTypeNumber, { ValueTypeString }, Exprfunc::modbasefromname, nullptr);
//Process information
RegisterEasy("peb,PEB", peb);
RegisterEasy("teb,TEB", teb);
RegisterEasy("tid,TID,ThreadId", tid);
RegisterEasy("kusd,KUSD,KUSER_SHARED_DATA", kusd);
//General purpose
RegisterEasy("bswap", bswap);
RegisterEasy("ternary,tern", ternary);
RegisterEasy("GetTickCount,gettickcount", gettickcount);
RegisterEasy("rdtsc", rdtsc);
//Memory
RegisterEasy("mem.valid,mem.isvalid", memvalid);
RegisterEasy("mem.base", membase);
RegisterEasy("mem.size", memsize);
RegisterEasy("mem.iscode", memiscode);
RegisterEasy("mem.isstring", memisstring);
RegisterEasy("mem.decodepointer", memdecodepointer);
//Disassembly
RegisterEasy("dis.len,dis.size", dislen);
RegisterEasy("dis.iscond", disiscond);
RegisterEasy("dis.isbranch", disisbranch);
RegisterEasy("dis.isret", disisret);
RegisterEasy("dis.iscall", disiscall);
RegisterEasy("dis.ismem", disismem);
RegisterEasy("dis.isnop", disisnop);
RegisterEasy("dis.isunusual", disisunusual);
RegisterEasy("dis.branchdest", disbranchdest);
RegisterEasy("dis.branchexec", disbranchexec);
RegisterEasy("dis.imm", disimm);
RegisterEasy("dis.brtrue", disbrtrue);
RegisterEasy("dis.brfalse", disbrfalse);
RegisterEasy("dis.next", disnext);
RegisterEasy("dis.prev", disprev);
RegisterEasy("dis.iscallsystem", disiscallsystem);
ExpressionFunctions::Register("dis.mnemonic", ValueTypeString, { ValueTypeNumber }, Exprfunc::dismnemonic, nullptr);
ExpressionFunctions::Register("dis.text", ValueTypeString, { ValueTypeNumber }, Exprfunc::distext, nullptr);
ExpressionFunctions::Register("dis.match", ValueTypeNumber, { ValueTypeNumber, ValueTypeString }, Exprfunc::dismatch, nullptr);
//Trace record
RegisterEasy("tr.enabled", trenabled);
RegisterEasy("tr.hitcount,tr.count", trhitcount);
RegisterEasy("tr.isrecording,tr.runtraceenabled", trisrecording);
//Byte/Word/Dword/Qword/Pointer
RegisterEasy("ReadByte,Byte,byte", readbyte);
RegisterEasy("ReadWord,Word,word", readword);
RegisterEasy("ReadDword,Dword,dword", readdword);
#ifdef _WIN64
RegisterEasy("ReadQword,Qword,qword", readqword);
#endif //_WIN64
RegisterEasy("ReadPtr,ReadPointer,ptr,Pointer,pointer", readptr);
//Functions
RegisterEasy("func.start,sub.start", funcstart);
RegisterEasy("func.end,sub.end", funcend);
//References
RegisterEasy("ref.count", refcount);
RegisterEasy("ref.addr", refaddr);
RegisterEasy("refsearch.count", refsearchcount);
RegisterEasy("refsearch.addr", refsearchaddr);
//Arguments
RegisterEasy("arg.get,arg", argget);
RegisterEasy("arg.set", argset);
//Exceptions
RegisterEasy("ex.firstchance", exfirstchance);
RegisterEasy("ex.addr", exaddr);
RegisterEasy("ex.code", excode);
RegisterEasy("ex.flags", exflags);
RegisterEasy("ex.infocount", exinfocount);
RegisterEasy("ex.info", exinfo);
//Undocumented
RegisterEasy("bpgoto", bpgoto);
//Other
RegisterEasy("isdebuggerfocused", isdebuggerfocused);
RegisterEasy("isdebuggeefocused", isdebuggeefocused);
// Strings
ExpressionFunctions::Register("ansi", ValueTypeString, { ValueTypeNumber }, Exprfunc::ansi, nullptr);
ExpressionFunctions::Register("ansi.strict", ValueTypeString, { ValueTypeNumber }, Exprfunc::ansi_strict, nullptr);
ExpressionFunctions::Register("utf8", ValueTypeString, { ValueTypeNumber }, Exprfunc::utf8, nullptr);
ExpressionFunctions::Register("utf8.strict", ValueTypeString, { ValueTypeNumber }, Exprfunc::utf8_strict, nullptr);
ExpressionFunctions::Register("utf16", ValueTypeString, { ValueTypeNumber }, Exprfunc::utf16, nullptr);
ExpressionFunctions::Register("utf16.strict", ValueTypeString, { ValueTypeNumber }, Exprfunc::utf16_strict, nullptr);
ExpressionFunctions::Register("strstr", ValueTypeNumber, { ValueTypeString, ValueTypeString }, Exprfunc::strstr, nullptr);
ExpressionFunctions::Register("stristr", ValueTypeNumber, { ValueTypeString, ValueTypeString }, Exprfunc::stristr, nullptr);
ExpressionFunctions::Register("streq", ValueTypeNumber, { ValueTypeString, ValueTypeString }, Exprfunc::streq, nullptr);
ExpressionFunctions::Register("strieq", ValueTypeNumber, { ValueTypeString, ValueTypeString }, Exprfunc::strieq, nullptr);
ExpressionFunctions::Register("strlen", ValueTypeNumber, { ValueTypeString }, Exprfunc::strlen, nullptr);
}
bool ExpressionFunctions::Register(const String & name, const ValueType & returnType, const std::vector<ValueType> & argTypes, const CBEXPRESSIONFUNCTION & cbFunction, void* userdata)
{
EXCLUSIVE_ACQUIRE(LockExpressionFunctions);
auto aliases = StringUtils::Split(name, ',');
if(!isValidName(aliases[0]))
return false;
if(mFunctions.count(aliases[0]))
return false;
Function f;
f.name = aliases[0];
f.argTypes = argTypes;
f.returnType = returnType;
f.cbFunction = cbFunction;
f.userdata = userdata;
mFunctions[aliases[0]] = f;
for(size_t i = 1; i < aliases.size(); i++)
ExpressionFunctions::RegisterAlias(aliases[0], aliases[i]);
return true;
}
bool ExpressionFunctions::RegisterAlias(const String & name, const String & alias)
{
EXCLUSIVE_ACQUIRE(LockExpressionFunctions);
auto found = mFunctions.find(name);
if(found == mFunctions.end())
return false;
if(!Register(alias, found->second.returnType, found->second.argTypes, found->second.cbFunction, found->second.userdata))
return false;
found->second.aliases.push_back(alias);
return true;
}
bool ExpressionFunctions::Unregister(const String & name)
{
EXCLUSIVE_ACQUIRE(LockExpressionFunctions);
auto found = mFunctions.find(name);
if(found == mFunctions.end())
return false;
auto aliases = found->second.aliases;
mFunctions.erase(found);
for(const auto & alias : aliases)
Unregister(alias);
return true;
}
bool ExpressionFunctions::Call(const String & name, ExpressionValue & result, std::vector<ExpressionValue> & argv)
{
SHARED_ACQUIRE(LockExpressionFunctions);
auto found = mFunctions.find(name);
if(found == mFunctions.end())
return false;
const auto & f = found->second;
if(f.argTypes.size() != int(argv.size()))
return false;
for(size_t i = 0; i < argv.size(); i++)
{
if(argv[i].type != f.argTypes[i] && f.argTypes[i] != ValueTypeAny)
return false;
}
return f.cbFunction(&result, (int)argv.size(), argv.data(), f.userdata);
}
bool ExpressionFunctions::GetType(const String & name, ValueType & returnType, std::vector<ValueType> & argTypes)
{
SHARED_ACQUIRE(LockExpressionFunctions);
auto found = mFunctions.find(name);
if(found == mFunctions.end())
return false;
returnType = found->second.returnType;
argTypes = found->second.argTypes;
return true;
}
bool ExpressionFunctions::isValidName(const String & name)
{
if(!name.length())
return false;
if(!(name[0] == '_' || isalpha(name[0])))
return false;
for(const auto & ch : name)
if(!(isalnum(ch) || ch == '_' || ch == '.'))
return false;
return true;
} |
C/C++ | x64dbg-development/src/dbg/expressionfunctions.h | #pragma once
#include "_global.h"
#include "_plugins.h"
#include <functional>
class ExpressionFunctions
{
public:
using CBEXPRESSIONFUNCTION = std::function<bool(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata)>;
static void Init();
static bool Register(const String & name, const ValueType & returnType, const std::vector<ValueType> & argTypes, const CBEXPRESSIONFUNCTION & cbFunction, void* userdata = nullptr);
static bool RegisterAlias(const String & name, const String & alias);
static bool Unregister(const String & name);
static bool Call(const String & name, ExpressionValue & result, std::vector<ExpressionValue> & argv);
static bool GetType(const String & name, ValueType & returnType, std::vector<ValueType> & argTypes);
private:
struct Function
{
String name;
ValueType returnType;
std::vector<ValueType> argTypes;
CBEXPRESSIONFUNCTION cbFunction;
void* userdata = nullptr;
std::vector<String> aliases;
};
static bool isValidName(const String & name);
static std::unordered_map<String, Function> mFunctions;
}; |
C++ | x64dbg-development/src/dbg/expressionparser.cpp | #include "expressionparser.h"
#include "value.h"
#include "console.h"
#include "variable.h"
#include "expressionfunctions.h"
#include <algorithm>
ExpressionParser::Token::Associativity ExpressionParser::Token::associativity() const
{
switch(mType)
{
case Type::OperatorUnarySub:
case Type::OperatorUnaryAdd:
case Type::OperatorNot:
case Type::OperatorLogicalNot:
case Type::OperatorAssign:
case Type::OperatorAssignMul:
case Type::OperatorAssignHiMul:
case Type::OperatorAssignDiv:
case Type::OperatorAssignMod:
case Type::OperatorAssignAdd:
case Type::OperatorAssignSub:
case Type::OperatorAssignShl:
case Type::OperatorAssignShr:
case Type::OperatorAssignRol:
case Type::OperatorAssignRor:
case Type::OperatorAssignAnd:
case Type::OperatorAssignXor:
case Type::OperatorAssignOr:
case Type::OperatorPrefixInc:
case Type::OperatorPrefixDec:
return Associativity::RightToLeft;
case Type::OperatorMul:
case Type::OperatorHiMul:
case Type::OperatorDiv:
case Type::OperatorMod:
case Type::OperatorAdd:
case Type::OperatorSub:
case Type::OperatorShl:
case Type::OperatorShr:
case Type::OperatorRol:
case Type::OperatorRor:
case Type::OperatorAnd:
case Type::OperatorXor:
case Type::OperatorOr:
case Type::OperatorEqual:
case Type::OperatorNotEqual:
case Type::OperatorBigger:
case Type::OperatorSmaller:
case Type::OperatorBiggerEqual:
case Type::OperatorSmallerEqual:
case Type::OperatorLogicalAnd:
case Type::OperatorLogicalOr:
case Type::OperatorLogicalImpl:
case Type::OperatorSuffixInc:
case Type::OperatorSuffixDec:
return Associativity::LeftToRight;
default:
return Associativity::Unspecified;
}
}
//As defined in http://en.cppreference.com/w/c/language/operator_precedence
int ExpressionParser::Token::precedence() const
{
switch(mType)
{
case Type::OperatorSuffixInc:
case Type::OperatorSuffixDec:
return 1;
case Type::OperatorUnarySub:
case Type::OperatorUnaryAdd:
case Type::OperatorNot:
case Type::OperatorLogicalNot:
case Type::OperatorPrefixInc:
case Type::OperatorPrefixDec:
return 2;
case Type::OperatorMul:
case Type::OperatorHiMul:
case Type::OperatorDiv:
case Type::OperatorMod:
return 3;
case Type::OperatorAdd:
case Type::OperatorSub:
return 4;
case Type::OperatorShl:
case Type::OperatorShr:
case Type::OperatorRol:
case Type::OperatorRor:
return 5;
case Type::OperatorSmaller:
case Type::OperatorSmallerEqual:
case Type::OperatorBigger:
case Type::OperatorBiggerEqual:
return 6;
case Type::OperatorEqual:
case Type::OperatorNotEqual:
return 7;
case Type::OperatorAnd:
return 8;
case Type::OperatorXor:
return 9;
case Type::OperatorOr:
return 10;
case Type::OperatorLogicalAnd:
return 11;
case Type::OperatorLogicalOr:
case Type::OperatorLogicalImpl:
return 12;
case Type::OperatorAssign:
case Type::OperatorAssignMul:
case Type::OperatorAssignHiMul:
case Type::OperatorAssignDiv:
case Type::OperatorAssignMod:
case Type::OperatorAssignAdd:
case Type::OperatorAssignSub:
case Type::OperatorAssignShl:
case Type::OperatorAssignShr:
case Type::OperatorAssignRol:
case Type::OperatorAssignRor:
case Type::OperatorAssignAnd:
case Type::OperatorAssignXor:
case Type::OperatorAssignOr:
return 14;
default:
return 16;
}
}
bool ExpressionParser::Token::isOperator() const
{
return mType >= Type::OperatorUnarySub;
}
ExpressionParser::ExpressionParser(const String & expression)
: mExpression(fixClosingBrackets(expression)),
mIsValidExpression(true)
{
const size_t r = 50;
mTokens.reserve(r);
mCurToken.reserve(r);
tokenize();
shuntingYard();
}
String ExpressionParser::fixClosingBrackets(const String & expression)
{
size_t open = 0;
size_t close = 0;
auto len = expression.length();
for(size_t i = 0; i < len; i++)
{
if(expression[i] == '(')
open++;
else if(expression[i] == ')')
close++;
}
auto result = expression;
if(close < open)
{
for(size_t i = 0; i < open - close; i++)
result += ")";
}
return result;
}
void ExpressionParser::tokenize()
{
size_t stateMemory = 0;
auto stateQuote = false;
auto len = mExpression.length();
auto push_token = [this, &stateQuote](char ch)
{
mCurToken.push_back(ch);
mCurTokenQuoted.push_back(stateQuote);
};
for(size_t i = 0; i < len; i++)
{
auto ch = mExpression[i];
switch(ch)
{
case '\"':
{
stateQuote = !stateQuote;
}
break;
case '[':
{
stateMemory++;
push_token(ch);
}
break;
case ']':
{
if(stateMemory)
stateMemory--;
else
mIsValidExpression = false;
push_token(ch);
}
break;
default:
{
if(stateMemory || stateQuote)
push_token(ch);
else
{
switch(ch)
{
case ',':
addOperatorToken(ch, Token::Type::Comma);
break;
case '(':
addOperatorToken(ch, Token::Type::OpenBracket);
break;
case ')':
addOperatorToken(ch, Token::Type::CloseBracket);
break;
case '~':
addOperatorToken(ch, Token::Type::OperatorNot);
break;
case '*':
if(tryEatNextCh(i, '='))
addOperatorToken("*=", Token::Type::OperatorAssignMul);
else
addOperatorToken(ch, Token::Type::OperatorMul);
break;
case '`':
if(tryEatNextCh(i, '='))
addOperatorToken("`=", Token::Type::OperatorAssignHiMul);
else
addOperatorToken(ch, Token::Type::OperatorHiMul);
break;
case '/':
if(tryEatNextCh(i, '='))
addOperatorToken("/=", Token::Type::OperatorAssignDiv);
else
addOperatorToken(ch, Token::Type::OperatorDiv);
break;
case '%':
if(tryEatNextCh(i, '='))
addOperatorToken("%=", Token::Type::OperatorAssignMod);
else
addOperatorToken(ch, Token::Type::OperatorMod);
break;
case '+':
if(tryEatNextCh(i, '='))
addOperatorToken("+=", Token::Type::OperatorAssignAdd);
else if(tryEatNextCh(i, '+'))
addOperatorToken("++", isUnaryOperator() ? Token::Type::OperatorPrefixInc : Token::Type::OperatorSuffixInc);
else if(isUnaryOperator())
addOperatorToken(ch, Token::Type::OperatorUnaryAdd);
else
addOperatorToken(ch, Token::Type::OperatorAdd);
break;
case '-':
if(tryEatNextCh(i, '>'))
addOperatorToken("->", Token::Type::OperatorLogicalImpl);
else if(tryEatNextCh(i, '='))
addOperatorToken("-=", Token::Type::OperatorAssignSub);
else if(tryEatNextCh(i, '-'))
addOperatorToken("--", isUnaryOperator() ? Token::Type::OperatorPrefixDec : Token::Type::OperatorSuffixDec);
else if(isUnaryOperator())
addOperatorToken(ch, Token::Type::OperatorUnarySub);
else
addOperatorToken(ch, Token::Type::OperatorSub);
break;
case '=':
if(tryEatNextCh(i, '='))
addOperatorToken("==", Token::Type::OperatorEqual);
else
addOperatorToken(ch, Token::Type::OperatorAssign);
break;
case '<':
if(tryEatNextCh(i, '='))
addOperatorToken("<=", Token::Type::OperatorSmallerEqual);
else if(tryEatNextCh(i, '<'))
{
if(tryEatNextCh(i, '<'))
{
if(tryEatNextCh(i, '='))
addOperatorToken("<<<=", Token::Type::OperatorAssignRol);
else
addOperatorToken("<<<", Token::Type::OperatorRol);
}
else if(tryEatNextCh(i, '='))
addOperatorToken("<<=", Token::Type::OperatorAssignShl);
else
addOperatorToken("<<", Token::Type::OperatorShl);
}
else
addOperatorToken(ch, Token::Type::OperatorSmaller);
break;
case '>':
if(tryEatNextCh(i, '='))
addOperatorToken(">=", Token::Type::OperatorBiggerEqual);
else if(tryEatNextCh(i, '>'))
{
if(tryEatNextCh(i, '>'))
{
if(tryEatNextCh(i, '='))
addOperatorToken(">>>=", Token::Type::OperatorAssignRor);
else
addOperatorToken(">>>", Token::Type::OperatorRor);
}
else if(tryEatNextCh(i, '='))
addOperatorToken(">>=", Token::Type::OperatorAssignShr);
else
addOperatorToken(">>", Token::Type::OperatorShr);
}
else
addOperatorToken(ch, Token::Type::OperatorBigger);
break;
case '&':
if(tryEatNextCh(i, '&'))
addOperatorToken("&&", Token::Type::OperatorLogicalAnd);
else if(tryEatNextCh(i, '='))
addOperatorToken("&=", Token::Type::OperatorAssignAnd);
else
addOperatorToken(ch, Token::Type::OperatorAnd);
break;
case '^':
if(tryEatNextCh(i, '='))
addOperatorToken("^=", Token::Type::OperatorAssignXor);
else
addOperatorToken(ch, Token::Type::OperatorXor);
break;
case '|':
if(tryEatNextCh(i, '|'))
addOperatorToken("||", Token::Type::OperatorLogicalOr);
else if(tryEatNextCh(i, '='))
addOperatorToken("|=", Token::Type::OperatorAssignOr);
else
addOperatorToken(ch, Token::Type::OperatorOr);
break;
case '!':
if(tryEatNextCh(i, '='))
addOperatorToken("!=", Token::Type::OperatorNotEqual);
else
addOperatorToken(ch, Token::Type::OperatorLogicalNot);
break;
case ' ': //ignore spaces
case '\t': //ignore tabs
break;
default:
push_token(ch);
break;
}
}
}
break;
}
}
if(mCurToken.length() != 0) //make sure the last token is added
{
mTokens.push_back(Token(mCurToken, resolveQuotedData()));
mCurToken.clear();
mCurTokenQuoted.clear();
}
}
void ExpressionParser::addOperatorToken(const String & data, Token::Type type)
{
if(mCurToken.length()) //add a new data token when there is data in the buffer
{
mTokens.push_back(Token(mCurToken, type == Token::Type::OpenBracket ? Token::Type::Function : resolveQuotedData()));
mCurToken.clear();
mCurTokenQuoted.clear();
}
mTokens.push_back(Token(data, type)); //add the operator token
}
ExpressionParser::Token::Type ExpressionParser::resolveQuotedData() const
{
auto allQuoted = std::find(mCurTokenQuoted.begin(), mCurTokenQuoted.end(), false) == mCurTokenQuoted.end();
return allQuoted ? Token::Type::QuotedData : Token::Type::Data;
}
bool ExpressionParser::isUnaryOperator() const
{
if(mCurToken.length()) //data before the operator means it is no unary operator
return false;
if(!mTokens.size()) //no tokens before the operator means it is an unary operator
return true;
auto lastType = mTokens.back().type();
//if the previous token is not data or a close bracket, this operator is a unary operator
return lastType != Token::Type::Data && lastType != Token::Type::QuotedData && lastType != Token::Type::CloseBracket;
}
void ExpressionParser::shuntingYard()
{
//Implementation of Dijkstra's Shunting-yard algorithm (https://en.wikipedia.org/wiki/Shunting-yard_algorithm)
std::vector<Token> queue;
std::vector<Token> stack;
auto len = mTokens.size();
queue.reserve(len);
stack.reserve(len);
//process the tokens
for(size_t i = 0; i < len; i++)
{
const auto & token = mTokens[i]; //Read a token
switch(token.type())
{
case Token::Type::Data: //If the token is a number, then push it to the output queue.
case Token::Type::QuotedData:
queue.push_back(token);
break;
case Token::Type::Function: //If the token is a function token, then push it onto the stack.
stack.push_back(token);
break;
case Token::Type::Comma: //If the token is a function argument separator (e.g., a comma):
while(true) //Until the token at the top of the stack is a left parenthesis, pop operators off the stack onto the output queue.
{
if(stack.empty()) //If no left parentheses are encountered, either the separator was misplaced or parentheses were mismatched.
{
mIsValidExpression = false;
return;
}
const auto & curToken = stack.back();
if(curToken.type() == Token::Type::OpenBracket)
break;
queue.push_back(curToken);
stack.pop_back();
}
break;
case Token::Type::OpenBracket: //If the token is a left parenthesis (i.e. "("), then push it onto the stack.
stack.push_back(token);
break;
case Token::Type::CloseBracket: //If the token is a right parenthesis (i.e. ")"):
{
while(true) //Until the token at the top of the stack is a left parenthesis, pop operators off the stack onto the output queue.
{
if(stack.empty()) //If the stack runs out without finding a left parenthesis, then there are mismatched parentheses.
{
mIsValidExpression = false;
return;
}
auto curToken = stack.back();
stack.pop_back(); //Pop the left parenthesis from the stack, but not onto the output queue.
if(curToken.type() == Token::Type::OpenBracket) //the bracket is already popped here
break;
queue.push_back(curToken);
}
auto size = stack.size();
if(size && stack[size - 1].type() == Token::Type::Function) //If the token at the top of the stack is a function token, pop it onto the output queue.
{
queue.push_back(stack[size - 1]);
stack.pop_back();
}
}
break;
default: //If the token is an operator, o1, then:
const auto & o1 = token;
while(!stack.empty()) //while there is an operator token o2, at the top of the operator stack and either
{
const auto & o2 = stack.back();
if(o2.isOperator() &&
(o1.associativity() == Token::Associativity::LeftToRight && o1.precedence() >= o2.precedence()) || //o1 is left-associative and its precedence is less than or equal to that of o2, or
(o1.associativity() == Token::Associativity::RightToLeft && o1.precedence() > o2.precedence())) //o1 is right associative, and has precedence less than that of o2,
{
queue.push_back(o2); //pop o2 off the operator stack, onto the output queue;
stack.pop_back();
}
else
break;
}
stack.push_back(o1); //at the end of iteration push o1 onto the operator stack.
break;
}
}
//When there are no more tokens to read:
while(!stack.empty()) //While there are still operator tokens in the stack:
{
const auto & curToken = stack.back();
if(curToken.type() == Token::Type::OpenBracket || curToken.type() == Token::Type::CloseBracket) //If the operator token on the top of the stack is a parenthesis, then there are mismatched parentheses.
{
mIsValidExpression = false;
return;
}
queue.push_back(curToken); //Pop the operator onto the output queue.
stack.pop_back();
}
mPrefixTokens = std::move(queue);
}
#if defined(_WIN64) && (!defined(__clang__) || __clang_major__ > 3) // This produces an ICE under Clang <= 3.8; fixed in 5.0.
#include <intrin.h>
static unsigned long long umulhi(unsigned long long x, unsigned long long y)
{
unsigned __int64 res;
_umul128(x, y, &res);
return res;
}
static long long mulhi(long long x, long long y)
{
__int64 res;
_mul128(x, y, &res);
return res;
}
#else
static unsigned int umulhi(unsigned int x, unsigned int y)
{
return (unsigned int)(((unsigned long long)x * y) >> 32);
}
static int mulhi(int x, int y)
{
return (int)(((long long)x * y) >> 32);
}
#endif //_WIN64
template<typename T>
static bool operation(ExpressionParser::Token::Type type, T op1, T op2, T & result, bool signedcalc)
{
result = 0;
switch(type)
{
case ExpressionParser::Token::Type::OperatorUnarySub:
result = op1 * ~0;
break;
case ExpressionParser::Token::Type::OperatorUnaryAdd:
result = +op1;
break;
case ExpressionParser::Token::Type::OperatorNot:
result = ~op1;
break;
case ExpressionParser::Token::Type::OperatorLogicalNot:
result = !op1 ? 1 : 0;
break;
case ExpressionParser::Token::Type::OperatorMul:
result = op1 * op2;
break;
case ExpressionParser::Token::Type::OperatorHiMul:
if(signedcalc)
result = mulhi(op1, op2);
else
result = umulhi(op1, op2);
break;
case ExpressionParser::Token::Type::OperatorDiv:
if(op2 == 0)
return false;
result = op1 / op2;
break;
case ExpressionParser::Token::Type::OperatorMod:
if(op2 == 0)
return false;
result = op1 % op2;
break;
case ExpressionParser::Token::Type::OperatorAdd:
result = op1 + op2;
break;
case ExpressionParser::Token::Type::OperatorSub:
result = op1 - op2;
break;
case ExpressionParser::Token::Type::OperatorShl:
result = op1 << op2;
break;
case ExpressionParser::Token::Type::OperatorShr:
result = op1 >> op2;
break;
case ExpressionParser::Token::Type::OperatorRol:
#ifdef _WIN64
result = _rotl64(op1, int(op2) % 64);
#else
result = _rotl(op1, int(op2) % 32);
#endif
break;
case ExpressionParser::Token::Type::OperatorRor:
#ifdef _WIN64
result = _rotr64(op1, int(op2) % 64);
#else
result = _rotr(op1, int(op2) % 32);
#endif
break;
case ExpressionParser::Token::Type::OperatorAnd:
result = op1 & op2;
break;
case ExpressionParser::Token::Type::OperatorXor:
result = op1 ^ op2;
break;
case ExpressionParser::Token::Type::OperatorOr:
result = op1 | op2;
break;
case ExpressionParser::Token::Type::OperatorEqual:
result = op1 == op2 ? 1 : 0;
break;
case ExpressionParser::Token::Type::OperatorNotEqual:
result = op1 != op2 ? 1 : 0;
break;
case ExpressionParser::Token::Type::OperatorBigger:
result = op1 > op2 ? 1 : 0;
break;
case ExpressionParser::Token::Type::OperatorSmaller:
result = op1 < op2 ? 1 : 0;
break;
case ExpressionParser::Token::Type::OperatorBiggerEqual:
result = op1 >= op2 ? 1 : 0;
break;
case ExpressionParser::Token::Type::OperatorSmallerEqual:
result = op1 <= op2 ? 1 : 0;
break;
case ExpressionParser::Token::Type::OperatorLogicalAnd:
result = op1 && op2 ? 1 : 0;
break;
case ExpressionParser::Token::Type::OperatorLogicalOr:
result = op1 || op2 ? 1 : 0;
break;
case ExpressionParser::Token::Type::OperatorLogicalImpl:
result = !op1 || op2 ? 1 : 0;
break;
default:
return false;
}
return true;
}
static bool getAssignmentOperator(ExpressionParser::Token::Type type, ExpressionParser::Token::Type & result)
{
switch(type)
{
case ExpressionParser::Token::Type::OperatorAssign:
return false;
case ExpressionParser::Token::Type::OperatorAssignMul:
result = ExpressionParser::Token::Type::OperatorMul;
break;
case ExpressionParser::Token::Type::OperatorAssignHiMul:
result = ExpressionParser::Token::Type::OperatorHiMul;
break;
case ExpressionParser::Token::Type::OperatorAssignDiv:
result = ExpressionParser::Token::Type::OperatorDiv;
break;
case ExpressionParser::Token::Type::OperatorAssignMod:
result = ExpressionParser::Token::Type::OperatorMod;
break;
case ExpressionParser::Token::Type::OperatorAssignAdd:
result = ExpressionParser::Token::Type::OperatorAdd;
break;
case ExpressionParser::Token::Type::OperatorAssignSub:
result = ExpressionParser::Token::Type::OperatorSub;
break;
case ExpressionParser::Token::Type::OperatorAssignShl:
result = ExpressionParser::Token::Type::OperatorShl;
break;
case ExpressionParser::Token::Type::OperatorAssignShr:
result = ExpressionParser::Token::Type::OperatorShr;
break;
case ExpressionParser::Token::Type::OperatorAssignRol:
result = ExpressionParser::Token::Type::OperatorRol;
break;
case ExpressionParser::Token::Type::OperatorAssignRor:
result = ExpressionParser::Token::Type::OperatorRor;
break;
case ExpressionParser::Token::Type::OperatorAssignAnd:
result = ExpressionParser::Token::Type::OperatorAnd;
break;
case ExpressionParser::Token::Type::OperatorAssignXor:
result = ExpressionParser::Token::Type::OperatorXor;
break;
case ExpressionParser::Token::Type::OperatorAssignOr:
result = ExpressionParser::Token::Type::OperatorOr;
break;
default:
__debugbreak();
}
return true;
}
static bool handleAssignment(const char* variable, duint resultv, bool silent, bool allowassign)
{
if(!allowassign)
return false;
bool destIsVar = false;
duint temp;
valfromstring_noexpr(variable, &temp, true, true, nullptr, &destIsVar, nullptr); //there is no return check on this because the destination might not exist yet
if(!destIsVar)
destIsVar = vargettype(variable, nullptr);
if(!destIsVar || !valtostring(variable, resultv, true))
{
duint value;
if(valfromstring(variable, &value)) //if the var is a value already it's an invalid destination
{
if(!silent)
dprintf(QT_TRANSLATE_NOOP("DBG", "invalid dest \"%s\"\n"), variable);
return false;
}
varnew(variable, resultv, VAR_USER);
}
return true;
}
template<typename T>
static bool evalOperation(ExpressionParser::Token::Type type, const ExpressionParser::EvalValue & op1, const ExpressionParser::EvalValue & op2, ExpressionParser::EvalValue & result, bool signedcalc, bool silent, bool baseonly, bool allowassign)
{
switch(type)
{
case ExpressionParser::Token::Type::OperatorAssign:
case ExpressionParser::Token::Type::OperatorAssignMul:
case ExpressionParser::Token::Type::OperatorAssignHiMul:
case ExpressionParser::Token::Type::OperatorAssignDiv:
case ExpressionParser::Token::Type::OperatorAssignMod:
case ExpressionParser::Token::Type::OperatorAssignAdd:
case ExpressionParser::Token::Type::OperatorAssignSub:
case ExpressionParser::Token::Type::OperatorAssignShl:
case ExpressionParser::Token::Type::OperatorAssignShr:
case ExpressionParser::Token::Type::OperatorAssignRol:
case ExpressionParser::Token::Type::OperatorAssignRor:
case ExpressionParser::Token::Type::OperatorAssignAnd:
case ExpressionParser::Token::Type::OperatorAssignXor:
case ExpressionParser::Token::Type::OperatorAssignOr:
{
if(op1.evaluated)
return false;
ExpressionParser::EvalValue newvalue(0);
ExpressionParser::Token::Type assop;
if(getAssignmentOperator(type, assop))
{
if(!evalOperation<T>(assop, op1, op2, newvalue, signedcalc, silent, baseonly, allowassign))
return false;
}
else
newvalue = op2;
duint resultv;
if(!newvalue.DoEvaluate(resultv, silent, baseonly))
return false;
if(!handleAssignment(op1.data.c_str(), resultv, silent, allowassign))
return false;
result = ExpressionParser::EvalValue(resultv);
}
break;
case ExpressionParser::Token::Type::OperatorPrefixInc:
case ExpressionParser::Token::Type::OperatorPrefixDec:
case ExpressionParser::Token::Type::OperatorSuffixInc:
case ExpressionParser::Token::Type::OperatorSuffixDec:
{
if(op1.evaluated)
return false;
duint op1v;
if(!op1.DoEvaluate(op1v, silent, baseonly))
return false;
duint resultv;
switch(type)
{
case ExpressionParser::Token::Type::OperatorPrefixInc:
resultv = ++op1v;
break;
case ExpressionParser::Token::Type::OperatorPrefixDec:
resultv = --op1v;
break;
case ExpressionParser::Token::Type::OperatorSuffixInc:
resultv = op1v++;
break;
case ExpressionParser::Token::Type::OperatorSuffixDec:
resultv = op1v--;
break;
default:
return false;
}
if(!handleAssignment(op1.data.c_str(), op1v, silent, allowassign))
return false;
result = ExpressionParser::EvalValue(resultv);
}
break;
default:
{
duint op1v, op2v;
if(op1.isString || op2.isString)
return false;
if(!op1.DoEvaluate(op1v, silent, baseonly) || !op2.DoEvaluate(op2v, silent, baseonly))
return false;
T resultv;
if(!operation<T>(type, T(op1v), T(op2v), resultv, signedcalc))
return false;
result = ExpressionParser::EvalValue(duint(resultv));
}
break;
}
return true;
}
bool ExpressionParser::unsignedOperation(Token::Type type, const EvalValue & op1, const EvalValue & op2, EvalValue & result, bool silent, bool baseonly, bool allowassign) const
{
return evalOperation<duint>(type, op1, op2, result, false, silent, baseonly, allowassign);
}
bool ExpressionParser::signedOperation(Token::Type type, const EvalValue & op1, const EvalValue & op2, EvalValue & result, bool silent, bool baseonly, bool allowassign) const
{
return evalOperation<dsint>(type, op1, op2, result, true, silent, baseonly, allowassign);
}
bool ExpressionParser::Calculate(duint & value, bool signedcalc, bool allowassign, bool silent, bool baseonly, int* value_size, bool* isvar, bool* hexonly) const
{
EvalValue evalue(0);
if(!Calculate(evalue, signedcalc, allowassign, silent, baseonly, value_size, isvar, hexonly))
return false;
if(evalue.isString)
{
if(!silent)
dprintf(QT_TRANSLATE_NOOP("DBG", "Expression evaluated to a string: \"%s\"\n"), StringUtils::Escape(evalue.data).c_str());
return false;
}
return evalue.DoEvaluate(value, silent, baseonly, value_size, isvar, hexonly);
}
bool ExpressionParser::Calculate(EvalValue & value, bool signedcalc, bool allowassign, bool silent, bool baseonly, int* value_size, bool* isvar, bool* hexonly) const
{
if(!mPrefixTokens.size() || !mIsValidExpression)
return false;
std::vector<EvalValue> stack;
stack.reserve(mPrefixTokens.size());
//calculate the result from the RPN queue
for(const auto & token : mPrefixTokens)
{
if(token.isOperator())
{
EvalValue op1(0);
EvalValue op2(0);
EvalValue result(0);
bool operationSuccess;
auto type = token.type();
switch(type)
{
case Token::Type::OperatorUnarySub:
case Token::Type::OperatorUnaryAdd:
case Token::Type::OperatorNot:
case Token::Type::OperatorLogicalNot:
case Token::Type::OperatorPrefixInc:
case Token::Type::OperatorPrefixDec:
case Token::Type::OperatorSuffixInc:
case Token::Type::OperatorSuffixDec:
if(stack.empty())
return false;
op1 = stack.back();
stack.pop_back();
if(signedcalc)
operationSuccess = signedOperation(type, op1, op2, result, silent, baseonly, allowassign);
else
operationSuccess = unsignedOperation(type, op1, op2, result, silent, baseonly, allowassign);
if(!operationSuccess)
return false;
stack.push_back(result);
break;
case Token::Type::OperatorMul:
case Token::Type::OperatorHiMul:
case Token::Type::OperatorDiv:
case Token::Type::OperatorMod:
case Token::Type::OperatorAdd:
case Token::Type::OperatorSub:
case Token::Type::OperatorShl:
case Token::Type::OperatorShr:
case Token::Type::OperatorRol:
case Token::Type::OperatorRor:
case Token::Type::OperatorAnd:
case Token::Type::OperatorXor:
case Token::Type::OperatorOr:
case Token::Type::OperatorEqual:
case Token::Type::OperatorNotEqual:
case Token::Type::OperatorBigger:
case Token::Type::OperatorSmaller:
case Token::Type::OperatorBiggerEqual:
case Token::Type::OperatorSmallerEqual:
case Token::Type::OperatorLogicalAnd:
case Token::Type::OperatorLogicalOr:
case Token::Type::OperatorLogicalImpl:
case Token::Type::OperatorAssign:
case Token::Type::OperatorAssignMul:
case Token::Type::OperatorAssignHiMul:
case Token::Type::OperatorAssignDiv:
case Token::Type::OperatorAssignMod:
case Token::Type::OperatorAssignAdd:
case Token::Type::OperatorAssignSub:
case Token::Type::OperatorAssignShl:
case Token::Type::OperatorAssignShr:
case Token::Type::OperatorAssignRol:
case Token::Type::OperatorAssignRor:
case Token::Type::OperatorAssignAnd:
case Token::Type::OperatorAssignXor:
case Token::Type::OperatorAssignOr:
if(stack.size() < 2)
return false;
op2 = stack.back();
stack.pop_back();
op1 = stack.back();
stack.pop_back();
if(signedcalc)
operationSuccess = signedOperation(type, op1, op2, result, silent, baseonly, allowassign);
else
operationSuccess = unsignedOperation(type, op1, op2, result, silent, baseonly, allowassign);
if(!operationSuccess)
return false;
stack.push_back(result);
break;
case Token::Type::Error:
return false;
default: //do nothing
break;
}
}
else if(token.type() == Token::Type::Function)
{
const auto & name = token.data();
ValueType returnType;
std::vector<ValueType> argTypes;
if(!ExpressionFunctions::GetType(name, returnType, argTypes))
return false;
if(int(stack.size()) < argTypes.size())
return false;
std::vector<ExpressionValue> argv;
argv.resize(argTypes.size());
for(size_t i = 0; i < argTypes.size(); i++)
{
const auto & argType = argTypes[argTypes.size() - i - 1];
auto & top = stack[stack.size() - i - 1];
ExpressionValue arg;
if(top.isString)
{
arg = { ValueTypeString, 0, StringValue{ top.data.c_str(), false } };
}
else if(top.evaluated)
{
arg = { ValueTypeNumber, top.value };
}
else
{
duint result;
if(!top.DoEvaluate(result, silent, baseonly, value_size, isvar, hexonly))
return false;
arg = { ValueTypeNumber, result };
}
if(arg.type != argType && argType != ValueTypeAny)
{
if(!silent)
{
auto typeName = [](ValueType t) -> String
{
switch(t)
{
case ValueTypeNumber:
return GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "number"));
case ValueTypeString:
return GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "string"));
}
return GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "invalid"));
};
String argValueStr;
if(arg.type == ValueTypeNumber)
{
argValueStr = StringUtils::sprintf("0x%p", arg.number);
}
else if(arg.type == ValueTypeString)
{
argValueStr = "\"" + StringUtils::Escape(arg.string.ptr) + "\"";
}
else
{
argValueStr = "???";
}
String signature = name;
signature += "(";
for(size_t j = 0; j < argTypes.size(); j++)
{
if(j > 0)
{
signature += ", ";
}
signature += typeName(argTypes[j]);
}
signature += ")";
dprintf(QT_TRANSLATE_NOOP("DBG", "Expression function %s argument %d/%d (%s) type mismatch (expected %s, got %s)!\n"),
signature.c_str(),
argTypes.size() - i,
argTypes.size(),
argValueStr.c_str(),
typeName(argType).c_str(),
typeName(arg.type).c_str()
);
}
return false;
}
argv[argTypes.size() - i - 1] = arg;
}
ExpressionValue result = { ValueTypeNumber, 0 };
if(!ExpressionFunctions::Call(name, result, argv))
return false;
if(result.type == ValueTypeAny)
return false;
for(size_t i = 0; i < argv.size(); i++)
{
stack.pop_back();
}
if(result.type == ValueTypeString)
{
stack.push_back(EvalValue(result.string.ptr, true));
if(result.string.isOwner)
BridgeFree((void*)result.string.ptr);
}
else
stack.push_back(EvalValue(result.number));
}
else
stack.push_back(EvalValue(token.data(), token.type() == Token::Type::QuotedData));
}
if(stack.size() != 1) //there should only be one value left on the stack
return false;
value = stack.back();
return true;
} |
C/C++ | x64dbg-development/src/dbg/expressionparser.h | #ifndef _EXPRESSION_PARSER_H
#define _EXPRESSION_PARSER_H
#include "_global.h"
#include "value.h"
class ExpressionParser
{
public:
struct EvalValue
{
bool evaluated = false;
bool isString = false;
duint value = 0;
String data;
explicit EvalValue(duint value)
: evaluated(true), value(value) {}
explicit EvalValue(const String & data, bool isString)
: evaluated(false), data(data), isString(isString) {}
bool DoEvaluate(duint & result, bool silent = true, bool baseonly = false, int* value_size = nullptr, bool* isvar = nullptr, bool* hexonly = nullptr) const
{
if(evaluated)
{
if(value_size)
*value_size = sizeof(duint);
if(isvar)
*isvar = false;
if(hexonly)
*hexonly = false;
result = value;
return true;
}
return valfromstring_noexpr(data.c_str(), &result, silent, baseonly, value_size, isvar, hexonly);
}
};
explicit ExpressionParser(const String & expression);
bool Calculate(duint & value, bool signedcalc, bool allowassign, bool silent = true, bool baseonly = false, int* value_size = nullptr, bool* isvar = nullptr, bool* hexonly = nullptr) const;
bool Calculate(EvalValue & value, bool signedcalc, bool allowassign, bool silent = true, bool baseonly = false, int* value_size = nullptr, bool* isvar = nullptr, bool* hexonly = nullptr) const;
const String & GetExpression() const
{
return mExpression;
}
bool IsValidExpression() const
{
return mIsValidExpression;
}
class Token
{
public:
enum class Type
{
Error,
Data,
QuotedData,
Function,
Comma,
OpenBracket,
CloseBracket,
OperatorUnarySub,
OperatorUnaryAdd,
OperatorNot,
OperatorMul,
OperatorHiMul,
OperatorDiv,
OperatorMod,
OperatorAdd,
OperatorSub,
OperatorShl,
OperatorShr,
OperatorRol,
OperatorRor,
OperatorAnd,
OperatorXor,
OperatorOr,
OperatorEqual,
OperatorNotEqual,
OperatorBigger,
OperatorSmaller,
OperatorBiggerEqual,
OperatorSmallerEqual,
OperatorLogicalAnd,
OperatorLogicalOr,
OperatorLogicalNot,
OperatorLogicalImpl,
OperatorAssign,
OperatorAssignMul,
OperatorAssignHiMul,
OperatorAssignDiv,
OperatorAssignMod,
OperatorAssignAdd,
OperatorAssignSub,
OperatorAssignShl,
OperatorAssignShr,
OperatorAssignRol,
OperatorAssignRor,
OperatorAssignAnd,
OperatorAssignXor,
OperatorAssignOr,
OperatorSuffixInc,
OperatorSuffixDec,
OperatorPrefixInc,
OperatorPrefixDec
};
enum class Associativity
{
LeftToRight,
RightToLeft,
Unspecified
};
Token(const String & data, Type type)
: mData(data),
mType(type)
{
}
const String & data() const
{
return mData;
}
Type type() const
{
return mType;
}
Associativity associativity() const;
int precedence() const;
bool isOperator() const;
private:
String mData;
Type mType;
};
private:
static String fixClosingBrackets(const String & expression);
Token::Type resolveQuotedData() const;
bool isUnaryOperator() const;
void tokenize();
void shuntingYard();
void addOperatorToken(const String & data, Token::Type type);
bool unsignedOperation(Token::Type type, const EvalValue & op1, const EvalValue & op2, EvalValue & result, bool silent, bool baseonly, bool allowassign) const;
bool signedOperation(Token::Type type, const EvalValue & op1, const EvalValue & op2, EvalValue & result, bool silent, bool baseonly, bool allowassign) const;
void addOperatorToken(char ch, Token::Type type)
{
String data;
data.push_back(ch);
addOperatorToken(data, type);
}
bool tryEatNextCh(size_t & i, char ch) const
{
if(!(i + 1 < mExpression.length() && mExpression[i + 1] == ch))
return false;
i++;
return true;
}
String mExpression;
bool mIsValidExpression;
std::vector<Token> mTokens;
std::vector<Token> mPrefixTokens;
String mCurToken;
std::vector<bool> mCurTokenQuoted;
};
#endif //_EXPRESSION_PARSER_H |
C++ | x64dbg-development/src/dbg/exprfunc.cpp | #include "exprfunc.h"
#include "symbolinfo.h"
#include "module.h"
#include "debugger.h"
#include "thread.h"
#include "memory.h"
#include "disasm_fast.h"
#include "TraceRecord.h"
#include "disasm_helper.h"
#include "function.h"
#include "value.h"
#include "TraceRecord.h"
#include "exhandlerinfo.h"
#include <vector>
#include <regex>
#include <string>
#include <cctype>
/// <summary>
/// Creates an owning ExpressionValue string
/// </summary>
static ExpressionValue ValueString(const char* str)
{
auto len = ::strlen(str);
auto buf = (char*)BridgeAlloc(len + 1);
memcpy(buf, str, len);
ExpressionValue value = {};
value.type = ValueTypeString;
value.string.ptr = buf;
value.string.isOwner = true;
return value;
}
/// <summary>
/// Creates an owning ExpressionValue string
/// </summary>
static ExpressionValue ValueString(const String & str)
{
auto len = str.length();
auto buf = (char*)BridgeAlloc(len + 1);
memcpy(buf, str.c_str(), len);
ExpressionValue value = {};
value.type = ValueTypeString;
value.string.ptr = buf;
value.string.isOwner = true;
return value;
}
/// <summary>
/// Creates an owning ExpressionValue number
/// </summary>
static ExpressionValue ValueNumber(duint number)
{
ExpressionValue value = {};
value.type = ValueTypeNumber;
value.number = number;
return value;
}
namespace Exprfunc
{
duint srcline(duint addr)
{
int line = 0;
if(!SymGetSourceLine(addr, nullptr, &line, nullptr))
return 0;
return line;
}
duint srcdisp(duint addr)
{
duint disp;
if(!SymGetSourceLine(addr, nullptr, nullptr, &disp))
return 0;
return disp;
}
duint modparty(duint addr)
{
return ModGetParty(addr);
}
duint modsystem(duint addr)
{
SHARED_ACQUIRE(LockModules);
auto info = ModInfoFromAddr(addr);
if(info)
return info->party == mod_system;
else
return 0;
}
duint moduser(duint addr)
{
SHARED_ACQUIRE(LockModules);
auto info = ModInfoFromAddr(addr);
if(info)
return info->party == mod_user;
else
return 0;
}
duint modrva(duint addr)
{
auto base = ModBaseFromAddr(addr);
return base ? addr - base : 0;
}
duint modheaderva(duint addr)
{
SHARED_ACQUIRE(LockModules);
auto info = ModInfoFromAddr(addr);
if(info)
return (addr - info->base) + info->headerImageBase;
else
return 0;
}
duint modisexport(duint addr)
{
SHARED_ACQUIRE(LockModules);
auto info = ModInfoFromAddr(addr);
if(info)
{
duint rva = addr - info->base;
return info->findExport(rva) ? 1 : 0;
}
return 0;
}
bool modbasefromname(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata)
{
assert(argc == 1);
assert(argv[0].type == ValueTypeString);
*result = ValueNumber(ModBaseFromName(argv[0].string.ptr));
return true;
}
static duint selstart(GUISELECTIONTYPE hWindow)
{
SELECTIONDATA selection;
GuiSelectionGet(hWindow, &selection);
return selection.start;
}
duint disasmsel()
{
return selstart(GUI_DISASSEMBLY);
}
duint dumpsel()
{
return selstart(GUI_DUMP);
}
duint stacksel()
{
return selstart(GUI_STACK);
}
duint peb()
{
return duint(GetPEBLocation(fdProcessInfo->hProcess));
}
duint teb()
{
return duint(GetTEBLocation(hActiveThread));
}
duint tid()
{
return duint(ThreadGetId(hActiveThread));
}
duint kusd()
{
return duint(SharedUserData);
}
duint bswap(duint value)
{
duint result = 0;
for(size_t i = 0; i < sizeof(value); i++)
((unsigned char*)&result)[sizeof(value) - i - 1] = ((unsigned char*)&value)[i];
return result;
}
duint ternary(duint condition, duint value1, duint value2)
{
return condition ? value1 : value2;
}
duint memvalid(duint addr)
{
return MemIsValidReadPtr(addr, true);
}
duint membase(duint addr)
{
return MemFindBaseAddr(addr, nullptr);
}
duint memsize(duint addr)
{
duint size;
return MemFindBaseAddr(addr, &size) ? size : 0;
}
duint memiscode(duint addr)
{
return MemIsCodePage(addr, false);
}
duint memisstring(duint addr)
{
STRING_TYPE strType;
disasmispossiblestring(addr, &strType);
if(strType != STRING_TYPE::str_none)
return strType == STRING_TYPE::str_unicode ? 2 : 1;
else
return 0;
}
duint memdecodepointer(duint ptr)
{
auto decoded = ptr;
return MemDecodePointer(&decoded, IsVistaOrLater()) ? decoded : ptr;
}
duint dislen(duint addr)
{
BASIC_INSTRUCTION_INFO info;
return disasmfast(addr, &info, true) ? info.size : 0;
}
duint disiscond(duint addr)
{
BASIC_INSTRUCTION_INFO info;
if(!disasmfast(addr, &info, true))
return 0;
return info.branch && !info.call && !::strstr(info.instruction, "jmp");
}
duint disisbranch(duint addr)
{
BASIC_INSTRUCTION_INFO info;
if(!disasmfast(addr, &info, true))
return 0;
return info.branch;
}
duint disisret(duint addr)
{
BASIC_INSTRUCTION_INFO info;
if(!disasmfast(addr, &info, true))
return 0;
return ::strstr(info.instruction, "ret") != nullptr;
}
duint disiscall(duint addr)
{
BASIC_INSTRUCTION_INFO info;
if(!disasmfast(addr, &info, true))
return 0;
return info.call;
}
duint disismem(duint addr)
{
BASIC_INSTRUCTION_INFO info;
if(!disasmfast(addr, &info, true))
return 0;
return (info.type & TYPE_MEMORY) == TYPE_MEMORY;
}
duint disisnop(duint addr)
{
unsigned char data[16];
if(MemRead(addr, data, sizeof(data), nullptr, true))
{
Zydis cp;
if(cp.Disassemble(addr, data))
return cp.IsNop();
}
return false;
}
duint disisunusual(duint addr)
{
unsigned char data[16];
if(MemRead(addr, data, sizeof(data), nullptr, true))
{
Zydis cp;
if(cp.Disassemble(addr, data))
return cp.IsUnusual();
}
return false;
}
duint disbranchdest(duint addr)
{
return DbgGetBranchDestination(addr);
}
duint disbranchexec(duint addr)
{
return DbgIsJumpGoingToExecute(addr);
}
duint disimm(duint addr)
{
BASIC_INSTRUCTION_INFO info;
if(!disasmfast(addr, &info, true))
return 0;
return info.value.value;
}
duint disbrtrue(duint addr)
{
BASIC_INSTRUCTION_INFO info;
if(!disasmfast(addr, &info, true))
return 0;
return info.branch ? info.addr : 0;
}
duint disbrfalse(duint addr)
{
BASIC_INSTRUCTION_INFO info;
if(!disasmfast(addr, &info, true))
return 0;
return info.branch && !::strstr(info.instruction, "jmp") ? addr + info.size : 0;
}
duint disnext(duint addr)
{
BASIC_INSTRUCTION_INFO info;
if(!disasmfast(addr, &info, true))
return 0;
return addr + info.size;
}
duint disprev(duint addr)
{
duint size = 0;
duint base = MemFindBaseAddr(addr, &size);
duint readStart = addr - 16 * 4;
if(readStart < base)
readStart = base;
unsigned char disasmData[256];
MemRead(readStart, disasmData, sizeof(disasmData));
return readStart + disasmback(disasmData, 0, sizeof(disasmData), addr - readStart, 1);
}
duint disiscallsystem(duint addr)
{
duint dest = disbranchdest(addr);
return dest && (modsystem(dest) || modsystem(disbranchdest(dest)));
}
bool dismnemonic(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata)
{
assert(argc == 1);
assert(argv[0].type == ValueTypeNumber);
String mnemonic = "???";
auto addr = argv[0].number;
unsigned char data[MAX_DISASM_BUFFER];
if(MemRead(addr, data, sizeof(data)))
{
Zydis dis;
if(dis.Disassemble(addr, data))
{
mnemonic = dis.Mnemonic();
}
}
*result = ValueString(mnemonic);
return true;
}
bool distext(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata)
{
assert(argc == 1);
assert(argv[0].type == ValueTypeNumber);
std::string text = "???";
auto addr = argv[0].number;
unsigned char data[MAX_DISASM_BUFFER];
if(MemRead(addr, data, sizeof(data)))
{
Zydis dis;
if(dis.Disassemble(addr, data))
{
text = dis.InstructionText();
}
}
*result = ValueString(text);
return true;
}
bool dismatch(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata)
{
assert(argc == 2);
assert(argv[0].type == ValueTypeNumber);
assert(argv[1].type == ValueTypeString);
bool matched = false;
auto addr = argv[0].number;
unsigned char data[MAX_DISASM_BUFFER];
if(MemRead(addr, data, sizeof(data)))
{
Zydis dis;
if(dis.Disassemble(addr, data))
{
auto text = dis.InstructionText();
std::smatch m;
std::regex re(argv[1].string.ptr);
matched = std::regex_search(text, m, re);
}
}
*result = ValueNumber(matched);
return true;
}
duint trenabled(duint addr)
{
return TraceRecord.getTraceRecordType(addr) != TraceRecordManager::TraceRecordNone;
}
duint trhitcount(duint addr)
{
return trenabled(addr) ? TraceRecord.getHitCount(addr) : 0;
}
duint trisrecording()
{
return TraceRecord.isTraceRecordingEnabled() ? 1 : 0;
}
duint gettickcount()
{
#ifdef _WIN64
static auto GTC64 = (duint(*)())GetProcAddress(GetModuleHandleW(L"kernel32.dll"), "GetTickCount64");
if(GTC64)
return GTC64();
#endif //_WIN64
return GetTickCount();
}
duint rdtsc()
{
return __rdtsc();
}
static duint readMem(duint addr, duint size)
{
duint value = 0;
return MemRead(addr, &value, size) ? value : 0;
}
duint readbyte(duint addr)
{
return readMem(addr, 1);
}
duint readword(duint addr)
{
return readMem(addr, 2);
}
duint readdword(duint addr)
{
return readMem(addr, 4);
}
duint readqword(duint addr)
{
return readMem(addr, 8);
}
duint readptr(duint addr)
{
return readMem(addr, sizeof(duint));
}
duint funcstart(duint addr)
{
duint start;
return FunctionGet(addr, &start) ? start : 0;
}
duint funcend(duint addr)
{
duint end;
return FunctionGet(addr, nullptr, &end) ? end : 0;
}
duint refcount()
{
return GuiReferenceGetRowCount();
}
duint refaddr(duint row)
{
auto content = GuiReferenceGetCellContent(int(row), 0);
duint addr = 0;
valfromstring(content, &addr, false);
BridgeFree(content);
return addr;
}
duint refsearchcount()
{
return GuiReferenceSearchGetRowCount();
}
duint refsearchaddr(duint row)
{
auto content = GuiReferenceSearchGetCellContent(int(row), 0);
duint addr = 0;
valfromstring(content, &addr, false);
BridgeFree(content);
return addr;
}
static String argExpr(duint index)
{
#ifdef _WIN64
//http://msdn.microsoft.com/en-us/library/windows/hardware/ff561499(v=vs.85).aspx
switch(index)
{
case 0:
return "rcx";
case 1:
return "rdx";
case 2:
return "r8";
case 3:
return "r9";
default:
break;
}
#endif
return StringUtils::sprintf("[csp+%X]", int32_t(++index * sizeof(duint)));
}
duint argget(duint index)
{
duint value = 0;
valfromstring(argExpr(index).c_str(), &value);
return value;
}
duint argset(duint index, duint value)
{
auto expr = argExpr(index);
duint oldvalue = 0;
valfromstring(expr.c_str(), &oldvalue);
valtostring(expr.c_str(), value, true);
return oldvalue;
}
duint bpgoto(duint cip)
{
//This is a function to sets CIP without calling DebugUpdateGui. This is a workaround for "bpgoto".
SetContextDataEx(hActiveThread, UE_CIP, cip);
return cip;
}
duint exfirstchance()
{
return getLastExceptionInfo().dwFirstChance;
}
duint exaddr()
{
return (duint)getLastExceptionInfo().ExceptionRecord.ExceptionAddress;
}
duint excode()
{
return getLastExceptionInfo().ExceptionRecord.ExceptionCode;
}
duint exflags()
{
return getLastExceptionInfo().ExceptionRecord.ExceptionFlags;
}
duint exinfocount()
{
return getLastExceptionInfo().ExceptionRecord.NumberParameters;
}
duint exinfo(duint index)
{
if(index >= EXCEPTION_MAXIMUM_PARAMETERS)
return 0;
return getLastExceptionInfo().ExceptionRecord.ExceptionInformation[index];
}
duint isprocessfocused(DWORD process)
{
HWND foreground = GetForegroundWindow();
if(foreground)
{
DWORD pid;
DWORD tid = GetWindowThreadProcessId(foreground, &pid);
return pid == process;
}
else
return 0;
}
duint isdebuggerfocused()
{
return isprocessfocused(GetCurrentProcessId());
}
duint isdebuggeefocused()
{
if(!DbgIsDebugging())
return 0;
return isprocessfocused(fdProcessInfo->dwProcessId);
}
bool streq(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata)
{
assert(argc == 2);
assert(argv[0].type == ValueTypeString);
assert(argv[1].type == ValueTypeString);
*result = ValueNumber(::strcmp(argv[0].string.ptr, argv[1].string.ptr) == 0);
return true;
}
bool strieq(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata)
{
assert(argc == 2);
assert(argv[0].type == ValueTypeString);
assert(argv[1].type == ValueTypeString);
*result = ValueNumber(::_stricmp(argv[0].string.ptr, argv[1].string.ptr) == 0);
return true;
}
bool strstr(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata)
{
assert(argc == 2);
assert(argv[0].type == ValueTypeString);
assert(argv[1].type == ValueTypeString);
*result = ValueNumber(::strstr(argv[0].string.ptr, argv[1].string.ptr) != nullptr);
return true;
}
bool stristr(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata)
{
assert(argc == 2);
assert(argv[0].type == ValueTypeString);
assert(argv[1].type == ValueTypeString);
size_t len1 = ::strlen(argv[0].string.ptr);
size_t len2 = ::strlen(argv[1].string.ptr);
auto it = std::search(
argv[0].string.ptr, argv[0].string.ptr + len1,
argv[1].string.ptr, argv[1].string.ptr + len2,
[](char ch1, char ch2) { return std::toupper(ch1) == std::toupper(ch2); }
);
*result = ValueNumber(it != argv[0].string.ptr + len1);
return true;
}
bool strlen(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata)
{
assert(argc == 1);
assert(argv[0].type == ValueTypeString);
*result = ValueNumber(::strlen(argv[0].string.ptr));
return true;
}
template<bool Strict>
bool ansi(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata)
{
assert(argc == 1);
assert(argv[0].type == ValueTypeNumber);
duint addr = argv[0].number;
std::vector<char> tempStr(MAX_STRING_SIZE + 1);
duint NumberOfBytesRead = 0;
if(!MemRead(addr, tempStr.data(), tempStr.size() - 1, &NumberOfBytesRead) && NumberOfBytesRead == 0 && Strict)
{
return false;
}
*result = ValueString(StringUtils::LocalCpToUtf8(tempStr.data()));
return true;
}
template<bool Strict>
bool utf8(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata)
{
assert(argc == 1);
assert(argv[0].type == ValueTypeNumber);
duint addr = argv[0].number;
std::vector<char> tempStr(MAX_STRING_SIZE + 1);
duint NumberOfBytesRead = 0;
if(!MemRead(addr, tempStr.data(), tempStr.size() - 1, &NumberOfBytesRead) && NumberOfBytesRead == 0 && Strict)
{
return false;
}
*result = ValueString(tempStr.data());
return true;
}
template<bool Strict>
bool utf16(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata)
{
assert(argc == 1);
assert(argv[0].type == ValueTypeNumber);
duint addr = argv[0].number;
std::vector<wchar_t> tempStr(MAX_STRING_SIZE + 1);
duint NumberOfBytesRead = 0;
if(!MemRead(addr, tempStr.data(), sizeof(wchar_t) * (tempStr.size() - 1), &NumberOfBytesRead) && NumberOfBytesRead == 0 && Strict)
{
return false;
}
auto utf8Str = StringUtils::Utf16ToUtf8(tempStr.data());
if(utf8Str.empty() && wcslen(tempStr.data()) > 0)
{
return false;
}
*result = ValueString(utf8Str);
return true;
}
bool ansi(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata)
{
return ansi<false>(result, argc, argv, userdata);
}
bool ansi_strict(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata)
{
return ansi<true>(result, argc, argv, userdata);
}
bool utf8(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata)
{
return utf8<false>(result, argc, argv, userdata);
}
bool utf8_strict(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata)
{
return utf8<true>(result, argc, argv, userdata);
}
bool utf16(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata)
{
return utf16<false>(result, argc, argv, userdata);
}
bool utf16_strict(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata)
{
return utf16<true>(result, argc, argv, userdata);
}
} |
C/C++ | x64dbg-development/src/dbg/exprfunc.h | #pragma once
#include "_global.h"
#include "expressionfunctions.h"
namespace Exprfunc
{
duint srcline(duint addr);
duint srcdisp(duint addr);
duint modparty(duint addr);
duint modsystem(duint addr);
duint moduser(duint addr);
duint modrva(duint addr);
duint modheaderva(duint addr);
duint modisexport(duint addr);
bool modbasefromname(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata);
duint disasmsel();
duint dumpsel();
duint stacksel();
duint peb();
duint teb();
duint tid();
duint kusd();
duint bswap(duint value);
duint ternary(duint condition, duint value1, duint value2);
duint memvalid(duint addr);
duint membase(duint addr);
duint memsize(duint addr);
duint memiscode(duint addr);
duint memisstring(duint addr);
duint memdecodepointer(duint ptr);
duint dislen(duint addr);
duint disiscond(duint addr);
duint disisbranch(duint addr);
duint disisret(duint addr);
duint disiscall(duint addr);
duint disismem(duint addr);
duint disisnop(duint addr);
duint disisunusual(duint addr);
duint disbranchdest(duint addr);
duint disbranchexec(duint addr);
duint disimm(duint addr);
duint disbrtrue(duint addr);
duint disbrfalse(duint addr);
duint disnext(duint addr);
duint disprev(duint addr);
duint disiscallsystem(duint addr);
bool dismnemonic(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata);
bool distext(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata);
bool dismatch(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata);
duint trenabled(duint addr);
duint trhitcount(duint addr);
duint trisrecording();
duint gettickcount();
duint rdtsc();
duint readbyte(duint addr);
duint readword(duint addr);
duint readdword(duint addr);
duint readqword(duint addr);
duint readptr(duint addr);
duint funcstart(duint addr);
duint funcend(duint addr);
duint refcount();
duint refaddr(duint row);
duint refsearchcount();
duint refsearchaddr(duint row);
duint argget(duint index);
duint argset(duint index, duint value);
duint bpgoto(duint cip);
duint exfirstchance();
duint exaddr();
duint excode();
duint exflags();
duint exinfocount();
duint exinfo(duint index);
duint isdebuggerfocused();
duint isdebuggeefocused();
bool streq(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata);
bool strieq(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata);
bool strstr(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata);
bool stristr(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata);
bool strlen(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata);
bool ansi(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata);
bool ansi_strict(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata);
bool utf8(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata);
bool utf8_strict(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata);
bool utf16(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata);
bool utf16_strict(ExpressionValue* result, int argc, const ExpressionValue* argv, void* userdata);
} |
C++ | x64dbg-development/src/dbg/filehelper.cpp | #include "filehelper.h"
#include "handle.h"
#include "stringutils.h"
bool FileHelper::ReadAllData(const String & fileName, std::vector<unsigned char> & content)
{
if(fileName.compare("x64dbg://localhost/clipboard") != 0)
{
Handle hFile = CreateFileW(StringUtils::Utf8ToUtf16(fileName).c_str(), GENERIC_READ, FILE_SHARE_READ, nullptr, OPEN_EXISTING, 0, nullptr);
if(hFile == INVALID_HANDLE_VALUE)
return false;
unsigned int filesize = GetFileSize(hFile, nullptr);
if(!filesize)
{
content.clear();
return true;
}
content.resize(filesize);
DWORD read = 0;
return !!ReadFile(hFile, content.data(), filesize, &read, nullptr);
}
else
{
if(!OpenClipboard(0))
return false;
HANDLE hData;
hData = GetClipboardData(CF_UNICODETEXT);
if(hData == NULL)
{
CloseClipboard();
return false;
}
wchar_t* wideString = reinterpret_cast<wchar_t*>(GlobalLock(hData));
if(wideString == nullptr)
{
CloseClipboard();
return false;
}
String text = StringUtils::Utf16ToUtf8(wideString);
GlobalUnlock(hData);
CloseClipboard();
content.resize(text.size());
memcpy(content.data(), text.c_str(), text.size());
return true;
}
}
bool FileHelper::WriteAllData(const String & fileName, const void* data, size_t size)
{
Handle hFile = CreateFileW(StringUtils::Utf8ToUtf16(fileName).c_str(), GENERIC_WRITE, 0, nullptr, CREATE_ALWAYS, 0, nullptr);
if(hFile == INVALID_HANDLE_VALUE)
return false;
DWORD written = 0;
return !!WriteFile(hFile, data, DWORD(size), &written, nullptr);
}
bool FileHelper::ReadAllText(const String & fileName, String & content)
{
std::vector<unsigned char> data;
if(!ReadAllData(fileName, data))
return false;
data.push_back(0);
content = String((const char*)data.data());
return true;
}
bool FileHelper::WriteAllText(const String & fileName, const String & content)
{
return WriteAllData(fileName, content.c_str(), content.length());
}
bool FileHelper::ReadAllLines(const String & fileName, std::vector<String> & lines, bool keepEmpty)
{
String content;
if(!ReadAllText(fileName, content))
return false;
lines.clear();
String line;
for(auto ch : content)
{
switch(ch)
{
case '\r':
break;
case '\n':
if(line.length() || keepEmpty)
lines.push_back(line);
line.clear();
break;
default:
line.resize(line.length() + 1);
line[line.length() - 1] = ch;
break;
}
}
if(line.length())
lines.push_back(line);
return true;
}
String FileHelper::GetFileName(const String & fileName)
{
auto last = strrchr(fileName.c_str(), '\\');
return last ? last + 1 : fileName;
} |
C/C++ | x64dbg-development/src/dbg/filehelper.h | #ifndef _FILEREADER_H
#define _FILEREADER_H
#include "_global.h"
class FileHelper
{
public:
static bool ReadAllData(const String & fileName, std::vector<unsigned char> & content);
static bool WriteAllData(const String & fileName, const void* data, size_t size);
static bool ReadAllText(const String & fileName, String & content);
static bool WriteAllText(const String & fileName, const String & content);
static bool ReadAllLines(const String & fileName, std::vector<String> & lines, bool keepEmpty = false);
static String GetFileName(const String & fileName);
};
#endif //_FILEREADER_H |
C/C++ | x64dbg-development/src/dbg/filemap.h | #pragma once
#include <Windows.h>
template<typename T>
struct FileMap
{
bool Map(const wchar_t* szFileName, bool mapImage = false)
{
hFile = CreateFileW(szFileName, GENERIC_READ, FILE_SHARE_READ, nullptr, OPEN_EXISTING, 0, nullptr);
if(hFile != INVALID_HANDLE_VALUE)
{
size = GetFileSize(hFile, nullptr);
hMap = CreateFileMappingW(hFile, nullptr, PAGE_READONLY | (mapImage ? SEC_IMAGE : 0), 0, 0, nullptr);
if(hMap)
data = (const T*)MapViewOfFile(hMap, FILE_MAP_READ, 0, 0, 0);
}
return data != nullptr;
}
unsigned int Size()
{
return size;
}
const T* Data()
{
return data;
}
void Unmap()
{
if(data)
UnmapViewOfFile(data);
if(hMap)
CloseHandle(hMap);
if(hFile != INVALID_HANDLE_VALUE)
CloseHandle(hFile);
hFile = INVALID_HANDLE_VALUE;
hMap = nullptr;
data = nullptr;
size = 0;
}
~FileMap()
{
Unmap();
}
private:
HANDLE hFile = INVALID_HANDLE_VALUE;
HANDLE hMap = nullptr;
const T* data = nullptr;
unsigned int size = 0;
};
struct BufferedWriter
{
explicit BufferedWriter(HANDLE hFile, size_t size = 65536)
: hFile(hFile),
mBuffer(new char[size]),
mSize(size),
mIndex(0)
{
memset(mBuffer, 0, size);
}
bool Write(const void* buffer, size_t size)
{
for(size_t i = 0; i < size; i++)
{
mBuffer[mIndex++] = ((const char*)buffer)[i];
if(mIndex == mSize)
{
if(!flush())
return false;
mIndex = 0;
}
}
return true;
}
~BufferedWriter()
{
flush();
delete[] mBuffer;
CloseHandle(hFile);
}
private:
HANDLE hFile;
char* mBuffer;
size_t mSize;
size_t mIndex;
bool flush()
{
if(!mIndex)
return true;
DWORD written;
auto result = WriteFile(hFile, mBuffer, DWORD(mIndex), &written, nullptr);
mIndex = 0;
return !!result;
}
}; |
C++ | x64dbg-development/src/dbg/formatfunctions.cpp | #include "formatfunctions.h"
#include "threading.h"
#include "value.h"
#include "memory.h"
#include "exception.h"
#include "ntdll/ntdll.h"
#include "disasm_fast.h"
std::unordered_map<String, FormatFunctions::Function> FormatFunctions::mFunctions;
static FORMATRESULT formatErrorMsg(HMODULE DLL, const String & errName, DWORD code, char* dest, size_t destCount)
{
const NTSTATUS ErrorStatus = code;
PMESSAGE_RESOURCE_ENTRY Entry;
NTSTATUS Status = RtlFindMessage(DLL,
LDR_FORMAT_MESSAGE_FROM_SYSTEM_MESSAGE_TABLE,
MAKELANGID(LANG_NEUTRAL, SUBLANG_DEFAULT),
ErrorStatus,
&Entry);
if(!NT_SUCCESS(Status))
{
if(destCount < errName.size() + 1)
return FORMAT_BUFFER_TOO_SMALL;
else
{
memcpy(dest, errName.c_str(), errName.size() + 1);
return FORMAT_SUCCESS;
}
}
if((Entry->Flags & MESSAGE_RESOURCE_UNICODE) != 0)
{
String UTF8Description = StringUtils::TrimRight(StringUtils::Utf16ToUtf8((const wchar_t*)Entry->Text));
if(UTF8Description.size() + 3 + errName.size() > destCount)
return FORMAT_BUFFER_TOO_SMALL;
else
{
sprintf_s(dest, destCount, "%s: %s", errName.c_str(), UTF8Description.c_str());
return FORMAT_SUCCESS;
}
}
else
{
String UTF8Description = StringUtils::TrimRight(StringUtils::LocalCpToUtf8((const char*)Entry->Text));
if(UTF8Description.size() + 3 + errName.size() > destCount)
return FORMAT_BUFFER_TOO_SMALL;
else
{
sprintf_s(dest, destCount, "%s: %s", errName.c_str(), UTF8Description.c_str());
return FORMAT_SUCCESS;
}
}
}
template<class Char, size_t DefaultSize = 0>
static FORMATRESULT memoryFormatter(char* dest, size_t destCount, int argc, char* argv[], duint addr, const std::function<String(std::vector<Char>&)> & format)
{
duint size = DefaultSize;
if(argc > 1 && !valfromstring(argv[1], &size))
{
strcpy_s(dest, destCount, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Invalid argument...")));
return FORMAT_ERROR_MESSAGE;
}
if(size == 0)
{
strcpy_s(dest, destCount, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Not enough arguments...")));
return FORMAT_ERROR_MESSAGE;
}
if(size > 1024 * 1024 * 10) //10MB max
{
strcpy_s(dest, destCount, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Too much data (10MB max)...")));
return FORMAT_ERROR_MESSAGE;
}
std::vector<Char> data(size);
duint read = 0;
if(!MemRead(addr, data.data(), size * sizeof(Char), &read) && read == 0)
{
strcpy_s(dest, destCount, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Failed to read memory...")));
return FORMAT_ERROR_MESSAGE;
}
data.resize(read);
auto result = format(data);
if(result.size() > destCount)
return FORMAT_BUFFER_TOO_SMALL;
strcpy_s(dest, destCount, result.c_str());
return FORMAT_SUCCESS;
}
static FORMATRESULT formatcpy_s(char* dest, size_t destCount, const char* source)
{
switch(strncpy_s(dest, destCount, source, _TRUNCATE))
{
case 0:
return FORMAT_SUCCESS;
case ERANGE:
case STRUNCATE:
return FORMAT_BUFFER_TOO_SMALL;
default:
return FORMAT_ERROR;
}
}
void FormatFunctions::Init()
{
Register("mem", [](char* dest, size_t destCount, int argc, char* argv[], duint addr, void* userdata)
{
return memoryFormatter<unsigned char>(dest, destCount, argc, argv, addr, [](std::vector<unsigned char> & data)
{
return StringUtils::ToHex(data.data(), data.size());
});
});
Register("ascii", [](char* dest, size_t destCount, int argc, char* argv[], duint addr, void* userdata)
{
return memoryFormatter<unsigned char, 512>(dest, destCount, argc, argv, addr, [](std::vector<unsigned char> & data)
{
String result;
result.reserve(data.size());
for(auto & ch : data)
{
if(isprint(ch))
result.push_back(char(ch));
else
result.push_back('?');
}
return result;
});
});
Register("ansi", [](char* dest, size_t destCount, int argc, char* argv[], duint addr, void* userdata)
{
return memoryFormatter<char, 512>(dest, destCount, argc, argv, addr, [](std::vector<char> & data)
{
if(data.empty() || data.back() != '\0')
data.push_back('\0');
return StringUtils::LocalCpToUtf8(data.data());
});
});
Register("utf8", [](char* dest, size_t destCount, int argc, char* argv[], duint addr, void* userdata)
{
return memoryFormatter<char, 512>(dest, destCount, argc, argv, addr, [](std::vector<char> & data)
{
if(data.empty() || data.back() != '\0')
data.push_back('\0');
return String(data.data());
});
});
Register("utf16", [](char* dest, size_t destCount, int argc, char* argv[], duint addr, void* userdata)
{
return memoryFormatter<wchar_t, 512>(dest, destCount, argc, argv, addr, [](std::vector<wchar_t> & data)
{
if(data.empty() || data.back() != L'\0')
data.push_back(L'\0');
return StringUtils::Utf16ToUtf8(data.data());
});
});
Register("winerror", [](char* dest, size_t destCount, int argc, char* argv[], duint code, void* userdata)
{
std::vector<wchar_t> helpMessage(destCount);
String errName = ErrorCodeToName((unsigned int)code);
#ifdef _WIN64
if((code >> 32) != 0) //Data in high part: not an error code
{
errName = StringUtils::sprintf("%p", code);
if(destCount < errName.size() + 1)
return FORMAT_BUFFER_TOO_SMALL;
else
{
memcpy(dest, errName.c_str(), errName.size() + 1);
return FORMAT_SUCCESS;
}
}
#endif //_WIN64
if(errName.size() == 0)
errName = StringUtils::sprintf("%08X", DWORD(code));
return formatErrorMsg(GetModuleHandleW(L"kernel32.dll"), errName, DWORD(code), dest, destCount);
});
Register("ntstatus", [](char* dest, size_t destCount, int argc, char* argv[], duint code, void* userdata)
{
std::vector<wchar_t> helpMessage(destCount);
String errName = NtStatusCodeToName((unsigned int)code);
if(errName.size() == 0)
errName = StringUtils::sprintf("%08X", DWORD(code));
return formatErrorMsg(GetModuleHandleW(L"ntdll.dll"), errName, DWORD(code), dest, destCount);
});
Register("disasm", [](char* dest, size_t destCount, int argc, char* argv[], duint addr, void* userdata)
{
const char* result = nullptr;
BASIC_INSTRUCTION_INFO info;
if(!disasmfast(addr, &info, true))
result = "???";
else
result = info.instruction;
return formatcpy_s(dest, destCount, result);
});
Register("modname", [](char* dest, size_t destCount, int argc, char* argv[], duint addr, void* userdata)
{
char mod[MAX_MODULE_SIZE] = "";
if(!ModNameFromAddr(addr, mod, true))
return FORMAT_ERROR;
return formatcpy_s(dest, destCount, mod);
});
Register("bswap", [](char* dest, size_t destCount, int argc, char* argv[], duint addr, void* userdata)
{
duint size = sizeof(duint);
if(argc > 1 && !valfromstring(argv[1], &size))
{
strcpy_s(dest, destCount, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Invalid argument...")));
return FORMAT_ERROR_MESSAGE;
}
if(size > sizeof(duint) || size == 0)
{
strcpy_s(dest, destCount, GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Invalid size...")));
return FORMAT_ERROR_MESSAGE;
}
auto data = (unsigned char*)&addr;
String result;
for(duint i = 0; i < size; i++)
result += StringUtils::sprintf("%02X", data[i]);
return formatcpy_s(dest, destCount, result.c_str());
});
Register("comment", [](char* dest, size_t destCount, int argc, char* argv[], duint addr, void* userdata)
{
char comment[MAX_COMMENT_SIZE] = "";
if(DbgGetCommentAt(addr, comment))
{
if(comment[0] == '\1') //automatic comment
return formatcpy_s(dest, destCount, comment + 1);
else
return formatcpy_s(dest, destCount, comment);
}
return FORMAT_ERROR;
});
Register("label", [](char* dest, size_t destCount, int argc, char* argv[], duint addr, void* userdata)
{
char label[MAX_LABEL_SIZE] = "";
if(DbgGetLabelAt(addr, SEG_DEFAULT, label))
return formatcpy_s(dest, destCount, label);
return FORMAT_ERROR;
});
}
bool FormatFunctions::Register(const String & type, const CBFORMATFUNCTION & cbFunction, void* userdata)
{
if(!isValidName(type))
return false;
EXCLUSIVE_ACQUIRE(LockFormatFunctions);
if(mFunctions.count(type))
return false;
Function f;
f.type = type;
f.cbFunction = cbFunction;
f.userdata = userdata;
mFunctions[type] = f;
return true;
}
bool FormatFunctions::RegisterAlias(const String & name, const String & alias)
{
EXCLUSIVE_ACQUIRE(LockFormatFunctions);
auto found = mFunctions.find(name);
if(found == mFunctions.end())
return false;
if(!Register(alias, found->second.cbFunction, found->second.userdata))
return false;
found->second.aliases.push_back(alias);
return true;
}
bool FormatFunctions::Unregister(const String & name)
{
EXCLUSIVE_ACQUIRE(LockFormatFunctions);
auto found = mFunctions.find(name);
if(found == mFunctions.end())
return false;
auto aliases = found->second.aliases;
mFunctions.erase(found);
for(const auto & alias : found->second.aliases)
Unregister(alias);
return true;
}
bool FormatFunctions::Call(std::vector<char> & dest, const String & type, std::vector<String> & argv, duint value)
{
SHARED_ACQUIRE(LockFormatFunctions);
auto found = mFunctions.find(type);
if(found == mFunctions.end())
return false;
std::vector<char*> argvn(argv.size());
for(size_t i = 0; i < argv.size(); i++)
argvn[i] = (char*)argv[i].c_str();
const auto & f = found->second;
dest.resize(512, '\0');
fuckthis:
auto result = f.cbFunction(dest.data(), dest.size() - 1, int(argv.size()), argvn.data(), value, f.userdata);
if(result == FORMAT_BUFFER_TOO_SMALL)
{
dest.resize(dest.size() * 2, '\0');
goto fuckthis;
}
return result != FORMAT_ERROR;
}
bool FormatFunctions::isValidName(const String & name)
{
if(!name.length())
return false;
if(!(name[0] == '_' || isalpha(name[0])))
return false;
for(const auto & ch : name)
if(!(isalnum(ch) || ch == '_' || ch == '.'))
return false;
return true;
} |
C/C++ | x64dbg-development/src/dbg/formatfunctions.h | #pragma once
#include "_global.h"
#include "_plugins.h"
#include <functional>
class FormatFunctions
{
public:
using CBFORMATFUNCTION = std::function<FORMATRESULT(char* dest, size_t destCount, int argc, char* argv[], duint value, void* userdata)>;
static void Init();
static bool Register(const String & type, const CBFORMATFUNCTION & cbFunction, void* userdata = nullptr);
static bool RegisterAlias(const String & type, const String & alias);
static bool Unregister(const String & type);
static bool Call(std::vector<char> & dest, const String & type, std::vector<String> & argv, duint value);
private:
struct Function
{
String type;
CBFORMATFUNCTION cbFunction;
void* userdata = nullptr;
std::vector<String> aliases;
};
static bool isValidName(const String & name);
static std::unordered_map<String, Function> mFunctions;
}; |
C++ | x64dbg-development/src/dbg/function.cpp | #include "function.h"
#include "module.h"
#include "memory.h"
#include "threading.h"
struct FunctionSerializer : JSONWrapper<FUNCTIONSINFO>
{
bool Save(const FUNCTIONSINFO & value) override
{
setString("module", value.mod());
setHex("start", value.start);
setHex("end", value.end);
setHex("icount", value.instructioncount);
setBool("manual", value.manual);
setHex("parent", value.parent);
return true;
}
bool Load(FUNCTIONSINFO & value) override
{
//legacy support
value.manual = true;
getBool("manual", value.manual);
std::string mod;
if(!getString("module", mod))
return false;
value.modhash = ModHashFromName(mod.c_str());
value.parent = 0;
getHex("parent", value.parent);
return getHex("start", value.start) &&
getHex("end", value.end) &&
getHex("icount", value.instructioncount) &&
value.end >= value.start;
}
};
struct Functions : SerializableModuleRangeMap<LockFunctions, FUNCTIONSINFO, FunctionSerializer>
{
void AdjustValue(FUNCTIONSINFO & value) const override
{
auto base = ModBaseFromName(value.mod().c_str());
value.start += base;
value.end += base;
value.parent += base;
}
protected:
const char* jsonKey() const override
{
return "functions";
}
ModuleRange makeKey(const FUNCTIONSINFO & value) const override
{
return ModuleRange(value.modhash, Range(value.start, value.end));
}
};
static Functions functions;
bool FunctionAdd(duint Start, duint End, bool Manual, duint InstructionCount, duint Parent)
{
// Make sure memory is readable
if(!MemIsValidReadPtr(Start))
return false;
// Fail if boundary exceeds module size
auto moduleBase = ModBaseFromAddr(Start);
if(moduleBase != ModBaseFromAddr(End))
return false;
// Fail if 'Start' and 'End' are incompatible
if(Start > End || FunctionOverlaps(Start, End))
return false;
FUNCTIONSINFO function;
function.modhash = ModHashFromAddr(moduleBase);
function.start = Start - moduleBase;
function.end = End - moduleBase;
function.manual = Manual;
function.instructioncount = InstructionCount;
function.parent = Parent ? Parent : Start;
function.parent -= moduleBase;
return functions.Add(function);
}
bool FunctionGet(duint Address, duint* Start, duint* End, duint* InstrCount, duint* Parent)
{
FUNCTIONSINFO function;
if(!functions.Get(Functions::VaKey(Address, Address), function))
return false;
functions.AdjustValue(function);
if(Start)
*Start = function.start;
if(End)
*End = function.end;
if(InstrCount)
*InstrCount = function.instructioncount;
if(Parent)
*Parent = function.parent;
return true;
}
bool FunctionOverlaps(duint Start, duint End)
{
// A function can't end before it begins
if(Start > End)
return false;
return functions.Contains(Functions::VaKey(Start, End));
}
bool FunctionDelete(duint Address)
{
return functions.Delete(Functions::VaKey(Address, Address));
}
void FunctionDelRange(duint Start, duint End, bool DeleteManual)
{
// Should all functions be deleted?
// 0x00000000 - 0xFFFFFFFF
if(Start == 0 && End == ~0)
{
FunctionClear();
}
else
{
// The start and end address must be in the same module
auto moduleBase = ModBaseFromAddr(Start);
if(moduleBase != ModBaseFromAddr(End))
return;
// Convert these to a relative offset
Start -= moduleBase;
End -= moduleBase;
functions.DeleteWhere([ = ](const FUNCTIONSINFO & value)
{
if(!DeleteManual && value.manual)
return false;
return value.end >= Start && value.start <= End;
});
}
}
void FunctionCacheSave(JSON Root)
{
functions.CacheSave(Root);
}
void FunctionCacheLoad(JSON Root)
{
functions.CacheLoad(Root);
functions.CacheLoad(Root, "auto"); //legacy support
}
bool FunctionEnum(FUNCTIONSINFO* List, size_t* Size)
{
return functions.Enum(List, Size);
}
void FunctionClear()
{
functions.Clear();
}
void FunctionGetList(std::vector<FUNCTIONSINFO> & list)
{
functions.GetList(list);
}
bool FunctionGetInfo(duint Address, FUNCTIONSINFO & info)
{
return functions.Get(Functions::VaKey(Address, Address), info);
} |
C/C++ | x64dbg-development/src/dbg/function.h | #ifndef _FUNCTION_H
#define _FUNCTION_H
#include "addrinfo.h"
struct FUNCTIONSINFO
{
duint modhash;
duint start;
duint end;
bool manual;
duint instructioncount;
duint parent;
std::string mod() const
{
return ModNameFromHash(modhash);
}
};
bool FunctionAdd(duint Start, duint End, bool Manual, duint InstructionCount = 0, duint Parent = 0);
bool FunctionGet(duint Address, duint* Start = nullptr, duint* End = nullptr, duint* InstrCount = nullptr, duint* Parent = nullptr);
bool FunctionOverlaps(duint Start, duint End);
bool FunctionDelete(duint Address);
void FunctionDelRange(duint Start, duint End, bool DeleteManual = false);
void FunctionCacheSave(JSON Root);
void FunctionCacheLoad(JSON Root);
bool FunctionEnum(FUNCTIONSINFO* List, size_t* Size);
void FunctionClear();
void FunctionGetList(std::vector<FUNCTIONSINFO> & list);
bool FunctionGetInfo(duint Address, FUNCTIONSINFO & info);
#endif // _FUNCTION_H |
C/C++ | x64dbg-development/src/dbg/GetPeArch.h | #pragma once
#include <windows.h>
enum class PeArch
{
Invalid,
Native86,
Native64,
Dotnet86,
Dotnet64,
DotnetAnyCpu,
DotnetAnyCpuPrefer32
};
// Thanks to blaquee for the investigative work!
static PeArch GetPeArch(const wchar_t* szFileName)
{
auto result = PeArch::Invalid;
auto hFile = CreateFileW(szFileName, GENERIC_READ, FILE_SHARE_READ, nullptr, OPEN_EXISTING, 0, nullptr);
if(hFile != INVALID_HANDLE_VALUE)
{
// SEC_IMAGE will load the file like the Windows loader would, saving us RVA -> File offset conversion crap.
auto hMappedFile = CreateFileMappingW(hFile, nullptr, PAGE_READONLY | SEC_IMAGE, 0, 0, nullptr);
if(hMappedFile)
{
auto fileMap = MapViewOfFile(hMappedFile, FILE_MAP_READ, 0, 0, 0);
if(fileMap)
{
__try
{
auto pidh = PIMAGE_DOS_HEADER(fileMap);
if(pidh->e_magic == IMAGE_DOS_SIGNATURE)
{
auto pnth = PIMAGE_NT_HEADERS(ULONG_PTR(fileMap) + pidh->e_lfanew);
if(pnth->Signature == IMAGE_NT_SIGNATURE)
{
auto Machine = pnth->FileHeader.Machine;
if(Machine == IMAGE_FILE_MACHINE_I386 || Machine == IMAGE_FILE_MACHINE_AMD64)
{
auto isDll = (pnth->FileHeader.Characteristics & IMAGE_FILE_DLL) == IMAGE_FILE_DLL;
auto isFile86 = Machine == IMAGE_FILE_MACHINE_I386;
// Set the native architecture of the PE file (to still have something to show for if the COM directory is invalid).
result = isFile86 ? PeArch::Native86 : PeArch::Native64;
// Get the address and size of the COM (.NET) directory.
ULONG_PTR comAddr = 0, comSize = 0;
if(isFile86) // x86
{
auto pnth32 = PIMAGE_NT_HEADERS32(pnth);
comAddr = pnth32->OptionalHeader.DataDirectory[IMAGE_DIRECTORY_ENTRY_COM_DESCRIPTOR].VirtualAddress;
comSize = pnth32->OptionalHeader.DataDirectory[IMAGE_DIRECTORY_ENTRY_COM_DESCRIPTOR].Size;
}
else // x64
{
auto pnth64 = PIMAGE_NT_HEADERS64(pnth);
comAddr = pnth64->OptionalHeader.DataDirectory[IMAGE_DIRECTORY_ENTRY_COM_DESCRIPTOR].VirtualAddress;
comSize = pnth64->OptionalHeader.DataDirectory[IMAGE_DIRECTORY_ENTRY_COM_DESCRIPTOR].Size;
}
// Check if the file has a (valid) COM (.NET) directory.
if(comAddr && comSize >= sizeof(IMAGE_COR20_HEADER))
{
// Find out which flavor of dotnet we're dealing with. Specifically,
// "Any CPU" can be compiled with two flavors, "Prefer 32 bit" or not.
// Without the 32bit preferred flag, the loader will load the .NET
// environment based on the current platforms bitness (x86 or x64)
// Class libraries (DLLs) cannot specify the "Prefer 32 bit".
// https://mega.nz/#!vx5nVILR!jLafWGWhhsC0Qo5fE-3oEIc-uHBcRpraOo8L_KlUeXI
// Binaries that do not have COMIMAGE_FLAGS_ILONLY appear to be executed
// in a process that matches their native type.
// https://github.com/x64dbg/x64dbg/issues/1758
auto pcorh = PIMAGE_COR20_HEADER(ULONG_PTR(fileMap) + comAddr);
if(pcorh->cb == sizeof(IMAGE_COR20_HEADER))
{
auto flags = pcorh->Flags;
#define test(x) (flags & x) == x
#define MY_COMIMAGE_FLAGS_32BITPREFERRED 0x00020000
if(isFile86) // x86
{
if(test(COMIMAGE_FLAGS_32BITREQUIRED))
result = !isDll && test(MY_COMIMAGE_FLAGS_32BITPREFERRED) ? PeArch::DotnetAnyCpuPrefer32 : PeArch::Dotnet86;
else if(test(COMIMAGE_FLAGS_ILONLY))
result = PeArch::DotnetAnyCpu;
else
result = PeArch::Dotnet86;
}
else // x64
result = PeArch::Dotnet64;
#undef MY_COMIMAGE_FLAGS_32BITPREFERRED
#undef test
}
}
}
}
}
}
__except(EXCEPTION_EXECUTE_HANDLER)
{
}
UnmapViewOfFile(fileMap);
}
CloseHandle(hMappedFile);
}
CloseHandle(hFile);
}
return result;
} |
C/C++ | x64dbg-development/src/dbg/handle.h | #ifndef _HANDLE_H
#define _HANDLE_H
#include <windows.h>
class Handle
{
public:
Handle(HANDLE h = nullptr) : mHandle(h) { }
Handle(const Handle &) = delete;
Handle(Handle &&) = delete;
~Handle()
{
Close();
}
void Close()
{
if(*this)
{
DWORD dwFlags = 0;
if(GetHandleInformation(mHandle, &dwFlags) && !(dwFlags & HANDLE_FLAG_PROTECT_FROM_CLOSE))
CloseHandle(mHandle);
mHandle = INVALID_HANDLE_VALUE;
}
}
operator HANDLE()
{
return mHandle;
}
explicit operator bool() const
{
return mHandle != nullptr && mHandle != INVALID_HANDLE_VALUE;
}
private:
HANDLE mHandle;
};
#endif //_HANDLE_H |
C++ | x64dbg-development/src/dbg/handles.cpp | #include <functional>
#include "handles.h"
#include "ntdll/ntdll.h"
#include "exception.h"
#include "debugger.h"
#include "thread.h"
#include "threading.h"
static std::unordered_map<UCHAR, String> HandleTypeNames;
static std::unordered_map<HANDLE, String> HandleTypeCache;
static void HandleTypesEnum()
{
Memory<POBJECT_TYPES_INFORMATION> TypesInformation(16 * 1024, "types");
NTSTATUS status = STATUS_SUCCESS;
for(;;)
{
status = NtQueryObject(nullptr, ObjectTypesInformation, TypesInformation(), ULONG(TypesInformation.size()), nullptr);
if(status != STATUS_INFO_LENGTH_MISMATCH)
break;
TypesInformation.realloc(TypesInformation.size() * 2, "types");
}
if(status != STATUS_SUCCESS)
return;
auto TypeInfo = TypesInformation()->TypeInformation;
for(ULONG i = 0; i < TypesInformation()->NumberOfTypes; i++)
{
auto wtypeName = WString(TypeInfo->TypeName.Buffer, TypeInfo->TypeName.Buffer + TypeInfo->TypeName.Length / 2);
auto typeName = StringUtils::Utf16ToUtf8(wtypeName);
auto typeIndex = i + 1;
if(BridgeGetNtBuildNumber() >= 9600 /* Windows 8.1 */)
{
typeIndex = TypeInfo->TypeIndex;
}
HandleTypeNames.emplace((UCHAR)typeIndex, typeName);
TypeInfo = (POBJECT_TYPE_INFORMATION)((char*)(TypeInfo + 1) + ALIGN_UP(TypeInfo->TypeName.MaximumLength, ULONG_PTR));
}
}
// Enumerate all handles in the debuggee
bool HandlesEnum(std::vector<HANDLEINFO> & handles)
{
if(HandleTypeNames.empty())
HandleTypesEnum();
duint pid;
Memory<PSYSTEM_HANDLE_INFORMATION> HandleInformation(16 * 1024, "_dbg_enumhandles");
NTSTATUS ErrorCode = ERROR_SUCCESS;
pid = fdProcessInfo->dwProcessId;
for(;;)
{
ErrorCode = NtQuerySystemInformation(SystemHandleInformation, HandleInformation(), ULONG(HandleInformation.size()), nullptr);
if(ErrorCode != STATUS_INFO_LENGTH_MISMATCH)
break;
HandleInformation.realloc(HandleInformation.size() * 2, "_dbg_enumhandles");
}
if(ErrorCode != STATUS_SUCCESS)
return false;
handles.reserve(HandleInformation()->NumberOfHandles);
EXCLUSIVE_ACQUIRE(LockHandleCache);
HandleTypeCache.clear();
HANDLEINFO info;
for(ULONG i = 0; i < HandleInformation()->NumberOfHandles; i++)
{
const auto & handle = HandleInformation()->Handles[i];
if(handle.UniqueProcessId != pid)
continue;
info.Handle = handle.HandleValue;
info.TypeNumber = handle.ObjectTypeIndex;
info.GrantedAccess = handle.GrantedAccess;
auto typeNameItr = HandleTypeNames.find(handle.ObjectTypeIndex);
if(typeNameItr != HandleTypeNames.end())
HandleTypeCache.emplace((HANDLE)handle.HandleValue, typeNameItr->second);
handles.push_back(info);
}
return true;
}
static DWORD WINAPI getNameThread(LPVOID lpParam)
{
(*(std::function<void()>*)lpParam)();
return 0;
}
static String getProcessName(DWORD PID)
{
wchar_t processName[MAX_PATH];
std::string processNameUtf8;
HANDLE hPIDProcess;
hPIDProcess = OpenProcess(PROCESS_QUERY_INFORMATION, FALSE, PID);
if(hPIDProcess != NULL)
{
if(GetProcessImageFileNameW(hPIDProcess, processName, _countof(processName)) > 0)
{
processNameUtf8 = StringUtils::Utf16ToUtf8(processName);
}
CloseHandle(hPIDProcess);
}
return processNameUtf8;
}
// Get the name of a handle of debuggee
bool HandlesGetName(HANDLE remoteHandle, String & name, String & typeName)
{
HANDLE hProcess = fdProcessInfo->hProcess;
HANDLE hLocalHandle;
if(DuplicateHandle(hProcess, remoteHandle, GetCurrentProcess(), &hLocalHandle, 0, FALSE, DUPLICATE_SAME_ACCESS)) //Needs privileges for PID/TID retrival
{
ULONG ReturnSize = 0;
if(NtQueryObject(hLocalHandle, ObjectTypeInformation, nullptr, 0, &ReturnSize) == STATUS_INFO_LENGTH_MISMATCH)
{
ReturnSize += 0x2000;
Memory<OBJECT_TYPE_INFORMATION*> objectTypeInfo(ReturnSize + sizeof(WCHAR) * 16, "_dbg_gethandlename:objectTypeInfo");
if(NtQueryObject(hLocalHandle, ObjectTypeInformation, objectTypeInfo(), ReturnSize, nullptr) == STATUS_SUCCESS)
typeName = StringUtils::Utf16ToUtf8(objectTypeInfo()->TypeName.Buffer);
}
std::function<void()> getName = [&]()
{
if(NtQueryObject(hLocalHandle, ObjectNameInformation, nullptr, 0, &ReturnSize) == STATUS_INFO_LENGTH_MISMATCH)
{
ReturnSize += 0x2000;
Memory<OBJECT_NAME_INFORMATION*> objectNameInfo(ReturnSize + sizeof(WCHAR) * 16, "_dbg_gethandlename:objectNameInfo");
if(NtQueryObject(hLocalHandle, ObjectNameInformation, objectNameInfo(), ReturnSize, nullptr) == STATUS_SUCCESS)
name = StringUtils::Utf16ToUtf8(objectNameInfo()->Name.Buffer);
}
};
name.clear();
if(strcmp(typeName.c_str(), "Process") == 0)
{
DWORD PID = GetProcessId(hLocalHandle); //Windows XP SP1
if(PID == 0) //The first time could fail because the process didn't specify query permissions.
{
HANDLE hLocalQueryHandle;
if(DuplicateHandle(hProcess, remoteHandle, GetCurrentProcess(), &hLocalQueryHandle, PROCESS_QUERY_INFORMATION, FALSE, 0))
{
PID = GetProcessId(hLocalQueryHandle);
CloseHandle(hLocalQueryHandle);
}
}
if(PID > 0)
{
if(PID == fdProcessInfo->dwProcessId)
{
name = StringUtils::sprintf("PID: %s (%s)", formatpidtid(PID).c_str(), GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Debuggee")));
}
else
{
std::string processName = getProcessName(PID);
if(processName.size() > 0)
name = StringUtils::sprintf("PID: %s (%s)", formatpidtid(PID).c_str(), processName.c_str());
else
name = StringUtils::sprintf("PID: %s", formatpidtid(PID).c_str());
}
}
}
else if(strcmp(typeName.c_str(), "Thread") == 0)
{
auto getTidPid = [](HANDLE hThread, DWORD & TID, DWORD & PID)
{
static auto pGetThreadId = (DWORD(__stdcall*)(HANDLE))GetProcAddress(GetModuleHandleW(L"kernel32.dll"), "GetThreadId");
static auto pGetProcessIdOfThread = (DWORD(__stdcall*)(HANDLE))GetProcAddress(GetModuleHandleW(L"kernel32.dll"), "GetProcessIdOfThread");
if(pGetThreadId != NULL && pGetProcessIdOfThread != NULL) //Vista or Server 2003 only
{
TID = pGetThreadId(hThread);
PID = pGetProcessIdOfThread(hThread);
}
else //Windows XP
{
THREAD_BASIC_INFORMATION threadInfo;
ULONG threadInfoSize = 0;
NTSTATUS isok = NtQueryInformationThread(hThread, ThreadBasicInformation, &threadInfo, sizeof(threadInfo), &threadInfoSize);
if(NT_SUCCESS(isok))
{
TID = (DWORD)threadInfo.ClientId.UniqueThread;
PID = (DWORD)threadInfo.ClientId.UniqueProcess;
}
}
};
DWORD TID, PID;
getTidPid(hLocalHandle, TID, PID);
if(TID == 0 || PID == 0) //The first time could fail because the process didn't specify query permissions.
{
HANDLE hLocalQueryHandle;
if(DuplicateHandle(hProcess, remoteHandle, GetCurrentProcess(), &hLocalQueryHandle, THREAD_QUERY_INFORMATION, FALSE, 0))
{
getTidPid(hLocalQueryHandle, TID, PID);
CloseHandle(hLocalQueryHandle);
}
}
if(TID > 0 && PID > 0)
{
// Check if the thread is in the debuggee
if(PID == fdProcessInfo->dwProcessId)
{
char ThreadName[MAX_THREAD_NAME_SIZE];
if(ThreadGetName(TID, ThreadName) && ThreadName[0] != 0)
name = StringUtils::sprintf("TID: %s (%s), PID: %s (%s)", formatpidtid(TID).c_str(), ThreadName, formatpidtid(PID).c_str(), GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Debuggee")));
else
name = StringUtils::sprintf("TID: %s, PID: %s (%s)", formatpidtid(TID).c_str(), ThreadName, formatpidtid(PID).c_str(), GuiTranslateText(QT_TRANSLATE_NOOP("DBG", "Debuggee")));
}
else
{
std::string processName = getProcessName(PID);
if(processName.size() > 0)
name = StringUtils::sprintf("TID: %s, PID: %s (%s)", formatpidtid(TID).c_str(), formatpidtid(PID).c_str(), processName.c_str());
else
name = StringUtils::sprintf("TID: %s, PID: %s", formatpidtid(TID).c_str(), formatpidtid(PID).c_str());
}
}
}
if(name.empty())
{
HANDLE hThread;
hThread = CreateThread(nullptr, 0, getNameThread, &getName, 0, nullptr);
auto result = WaitForSingleObject(hThread, 200);
if(result != WAIT_OBJECT_0)
{
TerminateThread(hThread, 0);
name = String(ErrorCodeToName(result));
}
else
CloseHandle(hThread);
}
CloseHandle(hLocalHandle);
}
else
name = String(ErrorCodeToName(GetLastError()));
if(typeName.empty())
{
SHARED_ACQUIRE(LockHandleCache);
auto itr = HandleTypeCache.find(remoteHandle);
if(itr != HandleTypeCache.end())
typeName = itr->second;
}
return true;
}
/**
\brief Get information about a window
*/
static WINDOW_INFO getWindowInfo(HWND hWnd)
{
WINDOW_INFO info;
memset(&info, 0, sizeof(info));
if(IsWindow(hWnd) != TRUE) //Not a window
{
return info;
}
info.handle = (duint)hWnd; //Get Window Handle
GetWindowRect(hWnd, &info.position); //Get Window Rect
info.style = GetWindowLong(hWnd, GWL_STYLE); //Get Window Style
info.styleEx = GetWindowLong(hWnd, GWL_EXSTYLE); //Get Window Stye ex
duint proc1, proc2;
proc1 = GetClassLongPtrW(hWnd, GCLP_WNDPROC);
proc2 = GetClassLongPtrA(hWnd, GCLP_WNDPROC);
if(!DbgMemIsValidReadPtr(proc1))
info.wndProc = proc2;
else if(!DbgMemIsValidReadPtr(proc2))
info.wndProc = proc1;
else if(IsWindowUnicode(hWnd))
info.wndProc = proc1;
else
info.wndProc = proc2;
if(DbgFunctions()->ModGetParty(info.wndProc) != 0 || !DbgMemIsValidReadPtr(info.wndProc))
{
duint dlgproc1, dlgproc2;
dlgproc1 = GetClassLongPtrW(hWnd, DWLP_DLGPROC);
dlgproc2 = GetClassLongPtrA(hWnd, DWLP_DLGPROC);
if(!DbgMemIsValidReadPtr(dlgproc1))
dlgproc1 = dlgproc2;
if(DbgMemIsValidReadPtr(dlgproc1))
{
info.wndProc = dlgproc1;
}
}
info.enabled = IsWindowEnabled(hWnd) == TRUE;
info.parent = (duint)GetParent(hWnd); //Get Parent Window
info.threadId = GetWindowThreadProcessId(hWnd, nullptr); //Get Window Thread Id
wchar_t limitedbuffer[256];
limitedbuffer[255] = 0;
GetWindowTextW(hWnd, limitedbuffer, 256);
if(limitedbuffer[255] != 0) //Window title too long. Add "..." to the end of buffer.
{
if(limitedbuffer[252] < 0xDC00 || limitedbuffer[252] > 0xDFFF) //protect the last surrogate of UTF-16 surrogate pair
limitedbuffer[252] = L'.';
limitedbuffer[253] = L'.';
limitedbuffer[254] = L'.';
limitedbuffer[255] = 0;
}
auto UTF8WindowTitle = StringUtils::Utf16ToUtf8(limitedbuffer);
memcpy(info.windowTitle, UTF8WindowTitle.c_str(), min(UTF8WindowTitle.size(), sizeof(info.windowTitle))); //Copy window title with repect to buffer size constraints
GetClassNameW(hWnd, limitedbuffer, 256);
if(limitedbuffer[255] != 0) //Window class too long. Add "..." to the end of buffer.
{
if(limitedbuffer[252] < 0xDC00 || limitedbuffer[252] > 0xDFFF) //protect the last surrogate of UTF-16 surrogate pair
limitedbuffer[252] = L'.';
limitedbuffer[253] = L'.';
limitedbuffer[254] = L'.';
limitedbuffer[255] = 0;
}
UTF8WindowTitle = StringUtils::Utf16ToUtf8(limitedbuffer);
memcpy(info.windowClass, UTF8WindowTitle.c_str(), min(UTF8WindowTitle.size(), sizeof(info.windowClass))); //Copy window class with repect to buffer size constraints
return info;
}
static BOOL CALLBACK getWindowInfoCallback(HWND hWnd, LPARAM lParam)
{
std::vector<WINDOW_INFO>* windowInfo = reinterpret_cast<std::vector<WINDOW_INFO>*>(lParam);
DWORD pid = 0;
GetWindowThreadProcessId(hWnd, &pid);
if(pid == fdProcessInfo->dwProcessId)
{
windowInfo->push_back(getWindowInfo(hWnd));
}
return TRUE;
}
/**
\brief Enumerates the window and return a list of all the windows owned by the debuggee (currently only top level windows)
*/
bool HandlesEnumWindows(std::vector<WINDOW_INFO> & windowsList)
{
std::vector<WINDOW_INFO> childWindowsList;
EnumWindows(getWindowInfoCallback, (LPARAM)&windowsList);
auto i = windowsList.begin();
for(auto i = windowsList.cbegin(); i != windowsList.cend(); ++i)
{
EnumChildWindows((HWND)i->handle, getWindowInfoCallback, (LPARAM)&childWindowsList);
}
for(auto i = childWindowsList.cbegin(); i != childWindowsList.cend(); ++i)
{
windowsList.push_back(*i);
}
return true;
}
/**
\brief Enumerates the heap and return a list of all the heaps in the debuggee
*/
bool HandlesEnumHeaps(std::vector<HEAPINFO> & heapList)
{
// Slow and official method to enum all heap blocks.
/*
HEAPLIST32 hl;
Handle hHeapSnap = CreateToolhelp32Snapshot(TH32CS_SNAPHEAPLIST, fdProcessInfo->dwProcessId);
hl.dwSize = sizeof(HEAPLIST32);
if(hHeapSnap == INVALID_HANDLE_VALUE)
{
return false;
}
if(Heap32ListFirst(hHeapSnap, &hl))
{
do
{
HEAPENTRY32 he;
ZeroMemory(&he, sizeof(HEAPENTRY32));
he.dwSize = sizeof(HEAPENTRY32);
if(Heap32First(&he, fdProcessInfo->dwProcessId, hl.th32HeapID))
{
do
{
HEAPINFO heapInfo;
memset(&heapInfo, 0, sizeof(heapInfo));
heapInfo.addr = he.dwAddress;
heapInfo.size = he.dwBlockSize;
heapInfo.flags = he.dwFlags;
heapList.push_back(heapInfo);
he.dwSize = sizeof(HEAPENTRY32);
}
while(Heap32Next(&he));
}
hl.dwSize = sizeof(HEAPLIST32);
}
while(Heap32ListNext(hHeapSnap, &hl));
}
else
{
return false;
}
return true;
*/
return false;
}
String LoadedAntiCheatDrivers()
{
Memory<RTL_PROCESS_MODULES*> HandleInformation(0x1000, __FUNCTION__);
NTSTATUS ErrorCode = ERROR_SUCCESS;
for(;;)
{
ErrorCode = NtQuerySystemInformation(SystemModuleInformation, HandleInformation(), ULONG(HandleInformation.size()), nullptr);
if(ErrorCode != STATUS_INFO_LENGTH_MISMATCH)
break;
HandleInformation.realloc(HandleInformation.size() * 2, __FUNCTION__);
}
if(ErrorCode != STATUS_SUCCESS)
return {};
const char* AntiCheatDrivers[] =
{
"EasyAntiCheat.sys",
"EasyAntiCheat_EOS.sys",
};
std::unordered_set<String> DriverSet;
for(auto & Driver : AntiCheatDrivers)
DriverSet.insert(StringUtils::ToLower(Driver));
String Result;
auto Modules = HandleInformation();
for(ULONG i = 0; i < Modules->NumberOfModules; i++)
{
const auto & Module = Modules->Modules[i];
String DriverName = (char*)Module.FullPathName + Module.OffsetToFileName;
if(DriverSet.count(StringUtils::ToLower(DriverName)))
{
if(!Result.empty())
Result += '\n';
Result += DriverName;
}
}
return Result;
} |
C/C++ | x64dbg-development/src/dbg/handles.h | #pragma once
#include "_global.h"
#include "_dbgfunctions.h"
bool HandlesEnum(std::vector<HANDLEINFO> & handlesList);
bool HandlesGetName(HANDLE remoteHandle, String & name, String & typeName);
bool HandlesEnumWindows(std::vector<WINDOW_INFO> & windowsList);
bool HandlesEnumHeaps(std::vector<HEAPINFO> & heapList);
String LoadedAntiCheatDrivers(); |
C++ | x64dbg-development/src/dbg/historycontext.cpp | #include "historycontext.h"
#include "disasm_helper.h"
#include "memory.h"
#include "console.h"
#include "watch.h"
#include "threading.h"
#include "cmd-watch-control.h"
#include "debugger.h"
#include <deque>
/**
* @brief The class used to hold history context.
**/
class HistoryContext
{
public:
HistoryContext();
void restore();
protected:
TITAN_ENGINE_CONTEXT_t registers;
struct ChangedData
{
duint addr;
char oldvalue[32];
};
std::vector<ChangedData> ChangedLocation;
bool invalid;
};
static const duint HistoryMaxCount = 4096;
static std::deque<HistoryContext> history;
//This will capture the current instruction
HistoryContext::HistoryContext()
{
DISASM_INSTR instruction;
if(GetFullContextDataEx(hActiveThread, ®isters) && MemIsValidReadPtr(registers.cip))
{
disasmget(registers.cip, &instruction);
if(!(memcmp(instruction.instruction, "nop ", 4) == 0 || memcmp(instruction.instruction, "lea ", 4) == 0))
// do not process the memory operands of these instructions, because these instructions do not write to the memory.
{
if(memcmp(instruction.instruction, "push", 4) == 0 || memcmp(instruction.instruction, "call", 4) == 0)
// push and call instruction : save previous content on the stack
{
ChangedData olddata;
olddata.addr = registers.csp - sizeof(duint);
MemRead(olddata.addr, (unsigned char*)olddata.oldvalue, sizeof(duint));
ChangedLocation.push_back(olddata);
}
// TODO: FPU/SSE instructions, ENTER instruction, and possibly other instructions.
// These instructions can write more than sizeof(duint) bytes.
for(int i = 0; i < instruction.argcount; i++)
{
DISASM_ARG & arg = instruction.arg[i];
if(arg.type == DISASM_ARGTYPE::arg_memory)
{
ChangedData olddata;
olddata.addr = arg.value;
memcpy(olddata.oldvalue, &arg.memvalue, sizeof(arg.memvalue));
ChangedLocation.push_back(olddata);
}
}
}
invalid = false;
}
else
invalid = true;
}
void HistoryContext::restore()
{
if(!invalid)
{
for(auto & i : ChangedLocation)
MemWrite(i.addr, i.oldvalue, sizeof(duint));
SetFullContextDataEx(hActiveThread, ®isters);
cbCheckWatchdog(0, nullptr);
DebugUpdateGui(GetContextDataEx(hActiveThread, UE_CIP), true);
}
else
{
HistoryClear();
dputs(QT_TRANSLATE_NOOP("DBG", "Cannot restore last instruction."));
}
}
void HistoryRecord()
{
EXCLUSIVE_ACQUIRE(LockHistory);
if(history.size() > HistoryMaxCount)
history.pop_front();
history.emplace_back(); // the constructor records the context
}
void HistoryRestore()
{
EXCLUSIVE_ACQUIRE(LockHistory);
if(!history.empty())
{
history.back().restore();
history.pop_back();
}
else
dputs(QT_TRANSLATE_NOOP("DBG", "History record is empty"));
}
bool HistoryIsEmpty()
{
SHARED_ACQUIRE(LockHistory);
return history.empty();
}
void HistoryClear()
{
EXCLUSIVE_ACQUIRE(LockHistory);
history.clear();
} |
C/C++ | x64dbg-development/src/dbg/historycontext.h | #ifndef HISTORYCONTEXT_H
#define HISTORYCONTEXT_H
#include "_global.h"
#include "TitanEngine/TitanEngine.h"
void HistoryRecord();
void HistoryRestore();
void HistoryClear();
bool HistoryIsEmpty();
#endif //HISTORY_CONTEXT_H |
C++ | x64dbg-development/src/dbg/jit.cpp | #include "jit.h"
static bool readwritejitkey(const wchar_t* jit_key_value, DWORD* jit_key_vale_size, const char* key, arch arch_in, arch* arch_out, readwritejitkey_error_t* error, bool write)
{
DWORD key_flags;
DWORD lRv;
HKEY hKey;
DWORD dwDisposition;
if(error != NULL)
*error = ERROR_RW;
if(write)
{
if(!BridgeIsProcessElevated())
{
if(error != NULL)
*error = ERROR_RW_NOTADMIN;
return false;
}
key_flags = KEY_WRITE;
}
else
key_flags = KEY_READ;
if(arch_out != NULL)
{
if(arch_in != x64 && arch_in != x32)
{
#ifdef _WIN64
*arch_out = x64;
#else //x86
*arch_out = x32;
#endif //_WIN64
}
else
*arch_out = arch_in;
}
if(arch_in == x64)
{
#ifndef _WIN64
if(!IsWow64())
{
if(error != NULL)
*error = ERROR_RW_NOTWOW64;
return false;
}
key_flags |= KEY_WOW64_64KEY;
#endif //_WIN64
}
else if(arch_in == x32)
{
#ifdef _WIN64
key_flags |= KEY_WOW64_32KEY;
#endif
}
if(write)
{
lRv = RegCreateKeyExW(HKEY_LOCAL_MACHINE, JIT_REG_KEY, 0, NULL, REG_OPTION_NON_VOLATILE, key_flags, NULL, &hKey, &dwDisposition);
if(lRv != ERROR_SUCCESS)
return false;
lRv = RegSetValueExW(hKey, StringUtils::Utf8ToUtf16(key).c_str(), 0, REG_SZ, (const BYTE*)jit_key_value, (DWORD)(*jit_key_vale_size) + 1);
}
else
{
lRv = RegOpenKeyExW(HKEY_LOCAL_MACHINE, JIT_REG_KEY, 0, key_flags, &hKey);
if(lRv != ERROR_SUCCESS)
{
if(error != NULL)
*error = ERROR_RW_FILE_NOT_FOUND;
return false;
}
lRv = RegQueryValueExW(hKey, StringUtils::Utf8ToUtf16(key).c_str(), 0, NULL, (LPBYTE)jit_key_value, jit_key_vale_size);
if(lRv != ERROR_SUCCESS)
{
if(error != NULL)
*error = ERROR_RW_FILE_NOT_FOUND;
}
}
RegCloseKey(hKey);
return (lRv == ERROR_SUCCESS);
}
bool dbggetjitauto(bool* auto_on, arch arch_in, arch* arch_out, readwritejitkey_error_t* rw_error_out)
{
wchar_t jit_entry[4] = L"";
DWORD jit_entry_size = sizeof(jit_entry) - 1;
readwritejitkey_error_t rw_error;
if(!readwritejitkey(jit_entry, &jit_entry_size, "Auto", arch_in, arch_out, &rw_error, false))
{
if(rw_error == ERROR_RW_FILE_NOT_FOUND)
{
if(rw_error_out != NULL)
*rw_error_out = rw_error;
return true;
}
return false;
}
if(_wcsicmp(jit_entry, L"1") == 0)
*auto_on = true;
else if(_wcsicmp(jit_entry, L"0") == 0)
*auto_on = false;
else
return false;
return true;
}
bool dbgsetjitauto(bool auto_on, arch arch_in, arch* arch_out, readwritejitkey_error_t* rw_error_out)
{
DWORD auto_string_size = sizeof(L"1");
readwritejitkey_error_t rw_error;
if(!auto_on)
{
wchar_t jit_entry[4] = L"";
DWORD jit_entry_size = sizeof(jit_entry) - 1;
if(!readwritejitkey(jit_entry, &jit_entry_size, "Auto", arch_in, arch_out, &rw_error, false))
{
if(rw_error == ERROR_RW_FILE_NOT_FOUND)
return true;
}
}
if(!readwritejitkey((wchar_t*)(auto_on ? L"1" : L"0"), &auto_string_size, "Auto", arch_in, arch_out, &rw_error, true))
{
if(rw_error_out != NULL)
*rw_error_out = rw_error;
return false;
}
return true;
}
bool dbggetjit(char jit_entry[JIT_ENTRY_MAX_SIZE], arch arch_in, arch* arch_out, readwritejitkey_error_t* rw_error_out)
{
wchar_t wszJitEntry[JIT_ENTRY_MAX_SIZE] = L"";
DWORD jit_entry_size = JIT_ENTRY_MAX_SIZE * sizeof(wchar_t);
readwritejitkey_error_t rw_error;
if(!readwritejitkey(wszJitEntry, &jit_entry_size, "Debugger", arch_in, arch_out, &rw_error, false))
{
if(rw_error_out != NULL)
*rw_error_out = rw_error;
return false;
}
strcpy_s(jit_entry, JIT_ENTRY_MAX_SIZE, StringUtils::Utf16ToUtf8(wszJitEntry).c_str());
return true;
}
bool dbggetdefjit(char* jit_entry)
{
char path[JIT_ENTRY_DEF_SIZE];
path[0] = '"';
wchar_t wszPath[MAX_PATH] = L"";
GetModuleFileNameW(GetModuleHandleW(NULL), wszPath, MAX_PATH);
strncpy_s(&path[1], JIT_ENTRY_DEF_SIZE - 1, StringUtils::Utf16ToUtf8(wszPath).c_str(), _TRUNCATE);
strncat_s(path, ATTACH_CMD_LINE, _TRUNCATE);
strncpy_s(jit_entry, JIT_ENTRY_DEF_SIZE, path, _TRUNCATE);
return true;
}
bool dbgsetjit(const char* jit_cmd, arch arch_in, arch* arch_out, readwritejitkey_error_t* rw_error_out)
{
DWORD jit_cmd_size = (DWORD)strlen(jit_cmd) * sizeof(wchar_t);
readwritejitkey_error_t rw_error;
if(!readwritejitkey((wchar_t*)StringUtils::Utf8ToUtf16(jit_cmd).c_str(), &jit_cmd_size, "Debugger", arch_in, arch_out, &rw_error, true))
{
if(rw_error_out != NULL)
*rw_error_out = rw_error;
return false;
}
return true;
} |
C/C++ | x64dbg-development/src/dbg/jit.h | #ifndef _JIT_H
#define _JIT_H
#include "_global.h"
#define ATTACH_CMD_LINE "\" -a %ld -e %ld"
#define JIT_REG_KEY L"SOFTWARE\\Microsoft\\Windows NT\\CurrentVersion\\AeDebug"
#define JIT_ENTRY_MAX_SIZE 512
#define JIT_ENTRY_DEF_SIZE (MAX_PATH + sizeof(ATTACH_CMD_LINE) + 2)
typedef enum
{
ERROR_RW = 0,
ERROR_RW_FILE_NOT_FOUND,
ERROR_RW_NOTWOW64,
ERROR_RW_NOTADMIN
} readwritejitkey_error_t;
enum arch
{
notfound,
x32,
x64,
};
bool dbggetjit(char jit_entry[JIT_ENTRY_MAX_SIZE], arch arch_in, arch* arch_out, readwritejitkey_error_t* rw_error_out);
bool dbgsetjit(const char* jit_cmd, arch arch_in, arch* arch_out, readwritejitkey_error_t* rw_error_out);
bool dbggetjitauto(bool* auto_on, arch arch_in, arch* arch_out, readwritejitkey_error_t* rw_error_out);
bool dbgsetjitauto(bool auto_on, arch arch_in, arch* arch_out, readwritejitkey_error_t* rw_error_out);
bool dbggetdefjit(char* jit_entry);
#endif // _JIT_H |
C++ | x64dbg-development/src/dbg/label.cpp | #include "label.h"
struct LabelSerializer : AddrInfoSerializer<LABELSINFO>
{
bool Save(const LABELSINFO & value) override
{
AddrInfoSerializer::Save(value);
setString("text", value.text);
return true;
}
bool Load(LABELSINFO & value) override
{
return AddrInfoSerializer::Load(value) &&
getString("text", value.text);
}
};
struct Labels : AddrInfoHashMap<LockLabels, LABELSINFO, LabelSerializer>
{
const char* jsonKey() const override
{
return "labels";
}
};
static Labels labels;
static std::unordered_map<duint, std::string> tempLabels;
bool LabelSet(duint Address, const char* Text, bool Manual, bool Temp)
{
// Make sure the string is supplied, within bounds, and not a special delimiter
if(!Text || Text[0] == '\1' || strlen(Text) >= MAX_LABEL_SIZE - 1)
return false;
// Delete the label if no text was supplied
if(Text[0] == '\0')
{
LabelDelete(Address);
return true;
}
if(Temp)
{
tempLabels[Address] = Text;
return true;
}
// Fill in the structure + add to database
LABELSINFO label;
if(!labels.PrepareValue(label, Address, Manual))
return false;
label.text = Text;
return labels.Add(label);
}
bool LabelFromString(const char* Text, duint* Address)
{
auto found = labels.GetWhere([&](const LABELSINFO & value)
{
if(strcmp(value.text.c_str(), Text))
return false;
if(Address)
*Address = value.addr + ModBaseFromName(value.mod().c_str());
return true;
});
if(!found)
{
for(auto & label : tempLabels)
if(strcmp(label.second.c_str(), Text) == 0)
{
if(Address)
*Address = label.first;
return true;
}
}
return found;
}
bool LabelGet(duint Address, char* Text)
{
LABELSINFO label;
if(!labels.Get(Labels::VaKey(Address), label))
{
auto found = tempLabels.find(Address);
if(found == tempLabels.end())
return false;
if(Text)
strncpy_s(Text, MAX_LABEL_SIZE, found->second.c_str(), _TRUNCATE);
return true;
}
if(Text)
strncpy_s(Text, MAX_LABEL_SIZE, label.text.c_str(), _TRUNCATE);
return true;
}
bool LabelIsTemporary(duint Address)
{
auto found = tempLabels.find(Address);
if(found == tempLabels.end())
return false;
return true;
}
bool LabelDelete(duint Address)
{
return labels.Delete(Labels::VaKey(Address)) || tempLabels.erase(Address) > 0;
}
void LabelDelRange(duint Start, duint End, bool Manual)
{
labels.DeleteRange(Start, End, Manual);
if(Start == 0 && End == ~0)
{
tempLabels.clear();
}
else
{
for(auto it = tempLabels.begin(); it != tempLabels.end();)
{
if(it->first >= Start && it->first < End)
it = tempLabels.erase(it);
else
++it;
}
}
}
void LabelCacheSave(JSON Root)
{
labels.CacheSave(Root);
}
void LabelCacheLoad(JSON Root)
{
labels.CacheLoad(Root);
labels.CacheLoad(Root, "auto"); //legacy support
}
void LabelClear()
{
labels.Clear();
tempLabels.clear();
}
void LabelGetList(std::vector<LABELSINFO> & list)
{
labels.GetList(list);
list.reserve(list.size() + tempLabels.size());
for(auto & label : tempLabels)
{
LABELSINFO info;
info.modhash = ModHashFromAddr(label.first);
info.addr = label.first;
info.manual = false;
info.text = label.second;
list.push_back(info);
}
}
bool LabelGetInfo(duint Address, LABELSINFO* info)
{
if(info == nullptr)
return false;
return labels.Get(Labels::VaKey(Address), *info);
} |
C/C++ | x64dbg-development/src/dbg/label.h | #ifndef _LABEL_H
#define _LABEL_H
#include "_global.h"
#include "addrinfo.h"
struct LABELSINFO : AddrInfo
{
std::string text;
};
bool LabelSet(duint Address, const char* Text, bool Manual, bool Temp = false);
bool LabelFromString(const char* Text, duint* Address);
bool LabelGet(duint Address, char* Text);
bool LabelIsTemporary(duint Address);
bool LabelDelete(duint Address);
void LabelDelRange(duint Start, duint End, bool Manual);
void LabelCacheSave(JSON root);
void LabelCacheLoad(JSON root);
void LabelClear();
void LabelGetList(std::vector<LABELSINFO> & list);
bool LabelGetInfo(duint Address, LABELSINFO* info);
#endif // _LABEL_H |
C++ | x64dbg-development/src/dbg/log.cpp | #include "_global.h"
#include "log.h"
log::log(void)
{
}
log::~log(void)
{
GuiAddLogMessage(message.str().c_str());
} |
C++ | x64dbg-development/src/dbg/loop.cpp | #include "loop.h"
#include "memory.h"
#include "threading.h"
#include "module.h"
#include "debugger.h"
static std::map<DepthModuleRange, LOOPSINFO, DepthModuleRangeCompare> loops;
bool LoopAdd(duint Start, duint End, bool Manual, duint instructionCount)
{
ASSERT_DEBUGGING("Export call");
// Loop must begin before it ends
if(Start > End)
return false;
// Memory addresses must be valid
if(!MemIsValidReadPtr(Start) || !MemIsValidReadPtr(End))
return false;
// Check if loop boundaries are in the same module range
const duint moduleBase = ModBaseFromAddr(Start);
if(moduleBase != ModBaseFromAddr(End))
return false;
// Loops cannot overlap other loops
int finalDepth = 0;
bool surround = false;
duint finalStart = 0, finalEnd = 0;
if(LoopOverlaps(0, Start, End, &finalDepth, &finalStart, &finalEnd))
{
if(Start <= finalStart && End >= finalEnd)
{
surround = true;
finalDepth = 0;
}
else
{
return false;
}
}
// Fill out loop information structure
LOOPSINFO loopInfo;
loopInfo.start = Start - moduleBase;
loopInfo.end = End - moduleBase;
loopInfo.depth = finalDepth;
loopInfo.manual = Manual;
loopInfo.instructioncount = instructionCount;
loopInfo.modhash = ModHashFromAddr(moduleBase);
loopInfo.parent = 0;
// Link this to a parent loop if one does exist
if(finalDepth)
LoopGet(finalDepth - 1, Start, &loopInfo.parent, 0);
else
loopInfo.parent = 0;
if(loopInfo.parent)
loopInfo.parent -= moduleBase;
EXCLUSIVE_ACQUIRE(LockLoops);
if(surround)
{
// TODO: make this algorithm smarter, now it's O(n), but can be O(logn) with lower_bound
// However, this is probably an edge case, so we can not care for now
std::vector<std::pair<DepthModuleRange, LOOPSINFO>> reinsert;
for(auto loopItr = loops.begin(); loopItr != loops.end();)
{
auto & loop = loopItr->second;
if(loopInfo.modhash == loop.modhash && loopInfo.start <= loop.start && loopInfo.end >= loop.end)
{
reinsert.emplace_back(loopItr->first, loopItr->second);
loopItr = loops.erase(loopItr);
}
else
{
++loopItr;
}
}
for(auto & loop : reinsert)
{
loop.first.first++;
loop.second.depth++;
loops.insert(loop);
}
}
// Insert into list
loops.emplace(DepthModuleRange(finalDepth, ModuleRange(loopInfo.modhash, Range(loopInfo.start, loopInfo.end))), loopInfo);
return true;
}
// Get the start/end of a loop at a certain depth and address
bool LoopGet(int Depth, duint Address, duint* Start, duint* End, duint* InstructionCount)
{
ASSERT_DEBUGGING("Export call");
// Get the virtual address module
const duint moduleBase = ModBaseFromAddr(Address);
// Virtual address to relative address
Address -= moduleBase;
SHARED_ACQUIRE(LockLoops);
// Search with this address range
auto found = loops.find(DepthModuleRange(Depth, ModuleRange(ModHashFromAddr(moduleBase), Range(Address, Address))));
if(found == loops.end())
return false;
// Return the loop start and end
if(Start)
*Start = found->second.start + moduleBase;
if(End)
*End = found->second.end + moduleBase;
if(InstructionCount)
*InstructionCount = found->second.instructioncount;
return true;
}
// Check if a loop overlaps a range, inside is not overlapping
bool LoopOverlaps(int Depth, duint Start, duint End, int* FinalDepth, duint* FinalStart, duint* FinalEnd)
{
ASSERT_DEBUGGING("Export call");
// Determine module addresses and lookup keys
const duint moduleBase = ModBaseFromAddr(Start);
// Virtual addresses to relative addresses
Start -= moduleBase;
End -= moduleBase;
// The last recursive call will set FinalDepth last
if(FinalDepth)
*FinalDepth = Depth;
SHARED_ACQUIRE(LockLoops);
auto found = loops.find(DepthModuleRange(Depth, ModuleRange(ModHashFromAddr(moduleBase), Range(Start, End))));
if(found == loops.end())
return false;
if(found->second.start <= Start && found->second.end >= End)
return LoopOverlaps(Depth + 1, Start + moduleBase, End + moduleBase, FinalDepth, FinalStart, FinalEnd);
if(FinalStart)
*FinalStart = found->second.start + moduleBase;
if(FinalEnd)
*FinalEnd = found->second.end + moduleBase;
return true;
}
static bool LoopDeleteAllRange(const DepthModuleRange & range)
{
auto erased = 0;
for(auto found = loops.find(range); found != loops.end(); found = loops.find(range), erased++)
loops.erase(found);
return erased > 0;
}
void LoopDeleteRange(duint Start, duint End)
{
EXCLUSIVE_ACQUIRE(LockLoops);
auto modBase = ModBaseFromAddr(Start);
auto modHash = ModHashFromAddr(modBase);
// Delete all loops in the given range increasing the depth until nothing is left to delete
auto range = DepthModuleRange(0, ModuleRange(modHash, Range(Start - modBase, End - modBase)));
while(LoopDeleteAllRange(range))
range.first++;
}
// This should delete a loop and all sub-loops that matches a certain addr
bool LoopDelete(int Depth, duint Address)
{
// Get the virtual address module
const duint moduleBase = ModBaseFromAddr(Address);
// Virtual address to relative address
Address -= moduleBase;
EXCLUSIVE_ACQUIRE(LockLoops);
// Search with this address range
auto found = loops.find(DepthModuleRange(Depth, ModuleRange(ModHashFromAddr(moduleBase), Range(Address, Address))));
if(found == loops.end())
return false;
// Delete all loops in the given range increasing the depth until nothing is left to delete
auto range = found->first;
while(LoopDeleteAllRange(range))
range.first++;
return true;
}
void LoopCacheSave(JSON Root)
{
EXCLUSIVE_ACQUIRE(LockLoops);
// Create the root JSON objects
const JSON jsonLoops = json_array();
const JSON jsonAutoLoops = json_array();
// Write all entries
for(auto & itr : loops)
{
const LOOPSINFO & currentLoop = itr.second;
JSON currentJson = json_object();
json_object_set_new(currentJson, "module", json_string(currentLoop.mod().c_str()));
json_object_set_new(currentJson, "start", json_hex(currentLoop.start));
json_object_set_new(currentJson, "end", json_hex(currentLoop.end));
json_object_set_new(currentJson, "depth", json_integer(currentLoop.depth));
json_object_set_new(currentJson, "parent", json_hex(currentLoop.parent));
json_object_set_new(currentJson, "icount", json_hex(currentLoop.instructioncount));
if(currentLoop.manual)
json_array_append_new(jsonLoops, currentJson);
else
json_array_append_new(jsonAutoLoops, currentJson);
}
// Append a link to the global root
if(json_array_size(jsonLoops))
json_object_set(Root, "loops", jsonLoops);
if(json_array_size(jsonAutoLoops))
json_object_set(Root, "autoloops", jsonAutoLoops);
// Release memory/references
json_decref(jsonLoops);
json_decref(jsonAutoLoops);
}
void LoopCacheLoad(JSON Root)
{
EXCLUSIVE_ACQUIRE(LockLoops);
// Inline lambda to parse each JSON entry
auto AddLoops = [](const JSON Object, bool Manual)
{
size_t i;
JSON value;
json_array_foreach(Object, i, value)
{
LOOPSINFO loopInfo;
// Module name
const char* mod = json_string_value(json_object_get(value, "module"));
if(mod && strlen(mod) < MAX_MODULE_SIZE)
loopInfo.modhash = ModHashFromName(mod);
else
loopInfo.modhash = 0;
// All other variables
loopInfo.start = (duint)json_hex_value(json_object_get(value, "start"));
loopInfo.end = (duint)json_hex_value(json_object_get(value, "end"));
loopInfo.depth = (int)json_integer_value(json_object_get(value, "depth"));
loopInfo.parent = (duint)json_hex_value(json_object_get(value, "parent"));
loopInfo.instructioncount = (duint)json_hex_value(json_object_get(value, "icount"));
loopInfo.manual = Manual;
// Coherence check: Make sure the loop starts before it ends
if(loopInfo.end < loopInfo.start)
continue;
// Insert into global list
loops[DepthModuleRange(loopInfo.depth, ModuleRange(loopInfo.modhash, Range(loopInfo.start, loopInfo.end)))] = loopInfo;
}
};
const JSON jsonLoops = json_object_get(Root, "loops");
const JSON jsonAutoLoops = json_object_get(Root, "autoloops");
// Load user-set loops
if(jsonLoops)
AddLoops(jsonLoops, true);
// Load auto-set loops
if(jsonAutoLoops)
AddLoops(jsonAutoLoops, false);
}
bool LoopEnum(LOOPSINFO* List, size_t* Size)
{
// If list or size is not requested, fail
ASSERT_FALSE(!List && !Size);
SHARED_ACQUIRE(LockLoops);
// See if the caller requested an output size
if(Size)
{
*Size = loops.size() * sizeof(LOOPSINFO);
if(!List)
return true;
}
for(auto & itr : loops)
{
*List = itr.second;
// Adjust the offset to a real virtual address
duint modbase = ModBaseFromName(List->mod().c_str());
List->start += modbase;
List->end += modbase;
List++;
}
return true;
}
void LoopClear()
{
EXCLUSIVE_ACQUIRE(LockLoops);
std::map<DepthModuleRange, LOOPSINFO, DepthModuleRangeCompare> empty;
std::swap(loops, empty);
} |
C/C++ | x64dbg-development/src/dbg/loop.h | #ifndef _LOOP_H
#define _LOOP_H
#include "addrinfo.h"
struct LOOPSINFO
{
duint modhash;
duint start;
duint end;
duint parent;
int depth;
bool manual;
duint instructioncount;
std::string mod() const
{
return ModNameFromHash(modhash);
}
};
bool LoopAdd(duint Start, duint End, bool Manual, duint InstructionCount = 0);
bool LoopGet(int Depth, duint Address, duint* Start = nullptr, duint* End = nullptr, duint* InstructionCount = nullptr);
bool LoopOverlaps(int Depth, duint Start, duint End, int* FinalDepth, duint* FinalStart = nullptr, duint* FinalEnd = nullptr);
void LoopDeleteRange(duint Start, duint End);
bool LoopDelete(int Depth, duint Address);
void LoopCacheSave(JSON Root);
void LoopCacheLoad(JSON Root);
bool LoopEnum(LOOPSINFO* List, size_t* Size);
void LoopClear();
#endif //_LOOP_H |
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