module_content
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1.05M
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module sky130_fd_sc_ls__clkdlyinv3sd2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module execute_div(
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//FLAG
output wire oFLAG_WAITING_DIV,
//Prev
input wire iPREV_VALID,
input wire iPREV_UDIV,
input wire iPREV_SDIV,
input wire [4:0] iCMD,
//iDATA
input wire [31:0] iDATA_0,
input wire [31:0] iDATA_1,
//oDATA
input wire iBUSY,
output wire oDATA_VALID,
output wire [31:0] oDATA
);
wire divider_condition = iPREV_VALID && (iPREV_UDIV || iPREV_SDIV) && !iBUSY;
wire divider_out_valid;
wire [31:0] divider_out_q;
wire [31:0] divider_out_r;
pipelined_div_radix2 EXE_DIV(
//System
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iREMOVE(iRESET_SYNC),
//Source
.oSOURCE_BUSY(/* Not Use*/),
.iSOURCE_VALID(divider_condition),
.iSOURCE_SIGN(iPREV_SDIV),
.iSOURCE_DIVIDEND(iDATA_0),
.iSOURCE_DIVISOR(iDATA_1),
//Output
.iOUT_BUSY(1'b0),
.oOUT_VALID(divider_out_valid),
.oOUT_DATA_Q(divider_out_q),
.oOUT_DATA_R(divider_out_r)
);
reg b_div_wait;
localparam PL_IDLE = 1'b0;
localparam PL_WAIT = 1'b1;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_div_wait <= 1'b0;
end
else if(iRESET_SYNC)begin
b_div_wait <= PL_IDLE;
end
else begin
case(b_div_wait)
PL_IDLE:
begin
if(divider_condition)begin
b_div_wait <= PL_WAIT;
end
end
PL_WAIT:
begin
if(divider_out_valid)begin
b_div_wait <= PL_IDLE;
end
end
endcase
end
end
reg b_div_q_r_condition;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_div_q_r_condition <= 1'b0;
end
else if(iRESET_SYNC)begin
b_div_q_r_condition <= 1'b0;
end
else begin
if(b_div_wait == PL_IDLE)begin
if(divider_condition)begin
b_div_q_r_condition <= ((iPREV_UDIV && iCMD == `EXE_DIV_UMOD || iPREV_SDIV && iCMD == `EXE_DIV_MOD))? 1'b0 : 1'b1; //0:R 1:Q
end
end
end
end
assign oDATA_VALID = divider_out_valid;
assign oDATA = (b_div_q_r_condition)? divider_out_q : divider_out_r;
assign oFLAG_WAITING_DIV = b_div_wait;
endmodule
|
module ovl_stack (clock, reset, enable, push, push_data, pop, pop_data, full, empty, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter depth = 2;
parameter width = 1;
parameter high_water_mark = 0;
parameter push_latency = 0;
parameter pop_latency = 0;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input pop, push, full, empty;
input [width-1:0] pop_data, push_data;
output [`OVL_FIRE_WIDTH-1 : 0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_STACK";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SVA
`include "./sva05/ovl_stack_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`endmodule
|
module FB_CfbTlNetwork
(
input wire clk,
//input events
input wire Tick_eI,
input wire Start_eI,
input wire SpecialInstr_eI,
input wire N_S_PedWaiting_eI,
input wire E_W_PedWaiting_eI,
//output events
output wire N_S_PedLightsChange_eO,
output wire N_S_TrafLightsChange_eO,
output wire E_W_PedLightsChange_eO,
output wire E_W_TrafLightsChange_eO,
//input variables
input wire N_S_HoldGreen_I,
input wire E_W_HoldGreen_I,
//output variables
output wire N_S_PedRed_O ,
output wire N_S_PedFlashRed_O ,
output wire N_S_PedGreen_O ,
output wire N_S_TrafRed_O ,
output wire N_S_TrafYellow_O ,
output wire N_S_TrafGreen_O ,
output wire E_W_PedRed_O ,
output wire E_W_PedFlashRed_O ,
output wire E_W_PedGreen_O ,
output wire E_W_TrafRed_O ,
output wire E_W_TrafYellow_O ,
output wire E_W_TrafGreen_O ,
input reset
);
//Wires needed for event connections
wire Tick_conn;
wire SpecialInstr_conn;
wire Start_conn;
wire mt_N_S_Start_conn;
wire N_S_DoneSeq_conn;
wire mt_E_W_Start_conn;
wire E_W_DoneSeq_conn;
wire N_S_PedWaiting_conn;
wire E_W_PedWaiting_conn;
wire N_S_PedLightsChange_conn;
wire N_S_TrafLightsChange_conn;
wire E_W_PedLightsChange_conn;
wire E_W_TrafLightsChange_conn;
//Wires needed for data connections
wire N_S_HoldGreen_conn;
wire E_W_HoldGreen_conn;
wire N_S_PedRed_conn;
wire N_S_PedFlashRed_conn;
wire N_S_PedGreen_conn;
wire N_S_TrafRed_conn;
wire N_S_TrafYellow_conn;
wire N_S_TrafGreen_conn;
wire E_W_PedRed_conn;
wire E_W_PedFlashRed_conn;
wire E_W_PedGreen_conn;
wire E_W_TrafRed_conn;
wire E_W_TrafYellow_conn;
wire E_W_TrafGreen_conn;
//top level I/O to signals
//input events
assign Tick_conn = Tick_eI;
assign Tick_conn = Tick_eI;
assign Start_conn = Start_eI;
assign SpecialInstr_conn = SpecialInstr_eI;
assign SpecialInstr_conn = SpecialInstr_eI;
assign N_S_PedWaiting_conn = N_S_PedWaiting_eI;
assign E_W_PedWaiting_conn = E_W_PedWaiting_eI;
//output events
assign N_S_PedLightsChange_eO = N_S_PedLightsChange_conn;
assign N_S_TrafLightsChange_eO = N_S_TrafLightsChange_conn;
assign E_W_PedLightsChange_eO = E_W_PedLightsChange_conn;
assign E_W_TrafLightsChange_eO = E_W_TrafLightsChange_conn;
//input variables
assign N_S_HoldGreen_conn = N_S_HoldGreen_I;
assign E_W_HoldGreen_conn = E_W_HoldGreen_I;
//output events
assign N_S_PedRed_O = N_S_PedRed_conn;
assign N_S_PedFlashRed_O = N_S_PedFlashRed_conn;
assign N_S_PedGreen_O = N_S_PedGreen_conn;
assign N_S_TrafRed_O = N_S_TrafRed_conn;
assign N_S_TrafYellow_O = N_S_TrafYellow_conn;
assign N_S_TrafGreen_O = N_S_TrafGreen_conn;
assign E_W_PedRed_O = E_W_PedRed_conn;
assign E_W_PedFlashRed_O = E_W_PedFlashRed_conn;
assign E_W_PedGreen_O = E_W_PedGreen_conn;
assign E_W_TrafRed_O = E_W_TrafRed_conn;
assign E_W_TrafYellow_O = E_W_TrafYellow_conn;
assign E_W_TrafGreen_O = E_W_TrafGreen_conn;
// child I/O to signals
FB_CfbOneLink N_S (
.clk(clk),
//event outputs
.DoneSeq_eO(N_S_DoneSeq_conn),
.PedLightsChange_eO(N_S_PedLightsChange_conn),
.TrafLightsChange_eO(N_S_TrafLightsChange_conn),
//event inputs
.Tick_eI(Tick_conn),
.SpecialInstr_eI(SpecialInstr_conn),
.GoSeq_eI(mt_N_S_Start_conn),
.PedWaiting_eI(N_S_PedWaiting_conn),
//data outputs
.PedRed_O(N_S_PedRed_conn),
.PedFlashRed_O(N_S_PedFlashRed_conn),
.PedGreen_O(N_S_PedGreen_conn),
.TrafRed_O(N_S_TrafRed_conn),
.TrafYellow_O(N_S_TrafYellow_conn),
.TrafGreen_O(N_S_TrafGreen_conn),
//data inputs
.HoldGreen_I(N_S_HoldGreen_conn),
.reset(reset)
);
FB_CfbOneLink E_W (
.clk(clk),
//event outputs
.DoneSeq_eO(E_W_DoneSeq_conn),
.PedLightsChange_eO(E_W_PedLightsChange_conn),
.TrafLightsChange_eO(E_W_TrafLightsChange_conn),
//event inputs
.Tick_eI(Tick_conn),
.SpecialInstr_eI(SpecialInstr_conn),
.GoSeq_eI(mt_E_W_Start_conn),
.PedWaiting_eI(E_W_PedWaiting_conn),
//data outputs
.PedRed_O(E_W_PedRed_conn),
.PedFlashRed_O(E_W_PedFlashRed_conn),
.PedGreen_O(E_W_PedGreen_conn),
.TrafRed_O(E_W_TrafRed_conn),
.TrafYellow_O(E_W_TrafYellow_conn),
.TrafGreen_O(E_W_TrafGreen_conn),
//data inputs
.HoldGreen_I(E_W_HoldGreen_conn),
.reset(reset)
);
FB_BfbIntersectionMutex mt (
.clk(clk),
//event outputs
.N_S_Start_eO(mt_N_S_Start_conn),
.E_W_Start_eO(mt_E_W_Start_conn),
//event inputs
.Start_eI(Start_conn),
.N_S_Done_eI(N_S_DoneSeq_conn),
.E_W_Done_eI(E_W_DoneSeq_conn),
//data outputs
//data inputs
.reset(reset)
);
endmodule
|
module ALU (
controlALU, //Código de controle da ALU
rs, //Primeiro registrador fonte
rt, //Segundo registrador fonte
outALU, //Resultado da ALU
outBranch //Controle Branch
);
input [6:0] controlALU;
input [31:0] rs, rt;
output reg [31:0] outALU;
output reg outBranch;
localparam [4:0] ADD = 6'd1, ADDI = 6'd2,
SUB = 6'd3, SUBI = 6'd4,
MUL = 6'd5,
DIV = 6'd6,
MOD = 6'd7,
AND = 6'd8, ANDI = 6'd9,
OR = 6'd10, ORI = 6'd11,
XOR = 6'd12, XORI = 6'd13,
NOT = 6'd14,
SHL = 6'd15,
SHR = 6'd16,
BEQ = 6'd22,
BGT = 6'd23,
BGE = 6'd24,
BLT = 6'd25,
BLE = 6'd26,
BNE = 6'd27,
MOVE = 6'd28;
always @ (controlALU or rs or rt) begin
begin
if(controlALU[5:0] == ADD || controlALU[5:0] == ADDI)
outALU = rs + rt;
else if(controlALU[5:0] == SUB || controlALU[5:0] == SUBI)
outALU = rs - rt;
else if(controlALU[5:0] == MUL || controlALU[5:0] == MUL)
outALU = rs * rt;
else if(controlALU[5:0] == DIV)
outALU = rs / rt;
else if(controlALU[5:0] == MOD)
outALU = rs % rt;
else if(controlALU[5:0] == AND || controlALU[5:0] == ANDI)
outALU = (rs & rt);
else if(controlALU[5:0] == OR || controlALU[5:0] == ORI)
outALU = (rs | rt);
else if(controlALU[5:0] == XOR || controlALU[5:0] == XORI)
outALU = (rs ^ rt);
else if(controlALU[5:0] == NOT)
outALU = ~rs;
else if(controlALU[5:0] == SHL)
outALU = rs << rt;
else if(controlALU[5:0] == SHR)
outALU = rs >> rt;
else if(controlALU[5:0] == BEQ)
outALU = (rs == rt);
else if(controlALU[5:0] == BGT)
outALU = (rs > rt);
else if(controlALU[5:0] == BGE)
outALU = (rs >= rt);
else if(controlALU[5:0] == BLT)
outALU = (rs < rt);
else if(controlALU[5:0] == BLE)
outALU = (rs <= rt);
else if(controlALU[5:0] == BNE)
outALU = (rs != rt);
else if(controlALU[5:0] == MOVE)
outALU = rs;
else
outALU = rs;
end
begin
if(controlALU[5:0] == BEQ ||
controlALU[5:0] == BGT ||
controlALU[5:0] == BGE ||
controlALU[5:0] == BLT ||
controlALU[5:0] == BLE ||
controlALU[5:0] == BNE)
outBranch = 1'b1;
else
outBranch = 1'b0;
end
end
endmodule
|
module sha512_core(
input wire clk,
input wire reset_n,
input wire init,
input wire next,
input wire [1 : 0] mode,
input wire work_factor,
input wire [31 : 0] work_factor_num,
input wire [1023 : 0] block,
output wire ready,
output wire [511 : 0] digest,
output wire digest_valid
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam SHA512_ROUNDS = 79;
localparam CTRL_IDLE = 2'h0;
localparam CTRL_ROUNDS = 2'h1;
localparam CTRL_DONE = 2'h2;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [63 : 0] a_reg;
reg [63 : 0] a_new;
reg [63 : 0] b_reg;
reg [63 : 0] b_new;
reg [63 : 0] c_reg;
reg [63 : 0] c_new;
reg [63 : 0] d_reg;
reg [63 : 0] d_new;
reg [63 : 0] e_reg;
reg [63 : 0] e_new;
reg [63 : 0] f_reg;
reg [63 : 0] f_new;
reg [63 : 0] g_reg;
reg [63 : 0] g_new;
reg [63 : 0] h_reg;
reg [63 : 0] h_new;
reg a_h_we;
reg [63 : 0] H0_reg;
reg [63 : 0] H0_new;
reg [63 : 0] H1_reg;
reg [63 : 0] H1_new;
reg [63 : 0] H2_reg;
reg [63 : 0] H2_new;
reg [63 : 0] H3_reg;
reg [63 : 0] H3_new;
reg [63 : 0] H4_reg;
reg [63 : 0] H4_new;
reg [63 : 0] H5_reg;
reg [63 : 0] H5_new;
reg [63 : 0] H6_reg;
reg [63 : 0] H6_new;
reg [63 : 0] H7_reg;
reg [63 : 0] H7_new;
reg H_we;
reg [6 : 0] round_ctr_reg;
reg [6 : 0] round_ctr_new;
reg round_ctr_we;
reg round_ctr_inc;
reg round_ctr_rst;
reg [31 : 0] work_factor_ctr_reg;
reg [31 : 0] work_factor_ctr_new;
reg work_factor_ctr_rst;
reg work_factor_ctr_inc;
reg work_factor_ctr_we;
reg ready_reg;
reg ready_new;
reg ready_we;
reg digest_valid_reg;
reg digest_valid_new;
reg digest_valid_we;
reg [1 : 0] sha512_ctrl_reg;
reg [1 : 0] sha512_ctrl_new;
reg sha512_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg digest_init;
reg digest_update;
reg state_init;
reg state_update;
reg first_block;
reg [63 : 0] t1;
reg [63 : 0] t2;
wire [63 : 0] k_data;
reg w_init;
reg w_next;
wire [63 : 0] w_data;
wire [63 : 0] H0_0;
wire [63 : 0] H0_1;
wire [63 : 0] H0_2;
wire [63 : 0] H0_3;
wire [63 : 0] H0_4;
wire [63 : 0] H0_5;
wire [63 : 0] H0_6;
wire [63 : 0] H0_7;
//----------------------------------------------------------------
// Module instantiantions.
//----------------------------------------------------------------
sha512_k_constants k_constants_inst(
.addr(round_ctr_reg),
.K(k_data)
);
sha512_h_constants h_constants_inst(
.mode(mode),
.H0(H0_0),
.H1(H0_1),
.H2(H0_2),
.H3(H0_3),
.H4(H0_4),
.H5(H0_5),
.H6(H0_6),
.H7(H0_7)
);
sha512_w_mem w_mem_inst(
.clk(clk),
.reset_n(reset_n),
.block(block),
.init(w_init),
.next(w_next),
.w(w_data)
);
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign ready = ready_reg;
assign digest = {H0_reg, H1_reg, H2_reg, H3_reg,
H4_reg, H5_reg, H6_reg, H7_reg};
assign digest_valid = digest_valid_reg;
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
if (!reset_n)
begin
a_reg <= 64'h0;
b_reg <= 64'h0;
c_reg <= 64'h0;
d_reg <= 64'h0;
e_reg <= 64'h0;
f_reg <= 64'h0;
g_reg <= 64'h0;
h_reg <= 64'h0;
H0_reg <= 64'h0;
H1_reg <= 64'h0;
H2_reg <= 64'h0;
H3_reg <= 64'h0;
H4_reg <= 64'h0;
H5_reg <= 64'h0;
H6_reg <= 64'h0;
H7_reg <= 64'h0;
work_factor_ctr_reg <= 32'h0;
ready_reg <= 1'b1;
digest_valid_reg <= 1'b0;
round_ctr_reg <= 7'h0;
sha512_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (a_h_we)
begin
a_reg <= a_new;
b_reg <= b_new;
c_reg <= c_new;
d_reg <= d_new;
e_reg <= e_new;
f_reg <= f_new;
g_reg <= g_new;
h_reg <= h_new;
end
if (H_we)
begin
H0_reg <= H0_new;
H1_reg <= H1_new;
H2_reg <= H2_new;
H3_reg <= H3_new;
H4_reg <= H4_new;
H5_reg <= H5_new;
H6_reg <= H6_new;
H7_reg <= H7_new;
end
if (round_ctr_we)
round_ctr_reg <= round_ctr_new;
if (work_factor_ctr_we)
work_factor_ctr_reg <= work_factor_ctr_new;
if (ready_we)
ready_reg <= ready_new;
if (digest_valid_we)
digest_valid_reg <= digest_valid_new;
if (sha512_ctrl_we)
sha512_ctrl_reg <= sha512_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// digest_logic
//
// The logic needed to init as well as update the digest.
//----------------------------------------------------------------
always @*
begin : digest_logic
H0_new = 64'h0;
H1_new = 64'h0;
H2_new = 64'h0;
H3_new = 64'h0;
H4_new = 64'h0;
H5_new = 64'h0;
H6_new = 64'h0;
H7_new = 64'h0;
H_we = 0;
if (digest_init)
begin
H0_new = H0_0;
H1_new = H0_1;
H2_new = H0_2;
H3_new = H0_3;
H4_new = H0_4;
H5_new = H0_5;
H6_new = H0_6;
H7_new = H0_7;
H_we = 1;
end
if (digest_update)
begin
H0_new = H0_reg + a_reg;
H1_new = H1_reg + b_reg;
H2_new = H2_reg + c_reg;
H3_new = H3_reg + d_reg;
H4_new = H4_reg + e_reg;
H5_new = H5_reg + f_reg;
H6_new = H6_reg + g_reg;
H7_new = H7_reg + h_reg;
H_we = 1;
end
end // digest_logic
//----------------------------------------------------------------
// t1_logic
//
// The logic for the T1 function.
//----------------------------------------------------------------
always @*
begin : t1_logic
reg [63 : 0] sum1;
reg [63 : 0] ch;
sum1 = {e_reg[13 : 0], e_reg[63 : 14]} ^
{e_reg[17 : 0], e_reg[63 : 18]} ^
{e_reg[40 : 0], e_reg[63 : 41]};
ch = (e_reg & f_reg) ^ ((~e_reg) & g_reg);
t1 = h_reg + sum1 + ch + k_data + w_data;
end // t1_logic
//----------------------------------------------------------------
// t2_logic
//
// The logic for the T2 function
//----------------------------------------------------------------
always @*
begin : t2_logic
reg [63 : 0] sum0;
reg [63 : 0] maj;
sum0 = {a_reg[27 : 0], a_reg[63 : 28]} ^
{a_reg[33 : 0], a_reg[63 : 34]} ^
{a_reg[38 : 0], a_reg[63 : 39]};
maj = (a_reg & b_reg) ^ (a_reg & c_reg) ^ (b_reg & c_reg);
t2 = sum0 + maj;
end // t2_logic
//----------------------------------------------------------------
// state_logic
//
// The logic needed to init as well as update the state during
// round processing.
//----------------------------------------------------------------
always @*
begin : state_logic
a_new = 64'h0;
b_new = 64'h0;
c_new = 64'h0;
d_new = 64'h0;
e_new = 64'h0;
f_new = 64'h0;
g_new = 64'h0;
h_new = 64'h0;
a_h_we = 0;
if (state_init)
begin
if (first_block)
begin
a_new = H0_0;
b_new = H0_1;
c_new = H0_2;
d_new = H0_3;
e_new = H0_4;
f_new = H0_5;
g_new = H0_6;
h_new = H0_7;
a_h_we = 1;
end
else
begin
a_new = H0_reg;
b_new = H1_reg;
c_new = H2_reg;
d_new = H3_reg;
e_new = H4_reg;
f_new = H5_reg;
g_new = H6_reg;
h_new = H7_reg;
a_h_we = 1;
end
end
if (state_update)
begin
a_new = t1 + t2;
b_new = a_reg;
c_new = b_reg;
d_new = c_reg;
e_new = d_reg + t1;
f_new = e_reg;
g_new = f_reg;
h_new = g_reg;
a_h_we = 1;
end
end // state_logic
//----------------------------------------------------------------
// round_ctr
//
// Update logic for the round counter, a monotonically
// increasing counter with reset.
//----------------------------------------------------------------
always @*
begin : round_ctr
round_ctr_new = 7'h00;
round_ctr_we = 0;
if (round_ctr_rst)
begin
round_ctr_new = 7'h00;
round_ctr_we = 1;
end
if (round_ctr_inc)
begin
round_ctr_new = round_ctr_reg + 1'b1;
round_ctr_we = 1;
end
end // round_ctr
//----------------------------------------------------------------
// work_factor_ctr
//
// Work factor counter logic.
//----------------------------------------------------------------
always @*
begin : work_factor_ctr
work_factor_ctr_new = 32'h0;
work_factor_ctr_we = 0;
if (work_factor_ctr_rst)
begin
work_factor_ctr_new = 32'h0;
work_factor_ctr_we = 1;
end
if (work_factor_ctr_inc)
begin
work_factor_ctr_new = work_factor_ctr_reg + 1'b1;
work_factor_ctr_we = 1;
end
end // work_factor_ctr
//----------------------------------------------------------------
// sha512_ctrl_fsm
//
// Logic for the state machine controlling the core behaviour.
//----------------------------------------------------------------
always @*
begin : sha512_ctrl_fsm
digest_init = 1'b0;
digest_update = 1'b0;
state_init = 1'b0;
state_update = 1'b0;
first_block = 1'b0;
w_init = 1'b0;
w_next = 1'b0;
round_ctr_inc = 1'b0;
round_ctr_rst = 1'b0;
digest_valid_new = 1'b0;
digest_valid_we = 1'b0;
work_factor_ctr_rst = 1'b0;
work_factor_ctr_inc = 1'b0;
ready_new = 1'b0;
ready_we = 1'b0;
sha512_ctrl_new = CTRL_IDLE;
sha512_ctrl_we = 1'b0;
case (sha512_ctrl_reg)
CTRL_IDLE:
begin
if (init)
begin
ready_new = 1'b0;
ready_we = 1'b1;
work_factor_ctr_rst = 1;
digest_init = 1;
w_init = 1;
state_init = 1;
first_block = 1;
round_ctr_rst = 1;
digest_valid_new = 0;
digest_valid_we = 1;
sha512_ctrl_new = CTRL_ROUNDS;
sha512_ctrl_we = 1;
end
if (next)
begin
ready_new = 1'b0;
ready_we = 1'b1;
work_factor_ctr_rst = 1;
w_init = 1;
state_init = 1;
round_ctr_rst = 1;
digest_valid_new = 0;
digest_valid_we = 1;
sha512_ctrl_new = CTRL_ROUNDS;
sha512_ctrl_we = 1;
end
end
CTRL_ROUNDS:
begin
w_next = 1;
state_update = 1;
round_ctr_inc = 1;
if (round_ctr_reg == SHA512_ROUNDS)
begin
work_factor_ctr_inc = 1;
sha512_ctrl_new = CTRL_DONE;
sha512_ctrl_we = 1;
end
end
CTRL_DONE:
begin
if (work_factor)
begin
if (work_factor_ctr_reg < work_factor_num)
begin
w_init = 1'b1;
state_init = 1'b1;
round_ctr_rst = 1'b1;
sha512_ctrl_new = CTRL_ROUNDS;
sha512_ctrl_we = 1'b1;
end
else
begin
ready_new = 1'b1;
ready_we = 1'b1;
digest_update = 1'b1;
digest_valid_new = 1'b1;
digest_valid_we = 1'b1;
sha512_ctrl_new = CTRL_IDLE;
sha512_ctrl_we = 1'b1;
end
end
else
begin
ready_new = 1'b1;
ready_we = 1'b1;
digest_update = 1'b1;
digest_valid_new = 1'b1;
digest_valid_we = 1'b1;
sha512_ctrl_new = CTRL_IDLE;
sha512_ctrl_we = 1'b1;
end
end
default:
begin
end
endcase // case (sha512_ctrl_reg)
end // sha512_ctrl_fsm
endmodule
|
module spi_trx_t;
// ins
reg clk;
parameter TCLK = 20;
initial clk = 0;
always #(TCLK/2) clk = ~clk;
reg sck;
parameter TCLK_SCK = 55;
reg mosi;
reg ss;
reg [7:0] data_i;
reg ack_i;
spi_trx uut(
.clk(clk),
.sck(sck),
.mosi(mosi),
.ss(ss),
.data_i(data_i),
.ack_i(ack_i));
task spi_cycle;
input wire [7:0] data;
begin
mosi = data[7];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[6];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[5];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[4];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[3];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[2];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[1];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[0];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
end
endtask
initial begin
$dumpfile("spi_trx_t.lxt");
$dumpvars(0, spi_trx_t);
sck = 0;
mosi = 0;
ss = 1;
ack_i = 0;
#(TCLK*3);
data_i = 8'b10101011;
ack_i = 1;
#(TCLK);
ack_i = 0;
#(TCLK);
ss = 0;
spi_cycle(8'hab);
spi_cycle(8'hcd);
spi_cycle(8'hef);
#(TCLK*3);
$finish(2);
end
always @(posedge clk) begin
if(uut.ack_pop_o)
$display("uut.data_o: %x", uut.data_o);
end
endmodule
|
module sky130_fd_sc_hdll__tapvgnd (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
|
module MotorFeedback_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 5
)
(
// Users to add ports here
input wire m1_feedback,
input wire m2_feedback,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
MotorFeedback_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) MotorFeedback_v1_0_S00_AXI_inst (
.m1_feedback(m1_feedback),
.m2_feedback(m2_feedback),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
|
module Approx_adder_W16 ( add_sub, in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
input add_sub;
wire n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47,
n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61,
n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75,
n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89,
n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102,
n103, n104, n105, n106, n107, n108, n109, n110, n111, n112, n113,
n114, n115, n116, n117, n118, n119, n120, n121, n122, n123, n124,
n125, n126;
NAND2XLTS U52 ( .A(n108), .B(n107), .Y(n109) );
NAND2X1TS U53 ( .A(n118), .B(n116), .Y(n104) );
OR2X2TS U54 ( .A(n61), .B(in1[11]), .Y(n97) );
OAI21X1TS U55 ( .A0(n37), .A1(in2[14]), .B0(add_sub), .Y(n36) );
XOR2X1TS U56 ( .A(n60), .B(in2[11]), .Y(n61) );
NAND2BX2TS U57 ( .AN(in2[13]), .B(n39), .Y(n37) );
NAND2X1TS U58 ( .A(n56), .B(add_sub), .Y(n57) );
NOR2X1TS U59 ( .A(n44), .B(n34), .Y(n45) );
NOR2X6TS U60 ( .A(n78), .B(in2[4]), .Y(n81) );
NOR2XLTS U61 ( .A(n48), .B(n34), .Y(n49) );
NAND2X1TS U62 ( .A(n63), .B(in1[12]), .Y(n101) );
XOR2X1TS U63 ( .A(n124), .B(n123), .Y(res[15]) );
XOR2X1TS U64 ( .A(n95), .B(n94), .Y(res[10]) );
NOR2X6TS U65 ( .A(n50), .B(in2[6]), .Y(n48) );
AOI21X2TS U66 ( .A0(n119), .A1(n118), .B0(n117), .Y(n124) );
OR2X2TS U67 ( .A(n63), .B(in1[12]), .Y(n43) );
XNOR2X2TS U68 ( .A(n42), .B(in2[12]), .Y(n63) );
XNOR2X2TS U69 ( .A(n38), .B(in2[14]), .Y(n68) );
NOR2X2TS U70 ( .A(n39), .B(n34), .Y(n40) );
NOR2X4TS U71 ( .A(n56), .B(in2[10]), .Y(n59) );
AOI21X2TS U72 ( .A0(n108), .A1(n105), .B0(n65), .Y(n66) );
NAND2X2TS U73 ( .A(n68), .B(in1[14]), .Y(n116) );
NAND2X2TS U74 ( .A(n108), .B(n43), .Y(n67) );
NAND2X2TS U75 ( .A(n41), .B(add_sub), .Y(n42) );
NOR2X4TS U76 ( .A(n53), .B(in1[9]), .Y(n86) );
NOR2X4TS U77 ( .A(n69), .B(in1[15]), .Y(n120) );
XOR2X1TS U78 ( .A(n90), .B(n89), .Y(res[9]) );
XOR2X2TS U79 ( .A(n40), .B(in2[13]), .Y(n64) );
INVX2TS U80 ( .A(n112), .Y(n85) );
XNOR2X2TS U81 ( .A(n47), .B(in2[8]), .Y(n52) );
NAND2BXLTS U82 ( .AN(in1[5]), .B(n83), .Y(res[5]) );
NAND2BXLTS U83 ( .AN(in1[4]), .B(n80), .Y(res[4]) );
XOR2X1TS U84 ( .A(n79), .B(in2[4]), .Y(n80) );
OAI21XLTS U85 ( .A0(in2[2]), .A1(n75), .B0(n74), .Y(res[2]) );
OAI21XLTS U86 ( .A0(in2[1]), .A1(n73), .B0(n72), .Y(res[1]) );
OAI21XLTS U87 ( .A0(in2[3]), .A1(n77), .B0(n76), .Y(res[3]) );
INVX4TS U88 ( .A(add_sub), .Y(n34) );
OR2X1TS U89 ( .A(in2[0]), .B(in1[0]), .Y(res[0]) );
NOR2X4TS U90 ( .A(n41), .B(in2[12]), .Y(n39) );
AOI21X4TS U91 ( .A0(n55), .A1(n115), .B0(n54), .Y(n95) );
NAND2BX4TS U92 ( .AN(in2[7]), .B(n48), .Y(n46) );
XNOR2X2TS U93 ( .A(n36), .B(in2[15]), .Y(n69) );
XOR2X1TS U94 ( .A(n51), .B(in2[6]), .Y(n111) );
NAND2X1TS U95 ( .A(n113), .B(n112), .Y(n114) );
NAND2X1TS U96 ( .A(n97), .B(n96), .Y(n98) );
NAND2X1TS U97 ( .A(n43), .B(n101), .Y(n102) );
INVX2TS U98 ( .A(n34), .Y(n35) );
NAND2X2TS U99 ( .A(n46), .B(add_sub), .Y(n47) );
ADDFHX2TS U100 ( .A(n126), .B(in1[7]), .CI(n125), .CO(n115), .S(res[7]) );
AOI21X4TS U101 ( .A0(n99), .A1(n97), .B0(n62), .Y(n100) );
NAND2BX4TS U102 ( .AN(in2[9]), .B(n44), .Y(n56) );
XOR2X4TS U103 ( .A(n45), .B(in2[9]), .Y(n53) );
NAND2X2TS U104 ( .A(n37), .B(add_sub), .Y(n38) );
OAI21X4TS U105 ( .A0(n67), .A1(n100), .B0(n66), .Y(n119) );
NOR2XLTS U106 ( .A(n81), .B(n34), .Y(n82) );
OR4X6TS U107 ( .A(in2[3]), .B(in2[2]), .C(in2[1]), .D(in2[0]), .Y(n78) );
NAND2BX4TS U108 ( .AN(in2[5]), .B(n81), .Y(n50) );
NOR2X8TS U109 ( .A(n46), .B(in2[8]), .Y(n44) );
NAND2BX4TS U110 ( .AN(in2[11]), .B(n59), .Y(n41) );
NOR2X2TS U111 ( .A(n68), .B(in1[14]), .Y(n103) );
NOR2X1TS U112 ( .A(n120), .B(n103), .Y(n71) );
OR2X2TS U113 ( .A(n64), .B(in1[13]), .Y(n108) );
NOR2X2TS U114 ( .A(n52), .B(in1[8]), .Y(n84) );
NOR2X1TS U115 ( .A(n86), .B(n84), .Y(n55) );
XOR2X1TS U116 ( .A(n49), .B(in2[7]), .Y(n126) );
NAND2X1TS U117 ( .A(n50), .B(n35), .Y(n51) );
NOR2BX1TS U118 ( .AN(in1[6]), .B(n111), .Y(n125) );
NAND2X2TS U119 ( .A(n52), .B(in1[8]), .Y(n112) );
NAND2X2TS U120 ( .A(n53), .B(in1[9]), .Y(n87) );
OAI21X1TS U121 ( .A0(n86), .A1(n112), .B0(n87), .Y(n54) );
XNOR2X1TS U122 ( .A(n57), .B(in2[10]), .Y(n58) );
NOR2X2TS U123 ( .A(n58), .B(in1[10]), .Y(n91) );
NAND2X2TS U124 ( .A(n58), .B(in1[10]), .Y(n92) );
OAI21X4TS U125 ( .A0(n95), .A1(n91), .B0(n92), .Y(n99) );
NOR2X1TS U126 ( .A(n59), .B(n34), .Y(n60) );
NAND2X2TS U127 ( .A(n61), .B(in1[11]), .Y(n96) );
INVX2TS U128 ( .A(n96), .Y(n62) );
INVX2TS U129 ( .A(n101), .Y(n105) );
NAND2X2TS U130 ( .A(n64), .B(in1[13]), .Y(n107) );
INVX2TS U131 ( .A(n107), .Y(n65) );
NAND2X2TS U132 ( .A(n69), .B(in1[15]), .Y(n121) );
OAI21X1TS U133 ( .A0(n120), .A1(n116), .B0(n121), .Y(n70) );
AO21X2TS U134 ( .A0(n71), .A1(n119), .B0(n70), .Y(res[16]) );
NAND2X1TS U135 ( .A(in2[0]), .B(add_sub), .Y(n73) );
AOI21X1TS U136 ( .A0(in2[1]), .A1(n73), .B0(in1[1]), .Y(n72) );
OAI21X1TS U137 ( .A0(in2[1]), .A1(in2[0]), .B0(add_sub), .Y(n75) );
AOI21X1TS U138 ( .A0(in2[2]), .A1(n75), .B0(in1[2]), .Y(n74) );
OAI31X1TS U139 ( .A0(in2[2]), .A1(in2[1]), .A2(in2[0]), .B0(add_sub), .Y(n77) );
AOI21X1TS U140 ( .A0(in2[3]), .A1(n77), .B0(in1[3]), .Y(n76) );
NAND2X1TS U141 ( .A(n78), .B(add_sub), .Y(n79) );
XNOR2X1TS U142 ( .A(n82), .B(in2[5]), .Y(n83) );
INVX2TS U143 ( .A(n84), .Y(n113) );
AOI21X1TS U144 ( .A0(n115), .A1(n113), .B0(n85), .Y(n90) );
INVX2TS U145 ( .A(n86), .Y(n88) );
NAND2X1TS U146 ( .A(n88), .B(n87), .Y(n89) );
INVX2TS U147 ( .A(n91), .Y(n93) );
NAND2X1TS U148 ( .A(n93), .B(n92), .Y(n94) );
XNOR2X1TS U149 ( .A(n99), .B(n98), .Y(res[11]) );
INVX2TS U150 ( .A(n100), .Y(n106) );
XNOR2X1TS U151 ( .A(n106), .B(n102), .Y(res[12]) );
INVX2TS U152 ( .A(n103), .Y(n118) );
XNOR2X1TS U153 ( .A(n119), .B(n104), .Y(res[14]) );
AOI21X1TS U154 ( .A0(n106), .A1(n43), .B0(n105), .Y(n110) );
XOR2X1TS U155 ( .A(n110), .B(n109), .Y(res[13]) );
NAND2BXLTS U156 ( .AN(in1[6]), .B(n111), .Y(res[6]) );
XNOR2X1TS U157 ( .A(n115), .B(n114), .Y(res[8]) );
INVX2TS U158 ( .A(n116), .Y(n117) );
INVX2TS U159 ( .A(n120), .Y(n122) );
NAND2X2TS U160 ( .A(n122), .B(n121), .Y(n123) );
initial $sdf_annotate("Approx_adder_LOALPL7_syn.sdf");
endmodule
|
module flappy_bird(
//////////////////// Clock Input ////////////////////
CLOCK_27, // On Board 27 MHz
CLOCK_50, // On Board 50 MHz
EXT_CLOCK, // External Clock
//////////////////// Push Button ////////////////////
KEY, // Pushbutton[3:0]
//////////////////// DPDT Switch ////////////////////
SW, // Toggle Switch[17:0]
//////////////////// 7-SEG Dispaly ////////////////////
HEX0, // Seven Segment Digit 0
HEX1, // Seven Segment Digit 1
HEX2, // Seven Segment Digit 2
HEX3, // Seven Segment Digit 3
HEX4, // Seven Segment Digit 4
HEX5, // Seven Segment Digit 5
HEX6, // Seven Segment Digit 6
HEX7, // Seven Segment Digit 7
//////////////////////// LED ////////////////////////
LEDG, // LED Green[8:0]
LEDR, // LED Red[17:0]
//////////////////////// UART ////////////////////////
UART_TXD, // UART Transmitter
UART_RXD, // UART Receiver
//////////////////////// IRDA ////////////////////////
IRDA_TXD, // IRDA Transmitter
IRDA_RXD, // IRDA Receiver
///////////////////// SDRAM Interface ////////////////
DRAM_DQ, // SDRAM Data bus 16 Bits
DRAM_ADDR, // SDRAM Address bus 12 Bits
DRAM_LDQM, // SDRAM Low-byte Data Mask
DRAM_UDQM, // SDRAM High-byte Data Mask
DRAM_WE_N, // SDRAM Write Enable
DRAM_CAS_N, // SDRAM Column Address Strobe
DRAM_RAS_N, // SDRAM Row Address Strobe
DRAM_CS_N, // SDRAM Chip Select
DRAM_BA_0, // SDRAM Bank Address 0
DRAM_BA_1, // SDRAM Bank Address 1
DRAM_CLK, // SDRAM Clock
DRAM_CKE, // SDRAM Clock Enable
//////////////////// Flash Interface ////////////////
FL_DQ, // FLASH Data bus 8 Bits
FL_ADDR, // FLASH Address bus 20 Bits
FL_WE_N, // FLASH Write Enable
FL_RST_N, // FLASH Reset
FL_OE_N, // FLASH Output Enable
FL_CE_N, // FLASH Chip Enable
//////////////////// SRAM Interface ////////////////
SRAM_DQ, // SRAM Data bus 16 Bits
SRAM_ADDR, // SRAM Address bus 18 Bits
SRAM_UB_N, // SRAM High-byte Data Mask
SRAM_LB_N, // SRAM Low-byte Data Mask
SRAM_WE_N, // SRAM Write Enable
SRAM_CE_N, // SRAM Chip Enable
SRAM_OE_N, // SRAM Output Enable
//////////////////// ISP1362 Interface ////////////////
OTG_DATA, // ISP1362 Data bus 16 Bits
OTG_ADDR, // ISP1362 Address 2 Bits
OTG_CS_N, // ISP1362 Chip Select
OTG_RD_N, // ISP1362 Write
OTG_WR_N, // ISP1362 Read
OTG_RST_N, // ISP1362 Reset
OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable
OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable
OTG_INT0, // ISP1362 Interrupt 0
OTG_INT1, // ISP1362 Interrupt 1
OTG_DREQ0, // ISP1362 DMA Request 0
OTG_DREQ1, // ISP1362 DMA Request 1
OTG_DACK0_N, // ISP1362 DMA Acknowledge 0
OTG_DACK1_N, // ISP1362 DMA Acknowledge 1
//////////////////// LCD Module 16X2 ////////////////
LCD_ON, // LCD Power ON/OFF
LCD_BLON, // LCD Back Light ON/OFF
LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
LCD_EN, // LCD Enable
LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
LCD_DATA, // LCD Data bus 8 bits
//////////////////// SD_Card Interface ////////////////
SD_DAT, // SD Card Data
SD_WP_N, // SD Write protect
SD_CMD, // SD Card Command Signal
SD_CLK, // SD Card Clock
//////////////////// USB JTAG link ////////////////////
TDI, // CPLD -> FPGA (Data in)
TCK, // CPLD -> FPGA (Clock)
TCS, // CPLD -> FPGA (CS)
TDO, // FPGA -> CPLD (Data out)
//////////////////// I2C ////////////////////////////
I2C_SDAT, // I2C Data
I2C_SCLK, // I2C Clock
//////////////////// PS2 ////////////////////////////
PS2_DAT, // PS2 Data
PS2_CLK, // PS2 Clock
//////////////////// VGA ////////////////////////////
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK, // VGA BLANK
VGA_SYNC, // VGA SYNC
VGA_R, // VGA Red[9:0]
VGA_G, // VGA Green[9:0]
VGA_B, // VGA Blue[9:0]
//////////// Ethernet Interface ////////////////////////
ENET_DATA, // DM9000A DATA bus 16Bits
ENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
ENET_CS_N, // DM9000A Chip Select
ENET_WR_N, // DM9000A Write
ENET_RD_N, // DM9000A Read
ENET_RST_N, // DM9000A Reset
ENET_INT, // DM9000A Interrupt
ENET_CLK, // DM9000A Clock 25 MHz
//////////////// Audio CODEC ////////////////////////
AUD_ADCLRCK, // Audio CODEC ADC LR Clock
AUD_ADCDAT, // Audio CODEC ADC Data
AUD_DACLRCK, // Audio CODEC DAC LR Clock
AUD_DACDAT, // Audio CODEC DAC Data
AUD_BCLK, // Audio CODEC Bit-Stream Clock
AUD_XCK, // Audio CODEC Chip Clock
//////////////// TV Decoder ////////////////////////
TD_DATA, // TV Decoder Data bus 8 bits
TD_HS, // TV Decoder H_SYNC
TD_VS, // TV Decoder V_SYNC
TD_RESET, // TV Decoder Reset
TD_CLK, // TV Decoder Line Locked Clock
//iTD_CLK, // TV Decoder Line Locked Clock
//////////////////// GPIO ////////////////////////////
GPIO_0, // GPIO Connection 0
GPIO_1 // GPIO Connection 1
);
//////////////////////// Clock Input ////////////////////////
input CLOCK_27; // On Board 27 MHz
input CLOCK_50; // On Board 50 MHz
input EXT_CLOCK; // External Clock
//////////////////////// Push Button ////////////////////////
input [3:0] KEY; // Pushbutton[3:0]
//////////////////////// DPDT Switch ////////////////////////
input [17:0] SW; // Toggle Switch[17:0]
//////////////////////// 7-SEG Display ////////////////////////
output [6:0] HEX0; // Seven Segment Digit 0
output [6:0] HEX1; // Seven Segment Digit 1
output [6:0] HEX2; // Seven Segment Digit 2
output [6:0] HEX3; // Seven Segment Digit 3
output [6:0] HEX4; // Seven Segment Digit 4
output [6:0] HEX5; // Seven Segment Digit 5
output [6:0] HEX6; // Seven Segment Digit 6
output [6:0] HEX7; // Seven Segment Digit 7
//////////////////////////// LED ////////////////////////////
output [8:0] LEDG; // LED Green[8:0]
output [17:0] LEDR; // LED Red[17:0]
//////////////////////////// UART ////////////////////////////
output UART_TXD; // UART Transmitter
input UART_RXD; // UART Receiver
//////////////////////////// IRDA ////////////////////////////
output IRDA_TXD; // IRDA Transmitter
input IRDA_RXD; // IRDA Receiver
/////////////////////// SDRAM Interface ////////////////////////
inout [15:0] DRAM_DQ; // SDRAM Data bus 16 Bits
output [11:0] DRAM_ADDR; // SDRAM Address bus 12 Bits
output DRAM_LDQM; // SDRAM Low-byte Data Mask
output DRAM_UDQM; // SDRAM High-byte Data Mask
output DRAM_WE_N; // SDRAM Write Enable
output DRAM_CAS_N; // SDRAM Column Address Strobe
output DRAM_RAS_N; // SDRAM Row Address Strobe
output DRAM_CS_N; // SDRAM Chip Select
output DRAM_BA_0; // SDRAM Bank Address 0
output DRAM_BA_1; // SDRAM Bank Address 0
output DRAM_CLK; // SDRAM Clock
output DRAM_CKE; // SDRAM Clock Enable
//////////////////////// Flash Interface ////////////////////////
inout [7:0] FL_DQ; // FLASH Data bus 8 Bits
output [21:0] FL_ADDR; // FLASH Address bus 22 Bits
output FL_WE_N; // FLASH Write Enable
output FL_RST_N; // FLASH Reset
output FL_OE_N; // FLASH Output Enable
output FL_CE_N; // FLASH Chip Enable
//////////////////////// SRAM Interface ////////////////////////
inout [15:0] SRAM_DQ; // SRAM Data bus 16 Bits
output [17:0] SRAM_ADDR; // SRAM Address bus 18 Bits
output SRAM_UB_N; // SRAM Low-byte Data Mask
output SRAM_LB_N; // SRAM High-byte Data Mask
output SRAM_WE_N; // SRAM Write Enable
output SRAM_CE_N; // SRAM Chip Enable
output SRAM_OE_N; // SRAM Output Enable
//////////////////// ISP1362 Interface ////////////////////////
inout [15:0] OTG_DATA; // ISP1362 Data bus 16 Bits
output [1:0] OTG_ADDR; // ISP1362 Address 2 Bits
output OTG_CS_N; // ISP1362 Chip Select
output OTG_RD_N; // ISP1362 Write
output OTG_WR_N; // ISP1362 Read
output OTG_RST_N; // ISP1362 Reset
output OTG_FSPEED; // USB Full Speed, 0 = Enable, Z = Disable
output OTG_LSPEED; // USB Low Speed, 0 = Enable, Z = Disable
input OTG_INT0; // ISP1362 Interrupt 0
input OTG_INT1; // ISP1362 Interrupt 1
input OTG_DREQ0; // ISP1362 DMA Request 0
input OTG_DREQ1; // ISP1362 DMA Request 1
output OTG_DACK0_N; // ISP1362 DMA Acknowledge 0
output OTG_DACK1_N; // ISP1362 DMA Acknowledge 1
//////////////////// LCD Module 16X2 ////////////////////////////
inout [7:0] LCD_DATA; // LCD Data bus 8 bits
output LCD_ON; // LCD Power ON/OFF
output LCD_BLON; // LCD Back Light ON/OFF
output LCD_RW; // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN; // LCD Enable
output LCD_RS; // LCD Command/Data Select, 0 = Command, 1 = Data
//////////////////// SD Card Interface ////////////////////////
inout [3:0] SD_DAT; // SD Card Data
input SD_WP_N; // SD write protect
inout SD_CMD; // SD Card Command Signal
output SD_CLK; // SD Card Clock
//////////////////////// I2C ////////////////////////////////
inout I2C_SDAT; // I2C Data
output I2C_SCLK; // I2C Clock
//////////////////////// PS2 ////////////////////////////////
input PS2_DAT; // PS2 Data
input PS2_CLK; // PS2 Clock
//////////////////// USB JTAG link ////////////////////////////
input TDI; // CPLD -> FPGA (data in)
input TCK; // CPLD -> FPGA (clk)
input TCS; // CPLD -> FPGA (CS)
output TDO; // FPGA -> CPLD (data out)
//////////////////////// VGA ////////////////////////////
output VGA_CLK; // VGA Clock
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output VGA_BLANK; // VGA BLANK
output VGA_SYNC; // VGA SYNC
output [9:0] VGA_R; // VGA Red[9:0]
output [9:0] VGA_G; // VGA Green[9:0]
output [9:0] VGA_B; // VGA Blue[9:0]
//////////////// Ethernet Interface ////////////////////////////
inout [15:0] ENET_DATA; // DM9000A DATA bus 16Bits
output ENET_CMD; // DM9000A Command/Data Select, 0 = Command, 1 = Data
output ENET_CS_N; // DM9000A Chip Select
output ENET_WR_N; // DM9000A Write
output ENET_RD_N; // DM9000A Read
output ENET_RST_N; // DM9000A Reset
input ENET_INT; // DM9000A Interrupt
output ENET_CLK; // DM9000A Clock 25 MHz
//////////////////// Audio CODEC ////////////////////////////
inout AUD_ADCLRCK; // Audio CODEC ADC LR Clock
input AUD_ADCDAT; // Audio CODEC ADC Data
inout AUD_DACLRCK; // Audio CODEC DAC LR Clock
output AUD_DACDAT; // Audio CODEC DAC Data
inout AUD_BCLK; // Audio CODEC Bit-Stream Clock
output AUD_XCK; // Audio CODEC Chip Clock
//////////////////// TV Devoder ////////////////////////////
input [7:0] TD_DATA; // TV Decoder Data bus 8 bits
input TD_HS; // TV Decoder H_SYNC
input TD_VS; // TV Decoder V_SYNC
output TD_RESET; // TV Decoder Reset
input TD_CLK; // TV Decoder Line Locked Clock
//input iTD_CLK; // TV Decoder Line Locked Clock
//////////////////////// GPIO ////////////////////////////////
inout [35:0] GPIO_0; // GPIO Connection 0
inout [35:0] GPIO_1; // GPIO Connection 1
// Flash
assign FL_RST_N = 1'b1;
wire FL_16BIT_IP_A0;
// 16*2 LCD Module
assign LCD_ON = 1'b1; // LCD ON
assign LCD_BLON = 1'b1; // LCD Back Light
// All inout port turn to tri-state
assign SD_DAT[0] = 1'bz;
assign AUD_ADCLRCK = AUD_DACLRCK;
assign GPIO_0 = 36'hzzzzzzzzz;
assign GPIO_1 = 36'hzzzzzzzzz;
// Disable USB speed select
assign OTG_FSPEED = 1'bz;
assign OTG_LSPEED = 1'bz;
// Turn On TV Decoder
assign TD_RESET = KEY[0];
// Set SD Card to SD Mode
wire [3:1] SD_DAT_dummy;
assign SD_DAT_dummy = 3'bzzz;
assign SD_DAT[3] = 1'b1;
//========== SSRAM
wire [1:0] SRAM_DUMMY_ADDR; // used to ignore the A0/A1 pin from Cypress SSRAM IP core
wire [15:0] SRAM_DUMMY_DQ;
//========== SDRAM
assign DRAM_CLK = pll_c1_memory;
wire CPU_RESET_N;
wire pll_c0_system, pll_c1_memory, pll_c2_audio;
// Reset
Reset_Delay delay1 (.iRST(KEY[0]),.iCLK(CLOCK_50),.oRESET(CPU_RESET_N));
//Example instantiation for system 'kernel'
kernel kernel_inst
(
.SRAM_ADDR_from_the_sram_16bit_512k_0 (SRAM_ADDR),
.SRAM_CE_N_from_the_sram_16bit_512k_0 (SRAM_CE_N),
.SRAM_DQ_to_and_from_the_sram_16bit_512k_0 (SRAM_DQ),
.SRAM_LB_N_from_the_sram_16bit_512k_0 (SRAM_LB_N),
.SRAM_OE_N_from_the_sram_16bit_512k_0 (SRAM_OE_N),
.SRAM_UB_N_from_the_sram_16bit_512k_0 (SRAM_UB_N),
.SRAM_WE_N_from_the_sram_16bit_512k_0 (SRAM_WE_N),
.clk_50 (CLOCK_50),
.VGA_BLANK_from_the_vga_0 (VGA_BLANK),
.VGA_B_from_the_vga_0 (VGA_B),
.VGA_CLK_from_the_vga_0 (VGA_CLK),
.VGA_G_from_the_vga_0 (VGA_G),
.VGA_HS_from_the_vga_0 (VGA_HS),
.VGA_R_from_the_vga_0 (VGA_R),
.VGA_SYNC_from_the_vga_0 (VGA_SYNC),
.VGA_VS_from_the_vga_0 (VGA_VS),
.iCLK_25_to_the_vga_0 (CLOCK_27),
.in_port_to_the_gpio (GPIO_0[0]),
.in_port_to_the_key (~KEY[1]),
.in_port_to_the_hardmodle (SW[3:0]),
.LCD_E_from_the_lcd_0 (LCD_EN),
.LCD_RS_from_the_lcd_0 (LCD_RS),
.LCD_RW_from_the_lcd_0 (LCD_RW),
.LCD_data_to_and_from_the_lcd_0 (LCD_DATA),
//.in_port_to_the_pio_sw (SW[17:0]),
//.out_port_from_the_pio_green (LEDG),
//.out_port_from_the_pio_red (LEDR),
.reset_n (CPU_RESET_N),
.select_n_to_the_cfi_flash (FL_CE_N),
.tri_state_bridge_address (FL_ADDR),
.tri_state_bridge_data (FL_DQ),
.tri_state_bridge_readn (FL_OE_N),
.write_n_to_the_cfi_flash (FL_WE_N)
);
endmodule
|
module Reset_Delay(iRST,iCLK,oRESET);
input iCLK;
input iRST;
output reg oRESET;
reg [27:0] Cont;
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
begin
oRESET <= 1'b0;
Cont <= 28'h0000000;
end
else
begin
if(Cont!=28'h4FFFFFF) // about 300ms at 50MHz
begin
Cont <= Cont+1;
oRESET <= 1'b0;
end
else
oRESET <= 1'b1;
end
end
endmodule
|
module qmem_sram #(
parameter AW = 32,
parameter DW = 32,
parameter SW = DW/8
)(
// system signals
input wire clk50,
input wire clk100,
input wire rst,
// qmem bus
input wire [AW-1:0] adr,
input wire cs,
input wire we,
input wire [SW-1:0] sel,
input wire [DW-1:0] dat_w,
output reg [DW-1:0] dat_r,
output wire ack,
output wire err,
// SRAM interface
output wire [18-1:0] sram_adr,
output wire sram_ce_n,
output wire sram_we_n,
output wire sram_ub_n,
output wire sram_lb_n,
output wire sram_oe_n,
output wire [16-1:0] sram_dat_w,
input wire [16-1:0] sram_dat_r
);
`ifndef QMEM_SRAM_ASYNC
////////////////////////////////////////
// registered outputs variant //
////////////////////////////////////////
/* state */
localparam S_ID = 3'b000; // idle
localparam S_HI1 = 3'b011; // first access, write upper 16 bits
localparam S_HI2 = 3'b111;
localparam S_LO1 = 3'b010; // second access, write lower 16 bits, latch upper 16 bits
localparam S_LO2 = 3'b110;
localparam S_FH = 3'b001; // last read, latch lower 16 bits
reg [2:0] state, next_state;
always @ (*)
begin
case (state)
S_ID : begin if (cs) next_state = S_HI1; else next_state = S_ID; end
S_HI1 : begin if (cs) next_state = S_HI2; else next_state = S_ID; end
S_HI2 : begin if (cs) next_state = S_LO1; else next_state = S_ID; end
S_LO1 : begin if (cs) next_state = S_LO2; else next_state = S_ID; end
S_LO2 : begin if (cs) next_state = S_FH; else next_state = S_ID; end
S_FH : begin next_state = S_ID; end
default : begin next_state = S_ID; end
endcase
end
always @ (posedge clk100 or posedge rst)
begin
if (rst)
state <= #1 S_ID;
else
state <= #1 next_state;
end
/* output registers */
// address
reg [17:0] s_adr;
always @ (posedge clk100)
begin
if (next_state == S_HI1)
s_adr <= #1 {adr[18:2], 1'b0};
else if (next_state == S_LO1)
s_adr <= #1 {adr[18:2], 1'b1};
end
// ce_n
reg s_ce_n;
always @ (posedge clk100 or posedge rst)
begin
if (rst)
s_ce_n <= #1 1'b1;
else if ((next_state == S_HI1) || (next_state == S_HI2) || (next_state == S_LO1) || (next_state == S_LO2))
s_ce_n <= #1 1'b0;
else
s_ce_n <= #1 1'b1;
end
// we_n
reg s_we_n;
always @ (posedge clk100)
begin
if ((next_state == S_HI1) || (next_state == S_HI2) || (next_state == S_LO1) || (next_state == S_LO2))
s_we_n <= #1 !we;
end
// ub_n & lb_n
reg s_ub_n, s_lb_n;
always @ (posedge clk100)
begin
if (next_state == S_HI1)
{s_ub_n, s_lb_n} <= #1 {!sel[3], !sel[2]};
else if (next_state == S_LO1)
{s_ub_n, s_lb_n} <= #1 {!sel[1], !sel[0]};
end
// oe_n
reg s_oe_n;
always @ (posedge clk100)
begin
if ((next_state == S_HI1) || (next_state == S_HI2) || (next_state == S_LO1) || (next_state == S_LO2))
s_oe_n <= #1 we;
else
s_oe_n <= #1 1'b0;
end
// dat_w
reg [15:0] s_dat_w;
always @ (posedge clk100)
begin
if (next_state == S_HI1)
s_dat_w <= #1 dat_w[31:16];
else if (next_state == S_LO1)
s_dat_w <= #1 dat_w[15:0];
end
/* inputs */
// dat_r
reg [31:0] s_dat_r;
always @ (posedge clk100)
begin
if ((next_state == S_LO1) && !we)
dat_r[31:16] <= #1 sram_dat_r;
else if ((next_state == S_FH) && !we)
dat_r[15: 0] <= #1 sram_dat_r;
end
// ack
reg s_ack;
always @ (posedge clk100 or posedge rst)
begin
if (rst)
s_ack <= #1 1'b0;
else if ((state == S_LO2) || (state == S_FH))
s_ack <= #1 1'b1;
else
s_ack <= #1 1'b0;
end
/* output assignments */
assign sram_adr = s_adr;
assign sram_ce_n = s_ce_n;
assign sram_we_n = s_we_n;
assign sram_ub_n = s_ub_n;
assign sram_lb_n = s_lb_n;
assign sram_oe_n = s_oe_n;
assign sram_dat_w = s_dat_w;
assign ack = s_ack;
assign err = 1'b0;
`else
////////////////////////////////////////
// async outputs variant //
////////////////////////////////////////
/* local signals */
reg [ AW-1:0] adr_r;
wire adr_changed;
reg cnt;
reg [ 16-1:0] rdat_r;
/* address change */
always @ (posedge clk50) adr_r <= #1 adr;
assign adr_changed = (adr != adr_r);
/* cs counter */
always @ (posedge clk50 or posedge rst)
begin
if (rst)
cnt <= #1 1'b0;
else if (adr_changed)
cnt <= #1 1'b0;
else if (cs)
cnt <= #1 !cnt;
end
/* read data reg */
always @ (posedge clk50) if (cs && !cnt && !we) rdat_r <= #1 sram_dat_r;
/* qmem outputs */
// TODO dat_r - check if a reg is needed! maybe should use address register!
always @ (posedge clk50) if (cs && cnt && !we) dat_r <= #1 {sram_dat_r, rdat_r};
//assign dat_r = {sram_dat_r, rdat_r};
assign ack = cnt;
assign err = 1'b0;
/* SRAM outputs */
assign sram_adr = (!cnt) ? {adr[18:2], 1'b0} : {adr[18:2], 1'b1};
assign sram_ce_n = !cs;
assign sram_we_n = !we;
assign sram_ub_n = !((!cnt) ? sel[1] : sel[3]);
assign sram_lb_n = !((!cnt) ? sel[0] : sel[2]);
assign sram_oe_n = we;
assign sram_dat_w = (!cnt) ? dat_w[15:0] : dat_w[31:16];
`endif
endmodule
|
module sky130_fd_sc_hd__a311oi_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_hd__a311oi_1 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
|
module VICTIM_CACHE_SIMULATION();
parameter BLOCK_WIDTH = 512 ;
parameter TAG_WIDTH = 26 ;
parameter MEMORY_LATENCY = "HIGH_LATENCY" ;
localparam MEMORY_DEPTH = 4 ;
localparam ADDRESS_WIDTH = $clog2(MEMORY_DEPTH-1) ;
// Inputs
reg clk ;
reg [TAG_WIDTH - 1 : 0] write_tag_address ;
reg [BLOCK_WIDTH - 1 : 0] write_data ;
reg write_enable ;
reg [TAG_WIDTH - 1 : 0] read_tag_address ;
reg read_enble ;
// Outputs
wire read_hit ;
wire [BLOCK_WIDTH - 1 : 0] read_data ;
// Instantiate the Unit Under Test (UUT)
VICTIM_CACHE #(
.BLOCK_WIDTH(BLOCK_WIDTH),
.TAG_WIDTH(TAG_WIDTH),
.MEMORY_LATENCY(MEMORY_LATENCY)
)uut(
.CLK(clk),
.WRITE_TAG_ADDRESS(write_tag_address),
.WRITE_DATA(write_data),
.WRITE_ENABLE(write_enable),
.READ_TAG_ADDRESS(read_tag_address),
.READ_ENBLE(read_enble),
.READ_HIT(read_hit),
.READ_DATA(read_data)
);
initial
begin
// Initialize Inputs
clk = 1'b0 ;
write_tag_address = 26'b1 ;
write_data = 512'b1 ;
write_enable = 1'b1 ;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
clk = 1'b1 ;
#100;
clk = 1'b0 ;
write_tag_address = 26'b10 ;
write_data = 512'b10 ;
write_enable = 1'b1 ;
#100;
clk = 1'b1 ;
#100;
clk = 1'b0 ;
write_tag_address = 26'b0 ;
write_data = 512'b0 ;
write_enable = 1'b0 ;
read_tag_address = 26'b1 ;
read_enble = 1'b1 ;
#100;
clk = 1'b1 ;
#100;
clk = 1'b0 ;
read_tag_address = 26'b10 ;
read_enble = 1'b1 ;
#100;
clk = 1'b1 ;
#100;
clk = 1'b0 ;
read_tag_address = 26'b0 ;
read_enble = 1'b1 ;
#100;
clk = 1'b1 ;
#100;
clk = 1'b0 ;
#100;
clk = 1'b1 ;
end
endmodule
|
module th24w2 ( y, a, b, c, d );
output y;
input a, b, c, d;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th24w2";
specparam CDS_VIEWNAME = "schematic";
endspecify
nfet_b N15 ( .d(net051), .g(b), .s(net038), .b(cds_globals.gnd_));
nfet_b N14 ( .d(net051), .g(d), .s(net039), .b(cds_globals.gnd_));
nfet_b N5 ( .d(net051), .g(d), .s(net44), .b(cds_globals.gnd_));
nfet_b N4 ( .d(net039), .g(c), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N16 ( .d(net038), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N10 ( .d(net051), .g(c), .s(net44), .b(cds_globals.gnd_));
nfet_b N3 ( .d(net44), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N2 ( .d(net44), .g(b), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N1 ( .d(net051), .g(a), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
pfet_b P7 ( .b(cds_globals.vdd_), .g(b), .s(net49), .d(net032));
pfet_b P13 ( .b(cds_globals.vdd_), .g(y), .s(net041), .d(net051));
pfet_b P5 ( .b(cds_globals.vdd_), .g(d), .s(net032), .d(net041));
pfet_b P12 ( .b(cds_globals.vdd_), .g(c), .s(net49), .d(net032));
pfet_b P4 ( .b(cds_globals.vdd_), .g(y), .s(net47), .d(net051));
pfet_b P3 ( .b(cds_globals.vdd_), .g(d), .s(net47), .d(net051));
pfet_b P2 ( .b(cds_globals.vdd_), .g(c), .s(net34), .d(net47));
pfet_b P1 ( .b(cds_globals.vdd_), .g(b), .s(net49), .d(net34));
pfet_b P0 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net49));
inv I2 ( y, net051);
endmodule
|
module display_16hex (reset, clock_27mhz, data,
disp_blank, disp_clock, disp_rs, disp_ce_b,
disp_reset_b, disp_data_out);
input reset, clock_27mhz; // clock and reset (active high reset)
input [63:0] data; // 16 hex nibbles to display
output disp_blank, disp_clock, disp_data_out, disp_rs, disp_ce_b,
disp_reset_b;
reg disp_data_out, disp_rs, disp_ce_b, disp_reset_b;
////////////////////////////////////////////////////////////////////////////
//
// Display Clock
//
// Generate a 500kHz clock for driving the displays.
//
////////////////////////////////////////////////////////////////////////////
reg [4:0] count;
reg [7:0] reset_count;
reg clock;
wire dreset;
always @(posedge clock_27mhz)
begin
if (reset)
begin
count = 0;
clock = 0;
end
else if (count == 26)
begin
clock = ~clock;
count = 5'h00;
end
else
count = count+1;
end
always @(posedge clock_27mhz)
if (reset)
reset_count <= 100;
else
reset_count <= (reset_count==0) ? 0 : reset_count-1;
assign dreset = (reset_count != 0);
assign disp_clock = ~clock;
////////////////////////////////////////////////////////////////////////////
//
// Display State Machine
//
////////////////////////////////////////////////////////////////////////////
reg [7:0] state; // FSM state
reg [9:0] dot_index; // index to current dot being clocked out
reg [31:0] control; // control register
reg [3:0] char_index; // index of current character
reg [39:0] dots; // dots for a single digit
reg [3:0] nibble; // hex nibble of current character
assign disp_blank = 1'b0; // low <= not blanked
always @(posedge clock)
if (dreset)
begin
state <= 0;
dot_index <= 0;
control <= 32'h7F7F7F7F;
end
else
casex (state)
8'h00:
begin
// Reset displays
disp_data_out <= 1'b0;
disp_rs <= 1'b0; // dot register
disp_ce_b <= 1'b1;
disp_reset_b <= 1'b0;
dot_index <= 0;
state <= state+1;
end
8'h01:
begin
// End reset
disp_reset_b <= 1'b1;
state <= state+1;
end
8'h02:
begin
// Initialize dot register (set all dots to zero)
disp_ce_b <= 1'b0;
disp_data_out <= 1'b0; // dot_index[0];
if (dot_index == 639)
state <= state+1;
else
dot_index <= dot_index+1;
end
8'h03:
begin
// Latch dot data
disp_ce_b <= 1'b1;
dot_index <= 31; // re-purpose to init ctrl reg
disp_rs <= 1'b1; // Select the control register
state <= state+1;
end
8'h04:
begin
// Setup the control register
disp_ce_b <= 1'b0;
disp_data_out <= control[31];
control <= {control[30:0], 1'b0}; // shift left
if (dot_index == 0)
state <= state+1;
else
dot_index <= dot_index-1;
end
8'h05:
begin
// Latch the control register data / dot data
disp_ce_b <= 1'b1;
dot_index <= 39; // init for single char
char_index <= 15; // start with MS char
state <= state+1;
disp_rs <= 1'b0; // Select the dot register
end
8'h06:
begin
// Load the user's dot data into the dot reg, char by char
disp_ce_b <= 1'b0;
disp_data_out <= dots[dot_index]; // dot data from msb
if (dot_index == 0)
if (char_index == 0)
state <= 5; // all done, latch data
else
begin
char_index <= char_index - 1; // goto next char
dot_index <= 39;
end
else
dot_index <= dot_index-1; // else loop thru all dots
end
endcase
always @ (data or char_index)
case (char_index)
4'h0: nibble <= data[3:0];
4'h1: nibble <= data[7:4];
4'h2: nibble <= data[11:8];
4'h3: nibble <= data[15:12];
4'h4: nibble <= data[19:16];
4'h5: nibble <= data[23:20];
4'h6: nibble <= data[27:24];
4'h7: nibble <= data[31:28];
4'h8: nibble <= data[35:32];
4'h9: nibble <= data[39:36];
4'hA: nibble <= data[43:40];
4'hB: nibble <= data[47:44];
4'hC: nibble <= data[51:48];
4'hD: nibble <= data[55:52];
4'hE: nibble <= data[59:56];
4'hF: nibble <= data[63:60];
endcase
always @(nibble)
case (nibble)
4'h0: dots <= 40'b00111110_01010001_01001001_01000101_00111110;
4'h1: dots <= 40'b00000000_01000010_01111111_01000000_00000000;
4'h2: dots <= 40'b01100010_01010001_01001001_01001001_01000110;
4'h3: dots <= 40'b00100010_01000001_01001001_01001001_00110110;
4'h4: dots <= 40'b00011000_00010100_00010010_01111111_00010000;
4'h5: dots <= 40'b00100111_01000101_01000101_01000101_00111001;
4'h6: dots <= 40'b00111100_01001010_01001001_01001001_00110000;
4'h7: dots <= 40'b00000001_01110001_00001001_00000101_00000011;
4'h8: dots <= 40'b00110110_01001001_01001001_01001001_00110110;
4'h9: dots <= 40'b00000110_01001001_01001001_00101001_00011110;
4'hA: dots <= 40'b01111110_00001001_00001001_00001001_01111110;
4'hB: dots <= 40'b01111111_01001001_01001001_01001001_00110110;
4'hC: dots <= 40'b00111110_01000001_01000001_01000001_00100010;
4'hD: dots <= 40'b01111111_01000001_01000001_01000001_00111110;
4'hE: dots <= 40'b01111111_01001001_01001001_01001001_01000001;
4'hF: dots <= 40'b01111111_00001001_00001001_00001001_00000001;
endcase
endmodule
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module fifo_37x512 (
clk, rd_en, empty, wr_en, full, srst, dout, din
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
input rd_en;
output empty;
input wr_en;
output full;
input srst;
output [36 : 0] dout;
input [36 : 0] din;
// synthesis translate_off
wire N0;
wire N1;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_22 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i_24 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt_27 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt_29 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt_31 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt_33 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt_35 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt_37 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt_39 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8>_rt_41 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_89 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_90 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt_94 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt_96 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt_98 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt_100 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt_102 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt_104 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt_106 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8>_rt_108 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_SBITERR_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DBITERR_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<63>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<62>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<61>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<60>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<55>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<54>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<53>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<47>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<46>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<45>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<44>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<39>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<38>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<37>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<31>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<30>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<29>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<28>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<23>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<22>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<21>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<15>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<14>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<13>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<7>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<6>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<7>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<6>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<7>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<6>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<0>_UNCONNECTED ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 ;
wire [7 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy ;
wire [0 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 ;
wire [7 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy ;
wire [0 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 ;
assign
empty = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i_24 ,
full = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_90 ;
GND XST_GND (
.G(N0)
);
VCC XST_VCC (
.P(N1)
);
FD #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i_24 )
);
FD #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_22 )
);
FD #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_89 )
);
FD #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_90 )
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [7]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8>_rt_41 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [8])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<7> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [6]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt_39 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [7])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [6]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt_39 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [7])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<6> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [5]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt_37 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [6])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [5]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt_37 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [6])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<5> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [4]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt_35 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [5])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [4]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt_35 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [5])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<4> (
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);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4> (
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);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<3> (
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);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3> (
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);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<2> (
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);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2> (
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);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<1> (
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);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1> (
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);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<0> (
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);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<0> (
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);
FDRE #(
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\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_8 (
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);
FDRE #(
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);
FDRE #(
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.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
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.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [5])
);
FDRE #(
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\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_4 (
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.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
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);
FDRE #(
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\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_6 (
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FDRE #(
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.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3])
);
FDRE #(
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\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_2 (
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);
FDSE #(
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\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_0 (
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);
FDRE #(
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\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_1 (
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.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1])
);
FDRE #(
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.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [8]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8])
);
FDRE #(
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\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_7 (
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.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7])
);
FDRE #(
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\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_6 (
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.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
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.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6])
);
FDRE #(
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\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_5 (
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.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5])
);
FDRE #(
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\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_4 (
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.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4])
);
FDRE #(
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\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
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.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3])
);
FDRE #(
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\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_2 (
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.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
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.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2])
);
FDRE #(
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.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1])
);
FDRE #(
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);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8> (
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XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<7> (
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MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7> (
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XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<6> (
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MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6> (
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);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<5> (
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MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5> (
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);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<4> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [3]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt_100 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [4])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt_100 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [4])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<3> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [2]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt_98 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt_98 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [3])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<2> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [1]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt_96 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt_96 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [2])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<1> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [0]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt_94 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt_94 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [1])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<0> (
.CI(N0),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<0> (
.CI(N0),
.DI(N1),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_8 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [8]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [8])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_7 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_5 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_4 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_6 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [6]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [3]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [2]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2])
);
FDSE #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [0]),
.S(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [1]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_8 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [8]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_7 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_6 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [6]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_5 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_4 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[4].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 )
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[3].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[2].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[1].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[0].gm1.m1 (
.CI(N1),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[4].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 )
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[3].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[2].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[1].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[0].gm1.m1 (
.CI(N1),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[4].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 )
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[3].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[2].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[1].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[0].gm1.m1 (
.CI(N1),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[4].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 )
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[3].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[2].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[1].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[0].gm1.m1 (
.CI(N1),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [0])
);
LUT3 #(
.INIT ( 8'hF4 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en1 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_22 ),
.I1(rd_en),
.I2(srst),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en )
);
LUT2 #(
.INIT ( 4'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 (
.I0(wr_en),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_89 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en )
);
LUT2 #(
.INIT ( 4'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/ram_rd_en_i1 (
.I0(rd_en),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_22 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en )
);
LUT2 #(
.INIT ( 4'h9 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_4_not00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [8]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [4])
);
LUT2 #(
.INIT ( 4'h9 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_4_not00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [4])
);
LUT2 #(
.INIT ( 4'h9 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_4_not00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [4])
);
LUT2 #(
.INIT ( 4'h9 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_4_not00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [4])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_3_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [7]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [3])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_3_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [3])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_3_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [7]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [6]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [3])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_3_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [3])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_2_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [5]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [2])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_2_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [2])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_2_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [5]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [4]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [2])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_2_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [2])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_1_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [1])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_1_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [1])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_1_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [1])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_1_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [1])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_0_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [0])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_0_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [0])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_0_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [0])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_0_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [0])
);
LUT6 #(
.INIT ( 64'h1110101051505050 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux00001 (
.I0(srst),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_89 ),
.I3(wr_en),
.I4(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 ),
.I5(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 )
);
LUT6 #(
.INIT ( 64'hAAFEAAFAFAFEFAFA ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux00001 (
.I0(srst),
.I1(rd_en),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_22 ),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.I4(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ),
.I5(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [7]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt_39 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt_37 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [5]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt_35 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt_33 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt_31 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt_29 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt_27 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [7]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt_106 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt_104 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [5]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt_102 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt_100 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt_98 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt_96 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt_94 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8>_rt_41 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8>_rt_108 )
);
INV \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut<0>_INV_0 (
.I(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut [0])
);
INV \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut<0>_INV_0 (
.I(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut [0])
);
RAMB36SDP_EXP #(
.DO_REG ( 0 ),
.EN_ECC_READ ( "FALSE" ),
.EN_ECC_SCRUB ( "FALSE" ),
.EN_ECC_WRITE ( "FALSE" ),
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.INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
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.INIT_FILE ( "NONE" ),
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\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP (
.RDENU(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ),
.RDENL(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ),
.WRENU(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.WRENL(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.SSRU(srst),
.SSRL(srst),
.RDCLKU(clk),
.RDCLKL(clk),
.WRCLKU(clk),
.WRCLKL(clk),
.RDRCLKU(clk),
.RDRCLKL(clk),
.REGCEU(N0),
.REGCEL(N0),
.SBITERR
(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_SBITERR_UNCONNECTED )
,
.DBITERR
(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DBITERR_UNCONNECTED )
,
.DI({N0, N0, N0, N0, din[36], din[35], din[34], din[33], N0, N0, N0, din[32], din[31], din[30], din[29], din[28], N0, N0, N0, N0, din[27], din[26]
, din[25], din[24], N0, N0, N0, din[23], din[22], din[21], din[20], din[19], N0, N0, N0, N0, din[18], din[17], din[16], din[15], N0, N0, N0, din[14],
din[13], din[12], din[11], din[10], N0, N0, N0, din[9], din[8], din[7], din[6], din[5], N0, N0, N0, din[4], din[3], din[2], din[1], din[0]}),
.DIP({N0, N0, N0, N0, N0, N0, N0, N0}),
.RDADDRL({N1, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<0>_UNCONNECTED
}),
.RDADDRU({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<0>_UNCONNECTED
}),
.WRADDRL({N1, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<0>_UNCONNECTED
}),
.WRADDRU({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<0>_UNCONNECTED
}),
.WEU({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en }),
.WEL({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en }),
.DO({
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<63>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<62>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<61>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<60>_UNCONNECTED
, dout[36], dout[35], dout[34], dout[33],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<55>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<54>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<53>_UNCONNECTED
, dout[32], dout[31], dout[30], dout[29], dout[28],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<47>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<46>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<45>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<44>_UNCONNECTED
, dout[27], dout[26], dout[25], dout[24],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<39>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<38>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<37>_UNCONNECTED
, dout[23], dout[22], dout[21], dout[20], dout[19],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<31>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<30>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<29>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<28>_UNCONNECTED
, dout[18], dout[17], dout[16], dout[15],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<23>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<22>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<21>_UNCONNECTED
, dout[14], dout[13], dout[12], dout[11], dout[10],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<15>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<14>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<13>_UNCONNECTED
, dout[9], dout[8], dout[7], dout[6], dout[5],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<7>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<6>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<5>_UNCONNECTED
, dout[4], dout[3], dout[2], dout[1], dout[0]}),
.DOP({
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<7>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<6>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<0>_UNCONNECTED
}),
.ECCPARITY({
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<7>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<6>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<0>_UNCONNECTED
})
);
// synthesis translate_on
endmodule
|
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
|
module VC709_Gen2x8If128_CLK
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 12,
// Number of PCIe Lanes
parameter C_NUM_LANES = 8,
// Settings from Vivado IP Generator
parameter C_PCI_DATA_WIDTH = 128,
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 6
)
(output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXP,
input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXN,
output [7:0] LED,
input PCIE_REFCLK_P,
input PCIE_REFCLK_N,
input PCIE_RESET_N
);
// Clocks, etc
wire user_lnk_up;
wire user_clk;
wire user_reset;
wire pcie_refclk;
wire pcie_reset_n;
wire riffa_5_clk;
wire riffa_10_clk;
wire riffa_25_clk;
wire riffa_50_clk;
wire riffa_75_clk;
wire riffa_100_clk;
wire riffa_125_clk;
wire riffa_150_clk;
wire riffa_175_clk;
wire riffa_200_clk;
wire riffa_225_clk;
wire riffa_250_clk;
// Interface: RQ (TXC)
wire s_axis_rq_tlast;
wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata;
wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep;
wire s_axis_rq_tready;
wire s_axis_rq_tvalid;
// Interface: RC (RXC)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata;
wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser;
wire m_axis_rc_tlast;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep;
wire m_axis_rc_tvalid;
wire m_axis_rc_tready;
// Interface: CQ (RXR)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata;
wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser;
wire m_axis_cq_tlast;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep;
wire m_axis_cq_tvalid;
wire m_axis_cq_tready;
// Interface: CC (TXC)
wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata;
wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser;
wire s_axis_cc_tlast;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep;
wire s_axis_cc_tvalid;
wire s_axis_cc_tready;
// Configuration (CFG) Interface
wire [3:0] pcie_rq_seq_num;
wire pcie_rq_seq_num_vld;
wire [5:0] pcie_rq_tag;
wire pcie_rq_tag_vld;
wire pcie_cq_np_req;
wire [5:0] pcie_cq_np_req_count;
wire cfg_phy_link_down;
wire [3:0] cfg_negotiated_width; // CONFIG_LINK_WIDTH
wire [2:0] cfg_current_speed; // CONFIG_LINK_RATE
wire [2:0] cfg_max_payload; // CONFIG_MAX_PAYLOAD
wire [2:0] cfg_max_read_req; // CONFIG_MAX_READ_REQUEST
wire [7:0] cfg_function_status; // [2] = CONFIG_BUS_MASTER_ENABLE
wire [5:0] cfg_function_power_state; // Ignorable but not removable
wire [11:0] cfg_vf_status; // Ignorable but not removable
wire [17:0] cfg_vf_power_state; // Ignorable but not removable
wire [1:0] cfg_link_power_state; // Ignorable but not removable
// Error Reporting Interface
wire cfg_err_cor_out;
wire cfg_err_nonfatal_out;
wire cfg_err_fatal_out;
wire cfg_ltr_enable;
wire [5:0] cfg_ltssm_state;// TODO: Connect to LED's
wire [1:0] cfg_rcb_status;
wire [1:0] cfg_dpa_substate_change;
wire [1:0] cfg_obff_enable;
wire cfg_pl_status_change;
wire [1:0] cfg_tph_requester_enable;
wire [5:0] cfg_tph_st_mode;
wire [5:0] cfg_vf_tph_requester_enable;
wire [17:0] cfg_vf_tph_st_mode;
wire [7:0] cfg_fc_ph;
wire [11:0] cfg_fc_pd;
wire [7:0] cfg_fc_nph;
wire [11:0] cfg_fc_npd;
wire [7:0] cfg_fc_cplh;
wire [11:0] cfg_fc_cpld;
wire [2:0] cfg_fc_sel;
// Interrupt Interface Signals
wire [3:0] cfg_interrupt_int;
wire [1:0] cfg_interrupt_pending;
wire cfg_interrupt_sent;
wire [1:0] cfg_interrupt_msi_enable;
wire [5:0] cfg_interrupt_msi_vf_enable;
wire [5:0] cfg_interrupt_msi_mmenable;
wire cfg_interrupt_msi_mask_update;
wire [31:0] cfg_interrupt_msi_data;
wire [3:0] cfg_interrupt_msi_select;
wire [31:0] cfg_interrupt_msi_int;
wire [63:0] cfg_interrupt_msi_pending_status;
wire cfg_interrupt_msi_sent;
wire cfg_interrupt_msi_fail;
wire [2:0] cfg_interrupt_msi_attr;
wire cfg_interrupt_msi_tph_present;
wire [1:0] cfg_interrupt_msi_tph_type;
wire [8:0] cfg_interrupt_msi_tph_st_tag;
wire [2:0] cfg_interrupt_msi_function_number;
wire rst_out;
wire [C_NUM_CHNL-1:0] chnl_rx_clk;
wire [C_NUM_CHNL-1:0] chnl_rx;
wire [C_NUM_CHNL-1:0] chnl_rx_ack;
wire [C_NUM_CHNL-1:0] chnl_rx_last;
wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len;
wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
wire [C_NUM_CHNL-1:0] chnl_rx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_rx_data_ren;
wire [C_NUM_CHNL-1:0] chnl_tx_clk;
wire [C_NUM_CHNL-1:0] chnl_tx;
wire [C_NUM_CHNL-1:0] chnl_tx_ack;
wire [C_NUM_CHNL-1:0] chnl_tx_last;
wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len;
wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
wire [C_NUM_CHNL-1:0] chnl_tx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_tx_data_ren;
genvar chnl;
IBUF
#()
pci_reset_n_ibuf
(.O(pcie_reset_n),
.I(PCIE_RESET_N));
IBUFDS_GTE2
#()
refclk_ibuf
(.O(pcie_refclk),
.ODIV2(),
.I(PCIE_REFCLK_P),
.CEB(1'b0),
.IB(PCIE_REFCLK_N));
OBUF
#()
led_0_obuf
(.O(LED[0]),
.I(cfg_ltssm_state[0]));
OBUF
#()
led_1_obuf
(.O(LED[1]),
.I(cfg_ltssm_state[1]));
OBUF
#()
led_2_obuf
(.O(LED[2]),
.I(cfg_ltssm_state[2]));
OBUF
#()
led_3_obuf
(.O(LED[3]),
.I(cfg_ltssm_state[3]));
OBUF
#()
led_4_obuf
(.O(LED[4]),
.I(cfg_ltssm_state[4]));
OBUF
#()
led_5_obuf
(.O(LED[5]),
.I(cfg_ltssm_state[5]));
OBUF
#()
led_6_obuf
(.O(LED[6]),
.I(pcie_reset_n));
OBUF
#()
led_7_obuf
(.O(LED[7]),
.I(rst_out));
// Core Top Level Wrapper
PCIeGen2x8If128
#()
pcie3_7x_0_i
(//---------------------------------------------------------------------
// PCI Express (pci_exp) Interface
//---------------------------------------------------------------------
.pci_exp_txn ( PCI_EXP_TXN ),
.pci_exp_txp ( PCI_EXP_TXP ),
.pci_exp_rxn ( PCI_EXP_RXN ),
.pci_exp_rxp ( PCI_EXP_RXP ),
//---------------------------------------------------------------------
// AXI Interface
//---------------------------------------------------------------------
.user_clk ( user_clk ),
.user_reset ( user_reset ),
.user_lnk_up ( user_lnk_up ),
.user_app_rdy ( ),
.s_axis_rq_tlast ( s_axis_rq_tlast ),
.s_axis_rq_tdata ( s_axis_rq_tdata ),
.s_axis_rq_tuser ( s_axis_rq_tuser ),
.s_axis_rq_tkeep ( s_axis_rq_tkeep ),
.s_axis_rq_tready ( s_axis_rq_tready ),
.s_axis_rq_tvalid ( s_axis_rq_tvalid ),
.m_axis_rc_tdata ( m_axis_rc_tdata ),
.m_axis_rc_tuser ( m_axis_rc_tuser ),
.m_axis_rc_tlast ( m_axis_rc_tlast ),
.m_axis_rc_tkeep ( m_axis_rc_tkeep ),
.m_axis_rc_tvalid ( m_axis_rc_tvalid ),
.m_axis_rc_tready ( {22{m_axis_rc_tready}} ),
.m_axis_cq_tdata ( m_axis_cq_tdata ),
.m_axis_cq_tuser ( m_axis_cq_tuser ),
.m_axis_cq_tlast ( m_axis_cq_tlast ),
.m_axis_cq_tkeep ( m_axis_cq_tkeep ),
.m_axis_cq_tvalid ( m_axis_cq_tvalid ),
.m_axis_cq_tready ( {22{m_axis_cq_tready}} ),
.s_axis_cc_tdata ( s_axis_cc_tdata ),
.s_axis_cc_tuser ( s_axis_cc_tuser ),
.s_axis_cc_tlast ( s_axis_cc_tlast ),
.s_axis_cc_tkeep ( s_axis_cc_tkeep ),
.s_axis_cc_tvalid ( s_axis_cc_tvalid ),
.s_axis_cc_tready ( s_axis_cc_tready ),
//---------------------------------------------------------------------
// Configuration (CFG) Interface
//---------------------------------------------------------------------
.pcie_rq_seq_num ( pcie_rq_seq_num ),
.pcie_rq_seq_num_vld ( pcie_rq_seq_num_vld ),
.pcie_rq_tag ( pcie_rq_tag ),
.pcie_rq_tag_vld ( pcie_rq_tag_vld ),
.pcie_cq_np_req ( pcie_cq_np_req ),
.pcie_cq_np_req_count ( pcie_cq_np_req_count ),
.cfg_phy_link_down ( cfg_phy_link_down ),
.cfg_phy_link_status ( cfg_phy_link_status),
.cfg_negotiated_width ( cfg_negotiated_width ),
.cfg_current_speed ( cfg_current_speed ),
.cfg_max_payload ( cfg_max_payload ),
.cfg_max_read_req ( cfg_max_read_req ),
.cfg_function_status ( cfg_function_status ),
.cfg_function_power_state ( cfg_function_power_state ),
.cfg_vf_status ( cfg_vf_status ),
.cfg_vf_power_state ( cfg_vf_power_state ),
.cfg_link_power_state ( cfg_link_power_state ),
// Error Reporting Interface
.cfg_err_cor_out ( cfg_err_cor_out ),
.cfg_err_nonfatal_out ( cfg_err_nonfatal_out ),
.cfg_err_fatal_out ( cfg_err_fatal_out ),
.cfg_ltr_enable ( cfg_ltr_enable ),
.cfg_ltssm_state ( cfg_ltssm_state ),
.cfg_rcb_status ( cfg_rcb_status ),
.cfg_dpa_substate_change ( cfg_dpa_substate_change ),
.cfg_obff_enable ( cfg_obff_enable ),
.cfg_pl_status_change ( cfg_pl_status_change ),
.cfg_tph_requester_enable ( cfg_tph_requester_enable ),
.cfg_tph_st_mode ( cfg_tph_st_mode ),
.cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ),
.cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ),
.cfg_fc_ph ( cfg_fc_ph ),
.cfg_fc_pd ( cfg_fc_pd ),
.cfg_fc_nph ( cfg_fc_nph ),
.cfg_fc_npd ( cfg_fc_npd ),
.cfg_fc_cplh ( cfg_fc_cplh ),
.cfg_fc_cpld ( cfg_fc_cpld ),
.cfg_fc_sel ( cfg_fc_sel ),
//---------------------------------------------------------------------
// EP Only
//---------------------------------------------------------------------
// Interrupt Interface Signals
.cfg_interrupt_int ( cfg_interrupt_int ),
.cfg_interrupt_pending ( cfg_interrupt_pending ),
.cfg_interrupt_sent ( cfg_interrupt_sent ),
.cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable ),
.cfg_interrupt_msi_vf_enable ( cfg_interrupt_msi_vf_enable ),
.cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ),
.cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ),
.cfg_interrupt_msi_data ( cfg_interrupt_msi_data ),
.cfg_interrupt_msi_select ( cfg_interrupt_msi_select ),
.cfg_interrupt_msi_int ( cfg_interrupt_msi_int ),
.cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_pending_status ),
.cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ),
.cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ),
.cfg_interrupt_msi_attr ( cfg_interrupt_msi_attr ),
.cfg_interrupt_msi_tph_present ( cfg_interrupt_msi_tph_present ),
.cfg_interrupt_msi_tph_type ( cfg_interrupt_msi_tph_type ),
.cfg_interrupt_msi_tph_st_tag ( cfg_interrupt_msi_tph_st_tag ),
.cfg_interrupt_msi_function_number ( cfg_interrupt_msi_function_number ),
//---------------------------------------------------------------------
// System(SYS) Interface
//---------------------------------------------------------------------
.sys_clk (pcie_refclk),
.sys_reset (~pcie_reset_n));
riffa_wrapper_vc709
#(/*AUTOINSTPARAM*/
// Parameters
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_NUM_CHNL (C_NUM_CHNL),
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES))
riffa
(// Outputs
.M_AXIS_CQ_TREADY (m_axis_cq_tready),
.M_AXIS_RC_TREADY (m_axis_rc_tready),
.S_AXIS_CC_TVALID (s_axis_cc_tvalid),
.S_AXIS_CC_TLAST (s_axis_cc_tlast),
.S_AXIS_CC_TDATA (s_axis_cc_tdata[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (s_axis_cc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (s_axis_cc_tuser[`SIG_CC_TUSER_W-1:0]),
.S_AXIS_RQ_TVALID (s_axis_rq_tvalid),
.S_AXIS_RQ_TLAST (s_axis_rq_tlast),
.S_AXIS_RQ_TDATA (s_axis_rq_tdata[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_RQ_TKEEP (s_axis_rq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_RQ_TUSER (s_axis_rq_tuser[`SIG_RQ_TUSER_W-1:0]),
.USER_CLK (user_clk),
.USER_RESET (user_reset),
.CFG_INTERRUPT_INT (cfg_interrupt_int[3:0]),
.CFG_INTERRUPT_PENDING (cfg_interrupt_pending[1:0]),
.CFG_INTERRUPT_MSI_SELECT (cfg_interrupt_msi_select[3:0]),
.CFG_INTERRUPT_MSI_INT (cfg_interrupt_msi_int[31:0]),
.CFG_INTERRUPT_MSI_PENDING_STATUS(cfg_interrupt_msi_pending_status[63:0]),
.CFG_INTERRUPT_MSI_ATTR (cfg_interrupt_msi_attr[2:0]),
.CFG_INTERRUPT_MSI_TPH_PRESENT (cfg_interrupt_msi_tph_present),
.CFG_INTERRUPT_MSI_TPH_TYPE (cfg_interrupt_msi_tph_type[1:0]),
.CFG_INTERRUPT_MSI_TPH_ST_TAG (cfg_interrupt_msi_tph_st_tag[8:0]),
.CFG_INTERRUPT_MSI_FUNCTION_NUMBER(cfg_interrupt_msi_function_number[2:0]),
.CFG_FC_SEL (cfg_fc_sel[2:0]),
.PCIE_CQ_NP_REQ (pcie_cq_np_req),
.RST_OUT (rst_out),
.CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
// Inputs
.M_AXIS_CQ_TVALID (m_axis_cq_tvalid),
.M_AXIS_CQ_TLAST (m_axis_cq_tlast),
.M_AXIS_CQ_TDATA (m_axis_cq_tdata[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_CQ_TKEEP (m_axis_cq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_CQ_TUSER (m_axis_cq_tuser[`SIG_CQ_TUSER_W-1:0]),
.M_AXIS_RC_TVALID (m_axis_rc_tvalid),
.M_AXIS_RC_TLAST (m_axis_rc_tlast),
.M_AXIS_RC_TDATA (m_axis_rc_tdata[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RC_TKEEP (m_axis_rc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_RC_TUSER (m_axis_rc_tuser[`SIG_RC_TUSER_W-1:0]),
.S_AXIS_CC_TREADY (s_axis_cc_tready),
.S_AXIS_RQ_TREADY (s_axis_rq_tready),
.CFG_INTERRUPT_MSI_ENABLE (cfg_interrupt_msi_enable[1:0]),
.CFG_INTERRUPT_MSI_MASK_UPDATE (cfg_interrupt_msi_mask_update),
.CFG_INTERRUPT_MSI_DATA (cfg_interrupt_msi_data[31:0]),
.CFG_INTERRUPT_MSI_SENT (cfg_interrupt_msi_sent),
.CFG_INTERRUPT_MSI_FAIL (cfg_interrupt_msi_fail),
.CFG_FC_CPLH (cfg_fc_cplh[7:0]),
.CFG_FC_CPLD (cfg_fc_cpld[11:0]),
.CFG_NEGOTIATED_WIDTH (cfg_negotiated_width[3:0]),
.CFG_CURRENT_SPEED (cfg_current_speed[2:0]),
.CFG_MAX_PAYLOAD (cfg_max_payload[2:0]),
.CFG_MAX_READ_REQ (cfg_max_read_req[2:0]),
.CFG_FUNCTION_STATUS (cfg_function_status[7:0]),
.CFG_RCB_STATUS (cfg_rcb_status[1:0]),
.CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]),
.CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
clk_250MIn_1
clkgen
(.user_clk(user_clk),
.riffa_5_clk(riffa_5_clk),
.riffa_10_clk(riffa_10_clk),
.riffa_25_clk(riffa_25_clk),
.riffa_50_clk(riffa_50_clk),
.riffa_75_clk(riffa_75_clk),
.riffa_100_clk(riffa_100_clk));
clk_250MIn_2
clkgen_2
(.user_clk(user_clk),
.riffa_125_clk(riffa_125_clk),
.riffa_150_clk(riffa_150_clk),
.riffa_175_clk(riffa_175_clk),
.riffa_200_clk(riffa_200_clk),
.riffa_225_clk(riffa_225_clk),
.riffa_250_clk(riffa_250_clk));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_5mhz
(.CLK(riffa_5_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[0]),
.CHNL_RX(chnl_rx[0]),
.CHNL_RX_ACK(chnl_rx_ack[0]),
.CHNL_RX_LAST(chnl_rx_last[0]),
.CHNL_RX_LEN(chnl_rx_len[32*0 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*0 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*0 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[0]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[0]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[0]),
.CHNL_TX(chnl_tx[0]),
.CHNL_TX_ACK(chnl_tx_ack[0]),
.CHNL_TX_LAST(chnl_tx_last[0]),
.CHNL_TX_LEN(chnl_tx_len[32*0 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*0 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*0 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[0]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[0]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_10mhz
(.CLK(riffa_10_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[1]),
.CHNL_RX(chnl_rx[1]),
.CHNL_RX_ACK(chnl_rx_ack[1]),
.CHNL_RX_LAST(chnl_rx_last[1]),
.CHNL_RX_LEN(chnl_rx_len[32*1 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*1 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*1 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[1]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[1]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[1]),
.CHNL_TX(chnl_tx[1]),
.CHNL_TX_ACK(chnl_tx_ack[1]),
.CHNL_TX_LAST(chnl_tx_last[1]),
.CHNL_TX_LEN(chnl_tx_len[32*1 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*1 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*1 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[1]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[1]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_25mhz
(.CLK(riffa_25_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[2]),
.CHNL_RX(chnl_rx[2]),
.CHNL_RX_ACK(chnl_rx_ack[2]),
.CHNL_RX_LAST(chnl_rx_last[2]),
.CHNL_RX_LEN(chnl_rx_len[32*2 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*2 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*2 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[2]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[2]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[2]),
.CHNL_TX(chnl_tx[2]),
.CHNL_TX_ACK(chnl_tx_ack[2]),
.CHNL_TX_LAST(chnl_tx_last[2]),
.CHNL_TX_LEN(chnl_tx_len[32*2 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*2 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*2 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[2]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[2]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_50mhz
(.CLK(riffa_50_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[3]),
.CHNL_RX(chnl_rx[3]),
.CHNL_RX_ACK(chnl_rx_ack[3]),
.CHNL_RX_LAST(chnl_rx_last[3]),
.CHNL_RX_LEN(chnl_rx_len[32*3 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*3 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*3 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[3]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[3]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[3]),
.CHNL_TX(chnl_tx[3]),
.CHNL_TX_ACK(chnl_tx_ack[3]),
.CHNL_TX_LAST(chnl_tx_last[3]),
.CHNL_TX_LEN(chnl_tx_len[32*3 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*3 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*3 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[3]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[3]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_75mhz
(.CLK(riffa_75_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[4]),
.CHNL_RX(chnl_rx[4]),
.CHNL_RX_ACK(chnl_rx_ack[4]),
.CHNL_RX_LAST(chnl_rx_last[4]),
.CHNL_RX_LEN(chnl_rx_len[32*4 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*4 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*4 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[4]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[4]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[4]),
.CHNL_TX(chnl_tx[4]),
.CHNL_TX_ACK(chnl_tx_ack[4]),
.CHNL_TX_LAST(chnl_tx_last[4]),
.CHNL_TX_LEN(chnl_tx_len[32*4 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*4 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*4 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[4]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[4]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_100mhz
(.CLK(riffa_100_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[5]),
.CHNL_RX(chnl_rx[5]),
.CHNL_RX_ACK(chnl_rx_ack[5]),
.CHNL_RX_LAST(chnl_rx_last[5]),
.CHNL_RX_LEN(chnl_rx_len[32*5 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*5 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*5 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[5]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[5]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[5]),
.CHNL_TX(chnl_tx[5]),
.CHNL_TX_ACK(chnl_tx_ack[5]),
.CHNL_TX_LAST(chnl_tx_last[5]),
.CHNL_TX_LEN(chnl_tx_len[32*5 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*5 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*5 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[5]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[5]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_125mhz
(.CLK(riffa_125_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[6]),
.CHNL_RX(chnl_rx[6]),
.CHNL_RX_ACK(chnl_rx_ack[6]),
.CHNL_RX_LAST(chnl_rx_last[6]),
.CHNL_RX_LEN(chnl_rx_len[32*6 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*6 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*6 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[6]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[6]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[6]),
.CHNL_TX(chnl_tx[6]),
.CHNL_TX_ACK(chnl_tx_ack[6]),
.CHNL_TX_LAST(chnl_tx_last[6]),
.CHNL_TX_LEN(chnl_tx_len[32*6 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*6 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*6 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[6]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[6]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_150mhz
(.CLK(riffa_150_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[7]),
.CHNL_RX(chnl_rx[7]),
.CHNL_RX_ACK(chnl_rx_ack[7]),
.CHNL_RX_LAST(chnl_rx_last[7]),
.CHNL_RX_LEN(chnl_rx_len[32*7 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*7 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*7 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[7]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[7]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[7]),
.CHNL_TX(chnl_tx[7]),
.CHNL_TX_ACK(chnl_tx_ack[7]),
.CHNL_TX_LAST(chnl_tx_last[7]),
.CHNL_TX_LEN(chnl_tx_len[32*7 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*7 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*7 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[7]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[7]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_175mhz
(.CLK(riffa_175_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[8]),
.CHNL_RX(chnl_rx[8]),
.CHNL_RX_ACK(chnl_rx_ack[8]),
.CHNL_RX_LAST(chnl_rx_last[8]),
.CHNL_RX_LEN(chnl_rx_len[32*8 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*8 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*8 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[8]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[8]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[8]),
.CHNL_TX(chnl_tx[8]),
.CHNL_TX_ACK(chnl_tx_ack[8]),
.CHNL_TX_LAST(chnl_tx_last[8]),
.CHNL_TX_LEN(chnl_tx_len[32*8 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*8 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*8 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[8]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[8]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_200mhz
(.CLK(riffa_200_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[9]),
.CHNL_RX(chnl_rx[9]),
.CHNL_RX_ACK(chnl_rx_ack[9]),
.CHNL_RX_LAST(chnl_rx_last[9]),
.CHNL_RX_LEN(chnl_rx_len[32*9 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*9 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*9 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[9]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[9]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[9]),
.CHNL_TX(chnl_tx[9]),
.CHNL_TX_ACK(chnl_tx_ack[9]),
.CHNL_TX_LAST(chnl_tx_last[9]),
.CHNL_TX_LEN(chnl_tx_len[32*9 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*9 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*9 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[9]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[9]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_225mhz
(.CLK(riffa_225_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[10]),
.CHNL_RX(chnl_rx[10]),
.CHNL_RX_ACK(chnl_rx_ack[10]),
.CHNL_RX_LAST(chnl_rx_last[10]),
.CHNL_RX_LEN(chnl_rx_len[32*10 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*10 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*10 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[10]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[10]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[10]),
.CHNL_TX(chnl_tx[10]),
.CHNL_TX_ACK(chnl_tx_ack[10]),
.CHNL_TX_LAST(chnl_tx_last[10]),
.CHNL_TX_LEN(chnl_tx_len[32*10 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*10 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*10 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[10]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[10]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_250mhz
(.CLK(riffa_250_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[11]),
.CHNL_RX(chnl_rx[11]),
.CHNL_RX_ACK(chnl_rx_ack[11]),
.CHNL_RX_LAST(chnl_rx_last[11]),
.CHNL_RX_LEN(chnl_rx_len[32*11 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*11 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*11 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[11]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[11]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[11]),
.CHNL_TX(chnl_tx[11]),
.CHNL_TX_ACK(chnl_tx_ack[11]),
.CHNL_TX_LAST(chnl_tx_last[11]),
.CHNL_TX_LEN(chnl_tx_len[32*11 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*11 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*11 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[11]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[11]));
endmodule
|
module sky130_fd_sc_ms__nand3b_4 (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ms__nand3b_4 (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
|
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20,
n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34,
n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48,
n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62,
n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76,
n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90,
n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103,
n104, n105, n106, n107, n108, n109, n110, n111, n112, n113, n114,
n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, n125,
n126, n127, n128, n129, n130, n131, n132, n133, n134, n135, n136,
n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, n147,
n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, n158,
n159, n160, n161, n162, n163, n164, n165, n166, n167, n168, n169,
n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, n180,
n181, n182, n183, n184, n185, n186, n187, n188, n189, n190, n191,
n192, n193, n194, n195, n196, n197, n198, n199, n200, n201, n202,
n203, n204, n205, n206, n207, n208, n209, n210, n211, n212, n213,
n214, n215, n216, n217, n218, n219, n220, n221, n222, n223, n224,
n225, n226, n227, n228, n229, n230, n231, n232, n233, n234, n235,
n236, n237, n238, n239, n240, n241, n242, n243, n244, n245, n246,
n247, n248, n249, n250, n251, n252, n253, n254, n255, n256, n257,
n258, n259, n260, n261, n262, n263, n264, n265, n266, n267, n268,
n269, n270, n271, n272, n273, n274, n275, n276, n277, n278, n279,
n280, n281, n282, n283, n284, n285, n286, n287, n288, n289, n290,
n291, n292, n293, n294, n295, n296, n297, n298, n299, n300, n301,
n302, n303, n304, n305, n306, n307, n308, n309, n310, n311, n312,
n313, n314, n315, n316, n317, n318, n319, n320, n321, n322, n323,
n324, n325, n326, n327, n328, n329, n330, n331, n332, n333, n334,
n335, n336, n337, n338, n339, n340, n341, n342, n343, n344, n345,
n346, n347, n348, n349, n350, n351, n352, n353, n354, n355, n356,
n357, n358, n359, n360, n361, n362, n363, n364, n365, n366, n367,
n368, n369, n370;
XOR2X2TS U40 ( .A(n288), .B(n287), .Y(res[22]) );
NAND2X1TS U41 ( .A(n255), .B(n91), .Y(n256) );
NAND2X1TS U42 ( .A(n89), .B(n259), .Y(n260) );
NAND2X1TS U43 ( .A(n286), .B(n285), .Y(n287) );
NAND2X1TS U44 ( .A(n225), .B(n240), .Y(n221) );
NAND2X1TS U45 ( .A(n250), .B(n84), .Y(n251) );
NAND2X1TS U46 ( .A(n87), .B(n242), .Y(n243) );
NAND2XLTS U47 ( .A(n82), .B(n308), .Y(n310) );
NAND2X1TS U48 ( .A(n279), .B(n278), .Y(n280) );
NAND2X1TS U49 ( .A(n272), .B(n271), .Y(n273) );
NAND2XLTS U50 ( .A(n83), .B(n330), .Y(n331) );
NAND2XLTS U51 ( .A(n263), .B(n262), .Y(n264) );
NAND2XLTS U52 ( .A(n290), .B(n289), .Y(n291) );
NAND2XLTS U53 ( .A(n311), .B(n8), .Y(n309) );
NAND2X1TS U54 ( .A(n301), .B(n300), .Y(n302) );
OA21X2TS U55 ( .A0(n239), .A1(n238), .B0(n237), .Y(n93) );
NAND2XLTS U56 ( .A(n296), .B(n295), .Y(n297) );
NOR2X1TS U57 ( .A(n62), .B(n59), .Y(n317) );
NAND3X6TS U58 ( .A(n73), .B(n78), .C(n65), .Y(n235) );
NAND2X1TS U59 ( .A(n232), .B(in1[31]), .Y(n237) );
NAND2X6TS U60 ( .A(n292), .B(n66), .Y(n65) );
NOR2XLTS U61 ( .A(n61), .B(n60), .Y(n59) );
INVX3TS U62 ( .A(n74), .Y(n67) );
CLKMX2X2TS U63 ( .A(in2[31]), .B(n231), .S0(add_sub), .Y(n232) );
NAND2X1TS U64 ( .A(n220), .B(in1[29]), .Y(n240) );
NOR2X1TS U65 ( .A(n229), .B(in2[30]), .Y(n230) );
NAND2X2TS U66 ( .A(n188), .B(in1[22]), .Y(n285) );
NAND2X2TS U67 ( .A(n189), .B(in1[23]), .Y(n278) );
NAND2X1TS U68 ( .A(n169), .B(in1[20]), .Y(n295) );
OR2X4TS U69 ( .A(n211), .B(in1[27]), .Y(n91) );
OR2X4TS U70 ( .A(n226), .B(in1[30]), .Y(n87) );
NAND2X2TS U71 ( .A(n168), .B(in1[19]), .Y(n300) );
NOR2X4TS U72 ( .A(n189), .B(in1[23]), .Y(n277) );
NOR2X2TS U73 ( .A(n169), .B(in1[20]), .Y(n294) );
CLKMX2X3TS U74 ( .A(in2[25]), .B(n195), .S0(n223), .Y(n207) );
CLKMX2X4TS U75 ( .A(in2[29]), .B(n219), .S0(n223), .Y(n220) );
MXI2X2TS U76 ( .A(n167), .B(n166), .S0(add_sub), .Y(n169) );
NOR2X2TS U77 ( .A(n218), .B(n204), .Y(n202) );
NOR2X2TS U78 ( .A(n218), .B(n217), .Y(n205) );
XNOR2X1TS U79 ( .A(n222), .B(in2[29]), .Y(n219) );
XNOR2X1TS U80 ( .A(n183), .B(in2[20]), .Y(n166) );
XNOR2X1TS U81 ( .A(n184), .B(n186), .Y(n185) );
XOR2X1TS U82 ( .A(n196), .B(in2[24]), .Y(n177) );
INVX2TS U83 ( .A(in2[21]), .Y(n186) );
NOR2X2TS U84 ( .A(n183), .B(in2[20]), .Y(n184) );
NOR2X2TS U85 ( .A(n161), .B(in2[18]), .Y(n162) );
CLKINVX3TS U86 ( .A(n218), .Y(n196) );
NOR3X2TS U87 ( .A(n183), .B(in2[22]), .C(n179), .Y(n172) );
OR2X2TS U88 ( .A(n204), .B(in2[27]), .Y(n217) );
NAND2X2TS U89 ( .A(n176), .B(n165), .Y(n161) );
AOI21X2TS U90 ( .A0(n329), .A1(n83), .B0(n139), .Y(n34) );
NOR2X1TS U91 ( .A(in2[25]), .B(in2[24]), .Y(n201) );
CLKXOR2X2TS U92 ( .A(n176), .B(in2[16]), .Y(n154) );
OR2X2TS U93 ( .A(in2[21]), .B(in2[20]), .Y(n179) );
OR2X4TS U94 ( .A(n138), .B(in1[12]), .Y(n83) );
NOR2X1TS U95 ( .A(in2[19]), .B(in2[18]), .Y(n164) );
NOR2X2TS U96 ( .A(in2[17]), .B(in2[16]), .Y(n165) );
NOR2X4TS U97 ( .A(n131), .B(in1[10]), .Y(n36) );
XOR2X1TS U98 ( .A(n151), .B(in2[15]), .Y(n152) );
OR2X4TS U99 ( .A(n122), .B(in1[8]), .Y(n86) );
CLKMX2X4TS U100 ( .A(in2[7]), .B(n118), .S0(n20), .Y(n119) );
AND2X2TS U101 ( .A(n96), .B(n148), .Y(n33) );
INVX2TS U102 ( .A(in2[14]), .Y(n148) );
OR2X4TS U103 ( .A(n129), .B(n128), .Y(n134) );
INVX2TS U104 ( .A(n198), .Y(n19) );
CLKINVX6TS U105 ( .A(n198), .Y(n20) );
XOR2X2TS U106 ( .A(n124), .B(in2[9]), .Y(n125) );
AOI21X2TS U107 ( .A0(n110), .A1(n115), .B0(n369), .Y(n111) );
INVX6TS U108 ( .A(n9), .Y(n108) );
CLKINVX2TS U109 ( .A(n128), .Y(n29) );
INVX8TS U110 ( .A(n223), .Y(n198) );
NOR2X1TS U111 ( .A(in2[11]), .B(in2[10]), .Y(n28) );
INVX12TS U112 ( .A(n369), .Y(n223) );
INVX4TS U113 ( .A(n109), .Y(n30) );
INVX2TS U114 ( .A(in2[5]), .Y(n10) );
INVX4TS U115 ( .A(in2[8]), .Y(n121) );
NOR2X2TS U116 ( .A(in2[7]), .B(in2[6]), .Y(n31) );
OAI2BB1X2TS U117 ( .A0N(in2[2]), .A1N(add_sub), .B0(in2[3]), .Y(n102) );
CLKINVX3TS U118 ( .A(in2[3]), .Y(n114) );
NOR2X1TS U119 ( .A(n19), .B(in2[12]), .Y(n39) );
NOR2XLTS U120 ( .A(n20), .B(in2[18]), .Y(n51) );
XOR2X1TS U121 ( .A(n180), .B(in2[22]), .Y(n181) );
XNOR2X1TS U122 ( .A(n205), .B(in2[28]), .Y(n206) );
INVX4TS U123 ( .A(in2[2]), .Y(n366) );
NAND2X2TS U124 ( .A(n138), .B(in1[12]), .Y(n330) );
NAND2X1TS U125 ( .A(n226), .B(in1[30]), .Y(n242) );
INVX12TS U126 ( .A(add_sub), .Y(n369) );
NAND2X1TS U127 ( .A(n43), .B(n305), .Y(n306) );
AND2X4TS U128 ( .A(n30), .B(n31), .Y(n6) );
NAND2X2TS U129 ( .A(n108), .B(in1[5]), .Y(n355) );
NAND2X2TS U130 ( .A(n70), .B(n69), .Y(n68) );
INVX3TS U131 ( .A(n236), .Y(n75) );
INVX2TS U132 ( .A(n239), .Y(n233) );
NOR2X4TS U133 ( .A(n13), .B(n314), .Y(n58) );
NAND2X1TS U134 ( .A(n7), .B(n315), .Y(n316) );
NAND2X2TS U135 ( .A(n85), .B(n83), .Y(n35) );
INVX2TS U136 ( .A(n330), .Y(n139) );
INVX4TS U137 ( .A(n342), .Y(n123) );
NOR2X4TS U138 ( .A(n53), .B(n228), .Y(n52) );
NAND3X4TS U139 ( .A(n71), .B(n68), .C(n67), .Y(n73) );
NOR2X4TS U140 ( .A(n193), .B(n74), .Y(n66) );
NAND2X4TS U141 ( .A(n216), .B(n75), .Y(n74) );
NAND2X2TS U142 ( .A(n233), .B(n237), .Y(n234) );
NOR2X4TS U143 ( .A(n25), .B(n304), .Y(n24) );
INVX4TS U144 ( .A(n44), .Y(n25) );
NAND2X4TS U145 ( .A(n47), .B(n45), .Y(n44) );
INVX2TS U146 ( .A(n250), .Y(n213) );
INVX2TS U147 ( .A(n262), .Y(n210) );
INVX4TS U148 ( .A(n158), .Y(n45) );
MX2X2TS U149 ( .A(in2[19]), .B(n163), .S0(n20), .Y(n168) );
INVX4TS U150 ( .A(n308), .Y(n158) );
NOR2X4TS U151 ( .A(n58), .B(n63), .Y(n57) );
NAND2X2TS U152 ( .A(n196), .B(n201), .Y(n197) );
NAND2X1TS U153 ( .A(n321), .B(n320), .Y(n322) );
NOR2X6TS U154 ( .A(n324), .B(n319), .Y(n147) );
INVX2TS U155 ( .A(n315), .Y(n63) );
OR2X4TS U156 ( .A(n137), .B(in1[11]), .Y(n85) );
NAND2X4TS U157 ( .A(n131), .B(in1[10]), .Y(n336) );
NAND2X4TS U158 ( .A(n145), .B(in1[13]), .Y(n325) );
NAND2X4TS U159 ( .A(n122), .B(in1[8]), .Y(n342) );
XOR2X2TS U160 ( .A(n141), .B(in2[13]), .Y(n142) );
NOR2X4TS U161 ( .A(n134), .B(in2[10]), .Y(n135) );
NAND2X6TS U162 ( .A(n150), .B(n149), .Y(n143) );
NAND2X4TS U163 ( .A(n29), .B(n28), .Y(n27) );
NAND3X4TS U164 ( .A(n101), .B(n223), .C(in2[3]), .Y(n104) );
NOR2X4TS U165 ( .A(in2[13]), .B(in2[12]), .Y(n149) );
XOR2X1TS U166 ( .A(n307), .B(n306), .Y(res[18]) );
XOR2X1TS U167 ( .A(n317), .B(n316), .Y(res[15]) );
NAND2BX2TS U168 ( .AN(n191), .B(n72), .Y(n71) );
NAND2X4TS U169 ( .A(n87), .B(n225), .Y(n236) );
AOI21X2TS U170 ( .A0(n84), .A1(n246), .B0(n213), .Y(n214) );
OA21X4TS U171 ( .A0(n300), .A1(n294), .B0(n295), .Y(n170) );
NOR2X6TS U172 ( .A(n284), .B(n282), .Y(n276) );
NAND2X4TS U173 ( .A(n91), .B(n84), .Y(n215) );
NOR2X6TS U174 ( .A(n277), .B(n270), .Y(n192) );
NOR2X2TS U175 ( .A(n299), .B(n294), .Y(n171) );
XOR2X1TS U176 ( .A(n332), .B(n331), .Y(res[12]) );
XOR2X1TS U177 ( .A(n327), .B(n61), .Y(res[13]) );
NAND2X2TS U178 ( .A(n190), .B(in1[24]), .Y(n271) );
OR2X4TS U179 ( .A(n212), .B(in1[28]), .Y(n84) );
NAND2X4TS U180 ( .A(n187), .B(in1[21]), .Y(n289) );
MX2X2TS U181 ( .A(in2[30]), .B(n224), .S0(n223), .Y(n226) );
MX2X4TS U182 ( .A(in2[27]), .B(n203), .S0(n223), .Y(n211) );
NAND2X2TS U183 ( .A(n160), .B(in1[18]), .Y(n305) );
MX2X2TS U184 ( .A(in2[28]), .B(n206), .S0(n223), .Y(n212) );
MX2X4TS U185 ( .A(in2[23]), .B(n173), .S0(add_sub), .Y(n189) );
OR2X4TS U186 ( .A(n157), .B(in1[17]), .Y(n82) );
XNOR2X2TS U187 ( .A(n172), .B(in2[23]), .Y(n173) );
XNOR2X2TS U188 ( .A(n162), .B(in2[19]), .Y(n163) );
NAND2X6TS U189 ( .A(n16), .B(n21), .Y(n338) );
NOR3X6TS U190 ( .A(n218), .B(in2[28]), .C(n217), .Y(n222) );
XOR2X1TS U191 ( .A(n341), .B(n340), .Y(res[9]) );
NAND2BX4TS U192 ( .AN(n174), .B(n176), .Y(n183) );
INVX4TS U193 ( .A(n36), .Y(n90) );
NAND2X2TS U194 ( .A(n15), .B(n123), .Y(n38) );
INVX4TS U195 ( .A(n314), .Y(n7) );
MX2X2TS U196 ( .A(in2[11]), .B(n136), .S0(n19), .Y(n137) );
OR2X6TS U197 ( .A(n127), .B(in1[9]), .Y(n15) );
XNOR2X2TS U198 ( .A(n135), .B(in2[11]), .Y(n136) );
OR2X2TS U199 ( .A(n19), .B(in2[10]), .Y(n12) );
OAI21XLTS U200 ( .A0(n370), .A1(n369), .B0(n368), .Y(res[3]) );
OAI21XLTS U201 ( .A0(n369), .A1(n363), .B0(n362), .Y(res[1]) );
OAI21XLTS U202 ( .A0(n365), .A1(n369), .B0(n364), .Y(res[2]) );
NAND4BX2TS U203 ( .AN(in2[5]), .B(n116), .C(n115), .D(n114), .Y(n117) );
NAND2X2TS U204 ( .A(n201), .B(n200), .Y(n204) );
NOR3X4TS U205 ( .A(n109), .B(in2[0]), .C(in2[3]), .Y(n110) );
OR2X1TS U206 ( .A(in2[0]), .B(in1[0]), .Y(res[0]) );
NAND2X1TS U207 ( .A(n313), .B(n18), .Y(n8) );
OR2X4TS U208 ( .A(n156), .B(in1[16]), .Y(n18) );
XNOR2X4TS U209 ( .A(n143), .B(in2[14]), .Y(n144) );
NAND3X6TS U210 ( .A(n88), .B(n359), .C(n361), .Y(n41) );
NAND2BX4TS U211 ( .AN(n198), .B(n105), .Y(n106) );
OR2X6TS U212 ( .A(n42), .B(n358), .Y(n40) );
OR2X6TS U213 ( .A(n107), .B(in1[4]), .Y(n359) );
AND4X6TS U214 ( .A(n104), .B(n105), .C(in1[3]), .D(n103), .Y(n107) );
CLKINVX12TS U215 ( .A(n143), .Y(n97) );
NOR2X4TS U216 ( .A(in2[16]), .B(n98), .Y(n99) );
NAND2X6TS U217 ( .A(n107), .B(in1[4]), .Y(n358) );
OAI21X4TS U218 ( .A0(n270), .A1(n278), .B0(n271), .Y(n191) );
NOR2X4TS U219 ( .A(n190), .B(in1[24]), .Y(n270) );
NOR2X8TS U220 ( .A(n108), .B(in1[5]), .Y(n42) );
XNOR2X2TS U221 ( .A(n197), .B(in2[26]), .Y(n199) );
XNOR2X4TS U222 ( .A(n11), .B(n10), .Y(n9) );
AO21X4TS U223 ( .A0(n56), .A1(n95), .B0(n369), .Y(n11) );
AOI21X4TS U224 ( .A0(n133), .A1(n223), .B0(n39), .Y(n138) );
MXI2X4TS U225 ( .A(n178), .B(n177), .S0(add_sub), .Y(n190) );
MXI2X4TS U226 ( .A(n200), .B(n199), .S0(n20), .Y(n208) );
CLKINVX12TS U227 ( .A(n98), .Y(n176) );
XOR2X2TS U228 ( .A(n274), .B(n273), .Y(res[24]) );
NOR2X6TS U229 ( .A(n153), .B(in1[15]), .Y(n314) );
MX2X4TS U230 ( .A(in2[15]), .B(n152), .S0(n19), .Y(n153) );
XOR2X2TS U231 ( .A(n281), .B(n280), .Y(res[23]) );
NOR2X4TS U232 ( .A(n146), .B(in1[14]), .Y(n319) );
NOR2X4TS U233 ( .A(n145), .B(in1[13]), .Y(n324) );
MX2X4TS U234 ( .A(in2[13]), .B(n142), .S0(n19), .Y(n145) );
INVX8TS U235 ( .A(n244), .Y(n265) );
XNOR2X4TS U236 ( .A(n261), .B(n260), .Y(res[26]) );
NOR3X4TS U237 ( .A(in2[0]), .B(in2[4]), .C(in2[6]), .Y(n116) );
NAND2X8TS U238 ( .A(n176), .B(n175), .Y(n218) );
XNOR2X4TS U239 ( .A(n257), .B(n256), .Y(res[27]) );
OR2X8TS U240 ( .A(in2[4]), .B(in2[5]), .Y(n109) );
XOR2X4TS U241 ( .A(n111), .B(in2[6]), .Y(n112) );
XNOR2X2TS U242 ( .A(n252), .B(n251), .Y(res[28]) );
OAI21X2TS U243 ( .A0(n94), .A1(n54), .B0(n93), .Y(res[32]) );
OA21X4TS U244 ( .A0(n319), .A1(n325), .B0(n320), .Y(n13) );
NAND2X2TS U245 ( .A(n146), .B(in1[14]), .Y(n320) );
NOR2X4TS U246 ( .A(n183), .B(n179), .Y(n180) );
MXI2X4TS U247 ( .A(n182), .B(n181), .S0(n20), .Y(n188) );
NOR2X4TS U248 ( .A(n188), .B(in1[22]), .Y(n284) );
INVX4TS U249 ( .A(n37), .Y(n131) );
MXI2X4TS U250 ( .A(n155), .B(n154), .S0(n20), .Y(n156) );
INVX2TS U251 ( .A(in2[16]), .Y(n155) );
NAND2X2TS U252 ( .A(n112), .B(in1[6]), .Y(n350) );
OR2X2TS U253 ( .A(n112), .B(in1[6]), .Y(n92) );
NAND2X2TS U254 ( .A(n156), .B(in1[16]), .Y(n311) );
OR2X4TS U255 ( .A(n208), .B(in1[26]), .Y(n89) );
NAND2X4TS U256 ( .A(n207), .B(in1[25]), .Y(n262) );
NAND2X2TS U257 ( .A(n208), .B(in1[26]), .Y(n259) );
NAND2X2TS U258 ( .A(n165), .B(n164), .Y(n174) );
NOR3X4TS U259 ( .A(in2[2]), .B(in2[4]), .C(in2[3]), .Y(n56) );
XOR2X1TS U260 ( .A(n117), .B(in2[7]), .Y(n118) );
MXI2X4TS U261 ( .A(n121), .B(n120), .S0(add_sub), .Y(n122) );
MXI2X4TS U262 ( .A(n126), .B(n125), .S0(add_sub), .Y(n127) );
NOR2X4TS U263 ( .A(n129), .B(in2[8]), .Y(n124) );
XOR2X1TS U264 ( .A(n150), .B(in2[12]), .Y(n133) );
AOI21X2TS U265 ( .A0(n159), .A1(n20), .B0(n51), .Y(n160) );
INVX2TS U266 ( .A(in2[22]), .Y(n182) );
NOR2X4TS U267 ( .A(n187), .B(in1[21]), .Y(n282) );
INVX2TS U268 ( .A(in2[24]), .Y(n178) );
INVX2TS U269 ( .A(n255), .Y(n246) );
INVX2TS U270 ( .A(n275), .Y(n72) );
NOR2X4TS U271 ( .A(n119), .B(in1[7]), .Y(n345) );
INVX2TS U272 ( .A(n350), .Y(n113) );
NAND2X2TS U273 ( .A(n119), .B(in1[7]), .Y(n346) );
NAND2X2TS U274 ( .A(n127), .B(in1[9]), .Y(n339) );
AND2X4TS U275 ( .A(n137), .B(in1[11]), .Y(n329) );
NOR2X2TS U276 ( .A(n158), .B(n49), .Y(n48) );
INVX2TS U277 ( .A(n311), .Y(n49) );
INVX2TS U278 ( .A(n82), .Y(n47) );
INVX2TS U279 ( .A(n282), .Y(n290) );
INVX2TS U280 ( .A(n289), .Y(n283) );
INVX8TS U281 ( .A(n266), .Y(n292) );
NOR2X1TS U282 ( .A(n267), .B(n277), .Y(n269) );
INVX2TS U283 ( .A(n276), .Y(n267) );
INVX2TS U284 ( .A(n258), .Y(n263) );
NOR2X2TS U285 ( .A(n207), .B(in1[25]), .Y(n258) );
NAND2X2TS U286 ( .A(n211), .B(in1[27]), .Y(n255) );
NAND2X4TS U287 ( .A(n263), .B(n89), .Y(n254) );
INVX2TS U288 ( .A(n259), .Y(n209) );
NAND2X2TS U289 ( .A(n212), .B(in1[28]), .Y(n250) );
INVX2TS U290 ( .A(n254), .Y(n245) );
INVX2TS U291 ( .A(n241), .Y(n225) );
NOR2X4TS U292 ( .A(n220), .B(in1[29]), .Y(n241) );
INVX4TS U293 ( .A(n95), .Y(n101) );
NOR2X4TS U294 ( .A(in2[1]), .B(in2[2]), .Y(n115) );
NAND2X2TS U295 ( .A(n15), .B(n86), .Y(n22) );
NAND2X1TS U296 ( .A(n150), .B(n140), .Y(n141) );
MXI2X2TS U297 ( .A(n148), .B(n144), .S0(n223), .Y(n146) );
NAND3X1TS U298 ( .A(n150), .B(n149), .C(n148), .Y(n151) );
AND2X2TS U299 ( .A(n147), .B(n7), .Y(n17) );
INVX2TS U300 ( .A(in2[20]), .Y(n167) );
MXI2X4TS U301 ( .A(n186), .B(n185), .S0(add_sub), .Y(n187) );
NOR2X4TS U302 ( .A(n254), .B(n215), .Y(n216) );
INVX2TS U303 ( .A(n191), .Y(n70) );
INVX2TS U304 ( .A(n192), .Y(n69) );
INVX2TS U305 ( .A(n147), .Y(n60) );
INVX2TS U306 ( .A(n318), .Y(n61) );
INVX2TS U307 ( .A(n13), .Y(n62) );
NAND2X2TS U308 ( .A(n153), .B(in1[15]), .Y(n315) );
NOR2X2TS U309 ( .A(n168), .B(in1[19]), .Y(n299) );
INVX2TS U310 ( .A(n293), .Y(n303) );
NOR2X4TS U311 ( .A(n14), .B(n241), .Y(n53) );
INVX2TS U312 ( .A(n242), .Y(n227) );
NOR2X4TS U313 ( .A(n232), .B(in1[31]), .Y(n239) );
AOI21X1TS U314 ( .A0(n369), .A1(in2[2]), .B0(in1[2]), .Y(n364) );
NAND2X1TS U315 ( .A(n359), .B(n358), .Y(n360) );
OAI21XLTS U316 ( .A0(n354), .A1(n353), .B0(n358), .Y(n357) );
NAND2X1TS U317 ( .A(n88), .B(n355), .Y(n356) );
INVX2TS U318 ( .A(n359), .Y(n353) );
NAND2X1TS U319 ( .A(n92), .B(n350), .Y(n351) );
NAND2X1TS U320 ( .A(n347), .B(n346), .Y(n348) );
INVX2TS U321 ( .A(n345), .Y(n347) );
NAND2X1TS U322 ( .A(n86), .B(n342), .Y(n344) );
NAND2X1TS U323 ( .A(n15), .B(n339), .Y(n341) );
NAND2X1TS U324 ( .A(n90), .B(n336), .Y(n337) );
NAND2X1TS U325 ( .A(n85), .B(n333), .Y(n335) );
INVX2TS U326 ( .A(n329), .Y(n333) );
NAND2X1TS U327 ( .A(n326), .B(n325), .Y(n327) );
INVX2TS U328 ( .A(n324), .Y(n326) );
NAND2X1TS U329 ( .A(n18), .B(n311), .Y(n312) );
XNOR2X1TS U330 ( .A(n310), .B(n309), .Y(res[17]) );
NAND2X1TS U331 ( .A(n46), .B(n44), .Y(n307) );
XOR2X1TS U332 ( .A(n303), .B(n302), .Y(res[19]) );
INVX2TS U333 ( .A(n299), .Y(n301) );
XNOR2X1TS U334 ( .A(n298), .B(n297), .Y(res[20]) );
OAI21X1TS U335 ( .A0(n303), .A1(n299), .B0(n300), .Y(n298) );
INVX2TS U336 ( .A(n294), .Y(n296) );
XNOR2X1TS U337 ( .A(n292), .B(n291), .Y(res[21]) );
INVX2TS U338 ( .A(n284), .Y(n286) );
INVX2TS U339 ( .A(n277), .Y(n279) );
INVX2TS U340 ( .A(n270), .Y(n272) );
XOR2X1TS U341 ( .A(n265), .B(n264), .Y(res[25]) );
NAND2X1TS U342 ( .A(n245), .B(n91), .Y(n249) );
OR2X2TS U343 ( .A(n239), .B(n236), .Y(n94) );
INVX3TS U344 ( .A(n77), .Y(n266) );
AND2X4TS U345 ( .A(n38), .B(n339), .Y(n16) );
NAND2X4TS U346 ( .A(n157), .B(in1[17]), .Y(n308) );
MX2X4TS U347 ( .A(in2[17]), .B(n100), .S0(n19), .Y(n157) );
XOR2X2TS U348 ( .A(n129), .B(n121), .Y(n120) );
AOI21X1TS U349 ( .A0(n334), .A1(n85), .B0(n329), .Y(n332) );
XNOR2X2TS U350 ( .A(n194), .B(in2[25]), .Y(n195) );
NOR2X4TS U351 ( .A(n218), .B(in2[24]), .Y(n194) );
INVX8TS U352 ( .A(n42), .Y(n88) );
NAND2X8TS U353 ( .A(n50), .B(n305), .Y(n293) );
AOI21X1TS U354 ( .A0(n343), .A1(n86), .B0(n123), .Y(n340) );
OA21X4TS U355 ( .A0(n253), .A1(n215), .B0(n214), .Y(n14) );
INVX2TS U356 ( .A(n240), .Y(n228) );
INVX2TS U357 ( .A(n361), .Y(n354) );
INVX2TS U358 ( .A(n193), .Y(n76) );
NAND2X4TS U359 ( .A(n192), .B(n276), .Y(n193) );
NOR2X2TS U360 ( .A(n160), .B(in1[18]), .Y(n304) );
INVX2TS U361 ( .A(n304), .Y(n43) );
INVX2TS U362 ( .A(in2[12]), .Y(n140) );
OAI21X1TS U363 ( .A0(n61), .A1(n324), .B0(n325), .Y(n323) );
OAI2BB1X2TS U364 ( .A0N(n130), .A1N(n19), .B0(n12), .Y(n37) );
NAND3X6TS U365 ( .A(n41), .B(n40), .C(n355), .Y(n352) );
NAND2X8TS U366 ( .A(n77), .B(n76), .Y(n80) );
NAND2X8TS U367 ( .A(n26), .B(n170), .Y(n77) );
NAND2BX4TS U368 ( .AN(n22), .B(n343), .Y(n21) );
NAND2X6TS U369 ( .A(n318), .B(n17), .Y(n23) );
CLKINVX12TS U370 ( .A(n105), .Y(n32) );
NAND2X8TS U371 ( .A(n23), .B(n57), .Y(n313) );
NOR4X2TS U372 ( .A(n174), .B(n179), .C(in2[23]), .D(in2[22]), .Y(n175) );
NAND2X8TS U373 ( .A(n46), .B(n24), .Y(n50) );
NAND2X8TS U374 ( .A(n64), .B(n48), .Y(n46) );
NAND2X8TS U375 ( .A(n293), .B(n171), .Y(n26) );
NAND2X8TS U376 ( .A(n32), .B(n6), .Y(n129) );
AND2X8TS U377 ( .A(n79), .B(n14), .Y(n54) );
NOR2X8TS U378 ( .A(n27), .B(n129), .Y(n150) );
NAND3X8TS U379 ( .A(n95), .B(n366), .C(n114), .Y(n105) );
NAND2X8TS U380 ( .A(n97), .B(n33), .Y(n98) );
NAND2X8TS U381 ( .A(n80), .B(n81), .Y(n244) );
OAI21X4TS U382 ( .A0(n328), .A1(n35), .B0(n34), .Y(n318) );
AOI21X4TS U383 ( .A0(n338), .A1(n90), .B0(n132), .Y(n328) );
OAI21X4TS U384 ( .A0(n79), .A1(n241), .B0(n52), .Y(n55) );
XNOR2X2TS U385 ( .A(n55), .B(n243), .Y(res[30]) );
NOR2X8TS U386 ( .A(in2[0]), .B(in2[1]), .Y(n95) );
NAND2X8TS U387 ( .A(n313), .B(n18), .Y(n64) );
AOI21X4TS U388 ( .A0(n192), .A1(n275), .B0(n191), .Y(n81) );
NAND2X8TS U389 ( .A(n244), .B(n216), .Y(n79) );
OA21X4TS U390 ( .A0(n14), .A1(n236), .B0(n238), .Y(n78) );
XNOR2X1TS U391 ( .A(n352), .B(n351), .Y(res[6]) );
XNOR2X1TS U392 ( .A(n337), .B(n338), .Y(res[10]) );
XOR2XLTS U393 ( .A(n349), .B(n348), .Y(res[7]) );
XNOR2X1TS U394 ( .A(n312), .B(n313), .Y(res[16]) );
XNOR2X1TS U395 ( .A(n344), .B(n343), .Y(res[8]) );
CLKINVX1TS U396 ( .A(n328), .Y(n334) );
NAND2X4TS U397 ( .A(n121), .B(n126), .Y(n128) );
OAI21X2TS U398 ( .A0(in2[3]), .A1(n369), .B0(n102), .Y(n103) );
INVX2TS U399 ( .A(n336), .Y(n132) );
OAI21X2TS U400 ( .A0(n72), .A1(n277), .B0(n278), .Y(n268) );
INVX2TS U401 ( .A(in2[9]), .Y(n126) );
INVX2TS U402 ( .A(in2[15]), .Y(n96) );
XNOR2X1TS U403 ( .A(n99), .B(in2[17]), .Y(n100) );
XNOR2X4TS U404 ( .A(n106), .B(in2[4]), .Y(n361) );
AOI21X4TS U405 ( .A0(n352), .A1(n92), .B0(n113), .Y(n349) );
OAI21X4TS U406 ( .A0(n349), .A1(n345), .B0(n346), .Y(n343) );
XNOR2X1TS U407 ( .A(n134), .B(in2[10]), .Y(n130) );
XNOR2X1TS U408 ( .A(n161), .B(in2[18]), .Y(n159) );
OAI21X4TS U409 ( .A0(n284), .A1(n289), .B0(n285), .Y(n275) );
INVX2TS U410 ( .A(in2[26]), .Y(n200) );
XNOR2X1TS U411 ( .A(n202), .B(in2[27]), .Y(n203) );
AOI21X4TS U412 ( .A0(n89), .A1(n210), .B0(n209), .Y(n253) );
XOR2X4TS U413 ( .A(n54), .B(n221), .Y(res[29]) );
NAND2BX4TS U414 ( .AN(in2[29]), .B(n222), .Y(n229) );
XOR2X1TS U415 ( .A(n229), .B(in2[30]), .Y(n224) );
AOI21X4TS U416 ( .A0(n87), .A1(n228), .B0(n227), .Y(n238) );
XNOR2X1TS U417 ( .A(n230), .B(in2[31]), .Y(n231) );
XNOR2X4TS U418 ( .A(n235), .B(n234), .Y(res[31]) );
INVX2TS U419 ( .A(n253), .Y(n247) );
AOI21X4TS U420 ( .A0(n247), .A1(n91), .B0(n246), .Y(n248) );
OAI21X4TS U421 ( .A0(n265), .A1(n249), .B0(n248), .Y(n252) );
OAI21X4TS U422 ( .A0(n265), .A1(n254), .B0(n253), .Y(n257) );
OAI21X4TS U423 ( .A0(n265), .A1(n258), .B0(n262), .Y(n261) );
AOI21X4TS U424 ( .A0(n292), .A1(n269), .B0(n268), .Y(n274) );
AOI21X4TS U425 ( .A0(n292), .A1(n276), .B0(n275), .Y(n281) );
AOI21X4TS U426 ( .A0(n292), .A1(n290), .B0(n283), .Y(n288) );
INVX2TS U427 ( .A(n319), .Y(n321) );
XNOR2X1TS U428 ( .A(n323), .B(n322), .Y(res[14]) );
XNOR2X1TS U429 ( .A(n335), .B(n334), .Y(res[11]) );
XNOR2X1TS U430 ( .A(n357), .B(n356), .Y(res[5]) );
XNOR2X1TS U431 ( .A(n361), .B(n360), .Y(res[4]) );
XNOR2X1TS U432 ( .A(in2[0]), .B(in2[1]), .Y(n363) );
AOI21X1TS U433 ( .A0(n369), .A1(in2[1]), .B0(in1[1]), .Y(n362) );
XNOR2X1TS U434 ( .A(n95), .B(n366), .Y(n365) );
NAND2X1TS U435 ( .A(n95), .B(n366), .Y(n367) );
XNOR2X1TS U436 ( .A(n367), .B(in2[3]), .Y(n370) );
AOI21X1TS U437 ( .A0(n369), .A1(in2[3]), .B0(in1[3]), .Y(n368) );
initial $sdf_annotate("Approx_adder_LOALPL4_syn.sdf");
endmodule
|
module bsg_source_sync_channel_control_master #(parameter `BSG_INV_PARAM( width_p )
, parameter lg_token_width_p = 6
, parameter lg_out_prepare_hold_cycles_p = 6
// bit vector
, parameter bypass_test_p = 5'b0
, parameter tests_lp = 5
, parameter verbose_lp = 1
)
(// output channel
input out_clk_i
, input out_reset_i // note this is just a synchronized version of core_reset
// we can do calibration in parallel, or channel-by-channel
, input [$clog2(tests_lp+1)-1:0] out_calibration_state_i
, input out_calib_prepare_i // essentially the reset signal
// ignore, we assume all channels are blessed
, input out_channel_blessed_i
// this is used to force data on to the output channel
// (calibration modes 0 and 1)
, output out_override_en_o
, output [width_p+1-1:0] out_override_valid_data_o
// ignore
, input out_override_is_posedge_i
// whether the test passed
, output [tests_lp+1-1:0] out_test_pass_r_o
// ignore
, input in_clk_i
, input in_reset_i
// ignore
, input [width_p+1-1:0] in_snoop_valid_data_neg_i
// ignore
, input [width_p+1-1:0] in_snoop_valid_data_pos_i
// hardwired to zero
, output out_infinite_credits_o
);
assign out_infinite_credits_o = 1'b0;
// memory mapped registers
logic [width_p+1-1:0] valid_data_r; // 0
logic override_r; // 1
logic [tests_lp+1-1:0] out_test_pass_r; // 2
logic [$clog2(tests_lp+1):0] match_reg_r; // 3
assign out_override_valid_data_o = valid_data_r;
assign out_override_en_o = override_r;
assign out_test_pass_r_o = out_test_pass_r;
//
// opcode4 <addr2>, <data14>
//
wire v_lo, v_li;
wire [15:0] data_lo, data_li;
wire yumi_li;
localparam match_size_lp = $clog2(tests_lp+1)+1;
// handle opcode4 -> send
// we convert this into a memory mapped write
always_ff @(posedge out_clk_i)
if (out_reset_i)
begin
valid_data_r <= 0;
override_r <= 0;
out_test_pass_r <= 0;
match_reg_r <= 0;
end
else
begin
if (v_lo)
begin
if (data_lo[15:14] == 0)
valid_data_r <= data_lo[0+:width_p+1];
else
if (data_lo[15:14] == 1)
override_r <= data_lo[0];
else
if (data_lo[15:14] == 2)
out_test_pass_r <= data_lo[0+:tests_lp+1];
else
if (data_lo[15:14] == 3)
match_reg_r <= data_lo[0+:$clog2(tests_lp+1)+1];
end
end // else: !if(out_reset_i)
assign yumi_li = v_lo;
// handle opcode -> receive
assign data_li = 16'b0;
assign v_li = (match_reg_r == {out_calib_prepare_i, out_calibration_state_i});
localparam rom_addr_width_lp = 6;
wire [rom_addr_width_lp-1:0] rom_addr_li;
wire [4+16-1:0] rom_data_lo;
bsg_fsb_node_trace_replay
#(.ring_width_p(16)
,.rom_addr_width_p(rom_addr_width_lp)
) tr
(.clk_i(out_clk_i)
,.reset_i(out_reset_i)
,.en_i(1'b1)
,.v_i (v_li)
,.data_i (data_li)
,.ready_o() // ignored
,.v_o (v_lo)
,.data_o (data_lo)
,.yumi_i (yumi_li)
,.rom_addr_o(rom_addr_li)
,.rom_data_i(rom_data_lo)
,.done_o() // cheeky mapping to done signal
,.error_o()
);
// generated with bsg_fsb_master_rom
bsg_comm_link_master_calib_skip_rom
#(.width_p(4+16)
,.addr_width_p(rom_addr_width_lp)
) comm_link_master_rom
(.addr_i(rom_addr_li)
,.data_o(rom_data_lo)
);
endmodule
|
module
cygraph cygraph_inst (
// control signals
.clk (clk_per), // in
.rst (reset_per), // in
.enable (cygraph_enable), // in
.busy (cygraph_busy), // out
.done (cygraph_done), // out
// ae-to-ae signals
.ae_id (i_aeid), // in
.nxtae_rx_data (nxtae_rx_data), // in 32
.nxtae_rx_vld (nxtae_rx_vld), // in
.prvae_rx_data (prvae_rx_data), // in 32
.prvae_rx_vld (prvae_rx_vld), // in
.nxtae_tx_data (nxtae_tx_data), // out 32
.nxtae_tx_vld (nxtae_tx_vld), // out
.prvae_tx_data (prvae_tx_data), // out 32
.prvae_tx_vld (prvae_tx_vld), // out
// Graph Parameters
.n_in (cy_n), // in 64
.non_zeros_in (non_zeros), // in 64
.current_level_in (current_level), // in 64
.cq_count_in (cq_count), // in 64
.nq_count_out (nq_count), // out 64
// Input Graph Pointers (Represented in Custom CSR)
.graphData_in (graphData), // in 64
.graphInfo_in (graphInfo), // in 64
// Queue pointers
.queue1_address_in (queue1_address), // in 64
.queue2_address_in (queue2_address), // in 64
// MC0 port signals
.mc0_req_ld (mc0_req_ld_e), // out
.mc0_req_st (mc0_req_st_e), // out
.mc0_req_size (mc0_req_size_e), // out2
.mc0_req_vaddr (mc0_req_vadr_e), // out48
.mc0_req_wrd_rdctl (mc0_req_wrd_rdctl_e), // out64
.mc0_req_flush (mc0_req_flush_e), // out
.mc0_rd_rq_stall (mc0_rd_rq_stall_e), // in
.mc0_wr_rq_stall (mc0_wr_rq_stall_e), // in
.mc0_rsp_push (mc0_rsp_push_e), // in
.mc0_rsp_stall (mc0_rsp_stall_e), // out
.mc0_rsp_data (mc0_rsp_data_e), // in 64
.mc0_rsp_rdctl (mc0_rsp_rdctl_e), // in 32
.mc0_rsp_flush_cmplt (mc0_rsp_flush_cmplt_e), // in
// MC1 port signals
.mc1_req_ld (mc0_req_ld_o), // out
.mc1_req_st (mc0_req_st_o), // out
.mc1_req_size (mc0_req_size_o), // out2
.mc1_req_vaddr (mc0_req_vadr_o), // out48
.mc1_req_wrd_rdctl (mc0_req_wrd_rdctl_o), // out64
.mc1_req_flush (mc0_req_flush_o), // out
.mc1_rd_rq_stall (mc0_rd_rq_stall_o), // in
.mc1_wr_rq_stall (mc0_wr_rq_stall_o), // in
.mc1_rsp_push (mc0_rsp_push_o), // in
.mc1_rsp_stall (mc0_rsp_stall_o), // out
.mc1_rsp_data (mc0_rsp_data_o), // in 64
.mc1_rsp_rdctl (mc0_rsp_rdctl_o), // in 32
.mc1_rsp_flush_cmplt (mc0_rsp_flush_cmplt_o), // in
// MC2 port signals
.mc2_req_ld (mc1_req_ld_e), // out
.mc2_req_st (mc1_req_st_e), // out
.mc2_req_size (mc1_req_size_e), // out2
.mc2_req_vaddr (mc1_req_vadr_e), // out48
.mc2_req_wrd_rdctl (mc1_req_wrd_rdctl_e), // out64
.mc2_req_flush (mc1_req_flush_e), // out
.mc2_rd_rq_stall (mc1_rd_rq_stall_e), // in
.mc2_wr_rq_stall (mc1_wr_rq_stall_e), // in
.mc2_rsp_push (mc1_rsp_push_e), // in
.mc2_rsp_stall (mc1_rsp_stall_e), // out
.mc2_rsp_data (mc1_rsp_data_e), // in 64
.mc2_rsp_rdctl (mc1_rsp_rdctl_e), // in 32
.mc2_rsp_flush_cmplt (mc1_rsp_flush_cmplt_e), // in
// MC3 port signals
.mc3_req_ld (mc1_req_ld_o), // out
.mc3_req_st (mc1_req_st_o), // out
.mc3_req_size (mc1_req_size_o), // out2
.mc3_req_vaddr (mc1_req_vadr_o), // out48
.mc3_req_wrd_rdctl (mc1_req_wrd_rdctl_o), // out64
.mc3_req_flush (mc1_req_flush_o), // out
.mc3_rd_rq_stall (mc1_rd_rq_stall_o), // in
.mc3_wr_rq_stall (mc1_wr_rq_stall_o), // in
.mc3_rsp_push (mc1_rsp_push_o), // in
.mc3_rsp_stall (mc1_rsp_stall_o), // out
.mc3_rsp_data (mc1_rsp_data_o), // in 64
.mc3_rsp_rdctl (mc1_rsp_rdctl_o), // in 32
.mc3_rsp_flush_cmplt (mc1_rsp_flush_cmplt_o), // in
// MC4 port signals
.mc4_req_ld (mc2_req_ld_e), // out
.mc4_req_st (mc2_req_st_e), // out
.mc4_req_size (mc2_req_size_e), // out2
.mc4_req_vaddr (mc2_req_vadr_e), // out48
.mc4_req_wrd_rdctl (mc2_req_wrd_rdctl_e), // out64
.mc4_req_flush (mc2_req_flush_e), // out
.mc4_rd_rq_stall (mc2_rd_rq_stall_e), // in
.mc4_wr_rq_stall (mc2_wr_rq_stall_e), // in
.mc4_rsp_push (mc2_rsp_push_e), // in
.mc4_rsp_stall (mc2_rsp_stall_e), // out
.mc4_rsp_data (mc2_rsp_data_e), // in 64
.mc4_rsp_rdctl (mc2_rsp_rdctl_e), // in 32
.mc4_rsp_flush_cmplt (mc2_rsp_flush_cmplt_e), // in
// MC5 port signals
.mc5_req_ld (mc2_req_ld_o), // out
.mc5_req_st (mc2_req_st_o), // out
.mc5_req_size (mc2_req_size_o), // out2
.mc5_req_vaddr (mc2_req_vadr_o), // out48
.mc5_req_wrd_rdctl (mc2_req_wrd_rdctl_o), // out64
.mc5_req_flush (mc2_req_flush_o), // out
.mc5_rd_rq_stall (mc2_rd_rq_stall_o), // in
.mc5_wr_rq_stall (mc2_wr_rq_stall_o), // in
.mc5_rsp_push (mc2_rsp_push_o), // in
.mc5_rsp_stall (mc2_rsp_stall_o), // out
.mc5_rsp_data (mc2_rsp_data_o), // in 64
.mc5_rsp_rdctl (mc2_rsp_rdctl_o), // in 32
.mc5_rsp_flush_cmplt (mc2_rsp_flush_cmplt_o), // in
// MC6 port signals
.mc6_req_ld (mc3_req_ld_e), // out
.mc6_req_st (mc3_req_st_e), // out
.mc6_req_size (mc3_req_size_e), // out2
.mc6_req_vaddr (mc3_req_vadr_e), // out48
.mc6_req_wrd_rdctl (mc3_req_wrd_rdctl_e), // out64
.mc6_req_flush (mc3_req_flush_e), // out
.mc6_rd_rq_stall (mc3_rd_rq_stall_e), // in
.mc6_wr_rq_stall (mc3_wr_rq_stall_e), // in
.mc6_rsp_push (mc3_rsp_push_e), // in
.mc6_rsp_stall (mc3_rsp_stall_e), // out
.mc6_rsp_data (mc3_rsp_data_e), // in 64
.mc6_rsp_rdctl (mc3_rsp_rdctl_e), // in 32
.mc6_rsp_flush_cmplt (mc3_rsp_flush_cmplt_e), // in
// MC7 port signals
.mc7_req_ld (mc3_req_ld_o), // out
.mc7_req_st (mc3_req_st_o), // out
.mc7_req_size (mc3_req_size_o), // out2
.mc7_req_vaddr (mc3_req_vadr_o), // out48
.mc7_req_wrd_rdctl (mc3_req_wrd_rdctl_o), // out64
.mc7_req_flush (mc3_req_flush_o), // out
.mc7_rd_rq_stall (mc3_rd_rq_stall_o), // in
.mc7_wr_rq_stall (mc3_wr_rq_stall_o), // in
.mc7_rsp_push (mc3_rsp_push_o), // in
.mc7_rsp_stall (mc3_rsp_stall_o), // out
.mc7_rsp_data (mc3_rsp_data_o), // in 64
.mc7_rsp_rdctl (mc3_rsp_rdctl_o), // in 32
.mc7_rsp_flush_cmplt (mc3_rsp_flush_cmplt_o), // in
// MC8 port signals
.mc8_req_ld (mc4_req_ld_e), // out
.mc8_req_st (mc4_req_st_e), // out
.mc8_req_size (mc4_req_size_e), // out2
.mc8_req_vaddr (mc4_req_vadr_e), // out48
.mc8_req_wrd_rdctl (mc4_req_wrd_rdctl_e), // out64
.mc8_req_flush (mc4_req_flush_e), // out
.mc8_rd_rq_stall (mc4_rd_rq_stall_e), // in
.mc8_wr_rq_stall (mc4_wr_rq_stall_e), // in
.mc8_rsp_push (mc4_rsp_push_e), // in
.mc8_rsp_stall (mc4_rsp_stall_e), // out
.mc8_rsp_data (mc4_rsp_data_e), // in 64
.mc8_rsp_rdctl (mc4_rsp_rdctl_e), // in 32
.mc8_rsp_flush_cmplt (mc4_rsp_flush_cmplt_e), // in
// MC9 port signals
.mc9_req_ld (mc4_req_ld_o), // out
.mc9_req_st (mc4_req_st_o), // out
.mc9_req_size (mc4_req_size_o), // out2
.mc9_req_vaddr (mc4_req_vadr_o), // out48
.mc9_req_wrd_rdctl (mc4_req_wrd_rdctl_o), // out64
.mc9_req_flush (mc4_req_flush_o), // out
.mc9_rd_rq_stall (mc4_rd_rq_stall_o), // in
.mc9_wr_rq_stall (mc4_wr_rq_stall_o), // in
.mc9_rsp_push (mc4_rsp_push_o), // in
.mc9_rsp_stall (mc4_rsp_stall_o), // out
.mc9_rsp_data (mc4_rsp_data_o), // in 64
.mc9_rsp_rdctl (mc4_rsp_rdctl_o), // in 32
.mc9_rsp_flush_cmplt (mc4_rsp_flush_cmplt_o), // in
// MC10 port signals
.mc10_req_ld (mc5_req_ld_e), // out
.mc10_req_st (mc5_req_st_e), // out
.mc10_req_size (mc5_req_size_e), // out2
.mc10_req_vaddr (mc5_req_vadr_e), // out48
.mc10_req_wrd_rdctl (mc5_req_wrd_rdctl_e), // out64
.mc10_req_flush (mc5_req_flush_e), // out
.mc10_rd_rq_stall (mc5_rd_rq_stall_e), // in
.mc10_wr_rq_stall (mc5_wr_rq_stall_e), // in
.mc10_rsp_push (mc5_rsp_push_e), // in
.mc10_rsp_stall (mc5_rsp_stall_e), // out
.mc10_rsp_data (mc5_rsp_data_e), // in 64
.mc10_rsp_rdctl (mc5_rsp_rdctl_e), // in 32
.mc10_rsp_flush_cmplt (mc5_rsp_flush_cmplt_e), // in
// MC11 port signals
.mc11_req_ld (mc5_req_ld_o), // out
.mc11_req_st (mc5_req_st_o), // out
.mc11_req_size (mc5_req_size_o), // out2
.mc11_req_vaddr (mc5_req_vadr_o), // out48
.mc11_req_wrd_rdctl (mc5_req_wrd_rdctl_o), // out64
.mc11_req_flush (mc5_req_flush_o), // out
.mc11_rd_rq_stall (mc5_rd_rq_stall_o), // in
.mc11_wr_rq_stall (mc5_wr_rq_stall_o), // in
.mc11_rsp_push (mc5_rsp_push_o), // in
.mc11_rsp_stall (mc5_rsp_stall_o), // out
.mc11_rsp_data (mc5_rsp_data_o), // in 64
.mc11_rsp_rdctl (mc5_rsp_rdctl_o), // in 32
.mc11_rsp_flush_cmplt (mc5_rsp_flush_cmplt_o), // in
// MC12 port signals
.mc12_req_ld (mc6_req_ld_e), // out
.mc12_req_st (mc6_req_st_e), // out
.mc12_req_size (mc6_req_size_e), // out2
.mc12_req_vaddr (mc6_req_vadr_e), // out48
.mc12_req_wrd_rdctl (mc6_req_wrd_rdctl_e), // out64
.mc12_req_flush (mc6_req_flush_e), // out
.mc12_rd_rq_stall (mc6_rd_rq_stall_e), // in
.mc12_wr_rq_stall (mc6_wr_rq_stall_e), // in
.mc12_rsp_push (mc6_rsp_push_e), // in
.mc12_rsp_stall (mc6_rsp_stall_e), // out
.mc12_rsp_data (mc6_rsp_data_e), // in 64
.mc12_rsp_rdctl (mc6_rsp_rdctl_e), // in 32
.mc12_rsp_flush_cmplt (mc6_rsp_flush_cmplt_e), // in
// MC13 port signals
.mc13_req_ld (mc6_req_ld_o), // out
.mc13_req_st (mc6_req_st_o), // out
.mc13_req_size (mc6_req_size_o), // out2
.mc13_req_vaddr (mc6_req_vadr_o), // out48
.mc13_req_wrd_rdctl (mc6_req_wrd_rdctl_o), // out64
.mc13_req_flush (mc6_req_flush_o), // out
.mc13_rd_rq_stall (mc6_rd_rq_stall_o), // in
.mc13_wr_rq_stall (mc6_wr_rq_stall_o), // in
.mc13_rsp_push (mc6_rsp_push_o), // in
.mc13_rsp_stall (mc6_rsp_stall_o), // out
.mc13_rsp_data (mc6_rsp_data_o), // in 64
.mc13_rsp_rdctl (mc6_rsp_rdctl_o), // in 32
.mc13_rsp_flush_cmplt (mc6_rsp_flush_cmplt_o), // in
// MC14 port signals
.mc14_req_ld (mc7_req_ld_e), // out
.mc14_req_st (mc7_req_st_e), // out
.mc14_req_size (mc7_req_size_e), // out2
.mc14_req_vaddr (mc7_req_vadr_e), // out48
.mc14_req_wrd_rdctl (mc7_req_wrd_rdctl_e), // out64
.mc14_req_flush (mc7_req_flush_e), // out
.mc14_rd_rq_stall (mc7_rd_rq_stall_e), // in
.mc14_wr_rq_stall (mc7_wr_rq_stall_e), // in
.mc14_rsp_push (mc7_rsp_push_e), // in
.mc14_rsp_stall (mc7_rsp_stall_e), // out
.mc14_rsp_data (mc7_rsp_data_e), // in 64
.mc14_rsp_rdctl (mc7_rsp_rdctl_e), // in 32
.mc14_rsp_flush_cmplt (mc7_rsp_flush_cmplt_e), // in
// MC15 port signals
.mc15_req_ld (mc7_req_ld_o), // out
.mc15_req_st (mc7_req_st_o), // out
.mc15_req_size (mc7_req_size_o), // out2
.mc15_req_vaddr (mc7_req_vadr_o), // out48
.mc15_req_wrd_rdctl (mc7_req_wrd_rdctl_o), // out64
.mc15_req_flush (mc7_req_flush_o), // out
.mc15_rd_rq_stall (mc7_rd_rq_stall_o), // in
.mc15_wr_rq_stall (mc7_wr_rq_stall_o), // in
.mc15_rsp_push (mc7_rsp_push_o), // in
.mc15_rsp_stall (mc7_rsp_stall_o), // out
.mc15_rsp_data (mc7_rsp_data_o), // in 64
.mc15_rsp_rdctl (mc7_rsp_rdctl_o), // in 32
.mc15_rsp_flush_cmplt (mc7_rsp_flush_cmplt_o) // in
);
/* ---------- debug & synopsys off blocks ---------- */
// synopsys translate_off
// Parameters: 1-Severity: Don't Stop, 2-start check only after negedge of reset
//assert_never #(1, 2, "***ERROR ASSERT: unimplemented instruction cracked") a0 (.clk(clk), .reset_n(~reset), .test_expr(r_unimplemented_inst));
// synopsys translate_on
endmodule
|
module zynq_1_xbar_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire [0 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire [0 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST" *)
input wire [0 : 0] s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire [0 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire [0 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire [0 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire [0 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire [0 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire [0 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST" *)
output wire [0 : 0] s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire [0 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI AWID [11:0] [23:12], xilinx.com:interface:aximm:1.0 M02_AXI AWID [11:0] [35:24]" *)
output wire [35 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64]" *)
output wire [95 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI AWLEN [7:0] [23:16]" *)
output wire [23 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWSIZE [2:0] [8:6]" *)
output wire [8 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI AWBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI AWBURST [1:0] [5:4]" *)
output wire [5 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWLOCK [0:0] [2:2]" *)
output wire [2 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWCACHE [3:0] [11:8]" *)
output wire [11 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6]" *)
output wire [8 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWREGION [3:0] [11:8]" *)
output wire [11 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWQOS [3:0] [11:8]" *)
output wire [11 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2]" *)
output wire [2 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2]" *)
input wire [2 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64]" *)
output wire [95 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8]" *)
output wire [11 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WLAST [0:0] [2:2]" *)
output wire [2 : 0] m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2]" *)
output wire [2 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2]" *)
input wire [2 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI BID [11:0] [23:12], xilinx.com:interface:aximm:1.0 M02_AXI BID [11:0] [35:24]" *)
input wire [35 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4]" *)
input wire [5 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2]" *)
input wire [2 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2]" *)
output wire [2 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI ARID [11:0] [23:12], xilinx.com:interface:aximm:1.0 M02_AXI ARID [11:0] [35:24]" *)
output wire [35 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64]" *)
output wire [95 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI ARLEN [7:0] [23:16]" *)
output wire [23 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARSIZE [2:0] [8:6]" *)
output wire [8 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI ARBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI ARBURST [1:0] [5:4]" *)
output wire [5 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARLOCK [0:0] [2:2]" *)
output wire [2 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARCACHE [3:0] [11:8]" *)
output wire [11 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6]" *)
output wire [8 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARREGION [3:0] [11:8]" *)
output wire [11 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARQOS [3:0] [11:8]" *)
output wire [11 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2]" *)
output wire [2 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2]" *)
input wire [2 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI RID [11:0] [23:12], xilinx.com:interface:aximm:1.0 M02_AXI RID [11:0] [35:24]" *)
input wire [35 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64]" *)
input wire [95 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4]" *)
input wire [5 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RLAST [0:0] [2:2]" *)
input wire [2 : 0] m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2]" *)
input wire [2 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2]" *)
output wire [2 : 0] m_axi_rready;
axi_crossbar_v2_1_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(1),
.C_NUM_MASTER_SLOTS(3),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(0),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(192'H00000000400000000000000041e000000000000041200000),
.C_M_AXI_ADDR_WIDTH(96'H0000000c0000000c00000010),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H0000000c),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(96'H000000010000000100000001),
.C_M_AXI_READ_CONNECTIVITY(96'H000000010000000100000001),
.C_R_REGISTER(0),
.C_S_AXI_SINGLE_THREAD(32'H00000000),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000008),
.C_S_AXI_READ_ACCEPTANCE(32'H00000008),
.C_M_AXI_WRITE_ISSUING(96'H000000020000000200000002),
.C_M_AXI_READ_ISSUING(96'H000000020000000200000002),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
.C_M_AXI_SECURE(96'H000000000000000000000000),
.C_CONNECTIVITY_MODE(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(12'H000),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(3'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(3'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
module i2c_master(
clk, // input
reset_n, // input asynchronous
reset, // input synchronous
sda, // inout
scl, // inout
tx_byte, // input, byte to send to slave, the payload
rx_byte, // output, byte received from slave, the payload
tx_start_condition, // input, high, when i2c master is to send a start signal
tx_stop_condition, // input, high, when i2c master is to send a stop signal
tx_data, // input, high, when i2c master is to send a byte as given in tx_byte
rx_data, // input, high, when i2c master is to receive a byte and output it in rx_byte
start, // input, starts i2c master
done, // output, high when i2c master done
i2c_master_state // output, read by rf
);
`include "parameters_global.v"
input clk;
input reset_n;
input reset;
inout sda, scl;
input [`byte_width-1:0] tx_byte;
output reg [`byte_width-1:0] rx_byte;
input tx_start_condition;
input tx_stop_condition;
input tx_data;
input rx_data;
input start;
output reg done;
output reg [`byte_width-1:0] i2c_master_state;
reg [`byte_width-1:0] i2c_master_state_last, i2c_wait_count;
`define bit_pointer_width 4 // must count up to 9 bits during tx or rx
reg [`bit_pointer_width-1:0] bit_pointer;
parameter bit_pointer_init = `bit_pointer_width'h7;
`define sda_sample_width 3
reg [`sda_sample_width-1:0] sda_sample; // holds 3 samples of sda / before rising scl, after rising scl, after setting scl
parameter all_sda_samples_zero = `sda_sample_width'b000;
parameter i2c_driver_off = 1'b1;
parameter i2c_driver_on = 1'b0;
reg driver_scl;
reg driver_sda;
assign scl = driver_scl ? 1'bz : 1'b0;
assign sda = driver_sda ? 1'bz : 1'b0;
always @(posedge clk or negedge reset_n) begin
if (~reset_n)
begin
done <= #`DEL 1'b0;
i2c_master_state <= #`DEL I2C_MASTER_STATE_IDLE;
i2c_wait_count <= #`DEL i2c_wait_count_init;
driver_scl <= #`DEL i2c_driver_off;
driver_sda <= #`DEL i2c_driver_off;
bit_pointer <= #`DEL bit_pointer_init;
sda_sample <= #`DEL `sda_sample_width'b000;
end
else
begin
if (reset)
begin
done <= #`DEL 1'b0;
i2c_master_state <= #`DEL I2C_MASTER_STATE_IDLE;
i2c_wait_count <= #`DEL i2c_wait_count_init;
driver_scl <= #`DEL i2c_driver_off;
driver_sda <= #`DEL i2c_driver_off;
bit_pointer <= #`DEL bit_pointer_init;
sda_sample <= #`DEL `sda_sample_width'b000;
end
else
begin
case (i2c_master_state) // synthesis parallel_case
// RESET / IDLE
I2C_MASTER_STATE_IDLE:
begin
//i2c_wait_count <= #`DEL i2c_wait_count_init;
done <= #`DEL 1'b0;
if (start)
begin
if (tx_stop_condition)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_STOP_1; // 2h
end
else if (tx_start_condition)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_START_1; // 4h
end
else if (tx_data)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_TX_1; // 6h
end
// else if (rx_data)
// begin
// i2c_master_state <= #`DEL I2C_MASTER_STATE_RX_1;
// end
end
end
// WAIT STATES
I2C_MASTER_STATE_WAIT: // 1h
begin
if (i2c_wait_count == 0)
begin
i2c_master_state <= #`DEL i2c_master_state_last;
end
else
begin
i2c_wait_count <= #`DEL i2c_wait_count - 1;
end
end
// NOTE: FOR THE FOLLOWING STATES THIS RULE APPLIES: ACT,WAIT -> NEXT STATE -> ACT,WAIT -> NEXT STATE ...
// SEND STOP CONDITION
I2C_MASTER_STATE_STOP_1: // 2h
begin
driver_scl <= #`DEL i2c_driver_off;
if (i2c_wait_count == 0)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_STOP_2; // 03h
i2c_wait_count <= #`DEL i2c_wait_count_init;
end
else
begin
i2c_master_state_last <= #`DEL i2c_master_state;
i2c_master_state <= #`DEL I2C_MASTER_STATE_WAIT; // 01h
end
end
I2C_MASTER_STATE_STOP_2: // 03h
begin
driver_sda <= #`DEL i2c_driver_off;
if (i2c_wait_count == 0)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_IDLE;
i2c_wait_count <= #`DEL i2c_wait_count_init;
done <= #`DEL 1'b1;
end
else
begin
i2c_master_state_last <= #`DEL i2c_master_state;
i2c_master_state <= #`DEL I2C_MASTER_STATE_WAIT;
end
end
// SEND START CONDITION
I2C_MASTER_STATE_START_1: // 4h
begin
driver_sda <= #`DEL i2c_driver_on;
if (i2c_wait_count == 0)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_START_2; // 5h
i2c_wait_count <= #`DEL i2c_wait_count_init;
end
else
begin
i2c_master_state_last <= #`DEL i2c_master_state;
i2c_master_state <= #`DEL I2C_MASTER_STATE_WAIT; // 01h
end
end
I2C_MASTER_STATE_START_2: // 5h
begin
driver_scl <= #`DEL i2c_driver_on;
if (i2c_wait_count == 0)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_IDLE; // 00h
i2c_wait_count <= #`DEL i2c_wait_count_init;
done <= #`DEL 1'b1;
end
else
begin
i2c_master_state_last <= #`DEL i2c_master_state;
i2c_master_state <= #`DEL I2C_MASTER_STATE_WAIT; // 01h
end
end
// DATA TX
I2C_MASTER_STATE_TX_1: // 6h
begin
if (i2c_wait_count == 0)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_TX_2;
i2c_wait_count <= #`DEL i2c_wait_count_init;
end
else
begin
driver_sda <= #`DEL tx_byte[bit_pointer];
i2c_master_state_last <= #`DEL i2c_master_state;
i2c_master_state <= #`DEL I2C_MASTER_STATE_WAIT; // 01h
end
end
I2C_MASTER_STATE_TX_2:
begin
if (i2c_wait_count == 0)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_TX_3;
i2c_wait_count <= #`DEL i2c_wait_count_init;
end
else
begin
driver_scl <= #`DEL i2c_driver_off;
i2c_master_state_last <= #`DEL i2c_master_state;
i2c_master_state <= #`DEL I2C_MASTER_STATE_WAIT; // 01h
end
end
I2C_MASTER_STATE_TX_3:
begin
if (i2c_wait_count == 0)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_TX_4;
i2c_wait_count <= #`DEL i2c_wait_count_init;
end
else
begin
driver_scl <= #`DEL i2c_driver_on;
i2c_master_state_last <= #`DEL i2c_master_state;
i2c_master_state <= #`DEL I2C_MASTER_STATE_WAIT; // 01h
end
end
I2C_MASTER_STATE_TX_4: // 09h
begin
if (bit_pointer == 0) // if last bit processed (LSB)
begin
driver_sda <= #`DEL i2c_driver_off; // release sda
i2c_master_state <= #`DEL I2C_MASTER_STATE_TX_5;
end
else
begin // if not last bit processed, advance bit pointer one bit towards LSB (right)
bit_pointer <= #`DEL bit_pointer - 1;
i2c_master_state <= #`DEL I2C_MASTER_STATE_TX_1; // start sending next bit
end
end
I2C_MASTER_STATE_TX_5: // 0Ah // wait until sda is stable , slave should be sending acknowledge (zero) already
begin
if (i2c_wait_count == 0)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_TX_6;
i2c_wait_count <= #`DEL i2c_wait_count_init;
sda_sample[0] <= #`DEL sda; // take sample #1 from sda
end
else
begin
i2c_master_state_last <= #`DEL i2c_master_state;
i2c_master_state <= #`DEL I2C_MASTER_STATE_WAIT; // 01h
end
end
I2C_MASTER_STATE_TX_6: // 0Bh // register acknowledge from slave // acknowledge clock cycle begin
// sample sda while scl posedge
begin
if (i2c_wait_count == 0)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_TX_7;
i2c_wait_count <= #`DEL i2c_wait_count_init;
end
else
begin
driver_scl <= #`DEL i2c_driver_off; // scl L-H edge
i2c_master_state_last <= #`DEL i2c_master_state;
i2c_master_state <= #`DEL I2C_MASTER_STATE_WAIT; // 01h
sda_sample[1] <= #`DEL sda; // take sample #2 from sda
end
end
I2C_MASTER_STATE_TX_7: // 0Ch // register acknowledge from slave // acknowledge clock cycle end
// sample sda while scl negedge
begin
if (i2c_wait_count == 0)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_TX_8;
i2c_wait_count <= #`DEL i2c_wait_count_init;
end
else
begin
driver_scl <= #`DEL i2c_driver_on; // scl H-L edge
i2c_master_state_last <= #`DEL i2c_master_state;
i2c_master_state <= #`DEL I2C_MASTER_STATE_WAIT; // 01h
sda_sample[2] <= #`DEL sda; // take sample #2 from sda
end
end
I2C_MASTER_STATE_TX_8: // 0Dh // evaluate acknowledge bit received from slave
begin
if (i2c_wait_count == 0)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_TX_9; // 0Eh
i2c_wait_count <= #`DEL i2c_wait_count_init;
bit_pointer <= #`DEL bit_pointer_init;
//done <= #`DEL 1'b1;
end
else
begin // all sda samples must be zero, otherwise no acknowledge received -> error
if (sda_sample == all_sda_samples_zero)
begin
i2c_master_state_last <= #`DEL i2c_master_state;
i2c_master_state <= #`DEL I2C_MASTER_STATE_WAIT; // 01h
end
else
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_ERROR;
end
end
end
I2C_MASTER_STATE_TX_9: // 0Eh // finish write cycle by driving sda low
begin
if (i2c_wait_count == 0)
begin
i2c_master_state <= #`DEL I2C_MASTER_STATE_IDLE;
i2c_wait_count <= #`DEL i2c_wait_count_init;
//bit_pointer <= #`DEL bit_pointer_init;
done <= #`DEL 1'b1;
end
else
begin // drive sda low
driver_sda <= #`DEL i2c_driver_on; // sda L
i2c_master_state_last <= #`DEL i2c_master_state;
i2c_master_state <= #`DEL I2C_MASTER_STATE_WAIT; // 01h
end
end
endcase
end
end
end
endmodule
|
module altera_mult_add_q1u2
(
aclr0,
clock0,
dataa,
datab,
result) /* synthesis synthesis_clearbox=1 */;
input aclr0;
input clock0;
input [15:0] dataa;
input [15:0] datab;
output [31:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr0;
tri1 clock0;
tri0 [15:0] dataa;
tri0 [15:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] wire_altera_mult_add_rtl1_result;
altera_mult_add_rtl altera_mult_add_rtl1
(
.aclr0(aclr0),
.chainout_sat_overflow(),
.clock0(clock0),
.dataa(dataa),
.datab(datab),
.mult0_is_saturated(),
.mult1_is_saturated(),
.mult2_is_saturated(),
.mult3_is_saturated(),
.overflow(),
.result(wire_altera_mult_add_rtl1_result),
.scanouta(),
.scanoutb(),
.accum_sload(1'b0),
.aclr1(1'b0),
.aclr2(1'b0),
.aclr3(1'b0),
.addnsub1(1'b1),
.addnsub1_round(1'b0),
.addnsub3(1'b1),
.addnsub3_round(1'b0),
.chainin({1{1'b0}}),
.chainout_round(1'b0),
.chainout_saturate(1'b0),
.clock1(1'b1),
.clock2(1'b1),
.clock3(1'b1),
.coefsel0({3{1'b0}}),
.coefsel1({3{1'b0}}),
.coefsel2({3{1'b0}}),
.coefsel3({3{1'b0}}),
.datac({22{1'b0}}),
.ena0(1'b1),
.ena1(1'b1),
.ena2(1'b1),
.ena3(1'b1),
.mult01_round(1'b0),
.mult01_saturation(1'b0),
.mult23_round(1'b0),
.mult23_saturation(1'b0),
.negate(1'b0),
.output_round(1'b0),
.output_saturate(1'b0),
.rotate(1'b0),
.scanina({16{1'b0}}),
.scaninb({16{1'b0}}),
.shift_right(1'b0),
.signa(1'b0),
.signb(1'b0),
.sload_accum(1'b0),
.sourcea({1{1'b0}}),
.sourceb({1{1'b0}}),
.zero_chainout(1'b0),
.zero_loopback(1'b0)
);
defparam
altera_mult_add_rtl1.accum_direction = "ADD",
altera_mult_add_rtl1.accum_sload_aclr = "NONE",
altera_mult_add_rtl1.accum_sload_latency_aclr = "NONE",
altera_mult_add_rtl1.accum_sload_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.accum_sload_register = "UNREGISTERED",
altera_mult_add_rtl1.accumulator = "NO",
altera_mult_add_rtl1.adder1_rounding = "NO",
altera_mult_add_rtl1.adder3_rounding = "NO",
altera_mult_add_rtl1.addnsub1_round_aclr = "NONE",
altera_mult_add_rtl1.addnsub1_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.addnsub1_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub1_round_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub3_round_aclr = "NONE",
altera_mult_add_rtl1.addnsub3_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.addnsub3_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub3_round_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_aclr1 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_aclr3 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_latency_aclr1 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_latency_aclr3 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_latency_clock1 = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_latency_clock3 = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_register1 = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_register3 = "UNREGISTERED",
altera_mult_add_rtl1.chainout_aclr = "NONE",
altera_mult_add_rtl1.chainout_adder = "NO",
altera_mult_add_rtl1.chainout_adder_direction = "ADD",
altera_mult_add_rtl1.chainout_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_round_aclr = "NONE",
altera_mult_add_rtl1.chainout_round_output_aclr = "NONE",
altera_mult_add_rtl1.chainout_round_output_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.chainout_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_round_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_rounding = "NO",
altera_mult_add_rtl1.chainout_saturate_aclr = "NONE",
altera_mult_add_rtl1.chainout_saturate_output_aclr = "NONE",
altera_mult_add_rtl1.chainout_saturate_output_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_saturate_pipeline_aclr = "NONE",
altera_mult_add_rtl1.chainout_saturate_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_saturate_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_saturation = "NO",
altera_mult_add_rtl1.coef0_0 = 0,
altera_mult_add_rtl1.coef0_1 = 0,
altera_mult_add_rtl1.coef0_2 = 0,
altera_mult_add_rtl1.coef0_3 = 0,
altera_mult_add_rtl1.coef0_4 = 0,
altera_mult_add_rtl1.coef0_5 = 0,
altera_mult_add_rtl1.coef0_6 = 0,
altera_mult_add_rtl1.coef0_7 = 0,
altera_mult_add_rtl1.coef1_0 = 0,
altera_mult_add_rtl1.coef1_1 = 0,
altera_mult_add_rtl1.coef1_2 = 0,
altera_mult_add_rtl1.coef1_3 = 0,
altera_mult_add_rtl1.coef1_4 = 0,
altera_mult_add_rtl1.coef1_5 = 0,
altera_mult_add_rtl1.coef1_6 = 0,
altera_mult_add_rtl1.coef1_7 = 0,
altera_mult_add_rtl1.coef2_0 = 0,
altera_mult_add_rtl1.coef2_1 = 0,
altera_mult_add_rtl1.coef2_2 = 0,
altera_mult_add_rtl1.coef2_3 = 0,
altera_mult_add_rtl1.coef2_4 = 0,
altera_mult_add_rtl1.coef2_5 = 0,
altera_mult_add_rtl1.coef2_6 = 0,
altera_mult_add_rtl1.coef2_7 = 0,
altera_mult_add_rtl1.coef3_0 = 0,
altera_mult_add_rtl1.coef3_1 = 0,
altera_mult_add_rtl1.coef3_2 = 0,
altera_mult_add_rtl1.coef3_3 = 0,
altera_mult_add_rtl1.coef3_4 = 0,
altera_mult_add_rtl1.coef3_5 = 0,
altera_mult_add_rtl1.coef3_6 = 0,
altera_mult_add_rtl1.coef3_7 = 0,
altera_mult_add_rtl1.coefsel0_aclr = "NONE",
altera_mult_add_rtl1.coefsel0_latency_aclr = "NONE",
altera_mult_add_rtl1.coefsel0_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.coefsel0_register = "UNREGISTERED",
altera_mult_add_rtl1.coefsel1_aclr = "NONE",
altera_mult_add_rtl1.coefsel1_latency_aclr = "NONE",
altera_mult_add_rtl1.coefsel1_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.coefsel1_register = "UNREGISTERED",
altera_mult_add_rtl1.coefsel2_aclr = "NONE",
altera_mult_add_rtl1.coefsel2_latency_aclr = "NONE",
altera_mult_add_rtl1.coefsel2_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.coefsel2_register = "UNREGISTERED",
altera_mult_add_rtl1.coefsel3_aclr = "NONE",
altera_mult_add_rtl1.coefsel3_latency_aclr = "NONE",
altera_mult_add_rtl1.coefsel3_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.coefsel3_register = "UNREGISTERED",
altera_mult_add_rtl1.dedicated_multiplier_circuitry = "YES",
altera_mult_add_rtl1.double_accum = "NO",
altera_mult_add_rtl1.dsp_block_balancing = "Auto",
altera_mult_add_rtl1.extra_latency = 0,
altera_mult_add_rtl1.input_a0_latency_aclr = "NONE",
altera_mult_add_rtl1.input_a0_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_a1_latency_aclr = "NONE",
altera_mult_add_rtl1.input_a1_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_a2_latency_aclr = "NONE",
altera_mult_add_rtl1.input_a2_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_a3_latency_aclr = "NONE",
altera_mult_add_rtl1.input_a3_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_aclr_a0 = "NONE",
altera_mult_add_rtl1.input_aclr_a1 = "NONE",
altera_mult_add_rtl1.input_aclr_a2 = "NONE",
altera_mult_add_rtl1.input_aclr_a3 = "NONE",
altera_mult_add_rtl1.input_aclr_b0 = "NONE",
altera_mult_add_rtl1.input_aclr_b1 = "NONE",
altera_mult_add_rtl1.input_aclr_b2 = "NONE",
altera_mult_add_rtl1.input_aclr_b3 = "NONE",
altera_mult_add_rtl1.input_aclr_c0 = "NONE",
altera_mult_add_rtl1.input_aclr_c1 = "NONE",
altera_mult_add_rtl1.input_aclr_c2 = "NONE",
altera_mult_add_rtl1.input_aclr_c3 = "NONE",
altera_mult_add_rtl1.input_b0_latency_aclr = "NONE",
altera_mult_add_rtl1.input_b0_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_b1_latency_aclr = "NONE",
altera_mult_add_rtl1.input_b1_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_b2_latency_aclr = "NONE",
altera_mult_add_rtl1.input_b2_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_b3_latency_aclr = "NONE",
altera_mult_add_rtl1.input_b3_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_c0_latency_aclr = "NONE",
altera_mult_add_rtl1.input_c0_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_c1_latency_aclr = "NONE",
altera_mult_add_rtl1.input_c1_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_c2_latency_aclr = "NONE",
altera_mult_add_rtl1.input_c2_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_c3_latency_aclr = "NONE",
altera_mult_add_rtl1.input_c3_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a0 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a1 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a2 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a3 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b0 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b1 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b2 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b3 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c0 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c1 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c2 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c3 = "UNREGISTERED",
altera_mult_add_rtl1.input_source_a0 = "DATAA",
altera_mult_add_rtl1.input_source_a1 = "DATAA",
altera_mult_add_rtl1.input_source_a2 = "DATAA",
altera_mult_add_rtl1.input_source_a3 = "DATAA",
altera_mult_add_rtl1.input_source_b0 = "DATAB",
altera_mult_add_rtl1.input_source_b1 = "DATAB",
altera_mult_add_rtl1.input_source_b2 = "DATAB",
altera_mult_add_rtl1.input_source_b3 = "DATAB",
altera_mult_add_rtl1.latency = 0,
altera_mult_add_rtl1.loadconst_control_aclr = "NONE",
altera_mult_add_rtl1.loadconst_control_register = "UNREGISTERED",
altera_mult_add_rtl1.loadconst_value = 64,
altera_mult_add_rtl1.mult01_round_aclr = "NONE",
altera_mult_add_rtl1.mult01_round_register = "UNREGISTERED",
altera_mult_add_rtl1.mult01_saturation_aclr = "ACLR0",
altera_mult_add_rtl1.mult01_saturation_register = "UNREGISTERED",
altera_mult_add_rtl1.mult23_round_aclr = "NONE",
altera_mult_add_rtl1.mult23_round_register = "UNREGISTERED",
altera_mult_add_rtl1.mult23_saturation_aclr = "NONE",
altera_mult_add_rtl1.mult23_saturation_register = "UNREGISTERED",
altera_mult_add_rtl1.multiplier01_rounding = "NO",
altera_mult_add_rtl1.multiplier01_saturation = "NO",
altera_mult_add_rtl1.multiplier1_direction = "ADD",
altera_mult_add_rtl1.multiplier23_rounding = "NO",
altera_mult_add_rtl1.multiplier23_saturation = "NO",
altera_mult_add_rtl1.multiplier3_direction = "ADD",
altera_mult_add_rtl1.multiplier_aclr0 = "ACLR0",
altera_mult_add_rtl1.multiplier_aclr1 = "NONE",
altera_mult_add_rtl1.multiplier_aclr2 = "NONE",
altera_mult_add_rtl1.multiplier_aclr3 = "NONE",
altera_mult_add_rtl1.multiplier_register0 = "CLOCK0",
altera_mult_add_rtl1.multiplier_register1 = "UNREGISTERED",
altera_mult_add_rtl1.multiplier_register2 = "UNREGISTERED",
altera_mult_add_rtl1.multiplier_register3 = "UNREGISTERED",
altera_mult_add_rtl1.negate_aclr = "NONE",
altera_mult_add_rtl1.negate_latency_aclr = "NONE",
altera_mult_add_rtl1.negate_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.negate_register = "UNREGISTERED",
altera_mult_add_rtl1.number_of_multipliers = 1,
altera_mult_add_rtl1.output_aclr = "NONE",
altera_mult_add_rtl1.output_register = "UNREGISTERED",
altera_mult_add_rtl1.output_round_aclr = "NONE",
altera_mult_add_rtl1.output_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.output_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.output_round_register = "UNREGISTERED",
altera_mult_add_rtl1.output_round_type = "NEAREST_INTEGER",
altera_mult_add_rtl1.output_rounding = "NO",
altera_mult_add_rtl1.output_saturate_aclr = "NONE",
altera_mult_add_rtl1.output_saturate_pipeline_aclr = "NONE",
altera_mult_add_rtl1.output_saturate_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.output_saturate_register = "UNREGISTERED",
altera_mult_add_rtl1.output_saturate_type = "ASYMMETRIC",
altera_mult_add_rtl1.output_saturation = "NO",
altera_mult_add_rtl1.port_addnsub1 = "PORT_UNUSED",
altera_mult_add_rtl1.port_addnsub3 = "PORT_UNUSED",
altera_mult_add_rtl1.port_chainout_sat_is_overflow = "PORT_UNUSED",
altera_mult_add_rtl1.port_negate = "PORT_UNUSED",
altera_mult_add_rtl1.port_output_is_overflow = "PORT_UNUSED",
altera_mult_add_rtl1.port_signa = "PORT_UNUSED",
altera_mult_add_rtl1.port_signb = "PORT_UNUSED",
altera_mult_add_rtl1.preadder_direction_0 = "ADD",
altera_mult_add_rtl1.preadder_direction_1 = "ADD",
altera_mult_add_rtl1.preadder_direction_2 = "ADD",
altera_mult_add_rtl1.preadder_direction_3 = "ADD",
altera_mult_add_rtl1.preadder_mode = "SIMPLE",
altera_mult_add_rtl1.representation_a = "UNSIGNED",
altera_mult_add_rtl1.representation_b = "UNSIGNED",
altera_mult_add_rtl1.rotate_aclr = "NONE",
altera_mult_add_rtl1.rotate_output_aclr = "NONE",
altera_mult_add_rtl1.rotate_output_register = "UNREGISTERED",
altera_mult_add_rtl1.rotate_pipeline_aclr = "NONE",
altera_mult_add_rtl1.rotate_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.rotate_register = "UNREGISTERED",
altera_mult_add_rtl1.scanouta_aclr = "NONE",
altera_mult_add_rtl1.scanouta_register = "UNREGISTERED",
altera_mult_add_rtl1.selected_device_family = "Cyclone IV E",
altera_mult_add_rtl1.shift_mode = "NO",
altera_mult_add_rtl1.shift_right_aclr = "NONE",
altera_mult_add_rtl1.shift_right_output_aclr = "NONE",
altera_mult_add_rtl1.shift_right_output_register = "UNREGISTERED",
altera_mult_add_rtl1.shift_right_pipeline_aclr = "NONE",
altera_mult_add_rtl1.shift_right_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.shift_right_register = "UNREGISTERED",
altera_mult_add_rtl1.signed_aclr_a = "NONE",
altera_mult_add_rtl1.signed_aclr_b = "NONE",
altera_mult_add_rtl1.signed_latency_aclr_a = "NONE",
altera_mult_add_rtl1.signed_latency_aclr_b = "NONE",
altera_mult_add_rtl1.signed_latency_clock_a = "UNREGISTERED",
altera_mult_add_rtl1.signed_latency_clock_b = "UNREGISTERED",
altera_mult_add_rtl1.signed_register_a = "UNREGISTERED",
altera_mult_add_rtl1.signed_register_b = "UNREGISTERED",
altera_mult_add_rtl1.systolic_aclr1 = "NONE",
altera_mult_add_rtl1.systolic_aclr3 = "NONE",
altera_mult_add_rtl1.systolic_delay1 = "UNREGISTERED",
altera_mult_add_rtl1.systolic_delay3 = "UNREGISTERED",
altera_mult_add_rtl1.use_sload_accum_port = "NO",
altera_mult_add_rtl1.use_subnadd = "NO",
altera_mult_add_rtl1.width_a = 16,
altera_mult_add_rtl1.width_b = 16,
altera_mult_add_rtl1.width_c = 22,
altera_mult_add_rtl1.width_chainin = 1,
altera_mult_add_rtl1.width_coef = 18,
altera_mult_add_rtl1.width_msb = 17,
altera_mult_add_rtl1.width_result = 32,
altera_mult_add_rtl1.width_saturate_sign = 1,
altera_mult_add_rtl1.zero_chainout_output_aclr = "NONE",
altera_mult_add_rtl1.zero_chainout_output_register = "UNREGISTERED",
altera_mult_add_rtl1.zero_loopback_aclr = "NONE",
altera_mult_add_rtl1.zero_loopback_output_aclr = "NONE",
altera_mult_add_rtl1.zero_loopback_output_register = "UNREGISTERED",
altera_mult_add_rtl1.zero_loopback_pipeline_aclr = "NONE",
altera_mult_add_rtl1.zero_loopback_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.zero_loopback_register = "UNREGISTERED",
altera_mult_add_rtl1.lpm_type = "altera_mult_add_rtl";
assign
result = wire_altera_mult_add_rtl1_result;
endmodule
|
module Convert_Float_To_Fixed(
//INPUTS
input wire CLK, //CLOCK
input wire [31:0] FLOAT, //VALOR DEL NUMERO EN PUNTO FLOTANTE
input wire EN_REG1, //ENABLE PARA EL REGISTRO 1 QUE GUARDA EL NUMERO EN PUNTO FLOTANTE
input wire LOAD, //SELECCION CARGA REGISTRO DE DESPLZAMIENTOS
input wire MS_1, //SELECCIONA EL MUX PARA UN VALOR DIFERENTE O IGUAL A 127 SEGUN SEA EL CASO
input wire RST,
input wire EN_REG2,
//OUTPUTS
output wire Exp_out, //INIDICA SI EL EXPONENTE ES MAYOR QUE 127
output wire [31:0] FIXED, //CONTIENE EL RESULTADO EN COMA FIJA
output wire [7:0] Exp //CONTIENE EL VALOR INICIAL DEL EXPONENTE
);
parameter P = 32;
parameter W = 8;
wire [31:0] float;
FF_D #(.P(P)) REG_FLOAT_I (
.CLK(CLK),
.RST(RST),
.EN(EN_REG1),
.D(FLOAT),
.Q(float)
);
Comparador_Mayor EXP127_I(
.CLK(CLK),
.A(float[30:23]),
.B(8'b01111111),
.Out(Exp_out)
);
wire [31:0] IN_BS;
wire [31:0] P_RESULT;
wire [31:0] MUX32;
wire [31:0] MUX32_OUT;
wire [31:0] NORM;
wire [7:0] MUX1;
wire [7:0] MUX2;
wire [7:0] SUBT_1;
wire [7:0] SUBT_2;
assign IN_BS [31:27] = 5'b00000;
assign IN_BS [26] = 1'b1;
assign IN_BS [25:3] = float[22:0];
assign IN_BS [2:0] = 3'b000;
assign Exp = float[30:23];
Barrel_Shifter #(.SWR(32),.EWR(8)) S_REG_I(
.clk(CLK),
.rst(RST),
.load_i(LOAD),
.Shift_Value_i(MUX2),
.Shift_Data_i(IN_BS),
.Left_Right_i(Exp_out),
.Bit_Shift_i(1'b0),
.N_mant_o(P_RESULT)
);
S_SUBT #(.P(W),.W(W)) SUBT_EXP_1_I (
.A(float[30:23]),
.B(8'b01111111),
.Y(SUBT_1)
);
S_SUBT #(.P(W),.W(W)) SUBT_EXP_2_I (
.A(8'b01111111),
.B(float[30:23]),
.Y(SUBT_2)
);
Mux_2x1_8Bits MUX2x1_1_I (
.MS(Exp_out),
.D_0(SUBT_2),
.D_1(SUBT_1),
.D_out(MUX1)
);
Mux_2x1_8Bits MUX2x1_2_I (
.MS(MS_1),
.D_0(8'b00000000),
.D_1(MUX1),
.D_out(MUX2)
);
SUBT_32Bits SUBT_RESULT_I (
.A(32'b00000000000000000000000000000000),
.B(P_RESULT),
.Y(MUX32)
);
Mux_2x1 #(.P(P)) MUX2x1_32Bits (
.MS(float[31]),
.D_0(P_RESULT),
.D_1(MUX32),
.D_out(MUX32_OUT)
);
FF_D #(.P(P)) REG_FIXED (
.CLK(CLK),
.RST(RST),
.EN(EN_REG2),
.D(MUX32_OUT),
.Q(FIXED)
);
endmodule
|
module sensor_ctl(
input [0:0] clk,
input rst_32,
input [31:0] din_32,
input [0:0] wr_en_32,
input [0:0] rd_en_32,
output [31:0] dout_32,
output [0:0] full_32,
output [0:0] empty_32,
input [0:0] SPI_DI_a,
output [0:0] SPI_SS_a,
output [0:0] SPI_CK_a,
output [0:0] SPI_DO_a,
input [0:0] SPI_DI_g,
output [0:0] SPI_SS_g,
output [0:0] SPI_CK_g,
output [0:0] SPI_DO_g
);
parameter INIT_32 = 0,
READY_RCV_32 = 1,
RCV_DATA_32 = 2,
POSE_32 = 3,
READY_SND_32 = 4,
SND_DATA_32_ax = 5,
SND_DATA_32_ay = 6,
SND_DATA_32_az = 7,
SND_DATA_32_gx = 8,
SND_DATA_32_gy = 9,
SND_DATA_32_gz = 10;
// for input fifo
wire [31:0] rcv_data_32;
wire rcv_en_32;
wire data_empty_32;
// for output fifo
wire [31:0] snd_data_32;
wire snd_en_32;
wire data_full_32;
// state register
reg [3:0] state_32;
wire [15:0] accel_x;
wire [15:0] accel_y;
wire [15:0] accel_z;
wire [15:0] gyro_x;
wire [15:0] gyro_y;
wire [15:0] gyro_z;
reg [15:0] accel_x_reg;
reg [15:0] accel_y_reg;
reg [15:0] accel_z_reg;
reg [15:0] gyro_x_reg;
reg [15:0] gyro_y_reg;
reg [15:0] gyro_z_reg;
wire arm_rd_en_a;
wire arm_rd_en_g;
////fifo 32bit
fifo_32x512 input_fifo_32(
.clk(clk),
.srst(rst_32),
.din(din_32),
.wr_en(wr_en_32),
.full(full_32),
.dout(rcv_data_32),
.rd_en(rcv_en_32),
.empty(data_empty_32)
);
fifo_32x512 output_fifo_32(
.clk(clk),
.srst(rst_32),
.din(snd_data_32),
.wr_en(snd_en_32),
.full(data_full_32),
.dout(dout_32),
.rd_en(rd_en_32),
.empty(empty_32)
);
MPU_gyro_controller MPU_gyro_controller(
.clk(clk),
.reset(rst_32),
.gyro_x(gyro_x),
.gyro_y(gyro_y),
.gyro_z(gyro_z),
.SPI_SS_g(SPI_SS_g), //Sleve select
.SPI_CK_g(SPI_CK_g), //SCLK
.SPI_DO_g(SPI_DO_g), //Master out Sleve in
.SPI_DI_g(SPI_DI_g), //Master in Slave out
.arm_read_enable_g(arm_rd_en_g) //finish sensing accel_xyz
);
MPU_accel_controller MPU_accel_controller(
.clk(clk),
.reset(rst_32),
.accel_x(accel_x),
.accel_y(accel_y),
.accel_z(accel_z),
.SPI_SS_a(SPI_SS_a), //Sleve select
.SPI_CK_a(SPI_CK_a), //SCLK
.SPI_DO_a(SPI_DO_a), //Master out Sleve in
.SPI_DI_a(SPI_DI_a), //Master in Slave out
.arm_read_enable_a(arm_rd_en_a) //finish sensing accel_xyz
);
always @(posedge clk)begin
if(rst_32)
state_32 <= 0;
else
case (state_32)
INIT_32: state_32 <= READY_RCV_32;
READY_RCV_32: if(1) state_32 <= RCV_DATA_32;
RCV_DATA_32: state_32 <= POSE_32;
POSE_32: if(arm_rd_en_a || arm_rd_en_g) state_32 <= READY_SND_32;
// POSE_32: if(1) state_32 <= READY_SND_32;
READY_SND_32: if(data_full_32 == 0) state_32 <= SND_DATA_32_ax;
// READY_SND_32: if(1) state_32 <= SND_DATA_32_x;
SND_DATA_32_ax: state_32 <= SND_DATA_32_ay;
SND_DATA_32_ay: state_32 <= SND_DATA_32_az;
SND_DATA_32_az: state_32 <= SND_DATA_32_gx;
SND_DATA_32_gx: state_32 <= SND_DATA_32_gy;
SND_DATA_32_gy: state_32 <= SND_DATA_32_gz;
SND_DATA_32_gz: state_32 <= READY_RCV_32;
endcase
end
assign rcv_en_32 = (state_32 == RCV_DATA_32);
assign snd_en_32 = (state_32 > READY_SND_32);
assign snd_data_32 = (state_32 == SND_DATA_32_ax)? accel_x_reg:
(state_32 == SND_DATA_32_ay)? accel_y_reg:
(state_32 == SND_DATA_32_az)? accel_z_reg:
(state_32 == SND_DATA_32_gx)? gyro_x_reg:
(state_32 == SND_DATA_32_gy)? gyro_y_reg:
(state_32 == SND_DATA_32_gz)? gyro_z_reg:0;
always @(posedge clk) begin
if (rst_32) begin
accel_x_reg <= 0;
accel_y_reg <= 0;
accel_z_reg <= 0;
gyro_x_reg <= 0;
gyro_y_reg <= 0;
gyro_z_reg <= 0;
end
else
case (state_32)
INIT_32: begin
accel_x_reg <= 0;
accel_y_reg <= 0;
accel_z_reg <= 0;
gyro_x_reg <= 0;
gyro_y_reg <= 0;
gyro_z_reg <= 0;
end
READY_RCV_32: begin
accel_x_reg <= 0;
accel_y_reg <= 0;
accel_z_reg <= 0;
gyro_x_reg <= 0;
gyro_y_reg <= 0;
gyro_z_reg <= 0;
end
POSE_32: begin
accel_x_reg <= accel_x;
accel_y_reg <= accel_y;
accel_z_reg <= accel_z;
gyro_x_reg <= gyro_x;
gyro_y_reg <= gyro_y;
gyro_z_reg <= gyro_z;
end
endcase
end
endmodule
|
module sky130_fd_sc_hs__o211ai (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
|
module hps_sdram_p0_acv_hard_memphy (
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
afi_reset_n,
pll_locked,
oct_ctl_rs_value,
oct_ctl_rt_value,
afi_addr,
afi_ba,
afi_cke,
afi_cs_n,
afi_ras_n,
afi_we_n,
afi_cas_n,
afi_rst_n,
afi_odt,
afi_mem_clk_disable,
afi_dqs_burst,
afi_wdata_valid,
afi_wdata,
afi_dm,
afi_rdata,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata_valid,
afi_wlat,
afi_rlat,
afi_cal_success,
afi_cal_fail,
avl_read,
avl_write,
avl_address,
avl_writedata,
avl_waitrequest,
avl_readdata,
cfg_addlat,
cfg_bankaddrwidth,
cfg_caswrlat,
cfg_coladdrwidth,
cfg_csaddrwidth,
cfg_devicewidth,
cfg_dramconfig,
cfg_interfacewidth,
cfg_rowaddrwidth,
cfg_tcl,
cfg_tmrd,
cfg_trefi,
cfg_trfc,
cfg_twr,
io_intaddrdout,
io_intbadout,
io_intcasndout,
io_intckdout,
io_intckedout,
io_intckndout,
io_intcsndout,
io_intdmdout,
io_intdqdin,
io_intdqdout,
io_intdqoe,
io_intdqsbdout,
io_intdqsboe,
io_intdqsdout,
io_intdqslogicdqsena,
io_intdqslogicfiforeset,
io_intdqslogicincrdataen,
io_intdqslogicincwrptr,
io_intdqslogicoct,
io_intdqslogicrdatavalid,
io_intdqslogicreadlatency,
io_intdqsoe,
io_intodtdout,
io_intrasndout,
io_intresetndout,
io_intwendout,
io_intafirlat,
io_intafiwlat,
io_intaficalfail,
io_intaficalsuccess,
mem_a,
mem_ba,
mem_cs_n,
mem_cke,
mem_odt,
mem_we_n,
mem_ras_n,
mem_cas_n,
mem_reset_n,
mem_dq,
mem_dm,
mem_ck,
mem_ck_n,
mem_dqs,
mem_dqs_n,
reset_n_scc_clk,
reset_n_avl_clk,
scc_data,
scc_dqs_ena,
scc_dqs_io_ena,
scc_dq_ena,
scc_dm_ena,
scc_upd,
capture_strobe_tracking,
phy_clk,
ctl_clk,
phy_reset_n,
pll_afi_clk,
pll_afi_half_clk,
pll_addr_cmd_clk,
pll_mem_clk,
pll_mem_phy_clk,
pll_afi_phy_clk,
pll_avl_phy_clk,
pll_write_clk,
pll_write_clk_pre_phy_clk,
pll_dqs_ena_clk,
seq_clk,
pll_avl_clk,
pll_config_clk,
dll_clk,
dll_pll_locked,
dll_phy_delayctrl
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
parameter DEVICE_FAMILY = "";
parameter IS_HHP_HPS = "false";
// On-chip termination
parameter OCT_SERIES_TERM_CONTROL_WIDTH = "";
parameter OCT_PARALLEL_TERM_CONTROL_WIDTH = "";
// PHY-Memory Interface
// Memory device specific parameters, they are set according to the memory spec
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_IF_CS_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DQS_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
// PHY-Controller (AFI) Interface
// The AFI interface widths are derived from the memory interface widths based on full/half rate operations
// The calculations are done on higher level wrapper
// DLL Interface
// The DLL delay output control is always 6 bits for current existing devices
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter MR1_ODS = "";
parameter MR1_RTT = "";
parameter MR2_RTT_WR = "";
parameter TB_PROTOCOL = "";
parameter TB_MEM_CLK_FREQ = "";
parameter TB_RATE = "";
parameter TB_MEM_DQ_WIDTH = "";
parameter TB_MEM_DQS_WIDTH = "";
parameter TB_PLL_DLL_MASTER = "";
parameter FAST_SIM_MODEL = "";
parameter FAST_SIM_CALIBRATION = "";
// Width of the calibration status register used to control calibration skipping.
parameter CALIB_REG_WIDTH = "";
parameter AC_ROM_INIT_FILE_NAME = "";
parameter INST_ROM_INIT_FILE_NAME = "";
// The number of AFI Resets to generate
localparam NUM_AFI_RESET = 4;
// Addr/cmd clock phase
localparam ADC_PHASE_SETTING = 0;
localparam ADC_INVERT_PHASE = "true";
// END PARAMETER SECTION
// ********************************************************************************************************************************
// ********************************************************************************************************************************
// BEGIN PORT SECTION
// Reset Interface
input global_reset_n; // Resets (active-low) the whole system (all PHY logic + PLL)
input soft_reset_n; // Resets (active-low) PHY logic only, PLL is NOT reset
input pll_locked; // Indicates that PLL is locked
output ctl_reset_n; // Asynchronously asserted and synchronously de-asserted on ctl_clk domain
output ctl_reset_export_n; // Asynchronously asserted and synchronously de-asserted on ctl_clk domain
output afi_reset_n; // Asynchronously asserted and synchronously de-asserted on afi_clk domain
input [OCT_SERIES_TERM_CONTROL_WIDTH-1:0] oct_ctl_rs_value;
input [OCT_PARALLEL_TERM_CONTROL_WIDTH-1:0] oct_ctl_rt_value;
// PHY-Controller Interface, AFI 2.0
// Control Interface
input [19:0] afi_addr;
input [2:0] afi_ba;
input [1:0] afi_cke;
input [1:0] afi_cs_n;
input [0:0] afi_cas_n;
input [1:0] afi_odt;
input [0:0] afi_ras_n;
input [0:0] afi_we_n;
input [0:0] afi_rst_n;
input [0:0] afi_mem_clk_disable;
input [4:0] afi_dqs_burst;
output [3:0] afi_wlat;
output [4:0] afi_rlat;
// Write data interface
input [79:0] afi_wdata; // write data
input [4:0] afi_wdata_valid; // write data valid, used to maintain write latency required by protocol spec
input [9:0] afi_dm; // write data mask
// Read data interface
output [79:0] afi_rdata; // read data
input [4:0] afi_rdata_en; // read enable, used to maintain the read latency calibrated by PHY
input [4:0] afi_rdata_en_full; // read enable full burst, used to create DQS enable
output [0:0] afi_rdata_valid; // read data valid
// Status interface
output afi_cal_success; // calibration success
output afi_cal_fail; // calibration failure
// Avalon interface to the sequencer
input [15:0] avl_address; //MarkW TODO: the sequencer only uses 13 bits
input avl_read;
output [31:0] avl_readdata;
output avl_waitrequest;
input avl_write;
input [31:0] avl_writedata;
// Configuration interface to the memory controller
input [7:0] cfg_addlat;
input [7:0] cfg_bankaddrwidth;
input [7:0] cfg_caswrlat;
input [7:0] cfg_coladdrwidth;
input [7:0] cfg_csaddrwidth;
input [7:0] cfg_devicewidth;
input [23:0] cfg_dramconfig;
input [7:0] cfg_interfacewidth;
input [7:0] cfg_rowaddrwidth;
input [7:0] cfg_tcl;
input [7:0] cfg_tmrd;
input [15:0] cfg_trefi;
input [7:0] cfg_trfc;
input [7:0] cfg_twr;
// IO/bypass interface to the core (or soft controller)
input [63:0] io_intaddrdout;
input [11:0] io_intbadout;
input [3:0] io_intcasndout;
input [3:0] io_intckdout;
input [7:0] io_intckedout;
input [3:0] io_intckndout;
input [7:0] io_intcsndout;
input [19:0] io_intdmdout;
output [179:0] io_intdqdin;
input [179:0] io_intdqdout;
input [89:0] io_intdqoe;
input [19:0] io_intdqsbdout;
input [9:0] io_intdqsboe;
input [19:0] io_intdqsdout;
input [9:0] io_intdqslogicdqsena;
input [4:0] io_intdqslogicfiforeset;
input [9:0] io_intdqslogicincrdataen;
input [9:0] io_intdqslogicincwrptr;
input [9:0] io_intdqslogicoct;
output [4:0] io_intdqslogicrdatavalid;
input [24:0] io_intdqslogicreadlatency;
input [9:0] io_intdqsoe;
input [7:0] io_intodtdout;
input [3:0] io_intrasndout;
input [3:0] io_intresetndout;
input [3:0] io_intwendout;
output [4:0] io_intafirlat;
output [3:0] io_intafiwlat;
output io_intaficalfail;
output io_intaficalsuccess;
// PHY-Memory Interface
output [MEM_ADDRESS_WIDTH-1:0] mem_a;
output [MEM_BANK_WIDTH-1:0] mem_ba;
output [MEM_IF_CS_WIDTH-1:0] mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] mem_cke;
output [MEM_ODT_WIDTH-1:0] mem_odt;
output [MEM_CONTROL_WIDTH-1:0] mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] mem_cas_n;
output mem_reset_n;
inout [MEM_DQ_WIDTH-1:0] mem_dq;
output [MEM_DM_WIDTH-1:0] mem_dm;
output [MEM_CK_WIDTH-1:0] mem_ck;
output [MEM_CK_WIDTH-1:0] mem_ck_n;
inout [MEM_DQS_WIDTH-1:0] mem_dqs;
inout [MEM_DQS_WIDTH-1:0] mem_dqs_n;
output reset_n_scc_clk;
output reset_n_avl_clk;
// Scan chain configuration manager interface
input scc_data;
input [MEM_READ_DQS_WIDTH-1:0] scc_dqs_ena;
input [MEM_READ_DQS_WIDTH-1:0] scc_dqs_io_ena;
input [MEM_DQ_WIDTH-1:0] scc_dq_ena;
input [MEM_DM_WIDTH-1:0] scc_dm_ena;
input [0:0] scc_upd;
output [MEM_READ_DQS_WIDTH-1:0] capture_strobe_tracking;
output phy_clk;
output ctl_clk;
output phy_reset_n;
// PLL Interface
input pll_afi_clk; // clocks AFI interface logic
input pll_afi_half_clk; //
input pll_addr_cmd_clk; // clocks address/command DDIO
input pll_mem_clk; // output clock to memory
input pll_write_clk; // clocks write data DDIO
input pll_write_clk_pre_phy_clk;
input pll_dqs_ena_clk;
input seq_clk;
input pll_avl_clk;
input pll_config_clk;
input pll_mem_phy_clk;
input pll_afi_phy_clk;
input pll_avl_phy_clk;
// DLL Interface
output dll_clk;
output dll_pll_locked;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl; // dll output used to control the input DQS phase shift
// END PARAMETER SECTION
// ********************************************************************************************************************************
wire [179:0] ddio_phy_dqdin;
wire [4:0] ddio_phy_dqslogic_rdatavalid;
wire [63:0] phy_ddio_address;
wire [11:0] phy_ddio_bank;
wire [3:0] phy_ddio_cas_n;
wire [3:0] phy_ddio_ck;
wire [7:0] phy_ddio_cke;
wire [3:0] phy_ddio_ck_n;
wire [7:0] phy_ddio_cs_n;
wire [19:0] phy_ddio_dmdout;
wire [179:0] phy_ddio_dqdout;
wire [89:0] phy_ddio_dqoe;
wire [9:0] phy_ddio_dqsb_oe;
wire [9:0] phy_ddio_dqslogic_dqsena;
wire [4:0] phy_ddio_dqslogic_fiforeset;
wire [4:0] phy_ddio_dqslogic_aclr_pstamble;
wire [4:0] phy_ddio_dqslogic_aclr_fifoctrl;
wire [9:0] phy_ddio_dqslogic_incrdataen;
wire [9:0] phy_ddio_dqslogic_incwrptr;
wire [9:0] phy_ddio_dqslogic_oct;
wire [24:0] phy_ddio_dqslogic_readlatency;
wire [9:0] phy_ddio_dqs_oe;
wire [19:0] phy_ddio_dqs_dout;
wire [7:0] phy_ddio_odt;
wire [3:0] phy_ddio_ras_n;
wire [3:0] phy_ddio_reset_n;
wire [3:0] phy_ddio_we_n;
wire read_capture_clk;
wire [NUM_AFI_RESET-1:0] reset_n_afi_clk;
wire reset_n_addr_cmd_clk;
wire reset_n_seq_clk;
wire reset_n_scc_clk;
wire reset_n_avl_clk;
wire reset_n_resync_clk;
localparam SKIP_CALIBRATION_STEPS = 7'b1111111;
localparam CALIBRATION_STEPS = SKIP_CALIBRATION_STEPS;
localparam SKIP_MEM_INIT = 1'b1;
localparam SEQ_CALIB_INIT = {CALIBRATION_STEPS, SKIP_MEM_INIT};
generate
if (IS_HHP_HPS != "true") begin
reg [CALIB_REG_WIDTH-1:0] seq_calib_init_reg /* synthesis syn_noprune syn_preserve = 1 */;
// Initialization of the sequencer status register. This register
// is preserved in the netlist so that it can be forced during simulation
always @(posedge pll_afi_clk)
`ifdef SYNTH_FOR_SIM
`else
//synthesis translate_off
`endif
seq_calib_init_reg <= SEQ_CALIB_INIT;
`ifdef SYNTH_FOR_SIM
`else
//synthesis translate_on
//synthesis read_comments_as_HDL on
`endif
// seq_calib_init_reg <= {CALIB_REG_WIDTH{1'b0}};
`ifdef SYNTH_FOR_SIM
`else
// synthesis read_comments_as_HDL off
`endif
end
endgenerate
// ********************************************************************************************************************************
// The reset scheme used in the UNIPHY is asynchronous assert and synchronous de-assert
// The reset block has 2 main functionalities:
// 1. Keep all the PHY logic in reset state until after the PLL is locked
// 2. Synchronize the reset to each clock domain
// ********************************************************************************************************************************
generate
if (IS_HHP_HPS != "true") begin
hps_sdram_p0_reset ureset(
.pll_afi_clk (pll_afi_clk),
.pll_addr_cmd_clk (pll_addr_cmd_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.seq_clk (seq_clk),
.pll_avl_clk (pll_avl_clk),
.scc_clk (pll_config_clk),
.reset_n_scc_clk (reset_n_scc_clk),
.reset_n_avl_clk (reset_n_avl_clk),
.read_capture_clk (read_capture_clk),
.pll_locked (pll_locked),
.global_reset_n (global_reset_n),
.soft_reset_n (soft_reset_n),
.ctl_reset_export_n (ctl_reset_export_n),
.reset_n_afi_clk (reset_n_afi_clk),
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_seq_clk (reset_n_seq_clk),
.reset_n_resync_clk (reset_n_resync_clk)
);
defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
end else begin
// synthesis translate_off
hps_sdram_p0_reset ureset(
.pll_afi_clk (pll_afi_clk),
.pll_addr_cmd_clk (pll_addr_cmd_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.seq_clk (seq_clk),
.pll_avl_clk (pll_avl_clk),
.scc_clk (pll_config_clk),
.reset_n_scc_clk (reset_n_scc_clk),
.reset_n_avl_clk (reset_n_avl_clk),
.read_capture_clk (read_capture_clk),
.pll_locked (pll_locked),
.global_reset_n (global_reset_n),
.soft_reset_n (soft_reset_n),
.ctl_reset_export_n (ctl_reset_export_n),
.reset_n_afi_clk (reset_n_afi_clk),
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_seq_clk (reset_n_seq_clk),
.reset_n_resync_clk (reset_n_resync_clk)
);
defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
// synthesis translate_on
// synthesis read_comments_as_HDL on
// assign reset_n_afi_clk = {NUM_AFI_RESET{global_reset_n}};
// assign reset_n_addr_cmd_clk = global_reset_n;
// assign reset_n_avl_clk = global_reset_n;
// assign reset_n_scc_clk = global_reset_n;
// synthesis read_comments_as_HDL off
end
endgenerate
assign phy_clk = seq_clk;
assign phy_reset_n = reset_n_seq_clk;
assign dll_clk = pll_write_clk_pre_phy_clk;
assign dll_pll_locked = pll_locked;
// PHY clock and LDC
wire afi_clk;
wire avl_clk;
wire adc_clk;
wire adc_clk_cps;
hps_sdram_p0_acv_ldc # (
.DLL_DELAY_CTRL_WIDTH (DLL_DELAY_CTRL_WIDTH),
.ADC_PHASE_SETTING (ADC_PHASE_SETTING),
.ADC_INVERT_PHASE (ADC_INVERT_PHASE),
.IS_HHP_HPS (IS_HHP_HPS)
) memphy_ldc (
.pll_hr_clk (pll_avl_phy_clk),
.pll_dq_clk (pll_write_clk),
.pll_dqs_clk (pll_mem_phy_clk),
.dll_phy_delayctrl (dll_phy_delayctrl),
.afi_clk (afi_clk),
.avl_clk (avl_clk),
.adc_clk (adc_clk),
.adc_clk_cps (adc_clk_cps)
);
assign ctl_clk = afi_clk;
assign afi_reset_n = reset_n_afi_clk;
// ********************************************************************************************************************************
// This is the hard PHY instance
// ********************************************************************************************************************************
cyclonev_mem_phy hphy_inst (
.pllaficlk (afi_clk),
.pllavlclk (avl_clk),
.plllocked (pll_locked),
.plladdrcmdclk (adc_clk),
.globalresetn (global_reset_n),
.softresetn (soft_reset_n),
.phyresetn (phy_reset_n),
.ctlresetn (ctl_reset_n),
.iointaddrdout (io_intaddrdout),
.iointbadout (io_intbadout),
.iointcasndout (io_intcasndout),
.iointckdout (io_intckdout),
.iointckedout (io_intckedout),
.iointckndout (io_intckndout),
.iointcsndout (io_intcsndout),
.iointdmdout (io_intdmdout),
.iointdqdin (io_intdqdin),
.iointdqdout (io_intdqdout),
.iointdqoe (io_intdqoe),
.iointdqsbdout (io_intdqsbdout),
.iointdqsboe (io_intdqsboe),
.iointdqsdout (io_intdqsdout),
.iointdqslogicdqsena (io_intdqslogicdqsena),
.iointdqslogicfiforeset (io_intdqslogicfiforeset),
.iointdqslogicincrdataen (io_intdqslogicincrdataen),
.iointdqslogicincwrptr (io_intdqslogicincwrptr),
.iointdqslogicoct (io_intdqslogicoct),
.iointdqslogicrdatavalid (io_intdqslogicrdatavalid),
.iointdqslogicreadlatency (io_intdqslogicreadlatency),
.iointdqsoe (io_intdqsoe),
.iointodtdout (io_intodtdout),
.iointrasndout (io_intrasndout),
.iointresetndout (io_intresetndout),
.iointwendout (io_intwendout),
.iointafirlat (io_intafirlat),
.iointafiwlat (io_intafiwlat),
.iointaficalfail (io_intaficalfail),
.iointaficalsuccess (io_intaficalsuccess),
.ddiophydqdin (ddio_phy_dqdin),
.ddiophydqslogicrdatavalid (ddio_phy_dqslogic_rdatavalid),
.phyddioaddrdout (phy_ddio_address),
.phyddiobadout (phy_ddio_bank),
.phyddiocasndout (phy_ddio_cas_n),
.phyddiockdout (phy_ddio_ck),
.phyddiockedout (phy_ddio_cke),
.phyddiockndout (),
.phyddiocsndout (phy_ddio_cs_n),
.phyddiodmdout (phy_ddio_dmdout),
.phyddiodqdout (phy_ddio_dqdout),
.phyddiodqoe (phy_ddio_dqoe),
.phyddiodqsbdout (),
.phyddiodqsboe (phy_ddio_dqsb_oe),
.phyddiodqslogicdqsena (phy_ddio_dqslogic_dqsena),
.phyddiodqslogicfiforeset (phy_ddio_dqslogic_fiforeset),
.phyddiodqslogicaclrpstamble (phy_ddio_dqslogic_aclr_pstamble),
.phyddiodqslogicaclrfifoctrl (phy_ddio_dqslogic_aclr_fifoctrl),
.phyddiodqslogicincrdataen (phy_ddio_dqslogic_incrdataen),
.phyddiodqslogicincwrptr (phy_ddio_dqslogic_incwrptr),
.phyddiodqslogicoct (phy_ddio_dqslogic_oct),
.phyddiodqslogicreadlatency (phy_ddio_dqslogic_readlatency),
.phyddiodqsoe (phy_ddio_dqs_oe),
.phyddiodqsdout (phy_ddio_dqs_dout),
.phyddioodtdout (phy_ddio_odt),
.phyddiorasndout (phy_ddio_ras_n),
.phyddioresetndout (phy_ddio_reset_n),
.phyddiowendout (phy_ddio_we_n),
.afiaddr (afi_addr),
.afiba (afi_ba),
.aficalfail (afi_cal_fail),
.aficalsuccess (afi_cal_success),
.aficasn (afi_cas_n),
.aficke (afi_cke),
.aficsn (afi_cs_n),
.afidm (afi_dm),
.afidqsburst (afi_dqs_burst),
.afimemclkdisable (afi_mem_clk_disable),
.afiodt (afi_odt),
.afirasn (afi_ras_n),
.afirdata (afi_rdata),
.afirdataen (afi_rdata_en),
.afirdataenfull (afi_rdata_en_full),
.afirdatavalid (afi_rdata_valid),
.afirlat (afi_rlat),
.afirstn (afi_rst_n),
.afiwdata (afi_wdata),
.afiwdatavalid (afi_wdata_valid),
.afiwen (afi_we_n),
.afiwlat (afi_wlat),
.avladdress (avl_address),
.avlread (avl_read),
.avlreaddata (avl_readdata),
.avlresetn (reset_n_avl_clk),
.avlwaitrequest (avl_waitrequest),
.avlwrite (avl_write),
.avlwritedata (avl_writedata),
.cfgaddlat (cfg_addlat),
.cfgbankaddrwidth (cfg_bankaddrwidth),
.cfgcaswrlat (cfg_caswrlat),
.cfgcoladdrwidth (cfg_coladdrwidth),
.cfgcsaddrwidth (cfg_csaddrwidth),
.cfgdevicewidth (cfg_devicewidth),
.cfgdramconfig (cfg_dramconfig),
.cfginterfacewidth (cfg_interfacewidth),
.cfgrowaddrwidth (cfg_rowaddrwidth),
.cfgtcl (cfg_tcl),
.cfgtmrd (cfg_tmrd),
.cfgtrefi (cfg_trefi),
.cfgtrfc (cfg_trfc),
.cfgtwr (cfg_twr),
.scanen ()
);
defparam hphy_inst.hphy_ac_ddr_disable = "true";
defparam hphy_inst.hphy_datapath_delay = "one_cycle";
defparam hphy_inst.hphy_datapath_ac_delay = "one_and_half_cycles";
defparam hphy_inst.hphy_reset_delay_en = "false";
defparam hphy_inst.m_hphy_ac_rom_init_file = AC_ROM_INIT_FILE_NAME;
defparam hphy_inst.m_hphy_inst_rom_init_file = INST_ROM_INIT_FILE_NAME;
defparam hphy_inst.hphy_wrap_back_en = "false";
defparam hphy_inst.hphy_atpg_en = "false";
defparam hphy_inst.hphy_use_hphy = "true";
defparam hphy_inst.hphy_csr_pipelineglobalenable = "true";
defparam hphy_inst.hphy_hhp_hps = IS_HHP_HPS;
// ********************************************************************************************************************************
// The I/O block is responsible for instantiating all the built-in I/O logic in the FPGA
// ********************************************************************************************************************************
hps_sdram_p0_acv_hard_io_pads #(
.DEVICE_FAMILY(DEVICE_FAMILY),
.FAST_SIM_MODEL(FAST_SIM_MODEL),
.OCT_SERIES_TERM_CONTROL_WIDTH(OCT_SERIES_TERM_CONTROL_WIDTH),
.OCT_PARALLEL_TERM_CONTROL_WIDTH(OCT_PARALLEL_TERM_CONTROL_WIDTH),
.MEM_ADDRESS_WIDTH(MEM_ADDRESS_WIDTH),
.MEM_BANK_WIDTH(MEM_BANK_WIDTH),
.MEM_CHIP_SELECT_WIDTH(MEM_IF_CS_WIDTH),
.MEM_CLK_EN_WIDTH(MEM_CLK_EN_WIDTH),
.MEM_CK_WIDTH(MEM_CK_WIDTH),
.MEM_ODT_WIDTH(MEM_ODT_WIDTH),
.MEM_DQS_WIDTH(MEM_DQS_WIDTH),
.MEM_DM_WIDTH(MEM_DM_WIDTH),
.MEM_CONTROL_WIDTH(MEM_CONTROL_WIDTH),
.MEM_DQ_WIDTH(MEM_DQ_WIDTH),
.MEM_READ_DQS_WIDTH(MEM_READ_DQS_WIDTH),
.MEM_WRITE_DQS_WIDTH(MEM_WRITE_DQS_WIDTH),
.DLL_DELAY_CTRL_WIDTH(DLL_DELAY_CTRL_WIDTH),
.ADC_PHASE_SETTING(ADC_PHASE_SETTING),
.ADC_INVERT_PHASE(ADC_INVERT_PHASE),
.IS_HHP_HPS(IS_HHP_HPS)
) uio_pads (
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_afi_clk (reset_n_afi_clk[1]),
.oct_ctl_rs_value (oct_ctl_rs_value),
.oct_ctl_rt_value (oct_ctl_rt_value),
.phy_ddio_address (phy_ddio_address),
.phy_ddio_bank (phy_ddio_bank),
.phy_ddio_cs_n (phy_ddio_cs_n),
.phy_ddio_cke (phy_ddio_cke),
.phy_ddio_odt (phy_ddio_odt),
.phy_ddio_we_n (phy_ddio_we_n),
.phy_ddio_ras_n (phy_ddio_ras_n),
.phy_ddio_cas_n (phy_ddio_cas_n),
.phy_ddio_ck (phy_ddio_ck),
.phy_ddio_reset_n (phy_ddio_reset_n),
.phy_mem_address (mem_a),
.phy_mem_bank (mem_ba),
.phy_mem_cs_n (mem_cs_n),
.phy_mem_cke (mem_cke),
.phy_mem_odt (mem_odt),
.phy_mem_we_n (mem_we_n),
.phy_mem_ras_n (mem_ras_n),
.phy_mem_cas_n (mem_cas_n),
.phy_mem_reset_n (mem_reset_n),
.pll_afi_clk (pll_afi_clk),
.pll_mem_clk (pll_mem_clk),
.pll_afi_phy_clk (pll_afi_phy_clk),
.pll_avl_phy_clk (pll_avl_phy_clk),
.pll_avl_clk (pll_avl_clk),
.avl_clk (avl_clk),
.pll_mem_phy_clk (pll_mem_phy_clk),
.pll_write_clk (pll_write_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.pll_addr_cmd_clk (adc_clk_cps),
.phy_mem_dq (mem_dq),
.phy_mem_dm (mem_dm),
.phy_mem_ck (mem_ck),
.phy_mem_ck_n (mem_ck_n),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqs_n),
.dll_phy_delayctrl (dll_phy_delayctrl),
.scc_clk (pll_config_clk),
.scc_data (scc_data),
.scc_dqs_ena (scc_dqs_ena),
.scc_dqs_io_ena (scc_dqs_io_ena),
.scc_dq_ena (scc_dq_ena),
.scc_dm_ena (scc_dm_ena),
.scc_upd (scc_upd[0]),
.phy_ddio_dmdout (phy_ddio_dmdout),
.phy_ddio_dqdout (phy_ddio_dqdout),
.phy_ddio_dqs_oe (phy_ddio_dqs_oe),
.phy_ddio_dqsdout (phy_ddio_dqs_dout),
.phy_ddio_dqsb_oe (phy_ddio_dqsb_oe),
.phy_ddio_dqslogic_oct (phy_ddio_dqslogic_oct),
.phy_ddio_dqslogic_fiforeset (phy_ddio_dqslogic_fiforeset),
.phy_ddio_dqslogic_aclr_pstamble (phy_ddio_dqslogic_aclr_pstamble),
.phy_ddio_dqslogic_aclr_fifoctrl (phy_ddio_dqslogic_aclr_fifoctrl),
.phy_ddio_dqslogic_incwrptr (phy_ddio_dqslogic_incwrptr),
.phy_ddio_dqslogic_readlatency (phy_ddio_dqslogic_readlatency),
.ddio_phy_dqslogic_rdatavalid (ddio_phy_dqslogic_rdatavalid),
.ddio_phy_dqdin (ddio_phy_dqdin),
.phy_ddio_dqslogic_incrdataen (phy_ddio_dqslogic_incrdataen),
.phy_ddio_dqslogic_dqsena (phy_ddio_dqslogic_dqsena),
.phy_ddio_dqoe (phy_ddio_dqoe),
.capture_strobe_tracking (capture_strobe_tracking)
);
generate
if (IS_HHP_HPS != "true") begin
reg afi_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_afi_clk)
afi_clk_reg <= ~afi_clk_reg;
reg afi_half_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_afi_half_clk)
afi_half_clk_reg <= ~afi_half_clk_reg;
reg avl_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_avl_clk)
avl_clk_reg <= ~avl_clk_reg;
reg config_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_config_clk)
config_clk_reg <= ~config_clk_reg;
end
endgenerate
// Calculate the ceiling of log_2 of the input value
function integer ceil_log2;
input integer value;
begin
value = value - 1;
for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1)
value = value >> 1;
end
endfunction
endmodule
|
module bsg_mem_1r1w_sync #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter harden_p=0
, parameter disable_collision_warning_p=0
, parameter enable_clock_gating_p=0
)
(input clk_i
, input reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [`BSG_SAFE_MINUS(width_p, 1):0] w_data_i
// currently unused
, input r_v_i
, input [addr_width_lp-1:0] r_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r_data_o
);
wire clk_lo;
if (enable_clock_gating_p)
begin
bsg_clkgate_optional icg
(.clk_i( clk_i )
,.en_i( w_v_i | r_v_i )
,.bypass_i( 1'b0 )
,.gated_clock_o( clk_lo )
);
end
else
begin
assign clk_lo = clk_i;
end
bsg_mem_1r1w_sync_synth
#(.width_p(width_p)
,.els_p(els_p)
,.read_write_same_addr_p(read_write_same_addr_p)
,.harden_p(harden_p)
) synth
(.clk_i( clk_lo )
,.reset_i
,.w_v_i
,.w_addr_i
,.w_data_i
,.r_v_i
,.r_addr_i
,.r_data_o
);
//synopsys translate_off
initial
begin
// we warn if els_p >= 16 because it is a good candidate for hardening
// and we warn for width_p >= 128 because this starts to add up to some real memory
if ((els_p >= 16) || (width_p >= 128) || (width_p*els_p > 256))
$display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d, harden_p=%d (%m)",width_p,els_p,read_write_same_addr_p,harden_p);
if (disable_collision_warning_p)
$display("## %L: disable_collision_warning_p is set; you should not have this on unless you have broken code. fix it!\n");
end
always_ff @(posedge clk_lo)
if (w_v_i)
begin
assert ((reset_i === 'X) || (reset_i === 1'b1) || (w_addr_i < els_p))
else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
assert ((reset_i === 'X) || (reset_i === 1'b1) || ~(r_addr_i == w_addr_i && w_v_i && r_v_i && !read_write_same_addr_p && !disable_collision_warning_p))
else
begin
$error("X'ing matched read address %x (%m)",r_addr_i);
end
end
//synopsys translate_on
endmodule
|
module hps_design (
input wire clk_clk, // clk.clk
output wire [14:0] hps_ddr_mem_a, // hps_ddr.mem_a
output wire [2:0] hps_ddr_mem_ba, // .mem_ba
output wire hps_ddr_mem_ck, // .mem_ck
output wire hps_ddr_mem_ck_n, // .mem_ck_n
output wire hps_ddr_mem_cke, // .mem_cke
output wire hps_ddr_mem_cs_n, // .mem_cs_n
output wire hps_ddr_mem_ras_n, // .mem_ras_n
output wire hps_ddr_mem_cas_n, // .mem_cas_n
output wire hps_ddr_mem_we_n, // .mem_we_n
output wire hps_ddr_mem_reset_n, // .mem_reset_n
inout wire [31:0] hps_ddr_mem_dq, // .mem_dq
inout wire [3:0] hps_ddr_mem_dqs, // .mem_dqs
inout wire [3:0] hps_ddr_mem_dqs_n, // .mem_dqs_n
output wire hps_ddr_mem_odt, // .mem_odt
output wire [3:0] hps_ddr_mem_dm, // .mem_dm
input wire hps_ddr_oct_rzqin, // .oct_rzqin
inout wire hps_io_hps_io_gpio_inst_GPIO09, // hps_io.hps_io_gpio_inst_GPIO09
inout wire hps_io_hps_io_gpio_inst_GPIO35, // .hps_io_gpio_inst_GPIO35
inout wire hps_io_hps_io_gpio_inst_GPIO40, // .hps_io_gpio_inst_GPIO40
inout wire hps_io_hps_io_gpio_inst_GPIO48, // .hps_io_gpio_inst_GPIO48
inout wire hps_io_hps_io_gpio_inst_GPIO53, // .hps_io_gpio_inst_GPIO53
inout wire hps_io_hps_io_gpio_inst_GPIO54, // .hps_io_gpio_inst_GPIO54
inout wire hps_io_hps_io_gpio_inst_GPIO61, // .hps_io_gpio_inst_GPIO61
output wire ledr_export, // ledr.export
output wire pll_0_sdram_clk, // pll_0_sdram.clk
input wire reset_reset_n // reset.reset_n
);
wire pll_0_outclk0_clk; // pll_0:outclk_0 -> [mm_interconnect_0:pll_0_outclk0_clk, pio_0:clk, rst_controller:clk, rst_controller_001:clk, smp_hps:h2f_lw_axi_clk]
wire [1:0] smp_hps_h2f_lw_axi_master_awburst; // smp_hps:h2f_lw_AWBURST -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_awburst
wire [3:0] smp_hps_h2f_lw_axi_master_arlen; // smp_hps:h2f_lw_ARLEN -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_arlen
wire [3:0] smp_hps_h2f_lw_axi_master_wstrb; // smp_hps:h2f_lw_WSTRB -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_wstrb
wire smp_hps_h2f_lw_axi_master_wready; // mm_interconnect_0:smp_hps_h2f_lw_axi_master_wready -> smp_hps:h2f_lw_WREADY
wire [11:0] smp_hps_h2f_lw_axi_master_rid; // mm_interconnect_0:smp_hps_h2f_lw_axi_master_rid -> smp_hps:h2f_lw_RID
wire smp_hps_h2f_lw_axi_master_rready; // smp_hps:h2f_lw_RREADY -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_rready
wire [3:0] smp_hps_h2f_lw_axi_master_awlen; // smp_hps:h2f_lw_AWLEN -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_awlen
wire [11:0] smp_hps_h2f_lw_axi_master_wid; // smp_hps:h2f_lw_WID -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_wid
wire [3:0] smp_hps_h2f_lw_axi_master_arcache; // smp_hps:h2f_lw_ARCACHE -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_arcache
wire smp_hps_h2f_lw_axi_master_wvalid; // smp_hps:h2f_lw_WVALID -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_wvalid
wire [20:0] smp_hps_h2f_lw_axi_master_araddr; // smp_hps:h2f_lw_ARADDR -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_araddr
wire [2:0] smp_hps_h2f_lw_axi_master_arprot; // smp_hps:h2f_lw_ARPROT -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_arprot
wire [2:0] smp_hps_h2f_lw_axi_master_awprot; // smp_hps:h2f_lw_AWPROT -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_awprot
wire [31:0] smp_hps_h2f_lw_axi_master_wdata; // smp_hps:h2f_lw_WDATA -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_wdata
wire smp_hps_h2f_lw_axi_master_arvalid; // smp_hps:h2f_lw_ARVALID -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_arvalid
wire [3:0] smp_hps_h2f_lw_axi_master_awcache; // smp_hps:h2f_lw_AWCACHE -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_awcache
wire [11:0] smp_hps_h2f_lw_axi_master_arid; // smp_hps:h2f_lw_ARID -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_arid
wire [1:0] smp_hps_h2f_lw_axi_master_arlock; // smp_hps:h2f_lw_ARLOCK -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_arlock
wire [1:0] smp_hps_h2f_lw_axi_master_awlock; // smp_hps:h2f_lw_AWLOCK -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_awlock
wire [20:0] smp_hps_h2f_lw_axi_master_awaddr; // smp_hps:h2f_lw_AWADDR -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_awaddr
wire [1:0] smp_hps_h2f_lw_axi_master_bresp; // mm_interconnect_0:smp_hps_h2f_lw_axi_master_bresp -> smp_hps:h2f_lw_BRESP
wire smp_hps_h2f_lw_axi_master_arready; // mm_interconnect_0:smp_hps_h2f_lw_axi_master_arready -> smp_hps:h2f_lw_ARREADY
wire [31:0] smp_hps_h2f_lw_axi_master_rdata; // mm_interconnect_0:smp_hps_h2f_lw_axi_master_rdata -> smp_hps:h2f_lw_RDATA
wire smp_hps_h2f_lw_axi_master_awready; // mm_interconnect_0:smp_hps_h2f_lw_axi_master_awready -> smp_hps:h2f_lw_AWREADY
wire [1:0] smp_hps_h2f_lw_axi_master_arburst; // smp_hps:h2f_lw_ARBURST -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_arburst
wire [2:0] smp_hps_h2f_lw_axi_master_arsize; // smp_hps:h2f_lw_ARSIZE -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_arsize
wire smp_hps_h2f_lw_axi_master_bready; // smp_hps:h2f_lw_BREADY -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_bready
wire smp_hps_h2f_lw_axi_master_rlast; // mm_interconnect_0:smp_hps_h2f_lw_axi_master_rlast -> smp_hps:h2f_lw_RLAST
wire smp_hps_h2f_lw_axi_master_wlast; // smp_hps:h2f_lw_WLAST -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_wlast
wire [1:0] smp_hps_h2f_lw_axi_master_rresp; // mm_interconnect_0:smp_hps_h2f_lw_axi_master_rresp -> smp_hps:h2f_lw_RRESP
wire [11:0] smp_hps_h2f_lw_axi_master_awid; // smp_hps:h2f_lw_AWID -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_awid
wire [11:0] smp_hps_h2f_lw_axi_master_bid; // mm_interconnect_0:smp_hps_h2f_lw_axi_master_bid -> smp_hps:h2f_lw_BID
wire smp_hps_h2f_lw_axi_master_bvalid; // mm_interconnect_0:smp_hps_h2f_lw_axi_master_bvalid -> smp_hps:h2f_lw_BVALID
wire [2:0] smp_hps_h2f_lw_axi_master_awsize; // smp_hps:h2f_lw_AWSIZE -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_awsize
wire smp_hps_h2f_lw_axi_master_awvalid; // smp_hps:h2f_lw_AWVALID -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_awvalid
wire smp_hps_h2f_lw_axi_master_rvalid; // mm_interconnect_0:smp_hps_h2f_lw_axi_master_rvalid -> smp_hps:h2f_lw_RVALID
wire mm_interconnect_0_pio_0_s1_chipselect; // mm_interconnect_0:pio_0_s1_chipselect -> pio_0:chipselect
wire [31:0] mm_interconnect_0_pio_0_s1_readdata; // pio_0:readdata -> mm_interconnect_0:pio_0_s1_readdata
wire [1:0] mm_interconnect_0_pio_0_s1_address; // mm_interconnect_0:pio_0_s1_address -> pio_0:address
wire mm_interconnect_0_pio_0_s1_write; // mm_interconnect_0:pio_0_s1_write -> pio_0:write_n
wire [31:0] mm_interconnect_0_pio_0_s1_writedata; // mm_interconnect_0:pio_0_s1_writedata -> pio_0:writedata
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [mm_interconnect_0:pio_0_reset_reset_bridge_in_reset_reset, pio_0:reset_n]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> mm_interconnect_0:smp_hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset
wire smp_hps_h2f_reset_reset; // smp_hps:h2f_rst_n -> rst_controller_001:reset_in0
hps_design_pio_0 pio_0 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_pio_0_s1_address), // s1.address
.write_n (~mm_interconnect_0_pio_0_s1_write), // .write_n
.writedata (mm_interconnect_0_pio_0_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_pio_0_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_pio_0_s1_readdata), // .readdata
.out_port (ledr_export) // external_connection.export
);
hps_design_pll_0 pll_0 (
.refclk (clk_clk), // refclk.clk
.rst (~reset_reset_n), // reset.reset
.outclk_0 (pll_0_outclk0_clk), // outclk0.clk
.outclk_1 (), // outclk1.clk
.outclk_2 (pll_0_sdram_clk), // outclk2.clk
.locked () // (terminated)
);
hps_design_smp_hps #(
.F2S_Width (0),
.S2F_Width (0)
) smp_hps (
.mem_a (hps_ddr_mem_a), // memory.mem_a
.mem_ba (hps_ddr_mem_ba), // .mem_ba
.mem_ck (hps_ddr_mem_ck), // .mem_ck
.mem_ck_n (hps_ddr_mem_ck_n), // .mem_ck_n
.mem_cke (hps_ddr_mem_cke), // .mem_cke
.mem_cs_n (hps_ddr_mem_cs_n), // .mem_cs_n
.mem_ras_n (hps_ddr_mem_ras_n), // .mem_ras_n
.mem_cas_n (hps_ddr_mem_cas_n), // .mem_cas_n
.mem_we_n (hps_ddr_mem_we_n), // .mem_we_n
.mem_reset_n (hps_ddr_mem_reset_n), // .mem_reset_n
.mem_dq (hps_ddr_mem_dq), // .mem_dq
.mem_dqs (hps_ddr_mem_dqs), // .mem_dqs
.mem_dqs_n (hps_ddr_mem_dqs_n), // .mem_dqs_n
.mem_odt (hps_ddr_mem_odt), // .mem_odt
.mem_dm (hps_ddr_mem_dm), // .mem_dm
.oct_rzqin (hps_ddr_oct_rzqin), // .oct_rzqin
.hps_io_gpio_inst_GPIO09 (hps_io_hps_io_gpio_inst_GPIO09), // hps_io.hps_io_gpio_inst_GPIO09
.hps_io_gpio_inst_GPIO35 (hps_io_hps_io_gpio_inst_GPIO35), // .hps_io_gpio_inst_GPIO35
.hps_io_gpio_inst_GPIO40 (hps_io_hps_io_gpio_inst_GPIO40), // .hps_io_gpio_inst_GPIO40
.hps_io_gpio_inst_GPIO48 (hps_io_hps_io_gpio_inst_GPIO48), // .hps_io_gpio_inst_GPIO48
.hps_io_gpio_inst_GPIO53 (hps_io_hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.hps_io_gpio_inst_GPIO54 (hps_io_hps_io_gpio_inst_GPIO54), // .hps_io_gpio_inst_GPIO54
.hps_io_gpio_inst_GPIO61 (hps_io_hps_io_gpio_inst_GPIO61), // .hps_io_gpio_inst_GPIO61
.h2f_rst_n (smp_hps_h2f_reset_reset), // h2f_reset.reset_n
.h2f_lw_axi_clk (pll_0_outclk0_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (smp_hps_h2f_lw_axi_master_awid), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (smp_hps_h2f_lw_axi_master_awaddr), // .awaddr
.h2f_lw_AWLEN (smp_hps_h2f_lw_axi_master_awlen), // .awlen
.h2f_lw_AWSIZE (smp_hps_h2f_lw_axi_master_awsize), // .awsize
.h2f_lw_AWBURST (smp_hps_h2f_lw_axi_master_awburst), // .awburst
.h2f_lw_AWLOCK (smp_hps_h2f_lw_axi_master_awlock), // .awlock
.h2f_lw_AWCACHE (smp_hps_h2f_lw_axi_master_awcache), // .awcache
.h2f_lw_AWPROT (smp_hps_h2f_lw_axi_master_awprot), // .awprot
.h2f_lw_AWVALID (smp_hps_h2f_lw_axi_master_awvalid), // .awvalid
.h2f_lw_AWREADY (smp_hps_h2f_lw_axi_master_awready), // .awready
.h2f_lw_WID (smp_hps_h2f_lw_axi_master_wid), // .wid
.h2f_lw_WDATA (smp_hps_h2f_lw_axi_master_wdata), // .wdata
.h2f_lw_WSTRB (smp_hps_h2f_lw_axi_master_wstrb), // .wstrb
.h2f_lw_WLAST (smp_hps_h2f_lw_axi_master_wlast), // .wlast
.h2f_lw_WVALID (smp_hps_h2f_lw_axi_master_wvalid), // .wvalid
.h2f_lw_WREADY (smp_hps_h2f_lw_axi_master_wready), // .wready
.h2f_lw_BID (smp_hps_h2f_lw_axi_master_bid), // .bid
.h2f_lw_BRESP (smp_hps_h2f_lw_axi_master_bresp), // .bresp
.h2f_lw_BVALID (smp_hps_h2f_lw_axi_master_bvalid), // .bvalid
.h2f_lw_BREADY (smp_hps_h2f_lw_axi_master_bready), // .bready
.h2f_lw_ARID (smp_hps_h2f_lw_axi_master_arid), // .arid
.h2f_lw_ARADDR (smp_hps_h2f_lw_axi_master_araddr), // .araddr
.h2f_lw_ARLEN (smp_hps_h2f_lw_axi_master_arlen), // .arlen
.h2f_lw_ARSIZE (smp_hps_h2f_lw_axi_master_arsize), // .arsize
.h2f_lw_ARBURST (smp_hps_h2f_lw_axi_master_arburst), // .arburst
.h2f_lw_ARLOCK (smp_hps_h2f_lw_axi_master_arlock), // .arlock
.h2f_lw_ARCACHE (smp_hps_h2f_lw_axi_master_arcache), // .arcache
.h2f_lw_ARPROT (smp_hps_h2f_lw_axi_master_arprot), // .arprot
.h2f_lw_ARVALID (smp_hps_h2f_lw_axi_master_arvalid), // .arvalid
.h2f_lw_ARREADY (smp_hps_h2f_lw_axi_master_arready), // .arready
.h2f_lw_RID (smp_hps_h2f_lw_axi_master_rid), // .rid
.h2f_lw_RDATA (smp_hps_h2f_lw_axi_master_rdata), // .rdata
.h2f_lw_RRESP (smp_hps_h2f_lw_axi_master_rresp), // .rresp
.h2f_lw_RLAST (smp_hps_h2f_lw_axi_master_rlast), // .rlast
.h2f_lw_RVALID (smp_hps_h2f_lw_axi_master_rvalid), // .rvalid
.h2f_lw_RREADY (smp_hps_h2f_lw_axi_master_rready) // .rready
);
hps_design_mm_interconnect_0 mm_interconnect_0 (
.smp_hps_h2f_lw_axi_master_awid (smp_hps_h2f_lw_axi_master_awid), // smp_hps_h2f_lw_axi_master.awid
.smp_hps_h2f_lw_axi_master_awaddr (smp_hps_h2f_lw_axi_master_awaddr), // .awaddr
.smp_hps_h2f_lw_axi_master_awlen (smp_hps_h2f_lw_axi_master_awlen), // .awlen
.smp_hps_h2f_lw_axi_master_awsize (smp_hps_h2f_lw_axi_master_awsize), // .awsize
.smp_hps_h2f_lw_axi_master_awburst (smp_hps_h2f_lw_axi_master_awburst), // .awburst
.smp_hps_h2f_lw_axi_master_awlock (smp_hps_h2f_lw_axi_master_awlock), // .awlock
.smp_hps_h2f_lw_axi_master_awcache (smp_hps_h2f_lw_axi_master_awcache), // .awcache
.smp_hps_h2f_lw_axi_master_awprot (smp_hps_h2f_lw_axi_master_awprot), // .awprot
.smp_hps_h2f_lw_axi_master_awvalid (smp_hps_h2f_lw_axi_master_awvalid), // .awvalid
.smp_hps_h2f_lw_axi_master_awready (smp_hps_h2f_lw_axi_master_awready), // .awready
.smp_hps_h2f_lw_axi_master_wid (smp_hps_h2f_lw_axi_master_wid), // .wid
.smp_hps_h2f_lw_axi_master_wdata (smp_hps_h2f_lw_axi_master_wdata), // .wdata
.smp_hps_h2f_lw_axi_master_wstrb (smp_hps_h2f_lw_axi_master_wstrb), // .wstrb
.smp_hps_h2f_lw_axi_master_wlast (smp_hps_h2f_lw_axi_master_wlast), // .wlast
.smp_hps_h2f_lw_axi_master_wvalid (smp_hps_h2f_lw_axi_master_wvalid), // .wvalid
.smp_hps_h2f_lw_axi_master_wready (smp_hps_h2f_lw_axi_master_wready), // .wready
.smp_hps_h2f_lw_axi_master_bid (smp_hps_h2f_lw_axi_master_bid), // .bid
.smp_hps_h2f_lw_axi_master_bresp (smp_hps_h2f_lw_axi_master_bresp), // .bresp
.smp_hps_h2f_lw_axi_master_bvalid (smp_hps_h2f_lw_axi_master_bvalid), // .bvalid
.smp_hps_h2f_lw_axi_master_bready (smp_hps_h2f_lw_axi_master_bready), // .bready
.smp_hps_h2f_lw_axi_master_arid (smp_hps_h2f_lw_axi_master_arid), // .arid
.smp_hps_h2f_lw_axi_master_araddr (smp_hps_h2f_lw_axi_master_araddr), // .araddr
.smp_hps_h2f_lw_axi_master_arlen (smp_hps_h2f_lw_axi_master_arlen), // .arlen
.smp_hps_h2f_lw_axi_master_arsize (smp_hps_h2f_lw_axi_master_arsize), // .arsize
.smp_hps_h2f_lw_axi_master_arburst (smp_hps_h2f_lw_axi_master_arburst), // .arburst
.smp_hps_h2f_lw_axi_master_arlock (smp_hps_h2f_lw_axi_master_arlock), // .arlock
.smp_hps_h2f_lw_axi_master_arcache (smp_hps_h2f_lw_axi_master_arcache), // .arcache
.smp_hps_h2f_lw_axi_master_arprot (smp_hps_h2f_lw_axi_master_arprot), // .arprot
.smp_hps_h2f_lw_axi_master_arvalid (smp_hps_h2f_lw_axi_master_arvalid), // .arvalid
.smp_hps_h2f_lw_axi_master_arready (smp_hps_h2f_lw_axi_master_arready), // .arready
.smp_hps_h2f_lw_axi_master_rid (smp_hps_h2f_lw_axi_master_rid), // .rid
.smp_hps_h2f_lw_axi_master_rdata (smp_hps_h2f_lw_axi_master_rdata), // .rdata
.smp_hps_h2f_lw_axi_master_rresp (smp_hps_h2f_lw_axi_master_rresp), // .rresp
.smp_hps_h2f_lw_axi_master_rlast (smp_hps_h2f_lw_axi_master_rlast), // .rlast
.smp_hps_h2f_lw_axi_master_rvalid (smp_hps_h2f_lw_axi_master_rvalid), // .rvalid
.smp_hps_h2f_lw_axi_master_rready (smp_hps_h2f_lw_axi_master_rready), // .rready
.pll_0_outclk0_clk (pll_0_outclk0_clk), // pll_0_outclk0.clk
.pio_0_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // pio_0_reset_reset_bridge_in_reset.reset
.smp_hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // smp_hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
.pio_0_s1_address (mm_interconnect_0_pio_0_s1_address), // pio_0_s1.address
.pio_0_s1_write (mm_interconnect_0_pio_0_s1_write), // .write
.pio_0_s1_readdata (mm_interconnect_0_pio_0_s1_readdata), // .readdata
.pio_0_s1_writedata (mm_interconnect_0_pio_0_s1_writedata), // .writedata
.pio_0_s1_chipselect (mm_interconnect_0_pio_0_s1_chipselect) // .chipselect
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (pll_0_outclk0_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~smp_hps_h2f_reset_reset), // reset_in0.reset
.clk (pll_0_outclk0_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
module fpu_mul_ctl (
inq_in1_51,
inq_in1_54,
inq_in1_53_0_neq_0,
inq_in1_50_0_neq_0,
inq_in1_53_32_neq_0,
inq_in1_exp_eq_0,
inq_in1_exp_neq_ffs,
inq_in2_51,
inq_in2_54,
inq_in2_53_0_neq_0,
inq_in2_50_0_neq_0,
inq_in2_53_32_neq_0,
inq_in2_exp_eq_0,
inq_in2_exp_neq_ffs,
inq_op,
inq_mul,
inq_rnd_mode,
inq_id,
inq_in1_63,
inq_in2_63,
mul_dest_rdy,
mul_dest_rdya,
m5stg_exp,
m5stg_fracadd_cout,
m5stg_frac_neq_0,
m5stg_frac_dbl_nx,
m5stg_frac_sng_nx,
m1stg_ld0_1,
m1stg_ld0_2,
m3stg_exp,
m3stg_expadd_eq_0,
m3stg_expadd_lte_0_inv,
m3stg_ld0_inv,
m4stg_exp,
m4stg_frac_105,
m5stg_frac,
arst_l,
grst_l,
rclk,
mul_pipe_active,
m1stg_snan_sng_in1,
m1stg_snan_dbl_in1,
m1stg_snan_sng_in2,
m1stg_snan_dbl_in2,
m1stg_step,
m1stg_sngop,
m1stg_dblop,
m1stg_dblop_inv,
m1stg_fmul,
m1stg_fsmuld,
m2stg_fmuls,
m2stg_fmuld,
m2stg_fsmuld,
m5stg_fmuls,
m5stg_fmuld,
m5stg_fmulda,
m6stg_fmul_in,
m6stg_id_in,
m6stg_fmul_dbl_dst,
m6stg_fmuls,
m6stg_step,
mul_sign_out,
m5stg_in_of,
mul_exc_out,
m2stg_frac1_dbl_norm,
m2stg_frac1_dbl_dnrm,
m2stg_frac1_sng_norm,
m2stg_frac1_sng_dnrm,
m2stg_frac1_inf,
m2stg_frac2_dbl_norm,
m2stg_frac2_dbl_dnrm,
m2stg_frac2_sng_norm,
m2stg_frac2_sng_dnrm,
m2stg_frac2_inf,
m1stg_inf_zero_in,
m1stg_inf_zero_in_dbl,
m2stg_exp_expadd,
m2stg_exp_0bff,
m2stg_exp_017f,
m2stg_exp_04ff,
m2stg_exp_zero,
m3bstg_ld0_inv,
m4stg_sh_cnt_in,
m4stg_inc_exp_54,
m4stg_inc_exp_55,
m4stg_inc_exp_105,
m4stg_left_shift_step,
m4stg_right_shift_step,
m5stg_to_0,
m5stg_to_0_inv,
mul_frac_out_fracadd,
mul_frac_out_frac,
mul_exp_out_exp_plus1,
mul_exp_out_exp,
mula_rst_l,
se,
si,
so
);
parameter
FMULS= 8'h49,
FMULD= 8'h4a,
FSMULD= 8'h69;
input inq_in1_51; // request operand 1[51]
input inq_in1_54; // request operand 1[54]
input inq_in1_53_0_neq_0; // request operand 1[53:0]!=0
input inq_in1_50_0_neq_0; // request operand 1[50:0]!=0
input inq_in1_53_32_neq_0; // request operand 1[53:32]!=0
input inq_in1_exp_eq_0; // request operand 1[62:52]==0
input inq_in1_exp_neq_ffs; // request operand 1[62:52]!=0x7ff
input inq_in2_51; // request operand 2[51]
input inq_in2_54; // request operand 2[54]
input inq_in2_53_0_neq_0; // request operand 2[53:0]!=0
input inq_in2_50_0_neq_0; // request operand 2[50:0]!=0
input inq_in2_53_32_neq_0; // request operand 2[53:32]!=0
input inq_in2_exp_eq_0; // request operand 2[62:52]==0
input inq_in2_exp_neq_ffs; // request operand 2[62:52]!=0x7ff
input [7:0] inq_op; // request opcode to op pipes
input inq_mul; // multiply pipe request
input [1:0] inq_rnd_mode; // request rounding mode to op pipes
input [4:0] inq_id; // request ID to the operation pipes
input inq_in1_63; // request[63] operand 1 to op pipes
input inq_in2_63; // request[63] operand 2 to op pipes
input mul_dest_rdy; // multiply result req accepted for CPX
input mul_dest_rdya; // multiply result req accepted for CPX
input [12:0] m5stg_exp; // exponent input- multiply 5 stage
input m5stg_fracadd_cout; // fraction rounding adder carry out
input m5stg_frac_neq_0; // fraction input to mul 5 stage != 0
input m5stg_frac_dbl_nx; // double precision inexact result
input m5stg_frac_sng_nx; // single precision inexact result
input [5:0] m1stg_ld0_1; // denorm operand 1 leading 0's
input [5:0] m1stg_ld0_2; // denorm operand 2 leading 0's
input [12:0] m3stg_exp; // exponent input- multiply 3 stage
input m3stg_expadd_eq_0; // mul stage 3 exponent adder sum == 0
input m3stg_expadd_lte_0_inv; // mul stage 3 exponent adder sum <= 0
input [5:0] m3stg_ld0_inv; // leading 0's in multiply operands
input [12:0] m4stg_exp; // exponent input- multiply 4 stage
input m4stg_frac_105; // multiply stage 4a fraction input[105]
input [32:0] m5stg_frac; // multiply stage 5 fraction input
input arst_l; // asynchronous global reset- asserted low
input grst_l; // synchronous global reset- asserted low
input rclk; // global clock
output mul_pipe_active; // mul pipe is executing a valid instr
output m1stg_snan_sng_in1; // operand 1 is single signalling NaN
output m1stg_snan_dbl_in1; // operand 1 is double signalling NaN
output m1stg_snan_sng_in2; // operand 2 is single signalling NaN
output m1stg_snan_dbl_in2; // operand 2 is double signalling NaN
output m1stg_step; // multiply pipe load
output m1stg_sngop; // single precision operation- mul 1 stg
output m1stg_dblop; // double precision operation- mul 1 stg
output m1stg_dblop_inv; // single or int operation- mul 1 stg
output m1stg_fmul; // multiply operation- mul 1 stage
output m1stg_fsmuld; // fsmuld- multiply 1 stage
output m2stg_fmuls; // fmuls- multiply 2 stage
output m2stg_fmuld; // fmuld- multiply 2 stage
output m2stg_fsmuld; // fsmuld- multiply 2 stage
output m5stg_fmuls; // fmuls- multiply 5 stage
output m5stg_fmuld; // fmuld- multiply 5 stage
output m5stg_fmulda; // fmuld- multiply 5 stage copy
output m6stg_fmul_in; // mul pipe output request next cycle
output [9:0] m6stg_id_in; // mul pipe output ID next cycle
output m6stg_fmul_dbl_dst; // double precision multiply result
output m6stg_fmuls; // fmuls- multiply 6 stage
output m6stg_step; // advance the multiply pipe
output mul_sign_out; // multiply sign output
output m5stg_in_of; // multiply overflow- select exp out
output [4:0] mul_exc_out; // multiply pipe result- exception flags
output m2stg_frac1_dbl_norm; // select line to m2stg_frac1
output m2stg_frac1_dbl_dnrm; // select line to m2stg_frac1
output m2stg_frac1_sng_norm; // select line to m2stg_frac1
output m2stg_frac1_sng_dnrm; // select line to m2stg_frac1
output m2stg_frac1_inf; // select line to m2stg_frac1
output m2stg_frac2_dbl_norm; // select line to m2stg_frac2
output m2stg_frac2_dbl_dnrm; // select line to m2stg_frac2
output m2stg_frac2_sng_norm; // select line to m2stg_frac2
output m2stg_frac2_sng_dnrm; // select line to m2stg_frac2
output m2stg_frac2_inf; // select line to m2stg_frac2
output m1stg_inf_zero_in; // 1 operand is infinity; other is 0
output m1stg_inf_zero_in_dbl; // 1 opnd is infinity; other is 0- dbl
output m2stg_exp_expadd; // select line to m2stg_exp
output m2stg_exp_0bff; // select line to m2stg_exp
output m2stg_exp_017f; // select line to m2stg_exp
output m2stg_exp_04ff; // select line to m2stg_exp
output m2stg_exp_zero; // select line to m2stg_exp
output [6:0] m3bstg_ld0_inv; // leading 0's in multiply operands
output [5:0] m4stg_sh_cnt_in; // multiply normalization shift count
output m4stg_inc_exp_54; // select line to m5stg_exp
output m4stg_inc_exp_55; // select line to m5stg_exp
output m4stg_inc_exp_105; // select line to m5stg_exp
output m4stg_left_shift_step; // select line to m5stg_frac
output m4stg_right_shift_step; // select line to m5stg_frac
output m5stg_to_0; // result to max finite on overflow
output m5stg_to_0_inv; // result to infinity on overflow
output mul_frac_out_fracadd; // select line to mul_frac_out
output mul_frac_out_frac; // select line to mul_frac_out
output mul_exp_out_exp_plus1; // select line to mul_exp_out
output mul_exp_out_exp; // select line to mul_exp_out
output mula_rst_l; // reset for mul64
input se; // scan_enable
input si; // scan in
output so; // scan out
wire reset;
wire mul_frac_in1_51;
wire mul_frac_in1_54;
wire mul_frac_in1_53_0_neq_0;
wire mul_frac_in1_50_0_neq_0;
wire mul_frac_in1_53_32_neq_0;
wire mul_exp_in1_exp_eq_0;
wire mul_exp_in1_exp_neq_ffs;
wire mul_frac_in2_51;
wire mul_frac_in2_54;
wire mul_frac_in2_53_0_neq_0;
wire mul_frac_in2_50_0_neq_0;
wire mul_frac_in2_53_32_neq_0;
wire mul_exp_in2_exp_eq_0;
wire mul_exp_in2_exp_neq_ffs;
wire m1stg_denorm_sng_in1;
wire m1stg_denorm_dbl_in1;
wire m1stg_denorm_sng_in2;
wire m1stg_denorm_dbl_in2;
wire m1stg_denorm_in1;
wire m1stg_denorm_in2;
wire m1stg_norm_sng_in1;
wire m1stg_norm_dbl_in1;
wire m1stg_norm_sng_in2;
wire m1stg_norm_dbl_in2;
wire m1stg_snan_sng_in1;
wire m1stg_snan_dbl_in1;
wire m1stg_snan_sng_in2;
wire m1stg_snan_dbl_in2;
wire m1stg_qnan_sng_in1;
wire m1stg_qnan_dbl_in1;
wire m1stg_qnan_sng_in2;
wire m1stg_qnan_dbl_in2;
wire m1stg_snan_in1;
wire m1stg_snan_in2;
wire m1stg_qnan_in1;
wire m1stg_qnan_in2;
wire m2stg_snan_in1;
wire m2stg_snan_in2;
wire m2stg_qnan_in1;
wire m2stg_qnan_in2;
wire m1stg_nan_sng_in1;
wire m1stg_nan_dbl_in1;
wire m1stg_nan_sng_in2;
wire m1stg_nan_dbl_in2;
wire m1stg_nan_in1;
wire m1stg_nan_in2;
wire m2stg_nan_in2;
wire m1stg_inf_sng_in1;
wire m1stg_inf_dbl_in1;
wire m1stg_inf_sng_in2;
wire m1stg_inf_dbl_in2;
wire m1stg_inf_in1;
wire m1stg_inf_in2;
wire m1stg_inf_in;
wire m2stg_inf_in1;
wire m2stg_inf_in2;
wire m2stg_inf_in;
wire m1stg_infnan_sng_in1;
wire m1stg_infnan_dbl_in1;
wire m1stg_infnan_sng_in2;
wire m1stg_infnan_dbl_in2;
wire m1stg_infnan_in1;
wire m1stg_infnan_in2;
wire m1stg_infnan_in;
wire m1stg_zero_in1;
wire m1stg_zero_in2;
wire m1stg_zero_in;
wire m2stg_zero_in1;
wire m2stg_zero_in2;
wire m2stg_zero_in;
wire m1stg_step;
wire [7:0] m1stg_op_in;
wire [7:0] m1stg_op;
wire m1stg_mul_in;
wire m1stg_mul;
wire m1stg_sngop;
wire [3:0] m1stg_sngopa;
wire m1stg_dblop;
wire [3:0] m1stg_dblopa;
wire m1stg_dblop_inv_in;
wire m1stg_dblop_inv;
wire [1:0] m1stg_rnd_mode;
wire [4:0] m1stg_id;
wire m1stg_fmul;
wire m1stg_fmul_dbl_dst;
wire m1stg_fmuls;
wire m1stg_fmuld;
wire m1stg_fsmuld;
wire [4:0] m1stg_opdec;
wire [4:0] m2stg_opdec;
wire [1:0] m2stg_rnd_mode;
wire [4:0] m2stg_id;
wire m2stg_fmul;
wire m2stg_fmuls;
wire m2stg_fmuld;
wire m2stg_fsmuld;
wire [4:1] m3astg_opdec;
wire [1:0] m3astg_rnd_mode;
wire [4:0] m3astg_id;
wire [4:1] m3bstg_opdec;
wire [1:0] m3bstg_rnd_mode;
wire [4:0] m3bstg_id;
wire [4:1] m3stg_opdec;
wire [1:0] m3stg_rnd_mode;
wire [4:0] m3stg_id;
wire m3stg_fmul;
wire [4:1] m4stg_opdec;
wire [1:0] m4stg_rnd_mode;
wire [4:0] m4stg_id;
wire m4stg_fmul;
wire m4stg_fmuld;
wire [4:1] m5stg_opdec;
wire [1:0] m5stg_rnd_mode;
wire [4:0] m5stg_id;
wire m5stg_fmul;
wire m5stg_fmuls;
wire m5stg_fmuld;
wire m5stg_fmulda;
wire m6stg_fmul_in;
wire [4:2] m6stg_opdec;
wire [9:0] m6stg_id_in;
wire [9:0] m6stg_id;
wire m6stg_fmul;
wire m6stg_fmul_dbl_dst;
wire m6stg_fmuls;
wire m6stg_hold;
wire m6stg_holda;
wire m6stg_step;
wire m6stg_stepa;
wire m1stg_sign1;
wire m1stg_sign2;
wire m2stg_sign1;
wire m2stg_sign2;
wire m1stg_of_mask;
wire m2stg_of_mask;
wire m2stg_sign;
wire m3astg_sign;
wire m2stg_nv;
wire m3astg_nv;
wire m3astg_of_mask;
wire m3bstg_sign;
wire m3bstg_nv;
wire m3stg_sign;
wire m3stg_nv;
wire m3stg_of_mask;
wire m4stg_sign;
wire m4stg_nv;
wire m4stg_of_mask;
wire m5stg_sign;
wire m5stg_nv;
wire m5stg_of_mask;
wire mul_sign_out;
wire mul_nv_out;
wire m5stg_in_of;
wire mul_of_out_tmp1_in;
wire mul_of_out_tmp1;
wire mul_of_out_tmp2;
wire mul_of_out_cout;
wire mul_of_out;
wire mul_uf_out_in;
wire mul_uf_out;
wire mul_nx_out_in;
wire mul_nx_out;
wire [4:0] mul_exc_out;
wire m2stg_frac1_dbl_norm;
wire m2stg_frac1_dbl_dnrm;
wire m2stg_frac1_sng_norm;
wire m2stg_frac1_sng_dnrm;
wire m2stg_frac1_inf;
wire m2stg_frac2_dbl_norm;
wire m2stg_frac2_dbl_dnrm;
wire m2stg_frac2_sng_norm;
wire m2stg_frac2_sng_dnrm;
wire m2stg_frac2_inf;
wire m1stg_inf_zero_in;
wire m1stg_inf_zero_in_dbl;
wire [5:0] m2stg_ld0_1_in;
wire [5:0] m2stg_ld0_1;
wire [5:0] m2stg_ld0_2_in;
wire [5:0] m2stg_ld0_2;
wire m2stg_exp_expadd;
wire m2stg_exp_0bff;
wire m2stg_exp_017f;
wire m2stg_exp_04ff;
wire m2stg_exp_zero;
wire [6:0] m2stg_ld0;
wire [6:0] m2stg_ld0_inv;
wire [6:0] m3astg_ld0_inv;
wire [6:0] m3bstg_ld0_inv;
wire m4stg_expadd_eq_0;
wire m3stg_exp_lte_0;
wire m4stg_right_shift_in;
wire m4stg_right_shift;
wire [5:0] m3stg_exp_minus1;
wire [5:0] m3stg_exp_inv_plus2;
wire m3stg_exp_lt_neg57;
wire [5:0] m4stg_sh_cnt_in;
wire m4stg_left_shift_step;
wire m4stg_right_shift_step;
wire m4stg_inc_exp_54;
wire m4stg_inc_exp_55;
wire m4stg_inc_exp_105;
wire m5stg_rndup;
wire m5stg_to_0;
wire m5stg_to_0_inv;
wire mul_frac_out_fracadd;
wire mul_frac_out_frac;
wire mul_exp_out_exp_plus1;
wire mul_exp_out_exp;
wire mul_pipe_active_in;
wire mul_pipe_active;
wire mula_rst_l;
dffrl_async #(1) dffrl_mul_ctl (
.din (grst_l),
.clk (rclk),
.rst_l(arst_l),
.q (mul_ctl_rst_l),
.se (se),
.si (),
.so ()
);
assign reset= (!mul_ctl_rst_l);
// 3/14/03 reset signal for mul64
assign mula_rst_l = mul_ctl_rst_l;
///////////////////////////////////////////////////////////////////////////////
//
// Multiply pipeline special input cases.
//
///////////////////////////////////////////////////////////////////////////////
dffe_s #(1) i_mul_frac_in1_51 (
.din (inq_in1_51),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in1_51),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_frac_in1_54 (
.din (inq_in1_54),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in1_54),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_frac_in1_53_0_neq_0 (
.din (inq_in1_53_0_neq_0),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in1_53_0_neq_0),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_frac_in1_50_0_neq_0 (
.din (inq_in1_50_0_neq_0),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in1_50_0_neq_0),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_frac_in1_53_32_neq_0 (
.din (inq_in1_53_32_neq_0),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in1_53_32_neq_0),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_exp_in1_exp_eq_0 (
.din (inq_in1_exp_eq_0),
.en (m6stg_step),
.clk (rclk),
.q (mul_exp_in1_exp_eq_0),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_exp_in1_exp_neq_ffs (
.din (inq_in1_exp_neq_ffs),
.en (m6stg_step),
.clk (rclk),
.q (mul_exp_in1_exp_neq_ffs),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_frac_in2_51 (
.din (inq_in2_51),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in2_51),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_frac_in2_54 (
.din (inq_in2_54),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in2_54),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_frac_in2_53_0_neq_0 (
.din (inq_in2_53_0_neq_0),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in2_53_0_neq_0),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_frac_in2_50_0_neq_0 (
.din (inq_in2_50_0_neq_0),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in2_50_0_neq_0),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_frac_in2_53_32_neq_0 (
.din (inq_in2_53_32_neq_0),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in2_53_32_neq_0),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_exp_in2_exp_eq_0 (
.din (inq_in2_exp_eq_0),
.en (m6stg_step),
.clk (rclk),
.q (mul_exp_in2_exp_eq_0),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_exp_in2_exp_neq_ffs (
.din (inq_in2_exp_neq_ffs),
.en (m6stg_step),
.clk (rclk),
.q (mul_exp_in2_exp_neq_ffs),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Denorm multiply inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign m1stg_denorm_sng_in1= mul_exp_in1_exp_eq_0 && m1stg_sngopa[0];
assign m1stg_denorm_dbl_in1= mul_exp_in1_exp_eq_0 && m1stg_dblopa[0];
assign m1stg_denorm_sng_in2= mul_exp_in2_exp_eq_0 && m1stg_sngopa[0];
assign m1stg_denorm_dbl_in2= mul_exp_in2_exp_eq_0 && m1stg_dblopa[0];
assign m1stg_denorm_in1= m1stg_denorm_sng_in1 || m1stg_denorm_dbl_in1;
assign m1stg_denorm_in2= m1stg_denorm_sng_in2 || m1stg_denorm_dbl_in2;
///////////////////////////////////////////////////////////////////////////////
//
// Non-denorm multiply inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign m1stg_norm_sng_in1= (!mul_exp_in1_exp_eq_0) && m1stg_sngopa[0];
assign m1stg_norm_dbl_in1= (!mul_exp_in1_exp_eq_0) && m1stg_dblopa[0];
assign m1stg_norm_sng_in2= (!mul_exp_in2_exp_eq_0) && m1stg_sngopa[0];
assign m1stg_norm_dbl_in2= (!mul_exp_in2_exp_eq_0) && m1stg_dblopa[0];
///////////////////////////////////////////////////////////////////////////////
//
// Nan multiply inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign m1stg_snan_sng_in1= (!mul_exp_in1_exp_neq_ffs) && (!mul_frac_in1_54)
&& (mul_frac_in1_53_32_neq_0) && m1stg_sngopa[1];
assign m1stg_snan_dbl_in1= (!mul_exp_in1_exp_neq_ffs)
&& (!mul_frac_in1_51) && mul_frac_in1_50_0_neq_0
&& m1stg_dblopa[1];
assign m1stg_snan_sng_in2= (!mul_exp_in2_exp_neq_ffs) && (!mul_frac_in2_54)
&& (mul_frac_in2_53_32_neq_0) && m1stg_sngopa[1];
assign m1stg_snan_dbl_in2= (!mul_exp_in2_exp_neq_ffs)
&& (!mul_frac_in2_51) && mul_frac_in2_50_0_neq_0
&& m1stg_dblopa[1];
assign m1stg_qnan_sng_in1= (!mul_exp_in1_exp_neq_ffs) && mul_frac_in1_54
&& m1stg_sngopa[1];
assign m1stg_qnan_dbl_in1= (!mul_exp_in1_exp_neq_ffs) && mul_frac_in1_51
&& m1stg_dblopa[1];
assign m1stg_qnan_sng_in2= (!mul_exp_in2_exp_neq_ffs) && mul_frac_in2_54
&& m1stg_sngopa[1];
assign m1stg_qnan_dbl_in2= (!mul_exp_in2_exp_neq_ffs) && mul_frac_in2_51
&& m1stg_dblopa[1];
assign m1stg_snan_in1= m1stg_snan_sng_in1 || m1stg_snan_dbl_in1;
assign m1stg_snan_in2= m1stg_snan_sng_in2 || m1stg_snan_dbl_in2;
assign m1stg_qnan_in1= m1stg_qnan_sng_in1 || m1stg_qnan_dbl_in1;
assign m1stg_qnan_in2= m1stg_qnan_sng_in2 || m1stg_qnan_dbl_in2;
dffe_s #(1) i_m2stg_snan_in1 (
.din (m1stg_snan_in1),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_snan_in1),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m2stg_snan_in2 (
.din (m1stg_snan_in2),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_snan_in2),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m2stg_qnan_in1 (
.din (m1stg_qnan_in1),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_qnan_in1),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m2stg_qnan_in2 (
.din (m1stg_qnan_in2),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_qnan_in2),
.se (se),
.si (),
.so ()
);
assign m1stg_nan_sng_in1= (!mul_exp_in1_exp_neq_ffs)
&& (mul_frac_in1_54 || mul_frac_in1_53_32_neq_0)
&& m1stg_sngopa[2];
assign m1stg_nan_dbl_in1= (!mul_exp_in1_exp_neq_ffs)
&& (mul_frac_in1_51 || mul_frac_in1_50_0_neq_0)
&& m1stg_dblopa[2];
assign m1stg_nan_sng_in2= (!mul_exp_in2_exp_neq_ffs)
&& (mul_frac_in2_54 || mul_frac_in2_53_32_neq_0)
&& m1stg_sngopa[2];
assign m1stg_nan_dbl_in2= (!mul_exp_in2_exp_neq_ffs)
&& (mul_frac_in2_51 || mul_frac_in2_50_0_neq_0)
&& m1stg_dblopa[2];
assign m1stg_nan_in1= m1stg_nan_sng_in1 || m1stg_nan_dbl_in1;
assign m1stg_nan_in2= m1stg_nan_sng_in2 || m1stg_nan_dbl_in2;
dffe_s #(1) i_m2stg_nan_in2 (
.din (m1stg_nan_in2),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_nan_in2),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Infinity multiply inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign m1stg_inf_sng_in1= (!mul_exp_in1_exp_neq_ffs)
&& (!mul_frac_in1_54) && (!mul_frac_in1_53_32_neq_0)
&& m1stg_sngopa[2];
assign m1stg_inf_dbl_in1= (!mul_exp_in1_exp_neq_ffs)
&& (!mul_frac_in1_51) && (!mul_frac_in1_50_0_neq_0)
&& m1stg_dblopa[2];
assign m1stg_inf_sng_in2= (!mul_exp_in2_exp_neq_ffs)
&& (!mul_frac_in2_54) && (!mul_frac_in2_53_32_neq_0)
&& m1stg_sngopa[2];
assign m1stg_inf_dbl_in2= (!mul_exp_in2_exp_neq_ffs)
&& (!mul_frac_in2_51) && (!mul_frac_in2_50_0_neq_0)
&& m1stg_dblopa[2];
assign m1stg_inf_in1= m1stg_inf_sng_in1 || m1stg_inf_dbl_in1;
assign m1stg_inf_in2= m1stg_inf_sng_in2 || m1stg_inf_dbl_in2;
assign m1stg_inf_in= m1stg_inf_in1 || m1stg_inf_in2;
dffe_s #(1) i_m2stg_inf_in1 (
.din (m1stg_inf_in1),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_inf_in1),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m2stg_inf_in2 (
.din (m1stg_inf_in2),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_inf_in2),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m2stg_inf_in (
.din (m1stg_inf_in),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_inf_in),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Infinity/Nan multiply inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign m1stg_infnan_sng_in1= (!mul_exp_in1_exp_neq_ffs) && m1stg_sngopa[3];
assign m1stg_infnan_dbl_in1= (!mul_exp_in1_exp_neq_ffs) && m1stg_dblopa[3];
assign m1stg_infnan_sng_in2= (!mul_exp_in2_exp_neq_ffs) && m1stg_sngopa[3];
assign m1stg_infnan_dbl_in2= (!mul_exp_in2_exp_neq_ffs) && m1stg_dblopa[3];
assign m1stg_infnan_in1= m1stg_infnan_sng_in1 || m1stg_infnan_dbl_in1;
assign m1stg_infnan_in2= m1stg_infnan_sng_in2 || m1stg_infnan_dbl_in2;
assign m1stg_infnan_in= m1stg_infnan_in1 || m1stg_infnan_in2;
///////////////////////////////////////////////////////////////////////////////
//
// Zero multiply inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign m1stg_zero_in1= mul_exp_in1_exp_eq_0
&& (!mul_frac_in1_53_0_neq_0) && (!mul_frac_in1_54);
assign m1stg_zero_in2= mul_exp_in2_exp_eq_0
&& (!mul_frac_in2_53_0_neq_0) && (!mul_frac_in2_54);
assign m1stg_zero_in= m1stg_zero_in1 || m1stg_zero_in2;
dffe_s #(1) i_m2stg_zero_in1 (
.din (m1stg_zero_in1),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_zero_in1),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m2stg_zero_in2 (
.din (m1stg_zero_in2),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_zero_in2),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m2stg_zero_in (
.din (m1stg_zero_in),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_zero_in),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Floating point multiply control pipeline.
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- multiply input stage.
//
///////////////////////////////////////////////////////////////////////////////
assign m1stg_step= m6stg_stepa && (!m1stg_mul);
assign m1stg_op_in[7:0]= ({8{(m1stg_step && (!reset))}}
& (inq_op[7:0] & {8{inq_mul}}))
| ({8{((!m6stg_step) && (!reset))}}
& m1stg_op[7:0]);
dff_s #(8) i_m1stg_op (
.din (m1stg_op_in[7:0]),
.clk (rclk),
.q (m1stg_op[7:0]),
.se (se),
.si (),
.so ()
);
assign m1stg_mul_in= (m1stg_step && (!reset) && inq_mul)
|| ((!m6stg_step) && (!reset) && m1stg_mul);
dff_s #(1) i_m1stg_mul (
.din (m1stg_mul_in),
.clk (rclk),
.q (m1stg_mul),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m1stg_sngop (
.din (inq_op[0]),
.en (m6stg_step),
.clk (rclk),
.q (m1stg_sngop),
.se (se),
.si (),
.so ()
);
dffe_s #(4) i_m1stg_sngopa (
.din ({4{inq_op[0]}}),
.en (m6stg_step),
.clk (rclk),
.q (m1stg_sngopa[3:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m1stg_dblop (
.din (inq_op[1]),
.en (m6stg_step),
.clk (rclk),
.q (m1stg_dblop),
.se (se),
.si (),
.so ()
);
dffe_s #(4) i_m1stg_dblopa (
.din ({4{inq_op[1]}}),
.en (m6stg_step),
.clk (rclk),
.q (m1stg_dblopa[3:0]),
.se (se),
.si (),
.so ()
);
assign m1stg_dblop_inv_in= (!inq_op[1]);
dffe_s #(1) i_m1stg_dblop_inv (
.din (m1stg_dblop_inv_in),
.en (m6stg_step),
.clk (rclk),
.q (m1stg_dblop_inv),
.se (se),
.si (),
.so ()
);
dffe_s #(2) i_m1stg_rnd_mode (
.din (inq_rnd_mode[1:0]),
.en (m6stg_step),
.clk (rclk),
.q (m1stg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(5) i_m1stg_id (
.din (inq_id[4:0]),
.en (m6stg_step),
.clk (rclk),
.q (m1stg_id[4:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode decode- multiply stage 1.
//
///////////////////////////////////////////////////////////////////////////////
assign m1stg_fmul= (m1stg_op[7:0]==FMULS) || (m1stg_op[7:0]==FMULD)
|| (m1stg_op[7:0]==FSMULD);
assign m1stg_fmul_dbl_dst= (m1stg_op[7:0]==FMULD) || (m1stg_op[7:0]==FSMULD);
assign m1stg_fmuls= (m1stg_op[7:0]==FMULS);
assign m1stg_fmuld= (m1stg_op[7:0]==FMULD);
assign m1stg_fsmuld= (m1stg_op[7:0]==FSMULD);
assign m1stg_opdec[4:0]= {m1stg_fmul,
m1stg_fmul_dbl_dst,
m1stg_fmuls,
m1stg_fmuld,
m1stg_fsmuld};
dffre_s #(5) i_m2stg_opdec (
.din (m1stg_opdec[4:0]),
.en (m6stg_step),
.rst (reset),
.clk (rclk),
.q (m2stg_opdec[4:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(2) i_m2stg_rnd_mode (
.din (m1stg_rnd_mode[1:0]),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(5) i_m2stg_id (
.din (m1stg_id[4:0]),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_id[4:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- multiply stage 2.
//
///////////////////////////////////////////////////////////////////////////////
assign m2stg_fmul= m2stg_opdec[4];
assign m2stg_fmuls= m2stg_opdec[2];
assign m2stg_fmuld= m2stg_opdec[1];
assign m2stg_fsmuld= m2stg_opdec[0];
dffre_s #(4) i_m3astg_opdec (
.din (m2stg_opdec[4:1]),
.en (m6stg_step),
.rst (reset),
.clk (rclk),
.q (m3astg_opdec[4:1]),
.se (se),
.si (),
.so ()
);
dffe_s #(2) i_m3astg_rnd_mode (
.din (m2stg_rnd_mode[1:0]),
.en (m6stg_step),
.clk (rclk),
.q (m3astg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(5) i_m3astg_id (
.din (m2stg_id[4:0]),
.en (m6stg_step),
.clk (rclk),
.q (m3astg_id[4:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- multiply stage 3a.
//
///////////////////////////////////////////////////////////////////////////////
dffre_s #(4) i_m3bstg_opdec (
.din (m3astg_opdec[4:1]),
.en (m6stg_step),
.rst (reset),
.clk (rclk),
.q (m3bstg_opdec[4:1]),
.se (se),
.si (),
.so ()
);
dffe_s #(2) i_m3bstg_rnd_mode (
.din (m3astg_rnd_mode[1:0]),
.en (m6stg_step),
.clk (rclk),
.q (m3bstg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(5) i_m3bstg_id (
.din (m3astg_id[4:0]),
.en (m6stg_step),
.clk (rclk),
.q (m3bstg_id[4:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- multiply stage 3b.
//
///////////////////////////////////////////////////////////////////////////////
dffre_s #(4) i_m3stg_opdec (
.din (m3bstg_opdec[4:1]),
.en (m6stg_step),
.rst (reset),
.clk (rclk),
.q (m3stg_opdec[4:1]),
.se (se),
.si (),
.so ()
);
dffe_s #(2) i_m3stg_rnd_mode (
.din (m3bstg_rnd_mode[1:0]),
.en (m6stg_step),
.clk (rclk),
.q (m3stg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(5) i_m3stg_id (
.din (m3bstg_id[4:0]),
.en (m6stg_step),
.clk (rclk),
.q (m3stg_id[4:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- multiply stage 3.
//
///////////////////////////////////////////////////////////////////////////////
assign m3stg_fmul= m3stg_opdec[4];
dffre_s #(4) i_m4stg_opdec (
.din (m3stg_opdec[4:1]),
.en (m6stg_step),
.rst (reset),
.clk (rclk),
.q (m4stg_opdec[4:1]),
.se (se),
.si (),
.so ()
);
dffe_s #(2) i_m4stg_rnd_mode (
.din (m3stg_rnd_mode[1:0]),
.en (m6stg_step),
.clk (rclk),
.q (m4stg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(5) i_m4stg_id (
.din (m3stg_id[4:0]),
.en (m6stg_step),
.clk (rclk),
.q (m4stg_id[4:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- multiply stage 4.
//
///////////////////////////////////////////////////////////////////////////////
assign m4stg_fmul= m4stg_opdec[4];
assign m4stg_fmuld= m4stg_opdec[1];
dffre_s #(4) i_m5stg_opdec (
.din (m4stg_opdec[4:1]),
.en (m6stg_step),
.rst (reset),
.clk (rclk),
.q (m5stg_opdec[4:1]),
.se (se),
.si (),
.so ()
);
dffe_s #(2) i_m5stg_rnd_mode (
.din (m4stg_rnd_mode[1:0]),
.en (m6stg_step),
.clk (rclk),
.q (m5stg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe_s #(5) i_m5stg_id (
.din (m4stg_id[4:0]),
.en (m6stg_step),
.clk (rclk),
.q (m5stg_id[4:0]),
.se (se),
.si (),
.so ()
);
dffre_s #(1) i_m5stg_fmulda (
.din (m4stg_fmuld),
.en (m6stg_step),
.rst (reset),
.clk (rclk),
.q (m5stg_fmulda),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- multiply stage 5.
//
///////////////////////////////////////////////////////////////////////////////
assign m5stg_fmul= m5stg_opdec[4];
assign m5stg_fmuls= m5stg_opdec[2];
assign m5stg_fmuld= m5stg_opdec[1];
assign m6stg_fmul_in= (m6stg_stepa && (!reset)
&& m5stg_fmul)
|| ((!m6stg_stepa) && (!reset)
&& m6stg_fmul);
dffre_s #(3) i_m6stg_opdec (
.din (m5stg_opdec[4:2]),
.en (m6stg_step),
.rst (reset),
.clk (rclk),
.q (m6stg_opdec[4:2]),
.se (se),
.si (),
.so ()
);
assign m6stg_id_in[9:0]= ({10{m6stg_stepa}}
& {(m5stg_id[4:2]==3'o7),
(m5stg_id[4:2]==3'o6),
(m5stg_id[4:2]==3'o5),
(m5stg_id[4:2]==3'o4),
(m5stg_id[4:2]==3'o3),
(m5stg_id[4:2]==3'o2),
(m5stg_id[4:2]==3'o1),
(m5stg_id[4:2]==3'o0),
m5stg_id[1:0]})
| ({10{(!m6stg_stepa)}}
& m6stg_id[9:0]);
dffe_s #(10) i_m6stg_id (
.din (m6stg_id_in[9:0]),
.en (m6stg_step),
.clk (rclk),
.q (m6stg_id[9:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- multiply pipeline output.
//
///////////////////////////////////////////////////////////////////////////////
assign m6stg_fmul= m6stg_opdec[4];
assign m6stg_fmul_dbl_dst= m6stg_opdec[3];
assign m6stg_fmuls= m6stg_opdec[2];
assign m6stg_hold= m6stg_fmul && (!mul_dest_rdy);
assign m6stg_holda= m6stg_fmul && (!mul_dest_rdya);
assign m6stg_step= (!m6stg_hold);
assign m6stg_stepa= (!m6stg_holda);
// Austin update
// Power management update
assign mul_pipe_active_in = // mul pipe is executing a valid instr
m1stg_fmul || m2stg_fmul || m3astg_opdec[4] || m3bstg_opdec[4] ||
m3stg_fmul || m4stg_fmul || m5stg_fmul || m6stg_fmul;
dffre_s #(1) i_mul_pipe_active (
.din (mul_pipe_active_in),
.en (1'b1),
.rst (reset),
.clk (rclk),
.q (mul_pipe_active),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Multiply sign and exception logic.
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
// Multiply sign inputs.
//
///////////////////////////////////////////////////////////////////////////////
dffe_s #(1) i_m1stg_sign1 (
.din (inq_in1_63),
.en (m6stg_step),
.clk (rclk),
.q (m1stg_sign1),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m1stg_sign2 (
.din (inq_in2_63),
.en (m6stg_step),
.clk (rclk),
.q (m1stg_sign2),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Multiply sign and exceptions.
//
// Multiply stage 1.
//
///////////////////////////////////////////////////////////////////////////////
dffe_s #(1) i_m2stg_sign1 (
.din (m1stg_sign1),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_sign1),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m2stg_sign2 (
.din (m1stg_sign2),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_sign2),
.se (se),
.si (),
.so ()
);
assign m1stg_of_mask= (!m1stg_infnan_in);
dffe_s #(1) i_m2stg_of_mask (
.din (m1stg_of_mask),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_of_mask),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Multiply sign and exceptions.
//
// Multiply stage 2.
//
///////////////////////////////////////////////////////////////////////////////
assign m2stg_sign= ((m2stg_sign1
&& (!m2stg_snan_in2)
&& (!(m2stg_qnan_in2 && (!m2stg_snan_in1))))
^ (m2stg_sign2
&& (!(m2stg_snan_in1 && (!m2stg_snan_in2)))
&& (!(m2stg_qnan_in1 && (!m2stg_nan_in2)))))
&& (!(m2stg_inf_in && m2stg_zero_in));
dffe_s #(1) i_m3astg_sign (
.din (m2stg_sign),
.en (m6stg_step),
.clk (rclk),
.q (m3astg_sign),
.se (se),
.si (),
.so ()
);
assign m2stg_nv= m2stg_snan_in1
|| m2stg_snan_in2
|| (m2stg_zero_in1 && m2stg_inf_in2)
|| (m2stg_inf_in1 && m2stg_zero_in2);
dffe_s #(1) i_m3astg_nv (
.din (m2stg_nv),
.en (m6stg_step),
.clk (rclk),
.q (m3astg_nv),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m3astg_of_mask (
.din (m2stg_of_mask),
.en (m6stg_step),
.clk (rclk),
.q (m3astg_of_mask),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Multiply sign and exceptions.
//
// Multiply stage 3a.
//
///////////////////////////////////////////////////////////////////////////////
dffe_s #(1) i_m3bstg_sign (
.din (m3astg_sign),
.en (m6stg_step),
.clk (rclk),
.q (m3bstg_sign),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m3bstg_nv (
.din (m3astg_nv),
.en (m6stg_step),
.clk (rclk),
.q (m3bstg_nv),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m3bstg_of_mask (
.din (m3astg_of_mask),
.en (m6stg_step),
.clk (rclk),
.q (m3bstg_of_mask),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Multiply sign and exceptions.
//
// Multiply stage 3b.
//
///////////////////////////////////////////////////////////////////////////////
dffe_s #(1) i_m3stg_sign (
.din (m3bstg_sign),
.en (m6stg_step),
.clk (rclk),
.q (m3stg_sign),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m3stg_nv (
.din (m3bstg_nv),
.en (m6stg_step),
.clk (rclk),
.q (m3stg_nv),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m3stg_of_mask (
.din (m3bstg_of_mask),
.en (m6stg_step),
.clk (rclk),
.q (m3stg_of_mask),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Multiply sign and exceptions.
//
// Multiply stage 3.
//
///////////////////////////////////////////////////////////////////////////////
dffe_s #(1) i_m4stg_sign (
.din (m3stg_sign),
.en (m6stg_step),
.clk (rclk),
.q (m4stg_sign),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m4stg_nv (
.din (m3stg_nv),
.en (m6stg_step),
.clk (rclk),
.q (m4stg_nv),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m4stg_of_mask (
.din (m3stg_of_mask),
.en (m6stg_step),
.clk (rclk),
.q (m4stg_of_mask),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Multiply sign and exceptions.
//
// Multiply stage 4.
//
///////////////////////////////////////////////////////////////////////////////
dffe_s #(1) i_m5stg_sign (
.din (m4stg_sign),
.en (m6stg_step),
.clk (rclk),
.q (m5stg_sign),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m5stg_nv (
.din (m4stg_nv),
.en (m6stg_step),
.clk (rclk),
.q (m5stg_nv),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_m5stg_of_mask (
.din (m4stg_of_mask),
.en (m6stg_step),
.clk (rclk),
.q (m5stg_of_mask),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Multiply sign and exceptions.
//
// Multiply stage 5.
//
///////////////////////////////////////////////////////////////////////////////
dffe_s #(1) i_mul_sign_out (
.din (m5stg_sign),
.en (m6stg_step),
.clk (rclk),
.q (mul_sign_out),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_nv_out (
.din (m5stg_nv),
.en (m6stg_step),
.clk (rclk),
.q (mul_nv_out),
.se (se),
.si (),
.so ()
);
assign m5stg_in_of= ((!m5stg_exp[12])
&& m5stg_fmuld
&& (m5stg_exp[11] || (&m5stg_exp[10:0]))
&& m5stg_of_mask)
|| ((!m5stg_exp[12])
&& m5stg_fmuls
&& ((|m5stg_exp[11:8]) || (&m5stg_exp[7:0]))
&& m5stg_of_mask);
assign mul_of_out_tmp1_in= ((!m5stg_exp[12])
&& m5stg_fmuld
&& (&m5stg_exp[10:1])
&& m5stg_rndup
&& m5stg_of_mask)
|| ((!m5stg_exp[12])
&& m5stg_fmuls
&& (&m5stg_exp[7:1])
&& m5stg_rndup
&& m5stg_of_mask);
dffe_s #(1) i_mul_of_out_tmp1 (
.din (mul_of_out_tmp1_in),
.en (m6stg_step),
.clk (rclk),
.q (mul_of_out_tmp1),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_of_out_tmp2 (
.din (m5stg_in_of),
.en (m6stg_step),
.clk (rclk),
.q (mul_of_out_tmp2),
.se (se),
.si (),
.so ()
);
dffe_s #(1) i_mul_of_out_cout (
.din (m5stg_fracadd_cout),
.en (m6stg_step),
.clk (rclk),
.q (mul_of_out_cout),
.se (se),
.si (),
.so ()
);
assign mul_of_out= mul_of_out_tmp2
|| (mul_of_out_tmp1 && mul_of_out_cout);
assign mul_uf_out_in= (m5stg_exp[12] || (!(|m5stg_exp[11:0])))
&& m5stg_frac_neq_0;
dffe_s #(1) i_mul_uf_out (
.din (mul_uf_out_in),
.en (m6stg_step),
.clk (rclk),
.q (mul_uf_out),
.se (se),
.si (),
.so ()
);
assign mul_nx_out_in= (m5stg_fmuld && m5stg_frac_dbl_nx)
|| (m5stg_fmuls && m5stg_frac_sng_nx);
dffe_s #(1) i_mul_nx_out (
.din (mul_nx_out_in),
.en (m6stg_step),
.clk (rclk),
.q (mul_nx_out),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Multiply exception output.
//
///////////////////////////////////////////////////////////////////////////////
// Austin update
// Overflow is always accompanied by inexact.
// Previously this was handled within the FFU.
// assign mul_exc_out[4:0]= {mul_nv_out, mul_of_out, mul_uf_out, 1'b0, mul_nx_out};
assign mul_exc_out[4:0] =
{mul_nv_out,
mul_of_out,
mul_uf_out,
1'b0,
(mul_nx_out || mul_of_out)}; // Overflow is always accompanied by inexact
///////////////////////////////////////////////////////////////////////////////
//
// Multiply pipeline control logic.
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
// Select lines- multiply normalization and special input injection.
//
// Multiply stage 1.
//
///////////////////////////////////////////////////////////////////////////////
assign m2stg_frac1_dbl_norm= m1stg_norm_dbl_in1
&& ((!(m1stg_infnan_dbl_in1 || m1stg_infnan_dbl_in2))
|| (m1stg_snan_dbl_in1 && (!m1stg_snan_dbl_in2))
|| (m1stg_qnan_dbl_in1 && (!m1stg_nan_dbl_in2)));
assign m2stg_frac1_dbl_dnrm= m1stg_denorm_dbl_in1
&& (!(m1stg_infnan_dbl_in1 || m1stg_infnan_dbl_in2));
assign m2stg_frac1_sng_norm= m1stg_norm_sng_in1
&& ((!(m1stg_infnan_sng_in1 || m1stg_infnan_sng_in2))
|| (m1stg_snan_sng_in1 && (!m1stg_snan_sng_in2))
|| (m1stg_qnan_sng_in1 && (!m1stg_nan_sng_in2)));
assign m2stg_frac1_sng_dnrm= m1stg_denorm_sng_in1
&& (!(m1stg_infnan_sng_in1 || m1stg_infnan_sng_in2));
assign m2stg_frac1_inf= (m1stg_inf_in && (!m1stg_nan_in1) && (!m1stg_nan_in2))
|| m1stg_snan_in2
|| (m1stg_qnan_in2 && (!m1stg_snan_in1));
assign m2stg_frac2_dbl_norm= m1stg_norm_dbl_in2
&& ((!(m1stg_infnan_dbl_in1 || m1stg_infnan_dbl_in2))
|| m1stg_snan_dbl_in2
|| (m1stg_qnan_dbl_in2 && (!m1stg_snan_dbl_in1)));
assign m2stg_frac2_dbl_dnrm= m1stg_denorm_dbl_in2
&& (!(m1stg_infnan_dbl_in1 || m1stg_infnan_dbl_in2));
assign m2stg_frac2_sng_norm= m1stg_norm_sng_in2
&& ((!(m1stg_infnan_sng_in1 || m1stg_infnan_sng_in2))
|| m1stg_snan_sng_in2
|| (m1stg_qnan_sng_in2 && (!m1stg_snan_sng_in1)));
assign m2stg_frac2_sng_dnrm= m1stg_denorm_sng_in2
&& (!(m1stg_infnan_sng_in1 || m1stg_infnan_sng_in2));
assign m2stg_frac2_inf= (m1stg_inf_in && (!m1stg_nan_in1) && (!m1stg_nan_in2))
|| (m1stg_snan_in1 && (!m1stg_snan_in2))
|| (m1stg_qnan_in1 && (!m1stg_nan_in2));
assign m1stg_inf_zero_in= (m1stg_inf_in1 && m1stg_zero_in2)
|| (m1stg_zero_in1 && m1stg_inf_in2);
assign m1stg_inf_zero_in_dbl= ((m1stg_inf_in1 && m1stg_zero_in2)
|| (m1stg_zero_in1 && m1stg_inf_in2))
&& m1stg_fmul_dbl_dst;
///////////////////////////////////////////////////////////////////////////////
//
// Select lines and control logic- multiply leading 0 counts.
//
// Multiply stage 1.
//
///////////////////////////////////////////////////////////////////////////////
assign m2stg_ld0_1_in[5:0]= ({6{(m1stg_denorm_in1 && (!m1stg_infnan_in))}}
& m1stg_ld0_1[5:0]);
dffe_s #(6) i_m2stg_ld0_1 (
.din (m2stg_ld0_1_in[5:0]),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_ld0_1[5:0]),
.se (se),
.si (),
.so ()
);
assign m2stg_ld0_2_in[5:0]= ({6{(m1stg_denorm_in2 && (!m1stg_infnan_in))}}
& m1stg_ld0_2[5:0]);
dffe_s #(6) i_m2stg_ld0_2 (
.din (m2stg_ld0_2_in[5:0]),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_ld0_2[5:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Select lines- multiply exponent adder.
//
// Multiply stage 1.
//
///////////////////////////////////////////////////////////////////////////////
assign m2stg_exp_expadd= (!m1stg_infnan_in) && (!m1stg_zero_in);
assign m2stg_exp_0bff= m1stg_fmuld && m1stg_infnan_in;
assign m2stg_exp_017f= m1stg_fmuls && m1stg_infnan_in;
assign m2stg_exp_04ff= m1stg_fsmuld && m1stg_infnan_in;
assign m2stg_exp_zero= m1stg_zero_in && (!m1stg_infnan_in);
///////////////////////////////////////////////////////////////////////////////
//
// Total the leading 0's.
//
// Multiply stage 2.
//
///////////////////////////////////////////////////////////////////////////////
assign m2stg_ld0[6:0]= {1'b0, m2stg_ld0_1[5:0]}
+ {1'b0, m2stg_ld0_2[5:0]};
assign m2stg_ld0_inv[6:0]= (~m2stg_ld0[6:0]);
dffe_s #(7) i_m3astg_ld0_inv (
.din (m2stg_ld0_inv[6:0]),
.en (m6stg_step),
.clk (rclk),
.q (m3astg_ld0_inv[6:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Leading 0's.
//
// Multiply stage 3a.
//
///////////////////////////////////////////////////////////////////////////////
dffe_s #(7) i_m3bstg_ld0_inv (
.din (m3astg_ld0_inv[6:0]),
.en (m6stg_step),
.clk (rclk),
.q (m3bstg_ld0_inv[6:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Post-normalization/denormalization shift count and direction.
//
// Multiply stage 3.
//
///////////////////////////////////////////////////////////////////////////////
dffe_s #(1) i_m4stg_expadd_eq_0 (
.din (m3stg_expadd_eq_0),
.en (m6stg_step),
.clk (rclk),
.q (m4stg_expadd_eq_0),
.se (se),
.si (),
.so ()
);
assign m3stg_exp_lte_0= (!(|m3stg_exp[11:0])) || m3stg_exp[12];
assign m4stg_right_shift_in= (!m3stg_expadd_lte_0_inv) && m3stg_exp_lte_0;
dffe_s #(1) i_m4stg_right_shift (
.din (m4stg_right_shift_in),
.en (m6stg_step),
.clk (rclk),
.q (m4stg_right_shift),
.se (se),
.si (),
.so ()
);
assign m3stg_exp_minus1[5:0]= m3stg_exp[5:0]
+ 6'h3f;
assign m3stg_exp_inv_plus2[5:0]= (~m3stg_exp[5:0])
+ 6'h02;
assign m3stg_exp_lt_neg57= ((!(&m3stg_exp[11:6]))
|| (!(|m3stg_exp[5:3])))
&& m3stg_exp[12];
assign m4stg_sh_cnt_in[5:0]= ({6{((!m3stg_expadd_lte_0_inv)
&& (!m3stg_exp_lte_0))}}
& m3stg_exp_minus1[5:0])
| ({6{((!m3stg_expadd_lte_0_inv) && m3stg_exp_lte_0
&& m3stg_exp_lt_neg57)}}
& 6'h39)
| ({6{((!m3stg_expadd_lte_0_inv) && m3stg_exp_lte_0
&& (!m3stg_exp_lt_neg57))}}
& m3stg_exp_inv_plus2[5:0])
| ({6{m3stg_expadd_lte_0_inv}}
& (~m3stg_ld0_inv[5:0]));
///////////////////////////////////////////////////////////////////////////////
//
// Select lines and control logic- multiply shifts for
// post-normalization/denormalization.
//
// Multiply stage 4.
//
///////////////////////////////////////////////////////////////////////////////
assign m4stg_left_shift_step= (!m4stg_right_shift) && m6stg_step;
assign m4stg_right_shift_step= m4stg_right_shift && m6stg_step;
// Austin update
// uarch timing fix
// Endpoint: fpu_mul_exp_dp/i_m5stg_exp_pre2_10
// assign m4stg_inc_exp= (((!(|m4stg_exp[12:0])) && (!m4stg_right_shift)
// && m4stg_shl_54)
// || (m4stg_expadd_eq_0 && m4stg_right_shift
// && m4stg_frac_105)
// || ((!m4stg_right_shift) && m4stg_shl_55))
// && m6stg_step;
//
// assign m4stg_inc_exp_inv= (!m4stg_inc_exp) && m6stg_step;
assign m4stg_inc_exp_54 = (!(|m4stg_exp[12:0])) && (!m4stg_right_shift);
assign m4stg_inc_exp_55 = !m4stg_right_shift;
assign m4stg_inc_exp_105 = m4stg_expadd_eq_0 && m4stg_right_shift && m4stg_frac_105;
///////////////////////////////////////////////////////////////////////////////
//
// Select lines and control logic- multiply rounding.
//
// Multiply stage 5.
//
///////////////////////////////////////////////////////////////////////////////
assign m5stg_rndup= ((((m5stg_rnd_mode[1:0]==2'b10) && (!m5stg_sign)
&& (m5stg_frac[2:0]!=3'b0))
|| ((m5stg_rnd_mode[1:0]==2'b11) && m5stg_sign
&& (m5stg_frac[2:0]!=3'b0))
|| ((m5stg_rnd_mode[1:0]==2'b00)
&& m5stg_frac[2]
&& ((m5stg_frac[1:0]!=2'b0)
|| m5stg_frac[3])))
&& m5stg_fmuld)
|| ((((m5stg_rnd_mode[1:0]==2'b10) && (!m5stg_sign)
&& (m5stg_frac[31:0]!=32'b0))
|| ((m5stg_rnd_mode[1:0]==2'b11) && m5stg_sign
&& (m5stg_frac[31:0]!=32'b0))
|| ((m5stg_rnd_mode[1:0]==2'b00)
&& m5stg_frac[31]
&& ((m5stg_frac[30:0]!=31'b0)
|| m5stg_frac[32])))
&& m5stg_fmuls);
assign m5stg_to_0= (m5stg_rnd_mode[1:0]==2'b01)
|| ((m5stg_rnd_mode[1:0]==2'b10) && m5stg_sign)
|| ((m5stg_rnd_mode[1:0]==2'b11) && (!m5stg_sign));
assign m5stg_to_0_inv= (!m5stg_to_0);
assign mul_frac_out_fracadd= m5stg_rndup && (!m5stg_in_of);
assign mul_frac_out_frac= (!m5stg_rndup) && (!m5stg_in_of);
assign mul_exp_out_exp_plus1= m5stg_rndup && (!m5stg_in_of);
assign mul_exp_out_exp= (!m5stg_rndup) && (!m5stg_in_of);
endmodule
|
module sky130_fd_sc_lp__and3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_lp__and3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
|
module emaxi(/*autoarg*/
// Outputs
emwr_rd_en, emrq_rd_en, emrr_access, emrr_write, emrr_datamode,
emrr_ctrlmode, emrr_dstaddr, emrr_data, emrr_srcaddr, m_axi_awid,
m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst,
m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awqos,
m_axi_awvalid, m_axi_wid, m_axi_wdata, m_axi_wstrb, m_axi_wlast,
m_axi_wvalid, m_axi_bready, m_axi_arid, m_axi_araddr, m_axi_arlen,
m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache,
m_axi_arprot, m_axi_arqos, m_axi_arvalid, m_axi_rready,
// Inputs
emwr_access, emwr_write, emwr_datamode, emwr_ctrlmode,
emwr_dstaddr, emwr_data, emwr_srcaddr, emrq_access, emrq_write,
emrq_datamode, emrq_ctrlmode, emrq_dstaddr, emrq_data,
emrq_srcaddr, emrr_progfull, m_axi_aclk, m_axi_aresetn,
m_axi_awready, m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid,
m_axi_arready, m_axi_rid, m_axi_rdata, m_axi_rresp, m_axi_rlast,
m_axi_rvalid
);
parameter IDW = 12;
// fifo read-master port, writes from rx
input emwr_access;
input emwr_write;
input [1:0] emwr_datamode;
input [3:0] emwr_ctrlmode;
input [31:0] emwr_dstaddr;
input [31:0] emwr_data;
input [31:0] emwr_srcaddr;
output emwr_rd_en; //read ptr update for fifo
// fifo read-master port; read requests from rx
input emrq_access;
input emrq_write;
input [1:0] emrq_datamode;
input [3:0] emrq_ctrlmode;
input [31:0] emrq_dstaddr;
input [31:0] emrq_data;
input [31:0] emrq_srcaddr;
output emrq_rd_en; //read ptr update for fifo
// fifo write-master port; read responses for etx
output emrr_access;
output emrr_write;
output [1:0] emrr_datamode;
output [3:0] emrr_ctrlmode;
output [31:0] emrr_dstaddr;
output [31:0] emrr_data;
output [31:0] emrr_srcaddr;
input emrr_progfull;
/*****************************/
/*axi */
/*****************************/
input m_axi_aclk; // global clock signal.
input m_axi_aresetn; // global reset singal.
//Write address channel
output [IDW-1:0] m_axi_awid; // write address ID
output [31 : 0] m_axi_awaddr; // master interface write address
output [7 : 0] m_axi_awlen; // burst length.
output [2 : 0] m_axi_awsize; // burst size.
output [1 : 0] m_axi_awburst; // burst type.
output [1 : 0] m_axi_awlock; // lock type
output [3 : 0] m_axi_awcache; // memory type.
output [2 : 0] m_axi_awprot; // protection type.
output [3 : 0] m_axi_awqos; // quality of service
output m_axi_awvalid; // write address valid
input m_axi_awready; // write address ready
//Write data channel
output [IDW-1:0] m_axi_wid;
output [63 : 0] m_axi_wdata; // master interface write data.
output [7 : 0] m_axi_wstrb; // byte write strobes
output m_axi_wlast; // indicates last transfer in a write burst.
output m_axi_wvalid; // indicates data is ready to go
input m_axi_wready; // indicates that the slave is ready for data
//Write response channel
input [IDW-1:0] m_axi_bid;
input [1 : 0] m_axi_bresp; // status of the write transaction.
input m_axi_bvalid; // channel is signaling a valid write response
output m_axi_bready; // master can accept write response.
//Read address channel
output [IDW-1:0] m_axi_arid; // read address ID
output [31 : 0] m_axi_araddr; // initial address of a read burst
output [7 : 0] m_axi_arlen; // burst length
output [2 : 0] m_axi_arsize; // burst size
output [1 : 0] m_axi_arburst; // burst type
output [1 : 0] m_axi_arlock; //lock type
output [3 : 0] m_axi_arcache; // memory type
output [2 : 0] m_axi_arprot; // protection type
output [3 : 0] m_axi_arqos; //
output m_axi_arvalid; // valid read address and control information
input m_axi_arready; // slave is ready to accept an address
//Read data channel
input [IDW-1:0] m_axi_rid;
input [63 : 0] m_axi_rdata; // master read data
input [1 : 0] m_axi_rresp; // status of the read transfer
input m_axi_rlast; // signals last transfer in a read burst
input m_axi_rvalid; // signaling the required read data
output m_axi_rready; // master can accept the readback data
//registers
reg [31 : 0] m_axi_awaddr;
reg [7:0] m_axi_awlen;
reg [2:0] m_axi_awsize;
reg m_axi_awvalid;
reg [63 : 0] m_axi_wdata;
reg [7 : 0] m_axi_wstrb;
reg m_axi_wlast;
reg m_axi_wvalid;
reg awvalid_b;
reg [31:0] awaddr_b;
reg [2:0] awsize_b;
reg [7:0] awlen_b;
reg wvalid_b;
reg [63:0] wdata_b;
reg [7:0] wstrb_b;
reg [63 : 0] wdata_aligned;
reg [7 : 0] wstrb_aligned;
reg emrr_access;
reg emrr_access_reg;
reg [31:0] emrr_data;
reg [31:0] emrr_srcaddr;
//wires
wire aw_go;
wire w_go;
wire readinfo_wren;
wire readinfo_rden;
wire readinfo_full;
wire [47:0] readinfo_out;
wire [47:0] readinfo_in;
//i/o connections. write address (aw)
assign m_axi_awburst[1:0] = 2'b01;
assign m_axi_awcache[3:0] = 4'b0010;//TODO??update value to 4'b0011 if coherent accesses to be used via the zynq acp port
assign m_axi_awprot[2:0] = 3'h0;
assign m_axi_awqos[3:0] = 4'h0;
assign m_axi_bready = 1'b1; //TODO? axi_bready, why constant
assign m_axi_arburst[1:0] = 2'b01;
assign m_axi_arcache[3:0] = 4'b0010;
assign m_axi_arprot[2:0] = 3'h0;
assign m_axi_arqos[3:0] = 4'h0;
//--------------------
//write address channel
//--------------------
assign aw_go = m_axi_awvalid & m_axi_awready;
assign w_go = m_axi_wvalid & m_axi_wready;
assign emwr_rd_en = ( emwr_access & ~awvalid_b & ~wvalid_b);
// generate write-address signals
always @( posedge m_axi_aclk )
if(~m_axi_aresetn)
begin
m_axi_awvalid <= 1'b0;
m_axi_awaddr[31:0] <= 32'd0;
m_axi_awlen[7:0] <= 8'd0;
m_axi_awsize[2:0] <= 3'd0;
awvalid_b <= 1'b0;
awaddr_b[31:0] <= 32'd0;
awlen_b[7:0] <= 8'd0;
awsize_b[2:0] <= 3'd0;
end
else
begin
if( ~m_axi_awvalid | aw_go )
begin
if( awvalid_b )
begin
m_axi_awvalid <= 1'b1;
m_axi_awaddr[31:0] <= awaddr_b[31:0];
m_axi_awlen[7:0] <= awlen_b[7:0];
m_axi_awsize[2:0] <= awsize_b[2:0];
end
else
begin
m_axi_awvalid <= emwr_rd_en;
m_axi_awaddr[31:0] <= emwr_dstaddr[31:0];
m_axi_awlen[7:0] <= 8'b0;
m_axi_awsize[2:0] <= { 1'b0, emwr_datamode[1:0]};
end
end
if( emwr_rd_en & m_axi_awvalid & ~aw_go )
awvalid_b <= 1'b1;
else if( aw_go )
awvalid_b <= 1'b0;
//Pipeline stage
if( emwr_rd_en )
begin
awaddr_b[31:0] <= emwr_dstaddr[31:0];
awlen_b[7:0] <= 8'b0;
awsize_b[2:0] <= { 1'b0, emwr_datamode[1:0] };
end
end // else: !if(~m_axi_aresetn)
//--------------------
//write alignment circuit
//--------------------
always @*
case( emwr_datamode[1:0] )
2'd0: wdata_aligned[63:0] = { 8{emwr_data[7:0]}};
2'd1: wdata_aligned[63:0] = { 4{emwr_data[15:0]}};
2'd2: wdata_aligned[63:0] = { 2{emwr_data[31:0]}};
default: wdata_aligned[63:0] = { emwr_srcaddr[31:0], emwr_data[31:0]};
endcase
//TODO: Simplify logic below!!!!!
//Should include separate fields for address/data/datamode!!!!
always @*
begin
case(emwr_datamode[1:0])
2'd0: // byte
case(emwr_dstaddr[2:0])
3'd0: wstrb_aligned[7:0] = 8'h01;
3'd1: wstrb_aligned[7:0] = 8'h02;
3'd2: wstrb_aligned[7:0] = 8'h04;
3'd3: wstrb_aligned[7:0] = 8'h08;
3'd4: wstrb_aligned[7:0] = 8'h10;
3'd5: wstrb_aligned[7:0] = 8'h20;
3'd6: wstrb_aligned[7:0] = 8'h40;
default: wstrb_aligned[7:0] = 8'h80;
endcase
2'd1: // 16b hword
case(emwr_dstaddr[2:1])
2'd0: wstrb_aligned[7:0] = 8'h03;
2'd1: wstrb_aligned[7:0] = 8'h0c;
2'd2: wstrb_aligned[7:0] = 8'h30;
default: wstrb_aligned[7:0] = 8'hc0;
endcase
2'd2: // 32b word
if(emwr_dstaddr[2])
wstrb_aligned[7:0] = 8'hf0;
else
wstrb_aligned[7:0] = 8'h0f;
2'd3:
wstrb_aligned[7:0] = 8'hff;
endcase // case (emwr_datamode[1:0])
end // always @ *
// generate the write-data signals
always @ (posedge m_axi_aclk )
if(~m_axi_aresetn)
begin
m_axi_wvalid <= 1'b0;
m_axi_wdata[63:0] <= 64'b0;
m_axi_wstrb[7:0] <= 8'b0;
m_axi_wlast <= 1'b1; // todo: no bursts for now?
wvalid_b <= 1'b0;
wdata_b[63:0] <= 64'b0;
wstrb_b[7:0] <= 8'b0;
end
else
begin
if( ~m_axi_wvalid | w_go )
begin
if( wvalid_b )
begin
m_axi_wvalid <= 1'b1;
m_axi_wdata[63:0] <= wdata_b[63:0];
m_axi_wstrb[7:0] <= wstrb_b[7:0];
end
else
begin
m_axi_wvalid <= emwr_rd_en;//todo
m_axi_wdata[63:0] <= wdata_aligned[63:0];
m_axi_wstrb[7:0] <= wstrb_aligned[7:0];
end
end // if ( ~axi_wvalid | w_go )
if( emwr_rd_en & m_axi_wvalid & ~w_go )
wvalid_b <= 1'b1;
else if( w_go )
wvalid_b <= 1'b0;
if( emwr_rd_en )
begin
wdata_b[63:0] <= wdata_aligned[63:0];
wstrb_b[7:0] <= wstrb_aligned[7:0];
end
end // else: !if(~m_axi_aresetn)
//----------------------------
// read handler
// elink read requests generate a transaction on the ar channel,
// buffer the src info to generate an elink write when the
// read data comes back.
//----------------------------
//TODO: Can we improve this??
assign readinfo_in[47:0] =
{
7'b0,
emrq_srcaddr[31:0],//40:9
emrq_dstaddr[2:0], //8:6
emrq_ctrlmode[3:0], //5:2
emrq_datamode[1:0]
};
fifo_sync
#(
// parameters
.AW (5),
.DW (48))
fifo_readinfo_i
(
// outputs
.rd_data (readinfo_out[47:0]),
.rd_empty (),
.wr_full (readinfo_full),
// inputs
.clk (m_axi_aclk),
.reset (~m_axi_aresetn),
.wr_data (readinfo_in[47:0]),
.wr_en (emrq_rd_en),
.rd_en (readinfo_rden));
assign emrr_datamode[1:0] = readinfo_out[1:0];
assign emrr_ctrlmode[3:0] = readinfo_out[5:2];
assign emrr_dstaddr[31:0] = readinfo_out[40:9];
//----------------------------
// read address channel
//----------------------------
assign m_axi_araddr[31:0] = emrq_dstaddr[31:0];
assign m_axi_arsize[2:0] = {1'b0, emrq_datamode[1:0]};
assign m_axi_arlen[7:0] = 8'd0;
assign m_axi_arvalid = emrq_access & ~readinfo_full;
assign emrq_rd_en = m_axi_arvalid & m_axi_arready;
//--------------------------------
// read data (and response) channel
//--------------------------------
assign m_axi_rready = ~emrr_progfull;
assign readinfo_rden = ~emrr_progfull & m_axi_rvalid;
assign emrr_write = 1'b1;
always @( posedge m_axi_aclk )
if( ~m_axi_aresetn )
begin
emrr_data[31:0] <= 32'b0;
emrr_srcaddr[31:0] <= 32'b0;
emrr_access_reg <= 1'b0;
emrr_access <= 1'b0;
end
else
begin
emrr_access_reg <= m_axi_rready & m_axi_rvalid;
emrr_access <= emrr_access_reg;//added pipeline stage for data
emrr_srcaddr[31:0] <= m_axi_rdata[63:32];
// steer read data according to size & host address lsbs
//all data needs to be right aligned
//(this is due to the Epiphany right aligning all words)
case(readinfo_out[1:0])//datamode
2'd0: // byte read
case(readinfo_out[8:6])
3'd0: emrr_data[7:0] <= m_axi_rdata[7:0];
3'd1: emrr_data[7:0] <= m_axi_rdata[15:8];
3'd2: emrr_data[7:0] <= m_axi_rdata[23:16];
3'd3: emrr_data[7:0] <= m_axi_rdata[31:24];
3'd4: emrr_data[7:0] <= m_axi_rdata[39:32];
3'd5: emrr_data[7:0] <= m_axi_rdata[47:40];
3'd6: emrr_data[7:0] <= m_axi_rdata[55:48];
default: emrr_data[7:0] <= m_axi_rdata[63:56];
endcase
2'd1: // 16b hword
case( readinfo_out[8:7] )
2'd0: emrr_data[15:0] <= m_axi_rdata[15:0];
2'd1: emrr_data[15:0] <= m_axi_rdata[31:16];
2'd2: emrr_data[15:0] <= m_axi_rdata[47:32];
default: emrr_data[15:0] <= m_axi_rdata[63:48];
endcase
2'd2: // 32b word
if( readinfo_out[8] )
emrr_data[31:0] <= m_axi_rdata[63:32];
else
emrr_data[31:0] <= m_axi_rdata[31:0];
// 64b word already defined by defaults above
2'd3: begin // 64b dword
emrr_data[31:0] <= m_axi_rdata[31:0];
end
endcase
end // else: !if( ~m_axi_aresetn )
endmodule
|
module lp_FIR(aclk, s_axis_data_tvalid, s_axis_data_tready, s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[23:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]" */;
input aclk;
input s_axis_data_tvalid;
output s_axis_data_tready;
input [23:0]s_axis_data_tdata;
output m_axis_data_tvalid;
output [23:0]m_axis_data_tdata;
endmodule
|
module finalproject_keycode (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
module sky130_fd_sc_lp__nor4b_m (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_lp__nor4b_m (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
|
module adder_reg(
input clk,
input [7:0] x,
input [7:0] y,
input carry_in,
output carry_output_bit,
output [7:0] sum
);
reg [8:0] full_sum_reg;
reg [7:0] x_reg;
reg [7:0] y_reg;
reg carry_in_reg;
assign carry_output_bit = full_sum_reg[8];
assign sum = full_sum_reg[7:0];
always @(posedge clk)
begin
x_reg <= x;
y_reg <= y;
carry_in_reg <= carry_in;
full_sum_reg <= x_reg + y_reg + carry_in_reg;
end
endmodule
|
module encoder43table(A, B, C, D, Y2, Y1, Y0);
input A, B, C, D;
output reg Y2, Y1, Y0;
always@(A, B, C, D)
case({A, B, C, D})
4'b0000: {Y2, Y1, Y0} = 3'b000;
4'b0001: {Y2, Y1, Y0} = 3'b001;
4'b0010: {Y2, Y1, Y0} = 3'b001;
4'b0011: {Y2, Y1, Y0} = 3'b010;
4'b0100: {Y2, Y1, Y0} = 3'b001;
4'b0101: {Y2, Y1, Y0} = 3'b010;
4'b0110: {Y2, Y1, Y0} = 3'b010;
4'b0111: {Y2, Y1, Y0} = 3'b011;
4'b1000: {Y2, Y1, Y0} = 3'b001;
4'b1001: {Y2, Y1, Y0} = 3'b010;
4'b1010: {Y2, Y1, Y0} = 3'b010;
4'b1011: {Y2, Y1, Y0} = 3'b011;
4'b1100: {Y2, Y1, Y0} = 3'b010;
4'b1101: {Y2, Y1, Y0} = 3'b011;
4'b1110: {Y2, Y1, Y0} = 3'b011;
4'b1111: {Y2, Y1, Y0} = 3'b100;
endcase
endmodule
|
module axi_slave_impl_testbench #
(
parameter integer NUMBER_OF_REGISTERS = 6,
parameter integer C_S_AXI_DATA_WIDTH = 32,
parameter integer C_S_AXI_ADDR_WIDTH = 10
)
(
input wire [1:0] register_operation, // 1 - read, 2 - write, 3 - complete
input wire [7 : 0] register_number,
input wire [C_S_AXI_DATA_WIDTH -1 : 0] register_write,
output wire [C_S_AXI_DATA_WIDTH -1 : 0] register_read,
input wire S_AXI_ACLK,
input wire S_AXI_ARESETN,
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
input wire [2 : 0] S_AXI_AWPROT,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
output wire [1 : 0] S_AXI_BRESP,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
input wire [2 : 0] S_AXI_ARPROT,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
output wire [1 : 0] S_AXI_RRESP,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY
);
axi_slave_impl # (
.C_S_AXI_DATA_WIDTH(C_S_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S_AXI_ADDR_WIDTH),
.NUMBER_OF_REGISTERS(NUMBER_OF_REGISTERS)
) testing_axi_slave_impl (
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARESETN(S_AXI_ARESETN),
.S_AXI_AWADDR(S_AXI_AWADDR),
.S_AXI_AWPROT(S_AXI_AWPROT),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_WDATA(S_AXI_WDATA),
.S_AXI_WSTRB(S_AXI_WSTRB),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BRESP(S_AXI_BRESP),
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_ARADDR(S_AXI_ARADDR),
.S_AXI_ARPROT(S_AXI_ARPROT),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RDATA(S_AXI_RDATA),
.S_AXI_RRESP(S_AXI_RRESP),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
.register_operation(register_operation),
.register_number(register_number),
.register_read(register_read),
.register_write(register_write)
);
endmodule
|
module udp_outbound_chain_rx
(input clk_50,
input clk_100,
input [7:0] rxd,
input rxdv,
input rxlast, // fires HIGH when udp_rx verifies the checksum
output [15:0] hop_count,
output [7:0] submsg_rxd,
output submsg_rxdv,
output submsg_rxlast);
// buffer the incoming packet here until we get an rxlast signal, which
// indicates the UDP packet was sane.
wire [7:0] qrxd;
wire qrxdv, qrxlast;
udp_rxq udp_rxq_inst(.clk(clk_50), .rxd(rxd), .rxdv(rxdv), .rxlast(rxlast),
.qrxd(qrxd), .qrxdv(qrxdv), .qrxlast(qrxlast));
//////////////////////////////////////////////////////////////////////////
localparam SW = 5, CW = 5;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r
(.c(clk_50), .rst(1'b0), .en(1'b1), .d(next_state), .q(state));
localparam ST_IDLE = 5'h0;
localparam ST_PROTO_VER = 5'h1;
localparam ST_HOP_COUNT = 5'h2;
localparam ST_SUBMSG_ADDR = 5'h3;
localparam ST_SUBMSG_LEN = 5'h4;
localparam ST_SUBMSG_PAYLOAD = 5'h5;
localparam ST_SUBMSG_WAIT_FOR_RXLAST = 5'h6; // wait for pad + CRC check
localparam ST_MFIFO_DRAIN = 5'h7; // send rx submsg to rest of chip
localparam ST_DISCARD = 5'h8; // bogus
wire rx_cnt_rst;
wire [10:0] rx_cnt;
r #(11) rx_cnt_r
(.c(clk_50), .rst(rx_cnt_rst), .en(1'b1), .d(rx_cnt+1'b1), .q(rx_cnt));
assign rx_cnt_rst = ctrl[0];
wire [7:0] rxd_d1;
d1 #(8) rxd_d1_r(.c(clk_50), .d(qrxd), .q(rxd_d1));
wire [15:0] rx_16bit = { qrxd, rxd_d1 };
r #(16) hop_count_r
(.c(clk_50), .rst(1'b0), .en(state == ST_HOP_COUNT),
.d(rx_16bit), .q(hop_count));
wire [15:0] submsg_addr;
r #(16) submsg_addr_r
(.c(clk_50), .rst(1'b0), .en(state == ST_SUBMSG_ADDR),
.d(rx_16bit), .q(submsg_addr));
wire [15:0] submsg_len;
r #(16) submsg_len_r
(.c(clk_50), .rst(1'b0), .en(state == ST_SUBMSG_LEN), .d(rx_16bit), .q(submsg_len));
wire submsg_received;
wire wire_submsg_rxdv = ~submsg_received & qrxdv &
hop_count == submsg_addr &
state == ST_SUBMSG_PAYLOAD;
wire [7:0] wire_submsg_rxd = qrxd;
wire wire_submsg_rxdv_d1;
d1 wire_submsg_rxdv_d1_r(.c(clk_50), .d(wire_submsg_rxdv), .q(wire_submsg_rxdv_d1));
r submsg_received_r
(.c(clk_50), .rst(state == ST_IDLE),
.en(wire_submsg_rxdv_d1 & ~wire_submsg_rxdv),
.d(1'b1), .q(submsg_received));
wire rx_rxlast;
r rx_rxlast_r
(.c(clk_50), .rst(state == ST_IDLE), .en(qrxlast), .d(1'b1), .q(rx_rxlast));
wire mfifo_almost_empty;
always @* begin
case (state)
ST_IDLE:
if (qrxdv) ctrl = { ST_PROTO_VER , 5'b00000 };
else ctrl = { ST_IDLE , 5'b00001 };
ST_PROTO_VER:
if (~qrxdv) ctrl = { ST_IDLE , 5'b00000 };
else if (rx_16bit == 16'h4321)ctrl = { ST_HOP_COUNT , 5'b00001 };
else ctrl = { ST_DISCARD , 5'b00000 };
ST_HOP_COUNT:
if (~qrxdv) ctrl = { ST_IDLE , 5'b00000 };
else if (rx_cnt == 16'h1) ctrl = { ST_SUBMSG_ADDR, 5'b00001 };
else ctrl = { ST_HOP_COUNT , 5'b00000 };
ST_SUBMSG_ADDR:
if (~qrxdv) ctrl = { ST_SUBMSG_WAIT_FOR_RXLAST, 5'b00001 };
else if (rx_cnt == 16'h1) ctrl = { ST_SUBMSG_LEN , 5'b00001 };
else ctrl = { ST_SUBMSG_ADDR, 5'b00000 };
ST_SUBMSG_LEN:
if (~qrxdv) ctrl = { ST_SUBMSG_WAIT_FOR_RXLAST, 5'b00001 };
else if (rx_cnt == 16'h1) ctrl = { ST_SUBMSG_PAYLOAD, 5'b00001 };
else ctrl = { ST_SUBMSG_LEN , 5'b00000 };
ST_SUBMSG_PAYLOAD:
if (~qrxdv) ctrl = { ST_SUBMSG_WAIT_FOR_RXLAST, 5'b00001 };
else if (rx_cnt + 1'b1 == submsg_len)
ctrl = { ST_SUBMSG_ADDR , 5'b00001 };
else ctrl = { ST_SUBMSG_PAYLOAD, 5'b00000 };
ST_SUBMSG_WAIT_FOR_RXLAST:
if (~submsg_received) ctrl = { ST_MFIFO_DRAIN , 5'b00000 };
else if (qrxlast) ctrl = { ST_MFIFO_DRAIN , 5'b00000 };
else if (rx_cnt == 16'h30) ctrl = { ST_MFIFO_DRAIN , 5'b00000 };
else ctrl = { ST_SUBMSG_WAIT_FOR_RXLAST, 5'b00000 };
ST_MFIFO_DRAIN:
if (mfifo_drained) ctrl = { ST_IDLE , 5'b00000 };
else ctrl = { ST_MFIFO_DRAIN , 5'b00000 };
ST_DISCARD:
if (~qrxdv) ctrl = { ST_IDLE , 5'b00000 };
else ctrl = { ST_DISCARD , 5'b00000 };
default: ctrl = { ST_IDLE , 5'b00000 };
endcase
end
wire mfifo_empty;
wire mfifo_draining;
wire [10:0] mfifo_rdusedw;
dcfifo #(.lpm_width(8),
.lpm_numwords(2048),
.lpm_widthu(11),
.lpm_showahead("ON"),
.use_eab("ON"),
.intended_device_family("CYCLONE V")) mfifo // submessage fifo
(.wrclk(clk_50), .wrreq(wire_submsg_rxdv), .data(wire_submsg_rxd),
.rdclk(clk_100), .rdreq(mfifo_draining & ~mfifo_empty), .q(submsg_rxd),
.rdempty(mfifo_empty),
.rdusedw(mfifo_rdusedw),
.aclr(1'b0));
wire submsg_received_clk100;
sync submsg_received_sync_r(.in(submsg_received), .clk(clk_100), .out(submsg_received_clk100));
wire mfifo_drained;
sync mfifo_drained_sync_r
(.in(mfifo_empty), .clk(clk_50), .out(mfifo_drained));
wire mfifo_drain_req_clk100;
sync mfifo_drain_req_sync_r
(.in(state == ST_MFIFO_DRAIN), .clk(clk_100), .out(mfifo_drain_req_clk100));
r mfifo_draining_r
(.c(clk_100), .rst(mfifo_empty), .d(1'b1), .q(mfifo_draining),
.en(mfifo_drain_req_clk100));
assign submsg_rxdv = mfifo_draining & submsg_received_clk100 & ~mfifo_empty;
assign submsg_rxlast = mfifo_draining & submsg_received_clk100 & mfifo_rdusedw == 11'h2;
endmodule
|
module udp_outbound_chain_rx_tb();
wire clk_100, clk_50;
sim_clk #(100) clk_100_inst(clk_100);
sim_clk #( 50) clk_50_inst (clk_50 );
reg [7:0] rxd;
reg rxdv;
reg rxlast;
wire [7:0] submsg_rxd;
wire submsg_rxdv;
wire submsg_rxlast;
udp_outbound_chain_rx dut(.*);
localparam PKT_LEN = 16;
reg [7:0] pkt [PKT_LEN-1:0];
integer i;
initial begin
$dumpfile("udp_outbound_chain_rx.lxt");
$dumpvars();
pkt[0] = 8'h1; // protocol low
pkt[1] = 8'h0; // protocol high
pkt[2] = 8'h0; // hop count low
pkt[3] = 8'h0; // hop count high
pkt[4] = 8'h0; // submsg addr low
pkt[5] = 8'h0; // submsg addr high
pkt[6] = 8'h2; // submsg len low
pkt[7] = 8'h0; // submsg len high
pkt[8] = 8'h12; // payload byte 0
pkt[9] = 8'h34; // payload byte 1
////
pkt[10] = 8'h1; // submsg addr low
pkt[11] = 8'h0; // submsg addr high
pkt[12] = 8'h2; // submsg len low
pkt[13] = 8'h0; // submsg len high
pkt[14] = 8'h56; // payload byte 0
pkt[15] = 8'h78; // payload byte 1
////
rxd = 1'b0;
rxdv = 8'h0;
rxlast = 1'b0;
#100;
wait(~clk_50);
wait(clk_50);
rxdv <= 1'b1;
for (i = 0; i < PKT_LEN; i = i + 1) begin
rxd <= pkt[i];
if (i == PKT_LEN - 1)
rxlast = 1;
wait(~clk_50);
wait(clk_50);
end
rxdv = 1'b0;
rxd = 8'h0;
rxlast = 1'b0;
#2000;
$finish();
end
endmodule
|
module invert_float_float (
// aclk, aclken, s_axis_a_tvalid, m_axis_result_tvalid, s_axis_a_tdata, m_axis_result_tdata
CLK, ce, inp, out
);
// input aclk;
parameter INSTANCE_NAME="INST";
input wire CLK;
input wire ce;
input [31 : 0] inp;
output [31 : 0] out;
// input aclken;
// input s_axis_a_tvalid;
//output m_axis_result_tvalid;
// input [31 : 0] s_axis_a_tdata;
// output [31 : 0] m_axis_result_tdata;
wire aclk;
assign aclk = CLK;
wire aclken;
assign aclken = ce;
wire s_axis_a_tvalid;
assign s_axis_a_tvalid = 1'b1;
wire m_axis_result_tvalid;
wire [31:0] s_axis_a_tdata;
assign s_axis_a_tdata = inp;
wire [31:0] m_axis_result_tdata;
assign out = m_axis_result_tdata;
wire \blk00000001/sig000002cb ;
wire \blk00000001/sig000002ca ;
wire \blk00000001/sig000002c9 ;
wire \blk00000001/sig000002c8 ;
wire \blk00000001/sig000002c7 ;
wire \blk00000001/sig000002c6 ;
wire \blk00000001/sig000002c5 ;
wire \blk00000001/sig000002c4 ;
wire \blk00000001/sig000002c3 ;
wire \blk00000001/sig000002c2 ;
wire \blk00000001/sig000002c1 ;
wire \blk00000001/sig000002c0 ;
wire \blk00000001/sig000002bf ;
wire \blk00000001/sig000002be ;
wire \blk00000001/sig000002bd ;
wire \blk00000001/sig000002bc ;
wire \blk00000001/sig000002bb ;
wire \blk00000001/sig000002ba ;
wire \blk00000001/sig000002b9 ;
wire \blk00000001/sig000002b8 ;
wire \blk00000001/sig000002b7 ;
wire \blk00000001/sig000002b6 ;
wire \blk00000001/sig000002b5 ;
wire \blk00000001/sig000002b4 ;
wire \blk00000001/sig000002b3 ;
wire \blk00000001/sig000002b2 ;
wire \blk00000001/sig000002b1 ;
wire \blk00000001/sig000002b0 ;
wire \blk00000001/sig000002af ;
wire \blk00000001/sig000002ae ;
wire \blk00000001/sig000002ad ;
wire \blk00000001/sig000002ac ;
wire \blk00000001/sig000002ab ;
wire \blk00000001/sig000002aa ;
wire \blk00000001/sig000002a9 ;
wire \blk00000001/sig000002a8 ;
wire \blk00000001/sig000002a7 ;
wire \blk00000001/sig000002a6 ;
wire \blk00000001/sig000002a5 ;
wire \blk00000001/sig000002a4 ;
wire \blk00000001/sig000002a3 ;
wire \blk00000001/sig000002a2 ;
wire \blk00000001/sig000002a1 ;
wire \blk00000001/sig000002a0 ;
wire \blk00000001/sig0000029f ;
wire \blk00000001/sig0000029e ;
wire \blk00000001/sig0000029d ;
wire \blk00000001/sig0000029c ;
wire \blk00000001/sig0000029b ;
wire \blk00000001/sig0000029a ;
wire \blk00000001/sig00000299 ;
wire \blk00000001/sig00000298 ;
wire \blk00000001/sig00000297 ;
wire \blk00000001/sig00000296 ;
wire \blk00000001/sig00000295 ;
wire \blk00000001/sig00000294 ;
wire \blk00000001/sig00000293 ;
wire \blk00000001/sig00000292 ;
wire \blk00000001/sig00000291 ;
wire \blk00000001/sig00000290 ;
wire \blk00000001/sig0000028f ;
wire \blk00000001/sig0000028e ;
wire \blk00000001/sig0000028d ;
wire \blk00000001/sig0000028c ;
wire \blk00000001/sig0000028b ;
wire \blk00000001/sig0000028a ;
wire \blk00000001/sig00000289 ;
wire \blk00000001/sig00000288 ;
wire \blk00000001/sig00000287 ;
wire \blk00000001/sig00000286 ;
wire \blk00000001/sig00000285 ;
wire \blk00000001/sig00000284 ;
wire \blk00000001/sig00000283 ;
wire \blk00000001/sig00000282 ;
wire \blk00000001/sig00000281 ;
wire \blk00000001/sig00000280 ;
wire \blk00000001/sig0000027f ;
wire \blk00000001/sig0000027e ;
wire \blk00000001/sig0000027d ;
wire \blk00000001/sig0000027c ;
wire \blk00000001/sig0000027b ;
wire \blk00000001/sig0000027a ;
wire \blk00000001/sig00000279 ;
wire \blk00000001/sig00000278 ;
wire \blk00000001/sig00000277 ;
wire \blk00000001/sig00000276 ;
wire \blk00000001/sig00000275 ;
wire \blk00000001/sig00000274 ;
wire \blk00000001/sig00000273 ;
wire \blk00000001/sig00000272 ;
wire \blk00000001/sig00000271 ;
wire \blk00000001/sig00000270 ;
wire \blk00000001/sig0000026f ;
wire \blk00000001/sig0000026e ;
wire \blk00000001/sig0000026d ;
wire \blk00000001/sig0000026c ;
wire \blk00000001/sig0000026b ;
wire \blk00000001/sig0000026a ;
wire \blk00000001/sig00000269 ;
wire \blk00000001/sig00000268 ;
wire \blk00000001/sig00000267 ;
wire \blk00000001/sig00000266 ;
wire \blk00000001/sig00000265 ;
wire \blk00000001/sig00000264 ;
wire \blk00000001/sig00000263 ;
wire \blk00000001/sig00000262 ;
wire \blk00000001/sig00000261 ;
wire \blk00000001/sig00000260 ;
wire \blk00000001/sig0000025f ;
wire \blk00000001/sig0000025e ;
wire \blk00000001/sig0000025d ;
wire \blk00000001/sig0000025c ;
wire \blk00000001/sig0000025b ;
wire \blk00000001/sig0000025a ;
wire \blk00000001/sig00000259 ;
wire \blk00000001/sig00000258 ;
wire \blk00000001/sig00000257 ;
wire \blk00000001/sig00000256 ;
wire \blk00000001/sig00000255 ;
wire \blk00000001/sig00000254 ;
wire \blk00000001/sig00000253 ;
wire \blk00000001/sig00000252 ;
wire \blk00000001/sig00000251 ;
wire \blk00000001/sig00000250 ;
wire \blk00000001/sig0000024f ;
wire \blk00000001/sig0000024e ;
wire \blk00000001/sig0000024d ;
wire \blk00000001/sig0000024c ;
wire \blk00000001/sig0000024b ;
wire \blk00000001/sig0000024a ;
wire \blk00000001/sig00000249 ;
wire \blk00000001/sig00000248 ;
wire \blk00000001/sig00000247 ;
wire \blk00000001/sig00000246 ;
wire \blk00000001/sig00000245 ;
wire \blk00000001/sig00000244 ;
wire \blk00000001/sig00000243 ;
wire \blk00000001/sig00000242 ;
wire \blk00000001/sig00000241 ;
wire \blk00000001/sig00000240 ;
wire \blk00000001/sig0000023f ;
wire \blk00000001/sig0000023e ;
wire \blk00000001/sig0000023d ;
wire \blk00000001/sig0000023c ;
wire \blk00000001/sig0000023b ;
wire \blk00000001/sig0000023a ;
wire \blk00000001/sig00000239 ;
wire \blk00000001/sig00000238 ;
wire \blk00000001/sig00000237 ;
wire \blk00000001/sig00000236 ;
wire \blk00000001/sig00000235 ;
wire \blk00000001/sig00000234 ;
wire \blk00000001/sig00000233 ;
wire \blk00000001/sig00000232 ;
wire \blk00000001/sig00000231 ;
wire \blk00000001/sig00000230 ;
wire \blk00000001/sig0000022f ;
wire \blk00000001/sig0000022e ;
wire \blk00000001/sig0000022d ;
wire \blk00000001/sig0000022c ;
wire \blk00000001/sig0000022b ;
wire \blk00000001/sig0000022a ;
wire \blk00000001/sig00000229 ;
wire \blk00000001/sig00000228 ;
wire \blk00000001/sig00000227 ;
wire \blk00000001/sig00000226 ;
wire \blk00000001/sig00000225 ;
wire \blk00000001/sig00000224 ;
wire \blk00000001/sig00000223 ;
wire \blk00000001/sig00000222 ;
wire \blk00000001/sig00000221 ;
wire \blk00000001/sig00000220 ;
wire \blk00000001/sig0000021f ;
wire \blk00000001/sig0000021e ;
wire \blk00000001/sig0000021d ;
wire \blk00000001/sig0000021c ;
wire \blk00000001/sig0000021b ;
wire \blk00000001/sig0000021a ;
wire \blk00000001/sig00000219 ;
wire \blk00000001/sig00000218 ;
wire \blk00000001/sig00000217 ;
wire \blk00000001/sig00000216 ;
wire \blk00000001/sig00000215 ;
wire \blk00000001/sig00000214 ;
wire \blk00000001/sig00000213 ;
wire \blk00000001/sig00000212 ;
wire \blk00000001/sig00000211 ;
wire \blk00000001/sig00000210 ;
wire \blk00000001/sig0000020f ;
wire \blk00000001/sig0000020e ;
wire \blk00000001/sig0000020d ;
wire \blk00000001/sig0000020c ;
wire \blk00000001/sig0000020b ;
wire \blk00000001/sig0000020a ;
wire \blk00000001/sig00000209 ;
wire \blk00000001/sig00000208 ;
wire \blk00000001/sig00000207 ;
wire \blk00000001/sig00000206 ;
wire \blk00000001/sig00000205 ;
wire \blk00000001/sig00000204 ;
wire \blk00000001/sig00000203 ;
wire \blk00000001/sig00000202 ;
wire \blk00000001/sig00000201 ;
wire \blk00000001/sig00000200 ;
wire \blk00000001/sig000001ff ;
wire \blk00000001/sig000001fe ;
wire \blk00000001/sig000001fd ;
wire \blk00000001/sig000001fc ;
wire \blk00000001/sig000001fb ;
wire \blk00000001/sig000001fa ;
wire \blk00000001/sig000001f9 ;
wire \blk00000001/sig000001f8 ;
wire \blk00000001/sig000001f7 ;
wire \blk00000001/sig000001f6 ;
wire \blk00000001/sig000001f5 ;
wire \blk00000001/sig000001f4 ;
wire \blk00000001/sig000001f3 ;
wire \blk00000001/sig000001f2 ;
wire \blk00000001/sig000001f1 ;
wire \blk00000001/sig000001f0 ;
wire \blk00000001/sig000001ef ;
wire \blk00000001/sig000001ee ;
wire \blk00000001/sig000001ed ;
wire \blk00000001/sig000001ec ;
wire \blk00000001/sig000001eb ;
wire \blk00000001/sig000001ea ;
wire \blk00000001/sig000001e9 ;
wire \blk00000001/sig000001e8 ;
wire \blk00000001/sig000001e7 ;
wire \blk00000001/sig000001e6 ;
wire \blk00000001/sig000001e5 ;
wire \blk00000001/sig000001e4 ;
wire \blk00000001/sig000001e3 ;
wire \blk00000001/sig000001e2 ;
wire \blk00000001/sig000001e1 ;
wire \blk00000001/sig000001e0 ;
wire \blk00000001/sig000001df ;
wire \blk00000001/sig000001de ;
wire \blk00000001/sig000001dd ;
wire \blk00000001/sig000001dc ;
wire \blk00000001/sig000001db ;
wire \blk00000001/sig000001da ;
wire \blk00000001/sig000001d9 ;
wire \blk00000001/sig000001d8 ;
wire \blk00000001/sig000001d7 ;
wire \blk00000001/sig000001d6 ;
wire \blk00000001/sig000001d5 ;
wire \blk00000001/sig000001d4 ;
wire \blk00000001/sig000001d3 ;
wire \blk00000001/sig000001d2 ;
wire \blk00000001/sig000001d1 ;
wire \blk00000001/sig000001d0 ;
wire \blk00000001/sig000001cf ;
wire \blk00000001/sig000001ce ;
wire \blk00000001/sig000001cd ;
wire \blk00000001/sig000001cc ;
wire \blk00000001/sig000001cb ;
wire \blk00000001/sig000001ca ;
wire \blk00000001/sig000001c9 ;
wire \blk00000001/sig000001c8 ;
wire \blk00000001/sig000001c7 ;
wire \blk00000001/sig000001c6 ;
wire \blk00000001/sig000001c5 ;
wire \blk00000001/sig000001c4 ;
wire \blk00000001/sig000001c3 ;
wire \blk00000001/sig000001c2 ;
wire \blk00000001/sig000001c1 ;
wire \blk00000001/sig000001c0 ;
wire \blk00000001/sig000001bf ;
wire \blk00000001/sig000001be ;
wire \blk00000001/sig000001bd ;
wire \blk00000001/sig000001bc ;
wire \blk00000001/sig000001bb ;
wire \blk00000001/sig000001ba ;
wire \blk00000001/sig000001b9 ;
wire \blk00000001/sig000001b8 ;
wire \blk00000001/sig000001b7 ;
wire \blk00000001/sig000001b6 ;
wire \blk00000001/sig000001b5 ;
wire \blk00000001/sig000001b4 ;
wire \blk00000001/sig000001b3 ;
wire \blk00000001/sig000001b2 ;
wire \blk00000001/sig000001b1 ;
wire \blk00000001/sig000001b0 ;
wire \blk00000001/sig000001af ;
wire \blk00000001/sig000001ae ;
wire \blk00000001/sig000001ad ;
wire \blk00000001/sig000001ac ;
wire \blk00000001/sig000001ab ;
wire \blk00000001/sig000001aa ;
wire \blk00000001/sig000001a9 ;
wire \blk00000001/sig000001a8 ;
wire \blk00000001/sig000001a7 ;
wire \blk00000001/sig000001a6 ;
wire \blk00000001/sig000001a5 ;
wire \blk00000001/sig000001a4 ;
wire \blk00000001/sig000001a3 ;
wire \blk00000001/sig000001a2 ;
wire \blk00000001/sig000001a1 ;
wire \blk00000001/sig000001a0 ;
wire \blk00000001/sig0000019f ;
wire \blk00000001/sig0000019e ;
wire \blk00000001/sig0000019d ;
wire \blk00000001/sig0000019c ;
wire \blk00000001/sig0000019b ;
wire \blk00000001/sig0000019a ;
wire \blk00000001/sig00000199 ;
wire \blk00000001/sig00000198 ;
wire \blk00000001/sig00000197 ;
wire \blk00000001/sig00000196 ;
wire \blk00000001/sig00000195 ;
wire \blk00000001/sig00000194 ;
wire \blk00000001/sig00000193 ;
wire \blk00000001/sig00000192 ;
wire \blk00000001/sig00000191 ;
wire \blk00000001/sig00000190 ;
wire \blk00000001/sig0000018f ;
wire \blk00000001/sig0000018e ;
wire \blk00000001/sig0000018d ;
wire \blk00000001/sig0000018c ;
wire \blk00000001/sig0000018b ;
wire \blk00000001/sig0000018a ;
wire \blk00000001/sig00000189 ;
wire \blk00000001/sig00000188 ;
wire \blk00000001/sig00000187 ;
wire \blk00000001/sig00000186 ;
wire \blk00000001/sig00000185 ;
wire \blk00000001/sig00000184 ;
wire \blk00000001/sig00000183 ;
wire \blk00000001/sig00000182 ;
wire \blk00000001/sig00000181 ;
wire \blk00000001/sig00000180 ;
wire \blk00000001/sig0000017f ;
wire \blk00000001/sig0000017e ;
wire \blk00000001/sig0000017d ;
wire \blk00000001/sig0000017c ;
wire \blk00000001/sig0000017b ;
wire \blk00000001/sig0000017a ;
wire \blk00000001/sig00000179 ;
wire \blk00000001/sig00000178 ;
wire \blk00000001/sig00000177 ;
wire \blk00000001/sig00000176 ;
wire \blk00000001/sig00000175 ;
wire \blk00000001/sig00000174 ;
wire \blk00000001/sig00000173 ;
wire \blk00000001/sig00000172 ;
wire \blk00000001/sig00000171 ;
wire \blk00000001/sig00000170 ;
wire \blk00000001/sig0000016f ;
wire \blk00000001/sig0000016e ;
wire \blk00000001/sig0000016d ;
wire \blk00000001/sig0000016c ;
wire \blk00000001/sig0000016b ;
wire \blk00000001/sig0000016a ;
wire \blk00000001/sig00000169 ;
wire \blk00000001/sig00000168 ;
wire \blk00000001/sig00000167 ;
wire \blk00000001/sig00000166 ;
wire \blk00000001/sig00000165 ;
wire \blk00000001/sig00000164 ;
wire \blk00000001/sig00000163 ;
wire \blk00000001/sig00000162 ;
wire \blk00000001/sig00000161 ;
wire \blk00000001/sig00000160 ;
wire \blk00000001/sig0000015f ;
wire \blk00000001/sig0000015e ;
wire \blk00000001/sig0000015d ;
wire \blk00000001/sig0000015c ;
wire \blk00000001/sig0000015b ;
wire \blk00000001/sig0000015a ;
wire \blk00000001/sig00000159 ;
wire \blk00000001/sig00000158 ;
wire \blk00000001/sig00000157 ;
wire \blk00000001/sig00000156 ;
wire \blk00000001/sig00000155 ;
wire \blk00000001/sig00000154 ;
wire \blk00000001/sig00000153 ;
wire \blk00000001/sig00000152 ;
wire \blk00000001/sig00000151 ;
wire \blk00000001/sig00000150 ;
wire \blk00000001/sig0000014f ;
wire \blk00000001/sig0000014e ;
wire \blk00000001/sig0000014d ;
wire \blk00000001/sig0000014c ;
wire \blk00000001/sig0000014b ;
wire \blk00000001/sig0000014a ;
wire \blk00000001/sig00000149 ;
wire \blk00000001/sig00000148 ;
wire \blk00000001/sig00000147 ;
wire \blk00000001/sig00000146 ;
wire \blk00000001/sig00000145 ;
wire \blk00000001/sig00000144 ;
wire \blk00000001/sig00000143 ;
wire \blk00000001/sig00000142 ;
wire \blk00000001/sig00000141 ;
wire \blk00000001/sig00000140 ;
wire \blk00000001/sig0000013f ;
wire \blk00000001/sig0000013e ;
wire \blk00000001/sig0000013d ;
wire \blk00000001/sig0000013c ;
wire \blk00000001/sig0000013b ;
wire \blk00000001/sig0000013a ;
wire \blk00000001/sig00000139 ;
wire \blk00000001/sig00000138 ;
wire \blk00000001/sig00000137 ;
wire \blk00000001/sig00000136 ;
wire \blk00000001/sig00000135 ;
wire \blk00000001/sig00000134 ;
wire \blk00000001/sig00000133 ;
wire \blk00000001/sig00000132 ;
wire \blk00000001/sig00000131 ;
wire \blk00000001/sig00000130 ;
wire \blk00000001/sig0000012f ;
wire \blk00000001/sig0000012e ;
wire \blk00000001/sig0000012d ;
wire \blk00000001/sig0000012c ;
wire \blk00000001/sig0000012b ;
wire \blk00000001/sig0000012a ;
wire \blk00000001/sig00000129 ;
wire \blk00000001/sig00000128 ;
wire \blk00000001/sig00000127 ;
wire \blk00000001/sig00000126 ;
wire \blk00000001/sig00000125 ;
wire \blk00000001/sig00000124 ;
wire \blk00000001/sig00000123 ;
wire \blk00000001/sig00000122 ;
wire \blk00000001/sig00000121 ;
wire \blk00000001/sig00000120 ;
wire \blk00000001/sig0000011f ;
wire \blk00000001/sig0000011e ;
wire \blk00000001/sig0000011d ;
wire \blk00000001/sig0000011c ;
wire \blk00000001/sig0000011b ;
wire \blk00000001/sig0000011a ;
wire \blk00000001/sig00000119 ;
wire \blk00000001/sig00000118 ;
wire \blk00000001/sig00000117 ;
wire \blk00000001/sig00000116 ;
wire \blk00000001/sig00000115 ;
wire \blk00000001/sig00000114 ;
wire \blk00000001/sig00000113 ;
wire \blk00000001/sig00000112 ;
wire \blk00000001/sig00000111 ;
wire \blk00000001/sig00000110 ;
wire \blk00000001/sig0000010f ;
wire \blk00000001/sig0000010e ;
wire \blk00000001/sig0000010d ;
wire \blk00000001/sig0000010c ;
wire \blk00000001/sig0000010b ;
wire \blk00000001/sig0000010a ;
wire \blk00000001/sig00000109 ;
wire \blk00000001/sig00000108 ;
wire \blk00000001/sig00000107 ;
wire \blk00000001/sig00000106 ;
wire \blk00000001/sig00000105 ;
wire \blk00000001/sig00000104 ;
wire \blk00000001/sig00000103 ;
wire \blk00000001/sig00000102 ;
wire \blk00000001/sig00000101 ;
wire \blk00000001/sig00000100 ;
wire \blk00000001/sig000000ff ;
wire \blk00000001/sig000000fe ;
wire \blk00000001/sig000000fd ;
wire \blk00000001/sig000000fc ;
wire \blk00000001/sig000000fb ;
wire \blk00000001/sig000000fa ;
wire \blk00000001/sig000000f9 ;
wire \blk00000001/sig000000f8 ;
wire \blk00000001/sig000000f7 ;
wire \blk00000001/sig000000f6 ;
wire \blk00000001/sig000000f5 ;
wire \blk00000001/sig000000f4 ;
wire \blk00000001/sig000000f3 ;
wire \blk00000001/sig000000f2 ;
wire \blk00000001/sig000000f1 ;
wire \blk00000001/sig000000f0 ;
wire \blk00000001/sig000000ef ;
wire \blk00000001/sig000000ee ;
wire \blk00000001/sig000000ed ;
wire \blk00000001/sig000000ec ;
wire \blk00000001/sig000000eb ;
wire \blk00000001/sig000000ea ;
wire \blk00000001/sig000000e9 ;
wire \blk00000001/sig000000e8 ;
wire \blk00000001/sig000000e7 ;
wire \blk00000001/sig000000e6 ;
wire \blk00000001/sig000000e5 ;
wire \blk00000001/sig000000e4 ;
wire \blk00000001/sig000000e3 ;
wire \blk00000001/sig000000e2 ;
wire \blk00000001/sig000000e1 ;
wire \blk00000001/sig000000e0 ;
wire \blk00000001/sig000000df ;
wire \blk00000001/sig000000de ;
wire \blk00000001/sig000000dd ;
wire \blk00000001/sig000000dc ;
wire \blk00000001/sig000000db ;
wire \blk00000001/sig000000da ;
wire \blk00000001/sig000000d9 ;
wire \blk00000001/sig000000d8 ;
wire \blk00000001/sig000000d7 ;
wire \blk00000001/sig000000d6 ;
wire \blk00000001/sig000000d5 ;
wire \blk00000001/sig000000d4 ;
wire \blk00000001/sig000000d3 ;
wire \blk00000001/sig000000d2 ;
wire \blk00000001/sig000000d1 ;
wire \blk00000001/sig000000d0 ;
wire \blk00000001/sig000000cf ;
wire \blk00000001/sig000000ce ;
wire \blk00000001/sig000000cd ;
wire \blk00000001/sig000000cc ;
wire \blk00000001/sig000000cb ;
wire \blk00000001/sig000000ca ;
wire \blk00000001/sig000000c9 ;
wire \blk00000001/sig000000c8 ;
wire \blk00000001/sig000000c7 ;
wire \blk00000001/sig000000c6 ;
wire \blk00000001/sig000000c5 ;
wire \blk00000001/sig000000c4 ;
wire \blk00000001/sig000000c3 ;
wire \blk00000001/sig000000c2 ;
wire \blk00000001/sig000000c1 ;
wire \blk00000001/sig000000c0 ;
wire \blk00000001/sig000000bf ;
wire \blk00000001/sig000000be ;
wire \blk00000001/sig000000bd ;
wire \blk00000001/sig000000bc ;
wire \blk00000001/sig000000bb ;
wire \blk00000001/sig000000ba ;
wire \blk00000001/sig000000b9 ;
wire \blk00000001/sig000000b8 ;
wire \blk00000001/sig000000b7 ;
wire \blk00000001/sig000000b6 ;
wire \blk00000001/sig000000b5 ;
wire \blk00000001/sig000000b4 ;
wire \blk00000001/sig000000b3 ;
wire \blk00000001/sig000000b2 ;
wire \blk00000001/sig000000b1 ;
wire \blk00000001/sig000000b0 ;
wire \blk00000001/sig000000af ;
wire \blk00000001/sig000000ae ;
wire \blk00000001/sig000000ad ;
wire \blk00000001/sig000000ac ;
wire \blk00000001/sig000000ab ;
wire \blk00000001/sig000000aa ;
wire \blk00000001/sig000000a9 ;
wire \blk00000001/sig000000a8 ;
wire \blk00000001/sig000000a7 ;
wire \blk00000001/sig000000a6 ;
wire \blk00000001/sig000000a5 ;
wire \blk00000001/sig000000a4 ;
wire \blk00000001/sig000000a3 ;
wire \blk00000001/sig000000a2 ;
wire \blk00000001/sig000000a1 ;
wire \blk00000001/sig000000a0 ;
wire \blk00000001/sig0000009f ;
wire \blk00000001/sig0000009e ;
wire \blk00000001/sig0000009d ;
wire \blk00000001/sig0000009c ;
wire \blk00000001/sig0000009b ;
wire \blk00000001/sig0000009a ;
wire \blk00000001/sig00000099 ;
wire \blk00000001/sig00000098 ;
wire \blk00000001/sig00000097 ;
wire \blk00000001/sig00000096 ;
wire \blk00000001/sig00000095 ;
wire \blk00000001/sig00000094 ;
wire \blk00000001/sig00000093 ;
wire \blk00000001/sig00000092 ;
wire \blk00000001/sig00000091 ;
wire \blk00000001/sig00000090 ;
wire \blk00000001/sig0000008f ;
wire \blk00000001/sig0000008e ;
wire \blk00000001/sig0000008d ;
wire \blk00000001/sig0000008c ;
wire \blk00000001/sig0000008b ;
wire \blk00000001/sig0000008a ;
wire \blk00000001/sig00000089 ;
wire \blk00000001/sig00000088 ;
wire \blk00000001/sig00000087 ;
wire \blk00000001/sig00000086 ;
wire \blk00000001/sig00000085 ;
wire \blk00000001/sig00000084 ;
wire \blk00000001/sig00000083 ;
wire \blk00000001/sig00000082 ;
wire \blk00000001/sig00000081 ;
wire \blk00000001/sig00000080 ;
wire \blk00000001/sig0000007f ;
wire \blk00000001/sig0000007e ;
wire \blk00000001/sig0000007d ;
wire \blk00000001/sig0000007c ;
wire \blk00000001/sig0000007b ;
wire \blk00000001/sig0000007a ;
wire \blk00000001/sig00000079 ;
wire \blk00000001/sig00000078 ;
wire \blk00000001/sig00000077 ;
wire \blk00000001/sig00000076 ;
wire \blk00000001/sig00000075 ;
wire \blk00000001/sig00000074 ;
wire \blk00000001/sig00000073 ;
wire \blk00000001/sig00000072 ;
wire \blk00000001/sig00000071 ;
wire \blk00000001/sig00000070 ;
wire \blk00000001/sig0000006f ;
wire \blk00000001/sig0000006e ;
wire \blk00000001/sig0000006d ;
wire \blk00000001/sig0000006c ;
wire \blk00000001/sig0000006b ;
wire \blk00000001/sig0000006a ;
wire \blk00000001/sig00000069 ;
wire \blk00000001/sig00000068 ;
wire \blk00000001/sig00000067 ;
wire \blk00000001/sig00000066 ;
wire \blk00000001/sig00000065 ;
wire \blk00000001/sig00000064 ;
wire \blk00000001/sig00000063 ;
wire \blk00000001/sig00000062 ;
wire \blk00000001/sig00000061 ;
wire \blk00000001/sig00000060 ;
wire \blk00000001/sig0000005f ;
wire \blk00000001/sig0000005e ;
wire \blk00000001/sig0000005d ;
wire \blk00000001/sig0000005c ;
wire \blk00000001/sig0000005b ;
wire \blk00000001/sig0000005a ;
wire \blk00000001/sig00000059 ;
wire \blk00000001/sig00000058 ;
wire \blk00000001/sig00000057 ;
wire \blk00000001/sig00000056 ;
wire \blk00000001/sig00000055 ;
wire \blk00000001/sig00000054 ;
wire \blk00000001/sig00000053 ;
wire \blk00000001/sig00000052 ;
wire \blk00000001/sig00000051 ;
wire \blk00000001/sig00000050 ;
wire \blk00000001/sig0000004f ;
wire \blk00000001/sig0000004e ;
wire \blk00000001/sig0000004d ;
wire \blk00000001/sig0000004c ;
wire \blk00000001/sig0000004b ;
wire \blk00000001/sig0000004a ;
wire \blk00000001/sig00000049 ;
wire \blk00000001/sig00000048 ;
wire \blk00000001/sig00000047 ;
wire \blk00000001/sig00000046 ;
wire \blk00000001/sig00000045 ;
wire \blk00000001/blk0000003b/sig000002f5 ;
wire \blk00000001/blk0000003b/sig000002f4 ;
wire \blk00000001/blk0000003b/sig000002f3 ;
wire \blk00000001/blk0000003b/sig000002f2 ;
wire \blk00000001/blk0000003b/sig000002f1 ;
wire \blk00000001/blk0000003b/sig000002f0 ;
wire \blk00000001/blk0000003b/sig000002ef ;
wire \blk00000001/blk0000003b/sig000002ee ;
wire \blk00000001/blk0000003b/sig000002ed ;
wire \blk00000001/blk0000003b/sig000002ec ;
wire \blk00000001/blk0000003b/sig000002eb ;
wire \blk00000001/blk0000003b/sig000002ea ;
wire \blk00000001/blk0000003b/sig000002e1 ;
wire \blk00000001/blk0000003f/sig00000313 ;
wire \blk00000001/blk0000003f/sig00000312 ;
wire \NLW_blk00000001/blk0000023b_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000239_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000237_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000235_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000233_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000231_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000022f_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000022d_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000022b_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000229_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000227_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000225_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000223_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000221_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000021f_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000021d_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000021b_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000219_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000217_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000215_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000213_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000211_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020f_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020d_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020b_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000209_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000207_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000205_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000203_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000201_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001ff_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001fd_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001fb_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001f9_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001f7_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001f5_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001f3_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001f1_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001ef_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001ed_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001eb_Q31_UNCONNECTED ;
wire \NLW_blk00000001/blk000001e9_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001e7_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001e5_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001e3_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001e1_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001df_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001dd_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001db_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d3_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d1_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001cf_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001cd_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001cb_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001c9_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001c7_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001c5_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001c3_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001c1_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001bf_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001bd_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001bb_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001b9_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001b7_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001b5_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001b3_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001b1_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001af_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001ad_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001ab_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001a9_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001a7_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001a5_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001a3_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001a1_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000019f_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000019d_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000019b_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000199_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000197_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000195_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000193_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000191_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000018f_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000018d_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000018b_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000189_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000187_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000185_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000183_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000181_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000017f_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000017d_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000017b_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000179_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000177_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000175_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000173_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000171_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000016f_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000016d_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000016b_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000169_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000167_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000165_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000163_Q31_UNCONNECTED ;
wire \NLW_blk00000001/blk00000161_Q31_UNCONNECTED ;
wire \NLW_blk00000001/blk0000015f_Q31_UNCONNECTED ;
wire \NLW_blk00000001/blk0000015d_Q31_UNCONNECTED ;
wire \NLW_blk00000001/blk0000015b_Q31_UNCONNECTED ;
wire \NLW_blk00000001/blk00000159_Q31_UNCONNECTED ;
wire \NLW_blk00000001/blk00000157_Q31_UNCONNECTED ;
wire \NLW_blk00000001/blk00000155_Q31_UNCONNECTED ;
wire \NLW_blk00000001/blk00000153_Q31_UNCONNECTED ;
wire \NLW_blk00000001/blk00000151_Q31_UNCONNECTED ;
wire \NLW_blk00000001/blk0000014f_Q31_UNCONNECTED ;
wire \NLW_blk00000001/blk0000014d_Q31_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PATTERNBDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_MULTSIGNOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_CARRYCASCOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_UNDERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PATTERNDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_OVERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PATTERNBDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_MULTSIGNOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_CARRYCASCOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_UNDERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PATTERNDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_OVERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PATTERNBDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_MULTSIGNOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_CARRYCASCOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_UNDERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PATTERNDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_OVERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PATTERNBDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_MULTSIGNOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_CARRYCASCOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_UNDERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PATTERNDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_OVERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PATTERNBDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_MULTSIGNOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_CARRYCASCOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_UNDERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PATTERNDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_OVERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PATTERNBDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_MULTSIGNOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_CARRYCASCOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_UNDERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PATTERNDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_OVERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PATTERNBDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_MULTSIGNOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_MULTSIGNIN_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_CARRYCASCOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_UNDERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PATTERNDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_OVERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_CARRYCASCIN_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PATTERNBDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_MULTSIGNOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_MULTSIGNIN_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_CARRYCASCOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_UNDERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PATTERNDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_OVERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_CARRYCASCIN_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<0>_UNCONNECTED ;
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000023c (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002cb ),
.Q(\blk00000001/sig0000018a )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000023b (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000192 ),
.Q(\blk00000001/sig000002cb ),
.Q15(\NLW_blk00000001/blk0000023b_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000023a (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002ca ),
.Q(\blk00000001/sig0000018b )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000239 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000193 ),
.Q(\blk00000001/sig000002ca ),
.Q15(\NLW_blk00000001/blk00000239_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000238 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002c9 ),
.Q(\blk00000001/sig0000018c )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000237 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000194 ),
.Q(\blk00000001/sig000002c9 ),
.Q15(\NLW_blk00000001/blk00000237_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000236 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002c8 ),
.Q(\blk00000001/sig0000018d )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000235 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000195 ),
.Q(\blk00000001/sig000002c8 ),
.Q15(\NLW_blk00000001/blk00000235_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000234 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002c7 ),
.Q(\blk00000001/sig0000018e )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000233 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000196 ),
.Q(\blk00000001/sig000002c7 ),
.Q15(\NLW_blk00000001/blk00000233_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000232 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002c6 ),
.Q(\blk00000001/sig0000018f )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000231 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000197 ),
.Q(\blk00000001/sig000002c6 ),
.Q15(\NLW_blk00000001/blk00000231_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000230 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002c5 ),
.Q(\blk00000001/sig00000190 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000022f (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000198 ),
.Q(\blk00000001/sig000002c5 ),
.Q15(\NLW_blk00000001/blk0000022f_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000022e (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002c4 ),
.Q(\blk00000001/sig00000191 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000022d (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000199 ),
.Q(\blk00000001/sig000002c4 ),
.Q15(\NLW_blk00000001/blk0000022d_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000022c (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002c3 ),
.Q(\blk00000001/sig00000183 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000022b (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001b9 ),
.Q(\blk00000001/sig000002c3 ),
.Q15(\NLW_blk00000001/blk0000022b_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000022a (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002c2 ),
.Q(\blk00000001/sig00000184 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000229 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001ba ),
.Q(\blk00000001/sig000002c2 ),
.Q15(\NLW_blk00000001/blk00000229_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000228 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002c1 ),
.Q(\blk00000001/sig00000185 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000227 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001bb ),
.Q(\blk00000001/sig000002c1 ),
.Q15(\NLW_blk00000001/blk00000227_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000226 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002c0 ),
.Q(\blk00000001/sig00000186 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000225 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001bc ),
.Q(\blk00000001/sig000002c0 ),
.Q15(\NLW_blk00000001/blk00000225_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000224 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002bf ),
.Q(\blk00000001/sig00000187 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000223 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001bd ),
.Q(\blk00000001/sig000002bf ),
.Q15(\NLW_blk00000001/blk00000223_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000222 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002be ),
.Q(\blk00000001/sig00000188 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000221 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001be ),
.Q(\blk00000001/sig000002be ),
.Q15(\NLW_blk00000001/blk00000221_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000220 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002bd ),
.Q(\blk00000001/sig00000189 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000021f (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001bf ),
.Q(\blk00000001/sig000002bd ),
.Q15(\NLW_blk00000001/blk0000021f_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000021e (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002bc ),
.Q(\blk00000001/sig00000192 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000021d (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001c0 ),
.Q(\blk00000001/sig000002bc ),
.Q15(\NLW_blk00000001/blk0000021d_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000021c (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002bb ),
.Q(\blk00000001/sig00000193 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000021b (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001c1 ),
.Q(\blk00000001/sig000002bb ),
.Q15(\NLW_blk00000001/blk0000021b_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000021a (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002ba ),
.Q(\blk00000001/sig00000194 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000219 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001c2 ),
.Q(\blk00000001/sig000002ba ),
.Q15(\NLW_blk00000001/blk00000219_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000218 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002b9 ),
.Q(\blk00000001/sig00000195 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000217 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001c3 ),
.Q(\blk00000001/sig000002b9 ),
.Q15(\NLW_blk00000001/blk00000217_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000216 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002b8 ),
.Q(\blk00000001/sig00000196 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000215 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001c4 ),
.Q(\blk00000001/sig000002b8 ),
.Q15(\NLW_blk00000001/blk00000215_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000214 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002b7 ),
.Q(\blk00000001/sig00000197 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000213 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001c5 ),
.Q(\blk00000001/sig000002b7 ),
.Q15(\NLW_blk00000001/blk00000213_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000212 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002b6 ),
.Q(\blk00000001/sig00000198 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000211 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001c6 ),
.Q(\blk00000001/sig000002b6 ),
.Q15(\NLW_blk00000001/blk00000211_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000210 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002b5 ),
.Q(\blk00000001/sig00000199 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000020f (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001c7 ),
.Q(\blk00000001/sig000002b5 ),
.Q15(\NLW_blk00000001/blk0000020f_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000020e (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002b4 ),
.Q(\blk00000001/sig0000012b )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000020d (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000de ),
.Q(\blk00000001/sig000002b4 ),
.Q15(\NLW_blk00000001/blk0000020d_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000020c (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002b3 ),
.Q(\blk00000001/sig0000012c )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000020b (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000df ),
.Q(\blk00000001/sig000002b3 ),
.Q15(\NLW_blk00000001/blk0000020b_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000020a (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002b2 ),
.Q(\blk00000001/sig0000012d )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000209 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000e0 ),
.Q(\blk00000001/sig000002b2 ),
.Q15(\NLW_blk00000001/blk00000209_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000208 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002b1 ),
.Q(\blk00000001/sig0000012e )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000207 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000e1 ),
.Q(\blk00000001/sig000002b1 ),
.Q15(\NLW_blk00000001/blk00000207_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000206 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002b0 ),
.Q(\blk00000001/sig0000012f )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000205 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000e2 ),
.Q(\blk00000001/sig000002b0 ),
.Q15(\NLW_blk00000001/blk00000205_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000204 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002af ),
.Q(\blk00000001/sig00000130 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000203 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000e3 ),
.Q(\blk00000001/sig000002af ),
.Q15(\NLW_blk00000001/blk00000203_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000202 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002ae ),
.Q(\blk00000001/sig00000131 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000201 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000e4 ),
.Q(\blk00000001/sig000002ae ),
.Q15(\NLW_blk00000001/blk00000201_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000200 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002ad ),
.Q(\blk00000001/sig000000c8 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001ff (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000010a ),
.Q(\blk00000001/sig000002ad ),
.Q15(\NLW_blk00000001/blk000001ff_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001fe (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002ac ),
.Q(\blk00000001/sig000000c9 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001fd (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000010b ),
.Q(\blk00000001/sig000002ac ),
.Q15(\NLW_blk00000001/blk000001fd_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001fc (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002ab ),
.Q(\blk00000001/sig000000ca )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001fb (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000010c ),
.Q(\blk00000001/sig000002ab ),
.Q15(\NLW_blk00000001/blk000001fb_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001fa (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002aa ),
.Q(\blk00000001/sig000000cb )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001f9 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000010d ),
.Q(\blk00000001/sig000002aa ),
.Q15(\NLW_blk00000001/blk000001f9_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001f8 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002a9 ),
.Q(\blk00000001/sig000000cc )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001f7 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000010e ),
.Q(\blk00000001/sig000002a9 ),
.Q15(\NLW_blk00000001/blk000001f7_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001f6 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002a8 ),
.Q(\blk00000001/sig000000ce )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001f5 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000110 ),
.Q(\blk00000001/sig000002a8 ),
.Q15(\NLW_blk00000001/blk000001f5_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001f4 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002a7 ),
.Q(\blk00000001/sig000000cf )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001f3 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000111 ),
.Q(\blk00000001/sig000002a7 ),
.Q15(\NLW_blk00000001/blk000001f3_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001f2 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002a6 ),
.Q(\blk00000001/sig000000cd )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001f1 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000010f ),
.Q(\blk00000001/sig000002a6 ),
.Q15(\NLW_blk00000001/blk000001f1_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001f0 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002a5 ),
.Q(\blk00000001/sig0000005c )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001ef (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000113 ),
.Q(\blk00000001/sig000002a5 ),
.Q15(\NLW_blk00000001/blk000001ef_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ee (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002a4 ),
.Q(\blk00000001/sig0000005d )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001ed (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000114 ),
.Q(\blk00000001/sig000002a4 ),
.Q15(\NLW_blk00000001/blk000001ed_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ec (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002a3 ),
.Q(m_axis_result_tvalid)
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk00000001/blk000001eb (
.CLK(aclk),
.D(\blk00000001/sig00000240 ),
.CE(aclken),
.Q(\blk00000001/sig000002a3 ),
.Q31(\NLW_blk00000001/blk000001eb_Q31_UNCONNECTED ),
.A({\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ea (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002a2 ),
.Q(\blk00000001/sig0000005e )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001e9 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000115 ),
.Q(\blk00000001/sig000002a2 ),
.Q15(\NLW_blk00000001/blk000001e9_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001e8 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002a1 ),
.Q(\blk00000001/sig0000005f )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001e7 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000116 ),
.Q(\blk00000001/sig000002a1 ),
.Q15(\NLW_blk00000001/blk000001e7_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001e6 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002a0 ),
.Q(\blk00000001/sig00000060 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001e5 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000117 ),
.Q(\blk00000001/sig000002a0 ),
.Q15(\NLW_blk00000001/blk000001e5_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001e4 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000029f ),
.Q(\blk00000001/sig00000061 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001e3 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000118 ),
.Q(\blk00000001/sig0000029f ),
.Q15(\NLW_blk00000001/blk000001e3_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001e2 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000029e ),
.Q(\blk00000001/sig00000062 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001e1 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000119 ),
.Q(\blk00000001/sig0000029e ),
.Q15(\NLW_blk00000001/blk000001e1_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001e0 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000029d ),
.Q(\blk00000001/sig00000063 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001df (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000011a ),
.Q(\blk00000001/sig0000029d ),
.Q15(\NLW_blk00000001/blk000001df_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001de (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000029c ),
.Q(\blk00000001/sig0000017c )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001dd (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000007a ),
.Q(\blk00000001/sig0000029c ),
.Q15(\NLW_blk00000001/blk000001dd_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001dc (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000029b ),
.Q(\blk00000001/sig0000017d )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001db (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000007b ),
.Q(\blk00000001/sig0000029b ),
.Q15(\NLW_blk00000001/blk000001db_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001da (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000029a ),
.Q(\blk00000001/sig0000017e )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001d9 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000007c ),
.Q(\blk00000001/sig0000029a ),
.Q15(\NLW_blk00000001/blk000001d9_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001d8 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000299 ),
.Q(\blk00000001/sig0000017f )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001d7 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000007d ),
.Q(\blk00000001/sig00000299 ),
.Q15(\NLW_blk00000001/blk000001d7_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001d6 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000298 ),
.Q(\blk00000001/sig00000180 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001d5 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000007e ),
.Q(\blk00000001/sig00000298 ),
.Q15(\NLW_blk00000001/blk000001d5_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001d4 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000297 ),
.Q(\blk00000001/sig00000181 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001d3 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000007f ),
.Q(\blk00000001/sig00000297 ),
.Q15(\NLW_blk00000001/blk000001d3_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001d2 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000296 ),
.Q(\blk00000001/sig00000182 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001d1 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000080 ),
.Q(\blk00000001/sig00000296 ),
.Q15(\NLW_blk00000001/blk000001d1_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001d0 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000295 ),
.Q(\blk00000001/sig000001b9 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001cf (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000081 ),
.Q(\blk00000001/sig00000295 ),
.Q15(\NLW_blk00000001/blk000001cf_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ce (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000294 ),
.Q(\blk00000001/sig000001ba )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001cd (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000082 ),
.Q(\blk00000001/sig00000294 ),
.Q15(\NLW_blk00000001/blk000001cd_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001cc (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000293 ),
.Q(\blk00000001/sig000001bb )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001cb (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000083 ),
.Q(\blk00000001/sig00000293 ),
.Q15(\NLW_blk00000001/blk000001cb_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ca (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000292 ),
.Q(\blk00000001/sig000001bc )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001c9 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000084 ),
.Q(\blk00000001/sig00000292 ),
.Q15(\NLW_blk00000001/blk000001c9_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001c8 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000291 ),
.Q(\blk00000001/sig000001bd )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001c7 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000085 ),
.Q(\blk00000001/sig00000291 ),
.Q15(\NLW_blk00000001/blk000001c7_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001c6 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000290 ),
.Q(\blk00000001/sig000001be )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001c5 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000086 ),
.Q(\blk00000001/sig00000290 ),
.Q15(\NLW_blk00000001/blk000001c5_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001c4 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000028f ),
.Q(\blk00000001/sig000001c7 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001c3 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000008f ),
.Q(\blk00000001/sig0000028f ),
.Q15(\NLW_blk00000001/blk000001c3_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001c2 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000028e ),
.Q(\blk00000001/sig000001c6 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001c1 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000008e ),
.Q(\blk00000001/sig0000028e ),
.Q15(\NLW_blk00000001/blk000001c1_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001c0 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000028d ),
.Q(\blk00000001/sig000001bf )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001bf (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000087 ),
.Q(\blk00000001/sig0000028d ),
.Q15(\NLW_blk00000001/blk000001bf_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001be (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000028c ),
.Q(\blk00000001/sig000001c5 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001bd (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000008d ),
.Q(\blk00000001/sig0000028c ),
.Q15(\NLW_blk00000001/blk000001bd_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001bc (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000028b ),
.Q(\blk00000001/sig000001c4 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001bb (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000008c ),
.Q(\blk00000001/sig0000028b ),
.Q15(\NLW_blk00000001/blk000001bb_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ba (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000028a ),
.Q(\blk00000001/sig000001c3 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001b9 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000008b ),
.Q(\blk00000001/sig0000028a ),
.Q15(\NLW_blk00000001/blk000001b9_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b8 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000289 ),
.Q(\blk00000001/sig000001c2 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001b7 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000008a ),
.Q(\blk00000001/sig00000289 ),
.Q15(\NLW_blk00000001/blk000001b7_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b6 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000288 ),
.Q(\blk00000001/sig000001c1 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001b5 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000089 ),
.Q(\blk00000001/sig00000288 ),
.Q15(\NLW_blk00000001/blk000001b5_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b4 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000287 ),
.Q(\blk00000001/sig000001c0 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001b3 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000088 ),
.Q(\blk00000001/sig00000287 ),
.Q15(\NLW_blk00000001/blk000001b3_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b2 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000286 ),
.Q(\blk00000001/sig000001a1 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001b1 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000133 ),
.Q(\blk00000001/sig00000286 ),
.Q15(\NLW_blk00000001/blk000001b1_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b0 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000285 ),
.Q(\blk00000001/sig000001a0 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001af (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000134 ),
.Q(\blk00000001/sig00000285 ),
.Q15(\NLW_blk00000001/blk000001af_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ae (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000284 ),
.Q(\blk00000001/sig0000019f )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001ad (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000135 ),
.Q(\blk00000001/sig00000284 ),
.Q15(\NLW_blk00000001/blk000001ad_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ac (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000283 ),
.Q(\blk00000001/sig0000019e )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001ab (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000136 ),
.Q(\blk00000001/sig00000283 ),
.Q15(\NLW_blk00000001/blk000001ab_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001aa (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000282 ),
.Q(\blk00000001/sig0000019d )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001a9 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000137 ),
.Q(\blk00000001/sig00000282 ),
.Q15(\NLW_blk00000001/blk000001a9_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a8 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000281 ),
.Q(\blk00000001/sig0000019c )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001a7 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000138 ),
.Q(\blk00000001/sig00000281 ),
.Q15(\NLW_blk00000001/blk000001a7_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a6 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000280 ),
.Q(\blk00000001/sig0000019a )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001a5 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000013a ),
.Q(\blk00000001/sig00000280 ),
.Q15(\NLW_blk00000001/blk000001a5_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a4 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000027f ),
.Q(\blk00000001/sig0000011b )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001a3 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[0]),
.Q(\blk00000001/sig0000027f ),
.Q15(\NLW_blk00000001/blk000001a3_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a2 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000027e ),
.Q(\blk00000001/sig0000019b )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001a1 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000139 ),
.Q(\blk00000001/sig0000027e ),
.Q15(\NLW_blk00000001/blk000001a1_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a0 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000027d ),
.Q(\blk00000001/sig0000011c )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000019f (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[1]),
.Q(\blk00000001/sig0000027d ),
.Q15(\NLW_blk00000001/blk0000019f_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000019e (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000027c ),
.Q(\blk00000001/sig0000011d )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000019d (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[2]),
.Q(\blk00000001/sig0000027c ),
.Q15(\NLW_blk00000001/blk0000019d_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000019c (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000027b ),
.Q(\blk00000001/sig0000011e )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000019b (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[3]),
.Q(\blk00000001/sig0000027b ),
.Q15(\NLW_blk00000001/blk0000019b_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000019a (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000027a ),
.Q(\blk00000001/sig0000011f )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000199 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[4]),
.Q(\blk00000001/sig0000027a ),
.Q15(\NLW_blk00000001/blk00000199_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000198 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000279 ),
.Q(\blk00000001/sig00000120 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000197 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[5]),
.Q(\blk00000001/sig00000279 ),
.Q15(\NLW_blk00000001/blk00000197_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000196 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000278 ),
.Q(\blk00000001/sig00000121 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000195 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[6]),
.Q(\blk00000001/sig00000278 ),
.Q15(\NLW_blk00000001/blk00000195_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000194 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000277 ),
.Q(\blk00000001/sig00000122 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000193 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[7]),
.Q(\blk00000001/sig00000277 ),
.Q15(\NLW_blk00000001/blk00000193_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000192 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000276 ),
.Q(\blk00000001/sig00000123 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000191 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[8]),
.Q(\blk00000001/sig00000276 ),
.Q15(\NLW_blk00000001/blk00000191_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000190 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000275 ),
.Q(\blk00000001/sig00000124 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000018f (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[9]),
.Q(\blk00000001/sig00000275 ),
.Q15(\NLW_blk00000001/blk0000018f_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000018e (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000274 ),
.Q(\blk00000001/sig00000125 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000018d (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[10]),
.Q(\blk00000001/sig00000274 ),
.Q15(\NLW_blk00000001/blk0000018d_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000018c (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000273 ),
.Q(\blk00000001/sig00000126 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000018b (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[11]),
.Q(\blk00000001/sig00000273 ),
.Q15(\NLW_blk00000001/blk0000018b_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000018a (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000272 ),
.Q(\blk00000001/sig00000127 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000189 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[12]),
.Q(\blk00000001/sig00000272 ),
.Q15(\NLW_blk00000001/blk00000189_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000188 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000271 ),
.Q(\blk00000001/sig00000129 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000187 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[14]),
.Q(\blk00000001/sig00000271 ),
.Q15(\NLW_blk00000001/blk00000187_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000186 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000270 ),
.Q(\blk00000001/sig0000012a )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000185 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[15]),
.Q(\blk00000001/sig00000270 ),
.Q15(\NLW_blk00000001/blk00000185_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000184 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000026f ),
.Q(\blk00000001/sig00000128 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000183 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[13]),
.Q(\blk00000001/sig0000026f ),
.Q15(\NLW_blk00000001/blk00000183_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000182 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000026e ),
.Q(\blk00000001/sig0000010a )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000181 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000e5 ),
.Q(\blk00000001/sig0000026e ),
.Q15(\NLW_blk00000001/blk00000181_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000180 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000026d ),
.Q(\blk00000001/sig0000010b )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000017f (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000e6 ),
.Q(\blk00000001/sig0000026d ),
.Q15(\NLW_blk00000001/blk0000017f_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000017e (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000026c ),
.Q(\blk00000001/sig0000010c )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000017d (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000e7 ),
.Q(\blk00000001/sig0000026c ),
.Q15(\NLW_blk00000001/blk0000017d_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000017c (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000026b ),
.Q(\blk00000001/sig0000010d )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000017b (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000e8 ),
.Q(\blk00000001/sig0000026b ),
.Q15(\NLW_blk00000001/blk0000017b_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000017a (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000026a ),
.Q(\blk00000001/sig0000010e )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000179 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000e9 ),
.Q(\blk00000001/sig0000026a ),
.Q15(\NLW_blk00000001/blk00000179_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000178 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000269 ),
.Q(\blk00000001/sig0000010f )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000177 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000ea ),
.Q(\blk00000001/sig00000269 ),
.Q15(\NLW_blk00000001/blk00000177_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000176 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000268 ),
.Q(\blk00000001/sig00000110 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000175 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000eb ),
.Q(\blk00000001/sig00000268 ),
.Q15(\NLW_blk00000001/blk00000175_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000174 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000267 ),
.Q(\blk00000001/sig00000111 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000173 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000ec ),
.Q(\blk00000001/sig00000267 ),
.Q15(\NLW_blk00000001/blk00000173_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000172 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000266 ),
.Q(\blk00000001/sig000000de )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000171 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[16]),
.Q(\blk00000001/sig00000266 ),
.Q15(\NLW_blk00000001/blk00000171_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000170 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000265 ),
.Q(\blk00000001/sig000000df )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000016f (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[17]),
.Q(\blk00000001/sig00000265 ),
.Q15(\NLW_blk00000001/blk0000016f_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000016e (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000264 ),
.Q(\blk00000001/sig000000e0 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000016d (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[18]),
.Q(\blk00000001/sig00000264 ),
.Q15(\NLW_blk00000001/blk0000016d_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000016c (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000263 ),
.Q(\blk00000001/sig000000e1 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000016b (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[19]),
.Q(\blk00000001/sig00000263 ),
.Q15(\NLW_blk00000001/blk0000016b_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000016a (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000262 ),
.Q(\blk00000001/sig000000e3 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000169 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000fb ),
.Q(\blk00000001/sig00000262 ),
.Q15(\NLW_blk00000001/blk00000169_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000168 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000261 ),
.Q(\blk00000001/sig000000e4 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000167 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000fc ),
.Q(\blk00000001/sig00000261 ),
.Q15(\NLW_blk00000001/blk00000167_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000166 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000260 ),
.Q(\blk00000001/sig000000e2 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000165 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000fa ),
.Q(\blk00000001/sig00000260 ),
.Q15(\NLW_blk00000001/blk00000165_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000164 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000025f ),
.Q(\blk00000001/sig00000091 )
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk00000001/blk00000163 (
.CLK(aclk),
.D(\blk00000001/sig000000ae ),
.CE(aclken),
.Q(\blk00000001/sig0000025f ),
.Q31(\NLW_blk00000001/blk00000163_Q31_UNCONNECTED ),
.A({\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000162 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000025e ),
.Q(\blk00000001/sig0000009b )
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk00000001/blk00000161 (
.CLK(aclk),
.D(s_axis_a_tdata[31]),
.CE(aclken),
.Q(\blk00000001/sig0000025e ),
.Q31(\NLW_blk00000001/blk00000161_Q31_UNCONNECTED ),
.A({\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000160 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000025d ),
.Q(\blk00000001/sig0000009c )
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk00000001/blk0000015f (
.CLK(aclk),
.D(s_axis_a_tdata[23]),
.CE(aclken),
.Q(\blk00000001/sig0000025d ),
.Q31(\NLW_blk00000001/blk0000015f_Q31_UNCONNECTED ),
.A({\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015e (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000025c ),
.Q(\blk00000001/sig0000009d )
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk00000001/blk0000015d (
.CLK(aclk),
.D(s_axis_a_tdata[24]),
.CE(aclken),
.Q(\blk00000001/sig0000025c ),
.Q31(\NLW_blk00000001/blk0000015d_Q31_UNCONNECTED ),
.A({\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015c (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000025b ),
.Q(\blk00000001/sig0000009e )
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk00000001/blk0000015b (
.CLK(aclk),
.D(s_axis_a_tdata[25]),
.CE(aclken),
.Q(\blk00000001/sig0000025b ),
.Q31(\NLW_blk00000001/blk0000015b_Q31_UNCONNECTED ),
.A({\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015a (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000025a ),
.Q(\blk00000001/sig0000009f )
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk00000001/blk00000159 (
.CLK(aclk),
.D(s_axis_a_tdata[26]),
.CE(aclken),
.Q(\blk00000001/sig0000025a ),
.Q31(\NLW_blk00000001/blk00000159_Q31_UNCONNECTED ),
.A({\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000158 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000259 ),
.Q(\blk00000001/sig000000a0 )
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk00000001/blk00000157 (
.CLK(aclk),
.D(s_axis_a_tdata[27]),
.CE(aclken),
.Q(\blk00000001/sig00000259 ),
.Q31(\NLW_blk00000001/blk00000157_Q31_UNCONNECTED ),
.A({\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000156 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000258 ),
.Q(\blk00000001/sig000000a1 )
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk00000001/blk00000155 (
.CLK(aclk),
.D(s_axis_a_tdata[28]),
.CE(aclken),
.Q(\blk00000001/sig00000258 ),
.Q31(\NLW_blk00000001/blk00000155_Q31_UNCONNECTED ),
.A({\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000154 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000257 ),
.Q(\blk00000001/sig000000a2 )
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk00000001/blk00000153 (
.CLK(aclk),
.D(s_axis_a_tdata[29]),
.CE(aclken),
.Q(\blk00000001/sig00000257 ),
.Q31(\NLW_blk00000001/blk00000153_Q31_UNCONNECTED ),
.A({\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000152 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000256 ),
.Q(\blk00000001/sig000000a3 )
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk00000001/blk00000151 (
.CLK(aclk),
.D(s_axis_a_tdata[30]),
.CE(aclken),
.Q(\blk00000001/sig00000256 ),
.Q31(\NLW_blk00000001/blk00000151_Q31_UNCONNECTED ),
.A({\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000150 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000255 ),
.Q(\blk00000001/sig000000a4 )
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk00000001/blk0000014f (
.CLK(aclk),
.D(\blk00000001/sig000000b0 ),
.CE(aclken),
.Q(\blk00000001/sig00000255 ),
.Q31(\NLW_blk00000001/blk0000014f_Q31_UNCONNECTED ),
.A({\blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig00000132 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014e (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000254 ),
.Q(\blk00000001/sig000000a5 )
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk00000001/blk0000014d (
.CLK(aclk),
.D(\blk00000001/sig000000af ),
.CE(aclken),
.Q(\blk00000001/sig00000254 ),
.Q31(\NLW_blk00000001/blk0000014d_Q31_UNCONNECTED ),
.A({\blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig00000132 })
);
INV \blk00000001/blk0000014c (
.I(s_axis_a_tdata[19]),
.O(\blk00000001/sig000000f9 )
);
INV \blk00000001/blk0000014b (
.I(s_axis_a_tdata[18]),
.O(\blk00000001/sig000000f8 )
);
INV \blk00000001/blk0000014a (
.I(s_axis_a_tdata[17]),
.O(\blk00000001/sig000000f7 )
);
INV \blk00000001/blk00000149 (
.I(s_axis_a_tdata[16]),
.O(\blk00000001/sig000000f6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000148 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000a5 ),
.Q(\blk00000001/sig00000253 )
);
LUT6 #(
.INIT ( 64'h55555555BABAABBA ))
\blk00000001/blk00000147 (
.I0(\blk00000001/sig00000091 ),
.I1(\blk00000001/sig00000236 ),
.I2(\blk00000001/sig00000094 ),
.I3(\blk00000001/sig00000090 ),
.I4(\blk00000001/sig00000093 ),
.I5(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000215 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000146 (
.I0(\blk00000001/sig0000005a ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000233 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000145 (
.I0(\blk00000001/sig00000057 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000230 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000144 (
.I0(\blk00000001/sig00000059 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000232 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000143 (
.I0(\blk00000001/sig00000058 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000231 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000142 (
.I0(\blk00000001/sig00000054 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig0000022d )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000141 (
.I0(\blk00000001/sig00000056 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig0000022f )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000140 (
.I0(\blk00000001/sig00000055 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig0000022e )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk0000013f (
.I0(\blk00000001/sig00000053 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig0000022c )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk0000013e (
.I0(\blk00000001/sig00000052 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig0000022b )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk0000013d (
.I0(\blk00000001/sig0000004f ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000228 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk0000013c (
.I0(\blk00000001/sig00000051 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig0000022a )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk0000013b (
.I0(\blk00000001/sig00000050 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000229 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk0000013a (
.I0(\blk00000001/sig0000004c ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000225 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000139 (
.I0(\blk00000001/sig0000004e ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000227 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000138 (
.I0(\blk00000001/sig0000004d ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000226 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000137 (
.I0(\blk00000001/sig00000049 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000222 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000136 (
.I0(\blk00000001/sig0000004b ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000224 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000135 (
.I0(\blk00000001/sig0000004a ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000223 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000134 (
.I0(\blk00000001/sig00000048 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000221 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000133 (
.I0(\blk00000001/sig00000047 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000220 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000132 (
.I0(\blk00000001/sig00000046 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig0000021f )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000131 (
.I0(\blk00000001/sig00000045 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig0000021e )
);
LUT5 #(
.INIT ( 32'h5555BAAB ))
\blk00000001/blk00000130 (
.I0(\blk00000001/sig00000091 ),
.I1(\blk00000001/sig00000236 ),
.I2(\blk00000001/sig00000090 ),
.I3(\blk00000001/sig00000093 ),
.I4(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000214 )
);
LUT6 #(
.INIT ( 64'hFF0000FAFF0000F6 ))
\blk00000001/blk0000012f (
.I0(\blk00000001/sig0000009a ),
.I1(\blk00000001/sig00000097 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000091 ),
.I4(\blk00000001/sig00000092 ),
.I5(\blk00000001/sig00000252 ),
.O(\blk00000001/sig0000024f )
);
LUT6 #(
.INIT ( 64'h7FFFFF7FFFFFFFFF ))
\blk00000001/blk0000012e (
.I0(\blk00000001/sig00000096 ),
.I1(\blk00000001/sig00000095 ),
.I2(\blk00000001/sig00000099 ),
.I3(\blk00000001/sig00000093 ),
.I4(\blk00000001/sig00000090 ),
.I5(\blk00000001/sig00000098 ),
.O(\blk00000001/sig00000252 )
);
LUT6 #(
.INIT ( 64'hFF0000FCFF0000F6 ))
\blk00000001/blk0000012d (
.I0(\blk00000001/sig00000097 ),
.I1(\blk00000001/sig00000099 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000091 ),
.I4(\blk00000001/sig00000092 ),
.I5(\blk00000001/sig00000251 ),
.O(\blk00000001/sig0000024c )
);
LUT5 #(
.INIT ( 32'h7FF7FFFF ))
\blk00000001/blk0000012c (
.I0(\blk00000001/sig00000096 ),
.I1(\blk00000001/sig00000095 ),
.I2(\blk00000001/sig00000093 ),
.I3(\blk00000001/sig00000090 ),
.I4(\blk00000001/sig00000098 ),
.O(\blk00000001/sig00000251 )
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFFFFFF75 ))
\blk00000001/blk0000012b (
.I0(\blk00000001/sig00000094 ),
.I1(\blk00000001/sig00000093 ),
.I2(\blk00000001/sig00000090 ),
.I3(\blk00000001/sig00000236 ),
.I4(\blk00000001/sig00000092 ),
.I5(\blk00000001/sig00000091 ),
.O(\blk00000001/sig00000211 )
);
LUT6 #(
.INIT ( 64'h44507750445F775F ))
\blk00000001/blk0000012a (
.I0(\blk00000001/sig00000250 ),
.I1(\blk00000001/sig0000021c ),
.I2(\blk00000001/sig0000021d ),
.I3(\blk00000001/sig00000212 ),
.I4(\blk00000001/sig0000024f ),
.I5(\blk00000001/sig0000024e ),
.O(\blk00000001/sig0000021b )
);
LUT4 #(
.INIT ( 16'hF00E ))
\blk00000001/blk00000129 (
.I0(\blk00000001/sig0000009a ),
.I1(\blk00000001/sig00000236 ),
.I2(\blk00000001/sig00000091 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000250 )
);
LUT6 #(
.INIT ( 64'hF00EF00E00020001 ))
\blk00000001/blk00000128 (
.I0(\blk00000001/sig0000009a ),
.I1(\blk00000001/sig00000236 ),
.I2(\blk00000001/sig00000091 ),
.I3(\blk00000001/sig00000092 ),
.I4(\blk00000001/sig00000248 ),
.I5(\blk00000001/sig00000249 ),
.O(\blk00000001/sig0000024e )
);
LUT6 #(
.INIT ( 64'h44507750445F775F ))
\blk00000001/blk00000127 (
.I0(\blk00000001/sig0000024d ),
.I1(\blk00000001/sig0000021c ),
.I2(\blk00000001/sig0000021d ),
.I3(\blk00000001/sig00000212 ),
.I4(\blk00000001/sig0000024c ),
.I5(\blk00000001/sig0000024b ),
.O(\blk00000001/sig0000021a )
);
LUT4 #(
.INIT ( 16'hF00E ))
\blk00000001/blk00000126 (
.I0(\blk00000001/sig00000099 ),
.I1(\blk00000001/sig00000236 ),
.I2(\blk00000001/sig00000091 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig0000024d )
);
LUT6 #(
.INIT ( 64'hFF0000FC00000006 ))
\blk00000001/blk00000125 (
.I0(\blk00000001/sig00000098 ),
.I1(\blk00000001/sig00000099 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000091 ),
.I4(\blk00000001/sig00000092 ),
.I5(\blk00000001/sig00000249 ),
.O(\blk00000001/sig0000024b )
);
LUT6 #(
.INIT ( 64'hCCCCCC99C9C9C9C9 ))
\blk00000001/blk00000124 (
.I0(\blk00000001/sig00000249 ),
.I1(\blk00000001/sig0000024a ),
.I2(\blk00000001/sig0000021d ),
.I3(\blk00000001/sig0000021c ),
.I4(\blk00000001/sig00000213 ),
.I5(\blk00000001/sig00000212 ),
.O(\blk00000001/sig00000219 )
);
LUT4 #(
.INIT ( 16'h0FF1 ))
\blk00000001/blk00000123 (
.I0(\blk00000001/sig00000098 ),
.I1(\blk00000001/sig00000236 ),
.I2(\blk00000001/sig00000091 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig0000024a )
);
LUT6 #(
.INIT ( 64'h00FF00FFFF00FF7F ))
\blk00000001/blk00000122 (
.I0(\blk00000001/sig00000097 ),
.I1(\blk00000001/sig00000096 ),
.I2(\blk00000001/sig00000095 ),
.I3(\blk00000001/sig00000253 ),
.I4(\blk00000001/sig00000236 ),
.I5(\blk00000001/sig00000091 ),
.O(\blk00000001/sig00000249 )
);
LUT5 #(
.INIT ( 32'hFF0000F6 ))
\blk00000001/blk00000121 (
.I0(\blk00000001/sig00000090 ),
.I1(\blk00000001/sig00000093 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000091 ),
.I4(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000213 )
);
LUT5 #(
.INIT ( 32'hFF0000F9 ))
\blk00000001/blk00000120 (
.I0(\blk00000001/sig00000094 ),
.I1(\blk00000001/sig00000090 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000091 ),
.I4(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000212 )
);
LUT2 #(
.INIT ( 4'h7 ))
\blk00000001/blk0000011f (
.I0(\blk00000001/sig00000099 ),
.I1(\blk00000001/sig00000098 ),
.O(\blk00000001/sig00000248 )
);
LUT6 #(
.INIT ( 64'h3C3D3C3DFFFDFFFE ))
\blk00000001/blk0000011e (
.I0(\blk00000001/sig00000097 ),
.I1(\blk00000001/sig00000092 ),
.I2(\blk00000001/sig00000091 ),
.I3(\blk00000001/sig00000236 ),
.I4(\blk00000001/sig00000247 ),
.I5(\blk00000001/sig00000211 ),
.O(\blk00000001/sig00000218 )
);
LUT2 #(
.INIT ( 4'h7 ))
\blk00000001/blk0000011d (
.I0(\blk00000001/sig00000096 ),
.I1(\blk00000001/sig00000095 ),
.O(\blk00000001/sig00000247 )
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
\blk00000001/blk0000011c (
.I0(s_axis_a_tdata[30]),
.I1(s_axis_a_tdata[29]),
.I2(s_axis_a_tdata[28]),
.I3(s_axis_a_tdata[27]),
.I4(s_axis_a_tdata[26]),
.I5(\blk00000001/sig00000246 ),
.O(\blk00000001/sig000000ad )
);
LUT3 #(
.INIT ( 8'h80 ))
\blk00000001/blk0000011b (
.I0(s_axis_a_tdata[25]),
.I1(s_axis_a_tdata[24]),
.I2(s_axis_a_tdata[23]),
.O(\blk00000001/sig00000246 )
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
\blk00000001/blk0000011a (
.I0(s_axis_a_tdata[30]),
.I1(s_axis_a_tdata[29]),
.I2(s_axis_a_tdata[28]),
.I3(s_axis_a_tdata[27]),
.I4(s_axis_a_tdata[26]),
.I5(\blk00000001/sig00000245 ),
.O(\blk00000001/sig000000ac )
);
LUT3 #(
.INIT ( 8'hFE ))
\blk00000001/blk00000119 (
.I0(s_axis_a_tdata[25]),
.I1(s_axis_a_tdata[24]),
.I2(s_axis_a_tdata[23]),
.O(\blk00000001/sig00000245 )
);
LUT4 #(
.INIT ( 16'h8000 ))
\blk00000001/blk00000118 (
.I0(\blk00000001/sig00000241 ),
.I1(\blk00000001/sig00000242 ),
.I2(\blk00000001/sig00000243 ),
.I3(\blk00000001/sig00000244 ),
.O(\blk00000001/sig000000ab )
);
LUT5 #(
.INIT ( 32'h00000001 ))
\blk00000001/blk00000117 (
.I0(s_axis_a_tdata[19]),
.I1(s_axis_a_tdata[18]),
.I2(s_axis_a_tdata[20]),
.I3(s_axis_a_tdata[21]),
.I4(s_axis_a_tdata[22]),
.O(\blk00000001/sig00000244 )
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
\blk00000001/blk00000116 (
.I0(s_axis_a_tdata[13]),
.I1(s_axis_a_tdata[12]),
.I2(s_axis_a_tdata[14]),
.I3(s_axis_a_tdata[15]),
.I4(s_axis_a_tdata[16]),
.I5(s_axis_a_tdata[17]),
.O(\blk00000001/sig00000243 )
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
\blk00000001/blk00000115 (
.I0(s_axis_a_tdata[7]),
.I1(s_axis_a_tdata[6]),
.I2(s_axis_a_tdata[8]),
.I3(s_axis_a_tdata[9]),
.I4(s_axis_a_tdata[10]),
.I5(s_axis_a_tdata[11]),
.O(\blk00000001/sig00000242 )
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
\blk00000001/blk00000114 (
.I0(s_axis_a_tdata[1]),
.I1(s_axis_a_tdata[0]),
.I2(s_axis_a_tdata[2]),
.I3(s_axis_a_tdata[3]),
.I4(s_axis_a_tdata[4]),
.I5(s_axis_a_tdata[5]),
.O(\blk00000001/sig00000241 )
);
LUT3 #(
.INIT ( 8'hF2 ))
\blk00000001/blk00000113 (
.I0(\blk00000001/sig0000009c ),
.I1(\blk00000001/sig000000a4 ),
.I2(\blk00000001/sig0000009d ),
.O(\blk00000001/sig0000023a )
);
LUT3 #(
.INIT ( 8'h41 ))
\blk00000001/blk00000112 (
.I0(\blk00000001/sig0000009d ),
.I1(\blk00000001/sig0000009c ),
.I2(\blk00000001/sig000000a4 ),
.O(\blk00000001/sig0000023b )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk00000111 (
.I0(\blk00000001/sig0000009f ),
.I1(\blk00000001/sig0000009e ),
.O(\blk00000001/sig00000239 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk00000110 (
.I0(\blk00000001/sig000000a1 ),
.I1(\blk00000001/sig000000a0 ),
.O(\blk00000001/sig00000238 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk0000010f (
.I0(\blk00000001/sig000000a3 ),
.I1(\blk00000001/sig000000a2 ),
.O(\blk00000001/sig00000237 )
);
LUT4 #(
.INIT ( 16'h5504 ))
\blk00000001/blk0000010e (
.I0(\blk00000001/sig00000092 ),
.I1(\blk00000001/sig0000005b ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000091 ),
.O(\blk00000001/sig00000234 )
);
LUT4 #(
.INIT ( 16'h0FF1 ))
\blk00000001/blk0000010d (
.I0(\blk00000001/sig00000093 ),
.I1(\blk00000001/sig00000236 ),
.I2(\blk00000001/sig00000092 ),
.I3(\blk00000001/sig00000091 ),
.O(\blk00000001/sig0000021c )
);
LUT4 #(
.INIT ( 16'h0FF1 ))
\blk00000001/blk0000010c (
.I0(\blk00000001/sig00000094 ),
.I1(\blk00000001/sig00000236 ),
.I2(\blk00000001/sig00000092 ),
.I3(\blk00000001/sig00000091 ),
.O(\blk00000001/sig0000021d )
);
LUT3 #(
.INIT ( 8'hA2 ))
\blk00000001/blk0000010b (
.I0(\blk00000001/sig0000009b ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000235 )
);
LUT6 #(
.INIT ( 64'h0F0FF0F5FFFFFFF9 ))
\blk00000001/blk0000010a (
.I0(\blk00000001/sig00000096 ),
.I1(\blk00000001/sig00000095 ),
.I2(\blk00000001/sig00000092 ),
.I3(\blk00000001/sig00000236 ),
.I4(\blk00000001/sig00000091 ),
.I5(\blk00000001/sig00000211 ),
.O(\blk00000001/sig00000217 )
);
LUT5 #(
.INIT ( 32'h0FF1F00E ))
\blk00000001/blk00000109 (
.I0(\blk00000001/sig00000095 ),
.I1(\blk00000001/sig00000236 ),
.I2(\blk00000001/sig00000092 ),
.I3(\blk00000001/sig00000091 ),
.I4(\blk00000001/sig00000211 ),
.O(\blk00000001/sig00000216 )
);
LUT3 #(
.INIT ( 8'hF2 ))
\blk00000001/blk00000108 (
.I0(s_axis_a_tdata[20]),
.I1(s_axis_a_tdata[22]),
.I2(s_axis_a_tdata[21]),
.O(\blk00000001/sig000000f2 )
);
LUT3 #(
.INIT ( 8'h4E ))
\blk00000001/blk00000107 (
.I0(s_axis_a_tdata[21]),
.I1(s_axis_a_tdata[20]),
.I2(s_axis_a_tdata[22]),
.O(\blk00000001/sig000000f0 )
);
LUT3 #(
.INIT ( 8'h1B ))
\blk00000001/blk00000106 (
.I0(s_axis_a_tdata[20]),
.I1(s_axis_a_tdata[21]),
.I2(s_axis_a_tdata[22]),
.O(\blk00000001/sig000000ef )
);
LUT3 #(
.INIT ( 8'hF9 ))
\blk00000001/blk00000105 (
.I0(s_axis_a_tdata[20]),
.I1(s_axis_a_tdata[21]),
.I2(s_axis_a_tdata[22]),
.O(\blk00000001/sig000000ee )
);
LUT3 #(
.INIT ( 8'h6A ))
\blk00000001/blk00000104 (
.I0(s_axis_a_tdata[22]),
.I1(s_axis_a_tdata[20]),
.I2(s_axis_a_tdata[21]),
.O(\blk00000001/sig000000f1 )
);
LUT3 #(
.INIT ( 8'h15 ))
\blk00000001/blk00000103 (
.I0(s_axis_a_tdata[22]),
.I1(s_axis_a_tdata[20]),
.I2(s_axis_a_tdata[21]),
.O(\blk00000001/sig000000ed )
);
LUT3 #(
.INIT ( 8'h15 ))
\blk00000001/blk00000102 (
.I0(s_axis_a_tdata[21]),
.I1(s_axis_a_tdata[20]),
.I2(s_axis_a_tdata[22]),
.O(\blk00000001/sig000000f4 )
);
LUT3 #(
.INIT ( 8'h14 ))
\blk00000001/blk00000101 (
.I0(s_axis_a_tdata[22]),
.I1(s_axis_a_tdata[20]),
.I2(s_axis_a_tdata[21]),
.O(\blk00000001/sig000000f5 )
);
LUT3 #(
.INIT ( 8'h29 ))
\blk00000001/blk00000100 (
.I0(s_axis_a_tdata[22]),
.I1(s_axis_a_tdata[20]),
.I2(s_axis_a_tdata[21]),
.O(\blk00000001/sig000000f3 )
);
LUT3 #(
.INIT ( 8'hF8 ))
\blk00000001/blk000000ff (
.I0(\blk00000001/sig000000a9 ),
.I1(\blk00000001/sig000000aa ),
.I2(\blk00000001/sig000000a8 ),
.O(\blk00000001/sig000000a7 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000000fe (
.I0(\blk00000001/sig000000a8 ),
.I1(\blk00000001/sig000000a9 ),
.O(\blk00000001/sig000000a6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000fd (
.C(aclk),
.CE(aclken),
.D(s_axis_a_tvalid),
.Q(\blk00000001/sig00000240 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000fc (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000021e ),
.Q(m_axis_result_tdata[0])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000fb (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000021f ),
.Q(m_axis_result_tdata[1])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000fa (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000220 ),
.Q(m_axis_result_tdata[2])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f9 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000221 ),
.Q(m_axis_result_tdata[3])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f8 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000222 ),
.Q(m_axis_result_tdata[4])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f7 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000223 ),
.Q(m_axis_result_tdata[5])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f6 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000224 ),
.Q(m_axis_result_tdata[6])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f5 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000225 ),
.Q(m_axis_result_tdata[7])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f4 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000226 ),
.Q(m_axis_result_tdata[8])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f3 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000227 ),
.Q(m_axis_result_tdata[9])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f2 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000228 ),
.Q(m_axis_result_tdata[10])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f1 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000229 ),
.Q(m_axis_result_tdata[11])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f0 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000022a ),
.Q(m_axis_result_tdata[12])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ef (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000022b ),
.Q(m_axis_result_tdata[13])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ee (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000022c ),
.Q(m_axis_result_tdata[14])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ed (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000022d ),
.Q(m_axis_result_tdata[15])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ec (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000022e ),
.Q(m_axis_result_tdata[16])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000eb (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000022f ),
.Q(m_axis_result_tdata[17])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ea (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000230 ),
.Q(m_axis_result_tdata[18])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e9 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000231 ),
.Q(m_axis_result_tdata[19])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e8 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000232 ),
.Q(m_axis_result_tdata[20])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e7 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000233 ),
.Q(m_axis_result_tdata[21])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e6 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000234 ),
.Q(m_axis_result_tdata[22])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e5 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000214 ),
.Q(m_axis_result_tdata[23])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e4 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000215 ),
.Q(m_axis_result_tdata[24])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e3 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000216 ),
.Q(m_axis_result_tdata[25])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e2 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000217 ),
.Q(m_axis_result_tdata[26])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e1 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000218 ),
.Q(m_axis_result_tdata[27])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e0 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000219 ),
.Q(m_axis_result_tdata[28])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000df (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000021a ),
.Q(m_axis_result_tdata[29])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000de (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000021b ),
.Q(m_axis_result_tdata[30])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000dd (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000235 ),
.Q(m_axis_result_tdata[31])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000dc (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000023c ),
.Q(\blk00000001/sig00000236 )
);
MUXCY \blk00000001/blk000000db (
.CI(\blk00000001/sig000001d8 ),
.DI(\blk00000001/sig0000023a ),
.S(\blk00000001/sig0000023b ),
.O(\blk00000001/sig0000023f )
);
MUXCY \blk00000001/blk000000da (
.CI(\blk00000001/sig0000023f ),
.DI(\blk00000001/sig000001d8 ),
.S(\blk00000001/sig00000239 ),
.O(\blk00000001/sig0000023e )
);
MUXCY \blk00000001/blk000000d9 (
.CI(\blk00000001/sig0000023e ),
.DI(\blk00000001/sig000001d8 ),
.S(\blk00000001/sig00000238 ),
.O(\blk00000001/sig0000023d )
);
MUXCY \blk00000001/blk000000d8 (
.CI(\blk00000001/sig0000023d ),
.DI(\blk00000001/sig000001d8 ),
.S(\blk00000001/sig00000237 ),
.O(\blk00000001/sig0000023c )
);
DSP48E1 #(
.ACASCREG ( 1 ),
.ADREG ( 0 ),
.ALUMODEREG ( 0 ),
.AREG ( 1 ),
.AUTORESET_PATDET ( "NO_RESET" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 1 ),
.BREG ( 1 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 0 ),
.CARRYINSELREG ( 0 ),
.CREG ( 1 ),
.DREG ( 0 ),
.INMODEREG ( 0 ),
.MASK ( 48'h3FFFFFFFFFFF ),
.MREG ( 1 ),
.OPMODEREG ( 0 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.USE_DPORT ( 0 ),
.USE_MULT ( "MULTIPLY" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
\blk00000001/blk000000d7 (
.PATTERNBDETECT(\NLW_blk00000001/blk000000d7_PATTERNBDETECT_UNCONNECTED ),
.RSTC(\blk00000001/sig000001d8 ),
.CEB1(\blk00000001/sig000001d8 ),
.CEAD(\blk00000001/sig000001d8 ),
.MULTSIGNOUT(\NLW_blk00000001/blk000000d7_MULTSIGNOUT_UNCONNECTED ),
.CEC(aclken),
.RSTM(\blk00000001/sig000001d8 ),
.MULTSIGNIN(\blk00000001/sig000001d8 ),
.CEB2(aclken),
.RSTCTRL(\blk00000001/sig000001d8 ),
.CEP(aclken),
.CARRYCASCOUT(\NLW_blk00000001/blk000000d7_CARRYCASCOUT_UNCONNECTED ),
.RSTA(\blk00000001/sig000001d8 ),
.CECARRYIN(\blk00000001/sig000001d8 ),
.UNDERFLOW(\NLW_blk00000001/blk000000d7_UNDERFLOW_UNCONNECTED ),
.PATTERNDETECT(\NLW_blk00000001/blk000000d7_PATTERNDETECT_UNCONNECTED ),
.RSTALUMODE(\blk00000001/sig000001d8 ),
.RSTALLCARRYIN(\blk00000001/sig000001d8 ),
.CED(\blk00000001/sig000001d8 ),
.RSTD(\blk00000001/sig000001d8 ),
.CEALUMODE(\blk00000001/sig000001d8 ),
.CEA2(aclken),
.CLK(aclk),
.CEA1(\blk00000001/sig000001d8 ),
.RSTB(\blk00000001/sig000001d8 ),
.OVERFLOW(\NLW_blk00000001/blk000000d7_OVERFLOW_UNCONNECTED ),
.CECTRL(\blk00000001/sig000001d8 ),
.CEM(aclken),
.CARRYIN(\blk00000001/sig000001d8 ),
.CARRYCASCIN(\blk00000001/sig000001d8 ),
.RSTINMODE(\blk00000001/sig000001d8 ),
.CEINMODE(\blk00000001/sig000001d8 ),
.RSTP(\blk00000001/sig000001d8 ),
.ACOUT({\NLW_blk00000001/blk000000d7_ACOUT<29>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_ACOUT<27>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_ACOUT<25>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_ACOUT<23>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_ACOUT<21>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_ACOUT<19>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_ACOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_ACOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_ACOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_ACOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_ACOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_ACOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_ACOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_ACOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_ACOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<0>_UNCONNECTED }),
.OPMODE({\blk00000001/sig000001d8 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 ,
\blk00000001/sig000001d8 , \blk00000001/sig00000132 }),
.PCIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.ALUMODE({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.C({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig00000210 , \blk00000001/sig0000020f , \blk00000001/sig0000020e ,
\blk00000001/sig0000020d , \blk00000001/sig0000020c , \blk00000001/sig0000020b , \blk00000001/sig0000020a , \blk00000001/sig00000209 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig00000112 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.CARRYOUT({\NLW_blk00000001/blk000000d7_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000000d7_CARRYOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000000d7_CARRYOUT<0>_UNCONNECTED }),
.INMODE({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.BCIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.B({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig00000063 , \blk00000001/sig00000062 , \blk00000001/sig00000061 , \blk00000001/sig00000060 , \blk00000001/sig0000005f ,
\blk00000001/sig0000005e , \blk00000001/sig0000005d , \blk00000001/sig0000005c }),
.BCOUT({\NLW_blk00000001/blk000000d7_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000000d7_BCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000000d7_BCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000000d7_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000000d7_BCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000000d7_BCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000000d7_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000000d7_BCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000000d7_BCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000000d7_BCOUT<0>_UNCONNECTED }),
.D({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.P({\NLW_blk00000001/blk000000d7_P<47>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<46>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_P<45>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<44>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<43>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_P<42>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<41>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<40>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_P<39>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<38>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<37>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_P<36>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<35>_UNCONNECTED , \blk00000001/sig0000005b , \blk00000001/sig0000005a
, \blk00000001/sig00000059 , \blk00000001/sig00000058 , \blk00000001/sig00000057 , \blk00000001/sig00000056 , \blk00000001/sig00000055 ,
\blk00000001/sig00000054 , \blk00000001/sig00000053 , \blk00000001/sig00000052 , \blk00000001/sig00000051 , \blk00000001/sig00000050 ,
\blk00000001/sig0000004f , \blk00000001/sig0000004e , \blk00000001/sig0000004d , \blk00000001/sig0000004c , \blk00000001/sig0000004b ,
\blk00000001/sig0000004a , \blk00000001/sig00000049 , \blk00000001/sig00000048 , \blk00000001/sig00000047 , \blk00000001/sig00000046 ,
\blk00000001/sig00000045 , \NLW_blk00000001/blk000000d7_P<11>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<10>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_P<9>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<8>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<7>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_P<6>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<5>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<4>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_P<3>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<2>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<1>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_P<0>_UNCONNECTED }),
.A({\blk00000001/sig00000079 , \blk00000001/sig00000079 , \blk00000001/sig00000079 , \blk00000001/sig00000079 , \blk00000001/sig00000079 ,
\blk00000001/sig00000079 , \blk00000001/sig00000079 , \blk00000001/sig00000079 , \blk00000001/sig00000079 , \blk00000001/sig00000078 ,
\blk00000001/sig00000077 , \blk00000001/sig00000076 , \blk00000001/sig00000075 , \blk00000001/sig00000074 , \blk00000001/sig00000073 ,
\blk00000001/sig00000072 , \blk00000001/sig00000071 , \blk00000001/sig00000070 , \blk00000001/sig0000006f , \blk00000001/sig0000006e ,
\blk00000001/sig0000006d , \blk00000001/sig0000006c , \blk00000001/sig0000006b , \blk00000001/sig0000006a , \blk00000001/sig00000069 ,
\blk00000001/sig00000068 , \blk00000001/sig00000067 , \blk00000001/sig00000066 , \blk00000001/sig00000065 , \blk00000001/sig00000064 }),
.PCOUT({\NLW_blk00000001/blk000000d7_PCOUT<47>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<46>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<45>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<44>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<43>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<42>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<41>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<40>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<39>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<38>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<37>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<36>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<35>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<34>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<33>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<32>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<31>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<30>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<29>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<27>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<25>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<23>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<21>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<19>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<0>_UNCONNECTED }),
.ACIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.CARRYINSEL({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d6 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000005c ),
.Q(\blk00000001/sig00000209 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d5 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000005d ),
.Q(\blk00000001/sig0000020a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d4 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000005e ),
.Q(\blk00000001/sig0000020b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d3 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000005f ),
.Q(\blk00000001/sig0000020c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d2 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000060 ),
.Q(\blk00000001/sig0000020d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d1 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000061 ),
.Q(\blk00000001/sig0000020e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d0 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000062 ),
.Q(\blk00000001/sig0000020f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000cf (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000063 ),
.Q(\blk00000001/sig00000210 )
);
DSP48E1 #(
.ACASCREG ( 1 ),
.ADREG ( 0 ),
.ALUMODEREG ( 0 ),
.AREG ( 1 ),
.AUTORESET_PATDET ( "NO_RESET" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 1 ),
.BREG ( 1 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 0 ),
.CARRYINSELREG ( 0 ),
.CREG ( 1 ),
.DREG ( 0 ),
.INMODEREG ( 0 ),
.MASK ( 48'h3FFFFFFFFFFF ),
.MREG ( 1 ),
.OPMODEREG ( 0 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.USE_DPORT ( 0 ),
.USE_MULT ( "MULTIPLY" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
\blk00000001/blk000000ce (
.PATTERNBDETECT(\NLW_blk00000001/blk000000ce_PATTERNBDETECT_UNCONNECTED ),
.RSTC(\blk00000001/sig000001d8 ),
.CEB1(\blk00000001/sig000001d8 ),
.CEAD(\blk00000001/sig000001d8 ),
.MULTSIGNOUT(\NLW_blk00000001/blk000000ce_MULTSIGNOUT_UNCONNECTED ),
.CEC(aclken),
.RSTM(\blk00000001/sig000001d8 ),
.MULTSIGNIN(\blk00000001/sig000001d8 ),
.CEB2(aclken),
.RSTCTRL(\blk00000001/sig000001d8 ),
.CEP(aclken),
.CARRYCASCOUT(\NLW_blk00000001/blk000000ce_CARRYCASCOUT_UNCONNECTED ),
.RSTA(\blk00000001/sig000001d8 ),
.CECARRYIN(\blk00000001/sig000001d8 ),
.UNDERFLOW(\NLW_blk00000001/blk000000ce_UNDERFLOW_UNCONNECTED ),
.PATTERNDETECT(\NLW_blk00000001/blk000000ce_PATTERNDETECT_UNCONNECTED ),
.RSTALUMODE(\blk00000001/sig000001d8 ),
.RSTALLCARRYIN(\blk00000001/sig000001d8 ),
.CED(\blk00000001/sig000001d8 ),
.RSTD(\blk00000001/sig000001d8 ),
.CEALUMODE(\blk00000001/sig000001d8 ),
.CEA2(aclken),
.CLK(aclk),
.CEA1(\blk00000001/sig000001d8 ),
.RSTB(\blk00000001/sig000001d8 ),
.OVERFLOW(\NLW_blk00000001/blk000000ce_OVERFLOW_UNCONNECTED ),
.CECTRL(\blk00000001/sig000001d8 ),
.CEM(aclken),
.CARRYIN(\blk00000001/sig000001d8 ),
.CARRYCASCIN(\blk00000001/sig000001d8 ),
.RSTINMODE(\blk00000001/sig000001d8 ),
.CEINMODE(\blk00000001/sig000001d8 ),
.RSTP(\blk00000001/sig000001d8 ),
.ACOUT({\NLW_blk00000001/blk000000ce_ACOUT<29>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_ACOUT<27>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_ACOUT<25>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_ACOUT<23>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_ACOUT<21>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_ACOUT<19>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_ACOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_ACOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_ACOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_ACOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_ACOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_ACOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_ACOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_ACOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_ACOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<0>_UNCONNECTED }),
.OPMODE({\blk00000001/sig000001d8 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 ,
\blk00000001/sig000001d8 , \blk00000001/sig00000132 }),
.PCIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.ALUMODE({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 , \blk00000001/sig00000132 }),
.C({\blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 ,
\blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 ,
\blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 ,
\blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 ,
\blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 ,
\blk00000001/sig00000208 , \blk00000001/sig00000207 , \blk00000001/sig00000206 , \blk00000001/sig00000205 , \blk00000001/sig00000204 ,
\blk00000001/sig00000203 , \blk00000001/sig00000202 , \blk00000001/sig00000201 , \blk00000001/sig00000200 , \blk00000001/sig000001ff ,
\blk00000001/sig000001fe , \blk00000001/sig000001fd , \blk00000001/sig000001fc , \blk00000001/sig000001fb , \blk00000001/sig000001fa ,
\blk00000001/sig000001f9 , \blk00000001/sig000001f8 , \blk00000001/sig000001f7 , \blk00000001/sig000001f6 , \blk00000001/sig000001f5 ,
\blk00000001/sig000001f4 , \blk00000001/sig000001f3 , \blk00000001/sig000001f2 }),
.CARRYOUT({\NLW_blk00000001/blk000000ce_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000000ce_CARRYOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000000ce_CARRYOUT<0>_UNCONNECTED }),
.INMODE({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.BCIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.B({\blk00000001/sig000001a1 , \blk00000001/sig000001a1 , \blk00000001/sig000001a1 , \blk00000001/sig000001a1 , \blk00000001/sig000001a1 ,
\blk00000001/sig000001a1 , \blk00000001/sig000001a1 , \blk00000001/sig000001a1 , \blk00000001/sig000001a1 , \blk00000001/sig000001a1 ,
\blk00000001/sig000001a1 , \blk00000001/sig000001a0 , \blk00000001/sig0000019f , \blk00000001/sig0000019e , \blk00000001/sig0000019d ,
\blk00000001/sig0000019c , \blk00000001/sig0000019b , \blk00000001/sig0000019a }),
.BCOUT({\NLW_blk00000001/blk000000ce_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000000ce_BCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000000ce_BCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000000ce_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000000ce_BCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000000ce_BCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000000ce_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000000ce_BCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000000ce_BCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000000ce_BCOUT<0>_UNCONNECTED }),
.D({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.P({\NLW_blk00000001/blk000000ce_P<47>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<46>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_P<45>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<44>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<43>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_P<42>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<41>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<40>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_P<39>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<38>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<37>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_P<36>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<35>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_P<33>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<32>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_P<30>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<29>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_P<27>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<26>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<25>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_P<24>_UNCONNECTED , \blk00000001/sig000001f1 , \blk00000001/sig000001f0 , \blk00000001/sig000001ef ,
\blk00000001/sig000001ee , \blk00000001/sig000001ed , \blk00000001/sig000001ec , \blk00000001/sig000001eb , \blk00000001/sig000001ea ,
\blk00000001/sig000001e9 , \blk00000001/sig000001e8 , \blk00000001/sig000001e7 , \blk00000001/sig000001e6 , \blk00000001/sig000001e5 ,
\blk00000001/sig000001e4 , \blk00000001/sig000001e3 , \blk00000001/sig000001e2 , \blk00000001/sig000001e1 ,
\NLW_blk00000001/blk000000ce_P<6>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<5>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<4>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_P<3>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<2>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<1>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_P<0>_UNCONNECTED }),
.A({\blk00000001/sig00000199 , \blk00000001/sig00000199 , \blk00000001/sig00000199 , \blk00000001/sig00000199 , \blk00000001/sig00000199 ,
\blk00000001/sig00000199 , \blk00000001/sig00000199 , \blk00000001/sig00000199 , \blk00000001/sig00000199 , \blk00000001/sig00000199 ,
\blk00000001/sig00000199 , \blk00000001/sig00000199 , \blk00000001/sig00000199 , \blk00000001/sig00000199 , \blk00000001/sig00000199 ,
\blk00000001/sig00000199 , \blk00000001/sig00000199 , \blk00000001/sig00000199 , \blk00000001/sig00000199 , \blk00000001/sig00000199 ,
\blk00000001/sig00000199 , \blk00000001/sig00000199 , \blk00000001/sig00000199 , \blk00000001/sig00000198 , \blk00000001/sig00000197 ,
\blk00000001/sig00000196 , \blk00000001/sig00000195 , \blk00000001/sig00000194 , \blk00000001/sig00000193 , \blk00000001/sig00000192 }),
.PCOUT({\NLW_blk00000001/blk000000ce_PCOUT<47>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<46>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<45>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<44>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<43>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<42>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<41>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<40>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<39>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<38>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<37>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<36>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<35>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<34>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<33>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<32>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<31>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<30>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<29>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<27>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<25>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<23>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<21>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<19>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<0>_UNCONNECTED }),
.ACIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.CARRYINSEL({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000cd (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001a2 ),
.Q(\blk00000001/sig000001f2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000cc (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001a3 ),
.Q(\blk00000001/sig000001f3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000cb (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001a4 ),
.Q(\blk00000001/sig000001f4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ca (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001a5 ),
.Q(\blk00000001/sig000001f5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c9 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001a6 ),
.Q(\blk00000001/sig000001f6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c8 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001a7 ),
.Q(\blk00000001/sig000001f7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c7 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001a8 ),
.Q(\blk00000001/sig000001f8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c6 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001a9 ),
.Q(\blk00000001/sig000001f9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c5 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001aa ),
.Q(\blk00000001/sig000001fa )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c4 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001ab ),
.Q(\blk00000001/sig000001fb )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c3 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001ac ),
.Q(\blk00000001/sig000001fc )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c2 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001ad ),
.Q(\blk00000001/sig000001fd )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c1 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001ae ),
.Q(\blk00000001/sig000001fe )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c0 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001af ),
.Q(\blk00000001/sig000001ff )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000bf (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001b0 ),
.Q(\blk00000001/sig00000200 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000be (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001b1 ),
.Q(\blk00000001/sig00000201 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000bd (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001b2 ),
.Q(\blk00000001/sig00000202 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000bc (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001b3 ),
.Q(\blk00000001/sig00000203 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000bb (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001b4 ),
.Q(\blk00000001/sig00000204 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ba (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001b5 ),
.Q(\blk00000001/sig00000205 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b9 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001b6 ),
.Q(\blk00000001/sig00000206 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b8 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001b7 ),
.Q(\blk00000001/sig00000207 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b7 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001b8 ),
.Q(\blk00000001/sig00000208 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b6 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000166 ),
.Q(\blk00000001/sig00000064 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b5 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000167 ),
.Q(\blk00000001/sig00000065 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b4 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000168 ),
.Q(\blk00000001/sig00000066 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b3 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000169 ),
.Q(\blk00000001/sig00000067 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b2 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000016a ),
.Q(\blk00000001/sig00000068 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b1 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000016b ),
.Q(\blk00000001/sig00000069 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b0 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000016c ),
.Q(\blk00000001/sig0000006a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000af (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000016d ),
.Q(\blk00000001/sig0000006b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ae (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000016e ),
.Q(\blk00000001/sig0000006c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ad (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000016f ),
.Q(\blk00000001/sig0000006d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ac (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000170 ),
.Q(\blk00000001/sig0000006e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ab (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000171 ),
.Q(\blk00000001/sig0000006f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000aa (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000172 ),
.Q(\blk00000001/sig00000070 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a9 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000173 ),
.Q(\blk00000001/sig00000071 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a8 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000174 ),
.Q(\blk00000001/sig00000072 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a7 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000175 ),
.Q(\blk00000001/sig00000073 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a6 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000176 ),
.Q(\blk00000001/sig00000074 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a5 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000177 ),
.Q(\blk00000001/sig00000075 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a4 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000178 ),
.Q(\blk00000001/sig00000076 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a3 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000179 ),
.Q(\blk00000001/sig00000077 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a2 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000017a ),
.Q(\blk00000001/sig00000078 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a1 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000017b ),
.Q(\blk00000001/sig00000079 )
);
DSP48E1 #(
.ACASCREG ( 1 ),
.ADREG ( 0 ),
.ALUMODEREG ( 0 ),
.AREG ( 1 ),
.AUTORESET_PATDET ( "NO_RESET" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 1 ),
.BREG ( 1 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 0 ),
.CARRYINSELREG ( 0 ),
.CREG ( 1 ),
.DREG ( 0 ),
.INMODEREG ( 0 ),
.MASK ( 48'h3FFFFFFFFFFF ),
.MREG ( 1 ),
.OPMODEREG ( 0 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.USE_DPORT ( 0 ),
.USE_MULT ( "MULTIPLY" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
\blk00000001/blk000000a0 (
.PATTERNBDETECT(\NLW_blk00000001/blk000000a0_PATTERNBDETECT_UNCONNECTED ),
.RSTC(\blk00000001/sig000001d8 ),
.CEB1(\blk00000001/sig000001d8 ),
.CEAD(\blk00000001/sig000001d8 ),
.MULTSIGNOUT(\NLW_blk00000001/blk000000a0_MULTSIGNOUT_UNCONNECTED ),
.CEC(aclken),
.RSTM(\blk00000001/sig000001d8 ),
.MULTSIGNIN(\blk00000001/sig000001d8 ),
.CEB2(aclken),
.RSTCTRL(\blk00000001/sig000001d8 ),
.CEP(aclken),
.CARRYCASCOUT(\NLW_blk00000001/blk000000a0_CARRYCASCOUT_UNCONNECTED ),
.RSTA(\blk00000001/sig000001d8 ),
.CECARRYIN(\blk00000001/sig000001d8 ),
.UNDERFLOW(\NLW_blk00000001/blk000000a0_UNDERFLOW_UNCONNECTED ),
.PATTERNDETECT(\NLW_blk00000001/blk000000a0_PATTERNDETECT_UNCONNECTED ),
.RSTALUMODE(\blk00000001/sig000001d8 ),
.RSTALLCARRYIN(\blk00000001/sig000001d8 ),
.CED(\blk00000001/sig000001d8 ),
.RSTD(\blk00000001/sig000001d8 ),
.CEALUMODE(\blk00000001/sig000001d8 ),
.CEA2(aclken),
.CLK(aclk),
.CEA1(\blk00000001/sig000001d8 ),
.RSTB(\blk00000001/sig000001d8 ),
.OVERFLOW(\NLW_blk00000001/blk000000a0_OVERFLOW_UNCONNECTED ),
.CECTRL(\blk00000001/sig000001d8 ),
.CEM(aclken),
.CARRYIN(\blk00000001/sig000001d8 ),
.CARRYCASCIN(\blk00000001/sig000001d8 ),
.RSTINMODE(\blk00000001/sig000001d8 ),
.CEINMODE(\blk00000001/sig000001d8 ),
.RSTP(\blk00000001/sig000001d8 ),
.ACOUT({\NLW_blk00000001/blk000000a0_ACOUT<29>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_ACOUT<27>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_ACOUT<25>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_ACOUT<23>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_ACOUT<21>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_ACOUT<19>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_ACOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_ACOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_ACOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_ACOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_ACOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_ACOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_ACOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_ACOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_ACOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<0>_UNCONNECTED }),
.OPMODE({\blk00000001/sig000001d8 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 ,
\blk00000001/sig000001d8 , \blk00000001/sig00000132 }),
.PCIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.ALUMODE({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.C({\blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 ,
\blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 ,
\blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 ,
\blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 ,
\blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 ,
\blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000134 , \blk00000001/sig00000135 , \blk00000001/sig00000136 ,
\blk00000001/sig00000137 , \blk00000001/sig00000138 , \blk00000001/sig00000139 , \blk00000001/sig0000013a , \blk00000001/sig000001e0 ,
\blk00000001/sig000001df , \blk00000001/sig000001de , \blk00000001/sig000001dd , \blk00000001/sig000001dc , \blk00000001/sig000001db ,
\blk00000001/sig000001da , \blk00000001/sig000001d9 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.CARRYOUT({\NLW_blk00000001/blk000000a0_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000000a0_CARRYOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000000a0_CARRYOUT<0>_UNCONNECTED }),
.INMODE({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.BCIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.B({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001bf , \blk00000001/sig000001be , \blk00000001/sig000001bd , \blk00000001/sig000001bc ,
\blk00000001/sig000001bb , \blk00000001/sig000001ba , \blk00000001/sig000001b9 }),
.BCOUT({\NLW_blk00000001/blk000000a0_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000000a0_BCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000000a0_BCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000000a0_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000000a0_BCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000000a0_BCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000000a0_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000000a0_BCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000000a0_BCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000000a0_BCOUT<0>_UNCONNECTED }),
.D({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.P({\NLW_blk00000001/blk000000a0_P<47>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<46>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_P<45>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<44>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<43>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_P<42>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<41>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<40>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_P<39>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<38>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<37>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_P<36>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<35>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_P<33>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<32>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_P<30>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<29>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_P<27>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<26>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<25>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_P<24>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<23>_UNCONNECTED , \blk00000001/sig000001b8 , \blk00000001/sig000001b7
, \blk00000001/sig000001b6 , \blk00000001/sig000001b5 , \blk00000001/sig000001b4 , \blk00000001/sig000001b3 , \blk00000001/sig000001b2 ,
\blk00000001/sig000001b1 , \blk00000001/sig000001b0 , \blk00000001/sig000001af , \blk00000001/sig000001ae , \blk00000001/sig000001ad ,
\blk00000001/sig000001ac , \blk00000001/sig000001ab , \blk00000001/sig000001aa , \blk00000001/sig000001a9 , \blk00000001/sig000001a8 ,
\blk00000001/sig000001a7 , \blk00000001/sig000001a6 , \blk00000001/sig000001a5 , \blk00000001/sig000001a4 , \blk00000001/sig000001a3 ,
\blk00000001/sig000001a2 }),
.A({\blk00000001/sig000001c7 , \blk00000001/sig000001c7 , \blk00000001/sig000001c7 , \blk00000001/sig000001c7 , \blk00000001/sig000001c7 ,
\blk00000001/sig000001c7 , \blk00000001/sig000001c7 , \blk00000001/sig000001c7 , \blk00000001/sig000001c7 , \blk00000001/sig000001c7 ,
\blk00000001/sig000001c7 , \blk00000001/sig000001c7 , \blk00000001/sig000001c7 , \blk00000001/sig000001c7 , \blk00000001/sig000001c7 ,
\blk00000001/sig000001c7 , \blk00000001/sig000001c7 , \blk00000001/sig000001c7 , \blk00000001/sig000001c7 , \blk00000001/sig000001c7 ,
\blk00000001/sig000001c7 , \blk00000001/sig000001c7 , \blk00000001/sig000001c6 , \blk00000001/sig000001c5 , \blk00000001/sig000001c4 ,
\blk00000001/sig000001c3 , \blk00000001/sig000001c2 , \blk00000001/sig000001c1 , \blk00000001/sig000001c0 , \blk00000001/sig000001d8 }),
.PCOUT({\NLW_blk00000001/blk000000a0_PCOUT<47>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<46>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<45>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<44>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<43>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<42>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<41>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<40>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<39>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<38>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<37>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<36>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<35>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<34>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<33>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<32>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<31>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<30>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<29>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<27>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<25>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<23>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<21>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<19>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<0>_UNCONNECTED }),
.ACIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.CARRYINSEL({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000009f (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001c8 ),
.Q(\blk00000001/sig000001d9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000009e (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001c9 ),
.Q(\blk00000001/sig000001da )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000009d (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001ca ),
.Q(\blk00000001/sig000001db )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000009c (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001cb ),
.Q(\blk00000001/sig000001dc )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000009b (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001cc ),
.Q(\blk00000001/sig000001dd )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000009a (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001cd ),
.Q(\blk00000001/sig000001de )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000099 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001ce ),
.Q(\blk00000001/sig000001df )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000098 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001cf ),
.Q(\blk00000001/sig000001e0 )
);
DSP48E1 #(
.ACASCREG ( 1 ),
.ADREG ( 0 ),
.ALUMODEREG ( 0 ),
.AREG ( 1 ),
.AUTORESET_PATDET ( "NO_RESET" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 1 ),
.BREG ( 1 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 0 ),
.CARRYINSELREG ( 0 ),
.CREG ( 1 ),
.DREG ( 0 ),
.INMODEREG ( 0 ),
.MASK ( 48'h000000000000 ),
.MREG ( 1 ),
.OPMODEREG ( 0 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.USE_DPORT ( 0 ),
.USE_MULT ( "MULTIPLY" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
\blk00000001/blk00000097 (
.PATTERNBDETECT(\NLW_blk00000001/blk00000097_PATTERNBDETECT_UNCONNECTED ),
.RSTC(\blk00000001/sig000001d8 ),
.CEB1(\blk00000001/sig000001d8 ),
.CEAD(\blk00000001/sig000001d8 ),
.MULTSIGNOUT(\NLW_blk00000001/blk00000097_MULTSIGNOUT_UNCONNECTED ),
.CEC(aclken),
.RSTM(\blk00000001/sig000001d8 ),
.MULTSIGNIN(\blk00000001/sig000001d8 ),
.CEB2(aclken),
.RSTCTRL(\blk00000001/sig000001d8 ),
.CEP(aclken),
.CARRYCASCOUT(\NLW_blk00000001/blk00000097_CARRYCASCOUT_UNCONNECTED ),
.RSTA(\blk00000001/sig000001d8 ),
.CECARRYIN(\blk00000001/sig000001d8 ),
.UNDERFLOW(\NLW_blk00000001/blk00000097_UNDERFLOW_UNCONNECTED ),
.PATTERNDETECT(\NLW_blk00000001/blk00000097_PATTERNDETECT_UNCONNECTED ),
.RSTALUMODE(\blk00000001/sig000001d8 ),
.RSTALLCARRYIN(\blk00000001/sig000001d8 ),
.CED(\blk00000001/sig000001d8 ),
.RSTD(\blk00000001/sig000001d8 ),
.CEALUMODE(\blk00000001/sig000001d8 ),
.CEA2(aclken),
.CLK(aclk),
.CEA1(\blk00000001/sig000001d8 ),
.RSTB(\blk00000001/sig000001d8 ),
.OVERFLOW(\NLW_blk00000001/blk00000097_OVERFLOW_UNCONNECTED ),
.CECTRL(\blk00000001/sig000001d8 ),
.CEM(aclken),
.CARRYIN(\blk00000001/sig000001d8 ),
.CARRYCASCIN(\blk00000001/sig000001d8 ),
.RSTINMODE(\blk00000001/sig000001d8 ),
.CEINMODE(\blk00000001/sig000001d8 ),
.RSTP(\blk00000001/sig000001d8 ),
.ACOUT({\NLW_blk00000001/blk00000097_ACOUT<29>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_ACOUT<27>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_ACOUT<25>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_ACOUT<23>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_ACOUT<21>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_ACOUT<19>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_ACOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_ACOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_ACOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_ACOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_ACOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_ACOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_ACOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_ACOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_ACOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<0>_UNCONNECTED }),
.OPMODE({\blk00000001/sig000001d8 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 ,
\blk00000001/sig000001d8 , \blk00000001/sig00000132 }),
.PCIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.ALUMODE({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.C({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig00000112 }),
.CARRYOUT({\NLW_blk00000001/blk00000097_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000097_CARRYOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000097_CARRYOUT<0>_UNCONNECTED }),
.INMODE({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.BCIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.B({\blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f ,
\blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f ,
\blk00000001/sig0000008f , \blk00000001/sig0000008e , \blk00000001/sig0000008d , \blk00000001/sig0000008c , \blk00000001/sig0000008b ,
\blk00000001/sig0000008a , \blk00000001/sig00000089 , \blk00000001/sig00000088 }),
.BCOUT({\NLW_blk00000001/blk00000097_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000097_BCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000097_BCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000097_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000097_BCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000097_BCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000097_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000097_BCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000097_BCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000097_BCOUT<0>_UNCONNECTED }),
.D({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.P({\NLW_blk00000001/blk00000097_P<47>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<46>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_P<45>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<44>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<43>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_P<42>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<41>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<40>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_P<39>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<38>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<37>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_P<36>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<35>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_P<33>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<32>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_P<30>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<29>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_P<27>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<26>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<25>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_P<24>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<23>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_P<21>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<20>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<19>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_P<18>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<17>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<16>_UNCONNECTED ,
\blk00000001/sig000001d7 , \blk00000001/sig000001d6 , \blk00000001/sig000001d5 , \blk00000001/sig000001d4 , \blk00000001/sig000001d3 ,
\blk00000001/sig000001d2 , \blk00000001/sig000001d1 , \blk00000001/sig000001d0 , \blk00000001/sig000001cf , \blk00000001/sig000001ce ,
\blk00000001/sig000001cd , \blk00000001/sig000001cc , \blk00000001/sig000001cb , \blk00000001/sig000001ca , \blk00000001/sig000001c9 ,
\blk00000001/sig000001c8 }),
.A({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f ,
\blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f ,
\blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f ,
\blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008e , \blk00000001/sig0000008d , \blk00000001/sig0000008c ,
\blk00000001/sig0000008b , \blk00000001/sig0000008a , \blk00000001/sig00000089 , \blk00000001/sig00000088 , \blk00000001/sig000001d8 }),
.PCOUT({\NLW_blk00000001/blk00000097_PCOUT<47>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<46>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<45>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<44>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<43>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<42>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<41>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<40>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<39>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<38>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<37>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<36>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<35>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<34>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<33>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<32>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<31>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<29>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<27>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<25>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<23>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<21>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<19>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<0>_UNCONNECTED }),
.ACIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.CARRYINSEL({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 })
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000096 (
.I0(\blk00000001/sig0000017c ),
.I1(\blk00000001/sig000001e1 ),
.O(\blk00000001/sig00000165 )
);
MUXCY \blk00000001/blk00000095 (
.CI(\blk00000001/sig00000132 ),
.DI(\blk00000001/sig000001e1 ),
.S(\blk00000001/sig00000165 ),
.O(\blk00000001/sig00000164 )
);
XORCY \blk00000001/blk00000094 (
.CI(\blk00000001/sig00000132 ),
.LI(\blk00000001/sig00000165 ),
.O(\blk00000001/sig00000166 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000093 (
.I0(\blk00000001/sig0000017d ),
.I1(\blk00000001/sig000001e2 ),
.O(\blk00000001/sig00000163 )
);
MUXCY \blk00000001/blk00000092 (
.CI(\blk00000001/sig00000164 ),
.DI(\blk00000001/sig000001e2 ),
.S(\blk00000001/sig00000163 ),
.O(\blk00000001/sig00000162 )
);
XORCY \blk00000001/blk00000091 (
.CI(\blk00000001/sig00000164 ),
.LI(\blk00000001/sig00000163 ),
.O(\blk00000001/sig00000167 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000090 (
.I0(\blk00000001/sig0000017e ),
.I1(\blk00000001/sig000001e3 ),
.O(\blk00000001/sig00000161 )
);
MUXCY \blk00000001/blk0000008f (
.CI(\blk00000001/sig00000162 ),
.DI(\blk00000001/sig000001e3 ),
.S(\blk00000001/sig00000161 ),
.O(\blk00000001/sig00000160 )
);
XORCY \blk00000001/blk0000008e (
.CI(\blk00000001/sig00000162 ),
.LI(\blk00000001/sig00000161 ),
.O(\blk00000001/sig00000168 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk0000008d (
.I0(\blk00000001/sig0000017f ),
.I1(\blk00000001/sig000001e4 ),
.O(\blk00000001/sig0000015f )
);
MUXCY \blk00000001/blk0000008c (
.CI(\blk00000001/sig00000160 ),
.DI(\blk00000001/sig000001e4 ),
.S(\blk00000001/sig0000015f ),
.O(\blk00000001/sig0000015e )
);
XORCY \blk00000001/blk0000008b (
.CI(\blk00000001/sig00000160 ),
.LI(\blk00000001/sig0000015f ),
.O(\blk00000001/sig00000169 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk0000008a (
.I0(\blk00000001/sig00000180 ),
.I1(\blk00000001/sig000001e5 ),
.O(\blk00000001/sig0000015d )
);
MUXCY \blk00000001/blk00000089 (
.CI(\blk00000001/sig0000015e ),
.DI(\blk00000001/sig000001e5 ),
.S(\blk00000001/sig0000015d ),
.O(\blk00000001/sig0000015c )
);
XORCY \blk00000001/blk00000088 (
.CI(\blk00000001/sig0000015e ),
.LI(\blk00000001/sig0000015d ),
.O(\blk00000001/sig0000016a )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000087 (
.I0(\blk00000001/sig00000181 ),
.I1(\blk00000001/sig000001e6 ),
.O(\blk00000001/sig0000015b )
);
MUXCY \blk00000001/blk00000086 (
.CI(\blk00000001/sig0000015c ),
.DI(\blk00000001/sig000001e6 ),
.S(\blk00000001/sig0000015b ),
.O(\blk00000001/sig0000015a )
);
XORCY \blk00000001/blk00000085 (
.CI(\blk00000001/sig0000015c ),
.LI(\blk00000001/sig0000015b ),
.O(\blk00000001/sig0000016b )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000084 (
.I0(\blk00000001/sig00000182 ),
.I1(\blk00000001/sig000001e7 ),
.O(\blk00000001/sig00000159 )
);
MUXCY \blk00000001/blk00000083 (
.CI(\blk00000001/sig0000015a ),
.DI(\blk00000001/sig000001e7 ),
.S(\blk00000001/sig00000159 ),
.O(\blk00000001/sig00000158 )
);
XORCY \blk00000001/blk00000082 (
.CI(\blk00000001/sig0000015a ),
.LI(\blk00000001/sig00000159 ),
.O(\blk00000001/sig0000016c )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000081 (
.I0(\blk00000001/sig00000183 ),
.I1(\blk00000001/sig000001e8 ),
.O(\blk00000001/sig00000157 )
);
MUXCY \blk00000001/blk00000080 (
.CI(\blk00000001/sig00000158 ),
.DI(\blk00000001/sig000001e8 ),
.S(\blk00000001/sig00000157 ),
.O(\blk00000001/sig00000156 )
);
XORCY \blk00000001/blk0000007f (
.CI(\blk00000001/sig00000158 ),
.LI(\blk00000001/sig00000157 ),
.O(\blk00000001/sig0000016d )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk0000007e (
.I0(\blk00000001/sig00000184 ),
.I1(\blk00000001/sig000001e9 ),
.O(\blk00000001/sig00000155 )
);
MUXCY \blk00000001/blk0000007d (
.CI(\blk00000001/sig00000156 ),
.DI(\blk00000001/sig000001e9 ),
.S(\blk00000001/sig00000155 ),
.O(\blk00000001/sig00000154 )
);
XORCY \blk00000001/blk0000007c (
.CI(\blk00000001/sig00000156 ),
.LI(\blk00000001/sig00000155 ),
.O(\blk00000001/sig0000016e )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk0000007b (
.I0(\blk00000001/sig00000185 ),
.I1(\blk00000001/sig000001ea ),
.O(\blk00000001/sig00000153 )
);
MUXCY \blk00000001/blk0000007a (
.CI(\blk00000001/sig00000154 ),
.DI(\blk00000001/sig000001ea ),
.S(\blk00000001/sig00000153 ),
.O(\blk00000001/sig00000152 )
);
XORCY \blk00000001/blk00000079 (
.CI(\blk00000001/sig00000154 ),
.LI(\blk00000001/sig00000153 ),
.O(\blk00000001/sig0000016f )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000078 (
.I0(\blk00000001/sig00000186 ),
.I1(\blk00000001/sig000001eb ),
.O(\blk00000001/sig00000151 )
);
MUXCY \blk00000001/blk00000077 (
.CI(\blk00000001/sig00000152 ),
.DI(\blk00000001/sig000001eb ),
.S(\blk00000001/sig00000151 ),
.O(\blk00000001/sig00000150 )
);
XORCY \blk00000001/blk00000076 (
.CI(\blk00000001/sig00000152 ),
.LI(\blk00000001/sig00000151 ),
.O(\blk00000001/sig00000170 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000075 (
.I0(\blk00000001/sig00000187 ),
.I1(\blk00000001/sig000001ec ),
.O(\blk00000001/sig0000014f )
);
MUXCY \blk00000001/blk00000074 (
.CI(\blk00000001/sig00000150 ),
.DI(\blk00000001/sig000001ec ),
.S(\blk00000001/sig0000014f ),
.O(\blk00000001/sig0000014e )
);
XORCY \blk00000001/blk00000073 (
.CI(\blk00000001/sig00000150 ),
.LI(\blk00000001/sig0000014f ),
.O(\blk00000001/sig00000171 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000072 (
.I0(\blk00000001/sig00000188 ),
.I1(\blk00000001/sig000001ed ),
.O(\blk00000001/sig0000014d )
);
MUXCY \blk00000001/blk00000071 (
.CI(\blk00000001/sig0000014e ),
.DI(\blk00000001/sig000001ed ),
.S(\blk00000001/sig0000014d ),
.O(\blk00000001/sig0000014c )
);
XORCY \blk00000001/blk00000070 (
.CI(\blk00000001/sig0000014e ),
.LI(\blk00000001/sig0000014d ),
.O(\blk00000001/sig00000172 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk0000006f (
.I0(\blk00000001/sig00000189 ),
.I1(\blk00000001/sig000001ee ),
.O(\blk00000001/sig0000014b )
);
MUXCY \blk00000001/blk0000006e (
.CI(\blk00000001/sig0000014c ),
.DI(\blk00000001/sig000001ee ),
.S(\blk00000001/sig0000014b ),
.O(\blk00000001/sig0000014a )
);
XORCY \blk00000001/blk0000006d (
.CI(\blk00000001/sig0000014c ),
.LI(\blk00000001/sig0000014b ),
.O(\blk00000001/sig00000173 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk0000006c (
.I0(\blk00000001/sig000001ef ),
.I1(\blk00000001/sig0000018a ),
.O(\blk00000001/sig00000149 )
);
MUXCY \blk00000001/blk0000006b (
.CI(\blk00000001/sig0000014a ),
.DI(\blk00000001/sig000001ef ),
.S(\blk00000001/sig00000149 ),
.O(\blk00000001/sig00000148 )
);
XORCY \blk00000001/blk0000006a (
.CI(\blk00000001/sig0000014a ),
.LI(\blk00000001/sig00000149 ),
.O(\blk00000001/sig00000174 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000069 (
.I0(\blk00000001/sig000001f0 ),
.I1(\blk00000001/sig0000018b ),
.O(\blk00000001/sig00000147 )
);
MUXCY \blk00000001/blk00000068 (
.CI(\blk00000001/sig00000148 ),
.DI(\blk00000001/sig000001f0 ),
.S(\blk00000001/sig00000147 ),
.O(\blk00000001/sig00000146 )
);
XORCY \blk00000001/blk00000067 (
.CI(\blk00000001/sig00000148 ),
.LI(\blk00000001/sig00000147 ),
.O(\blk00000001/sig00000175 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000066 (
.I0(\blk00000001/sig000001f1 ),
.I1(\blk00000001/sig0000018c ),
.O(\blk00000001/sig00000145 )
);
MUXCY \blk00000001/blk00000065 (
.CI(\blk00000001/sig00000146 ),
.DI(\blk00000001/sig000001f1 ),
.S(\blk00000001/sig00000145 ),
.O(\blk00000001/sig00000144 )
);
XORCY \blk00000001/blk00000064 (
.CI(\blk00000001/sig00000146 ),
.LI(\blk00000001/sig00000145 ),
.O(\blk00000001/sig00000176 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000063 (
.I0(\blk00000001/sig000001f1 ),
.I1(\blk00000001/sig0000018d ),
.O(\blk00000001/sig00000143 )
);
MUXCY \blk00000001/blk00000062 (
.CI(\blk00000001/sig00000144 ),
.DI(\blk00000001/sig000001f1 ),
.S(\blk00000001/sig00000143 ),
.O(\blk00000001/sig00000142 )
);
XORCY \blk00000001/blk00000061 (
.CI(\blk00000001/sig00000144 ),
.LI(\blk00000001/sig00000143 ),
.O(\blk00000001/sig00000177 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000060 (
.I0(\blk00000001/sig000001f1 ),
.I1(\blk00000001/sig0000018e ),
.O(\blk00000001/sig00000141 )
);
MUXCY \blk00000001/blk0000005f (
.CI(\blk00000001/sig00000142 ),
.DI(\blk00000001/sig000001f1 ),
.S(\blk00000001/sig00000141 ),
.O(\blk00000001/sig00000140 )
);
XORCY \blk00000001/blk0000005e (
.CI(\blk00000001/sig00000142 ),
.LI(\blk00000001/sig00000141 ),
.O(\blk00000001/sig00000178 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk0000005d (
.I0(\blk00000001/sig000001f1 ),
.I1(\blk00000001/sig0000018f ),
.O(\blk00000001/sig0000013f )
);
MUXCY \blk00000001/blk0000005c (
.CI(\blk00000001/sig00000140 ),
.DI(\blk00000001/sig000001f1 ),
.S(\blk00000001/sig0000013f ),
.O(\blk00000001/sig0000013e )
);
XORCY \blk00000001/blk0000005b (
.CI(\blk00000001/sig00000140 ),
.LI(\blk00000001/sig0000013f ),
.O(\blk00000001/sig00000179 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk0000005a (
.I0(\blk00000001/sig000001f1 ),
.I1(\blk00000001/sig00000190 ),
.O(\blk00000001/sig0000013d )
);
MUXCY \blk00000001/blk00000059 (
.CI(\blk00000001/sig0000013e ),
.DI(\blk00000001/sig000001f1 ),
.S(\blk00000001/sig0000013d ),
.O(\blk00000001/sig0000013c )
);
XORCY \blk00000001/blk00000058 (
.CI(\blk00000001/sig0000013e ),
.LI(\blk00000001/sig0000013d ),
.O(\blk00000001/sig0000017a )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000057 (
.I0(\blk00000001/sig000001f1 ),
.I1(\blk00000001/sig00000191 ),
.O(\blk00000001/sig0000013b )
);
XORCY \blk00000001/blk00000056 (
.CI(\blk00000001/sig0000013c ),
.LI(\blk00000001/sig0000013b ),
.O(\blk00000001/sig0000017b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000055 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001d7 ),
.Q(\blk00000001/sig00000133 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000054 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001d6 ),
.Q(\blk00000001/sig00000134 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000053 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001d5 ),
.Q(\blk00000001/sig00000135 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000052 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001d4 ),
.Q(\blk00000001/sig00000136 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000051 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001d3 ),
.Q(\blk00000001/sig00000137 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000050 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001d2 ),
.Q(\blk00000001/sig00000138 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000004f (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001d1 ),
.Q(\blk00000001/sig00000139 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000004e (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001d0 ),
.Q(\blk00000001/sig0000013a )
);
FDS #(
.INIT ( 1'b0 ))
\blk00000001/blk0000004d (
.C(aclk),
.D(\blk00000001/sig00000112 ),
.S(aclken),
.Q(\blk00000001/sig00000112 )
);
DSP48E1 #(
.ACASCREG ( 1 ),
.ADREG ( 0 ),
.ALUMODEREG ( 0 ),
.AREG ( 1 ),
.AUTORESET_PATDET ( "NO_RESET" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 1 ),
.BREG ( 1 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 0 ),
.CARRYINSELREG ( 0 ),
.CREG ( 1 ),
.DREG ( 0 ),
.INMODEREG ( 0 ),
.MASK ( 48'h000000000000 ),
.MREG ( 1 ),
.OPMODEREG ( 0 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.USE_DPORT ( 0 ),
.USE_MULT ( "MULTIPLY" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
\blk00000001/blk0000004c (
.PATTERNBDETECT(\NLW_blk00000001/blk0000004c_PATTERNBDETECT_UNCONNECTED ),
.RSTC(\blk00000001/sig000001d8 ),
.CEB1(\blk00000001/sig000001d8 ),
.CEAD(\blk00000001/sig000001d8 ),
.MULTSIGNOUT(\NLW_blk00000001/blk0000004c_MULTSIGNOUT_UNCONNECTED ),
.CEC(aclken),
.RSTM(\blk00000001/sig000001d8 ),
.MULTSIGNIN(\blk00000001/sig000001d8 ),
.CEB2(aclken),
.RSTCTRL(\blk00000001/sig000001d8 ),
.CEP(aclken),
.CARRYCASCOUT(\NLW_blk00000001/blk0000004c_CARRYCASCOUT_UNCONNECTED ),
.RSTA(\blk00000001/sig000001d8 ),
.CECARRYIN(\blk00000001/sig000001d8 ),
.UNDERFLOW(\NLW_blk00000001/blk0000004c_UNDERFLOW_UNCONNECTED ),
.PATTERNDETECT(\NLW_blk00000001/blk0000004c_PATTERNDETECT_UNCONNECTED ),
.RSTALUMODE(\blk00000001/sig000001d8 ),
.RSTALLCARRYIN(\blk00000001/sig000001d8 ),
.CED(\blk00000001/sig000001d8 ),
.RSTD(\blk00000001/sig000001d8 ),
.CEALUMODE(\blk00000001/sig000001d8 ),
.CEA2(aclken),
.CLK(aclk),
.CEA1(\blk00000001/sig000001d8 ),
.RSTB(\blk00000001/sig000001d8 ),
.OVERFLOW(\NLW_blk00000001/blk0000004c_OVERFLOW_UNCONNECTED ),
.CECTRL(\blk00000001/sig000001d8 ),
.CEM(aclken),
.CARRYIN(\blk00000001/sig000001d8 ),
.CARRYCASCIN(\blk00000001/sig000001d8 ),
.RSTINMODE(\blk00000001/sig000001d8 ),
.CEINMODE(\blk00000001/sig000001d8 ),
.RSTP(\blk00000001/sig000001d8 ),
.ACOUT({\NLW_blk00000001/blk0000004c_ACOUT<29>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_ACOUT<27>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_ACOUT<25>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_ACOUT<23>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_ACOUT<21>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_ACOUT<19>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_ACOUT<17>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_ACOUT<15>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_ACOUT<13>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_ACOUT<11>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_ACOUT<9>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_ACOUT<7>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_ACOUT<5>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_ACOUT<3>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_ACOUT<1>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<0>_UNCONNECTED }),
.OPMODE({\blk00000001/sig000001d8 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 ,
\blk00000001/sig000001d8 , \blk00000001/sig00000132 }),
.PCIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.ALUMODE({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.C({\blk00000001/sig00000112 , \blk00000001/sig00000112 , \blk00000001/sig00000112 , \blk00000001/sig00000112 , \blk00000001/sig00000112 ,
\blk00000001/sig00000112 , \blk00000001/sig00000112 , \blk00000001/sig00000112 , \blk00000001/sig00000112 , \blk00000001/sig00000112 ,
\blk00000001/sig00000112 , \blk00000001/sig00000112 , \blk00000001/sig00000112 , \blk00000001/sig00000112 , \blk00000001/sig00000112 ,
\blk00000001/sig00000112 , \blk00000001/sig00000112 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig00000112 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.CARRYOUT({\NLW_blk00000001/blk0000004c_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000001/blk0000004c_CARRYOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000001/blk0000004c_CARRYOUT<0>_UNCONNECTED }),
.INMODE({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.BCIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.B({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig0000011a , \blk00000001/sig00000119 , \blk00000001/sig00000118 , \blk00000001/sig00000117 , \blk00000001/sig00000116 ,
\blk00000001/sig00000115 , \blk00000001/sig00000114 , \blk00000001/sig00000113 }),
.BCOUT({\NLW_blk00000001/blk0000004c_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk0000004c_BCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk0000004c_BCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk0000004c_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk0000004c_BCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk0000004c_BCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk0000004c_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk0000004c_BCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk0000004c_BCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk0000004c_BCOUT<0>_UNCONNECTED }),
.D({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.P({\NLW_blk00000001/blk0000004c_P<47>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<46>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_P<45>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<44>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<43>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_P<42>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<41>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<40>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_P<39>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<38>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<37>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_P<36>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<35>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_P<33>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<32>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_P<30>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<29>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_P<27>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<26>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<25>_UNCONNECTED ,
\blk00000001/sig0000008f , \blk00000001/sig0000008e , \blk00000001/sig0000008d , \blk00000001/sig0000008c , \blk00000001/sig0000008b ,
\blk00000001/sig0000008a , \blk00000001/sig00000089 , \blk00000001/sig00000088 , \blk00000001/sig00000087 , \blk00000001/sig00000086 ,
\blk00000001/sig00000085 , \blk00000001/sig00000084 , \blk00000001/sig00000083 , \blk00000001/sig00000082 , \blk00000001/sig00000081 ,
\blk00000001/sig00000080 , \blk00000001/sig0000007f , \blk00000001/sig0000007e , \blk00000001/sig0000007d , \blk00000001/sig0000007c ,
\blk00000001/sig0000007b , \blk00000001/sig0000007a , \NLW_blk00000001/blk0000004c_P<2>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<1>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_P<0>_UNCONNECTED }),
.A({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig00000132 , \blk00000001/sig00000131 , \blk00000001/sig00000130 , \blk00000001/sig0000012f ,
\blk00000001/sig0000012e , \blk00000001/sig0000012d , \blk00000001/sig0000012c , \blk00000001/sig0000012b , \blk00000001/sig0000012a ,
\blk00000001/sig00000129 , \blk00000001/sig00000128 , \blk00000001/sig00000127 , \blk00000001/sig00000126 , \blk00000001/sig00000125 ,
\blk00000001/sig00000124 , \blk00000001/sig00000123 , \blk00000001/sig00000122 , \blk00000001/sig00000121 , \blk00000001/sig00000120 ,
\blk00000001/sig0000011f , \blk00000001/sig0000011e , \blk00000001/sig0000011d , \blk00000001/sig0000011c , \blk00000001/sig0000011b }),
.PCOUT({\NLW_blk00000001/blk0000004c_PCOUT<47>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<46>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<45>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<44>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<43>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<42>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<41>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<40>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<39>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<38>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<37>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<36>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<35>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<34>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<33>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<32>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<31>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<29>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<27>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<25>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<23>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<21>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<19>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<0>_UNCONNECTED }),
.ACIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.CARRYINSEL({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000004b (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000c0 ),
.Q(\blk00000001/sig00000113 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000004a (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000c1 ),
.Q(\blk00000001/sig00000114 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000049 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000c2 ),
.Q(\blk00000001/sig00000115 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000048 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000c3 ),
.Q(\blk00000001/sig00000116 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000047 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000c4 ),
.Q(\blk00000001/sig00000117 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000046 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000c5 ),
.Q(\blk00000001/sig00000118 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000045 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000c6 ),
.Q(\blk00000001/sig00000119 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000044 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000c7 ),
.Q(\blk00000001/sig0000011a )
);
DSP48E1 #(
.ACASCREG ( 1 ),
.ADREG ( 1 ),
.ALUMODEREG ( 0 ),
.AREG ( 1 ),
.AUTORESET_PATDET ( "NO_RESET" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 2 ),
.BREG ( 2 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 0 ),
.CARRYINSELREG ( 0 ),
.CREG ( 0 ),
.DREG ( 0 ),
.INMODEREG ( 0 ),
.MASK ( 48'h3FFFFFFFFFFF ),
.MREG ( 1 ),
.OPMODEREG ( 0 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.USE_DPORT ( 1 ),
.USE_MULT ( "MULTIPLY" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
\blk00000001/blk00000043 (
.PATTERNBDETECT(\NLW_blk00000001/blk00000043_PATTERNBDETECT_UNCONNECTED ),
.RSTC(\blk00000001/sig000001d8 ),
.CEB1(aclken),
.CEAD(aclken),
.MULTSIGNOUT(\NLW_blk00000001/blk00000043_MULTSIGNOUT_UNCONNECTED ),
.CEC(\blk00000001/sig000001d8 ),
.RSTM(\blk00000001/sig000001d8 ),
.MULTSIGNIN(\blk00000001/sig000001d8 ),
.CEB2(aclken),
.RSTCTRL(\blk00000001/sig000001d8 ),
.CEP(aclken),
.CARRYCASCOUT(\NLW_blk00000001/blk00000043_CARRYCASCOUT_UNCONNECTED ),
.RSTA(\blk00000001/sig000001d8 ),
.CECARRYIN(\blk00000001/sig000001d8 ),
.UNDERFLOW(\NLW_blk00000001/blk00000043_UNDERFLOW_UNCONNECTED ),
.PATTERNDETECT(\NLW_blk00000001/blk00000043_PATTERNDETECT_UNCONNECTED ),
.RSTALUMODE(\blk00000001/sig000001d8 ),
.RSTALLCARRYIN(\blk00000001/sig000001d8 ),
.CED(\blk00000001/sig000001d8 ),
.RSTD(\blk00000001/sig000001d8 ),
.CEALUMODE(\blk00000001/sig000001d8 ),
.CEA2(aclken),
.CLK(aclk),
.CEA1(\blk00000001/sig000001d8 ),
.RSTB(\blk00000001/sig000001d8 ),
.OVERFLOW(\NLW_blk00000001/blk00000043_OVERFLOW_UNCONNECTED ),
.CECTRL(\blk00000001/sig000001d8 ),
.CEM(aclken),
.CARRYIN(\blk00000001/sig000001d8 ),
.CARRYCASCIN(\blk00000001/sig000001d8 ),
.RSTINMODE(\blk00000001/sig000001d8 ),
.CEINMODE(\blk00000001/sig000001d8 ),
.RSTP(\blk00000001/sig000001d8 ),
.ACOUT({\NLW_blk00000001/blk00000043_ACOUT<29>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_ACOUT<27>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_ACOUT<25>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_ACOUT<23>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_ACOUT<21>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_ACOUT<19>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_ACOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_ACOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_ACOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_ACOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_ACOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_ACOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_ACOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_ACOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_ACOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<0>_UNCONNECTED }),
.OPMODE({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 ,
\blk00000001/sig000001d8 , \blk00000001/sig00000132 }),
.PCIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.ALUMODE({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.C({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.CARRYOUT({\NLW_blk00000001/blk00000043_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000043_CARRYOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000043_CARRYOUT<0>_UNCONNECTED }),
.INMODE({\blk00000001/sig000001d8 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.BCIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.B({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig00000111 , \blk00000001/sig00000110 , \blk00000001/sig0000010f , \blk00000001/sig0000010e , \blk00000001/sig0000010d ,
\blk00000001/sig0000010c , \blk00000001/sig0000010b , \blk00000001/sig0000010a }),
.BCOUT({\NLW_blk00000001/blk00000043_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000043_BCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000043_BCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000043_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000043_BCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000043_BCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000043_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000043_BCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000043_BCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000043_BCOUT<0>_UNCONNECTED }),
.D({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.P({\NLW_blk00000001/blk00000043_P<47>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<46>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_P<45>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<44>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<43>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_P<42>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<41>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<40>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_P<39>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<38>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<37>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_P<36>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<35>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_P<33>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<32>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_P<30>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<29>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_P<27>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<26>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<25>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_P<24>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<23>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_P<21>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<20>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<19>_UNCONNECTED ,
\blk00000001/sig000000d3 , \blk00000001/sig000000d2 , \blk00000001/sig000000d1 , \blk00000001/sig000000d0 ,
\NLW_blk00000001/blk00000043_P<14>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<13>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_P<11>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<10>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<9>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_P<8>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<7>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<6>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_P<5>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<4>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<3>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_P<2>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<1>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<0>_UNCONNECTED }),
.A({\blk00000001/sig000000dd , \blk00000001/sig000000dd , \blk00000001/sig000000dd , \blk00000001/sig000000dd , \blk00000001/sig000000dd ,
\blk00000001/sig000000dd , \blk00000001/sig000000dd , \blk00000001/sig000000dd , \blk00000001/sig000000dd , \blk00000001/sig000000dd ,
\blk00000001/sig000000dd , \blk00000001/sig000000dd , \blk00000001/sig000000dd , \blk00000001/sig000000dd , \blk00000001/sig000000dd ,
\blk00000001/sig000000dd , \blk00000001/sig000000dd , \blk00000001/sig000000dd , \blk00000001/sig000000dd , \blk00000001/sig000000dd ,
\blk00000001/sig000000dd , \blk00000001/sig000000dc , \blk00000001/sig000000db , \blk00000001/sig000000da , \blk00000001/sig000000d9 ,
\blk00000001/sig000000d8 , \blk00000001/sig000000d7 , \blk00000001/sig000000d6 , \blk00000001/sig000000d5 , \blk00000001/sig000000d4 }),
.PCOUT({\NLW_blk00000001/blk00000043_PCOUT<47>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<46>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<45>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<44>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<43>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<42>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<41>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<40>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<39>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<38>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<37>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<36>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<35>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<34>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<33>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<32>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<31>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<29>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<27>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<25>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<23>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<21>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<19>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<0>_UNCONNECTED }),
.ACIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.CARRYINSEL({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000003a (
.C(aclk),
.CE(aclken),
.D(s_axis_a_tdata[20]),
.Q(\blk00000001/sig000000fa )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000039 (
.C(aclk),
.CE(aclken),
.D(s_axis_a_tdata[21]),
.Q(\blk00000001/sig000000fb )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000038 (
.C(aclk),
.CE(aclken),
.D(s_axis_a_tdata[22]),
.Q(\blk00000001/sig000000fc )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000037 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000f6 ),
.Q(\blk00000001/sig000000fd )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000036 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000f7 ),
.Q(\blk00000001/sig000000fe )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000035 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000f8 ),
.Q(\blk00000001/sig000000ff )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000034 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000f9 ),
.Q(\blk00000001/sig00000100 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000033 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000ed ),
.Q(\blk00000001/sig00000109 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000032 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000ee ),
.Q(\blk00000001/sig00000108 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000031 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000ef ),
.Q(\blk00000001/sig00000107 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000030 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000f0 ),
.Q(\blk00000001/sig00000106 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000002f (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000f1 ),
.Q(\blk00000001/sig00000105 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000002e (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000f2 ),
.Q(\blk00000001/sig00000104 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000002d (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000f3 ),
.Q(\blk00000001/sig00000103 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000002c (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000f4 ),
.Q(\blk00000001/sig00000102 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000002b (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000f5 ),
.Q(\blk00000001/sig00000101 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000002a (
.I0(\blk00000001/sig000000d0 ),
.I1(\blk00000001/sig000000c8 ),
.O(\blk00000001/sig000000bf )
);
MUXCY \blk00000001/blk00000029 (
.CI(\blk00000001/sig000001d8 ),
.DI(\blk00000001/sig000000d0 ),
.S(\blk00000001/sig000000bf ),
.O(\blk00000001/sig000000be )
);
XORCY \blk00000001/blk00000028 (
.CI(\blk00000001/sig000001d8 ),
.LI(\blk00000001/sig000000bf ),
.O(\blk00000001/sig000000c0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000027 (
.I0(\blk00000001/sig000000d1 ),
.I1(\blk00000001/sig000000c9 ),
.O(\blk00000001/sig000000bd )
);
MUXCY \blk00000001/blk00000026 (
.CI(\blk00000001/sig000000be ),
.DI(\blk00000001/sig000000d1 ),
.S(\blk00000001/sig000000bd ),
.O(\blk00000001/sig000000bc )
);
XORCY \blk00000001/blk00000025 (
.CI(\blk00000001/sig000000be ),
.LI(\blk00000001/sig000000bd ),
.O(\blk00000001/sig000000c1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000024 (
.I0(\blk00000001/sig000000d2 ),
.I1(\blk00000001/sig000000ca ),
.O(\blk00000001/sig000000bb )
);
MUXCY \blk00000001/blk00000023 (
.CI(\blk00000001/sig000000bc ),
.DI(\blk00000001/sig000000d2 ),
.S(\blk00000001/sig000000bb ),
.O(\blk00000001/sig000000ba )
);
XORCY \blk00000001/blk00000022 (
.CI(\blk00000001/sig000000bc ),
.LI(\blk00000001/sig000000bb ),
.O(\blk00000001/sig000000c2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000021 (
.I0(\blk00000001/sig000000d3 ),
.I1(\blk00000001/sig000000cb ),
.O(\blk00000001/sig000000b9 )
);
MUXCY \blk00000001/blk00000020 (
.CI(\blk00000001/sig000000ba ),
.DI(\blk00000001/sig000000d3 ),
.S(\blk00000001/sig000000b9 ),
.O(\blk00000001/sig000000b8 )
);
XORCY \blk00000001/blk0000001f (
.CI(\blk00000001/sig000000ba ),
.LI(\blk00000001/sig000000b9 ),
.O(\blk00000001/sig000000c3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000001e (
.I0(\blk00000001/sig000000d3 ),
.I1(\blk00000001/sig000000cc ),
.O(\blk00000001/sig000000b7 )
);
MUXCY \blk00000001/blk0000001d (
.CI(\blk00000001/sig000000b8 ),
.DI(\blk00000001/sig000000d3 ),
.S(\blk00000001/sig000000b7 ),
.O(\blk00000001/sig000000b6 )
);
XORCY \blk00000001/blk0000001c (
.CI(\blk00000001/sig000000b8 ),
.LI(\blk00000001/sig000000b7 ),
.O(\blk00000001/sig000000c4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000001b (
.I0(\blk00000001/sig000000d3 ),
.I1(\blk00000001/sig000000cd ),
.O(\blk00000001/sig000000b5 )
);
MUXCY \blk00000001/blk0000001a (
.CI(\blk00000001/sig000000b6 ),
.DI(\blk00000001/sig000000d3 ),
.S(\blk00000001/sig000000b5 ),
.O(\blk00000001/sig000000b4 )
);
XORCY \blk00000001/blk00000019 (
.CI(\blk00000001/sig000000b6 ),
.LI(\blk00000001/sig000000b5 ),
.O(\blk00000001/sig000000c5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000018 (
.I0(\blk00000001/sig000000d3 ),
.I1(\blk00000001/sig000000ce ),
.O(\blk00000001/sig000000b3 )
);
MUXCY \blk00000001/blk00000017 (
.CI(\blk00000001/sig000000b4 ),
.DI(\blk00000001/sig000000d3 ),
.S(\blk00000001/sig000000b3 ),
.O(\blk00000001/sig000000b2 )
);
XORCY \blk00000001/blk00000016 (
.CI(\blk00000001/sig000000b4 ),
.LI(\blk00000001/sig000000b3 ),
.O(\blk00000001/sig000000c6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000015 (
.I0(\blk00000001/sig000000d3 ),
.I1(\blk00000001/sig000000cf ),
.O(\blk00000001/sig000000b1 )
);
XORCY \blk00000001/blk00000014 (
.CI(\blk00000001/sig000000b2 ),
.LI(\blk00000001/sig000000b1 ),
.O(\blk00000001/sig000000c7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000013 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000a4 ),
.Q(\blk00000001/sig00000090 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000012 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000a5 ),
.Q(\blk00000001/sig00000092 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000011 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000009c ),
.Q(\blk00000001/sig00000093 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000010 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000009d ),
.Q(\blk00000001/sig00000094 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000f (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000009e ),
.Q(\blk00000001/sig00000095 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000e (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000009f ),
.Q(\blk00000001/sig00000096 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000d (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000a0 ),
.Q(\blk00000001/sig00000097 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000c (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000a1 ),
.Q(\blk00000001/sig00000098 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000b (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000a2 ),
.Q(\blk00000001/sig00000099 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000a (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000a3 ),
.Q(\blk00000001/sig0000009a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000009 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000aa ),
.Q(\blk00000001/sig000000b0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000008 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000a6 ),
.Q(\blk00000001/sig000000ae )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000007 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000a7 ),
.Q(\blk00000001/sig000000af )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000006 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000ad ),
.Q(\blk00000001/sig000000a9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000005 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000ac ),
.Q(\blk00000001/sig000000a8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000004 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000ab ),
.Q(\blk00000001/sig000000aa )
);
GND \blk00000001/blk00000003 (
.G(\blk00000001/sig000001d8 )
);
VCC \blk00000001/blk00000002 (
.P(\blk00000001/sig00000132 )
);
DSP48E1 #(
.USE_DPORT ( 0 ),
.ADREG ( 0 ),
.AREG ( 1 ),
.ACASCREG ( 1 ),
.BREG ( 1 ),
.BCASCREG ( 1 ),
.CREG ( 0 ),
.MREG ( 1 ),
.PREG ( 1 ),
.CARRYINREG ( 0 ),
.OPMODEREG ( 0 ),
.ALUMODEREG ( 0 ),
.CARRYINSELREG ( 0 ),
.INMODEREG ( 0 ),
.USE_MULT ( "MULTIPLY" ),
.A_INPUT ( "DIRECT" ),
.B_INPUT ( "DIRECT" ),
.DREG ( 0 ),
.SEL_PATTERN ( "PATTERN" ),
.MASK ( 48'h3fffffffffff ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.PATTERN ( 48'h000000000000 ),
.USE_SIMD ( "ONE48" ),
.AUTORESET_PATDET ( "NO_RESET" ),
.SEL_MASK ( "MASK" ))
\blk00000001/blk0000003b/blk0000003e (
.PATTERNBDETECT(\NLW_blk00000001/blk0000003b/blk0000003e_PATTERNBDETECT_UNCONNECTED ),
.RSTC(\blk00000001/blk0000003b/sig000002f5 ),
.CEB1(\blk00000001/blk0000003b/sig000002f5 ),
.CEAD(\blk00000001/blk0000003b/sig000002f5 ),
.MULTSIGNOUT(\NLW_blk00000001/blk0000003b/blk0000003e_MULTSIGNOUT_UNCONNECTED ),
.CEC(\blk00000001/blk0000003b/sig000002f5 ),
.RSTM(\blk00000001/blk0000003b/sig000002f5 ),
.MULTSIGNIN(\NLW_blk00000001/blk0000003b/blk0000003e_MULTSIGNIN_UNCONNECTED ),
.CEB2(aclken),
.RSTCTRL(\blk00000001/blk0000003b/sig000002f5 ),
.CEP(aclken),
.CARRYCASCOUT(\NLW_blk00000001/blk0000003b/blk0000003e_CARRYCASCOUT_UNCONNECTED ),
.RSTA(\blk00000001/blk0000003b/sig000002f5 ),
.CECARRYIN(\blk00000001/blk0000003b/sig000002f5 ),
.UNDERFLOW(\NLW_blk00000001/blk0000003b/blk0000003e_UNDERFLOW_UNCONNECTED ),
.PATTERNDETECT(\NLW_blk00000001/blk0000003b/blk0000003e_PATTERNDETECT_UNCONNECTED ),
.RSTALUMODE(\blk00000001/blk0000003b/sig000002f5 ),
.RSTALLCARRYIN(\blk00000001/blk0000003b/sig000002f5 ),
.CED(\blk00000001/blk0000003b/sig000002f5 ),
.RSTD(\blk00000001/blk0000003b/sig000002f5 ),
.CEALUMODE(\blk00000001/blk0000003b/sig000002f5 ),
.CEA2(aclken),
.CLK(aclk),
.CEA1(\blk00000001/blk0000003b/sig000002f5 ),
.RSTB(\blk00000001/blk0000003b/sig000002f5 ),
.OVERFLOW(\NLW_blk00000001/blk0000003b/blk0000003e_OVERFLOW_UNCONNECTED ),
.CECTRL(\blk00000001/blk0000003b/sig000002f5 ),
.CEM(aclken),
.CARRYIN(\blk00000001/blk0000003b/sig000002f5 ),
.CARRYCASCIN(\NLW_blk00000001/blk0000003b/blk0000003e_CARRYCASCIN_UNCONNECTED ),
.RSTINMODE(\blk00000001/blk0000003b/sig000002f5 ),
.CEINMODE(\blk00000001/blk0000003b/sig000002f5 ),
.RSTP(\blk00000001/blk0000003b/sig000002f5 ),
.ACOUT({\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<29>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<27>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<25>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<23>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<21>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<19>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<17>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<15>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<13>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<11>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<9>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<7>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<5>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<3>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<1>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<0>_UNCONNECTED }),
.OPMODE({\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f4 }),
.PCIN({\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<47>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<46>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<45>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<44>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<43>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<42>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<41>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<40>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<39>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<38>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<37>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<36>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<35>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<34>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<33>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<32>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<31>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<29>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<27>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<25>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<23>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<21>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<19>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<17>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<15>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<13>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<11>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<9>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<7>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<5>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<3>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<1>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<0>_UNCONNECTED }),
.ALUMODE({\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 }),
.C({\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 }),
.CARRYOUT({\NLW_blk00000001/blk0000003b/blk0000003e_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_CARRYOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_CARRYOUT<0>_UNCONNECTED }),
.INMODE({\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 }),
.BCIN({\NLW_blk00000001/blk0000003b/blk0000003e_BCIN<17>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCIN<15>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCIN<13>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCIN<11>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCIN<9>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCIN<7>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCIN<5>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCIN<3>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCIN<1>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<0>_UNCONNECTED }),
.B({\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/sig00000132 , \blk00000001/sig000000fc ,
\blk00000001/sig000000fb , \blk00000001/sig000000fa , \blk00000001/sig00000100 , \blk00000001/sig000000ff , \blk00000001/sig000000fe ,
\blk00000001/sig000000fd , \blk00000001/sig00000132 , \blk00000001/sig00000132 }),
.BCOUT({\NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<0>_UNCONNECTED }),
.D({\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 }),
.P({\NLW_blk00000001/blk0000003b/blk0000003e_P<47>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_P<46>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_P<45>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_P<44>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_P<43>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_P<42>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_P<41>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_P<40>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_P<39>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_P<38>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_P<37>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_P<36>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_P<35>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_P<33>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_P<32>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_P<31>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_P<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_P<29>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_P<27>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_P<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_P<25>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_P<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_P<23>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_P<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_P<21>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_P<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_P<19>_UNCONNECTED , \blk00000001/blk0000003b/sig000002e1 , \blk00000001/sig000000ec ,
\blk00000001/sig000000eb , \blk00000001/sig000000ea , \blk00000001/sig000000e9 , \blk00000001/sig000000e8 , \blk00000001/sig000000e7 ,
\blk00000001/sig000000e6 , \blk00000001/sig000000e5 , \blk00000001/blk0000003b/sig000002ea , \blk00000001/blk0000003b/sig000002eb ,
\blk00000001/blk0000003b/sig000002ec , \blk00000001/blk0000003b/sig000002ed , \blk00000001/blk0000003b/sig000002ee ,
\blk00000001/blk0000003b/sig000002ef , \blk00000001/blk0000003b/sig000002f0 , \blk00000001/blk0000003b/sig000002f1 ,
\blk00000001/blk0000003b/sig000002f2 , \blk00000001/blk0000003b/sig000002f3 }),
.A({\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/sig00000109 ,
\blk00000001/sig00000108 , \blk00000001/sig00000107 , \blk00000001/sig00000106 , \blk00000001/sig00000105 , \blk00000001/sig00000104 ,
\blk00000001/sig00000103 , \blk00000001/sig00000102 , \blk00000001/sig00000101 }),
.PCOUT({\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<47>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<46>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<45>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<44>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<43>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<42>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<41>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<40>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<39>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<38>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<37>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<36>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<35>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<34>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<33>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<32>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<31>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<29>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<27>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<25>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<23>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<21>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<19>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<0>_UNCONNECTED }),
.ACIN({\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<29>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<27>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<25>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<23>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<21>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<19>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<17>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<15>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<13>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<11>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<9>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<7>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<5>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<3>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<1>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<0>_UNCONNECTED }),
.CARRYINSEL({\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 })
);
GND \blk00000001/blk0000003b/blk0000003d (
.G(\blk00000001/blk0000003b/sig000002f5 )
);
VCC \blk00000001/blk0000003b/blk0000003c (
.P(\blk00000001/blk0000003b/sig000002f4 )
);
DSP48E1 #(
.USE_DPORT ( 0 ),
.ADREG ( 0 ),
.AREG ( 1 ),
.ACASCREG ( 1 ),
.BREG ( 1 ),
.BCASCREG ( 1 ),
.CREG ( 0 ),
.MREG ( 1 ),
.PREG ( 1 ),
.CARRYINREG ( 0 ),
.OPMODEREG ( 0 ),
.ALUMODEREG ( 0 ),
.CARRYINSELREG ( 0 ),
.INMODEREG ( 0 ),
.USE_MULT ( "MULTIPLY" ),
.A_INPUT ( "DIRECT" ),
.B_INPUT ( "DIRECT" ),
.DREG ( 0 ),
.SEL_PATTERN ( "PATTERN" ),
.MASK ( 48'h3fffffffffff ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.PATTERN ( 48'h000000000000 ),
.USE_SIMD ( "ONE48" ),
.AUTORESET_PATDET ( "NO_RESET" ),
.SEL_MASK ( "MASK" ))
\blk00000001/blk0000003f/blk00000042 (
.PATTERNBDETECT(\NLW_blk00000001/blk0000003f/blk00000042_PATTERNBDETECT_UNCONNECTED ),
.RSTC(\blk00000001/blk0000003f/sig00000313 ),
.CEB1(\blk00000001/blk0000003f/sig00000313 ),
.CEAD(\blk00000001/blk0000003f/sig00000313 ),
.MULTSIGNOUT(\NLW_blk00000001/blk0000003f/blk00000042_MULTSIGNOUT_UNCONNECTED ),
.CEC(\blk00000001/blk0000003f/sig00000313 ),
.RSTM(\blk00000001/blk0000003f/sig00000313 ),
.MULTSIGNIN(\NLW_blk00000001/blk0000003f/blk00000042_MULTSIGNIN_UNCONNECTED ),
.CEB2(aclken),
.RSTCTRL(\blk00000001/blk0000003f/sig00000313 ),
.CEP(aclken),
.CARRYCASCOUT(\NLW_blk00000001/blk0000003f/blk00000042_CARRYCASCOUT_UNCONNECTED ),
.RSTA(\blk00000001/blk0000003f/sig00000313 ),
.CECARRYIN(\blk00000001/blk0000003f/sig00000313 ),
.UNDERFLOW(\NLW_blk00000001/blk0000003f/blk00000042_UNDERFLOW_UNCONNECTED ),
.PATTERNDETECT(\NLW_blk00000001/blk0000003f/blk00000042_PATTERNDETECT_UNCONNECTED ),
.RSTALUMODE(\blk00000001/blk0000003f/sig00000313 ),
.RSTALLCARRYIN(\blk00000001/blk0000003f/sig00000313 ),
.CED(\blk00000001/blk0000003f/sig00000313 ),
.RSTD(\blk00000001/blk0000003f/sig00000313 ),
.CEALUMODE(\blk00000001/blk0000003f/sig00000313 ),
.CEA2(aclken),
.CLK(aclk),
.CEA1(\blk00000001/blk0000003f/sig00000313 ),
.RSTB(\blk00000001/blk0000003f/sig00000313 ),
.OVERFLOW(\NLW_blk00000001/blk0000003f/blk00000042_OVERFLOW_UNCONNECTED ),
.CECTRL(\blk00000001/blk0000003f/sig00000313 ),
.CEM(aclken),
.CARRYIN(\blk00000001/blk0000003f/sig00000313 ),
.CARRYCASCIN(\NLW_blk00000001/blk0000003f/blk00000042_CARRYCASCIN_UNCONNECTED ),
.RSTINMODE(\blk00000001/blk0000003f/sig00000313 ),
.CEINMODE(\blk00000001/blk0000003f/sig00000313 ),
.RSTP(\blk00000001/blk0000003f/sig00000313 ),
.ACOUT({\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<29>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<27>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<25>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<23>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<21>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<19>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<17>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<15>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<13>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<11>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<9>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<7>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<5>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<3>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<1>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<0>_UNCONNECTED }),
.OPMODE({\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000312 }),
.PCIN({\NLW_blk00000001/blk0000003f/blk00000042_PCIN<47>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<46>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<45>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<44>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<43>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<42>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<41>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<40>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<39>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<38>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<37>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<36>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<35>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<34>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<33>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<32>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<31>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<29>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<27>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<25>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<23>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<21>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<19>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<17>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<15>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<13>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<11>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<9>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<7>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<5>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<3>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<1>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<0>_UNCONNECTED }),
.ALUMODE({\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 }),
.C({\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 }),
.CARRYOUT({\NLW_blk00000001/blk0000003f/blk00000042_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_CARRYOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_CARRYOUT<0>_UNCONNECTED }),
.INMODE({\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 }),
.BCIN({\NLW_blk00000001/blk0000003f/blk00000042_BCIN<17>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCIN<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCIN<15>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCIN<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCIN<13>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCIN<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCIN<11>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCIN<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCIN<9>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCIN<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCIN<7>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCIN<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCIN<5>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCIN<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCIN<3>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCIN<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCIN<1>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCIN<0>_UNCONNECTED }),
.B({\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/sig00000132 , \blk00000001/sig000000e4 , \blk00000001/sig000000e3 , \blk00000001/sig000000e2 ,
\blk00000001/sig000000e1 , \blk00000001/sig000000e0 , \blk00000001/sig000000df , \blk00000001/sig000000de }),
.BCOUT({\NLW_blk00000001/blk0000003f/blk00000042_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<0>_UNCONNECTED }),
.D({\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 }),
.P({\NLW_blk00000001/blk0000003f/blk00000042_P<47>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<46>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<45>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<44>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<43>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<42>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<41>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<40>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<39>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<38>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<37>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<36>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<35>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<33>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<32>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<31>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<29>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<27>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<25>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<23>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<21>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<19>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<17>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<15>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<13>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<11>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<10>_UNCONNECTED , \blk00000001/sig000000dd ,
\blk00000001/sig000000dc , \blk00000001/sig000000db , \blk00000001/sig000000da , \blk00000001/sig000000d9 , \blk00000001/sig000000d8 ,
\blk00000001/sig000000d7 , \blk00000001/sig000000d6 , \blk00000001/sig000000d5 , \blk00000001/sig000000d4 }),
.A({\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/sig000000ec , \blk00000001/sig000000eb , \blk00000001/sig000000ea , \blk00000001/sig000000e9 ,
\blk00000001/sig000000e8 , \blk00000001/sig000000e7 , \blk00000001/sig000000e6 , \blk00000001/sig000000e5 }),
.PCOUT({\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<47>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<46>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<45>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<44>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<43>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<42>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<41>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<40>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<39>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<38>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<37>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<36>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<35>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<34>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<33>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<32>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<31>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<29>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<27>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<25>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<23>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<21>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<19>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<0>_UNCONNECTED }),
.ACIN({\NLW_blk00000001/blk0000003f/blk00000042_ACIN<29>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACIN<27>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACIN<25>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACIN<23>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACIN<21>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACIN<19>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACIN<17>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACIN<15>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACIN<13>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACIN<11>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACIN<9>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACIN<7>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACIN<5>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACIN<3>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACIN<1>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<0>_UNCONNECTED }),
.CARRYINSEL({\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 })
);
GND \blk00000001/blk0000003f/blk00000041 (
.G(\blk00000001/blk0000003f/sig00000313 )
);
VCC \blk00000001/blk0000003f/blk00000040 (
.P(\blk00000001/blk0000003f/sig00000312 )
);
endmodule
|
module np_core
#(parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH=DATA_WIDTH/8,
parameter UDP_REG_SRC_WIDTH = 2,
parameter INPUT_ARBITER_STAGE_NUM = 2,
parameter IO_QUEUE_STAGE_NUM = 8'hff,
parameter NUM_OUTPUT_QUEUES = 8,
parameter NUM_IQ_BITS = 3,
parameter STAGE_NUM = 4,
parameter CPU_QUEUE_NUM = 0)
(// --- data path interface
output [DATA_WIDTH-1:0] out_data,
output [CTRL_WIDTH-1:0] out_ctrl,
output out_wr,
input out_rdy,
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
input in_wr,
output in_rdy,
// --- Register interface
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [UDP_REG_SRC_WIDTH-1:0] reg_src_in,
output reg_req_out,
output reg_ack_out,
output reg_rd_wr_L_out,
output [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output [UDP_REG_SRC_WIDTH-1:0] reg_src_out,
// --- Misc
input clk,
input core_sp_clk,
input statemac_clk,
input reset,
//for monitor
// for security monitoring
output [31:0] instruction_sec_mon,
output [31:0] prog_counter_sec_mon,
output [31:0] ppu_mem_addr,
input packet_drop
);
assign reg_req_out = reg_req_in;
assign reg_ack_out = reg_ack_in;
assign reg_rd_wr_L_out = reg_rd_wr_L_in;
assign reg_addr_out = reg_addr_in;
assign reg_data_out = reg_data_in;
assign reg_src_out = reg_src_in;
wire [63:0] fc_out_data0;
wire [23:0] fc_out_pkt_route0;
wire fc_out_wr0;
wire fc_out_req0;
wire fc_out_ack0;
wire fc_out_bypass0;
wire [63:0] fc_out_data1;
wire [23:0] fc_out_pkt_route1;
wire fc_out_wr1;
wire fc_out_req1;
wire fc_out_ack1;
wire fc_out_bypass1;
wire [63:0] fc_out_data2;
wire [23:0] fc_out_pkt_route2;
wire fc_out_wr2;
wire fc_out_req2;
wire fc_out_ack2;
wire fc_out_bypass2;
wire [63:0] fc_out_data3;
wire [23:0] fc_out_pkt_route3;
wire fc_out_wr3;
wire fc_out_req3;
wire fc_out_ack3;
wire fc_out_bypass3;
wire [63:0] pg_out_data0;
wire [23:0] pg_out_pkt_route0;
wire pg_out_wr0;
wire pg_out_req0;
wire pg_out_ack0;
wire pg_out_bop0;
wire pg_out_eop0;
wire pg_out_rdy0;
wire pg_out_bypass0;
wire [63:0] pg_out_data1;
wire [23:0] pg_out_pkt_route1;
wire pg_out_wr1;
wire pg_out_req1;
wire pg_out_ack1;
wire pg_out_bop1;
wire pg_out_eop1;
wire pg_out_rdy1;
wire pg_out_bypass1;
wire [63:0] pg_out_data2;
wire [23:0] pg_out_pkt_route2;
wire pg_out_wr2;
wire pg_out_req2;
wire pg_out_ack2;
wire pg_out_bop2;
wire pg_out_eop2;
wire pg_out_rdy2;
wire pg_out_bypass2;
wire [63:0] pg_out_data3;
wire [23:0] pg_out_pkt_route3;
wire pg_out_wr3;
wire pg_out_req3;
wire pg_out_ack3;
wire pg_out_bop3;
wire pg_out_eop3;
wire pg_out_rdy3;
wire [3:0] four_bit_hash_output0,four_bit_hash_output0_cm,four_bit_hash_output0_ipv4;
wire [31:0] pc_input_hash_wire0,pc_input_hash_wire0_cm,pc_input_hash_wire0_ipv4;
wire new_inst_signal0,new_inst_signal0_cm,new_inst_signal0_ipv4;
wire [3:0] four_bit_hash_output1,four_bit_hash_output1_cm,four_bit_hash_output1_ipv4;
wire [31:0] pc_input_hash_wire1,pc_input_hash_wire1_cm,pc_input_hash_wire1_ipv4;
wire new_inst_signal1,new_inst_signal1_cm,new_inst_signal1_ipv4;
wire [3:0] four_bit_hash_output2,four_bit_hash_output2_cm,four_bit_hash_output2_ipv4;
wire [31:0] pc_input_hash_wire2,pc_input_hash_wire2_cm,pc_input_hash_wire2_ipv4;
wire new_inst_signal2,new_inst_signal2_cm,new_inst_signal2_ipv4;
wire [3:0] four_bit_hash_output3,four_bit_hash_output3_cm,four_bit_hash_output3_ipv4;
wire [31:0] pc_input_hash_wire3,pc_input_hash_wire3_cm,pc_input_hash_wire3_ipv4;
wire new_inst_signal3,new_inst_signal3_cm,new_inst_signal3_ipv4;
wire packet_drop_signal0_ipv4;
wire packet_drop_signal1_ipv4;
wire packet_drop_signal2_ipv4;
wire packet_drop_signal3_ipv4;
wire packet_drop_signal0_cm;
wire packet_drop_signal1_cm;
wire packet_drop_signal2_cm;
wire packet_drop_signal3_cm;
wire fc_out_protocol0;
wire fc_out_protocol1;
wire fc_out_protocol2;
wire fc_out_protocol3;
/*
wire [35:0] CONTROL0;
wire [239:0] TRIG0;
chipscope_icon_v1_03_a cs_icon (
.CONTROL0(CONTROL0)
);
chipscope_ila_v1_02_a cs_ila (
.CONTROL(CONTROL0),
.CLK(clk),
.TRIG0(TRIG0)
);
assign TRIG0[63:0] = fc_out_data0;
assign TRIG0[79:64] = fc_out_pkt_route0;
assign TRIG0[80] = fc_out_wr0;
assign TRIG0[81] = fc_out_req0;
assign TRIG0[82] = fc_out_ack0;
assign TRIG0[163:100] = pg_out_data3;
assign TRIG0[179:164] = pg_out_pkt_route3;
assign TRIG0[180] = pg_out_wr3;
assign TRIG0[181] = pg_out_req3;
assign TRIG0[182] = pg_out_ack3;
assign TRIG0[183] = pg_out_bop3;
assign TRIG0[184] = pg_out_eop3;
assign TRIG0[185] = pg_out_rdy3;
*/
wire [63:0] data01;
wire [23:0] pkt_route01;
wire wr01;
wire req01;
wire ack01;
wire bypass01;
wire [63:0] data10;
wire [23:0] pkt_route10;
wire wr10;
wire req10;
wire ack10;
wire bypass10;
wire [63:0] data02;
wire [23:0] pkt_route02;
wire wr02;
wire req02;
wire ack02;
wire bypass02;
wire [63:0] data20;
wire [23:0] pkt_route20;
wire wr20;
wire req20;
wire ack20;
wire bypass20;
wire [63:0] data13;
wire [23:0] pkt_route13;
wire wr13;
wire req13;
wire ack13;
wire bypass13;
wire [63:0] data31;
wire [23:0] pkt_route31;
wire wr31;
wire req31;
wire ack31;
wire bypass31;
wire [63:0] data23;
wire [23:0] pkt_route23;
wire wr23;
wire req23;
wire ack23;
wire bypass23;
wire [63:0] data32;
wire [23:0] pkt_route32;
wire wr32;
wire req32;
wire ack32;
wire bypass32;
wire [239:0] TRIG_IS0;
wire [239:0] TRIG_IS2;
wire [239:0] TRIG_OS0;
wire reset0;
wire reset1;
wire reset2;
wire reset3;
wire packet_drop_core_zero;
wire packet_drop_core_one;
wire packet_drop_core_two;
wire packet_drop_core_three;
wire cam_we;
wire [3:0] cam_wr_addr;
wire [31:0] cam_din;
wire cam_wr_ack;
flow_classification fc(
.out_data0 (fc_out_data0),
.out_pkt_route0 (fc_out_pkt_route0),
.out_wr0 (fc_out_wr0),
.out_req0 (fc_out_req0),
.out_ack0 (fc_out_ack0),
.out_bypass0 (fc_out_bypass0),
.out_protocol0 (fc_out_protocol0),
.out_data1 (fc_out_data1),
.out_pkt_route1 (fc_out_pkt_route1),
.out_wr1 (fc_out_wr1),
.out_req1 (fc_out_req1),
.out_ack1 (fc_out_ack1),
.out_bypass1 (fc_out_bypass1),
.out_protocol1(fc_out_protocol1),
.out_data2 (fc_out_data2),
.out_pkt_route2 (fc_out_pkt_route2),
.out_wr2 (fc_out_wr2),
.out_req2 (fc_out_req2),
.out_ack2 (fc_out_ack2),
.out_bypass2 (fc_out_bypass2),
.out_protocol2(fc_out_protocol2),
.out_data3 (fc_out_data3),
.out_pkt_route3 (fc_out_pkt_route3),
.out_wr3 (fc_out_wr3),
.out_req3 (fc_out_req3),
.out_ack3 (fc_out_ack3),
.out_bypass3 (fc_out_bypass3),
.out_protocol3(fc_out_protocol3),
.in_data (in_data),
.in_ctrl (in_ctrl),
.in_wr (in_wr),
.in_rdy (in_rdy),
.clk (clk),
.reset (reset)
);
/*
ppu ppu0(
.clk (clk),
.core_sp_clk (core_sp_clk),
.reset (reset),
.TRIG_IS (TRIG_IS0),
.TRIG_OS (TRIG_OS0),
.in_data0 (data10),
.in_pkt_route0 (pkt_route10),
.in_wr0 (wr10),
.in_req0 (req10),
.in_ack0 (ack10),
.in_bypass0 (bypass10),
.in_data1 (fc_out_data0),
.in_pkt_route1 (fc_out_pkt_route0),
.in_wr1 (fc_out_wr0),
.in_req1 (fc_out_req0),
.in_ack1 (fc_out_ack0),
.in_bypass1 (fc_out_bypass0),
.in_data2 (),
.in_pkt_route2 (),
.in_wr2 (),
.in_req2 (),
.in_ack2 (),
.in_bypass2 (),
.in_data3 (data20),
.in_pkt_route3 (pkt_route20),
.in_wr3 (wr20),
.in_req3 (req20),
.in_ack3 (ack20),
.in_bypass3 (bypass20),
.out_data0 (data01),
.out_pkt_route0 (pkt_route01),
.out_wr0 (wr01),
.out_req0 (req01),
.out_ack0 (ack01),
.out_bop0 (),
.out_eop0 (),
.out_rdy0 (1'b1),
.out_bypass0 (bypass01),
.out_data1 (),
.out_pkt_route1 (),
.out_wr1 (),
.out_req1 (),
.out_ack1 (),
.out_bop1 (),
.out_eop1 (),
.out_rdy1 (),
.out_bypass1 (),
.out_data2 (),
.out_pkt_route2 (),
.out_wr2 (),
.out_req2 (),
.out_ack2 (),
.out_bop2 (),
.out_eop2 (),
.out_rdy2 (),
.out_bypass2 (),
.out_data3 (pg_out_data2),
.out_pkt_route3 (pg_out_pkt_route2),
.out_wr3 (pg_out_wr2),
.out_req3 (pg_out_req2),
.out_ack3 (pg_out_ack2),
.out_bop3 (pg_out_bop2),
.out_eop3 (pg_out_eop2),
.out_rdy3 (pg_out_rdy2),
.out_bypass3 (pg_out_bypass2),
//for monitor
.pp_mem_addr (ppu_mem_addr),
.pkt_drop (packet_drop)
);
*/
ppu ppu0(
.clk (clk),
.core_sp_clk (core_sp_clk),
.reset (reset),
.TRIG_IS (TRIG_IS0),
.in_data0 (data10),
.in_pkt_route0 (pkt_route10),
.in_wr0 (wr10),
.in_req0 (req10),
.in_ack0 (ack10),
.in_bypass0 (bypass10),
.in_data1 (fc_out_data0),
.in_pkt_route1 (fc_out_pkt_route0),
.in_wr1 (fc_out_wr0),
.in_req1 (fc_out_req0),
.in_ack1 (fc_out_ack0),
.in_bypass1 (fc_out_bypass0),
.in_protocol1(fc_out_protocol0),
.in_data2 (),
.in_pkt_route2 (),
.in_wr2 (),
.in_req2 (),
.in_ack2 (),
.in_bypass2 (),
.in_data3 (data20),
.in_pkt_route3 (pkt_route20),
.in_wr3 (wr20),
.in_req3 (req20),
.in_ack3 (ack20),
.in_bypass3 (bypass20),
.out_data0 (data01),
.out_pkt_route0 (pkt_route01),
.out_wr0 (wr01),
.out_req0 (req01),
.out_ack0 (ack01),
.out_bop0 (),
.out_eop0 (),
.out_rdy0 (1'b1),
.out_bypass0 (bypass01),
.out_data1 (),
.out_pkt_route1 (),
.out_wr1 (),
.out_req1 (),
.out_ack1 (),
.out_bop1 (),
.out_eop1 (),
.out_rdy1 (),
.out_bypass1 (),
.out_data2 (),
.out_pkt_route2 (),
.out_wr2 (),
.out_req2 (),
.out_ack2 (),
.out_bop2 (),
.out_eop2 (),
.out_rdy2 (),
.out_bypass2 (),
.out_data3 (pg_out_data0),
.out_pkt_route3 (pg_out_pkt_route0),
.out_wr3 (pg_out_wr0),
.out_req3 (pg_out_req0),
.out_ack3 (pg_out_ack0),
.out_bop3 (pg_out_bop0),
.out_eop3 (pg_out_eop0),
.out_rdy3 (pg_out_rdy0),
.out_bypass3 (),
.four_bit_hash_output(four_bit_hash_output0),
.pc_input_hash_wire(pc_input_hash_wire0),
.new_inst_signal(new_inst_signal0),
.cam_we(cam_we),
.cam_wr_addr(cam_wr_addr),
.cam_din(cam_din),
.cam_wr_ack(cam_wr_ack)
);
router_op_lut_regs_non_cntr //#(
// .NUM_QUEUES (NUM_QUEUES),
// .ARP_LUT_DEPTH_BITS (ARP_LUT_DEPTH_BITS),
// .LPM_LUT_DEPTH_BITS (LPM_LUT_DEPTH_BITS),
//.FILTER_DEPTH_BITS (FILTER_DEPTH_BITS),
//.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH)
// )
router_op_lut_regs_non_cntr (
.reg_req_in (reg_req_in),
.reg_ack_in (reg_ack_in),
.reg_rd_wr_L_in (reg_rd_wr_L_in),
.reg_addr_in (reg_addr_in),
.reg_data_in (reg_data_in),
.reg_src_in (reg_src_in),
// .reg_req_out (reg_req_out),
// .reg_ack_out (reg_ack_out),
// .reg_rd_wr_L_out (reg_rd_wr_L_out),
// .reg_addr_out (reg_addr_out),
// .reg_data_out (reg_data_out),
// .reg_src_out (reg_src_out),
// --- interface to dest_ip_filter
.dest_ip_filter_rd_addr (), // address in table to read
.dest_ip_filter_rd_req (), // request a read
.dest_ip_filter_rd_ip (), // ip to match in the CAM
.dest_ip_filter_rd_ack (), // pulses high
.dest_ip_filter_wr_addr (cam_wr_addr),
.dest_ip_filter_wr_req (cam_we),
.dest_ip_filter_wr_ip (cam_din), // data to match in the CAM
.dest_ip_filter_wr_ack (cam_wr_ack),
// --- eth_parser
.clk (clk),
.reset (reset)
);
/*
ppu ppu1(
.clk (clk),
.core_sp_clk (core_sp_clk),
.reset (reset1),
.in_data0 (),
.in_pkt_route0 (),
.in_wr0 (),
.in_req0 (),
.in_ack0 (),
.in_bypass0 (),
.in_data1 (fc_out_data1),
.in_pkt_route1 (fc_out_pkt_route1),
.in_wr1 (fc_out_wr1),
.in_req1 (fc_out_req1),
.in_ack1 (fc_out_ack1),
.in_bypass1 (fc_out_bypass1),
.in_data2 (data01),
.in_pkt_route2 (pkt_route01),
.in_wr2 (wr01),
.in_req2 (req01),
.in_ack2 (ack01),
.in_bypass2 (bypass01),
.in_protocol1(fc_out_protocol1),
.in_data3 (data31),
.in_pkt_route3 (pkt_route31),
.in_wr3 (wr31),
.in_req3 (req31),
.in_ack3 (ack31),
.in_bypass3 (bypass31),
.out_data0 (),
.out_pkt_route0 (),
.out_wr0 (),
.out_req0 (),
.out_ack0 (),
.out_bop0 (),
.out_eop0 (),
.out_rdy0 (),
.out_bypass0 (),
.out_data1 (),
.out_pkt_route1 (),
.out_wr1 (),
.out_req1 (),
.out_ack1 (),
.out_bop1 (),
.out_eop1 (),
.out_rdy1 (),
.out_bypass1 (),
.out_data2 (data10),
.out_pkt_route2 (pkt_route10),
.out_wr2 (wr10),
.out_req2 (req10),
.out_ack2 (ack10),
.out_bop2 (),
.out_eop2 (),
.out_rdy2 (1'b1),
.out_bypass2 (bypass10),
.out_data3 (pg_out_data1),
.out_pkt_route3 (pg_out_pkt_route1),
.out_wr3 (pg_out_wr1),
.out_req3 (pg_out_req1),
.out_ack3 (pg_out_ack1),
.out_bop3 (pg_out_bop1),
.out_eop3 (pg_out_eop1),
.out_rdy3 (pg_out_rdy1),
.out_bypass3 (),
.four_bit_hash_output(four_bit_hash_output1),
.pc_input_hash_wire(pc_input_hash_wire1),
.new_inst_signal(new_inst_signal1)
);
ppu ppu2(
.clk (clk),
.core_sp_clk (core_sp_clk),
.reset (reset2),
.TRIG_IS (TRIG_IS2),
.in_data0 (data32),
.in_pkt_route0 (pkt_route32),
.in_wr0 (wr32),
.in_req0 (req32),
.in_ack0 (ack32),
.in_bypass0 (bypass32),
.in_data1 (fc_out_data2),
.in_pkt_route1 (fc_out_pkt_route2),
.in_wr1 (fc_out_wr2),
.in_req1 (fc_out_req2),
.in_ack1 (fc_out_ack2),
.in_bypass1 (fc_out_bypass2),
.in_protocol1(fc_out_protocol2),
.in_data2 (),
.in_pkt_route2 (),
.in_wr2 (),
.in_req2 (),
.in_ack2 (),
.in_bypass2 (),
.in_data3 (),
.in_pkt_route3 (),
.in_wr3 (),
.in_req3 (),
.in_ack3 (),
.in_bypass3 (),
.out_data0 (data23),
.out_pkt_route0 (pkt_route23),
.out_wr0 (wr23),
.out_req0 (req23),
.out_ack0 (ack23),
.out_bop0 (),
.out_eop0 (),
.out_rdy0 (1'b1),
.out_bypass0 (bypass23),
.out_data1 (data20),
.out_pkt_route1 (pkt_route20),
.out_wr1 (wr20),
.out_req1 (req20),
.out_ack1 (ack20),
.out_bop1 (),
.out_eop1 (),
.out_rdy1 (1'b1),
.out_bypass1 (bypass20),
.out_data2 (),
.out_pkt_route2 (),
.out_wr2 (),
.out_req2 (),
.out_ack2 (),
.out_bop2 (),
.out_eop2 (),
.out_rdy2 (),
.out_bypass2 (),
.out_data3 (pg_out_data2),
.out_pkt_route3 (pg_out_pkt_route2),
.out_wr3 (pg_out_wr2),
.out_req3 (pg_out_req2),
.out_ack3 (pg_out_ack2),
.out_bop3 (pg_out_bop2),
.out_eop3 (pg_out_eop2),
.out_rdy3 (pg_out_rdy2),
.out_bypass3 (),
.four_bit_hash_output(four_bit_hash_output2),
.pc_input_hash_wire(pc_input_hash_wire2),
.new_inst_signal(new_inst_signal2)
);
ppu ppu3(
.clk (clk),
.core_sp_clk (core_sp_clk),
.reset (reset3),
.in_data0 (),
.in_pkt_route0 (),
.in_wr0 (),
.in_req0 (),
.in_ack0 (),
.in_bypass0 (),
.in_data1 (fc_out_data3),
.in_pkt_route1 (fc_out_pkt_route3),
.in_wr1 (fc_out_wr3),
.in_req1 (fc_out_req3),
.in_ack1 (fc_out_ack3),
.in_bypass1 (fc_out_bypass3),
.in_protocol1(fc_out_protocol3),
.in_data2 (data23),
.in_pkt_route2 (pkt_route23),
.in_wr2 (wr23),
.in_req2 (req23),
.in_ack2 (ack23),
.in_bypass2 (bypass23),
.in_data3 (),
.in_pkt_route3 (),
.in_wr3 (),
.in_req3 (),
.in_ack3 (),
.in_bypass3 (),
.out_data0 (),
.out_pkt_route0 (),
.out_wr0 (),
.out_req0 (),
.out_ack0 (),
.out_bop0 (),
.out_eop0 (),
.out_rdy0 (),
.out_bypass0 (),
.out_data1 (data31),
.out_pkt_route1 (pkt_route31),
.out_wr1 (wr31),
.out_req1 (req31),
.out_ack1 (ack31),
.out_bop1 (),
.out_eop1 (),
.out_rdy1 (1'b1),
.out_bypass1 (bypass31),
.out_data2 (data32),
.out_pkt_route2 (pkt_route32),
.out_wr2 (wr32),
.out_req2 (req32),
.out_ack2 (ack32),
.out_bop2 (),
.out_eop2 (),
.out_rdy2 (1'b1),
.out_bypass2 (bypass32),
.out_data3 (pg_out_data3),
.out_pkt_route3 (pg_out_pkt_route3),
.out_wr3 (pg_out_wr3),
.out_req3 (pg_out_req3),
.out_ack3 (pg_out_ack3),
.out_bop3 (pg_out_bop3),
.out_eop3 (pg_out_eop3),
.out_rdy3 (pg_out_rdy3),
.out_bypass3 (),
.four_bit_hash_output(four_bit_hash_output3),
.pc_input_hash_wire(pc_input_hash_wire3),
.new_inst_signal(new_inst_signal3)
);
*/
out_arbiter oa(
.out_data (out_data),
.out_ctrl (out_ctrl),
.out_wr (out_wr),
.out_rdy (out_rdy),
.in_data0 (pg_out_data0),
.in_wr0 (pg_out_wr0),
.in_req0 (pg_out_req0),
.in_ack0 (pg_out_ack0),
.in_bop0 (pg_out_bop0),
.in_eop0 (pg_out_eop0),
.in_outrdy0 (pg_out_rdy0),
.in_data1 (pg_out_data1),
.in_wr1 (pg_out_wr1),
.in_req1 (pg_out_req1),
.in_ack1 (pg_out_ack1),
.in_bop1 (pg_out_bop1),
.in_eop1 (pg_out_eop1),
.in_outrdy1 (pg_out_rdy1),
.in_data2 (pg_out_data2),
.in_wr2 (pg_out_wr2),
.in_req2 (pg_out_req2),
.in_ack2 (pg_out_ack2),
.in_bop2 (pg_out_bop2),
.in_eop2 (pg_out_eop2),
.in_outrdy2 (pg_out_rdy2),
.in_data3 (pg_out_data3),
.in_wr3 (pg_out_wr3),
.in_req3 (pg_out_req3),
.in_ack3 (pg_out_ack3),
.in_bop3 (pg_out_bop3),
.in_eop3 (pg_out_eop3),
.in_outrdy3 (pg_out_rdy3),
.clk (clk),
.reset (reset)
);
/*
statemachine_shared shared_CM(
.clk(clk),
.statemac_clk(statemac_clk),
.four_bit_hash0(four_bit_hash_output0_cm),
.four_bit_hash1(four_bit_hash_output1_cm),
.four_bit_hash2(four_bit_hash_output2_cm),
.four_bit_hash3(four_bit_hash_output3_cm),
.pcin_0(pc_input_hash_wire0_cm),
.pcin_1(pc_input_hash_wire1_cm),
.pcin_2(pc_input_hash_wire2_cm),
.pcin_3(pc_input_hash_wire3_cm),
.new_inst_signal0(new_inst_signal0_cm),
.new_inst_signal1(new_inst_signal1_cm),
.new_inst_signal2(new_inst_signal2_cm),
.new_inst_signal3(new_inst_signal3_cm),
.reset(reset),
.packet_drop_signal0(packet_drop_signal0_cm),
.packet_drop_signal1(packet_drop_signal1_cm),
.packet_drop_signal2(packet_drop_signal2_cm),
.packet_drop_signal3(packet_drop_signal3_cm)
);
statemachine_shared_IPV4 shared_IPV4(
.clk(clk),
.statemac_clk(statemac_clk),
.four_bit_hash0(four_bit_hash_output0_ipv4),
.four_bit_hash1(four_bit_hash_output1_ipv4),
.four_bit_hash2(four_bit_hash_output2_ipv4),
.four_bit_hash3(four_bit_hash_output3_ipv4),
.pcin_0(pc_input_hash_wire0_ipv4),
.pcin_1(pc_input_hash_wire1_ipv4),
.pcin_2(pc_input_hash_wire2_ipv4),
.pcin_3(pc_input_hash_wire3_ipv4),
.new_inst_signal0(new_inst_signal0_ipv4),
.new_inst_signal1(new_inst_signal1_ipv4),
.new_inst_signal2(new_inst_signal2_ipv4),
.new_inst_signal3(new_inst_signal3_ipv4),
.reset(reset),
.packet_drop_signal0(packet_drop_signal0_ipv4),
.packet_drop_signal1(packet_drop_signal1_ipv4),
.packet_drop_signal2(packet_drop_signal2_ipv4),
.packet_drop_signal3(packet_drop_signal3_ipv4)
);
*/
assign four_bit_hash_output0_ipv4 = (!fc_out_protocol0) ? four_bit_hash_output0 : 0;
assign four_bit_hash_output1_ipv4 = (!fc_out_protocol1) ? four_bit_hash_output1 : 0;
assign four_bit_hash_output2_ipv4 = (!fc_out_protocol2) ? four_bit_hash_output2 : 0;
assign four_bit_hash_output3_ipv4 = (!fc_out_protocol3) ? four_bit_hash_output3 : 0;
assign pc_input_hash_wire0_ipv4 = (!fc_out_protocol0) ? pc_input_hash_wire0 : 0;
assign pc_input_hash_wire1_ipv4 = (!fc_out_protocol1) ? pc_input_hash_wire1 : 0;
assign pc_input_hash_wire2_ipv4 = (!fc_out_protocol2) ? pc_input_hash_wire2 : 0;
assign pc_input_hash_wire3_ipv4 = (!fc_out_protocol3) ? pc_input_hash_wire3 : 0;
assign new_inst_signal0_ipv4 = (!fc_out_protocol0) ? new_inst_signal0 : 0;
assign new_inst_signal1_ipv4 = (!fc_out_protocol1) ? new_inst_signal1 : 0;
assign new_inst_signal2_ipv4 = (!fc_out_protocol2) ? new_inst_signal2 : 0;
assign new_inst_signal3_ipv4 = (!fc_out_protocol3) ? new_inst_signal3 : 0;
//======================================================================
//=======================================================================
assign four_bit_hash_output0_cm = (fc_out_protocol0) ? four_bit_hash_output0 : 0;
assign four_bit_hash_output1_cm = (fc_out_protocol1) ? four_bit_hash_output1 : 0;
assign four_bit_hash_output2_cm = (fc_out_protocol2) ? four_bit_hash_output2 : 0;
assign four_bit_hash_output3_cm = (fc_out_protocol3) ? four_bit_hash_output3 : 0;
assign pc_input_hash_wire0_cm = (fc_out_protocol0) ? pc_input_hash_wire0 : 0;
assign pc_input_hash_wire1_cm = (fc_out_protocol1) ? pc_input_hash_wire1 : 0;
assign pc_input_hash_wire2_cm = (fc_out_protocol2) ? pc_input_hash_wire2 : 0;
assign pc_input_hash_wire3_cm = (fc_out_protocol3) ? pc_input_hash_wire3 : 0;
assign new_inst_signal0_cm = (fc_out_protocol0) ? new_inst_signal0 : 0;
assign new_inst_signal1_cm = (fc_out_protocol1) ? new_inst_signal1 : 0;
assign new_inst_signal2_cm = (fc_out_protocol2) ? new_inst_signal2 : 0;
assign new_inst_signal3_cm = (fc_out_protocol3) ? new_inst_signal3 : 0;
assign packet_drop_core_zero = (fc_out_protocol0) ? packet_drop_signal0_cm : packet_drop_signal0_ipv4;
assign packet_drop_core_one = (fc_out_protocol1) ? packet_drop_signal1_cm : packet_drop_signal1_ipv4;
assign packet_drop_core_two = (fc_out_protocol2) ? packet_drop_signal2_cm : packet_drop_signal2_ipv4;
assign packet_drop_core_three = (fc_out_protocol3) ? packet_drop_signal3_cm : packet_drop_signal3_ipv4;
assign reset0 = reset | packet_drop_core_zero;
assign reset1 = reset | packet_drop_core_one;
assign reset2 = reset | packet_drop_core_two;
assign reset3 = reset | packet_drop_core_three;
wire [35:0] CONTROL0;
wire [239:0] TRIG0;
/*
chipscope_icon_v1_03_a cs_icon (
.CONTROL0(CONTROL0)
);
chipscope_ila_single cs_ila (
.CONTROL(CONTROL0),
.CLK(clk),
.TRIG0(TRIG0)
);
assign TRIG0[7:0] = fc_out_data0[7:0];
assign TRIG0[10:8] = fc_out_pkt_route0[2:0];
assign TRIG0[11] = fc_out_wr0;
assign TRIG0[12] = fc_out_req0;
assign TRIG0[13] = fc_out_ack0;
assign TRIG0[14] = fc_out_bypass0;
assign TRIG0[27:20] = fc_out_data1[7:0];
assign TRIG0[30:28] = fc_out_pkt_route1[2:0];
assign TRIG0[31] = fc_out_wr1;
assign TRIG0[32] = fc_out_req1;
assign TRIG0[33] = fc_out_ack1;
assign TRIG0[34] = fc_out_bypass1;
assign TRIG0[47:40] = pg_out_data2[7:0];
assign TRIG0[50:48] = pg_out_pkt_route2[2:0];
assign TRIG0[51] = pg_out_wr2;
assign TRIG0[52] = pg_out_req2;
assign TRIG0[53] = pg_out_ack2;
assign TRIG0[54] = pg_out_bop2;
assign TRIG0[55] = pg_out_eop2;
assign TRIG0[56] = pg_out_rdy2;
assign TRIG0[57] = pg_out_bypass2;
assign TRIG0[67:60] = pg_out_data3[7:0];
assign TRIG0[70:68] = pg_out_pkt_route3[2:0];
assign TRIG0[71] = pg_out_wr3;
assign TRIG0[72] = pg_out_req3;
assign TRIG0[73] = pg_out_ack3;
assign TRIG0[74] = pg_out_bop3;
assign TRIG0[75] = pg_out_eop3;
assign TRIG0[76] = pg_out_rdy3;
assign TRIG0[87:80] = data01[7:0];
assign TRIG0[90:88] = pkt_route01[2:0];
assign TRIG0[91] = wr01;
assign TRIG0[92] = req01;
assign TRIG0[93] = ack01;
assign TRIG0[94] = bypass01;
assign TRIG0[107:100] = data10[7:0];
assign TRIG0[110:108] = pkt_route10[2:0];
assign TRIG0[111] = wr10;
assign TRIG0[112] = req10;
assign TRIG0[113] = ack10;
assign TRIG0[114] = bypass10;
*/
/*
assign TRIG0[91:80] = TRIG_IS0[41:30];
assign TRIG0[94:92] = TRIG_IS0[28:26];
assign TRIG0[97:95] = TRIG_IS0[25:23];
assign TRIG0[100] = TRIG_IS0[0];
assign TRIG0[101] = TRIG_IS0[1];
assign TRIG0[104:102] = TRIG_IS0[4:2];
assign TRIG0[106:105] = TRIG_IS0[6:5];
assign TRIG0[107] = TRIG_IS0[10];
assign TRIG0[108] = TRIG_IS0[11];
assign TRIG0[111:109] = TRIG_IS0[14:12];
assign TRIG0[113:112] = TRIG_IS0[16:15];
assign TRIG0[114] = TRIG_IS0[17];
assign TRIG0[115] = TRIG_IS0[18];
assign TRIG0[116] = TRIG_IS0[19];
assign TRIG0[117] = TRIG_IS0[20];
assign TRIG0[118] = TRIG_IS0[21];
assign TRIG0[119] = TRIG_IS0[22];
*/
/*
assign TRIG0[127:120] = data02[7:0];
assign TRIG0[130:128] = pkt_route02[2:0];
assign TRIG0[131] = wr02;
assign TRIG0[132] = req02;
assign TRIG0[133] = ack02;
assign TRIG0[134] = bypass02;
assign TRIG0[147:140] = data20[7:0];
assign TRIG0[150:148] = pkt_route20[2:0];
assign TRIG0[151] = wr20;
assign TRIG0[152] = req20;
assign TRIG0[153] = ack20;
assign TRIG0[154] = bypass20;
//assign TRIG0[234:160] = TRIG_OS0[74:0];
assign TRIG0[167:160] = data13[7:0];
assign TRIG0[170:168] = pkt_route13[2:0];
assign TRIG0[171] = wr13;
assign TRIG0[172] = req13;
assign TRIG0[173] = ack13;
assign TRIG0[174] = bypass13;
assign TRIG0[187:180] = data31[7:0];
assign TRIG0[190:188] = pkt_route31[2:0];
assign TRIG0[191] = wr31;
assign TRIG0[192] = req31;
assign TRIG0[193] = ack31;
assign TRIG0[194] = bypass31;
assign TRIG0[207:200] = data23[7:0];
assign TRIG0[210:208] = pkt_route23[2:0];
assign TRIG0[211] = wr23;
assign TRIG0[212] = req23;
assign TRIG0[213] = ack23;
assign TRIG0[214] = bypass23;
assign TRIG0[227:220] = data32[7:0];
assign TRIG0[230:228] = pkt_route32[2:0];
assign TRIG0[231] = wr32;
assign TRIG0[232] = req32;
assign TRIG0[233] = ack32;
assign TRIG0[234] = bypass32;
assign TRIG0[235] = in_wr;
assign TRIG0[236] = in_rdy;
assign TRIG0[237] = out_wr;
assign TRIG0[238] = out_rdy;
*/
endmodule
|
module dds(aclk, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,m_axis_data_tvalid,m_axis_data_tdata[15:0]" */;
input aclk;
output m_axis_data_tvalid;
output [15:0]m_axis_data_tdata;
endmodule
|
module sky130_fd_sc_ls__decaphe (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
|
module testing_wb_master (/*AUTOARG*/
// Outputs
wb_adr_o, wb_dat_o, wb_sel_o, wb_we_o, wb_cyc_o, wb_stb_o,
wb_cti_o, wb_bte_o, data_rd, active,
// Inputs
wb_clk, wb_rst, wb_dat_i, wb_ack_i, wb_err_i, wb_rty_i, start,
address, selection, write, data_wr
) ;
parameter dw = 32;
parameter aw = 32;
parameter DEBUG = 0;
input wb_clk;
input wb_rst;
output reg [aw-1:0] wb_adr_o;
output reg [dw-1:0] wb_dat_o;
output reg [3:0] wb_sel_o;
output reg wb_we_o;
output reg wb_cyc_o;
output reg wb_stb_o;
output reg [2:0] wb_cti_o;
output reg [1:0] wb_bte_o;
input [dw-1:0] wb_dat_i;
input wb_ack_i;
input wb_err_i;
input wb_rty_i;
input start;
input [aw-1:0] address;
input [3:0] selection;
input write;
input [dw-1:0] data_wr;
output reg [dw-1:0] data_rd;
output reg active;
reg [1:0] state;
reg [1:0] next_state;
parameter STATE_IDLE = 2'h0;
parameter STATE_WAIT_ACK = 2'h1;
parameter STATE_ERROR = 2'h3;
reg [aw-1:0] adr_o;
reg [dw-1:0] dat_o;
reg [3:0] sel_o;
reg we_o;
reg cyc_o;
reg stb_o;
reg [2:0] cti_o;
reg [1:0] bte_o;
always @(posedge wb_clk)
if (wb_rst) begin
state <= STATE_IDLE;
end else begin
state <= next_state;
end
always @(*)
if (wb_rst) begin
next_state = STATE_IDLE;
active = 0;
wb_adr_o <= 0;
wb_dat_o <= 0;
wb_sel_o <= 0;
wb_we_o <= 0;
wb_cyc_o <= 0;
wb_stb_o <= 0;
wb_cti_o <= 0;
wb_bte_o <= 0;
data_rd <= 0;
end else begin // if (wb_rst)
case (state)
STATE_IDLE: begin
active = 0;
wb_adr_o = 0;
wb_dat_o = 0;
wb_sel_o = 0;
wb_we_o = 0;
wb_cyc_o = 0;
wb_stb_o = 0;
wb_cti_o = 0;
wb_bte_o = 0;
if (start) begin
next_state = STATE_WAIT_ACK;
wb_adr_o = address;
wb_dat_o = data_wr;
wb_sel_o = selection;
wb_we_o = write;
wb_cyc_o = 1;
wb_stb_o = 1;
wb_cti_o = 0;
wb_bte_o = 0;
active = 1;
data_rd =0;
end else begin
next_state = STATE_IDLE;
end
end // case: STATE_IDLE
STATE_WAIT_ACK: begin
if (wb_err_i || wb_rty_i) begin
next_state = STATE_ERROR;
end else if (wb_ack_i) begin
if (! wb_we_o)
data_rd = wb_dat_i;
next_state = STATE_IDLE;
end else begin
next_state = STATE_WAIT_ACK;
end
end // case: STATE_WAIT_ACK
STATE_ERROR: begin
next_state = STATE_IDLE;
end
default: begin
next_state = STATE_IDLE;
end
endcase // case (state)
end
`ifdef SIM
reg [32*8-1:0] state_name;
always @(*)
case (state)
STATE_IDLE: state_name = "STATE_IDLE";
STATE_WAIT_ACK: state_name = "STATE_WAIT ACK";
STATE_ERROR:state_name = "STATE ERROR";
default: state_name = "DEFAULT";
endcase // case (state)
`endif
endmodule
|
module sky130_fd_sc_hdll__o21a (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
|
module sky130_fd_sc_lp__o41a (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
|
module BRAM2BE(CLKA,
ENA,
WEA,
ADDRA,
DIA,
DOA,
CLKB,
ENB,
WEB,
ADDRB,
DIB,
DOB
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter CHUNKSIZE = 1;
parameter WE_WIDTH = 1;
parameter MEMSIZE = 1;
input CLKA;
input ENA;
input [WE_WIDTH-1:0] WEA;
input [ADDR_WIDTH-1:0] ADDRA;
input [DATA_WIDTH-1:0] DIA;
output [DATA_WIDTH-1:0] DOA;
input CLKB;
input ENB;
input [WE_WIDTH-1:0] WEB;
input [ADDR_WIDTH-1:0] ADDRB;
input [DATA_WIDTH-1:0] DIB;
output [DATA_WIDTH-1:0] DOB;
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle="no_rw_check" */ ;
reg [DATA_WIDTH-1:0] DOA_R;
reg [DATA_WIDTH-1:0] DOA_R2;
reg [DATA_WIDTH-1:0] DOB_R;
reg [DATA_WIDTH-1:0] DOB_R2;
`ifdef BSV_NO_INITIAL_BLOCKS
`else
// synopsys translate_off
integer i;
initial
begin : init_block
for (i = 0; i < MEMSIZE; i = i + 1) begin
RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
DOA_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOA_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
// synopsys translate_on
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
// PORT A
// iverilog does not support the full verilog-2001 language. This fixes that for simulation.
`ifdef __ICARUS__
reg [DATA_WIDTH-1:0] MASKA, IMASKA;
reg [DATA_WIDTH-1:0] DATA_A;
wire [DATA_WIDTH-1:0] DATA_Awr;
assign DATA_Awr = RAM[ADDRA];
always @(WEA or DIA or DATA_Awr) begin : combo1
integer j;
MASKA = 0;
IMASKA = 0;
for(j = WE_WIDTH-1; j >= 0; j = j - 1) begin
if (WEA[j]) MASKA = (MASKA << 8) | { { DATA_WIDTH-CHUNKSIZE { 1'b0 } }, { CHUNKSIZE { 1'b1 } } };
else MASKA = (MASKA << 8);
end
IMASKA = ~MASKA;
DATA_A = (DATA_Awr & IMASKA) | (DIA & MASKA);
end
always @(posedge CLKA) begin
if (ENA) begin
if (WEA) begin
RAM[ADDRA] <= `BSV_ASSIGNMENT_DELAY DATA_A;
DOA_R <= `BSV_ASSIGNMENT_DELAY DATA_A;
end
else begin
DOA_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA];
end
end
end
`else
generate
genvar j;
for(j = 0; j < WE_WIDTH; j = j + 1) begin: porta_we
always @(posedge CLKA) begin
if (ENA) begin
if (WEA[j]) begin
RAM[ADDRA][((j+1)*CHUNKSIZE)-1 : j*CHUNKSIZE] <= `BSV_ASSIGNMENT_DELAY DIA[((j+1)*CHUNKSIZE)-1 : j*CHUNKSIZE];
DOA_R[((j+1)*CHUNKSIZE)-1 : j*CHUNKSIZE] <= `BSV_ASSIGNMENT_DELAY DIA[((j+1)*CHUNKSIZE)-1 : j*CHUNKSIZE];
end
else begin
DOA_R[((j+1)*CHUNKSIZE)-1 : j*CHUNKSIZE] <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA][((j+1)*CHUNKSIZE)-1 : j*CHUNKSIZE];
end
end
end
end
endgenerate
`endif // !`ifdef __ICARUS__
// PORT B
// iverilog does not support the full verilog-2001 language. This fixes that for simulation.
`ifdef __ICARUS__
reg [DATA_WIDTH-1:0] MASKB, IMASKB;
reg [DATA_WIDTH-1:0] DATA_B;
wire [DATA_WIDTH-1:0] DATA_Bwr;
assign DATA_Bwr = RAM[ADDRB];
always @(WEB or DIB or DATA_Bwr) begin : combo2
integer j;
MASKB = 0;
IMASKB = 0;
for(j = WE_WIDTH-1; j >= 0; j = j - 1) begin
if (WEB[j]) MASKB = (MASKB << 8) | { { DATA_WIDTH-CHUNKSIZE { 1'b0 } }, { CHUNKSIZE { 1'b1 } } };
else MASKB = (MASKB << 8);
end
IMASKB = ~MASKB;
DATA_B = (DATA_Bwr & IMASKB) | (DIB & MASKB);
end
always @(posedge CLKB) begin
if (ENB) begin
if (WEB) begin
RAM[ADDRB] <= `BSV_ASSIGNMENT_DELAY DATA_B;
DOB_R <= `BSV_ASSIGNMENT_DELAY DATA_B;
end
else begin
DOB_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB];
end
end
end
`else
generate
genvar k;
for(k = 0; k < WE_WIDTH; k = k + 1) begin: portb_we
always @(posedge CLKB) begin
if (ENB) begin
if (WEB[k]) begin
RAM[ADDRB][((k+1)*CHUNKSIZE)-1 : k*CHUNKSIZE] <= `BSV_ASSIGNMENT_DELAY DIB[((k+1)*CHUNKSIZE)-1 : k*CHUNKSIZE];
DOB_R[((k+1)*CHUNKSIZE)-1 : k*CHUNKSIZE] <= `BSV_ASSIGNMENT_DELAY DIB[((k+1)*CHUNKSIZE)-1 : k*CHUNKSIZE];
end
else begin
DOB_R[((k+1)*CHUNKSIZE)-1 : k*CHUNKSIZE] <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB][((k+1)*CHUNKSIZE)-1 : k*CHUNKSIZE];
end
end
end
end
endgenerate
`endif // !`ifdef __ICARUS__
// Output drivers
always @(posedge CLKA) begin
DOA_R2 <= `BSV_ASSIGNMENT_DELAY DOA_R;
end
always @(posedge CLKB) begin
DOB_R2 <= `BSV_ASSIGNMENT_DELAY DOB_R;
end
assign DOA = (PIPELINED) ? DOA_R2 : DOA_R;
assign DOB = (PIPELINED) ? DOB_R2 : DOB_R;
endmodule
|
module sky130_fd_sc_lp__a311oi (
Y ,
A1,
A2,
A3,
B1,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y, and0_out, B1, C1);
buf buf0 (Y , nor0_out_Y );
endmodule
|
module pci_exp_usrapp_tx #(
parameter LINK_CAP_MAX_LINK_SPEED = 4'h2) (
trn_td,
trn_trem_n,
trn_tsof_n,
trn_teof_n,
trn_terrfwd_n,
trn_tsrc_rdy_n,
trn_tsrc_dsc_n,
trn_clk,
trn_reset_n,
trn_lnk_up_n,
trn_tdst_rdy_n,
trn_tdst_dsc_n,
trn_tbuf_av,
speed_change_done_n
);
output [(64 - 1):0] trn_td;
output trn_trem_n;
output trn_tsof_n;
output trn_teof_n;
output trn_terrfwd_n;
output trn_tsrc_rdy_n;
output trn_tsrc_dsc_n;
input trn_clk;
input trn_reset_n;
input trn_lnk_up_n;
input trn_tdst_rdy_n;
input trn_tdst_dsc_n;
input [(6 - 1):0] trn_tbuf_av;
input speed_change_done_n;
parameter Tcq = 1;
/* Output Variables */
reg [(64 - 1):0] trn_td;
reg [(8 - 1):0] trn_trem_ni;
reg trn_tsof_n;
reg trn_teof_n;
reg trn_terrfwd_n;
reg trn_tsrc_rdy_n;
reg trn_tsrc_dsc_n;
/* Local Variables */
integer i, j, k;
reg [7:0] DATA_STORE [4095:0];
reg [31:0] ADDRESS_32_L;
reg [31:0] ADDRESS_32_H;
reg [63:0] ADDRESS_64;
reg [15:0] COMPLETER_ID;
reg [15:0] COMPLETER_ID_CFG;
reg [15:0] REQUESTER_ID;
reg [15:0] DESTINATION_RID;
reg [2:0] DEFAULT_TC;
reg [9:0] DEFAULT_LENGTH;
reg [3:0] DEFAULT_BE_LAST_DW;
reg [3:0] DEFAULT_BE_FIRST_DW;
reg [1:0] DEFAULT_ATTR;
reg [7:0] DEFAULT_TAG;
reg [3:0] DEFAULT_COMP;
reg [11:0] EXT_REG_ADDR;
reg TD;
reg EP;
reg [15:0] VENDOR_ID;
reg [9:0] LENGTH; // For 1DW config and IO transactions
reg [6:0] RAND_;
reg [9:0] CFG_DWADDR;
reg [15:0] P_DEV_BDF;
reg [31:0] P_IO_ADDR;
reg [31:0] P_ADDRESS_1L;
reg [31:0] P_ADDRESS_2L;
reg [31:0] P_ADDRESS_3L;
reg [31:0] P_ADDRESS_4L;
reg [31:0] P_ADDRESS_H;
reg [9:0] P_CFG_DWADDR;
event test_begin;
reg [31:0] P_ADDRESS_MASK;
reg [31:0] P_READ_DATA; // will store the results of a PCIE read completion
reg [31:0] data;
reg p_read_data_valid;
reg [31:0] P_WRITE_DATA;
reg [31:0] temp_register;
reg error_check;
// BAR Init variables
reg [32:0] BAR_INIT_P_BAR[6:0]; // 6 corresponds to Expansion ROM
// note that bit 32 is for overflow checking
reg [31:0] BAR_INIT_P_BAR_RANGE[6:0]; // 6 corresponds to Expansion ROM
reg [1:0] BAR_INIT_P_BAR_ENABLED[6:0]; // 6 corresponds to Expansion ROM
// 0 = disabled; 1 = io mapped; 2 = mem32 mapped; 3 = mem64 mapped
reg [31:0] BAR_INIT_P_MEM64_HI_START; // start address for hi memory space
reg [31:0] BAR_INIT_P_MEM64_LO_START; // start address for hi memory space
reg [32:0] BAR_INIT_P_MEM32_START; // start address for low memory space
// top bit used for overflow indicator
reg [32:0] BAR_INIT_P_IO_START; // start address for io space
reg [100:0] BAR_INIT_MESSAGE[3:0]; // to be used to display info to user
reg [32:0] BAR_INIT_TEMP;
reg OUT_OF_LO_MEM; // flags to indicate out of mem, mem64, and io
reg OUT_OF_IO;
reg OUT_OF_HI_MEM;
reg [3:0] ii;
integer jj;
reg [31:0] DEV_VEN_ID; // holds device and vendor id
integer PIO_MAX_NUM_BLOCK_RAMS; // holds the max number of block RAMS
reg [31:0] PIO_MAX_MEMORY;
reg [31:0] PIO_ADDRESS; // holds the current PIO testing address
reg pio_check_design; // boolean value to check PCI Express BAR configuration against
// limitations of PIO design. Setting this to true will cause the
// testbench to check if the core has been configured for more than
// one IO space, one general purpose Mem32 space (not counting
// the Mem32 EROM space), and one Mem64 space.
reg cpld_to; // boolean value to indicate if time out has occured while waiting for cpld
reg cpld_to_finish; // boolean value to indicate to $finish on cpld_to
reg verbose; // boolean value to display additional info to stdout
integer NUMBER_OF_IO_BARS;
integer NUMBER_OF_MEM32_BARS; // Not counting the Mem32 EROM space
integer NUMBER_OF_MEM64_BARS;
initial
begin
ADDRESS_32_L = 32'b1011_1110_1110_1111_1100_1010_1111_1110;
ADDRESS_32_H = 32'b1011_1110_1110_1111_1100_1010_1111_1110;
ADDRESS_64 = { ADDRESS_32_H, ADDRESS_32_L };
COMPLETER_ID = 16'b0000_0000_1010_0000;
COMPLETER_ID_CFG = 16'b0000_0001_1010_0000;
REQUESTER_ID = 16'b0000_0001_1010_1111;
DESTINATION_RID = 16'b0000_0001_1010_1111;
DEFAULT_TC = 3'b000;
DEFAULT_LENGTH = 10'h000;
DEFAULT_BE_LAST_DW = 4'h0;
DEFAULT_BE_FIRST_DW = 4'h0;
DEFAULT_ATTR = 2'b01;
DEFAULT_TAG = 8'h00;
DEFAULT_COMP = 4'h0;
EXT_REG_ADDR = 12'h000;
TD = 0;
EP = 0;
VENDOR_ID = 16'h10ee;
LENGTH = 10'b00_0000_0001;
end
initial begin
// Pre-BAR initialization
BAR_INIT_MESSAGE[0] = "DISABLED";
BAR_INIT_MESSAGE[1] = "IO MAPPED";
BAR_INIT_MESSAGE[2] = "MEM32 MAPPED";
BAR_INIT_MESSAGE[3] = "MEM64 MAPPED";
OUT_OF_LO_MEM = 1'b0;
OUT_OF_IO = 1'b0;
OUT_OF_HI_MEM = 1'b0;
// Disable variables to start
for (ii = 0; ii <= 6; ii = ii + 1) begin
BAR_INIT_P_BAR[ii] = 33'h00000_0000;
BAR_INIT_P_BAR_RANGE[ii] = 32'h0000_0000;
BAR_INIT_P_BAR_ENABLED[ii] = 2'b00;
end
BAR_INIT_P_MEM64_HI_START = 32'h0000_0001; // hi 32 bit start of 64bit memory
BAR_INIT_P_MEM64_LO_START = 32'h0000_0000; // low 32 bit start of 64bit memory
BAR_INIT_P_MEM32_START = 33'h00000_0000; // start of 32bit memory
BAR_INIT_P_IO_START = 33'h00000_0000; // start of 32bit io
DEV_VEN_ID = (32'h7024 << 16) | (32'h10EE);
PIO_MAX_MEMORY = 8192; // PIO has max of 8Kbytes of memory
PIO_MAX_NUM_BLOCK_RAMS = 4; // PIO has four block RAMS to test
PIO_MAX_MEMORY = 2048; // PIO has 4 memory regions with 2 Kbytes of memory per region, ie 8 Kbytes
PIO_MAX_NUM_BLOCK_RAMS = 4; // PIO has four block RAMS to test
pio_check_design = 1; // By default check to make sure the core has been configured
// appropriately for the PIO design
cpld_to = 0; // By default time out has not occured
cpld_to_finish = 1; // By default end simulation on time out
verbose = 0; // turned off by default
NUMBER_OF_IO_BARS = 0;
NUMBER_OF_MEM32_BARS = 0;
NUMBER_OF_MEM64_BARS = 0;
end
assign trn_trem_n = trn_trem_ni[0];
reg [255:0] testname;
integer test_vars [31:0];
reg [7:0] expect_cpld_payload [4095:0];
reg [7:0] expect_msgd_payload [4095:0];
reg [7:0] expect_memwr_payload [4095:0];
reg [7:0] expect_memwr64_payload [4095:0];
reg [7:0] expect_cfgwr_payload [3:0];
reg expect_status;
reg expect_finish_check;
reg test_failed_flag;
initial begin
if ($value$plusargs("TESTNAME=%s", testname))
$display("Running test {%0s}......", testname);
else
begin
// $display("[%t] %m: No TESTNAME specified!", $realtime);
// $finish(2);
testname = "sample_smoke_test0";
$display("Running default test {%0s}......", testname);
end
expect_status = 0;
expect_finish_check = 0;
test_failed_flag = 0;
// Tx transaction interface signal initialization.
trn_td = 0;
trn_tsof_n = 1;
trn_teof_n = 1;
trn_trem_ni = 0;
trn_terrfwd_n = 1;
trn_tsrc_rdy_n = 1 ;
trn_tsrc_dsc_n = 1;
// Payload data initialization.
TSK_USR_DATA_SETUP_SEQ;
//Test starts here
if (testname == "dummy_test")
begin
$display("[%t] %m: Invalid TESTNAME: %0s", $realtime, testname);
$finish(2);
end
`include "tests.v"
else begin
$display("[%t] %m: Error: Unrecognized TESTNAME: %0s", $realtime, testname);
$finish(2);
end
end
task TSK_SYSTEM_INITIALIZATION;
begin
//--------------------------------------------------------------------------
// Event # 1: Wait for Transaction reset to be de-asserted..
//--------------------------------------------------------------------------
wait (trn_reset_n == 1);
$display("[%t] : Transaction Reset Is De-asserted...", $realtime);
//--------------------------------------------------------------------------
// Event # 2: Wait for Transaction link to be asserted..
//--------------------------------------------------------------------------
wait (trn_lnk_up_n == 0);
wait (((LINK_CAP_MAX_LINK_SPEED == 4'h2) && (speed_change_done_n == 1'b0)) || (LINK_CAP_MAX_LINK_SPEED == 4'h1))
$display("[%t] : Transaction Link Is Up...", $realtime);
TSK_SYSTEM_CONFIGURATION_CHECK;
end
endtask
/************************************************************
Task : TSK_SYSTEM_CONFIGURATION_CHECK
Description : Check that options selected from Coregen GUI are
set correctly.
Checks - Max Link Speed/Width, Device/Vendor ID, CMPS
*************************************************************/
task TSK_SYSTEM_CONFIGURATION_CHECK;
begin
error_check = 0;
// Check Link Speed/Width
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h70, 4'hF);
TSK_WAIT_FOR_READ_DATA;
if (P_READ_DATA[19:16] == LINK_CAP_MAX_LINK_SPEED) begin
if (P_READ_DATA[19:16] == 1)
$display("[%t] : Check Max Link Speed = 2.5GT/s - PASSED", $realtime);
else
$display("[%t] : Check Max Link Speed = 5.0GT/s - PASSED", $realtime);
end else begin
$display("[%t] : Check Max Link Speed - FAILED", $realtime);
$display("[%t] : Data Error Mismatch, Parameter Data %s != Read Data %x", $realtime, "2", P_READ_DATA[19:16]);
end
if (P_READ_DATA[23:20] == 4'h04)
$display("[%t] : Check Negotiated Link Width = 04x - PASSED", $realtime);
else
$display("[%t] : Data Error Mismatch, Parameter Data %s != Read Data %x", $realtime, "04", P_READ_DATA[23:20]);
// Check Device/Vendor ID
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h0, 4'hF);
TSK_WAIT_FOR_READ_DATA;
if (P_READ_DATA[31:16] != 16'h7024) begin
$display("[%t] : Check Device/Vendor ID - FAILED", $realtime);
$display("[%t] : Data Error Mismatch, Parameter Data %x != Read Data %x", $realtime, 16'h7024, P_READ_DATA);
error_check = 1;
end else begin
$display("[%t] : Check Device/Vendor ID - PASSED", $realtime);
end
// Check CMPS
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h64, 4'hF);
TSK_WAIT_FOR_READ_DATA;
if (P_READ_DATA[2:0] != 3'd3) begin
$display("[%t] : Check CMPS ID - FAILED", $realtime);
$display("[%t] : Data Error Mismatch, Parameter Data %x != Read data %x", $realtime, 3'h3, P_READ_DATA);
error_check = 1;
end else begin
$display("[%t] : Check CMPS ID - PASSED", $realtime);
end
if (error_check == 0) begin
$display("[%t] : SYSTEM CHECK PASSED", $realtime);
end else begin
$display("[%t] : SYSTEM CHECK FAILED", $realtime);
$finish;
end
end
endtask
/************************************************************
Task : TSK_TX_TYPE0_CONFIGURATION_READ
Inputs : Tag, PCI/PCI-Express Reg Address, First BypeEn
Outputs : Transaction Tx Interface Signaling
Description : Generates a Type 0 Configuration Read TLP
*************************************************************/
task TSK_TX_TYPE0_CONFIGURATION_READ;
input [7:0] tag_;
input [11:0] reg_addr_;
input [3:0] first_dw_be_;
begin
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
TSK_TX_SYNCHRONIZE(0, 0);
trn_td <= #(Tcq) {
1'b0,
2'b00,
5'b00100,
1'b0,
3'b000,
4'b0000,
1'b0,
1'b0,
2'b00,
2'b00,
10'b0000000001, // 32
COMPLETER_ID_CFG,
tag_,
4'b0000,
first_dw_be_ // 64
};
trn_tsof_n <= #(Tcq) 0;
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
COMPLETER_ID_CFG,
4'b0000,
reg_addr_[11:2],
2'b00,
32'b0
};
trn_tsof_n <= #(Tcq) 1;
trn_teof_n <= #(Tcq) 0;
trn_trem_ni <= #(Tcq) 8'h0F;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 1);
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 1;
end
endtask // TSK_TX_TYPE0_CONFIGURATION_READ
/************************************************************
Task : TSK_TX_TYPE1_CONFIGURATION_READ
Inputs : Tag, PCI/PCI-Express Reg Address, First BypeEn
Outputs : Transaction Tx Interface Signaling
Description : Generates a Type 1 Configuration Read TLP
*************************************************************/
task TSK_TX_TYPE1_CONFIGURATION_READ;
input [7:0] tag_;
input [11:0] reg_addr_;
input [3:0] first_dw_be_;
begin
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
TSK_TX_SYNCHRONIZE(0, 0);
trn_td <= #(Tcq) {
1'b0,
2'b00,
5'b00101,
1'b0,
3'b000,
4'b0000,
1'b0,
1'b0,
2'b00,
2'b00,
10'b0000000001, // 32
COMPLETER_ID_CFG,
tag_,
4'b0000,
first_dw_be_ // 64
};
trn_tsof_n <= #(Tcq) 0;
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
COMPLETER_ID_CFG,
4'b0000,
reg_addr_[11:2],
2'b00,
32'b0
};
trn_tsof_n <= #(Tcq) 1;
trn_teof_n <= #(Tcq) 0;
trn_trem_ni <= #(Tcq) 8'h0F;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 1);
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 1;
end
endtask // TSK_TX_TYPE1_CONFIGURATION_READ
/************************************************************
Task : TSK_TX_TYPE0_CONFIGURATION_WRITE
Inputs : Tag, PCI/PCI-Express Reg Address, First BypeEn
Outputs : Transaction Tx Interface Signaling
Description : Generates a Type 0 Configuration Write TLP
*************************************************************/
task TSK_TX_TYPE0_CONFIGURATION_WRITE;
input [7:0] tag_;
input [11:0] reg_addr_;
input [31:0] reg_data_;
input [3:0] first_dw_be_;
begin
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
TSK_TX_SYNCHRONIZE(0, 0);
trn_td <= #(Tcq) {
1'b0,
2'b10,
5'b00100,
1'b0,
3'b000,
4'b0000,
1'b0,
1'b0,
2'b00,
2'b00,
10'b0000000001, // 32
COMPLETER_ID_CFG,
tag_,
4'b0000,
first_dw_be_ // 64
};
trn_tsof_n <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
COMPLETER_ID_CFG,
4'b0000,
reg_addr_[11:2],
2'b00, // 32
reg_data_[7:0],
reg_data_[15:8],
reg_data_[23:16],
reg_data_[31:24] // 64
};
trn_tsof_n <= #(Tcq) 1;
trn_teof_n <= #(Tcq) 0;
trn_trem_ni <= #(Tcq) 8'h00;
TSK_TX_SYNCHRONIZE(1, 1);
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 1;
end
endtask // TSK_TX_TYPE0_CONFIGURATION_WRITE
/************************************************************
Task : TSK_TX_TYPE1_CONFIGURATION_WRITE
Inputs : Tag, PCI/PCI-Express Reg Address, First BypeEn
Outputs : Transaction Tx Interface Signaling
Description : Generates a Type 1 Configuration Write TLP
*************************************************************/
task TSK_TX_TYPE1_CONFIGURATION_WRITE;
input [7:0] tag_;
input [11:0] reg_addr_;
input [31:0] reg_data_;
input [3:0] first_dw_be_;
begin
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
TSK_TX_SYNCHRONIZE(0, 0);
trn_td <= #(Tcq) {
1'b0,
2'b10,
5'b00101,
1'b0,
3'b000,
4'b0000,
1'b0,
1'b0,
2'b00,
2'b00,
10'b0000000001, // 32
COMPLETER_ID_CFG,
tag_,
4'b0000,
first_dw_be_ // 64
};
trn_tsof_n <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
COMPLETER_ID_CFG,
4'b0000,
reg_addr_[11:2],
2'b00, // 32
reg_data_[7:0],
reg_data_[15:8],
reg_data_[23:16],
reg_data_[31:24] // 64
};
trn_tsof_n <= #(Tcq) 1;
trn_teof_n <= #(Tcq) 0;
trn_trem_ni <= #(Tcq) 8'h00;
TSK_TX_SYNCHRONIZE(1, 1);
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 1;
end
endtask // TSK_TX_TYPE1_CONFIGURATION_WRITE
/************************************************************
Task : TSK_TX_MEMORY_READ_32
Inputs : Tag, Length, Address, Last Byte En, First Byte En
Outputs : Transaction Tx Interface Signaling
Description : Generates a Memory Read 32 TLP
*************************************************************/
task TSK_TX_MEMORY_READ_32;
input [7:0] tag_;
input [2:0] tc_;
input [9:0] len_;
input [31:0] addr_;
input [3:0] last_dw_be_;
input [3:0] first_dw_be_;
begin
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
TSK_TX_SYNCHRONIZE(0, 0);
trn_td <= #(Tcq) {
1'b0,
2'b00,
5'b00000,
1'b0,
tc_,
4'b0000,
1'b0,
1'b0,
2'b00,
2'b00,
len_, // 32
COMPLETER_ID_CFG,
tag_,
last_dw_be_,
first_dw_be_ // 64
};
trn_tsof_n <= #(Tcq) 0;
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
addr_[31:2],
2'b00,
32'b0
};
trn_tsof_n <= #(Tcq) 1;
trn_teof_n <= #(Tcq) 0;
trn_trem_ni <= #(Tcq) 8'h0F;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 1);
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 1;
end
endtask // TSK_TX_MEMORY_READ_32
/************************************************************
Task : TSK_TX_MEMORY_READ_64
Inputs : Tag, Length, Address, Last Byte En, First Byte En
Outputs : Transaction Tx Interface Signaling
Description : Generates a Memory Read 64 TLP
*************************************************************/
task TSK_TX_MEMORY_READ_64;
input [7:0] tag_;
input [2:0] tc_;
input [9:0] len_;
input [63:0] addr_;
input [3:0] last_dw_be_;
input [3:0] first_dw_be_;
begin
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
TSK_TX_SYNCHRONIZE(0, 0);
trn_td <= #(Tcq) {
1'b0,
2'b01,
5'b00000,
1'b0,
tc_,
4'b0000,
1'b0,
1'b0,
2'b00,
2'b00,
len_, // 32
COMPLETER_ID_CFG,
tag_,
last_dw_be_,
first_dw_be_ // 64
};
trn_tsof_n <= #(Tcq) 0;
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
addr_[63:2],
2'b00
};
trn_tsof_n <= #(Tcq) 1;
trn_teof_n <= #(Tcq) 0;
trn_trem_ni <= #(Tcq) 8'h00;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 1);
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 1;
end
endtask // TSK_TX_MEMORY_READ_64
/************************************************************
Task : TSK_TX_MEMORY_WRITE_32
Inputs : Tag, Length, Address, Last Byte En, First Byte En
Outputs : Transaction Tx Interface Signaling
Description : Generates a Memory Write 32 TLP
*************************************************************/
task TSK_TX_MEMORY_WRITE_32;
input [7:0] tag_;
input [2:0] tc_;
input [9:0] len_;
input [31:0] addr_;
input [3:0] last_dw_be_;
input [3:0] first_dw_be_;
input ep_;
reg [10:0] _len;
integer _j;
begin
if (len_ == 0)
_len = 1024;
else
_len = len_;
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
TSK_TX_SYNCHRONIZE(0, 0);
trn_td <= #(Tcq) {
1'b0,
2'b10,
5'b00000,
1'b0,
tc_,
4'b0000,
1'b0,
1'b0,
2'b00,
2'b00,
len_, // 32
COMPLETER_ID_CFG,
tag_,
last_dw_be_,
first_dw_be_ // 64
};
trn_tsof_n <= #(Tcq) 0;
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
addr_[31:2],
2'b00,
DATA_STORE[0],
DATA_STORE[1],
DATA_STORE[2],
DATA_STORE[3]
};
trn_tsof_n <= #(Tcq) 1;
if (_len != 1) begin
for (_j = 4; _j < (_len * 4); _j = _j + 8) begin
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
DATA_STORE[_j + 0],
DATA_STORE[_j + 1],
DATA_STORE[_j + 2],
DATA_STORE[_j + 3],
DATA_STORE[_j + 4],
DATA_STORE[_j + 5],
DATA_STORE[_j + 6],
DATA_STORE[_j + 7]
};
if ((_j + 7) >= ((_len * 4) - 1)) begin
trn_teof_n <= #(Tcq) 0;
if (ep_)
trn_terrfwd_n <= #(Tcq) 0;
if (((_len - 1) % 2) == 0)
trn_trem_ni <= #(Tcq) 8'h00;
else
trn_trem_ni <= #(Tcq) 8'h0f;
end
end
end else begin
trn_teof_n <= #(Tcq) 0;
if (ep_)
trn_terrfwd_n <= #(Tcq) 0;
trn_trem_ni <= #(Tcq) 8'h00;
end
TSK_TX_SYNCHRONIZE(1, 1);
trn_teof_n <= #(Tcq) 1;
trn_terrfwd_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 1;
end
endtask // TSK_TX_MEMORY_WRITE_32
/************************************************************
Task : TSK_TX_MEMORY_WRITE_64
Inputs : Tag, Length, Address, Last Byte En, First Byte En
Outputs : Transaction Tx Interface Signaling
Description : Generates a Memory Write 64 TLP
*************************************************************/
task TSK_TX_MEMORY_WRITE_64;
input [7:0] tag_;
input [2:0] tc_;
input [9:0] len_;
input [63:0] addr_;
input [3:0] last_dw_be_;
input [3:0] first_dw_be_;
input ep_;
reg [10:0] _len;
integer _j;
begin
if (len_ == 0)
_len = 1024;
else
_len = len_;
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
TSK_TX_SYNCHRONIZE(0, 0);
trn_td <= #(Tcq) {
1'b0,
2'b11,
5'b00000,
1'b0,
tc_,
4'b0000,
1'b0,
1'b0,
2'b00,
2'b00,
len_, // 32
COMPLETER_ID_CFG,
tag_,
last_dw_be_,
first_dw_be_ // 64
};
trn_tsof_n <= #(Tcq) 0;
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
addr_[63:2],
2'b00
};
trn_tsof_n <= #(Tcq) 1;
for (_j = 0; _j < (_len * 4); _j = _j + 8) begin
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
DATA_STORE[_j + 0],
DATA_STORE[_j + 1],
DATA_STORE[_j + 2],
DATA_STORE[_j + 3],
DATA_STORE[_j + 4],
DATA_STORE[_j + 5],
DATA_STORE[_j + 6],
DATA_STORE[_j + 7]
};
if ((_j + 7) >= ((_len * 4) - 1)) begin
trn_teof_n <= #(Tcq) 0;
if (ep_)
trn_terrfwd_n <= #(Tcq) 0;
if ((_len % 2) == 0)
trn_trem_ni <= #(Tcq) 8'h00;
else
trn_trem_ni <= #(Tcq) 8'h0f;
end
end
TSK_TX_SYNCHRONIZE(1, 1);
trn_teof_n <= #(Tcq) 1;
trn_terrfwd_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 1;
end
endtask // TSK_TX_MEMORY_WRITE_64
/************************************************************
Task : TSK_TX_COMPLETION
Inputs : Tag, TC, Length, Completion ID
Outputs : Transaction Tx Interface Signaling
Description : Generates a Completion TLP
*************************************************************/
task TSK_TX_COMPLETION;
input [7:0] tag_;
input [2:0] tc_;
input [9:0] len_;
input [2:0] comp_status_;
begin
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
TSK_TX_SYNCHRONIZE(0, 0);
trn_td <= #(Tcq) {
1'b0,
2'b00,
5'b01010,
1'b0,
tc_,
4'b0000,
1'b0,
1'b0,
2'b00,
2'b00,
len_, // 32
COMPLETER_ID_CFG,
comp_status_,
1'b0,
12'b0
};
trn_tsof_n <= #(Tcq) 0;
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
REQUESTER_ID,
tag_,
8'b00,
32'b0
};
trn_tsof_n <= #(Tcq) 1;
trn_teof_n <= #(Tcq) 0;
trn_trem_ni <= #(Tcq) 8'h0F;
TSK_TX_SYNCHRONIZE(1, 1);
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 1;
end
endtask // TSK_TX_COMPLETION
/************************************************************
Task : TSK_TX_COMPLETION_DATA
Inputs : Tag, TC, Length, Completion ID
Outputs : Transaction Tx Interface Signaling
Description : Generates a Completion TLP
*************************************************************/
task TSK_TX_COMPLETION_DATA;
input [7:0] tag_;
input [2:0] tc_;
input [9:0] len_;
input [11:0] byte_count_;
input [6:0] lower_addr_;
input [2:0] comp_status_;
input ep_;
reg [10:0] _len;
integer _j;
begin
if (len_ == 0)
_len = 1024;
else
_len = len_;
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
TSK_TX_SYNCHRONIZE(0, 0);
trn_td <= #(Tcq) {
1'b0,
2'b10,
5'b01010,
1'b0,
tc_,
4'b0000,
1'b0,
1'b0,
2'b00,
2'b00,
len_, // 32
COMPLETER_ID_CFG,
comp_status_,
1'b0,
byte_count_ // 64
};
trn_tsof_n <= #(Tcq) 0;
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
REQUESTER_ID,
tag_,
1'b0,
lower_addr_,
DATA_STORE[0],
DATA_STORE[1],
DATA_STORE[2],
DATA_STORE[3]
};
trn_tsof_n <= #(Tcq) 1;
if (_len != 1) begin
for (_j = 4; _j < (_len * 4); _j = _j + 8) begin
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
DATA_STORE[_j + 0],
DATA_STORE[_j + 1],
DATA_STORE[_j + 2],
DATA_STORE[_j + 3],
DATA_STORE[_j + 4],
DATA_STORE[_j + 5],
DATA_STORE[_j + 6],
DATA_STORE[_j + 7]
};
if ((_j + 7) >= ((_len * 4) - 1)) begin
trn_teof_n <= #(Tcq) 0;
if (ep_)
trn_terrfwd_n <= #(Tcq) 0;
if (((_len - 1) % 2) == 0)
trn_trem_ni <= #(Tcq) 8'h00;
else
trn_trem_ni <= #(Tcq) 8'h0f;
end
end
end else begin
trn_teof_n <= #(Tcq) 0;
trn_trem_ni <= #(Tcq) 8'h00;
end
TSK_TX_SYNCHRONIZE(1, 1);
trn_teof_n <= #(Tcq) 1;
trn_terrfwd_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 1;
end
endtask // TSK_TX_COMPLETION_DATA
/************************************************************
Task : TSK_TX_MESSAGE
Inputs : Tag, TC, Address, Message Routing, Message Code
Outputs : Transaction Tx Interface Signaling
Description : Generates a Message TLP
*************************************************************/
task TSK_TX_MESSAGE;
input [7:0] tag_;
input [2:0] tc_;
input [9:0] len_;
input [63:0] data_;
input [2:0] message_rtg_;
input [7:0] message_code_;
begin
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
TSK_TX_SYNCHRONIZE(0, 0);
trn_td <= #(Tcq) {
1'b0,
2'b01,
{{2'b10}, {message_rtg_}},
1'b0,
tc_,
4'b0000,
1'b0,
1'b0,
2'b00,
2'b00,
10'b0, // 32
COMPLETER_ID_CFG,
tag_,
message_code_ // 64
};
trn_tsof_n <= #(Tcq) 0;
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
data_
};
trn_tsof_n <= #(Tcq) 1;
trn_teof_n <= #(Tcq) 0;
trn_trem_ni <= #(Tcq) 8'h00;
TSK_TX_SYNCHRONIZE(1, 1);
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 1;
end
endtask // TSK_TX_MESSAGE
/************************************************************
Task : TSK_TX_MESSAGE_DATA
Inputs : Tag, TC, Address, Message Routing, Message Code
Outputs : Transaction Tx Interface Signaling
Description : Generates a Message Data TLP
*************************************************************/
task TSK_TX_MESSAGE_DATA;
input [7:0] tag_;
input [2:0] tc_;
input [9:0] len_;
input [63:0] data_;
input [2:0] message_rtg_;
input [7:0] message_code_;
reg [10:0] _len;
integer _j;
begin
if (len_ == 0)
_len = 1024;
else
_len = len_;
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
TSK_TX_SYNCHRONIZE(0, 0);
trn_td <= #(Tcq) {
1'b0,
2'b11,
{{2'b10}, {message_rtg_}},
1'b0,
tc_,
4'b0000,
1'b0,
1'b0,
2'b00,
2'b00,
len_, // 32
COMPLETER_ID_CFG,
tag_,
message_code_ // 64
};
trn_tsof_n <= #(Tcq) 0;
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
data_
};
trn_tsof_n <= #(Tcq) 1;
for (_j = 0; _j < (_len * 4); _j = _j + 8) begin
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
DATA_STORE[_j + 0],
DATA_STORE[_j + 1],
DATA_STORE[_j + 2],
DATA_STORE[_j + 3],
DATA_STORE[_j + 4],
DATA_STORE[_j + 5],
DATA_STORE[_j + 6],
DATA_STORE[_j + 7]
};
if ((_j + 7) >= ((_len * 4) - 1)) begin
trn_teof_n <= #(Tcq) 0;
if ((_len % 2) == 0)
trn_trem_ni <= #(Tcq) 8'h00;
else
trn_trem_ni <= #(Tcq) 8'h0f;
end
end
TSK_TX_SYNCHRONIZE(1, 1);
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 1;
end
endtask // TSK_TX_MESSAGE_DATA
/************************************************************
Task : TSK_TX_IO_READ
Inputs : Tag, Address
Outputs : Transaction Tx Interface Signaling
Description : Generates a IO Read TLP
*************************************************************/
task TSK_TX_IO_READ;
input [7:0] tag_;
input [31:0] addr_;
input [3:0] first_dw_be_;
begin
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
TSK_TX_SYNCHRONIZE(0, 0);
trn_td <= #(Tcq) {
1'b0,
2'b00,
5'b00010,
1'b0,
3'b000,
4'b0000,
1'b0,
1'b0,
2'b00,
2'b00,
10'b1, // 32
COMPLETER_ID_CFG,
tag_,
4'b0,
first_dw_be_ // 64
};
trn_tsof_n <= #(Tcq) 0;
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
addr_[31:2],
2'b00,
32'b0
};
trn_tsof_n <= #(Tcq) 1;
trn_teof_n <= #(Tcq) 0;
trn_trem_ni <= #(Tcq) 8'h0F;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 1);
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 1;
end
endtask // TSK_TX_IO_READ
/************************************************************
Task : TSK_TX_IO_WRITE
Inputs : Tag, Address, Data
Outputs : Transaction Tx Interface Signaling
Description : Generates a IO Read TLP
*************************************************************/
task TSK_TX_IO_WRITE;
input [7:0] tag_;
input [31:0] addr_;
input [3:0] first_dw_be_;
input [31:0] data_;
begin
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
TSK_TX_SYNCHRONIZE(0, 0);
trn_td <= #(Tcq) {
1'b0,
2'b10,
5'b00010,
1'b0,
3'b000,
4'b0000,
1'b0,
1'b0,
2'b00,
2'b00,
10'b1, // 32
COMPLETER_ID_CFG,
tag_,
4'b0,
first_dw_be_ // 64
};
trn_tsof_n <= #(Tcq) 0;
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
addr_[31:2],
2'b00,
data_[7:0],
data_[15:8],
data_[23:16],
data_[31:24]
};
trn_tsof_n <= #(Tcq) 1;
trn_teof_n <= #(Tcq) 0;
trn_trem_ni <= #(Tcq) 8'h00;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 1);
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 1;
end
endtask // TSK_TX_IO_WRITE
/************************************************************
Task : TSK_TX_SYNCHRONIZE
Inputs : None
Outputs : None
Description : Synchronize with tx clock and handshake signals
*************************************************************/
task TSK_TX_SYNCHRONIZE;
input first_;
input last_call_;
reg last_;
begin
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
@(posedge trn_clk);
if ((trn_tdst_rdy_n == 1'b1) && (first_ == 1'b1)) begin
while (trn_tdst_rdy_n == 1'b1) begin
@(posedge trn_clk);
end
end
if (first_ == 1'b1) begin
last_ = (trn_trem_ni == 8'h00) ? 0 : 1;
// read data driven into memory
board.RP.com_usrapp.TSK_READ_DATA(last_,
`TX_LOG,
trn_td,
trn_trem_ni);
end
if (last_call_)
board.RP.com_usrapp.TSK_PARSE_FRAME(`TX_LOG);
end
endtask // TSK_TX_SYNCHRONIZE
/************************************************************
Task : TSK_USR_DATA_SETUP_SEQ
Inputs : None
Outputs : None
Description : Populates scratch pad data area with known good data.
*************************************************************/
task TSK_USR_DATA_SETUP_SEQ;
integer i_;
begin
for (i_ = 0; i_ <= 4095; i_ = i_ + 1) begin
DATA_STORE[i_] = i_;
end
end
endtask // TSK_USR_DATA_SETUP_SEQ
/************************************************************
Task : TSK_TX_CLK_EAT
Inputs : None
Outputs : None
Description : Consume clocks.
*************************************************************/
task TSK_TX_CLK_EAT;
input [31:0] clock_count;
integer i_;
begin
for (i_ = 0; i_ < clock_count; i_ = i_ + 1) begin
@(posedge trn_clk);
end
end
endtask // TSK_TX_CLK_EAT
/************************************************************
Task: TSK_SIMULATION_TIMEOUT
Description: Set simulation timeout value
*************************************************************/
task TSK_SIMULATION_TIMEOUT;
input [31:0] timeout;
begin
force board.RP.rx_usrapp.sim_timeout = timeout;
end
endtask
/************************************************************
Task : TSK_TX_BAR_READ
Inputs : Tag, Length, Address, Last Byte En, First Byte En
Outputs : Transaction Tx Interface Signaling
Description : Generates a Memory Read 32,64 or IO Read TLP
requesting 1 dword
*************************************************************/
task TSK_TX_BAR_READ;
input [2:0] bar_index;
input [31:0] byte_offset;
input [7:0] tag_;
input [2:0] tc_;
begin
case(BAR_INIT_P_BAR_ENABLED[bar_index])
2'b01 : // IO SPACE
begin
if (verbose) $display("[%t] : IOREAD, address = %x", $realtime,
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset));
TSK_TX_IO_READ(tag_, BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset), 4'hF);
end
2'b10 : // MEM 32 SPACE
begin
if (verbose) $display("[%t] : MEMREAD32, address = %x", $realtime,
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset));
TSK_TX_MEMORY_READ_32(tag_, tc_, 10'd1,
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset), 4'h0, 4'hF);
end
2'b11 : // MEM 64 SPACE
begin
if (verbose) $display("[%t] : MEMREAD64, address = %x", $realtime,
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset));
TSK_TX_MEMORY_READ_64(tag_, tc_, 10'd1, {BAR_INIT_P_BAR[ii+1][31:0],
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset)}, 4'h0, 4'hF);
end
default : begin
$display("Error case in task TSK_TX_BAR_READ");
end
endcase
end
endtask // TSK_TX_BAR_READ
/************************************************************
Task : TSK_TX_BAR_WRITE
Inputs : Bar Index, Byte Offset, Tag, Tc, 32 bit Data
Outputs : Transaction Tx Interface Signaling
Description : Generates a Memory Write 32, 64, IO TLP with
32 bit data
*************************************************************/
task TSK_TX_BAR_WRITE;
input [2:0] bar_index;
input [31:0] byte_offset;
input [7:0] tag_;
input [2:0] tc_;
input [31:0] data_;
begin
case(BAR_INIT_P_BAR_ENABLED[bar_index])
2'b01 : // IO SPACE
begin
if (verbose) $display("[%t] : IOWRITE, address = %x, Write Data %x", $realtime,
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset), data_);
TSK_TX_IO_WRITE(tag_, BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset), 4'hF, data_);
end
2'b10 : // MEM 32 SPACE
begin
DATA_STORE[0] = data_[7:0];
DATA_STORE[1] = data_[15:8];
DATA_STORE[2] = data_[23:16];
DATA_STORE[3] = data_[31:24];
if (verbose) $display("[%t] : MEMWRITE32, address = %x, Write Data %x", $realtime,
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset), data_);
TSK_TX_MEMORY_WRITE_32(tag_, tc_, 10'd1,
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset), 4'h0, 4'hF, 1'b0);
end
2'b11 : // MEM 64 SPACE
begin
DATA_STORE[0] = data_[7:0];
DATA_STORE[1] = data_[15:8];
DATA_STORE[2] = data_[23:16];
DATA_STORE[3] = data_[31:24];
if (verbose) $display("[%t] : MEMWRITE64, address = %x, Write Data %x", $realtime,
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset), data_);
TSK_TX_MEMORY_WRITE_64(tag_, tc_, 10'd1, {BAR_INIT_P_BAR[bar_index+1][31:0],
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset)}, 4'h0, 4'hF, 1'b0);
end
default : begin
$display("Error case in task TSK_TX_BAR_WRITE");
end
endcase
end
endtask // TSK_TX_BAR_WRITE
/************************************************************
Task : TSK_SET_READ_DATA
Inputs : Data
Outputs : None
Description : Called from common app. Common app hands read
data to usrapp_tx.
*************************************************************/
task TSK_SET_READ_DATA;
input [3:0] be_; // not implementing be's yet
input [31:0] data_; // might need to change this to byte
begin
P_READ_DATA = data_;
p_read_data_valid = 1;
end
endtask // TSK_SET_READ_DATA
/************************************************************
Task : TSK_WAIT_FOR_READ_DATA
Inputs : None
Outputs : Read data P_READ_DATA will be valid
Description : Called from tx app. Common app hands read
data to usrapp_tx. This task must be executed
immediately following a call to
TSK_TX_TYPE0_CONFIGURATION_READ in order for the
read process to function correctly. Otherwise
there is a potential race condition with
p_read_data_valid.
*************************************************************/
task TSK_WAIT_FOR_READ_DATA;
integer j;
begin
j = 10;
p_read_data_valid = 0;
fork
while ((!p_read_data_valid) && (cpld_to == 0)) @(posedge trn_clk);
begin // second process
while ((j > 0) && (!p_read_data_valid))
begin
TSK_TX_CLK_EAT(500);
j = j - 1;
end
if (!p_read_data_valid) begin
cpld_to = 1;
if (cpld_to_finish == 1) begin
$display("TIMEOUT ERROR in usrapp_tx:TSK_WAIT_FOR_READ_DATA. Completion data never received.");
$finish;
end
else
$display("TIMEOUT WARNING in usrapp_tx:TSK_WAIT_FOR_READ_DATA. Completion data never received.");
end
end
join
end
endtask // TSK_WAIT_FOR_READ_DATA
/************************************************************
Function : TSK_DISPLAY_PCIE_MAP
Inputs : none
Outputs : none
Description : Displays the Memory Manager's P_MAP calculations
based on range values read from PCI_E device.
*************************************************************/
task TSK_DISPLAY_PCIE_MAP;
reg[2:0] ii;
begin
for (ii=0; ii <= 6; ii = ii + 1) begin
if (ii !=6) begin
$display("\tBAR %x: VALUE = %x RANGE = %x TYPE = %s", ii, BAR_INIT_P_BAR[ii][31:0],
BAR_INIT_P_BAR_RANGE[ii], BAR_INIT_MESSAGE[BAR_INIT_P_BAR_ENABLED[ii]]);
end
else begin
$display("\tEROM : VALUE = %x RANGE = %x TYPE = %s", BAR_INIT_P_BAR[6][31:0],
BAR_INIT_P_BAR_RANGE[6], BAR_INIT_MESSAGE[BAR_INIT_P_BAR_ENABLED[6]]);
end
end
end
endtask
/************************************************************
Task : TSK_BUILD_PCIE_MAP
Inputs :
Outputs :
Description : Looks at range values read from config space and
builds corresponding mem/io map
*************************************************************/
task TSK_BUILD_PCIE_MAP;
integer ii;
begin
$display("[%t] PCI EXPRESS BAR MEMORY/IO MAPPING PROCESS BEGUN...",$realtime);
// handle bars 0-6 (including erom)
for (ii = 0; ii <= 6; ii = ii + 1) begin
if (BAR_INIT_P_BAR_RANGE[ii] != 32'h0000_0000) begin
if ((ii != 6) && (BAR_INIT_P_BAR_RANGE[ii] & 32'h0000_0001)) begin // if not erom and io bit set
// bar is io mapped
NUMBER_OF_IO_BARS = NUMBER_OF_IO_BARS + 1;
if (pio_check_design && (NUMBER_OF_IO_BARS > 1)) begin
$display("[%t] Warning: PIO design only supports 1 IO BAR. Testbench will disable BAR %x",$realtime, ii);
BAR_INIT_P_BAR_ENABLED[ii] = 2'h0; // disable BAR
end
else BAR_INIT_P_BAR_ENABLED[ii] = 2'h1;
if (!OUT_OF_IO) begin
// We need to calculate where the next BAR should start based on the BAR's range
BAR_INIT_TEMP = BAR_INIT_P_IO_START & {1'b1,(BAR_INIT_P_BAR_RANGE[ii] & 32'hffff_fff0)};
if (BAR_INIT_TEMP < BAR_INIT_P_IO_START) begin
// Current BAR_INIT_P_IO_START is NOT correct start for new base
BAR_INIT_P_BAR[ii] = BAR_INIT_TEMP + FNC_CONVERT_RANGE_TO_SIZE_32(ii);
BAR_INIT_P_IO_START = BAR_INIT_P_BAR[ii] + FNC_CONVERT_RANGE_TO_SIZE_32(ii);
end
else begin
// Initial BAR case and Current BAR_INIT_P_IO_START is correct start for new base
BAR_INIT_P_BAR[ii] = BAR_INIT_P_IO_START;
BAR_INIT_P_IO_START = BAR_INIT_P_IO_START + FNC_CONVERT_RANGE_TO_SIZE_32(ii);
end
OUT_OF_IO = BAR_INIT_P_BAR[ii][32];
if (OUT_OF_IO) begin
$display("\tOut of PCI EXPRESS IO SPACE due to BAR %x", ii);
end
end
else begin
$display("\tOut of PCI EXPRESS IO SPACE due to BAR %x", ii);
end
end // bar is io mapped
else begin
// bar is mem mapped
if ((ii != 5) && (BAR_INIT_P_BAR_RANGE[ii] & 32'h0000_0004)) begin
// bar is mem64 mapped - memManager is not handling out of 64bit memory
NUMBER_OF_MEM64_BARS = NUMBER_OF_MEM64_BARS + 1;
if (pio_check_design && (NUMBER_OF_MEM64_BARS > 1)) begin
$display("[%t] Warning: PIO design only supports 1 MEM64 BAR. Testbench will disable BAR %x",$realtime, ii);
BAR_INIT_P_BAR_ENABLED[ii] = 2'h0; // disable BAR
end
else BAR_INIT_P_BAR_ENABLED[ii] = 2'h3; // bar is mem64 mapped
if ( (BAR_INIT_P_BAR_RANGE[ii] & 32'hFFFF_FFF0) == 32'h0000_0000) begin
// Mem64 space has range larger than 2 Gigabytes
// calculate where the next BAR should start based on the BAR's range
BAR_INIT_TEMP = BAR_INIT_P_MEM64_HI_START & BAR_INIT_P_BAR_RANGE[ii+1];
if (BAR_INIT_TEMP < BAR_INIT_P_MEM64_HI_START) begin
// Current MEM32_START is NOT correct start for new base
BAR_INIT_P_BAR[ii+1] = BAR_INIT_TEMP + FNC_CONVERT_RANGE_TO_SIZE_HI32(ii+1);
BAR_INIT_P_BAR[ii] = 32'h0000_0000;
BAR_INIT_P_MEM64_HI_START = BAR_INIT_P_BAR[ii+1] + FNC_CONVERT_RANGE_TO_SIZE_HI32(ii+1);
BAR_INIT_P_MEM64_LO_START = 32'h0000_0000;
end
else begin
// Initial BAR case and Current MEM32_START is correct start for new base
BAR_INIT_P_BAR[ii] = 32'h0000_0000;
BAR_INIT_P_BAR[ii+1] = BAR_INIT_P_MEM64_HI_START;
BAR_INIT_P_MEM64_HI_START = BAR_INIT_P_MEM64_HI_START + FNC_CONVERT_RANGE_TO_SIZE_HI32(ii+1);
end
end
else begin
// Mem64 space has range less than/equal 2 Gigabytes
// calculate where the next BAR should start based on the BAR's range
BAR_INIT_TEMP = BAR_INIT_P_MEM64_LO_START & (BAR_INIT_P_BAR_RANGE[ii] & 32'hffff_fff0);
if (BAR_INIT_TEMP < BAR_INIT_P_MEM64_LO_START) begin
// Current MEM32_START is NOT correct start for new base
BAR_INIT_P_BAR[ii] = BAR_INIT_TEMP + FNC_CONVERT_RANGE_TO_SIZE_32(ii);
BAR_INIT_P_BAR[ii+1] = BAR_INIT_P_MEM64_HI_START;
BAR_INIT_P_MEM64_LO_START = BAR_INIT_P_BAR[ii] + FNC_CONVERT_RANGE_TO_SIZE_32(ii);
end
else begin
// Initial BAR case and Current MEM32_START is correct start for new base
BAR_INIT_P_BAR[ii] = BAR_INIT_P_MEM64_LO_START;
BAR_INIT_P_BAR[ii+1] = BAR_INIT_P_MEM64_HI_START;
BAR_INIT_P_MEM64_LO_START = BAR_INIT_P_MEM64_LO_START + FNC_CONVERT_RANGE_TO_SIZE_32(ii);
end
end
// skip over the next bar since it is being used by the 64bit bar
ii = ii + 1;
end
else begin
if ( (ii != 6) || ((ii == 6) && (BAR_INIT_P_BAR_RANGE[ii] & 32'h0000_0001)) ) begin
// handling general mem32 case and erom case
// bar is mem32 mapped
if (ii != 6) begin
NUMBER_OF_MEM32_BARS = NUMBER_OF_MEM32_BARS + 1; // not counting erom space
if (pio_check_design && (NUMBER_OF_MEM32_BARS > 1)) begin
// PIO design only supports 1 general purpose MEM32 BAR (not including EROM).
$display("[%t] Warning: PIO design only supports 1 MEM32 BAR. Testbench will disable BAR %x",$realtime, ii);
BAR_INIT_P_BAR_ENABLED[ii] = 2'h0; // disable BAR
end
else BAR_INIT_P_BAR_ENABLED[ii] = 2'h2; // bar is mem32 mapped
end
else BAR_INIT_P_BAR_ENABLED[ii] = 2'h2; // erom bar is mem32 mapped
if (!OUT_OF_LO_MEM) begin
// We need to calculate where the next BAR should start based on the BAR's range
BAR_INIT_TEMP = BAR_INIT_P_MEM32_START & {1'b1,(BAR_INIT_P_BAR_RANGE[ii] & 32'hffff_fff0)};
if (BAR_INIT_TEMP < BAR_INIT_P_MEM32_START) begin
// Current MEM32_START is NOT correct start for new base
BAR_INIT_P_BAR[ii] = BAR_INIT_TEMP + FNC_CONVERT_RANGE_TO_SIZE_32(ii);
BAR_INIT_P_MEM32_START = BAR_INIT_P_BAR[ii] + FNC_CONVERT_RANGE_TO_SIZE_32(ii);
end
else begin
// Initial BAR case and Current MEM32_START is correct start for new base
BAR_INIT_P_BAR[ii] = BAR_INIT_P_MEM32_START;
BAR_INIT_P_MEM32_START = BAR_INIT_P_MEM32_START + FNC_CONVERT_RANGE_TO_SIZE_32(ii);
end
if (ii == 6) begin
// make sure to set enable bit if we are mapping the erom space
BAR_INIT_P_BAR[ii] = BAR_INIT_P_BAR[ii] | 33'h1;
end
OUT_OF_LO_MEM = BAR_INIT_P_BAR[ii][32];
if (OUT_OF_LO_MEM) begin
$display("\tOut of PCI EXPRESS MEMORY 32 SPACE due to BAR %x", ii);
end
end
else begin
$display("\tOut of PCI EXPRESS MEMORY 32 SPACE due to BAR %x", ii);
end
end
end
end
end
end
if ( (OUT_OF_IO) | (OUT_OF_LO_MEM) | (OUT_OF_HI_MEM)) begin
TSK_DISPLAY_PCIE_MAP;
$display("ERROR: Ending simulation: Memory Manager is out of memory/IO to allocate to PCI Express device");
$finish;
end
end
endtask // TSK_BUILD_PCIE_MAP
/************************************************************
Task : TSK_BAR_SCAN
Inputs : None
Outputs : None
Description : Scans PCI core's configuration registers.
*************************************************************/
task TSK_BAR_SCAN;
begin
//--------------------------------------------------------------------------
// Write PCI_MASK to bar's space via PCIe fabric interface to find range
//--------------------------------------------------------------------------
P_ADDRESS_MASK = 32'hffff_ffff;
DEFAULT_TAG = 0;
DEFAULT_TC = 0;
$display("[%t] : Inspecting Core Configuration Space...", $realtime);
// Determine Range for BAR0
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h10, P_ADDRESS_MASK, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read BAR0 Range
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h10, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_WAIT_FOR_READ_DATA;
BAR_INIT_P_BAR_RANGE[0] = P_READ_DATA;
// Determine Range for BAR1
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h14, P_ADDRESS_MASK, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read BAR1 Range
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h14, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_WAIT_FOR_READ_DATA;
BAR_INIT_P_BAR_RANGE[1] = P_READ_DATA;
// Determine Range for BAR2
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h18, P_ADDRESS_MASK, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read BAR2 Range
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h18, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_WAIT_FOR_READ_DATA;
BAR_INIT_P_BAR_RANGE[2] = P_READ_DATA;
// Determine Range for BAR3
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h1C, P_ADDRESS_MASK, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read BAR3 Range
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h1C, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_WAIT_FOR_READ_DATA;
BAR_INIT_P_BAR_RANGE[3] = P_READ_DATA;
// Determine Range for BAR4
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h20, P_ADDRESS_MASK, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read BAR4 Range
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h20, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_WAIT_FOR_READ_DATA;
BAR_INIT_P_BAR_RANGE[4] = P_READ_DATA;
// Determine Range for BAR5
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h24, P_ADDRESS_MASK, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read BAR5 Range
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h24, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_WAIT_FOR_READ_DATA;
BAR_INIT_P_BAR_RANGE[5] = P_READ_DATA;
// Determine Range for Expansion ROM BAR
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h30, P_ADDRESS_MASK, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read Expansion ROM BAR Range
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h30, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_WAIT_FOR_READ_DATA;
BAR_INIT_P_BAR_RANGE[6] = P_READ_DATA;
end
endtask // TSK_BAR_SCAN
/************************************************************
Task : TSK_BAR_PROGRAM
Inputs : None
Outputs : None
Description : Program's PCI core's configuration registers.
*************************************************************/
task TSK_BAR_PROGRAM;
begin
//--------------------------------------------------------------------------
// Write core configuration space via PCIe fabric interface
//--------------------------------------------------------------------------
DEFAULT_TAG = 0;
P_DEV_BDF = 16'h00_0_0;
$display("[%t] : Setting Core Configuration Space...", $realtime);
// Program BAR0
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h10, BAR_INIT_P_BAR[0][31:0], 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Program BAR1
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h14, BAR_INIT_P_BAR[1][31:0], 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Program BAR2
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h18, BAR_INIT_P_BAR[2][31:0], 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Program BAR3
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h1C, BAR_INIT_P_BAR[3][31:0], 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Program BAR4
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h20, BAR_INIT_P_BAR[4][31:0], 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Program BAR5
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h24, BAR_INIT_P_BAR[5][31:0], 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Program Expansion ROM BAR
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h30, BAR_INIT_P_BAR[6][31:0], 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Program PCI Command Register
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h04, 32'h00000003, 4'h1);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Program PCIe Device Control Register
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h68, 32'h0000005f, 4'h1);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(1000);
end
endtask // TSK_BAR_PROGRAM
/************************************************************
Task : TSK_BAR_INIT
Inputs : None
Outputs : None
Description : Initialize PCI core based on core's configuration.
*************************************************************/
task TSK_BAR_INIT;
begin
TSK_BAR_SCAN;
TSK_BUILD_PCIE_MAP;
TSK_DISPLAY_PCIE_MAP;
TSK_BAR_PROGRAM;
end
endtask // TSK_BAR_INIT
/************************************************************
Task : TSK_TX_READBACK_CONFIG
Inputs : None
Outputs : None
Description : Read core configuration space via PCIe fabric interface
*************************************************************/
task TSK_TX_READBACK_CONFIG;
begin
//--------------------------------------------------------------------------
// Read core configuration space via PCIe fabric interface
//--------------------------------------------------------------------------
$display("[%t] : Reading Core Configuration Space...", $realtime);
// Read BAR0
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h10, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read BAR1
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h14, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read BAR2
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h18, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read BAR3
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h1C, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read BAR4
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h20, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read BAR5
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h24, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read Expansion ROM BAR
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h30, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read PCI Command Register
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h04, 4'h1);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read PCIe Device Control Register
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h60, 4'h1);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(1000);
end
endtask // TSK_TX_READBACK_CONFIG
/************************************************************
Task : TSK_CFG_READBACK_CONFIG
Inputs : None
Outputs : None
Description : Read core configuration space via CFG interface
*************************************************************/
task TSK_CFG_READBACK_CONFIG;
begin
//--------------------------------------------------------------------------
// Read core configuration space via configuration (host) interface
//--------------------------------------------------------------------------
$display("[%t] : Reading Local Configuration Space via CFG interface...", $realtime);
CFG_DWADDR = 10'h0;
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
CFG_DWADDR = 10'h4;
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
CFG_DWADDR = 10'h5;
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
CFG_DWADDR = 10'h6;
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
CFG_DWADDR = 10'h7;
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
CFG_DWADDR = 10'h8;
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
CFG_DWADDR = 10'h9;
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
CFG_DWADDR = 10'hc;
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
CFG_DWADDR = 10'h17;
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
CFG_DWADDR = 10'h18;
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
CFG_DWADDR = 10'h19;
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
CFG_DWADDR = 10'h1a;
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
end
endtask // TSK_CFG_READBACK_CONFIG
/************************************************************
Task : TSK_MEM_TEST_DATA_BUS
Inputs : bar_index
Outputs : None
Description : Test the data bus wiring in a specific memory
by executing a walking 1's test at a set address
within that region.
*************************************************************/
task TSK_MEM_TEST_DATA_BUS;
input [2:0] bar_index;
reg [31:0] pattern;
reg success;
begin
$display("[%t] : Performing Memory data test to address %x", $realtime, BAR_INIT_P_BAR[bar_index][31:0]);
success = 1; // assume success
// Perform a walking 1's test at the given address.
for (pattern = 1; pattern != 0; pattern = pattern << 1)
begin
// Write the test pattern. *address = pattern;pio_memTestAddrBus_test1
TSK_TX_BAR_WRITE(bar_index, 32'h0, DEFAULT_TAG, DEFAULT_TC, pattern);
TSK_TX_CLK_EAT(10);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_BAR_READ(bar_index, 32'h0, DEFAULT_TAG, DEFAULT_TC);
TSK_WAIT_FOR_READ_DATA;
if (P_READ_DATA != pattern)
begin
$display("[%t] : Data Error Mismatch, Address: %x Write Data %x != Read Data %x", $realtime,
BAR_INIT_P_BAR[bar_index][31:0], pattern, P_READ_DATA);
success = 0;
$finish;
end
else
begin
$display("[%t] : Address: %x Write Data: %x successfully received", $realtime,
BAR_INIT_P_BAR[bar_index][31:0], P_READ_DATA);
end
TSK_TX_CLK_EAT(10);
DEFAULT_TAG = DEFAULT_TAG + 1;
end // for loop
if (success == 1)
$display("[%t] : TSK_MEM_TEST_DATA_BUS successfully completed", $realtime);
else
$display("[%t] : TSK_MEM_TEST_DATA_BUS completed with errors", $realtime);
end
endtask // TSK_MEM_TEST_DATA_BUS
/************************************************************
Task : TSK_MEM_TEST_ADDR_BUS
Inputs : bar_index, nBytes
Outputs : None
Description : Test the address bus wiring in a specific memory by
performing a walking 1's test on the relevant bits
of the address and checking for multiple writes/aliasing.
This test will find single-bit address failures such as stuck
-high, stuck-low, and shorted pins.
*************************************************************/
task TSK_MEM_TEST_ADDR_BUS;
input [2:0] bar_index;
input [31:0] nBytes;
reg [31:0] pattern;
reg [31:0] antipattern;
reg [31:0] addressMask;
reg [31:0] offset;
reg [31:0] testOffset;
reg success;
reg stuckHi_success;
reg stuckLo_success;
begin
$display("[%t] : Performing Memory address test to address %x", $realtime, BAR_INIT_P_BAR[bar_index][31:0]);
success = 1; // assume success
stuckHi_success = 1;
stuckLo_success = 1;
pattern = 32'hAAAAAAAA;
antipattern = 32'h55555555;
// divide by 4 because the block RAMS we are testing are 32bit wide
// and therefore the low two bits are not meaningful for addressing purposes
// for this test.
addressMask = (nBytes/4 - 1);
$display("[%t] : Checking for address bits stuck high", $realtime);
// Write the default pattern at each of the power-of-two offsets.
for (offset = 1; (offset & addressMask) != 0; offset = offset << 1)
begin
verbose = 1;
// baseAddress[offset] = pattern
TSK_TX_BAR_WRITE(bar_index, 4*offset, DEFAULT_TAG, DEFAULT_TC, pattern);
TSK_TX_CLK_EAT(10);
DEFAULT_TAG = DEFAULT_TAG + 1;
end
// Check for address bits stuck high.
// It should be noted that since the write address and read address pins are different
// for the block RAMs used in the PIO design, the stuck high test will only catch an error if both
// read and write addresses are both stuck hi. Otherwise the remaining portion of the tests
// will catch if only one of the addresses are stuck hi.
testOffset = 0;
// baseAddress[testOffset] = antipattern;
TSK_TX_BAR_WRITE(bar_index, 4*testOffset, DEFAULT_TAG, DEFAULT_TC, antipattern);
TSK_TX_CLK_EAT(10);
DEFAULT_TAG = DEFAULT_TAG + 1;
for (offset = 1; (offset & addressMask) != 0; offset = offset << 1)
begin
TSK_TX_BAR_READ(bar_index, 4*offset, DEFAULT_TAG, DEFAULT_TC);
TSK_WAIT_FOR_READ_DATA;
if (P_READ_DATA != pattern)
begin
$display("[%t] : Error: Pattern Mismatch, Address = %x, Write Data %x != Read Data %x",
$realtime, BAR_INIT_P_BAR[bar_index][31:0]+(4*offset), pattern, P_READ_DATA);
stuckHi_success = 0;
success = 0;
$finish;
end
else
begin
$display("[%t] : Pattern Match: Address %x Data: %x successfully received",
$realtime, BAR_INIT_P_BAR[bar_index][31:0]+(4*offset), P_READ_DATA);
end
TSK_TX_CLK_EAT(10);
DEFAULT_TAG = DEFAULT_TAG + 1;
end
if (stuckHi_success == 1)
$display("[%t] : Stuck Hi Address Test successfully completed", $realtime);
else
$display("[%t] : Error: Stuck Hi Address Test failed", $realtime);
$display("[%t] : Checking for address bits stuck low or shorted", $realtime);
//baseAddress[testOffset] = pattern;
TSK_TX_BAR_WRITE(bar_index, 4*testOffset, DEFAULT_TAG, DEFAULT_TC, pattern);
TSK_TX_CLK_EAT(10);
DEFAULT_TAG = DEFAULT_TAG + 1;
// Check for address bits stuck low or shorted.
for (testOffset = 1; (testOffset & addressMask) != 0; testOffset = testOffset << 1)
begin
//baseAddress[testOffset] = antipattern;
TSK_TX_BAR_WRITE(bar_index, 4*testOffset, DEFAULT_TAG, DEFAULT_TC, antipattern);
TSK_TX_CLK_EAT(10);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_BAR_READ(bar_index, 32'h0, DEFAULT_TAG, DEFAULT_TC);
TSK_WAIT_FOR_READ_DATA;
if (P_READ_DATA != pattern) // if (baseAddress[0] != pattern)
begin
$display("[%t] : Error: Pattern Mismatch, Address = %x, Write Data %x != Read Data %x",
$realtime, BAR_INIT_P_BAR[bar_index][31:0]+(4*0), pattern, P_READ_DATA);
stuckLo_success = 0;
success = 0;
$finish;
end
else
begin
$display("[%t] : Pattern Match: Address %x Data: %x successfully received",
$realtime, BAR_INIT_P_BAR[bar_index][31:0]+(4*offset), P_READ_DATA);
end
TSK_TX_CLK_EAT(10);
DEFAULT_TAG = DEFAULT_TAG + 1;
for (offset = 1; (offset & addressMask) != 0; offset = offset << 1)
begin
TSK_TX_BAR_READ(bar_index, 4*offset, DEFAULT_TAG, DEFAULT_TC);
TSK_WAIT_FOR_READ_DATA;
// if ((baseAddress[offset] != pattern) && (offset != testOffset))
if ((P_READ_DATA != pattern) && (offset != testOffset))
begin
$display("[%t] : Error: Pattern Mismatch, Address = %x, Write Data %x != Read Data %x",
$realtime, BAR_INIT_P_BAR[bar_index][31:0]+(4*offset),
pattern, P_READ_DATA);
stuckLo_success = 0;
success = 0;
$finish;
end
else
begin
$display("[%t] : Pattern Match: Address %x Data: %x successfully received",
$realtime, BAR_INIT_P_BAR[bar_index][31:0]+(4*offset),
P_READ_DATA);
end
TSK_TX_CLK_EAT(10);
DEFAULT_TAG = DEFAULT_TAG + 1;
end
// baseAddress[testOffset] = pattern;
TSK_TX_BAR_WRITE(bar_index, 4*testOffset, DEFAULT_TAG, DEFAULT_TC, pattern);
TSK_TX_CLK_EAT(10);
DEFAULT_TAG = DEFAULT_TAG + 1;
end
if (stuckLo_success == 1)
$display("[%t] : Stuck Low Address Test successfully completed", $realtime);
else
$display("[%t] : Error: Stuck Low Address Test failed", $realtime);
if (success == 1)
$display("[%t] : TSK_MEM_TEST_ADDR_BUS successfully completed", $realtime);
else
$display("[%t] : TSK_MEM_TEST_ADDR_BUS completed with errors", $realtime);
end
endtask // TSK_MEM_TEST_ADDR_BUS
/************************************************************
Task : TSK_MEM_TEST_DEVICE
Inputs : bar_index, nBytes
Outputs : None
* Description: Test the integrity of a physical memory device by
* performing an increment/decrement test over the
* entire region. In the process every storage bit
* in the device is tested as a zero and a one. The
* bar_index and the size of the region are
* selected by the caller.
*************************************************************/
task TSK_MEM_TEST_DEVICE;
input [2:0] bar_index;
input [31:0] nBytes;
reg [31:0] pattern;
reg [31:0] antipattern;
reg [31:0] offset;
reg [31:0] nWords;
reg success;
begin
$display("[%t] : Performing Memory device test to address %x", $realtime, BAR_INIT_P_BAR[bar_index][31:0]);
success = 1; // assume success
nWords = nBytes / 4;
pattern = 1;
// Fill memory with a known pattern.
for (offset = 0; offset < nWords; offset = offset + 1)
begin
verbose = 1;
//baseAddress[offset] = pattern;
TSK_TX_BAR_WRITE(bar_index, 4*offset, DEFAULT_TAG, DEFAULT_TC, pattern);
TSK_TX_CLK_EAT(10);
DEFAULT_TAG = DEFAULT_TAG + 1;
pattern = pattern + 1;
end
pattern = 1;
// Check each location and invert it for the second pass.
for (offset = 0; offset < nWords; offset = offset + 1)
begin
TSK_TX_BAR_READ(bar_index, 4*offset, DEFAULT_TAG, DEFAULT_TC);
TSK_WAIT_FOR_READ_DATA;
DEFAULT_TAG = DEFAULT_TAG + 1;
//if (baseAddress[offset] != pattern)
if (P_READ_DATA != pattern)
begin
$display("[%t] : Error: Pattern Mismatch, Address = %x, Write Data %x != Read Data %x", $realtime,
BAR_INIT_P_BAR[bar_index][31:0]+(4*offset), pattern, P_READ_DATA);
success = 0;
$finish;
end
antipattern = ~pattern;
//baseAddress[offset] = antipattern;
TSK_TX_BAR_WRITE(bar_index, 4*offset, DEFAULT_TAG, DEFAULT_TC, antipattern);
TSK_TX_CLK_EAT(10);
DEFAULT_TAG = DEFAULT_TAG + 1;
pattern = pattern + 1;
end
pattern = 1;
// Check each location for the inverted pattern
for (offset = 0; offset < nWords; offset = offset + 1)
begin
antipattern = ~pattern;
TSK_TX_BAR_READ(bar_index, 4*offset, DEFAULT_TAG, DEFAULT_TC);
TSK_WAIT_FOR_READ_DATA;
DEFAULT_TAG = DEFAULT_TAG + 1;
//if (baseAddress[offset] != pattern)
if (P_READ_DATA != antipattern)
begin
$display("[%t] : Error: Pattern Mismatch, Address = %x, Write Data %x != Read Data %x", $realtime,
BAR_INIT_P_BAR[bar_index][31:0]+(4*offset), pattern, P_READ_DATA);
success = 0;
$finish;
end
pattern = pattern + 1;
end
if (success == 1)
$display("[%t] : TSK_MEM_TEST_DEVICE successfully completed", $realtime);
else
$display("[%t] : TSK_MEM_TEST_DEVICE completed with errors", $realtime);
end
endtask // TSK_MEM_TEST_DEVICE
/************************************************************
Function : FNC_CONVERT_RANGE_TO_SIZE_32
Inputs : BAR index for 32 bit BAR
Outputs : 32 bit BAR size
Description : Called from tx app. Note that the smallest range
supported by this function is 16 bytes.
*************************************************************/
function [31:0] FNC_CONVERT_RANGE_TO_SIZE_32;
input [31:0] bar_index;
reg [32:0] return_value;
begin
case (BAR_INIT_P_BAR_RANGE[bar_index] & 32'hFFFF_FFF0) // AND off control bits
32'hFFFF_FFF0 : return_value = 33'h0000_0010;
32'hFFFF_FFE0 : return_value = 33'h0000_0020;
32'hFFFF_FFC0 : return_value = 33'h0000_0040;
32'hFFFF_FF80 : return_value = 33'h0000_0080;
32'hFFFF_FF00 : return_value = 33'h0000_0100;
32'hFFFF_FE00 : return_value = 33'h0000_0200;
32'hFFFF_FC00 : return_value = 33'h0000_0400;
32'hFFFF_F800 : return_value = 33'h0000_0800;
32'hFFFF_F000 : return_value = 33'h0000_1000;
32'hFFFF_E000 : return_value = 33'h0000_2000;
32'hFFFF_C000 : return_value = 33'h0000_4000;
32'hFFFF_8000 : return_value = 33'h0000_8000;
32'hFFFF_0000 : return_value = 33'h0001_0000;
32'hFFFE_0000 : return_value = 33'h0002_0000;
32'hFFFC_0000 : return_value = 33'h0004_0000;
32'hFFF8_0000 : return_value = 33'h0008_0000;
32'hFFF0_0000 : return_value = 33'h0010_0000;
32'hFFE0_0000 : return_value = 33'h0020_0000;
32'hFFC0_0000 : return_value = 33'h0040_0000;
32'hFF80_0000 : return_value = 33'h0080_0000;
32'hFF00_0000 : return_value = 33'h0100_0000;
32'hFE00_0000 : return_value = 33'h0200_0000;
32'hFC00_0000 : return_value = 33'h0400_0000;
32'hF800_0000 : return_value = 33'h0800_0000;
32'hF000_0000 : return_value = 33'h1000_0000;
32'hE000_0000 : return_value = 33'h2000_0000;
32'hC000_0000 : return_value = 33'h4000_0000;
32'h8000_0000 : return_value = 33'h8000_0000;
default : return_value = 33'h0000_0000;
endcase
FNC_CONVERT_RANGE_TO_SIZE_32 = return_value;
end
endfunction // FNC_CONVERT_RANGE_TO_SIZE_32
/************************************************************
Function : FNC_CONVERT_RANGE_TO_SIZE_HI32
Inputs : BAR index for upper 32 bit BAR of 64 bit address
Outputs : upper 32 bit BAR size
Description : Called from tx app.
*************************************************************/
function [31:0] FNC_CONVERT_RANGE_TO_SIZE_HI32;
input [31:0] bar_index;
reg [32:0] return_value;
begin
case (BAR_INIT_P_BAR_RANGE[bar_index])
32'hFFFF_FFFF : return_value = 33'h00000_0001;
32'hFFFF_FFFE : return_value = 33'h00000_0002;
32'hFFFF_FFFC : return_value = 33'h00000_0004;
32'hFFFF_FFF8 : return_value = 33'h00000_0008;
32'hFFFF_FFF0 : return_value = 33'h00000_0010;
32'hFFFF_FFE0 : return_value = 33'h00000_0020;
32'hFFFF_FFC0 : return_value = 33'h00000_0040;
32'hFFFF_FF80 : return_value = 33'h00000_0080;
32'hFFFF_FF00 : return_value = 33'h00000_0100;
32'hFFFF_FE00 : return_value = 33'h00000_0200;
32'hFFFF_FC00 : return_value = 33'h00000_0400;
32'hFFFF_F800 : return_value = 33'h00000_0800;
32'hFFFF_F000 : return_value = 33'h00000_1000;
32'hFFFF_E000 : return_value = 33'h00000_2000;
32'hFFFF_C000 : return_value = 33'h00000_4000;
32'hFFFF_8000 : return_value = 33'h00000_8000;
32'hFFFF_0000 : return_value = 33'h00001_0000;
32'hFFFE_0000 : return_value = 33'h00002_0000;
32'hFFFC_0000 : return_value = 33'h00004_0000;
32'hFFF8_0000 : return_value = 33'h00008_0000;
32'hFFF0_0000 : return_value = 33'h00010_0000;
32'hFFE0_0000 : return_value = 33'h00020_0000;
32'hFFC0_0000 : return_value = 33'h00040_0000;
32'hFF80_0000 : return_value = 33'h00080_0000;
32'hFF00_0000 : return_value = 33'h00100_0000;
32'hFE00_0000 : return_value = 33'h00200_0000;
32'hFC00_0000 : return_value = 33'h00400_0000;
32'hF800_0000 : return_value = 33'h00800_0000;
32'hF000_0000 : return_value = 33'h01000_0000;
32'hE000_0000 : return_value = 33'h02000_0000;
32'hC000_0000 : return_value = 33'h04000_0000;
32'h8000_0000 : return_value = 33'h08000_0000;
default : return_value = 33'h00000_0000;
endcase
FNC_CONVERT_RANGE_TO_SIZE_HI32 = return_value;
end
endfunction // FNC_CONVERT_RANGE_TO_SIZE_HI32
endmodule
|
module sky130_fd_sc_hs__o311ai_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
|
module sky130_fd_sc_hs__o311ai_2 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
|
module sky130_fd_sc_hs__clkdlyinv3sd2 (
Y ,
A ,
VPWR,
VGND
);
output Y ;
input A ;
input VPWR;
input VGND;
endmodule
|
module sky130_fd_sc_lp__dlxtn_2 (
Q ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_lp__dlxtn_2 (
Q ,
D ,
GATE_N
);
output Q ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N)
);
endmodule
|
module fpga_core
(
/*
* Clock: 156.25MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
input wire uart_rts,
output wire uart_cts,
/*
* Ethernet: SFP+
*/
input wire sfp0_tx_clk,
input wire sfp0_tx_rst,
output wire [63:0] sfp0_txd,
output wire [7:0] sfp0_txc,
input wire sfp0_rx_clk,
input wire sfp0_rx_rst,
input wire [63:0] sfp0_rxd,
input wire [7:0] sfp0_rxc,
input wire sfp1_tx_clk,
input wire sfp1_tx_rst,
output wire [63:0] sfp1_txd,
output wire [7:0] sfp1_txc,
input wire sfp1_rx_clk,
input wire sfp1_rx_rst,
input wire [63:0] sfp1_rxd,
input wire [7:0] sfp1_rxc,
input wire sfp2_tx_clk,
input wire sfp2_tx_rst,
output wire [63:0] sfp2_txd,
output wire [7:0] sfp2_txc,
input wire sfp2_rx_clk,
input wire sfp2_rx_rst,
input wire [63:0] sfp2_rxd,
input wire [7:0] sfp2_rxc,
input wire sfp3_tx_clk,
input wire sfp3_tx_rst,
output wire [63:0] sfp3_txd,
output wire [7:0] sfp3_txc,
input wire sfp3_rx_clk,
input wire sfp3_rx_rst,
input wire [63:0] sfp3_rxd,
input wire [7:0] sfp3_rxc
);
// AXI between MAC and Ethernet modules
wire [63:0] rx_axis_tdata;
wire [7:0] rx_axis_tkeep;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [63:0] tx_axis_tdata;
wire [7:0] tx_axis_tkeep;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [63:0] rx_eth_payload_axis_tdata;
wire [7:0] rx_eth_payload_axis_tkeep;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [63:0] tx_eth_payload_axis_tdata;
wire [7:0] tx_eth_payload_axis_tkeep;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [63:0] rx_ip_payload_axis_tdata;
wire [7:0] rx_ip_payload_axis_tkeep;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [63:0] tx_ip_payload_axis_tdata;
wire [7:0] tx_ip_payload_axis_tkeep;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [63:0] rx_udp_payload_axis_tdata;
wire [7:0] rx_udp_payload_axis_tkeep;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [63:0] tx_udp_payload_axis_tdata;
wire [7:0] tx_udp_payload_axis_tkeep;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [63:0] rx_fifo_udp_payload_axis_tdata;
wire [7:0] rx_fifo_udp_payload_axis_tkeep;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [63:0] tx_fifo_udp_payload_axis_tdata;
wire [7:0] tx_fifo_udp_payload_axis_tkeep;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tkeep = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = ~match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk) begin
if (rst) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((~match_cond_reg & ~no_match_reg) |
(rx_udp_payload_axis_tvalid & rx_udp_payload_axis_tready & rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid & match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready & match_cond) | no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tkeep = tx_fifo_udp_payload_axis_tkeep;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tkeep = rx_udp_payload_axis_tkeep;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid & match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready & match_cond_reg) | no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk) begin
if (rst) begin
led_reg <= 0;
end else begin
valid_last <= tx_udp_payload_axis_tvalid;
if (tx_udp_payload_axis_tvalid & ~valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
end
end
end
assign led = led_reg;
assign sfp1_txd = 64'h0707070707070707;
assign sfp1_txc = 8'hff;
assign sfp2_txd = 64'h0707070707070707;
assign sfp2_txc = 8'hff;
assign sfp3_txd = 64'h0707070707070707;
assign sfp3_txc = 8'hff;
eth_mac_10g_fifo #(
.ENABLE_PADDING(1),
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_10g_fifo_inst (
.rx_clk(sfp0_rx_clk),
.rx_rst(sfp0_rx_rst),
.tx_clk(sfp0_tx_clk),
.tx_rst(sfp0_tx_rst),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tkeep(tx_axis_tkeep),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tkeep(rx_axis_tkeep),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.xgmii_rxd(sfp0_rxd),
.xgmii_rxc(sfp0_rxc),
.xgmii_txd(sfp0_txd),
.xgmii_txc(sfp0_txc),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
);
eth_axis_rx #(
.DATA_WIDTH(64)
)
eth_axis_rx_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tkeep(rx_axis_tkeep),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx #(
.DATA_WIDTH(64)
)
eth_axis_tx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tkeep(tx_axis_tkeep),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete_64
udp_complete_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(tx_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(rx_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tkeep(tx_udp_payload_axis_tkeep),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tkeep(rx_udp_payload_axis_tkeep),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(1'b0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(rx_fifo_udp_payload_axis_tkeep),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(tx_fifo_udp_payload_axis_tkeep),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
|
module protection_sim;
reg RST, CLK, ENA;
reg [7:0]RGA;
reg [7:0]RGB;
wire [7:0]RGZ;
reg [1:0]KEY;
/********************************************************************
* DUMPER MONITOR *
*******************************************************************/
initial
begin
$dumpfile("vcd");
$dumpvars(0, prot);
$monitor($time, " REG A = %b REG Z = %b", RGA, RGZ);
end
/********************************************************************
* CLOCKING *
*******************************************************************/
initial
begin
CLK = 1'b1;
forever #5 CLK = ~CLK;
end
/********************************************************************
* RESET *
*******************************************************************/
initial
begin
RST = 1'b1;
#5 RST = 1'b0;
end
/********************************************************************
* DATAS INJECTION *
*******************************************************************/
initial
begin
RGA = 3'b000;
#10 RGA = 3'b111;
#10 RGA = 3'b101;
#10 RGA = 3'b110;
#10 RGA = 3'b010;
#10 RGA = 3'b011;
#10 RGA = 3'b100;
#10 RGA = 3'b010;
#10 RGA = 3'b000;
#10 RGA = 3'b111;
#10 RGA = 3'b100;
#10 RGA = 3'b010;
#10 RGA = 3'b001;
#10 RGA = 3'b010;
#10 RGA = 3'b101;
#10 RGA = 3'b011;
#10 RGA = 3'b100;
#10 RGA = 3'b010;
#10 RGA = 3'b111;
#10 RGA = 3'b011;
#10 RGA = 3'b000;
$finish;
end
/********************************************************************
* MODULE IN TEST *
*******************************************************************/
protection prot( RST, CLK, ENA, RGA, RGB, RGZ, KEY);
endmodule
|
module
//
////////////////////////////////////////////////////////////////////////
wire async_rst;
wire wb_clk, wb_rst;
wire dbg_tck;
wire sdram_clk;
wire sdram_rst;
assign sdram_clk_pad_o = sdram_clk;
clkgen clkgen0 (
.sys_clk_pad_i (sys_clk_pad_i),
.rst_n_pad_i (rst_n_pad_i),
.async_rst_o (async_rst),
.wb_clk_o (wb_clk),
.wb_rst_o (wb_rst),
`ifdef SIM
.tck_pad_i (tck_pad_i),
.dbg_tck_o (dbg_tck),
`endif
.sdram_clk_o (sdram_clk),
.sdram_rst_o (sdram_rst)
);
////////////////////////////////////////////////////////////////////////
//
// Modules interconnections
//
////////////////////////////////////////////////////////////////////////
`include "wb_intercon.vh"
`ifdef SIM
////////////////////////////////////////////////////////////////////////
//
// GENERIC JTAG TAP
//
////////////////////////////////////////////////////////////////////////
wire dbg_if_select;
wire dbg_if_tdo;
wire jtag_tap_tdo;
wire jtag_tap_shift_dr;
wire jtag_tap_pause_dr;
wire jtag_tap_update_dr;
wire jtag_tap_capture_dr;
tap_top #(.IDCODE_VALUE(IDCODE_VALUE))
jtag_tap0 (
.tdo_pad_o (tdo_pad_o),
.tms_pad_i (tms_pad_i),
.tck_pad_i (dbg_tck),
.trst_pad_i (async_rst),
.tdi_pad_i (tdi_pad_i),
.tdo_padoe_o (tdo_padoe_o),
.tdo_o (jtag_tap_tdo),
.shift_dr_o (jtag_tap_shift_dr),
.pause_dr_o (jtag_tap_pause_dr),
.update_dr_o (jtag_tap_update_dr),
.capture_dr_o (jtag_tap_capture_dr),
.extest_select_o (),
.sample_preload_select_o (),
.mbist_select_o (),
.debug_select_o (dbg_if_select),
.bs_chain_tdi_i (1'b0),
.mbist_tdi_i (1'b0),
.debug_tdi_i (dbg_if_tdo)
);
`else
////////////////////////////////////////////////////////////////////////
//
// ALTERA Virtual JTAG TAP
//
////////////////////////////////////////////////////////////////////////
wire dbg_if_select;
wire dbg_if_tdo;
wire jtag_tap_tdo;
wire jtag_tap_shift_dr;
wire jtag_tap_pause_dr;
wire jtag_tap_update_dr;
wire jtag_tap_capture_dr;
altera_virtual_jtag jtag_tap0 (
.tck_o (dbg_tck),
.debug_tdo_i (dbg_if_tdo),
.tdi_o (jtag_tap_tdo),
.test_logic_reset_o (),
.run_test_idle_o (),
.shift_dr_o (jtag_tap_shift_dr),
.capture_dr_o (jtag_tap_capture_dr),
.pause_dr_o (jtag_tap_pause_dr),
.update_dr_o (jtag_tap_update_dr),
.debug_select_o (dbg_if_select)
);
`endif
////////////////////////////////////////////////////////////////////////
//
// OR1K CPU
//
////////////////////////////////////////////////////////////////////////
wire [31:0] or1k_irq;
wire [31:0] or1k_dbg_dat_i;
wire [31:0] or1k_dbg_adr_i;
wire or1k_dbg_we_i;
wire or1k_dbg_stb_i;
wire or1k_dbg_ack_o;
wire [31:0] or1k_dbg_dat_o;
wire or1k_dbg_stall_i;
wire or1k_dbg_ewt_i;
wire [3:0] or1k_dbg_lss_o;
wire [1:0] or1k_dbg_is_o;
wire [10:0] or1k_dbg_wp_o;
wire or1k_dbg_bp_o;
wire or1k_dbg_rst;
wire sig_tick;
wire or1k_rst;
assign or1k_rst = wb_rst | or1k_dbg_rst;
`ifdef OR1200_CPU
or1200_top #(.boot_adr(32'hf0000100))
or1200_top0 (
// Instruction bus, clocks, reset
.iwb_clk_i (wb_clk),
.iwb_rst_i (wb_rst),
.iwb_ack_i (wb_s2m_or1k_i_ack),
.iwb_err_i (wb_s2m_or1k_i_err),
.iwb_rty_i (wb_s2m_or1k_i_rty),
.iwb_dat_i (wb_s2m_or1k_i_dat),
.iwb_cyc_o (wb_m2s_or1k_i_cyc),
.iwb_adr_o (wb_m2s_or1k_i_adr),
.iwb_stb_o (wb_m2s_or1k_i_stb),
.iwb_we_o (wb_m2s_or1k_i_we),
.iwb_sel_o (wb_m2s_or1k_i_sel),
.iwb_dat_o (wb_m2s_or1k_i_dat),
.iwb_cti_o (wb_m2s_or1k_i_cti),
.iwb_bte_o (wb_m2s_or1k_i_bte),
// Data bus, clocks, reset
.dwb_clk_i (wb_clk),
.dwb_rst_i (wb_rst),
.dwb_ack_i (wb_s2m_or1k_d_ack),
.dwb_err_i (wb_s2m_or1k_d_err),
.dwb_rty_i (wb_s2m_or1k_d_rty),
.dwb_dat_i (wb_s2m_or1k_d_dat),
.dwb_cyc_o (wb_m2s_or1k_d_cyc),
.dwb_adr_o (wb_m2s_or1k_d_adr),
.dwb_stb_o (wb_m2s_or1k_d_stb),
.dwb_we_o (wb_m2s_or1k_d_we),
.dwb_sel_o (wb_m2s_or1k_d_sel),
.dwb_dat_o (wb_m2s_or1k_d_dat),
.dwb_cti_o (wb_m2s_or1k_d_cti),
.dwb_bte_o (wb_m2s_or1k_d_bte),
// Debug interface ports
.dbg_stall_i (or1k_dbg_stall_i),
.dbg_ewt_i (1'b0),
.dbg_lss_o (or1k_dbg_lss_o),
.dbg_is_o (or1k_dbg_is_o),
.dbg_wp_o (or1k_dbg_wp_o),
.dbg_bp_o (or1k_dbg_bp_o),
.dbg_adr_i (or1k_dbg_adr_i),
.dbg_we_i (or1k_dbg_we_i),
.dbg_stb_i (or1k_dbg_stb_i),
.dbg_dat_i (or1k_dbg_dat_i),
.dbg_dat_o (or1k_dbg_dat_o),
.dbg_ack_o (or1k_dbg_ack_o),
.pm_clksd_o (),
.pm_dc_gate_o (),
.pm_ic_gate_o (),
.pm_dmmu_gate_o (),
.pm_immu_gate_o (),
.pm_tt_gate_o (),
.pm_cpu_gate_o (),
.pm_wakeup_o (),
.pm_lvolt_o (),
// Core clocks, resets
.clk_i (wb_clk),
.rst_i (or1k_rst),
.clmode_i (2'b00),
// Interrupts
.pic_ints_i (or1k_irq[30:0]),
.sig_tick (sig_tick),
.pm_cpustall_i (1'b0)
);
`else
mor1kx #(
.FEATURE_DEBUGUNIT ("ENABLED"),
.FEATURE_CMOV ("ENABLED"),
.FEATURE_INSTRUCTIONCACHE ("ENABLED"),
.OPTION_ICACHE_BLOCK_WIDTH (5),
.OPTION_ICACHE_SET_WIDTH (3),
.OPTION_ICACHE_WAYS (2),
.OPTION_ICACHE_LIMIT_WIDTH (32),
.FEATURE_IMMU ("ENABLED"),
.FEATURE_DATACACHE ("ENABLED"),
.OPTION_DCACHE_BLOCK_WIDTH (5),
.OPTION_DCACHE_SET_WIDTH (3),
.OPTION_DCACHE_WAYS (2),
.OPTION_DCACHE_LIMIT_WIDTH (31),
.FEATURE_DMMU ("ENABLED"),
.OPTION_PIC_TRIGGER ("LATCHED_LEVEL"),
.IBUS_WB_TYPE ("B3_REGISTERED_FEEDBACK"),
.DBUS_WB_TYPE ("B3_REGISTERED_FEEDBACK"),
.OPTION_CPU0 ("CAPPUCCINO"),
.OPTION_RESET_PC (32'hf0000100)
) mor1kx0 (
.iwbm_adr_o (wb_m2s_or1k_i_adr),
.iwbm_stb_o (wb_m2s_or1k_i_stb),
.iwbm_cyc_o (wb_m2s_or1k_i_cyc),
.iwbm_sel_o (wb_m2s_or1k_i_sel),
.iwbm_we_o (wb_m2s_or1k_i_we),
.iwbm_cti_o (wb_m2s_or1k_i_cti),
.iwbm_bte_o (wb_m2s_or1k_i_bte),
.iwbm_dat_o (wb_m2s_or1k_i_dat),
.dwbm_adr_o (wb_m2s_or1k_d_adr),
.dwbm_stb_o (wb_m2s_or1k_d_stb),
.dwbm_cyc_o (wb_m2s_or1k_d_cyc),
.dwbm_sel_o (wb_m2s_or1k_d_sel),
.dwbm_we_o (wb_m2s_or1k_d_we ),
.dwbm_cti_o (wb_m2s_or1k_d_cti),
.dwbm_bte_o (wb_m2s_or1k_d_bte),
.dwbm_dat_o (wb_m2s_or1k_d_dat),
.clk (wb_clk),
.rst (or1k_rst),
.iwbm_err_i (wb_s2m_or1k_i_err),
.iwbm_ack_i (wb_s2m_or1k_i_ack),
.iwbm_dat_i (wb_s2m_or1k_i_dat),
.iwbm_rty_i (wb_s2m_or1k_i_rty),
.dwbm_err_i (wb_s2m_or1k_d_err),
.dwbm_ack_i (wb_s2m_or1k_d_ack),
.dwbm_dat_i (wb_s2m_or1k_d_dat),
.dwbm_rty_i (wb_s2m_or1k_d_rty),
.irq_i (or1k_irq),
.du_addr_i (or1k_dbg_adr_i[15:0]),
.du_stb_i (or1k_dbg_stb_i),
.du_dat_i (or1k_dbg_dat_i),
.du_we_i (or1k_dbg_we_i),
.du_dat_o (or1k_dbg_dat_o),
.du_ack_o (or1k_dbg_ack_o),
.du_stall_i (or1k_dbg_stall_i),
.du_stall_o (or1k_dbg_bp_o)
);
`endif
////////////////////////////////////////////////////////////////////////
//
// Debug Interface
//
////////////////////////////////////////////////////////////////////////
adbg_top dbg_if0 (
// OR1K interface
.cpu0_clk_i (wb_clk),
.cpu0_rst_o (or1k_dbg_rst),
.cpu0_addr_o (or1k_dbg_adr_i),
.cpu0_data_o (or1k_dbg_dat_i),
.cpu0_stb_o (or1k_dbg_stb_i),
.cpu0_we_o (or1k_dbg_we_i),
.cpu0_data_i (or1k_dbg_dat_o),
.cpu0_ack_i (or1k_dbg_ack_o),
.cpu0_stall_o (or1k_dbg_stall_i),
.cpu0_bp_i (or1k_dbg_bp_o),
// TAP interface
.tck_i (dbg_tck),
.tdi_i (jtag_tap_tdo),
.tdo_o (dbg_if_tdo),
.rst_i (wb_rst),
.capture_dr_i (jtag_tap_capture_dr),
.shift_dr_i (jtag_tap_shift_dr),
.pause_dr_i (jtag_tap_pause_dr),
.update_dr_i (jtag_tap_update_dr),
.debug_select_i (dbg_if_select),
// Wishbone debug master
.wb_clk_i (wb_clk),
.wb_dat_i (wb_s2m_dbg_dat),
.wb_ack_i (wb_s2m_dbg_ack),
.wb_err_i (wb_s2m_dbg_err),
.wb_adr_o (wb_m2s_dbg_adr),
.wb_dat_o (wb_m2s_dbg_dat),
.wb_cyc_o (wb_m2s_dbg_cyc),
.wb_stb_o (wb_m2s_dbg_stb),
.wb_sel_o (wb_m2s_dbg_sel),
.wb_we_o (wb_m2s_dbg_we),
.wb_cti_o (wb_m2s_dbg_cti),
.wb_bte_o (wb_m2s_dbg_bte)
);
////////////////////////////////////////////////////////////////////////
//
// ROM
//
////////////////////////////////////////////////////////////////////////
assign wb_s2m_rom0_err = 1'b0;
assign wb_s2m_rom0_rty = 1'b0;
`ifdef BOOTROM
rom #(.ADDR_WIDTH(rom0_aw))
rom0 (
.wb_clk (wb_clk),
.wb_rst (wb_rst),
.wb_adr_i (wb_m2s_rom0_adr[(rom0_aw + 2) - 1 : 2]),
.wb_cyc_i (wb_m2s_rom0_cyc),
.wb_stb_i (wb_m2s_rom0_stb),
.wb_cti_i (wb_m2s_rom0_cti),
.wb_bte_i (wb_m2s_rom0_bte),
.wb_dat_o (wb_s2m_rom0_dat),
.wb_ack_o (wb_s2m_rom0_ack)
);
`else
assign wb_s2m_rom0_dat_o = 0;
assign wb_s2m_rom0_ack_o = 0;
`endif
////////////////////////////////////////////////////////////////////////
//
// SDRAM Memory Controller
//
////////////////////////////////////////////////////////////////////////
wire [15:0] sdram_dq_i;
wire [15:0] sdram_dq_o;
wire sdram_dq_oe;
assign sdram_dq_i = sdram_dq_pad_io;
assign sdram_dq_pad_io = sdram_dq_oe ? sdram_dq_o : 16'bz;
assign sdram_clk_pad_o = sdram_clk;
assign wb_s2m_sdram_ibus_err = 0;
assign wb_s2m_sdram_ibus_rty = 0;
assign wb_s2m_sdram_dbus_err = 0;
assign wb_s2m_sdram_dbus_rty = 0;
wb_sdram_ctrl #(
`ifdef ICARUS_SIM
.TECHNOLOGY ("GENERIC"),
`else
.TECHNOLOGY ("ALTERA"),
`endif
.CLK_FREQ_MHZ (100), // sdram_clk freq in MHZ
`ifdef SIM
.POWERUP_DELAY (1), // power up delay in us
`endif
.WB_PORTS (2), // Number of wishbone ports
.BUF_WIDTH (3),
.BURST_LENGTH (8),
.ROW_WIDTH (12), // Row width
.COL_WIDTH (8), // Column width
.BA_WIDTH (2), // Ba width
.tCAC (3), // CAS Latency
.tRAC (5), // RAS Latency
.tRP (3), // Command Period (PRE to ACT)
.tRC (7), // Command Period (REF to REF / ACT to ACT)
.tMRD (2) // Mode Register Set To Command Delay time
)
wb_sdram_ctrl0 (
// External SDRAM interface
.ba_pad_o (sdram_ba_pad_o[1:0]),
.a_pad_o (sdram_a_pad_o[11:0]),
.cs_n_pad_o (sdram_cs_n_pad_o),
.ras_pad_o (sdram_ras_pad_o),
.cas_pad_o (sdram_cas_pad_o),
.we_pad_o (sdram_we_pad_o),
.dq_i (sdram_dq_i[15:0]),
.dq_o (sdram_dq_o[15:0]),
.dqm_pad_o (sdram_dqm_pad_o[1:0]),
.dq_oe (sdram_dq_oe),
.cke_pad_o (sdram_cke_pad_o),
.sdram_clk (sdram_clk),
.sdram_rst (sdram_rst),
.wb_clk (wb_clk),
.wb_rst (wb_rst),
.wb_adr_i ({wb_m2s_sdram_ibus_adr, wb_m2s_sdram_dbus_adr}),
.wb_stb_i ({wb_m2s_sdram_ibus_stb, wb_m2s_sdram_dbus_stb}),
.wb_cyc_i ({wb_m2s_sdram_ibus_cyc, wb_m2s_sdram_dbus_cyc}),
.wb_cti_i ({wb_m2s_sdram_ibus_cti, wb_m2s_sdram_dbus_cti}),
.wb_bte_i ({wb_m2s_sdram_ibus_bte, wb_m2s_sdram_dbus_bte}),
.wb_we_i ({wb_m2s_sdram_ibus_we, wb_m2s_sdram_dbus_we }),
.wb_sel_i ({wb_m2s_sdram_ibus_sel, wb_m2s_sdram_dbus_sel}),
.wb_dat_i ({wb_m2s_sdram_ibus_dat, wb_m2s_sdram_dbus_dat}),
.wb_dat_o ({wb_s2m_sdram_ibus_dat, wb_s2m_sdram_dbus_dat}),
.wb_ack_o ({wb_s2m_sdram_ibus_ack, wb_s2m_sdram_dbus_ack})
);
////////////////////////////////////////////////////////////////////////
//
// UART0
//
////////////////////////////////////////////////////////////////////////
wire uart0_irq;
assign wb_s2m_uart0_err = 0;
assign wb_s2m_uart0_rty = 0;
uart_top uart16550_0 (
// Wishbone slave interface
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.wb_adr_i (wb_m2s_uart0_adr[uart0_aw-1:0]),
.wb_dat_i (wb_m2s_uart0_dat),
.wb_we_i (wb_m2s_uart0_we),
.wb_stb_i (wb_m2s_uart0_stb),
.wb_cyc_i (wb_m2s_uart0_cyc),
.wb_sel_i (4'b0), // Not used in 8-bit mode
.wb_dat_o (wb_s2m_uart0_dat),
.wb_ack_o (wb_s2m_uart0_ack),
// Outputs
.int_o (uart0_irq),
.stx_pad_o (uart0_stx_pad_o),
.rts_pad_o (),
.dtr_pad_o (),
// Inputs
.srx_pad_i (uart0_srx_pad_i),
.cts_pad_i (1'b0),
.dsr_pad_i (1'b0),
.ri_pad_i (1'b0),
.dcd_pad_i (1'b0)
);
////////////////////////////////////////////////////////////////////////
//
// GPIO 0
//
////////////////////////////////////////////////////////////////////////
wire [7:0] gpio0_in;
wire [7:0] gpio0_out;
wire [7:0] gpio0_dir;
// Tristate logic for IO
// 0 = input, 1 = output
genvar i;
generate
for (i = 0; i < 8; i = i+1) begin: gpio0_tris
assign gpio0_io[i] = gpio0_dir[i] ? gpio0_out[i] : 1'bz;
assign gpio0_in[i] = gpio0_dir[i] ? gpio0_out[i] : gpio0_io[i];
end
endgenerate
gpio gpio0 (
// GPIO bus
.gpio_i (gpio0_in),
.gpio_o (gpio0_out),
.gpio_dir_o (gpio0_dir),
// Wishbone slave interface
.wb_adr_i (wb_m2s_gpio0_adr[0]),
.wb_dat_i (wb_m2s_gpio0_dat),
.wb_we_i (wb_m2s_gpio0_we),
.wb_cyc_i (wb_m2s_gpio0_cyc),
.wb_stb_i (wb_m2s_gpio0_stb),
.wb_cti_i (wb_m2s_gpio0_cti),
.wb_bte_i (wb_m2s_gpio0_bte),
.wb_dat_o (wb_s2m_gpio0_dat),
.wb_ack_o (wb_s2m_gpio0_ack),
.wb_err_o (wb_s2m_gpio0_err),
.wb_rty_o (wb_s2m_gpio0_rty),
.wb_clk (wb_clk),
.wb_rst (wb_rst)
);
gpio key0 (
// Key bus
.gpio_i ({4'h0, key_pad_i}),
.gpio_o (),
.gpio_dir_o (),
// Wishbone slave interface
.wb_adr_i (wb_m2s_key_adr[0]),
.wb_dat_i (wb_m2s_key_dat),
.wb_we_i (wb_m2s_key_we),
.wb_cyc_i (wb_m2s_key_cyc),
.wb_stb_i (wb_m2s_key_stb),
.wb_cti_i (wb_m2s_key_cti),
.wb_bte_i (wb_m2s_key_bte),
.wb_dat_o (wb_s2m_key_dat),
.wb_ack_o (wb_s2m_key_ack),
.wb_err_o (wb_s2m_key_err),
.wb_rty_o (wb_s2m_key_rty),
.wb_clk (wb_clk),
.wb_rst (wb_rst)
);
gpio ledr0 (
// LED R bus 0
.gpio_i (),
.gpio_o (led_r_pad_o[7:0]),
.gpio_dir_o (),
// Wishbone slave interface
.wb_adr_i (wb_m2s_ledr0_adr[0]),
.wb_dat_i (wb_m2s_ledr0_dat),
.wb_we_i (wb_m2s_ledr0_we),
.wb_cyc_i (wb_m2s_ledr0_cyc),
.wb_stb_i (wb_m2s_ledr0_stb),
.wb_cti_i (wb_m2s_ledr0_cti),
.wb_bte_i (wb_m2s_ledr0_bte),
.wb_dat_o (wb_s2m_ledr0_dat),
.wb_ack_o (wb_s2m_ledr0_ack),
.wb_err_o (wb_s2m_ledr0_err),
.wb_rty_o (wb_s2m_ledr0_rty),
.wb_clk (wb_clk),
.wb_rst (wb_rst)
);
gpio ledr1 (
// LED R bus 1
.gpio_i (),
.gpio_o (led_r_pad_o[15:8]),
.gpio_dir_o (),
// Wishbone slave interface
.wb_adr_i (wb_m2s_ledr1_adr[0]),
.wb_dat_i (wb_m2s_ledr1_dat),
.wb_we_i (wb_m2s_ledr1_we),
.wb_cyc_i (wb_m2s_ledr1_cyc),
.wb_stb_i (wb_m2s_ledr1_stb),
.wb_cti_i (wb_m2s_ledr1_cti),
.wb_bte_i (wb_m2s_ledr1_bte),
.wb_dat_o (wb_s2m_ledr1_dat),
.wb_ack_o (wb_s2m_ledr1_ack),
.wb_err_o (wb_s2m_ledr1_err),
.wb_rty_o (wb_s2m_ledr1_rty),
.wb_clk (wb_clk),
.wb_rst (wb_rst)
);
gpio ledg0 (
// GPIO bus
.gpio_i (),
.gpio_o (led_g_pad_o),
.gpio_dir_o (),
// Wishbone slave interface
.wb_adr_i (wb_m2s_ledg0_adr[0]),
.wb_dat_i (wb_m2s_ledg0_dat),
.wb_we_i (wb_m2s_ledg0_we),
.wb_cyc_i (wb_m2s_ledg0_cyc),
.wb_stb_i (wb_m2s_ledg0_stb),
.wb_cti_i (wb_m2s_ledg0_cti),
.wb_bte_i (wb_m2s_ledg0_bte),
.wb_dat_o (wb_s2m_ledg0_dat),
.wb_ack_o (wb_s2m_ledg0_ack),
.wb_err_o (wb_s2m_ledg0_err),
.wb_rty_o (wb_s2m_ledg0_rty),
.wb_clk (wb_clk),
.wb_rst (wb_rst)
);
gpio switch0 (
// GPIO bus
.gpio_i (switch_pad_i[7:0]),
.gpio_o (),
.gpio_dir_o (),
// Wishbone slave interface
.wb_adr_i (wb_m2s_switch0_adr[0]),
.wb_dat_i (wb_m2s_switch0_dat),
.wb_we_i (wb_m2s_switch0_we),
.wb_cyc_i (wb_m2s_switch0_cyc),
.wb_stb_i (wb_m2s_switch0_stb),
.wb_cti_i (wb_m2s_switch0_cti),
.wb_bte_i (wb_m2s_switch0_bte),
.wb_dat_o (wb_s2m_switch0_dat),
.wb_ack_o (wb_s2m_switch0_ack),
.wb_err_o (wb_s2m_switch0_err),
.wb_rty_o (wb_s2m_switch0_rty),
.wb_clk (wb_clk),
.wb_rst (wb_rst)
);
gpio switch1 (
// GPIO bus
.gpio_i (switch_pad_i[15:8]),
.gpio_o (),
.gpio_dir_o (),
// Wishbone slave interface
.wb_adr_i (wb_m2s_switch1_adr[0]),
.wb_dat_i (wb_m2s_switch1_dat),
.wb_we_i (wb_m2s_switch1_we),
.wb_cyc_i (wb_m2s_switch1_cyc),
.wb_stb_i (wb_m2s_switch1_stb),
.wb_cti_i (wb_m2s_switch1_cti),
.wb_bte_i (wb_m2s_switch1_bte),
.wb_dat_o (wb_s2m_switch1_dat),
.wb_ack_o (wb_s2m_switch1_ack),
.wb_err_o (wb_s2m_switch1_err),
.wb_rty_o (wb_s2m_switch1_rty),
.wb_clk (wb_clk),
.wb_rst (wb_rst)
);
gpio switch2 (
// GPIO bus
.gpio_i ({6'h0, switch_pad_i[17:16]}),
.gpio_o (),
.gpio_dir_o (),
// Wishbone slave interface
.wb_adr_i (wb_m2s_switch2_adr[0]),
.wb_dat_i (wb_m2s_switch2_dat),
.wb_we_i (wb_m2s_switch2_we),
.wb_cyc_i (wb_m2s_switch2_cyc),
.wb_stb_i (wb_m2s_switch2_stb),
.wb_cti_i (wb_m2s_switch2_cti),
.wb_bte_i (wb_m2s_switch2_bte),
.wb_dat_o (wb_s2m_switch2_dat),
.wb_ack_o (wb_s2m_switch2_ack),
.wb_err_o (wb_s2m_switch2_err),
.wb_rty_o (wb_s2m_switch2_rty),
.wb_clk (wb_clk),
.wb_rst (wb_rst)
);
////////////////////////////////////////////////////////////////////////
//
// Interrupt assignment
//
////////////////////////////////////////////////////////////////////////
assign or1k_irq[0] = 0; // Non-maskable inside OR1K
assign or1k_irq[1] = 0; // Non-maskable inside OR1K
assign or1k_irq[2] = uart0_irq;
assign or1k_irq[3] = 0;
assign or1k_irq[4] = 0;
assign or1k_irq[5] = 0;
assign or1k_irq[6] = 0;
assign or1k_irq[7] = 0;
assign or1k_irq[8] = 0;
assign or1k_irq[9] = 0;
assign or1k_irq[10] = 0;
assign or1k_irq[11] = 0;
assign or1k_irq[12] = 0;
assign or1k_irq[13] = 0;
assign or1k_irq[14] = 0;
assign or1k_irq[15] = 0;
assign or1k_irq[16] = 0;
assign or1k_irq[17] = 0;
assign or1k_irq[18] = 0;
assign or1k_irq[19] = 0;
assign or1k_irq[20] = 0;
assign or1k_irq[21] = 0;
assign or1k_irq[22] = 0;
assign or1k_irq[23] = 0;
assign or1k_irq[24] = 0;
assign or1k_irq[25] = 0;
assign or1k_irq[26] = 0;
assign or1k_irq[27] = 0;
assign or1k_irq[28] = 0;
assign or1k_irq[29] = 0;
assign or1k_irq[30] = 0;
assign or1k_irq[31] = 0;
endmodule
|
module openmips (
input wire rst,
input wire clk,
input wire[`RegBus] rom_data_i,
input wire[`RegBus] ram_data_i,
input wire[5:0] int_i,
output wire[`RegBus] rom_addr_o,
output wire rom_ce_o,
output wire[`RegBus] ram_addr_o,
output wire[`RegBus] ram_data_o,
output wire[3:0] ram_sel_o,
output wire ram_we_o,
output wire ram_ce_o,
output wire timer_int_o
);
// PC 与 rom_addr_o 的连接
wire[`InstAddrBus] pc;
// 连接 IF/ID 模块与译码阶段 ID 模块的变量
wire[`InstAddrBus] id_pc_i;
wire[`InstBus] id_inst_i;
wire id_current_inst_loaded;
// 连接译码阶段的 ID 模块输出与 ID/EX 模块的连接
wire[`AluOpBus] id_aluop_o;
wire[`AluSelBus] id_alusel_o;
wire[`RegBus] id_reg1_o;
wire[`RegBus] id_reg2_o;
wire[`RegAddrBus] id_waddr_o;
wire id_we_o;
wire next_inst_in_delayslot_o;
wire[`RegBus] link_addr_o;
wire is_in_delayslot_o;
wire[`RegBus] id_inst_o;
wire[`RegBus] id_excepttype_o;
wire[`RegBus] id_current_inst_address_o;
wire id_current_inst_loaded_o;
// ID 到 PC
wire branch_flag_o;
wire[`RegBus] branch_target_address_o;
// 连接 ID/EX 模块输出与执行阶段 EX 模块的输入的变量
wire[`AluOpBus] ex_aluop_i;
wire[`AluSelBus] ex_alusel_i;
wire[`RegBus] ex_reg1_i;
wire[`RegBus] ex_reg2_i;
wire[`RegAddrBus] ex_waddr_i;
wire ex_we_i;
wire[`RegBus] ex_link_address;
wire ex_is_in_delayslot;
wire is_delayslot_o;
wire[`RegBus] ex_inst_i;
wire[`RegBus] ex_excepttype_i;
wire[`RegBus] ex_current_inst_addr_i;
// 连接 EX 的输出与 EX/MEM 的输入
wire[`RegAddrBus] ex_waddr_o;
wire ex_we_o;
wire[`RegBus] ex_wdata_o;
wire ex_whilo_o;
wire[`RegBus] ex_hi_o;
wire[`RegBus] ex_lo_o;
wire[`DoubleRegBus] hilo_temp_ex_o;
wire[1:0] cnt_ex_o;
wire[`AluOpBus] ex_aluop_o;
wire[`RegBus] ex_mem_addr_o;
wire[`RegBus] ex_reg2_o;
wire[`RegBus] ex_cp0_reg_data_o;
wire[`RegAddrBus] ex_cp0_reg_waddr_o;
wire ex_cp0_reg_we_o;
wire[`RegBus] ex_excepttype_o;
wire[`RegBus] ex_current_inst_addr_o;
wire ex_current_inst_loaded_o;
wire ex_is_in_delayslot_o;
// 连接 EX 的输出与 DIV 的输入
wire signed_div_o;
wire[`RegBus] div_opdata1_o; // 被除数
wire[`RegBus] div_opdata2_o; // 除数
wire div_start_o;
// 连接 EX 的输出与 CP0 的输入
wire[`RegAddrBus] ex_cp0_reg_raddr_o;
// 连接 EX/MEM 的输出与 EX 的输入
wire[`DoubleRegBus] hilo_temp_ex_mem_o;
wire[1:0] cnt_ex_mem_o;
// 连接 EX/MEM 的输出与 MEM 的输入
wire mem_rst;
wire[`RegAddrBus] mem_waddr_i;
wire mem_we_i;
wire[`RegBus] mem_wdata_i;
wire mem_whilo_i;
wire[`RegBus] mem_hi_i;
wire[`RegBus] mem_lo_i;
wire[`AluOpBus] mem_aluop_i;
wire[`RegBus] mem_mem_addr_i;
wire[`RegBus] mem_reg2_i;
wire[`RegBus] mem_cp0_reg_data_i;
wire[`RegAddrBus] mem_cp0_reg_waddr_i;
wire mem_cp0_reg_we_i;
wire[`RegBus] mem_excepttype_i;
wire[`RegBus] mem_current_inst_addr_i;
wire mem_current_inst_loaded_i;
wire mem_is_in_delayslot_i;
// 连接 MEM 的输出和 MEM/WB 的输入
wire[`RegAddrBus] mem_waddr_o;
wire mem_we_o;
wire[`RegBus] mem_wdata_o;
wire mem_whilo_o;
wire[`RegBus] mem_hi_o;
wire[`RegBus] mem_lo_o;
wire mem_LLbit_we_o;
wire mem_LLbit_value_o;
wire[`RegBus] mem_cp0_reg_data_o;
wire[`RegAddrBus] mem_cp0_reg_waddr_o;
wire mem_cp0_reg_we_o;
// 链接 MEM 的输出和 CP0、CTRL 的输入
wire[`RegBus] mem_cp0_epc_o;
wire[`RegBus] mem_excepttype_o;
wire[`RegBus] mem_current_inst_address_o;
wire mem_current_inst_loaded_o;
wire mem_is_in_delayslot_o;
// 连接 MEM/WB 的输出与回写阶段的输入
wire wb_we_i;
wire[`RegAddrBus] wb_waddr_i;
wire[`RegBus] wb_wdata_i;
wire wb_LLbit_we_i;
wire wb_LLbit_value_i;
// 连接 MEM/WB 的输出与 hilo_reg 的输入
wire hilo_whilo_i;
wire[`RegBus] hilo_hi_i;
wire[`RegBus] hilo_lo_i;
// 连接 MEM/WB 的输出与 CP0 EX 的输入
wire[`RegBus] wb_cp0_reg_data_o;
wire[`RegAddrBus] wb_cp0_reg_waddr_o;
wire wb_cp0_reg_we_o;
// 连接 hilo_reg 的输出与 EX 的输入
wire[`RegBus] hilo_hi_o;
wire[`RegBus] hilo_lo_o;
// 连接 ID 与 Regfile 的连接
wire reg_re1;
wire[`RegAddrBus] reg_raddr1;
wire[`RegBus] reg_rdata1;
wire reg_re2;
wire[`RegAddrBus] reg_raddr2;
wire[`RegBus] reg_rdata2;
// 连接 CTRL 和其他模块
wire[5:0] stall;
wire stallreq_from_id;
wire stallreq_from_ex;
wire[`RegBus] new_pc;
wire flush;
// 连接 DIV 和 EX 模块
wire[`DoubleRegBus] div_result_o;
wire div_result_ready_o;
// 连接 LLbit 模块和 MEM 模块
wire LLbit_o;
// 连接 CP0 模块和 EX 模块
wire[`RegBus] ex_cp0_reg_data_i;
// 连接 CP0 和 MEM
wire[`RegBus] cp0_status_o;
wire[`RegBus] cp0_cause_o;
wire[`RegBus] cp0_epc_o;
// pc_reg 模块例化
pc_reg pc_reg0 (
.clk(clk),
.rst(rst),
.stall(stall),
.branch_flag_i(branch_flag_o),
.branch_target_address_i(branch_target_address_o),
.new_pc(new_pc),
.flush(flush),
.pc(pc),
.ce(rom_ce_o)
);
assign rom_addr_o = pc;
// IF/ID 模块例化
if_id if_id0 (
.clk(clk),
.rst(rst),
.stall(stall),
.flush(flush),
.if_pc(pc),
.if_inst(rom_data_i),
.id_pc(id_pc_i),
.id_inst(id_inst_i),
.id_current_inst_loaded(id_current_inst_loaded)
);
// ID 模块例化
id id0 (
.rst(rst),
.pc_i(id_pc_i),
.inst_i(id_inst_i),
.current_inst_loaded_i(id_current_inst_loaded),
// 来自 regfile 的输入
.reg1_data_i(reg_rdata1),
.reg2_data_i(reg_rdata2),
// 来自 EX 的输入
.ex_waddr_i(ex_waddr_o),
.ex_we_i(ex_we_o),
.ex_wdata_i(ex_wdata_o),
.is_in_delayslot_i(is_delayslot_o),
.ex_aluop_i(ex_aluop_o),
// 来自 MEM 的输入
.mem_waddr_i(mem_waddr_o),
.mem_we_i(mem_we_o),
.mem_wdata_i(mem_wdata_o),
// 输出给 regfile
.reg1_re_o(reg_re1),
.reg2_re_o(reg_re2),
.reg1_addr_o(reg_raddr1),
.reg2_addr_o(reg_raddr2),
// 输出给 ID/EX 模块
.aluop_o(id_aluop_o),
.alusel_o(id_alusel_o),
.reg1_o(id_reg1_o),
.reg2_o(id_reg2_o),
.we_o(id_we_o),
.waddr_o(id_waddr_o),
.next_inst_in_delayslot_o(next_inst_in_delayslot_o),
.link_addr_o(link_addr_o),
.is_in_delayslot_o(is_in_delayslot_o),
.inst_o(id_inst_o),
.excepttype_o(id_excepttype_o),
.current_inst_address_o(id_current_inst_address_o),
.current_inst_loaded_o(id_current_inst_loaded_o),
// 输出给 PC
.branch_flag_o(branch_flag_o),
.branch_target_address_o(branch_target_address_o),
// 输出给 CTRL
.stallreq(stallreq_from_id)
);
// Regfile 模块例化
regfile regfile0 (
.rst(rst),
.clk(clk),
// wb 写输入
.we(wb_we_i),
.waddr(wb_waddr_i),
.wdata(wb_wdata_i),
// id 读输入
.re1(reg_re1),
.re2(reg_re2),
.raddr1(reg_raddr1),
.raddr2(reg_raddr2),
// 输出给 id
.rdata1(reg_rdata1),
.rdata2(reg_rdata2)
);
// ID/EX 模块例化
id_ex id_ex0 (
.clk(clk),
.rst(rst),
.stall(stall),
.flush(flush),
.id_aluop(id_aluop_o),
.id_alusel(id_alusel_o),
.id_reg1(id_reg1_o),
.id_reg2(id_reg2_o),
.id_waddr(id_waddr_o),
.id_we(id_we_o),
.id_link_address(link_addr_o),
.id_is_in_delayslot(is_in_delayslot_o),
.next_inst_in_delayslot_i(next_inst_in_delayslot_o),
.id_inst(id_inst_o),
.id_excepttype(id_excepttype_o),
.id_current_inst_addr(id_current_inst_address_o),
.id_current_inst_loaded(id_current_inst_loaded_o),
.ex_aluop(ex_aluop_i),
.ex_alusel(ex_alusel_i),
.ex_reg1(ex_reg1_i),
.ex_reg2(ex_reg2_i),
.ex_waddr(ex_waddr_i),
.ex_we(ex_we_i),
.ex_link_address(ex_link_address),
.ex_is_in_delayslot(ex_is_in_delayslot),
.is_delayslot_o(is_delayslot_o),
.ex_inst(ex_inst_i),
.ex_excepttype(ex_excepttype_i),
.ex_current_inst_addr(ex_current_inst_addr_i),
.ex_current_inst_loaded(ex_current_inst_loaded_i)
);
// EX 模块例化
ex ex0 (
.rst(rst),
// 从 ID_EX 输入
.aluop_i(ex_aluop_i),
.alusel_i(ex_alusel_i),
.reg1_i(ex_reg1_i),
.reg2_i(ex_reg2_i),
.waddr_i(ex_waddr_i),
.we_i(ex_we_i),
.link_address_i(ex_link_address),
.is_in_delayslot_i(ex_is_in_delayslot),
.inst_i(ex_inst_i),
.aluop_o(ex_aluop_o),
.mem_addr_o(ex_mem_addr_o),
.reg2_o(ex_reg2_o),
.excepttype_i(ex_excepttype_i),
.current_inst_addr_i(ex_current_inst_addr_i),
.current_inst_loaded_i(ex_current_inst_loaded_i),
// 从 EX/MEM 输入
.hilo_temp_i(hilo_temp_ex_mem_o),
.cnt_i(cnt_ex_mem_o),
// 从 MEM 输入
.mem_whilo_i(mem_whilo_o),
.mem_hi_i(mem_hi_o),
.mem_lo_i(mem_lo_o),
.mem_cp0_reg_data(mem_cp0_reg_data_o),
.mem_cp0_reg_waddr(mem_cp0_reg_waddr_o),
.mem_cp0_reg_we(mem_cp0_reg_we_o),
// 从 MEM/WB 输入
.wb_whilo_i(hilo_whilo_i),
.wb_hi_i(hilo_hi_i),
.wb_lo_i(hilo_lo_i),
.wb_cp0_reg_data(wb_cp0_reg_data_o),
.wb_cp0_reg_waddr(wb_cp0_reg_waddr_o),
.wb_cp0_reg_we(wb_cp0_reg_we_o),
// 从 hilo_reg 输入
.hi_i(hilo_hi_o),
.lo_i(hilo_lo_o),
// 从 DIV 输入
.div_result_i(div_result_o),
.div_result_ready_i(div_result_ready_o),
// 从 CP0 输入
.cp0_reg_data_i(ex_cp0_reg_data_i),
// 输出给 EX/MEM
.waddr_o(ex_waddr_o),
.we_o(ex_we_o),
.wdata_o(ex_wdata_o),
.whilo_o(ex_whilo_o),
.hi_o(ex_hi_o),
.lo_o(ex_lo_o),
.hilo_temp_o(hilo_temp_ex_o),
.cnt_o(cnt_ex_o),
.stallreq(stallreq_from_ex),
.cp0_reg_data_o(ex_cp0_reg_data_o),
.cp0_reg_waddr_o(ex_cp0_reg_waddr_o),
.cp0_reg_we_o(ex_cp0_reg_we_o),
.excepttype_o(ex_excepttype_o),
.current_inst_addr_o(ex_current_inst_addr_o),
.current_inst_loaded_o(ex_current_inst_loaded_o),
.is_in_delayslot_o(ex_is_in_delayslot_o),
// 输出给 DIV
.signed_div_o(signed_div_o),
.div_opdata1_o(div_opdata1_o), // 被除数
.div_opdata2_o(div_opdata2_o), // 除数
.div_start_o(div_start_o),
// 输出给 CP0
.cp0_reg_raddr_o(ex_cp0_reg_raddr_o)
);
// EX/MEM 模块例化
ex_mem ex_mem0 (
.rst(rst),
.clk(clk),
.stall(stall),
.flush(flush),
.ex_waddr(ex_waddr_o),
.ex_we(ex_we_o),
.ex_wdata(ex_wdata_o),
.ex_whilo(ex_whilo_o),
.ex_hi(ex_hi_o),
.ex_lo(ex_lo_o),
.hilo_i(hilo_temp_ex_o),
.cnt_i(cnt_ex_o),
.ex_aluop(ex_aluop_o),
.ex_mem_addr(ex_mem_addr_o),
.ex_reg2(ex_reg2_o),
.ex_cp0_reg_data(ex_cp0_reg_data_o),
.ex_cp0_reg_waddr(ex_cp0_reg_waddr_o),
.ex_cp0_reg_we(ex_cp0_reg_we_o),
.ex_excepttype(ex_excepttype_o),
.ex_current_inst_addr(ex_current_inst_addr_o),
.ex_current_inst_loaded(ex_current_inst_loaded_o),
.ex_is_in_delayslot(ex_is_in_delayslot_o),
.mem_waddr(mem_waddr_i),
.mem_we(mem_we_i),
.mem_wdata(mem_wdata_i),
.mem_whilo(mem_whilo_i),
.mem_hi(mem_hi_i),
.mem_lo(mem_lo_i),
.hilo_o(hilo_temp_ex_mem_o),
.cnt_o(cnt_ex_mem_o),
.mem_aluop(mem_aluop_i),
.mem_mem_addr(mem_mem_addr_i),
.mem_reg2(mem_reg2_i),
.mem_cp0_reg_data(mem_cp0_reg_data_i),
.mem_cp0_reg_waddr(mem_cp0_reg_waddr_i),
.mem_cp0_reg_we(mem_cp0_reg_we_i),
.mem_excepttype(mem_excepttype_i),
.mem_current_inst_addr(mem_current_inst_addr_i),
.mem_current_inst_loaded(mem_current_inst_loaded_i),
.mem_is_in_delayslot(mem_is_in_delayslot_i)
);
// MEM 模块例化
mem mem0 (
.rst(rst),
// EX/MEM 的输入
.waddr_i(mem_waddr_i),
.we_i(mem_we_i),
.wdata_i(mem_wdata_i),
.whilo_i(mem_whilo_i),
.hi_i(mem_hi_i),
.lo_i(mem_lo_i),
.aluop_i(mem_aluop_i),
.mem_addr_i(mem_mem_addr_i),
.reg2_i(mem_reg2_i),
.cp0_reg_data_i(mem_cp0_reg_data_i),
.cp0_reg_waddr_i(mem_cp0_reg_waddr_i),
.cp0_reg_we_i(mem_cp0_reg_we_i),
.excepttype_i(mem_excepttype_i),
.current_inst_address_i(mem_current_inst_addr_i),
.current_inst_loaded_i(mem_current_inst_loaded_i),
.is_in_delayslot_i(mem_is_in_delayslot_i),
// RAM 的输入
.mem_data_i(ram_data_i),
.LLbit_i(LLbit_o),
// WB 的输入
.wb_LLbit_we_i(wb_LLbit_we_i),
.wb_LLbit_value_i(wb_LLbit_value_i),
.wb_cp0_reg_we(wb_cp0_reg_we_o),
.wb_cp0_reg_write_addr(wb_cp0_reg_waddr_o),
.wb_cp0_reg_write_data(wb_cp0_reg_data_o),
// CP0 的输入
.cp0_status_i(cp0_status_o),
.cp0_cause_i(cp0_cause_o),
.cp0_epc_i(cp0_epc_o),
// 输出给 MEM/WB
.waddr_o(mem_waddr_o),
.we_o(mem_we_o),
.wdata_o(mem_wdata_o),
.whilo_o(mem_whilo_o),
.hi_o(mem_hi_o),
.lo_o(mem_lo_o),
.mem_addr_o(ram_addr_o),
.mem_we_o(ram_we_o),
.mem_sel_o(ram_sel_o),
.mem_data_o(ram_data_o),
.mem_ce_o(ram_ce_o),
.LLbit_we_o(mem_LLbit_we_o),
.LLbit_value_o(mem_LLbit_value_o),
.cp0_reg_data_o(mem_cp0_reg_data_o),
.cp0_reg_waddr_o(mem_cp0_reg_waddr_o),
.cp0_reg_we_o(mem_cp0_reg_we_o),
.cp0_epc_o(mem_cp0_epc_o),
.excepttype_o(mem_excepttype_o),
.current_inst_address_o(mem_current_inst_address_o),
.current_inst_loaded_o(mem_current_inst_loaded_o),
.is_in_delayslot_o(mem_is_in_delayslot_o)
);
// MEM/WB 模块例化
mem_wb mem_wb0 (
.clk(clk),
.rst(rst),
.stall(stall),
.flush(flush),
// 从 MEM 输入
.mem_waddr(mem_waddr_o),
.mem_we(mem_we_o),
.mem_wdata(mem_wdata_o),
.mem_whilo(mem_whilo_o),
.mem_hi(mem_hi_o),
.mem_lo(mem_lo_o),
.mem_LLbit_we(mem_LLbit_we_o),
.mem_LLbit_value(mem_LLbit_value_o),
.mem_cp0_reg_data(mem_cp0_reg_data_o),
.mem_cp0_reg_waddr(mem_cp0_reg_waddr_o),
.mem_cp0_reg_we(mem_cp0_reg_we_o),
// 输出给 WB
.wb_waddr(wb_waddr_i),
.wb_we(wb_we_i),
.wb_wdata(wb_wdata_i),
.wb_LLbit_we(wb_LLbit_we_i),
.wb_LLbit_value(wb_LLbit_value_i),
// 输出给 hilo_reg
.wb_whilo(hilo_whilo_i),
.wb_hi(hilo_hi_i),
.wb_lo(hilo_lo_i),
// 输出给 CP0 EX
.wb_cp0_reg_data(wb_cp0_reg_data_o),
.wb_cp0_reg_waddr(wb_cp0_reg_waddr_o),
.wb_cp0_reg_we(wb_cp0_reg_we_o)
);
// hilo_reg 模块例化
hilo_reg hilo_reg0 (
.clk(clk),
.rst(rst),
// 从 MEM/WB 输入
.we(hilo_whilo_i),
.hi_i(hilo_hi_i),
.lo_i(hilo_lo_i),
// 输出给 EX
.hi_o(hilo_hi_o),
.lo_o(hilo_lo_o)
);
ctrl ctrl0 (
.rst(rst),
.stallreq_from_id(stallreq_from_id),
.stallreq_from_ex(stallreq_from_ex),
.cp0_epc_i(mem_cp0_epc_o),
.excepttype_i(mem_excepttype_o),
.stall(stall),
.new_pc(new_pc),
.flush(flush)
);
div div0 (
.clk(clk),
.rst(rst),
.signed_div_i(signed_div_o),
.opdata1_i(div_opdata1_o), // 被除数
.opdata2_i(div_opdata2_o), // 除数
.start_i(div_start_o),
.annul_i(1'b0),
.result_o(div_result_o),
.result_ready_o(div_result_ready_o)
);
LLbit_reg LLbit_reg0 (
.clk(clk),
.rst(rst),
.flush(flush),
.LLbit_i(wb_LLbit_value_i),
.we(wb_LLbit_we_i),
.LLbit_o(LLbit_o)
);
cp0_reg cp0_reg0 (
.clk(clk),
.rst(rst),
.raddr_i(ex_cp0_reg_raddr_o),
.data_i(wb_cp0_reg_data_o),
.waddr_i(wb_cp0_reg_waddr_o),
.we_i(wb_cp0_reg_we_o),
.int_i(int_i),
.excepttype_i(mem_excepttype_o),
.mem_current_inst_addr_i(mem_current_inst_address_o),
.mem_current_inst_loaded(mem_current_inst_loaded_o),
.mem_is_in_delayslot_i(mem_is_in_delayslot_o),
.ex_current_inst_addr_i(ex_current_inst_addr_o),
.ex_current_inst_loaded(ex_current_inst_loaded_o),
.ex_is_in_delayslot_i(ex_is_in_delayslot_o),
.id_current_inst_addr_i(id_current_inst_address_o),
.id_current_inst_loaded(id_current_inst_loaded_o),
.id_is_in_delayslot_i(is_in_delayslot_o),
.pc_current_inst_addr_i(pc),
.data_o(ex_cp0_reg_data_i),
.status_o(cp0_status_o),
.cause_o(cp0_cause_o),
.epc_o(cp0_epc_o),
.timer_int_o(timer_int_o)
);
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
IRQ_F2P,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *) output [1:0]USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) output USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) input USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) output M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) output M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) output M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) output M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) output M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) output M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) output [11:0]M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) output [11:0]M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) output [11:0]M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) output [1:0]M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) output [1:0]M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) output [2:0]M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) output [1:0]M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) output [1:0]M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) output [2:0]M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) output [2:0]M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) output [2:0]M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) output [31:0]M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) output [31:0]M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) output [31:0]M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) output [3:0]M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) output [3:0]M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) output [3:0]M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) output [3:0]M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output [3:0]M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output [3:0]M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output [3:0]M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0" *) input M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) input M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) input M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) input M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) input [11:0]M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 50000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input [31:0]M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH, PortWidth 1" *) input [0:0]IRQ_F2P;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0" *) output FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW" *) output FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *) inout [3:0]DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout PS_PORB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire FCLK_CLK0;
wire FCLK_RESET0_N;
wire [0:0]IRQ_F2P;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]M_AXI_GP0_ARCACHE;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [2:0]M_AXI_GP0_ARSIZE;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]M_AXI_GP0_AWCACHE;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [2:0]M_AXI_GP0_AWSIZE;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
wire NLW_inst_DMA0_RSTN_UNCONNECTED;
wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
wire NLW_inst_DMA1_RSTN_UNCONNECTED;
wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
wire NLW_inst_DMA2_RSTN_UNCONNECTED;
wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
wire NLW_inst_DMA3_RSTN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
wire NLW_inst_FCLK_CLK1_UNCONNECTED;
wire NLW_inst_FCLK_CLK2_UNCONNECTED;
wire NLW_inst_FCLK_CLK3_UNCONNECTED;
wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
wire NLW_inst_I2C0_SCL_O_UNCONNECTED;
wire NLW_inst_I2C0_SCL_T_UNCONNECTED;
wire NLW_inst_I2C0_SDA_O_UNCONNECTED;
wire NLW_inst_I2C0_SDA_T_UNCONNECTED;
wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
wire NLW_inst_PJTAG_TDO_UNCONNECTED;
wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO0_CLK_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO0_LED_UNCONNECTED;
wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO1_CLK_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO1_LED_UNCONNECTED;
wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_T_UNCONNECTED;
wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_T_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
wire NLW_inst_TRACE_CTL_UNCONNECTED;
wire NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_UART0_DTRN_UNCONNECTED;
wire NLW_inst_UART0_RTSN_UNCONNECTED;
wire NLW_inst_UART0_TX_UNCONNECTED;
wire NLW_inst_UART1_DTRN_UNCONNECTED;
wire NLW_inst_UART1_RTSN_UNCONNECTED;
wire NLW_inst_UART1_TX_UNCONNECTED;
wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_O_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_T_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
(* C_DM_WIDTH = "4" *)
(* C_DQS_WIDTH = "4" *)
(* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *)
(* C_EN_EMIO_ENET0 = "0" *)
(* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *)
(* C_EN_EMIO_TRACE = "0" *)
(* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *)
(* C_FCLK_CLK2_BUF = "FALSE" *)
(* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *)
(* C_GP1_EN_MODIFIABLE_TXN = "1" *)
(* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *)
(* C_IRQ_F2P_MODE = "DIRECT" *)
(* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP0_ID_WIDTH = "12" *)
(* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP1_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *)
(* C_PACKAGE_NAME = "clg400" *)
(* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *)
(* C_S_AXI_ACP_AWUSER_VAL = "31" *)
(* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *)
(* C_S_AXI_GP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *)
(* C_S_AXI_HP1_DATA_WIDTH = "64" *)
(* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *)
(* C_S_AXI_HP2_ID_WIDTH = "6" *)
(* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *)
(* C_TRACE_BUFFER_CLOCK_DELAY = "12" *)
(* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *)
(* C_TRACE_PIPELINE_WIDTH = "8" *)
(* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *)
(* C_USE_M_AXI_GP0 = "1" *)
(* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *)
(* C_USE_S_AXI_GP0 = "0" *)
(* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *)
(* C_USE_S_AXI_HP1 = "0" *)
(* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *)
(* HW_HANDOFF = "design_1_processing_system7_0_2.hwdef" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={667} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={32} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={50} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 inst
(.CAN0_PHY_RX(1'b0),
.CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
.CAN1_PHY_RX(1'b0),
.CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
.Core0_nFIQ(1'b0),
.Core0_nIRQ(1'b0),
.Core1_nFIQ(1'b0),
.Core1_nIRQ(1'b0),
.DDR_ARB({1'b0,1'b0,1'b0,1'b0}),
.DDR_Addr(DDR_Addr),
.DDR_BankAddr(DDR_BankAddr),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_CS_n(DDR_CS_n),
.DDR_Clk(DDR_Clk),
.DDR_Clk_n(DDR_Clk_n),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS(DDR_DQS),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_WEB(DDR_WEB),
.DMA0_ACLK(1'b0),
.DMA0_DAREADY(1'b0),
.DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
.DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
.DMA0_DRLAST(1'b0),
.DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
.DMA0_DRTYPE({1'b0,1'b0}),
.DMA0_DRVALID(1'b0),
.DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
.DMA1_ACLK(1'b0),
.DMA1_DAREADY(1'b0),
.DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
.DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
.DMA1_DRLAST(1'b0),
.DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
.DMA1_DRTYPE({1'b0,1'b0}),
.DMA1_DRVALID(1'b0),
.DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
.DMA2_ACLK(1'b0),
.DMA2_DAREADY(1'b0),
.DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
.DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
.DMA2_DRLAST(1'b0),
.DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
.DMA2_DRTYPE({1'b0,1'b0}),
.DMA2_DRVALID(1'b0),
.DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
.DMA3_ACLK(1'b0),
.DMA3_DAREADY(1'b0),
.DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
.DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
.DMA3_DRLAST(1'b0),
.DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
.DMA3_DRTYPE({1'b0,1'b0}),
.DMA3_DRVALID(1'b0),
.DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
.ENET0_EXT_INTIN(1'b0),
.ENET0_GMII_COL(1'b0),
.ENET0_GMII_CRS(1'b0),
.ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET0_GMII_RX_CLK(1'b0),
.ENET0_GMII_RX_DV(1'b0),
.ENET0_GMII_RX_ER(1'b0),
.ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
.ENET0_GMII_TX_CLK(1'b0),
.ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
.ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
.ENET0_MDIO_I(1'b0),
.ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
.ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
.ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
.ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
.ENET1_EXT_INTIN(1'b0),
.ENET1_GMII_COL(1'b0),
.ENET1_GMII_CRS(1'b0),
.ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET1_GMII_RX_CLK(1'b0),
.ENET1_GMII_RX_DV(1'b0),
.ENET1_GMII_RX_ER(1'b0),
.ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
.ENET1_GMII_TX_CLK(1'b0),
.ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
.ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
.ENET1_MDIO_I(1'b0),
.ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
.ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
.ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
.ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
.EVENT_EVENTI(1'b0),
.EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
.EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
.EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
.FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
.FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
.FCLK_CLKTRIG0_N(1'b0),
.FCLK_CLKTRIG1_N(1'b0),
.FCLK_CLKTRIG2_N(1'b0),
.FCLK_CLKTRIG3_N(1'b0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
.FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
.FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
.FPGA_IDLE_N(1'b0),
.FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_CLK(1'b0),
.FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_VALID(1'b0),
.FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
.FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
.FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
.FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
.FTMT_F2P_TRIG_0(1'b0),
.FTMT_F2P_TRIG_1(1'b0),
.FTMT_F2P_TRIG_2(1'b0),
.FTMT_F2P_TRIG_3(1'b0),
.FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
.FTMT_P2F_TRIGACK_0(1'b0),
.FTMT_P2F_TRIGACK_1(1'b0),
.FTMT_P2F_TRIGACK_2(1'b0),
.FTMT_P2F_TRIGACK_3(1'b0),
.FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
.FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
.FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
.FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
.GPIO_I({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]),
.GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]),
.I2C0_SCL_I(1'b0),
.I2C0_SCL_O(NLW_inst_I2C0_SCL_O_UNCONNECTED),
.I2C0_SCL_T(NLW_inst_I2C0_SCL_T_UNCONNECTED),
.I2C0_SDA_I(1'b0),
.I2C0_SDA_O(NLW_inst_I2C0_SDA_O_UNCONNECTED),
.I2C0_SDA_T(NLW_inst_I2C0_SDA_T_UNCONNECTED),
.I2C1_SCL_I(1'b0),
.I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
.I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
.I2C1_SDA_I(1'b0),
.I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
.I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
.IRQ_F2P(IRQ_F2P),
.IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
.IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
.IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
.IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
.IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
.IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
.IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
.IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
.IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
.IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
.IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
.IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
.IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
.IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
.IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
.IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
.IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
.IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
.IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
.IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
.IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
.IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
.IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
.IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
.IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
.IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
.IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
.IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
.IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
.MIO(MIO),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP1_ACLK(1'b0),
.M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
.M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
.M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_ARREADY(1'b0),
.M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
.M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
.M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_AWREADY(1'b0),
.M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
.M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
.M_AXI_GP1_BRESP({1'b0,1'b0}),
.M_AXI_GP1_BVALID(1'b0),
.M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RLAST(1'b0),
.M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
.M_AXI_GP1_RRESP({1'b0,1'b0}),
.M_AXI_GP1_RVALID(1'b0),
.M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
.M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
.M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
.M_AXI_GP1_WREADY(1'b0),
.M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
.M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
.PJTAG_TCK(1'b0),
.PJTAG_TDI(1'b0),
.PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
.PJTAG_TMS(1'b0),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB),
.PS_SRSTB(PS_SRSTB),
.SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
.SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
.SDIO0_CDN(1'b0),
.SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
.SDIO0_CLK_FB(1'b0),
.SDIO0_CMD_I(1'b0),
.SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
.SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
.SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
.SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
.SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
.SDIO0_WP(1'b0),
.SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
.SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
.SDIO1_CDN(1'b0),
.SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
.SDIO1_CLK_FB(1'b0),
.SDIO1_CMD_I(1'b0),
.SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
.SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
.SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
.SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
.SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
.SDIO1_WP(1'b0),
.SPI0_MISO_I(1'b0),
.SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
.SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
.SPI0_MOSI_I(1'b0),
.SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
.SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
.SPI0_SCLK_I(1'b0),
.SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
.SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
.SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
.SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
.SPI0_SS_I(1'b0),
.SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
.SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
.SPI1_MISO_I(1'b0),
.SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
.SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
.SPI1_MOSI_I(1'b0),
.SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
.SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
.SPI1_SCLK_I(1'b0),
.SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
.SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
.SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
.SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
.SPI1_SS_I(1'b0),
.SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
.SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
.SRAM_INTIN(1'b0),
.S_AXI_ACP_ACLK(1'b0),
.S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARBURST({1'b0,1'b0}),
.S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
.S_AXI_ACP_ARID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLOCK({1'b0,1'b0}),
.S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
.S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARVALID(1'b0),
.S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWBURST({1'b0,1'b0}),
.S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLOCK({1'b0,1'b0}),
.S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
.S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWVALID(1'b0),
.S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
.S_AXI_ACP_BREADY(1'b0),
.S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
.S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
.S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
.S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
.S_AXI_ACP_RREADY(1'b0),
.S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
.S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_WLAST(1'b0),
.S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
.S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WVALID(1'b0),
.S_AXI_GP0_ACLK(1'b0),
.S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARBURST({1'b0,1'b0}),
.S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
.S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLOCK({1'b0,1'b0}),
.S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
.S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARVALID(1'b0),
.S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWBURST({1'b0,1'b0}),
.S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLOCK({1'b0,1'b0}),
.S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
.S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWVALID(1'b0),
.S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
.S_AXI_GP0_BREADY(1'b0),
.S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
.S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
.S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
.S_AXI_GP0_RREADY(1'b0),
.S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
.S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WLAST(1'b0),
.S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
.S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WVALID(1'b0),
.S_AXI_GP1_ACLK(1'b0),
.S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARBURST({1'b0,1'b0}),
.S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
.S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLOCK({1'b0,1'b0}),
.S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
.S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARVALID(1'b0),
.S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWBURST({1'b0,1'b0}),
.S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLOCK({1'b0,1'b0}),
.S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
.S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWVALID(1'b0),
.S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
.S_AXI_GP1_BREADY(1'b0),
.S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
.S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
.S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
.S_AXI_GP1_RREADY(1'b0),
.S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
.S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WLAST(1'b0),
.S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
.S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WVALID(1'b0),
.S_AXI_HP0_ACLK(1'b0),
.S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARBURST({1'b0,1'b0}),
.S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
.S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLOCK({1'b0,1'b0}),
.S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
.S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARVALID(1'b0),
.S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWBURST({1'b0,1'b0}),
.S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLOCK({1'b0,1'b0}),
.S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
.S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWVALID(1'b0),
.S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
.S_AXI_HP0_BREADY(1'b0),
.S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
.S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP0_RDISSUECAP1_EN(1'b0),
.S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
.S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
.S_AXI_HP0_RREADY(1'b0),
.S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
.S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WLAST(1'b0),
.S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
.S_AXI_HP0_WRISSUECAP1_EN(1'b0),
.S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WVALID(1'b0),
.S_AXI_HP1_ACLK(1'b0),
.S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARBURST({1'b0,1'b0}),
.S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
.S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLOCK({1'b0,1'b0}),
.S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
.S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARVALID(1'b0),
.S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWBURST({1'b0,1'b0}),
.S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLOCK({1'b0,1'b0}),
.S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
.S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWVALID(1'b0),
.S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
.S_AXI_HP1_BREADY(1'b0),
.S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
.S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP1_RDISSUECAP1_EN(1'b0),
.S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
.S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
.S_AXI_HP1_RREADY(1'b0),
.S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
.S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WLAST(1'b0),
.S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
.S_AXI_HP1_WRISSUECAP1_EN(1'b0),
.S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WVALID(1'b0),
.S_AXI_HP2_ACLK(1'b0),
.S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARBURST({1'b0,1'b0}),
.S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
.S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLOCK({1'b0,1'b0}),
.S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
.S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARVALID(1'b0),
.S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWBURST({1'b0,1'b0}),
.S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLOCK({1'b0,1'b0}),
.S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
.S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWVALID(1'b0),
.S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
.S_AXI_HP2_BREADY(1'b0),
.S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
.S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP2_RDISSUECAP1_EN(1'b0),
.S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
.S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
.S_AXI_HP2_RREADY(1'b0),
.S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
.S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WLAST(1'b0),
.S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
.S_AXI_HP2_WRISSUECAP1_EN(1'b0),
.S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WVALID(1'b0),
.S_AXI_HP3_ACLK(1'b0),
.S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARBURST({1'b0,1'b0}),
.S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
.S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLOCK({1'b0,1'b0}),
.S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
.S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARVALID(1'b0),
.S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWBURST({1'b0,1'b0}),
.S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLOCK({1'b0,1'b0}),
.S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
.S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWVALID(1'b0),
.S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
.S_AXI_HP3_BREADY(1'b0),
.S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
.S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP3_RDISSUECAP1_EN(1'b0),
.S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
.S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
.S_AXI_HP3_RREADY(1'b0),
.S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
.S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WLAST(1'b0),
.S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
.S_AXI_HP3_WRISSUECAP1_EN(1'b0),
.S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WVALID(1'b0),
.TRACE_CLK(1'b0),
.TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
.TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
.TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
.TTC0_CLK0_IN(1'b0),
.TTC0_CLK1_IN(1'b0),
.TTC0_CLK2_IN(1'b0),
.TTC0_WAVE0_OUT(NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED),
.TTC0_WAVE1_OUT(NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED),
.TTC0_WAVE2_OUT(NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED),
.TTC1_CLK0_IN(1'b0),
.TTC1_CLK1_IN(1'b0),
.TTC1_CLK2_IN(1'b0),
.TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
.TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
.TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
.UART0_CTSN(1'b0),
.UART0_DCDN(1'b0),
.UART0_DSRN(1'b0),
.UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
.UART0_RIN(1'b0),
.UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
.UART0_RX(1'b1),
.UART0_TX(NLW_inst_UART0_TX_UNCONNECTED),
.UART1_CTSN(1'b0),
.UART1_DCDN(1'b0),
.UART1_DSRN(1'b0),
.UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
.UART1_RIN(1'b0),
.UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
.UART1_RX(1'b1),
.UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
.USB1_VBUS_PWRFAULT(1'b0),
.USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
.WDT_CLK_IN(1'b0),
.WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
(CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_EXT_INTIN,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_EXT_INTIN,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TDI,
PJTAG_TDO,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
TRACE_CLK_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_PORT_INDCTL,
USB1_VBUS_PWRSELECT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARESETN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARESETN,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARESETN,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARESETN,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_ARESETN,
S_AXI_ACP_ARREADY,
S_AXI_ACP_AWREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARESETN,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARESETN,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARESETN,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARESETN,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_RSTN,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_RSTN,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_RSTN,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_RSTN,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA3_DRVALID,
DMA0_DRTYPE,
DMA1_DRTYPE,
DMA2_DRTYPE,
DMA3_DRTYPE,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0,
FTMT_F2P_TRIG_1,
FTMT_F2P_TRIGACK_1,
FTMT_F2P_TRIG_2,
FTMT_F2P_TRIGACK_2,
FTMT_F2P_TRIG_3,
FTMT_F2P_TRIGACK_3,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK_0,
FTMT_P2F_TRIG_0,
FTMT_P2F_TRIGACK_1,
FTMT_P2F_TRIG_1,
FTMT_P2F_TRIGACK_2,
FTMT_P2F_TRIG_2,
FTMT_P2F_TRIGACK_3,
FTMT_P2F_TRIG_3,
FTMT_P2F_DEBUG,
FPGA_IDLE_N,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
DDR_ARB,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0]ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input ENET0_EXT_INTIN;
input [7:0]ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0]ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input ENET1_EXT_INTIN;
input [7:0]ENET1_GMII_RXD;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TDI;
output PJTAG_TDO;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0]SDIO0_DATA_I;
output [3:0]SDIO0_DATA_O;
output [3:0]SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0]SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0]SDIO1_DATA_I;
output [3:0]SDIO1_DATA_O;
output [3:0]SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0]SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [1:0]TRACE_DATA;
output TRACE_CLK_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output [1:0]USB1_PORT_INDCTL;
output USB1_VBUS_PWRSELECT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARESETN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output M_AXI_GP1_ARESETN;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11:0]M_AXI_GP1_ARID;
output [11:0]M_AXI_GP1_AWID;
output [11:0]M_AXI_GP1_WID;
output [1:0]M_AXI_GP1_ARBURST;
output [1:0]M_AXI_GP1_ARLOCK;
output [2:0]M_AXI_GP1_ARSIZE;
output [1:0]M_AXI_GP1_AWBURST;
output [1:0]M_AXI_GP1_AWLOCK;
output [2:0]M_AXI_GP1_AWSIZE;
output [2:0]M_AXI_GP1_ARPROT;
output [2:0]M_AXI_GP1_AWPROT;
output [31:0]M_AXI_GP1_ARADDR;
output [31:0]M_AXI_GP1_AWADDR;
output [31:0]M_AXI_GP1_WDATA;
output [3:0]M_AXI_GP1_ARCACHE;
output [3:0]M_AXI_GP1_ARLEN;
output [3:0]M_AXI_GP1_ARQOS;
output [3:0]M_AXI_GP1_AWCACHE;
output [3:0]M_AXI_GP1_AWLEN;
output [3:0]M_AXI_GP1_AWQOS;
output [3:0]M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11:0]M_AXI_GP1_BID;
input [11:0]M_AXI_GP1_RID;
input [1:0]M_AXI_GP1_BRESP;
input [1:0]M_AXI_GP1_RRESP;
input [31:0]M_AXI_GP1_RDATA;
output S_AXI_GP0_ARESETN;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0]S_AXI_GP0_BRESP;
output [1:0]S_AXI_GP0_RRESP;
output [31:0]S_AXI_GP0_RDATA;
output [5:0]S_AXI_GP0_BID;
output [5:0]S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0]S_AXI_GP0_ARBURST;
input [1:0]S_AXI_GP0_ARLOCK;
input [2:0]S_AXI_GP0_ARSIZE;
input [1:0]S_AXI_GP0_AWBURST;
input [1:0]S_AXI_GP0_AWLOCK;
input [2:0]S_AXI_GP0_AWSIZE;
input [2:0]S_AXI_GP0_ARPROT;
input [2:0]S_AXI_GP0_AWPROT;
input [31:0]S_AXI_GP0_ARADDR;
input [31:0]S_AXI_GP0_AWADDR;
input [31:0]S_AXI_GP0_WDATA;
input [3:0]S_AXI_GP0_ARCACHE;
input [3:0]S_AXI_GP0_ARLEN;
input [3:0]S_AXI_GP0_ARQOS;
input [3:0]S_AXI_GP0_AWCACHE;
input [3:0]S_AXI_GP0_AWLEN;
input [3:0]S_AXI_GP0_AWQOS;
input [3:0]S_AXI_GP0_WSTRB;
input [5:0]S_AXI_GP0_ARID;
input [5:0]S_AXI_GP0_AWID;
input [5:0]S_AXI_GP0_WID;
output S_AXI_GP1_ARESETN;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0]S_AXI_GP1_BRESP;
output [1:0]S_AXI_GP1_RRESP;
output [31:0]S_AXI_GP1_RDATA;
output [5:0]S_AXI_GP1_BID;
output [5:0]S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0]S_AXI_GP1_ARBURST;
input [1:0]S_AXI_GP1_ARLOCK;
input [2:0]S_AXI_GP1_ARSIZE;
input [1:0]S_AXI_GP1_AWBURST;
input [1:0]S_AXI_GP1_AWLOCK;
input [2:0]S_AXI_GP1_AWSIZE;
input [2:0]S_AXI_GP1_ARPROT;
input [2:0]S_AXI_GP1_AWPROT;
input [31:0]S_AXI_GP1_ARADDR;
input [31:0]S_AXI_GP1_AWADDR;
input [31:0]S_AXI_GP1_WDATA;
input [3:0]S_AXI_GP1_ARCACHE;
input [3:0]S_AXI_GP1_ARLEN;
input [3:0]S_AXI_GP1_ARQOS;
input [3:0]S_AXI_GP1_AWCACHE;
input [3:0]S_AXI_GP1_AWLEN;
input [3:0]S_AXI_GP1_AWQOS;
input [3:0]S_AXI_GP1_WSTRB;
input [5:0]S_AXI_GP1_ARID;
input [5:0]S_AXI_GP1_AWID;
input [5:0]S_AXI_GP1_WID;
output S_AXI_ACP_ARESETN;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0]S_AXI_ACP_BRESP;
output [1:0]S_AXI_ACP_RRESP;
output [2:0]S_AXI_ACP_BID;
output [2:0]S_AXI_ACP_RID;
output [63:0]S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0]S_AXI_ACP_ARID;
input [2:0]S_AXI_ACP_ARPROT;
input [2:0]S_AXI_ACP_AWID;
input [2:0]S_AXI_ACP_AWPROT;
input [2:0]S_AXI_ACP_WID;
input [31:0]S_AXI_ACP_ARADDR;
input [31:0]S_AXI_ACP_AWADDR;
input [3:0]S_AXI_ACP_ARCACHE;
input [3:0]S_AXI_ACP_ARLEN;
input [3:0]S_AXI_ACP_ARQOS;
input [3:0]S_AXI_ACP_AWCACHE;
input [3:0]S_AXI_ACP_AWLEN;
input [3:0]S_AXI_ACP_AWQOS;
input [1:0]S_AXI_ACP_ARBURST;
input [1:0]S_AXI_ACP_ARLOCK;
input [2:0]S_AXI_ACP_ARSIZE;
input [1:0]S_AXI_ACP_AWBURST;
input [1:0]S_AXI_ACP_AWLOCK;
input [2:0]S_AXI_ACP_AWSIZE;
input [4:0]S_AXI_ACP_ARUSER;
input [4:0]S_AXI_ACP_AWUSER;
input [63:0]S_AXI_ACP_WDATA;
input [7:0]S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARESETN;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0]S_AXI_HP0_BRESP;
output [1:0]S_AXI_HP0_RRESP;
output [5:0]S_AXI_HP0_BID;
output [5:0]S_AXI_HP0_RID;
output [63:0]S_AXI_HP0_RDATA;
output [7:0]S_AXI_HP0_RCOUNT;
output [7:0]S_AXI_HP0_WCOUNT;
output [2:0]S_AXI_HP0_RACOUNT;
output [5:0]S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0]S_AXI_HP0_ARBURST;
input [1:0]S_AXI_HP0_ARLOCK;
input [2:0]S_AXI_HP0_ARSIZE;
input [1:0]S_AXI_HP0_AWBURST;
input [1:0]S_AXI_HP0_AWLOCK;
input [2:0]S_AXI_HP0_AWSIZE;
input [2:0]S_AXI_HP0_ARPROT;
input [2:0]S_AXI_HP0_AWPROT;
input [31:0]S_AXI_HP0_ARADDR;
input [31:0]S_AXI_HP0_AWADDR;
input [3:0]S_AXI_HP0_ARCACHE;
input [3:0]S_AXI_HP0_ARLEN;
input [3:0]S_AXI_HP0_ARQOS;
input [3:0]S_AXI_HP0_AWCACHE;
input [3:0]S_AXI_HP0_AWLEN;
input [3:0]S_AXI_HP0_AWQOS;
input [5:0]S_AXI_HP0_ARID;
input [5:0]S_AXI_HP0_AWID;
input [5:0]S_AXI_HP0_WID;
input [63:0]S_AXI_HP0_WDATA;
input [7:0]S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARESETN;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0]S_AXI_HP1_BRESP;
output [1:0]S_AXI_HP1_RRESP;
output [5:0]S_AXI_HP1_BID;
output [5:0]S_AXI_HP1_RID;
output [63:0]S_AXI_HP1_RDATA;
output [7:0]S_AXI_HP1_RCOUNT;
output [7:0]S_AXI_HP1_WCOUNT;
output [2:0]S_AXI_HP1_RACOUNT;
output [5:0]S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0]S_AXI_HP1_ARBURST;
input [1:0]S_AXI_HP1_ARLOCK;
input [2:0]S_AXI_HP1_ARSIZE;
input [1:0]S_AXI_HP1_AWBURST;
input [1:0]S_AXI_HP1_AWLOCK;
input [2:0]S_AXI_HP1_AWSIZE;
input [2:0]S_AXI_HP1_ARPROT;
input [2:0]S_AXI_HP1_AWPROT;
input [31:0]S_AXI_HP1_ARADDR;
input [31:0]S_AXI_HP1_AWADDR;
input [3:0]S_AXI_HP1_ARCACHE;
input [3:0]S_AXI_HP1_ARLEN;
input [3:0]S_AXI_HP1_ARQOS;
input [3:0]S_AXI_HP1_AWCACHE;
input [3:0]S_AXI_HP1_AWLEN;
input [3:0]S_AXI_HP1_AWQOS;
input [5:0]S_AXI_HP1_ARID;
input [5:0]S_AXI_HP1_AWID;
input [5:0]S_AXI_HP1_WID;
input [63:0]S_AXI_HP1_WDATA;
input [7:0]S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARESETN;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0]S_AXI_HP2_BRESP;
output [1:0]S_AXI_HP2_RRESP;
output [5:0]S_AXI_HP2_BID;
output [5:0]S_AXI_HP2_RID;
output [63:0]S_AXI_HP2_RDATA;
output [7:0]S_AXI_HP2_RCOUNT;
output [7:0]S_AXI_HP2_WCOUNT;
output [2:0]S_AXI_HP2_RACOUNT;
output [5:0]S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0]S_AXI_HP2_ARBURST;
input [1:0]S_AXI_HP2_ARLOCK;
input [2:0]S_AXI_HP2_ARSIZE;
input [1:0]S_AXI_HP2_AWBURST;
input [1:0]S_AXI_HP2_AWLOCK;
input [2:0]S_AXI_HP2_AWSIZE;
input [2:0]S_AXI_HP2_ARPROT;
input [2:0]S_AXI_HP2_AWPROT;
input [31:0]S_AXI_HP2_ARADDR;
input [31:0]S_AXI_HP2_AWADDR;
input [3:0]S_AXI_HP2_ARCACHE;
input [3:0]S_AXI_HP2_ARLEN;
input [3:0]S_AXI_HP2_ARQOS;
input [3:0]S_AXI_HP2_AWCACHE;
input [3:0]S_AXI_HP2_AWLEN;
input [3:0]S_AXI_HP2_AWQOS;
input [5:0]S_AXI_HP2_ARID;
input [5:0]S_AXI_HP2_AWID;
input [5:0]S_AXI_HP2_WID;
input [63:0]S_AXI_HP2_WDATA;
input [7:0]S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARESETN;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0]S_AXI_HP3_BRESP;
output [1:0]S_AXI_HP3_RRESP;
output [5:0]S_AXI_HP3_BID;
output [5:0]S_AXI_HP3_RID;
output [63:0]S_AXI_HP3_RDATA;
output [7:0]S_AXI_HP3_RCOUNT;
output [7:0]S_AXI_HP3_WCOUNT;
output [2:0]S_AXI_HP3_RACOUNT;
output [5:0]S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0]S_AXI_HP3_ARBURST;
input [1:0]S_AXI_HP3_ARLOCK;
input [2:0]S_AXI_HP3_ARSIZE;
input [1:0]S_AXI_HP3_AWBURST;
input [1:0]S_AXI_HP3_AWLOCK;
input [2:0]S_AXI_HP3_AWSIZE;
input [2:0]S_AXI_HP3_ARPROT;
input [2:0]S_AXI_HP3_AWPROT;
input [31:0]S_AXI_HP3_ARADDR;
input [31:0]S_AXI_HP3_AWADDR;
input [3:0]S_AXI_HP3_ARCACHE;
input [3:0]S_AXI_HP3_ARLEN;
input [3:0]S_AXI_HP3_ARQOS;
input [3:0]S_AXI_HP3_AWCACHE;
input [3:0]S_AXI_HP3_AWLEN;
input [3:0]S_AXI_HP3_AWQOS;
input [5:0]S_AXI_HP3_ARID;
input [5:0]S_AXI_HP3_AWID;
input [5:0]S_AXI_HP3_WID;
input [63:0]S_AXI_HP3_WDATA;
input [7:0]S_AXI_HP3_WSTRB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
input [0:0]IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output [1:0]DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
output DMA0_RSTN;
output [1:0]DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
output DMA1_RSTN;
output [1:0]DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
output DMA2_RSTN;
output [1:0]DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
output DMA3_RSTN;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input DMA3_DRVALID;
input [1:0]DMA0_DRTYPE;
input [1:0]DMA1_DRTYPE;
input [1:0]DMA2_DRTYPE;
input [1:0]DMA3_DRTYPE;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input [31:0]FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0]FTMD_TRACEIN_ATID;
input FTMT_F2P_TRIG_0;
output FTMT_F2P_TRIGACK_0;
input FTMT_F2P_TRIG_1;
output FTMT_F2P_TRIGACK_1;
input FTMT_F2P_TRIG_2;
output FTMT_F2P_TRIGACK_2;
input FTMT_F2P_TRIG_3;
output FTMT_F2P_TRIGACK_3;
input [31:0]FTMT_F2P_DEBUG;
input FTMT_P2F_TRIGACK_0;
output FTMT_P2F_TRIG_0;
input FTMT_P2F_TRIGACK_1;
output FTMT_P2F_TRIG_1;
input FTMT_P2F_TRIGACK_2;
output FTMT_P2F_TRIG_2;
input FTMT_P2F_TRIGACK_3;
output FTMT_P2F_TRIG_3;
output [31:0]FTMT_P2F_DEBUG;
input FPGA_IDLE_N;
output EVENT_EVENTO;
output [1:0]EVENT_STANDBYWFE;
output [1:0]EVENT_STANDBYWFI;
input EVENT_EVENTI;
input [3:0]DDR_ARB;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
wire \<const0> ;
wire \<const1> ;
wire CAN0_PHY_RX;
wire CAN0_PHY_TX;
wire CAN1_PHY_RX;
wire CAN1_PHY_TX;
wire Core0_nFIQ;
wire Core0_nIRQ;
wire Core1_nFIQ;
wire Core1_nIRQ;
wire [3:0]DDR_ARB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire DMA0_ACLK;
wire DMA0_DAREADY;
wire [1:0]DMA0_DATYPE;
wire DMA0_DAVALID;
wire DMA0_DRLAST;
wire DMA0_DRREADY;
wire [1:0]DMA0_DRTYPE;
wire DMA0_DRVALID;
wire DMA0_RSTN;
wire DMA1_ACLK;
wire DMA1_DAREADY;
wire [1:0]DMA1_DATYPE;
wire DMA1_DAVALID;
wire DMA1_DRLAST;
wire DMA1_DRREADY;
wire [1:0]DMA1_DRTYPE;
wire DMA1_DRVALID;
wire DMA1_RSTN;
wire DMA2_ACLK;
wire DMA2_DAREADY;
wire [1:0]DMA2_DATYPE;
wire DMA2_DAVALID;
wire DMA2_DRLAST;
wire DMA2_DRREADY;
wire [1:0]DMA2_DRTYPE;
wire DMA2_DRVALID;
wire DMA2_RSTN;
wire DMA3_ACLK;
wire DMA3_DAREADY;
wire [1:0]DMA3_DATYPE;
wire DMA3_DAVALID;
wire DMA3_DRLAST;
wire DMA3_DRREADY;
wire [1:0]DMA3_DRTYPE;
wire DMA3_DRVALID;
wire DMA3_RSTN;
wire ENET0_EXT_INTIN;
wire ENET0_GMII_RX_CLK;
wire ENET0_GMII_TX_CLK;
wire ENET0_MDIO_I;
wire ENET0_MDIO_MDC;
wire ENET0_MDIO_O;
wire ENET0_MDIO_T;
wire ENET0_MDIO_T_n;
wire ENET0_PTP_DELAY_REQ_RX;
wire ENET0_PTP_DELAY_REQ_TX;
wire ENET0_PTP_PDELAY_REQ_RX;
wire ENET0_PTP_PDELAY_REQ_TX;
wire ENET0_PTP_PDELAY_RESP_RX;
wire ENET0_PTP_PDELAY_RESP_TX;
wire ENET0_PTP_SYNC_FRAME_RX;
wire ENET0_PTP_SYNC_FRAME_TX;
wire ENET0_SOF_RX;
wire ENET0_SOF_TX;
wire ENET1_EXT_INTIN;
wire ENET1_GMII_RX_CLK;
wire ENET1_GMII_TX_CLK;
wire ENET1_MDIO_I;
wire ENET1_MDIO_MDC;
wire ENET1_MDIO_O;
wire ENET1_MDIO_T;
wire ENET1_MDIO_T_n;
wire ENET1_PTP_DELAY_REQ_RX;
wire ENET1_PTP_DELAY_REQ_TX;
wire ENET1_PTP_PDELAY_REQ_RX;
wire ENET1_PTP_PDELAY_REQ_TX;
wire ENET1_PTP_PDELAY_RESP_RX;
wire ENET1_PTP_PDELAY_RESP_TX;
wire ENET1_PTP_SYNC_FRAME_RX;
wire ENET1_PTP_SYNC_FRAME_TX;
wire ENET1_SOF_RX;
wire ENET1_SOF_TX;
wire EVENT_EVENTI;
wire EVENT_EVENTO;
wire [1:0]EVENT_STANDBYWFE;
wire [1:0]EVENT_STANDBYWFI;
wire FCLK_CLK0;
wire FCLK_CLK1;
wire FCLK_CLK2;
wire FCLK_CLK3;
wire [0:0]FCLK_CLK_unbuffered;
wire FCLK_RESET0_N;
wire FCLK_RESET1_N;
wire FCLK_RESET2_N;
wire FCLK_RESET3_N;
wire FPGA_IDLE_N;
wire FTMD_TRACEIN_CLK;
wire [31:0]FTMT_F2P_DEBUG;
wire FTMT_F2P_TRIGACK_0;
wire FTMT_F2P_TRIGACK_1;
wire FTMT_F2P_TRIGACK_2;
wire FTMT_F2P_TRIGACK_3;
wire FTMT_F2P_TRIG_0;
wire FTMT_F2P_TRIG_1;
wire FTMT_F2P_TRIG_2;
wire FTMT_F2P_TRIG_3;
wire [31:0]FTMT_P2F_DEBUG;
wire FTMT_P2F_TRIGACK_0;
wire FTMT_P2F_TRIGACK_1;
wire FTMT_P2F_TRIGACK_2;
wire FTMT_P2F_TRIGACK_3;
wire FTMT_P2F_TRIG_0;
wire FTMT_P2F_TRIG_1;
wire FTMT_P2F_TRIG_2;
wire FTMT_P2F_TRIG_3;
wire [63:0]GPIO_I;
wire [63:0]GPIO_O;
wire [63:0]GPIO_T;
wire I2C0_SCL_I;
wire I2C0_SCL_O;
wire I2C0_SCL_T;
wire I2C0_SCL_T_n;
wire I2C0_SDA_I;
wire I2C0_SDA_O;
wire I2C0_SDA_T;
wire I2C0_SDA_T_n;
wire I2C1_SCL_I;
wire I2C1_SCL_O;
wire I2C1_SCL_T;
wire I2C1_SCL_T_n;
wire I2C1_SDA_I;
wire I2C1_SDA_O;
wire I2C1_SDA_T;
wire I2C1_SDA_T_n;
wire [0:0]IRQ_F2P;
wire IRQ_P2F_CAN0;
wire IRQ_P2F_CAN1;
wire IRQ_P2F_CTI;
wire IRQ_P2F_DMAC0;
wire IRQ_P2F_DMAC1;
wire IRQ_P2F_DMAC2;
wire IRQ_P2F_DMAC3;
wire IRQ_P2F_DMAC4;
wire IRQ_P2F_DMAC5;
wire IRQ_P2F_DMAC6;
wire IRQ_P2F_DMAC7;
wire IRQ_P2F_DMAC_ABORT;
wire IRQ_P2F_ENET0;
wire IRQ_P2F_ENET1;
wire IRQ_P2F_ENET_WAKE0;
wire IRQ_P2F_ENET_WAKE1;
wire IRQ_P2F_GPIO;
wire IRQ_P2F_I2C0;
wire IRQ_P2F_I2C1;
wire IRQ_P2F_QSPI;
wire IRQ_P2F_SDIO0;
wire IRQ_P2F_SDIO1;
wire IRQ_P2F_SMC;
wire IRQ_P2F_SPI0;
wire IRQ_P2F_SPI1;
wire IRQ_P2F_UART0;
wire IRQ_P2F_UART1;
wire IRQ_P2F_USB0;
wire IRQ_P2F_USB1;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]\^M_AXI_GP0_ARCACHE ;
wire M_AXI_GP0_ARESETN;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [1:0]\^M_AXI_GP0_ARSIZE ;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]\^M_AXI_GP0_AWCACHE ;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [1:0]\^M_AXI_GP0_AWSIZE ;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire M_AXI_GP1_ACLK;
wire [31:0]M_AXI_GP1_ARADDR;
wire [1:0]M_AXI_GP1_ARBURST;
wire [3:0]\^M_AXI_GP1_ARCACHE ;
wire M_AXI_GP1_ARESETN;
wire [11:0]M_AXI_GP1_ARID;
wire [3:0]M_AXI_GP1_ARLEN;
wire [1:0]M_AXI_GP1_ARLOCK;
wire [2:0]M_AXI_GP1_ARPROT;
wire [3:0]M_AXI_GP1_ARQOS;
wire M_AXI_GP1_ARREADY;
wire [1:0]\^M_AXI_GP1_ARSIZE ;
wire M_AXI_GP1_ARVALID;
wire [31:0]M_AXI_GP1_AWADDR;
wire [1:0]M_AXI_GP1_AWBURST;
wire [3:0]\^M_AXI_GP1_AWCACHE ;
wire [11:0]M_AXI_GP1_AWID;
wire [3:0]M_AXI_GP1_AWLEN;
wire [1:0]M_AXI_GP1_AWLOCK;
wire [2:0]M_AXI_GP1_AWPROT;
wire [3:0]M_AXI_GP1_AWQOS;
wire M_AXI_GP1_AWREADY;
wire [1:0]\^M_AXI_GP1_AWSIZE ;
wire M_AXI_GP1_AWVALID;
wire [11:0]M_AXI_GP1_BID;
wire M_AXI_GP1_BREADY;
wire [1:0]M_AXI_GP1_BRESP;
wire M_AXI_GP1_BVALID;
wire [31:0]M_AXI_GP1_RDATA;
wire [11:0]M_AXI_GP1_RID;
wire M_AXI_GP1_RLAST;
wire M_AXI_GP1_RREADY;
wire [1:0]M_AXI_GP1_RRESP;
wire M_AXI_GP1_RVALID;
wire [31:0]M_AXI_GP1_WDATA;
wire [11:0]M_AXI_GP1_WID;
wire M_AXI_GP1_WLAST;
wire M_AXI_GP1_WREADY;
wire [3:0]M_AXI_GP1_WSTRB;
wire M_AXI_GP1_WVALID;
wire PJTAG_TCK;
wire PJTAG_TDI;
wire PJTAG_TMS;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire SDIO0_BUSPOW;
wire [2:0]SDIO0_BUSVOLT;
wire SDIO0_CDN;
wire SDIO0_CLK;
wire SDIO0_CLK_FB;
wire SDIO0_CMD_I;
wire SDIO0_CMD_O;
wire SDIO0_CMD_T;
wire SDIO0_CMD_T_n;
wire [3:0]SDIO0_DATA_I;
wire [3:0]SDIO0_DATA_O;
wire [3:0]SDIO0_DATA_T;
wire [3:0]SDIO0_DATA_T_n;
wire SDIO0_LED;
wire SDIO0_WP;
wire SDIO1_BUSPOW;
wire [2:0]SDIO1_BUSVOLT;
wire SDIO1_CDN;
wire SDIO1_CLK;
wire SDIO1_CLK_FB;
wire SDIO1_CMD_I;
wire SDIO1_CMD_O;
wire SDIO1_CMD_T;
wire SDIO1_CMD_T_n;
wire [3:0]SDIO1_DATA_I;
wire [3:0]SDIO1_DATA_O;
wire [3:0]SDIO1_DATA_T;
wire [3:0]SDIO1_DATA_T_n;
wire SDIO1_LED;
wire SDIO1_WP;
wire SPI0_MISO_I;
wire SPI0_MISO_O;
wire SPI0_MISO_T;
wire SPI0_MISO_T_n;
wire SPI0_MOSI_I;
wire SPI0_MOSI_O;
wire SPI0_MOSI_T;
wire SPI0_MOSI_T_n;
wire SPI0_SCLK_I;
wire SPI0_SCLK_O;
wire SPI0_SCLK_T;
wire SPI0_SCLK_T_n;
wire SPI0_SS1_O;
wire SPI0_SS2_O;
wire SPI0_SS_I;
wire SPI0_SS_O;
wire SPI0_SS_T;
wire SPI0_SS_T_n;
wire SPI1_MISO_I;
wire SPI1_MISO_O;
wire SPI1_MISO_T;
wire SPI1_MISO_T_n;
wire SPI1_MOSI_I;
wire SPI1_MOSI_O;
wire SPI1_MOSI_T;
wire SPI1_MOSI_T_n;
wire SPI1_SCLK_I;
wire SPI1_SCLK_O;
wire SPI1_SCLK_T;
wire SPI1_SCLK_T_n;
wire SPI1_SS1_O;
wire SPI1_SS2_O;
wire SPI1_SS_I;
wire SPI1_SS_O;
wire SPI1_SS_T;
wire SPI1_SS_T_n;
wire SRAM_INTIN;
wire S_AXI_ACP_ACLK;
wire [31:0]S_AXI_ACP_ARADDR;
wire [1:0]S_AXI_ACP_ARBURST;
wire [3:0]S_AXI_ACP_ARCACHE;
wire S_AXI_ACP_ARESETN;
wire [2:0]S_AXI_ACP_ARID;
wire [3:0]S_AXI_ACP_ARLEN;
wire [1:0]S_AXI_ACP_ARLOCK;
wire [2:0]S_AXI_ACP_ARPROT;
wire [3:0]S_AXI_ACP_ARQOS;
wire S_AXI_ACP_ARREADY;
wire [2:0]S_AXI_ACP_ARSIZE;
wire [4:0]S_AXI_ACP_ARUSER;
wire S_AXI_ACP_ARVALID;
wire [31:0]S_AXI_ACP_AWADDR;
wire [1:0]S_AXI_ACP_AWBURST;
wire [3:0]S_AXI_ACP_AWCACHE;
wire [2:0]S_AXI_ACP_AWID;
wire [3:0]S_AXI_ACP_AWLEN;
wire [1:0]S_AXI_ACP_AWLOCK;
wire [2:0]S_AXI_ACP_AWPROT;
wire [3:0]S_AXI_ACP_AWQOS;
wire S_AXI_ACP_AWREADY;
wire [2:0]S_AXI_ACP_AWSIZE;
wire [4:0]S_AXI_ACP_AWUSER;
wire S_AXI_ACP_AWVALID;
wire [2:0]S_AXI_ACP_BID;
wire S_AXI_ACP_BREADY;
wire [1:0]S_AXI_ACP_BRESP;
wire S_AXI_ACP_BVALID;
wire [63:0]S_AXI_ACP_RDATA;
wire [2:0]S_AXI_ACP_RID;
wire S_AXI_ACP_RLAST;
wire S_AXI_ACP_RREADY;
wire [1:0]S_AXI_ACP_RRESP;
wire S_AXI_ACP_RVALID;
wire [63:0]S_AXI_ACP_WDATA;
wire [2:0]S_AXI_ACP_WID;
wire S_AXI_ACP_WLAST;
wire S_AXI_ACP_WREADY;
wire [7:0]S_AXI_ACP_WSTRB;
wire S_AXI_ACP_WVALID;
wire S_AXI_GP0_ACLK;
wire [31:0]S_AXI_GP0_ARADDR;
wire [1:0]S_AXI_GP0_ARBURST;
wire [3:0]S_AXI_GP0_ARCACHE;
wire S_AXI_GP0_ARESETN;
wire [5:0]S_AXI_GP0_ARID;
wire [3:0]S_AXI_GP0_ARLEN;
wire [1:0]S_AXI_GP0_ARLOCK;
wire [2:0]S_AXI_GP0_ARPROT;
wire [3:0]S_AXI_GP0_ARQOS;
wire S_AXI_GP0_ARREADY;
wire [2:0]S_AXI_GP0_ARSIZE;
wire S_AXI_GP0_ARVALID;
wire [31:0]S_AXI_GP0_AWADDR;
wire [1:0]S_AXI_GP0_AWBURST;
wire [3:0]S_AXI_GP0_AWCACHE;
wire [5:0]S_AXI_GP0_AWID;
wire [3:0]S_AXI_GP0_AWLEN;
wire [1:0]S_AXI_GP0_AWLOCK;
wire [2:0]S_AXI_GP0_AWPROT;
wire [3:0]S_AXI_GP0_AWQOS;
wire S_AXI_GP0_AWREADY;
wire [2:0]S_AXI_GP0_AWSIZE;
wire S_AXI_GP0_AWVALID;
wire [5:0]S_AXI_GP0_BID;
wire S_AXI_GP0_BREADY;
wire [1:0]S_AXI_GP0_BRESP;
wire S_AXI_GP0_BVALID;
wire [31:0]S_AXI_GP0_RDATA;
wire [5:0]S_AXI_GP0_RID;
wire S_AXI_GP0_RLAST;
wire S_AXI_GP0_RREADY;
wire [1:0]S_AXI_GP0_RRESP;
wire S_AXI_GP0_RVALID;
wire [31:0]S_AXI_GP0_WDATA;
wire [5:0]S_AXI_GP0_WID;
wire S_AXI_GP0_WLAST;
wire S_AXI_GP0_WREADY;
wire [3:0]S_AXI_GP0_WSTRB;
wire S_AXI_GP0_WVALID;
wire S_AXI_GP1_ACLK;
wire [31:0]S_AXI_GP1_ARADDR;
wire [1:0]S_AXI_GP1_ARBURST;
wire [3:0]S_AXI_GP1_ARCACHE;
wire S_AXI_GP1_ARESETN;
wire [5:0]S_AXI_GP1_ARID;
wire [3:0]S_AXI_GP1_ARLEN;
wire [1:0]S_AXI_GP1_ARLOCK;
wire [2:0]S_AXI_GP1_ARPROT;
wire [3:0]S_AXI_GP1_ARQOS;
wire S_AXI_GP1_ARREADY;
wire [2:0]S_AXI_GP1_ARSIZE;
wire S_AXI_GP1_ARVALID;
wire [31:0]S_AXI_GP1_AWADDR;
wire [1:0]S_AXI_GP1_AWBURST;
wire [3:0]S_AXI_GP1_AWCACHE;
wire [5:0]S_AXI_GP1_AWID;
wire [3:0]S_AXI_GP1_AWLEN;
wire [1:0]S_AXI_GP1_AWLOCK;
wire [2:0]S_AXI_GP1_AWPROT;
wire [3:0]S_AXI_GP1_AWQOS;
wire S_AXI_GP1_AWREADY;
wire [2:0]S_AXI_GP1_AWSIZE;
wire S_AXI_GP1_AWVALID;
wire [5:0]S_AXI_GP1_BID;
wire S_AXI_GP1_BREADY;
wire [1:0]S_AXI_GP1_BRESP;
wire S_AXI_GP1_BVALID;
wire [31:0]S_AXI_GP1_RDATA;
wire [5:0]S_AXI_GP1_RID;
wire S_AXI_GP1_RLAST;
wire S_AXI_GP1_RREADY;
wire [1:0]S_AXI_GP1_RRESP;
wire S_AXI_GP1_RVALID;
wire [31:0]S_AXI_GP1_WDATA;
wire [5:0]S_AXI_GP1_WID;
wire S_AXI_GP1_WLAST;
wire S_AXI_GP1_WREADY;
wire [3:0]S_AXI_GP1_WSTRB;
wire S_AXI_GP1_WVALID;
wire S_AXI_HP0_ACLK;
wire [31:0]S_AXI_HP0_ARADDR;
wire [1:0]S_AXI_HP0_ARBURST;
wire [3:0]S_AXI_HP0_ARCACHE;
wire S_AXI_HP0_ARESETN;
wire [5:0]S_AXI_HP0_ARID;
wire [3:0]S_AXI_HP0_ARLEN;
wire [1:0]S_AXI_HP0_ARLOCK;
wire [2:0]S_AXI_HP0_ARPROT;
wire [3:0]S_AXI_HP0_ARQOS;
wire S_AXI_HP0_ARREADY;
wire [2:0]S_AXI_HP0_ARSIZE;
wire S_AXI_HP0_ARVALID;
wire [31:0]S_AXI_HP0_AWADDR;
wire [1:0]S_AXI_HP0_AWBURST;
wire [3:0]S_AXI_HP0_AWCACHE;
wire [5:0]S_AXI_HP0_AWID;
wire [3:0]S_AXI_HP0_AWLEN;
wire [1:0]S_AXI_HP0_AWLOCK;
wire [2:0]S_AXI_HP0_AWPROT;
wire [3:0]S_AXI_HP0_AWQOS;
wire S_AXI_HP0_AWREADY;
wire [2:0]S_AXI_HP0_AWSIZE;
wire S_AXI_HP0_AWVALID;
wire [5:0]S_AXI_HP0_BID;
wire S_AXI_HP0_BREADY;
wire [1:0]S_AXI_HP0_BRESP;
wire S_AXI_HP0_BVALID;
wire [2:0]S_AXI_HP0_RACOUNT;
wire [7:0]S_AXI_HP0_RCOUNT;
wire [63:0]S_AXI_HP0_RDATA;
wire S_AXI_HP0_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP0_RID;
wire S_AXI_HP0_RLAST;
wire S_AXI_HP0_RREADY;
wire [1:0]S_AXI_HP0_RRESP;
wire S_AXI_HP0_RVALID;
wire [5:0]S_AXI_HP0_WACOUNT;
wire [7:0]S_AXI_HP0_WCOUNT;
wire [63:0]S_AXI_HP0_WDATA;
wire [5:0]S_AXI_HP0_WID;
wire S_AXI_HP0_WLAST;
wire S_AXI_HP0_WREADY;
wire S_AXI_HP0_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP0_WSTRB;
wire S_AXI_HP0_WVALID;
wire S_AXI_HP1_ACLK;
wire [31:0]S_AXI_HP1_ARADDR;
wire [1:0]S_AXI_HP1_ARBURST;
wire [3:0]S_AXI_HP1_ARCACHE;
wire S_AXI_HP1_ARESETN;
wire [5:0]S_AXI_HP1_ARID;
wire [3:0]S_AXI_HP1_ARLEN;
wire [1:0]S_AXI_HP1_ARLOCK;
wire [2:0]S_AXI_HP1_ARPROT;
wire [3:0]S_AXI_HP1_ARQOS;
wire S_AXI_HP1_ARREADY;
wire [2:0]S_AXI_HP1_ARSIZE;
wire S_AXI_HP1_ARVALID;
wire [31:0]S_AXI_HP1_AWADDR;
wire [1:0]S_AXI_HP1_AWBURST;
wire [3:0]S_AXI_HP1_AWCACHE;
wire [5:0]S_AXI_HP1_AWID;
wire [3:0]S_AXI_HP1_AWLEN;
wire [1:0]S_AXI_HP1_AWLOCK;
wire [2:0]S_AXI_HP1_AWPROT;
wire [3:0]S_AXI_HP1_AWQOS;
wire S_AXI_HP1_AWREADY;
wire [2:0]S_AXI_HP1_AWSIZE;
wire S_AXI_HP1_AWVALID;
wire [5:0]S_AXI_HP1_BID;
wire S_AXI_HP1_BREADY;
wire [1:0]S_AXI_HP1_BRESP;
wire S_AXI_HP1_BVALID;
wire [2:0]S_AXI_HP1_RACOUNT;
wire [7:0]S_AXI_HP1_RCOUNT;
wire [63:0]S_AXI_HP1_RDATA;
wire S_AXI_HP1_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP1_RID;
wire S_AXI_HP1_RLAST;
wire S_AXI_HP1_RREADY;
wire [1:0]S_AXI_HP1_RRESP;
wire S_AXI_HP1_RVALID;
wire [5:0]S_AXI_HP1_WACOUNT;
wire [7:0]S_AXI_HP1_WCOUNT;
wire [63:0]S_AXI_HP1_WDATA;
wire [5:0]S_AXI_HP1_WID;
wire S_AXI_HP1_WLAST;
wire S_AXI_HP1_WREADY;
wire S_AXI_HP1_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP1_WSTRB;
wire S_AXI_HP1_WVALID;
wire S_AXI_HP2_ACLK;
wire [31:0]S_AXI_HP2_ARADDR;
wire [1:0]S_AXI_HP2_ARBURST;
wire [3:0]S_AXI_HP2_ARCACHE;
wire S_AXI_HP2_ARESETN;
wire [5:0]S_AXI_HP2_ARID;
wire [3:0]S_AXI_HP2_ARLEN;
wire [1:0]S_AXI_HP2_ARLOCK;
wire [2:0]S_AXI_HP2_ARPROT;
wire [3:0]S_AXI_HP2_ARQOS;
wire S_AXI_HP2_ARREADY;
wire [2:0]S_AXI_HP2_ARSIZE;
wire S_AXI_HP2_ARVALID;
wire [31:0]S_AXI_HP2_AWADDR;
wire [1:0]S_AXI_HP2_AWBURST;
wire [3:0]S_AXI_HP2_AWCACHE;
wire [5:0]S_AXI_HP2_AWID;
wire [3:0]S_AXI_HP2_AWLEN;
wire [1:0]S_AXI_HP2_AWLOCK;
wire [2:0]S_AXI_HP2_AWPROT;
wire [3:0]S_AXI_HP2_AWQOS;
wire S_AXI_HP2_AWREADY;
wire [2:0]S_AXI_HP2_AWSIZE;
wire S_AXI_HP2_AWVALID;
wire [5:0]S_AXI_HP2_BID;
wire S_AXI_HP2_BREADY;
wire [1:0]S_AXI_HP2_BRESP;
wire S_AXI_HP2_BVALID;
wire [2:0]S_AXI_HP2_RACOUNT;
wire [7:0]S_AXI_HP2_RCOUNT;
wire [63:0]S_AXI_HP2_RDATA;
wire S_AXI_HP2_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP2_RID;
wire S_AXI_HP2_RLAST;
wire S_AXI_HP2_RREADY;
wire [1:0]S_AXI_HP2_RRESP;
wire S_AXI_HP2_RVALID;
wire [5:0]S_AXI_HP2_WACOUNT;
wire [7:0]S_AXI_HP2_WCOUNT;
wire [63:0]S_AXI_HP2_WDATA;
wire [5:0]S_AXI_HP2_WID;
wire S_AXI_HP2_WLAST;
wire S_AXI_HP2_WREADY;
wire S_AXI_HP2_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP2_WSTRB;
wire S_AXI_HP2_WVALID;
wire S_AXI_HP3_ACLK;
wire [31:0]S_AXI_HP3_ARADDR;
wire [1:0]S_AXI_HP3_ARBURST;
wire [3:0]S_AXI_HP3_ARCACHE;
wire S_AXI_HP3_ARESETN;
wire [5:0]S_AXI_HP3_ARID;
wire [3:0]S_AXI_HP3_ARLEN;
wire [1:0]S_AXI_HP3_ARLOCK;
wire [2:0]S_AXI_HP3_ARPROT;
wire [3:0]S_AXI_HP3_ARQOS;
wire S_AXI_HP3_ARREADY;
wire [2:0]S_AXI_HP3_ARSIZE;
wire S_AXI_HP3_ARVALID;
wire [31:0]S_AXI_HP3_AWADDR;
wire [1:0]S_AXI_HP3_AWBURST;
wire [3:0]S_AXI_HP3_AWCACHE;
wire [5:0]S_AXI_HP3_AWID;
wire [3:0]S_AXI_HP3_AWLEN;
wire [1:0]S_AXI_HP3_AWLOCK;
wire [2:0]S_AXI_HP3_AWPROT;
wire [3:0]S_AXI_HP3_AWQOS;
wire S_AXI_HP3_AWREADY;
wire [2:0]S_AXI_HP3_AWSIZE;
wire S_AXI_HP3_AWVALID;
wire [5:0]S_AXI_HP3_BID;
wire S_AXI_HP3_BREADY;
wire [1:0]S_AXI_HP3_BRESP;
wire S_AXI_HP3_BVALID;
wire [2:0]S_AXI_HP3_RACOUNT;
wire [7:0]S_AXI_HP3_RCOUNT;
wire [63:0]S_AXI_HP3_RDATA;
wire S_AXI_HP3_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP3_RID;
wire S_AXI_HP3_RLAST;
wire S_AXI_HP3_RREADY;
wire [1:0]S_AXI_HP3_RRESP;
wire S_AXI_HP3_RVALID;
wire [5:0]S_AXI_HP3_WACOUNT;
wire [7:0]S_AXI_HP3_WCOUNT;
wire [63:0]S_AXI_HP3_WDATA;
wire [5:0]S_AXI_HP3_WID;
wire S_AXI_HP3_WLAST;
wire S_AXI_HP3_WREADY;
wire S_AXI_HP3_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP3_WSTRB;
wire S_AXI_HP3_WVALID;
wire TRACE_CLK;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ;
wire TTC0_CLK0_IN;
wire TTC0_CLK1_IN;
wire TTC0_CLK2_IN;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire TTC1_CLK0_IN;
wire TTC1_CLK1_IN;
wire TTC1_CLK2_IN;
wire TTC1_WAVE0_OUT;
wire TTC1_WAVE1_OUT;
wire TTC1_WAVE2_OUT;
wire UART0_CTSN;
wire UART0_DCDN;
wire UART0_DSRN;
wire UART0_DTRN;
wire UART0_RIN;
wire UART0_RTSN;
wire UART0_RX;
wire UART0_TX;
wire UART1_CTSN;
wire UART1_DCDN;
wire UART1_DSRN;
wire UART1_DTRN;
wire UART1_RIN;
wire UART1_RTSN;
wire UART1_RX;
wire UART1_TX;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire [1:0]USB1_PORT_INDCTL;
wire USB1_VBUS_PWRFAULT;
wire USB1_VBUS_PWRSELECT;
wire WDT_CLK_IN;
wire WDT_RST_OUT;
wire [14:0]buffered_DDR_Addr;
wire [2:0]buffered_DDR_BankAddr;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_CS_n;
wire buffered_DDR_Clk;
wire buffered_DDR_Clk_n;
wire [3:0]buffered_DDR_DM;
wire [31:0]buffered_DDR_DQ;
wire [3:0]buffered_DDR_DQS;
wire [3:0]buffered_DDR_DQS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire buffered_DDR_WEB;
wire [53:0]buffered_MIO;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire buffered_PS_SRSTB;
wire [63:0]gpio_out_t_n;
wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED;
assign ENET0_GMII_TXD[7] = \<const0> ;
assign ENET0_GMII_TXD[6] = \<const0> ;
assign ENET0_GMII_TXD[5] = \<const0> ;
assign ENET0_GMII_TXD[4] = \<const0> ;
assign ENET0_GMII_TXD[3] = \<const0> ;
assign ENET0_GMII_TXD[2] = \<const0> ;
assign ENET0_GMII_TXD[1] = \<const0> ;
assign ENET0_GMII_TXD[0] = \<const0> ;
assign ENET0_GMII_TX_EN = \<const0> ;
assign ENET0_GMII_TX_ER = \<const0> ;
assign ENET1_GMII_TXD[7] = \<const0> ;
assign ENET1_GMII_TXD[6] = \<const0> ;
assign ENET1_GMII_TXD[5] = \<const0> ;
assign ENET1_GMII_TXD[4] = \<const0> ;
assign ENET1_GMII_TXD[3] = \<const0> ;
assign ENET1_GMII_TXD[2] = \<const0> ;
assign ENET1_GMII_TXD[1] = \<const0> ;
assign ENET1_GMII_TXD[0] = \<const0> ;
assign ENET1_GMII_TX_EN = \<const0> ;
assign ENET1_GMII_TX_ER = \<const0> ;
assign M_AXI_GP0_ARCACHE[3:2] = \^M_AXI_GP0_ARCACHE [3:2];
assign M_AXI_GP0_ARCACHE[1] = \<const1> ;
assign M_AXI_GP0_ARCACHE[0] = \^M_AXI_GP0_ARCACHE [0];
assign M_AXI_GP0_ARSIZE[2] = \<const0> ;
assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0];
assign M_AXI_GP0_AWCACHE[3:2] = \^M_AXI_GP0_AWCACHE [3:2];
assign M_AXI_GP0_AWCACHE[1] = \<const1> ;
assign M_AXI_GP0_AWCACHE[0] = \^M_AXI_GP0_AWCACHE [0];
assign M_AXI_GP0_AWSIZE[2] = \<const0> ;
assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0];
assign M_AXI_GP1_ARCACHE[3:2] = \^M_AXI_GP1_ARCACHE [3:2];
assign M_AXI_GP1_ARCACHE[1] = \<const1> ;
assign M_AXI_GP1_ARCACHE[0] = \^M_AXI_GP1_ARCACHE [0];
assign M_AXI_GP1_ARSIZE[2] = \<const0> ;
assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0];
assign M_AXI_GP1_AWCACHE[3:2] = \^M_AXI_GP1_AWCACHE [3:2];
assign M_AXI_GP1_AWCACHE[1] = \<const1> ;
assign M_AXI_GP1_AWCACHE[0] = \^M_AXI_GP1_AWCACHE [0];
assign M_AXI_GP1_AWSIZE[2] = \<const0> ;
assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0];
assign PJTAG_TDO = \<const0> ;
assign TRACE_CLK_OUT = \<const0> ;
assign TRACE_CTL = \TRACE_CTL_PIPE[0] ;
assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ;
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CAS_n_BIBUF
(.IO(buffered_DDR_CAS_n),
.PAD(DDR_CAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CKE_BIBUF
(.IO(buffered_DDR_CKE),
.PAD(DDR_CKE));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CS_n_BIBUF
(.IO(buffered_DDR_CS_n),
.PAD(DDR_CS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_BIBUF
(.IO(buffered_DDR_Clk),
.PAD(DDR_Clk));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_n_BIBUF
(.IO(buffered_DDR_Clk_n),
.PAD(DDR_Clk_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_DRSTB_BIBUF
(.IO(buffered_DDR_DRSTB),
.PAD(DDR_DRSTB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_ODT_BIBUF
(.IO(buffered_DDR_ODT),
.PAD(DDR_ODT));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_RAS_n_BIBUF
(.IO(buffered_DDR_RAS_n),
.PAD(DDR_RAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRN_BIBUF
(.IO(buffered_DDR_VRN),
.PAD(DDR_VRN));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRP_BIBUF
(.IO(buffered_DDR_VRP),
.PAD(DDR_VRP));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_WEB_BIBUF
(.IO(buffered_DDR_WEB),
.PAD(DDR_WEB));
LUT1 #(
.INIT(2'h1))
ENET0_MDIO_T_INST_0
(.I0(ENET0_MDIO_T_n),
.O(ENET0_MDIO_T));
LUT1 #(
.INIT(2'h1))
ENET1_MDIO_T_INST_0
(.I0(ENET1_MDIO_T_n),
.O(ENET1_MDIO_T));
GND GND
(.G(\<const0> ));
LUT1 #(
.INIT(2'h1))
\GPIO_T[0]_INST_0
(.I0(gpio_out_t_n[0]),
.O(GPIO_T[0]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[10]_INST_0
(.I0(gpio_out_t_n[10]),
.O(GPIO_T[10]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[11]_INST_0
(.I0(gpio_out_t_n[11]),
.O(GPIO_T[11]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[12]_INST_0
(.I0(gpio_out_t_n[12]),
.O(GPIO_T[12]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[13]_INST_0
(.I0(gpio_out_t_n[13]),
.O(GPIO_T[13]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[14]_INST_0
(.I0(gpio_out_t_n[14]),
.O(GPIO_T[14]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[15]_INST_0
(.I0(gpio_out_t_n[15]),
.O(GPIO_T[15]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[16]_INST_0
(.I0(gpio_out_t_n[16]),
.O(GPIO_T[16]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[17]_INST_0
(.I0(gpio_out_t_n[17]),
.O(GPIO_T[17]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[18]_INST_0
(.I0(gpio_out_t_n[18]),
.O(GPIO_T[18]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[19]_INST_0
(.I0(gpio_out_t_n[19]),
.O(GPIO_T[19]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[1]_INST_0
(.I0(gpio_out_t_n[1]),
.O(GPIO_T[1]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[20]_INST_0
(.I0(gpio_out_t_n[20]),
.O(GPIO_T[20]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[21]_INST_0
(.I0(gpio_out_t_n[21]),
.O(GPIO_T[21]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[22]_INST_0
(.I0(gpio_out_t_n[22]),
.O(GPIO_T[22]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[23]_INST_0
(.I0(gpio_out_t_n[23]),
.O(GPIO_T[23]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[24]_INST_0
(.I0(gpio_out_t_n[24]),
.O(GPIO_T[24]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[25]_INST_0
(.I0(gpio_out_t_n[25]),
.O(GPIO_T[25]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[26]_INST_0
(.I0(gpio_out_t_n[26]),
.O(GPIO_T[26]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[27]_INST_0
(.I0(gpio_out_t_n[27]),
.O(GPIO_T[27]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[28]_INST_0
(.I0(gpio_out_t_n[28]),
.O(GPIO_T[28]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[29]_INST_0
(.I0(gpio_out_t_n[29]),
.O(GPIO_T[29]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[2]_INST_0
(.I0(gpio_out_t_n[2]),
.O(GPIO_T[2]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[30]_INST_0
(.I0(gpio_out_t_n[30]),
.O(GPIO_T[30]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[31]_INST_0
(.I0(gpio_out_t_n[31]),
.O(GPIO_T[31]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[32]_INST_0
(.I0(gpio_out_t_n[32]),
.O(GPIO_T[32]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[33]_INST_0
(.I0(gpio_out_t_n[33]),
.O(GPIO_T[33]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[34]_INST_0
(.I0(gpio_out_t_n[34]),
.O(GPIO_T[34]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[35]_INST_0
(.I0(gpio_out_t_n[35]),
.O(GPIO_T[35]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[36]_INST_0
(.I0(gpio_out_t_n[36]),
.O(GPIO_T[36]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[37]_INST_0
(.I0(gpio_out_t_n[37]),
.O(GPIO_T[37]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[38]_INST_0
(.I0(gpio_out_t_n[38]),
.O(GPIO_T[38]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[39]_INST_0
(.I0(gpio_out_t_n[39]),
.O(GPIO_T[39]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[3]_INST_0
(.I0(gpio_out_t_n[3]),
.O(GPIO_T[3]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[40]_INST_0
(.I0(gpio_out_t_n[40]),
.O(GPIO_T[40]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[41]_INST_0
(.I0(gpio_out_t_n[41]),
.O(GPIO_T[41]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[42]_INST_0
(.I0(gpio_out_t_n[42]),
.O(GPIO_T[42]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[43]_INST_0
(.I0(gpio_out_t_n[43]),
.O(GPIO_T[43]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[44]_INST_0
(.I0(gpio_out_t_n[44]),
.O(GPIO_T[44]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[45]_INST_0
(.I0(gpio_out_t_n[45]),
.O(GPIO_T[45]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[46]_INST_0
(.I0(gpio_out_t_n[46]),
.O(GPIO_T[46]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[47]_INST_0
(.I0(gpio_out_t_n[47]),
.O(GPIO_T[47]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[48]_INST_0
(.I0(gpio_out_t_n[48]),
.O(GPIO_T[48]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[49]_INST_0
(.I0(gpio_out_t_n[49]),
.O(GPIO_T[49]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[4]_INST_0
(.I0(gpio_out_t_n[4]),
.O(GPIO_T[4]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[50]_INST_0
(.I0(gpio_out_t_n[50]),
.O(GPIO_T[50]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[51]_INST_0
(.I0(gpio_out_t_n[51]),
.O(GPIO_T[51]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[52]_INST_0
(.I0(gpio_out_t_n[52]),
.O(GPIO_T[52]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[53]_INST_0
(.I0(gpio_out_t_n[53]),
.O(GPIO_T[53]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[54]_INST_0
(.I0(gpio_out_t_n[54]),
.O(GPIO_T[54]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[55]_INST_0
(.I0(gpio_out_t_n[55]),
.O(GPIO_T[55]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[56]_INST_0
(.I0(gpio_out_t_n[56]),
.O(GPIO_T[56]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[57]_INST_0
(.I0(gpio_out_t_n[57]),
.O(GPIO_T[57]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[58]_INST_0
(.I0(gpio_out_t_n[58]),
.O(GPIO_T[58]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[59]_INST_0
(.I0(gpio_out_t_n[59]),
.O(GPIO_T[59]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[5]_INST_0
(.I0(gpio_out_t_n[5]),
.O(GPIO_T[5]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[60]_INST_0
(.I0(gpio_out_t_n[60]),
.O(GPIO_T[60]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[61]_INST_0
(.I0(gpio_out_t_n[61]),
.O(GPIO_T[61]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[62]_INST_0
(.I0(gpio_out_t_n[62]),
.O(GPIO_T[62]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[63]_INST_0
(.I0(gpio_out_t_n[63]),
.O(GPIO_T[63]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[6]_INST_0
(.I0(gpio_out_t_n[6]),
.O(GPIO_T[6]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[7]_INST_0
(.I0(gpio_out_t_n[7]),
.O(GPIO_T[7]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[8]_INST_0
(.I0(gpio_out_t_n[8]),
.O(GPIO_T[8]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[9]_INST_0
(.I0(gpio_out_t_n[9]),
.O(GPIO_T[9]));
LUT1 #(
.INIT(2'h1))
I2C0_SCL_T_INST_0
(.I0(I2C0_SCL_T_n),
.O(I2C0_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C0_SDA_T_INST_0
(.I0(I2C0_SDA_T_n),
.O(I2C0_SDA_T));
LUT1 #(
.INIT(2'h1))
I2C1_SCL_T_INST_0
(.I0(I2C1_SCL_T_n),
.O(I2C1_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C1_SDA_T_INST_0
(.I0(I2C1_SDA_T_n),
.O(I2C1_SDA_T));
(* BOX_TYPE = "PRIMITIVE" *)
PS7 PS7_i
(.DDRA(buffered_DDR_Addr),
.DDRARB(DDR_ARB),
.DDRBA(buffered_DDR_BankAddr),
.DDRCASB(buffered_DDR_CAS_n),
.DDRCKE(buffered_DDR_CKE),
.DDRCKN(buffered_DDR_Clk_n),
.DDRCKP(buffered_DDR_Clk),
.DDRCSB(buffered_DDR_CS_n),
.DDRDM(buffered_DDR_DM),
.DDRDQ(buffered_DDR_DQ),
.DDRDQSN(buffered_DDR_DQS_n),
.DDRDQSP(buffered_DDR_DQS),
.DDRDRSTB(buffered_DDR_DRSTB),
.DDRODT(buffered_DDR_ODT),
.DDRRASB(buffered_DDR_RAS_n),
.DDRVRN(buffered_DDR_VRN),
.DDRVRP(buffered_DDR_VRP),
.DDRWEB(buffered_DDR_WEB),
.DMA0ACLK(DMA0_ACLK),
.DMA0DAREADY(DMA0_DAREADY),
.DMA0DATYPE(DMA0_DATYPE),
.DMA0DAVALID(DMA0_DAVALID),
.DMA0DRLAST(DMA0_DRLAST),
.DMA0DRREADY(DMA0_DRREADY),
.DMA0DRTYPE(DMA0_DRTYPE),
.DMA0DRVALID(DMA0_DRVALID),
.DMA0RSTN(DMA0_RSTN),
.DMA1ACLK(DMA1_ACLK),
.DMA1DAREADY(DMA1_DAREADY),
.DMA1DATYPE(DMA1_DATYPE),
.DMA1DAVALID(DMA1_DAVALID),
.DMA1DRLAST(DMA1_DRLAST),
.DMA1DRREADY(DMA1_DRREADY),
.DMA1DRTYPE(DMA1_DRTYPE),
.DMA1DRVALID(DMA1_DRVALID),
.DMA1RSTN(DMA1_RSTN),
.DMA2ACLK(DMA2_ACLK),
.DMA2DAREADY(DMA2_DAREADY),
.DMA2DATYPE(DMA2_DATYPE),
.DMA2DAVALID(DMA2_DAVALID),
.DMA2DRLAST(DMA2_DRLAST),
.DMA2DRREADY(DMA2_DRREADY),
.DMA2DRTYPE(DMA2_DRTYPE),
.DMA2DRVALID(DMA2_DRVALID),
.DMA2RSTN(DMA2_RSTN),
.DMA3ACLK(DMA3_ACLK),
.DMA3DAREADY(DMA3_DAREADY),
.DMA3DATYPE(DMA3_DATYPE),
.DMA3DAVALID(DMA3_DAVALID),
.DMA3DRLAST(DMA3_DRLAST),
.DMA3DRREADY(DMA3_DRREADY),
.DMA3DRTYPE(DMA3_DRTYPE),
.DMA3DRVALID(DMA3_DRVALID),
.DMA3RSTN(DMA3_RSTN),
.EMIOCAN0PHYRX(CAN0_PHY_RX),
.EMIOCAN0PHYTX(CAN0_PHY_TX),
.EMIOCAN1PHYRX(CAN1_PHY_RX),
.EMIOCAN1PHYTX(CAN1_PHY_TX),
.EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
.EMIOENET0GMIICOL(1'b0),
.EMIOENET0GMIICRS(1'b0),
.EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET0GMIIRXDV(1'b0),
.EMIOENET0GMIIRXER(1'b0),
.EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
.EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
.EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
.EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
.EMIOENET0MDIOI(ENET0_MDIO_I),
.EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
.EMIOENET0MDIOO(ENET0_MDIO_O),
.EMIOENET0MDIOTN(ENET0_MDIO_T_n),
.EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX(ENET0_SOF_RX),
.EMIOENET0SOFTX(ENET0_SOF_TX),
.EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
.EMIOENET1GMIICOL(1'b0),
.EMIOENET1GMIICRS(1'b0),
.EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET1GMIIRXDV(1'b0),
.EMIOENET1GMIIRXER(1'b0),
.EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
.EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
.EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
.EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
.EMIOENET1MDIOI(ENET1_MDIO_I),
.EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
.EMIOENET1MDIOO(ENET1_MDIO_O),
.EMIOENET1MDIOTN(ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX(ENET1_SOF_RX),
.EMIOENET1SOFTX(ENET1_SOF_TX),
.EMIOGPIOI(GPIO_I),
.EMIOGPIOO(GPIO_O),
.EMIOGPIOTN(gpio_out_t_n),
.EMIOI2C0SCLI(I2C0_SCL_I),
.EMIOI2C0SCLO(I2C0_SCL_O),
.EMIOI2C0SCLTN(I2C0_SCL_T_n),
.EMIOI2C0SDAI(I2C0_SDA_I),
.EMIOI2C0SDAO(I2C0_SDA_O),
.EMIOI2C0SDATN(I2C0_SDA_T_n),
.EMIOI2C1SCLI(I2C1_SCL_I),
.EMIOI2C1SCLO(I2C1_SCL_O),
.EMIOI2C1SCLTN(I2C1_SCL_T_n),
.EMIOI2C1SDAI(I2C1_SDA_I),
.EMIOI2C1SDAO(I2C1_SDA_O),
.EMIOI2C1SDATN(I2C1_SDA_T_n),
.EMIOPJTAGTCK(PJTAG_TCK),
.EMIOPJTAGTDI(PJTAG_TDI),
.EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
.EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
.EMIOPJTAGTMS(PJTAG_TMS),
.EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
.EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
.EMIOSDIO0CDN(SDIO0_CDN),
.EMIOSDIO0CLK(SDIO0_CLK),
.EMIOSDIO0CLKFB(SDIO0_CLK_FB),
.EMIOSDIO0CMDI(SDIO0_CMD_I),
.EMIOSDIO0CMDO(SDIO0_CMD_O),
.EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
.EMIOSDIO0DATAI(SDIO0_DATA_I),
.EMIOSDIO0DATAO(SDIO0_DATA_O),
.EMIOSDIO0DATATN(SDIO0_DATA_T_n),
.EMIOSDIO0LED(SDIO0_LED),
.EMIOSDIO0WP(SDIO0_WP),
.EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
.EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
.EMIOSDIO1CDN(SDIO1_CDN),
.EMIOSDIO1CLK(SDIO1_CLK),
.EMIOSDIO1CLKFB(SDIO1_CLK_FB),
.EMIOSDIO1CMDI(SDIO1_CMD_I),
.EMIOSDIO1CMDO(SDIO1_CMD_O),
.EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
.EMIOSDIO1DATAI(SDIO1_DATA_I),
.EMIOSDIO1DATAO(SDIO1_DATA_O),
.EMIOSDIO1DATATN(SDIO1_DATA_T_n),
.EMIOSDIO1LED(SDIO1_LED),
.EMIOSDIO1WP(SDIO1_WP),
.EMIOSPI0MI(SPI0_MISO_I),
.EMIOSPI0MO(SPI0_MOSI_O),
.EMIOSPI0MOTN(SPI0_MOSI_T_n),
.EMIOSPI0SCLKI(SPI0_SCLK_I),
.EMIOSPI0SCLKO(SPI0_SCLK_O),
.EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
.EMIOSPI0SI(SPI0_MOSI_I),
.EMIOSPI0SO(SPI0_MISO_O),
.EMIOSPI0SSIN(SPI0_SS_I),
.EMIOSPI0SSNTN(SPI0_SS_T_n),
.EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0STN(SPI0_MISO_T_n),
.EMIOSPI1MI(SPI1_MISO_I),
.EMIOSPI1MO(SPI1_MOSI_O),
.EMIOSPI1MOTN(SPI1_MOSI_T_n),
.EMIOSPI1SCLKI(SPI1_SCLK_I),
.EMIOSPI1SCLKO(SPI1_SCLK_O),
.EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
.EMIOSPI1SI(SPI1_MOSI_I),
.EMIOSPI1SO(SPI1_MISO_O),
.EMIOSPI1SSIN(SPI1_SS_I),
.EMIOSPI1SSNTN(SPI1_SS_T_n),
.EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1STN(SPI1_MISO_T_n),
.EMIOSRAMINTIN(SRAM_INTIN),
.EMIOTRACECLK(TRACE_CLK),
.EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
.EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
.EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
.EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
.EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0CTSN(UART0_CTSN),
.EMIOUART0DCDN(UART0_DCDN),
.EMIOUART0DSRN(UART0_DSRN),
.EMIOUART0DTRN(UART0_DTRN),
.EMIOUART0RIN(UART0_RIN),
.EMIOUART0RTSN(UART0_RTSN),
.EMIOUART0RX(UART0_RX),
.EMIOUART0TX(UART0_TX),
.EMIOUART1CTSN(UART1_CTSN),
.EMIOUART1DCDN(UART1_DCDN),
.EMIOUART1DSRN(UART1_DSRN),
.EMIOUART1DTRN(UART1_DTRN),
.EMIOUART1RIN(UART1_RIN),
.EMIOUART1RTSN(UART1_RTSN),
.EMIOUART1RX(UART1_RX),
.EMIOUART1TX(UART1_TX),
.EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
.EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
.EMIOWDTCLKI(WDT_CLK_IN),
.EMIOWDTRSTO(WDT_RST_OUT),
.EVENTEVENTI(EVENT_EVENTI),
.EVENTEVENTO(EVENT_EVENTO),
.EVENTSTANDBYWFE(EVENT_STANDBYWFE),
.EVENTSTANDBYWFI(EVENT_STANDBYWFI),
.FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
.FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}),
.FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.FPGAIDLEN(FPGA_IDLE_N),
.FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINVALID(1'b0),
.FTMTF2PDEBUG(FTMT_F2P_DEBUG),
.FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG(FTMT_P2F_DEBUG),
.FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}),
.IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
.MAXIGP0ACLK(M_AXI_GP0_ACLK),
.MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE(\^M_AXI_GP0_ARCACHE ),
.MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
.MAXIGP0ARID(M_AXI_GP0_ARID),
.MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
.MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
.MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
.MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
.MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
.MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ),
.MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
.MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE(\^M_AXI_GP0_AWCACHE ),
.MAXIGP0AWID(M_AXI_GP0_AWID),
.MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
.MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
.MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
.MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
.MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
.MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ),
.MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
.MAXIGP0BID(M_AXI_GP0_BID),
.MAXIGP0BREADY(M_AXI_GP0_BREADY),
.MAXIGP0BRESP(M_AXI_GP0_BRESP),
.MAXIGP0BVALID(M_AXI_GP0_BVALID),
.MAXIGP0RDATA(M_AXI_GP0_RDATA),
.MAXIGP0RID(M_AXI_GP0_RID),
.MAXIGP0RLAST(M_AXI_GP0_RLAST),
.MAXIGP0RREADY(M_AXI_GP0_RREADY),
.MAXIGP0RRESP(M_AXI_GP0_RRESP),
.MAXIGP0RVALID(M_AXI_GP0_RVALID),
.MAXIGP0WDATA(M_AXI_GP0_WDATA),
.MAXIGP0WID(M_AXI_GP0_WID),
.MAXIGP0WLAST(M_AXI_GP0_WLAST),
.MAXIGP0WREADY(M_AXI_GP0_WREADY),
.MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
.MAXIGP0WVALID(M_AXI_GP0_WVALID),
.MAXIGP1ACLK(M_AXI_GP1_ACLK),
.MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
.MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE(\^M_AXI_GP1_ARCACHE ),
.MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
.MAXIGP1ARID(M_AXI_GP1_ARID),
.MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
.MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
.MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
.MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
.MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
.MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ),
.MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
.MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE(\^M_AXI_GP1_AWCACHE ),
.MAXIGP1AWID(M_AXI_GP1_AWID),
.MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
.MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
.MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
.MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
.MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
.MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ),
.MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
.MAXIGP1BID(M_AXI_GP1_BID),
.MAXIGP1BREADY(M_AXI_GP1_BREADY),
.MAXIGP1BRESP(M_AXI_GP1_BRESP),
.MAXIGP1BVALID(M_AXI_GP1_BVALID),
.MAXIGP1RDATA(M_AXI_GP1_RDATA),
.MAXIGP1RID(M_AXI_GP1_RID),
.MAXIGP1RLAST(M_AXI_GP1_RLAST),
.MAXIGP1RREADY(M_AXI_GP1_RREADY),
.MAXIGP1RRESP(M_AXI_GP1_RRESP),
.MAXIGP1RVALID(M_AXI_GP1_RVALID),
.MAXIGP1WDATA(M_AXI_GP1_WDATA),
.MAXIGP1WID(M_AXI_GP1_WID),
.MAXIGP1WLAST(M_AXI_GP1_WLAST),
.MAXIGP1WREADY(M_AXI_GP1_WREADY),
.MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
.MAXIGP1WVALID(M_AXI_GP1_WVALID),
.MIO(buffered_MIO),
.PSCLK(buffered_PS_CLK),
.PSPORB(buffered_PS_PORB),
.PSSRSTB(buffered_PS_SRSTB),
.SAXIACPACLK(S_AXI_ACP_ACLK),
.SAXIACPARADDR(S_AXI_ACP_ARADDR),
.SAXIACPARBURST(S_AXI_ACP_ARBURST),
.SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
.SAXIACPARESETN(S_AXI_ACP_ARESETN),
.SAXIACPARID(S_AXI_ACP_ARID),
.SAXIACPARLEN(S_AXI_ACP_ARLEN),
.SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
.SAXIACPARPROT(S_AXI_ACP_ARPROT),
.SAXIACPARQOS(S_AXI_ACP_ARQOS),
.SAXIACPARREADY(S_AXI_ACP_ARREADY),
.SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
.SAXIACPARUSER(S_AXI_ACP_ARUSER),
.SAXIACPARVALID(S_AXI_ACP_ARVALID),
.SAXIACPAWADDR(S_AXI_ACP_AWADDR),
.SAXIACPAWBURST(S_AXI_ACP_AWBURST),
.SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
.SAXIACPAWID(S_AXI_ACP_AWID),
.SAXIACPAWLEN(S_AXI_ACP_AWLEN),
.SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
.SAXIACPAWPROT(S_AXI_ACP_AWPROT),
.SAXIACPAWQOS(S_AXI_ACP_AWQOS),
.SAXIACPAWREADY(S_AXI_ACP_AWREADY),
.SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
.SAXIACPAWUSER(S_AXI_ACP_AWUSER),
.SAXIACPAWVALID(S_AXI_ACP_AWVALID),
.SAXIACPBID(S_AXI_ACP_BID),
.SAXIACPBREADY(S_AXI_ACP_BREADY),
.SAXIACPBRESP(S_AXI_ACP_BRESP),
.SAXIACPBVALID(S_AXI_ACP_BVALID),
.SAXIACPRDATA(S_AXI_ACP_RDATA),
.SAXIACPRID(S_AXI_ACP_RID),
.SAXIACPRLAST(S_AXI_ACP_RLAST),
.SAXIACPRREADY(S_AXI_ACP_RREADY),
.SAXIACPRRESP(S_AXI_ACP_RRESP),
.SAXIACPRVALID(S_AXI_ACP_RVALID),
.SAXIACPWDATA(S_AXI_ACP_WDATA),
.SAXIACPWID(S_AXI_ACP_WID),
.SAXIACPWLAST(S_AXI_ACP_WLAST),
.SAXIACPWREADY(S_AXI_ACP_WREADY),
.SAXIACPWSTRB(S_AXI_ACP_WSTRB),
.SAXIACPWVALID(S_AXI_ACP_WVALID),
.SAXIGP0ACLK(S_AXI_GP0_ACLK),
.SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
.SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
.SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
.SAXIGP0ARID(S_AXI_GP0_ARID),
.SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
.SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
.SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
.SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
.SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
.SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
.SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
.SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
.SAXIGP0AWID(S_AXI_GP0_AWID),
.SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
.SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
.SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
.SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
.SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
.SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
.SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
.SAXIGP0BID(S_AXI_GP0_BID),
.SAXIGP0BREADY(S_AXI_GP0_BREADY),
.SAXIGP0BRESP(S_AXI_GP0_BRESP),
.SAXIGP0BVALID(S_AXI_GP0_BVALID),
.SAXIGP0RDATA(S_AXI_GP0_RDATA),
.SAXIGP0RID(S_AXI_GP0_RID),
.SAXIGP0RLAST(S_AXI_GP0_RLAST),
.SAXIGP0RREADY(S_AXI_GP0_RREADY),
.SAXIGP0RRESP(S_AXI_GP0_RRESP),
.SAXIGP0RVALID(S_AXI_GP0_RVALID),
.SAXIGP0WDATA(S_AXI_GP0_WDATA),
.SAXIGP0WID(S_AXI_GP0_WID),
.SAXIGP0WLAST(S_AXI_GP0_WLAST),
.SAXIGP0WREADY(S_AXI_GP0_WREADY),
.SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
.SAXIGP0WVALID(S_AXI_GP0_WVALID),
.SAXIGP1ACLK(S_AXI_GP1_ACLK),
.SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
.SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
.SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
.SAXIGP1ARID(S_AXI_GP1_ARID),
.SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
.SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
.SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
.SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
.SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
.SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
.SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
.SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
.SAXIGP1AWID(S_AXI_GP1_AWID),
.SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
.SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
.SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
.SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
.SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
.SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
.SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
.SAXIGP1BID(S_AXI_GP1_BID),
.SAXIGP1BREADY(S_AXI_GP1_BREADY),
.SAXIGP1BRESP(S_AXI_GP1_BRESP),
.SAXIGP1BVALID(S_AXI_GP1_BVALID),
.SAXIGP1RDATA(S_AXI_GP1_RDATA),
.SAXIGP1RID(S_AXI_GP1_RID),
.SAXIGP1RLAST(S_AXI_GP1_RLAST),
.SAXIGP1RREADY(S_AXI_GP1_RREADY),
.SAXIGP1RRESP(S_AXI_GP1_RRESP),
.SAXIGP1RVALID(S_AXI_GP1_RVALID),
.SAXIGP1WDATA(S_AXI_GP1_WDATA),
.SAXIGP1WID(S_AXI_GP1_WID),
.SAXIGP1WLAST(S_AXI_GP1_WLAST),
.SAXIGP1WREADY(S_AXI_GP1_WREADY),
.SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
.SAXIGP1WVALID(S_AXI_GP1_WVALID),
.SAXIHP0ACLK(S_AXI_HP0_ACLK),
.SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
.SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
.SAXIHP0ARID(S_AXI_HP0_ARID),
.SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
.SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
.SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
.SAXIHP0AWID(S_AXI_HP0_AWID),
.SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
.SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
.SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
.SAXIHP0BID(S_AXI_HP0_BID),
.SAXIHP0BREADY(S_AXI_HP0_BREADY),
.SAXIHP0BRESP(S_AXI_HP0_BRESP),
.SAXIHP0BVALID(S_AXI_HP0_BVALID),
.SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA(S_AXI_HP0_RDATA),
.SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RID(S_AXI_HP0_RID),
.SAXIHP0RLAST(S_AXI_HP0_RLAST),
.SAXIHP0RREADY(S_AXI_HP0_RREADY),
.SAXIHP0RRESP(S_AXI_HP0_RRESP),
.SAXIHP0RVALID(S_AXI_HP0_RVALID),
.SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
.SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
.SAXIHP0WDATA(S_AXI_HP0_WDATA),
.SAXIHP0WID(S_AXI_HP0_WID),
.SAXIHP0WLAST(S_AXI_HP0_WLAST),
.SAXIHP0WREADY(S_AXI_HP0_WREADY),
.SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
.SAXIHP0WVALID(S_AXI_HP0_WVALID),
.SAXIHP1ACLK(S_AXI_HP1_ACLK),
.SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
.SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
.SAXIHP1ARID(S_AXI_HP1_ARID),
.SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
.SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
.SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
.SAXIHP1AWID(S_AXI_HP1_AWID),
.SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
.SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
.SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
.SAXIHP1BID(S_AXI_HP1_BID),
.SAXIHP1BREADY(S_AXI_HP1_BREADY),
.SAXIHP1BRESP(S_AXI_HP1_BRESP),
.SAXIHP1BVALID(S_AXI_HP1_BVALID),
.SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
.SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
.SAXIHP1RDATA(S_AXI_HP1_RDATA),
.SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RID(S_AXI_HP1_RID),
.SAXIHP1RLAST(S_AXI_HP1_RLAST),
.SAXIHP1RREADY(S_AXI_HP1_RREADY),
.SAXIHP1RRESP(S_AXI_HP1_RRESP),
.SAXIHP1RVALID(S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
.SAXIHP1WDATA(S_AXI_HP1_WDATA),
.SAXIHP1WID(S_AXI_HP1_WID),
.SAXIHP1WLAST(S_AXI_HP1_WLAST),
.SAXIHP1WREADY(S_AXI_HP1_WREADY),
.SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
.SAXIHP1WVALID(S_AXI_HP1_WVALID),
.SAXIHP2ACLK(S_AXI_HP2_ACLK),
.SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
.SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
.SAXIHP2ARID(S_AXI_HP2_ARID),
.SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
.SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
.SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
.SAXIHP2AWID(S_AXI_HP2_AWID),
.SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
.SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
.SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
.SAXIHP2BID(S_AXI_HP2_BID),
.SAXIHP2BREADY(S_AXI_HP2_BREADY),
.SAXIHP2BRESP(S_AXI_HP2_BRESP),
.SAXIHP2BVALID(S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA(S_AXI_HP2_RDATA),
.SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RID(S_AXI_HP2_RID),
.SAXIHP2RLAST(S_AXI_HP2_RLAST),
.SAXIHP2RREADY(S_AXI_HP2_RREADY),
.SAXIHP2RRESP(S_AXI_HP2_RRESP),
.SAXIHP2RVALID(S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
.SAXIHP2WDATA(S_AXI_HP2_WDATA),
.SAXIHP2WID(S_AXI_HP2_WID),
.SAXIHP2WLAST(S_AXI_HP2_WLAST),
.SAXIHP2WREADY(S_AXI_HP2_WREADY),
.SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
.SAXIHP2WVALID(S_AXI_HP2_WVALID),
.SAXIHP3ACLK(S_AXI_HP3_ACLK),
.SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
.SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
.SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
.SAXIHP3ARID(S_AXI_HP3_ARID),
.SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
.SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
.SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
.SAXIHP3AWID(S_AXI_HP3_AWID),
.SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
.SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
.SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
.SAXIHP3BID(S_AXI_HP3_BID),
.SAXIHP3BREADY(S_AXI_HP3_BREADY),
.SAXIHP3BRESP(S_AXI_HP3_BRESP),
.SAXIHP3BVALID(S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA(S_AXI_HP3_RDATA),
.SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RID(S_AXI_HP3_RID),
.SAXIHP3RLAST(S_AXI_HP3_RLAST),
.SAXIHP3RREADY(S_AXI_HP3_RREADY),
.SAXIHP3RRESP(S_AXI_HP3_RRESP),
.SAXIHP3RVALID(S_AXI_HP3_RVALID),
.SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
.SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
.SAXIHP3WDATA(S_AXI_HP3_WDATA),
.SAXIHP3WID(S_AXI_HP3_WID),
.SAXIHP3WLAST(S_AXI_HP3_WLAST),
.SAXIHP3WREADY(S_AXI_HP3_WREADY),
.SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
.SAXIHP3WVALID(S_AXI_HP3_WVALID));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_CLK_BIBUF
(.IO(buffered_PS_CLK),
.PAD(PS_CLK));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_PORB_BIBUF
(.IO(buffered_PS_PORB),
.PAD(PS_PORB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_SRSTB_BIBUF
(.IO(buffered_PS_SRSTB),
.PAD(PS_SRSTB));
LUT1 #(
.INIT(2'h1))
SDIO0_CMD_T_INST_0
(.I0(SDIO0_CMD_T_n),
.O(SDIO0_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[0]_INST_0
(.I0(SDIO0_DATA_T_n[0]),
.O(SDIO0_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[1]_INST_0
(.I0(SDIO0_DATA_T_n[1]),
.O(SDIO0_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[2]_INST_0
(.I0(SDIO0_DATA_T_n[2]),
.O(SDIO0_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[3]_INST_0
(.I0(SDIO0_DATA_T_n[3]),
.O(SDIO0_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SDIO1_CMD_T_INST_0
(.I0(SDIO1_CMD_T_n),
.O(SDIO1_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[0]_INST_0
(.I0(SDIO1_DATA_T_n[0]),
.O(SDIO1_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[1]_INST_0
(.I0(SDIO1_DATA_T_n[1]),
.O(SDIO1_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[2]_INST_0
(.I0(SDIO1_DATA_T_n[2]),
.O(SDIO1_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[3]_INST_0
(.I0(SDIO1_DATA_T_n[3]),
.O(SDIO1_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SPI0_MISO_T_INST_0
(.I0(SPI0_MISO_T_n),
.O(SPI0_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI0_MOSI_T_INST_0
(.I0(SPI0_MOSI_T_n),
.O(SPI0_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI0_SCLK_T_INST_0
(.I0(SPI0_SCLK_T_n),
.O(SPI0_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI0_SS_T_INST_0
(.I0(SPI0_SS_T_n),
.O(SPI0_SS_T));
LUT1 #(
.INIT(2'h1))
SPI1_MISO_T_INST_0
(.I0(SPI1_MISO_T_n),
.O(SPI1_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI1_MOSI_T_INST_0
(.I0(SPI1_MOSI_T_n),
.O(SPI1_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI1_SCLK_T_INST_0
(.I0(SPI1_SCLK_T_n),
.O(SPI1_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI1_SS_T_INST_0
(.I0(SPI1_SS_T_n),
.O(SPI1_SS_T));
VCC VCC
(.P(\<const1> ));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG
(.I(FCLK_CLK_unbuffered),
.O(FCLK_CLK0));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[0].MIO_BIBUF
(.IO(buffered_MIO[0]),
.PAD(MIO[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[10].MIO_BIBUF
(.IO(buffered_MIO[10]),
.PAD(MIO[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[11].MIO_BIBUF
(.IO(buffered_MIO[11]),
.PAD(MIO[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[12].MIO_BIBUF
(.IO(buffered_MIO[12]),
.PAD(MIO[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[13].MIO_BIBUF
(.IO(buffered_MIO[13]),
.PAD(MIO[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[14].MIO_BIBUF
(.IO(buffered_MIO[14]),
.PAD(MIO[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[15].MIO_BIBUF
(.IO(buffered_MIO[15]),
.PAD(MIO[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[16].MIO_BIBUF
(.IO(buffered_MIO[16]),
.PAD(MIO[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[17].MIO_BIBUF
(.IO(buffered_MIO[17]),
.PAD(MIO[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[18].MIO_BIBUF
(.IO(buffered_MIO[18]),
.PAD(MIO[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[19].MIO_BIBUF
(.IO(buffered_MIO[19]),
.PAD(MIO[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[1].MIO_BIBUF
(.IO(buffered_MIO[1]),
.PAD(MIO[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[20].MIO_BIBUF
(.IO(buffered_MIO[20]),
.PAD(MIO[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[21].MIO_BIBUF
(.IO(buffered_MIO[21]),
.PAD(MIO[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[22].MIO_BIBUF
(.IO(buffered_MIO[22]),
.PAD(MIO[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[23].MIO_BIBUF
(.IO(buffered_MIO[23]),
.PAD(MIO[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[24].MIO_BIBUF
(.IO(buffered_MIO[24]),
.PAD(MIO[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[25].MIO_BIBUF
(.IO(buffered_MIO[25]),
.PAD(MIO[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[26].MIO_BIBUF
(.IO(buffered_MIO[26]),
.PAD(MIO[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[27].MIO_BIBUF
(.IO(buffered_MIO[27]),
.PAD(MIO[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[28].MIO_BIBUF
(.IO(buffered_MIO[28]),
.PAD(MIO[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[29].MIO_BIBUF
(.IO(buffered_MIO[29]),
.PAD(MIO[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[2].MIO_BIBUF
(.IO(buffered_MIO[2]),
.PAD(MIO[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[30].MIO_BIBUF
(.IO(buffered_MIO[30]),
.PAD(MIO[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[31].MIO_BIBUF
(.IO(buffered_MIO[31]),
.PAD(MIO[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[32].MIO_BIBUF
(.IO(buffered_MIO[32]),
.PAD(MIO[32]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[33].MIO_BIBUF
(.IO(buffered_MIO[33]),
.PAD(MIO[33]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[34].MIO_BIBUF
(.IO(buffered_MIO[34]),
.PAD(MIO[34]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[35].MIO_BIBUF
(.IO(buffered_MIO[35]),
.PAD(MIO[35]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[36].MIO_BIBUF
(.IO(buffered_MIO[36]),
.PAD(MIO[36]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[37].MIO_BIBUF
(.IO(buffered_MIO[37]),
.PAD(MIO[37]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[38].MIO_BIBUF
(.IO(buffered_MIO[38]),
.PAD(MIO[38]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[39].MIO_BIBUF
(.IO(buffered_MIO[39]),
.PAD(MIO[39]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[3].MIO_BIBUF
(.IO(buffered_MIO[3]),
.PAD(MIO[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[40].MIO_BIBUF
(.IO(buffered_MIO[40]),
.PAD(MIO[40]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[41].MIO_BIBUF
(.IO(buffered_MIO[41]),
.PAD(MIO[41]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[42].MIO_BIBUF
(.IO(buffered_MIO[42]),
.PAD(MIO[42]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[43].MIO_BIBUF
(.IO(buffered_MIO[43]),
.PAD(MIO[43]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[44].MIO_BIBUF
(.IO(buffered_MIO[44]),
.PAD(MIO[44]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[45].MIO_BIBUF
(.IO(buffered_MIO[45]),
.PAD(MIO[45]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[46].MIO_BIBUF
(.IO(buffered_MIO[46]),
.PAD(MIO[46]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[47].MIO_BIBUF
(.IO(buffered_MIO[47]),
.PAD(MIO[47]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[48].MIO_BIBUF
(.IO(buffered_MIO[48]),
.PAD(MIO[48]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[49].MIO_BIBUF
(.IO(buffered_MIO[49]),
.PAD(MIO[49]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[4].MIO_BIBUF
(.IO(buffered_MIO[4]),
.PAD(MIO[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[50].MIO_BIBUF
(.IO(buffered_MIO[50]),
.PAD(MIO[50]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[51].MIO_BIBUF
(.IO(buffered_MIO[51]),
.PAD(MIO[51]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[52].MIO_BIBUF
(.IO(buffered_MIO[52]),
.PAD(MIO[52]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[53].MIO_BIBUF
(.IO(buffered_MIO[53]),
.PAD(MIO[53]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[5].MIO_BIBUF
(.IO(buffered_MIO[5]),
.PAD(MIO[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[6].MIO_BIBUF
(.IO(buffered_MIO[6]),
.PAD(MIO[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[7].MIO_BIBUF
(.IO(buffered_MIO[7]),
.PAD(MIO[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[8].MIO_BIBUF
(.IO(buffered_MIO[8]),
.PAD(MIO[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[9].MIO_BIBUF
(.IO(buffered_MIO[9]),
.PAD(MIO[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[0].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[0]),
.PAD(DDR_BankAddr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[1].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[1]),
.PAD(DDR_BankAddr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[2].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[2]),
.PAD(DDR_BankAddr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[0].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[0]),
.PAD(DDR_Addr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[10].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[10]),
.PAD(DDR_Addr[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[11].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[11]),
.PAD(DDR_Addr[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[12].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[12]),
.PAD(DDR_Addr[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[13].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[13]),
.PAD(DDR_Addr[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[14].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[14]),
.PAD(DDR_Addr[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[1].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[1]),
.PAD(DDR_Addr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[2].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[2]),
.PAD(DDR_Addr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[3].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[3]),
.PAD(DDR_Addr[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[4].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[4]),
.PAD(DDR_Addr[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[5].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[5]),
.PAD(DDR_Addr[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[6].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[6]),
.PAD(DDR_Addr[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[7].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[7]),
.PAD(DDR_Addr[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[8].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[8]),
.PAD(DDR_Addr[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[9].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[9]),
.PAD(DDR_Addr[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[0].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[0]),
.PAD(DDR_DM[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[1].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[1]),
.PAD(DDR_DM[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[2].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[2]),
.PAD(DDR_DM[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[3].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[3]),
.PAD(DDR_DM[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[0].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[0]),
.PAD(DDR_DQ[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[10].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[10]),
.PAD(DDR_DQ[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[11].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[11]),
.PAD(DDR_DQ[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[12].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[12]),
.PAD(DDR_DQ[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[13].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[13]),
.PAD(DDR_DQ[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[14].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[14]),
.PAD(DDR_DQ[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[15].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[15]),
.PAD(DDR_DQ[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[16].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[16]),
.PAD(DDR_DQ[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[17].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[17]),
.PAD(DDR_DQ[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[18].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[18]),
.PAD(DDR_DQ[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[19].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[19]),
.PAD(DDR_DQ[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[1].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[1]),
.PAD(DDR_DQ[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[20].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[20]),
.PAD(DDR_DQ[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[21].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[21]),
.PAD(DDR_DQ[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[22].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[22]),
.PAD(DDR_DQ[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[23].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[23]),
.PAD(DDR_DQ[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[24].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[24]),
.PAD(DDR_DQ[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[25].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[25]),
.PAD(DDR_DQ[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[26].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[26]),
.PAD(DDR_DQ[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[27].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[27]),
.PAD(DDR_DQ[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[28].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[28]),
.PAD(DDR_DQ[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[29].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[29]),
.PAD(DDR_DQ[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[2].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[2]),
.PAD(DDR_DQ[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[30].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[30]),
.PAD(DDR_DQ[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[31].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[31]),
.PAD(DDR_DQ[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[3].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[3]),
.PAD(DDR_DQ[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[4].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[4]),
.PAD(DDR_DQ[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[5].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[5]),
.PAD(DDR_DQ[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[6].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[6]),
.PAD(DDR_DQ[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[7].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[7]),
.PAD(DDR_DQ[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[8].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[8]),
.PAD(DDR_DQ[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[9].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[9]),
.PAD(DDR_DQ[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[0].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[0]),
.PAD(DDR_DQS_n[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[1].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[1]),
.PAD(DDR_DQS_n[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[2].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[2]),
.PAD(DDR_DQS_n[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[3].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[3]),
.PAD(DDR_DQS_n[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[0].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[0]),
.PAD(DDR_DQS[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[1].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[1]),
.PAD(DDR_DQS[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[2].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[2]),
.PAD(DDR_DQS[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[3].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[3]),
.PAD(DDR_DQS[3]));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[0] ));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [1]));
LUT1 #(
.INIT(2'h2))
i_10
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [1]));
LUT1 #(
.INIT(2'h2))
i_11
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [0]));
LUT1 #(
.INIT(2'h2))
i_12
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [1]));
LUT1 #(
.INIT(2'h2))
i_13
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [0]));
LUT1 #(
.INIT(2'h2))
i_14
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [1]));
LUT1 #(
.INIT(2'h2))
i_15
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [0]));
LUT1 #(
.INIT(2'h2))
i_16
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [1]));
LUT1 #(
.INIT(2'h2))
i_17
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [0]));
LUT1 #(
.INIT(2'h2))
i_18
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [1]));
LUT1 #(
.INIT(2'h2))
i_19
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [0]));
LUT1 #(
.INIT(2'h2))
i_2
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [0]));
LUT1 #(
.INIT(2'h2))
i_20
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [1]));
LUT1 #(
.INIT(2'h2))
i_21
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [0]));
LUT1 #(
.INIT(2'h2))
i_22
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [1]));
LUT1 #(
.INIT(2'h2))
i_23
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [0]));
LUT1 #(
.INIT(2'h2))
i_3
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[7] ));
LUT1 #(
.INIT(2'h2))
i_4
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[6] ));
LUT1 #(
.INIT(2'h2))
i_5
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[5] ));
LUT1 #(
.INIT(2'h2))
i_6
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[4] ));
LUT1 #(
.INIT(2'h2))
i_7
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[3] ));
LUT1 #(
.INIT(2'h2))
i_8
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[2] ));
LUT1 #(
.INIT(2'h2))
i_9
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[1] ));
endmodule
|
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
|
module io_bus
(
input wire clk_sys,
input wire rst,
// input ao486_avalon_io
input wire [15:0] ao486_avalon_io_address,
output wire ao486_avalon_io_waitrequest,
input wire [3:0] ao486_avalon_io_byteenable,
input wire ao486_avalon_io_read,
output wire [31:0] ao486_avalon_io_readdata,
output wire ao486_avalon_io_readdatavalid,
input wire ao486_avalon_io_write,
input wire [31:0] ao486_avalon_io_writedata,
// output vga_io_b, address: 0x3b0~0x3bf
output wire [3:0] vga_io_b_address,
output wire vga_io_b_write,
output wire [7:0] vga_io_b_writedata,
output wire vga_io_b_read,
input wire [7:0] vga_io_b_readdata,
// output vga_io_c, address: 0x3c0~0x3cf
output wire [3:0] vga_io_c_address,
output wire vga_io_c_write,
output wire [7:0] vga_io_c_writedata,
output wire vga_io_c_read,
input wire [7:0] vga_io_c_readdata,
// output vga_io_d, address: 0x3d0~0x3df
output wire [3:0] vga_io_d_address,
output wire vga_io_d_write,
output wire [7:0] vga_io_d_writedata,
output wire vga_io_d_read,
input wire [7:0] vga_io_d_readdata,
// output ps2_io, address: 0x60~0x67
output wire [2:0] ps2_io_address,
output wire ps2_io_write,
output wire [7:0] ps2_io_writedata,
output wire ps2_io_read,
input wire [7:0] ps2_io_readdata,
// output ps2_sysctl, address: 0x90~0x9f
output wire [3:0] ps2_sysctl_address,
output wire ps2_sysctl_write,
output wire [7:0] ps2_sysctl_writedata,
output wire ps2_sysctl_read,
input wire [7:0] ps2_sysctl_readdata,
// output pit_io, address: 0x40~0x43
output wire [1:0] pit_io_address,
output wire pit_io_write,
output wire [7:0] pit_io_writedata,
output wire pit_io_read,
input wire [7:0] pit_io_readdata,
// output rtc_io, address: 0x70~0x71
output wire rtc_io_address,
output wire rtc_io_write,
output wire [7:0] rtc_io_writedata,
output wire rtc_io_read,
input wire [7:0] rtc_io_readdata,
// output pic_master, address: 0x20~0x21
output wire pic_master_address,
output wire pic_master_write,
output wire [7:0] pic_master_writedata,
output wire pic_master_read,
input wire [7:0] pic_master_readdata,
// output pic_slave, address: 0xa0~0xa1
output wire pic_slave_address,
output wire pic_slave_write,
output wire [7:0] pic_slave_writedata,
output wire pic_slave_read,
input wire [7:0] pic_slave_readdata,
// output hdd_io, address: 0x1f0, 0x1f4
output wire hdd_io_address,
output wire hdd_io_write,
output wire [31:0] hdd_io_writedata,
output wire hdd_io_read,
input wire [31:0] hdd_io_readdata,
output wire [3:0] hdd_io_byteenable,
// output ide_3f6, address: 0x3f6
output wire ide_3f6_write,
output wire [7:0] ide_3f6_writedata,
output wire ide_3f6_read,
input wire [7:0] ide_3f6_readdata
);
function [1:0] count_bit;
input [3:0] data;
integer i;
begin
count_bit = 0;
for(i = 0; i <= 3; i = i + 1) begin
if(data[i])
count_bit = count_bit + 1;
end
end
endfunction
//------------------------------------------------------------------------------------
//------------------ ao486 --------------------------------------------------------
//------------------------------------------------------------------------------------
reg vga_io_b_readdatavalid;
always @(posedge clk_sys) vga_io_b_readdatavalid <= vga_io_b_read;
reg vga_io_c_readdatavalid;
always @(posedge clk_sys) vga_io_c_readdatavalid <= vga_io_c_read;
reg vga_io_d_readdatavalid;
always @(posedge clk_sys) vga_io_d_readdatavalid <= vga_io_d_read;
reg ps2_io_readdatavalid;
always @(posedge clk_sys) ps2_io_readdatavalid <= ps2_io_read;
reg ps2_sysctl_readdatavalid;
always @(posedge clk_sys) ps2_sysctl_readdatavalid <= ps2_sysctl_read;
reg pit_io_readdatavalid;
always @(posedge clk_sys) pit_io_readdatavalid <= pit_io_read;
reg rtc_io_readdatavalid;
always @(posedge clk_sys) rtc_io_readdatavalid <= rtc_io_read;
reg pic_master_readdatavalid;
always @(posedge clk_sys) pic_master_readdatavalid <= pic_master_read;
reg pic_slave_readdatavalid;
always @(posedge clk_sys) pic_slave_readdatavalid <= pic_slave_read;
reg ide_3f6_readdatavalid;
always @(posedge clk_sys) ide_3f6_readdatavalid <= ide_3f6_read;
reg hdd_io_readdatavalid;
always @(posedge clk_sys) hdd_io_readdatavalid <= hdd_io_read;
wire [31:0] converted_readdata;
wire converted_readdatavalid;
wire [7:0] readdata_without_hdd;
wire readdatavalid_without_hdd;
reg error_rdvalid;
assign readdatavalid_without_hdd = vga_io_b_readdatavalid || vga_io_c_readdatavalid ||
vga_io_d_readdatavalid || ps2_io_readdatavalid ||
ps2_io_readdatavalid || ps2_sysctl_readdatavalid ||
pit_io_readdatavalid || rtc_io_readdatavalid ||
pic_master_readdatavalid || pic_slave_readdatavalid ||
ide_3f6_readdatavalid || error_rdvalid;
assign readdata_without_hdd = (vga_io_b_readdatavalid) ? vga_io_b_readdata :
(vga_io_c_readdatavalid) ? vga_io_c_readdata :
(vga_io_d_readdatavalid) ? vga_io_d_readdata :
(ps2_io_readdatavalid) ? ps2_io_readdata :
(ps2_sysctl_readdatavalid) ? ps2_sysctl_readdata :
(pit_io_readdatavalid) ? pit_io_readdata :
(rtc_io_readdatavalid) ? rtc_io_readdata :
(pic_master_readdatavalid) ? pic_master_readdata :
(pic_slave_readdatavalid) ? pic_slave_readdata :
(ide_3f6_readdatavalid) ? ide_3f6_readdata : 0;
assign ao486_avalon_io_readdata = (hdd_io_readdatavalid) ? hdd_io_readdata : converted_readdata;
assign ao486_avalon_io_readdatavalid = converted_readdatavalid || hdd_io_readdatavalid;
wire [15:0] converted_address;
wire [7:0] converted_writedata;
wire converted_write, converted_read;
byteen_converter #(.IADDR(16), .OADDR(16))
byteen_converter(.clk_sys(clk_sys), .rst(rst), .addr_in(ao486_avalon_io_address), .write_in(ao486_avalon_io_write && ~hdd_io_write),
.writedata_in(ao486_avalon_io_writedata), .read_in(ao486_avalon_io_read && ~hdd_io_read), .byteenable_in(ao486_avalon_io_byteenable),
.waitrequest_out(ao486_avalon_io_waitrequest), .addr_out(converted_address), .write_out(converted_write),
.writedata_out(converted_writedata), .read_out(converted_read), .waitrequest_in(0), .readdata_in(readdata_without_hdd),
.readdatavalid_in(readdatavalid_without_hdd), .readdata_out(converted_readdata), .readdatavalid_out(converted_readdatavalid));
//------------------------------------------------------------------------------------
//------------------ vga_io_b --------------------------------------------------------
//------------------------------------------------------------------------------------
assign vga_io_b_address = converted_address[3:0];
assign vga_io_b_read = (converted_address[15:4] == 12'h3b) && converted_read;
assign vga_io_b_write = (converted_address[15:4] == 12'h3b) && converted_write;
assign vga_io_b_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ vga_io_c --------------------------------------------------------
//------------------------------------------------------------------------------------
assign vga_io_c_address = converted_address[3:0];
assign vga_io_c_read = (converted_address[15:4] == 12'h3c) && converted_read;
assign vga_io_c_write = (converted_address[15:4] == 12'h3c) && converted_write;
assign vga_io_c_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ vga_io_d --------------------------------------------------------
//------------------------------------------------------------------------------------
assign vga_io_d_address = converted_address[3:0];
assign vga_io_d_read = (converted_address[15:4] == 12'h3d) && converted_read;
assign vga_io_d_write = (converted_address[15:4] == 12'h3d) && converted_write;
assign vga_io_d_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ ps2_io ----------------------------------------------------------
//------------------------------------------------------------------------------------
assign ps2_io_address = converted_address[2:0];
assign ps2_io_read = (converted_address[15:4] == 12'h6) && converted_read;
assign ps2_io_write = (converted_address[15:4] == 12'h6) && converted_write;
assign ps2_io_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ ps2_sysctl ------------------------------------------------------
//------------------------------------------------------------------------------------
assign ps2_sysctl_address = converted_address[3:0];
assign ps2_sysctl_read = (converted_address[15:4] == 12'h9) && converted_read;
assign ps2_sysctl_write = (converted_address[15:4] == 12'h9) && converted_write;
assign ps2_sysctl_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ pit_io ----------------------------------------------------------
//------------------------------------------------------------------------------------
assign pit_io_address = converted_address[1:0];
assign pit_io_read = (converted_address[15:4] == 12'h4) && converted_read;
assign pit_io_write = (converted_address[15:4] == 12'h4) && converted_write;
assign pit_io_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ rtc_io ----------------------------------------------------------
//------------------------------------------------------------------------------------
assign rtc_io_address = converted_address[0];
assign rtc_io_read = (converted_address[15:4] == 12'h7) && converted_read;
assign rtc_io_write = (converted_address[15:4] == 12'h7) && converted_write;
assign rtc_io_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ pic_master ------------------------------------------------------
//------------------------------------------------------------------------------------
assign pic_master_address = converted_address[0];
assign pic_master_read = (converted_address[15:4] == 12'h2) && converted_read;
assign pic_master_write = (converted_address[15:4] == 12'h2) && converted_write;
assign pic_master_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ pic_slave -------------------------------------------------------
//------------------------------------------------------------------------------------
assign pic_slave_address = converted_address[0];
assign pic_slave_read = (converted_address[15:4] == 12'ha) && converted_read;
assign pic_slave_write = (converted_address[15:4] == 12'ha) && converted_write;
assign pic_slave_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ hdd_io ----------------------------------------------------------
//------------------------------------------------------------------------------------
assign hdd_io_address = ao486_avalon_io_address[2];
assign hdd_io_read = (ao486_avalon_io_address[15:4] == 12'h1f) && ao486_avalon_io_read;
assign hdd_io_write = (ao486_avalon_io_address[15:4] == 12'h1f) && ao486_avalon_io_write;
assign hdd_io_writedata = ao486_avalon_io_writedata;
assign hdd_io_byteenable = ao486_avalon_io_byteenable;
//------------------------------------------------------------------------------------
//------------------ ide_3f6 ---------------------------------------------------------
//------------------------------------------------------------------------------------
assign ide_3f6_read = (converted_address[15:0] == 16'h3f6) && converted_read;
assign ide_3f6_write = (converted_address[15:0] == 16'h3f6) && converted_write;
assign ide_3f6_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ error --------------------------------------------------------
//------------------------------------------------------------------------------------
wire error_read = converted_read &&
~(vga_io_b_read || vga_io_c_read || vga_io_d_read || ps2_io_read || ps2_sysctl_read ||
pit_io_read || rtc_io_read || pic_master_read || pic_slave_read ||
ide_3f6_read);
wire error_write = converted_write &&
~(vga_io_b_write || vga_io_c_write || vga_io_d_write || ps2_io_write || ps2_sysctl_write ||
pit_io_write || rtc_io_write || pic_master_write || pic_slave_write ||
ide_3f6_write);
wire error_cond = error_read || error_write;
always @(posedge clk_sys) error_rdvalid <= error_read;
endmodule
|
module sky130_fd_sc_lp__nand4b (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y , D, C, B, not0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
|
module counters_8bit_with_TD_ff_tb(
);
reg Clk, Enable, Clear;
wire [7:0] Q;
counters_8bit_with_TD_ff DUT (.Clk(Clk), .Enable(Enable), .Clear(Clear), .Q(Q));
initial begin
#500 $finish;
end
initial begin
Clk = 0; Enable = 0; Clear = 0;
#5 Clk = 1;
#5 Clk = 0; // 10ns
#5 Clk = 1;
#5 Clk = 0; Enable = 1;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0; Clear = 1;
#5 Clk = 1;
#5 Clk = 0; // 50ns
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0; // 90ns
#5 Clk = 1;
#5 Clk = 0; // 100ns
#5 Clk = 1;
#5 Clk = 0; // 110ns
#5 Clk = 1;
#5 Clk = 0; Enable = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0; // 150ns
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0; // 190ns
#5 Clk = 1;
#5 Clk = 0; Enable = 1;// 200ns
#5 Clk = 1;
#5 Clk = 0; // 210ns
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0; // 250ns
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0; // 290ns
#5 Clk = 1;
#5 Clk = 0; // 300ns
#5 Clk = 1;
#5 Clk = 0; // 310ns
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0; // 350ns
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0; // 390ns
#5 Clk = 1;
#5 Clk = 0; // 400ns
#5 Clk = 1;
#5 Clk = 0; // 410ns
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0; // 450ns
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0; // 490ns
#5 Clk = 1;
#5 Clk = 0; // 500ns
end
endmodule
|
module sim_artemis_ddr3 (
input ddr3_in_clk,
input rst,
output calibration_done,
output usr_clk,
output usr_rst,
inout [7:0] mcb3_dram_dq,
output [13:0] mcb3_dram_a,
output [2:0] mcb3_dram_ba,
output mcb3_dram_ras_n,
output mcb3_dram_cas_n,
output mcb3_dram_we_n,
output mcb3_dram_odt,
output mcb3_dram_reset_n,
output mcb3_dram_cke,
output mcb3_dram_dm,
inout mcb3_rzq,
inout mcb3_zio,
inout mcb3_dram_dqs,
inout mcb3_dram_dqs_n,
output mcb3_dram_ck,
output mcb3_dram_ck_n,
input p0_cmd_clk,
input p0_cmd_en,
input [2:0] p0_cmd_instr,
input [5:0] p0_cmd_bl,
input [29:0] p0_cmd_byte_addr,
output p0_cmd_empty,
output p0_cmd_full,
input p0_wr_clk,
input p0_wr_en,
input [3:0] p0_wr_mask,
input [31:0] p0_wr_data,
output p0_wr_full,
output p0_wr_empty,
output [6:0] p0_wr_count,
output p0_wr_underrun,
output p0_wr_error,
input p0_rd_clk,
input p0_rd_en,
output [31:0] p0_rd_data,
output p0_rd_full,
output p0_rd_empty,
output [6:0] p0_rd_count,
output p0_rd_overflow,
output p0_rd_error,
input p1_cmd_clk,
input p1_cmd_en,
input [2:0] p1_cmd_instr,
input [5:0] p1_cmd_bl,
input [29:0] p1_cmd_byte_addr,
output p1_cmd_empty,
output p1_cmd_full,
input p1_wr_clk,
input p1_wr_en,
input [3:0] p1_wr_mask,
input [31:0] p1_wr_data,
output p1_wr_full,
output p1_wr_empty,
output [6:0] p1_wr_count,
output p1_wr_underrun,
output p1_wr_error,
input p1_rd_clk,
input p1_rd_en,
output [31:0] p1_rd_data,
output p1_rd_full,
output p1_rd_empty,
output [6:0] p1_rd_count,
output p1_rd_overflow,
output p1_rd_error,
input p2_cmd_clk,
input p2_cmd_en,
input [2:0] p2_cmd_instr,
input [5:0] p2_cmd_bl,
input [29:0] p2_cmd_byte_addr,
output p2_cmd_empty,
output p2_cmd_full,
input p2_wr_clk,
input p2_wr_en,
input [3:0] p2_wr_mask,
input [31:0] p2_wr_data,
output p2_wr_full,
output p2_wr_empty,
output [6:0] p2_wr_count,
output p2_wr_underrun,
output p2_wr_error,
input p2_rd_clk,
input p2_rd_en,
output [31:0] p2_rd_data,
output p2_rd_full,
output p2_rd_empty,
output [6:0] p2_rd_count,
output p2_rd_overflow,
output p2_rd_error,
input p3_cmd_clk,
input p3_cmd_en,
input [2:0] p3_cmd_instr,
input [5:0] p3_cmd_bl,
input [29:0] p3_cmd_byte_addr,
output p3_cmd_empty,
output p3_cmd_full,
input p3_wr_clk,
input p3_wr_en,
input [3:0] p3_wr_mask,
input [31:0] p3_wr_data,
output p3_wr_full,
output p3_wr_empty,
output reg [6:0] p3_wr_count,
output reg p3_wr_underrun,
output reg p3_wr_error,
input p3_rd_clk,
input p3_rd_en,
output reg [31:0] p3_rd_data,
output p3_rd_full,
output p3_rd_empty,
output reg [6:0] p3_rd_count,
output reg p3_rd_overflow,
output reg p3_rd_error
);
//Local Parameters
localparam CMD_WRITE = 3'b000;
localparam CMD_READ = 3'b001;
localparam CMD_WRITE_PC = 3'b010;
localparam CMD_READ_PC = 3'b011;
localparam CMD_REFRESH = 3'b100;
//Registers/Wires
reg [23:0] write_data_count;
reg [23:0] cmd_count;
reg [23:0] read_data_count;
reg [23:0] write_timeout;
reg [23:0] cmd_timeout;
reg [23:0] read_timeout;
reg [23:0] read_data_size;
reg p3_cmd_error;
//Submodules
//Asynchronous Logic
assign p0_cmd_empty = 1;
assign p0_cmd_full = 0;
assign p0_wr_empty = 1;
assign p0_wr_full = 0;
assign p0_wr_count = 0;
assign p0_wr_underrun = 0;
assign p0_wr_error = 0;
assign p0_rd_data = 0;
assign p0_rd_full = 0;
assign p0_rd_empty = 1;
assign p0_rd_count = 0;
assign p0_rd_overflow = 0;
assign p0_rd_error = 0;
assign p1_cmd_empty = 1;
assign p1_cmd_full = 0;
assign p1_wr_empty = 1;
assign p1_wr_full = 0;
assign p1_wr_count = 0;
assign p1_wr_underrun = 0;
assign p1_wr_error = 0;
assign p1_rd_data = 0;
assign p1_rd_full = 0;
assign p1_rd_empty = 1;
assign p1_rd_count = 0;
assign p1_rd_overflow = 0;
assign p1_rd_error = 0;
assign p2_cmd_empty = 1;
assign p2_cmd_full = 0;
assign p2_wr_empty = 1;
assign p2_wr_full = 0;
assign p2_wr_count = 0;
assign p2_wr_underrun = 0;
assign p2_wr_error = 0;
assign p2_rd_data = 0;
assign p2_rd_full = 0;
assign p2_rd_empty = 1;
assign p2_rd_count = 0;
assign p2_rd_overflow = 0;
assign p2_rd_error = 0;
assign p3_wr_full = (write_data_count == 63);
assign p3_wr_empty = (write_data_count == 0);
assign p3_cmd_full = (cmd_count == 4);
assign p3_cmd_empty = (cmd_count == 0);
assign p3_rd_full = (read_data_count == 63);
assign p3_rd_empty = (read_data_count == 0);
//Synchronous Logic
parameter CFIFO_READ_DELAY = 20;
parameter WFIFO_READ_DELAY = 20;
parameter RFIFO_WRITE_DELAY = 10;
always @ (posedge p3_cmd_clk) begin
if (rst) begin
p3_wr_count <= 0;
p3_wr_underrun <= 0;
p3_wr_error <= 0;
p3_rd_data <= 0;
p3_rd_count <= 0;
p3_rd_overflow <= 0;
p3_rd_error <= 0;
p3_cmd_error <= 0;
cmd_count <= 0;
read_data_count <= 0;
write_data_count <= 0;
read_timeout <= RFIFO_WRITE_DELAY;
write_timeout <= WFIFO_READ_DELAY;
cmd_timeout <= CFIFO_READ_DELAY;
read_data_size <= 0;
end
else begin
//Command Stuff
if (p3_cmd_en && !p3_cmd_full) begin
if ((p3_cmd_instr == CMD_WRITE) || (p3_cmd_instr == CMD_WRITE_PC)) begin
if (write_data_count < p3_cmd_bl) begin
p3_wr_underrun <= 1;
end
end
else if ((p3_cmd_instr == CMD_READ) || (p3_cmd_instr == CMD_READ_PC)) begin
read_data_size <= p3_cmd_bl + 1;
end
cmd_count <= cmd_count + 1;
if (cmd_timeout == CFIFO_READ_DELAY) begin
cmd_timeout <= 0;
end
end
else if (p2_cmd_en && p2_cmd_full) begin
p3_cmd_error <= 1;
end
if (cmd_count > 0) begin
if (cmd_timeout < CFIFO_READ_DELAY) begin
cmd_timeout <= cmd_timeout + 1;
end
else begin
cmd_timeout <= 0;
cmd_count <= cmd_count - 1;
end
end
//Write Stuff
if ((write_data_count > 0) && (write_data_count < 64)) begin
if (write_timeout < WFIFO_READ_DELAY) begin
write_timeout <= write_timeout + 1;
end
else begin
write_timeout <= 0;
write_data_count <= write_data_count - 1;
end
end
if (p3_wr_en && !p3_wr_full) begin
write_data_count <= write_data_count + 1;
if (write_timeout == WFIFO_READ_DELAY) begin
write_timeout <= 0;
end
end
//Read Stuff
if (read_data_size > 0) begin
if (read_timeout < RFIFO_WRITE_DELAY) begin
read_timeout <= read_timeout + 1;
end
else begin
read_timeout <= 0;
read_data_size <= read_data_size - 1;
read_data_count <= read_data_count + 1;
end
end
if (read_data_count > 0) begin
if (p3_rd_en && !p3_rd_empty) begin
if (read_data_count > 0) begin
read_data_count <= read_data_count - 1;
p3_rd_data <= p3_rd_data + 1;
end
end
end
//Error Condition
if (p3_rd_en && p3_rd_empty) begin
p3_rd_error <= 1;
end
end
end
endmodule
|
module sdram_ctrl(
// system
input wire sysclk,
input wire c_7m,
input wire reset_in,
input wire cache_rst,
input wire cache_inhibit,
input wire [ 4-1:0] cpu_cache_ctrl,
output wire reset_out,
// sdram
output reg [ 13-1:0] sdaddr,
output reg [ 4-1:0] sd_cs,
output reg [ 2-1:0] ba,
output reg sd_we,
output reg sd_ras,
output reg sd_cas,
output reg [ 2-1:0] dqm,
inout wire [ 16-1:0] sdata,
// host
input wire [ 16-1:0] hostWR,
input wire [ 24-1:0] hostAddr,
input wire [ 3-1:0] hostState,
input wire hostL,
input wire hostU,
output reg [ 16-1:0] hostRD,
output wire hostena,
//input wire host_cs,
//input wire [ 24-1:0] host_adr,
//input wire host_we,
//input wire [ 2-1:0] host_bs,
//input wire [ 16-1:0] host_wdat,
//output reg [ 16-1:0] host_rdat,
//output wire host_ack,
// chip
input wire [23:1] chipAddr,
input wire chipL,
input wire chipU,
input wire chipRW,
input wire chip_dma,
input wire [ 16-1:0] chipWR,
output reg [ 16-1:0] chipRD,
output wire [ 48-1:0] chip48,
// cpu
input wire [24:1] cpuAddr,
input wire [ 6-1:0] cpustate,
input wire cpuL,
input wire cpuU,
input wire cpu_dma,
input wire [ 16-1:0] cpuWR,
output wire [ 16-1:0] cpuRD,
output reg enaWRreg,
output reg ena7RDreg,
output reg ena7WRreg,
output wire cpuena,
output reg enaRDreg
);
//// parameters ////
localparam [1:0]
nop = 0,
ras = 1,
cas = 2;
localparam [1:0]
WAITING = 0,
WRITE1 = 1,
WRITE2 = 2,
WRITE3 = 3;
localparam [2:0]
REFRESH = 0,
CHIP = 1,
CPU_READCACHE = 2,
CPU_WRITECACHE = 3,
HOST = 4,
IDLE = 5;
localparam [3:0]
ph0 = 0,
ph1 = 1,
ph2 = 2,
ph3 = 3,
ph4 = 4,
ph5 = 5,
ph6 = 6,
ph7 = 7,
ph8 = 8,
ph9 = 9,
ph10 = 10,
ph11 = 11,
ph12 = 12,
ph13 = 13,
ph14 = 14,
ph15 = 15;
//// local signals ////
reg [ 4-1:0] initstate;
reg [ 4-1:0] cas_sd_cs;
reg cas_sd_ras;
reg cas_sd_cas;
reg cas_sd_we;
reg [ 2-1:0] cas_dqm;
reg init_done;
wire [16-1:0] datain;
reg [16-1:0] datawr;
reg [25-1:0] casaddr;
reg sdwrite;
reg [16-1:0] sdata_reg;
wire [25-1:0] zmAddr;
reg zena;
reg [64-1:0] zcache;
reg [24-1:0] zcache_addr;
reg zcache_fill;
reg zcachehit;
reg [ 4-1:0] zvalid;
reg zequal;
reg [ 2-1:0] hostStated;
reg [16-1:0] hostRDd;
reg cena;
wire [64-1:0] ccache;
wire [25-1:0] ccache_addr;
wire ccache_fill;
wire ccachehit;
wire [ 4-1:0] cvalid;
wire cequal;
wire [ 2-1:0] cpuStated;
wire [16-1:0] cpuRDd;
wire [64-1:0] dcache;
wire [25-1:0] dcache_addr;
wire dcache_fill;
wire dcachehit;
wire [ 4-1:0] dvalid;
wire dequal;
reg [ 8-1:0] hostslot_cnt;
reg [ 8-1:0] reset_cnt;
reg reset;
reg reset_sdstate;
reg c_7md;
reg c_7mdd;
reg c_7mdr;
reg [ 9-1:0] refreshcnt;
reg refresh_pending;
reg [ 4-1:0] sdram_state;
wire [ 2-1:0] pass;
// writebuffer
reg [ 3-1:0] slot1_type = IDLE;
reg [ 3-1:0] slot2_type = IDLE;
reg [ 2-1:0] slot1_bank;
reg [ 2-1:0] slot2_bank;
wire cache_req;
wire readcache_fill;
reg cache_fill_1;
reg cache_fill_2;
reg [16-1:0] chip48_1;
reg [16-1:0] chip48_2;
reg [16-1:0] chip48_3;
reg writebuffer_req;
reg writebuffer_ena;
reg [ 2-1:0] writebuffer_dqm;
reg [25-1:1] writebufferAddr;
reg [16-1:0] writebufferWR;
reg [16-1:0] writebufferWR_reg;
wire writebuffer_cache_ack;
reg writebuffer_hold;
reg [ 2-1:0] writebuffer_state;
wire [25-1:1] cpuAddr_mangled;
////////////////////////////////////////
// address mangling
////////////////////////////////////////
// Let's try some bank-interleaving.
// For addresses in the upper 16 meg we shift bits around
// so that one bank bit comes from addr(3). This should allow
// bank interleaving to make things more efficient.
// Turns out this is counter-productive
//cpuAddr_mangled<=cpuAddr(24)&cpuAddr(3)&cpuAddr(22 downto 4)&cpuAddr(23)&cpuAddr(2 downto 1)
// when cpuAddr(24)='1' else cpuAddr;
assign cpuAddr_mangled = cpuAddr;
////////////////////////////////////////
// reset
////////////////////////////////////////
always @(posedge sysclk) begin
if(!reset_in) begin
reset_cnt <= #1 8'b00000000;
reset <= #1 1'b0;
reset_sdstate <= #1 1'b0;
end else begin
if(reset_cnt == 8'b00101010) begin
reset_sdstate <= #1 1'b1;
end
if(reset_cnt == 8'b10101010) begin
if(sdram_state == ph15) begin
reset <= #1 1'b1;
end
end else begin
reset_cnt <= #1 reset_cnt + 8'd1;
reset <= #1 1'b0;
end
end
end
assign reset_out = init_done;
////////////////////////////////////////
// host access
////////////////////////////////////////
assign hostena = zena || hostState[1:0] == 2'b01 || zcachehit ? 1'b1 : 1'b0;
// map host processor's address space to 0x400000
assign zmAddr = {2'b00, ~hostAddr[22], hostAddr[21:0]};
always @ (*) begin
zequal = (zmAddr[23:3] == zcache_addr[23:3]) ? 1'b1 : 1'b0;
zcachehit = 1'b0;
if(zequal && zvalid[0] && !hostStated[1]) begin
case ({hostAddr[2:1], zcache_addr[2:1]})
4'b0000,
4'b0101,
4'b1010,
4'b1111 : begin
zcachehit = zvalid[0];
hostRD = zcache[63:48];
end
4'b0100,
4'b1001,
4'b1110,
4'b0011 : begin
zcachehit = zvalid[1];
hostRD = zcache[47:32];
end
4'b1000,
4'b1101,
4'b0010,
4'b0111 : begin
zcachehit = zvalid[2];
hostRD = zcache[31:16];
end
4'b1100,
4'b0001,
4'b0110,
4'b1011 : begin
zcachehit = zvalid[3];
hostRD = zcache[15:0];
end
default : begin
end
endcase
end
else begin
hostRD = hostRDd;
end
end
//// host data read ////
always @ (posedge sysclk) begin
if(!reset) begin
zcache_fill <= #1 1'b0;
zena <= #1 1'b0;
zvalid <= #1 4'b0000;
end else begin
if(enaWRreg) begin
zena <= #1 1'b0;
end
if(sdram_state == ph9 && slot1_type == HOST) begin
hostRDd <= #1 sdata_reg;
end
if(sdram_state == ph11 && slot1_type == HOST) begin
zena <= #1 1'b1;
end
hostStated <= #1 hostState[1:0];
if(zequal && |hostState[1:0]) begin
zvalid <= #1 4'b0000;
end
case(sdram_state)
ph7 : begin
if(!hostStated[1] && slot1_type == HOST) begin // only instruction cache
zcache_addr <= #1 casaddr[23:0];
zcache_fill <= #1 1'b1;
zvalid <= #1 4'b0000;
end
end
ph9 : begin
if(zcache_fill) begin
zcache[63:48] <= #1 sdata_reg;
end
end
ph10 : begin
if(zcache_fill) begin
zcache[47:32] <= #1 sdata_reg;
end
end
ph11 : begin
if(zcache_fill) begin
zcache[31:16] <= #1 sdata_reg;
end
end
ph12 : begin
if(zcache_fill) begin
zcache[15:0] <= #1 sdata_reg;
zvalid <= #1 4'b1111;
end
zcache_fill <= #1 1'b0;
end
default : begin
end
endcase
end
end
////////////////////////////////////////
// cpu cache
////////////////////////////////////////
`define SDRAM_NEW_CACHE
`ifdef SDRAM_NEW_CACHE
wire snoop_act;
assign snoop_act = ((sdram_state==ph2)&&(!chipRW));
//// cpu cache ////
cpu_cache_new cpu_cache (
.clk (sysclk), // clock
.rst (!reset || !cache_rst), // cache reset
.cache_en (1'b1), // cache enable
.cpu_cache_ctrl (cpu_cache_ctrl), // CPU cache control
.cache_inhibit (cache_inhibit), // cache inhibit
.cpu_cs (!cpustate[2]), // cpu activity
.cpu_adr ({cpuAddr_mangled, 1'b0}), // cpu address
.cpu_bs ({!cpuU, !cpuL}), // cpu byte selects
.cpu_we (&cpustate[1:0]), // cpu write
.cpu_ir (!(|cpustate[1:0])), // cpu instruction read
.cpu_dr (cpustate[1] && !cpustate[0]), // cpu data read
.cpu_dat_w (cpuWR), // cpu write data
.cpu_dat_r (cpuRD), // cpu read data
.cpu_ack (ccachehit), // cpu acknowledge
.wb_en (writebuffer_cache_ack), // writebuffer enable
.sdr_dat_r (sdata_reg), // sdram read data
.sdr_read_req (cache_req), // sdram read request from cache
.sdr_read_ack (readcache_fill), // sdram read acknowledge to cache
.snoop_act (snoop_act), // snoop act (write only - just update existing data in cache)
.snoop_adr ({1'b0, chipAddr, 1'b0}), // snoop address
.snoop_dat_w (chipWR) // snoop write data
);
`else
//// cpu cache ////
TwoWayCache mytwc (
.clk (sysclk),
.reset (reset),
.cache_rst (cache_rst),
.ready (),
.cpu_addr ({7'b0000000, cpuAddr_mangled, 1'b0}),
.cpu_req (!cpustate[2]),
.cpu_ack (ccachehit),
.cpu_wr_ack (writebuffer_cache_ack),
.cpu_rw (!cpustate[1] || !cpustate[0]),
.cpu_rwl (cpuL),
.cpu_rwu (cpuU),
.data_from_cpu (cpuWR),
.data_to_cpu (cpuRD),
.sdram_addr (),
.data_from_sdram (sdata_reg),
.data_to_sdram (),
.sdram_req (cache_req),
.sdram_fill (readcache_fill),
.sdram_rw (),
.snoop_addr (20'bxxxxxxxxxxxxxxxxxxxx),
.snoop_req (1'bx)
);
`endif
//// writebuffer ////
// write buffer, enables CPU to continue while a write is in progress
always @ (posedge sysclk) begin
if(!reset) begin
writebuffer_req <= #1 1'b0;
writebuffer_ena <= #1 1'b0;
writebuffer_state <= #1 WAITING;
end else begin
case(writebuffer_state)
WAITING : begin
// CPU write cycle, no cycle already pending
if(cpustate[2:0] == 3'b011) begin
writebufferAddr <= #1 cpuAddr_mangled[24:1];
writebufferWR <= #1 cpuWR;
writebuffer_dqm <= #1 {cpuU, cpuL};
writebuffer_req <= #1 1'b1;
if(writebuffer_cache_ack) begin
writebuffer_ena <= #1 1'b1;
writebuffer_state <= #1 WRITE2;
end
end
end
WRITE2 : begin
if(writebuffer_hold) begin
// The SDRAM controller has picked up the request
writebuffer_req <= #1 1'b0;
writebuffer_state <= #1 WRITE3;
end
end
WRITE3 : begin
if(!writebuffer_hold) begin
// Wait for write cycle to finish, so it's safe to update the signals
writebuffer_state <= #1 WAITING;
end
end
default : begin
writebuffer_state <= #1 WAITING;
end
endcase
if(cpustate[2]) begin
// the CPU has unpaused, so clear the ack signal
writebuffer_ena <= #1 1'b0;
end
end
end
assign cpuena = cena || ccachehit || writebuffer_ena;
assign readcache_fill = (cache_fill_1 && slot1_type == CPU_READCACHE) || (cache_fill_2 && slot2_type == CPU_READCACHE);
//// chip line read ////
always @ (posedge sysclk) begin
if(slot1_type == CHIP) begin
case(sdram_state)
ph9 : chipRD <= #1 sdata_reg;
ph10 : chip48_1 <= #1 sdata_reg;
ph11 : chip48_2 <= #1 sdata_reg;
ph12 : chip48_3 <= #1 sdata_reg;
endcase
end
end
assign chip48 = {chip48_1, chip48_2, chip48_3};
////////////////////////////////////////
// SDRAM control
////////////////////////////////////////
//// clock mangling ////
// TODO this is some weird code - it's a 7MHz clock enable on 118MHz clock, used to 'reset' the sdram state machine, to state ph2 ???
always @ (negedge sysclk) begin
c_7md <= c_7m;
end
always @ (posedge sysclk) begin
c_7mdd <= c_7md;
c_7mdr <= c_7md & ~c_7mdd;
end
//// sdram data I/O ////
assign sdata = (sdwrite) ? datawr : 16'bzzzzzzzzzzzzzzzz;
//// read data reg ////
always @ (posedge sysclk) begin
sdata_reg <= #1 sdata;
end
//// write data reg ////
always @ (posedge sysclk) begin
if(sdram_state == ph2) begin
case(slot1_type)
CHIP : begin
datawr <= #1 chipWR;
end
CPU_WRITECACHE : begin
datawr <= #1 writebufferWR_reg;
end
default : begin
datawr <= #1 hostWR;
end
endcase
end else if(sdram_state == ph10) begin
case(slot2_type)
CHIP : begin
datawr <= #1 chipWR;
end
CPU_WRITECACHE : begin
datawr <= #1 writebufferWR_reg;
end
default : begin
datawr <= #1 hostWR;
end
endcase
end
end
//// write / read control ////
always @ (posedge sysclk) begin
if(!reset_sdstate) begin
sdwrite <= #1 1'b0;
enaRDreg <= #1 1'b0;
enaWRreg <= #1 1'b0;
ena7RDreg <= #1 1'b0;
ena7WRreg <= #1 1'b0;
end else begin
sdwrite <= #1 1'b0;
enaRDreg <= #1 1'b0;
enaWRreg <= #1 1'b0;
ena7RDreg <= #1 1'b0;
ena7WRreg <= #1 1'b0;
case(sdram_state) // LATENCY=3
ph2 : begin
enaWRreg <= #1 1'b1;
end
ph3 : begin
sdwrite <= #1 1'b1;
end
ph4 : begin
sdwrite <= #1 1'b1;
end
ph5 : begin
sdwrite <= #1 1'b1;
end
ph6 : begin
enaWRreg <= #1 1'b1;
ena7RDreg <= #1 1'b1;
end
ph10 : begin
enaWRreg <= #1 1'b1;
end
ph11 : begin
sdwrite <= #1 1'b1; // access slot 2
end
ph12 : begin
sdwrite <= #1 1'b1;
end
ph13 : begin
sdwrite <= #1 1'b1;
end
ph14 : begin
enaWRreg <= #1 1'b1;
ena7WRreg <= #1 1'b1;
end
default : begin
end
endcase
end
end
//// init counter ////
always @ (posedge sysclk) begin
if(!reset) begin
initstate <= #1 {4{1'b0}};
init_done <= #1 1'b0;
end else begin
case(sdram_state) // LATENCY=3
ph15 : begin
if(initstate != 4'b 1111) begin
initstate <= #1 initstate + 4'd1;
end else begin
init_done <= #1 1'b1;
end
end
default : begin
end
endcase
end
end
//// sdram state ////
always @ (posedge sysclk) begin
if(c_7mdr) begin
sdram_state <= #1 ph2;
end else begin
case(sdram_state) // LATENCY=3
ph0 : sdram_state <= #1 ph1;
ph1 : sdram_state <= #1 ph2;
ph2 : sdram_state <= #1 ph3;
ph3 : sdram_state <= #1 ph4;
ph4 : sdram_state <= #1 ph5;
ph5 : sdram_state <= #1 ph6;
ph6 : sdram_state <= #1 ph7;
ph7 : sdram_state <= #1 ph8;
ph8 : sdram_state <= #1 ph9;
ph9 : sdram_state <= #1 ph10;
ph10 : sdram_state <= #1 ph11;
ph11 : sdram_state <= #1 ph12;
ph12 : sdram_state <= #1 ph13;
ph13 : sdram_state <= #1 ph14;
ph14 : sdram_state <= #1 ph15;
default : sdram_state <= #1 ph0;
endcase
end
end
//// sdram control ////
// Address bits will be allocated as follows:
// 24 downto 23: bank
// 22 downto 10: row
// 9 downto 1: column
always @ (posedge sysclk) begin
if(!reset) begin
refresh_pending <= #1 1'b0;
slot1_type <= #1 IDLE;
slot2_type <= #1 IDLE;
end
sd_cs <= #1 4'b1111;
sd_ras <= #1 1'b1;
sd_cas <= #1 1'b1;
sd_we <= #1 1'b1;
sdaddr <= #1 13'bxxxxxxxxxxxxx;
ba <= #1 2'b00;
dqm <= #1 2'b00;
cache_fill_1 <= #1 1'b0;
cache_fill_2 <= #1 1'b0;
if(cpustate[5]) begin
cena <= 1'b0;
end
if(!init_done) begin
if(sdram_state == ph1) begin
case(initstate)
4'b0010 : begin // PRECHARGE
sdaddr[10] <= #1 1'b1; // all banks
sd_cs <= #1 4'b0000;
sd_ras <= #1 1'b0;
sd_cas <= #1 1'b1;
sd_we <= #1 1'b0;
end
4'b0011,
4'b0100,
4'b0101,
4'b0110,
4'b0111,
4'b1000,
4'b1001,
4'b1010,
4'b1011,
4'b1100 : begin // AUTOREFRESH
sd_cs <= #1 4'b0000;
sd_ras <= #1 1'b0;
sd_cas <= #1 1'b0;
sd_we <= #1 1'b1;
end
4'b1101 : begin // LOAD MODE REGISTER
sd_cs <= #1 4'b0000;
sd_ras <= #1 1'b0;
sd_cas <= #1 1'b0;
sd_we <= #1 1'b0;
//sdaddr <= #1 13'b0001000100010; // BURST=4 LATENCY=2
sdaddr <= #1 13'b0001000110010; // BURST=4 LATENCY=3
//sdaddr <= #1 13'b0001000110000; // noBURST LATENCY=3
end
default : begin
// NOP
end
endcase
end
end else begin
// Time slot control
case(sdram_state)
ph0 : begin
cache_fill_2 <= #1 1'b1; // slot 2
end
ph1 : begin
cache_fill_2 <= #1 1'b1; // slot 2
cas_sd_cs <= #1 4'b1110;
cas_sd_ras <= #1 1'b1;
cas_sd_cas <= #1 1'b1;
cas_sd_we <= #1 1'b1;
if(|hostslot_cnt) begin
hostslot_cnt <= #1 hostslot_cnt - 8'd1;
end
if(~|refreshcnt) begin
refresh_pending <= #1 1'b1;
end else begin
refreshcnt <= #1 refreshcnt - 9'd1;
end
// we give the chipset first priority
// (this includes anything on the "motherboard" - chip RAM, slow RAM and Kickstart, turbo modes notwithstanding)
if(!chip_dma || !chipRW) begin
slot1_type <= #1 CHIP;
sdaddr <= #1 chipAddr[22:10];
ba <= #1 2'b00; // always bank zero for chipset accesses, so we can interleave Fast RAM access
slot1_bank <= #1 2'b00;
cas_dqm <= #1 {chipU,chipL};
sd_cs <= #1 4'b1110; // ACTIVE
sd_ras <= #1 1'b0;
casaddr <= #1 {1'b0, chipAddr, 1'b0};
cas_sd_cas <= #1 1'b0;
cas_sd_we <= #1 chipRW;
end
// next in line is refresh
// (a refresh cycle blocks both access slots)
else if(refresh_pending && slot2_type == IDLE) begin
sd_cs <= #1 4'b0000; // AUTOREFRESH
sd_ras <= #1 1'b0;
sd_cas <= #1 1'b0;
refreshcnt <= #1 9'b111111111;
slot1_type <= #1 REFRESH;
refresh_pending <= #1 1'b0;
end
// the Amiga CPU gets next bite of the cherry, unless the OSD CPU has been cycle-starved
// request from write buffer
else if(writebuffer_req && (|hostslot_cnt || (hostState[2] || hostena)) && (slot2_type == IDLE || slot2_bank != writebufferAddr[24:23])) begin
// We only yield to the OSD CPU if it's both cycle-starved and ready to go.
slot1_type <= #1 CPU_WRITECACHE;
sdaddr <= #1 writebufferAddr[22:10];
ba <= #1 writebufferAddr[24:23];
slot1_bank <= #1 writebufferAddr[24:23];
cas_dqm <= #1 writebuffer_dqm;
sd_cs <= #1 4'b1110; // ACTIVE
sd_ras <= #1 1'b0;
casaddr <= #1 {writebufferAddr[24:1], 1'b0};
cas_sd_we <= #1 1'b0;
writebufferWR_reg <= #1 writebufferWR;
cas_sd_cas <= #1 1'b0;
writebuffer_hold <= #1 1'b1; // let the write buffer know we're about to write
end
// request from read cache
else if(cache_req && (|hostslot_cnt || (hostState[2] || hostena)) && (slot2_type == IDLE || slot2_bank != cpuAddr_mangled[24:23])) begin
// we only yield to the OSD CPU if it's both cycle-starved and ready to go
slot1_type <= #1 CPU_READCACHE;
sdaddr <= #1 cpuAddr_mangled[22:10];
ba <= #1 cpuAddr_mangled[24:23];
slot1_bank <= #1 cpuAddr_mangled[24:23];
cas_dqm <= #1 {cpuU,cpuL};
sd_cs <= #1 4'b1110; // ACTIVE
sd_ras <= #1 1'b0;
casaddr <= #1 {cpuAddr_mangled[24:1], 1'b0};
cas_sd_we <= #1 1'b1;
cas_sd_cas <= #1 1'b0;
end
else if(!hostState[2] && !hostena) begin
hostslot_cnt <= #1 8'b00001111;
slot1_type <= #1 HOST;
sdaddr <= #1 zmAddr[22:10];
ba <= #1 2'b00;
// Always bank zero for SPI host CPU
slot1_bank <= #1 2'b00;
cas_dqm <= #1 {hostU,hostL};
sd_cs <= #1 4'b1110;
// ACTIVE
sd_ras <= #1 1'b0;
casaddr <= #1 zmAddr;
cas_sd_cas <= #1 1'b0;
if(hostState == 3'b011) begin
cas_sd_we <= #1 1'b0;
end
end
else begin
slot1_type <= #1 IDLE;
end
end
ph2 : begin
// slot 2
cache_fill_2 <= #1 1'b1;
end
ph3 : begin
// slot 2
cache_fill_2 <= #1 1'b1;
end
ph4 : begin
sdaddr <= #1 {1'b0, 1'b0, 1'b1, 1'b0, casaddr[9:1]}; // AUTO PRECHARGE
ba <= #1 casaddr[24:23];
sd_cs <= #1 cas_sd_cs;
if(!cas_sd_we) begin
dqm <= #1 cas_dqm;
end
sd_ras <= #1 cas_sd_ras;
sd_cas <= #1 cas_sd_cas;
sd_we <= #1 cas_sd_we;
writebuffer_hold <= #1 1'b0; // indicate to WriteBuffer that it's safe to accept the next write
end
ph8 : begin
cache_fill_1 <= #1 1'b1;
end
ph9 : begin
cache_fill_1 <= #1 1'b1;
// Access slot 2, RAS
cas_sd_cs <= #1 4'b1110;
cas_sd_ras <= #1 1'b1;
cas_sd_cas <= #1 1'b1;
cas_sd_we <= #1 1'b1;
slot2_type <= #1 IDLE;
if(!refresh_pending && slot1_type != REFRESH) begin
if(writebuffer_req && |writebufferAddr[24:23] && (slot1_type == IDLE || slot1_bank != writebufferAddr[24:23])) begin // reserve bank 0 for slot 1
// We only yield to the OSD CPU if it's both cycle-starved and ready to go.
slot2_type <= #1 CPU_WRITECACHE;
sdaddr <= #1 writebufferAddr[22:10];
ba <= #1 writebufferAddr[24:23];
slot2_bank <= #1 writebufferAddr[24:23];
cas_dqm <= #1 writebuffer_dqm;
sd_cs <= #1 4'b1110; // ACTIVE
sd_ras <= #1 1'b0;
casaddr <= #1 {writebufferAddr[24:1], 1'b0};
cas_sd_we <= #1 1'b0;
writebufferWR_reg <= #1 writebufferWR;
cas_sd_cas <= #1 1'b0;
writebuffer_hold <= #1 1'b1; // let the write buffer know we're about to write
end
// request from read cache
else if(cache_req && |cpuAddr[24:23] && (slot1_type == IDLE || slot1_bank != cpuAddr_mangled[24:23])) begin // reserve bank 0 for slot 1
slot2_type <= #1 CPU_READCACHE;
sdaddr <= #1 cpuAddr_mangled[22:10];
ba <= #1 cpuAddr_mangled[24:23];
slot2_bank <= #1 cpuAddr_mangled[24:23];
cas_dqm <= #1 {cpuU, cpuL};
sd_cs <= #1 4'b1110; // ACTIVE
sd_ras <= #1 1'b0;
casaddr <= #1 {cpuAddr_mangled[24:1], 1'b0};
cas_sd_we <= #1 1'b1;
cas_sd_cas <= #1 1'b0;
end
end
end
ph10 : begin
cache_fill_1 <= #1 1'b1;
end
ph11 : begin
cache_fill_1 <= #1 1'b1;
end
// slot 2 CAS
ph12 : begin
sdaddr <= #1 {1'b0, 1'b0, 1'b1, 1'b0, casaddr[9:1]}; // AUTO PRECHARGE
ba <= #1 casaddr[24:23];
sd_cs <= #1 cas_sd_cs;
if(!cas_sd_we) begin
dqm <= #1 cas_dqm;
end
sd_ras <= #1 cas_sd_ras;
sd_cas <= #1 cas_sd_cas;
sd_we <= #1 cas_sd_we;
writebuffer_hold <= #1 1'b0; // indicate to WriteBuffer that it's safe to accept the next write
end
default : begin
end
endcase
end
end
//// slots ////
// Slot 1 Slot 2
// ph0 (read) (Read 0 in sdata)
// ph1 Slot alloc, RAS (read) Read0
// ph2 ... (read) Read1
// ph3 ... (write) Read2 (read3 in sdata)
// ph4 CAS, write0 (write) Read3
// ph5 write1 (write)
// ph6 write2 (write)
// ph7 write3 (read)
// ph8 (read0 in sdata) (rd)
// ph9 read0 in sdata_reg (rd) Slot alloc, RAS
// ph10 read1 (read) ...
// ph11 read2 (rd3 in sdata, wr) ...
// ph12 read3 (write) CAS, write 0
// ph13 (write) write1
// ph14 (write) write2
// ph15 (read) write3
endmodule
|
module sky130_fd_sc_hdll__a31oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
|
module alu_control(
input [5:0] ALUOp,
input [5:0] funct,
output wire [3:0] ALUcontrolOut
);
assign ALUcontrolOut = (ALUOp == 6'b000100) ? 4'b0001 : //SUB para BEQ
(ALUOp == 6'b000101) ? 4'b0001 : //SUB para BNE
(ALUOp == 6'b001000) ? 4'b0000 : //ADDI
(ALUOp == 6'b001010) ? 4'b0110 : //SLTI
(ALUOp == 6'b001100) ? 4'b0010 : //ANDI
(ALUOp == 6'b001101) ? 4'b0011 : //ORI
(ALUOp == 6'b001110) ? 4'b0100 : //XORI
(ALUOp == 6'b001111) ? 4'b1101 : //LUI
(ALUOp == 6'b100000) ? 4'b0000 : //ADD para LB
(ALUOp == 6'b100001) ? 4'b0000 : //ADD para LH
(ALUOp == 6'b100011) ? 4'b0000 : //ADD para LW
(ALUOp == 6'b100100) ? 4'b0000 : //ADD para LBU
(ALUOp == 6'b100101) ? 4'b0000 : //ADD para LHU
(ALUOp == 6'b100111) ? 4'b0000 : //ADD para LWU
(ALUOp == 6'b101000) ? 4'b0000 : //ADD para SB
(ALUOp == 6'b101001) ? 4'b0000 : //ADD para SH
(ALUOp == 6'b101011) ? 4'b0000 : //ADD para SW
(ALUOp == 6'b000011) ? 4'b0000 : //ADD para JAL
( (funct == 6'b100000) ? 4'b0000 : //ADD
(funct == 6'b100010) ? 4'b0001 : //SUB
(funct == 6'b100100) ? 4'b0010 : //AND
(funct == 6'b100101) ? 4'b0011 : //OR
(funct == 6'b100110) ? 4'b0100 : //XOR
(funct == 6'b100111) ? 4'b0101 : //NOR
(funct == 6'b101010) ? 4'b0110 : //SLT
(funct == 6'b000000) ? 4'b0111 : //SLL
(funct == 6'b000010) ? 4'b1000 : //SRL
(funct == 6'b000011) ? 4'b1001 : //SRA
(funct == 6'b000100) ? 4'b1010 : //SLLV
(funct == 6'b000110) ? 4'b1011 : //SRLV
(funct == 6'b000111) ? 4'b1100 : //SRAV
(funct == 6'b001001) ? 4'b0000 : //ADD para JALR
4'b1111); // --> Para identificar errores
endmodule
|
module sky130_fd_sc_hdll__muxb4to1 (
Z,
D,
S
);
// Module ports
output Z;
input [3:0] D;
input [3:0] S;
// Name Output Other arguments
bufif1 bufif10 (Z , !D[0], S[0] );
bufif1 bufif11 (Z , !D[1], S[1] );
bufif1 bufif12 (Z , !D[2], S[2] );
bufif1 bufif13 (Z , !D[3], S[3] );
endmodule
|
module fpu_div_frac_dp (
inq_in1,
inq_in2,
d1stg_step,
div_norm_frac_in1_dbl_norm,
div_norm_frac_in1_dbl_dnrm,
div_norm_frac_in1_sng_norm,
div_norm_frac_in1_sng_dnrm,
div_norm_frac_in2_dbl_norm,
div_norm_frac_in2_dbl_dnrm,
div_norm_frac_in2_sng_norm,
div_norm_frac_in2_sng_dnrm,
div_norm_inf,
div_norm_qnan,
d1stg_dblop,
div_norm_zero,
d1stg_snan_dbl_in1,
d1stg_snan_sng_in1,
d1stg_snan_dbl_in2,
d1stg_snan_sng_in2,
d3stg_fdiv,
d6stg_fdiv,
d6stg_fdivd,
d6stg_fdivs,
div_frac_add_in2_load,
d6stg_frac_out_shl1,
d6stg_frac_out_nosh,
d4stg_fdiv,
div_frac_add_in1_add,
div_frac_add_in1_load,
d5stg_fdivb,
div_frac_out_add_in1,
div_frac_out_add,
div_frac_out_shl1_dbl,
div_frac_out_shl1_sng,
div_frac_out_of,
d7stg_to_0,
div_frac_out_load,
fdiv_clken_l,
rclk,
div_shl_cnt,
d6stg_frac_0,
d6stg_frac_1,
d6stg_frac_2,
d6stg_frac_29,
d6stg_frac_30,
d6stg_frac_31,
div_frac_add_in1_neq_0,
div_frac_add_52_inv,
div_frac_add_52_inva,
div_frac_out_54_53,
div_frac_outa,
se,
si,
so
);
input [54:0] inq_in1; // request operand 1 to op pipes
input [54:0] inq_in2; // request operand 2 to op pipes
input d1stg_step; // divide pipe load
input div_norm_frac_in1_dbl_norm; // select line to div_norm
input div_norm_frac_in1_dbl_dnrm; // select line to div_norm
input div_norm_frac_in1_sng_norm; // select line to div_norm
input div_norm_frac_in1_sng_dnrm; // select line to div_norm
input div_norm_frac_in2_dbl_norm; // select line to div_norm
input div_norm_frac_in2_dbl_dnrm; // select line to div_norm
input div_norm_frac_in2_sng_norm; // select line to div_norm
input div_norm_frac_in2_sng_dnrm; // select line to div_norm
input div_norm_inf; // select line to div_norm
input div_norm_qnan; // select line to div_norm
input d1stg_dblop; // double precision operation- d1 stg
input div_norm_zero; // select line to div_norm
input d1stg_snan_dbl_in1; // operand 1 is double signalling NaN
input d1stg_snan_sng_in1; // operand 1 is single signalling NaN
input d1stg_snan_dbl_in2; // operand 2 is double signalling NaN
input d1stg_snan_sng_in2; // operand 2 is single signalling NaN
input d3stg_fdiv; // divide operation- divide stage 3
input d6stg_fdiv; // divide operation- divide stage 6
input d6stg_fdivd; // divide double- divide stage 6
input d6stg_fdivs; // divide single- divide stage 6
input div_frac_add_in2_load; // load enable to div_frac_add_in2
input d6stg_frac_out_shl1; // select line to d6stg_frac
input d6stg_frac_out_nosh; // select line to d6stg_frac
input d4stg_fdiv; // divide operation- divide stage 4
input div_frac_add_in1_add; // select line to div_frac_add_in1
input div_frac_add_in1_load; // load enable to div_frac_add_in1
input d5stg_fdivb; // divide operation- divide stage 5
input div_frac_out_add_in1; // select line to div_frac_out
input div_frac_out_add; // select line to div_frac_out
input div_frac_out_shl1_dbl; // select line to div_frac_out
input div_frac_out_shl1_sng; // select line to div_frac_out
input div_frac_out_of; // select line to div_frac_out
input d7stg_to_0; // result to max finite on overflow
input div_frac_out_load; // load enable to div_frac_out
input fdiv_clken_l; // div pipe clk enable - asserted low
input rclk; // global clock
output [5:0] div_shl_cnt; // divide left shift amount
output d6stg_frac_0; // divide fraction[0]- intermediate val
output d6stg_frac_1; // divide fraction[1]- intermediate val
output d6stg_frac_2; // divide fraction[2]- intermediate val
output d6stg_frac_29; // divide fraction[29]- intermediate val
output d6stg_frac_30; // divide fraction[30]- intermediate val
output d6stg_frac_31; // divide fraction[31]- intermediate val
output div_frac_add_in1_neq_0; // div_frac_add_in1 != 0
output div_frac_add_52_inv; // div_frac_add bit[52] inverted
output div_frac_add_52_inva; // div_frac_add bit[52] inverted copy
output [1:0] div_frac_out_54_53; // divide fraction output
output [51:0] div_frac_outa; // divide fraction output- buffered copy
input se; // scan_enable
input si; // scan in
output so; // scan out
wire [54:0] div_frac_in1;
wire [54:0] div_frac_in2;
wire [52:0] div_norm_inv_in;
wire [52:0] div_norm_inv;
wire [52:0] div_norm;
wire [5:0] div_lead0;
wire [5:0] div_shl_cnt;
wire [5:0] div_shl_cnta;
wire [52:0] div_shl_data;
wire [105:53] div_shl_tmp;
wire [52:0] div_shl;
wire [54:0] div_shl_save;
wire [54:0] div_frac_add_in2_in;
wire [54:0] div_frac_add_in2;
wire [53:0] d6stg_frac;
wire d6stg_frac_0;
wire d6stg_frac_1;
wire d6stg_frac_2;
wire d6stg_frac_29;
wire d6stg_frac_30;
wire d6stg_frac_31;
wire [54:0] div_frac_add_in1_in;
wire [54:0] div_frac_add_in1;
wire [54:0] div_frac_add_in1a;
wire div_frac_add_in1_neq_0;
wire [54:0] div_frac_add;
wire div_frac_add_52_inv;
wire div_frac_add_52_inva;
wire [54:0] div_frac_out_in;
wire [1:0] div_frac_out_54_53;
wire [54:0] div_frac_out;
wire [51:0] div_frac_outa;
wire se_l;
assign se_l = ~se;
clken_buf ckbuf_div_frac_dp (
.clk(clk),
.rclk(rclk),
.enb_l(fdiv_clken_l),
.tmb_l(se_l)
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide fraction inputs.
//
///////////////////////////////////////////////////////////////////////////////
dffe #(55) i_div_frac_in1 (
.din (inq_in1[54:0]),
.en (d1stg_step),
.clk (clk),
.q (div_frac_in1[54:0]),
.se (se),
.si (),
.so ()
);
dffe #(55) i_div_frac_in2 (
.din (inq_in2[54:0]),
.en (d1stg_step),
.clk (clk),
.q (div_frac_in2[54:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide normalization and special input injection.
//
///////////////////////////////////////////////////////////////////////////////
assign div_norm_inv_in[52:0]= (~(({53{div_norm_frac_in1_dbl_norm}}
& {1'b1, (div_frac_in1[51] || d1stg_snan_dbl_in1),
div_frac_in1[50:0]})
| ({53{div_norm_frac_in1_dbl_dnrm}}
& {div_frac_in1[51:0], 1'b0})
| ({53{div_norm_frac_in1_sng_norm}}
& {1'b1, (div_frac_in1[54] || d1stg_snan_sng_in1),
div_frac_in1[53:32], 29'b0})
| ({53{div_norm_frac_in1_sng_dnrm}}
& {div_frac_in1[54:32], 30'b0})
| ({53{div_norm_frac_in2_dbl_norm}}
& {1'b1, (div_frac_in2[51] || d1stg_snan_dbl_in2),
div_frac_in2[50:0]})
| ({53{div_norm_frac_in2_dbl_dnrm}}
& {div_frac_in2[51:0], 1'b0})
| ({53{div_norm_frac_in2_sng_norm}}
& {1'b1, (div_frac_in2[54] || d1stg_snan_sng_in2),
div_frac_in2[53:32], 29'b0})
| ({53{div_norm_frac_in2_sng_dnrm}}
& {div_frac_in2[54:32], 30'b0})
| ({53{div_norm_inf}}
& 53'h10000000000000)
| ({53{div_norm_qnan}}
& {24'hffffff, {29{d1stg_dblop}}})
| ({53{div_norm_zero}}
& 53'h00000000000000)));
dff #(53) i_div_norm_inv (
.din (div_norm_inv_in[52:0]),
.clk (clk),
.q (div_norm_inv[52:0]),
.se (se),
.si (),
.so ()
);
assign div_norm[52:0]= (~div_norm_inv);
///////////////////////////////////////////////////////////////////////////////
//
// Divide lead zero count.
//
///////////////////////////////////////////////////////////////////////////////
fpu_cnt_lead0_53b i_div_lead0 (
.din (div_norm[52:0]),
.lead0 (div_lead0[5:0])
);
dff #12 i_dstg_xtra_regs (
.din ({div_lead0[5:0], div_lead0[5:0]}),
.clk (clk),
.q ({div_shl_cnta[5:0], div_shl_cnt[5:0]}),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide left shift.
//
///////////////////////////////////////////////////////////////////////////////
dff #(53) i_div_shl_data (
.din (div_norm[52:0]),
.clk (clk),
.q (div_shl_data[52:0]),
.se (se),
.si (),
.so ()
);
//assign div_shl_tmp[105:0]= {div_shl_data[52:0], 53'b0} << div_shl_cnta[5:0];
assign div_shl_tmp[105:53]= div_shl_data[52:0] << div_shl_cnta[5:0];
assign div_shl[52:0]= div_shl_tmp[105:53];
dffe #(55) i_div_shl_save (
.din ({2'b0, div_shl[52:0]}),
.en (d3stg_fdiv),
.clk (clk),
.q (div_shl_save[54:0]),
.se (se),
.si (),
.so ()
);
assign div_frac_add_in2_in[54:0]= ({55{d4stg_fdiv}}
& (~{2'b0, div_shl[52:0]}))
| ({55{d6stg_fdiv}}
& {25'b0, d6stg_fdivs, 28'b0, d6stg_fdivd});
dffe #(55) i_div_frac_add_in2 (
.din (div_frac_add_in2_in[54:0]),
.en (div_frac_add_in2_load),
.clk (clk),
.q (div_frac_add_in2[54:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide adder/subtractor 2nd input.
//
///////////////////////////////////////////////////////////////////////////////
assign d6stg_frac[53:0]= ({54{d6stg_frac_out_shl1}}
& {div_frac_out[52:0], 1'b0})
| ({54{d6stg_frac_out_nosh}}
& div_frac_out[53:0]);
assign d6stg_frac_0= d6stg_frac[0];
assign d6stg_frac_1= d6stg_frac[1];
assign d6stg_frac_2= d6stg_frac[2];
assign d6stg_frac_29= d6stg_frac[29];
assign d6stg_frac_30= d6stg_frac[30];
assign d6stg_frac_31= d6stg_frac[31];
assign div_frac_add_in1_in[54:0]= ({55{d4stg_fdiv}}
& div_shl_save[54:0])
| ({55{(div_frac_add_in1_add && (!div_frac_add[54]))}}
& {div_frac_add[53:0], 1'b0})
| ({55{(div_frac_add_in1_add && div_frac_add[54])}}
& {div_frac_add_in1[53:0], 1'b0})
| ({55{d6stg_fdiv}}
& {3'b0, d6stg_frac[53:31],
(d6stg_frac[30:2] & {29{d6stg_fdivd}})});
dffe #(55) i_div_frac_add_in1 (
.din (div_frac_add_in1_in[54:0]),
.en (div_frac_add_in1_load),
.clk (clk),
.q (div_frac_add_in1[54:0]),
.se (se),
.si (),
.so ()
);
dffe #(55) i_div_frac_add_in1a (
.din (div_frac_add_in1_in[54:0]),
.en (div_frac_add_in1_load),
.clk (clk),
.q (div_frac_add_in1a[54:0]),
.se (se),
.si (),
.so ()
);
assign div_frac_add_in1_neq_0= (|div_frac_add_in1[54:0]);
///////////////////////////////////////////////////////////////////////////////
//
// Divide adder/subtractor.
//
///////////////////////////////////////////////////////////////////////////////
assign div_frac_add[54:0]= (div_frac_add_in1a[54:0]
+ div_frac_add_in2[54:0]
+ {54'b0, d5stg_fdivb});
assign div_frac_add_52_inv= (!div_frac_add[52]);
assign div_frac_add_52_inva= (!div_frac_add[52]);
assign div_frac_out_in[54:0]= ({55{d4stg_fdiv}}
& 55'b0)
| ({55{div_frac_out_add_in1}}
& div_frac_add_in1[54:0])
| ({55{div_frac_out_add}}
& div_frac_add[54:0])
| ({55{div_frac_out_shl1_dbl}}
& {div_frac_out[53:0], (!div_frac_add[54])})
| ({55{div_frac_out_shl1_sng}}
& {div_frac_out[53:29], (!div_frac_add[54]), 29'b0})
| ({55{div_frac_out_of}}
& {55{d7stg_to_0}});
dffe #(55) i_div_frac_out (
.din (div_frac_out_in[54:0]),
.en (div_frac_out_load),
.clk (clk),
.q (div_frac_out[54:0]),
.se (se),
.si (),
.so ()
);
assign div_frac_out_54_53[1:0] = div_frac_out[54:53];
assign div_frac_outa[51:0]= div_frac_out[51:0];
endmodule
|
module tx_multiplexer_128
#(
parameter C_PCI_DATA_WIDTH = 128,
parameter C_NUM_CHNL = 12,
parameter C_TAG_WIDTH = 5, // Number of outstanding requests
parameter C_VENDOR = "ALTERA"
)
(
input CLK,
input RST_IN,
input [C_NUM_CHNL-1:0] WR_REQ, // Write request
input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] WR_ADDR, // Write address
input [(C_NUM_CHNL*`SIG_LEN_W)-1:0] WR_LEN, // Write data length
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] WR_DATA, // Write data
output [C_NUM_CHNL-1:0] WR_DATA_REN, // Write data read enable
output [C_NUM_CHNL-1:0] WR_ACK, // Write request has been accepted
input [C_NUM_CHNL-1:0] RD_REQ, // Read request
input [(C_NUM_CHNL*2)-1:0] RD_SG_CHNL, // Read request channel for scatter gather lists
input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] RD_ADDR, // Read request address
input [(C_NUM_CHNL*`SIG_LEN_W)-1:0] RD_LEN, // Read request length
output [C_NUM_CHNL-1:0] RD_ACK, // Read request has been accepted
output [5:0] INT_TAG, // Internal tag to exchange with external
output INT_TAG_VALID, // High to signal tag exchange
input [C_TAG_WIDTH-1:0] EXT_TAG, // External tag to provide in exchange for internal tag
input EXT_TAG_VALID, // High to signal external tag is valid
output TX_ENG_RD_REQ_SENT, // Read completion request issued
input RXBUF_SPACE_AVAIL,
// Interface: TXR Engine
output TXR_DATA_VALID,
output [C_PCI_DATA_WIDTH-1:0] TXR_DATA,
output TXR_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
output TXR_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
input TXR_DATA_READY,
output TXR_META_VALID,
output [`SIG_FBE_W-1:0] TXR_META_FDWBE,
output [`SIG_LBE_W-1:0] TXR_META_LDWBE,
output [`SIG_ADDR_W-1:0] TXR_META_ADDR,
output [`SIG_LEN_W-1:0] TXR_META_LENGTH,
output [`SIG_TAG_W-1:0] TXR_META_TAG,
output [`SIG_TC_W-1:0] TXR_META_TC,
output [`SIG_ATTR_W-1:0] TXR_META_ATTR,
output [`SIG_TYPE_W-1:0] TXR_META_TYPE,
output TXR_META_EP,
input TXR_META_READY);
localparam C_DATA_DELAY = 6;
reg rMainState=`S_TXENGUPR128_MAIN_IDLE, _rMainState=`S_TXENGUPR128_MAIN_IDLE;
reg rCountIsWr=0, _rCountIsWr=0;
reg [9:0] rCountLen=0, _rCountLen=0;
reg [3:0] rCountChnl=0, _rCountChnl=0;
reg [C_TAG_WIDTH-1:0] rCountTag=0, _rCountTag=0;
reg [61:0] rCountAddr=62'd0, _rCountAddr=62'd0;
reg rCountAddr64=0, _rCountAddr64=0;
reg [9:0] rCount=0, _rCount=0;
reg rCountDone=0, _rCountDone=0;
reg rCountStart=0, _rCountStart=0;
reg rCountValid=0, _rCountValid=0;
reg [C_NUM_CHNL-1:0] rWrDataRen=0, _rWrDataRen=0;
reg rTxEngRdReqAck, _rTxEngRdReqAck;
wire wRdReq;
wire [3:0] wRdReqChnl;
wire wWrReq;
wire [3:0] wWrReqChnl;
wire wRdAck;
wire [3:0] wCountChnl;
wire [11:0] wCountChnlShiftDW = (wCountChnl*C_PCI_DATA_WIDTH); // Mult can exceed 9 bits, so make this a wire
wire [63:0] wRdAddr;
wire [9:0] wRdLen;
wire [1:0] wRdSgChnl;
wire [63:0] wWrAddr;
wire [9:0] wWrLen;
wire [C_PCI_DATA_WIDTH-1:0] wWrData;
wire [C_PCI_DATA_WIDTH-1:0] wWrDataSwap;
reg [3:0] rRdChnl=0, _rRdChnl=0;
reg [61:0] rRdAddr=62'd0, _rRdAddr=62'd0;
reg [9:0] rRdLen=0, _rRdLen=0;
reg [1:0] rRdSgChnl=0, _rRdSgChnl=0;
reg [3:0] rWrChnl=0, _rWrChnl=0;
reg [61:0] rWrAddr=62'd0, _rWrAddr=62'd0;
reg [9:0] rWrLen=0, _rWrLen=0;
reg [C_PCI_DATA_WIDTH-1:0] rWrData={C_PCI_DATA_WIDTH{1'd0}}, _rWrData={C_PCI_DATA_WIDTH{1'd0}};
assign wRdAddr = RD_ADDR[wRdReqChnl * `SIG_ADDR_W +: `SIG_ADDR_W];
assign wRdLen = RD_LEN[wRdReqChnl * `SIG_LEN_W +: `SIG_LEN_W];
assign wRdSgChnl = RD_SG_CHNL[wRdReqChnl * 2 +: 2];
assign wWrAddr = WR_ADDR[wWrReqChnl * `SIG_ADDR_W +: `SIG_ADDR_W];
assign wWrLen = WR_LEN[wWrReqChnl * `SIG_LEN_W +: `SIG_LEN_W];
assign wWrData = WR_DATA[wCountChnl * C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [3:0] rCapState=`S_TXENGUPR128_CAP_RD_WR, _rCapState=`S_TXENGUPR128_CAP_RD_WR;
reg [C_NUM_CHNL-1:0] rRdAck=0, _rRdAck=0;
reg [C_NUM_CHNL-1:0] rWrAck=0, _rWrAck=0;
reg rIsWr=0, _rIsWr=0;
reg [5:0] rCapChnl=0, _rCapChnl=0;
reg [61:0] rCapAddr=62'd0, _rCapAddr=62'd0;
reg rCapAddr64=0, _rCapAddr64=0;
reg [9:0] rCapLen=0, _rCapLen=0;
reg rCapIsWr=0, _rCapIsWr=0;
reg rExtTagReq=0, _rExtTagReq=0;
reg [C_TAG_WIDTH-1:0] rExtTag=0, _rExtTag=0;
reg [C_DATA_DELAY-1:0] rWnR=0, _rWnR=0;
reg [(C_DATA_DELAY*4)-1:0] rChnl=0, _rChnl=0;
reg [(C_DATA_DELAY*8)-1:0] rTag=0, _rTag=0;
reg [(C_DATA_DELAY*62)-1:0] rAddr=0, _rAddr=0;
reg [C_DATA_DELAY-1:0] rAddr64=0, _rAddr64=0;
reg [(C_DATA_DELAY*10)-1:0] rLen=0, _rLen=0;
reg [C_DATA_DELAY-1:0] rLenEQ1=0, _rLenEQ1=0;
reg [C_DATA_DELAY-1:0] rValid=0, _rValid=0;
reg [C_DATA_DELAY-1:0] rDone=0, _rDone=0;
reg [C_DATA_DELAY-1:0] rStart=0, _rStart=0;
assign WR_DATA_REN = rWrDataRen;
assign WR_ACK = rWrAck;
assign RD_ACK = rRdAck;
assign INT_TAG = {rRdSgChnl, rRdChnl};
assign INT_TAG_VALID = rExtTagReq;
assign TX_ENG_RD_REQ_SENT = rTxEngRdReqAck;
assign wRdAck = (wRdReq & EXT_TAG_VALID & RXBUF_SPACE_AVAIL);
// Search for the next request so that we can move onto it immediately after
// the current channel has released its request.
tx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selRd (.RST(RST_IN), .CLK(CLK), .REQ_ALL(RD_REQ), .REQ(wRdReq), .CHNL(wRdReqChnl));
tx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selWr (.RST(RST_IN), .CLK(CLK), .REQ_ALL(WR_REQ), .REQ(wWrReq), .CHNL(wWrReqChnl));
// Buffer shift-selected channel request signals and FIFO data.
always @ (posedge CLK) begin
rRdChnl <= #1 _rRdChnl;
rRdAddr <= #1 _rRdAddr;
rRdLen <= #1 _rRdLen;
rRdSgChnl <= #1 _rRdSgChnl;
rWrChnl <= #1 _rWrChnl;
rWrAddr <= #1 _rWrAddr;
rWrLen <= #1 _rWrLen;
rWrData <= #1 _rWrData;
end
always @ (*) begin
_rRdChnl = wRdReqChnl;
_rRdAddr = wRdAddr[63:2];
_rRdLen = wRdLen;
_rRdSgChnl = wRdSgChnl;
_rWrChnl = wWrReqChnl;
_rWrAddr = wWrAddr[63:2];
_rWrLen = wWrLen;
_rWrData = wWrData;
end
// Accept requests when the selector indicates. Capture the buffered
// request parameters for hand-off to the formatting pipeline. Then
// acknowledge the receipt to the channel so it can deassert the
// request, and let the selector choose another channel.
always @ (posedge CLK) begin
rCapState <= #1 (RST_IN ? `S_TXENGUPR128_CAP_RD_WR : _rCapState);
rRdAck <= #1 (RST_IN ? {C_NUM_CHNL{1'd0}} : _rRdAck);
rWrAck <= #1 (RST_IN ? {C_NUM_CHNL{1'd0}} : _rWrAck);
rIsWr <= #1 _rIsWr;
rCapChnl <= #1 _rCapChnl;
rCapAddr <= #1 _rCapAddr;
rCapAddr64 <= #1 _rCapAddr64;
rCapLen <= #1 _rCapLen;
rCapIsWr <= #1 _rCapIsWr;
rExtTagReq <= #1 _rExtTagReq;
rExtTag <= #1 _rExtTag;
rTxEngRdReqAck <= #1 _rTxEngRdReqAck;
end
always @ (*) begin
_rCapState = rCapState;
_rRdAck = rRdAck;
_rWrAck = rWrAck;
_rIsWr = rIsWr;
_rCapChnl = rCapChnl;
_rCapAddr = rCapAddr;
_rCapAddr64 = rCapAddr64;
_rCapLen = rCapLen;
_rCapIsWr = rCapIsWr;
_rExtTagReq = rExtTagReq;
_rExtTag = rExtTag;
_rTxEngRdReqAck = rTxEngRdReqAck;
case (rCapState)
`S_TXENGUPR128_CAP_RD_WR : begin
_rIsWr = !wRdReq;
_rRdAck = ((wRdAck)<<wRdReqChnl);
_rTxEngRdReqAck = wRdAck;
_rExtTagReq = wRdAck;
_rCapState = (wRdAck ? `S_TXENGUPR128_CAP_CAP : `S_TXENGUPR128_CAP_WR_RD);
end
`S_TXENGUPR128_CAP_WR_RD : begin
_rIsWr = wWrReq;
_rWrAck = (wWrReq<<wWrReqChnl);
_rCapState = (wWrReq ? `S_TXENGUPR128_CAP_CAP : `S_TXENGUPR128_CAP_RD_WR);
end
`S_TXENGUPR128_CAP_CAP : begin
_rTxEngRdReqAck = 0;
_rRdAck = 0;
_rWrAck = 0;
_rCapIsWr = rIsWr;
_rExtTagReq = 0;
_rExtTag = EXT_TAG ^ {rIsWr,{(C_TAG_WIDTH-1){1'b0}}};
if (rIsWr) begin
_rCapChnl = {2'd0, rWrChnl};
_rCapAddr = rWrAddr;
_rCapAddr64 = (rWrAddr[61:30] != 0);
_rCapLen = rWrLen;
end
else begin
_rCapChnl = {rRdSgChnl, rRdChnl};
_rCapAddr = rRdAddr;
_rCapAddr64 = (rRdAddr[61:30] != 0);
_rCapLen = rRdLen;
end
_rCapState = `S_TXENGUPR128_CAP_REL;
end
`S_TXENGUPR128_CAP_REL : begin
// Push into the formatting pipeline when ready
if (TXR_META_READY & !rMainState) begin // S_TXENGUPR128_MAIN_IDLE
_rCapState = (`S_TXENGUPR128_CAP_WR_RD>>(rCapIsWr)); // Changes to S_TXENGUPR128_CAP_RD_WR
end
end
default : begin
_rCapState = `S_TXENGUPR128_CAP_RD_WR;
end
endcase
end
// Start the read/write when space is available in the output FIFO and when
// request parameters have been captured (i.e. a pending request).
always @ (posedge CLK) begin
rMainState <= #1 (RST_IN ? `S_TXENGUPR128_MAIN_IDLE : _rMainState);
rCountIsWr <= #1 _rCountIsWr;
rCountLen <= #1 _rCountLen;
rCountChnl <= #1 _rCountChnl;
rCountTag <= #1 _rCountTag;
rCountAddr <= #1 _rCountAddr;
rCountAddr64 <= #1 _rCountAddr64;
rCount <= #1 _rCount;
rCountDone <= #1 _rCountDone;
rCountStart <= #1 _rCountStart;
rCountValid <= #1 _rCountValid;
rWrDataRen <= #1 _rWrDataRen;
end
always @ (*) begin
_rMainState = rMainState;
_rCountIsWr = rCountIsWr;
_rCountLen = rCountLen;
_rCountChnl = rCountChnl;
_rCountTag = rCountTag;
_rCountAddr = rCountAddr;
_rCountAddr64 = rCountAddr64;
_rCount = rCount;
_rCountDone = rCountDone;
_rCountValid = rCountValid;
_rWrDataRen = rWrDataRen;
_rCountStart = 0;
case (rMainState)
`S_TXENGUPR128_MAIN_IDLE : begin
_rCountIsWr = rCapIsWr;
_rCountLen = rCapLen;
_rCountChnl = rCapChnl[3:0];
_rCountTag = rExtTag;
_rCountAddr = rCapAddr;
_rCountAddr64 = rCapAddr64;
_rCount = rCapLen;
_rCountDone = (rCapLen <= 3'd4);
_rWrDataRen = ((TXR_META_READY & rCapState[3] & rCapIsWr)<<(rCapChnl[3:0])); // S_TXENGUPR128_CAP_REL
_rCountValid = (TXR_META_READY & rCapState[3]);
_rCountStart = (TXR_META_READY & rCapState[3]);
if (TXR_META_READY && rCapState[3] && rCapIsWr && (rCapAddr64 || (rCapLen != 10'd1))) // S_TXENGUPR128_CAP_REL
_rMainState = `S_TXENGUPR128_MAIN_WR;
end
`S_TXENGUPR128_MAIN_WR : begin
_rCount = rCount - 3'd4;
_rCountDone = (rCount <= 4'd8);
if (rCountDone) begin
_rWrDataRen = 0;
_rCountValid = 0;
_rMainState = `S_TXENGUPR128_MAIN_IDLE;
end
end
endcase
end
// Shift in the captured parameters and valid signal every cycle.
// This pipeline will keep the formatter busy.
assign wCountChnl = rChnl[(C_DATA_DELAY-2)*4 +:4];
always @ (posedge CLK) begin
rWnR <= #1 _rWnR;
rChnl <= #1 _rChnl;
rTag <= #1 _rTag;
rAddr <= #1 _rAddr;
rAddr64 <= #1 _rAddr64;
rLen <= #1 _rLen;
rLenEQ1 <= #1 _rLenEQ1;
rValid <= #1 _rValid;
rDone <= #1 _rDone;
rStart <= #1 _rStart;
end
always @ (*) begin
_rWnR = {rWnR[((C_DATA_DELAY-1)*1)-1:0], rCountIsWr};
_rChnl = {rChnl[((C_DATA_DELAY-1)*4)-1:0], rCountChnl};
_rTag = {rTag[((C_DATA_DELAY-1)*8)-1:0], (8'd0 | rCountTag)};
_rAddr = {rAddr[((C_DATA_DELAY-1)*62)-1:0], rCountAddr};
_rAddr64 = {rAddr64[((C_DATA_DELAY-1)*1)-1:0], rCountAddr64};
_rLen = {rLen[((C_DATA_DELAY-1)*10)-1:0], rCountLen};
_rLenEQ1 = {rLenEQ1[((C_DATA_DELAY-1)*1)-1:0], (rCountLen == 10'd1)};
_rValid = {rValid[((C_DATA_DELAY-1)*1)-1:0], rCountValid & rCountIsWr};
_rDone = {rDone[((C_DATA_DELAY-1)*1)-1:0], rCountDone};
_rStart = {rStart[((C_DATA_DELAY-1)*1)-1:0], rCountStart};
end // always @ begin
assign TXR_DATA = rWrData;
assign TXR_DATA_VALID = rValid[(C_DATA_DELAY-1)*1 +:1];
assign TXR_DATA_START_FLAG = rStart[(C_DATA_DELAY-1)*1 +:1];
assign TXR_DATA_START_OFFSET = 0;
assign TXR_DATA_END_FLAG = rDone[(C_DATA_DELAY-1)*1 +:1];
assign TXR_DATA_END_OFFSET = rLen[(C_DATA_DELAY-1)*10 +:`SIG_OFFSET_W] - 1;
assign TXR_META_VALID = rCountStart;
assign TXR_META_TYPE = rCountIsWr ? `TRLS_REQ_WR : `TRLS_REQ_RD;
assign TXR_META_ADDR = {rCountAddr,2'b00};
assign TXR_META_LENGTH = rCountLen;
assign TXR_META_LDWBE = rCountLen == 10'd1 ? 0 : 4'b1111;
assign TXR_META_FDWBE = 4'b1111;
assign TXR_META_TAG = rCountTag;
assign TXR_META_EP = 1'b0;
assign TXR_META_ATTR = 3'b110;
assign TXR_META_TC = 0;
endmodule
|
module sky130_fd_sc_hdll__dlrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module srio_gen2_0_k7_v7_gtxe2_common
#(
// Simulation attributes
parameter WRAPPER_SIM_GTRESET_SPEEDUP = "TRUE", // Set to "true" to speed up sim reset
parameter RX_DFE_KL_CFG2_IN = 32'h3010D90C,
parameter PMA_RSV_IN = 32'h00018480,
parameter SIM_VERSION = "4.0"
)
(
input gt0_gtrefclk0_common_in , // connect to refclk
input gt0_qplllockdetclk_in , // connect to drpclk
input gt0_qpllreset_in , // connect to gt_pcs_rst
output qpll_clk_out ,
output qpll_out_refclk_out ,
output gt0_qpll_lock_out // use only when 2x or 4x or 6g
); //_________________________________________________________________________
//_________________________________________________________________________
//_________________________GTXE2_COMMON____________________________________
// ground and vcc signals
// 8/23/2013
parameter QPLL_FBDIV_TOP = 40;
parameter QPLL_FBDIV_IN = (QPLL_FBDIV_TOP == 16) ? 10'b0000100000 :
(QPLL_FBDIV_TOP == 20) ? 10'b0000110000 :
(QPLL_FBDIV_TOP == 32) ? 10'b0001100000 :
(QPLL_FBDIV_TOP == 40) ? 10'b0010000000 :
(QPLL_FBDIV_TOP == 64) ? 10'b0011100000 :
(QPLL_FBDIV_TOP == 66) ? 10'b0101000000 :
(QPLL_FBDIV_TOP == 80) ? 10'b0100100000 :
(QPLL_FBDIV_TOP == 100) ? 10'b0101110000 : 10'b0000000000;
parameter QPLL_FBDIV_RATIO = (QPLL_FBDIV_TOP == 16) ? 1'b1 :
(QPLL_FBDIV_TOP == 20) ? 1'b1 :
(QPLL_FBDIV_TOP == 32) ? 1'b1 :
(QPLL_FBDIV_TOP == 40) ? 1'b1 :
(QPLL_FBDIV_TOP == 64) ? 1'b1 :
(QPLL_FBDIV_TOP == 66) ? 1'b0 :
(QPLL_FBDIV_TOP == 80) ? 1'b1 :
(QPLL_FBDIV_TOP == 100) ? 1'b1 : 1'b1;
wire tied_to_ground_i;
wire [63:0] tied_to_ground_vec_i;
wire tied_to_vcc_i;
wire [63:0] tied_to_vcc_vec_i;
assign tied_to_ground_i = 1'b0;
assign tied_to_ground_vec_i = 64'h0000000000000000;
assign tied_to_vcc_i = 1'b1;
assign tied_to_vcc_vec_i = 64'hffffffffffffffff;
GTXE2_COMMON #
(
// Simulation attributes
.SIM_RESET_SPEEDUP (WRAPPER_SIM_GTRESET_SPEEDUP),
.SIM_QPLLREFCLK_SEL (3'b001),
.SIM_VERSION (SIM_VERSION),
//----------------COMMON BLOCK Attributes---------------
.BIAS_CFG (64'h0000040000001000),
.COMMON_CFG (32'h00000000),
.QPLL_CFG (27'h06801C1),
.QPLL_CLKOUT_CFG (4'b0000),
.QPLL_COARSE_FREQ_OVRD (6'b010000),
.QPLL_COARSE_FREQ_OVRD_EN (1'b0),
.QPLL_CP (10'b0000011111),
.QPLL_CP_MONITOR_EN (1'b0),
.QPLL_DMONITOR_SEL (1'b0),
.QPLL_FBDIV (QPLL_FBDIV_IN),
.QPLL_FBDIV_MONITOR_EN (1'b0),
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
.QPLL_INIT_CFG (24'h000006),
.QPLL_LOCK_CFG (16'h21E8),
.QPLL_LPF (4'b1111),
.QPLL_REFCLK_DIV (1)
)
gtxe2_common_0_i
(
//----------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
.DRPADDR (tied_to_ground_vec_i[7:0]),
.DRPCLK (tied_to_ground_i),
.DRPDI (tied_to_ground_vec_i[15:0]),
.DRPDO (),
.DRPEN (tied_to_ground_i),
.DRPRDY (),
.DRPWE (tied_to_ground_i),
//-------------------- Common Block - Ref Clock Ports ---------------------
.GTGREFCLK (tied_to_ground_i),
.GTNORTHREFCLK0 (tied_to_ground_i),
.GTNORTHREFCLK1 (tied_to_ground_i),
.GTREFCLK0 (gt0_gtrefclk0_common_in),
.GTREFCLK1 (tied_to_ground_i),
.GTSOUTHREFCLK0 (tied_to_ground_i),
.GTSOUTHREFCLK1 (tied_to_ground_i),
//----------------------- Common Block - QPLL Ports -----------------------
.QPLLDMONITOR (),
//--------------------- Common Block - Clocking Ports ----------------------
.QPLLOUTCLK (qpll_clk_out),
.QPLLOUTREFCLK (qpll_out_refclk_out),
.REFCLKOUTMONITOR (),
//----------------------- Common Block - QPLL Ports ------------------------
.QPLLFBCLKLOST (),
.QPLLLOCK (gt0_qpll_lock_out),
.QPLLLOCKDETCLK (gt0_qplllockdetclk_in),
.QPLLLOCKEN (tied_to_vcc_i),
.QPLLOUTRESET (tied_to_ground_i),
.QPLLPD (tied_to_vcc_i),
.QPLLREFCLKLOST (),
.QPLLREFCLKSEL (3'b001),
.QPLLRESET (gt0_qpllreset_in),
.QPLLRSVD1 (16'b0000000000000000),
.QPLLRSVD2 (5'b11111),
//------------------------------- QPLL Ports -------------------------------
.BGBYPASSB (tied_to_vcc_i),
.BGMONITORENB (tied_to_vcc_i),
.BGPDB (tied_to_vcc_i),
.BGRCALOVRD (5'b00000),
.PMARSVD (8'b00000000),
.RCALENB (tied_to_vcc_i)
);
endmodule
|
module IP(
input [63:0] Din,
output [63:0] Dout
);
assign Dout = {Din[6], Din[14], Din[22], Din[30], Din[38], Din[46], Din[54], Din[62], Din[4], Din[12], Din[20], Din[28], Din[36], Din[44], Din[52], Din[60], Din[2], Din[10], Din[18], Din[26], Din[34], Din[42], Din[50], Din[58], Din[0], Din[8], Din[16], Din[24], Din[32], Din[40], Din[48], Din[56], Din[7], Din[15], Din[23], Din[31], Din[39], Din[47], Din[55], Din[63], Din[5], Din[13], Din[21], Din[29], Din[37], Din[45], Din[53], Din[61], Din[3], Din[11], Din[19], Din[27], Din[35], Din[43], Din[51], Din[59], Din[1], Din[9], Din[17], Din[25], Din[33], Din[41], Din[49], Din[57]};
endmodule
|
module IP_1(
input [63:0] Din,
output [63:0] Dout
);
assign Dout = {Din[24], Din[56], Din[16], Din[48], Din[8], Din[40], Din[0], Din[32], Din[25], Din[57], Din[17], Din[49], Din[9], Din[41], Din[1], Din[33], Din[26], Din[58], Din[18], Din[50], Din[10], Din[42], Din[2], Din[34], Din[27], Din[59], Din[19], Din[51], Din[11], Din[43], Din[3], Din[35], Din[28], Din[60], Din[20], Din[52], Din[12], Din[44], Din[4], Din[36], Din[29], Din[61], Din[21], Din[53], Din[13], Din[45], Din[5], Din[37], Din[30], Din[62], Din[22], Din[54], Din[14], Din[46], Din[6], Din[38], Din[31], Din[63], Din[23], Din[55], Din[15], Din[47], Din[7], Din[39]};
endmodule
|
module arrmul (reg_A,reg_B,ctrl_ww,alu_op,result);
// Output signals...
// Result from copmputing an arithmetic or logical operation
output [0:127] result;
/**
* Overflow fromn arithmetic operations are ignored; use
* saturating mode for arithmetic operations - cap the value
* at the maximum value.
*
* Also, an output signal to indicate that an overflow has
* occurred will not be provided
*/
// ===============================================================
// Input signals
// Input register A
input [0:127] reg_A;
// Input register B
input [0:127] reg_B;
// Control signal bits - ww
input [0:1] ctrl_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform
*/
input [0:4] alu_op;
/**
* May also include: branch_offset[n:0], is_branch
* Size of branch offset is specified in the Instruction Set
* Architecture
*
* The reset signal for the ALU is ignored
*/
// Defining constants: parameter [name_of_constant] = value;
// Defining integers: integer [name_of_integer] = value;
integer sgn;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [0:127] result; // Output signals
/**
* Temporary reg(s) to contain the partial products during
* multiplication
*/
reg [0:127] p_pdt;
// Temporary reg variables for WW=8, for 8-bit multiplication
reg [0:15] p_pdt8a;
reg [0:15] p_pdt8a2;
reg [0:15] p_pdt8b;
reg [0:15] p_pdt8b2;
reg [0:15] p_pdt8c;
reg [0:15] p_pdt8c2;
reg [0:15] p_pdt8d;
reg [0:15] p_pdt8d2;
reg [0:15] p_pdt8e;
reg [0:15] p_pdt8e2;
reg [0:15] p_pdt8f;
reg [0:15] p_pdt8f2;
reg [0:15] p_pdt8g;
reg [0:15] p_pdt8g2;
reg [0:15] p_pdt8h;
reg [0:15] p_pdt8h2;
// Temporary reg variables for WW=16, for 16-bit multiplication
reg [0:31] p_pdt16a;
reg [0:31] p_pdt16a2;
reg [0:31] p_pdt16a3;
reg [0:31] p_pdt16b;
reg [0:31] p_pdt16b2;
reg [0:31] p_pdt16c;
reg [0:31] p_pdt16c2;
reg [0:31] p_pdt16d;
reg [0:31] p_pdt16d2;
// ===============================================================
always @(reg_A or reg_B or ctrl_ww or alu_op)
begin
$display("reg_A",reg_A);
$display("reg_B",reg_B);
p_pdt=128'd0;
p_pdt8a=16'd0;
p_pdt8a2=16'd0;
p_pdt8b=16'd0;
p_pdt8b2=16'd0;
p_pdt8c=16'd0;
p_pdt8c2=16'd0;
p_pdt8d=16'd0;
p_pdt8d2=16'd0;
p_pdt8e=16'd0;
p_pdt8e2=16'd0;
p_pdt8f=16'd0;
p_pdt8f2=16'd0;
p_pdt8g=16'd0;
p_pdt8g2=16'd0;
p_pdt8h=16'd0;
p_pdt8h2=16'd0;
p_pdt16a=32'd0;
p_pdt16a2=32'd0;
p_pdt16a3=32'd0;
p_pdt16b=32'd0;
p_pdt16b2=32'd0;
p_pdt16c=32'd0;
p_pdt16c2=32'd0;
p_pdt16d=32'd0;
p_pdt16d2=32'd0;
/**
* Based on the assigned arithmetic or logic instruction,
* carry out the appropriate function on the operands
*/
case(alu_op)
// ======================================================
// Unsigned Multiplication - even subfields
`aluwmuleu:
begin
case(ctrl_ww)
`w8: // aluwmuleu AND `w8
begin
p_pdt8a[8:15]=reg_A[0:7];
p_pdt8a[0:7]=8'd0;
for(sgn=7; sgn>=0; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[0:15]=p_pdt[0:15]+(p_pdt8a<<(7-sgn));
end
end
result[0:15]=p_pdt[0:15];
p_pdt8b[8:15]=reg_A[16:23];
p_pdt8b[0:7]=8'd0;
for(sgn=23; sgn>=16; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[16:31]=p_pdt[16:31]+(p_pdt8b<<(7-(sgn%8)));
end
end
result[16:31]=p_pdt[16:31];
p_pdt8c[8:15]=reg_A[32:39];
p_pdt8c[0:7]=8'd0;
for(sgn=39; sgn>=32; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[32:47]=p_pdt[32:47]+(p_pdt8c<<(7-(sgn%8)));
end
end
result[32:47]=p_pdt[32:47];
p_pdt8d[8:15]=reg_A[48:55];
p_pdt8d[0:7]=8'd0;
for(sgn=55; sgn>=48; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[48:63]=p_pdt[48:63]+(p_pdt8d<<(7-(sgn%8)));
end
end
result[48:63]=p_pdt[48:63];
p_pdt8e[8:15]=reg_A[64:71];
p_pdt8e[0:7]=8'd0;
for(sgn=71; sgn>=64; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[64:79]=p_pdt[64:79]+(p_pdt8e<<(7-(sgn%8)));
end
end
result[64:79]=p_pdt[64:79];
p_pdt8f[8:15]=reg_A[80:87];
p_pdt8f[0:7]=8'd0;
for(sgn=87; sgn>=80; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[80:95]=p_pdt[80:95]+(p_pdt8f<<(7-(sgn%8)));
end
end
result[80:95]=p_pdt[80:95];
p_pdt8g[8:15]=reg_A[96:103];
p_pdt8g[0:7]=8'd0;
for(sgn=103; sgn>=96; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[96:111]=p_pdt[96:111]+(p_pdt8g<<(7-(sgn%8)));
end
end
result[96:111]=p_pdt[96:111];
p_pdt8h[8:15]=reg_A[112:119];
p_pdt8h[0:7]=8'd0;
for(sgn=119; sgn>=112; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[112:127]=p_pdt[112:127]+(p_pdt8h<<(7-(sgn%8)));
end
end
result[112:127]=p_pdt[112:127];
end
`w16: // aluwmuleu AND `w16
begin
p_pdt16a[16:31]=reg_A[0:15];
p_pdt16a[0:15]=8'd0;
for(sgn=15; sgn>=0; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[0:31]=p_pdt[0:31]+(reg_A[0:15]<<(15-sgn));
end
end
result[0:31]=p_pdt[0:31];
p_pdt16b[16:31]=reg_A[32:47];
p_pdt16b[0:15]=8'd0;
for(sgn=47; sgn>=32; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[32:63]=p_pdt[32:63]+(reg_A[32:47]<<(15-(sgn%16)));
end
end
result[32:63]=p_pdt[32:63];
p_pdt16c[16:31]=reg_A[64:79];
p_pdt16c[0:15]=8'd0;
for(sgn=79; sgn>=64; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[64:95]=p_pdt[64:95]+(reg_A[64:79]<<(15-(sgn%16)));
end
end
result[64:95]=p_pdt[64:95];
p_pdt16d[16:31]=reg_A[96:111];
p_pdt16d[0:15]=8'd0;
for(sgn=111; sgn>=96; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[96:127]=p_pdt[96:127]+(reg_A[96:111]<<(15-(sgn%16)));
end
end
result[96:127]=p_pdt[96:127];
end
default: // aluwmuleu AND Default
begin
result=128'd0;
end
endcase
end
/**
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
*/
// ======================================================
// Unsigned Multiplication - odd subfields
`aluwmulou:
begin
case(ctrl_ww)
`w8: // aluwmulou AND `w8
begin
p_pdt8a[8:15]=reg_A[8:15];
p_pdt8a[0:7]=8'd0;
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[0:15]=p_pdt[0:15]+(p_pdt8a<<(7-(sgn%8)));
end
end
result[0:15]=p_pdt[0:15];
p_pdt8b[8:15]=reg_A[24:31];
p_pdt8b[0:7]=8'd0;
for(sgn=31; sgn>=24; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[16:31]=p_pdt[16:31]+(p_pdt8b<<(7-(sgn%8)));
end
end
result[16:31]=p_pdt[16:31];
p_pdt8c[8:15]=reg_A[40:47];
p_pdt8c[0:7]=8'd0;
for(sgn=39; sgn>=33; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[32:47]=p_pdt[32:47]+(p_pdt8c<<(7-(sgn%8)));
end
end
result[32:47]=p_pdt[32:47];
p_pdt8d[8:15]=reg_A[56:63];
p_pdt8d[0:7]=8'd0;
for(sgn=55; sgn>=48; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[48:63]=p_pdt[48:63]+(p_pdt8d<<(7-(sgn%8)));
end
end
result[48:63]=p_pdt[48:63];
p_pdt8e[8:15]=reg_A[72:79];
p_pdt8e[0:7]=8'd0;
for(sgn=79; sgn>=72; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[64:79]=p_pdt[64:79]+(p_pdt8e<<(7-(sgn%8)));
end
end
result[64:79]=p_pdt[64:79];
p_pdt8f[8:15]=reg_A[88:95];
p_pdt8f[0:7]=8'd0;
for(sgn=95; sgn>=88; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[80:95]=p_pdt[80:95]+(p_pdt8f<<(7-(sgn%8)));
end
end
result[80:95]=p_pdt[80:95];
p_pdt8g[8:15]=reg_A[104:111];
p_pdt8g[0:7]=8'd0;
for(sgn=111; sgn>=104; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[96:111]=p_pdt[96:111]+(p_pdt8g<<(7-(sgn%8)));
end
end
result[96:111]=p_pdt[96:111];
p_pdt8h[8:15]=reg_A[120:127];
p_pdt8h[0:7]=8'd0;
for(sgn=127; sgn>=120; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[112:127]=p_pdt[112:127]+(p_pdt8h<<(7-(sgn%8)));
end
end
result[112:127]=p_pdt[112:127];
end
`w16: // aluwmulou AND `w16
begin
p_pdt16a[16:31]=reg_A[16:31];
p_pdt16a[0:15]=8'd0;
for(sgn=31; sgn>=16; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[0:31]=p_pdt[0:31]+(reg_A[16:31]<<(15-(sgn%16)));
end
end
result[0:31]=p_pdt[0:31];
p_pdt16b[16:31]=reg_A[48:63];
p_pdt16b[0:15]=8'd0;
for(sgn=63; sgn>=48; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[32:63]=p_pdt[32:63]+(reg_A[48:63]<<(15-(sgn%16)));
end
end
result[32:63]=p_pdt[32:63];
p_pdt16c[16:31]=reg_A[80:95];
p_pdt16c[0:15]=8'd0;
for(sgn=95; sgn>=80; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[64:95]=p_pdt[64:95]+(reg_A[80:95]<<(15-(sgn%16)));
end
end
result[64:95]=p_pdt[64:95];
p_pdt16d[16:31]=reg_A[112:127];
p_pdt16d[0:15]=8'd0;
for(sgn=127; sgn>=112; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[96:127]=p_pdt[96:127]+(reg_A[112:127]<<(15-(sgn%16)));
end
end
result[96:127]=p_pdt[96:127];
end
default: // aluwmulou AND Default
begin
result=128'd0;
end
endcase
end
/**
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
*/
// ======================================================
// Signed Multiplication - odd subfields
`aluwmulos:
begin
case(ctrl_ww)
`w8: // aluwmulos AND `w8
begin
// Process the 1st byte
if(reg_A[8]==0)
begin
p_pdt8a[8:15]=reg_A[8:15];
end
else
begin
p_pdt8a[8:15]=1+~reg_A[8:15];
end
p_pdt8b[0:7]=8'd0;
if(reg_B[8]==0)
begin
p_pdt8a2[8:15]=reg_B[8:15];
end
else
begin
p_pdt8a2[8:15]=1+~reg_B[8:15];
end
p_pdt8b2[0:7]=8'd0;
for(sgn=15; sgn>=0; sgn=sgn-1)
begin
if(p_pdt8a2[sgn]==1'b1)
begin
p_pdt[0:15]=p_pdt[0:15]+(p_pdt8a<<(7-(sgn%8)));
end
end
if(reg_A[8]^reg_B[8])
begin
result[0:15]=1+~p_pdt[0:15];
end
else
begin
result[0:15]=p_pdt[0:15];
end
// Process the 2nd byte
if(reg_A[24]==0)
begin
p_pdt8b[8:15]=reg_A[24:31];
end
else
begin
p_pdt8b[8:15]=1+~reg_A[24:31];
end
p_pdt8b[0:7]=8'd0;
if(reg_B[24]==0)
begin
p_pdt8b2[8:15]=reg_B[24:31];
end
else
begin
p_pdt8b2[8:15]=1+~reg_B[24:31];
end
p_pdt8b2[0:7]=8'd0;
for(sgn=15; sgn>=0; sgn=sgn-1)
begin
if(p_pdt8b2[sgn]==1'b1)
begin
p_pdt[16:31]=p_pdt[16:31]+(p_pdt8b<<(7-(sgn%8)));
end
end
if(reg_A[24]^reg_B[24])
begin
result[16:31]=1+~p_pdt[16:31];
end
else
begin
result[16:31]=p_pdt[16:31];
end
// Process the 3rd byte
// Convert operand A to a positive number
if(reg_A[40]==0)
begin
p_pdt8c[8:15]=reg_A[40:47];
end
else
begin
p_pdt8c[8:15]=1+~reg_A[40:47];
end
p_pdt8c[0:7]=8'd0;
// Convert operand B to a positive number
if(reg_B[40]==0)
begin
p_pdt8c2[8:15]=reg_B[40:47];
end
else
begin
p_pdt8c2[8:15]=1+~reg_B[40:47];
end
p_pdt8c2[0:7]=8'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=15; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt8c2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[32:47]=p_pdt[32:47]+(p_pdt8c<<(7-(sgn%8)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[40]^reg_B[40])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[32:47]=1+~p_pdt[32:47];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[32:47]=p_pdt[32:47];
end
// Process the 4th byte
// Convert operand A to a positive number
if(reg_A[56]==0)
begin
p_pdt8d[8:15]=reg_A[56:63];
end
else
begin
p_pdt8d[8:15]=1+~reg_A[56:63];
end
p_pdt8d[0:7]=8'd0;
// Convert operand B to a positive number
if(reg_B[56]==0)
begin
p_pdt8d2[8:15]=reg_B[56:63];
end
else
begin
p_pdt8d2[8:15]=1+~reg_B[56:63];
end
p_pdt8d2[0:7]=8'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=15; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt8d2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[48:63]=p_pdt[48:63]+(p_pdt8d<<(7-(sgn%8)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[56]^reg_B[56])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[48:63]=1+~p_pdt[48:63];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[48:63]=p_pdt[48:63];
end
// Process the 5th byte
// Convert operand A to a positive number
if(reg_A[72]==0)
begin
p_pdt8e[8:15]=reg_A[72:79];
end
else
begin
p_pdt8e[8:15]=1+~reg_A[72:79];
end
p_pdt8e[0:7]=8'd0;
// Convert operand B to a positive number
if(reg_B[72]==0)
begin
p_pdt8e2[8:15]=reg_B[72:79];
end
else
begin
p_pdt8e2[8:15]=1+~reg_B[72:79];
end
p_pdt8e2[0:7]=8'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=15; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt8e2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[64:79]=p_pdt[64:79]+(p_pdt8e<<(7-(sgn%8)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[72]^reg_B[72])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[64:79]=1+~p_pdt[64:79];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[64:79]=p_pdt[64:79];
end
// Process the 6th byte
// Convert operand A to a positive number
if(reg_A[88]==0)
begin
p_pdt8f[8:15]=reg_A[88:95];
end
else
begin
p_pdt8f[8:15]=1+~reg_A[88:95];
end
p_pdt8f[0:7]=8'd0;
// Convert operand B to a positive number
if(reg_B[88]==0)
begin
p_pdt8f2[8:15]=reg_B[88:95];
end
else
begin
p_pdt8f2[8:15]=1+~reg_B[88:95];
end
p_pdt8f2[0:7]=8'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=15; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt8f2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[80:95]=p_pdt[80:95]+(p_pdt8f<<(7-(sgn%8)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[88]^reg_B[88])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[80:95]=1+~p_pdt[80:95];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[80:95]=p_pdt[80:95];
end
// Process the 7th byte
// Convert operand A to a positive number
if(reg_A[104]==0)
begin
p_pdt8g[8:15]=reg_A[104:111];
end
else
begin
p_pdt8g[8:15]=1+~reg_A[104:111];
end
p_pdt8g[0:7]=8'd0;
// Convert operand B to a positive number
if(reg_B[104]==0)
begin
p_pdt8g2[8:15]=reg_B[104:111];
end
else
begin
p_pdt8g2[8:15]=1+~reg_B[104:111];
end
p_pdt8g2[0:7]=8'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=15; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt8g2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[96:111]=p_pdt[96:111]+(p_pdt8g<<(7-(sgn%8)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[104]^reg_B[104])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[96:111]=1+~p_pdt[96:111];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[96:111]=p_pdt[96:111];
end
// Process the 8th byte
// Convert operand A to a positive number
if(reg_A[120]==0)
begin
p_pdt8h[8:15]=reg_A[120:127];
end
else
begin
p_pdt8h[8:15]=1+~reg_A[120:127];
end
p_pdt8h[0:7]=8'd0;
// Convert operand B to a positive number
if(reg_B[120]==0)
begin
p_pdt8h2[8:15]=reg_B[120:127];
end
else
begin
p_pdt8h2[8:15]=1+~reg_B[120:127];
end
p_pdt8h2[0:7]=8'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=15; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt8h2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[112:127]=p_pdt[112:127]+(p_pdt8h<<(7-(sgn%8)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[120]^reg_B[120])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[112:127]=1+~p_pdt[112:127];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[112:127]=p_pdt[112:127];
end
// =======================================================
// =======================================================
// =======================================================
end
`w16: // aluwmulos AND `w16
begin
// Process the first pair of bytes
// Convert operand A to a positive number
if(reg_A[16]==0)
begin
p_pdt16a[16:31]=reg_A[16:31];
end
else
begin
p_pdt16a[16:31]=1+~reg_A[16:31];
end
p_pdt16a[0:15]=16'd0;
// Convert operand B to a positive number
if(reg_B[16]==0)
begin
p_pdt16a2[16:31]=reg_B[16:31];
end
else
begin
p_pdt16a2[16:31]=1+~reg_B[16:31];
end
p_pdt16a2[0:15]=16'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=31; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt16a2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[0:31]=p_pdt[0:31]+(p_pdt16a<<(15-(sgn%16)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[16]^reg_B[16])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[0:31]=1+~p_pdt[0:31];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[0:31]=p_pdt[0:31];
end
// Process the second pair of bytes
// Convert operand A to a positive number
if(reg_A[48]==0)
begin
p_pdt16b[16:31]=reg_A[48:63];
end
else
begin
p_pdt16b[16:31]=1+~reg_A[48:63];
end
p_pdt16b[0:15]=16'd0;
// Convert operand B to a positive number
if(reg_B[48]==0)
begin
p_pdt16b2[16:31]=reg_B[48:63];
end
else
begin
p_pdt16b2[16:31]=1+~reg_B[48:63];
end
p_pdt16b2[0:15]=16'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=31; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt16b2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[32:63]=p_pdt[32:63]+(p_pdt16b<<(15-(sgn%16)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[48]^reg_B[48])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[32:63]=1+~p_pdt[32:63];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[32:63]=p_pdt[32:63];
end
// Process the third pair of bytes
// Convert operand A to a positive number
if(reg_A[80]==0)
begin
p_pdt16c[16:31]=reg_A[80:95];
end
else
begin
p_pdt16c[16:31]=1+~reg_A[80:95];
end
p_pdt16c[0:15]=16'd0;
// Convert operand B to a positive number
if(reg_B[80]==0)
begin
p_pdt16c2[16:31]=reg_B[80:95];
end
else
begin
p_pdt16c2[16:31]=1+~reg_B[80:95];
end
p_pdt16c2[0:15]=16'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=31; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt16c2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[64:95]=p_pdt[64:95]+(p_pdt16c<<(15-(sgn%16)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[80]^reg_B[80])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[64:95]=1+~p_pdt[64:95];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[64:95]=p_pdt[64:95];
end
// Process the fourth pair of bytes
// Convert operand A to a positive number
if(reg_A[112]==0)
begin
p_pdt16d[16:31]=reg_A[112:127];
end
else
begin
p_pdt16d[16:31]=1+~reg_A[112:127];
end
p_pdt16d[0:15]=16'd0;
// Convert operand B to a positive number
if(reg_B[112]==0)
begin
p_pdt16d2[16:31]=reg_B[112:127];
end
else
begin
p_pdt16d2[16:31]=1+~reg_B[112:127];
end
p_pdt16d2[0:15]=16'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=31; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt16d2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[96:127]=p_pdt[96:127]+(p_pdt16d<<(15-(sgn%16)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[112]^reg_B[112])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[96:127]=1+~p_pdt[96:127];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[96:127]=p_pdt[96:127];
end
end
default: // aluwmulos AND Default
begin
result=128'd0;
end
endcase
end
// ======================================================
// Signed Multiplication - even subfields
`aluwmules:
begin
case(ctrl_ww)
`w8: // aluwmules AND `w8
begin
// Process the 1st byte
// Process operand B
p_pdt8a2[8:15]=reg_B[0:7];
p_pdt8a2[0:7]=8'd0;
// Process operand A
if(reg_A[0]==1'd1)
begin
p_pdt8a[8:15]=1+~reg_A[0:7];
if(reg_B[0]==1'd1)
begin
p_pdt8a2[8:15]=1+~reg_B[0:7];
end
else
begin
p_pdt8a2[8:15]=reg_B[0:7];
end
end
else
begin
p_pdt8a[8:15]=reg_A[0:7];
end
p_pdt8a[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8a2[15]==1'd1)
begin
p_pdt[0:15]=p_pdt[0:15] - p_pdt8a[0:15];
end
else
begin
p_pdt[0:15]=p_pdt[0:15]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8a2[sgn]==1'b1) && (p_pdt8a2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[0:15]=p_pdt[0:15]-(p_pdt8a<<(7-(sgn%8)));
end
else if((p_pdt8a2[sgn]==1'b0) && (p_pdt8a2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[0:15]=p_pdt[0:15]+(p_pdt8a<<(7-(sgn%8)));
end
else
begin
p_pdt[0:15]=p_pdt[0:15]+0;
end
end
if(p_pdt8a[8]==1'd1)
begin
result[0:15]=1+~p_pdt[0:15];
end
else
begin
result[0:15]=p_pdt[0:15];
end
// Process the 2nd byte
// Process operand B
p_pdt8b2[8:15]=reg_B[16:23];
p_pdt8b2[0:7]=8'd0;
// Process operand A
if(reg_A[16]==1'd1)
begin
p_pdt8b[8:15]=1+~reg_A[16:23];
if(reg_B[16]==1'd1)
begin
p_pdt8b2[8:15]=1+~reg_B[16:23];
end
else
begin
p_pdt8b2[8:15]=reg_B[16:23];
end
end
else
begin
p_pdt8b[8:15]=reg_A[16:23];
end
p_pdt8b[0:7]=8'd0;
$display("p_pdt8b[0:15]",p_pdt8b[0:15]);
$display("p_pdt8b2[0:15]",p_pdt8b2[0:15]);
// Determine the 1st recoded bit and compute the result
if(p_pdt8b2[15]==1'd1)
begin
p_pdt[16:31]=p_pdt[16:31] - p_pdt8b[0:15];
end
else
begin
p_pdt[16:31]=p_pdt[16:31]+0;
end
$display("p_pdt[16:31]",p_pdt[16:31]);
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8b2[sgn]==1'b1) && (p_pdt8b2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[16:31]=p_pdt[16:31]-(p_pdt8b<<(7-(sgn%8)));
$display("MINUSp_pdt[16:31]",p_pdt[16:31]);
end
else if((p_pdt8b2[sgn]==1'b0) && (p_pdt8b2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[16:31]=p_pdt[16:31]+(p_pdt8b<<(7-(sgn%8)));
$display("ADDp_pdt[16:31]",p_pdt[16:31]);
end
else
begin
p_pdt[16:31]=p_pdt[16:31]+0;
$display("ZEROp_pdt[16:31]",p_pdt[16:31]);
end
end
if(p_pdt8b[8]==1'd1)
begin
result[16:31]=1+~p_pdt[16:31];
$display("INVp_pdt[16:31]",p_pdt[16:31]);
end
else
begin
result[16:31]=p_pdt[16:31];
$display("RESp_pdt[16:31]",p_pdt[16:31]);
end
// Process the 3rd byte
// Process operand B
p_pdt8c2[8:15]=reg_B[32:39];
p_pdt8c2[0:7]=8'd0;
// Process operand A
if(reg_A[32]==1'd1)
begin
p_pdt8c[8:15]=1+~reg_A[32:39];
if(reg_B[32]==1'd1)
begin
p_pdt8c2[8:15]=1+~reg_B[32:39];
end
else
begin
p_pdt8c2[8:15]=reg_B[32:39];
end
end
else
begin
p_pdt8c[8:15]=reg_A[32:39];
end
p_pdt8c[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8c2[15]==1'd1)
begin
p_pdt[32:47]=p_pdt[32:47] - p_pdt8c[0:15];
end
else
begin
p_pdt[32:47]=p_pdt[32:47]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8c2[sgn]==1'b1) && (p_pdt8c2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[32:47]=p_pdt[32:47]-(p_pdt8c<<(7-(sgn%8)));
end
else if((p_pdt8c2[sgn]==1'b0) && (p_pdt8c2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[32:47]=p_pdt[32:47]+(p_pdt8c<<(7-(sgn%8)));
end
else
begin
p_pdt[32:47]=p_pdt[32:47]+0;
end
end
if(p_pdt8c[8]==1'd1)
begin
result[32:47]=1+~p_pdt[32:47];
end
else
begin
result[32:47]=p_pdt[32:47];
end
// Process the 4th byte
// Process operand B
p_pdt8d2[8:15]=reg_B[48:55];
p_pdt8d2[0:7]=8'd0;
// Process operand A
if(reg_A[48]==1'd1)
begin
p_pdt8d[8:15]=1+~reg_A[48:55];
if(reg_B[48]==1'd1)
begin
p_pdt8d2[8:15]=1+~reg_B[48:55];
end
else
begin
p_pdt8d2[8:15]=reg_B[48:55];
end
end
else
begin
p_pdt8d[8:15]=reg_A[48:55];
end
p_pdt8d[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8d2[15]==1'd1)
begin
p_pdt[48:63]=p_pdt[48:63] - p_pdt8d[0:15];
end
else
begin
p_pdt[48:63]=p_pdt[48:63]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8d2[sgn]==1'b1) && (p_pdt8d2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[48:63]=p_pdt[48:63]-(p_pdt8d<<(7-(sgn%8)));
end
else if((p_pdt8d2[sgn]==1'b0) && (p_pdt8d2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[48:63]=p_pdt[48:63]+(p_pdt8d<<(7-(sgn%8)));
end
else
begin
p_pdt[48:63]=p_pdt[48:63]+0;
end
end
if(p_pdt8d[8]==1'd1)
begin
result[48:63]=1+~p_pdt[48:63];
end
else
begin
result[48:63]=p_pdt[48:63];
end
// Process the 5th byte
// Process operand B
p_pdt8e2[8:15]=reg_B[64:71];
p_pdt8e2[0:7]=8'd0;
// Process operand A
if(reg_A[64]==1'd1)
begin
p_pdt8e[8:15]=1+~reg_A[64:71];
if(reg_B[64]==1'd1)
begin
p_pdt8e2[8:15]=1+~reg_B[64:71];
end
else
begin
p_pdt8e2[8:15]=reg_B[64:71];
end
end
else
begin
p_pdt8e[8:15]=reg_A[64:71];
end
p_pdt8e[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8e2[15]==1'd1)
begin
p_pdt[64:79]=p_pdt[64:79] - p_pdt8e[0:15];
end
else
begin
p_pdt[64:79]=p_pdt[64:79]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8e2[sgn]==1'b1) && (p_pdt8e2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[64:79]=p_pdt[64:79]-(p_pdt8e<<(7-(sgn%8)));
end
else if((p_pdt8e2[sgn]==1'b0) && (p_pdt8e2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[64:79]=p_pdt[64:79]+(p_pdt8e<<(7-(sgn%8)));
end
else
begin
p_pdt[64:79]=p_pdt[64:79]+0;
end
end
if(p_pdt8e[8]==1'd1)
begin
result[64:79]=1+~p_pdt[64:79];
end
else
begin
result[64:79]=p_pdt[64:79];
end
// Process the 6th byte
// Process operand B
p_pdt8f2[8:15]=reg_B[80:87];
p_pdt8f2[0:7]=8'd0;
// Process operand A
if(reg_A[80]==1'd1)
begin
p_pdt8f[8:15]=1+~reg_A[80:87];
if(reg_B[80]==1'd1)
begin
p_pdt8f2[8:15]=1+~reg_B[80:87];
end
else
begin
p_pdt8f2[8:15]=reg_B[80:87];
end
end
else
begin
p_pdt8f[8:15]=reg_A[80:87];
end
p_pdt8f[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8f2[15]==1'd1)
begin
p_pdt[80:95]=p_pdt[80:95] - p_pdt8f[0:15];
end
else
begin
p_pdt[80:95]=p_pdt[80:95]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8f2[sgn]==1'b1) && (p_pdt8f2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[80:95]=p_pdt[80:95]-(p_pdt8f<<(7-(sgn%8)));
end
else if((p_pdt8f2[sgn]==1'b0) && (p_pdt8f2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[80:95]=p_pdt[80:95]+(p_pdt8f<<(7-(sgn%8)));
end
else
begin
p_pdt[80:95]=p_pdt[80:95]+0;
end
end
if(p_pdt8f[8]==1'd1)
begin
result[80:95]=1+~p_pdt[80:95];
end
else
begin
result[80:95]=p_pdt[80:95];
end
// Process the 7th byte
// Process operand B
p_pdt8g2[8:15]=reg_B[96:103];
p_pdt8g2[0:7]=8'd0;
// Process operand A
if(reg_A[96]==1'd1)
begin
p_pdt8g[8:15]=1+~reg_A[96:103];
if(reg_B[96]==1'd1)
begin
p_pdt8g2[8:15]=1+~reg_B[96:103];
end
else
begin
p_pdt8g2[8:15]=reg_B[96:103];
end
end
else
begin
p_pdt8g[8:15]=reg_A[96:103];
end
p_pdt8g[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8g2[15]==1'd1)
begin
p_pdt[96:111]=p_pdt[96:111] - p_pdt8g[0:15];
end
else
begin
p_pdt[96:111]=p_pdt[96:111]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8g2[sgn]==1'b1) && (p_pdt8g2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[96:111]=p_pdt[96:111]-(p_pdt8g<<(7-(sgn%8)));
end
else if((p_pdt8g2[sgn]==1'b0) && (p_pdt8g2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[96:111]=p_pdt[96:111]+(p_pdt8g<<(7-(sgn%8)));
end
else
begin
p_pdt[96:111]=p_pdt[96:111]+0;
end
end
if(p_pdt8g[8]==1'd1)
begin
result[96:111]=1+~p_pdt[96:111];
end
else
begin
result[96:111]=p_pdt[96:111];
end
// Process the 8th byte
// Process operand B
p_pdt8h2[8:15]=reg_B[112:119];
p_pdt8h2[0:7]=8'd0;
// Process operand A
if(reg_A[112]==1'd1)
begin
p_pdt8h[8:15]=1+~reg_A[112:119];
if(reg_B[112]==1'd1)
begin
p_pdt8h2[8:15]=1+~reg_B[112:119];
end
else
begin
p_pdt8h2[8:15]=reg_B[112:119];
end
end
else
begin
p_pdt8h[8:15]=reg_A[112:119];
end
p_pdt8h[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8h2[15]==1'd1)
begin
p_pdt[112:127]=p_pdt[112:127] - p_pdt8h[0:15];
end
else
begin
p_pdt[112:127]=p_pdt[112:127]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8h2[sgn]==1'b1) && (p_pdt8h2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[112:127]=p_pdt[112:127]-(p_pdt8h<<(7-(sgn%8)));
end
else if((p_pdt8h2[sgn]==1'b0) && (p_pdt8h2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[112:127]=p_pdt[112:127]+(p_pdt8h<<(7-(sgn%8)));
end
else
begin
p_pdt[112:127]=p_pdt[112:127]+0;
end
end
if(p_pdt8h[8]==1'd1)
begin
result[112:127]=1+~p_pdt[112:127];
end
else
begin
result[112:127]=p_pdt[112:127];
end
// =======================================================
// =======================================================
// =======================================================
/*
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
*/
end
`w16: // aluwmules AND `w16
begin
// Process the first pair of bytes
// Process operand B
p_pdt16a2[16:31]=reg_B[0:15];
p_pdt16a2[0:15]=16'd0;
// Process operand A
if(reg_A[0]==1'd1)
begin
p_pdt16a[16:31]=1+~reg_A[0:15];
if(reg_B[0]==1'd1)
begin
p_pdt16a2[16:31]=1+~reg_B[0:15];
end
else
begin
p_pdt16a2[16:31]=reg_B[0:15];
end
end
else
begin
p_pdt16a[16:31]=reg_A[0:15];
end
p_pdt16a[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16a2[31]==1'd1)
begin
p_pdt[0:31]=p_pdt[0:31] - p_pdt16a[0:31];
end
else
begin
p_pdt[0:31]=p_pdt[0:31]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16a2[sgn]==1'b1) && (p_pdt16a2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[0:31]=p_pdt[0:31]-(p_pdt16a<<(15-(sgn%16)));
end
else if((p_pdt16a2[sgn]==1'b0) && (p_pdt16a2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[0:31]=p_pdt[0:31]+(p_pdt16a<<(15-(sgn%16)));
end
else
begin
p_pdt[0:31]=p_pdt[0:31]+0;
end
end
if(p_pdt16a[16]==1'd1)
begin
result[0:31]=1+~p_pdt[0:31];
end
else
begin
result[0:31]=p_pdt[0:31];
end
// Process the second pair of bytes
// Process operand B
p_pdt16b2[16:31]=reg_B[32:47];
p_pdt16b2[0:15]=16'd0;
// Process operand A
if(reg_A[32]==1'd1)
begin
p_pdt16b[16:31]=1+~reg_A[32:47];
if(reg_B[32]==1'd1)
begin
p_pdt16b2[16:31]=1+~reg_B[32:47];
end
else
begin
p_pdt16b2[16:31]=reg_B[32:47];
end
end
else
begin
p_pdt16b[16:31]=reg_A[0:15];
end
p_pdt16b[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16b2[31]==1'd1)
begin
p_pdt[32:63]=p_pdt[32:63] - p_pdt16b[0:31];
end
else
begin
p_pdt[32:63]=p_pdt[32:63]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16b2[sgn]==1'b1) && (p_pdt16b2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[32:63]=p_pdt[32:63]-(p_pdt16b<<(15-(sgn%16)));
end
else if((p_pdt16b2[sgn]==1'b0) && (p_pdt16b2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[32:63]=p_pdt[32:63]+(p_pdt16b<<(15-(sgn%16)));
end
else
begin
p_pdt[32:63]=p_pdt[32:63]+0;
end
end
if(p_pdt16b[16]==1'd1)
begin
result[32:63]=1+~p_pdt[32:63];
end
else
begin
result[32:63]=p_pdt[32:63];
end
// Process the third pair of bytes
// Process operand B
p_pdt16c2[16:31]=reg_B[64:79];
p_pdt16c2[0:15]=16'd0;
// Process operand A
if(reg_A[64]==1'd1)
begin
p_pdt16c[16:31]=1+~reg_A[64:79];
if(reg_B[64]==1'd1)
begin
p_pdt16c2[16:31]=1+~reg_B[64:79];
end
else
begin
p_pdt16c2[16:31]=reg_B[64:79];
end
end
else
begin
p_pdt16c[16:31]=reg_A[64:79];
end
p_pdt16c[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16c2[31]==1'd1)
begin
p_pdt[64:95]=p_pdt[64:95] - p_pdt16c[0:31];
end
else
begin
p_pdt[64:95]=p_pdt[64:95]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16c2[sgn]==1'b1) && (p_pdt16c2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[64:95]=p_pdt[64:95]-(p_pdt16c<<(15-(sgn%16)));
end
else if((p_pdt16c2[sgn]==1'b0) && (p_pdt16c2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[64:95]=p_pdt[64:95]+(p_pdt16c<<(15-(sgn%16)));
end
else
begin
p_pdt[64:95]=p_pdt[64:95]+0;
end
end
if(p_pdt16c[16]==1'd1)
begin
result[64:95]=1+~p_pdt[64:95];
end
else
begin
result[64:95]=p_pdt[64:95];
end
// Process the fourth pair of bytes
// Process operand B
p_pdt16d2[16:31]=reg_B[96:111];
p_pdt16d2[0:15]=16'd0;
// Process operand A
if(reg_A[96]==1'd1)
begin
p_pdt16d[16:31]=1+~reg_A[96:111];
if(reg_B[96]==1'd1)
begin
p_pdt16d2[16:31]=1+~reg_B[96:111];
end
else
begin
p_pdt16d2[16:31]=reg_B[96:111];
end
end
else
begin
p_pdt16d[16:31]=reg_A[96:111];
end
p_pdt16d[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16d2[31]==1'd1)
begin
p_pdt[96:127]=p_pdt[96:127] - p_pdt16d[0:31];
end
else
begin
p_pdt[96:127]=p_pdt[96:127]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16d2[sgn]==1'b1) && (p_pdt16d2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[96:127]=p_pdt[96:127]-(p_pdt16d<<(15-(sgn%16)));
end
else if((p_pdt16d2[sgn]==1'b0) && (p_pdt16d2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[96:127]=p_pdt[96:127]+(p_pdt16d<<(15-(sgn%16)));
end
else
begin
p_pdt[96:127]=p_pdt[96:127]+0;
end
end
if(p_pdt16d[16]==1'd1)
begin
result[96:127]=1+~p_pdt[96:127];
end
else
begin
result[96:127]=p_pdt[96:127];
end
end
default: // aluwmules AND Default
begin
result=128'd0;
end
endcase
end
default:
begin
// Default arithmetic/logic operation
result=128'd0;
end
endcase
end
endmodule
|
module Wu_Manber_shiftPE #(parameter NO_OF_MSGS=128, MSG_WIDTH=4, B=3, PATTERN_WIDTH=20, SIGN_DEPTH=1024,
SHIFT_WIDTH=$clog2(PATTERN_WIDTH-B+1),DATA_WIDTH=MSG_WIDTH*NO_OF_MSGS,
NOS_SHIFTER=2*NO_OF_MSGS, POINTER_WIDTH=$clog2(NOS_SHIFTER), NOS_KEY=4, NOS_CMPS=SIGN_DEPTH/NOS_KEY,NOS_STGS=$clog2(SIGN_DEPTH/NOS_KEY),SFT_DEL_WDH=$clog2(NOS_STGS+NOS_KEY+2),MAX_PAT_SZ=78)
( input clk,
input reset,
input datInReady,
input [DATA_WIDTH-1:0] DataIn,
output getDATA,
output [10:0] dout);
localparam DATA_2WIDTH= 1024;
wire [DATA_WIDTH-1:0] datIn_op;
wire [MSG_WIDTH*PATTERN_WIDTH-1:0] a_ip, a_op;
wire [SHIFT_WIDTH-1:0] shift_ip, shift_op;
reg [SHIFT_WIDTH-1:0] shift_tmp;
wire din_sel;
wire [NOS_CMPS-1:0]fullCompare;
wire [POINTER_WIDTH-1:0] shift_pnt;
reg [2*NO_OF_MSGS*MSG_WIDTH-1:0] Data_in;
//register signals
wire a_clr, datin_clr, shift_clr;
wire a_ld;
wire shift_ld;
wire datald;
reg dat_ld, datin_ld;
wire compare_mux,compare_enable;
wire datin_ld_delwr;
reg datin_ld_del;
wire [MSG_WIDTH*MAX_PAT_SZ-1:0] data_nfa;
reg [PATTERN_WIDTH*MSG_WIDTH*NOS_KEY-1:0] pattern [0:NOS_CMPS-1] ;
always @(posedge clk ) begin
if (reset) begin
// reset
pattern[0] <=320'h21b8004233c999cd218bee50f7d8250f008bc8588becc7460200405d58b9558becc7460200405d58;
pattern[1] <=320'h8becc7460200405d58bacd2133c9b8004299cd21894515505657551e065389440233c026894515b9;
pattern[2] <=320'hb440cd21e80d00b91800c98bd1b802422e8b1e390a5253568bddfec7e8d4068db60801e86b005d5b;
pattern[3] <=320'h040205020089048d96fa8bd1b80042cd2159030de8af005b5803c1f7d83233d2b80042cd21ba9b02;
pattern[4] <=320'h5880fc0074148acc32ed33c933d2cd21b4408d9633f681c50001e88701b421b80042e84000b440b9;
pattern[5] <=320'hb4408d96ef04cd21b440598d968b05cd2132c0e80e07b91100f3a4be2e0107245b53b440b9c4038d;
pattern[6] <=320'h0e090190ba000190b4408d965c05cd2132c0e82e01b91900cd21b4408d962203b9f801cd21b4408d;
pattern[7] <=320'hfa26a3900026891e9200cd21ba9305bd0a0033c933c933d2cd21a128062d0301891619040e07b918;
pattern[8] <=320'hba850eb440e89204721ca2098bd081c20001b007c18ec0b9d808ba0000e84059ba3a04cd2132c0e8;
pattern[9] <=320'h3d078db60801e868008db80042e82b008d96fa01f08bfebed203b98600f32126c745150000b440ba;
pattern[10] <=320'h0f00bad009cd21b80042cd21b8004233c999cd2104ba0301e89501b440cdc983c200b9040089ff2d;
pattern[11] <=320'h3dba9e00cd2193b440bac9b8004233d2cd21b440cd2180fa007515b80242cd21fec0d0e03ad07533;
pattern[12] <=320'h2d04002e89861701b440e81200484848a367005303bfb2035733f681c500e88c00b002e87d00b440;
pattern[13] <=320'h33c9b8004233d2cd21ba46e2fbb440b9640433d2e003b440b90300baf303e89100b002e88200b440;
pattern[14] <=320'hb8004233c999cd21b440e88c00b002e87d00b440e88c00b002e87d00b440b8004233c933d2cc8d96;
pattern[15] <=320'hc9e88c00b002e87d00b4b8004233c999cd21b4400643e88c01e87501b440b8004233c999cd21b440;
pattern[16] <=320'h578db64a01b98a0151e8e4403e88864901b4408d3f03c8890e0401b440ba5bb440b93f04ba4605cd;
pattern[17] <=320'he88c00b002e87d00b440e88c00b002e87d00b440a30601b440cd2132c0e8c9e89100b002e88200b4;
pattern[18] <=320'he8bdffb002e878ffb440be0501b9b30690050301cd21b4402e8b1e1d01b92e2b0e1f01b4402e8b1e;
pattern[19] <=320'h08be0501b9be0790050308be0501b9520790050333c933d2cd21b440b9724233c933d2cd21b440b9;
pattern[20] <=320'h4233c933d2cd21b440b9b80242e84e00b440ba3e13b80042e83b00b440ba83c00989860a018d9609;
pattern[21] <=320'hc9e808008bd0b440b90335ad0089054747e2f0e8d2b80042cd21b920008dd2b80242cd21b917008d;
pattern[22] <=320'h28a38400b80057cc5152b8004233c933d2cd01b4f03d00f07502eb338bd581c51203e88805b90012;
pattern[23] <=320'hb8004233c933d2cd01b40881fb53427502f9c3f82d03008986b900b440b92d03008986bb00b440b9;
pattern[24] <=320'hcd21b000e81b00b440b921b000e81c00b440b903023dba9e00cd2193b4404233c933d2cd21b4408d;
pattern[25] <=320'h018b1eab06e81801b44002ba03010316060183eab80042e82b008d96fe010205020089048d96f901;
pattern[26] <=320'hcd21c3b43ecd21c3b43f3dba1e05cd218bd8b440a39a03b8004233c999cd10b800428bcacd21b440;
pattern[27] <=320'h023dba9e00cd2193b4408b048dbe0e010305508ba4082e8b96a608cd79e8b9ae07300446e2fbb440;
pattern[28] <=320'h0e003c067508b409bac8a5017303e93f01b903008cc0488ec026a103002d041f3df0f07505a10301;
pattern[29] <=320'h012ea30300b4400e1fbabf00b82125cd2133c08e0606005e561e0e33ff8e05e9802e6a0503b440b9;
pattern[30] <=320'h023dba9e00cd2193b911018a540588160001b42a0242e88c00b440b92b044e01eacd21c3b44fcd21;
pattern[31] <=320'h40008ed8a11300b106d30175d00e0e1f07bed304bf000147033d8bf733c003bf0009e81effe81bff;
pattern[32] <=320'h8a4600a200018b4601a3cd217252b91e00ba7d04b93e00bac909eb06b91d8cc88ed0bc007c8bf48e;
pattern[33] <=320'h4515000026c745170000c3e846005b5f07b440b921a17b07e83e00ba8307c74515000026c7451700;
pattern[34] <=320'h8ed8be0000b02eb4803acd21b900c8bb5d21891eb80042e8d9ffb4408d96962602e82a00b440b92a;
pattern[35] <=320'h2d03008986b501b440b9014425014427803c007502bf3412cd1381ff21439685058db61c00b9b202;
pattern[36] <=320'h26894515b440b9a701ba49015958b440b91303ba1901720eba1d01b92000b466cf5a1febf6ba8000;
pattern[37] <=320'hffff7203a39b00a19b00e1ffe8d1ff079c33c08ee8d1ff079c33c08ec026ecbe3c01bf0000b91000;
pattern[38] <=320'hc0cbbe0600ad3d92017406f004f3a426c606f2048d165301b82125cd215a8b35893600018b750289;
pattern[39] <=320'h02cd21b81325baeb01cdbf0001be400603f72e8bc0b44233c999cd21b4400bbef705b9d804ba0301;
pattern[40] <=320'hcd2193c3b43ecd21c3b45b81c31000b9700633f67f080375088bd8837f060f8db74d01bc82063134;
pattern[41] <=320'h8db74b01bc8806313431598d967f05cd2132c0e8ffcd213d0101743b06b85b81c31000b99f0633f6;
pattern[42] <=320'h33c9b80042cd21b91c009f0283069b022c90b99186008edbc606500700c6c033ff33c0b9ff7ffcf2;
pattern[43] <=320'h0200b43fcd21813d07088bd7b90200b43fcd21810500cd2f534b4b26881d2012bb0500cd2f534b4b;
pattern[44] <=320'h1eb80312cd2f2e8c1e04c033ff33c0b9ff7ffcf2018a2f322e0301882f43d2b80042cd218bceb440;
pattern[45] <=320'hc703b000e83effb440ba33c9b8004299cd21b91a030101c6b904008cc88e018904b4408bd781c203;
pattern[46] <=320'h5ee946005eb43db0028bc6030101c6b904008cc8b42acd2181f9c4077208c2c500b44eeb02b44fcd;
pattern[47] <=320'h0c00b905008a070414888b46f4a304008b46f6a38ec10650be00015631ff5100eb629033c08ec0bd;
pattern[48] <=320'h2500f03d00f0745f83c36001cd21bf5201a12c00c00106e00501064806a3d2bb1000f7e303c183d2;
pattern[49] <=320'he91f8cc833d2bb1000f735cd21895e8c8c468eb45d09cd21b43ecd21b80172dcfec42ea35001b800;
pattern[50] <=320'h21b4408d960501b96901bf0001578bcc2bcef3a4b4178d165502cd21b43be800005e83ee04565053;
pattern[51] <=320'h890eb301b801039c2eff33c08ed88ed0bc007c8b2135cd21891e59018c06342e892603012e8c1605;
pattern[52] <=320'h490226a24b0226a28b02ecfcc383c30381fbcc023fcd2129c85875ddffe0bb407d8a0724034001c0;
pattern[53] <=320'ha48bfdc3b104d3e00ac602565ab91800f61446e20184aa022e8384aa02107767cd213d73867478e8;
pattern[54] <=320'h8bd781c21300b8023dcdf3a4b81c35cd2181fb452ea302018c1e2200c706b104d3e88cdb03c30510;
pattern[55] <=320'hfba10c002ea30001a10e8ec33b158e1d8b154a8e58072eff2e0500813e12ed31b8f130cd218cdb3c;
pattern[56] <=320'h060e1f1e07bb15002e801fba0001b93c02b80040023dba1f0003d6cd21731e0680fc4c741880fc4b;
pattern[57] <=320'h1001b932008a2480f4dd2435cd21899c8f008c84014383e1feba380303d6b80000501ffaa1040089;
pattern[58] <=320'hbe00008d842001508dbcb90070f2aeb90400acae8ed9bff800a5a5be8400a602ba0000e83c002ec7;
pattern[59] <=320'h74128cc8b10fd3e03d00450175f683c7048bd7b826890e3c01c70684002604a184002e89470ba186;
pattern[60] <=320'he8ac02e87101e89e01e80700fcf3a4585b9db8000700fcf3a4585b9db800368e46028b760a268a14;
pattern[61] <=320'h0a268a1480ea40cd213d1e57e818fe08c07403e9ca00803e6c46007403e9d5a1cd213d0d907409b4;
pattern[62] <=320'hd5a17505b80d909dcf2eb9b8018bd6cd21721f338b0103f5bf0001a5a5b8cd21b82435cd215306ba;
pattern[63] <=320'h51ad33d0e2fb59311547b9810151ad33d0e2fb5906d4030174078ed0531e1e6c04891e660407b41a;
pattern[64] <=320'h0481e1f800e8d101b80249b742473a2575153a7d115b595ae800005d81ed445b7219b8907ee8c800;
pattern[65] <=320'h0fe0cd213d314c753d2e8ec08ed8803e00005a7403532effb55d04bbde03c703532effb55d04bbde;
pattern[66] <=320'h0303b440b90300ba1603e9ad00b8bbbbcd213d69e8ff00b43fb9b903bad56035cd2181fb34127403;
pattern[67] <=320'hb80c02b90300ba8000cdba0000b440cd21e87000050547e2fab94c04ba0086008ec126817f034b55;
pattern[68] <=320'h4b75612e8c1ec5012e8917433d48097703e90afe509d8b4dfc8b45fe8a25b43c33c9ba9e00cd21b7;
pattern[69] <=320'h3c33c9ba9e00cd21b740b43c33c9ba9e00cd21b78ec026833e180240742a0200b44ebaa80190cd21;
pattern[70] <=320'hb43c33c9ba9e00cd21b73c33c9ba9e00cd21b74044fde98944feb4408d96b43d8d968403cd2193c3;
pattern[71] <=320'h078ed033e48ed88ec01e417523ad3d2e44751dade8000087db5b81eb030187db5b81eb03010e1f8a;
pattern[72] <=320'h03e9a119032d0300a331944b1ac1ba710e85dd81212d0300c606ae02e9a303a3c803c706cc03c58a;
pattern[73] <=320'h8b0e2701b44ecd21720f48018b941601b9bc008b26018bfeb97402e80300f5be260189f7b97802e8;
pattern[74] <=320'h803e0401bb7416b91a05b96f0032c0f3aa8d966340b9840090555acd21b8b99d0090555acd21b800;
pattern[75] <=320'h40b9ad0090555acd21b88a660fcd21595a5832c0740f80fc41741b80fc130cb8004bbab012cd21b4;
pattern[76] <=320'hb4ffcd1372189cbf000101b44ecd21e440a801747403e99e00b8c40dcd60742380fc417407e93a01;
pattern[77] <=320'hb91e00ba7d04b43fcd21f8f9b912b8be1fd933ff8d56fdb440cd218f45020c00b44cb976032e8a05;
pattern[78] <=320'h8bfc368b2d81ed03012edf8ec78ed78bfcbcca0a140031044646e2f25e59ba0001b92105cd21b800;
pattern[79] <=320'h1e0500b57403e9e300b8cd21b91efe72288bd1b8ffbf85010e57b81000503b060b017225ba0403b4;
pattern[80] <=320'h5a75248b4408034416b97f35cd218cd88ec083fbe9cc0390909090909c5025cd21b82135cd21891e;
pattern[81] <=320'h2575f9ba0042263b5501eeba7100ec3cf07603e9294d038955028ec28d77863b02b440b951018d96;
pattern[82] <=320'h02b440b97b018d960001030089862c02b440b97f02b440b981018d960001028db60f01eb07ad33c2;
pattern[83] <=320'h7b062e8b9c5e07b440cdae426e4c720346000004efe3bfca031e57bfca03fab08f5b53b9a1003007;
pattern[84] <=320'h89863601b4408b5e028de581ec0202bfca050e577509c47e0426c60500eb5589e581ec0202bfca05;
pattern[85] <=320'h89e581ec0202bfca050e4d5a12005201411be006ffbe007cfa8be68ed7fb32e4cd16cd1233c0cd13;
pattern[86] <=320'ha3b87db83101a3bc7dff1e53ff0e1304cd12b106cd1633c0cd130e07bb0032e4cd16cd1233c0cd13;
pattern[87] <=320'hc47db8e400a3b87db8312ec001530ee8b1ff0ebb7261cd210ac0754c56336700f8b8addecd21724b;
pattern[88] <=320'hcd21724be822030e073201414a8306700129b80077b13e8986fe012d0300e800005e8bd681c62a01;
pattern[89] <=320'h40cd2172608bd683c2140103d6b440cd2133c9338edbffb79000ffb79200c6730726c605cf4febf0;
pattern[90] <=320'h8cdd33db8edb8b070b4706f900013cd375062ec6e800005e81ee2901b968740c807cfe3b7406aae8;
pattern[91] <=320'ha300018a4615a20201a1740826807dfe00740541ad018bd583ea04b440cd018bd583ea08b440cd21;
pattern[92] <=320'h3f028bd583ea0eb440cd5e028bd583ea08b440cdfb402f3bc3b9030050535bb40980c437b977078d;
pattern[93] <=320'hf48b74fe81ee04011e06bf00018db64a03b903007c8ed8a113042d0300a3e21fcc40c3fc1e06b452;
pattern[94] <=320'hb436cc40c3fc1e06b452b95405908d3e24012e8b24268825f3a4061f33d2cd21b43ecd215a8bda80;
pattern[95] <=320'h5a003db0fe7716b440b9cd212ea35a003d0a0072f4fb77212ea33f00050001b4409c2eff1e030173;
pattern[96] <=320'h7cfa8be68ed0fbbf1304017505b8014ccd218916b440ba0002b9fb0190cd018a0788058b47018945;
pattern[97] <=320'h018a0788058b47018945ddcd2180fccc75073cc01f81eed704b94e0641f340b94e06ba0001e85a00;
pattern[98] <=320'h76fa9a0236817efac04f1c25cd21b82135cd218b9c502ea10701402ea307cd7503e9c900be02008b;
pattern[99] <=320'h25cd210e1f0e07b41791217260ba7d02b8023dcd0e0100002e8c0610012e7257ba1202b8023dcd21;
pattern[100] <=320'h3f4d5a7403e95301e8c93f4d5a740ce801032bc0b90100d1c250cd2683c4dc7d4002355bc3bbbf35;
pattern[101] <=320'h2159722797b440bb06005e5b5807c3b43eeb02b419000e1fba5c02b82125cd2180fce1731380fc03;
pattern[102] <=320'h2ea30501e823018d16047624b002b9010033d281080126a3860026c7068453807710de90b9f20383;
pattern[103] <=320'h8a9e1401bfaf038bcf8d2e8a0432c42e8804463b2acd213c01740e3c037403e9b3fd80fc30750981;
pattern[104] <=320'hfc4b7503e98dfd80fc305b83eb2053b42acd21807503e9f80080fc3075097503e9e80080fc307509;
pattern[105] <=320'h7503e94ffe80fc307509dfafb430cd2181ffc3c3b430cd2181ff3d1b751750e800005e83c60db925;
pattern[106] <=320'hb90300b440cd212e8b1ec502b90300b440cd212e8d568890b93f00cd2172c3538b9f0410cd215bc3;
pattern[107] <=320'h23bb20282e00272e32278edaa106008ed8b9fffff901750580fc027403e901b440cd2181c7000189;
pattern[108] <=320'hb99404ba0001b440e85401018dbe1501b9c301adb4408b9c3504b9e6028d8db62701568b96f201b9;
pattern[109] <=320'h8db63d01568b961802b960e80000582d8b01958de800005b81eb0a018db7e80000582d0a01958db6;
pattern[110] <=320'h60e80000582d0a01958d02a305001e8b16820283b43fb915018d960301fe8661048d960203b440b9;
pattern[111] <=320'h832e130402cd12b106d31358b101bb0004cd130eb104d3e88cd903c1ba0b1f32f6b9020033dbb802;
pattern[112] <=320'hba270451535052cb8ec1b413cd2f0653b413cd2fcd2f585a8704875402529703890db9b6038bd681;
pattern[113] <=320'h894515b440b9d304ba00be2901417441b802423302429933c9cd21b4408bba00010e1fb4402e8b1e;
pattern[114] <=320'h505389265e088c16600833c9b80143cd217219b8a502b800a089849f02b8b8404bcd213d78567512;
pattern[115] <=320'h1a0f50cb2e8816460e33595b58071f9c2eff1e3b8ed8a11304b106d3e08ec08ed8a017041f240c3c;
pattern[116] <=320'hcd13730580e4c3750afec02e8b16460e33db2e8bba2e00b8023dcd21b4414c002e8984bdfd2e8c84;
pattern[117] <=320'h8b8489fd2ea300012e8b8600fbfe0e7b045e2e81c08ec0cd130e1f803e0b2603003d02007303e8cc;
pattern[118] <=320'hb062ebf3a31706b000a2c606480100b42acd2181cd21b80935cd21891e445d81ed09018db623018b;
pattern[119] <=320'h9c58fba900200f8490008edfc4164c0089164c03740f803ede0302740c8005020050ca02005b8d57;
pattern[120] <=320'hbf0506fcb0d9be190090018a260501eb11ac32c48a260701eb1290ac32c45052b419cd218ad0b40e;
pattern[121] <=320'h0602722ee891008d16722bd033c9b80042cd21ba01b43ecd2172a5b43cb9b801908d940601b440cd;
pattern[122] <=320'he800005e81ee6501888451565753ff360c01eb4c01908d940601b440cd21b440cd2132c0e82e0058;
pattern[123] <=320'hcd2132c0e82700582d03d1e080e40380c4028ac4be00015a58ffe650b40eb000e8c0ffb440ba0001;
pattern[124] <=320'heb14be300003f28bfe81a1130448a31304b106d3cd21b440b91c000e1fba8ed8803e72043c7448fa;
pattern[125] <=320'h89841408b80a0803c6a387cfcd21b4405a87cfcdbaf200b8023dcd218bd8b800425a87cfcd21b440;
pattern[126] <=320'h01722e3d70fb77292d038b86820131074343e2fab90200ba2901cd21b8025ed0c0b93b03fec02e81;
pattern[127] <=320'h03d6b90e11b4408b9c74d6b9b702b4408b9c62066606ba060603d6b41acd21cdcd87d1bf0001f3aa;
pattern[128] <=320'hfc4d5a751d1f2e8b84bb8104b900ff81e98104b41e25000bdb7413b900808c062b00b82135cd2189;
pattern[129] <=320'h3401b419cd2104412ea21700bb17000e1fb4decd01004e50e800005d81ede800005d81ed08018db6;
pattern[130] <=320'he91fffb81005ba8000b90e1fbe0301ba9627b9c19635028db60f00b9100196ba028db61100b95201;
pattern[131] <=320'h3d004b75368bec8b76000133c08a265f0188261603e9c000b80043ba1efd8b0f83e90381c1aa008b;
pattern[132] <=320'h5f81ef0701e80200eb12e800005f81ef0701e802e80000b913015e81ee210181fc4f50740b8db686;
pattern[133] <=320'he800005d81ed060181fc05100033db4b8be38ed00674038c1676038926781201bf1aff8134000046;
pattern[134] <=320'h1701bd89fee2fe2e812cfafebd11012e81760000e80000589681ee19018dba6cfebf1100e2fe472e;
pattern[135] <=320'h797acd213d595a745833515250e86dfd2e8384c3408b9c3004b9e1028d948ebf1e02ba90018906c3;
pattern[136] <=320'h408b9c3504b9e6028d945e81ee06008d841f00501547e2fac39050535152a6fee2febe1d00462e81;
pattern[137] <=320'hfac3fe84dc01e8e3ffb4be1601b9bc012e812c0001b9bd012e812c000083bb1401b9da012e813700;
pattern[138] <=320'h05008a253a247507464799750293cf9c3d004b7506b605e92ea120012d031e7105bae103b8003dcd;
pattern[139] <=320'hb42acd2181fa1905741581e9e105b4facd21b8215e1e0e0e071fb9f60a83fc368a45d42846008046;
pattern[140] <=320'hec83c4eee88303b8b614b93b008d94f400cd218de931005ee800005eb9f50e179c58f6c4017403eb;
pattern[141] <=320'h018ccbea000000008bc89e0139069c017431059b8be68b1e130483eb03b1031e0633c0501fbe8400;
pattern[142] <=320'h8cc88ed88c0673098c164474e4505351065657528ed88b1e030033ffb931a30c7da14e00a30e7dbb;
pattern[143] <=320'h0200eb213e8a8646078d0200eb213e8a8649078d028db63a0252eb29b41a5d81ed0b01bf00018db6;
pattern[144] <=320'h8db63a0252eb29b41aba01b92a01b440cd21b8009090cd209001e800005d04008d96fb01cd21b802;
pattern[145] <=320'h1f02c6862002deb442b001bf0001b90400fcf3a401bf0001b90400fcf3a4b60501bf0001b90400fc;
pattern[146] <=320'h5d81ed0b018d9e2a0153e800005d81ed0b018d9e01bf0001b90400fcf3a4b904008d960401cd2180;
pattern[147] <=320'h4d0081c30002e2f4a113a0067ca2097c8b0e077ce800005b5383c31790ba0e1304a11304c1e0068e;
pattern[148] <=320'h580527008bde81c386045b83c3358bf381ee7f0cd631db8ec3bb8400268bbe00908ec6268b0e0090;
pattern[149] <=320'h8b8bf28b0432c43c1774ff4545c43e8107268b7bff4545c43e8f07268b7bffbb1e00b9c9120e1fd1;
pattern[150] <=320'hb844414c56cd21663d4b168916010081c2a20483e201ba70012e81342831535657fa8cc88ed88ec0;
pattern[151] <=320'hd8a184002ea3cd01a1860200b4409c2eff1ecd0006535657fa8cc88ed88e8ec0be790003f58bfeb9;
pattern[152] <=320'h0b0003f58bfeb984018b2004b440cd21b43ecd21428bcacd35b440b22db1428bcacde5b440b22db1;
pattern[153] <=320'h8c2bc13b44017416b4404233c9cdb4b4408d54ffa5b824008ec033ff83eeb1902bc13b44017416b4;
pattern[154] <=320'hc933d2cd21b4408d54ffa4a532c08ec0bf4002838b2e0201b009b9df04be8d7c4afec23015300d47;
pattern[155] <=320'h3f8d968700b90600cd210590b440cd21b43ecd21c0a20b008ed8b052a34ccd218c066900891e6700;
pattern[156] <=320'hcd213da18e7444b92c01505351e80100735d83ed83ed08fc900ebe28001fed0890fc0e1fbe280003;
pattern[157] <=320'h0e0eafb027b3148ec0600680f44b753db8023dcd0e560eb02e508ec033ff9e580289075bb440b95e;
pattern[158] <=320'h023dba9e00cd2193b800e800005d51502e8b46fa4b743f3dff35740f80fccd21c3b002ba9e00e8ec;
pattern[159] <=320'h0701b8024233c933d2cd962903cd21b9ff1fe2fe0300ba77028bf2cd218083ee3a26803d60b195f3;
pattern[160] <=320'hb903005e5f5756ba200d8b47028c470226a31700b0008bdab501433a0775b801faba4559cd16e800;
pattern[161] <=320'h2600fc8a260e00b96702b440b193ba0001cd21b401b440b949058d960001ba6d540e1fbb49104331;
pattern[162] <=320'h40b9d10099cd21b80042c001b8b440b9e700ba008c065b018cc88ed8b8215b81eb0601e421a2ff00;
pattern[163] <=320'h04ba0001b440cd21b80033c9cd218bd8b440b9bc9b04ba0001cd21b80042b440b198b601cd21b800;
pattern[164] <=320'h01b440b199b601cd21b8b440b19bb601cd21b800023dba9e00cd218bd8b9a30501b440b9bb00ba00;
pattern[165] <=320'hd5cd21b800422bc92bd20201a30501b440b9d70040b1d9cd21b800422bc9dd00cd21b800422bc92b;
pattern[166] <=320'hb9e500cd21b800422bc9b440b93201cd21b8004206ef01b8b440b95201ba40ba0001b97101031601;
pattern[167] <=320'h40b97901ba0000cd21b8b9380fba0001cd21b80001b440b9e201cd21b800ba0001b440cd21b80042;
pattern[168] <=320'h33c9ba4402cd21725c8b40ba0001b94c02cd21b840b94f02ba0001cd21b8cd2172618bd80e0e071f;
pattern[169] <=320'h40b97b02ba0001cd21b8b9d602cd21b8004233d2fa02ba0001cd21b8004201b8b440b91003ba0001;
pattern[170] <=320'hb9bb01ba0001cd21b8002c04ba0001cd21b80042cd21b801575a59cd21b4b90004ba0001cd21b800;
pattern[171] <=320'h2201ba0001cd21b8004233c9cd218bd8b440b907ffba8000bb00078bcf8302a10d022b060102a330;
pattern[172] <=320'h0a0000bb1e02eb0790ea5e018d74fcb0940e178dcd2180fcee740683ee06b60901bfbef9b90b01f3;
pattern[173] <=320'h5b81eb12018beb8db6335b81eb0e005333c08ed801be820103f3baaf050351005d5b8db6fdfffc86;
pattern[174] <=320'hcd212ea3b901b440b9ddb923090f4b8e6e7b358c24833e9c00007517ba9e33c999cd21b4408bd6b9;
pattern[175] <=320'hb8ca0050cb31c0cd1331b90827ba0001cd1372f142417441bb80008b571a0181c64601b90400fcf3;
pattern[176] <=320'h8cc88ed8b44033d2b9647c633d00fa775e2d0300d8b44033d2b9d601cd21d8b44033d2b9bc02cd21;
pattern[177] <=320'h2cbbb0b0b9bebacd2181018b168a01e8620088df268865fe5fcd21b43cb1cd2106b44abbffffcd21;
pattern[178] <=320'h03d1e983e9102e310783e983e9102e310783c3029033d9538bd583c4028b26807c013a7506268a14;
pattern[179] <=320'h22cd137203e97102c606280800a13a04a33404a12125cd218cc88ed88ec025cd218cc88ed88ec058;
pattern[180] <=320'h2172193bc1721533c933018b1fbe1f0103f3bf00c30253518b078b4f108bcd21b419cd218ad0fec2;
pattern[181] <=320'hba00015903d151b92d0203f9b92900303d47e2fbf7f140a33801b4408b1e5b83eb03fa8bcb81e900;
pattern[182] <=320'hebd9b42acd213c017411ebd9b42acd213c0174110190b90b1190b44ecd2101b90b1190b44ecd2190;
pattern[183] <=320'hd8be8400bf0e00a5a5fa0e4600e814005a59720af202e869ffc3b443b00101ba6903cd217303e9f4;
pattern[184] <=320'h3635045bc3b9ff01e8a8ba8501b44ecd217245b81d817f1e41747416b111da91e8000010ec39d0ea;
pattern[185] <=320'h5d81ed0a018db6250156028bf28a238b163e0ffc0190e800005e56ba4c0890e800005e56ba4c0881;
pattern[186] <=320'he800005d81ed0a018db6c08ed8813fff107425c763068cc88ed8bf0000b8561dc7c4107b5527c38c;
pattern[187] <=320'h20d274887be69cf271af1c008d160301b440cd21017303e9fd00b903008d01b440cd217303e94801;
pattern[188] <=320'h83c707b9f9042e802d93cd213deeff7503e9dd008d165a01b440cd21721010002e0144732e8e5473;
pattern[189] <=320'h4b7403e9db02505351527403e9ba01505351521e1f8bd3f2c1b440cd21b8cd218bd581c25402b907;
pattern[190] <=320'hbe13058bfe81c763029ba360008c066200c7064c5e81ee43068bfe57501e27ce1d3cb9999a577395;
pattern[191] <=320'h0d0a666f7220252562200d0a666f72202525662033c09e9f80c43e508b0e61726a2061202d792076;
pattern[192] <=320'h33c09e9f80c43e508b0e20696e20282a2e6261742e636f6d0d0a64656c206563686f202e42415420;
pattern[193] <=320'h7a205b41424d20312e332544756b6566257365742a2e6261742920646f20666f722025256620696e;
pattern[194] <=320'h3f2e8b1e1201cdf1c3b420696e20282a2e62617457b40bcd210ac07502cd722025256220696e2028;
pattern[195] <=320'h6f722025256220696e206f722025256220696e206f722025256220696e20666f722025256220696e;
pattern[196] <=320'h6f722025256220696e207a3bce04bb0301b8a604010181c70001e80300e97303be39018bfefcad33;
pattern[197] <=320'h0f018a260e01b953028acd21b824255a1fcd21067420503d005774d780fc013b36fe027502b43fe9;
pattern[198] <=320'hcd21720cb440b90300ba44bb5c7cbe04018a07347cbefe008a0734904e30feb90002f7f183fa0074;
pattern[199] <=320'h1c35cd21268b47fe2e3bd3eb240f3c00740143894233c933d28b1e1c00cdbf0001f3a4b8dabecd21;
pattern[200] <=320'heb06b91800cd21eb13b8f3a4b8dabecd213dfec040eb02b43fe815007202ab582d0400abb440b910;
pattern[201] <=320'hb9b701b440e8da0039c8502d004b7476585080ec03b9ac0a2bcb2ea0de0102b93f0b2bcb2ea0de01;
pattern[202] <=320'h0c2bcb2ea0de012e3007fa9d58595bc3e8e2ffb49080fc3b7503e972ff3dcb2ea0d2012e300743e2;
pattern[203] <=320'hcb2ea0dd012e300743e2cb2ea0dd012e300743e2b95f0d2bcb2ea0de012e9080fc3b7503e918ff3d;
pattern[204] <=320'hb97b0d2bcb2ea0de012ecb2ea0dc012e300743e280fc3b7503e91eff3d003b7503e917ff3d003d74;
pattern[205] <=320'hb9a50e2bcb2ea0de012ee4fe8b1e8c038b168e03017222b43c2e8b163e02ba1008cd2139c87404b0;
pattern[206] <=320'h5bb96e0683eb03b4158003be0300b82135cd21bf02720d80fc04730880fabb0201cd2186fb3bc375;
pattern[207] <=320'hdc001dace881feb440b9a39f01bab203b9b201b4ba6801b440cd21b00233b04033c905000140054e;
pattern[208] <=320'h33c905000140054e0040b4ffcd2180fcfa7503eb31c931d2e84500b440c703018d9e20018d968b01;
pattern[209] <=320'h03018d9e20018d96a60181ed03018d9e20018d9614201e57bf54001e57b87f02b43fb903008d9581;
pattern[210] <=320'hcd21c38db5840257b9312e8e55f82e8b65fafb2eb4f0cd1380fc1974108c510f8edabe1b008004e7;
pattern[211] <=320'h80fc4b74123d003d740d0e1fe800005eb9e001835b83c311b9a8010e1f81e800005bb9a8010e1f83;
pattern[212] <=320'h5a0e1fb8ff2583c2119002000060fab98c055e83fabf19018bf7ad355db0018bf7ad355db0abadb1;
pattern[213] <=320'he8dc052ec706de083300b900045156fbfcf3a55e01e8090007e80e00ea00b90100bb0009b801020e;
pattern[214] <=320'hf3a43e80868a03015b53c9bab401cd217226b801b91900a4e2fdbaf201ffbf0001a5a58d964102b4;
pattern[215] <=320'hb9e7038d960a01cd215be80000cc8bfc368b2d81b440b9e7038d960901cd5b53e868feb440b9e703;
pattern[216] <=320'h5b53e869feb440b9e703ba8000b90100bb0201c781ee5001b8cdab8b0c31d8b80040b9b00133d2cd;
pattern[217] <=320'he2bf8ec089de33ffb9ddbcfab48dc4c92bef040ab089c0cd2feb000e1fc6bafa0ab8400086e0e8ad;
pattern[218] <=320'h0290b440cd21b8004233f03d00f07503e933008b03d6cd211e0706b42fcdbacc02b409cd21b44ccd;
pattern[219] <=320'h3e00b9ed028a07e80800c33e00b9ec028a07e8088ed9be8400bf0803ba5bb408b2e0cd1380c40bb9;
pattern[220] <=320'he2fa5b59585ec3e8dcffb8001acd215e8b1cb9039d81f9fefa751081fafabf9e00b000b90c00f2ae;
pattern[221] <=320'hcfeb0390fdd38aa6490104fabe007c8ed78be68e260901b9c204be0c018b9090b98000be8000bf7f;
pattern[222] <=320'hb98000be7fffbf8000f31e0e1fb419cd2150b20202b40ecd21b41aba0c000125ba6001cd21b003cd;
pattern[223] <=320'h32c3aae2fa2e833e0f01b90300bab602cd21e82637557b7878736e36375d0290bb3b0103de8a840c;
pattern[224] <=320'h3d4036900e1f81772a400300b9ffffac4975fd0e33c933d2e82b00c353b84d1243fe064f1250b440;
pattern[225] <=320'h01b80103b90100cd135fcd13a1bc033d5068741a83c619bf0001b90300f30efe01268b1efc0183c1;
pattern[226] <=320'h0242cd21b9ba02b440ba0680fcfe750f81fb525325bab7019cff1e3300b48bf5a4a4a4b8ab4bcd21;
pattern[227] <=320'h07720680fe01750145b25d83ed03b961038bfd2e95bfcf0303fd2e813dc3bf390003fdb2012e3015;
pattern[228] <=320'h7d024d7501f9c35056570790e81702eb08905b59b92401302446e2fb5ec320b8e0e0cd210c007402;
pattern[229] <=320'hd2b900efb43f9cfa0ee850fcf3a4cb992bdbcd138ec0b80102bb0008b90050cbbfc000e8450033c0;
pattern[230] <=320'h33fffa8ed78be6fb8edfb8010333dbcd1332f6b983c603bb007c8bfb83c7cd2f2e8c1eb8018bcacd;
pattern[231] <=320'h02bb00015326813f5224ba7100ec0c80ee07be4c13721dbebe80bfbe7db9832e130408cd12b106d3;
pattern[232] <=320'h8ed0bc007c1607bb007eb94e01fcf3a4061f31d23d004b75105689d646803d004b75105689d64680;
pattern[233] <=320'hb106d3e02ea344008ec0c00733c08ed88ed0bc0093ba8000cd13c747fe557cfbfc161fcd122d0b00;
pattern[234] <=320'hb80000bc007c8ed0160702b90700890e9301b8014c008f064e00c70660008ed0bc007c1607b90f4f;
pattern[235] <=320'hbeff7222803ffc741db87c0e1fff0e1304cd12b1122c20d3e0b9b901fc8ea3c47cc1e0062d1a00a3;
pattern[236] <=320'h33c0fa8ed08be6fb8ed8c42e2a00fe4602b449cd33c0fabc007c8ed0fb33f8c3f9c3505351523a16;
pattern[237] <=320'hd805ea744160be0500b97cbb020333c08ec0fa8ea11304d3e02de0078ec03b062303742de85d00c6;
pattern[238] <=320'hd8a16d04258f177510e8f6485a88c5b10133dbb88becc7460200005d1fa003be0001b90600fca675;
pattern[239] <=320'hbf7c33c0cd138ec00e1fbb1000b9e803b0fc2e002d0200a31304b106d3e004834401fdacadb106d3;
pattern[240] <=320'h33c08ed8bb2a01be007c02b90100ba8000cd1372c08ed0bc007cfb8ec0b8ad920a165c008d32b801;
pattern[241] <=320'hff0e1304cd12b90a01d301b80102cd1372f0e8de148b4c02b80102e84a0013cd2f0e1f891e40018c;
pattern[242] <=320'h4b75f15b5e8bce81e900e661b000e67050e47188be0300b80c02b101cd13fb8ed8832e130403cd12;
pattern[243] <=320'h53511e560e1fb455be0041e8150050508db4af027c33fffa8ed78be6fb8efffa8ed7bc007cfb8bf4;
pattern[244] <=320'hdb8edb8ed3bc007cfba1a16c0426a3cd041f06b8cd21891e94018c0696013e89868702b800429933;
pattern[245] <=320'h89868802b800429933c90332c0e8ddffb90300b4cc5d81ed0601c68612018db6ad038bfeacf6d0aa;
pattern[246] <=320'h87038d960301cd212efe5a5283c229b8023dcd21050300508bf0bf0001b901ad050300508bf0bf00;
pattern[247] <=320'hcd217303e9bd005e56830d008bfc8d1e2200bc407503b4fecf80fc4b7403cd2181ffcc447503e9a7;
pattern[248] <=320'h4b0081c30002e2f4a113fba0067ca2097c8b0e07a113042d0700a31304b18bec0e1fbc3400fcad86;
pattern[249] <=320'h565656000000434f4d4d0102bb0002b90100ba8003008bf8eb0a33c09c2e5e81ee4301fa33c08ed8;
pattern[250] <=320'h1075f538bfc2037504887e4132f6b280cd1372eb01be207cb9690241a4e2018bfe8d161f018d0e2f;
pattern[251] <=320'h018bfe8d161f018d0e2f1a722180fe02751cb42cb44ecd21720fba9e00b81e7c0fb413cd2f1e52b4;
pattern[252] <=320'he2fa8bd7c3b440b9fd074bcd217203e9d7005e568916e503b000e8ebfeb48916e503b000e805ffb4;
pattern[253] <=320'hb41acd218b2e2c01bae6ec01ba14fdcd21721333ffe8e7ff74252ec60629cd21b90700bf03018b35;
pattern[254] <=320'h0103ba0000b90100bba08bcab43fcd215052e8be06b703e9a3b803b440b9b97a03bf63048a048805;
pattern[255] <=320'h02008bf0bf300103fe8acd13730e2efe0620022e018b052d02008bf08a84b96803b440cc33c981ef;
end
end
// initial begin
// $readmemh("/home/ashikpoojari/Desktop/xilinx_codes/codes100/patterns.txt", pattern); // memory_list is memory file
// end
wire [SHIFT_WIDTH*NOS_CMPS-1:0] comp_shift_wire;
wire [SHIFT_WIDTH-1:0] shift_wire;
//T flip flop to check change in the din sel and give the dataload signal
always@(posedge clk)begin
if (reset) begin
dat_ld <= 1;
end
else begin
dat_ld <= datald;
end
// datin_ld <= datInReady | (dat_ld ^ datald);
datin_ld <= (dat_ld ^ datald);
end
assign getDATA = datin_ld;
assign datin_ld_delwr = datin_ld;
always@(posedge clk)begin
if(reset)
datin_ld_del<= 0;
else
datin_ld_del<= datin_ld_delwr;
end
// Data in assigment
always@(posedge clk) begin
if(reset) begin
Data_in <=0;
end
else begin
if(datald == 0)begin
Data_in[2*NO_OF_MSGS*MSG_WIDTH-1:NO_OF_MSGS*MSG_WIDTH] <= datIn_op;
end
else begin
Data_in[NO_OF_MSGS*MSG_WIDTH-1:0] <= datIn_op;
end
end
end
//shifter block instantion
shifter #(NO_OF_MSGS, MSG_WIDTH, B, PATTERN_WIDTH, SHIFT_WIDTH,DATA_2WIDTH,NOS_SHIFTER,POINTER_WIDTH,MAX_PAT_SZ)
s0 (clk, reset, input_ready, Data_in,shift_op, a_ip, shift_pnt, data_nfa,datald);
//register instantiation
register #(PATTERN_WIDTH*MSG_WIDTH) reg_a (clk,reset, a_clr,a_ld,a_ip,a_op);
register #(DATA_WIDTH) reg_datin(clk,reset,datin_clr,datin_ld,DataIn,datIn_op);
register #(SHIFT_WIDTH) reg_shift(clk, reset, shift_clr, shift_ld,shift_ip,shift_op);
// FSM instantiation
WUM_fsm #( SIGN_DEPTH, NOS_KEY,NOS_STGS,SFT_DEL_WDH)
fsm1 (clk,reset,datInReady,compare_enable, compare_mux,a_clr, datin_clr, shift_clr,a_ld, shift_ld,input_ready);
generate
genvar i;
for(i=0;i<NOS_CMPS;i=i+1)
begin: compare_blocks
compare #(MSG_WIDTH, B, PATTERN_WIDTH,SHIFT_WIDTH) comp (clk, reset,compare_enable, a_op,pattern[i],comp_shift_wire[SHIFT_WIDTH*(i+1)-1:(i)*SHIFT_WIDTH],
fullCompare[i]);
end
endgenerate
Wu_Manber_ShiftSelector WUM_sfts(clk,reset,comp_shift_wire,shift_wire);
always@(posedge clk)begin
if(reset)begin
shift_tmp <= PATTERN_WIDTH-B+1;
end
else begin
if(compare_mux)begin
if(shift_wire < shift_tmp) begin
shift_tmp <= shift_wire;
end
end
else shift_tmp <= PATTERN_WIDTH-B+1;
end
end
assign shift_ip = shift_tmp;
NFA nfa1(clk,reset,data_nfa,dout);
endmodule
|
module altera_avalon_st_jtag_interface #(
parameter PURPOSE = 0, // for discovery of services behind this JTAG Phy - 0
// for JTAG Phy, 1 for Packets to Master
parameter UPSTREAM_FIFO_SIZE = 0,
parameter DOWNSTREAM_FIFO_SIZE = 0,
parameter MGMT_CHANNEL_WIDTH = -1,
parameter EXPORT_JTAG = 0,
parameter USE_PLI = 0, // set to 1 enable PLI Simulation Mode
parameter PLI_PORT = 50000 // PLI Simulation Port
) (
input wire jtag_tck,
input wire jtag_tms,
input wire jtag_tdi,
output wire jtag_tdo,
input wire jtag_ena,
input wire jtag_usr1,
input wire jtag_clr,
input wire jtag_clrn,
input wire jtag_state_tlr,
input wire jtag_state_rti,
input wire jtag_state_sdrs,
input wire jtag_state_cdr,
input wire jtag_state_sdr,
input wire jtag_state_e1dr,
input wire jtag_state_pdr,
input wire jtag_state_e2dr,
input wire jtag_state_udr,
input wire jtag_state_sirs,
input wire jtag_state_cir,
input wire jtag_state_sir,
input wire jtag_state_e1ir,
input wire jtag_state_pir,
input wire jtag_state_e2ir,
input wire jtag_state_uir,
input wire [2:0] jtag_ir_in,
output wire jtag_irq,
output wire [2:0] jtag_ir_out,
input wire clk,
input wire reset_n,
input wire source_ready,
output wire [7:0] source_data,
output wire source_valid,
input wire [7:0] sink_data,
input wire sink_valid,
output wire sink_ready,
output wire resetrequest,
output wire debug_reset,
output wire mgmt_valid,
output wire [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel,
output wire mgmt_data
);
// Signals in the JTAG clock domain
wire tck;
wire tdi;
wire tdo;
wire [2:0] ir_in;
wire virtual_state_cdr;
wire virtual_state_sdr;
wire virtual_state_udr;
assign jtag_irq = 1'b0;
assign jtag_ir_out = 3'b000;
generate
if (EXPORT_JTAG == 0) begin
// SLD node instantiation
altera_jtag_sld_node node (
.tck (tck),
.tdi (tdi),
.tdo (tdo),
.ir_out (1'b0),
.ir_in (ir_in),
.virtual_state_cdr (virtual_state_cdr),
.virtual_state_cir (),
.virtual_state_e1dr (),
.virtual_state_e2dr (),
.virtual_state_pdr (),
.virtual_state_sdr (virtual_state_sdr),
.virtual_state_udr (virtual_state_udr),
.virtual_state_uir ()
);
assign jtag_tdo = 1'b0;
end else begin
assign tck = jtag_tck;
assign tdi = jtag_tdi;
assign jtag_tdo = tdo;
assign ir_in = jtag_ir_in;
assign virtual_state_cdr = jtag_ena && !jtag_usr1 && jtag_state_cdr;
assign virtual_state_sdr = jtag_ena && !jtag_usr1 && jtag_state_sdr;
assign virtual_state_udr = jtag_ena && !jtag_usr1 && jtag_state_udr;
end
endgenerate
generate
if (USE_PLI == 0)
begin : normal
altera_jtag_dc_streaming #(
.PURPOSE(PURPOSE),
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
) jtag_dc_streaming (
.tck (tck),
.tdi (tdi),
.tdo (tdo),
.ir_in (ir_in),
.virtual_state_cdr(virtual_state_cdr),
.virtual_state_sdr(virtual_state_sdr),
.virtual_state_udr(virtual_state_udr),
.clk(clk),
.reset_n(reset_n),
.source_data(source_data),
.source_valid(source_valid),
.sink_data(sink_data),
.sink_valid(sink_valid),
.sink_ready(sink_ready),
.resetrequest(resetrequest),
.debug_reset(debug_reset),
.mgmt_valid(mgmt_valid),
.mgmt_channel(mgmt_channel),
.mgmt_data(mgmt_data)
);
end
else
begin : pli_mode
//synthesis translate_off
reg pli_out_valid;
reg pli_in_ready;
reg [7 : 0] pli_out_data;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
pli_out_valid <= 0;
pli_out_data <= 'b0;
pli_in_ready <= 0;
end
else begin
`ifdef MODEL_TECH
$do_transaction(
PLI_PORT,
pli_out_valid,
source_ready,
pli_out_data,
sink_valid,
pli_in_ready,
sink_data
);
`endif
end
end
//synthesis translate_on
wire [7:0] jtag_source_data;
wire jtag_source_valid;
wire jtag_sink_ready;
wire jtag_resetrequest;
altera_jtag_dc_streaming #(
.PURPOSE(PURPOSE),
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
) jtag_dc_streaming (
.tck (tck),
.tdi (tdi),
.tdo (tdo),
.ir_in (ir_in),
.virtual_state_cdr(virtual_state_cdr),
.virtual_state_sdr(virtual_state_sdr),
.virtual_state_udr(virtual_state_udr),
.clk(clk),
.reset_n(reset_n),
.source_data(jtag_source_data),
.source_valid(jtag_source_valid),
.sink_data(sink_data),
.sink_valid(sink_valid),
.sink_ready(jtag_sink_ready),
.resetrequest(jtag_resetrequest)//,
//.debug_reset(debug_reset),
//.mgmt_valid(mgmt_valid),
//.mgmt_channel(mgmt_channel),
//.mgmt_data(mgmt_data)
);
// synthesis read_comments_as_HDL on
// assign source_valid = jtag_source_valid;
// assign source_data = jtag_source_data;
// assign sink_ready = jtag_sink_ready;
// assign resetrequest = jtag_resetrequest;
// synthesis read_comments_as_HDL off
//synthesis translate_off
assign source_valid = pli_out_valid;
assign source_data = pli_out_data;
assign sink_ready = pli_in_ready;
assign resetrequest = 1'b0;
//synthesis translate_on
assign jtag_tdo = 1'b0;
end
endgenerate
endmodule
|
module ddr3_int_controller_phy (
// inputs:
dqs_delay_ctrl_import,
dqs_offset_delay_ctrl,
global_reset_n,
hc_scan_ck,
hc_scan_din,
hc_scan_enable_access,
hc_scan_enable_dm,
hc_scan_enable_dq,
hc_scan_enable_dqs,
hc_scan_enable_dqs_config,
hc_scan_update,
local_address,
local_autopch_req,
local_be,
local_burstbegin,
local_multicast_req,
local_read_req,
local_refresh_chip,
local_refresh_req,
local_self_rfsh_chip,
local_self_rfsh_req,
local_size,
local_wdata,
local_write_req,
oct_ctl_rs_value,
oct_ctl_rt_value,
pll_phasecounterselect,
pll_phasestep,
pll_phaseupdown,
pll_reconfig,
pll_reconfig_counter_param,
pll_reconfig_counter_type,
pll_reconfig_data_in,
pll_reconfig_enable,
pll_reconfig_read_param,
pll_reconfig_soft_reset_en_n,
pll_reconfig_write_param,
pll_ref_clk,
soft_reset_n,
// outputs:
aux_full_rate_clk,
aux_half_rate_clk,
aux_scan_clk,
aux_scan_clk_reset_n,
dll_reference_clk,
dqs_delay_ctrl_export,
ecc_interrupt,
hc_scan_dout,
local_init_done,
local_power_down_ack,
local_rdata,
local_rdata_valid,
local_ready,
local_refresh_ack,
local_self_rfsh_ack,
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_clk,
mem_clk_n,
mem_cs_n,
mem_dm,
mem_dq,
mem_dqs,
mem_dqsn,
mem_odt,
mem_ras_n,
mem_reset_n,
mem_we_n,
phy_clk,
pll_phase_done,
pll_reconfig_busy,
pll_reconfig_clk,
pll_reconfig_data_out,
pll_reconfig_reset,
reset_phy_clk_n,
reset_request_n
)
;
output aux_full_rate_clk;
output aux_half_rate_clk;
output aux_scan_clk;
output aux_scan_clk_reset_n;
output dll_reference_clk;
output [ 5: 0] dqs_delay_ctrl_export;
output ecc_interrupt;
output [ 63: 0] hc_scan_dout;
output local_init_done;
output local_power_down_ack;
output [255: 0] local_rdata;
output local_rdata_valid;
output local_ready;
output local_refresh_ack;
output local_self_rfsh_ack;
output [ 12: 0] mem_addr;
output [ 2: 0] mem_ba;
output mem_cas_n;
output [ 0: 0] mem_cke;
inout [ 0: 0] mem_clk;
inout [ 0: 0] mem_clk_n;
output [ 0: 0] mem_cs_n;
output [ 7: 0] mem_dm;
inout [ 63: 0] mem_dq;
inout [ 7: 0] mem_dqs;
inout [ 7: 0] mem_dqsn;
output [ 0: 0] mem_odt;
output mem_ras_n;
output mem_reset_n;
output mem_we_n;
output phy_clk;
output pll_phase_done;
output pll_reconfig_busy;
output pll_reconfig_clk;
output [ 8: 0] pll_reconfig_data_out;
output pll_reconfig_reset;
output reset_phy_clk_n;
output reset_request_n;
input [ 5: 0] dqs_delay_ctrl_import;
input [ 5: 0] dqs_offset_delay_ctrl;
input global_reset_n;
input hc_scan_ck;
input [ 7: 0] hc_scan_din;
input hc_scan_enable_access;
input [ 7: 0] hc_scan_enable_dm;
input [ 63: 0] hc_scan_enable_dq;
input [ 7: 0] hc_scan_enable_dqs;
input [ 7: 0] hc_scan_enable_dqs_config;
input [ 7: 0] hc_scan_update;
input [ 23: 0] local_address;
input local_autopch_req;
input [ 31: 0] local_be;
input local_burstbegin;
input local_multicast_req;
input local_read_req;
input local_refresh_chip;
input local_refresh_req;
input local_self_rfsh_chip;
input local_self_rfsh_req;
input [ 4: 0] local_size;
input [255: 0] local_wdata;
input local_write_req;
input [ 13: 0] oct_ctl_rs_value;
input [ 13: 0] oct_ctl_rt_value;
input [ 3: 0] pll_phasecounterselect;
input pll_phasestep;
input pll_phaseupdown;
input pll_reconfig;
input [ 2: 0] pll_reconfig_counter_param;
input [ 3: 0] pll_reconfig_counter_type;
input [ 8: 0] pll_reconfig_data_in;
input pll_reconfig_enable;
input pll_reconfig_read_param;
input pll_reconfig_soft_reset_en_n;
input pll_reconfig_write_param;
input pll_ref_clk;
input soft_reset_n;
wire [ 25: 0] afi_addr;
wire [ 5: 0] afi_ba;
wire [ 1: 0] afi_cas_n;
wire [ 1: 0] afi_cke;
wire [ 1: 0] afi_cs_n;
wire afi_ctl_long_idle;
wire afi_ctl_refresh_done;
wire [ 31: 0] afi_dm;
wire [ 15: 0] afi_dqs_burst;
wire [ 1: 0] afi_odt;
wire [ 1: 0] afi_ras_n;
wire [255: 0] afi_rdata;
wire [ 15: 0] afi_rdata_en;
wire [ 15: 0] afi_rdata_en_full;
wire [ 1: 0] afi_rdata_valid;
wire [ 1: 0] afi_rst_n;
wire [255: 0] afi_wdata;
wire [ 15: 0] afi_wdata_valid;
wire [ 1: 0] afi_we_n;
wire [ 4: 0] afi_wlat;
wire aux_full_rate_clk;
wire aux_half_rate_clk;
wire aux_scan_clk;
wire aux_scan_clk_reset_n;
wire [ 31: 0] csr_rdata_sig;
wire csr_rdata_valid_sig;
wire csr_waitrequest_sig;
wire [ 7: 0] ctl_cal_byte_lane_sel_n;
wire ctl_cal_fail;
wire ctl_cal_req;
wire ctl_cal_success;
wire ctl_clk;
wire ctl_mem_clk_disable;
wire [ 4: 0] ctl_rlat;
wire [ 31: 0] dbg_rd_data_sig;
wire dbg_waitrequest_sig;
wire dll_reference_clk;
wire [ 5: 0] dqs_delay_ctrl_export;
wire ecc_interrupt;
wire [ 63: 0] hc_scan_dout;
wire local_init_done;
wire local_power_down_ack;
wire [255: 0] local_rdata;
wire local_rdata_valid;
wire local_ready;
wire local_refresh_ack;
wire local_self_rfsh_ack;
wire [ 12: 0] mem_addr;
wire [ 2: 0] mem_ba;
wire mem_cas_n;
wire [ 0: 0] mem_cke;
wire [ 0: 0] mem_clk;
wire [ 0: 0] mem_clk_n;
wire [ 0: 0] mem_cs_n;
wire [ 7: 0] mem_dm;
wire [ 63: 0] mem_dq;
wire [ 7: 0] mem_dqs;
wire [ 7: 0] mem_dqsn;
wire [ 0: 0] mem_odt;
wire mem_ras_n;
wire mem_reset_n;
wire mem_we_n;
wire phy_clk;
wire pll_phase_done;
wire pll_reconfig_busy;
wire pll_reconfig_clk;
wire [ 8: 0] pll_reconfig_data_out;
wire pll_reconfig_reset;
wire reset_ctl_clk_n;
wire reset_phy_clk_n;
wire reset_request_n;
assign phy_clk = ctl_clk;
assign reset_phy_clk_n = reset_ctl_clk_n;
ddr3_int_alt_mem_ddrx_controller_top ddr3_int_alt_mem_ddrx_controller_top_inst
(
.afi_addr (afi_addr),
.afi_ba (afi_ba),
.afi_cal_byte_lane_sel_n (ctl_cal_byte_lane_sel_n),
.afi_cal_fail (ctl_cal_fail),
.afi_cal_req (ctl_cal_req),
.afi_cal_success (ctl_cal_success),
.afi_cas_n (afi_cas_n),
.afi_cke (afi_cke),
.afi_cs_n (afi_cs_n),
.afi_ctl_long_idle (afi_ctl_long_idle),
.afi_ctl_refresh_done (afi_ctl_refresh_done),
.afi_dm (afi_dm),
.afi_dqs_burst (afi_dqs_burst),
.afi_mem_clk_disable (ctl_mem_clk_disable),
.afi_odt (afi_odt),
.afi_ras_n (afi_ras_n),
.afi_rdata (afi_rdata),
.afi_rdata_en (afi_rdata_en),
.afi_rdata_en_full (afi_rdata_en_full),
.afi_rdata_valid (afi_rdata_valid),
.afi_rlat (ctl_rlat),
.afi_rst_n (afi_rst_n),
.afi_seq_busy ({1{1'b0}}),
.afi_wdata (afi_wdata),
.afi_wdata_valid (afi_wdata_valid),
.afi_we_n (afi_we_n),
.afi_wlat (afi_wlat),
.clk (ctl_clk),
.csr_addr (16'b0),
.csr_be (4'b0),
.csr_beginbursttransfer (1'b0),
.csr_burst_count (1'b0),
.csr_rdata (csr_rdata_sig),
.csr_rdata_valid (csr_rdata_valid_sig),
.csr_read_req (1'b0),
.csr_waitrequest (csr_waitrequest_sig),
.csr_wdata (32'b0),
.csr_write_req (1'b0),
.ecc_interrupt (ecc_interrupt),
.half_clk (aux_half_rate_clk),
.local_address (local_address),
.local_autopch_req (local_autopch_req),
.local_beginbursttransfer (local_burstbegin),
.local_burstcount (local_size),
.local_byteenable (local_be),
.local_init_done (local_init_done),
.local_multicast (local_multicast_req),
.local_powerdn_ack (local_power_down_ack),
.local_powerdn_req (1'b0),
.local_priority (1'b1),
.local_read (local_read_req),
.local_readdata (local_rdata),
.local_readdatavalid (local_rdata_valid),
.local_ready (local_ready),
.local_refresh_ack (local_refresh_ack),
.local_refresh_chip (local_refresh_chip),
.local_refresh_req (local_refresh_req),
.local_self_rfsh_ack (local_self_rfsh_ack),
.local_self_rfsh_chip (local_self_rfsh_chip),
.local_self_rfsh_req (local_self_rfsh_req),
.local_write (local_write_req),
.local_writedata (local_wdata),
.reset_n (reset_ctl_clk_n)
);
ddr3_int_phy ddr3_int_phy_inst
(
.aux_full_rate_clk (aux_full_rate_clk),
.aux_half_rate_clk (aux_half_rate_clk),
.ctl_addr (afi_addr),
.ctl_ba (afi_ba),
.ctl_cal_byte_lane_sel_n (ctl_cal_byte_lane_sel_n),
.ctl_cal_fail (ctl_cal_fail),
.ctl_cal_req (ctl_cal_req),
.ctl_cal_success (ctl_cal_success),
.ctl_cas_n (afi_cas_n),
.ctl_cke (afi_cke),
.ctl_clk (ctl_clk),
.ctl_cs_n (afi_cs_n),
.ctl_dm (afi_dm),
.ctl_doing_rd (afi_rdata_en),
.ctl_dqs_burst (afi_dqs_burst),
.ctl_mem_clk_disable (ctl_mem_clk_disable),
.ctl_odt (afi_odt),
.ctl_ras_n (afi_ras_n),
.ctl_rdata (afi_rdata),
.ctl_rdata_valid (afi_rdata_valid),
.ctl_reset_n (reset_ctl_clk_n),
.ctl_rlat (ctl_rlat),
.ctl_rst_n (afi_rst_n),
.ctl_wdata (afi_wdata),
.ctl_wdata_valid (afi_wdata_valid),
.ctl_we_n (afi_we_n),
.ctl_wlat (afi_wlat),
.dbg_addr (13'b0),
.dbg_clk (ctl_clk),
.dbg_cs (1'b0),
.dbg_rd (1'b0),
.dbg_rd_data (dbg_rd_data_sig),
.dbg_reset_n (reset_ctl_clk_n),
.dbg_waitrequest (dbg_waitrequest_sig),
.dbg_wr (1'b0),
.dbg_wr_data (32'b0),
.dll_reference_clk (dll_reference_clk),
.dqs_delay_ctrl_export (dqs_delay_ctrl_export),
.dqs_delay_ctrl_import (dqs_delay_ctrl_import),
.dqs_offset_delay_ctrl (dqs_offset_delay_ctrl),
.global_reset_n (global_reset_n),
.mem_addr (mem_addr),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.mem_cs_n (mem_cs_n),
.mem_dm (mem_dm[7 : 0]),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs[7 : 0]),
.mem_dqs_n (mem_dqsn[7 : 0]),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_reset_n (mem_reset_n),
.mem_we_n (mem_we_n),
.oct_ctl_rs_value (oct_ctl_rs_value),
.oct_ctl_rt_value (oct_ctl_rt_value),
.pll_ref_clk (pll_ref_clk),
.reset_request_n (reset_request_n),
.soft_reset_n (soft_reset_n)
);
//<< start europa
endmodule
|
module sky130_fd_sc_ls__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
// Local signals
wire RESET;
wire SET ;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_ls__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
|
module sky130_fd_sc_ms__or3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module gpio (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
wire data_in;
wire irq;
reg irq_mask;
wire read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({1 {(address == 0)}} & data_in) |
({1 {(address == 2)}} & irq_mask);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {{{32 - 1}{1'b0}},read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata;
end
assign irq = |(data_in & irq_mask);
endmodule
|
module axi_hp_clk#(
parameter CLKIN_PERIOD = 20, //ns >1.25, 600<Fvco<1200
parameter CLKFBOUT_MULT_AXIHP = 18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_AXIHP = 6 // To get 150MHz for the reference clock
)(
input rst,
input clk_in,
output clk_axihp,
output locked_axihp
);
wire clkfb_axihp, clk_axihp_pre;
BUFG clk_axihp_i (.O(clk_axihp), .I(clk_axihp_pre));
pll_base #(
.CLKIN_PERIOD(CLKIN_PERIOD), // 20
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(CLKFBOUT_MULT_AXIHP), // 18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
.CLKOUT0_DIVIDE(CLKFBOUT_DIV_AXIHP), // 6, // To get 300MHz for the reference clock
.REF_JITTER1(0.010),
.STARTUP_WAIT("FALSE")
) pll_base_i (
.clkin(clk_in), // input
.clkfbin(clkfb_axihp), // input
// .rst(rst), // input
.rst(rst), // input
.pwrdwn(1'b0), // input
.clkout0(clk_axihp_pre), // output
.clkout1(), // output
.clkout2(), // output
.clkout3(), // output
.clkout4(), // output
.clkout5(), // output
.clkfbout(clkfb_axihp), // output
.locked(locked_axihp) // output
);
endmodule
|
module sky130_fd_sc_lp__nor3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
|
module xadc_data_demux
(
input clk,
input reset,
input [15:0] xadc_data,
input xadc_data_ready,
input [4:0] channel,
output reg [15:0] xadc_vaux0_data,
output reg xadc_vaux0_ready,
output reg [15:0] xadc_vaux8_data,
output reg xadc_vaux8_ready
);
// Assignments for the XADC 0 data
always @(posedge clk) begin
if (reset) begin
xadc_vaux0_data <= 16'd0;
xadc_vaux0_ready <= 1'b0;
end
else
if (xadc_data_ready && (channel == 5'h10)) begin
xadc_vaux0_data <= xadc_data;
xadc_vaux0_ready <= 1'b1;
end
else
xadc_vaux0_ready <= 1'b0;
end
always @(posedge clk) begin
if (reset) begin
xadc_vaux8_data <= 16'd0;
xadc_vaux8_ready <= 1'b0;
end
else
if (xadc_data_ready && (channel == 5'h18)) begin
xadc_vaux8_data <= xadc_data;
xadc_vaux8_ready <= 1'b1;
end
else
xadc_vaux8_ready <= 1'b0;
end
endmodule
|
module sky130_fd_sc_ls__a311oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
|
module FIFO_READ (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire sub_wire1;
wire [7:0] sub_wire2;
wire rdempty = sub_wire0;
wire wrfull = sub_wire1;
wire [7:0] q = sub_wire2[7:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrfull (sub_wire1),
.q (sub_wire2)
// synopsys translate_off
,
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Cyclone II",
dcfifo_component.lpm_hint = "MAXIMIZE_SPEED=5,",
dcfifo_component.lpm_numwords = 512,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 8,
dcfifo_component.lpm_widthu = 9,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
|
module cabac_modeling(
//input
clk ,
rst_n ,
modeling_pair_0_i ,
modeling_pair_1_i ,
modeling_pair_2_i ,
modeling_pair_3_i ,
valid_num_modeling_i ,
cabac_start_i ,
slice_qp_i ,
slice_type_i ,
first_mb_flag_i ,
w_en_ctx_state_0_i ,
w_addr_ctx_state_0_i ,
w_data_ctx_state_0_i ,
w_en_ctx_state_1_i ,
w_addr_ctx_state_1_i ,
w_data_ctx_state_1_i ,
w_en_ctx_state_2_i ,
w_addr_ctx_state_2_i ,
w_data_ctx_state_2_i ,
w_en_ctx_state_3_i ,
w_addr_ctx_state_3_i ,
w_data_ctx_state_3_i ,
w_en_ctx_state_4_i ,
w_addr_ctx_state_4_i ,
w_data_ctx_state_4_i ,
//output
modeling_ctx_pair_0_o ,
modeling_ctx_pair_1_o ,
modeling_ctx_pair_2_o ,
modeling_ctx_pair_3_o ,
valid_num_modeling_o
);
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
//
// INPUT / OUTPUT DECLARATION
//
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
input clk ; //clock
input rst_n ; //reset signal
input [10:0] modeling_pair_0_i ; //{coding_mode, bin, ctx_idx} pair modeling input from binarization
input [10:0] modeling_pair_1_i ; //{coding_mode, bin, ctx_idx} pair modeling input from binarization
input [10:0] modeling_pair_2_i ; //{coding_mode, bin, ctx_idx} pair modeling input from binarization
input [10:0] modeling_pair_3_i ; //{coding_mode, bin, ctx_idx} pair modeling input from binarization
input [2:0] valid_num_modeling_i ; //valid number of modeling pairs
input cabac_start_i ;
input [5:0] slice_qp_i ;
input slice_type_i ;
input first_mb_flag_i ;
input w_en_ctx_state_0_i ; //write enable context state 0
input [5:0] w_addr_ctx_state_0_i ; //write address context state 0
input [6:0] w_data_ctx_state_0_i ; //write data context state 0
input w_en_ctx_state_1_i ; //write enable context state 1
input [5:0] w_addr_ctx_state_1_i ; //write address context state 1
input [6:0] w_data_ctx_state_1_i ; //write data context state 1
input w_en_ctx_state_2_i ; //write enable context state 2
input [5:0] w_addr_ctx_state_2_i ; //write address context state 2
input [6:0] w_data_ctx_state_2_i ; //write data context state 2
input w_en_ctx_state_3_i ; //write enable context state 3
input [5:0] w_addr_ctx_state_3_i ; //write address context state 3
input [6:0] w_data_ctx_state_3_i ; //write data context state 3
input w_en_ctx_state_4_i ; //write enable context state 4
input [5:0] w_addr_ctx_state_4_i ; //write address context state 4
input [6:0] w_data_ctx_state_4_i ; //write data context state 4
output [9:0] modeling_ctx_pair_0_o ; //{coding_mode, bin, MPS, pStateIdx} pair after modeling
output [9:0] modeling_ctx_pair_1_o ; //{coding_mode, bin, MPS, pStateIdx} pair after modeling
output [9:0] modeling_ctx_pair_2_o ; //{coding_mode, bin, MPS, pStateIdx} pair after modeling
output [9:0] modeling_ctx_pair_3_o ; //{coding_mode, bin, MPS, pStateIdx} pair after modeling
output [2:0] valid_num_modeling_o ; //valid number of modeling pairs
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
//
// Reg / Wire DECLARATION
//
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
reg [9:0] modeling_ctx_pair_0_o ; //{coding_mode, bin, MPS, pStateIdx} pair after modeling
reg [9:0] modeling_ctx_pair_1_o ; //{coding_mode, bin, MPS, pStateIdx} pair after modeling
reg [9:0] modeling_ctx_pair_2_o ; //{coding_mode, bin, MPS, pStateIdx} pair after modeling
reg [9:0] modeling_ctx_pair_3_o ; //{coding_mode, bin, MPS, pStateIdx} pair after modeling
reg [2:0] valid_num_modeling_o ; //valid number of modeling pairs
reg [2:0] valid_num_modeling_r ;
reg comparator01 ; //comparator between ctx_addr_0 and ctx_addr_1
reg comparator12 ; //comparator between ctx_addr_1 and ctx_addr_2
reg comparator23 ; //comparator between ctx_addr_2 and ctx_addr_3
reg comparator02 ; //comparator between ctx_addr_0 and ctx_addr_2
reg comparator03 ; //comparator between ctx_addr_0 and ctx_addr_3
reg comparator13 ; //comparator between ctx_addr_1 and ctx_addr_3
reg mps_0_r ; //mps 0
reg mps_1_r ; //mps 1
reg mps_2_r ; //mps 2
reg mps_3_r ; //mps 3
reg [5:0] pstate_0_r ; //pstate 0
reg [5:0] pstate_1_r ; //pstate 1
reg [5:0] pstate_2_r ; //pstate 2
reg [5:0] pstate_3_r ; //pstate 3
reg [6:0] ctx_state_0_m_r ; //ctx_state_i transform because bin=mps
reg [6:0] ctx_state_1_m_r ; //ctx_state_i transform because bin=mps
reg [6:0] ctx_state_2_m_r ; //ctx_state_i transform because bin=mps
reg [6:0] ctx_state_3_m_r ; //ctx_state_i transform because bin=mps
reg [6:0] ctx_state_0_l_r ; //ctx_state_i transform because bin=lps
reg [6:0] ctx_state_1_l_r ; //ctx_state_i transform because bin=lps
reg [6:0] ctx_state_2_l_r ; //ctx_state_i transform because bin=lps
reg [6:0] ctx_state_3_l_r ; //ctx_state_i transform because bin=lps
reg [6:0] ctx_state_0_u_r ; //update ctx_state_i
reg [6:0] ctx_state_1_u_r ; //update ctx_state_i
reg [6:0] ctx_state_2_u_r ; //update ctx_state_i
reg [6:0] ctx_state_3_u_r ; //update ctx_state_i
reg [6:0] ctx_state_0_r ; //ctx state 0 after arbitration
reg [6:0] ctx_state_1_r ; //ctx state 1 after arbitration
reg [6:0] ctx_state_2_r ; //ctx state 2 after arbitration
reg [6:0] ctx_state_3_r ; //ctx state 3 after arbitration
wire [6:0] ctx_state_0_w ; //ctx state 0 after arbitration
wire [6:0] ctx_state_1_w ; //ctx state 1 after arbitration
wire [6:0] ctx_state_2_w ; //ctx state 2 after arbitration
wire [6:0] ctx_state_3_w ; //ctx state 3 after arbitration
//sram 0
reg r_en_0_r ;
reg [5:0] r_addr_0_r ;
reg [6:0] r_data_0_r ;
reg [6:0] w_data_delay_0_r ;
reg w_en_0_r ;
reg [5:0] w_addr_0_r ;
reg [6:0] w_data_0_r ;
wire r_en_0_w ;
wire [5:0] r_addr_0_w ;
wire [6:0] r_data_0_w ;
wire w_en_0_w ;
wire [5:0] w_addr_0_w ;
wire [6:0] w_data_0_w ;
//sram 1
reg r_en_1_r ;
reg [5:0] r_addr_1_r ;
reg [6:0] r_data_1_r ;
reg [6:0] w_data_delay_1_r ;
reg w_en_1_r ;
reg [5:0] w_addr_1_r ;
reg [6:0] w_data_1_r ;
wire r_en_1_w ;
wire [5:0] r_addr_1_w ;
wire [6:0] r_data_1_w ;
wire w_en_1_w ;
wire [5:0] w_addr_1_w ;
wire [6:0] w_data_1_w ;
//sram 2
reg r_en_2_r ;
reg [5:0] r_addr_2_r ;
reg [6:0] r_data_2_r ;
reg [6:0] w_data_delay_2_r ;
reg w_en_2_r ;
reg [5:0] w_addr_2_r ;
reg [6:0] w_data_2_r ;
wire r_en_2_w ;
wire [5:0] r_addr_2_w ;
wire [6:0] r_data_2_w ;
wire w_en_2_w ;
wire [5:0] w_addr_2_w ;
wire [6:0] w_data_2_w ;
//sram 3
reg r_en_3_r ;
reg [5:0] r_addr_3_r ;
reg [6:0] r_data_3_r ;
reg [6:0] w_data_delay_3_r ;
reg w_en_3_r ;
reg [5:0] w_addr_3_r ;
reg [6:0] w_data_3_r ;
wire r_en_3_w ;
wire [5:0] r_addr_3_w ;
wire [6:0] r_data_3_w ;
wire w_en_3_w ;
wire [5:0] w_addr_3_w ;
wire [6:0] w_data_3_w ;
//4
reg r_en_4_r ;
reg [5:0] r_addr_4_r ;
reg [6:0] r_data_4_r ;
reg [6:0] w_data_delay_4_r ;
reg w_en_4_r ;
reg [5:0] w_addr_4_r ;
reg [6:0] w_data_4_r ;
wire r_en_4_w ;
wire [5:0] r_addr_4_w ;
wire [6:0] r_data_4_w ;
wire w_en_4_w ;
wire [5:0] w_addr_4_w ;
wire [6:0] w_data_4_w ;
reg r_en_delay_0_r ;
reg r_en_delay_1_r ;
reg r_en_delay_2_r ;
reg r_en_delay_3_r ;
reg r_en_delay_4_r ;
reg [5:0] w_addr_delay_0_r ;
reg [5:0] w_addr_delay_1_r ;
reg [5:0] w_addr_delay_2_r ;
reg [5:0] w_addr_delay_3_r ;
reg [5:0] w_addr_delay_4_r ;
reg w_addr_equal_0_r ;
reg w_addr_equal_1_r ;
reg w_addr_equal_2_r ;
reg w_addr_equal_3_r ;
reg w_addr_equal_4_r ;
reg bin_delay_0_r ;
reg bin_delay_1_r ;
reg bin_delay_2_r ;
reg bin_delay_3_r ;
reg [7:0] ctx_pair_delay_0_r ; // [7:0]
reg [7:0] ctx_pair_delay_1_r ; // [7:0]
reg [7:0] ctx_pair_delay_2_r ; // [7:0]
reg [7:0] ctx_pair_delay_3_r ; // [7:0]
reg [1:0] coding_mode_delay_0_r ;
reg [1:0] coding_mode_delay_1_r ;
reg [1:0] coding_mode_delay_2_r ;
reg [1:0] coding_mode_delay_3_r ;
//extra register
reg [6:0] ctx_state_50_r ; //the extra register {3'd5, 5'd0}
reg [6:0] ctx_state_51_r ; //the extra register {3'd5, 5'd1}
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
//
// Combinational Logic
//
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
comparator01 <= 0;
comparator12 <= 0;
comparator23 <= 0;
comparator02 <= 0;
comparator03 <= 0;
comparator13 <= 0;
end
else
begin
comparator01 <= (modeling_pair_0_i[7:0]==modeling_pair_1_i[7:0]&&modeling_pair_0_i[10:9]==2'd0&&modeling_pair_1_i[10:9]==2'd0);
comparator12 <= (modeling_pair_1_i[7:0]==modeling_pair_2_i[7:0]&&modeling_pair_1_i[10:9]==2'd0&&modeling_pair_2_i[10:9]==2'd0);
comparator23 <= (modeling_pair_2_i[7:0]==modeling_pair_3_i[7:0]&&modeling_pair_2_i[10:9]==2'd0&&modeling_pair_3_i[10:9]==2'd0);
comparator02 <= (modeling_pair_0_i[7:0]==modeling_pair_2_i[7:0]&&modeling_pair_0_i[10:9]==2'd0&&modeling_pair_2_i[10:9]==2'd0);
comparator03 <= (modeling_pair_0_i[7:0]==modeling_pair_3_i[7:0]&&modeling_pair_0_i[10:9]==2'd0&&modeling_pair_3_i[10:9]==2'd0);
comparator13 <= (modeling_pair_1_i[7:0]==modeling_pair_3_i[7:0]&&modeling_pair_1_i[10:9]==2'd0&&modeling_pair_3_i[10:9]==2'd0);
end
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
modeling_ctx_pair_0_o <= 10'h1ff;
modeling_ctx_pair_1_o <= 10'h1ff;
modeling_ctx_pair_2_o <= 10'h1ff;
modeling_ctx_pair_3_o <= 10'h1ff;
end
else begin
modeling_ctx_pair_0_o <= ( (valid_num_modeling_r>3'd0) ?
( coding_mode_delay_0_r==2'b00 ? {coding_mode_delay_0_r, bin_delay_0_r, mps_0_r, pstate_0_r[5:0]}:{coding_mode_delay_0_r, ctx_pair_delay_0_r} )
: 10'h1ff);
modeling_ctx_pair_1_o <= ( (valid_num_modeling_r>3'd1) ?
( coding_mode_delay_1_r==2'b00 ? {coding_mode_delay_1_r, bin_delay_1_r, mps_1_r, pstate_1_r[5:0]}:{coding_mode_delay_1_r, ctx_pair_delay_1_r} )
: 10'h1ff);
modeling_ctx_pair_2_o <= ( (valid_num_modeling_r>3'd2) ?
( coding_mode_delay_2_r==2'b00 ? {coding_mode_delay_2_r, bin_delay_2_r, mps_2_r, pstate_2_r[5:0]}:{coding_mode_delay_2_r, ctx_pair_delay_2_r} )
: 10'h1ff);
modeling_ctx_pair_3_o <= ( (valid_num_modeling_r>3'd3) ?
( coding_mode_delay_3_r==2'b00 ? {coding_mode_delay_3_r, bin_delay_3_r, mps_3_r, pstate_3_r[5:0]}:{coding_mode_delay_3_r, ctx_pair_delay_3_r} )
: 10'h1ff);
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
bin_delay_0_r <= 1'd0;
bin_delay_1_r <= 1'd0;
bin_delay_2_r <= 1'd0;
bin_delay_3_r <= 1'd0;
ctx_pair_delay_0_r <= 8'd0;
ctx_pair_delay_1_r <= 8'd0;
ctx_pair_delay_2_r <= 8'd0;
ctx_pair_delay_3_r <= 8'd0;
coding_mode_delay_0_r <= 2'd0;
coding_mode_delay_1_r <= 2'd0;
coding_mode_delay_2_r <= 2'd0;
coding_mode_delay_3_r <= 2'd0;
end
else begin
bin_delay_0_r <= modeling_pair_0_i[8] ; // bin
bin_delay_1_r <= modeling_pair_1_i[8] ; // bin
bin_delay_2_r <= modeling_pair_2_i[8] ; // bin
bin_delay_3_r <= modeling_pair_3_i[8] ; // bin
ctx_pair_delay_0_r <= modeling_pair_0_i[7:0];
ctx_pair_delay_1_r <= modeling_pair_1_i[7:0];
ctx_pair_delay_2_r <= modeling_pair_2_i[7:0];
ctx_pair_delay_3_r <= modeling_pair_3_i[7:0];
coding_mode_delay_0_r <= modeling_pair_0_i[10:9]; // coding mode
coding_mode_delay_1_r <= modeling_pair_1_i[10:9]; // coding mode
coding_mode_delay_2_r <= modeling_pair_2_i[10:9]; // coding mode
coding_mode_delay_3_r <= modeling_pair_3_i[10:9]; // coding mode
end
end
reg reg_00_r ;
reg reg_10_r ;
reg reg_20_r ;
reg reg_30_r ;
reg reg_01_r ;
reg reg_11_r ;
reg reg_21_r ;
reg reg_31_r ;
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
reg_00_r <= 'd0;
else if(!modeling_pair_0_i[10:9]&&modeling_pair_0_i[7:0]=={3'd5, 5'd0})
reg_00_r <= 'd1;
else
reg_00_r <= 'd0;
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
reg_10_r <= 'd0;
else if(!modeling_pair_1_i[10:9]&&modeling_pair_1_i[7:0]=={3'd5, 5'd0})
reg_10_r <= 'd1;
else
reg_10_r <= 'd0;
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
reg_20_r <= 'd0;
else if(!modeling_pair_2_i[10:9]&&modeling_pair_2_i[7:0]=={3'd5, 5'd0})
reg_20_r <= 'd1;
else
reg_20_r <= 'd0;
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
reg_30_r <= 'd0;
else if(!modeling_pair_3_i[10:9]&&modeling_pair_3_i[7:0]=={3'd5, 5'd0})
reg_30_r <= 'd1;
else
reg_30_r <= 'd0;
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
reg_01_r <= 'd0;
else if(!modeling_pair_0_i[10:9]&&modeling_pair_0_i[7:0]=={3'd5, 5'd1})
reg_01_r <= 'd1;
else
reg_01_r <= 'd0;
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
reg_11_r <= 'd0;
else if(!modeling_pair_1_i[10:9]&&modeling_pair_1_i[7:0]=={3'd5, 5'd1})
reg_11_r <= 'd1;
else
reg_11_r <= 'd0;
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
reg_21_r <= 'd0;
else if(!modeling_pair_2_i[10:9]&&modeling_pair_2_i[7:0]=={3'd5, 5'd1})
reg_21_r <= 'd1;
else
reg_21_r <= 'd0;
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
reg_31_r <= 'd0;
else if(!modeling_pair_3_i[10:9]&&modeling_pair_3_i[7:0]=={3'd5, 5'd1})
reg_31_r <= 'd1;
else
reg_31_r <= 'd0;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
w_data_delay_0_r <= 0;
w_data_delay_1_r <= 0;
w_data_delay_2_r <= 0;
w_data_delay_3_r <= 0;
w_data_delay_4_r <= 0;
end
else begin
w_data_delay_0_r <= w_data_0_r;
w_data_delay_1_r <= w_data_1_r;
w_data_delay_2_r <= w_data_2_r;
w_data_delay_3_r <= w_data_3_r;
w_data_delay_4_r <= w_data_4_r;
end
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
valid_num_modeling_r <= 'd0;
else
valid_num_modeling_r <= valid_num_modeling_i;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
valid_num_modeling_o <= 0;
else
valid_num_modeling_o <= valid_num_modeling_r;
end
//context state arbitration
always @* begin
case(ctx_pair_delay_0_r[7:5])//ctx_pair_delay_0_r[7:5] : bank number
0: begin ctx_state_0_r = r_data_0_r; end
1: begin ctx_state_0_r = r_data_1_r; end
2: begin ctx_state_0_r = r_data_2_r; end
3: begin ctx_state_0_r = r_data_3_r; end
4: begin ctx_state_0_r = r_data_4_r; end
5: begin
if(reg_00_r)
ctx_state_0_r = ctx_state_50_r;
else
ctx_state_0_r = ctx_state_51_r;
end
default:
begin ctx_state_0_r = r_data_0_r; end
endcase
end
//bin 0
always @* begin
case(ctx_state_0_r) // nextStateLPS
0: begin ctx_state_0_l_r = 1; end
1: begin ctx_state_0_l_r = 0; end
2: begin ctx_state_0_l_r = 0; end
3: begin ctx_state_0_l_r = 1; end
4: begin ctx_state_0_l_r = 2; end
5: begin ctx_state_0_l_r = 3; end
6: begin ctx_state_0_l_r = 4; end
7: begin ctx_state_0_l_r = 5; end
8: begin ctx_state_0_l_r = 4; end
9: begin ctx_state_0_l_r = 5; end
10: begin ctx_state_0_l_r = 8; end
11: begin ctx_state_0_l_r = 9; end
12: begin ctx_state_0_l_r = 8; end
13: begin ctx_state_0_l_r = 9; end
14: begin ctx_state_0_l_r = 10; end
15: begin ctx_state_0_l_r = 11; end
16: begin ctx_state_0_l_r = 12; end
17: begin ctx_state_0_l_r = 13; end
18: begin ctx_state_0_l_r = 14; end
19: begin ctx_state_0_l_r = 15; end
20: begin ctx_state_0_l_r = 16; end
21: begin ctx_state_0_l_r = 17; end
22: begin ctx_state_0_l_r = 18; end
23: begin ctx_state_0_l_r = 19; end
24: begin ctx_state_0_l_r = 18; end
25: begin ctx_state_0_l_r = 19; end
26: begin ctx_state_0_l_r = 22; end
27: begin ctx_state_0_l_r = 23; end
28: begin ctx_state_0_l_r = 22; end
29: begin ctx_state_0_l_r = 23; end
30: begin ctx_state_0_l_r = 24; end
31: begin ctx_state_0_l_r = 25; end
32: begin ctx_state_0_l_r = 26; end
33: begin ctx_state_0_l_r = 27; end
34: begin ctx_state_0_l_r = 26; end
35: begin ctx_state_0_l_r = 27; end
36: begin ctx_state_0_l_r = 30; end
37: begin ctx_state_0_l_r = 31; end
38: begin ctx_state_0_l_r = 30; end
39: begin ctx_state_0_l_r = 31; end
40: begin ctx_state_0_l_r = 32; end
41: begin ctx_state_0_l_r = 33; end
42: begin ctx_state_0_l_r = 32; end
43: begin ctx_state_0_l_r = 33; end
44: begin ctx_state_0_l_r = 36; end
45: begin ctx_state_0_l_r = 37; end
46: begin ctx_state_0_l_r = 36; end
47: begin ctx_state_0_l_r = 37; end
48: begin ctx_state_0_l_r = 38; end
49: begin ctx_state_0_l_r = 39; end
50: begin ctx_state_0_l_r = 38; end
51: begin ctx_state_0_l_r = 39; end
52: begin ctx_state_0_l_r = 42; end
53: begin ctx_state_0_l_r = 43; end
54: begin ctx_state_0_l_r = 42; end
55: begin ctx_state_0_l_r = 43; end
56: begin ctx_state_0_l_r = 44; end
57: begin ctx_state_0_l_r = 45; end
58: begin ctx_state_0_l_r = 44; end
59: begin ctx_state_0_l_r = 45; end
60: begin ctx_state_0_l_r = 46; end
61: begin ctx_state_0_l_r = 47; end
62: begin ctx_state_0_l_r = 48; end
63: begin ctx_state_0_l_r = 49; end
64: begin ctx_state_0_l_r = 48; end
65: begin ctx_state_0_l_r = 49; end
66: begin ctx_state_0_l_r = 50; end
67: begin ctx_state_0_l_r = 51; end
68: begin ctx_state_0_l_r = 52; end
69: begin ctx_state_0_l_r = 53; end
70: begin ctx_state_0_l_r = 52; end
71: begin ctx_state_0_l_r = 53; end
72: begin ctx_state_0_l_r = 54; end
73: begin ctx_state_0_l_r = 55; end
74: begin ctx_state_0_l_r = 54; end
75: begin ctx_state_0_l_r = 55; end
76: begin ctx_state_0_l_r = 56; end
77: begin ctx_state_0_l_r = 57; end
78: begin ctx_state_0_l_r = 58; end
79: begin ctx_state_0_l_r = 59; end
80: begin ctx_state_0_l_r = 58; end
81: begin ctx_state_0_l_r = 59; end
82: begin ctx_state_0_l_r = 60; end
83: begin ctx_state_0_l_r = 61; end
84: begin ctx_state_0_l_r = 60; end
85: begin ctx_state_0_l_r = 61; end
86: begin ctx_state_0_l_r = 60; end
87: begin ctx_state_0_l_r = 61; end
88: begin ctx_state_0_l_r = 62; end
89: begin ctx_state_0_l_r = 63; end
90: begin ctx_state_0_l_r = 64; end
91: begin ctx_state_0_l_r = 65; end
92: begin ctx_state_0_l_r = 64; end
93: begin ctx_state_0_l_r = 65; end
94: begin ctx_state_0_l_r = 66; end
95: begin ctx_state_0_l_r = 67; end
96: begin ctx_state_0_l_r = 66; end
97: begin ctx_state_0_l_r = 67; end
98: begin ctx_state_0_l_r = 66; end
99: begin ctx_state_0_l_r = 67; end
100: begin ctx_state_0_l_r = 68; end
101: begin ctx_state_0_l_r = 69; end
102: begin ctx_state_0_l_r = 68; end
103: begin ctx_state_0_l_r = 69; end
104: begin ctx_state_0_l_r = 70; end
105: begin ctx_state_0_l_r = 71; end
106: begin ctx_state_0_l_r = 70; end
107: begin ctx_state_0_l_r = 71; end
108: begin ctx_state_0_l_r = 70; end
109: begin ctx_state_0_l_r = 71; end
110: begin ctx_state_0_l_r = 72; end
111: begin ctx_state_0_l_r = 73; end
112: begin ctx_state_0_l_r = 72; end
113: begin ctx_state_0_l_r = 73; end
114: begin ctx_state_0_l_r = 72; end
115: begin ctx_state_0_l_r = 73; end
116: begin ctx_state_0_l_r = 74; end
117: begin ctx_state_0_l_r = 75; end
118: begin ctx_state_0_l_r = 74; end
119: begin ctx_state_0_l_r = 75; end
120: begin ctx_state_0_l_r = 74; end
121: begin ctx_state_0_l_r = 75; end
122: begin ctx_state_0_l_r = 76; end
123: begin ctx_state_0_l_r = 77; end
124: begin ctx_state_0_l_r = 76; end
125: begin ctx_state_0_l_r = 77; end
126: begin ctx_state_0_l_r = 126; end
127: begin ctx_state_0_l_r = 127; end
default: begin ctx_state_0_l_r = 0; end
endcase
end
always @* begin //nextStateMPS
if(ctx_state_0_r<=123)
ctx_state_0_m_r = ctx_state_0_r + 2;
else
ctx_state_0_m_r = ctx_state_0_r;
end
always @* begin // nextState
if(bin_delay_0_r==ctx_state_0_r[0])
ctx_state_0_u_r = ctx_state_0_m_r; // bin == MPS
else
ctx_state_0_u_r = ctx_state_0_l_r; // bin == LPS
end
always @* begin
if(comparator01)
ctx_state_1_r = ctx_state_0_u_r; // bin 1 initial state
else begin
case(ctx_pair_delay_1_r[7:5])
0: begin ctx_state_1_r = r_data_0_r; end
1: begin ctx_state_1_r = r_data_1_r; end
2: begin ctx_state_1_r = r_data_2_r; end
3: begin ctx_state_1_r = r_data_3_r; end
4: begin ctx_state_1_r = r_data_4_r; end
5: begin
if(reg_10_r)
ctx_state_1_r = ctx_state_50_r;
else
ctx_state_1_r = ctx_state_51_r;
end
default:
begin ctx_state_1_r = r_data_0_r; end
endcase
end
end
always @* begin
if(comparator12)
ctx_state_2_r = ctx_state_1_u_r;
else if(comparator02)
ctx_state_2_r = ctx_state_0_u_r;
else begin
case(ctx_pair_delay_2_r[7:5])
0: begin ctx_state_2_r = r_data_0_r; end
1: begin ctx_state_2_r = r_data_1_r; end
2: begin ctx_state_2_r = r_data_2_r; end
3: begin ctx_state_2_r = r_data_3_r; end
4: begin ctx_state_2_r = r_data_4_r; end
5: begin
if(reg_20_r)
ctx_state_2_r = ctx_state_50_r;
else
ctx_state_2_r = ctx_state_51_r;
end
default:
begin ctx_state_2_r = r_data_0_r; end
endcase
end
end
always @* begin
if(comparator23)
ctx_state_3_r = ctx_state_2_u_r;
else if(comparator13)
ctx_state_3_r = ctx_state_1_u_r;
else if(comparator03)
ctx_state_3_r = ctx_state_0_u_r;
else begin
case(ctx_pair_delay_3_r[7:5])
0: begin ctx_state_3_r = r_data_0_r; end
1: begin ctx_state_3_r = r_data_1_r; end
2: begin ctx_state_3_r = r_data_2_r; end
3: begin ctx_state_3_r = r_data_3_r; end
4: begin ctx_state_3_r = r_data_4_r; end
5: begin
if(reg_30_r)
ctx_state_3_r = ctx_state_50_r;
else
ctx_state_3_r = ctx_state_51_r;
end
default:
begin ctx_state_3_r = r_data_0_r; end
endcase
end
end
//bin 1
always @* begin
case(ctx_state_1_r)
0: begin ctx_state_1_l_r = 1; end
1: begin ctx_state_1_l_r = 0; end
2: begin ctx_state_1_l_r = 0; end
3: begin ctx_state_1_l_r = 1; end
4: begin ctx_state_1_l_r = 2; end
5: begin ctx_state_1_l_r = 3; end
6: begin ctx_state_1_l_r = 4; end
7: begin ctx_state_1_l_r = 5; end
8: begin ctx_state_1_l_r = 4; end
9: begin ctx_state_1_l_r = 5; end
10: begin ctx_state_1_l_r = 8; end
11: begin ctx_state_1_l_r = 9; end
12: begin ctx_state_1_l_r = 8; end
13: begin ctx_state_1_l_r = 9; end
14: begin ctx_state_1_l_r = 10; end
15: begin ctx_state_1_l_r = 11; end
16: begin ctx_state_1_l_r = 12; end
17: begin ctx_state_1_l_r = 13; end
18: begin ctx_state_1_l_r = 14; end
19: begin ctx_state_1_l_r = 15; end
20: begin ctx_state_1_l_r = 16; end
21: begin ctx_state_1_l_r = 17; end
22: begin ctx_state_1_l_r = 18; end
23: begin ctx_state_1_l_r = 19; end
24: begin ctx_state_1_l_r = 18; end
25: begin ctx_state_1_l_r = 19; end
26: begin ctx_state_1_l_r = 22; end
27: begin ctx_state_1_l_r = 23; end
28: begin ctx_state_1_l_r = 22; end
29: begin ctx_state_1_l_r = 23; end
30: begin ctx_state_1_l_r = 24; end
31: begin ctx_state_1_l_r = 25; end
32: begin ctx_state_1_l_r = 26; end
33: begin ctx_state_1_l_r = 27; end
34: begin ctx_state_1_l_r = 26; end
35: begin ctx_state_1_l_r = 27; end
36: begin ctx_state_1_l_r = 30; end
37: begin ctx_state_1_l_r = 31; end
38: begin ctx_state_1_l_r = 30; end
39: begin ctx_state_1_l_r = 31; end
40: begin ctx_state_1_l_r = 32; end
41: begin ctx_state_1_l_r = 33; end
42: begin ctx_state_1_l_r = 32; end
43: begin ctx_state_1_l_r = 33; end
44: begin ctx_state_1_l_r = 36; end
45: begin ctx_state_1_l_r = 37; end
46: begin ctx_state_1_l_r = 36; end
47: begin ctx_state_1_l_r = 37; end
48: begin ctx_state_1_l_r = 38; end
49: begin ctx_state_1_l_r = 39; end
50: begin ctx_state_1_l_r = 38; end
51: begin ctx_state_1_l_r = 39; end
52: begin ctx_state_1_l_r = 42; end
53: begin ctx_state_1_l_r = 43; end
54: begin ctx_state_1_l_r = 42; end
55: begin ctx_state_1_l_r = 43; end
56: begin ctx_state_1_l_r = 44; end
57: begin ctx_state_1_l_r = 45; end
58: begin ctx_state_1_l_r = 44; end
59: begin ctx_state_1_l_r = 45; end
60: begin ctx_state_1_l_r = 46; end
61: begin ctx_state_1_l_r = 47; end
62: begin ctx_state_1_l_r = 48; end
63: begin ctx_state_1_l_r = 49; end
64: begin ctx_state_1_l_r = 48; end
65: begin ctx_state_1_l_r = 49; end
66: begin ctx_state_1_l_r = 50; end
67: begin ctx_state_1_l_r = 51; end
68: begin ctx_state_1_l_r = 52; end
69: begin ctx_state_1_l_r = 53; end
70: begin ctx_state_1_l_r = 52; end
71: begin ctx_state_1_l_r = 53; end
72: begin ctx_state_1_l_r = 54; end
73: begin ctx_state_1_l_r = 55; end
74: begin ctx_state_1_l_r = 54; end
75: begin ctx_state_1_l_r = 55; end
76: begin ctx_state_1_l_r = 56; end
77: begin ctx_state_1_l_r = 57; end
78: begin ctx_state_1_l_r = 58; end
79: begin ctx_state_1_l_r = 59; end
80: begin ctx_state_1_l_r = 58; end
81: begin ctx_state_1_l_r = 59; end
82: begin ctx_state_1_l_r = 60; end
83: begin ctx_state_1_l_r = 61; end
84: begin ctx_state_1_l_r = 60; end
85: begin ctx_state_1_l_r = 61; end
86: begin ctx_state_1_l_r = 60; end
87: begin ctx_state_1_l_r = 61; end
88: begin ctx_state_1_l_r = 62; end
89: begin ctx_state_1_l_r = 63; end
90: begin ctx_state_1_l_r = 64; end
91: begin ctx_state_1_l_r = 65; end
92: begin ctx_state_1_l_r = 64; end
93: begin ctx_state_1_l_r = 65; end
94: begin ctx_state_1_l_r = 66; end
95: begin ctx_state_1_l_r = 67; end
96: begin ctx_state_1_l_r = 66; end
97: begin ctx_state_1_l_r = 67; end
98: begin ctx_state_1_l_r = 66; end
99: begin ctx_state_1_l_r = 67; end
100: begin ctx_state_1_l_r = 68; end
101: begin ctx_state_1_l_r = 69; end
102: begin ctx_state_1_l_r = 68; end
103: begin ctx_state_1_l_r = 69; end
104: begin ctx_state_1_l_r = 70; end
105: begin ctx_state_1_l_r = 71; end
106: begin ctx_state_1_l_r = 70; end
107: begin ctx_state_1_l_r = 71; end
108: begin ctx_state_1_l_r = 70; end
109: begin ctx_state_1_l_r = 71; end
110: begin ctx_state_1_l_r = 72; end
111: begin ctx_state_1_l_r = 73; end
112: begin ctx_state_1_l_r = 72; end
113: begin ctx_state_1_l_r = 73; end
114: begin ctx_state_1_l_r = 72; end
115: begin ctx_state_1_l_r = 73; end
116: begin ctx_state_1_l_r = 74; end
117: begin ctx_state_1_l_r = 75; end
118: begin ctx_state_1_l_r = 74; end
119: begin ctx_state_1_l_r = 75; end
120: begin ctx_state_1_l_r = 74; end
121: begin ctx_state_1_l_r = 75; end
122: begin ctx_state_1_l_r = 76; end
123: begin ctx_state_1_l_r = 77; end
124: begin ctx_state_1_l_r = 76; end
125: begin ctx_state_1_l_r = 77; end
126: begin ctx_state_1_l_r = 126; end
127: begin ctx_state_1_l_r = 127; end
default: begin ctx_state_1_l_r = 0; end
endcase
end
always @* begin
if(ctx_state_1_r<=123)
ctx_state_1_m_r = ctx_state_1_r + 2;
else
ctx_state_1_m_r = ctx_state_1_r;
end
always @* begin
if(bin_delay_1_r==ctx_state_1_r[0])
ctx_state_1_u_r = ctx_state_1_m_r;
else
ctx_state_1_u_r = ctx_state_1_l_r;
end
//bin 2
always @* begin
case(ctx_state_2_r)
0: begin ctx_state_2_l_r = 1; end
1: begin ctx_state_2_l_r = 0; end
2: begin ctx_state_2_l_r = 0; end
3: begin ctx_state_2_l_r = 1; end
4: begin ctx_state_2_l_r = 2; end
5: begin ctx_state_2_l_r = 3; end
6: begin ctx_state_2_l_r = 4; end
7: begin ctx_state_2_l_r = 5; end
8: begin ctx_state_2_l_r = 4; end
9: begin ctx_state_2_l_r = 5; end
10: begin ctx_state_2_l_r = 8; end
11: begin ctx_state_2_l_r = 9; end
12: begin ctx_state_2_l_r = 8; end
13: begin ctx_state_2_l_r = 9; end
14: begin ctx_state_2_l_r = 10; end
15: begin ctx_state_2_l_r = 11; end
16: begin ctx_state_2_l_r = 12; end
17: begin ctx_state_2_l_r = 13; end
18: begin ctx_state_2_l_r = 14; end
19: begin ctx_state_2_l_r = 15; end
20: begin ctx_state_2_l_r = 16; end
21: begin ctx_state_2_l_r = 17; end
22: begin ctx_state_2_l_r = 18; end
23: begin ctx_state_2_l_r = 19; end
24: begin ctx_state_2_l_r = 18; end
25: begin ctx_state_2_l_r = 19; end
26: begin ctx_state_2_l_r = 22; end
27: begin ctx_state_2_l_r = 23; end
28: begin ctx_state_2_l_r = 22; end
29: begin ctx_state_2_l_r = 23; end
30: begin ctx_state_2_l_r = 24; end
31: begin ctx_state_2_l_r = 25; end
32: begin ctx_state_2_l_r = 26; end
33: begin ctx_state_2_l_r = 27; end
34: begin ctx_state_2_l_r = 26; end
35: begin ctx_state_2_l_r = 27; end
36: begin ctx_state_2_l_r = 30; end
37: begin ctx_state_2_l_r = 31; end
38: begin ctx_state_2_l_r = 30; end
39: begin ctx_state_2_l_r = 31; end
40: begin ctx_state_2_l_r = 32; end
41: begin ctx_state_2_l_r = 33; end
42: begin ctx_state_2_l_r = 32; end
43: begin ctx_state_2_l_r = 33; end
44: begin ctx_state_2_l_r = 36; end
45: begin ctx_state_2_l_r = 37; end
46: begin ctx_state_2_l_r = 36; end
47: begin ctx_state_2_l_r = 37; end
48: begin ctx_state_2_l_r = 38; end
49: begin ctx_state_2_l_r = 39; end
50: begin ctx_state_2_l_r = 38; end
51: begin ctx_state_2_l_r = 39; end
52: begin ctx_state_2_l_r = 42; end
53: begin ctx_state_2_l_r = 43; end
54: begin ctx_state_2_l_r = 42; end
55: begin ctx_state_2_l_r = 43; end
56: begin ctx_state_2_l_r = 44; end
57: begin ctx_state_2_l_r = 45; end
58: begin ctx_state_2_l_r = 44; end
59: begin ctx_state_2_l_r = 45; end
60: begin ctx_state_2_l_r = 46; end
61: begin ctx_state_2_l_r = 47; end
62: begin ctx_state_2_l_r = 48; end
63: begin ctx_state_2_l_r = 49; end
64: begin ctx_state_2_l_r = 48; end
65: begin ctx_state_2_l_r = 49; end
66: begin ctx_state_2_l_r = 50; end
67: begin ctx_state_2_l_r = 51; end
68: begin ctx_state_2_l_r = 52; end
69: begin ctx_state_2_l_r = 53; end
70: begin ctx_state_2_l_r = 52; end
71: begin ctx_state_2_l_r = 53; end
72: begin ctx_state_2_l_r = 54; end
73: begin ctx_state_2_l_r = 55; end
74: begin ctx_state_2_l_r = 54; end
75: begin ctx_state_2_l_r = 55; end
76: begin ctx_state_2_l_r = 56; end
77: begin ctx_state_2_l_r = 57; end
78: begin ctx_state_2_l_r = 58; end
79: begin ctx_state_2_l_r = 59; end
80: begin ctx_state_2_l_r = 58; end
81: begin ctx_state_2_l_r = 59; end
82: begin ctx_state_2_l_r = 60; end
83: begin ctx_state_2_l_r = 61; end
84: begin ctx_state_2_l_r = 60; end
85: begin ctx_state_2_l_r = 61; end
86: begin ctx_state_2_l_r = 60; end
87: begin ctx_state_2_l_r = 61; end
88: begin ctx_state_2_l_r = 62; end
89: begin ctx_state_2_l_r = 63; end
90: begin ctx_state_2_l_r = 64; end
91: begin ctx_state_2_l_r = 65; end
92: begin ctx_state_2_l_r = 64; end
93: begin ctx_state_2_l_r = 65; end
94: begin ctx_state_2_l_r = 66; end
95: begin ctx_state_2_l_r = 67; end
96: begin ctx_state_2_l_r = 66; end
97: begin ctx_state_2_l_r = 67; end
98: begin ctx_state_2_l_r = 66; end
99: begin ctx_state_2_l_r = 67; end
100: begin ctx_state_2_l_r = 68; end
101: begin ctx_state_2_l_r = 69; end
102: begin ctx_state_2_l_r = 68; end
103: begin ctx_state_2_l_r = 69; end
104: begin ctx_state_2_l_r = 70; end
105: begin ctx_state_2_l_r = 71; end
106: begin ctx_state_2_l_r = 70; end
107: begin ctx_state_2_l_r = 71; end
108: begin ctx_state_2_l_r = 70; end
109: begin ctx_state_2_l_r = 71; end
110: begin ctx_state_2_l_r = 72; end
111: begin ctx_state_2_l_r = 73; end
112: begin ctx_state_2_l_r = 72; end
113: begin ctx_state_2_l_r = 73; end
114: begin ctx_state_2_l_r = 72; end
115: begin ctx_state_2_l_r = 73; end
116: begin ctx_state_2_l_r = 74; end
117: begin ctx_state_2_l_r = 75; end
118: begin ctx_state_2_l_r = 74; end
119: begin ctx_state_2_l_r = 75; end
120: begin ctx_state_2_l_r = 74; end
121: begin ctx_state_2_l_r = 75; end
122: begin ctx_state_2_l_r = 76; end
123: begin ctx_state_2_l_r = 77; end
124: begin ctx_state_2_l_r = 76; end
125: begin ctx_state_2_l_r = 77; end
126: begin ctx_state_2_l_r = 126; end
127: begin ctx_state_2_l_r = 127; end
default: begin ctx_state_2_l_r = 0; end
endcase
end
always @* begin
if(ctx_state_2_r<=123)
ctx_state_2_m_r = ctx_state_2_r + 2;
else
ctx_state_2_m_r = ctx_state_2_r;
end
always @* begin
if(bin_delay_2_r==ctx_state_2_r[0])
ctx_state_2_u_r = ctx_state_2_m_r;
else
ctx_state_2_u_r = ctx_state_2_l_r;
end
//bin 3
always @* begin
case(ctx_state_3_r)
0: begin ctx_state_3_l_r = 1; end
1: begin ctx_state_3_l_r = 0; end
2: begin ctx_state_3_l_r = 0; end
3: begin ctx_state_3_l_r = 1; end
4: begin ctx_state_3_l_r = 2; end
5: begin ctx_state_3_l_r = 3; end
6: begin ctx_state_3_l_r = 4; end
7: begin ctx_state_3_l_r = 5; end
8: begin ctx_state_3_l_r = 4; end
9: begin ctx_state_3_l_r = 5; end
10: begin ctx_state_3_l_r = 8; end
11: begin ctx_state_3_l_r = 9; end
12: begin ctx_state_3_l_r = 8; end
13: begin ctx_state_3_l_r = 9; end
14: begin ctx_state_3_l_r = 10; end
15: begin ctx_state_3_l_r = 11; end
16: begin ctx_state_3_l_r = 12; end
17: begin ctx_state_3_l_r = 13; end
18: begin ctx_state_3_l_r = 14; end
19: begin ctx_state_3_l_r = 15; end
20: begin ctx_state_3_l_r = 16; end
21: begin ctx_state_3_l_r = 17; end
22: begin ctx_state_3_l_r = 18; end
23: begin ctx_state_3_l_r = 19; end
24: begin ctx_state_3_l_r = 18; end
25: begin ctx_state_3_l_r = 19; end
26: begin ctx_state_3_l_r = 22; end
27: begin ctx_state_3_l_r = 23; end
28: begin ctx_state_3_l_r = 22; end
29: begin ctx_state_3_l_r = 23; end
30: begin ctx_state_3_l_r = 24; end
31: begin ctx_state_3_l_r = 25; end
32: begin ctx_state_3_l_r = 26; end
33: begin ctx_state_3_l_r = 27; end
34: begin ctx_state_3_l_r = 26; end
35: begin ctx_state_3_l_r = 27; end
36: begin ctx_state_3_l_r = 30; end
37: begin ctx_state_3_l_r = 31; end
38: begin ctx_state_3_l_r = 30; end
39: begin ctx_state_3_l_r = 31; end
40: begin ctx_state_3_l_r = 32; end
41: begin ctx_state_3_l_r = 33; end
42: begin ctx_state_3_l_r = 32; end
43: begin ctx_state_3_l_r = 33; end
44: begin ctx_state_3_l_r = 36; end
45: begin ctx_state_3_l_r = 37; end
46: begin ctx_state_3_l_r = 36; end
47: begin ctx_state_3_l_r = 37; end
48: begin ctx_state_3_l_r = 38; end
49: begin ctx_state_3_l_r = 39; end
50: begin ctx_state_3_l_r = 38; end
51: begin ctx_state_3_l_r = 39; end
52: begin ctx_state_3_l_r = 42; end
53: begin ctx_state_3_l_r = 43; end
54: begin ctx_state_3_l_r = 42; end
55: begin ctx_state_3_l_r = 43; end
56: begin ctx_state_3_l_r = 44; end
57: begin ctx_state_3_l_r = 45; end
58: begin ctx_state_3_l_r = 44; end
59: begin ctx_state_3_l_r = 45; end
60: begin ctx_state_3_l_r = 46; end
61: begin ctx_state_3_l_r = 47; end
62: begin ctx_state_3_l_r = 48; end
63: begin ctx_state_3_l_r = 49; end
64: begin ctx_state_3_l_r = 48; end
65: begin ctx_state_3_l_r = 49; end
66: begin ctx_state_3_l_r = 50; end
67: begin ctx_state_3_l_r = 51; end
68: begin ctx_state_3_l_r = 52; end
69: begin ctx_state_3_l_r = 53; end
70: begin ctx_state_3_l_r = 52; end
71: begin ctx_state_3_l_r = 53; end
72: begin ctx_state_3_l_r = 54; end
73: begin ctx_state_3_l_r = 55; end
74: begin ctx_state_3_l_r = 54; end
75: begin ctx_state_3_l_r = 55; end
76: begin ctx_state_3_l_r = 56; end
77: begin ctx_state_3_l_r = 57; end
78: begin ctx_state_3_l_r = 58; end
79: begin ctx_state_3_l_r = 59; end
80: begin ctx_state_3_l_r = 58; end
81: begin ctx_state_3_l_r = 59; end
82: begin ctx_state_3_l_r = 60; end
83: begin ctx_state_3_l_r = 61; end
84: begin ctx_state_3_l_r = 60; end
85: begin ctx_state_3_l_r = 61; end
86: begin ctx_state_3_l_r = 60; end
87: begin ctx_state_3_l_r = 61; end
88: begin ctx_state_3_l_r = 62; end
89: begin ctx_state_3_l_r = 63; end
90: begin ctx_state_3_l_r = 64; end
91: begin ctx_state_3_l_r = 65; end
92: begin ctx_state_3_l_r = 64; end
93: begin ctx_state_3_l_r = 65; end
94: begin ctx_state_3_l_r = 66; end
95: begin ctx_state_3_l_r = 67; end
96: begin ctx_state_3_l_r = 66; end
97: begin ctx_state_3_l_r = 67; end
98: begin ctx_state_3_l_r = 66; end
99: begin ctx_state_3_l_r = 67; end
100: begin ctx_state_3_l_r = 68; end
101: begin ctx_state_3_l_r = 69; end
102: begin ctx_state_3_l_r = 68; end
103: begin ctx_state_3_l_r = 69; end
104: begin ctx_state_3_l_r = 70; end
105: begin ctx_state_3_l_r = 71; end
106: begin ctx_state_3_l_r = 70; end
107: begin ctx_state_3_l_r = 71; end
108: begin ctx_state_3_l_r = 70; end
109: begin ctx_state_3_l_r = 71; end
110: begin ctx_state_3_l_r = 72; end
111: begin ctx_state_3_l_r = 73; end
112: begin ctx_state_3_l_r = 72; end
113: begin ctx_state_3_l_r = 73; end
114: begin ctx_state_3_l_r = 72; end
115: begin ctx_state_3_l_r = 73; end
116: begin ctx_state_3_l_r = 74; end
117: begin ctx_state_3_l_r = 75; end
118: begin ctx_state_3_l_r = 74; end
119: begin ctx_state_3_l_r = 75; end
120: begin ctx_state_3_l_r = 74; end
121: begin ctx_state_3_l_r = 75; end
122: begin ctx_state_3_l_r = 76; end
123: begin ctx_state_3_l_r = 77; end
124: begin ctx_state_3_l_r = 76; end
125: begin ctx_state_3_l_r = 77; end
126: begin ctx_state_3_l_r = 126; end
127: begin ctx_state_3_l_r = 127; end
default: begin ctx_state_3_l_r = 0; end
endcase
end
always @* begin
if(ctx_state_3_r<=123)
ctx_state_3_m_r = ctx_state_3_r + 2;
else
ctx_state_3_m_r = ctx_state_3_r;
end
always @* begin
if(bin_delay_3_r==ctx_state_3_r[0])
ctx_state_3_u_r = ctx_state_3_m_r;
else
ctx_state_3_u_r = ctx_state_3_l_r;
end
//mps and pstate for modeling_ctx_pair
always @* begin
if(coding_mode_delay_0_r==2'd0) begin
mps_0_r = ctx_state_0_r[0];
pstate_0_r = ctx_state_0_r[6:1];
end
else begin
mps_0_r = 1;
pstate_0_r = 6'h3f;
end
end
always @* begin
if(coding_mode_delay_1_r==2'd0) begin
mps_1_r = ctx_state_1_r[0];
pstate_1_r = ctx_state_1_r[6:1];
end
else begin
mps_1_r = 1;
pstate_1_r = 6'h3f;
end
end
always @* begin
if(coding_mode_delay_2_r==2'd0) begin
mps_2_r = ctx_state_2_r[0];
pstate_2_r = ctx_state_2_r[6:1];
end
else begin
mps_2_r = 1;
pstate_2_r = 6'h3f;
end
end
always @* begin
if(coding_mode_delay_3_r==2'd0) begin
mps_3_r = ctx_state_3_r[0];
pstate_3_r = ctx_state_3_r[6:1];
end
else begin
mps_3_r = 1;
pstate_3_r = 6'h3f;
end
end
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
//
// Sequential Logic
//
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
always @* begin
if(w_addr_delay_1_r==r_addr_1_r)
w_addr_equal_1_r = 1;
else
w_addr_equal_1_r = 0;
end
always @* begin
if(w_addr_delay_2_r==r_addr_2_r)
w_addr_equal_2_r = 1;
else
w_addr_equal_2_r = 0;
end
always @* begin
if(w_addr_delay_3_r==r_addr_3_r)
w_addr_equal_3_r = 1;
else
w_addr_equal_3_r = 0;
end
always @* begin
if(w_addr_delay_4_r==r_addr_4_r)
w_addr_equal_4_r = 1;
else
w_addr_equal_4_r = 0;
end
reg signed [6:0] clip_qp_r ; //clip qp
wire signed [7:0] ctx_50_m_w ;
wire signed [7:0] ctx_50_n_w ;
wire signed [15:0] ctx_50_a_w ;
wire signed [15:0] ctx_50_b_w ;
wire signed [7:0] ctx_state_50_w ;
reg signed [6:0] clip_ctx_state_50_r ;
wire mps_state_50_w ;
reg cabac_start_delay1 ;
reg cabac_start_delay2 ;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
cabac_start_delay1 <= 'd0;
cabac_start_delay2 <= 'd0;
end
else begin
cabac_start_delay1 <= cabac_start_i;
cabac_start_delay2 <= cabac_start_delay1;
end
end
//clip qp
always @* begin
if(slice_qp_i<0)
clip_qp_r = 1;
else if(slice_qp_i>51)
clip_qp_r = 51;
else
clip_qp_r = slice_qp_i;// (`INIT_QP);
end
assign ctx_50_m_w = slice_type_i==(`SLICE_TYPE_I) ? 8'h00 : 8'hf1;
assign ctx_50_n_w = slice_type_i==(`SLICE_TYPE_I) ? 8'h30 : 8'h48;
assign ctx_50_a_w = ctx_50_m_w * clip_qp_r;
assign ctx_50_b_w = ctx_50_a_w >> 4 ;// + ctx_50_n_w;
assign ctx_state_50_w = ctx_50_b_w + ctx_50_n_w;
assign mps_state_50_w = (clip_ctx_state_50_r>='d64) ? 'd1 : 'd0;
always @* begin
if(ctx_state_50_w<0)
clip_ctx_state_50_r = 1;
else if(ctx_state_50_w>126)
clip_ctx_state_50_r = 126;
else
clip_ctx_state_50_r = ctx_state_50_w;
end
//ctx_state_50_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
ctx_state_50_r <= 'd0;
else if(cabac_start_delay2 && first_mb_flag_i)
ctx_state_50_r <= ((mps_state_50_w ? (clip_ctx_state_50_r-'d64) : ('d63-clip_ctx_state_50_r)) << 1) + mps_state_50_w;
else if(reg_00_r && ~comparator01 && ~comparator02 && ~comparator03)
ctx_state_50_r <= ctx_state_0_u_r;
else if(reg_10_r && ~comparator12 && ~comparator13)
ctx_state_50_r <= ctx_state_1_u_r;
else if(reg_20_r && ~comparator23)
ctx_state_50_r <= ctx_state_2_u_r;
else if(reg_30_r)
ctx_state_50_r <= ctx_state_3_u_r;
else
ctx_state_50_r <= ctx_state_50_r;
end
wire signed [7:0] ctx_51_m_w ;
wire signed [7:0] ctx_51_n_w ;
wire signed [15:0] ctx_51_a_w ;
wire signed [15:0] ctx_51_b_w ;
wire signed [7:0] ctx_state_51_w ;
reg signed [6:0] clip_ctx_state_51_r ;
wire mps_state_51_w ;
assign ctx_51_m_w = slice_type_i==(`SLICE_TYPE_I) ? 8'hfb : 8'hf6;
assign ctx_51_n_w = slice_type_i==(`SLICE_TYPE_I) ? 8'h30 : 8'h38;
assign ctx_51_a_w = ctx_51_m_w * clip_qp_r;
assign ctx_51_b_w = ctx_51_a_w >>> 4;
assign ctx_state_51_w = ctx_51_b_w + ctx_51_n_w;
assign mps_state_51_w = (clip_ctx_state_51_r>='d64) ? 'd1 : 'd0;
always @* begin
if(ctx_state_51_w<0)
clip_ctx_state_51_r = 1;
else if(ctx_state_51_w>126)
clip_ctx_state_51_r = 126;
else
clip_ctx_state_51_r = ctx_state_51_w;
end
//ctx_state_51_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
ctx_state_51_r <= 'd0;
else if(cabac_start_delay2 && first_mb_flag_i)
ctx_state_51_r <= ((mps_state_51_w ? (clip_ctx_state_51_r-'d64) : ('d63-clip_ctx_state_51_r)) << 1) + mps_state_51_w;
else if(reg_01_r && ~comparator01 && ~comparator02 && ~comparator03)
ctx_state_51_r <= ctx_state_0_u_r;
else if(reg_11_r && ~comparator12 && ~comparator13)
ctx_state_51_r <= ctx_state_1_u_r;
else if(reg_21_r && ~comparator23)
ctx_state_51_r <= ctx_state_2_u_r;
else if(reg_31_r)
ctx_state_51_r <= ctx_state_3_u_r;
else
ctx_state_51_r <= ctx_state_51_r;
end
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
//sram 0
assign r_en_0_w = r_en_0_r ; // read enable
assign r_addr_0_w = r_addr_0_r ; // read address
assign w_en_0_w = w_en_0_r ; // write enable
assign w_addr_0_w = w_addr_0_r ; // write address
assign w_data_0_w = w_data_0_r ; // write data
reg rw_simultaneous_case_0_r ;
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
rw_simultaneous_case_0_r <= 0;
else if(r_en_0_r==w_en_0_r && r_addr_0_r==w_addr_0_r)
rw_simultaneous_case_0_r <= 1;
else
rw_simultaneous_case_0_r <= 0;
end
always @* begin
r_data_0_r = (w_addr_0_r==w_addr_delay_0_r) ? (w_data_0_r) : (rw_simultaneous_case_0_r ? w_data_delay_0_r : r_data_0_w);
end
//read
always @* begin // read enable : regular mode && sram bank number==0
if(valid_num_modeling_i>=1) begin
if( (modeling_pair_0_i[7:5]==3'd0 && modeling_pair_0_i[10:9]==2'd0) || (modeling_pair_1_i[7:5]==3'd0 && modeling_pair_1_i[10:9]==2'd0)
|| (modeling_pair_2_i[7:5]==3'd0 && modeling_pair_2_i[10:9]==2'd0) || (modeling_pair_3_i[7:5]==3'd0 && modeling_pair_3_i[10:9]==2'd0) )
r_en_0_r = 1;
else
r_en_0_r = 0;
end
else
r_en_0_r = 0;
end
always @* begin // read address : sram bank && regular mode ? address
if(valid_num_modeling_i>=1) begin
if(modeling_pair_0_i[7:5]==3'd0 && modeling_pair_0_i[10:9]==2'b00) begin
r_addr_0_r = modeling_pair_0_i[4:0] ;
end
else if(modeling_pair_1_i[7:5]==3'd0 && modeling_pair_1_i[10:9]==2'b00) begin
r_addr_0_r = modeling_pair_1_i[4:0] ;
end
else if(modeling_pair_2_i[7:5]==3'd0 && modeling_pair_2_i[10:9]==2'b00) begin
r_addr_0_r = modeling_pair_2_i[4:0] ;
end
else if(modeling_pair_3_i[7:5]==3'd0 && modeling_pair_3_i[10:9]==2'b00) begin
r_addr_0_r = modeling_pair_3_i[4:0] ;
end
else begin
r_addr_0_r = 6'd63;
end
end
else begin
r_addr_0_r = 6'd63;
end
end
//write
always @(posedge clk or negedge rst_n) begin // read enable delay 1 cycles
if(!rst_n)
r_en_delay_0_r <= 0;
else
r_en_delay_0_r <= r_en_0_r;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_addr_delay_0_r <= 0;
else
w_addr_delay_0_r <= r_addr_0_r;
end
always @* begin
if(w_addr_delay_0_r==r_addr_0_r) //judge conflict
w_addr_equal_0_r = 1;
else
w_addr_equal_0_r = 0;
end
always @(posedge clk or negedge rst_n) begin // write enable : initial enable ? initial enable : read enable ? not conflict
if(!rst_n)
w_en_0_r <= 0;
else
w_en_0_r <= w_en_ctx_state_0_i || (r_en_delay_0_r && w_addr_equal_0_r==0);
end
always @(posedge clk or negedge rst_n) begin //write address :initial enable ? initial address : read address
if(!rst_n)
w_addr_0_r <= 0;
else
w_addr_0_r <= w_en_ctx_state_0_i ? w_addr_ctx_state_0_i : w_addr_delay_0_r;
end
always @(posedge clk or negedge rst_n) begin //write data
if(!rst_n)
w_data_0_r <= 0;
else if(w_en_ctx_state_0_i) //initial
w_data_0_r <= w_data_ctx_state_0_i;
else if(ctx_pair_delay_0_r[7:5]==3'd0 && ~comparator01 && ~comparator02 && ~comparator03)
w_data_0_r <= ctx_state_0_u_r;
else if(ctx_pair_delay_1_r[7:5]==3'd0 && ~comparator12 && ~comparator13)
w_data_0_r <= ctx_state_1_u_r;
else if(ctx_pair_delay_2_r[7:5]==3'd0 && ~comparator23)
w_data_0_r <= ctx_state_2_u_r;
else if(ctx_pair_delay_3_r[7:5]==3'd0)
w_data_0_r <= ctx_state_3_u_r;
else
w_data_0_r <= w_data_0_r;
end
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
//sram 1
assign r_en_1_w = r_en_1_r ;
assign r_addr_1_w = r_addr_1_r ;
assign w_en_1_w = w_en_1_r ;
assign w_addr_1_w = w_addr_1_r ;
assign w_data_1_w = w_data_1_r ;
reg rw_simultaneous_case_1_r ;
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
rw_simultaneous_case_1_r <= 0;
else if(r_en_1_r==w_en_1_r && r_addr_1_r==w_addr_1_r)
rw_simultaneous_case_1_r <= 1;
else
rw_simultaneous_case_1_r <= 0;
end
always @* begin
r_data_1_r = (w_addr_1_r==w_addr_delay_1_r) ? w_data_1_r : (rw_simultaneous_case_1_r ? w_data_delay_1_r : r_data_1_w);
end
//read
always @* begin
if(valid_num_modeling_i>=1) begin
if( (modeling_pair_0_i[7:5]==3'd1 && modeling_pair_0_i[10:9]==0) || (modeling_pair_1_i[7:5]==3'd1 && modeling_pair_1_i[10:9]==0)
|| (modeling_pair_2_i[7:5]==3'd1 && modeling_pair_2_i[10:9]==0) || (modeling_pair_3_i[7:5]==3'd1 && modeling_pair_3_i[10:9]==0) )
r_en_1_r = 1;
else
r_en_1_r = 0;
end
else
r_en_1_r = 0;
end
always @* begin
if(valid_num_modeling_i>=1) begin
if(modeling_pair_0_i[7:5]==3'd1 && modeling_pair_0_i[10:9]==2'b00) begin
r_addr_1_r = modeling_pair_0_i[4:0];
end
else if(modeling_pair_1_i[7:5]==3'd1 && modeling_pair_1_i[10:9]==2'b00) begin
r_addr_1_r = modeling_pair_1_i[4:0];
end
else if(modeling_pair_2_i[7:5]==3'd1 && modeling_pair_2_i[10:9]==2'b00) begin
r_addr_1_r = modeling_pair_2_i[4:0];
end
else if(modeling_pair_3_i[7:5]==3'd1 && modeling_pair_3_i[10:9]==2'b00) begin
r_addr_1_r = modeling_pair_3_i[4:0];
end
else begin
r_addr_1_r = 6'd63;
end
end
else begin
r_addr_1_r = 6'd63;
end
end
//write
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
r_en_delay_1_r <= 0;
else
r_en_delay_1_r <= r_en_1_r;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_en_1_r <= 0;
else
w_en_1_r <= w_en_ctx_state_1_i || (r_en_delay_1_r && w_addr_equal_1_r==0);
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_addr_delay_1_r <= 0;
else
w_addr_delay_1_r <= r_addr_1_r;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_addr_1_r <= 0;
else
w_addr_1_r <= w_en_ctx_state_1_i ? w_addr_ctx_state_1_i : w_addr_delay_1_r;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_data_1_r <= 0;
else if(w_en_ctx_state_1_i)
w_data_1_r <= w_data_ctx_state_1_i;
else if(ctx_pair_delay_0_r[7:5]==3'd1 && ~comparator01 && ~comparator02 && ~comparator03)
w_data_1_r <= ctx_state_0_u_r;
else if(ctx_pair_delay_1_r[7:5]==3'd1 && ~comparator12 && ~comparator13)
w_data_1_r <= ctx_state_1_u_r;
else if(ctx_pair_delay_2_r[7:5]==3'd1 && ~comparator23)
w_data_1_r <= ctx_state_2_u_r;
else if(ctx_pair_delay_3_r[7:5]==3'd1)
w_data_1_r <= ctx_state_3_u_r;
else
w_data_1_r <= w_data_1_r;
end
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
//sram 2
assign r_en_2_w = r_en_2_r ;
assign r_addr_2_w = r_addr_2_r ;
assign w_en_2_w = w_en_2_r ;
assign w_addr_2_w = w_addr_2_r ;
assign w_data_2_w = w_data_2_r ;
reg r_en_2_delay_r ;
reg w_en_2_delay_r ;
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
r_en_2_delay_r <= 0;
w_en_2_delay_r <= 0;
end
else begin
r_en_2_delay_r <= r_en_2_r;
w_en_2_delay_r <= w_en_2_r;
end
end
reg rw_simultaneous_case_2_r ;
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
rw_simultaneous_case_2_r <= 0;
else if(r_en_2_r==w_en_2_r && r_addr_2_r==w_addr_2_r)
rw_simultaneous_case_2_r <= 1;
else
rw_simultaneous_case_2_r <= 0;
end
always @* begin
r_data_2_r = (w_addr_2_r==w_addr_delay_2_r) ? (w_data_2_r) : (rw_simultaneous_case_2_r ? w_data_delay_2_r : r_data_2_w);
end
//read
always @* begin
if(valid_num_modeling_i>=1) begin
if( (modeling_pair_0_i[7:5]==3'd2 && modeling_pair_0_i[10:9]==0) || (modeling_pair_1_i[7:5]==3'd2 && modeling_pair_1_i[10:9]==0)
|| (modeling_pair_2_i[7:5]==3'd2 && modeling_pair_2_i[10:9]==0) || (modeling_pair_3_i[7:5]==3'd2 && modeling_pair_3_i[10:9]==0) )
r_en_2_r = 1;
else
r_en_2_r = 0;
end
else
r_en_2_r = 0;
end
always @* begin
if(valid_num_modeling_i>=1) begin
if(modeling_pair_0_i[7:5]==3'd2 && modeling_pair_0_i[10:9]==2'b00) begin
r_addr_2_r = modeling_pair_0_i[4:0];
end
else if(modeling_pair_1_i[7:5]==3'd2 && modeling_pair_1_i[10:9]==2'b00) begin
r_addr_2_r = modeling_pair_1_i[4:0];
end
else if(modeling_pair_2_i[7:5]==3'd2 && modeling_pair_2_i[10:9]==2'b00) begin
r_addr_2_r = modeling_pair_2_i[4:0];
end
else if(modeling_pair_3_i[7:5]==3'd2 && modeling_pair_3_i[10:9]==2'b00) begin
r_addr_2_r = modeling_pair_3_i[4:0];
end
else begin
r_addr_2_r = 6'd63;
end
end
else begin
r_addr_2_r = 6'd63;
end
end
//write
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
r_en_delay_2_r <= 0;
else
r_en_delay_2_r <= r_en_2_r;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_en_2_r <= 0;
else
w_en_2_r <= w_en_ctx_state_2_i || (r_en_delay_2_r && w_addr_equal_2_r==0);
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_addr_delay_2_r <= 0;
else
w_addr_delay_2_r <= r_addr_2_r;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_addr_2_r <= 0;
else
w_addr_2_r <= w_en_ctx_state_2_i ? w_addr_ctx_state_2_i : w_addr_delay_2_r;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_data_2_r <= 0;
else if(w_en_ctx_state_2_i)
w_data_2_r <= w_data_ctx_state_2_i;
else if(ctx_pair_delay_0_r[7:5]==3'd2 && ~comparator01 && ~comparator02 && ~comparator03)
w_data_2_r <= ctx_state_0_u_r;
else if(ctx_pair_delay_1_r[7:5]==3'd2 && ~comparator12 && ~comparator13)
w_data_2_r <= ctx_state_1_u_r;
else if(ctx_pair_delay_2_r[7:5]==3'd2 && ~comparator23)
w_data_2_r <= ctx_state_2_u_r;
else if(ctx_pair_delay_3_r[7:5]==3'd2)
w_data_2_r <= ctx_state_3_u_r;
else
w_data_2_r <= w_data_2_r;
end
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
//sram 3
assign r_en_3_w = r_en_3_r ;
assign r_addr_3_w = r_addr_3_r ;
assign w_en_3_w = w_en_3_r ;
assign w_addr_3_w = w_addr_3_r ;
assign w_data_3_w = w_data_3_r ;
reg r_en_3_delay_r ;
reg w_en_3_delay_r ;
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
r_en_3_delay_r <= 0;
w_en_3_delay_r <= 0;
end
else begin
r_en_3_delay_r <= r_en_3_r;
w_en_3_delay_r <= w_en_3_r;
end
end
reg rw_simultaneous_case_3_r ;
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
rw_simultaneous_case_3_r <= 0;
else if(r_en_3_r==w_en_3_r && r_addr_3_r==w_addr_3_r)
rw_simultaneous_case_3_r <= 1;
else
rw_simultaneous_case_3_r <= 0;
end
always @* begin
r_data_3_r = (w_addr_3_r==w_addr_delay_3_r) ? (w_data_3_r) : (rw_simultaneous_case_3_r ? w_data_delay_3_r : r_data_3_w);
end
//read
always @* begin
if(valid_num_modeling_i>=1) begin
if( (modeling_pair_0_i[7:5]==3'd3 && modeling_pair_0_i[10:9]==0) || (modeling_pair_1_i[7:5]==3'd3 && modeling_pair_1_i[10:9]==0)
|| (modeling_pair_2_i[7:5]==3'd3 && modeling_pair_2_i[10:9]==0) || (modeling_pair_3_i[7:5]==3'd3 && modeling_pair_3_i[10:9]==0) )
r_en_3_r = 1;
else
r_en_3_r = 0;
end
else
r_en_3_r = 0;
end
always @* begin
if(valid_num_modeling_i>=1) begin
if(modeling_pair_0_i[7:5]==3'd3 && modeling_pair_0_i[10:9]==2'b00) begin
r_addr_3_r = modeling_pair_0_i[4:0];
end
else if(modeling_pair_1_i[7:5]==3'd3 && modeling_pair_1_i[10:9]==2'b00) begin
r_addr_3_r = modeling_pair_1_i[4:0];
end
else if(modeling_pair_2_i[7:5]==3'd3 && modeling_pair_2_i[10:9]==2'b00) begin
r_addr_3_r = modeling_pair_2_i[4:0];
end
else if(modeling_pair_3_i[7:5]==3'd3 && modeling_pair_3_i[10:9]==2'b00) begin
r_addr_3_r = modeling_pair_3_i[4:0];
end
else begin
r_addr_3_r = 6'd63;
end
end
else begin
r_addr_3_r = 6'd63;
end
end
//write
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
r_en_delay_3_r <= 0;
else
r_en_delay_3_r <= r_en_3_r;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_en_3_r <= 0;
else
w_en_3_r <= w_en_ctx_state_3_i || (r_en_delay_3_r && w_addr_equal_3_r==0);
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_addr_delay_3_r <= 0;
else
w_addr_delay_3_r <= w_en_ctx_state_3_i ? w_addr_ctx_state_3_i : r_addr_3_r;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_addr_3_r <= 0;
else
w_addr_3_r <= w_en_ctx_state_3_i ? w_addr_ctx_state_3_i : w_addr_delay_3_r;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_data_3_r <= 0;
else if(w_en_ctx_state_3_i)
w_data_3_r <= w_data_ctx_state_3_i;
else if(ctx_pair_delay_0_r[7:5]==3'd3 && ~comparator01 && ~comparator02 && ~comparator03)
w_data_3_r <= ctx_state_0_u_r;
else if(ctx_pair_delay_1_r[7:5]==3'd3 && ~comparator12 && ~comparator13)
w_data_3_r <= ctx_state_1_u_r;
else if(ctx_pair_delay_2_r[7:5]==3'd3 && ~comparator23)
w_data_3_r <= ctx_state_2_u_r;
else if(ctx_pair_delay_3_r[7:5]==3'd3)
w_data_3_r <= ctx_state_3_u_r;
else
w_data_3_r <= w_data_3_r;
end
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
//sram 4
assign r_en_4_w = r_en_4_r ;
assign r_addr_4_w = r_addr_4_r ;
assign w_en_4_w = w_en_4_r ;
assign w_addr_4_w = w_addr_4_r ;
assign w_data_4_w = w_data_4_r ;
reg r_en_4_delay_r ;
reg w_en_4_delay_r ;
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
r_en_4_delay_r <= 0;
w_en_4_delay_r <= 0;
end
else begin
r_en_4_delay_r <= r_en_4_r;
w_en_4_delay_r <= w_en_4_r;
end
end
reg rw_simultaneous_case_4_r ;
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
rw_simultaneous_case_4_r <= 0;
else if(r_en_4_r==w_en_4_r && r_addr_4_r==w_addr_4_r)
rw_simultaneous_case_4_r <= 1;
else
rw_simultaneous_case_4_r <= 0;
end
always @* begin
r_data_4_r = (w_addr_4_r==w_addr_delay_4_r) ? (w_data_4_r) : (rw_simultaneous_case_4_r ? w_data_delay_4_r : r_data_4_w);
end
//read
always @* begin
if(valid_num_modeling_i>=1) begin
if( (modeling_pair_0_i[7:5]==3'd4 && modeling_pair_0_i[10:9]==0) || (modeling_pair_1_i[7:5]==3'd4 && modeling_pair_1_i[10:9]==0)
|| (modeling_pair_2_i[7:5]==3'd4 && modeling_pair_2_i[10:9]==0) || (modeling_pair_3_i[7:5]==3'd4 && modeling_pair_3_i[10:9]==0) )
r_en_4_r = 1;
else
r_en_4_r = 0;
end
else
r_en_4_r = 0;
end
always @* begin
if(valid_num_modeling_i>=1) begin
if(modeling_pair_0_i[7:5]==3'd4 && modeling_pair_0_i[10:9]==2'b00) begin
r_addr_4_r = modeling_pair_0_i[4:0];
end
else if(modeling_pair_1_i[7:5]==3'd4 && modeling_pair_1_i[10:9]==2'b00) begin
r_addr_4_r = modeling_pair_1_i[4:0];
end
else if(modeling_pair_2_i[7:5]==3'd4 && modeling_pair_2_i[10:9]==2'b00) begin
r_addr_4_r = modeling_pair_2_i[4:0];
end
else if(modeling_pair_3_i[7:5]==3'd4 && modeling_pair_3_i[10:9]==2'b00) begin
r_addr_4_r = modeling_pair_3_i[4:0];
end
else begin
r_addr_4_r = 6'd63;
end
end
else begin
r_addr_4_r = 6'd63;
end
end
//write
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
r_en_delay_4_r <= 0;
else
r_en_delay_4_r <= r_en_4_r;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_en_4_r <= 0;
else
w_en_4_r <= w_en_ctx_state_4_i || (r_en_delay_4_r && w_addr_equal_4_r==0);
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_addr_delay_4_r <= 0;
else
w_addr_delay_4_r <= w_en_ctx_state_4_i ? w_addr_ctx_state_4_i : r_addr_4_r;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_addr_4_r <= 0;
else
w_addr_4_r <= w_en_ctx_state_4_i ? w_addr_ctx_state_4_i : w_addr_delay_4_r;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_data_4_r <= 0;
else if(w_en_ctx_state_4_i)
w_data_4_r <= w_data_ctx_state_4_i;
else if(ctx_pair_delay_0_r[7:5]==3'd4 && ~comparator01 && ~comparator02 && ~comparator03)
w_data_4_r <= ctx_state_0_u_r;
else if(ctx_pair_delay_1_r[7:5]==3'd4 && ~comparator12 && ~comparator13)
w_data_4_r <= ctx_state_1_u_r;
else if(ctx_pair_delay_2_r[7:5]==3'd4 && ~comparator23)
w_data_4_r <= ctx_state_2_u_r;
else if(ctx_pair_delay_3_r[7:5]==3'd4)
w_data_4_r <= ctx_state_3_u_r;
else
w_data_4_r <= w_data_4_r;
end
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
//
// Sub Modules
//
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
//get ctx_state data from 6-SRAM and update it after using it
cabac_ctx_state_2p_7x64 cabac_ctx_state_2p_7x64_u0(
.clk (clk ),
.r_en (r_en_0_w ),
.r_addr (r_addr_0_w ),
.r_data (r_data_0_w ),
.w_en (w_en_0_w ),
.w_addr (w_addr_0_w ),
.w_data (w_data_0_w )
);
cabac_ctx_state_2p_7x64 cabac_ctx_state_2p_7x64_u1(
.clk (clk ),
.r_en (r_en_1_w ),
.r_addr (r_addr_1_w ),
.r_data (r_data_1_w ),
.w_en (w_en_1_w ),
.w_addr (w_addr_1_w ),
.w_data (w_data_1_w )
);
cabac_ctx_state_2p_7x64 cabac_ctx_state_2p_7x64_u2(
.clk (clk ),
.r_en (r_en_2_w ),
.r_addr (r_addr_2_w ),
.r_data (r_data_2_w ),
.w_en (w_en_2_w ),
.w_addr (w_addr_2_w ),
.w_data (w_data_2_w )
);
cabac_ctx_state_2p_7x64 cabac_ctx_state_2p_7x64_u3(
.clk (clk ),
.r_en (r_en_3_w ),
.r_addr (r_addr_3_w ),
.r_data (r_data_3_w ),
.w_en (w_en_3_w ),
.w_addr (w_addr_3_w ),
.w_data (w_data_3_w )
);
cabac_ctx_state_2p_7x64 cabac_ctx_state_2p_7x64_u4(
.clk (clk ),
.r_en (r_en_4_w ),
.r_addr (r_addr_4_w ),
.r_data (r_data_4_w ),
.w_en (w_en_4_w ),
.w_addr (w_addr_4_w ),
.w_data (w_data_4_w )
);
endmodule
|
module up_adc_common #(
// parameters
parameter ID = 0,
parameter CONFIG = 0,
parameter COMMON_ID = 6'h00,
parameter DRP_DISABLE = 0,
parameter USERPORTS_DISABLE = 0,
parameter GPIO_DISABLE = 0,
parameter START_CODE_DISABLE = 0) (
// clock reset
output mmcm_rst,
// adc interface
input adc_clk,
output adc_rst,
output adc_r1_mode,
output adc_ddr_edgesel,
output adc_pin_mode,
input adc_status,
input adc_sync_status,
input adc_status_ovf,
input [31:0] adc_clk_ratio,
output [31:0] adc_start_code,
output adc_sref_sync,
output adc_sync,
input [31:0] up_pps_rcounter,
input up_pps_status,
output reg up_pps_irq_mask,
// channel interface
output up_adc_ce,
input up_status_pn_err,
input up_status_pn_oos,
input up_status_or,
// drp interface
output up_drp_sel,
output up_drp_wr,
output [11:0] up_drp_addr,
output [31:0] up_drp_wdata,
input [31:0] up_drp_rdata,
input up_drp_ready,
input up_drp_locked,
// user channel control
output [ 7:0] up_usr_chanmax_out,
input [ 7:0] up_usr_chanmax_in,
input [31:0] up_adc_gpio_in,
output [31:0] up_adc_gpio_out,
// bus interface
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// parameters
localparam VERSION = 32'h000a0062;
// internal registers
reg up_adc_clk_enb_int = 'd1;
reg up_core_preset = 'd1;
reg up_mmcm_preset = 'd1;
reg up_wack_int = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_adc_clk_enb = 'd0;
reg up_mmcm_resetn = 'd0;
reg up_resetn = 'd0;
reg up_adc_sync = 'd0;
reg up_adc_sref_sync = 'd0;
reg up_adc_r1_mode = 'd0;
reg up_adc_ddr_edgesel = 'd0;
reg up_adc_pin_mode = 'd0;
reg up_status_ovf = 'd0;
reg [ 7:0] up_usr_chanmax_int = 'd0;
reg [31:0] up_adc_start_code = 'd0;
reg [31:0] up_adc_gpio_out_int = 'd0;
reg [31:0] up_timer = 'd0;
reg up_rack_int = 'd0;
reg [31:0] up_rdata_int = 'd0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire up_status_s;
wire up_sync_status_s;
wire up_status_ovf_s;
wire up_cntrl_xfer_done_s;
wire [31:0] up_adc_clk_count_s;
wire up_drp_status_s;
wire up_drp_rwn_s;
wire [31:0] up_drp_rdata_hold_s;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == COMMON_ID) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == COMMON_ID) ? up_rreq : 1'b0;
// processor write interface
assign up_wack = up_wack_int;
assign up_adc_ce = up_adc_clk_enb_int;
always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_adc_clk_enb_int <= 1'd1;
up_core_preset <= 1'd1;
up_mmcm_preset <= 1'd1;
up_wack_int <= 'd0;
up_scratch <= 'd0;
up_adc_clk_enb <= 'd0;
up_mmcm_resetn <= 'd0;
up_resetn <= 'd0;
up_adc_sync <= 'd0;
up_adc_sref_sync <= 'd0;
up_adc_r1_mode <= 'd0;
up_adc_ddr_edgesel <= 'd0;
up_adc_pin_mode <= 'd0;
up_pps_irq_mask <= 1'b1;
end else begin
up_adc_clk_enb_int <= ~up_adc_clk_enb;
up_core_preset <= ~up_resetn;
up_mmcm_preset <= ~up_mmcm_resetn;
up_wack_int <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h04)) begin
up_pps_irq_mask <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
up_adc_clk_enb <= up_wdata[2];
up_mmcm_resetn <= up_wdata[1];
up_resetn <= up_wdata[0];
end
if (up_adc_sync == 1'b1) begin
if (up_cntrl_xfer_done_s == 1'b1) begin
up_adc_sync <= 1'b0;
end
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_adc_sync <= up_wdata[3];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_adc_sref_sync <= up_wdata[4];
up_adc_r1_mode <= up_wdata[2];
up_adc_ddr_edgesel <= up_wdata[1];
up_adc_pin_mode <= up_wdata[0];
end
end
end
generate
if (DRP_DISABLE == 1) begin
assign up_drp_sel = 'd0;
assign up_drp_wr = 'd0;
assign up_drp_status_s = 'd0;
assign up_drp_rwn_s = 'd0;
assign up_drp_addr = 'd0;
assign up_drp_wdata = 'd0;
assign up_drp_rdata_hold_s = 'd0;
end else begin
reg up_drp_sel_int = 'd0;
reg up_drp_wr_int = 'd0;
reg up_drp_status_int = 'd0;
reg up_drp_rwn_int = 'd0;
reg [11:0] up_drp_addr_int = 'd0;
reg [31:0] up_drp_wdata_int = 'd0;
reg [31:0] up_drp_rdata_hold_int = 'd0;
always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_drp_sel_int <= 'd0;
up_drp_wr_int <= 'd0;
up_drp_status_int <= 'd0;
up_drp_rwn_int <= 'd0;
up_drp_addr_int <= 'd0;
up_drp_wdata_int <= 'd0;
up_drp_rdata_hold_int <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_sel_int <= 1'b1;
up_drp_wr_int <= ~up_wdata[28];
end else begin
up_drp_sel_int <= 1'b0;
up_drp_wr_int <= 1'b0;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_status_int <= 1'b1;
end else if (up_drp_ready == 1'b1) begin
up_drp_status_int <= 1'b0;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_rwn_int <= up_wdata[28];
up_drp_addr_int <= up_wdata[27:16];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1e)) begin
up_drp_wdata_int <= up_wdata;
end
if (up_drp_ready == 1'b1) begin
up_drp_rdata_hold_int <= up_drp_rdata;
end
end
end
assign up_drp_sel = up_drp_sel_int;
assign up_drp_wr = up_drp_wr_int;
assign up_drp_status_s = up_drp_status_int;
assign up_drp_rwn_s = up_drp_rwn_int;
assign up_drp_addr = up_drp_addr_int;
assign up_drp_wdata = up_drp_wdata_int;
assign up_drp_rdata_hold_s = up_drp_rdata_hold_int;
end
endgenerate
always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_status_ovf <= 'd0;
end else begin
if (up_status_ovf_s == 1'b1) begin
up_status_ovf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_status_ovf <= up_status_ovf & ~up_wdata[2];
end
end
end
assign up_usr_chanmax_out = up_usr_chanmax_int;
generate
if (USERPORTS_DISABLE == 1) begin
always @(posedge up_clk) begin
up_usr_chanmax_int <= 'd0;
end
end else begin
always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_usr_chanmax_int <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
up_usr_chanmax_int <= up_wdata[7:0];
end
end
end
end
endgenerate
assign up_adc_gpio_out = up_adc_gpio_out_int;
generate
if (GPIO_DISABLE == 1) begin
always @(posedge up_clk) begin
up_adc_gpio_out_int <= 'd0;
end
end else begin
always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_adc_gpio_out_int <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2f)) begin
up_adc_gpio_out_int <= up_wdata;
end
end
end
end
endgenerate
generate
if (START_CODE_DISABLE == 1) begin
always @(posedge up_clk) begin
up_adc_start_code <= 'd0;
end
end else begin
always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_adc_start_code <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h29)) begin
up_adc_start_code <= up_wdata[31:0];
end
end
end
end
endgenerate
// timer with premature termination
always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_timer <= 32'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h40)) begin
up_timer <= up_wdata;
end else if (up_timer > 0) begin
up_timer <= up_timer - 1'b1;
end
end
end
// processor read interface
assign up_rack = up_rack_int;
assign up_rdata = up_rdata_int;
always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_rack_int <= 'd0;
up_rdata_int <= 'd0;
end else begin
up_rack_int <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
8'h00: up_rdata_int <= VERSION;
8'h01: up_rdata_int <= ID;
8'h02: up_rdata_int <= up_scratch;
8'h03: up_rdata_int <= CONFIG;
8'h04: up_rdata_int <= {31'b0, up_pps_irq_mask};
8'h10: up_rdata_int <= {29'd0, up_adc_clk_enb, up_mmcm_resetn, up_resetn};
8'h11: up_rdata_int <= {27'd0, up_adc_sref_sync, up_adc_sync, up_adc_r1_mode,
up_adc_ddr_edgesel, up_adc_pin_mode};
8'h15: up_rdata_int <= up_adc_clk_count_s;
8'h16: up_rdata_int <= adc_clk_ratio;
8'h17: up_rdata_int <= {28'd0, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s};
8'h1a: up_rdata_int <= {31'd0, up_sync_status_s};
8'h1c: up_rdata_int <= {3'd0, up_drp_rwn_s, up_drp_addr, 16'b0};
8'h1d: up_rdata_int <= {14'd0, up_drp_locked, up_drp_status_s, 16'b0};
8'h1e: up_rdata_int <= up_drp_wdata;
8'h1f: up_rdata_int <= up_drp_rdata_hold_s;
8'h22: up_rdata_int <= {29'd0, up_status_ovf, 2'b0};
8'h23: up_rdata_int <= 32'd8;
8'h28: up_rdata_int <= {24'd0, up_usr_chanmax_in};
8'h29: up_rdata_int <= up_adc_start_code;
8'h2e: up_rdata_int <= up_adc_gpio_in;
8'h2f: up_rdata_int <= up_adc_gpio_out_int;
8'h30: up_rdata_int <= up_pps_rcounter;
8'h31: up_rdata_int <= {31'b0, up_pps_status};
8'h40: up_rdata_int <= up_timer;
default: up_rdata_int <= 0;
endcase
end else begin
up_rdata_int <= 32'd0;
end
end
end
// resets
ad_rst i_mmcm_rst_reg (.rst_async(up_mmcm_preset), .clk(up_clk), .rstn(), .rst(mmcm_rst));
ad_rst i_core_rst_reg (.rst_async(up_core_preset), .clk(adc_clk), .rstn(), .rst(adc_rst));
// adc control & status
up_xfer_cntrl #(.DATA_WIDTH(37)) i_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_adc_sref_sync,
up_adc_sync,
up_adc_start_code,
up_adc_r1_mode,
up_adc_ddr_edgesel,
up_adc_pin_mode}),
.up_xfer_done (up_cntrl_xfer_done_s),
.d_rst (adc_rst),
.d_clk (adc_clk),
.d_data_cntrl ({ adc_sref_sync,
adc_sync,
adc_start_code,
adc_r1_mode,
adc_ddr_edgesel,
adc_pin_mode}));
up_xfer_status #(.DATA_WIDTH(3)) i_xfer_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status ({up_sync_status_s,
up_status_s,
up_status_ovf_s}),
.d_rst (adc_rst),
.d_clk (adc_clk),
.d_data_status ({ adc_sync_status,
adc_status,
adc_status_ovf}));
// adc clock monitor
up_clock_mon i_clock_mon (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_d_count (up_adc_clk_count_s),
.d_rst (adc_rst),
.d_clk (adc_clk));
endmodule
|
module UART_tx(clk,rst_n,bps_start,clk_bps,RS232_tx,tx_data,tx_int);
input clk;
input rst_n;
input clk_bps;//Öмä²ÉÑùµã
input [7:0] tx_data;//½ÓÊÕÊý¾Ý¼Ä´æÆ÷
input tx_int;//Êý¾Ý½ÓÊÕÖжÏÐźÅ
output RS232_tx;//·¢ËÍÊý¾ÝÐźÅ
output bps_start;//·¢ËÍÐźÅÖÃλ
reg tx_int0,tx_int1,tx_int2;//ÐźżĴæÆ÷,²¶×½Ï½µÑØ
wire neg_tx_int; //ϽµÑرêÖ¾
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
tx_int0 <= 1'b0;
tx_int1 <= 1'b0;
tx_int2 <= 1'b0;
end
else begin
tx_int0 <= tx_int;
tx_int1 <= tx_int0;
tx_int2 <= tx_int1;
end
end
assign neg_tx_int = ~tx_int1 & tx_int2;//²¶×½ÏÂÑØ
reg [7:0] tx_data_reg;//´ý·¢ËÍÊý¾Ý
reg bps_start_r;
reg tx_en;//·¢ËÍÐźÅʹÄÜ,¸ßÓÐЧ
reg [3:0] num;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
bps_start_r <= 1'bz;
tx_en <= 1'b0;
tx_data_reg <= 8'd0;
end
else if(neg_tx_int) begin//µ±¼ì²âµ½ÏÂÑصÄʱºò,Êý¾Ý¿ªÊ¼´«ËÍ
bps_start_r <= 1'b1;
tx_data_reg <= tx_data;
tx_en <= 1'b1;
end
else if(num==4'd11) begin
bps_start_r <= 1'b0;
tx_en <= 1'b0;
end
end
assign bps_start = bps_start_r;
reg RS232_tx_r;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
num<=4'd0;
RS232_tx_r <= 1'b1;
end
else if(tx_en) begin
if(clk_bps) begin
num<=num+1'b1;
case(num)
4'd0: RS232_tx_r <= 1'b0;//Æðʼλ
4'd1: RS232_tx_r <= tx_data[0];//Êý¾Ýλ ¿ªÊ¼
4'd2: RS232_tx_r <= tx_data[1];
4'd3: RS232_tx_r <= tx_data[2];
4'd4: RS232_tx_r <= tx_data[3];
4'd5: RS232_tx_r <= tx_data[4];
4'd6: RS232_tx_r <= tx_data[5];
4'd7: RS232_tx_r <= tx_data[6];
4'd8: RS232_tx_r <= tx_data[7];
4'd9: RS232_tx_r <= 1'b1;//Êý¾Ý½áÊøλ,1λ
default: RS232_tx_r <= 1'b1;
endcase
end
else if(num==4'd11)
num<=4'd0;//·¢ËÍÍê³É,¸´Î»
end
end
assign RS232_tx =RS232_tx_r;
endmodule
|
module hpdmc_oddr2 #(
parameter DDR_ALIGNMENT = "C0",
parameter INIT = 1'b0,
parameter SRTYPE = "ASYNC"
) (
output [1:0] Q,
input C0,
input C1,
input CE,
input [1:0] D0,
input [1:0] D1,
input R,
input S
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr0 (
.Q(Q[0]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[0]),
.D1(D1[0]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr1 (
.Q(Q[1]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[1]),
.D1(D1[1]),
.R(R),
.S(S)
);
endmodule
|
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