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module generic_baseblocks_v2_1_0_carry_and #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign COUT = CIN & S;
end else begin : USE_FPGA
MUXCY and_inst
(
.O (COUT),
.CI (CIN),
.DI (1'b0),
.S (S)
);
end
endgenerate
endmodule
|
module generic_baseblocks_v2_1_0_carry_and #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign COUT = CIN & S;
end else begin : USE_FPGA
MUXCY and_inst
(
.O (COUT),
.CI (CIN),
.DI (1'b0),
.S (S)
);
end
endgenerate
endmodule
|
module generic_baseblocks_v2_1_0_carry_and #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign COUT = CIN & S;
end else begin : USE_FPGA
MUXCY and_inst
(
.O (COUT),
.CI (CIN),
.DI (1'b0),
.S (S)
);
end
endgenerate
endmodule
|
module axi_infrastructure_v1_1_0_axic_srl_fifo #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_FAMILY = "virtex7",
parameter integer C_PAYLOAD_WIDTH = 1,
parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire aclk, // Clock
input wire aresetn, // Reset
input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data
input wire s_valid, // Input data valid
output reg s_ready, // Input data ready
output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data
output reg m_valid, // Output data valid
input wire m_ready // Output data ready
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
// ceiling logb2
function integer f_clogb2 (input integer size);
integer s;
begin
s = size;
s = s - 1;
for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
s = s >> 1;
end
endfunction // clogb2
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index;
wire [4-1:0] fifo_addr;
wire push;
wire pop ;
reg areset_r1;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
always @(posedge aclk) begin
areset_r1 <= ~aresetn;
end
always @(posedge aclk) begin
if (~aresetn) begin
fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};
end
else begin
fifo_index <= push & ~pop ? fifo_index + 1'b1 :
~push & pop ? fifo_index - 1'b1 :
fifo_index;
end
end
assign push = s_valid & s_ready;
always @(posedge aclk) begin
if (~aresetn) begin
s_ready <= 1'b0;
end
else begin
s_ready <= areset_r1 ? 1'b1 :
push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :
~push & pop ? 1'b1 :
s_ready;
end
end
assign pop = m_valid & m_ready;
always @(posedge aclk) begin
if (~aresetn) begin
m_valid <= 1'b0;
end
else begin
m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :
push & ~pop ? 1'b1 :
m_valid;
end
end
generate
if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr
assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};
end
else begin : gen_fifo_addr
assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
end
endgenerate
generate
genvar i;
for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit
SRL16E
u_srl_fifo(
.Q ( m_payload[i] ) ,
.A0 ( fifo_addr[0] ) ,
.A1 ( fifo_addr[1] ) ,
.A2 ( fifo_addr[2] ) ,
.A3 ( fifo_addr[3] ) ,
.CE ( push ) ,
.CLK ( aclk ) ,
.D ( s_payload[i] )
);
end
endgenerate
endmodule
|
module reset_and_status
#(
parameter PIO_WIDTH=32
)
(
input clk,
input resetn,
output reg [PIO_WIDTH-1 : 0 ] pio_in,
input [PIO_WIDTH-1 : 0 ] pio_out,
input lock_kernel_pll,
input fixedclk_locked, // pcie fixedclk lock
input mem0_local_cal_success,
input mem0_local_cal_fail,
input mem0_local_init_done,
input mem1_local_cal_success,
input mem1_local_cal_fail,
input mem1_local_init_done,
output reg [1:0] mem_organization,
output [1:0] mem_organization_export,
output pll_reset,
output reg sw_reset_n_out
);
reg [1:0] pio_out_ddr_mode;
reg pio_out_pll_reset;
reg pio_out_sw_reset;
reg [9:0] reset_count;
always@(posedge clk or negedge resetn)
if (!resetn)
reset_count <= 10'b0;
else if (pio_out_sw_reset)
reset_count <= 10'b0;
else if (!reset_count[9])
reset_count <= reset_count + 2'b01;
// false paths set for pio_out_*
(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_out_*]\"" *)
always@(posedge clk)
begin
pio_out_ddr_mode = pio_out[9:8];
pio_out_pll_reset = pio_out[30];
pio_out_sw_reset = pio_out[31];
end
// false paths for pio_in - these are asynchronous
(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_in*]\"" *)
always@(posedge clk)
begin
pio_in = {
lock_kernel_pll,
fixedclk_locked,
1'b0,
1'b0,
mem1_local_cal_fail,
mem0_local_cal_fail,
mem1_local_cal_success,
mem1_local_init_done,
mem0_local_cal_success,
mem0_local_init_done};
end
(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -from [get_registers *mem_organization*]\"" *)
always@(posedge clk)
mem_organization = pio_out_ddr_mode;
assign mem_organization_export = mem_organization;
assign pll_reset = pio_out_pll_reset;
// Export sw kernel reset out of iface to connect to kernel
always@(posedge clk)
sw_reset_n_out = !(!reset_count[9] && (reset_count[8:0] != 0));
endmodule
|
module reset_and_status
#(
parameter PIO_WIDTH=32
)
(
input clk,
input resetn,
output reg [PIO_WIDTH-1 : 0 ] pio_in,
input [PIO_WIDTH-1 : 0 ] pio_out,
input lock_kernel_pll,
input fixedclk_locked, // pcie fixedclk lock
input mem0_local_cal_success,
input mem0_local_cal_fail,
input mem0_local_init_done,
input mem1_local_cal_success,
input mem1_local_cal_fail,
input mem1_local_init_done,
output reg [1:0] mem_organization,
output [1:0] mem_organization_export,
output pll_reset,
output reg sw_reset_n_out
);
reg [1:0] pio_out_ddr_mode;
reg pio_out_pll_reset;
reg pio_out_sw_reset;
reg [9:0] reset_count;
always@(posedge clk or negedge resetn)
if (!resetn)
reset_count <= 10'b0;
else if (pio_out_sw_reset)
reset_count <= 10'b0;
else if (!reset_count[9])
reset_count <= reset_count + 2'b01;
// false paths set for pio_out_*
(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_out_*]\"" *)
always@(posedge clk)
begin
pio_out_ddr_mode = pio_out[9:8];
pio_out_pll_reset = pio_out[30];
pio_out_sw_reset = pio_out[31];
end
// false paths for pio_in - these are asynchronous
(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_in*]\"" *)
always@(posedge clk)
begin
pio_in = {
lock_kernel_pll,
fixedclk_locked,
1'b0,
1'b0,
mem1_local_cal_fail,
mem0_local_cal_fail,
mem1_local_cal_success,
mem1_local_init_done,
mem0_local_cal_success,
mem0_local_init_done};
end
(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -from [get_registers *mem_organization*]\"" *)
always@(posedge clk)
mem_organization = pio_out_ddr_mode;
assign mem_organization_export = mem_organization;
assign pll_reset = pio_out_pll_reset;
// Export sw kernel reset out of iface to connect to kernel
always@(posedge clk)
sw_reset_n_out = !(!reset_count[9] && (reset_count[8:0] != 0));
endmodule
|
module reset_and_status
#(
parameter PIO_WIDTH=32
)
(
input clk,
input resetn,
output reg [PIO_WIDTH-1 : 0 ] pio_in,
input [PIO_WIDTH-1 : 0 ] pio_out,
input lock_kernel_pll,
input fixedclk_locked, // pcie fixedclk lock
input mem0_local_cal_success,
input mem0_local_cal_fail,
input mem0_local_init_done,
input mem1_local_cal_success,
input mem1_local_cal_fail,
input mem1_local_init_done,
output reg [1:0] mem_organization,
output [1:0] mem_organization_export,
output pll_reset,
output reg sw_reset_n_out
);
reg [1:0] pio_out_ddr_mode;
reg pio_out_pll_reset;
reg pio_out_sw_reset;
reg [9:0] reset_count;
always@(posedge clk or negedge resetn)
if (!resetn)
reset_count <= 10'b0;
else if (pio_out_sw_reset)
reset_count <= 10'b0;
else if (!reset_count[9])
reset_count <= reset_count + 2'b01;
// false paths set for pio_out_*
(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_out_*]\"" *)
always@(posedge clk)
begin
pio_out_ddr_mode = pio_out[9:8];
pio_out_pll_reset = pio_out[30];
pio_out_sw_reset = pio_out[31];
end
// false paths for pio_in - these are asynchronous
(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_in*]\"" *)
always@(posedge clk)
begin
pio_in = {
lock_kernel_pll,
fixedclk_locked,
1'b0,
1'b0,
mem1_local_cal_fail,
mem0_local_cal_fail,
mem1_local_cal_success,
mem1_local_init_done,
mem0_local_cal_success,
mem0_local_init_done};
end
(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -from [get_registers *mem_organization*]\"" *)
always@(posedge clk)
mem_organization = pio_out_ddr_mode;
assign mem_organization_export = mem_organization;
assign pll_reset = pio_out_pll_reset;
// Export sw kernel reset out of iface to connect to kernel
always@(posedge clk)
sw_reset_n_out = !(!reset_count[9] && (reset_count[8:0] != 0));
endmodule
|
module generic_baseblocks_v2_1_0_mux #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_SEL_WIDTH = 4,
// Data width for comparator.
parameter integer C_DATA_WIDTH = 2
// Data width for comparator.
)
(
input wire [C_SEL_WIDTH-1:0] S,
input wire [(2**C_SEL_WIDTH)*C_DATA_WIDTH-1:0] A,
output wire [C_DATA_WIDTH-1:0] O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" || C_SEL_WIDTH < 3 ) begin : USE_RTL
assign O = A[(S)*C_DATA_WIDTH +: C_DATA_WIDTH];
end else begin : USE_FPGA
wire [C_DATA_WIDTH-1:0] C;
wire [C_DATA_WIDTH-1:0] D;
// Lower half recursively.
generic_baseblocks_v2_1_0_mux #
(
.C_FAMILY (C_FAMILY),
.C_SEL_WIDTH (C_SEL_WIDTH-1),
.C_DATA_WIDTH (C_DATA_WIDTH)
) mux_c_inst
(
.S (S[C_SEL_WIDTH-2:0]),
.A (A[(2**(C_SEL_WIDTH-1))*C_DATA_WIDTH-1 : 0]),
.O (C)
);
// Upper half recursively.
generic_baseblocks_v2_1_0_mux #
(
.C_FAMILY (C_FAMILY),
.C_SEL_WIDTH (C_SEL_WIDTH-1),
.C_DATA_WIDTH (C_DATA_WIDTH)
) mux_d_inst
(
.S (S[C_SEL_WIDTH-2:0]),
.A (A[(2**C_SEL_WIDTH)*C_DATA_WIDTH-1 : (2**(C_SEL_WIDTH-1))*C_DATA_WIDTH]),
.O (D)
);
// Generate instantiated generic_baseblocks_v2_1_0_mux components as required.
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : NUM
if ( C_SEL_WIDTH == 4 ) begin : USE_F8
MUXF8 muxf8_inst
(
.I0 (C[bit_cnt]),
.I1 (D[bit_cnt]),
.S (S[C_SEL_WIDTH-1]),
.O (O[bit_cnt])
);
end else if ( C_SEL_WIDTH == 3 ) begin : USE_F7
MUXF7 muxf7_inst
(
.I0 (C[bit_cnt]),
.I1 (D[bit_cnt]),
.S (S[C_SEL_WIDTH-1]),
.O (O[bit_cnt])
);
end // C_SEL_WIDTH
end // end for bit_cnt
end
endgenerate
endmodule
|
module read_signal_breakout (
read_command_data_in, // descriptor from the read FIFO
read_command_data_out, // reformated descriptor to the read master
// breakout of command information
read_address,
read_length,
read_transmit_channel,
read_generate_sop,
read_generate_eop,
read_park,
read_transfer_complete_IRQ_mask,
read_burst_count, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
read_stride, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
read_sequence_number, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
read_transmit_error,
read_early_done_enable,
// additional control information that needs to go out asynchronously with the command data
read_stop,
read_sw_reset
);
parameter DATA_WIDTH = 256; // 256 bits when enhanced settings are enabled otherwise 128 bits
input [DATA_WIDTH-1:0] read_command_data_in;
output wire [255:0] read_command_data_out;
output wire [63:0] read_address;
output wire [31:0] read_length;
output wire [7:0] read_transmit_channel;
output wire read_generate_sop;
output wire read_generate_eop;
output wire read_park;
output wire read_transfer_complete_IRQ_mask;
output wire [7:0] read_burst_count;
output wire [15:0] read_stride;
output wire [15:0] read_sequence_number;
output wire [7:0] read_transmit_error;
output wire read_early_done_enable;
input read_stop;
input read_sw_reset;
assign read_address[31:0] = read_command_data_in[31:0];
assign read_length = read_command_data_in[95:64];
generate
if (DATA_WIDTH == 256)
begin
assign read_early_done_enable = read_command_data_in[248];
assign read_transmit_error = read_command_data_in[247:240];
assign read_transmit_channel = read_command_data_in[231:224];
assign read_generate_sop = read_command_data_in[232];
assign read_generate_eop = read_command_data_in[233];
assign read_park = read_command_data_in[234];
assign read_transfer_complete_IRQ_mask = read_command_data_in[238];
assign read_burst_count = read_command_data_in[119:112];
assign read_stride = read_command_data_in[143:128];
assign read_sequence_number = read_command_data_in[111:96];
assign read_address[63:32] = read_command_data_in[191:160];
end
else
begin
assign read_early_done_enable = read_command_data_in[120];
assign read_transmit_error = read_command_data_in[119:112];
assign read_transmit_channel = read_command_data_in[103:96];
assign read_generate_sop = read_command_data_in[104];
assign read_generate_eop = read_command_data_in[105];
assign read_park = read_command_data_in[106];
assign read_transfer_complete_IRQ_mask = read_command_data_in[110];
assign read_burst_count = 8'h00;
assign read_stride = 16'h0000;
assign read_sequence_number = 16'h0000;
assign read_address[63:32] = 32'h00000000;
end
endgenerate
// big concat statement to glue all the signals back together to go out to the read master (MSBs to LSBs)
assign read_command_data_out = {{115{1'b0}}, // zero pad the upper 115 bits
read_address[63:32],
read_early_done_enable,
read_transmit_error,
read_stride,
read_burst_count,
read_sw_reset,
read_stop,
read_generate_eop,
read_generate_sop,
read_transmit_channel,
read_length,
read_address[31:0]};
endmodule
|
module read_signal_breakout (
read_command_data_in, // descriptor from the read FIFO
read_command_data_out, // reformated descriptor to the read master
// breakout of command information
read_address,
read_length,
read_transmit_channel,
read_generate_sop,
read_generate_eop,
read_park,
read_transfer_complete_IRQ_mask,
read_burst_count, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
read_stride, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
read_sequence_number, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
read_transmit_error,
read_early_done_enable,
// additional control information that needs to go out asynchronously with the command data
read_stop,
read_sw_reset
);
parameter DATA_WIDTH = 256; // 256 bits when enhanced settings are enabled otherwise 128 bits
input [DATA_WIDTH-1:0] read_command_data_in;
output wire [255:0] read_command_data_out;
output wire [63:0] read_address;
output wire [31:0] read_length;
output wire [7:0] read_transmit_channel;
output wire read_generate_sop;
output wire read_generate_eop;
output wire read_park;
output wire read_transfer_complete_IRQ_mask;
output wire [7:0] read_burst_count;
output wire [15:0] read_stride;
output wire [15:0] read_sequence_number;
output wire [7:0] read_transmit_error;
output wire read_early_done_enable;
input read_stop;
input read_sw_reset;
assign read_address[31:0] = read_command_data_in[31:0];
assign read_length = read_command_data_in[95:64];
generate
if (DATA_WIDTH == 256)
begin
assign read_early_done_enable = read_command_data_in[248];
assign read_transmit_error = read_command_data_in[247:240];
assign read_transmit_channel = read_command_data_in[231:224];
assign read_generate_sop = read_command_data_in[232];
assign read_generate_eop = read_command_data_in[233];
assign read_park = read_command_data_in[234];
assign read_transfer_complete_IRQ_mask = read_command_data_in[238];
assign read_burst_count = read_command_data_in[119:112];
assign read_stride = read_command_data_in[143:128];
assign read_sequence_number = read_command_data_in[111:96];
assign read_address[63:32] = read_command_data_in[191:160];
end
else
begin
assign read_early_done_enable = read_command_data_in[120];
assign read_transmit_error = read_command_data_in[119:112];
assign read_transmit_channel = read_command_data_in[103:96];
assign read_generate_sop = read_command_data_in[104];
assign read_generate_eop = read_command_data_in[105];
assign read_park = read_command_data_in[106];
assign read_transfer_complete_IRQ_mask = read_command_data_in[110];
assign read_burst_count = 8'h00;
assign read_stride = 16'h0000;
assign read_sequence_number = 16'h0000;
assign read_address[63:32] = 32'h00000000;
end
endgenerate
// big concat statement to glue all the signals back together to go out to the read master (MSBs to LSBs)
assign read_command_data_out = {{115{1'b0}}, // zero pad the upper 115 bits
read_address[63:32],
read_early_done_enable,
read_transmit_error,
read_stride,
read_burst_count,
read_sw_reset,
read_stop,
read_generate_eop,
read_generate_sop,
read_transmit_channel,
read_length,
read_address[31:0]};
endmodule
|
module read_signal_breakout (
read_command_data_in, // descriptor from the read FIFO
read_command_data_out, // reformated descriptor to the read master
// breakout of command information
read_address,
read_length,
read_transmit_channel,
read_generate_sop,
read_generate_eop,
read_park,
read_transfer_complete_IRQ_mask,
read_burst_count, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
read_stride, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
read_sequence_number, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
read_transmit_error,
read_early_done_enable,
// additional control information that needs to go out asynchronously with the command data
read_stop,
read_sw_reset
);
parameter DATA_WIDTH = 256; // 256 bits when enhanced settings are enabled otherwise 128 bits
input [DATA_WIDTH-1:0] read_command_data_in;
output wire [255:0] read_command_data_out;
output wire [63:0] read_address;
output wire [31:0] read_length;
output wire [7:0] read_transmit_channel;
output wire read_generate_sop;
output wire read_generate_eop;
output wire read_park;
output wire read_transfer_complete_IRQ_mask;
output wire [7:0] read_burst_count;
output wire [15:0] read_stride;
output wire [15:0] read_sequence_number;
output wire [7:0] read_transmit_error;
output wire read_early_done_enable;
input read_stop;
input read_sw_reset;
assign read_address[31:0] = read_command_data_in[31:0];
assign read_length = read_command_data_in[95:64];
generate
if (DATA_WIDTH == 256)
begin
assign read_early_done_enable = read_command_data_in[248];
assign read_transmit_error = read_command_data_in[247:240];
assign read_transmit_channel = read_command_data_in[231:224];
assign read_generate_sop = read_command_data_in[232];
assign read_generate_eop = read_command_data_in[233];
assign read_park = read_command_data_in[234];
assign read_transfer_complete_IRQ_mask = read_command_data_in[238];
assign read_burst_count = read_command_data_in[119:112];
assign read_stride = read_command_data_in[143:128];
assign read_sequence_number = read_command_data_in[111:96];
assign read_address[63:32] = read_command_data_in[191:160];
end
else
begin
assign read_early_done_enable = read_command_data_in[120];
assign read_transmit_error = read_command_data_in[119:112];
assign read_transmit_channel = read_command_data_in[103:96];
assign read_generate_sop = read_command_data_in[104];
assign read_generate_eop = read_command_data_in[105];
assign read_park = read_command_data_in[106];
assign read_transfer_complete_IRQ_mask = read_command_data_in[110];
assign read_burst_count = 8'h00;
assign read_stride = 16'h0000;
assign read_sequence_number = 16'h0000;
assign read_address[63:32] = 32'h00000000;
end
endgenerate
// big concat statement to glue all the signals back together to go out to the read master (MSBs to LSBs)
assign read_command_data_out = {{115{1'b0}}, // zero pad the upper 115 bits
read_address[63:32],
read_early_done_enable,
read_transmit_error,
read_stride,
read_burst_count,
read_sw_reset,
read_stop,
read_generate_eop,
read_generate_sop,
read_transmit_channel,
read_length,
read_address[31:0]};
endmodule
|
module read_signal_breakout (
read_command_data_in, // descriptor from the read FIFO
read_command_data_out, // reformated descriptor to the read master
// breakout of command information
read_address,
read_length,
read_transmit_channel,
read_generate_sop,
read_generate_eop,
read_park,
read_transfer_complete_IRQ_mask,
read_burst_count, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
read_stride, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
read_sequence_number, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
read_transmit_error,
read_early_done_enable,
// additional control information that needs to go out asynchronously with the command data
read_stop,
read_sw_reset
);
parameter DATA_WIDTH = 256; // 256 bits when enhanced settings are enabled otherwise 128 bits
input [DATA_WIDTH-1:0] read_command_data_in;
output wire [255:0] read_command_data_out;
output wire [63:0] read_address;
output wire [31:0] read_length;
output wire [7:0] read_transmit_channel;
output wire read_generate_sop;
output wire read_generate_eop;
output wire read_park;
output wire read_transfer_complete_IRQ_mask;
output wire [7:0] read_burst_count;
output wire [15:0] read_stride;
output wire [15:0] read_sequence_number;
output wire [7:0] read_transmit_error;
output wire read_early_done_enable;
input read_stop;
input read_sw_reset;
assign read_address[31:0] = read_command_data_in[31:0];
assign read_length = read_command_data_in[95:64];
generate
if (DATA_WIDTH == 256)
begin
assign read_early_done_enable = read_command_data_in[248];
assign read_transmit_error = read_command_data_in[247:240];
assign read_transmit_channel = read_command_data_in[231:224];
assign read_generate_sop = read_command_data_in[232];
assign read_generate_eop = read_command_data_in[233];
assign read_park = read_command_data_in[234];
assign read_transfer_complete_IRQ_mask = read_command_data_in[238];
assign read_burst_count = read_command_data_in[119:112];
assign read_stride = read_command_data_in[143:128];
assign read_sequence_number = read_command_data_in[111:96];
assign read_address[63:32] = read_command_data_in[191:160];
end
else
begin
assign read_early_done_enable = read_command_data_in[120];
assign read_transmit_error = read_command_data_in[119:112];
assign read_transmit_channel = read_command_data_in[103:96];
assign read_generate_sop = read_command_data_in[104];
assign read_generate_eop = read_command_data_in[105];
assign read_park = read_command_data_in[106];
assign read_transfer_complete_IRQ_mask = read_command_data_in[110];
assign read_burst_count = 8'h00;
assign read_stride = 16'h0000;
assign read_sequence_number = 16'h0000;
assign read_address[63:32] = 32'h00000000;
end
endgenerate
// big concat statement to glue all the signals back together to go out to the read master (MSBs to LSBs)
assign read_command_data_out = {{115{1'b0}}, // zero pad the upper 115 bits
read_address[63:32],
read_early_done_enable,
read_transmit_error,
read_stride,
read_burst_count,
read_sw_reset,
read_stop,
read_generate_eop,
read_generate_sop,
read_transmit_channel,
read_length,
read_address[31:0]};
endmodule
|
module response_block (
clk,
reset,
mm_response_readdata,
mm_response_read,
mm_response_address,
mm_response_byteenable,
mm_response_waitrequest,
src_response_data,
src_response_valid,
src_response_ready,
sw_reset,
response_watermark,
response_fifo_full,
response_fifo_empty,
done_strobe,
actual_bytes_transferred,
error,
early_termination,
transfer_complete_IRQ_mask,
error_IRQ_mask,
early_termination_IRQ_mask,
descriptor_buffer_full
);
parameter RESPONSE_PORT = 0; // when disabled all the outputs will be disconnected by the component wrapper
parameter FIFO_DEPTH = 256; // needs to be double the descriptor FIFO depth
parameter FIFO_DEPTH_LOG2 = 8;
localparam FIFO_WIDTH = (RESPONSE_PORT == 0)? 41 : 51; // when 'RESPONSE_PORT' is 1 then the response port is set to streaming and must pass the interrupt masks as well
input clk;
input reset;
output wire [31:0] mm_response_readdata;
input mm_response_read;
input mm_response_address; // only have 2 addresses
input [3:0] mm_response_byteenable;
output wire mm_response_waitrequest;
output wire [255:0] src_response_data; // not going to use all these bits, the remainder will be grounded
output wire src_response_valid;
input src_response_ready;
input sw_reset;
output wire [15:0] response_watermark;
output wire response_fifo_full;
output wire response_fifo_empty;
input done_strobe;
input [31:0] actual_bytes_transferred;
input [7:0] error;
input early_termination;
// all of these signals are only used the ST source response port since the pre-fetching master component will handle the interrupt generation as apposed to the CSR block
input transfer_complete_IRQ_mask;
input [7:0] error_IRQ_mask;
input early_termination_IRQ_mask;
input descriptor_buffer_full; // handy signal for the prefetching master to use so that it known when to blast a new descriptor into the dispatcher
/* internal signals and registers */
wire [FIFO_DEPTH_LOG2-1:0] fifo_used;
wire fifo_full;
wire fifo_empty;
wire fifo_read;
wire [FIFO_WIDTH-1:0] fifo_input;
wire [FIFO_WIDTH-1:0] fifo_output;
generate
if (RESPONSE_PORT == 0) // slave port used for response data
begin
assign fifo_input = {early_termination, error, actual_bytes_transferred};
assign fifo_read = (mm_response_read == 1) & (fifo_empty == 0) & (mm_response_address == 1) & (mm_response_byteenable[3] == 1); // reading from the upper byte (byte offset 7) pops the fifo
scfifo the_response_FIFO (
.clock (clk),
.aclr (reset),
.sclr (sw_reset),
.data (fifo_input),
.wrreq (done_strobe),
.rdreq (fifo_read),
.q (fifo_output),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used)
);
defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_response_FIFO.lpm_showahead = "ON";
defparam the_response_FIFO.use_eab = "ON";
defparam the_response_FIFO.overflow_checking = "OFF";
defparam the_response_FIFO.underflow_checking = "OFF";
defparam the_response_FIFO.add_ram_output_register = "ON";
defparam the_response_FIFO.lpm_type = "scfifo";
// either actual bytes transfered when address == 0 or {zero padding, early_termination, error[7:0]} when address = 1
assign mm_response_readdata = (mm_response_address == 0)? fifo_output[31:0] : {{23{1'b0}}, fifo_output[40:32]};
assign mm_response_waitrequest = fifo_empty;
assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount
assign response_fifo_full = fifo_full;
assign response_fifo_empty = fifo_empty;
// no streaming port so ground all of its outputs
assign src_response_data = 0;
assign src_response_valid = 0;
end
else if (RESPONSE_PORT == 1) // streaming source port used for response data (prefetcher will catch this data)
begin
assign fifo_input = {early_termination_IRQ_mask, error_IRQ_mask, transfer_complete_IRQ_mask, early_termination, error, actual_bytes_transferred};
assign fifo_read = (fifo_empty == 0) & (src_response_ready == 1);
scfifo the_response_FIFO (
.clock (clk),
.aclr (reset | sw_reset),
.data (fifo_input),
.wrreq (done_strobe),
.rdreq (fifo_read),
.q (fifo_output),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used)
);
defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_response_FIFO.lpm_showahead = "ON";
defparam the_response_FIFO.use_eab = "ON";
defparam the_response_FIFO.overflow_checking = "OFF";
defparam the_response_FIFO.underflow_checking = "OFF";
defparam the_response_FIFO.add_ram_output_register = "ON";
defparam the_response_FIFO.lpm_type = "scfifo";
assign src_response_data = {{204{1'b0}}, descriptor_buffer_full, fifo_output}; // zero padding the upper bits, also sending out the descriptor buffer full signal to simplify the throttling in the prefetching master (bit 52)
assign src_response_valid = (fifo_empty == 0);
assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount;
assign response_fifo_full = fifo_full;
assign response_fifo_empty = fifo_empty;
// no slave port so ground all of its outputs
assign mm_response_readdata = 0;
assign mm_response_waitrequest = 0;
end
else // no response port so grounding all outputs
begin
assign fifo_input = 0;
assign fifo_output = 0;
assign mm_response_readdata = 0;
assign mm_response_waitrequest = 0;
assign src_response_data = 0;
assign src_response_valid = 0;
assign response_watermark = 0;
assign response_fifo_full = 0;
assign response_fifo_empty = 0;
end
endgenerate
endmodule
|
module response_block (
clk,
reset,
mm_response_readdata,
mm_response_read,
mm_response_address,
mm_response_byteenable,
mm_response_waitrequest,
src_response_data,
src_response_valid,
src_response_ready,
sw_reset,
response_watermark,
response_fifo_full,
response_fifo_empty,
done_strobe,
actual_bytes_transferred,
error,
early_termination,
transfer_complete_IRQ_mask,
error_IRQ_mask,
early_termination_IRQ_mask,
descriptor_buffer_full
);
parameter RESPONSE_PORT = 0; // when disabled all the outputs will be disconnected by the component wrapper
parameter FIFO_DEPTH = 256; // needs to be double the descriptor FIFO depth
parameter FIFO_DEPTH_LOG2 = 8;
localparam FIFO_WIDTH = (RESPONSE_PORT == 0)? 41 : 51; // when 'RESPONSE_PORT' is 1 then the response port is set to streaming and must pass the interrupt masks as well
input clk;
input reset;
output wire [31:0] mm_response_readdata;
input mm_response_read;
input mm_response_address; // only have 2 addresses
input [3:0] mm_response_byteenable;
output wire mm_response_waitrequest;
output wire [255:0] src_response_data; // not going to use all these bits, the remainder will be grounded
output wire src_response_valid;
input src_response_ready;
input sw_reset;
output wire [15:0] response_watermark;
output wire response_fifo_full;
output wire response_fifo_empty;
input done_strobe;
input [31:0] actual_bytes_transferred;
input [7:0] error;
input early_termination;
// all of these signals are only used the ST source response port since the pre-fetching master component will handle the interrupt generation as apposed to the CSR block
input transfer_complete_IRQ_mask;
input [7:0] error_IRQ_mask;
input early_termination_IRQ_mask;
input descriptor_buffer_full; // handy signal for the prefetching master to use so that it known when to blast a new descriptor into the dispatcher
/* internal signals and registers */
wire [FIFO_DEPTH_LOG2-1:0] fifo_used;
wire fifo_full;
wire fifo_empty;
wire fifo_read;
wire [FIFO_WIDTH-1:0] fifo_input;
wire [FIFO_WIDTH-1:0] fifo_output;
generate
if (RESPONSE_PORT == 0) // slave port used for response data
begin
assign fifo_input = {early_termination, error, actual_bytes_transferred};
assign fifo_read = (mm_response_read == 1) & (fifo_empty == 0) & (mm_response_address == 1) & (mm_response_byteenable[3] == 1); // reading from the upper byte (byte offset 7) pops the fifo
scfifo the_response_FIFO (
.clock (clk),
.aclr (reset),
.sclr (sw_reset),
.data (fifo_input),
.wrreq (done_strobe),
.rdreq (fifo_read),
.q (fifo_output),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used)
);
defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_response_FIFO.lpm_showahead = "ON";
defparam the_response_FIFO.use_eab = "ON";
defparam the_response_FIFO.overflow_checking = "OFF";
defparam the_response_FIFO.underflow_checking = "OFF";
defparam the_response_FIFO.add_ram_output_register = "ON";
defparam the_response_FIFO.lpm_type = "scfifo";
// either actual bytes transfered when address == 0 or {zero padding, early_termination, error[7:0]} when address = 1
assign mm_response_readdata = (mm_response_address == 0)? fifo_output[31:0] : {{23{1'b0}}, fifo_output[40:32]};
assign mm_response_waitrequest = fifo_empty;
assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount
assign response_fifo_full = fifo_full;
assign response_fifo_empty = fifo_empty;
// no streaming port so ground all of its outputs
assign src_response_data = 0;
assign src_response_valid = 0;
end
else if (RESPONSE_PORT == 1) // streaming source port used for response data (prefetcher will catch this data)
begin
assign fifo_input = {early_termination_IRQ_mask, error_IRQ_mask, transfer_complete_IRQ_mask, early_termination, error, actual_bytes_transferred};
assign fifo_read = (fifo_empty == 0) & (src_response_ready == 1);
scfifo the_response_FIFO (
.clock (clk),
.aclr (reset | sw_reset),
.data (fifo_input),
.wrreq (done_strobe),
.rdreq (fifo_read),
.q (fifo_output),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used)
);
defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_response_FIFO.lpm_showahead = "ON";
defparam the_response_FIFO.use_eab = "ON";
defparam the_response_FIFO.overflow_checking = "OFF";
defparam the_response_FIFO.underflow_checking = "OFF";
defparam the_response_FIFO.add_ram_output_register = "ON";
defparam the_response_FIFO.lpm_type = "scfifo";
assign src_response_data = {{204{1'b0}}, descriptor_buffer_full, fifo_output}; // zero padding the upper bits, also sending out the descriptor buffer full signal to simplify the throttling in the prefetching master (bit 52)
assign src_response_valid = (fifo_empty == 0);
assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount;
assign response_fifo_full = fifo_full;
assign response_fifo_empty = fifo_empty;
// no slave port so ground all of its outputs
assign mm_response_readdata = 0;
assign mm_response_waitrequest = 0;
end
else // no response port so grounding all outputs
begin
assign fifo_input = 0;
assign fifo_output = 0;
assign mm_response_readdata = 0;
assign mm_response_waitrequest = 0;
assign src_response_data = 0;
assign src_response_valid = 0;
assign response_watermark = 0;
assign response_fifo_full = 0;
assign response_fifo_empty = 0;
end
endgenerate
endmodule
|
module response_block (
clk,
reset,
mm_response_readdata,
mm_response_read,
mm_response_address,
mm_response_byteenable,
mm_response_waitrequest,
src_response_data,
src_response_valid,
src_response_ready,
sw_reset,
response_watermark,
response_fifo_full,
response_fifo_empty,
done_strobe,
actual_bytes_transferred,
error,
early_termination,
transfer_complete_IRQ_mask,
error_IRQ_mask,
early_termination_IRQ_mask,
descriptor_buffer_full
);
parameter RESPONSE_PORT = 0; // when disabled all the outputs will be disconnected by the component wrapper
parameter FIFO_DEPTH = 256; // needs to be double the descriptor FIFO depth
parameter FIFO_DEPTH_LOG2 = 8;
localparam FIFO_WIDTH = (RESPONSE_PORT == 0)? 41 : 51; // when 'RESPONSE_PORT' is 1 then the response port is set to streaming and must pass the interrupt masks as well
input clk;
input reset;
output wire [31:0] mm_response_readdata;
input mm_response_read;
input mm_response_address; // only have 2 addresses
input [3:0] mm_response_byteenable;
output wire mm_response_waitrequest;
output wire [255:0] src_response_data; // not going to use all these bits, the remainder will be grounded
output wire src_response_valid;
input src_response_ready;
input sw_reset;
output wire [15:0] response_watermark;
output wire response_fifo_full;
output wire response_fifo_empty;
input done_strobe;
input [31:0] actual_bytes_transferred;
input [7:0] error;
input early_termination;
// all of these signals are only used the ST source response port since the pre-fetching master component will handle the interrupt generation as apposed to the CSR block
input transfer_complete_IRQ_mask;
input [7:0] error_IRQ_mask;
input early_termination_IRQ_mask;
input descriptor_buffer_full; // handy signal for the prefetching master to use so that it known when to blast a new descriptor into the dispatcher
/* internal signals and registers */
wire [FIFO_DEPTH_LOG2-1:0] fifo_used;
wire fifo_full;
wire fifo_empty;
wire fifo_read;
wire [FIFO_WIDTH-1:0] fifo_input;
wire [FIFO_WIDTH-1:0] fifo_output;
generate
if (RESPONSE_PORT == 0) // slave port used for response data
begin
assign fifo_input = {early_termination, error, actual_bytes_transferred};
assign fifo_read = (mm_response_read == 1) & (fifo_empty == 0) & (mm_response_address == 1) & (mm_response_byteenable[3] == 1); // reading from the upper byte (byte offset 7) pops the fifo
scfifo the_response_FIFO (
.clock (clk),
.aclr (reset),
.sclr (sw_reset),
.data (fifo_input),
.wrreq (done_strobe),
.rdreq (fifo_read),
.q (fifo_output),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used)
);
defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_response_FIFO.lpm_showahead = "ON";
defparam the_response_FIFO.use_eab = "ON";
defparam the_response_FIFO.overflow_checking = "OFF";
defparam the_response_FIFO.underflow_checking = "OFF";
defparam the_response_FIFO.add_ram_output_register = "ON";
defparam the_response_FIFO.lpm_type = "scfifo";
// either actual bytes transfered when address == 0 or {zero padding, early_termination, error[7:0]} when address = 1
assign mm_response_readdata = (mm_response_address == 0)? fifo_output[31:0] : {{23{1'b0}}, fifo_output[40:32]};
assign mm_response_waitrequest = fifo_empty;
assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount
assign response_fifo_full = fifo_full;
assign response_fifo_empty = fifo_empty;
// no streaming port so ground all of its outputs
assign src_response_data = 0;
assign src_response_valid = 0;
end
else if (RESPONSE_PORT == 1) // streaming source port used for response data (prefetcher will catch this data)
begin
assign fifo_input = {early_termination_IRQ_mask, error_IRQ_mask, transfer_complete_IRQ_mask, early_termination, error, actual_bytes_transferred};
assign fifo_read = (fifo_empty == 0) & (src_response_ready == 1);
scfifo the_response_FIFO (
.clock (clk),
.aclr (reset | sw_reset),
.data (fifo_input),
.wrreq (done_strobe),
.rdreq (fifo_read),
.q (fifo_output),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used)
);
defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_response_FIFO.lpm_showahead = "ON";
defparam the_response_FIFO.use_eab = "ON";
defparam the_response_FIFO.overflow_checking = "OFF";
defparam the_response_FIFO.underflow_checking = "OFF";
defparam the_response_FIFO.add_ram_output_register = "ON";
defparam the_response_FIFO.lpm_type = "scfifo";
assign src_response_data = {{204{1'b0}}, descriptor_buffer_full, fifo_output}; // zero padding the upper bits, also sending out the descriptor buffer full signal to simplify the throttling in the prefetching master (bit 52)
assign src_response_valid = (fifo_empty == 0);
assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount;
assign response_fifo_full = fifo_full;
assign response_fifo_empty = fifo_empty;
// no slave port so ground all of its outputs
assign mm_response_readdata = 0;
assign mm_response_waitrequest = 0;
end
else // no response port so grounding all outputs
begin
assign fifo_input = 0;
assign fifo_output = 0;
assign mm_response_readdata = 0;
assign mm_response_waitrequest = 0;
assign src_response_data = 0;
assign src_response_valid = 0;
assign response_watermark = 0;
assign response_fifo_full = 0;
assign response_fifo_empty = 0;
end
endgenerate
endmodule
|
module dma_pcie_bridge
(
clk,
reset,
// DMA interface (slave)
dma_address,
dma_read,
dma_readdata,
dma_readdatavalid,
dma_write,
dma_writedata,
dma_burstcount,
dma_byteenable,
dma_waitrequest,
// PCIe interface (master)
pcie_address,
pcie_read,
pcie_readdata,
pcie_readdatavalid,
pcie_write,
pcie_writedata,
pcie_burstcount,
pcie_byteenable,
pcie_waitrequest
);
// Parameters set from the GUI
parameter DMA_WIDTH = 256;
parameter PCIE_WIDTH = 64;
parameter DMA_BURSTCOUNT = 6;
parameter PCIE_BURSTCOUNT = 10;
parameter PCIE_ADDR_WIDTH = 30; // Byte-address width required
parameter ADDR_OFFSET = 0;
// Derived parameters
localparam DMA_WIDTH_BYTES = DMA_WIDTH / 8;
localparam PCIE_WIDTH_BYTES = PCIE_WIDTH / 8;
localparam WIDTH_RATIO = DMA_WIDTH / PCIE_WIDTH;
localparam ADDR_SHIFT = $clog2( WIDTH_RATIO );
localparam DMA_ADDR_WIDTH = PCIE_ADDR_WIDTH - $clog2( DMA_WIDTH_BYTES );
// Global ports
input clk;
input reset;
// DMA slave ports
input [DMA_ADDR_WIDTH-1:0] dma_address;
input dma_read;
output [DMA_WIDTH-1:0 ]dma_readdata;
output dma_readdatavalid;
input dma_write;
input [DMA_WIDTH-1:0] dma_writedata;
input [DMA_BURSTCOUNT-1:0] dma_burstcount;
input [DMA_WIDTH_BYTES-1:0] dma_byteenable;
output dma_waitrequest;
// PCIe master ports
output [31:0] pcie_address;
output pcie_read;
input [PCIE_WIDTH-1:0] pcie_readdata;
input pcie_readdatavalid;
output pcie_write;
output [PCIE_WIDTH-1:0] pcie_writedata;
output [PCIE_BURSTCOUNT-1:0] pcie_burstcount;
output [PCIE_WIDTH_BYTES-1:0] pcie_byteenable;
input pcie_waitrequest;
// Address decoding into byte-address
wire [31:0] dma_byte_address;
assign dma_byte_address = (dma_address * DMA_WIDTH_BYTES);
// Read logic - Buffer the pcie words into a full-sized dma word. The
// last word gets passed through, the first few words are stored
reg [DMA_WIDTH-1:0] r_buffer; // The last PCIE_WIDTH bits are not used and will be swept away
reg [$clog2(WIDTH_RATIO)-1:0] r_wc;
reg [DMA_WIDTH-1:0] r_demux;
wire [DMA_WIDTH-1:0] r_data;
wire r_full;
wire r_waitrequest;
// Full indicates that a full word is ready to be passed on to the DMA
// as soon as the next pcie-word arrives
assign r_full = &r_wc;
// True when a read request is being stalled (not a function of this unit)
assign r_waitrequest = pcie_waitrequest;
// Groups the previously stored words with the next read data on the pcie bus
assign r_data = {pcie_readdata, r_buffer[DMA_WIDTH-PCIE_WIDTH-1:0]};
// Store the first returned words in a buffer, keep track of which word
// we are waiting for in the word counter (r_wc)
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
r_wc <= {$clog2(DMA_WIDTH){1'b0}};
r_buffer <= {(DMA_WIDTH){1'b0}};
end
else
begin
r_wc <= pcie_readdatavalid ? (r_wc + 1) : r_wc;
if(pcie_readdatavalid)
r_buffer[ r_wc*PCIE_WIDTH +: PCIE_WIDTH ] <= pcie_readdata;
end
end
// Write logic - First word passes through, last words are registered
// and passed on to the fabric in order. Master is stalled until the
// full write has been completed (in PCIe word sized segments)
reg [$clog2(WIDTH_RATIO)-1:0] w_wc;
wire [PCIE_WIDTH_BYTES-1:0] w_byteenable;
wire [PCIE_WIDTH-1:0] w_writedata;
wire w_waitrequest;
wire w_sent;
// Indicates the successful transfer of a pcie-word to PCIe
assign w_sent = pcie_write && !pcie_waitrequest;
// Select the appropriate word to send downstream
assign w_writedata = dma_writedata[w_wc*PCIE_WIDTH +: PCIE_WIDTH];
assign w_byteenable = dma_byteenable[w_wc*PCIE_WIDTH_BYTES +: PCIE_WIDTH_BYTES];
// True when avalon is waiting, or the full word has not been written
assign w_waitrequest = (pcie_write && !(&w_wc)) || pcie_waitrequest;
// Keep track of which word segment we are sending in the word counter (w_wc)
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
w_wc <= {$clog2(DMA_WIDTH){1'b0}};
else
w_wc <= w_sent ? (w_wc + 1) : w_wc;
end
// Shared read/write logic
assign pcie_address = ADDR_OFFSET + dma_byte_address;
assign pcie_read = dma_read;
assign pcie_write = dma_write;
assign pcie_writedata = w_writedata;
assign pcie_burstcount = (dma_burstcount << ADDR_SHIFT);
assign pcie_byteenable = pcie_write ? w_byteenable : dma_byteenable;
assign dma_readdata = r_data;
assign dma_readdatavalid = r_full && pcie_readdatavalid;
assign dma_waitrequest = r_waitrequest || w_waitrequest;
endmodule
|
module dma_pcie_bridge
(
clk,
reset,
// DMA interface (slave)
dma_address,
dma_read,
dma_readdata,
dma_readdatavalid,
dma_write,
dma_writedata,
dma_burstcount,
dma_byteenable,
dma_waitrequest,
// PCIe interface (master)
pcie_address,
pcie_read,
pcie_readdata,
pcie_readdatavalid,
pcie_write,
pcie_writedata,
pcie_burstcount,
pcie_byteenable,
pcie_waitrequest
);
// Parameters set from the GUI
parameter DMA_WIDTH = 256;
parameter PCIE_WIDTH = 64;
parameter DMA_BURSTCOUNT = 6;
parameter PCIE_BURSTCOUNT = 10;
parameter PCIE_ADDR_WIDTH = 30; // Byte-address width required
parameter ADDR_OFFSET = 0;
// Derived parameters
localparam DMA_WIDTH_BYTES = DMA_WIDTH / 8;
localparam PCIE_WIDTH_BYTES = PCIE_WIDTH / 8;
localparam WIDTH_RATIO = DMA_WIDTH / PCIE_WIDTH;
localparam ADDR_SHIFT = $clog2( WIDTH_RATIO );
localparam DMA_ADDR_WIDTH = PCIE_ADDR_WIDTH - $clog2( DMA_WIDTH_BYTES );
// Global ports
input clk;
input reset;
// DMA slave ports
input [DMA_ADDR_WIDTH-1:0] dma_address;
input dma_read;
output [DMA_WIDTH-1:0 ]dma_readdata;
output dma_readdatavalid;
input dma_write;
input [DMA_WIDTH-1:0] dma_writedata;
input [DMA_BURSTCOUNT-1:0] dma_burstcount;
input [DMA_WIDTH_BYTES-1:0] dma_byteenable;
output dma_waitrequest;
// PCIe master ports
output [31:0] pcie_address;
output pcie_read;
input [PCIE_WIDTH-1:0] pcie_readdata;
input pcie_readdatavalid;
output pcie_write;
output [PCIE_WIDTH-1:0] pcie_writedata;
output [PCIE_BURSTCOUNT-1:0] pcie_burstcount;
output [PCIE_WIDTH_BYTES-1:0] pcie_byteenable;
input pcie_waitrequest;
// Address decoding into byte-address
wire [31:0] dma_byte_address;
assign dma_byte_address = (dma_address * DMA_WIDTH_BYTES);
// Read logic - Buffer the pcie words into a full-sized dma word. The
// last word gets passed through, the first few words are stored
reg [DMA_WIDTH-1:0] r_buffer; // The last PCIE_WIDTH bits are not used and will be swept away
reg [$clog2(WIDTH_RATIO)-1:0] r_wc;
reg [DMA_WIDTH-1:0] r_demux;
wire [DMA_WIDTH-1:0] r_data;
wire r_full;
wire r_waitrequest;
// Full indicates that a full word is ready to be passed on to the DMA
// as soon as the next pcie-word arrives
assign r_full = &r_wc;
// True when a read request is being stalled (not a function of this unit)
assign r_waitrequest = pcie_waitrequest;
// Groups the previously stored words with the next read data on the pcie bus
assign r_data = {pcie_readdata, r_buffer[DMA_WIDTH-PCIE_WIDTH-1:0]};
// Store the first returned words in a buffer, keep track of which word
// we are waiting for in the word counter (r_wc)
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
r_wc <= {$clog2(DMA_WIDTH){1'b0}};
r_buffer <= {(DMA_WIDTH){1'b0}};
end
else
begin
r_wc <= pcie_readdatavalid ? (r_wc + 1) : r_wc;
if(pcie_readdatavalid)
r_buffer[ r_wc*PCIE_WIDTH +: PCIE_WIDTH ] <= pcie_readdata;
end
end
// Write logic - First word passes through, last words are registered
// and passed on to the fabric in order. Master is stalled until the
// full write has been completed (in PCIe word sized segments)
reg [$clog2(WIDTH_RATIO)-1:0] w_wc;
wire [PCIE_WIDTH_BYTES-1:0] w_byteenable;
wire [PCIE_WIDTH-1:0] w_writedata;
wire w_waitrequest;
wire w_sent;
// Indicates the successful transfer of a pcie-word to PCIe
assign w_sent = pcie_write && !pcie_waitrequest;
// Select the appropriate word to send downstream
assign w_writedata = dma_writedata[w_wc*PCIE_WIDTH +: PCIE_WIDTH];
assign w_byteenable = dma_byteenable[w_wc*PCIE_WIDTH_BYTES +: PCIE_WIDTH_BYTES];
// True when avalon is waiting, or the full word has not been written
assign w_waitrequest = (pcie_write && !(&w_wc)) || pcie_waitrequest;
// Keep track of which word segment we are sending in the word counter (w_wc)
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
w_wc <= {$clog2(DMA_WIDTH){1'b0}};
else
w_wc <= w_sent ? (w_wc + 1) : w_wc;
end
// Shared read/write logic
assign pcie_address = ADDR_OFFSET + dma_byte_address;
assign pcie_read = dma_read;
assign pcie_write = dma_write;
assign pcie_writedata = w_writedata;
assign pcie_burstcount = (dma_burstcount << ADDR_SHIFT);
assign pcie_byteenable = pcie_write ? w_byteenable : dma_byteenable;
assign dma_readdata = r_data;
assign dma_readdatavalid = r_full && pcie_readdatavalid;
assign dma_waitrequest = r_waitrequest || w_waitrequest;
endmodule
|
module dma_pcie_bridge
(
clk,
reset,
// DMA interface (slave)
dma_address,
dma_read,
dma_readdata,
dma_readdatavalid,
dma_write,
dma_writedata,
dma_burstcount,
dma_byteenable,
dma_waitrequest,
// PCIe interface (master)
pcie_address,
pcie_read,
pcie_readdata,
pcie_readdatavalid,
pcie_write,
pcie_writedata,
pcie_burstcount,
pcie_byteenable,
pcie_waitrequest
);
// Parameters set from the GUI
parameter DMA_WIDTH = 256;
parameter PCIE_WIDTH = 64;
parameter DMA_BURSTCOUNT = 6;
parameter PCIE_BURSTCOUNT = 10;
parameter PCIE_ADDR_WIDTH = 30; // Byte-address width required
parameter ADDR_OFFSET = 0;
// Derived parameters
localparam DMA_WIDTH_BYTES = DMA_WIDTH / 8;
localparam PCIE_WIDTH_BYTES = PCIE_WIDTH / 8;
localparam WIDTH_RATIO = DMA_WIDTH / PCIE_WIDTH;
localparam ADDR_SHIFT = $clog2( WIDTH_RATIO );
localparam DMA_ADDR_WIDTH = PCIE_ADDR_WIDTH - $clog2( DMA_WIDTH_BYTES );
// Global ports
input clk;
input reset;
// DMA slave ports
input [DMA_ADDR_WIDTH-1:0] dma_address;
input dma_read;
output [DMA_WIDTH-1:0 ]dma_readdata;
output dma_readdatavalid;
input dma_write;
input [DMA_WIDTH-1:0] dma_writedata;
input [DMA_BURSTCOUNT-1:0] dma_burstcount;
input [DMA_WIDTH_BYTES-1:0] dma_byteenable;
output dma_waitrequest;
// PCIe master ports
output [31:0] pcie_address;
output pcie_read;
input [PCIE_WIDTH-1:0] pcie_readdata;
input pcie_readdatavalid;
output pcie_write;
output [PCIE_WIDTH-1:0] pcie_writedata;
output [PCIE_BURSTCOUNT-1:0] pcie_burstcount;
output [PCIE_WIDTH_BYTES-1:0] pcie_byteenable;
input pcie_waitrequest;
// Address decoding into byte-address
wire [31:0] dma_byte_address;
assign dma_byte_address = (dma_address * DMA_WIDTH_BYTES);
// Read logic - Buffer the pcie words into a full-sized dma word. The
// last word gets passed through, the first few words are stored
reg [DMA_WIDTH-1:0] r_buffer; // The last PCIE_WIDTH bits are not used and will be swept away
reg [$clog2(WIDTH_RATIO)-1:0] r_wc;
reg [DMA_WIDTH-1:0] r_demux;
wire [DMA_WIDTH-1:0] r_data;
wire r_full;
wire r_waitrequest;
// Full indicates that a full word is ready to be passed on to the DMA
// as soon as the next pcie-word arrives
assign r_full = &r_wc;
// True when a read request is being stalled (not a function of this unit)
assign r_waitrequest = pcie_waitrequest;
// Groups the previously stored words with the next read data on the pcie bus
assign r_data = {pcie_readdata, r_buffer[DMA_WIDTH-PCIE_WIDTH-1:0]};
// Store the first returned words in a buffer, keep track of which word
// we are waiting for in the word counter (r_wc)
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
r_wc <= {$clog2(DMA_WIDTH){1'b0}};
r_buffer <= {(DMA_WIDTH){1'b0}};
end
else
begin
r_wc <= pcie_readdatavalid ? (r_wc + 1) : r_wc;
if(pcie_readdatavalid)
r_buffer[ r_wc*PCIE_WIDTH +: PCIE_WIDTH ] <= pcie_readdata;
end
end
// Write logic - First word passes through, last words are registered
// and passed on to the fabric in order. Master is stalled until the
// full write has been completed (in PCIe word sized segments)
reg [$clog2(WIDTH_RATIO)-1:0] w_wc;
wire [PCIE_WIDTH_BYTES-1:0] w_byteenable;
wire [PCIE_WIDTH-1:0] w_writedata;
wire w_waitrequest;
wire w_sent;
// Indicates the successful transfer of a pcie-word to PCIe
assign w_sent = pcie_write && !pcie_waitrequest;
// Select the appropriate word to send downstream
assign w_writedata = dma_writedata[w_wc*PCIE_WIDTH +: PCIE_WIDTH];
assign w_byteenable = dma_byteenable[w_wc*PCIE_WIDTH_BYTES +: PCIE_WIDTH_BYTES];
// True when avalon is waiting, or the full word has not been written
assign w_waitrequest = (pcie_write && !(&w_wc)) || pcie_waitrequest;
// Keep track of which word segment we are sending in the word counter (w_wc)
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
w_wc <= {$clog2(DMA_WIDTH){1'b0}};
else
w_wc <= w_sent ? (w_wc + 1) : w_wc;
end
// Shared read/write logic
assign pcie_address = ADDR_OFFSET + dma_byte_address;
assign pcie_read = dma_read;
assign pcie_write = dma_write;
assign pcie_writedata = w_writedata;
assign pcie_burstcount = (dma_burstcount << ADDR_SHIFT);
assign pcie_byteenable = pcie_write ? w_byteenable : dma_byteenable;
assign dma_readdata = r_data;
assign dma_readdatavalid = r_full && pcie_readdatavalid;
assign dma_waitrequest = r_waitrequest || w_waitrequest;
endmodule
|
module dma_pcie_bridge
(
clk,
reset,
// DMA interface (slave)
dma_address,
dma_read,
dma_readdata,
dma_readdatavalid,
dma_write,
dma_writedata,
dma_burstcount,
dma_byteenable,
dma_waitrequest,
// PCIe interface (master)
pcie_address,
pcie_read,
pcie_readdata,
pcie_readdatavalid,
pcie_write,
pcie_writedata,
pcie_burstcount,
pcie_byteenable,
pcie_waitrequest
);
// Parameters set from the GUI
parameter DMA_WIDTH = 256;
parameter PCIE_WIDTH = 64;
parameter DMA_BURSTCOUNT = 6;
parameter PCIE_BURSTCOUNT = 10;
parameter PCIE_ADDR_WIDTH = 30; // Byte-address width required
parameter ADDR_OFFSET = 0;
// Derived parameters
localparam DMA_WIDTH_BYTES = DMA_WIDTH / 8;
localparam PCIE_WIDTH_BYTES = PCIE_WIDTH / 8;
localparam WIDTH_RATIO = DMA_WIDTH / PCIE_WIDTH;
localparam ADDR_SHIFT = $clog2( WIDTH_RATIO );
localparam DMA_ADDR_WIDTH = PCIE_ADDR_WIDTH - $clog2( DMA_WIDTH_BYTES );
// Global ports
input clk;
input reset;
// DMA slave ports
input [DMA_ADDR_WIDTH-1:0] dma_address;
input dma_read;
output [DMA_WIDTH-1:0 ]dma_readdata;
output dma_readdatavalid;
input dma_write;
input [DMA_WIDTH-1:0] dma_writedata;
input [DMA_BURSTCOUNT-1:0] dma_burstcount;
input [DMA_WIDTH_BYTES-1:0] dma_byteenable;
output dma_waitrequest;
// PCIe master ports
output [31:0] pcie_address;
output pcie_read;
input [PCIE_WIDTH-1:0] pcie_readdata;
input pcie_readdatavalid;
output pcie_write;
output [PCIE_WIDTH-1:0] pcie_writedata;
output [PCIE_BURSTCOUNT-1:0] pcie_burstcount;
output [PCIE_WIDTH_BYTES-1:0] pcie_byteenable;
input pcie_waitrequest;
// Address decoding into byte-address
wire [31:0] dma_byte_address;
assign dma_byte_address = (dma_address * DMA_WIDTH_BYTES);
// Read logic - Buffer the pcie words into a full-sized dma word. The
// last word gets passed through, the first few words are stored
reg [DMA_WIDTH-1:0] r_buffer; // The last PCIE_WIDTH bits are not used and will be swept away
reg [$clog2(WIDTH_RATIO)-1:0] r_wc;
reg [DMA_WIDTH-1:0] r_demux;
wire [DMA_WIDTH-1:0] r_data;
wire r_full;
wire r_waitrequest;
// Full indicates that a full word is ready to be passed on to the DMA
// as soon as the next pcie-word arrives
assign r_full = &r_wc;
// True when a read request is being stalled (not a function of this unit)
assign r_waitrequest = pcie_waitrequest;
// Groups the previously stored words with the next read data on the pcie bus
assign r_data = {pcie_readdata, r_buffer[DMA_WIDTH-PCIE_WIDTH-1:0]};
// Store the first returned words in a buffer, keep track of which word
// we are waiting for in the word counter (r_wc)
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
r_wc <= {$clog2(DMA_WIDTH){1'b0}};
r_buffer <= {(DMA_WIDTH){1'b0}};
end
else
begin
r_wc <= pcie_readdatavalid ? (r_wc + 1) : r_wc;
if(pcie_readdatavalid)
r_buffer[ r_wc*PCIE_WIDTH +: PCIE_WIDTH ] <= pcie_readdata;
end
end
// Write logic - First word passes through, last words are registered
// and passed on to the fabric in order. Master is stalled until the
// full write has been completed (in PCIe word sized segments)
reg [$clog2(WIDTH_RATIO)-1:0] w_wc;
wire [PCIE_WIDTH_BYTES-1:0] w_byteenable;
wire [PCIE_WIDTH-1:0] w_writedata;
wire w_waitrequest;
wire w_sent;
// Indicates the successful transfer of a pcie-word to PCIe
assign w_sent = pcie_write && !pcie_waitrequest;
// Select the appropriate word to send downstream
assign w_writedata = dma_writedata[w_wc*PCIE_WIDTH +: PCIE_WIDTH];
assign w_byteenable = dma_byteenable[w_wc*PCIE_WIDTH_BYTES +: PCIE_WIDTH_BYTES];
// True when avalon is waiting, or the full word has not been written
assign w_waitrequest = (pcie_write && !(&w_wc)) || pcie_waitrequest;
// Keep track of which word segment we are sending in the word counter (w_wc)
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
w_wc <= {$clog2(DMA_WIDTH){1'b0}};
else
w_wc <= w_sent ? (w_wc + 1) : w_wc;
end
// Shared read/write logic
assign pcie_address = ADDR_OFFSET + dma_byte_address;
assign pcie_read = dma_read;
assign pcie_write = dma_write;
assign pcie_writedata = w_writedata;
assign pcie_burstcount = (dma_burstcount << ADDR_SHIFT);
assign pcie_byteenable = pcie_write ? w_byteenable : dma_byteenable;
assign dma_readdata = r_data;
assign dma_readdatavalid = r_full && pcie_readdatavalid;
assign dma_waitrequest = r_waitrequest || w_waitrequest;
endmodule
|
module channel_ram
( // System
input txclk, input reset,
// USB side
input [31:0] datain, input WR, input WR_done, output have_space,
// Reader side
output [31:0] dataout, input RD, input RD_done, output packet_waiting);
reg [6:0] wr_addr, rd_addr;
reg [1:0] which_ram_wr, which_ram_rd;
reg [2:0] nb_packets;
reg [31:0] ram0 [0:127];
reg [31:0] ram1 [0:127];
reg [31:0] ram2 [0:127];
reg [31:0] ram3 [0:127];
reg [31:0] dataout0;
reg [31:0] dataout1;
reg [31:0] dataout2;
reg [31:0] dataout3;
wire wr_done_int;
wire rd_done_int;
wire [6:0] rd_addr_final;
wire [1:0] which_ram_rd_final;
// USB side
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd0)) ram0[wr_addr] <= datain;
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd1)) ram1[wr_addr] <= datain;
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd2)) ram2[wr_addr] <= datain;
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd3)) ram3[wr_addr] <= datain;
assign wr_done_int = ((WR && (wr_addr == 7'd127)) || WR_done);
always @(posedge txclk)
if(reset)
wr_addr <= 0;
else if (WR_done)
wr_addr <= 0;
else if (WR)
wr_addr <= wr_addr + 7'd1;
always @(posedge txclk)
if(reset)
which_ram_wr <= 0;
else if (wr_done_int)
which_ram_wr <= which_ram_wr + 2'd1;
assign have_space = (nb_packets < 3'd3);
// Reader side
// short hand fifo
// rd_addr_final is what rd_addr is going to be next clock cycle
// which_ram_rd_final is what which_ram_rd is going to be next clock cycle
always @(posedge txclk) dataout0 <= ram0[rd_addr_final];
always @(posedge txclk) dataout1 <= ram1[rd_addr_final];
always @(posedge txclk) dataout2 <= ram2[rd_addr_final];
always @(posedge txclk) dataout3 <= ram3[rd_addr_final];
assign dataout = (which_ram_rd_final[1]) ?
(which_ram_rd_final[0] ? dataout3 : dataout2) :
(which_ram_rd_final[0] ? dataout1 : dataout0);
//RD_done is the only way to signal the end of one packet
assign rd_done_int = RD_done;
always @(posedge txclk)
if (reset)
rd_addr <= 0;
else if (RD_done)
rd_addr <= 0;
else if (RD)
rd_addr <= rd_addr + 7'd1;
assign rd_addr_final = (reset|RD_done) ? (6'd0) :
((RD)?(rd_addr+7'd1):rd_addr);
always @(posedge txclk)
if (reset)
which_ram_rd <= 0;
else if (rd_done_int)
which_ram_rd <= which_ram_rd + 2'd1;
assign which_ram_rd_final = (reset) ? (2'd0):
((rd_done_int) ? (which_ram_rd + 2'd1) : which_ram_rd);
//packet_waiting is set to zero if rd_done_int is high
//because there is no guarantee that nb_packets will be pos.
assign packet_waiting = (nb_packets > 1) | ((nb_packets == 1)&(~rd_done_int));
always @(posedge txclk)
if (reset)
nb_packets <= 0;
else if (wr_done_int & ~rd_done_int)
nb_packets <= nb_packets + 3'd1;
else if (rd_done_int & ~wr_done_int)
nb_packets <= nb_packets - 3'd1;
endmodule
|
module channel_ram
( // System
input txclk, input reset,
// USB side
input [31:0] datain, input WR, input WR_done, output have_space,
// Reader side
output [31:0] dataout, input RD, input RD_done, output packet_waiting);
reg [6:0] wr_addr, rd_addr;
reg [1:0] which_ram_wr, which_ram_rd;
reg [2:0] nb_packets;
reg [31:0] ram0 [0:127];
reg [31:0] ram1 [0:127];
reg [31:0] ram2 [0:127];
reg [31:0] ram3 [0:127];
reg [31:0] dataout0;
reg [31:0] dataout1;
reg [31:0] dataout2;
reg [31:0] dataout3;
wire wr_done_int;
wire rd_done_int;
wire [6:0] rd_addr_final;
wire [1:0] which_ram_rd_final;
// USB side
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd0)) ram0[wr_addr] <= datain;
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd1)) ram1[wr_addr] <= datain;
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd2)) ram2[wr_addr] <= datain;
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd3)) ram3[wr_addr] <= datain;
assign wr_done_int = ((WR && (wr_addr == 7'd127)) || WR_done);
always @(posedge txclk)
if(reset)
wr_addr <= 0;
else if (WR_done)
wr_addr <= 0;
else if (WR)
wr_addr <= wr_addr + 7'd1;
always @(posedge txclk)
if(reset)
which_ram_wr <= 0;
else if (wr_done_int)
which_ram_wr <= which_ram_wr + 2'd1;
assign have_space = (nb_packets < 3'd3);
// Reader side
// short hand fifo
// rd_addr_final is what rd_addr is going to be next clock cycle
// which_ram_rd_final is what which_ram_rd is going to be next clock cycle
always @(posedge txclk) dataout0 <= ram0[rd_addr_final];
always @(posedge txclk) dataout1 <= ram1[rd_addr_final];
always @(posedge txclk) dataout2 <= ram2[rd_addr_final];
always @(posedge txclk) dataout3 <= ram3[rd_addr_final];
assign dataout = (which_ram_rd_final[1]) ?
(which_ram_rd_final[0] ? dataout3 : dataout2) :
(which_ram_rd_final[0] ? dataout1 : dataout0);
//RD_done is the only way to signal the end of one packet
assign rd_done_int = RD_done;
always @(posedge txclk)
if (reset)
rd_addr <= 0;
else if (RD_done)
rd_addr <= 0;
else if (RD)
rd_addr <= rd_addr + 7'd1;
assign rd_addr_final = (reset|RD_done) ? (6'd0) :
((RD)?(rd_addr+7'd1):rd_addr);
always @(posedge txclk)
if (reset)
which_ram_rd <= 0;
else if (rd_done_int)
which_ram_rd <= which_ram_rd + 2'd1;
assign which_ram_rd_final = (reset) ? (2'd0):
((rd_done_int) ? (which_ram_rd + 2'd1) : which_ram_rd);
//packet_waiting is set to zero if rd_done_int is high
//because there is no guarantee that nb_packets will be pos.
assign packet_waiting = (nb_packets > 1) | ((nb_packets == 1)&(~rd_done_int));
always @(posedge txclk)
if (reset)
nb_packets <= 0;
else if (wr_done_int & ~rd_done_int)
nb_packets <= nb_packets + 3'd1;
else if (rd_done_int & ~wr_done_int)
nb_packets <= nb_packets - 3'd1;
endmodule
|
module channel_ram
( // System
input txclk, input reset,
// USB side
input [31:0] datain, input WR, input WR_done, output have_space,
// Reader side
output [31:0] dataout, input RD, input RD_done, output packet_waiting);
reg [6:0] wr_addr, rd_addr;
reg [1:0] which_ram_wr, which_ram_rd;
reg [2:0] nb_packets;
reg [31:0] ram0 [0:127];
reg [31:0] ram1 [0:127];
reg [31:0] ram2 [0:127];
reg [31:0] ram3 [0:127];
reg [31:0] dataout0;
reg [31:0] dataout1;
reg [31:0] dataout2;
reg [31:0] dataout3;
wire wr_done_int;
wire rd_done_int;
wire [6:0] rd_addr_final;
wire [1:0] which_ram_rd_final;
// USB side
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd0)) ram0[wr_addr] <= datain;
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd1)) ram1[wr_addr] <= datain;
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd2)) ram2[wr_addr] <= datain;
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd3)) ram3[wr_addr] <= datain;
assign wr_done_int = ((WR && (wr_addr == 7'd127)) || WR_done);
always @(posedge txclk)
if(reset)
wr_addr <= 0;
else if (WR_done)
wr_addr <= 0;
else if (WR)
wr_addr <= wr_addr + 7'd1;
always @(posedge txclk)
if(reset)
which_ram_wr <= 0;
else if (wr_done_int)
which_ram_wr <= which_ram_wr + 2'd1;
assign have_space = (nb_packets < 3'd3);
// Reader side
// short hand fifo
// rd_addr_final is what rd_addr is going to be next clock cycle
// which_ram_rd_final is what which_ram_rd is going to be next clock cycle
always @(posedge txclk) dataout0 <= ram0[rd_addr_final];
always @(posedge txclk) dataout1 <= ram1[rd_addr_final];
always @(posedge txclk) dataout2 <= ram2[rd_addr_final];
always @(posedge txclk) dataout3 <= ram3[rd_addr_final];
assign dataout = (which_ram_rd_final[1]) ?
(which_ram_rd_final[0] ? dataout3 : dataout2) :
(which_ram_rd_final[0] ? dataout1 : dataout0);
//RD_done is the only way to signal the end of one packet
assign rd_done_int = RD_done;
always @(posedge txclk)
if (reset)
rd_addr <= 0;
else if (RD_done)
rd_addr <= 0;
else if (RD)
rd_addr <= rd_addr + 7'd1;
assign rd_addr_final = (reset|RD_done) ? (6'd0) :
((RD)?(rd_addr+7'd1):rd_addr);
always @(posedge txclk)
if (reset)
which_ram_rd <= 0;
else if (rd_done_int)
which_ram_rd <= which_ram_rd + 2'd1;
assign which_ram_rd_final = (reset) ? (2'd0):
((rd_done_int) ? (which_ram_rd + 2'd1) : which_ram_rd);
//packet_waiting is set to zero if rd_done_int is high
//because there is no guarantee that nb_packets will be pos.
assign packet_waiting = (nb_packets > 1) | ((nb_packets == 1)&(~rd_done_int));
always @(posedge txclk)
if (reset)
nb_packets <= 0;
else if (wr_done_int & ~rd_done_int)
nb_packets <= nb_packets + 3'd1;
else if (rd_done_int & ~wr_done_int)
nb_packets <= nb_packets - 3'd1;
endmodule
|
module channel_ram
( // System
input txclk, input reset,
// USB side
input [31:0] datain, input WR, input WR_done, output have_space,
// Reader side
output [31:0] dataout, input RD, input RD_done, output packet_waiting);
reg [6:0] wr_addr, rd_addr;
reg [1:0] which_ram_wr, which_ram_rd;
reg [2:0] nb_packets;
reg [31:0] ram0 [0:127];
reg [31:0] ram1 [0:127];
reg [31:0] ram2 [0:127];
reg [31:0] ram3 [0:127];
reg [31:0] dataout0;
reg [31:0] dataout1;
reg [31:0] dataout2;
reg [31:0] dataout3;
wire wr_done_int;
wire rd_done_int;
wire [6:0] rd_addr_final;
wire [1:0] which_ram_rd_final;
// USB side
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd0)) ram0[wr_addr] <= datain;
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd1)) ram1[wr_addr] <= datain;
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd2)) ram2[wr_addr] <= datain;
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd3)) ram3[wr_addr] <= datain;
assign wr_done_int = ((WR && (wr_addr == 7'd127)) || WR_done);
always @(posedge txclk)
if(reset)
wr_addr <= 0;
else if (WR_done)
wr_addr <= 0;
else if (WR)
wr_addr <= wr_addr + 7'd1;
always @(posedge txclk)
if(reset)
which_ram_wr <= 0;
else if (wr_done_int)
which_ram_wr <= which_ram_wr + 2'd1;
assign have_space = (nb_packets < 3'd3);
// Reader side
// short hand fifo
// rd_addr_final is what rd_addr is going to be next clock cycle
// which_ram_rd_final is what which_ram_rd is going to be next clock cycle
always @(posedge txclk) dataout0 <= ram0[rd_addr_final];
always @(posedge txclk) dataout1 <= ram1[rd_addr_final];
always @(posedge txclk) dataout2 <= ram2[rd_addr_final];
always @(posedge txclk) dataout3 <= ram3[rd_addr_final];
assign dataout = (which_ram_rd_final[1]) ?
(which_ram_rd_final[0] ? dataout3 : dataout2) :
(which_ram_rd_final[0] ? dataout1 : dataout0);
//RD_done is the only way to signal the end of one packet
assign rd_done_int = RD_done;
always @(posedge txclk)
if (reset)
rd_addr <= 0;
else if (RD_done)
rd_addr <= 0;
else if (RD)
rd_addr <= rd_addr + 7'd1;
assign rd_addr_final = (reset|RD_done) ? (6'd0) :
((RD)?(rd_addr+7'd1):rd_addr);
always @(posedge txclk)
if (reset)
which_ram_rd <= 0;
else if (rd_done_int)
which_ram_rd <= which_ram_rd + 2'd1;
assign which_ram_rd_final = (reset) ? (2'd0):
((rd_done_int) ? (which_ram_rd + 2'd1) : which_ram_rd);
//packet_waiting is set to zero if rd_done_int is high
//because there is no guarantee that nb_packets will be pos.
assign packet_waiting = (nb_packets > 1) | ((nb_packets == 1)&(~rd_done_int));
always @(posedge txclk)
if (reset)
nb_packets <= 0;
else if (wr_done_int & ~rd_done_int)
nb_packets <= nb_packets + 3'd1;
else if (rd_done_int & ~wr_done_int)
nb_packets <= nb_packets - 3'd1;
endmodule
|
module generic_baseblocks_v2_1_0_mux_enc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_RATIO = 4,
// Mux select ratio. Can be any binary value (>= 1)
parameter integer C_SEL_WIDTH = 2,
// Log2-ceiling of C_RATIO (>= 1)
parameter integer C_DATA_WIDTH = 1
// Data width for generic_baseblocks_v2_1_0_comparator (>= 1)
)
(
input wire [C_SEL_WIDTH-1:0] S,
input wire [C_RATIO*C_DATA_WIDTH-1:0] A,
output wire [C_DATA_WIDTH-1:0] O,
input wire OE
);
wire [C_DATA_WIDTH-1:0] o_i;
genvar bit_cnt;
function [C_DATA_WIDTH-1:0] f_mux
(
input [C_SEL_WIDTH-1:0] s,
input [C_RATIO*C_DATA_WIDTH-1:0] a
);
integer i;
reg [C_RATIO*C_DATA_WIDTH-1:0] carry;
begin
carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc
carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] =
carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |
({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);
end
f_mux = carry[C_DATA_WIDTH*C_RATIO-1:C_DATA_WIDTH*(C_RATIO-1)];
end
endfunction
function [C_DATA_WIDTH-1:0] f_mux4
(
input [1:0] s,
input [4*C_DATA_WIDTH-1:0] a
);
integer i;
reg [4*C_DATA_WIDTH-1:0] carry;
begin
carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];
for (i=1;i<4;i=i+1) begin : gen_carrychain_enc
carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] =
carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |
({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);
end
f_mux4 = carry[C_DATA_WIDTH*4-1:C_DATA_WIDTH*3];
end
endfunction
assign O = o_i & {C_DATA_WIDTH{OE}}; // OE is gated AFTER any MUXF7/8 (can only optimize forward into downstream logic)
generate
if ( C_RATIO < 2 ) begin : gen_bypass
assign o_i = A;
end else if ( C_FAMILY == "rtl" || C_RATIO < 5 ) begin : gen_rtl
assign o_i = f_mux(S, A);
end else begin : gen_fpga
wire [C_DATA_WIDTH-1:0] l;
wire [C_DATA_WIDTH-1:0] h;
wire [C_DATA_WIDTH-1:0] ll;
wire [C_DATA_WIDTH-1:0] lh;
wire [C_DATA_WIDTH-1:0] hl;
wire [C_DATA_WIDTH-1:0] hh;
case (C_RATIO)
1, 5, 9, 13:
assign hh = A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH];
2, 6, 10, 14:
assign hh = S[0] ?
A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ;
3, 7, 11, 15:
assign hh = S[1] ?
A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
(S[0] ?
A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] );
4, 8, 12, 16:
assign hh = S[1] ?
(S[0] ?
A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ) :
(S[0] ?
A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-4)*C_DATA_WIDTH +: C_DATA_WIDTH] );
17:
assign hh = S[1] ?
(S[0] ?
A[15*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[14*C_DATA_WIDTH +: C_DATA_WIDTH] ) :
(S[0] ?
A[13*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[12*C_DATA_WIDTH +: C_DATA_WIDTH] );
default:
assign hh = 0;
endcase
case (C_RATIO)
5, 6, 7, 8: begin
assign l = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_5_8
MUXF7 mux_s2_inst
(
.I0 (l[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[2]),
.O (o_i[bit_cnt])
);
end
end
9, 10, 11, 12: begin
assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_9_12
MUXF7 muxf_s2_low_inst
(
.I0 (ll[bit_cnt]),
.I1 (lh[bit_cnt]),
.S (S[2]),
.O (l[bit_cnt])
);
MUXF8 muxf_s3_inst
(
.I0 (l[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[3]),
.O (o_i[bit_cnt])
);
end
end
13,14,15,16: begin
assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_13_16
MUXF7 muxf_s2_low_inst
(
.I0 (ll[bit_cnt]),
.I1 (lh[bit_cnt]),
.S (S[2]),
.O (l[bit_cnt])
);
MUXF7 muxf_s2_hi_inst
(
.I0 (hl[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[2]),
.O (h[bit_cnt])
);
MUXF8 muxf_s3_inst
(
.I0 (l[bit_cnt]),
.I1 (h[bit_cnt]),
.S (S[3]),
.O (o_i[bit_cnt])
);
end
end
17: begin
assign ll = S[4] ? A[16*C_DATA_WIDTH +: C_DATA_WIDTH] : f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]); // 5-input mux
assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_17
MUXF7 muxf_s2_low_inst
(
.I0 (ll[bit_cnt]),
.I1 (lh[bit_cnt]),
.S (S[2]),
.O (l[bit_cnt])
);
MUXF7 muxf_s2_hi_inst
(
.I0 (hl[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[2]),
.O (h[bit_cnt])
);
MUXF8 muxf_s3_inst
(
.I0 (l[bit_cnt]),
.I1 (h[bit_cnt]),
.S (S[3]),
.O (o_i[bit_cnt])
);
end
end
default: // If RATIO > 17, use RTL
assign o_i = f_mux(S, A);
endcase
end // gen_fpga
endgenerate
endmodule
|
module generic_baseblocks_v2_1_0_mux_enc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_RATIO = 4,
// Mux select ratio. Can be any binary value (>= 1)
parameter integer C_SEL_WIDTH = 2,
// Log2-ceiling of C_RATIO (>= 1)
parameter integer C_DATA_WIDTH = 1
// Data width for generic_baseblocks_v2_1_0_comparator (>= 1)
)
(
input wire [C_SEL_WIDTH-1:0] S,
input wire [C_RATIO*C_DATA_WIDTH-1:0] A,
output wire [C_DATA_WIDTH-1:0] O,
input wire OE
);
wire [C_DATA_WIDTH-1:0] o_i;
genvar bit_cnt;
function [C_DATA_WIDTH-1:0] f_mux
(
input [C_SEL_WIDTH-1:0] s,
input [C_RATIO*C_DATA_WIDTH-1:0] a
);
integer i;
reg [C_RATIO*C_DATA_WIDTH-1:0] carry;
begin
carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc
carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] =
carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |
({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);
end
f_mux = carry[C_DATA_WIDTH*C_RATIO-1:C_DATA_WIDTH*(C_RATIO-1)];
end
endfunction
function [C_DATA_WIDTH-1:0] f_mux4
(
input [1:0] s,
input [4*C_DATA_WIDTH-1:0] a
);
integer i;
reg [4*C_DATA_WIDTH-1:0] carry;
begin
carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];
for (i=1;i<4;i=i+1) begin : gen_carrychain_enc
carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] =
carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |
({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);
end
f_mux4 = carry[C_DATA_WIDTH*4-1:C_DATA_WIDTH*3];
end
endfunction
assign O = o_i & {C_DATA_WIDTH{OE}}; // OE is gated AFTER any MUXF7/8 (can only optimize forward into downstream logic)
generate
if ( C_RATIO < 2 ) begin : gen_bypass
assign o_i = A;
end else if ( C_FAMILY == "rtl" || C_RATIO < 5 ) begin : gen_rtl
assign o_i = f_mux(S, A);
end else begin : gen_fpga
wire [C_DATA_WIDTH-1:0] l;
wire [C_DATA_WIDTH-1:0] h;
wire [C_DATA_WIDTH-1:0] ll;
wire [C_DATA_WIDTH-1:0] lh;
wire [C_DATA_WIDTH-1:0] hl;
wire [C_DATA_WIDTH-1:0] hh;
case (C_RATIO)
1, 5, 9, 13:
assign hh = A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH];
2, 6, 10, 14:
assign hh = S[0] ?
A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ;
3, 7, 11, 15:
assign hh = S[1] ?
A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
(S[0] ?
A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] );
4, 8, 12, 16:
assign hh = S[1] ?
(S[0] ?
A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ) :
(S[0] ?
A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-4)*C_DATA_WIDTH +: C_DATA_WIDTH] );
17:
assign hh = S[1] ?
(S[0] ?
A[15*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[14*C_DATA_WIDTH +: C_DATA_WIDTH] ) :
(S[0] ?
A[13*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[12*C_DATA_WIDTH +: C_DATA_WIDTH] );
default:
assign hh = 0;
endcase
case (C_RATIO)
5, 6, 7, 8: begin
assign l = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_5_8
MUXF7 mux_s2_inst
(
.I0 (l[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[2]),
.O (o_i[bit_cnt])
);
end
end
9, 10, 11, 12: begin
assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_9_12
MUXF7 muxf_s2_low_inst
(
.I0 (ll[bit_cnt]),
.I1 (lh[bit_cnt]),
.S (S[2]),
.O (l[bit_cnt])
);
MUXF8 muxf_s3_inst
(
.I0 (l[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[3]),
.O (o_i[bit_cnt])
);
end
end
13,14,15,16: begin
assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_13_16
MUXF7 muxf_s2_low_inst
(
.I0 (ll[bit_cnt]),
.I1 (lh[bit_cnt]),
.S (S[2]),
.O (l[bit_cnt])
);
MUXF7 muxf_s2_hi_inst
(
.I0 (hl[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[2]),
.O (h[bit_cnt])
);
MUXF8 muxf_s3_inst
(
.I0 (l[bit_cnt]),
.I1 (h[bit_cnt]),
.S (S[3]),
.O (o_i[bit_cnt])
);
end
end
17: begin
assign ll = S[4] ? A[16*C_DATA_WIDTH +: C_DATA_WIDTH] : f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]); // 5-input mux
assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_17
MUXF7 muxf_s2_low_inst
(
.I0 (ll[bit_cnt]),
.I1 (lh[bit_cnt]),
.S (S[2]),
.O (l[bit_cnt])
);
MUXF7 muxf_s2_hi_inst
(
.I0 (hl[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[2]),
.O (h[bit_cnt])
);
MUXF8 muxf_s3_inst
(
.I0 (l[bit_cnt]),
.I1 (h[bit_cnt]),
.S (S[3]),
.O (o_i[bit_cnt])
);
end
end
default: // If RATIO > 17, use RTL
assign o_i = f_mux(S, A);
endcase
end // gen_fpga
endgenerate
endmodule
|
module temp_sense_alttemp_sense_v8t
(
ce,
clk,
clr,
tsdcaldone,
tsdcalo) /* synthesis synthesis_clearbox=2 */;
input ce;
input clk;
input clr;
output tsdcaldone;
output [7:0] tsdcalo;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 ce;
tri0 clr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_sd1_tsdcaldone;
wire [7:0] wire_sd1_tsdcalo;
stratixv_tsdblock sd1
(
.ce(ce),
.clk(clk),
.clr(clr),
.tsdcaldone(wire_sd1_tsdcaldone),
.tsdcalo(wire_sd1_tsdcalo));
defparam
sd1.clock_divider_enable = "true",
sd1.clock_divider_value = 80,
sd1.sim_tsdcalo = 0,
sd1.lpm_type = "stratixv_tsdblock";
assign
tsdcaldone = wire_sd1_tsdcaldone,
tsdcalo = wire_sd1_tsdcalo;
endmodule
|
module temp_sense (
ce,
clk,
clr,
tsdcaldone,
tsdcalo)/* synthesis synthesis_clearbox = 2 */;
input ce;
input clk;
input clr;
output tsdcaldone;
output [7:0] tsdcalo;
wire [7:0] sub_wire0;
wire sub_wire1;
wire [7:0] tsdcalo = sub_wire0[7:0];
wire tsdcaldone = sub_wire1;
temp_sense_alttemp_sense_v8t temp_sense_alttemp_sense_v8t_component (
.ce (ce),
.clk (clk),
.clr (clr),
.tsdcalo (sub_wire0),
.tsdcaldone (sub_wire1))/* synthesis synthesis_clearbox=2
clearbox_macroname = ALTTEMP_SENSE
clearbox_defparam = "clk_frequency=50.0;clock_divider_enable=ON;clock_divider_value=80;intended_device_family=Stratix V;lpm_hint=UNUSED;lpm_type=alttemp_sense;number_of_samples=128;poi_cal_temperature=85;sim_tsdcalo=0;user_offset_enable=off;use_wys=on;" */;
endmodule
|
module usb_packet_fifo
( input reset,
input clock_in,
input clock_out,
input [15:0]ram_data_in,
input write_enable,
output reg [15:0]ram_data_out,
output reg pkt_waiting,
output reg have_space,
input read_enable,
input skip_packet ) ;
/* Some parameters for usage later on */
parameter DATA_WIDTH = 16 ;
parameter NUM_PACKETS = 4 ;
/* Create the RAM here */
reg [DATA_WIDTH-1:0] usb_ram [256*NUM_PACKETS-1:0] ;
/* Create the address signals */
reg [7-2+NUM_PACKETS:0] usb_ram_ain ;
reg [7:0] usb_ram_offset ;
reg [1:0] usb_ram_packet ;
wire [7-2+NUM_PACKETS:0] usb_ram_aout ;
reg isfull;
assign usb_ram_aout = {usb_ram_packet,usb_ram_offset} ;
// Check if there is one full packet to process
always @(usb_ram_ain, usb_ram_aout)
begin
if (reset)
pkt_waiting <= 0;
else if (usb_ram_ain == usb_ram_aout)
pkt_waiting <= isfull;
else if (usb_ram_ain > usb_ram_aout)
pkt_waiting <= (usb_ram_ain - usb_ram_aout) >= 256;
else
pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >= 256;
end
// Check if there is room
always @(usb_ram_ain, usb_ram_aout)
begin
if (reset)
have_space <= 1;
else if (usb_ram_ain == usb_ram_aout)
have_space <= ~isfull;
else if (usb_ram_ain > usb_ram_aout)
have_space <= (usb_ram_ain - usb_ram_aout) <= 256 * (NUM_PACKETS - 1);
else
have_space <= (usb_ram_aout - usb_ram_ain) >= 256;
end
/* RAM Write Address process */
always @(posedge clock_in)
begin
if( reset )
usb_ram_ain <= 0 ;
else
if( write_enable )
begin
usb_ram_ain <= usb_ram_ain + 1 ;
if (usb_ram_ain + 1 == usb_ram_aout)
isfull <= 1;
end
end
/* RAM Writing process */
always @(posedge clock_in)
begin
if( write_enable )
begin
usb_ram[usb_ram_ain] <= ram_data_in ;
end
end
/* RAM Read Address process */
always @(posedge clock_out)
begin
if( reset )
begin
usb_ram_packet <= 0 ;
usb_ram_offset <= 0 ;
isfull <= 0;
end
else
if( skip_packet )
begin
usb_ram_packet <= usb_ram_packet + 1 ;
usb_ram_offset <= 0 ;
end
else if(read_enable)
if( usb_ram_offset == 8'b11111111 )
begin
usb_ram_offset <= 0 ;
usb_ram_packet <= usb_ram_packet + 1 ;
end
else
usb_ram_offset <= usb_ram_offset + 1 ;
if (usb_ram_ain == usb_ram_aout)
isfull <= 0;
end
/* RAM Reading Process */
always @(posedge clock_out)
begin
ram_data_out <= usb_ram[usb_ram_aout] ;
end
endmodule
|
module usb_packet_fifo
( input reset,
input clock_in,
input clock_out,
input [15:0]ram_data_in,
input write_enable,
output reg [15:0]ram_data_out,
output reg pkt_waiting,
output reg have_space,
input read_enable,
input skip_packet ) ;
/* Some parameters for usage later on */
parameter DATA_WIDTH = 16 ;
parameter NUM_PACKETS = 4 ;
/* Create the RAM here */
reg [DATA_WIDTH-1:0] usb_ram [256*NUM_PACKETS-1:0] ;
/* Create the address signals */
reg [7-2+NUM_PACKETS:0] usb_ram_ain ;
reg [7:0] usb_ram_offset ;
reg [1:0] usb_ram_packet ;
wire [7-2+NUM_PACKETS:0] usb_ram_aout ;
reg isfull;
assign usb_ram_aout = {usb_ram_packet,usb_ram_offset} ;
// Check if there is one full packet to process
always @(usb_ram_ain, usb_ram_aout)
begin
if (reset)
pkt_waiting <= 0;
else if (usb_ram_ain == usb_ram_aout)
pkt_waiting <= isfull;
else if (usb_ram_ain > usb_ram_aout)
pkt_waiting <= (usb_ram_ain - usb_ram_aout) >= 256;
else
pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >= 256;
end
// Check if there is room
always @(usb_ram_ain, usb_ram_aout)
begin
if (reset)
have_space <= 1;
else if (usb_ram_ain == usb_ram_aout)
have_space <= ~isfull;
else if (usb_ram_ain > usb_ram_aout)
have_space <= (usb_ram_ain - usb_ram_aout) <= 256 * (NUM_PACKETS - 1);
else
have_space <= (usb_ram_aout - usb_ram_ain) >= 256;
end
/* RAM Write Address process */
always @(posedge clock_in)
begin
if( reset )
usb_ram_ain <= 0 ;
else
if( write_enable )
begin
usb_ram_ain <= usb_ram_ain + 1 ;
if (usb_ram_ain + 1 == usb_ram_aout)
isfull <= 1;
end
end
/* RAM Writing process */
always @(posedge clock_in)
begin
if( write_enable )
begin
usb_ram[usb_ram_ain] <= ram_data_in ;
end
end
/* RAM Read Address process */
always @(posedge clock_out)
begin
if( reset )
begin
usb_ram_packet <= 0 ;
usb_ram_offset <= 0 ;
isfull <= 0;
end
else
if( skip_packet )
begin
usb_ram_packet <= usb_ram_packet + 1 ;
usb_ram_offset <= 0 ;
end
else if(read_enable)
if( usb_ram_offset == 8'b11111111 )
begin
usb_ram_offset <= 0 ;
usb_ram_packet <= usb_ram_packet + 1 ;
end
else
usb_ram_offset <= usb_ram_offset + 1 ;
if (usb_ram_ain == usb_ram_aout)
isfull <= 0;
end
/* RAM Reading Process */
always @(posedge clock_out)
begin
ram_data_out <= usb_ram[usb_ram_aout] ;
end
endmodule
|
module usb_packet_fifo
( input reset,
input clock_in,
input clock_out,
input [15:0]ram_data_in,
input write_enable,
output reg [15:0]ram_data_out,
output reg pkt_waiting,
output reg have_space,
input read_enable,
input skip_packet ) ;
/* Some parameters for usage later on */
parameter DATA_WIDTH = 16 ;
parameter NUM_PACKETS = 4 ;
/* Create the RAM here */
reg [DATA_WIDTH-1:0] usb_ram [256*NUM_PACKETS-1:0] ;
/* Create the address signals */
reg [7-2+NUM_PACKETS:0] usb_ram_ain ;
reg [7:0] usb_ram_offset ;
reg [1:0] usb_ram_packet ;
wire [7-2+NUM_PACKETS:0] usb_ram_aout ;
reg isfull;
assign usb_ram_aout = {usb_ram_packet,usb_ram_offset} ;
// Check if there is one full packet to process
always @(usb_ram_ain, usb_ram_aout)
begin
if (reset)
pkt_waiting <= 0;
else if (usb_ram_ain == usb_ram_aout)
pkt_waiting <= isfull;
else if (usb_ram_ain > usb_ram_aout)
pkt_waiting <= (usb_ram_ain - usb_ram_aout) >= 256;
else
pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >= 256;
end
// Check if there is room
always @(usb_ram_ain, usb_ram_aout)
begin
if (reset)
have_space <= 1;
else if (usb_ram_ain == usb_ram_aout)
have_space <= ~isfull;
else if (usb_ram_ain > usb_ram_aout)
have_space <= (usb_ram_ain - usb_ram_aout) <= 256 * (NUM_PACKETS - 1);
else
have_space <= (usb_ram_aout - usb_ram_ain) >= 256;
end
/* RAM Write Address process */
always @(posedge clock_in)
begin
if( reset )
usb_ram_ain <= 0 ;
else
if( write_enable )
begin
usb_ram_ain <= usb_ram_ain + 1 ;
if (usb_ram_ain + 1 == usb_ram_aout)
isfull <= 1;
end
end
/* RAM Writing process */
always @(posedge clock_in)
begin
if( write_enable )
begin
usb_ram[usb_ram_ain] <= ram_data_in ;
end
end
/* RAM Read Address process */
always @(posedge clock_out)
begin
if( reset )
begin
usb_ram_packet <= 0 ;
usb_ram_offset <= 0 ;
isfull <= 0;
end
else
if( skip_packet )
begin
usb_ram_packet <= usb_ram_packet + 1 ;
usb_ram_offset <= 0 ;
end
else if(read_enable)
if( usb_ram_offset == 8'b11111111 )
begin
usb_ram_offset <= 0 ;
usb_ram_packet <= usb_ram_packet + 1 ;
end
else
usb_ram_offset <= usb_ram_offset + 1 ;
if (usb_ram_ain == usb_ram_aout)
isfull <= 0;
end
/* RAM Reading Process */
always @(posedge clock_out)
begin
ram_data_out <= usb_ram[usb_ram_aout] ;
end
endmodule
|
module write_signal_breakout (
write_command_data_in, // descriptor from the write FIFO
write_command_data_out, // reformated descriptor to the write master
// breakout of command information
write_address,
write_length,
write_park,
write_end_on_eop,
write_transfer_complete_IRQ_mask,
write_early_termination_IRQ_mask,
write_error_IRQ_mask,
write_burst_count, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
write_stride, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
write_sequence_number, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
// additional control information that needs to go out asynchronously with the command data
write_stop,
write_sw_reset
);
parameter DATA_WIDTH = 256; // 256 bits when enhanced settings are enabled otherwise 128 bits
input [DATA_WIDTH-1:0] write_command_data_in;
output wire [255:0] write_command_data_out;
output wire [63:0] write_address;
output wire [31:0] write_length;
output wire write_park;
output wire write_end_on_eop;
output wire write_transfer_complete_IRQ_mask;
output wire write_early_termination_IRQ_mask;
output wire [7:0] write_error_IRQ_mask;
output wire [7:0] write_burst_count;
output wire [15:0] write_stride;
output wire [15:0] write_sequence_number;
input write_stop;
input write_sw_reset;
assign write_address[31:0] = write_command_data_in[63:32];
assign write_length = write_command_data_in[95:64];
generate
if (DATA_WIDTH == 256)
begin
assign write_park = write_command_data_in[235];
assign write_end_on_eop = write_command_data_in[236];
assign write_transfer_complete_IRQ_mask = write_command_data_in[238];
assign write_early_termination_IRQ_mask = write_command_data_in[239];
assign write_error_IRQ_mask = write_command_data_in[247:240];
assign write_burst_count = write_command_data_in[127:120];
assign write_stride = write_command_data_in[159:144];
assign write_sequence_number = write_command_data_in[111:96];
assign write_address[63:32] = write_command_data_in[223:192];
end
else
begin
assign write_park = write_command_data_in[107];
assign write_end_on_eop = write_command_data_in[108];
assign write_transfer_complete_IRQ_mask = write_command_data_in[110];
assign write_early_termination_IRQ_mask = write_command_data_in[111];
assign write_error_IRQ_mask = write_command_data_in[119:112];
assign write_burst_count = 8'h00;
assign write_stride = 16'h0000;
assign write_sequence_number = 16'h0000;
assign write_address[63:32] = 32'h00000000;
end
endgenerate
// big concat statement to glue all the signals back together to go out to the write master (MSBs to LSBs)
assign write_command_data_out = {{132{1'b0}}, // zero pad the upper 132 bits
write_address[63:32],
write_stride,
write_burst_count,
write_sw_reset,
write_stop,
1'b0, // used to be the early termination bit so now it's reserved
write_end_on_eop,
write_length,
write_address[31:0]};
endmodule
|
module write_signal_breakout (
write_command_data_in, // descriptor from the write FIFO
write_command_data_out, // reformated descriptor to the write master
// breakout of command information
write_address,
write_length,
write_park,
write_end_on_eop,
write_transfer_complete_IRQ_mask,
write_early_termination_IRQ_mask,
write_error_IRQ_mask,
write_burst_count, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
write_stride, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
write_sequence_number, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
// additional control information that needs to go out asynchronously with the command data
write_stop,
write_sw_reset
);
parameter DATA_WIDTH = 256; // 256 bits when enhanced settings are enabled otherwise 128 bits
input [DATA_WIDTH-1:0] write_command_data_in;
output wire [255:0] write_command_data_out;
output wire [63:0] write_address;
output wire [31:0] write_length;
output wire write_park;
output wire write_end_on_eop;
output wire write_transfer_complete_IRQ_mask;
output wire write_early_termination_IRQ_mask;
output wire [7:0] write_error_IRQ_mask;
output wire [7:0] write_burst_count;
output wire [15:0] write_stride;
output wire [15:0] write_sequence_number;
input write_stop;
input write_sw_reset;
assign write_address[31:0] = write_command_data_in[63:32];
assign write_length = write_command_data_in[95:64];
generate
if (DATA_WIDTH == 256)
begin
assign write_park = write_command_data_in[235];
assign write_end_on_eop = write_command_data_in[236];
assign write_transfer_complete_IRQ_mask = write_command_data_in[238];
assign write_early_termination_IRQ_mask = write_command_data_in[239];
assign write_error_IRQ_mask = write_command_data_in[247:240];
assign write_burst_count = write_command_data_in[127:120];
assign write_stride = write_command_data_in[159:144];
assign write_sequence_number = write_command_data_in[111:96];
assign write_address[63:32] = write_command_data_in[223:192];
end
else
begin
assign write_park = write_command_data_in[107];
assign write_end_on_eop = write_command_data_in[108];
assign write_transfer_complete_IRQ_mask = write_command_data_in[110];
assign write_early_termination_IRQ_mask = write_command_data_in[111];
assign write_error_IRQ_mask = write_command_data_in[119:112];
assign write_burst_count = 8'h00;
assign write_stride = 16'h0000;
assign write_sequence_number = 16'h0000;
assign write_address[63:32] = 32'h00000000;
end
endgenerate
// big concat statement to glue all the signals back together to go out to the write master (MSBs to LSBs)
assign write_command_data_out = {{132{1'b0}}, // zero pad the upper 132 bits
write_address[63:32],
write_stride,
write_burst_count,
write_sw_reset,
write_stop,
1'b0, // used to be the early termination bit so now it's reserved
write_end_on_eop,
write_length,
write_address[31:0]};
endmodule
|
module write_signal_breakout (
write_command_data_in, // descriptor from the write FIFO
write_command_data_out, // reformated descriptor to the write master
// breakout of command information
write_address,
write_length,
write_park,
write_end_on_eop,
write_transfer_complete_IRQ_mask,
write_early_termination_IRQ_mask,
write_error_IRQ_mask,
write_burst_count, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
write_stride, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
write_sequence_number, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
// additional control information that needs to go out asynchronously with the command data
write_stop,
write_sw_reset
);
parameter DATA_WIDTH = 256; // 256 bits when enhanced settings are enabled otherwise 128 bits
input [DATA_WIDTH-1:0] write_command_data_in;
output wire [255:0] write_command_data_out;
output wire [63:0] write_address;
output wire [31:0] write_length;
output wire write_park;
output wire write_end_on_eop;
output wire write_transfer_complete_IRQ_mask;
output wire write_early_termination_IRQ_mask;
output wire [7:0] write_error_IRQ_mask;
output wire [7:0] write_burst_count;
output wire [15:0] write_stride;
output wire [15:0] write_sequence_number;
input write_stop;
input write_sw_reset;
assign write_address[31:0] = write_command_data_in[63:32];
assign write_length = write_command_data_in[95:64];
generate
if (DATA_WIDTH == 256)
begin
assign write_park = write_command_data_in[235];
assign write_end_on_eop = write_command_data_in[236];
assign write_transfer_complete_IRQ_mask = write_command_data_in[238];
assign write_early_termination_IRQ_mask = write_command_data_in[239];
assign write_error_IRQ_mask = write_command_data_in[247:240];
assign write_burst_count = write_command_data_in[127:120];
assign write_stride = write_command_data_in[159:144];
assign write_sequence_number = write_command_data_in[111:96];
assign write_address[63:32] = write_command_data_in[223:192];
end
else
begin
assign write_park = write_command_data_in[107];
assign write_end_on_eop = write_command_data_in[108];
assign write_transfer_complete_IRQ_mask = write_command_data_in[110];
assign write_early_termination_IRQ_mask = write_command_data_in[111];
assign write_error_IRQ_mask = write_command_data_in[119:112];
assign write_burst_count = 8'h00;
assign write_stride = 16'h0000;
assign write_sequence_number = 16'h0000;
assign write_address[63:32] = 32'h00000000;
end
endgenerate
// big concat statement to glue all the signals back together to go out to the write master (MSBs to LSBs)
assign write_command_data_out = {{132{1'b0}}, // zero pad the upper 132 bits
write_address[63:32],
write_stride,
write_burst_count,
write_sw_reset,
write_stop,
1'b0, // used to be the early termination bit so now it's reserved
write_end_on_eop,
write_length,
write_address[31:0]};
endmodule
|
module unpipeline #
(
parameter WIDTH_D = 256,
parameter S_WIDTH_A = 26,
parameter M_WIDTH_A = S_WIDTH_A+$clog2(WIDTH_D/8),
parameter BURSTCOUNT_WIDTH = 1,
parameter BYTEENABLE_WIDTH = WIDTH_D,
parameter MAX_PENDING_READS = 64
)
(
input clk,
input resetn,
// Slave port
input [S_WIDTH_A-1:0] slave_address, // Word address
input [WIDTH_D-1:0] slave_writedata,
input slave_read,
input slave_write,
input [BURSTCOUNT_WIDTH-1:0] slave_burstcount,
input [BYTEENABLE_WIDTH-1:0] slave_byteenable,
output slave_waitrequest,
output [WIDTH_D-1:0] slave_readdata,
output slave_readdatavalid,
output [M_WIDTH_A-1:0] master_address, // Byte address
output [WIDTH_D-1:0] master_writedata,
output master_read,
output master_write,
output [BYTEENABLE_WIDTH-1:0] master_byteenable,
input master_waitrequest,
input [WIDTH_D-1:0] master_readdata
);
assign master_read = slave_read;
assign master_write = slave_write;
assign master_writedata = slave_writedata;
assign master_address = {slave_address,{$clog2(WIDTH_D/8){1'b0}}}; //byteaddr
assign master_byteenable = slave_byteenable;
assign slave_waitrequest = master_waitrequest;
assign slave_readdatavalid = slave_read & ~master_waitrequest;
assign slave_readdata = master_readdata;
endmodule
|
module unpipeline #
(
parameter WIDTH_D = 256,
parameter S_WIDTH_A = 26,
parameter M_WIDTH_A = S_WIDTH_A+$clog2(WIDTH_D/8),
parameter BURSTCOUNT_WIDTH = 1,
parameter BYTEENABLE_WIDTH = WIDTH_D,
parameter MAX_PENDING_READS = 64
)
(
input clk,
input resetn,
// Slave port
input [S_WIDTH_A-1:0] slave_address, // Word address
input [WIDTH_D-1:0] slave_writedata,
input slave_read,
input slave_write,
input [BURSTCOUNT_WIDTH-1:0] slave_burstcount,
input [BYTEENABLE_WIDTH-1:0] slave_byteenable,
output slave_waitrequest,
output [WIDTH_D-1:0] slave_readdata,
output slave_readdatavalid,
output [M_WIDTH_A-1:0] master_address, // Byte address
output [WIDTH_D-1:0] master_writedata,
output master_read,
output master_write,
output [BYTEENABLE_WIDTH-1:0] master_byteenable,
input master_waitrequest,
input [WIDTH_D-1:0] master_readdata
);
assign master_read = slave_read;
assign master_write = slave_write;
assign master_writedata = slave_writedata;
assign master_address = {slave_address,{$clog2(WIDTH_D/8){1'b0}}}; //byteaddr
assign master_byteenable = slave_byteenable;
assign slave_waitrequest = master_waitrequest;
assign slave_readdatavalid = slave_read & ~master_waitrequest;
assign slave_readdata = master_readdata;
endmodule
|
module csr_block (
clk,
reset,
csr_writedata,
csr_write,
csr_byteenable,
csr_readdata,
csr_read,
csr_address,
csr_irq,
done_strobe,
busy,
descriptor_buffer_empty,
descriptor_buffer_full,
stop_state,
stopped_on_error,
stopped_on_early_termination,
reset_stalled,
stop,
sw_reset,
stop_on_error,
stop_on_early_termination,
stop_descriptors,
sequence_number,
descriptor_watermark,
response_watermark,
response_buffer_empty,
response_buffer_full,
transfer_complete_IRQ_mask,
error_IRQ_mask,
early_termination_IRQ_mask,
error,
early_termination
);
parameter ADDRESS_WIDTH = 3;
localparam CONTROL_REGISTER_ADDRESS = 3'b001;
input clk;
input reset;
input [31:0] csr_writedata;
input csr_write;
input [3:0] csr_byteenable;
output wire [31:0] csr_readdata;
input csr_read;
input [ADDRESS_WIDTH-1:0] csr_address;
output wire csr_irq;
input done_strobe;
input busy;
input descriptor_buffer_empty;
input descriptor_buffer_full;
input stop_state; // when the DMA runs into some error condition and you have enabled the stop on error (or when the stop control bit is written to)
input reset_stalled; // the read or write master could be in the middle of a transfer/burst so it might take a while to flush the buffers
output wire stop;
output reg stopped_on_error;
output reg stopped_on_early_termination;
output reg sw_reset;
output wire stop_on_error;
output wire stop_on_early_termination;
output wire stop_descriptors;
input [31:0] sequence_number;
input [31:0] descriptor_watermark;
input [15:0] response_watermark;
input response_buffer_empty;
input response_buffer_full;
input transfer_complete_IRQ_mask;
input [7:0] error_IRQ_mask;
input early_termination_IRQ_mask;
input [7:0] error;
input early_termination;
/* Internal wires and registers */
wire [31:0] status;
reg [31:0] control;
reg [31:0] readdata;
reg [31:0] readdata_d1;
reg irq; // writing to the status register clears the irq bit
wire set_irq;
wire clear_irq;
reg [15:0] irq_count; // writing to bit 0 clears the counter
wire clear_irq_count;
wire incr_irq_count;
wire set_stopped_on_error;
wire set_stopped_on_early_termination;
wire set_stop;
wire clear_stop;
wire global_interrupt_enable;
wire sw_reset_strobe; // this strobe will be one cycle earlier than sw_reset
wire set_sw_reset;
wire clear_sw_reset;
/********************************************** Registers ***************************************************/
// read latency is 1 cycle
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
readdata_d1 <= 0;
end
else if (csr_read == 1)
begin
readdata_d1 <= readdata;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
control[31:1] <= 0;
end
else
begin
if (sw_reset_strobe == 1) // reset strobe is a strobe due to this sync reset
begin
control[31:1] <= 0;
end
else
begin
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1))
begin
control[7:1] <= csr_writedata[7:1]; // stop bit will be handled seperately since it can be set by the csr slave port access or the SGDMA hitting an error condition
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[1] == 1))
begin
control[15:8] <= csr_writedata[15:8];
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[2] == 1))
begin
control[23:16] <= csr_writedata[23:16];
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[3] == 1))
begin
control[31:24] <= csr_writedata[31:24];
end
end
end
end
// control bit 0 (stop) is set by different sources so handling it seperately
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
control[0] <= 0;
end
else
begin
if (sw_reset_strobe == 1)
begin
control[0] <= 0;
end
else
begin
case ({set_stop, clear_stop})
2'b00: control[0] <= control[0];
2'b01: control[0] <= 1'b0;
2'b10: control[0] <= 1'b1;
2'b11: control[0] <= 1'b1; // setting will win, this case happens control[0] is being set to 0 (resume) at the same time an error/early termination stop condition occurs
endcase
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
sw_reset <= 0;
end
else
begin
if (set_sw_reset == 1)
begin
sw_reset <= 1;
end
else if (clear_sw_reset == 1)
begin
sw_reset <= 0;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped_on_error <= 0;
end
else
begin
case ({set_stopped_on_error, clear_stop})
2'b00: stopped_on_error <= stopped_on_error;
2'b01: stopped_on_error <= 1'b0;
2'b10: stopped_on_error <= 1'b1;
2'b11: stopped_on_error <= 1'b0;
endcase
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped_on_early_termination <= 0;
end
else
begin
case ({set_stopped_on_early_termination, clear_stop})
2'b00: stopped_on_early_termination <= stopped_on_early_termination;
2'b01: stopped_on_early_termination <= 1'b0;
2'b10: stopped_on_early_termination <= 1'b1;
2'b11: stopped_on_early_termination <= 1'b0;
endcase
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
irq <= 0;
end
else
begin
if (sw_reset_strobe == 1)
begin
irq <= 0;
end
else
begin
case ({clear_irq, set_irq})
2'b00: irq <= irq;
2'b01: irq <= 1'b1;
2'b10: irq <= 1'b0;
2'b11: irq <= 1'b1; // setting will win over a clear
endcase
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
irq_count <= {16{1'b0}};
end
else
begin
if (sw_reset_strobe == 1)
begin
irq_count <= {16{1'b0}};
end
else
begin
case ({clear_irq_count, incr_irq_count})
2'b00: irq_count <= irq_count;
2'b01: irq_count <= irq_count + 1;
2'b10: irq_count <= {16{1'b0}};
2'b11: irq_count <= {{15{1'b0}}, 1'b1};
endcase
end
end
end
/******************************************** End Registers *************************************************/
/**************************************** Combinational Signals *********************************************/
generate
if (ADDRESS_WIDTH == 3)
begin
always @ (csr_address or status or control or descriptor_watermark or response_watermark or sequence_number)
begin
case (csr_address)
3'b000: readdata = status;
3'b001: readdata = control;
3'b010: readdata = descriptor_watermark;
3'b011: readdata = response_watermark;
default: readdata = sequence_number; // all other addresses will decode to the sequence number
endcase
end
end
else
begin
always @ (csr_address or status or control or descriptor_watermark or response_watermark)
begin
case (csr_address)
3'b000: readdata = status;
3'b001: readdata = control;
3'b010: readdata = descriptor_watermark;
default: readdata = response_watermark; // all other addresses will decode to the response watermark
endcase
end
end
endgenerate
assign clear_irq = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[1] == 1) & (csr_writedata[9] == 1); // this is the IRQ bit
assign set_irq = (global_interrupt_enable == 1) & (done_strobe == 1) & // transfer ended and interrupts are enabled
((transfer_complete_IRQ_mask == 1) | // transfer ended and the transfer complete IRQ is enabled
((error & error_IRQ_mask) != 0) | // transfer ended with an error and this IRQ is enabled
((early_termination & early_termination_IRQ_mask) == 1)); // transfer ended early due to early termination and this IRQ is enabled
assign csr_irq = irq;
// Done count
assign incr_irq_count = set_irq; // Done count just counts the number of interrupts since the last reset
assign clear_irq_count = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[2] == 1) & (csr_writedata[16] == 1); // the LSB irq_count bit
assign clear_stop = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 0);
assign set_stopped_on_error = (done_strobe == 1) & (stop_on_error == 1) & (error != 0); // when clear_stop is set then the stopped_on_error register will be cleared
assign set_stopped_on_early_termination = (done_strobe == 1) & (stop_on_early_termination == 1) & (early_termination == 1); // when clear_stop is set then the stopped_on_early_termination register will be cleared
assign set_stop = ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 1)) | // host set the stop bit
(set_stopped_on_error == 1) | // SGDMA setup to stop when an error occurs from the write master
(set_stopped_on_early_termination == 1) ; // SGDMA setup to stop when the write master overflows
assign stop = control[0];
assign set_sw_reset = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[1] == 1);
assign clear_sw_reset = (sw_reset == 1) & (reset_stalled == 0);
assign sw_reset_strobe = control[1];
assign stop_on_error = control[2];
assign stop_on_early_termination = control[3];
assign global_interrupt_enable = control[4];
assign stop_descriptors = control[5];
assign csr_readdata = readdata_d1;
assign status = {irq_count, {6{1'b0}}, irq, stopped_on_early_termination, stopped_on_error, sw_reset, stop_state, response_buffer_full, response_buffer_empty, descriptor_buffer_full, descriptor_buffer_empty, busy}; // writing to the lower byte of the status register clears the irq bit
/**************************************** Combinational Signals *********************************************/
endmodule
|
module csr_block (
clk,
reset,
csr_writedata,
csr_write,
csr_byteenable,
csr_readdata,
csr_read,
csr_address,
csr_irq,
done_strobe,
busy,
descriptor_buffer_empty,
descriptor_buffer_full,
stop_state,
stopped_on_error,
stopped_on_early_termination,
reset_stalled,
stop,
sw_reset,
stop_on_error,
stop_on_early_termination,
stop_descriptors,
sequence_number,
descriptor_watermark,
response_watermark,
response_buffer_empty,
response_buffer_full,
transfer_complete_IRQ_mask,
error_IRQ_mask,
early_termination_IRQ_mask,
error,
early_termination
);
parameter ADDRESS_WIDTH = 3;
localparam CONTROL_REGISTER_ADDRESS = 3'b001;
input clk;
input reset;
input [31:0] csr_writedata;
input csr_write;
input [3:0] csr_byteenable;
output wire [31:0] csr_readdata;
input csr_read;
input [ADDRESS_WIDTH-1:0] csr_address;
output wire csr_irq;
input done_strobe;
input busy;
input descriptor_buffer_empty;
input descriptor_buffer_full;
input stop_state; // when the DMA runs into some error condition and you have enabled the stop on error (or when the stop control bit is written to)
input reset_stalled; // the read or write master could be in the middle of a transfer/burst so it might take a while to flush the buffers
output wire stop;
output reg stopped_on_error;
output reg stopped_on_early_termination;
output reg sw_reset;
output wire stop_on_error;
output wire stop_on_early_termination;
output wire stop_descriptors;
input [31:0] sequence_number;
input [31:0] descriptor_watermark;
input [15:0] response_watermark;
input response_buffer_empty;
input response_buffer_full;
input transfer_complete_IRQ_mask;
input [7:0] error_IRQ_mask;
input early_termination_IRQ_mask;
input [7:0] error;
input early_termination;
/* Internal wires and registers */
wire [31:0] status;
reg [31:0] control;
reg [31:0] readdata;
reg [31:0] readdata_d1;
reg irq; // writing to the status register clears the irq bit
wire set_irq;
wire clear_irq;
reg [15:0] irq_count; // writing to bit 0 clears the counter
wire clear_irq_count;
wire incr_irq_count;
wire set_stopped_on_error;
wire set_stopped_on_early_termination;
wire set_stop;
wire clear_stop;
wire global_interrupt_enable;
wire sw_reset_strobe; // this strobe will be one cycle earlier than sw_reset
wire set_sw_reset;
wire clear_sw_reset;
/********************************************** Registers ***************************************************/
// read latency is 1 cycle
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
readdata_d1 <= 0;
end
else if (csr_read == 1)
begin
readdata_d1 <= readdata;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
control[31:1] <= 0;
end
else
begin
if (sw_reset_strobe == 1) // reset strobe is a strobe due to this sync reset
begin
control[31:1] <= 0;
end
else
begin
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1))
begin
control[7:1] <= csr_writedata[7:1]; // stop bit will be handled seperately since it can be set by the csr slave port access or the SGDMA hitting an error condition
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[1] == 1))
begin
control[15:8] <= csr_writedata[15:8];
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[2] == 1))
begin
control[23:16] <= csr_writedata[23:16];
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[3] == 1))
begin
control[31:24] <= csr_writedata[31:24];
end
end
end
end
// control bit 0 (stop) is set by different sources so handling it seperately
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
control[0] <= 0;
end
else
begin
if (sw_reset_strobe == 1)
begin
control[0] <= 0;
end
else
begin
case ({set_stop, clear_stop})
2'b00: control[0] <= control[0];
2'b01: control[0] <= 1'b0;
2'b10: control[0] <= 1'b1;
2'b11: control[0] <= 1'b1; // setting will win, this case happens control[0] is being set to 0 (resume) at the same time an error/early termination stop condition occurs
endcase
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
sw_reset <= 0;
end
else
begin
if (set_sw_reset == 1)
begin
sw_reset <= 1;
end
else if (clear_sw_reset == 1)
begin
sw_reset <= 0;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped_on_error <= 0;
end
else
begin
case ({set_stopped_on_error, clear_stop})
2'b00: stopped_on_error <= stopped_on_error;
2'b01: stopped_on_error <= 1'b0;
2'b10: stopped_on_error <= 1'b1;
2'b11: stopped_on_error <= 1'b0;
endcase
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped_on_early_termination <= 0;
end
else
begin
case ({set_stopped_on_early_termination, clear_stop})
2'b00: stopped_on_early_termination <= stopped_on_early_termination;
2'b01: stopped_on_early_termination <= 1'b0;
2'b10: stopped_on_early_termination <= 1'b1;
2'b11: stopped_on_early_termination <= 1'b0;
endcase
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
irq <= 0;
end
else
begin
if (sw_reset_strobe == 1)
begin
irq <= 0;
end
else
begin
case ({clear_irq, set_irq})
2'b00: irq <= irq;
2'b01: irq <= 1'b1;
2'b10: irq <= 1'b0;
2'b11: irq <= 1'b1; // setting will win over a clear
endcase
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
irq_count <= {16{1'b0}};
end
else
begin
if (sw_reset_strobe == 1)
begin
irq_count <= {16{1'b0}};
end
else
begin
case ({clear_irq_count, incr_irq_count})
2'b00: irq_count <= irq_count;
2'b01: irq_count <= irq_count + 1;
2'b10: irq_count <= {16{1'b0}};
2'b11: irq_count <= {{15{1'b0}}, 1'b1};
endcase
end
end
end
/******************************************** End Registers *************************************************/
/**************************************** Combinational Signals *********************************************/
generate
if (ADDRESS_WIDTH == 3)
begin
always @ (csr_address or status or control or descriptor_watermark or response_watermark or sequence_number)
begin
case (csr_address)
3'b000: readdata = status;
3'b001: readdata = control;
3'b010: readdata = descriptor_watermark;
3'b011: readdata = response_watermark;
default: readdata = sequence_number; // all other addresses will decode to the sequence number
endcase
end
end
else
begin
always @ (csr_address or status or control or descriptor_watermark or response_watermark)
begin
case (csr_address)
3'b000: readdata = status;
3'b001: readdata = control;
3'b010: readdata = descriptor_watermark;
default: readdata = response_watermark; // all other addresses will decode to the response watermark
endcase
end
end
endgenerate
assign clear_irq = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[1] == 1) & (csr_writedata[9] == 1); // this is the IRQ bit
assign set_irq = (global_interrupt_enable == 1) & (done_strobe == 1) & // transfer ended and interrupts are enabled
((transfer_complete_IRQ_mask == 1) | // transfer ended and the transfer complete IRQ is enabled
((error & error_IRQ_mask) != 0) | // transfer ended with an error and this IRQ is enabled
((early_termination & early_termination_IRQ_mask) == 1)); // transfer ended early due to early termination and this IRQ is enabled
assign csr_irq = irq;
// Done count
assign incr_irq_count = set_irq; // Done count just counts the number of interrupts since the last reset
assign clear_irq_count = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[2] == 1) & (csr_writedata[16] == 1); // the LSB irq_count bit
assign clear_stop = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 0);
assign set_stopped_on_error = (done_strobe == 1) & (stop_on_error == 1) & (error != 0); // when clear_stop is set then the stopped_on_error register will be cleared
assign set_stopped_on_early_termination = (done_strobe == 1) & (stop_on_early_termination == 1) & (early_termination == 1); // when clear_stop is set then the stopped_on_early_termination register will be cleared
assign set_stop = ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 1)) | // host set the stop bit
(set_stopped_on_error == 1) | // SGDMA setup to stop when an error occurs from the write master
(set_stopped_on_early_termination == 1) ; // SGDMA setup to stop when the write master overflows
assign stop = control[0];
assign set_sw_reset = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[1] == 1);
assign clear_sw_reset = (sw_reset == 1) & (reset_stalled == 0);
assign sw_reset_strobe = control[1];
assign stop_on_error = control[2];
assign stop_on_early_termination = control[3];
assign global_interrupt_enable = control[4];
assign stop_descriptors = control[5];
assign csr_readdata = readdata_d1;
assign status = {irq_count, {6{1'b0}}, irq, stopped_on_early_termination, stopped_on_error, sw_reset, stop_state, response_buffer_full, response_buffer_empty, descriptor_buffer_full, descriptor_buffer_empty, busy}; // writing to the lower byte of the status register clears the irq bit
/**************************************** Combinational Signals *********************************************/
endmodule
|
module generic_baseblocks_v2_1_0_carry_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign COUT = CIN | S;
end else begin : USE_FPGA
wire S_n;
assign S_n = ~S;
MUXCY and_inst
(
.O (COUT),
.CI (CIN),
.DI (1'b1),
.S (S_n)
);
end
endgenerate
endmodule
|
module generic_baseblocks_v2_1_0_carry_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign COUT = CIN | S;
end else begin : USE_FPGA
wire S_n;
assign S_n = ~S;
MUXCY and_inst
(
.O (COUT),
.CI (CIN),
.DI (1'b1),
.S (S_n)
);
end
endgenerate
endmodule
|
module generic_baseblocks_v2_1_0_carry_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign COUT = CIN | S;
end else begin : USE_FPGA
wire S_n;
assign S_n = ~S;
MUXCY and_inst
(
.O (COUT),
.CI (CIN),
.DI (1'b1),
.S (S_n)
);
end
endgenerate
endmodule
|
module generic_baseblocks_v2_1_0_carry_latch_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign O = CIN | I;
end else begin : USE_FPGA
OR2L or2l_inst1
(
.O(O),
.DI(CIN),
.SRI(I)
);
end
endgenerate
endmodule
|
module generic_baseblocks_v2_1_0_carry_latch_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign O = CIN | I;
end else begin : USE_FPGA
OR2L or2l_inst1
(
.O(O),
.DI(CIN),
.SRI(I)
);
end
endgenerate
endmodule
|
module ST_to_MM_Adapter (
clk,
reset,
enable,
address,
start,
waitrequest,
stall,
write_data,
fifo_data,
fifo_empty,
fifo_readack
);
parameter DATA_WIDTH = 32;
parameter BYTEENABLE_WIDTH_LOG2 = 2;
parameter ADDRESS_WIDTH = 32;
parameter UNALIGNED_ACCESS_ENABLE = 0; // when set to 0 this block will be a pass through (save on resources when unaligned accesses are not needed)
localparam BYTES_TO_NEXT_BOUNDARY_WIDTH = BYTEENABLE_WIDTH_LOG2 + 1; // 2, 3, 4, 5, 6 for byte enable widths of 2, 4, 8, 16, 32
input clk;
input reset;
input enable; // must make sure that the adapter doesn't accept data when a transfer it doesn't know what "bytes_to_transfer" is yet
input [ADDRESS_WIDTH-1:0] address;
input start; // one cycle strobe at the start of a transfer used to determine bytes_to_transfer
input waitrequest;
input stall;
output wire [DATA_WIDTH-1:0] write_data;
input [DATA_WIDTH-1:0] fifo_data;
input fifo_empty;
output wire fifo_readack;
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-1:0] bytes_to_next_boundary;
wire [DATA_WIDTH-1:0] barrelshifter_A;
wire [DATA_WIDTH-1:0] barrelshifter_B;
reg [DATA_WIDTH-1:0] barrelshifter_B_d1;
wire [DATA_WIDTH-1:0] combined_word; // bitwise OR between barrelshifter_A and barrelshifter_B (each has zero padding so that bytelanes don't overlap)
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one; // simplifies barrelshifter select logic
reg [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one_d1;
wire [DATA_WIDTH-1:0] barrelshifter_input_A [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_A inputs
wire [DATA_WIDTH-1:0] barrelshifter_input_B [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_B inputs
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
bytes_to_next_boundary_minus_one_d1 <= 0;
end
else if (start)
begin
bytes_to_next_boundary_minus_one_d1 <= bytes_to_next_boundary_minus_one;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
barrelshifter_B_d1 <= 0;
end
else
begin
if (start == 1)
begin
barrelshifter_B_d1 <= 0;
end
else if (fifo_readack == 1)
begin
barrelshifter_B_d1 <= barrelshifter_B;
end
end
end
assign bytes_to_next_boundary = (DATA_WIDTH/8) - address[BYTEENABLE_WIDTH_LOG2-1:0]; // bytes per word - unaligned byte offset = distance to next boundary
assign bytes_to_next_boundary_minus_one = bytes_to_next_boundary - 1;
assign combined_word = barrelshifter_A | barrelshifter_B_d1;
generate
genvar input_offset;
for(input_offset = 0; input_offset < (DATA_WIDTH/8); input_offset = input_offset + 1)
begin: barrel_shifter_inputs
assign barrelshifter_input_A[input_offset] = fifo_data << (8 * ((DATA_WIDTH/8)-(input_offset+1)));
assign barrelshifter_input_B[input_offset] = fifo_data >> (8 * (input_offset + 1));
end
endgenerate
assign barrelshifter_A = barrelshifter_input_A[bytes_to_next_boundary_minus_one_d1];
assign barrelshifter_B = barrelshifter_input_B[bytes_to_next_boundary_minus_one_d1];
generate
if (UNALIGNED_ACCESS_ENABLE == 1)
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1) & (start == 0);
assign write_data = combined_word;
end
else
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1);
assign write_data = fifo_data;
end
endgenerate
endmodule
|
module ST_to_MM_Adapter (
clk,
reset,
enable,
address,
start,
waitrequest,
stall,
write_data,
fifo_data,
fifo_empty,
fifo_readack
);
parameter DATA_WIDTH = 32;
parameter BYTEENABLE_WIDTH_LOG2 = 2;
parameter ADDRESS_WIDTH = 32;
parameter UNALIGNED_ACCESS_ENABLE = 0; // when set to 0 this block will be a pass through (save on resources when unaligned accesses are not needed)
localparam BYTES_TO_NEXT_BOUNDARY_WIDTH = BYTEENABLE_WIDTH_LOG2 + 1; // 2, 3, 4, 5, 6 for byte enable widths of 2, 4, 8, 16, 32
input clk;
input reset;
input enable; // must make sure that the adapter doesn't accept data when a transfer it doesn't know what "bytes_to_transfer" is yet
input [ADDRESS_WIDTH-1:0] address;
input start; // one cycle strobe at the start of a transfer used to determine bytes_to_transfer
input waitrequest;
input stall;
output wire [DATA_WIDTH-1:0] write_data;
input [DATA_WIDTH-1:0] fifo_data;
input fifo_empty;
output wire fifo_readack;
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-1:0] bytes_to_next_boundary;
wire [DATA_WIDTH-1:0] barrelshifter_A;
wire [DATA_WIDTH-1:0] barrelshifter_B;
reg [DATA_WIDTH-1:0] barrelshifter_B_d1;
wire [DATA_WIDTH-1:0] combined_word; // bitwise OR between barrelshifter_A and barrelshifter_B (each has zero padding so that bytelanes don't overlap)
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one; // simplifies barrelshifter select logic
reg [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one_d1;
wire [DATA_WIDTH-1:0] barrelshifter_input_A [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_A inputs
wire [DATA_WIDTH-1:0] barrelshifter_input_B [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_B inputs
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
bytes_to_next_boundary_minus_one_d1 <= 0;
end
else if (start)
begin
bytes_to_next_boundary_minus_one_d1 <= bytes_to_next_boundary_minus_one;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
barrelshifter_B_d1 <= 0;
end
else
begin
if (start == 1)
begin
barrelshifter_B_d1 <= 0;
end
else if (fifo_readack == 1)
begin
barrelshifter_B_d1 <= barrelshifter_B;
end
end
end
assign bytes_to_next_boundary = (DATA_WIDTH/8) - address[BYTEENABLE_WIDTH_LOG2-1:0]; // bytes per word - unaligned byte offset = distance to next boundary
assign bytes_to_next_boundary_minus_one = bytes_to_next_boundary - 1;
assign combined_word = barrelshifter_A | barrelshifter_B_d1;
generate
genvar input_offset;
for(input_offset = 0; input_offset < (DATA_WIDTH/8); input_offset = input_offset + 1)
begin: barrel_shifter_inputs
assign barrelshifter_input_A[input_offset] = fifo_data << (8 * ((DATA_WIDTH/8)-(input_offset+1)));
assign barrelshifter_input_B[input_offset] = fifo_data >> (8 * (input_offset + 1));
end
endgenerate
assign barrelshifter_A = barrelshifter_input_A[bytes_to_next_boundary_minus_one_d1];
assign barrelshifter_B = barrelshifter_input_B[bytes_to_next_boundary_minus_one_d1];
generate
if (UNALIGNED_ACCESS_ENABLE == 1)
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1) & (start == 0);
assign write_data = combined_word;
end
else
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1);
assign write_data = fifo_data;
end
endgenerate
endmodule
|
module generic_baseblocks_v2_1_0_comparator_mask_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 3;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = C_VALUE;
assign m_local = M;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
module generic_baseblocks_v2_1_0_nto1_mux #
(
parameter integer C_RATIO = 1, // Range: >=1
parameter integer C_SEL_WIDTH = 1, // Range: >=1; recommended: ceil_log2(C_RATIO)
parameter integer C_DATAOUT_WIDTH = 1, // Range: >=1
parameter integer C_ONEHOT = 0 // Values: 0 = binary-encoded (use SEL); 1 = one-hot (use SEL_ONEHOT)
)
(
input wire [C_RATIO-1:0] SEL_ONEHOT, // One-hot generic_baseblocks_v2_1_0_mux select (only used if C_ONEHOT=1)
input wire [C_SEL_WIDTH-1:0] SEL, // Binary-encoded generic_baseblocks_v2_1_0_mux select (only used if C_ONEHOT=0)
input wire [C_RATIO*C_DATAOUT_WIDTH-1:0] IN, // Data input array (num_selections x data_width)
output wire [C_DATAOUT_WIDTH-1:0] OUT // Data output vector
);
wire [C_DATAOUT_WIDTH*C_RATIO-1:0] carry;
genvar i;
generate
if (C_ONEHOT == 0) begin : gen_encoded
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{(SEL==0)?1'b1:1'b0}} & IN[C_DATAOUT_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{(SEL==i)?1'b1:1'b0}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end else begin : gen_onehot
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{SEL_ONEHOT[0]}} & IN[C_DATAOUT_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_hot
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{SEL_ONEHOT[i]}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end
endgenerate
assign OUT = carry[C_DATAOUT_WIDTH*C_RATIO-1:
C_DATAOUT_WIDTH*(C_RATIO-1)];
endmodule
|
module generic_baseblocks_v2_1_0_nto1_mux #
(
parameter integer C_RATIO = 1, // Range: >=1
parameter integer C_SEL_WIDTH = 1, // Range: >=1; recommended: ceil_log2(C_RATIO)
parameter integer C_DATAOUT_WIDTH = 1, // Range: >=1
parameter integer C_ONEHOT = 0 // Values: 0 = binary-encoded (use SEL); 1 = one-hot (use SEL_ONEHOT)
)
(
input wire [C_RATIO-1:0] SEL_ONEHOT, // One-hot generic_baseblocks_v2_1_0_mux select (only used if C_ONEHOT=1)
input wire [C_SEL_WIDTH-1:0] SEL, // Binary-encoded generic_baseblocks_v2_1_0_mux select (only used if C_ONEHOT=0)
input wire [C_RATIO*C_DATAOUT_WIDTH-1:0] IN, // Data input array (num_selections x data_width)
output wire [C_DATAOUT_WIDTH-1:0] OUT // Data output vector
);
wire [C_DATAOUT_WIDTH*C_RATIO-1:0] carry;
genvar i;
generate
if (C_ONEHOT == 0) begin : gen_encoded
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{(SEL==0)?1'b1:1'b0}} & IN[C_DATAOUT_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{(SEL==i)?1'b1:1'b0}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end else begin : gen_onehot
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{SEL_ONEHOT[0]}} & IN[C_DATAOUT_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_hot
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{SEL_ONEHOT[i]}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end
endgenerate
assign OUT = carry[C_DATAOUT_WIDTH*C_RATIO-1:
C_DATAOUT_WIDTH*(C_RATIO-1)];
endmodule
|
module generic_baseblocks_v2_1_0_nto1_mux #
(
parameter integer C_RATIO = 1, // Range: >=1
parameter integer C_SEL_WIDTH = 1, // Range: >=1; recommended: ceil_log2(C_RATIO)
parameter integer C_DATAOUT_WIDTH = 1, // Range: >=1
parameter integer C_ONEHOT = 0 // Values: 0 = binary-encoded (use SEL); 1 = one-hot (use SEL_ONEHOT)
)
(
input wire [C_RATIO-1:0] SEL_ONEHOT, // One-hot generic_baseblocks_v2_1_0_mux select (only used if C_ONEHOT=1)
input wire [C_SEL_WIDTH-1:0] SEL, // Binary-encoded generic_baseblocks_v2_1_0_mux select (only used if C_ONEHOT=0)
input wire [C_RATIO*C_DATAOUT_WIDTH-1:0] IN, // Data input array (num_selections x data_width)
output wire [C_DATAOUT_WIDTH-1:0] OUT // Data output vector
);
wire [C_DATAOUT_WIDTH*C_RATIO-1:0] carry;
genvar i;
generate
if (C_ONEHOT == 0) begin : gen_encoded
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{(SEL==0)?1'b1:1'b0}} & IN[C_DATAOUT_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{(SEL==i)?1'b1:1'b0}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end else begin : gen_onehot
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{SEL_ONEHOT[0]}} & IN[C_DATAOUT_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_hot
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{SEL_ONEHOT[i]}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end
endgenerate
assign OUT = carry[C_DATAOUT_WIDTH*C_RATIO-1:
C_DATAOUT_WIDTH*(C_RATIO-1)];
endmodule
|
module write_burst_control (
clk,
reset,
sw_reset,
sw_stop,
length,
eop_enabled,
eop,
ready,
valid,
early_termination,
address_in,
write_in,
max_burst_count,
write_fifo_used,
waitrequest,
short_first_access_enable,
short_last_access_enable,
short_first_and_last_access_enable,
address_out,
write_out,
burst_count,
stall,
reset_taken,
stopped
);
parameter BURST_ENABLE = 1; // set to 0 to hardwire the address and write signals straight out
parameter BURST_COUNT_WIDTH = 3;
parameter WORD_SIZE = 4;
parameter WORD_SIZE_LOG2 = 2;
parameter ADDRESS_WIDTH = 32;
parameter LENGTH_WIDTH = 32;
parameter WRITE_FIFO_USED_WIDTH = 5;
parameter BURST_WRAPPING_SUPPORT = 1; // set 1 for on, set 0 for off. This parameter can't be enabled when the master supports programmable bursting.
localparam BURST_OFFSET_WIDTH = (BURST_COUNT_WIDTH == 1)? 1: (BURST_COUNT_WIDTH-1);
input clk;
input reset;
input sw_reset;
input sw_stop;
input [LENGTH_WIDTH-1:0] length;
input eop_enabled;
input eop;
input ready;
input valid;
input early_termination;
input [ADDRESS_WIDTH-1:0] address_in;
input write_in;
input [BURST_COUNT_WIDTH-1:0] max_burst_count; // will be either a hardcoded input or programmable
input [WRITE_FIFO_USED_WIDTH:0] write_fifo_used; // using the fifo full MSB as well
input waitrequest; // this needs to be the waitrequest from the fabric and not the byte enable generator since partial transfers count as burst beats
input short_first_access_enable;
input short_last_access_enable;
input short_first_and_last_access_enable;
output wire [ADDRESS_WIDTH-1:0] address_out;
output wire write_out;
output wire [BURST_COUNT_WIDTH-1:0] burst_count;
output wire stall; // need to issue a stall if there isn't enough data buffered to start a burst
output wire reset_taken; // if a reset occurs in the middle of a burst larger than 1 then the write master needs to know that the burst hasn't completed yet
output wire stopped; // if a stop occurs in the middle of a burst larger than 1 then the write master needs to know that the burst hasn't completed yet
reg [ADDRESS_WIDTH-1:0] address_d1;
reg [BURST_COUNT_WIDTH-1:0] burst_counter; // interal statemachine register
wire idle_state;
wire decrement_burst_counter;
wire ready_during_idle_state; // when there is enough data buffered to start up the burst counter state machine again
wire ready_for_quick_burst; // when there is enough data bufferred to start another burst immediately
wire burst_begin_from_idle_state;
wire burst_begin_quickly; // start another burst immediately after the previous burst completes
wire burst_begin;
wire burst_of_one_enable; // asserted when partial word accesses are occuring or the last early termination word is being written out
wire [BURST_COUNT_WIDTH-1:0] short_length_burst;
wire [BURST_COUNT_WIDTH-1:0] short_packet_burst;
wire short_length_burst_enable;
wire short_early_termination_burst_enable;
wire short_packet_burst_enable;
wire [3:0] mux_select;
reg [BURST_COUNT_WIDTH-1:0] internal_burst_count;
reg [BURST_COUNT_WIDTH-1:0] internal_burst_count_d1;
reg packet_complete;
wire [BURST_OFFSET_WIDTH-1:0] burst_offset;
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
packet_complete <= 0;
end
else
begin
if ((packet_complete == 1) & (write_fifo_used == 0))
begin
packet_complete <= 0;
end
else if ((eop == 1) & (ready == 1) & (valid == 1))
begin
packet_complete <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
address_d1 <= 0;
end
else if (burst_begin == 1)
begin
address_d1 <= (burst_begin_quickly == 1)? (address_in + WORD_SIZE) : address_in;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
burst_counter <= 0;
end
else
if ((burst_begin == 1) & (sw_reset == 0) & (sw_stop == 0)) // for reset and stop we need to let the burst complete so the fabric doesn't lock up
begin
burst_counter <= internal_burst_count;
end
else if (decrement_burst_counter == 1)
begin
burst_counter <= burst_counter - 1'b1;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
internal_burst_count_d1 <= 0;
end
else if (burst_begin == 1)
begin
internal_burst_count_d1 <= internal_burst_count;
end
end
// state machine status and control
assign idle_state = (burst_counter == 0); // any time idle_state is set then there is no burst underway
assign decrement_burst_counter = (idle_state == 0) & (waitrequest == 0);
// control for all the various cases that a burst of one beat needs to be posted
assign burst_offset = address_in[BURST_OFFSET_WIDTH+WORD_SIZE_LOG2-1:WORD_SIZE_LOG2];
assign burst_of_one_enable = (short_first_access_enable == 1) | (short_last_access_enable == 1) | (short_first_and_last_access_enable == 1) | (early_termination == 1) |
((BURST_WRAPPING_SUPPORT == 1) & (idle_state == 1) & (burst_offset != 0)) | // need to make sure bursts start on burst boundaries
((BURST_WRAPPING_SUPPORT == 1) & (idle_state == 0) & (burst_offset != (max_burst_count - 1))); // need to make sure bursts start on burst boundaries
assign short_length_burst_enable = ((length >> WORD_SIZE_LOG2) < max_burst_count) & (eop_enabled == 0) & (burst_of_one_enable == 0);
assign short_early_termination_burst_enable = ((length >> WORD_SIZE_LOG2) < max_burst_count) & (eop_enabled == 1) & (burst_of_one_enable == 0); // trim back the burst count regardless if there is enough data buffered for a full burst
assign short_packet_burst_enable = (short_early_termination_burst_enable == 0) & (eop_enabled == 1) & (packet_complete == 1) & (write_fifo_used < max_burst_count) & (burst_of_one_enable == 0);
// various burst amounts that are not the max burst count or 1 that feed the internal_burst_count mux. short_length_burst is used when short_length_burst_enable or short_early_termination_burst_enable is asserted.
assign short_length_burst = (length >> WORD_SIZE_LOG2) & {(BURST_COUNT_WIDTH-1){1'b1}};
assign short_packet_burst = (write_fifo_used & {(BURST_COUNT_WIDTH-1){1'b1}});
// since the write master may not have enough data buffered in the FIFO to start a burst the FIFO fill level must be checked before starting another burst
assign ready_during_idle_state = (burst_of_one_enable == 1) | // burst of one is only enabled when there is data in the write fifo so write_fifo_used doesn't need to be checked in this case
((write_fifo_used >= short_length_burst) & (short_length_burst_enable == 1)) |
((write_fifo_used >= short_length_burst) & (short_early_termination_burst_enable == 1)) |
((write_fifo_used >= short_packet_burst) & (short_packet_burst_enable == 1)) |
(write_fifo_used >= max_burst_count);
// same as ready_during_idle_state only we need to make sure there is more data in the fifo than the burst being posted (since the FIFO is in the middle of being popped)
assign ready_for_quick_burst = (length >= (max_burst_count << WORD_SIZE_LOG2)) & (burst_of_one_enable == 0) & // address and length lags by one clock cycle so this will let the state machine catch up
( ((write_fifo_used > short_length_burst) & (short_length_burst_enable == 1)) |
((write_fifo_used > short_length_burst) & (short_early_termination_burst_enable == 1)) |
((write_fifo_used > short_packet_burst) & (short_packet_burst_enable == 1)) |
(write_fifo_used > max_burst_count) );
// burst begin signals used to start up the burst counter state machine
assign burst_begin_from_idle_state = (write_in == 1) & (idle_state == 1) & (ready_during_idle_state == 1); // start the state machine up again
assign burst_begin_quickly = (write_in == 1) & (burst_counter == 1) & (waitrequest == 0) & (ready_for_quick_burst == 1); // enough data is buffered to start another burst immediately after the current burst
assign burst_begin = (burst_begin_quickly == 1) | (burst_begin_from_idle_state == 1);
assign mux_select = {short_packet_burst_enable, short_early_termination_burst_enable, short_length_burst_enable, burst_of_one_enable};
// one-hot mux that selects the appropriate burst count to present to the fabric
always @ (short_length_burst or short_packet_burst or max_burst_count or mux_select)
begin
case (mux_select)
4'b0001 : internal_burst_count = 1;
4'b0010 : internal_burst_count = short_length_burst;
4'b0100 : internal_burst_count = short_length_burst;
4'b1000 : internal_burst_count = short_packet_burst;
default : internal_burst_count = max_burst_count;
endcase
end
generate
if (BURST_ENABLE == 1)
begin
// outputs that need to be held constant throughout the entire burst transaction
assign address_out = address_d1;
assign burst_count = internal_burst_count_d1;
assign write_out = (idle_state == 0);
assign stall = (idle_state == 1);
assign reset_taken = (sw_reset == 1) & (idle_state == 1); // for bursts of 1 the write master logic will handle the correct reset timing
assign stopped = (sw_stop == 1) & (idle_state == 1); // for bursts of 1 the write master logic will handle the correct stop timing
end
else
begin
assign address_out = address_in;
assign burst_count = 1; // this will be stubbed at the top level
assign write_out = write_in;
assign stall = 0;
assign reset_taken = sw_reset;
assign stopped = sw_stop;
end
endgenerate
endmodule
|
module write_burst_control (
clk,
reset,
sw_reset,
sw_stop,
length,
eop_enabled,
eop,
ready,
valid,
early_termination,
address_in,
write_in,
max_burst_count,
write_fifo_used,
waitrequest,
short_first_access_enable,
short_last_access_enable,
short_first_and_last_access_enable,
address_out,
write_out,
burst_count,
stall,
reset_taken,
stopped
);
parameter BURST_ENABLE = 1; // set to 0 to hardwire the address and write signals straight out
parameter BURST_COUNT_WIDTH = 3;
parameter WORD_SIZE = 4;
parameter WORD_SIZE_LOG2 = 2;
parameter ADDRESS_WIDTH = 32;
parameter LENGTH_WIDTH = 32;
parameter WRITE_FIFO_USED_WIDTH = 5;
parameter BURST_WRAPPING_SUPPORT = 1; // set 1 for on, set 0 for off. This parameter can't be enabled when the master supports programmable bursting.
localparam BURST_OFFSET_WIDTH = (BURST_COUNT_WIDTH == 1)? 1: (BURST_COUNT_WIDTH-1);
input clk;
input reset;
input sw_reset;
input sw_stop;
input [LENGTH_WIDTH-1:0] length;
input eop_enabled;
input eop;
input ready;
input valid;
input early_termination;
input [ADDRESS_WIDTH-1:0] address_in;
input write_in;
input [BURST_COUNT_WIDTH-1:0] max_burst_count; // will be either a hardcoded input or programmable
input [WRITE_FIFO_USED_WIDTH:0] write_fifo_used; // using the fifo full MSB as well
input waitrequest; // this needs to be the waitrequest from the fabric and not the byte enable generator since partial transfers count as burst beats
input short_first_access_enable;
input short_last_access_enable;
input short_first_and_last_access_enable;
output wire [ADDRESS_WIDTH-1:0] address_out;
output wire write_out;
output wire [BURST_COUNT_WIDTH-1:0] burst_count;
output wire stall; // need to issue a stall if there isn't enough data buffered to start a burst
output wire reset_taken; // if a reset occurs in the middle of a burst larger than 1 then the write master needs to know that the burst hasn't completed yet
output wire stopped; // if a stop occurs in the middle of a burst larger than 1 then the write master needs to know that the burst hasn't completed yet
reg [ADDRESS_WIDTH-1:0] address_d1;
reg [BURST_COUNT_WIDTH-1:0] burst_counter; // interal statemachine register
wire idle_state;
wire decrement_burst_counter;
wire ready_during_idle_state; // when there is enough data buffered to start up the burst counter state machine again
wire ready_for_quick_burst; // when there is enough data bufferred to start another burst immediately
wire burst_begin_from_idle_state;
wire burst_begin_quickly; // start another burst immediately after the previous burst completes
wire burst_begin;
wire burst_of_one_enable; // asserted when partial word accesses are occuring or the last early termination word is being written out
wire [BURST_COUNT_WIDTH-1:0] short_length_burst;
wire [BURST_COUNT_WIDTH-1:0] short_packet_burst;
wire short_length_burst_enable;
wire short_early_termination_burst_enable;
wire short_packet_burst_enable;
wire [3:0] mux_select;
reg [BURST_COUNT_WIDTH-1:0] internal_burst_count;
reg [BURST_COUNT_WIDTH-1:0] internal_burst_count_d1;
reg packet_complete;
wire [BURST_OFFSET_WIDTH-1:0] burst_offset;
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
packet_complete <= 0;
end
else
begin
if ((packet_complete == 1) & (write_fifo_used == 0))
begin
packet_complete <= 0;
end
else if ((eop == 1) & (ready == 1) & (valid == 1))
begin
packet_complete <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
address_d1 <= 0;
end
else if (burst_begin == 1)
begin
address_d1 <= (burst_begin_quickly == 1)? (address_in + WORD_SIZE) : address_in;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
burst_counter <= 0;
end
else
if ((burst_begin == 1) & (sw_reset == 0) & (sw_stop == 0)) // for reset and stop we need to let the burst complete so the fabric doesn't lock up
begin
burst_counter <= internal_burst_count;
end
else if (decrement_burst_counter == 1)
begin
burst_counter <= burst_counter - 1'b1;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
internal_burst_count_d1 <= 0;
end
else if (burst_begin == 1)
begin
internal_burst_count_d1 <= internal_burst_count;
end
end
// state machine status and control
assign idle_state = (burst_counter == 0); // any time idle_state is set then there is no burst underway
assign decrement_burst_counter = (idle_state == 0) & (waitrequest == 0);
// control for all the various cases that a burst of one beat needs to be posted
assign burst_offset = address_in[BURST_OFFSET_WIDTH+WORD_SIZE_LOG2-1:WORD_SIZE_LOG2];
assign burst_of_one_enable = (short_first_access_enable == 1) | (short_last_access_enable == 1) | (short_first_and_last_access_enable == 1) | (early_termination == 1) |
((BURST_WRAPPING_SUPPORT == 1) & (idle_state == 1) & (burst_offset != 0)) | // need to make sure bursts start on burst boundaries
((BURST_WRAPPING_SUPPORT == 1) & (idle_state == 0) & (burst_offset != (max_burst_count - 1))); // need to make sure bursts start on burst boundaries
assign short_length_burst_enable = ((length >> WORD_SIZE_LOG2) < max_burst_count) & (eop_enabled == 0) & (burst_of_one_enable == 0);
assign short_early_termination_burst_enable = ((length >> WORD_SIZE_LOG2) < max_burst_count) & (eop_enabled == 1) & (burst_of_one_enable == 0); // trim back the burst count regardless if there is enough data buffered for a full burst
assign short_packet_burst_enable = (short_early_termination_burst_enable == 0) & (eop_enabled == 1) & (packet_complete == 1) & (write_fifo_used < max_burst_count) & (burst_of_one_enable == 0);
// various burst amounts that are not the max burst count or 1 that feed the internal_burst_count mux. short_length_burst is used when short_length_burst_enable or short_early_termination_burst_enable is asserted.
assign short_length_burst = (length >> WORD_SIZE_LOG2) & {(BURST_COUNT_WIDTH-1){1'b1}};
assign short_packet_burst = (write_fifo_used & {(BURST_COUNT_WIDTH-1){1'b1}});
// since the write master may not have enough data buffered in the FIFO to start a burst the FIFO fill level must be checked before starting another burst
assign ready_during_idle_state = (burst_of_one_enable == 1) | // burst of one is only enabled when there is data in the write fifo so write_fifo_used doesn't need to be checked in this case
((write_fifo_used >= short_length_burst) & (short_length_burst_enable == 1)) |
((write_fifo_used >= short_length_burst) & (short_early_termination_burst_enable == 1)) |
((write_fifo_used >= short_packet_burst) & (short_packet_burst_enable == 1)) |
(write_fifo_used >= max_burst_count);
// same as ready_during_idle_state only we need to make sure there is more data in the fifo than the burst being posted (since the FIFO is in the middle of being popped)
assign ready_for_quick_burst = (length >= (max_burst_count << WORD_SIZE_LOG2)) & (burst_of_one_enable == 0) & // address and length lags by one clock cycle so this will let the state machine catch up
( ((write_fifo_used > short_length_burst) & (short_length_burst_enable == 1)) |
((write_fifo_used > short_length_burst) & (short_early_termination_burst_enable == 1)) |
((write_fifo_used > short_packet_burst) & (short_packet_burst_enable == 1)) |
(write_fifo_used > max_burst_count) );
// burst begin signals used to start up the burst counter state machine
assign burst_begin_from_idle_state = (write_in == 1) & (idle_state == 1) & (ready_during_idle_state == 1); // start the state machine up again
assign burst_begin_quickly = (write_in == 1) & (burst_counter == 1) & (waitrequest == 0) & (ready_for_quick_burst == 1); // enough data is buffered to start another burst immediately after the current burst
assign burst_begin = (burst_begin_quickly == 1) | (burst_begin_from_idle_state == 1);
assign mux_select = {short_packet_burst_enable, short_early_termination_burst_enable, short_length_burst_enable, burst_of_one_enable};
// one-hot mux that selects the appropriate burst count to present to the fabric
always @ (short_length_burst or short_packet_burst or max_burst_count or mux_select)
begin
case (mux_select)
4'b0001 : internal_burst_count = 1;
4'b0010 : internal_burst_count = short_length_burst;
4'b0100 : internal_burst_count = short_length_burst;
4'b1000 : internal_burst_count = short_packet_burst;
default : internal_burst_count = max_burst_count;
endcase
end
generate
if (BURST_ENABLE == 1)
begin
// outputs that need to be held constant throughout the entire burst transaction
assign address_out = address_d1;
assign burst_count = internal_burst_count_d1;
assign write_out = (idle_state == 0);
assign stall = (idle_state == 1);
assign reset_taken = (sw_reset == 1) & (idle_state == 1); // for bursts of 1 the write master logic will handle the correct reset timing
assign stopped = (sw_stop == 1) & (idle_state == 1); // for bursts of 1 the write master logic will handle the correct stop timing
end
else
begin
assign address_out = address_in;
assign burst_count = 1; // this will be stubbed at the top level
assign write_out = write_in;
assign stall = 0;
assign reset_taken = sw_reset;
assign stopped = sw_stop;
end
endgenerate
endmodule
|
module write_burst_control (
clk,
reset,
sw_reset,
sw_stop,
length,
eop_enabled,
eop,
ready,
valid,
early_termination,
address_in,
write_in,
max_burst_count,
write_fifo_used,
waitrequest,
short_first_access_enable,
short_last_access_enable,
short_first_and_last_access_enable,
address_out,
write_out,
burst_count,
stall,
reset_taken,
stopped
);
parameter BURST_ENABLE = 1; // set to 0 to hardwire the address and write signals straight out
parameter BURST_COUNT_WIDTH = 3;
parameter WORD_SIZE = 4;
parameter WORD_SIZE_LOG2 = 2;
parameter ADDRESS_WIDTH = 32;
parameter LENGTH_WIDTH = 32;
parameter WRITE_FIFO_USED_WIDTH = 5;
parameter BURST_WRAPPING_SUPPORT = 1; // set 1 for on, set 0 for off. This parameter can't be enabled when the master supports programmable bursting.
localparam BURST_OFFSET_WIDTH = (BURST_COUNT_WIDTH == 1)? 1: (BURST_COUNT_WIDTH-1);
input clk;
input reset;
input sw_reset;
input sw_stop;
input [LENGTH_WIDTH-1:0] length;
input eop_enabled;
input eop;
input ready;
input valid;
input early_termination;
input [ADDRESS_WIDTH-1:0] address_in;
input write_in;
input [BURST_COUNT_WIDTH-1:0] max_burst_count; // will be either a hardcoded input or programmable
input [WRITE_FIFO_USED_WIDTH:0] write_fifo_used; // using the fifo full MSB as well
input waitrequest; // this needs to be the waitrequest from the fabric and not the byte enable generator since partial transfers count as burst beats
input short_first_access_enable;
input short_last_access_enable;
input short_first_and_last_access_enable;
output wire [ADDRESS_WIDTH-1:0] address_out;
output wire write_out;
output wire [BURST_COUNT_WIDTH-1:0] burst_count;
output wire stall; // need to issue a stall if there isn't enough data buffered to start a burst
output wire reset_taken; // if a reset occurs in the middle of a burst larger than 1 then the write master needs to know that the burst hasn't completed yet
output wire stopped; // if a stop occurs in the middle of a burst larger than 1 then the write master needs to know that the burst hasn't completed yet
reg [ADDRESS_WIDTH-1:0] address_d1;
reg [BURST_COUNT_WIDTH-1:0] burst_counter; // interal statemachine register
wire idle_state;
wire decrement_burst_counter;
wire ready_during_idle_state; // when there is enough data buffered to start up the burst counter state machine again
wire ready_for_quick_burst; // when there is enough data bufferred to start another burst immediately
wire burst_begin_from_idle_state;
wire burst_begin_quickly; // start another burst immediately after the previous burst completes
wire burst_begin;
wire burst_of_one_enable; // asserted when partial word accesses are occuring or the last early termination word is being written out
wire [BURST_COUNT_WIDTH-1:0] short_length_burst;
wire [BURST_COUNT_WIDTH-1:0] short_packet_burst;
wire short_length_burst_enable;
wire short_early_termination_burst_enable;
wire short_packet_burst_enable;
wire [3:0] mux_select;
reg [BURST_COUNT_WIDTH-1:0] internal_burst_count;
reg [BURST_COUNT_WIDTH-1:0] internal_burst_count_d1;
reg packet_complete;
wire [BURST_OFFSET_WIDTH-1:0] burst_offset;
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
packet_complete <= 0;
end
else
begin
if ((packet_complete == 1) & (write_fifo_used == 0))
begin
packet_complete <= 0;
end
else if ((eop == 1) & (ready == 1) & (valid == 1))
begin
packet_complete <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
address_d1 <= 0;
end
else if (burst_begin == 1)
begin
address_d1 <= (burst_begin_quickly == 1)? (address_in + WORD_SIZE) : address_in;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
burst_counter <= 0;
end
else
if ((burst_begin == 1) & (sw_reset == 0) & (sw_stop == 0)) // for reset and stop we need to let the burst complete so the fabric doesn't lock up
begin
burst_counter <= internal_burst_count;
end
else if (decrement_burst_counter == 1)
begin
burst_counter <= burst_counter - 1'b1;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
internal_burst_count_d1 <= 0;
end
else if (burst_begin == 1)
begin
internal_burst_count_d1 <= internal_burst_count;
end
end
// state machine status and control
assign idle_state = (burst_counter == 0); // any time idle_state is set then there is no burst underway
assign decrement_burst_counter = (idle_state == 0) & (waitrequest == 0);
// control for all the various cases that a burst of one beat needs to be posted
assign burst_offset = address_in[BURST_OFFSET_WIDTH+WORD_SIZE_LOG2-1:WORD_SIZE_LOG2];
assign burst_of_one_enable = (short_first_access_enable == 1) | (short_last_access_enable == 1) | (short_first_and_last_access_enable == 1) | (early_termination == 1) |
((BURST_WRAPPING_SUPPORT == 1) & (idle_state == 1) & (burst_offset != 0)) | // need to make sure bursts start on burst boundaries
((BURST_WRAPPING_SUPPORT == 1) & (idle_state == 0) & (burst_offset != (max_burst_count - 1))); // need to make sure bursts start on burst boundaries
assign short_length_burst_enable = ((length >> WORD_SIZE_LOG2) < max_burst_count) & (eop_enabled == 0) & (burst_of_one_enable == 0);
assign short_early_termination_burst_enable = ((length >> WORD_SIZE_LOG2) < max_burst_count) & (eop_enabled == 1) & (burst_of_one_enable == 0); // trim back the burst count regardless if there is enough data buffered for a full burst
assign short_packet_burst_enable = (short_early_termination_burst_enable == 0) & (eop_enabled == 1) & (packet_complete == 1) & (write_fifo_used < max_burst_count) & (burst_of_one_enable == 0);
// various burst amounts that are not the max burst count or 1 that feed the internal_burst_count mux. short_length_burst is used when short_length_burst_enable or short_early_termination_burst_enable is asserted.
assign short_length_burst = (length >> WORD_SIZE_LOG2) & {(BURST_COUNT_WIDTH-1){1'b1}};
assign short_packet_burst = (write_fifo_used & {(BURST_COUNT_WIDTH-1){1'b1}});
// since the write master may not have enough data buffered in the FIFO to start a burst the FIFO fill level must be checked before starting another burst
assign ready_during_idle_state = (burst_of_one_enable == 1) | // burst of one is only enabled when there is data in the write fifo so write_fifo_used doesn't need to be checked in this case
((write_fifo_used >= short_length_burst) & (short_length_burst_enable == 1)) |
((write_fifo_used >= short_length_burst) & (short_early_termination_burst_enable == 1)) |
((write_fifo_used >= short_packet_burst) & (short_packet_burst_enable == 1)) |
(write_fifo_used >= max_burst_count);
// same as ready_during_idle_state only we need to make sure there is more data in the fifo than the burst being posted (since the FIFO is in the middle of being popped)
assign ready_for_quick_burst = (length >= (max_burst_count << WORD_SIZE_LOG2)) & (burst_of_one_enable == 0) & // address and length lags by one clock cycle so this will let the state machine catch up
( ((write_fifo_used > short_length_burst) & (short_length_burst_enable == 1)) |
((write_fifo_used > short_length_burst) & (short_early_termination_burst_enable == 1)) |
((write_fifo_used > short_packet_burst) & (short_packet_burst_enable == 1)) |
(write_fifo_used > max_burst_count) );
// burst begin signals used to start up the burst counter state machine
assign burst_begin_from_idle_state = (write_in == 1) & (idle_state == 1) & (ready_during_idle_state == 1); // start the state machine up again
assign burst_begin_quickly = (write_in == 1) & (burst_counter == 1) & (waitrequest == 0) & (ready_for_quick_burst == 1); // enough data is buffered to start another burst immediately after the current burst
assign burst_begin = (burst_begin_quickly == 1) | (burst_begin_from_idle_state == 1);
assign mux_select = {short_packet_burst_enable, short_early_termination_burst_enable, short_length_burst_enable, burst_of_one_enable};
// one-hot mux that selects the appropriate burst count to present to the fabric
always @ (short_length_burst or short_packet_burst or max_burst_count or mux_select)
begin
case (mux_select)
4'b0001 : internal_burst_count = 1;
4'b0010 : internal_burst_count = short_length_burst;
4'b0100 : internal_burst_count = short_length_burst;
4'b1000 : internal_burst_count = short_packet_burst;
default : internal_burst_count = max_burst_count;
endcase
end
generate
if (BURST_ENABLE == 1)
begin
// outputs that need to be held constant throughout the entire burst transaction
assign address_out = address_d1;
assign burst_count = internal_burst_count_d1;
assign write_out = (idle_state == 0);
assign stall = (idle_state == 1);
assign reset_taken = (sw_reset == 1) & (idle_state == 1); // for bursts of 1 the write master logic will handle the correct reset timing
assign stopped = (sw_stop == 1) & (idle_state == 1); // for bursts of 1 the write master logic will handle the correct stop timing
end
else
begin
assign address_out = address_in;
assign burst_count = 1; // this will be stubbed at the top level
assign write_out = write_in;
assign stall = 0;
assign reset_taken = sw_reset;
assign stopped = sw_stop;
end
endgenerate
endmodule
|
module mem_window (
clk,
reset,
// Memory slave port
s1_address,
s1_read,
s1_readdata,
s1_readdatavalid,
s1_write,
s1_writedata,
s1_burstcount,
s1_byteenable,
s1_waitrequest,
// Configuration register slave port
cra_write,
cra_writedata,
cra_byteenable,
// Bridged master port to memory
m1_address,
m1_read,
m1_readdata,
m1_readdatavalid,
m1_write,
m1_writedata,
m1_burstcount,
m1_byteenable,
m1_waitrequest
);
parameter PAGE_ADDRESS_WIDTH = 20;
parameter MEM_ADDRESS_WIDTH = 32;
parameter NUM_BYTES = 32;
parameter BURSTCOUNT_WIDTH = 1;
parameter CRA_BITWIDTH = 32;
localparam ADDRESS_SHIFT = $clog2(NUM_BYTES);
localparam PAGE_ID_WIDTH = MEM_ADDRESS_WIDTH - PAGE_ADDRESS_WIDTH - ADDRESS_SHIFT;
localparam DATA_WIDTH = NUM_BYTES * 8;
input clk;
input reset;
// Memory slave port
input [PAGE_ADDRESS_WIDTH-1:0] s1_address;
input s1_read;
output [DATA_WIDTH-1:0] s1_readdata;
output s1_readdatavalid;
input s1_write;
input [DATA_WIDTH-1:0] s1_writedata;
input [BURSTCOUNT_WIDTH-1:0] s1_burstcount;
input [NUM_BYTES-1:0] s1_byteenable;
output s1_waitrequest;
// Bridged master port to memory
output [MEM_ADDRESS_WIDTH-1:0] m1_address;
output m1_read;
input [DATA_WIDTH-1:0] m1_readdata;
input m1_readdatavalid;
output m1_write;
output [DATA_WIDTH-1:0] m1_writedata;
output [BURSTCOUNT_WIDTH-1:0] m1_burstcount;
output [NUM_BYTES-1:0] m1_byteenable;
input m1_waitrequest;
// CRA slave
input cra_write;
input [CRA_BITWIDTH-1:0] cra_writedata;
input [CRA_BITWIDTH/8-1:0] cra_byteenable;
// Architecture
// CRA slave allows the master to change the active page
reg [PAGE_ID_WIDTH-1:0] page_id;
reg [CRA_BITWIDTH-1:0] cra_writemask;
integer i;
always@*
for (i=0; i<CRA_BITWIDTH; i=i+1)
cra_writemask[i] = cra_byteenable[i/8] & cra_write;
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
page_id <= {PAGE_ID_WIDTH{1'b0}};
else
page_id <= (cra_writedata & cra_writemask) | (page_id & ~cra_writemask);
end
// The s1 port bridges to the m1 port - with the page ID tacked on to the address
assign m1_address = {page_id, s1_address, {ADDRESS_SHIFT{1'b0}}};
assign m1_read = s1_read;
assign s1_readdata = m1_readdata;
assign s1_readdatavalid = m1_readdatavalid;
assign m1_write = s1_write;
assign m1_writedata = s1_writedata;
assign m1_burstcount = s1_burstcount;
assign m1_byteenable = s1_byteenable;
assign s1_waitrequest = m1_waitrequest;
endmodule
|
module mem_window (
clk,
reset,
// Memory slave port
s1_address,
s1_read,
s1_readdata,
s1_readdatavalid,
s1_write,
s1_writedata,
s1_burstcount,
s1_byteenable,
s1_waitrequest,
// Configuration register slave port
cra_write,
cra_writedata,
cra_byteenable,
// Bridged master port to memory
m1_address,
m1_read,
m1_readdata,
m1_readdatavalid,
m1_write,
m1_writedata,
m1_burstcount,
m1_byteenable,
m1_waitrequest
);
parameter PAGE_ADDRESS_WIDTH = 20;
parameter MEM_ADDRESS_WIDTH = 32;
parameter NUM_BYTES = 32;
parameter BURSTCOUNT_WIDTH = 1;
parameter CRA_BITWIDTH = 32;
localparam ADDRESS_SHIFT = $clog2(NUM_BYTES);
localparam PAGE_ID_WIDTH = MEM_ADDRESS_WIDTH - PAGE_ADDRESS_WIDTH - ADDRESS_SHIFT;
localparam DATA_WIDTH = NUM_BYTES * 8;
input clk;
input reset;
// Memory slave port
input [PAGE_ADDRESS_WIDTH-1:0] s1_address;
input s1_read;
output [DATA_WIDTH-1:0] s1_readdata;
output s1_readdatavalid;
input s1_write;
input [DATA_WIDTH-1:0] s1_writedata;
input [BURSTCOUNT_WIDTH-1:0] s1_burstcount;
input [NUM_BYTES-1:0] s1_byteenable;
output s1_waitrequest;
// Bridged master port to memory
output [MEM_ADDRESS_WIDTH-1:0] m1_address;
output m1_read;
input [DATA_WIDTH-1:0] m1_readdata;
input m1_readdatavalid;
output m1_write;
output [DATA_WIDTH-1:0] m1_writedata;
output [BURSTCOUNT_WIDTH-1:0] m1_burstcount;
output [NUM_BYTES-1:0] m1_byteenable;
input m1_waitrequest;
// CRA slave
input cra_write;
input [CRA_BITWIDTH-1:0] cra_writedata;
input [CRA_BITWIDTH/8-1:0] cra_byteenable;
// Architecture
// CRA slave allows the master to change the active page
reg [PAGE_ID_WIDTH-1:0] page_id;
reg [CRA_BITWIDTH-1:0] cra_writemask;
integer i;
always@*
for (i=0; i<CRA_BITWIDTH; i=i+1)
cra_writemask[i] = cra_byteenable[i/8] & cra_write;
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
page_id <= {PAGE_ID_WIDTH{1'b0}};
else
page_id <= (cra_writedata & cra_writemask) | (page_id & ~cra_writemask);
end
// The s1 port bridges to the m1 port - with the page ID tacked on to the address
assign m1_address = {page_id, s1_address, {ADDRESS_SHIFT{1'b0}}};
assign m1_read = s1_read;
assign s1_readdata = m1_readdata;
assign s1_readdatavalid = m1_readdatavalid;
assign m1_write = s1_write;
assign m1_writedata = s1_writedata;
assign m1_burstcount = s1_burstcount;
assign m1_byteenable = s1_byteenable;
assign s1_waitrequest = m1_waitrequest;
endmodule
|
module export_master (
clk,
reset,
address,
read,
readdata,
readdatavalid,
write,
writedata,
burstcount,
byteenable,
waitrequest,
burstbegin,
export_address,
export_read,
export_readdata,
export_readdatavalid,
export_write,
export_writedata,
export_burstcount,
export_burstbegin,
export_byteenable,
export_waitrequest,
interrupt,
export_interrupt
);
parameter NUM_BYTES = 4;
parameter BYTE_ADDRESS_WIDTH = 32;
parameter WORD_ADDRESS_WIDTH = 32;
parameter BURSTCOUNT_WIDTH = 1;
localparam DATA_WIDTH = NUM_BYTES * 8;
localparam ADDRESS_SHIFT = BYTE_ADDRESS_WIDTH - WORD_ADDRESS_WIDTH;
input clk;
input reset;
input [WORD_ADDRESS_WIDTH-1:0] address;
input read;
output [DATA_WIDTH-1:0] readdata;
output readdatavalid;
input write;
input [DATA_WIDTH-1:0] writedata;
input [BURSTCOUNT_WIDTH-1:0] burstcount;
input burstbegin;
input [NUM_BYTES-1:0] byteenable;
output waitrequest;
output interrupt;
output [BYTE_ADDRESS_WIDTH-1:0] export_address;
output export_read;
input [DATA_WIDTH-1:0] export_readdata;
input export_readdatavalid;
output export_write;
output [DATA_WIDTH-1:0] export_writedata;
output [BURSTCOUNT_WIDTH-1:0] export_burstcount;
output export_burstbegin;
output [NUM_BYTES-1:0] export_byteenable;
input export_waitrequest;
input export_interrupt;
assign export_address = address << ADDRESS_SHIFT;
assign export_read = read;
assign readdata = export_readdata;
assign readdatavalid = export_readdatavalid;
assign export_write = write;
assign export_writedata = writedata;
assign export_burstcount = burstcount;
assign export_burstbegin = burstbegin;
assign export_byteenable = byteenable;
assign interrupt = export_interrupt;
assign waitrequest = export_waitrequest;
endmodule
|
module export_master (
clk,
reset,
address,
read,
readdata,
readdatavalid,
write,
writedata,
burstcount,
byteenable,
waitrequest,
burstbegin,
export_address,
export_read,
export_readdata,
export_readdatavalid,
export_write,
export_writedata,
export_burstcount,
export_burstbegin,
export_byteenable,
export_waitrequest,
interrupt,
export_interrupt
);
parameter NUM_BYTES = 4;
parameter BYTE_ADDRESS_WIDTH = 32;
parameter WORD_ADDRESS_WIDTH = 32;
parameter BURSTCOUNT_WIDTH = 1;
localparam DATA_WIDTH = NUM_BYTES * 8;
localparam ADDRESS_SHIFT = BYTE_ADDRESS_WIDTH - WORD_ADDRESS_WIDTH;
input clk;
input reset;
input [WORD_ADDRESS_WIDTH-1:0] address;
input read;
output [DATA_WIDTH-1:0] readdata;
output readdatavalid;
input write;
input [DATA_WIDTH-1:0] writedata;
input [BURSTCOUNT_WIDTH-1:0] burstcount;
input burstbegin;
input [NUM_BYTES-1:0] byteenable;
output waitrequest;
output interrupt;
output [BYTE_ADDRESS_WIDTH-1:0] export_address;
output export_read;
input [DATA_WIDTH-1:0] export_readdata;
input export_readdatavalid;
output export_write;
output [DATA_WIDTH-1:0] export_writedata;
output [BURSTCOUNT_WIDTH-1:0] export_burstcount;
output export_burstbegin;
output [NUM_BYTES-1:0] export_byteenable;
input export_waitrequest;
input export_interrupt;
assign export_address = address << ADDRESS_SHIFT;
assign export_read = read;
assign readdata = export_readdata;
assign readdatavalid = export_readdatavalid;
assign export_write = write;
assign export_writedata = writedata;
assign export_burstcount = burstcount;
assign export_burstbegin = burstbegin;
assign export_byteenable = byteenable;
assign interrupt = export_interrupt;
assign waitrequest = export_waitrequest;
endmodule
|
module read_burst_control (
address,
length,
maximum_burst_count,
short_first_access_enable,
short_last_access_enable,
short_first_and_last_access_enable,
burst_count
);
parameter BURST_ENABLE = 1; // set to 0 to hardwire the address and write signals straight out
parameter BURST_COUNT_WIDTH = 3;
parameter WORD_SIZE_LOG2 = 2; // log2(DATA WIDTH/8)
parameter ADDRESS_WIDTH = 32;
parameter LENGTH_WIDTH = 32;
parameter BURST_WRAPPING_SUPPORT = 1; // set 1 for on, set 0 for off. This parameter can't be enabled when hte master supports programmable burst.
localparam BURST_OFFSET_WIDTH = (BURST_COUNT_WIDTH == 1)? 1: (BURST_COUNT_WIDTH-1);
input [ADDRESS_WIDTH-1:0] address;
input [LENGTH_WIDTH-1:0] length;
input [BURST_COUNT_WIDTH-1:0] maximum_burst_count; // will be either a hardcoded input or programmable
input short_first_access_enable;
input short_last_access_enable;
input short_first_and_last_access_enable;
output wire [BURST_COUNT_WIDTH-1:0] burst_count;
wire [BURST_COUNT_WIDTH-1:0] posted_burst; // when the burst statemachine is used this will be the burst count posted to the fabric
reg [BURST_COUNT_WIDTH-1:0] internal_burst_count; // muxes posted_burst, posted_burst_d1, and '1' since we need to be able to post bursts of '1' for short accesses
wire burst_of_one_enable; // asserted when partial word accesses are occuring
wire short_burst_enable;
wire [BURST_OFFSET_WIDTH-1:0] burst_offset;
assign burst_offset = address[BURST_OFFSET_WIDTH+WORD_SIZE_LOG2-1:WORD_SIZE_LOG2];
// for unaligned or partial transfers we must use a burst length of 1 so that
assign burst_of_one_enable = (short_first_access_enable == 1) | (short_last_access_enable == 1) | (short_first_and_last_access_enable == 1) | // when performing partial accesses use a burst length of 1
((BURST_WRAPPING_SUPPORT == 1) & (burst_offset != 0)); // when the burst boundary offset is non-zero then the master isn't in burst alignment yet as so a burst of 1 needs to be posted
assign short_burst_enable = ((length >> WORD_SIZE_LOG2) < maximum_burst_count);
always @ (maximum_burst_count or length or short_burst_enable or burst_of_one_enable)
begin
case ({short_burst_enable, burst_of_one_enable})
2'b00 : internal_burst_count = maximum_burst_count;
2'b01 : internal_burst_count = 1; // this is when the master starts unaligned
2'b10 : internal_burst_count = ((length >> WORD_SIZE_LOG2) & {(BURST_COUNT_WIDTH-1){1'b1}}); // this could be followed by a burst of 1 if there are a few bytes leftover
2'b11 : internal_burst_count = 1; // burst of 1 needs to win, this is when the master starts with very little data to transfer
endcase
end
generate
if (BURST_ENABLE == 1)
begin
assign burst_count = internal_burst_count;
end
else
begin
assign burst_count = 1; // this will be stubbed at the top level but will be used for the address and pending reads incrementing
end
endgenerate
endmodule
|
module read_burst_control (
address,
length,
maximum_burst_count,
short_first_access_enable,
short_last_access_enable,
short_first_and_last_access_enable,
burst_count
);
parameter BURST_ENABLE = 1; // set to 0 to hardwire the address and write signals straight out
parameter BURST_COUNT_WIDTH = 3;
parameter WORD_SIZE_LOG2 = 2; // log2(DATA WIDTH/8)
parameter ADDRESS_WIDTH = 32;
parameter LENGTH_WIDTH = 32;
parameter BURST_WRAPPING_SUPPORT = 1; // set 1 for on, set 0 for off. This parameter can't be enabled when hte master supports programmable burst.
localparam BURST_OFFSET_WIDTH = (BURST_COUNT_WIDTH == 1)? 1: (BURST_COUNT_WIDTH-1);
input [ADDRESS_WIDTH-1:0] address;
input [LENGTH_WIDTH-1:0] length;
input [BURST_COUNT_WIDTH-1:0] maximum_burst_count; // will be either a hardcoded input or programmable
input short_first_access_enable;
input short_last_access_enable;
input short_first_and_last_access_enable;
output wire [BURST_COUNT_WIDTH-1:0] burst_count;
wire [BURST_COUNT_WIDTH-1:0] posted_burst; // when the burst statemachine is used this will be the burst count posted to the fabric
reg [BURST_COUNT_WIDTH-1:0] internal_burst_count; // muxes posted_burst, posted_burst_d1, and '1' since we need to be able to post bursts of '1' for short accesses
wire burst_of_one_enable; // asserted when partial word accesses are occuring
wire short_burst_enable;
wire [BURST_OFFSET_WIDTH-1:0] burst_offset;
assign burst_offset = address[BURST_OFFSET_WIDTH+WORD_SIZE_LOG2-1:WORD_SIZE_LOG2];
// for unaligned or partial transfers we must use a burst length of 1 so that
assign burst_of_one_enable = (short_first_access_enable == 1) | (short_last_access_enable == 1) | (short_first_and_last_access_enable == 1) | // when performing partial accesses use a burst length of 1
((BURST_WRAPPING_SUPPORT == 1) & (burst_offset != 0)); // when the burst boundary offset is non-zero then the master isn't in burst alignment yet as so a burst of 1 needs to be posted
assign short_burst_enable = ((length >> WORD_SIZE_LOG2) < maximum_burst_count);
always @ (maximum_burst_count or length or short_burst_enable or burst_of_one_enable)
begin
case ({short_burst_enable, burst_of_one_enable})
2'b00 : internal_burst_count = maximum_burst_count;
2'b01 : internal_burst_count = 1; // this is when the master starts unaligned
2'b10 : internal_burst_count = ((length >> WORD_SIZE_LOG2) & {(BURST_COUNT_WIDTH-1){1'b1}}); // this could be followed by a burst of 1 if there are a few bytes leftover
2'b11 : internal_burst_count = 1; // burst of 1 needs to win, this is when the master starts with very little data to transfer
endcase
end
generate
if (BURST_ENABLE == 1)
begin
assign burst_count = internal_burst_count;
end
else
begin
assign burst_count = 1; // this will be stubbed at the top level but will be used for the address and pending reads incrementing
end
endgenerate
endmodule
|
module read_burst_control (
address,
length,
maximum_burst_count,
short_first_access_enable,
short_last_access_enable,
short_first_and_last_access_enable,
burst_count
);
parameter BURST_ENABLE = 1; // set to 0 to hardwire the address and write signals straight out
parameter BURST_COUNT_WIDTH = 3;
parameter WORD_SIZE_LOG2 = 2; // log2(DATA WIDTH/8)
parameter ADDRESS_WIDTH = 32;
parameter LENGTH_WIDTH = 32;
parameter BURST_WRAPPING_SUPPORT = 1; // set 1 for on, set 0 for off. This parameter can't be enabled when hte master supports programmable burst.
localparam BURST_OFFSET_WIDTH = (BURST_COUNT_WIDTH == 1)? 1: (BURST_COUNT_WIDTH-1);
input [ADDRESS_WIDTH-1:0] address;
input [LENGTH_WIDTH-1:0] length;
input [BURST_COUNT_WIDTH-1:0] maximum_burst_count; // will be either a hardcoded input or programmable
input short_first_access_enable;
input short_last_access_enable;
input short_first_and_last_access_enable;
output wire [BURST_COUNT_WIDTH-1:0] burst_count;
wire [BURST_COUNT_WIDTH-1:0] posted_burst; // when the burst statemachine is used this will be the burst count posted to the fabric
reg [BURST_COUNT_WIDTH-1:0] internal_burst_count; // muxes posted_burst, posted_burst_d1, and '1' since we need to be able to post bursts of '1' for short accesses
wire burst_of_one_enable; // asserted when partial word accesses are occuring
wire short_burst_enable;
wire [BURST_OFFSET_WIDTH-1:0] burst_offset;
assign burst_offset = address[BURST_OFFSET_WIDTH+WORD_SIZE_LOG2-1:WORD_SIZE_LOG2];
// for unaligned or partial transfers we must use a burst length of 1 so that
assign burst_of_one_enable = (short_first_access_enable == 1) | (short_last_access_enable == 1) | (short_first_and_last_access_enable == 1) | // when performing partial accesses use a burst length of 1
((BURST_WRAPPING_SUPPORT == 1) & (burst_offset != 0)); // when the burst boundary offset is non-zero then the master isn't in burst alignment yet as so a burst of 1 needs to be posted
assign short_burst_enable = ((length >> WORD_SIZE_LOG2) < maximum_burst_count);
always @ (maximum_burst_count or length or short_burst_enable or burst_of_one_enable)
begin
case ({short_burst_enable, burst_of_one_enable})
2'b00 : internal_burst_count = maximum_burst_count;
2'b01 : internal_burst_count = 1; // this is when the master starts unaligned
2'b10 : internal_burst_count = ((length >> WORD_SIZE_LOG2) & {(BURST_COUNT_WIDTH-1){1'b1}}); // this could be followed by a burst of 1 if there are a few bytes leftover
2'b11 : internal_burst_count = 1; // burst of 1 needs to win, this is when the master starts with very little data to transfer
endcase
end
generate
if (BURST_ENABLE == 1)
begin
assign burst_count = internal_burst_count;
end
else
begin
assign burst_count = 1; // this will be stubbed at the top level but will be used for the address and pending reads incrementing
end
endgenerate
endmodule
|
module read_burst_control (
address,
length,
maximum_burst_count,
short_first_access_enable,
short_last_access_enable,
short_first_and_last_access_enable,
burst_count
);
parameter BURST_ENABLE = 1; // set to 0 to hardwire the address and write signals straight out
parameter BURST_COUNT_WIDTH = 3;
parameter WORD_SIZE_LOG2 = 2; // log2(DATA WIDTH/8)
parameter ADDRESS_WIDTH = 32;
parameter LENGTH_WIDTH = 32;
parameter BURST_WRAPPING_SUPPORT = 1; // set 1 for on, set 0 for off. This parameter can't be enabled when hte master supports programmable burst.
localparam BURST_OFFSET_WIDTH = (BURST_COUNT_WIDTH == 1)? 1: (BURST_COUNT_WIDTH-1);
input [ADDRESS_WIDTH-1:0] address;
input [LENGTH_WIDTH-1:0] length;
input [BURST_COUNT_WIDTH-1:0] maximum_burst_count; // will be either a hardcoded input or programmable
input short_first_access_enable;
input short_last_access_enable;
input short_first_and_last_access_enable;
output wire [BURST_COUNT_WIDTH-1:0] burst_count;
wire [BURST_COUNT_WIDTH-1:0] posted_burst; // when the burst statemachine is used this will be the burst count posted to the fabric
reg [BURST_COUNT_WIDTH-1:0] internal_burst_count; // muxes posted_burst, posted_burst_d1, and '1' since we need to be able to post bursts of '1' for short accesses
wire burst_of_one_enable; // asserted when partial word accesses are occuring
wire short_burst_enable;
wire [BURST_OFFSET_WIDTH-1:0] burst_offset;
assign burst_offset = address[BURST_OFFSET_WIDTH+WORD_SIZE_LOG2-1:WORD_SIZE_LOG2];
// for unaligned or partial transfers we must use a burst length of 1 so that
assign burst_of_one_enable = (short_first_access_enable == 1) | (short_last_access_enable == 1) | (short_first_and_last_access_enable == 1) | // when performing partial accesses use a burst length of 1
((BURST_WRAPPING_SUPPORT == 1) & (burst_offset != 0)); // when the burst boundary offset is non-zero then the master isn't in burst alignment yet as so a burst of 1 needs to be posted
assign short_burst_enable = ((length >> WORD_SIZE_LOG2) < maximum_burst_count);
always @ (maximum_burst_count or length or short_burst_enable or burst_of_one_enable)
begin
case ({short_burst_enable, burst_of_one_enable})
2'b00 : internal_burst_count = maximum_burst_count;
2'b01 : internal_burst_count = 1; // this is when the master starts unaligned
2'b10 : internal_burst_count = ((length >> WORD_SIZE_LOG2) & {(BURST_COUNT_WIDTH-1){1'b1}}); // this could be followed by a burst of 1 if there are a few bytes leftover
2'b11 : internal_burst_count = 1; // burst of 1 needs to win, this is when the master starts with very little data to transfer
endcase
end
generate
if (BURST_ENABLE == 1)
begin
assign burst_count = internal_burst_count;
end
else
begin
assign burst_count = 1; // this will be stubbed at the top level but will be used for the address and pending reads incrementing
end
endgenerate
endmodule
|
module channel_demux
#(parameter NUM_CHAN = 2) ( //usb Side
input [31:0]usbdata_final,
input WR_final,
// TX Side
input reset,
input txclk,
output reg [NUM_CHAN:0] WR_channel,
output reg [31:0] ram_data,
output reg [NUM_CHAN:0] WR_done_channel );
/* Parse header and forward to ram */
reg [2:0]reader_state;
reg [4:0]channel ;
reg [6:0]read_length ;
// States
parameter IDLE = 3'd0;
parameter HEADER = 3'd1;
parameter WAIT = 3'd2;
parameter FORWARD = 3'd3;
`define CHANNEL 20:16
`define PKT_SIZE 127
wire [4:0] true_channel;
assign true_channel = (usbdata_final[`CHANNEL] == 5'h1f) ?
NUM_CHAN : (usbdata_final[`CHANNEL]);
always @(posedge txclk)
begin
if (reset)
begin
reader_state <= IDLE;
WR_channel <= 0;
WR_done_channel <= 0;
end
else
case (reader_state)
IDLE: begin
if (WR_final)
reader_state <= HEADER;
end
// Store channel and forware header
HEADER: begin
channel <= true_channel;
WR_channel[true_channel] <= 1;
ram_data <= usbdata_final;
read_length <= 7'd0 ;
reader_state <= WAIT;
end
WAIT: begin
WR_channel[channel] <= 0;
if (read_length == `PKT_SIZE)
reader_state <= IDLE;
else if (WR_final)
reader_state <= FORWARD;
end
FORWARD: begin
WR_channel[channel] <= 1;
ram_data <= usbdata_final;
read_length <= read_length + 7'd1;
reader_state <= WAIT;
end
default:
begin
//error handling
reader_state <= IDLE;
end
endcase
end
endmodule
|
module channel_demux
#(parameter NUM_CHAN = 2) ( //usb Side
input [31:0]usbdata_final,
input WR_final,
// TX Side
input reset,
input txclk,
output reg [NUM_CHAN:0] WR_channel,
output reg [31:0] ram_data,
output reg [NUM_CHAN:0] WR_done_channel );
/* Parse header and forward to ram */
reg [2:0]reader_state;
reg [4:0]channel ;
reg [6:0]read_length ;
// States
parameter IDLE = 3'd0;
parameter HEADER = 3'd1;
parameter WAIT = 3'd2;
parameter FORWARD = 3'd3;
`define CHANNEL 20:16
`define PKT_SIZE 127
wire [4:0] true_channel;
assign true_channel = (usbdata_final[`CHANNEL] == 5'h1f) ?
NUM_CHAN : (usbdata_final[`CHANNEL]);
always @(posedge txclk)
begin
if (reset)
begin
reader_state <= IDLE;
WR_channel <= 0;
WR_done_channel <= 0;
end
else
case (reader_state)
IDLE: begin
if (WR_final)
reader_state <= HEADER;
end
// Store channel and forware header
HEADER: begin
channel <= true_channel;
WR_channel[true_channel] <= 1;
ram_data <= usbdata_final;
read_length <= 7'd0 ;
reader_state <= WAIT;
end
WAIT: begin
WR_channel[channel] <= 0;
if (read_length == `PKT_SIZE)
reader_state <= IDLE;
else if (WR_final)
reader_state <= FORWARD;
end
FORWARD: begin
WR_channel[channel] <= 1;
ram_data <= usbdata_final;
read_length <= read_length + 7'd1;
reader_state <= WAIT;
end
default:
begin
//error handling
reader_state <= IDLE;
end
endcase
end
endmodule
|
module fifo_1c_1k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 32;
parameter depth = 1024;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [31:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [31:0] q;
output rdfull;
output rdempty;
output [9:0] rdusedw;
output wrfull;
output wrempty;
output [9:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [7:0] rdptr;
reg [7:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
reg [9:0] rdusedw;
reg [9:0] wrusedw;
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
assign wrempty = (wrusedw == 0);
assign wrfull = (wrusedw == depth-1);
assign rdempty = (rdusedw == 0);
assign rdfull = (rdusedw == depth-1);
endmodule
|
module fifo_1c_1k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 32;
parameter depth = 1024;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [31:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [31:0] q;
output rdfull;
output rdempty;
output [9:0] rdusedw;
output wrfull;
output wrempty;
output [9:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [7:0] rdptr;
reg [7:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
reg [9:0] rdusedw;
reg [9:0] wrusedw;
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
assign wrempty = (wrusedw == 0);
assign wrfull = (wrusedw == depth-1);
assign rdempty = (rdusedw == 0);
assign rdfull = (rdusedw == depth-1);
endmodule
|
module pll (
inclk0,
c0);
input inclk0;
output c0;
endmodule
|
module pll (
inclk0,
c0);
input inclk0;
output c0;
endmodule
|
module rx_chain_dual
(input clock,
input clock_2x,
input reset,
input enable,
input wire [7:0] decim_rate,
input sample_strobe,
input decimator_strobe,
input wire [31:0] freq0,
input wire [15:0] i_in0,
input wire [15:0] q_in0,
output wire [15:0] i_out0,
output wire [15:0] q_out0,
input wire [31:0] freq1,
input wire [15:0] i_in1,
input wire [15:0] q_in1,
output wire [15:0] i_out1,
output wire [15:0] q_out1
);
wire [15:0] phase;
wire [15:0] bb_i, bb_q;
wire [15:0] i_in, q_in;
wire [31:0] phase0;
wire [31:0] phase1;
reg [15:0] bb_i0, bb_q0;
reg [15:0] bb_i1, bb_q1;
// We want to time-share the CORDIC by double-clocking it
phase_acc rx_phase_acc_0
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq0),.phase(phase0) );
phase_acc rx_phase_acc_1
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq1),.phase(phase1) );
assign phase = clock ? phase0[31:16] : phase1[31:16];
assign i_in = clock ? i_in0 : i_in1;
assign q_in = clock ? q_in0 : q_in1;
// This appears reversed because of the number of CORDIC stages
always @(posedge clock_2x)
if(clock)
begin
bb_i1 <= #1 bb_i;
bb_q1 <= #1 bb_q;
end
else
begin
bb_i0 <= #1 bb_i;
bb_q0 <= #1 bb_q;
end
cordic rx_cordic
( .clock(clock_2x),.reset(reset),.enable(enable),
.xi(i_in),.yi(q_in),.zi(phase),
.xo(bb_i),.yo(bb_q),.zo() );
cic_decim cic_decim_i_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_i0),.signal_out(i_out0) );
cic_decim cic_decim_q_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_q0),.signal_out(q_out0) );
cic_decim cic_decim_i_1
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_i1),.signal_out(i_out1) );
cic_decim cic_decim_q_1
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_q1),.signal_out(q_out1) );
endmodule
|
module phase_acc (clk,reset,enable,strobe,serial_addr,serial_data,serial_strobe,phase);
parameter FREQADDR = 0;
parameter PHASEADDR = 0;
parameter resolution = 32;
input clk, reset, enable, strobe;
input [6:0] serial_addr;
input [31:0] serial_data;
input serial_strobe;
output reg [resolution-1:0] phase;
wire [resolution-1:0] freq;
setting_reg #(FREQADDR) sr_rxfreq0(.clock(clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(freq));
always @(posedge clk)
if(reset)
phase <= #1 32'b0;
else if(serial_strobe & (serial_addr == PHASEADDR))
phase <= #1 serial_data;
else if(enable & strobe)
phase <= #1 phase + freq;
endmodule
|
module phase_acc (clk,reset,enable,strobe,serial_addr,serial_data,serial_strobe,phase);
parameter FREQADDR = 0;
parameter PHASEADDR = 0;
parameter resolution = 32;
input clk, reset, enable, strobe;
input [6:0] serial_addr;
input [31:0] serial_data;
input serial_strobe;
output reg [resolution-1:0] phase;
wire [resolution-1:0] freq;
setting_reg #(FREQADDR) sr_rxfreq0(.clock(clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(freq));
always @(posedge clk)
if(reset)
phase <= #1 32'b0;
else if(serial_strobe & (serial_addr == PHASEADDR))
phase <= #1 serial_data;
else if(enable & strobe)
phase <= #1 phase + freq;
endmodule
|
module bustri (
data,
enabledt,
tridata);
input [15:0] data;
input enabledt;
inout [15:0] tridata;
lpm_bustri lpm_bustri_component (
.tridata (tridata),
.enabledt (enabledt),
.data (data));
defparam
lpm_bustri_component.lpm_width = 16,
lpm_bustri_component.lpm_type = "LPM_BUSTRI";
endmodule
|
module sub32_add_sub_cqa
(
aclr,
clken,
clock,
dataa,
datab,
result) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clken;
input clock;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
wire [0:0] wire_add_sub_cella_0cout;
wire [0:0] wire_add_sub_cella_1cout;
wire [0:0] wire_add_sub_cella_2cout;
wire [0:0] wire_add_sub_cella_3cout;
wire [0:0] wire_add_sub_cella_4cout;
wire [0:0] wire_add_sub_cella_5cout;
wire [0:0] wire_add_sub_cella_6cout;
wire [0:0] wire_add_sub_cella_7cout;
wire [0:0] wire_add_sub_cella_8cout;
wire [0:0] wire_add_sub_cella_9cout;
wire [0:0] wire_add_sub_cella_10cout;
wire [0:0] wire_add_sub_cella_11cout;
wire [0:0] wire_add_sub_cella_12cout;
wire [0:0] wire_add_sub_cella_13cout;
wire [0:0] wire_add_sub_cella_14cout;
wire [0:0] wire_add_sub_cella_15cout;
wire [0:0] wire_add_sub_cella_16cout;
wire [0:0] wire_add_sub_cella_17cout;
wire [0:0] wire_add_sub_cella_18cout;
wire [0:0] wire_add_sub_cella_19cout;
wire [0:0] wire_add_sub_cella_20cout;
wire [0:0] wire_add_sub_cella_21cout;
wire [0:0] wire_add_sub_cella_22cout;
wire [0:0] wire_add_sub_cella_23cout;
wire [0:0] wire_add_sub_cella_24cout;
wire [0:0] wire_add_sub_cella_25cout;
wire [0:0] wire_add_sub_cella_26cout;
wire [0:0] wire_add_sub_cella_27cout;
wire [0:0] wire_add_sub_cella_28cout;
wire [0:0] wire_add_sub_cella_29cout;
wire [0:0] wire_add_sub_cella_30cout;
wire [31:0] wire_add_sub_cella_dataa;
wire [31:0] wire_add_sub_cella_datab;
wire [31:0] wire_add_sub_cella_regout;
stratix_lcell add_sub_cella_0
(
.aclr(aclr),
.cin(1'b1),
.clk(clock),
.cout(wire_add_sub_cella_0cout[0:0]),
.dataa(wire_add_sub_cella_dataa[0:0]),
.datab(wire_add_sub_cella_datab[0:0]),
.ena(clken),
.regout(wire_add_sub_cella_regout[0:0]));
defparam
add_sub_cella_0.cin_used = "true",
add_sub_cella_0.lut_mask = "69b2",
add_sub_cella_0.operation_mode = "arithmetic",
add_sub_cella_0.sum_lutc_input = "cin",
add_sub_cella_0.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_1
(
.aclr(aclr),
.cin(wire_add_sub_cella_0cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_1cout[0:0]),
.dataa(wire_add_sub_cella_dataa[1:1]),
.datab(wire_add_sub_cella_datab[1:1]),
.ena(clken),
.regout(wire_add_sub_cella_regout[1:1]));
defparam
add_sub_cella_1.cin_used = "true",
add_sub_cella_1.lut_mask = "69b2",
add_sub_cella_1.operation_mode = "arithmetic",
add_sub_cella_1.sum_lutc_input = "cin",
add_sub_cella_1.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_2
(
.aclr(aclr),
.cin(wire_add_sub_cella_1cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_2cout[0:0]),
.dataa(wire_add_sub_cella_dataa[2:2]),
.datab(wire_add_sub_cella_datab[2:2]),
.ena(clken),
.regout(wire_add_sub_cella_regout[2:2]));
defparam
add_sub_cella_2.cin_used = "true",
add_sub_cella_2.lut_mask = "69b2",
add_sub_cella_2.operation_mode = "arithmetic",
add_sub_cella_2.sum_lutc_input = "cin",
add_sub_cella_2.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_3
(
.aclr(aclr),
.cin(wire_add_sub_cella_2cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_3cout[0:0]),
.dataa(wire_add_sub_cella_dataa[3:3]),
.datab(wire_add_sub_cella_datab[3:3]),
.ena(clken),
.regout(wire_add_sub_cella_regout[3:3]));
defparam
add_sub_cella_3.cin_used = "true",
add_sub_cella_3.lut_mask = "69b2",
add_sub_cella_3.operation_mode = "arithmetic",
add_sub_cella_3.sum_lutc_input = "cin",
add_sub_cella_3.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_4
(
.aclr(aclr),
.cin(wire_add_sub_cella_3cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_4cout[0:0]),
.dataa(wire_add_sub_cella_dataa[4:4]),
.datab(wire_add_sub_cella_datab[4:4]),
.ena(clken),
.regout(wire_add_sub_cella_regout[4:4]));
defparam
add_sub_cella_4.cin_used = "true",
add_sub_cella_4.lut_mask = "69b2",
add_sub_cella_4.operation_mode = "arithmetic",
add_sub_cella_4.sum_lutc_input = "cin",
add_sub_cella_4.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_5
(
.aclr(aclr),
.cin(wire_add_sub_cella_4cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_5cout[0:0]),
.dataa(wire_add_sub_cella_dataa[5:5]),
.datab(wire_add_sub_cella_datab[5:5]),
.ena(clken),
.regout(wire_add_sub_cella_regout[5:5]));
defparam
add_sub_cella_5.cin_used = "true",
add_sub_cella_5.lut_mask = "69b2",
add_sub_cella_5.operation_mode = "arithmetic",
add_sub_cella_5.sum_lutc_input = "cin",
add_sub_cella_5.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_6
(
.aclr(aclr),
.cin(wire_add_sub_cella_5cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_6cout[0:0]),
.dataa(wire_add_sub_cella_dataa[6:6]),
.datab(wire_add_sub_cella_datab[6:6]),
.ena(clken),
.regout(wire_add_sub_cella_regout[6:6]));
defparam
add_sub_cella_6.cin_used = "true",
add_sub_cella_6.lut_mask = "69b2",
add_sub_cella_6.operation_mode = "arithmetic",
add_sub_cella_6.sum_lutc_input = "cin",
add_sub_cella_6.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_7
(
.aclr(aclr),
.cin(wire_add_sub_cella_6cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_7cout[0:0]),
.dataa(wire_add_sub_cella_dataa[7:7]),
.datab(wire_add_sub_cella_datab[7:7]),
.ena(clken),
.regout(wire_add_sub_cella_regout[7:7]));
defparam
add_sub_cella_7.cin_used = "true",
add_sub_cella_7.lut_mask = "69b2",
add_sub_cella_7.operation_mode = "arithmetic",
add_sub_cella_7.sum_lutc_input = "cin",
add_sub_cella_7.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_8
(
.aclr(aclr),
.cin(wire_add_sub_cella_7cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_8cout[0:0]),
.dataa(wire_add_sub_cella_dataa[8:8]),
.datab(wire_add_sub_cella_datab[8:8]),
.ena(clken),
.regout(wire_add_sub_cella_regout[8:8]));
defparam
add_sub_cella_8.cin_used = "true",
add_sub_cella_8.lut_mask = "69b2",
add_sub_cella_8.operation_mode = "arithmetic",
add_sub_cella_8.sum_lutc_input = "cin",
add_sub_cella_8.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_9
(
.aclr(aclr),
.cin(wire_add_sub_cella_8cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_9cout[0:0]),
.dataa(wire_add_sub_cella_dataa[9:9]),
.datab(wire_add_sub_cella_datab[9:9]),
.ena(clken),
.regout(wire_add_sub_cella_regout[9:9]));
defparam
add_sub_cella_9.cin_used = "true",
add_sub_cella_9.lut_mask = "69b2",
add_sub_cella_9.operation_mode = "arithmetic",
add_sub_cella_9.sum_lutc_input = "cin",
add_sub_cella_9.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_10
(
.aclr(aclr),
.cin(wire_add_sub_cella_9cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_10cout[0:0]),
.dataa(wire_add_sub_cella_dataa[10:10]),
.datab(wire_add_sub_cella_datab[10:10]),
.ena(clken),
.regout(wire_add_sub_cella_regout[10:10]));
defparam
add_sub_cella_10.cin_used = "true",
add_sub_cella_10.lut_mask = "69b2",
add_sub_cella_10.operation_mode = "arithmetic",
add_sub_cella_10.sum_lutc_input = "cin",
add_sub_cella_10.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_11
(
.aclr(aclr),
.cin(wire_add_sub_cella_10cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_11cout[0:0]),
.dataa(wire_add_sub_cella_dataa[11:11]),
.datab(wire_add_sub_cella_datab[11:11]),
.ena(clken),
.regout(wire_add_sub_cella_regout[11:11]));
defparam
add_sub_cella_11.cin_used = "true",
add_sub_cella_11.lut_mask = "69b2",
add_sub_cella_11.operation_mode = "arithmetic",
add_sub_cella_11.sum_lutc_input = "cin",
add_sub_cella_11.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_12
(
.aclr(aclr),
.cin(wire_add_sub_cella_11cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_12cout[0:0]),
.dataa(wire_add_sub_cella_dataa[12:12]),
.datab(wire_add_sub_cella_datab[12:12]),
.ena(clken),
.regout(wire_add_sub_cella_regout[12:12]));
defparam
add_sub_cella_12.cin_used = "true",
add_sub_cella_12.lut_mask = "69b2",
add_sub_cella_12.operation_mode = "arithmetic",
add_sub_cella_12.sum_lutc_input = "cin",
add_sub_cella_12.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_13
(
.aclr(aclr),
.cin(wire_add_sub_cella_12cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_13cout[0:0]),
.dataa(wire_add_sub_cella_dataa[13:13]),
.datab(wire_add_sub_cella_datab[13:13]),
.ena(clken),
.regout(wire_add_sub_cella_regout[13:13]));
defparam
add_sub_cella_13.cin_used = "true",
add_sub_cella_13.lut_mask = "69b2",
add_sub_cella_13.operation_mode = "arithmetic",
add_sub_cella_13.sum_lutc_input = "cin",
add_sub_cella_13.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_14
(
.aclr(aclr),
.cin(wire_add_sub_cella_13cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_14cout[0:0]),
.dataa(wire_add_sub_cella_dataa[14:14]),
.datab(wire_add_sub_cella_datab[14:14]),
.ena(clken),
.regout(wire_add_sub_cella_regout[14:14]));
defparam
add_sub_cella_14.cin_used = "true",
add_sub_cella_14.lut_mask = "69b2",
add_sub_cella_14.operation_mode = "arithmetic",
add_sub_cella_14.sum_lutc_input = "cin",
add_sub_cella_14.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_15
(
.aclr(aclr),
.cin(wire_add_sub_cella_14cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_15cout[0:0]),
.dataa(wire_add_sub_cella_dataa[15:15]),
.datab(wire_add_sub_cella_datab[15:15]),
.ena(clken),
.regout(wire_add_sub_cella_regout[15:15]));
defparam
add_sub_cella_15.cin_used = "true",
add_sub_cella_15.lut_mask = "69b2",
add_sub_cella_15.operation_mode = "arithmetic",
add_sub_cella_15.sum_lutc_input = "cin",
add_sub_cella_15.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_16
(
.aclr(aclr),
.cin(wire_add_sub_cella_15cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_16cout[0:0]),
.dataa(wire_add_sub_cella_dataa[16:16]),
.datab(wire_add_sub_cella_datab[16:16]),
.ena(clken),
.regout(wire_add_sub_cella_regout[16:16]));
defparam
add_sub_cella_16.cin_used = "true",
add_sub_cella_16.lut_mask = "69b2",
add_sub_cella_16.operation_mode = "arithmetic",
add_sub_cella_16.sum_lutc_input = "cin",
add_sub_cella_16.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_17
(
.aclr(aclr),
.cin(wire_add_sub_cella_16cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_17cout[0:0]),
.dataa(wire_add_sub_cella_dataa[17:17]),
.datab(wire_add_sub_cella_datab[17:17]),
.ena(clken),
.regout(wire_add_sub_cella_regout[17:17]));
defparam
add_sub_cella_17.cin_used = "true",
add_sub_cella_17.lut_mask = "69b2",
add_sub_cella_17.operation_mode = "arithmetic",
add_sub_cella_17.sum_lutc_input = "cin",
add_sub_cella_17.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_18
(
.aclr(aclr),
.cin(wire_add_sub_cella_17cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_18cout[0:0]),
.dataa(wire_add_sub_cella_dataa[18:18]),
.datab(wire_add_sub_cella_datab[18:18]),
.ena(clken),
.regout(wire_add_sub_cella_regout[18:18]));
defparam
add_sub_cella_18.cin_used = "true",
add_sub_cella_18.lut_mask = "69b2",
add_sub_cella_18.operation_mode = "arithmetic",
add_sub_cella_18.sum_lutc_input = "cin",
add_sub_cella_18.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_19
(
.aclr(aclr),
.cin(wire_add_sub_cella_18cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_19cout[0:0]),
.dataa(wire_add_sub_cella_dataa[19:19]),
.datab(wire_add_sub_cella_datab[19:19]),
.ena(clken),
.regout(wire_add_sub_cella_regout[19:19]));
defparam
add_sub_cella_19.cin_used = "true",
add_sub_cella_19.lut_mask = "69b2",
add_sub_cella_19.operation_mode = "arithmetic",
add_sub_cella_19.sum_lutc_input = "cin",
add_sub_cella_19.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_20
(
.aclr(aclr),
.cin(wire_add_sub_cella_19cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_20cout[0:0]),
.dataa(wire_add_sub_cella_dataa[20:20]),
.datab(wire_add_sub_cella_datab[20:20]),
.ena(clken),
.regout(wire_add_sub_cella_regout[20:20]));
defparam
add_sub_cella_20.cin_used = "true",
add_sub_cella_20.lut_mask = "69b2",
add_sub_cella_20.operation_mode = "arithmetic",
add_sub_cella_20.sum_lutc_input = "cin",
add_sub_cella_20.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_21
(
.aclr(aclr),
.cin(wire_add_sub_cella_20cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_21cout[0:0]),
.dataa(wire_add_sub_cella_dataa[21:21]),
.datab(wire_add_sub_cella_datab[21:21]),
.ena(clken),
.regout(wire_add_sub_cella_regout[21:21]));
defparam
add_sub_cella_21.cin_used = "true",
add_sub_cella_21.lut_mask = "69b2",
add_sub_cella_21.operation_mode = "arithmetic",
add_sub_cella_21.sum_lutc_input = "cin",
add_sub_cella_21.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_22
(
.aclr(aclr),
.cin(wire_add_sub_cella_21cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_22cout[0:0]),
.dataa(wire_add_sub_cella_dataa[22:22]),
.datab(wire_add_sub_cella_datab[22:22]),
.ena(clken),
.regout(wire_add_sub_cella_regout[22:22]));
defparam
add_sub_cella_22.cin_used = "true",
add_sub_cella_22.lut_mask = "69b2",
add_sub_cella_22.operation_mode = "arithmetic",
add_sub_cella_22.sum_lutc_input = "cin",
add_sub_cella_22.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_23
(
.aclr(aclr),
.cin(wire_add_sub_cella_22cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_23cout[0:0]),
.dataa(wire_add_sub_cella_dataa[23:23]),
.datab(wire_add_sub_cella_datab[23:23]),
.ena(clken),
.regout(wire_add_sub_cella_regout[23:23]));
defparam
add_sub_cella_23.cin_used = "true",
add_sub_cella_23.lut_mask = "69b2",
add_sub_cella_23.operation_mode = "arithmetic",
add_sub_cella_23.sum_lutc_input = "cin",
add_sub_cella_23.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_24
(
.aclr(aclr),
.cin(wire_add_sub_cella_23cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_24cout[0:0]),
.dataa(wire_add_sub_cella_dataa[24:24]),
.datab(wire_add_sub_cella_datab[24:24]),
.ena(clken),
.regout(wire_add_sub_cella_regout[24:24]));
defparam
add_sub_cella_24.cin_used = "true",
add_sub_cella_24.lut_mask = "69b2",
add_sub_cella_24.operation_mode = "arithmetic",
add_sub_cella_24.sum_lutc_input = "cin",
add_sub_cella_24.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_25
(
.aclr(aclr),
.cin(wire_add_sub_cella_24cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_25cout[0:0]),
.dataa(wire_add_sub_cella_dataa[25:25]),
.datab(wire_add_sub_cella_datab[25:25]),
.ena(clken),
.regout(wire_add_sub_cella_regout[25:25]));
defparam
add_sub_cella_25.cin_used = "true",
add_sub_cella_25.lut_mask = "69b2",
add_sub_cella_25.operation_mode = "arithmetic",
add_sub_cella_25.sum_lutc_input = "cin",
add_sub_cella_25.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_26
(
.aclr(aclr),
.cin(wire_add_sub_cella_25cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_26cout[0:0]),
.dataa(wire_add_sub_cella_dataa[26:26]),
.datab(wire_add_sub_cella_datab[26:26]),
.ena(clken),
.regout(wire_add_sub_cella_regout[26:26]));
defparam
add_sub_cella_26.cin_used = "true",
add_sub_cella_26.lut_mask = "69b2",
add_sub_cella_26.operation_mode = "arithmetic",
add_sub_cella_26.sum_lutc_input = "cin",
add_sub_cella_26.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_27
(
.aclr(aclr),
.cin(wire_add_sub_cella_26cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_27cout[0:0]),
.dataa(wire_add_sub_cella_dataa[27:27]),
.datab(wire_add_sub_cella_datab[27:27]),
.ena(clken),
.regout(wire_add_sub_cella_regout[27:27]));
defparam
add_sub_cella_27.cin_used = "true",
add_sub_cella_27.lut_mask = "69b2",
add_sub_cella_27.operation_mode = "arithmetic",
add_sub_cella_27.sum_lutc_input = "cin",
add_sub_cella_27.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_28
(
.aclr(aclr),
.cin(wire_add_sub_cella_27cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_28cout[0:0]),
.dataa(wire_add_sub_cella_dataa[28:28]),
.datab(wire_add_sub_cella_datab[28:28]),
.ena(clken),
.regout(wire_add_sub_cella_regout[28:28]));
defparam
add_sub_cella_28.cin_used = "true",
add_sub_cella_28.lut_mask = "69b2",
add_sub_cella_28.operation_mode = "arithmetic",
add_sub_cella_28.sum_lutc_input = "cin",
add_sub_cella_28.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_29
(
.aclr(aclr),
.cin(wire_add_sub_cella_28cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_29cout[0:0]),
.dataa(wire_add_sub_cella_dataa[29:29]),
.datab(wire_add_sub_cella_datab[29:29]),
.ena(clken),
.regout(wire_add_sub_cella_regout[29:29]));
defparam
add_sub_cella_29.cin_used = "true",
add_sub_cella_29.lut_mask = "69b2",
add_sub_cella_29.operation_mode = "arithmetic",
add_sub_cella_29.sum_lutc_input = "cin",
add_sub_cella_29.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_30
(
.aclr(aclr),
.cin(wire_add_sub_cella_29cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_30cout[0:0]),
.dataa(wire_add_sub_cella_dataa[30:30]),
.datab(wire_add_sub_cella_datab[30:30]),
.ena(clken),
.regout(wire_add_sub_cella_regout[30:30]));
defparam
add_sub_cella_30.cin_used = "true",
add_sub_cella_30.lut_mask = "69b2",
add_sub_cella_30.operation_mode = "arithmetic",
add_sub_cella_30.sum_lutc_input = "cin",
add_sub_cella_30.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_31
(
.aclr(aclr),
.cin(wire_add_sub_cella_30cout[0:0]),
.clk(clock),
.dataa(wire_add_sub_cella_dataa[31:31]),
.datab(wire_add_sub_cella_datab[31:31]),
.ena(clken),
.regout(wire_add_sub_cella_regout[31:31]));
defparam
add_sub_cella_31.cin_used = "true",
add_sub_cella_31.lut_mask = "6969",
add_sub_cella_31.operation_mode = "normal",
add_sub_cella_31.sum_lutc_input = "cin",
add_sub_cella_31.lpm_type = "stratix_lcell";
assign
wire_add_sub_cella_dataa = dataa,
wire_add_sub_cella_datab = datab;
assign
result = wire_add_sub_cella_regout;
endmodule
|
module sub32 (
dataa,
datab,
clock,
aclr,
clken,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] dataa;
input [31:0] datab;
input clock;
input aclr;
input clken;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
sub32_add_sub_cqa sub32_add_sub_cqa_component (
.dataa (dataa),
.datab (datab),
.clken (clken),
.aclr (aclr),
.clock (clock),
.result (sub_wire0));
endmodule
|
module sub32 (
dataa,
datab,
clock,
aclr,
clken,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] dataa;
input [31:0] datab;
input clock;
input aclr;
input clken;
output [31:0] result;
endmodule
|
module sub32 (
dataa,
datab,
clock,
aclr,
clken,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] dataa;
input [31:0] datab;
input clock;
input aclr;
input clken;
output [31:0] result;
endmodule
|
module rx_chain
(input clock,
input reset,
input enable,
input wire [7:0] decim_rate,
input sample_strobe,
input decimator_strobe,
output wire hb_strobe,
input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out,
output wire [15:0] debugdata,output wire [15:0] debugctrl
);
parameter FREQADDR = 0;
parameter PHASEADDR = 0;
wire [31:0] phase;
wire [15:0] bb_i, bb_q;
wire [15:0] hb_in_i, hb_in_q;
assign debugdata = hb_in_i;
`ifdef RX_NCO_ON
phase_acc #(FREQADDR,PHASEADDR,32) rx_phase_acc
(.clk(clock),.reset(reset),.enable(enable),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.strobe(sample_strobe),.phase(phase) );
cordic rx_cordic
( .clock(clock),.reset(reset),.enable(enable),
.xi(i_in),.yi(q_in),.zi(phase[31:16]),
.xo(bb_i),.yo(bb_q),.zo() );
`else
assign bb_i = i_in;
assign bb_q = q_in;
assign sample_strobe = 1;
`endif // !`ifdef RX_NCO_ON
`ifdef RX_CIC_ON
cic_decim cic_decim_i_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_i),.signal_out(hb_in_i) );
`else
assign hb_in_i = bb_i;
assign decimator_strobe = sample_strobe;
`endif
`ifdef RX_HB_ON
halfband_decim hbd_i_0
( .clock(clock),.reset(reset),.enable(enable),
.strobe_in(decimator_strobe),.strobe_out(hb_strobe),
.data_in(hb_in_i),.data_out(i_out),.debugctrl(debugctrl) );
`else
assign i_out = hb_in_i;
assign hb_strobe = decimator_strobe;
`endif
`ifdef RX_CIC_ON
cic_decim cic_decim_q_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_q),.signal_out(hb_in_q) );
`else
assign hb_in_q = bb_q;
`endif
`ifdef RX_HB_ON
halfband_decim hbd_q_0
( .clock(clock),.reset(reset),.enable(enable),
.strobe_in(decimator_strobe),.strobe_out(),
.data_in(hb_in_q),.data_out(q_out) );
`else
assign q_out = hb_in_q;
`endif
endmodule
|
module rx_chain
(input clock,
input reset,
input enable,
input wire [7:0] decim_rate,
input sample_strobe,
input decimator_strobe,
output wire hb_strobe,
input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out,
output wire [15:0] debugdata,output wire [15:0] debugctrl
);
parameter FREQADDR = 0;
parameter PHASEADDR = 0;
wire [31:0] phase;
wire [15:0] bb_i, bb_q;
wire [15:0] hb_in_i, hb_in_q;
assign debugdata = hb_in_i;
`ifdef RX_NCO_ON
phase_acc #(FREQADDR,PHASEADDR,32) rx_phase_acc
(.clk(clock),.reset(reset),.enable(enable),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.strobe(sample_strobe),.phase(phase) );
cordic rx_cordic
( .clock(clock),.reset(reset),.enable(enable),
.xi(i_in),.yi(q_in),.zi(phase[31:16]),
.xo(bb_i),.yo(bb_q),.zo() );
`else
assign bb_i = i_in;
assign bb_q = q_in;
assign sample_strobe = 1;
`endif // !`ifdef RX_NCO_ON
`ifdef RX_CIC_ON
cic_decim cic_decim_i_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_i),.signal_out(hb_in_i) );
`else
assign hb_in_i = bb_i;
assign decimator_strobe = sample_strobe;
`endif
`ifdef RX_HB_ON
halfband_decim hbd_i_0
( .clock(clock),.reset(reset),.enable(enable),
.strobe_in(decimator_strobe),.strobe_out(hb_strobe),
.data_in(hb_in_i),.data_out(i_out),.debugctrl(debugctrl) );
`else
assign i_out = hb_in_i;
assign hb_strobe = decimator_strobe;
`endif
`ifdef RX_CIC_ON
cic_decim cic_decim_q_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_q),.signal_out(hb_in_q) );
`else
assign hb_in_q = bb_q;
`endif
`ifdef RX_HB_ON
halfband_decim hbd_q_0
( .clock(clock),.reset(reset),.enable(enable),
.strobe_in(decimator_strobe),.strobe_out(),
.data_in(hb_in_q),.data_out(q_out) );
`else
assign q_out = hb_in_q;
`endif
endmodule
|
module rx_chain
(input clock,
input reset,
input enable,
input wire [7:0] decim_rate,
input sample_strobe,
input decimator_strobe,
output wire hb_strobe,
input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out,
output wire [15:0] debugdata,output wire [15:0] debugctrl
);
parameter FREQADDR = 0;
parameter PHASEADDR = 0;
wire [31:0] phase;
wire [15:0] bb_i, bb_q;
wire [15:0] hb_in_i, hb_in_q;
assign debugdata = hb_in_i;
`ifdef RX_NCO_ON
phase_acc #(FREQADDR,PHASEADDR,32) rx_phase_acc
(.clk(clock),.reset(reset),.enable(enable),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.strobe(sample_strobe),.phase(phase) );
cordic rx_cordic
( .clock(clock),.reset(reset),.enable(enable),
.xi(i_in),.yi(q_in),.zi(phase[31:16]),
.xo(bb_i),.yo(bb_q),.zo() );
`else
assign bb_i = i_in;
assign bb_q = q_in;
assign sample_strobe = 1;
`endif // !`ifdef RX_NCO_ON
`ifdef RX_CIC_ON
cic_decim cic_decim_i_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_i),.signal_out(hb_in_i) );
`else
assign hb_in_i = bb_i;
assign decimator_strobe = sample_strobe;
`endif
`ifdef RX_HB_ON
halfband_decim hbd_i_0
( .clock(clock),.reset(reset),.enable(enable),
.strobe_in(decimator_strobe),.strobe_out(hb_strobe),
.data_in(hb_in_i),.data_out(i_out),.debugctrl(debugctrl) );
`else
assign i_out = hb_in_i;
assign hb_strobe = decimator_strobe;
`endif
`ifdef RX_CIC_ON
cic_decim cic_decim_q_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_q),.signal_out(hb_in_q) );
`else
assign hb_in_q = bb_q;
`endif
`ifdef RX_HB_ON
halfband_decim hbd_q_0
( .clock(clock),.reset(reset),.enable(enable),
.strobe_in(decimator_strobe),.strobe_out(),
.data_in(hb_in_q),.data_out(q_out) );
`else
assign q_out = hb_in_q;
`endif
endmodule
|
module halfband_interp
(input clock, input reset, input enable,
input strobe_in, input strobe_out,
input [15:0] signal_in_i, input [15:0] signal_in_q,
output reg [15:0] signal_out_i, output reg [15:0] signal_out_q,
output wire [12:0] debug);
wire [15:0] coeff_ram_out;
wire [15:0] data_ram_out_i;
wire [15:0] data_ram_out_q;
wire [3:0] data_rd_addr;
reg [3:0] data_wr_addr;
reg [2:0] coeff_rd_addr;
wire filt_done;
wire [15:0] mac_out_i;
wire [15:0] mac_out_q;
reg [15:0] delayed_middle_i, delayed_middle_q;
wire [7:0] shift = 8'd9;
reg stb_out_happened;
wire [15:0] data_ram_out_i_b;
always @(posedge clock)
if(strobe_in)
stb_out_happened <= #1 1'b0;
else if(strobe_out)
stb_out_happened <= #1 1'b1;
assign debug = {filt_done,data_rd_addr,data_wr_addr,coeff_rd_addr};
wire [15:0] signal_out_i = stb_out_happened ? mac_out_i : delayed_middle_i;
wire [15:0] signal_out_q = stb_out_happened ? mac_out_q : delayed_middle_q;
/* always @(posedge clock)
if(reset)
begin
signal_out_i <= #1 16'd0;
signal_out_q <= #1 16'd0;
end
else if(strobe_in)
begin
signal_out_i <= #1 delayed_middle_i; // Multiply by 1 for middle coeff
signal_out_q <= #1 delayed_middle_q;
end
//else if(filt_done&stb_out_happened)
else if(stb_out_happened)
begin
signal_out_i <= #1 mac_out_i;
signal_out_q <= #1 mac_out_q;
end
*/
always @(posedge clock)
if(reset)
coeff_rd_addr <= #1 3'd0;
else if(coeff_rd_addr != 3'd0)
coeff_rd_addr <= #1 coeff_rd_addr + 3'd1;
else if(strobe_in)
coeff_rd_addr <= #1 3'd1;
reg filt_done_d1;
always@(posedge clock)
filt_done_d1 <= #1 filt_done;
always @(posedge clock)
if(reset)
data_wr_addr <= #1 4'd0;
//else if(strobe_in)
else if(filt_done & ~filt_done_d1)
data_wr_addr <= #1 data_wr_addr + 4'd1;
always @(posedge clock)
if(coeff_rd_addr == 3'd7)
begin
delayed_middle_i <= #1 data_ram_out_i_b;
// delayed_middle_q <= #1 data_ram_out_q_b;
end
// always @(posedge clock)
// if(reset)
// data_rd_addr <= #1 4'd0;
// else if(strobe_in)
// data_rd_addr <= #1 data_wr_addr + 4'd1;
// else if(!filt_done)
// data_rd_addr <= #1 data_rd_addr + 4'd1;
// else
// data_rd_addr <= #1 data_wr_addr;
wire [3:0] data_rd_addr1 = data_wr_addr + {1'b0,coeff_rd_addr};
wire [3:0] data_rd_addr2 = data_wr_addr + 15 - {1'b0,coeff_rd_addr};
// always @(posedge clock)
// if(reset)
// filt_done <= #1 1'b1;
// else if(strobe_in)
// filt_done <= #1 1'b0;
// else if(coeff_rd_addr == 4'd0)
// filt_done <= #1 1'b1;
assign filt_done = (coeff_rd_addr == 3'd0);
coeff_ram coeff_ram ( .clock(clock),.rd_addr({1'b0,coeff_rd_addr}),.rd_data(coeff_ram_out) );
ram16_2sum data_ram_i ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_i),
.rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_i_b),.sum(data_ram_out_i));
ram16_2sum data_ram_q ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_q),
.rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_q));
mac mac_i (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in),
.x(data_ram_out_i),.y(coeff_ram_out),.shift(shift),.z(mac_out_i) );
mac mac_q (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in),
.x(data_ram_out_q),.y(coeff_ram_out),.shift(shift),.z(mac_out_q) );
endmodule
|
module add32_add_sub_nq7
(
dataa,
datab,
result) /* synthesis synthesis_clearbox=1 */;
input [7:0] dataa;
input [7:0] datab;
output [7:0] result;
wire [7:0] wire_add_sub_cella_combout;
wire [0:0] wire_add_sub_cella_0cout;
wire [0:0] wire_add_sub_cella_1cout;
wire [0:0] wire_add_sub_cella_2cout;
wire [0:0] wire_add_sub_cella_3cout;
wire [0:0] wire_add_sub_cella_4cout;
wire [0:0] wire_add_sub_cella_5cout;
wire [0:0] wire_add_sub_cella_6cout;
wire [7:0] wire_add_sub_cella_dataa;
wire [7:0] wire_add_sub_cella_datab;
stratix_lcell add_sub_cella_0
(
.cin(1'b0),
.combout(wire_add_sub_cella_combout[0:0]),
.cout(wire_add_sub_cella_0cout[0:0]),
.dataa(wire_add_sub_cella_dataa[0:0]),
.datab(wire_add_sub_cella_datab[0:0]));
defparam
add_sub_cella_0.cin_used = "true",
add_sub_cella_0.lut_mask = "96e8",
add_sub_cella_0.operation_mode = "arithmetic",
add_sub_cella_0.sum_lutc_input = "cin",
add_sub_cella_0.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_1
(
.cin(wire_add_sub_cella_0cout[0:0]),
.combout(wire_add_sub_cella_combout[1:1]),
.cout(wire_add_sub_cella_1cout[0:0]),
.dataa(wire_add_sub_cella_dataa[1:1]),
.datab(wire_add_sub_cella_datab[1:1]));
defparam
add_sub_cella_1.cin_used = "true",
add_sub_cella_1.lut_mask = "96e8",
add_sub_cella_1.operation_mode = "arithmetic",
add_sub_cella_1.sum_lutc_input = "cin",
add_sub_cella_1.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_2
(
.cin(wire_add_sub_cella_1cout[0:0]),
.combout(wire_add_sub_cella_combout[2:2]),
.cout(wire_add_sub_cella_2cout[0:0]),
.dataa(wire_add_sub_cella_dataa[2:2]),
.datab(wire_add_sub_cella_datab[2:2]));
defparam
add_sub_cella_2.cin_used = "true",
add_sub_cella_2.lut_mask = "96e8",
add_sub_cella_2.operation_mode = "arithmetic",
add_sub_cella_2.sum_lutc_input = "cin",
add_sub_cella_2.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_3
(
.cin(wire_add_sub_cella_2cout[0:0]),
.combout(wire_add_sub_cella_combout[3:3]),
.cout(wire_add_sub_cella_3cout[0:0]),
.dataa(wire_add_sub_cella_dataa[3:3]),
.datab(wire_add_sub_cella_datab[3:3]));
defparam
add_sub_cella_3.cin_used = "true",
add_sub_cella_3.lut_mask = "96e8",
add_sub_cella_3.operation_mode = "arithmetic",
add_sub_cella_3.sum_lutc_input = "cin",
add_sub_cella_3.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_4
(
.cin(wire_add_sub_cella_3cout[0:0]),
.combout(wire_add_sub_cella_combout[4:4]),
.cout(wire_add_sub_cella_4cout[0:0]),
.dataa(wire_add_sub_cella_dataa[4:4]),
.datab(wire_add_sub_cella_datab[4:4]));
defparam
add_sub_cella_4.cin_used = "true",
add_sub_cella_4.lut_mask = "96e8",
add_sub_cella_4.operation_mode = "arithmetic",
add_sub_cella_4.sum_lutc_input = "cin",
add_sub_cella_4.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_5
(
.cin(wire_add_sub_cella_4cout[0:0]),
.combout(wire_add_sub_cella_combout[5:5]),
.cout(wire_add_sub_cella_5cout[0:0]),
.dataa(wire_add_sub_cella_dataa[5:5]),
.datab(wire_add_sub_cella_datab[5:5]));
defparam
add_sub_cella_5.cin_used = "true",
add_sub_cella_5.lut_mask = "96e8",
add_sub_cella_5.operation_mode = "arithmetic",
add_sub_cella_5.sum_lutc_input = "cin",
add_sub_cella_5.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_6
(
.cin(wire_add_sub_cella_5cout[0:0]),
.combout(wire_add_sub_cella_combout[6:6]),
.cout(wire_add_sub_cella_6cout[0:0]),
.dataa(wire_add_sub_cella_dataa[6:6]),
.datab(wire_add_sub_cella_datab[6:6]));
defparam
add_sub_cella_6.cin_used = "true",
add_sub_cella_6.lut_mask = "96e8",
add_sub_cella_6.operation_mode = "arithmetic",
add_sub_cella_6.sum_lutc_input = "cin",
add_sub_cella_6.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_7
(
.cin(wire_add_sub_cella_6cout[0:0]),
.combout(wire_add_sub_cella_combout[7:7]),
.dataa(wire_add_sub_cella_dataa[7:7]),
.datab(wire_add_sub_cella_datab[7:7]));
defparam
add_sub_cella_7.cin_used = "true",
add_sub_cella_7.lut_mask = "9696",
add_sub_cella_7.operation_mode = "normal",
add_sub_cella_7.sum_lutc_input = "cin",
add_sub_cella_7.lpm_type = "stratix_lcell";
assign
wire_add_sub_cella_dataa = dataa,
wire_add_sub_cella_datab = datab;
assign
result = wire_add_sub_cella_combout;
endmodule
|
module add32 (
dataa,
datab,
result)/* synthesis synthesis_clearbox = 1 */;
input [7:0] dataa;
input [7:0] datab;
output [7:0] result;
wire [7:0] sub_wire0;
wire [7:0] result = sub_wire0[7:0];
add32_add_sub_nq7 add32_add_sub_nq7_component (
.dataa (dataa),
.datab (datab),
.result (sub_wire0));
endmodule
|
module tx_chain
(input clock,
input reset,
input enable,
input wire [7:0] interp_rate,
input sample_strobe,
input interpolator_strobe,
input wire [31:0] freq,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out
);
wire [15:0] bb_i, bb_q;
cic_interp cic_interp_i
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe),
.signal_in(i_in),.signal_out(bb_i) );
cic_interp cic_interp_q
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe),
.signal_in(q_in),.signal_out(bb_q) );
`define NOCORDIC_TX
`ifdef NOCORDIC_TX
assign i_out = bb_i;
assign q_out = bb_q;
`else
wire [31:0] phase;
phase_acc phase_acc_tx
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq),.phase(phase) );
cordic tx_cordic_0
( .clock(clock),.reset(reset),.enable(sample_strobe),
.xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
.xo(i_out),.yo(q_out),.zo() );
`endif
endmodule
|
module pll (
inclk0,
c0);
input inclk0;
output c0;
wire [5:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0)
// synopsys translate_off
,
.fbin (),
.pllena (),
.clkswitch (),
.areset (),
.pfdena (),
.clkena (),
.extclkena (),
.scanclk (),
.scanaclr (),
.scandata (),
.scanread (),
.scanwrite (),
.extclk (),
.clkbad (),
.activeclock (),
.locked (),
.clkloss (),
.scandataout (),
.scandone (),
.sclkout1 (),
.sclkout0 (),
.enable0 (),
.enable1 ()
// synopsys translate_on
);
defparam
altpll_component.clk0_duty_cycle = 50,
altpll_component.lpm_type = "altpll",
altpll_component.clk0_multiply_by = 1,
altpll_component.inclk0_input_frequency = 20833,
altpll_component.clk0_divide_by = 1,
altpll_component.pll_type = "AUTO",
altpll_component.clk0_time_delay = "0",
altpll_component.intended_device_family = "Cyclone",
altpll_component.operation_mode = "NORMAL",
altpll_component.compensate_clock = "CLK0",
altpll_component.clk0_phase_shift = "-3000";
endmodule
|
module pll (
inclk0,
c0);
input inclk0;
output c0;
wire [5:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0)
// synopsys translate_off
,
.fbin (),
.pllena (),
.clkswitch (),
.areset (),
.pfdena (),
.clkena (),
.extclkena (),
.scanclk (),
.scanaclr (),
.scandata (),
.scanread (),
.scanwrite (),
.extclk (),
.clkbad (),
.activeclock (),
.locked (),
.clkloss (),
.scandataout (),
.scandone (),
.sclkout1 (),
.sclkout0 (),
.enable0 (),
.enable1 ()
// synopsys translate_on
);
defparam
altpll_component.clk0_duty_cycle = 50,
altpll_component.lpm_type = "altpll",
altpll_component.clk0_multiply_by = 1,
altpll_component.inclk0_input_frequency = 20833,
altpll_component.clk0_divide_by = 1,
altpll_component.pll_type = "AUTO",
altpll_component.clk0_time_delay = "0",
altpll_component.intended_device_family = "Cyclone",
altpll_component.operation_mode = "NORMAL",
altpll_component.compensate_clock = "CLK0",
altpll_component.clk0_phase_shift = "-3000";
endmodule
|
module pll (
inclk0,
c0);
input inclk0;
output c0;
wire [5:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0)
// synopsys translate_off
,
.fbin (),
.pllena (),
.clkswitch (),
.areset (),
.pfdena (),
.clkena (),
.extclkena (),
.scanclk (),
.scanaclr (),
.scandata (),
.scanread (),
.scanwrite (),
.extclk (),
.clkbad (),
.activeclock (),
.locked (),
.clkloss (),
.scandataout (),
.scandone (),
.sclkout1 (),
.sclkout0 (),
.enable0 (),
.enable1 ()
// synopsys translate_on
);
defparam
altpll_component.clk0_duty_cycle = 50,
altpll_component.lpm_type = "altpll",
altpll_component.clk0_multiply_by = 1,
altpll_component.inclk0_input_frequency = 20833,
altpll_component.clk0_divide_by = 1,
altpll_component.pll_type = "AUTO",
altpll_component.clk0_time_delay = "0",
altpll_component.intended_device_family = "Cyclone",
altpll_component.operation_mode = "NORMAL",
altpll_component.compensate_clock = "CLK0",
altpll_component.clk0_phase_shift = "-3000";
endmodule
|
module pll (
inclk0,
c0);
input inclk0;
output c0;
wire [5:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0)
// synopsys translate_off
,
.fbin (),
.pllena (),
.clkswitch (),
.areset (),
.pfdena (),
.clkena (),
.extclkena (),
.scanclk (),
.scanaclr (),
.scandata (),
.scanread (),
.scanwrite (),
.extclk (),
.clkbad (),
.activeclock (),
.locked (),
.clkloss (),
.scandataout (),
.scandone (),
.sclkout1 (),
.sclkout0 (),
.enable0 (),
.enable1 ()
// synopsys translate_on
);
defparam
altpll_component.clk0_duty_cycle = 50,
altpll_component.lpm_type = "altpll",
altpll_component.clk0_multiply_by = 1,
altpll_component.inclk0_input_frequency = 20833,
altpll_component.clk0_divide_by = 1,
altpll_component.pll_type = "AUTO",
altpll_component.clk0_time_delay = "0",
altpll_component.intended_device_family = "Cyclone",
altpll_component.operation_mode = "NORMAL",
altpll_component.compensate_clock = "CLK0",
altpll_component.clk0_phase_shift = "-3000";
endmodule
|
module bustri (
data,
enabledt,
tridata);
input [15:0] data;
input enabledt;
inout [15:0] tridata;
endmodule
|
module bustri (
data,
enabledt,
tridata);
input [15:0] data;
input enabledt;
inout [15:0] tridata;
endmodule
|
module as members of the synchronizer
// to enable automatic metastability MTBF analysis.
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON "} *) reg din_s1;
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg;
//synthesis translate_off
initial begin
if (depth <2) begin
$display("%m: Error: synchronizer length: %0d less than 2.", depth);
end
end
// the first synchronizer register is either a simple D flop for synthesis
// and non-metastable simulation or a D flop with a method to inject random
// metastable events resulting in random delay of [0,1] cycles
`ifdef __ALTERA_STD__METASTABLE_SIM
reg[31:0] RANDOM_SEED = 123456;
wire next_din_s1;
wire dout;
reg din_last;
reg random;
event metastable_event; // hook for debug monitoring
initial begin
$display("%m: Info: Metastable event injection simulation mode enabled");
end
always @(posedge clk) begin
if (reset_n == 0)
random <= $random(RANDOM_SEED);
else
random <= $random;
end
assign next_din_s1 = (din_last ^ din) ? random : din;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_last <= 1'b0;
else
din_last <= din;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b0;
else
din_s1 <= next_din_s1;
end
`else
//synthesis translate_on
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b0;
else
din_s1 <= din;
end
//synthesis translate_off
`endif
`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE
always @(*) begin
if (reset_n && (din_last != din) && (random != din)) begin
$display("%m: Verbose Info: metastable event @ time %t", $time);
->metastable_event;
end
end
`endif
//synthesis translate_on
// the remaining synchronizer registers form a simple shift register
// of length depth-1
generate
if (depth < 3) begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= din_s1;
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= {dreg[depth-3:0], din_s1};
end
end
endgenerate
assign dout = dreg[depth-2];
endmodule
|
module accum32_accum_nta
(
aclr,
clken,
clock,
data,
result) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clken;
input clock;
input [31:0] data;
output [31:0] result;
wire [0:0] wire_acc_cella_0cout;
wire [0:0] wire_acc_cella_1cout;
wire [0:0] wire_acc_cella_2cout;
wire [0:0] wire_acc_cella_3cout;
wire [0:0] wire_acc_cella_4cout;
wire [0:0] wire_acc_cella_5cout;
wire [0:0] wire_acc_cella_6cout;
wire [0:0] wire_acc_cella_7cout;
wire [0:0] wire_acc_cella_8cout;
wire [0:0] wire_acc_cella_9cout;
wire [0:0] wire_acc_cella_10cout;
wire [0:0] wire_acc_cella_11cout;
wire [0:0] wire_acc_cella_12cout;
wire [0:0] wire_acc_cella_13cout;
wire [0:0] wire_acc_cella_14cout;
wire [0:0] wire_acc_cella_15cout;
wire [0:0] wire_acc_cella_16cout;
wire [0:0] wire_acc_cella_17cout;
wire [0:0] wire_acc_cella_18cout;
wire [0:0] wire_acc_cella_19cout;
wire [0:0] wire_acc_cella_20cout;
wire [0:0] wire_acc_cella_21cout;
wire [0:0] wire_acc_cella_22cout;
wire [0:0] wire_acc_cella_23cout;
wire [0:0] wire_acc_cella_24cout;
wire [0:0] wire_acc_cella_25cout;
wire [0:0] wire_acc_cella_26cout;
wire [0:0] wire_acc_cella_27cout;
wire [0:0] wire_acc_cella_28cout;
wire [0:0] wire_acc_cella_29cout;
wire [0:0] wire_acc_cella_30cout;
wire [31:0] wire_acc_cella_dataa;
wire [31:0] wire_acc_cella_datab;
wire [31:0] wire_acc_cella_datac;
wire [31:0] wire_acc_cella_regout;
wire sload;
stratix_lcell acc_cella_0
(
.aclr(aclr),
.cin(1'b0),
.clk(clock),
.cout(wire_acc_cella_0cout[0:0]),
.dataa(wire_acc_cella_dataa[0:0]),
.datab(wire_acc_cella_datab[0:0]),
.datac(wire_acc_cella_datac[0:0]),
.ena(clken),
.regout(wire_acc_cella_regout[0:0]),
.sload(sload));
defparam
acc_cella_0.cin_used = "true",
acc_cella_0.lut_mask = "96e8",
acc_cella_0.operation_mode = "arithmetic",
acc_cella_0.sum_lutc_input = "cin",
acc_cella_0.synch_mode = "on",
acc_cella_0.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_1
(
.aclr(aclr),
.cin(wire_acc_cella_0cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_1cout[0:0]),
.dataa(wire_acc_cella_dataa[1:1]),
.datab(wire_acc_cella_datab[1:1]),
.datac(wire_acc_cella_datac[1:1]),
.ena(clken),
.regout(wire_acc_cella_regout[1:1]),
.sload(sload));
defparam
acc_cella_1.cin_used = "true",
acc_cella_1.lut_mask = "96e8",
acc_cella_1.operation_mode = "arithmetic",
acc_cella_1.sum_lutc_input = "cin",
acc_cella_1.synch_mode = "on",
acc_cella_1.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_2
(
.aclr(aclr),
.cin(wire_acc_cella_1cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_2cout[0:0]),
.dataa(wire_acc_cella_dataa[2:2]),
.datab(wire_acc_cella_datab[2:2]),
.datac(wire_acc_cella_datac[2:2]),
.ena(clken),
.regout(wire_acc_cella_regout[2:2]),
.sload(sload));
defparam
acc_cella_2.cin_used = "true",
acc_cella_2.lut_mask = "96e8",
acc_cella_2.operation_mode = "arithmetic",
acc_cella_2.sum_lutc_input = "cin",
acc_cella_2.synch_mode = "on",
acc_cella_2.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_3
(
.aclr(aclr),
.cin(wire_acc_cella_2cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_3cout[0:0]),
.dataa(wire_acc_cella_dataa[3:3]),
.datab(wire_acc_cella_datab[3:3]),
.datac(wire_acc_cella_datac[3:3]),
.ena(clken),
.regout(wire_acc_cella_regout[3:3]),
.sload(sload));
defparam
acc_cella_3.cin_used = "true",
acc_cella_3.lut_mask = "96e8",
acc_cella_3.operation_mode = "arithmetic",
acc_cella_3.sum_lutc_input = "cin",
acc_cella_3.synch_mode = "on",
acc_cella_3.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_4
(
.aclr(aclr),
.cin(wire_acc_cella_3cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_4cout[0:0]),
.dataa(wire_acc_cella_dataa[4:4]),
.datab(wire_acc_cella_datab[4:4]),
.datac(wire_acc_cella_datac[4:4]),
.ena(clken),
.regout(wire_acc_cella_regout[4:4]),
.sload(sload));
defparam
acc_cella_4.cin_used = "true",
acc_cella_4.lut_mask = "96e8",
acc_cella_4.operation_mode = "arithmetic",
acc_cella_4.sum_lutc_input = "cin",
acc_cella_4.synch_mode = "on",
acc_cella_4.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_5
(
.aclr(aclr),
.cin(wire_acc_cella_4cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_5cout[0:0]),
.dataa(wire_acc_cella_dataa[5:5]),
.datab(wire_acc_cella_datab[5:5]),
.datac(wire_acc_cella_datac[5:5]),
.ena(clken),
.regout(wire_acc_cella_regout[5:5]),
.sload(sload));
defparam
acc_cella_5.cin_used = "true",
acc_cella_5.lut_mask = "96e8",
acc_cella_5.operation_mode = "arithmetic",
acc_cella_5.sum_lutc_input = "cin",
acc_cella_5.synch_mode = "on",
acc_cella_5.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_6
(
.aclr(aclr),
.cin(wire_acc_cella_5cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_6cout[0:0]),
.dataa(wire_acc_cella_dataa[6:6]),
.datab(wire_acc_cella_datab[6:6]),
.datac(wire_acc_cella_datac[6:6]),
.ena(clken),
.regout(wire_acc_cella_regout[6:6]),
.sload(sload));
defparam
acc_cella_6.cin_used = "true",
acc_cella_6.lut_mask = "96e8",
acc_cella_6.operation_mode = "arithmetic",
acc_cella_6.sum_lutc_input = "cin",
acc_cella_6.synch_mode = "on",
acc_cella_6.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_7
(
.aclr(aclr),
.cin(wire_acc_cella_6cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_7cout[0:0]),
.dataa(wire_acc_cella_dataa[7:7]),
.datab(wire_acc_cella_datab[7:7]),
.datac(wire_acc_cella_datac[7:7]),
.ena(clken),
.regout(wire_acc_cella_regout[7:7]),
.sload(sload));
defparam
acc_cella_7.cin_used = "true",
acc_cella_7.lut_mask = "96e8",
acc_cella_7.operation_mode = "arithmetic",
acc_cella_7.sum_lutc_input = "cin",
acc_cella_7.synch_mode = "on",
acc_cella_7.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_8
(
.aclr(aclr),
.cin(wire_acc_cella_7cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_8cout[0:0]),
.dataa(wire_acc_cella_dataa[8:8]),
.datab(wire_acc_cella_datab[8:8]),
.datac(wire_acc_cella_datac[8:8]),
.ena(clken),
.regout(wire_acc_cella_regout[8:8]),
.sload(sload));
defparam
acc_cella_8.cin_used = "true",
acc_cella_8.lut_mask = "96e8",
acc_cella_8.operation_mode = "arithmetic",
acc_cella_8.sum_lutc_input = "cin",
acc_cella_8.synch_mode = "on",
acc_cella_8.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_9
(
.aclr(aclr),
.cin(wire_acc_cella_8cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_9cout[0:0]),
.dataa(wire_acc_cella_dataa[9:9]),
.datab(wire_acc_cella_datab[9:9]),
.datac(wire_acc_cella_datac[9:9]),
.ena(clken),
.regout(wire_acc_cella_regout[9:9]),
.sload(sload));
defparam
acc_cella_9.cin_used = "true",
acc_cella_9.lut_mask = "96e8",
acc_cella_9.operation_mode = "arithmetic",
acc_cella_9.sum_lutc_input = "cin",
acc_cella_9.synch_mode = "on",
acc_cella_9.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_10
(
.aclr(aclr),
.cin(wire_acc_cella_9cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_10cout[0:0]),
.dataa(wire_acc_cella_dataa[10:10]),
.datab(wire_acc_cella_datab[10:10]),
.datac(wire_acc_cella_datac[10:10]),
.ena(clken),
.regout(wire_acc_cella_regout[10:10]),
.sload(sload));
defparam
acc_cella_10.cin_used = "true",
acc_cella_10.lut_mask = "96e8",
acc_cella_10.operation_mode = "arithmetic",
acc_cella_10.sum_lutc_input = "cin",
acc_cella_10.synch_mode = "on",
acc_cella_10.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_11
(
.aclr(aclr),
.cin(wire_acc_cella_10cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_11cout[0:0]),
.dataa(wire_acc_cella_dataa[11:11]),
.datab(wire_acc_cella_datab[11:11]),
.datac(wire_acc_cella_datac[11:11]),
.ena(clken),
.regout(wire_acc_cella_regout[11:11]),
.sload(sload));
defparam
acc_cella_11.cin_used = "true",
acc_cella_11.lut_mask = "96e8",
acc_cella_11.operation_mode = "arithmetic",
acc_cella_11.sum_lutc_input = "cin",
acc_cella_11.synch_mode = "on",
acc_cella_11.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_12
(
.aclr(aclr),
.cin(wire_acc_cella_11cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_12cout[0:0]),
.dataa(wire_acc_cella_dataa[12:12]),
.datab(wire_acc_cella_datab[12:12]),
.datac(wire_acc_cella_datac[12:12]),
.ena(clken),
.regout(wire_acc_cella_regout[12:12]),
.sload(sload));
defparam
acc_cella_12.cin_used = "true",
acc_cella_12.lut_mask = "96e8",
acc_cella_12.operation_mode = "arithmetic",
acc_cella_12.sum_lutc_input = "cin",
acc_cella_12.synch_mode = "on",
acc_cella_12.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_13
(
.aclr(aclr),
.cin(wire_acc_cella_12cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_13cout[0:0]),
.dataa(wire_acc_cella_dataa[13:13]),
.datab(wire_acc_cella_datab[13:13]),
.datac(wire_acc_cella_datac[13:13]),
.ena(clken),
.regout(wire_acc_cella_regout[13:13]),
.sload(sload));
defparam
acc_cella_13.cin_used = "true",
acc_cella_13.lut_mask = "96e8",
acc_cella_13.operation_mode = "arithmetic",
acc_cella_13.sum_lutc_input = "cin",
acc_cella_13.synch_mode = "on",
acc_cella_13.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_14
(
.aclr(aclr),
.cin(wire_acc_cella_13cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_14cout[0:0]),
.dataa(wire_acc_cella_dataa[14:14]),
.datab(wire_acc_cella_datab[14:14]),
.datac(wire_acc_cella_datac[14:14]),
.ena(clken),
.regout(wire_acc_cella_regout[14:14]),
.sload(sload));
defparam
acc_cella_14.cin_used = "true",
acc_cella_14.lut_mask = "96e8",
acc_cella_14.operation_mode = "arithmetic",
acc_cella_14.sum_lutc_input = "cin",
acc_cella_14.synch_mode = "on",
acc_cella_14.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_15
(
.aclr(aclr),
.cin(wire_acc_cella_14cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_15cout[0:0]),
.dataa(wire_acc_cella_dataa[15:15]),
.datab(wire_acc_cella_datab[15:15]),
.datac(wire_acc_cella_datac[15:15]),
.ena(clken),
.regout(wire_acc_cella_regout[15:15]),
.sload(sload));
defparam
acc_cella_15.cin_used = "true",
acc_cella_15.lut_mask = "96e8",
acc_cella_15.operation_mode = "arithmetic",
acc_cella_15.sum_lutc_input = "cin",
acc_cella_15.synch_mode = "on",
acc_cella_15.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_16
(
.aclr(aclr),
.cin(wire_acc_cella_15cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_16cout[0:0]),
.dataa(wire_acc_cella_dataa[16:16]),
.datab(wire_acc_cella_datab[16:16]),
.datac(wire_acc_cella_datac[16:16]),
.ena(clken),
.regout(wire_acc_cella_regout[16:16]),
.sload(sload));
defparam
acc_cella_16.cin_used = "true",
acc_cella_16.lut_mask = "96e8",
acc_cella_16.operation_mode = "arithmetic",
acc_cella_16.sum_lutc_input = "cin",
acc_cella_16.synch_mode = "on",
acc_cella_16.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_17
(
.aclr(aclr),
.cin(wire_acc_cella_16cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_17cout[0:0]),
.dataa(wire_acc_cella_dataa[17:17]),
.datab(wire_acc_cella_datab[17:17]),
.datac(wire_acc_cella_datac[17:17]),
.ena(clken),
.regout(wire_acc_cella_regout[17:17]),
.sload(sload));
defparam
acc_cella_17.cin_used = "true",
acc_cella_17.lut_mask = "96e8",
acc_cella_17.operation_mode = "arithmetic",
acc_cella_17.sum_lutc_input = "cin",
acc_cella_17.synch_mode = "on",
acc_cella_17.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_18
(
.aclr(aclr),
.cin(wire_acc_cella_17cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_18cout[0:0]),
.dataa(wire_acc_cella_dataa[18:18]),
.datab(wire_acc_cella_datab[18:18]),
.datac(wire_acc_cella_datac[18:18]),
.ena(clken),
.regout(wire_acc_cella_regout[18:18]),
.sload(sload));
defparam
acc_cella_18.cin_used = "true",
acc_cella_18.lut_mask = "96e8",
acc_cella_18.operation_mode = "arithmetic",
acc_cella_18.sum_lutc_input = "cin",
acc_cella_18.synch_mode = "on",
acc_cella_18.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_19
(
.aclr(aclr),
.cin(wire_acc_cella_18cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_19cout[0:0]),
.dataa(wire_acc_cella_dataa[19:19]),
.datab(wire_acc_cella_datab[19:19]),
.datac(wire_acc_cella_datac[19:19]),
.ena(clken),
.regout(wire_acc_cella_regout[19:19]),
.sload(sload));
defparam
acc_cella_19.cin_used = "true",
acc_cella_19.lut_mask = "96e8",
acc_cella_19.operation_mode = "arithmetic",
acc_cella_19.sum_lutc_input = "cin",
acc_cella_19.synch_mode = "on",
acc_cella_19.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_20
(
.aclr(aclr),
.cin(wire_acc_cella_19cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_20cout[0:0]),
.dataa(wire_acc_cella_dataa[20:20]),
.datab(wire_acc_cella_datab[20:20]),
.datac(wire_acc_cella_datac[20:20]),
.ena(clken),
.regout(wire_acc_cella_regout[20:20]),
.sload(sload));
defparam
acc_cella_20.cin_used = "true",
acc_cella_20.lut_mask = "96e8",
acc_cella_20.operation_mode = "arithmetic",
acc_cella_20.sum_lutc_input = "cin",
acc_cella_20.synch_mode = "on",
acc_cella_20.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_21
(
.aclr(aclr),
.cin(wire_acc_cella_20cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_21cout[0:0]),
.dataa(wire_acc_cella_dataa[21:21]),
.datab(wire_acc_cella_datab[21:21]),
.datac(wire_acc_cella_datac[21:21]),
.ena(clken),
.regout(wire_acc_cella_regout[21:21]),
.sload(sload));
defparam
acc_cella_21.cin_used = "true",
acc_cella_21.lut_mask = "96e8",
acc_cella_21.operation_mode = "arithmetic",
acc_cella_21.sum_lutc_input = "cin",
acc_cella_21.synch_mode = "on",
acc_cella_21.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_22
(
.aclr(aclr),
.cin(wire_acc_cella_21cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_22cout[0:0]),
.dataa(wire_acc_cella_dataa[22:22]),
.datab(wire_acc_cella_datab[22:22]),
.datac(wire_acc_cella_datac[22:22]),
.ena(clken),
.regout(wire_acc_cella_regout[22:22]),
.sload(sload));
defparam
acc_cella_22.cin_used = "true",
acc_cella_22.lut_mask = "96e8",
acc_cella_22.operation_mode = "arithmetic",
acc_cella_22.sum_lutc_input = "cin",
acc_cella_22.synch_mode = "on",
acc_cella_22.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_23
(
.aclr(aclr),
.cin(wire_acc_cella_22cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_23cout[0:0]),
.dataa(wire_acc_cella_dataa[23:23]),
.datab(wire_acc_cella_datab[23:23]),
.datac(wire_acc_cella_datac[23:23]),
.ena(clken),
.regout(wire_acc_cella_regout[23:23]),
.sload(sload));
defparam
acc_cella_23.cin_used = "true",
acc_cella_23.lut_mask = "96e8",
acc_cella_23.operation_mode = "arithmetic",
acc_cella_23.sum_lutc_input = "cin",
acc_cella_23.synch_mode = "on",
acc_cella_23.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_24
(
.aclr(aclr),
.cin(wire_acc_cella_23cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_24cout[0:0]),
.dataa(wire_acc_cella_dataa[24:24]),
.datab(wire_acc_cella_datab[24:24]),
.datac(wire_acc_cella_datac[24:24]),
.ena(clken),
.regout(wire_acc_cella_regout[24:24]),
.sload(sload));
defparam
acc_cella_24.cin_used = "true",
acc_cella_24.lut_mask = "96e8",
acc_cella_24.operation_mode = "arithmetic",
acc_cella_24.sum_lutc_input = "cin",
acc_cella_24.synch_mode = "on",
acc_cella_24.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_25
(
.aclr(aclr),
.cin(wire_acc_cella_24cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_25cout[0:0]),
.dataa(wire_acc_cella_dataa[25:25]),
.datab(wire_acc_cella_datab[25:25]),
.datac(wire_acc_cella_datac[25:25]),
.ena(clken),
.regout(wire_acc_cella_regout[25:25]),
.sload(sload));
defparam
acc_cella_25.cin_used = "true",
acc_cella_25.lut_mask = "96e8",
acc_cella_25.operation_mode = "arithmetic",
acc_cella_25.sum_lutc_input = "cin",
acc_cella_25.synch_mode = "on",
acc_cella_25.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_26
(
.aclr(aclr),
.cin(wire_acc_cella_25cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_26cout[0:0]),
.dataa(wire_acc_cella_dataa[26:26]),
.datab(wire_acc_cella_datab[26:26]),
.datac(wire_acc_cella_datac[26:26]),
.ena(clken),
.regout(wire_acc_cella_regout[26:26]),
.sload(sload));
defparam
acc_cella_26.cin_used = "true",
acc_cella_26.lut_mask = "96e8",
acc_cella_26.operation_mode = "arithmetic",
acc_cella_26.sum_lutc_input = "cin",
acc_cella_26.synch_mode = "on",
acc_cella_26.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_27
(
.aclr(aclr),
.cin(wire_acc_cella_26cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_27cout[0:0]),
.dataa(wire_acc_cella_dataa[27:27]),
.datab(wire_acc_cella_datab[27:27]),
.datac(wire_acc_cella_datac[27:27]),
.ena(clken),
.regout(wire_acc_cella_regout[27:27]),
.sload(sload));
defparam
acc_cella_27.cin_used = "true",
acc_cella_27.lut_mask = "96e8",
acc_cella_27.operation_mode = "arithmetic",
acc_cella_27.sum_lutc_input = "cin",
acc_cella_27.synch_mode = "on",
acc_cella_27.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_28
(
.aclr(aclr),
.cin(wire_acc_cella_27cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_28cout[0:0]),
.dataa(wire_acc_cella_dataa[28:28]),
.datab(wire_acc_cella_datab[28:28]),
.datac(wire_acc_cella_datac[28:28]),
.ena(clken),
.regout(wire_acc_cella_regout[28:28]),
.sload(sload));
defparam
acc_cella_28.cin_used = "true",
acc_cella_28.lut_mask = "96e8",
acc_cella_28.operation_mode = "arithmetic",
acc_cella_28.sum_lutc_input = "cin",
acc_cella_28.synch_mode = "on",
acc_cella_28.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_29
(
.aclr(aclr),
.cin(wire_acc_cella_28cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_29cout[0:0]),
.dataa(wire_acc_cella_dataa[29:29]),
.datab(wire_acc_cella_datab[29:29]),
.datac(wire_acc_cella_datac[29:29]),
.ena(clken),
.regout(wire_acc_cella_regout[29:29]),
.sload(sload));
defparam
acc_cella_29.cin_used = "true",
acc_cella_29.lut_mask = "96e8",
acc_cella_29.operation_mode = "arithmetic",
acc_cella_29.sum_lutc_input = "cin",
acc_cella_29.synch_mode = "on",
acc_cella_29.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_30
(
.aclr(aclr),
.cin(wire_acc_cella_29cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_30cout[0:0]),
.dataa(wire_acc_cella_dataa[30:30]),
.datab(wire_acc_cella_datab[30:30]),
.datac(wire_acc_cella_datac[30:30]),
.ena(clken),
.regout(wire_acc_cella_regout[30:30]),
.sload(sload));
defparam
acc_cella_30.cin_used = "true",
acc_cella_30.lut_mask = "96e8",
acc_cella_30.operation_mode = "arithmetic",
acc_cella_30.sum_lutc_input = "cin",
acc_cella_30.synch_mode = "on",
acc_cella_30.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_31
(
.aclr(aclr),
.cin(wire_acc_cella_30cout[0:0]),
.clk(clock),
.dataa(wire_acc_cella_dataa[31:31]),
.datab(wire_acc_cella_datab[31:31]),
.datac(wire_acc_cella_datac[31:31]),
.ena(clken),
.regout(wire_acc_cella_regout[31:31]),
.sload(sload));
defparam
acc_cella_31.cin_used = "true",
acc_cella_31.lut_mask = "9696",
acc_cella_31.operation_mode = "normal",
acc_cella_31.sum_lutc_input = "cin",
acc_cella_31.synch_mode = "on",
acc_cella_31.lpm_type = "stratix_lcell";
assign
wire_acc_cella_dataa = data,
wire_acc_cella_datab = wire_acc_cella_regout,
wire_acc_cella_datac = data;
assign
result = wire_acc_cella_regout,
sload = 1'b0;
endmodule
|
module accum32 (
data,
clock,
clken,
aclr,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] data;
input clock;
input clken;
input aclr;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
accum32_accum_nta accum32_accum_nta_component (
.clken (clken),
.aclr (aclr),
.clock (clock),
.data (data),
.result (sub_wire0));
endmodule
|
module accum32_accum_nta
(
aclr,
clken,
clock,
data,
result) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clken;
input clock;
input [31:0] data;
output [31:0] result;
wire [0:0] wire_acc_cella_0cout;
wire [0:0] wire_acc_cella_1cout;
wire [0:0] wire_acc_cella_2cout;
wire [0:0] wire_acc_cella_3cout;
wire [0:0] wire_acc_cella_4cout;
wire [0:0] wire_acc_cella_5cout;
wire [0:0] wire_acc_cella_6cout;
wire [0:0] wire_acc_cella_7cout;
wire [0:0] wire_acc_cella_8cout;
wire [0:0] wire_acc_cella_9cout;
wire [0:0] wire_acc_cella_10cout;
wire [0:0] wire_acc_cella_11cout;
wire [0:0] wire_acc_cella_12cout;
wire [0:0] wire_acc_cella_13cout;
wire [0:0] wire_acc_cella_14cout;
wire [0:0] wire_acc_cella_15cout;
wire [0:0] wire_acc_cella_16cout;
wire [0:0] wire_acc_cella_17cout;
wire [0:0] wire_acc_cella_18cout;
wire [0:0] wire_acc_cella_19cout;
wire [0:0] wire_acc_cella_20cout;
wire [0:0] wire_acc_cella_21cout;
wire [0:0] wire_acc_cella_22cout;
wire [0:0] wire_acc_cella_23cout;
wire [0:0] wire_acc_cella_24cout;
wire [0:0] wire_acc_cella_25cout;
wire [0:0] wire_acc_cella_26cout;
wire [0:0] wire_acc_cella_27cout;
wire [0:0] wire_acc_cella_28cout;
wire [0:0] wire_acc_cella_29cout;
wire [0:0] wire_acc_cella_30cout;
wire [31:0] wire_acc_cella_dataa;
wire [31:0] wire_acc_cella_datab;
wire [31:0] wire_acc_cella_datac;
wire [31:0] wire_acc_cella_regout;
wire sload;
stratix_lcell acc_cella_0
(
.aclr(aclr),
.cin(1'b0),
.clk(clock),
.cout(wire_acc_cella_0cout[0:0]),
.dataa(wire_acc_cella_dataa[0:0]),
.datab(wire_acc_cella_datab[0:0]),
.datac(wire_acc_cella_datac[0:0]),
.ena(clken),
.regout(wire_acc_cella_regout[0:0]),
.sload(sload));
defparam
acc_cella_0.cin_used = "true",
acc_cella_0.lut_mask = "96e8",
acc_cella_0.operation_mode = "arithmetic",
acc_cella_0.sum_lutc_input = "cin",
acc_cella_0.synch_mode = "on",
acc_cella_0.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_1
(
.aclr(aclr),
.cin(wire_acc_cella_0cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_1cout[0:0]),
.dataa(wire_acc_cella_dataa[1:1]),
.datab(wire_acc_cella_datab[1:1]),
.datac(wire_acc_cella_datac[1:1]),
.ena(clken),
.regout(wire_acc_cella_regout[1:1]),
.sload(sload));
defparam
acc_cella_1.cin_used = "true",
acc_cella_1.lut_mask = "96e8",
acc_cella_1.operation_mode = "arithmetic",
acc_cella_1.sum_lutc_input = "cin",
acc_cella_1.synch_mode = "on",
acc_cella_1.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_2
(
.aclr(aclr),
.cin(wire_acc_cella_1cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_2cout[0:0]),
.dataa(wire_acc_cella_dataa[2:2]),
.datab(wire_acc_cella_datab[2:2]),
.datac(wire_acc_cella_datac[2:2]),
.ena(clken),
.regout(wire_acc_cella_regout[2:2]),
.sload(sload));
defparam
acc_cella_2.cin_used = "true",
acc_cella_2.lut_mask = "96e8",
acc_cella_2.operation_mode = "arithmetic",
acc_cella_2.sum_lutc_input = "cin",
acc_cella_2.synch_mode = "on",
acc_cella_2.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_3
(
.aclr(aclr),
.cin(wire_acc_cella_2cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_3cout[0:0]),
.dataa(wire_acc_cella_dataa[3:3]),
.datab(wire_acc_cella_datab[3:3]),
.datac(wire_acc_cella_datac[3:3]),
.ena(clken),
.regout(wire_acc_cella_regout[3:3]),
.sload(sload));
defparam
acc_cella_3.cin_used = "true",
acc_cella_3.lut_mask = "96e8",
acc_cella_3.operation_mode = "arithmetic",
acc_cella_3.sum_lutc_input = "cin",
acc_cella_3.synch_mode = "on",
acc_cella_3.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_4
(
.aclr(aclr),
.cin(wire_acc_cella_3cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_4cout[0:0]),
.dataa(wire_acc_cella_dataa[4:4]),
.datab(wire_acc_cella_datab[4:4]),
.datac(wire_acc_cella_datac[4:4]),
.ena(clken),
.regout(wire_acc_cella_regout[4:4]),
.sload(sload));
defparam
acc_cella_4.cin_used = "true",
acc_cella_4.lut_mask = "96e8",
acc_cella_4.operation_mode = "arithmetic",
acc_cella_4.sum_lutc_input = "cin",
acc_cella_4.synch_mode = "on",
acc_cella_4.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_5
(
.aclr(aclr),
.cin(wire_acc_cella_4cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_5cout[0:0]),
.dataa(wire_acc_cella_dataa[5:5]),
.datab(wire_acc_cella_datab[5:5]),
.datac(wire_acc_cella_datac[5:5]),
.ena(clken),
.regout(wire_acc_cella_regout[5:5]),
.sload(sload));
defparam
acc_cella_5.cin_used = "true",
acc_cella_5.lut_mask = "96e8",
acc_cella_5.operation_mode = "arithmetic",
acc_cella_5.sum_lutc_input = "cin",
acc_cella_5.synch_mode = "on",
acc_cella_5.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_6
(
.aclr(aclr),
.cin(wire_acc_cella_5cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_6cout[0:0]),
.dataa(wire_acc_cella_dataa[6:6]),
.datab(wire_acc_cella_datab[6:6]),
.datac(wire_acc_cella_datac[6:6]),
.ena(clken),
.regout(wire_acc_cella_regout[6:6]),
.sload(sload));
defparam
acc_cella_6.cin_used = "true",
acc_cella_6.lut_mask = "96e8",
acc_cella_6.operation_mode = "arithmetic",
acc_cella_6.sum_lutc_input = "cin",
acc_cella_6.synch_mode = "on",
acc_cella_6.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_7
(
.aclr(aclr),
.cin(wire_acc_cella_6cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_7cout[0:0]),
.dataa(wire_acc_cella_dataa[7:7]),
.datab(wire_acc_cella_datab[7:7]),
.datac(wire_acc_cella_datac[7:7]),
.ena(clken),
.regout(wire_acc_cella_regout[7:7]),
.sload(sload));
defparam
acc_cella_7.cin_used = "true",
acc_cella_7.lut_mask = "96e8",
acc_cella_7.operation_mode = "arithmetic",
acc_cella_7.sum_lutc_input = "cin",
acc_cella_7.synch_mode = "on",
acc_cella_7.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_8
(
.aclr(aclr),
.cin(wire_acc_cella_7cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_8cout[0:0]),
.dataa(wire_acc_cella_dataa[8:8]),
.datab(wire_acc_cella_datab[8:8]),
.datac(wire_acc_cella_datac[8:8]),
.ena(clken),
.regout(wire_acc_cella_regout[8:8]),
.sload(sload));
defparam
acc_cella_8.cin_used = "true",
acc_cella_8.lut_mask = "96e8",
acc_cella_8.operation_mode = "arithmetic",
acc_cella_8.sum_lutc_input = "cin",
acc_cella_8.synch_mode = "on",
acc_cella_8.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_9
(
.aclr(aclr),
.cin(wire_acc_cella_8cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_9cout[0:0]),
.dataa(wire_acc_cella_dataa[9:9]),
.datab(wire_acc_cella_datab[9:9]),
.datac(wire_acc_cella_datac[9:9]),
.ena(clken),
.regout(wire_acc_cella_regout[9:9]),
.sload(sload));
defparam
acc_cella_9.cin_used = "true",
acc_cella_9.lut_mask = "96e8",
acc_cella_9.operation_mode = "arithmetic",
acc_cella_9.sum_lutc_input = "cin",
acc_cella_9.synch_mode = "on",
acc_cella_9.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_10
(
.aclr(aclr),
.cin(wire_acc_cella_9cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_10cout[0:0]),
.dataa(wire_acc_cella_dataa[10:10]),
.datab(wire_acc_cella_datab[10:10]),
.datac(wire_acc_cella_datac[10:10]),
.ena(clken),
.regout(wire_acc_cella_regout[10:10]),
.sload(sload));
defparam
acc_cella_10.cin_used = "true",
acc_cella_10.lut_mask = "96e8",
acc_cella_10.operation_mode = "arithmetic",
acc_cella_10.sum_lutc_input = "cin",
acc_cella_10.synch_mode = "on",
acc_cella_10.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_11
(
.aclr(aclr),
.cin(wire_acc_cella_10cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_11cout[0:0]),
.dataa(wire_acc_cella_dataa[11:11]),
.datab(wire_acc_cella_datab[11:11]),
.datac(wire_acc_cella_datac[11:11]),
.ena(clken),
.regout(wire_acc_cella_regout[11:11]),
.sload(sload));
defparam
acc_cella_11.cin_used = "true",
acc_cella_11.lut_mask = "96e8",
acc_cella_11.operation_mode = "arithmetic",
acc_cella_11.sum_lutc_input = "cin",
acc_cella_11.synch_mode = "on",
acc_cella_11.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_12
(
.aclr(aclr),
.cin(wire_acc_cella_11cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_12cout[0:0]),
.dataa(wire_acc_cella_dataa[12:12]),
.datab(wire_acc_cella_datab[12:12]),
.datac(wire_acc_cella_datac[12:12]),
.ena(clken),
.regout(wire_acc_cella_regout[12:12]),
.sload(sload));
defparam
acc_cella_12.cin_used = "true",
acc_cella_12.lut_mask = "96e8",
acc_cella_12.operation_mode = "arithmetic",
acc_cella_12.sum_lutc_input = "cin",
acc_cella_12.synch_mode = "on",
acc_cella_12.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_13
(
.aclr(aclr),
.cin(wire_acc_cella_12cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_13cout[0:0]),
.dataa(wire_acc_cella_dataa[13:13]),
.datab(wire_acc_cella_datab[13:13]),
.datac(wire_acc_cella_datac[13:13]),
.ena(clken),
.regout(wire_acc_cella_regout[13:13]),
.sload(sload));
defparam
acc_cella_13.cin_used = "true",
acc_cella_13.lut_mask = "96e8",
acc_cella_13.operation_mode = "arithmetic",
acc_cella_13.sum_lutc_input = "cin",
acc_cella_13.synch_mode = "on",
acc_cella_13.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_14
(
.aclr(aclr),
.cin(wire_acc_cella_13cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_14cout[0:0]),
.dataa(wire_acc_cella_dataa[14:14]),
.datab(wire_acc_cella_datab[14:14]),
.datac(wire_acc_cella_datac[14:14]),
.ena(clken),
.regout(wire_acc_cella_regout[14:14]),
.sload(sload));
defparam
acc_cella_14.cin_used = "true",
acc_cella_14.lut_mask = "96e8",
acc_cella_14.operation_mode = "arithmetic",
acc_cella_14.sum_lutc_input = "cin",
acc_cella_14.synch_mode = "on",
acc_cella_14.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_15
(
.aclr(aclr),
.cin(wire_acc_cella_14cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_15cout[0:0]),
.dataa(wire_acc_cella_dataa[15:15]),
.datab(wire_acc_cella_datab[15:15]),
.datac(wire_acc_cella_datac[15:15]),
.ena(clken),
.regout(wire_acc_cella_regout[15:15]),
.sload(sload));
defparam
acc_cella_15.cin_used = "true",
acc_cella_15.lut_mask = "96e8",
acc_cella_15.operation_mode = "arithmetic",
acc_cella_15.sum_lutc_input = "cin",
acc_cella_15.synch_mode = "on",
acc_cella_15.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_16
(
.aclr(aclr),
.cin(wire_acc_cella_15cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_16cout[0:0]),
.dataa(wire_acc_cella_dataa[16:16]),
.datab(wire_acc_cella_datab[16:16]),
.datac(wire_acc_cella_datac[16:16]),
.ena(clken),
.regout(wire_acc_cella_regout[16:16]),
.sload(sload));
defparam
acc_cella_16.cin_used = "true",
acc_cella_16.lut_mask = "96e8",
acc_cella_16.operation_mode = "arithmetic",
acc_cella_16.sum_lutc_input = "cin",
acc_cella_16.synch_mode = "on",
acc_cella_16.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_17
(
.aclr(aclr),
.cin(wire_acc_cella_16cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_17cout[0:0]),
.dataa(wire_acc_cella_dataa[17:17]),
.datab(wire_acc_cella_datab[17:17]),
.datac(wire_acc_cella_datac[17:17]),
.ena(clken),
.regout(wire_acc_cella_regout[17:17]),
.sload(sload));
defparam
acc_cella_17.cin_used = "true",
acc_cella_17.lut_mask = "96e8",
acc_cella_17.operation_mode = "arithmetic",
acc_cella_17.sum_lutc_input = "cin",
acc_cella_17.synch_mode = "on",
acc_cella_17.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_18
(
.aclr(aclr),
.cin(wire_acc_cella_17cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_18cout[0:0]),
.dataa(wire_acc_cella_dataa[18:18]),
.datab(wire_acc_cella_datab[18:18]),
.datac(wire_acc_cella_datac[18:18]),
.ena(clken),
.regout(wire_acc_cella_regout[18:18]),
.sload(sload));
defparam
acc_cella_18.cin_used = "true",
acc_cella_18.lut_mask = "96e8",
acc_cella_18.operation_mode = "arithmetic",
acc_cella_18.sum_lutc_input = "cin",
acc_cella_18.synch_mode = "on",
acc_cella_18.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_19
(
.aclr(aclr),
.cin(wire_acc_cella_18cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_19cout[0:0]),
.dataa(wire_acc_cella_dataa[19:19]),
.datab(wire_acc_cella_datab[19:19]),
.datac(wire_acc_cella_datac[19:19]),
.ena(clken),
.regout(wire_acc_cella_regout[19:19]),
.sload(sload));
defparam
acc_cella_19.cin_used = "true",
acc_cella_19.lut_mask = "96e8",
acc_cella_19.operation_mode = "arithmetic",
acc_cella_19.sum_lutc_input = "cin",
acc_cella_19.synch_mode = "on",
acc_cella_19.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_20
(
.aclr(aclr),
.cin(wire_acc_cella_19cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_20cout[0:0]),
.dataa(wire_acc_cella_dataa[20:20]),
.datab(wire_acc_cella_datab[20:20]),
.datac(wire_acc_cella_datac[20:20]),
.ena(clken),
.regout(wire_acc_cella_regout[20:20]),
.sload(sload));
defparam
acc_cella_20.cin_used = "true",
acc_cella_20.lut_mask = "96e8",
acc_cella_20.operation_mode = "arithmetic",
acc_cella_20.sum_lutc_input = "cin",
acc_cella_20.synch_mode = "on",
acc_cella_20.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_21
(
.aclr(aclr),
.cin(wire_acc_cella_20cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_21cout[0:0]),
.dataa(wire_acc_cella_dataa[21:21]),
.datab(wire_acc_cella_datab[21:21]),
.datac(wire_acc_cella_datac[21:21]),
.ena(clken),
.regout(wire_acc_cella_regout[21:21]),
.sload(sload));
defparam
acc_cella_21.cin_used = "true",
acc_cella_21.lut_mask = "96e8",
acc_cella_21.operation_mode = "arithmetic",
acc_cella_21.sum_lutc_input = "cin",
acc_cella_21.synch_mode = "on",
acc_cella_21.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_22
(
.aclr(aclr),
.cin(wire_acc_cella_21cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_22cout[0:0]),
.dataa(wire_acc_cella_dataa[22:22]),
.datab(wire_acc_cella_datab[22:22]),
.datac(wire_acc_cella_datac[22:22]),
.ena(clken),
.regout(wire_acc_cella_regout[22:22]),
.sload(sload));
defparam
acc_cella_22.cin_used = "true",
acc_cella_22.lut_mask = "96e8",
acc_cella_22.operation_mode = "arithmetic",
acc_cella_22.sum_lutc_input = "cin",
acc_cella_22.synch_mode = "on",
acc_cella_22.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_23
(
.aclr(aclr),
.cin(wire_acc_cella_22cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_23cout[0:0]),
.dataa(wire_acc_cella_dataa[23:23]),
.datab(wire_acc_cella_datab[23:23]),
.datac(wire_acc_cella_datac[23:23]),
.ena(clken),
.regout(wire_acc_cella_regout[23:23]),
.sload(sload));
defparam
acc_cella_23.cin_used = "true",
acc_cella_23.lut_mask = "96e8",
acc_cella_23.operation_mode = "arithmetic",
acc_cella_23.sum_lutc_input = "cin",
acc_cella_23.synch_mode = "on",
acc_cella_23.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_24
(
.aclr(aclr),
.cin(wire_acc_cella_23cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_24cout[0:0]),
.dataa(wire_acc_cella_dataa[24:24]),
.datab(wire_acc_cella_datab[24:24]),
.datac(wire_acc_cella_datac[24:24]),
.ena(clken),
.regout(wire_acc_cella_regout[24:24]),
.sload(sload));
defparam
acc_cella_24.cin_used = "true",
acc_cella_24.lut_mask = "96e8",
acc_cella_24.operation_mode = "arithmetic",
acc_cella_24.sum_lutc_input = "cin",
acc_cella_24.synch_mode = "on",
acc_cella_24.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_25
(
.aclr(aclr),
.cin(wire_acc_cella_24cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_25cout[0:0]),
.dataa(wire_acc_cella_dataa[25:25]),
.datab(wire_acc_cella_datab[25:25]),
.datac(wire_acc_cella_datac[25:25]),
.ena(clken),
.regout(wire_acc_cella_regout[25:25]),
.sload(sload));
defparam
acc_cella_25.cin_used = "true",
acc_cella_25.lut_mask = "96e8",
acc_cella_25.operation_mode = "arithmetic",
acc_cella_25.sum_lutc_input = "cin",
acc_cella_25.synch_mode = "on",
acc_cella_25.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_26
(
.aclr(aclr),
.cin(wire_acc_cella_25cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_26cout[0:0]),
.dataa(wire_acc_cella_dataa[26:26]),
.datab(wire_acc_cella_datab[26:26]),
.datac(wire_acc_cella_datac[26:26]),
.ena(clken),
.regout(wire_acc_cella_regout[26:26]),
.sload(sload));
defparam
acc_cella_26.cin_used = "true",
acc_cella_26.lut_mask = "96e8",
acc_cella_26.operation_mode = "arithmetic",
acc_cella_26.sum_lutc_input = "cin",
acc_cella_26.synch_mode = "on",
acc_cella_26.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_27
(
.aclr(aclr),
.cin(wire_acc_cella_26cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_27cout[0:0]),
.dataa(wire_acc_cella_dataa[27:27]),
.datab(wire_acc_cella_datab[27:27]),
.datac(wire_acc_cella_datac[27:27]),
.ena(clken),
.regout(wire_acc_cella_regout[27:27]),
.sload(sload));
defparam
acc_cella_27.cin_used = "true",
acc_cella_27.lut_mask = "96e8",
acc_cella_27.operation_mode = "arithmetic",
acc_cella_27.sum_lutc_input = "cin",
acc_cella_27.synch_mode = "on",
acc_cella_27.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_28
(
.aclr(aclr),
.cin(wire_acc_cella_27cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_28cout[0:0]),
.dataa(wire_acc_cella_dataa[28:28]),
.datab(wire_acc_cella_datab[28:28]),
.datac(wire_acc_cella_datac[28:28]),
.ena(clken),
.regout(wire_acc_cella_regout[28:28]),
.sload(sload));
defparam
acc_cella_28.cin_used = "true",
acc_cella_28.lut_mask = "96e8",
acc_cella_28.operation_mode = "arithmetic",
acc_cella_28.sum_lutc_input = "cin",
acc_cella_28.synch_mode = "on",
acc_cella_28.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_29
(
.aclr(aclr),
.cin(wire_acc_cella_28cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_29cout[0:0]),
.dataa(wire_acc_cella_dataa[29:29]),
.datab(wire_acc_cella_datab[29:29]),
.datac(wire_acc_cella_datac[29:29]),
.ena(clken),
.regout(wire_acc_cella_regout[29:29]),
.sload(sload));
defparam
acc_cella_29.cin_used = "true",
acc_cella_29.lut_mask = "96e8",
acc_cella_29.operation_mode = "arithmetic",
acc_cella_29.sum_lutc_input = "cin",
acc_cella_29.synch_mode = "on",
acc_cella_29.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_30
(
.aclr(aclr),
.cin(wire_acc_cella_29cout[0:0]),
.clk(clock),
.cout(wire_acc_cella_30cout[0:0]),
.dataa(wire_acc_cella_dataa[30:30]),
.datab(wire_acc_cella_datab[30:30]),
.datac(wire_acc_cella_datac[30:30]),
.ena(clken),
.regout(wire_acc_cella_regout[30:30]),
.sload(sload));
defparam
acc_cella_30.cin_used = "true",
acc_cella_30.lut_mask = "96e8",
acc_cella_30.operation_mode = "arithmetic",
acc_cella_30.sum_lutc_input = "cin",
acc_cella_30.synch_mode = "on",
acc_cella_30.lpm_type = "stratix_lcell";
stratix_lcell acc_cella_31
(
.aclr(aclr),
.cin(wire_acc_cella_30cout[0:0]),
.clk(clock),
.dataa(wire_acc_cella_dataa[31:31]),
.datab(wire_acc_cella_datab[31:31]),
.datac(wire_acc_cella_datac[31:31]),
.ena(clken),
.regout(wire_acc_cella_regout[31:31]),
.sload(sload));
defparam
acc_cella_31.cin_used = "true",
acc_cella_31.lut_mask = "9696",
acc_cella_31.operation_mode = "normal",
acc_cella_31.sum_lutc_input = "cin",
acc_cella_31.synch_mode = "on",
acc_cella_31.lpm_type = "stratix_lcell";
assign
wire_acc_cella_dataa = data,
wire_acc_cella_datab = wire_acc_cella_regout,
wire_acc_cella_datac = data;
assign
result = wire_acc_cella_regout,
sload = 1'b0;
endmodule
|
module accum32 (
data,
clock,
clken,
aclr,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] data;
input clock;
input clken;
input aclr;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
accum32_accum_nta accum32_accum_nta_component (
.clken (clken),
.aclr (aclr),
.clock (clock),
.data (data),
.result (sub_wire0));
endmodule
|
module spi(
input clk,
input SCK,
input MOSI,
inout MISO,
input SSEL,
output cmd_ready,
output param_ready,
output [7:0] cmd_data,
output [7:0] param_data,
output endmessage,
output startmessage,
input [7:0] input_data,
output [31:0] byte_cnt,
output [2:0] bit_cnt
);
reg [7:0] cmd_data_r;
reg [7:0] param_data_r;
reg [2:0] SSELr;
reg [2:0] SSELSCKr;
always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
always @(posedge SCK) SSELSCKr <= {SSELSCKr[1:0], SSEL};
wire SSEL_inactive = SSELr[1];
wire SSEL_active = ~SSELr[1]; // SSEL is active low
wire SSEL_startmessage = (SSELr[2:1]==2'b10); // message starts at falling edge
wire SSEL_endmessage = (SSELr[2:1]==2'b01); // message stops at rising edge
assign endmessage = SSEL_endmessage;
assign startmessage = SSEL_startmessage;
// bit count for one SPI byte + byte count for the message
reg [2:0] bitcnt;
initial bitcnt = 3'b000;
wire bitcnt_msb = bitcnt[2];
reg [2:0] bitcnt_wrap_r;
always @(posedge clk) bitcnt_wrap_r <= {bitcnt_wrap_r[1:0], bitcnt_msb};
wire byte_received_sync = (bitcnt_wrap_r[2:1] == 2'b10);
reg [31:0] byte_cnt_r;
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;
assign bit_cnt = bitcnt;
always @(posedge SCK) begin
if(SSELSCKr[1]) bitcnt <= 3'b000;
else bitcnt <= bitcnt + 3'b001;
end
always @(posedge SCK) begin
if(~SSELSCKr[1])
byte_data_received <= {byte_data_received[6:0], MOSI};
if(~SSELSCKr[1] && bitcnt==3'b111)
byte_received <= 1'b1;
else byte_received <= 1'b0;
end
//reg [2:0] byte_received_r;
//always @(posedge clk) byte_received_r <= {byte_received_r[1:0], byte_received};
//wire byte_received_sync = (byte_received_r[2:1] == 2'b01);
always @(posedge clk) begin
if(SSEL_inactive)
byte_cnt_r <= 16'h0000;
else if(byte_received_sync)
byte_cnt_r <= byte_cnt_r + 16'h0001;
end
reg [7:0] byte_data_sent;
assign MISO = ~SSEL ? input_data[7-bitcnt] : 1'bZ; // send MSB first
reg cmd_ready_r;
reg param_ready_r;
reg cmd_ready_r2;
reg param_ready_r2;
assign cmd_ready = cmd_ready_r;
assign param_ready = param_ready_r;
assign cmd_data = cmd_data_r;
assign param_data = param_data_r;
assign byte_cnt = byte_cnt_r;
always @(posedge clk) cmd_ready_r2 = byte_received_sync && byte_cnt_r == 32'h0;
always @(posedge clk) param_ready_r2 = byte_received_sync && byte_cnt_r > 32'h0;
// fill registers
always @(posedge clk) begin
if (SSEL_startmessage)
cmd_data_r <= 8'h00;
else if(cmd_ready_r2)
cmd_data_r <= byte_data_received;
else if(param_ready_r2)
param_data_r <= byte_data_received;
end
// delay ready signals by one clock
always @(posedge clk) begin
cmd_ready_r <= cmd_ready_r2;
param_ready_r <= param_ready_r2;
end
endmodule
|
module spi(
input clk,
input SCK,
input MOSI,
inout MISO,
input SSEL,
output cmd_ready,
output param_ready,
output [7:0] cmd_data,
output [7:0] param_data,
output endmessage,
output startmessage,
input [7:0] input_data,
output [31:0] byte_cnt,
output [2:0] bit_cnt
);
reg [7:0] cmd_data_r;
reg [7:0] param_data_r;
reg [2:0] SSELr;
reg [2:0] SSELSCKr;
always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
always @(posedge SCK) SSELSCKr <= {SSELSCKr[1:0], SSEL};
wire SSEL_inactive = SSELr[1];
wire SSEL_active = ~SSELr[1]; // SSEL is active low
wire SSEL_startmessage = (SSELr[2:1]==2'b10); // message starts at falling edge
wire SSEL_endmessage = (SSELr[2:1]==2'b01); // message stops at rising edge
assign endmessage = SSEL_endmessage;
assign startmessage = SSEL_startmessage;
// bit count for one SPI byte + byte count for the message
reg [2:0] bitcnt;
initial bitcnt = 3'b000;
wire bitcnt_msb = bitcnt[2];
reg [2:0] bitcnt_wrap_r;
always @(posedge clk) bitcnt_wrap_r <= {bitcnt_wrap_r[1:0], bitcnt_msb};
wire byte_received_sync = (bitcnt_wrap_r[2:1] == 2'b10);
reg [31:0] byte_cnt_r;
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;
assign bit_cnt = bitcnt;
always @(posedge SCK) begin
if(SSELSCKr[1]) bitcnt <= 3'b000;
else bitcnt <= bitcnt + 3'b001;
end
always @(posedge SCK) begin
if(~SSELSCKr[1])
byte_data_received <= {byte_data_received[6:0], MOSI};
if(~SSELSCKr[1] && bitcnt==3'b111)
byte_received <= 1'b1;
else byte_received <= 1'b0;
end
//reg [2:0] byte_received_r;
//always @(posedge clk) byte_received_r <= {byte_received_r[1:0], byte_received};
//wire byte_received_sync = (byte_received_r[2:1] == 2'b01);
always @(posedge clk) begin
if(SSEL_inactive)
byte_cnt_r <= 16'h0000;
else if(byte_received_sync)
byte_cnt_r <= byte_cnt_r + 16'h0001;
end
reg [7:0] byte_data_sent;
assign MISO = ~SSEL ? input_data[7-bitcnt] : 1'bZ; // send MSB first
reg cmd_ready_r;
reg param_ready_r;
reg cmd_ready_r2;
reg param_ready_r2;
assign cmd_ready = cmd_ready_r;
assign param_ready = param_ready_r;
assign cmd_data = cmd_data_r;
assign param_data = param_data_r;
assign byte_cnt = byte_cnt_r;
always @(posedge clk) cmd_ready_r2 = byte_received_sync && byte_cnt_r == 32'h0;
always @(posedge clk) param_ready_r2 = byte_received_sync && byte_cnt_r > 32'h0;
// fill registers
always @(posedge clk) begin
if (SSEL_startmessage)
cmd_data_r <= 8'h00;
else if(cmd_ready_r2)
cmd_data_r <= byte_data_received;
else if(param_ready_r2)
param_data_r <= byte_data_received;
end
// delay ready signals by one clock
always @(posedge clk) begin
cmd_ready_r <= cmd_ready_r2;
param_ready_r <= param_ready_r2;
end
endmodule
|
module spi(
input clk,
input SCK,
input MOSI,
inout MISO,
input SSEL,
output cmd_ready,
output param_ready,
output [7:0] cmd_data,
output [7:0] param_data,
output endmessage,
output startmessage,
input [7:0] input_data,
output [31:0] byte_cnt,
output [2:0] bit_cnt
);
reg [7:0] cmd_data_r;
reg [7:0] param_data_r;
reg [2:0] SSELr;
reg [2:0] SSELSCKr;
always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
always @(posedge SCK) SSELSCKr <= {SSELSCKr[1:0], SSEL};
wire SSEL_inactive = SSELr[1];
wire SSEL_active = ~SSELr[1]; // SSEL is active low
wire SSEL_startmessage = (SSELr[2:1]==2'b10); // message starts at falling edge
wire SSEL_endmessage = (SSELr[2:1]==2'b01); // message stops at rising edge
assign endmessage = SSEL_endmessage;
assign startmessage = SSEL_startmessage;
// bit count for one SPI byte + byte count for the message
reg [2:0] bitcnt;
initial bitcnt = 3'b000;
wire bitcnt_msb = bitcnt[2];
reg [2:0] bitcnt_wrap_r;
always @(posedge clk) bitcnt_wrap_r <= {bitcnt_wrap_r[1:0], bitcnt_msb};
wire byte_received_sync = (bitcnt_wrap_r[2:1] == 2'b10);
reg [31:0] byte_cnt_r;
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;
assign bit_cnt = bitcnt;
always @(posedge SCK) begin
if(SSELSCKr[1]) bitcnt <= 3'b000;
else bitcnt <= bitcnt + 3'b001;
end
always @(posedge SCK) begin
if(~SSELSCKr[1])
byte_data_received <= {byte_data_received[6:0], MOSI};
if(~SSELSCKr[1] && bitcnt==3'b111)
byte_received <= 1'b1;
else byte_received <= 1'b0;
end
//reg [2:0] byte_received_r;
//always @(posedge clk) byte_received_r <= {byte_received_r[1:0], byte_received};
//wire byte_received_sync = (byte_received_r[2:1] == 2'b01);
always @(posedge clk) begin
if(SSEL_inactive)
byte_cnt_r <= 16'h0000;
else if(byte_received_sync)
byte_cnt_r <= byte_cnt_r + 16'h0001;
end
reg [7:0] byte_data_sent;
assign MISO = ~SSEL ? input_data[7-bitcnt] : 1'bZ; // send MSB first
reg cmd_ready_r;
reg param_ready_r;
reg cmd_ready_r2;
reg param_ready_r2;
assign cmd_ready = cmd_ready_r;
assign param_ready = param_ready_r;
assign cmd_data = cmd_data_r;
assign param_data = param_data_r;
assign byte_cnt = byte_cnt_r;
always @(posedge clk) cmd_ready_r2 = byte_received_sync && byte_cnt_r == 32'h0;
always @(posedge clk) param_ready_r2 = byte_received_sync && byte_cnt_r > 32'h0;
// fill registers
always @(posedge clk) begin
if (SSEL_startmessage)
cmd_data_r <= 8'h00;
else if(cmd_ready_r2)
cmd_data_r <= byte_data_received;
else if(param_ready_r2)
param_data_r <= byte_data_received;
end
// delay ready signals by one clock
always @(posedge clk) begin
cmd_ready_r <= cmd_ready_r2;
param_ready_r <= param_ready_r2;
end
endmodule
|
module fifo( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 16;
parameter depth = 1024;
parameter addr_bits = 10;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [width-1:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [width-1:0] q;
output rdfull;
output rdempty;
output reg [addr_bits-1:0] rdusedw;
output wrfull;
output wrempty;
output reg [addr_bits-1:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [addr_bits-1:0] rdptr;
reg [addr_bits-1:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
assign wrempty = (wrusedw == 0);
assign wrfull = (wrusedw == depth-1);
assign rdempty = (rdusedw == 0);
assign rdfull = (rdusedw == depth-1);
endmodule
|
module fifo( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 16;
parameter depth = 1024;
parameter addr_bits = 10;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [width-1:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [width-1:0] q;
output rdfull;
output rdempty;
output reg [addr_bits-1:0] rdusedw;
output wrfull;
output wrempty;
output reg [addr_bits-1:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [addr_bits-1:0] rdptr;
reg [addr_bits-1:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
assign wrempty = (wrusedw == 0);
assign wrfull = (wrusedw == depth-1);
assign rdempty = (rdusedw == 0);
assign rdfull = (rdusedw == depth-1);
endmodule
|
module bidir_reg
( inout wire [15:0] tristate,
input wire [15:0] oe,
input wire [15:0] reg_val );
// This would be much cleaner if all the tools
// supported "for generate"........
assign tristate[0] = oe[0] ? reg_val[0] : 1'bz;
assign tristate[1] = oe[1] ? reg_val[1] : 1'bz;
assign tristate[2] = oe[2] ? reg_val[2] : 1'bz;
assign tristate[3] = oe[3] ? reg_val[3] : 1'bz;
assign tristate[4] = oe[4] ? reg_val[4] : 1'bz;
assign tristate[5] = oe[5] ? reg_val[5] : 1'bz;
assign tristate[6] = oe[6] ? reg_val[6] : 1'bz;
assign tristate[7] = oe[7] ? reg_val[7] : 1'bz;
assign tristate[8] = oe[8] ? reg_val[8] : 1'bz;
assign tristate[9] = oe[9] ? reg_val[9] : 1'bz;
assign tristate[10] = oe[10] ? reg_val[10] : 1'bz;
assign tristate[11] = oe[11] ? reg_val[11] : 1'bz;
assign tristate[12] = oe[12] ? reg_val[12] : 1'bz;
assign tristate[13] = oe[13] ? reg_val[13] : 1'bz;
assign tristate[14] = oe[14] ? reg_val[14] : 1'bz;
assign tristate[15] = oe[15] ? reg_val[15] : 1'bz;
endmodule
|
module bidir_reg
( inout wire [15:0] tristate,
input wire [15:0] oe,
input wire [15:0] reg_val );
// This would be much cleaner if all the tools
// supported "for generate"........
assign tristate[0] = oe[0] ? reg_val[0] : 1'bz;
assign tristate[1] = oe[1] ? reg_val[1] : 1'bz;
assign tristate[2] = oe[2] ? reg_val[2] : 1'bz;
assign tristate[3] = oe[3] ? reg_val[3] : 1'bz;
assign tristate[4] = oe[4] ? reg_val[4] : 1'bz;
assign tristate[5] = oe[5] ? reg_val[5] : 1'bz;
assign tristate[6] = oe[6] ? reg_val[6] : 1'bz;
assign tristate[7] = oe[7] ? reg_val[7] : 1'bz;
assign tristate[8] = oe[8] ? reg_val[8] : 1'bz;
assign tristate[9] = oe[9] ? reg_val[9] : 1'bz;
assign tristate[10] = oe[10] ? reg_val[10] : 1'bz;
assign tristate[11] = oe[11] ? reg_val[11] : 1'bz;
assign tristate[12] = oe[12] ? reg_val[12] : 1'bz;
assign tristate[13] = oe[13] ? reg_val[13] : 1'bz;
assign tristate[14] = oe[14] ? reg_val[14] : 1'bz;
assign tristate[15] = oe[15] ? reg_val[15] : 1'bz;
endmodule
|
module mylpm_addsub (
add_sub,
dataa,
datab,
clock,
result);
input add_sub;
input [15:0] dataa;
input [15:0] datab;
input clock;
output [15:0] result;
wire [15:0] sub_wire0;
wire [15:0] result = sub_wire0[15:0];
lpm_add_sub lpm_add_sub_component (
.dataa (dataa),
.add_sub (add_sub),
.datab (datab),
.clock (clock),
.result (sub_wire0));
defparam
lpm_add_sub_component.lpm_width = 16,
lpm_add_sub_component.lpm_direction = "UNUSED",
lpm_add_sub_component.lpm_type = "LPM_ADD_SUB",
lpm_add_sub_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO",
lpm_add_sub_component.lpm_pipeline = 1;
endmodule
|
module mylpm_addsub (
add_sub,
dataa,
datab,
clock,
result);
input add_sub;
input [15:0] dataa;
input [15:0] datab;
input clock;
output [15:0] result;
wire [15:0] sub_wire0;
wire [15:0] result = sub_wire0[15:0];
lpm_add_sub lpm_add_sub_component (
.dataa (dataa),
.add_sub (add_sub),
.datab (datab),
.clock (clock),
.result (sub_wire0));
defparam
lpm_add_sub_component.lpm_width = 16,
lpm_add_sub_component.lpm_direction = "UNUSED",
lpm_add_sub_component.lpm_type = "LPM_ADD_SUB",
lpm_add_sub_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO",
lpm_add_sub_component.lpm_pipeline = 1;
endmodule
|
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