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module processing_system7_bfm_v2_0_5_arb_hp0_1(
sw_clk,
rstn,
w_qos_hp0,
r_qos_hp0,
w_qos_hp1,
r_qos_hp1,
wr_ack_ddr_hp0,
wr_data_hp0,
wr_addr_hp0,
wr_bytes_hp0,
wr_dv_ddr_hp0,
rd_req_ddr_hp0,
rd_addr_hp0,
rd_bytes_hp0,
rd_data_ddr_hp0,
rd_dv_ddr_hp0,
wr_ack_ddr_hp1,
wr_data_hp1,
wr_addr_hp1,
wr_bytes_hp1,
wr_dv_ddr_hp1,
rd_req_ddr_hp1,
rd_addr_hp1,
rd_bytes_hp1,
rd_data_ddr_hp1,
rd_dv_ddr_hp1,
ddr_wr_ack,
ddr_wr_dv,
ddr_rd_req,
ddr_rd_dv,
ddr_rd_qos,
ddr_wr_qos,
ddr_wr_addr,
ddr_wr_data,
ddr_wr_bytes,
ddr_rd_addr,
ddr_rd_data,
ddr_rd_bytes
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input sw_clk;
input rstn;
input [axi_qos_width-1:0] w_qos_hp0;
input [axi_qos_width-1:0] r_qos_hp0;
input [axi_qos_width-1:0] w_qos_hp1;
input [axi_qos_width-1:0] r_qos_hp1;
input [axi_qos_width-1:0] ddr_rd_qos;
input [axi_qos_width-1:0] ddr_wr_qos;
output wr_ack_ddr_hp0;
input [max_burst_bits-1:0] wr_data_hp0;
input [addr_width-1:0] wr_addr_hp0;
input [max_burst_bytes_width:0] wr_bytes_hp0;
output wr_dv_ddr_hp0;
input rd_req_ddr_hp0;
input [addr_width-1:0] rd_addr_hp0;
input [max_burst_bytes_width:0] rd_bytes_hp0;
output [max_burst_bits-1:0] rd_data_ddr_hp0;
output rd_dv_ddr_hp0;
output wr_ack_ddr_hp1;
input [max_burst_bits-1:0] wr_data_hp1;
input [addr_width-1:0] wr_addr_hp1;
input [max_burst_bytes_width:0] wr_bytes_hp1;
output wr_dv_ddr_hp1;
input rd_req_ddr_hp1;
input [addr_width-1:0] rd_addr_hp1;
input [max_burst_bytes_width:0] rd_bytes_hp1;
output [max_burst_bits-1:0] rd_data_ddr_hp1;
output rd_dv_ddr_hp1;
input ddr_wr_ack;
output ddr_wr_dv;
output [addr_width-1:0]ddr_wr_addr;
output [max_burst_bits-1:0]ddr_wr_data;
output [max_burst_bytes_width:0]ddr_wr_bytes;
input ddr_rd_dv;
input [max_burst_bits-1:0] ddr_rd_data;
output ddr_rd_req;
output [addr_width-1:0] ddr_rd_addr;
output [max_burst_bytes_width:0] ddr_rd_bytes;
processing_system7_bfm_v2_0_5_arb_wr ddr_hp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_hp0),
.qos2(w_qos_hp1),
.prt_dv1(wr_dv_ddr_hp0),
.prt_dv2(wr_dv_ddr_hp1),
.prt_data1(wr_data_hp0),
.prt_data2(wr_data_hp1),
.prt_addr1(wr_addr_hp0),
.prt_addr2(wr_addr_hp1),
.prt_bytes1(wr_bytes_hp0),
.prt_bytes2(wr_bytes_hp1),
.prt_ack1(wr_ack_ddr_hp0),
.prt_ack2(wr_ack_ddr_hp1),
.prt_req(ddr_wr_dv),
.prt_qos(ddr_wr_qos),
.prt_data(ddr_wr_data),
.prt_addr(ddr_wr_addr),
.prt_bytes(ddr_wr_bytes),
.prt_ack(ddr_wr_ack)
);
processing_system7_bfm_v2_0_5_arb_rd ddr_hp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_hp0),
.qos2(r_qos_hp1),
.prt_req1(rd_req_ddr_hp0),
.prt_req2(rd_req_ddr_hp1),
.prt_data1(rd_data_ddr_hp0),
.prt_data2(rd_data_ddr_hp1),
.prt_addr1(rd_addr_hp0),
.prt_addr2(rd_addr_hp1),
.prt_bytes1(rd_bytes_hp0),
.prt_bytes2(rd_bytes_hp1),
.prt_dv1(rd_dv_ddr_hp0),
.prt_dv2(rd_dv_ddr_hp1),
.prt_qos(ddr_rd_qos),
.prt_req(ddr_rd_req),
.prt_data(ddr_rd_data),
.prt_addr(ddr_rd_addr),
.prt_bytes(ddr_rd_bytes),
.prt_dv(ddr_rd_dv)
);
endmodule |
module processing_system7_bfm_v2_0_5_arb_hp0_1(
sw_clk,
rstn,
w_qos_hp0,
r_qos_hp0,
w_qos_hp1,
r_qos_hp1,
wr_ack_ddr_hp0,
wr_data_hp0,
wr_addr_hp0,
wr_bytes_hp0,
wr_dv_ddr_hp0,
rd_req_ddr_hp0,
rd_addr_hp0,
rd_bytes_hp0,
rd_data_ddr_hp0,
rd_dv_ddr_hp0,
wr_ack_ddr_hp1,
wr_data_hp1,
wr_addr_hp1,
wr_bytes_hp1,
wr_dv_ddr_hp1,
rd_req_ddr_hp1,
rd_addr_hp1,
rd_bytes_hp1,
rd_data_ddr_hp1,
rd_dv_ddr_hp1,
ddr_wr_ack,
ddr_wr_dv,
ddr_rd_req,
ddr_rd_dv,
ddr_rd_qos,
ddr_wr_qos,
ddr_wr_addr,
ddr_wr_data,
ddr_wr_bytes,
ddr_rd_addr,
ddr_rd_data,
ddr_rd_bytes
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input sw_clk;
input rstn;
input [axi_qos_width-1:0] w_qos_hp0;
input [axi_qos_width-1:0] r_qos_hp0;
input [axi_qos_width-1:0] w_qos_hp1;
input [axi_qos_width-1:0] r_qos_hp1;
input [axi_qos_width-1:0] ddr_rd_qos;
input [axi_qos_width-1:0] ddr_wr_qos;
output wr_ack_ddr_hp0;
input [max_burst_bits-1:0] wr_data_hp0;
input [addr_width-1:0] wr_addr_hp0;
input [max_burst_bytes_width:0] wr_bytes_hp0;
output wr_dv_ddr_hp0;
input rd_req_ddr_hp0;
input [addr_width-1:0] rd_addr_hp0;
input [max_burst_bytes_width:0] rd_bytes_hp0;
output [max_burst_bits-1:0] rd_data_ddr_hp0;
output rd_dv_ddr_hp0;
output wr_ack_ddr_hp1;
input [max_burst_bits-1:0] wr_data_hp1;
input [addr_width-1:0] wr_addr_hp1;
input [max_burst_bytes_width:0] wr_bytes_hp1;
output wr_dv_ddr_hp1;
input rd_req_ddr_hp1;
input [addr_width-1:0] rd_addr_hp1;
input [max_burst_bytes_width:0] rd_bytes_hp1;
output [max_burst_bits-1:0] rd_data_ddr_hp1;
output rd_dv_ddr_hp1;
input ddr_wr_ack;
output ddr_wr_dv;
output [addr_width-1:0]ddr_wr_addr;
output [max_burst_bits-1:0]ddr_wr_data;
output [max_burst_bytes_width:0]ddr_wr_bytes;
input ddr_rd_dv;
input [max_burst_bits-1:0] ddr_rd_data;
output ddr_rd_req;
output [addr_width-1:0] ddr_rd_addr;
output [max_burst_bytes_width:0] ddr_rd_bytes;
processing_system7_bfm_v2_0_5_arb_wr ddr_hp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_hp0),
.qos2(w_qos_hp1),
.prt_dv1(wr_dv_ddr_hp0),
.prt_dv2(wr_dv_ddr_hp1),
.prt_data1(wr_data_hp0),
.prt_data2(wr_data_hp1),
.prt_addr1(wr_addr_hp0),
.prt_addr2(wr_addr_hp1),
.prt_bytes1(wr_bytes_hp0),
.prt_bytes2(wr_bytes_hp1),
.prt_ack1(wr_ack_ddr_hp0),
.prt_ack2(wr_ack_ddr_hp1),
.prt_req(ddr_wr_dv),
.prt_qos(ddr_wr_qos),
.prt_data(ddr_wr_data),
.prt_addr(ddr_wr_addr),
.prt_bytes(ddr_wr_bytes),
.prt_ack(ddr_wr_ack)
);
processing_system7_bfm_v2_0_5_arb_rd ddr_hp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_hp0),
.qos2(r_qos_hp1),
.prt_req1(rd_req_ddr_hp0),
.prt_req2(rd_req_ddr_hp1),
.prt_data1(rd_data_ddr_hp0),
.prt_data2(rd_data_ddr_hp1),
.prt_addr1(rd_addr_hp0),
.prt_addr2(rd_addr_hp1),
.prt_bytes1(rd_bytes_hp0),
.prt_bytes2(rd_bytes_hp1),
.prt_dv1(rd_dv_ddr_hp0),
.prt_dv2(rd_dv_ddr_hp1),
.prt_qos(ddr_rd_qos),
.prt_req(ddr_rd_req),
.prt_data(ddr_rd_data),
.prt_addr(ddr_rd_addr),
.prt_bytes(ddr_rd_bytes),
.prt_dv(ddr_rd_dv)
);
endmodule |
module axi_crossbar_v2_1_decerr_slave #
(
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_RESP = 2'b11
)
(
input wire S_AXI_ACLK,
input wire S_AXI_ARESET,
input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_AWID,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
input wire S_AXI_WLAST,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_BID,
output wire [1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_ARID,
input wire [7:0] S_AXI_ARLEN,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_RID,
output wire [(C_AXI_DATA_WIDTH-1):0] S_AXI_RDATA,
output wire [1:0] S_AXI_RRESP,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RLAST,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY
);
reg s_axi_awready_i;
reg s_axi_wready_i;
reg s_axi_bvalid_i;
reg s_axi_arready_i;
reg s_axi_rvalid_i;
localparam P_WRITE_IDLE = 2'b00;
localparam P_WRITE_DATA = 2'b01;
localparam P_WRITE_RESP = 2'b10;
localparam P_READ_IDLE = 1'b0;
localparam P_READ_DATA = 1'b1;
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
assign S_AXI_BRESP = C_RESP;
assign S_AXI_RRESP = C_RESP;
assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1'b0}};
assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}};
assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}};
assign S_AXI_AWREADY = s_axi_awready_i;
assign S_AXI_WREADY = s_axi_wready_i;
assign S_AXI_BVALID = s_axi_bvalid_i;
assign S_AXI_ARREADY = s_axi_arready_i;
assign S_AXI_RVALID = s_axi_rvalid_i;
generate
if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_axilite
assign S_AXI_RLAST = 1'b1;
assign S_AXI_BID = 0;
assign S_AXI_RID = 0;
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESET) begin
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b0;
end else begin
if (s_axi_bvalid_i) begin
if (S_AXI_BREADY) begin
s_axi_bvalid_i <= 1'b0;
end
end else if (S_AXI_AWVALID & S_AXI_WVALID) begin
if (s_axi_awready_i) begin
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b1;
end else begin
s_axi_awready_i <= 1'b1;
s_axi_wready_i <= 1'b1;
end
end
end
end
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESET) begin
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b0;
end else begin
if (s_axi_rvalid_i) begin
if (S_AXI_RREADY) begin
s_axi_rvalid_i <= 1'b0;
end
end else if (S_AXI_ARVALID & s_axi_arready_i) begin
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b1;
end else begin
s_axi_arready_i <= 1'b1;
end
end
end
end else begin : gen_axi
reg s_axi_rlast_i;
reg [(C_AXI_ID_WIDTH-1):0] s_axi_bid_i;
reg [(C_AXI_ID_WIDTH-1):0] s_axi_rid_i;
reg [7:0] read_cnt;
reg [1:0] write_cs;
reg [0:0] read_cs;
assign S_AXI_RLAST = s_axi_rlast_i;
assign S_AXI_BID = s_axi_bid_i;
assign S_AXI_RID = s_axi_rid_i;
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESET) begin
write_cs <= P_WRITE_IDLE;
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b0;
s_axi_bid_i <= 0;
end else begin
case (write_cs)
P_WRITE_IDLE:
begin
if (S_AXI_AWVALID & s_axi_awready_i) begin
s_axi_awready_i <= 1'b0;
s_axi_bid_i <= S_AXI_AWID;
s_axi_wready_i <= 1'b1;
write_cs <= P_WRITE_DATA;
end else begin
s_axi_awready_i <= 1'b1;
end
end
P_WRITE_DATA:
begin
if (S_AXI_WVALID & S_AXI_WLAST) begin
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b1;
write_cs <= P_WRITE_RESP;
end
end
P_WRITE_RESP:
begin
if (S_AXI_BREADY) begin
s_axi_bvalid_i <= 1'b0;
s_axi_awready_i <= 1'b1;
write_cs <= P_WRITE_IDLE;
end
end
endcase
end
end
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESET) begin
read_cs <= P_READ_IDLE;
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b0;
s_axi_rlast_i <= 1'b0;
s_axi_rid_i <= 0;
read_cnt <= 0;
end else begin
case (read_cs)
P_READ_IDLE:
begin
if (S_AXI_ARVALID & s_axi_arready_i) begin
s_axi_arready_i <= 1'b0;
s_axi_rid_i <= S_AXI_ARID;
read_cnt <= S_AXI_ARLEN;
s_axi_rvalid_i <= 1'b1;
if (S_AXI_ARLEN == 0) begin
s_axi_rlast_i <= 1'b1;
end else begin
s_axi_rlast_i <= 1'b0;
end
read_cs <= P_READ_DATA;
end else begin
s_axi_arready_i <= 1'b1;
end
end
P_READ_DATA:
begin
if (S_AXI_RREADY) begin
if (read_cnt == 0) begin
s_axi_rvalid_i <= 1'b0;
s_axi_rlast_i <= 1'b0;
s_axi_arready_i <= 1'b1;
read_cs <= P_READ_IDLE;
end else begin
if (read_cnt == 1) begin
s_axi_rlast_i <= 1'b1;
end
read_cnt <= read_cnt - 1;
end
end
end
endcase
end
end
end
endgenerate
endmodule |
module axi_crossbar_v2_1_decerr_slave #
(
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_RESP = 2'b11
)
(
input wire S_AXI_ACLK,
input wire S_AXI_ARESET,
input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_AWID,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
input wire S_AXI_WLAST,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_BID,
output wire [1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_ARID,
input wire [7:0] S_AXI_ARLEN,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_RID,
output wire [(C_AXI_DATA_WIDTH-1):0] S_AXI_RDATA,
output wire [1:0] S_AXI_RRESP,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RLAST,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY
);
reg s_axi_awready_i;
reg s_axi_wready_i;
reg s_axi_bvalid_i;
reg s_axi_arready_i;
reg s_axi_rvalid_i;
localparam P_WRITE_IDLE = 2'b00;
localparam P_WRITE_DATA = 2'b01;
localparam P_WRITE_RESP = 2'b10;
localparam P_READ_IDLE = 1'b0;
localparam P_READ_DATA = 1'b1;
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
assign S_AXI_BRESP = C_RESP;
assign S_AXI_RRESP = C_RESP;
assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1'b0}};
assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}};
assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}};
assign S_AXI_AWREADY = s_axi_awready_i;
assign S_AXI_WREADY = s_axi_wready_i;
assign S_AXI_BVALID = s_axi_bvalid_i;
assign S_AXI_ARREADY = s_axi_arready_i;
assign S_AXI_RVALID = s_axi_rvalid_i;
generate
if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_axilite
assign S_AXI_RLAST = 1'b1;
assign S_AXI_BID = 0;
assign S_AXI_RID = 0;
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESET) begin
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b0;
end else begin
if (s_axi_bvalid_i) begin
if (S_AXI_BREADY) begin
s_axi_bvalid_i <= 1'b0;
end
end else if (S_AXI_AWVALID & S_AXI_WVALID) begin
if (s_axi_awready_i) begin
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b1;
end else begin
s_axi_awready_i <= 1'b1;
s_axi_wready_i <= 1'b1;
end
end
end
end
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESET) begin
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b0;
end else begin
if (s_axi_rvalid_i) begin
if (S_AXI_RREADY) begin
s_axi_rvalid_i <= 1'b0;
end
end else if (S_AXI_ARVALID & s_axi_arready_i) begin
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b1;
end else begin
s_axi_arready_i <= 1'b1;
end
end
end
end else begin : gen_axi
reg s_axi_rlast_i;
reg [(C_AXI_ID_WIDTH-1):0] s_axi_bid_i;
reg [(C_AXI_ID_WIDTH-1):0] s_axi_rid_i;
reg [7:0] read_cnt;
reg [1:0] write_cs;
reg [0:0] read_cs;
assign S_AXI_RLAST = s_axi_rlast_i;
assign S_AXI_BID = s_axi_bid_i;
assign S_AXI_RID = s_axi_rid_i;
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESET) begin
write_cs <= P_WRITE_IDLE;
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b0;
s_axi_bid_i <= 0;
end else begin
case (write_cs)
P_WRITE_IDLE:
begin
if (S_AXI_AWVALID & s_axi_awready_i) begin
s_axi_awready_i <= 1'b0;
s_axi_bid_i <= S_AXI_AWID;
s_axi_wready_i <= 1'b1;
write_cs <= P_WRITE_DATA;
end else begin
s_axi_awready_i <= 1'b1;
end
end
P_WRITE_DATA:
begin
if (S_AXI_WVALID & S_AXI_WLAST) begin
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b1;
write_cs <= P_WRITE_RESP;
end
end
P_WRITE_RESP:
begin
if (S_AXI_BREADY) begin
s_axi_bvalid_i <= 1'b0;
s_axi_awready_i <= 1'b1;
write_cs <= P_WRITE_IDLE;
end
end
endcase
end
end
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESET) begin
read_cs <= P_READ_IDLE;
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b0;
s_axi_rlast_i <= 1'b0;
s_axi_rid_i <= 0;
read_cnt <= 0;
end else begin
case (read_cs)
P_READ_IDLE:
begin
if (S_AXI_ARVALID & s_axi_arready_i) begin
s_axi_arready_i <= 1'b0;
s_axi_rid_i <= S_AXI_ARID;
read_cnt <= S_AXI_ARLEN;
s_axi_rvalid_i <= 1'b1;
if (S_AXI_ARLEN == 0) begin
s_axi_rlast_i <= 1'b1;
end else begin
s_axi_rlast_i <= 1'b0;
end
read_cs <= P_READ_DATA;
end else begin
s_axi_arready_i <= 1'b1;
end
end
P_READ_DATA:
begin
if (S_AXI_RREADY) begin
if (read_cnt == 0) begin
s_axi_rvalid_i <= 1'b0;
s_axi_rlast_i <= 1'b0;
s_axi_arready_i <= 1'b1;
read_cs <= P_READ_IDLE;
end else begin
if (read_cnt == 1) begin
s_axi_rlast_i <= 1'b1;
end
read_cnt <= read_cnt - 1;
end
end
end
endcase
end
end
end
endgenerate
endmodule |
module axi_crossbar_v2_1_decerr_slave #
(
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_RESP = 2'b11
)
(
input wire S_AXI_ACLK,
input wire S_AXI_ARESET,
input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_AWID,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
input wire S_AXI_WLAST,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_BID,
output wire [1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_ARID,
input wire [7:0] S_AXI_ARLEN,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_RID,
output wire [(C_AXI_DATA_WIDTH-1):0] S_AXI_RDATA,
output wire [1:0] S_AXI_RRESP,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RLAST,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY
);
reg s_axi_awready_i;
reg s_axi_wready_i;
reg s_axi_bvalid_i;
reg s_axi_arready_i;
reg s_axi_rvalid_i;
localparam P_WRITE_IDLE = 2'b00;
localparam P_WRITE_DATA = 2'b01;
localparam P_WRITE_RESP = 2'b10;
localparam P_READ_IDLE = 1'b0;
localparam P_READ_DATA = 1'b1;
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
assign S_AXI_BRESP = C_RESP;
assign S_AXI_RRESP = C_RESP;
assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1'b0}};
assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}};
assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}};
assign S_AXI_AWREADY = s_axi_awready_i;
assign S_AXI_WREADY = s_axi_wready_i;
assign S_AXI_BVALID = s_axi_bvalid_i;
assign S_AXI_ARREADY = s_axi_arready_i;
assign S_AXI_RVALID = s_axi_rvalid_i;
generate
if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_axilite
assign S_AXI_RLAST = 1'b1;
assign S_AXI_BID = 0;
assign S_AXI_RID = 0;
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESET) begin
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b0;
end else begin
if (s_axi_bvalid_i) begin
if (S_AXI_BREADY) begin
s_axi_bvalid_i <= 1'b0;
end
end else if (S_AXI_AWVALID & S_AXI_WVALID) begin
if (s_axi_awready_i) begin
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b1;
end else begin
s_axi_awready_i <= 1'b1;
s_axi_wready_i <= 1'b1;
end
end
end
end
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESET) begin
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b0;
end else begin
if (s_axi_rvalid_i) begin
if (S_AXI_RREADY) begin
s_axi_rvalid_i <= 1'b0;
end
end else if (S_AXI_ARVALID & s_axi_arready_i) begin
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b1;
end else begin
s_axi_arready_i <= 1'b1;
end
end
end
end else begin : gen_axi
reg s_axi_rlast_i;
reg [(C_AXI_ID_WIDTH-1):0] s_axi_bid_i;
reg [(C_AXI_ID_WIDTH-1):0] s_axi_rid_i;
reg [7:0] read_cnt;
reg [1:0] write_cs;
reg [0:0] read_cs;
assign S_AXI_RLAST = s_axi_rlast_i;
assign S_AXI_BID = s_axi_bid_i;
assign S_AXI_RID = s_axi_rid_i;
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESET) begin
write_cs <= P_WRITE_IDLE;
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b0;
s_axi_bid_i <= 0;
end else begin
case (write_cs)
P_WRITE_IDLE:
begin
if (S_AXI_AWVALID & s_axi_awready_i) begin
s_axi_awready_i <= 1'b0;
s_axi_bid_i <= S_AXI_AWID;
s_axi_wready_i <= 1'b1;
write_cs <= P_WRITE_DATA;
end else begin
s_axi_awready_i <= 1'b1;
end
end
P_WRITE_DATA:
begin
if (S_AXI_WVALID & S_AXI_WLAST) begin
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b1;
write_cs <= P_WRITE_RESP;
end
end
P_WRITE_RESP:
begin
if (S_AXI_BREADY) begin
s_axi_bvalid_i <= 1'b0;
s_axi_awready_i <= 1'b1;
write_cs <= P_WRITE_IDLE;
end
end
endcase
end
end
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESET) begin
read_cs <= P_READ_IDLE;
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b0;
s_axi_rlast_i <= 1'b0;
s_axi_rid_i <= 0;
read_cnt <= 0;
end else begin
case (read_cs)
P_READ_IDLE:
begin
if (S_AXI_ARVALID & s_axi_arready_i) begin
s_axi_arready_i <= 1'b0;
s_axi_rid_i <= S_AXI_ARID;
read_cnt <= S_AXI_ARLEN;
s_axi_rvalid_i <= 1'b1;
if (S_AXI_ARLEN == 0) begin
s_axi_rlast_i <= 1'b1;
end else begin
s_axi_rlast_i <= 1'b0;
end
read_cs <= P_READ_DATA;
end else begin
s_axi_arready_i <= 1'b1;
end
end
P_READ_DATA:
begin
if (S_AXI_RREADY) begin
if (read_cnt == 0) begin
s_axi_rvalid_i <= 1'b0;
s_axi_rlast_i <= 1'b0;
s_axi_arready_i <= 1'b1;
read_cs <= P_READ_IDLE;
end else begin
if (read_cnt == 1) begin
s_axi_rlast_i <= 1'b1;
end
read_cnt <= read_cnt - 1;
end
end
end
endcase
end
end
end
endgenerate
endmodule |
module processing_system7_bfm_v2_0_5_interconnect_model (
rstn,
sw_clk,
w_qos_gp0,
w_qos_gp1,
w_qos_hp0,
w_qos_hp1,
w_qos_hp2,
w_qos_hp3,
r_qos_gp0,
r_qos_gp1,
r_qos_hp0,
r_qos_hp1,
r_qos_hp2,
r_qos_hp3,
wr_ack_ddr_gp0,
wr_ack_ocm_gp0,
wr_data_gp0,
wr_addr_gp0,
wr_bytes_gp0,
wr_dv_ddr_gp0,
wr_dv_ocm_gp0,
rd_req_ddr_gp0,
rd_req_ocm_gp0,
rd_req_reg_gp0,
rd_addr_gp0,
rd_bytes_gp0,
rd_data_ddr_gp0,
rd_data_ocm_gp0,
rd_data_reg_gp0,
rd_dv_ddr_gp0,
rd_dv_ocm_gp0,
rd_dv_reg_gp0,
wr_ack_ddr_gp1,
wr_ack_ocm_gp1,
wr_data_gp1,
wr_addr_gp1,
wr_bytes_gp1,
wr_dv_ddr_gp1,
wr_dv_ocm_gp1,
rd_req_ddr_gp1,
rd_req_ocm_gp1,
rd_req_reg_gp1,
rd_addr_gp1,
rd_bytes_gp1,
rd_data_ddr_gp1,
rd_data_ocm_gp1,
rd_data_reg_gp1,
rd_dv_ddr_gp1,
rd_dv_ocm_gp1,
rd_dv_reg_gp1,
wr_ack_ddr_hp0,
wr_ack_ocm_hp0,
wr_data_hp0,
wr_addr_hp0,
wr_bytes_hp0,
wr_dv_ddr_hp0,
wr_dv_ocm_hp0,
rd_req_ddr_hp0,
rd_req_ocm_hp0,
rd_addr_hp0,
rd_bytes_hp0,
rd_data_ddr_hp0,
rd_data_ocm_hp0,
rd_dv_ddr_hp0,
rd_dv_ocm_hp0,
wr_ack_ddr_hp1,
wr_ack_ocm_hp1,
wr_data_hp1,
wr_addr_hp1,
wr_bytes_hp1,
wr_dv_ddr_hp1,
wr_dv_ocm_hp1,
rd_req_ddr_hp1,
rd_req_ocm_hp1,
rd_addr_hp1,
rd_bytes_hp1,
rd_data_ddr_hp1,
rd_data_ocm_hp1,
rd_dv_ddr_hp1,
rd_dv_ocm_hp1,
wr_ack_ddr_hp2,
wr_ack_ocm_hp2,
wr_data_hp2,
wr_addr_hp2,
wr_bytes_hp2,
wr_dv_ddr_hp2,
wr_dv_ocm_hp2,
rd_req_ddr_hp2,
rd_req_ocm_hp2,
rd_addr_hp2,
rd_bytes_hp2,
rd_data_ddr_hp2,
rd_data_ocm_hp2,
rd_dv_ddr_hp2,
rd_dv_ocm_hp2,
wr_ack_ddr_hp3,
wr_ack_ocm_hp3,
wr_data_hp3,
wr_addr_hp3,
wr_bytes_hp3,
wr_dv_ddr_hp3,
wr_dv_ocm_hp3,
rd_req_ddr_hp3,
rd_req_ocm_hp3,
rd_addr_hp3,
rd_bytes_hp3,
rd_data_ddr_hp3,
rd_data_ocm_hp3,
rd_dv_ddr_hp3,
rd_dv_ocm_hp3,
/* Goes to port 1 of DDR */
ddr_wr_ack_port1,
ddr_wr_dv_port1,
ddr_rd_req_port1,
ddr_rd_dv_port1,
ddr_wr_addr_port1,
ddr_wr_data_port1,
ddr_wr_bytes_port1,
ddr_rd_addr_port1,
ddr_rd_data_port1,
ddr_rd_bytes_port1,
ddr_wr_qos_port1,
ddr_rd_qos_port1,
/* Goes to port2 of DDR */
ddr_wr_ack_port2,
ddr_wr_dv_port2,
ddr_rd_req_port2,
ddr_rd_dv_port2,
ddr_wr_addr_port2,
ddr_wr_data_port2,
ddr_wr_bytes_port2,
ddr_rd_addr_port2,
ddr_rd_data_port2,
ddr_rd_bytes_port2,
ddr_wr_qos_port2,
ddr_rd_qos_port2,
/* Goes to port3 of DDR */
ddr_wr_ack_port3,
ddr_wr_dv_port3,
ddr_rd_req_port3,
ddr_rd_dv_port3,
ddr_wr_addr_port3,
ddr_wr_data_port3,
ddr_wr_bytes_port3,
ddr_rd_addr_port3,
ddr_rd_data_port3,
ddr_rd_bytes_port3,
ddr_wr_qos_port3,
ddr_rd_qos_port3,
/* Goes to port1 of OCM */
ocm_wr_qos_port1,
ocm_rd_qos_port1,
ocm_wr_dv_port1,
ocm_wr_data_port1,
ocm_wr_addr_port1,
ocm_wr_bytes_port1,
ocm_wr_ack_port1,
ocm_rd_req_port1,
ocm_rd_data_port1,
ocm_rd_addr_port1,
ocm_rd_bytes_port1,
ocm_rd_dv_port1,
/* Goes to port1 for RegMap */
reg_rd_qos_port1,
reg_rd_req_port1,
reg_rd_data_port1,
reg_rd_addr_port1,
reg_rd_bytes_port1,
reg_rd_dv_port1
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn;
input sw_clk;
input [axi_qos_width-1:0] w_qos_gp0;
input [axi_qos_width-1:0] w_qos_gp1;
input [axi_qos_width-1:0] w_qos_hp0;
input [axi_qos_width-1:0] w_qos_hp1;
input [axi_qos_width-1:0] w_qos_hp2;
input [axi_qos_width-1:0] w_qos_hp3;
input [axi_qos_width-1:0] r_qos_gp0;
input [axi_qos_width-1:0] r_qos_gp1;
input [axi_qos_width-1:0] r_qos_hp0;
input [axi_qos_width-1:0] r_qos_hp1;
input [axi_qos_width-1:0] r_qos_hp2;
input [axi_qos_width-1:0] r_qos_hp3;
output [axi_qos_width-1:0] ocm_wr_qos_port1;
output [axi_qos_width-1:0] ocm_rd_qos_port1;
output wr_ack_ddr_gp0;
output wr_ack_ocm_gp0;
input[max_burst_bits-1:0] wr_data_gp0;
input[addr_width-1:0] wr_addr_gp0;
input[max_burst_bytes_width:0] wr_bytes_gp0;
input wr_dv_ddr_gp0;
input wr_dv_ocm_gp0;
input rd_req_ddr_gp0;
input rd_req_ocm_gp0;
input rd_req_reg_gp0;
input[addr_width-1:0] rd_addr_gp0;
input[max_burst_bytes_width:0] rd_bytes_gp0;
output[max_burst_bits-1:0] rd_data_ddr_gp0;
output[max_burst_bits-1:0] rd_data_ocm_gp0;
output[max_burst_bits-1:0] rd_data_reg_gp0;
output rd_dv_ddr_gp0;
output rd_dv_ocm_gp0;
output rd_dv_reg_gp0;
output wr_ack_ddr_gp1;
output wr_ack_ocm_gp1;
input[max_burst_bits-1:0] wr_data_gp1;
input[addr_width-1:0] wr_addr_gp1;
input[max_burst_bytes_width:0] wr_bytes_gp1;
input wr_dv_ddr_gp1;
input wr_dv_ocm_gp1;
input rd_req_ddr_gp1;
input rd_req_ocm_gp1;
input rd_req_reg_gp1;
input[addr_width-1:0] rd_addr_gp1;
input[max_burst_bytes_width:0] rd_bytes_gp1;
output[max_burst_bits-1:0] rd_data_ddr_gp1;
output[max_burst_bits-1:0] rd_data_ocm_gp1;
output[max_burst_bits-1:0] rd_data_reg_gp1;
output rd_dv_ddr_gp1;
output rd_dv_ocm_gp1;
output rd_dv_reg_gp1;
output wr_ack_ddr_hp0;
output wr_ack_ocm_hp0;
input[max_burst_bits-1:0] wr_data_hp0;
input[addr_width-1:0] wr_addr_hp0;
input[max_burst_bytes_width:0] wr_bytes_hp0;
input wr_dv_ddr_hp0;
input wr_dv_ocm_hp0;
input rd_req_ddr_hp0;
input rd_req_ocm_hp0;
input[addr_width-1:0] rd_addr_hp0;
input[max_burst_bytes_width:0] rd_bytes_hp0;
output[max_burst_bits-1:0] rd_data_ddr_hp0;
output[max_burst_bits-1:0] rd_data_ocm_hp0;
output rd_dv_ddr_hp0;
output rd_dv_ocm_hp0;
output wr_ack_ddr_hp1;
output wr_ack_ocm_hp1;
input[max_burst_bits-1:0] wr_data_hp1;
input[addr_width-1:0] wr_addr_hp1;
input[max_burst_bytes_width:0] wr_bytes_hp1;
input wr_dv_ddr_hp1;
input wr_dv_ocm_hp1;
input rd_req_ddr_hp1;
input rd_req_ocm_hp1;
input[addr_width-1:0] rd_addr_hp1;
input[max_burst_bytes_width:0] rd_bytes_hp1;
output[max_burst_bits-1:0] rd_data_ddr_hp1;
output[max_burst_bits-1:0] rd_data_ocm_hp1;
output rd_dv_ddr_hp1;
output rd_dv_ocm_hp1;
output wr_ack_ddr_hp2;
output wr_ack_ocm_hp2;
input[max_burst_bits-1:0] wr_data_hp2;
input[addr_width-1:0] wr_addr_hp2;
input[max_burst_bytes_width:0] wr_bytes_hp2;
input wr_dv_ddr_hp2;
input wr_dv_ocm_hp2;
input rd_req_ddr_hp2;
input rd_req_ocm_hp2;
input[addr_width-1:0] rd_addr_hp2;
input[max_burst_bytes_width:0] rd_bytes_hp2;
output[max_burst_bits-1:0] rd_data_ddr_hp2;
output[max_burst_bits-1:0] rd_data_ocm_hp2;
output rd_dv_ddr_hp2;
output rd_dv_ocm_hp2;
output wr_ack_ddr_hp3;
output wr_ack_ocm_hp3;
input[max_burst_bits-1:0] wr_data_hp3;
input[addr_width-1:0] wr_addr_hp3;
input[max_burst_bytes_width:0] wr_bytes_hp3;
input wr_dv_ddr_hp3;
input wr_dv_ocm_hp3;
input rd_req_ddr_hp3;
input rd_req_ocm_hp3;
input[addr_width-1:0] rd_addr_hp3;
input[max_burst_bytes_width:0] rd_bytes_hp3;
output[max_burst_bits-1:0] rd_data_ddr_hp3;
output[max_burst_bits-1:0] rd_data_ocm_hp3;
output rd_dv_ddr_hp3;
output rd_dv_ocm_hp3;
/* Goes to port 1 of DDR */
input ddr_wr_ack_port1;
output ddr_wr_dv_port1;
output ddr_rd_req_port1;
input ddr_rd_dv_port1;
output[addr_width-1:0] ddr_wr_addr_port1;
output[max_burst_bits-1:0] ddr_wr_data_port1;
output[max_burst_bytes_width:0] ddr_wr_bytes_port1;
output[addr_width-1:0] ddr_rd_addr_port1;
input[max_burst_bits-1:0] ddr_rd_data_port1;
output[max_burst_bytes_width:0] ddr_rd_bytes_port1;
output [axi_qos_width-1:0] ddr_wr_qos_port1;
output [axi_qos_width-1:0] ddr_rd_qos_port1;
/* Goes to port2 of DDR */
input ddr_wr_ack_port2;
output ddr_wr_dv_port2;
output ddr_rd_req_port2;
input ddr_rd_dv_port2;
output[addr_width-1:0] ddr_wr_addr_port2;
output[max_burst_bits-1:0] ddr_wr_data_port2;
output[max_burst_bytes_width:0] ddr_wr_bytes_port2;
output[addr_width-1:0] ddr_rd_addr_port2;
input[max_burst_bits-1:0] ddr_rd_data_port2;
output[max_burst_bytes_width:0] ddr_rd_bytes_port2;
output [axi_qos_width-1:0] ddr_wr_qos_port2;
output [axi_qos_width-1:0] ddr_rd_qos_port2;
/* Goes to port3 of DDR */
input ddr_wr_ack_port3;
output ddr_wr_dv_port3;
output ddr_rd_req_port3;
input ddr_rd_dv_port3;
output[addr_width-1:0] ddr_wr_addr_port3;
output[max_burst_bits-1:0] ddr_wr_data_port3;
output[max_burst_bytes_width:0] ddr_wr_bytes_port3;
output[addr_width-1:0] ddr_rd_addr_port3;
input[max_burst_bits-1:0] ddr_rd_data_port3;
output[max_burst_bytes_width:0] ddr_rd_bytes_port3;
output [axi_qos_width-1:0] ddr_wr_qos_port3;
output [axi_qos_width-1:0] ddr_rd_qos_port3;
/* Goes to port1 of OCM */
input ocm_wr_ack_port1;
output ocm_wr_dv_port1;
output ocm_rd_req_port1;
input ocm_rd_dv_port1;
output[max_burst_bits-1:0] ocm_wr_data_port1;
output[addr_width-1:0] ocm_wr_addr_port1;
output[max_burst_bytes_width:0] ocm_wr_bytes_port1;
input[max_burst_bits-1:0] ocm_rd_data_port1;
output[addr_width-1:0] ocm_rd_addr_port1;
output[max_burst_bytes_width:0] ocm_rd_bytes_port1;
/* Goes to port1 of REG */
output [axi_qos_width-1:0] reg_rd_qos_port1;
output reg_rd_req_port1;
input reg_rd_dv_port1;
input[max_burst_bits-1:0] reg_rd_data_port1;
output[addr_width-1:0] reg_rd_addr_port1;
output[max_burst_bytes_width:0] reg_rd_bytes_port1;
wire ocm_wr_dv_osw0;
wire ocm_wr_dv_osw1;
wire[max_burst_bits-1:0] ocm_wr_data_osw0;
wire[max_burst_bits-1:0] ocm_wr_data_osw1;
wire[addr_width-1:0] ocm_wr_addr_osw0;
wire[addr_width-1:0] ocm_wr_addr_osw1;
wire[max_burst_bytes_width:0] ocm_wr_bytes_osw0;
wire[max_burst_bytes_width:0] ocm_wr_bytes_osw1;
wire ocm_wr_ack_osw0;
wire ocm_wr_ack_osw1;
wire ocm_rd_req_osw0;
wire ocm_rd_req_osw1;
wire[max_burst_bits-1:0] ocm_rd_data_osw0;
wire[max_burst_bits-1:0] ocm_rd_data_osw1;
wire[addr_width-1:0] ocm_rd_addr_osw0;
wire[addr_width-1:0] ocm_rd_addr_osw1;
wire[max_burst_bytes_width:0] ocm_rd_bytes_osw0;
wire[max_burst_bytes_width:0] ocm_rd_bytes_osw1;
wire ocm_rd_dv_osw0;
wire ocm_rd_dv_osw1;
wire [axi_qos_width-1:0] ocm_wr_qos_osw0;
wire [axi_qos_width-1:0] ocm_wr_qos_osw1;
wire [axi_qos_width-1:0] ocm_rd_qos_osw0;
wire [axi_qos_width-1:0] ocm_rd_qos_osw1;
processing_system7_bfm_v2_0_5_fmsw_gp fmsw (
.sw_clk(sw_clk),
.rstn(rstn),
.w_qos_gp0(w_qos_gp0),
.r_qos_gp0(r_qos_gp0),
.wr_ack_ocm_gp0(wr_ack_ocm_gp0),
.wr_ack_ddr_gp0(wr_ack_ddr_gp0),
.wr_data_gp0(wr_data_gp0),
.wr_addr_gp0(wr_addr_gp0),
.wr_bytes_gp0(wr_bytes_gp0),
.wr_dv_ocm_gp0(wr_dv_ocm_gp0),
.wr_dv_ddr_gp0(wr_dv_ddr_gp0),
.rd_req_ocm_gp0(rd_req_ocm_gp0),
.rd_req_ddr_gp0(rd_req_ddr_gp0),
.rd_req_reg_gp0(rd_req_reg_gp0),
.rd_addr_gp0(rd_addr_gp0),
.rd_bytes_gp0(rd_bytes_gp0),
.rd_data_ddr_gp0(rd_data_ddr_gp0),
.rd_data_ocm_gp0(rd_data_ocm_gp0),
.rd_data_reg_gp0(rd_data_reg_gp0),
.rd_dv_ocm_gp0(rd_dv_ocm_gp0),
.rd_dv_ddr_gp0(rd_dv_ddr_gp0),
.rd_dv_reg_gp0(rd_dv_reg_gp0),
.w_qos_gp1(w_qos_gp1),
.r_qos_gp1(r_qos_gp1),
.wr_ack_ocm_gp1(wr_ack_ocm_gp1),
.wr_ack_ddr_gp1(wr_ack_ddr_gp1),
.wr_data_gp1(wr_data_gp1),
.wr_addr_gp1(wr_addr_gp1),
.wr_bytes_gp1(wr_bytes_gp1),
.wr_dv_ocm_gp1(wr_dv_ocm_gp1),
.wr_dv_ddr_gp1(wr_dv_ddr_gp1),
.rd_req_ocm_gp1(rd_req_ocm_gp1),
.rd_req_ddr_gp1(rd_req_ddr_gp1),
.rd_req_reg_gp1(rd_req_reg_gp1),
.rd_addr_gp1(rd_addr_gp1),
.rd_bytes_gp1(rd_bytes_gp1),
.rd_data_ddr_gp1(rd_data_ddr_gp1),
.rd_data_ocm_gp1(rd_data_ocm_gp1),
.rd_data_reg_gp1(rd_data_reg_gp1),
.rd_dv_ocm_gp1(rd_dv_ocm_gp1),
.rd_dv_ddr_gp1(rd_dv_ddr_gp1),
.rd_dv_reg_gp1(rd_dv_reg_gp1),
.ocm_wr_ack (ocm_wr_ack_osw0),
.ocm_wr_dv (ocm_wr_dv_osw0),
.ocm_rd_req (ocm_rd_req_osw0),
.ocm_rd_dv (ocm_rd_dv_osw0),
.ocm_wr_addr(ocm_wr_addr_osw0),
.ocm_wr_data(ocm_wr_data_osw0),
.ocm_wr_bytes(ocm_wr_bytes_osw0),
.ocm_rd_addr(ocm_rd_addr_osw0),
.ocm_rd_data(ocm_rd_data_osw0),
.ocm_rd_bytes(ocm_rd_bytes_osw0),
.ocm_wr_qos(ocm_wr_qos_osw0),
.ocm_rd_qos(ocm_rd_qos_osw0),
.ddr_wr_qos(ddr_wr_qos_port1),
.ddr_rd_qos(ddr_rd_qos_port1),
.reg_rd_qos(reg_rd_qos_port1),
.ddr_wr_ack(ddr_wr_ack_port1),
.ddr_wr_dv(ddr_wr_dv_port1),
.ddr_rd_req(ddr_rd_req_port1),
.ddr_rd_dv(ddr_rd_dv_port1),
.ddr_wr_addr(ddr_wr_addr_port1),
.ddr_wr_data(ddr_wr_data_port1),
.ddr_wr_bytes(ddr_wr_bytes_port1),
.ddr_rd_addr(ddr_rd_addr_port1),
.ddr_rd_data(ddr_rd_data_port1),
.ddr_rd_bytes(ddr_rd_bytes_port1),
.reg_rd_req(reg_rd_req_port1),
.reg_rd_dv(reg_rd_dv_port1),
.reg_rd_addr(reg_rd_addr_port1),
.reg_rd_data(reg_rd_data_port1),
.reg_rd_bytes(reg_rd_bytes_port1)
);
processing_system7_bfm_v2_0_5_ssw_hp ssw(
.sw_clk(sw_clk),
.rstn(rstn),
.w_qos_hp0(w_qos_hp0),
.r_qos_hp0(r_qos_hp0),
.w_qos_hp1(w_qos_hp1),
.r_qos_hp1(r_qos_hp1),
.w_qos_hp2(w_qos_hp2),
.r_qos_hp2(r_qos_hp2),
.w_qos_hp3(w_qos_hp3),
.r_qos_hp3(r_qos_hp3),
.wr_ack_ddr_hp0(wr_ack_ddr_hp0),
.wr_data_hp0(wr_data_hp0),
.wr_addr_hp0(wr_addr_hp0),
.wr_bytes_hp0(wr_bytes_hp0),
.wr_dv_ddr_hp0(wr_dv_ddr_hp0),
.rd_req_ddr_hp0(rd_req_ddr_hp0),
.rd_addr_hp0(rd_addr_hp0),
.rd_bytes_hp0(rd_bytes_hp0),
.rd_data_ddr_hp0(rd_data_ddr_hp0),
.rd_data_ocm_hp0(rd_data_ocm_hp0),
.rd_dv_ddr_hp0(rd_dv_ddr_hp0),
.wr_ack_ocm_hp0(wr_ack_ocm_hp0),
.wr_dv_ocm_hp0(wr_dv_ocm_hp0),
.rd_req_ocm_hp0(rd_req_ocm_hp0),
.rd_dv_ocm_hp0(rd_dv_ocm_hp0),
.wr_ack_ddr_hp1(wr_ack_ddr_hp1),
.wr_data_hp1(wr_data_hp1),
.wr_addr_hp1(wr_addr_hp1),
.wr_bytes_hp1(wr_bytes_hp1),
.wr_dv_ddr_hp1(wr_dv_ddr_hp1),
.rd_req_ddr_hp1(rd_req_ddr_hp1),
.rd_addr_hp1(rd_addr_hp1),
.rd_bytes_hp1(rd_bytes_hp1),
.rd_data_ddr_hp1(rd_data_ddr_hp1),
.rd_data_ocm_hp1(rd_data_ocm_hp1),
.rd_dv_ddr_hp1(rd_dv_ddr_hp1),
.wr_ack_ocm_hp1(wr_ack_ocm_hp1),
.wr_dv_ocm_hp1(wr_dv_ocm_hp1),
.rd_req_ocm_hp1(rd_req_ocm_hp1),
.rd_dv_ocm_hp1(rd_dv_ocm_hp1),
.wr_ack_ddr_hp2(wr_ack_ddr_hp2),
.wr_data_hp2(wr_data_hp2),
.wr_addr_hp2(wr_addr_hp2),
.wr_bytes_hp2(wr_bytes_hp2),
.wr_dv_ddr_hp2(wr_dv_ddr_hp2),
.rd_req_ddr_hp2(rd_req_ddr_hp2),
.rd_addr_hp2(rd_addr_hp2),
.rd_bytes_hp2(rd_bytes_hp2),
.rd_data_ddr_hp2(rd_data_ddr_hp2),
.rd_data_ocm_hp2(rd_data_ocm_hp2),
.rd_dv_ddr_hp2(rd_dv_ddr_hp2),
.wr_ack_ocm_hp2(wr_ack_ocm_hp2),
.wr_dv_ocm_hp2(wr_dv_ocm_hp2),
.rd_req_ocm_hp2(rd_req_ocm_hp2),
.rd_dv_ocm_hp2(rd_dv_ocm_hp2),
.wr_ack_ddr_hp3(wr_ack_ddr_hp3),
.wr_data_hp3(wr_data_hp3),
.wr_addr_hp3(wr_addr_hp3),
.wr_bytes_hp3(wr_bytes_hp3),
.wr_dv_ddr_hp3(wr_dv_ddr_hp3),
.rd_req_ddr_hp3(rd_req_ddr_hp3),
.rd_addr_hp3(rd_addr_hp3),
.rd_bytes_hp3(rd_bytes_hp3),
.rd_data_ddr_hp3(rd_data_ddr_hp3),
.rd_data_ocm_hp3(rd_data_ocm_hp3),
.rd_dv_ddr_hp3(rd_dv_ddr_hp3),
.wr_ack_ocm_hp3(wr_ack_ocm_hp3),
.wr_dv_ocm_hp3(wr_dv_ocm_hp3),
.rd_req_ocm_hp3(rd_req_ocm_hp3),
.rd_dv_ocm_hp3(rd_dv_ocm_hp3),
.ddr_wr_ack0(ddr_wr_ack_port2),
.ddr_wr_dv0(ddr_wr_dv_port2),
.ddr_rd_req0(ddr_rd_req_port2),
.ddr_rd_dv0(ddr_rd_dv_port2),
.ddr_wr_addr0(ddr_wr_addr_port2),
.ddr_wr_data0(ddr_wr_data_port2),
.ddr_wr_bytes0(ddr_wr_bytes_port2),
.ddr_rd_addr0(ddr_rd_addr_port2),
.ddr_rd_data0(ddr_rd_data_port2),
.ddr_rd_bytes0(ddr_rd_bytes_port2),
.ddr_wr_qos0(ddr_wr_qos_port2),
.ddr_rd_qos0(ddr_rd_qos_port2),
.ddr_wr_ack1(ddr_wr_ack_port3),
.ddr_wr_dv1(ddr_wr_dv_port3),
.ddr_rd_req1(ddr_rd_req_port3),
.ddr_rd_dv1(ddr_rd_dv_port3),
.ddr_wr_addr1(ddr_wr_addr_port3),
.ddr_wr_data1(ddr_wr_data_port3),
.ddr_wr_bytes1(ddr_wr_bytes_port3),
.ddr_rd_addr1(ddr_rd_addr_port3),
.ddr_rd_data1(ddr_rd_data_port3),
.ddr_rd_bytes1(ddr_rd_bytes_port3),
.ddr_wr_qos1(ddr_wr_qos_port3),
.ddr_rd_qos1(ddr_rd_qos_port3),
.ocm_wr_qos(ocm_wr_qos_osw1),
.ocm_rd_qos(ocm_rd_qos_osw1),
.ocm_wr_ack (ocm_wr_ack_osw1),
.ocm_wr_dv (ocm_wr_dv_osw1),
.ocm_rd_req (ocm_rd_req_osw1),
.ocm_rd_dv (ocm_rd_dv_osw1),
.ocm_wr_addr(ocm_wr_addr_osw1),
.ocm_wr_data(ocm_wr_data_osw1),
.ocm_wr_bytes(ocm_wr_bytes_osw1),
.ocm_rd_addr(ocm_rd_addr_osw1),
.ocm_rd_data(ocm_rd_data_osw1),
.ocm_rd_bytes(ocm_rd_bytes_osw1)
);
processing_system7_bfm_v2_0_5_arb_wr osw_wr (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ocm_wr_qos_osw0), /// chk
.qos2(ocm_wr_qos_osw1), /// chk
.prt_dv1(ocm_wr_dv_osw0),
.prt_dv2(ocm_wr_dv_osw1),
.prt_data1(ocm_wr_data_osw0),
.prt_data2(ocm_wr_data_osw1),
.prt_addr1(ocm_wr_addr_osw0),
.prt_addr2(ocm_wr_addr_osw1),
.prt_bytes1(ocm_wr_bytes_osw0),
.prt_bytes2(ocm_wr_bytes_osw1),
.prt_ack1(ocm_wr_ack_osw0),
.prt_ack2(ocm_wr_ack_osw1),
.prt_req(ocm_wr_dv_port1),
.prt_qos(ocm_wr_qos_port1),
.prt_data(ocm_wr_data_port1),
.prt_addr(ocm_wr_addr_port1),
.prt_bytes(ocm_wr_bytes_port1),
.prt_ack(ocm_wr_ack_port1)
);
processing_system7_bfm_v2_0_5_arb_rd osw_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ocm_rd_qos_osw0), // chk
.qos2(ocm_rd_qos_osw1), // chk
.prt_req1(ocm_rd_req_osw0),
.prt_req2(ocm_rd_req_osw1),
.prt_data1(ocm_rd_data_osw0),
.prt_data2(ocm_rd_data_osw1),
.prt_addr1(ocm_rd_addr_osw0),
.prt_addr2(ocm_rd_addr_osw1),
.prt_bytes1(ocm_rd_bytes_osw0),
.prt_bytes2(ocm_rd_bytes_osw1),
.prt_dv1(ocm_rd_dv_osw0),
.prt_dv2(ocm_rd_dv_osw1),
.prt_req(ocm_rd_req_port1),
.prt_qos(ocm_rd_qos_port1),
.prt_data(ocm_rd_data_port1),
.prt_addr(ocm_rd_addr_port1),
.prt_bytes(ocm_rd_bytes_port1),
.prt_dv(ocm_rd_dv_port1)
);
endmodule |
module processing_system7_bfm_v2_0_5_arb_wr_4(
rstn,
sw_clk,
qos1,
qos2,
qos3,
qos4,
prt_dv1,
prt_dv2,
prt_dv3,
prt_dv4,
prt_data1,
prt_data2,
prt_data3,
prt_data4,
prt_addr1,
prt_addr2,
prt_addr3,
prt_addr4,
prt_bytes1,
prt_bytes2,
prt_bytes3,
prt_bytes4,
prt_ack1,
prt_ack2,
prt_ack3,
prt_ack4,
prt_qos,
prt_req,
prt_data,
prt_addr,
prt_bytes,
prt_ack
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2,qos3,qos4;
input [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4;
input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4;
input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4;
input prt_dv1, prt_dv2,prt_dv3, prt_dv4, prt_ack;
output reg prt_ack1,prt_ack2,prt_ack3,prt_ack4,prt_req;
output reg [max_burst_bits-1:0] prt_data;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
output reg [axi_qos_width-1:0] prt_qos;
parameter wait_req = 3'b000, serv_req1 = 3'b001, serv_req2 = 3'b010, serv_req3 = 3'b011, serv_req4 = 4'b100,wait_ack_low = 3'b101;
reg [2:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
prt_req = 0;
if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
serv_req1:begin
state = serv_req1;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack1 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv2) begin
state = serv_req2;
prt_qos = qos2;
prt_req = 1;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
end
serv_req2:begin
state = serv_req2;
prt_ack1 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack2 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv3) begin
state = serv_req3;
prt_qos = qos3;
prt_req = 1;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
state = serv_req4;
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_dv1) begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req3:begin
state = serv_req3;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack3 = 1'b1;
// state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv4) begin
state = serv_req4;
prt_qos = qos4;
prt_req = 1;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end
end
end
serv_req4:begin
state = serv_req4;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
if(prt_ack)begin
prt_ack4 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
state = serv_req3;
end
end
end
wait_ack_low:begin
state = wait_ack_low;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(!prt_ack)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule |
module processing_system7_bfm_v2_0_5_arb_wr_4(
rstn,
sw_clk,
qos1,
qos2,
qos3,
qos4,
prt_dv1,
prt_dv2,
prt_dv3,
prt_dv4,
prt_data1,
prt_data2,
prt_data3,
prt_data4,
prt_addr1,
prt_addr2,
prt_addr3,
prt_addr4,
prt_bytes1,
prt_bytes2,
prt_bytes3,
prt_bytes4,
prt_ack1,
prt_ack2,
prt_ack3,
prt_ack4,
prt_qos,
prt_req,
prt_data,
prt_addr,
prt_bytes,
prt_ack
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2,qos3,qos4;
input [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4;
input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4;
input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4;
input prt_dv1, prt_dv2,prt_dv3, prt_dv4, prt_ack;
output reg prt_ack1,prt_ack2,prt_ack3,prt_ack4,prt_req;
output reg [max_burst_bits-1:0] prt_data;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
output reg [axi_qos_width-1:0] prt_qos;
parameter wait_req = 3'b000, serv_req1 = 3'b001, serv_req2 = 3'b010, serv_req3 = 3'b011, serv_req4 = 4'b100,wait_ack_low = 3'b101;
reg [2:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
prt_req = 0;
if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
serv_req1:begin
state = serv_req1;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack1 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv2) begin
state = serv_req2;
prt_qos = qos2;
prt_req = 1;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
end
serv_req2:begin
state = serv_req2;
prt_ack1 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack2 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv3) begin
state = serv_req3;
prt_qos = qos3;
prt_req = 1;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
state = serv_req4;
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_dv1) begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req3:begin
state = serv_req3;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack3 = 1'b1;
// state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv4) begin
state = serv_req4;
prt_qos = qos4;
prt_req = 1;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end
end
end
serv_req4:begin
state = serv_req4;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
if(prt_ack)begin
prt_ack4 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
state = serv_req3;
end
end
end
wait_ack_low:begin
state = wait_ack_low;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(!prt_ack)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule |
module processing_system7_bfm_v2_0_5_arb_wr_4(
rstn,
sw_clk,
qos1,
qos2,
qos3,
qos4,
prt_dv1,
prt_dv2,
prt_dv3,
prt_dv4,
prt_data1,
prt_data2,
prt_data3,
prt_data4,
prt_addr1,
prt_addr2,
prt_addr3,
prt_addr4,
prt_bytes1,
prt_bytes2,
prt_bytes3,
prt_bytes4,
prt_ack1,
prt_ack2,
prt_ack3,
prt_ack4,
prt_qos,
prt_req,
prt_data,
prt_addr,
prt_bytes,
prt_ack
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2,qos3,qos4;
input [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4;
input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4;
input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4;
input prt_dv1, prt_dv2,prt_dv3, prt_dv4, prt_ack;
output reg prt_ack1,prt_ack2,prt_ack3,prt_ack4,prt_req;
output reg [max_burst_bits-1:0] prt_data;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
output reg [axi_qos_width-1:0] prt_qos;
parameter wait_req = 3'b000, serv_req1 = 3'b001, serv_req2 = 3'b010, serv_req3 = 3'b011, serv_req4 = 4'b100,wait_ack_low = 3'b101;
reg [2:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
prt_req = 0;
if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
serv_req1:begin
state = serv_req1;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack1 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv2) begin
state = serv_req2;
prt_qos = qos2;
prt_req = 1;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
end
serv_req2:begin
state = serv_req2;
prt_ack1 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack2 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv3) begin
state = serv_req3;
prt_qos = qos3;
prt_req = 1;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
state = serv_req4;
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_dv1) begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req3:begin
state = serv_req3;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack3 = 1'b1;
// state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv4) begin
state = serv_req4;
prt_qos = qos4;
prt_req = 1;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end
end
end
serv_req4:begin
state = serv_req4;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
if(prt_ack)begin
prt_ack4 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
state = serv_req3;
end
end
end
wait_ack_low:begin
state = wait_ack_low;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(!prt_ack)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule |
module processing_system7_bfm_v2_0_5_arb_wr_4(
rstn,
sw_clk,
qos1,
qos2,
qos3,
qos4,
prt_dv1,
prt_dv2,
prt_dv3,
prt_dv4,
prt_data1,
prt_data2,
prt_data3,
prt_data4,
prt_addr1,
prt_addr2,
prt_addr3,
prt_addr4,
prt_bytes1,
prt_bytes2,
prt_bytes3,
prt_bytes4,
prt_ack1,
prt_ack2,
prt_ack3,
prt_ack4,
prt_qos,
prt_req,
prt_data,
prt_addr,
prt_bytes,
prt_ack
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2,qos3,qos4;
input [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4;
input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4;
input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4;
input prt_dv1, prt_dv2,prt_dv3, prt_dv4, prt_ack;
output reg prt_ack1,prt_ack2,prt_ack3,prt_ack4,prt_req;
output reg [max_burst_bits-1:0] prt_data;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
output reg [axi_qos_width-1:0] prt_qos;
parameter wait_req = 3'b000, serv_req1 = 3'b001, serv_req2 = 3'b010, serv_req3 = 3'b011, serv_req4 = 4'b100,wait_ack_low = 3'b101;
reg [2:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
prt_req = 0;
if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
serv_req1:begin
state = serv_req1;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack1 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv2) begin
state = serv_req2;
prt_qos = qos2;
prt_req = 1;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
end
serv_req2:begin
state = serv_req2;
prt_ack1 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack2 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv3) begin
state = serv_req3;
prt_qos = qos3;
prt_req = 1;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
state = serv_req4;
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_dv1) begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req3:begin
state = serv_req3;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack3 = 1'b1;
// state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv4) begin
state = serv_req4;
prt_qos = qos4;
prt_req = 1;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end
end
end
serv_req4:begin
state = serv_req4;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
if(prt_ack)begin
prt_ack4 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
state = serv_req3;
end
end
end
wait_ack_low:begin
state = wait_ack_low;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(!prt_ack)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule |
module processing_system7_bfm_v2_0_5_gen_reset(
por_rst_n,
sys_rst_n,
rst_out_n,
m_axi_gp0_clk,
m_axi_gp1_clk,
s_axi_gp0_clk,
s_axi_gp1_clk,
s_axi_hp0_clk,
s_axi_hp1_clk,
s_axi_hp2_clk,
s_axi_hp3_clk,
s_axi_acp_clk,
m_axi_gp0_rstn,
m_axi_gp1_rstn,
s_axi_gp0_rstn,
s_axi_gp1_rstn,
s_axi_hp0_rstn,
s_axi_hp1_rstn,
s_axi_hp2_rstn,
s_axi_hp3_rstn,
s_axi_acp_rstn,
fclk_reset3_n,
fclk_reset2_n,
fclk_reset1_n,
fclk_reset0_n,
fpga_acp_reset_n,
fpga_gp_m0_reset_n,
fpga_gp_m1_reset_n,
fpga_gp_s0_reset_n,
fpga_gp_s1_reset_n,
fpga_hp_s0_reset_n,
fpga_hp_s1_reset_n,
fpga_hp_s2_reset_n,
fpga_hp_s3_reset_n
);
input por_rst_n;
input sys_rst_n;
input m_axi_gp0_clk;
input m_axi_gp1_clk;
input s_axi_gp0_clk;
input s_axi_gp1_clk;
input s_axi_hp0_clk;
input s_axi_hp1_clk;
input s_axi_hp2_clk;
input s_axi_hp3_clk;
input s_axi_acp_clk;
output reg m_axi_gp0_rstn;
output reg m_axi_gp1_rstn;
output reg s_axi_gp0_rstn;
output reg s_axi_gp1_rstn;
output reg s_axi_hp0_rstn;
output reg s_axi_hp1_rstn;
output reg s_axi_hp2_rstn;
output reg s_axi_hp3_rstn;
output reg s_axi_acp_rstn;
output rst_out_n;
output fclk_reset3_n;
output fclk_reset2_n;
output fclk_reset1_n;
output fclk_reset0_n;
output fpga_acp_reset_n;
output fpga_gp_m0_reset_n;
output fpga_gp_m1_reset_n;
output fpga_gp_s0_reset_n;
output fpga_gp_s1_reset_n;
output fpga_hp_s0_reset_n;
output fpga_hp_s1_reset_n;
output fpga_hp_s2_reset_n;
output fpga_hp_s3_reset_n;
reg [31:0] fabric_rst_n;
reg r_m_axi_gp0_rstn;
reg r_m_axi_gp1_rstn;
reg r_s_axi_gp0_rstn;
reg r_s_axi_gp1_rstn;
reg r_s_axi_hp0_rstn;
reg r_s_axi_hp1_rstn;
reg r_s_axi_hp2_rstn;
reg r_s_axi_hp3_rstn;
reg r_s_axi_acp_rstn;
assign rst_out_n = por_rst_n & sys_rst_n;
assign fclk_reset0_n = !fabric_rst_n[0];
assign fclk_reset1_n = !fabric_rst_n[1];
assign fclk_reset2_n = !fabric_rst_n[2];
assign fclk_reset3_n = !fabric_rst_n[3];
assign fpga_acp_reset_n = !fabric_rst_n[24];
assign fpga_hp_s3_reset_n = !fabric_rst_n[23];
assign fpga_hp_s2_reset_n = !fabric_rst_n[22];
assign fpga_hp_s1_reset_n = !fabric_rst_n[21];
assign fpga_hp_s0_reset_n = !fabric_rst_n[20];
assign fpga_gp_s1_reset_n = !fabric_rst_n[17];
assign fpga_gp_s0_reset_n = !fabric_rst_n[16];
assign fpga_gp_m1_reset_n = !fabric_rst_n[13];
assign fpga_gp_m0_reset_n = !fabric_rst_n[12];
task fpga_soft_reset;
input[31:0] reset_ctrl;
begin
fabric_rst_n[0] = reset_ctrl[0];
fabric_rst_n[1] = reset_ctrl[1];
fabric_rst_n[2] = reset_ctrl[2];
fabric_rst_n[3] = reset_ctrl[3];
fabric_rst_n[12] = reset_ctrl[12];
fabric_rst_n[13] = reset_ctrl[13];
fabric_rst_n[16] = reset_ctrl[16];
fabric_rst_n[17] = reset_ctrl[17];
fabric_rst_n[20] = reset_ctrl[20];
fabric_rst_n[21] = reset_ctrl[21];
fabric_rst_n[22] = reset_ctrl[22];
fabric_rst_n[23] = reset_ctrl[23];
fabric_rst_n[24] = reset_ctrl[24];
end
endtask
always@(negedge por_rst_n or negedge sys_rst_n) fabric_rst_n = 32'h01f3_300f;
always@(posedge m_axi_gp0_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
m_axi_gp0_rstn = 1'b0;
else
m_axi_gp0_rstn = 1'b1;
end
always@(posedge m_axi_gp1_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
m_axi_gp1_rstn = 1'b0;
else
m_axi_gp1_rstn = 1'b1;
end
always@(posedge s_axi_gp0_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_gp0_rstn = 1'b0;
else
s_axi_gp0_rstn = 1'b1;
end
always@(posedge s_axi_gp1_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_gp1_rstn = 1'b0;
else
s_axi_gp1_rstn = 1'b1;
end
always@(posedge s_axi_hp0_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_hp0_rstn = 1'b0;
else
s_axi_hp0_rstn = 1'b1;
end
always@(posedge s_axi_hp1_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_hp1_rstn = 1'b0;
else
s_axi_hp1_rstn = 1'b1;
end
always@(posedge s_axi_hp2_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_hp2_rstn = 1'b0;
else
s_axi_hp2_rstn = 1'b1;
end
always@(posedge s_axi_hp3_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_hp3_rstn = 1'b0;
else
s_axi_hp3_rstn = 1'b1;
end
always@(posedge s_axi_acp_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_acp_rstn = 1'b0;
else
s_axi_acp_rstn = 1'b1;
end
always@(*) begin
if ((por_rst_n!= 1'b0) && (por_rst_n!= 1'b1) && (sys_rst_n != 1'b0) && (sys_rst_n != 1'b1)) begin
$display(" Error:processing_system7_bfm_v2_0_5_gen_reset. PS_PORB and PS_SRSTB must be driven to known state");
$finish();
end
end
endmodule |
module axi_crossbar_v2_1_addr_arbiter_sasd #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_S = 1,
parameter integer C_NUM_S_LOG = 1,
parameter integer C_AMESG_WIDTH = 1,
parameter C_GRANT_ENC = 0,
parameter [C_NUM_S*32-1:0] C_ARB_PRIORITY = {C_NUM_S{32'h00000000}}
// Arbitration priority among each SI slot.
// Higher values indicate higher priority.
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 'h0-'hF.
)
(
// Global Signals
input wire ACLK,
input wire ARESET,
// Slave Ports
input wire [C_NUM_S*C_AMESG_WIDTH-1:0] S_AWMESG,
input wire [C_NUM_S*C_AMESG_WIDTH-1:0] S_ARMESG,
input wire [C_NUM_S-1:0] S_AWVALID,
output wire [C_NUM_S-1:0] S_AWREADY,
input wire [C_NUM_S-1:0] S_ARVALID,
output wire [C_NUM_S-1:0] S_ARREADY,
// Master Ports
output wire [C_AMESG_WIDTH-1:0] M_AMESG,
output wire [C_NUM_S_LOG-1:0] M_GRANT_ENC,
output wire [C_NUM_S-1:0] M_GRANT_HOT,
output wire M_GRANT_RNW,
output wire M_GRANT_ANY,
output wire M_AWVALID,
input wire M_AWREADY,
output wire M_ARVALID,
input wire M_ARREADY
);
// Generates a mask for all input slots that are priority based
function [C_NUM_S-1:0] f_prio_mask
(
input integer null_arg
);
reg [C_NUM_S-1:0] mask;
integer i;
begin
mask = 0;
for (i=0; i < C_NUM_S; i=i+1) begin
mask[i] = (C_ARB_PRIORITY[i*32+:32] != 0);
end
f_prio_mask = mask;
end
endfunction
// Convert 16-bit one-hot to 4-bit binary
function [3:0] f_hot2enc
(
input [15:0] one_hot
);
begin
f_hot2enc[0] = |(one_hot & 16'b1010101010101010);
f_hot2enc[1] = |(one_hot & 16'b1100110011001100);
f_hot2enc[2] = |(one_hot & 16'b1111000011110000);
f_hot2enc[3] = |(one_hot & 16'b1111111100000000);
end
endfunction
localparam [C_NUM_S-1:0] P_PRIO_MASK = f_prio_mask(0);
reg m_valid_i;
reg [C_NUM_S-1:0] s_ready_i;
reg [C_NUM_S-1:0] s_awvalid_reg;
reg [C_NUM_S-1:0] s_arvalid_reg;
wire [15:0] s_avalid;
wire m_aready;
wire [C_NUM_S-1:0] rnw;
reg grant_rnw;
reg [C_NUM_S_LOG-1:0] m_grant_enc_i;
reg [C_NUM_S-1:0] m_grant_hot_i;
reg [C_NUM_S-1:0] last_rr_hot;
reg any_grant;
reg any_prio;
reg [C_NUM_S-1:0] which_prio_hot;
reg [C_NUM_S_LOG-1:0] which_prio_enc;
reg [4:0] current_highest;
reg [15:0] next_prio_hot;
reg [C_NUM_S_LOG-1:0] next_prio_enc;
reg found_prio;
wire [C_NUM_S-1:0] valid_rr;
reg [15:0] next_rr_hot;
reg [C_NUM_S_LOG-1:0] next_rr_enc;
reg [C_NUM_S*C_NUM_S-1:0] carry_rr;
reg [C_NUM_S*C_NUM_S-1:0] mask_rr;
reg found_rr;
wire [C_NUM_S-1:0] next_hot;
wire [C_NUM_S_LOG-1:0] next_enc;
integer i;
wire [C_AMESG_WIDTH-1:0] amesg_mux;
reg [C_AMESG_WIDTH-1:0] m_amesg_i;
wire [C_NUM_S*C_AMESG_WIDTH-1:0] s_amesg;
genvar gen_si;
always @(posedge ACLK) begin
if (ARESET) begin
s_awvalid_reg <= 0;
s_arvalid_reg <= 0;
end else if (|s_ready_i) begin
s_awvalid_reg <= 0;
s_arvalid_reg <= 0;
end else begin
s_arvalid_reg <= S_ARVALID & ~s_awvalid_reg;
s_awvalid_reg <= S_AWVALID & ~s_arvalid_reg & (~S_ARVALID | s_awvalid_reg);
end
end
assign s_avalid = S_AWVALID | S_ARVALID;
assign M_AWVALID = m_valid_i & ~grant_rnw;
assign M_ARVALID = m_valid_i & grant_rnw;
assign S_AWREADY = s_ready_i & {C_NUM_S{~grant_rnw}};
assign S_ARREADY = s_ready_i & {C_NUM_S{grant_rnw}};
assign M_GRANT_ENC = C_GRANT_ENC ? m_grant_enc_i : 0;
assign M_GRANT_HOT = m_grant_hot_i;
assign M_GRANT_RNW = grant_rnw;
assign rnw = S_ARVALID & ~s_awvalid_reg;
assign M_AMESG = m_amesg_i;
assign m_aready = grant_rnw ? M_ARREADY : M_AWREADY;
generate
for (gen_si=0; gen_si<C_NUM_S; gen_si=gen_si+1) begin : gen_mesg_mux
assign s_amesg[C_AMESG_WIDTH*gen_si +: C_AMESG_WIDTH] = rnw[gen_si] ? S_ARMESG[C_AMESG_WIDTH*gen_si +: C_AMESG_WIDTH] : S_AWMESG[C_AMESG_WIDTH*gen_si +: C_AMESG_WIDTH];
end // gen_mesg_mux
if (C_NUM_S>1) begin : gen_arbiter
/////////////////////////////////////////////////////////////////////////////
// Grant a new request when there is none still pending.
// If no qualified requests found, de-assert M_VALID.
/////////////////////////////////////////////////////////////////////////////
assign M_GRANT_ANY = any_grant;
assign next_hot = found_prio ? next_prio_hot : next_rr_hot;
assign next_enc = found_prio ? next_prio_enc : next_rr_enc;
always @(posedge ACLK) begin
if (ARESET) begin
m_valid_i <= 0;
s_ready_i <= 0;
m_grant_hot_i <= 0;
m_grant_enc_i <= 0;
any_grant <= 1'b0;
last_rr_hot <= {1'b1, {C_NUM_S-1{1'b0}}};
grant_rnw <= 1'b0;
end else begin
s_ready_i <= 0;
if (m_valid_i) begin
// Stall 1 cycle after each master-side completion.
if (m_aready) begin // Master-side completion
m_valid_i <= 1'b0;
m_grant_hot_i <= 0;
any_grant <= 1'b0;
end
end else if (any_grant) begin
m_valid_i <= 1'b1;
s_ready_i <= m_grant_hot_i; // Assert S_AW/READY for 1 cycle to complete SI address transfer
end else begin
if (found_prio | found_rr) begin
m_grant_hot_i <= next_hot;
m_grant_enc_i <= next_enc;
any_grant <= 1'b1;
grant_rnw <= |(rnw & next_hot);
if (~found_prio) begin
last_rr_hot <= next_rr_hot;
end
end
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Fixed Priority arbiter
// Selects next request to grant from among inputs with PRIO > 0, if any.
/////////////////////////////////////////////////////////////////////////////
always @ * begin : ALG_PRIO
integer ip;
any_prio = 1'b0;
which_prio_hot = 0;
which_prio_enc = 0;
current_highest = 0;
for (ip=0; ip < C_NUM_S; ip=ip+1) begin
if (P_PRIO_MASK[ip] & ({1'b0, C_ARB_PRIORITY[ip*32+:4]} > current_highest)) begin
if (s_avalid[ip]) begin
current_highest[0+:4] = C_ARB_PRIORITY[ip*32+:4];
any_prio = 1'b1;
which_prio_hot = 1'b1 << ip;
which_prio_enc = ip;
end
end
end
found_prio = any_prio;
next_prio_hot = which_prio_hot;
next_prio_enc = which_prio_enc;
end
/////////////////////////////////////////////////////////////////////////////
// Round-robin arbiter
// Selects next request to grant from among inputs with PRIO = 0, if any.
/////////////////////////////////////////////////////////////////////////////
assign valid_rr = ~P_PRIO_MASK & s_avalid;
always @ * begin : ALG_RR
integer ir, jr, nr;
next_rr_hot = 0;
for (ir=0;ir<C_NUM_S;ir=ir+1) begin
nr = (ir>0) ? (ir-1) : (C_NUM_S-1);
carry_rr[ir*C_NUM_S] = last_rr_hot[nr];
mask_rr[ir*C_NUM_S] = ~valid_rr[nr];
for (jr=1;jr<C_NUM_S;jr=jr+1) begin
nr = (ir-jr > 0) ? (ir-jr-1) : (C_NUM_S+ir-jr-1);
carry_rr[ir*C_NUM_S+jr] = carry_rr[ir*C_NUM_S+jr-1] | (last_rr_hot[nr] & mask_rr[ir*C_NUM_S+jr-1]);
if (jr < C_NUM_S-1) begin
mask_rr[ir*C_NUM_S+jr] = mask_rr[ir*C_NUM_S+jr-1] & ~valid_rr[nr];
end
end
next_rr_hot[ir] = valid_rr[ir] & carry_rr[(ir+1)*C_NUM_S-1];
end
next_rr_enc = f_hot2enc(next_rr_hot);
found_rr = |(next_rr_hot);
end
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (C_NUM_S),
.C_SEL_WIDTH (C_NUM_S_LOG),
.C_DATA_WIDTH (C_AMESG_WIDTH)
) si_amesg_mux_inst
(
.S (next_enc),
.A (s_amesg),
.O (amesg_mux),
.OE (1'b1)
);
always @(posedge ACLK) begin
if (ARESET) begin
m_amesg_i <= 0;
end else if (~any_grant) begin
m_amesg_i <= amesg_mux;
end
end
end else begin : gen_no_arbiter
assign M_GRANT_ANY = m_grant_hot_i;
always @ (posedge ACLK) begin
if (ARESET) begin
m_valid_i <= 1'b0;
s_ready_i <= 1'b0;
m_grant_enc_i <= 0;
m_grant_hot_i <= 1'b0;
grant_rnw <= 1'b0;
end else begin
s_ready_i <= 1'b0;
if (m_valid_i) begin
if (m_aready) begin
m_valid_i <= 1'b0;
m_grant_hot_i <= 1'b0;
end
end else if (m_grant_hot_i) begin
m_valid_i <= 1'b1;
s_ready_i[0] <= 1'b1; // Assert S_AW/READY for 1 cycle to complete SI address transfer
end else if (s_avalid[0]) begin
m_grant_hot_i <= 1'b1;
grant_rnw <= rnw[0];
end
end
end
always @ (posedge ACLK) begin
if (ARESET) begin
m_amesg_i <= 0;
end else if (~m_grant_hot_i) begin
m_amesg_i <= s_amesg;
end
end
end // gen_arbiter
endgenerate
endmodule |
module processing_system7_bfm_v2_0_5_arb_wr(
rstn,
sw_clk,
qos1,
qos2,
prt_dv1,
prt_dv2,
prt_data1,
prt_data2,
prt_addr1,
prt_addr2,
prt_bytes1,
prt_bytes2,
prt_ack1,
prt_ack2,
prt_qos,
prt_req,
prt_data,
prt_addr,
prt_bytes,
prt_ack
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2;
input [max_burst_bits-1:0] prt_data1,prt_data2;
input [addr_width-1:0] prt_addr1,prt_addr2;
input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2;
input prt_dv1, prt_dv2, prt_ack;
output reg prt_ack1,prt_ack2,prt_req;
output reg [max_burst_bits-1:0] prt_data;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
output reg [axi_qos_width-1:0] prt_qos;
parameter wait_req = 2'b00, serv_req1 = 2'b01, serv_req2 = 2'b10,wait_ack_low = 2'b11;
reg [1:0] state,temp_state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_req = 1'b0;
if(prt_dv1 && !prt_dv2) begin
state = serv_req1;
prt_req = 1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
prt_qos = qos1;
end else if(!prt_dv1 && prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv1 && prt_dv2) begin
if(qos1 > qos2) begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else if(qos1 < qos2) begin
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req1:begin
state = serv_req1;
prt_ack2 = 1'b0;
if(prt_ack) begin
prt_ack1 = 1'b1;
prt_req = 0;
if(prt_dv2) begin
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
// state = wait_req;
state = wait_ack_low;
end
end
end
serv_req2:begin
state = serv_req2;
prt_ack1 = 1'b0;
if(prt_ack) begin
prt_ack2 = 1'b1;
prt_req = 0;
if(prt_dv1) begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else begin
state = wait_ack_low;
// state = wait_req;
end
end
end
wait_ack_low:begin
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
state = wait_ack_low;
if(!prt_ack)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule |
module processing_system7_bfm_v2_0_5_arb_wr(
rstn,
sw_clk,
qos1,
qos2,
prt_dv1,
prt_dv2,
prt_data1,
prt_data2,
prt_addr1,
prt_addr2,
prt_bytes1,
prt_bytes2,
prt_ack1,
prt_ack2,
prt_qos,
prt_req,
prt_data,
prt_addr,
prt_bytes,
prt_ack
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2;
input [max_burst_bits-1:0] prt_data1,prt_data2;
input [addr_width-1:0] prt_addr1,prt_addr2;
input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2;
input prt_dv1, prt_dv2, prt_ack;
output reg prt_ack1,prt_ack2,prt_req;
output reg [max_burst_bits-1:0] prt_data;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
output reg [axi_qos_width-1:0] prt_qos;
parameter wait_req = 2'b00, serv_req1 = 2'b01, serv_req2 = 2'b10,wait_ack_low = 2'b11;
reg [1:0] state,temp_state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_req = 1'b0;
if(prt_dv1 && !prt_dv2) begin
state = serv_req1;
prt_req = 1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
prt_qos = qos1;
end else if(!prt_dv1 && prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv1 && prt_dv2) begin
if(qos1 > qos2) begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else if(qos1 < qos2) begin
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req1:begin
state = serv_req1;
prt_ack2 = 1'b0;
if(prt_ack) begin
prt_ack1 = 1'b1;
prt_req = 0;
if(prt_dv2) begin
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
// state = wait_req;
state = wait_ack_low;
end
end
end
serv_req2:begin
state = serv_req2;
prt_ack1 = 1'b0;
if(prt_ack) begin
prt_ack2 = 1'b1;
prt_req = 0;
if(prt_dv1) begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else begin
state = wait_ack_low;
// state = wait_req;
end
end
end
wait_ack_low:begin
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
state = wait_ack_low;
if(!prt_ack)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule |
module processing_system7_bfm_v2_0_5_arb_wr(
rstn,
sw_clk,
qos1,
qos2,
prt_dv1,
prt_dv2,
prt_data1,
prt_data2,
prt_addr1,
prt_addr2,
prt_bytes1,
prt_bytes2,
prt_ack1,
prt_ack2,
prt_qos,
prt_req,
prt_data,
prt_addr,
prt_bytes,
prt_ack
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2;
input [max_burst_bits-1:0] prt_data1,prt_data2;
input [addr_width-1:0] prt_addr1,prt_addr2;
input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2;
input prt_dv1, prt_dv2, prt_ack;
output reg prt_ack1,prt_ack2,prt_req;
output reg [max_burst_bits-1:0] prt_data;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
output reg [axi_qos_width-1:0] prt_qos;
parameter wait_req = 2'b00, serv_req1 = 2'b01, serv_req2 = 2'b10,wait_ack_low = 2'b11;
reg [1:0] state,temp_state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_req = 1'b0;
if(prt_dv1 && !prt_dv2) begin
state = serv_req1;
prt_req = 1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
prt_qos = qos1;
end else if(!prt_dv1 && prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv1 && prt_dv2) begin
if(qos1 > qos2) begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else if(qos1 < qos2) begin
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req1:begin
state = serv_req1;
prt_ack2 = 1'b0;
if(prt_ack) begin
prt_ack1 = 1'b1;
prt_req = 0;
if(prt_dv2) begin
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
// state = wait_req;
state = wait_ack_low;
end
end
end
serv_req2:begin
state = serv_req2;
prt_ack1 = 1'b0;
if(prt_ack) begin
prt_ack2 = 1'b1;
prt_req = 0;
if(prt_dv1) begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else begin
state = wait_ack_low;
// state = wait_req;
end
end
end
wait_ack_low:begin
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
state = wait_ack_low;
if(!prt_ack)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule |
module */
/* Internal counters that are used as Read/Write pointers to the fifo's that store all the transaction info on all channles.
This parameter is used to define the width of these pointers --> depending on Maximum outstanding transactions supported.
1-bit extra width than the no.of.bits needed to represent the outstanding transactions
Extra bit helps in generating the empty and full flags
*/
parameter int_cntr_width = clogb2(max_outstanding_transactions)+1;
/* RESP data */
parameter rsp_fifo_bits = axi_rsp_width+id_bus_width;
parameter rsp_lsb = 0;
parameter rsp_msb = axi_rsp_width-1;
parameter rsp_id_lsb = rsp_msb + 1;
parameter rsp_id_msb = rsp_id_lsb + id_bus_width-1;
input S_RESETN;
output S_ARREADY;
output S_AWREADY;
output S_BVALID;
output S_RLAST;
output S_RVALID;
output S_WREADY;
output [axi_rsp_width-1:0] S_BRESP;
output [axi_rsp_width-1:0] S_RRESP;
output [data_bus_width-1:0] S_RDATA;
output [id_bus_width-1:0] S_BID;
output [id_bus_width-1:0] S_RID;
input S_ACLK;
input S_ARVALID;
input S_AWVALID;
input S_BREADY;
input S_RREADY;
input S_WLAST;
input S_WVALID;
input [axi_brst_type_width-1:0] S_ARBURST;
input [axi_lock_width-1:0] S_ARLOCK;
input [axi_size_width-1:0] S_ARSIZE;
input [axi_brst_type_width-1:0] S_AWBURST;
input [axi_lock_width-1:0] S_AWLOCK;
input [axi_size_width-1:0] S_AWSIZE;
input [axi_prot_width-1:0] S_ARPROT;
input [axi_prot_width-1:0] S_AWPROT;
input [address_bus_width-1:0] S_ARADDR;
input [address_bus_width-1:0] S_AWADDR;
input [data_bus_width-1:0] S_WDATA;
input [axi_cache_width-1:0] S_ARCACHE;
input [axi_cache_width-1:0] S_ARLEN;
input [axi_qos_width-1:0] S_ARQOS;
input [axi_cache_width-1:0] S_AWCACHE;
input [axi_len_width-1:0] S_AWLEN;
input [axi_qos_width-1:0] S_AWQOS;
input [(data_bus_width/8)-1:0] S_WSTRB;
input [id_bus_width-1:0] S_ARID;
input [id_bus_width-1:0] S_AWID;
input [id_bus_width-1:0] S_WID;
input SW_CLK;
input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM;
output WR_DATA_VALID_DDR, WR_DATA_VALID_OCM;
output [max_burst_bits-1:0] WR_DATA;
output [addr_width-1:0] WR_ADDR;
output [max_transfer_bytes_width:0] WR_BYTES;
output reg RD_REQ_OCM, RD_REQ_DDR;
output reg [addr_width-1:0] RD_ADDR;
input [max_burst_bits-1:0] RD_DATA_DDR,RD_DATA_OCM;
output reg[max_transfer_bytes_width:0] RD_BYTES;
input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR;
output [axi_qos_width-1:0] WR_QOS;
output reg [axi_qos_width-1:0] RD_QOS;
input S_RDISSUECAP1_EN;
input S_WRISSUECAP1_EN;
output [7:0] S_RCOUNT;
output [7:0] S_WCOUNT;
output [2:0] S_RACOUNT;
output [5:0] S_WACOUNT;
wire net_ARVALID;
wire net_AWVALID;
wire net_WVALID;
real s_aclk_period;
cdn_axi3_slave_bfm #(slave_name,
data_bus_width,
address_bus_width,
id_bus_width,
slave_base_address,
(slave_high_address- slave_base_address),
max_outstanding_transactions,
0, ///MEMORY_MODEL_MODE,
exclusive_access_supported)
slave (.ACLK (S_ACLK),
.ARESETn (S_RESETN), /// confirm this
// Write Address Channel
.AWID (S_AWID),
.AWADDR (S_AWADDR),
.AWLEN (S_AWLEN),
.AWSIZE (S_AWSIZE),
.AWBURST (S_AWBURST),
.AWLOCK (S_AWLOCK),
.AWCACHE (S_AWCACHE),
.AWPROT (S_AWPROT),
.AWVALID (net_AWVALID),
.AWREADY (S_AWREADY),
// Write Data Channel Signals.
.WID (S_WID),
.WDATA (S_WDATA),
.WSTRB (S_WSTRB),
.WLAST (S_WLAST),
.WVALID (net_WVALID),
.WREADY (S_WREADY),
// Write Response Channel Signals.
.BID (S_BID),
.BRESP (S_BRESP),
.BVALID (S_BVALID),
.BREADY (S_BREADY),
// Read Address Channel Signals.
.ARID (S_ARID),
.ARADDR (S_ARADDR),
.ARLEN (S_ARLEN),
.ARSIZE (S_ARSIZE),
.ARBURST (S_ARBURST),
.ARLOCK (S_ARLOCK),
.ARCACHE (S_ARCACHE),
.ARPROT (S_ARPROT),
.ARVALID (net_ARVALID),
.ARREADY (S_ARREADY),
// Read Data Channel Signals.
.RID (S_RID),
.RDATA (S_RDATA),
.RRESP (S_RRESP),
.RLAST (S_RLAST),
.RVALID (S_RVALID),
.RREADY (S_RREADY));
wire wr_intr_fifo_full;
reg temp_wr_intr_fifo_full;
/* Interconnect WR_FIFO model instance */
processing_system7_bfm_v2_0_5_intr_wr_mem wr_intr_fifo(SW_CLK, S_RESETN, wr_intr_fifo_full, WR_DATA_ACK_OCM, WR_DATA_ACK_DDR, WR_ADDR, WR_DATA, WR_BYTES, WR_QOS, WR_DATA_VALID_OCM, WR_DATA_VALID_DDR);
/* Register the async 'full' signal to S_ACLK clock */
always@(posedge S_ACLK) temp_wr_intr_fifo_full = wr_intr_fifo_full;
/* Latency type and Debug/Error Control */
reg[1:0] latency_type = RANDOM_CASE;
reg DEBUG_INFO = 1;
reg STOP_ON_ERROR = 1'b1;
/* Internal nets/regs for calling slave BFM API's*/
reg [wr_afi_fifo_data_bits-1:0] wr_fifo [0:max_outstanding_transactions-1];
reg [int_cntr_width-1:0] wr_fifo_wr_ptr = 0, wr_fifo_rd_ptr = 0;
wire wr_fifo_empty;
/* Store the awvalid receive time --- necessary for calculating the bresp latency */
reg [7:0] aw_time_cnt = 0,bresp_time_cnt = 0;
real awvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new awvalid is received
reg awvalid_flag[0:max_outstanding_transactions]; // store the time when a new awvalid is received
/* Address Write Channel handshake*/
reg[int_cntr_width-1:0] aw_cnt = 0;//
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] awsize [0:max_outstanding_transactions-1];
reg [axi_prot_width-1:0] awprot [0:max_outstanding_transactions-1];
reg [axi_lock_width-1:0] awlock [0:max_outstanding_transactions-1];
reg [axi_cache_width-1:0] awcache [0:max_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] awbrst [0:max_outstanding_transactions-1];
reg [axi_len_width-1:0] awlen [0:max_outstanding_transactions-1];
reg aw_flag [0:max_outstanding_transactions-1];
reg [addr_width-1:0] awaddr [0:max_outstanding_transactions-1];
reg [id_bus_width-1:0] awid [0:max_outstanding_transactions-1];
reg [axi_qos_width-1:0] awqos [0:max_outstanding_transactions-1];
wire aw_fifo_full; // indicates awvalid_fifo is full (max outstanding transactions reached)
/* internal fifos to store burst write data, ID & strobes*/
reg [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_outstanding_transactions-1];
reg [max_burst_bytes_width:0] burst_valid_bytes [0:max_outstanding_transactions-1]; /// total valid bytes received in a complete burst transfer
reg wlast_flag [0:max_outstanding_transactions-1]; // flag to indicate WLAST received
wire wd_fifo_full;
/* Write Data Channel and Write Response handshake signals*/
reg [int_cntr_width-1:0] wd_cnt = 0;
reg [(data_bus_width*axi_burst_len)-1:0] aligned_wr_data;
reg [addr_width-1:0] aligned_wr_addr;
reg [max_burst_bytes_width:0] valid_data_bytes;
reg [int_cntr_width-1:0] wr_bresp_cnt = 0;
reg [axi_rsp_width-1:0] bresp;
reg [rsp_fifo_bits-1:0] fifo_bresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response
reg enable_write_bresp;
reg [int_cntr_width-1:0] rd_bresp_cnt = 0;
integer wr_latency_count;
reg wr_delayed;
wire bresp_fifo_empty;
/* keep track of count values */
reg[7:0] wcount;
reg[5:0] wacount;
/* Qos*/
reg [axi_qos_width-1:0] ar_qos, aw_qos;
initial begin
if(DEBUG_INFO) begin
if(enable_this_port)
$display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, slave_name);
else
$display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, slave_name);
end
end
/*--------------------------------------------------------------------------------*/
/* Store the Clock cycle time period */
always@(S_RESETN)
begin
if(S_RESETN) begin
@(posedge S_ACLK);
s_aclk_period = $time;
@(posedge S_ACLK);
s_aclk_period = $time - s_aclk_period;
end
end
/*--------------------------------------------------------------------------------*/
initial slave.set_disable_reset_value_checks(1);
initial begin
repeat(2) @(posedge S_ACLK);
if(!enable_this_port) begin
slave.set_channel_level_info(0);
slave.set_function_level_info(0);
end
slave.RESPONSE_TIMEOUT = 0;
end
/*--------------------------------------------------------------------------------*/
/* Set Latency type to be used */
task set_latency_type;
input[1:0] lat;
begin
if(enable_this_port)
latency_type = lat;
else begin
//if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'Latency Profile' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set ARQoS to be used */
task set_arqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
ar_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'ARQOS' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set AWQoS to be used */
task set_awqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
aw_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'AWQOS' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* get the wr latency number */
function [31:0] get_wr_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : get_wr_lat_number = afi_wr_min;
AVG_CASE : get_wr_lat_number = afi_wr_avg;
WORST_CASE : get_wr_lat_number = afi_wr_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2'b00 : get_wr_lat_number = ($random()%10+ afi_wr_min);
2'b01 : get_wr_lat_number = ($random()%40+ afi_wr_avg);
default : get_wr_lat_number = ($random()%60+ afi_wr_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* get the rd latency number */
function [31:0] get_rd_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : get_rd_lat_number = afi_rd_min;
AVG_CASE : get_rd_lat_number = afi_rd_avg;
WORST_CASE : get_rd_lat_number = afi_rd_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2'b00 : get_rd_lat_number = ($random()%10+ afi_rd_min);
2'b01 : get_rd_lat_number = ($random()%40+ afi_rd_avg);
default : get_rd_lat_number = ($random()%60+ afi_rd_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Check for any WRITE/READs when this port is disabled */
always@(S_AWVALID or S_WVALID or S_ARVALID)
begin
if((S_AWVALID | S_WVALID | S_ARVALID) && !enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. AXI transaction is initiated on this port ...\nSimulation will halt ..",$time, DISP_ERR, slave_name);
$stop;
end
end
/*--------------------------------------------------------------------------------*/
assign net_ARVALID = enable_this_port ? S_ARVALID : 1'b0;
assign net_AWVALID = enable_this_port ? S_AWVALID : 1'b0;
assign net_WVALID = enable_this_port ? S_WVALID : 1'b0;
assign wr_fifo_empty = (wr_fifo_wr_ptr === wr_fifo_rd_ptr)?1'b1: 1'b0;
assign bresp_fifo_empty = (wr_bresp_cnt === rd_bresp_cnt)?1'b1:1'b0;
assign bresp_fifo_full = ((wr_bresp_cnt[int_cntr_width-1] !== rd_bresp_cnt[int_cntr_width-1]) && (wr_bresp_cnt[int_cntr_width-2:0] === rd_bresp_cnt[int_cntr_width-2:0]))?1'b1:1'b0;
assign S_WCOUNT = wcount;
assign S_WACOUNT = wacount;
// FIFO_STATUS (only if AFI port) 1- full
function automatic wrfifo_full ;
input [axi_len_width:0] fifo_space_exp;
integer fifo_space_left;
begin
fifo_space_left = afi_fifo_locations - wcount;
if(fifo_space_left < fifo_space_exp)
wrfifo_full = 1;
else
wrfifo_full = 0;
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Store the awvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or S_AWID or S_AWADDR or S_AWVALID )
begin
if(!S_RESETN)
aw_time_cnt = 0;
else begin
if(S_AWVALID) begin
awvalid_receive_time[aw_time_cnt] = $time;
awvalid_flag[aw_time_cnt] = 1'b1;
aw_time_cnt = aw_time_cnt + 1;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_AWVALID && S_AWREADY) begin
if(S_AWQOS === 0) awqos[aw_cnt[int_cntr_width-2:0]] = aw_qos;
else awqos[aw_cnt[int_cntr_width-2:0]] = S_AWQOS;
end
end
/* Address Write Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
aw_cnt = 0;
wacount = 0;
end else begin
if(S_AWVALID && !wrfifo_full(S_AWLEN+1)) begin
slave.RECEIVE_WRITE_ADDRESS(0,
id_invalid,
awaddr[aw_cnt[int_cntr_width-2:0]],
awlen[aw_cnt[int_cntr_width-2:0]],
awsize[aw_cnt[int_cntr_width-2:0]],
awbrst[aw_cnt[int_cntr_width-2:0]],
awlock[aw_cnt[int_cntr_width-2:0]],
awcache[aw_cnt[int_cntr_width-2:0]],
awprot[aw_cnt[int_cntr_width-2:0]],
awid[aw_cnt[int_cntr_width-2:0]]); /// sampled valid ID.
aw_flag[aw_cnt[int_cntr_width-2:0]] = 1'b1;
aw_cnt = aw_cnt + 1;
wacount = wacount + 1;
end // if (!aw_fifo_full)
end /// if else
end /// always
/*--------------------------------------------------------------------------------*/
/* Write Data Channel Handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wd_cnt = 0;
end else begin
if(aw_flag[wd_cnt[int_cntr_width-2:0]]) begin
if(S_WVALID && !wrfifo_full(awlen[wd_cnt[int_cntr_width-2:0]] + 1)) begin
slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]);
wlast_flag[wd_cnt[int_cntr_width-2:0]] = 1'b1;
wd_cnt = wd_cnt + 1;
end
end else begin
if(!wrfifo_full(axi_burst_len+1) && S_WVALID) begin
slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]);
wlast_flag[wd_cnt[int_cntr_width-2:0]] = 1'b1;
wd_cnt = wd_cnt + 1;
end
end /// if
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
/* Align the wrap data for write transaction */
task automatic get_wrap_aligned_wr_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
output [addr_width-1:0] start_addr; /// aligned start address
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
wrp_data = wrp_data << ((data_bus_width*axi_burst_len) - (v_bytes*8));
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data << 8;
temp_data[7:0] = wrp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8];
wrp_data = wrp_data << 8;
wrp_bytes = wrp_bytes - 1;
end
wrp_bytes = addr - start_addr;
wrp_data = b_data << (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
/* Calculate the Response for each read/write transaction */
function [axi_rsp_width-1:0] calculate_resp;
input [addr_width-1:0] awaddr;
input [axi_prot_width-1:0] awprot;
reg [axi_rsp_width-1:0] rsp;
begin
rsp = AXI_OK;
/* Address Decode */
if(decode_address(awaddr) === INVALID_MEM_TYPE) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) ",$time, DISP_ERR, slave_name, awaddr);
end
else if(decode_address(awaddr) === REG_MEM) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Access to Register Map(0x%0h) is not allowed through this port.",$time, DISP_ERR, slave_name, awaddr);
end
if(secure_access_enabled && awprot[1])
rsp = AXI_DEC_ERR; // decode error
calculate_resp = rsp;
end
endfunction
/*--------------------------------------------------------------------------------*/
reg[max_burst_bits-1:0] temp_wr_data;
/* Store the Write response for each write transaction */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wr_fifo_wr_ptr = 0;
wcount = 0;
end else begin
enable_write_bresp = aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] && wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]];
/* calculate bresp only when AWVALID && WLAST is received */
if(enable_write_bresp) begin
aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] = 0;
wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] = 0;
bresp = calculate_resp(awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], awprot[wr_fifo_wr_ptr[int_cntr_width-2:0]]);
/* Fill AFI_WR_data FIFO */
if(bresp === AXI_OK ) begin
if(awbrst[wr_fifo_wr_ptr[int_cntr_width-2:0]]=== AXI_WRAP) begin /// wrap type? then align the data
get_wrap_aligned_wr_data(aligned_wr_data, aligned_wr_addr, awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]],burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]]); /// gives wrapped start address
end else begin
aligned_wr_data = burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]];
aligned_wr_addr = awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]] ;
end
valid_data_bytes = burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]];
end else
valid_data_bytes = 0;
temp_wr_data = aligned_wr_data;
wr_fifo[wr_fifo_wr_ptr[int_cntr_width-2:0]] = {awqos[wr_fifo_wr_ptr[int_cntr_width-2:0]], awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]], awid[wr_fifo_wr_ptr[int_cntr_width-2:0]], bresp, temp_wr_data, aligned_wr_addr, valid_data_bytes};
wcount = wcount + awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]]+1;
wr_fifo_wr_ptr = wr_fifo_wr_ptr + 1;
end
end // else
end // always
/*--------------------------------------------------------------------------------*/
/* Send Write Response Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
rd_bresp_cnt = 0;
wr_latency_count = get_wr_lat_number(1);
wr_delayed = 0;
bresp_time_cnt = 0;
end else begin
wr_delayed = 1'b0;
if(awvalid_flag[bresp_time_cnt] && (($time - awvalid_receive_time[bresp_time_cnt])/s_aclk_period >= wr_latency_count))
wr_delayed = 1;
if(!bresp_fifo_empty && wr_delayed) begin
slave.SEND_WRITE_RESPONSE(fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb], // ID
fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_msb : rsp_lsb] // Response
);
wr_delayed = 0;
awvalid_flag[bresp_time_cnt] = 1'b0;
bresp_time_cnt = bresp_time_cnt+1;
rd_bresp_cnt = rd_bresp_cnt + 1;
wr_latency_count = get_wr_lat_number(1);
end
end // else
end//always
/*--------------------------------------------------------------------------------*/
/* Write Response Channel handshake */
reg wr_int_state;
/* Reading from the wr_fifo and sending to Interconnect fifo*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wr_int_state = 1'b0;
wr_bresp_cnt = 0;
wr_fifo_rd_ptr = 0;
end else begin
case(wr_int_state)
1'b0 : begin
wr_int_state = 1'b0;
if(!temp_wr_intr_fifo_full && !bresp_fifo_full && !wr_fifo_empty) begin
wr_intr_fifo.write_mem({wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_qos_msb:wr_afi_qos_lsb], wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_data_msb:wr_afi_bytes_lsb]}); /// qos, data, address and valid_bytes
wr_int_state = 1'b1;
/* start filling the write response fifo at the same time */
fifo_bresp[wr_bresp_cnt[int_cntr_width-2:0]] = wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_id_msb:wr_afi_rsp_lsb]; // ID and Resp
wcount = wcount - (wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_ln_msb:wr_afi_ln_lsb] + 1); /// burst length
wacount = wacount - 1;
wr_fifo_rd_ptr = wr_fifo_rd_ptr + 1;
wr_bresp_cnt = wr_bresp_cnt+1;
end
end
1'b1 : begin
wr_int_state = 0;
end
endcase
end
end
/*--------------------------------------------------------------------------------*/
/*-------------------------------- WRITE HANDSHAKE END ----------------------------------------*/
/*-------------------------------- READ HANDSHAKE ---------------------------------------------*/
/* READ CHANNELS */
/* Store the arvalid receive time --- necessary for calculating latency in sending the rresp latency */
reg [7:0] ar_time_cnt = 0,rresp_time_cnt = 0;
real arvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new arvalid is received
reg arvalid_flag[0:max_outstanding_transactions]; // store the time when a new arvalid is received
reg [int_cntr_width-1:0] ar_cnt = 0;// counter for arvalid info
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] arsize [0:max_outstanding_transactions-1];
reg [axi_prot_width-1:0] arprot [0:max_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] arbrst [0:max_outstanding_transactions-1];
reg [axi_len_width-1:0] arlen [0:max_outstanding_transactions-1];
reg [axi_cache_width-1:0] arcache [0:max_outstanding_transactions-1];
reg [axi_lock_width-1:0] arlock [0:max_outstanding_transactions-1];
reg ar_flag [0:max_outstanding_transactions-1];
reg [addr_width-1:0] araddr [0:max_outstanding_transactions-1];
reg [id_bus_width-1:0] arid [0:max_outstanding_transactions-1];
reg [axi_qos_width-1:0] arqos [0:max_outstanding_transactions-1];
wire ar_fifo_full; // indicates arvalid_fifo is full (max outstanding transactions reached)
reg [int_cntr_width-1:0] wr_rresp_cnt = 0;
reg [axi_rsp_width-1:0] rresp;
reg [rsp_fifo_bits-1:0] fifo_rresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response
reg enable_write_rresp;
/* Send Read Response & Data Channel handshake */
integer rd_latency_count;
reg rd_delayed;
reg [rd_afi_fifo_bits-1:0] read_fifo[0:max_outstanding_transactions-1]; /// Read Burst Data, addr, size, burst, len, RID, RRESP, valid_bytes
reg [int_cntr_width-1:0] rd_fifo_wr_ptr = 0, rd_fifo_rd_ptr = 0;
wire read_fifo_full;
reg [7:0] rcount;
reg [2:0] racount;
wire rd_intr_fifo_full, rd_intr_fifo_empty;
wire read_fifo_empty;
/* signals to communicate with interconnect RD_FIFO model */
reg rd_req, invalid_rd_req;
/* REad control Info
56:25 : Address (32)
24:22 : Size (3)
21:20 : BRST (2)
19:16 : LEN (4)
15:10 : RID (6)
9:8 : RRSP (2)
7:0 : byte cnt (8)
*/
reg [rd_info_bits-1:0] read_control_info;
reg [(data_bus_width*axi_burst_len)-1:0] aligned_rd_data;
reg temp_rd_intr_fifo_empty;
processing_system7_bfm_v2_0_5_intr_rd_mem rd_intr_fifo(SW_CLK, S_RESETN, rd_intr_fifo_full, rd_intr_fifo_empty, rd_req, invalid_rd_req, read_control_info , RD_DATA_OCM, RD_DATA_DDR, RD_DATA_VALID_OCM, RD_DATA_VALID_DDR);
assign read_fifo_empty = (rd_fifo_wr_ptr === rd_fifo_rd_ptr)?1'b1: 1'b0;
assign S_RCOUNT = rcount;
assign S_RACOUNT = racount;
/* Register the asynch signal empty coming from Interconnect READ FIFO */
always@(posedge S_ACLK) temp_rd_intr_fifo_empty = rd_intr_fifo_empty;
// FIFO_STATUS (only if AFI port) 1- full
function automatic rdfifo_full ;
input [axi_len_width:0] fifo_space_exp;
integer fifo_space_left;
begin
fifo_space_left = afi_fifo_locations - rcount;
if(fifo_space_left < fifo_space_exp)
rdfifo_full = 1;
else
rdfifo_full = 0;
end
endfunction
/* Store the arvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or S_ARID or S_ARADDR or S_ARVALID )
begin
if(!S_RESETN)
ar_time_cnt = 0;
else begin
if(S_ARVALID) begin
arvalid_receive_time[ar_time_cnt] = $time;
arvalid_flag[ar_time_cnt] = 1'b1;
ar_time_cnt = ar_time_cnt + 1;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_ARVALID && S_ARREADY) begin
if(S_ARQOS === 0) arqos[aw_cnt[int_cntr_width-2:0]] = ar_qos;
else arqos[aw_cnt[int_cntr_width-2:0]] = S_ARQOS;
end
end
/* Address Read Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
ar_cnt = 0;
racount = 0;
end else begin
if(S_ARVALID && !rdfifo_full(S_ARLEN+1)) begin /// if AFI read fifo is not full
slave.RECEIVE_READ_ADDRESS(0,
id_invalid,
araddr[ar_cnt[int_cntr_width-2:0]],
arlen[ar_cnt[int_cntr_width-2:0]],
arsize[ar_cnt[int_cntr_width-2:0]],
arbrst[ar_cnt[int_cntr_width-2:0]],
arlock[ar_cnt[int_cntr_width-2:0]],
arcache[ar_cnt[int_cntr_width-2:0]],
arprot[ar_cnt[int_cntr_width-2:0]],
arid[ar_cnt[int_cntr_width-2:0]]); /// sampled valid ID.
ar_flag[ar_cnt[int_cntr_width-2:0]] = 1'b1;
ar_cnt = ar_cnt+1;
racount = racount + 1;
end /// if(!ar_fifo_full)
end /// if else
end /// always*/
/*--------------------------------------------------------------------------------*/
/* Align Wrap data for read transaction*/
task automatic get_wrap_aligned_rd_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [addr_width-1:0] start_addr;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data >> 8;
temp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8] = wrp_data[7:0];
wrp_data = wrp_data >> 8;
wrp_bytes = wrp_bytes - 1;
end
temp_data = temp_data >> ((data_bus_width*axi_burst_len) - (v_bytes*8));
wrp_bytes = addr - start_addr;
wrp_data = b_data >> (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
parameter RD_DATA_REQ = 1'b0, WAIT_RD_VALID = 1'b1;
reg rd_fifo_state;
reg [addr_width-1:0] temp_read_address;
reg [max_burst_bytes_width:0] temp_rd_valid_bytes;
/* get the data from memory && also calculate the rresp*/
always@(negedge S_RESETN or posedge SW_CLK)
begin
if(!S_RESETN)begin
wr_rresp_cnt =0;
rd_fifo_state = RD_DATA_REQ;
temp_rd_valid_bytes = 0;
temp_read_address = 0;
RD_REQ_DDR = 1'b0;
RD_REQ_OCM = 1'b0;
rd_req = 0;
invalid_rd_req= 0;
RD_QOS = 0;
end else begin
case(rd_fifo_state)
RD_DATA_REQ : begin
rd_fifo_state = RD_DATA_REQ;
RD_REQ_DDR = 1'b0;
RD_REQ_OCM = 1'b0;
invalid_rd_req = 0;
if(ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] && !rd_intr_fifo_full) begin /// check the rd_fifo_bytes, interconnect fifo full condition
ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] = 0;
rresp = calculate_resp(araddr[wr_rresp_cnt[int_cntr_width-2:0]],arprot[wr_rresp_cnt[int_cntr_width-2:0]]);
temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_cntr_width-2:0]]+1)*(2**arsize[wr_rresp_cnt[int_cntr_width-2:0]]);//data_bus_width/8;
if(arbrst[wr_rresp_cnt[int_cntr_width-2:0]] === AXI_WRAP) /// wrap begin
temp_read_address = (araddr[wr_rresp_cnt[int_cntr_width-2:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes;
else
temp_read_address = araddr[wr_rresp_cnt[int_cntr_width-2:0]];
if(rresp === AXI_OK) begin
case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_cntr_width-2:0]]);
OCM_MEM : RD_REQ_OCM = 1;
DDR_MEM : RD_REQ_DDR = 1;
default : invalid_rd_req = 1;
endcase
end else
invalid_rd_req = 1;
RD_ADDR = temp_read_address; ///araddr[wr_rresp_cnt[int_cntr_width-2:0]];
RD_BYTES = temp_rd_valid_bytes;
RD_QOS = arqos[wr_rresp_cnt[int_cntr_width-2:0]];
rd_fifo_state = WAIT_RD_VALID;
rd_req = 1;
racount = racount - 1;
read_control_info = {araddr[wr_rresp_cnt[int_cntr_width-2:0]], arsize[wr_rresp_cnt[int_cntr_width-2:0]], arbrst[wr_rresp_cnt[int_cntr_width-2:0]], arlen[wr_rresp_cnt[int_cntr_width-2:0]], arid[wr_rresp_cnt[int_cntr_width-2:0]], rresp, temp_rd_valid_bytes };
wr_rresp_cnt = wr_rresp_cnt + 1;
end
end
WAIT_RD_VALID : begin
rd_fifo_state = WAIT_RD_VALID;
rd_req = 0;
if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd_req) begin ///temp_dec == 2'b11) begin
RD_REQ_DDR = 1'b0;
RD_REQ_OCM = 1'b0;
invalid_rd_req = 0;
rd_fifo_state = RD_DATA_REQ;
end
end
endcase
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
/* thread to fill in the AFI RD_FIFO */
reg[rd_afi_fifo_bits-1:0] temp_rd_data;//Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes
reg tmp_state;
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN)begin
rd_fifo_wr_ptr = 0;
rcount = 0;
tmp_state = 0;
end else begin
case(tmp_state)
0 : begin
tmp_state = 0;
if(!temp_rd_intr_fifo_empty) begin
rd_intr_fifo.read_mem(temp_rd_data);
tmp_state = 1;
end
end
1 : begin
tmp_state = 1;
if(!rdfifo_full(temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1)) begin
read_fifo[rd_fifo_wr_ptr[int_cntr_width-2:0]] = temp_rd_data;
rd_fifo_wr_ptr = rd_fifo_wr_ptr + 1;
rcount = rcount + temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1; /// Burst length
tmp_state = 0;
end
end
endcase
end
end
/*--------------------------------------------------------------------------------*/
reg[max_burst_bytes_width:0] rd_v_b;
reg[rd_afi_fifo_bits-1:0] tmp_fifo_rd; /// Data, addr, size, burst, len, RID, RRESP,valid_bytes
reg[(data_bus_width*axi_burst_len)-1:0] temp_read_data;
reg[(axi_rsp_width*axi_burst_len)-1:0] temp_read_rsp;
/* Read Data Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN)begin
rd_fifo_rd_ptr = 0;
rd_latency_count = get_rd_lat_number(1);
rd_delayed = 0;
rresp_time_cnt = 0;
rd_v_b = 0;
end else begin
if(arvalid_flag[rresp_time_cnt] && ((($time - arvalid_receive_time[rresp_time_cnt])/s_aclk_period) >= rd_latency_count)) begin
rd_delayed = 1;
end
if(!read_fifo_empty && rd_delayed)begin
rd_delayed = 0;
arvalid_flag[rresp_time_cnt] = 1'b0;
tmp_fifo_rd = read_fifo[rd_fifo_rd_ptr[int_cntr_width-2:0]];
rd_v_b = (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+1)*(2**tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb]);
temp_read_data = tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb];
if(tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb] === AXI_WRAP) begin
get_wrap_aligned_rd_data(aligned_rd_data, tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb], tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb], rd_v_b);
temp_read_data = aligned_rd_data;
end
temp_read_rsp = 0;
repeat(axi_burst_len) begin
temp_read_rsp = temp_read_rsp >> axi_rsp_width;
temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = tmp_fifo_rd[rd_afi_rsp_msb : rd_afi_rsp_lsb];
end
slave.SEND_READ_BURST_RESP_CTRL(tmp_fifo_rd[rd_afi_id_msb : rd_afi_id_lsb],
tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb],
tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb],
tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb],
tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb],
temp_read_data,
temp_read_rsp);
rcount = rcount - (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+ 1) ;
rresp_time_cnt = rresp_time_cnt+1;
rd_latency_count = get_rd_lat_number(1);
rd_fifo_rd_ptr = rd_fifo_rd_ptr+1;
end
end /// else
end /// always
endmodule |
module */
/* Internal counters that are used as Read/Write pointers to the fifo's that store all the transaction info on all channles.
This parameter is used to define the width of these pointers --> depending on Maximum outstanding transactions supported.
1-bit extra width than the no.of.bits needed to represent the outstanding transactions
Extra bit helps in generating the empty and full flags
*/
parameter int_cntr_width = clogb2(max_outstanding_transactions)+1;
/* RESP data */
parameter rsp_fifo_bits = axi_rsp_width+id_bus_width;
parameter rsp_lsb = 0;
parameter rsp_msb = axi_rsp_width-1;
parameter rsp_id_lsb = rsp_msb + 1;
parameter rsp_id_msb = rsp_id_lsb + id_bus_width-1;
input S_RESETN;
output S_ARREADY;
output S_AWREADY;
output S_BVALID;
output S_RLAST;
output S_RVALID;
output S_WREADY;
output [axi_rsp_width-1:0] S_BRESP;
output [axi_rsp_width-1:0] S_RRESP;
output [data_bus_width-1:0] S_RDATA;
output [id_bus_width-1:0] S_BID;
output [id_bus_width-1:0] S_RID;
input S_ACLK;
input S_ARVALID;
input S_AWVALID;
input S_BREADY;
input S_RREADY;
input S_WLAST;
input S_WVALID;
input [axi_brst_type_width-1:0] S_ARBURST;
input [axi_lock_width-1:0] S_ARLOCK;
input [axi_size_width-1:0] S_ARSIZE;
input [axi_brst_type_width-1:0] S_AWBURST;
input [axi_lock_width-1:0] S_AWLOCK;
input [axi_size_width-1:0] S_AWSIZE;
input [axi_prot_width-1:0] S_ARPROT;
input [axi_prot_width-1:0] S_AWPROT;
input [address_bus_width-1:0] S_ARADDR;
input [address_bus_width-1:0] S_AWADDR;
input [data_bus_width-1:0] S_WDATA;
input [axi_cache_width-1:0] S_ARCACHE;
input [axi_cache_width-1:0] S_ARLEN;
input [axi_qos_width-1:0] S_ARQOS;
input [axi_cache_width-1:0] S_AWCACHE;
input [axi_len_width-1:0] S_AWLEN;
input [axi_qos_width-1:0] S_AWQOS;
input [(data_bus_width/8)-1:0] S_WSTRB;
input [id_bus_width-1:0] S_ARID;
input [id_bus_width-1:0] S_AWID;
input [id_bus_width-1:0] S_WID;
input SW_CLK;
input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM;
output WR_DATA_VALID_DDR, WR_DATA_VALID_OCM;
output [max_burst_bits-1:0] WR_DATA;
output [addr_width-1:0] WR_ADDR;
output [max_transfer_bytes_width:0] WR_BYTES;
output reg RD_REQ_OCM, RD_REQ_DDR;
output reg [addr_width-1:0] RD_ADDR;
input [max_burst_bits-1:0] RD_DATA_DDR,RD_DATA_OCM;
output reg[max_transfer_bytes_width:0] RD_BYTES;
input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR;
output [axi_qos_width-1:0] WR_QOS;
output reg [axi_qos_width-1:0] RD_QOS;
input S_RDISSUECAP1_EN;
input S_WRISSUECAP1_EN;
output [7:0] S_RCOUNT;
output [7:0] S_WCOUNT;
output [2:0] S_RACOUNT;
output [5:0] S_WACOUNT;
wire net_ARVALID;
wire net_AWVALID;
wire net_WVALID;
real s_aclk_period;
cdn_axi3_slave_bfm #(slave_name,
data_bus_width,
address_bus_width,
id_bus_width,
slave_base_address,
(slave_high_address- slave_base_address),
max_outstanding_transactions,
0, ///MEMORY_MODEL_MODE,
exclusive_access_supported)
slave (.ACLK (S_ACLK),
.ARESETn (S_RESETN), /// confirm this
// Write Address Channel
.AWID (S_AWID),
.AWADDR (S_AWADDR),
.AWLEN (S_AWLEN),
.AWSIZE (S_AWSIZE),
.AWBURST (S_AWBURST),
.AWLOCK (S_AWLOCK),
.AWCACHE (S_AWCACHE),
.AWPROT (S_AWPROT),
.AWVALID (net_AWVALID),
.AWREADY (S_AWREADY),
// Write Data Channel Signals.
.WID (S_WID),
.WDATA (S_WDATA),
.WSTRB (S_WSTRB),
.WLAST (S_WLAST),
.WVALID (net_WVALID),
.WREADY (S_WREADY),
// Write Response Channel Signals.
.BID (S_BID),
.BRESP (S_BRESP),
.BVALID (S_BVALID),
.BREADY (S_BREADY),
// Read Address Channel Signals.
.ARID (S_ARID),
.ARADDR (S_ARADDR),
.ARLEN (S_ARLEN),
.ARSIZE (S_ARSIZE),
.ARBURST (S_ARBURST),
.ARLOCK (S_ARLOCK),
.ARCACHE (S_ARCACHE),
.ARPROT (S_ARPROT),
.ARVALID (net_ARVALID),
.ARREADY (S_ARREADY),
// Read Data Channel Signals.
.RID (S_RID),
.RDATA (S_RDATA),
.RRESP (S_RRESP),
.RLAST (S_RLAST),
.RVALID (S_RVALID),
.RREADY (S_RREADY));
wire wr_intr_fifo_full;
reg temp_wr_intr_fifo_full;
/* Interconnect WR_FIFO model instance */
processing_system7_bfm_v2_0_5_intr_wr_mem wr_intr_fifo(SW_CLK, S_RESETN, wr_intr_fifo_full, WR_DATA_ACK_OCM, WR_DATA_ACK_DDR, WR_ADDR, WR_DATA, WR_BYTES, WR_QOS, WR_DATA_VALID_OCM, WR_DATA_VALID_DDR);
/* Register the async 'full' signal to S_ACLK clock */
always@(posedge S_ACLK) temp_wr_intr_fifo_full = wr_intr_fifo_full;
/* Latency type and Debug/Error Control */
reg[1:0] latency_type = RANDOM_CASE;
reg DEBUG_INFO = 1;
reg STOP_ON_ERROR = 1'b1;
/* Internal nets/regs for calling slave BFM API's*/
reg [wr_afi_fifo_data_bits-1:0] wr_fifo [0:max_outstanding_transactions-1];
reg [int_cntr_width-1:0] wr_fifo_wr_ptr = 0, wr_fifo_rd_ptr = 0;
wire wr_fifo_empty;
/* Store the awvalid receive time --- necessary for calculating the bresp latency */
reg [7:0] aw_time_cnt = 0,bresp_time_cnt = 0;
real awvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new awvalid is received
reg awvalid_flag[0:max_outstanding_transactions]; // store the time when a new awvalid is received
/* Address Write Channel handshake*/
reg[int_cntr_width-1:0] aw_cnt = 0;//
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] awsize [0:max_outstanding_transactions-1];
reg [axi_prot_width-1:0] awprot [0:max_outstanding_transactions-1];
reg [axi_lock_width-1:0] awlock [0:max_outstanding_transactions-1];
reg [axi_cache_width-1:0] awcache [0:max_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] awbrst [0:max_outstanding_transactions-1];
reg [axi_len_width-1:0] awlen [0:max_outstanding_transactions-1];
reg aw_flag [0:max_outstanding_transactions-1];
reg [addr_width-1:0] awaddr [0:max_outstanding_transactions-1];
reg [id_bus_width-1:0] awid [0:max_outstanding_transactions-1];
reg [axi_qos_width-1:0] awqos [0:max_outstanding_transactions-1];
wire aw_fifo_full; // indicates awvalid_fifo is full (max outstanding transactions reached)
/* internal fifos to store burst write data, ID & strobes*/
reg [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_outstanding_transactions-1];
reg [max_burst_bytes_width:0] burst_valid_bytes [0:max_outstanding_transactions-1]; /// total valid bytes received in a complete burst transfer
reg wlast_flag [0:max_outstanding_transactions-1]; // flag to indicate WLAST received
wire wd_fifo_full;
/* Write Data Channel and Write Response handshake signals*/
reg [int_cntr_width-1:0] wd_cnt = 0;
reg [(data_bus_width*axi_burst_len)-1:0] aligned_wr_data;
reg [addr_width-1:0] aligned_wr_addr;
reg [max_burst_bytes_width:0] valid_data_bytes;
reg [int_cntr_width-1:0] wr_bresp_cnt = 0;
reg [axi_rsp_width-1:0] bresp;
reg [rsp_fifo_bits-1:0] fifo_bresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response
reg enable_write_bresp;
reg [int_cntr_width-1:0] rd_bresp_cnt = 0;
integer wr_latency_count;
reg wr_delayed;
wire bresp_fifo_empty;
/* keep track of count values */
reg[7:0] wcount;
reg[5:0] wacount;
/* Qos*/
reg [axi_qos_width-1:0] ar_qos, aw_qos;
initial begin
if(DEBUG_INFO) begin
if(enable_this_port)
$display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, slave_name);
else
$display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, slave_name);
end
end
/*--------------------------------------------------------------------------------*/
/* Store the Clock cycle time period */
always@(S_RESETN)
begin
if(S_RESETN) begin
@(posedge S_ACLK);
s_aclk_period = $time;
@(posedge S_ACLK);
s_aclk_period = $time - s_aclk_period;
end
end
/*--------------------------------------------------------------------------------*/
initial slave.set_disable_reset_value_checks(1);
initial begin
repeat(2) @(posedge S_ACLK);
if(!enable_this_port) begin
slave.set_channel_level_info(0);
slave.set_function_level_info(0);
end
slave.RESPONSE_TIMEOUT = 0;
end
/*--------------------------------------------------------------------------------*/
/* Set Latency type to be used */
task set_latency_type;
input[1:0] lat;
begin
if(enable_this_port)
latency_type = lat;
else begin
//if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'Latency Profile' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set ARQoS to be used */
task set_arqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
ar_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'ARQOS' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set AWQoS to be used */
task set_awqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
aw_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'AWQOS' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* get the wr latency number */
function [31:0] get_wr_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : get_wr_lat_number = afi_wr_min;
AVG_CASE : get_wr_lat_number = afi_wr_avg;
WORST_CASE : get_wr_lat_number = afi_wr_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2'b00 : get_wr_lat_number = ($random()%10+ afi_wr_min);
2'b01 : get_wr_lat_number = ($random()%40+ afi_wr_avg);
default : get_wr_lat_number = ($random()%60+ afi_wr_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* get the rd latency number */
function [31:0] get_rd_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : get_rd_lat_number = afi_rd_min;
AVG_CASE : get_rd_lat_number = afi_rd_avg;
WORST_CASE : get_rd_lat_number = afi_rd_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2'b00 : get_rd_lat_number = ($random()%10+ afi_rd_min);
2'b01 : get_rd_lat_number = ($random()%40+ afi_rd_avg);
default : get_rd_lat_number = ($random()%60+ afi_rd_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Check for any WRITE/READs when this port is disabled */
always@(S_AWVALID or S_WVALID or S_ARVALID)
begin
if((S_AWVALID | S_WVALID | S_ARVALID) && !enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. AXI transaction is initiated on this port ...\nSimulation will halt ..",$time, DISP_ERR, slave_name);
$stop;
end
end
/*--------------------------------------------------------------------------------*/
assign net_ARVALID = enable_this_port ? S_ARVALID : 1'b0;
assign net_AWVALID = enable_this_port ? S_AWVALID : 1'b0;
assign net_WVALID = enable_this_port ? S_WVALID : 1'b0;
assign wr_fifo_empty = (wr_fifo_wr_ptr === wr_fifo_rd_ptr)?1'b1: 1'b0;
assign bresp_fifo_empty = (wr_bresp_cnt === rd_bresp_cnt)?1'b1:1'b0;
assign bresp_fifo_full = ((wr_bresp_cnt[int_cntr_width-1] !== rd_bresp_cnt[int_cntr_width-1]) && (wr_bresp_cnt[int_cntr_width-2:0] === rd_bresp_cnt[int_cntr_width-2:0]))?1'b1:1'b0;
assign S_WCOUNT = wcount;
assign S_WACOUNT = wacount;
// FIFO_STATUS (only if AFI port) 1- full
function automatic wrfifo_full ;
input [axi_len_width:0] fifo_space_exp;
integer fifo_space_left;
begin
fifo_space_left = afi_fifo_locations - wcount;
if(fifo_space_left < fifo_space_exp)
wrfifo_full = 1;
else
wrfifo_full = 0;
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Store the awvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or S_AWID or S_AWADDR or S_AWVALID )
begin
if(!S_RESETN)
aw_time_cnt = 0;
else begin
if(S_AWVALID) begin
awvalid_receive_time[aw_time_cnt] = $time;
awvalid_flag[aw_time_cnt] = 1'b1;
aw_time_cnt = aw_time_cnt + 1;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_AWVALID && S_AWREADY) begin
if(S_AWQOS === 0) awqos[aw_cnt[int_cntr_width-2:0]] = aw_qos;
else awqos[aw_cnt[int_cntr_width-2:0]] = S_AWQOS;
end
end
/* Address Write Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
aw_cnt = 0;
wacount = 0;
end else begin
if(S_AWVALID && !wrfifo_full(S_AWLEN+1)) begin
slave.RECEIVE_WRITE_ADDRESS(0,
id_invalid,
awaddr[aw_cnt[int_cntr_width-2:0]],
awlen[aw_cnt[int_cntr_width-2:0]],
awsize[aw_cnt[int_cntr_width-2:0]],
awbrst[aw_cnt[int_cntr_width-2:0]],
awlock[aw_cnt[int_cntr_width-2:0]],
awcache[aw_cnt[int_cntr_width-2:0]],
awprot[aw_cnt[int_cntr_width-2:0]],
awid[aw_cnt[int_cntr_width-2:0]]); /// sampled valid ID.
aw_flag[aw_cnt[int_cntr_width-2:0]] = 1'b1;
aw_cnt = aw_cnt + 1;
wacount = wacount + 1;
end // if (!aw_fifo_full)
end /// if else
end /// always
/*--------------------------------------------------------------------------------*/
/* Write Data Channel Handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wd_cnt = 0;
end else begin
if(aw_flag[wd_cnt[int_cntr_width-2:0]]) begin
if(S_WVALID && !wrfifo_full(awlen[wd_cnt[int_cntr_width-2:0]] + 1)) begin
slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]);
wlast_flag[wd_cnt[int_cntr_width-2:0]] = 1'b1;
wd_cnt = wd_cnt + 1;
end
end else begin
if(!wrfifo_full(axi_burst_len+1) && S_WVALID) begin
slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]);
wlast_flag[wd_cnt[int_cntr_width-2:0]] = 1'b1;
wd_cnt = wd_cnt + 1;
end
end /// if
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
/* Align the wrap data for write transaction */
task automatic get_wrap_aligned_wr_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
output [addr_width-1:0] start_addr; /// aligned start address
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
wrp_data = wrp_data << ((data_bus_width*axi_burst_len) - (v_bytes*8));
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data << 8;
temp_data[7:0] = wrp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8];
wrp_data = wrp_data << 8;
wrp_bytes = wrp_bytes - 1;
end
wrp_bytes = addr - start_addr;
wrp_data = b_data << (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
/* Calculate the Response for each read/write transaction */
function [axi_rsp_width-1:0] calculate_resp;
input [addr_width-1:0] awaddr;
input [axi_prot_width-1:0] awprot;
reg [axi_rsp_width-1:0] rsp;
begin
rsp = AXI_OK;
/* Address Decode */
if(decode_address(awaddr) === INVALID_MEM_TYPE) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) ",$time, DISP_ERR, slave_name, awaddr);
end
else if(decode_address(awaddr) === REG_MEM) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Access to Register Map(0x%0h) is not allowed through this port.",$time, DISP_ERR, slave_name, awaddr);
end
if(secure_access_enabled && awprot[1])
rsp = AXI_DEC_ERR; // decode error
calculate_resp = rsp;
end
endfunction
/*--------------------------------------------------------------------------------*/
reg[max_burst_bits-1:0] temp_wr_data;
/* Store the Write response for each write transaction */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wr_fifo_wr_ptr = 0;
wcount = 0;
end else begin
enable_write_bresp = aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] && wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]];
/* calculate bresp only when AWVALID && WLAST is received */
if(enable_write_bresp) begin
aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] = 0;
wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] = 0;
bresp = calculate_resp(awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], awprot[wr_fifo_wr_ptr[int_cntr_width-2:0]]);
/* Fill AFI_WR_data FIFO */
if(bresp === AXI_OK ) begin
if(awbrst[wr_fifo_wr_ptr[int_cntr_width-2:0]]=== AXI_WRAP) begin /// wrap type? then align the data
get_wrap_aligned_wr_data(aligned_wr_data, aligned_wr_addr, awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]],burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]]); /// gives wrapped start address
end else begin
aligned_wr_data = burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]];
aligned_wr_addr = awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]] ;
end
valid_data_bytes = burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]];
end else
valid_data_bytes = 0;
temp_wr_data = aligned_wr_data;
wr_fifo[wr_fifo_wr_ptr[int_cntr_width-2:0]] = {awqos[wr_fifo_wr_ptr[int_cntr_width-2:0]], awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]], awid[wr_fifo_wr_ptr[int_cntr_width-2:0]], bresp, temp_wr_data, aligned_wr_addr, valid_data_bytes};
wcount = wcount + awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]]+1;
wr_fifo_wr_ptr = wr_fifo_wr_ptr + 1;
end
end // else
end // always
/*--------------------------------------------------------------------------------*/
/* Send Write Response Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
rd_bresp_cnt = 0;
wr_latency_count = get_wr_lat_number(1);
wr_delayed = 0;
bresp_time_cnt = 0;
end else begin
wr_delayed = 1'b0;
if(awvalid_flag[bresp_time_cnt] && (($time - awvalid_receive_time[bresp_time_cnt])/s_aclk_period >= wr_latency_count))
wr_delayed = 1;
if(!bresp_fifo_empty && wr_delayed) begin
slave.SEND_WRITE_RESPONSE(fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb], // ID
fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_msb : rsp_lsb] // Response
);
wr_delayed = 0;
awvalid_flag[bresp_time_cnt] = 1'b0;
bresp_time_cnt = bresp_time_cnt+1;
rd_bresp_cnt = rd_bresp_cnt + 1;
wr_latency_count = get_wr_lat_number(1);
end
end // else
end//always
/*--------------------------------------------------------------------------------*/
/* Write Response Channel handshake */
reg wr_int_state;
/* Reading from the wr_fifo and sending to Interconnect fifo*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wr_int_state = 1'b0;
wr_bresp_cnt = 0;
wr_fifo_rd_ptr = 0;
end else begin
case(wr_int_state)
1'b0 : begin
wr_int_state = 1'b0;
if(!temp_wr_intr_fifo_full && !bresp_fifo_full && !wr_fifo_empty) begin
wr_intr_fifo.write_mem({wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_qos_msb:wr_afi_qos_lsb], wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_data_msb:wr_afi_bytes_lsb]}); /// qos, data, address and valid_bytes
wr_int_state = 1'b1;
/* start filling the write response fifo at the same time */
fifo_bresp[wr_bresp_cnt[int_cntr_width-2:0]] = wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_id_msb:wr_afi_rsp_lsb]; // ID and Resp
wcount = wcount - (wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_ln_msb:wr_afi_ln_lsb] + 1); /// burst length
wacount = wacount - 1;
wr_fifo_rd_ptr = wr_fifo_rd_ptr + 1;
wr_bresp_cnt = wr_bresp_cnt+1;
end
end
1'b1 : begin
wr_int_state = 0;
end
endcase
end
end
/*--------------------------------------------------------------------------------*/
/*-------------------------------- WRITE HANDSHAKE END ----------------------------------------*/
/*-------------------------------- READ HANDSHAKE ---------------------------------------------*/
/* READ CHANNELS */
/* Store the arvalid receive time --- necessary for calculating latency in sending the rresp latency */
reg [7:0] ar_time_cnt = 0,rresp_time_cnt = 0;
real arvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new arvalid is received
reg arvalid_flag[0:max_outstanding_transactions]; // store the time when a new arvalid is received
reg [int_cntr_width-1:0] ar_cnt = 0;// counter for arvalid info
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] arsize [0:max_outstanding_transactions-1];
reg [axi_prot_width-1:0] arprot [0:max_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] arbrst [0:max_outstanding_transactions-1];
reg [axi_len_width-1:0] arlen [0:max_outstanding_transactions-1];
reg [axi_cache_width-1:0] arcache [0:max_outstanding_transactions-1];
reg [axi_lock_width-1:0] arlock [0:max_outstanding_transactions-1];
reg ar_flag [0:max_outstanding_transactions-1];
reg [addr_width-1:0] araddr [0:max_outstanding_transactions-1];
reg [id_bus_width-1:0] arid [0:max_outstanding_transactions-1];
reg [axi_qos_width-1:0] arqos [0:max_outstanding_transactions-1];
wire ar_fifo_full; // indicates arvalid_fifo is full (max outstanding transactions reached)
reg [int_cntr_width-1:0] wr_rresp_cnt = 0;
reg [axi_rsp_width-1:0] rresp;
reg [rsp_fifo_bits-1:0] fifo_rresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response
reg enable_write_rresp;
/* Send Read Response & Data Channel handshake */
integer rd_latency_count;
reg rd_delayed;
reg [rd_afi_fifo_bits-1:0] read_fifo[0:max_outstanding_transactions-1]; /// Read Burst Data, addr, size, burst, len, RID, RRESP, valid_bytes
reg [int_cntr_width-1:0] rd_fifo_wr_ptr = 0, rd_fifo_rd_ptr = 0;
wire read_fifo_full;
reg [7:0] rcount;
reg [2:0] racount;
wire rd_intr_fifo_full, rd_intr_fifo_empty;
wire read_fifo_empty;
/* signals to communicate with interconnect RD_FIFO model */
reg rd_req, invalid_rd_req;
/* REad control Info
56:25 : Address (32)
24:22 : Size (3)
21:20 : BRST (2)
19:16 : LEN (4)
15:10 : RID (6)
9:8 : RRSP (2)
7:0 : byte cnt (8)
*/
reg [rd_info_bits-1:0] read_control_info;
reg [(data_bus_width*axi_burst_len)-1:0] aligned_rd_data;
reg temp_rd_intr_fifo_empty;
processing_system7_bfm_v2_0_5_intr_rd_mem rd_intr_fifo(SW_CLK, S_RESETN, rd_intr_fifo_full, rd_intr_fifo_empty, rd_req, invalid_rd_req, read_control_info , RD_DATA_OCM, RD_DATA_DDR, RD_DATA_VALID_OCM, RD_DATA_VALID_DDR);
assign read_fifo_empty = (rd_fifo_wr_ptr === rd_fifo_rd_ptr)?1'b1: 1'b0;
assign S_RCOUNT = rcount;
assign S_RACOUNT = racount;
/* Register the asynch signal empty coming from Interconnect READ FIFO */
always@(posedge S_ACLK) temp_rd_intr_fifo_empty = rd_intr_fifo_empty;
// FIFO_STATUS (only if AFI port) 1- full
function automatic rdfifo_full ;
input [axi_len_width:0] fifo_space_exp;
integer fifo_space_left;
begin
fifo_space_left = afi_fifo_locations - rcount;
if(fifo_space_left < fifo_space_exp)
rdfifo_full = 1;
else
rdfifo_full = 0;
end
endfunction
/* Store the arvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or S_ARID or S_ARADDR or S_ARVALID )
begin
if(!S_RESETN)
ar_time_cnt = 0;
else begin
if(S_ARVALID) begin
arvalid_receive_time[ar_time_cnt] = $time;
arvalid_flag[ar_time_cnt] = 1'b1;
ar_time_cnt = ar_time_cnt + 1;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_ARVALID && S_ARREADY) begin
if(S_ARQOS === 0) arqos[aw_cnt[int_cntr_width-2:0]] = ar_qos;
else arqos[aw_cnt[int_cntr_width-2:0]] = S_ARQOS;
end
end
/* Address Read Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
ar_cnt = 0;
racount = 0;
end else begin
if(S_ARVALID && !rdfifo_full(S_ARLEN+1)) begin /// if AFI read fifo is not full
slave.RECEIVE_READ_ADDRESS(0,
id_invalid,
araddr[ar_cnt[int_cntr_width-2:0]],
arlen[ar_cnt[int_cntr_width-2:0]],
arsize[ar_cnt[int_cntr_width-2:0]],
arbrst[ar_cnt[int_cntr_width-2:0]],
arlock[ar_cnt[int_cntr_width-2:0]],
arcache[ar_cnt[int_cntr_width-2:0]],
arprot[ar_cnt[int_cntr_width-2:0]],
arid[ar_cnt[int_cntr_width-2:0]]); /// sampled valid ID.
ar_flag[ar_cnt[int_cntr_width-2:0]] = 1'b1;
ar_cnt = ar_cnt+1;
racount = racount + 1;
end /// if(!ar_fifo_full)
end /// if else
end /// always*/
/*--------------------------------------------------------------------------------*/
/* Align Wrap data for read transaction*/
task automatic get_wrap_aligned_rd_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [addr_width-1:0] start_addr;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data >> 8;
temp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8] = wrp_data[7:0];
wrp_data = wrp_data >> 8;
wrp_bytes = wrp_bytes - 1;
end
temp_data = temp_data >> ((data_bus_width*axi_burst_len) - (v_bytes*8));
wrp_bytes = addr - start_addr;
wrp_data = b_data >> (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
parameter RD_DATA_REQ = 1'b0, WAIT_RD_VALID = 1'b1;
reg rd_fifo_state;
reg [addr_width-1:0] temp_read_address;
reg [max_burst_bytes_width:0] temp_rd_valid_bytes;
/* get the data from memory && also calculate the rresp*/
always@(negedge S_RESETN or posedge SW_CLK)
begin
if(!S_RESETN)begin
wr_rresp_cnt =0;
rd_fifo_state = RD_DATA_REQ;
temp_rd_valid_bytes = 0;
temp_read_address = 0;
RD_REQ_DDR = 1'b0;
RD_REQ_OCM = 1'b0;
rd_req = 0;
invalid_rd_req= 0;
RD_QOS = 0;
end else begin
case(rd_fifo_state)
RD_DATA_REQ : begin
rd_fifo_state = RD_DATA_REQ;
RD_REQ_DDR = 1'b0;
RD_REQ_OCM = 1'b0;
invalid_rd_req = 0;
if(ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] && !rd_intr_fifo_full) begin /// check the rd_fifo_bytes, interconnect fifo full condition
ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] = 0;
rresp = calculate_resp(araddr[wr_rresp_cnt[int_cntr_width-2:0]],arprot[wr_rresp_cnt[int_cntr_width-2:0]]);
temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_cntr_width-2:0]]+1)*(2**arsize[wr_rresp_cnt[int_cntr_width-2:0]]);//data_bus_width/8;
if(arbrst[wr_rresp_cnt[int_cntr_width-2:0]] === AXI_WRAP) /// wrap begin
temp_read_address = (araddr[wr_rresp_cnt[int_cntr_width-2:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes;
else
temp_read_address = araddr[wr_rresp_cnt[int_cntr_width-2:0]];
if(rresp === AXI_OK) begin
case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_cntr_width-2:0]]);
OCM_MEM : RD_REQ_OCM = 1;
DDR_MEM : RD_REQ_DDR = 1;
default : invalid_rd_req = 1;
endcase
end else
invalid_rd_req = 1;
RD_ADDR = temp_read_address; ///araddr[wr_rresp_cnt[int_cntr_width-2:0]];
RD_BYTES = temp_rd_valid_bytes;
RD_QOS = arqos[wr_rresp_cnt[int_cntr_width-2:0]];
rd_fifo_state = WAIT_RD_VALID;
rd_req = 1;
racount = racount - 1;
read_control_info = {araddr[wr_rresp_cnt[int_cntr_width-2:0]], arsize[wr_rresp_cnt[int_cntr_width-2:0]], arbrst[wr_rresp_cnt[int_cntr_width-2:0]], arlen[wr_rresp_cnt[int_cntr_width-2:0]], arid[wr_rresp_cnt[int_cntr_width-2:0]], rresp, temp_rd_valid_bytes };
wr_rresp_cnt = wr_rresp_cnt + 1;
end
end
WAIT_RD_VALID : begin
rd_fifo_state = WAIT_RD_VALID;
rd_req = 0;
if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd_req) begin ///temp_dec == 2'b11) begin
RD_REQ_DDR = 1'b0;
RD_REQ_OCM = 1'b0;
invalid_rd_req = 0;
rd_fifo_state = RD_DATA_REQ;
end
end
endcase
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
/* thread to fill in the AFI RD_FIFO */
reg[rd_afi_fifo_bits-1:0] temp_rd_data;//Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes
reg tmp_state;
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN)begin
rd_fifo_wr_ptr = 0;
rcount = 0;
tmp_state = 0;
end else begin
case(tmp_state)
0 : begin
tmp_state = 0;
if(!temp_rd_intr_fifo_empty) begin
rd_intr_fifo.read_mem(temp_rd_data);
tmp_state = 1;
end
end
1 : begin
tmp_state = 1;
if(!rdfifo_full(temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1)) begin
read_fifo[rd_fifo_wr_ptr[int_cntr_width-2:0]] = temp_rd_data;
rd_fifo_wr_ptr = rd_fifo_wr_ptr + 1;
rcount = rcount + temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1; /// Burst length
tmp_state = 0;
end
end
endcase
end
end
/*--------------------------------------------------------------------------------*/
reg[max_burst_bytes_width:0] rd_v_b;
reg[rd_afi_fifo_bits-1:0] tmp_fifo_rd; /// Data, addr, size, burst, len, RID, RRESP,valid_bytes
reg[(data_bus_width*axi_burst_len)-1:0] temp_read_data;
reg[(axi_rsp_width*axi_burst_len)-1:0] temp_read_rsp;
/* Read Data Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN)begin
rd_fifo_rd_ptr = 0;
rd_latency_count = get_rd_lat_number(1);
rd_delayed = 0;
rresp_time_cnt = 0;
rd_v_b = 0;
end else begin
if(arvalid_flag[rresp_time_cnt] && ((($time - arvalid_receive_time[rresp_time_cnt])/s_aclk_period) >= rd_latency_count)) begin
rd_delayed = 1;
end
if(!read_fifo_empty && rd_delayed)begin
rd_delayed = 0;
arvalid_flag[rresp_time_cnt] = 1'b0;
tmp_fifo_rd = read_fifo[rd_fifo_rd_ptr[int_cntr_width-2:0]];
rd_v_b = (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+1)*(2**tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb]);
temp_read_data = tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb];
if(tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb] === AXI_WRAP) begin
get_wrap_aligned_rd_data(aligned_rd_data, tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb], tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb], rd_v_b);
temp_read_data = aligned_rd_data;
end
temp_read_rsp = 0;
repeat(axi_burst_len) begin
temp_read_rsp = temp_read_rsp >> axi_rsp_width;
temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = tmp_fifo_rd[rd_afi_rsp_msb : rd_afi_rsp_lsb];
end
slave.SEND_READ_BURST_RESP_CTRL(tmp_fifo_rd[rd_afi_id_msb : rd_afi_id_lsb],
tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb],
tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb],
tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb],
tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb],
temp_read_data,
temp_read_rsp);
rcount = rcount - (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+ 1) ;
rresp_time_cnt = rresp_time_cnt+1;
rd_latency_count = get_rd_lat_number(1);
rd_fifo_rd_ptr = rd_fifo_rd_ptr+1;
end
end /// else
end /// always
endmodule |
module processing_system7_bfm_v2_0_5_regc(
rstn,
sw_clk,
/* Goes to port 0 of REG */
reg_rd_req_port0,
reg_rd_dv_port0,
reg_rd_addr_port0,
reg_rd_data_port0,
reg_rd_bytes_port0,
reg_rd_qos_port0,
/* Goes to port 1 of REG */
reg_rd_req_port1,
reg_rd_dv_port1,
reg_rd_addr_port1,
reg_rd_data_port1,
reg_rd_bytes_port1,
reg_rd_qos_port1
);
input rstn;
input sw_clk;
input reg_rd_req_port0;
output reg_rd_dv_port0;
input[31:0] reg_rd_addr_port0;
output[1023:0] reg_rd_data_port0;
input[7:0] reg_rd_bytes_port0;
input [3:0] reg_rd_qos_port0;
input reg_rd_req_port1;
output reg_rd_dv_port1;
input[31:0] reg_rd_addr_port1;
output[1023:0] reg_rd_data_port1;
input[7:0] reg_rd_bytes_port1;
input[3:0] reg_rd_qos_port1;
wire [3:0] rd_qos;
reg [1023:0] rd_data;
wire [31:0] rd_addr;
wire [7:0] rd_bytes;
reg rd_dv;
wire rd_req;
processing_system7_bfm_v2_0_5_arb_rd reg_read_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(reg_rd_qos_port0),
.qos2(reg_rd_qos_port1),
.prt_req1(reg_rd_req_port0),
.prt_req2(reg_rd_req_port1),
.prt_data1(reg_rd_data_port0),
.prt_data2(reg_rd_data_port1),
.prt_addr1(reg_rd_addr_port0),
.prt_addr2(reg_rd_addr_port1),
.prt_bytes1(reg_rd_bytes_port0),
.prt_bytes2(reg_rd_bytes_port1),
.prt_dv1(reg_rd_dv_port0),
.prt_dv2(reg_rd_dv_port1),
.prt_qos(rd_qos),
.prt_req(rd_req),
.prt_data(rd_data),
.prt_addr(rd_addr),
.prt_bytes(rd_bytes),
.prt_dv(rd_dv)
);
processing_system7_bfm_v2_0_5_reg_map regm();
reg state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
rd_dv <= 0;
state <= 0;
end else begin
case(state)
0:begin
state <= 0;
rd_dv <= 0;
if(rd_req) begin
regm.read_reg_mem(rd_data,rd_addr, rd_bytes);
rd_dv <= 1;
state <= 1;
end
end
1:begin
rd_dv <= 0;
state <= 0;
end
endcase
end /// if
end// always
endmodule |
module processing_system7_bfm_v2_0_5_regc(
rstn,
sw_clk,
/* Goes to port 0 of REG */
reg_rd_req_port0,
reg_rd_dv_port0,
reg_rd_addr_port0,
reg_rd_data_port0,
reg_rd_bytes_port0,
reg_rd_qos_port0,
/* Goes to port 1 of REG */
reg_rd_req_port1,
reg_rd_dv_port1,
reg_rd_addr_port1,
reg_rd_data_port1,
reg_rd_bytes_port1,
reg_rd_qos_port1
);
input rstn;
input sw_clk;
input reg_rd_req_port0;
output reg_rd_dv_port0;
input[31:0] reg_rd_addr_port0;
output[1023:0] reg_rd_data_port0;
input[7:0] reg_rd_bytes_port0;
input [3:0] reg_rd_qos_port0;
input reg_rd_req_port1;
output reg_rd_dv_port1;
input[31:0] reg_rd_addr_port1;
output[1023:0] reg_rd_data_port1;
input[7:0] reg_rd_bytes_port1;
input[3:0] reg_rd_qos_port1;
wire [3:0] rd_qos;
reg [1023:0] rd_data;
wire [31:0] rd_addr;
wire [7:0] rd_bytes;
reg rd_dv;
wire rd_req;
processing_system7_bfm_v2_0_5_arb_rd reg_read_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(reg_rd_qos_port0),
.qos2(reg_rd_qos_port1),
.prt_req1(reg_rd_req_port0),
.prt_req2(reg_rd_req_port1),
.prt_data1(reg_rd_data_port0),
.prt_data2(reg_rd_data_port1),
.prt_addr1(reg_rd_addr_port0),
.prt_addr2(reg_rd_addr_port1),
.prt_bytes1(reg_rd_bytes_port0),
.prt_bytes2(reg_rd_bytes_port1),
.prt_dv1(reg_rd_dv_port0),
.prt_dv2(reg_rd_dv_port1),
.prt_qos(rd_qos),
.prt_req(rd_req),
.prt_data(rd_data),
.prt_addr(rd_addr),
.prt_bytes(rd_bytes),
.prt_dv(rd_dv)
);
processing_system7_bfm_v2_0_5_reg_map regm();
reg state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
rd_dv <= 0;
state <= 0;
end else begin
case(state)
0:begin
state <= 0;
rd_dv <= 0;
if(rd_req) begin
regm.read_reg_mem(rd_data,rd_addr, rd_bytes);
rd_dv <= 1;
state <= 1;
end
end
1:begin
rd_dv <= 0;
state <= 0;
end
endcase
end /// if
end// always
endmodule |
module processing_system7_bfm_v2_0_5_arb_rd_4(
rstn,
sw_clk,
qos1,
qos2,
qos3,
qos4,
prt_req1,
prt_req2,
prt_req3,
prt_req4,
prt_data1,
prt_data2,
prt_data3,
prt_data4,
prt_addr1,
prt_addr2,
prt_addr3,
prt_addr4,
prt_bytes1,
prt_bytes2,
prt_bytes3,
prt_bytes4,
prt_dv1,
prt_dv2,
prt_dv3,
prt_dv4,
prt_qos,
prt_req,
prt_data,
prt_addr,
prt_bytes,
prt_dv
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2,qos3,qos4;
input prt_req1, prt_req2,prt_req3, prt_req4, prt_dv;
output reg [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4;
input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4;
input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4;
output reg prt_dv1,prt_dv2,prt_dv3,prt_dv4,prt_req;
input [max_burst_bits-1:0] prt_data;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
output reg [axi_qos_width-1:0] prt_qos;
parameter wait_req = 3'b000, serv_req1 = 3'b001, serv_req2 = 3'b010, serv_req3 = 3'b011, serv_req4 = 3'b100, wait_dv_low=3'b101;
reg [2:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
prt_req = 1'b0;
if(prt_req1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_req2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_req4) begin
prt_req = 1;
prt_addr = prt_addr4;
prt_qos = qos4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
serv_req1:begin
state = serv_req1;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
if(prt_dv)begin
prt_dv1 = 1'b1;
prt_data1 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req2) begin
state = serv_req2;
prt_qos = qos2;
prt_req = 1;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req3) begin
state = serv_req3;
prt_qos = qos3;
prt_req = 1;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_req4) begin
prt_req = 1;
prt_qos = qos4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
end
serv_req2:begin
state = serv_req2;
prt_dv1 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
if(prt_dv)begin
prt_dv2 = 1'b1;
prt_data2 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_req4) begin
state = serv_req4;
prt_req = 1;
prt_qos = qos4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_req1) begin
prt_req = 1;
prt_addr = prt_addr1;
prt_qos = qos1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req3:begin
state = serv_req3;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv4 = 1'b0;
if(prt_dv)begin
prt_dv3 = 1'b1;
prt_data3 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req4) begin
state = serv_req4;
prt_qos = qos4;
prt_req = 1;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_req1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_req2) begin
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end
end
end
serv_req4:begin
state = serv_req4;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
if(prt_dv)begin
prt_dv4 = 1'b1;
prt_data4 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req1) begin
state = serv_req1;
prt_qos = qos1;
prt_req = 1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_req2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req3) begin
prt_req = 1;
prt_addr = prt_addr3;
prt_qos = qos3;
prt_bytes = prt_bytes3;
state = serv_req3;
end
end
end
wait_dv_low:begin
state = wait_dv_low;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
if(!prt_dv)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule |
module processing_system7_bfm_v2_0_5_arb_rd_4(
rstn,
sw_clk,
qos1,
qos2,
qos3,
qos4,
prt_req1,
prt_req2,
prt_req3,
prt_req4,
prt_data1,
prt_data2,
prt_data3,
prt_data4,
prt_addr1,
prt_addr2,
prt_addr3,
prt_addr4,
prt_bytes1,
prt_bytes2,
prt_bytes3,
prt_bytes4,
prt_dv1,
prt_dv2,
prt_dv3,
prt_dv4,
prt_qos,
prt_req,
prt_data,
prt_addr,
prt_bytes,
prt_dv
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2,qos3,qos4;
input prt_req1, prt_req2,prt_req3, prt_req4, prt_dv;
output reg [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4;
input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4;
input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4;
output reg prt_dv1,prt_dv2,prt_dv3,prt_dv4,prt_req;
input [max_burst_bits-1:0] prt_data;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
output reg [axi_qos_width-1:0] prt_qos;
parameter wait_req = 3'b000, serv_req1 = 3'b001, serv_req2 = 3'b010, serv_req3 = 3'b011, serv_req4 = 3'b100, wait_dv_low=3'b101;
reg [2:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
prt_req = 1'b0;
if(prt_req1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_req2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_req4) begin
prt_req = 1;
prt_addr = prt_addr4;
prt_qos = qos4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
serv_req1:begin
state = serv_req1;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
if(prt_dv)begin
prt_dv1 = 1'b1;
prt_data1 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req2) begin
state = serv_req2;
prt_qos = qos2;
prt_req = 1;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req3) begin
state = serv_req3;
prt_qos = qos3;
prt_req = 1;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_req4) begin
prt_req = 1;
prt_qos = qos4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
end
serv_req2:begin
state = serv_req2;
prt_dv1 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
if(prt_dv)begin
prt_dv2 = 1'b1;
prt_data2 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_req4) begin
state = serv_req4;
prt_req = 1;
prt_qos = qos4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_req1) begin
prt_req = 1;
prt_addr = prt_addr1;
prt_qos = qos1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req3:begin
state = serv_req3;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv4 = 1'b0;
if(prt_dv)begin
prt_dv3 = 1'b1;
prt_data3 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req4) begin
state = serv_req4;
prt_qos = qos4;
prt_req = 1;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_req1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_req2) begin
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end
end
end
serv_req4:begin
state = serv_req4;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
if(prt_dv)begin
prt_dv4 = 1'b1;
prt_data4 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req1) begin
state = serv_req1;
prt_qos = qos1;
prt_req = 1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_req2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req3) begin
prt_req = 1;
prt_addr = prt_addr3;
prt_qos = qos3;
prt_bytes = prt_bytes3;
state = serv_req3;
end
end
end
wait_dv_low:begin
state = wait_dv_low;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
if(!prt_dv)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule |
module processing_system7_bfm_v2_0_5_ssw_hp(
sw_clk,
rstn,
w_qos_hp0,
r_qos_hp0,
w_qos_hp1,
r_qos_hp1,
w_qos_hp2,
r_qos_hp2,
w_qos_hp3,
r_qos_hp3,
wr_ack_ddr_hp0,
wr_data_hp0,
wr_addr_hp0,
wr_bytes_hp0,
wr_dv_ddr_hp0,
rd_req_ddr_hp0,
rd_addr_hp0,
rd_bytes_hp0,
rd_data_ddr_hp0,
rd_dv_ddr_hp0,
rd_data_ocm_hp0,
wr_ack_ocm_hp0,
wr_dv_ocm_hp0,
rd_req_ocm_hp0,
rd_dv_ocm_hp0,
wr_ack_ddr_hp1,
wr_data_hp1,
wr_addr_hp1,
wr_bytes_hp1,
wr_dv_ddr_hp1,
rd_req_ddr_hp1,
rd_addr_hp1,
rd_bytes_hp1,
rd_data_ddr_hp1,
rd_data_ocm_hp1,
rd_dv_ddr_hp1,
wr_ack_ocm_hp1,
wr_dv_ocm_hp1,
rd_req_ocm_hp1,
rd_dv_ocm_hp1,
wr_ack_ddr_hp2,
wr_data_hp2,
wr_addr_hp2,
wr_bytes_hp2,
wr_dv_ddr_hp2,
rd_req_ddr_hp2,
rd_addr_hp2,
rd_bytes_hp2,
rd_data_ddr_hp2,
rd_data_ocm_hp2,
rd_dv_ddr_hp2,
wr_ack_ocm_hp2,
wr_dv_ocm_hp2,
rd_req_ocm_hp2,
rd_dv_ocm_hp2,
wr_ack_ddr_hp3,
wr_data_hp3,
wr_addr_hp3,
wr_bytes_hp3,
wr_dv_ddr_hp3,
rd_req_ddr_hp3,
rd_addr_hp3,
rd_bytes_hp3,
rd_data_ocm_hp3,
rd_data_ddr_hp3,
rd_dv_ddr_hp3,
wr_ack_ocm_hp3,
wr_dv_ocm_hp3,
rd_req_ocm_hp3,
rd_dv_ocm_hp3,
ddr_wr_ack0,
ddr_wr_dv0,
ddr_rd_req0,
ddr_rd_dv0,
ddr_rd_qos0,
ddr_wr_qos0,
ddr_wr_addr0,
ddr_wr_data0,
ddr_wr_bytes0,
ddr_rd_addr0,
ddr_rd_data0,
ddr_rd_bytes0,
ddr_wr_ack1,
ddr_wr_dv1,
ddr_rd_req1,
ddr_rd_dv1,
ddr_rd_qos1,
ddr_wr_qos1,
ddr_wr_addr1,
ddr_wr_data1,
ddr_wr_bytes1,
ddr_rd_addr1,
ddr_rd_data1,
ddr_rd_bytes1,
ocm_wr_ack,
ocm_wr_dv,
ocm_rd_req,
ocm_rd_dv,
ocm_wr_qos,
ocm_rd_qos,
ocm_wr_addr,
ocm_wr_data,
ocm_wr_bytes,
ocm_rd_addr,
ocm_rd_data,
ocm_rd_bytes
);
input sw_clk;
input rstn;
input [3:0] w_qos_hp0;
input [3:0] r_qos_hp0;
input [3:0] w_qos_hp1;
input [3:0] r_qos_hp1;
input [3:0] w_qos_hp2;
input [3:0] r_qos_hp2;
input [3:0] w_qos_hp3;
input [3:0] r_qos_hp3;
output [3:0] ddr_rd_qos0;
output [3:0] ddr_wr_qos0;
output [3:0] ddr_rd_qos1;
output [3:0] ddr_wr_qos1;
output [3:0] ocm_wr_qos;
output [3:0] ocm_rd_qos;
output wr_ack_ddr_hp0;
input [1023:0] wr_data_hp0;
input [31:0] wr_addr_hp0;
input [7:0] wr_bytes_hp0;
output wr_dv_ddr_hp0;
input rd_req_ddr_hp0;
input [31:0] rd_addr_hp0;
input [7:0] rd_bytes_hp0;
output [1023:0] rd_data_ddr_hp0;
output rd_dv_ddr_hp0;
output wr_ack_ddr_hp1;
input [1023:0] wr_data_hp1;
input [31:0] wr_addr_hp1;
input [7:0] wr_bytes_hp1;
output wr_dv_ddr_hp1;
input rd_req_ddr_hp1;
input [31:0] rd_addr_hp1;
input [7:0] rd_bytes_hp1;
output [1023:0] rd_data_ddr_hp1;
output rd_dv_ddr_hp1;
output wr_ack_ddr_hp2;
input [1023:0] wr_data_hp2;
input [31:0] wr_addr_hp2;
input [7:0] wr_bytes_hp2;
output wr_dv_ddr_hp2;
input rd_req_ddr_hp2;
input [31:0] rd_addr_hp2;
input [7:0] rd_bytes_hp2;
output [1023:0] rd_data_ddr_hp2;
output rd_dv_ddr_hp2;
output wr_ack_ddr_hp3;
input [1023:0] wr_data_hp3;
input [31:0] wr_addr_hp3;
input [7:0] wr_bytes_hp3;
output wr_dv_ddr_hp3;
input rd_req_ddr_hp3;
input [31:0] rd_addr_hp3;
input [7:0] rd_bytes_hp3;
output [1023:0] rd_data_ddr_hp3;
output rd_dv_ddr_hp3;
input ddr_wr_ack0;
output ddr_wr_dv0;
output [31:0]ddr_wr_addr0;
output [1023:0]ddr_wr_data0;
output [7:0]ddr_wr_bytes0;
input ddr_rd_dv0;
input [1023:0] ddr_rd_data0;
output ddr_rd_req0;
output [31:0] ddr_rd_addr0;
output [7:0] ddr_rd_bytes0;
input ddr_wr_ack1;
output ddr_wr_dv1;
output [31:0]ddr_wr_addr1;
output [1023:0]ddr_wr_data1;
output [7:0]ddr_wr_bytes1;
input ddr_rd_dv1;
input [1023:0] ddr_rd_data1;
output ddr_rd_req1;
output [31:0] ddr_rd_addr1;
output [7:0] ddr_rd_bytes1;
output wr_ack_ocm_hp0;
input wr_dv_ocm_hp0;
input rd_req_ocm_hp0;
output rd_dv_ocm_hp0;
output [1023:0] rd_data_ocm_hp0;
output wr_ack_ocm_hp1;
input wr_dv_ocm_hp1;
input rd_req_ocm_hp1;
output rd_dv_ocm_hp1;
output [1023:0] rd_data_ocm_hp1;
output wr_ack_ocm_hp2;
input wr_dv_ocm_hp2;
input rd_req_ocm_hp2;
output rd_dv_ocm_hp2;
output [1023:0] rd_data_ocm_hp2;
output wr_ack_ocm_hp3;
input wr_dv_ocm_hp3;
input rd_req_ocm_hp3;
output rd_dv_ocm_hp3;
output [1023:0] rd_data_ocm_hp3;
input ocm_wr_ack;
output ocm_wr_dv;
output [31:0]ocm_wr_addr;
output [1023:0]ocm_wr_data;
output [7:0]ocm_wr_bytes;
input ocm_rd_dv;
input [1023:0] ocm_rd_data;
output ocm_rd_req;
output [31:0] ocm_rd_addr;
output [7:0] ocm_rd_bytes;
/* FOR DDR */
processing_system7_bfm_v2_0_5_arb_hp0_1 ddr_hp01 (
.sw_clk(sw_clk),
.rstn(rstn),
.w_qos_hp0(w_qos_hp0),
.r_qos_hp0(r_qos_hp0),
.w_qos_hp1(w_qos_hp1),
.r_qos_hp1(r_qos_hp1),
.wr_ack_ddr_hp0(wr_ack_ddr_hp0),
.wr_data_hp0(wr_data_hp0),
.wr_addr_hp0(wr_addr_hp0),
.wr_bytes_hp0(wr_bytes_hp0),
.wr_dv_ddr_hp0(wr_dv_ddr_hp0),
.rd_req_ddr_hp0(rd_req_ddr_hp0),
.rd_addr_hp0(rd_addr_hp0),
.rd_bytes_hp0(rd_bytes_hp0),
.rd_data_ddr_hp0(rd_data_ddr_hp0),
.rd_dv_ddr_hp0(rd_dv_ddr_hp0),
.wr_ack_ddr_hp1(wr_ack_ddr_hp1),
.wr_data_hp1(wr_data_hp1),
.wr_addr_hp1(wr_addr_hp1),
.wr_bytes_hp1(wr_bytes_hp1),
.wr_dv_ddr_hp1(wr_dv_ddr_hp1),
.rd_req_ddr_hp1(rd_req_ddr_hp1),
.rd_addr_hp1(rd_addr_hp1),
.rd_bytes_hp1(rd_bytes_hp1),
.rd_data_ddr_hp1(rd_data_ddr_hp1),
.rd_dv_ddr_hp1(rd_dv_ddr_hp1),
.ddr_wr_ack(ddr_wr_ack0),
.ddr_wr_dv(ddr_wr_dv0),
.ddr_rd_req(ddr_rd_req0),
.ddr_rd_dv(ddr_rd_dv0),
.ddr_rd_qos(ddr_rd_qos0),
.ddr_wr_qos(ddr_wr_qos0),
.ddr_wr_addr(ddr_wr_addr0),
.ddr_wr_data(ddr_wr_data0),
.ddr_wr_bytes(ddr_wr_bytes0),
.ddr_rd_addr(ddr_rd_addr0),
.ddr_rd_data(ddr_rd_data0),
.ddr_rd_bytes(ddr_rd_bytes0)
);
/* FOR DDR */
processing_system7_bfm_v2_0_5_arb_hp2_3 ddr_hp23 (
.sw_clk(sw_clk),
.rstn(rstn),
.w_qos_hp2(w_qos_hp2),
.r_qos_hp2(r_qos_hp2),
.w_qos_hp3(w_qos_hp3),
.r_qos_hp3(r_qos_hp3),
.wr_ack_ddr_hp2(wr_ack_ddr_hp2),
.wr_data_hp2(wr_data_hp2),
.wr_addr_hp2(wr_addr_hp2),
.wr_bytes_hp2(wr_bytes_hp2),
.wr_dv_ddr_hp2(wr_dv_ddr_hp2),
.rd_req_ddr_hp2(rd_req_ddr_hp2),
.rd_addr_hp2(rd_addr_hp2),
.rd_bytes_hp2(rd_bytes_hp2),
.rd_data_ddr_hp2(rd_data_ddr_hp2),
.rd_dv_ddr_hp2(rd_dv_ddr_hp2),
.wr_ack_ddr_hp3(wr_ack_ddr_hp3),
.wr_data_hp3(wr_data_hp3),
.wr_addr_hp3(wr_addr_hp3),
.wr_bytes_hp3(wr_bytes_hp3),
.wr_dv_ddr_hp3(wr_dv_ddr_hp3),
.rd_req_ddr_hp3(rd_req_ddr_hp3),
.rd_addr_hp3(rd_addr_hp3),
.rd_bytes_hp3(rd_bytes_hp3),
.rd_data_ddr_hp3(rd_data_ddr_hp3),
.rd_dv_ddr_hp3(rd_dv_ddr_hp3),
.ddr_wr_ack(ddr_wr_ack1),
.ddr_wr_dv(ddr_wr_dv1),
.ddr_rd_req(ddr_rd_req1),
.ddr_rd_dv(ddr_rd_dv1),
.ddr_rd_qos(ddr_rd_qos1),
.ddr_wr_qos(ddr_wr_qos1),
.ddr_wr_addr(ddr_wr_addr1),
.ddr_wr_data(ddr_wr_data1),
.ddr_wr_bytes(ddr_wr_bytes1),
.ddr_rd_addr(ddr_rd_addr1),
.ddr_rd_data(ddr_rd_data1),
.ddr_rd_bytes(ddr_rd_bytes1)
);
/* FOR OCM_WR */
processing_system7_bfm_v2_0_5_arb_wr_4 ocm_wr_hp(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_hp0),
.qos2(w_qos_hp1),
.qos3(w_qos_hp2),
.qos4(w_qos_hp3),
.prt_dv1(wr_dv_ocm_hp0),
.prt_dv2(wr_dv_ocm_hp1),
.prt_dv3(wr_dv_ocm_hp2),
.prt_dv4(wr_dv_ocm_hp3),
.prt_data1(wr_data_hp0),
.prt_data2(wr_data_hp1),
.prt_data3(wr_data_hp2),
.prt_data4(wr_data_hp3),
.prt_addr1(wr_addr_hp0),
.prt_addr2(wr_addr_hp1),
.prt_addr3(wr_addr_hp2),
.prt_addr4(wr_addr_hp3),
.prt_bytes1(wr_bytes_hp0),
.prt_bytes2(wr_bytes_hp1),
.prt_bytes3(wr_bytes_hp2),
.prt_bytes4(wr_bytes_hp3),
.prt_ack1(wr_ack_ocm_hp0),
.prt_ack2(wr_ack_ocm_hp1),
.prt_ack3(wr_ack_ocm_hp2),
.prt_ack4(wr_ack_ocm_hp3),
.prt_qos(ocm_wr_qos),
.prt_req(ocm_wr_dv),
.prt_data(ocm_wr_data),
.prt_addr(ocm_wr_addr),
.prt_bytes(ocm_wr_bytes),
.prt_ack(ocm_wr_ack)
);
/* FOR OCM_RD */
processing_system7_bfm_v2_0_5_arb_rd_4 ocm_rd_hp(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_hp0),
.qos2(r_qos_hp1),
.qos3(r_qos_hp2),
.qos4(r_qos_hp3),
.prt_req1(rd_req_ocm_hp0),
.prt_req2(rd_req_ocm_hp1),
.prt_req3(rd_req_ocm_hp2),
.prt_req4(rd_req_ocm_hp3),
.prt_data1(rd_data_ocm_hp0),
.prt_data2(rd_data_ocm_hp1),
.prt_data3(rd_data_ocm_hp2),
.prt_data4(rd_data_ocm_hp3),
.prt_addr1(rd_addr_hp0),
.prt_addr2(rd_addr_hp1),
.prt_addr3(rd_addr_hp2),
.prt_addr4(rd_addr_hp3),
.prt_bytes1(rd_bytes_hp0),
.prt_bytes2(rd_bytes_hp1),
.prt_bytes3(rd_bytes_hp2),
.prt_bytes4(rd_bytes_hp3),
.prt_dv1(rd_dv_ocm_hp0),
.prt_dv2(rd_dv_ocm_hp1),
.prt_dv3(rd_dv_ocm_hp2),
.prt_dv4(rd_dv_ocm_hp3),
.prt_qos(ocm_rd_qos),
.prt_req(ocm_rd_req),
.prt_data(ocm_rd_data),
.prt_addr(ocm_rd_addr),
.prt_bytes(ocm_rd_bytes),
.prt_dv(ocm_rd_dv)
);
endmodule |
module processing_system7_bfm_v2_0_5_reg_map();
`include "processing_system7_bfm_v2_0_5_local_params.v"
/* Register definitions */
`include "processing_system7_bfm_v2_0_5_reg_params.v"
parameter mem_size = 32'h2000_0000; ///as the memory is implemented 4 byte wide
parameter xsim_mem_size = 32'h1000_0000; ///as the memory is implemented 4 byte wide 256 MB
`ifdef XSIM_ISIM
reg [data_width-1:0] reg_mem0 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
reg [data_width-1:0] reg_mem1 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
parameter addr_offset_bits = 26;
`else
reg /*sparse*/ [data_width-1:0] reg_mem [0:(mem_size/mem_width)-1]; // 512 MB needed for reg space
parameter addr_offset_bits = 27;
`endif
/* preload reset_values from file */
task automatic pre_load_rst_values;
input dummy;
begin
`include "processing_system7_bfm_v2_0_5_reg_init.v" /* This file has list of set_reset_data() calls to set the reset value for each register*/
end
endtask
/* writes the reset data into the reg memory */
task automatic set_reset_data;
input [addr_width-1:0] address;
input [data_width-1:0] data;
reg [addr_width-1:0] addr;
begin
addr = address >> 2;
`ifdef XSIM_ISIM
case(addr[addr_width-1:addr_offset_bits])
14 : reg_mem0[addr[addr_offset_bits-1:0]] = data;
15 : reg_mem1[addr[addr_offset_bits-1:0]] = data;
endcase
`else
reg_mem[addr[addr_offset_bits-1:0]] = data;
`endif
end
endtask
/* writes the data into the reg memory */
task automatic set_data;
input [addr_width-1:0] addr;
input [data_width-1:0] data;
begin
`ifdef XSIM_ISIM
case(addr[addr_width-1:addr_offset_bits])
6'h0E : reg_mem0[addr[addr_offset_bits-1:0]] = data;
6'h0F : reg_mem1[addr[addr_offset_bits-1:0]] = data;
endcase
`else
reg_mem[addr[addr_offset_bits-1:0]] = data;
`endif
end
endtask
/* get the read data from reg mem */
task automatic get_data;
input [addr_width-1:0] addr;
output [data_width-1:0] data;
begin
`ifdef XSIM_ISIM
case(addr[addr_width-1:addr_offset_bits])
6'h0E : data = reg_mem0[addr[addr_offset_bits-1:0]];
6'h0F : data = reg_mem1[addr[addr_offset_bits-1:0]];
endcase
`else
data = reg_mem[addr[addr_offset_bits-1:0]];
`endif
end
endtask
/* read chunk of registers */
task read_reg_mem;
output[max_burst_bits-1 :0] data;
input [addr_width-1:0] start_addr;
input [max_burst_bytes_width:0] no_of_bytes;
integer i;
reg [addr_width-1:0] addr;
reg [data_width-1:0] temp_rd_data;
reg [max_burst_bits-1:0] temp_data;
integer bytes_left;
begin
addr = start_addr >> shft_addr_bits;
bytes_left = no_of_bytes;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : Reading Register Map starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes );
`endif
/* Get first data ... if unaligned address */
get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits- data_width]);
if(no_of_bytes < mem_width ) begin
repeat(max_burst_bytes - mem_width)
temp_data = temp_data >> 8;
end else begin
bytes_left = bytes_left - mem_width;
addr = addr+1;
/* Got first data */
while (bytes_left > (mem_width-1) ) begin
temp_data = temp_data >> data_width;
get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]);
addr = addr+1;
bytes_left = bytes_left - mem_width;
end
/* Get last valid data in the burst*/
get_data(addr,temp_rd_data);
while(bytes_left > 0) begin
temp_data = temp_data >> 8;
temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0];
temp_rd_data = temp_rd_data >> 8;
bytes_left = bytes_left - 1;
end
/* align to the brst_byte length */
repeat(max_burst_bytes - no_of_bytes)
temp_data = temp_data >> 8;
end
data = temp_data;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : DONE -> Reading Register Map starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data );
`endif
end
endtask
initial
begin
pre_load_rst_values(1);
end
endmodule |
module processing_system7_bfm_v2_0_5_reg_map();
`include "processing_system7_bfm_v2_0_5_local_params.v"
/* Register definitions */
`include "processing_system7_bfm_v2_0_5_reg_params.v"
parameter mem_size = 32'h2000_0000; ///as the memory is implemented 4 byte wide
parameter xsim_mem_size = 32'h1000_0000; ///as the memory is implemented 4 byte wide 256 MB
`ifdef XSIM_ISIM
reg [data_width-1:0] reg_mem0 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
reg [data_width-1:0] reg_mem1 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
parameter addr_offset_bits = 26;
`else
reg /*sparse*/ [data_width-1:0] reg_mem [0:(mem_size/mem_width)-1]; // 512 MB needed for reg space
parameter addr_offset_bits = 27;
`endif
/* preload reset_values from file */
task automatic pre_load_rst_values;
input dummy;
begin
`include "processing_system7_bfm_v2_0_5_reg_init.v" /* This file has list of set_reset_data() calls to set the reset value for each register*/
end
endtask
/* writes the reset data into the reg memory */
task automatic set_reset_data;
input [addr_width-1:0] address;
input [data_width-1:0] data;
reg [addr_width-1:0] addr;
begin
addr = address >> 2;
`ifdef XSIM_ISIM
case(addr[addr_width-1:addr_offset_bits])
14 : reg_mem0[addr[addr_offset_bits-1:0]] = data;
15 : reg_mem1[addr[addr_offset_bits-1:0]] = data;
endcase
`else
reg_mem[addr[addr_offset_bits-1:0]] = data;
`endif
end
endtask
/* writes the data into the reg memory */
task automatic set_data;
input [addr_width-1:0] addr;
input [data_width-1:0] data;
begin
`ifdef XSIM_ISIM
case(addr[addr_width-1:addr_offset_bits])
6'h0E : reg_mem0[addr[addr_offset_bits-1:0]] = data;
6'h0F : reg_mem1[addr[addr_offset_bits-1:0]] = data;
endcase
`else
reg_mem[addr[addr_offset_bits-1:0]] = data;
`endif
end
endtask
/* get the read data from reg mem */
task automatic get_data;
input [addr_width-1:0] addr;
output [data_width-1:0] data;
begin
`ifdef XSIM_ISIM
case(addr[addr_width-1:addr_offset_bits])
6'h0E : data = reg_mem0[addr[addr_offset_bits-1:0]];
6'h0F : data = reg_mem1[addr[addr_offset_bits-1:0]];
endcase
`else
data = reg_mem[addr[addr_offset_bits-1:0]];
`endif
end
endtask
/* read chunk of registers */
task read_reg_mem;
output[max_burst_bits-1 :0] data;
input [addr_width-1:0] start_addr;
input [max_burst_bytes_width:0] no_of_bytes;
integer i;
reg [addr_width-1:0] addr;
reg [data_width-1:0] temp_rd_data;
reg [max_burst_bits-1:0] temp_data;
integer bytes_left;
begin
addr = start_addr >> shft_addr_bits;
bytes_left = no_of_bytes;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : Reading Register Map starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes );
`endif
/* Get first data ... if unaligned address */
get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits- data_width]);
if(no_of_bytes < mem_width ) begin
repeat(max_burst_bytes - mem_width)
temp_data = temp_data >> 8;
end else begin
bytes_left = bytes_left - mem_width;
addr = addr+1;
/* Got first data */
while (bytes_left > (mem_width-1) ) begin
temp_data = temp_data >> data_width;
get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]);
addr = addr+1;
bytes_left = bytes_left - mem_width;
end
/* Get last valid data in the burst*/
get_data(addr,temp_rd_data);
while(bytes_left > 0) begin
temp_data = temp_data >> 8;
temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0];
temp_rd_data = temp_rd_data >> 8;
bytes_left = bytes_left - 1;
end
/* align to the brst_byte length */
repeat(max_burst_bytes - no_of_bytes)
temp_data = temp_data >> 8;
end
data = temp_data;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : DONE -> Reading Register Map starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data );
`endif
end
endtask
initial
begin
pre_load_rst_values(1);
end
endmodule |
module processing_system7_bfm_v2_0_5_ddrc(
rstn,
sw_clk,
/* Goes to port 0 of DDR */
ddr_wr_ack_port0,
ddr_wr_dv_port0,
ddr_rd_req_port0,
ddr_rd_dv_port0,
ddr_wr_addr_port0,
ddr_wr_data_port0,
ddr_wr_bytes_port0,
ddr_rd_addr_port0,
ddr_rd_data_port0,
ddr_rd_bytes_port0,
ddr_wr_qos_port0,
ddr_rd_qos_port0,
/* Goes to port 1 of DDR */
ddr_wr_ack_port1,
ddr_wr_dv_port1,
ddr_rd_req_port1,
ddr_rd_dv_port1,
ddr_wr_addr_port1,
ddr_wr_data_port1,
ddr_wr_bytes_port1,
ddr_rd_addr_port1,
ddr_rd_data_port1,
ddr_rd_bytes_port1,
ddr_wr_qos_port1,
ddr_rd_qos_port1,
/* Goes to port2 of DDR */
ddr_wr_ack_port2,
ddr_wr_dv_port2,
ddr_rd_req_port2,
ddr_rd_dv_port2,
ddr_wr_addr_port2,
ddr_wr_data_port2,
ddr_wr_bytes_port2,
ddr_rd_addr_port2,
ddr_rd_data_port2,
ddr_rd_bytes_port2,
ddr_wr_qos_port2,
ddr_rd_qos_port2,
/* Goes to port3 of DDR */
ddr_wr_ack_port3,
ddr_wr_dv_port3,
ddr_rd_req_port3,
ddr_rd_dv_port3,
ddr_wr_addr_port3,
ddr_wr_data_port3,
ddr_wr_bytes_port3,
ddr_rd_addr_port3,
ddr_rd_data_port3,
ddr_rd_bytes_port3,
ddr_wr_qos_port3,
ddr_rd_qos_port3
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn;
input sw_clk;
output ddr_wr_ack_port0;
input ddr_wr_dv_port0;
input ddr_rd_req_port0;
output ddr_rd_dv_port0;
input[addr_width-1:0] ddr_wr_addr_port0;
input[max_burst_bits-1:0] ddr_wr_data_port0;
input[max_burst_bytes_width:0] ddr_wr_bytes_port0;
input[addr_width-1:0] ddr_rd_addr_port0;
output[max_burst_bits-1:0] ddr_rd_data_port0;
input[max_burst_bytes_width:0] ddr_rd_bytes_port0;
input [axi_qos_width-1:0] ddr_wr_qos_port0;
input [axi_qos_width-1:0] ddr_rd_qos_port0;
output ddr_wr_ack_port1;
input ddr_wr_dv_port1;
input ddr_rd_req_port1;
output ddr_rd_dv_port1;
input[addr_width-1:0] ddr_wr_addr_port1;
input[max_burst_bits-1:0] ddr_wr_data_port1;
input[max_burst_bytes_width:0] ddr_wr_bytes_port1;
input[addr_width-1:0] ddr_rd_addr_port1;
output[max_burst_bits-1:0] ddr_rd_data_port1;
input[max_burst_bytes_width:0] ddr_rd_bytes_port1;
input[axi_qos_width-1:0] ddr_wr_qos_port1;
input[axi_qos_width-1:0] ddr_rd_qos_port1;
output ddr_wr_ack_port2;
input ddr_wr_dv_port2;
input ddr_rd_req_port2;
output ddr_rd_dv_port2;
input[addr_width-1:0] ddr_wr_addr_port2;
input[max_burst_bits-1:0] ddr_wr_data_port2;
input[max_burst_bytes_width:0] ddr_wr_bytes_port2;
input[addr_width-1:0] ddr_rd_addr_port2;
output[max_burst_bits-1:0] ddr_rd_data_port2;
input[max_burst_bytes_width:0] ddr_rd_bytes_port2;
input[axi_qos_width-1:0] ddr_wr_qos_port2;
input[axi_qos_width-1:0] ddr_rd_qos_port2;
output ddr_wr_ack_port3;
input ddr_wr_dv_port3;
input ddr_rd_req_port3;
output ddr_rd_dv_port3;
input[addr_width-1:0] ddr_wr_addr_port3;
input[max_burst_bits-1:0] ddr_wr_data_port3;
input[max_burst_bytes_width:0] ddr_wr_bytes_port3;
input[addr_width-1:0] ddr_rd_addr_port3;
output[max_burst_bits-1:0] ddr_rd_data_port3;
input[max_burst_bytes_width:0] ddr_rd_bytes_port3;
input[axi_qos_width-1:0] ddr_wr_qos_port3;
input[axi_qos_width-1:0] ddr_rd_qos_port3;
wire [axi_qos_width-1:0] wr_qos;
wire wr_req;
wire [max_burst_bits-1:0] wr_data;
wire [addr_width-1:0] wr_addr;
wire [max_burst_bytes_width:0] wr_bytes;
reg wr_ack;
wire [axi_qos_width-1:0] rd_qos;
reg [max_burst_bits-1:0] rd_data;
wire [addr_width-1:0] rd_addr;
wire [max_burst_bytes_width:0] rd_bytes;
reg rd_dv;
wire rd_req;
processing_system7_bfm_v2_0_5_arb_wr_4 ddr_write_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ddr_wr_qos_port0),
.qos2(ddr_wr_qos_port1),
.qos3(ddr_wr_qos_port2),
.qos4(ddr_wr_qos_port3),
.prt_dv1(ddr_wr_dv_port0),
.prt_dv2(ddr_wr_dv_port1),
.prt_dv3(ddr_wr_dv_port2),
.prt_dv4(ddr_wr_dv_port3),
.prt_data1(ddr_wr_data_port0),
.prt_data2(ddr_wr_data_port1),
.prt_data3(ddr_wr_data_port2),
.prt_data4(ddr_wr_data_port3),
.prt_addr1(ddr_wr_addr_port0),
.prt_addr2(ddr_wr_addr_port1),
.prt_addr3(ddr_wr_addr_port2),
.prt_addr4(ddr_wr_addr_port3),
.prt_bytes1(ddr_wr_bytes_port0),
.prt_bytes2(ddr_wr_bytes_port1),
.prt_bytes3(ddr_wr_bytes_port2),
.prt_bytes4(ddr_wr_bytes_port3),
.prt_ack1(ddr_wr_ack_port0),
.prt_ack2(ddr_wr_ack_port1),
.prt_ack3(ddr_wr_ack_port2),
.prt_ack4(ddr_wr_ack_port3),
.prt_qos(wr_qos),
.prt_req(wr_req),
.prt_data(wr_data),
.prt_addr(wr_addr),
.prt_bytes(wr_bytes),
.prt_ack(wr_ack)
);
processing_system7_bfm_v2_0_5_arb_rd_4 ddr_read_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ddr_rd_qos_port0),
.qos2(ddr_rd_qos_port1),
.qos3(ddr_rd_qos_port2),
.qos4(ddr_rd_qos_port3),
.prt_req1(ddr_rd_req_port0),
.prt_req2(ddr_rd_req_port1),
.prt_req3(ddr_rd_req_port2),
.prt_req4(ddr_rd_req_port3),
.prt_data1(ddr_rd_data_port0),
.prt_data2(ddr_rd_data_port1),
.prt_data3(ddr_rd_data_port2),
.prt_data4(ddr_rd_data_port3),
.prt_addr1(ddr_rd_addr_port0),
.prt_addr2(ddr_rd_addr_port1),
.prt_addr3(ddr_rd_addr_port2),
.prt_addr4(ddr_rd_addr_port3),
.prt_bytes1(ddr_rd_bytes_port0),
.prt_bytes2(ddr_rd_bytes_port1),
.prt_bytes3(ddr_rd_bytes_port2),
.prt_bytes4(ddr_rd_bytes_port3),
.prt_dv1(ddr_rd_dv_port0),
.prt_dv2(ddr_rd_dv_port1),
.prt_dv3(ddr_rd_dv_port2),
.prt_dv4(ddr_rd_dv_port3),
.prt_qos(rd_qos),
.prt_req(rd_req),
.prt_data(rd_data),
.prt_addr(rd_addr),
.prt_bytes(rd_bytes),
.prt_dv(rd_dv)
);
processing_system7_bfm_v2_0_5_sparse_mem ddr();
reg [1:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
wr_ack <= 0;
rd_dv <= 0;
state <= 2'd0;
end else begin
case(state)
0:begin
state <= 0;
wr_ack <= 0;
rd_dv <= 0;
if(wr_req) begin
ddr.write_mem(wr_data , wr_addr, wr_bytes);
wr_ack <= 1;
state <= 1;
end
if(rd_req) begin
ddr.read_mem(rd_data,rd_addr, rd_bytes);
rd_dv <= 1;
state <= 1;
end
end
1:begin
wr_ack <= 0;
rd_dv <= 0;
state <= 0;
end
endcase
end /// if
end// always
endmodule |
module processing_system7_bfm_v2_0_5_ddrc(
rstn,
sw_clk,
/* Goes to port 0 of DDR */
ddr_wr_ack_port0,
ddr_wr_dv_port0,
ddr_rd_req_port0,
ddr_rd_dv_port0,
ddr_wr_addr_port0,
ddr_wr_data_port0,
ddr_wr_bytes_port0,
ddr_rd_addr_port0,
ddr_rd_data_port0,
ddr_rd_bytes_port0,
ddr_wr_qos_port0,
ddr_rd_qos_port0,
/* Goes to port 1 of DDR */
ddr_wr_ack_port1,
ddr_wr_dv_port1,
ddr_rd_req_port1,
ddr_rd_dv_port1,
ddr_wr_addr_port1,
ddr_wr_data_port1,
ddr_wr_bytes_port1,
ddr_rd_addr_port1,
ddr_rd_data_port1,
ddr_rd_bytes_port1,
ddr_wr_qos_port1,
ddr_rd_qos_port1,
/* Goes to port2 of DDR */
ddr_wr_ack_port2,
ddr_wr_dv_port2,
ddr_rd_req_port2,
ddr_rd_dv_port2,
ddr_wr_addr_port2,
ddr_wr_data_port2,
ddr_wr_bytes_port2,
ddr_rd_addr_port2,
ddr_rd_data_port2,
ddr_rd_bytes_port2,
ddr_wr_qos_port2,
ddr_rd_qos_port2,
/* Goes to port3 of DDR */
ddr_wr_ack_port3,
ddr_wr_dv_port3,
ddr_rd_req_port3,
ddr_rd_dv_port3,
ddr_wr_addr_port3,
ddr_wr_data_port3,
ddr_wr_bytes_port3,
ddr_rd_addr_port3,
ddr_rd_data_port3,
ddr_rd_bytes_port3,
ddr_wr_qos_port3,
ddr_rd_qos_port3
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn;
input sw_clk;
output ddr_wr_ack_port0;
input ddr_wr_dv_port0;
input ddr_rd_req_port0;
output ddr_rd_dv_port0;
input[addr_width-1:0] ddr_wr_addr_port0;
input[max_burst_bits-1:0] ddr_wr_data_port0;
input[max_burst_bytes_width:0] ddr_wr_bytes_port0;
input[addr_width-1:0] ddr_rd_addr_port0;
output[max_burst_bits-1:0] ddr_rd_data_port0;
input[max_burst_bytes_width:0] ddr_rd_bytes_port0;
input [axi_qos_width-1:0] ddr_wr_qos_port0;
input [axi_qos_width-1:0] ddr_rd_qos_port0;
output ddr_wr_ack_port1;
input ddr_wr_dv_port1;
input ddr_rd_req_port1;
output ddr_rd_dv_port1;
input[addr_width-1:0] ddr_wr_addr_port1;
input[max_burst_bits-1:0] ddr_wr_data_port1;
input[max_burst_bytes_width:0] ddr_wr_bytes_port1;
input[addr_width-1:0] ddr_rd_addr_port1;
output[max_burst_bits-1:0] ddr_rd_data_port1;
input[max_burst_bytes_width:0] ddr_rd_bytes_port1;
input[axi_qos_width-1:0] ddr_wr_qos_port1;
input[axi_qos_width-1:0] ddr_rd_qos_port1;
output ddr_wr_ack_port2;
input ddr_wr_dv_port2;
input ddr_rd_req_port2;
output ddr_rd_dv_port2;
input[addr_width-1:0] ddr_wr_addr_port2;
input[max_burst_bits-1:0] ddr_wr_data_port2;
input[max_burst_bytes_width:0] ddr_wr_bytes_port2;
input[addr_width-1:0] ddr_rd_addr_port2;
output[max_burst_bits-1:0] ddr_rd_data_port2;
input[max_burst_bytes_width:0] ddr_rd_bytes_port2;
input[axi_qos_width-1:0] ddr_wr_qos_port2;
input[axi_qos_width-1:0] ddr_rd_qos_port2;
output ddr_wr_ack_port3;
input ddr_wr_dv_port3;
input ddr_rd_req_port3;
output ddr_rd_dv_port3;
input[addr_width-1:0] ddr_wr_addr_port3;
input[max_burst_bits-1:0] ddr_wr_data_port3;
input[max_burst_bytes_width:0] ddr_wr_bytes_port3;
input[addr_width-1:0] ddr_rd_addr_port3;
output[max_burst_bits-1:0] ddr_rd_data_port3;
input[max_burst_bytes_width:0] ddr_rd_bytes_port3;
input[axi_qos_width-1:0] ddr_wr_qos_port3;
input[axi_qos_width-1:0] ddr_rd_qos_port3;
wire [axi_qos_width-1:0] wr_qos;
wire wr_req;
wire [max_burst_bits-1:0] wr_data;
wire [addr_width-1:0] wr_addr;
wire [max_burst_bytes_width:0] wr_bytes;
reg wr_ack;
wire [axi_qos_width-1:0] rd_qos;
reg [max_burst_bits-1:0] rd_data;
wire [addr_width-1:0] rd_addr;
wire [max_burst_bytes_width:0] rd_bytes;
reg rd_dv;
wire rd_req;
processing_system7_bfm_v2_0_5_arb_wr_4 ddr_write_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ddr_wr_qos_port0),
.qos2(ddr_wr_qos_port1),
.qos3(ddr_wr_qos_port2),
.qos4(ddr_wr_qos_port3),
.prt_dv1(ddr_wr_dv_port0),
.prt_dv2(ddr_wr_dv_port1),
.prt_dv3(ddr_wr_dv_port2),
.prt_dv4(ddr_wr_dv_port3),
.prt_data1(ddr_wr_data_port0),
.prt_data2(ddr_wr_data_port1),
.prt_data3(ddr_wr_data_port2),
.prt_data4(ddr_wr_data_port3),
.prt_addr1(ddr_wr_addr_port0),
.prt_addr2(ddr_wr_addr_port1),
.prt_addr3(ddr_wr_addr_port2),
.prt_addr4(ddr_wr_addr_port3),
.prt_bytes1(ddr_wr_bytes_port0),
.prt_bytes2(ddr_wr_bytes_port1),
.prt_bytes3(ddr_wr_bytes_port2),
.prt_bytes4(ddr_wr_bytes_port3),
.prt_ack1(ddr_wr_ack_port0),
.prt_ack2(ddr_wr_ack_port1),
.prt_ack3(ddr_wr_ack_port2),
.prt_ack4(ddr_wr_ack_port3),
.prt_qos(wr_qos),
.prt_req(wr_req),
.prt_data(wr_data),
.prt_addr(wr_addr),
.prt_bytes(wr_bytes),
.prt_ack(wr_ack)
);
processing_system7_bfm_v2_0_5_arb_rd_4 ddr_read_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ddr_rd_qos_port0),
.qos2(ddr_rd_qos_port1),
.qos3(ddr_rd_qos_port2),
.qos4(ddr_rd_qos_port3),
.prt_req1(ddr_rd_req_port0),
.prt_req2(ddr_rd_req_port1),
.prt_req3(ddr_rd_req_port2),
.prt_req4(ddr_rd_req_port3),
.prt_data1(ddr_rd_data_port0),
.prt_data2(ddr_rd_data_port1),
.prt_data3(ddr_rd_data_port2),
.prt_data4(ddr_rd_data_port3),
.prt_addr1(ddr_rd_addr_port0),
.prt_addr2(ddr_rd_addr_port1),
.prt_addr3(ddr_rd_addr_port2),
.prt_addr4(ddr_rd_addr_port3),
.prt_bytes1(ddr_rd_bytes_port0),
.prt_bytes2(ddr_rd_bytes_port1),
.prt_bytes3(ddr_rd_bytes_port2),
.prt_bytes4(ddr_rd_bytes_port3),
.prt_dv1(ddr_rd_dv_port0),
.prt_dv2(ddr_rd_dv_port1),
.prt_dv3(ddr_rd_dv_port2),
.prt_dv4(ddr_rd_dv_port3),
.prt_qos(rd_qos),
.prt_req(rd_req),
.prt_data(rd_data),
.prt_addr(rd_addr),
.prt_bytes(rd_bytes),
.prt_dv(rd_dv)
);
processing_system7_bfm_v2_0_5_sparse_mem ddr();
reg [1:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
wr_ack <= 0;
rd_dv <= 0;
state <= 2'd0;
end else begin
case(state)
0:begin
state <= 0;
wr_ack <= 0;
rd_dv <= 0;
if(wr_req) begin
ddr.write_mem(wr_data , wr_addr, wr_bytes);
wr_ack <= 1;
state <= 1;
end
if(rd_req) begin
ddr.read_mem(rd_data,rd_addr, rd_bytes);
rd_dv <= 1;
state <= 1;
end
end
1:begin
wr_ack <= 0;
rd_dv <= 0;
state <= 0;
end
endcase
end /// if
end// always
endmodule |
module processing_system7_bfm_v2_0_5_ddrc(
rstn,
sw_clk,
/* Goes to port 0 of DDR */
ddr_wr_ack_port0,
ddr_wr_dv_port0,
ddr_rd_req_port0,
ddr_rd_dv_port0,
ddr_wr_addr_port0,
ddr_wr_data_port0,
ddr_wr_bytes_port0,
ddr_rd_addr_port0,
ddr_rd_data_port0,
ddr_rd_bytes_port0,
ddr_wr_qos_port0,
ddr_rd_qos_port0,
/* Goes to port 1 of DDR */
ddr_wr_ack_port1,
ddr_wr_dv_port1,
ddr_rd_req_port1,
ddr_rd_dv_port1,
ddr_wr_addr_port1,
ddr_wr_data_port1,
ddr_wr_bytes_port1,
ddr_rd_addr_port1,
ddr_rd_data_port1,
ddr_rd_bytes_port1,
ddr_wr_qos_port1,
ddr_rd_qos_port1,
/* Goes to port2 of DDR */
ddr_wr_ack_port2,
ddr_wr_dv_port2,
ddr_rd_req_port2,
ddr_rd_dv_port2,
ddr_wr_addr_port2,
ddr_wr_data_port2,
ddr_wr_bytes_port2,
ddr_rd_addr_port2,
ddr_rd_data_port2,
ddr_rd_bytes_port2,
ddr_wr_qos_port2,
ddr_rd_qos_port2,
/* Goes to port3 of DDR */
ddr_wr_ack_port3,
ddr_wr_dv_port3,
ddr_rd_req_port3,
ddr_rd_dv_port3,
ddr_wr_addr_port3,
ddr_wr_data_port3,
ddr_wr_bytes_port3,
ddr_rd_addr_port3,
ddr_rd_data_port3,
ddr_rd_bytes_port3,
ddr_wr_qos_port3,
ddr_rd_qos_port3
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn;
input sw_clk;
output ddr_wr_ack_port0;
input ddr_wr_dv_port0;
input ddr_rd_req_port0;
output ddr_rd_dv_port0;
input[addr_width-1:0] ddr_wr_addr_port0;
input[max_burst_bits-1:0] ddr_wr_data_port0;
input[max_burst_bytes_width:0] ddr_wr_bytes_port0;
input[addr_width-1:0] ddr_rd_addr_port0;
output[max_burst_bits-1:0] ddr_rd_data_port0;
input[max_burst_bytes_width:0] ddr_rd_bytes_port0;
input [axi_qos_width-1:0] ddr_wr_qos_port0;
input [axi_qos_width-1:0] ddr_rd_qos_port0;
output ddr_wr_ack_port1;
input ddr_wr_dv_port1;
input ddr_rd_req_port1;
output ddr_rd_dv_port1;
input[addr_width-1:0] ddr_wr_addr_port1;
input[max_burst_bits-1:0] ddr_wr_data_port1;
input[max_burst_bytes_width:0] ddr_wr_bytes_port1;
input[addr_width-1:0] ddr_rd_addr_port1;
output[max_burst_bits-1:0] ddr_rd_data_port1;
input[max_burst_bytes_width:0] ddr_rd_bytes_port1;
input[axi_qos_width-1:0] ddr_wr_qos_port1;
input[axi_qos_width-1:0] ddr_rd_qos_port1;
output ddr_wr_ack_port2;
input ddr_wr_dv_port2;
input ddr_rd_req_port2;
output ddr_rd_dv_port2;
input[addr_width-1:0] ddr_wr_addr_port2;
input[max_burst_bits-1:0] ddr_wr_data_port2;
input[max_burst_bytes_width:0] ddr_wr_bytes_port2;
input[addr_width-1:0] ddr_rd_addr_port2;
output[max_burst_bits-1:0] ddr_rd_data_port2;
input[max_burst_bytes_width:0] ddr_rd_bytes_port2;
input[axi_qos_width-1:0] ddr_wr_qos_port2;
input[axi_qos_width-1:0] ddr_rd_qos_port2;
output ddr_wr_ack_port3;
input ddr_wr_dv_port3;
input ddr_rd_req_port3;
output ddr_rd_dv_port3;
input[addr_width-1:0] ddr_wr_addr_port3;
input[max_burst_bits-1:0] ddr_wr_data_port3;
input[max_burst_bytes_width:0] ddr_wr_bytes_port3;
input[addr_width-1:0] ddr_rd_addr_port3;
output[max_burst_bits-1:0] ddr_rd_data_port3;
input[max_burst_bytes_width:0] ddr_rd_bytes_port3;
input[axi_qos_width-1:0] ddr_wr_qos_port3;
input[axi_qos_width-1:0] ddr_rd_qos_port3;
wire [axi_qos_width-1:0] wr_qos;
wire wr_req;
wire [max_burst_bits-1:0] wr_data;
wire [addr_width-1:0] wr_addr;
wire [max_burst_bytes_width:0] wr_bytes;
reg wr_ack;
wire [axi_qos_width-1:0] rd_qos;
reg [max_burst_bits-1:0] rd_data;
wire [addr_width-1:0] rd_addr;
wire [max_burst_bytes_width:0] rd_bytes;
reg rd_dv;
wire rd_req;
processing_system7_bfm_v2_0_5_arb_wr_4 ddr_write_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ddr_wr_qos_port0),
.qos2(ddr_wr_qos_port1),
.qos3(ddr_wr_qos_port2),
.qos4(ddr_wr_qos_port3),
.prt_dv1(ddr_wr_dv_port0),
.prt_dv2(ddr_wr_dv_port1),
.prt_dv3(ddr_wr_dv_port2),
.prt_dv4(ddr_wr_dv_port3),
.prt_data1(ddr_wr_data_port0),
.prt_data2(ddr_wr_data_port1),
.prt_data3(ddr_wr_data_port2),
.prt_data4(ddr_wr_data_port3),
.prt_addr1(ddr_wr_addr_port0),
.prt_addr2(ddr_wr_addr_port1),
.prt_addr3(ddr_wr_addr_port2),
.prt_addr4(ddr_wr_addr_port3),
.prt_bytes1(ddr_wr_bytes_port0),
.prt_bytes2(ddr_wr_bytes_port1),
.prt_bytes3(ddr_wr_bytes_port2),
.prt_bytes4(ddr_wr_bytes_port3),
.prt_ack1(ddr_wr_ack_port0),
.prt_ack2(ddr_wr_ack_port1),
.prt_ack3(ddr_wr_ack_port2),
.prt_ack4(ddr_wr_ack_port3),
.prt_qos(wr_qos),
.prt_req(wr_req),
.prt_data(wr_data),
.prt_addr(wr_addr),
.prt_bytes(wr_bytes),
.prt_ack(wr_ack)
);
processing_system7_bfm_v2_0_5_arb_rd_4 ddr_read_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ddr_rd_qos_port0),
.qos2(ddr_rd_qos_port1),
.qos3(ddr_rd_qos_port2),
.qos4(ddr_rd_qos_port3),
.prt_req1(ddr_rd_req_port0),
.prt_req2(ddr_rd_req_port1),
.prt_req3(ddr_rd_req_port2),
.prt_req4(ddr_rd_req_port3),
.prt_data1(ddr_rd_data_port0),
.prt_data2(ddr_rd_data_port1),
.prt_data3(ddr_rd_data_port2),
.prt_data4(ddr_rd_data_port3),
.prt_addr1(ddr_rd_addr_port0),
.prt_addr2(ddr_rd_addr_port1),
.prt_addr3(ddr_rd_addr_port2),
.prt_addr4(ddr_rd_addr_port3),
.prt_bytes1(ddr_rd_bytes_port0),
.prt_bytes2(ddr_rd_bytes_port1),
.prt_bytes3(ddr_rd_bytes_port2),
.prt_bytes4(ddr_rd_bytes_port3),
.prt_dv1(ddr_rd_dv_port0),
.prt_dv2(ddr_rd_dv_port1),
.prt_dv3(ddr_rd_dv_port2),
.prt_dv4(ddr_rd_dv_port3),
.prt_qos(rd_qos),
.prt_req(rd_req),
.prt_data(rd_data),
.prt_addr(rd_addr),
.prt_bytes(rd_bytes),
.prt_dv(rd_dv)
);
processing_system7_bfm_v2_0_5_sparse_mem ddr();
reg [1:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
wr_ack <= 0;
rd_dv <= 0;
state <= 2'd0;
end else begin
case(state)
0:begin
state <= 0;
wr_ack <= 0;
rd_dv <= 0;
if(wr_req) begin
ddr.write_mem(wr_data , wr_addr, wr_bytes);
wr_ack <= 1;
state <= 1;
end
if(rd_req) begin
ddr.read_mem(rd_data,rd_addr, rd_bytes);
rd_dv <= 1;
state <= 1;
end
end
1:begin
wr_ack <= 0;
rd_dv <= 0;
state <= 0;
end
endcase
end /// if
end// always
endmodule |
module processing_system7_bfm_v2_0_5_ddrc(
rstn,
sw_clk,
/* Goes to port 0 of DDR */
ddr_wr_ack_port0,
ddr_wr_dv_port0,
ddr_rd_req_port0,
ddr_rd_dv_port0,
ddr_wr_addr_port0,
ddr_wr_data_port0,
ddr_wr_bytes_port0,
ddr_rd_addr_port0,
ddr_rd_data_port0,
ddr_rd_bytes_port0,
ddr_wr_qos_port0,
ddr_rd_qos_port0,
/* Goes to port 1 of DDR */
ddr_wr_ack_port1,
ddr_wr_dv_port1,
ddr_rd_req_port1,
ddr_rd_dv_port1,
ddr_wr_addr_port1,
ddr_wr_data_port1,
ddr_wr_bytes_port1,
ddr_rd_addr_port1,
ddr_rd_data_port1,
ddr_rd_bytes_port1,
ddr_wr_qos_port1,
ddr_rd_qos_port1,
/* Goes to port2 of DDR */
ddr_wr_ack_port2,
ddr_wr_dv_port2,
ddr_rd_req_port2,
ddr_rd_dv_port2,
ddr_wr_addr_port2,
ddr_wr_data_port2,
ddr_wr_bytes_port2,
ddr_rd_addr_port2,
ddr_rd_data_port2,
ddr_rd_bytes_port2,
ddr_wr_qos_port2,
ddr_rd_qos_port2,
/* Goes to port3 of DDR */
ddr_wr_ack_port3,
ddr_wr_dv_port3,
ddr_rd_req_port3,
ddr_rd_dv_port3,
ddr_wr_addr_port3,
ddr_wr_data_port3,
ddr_wr_bytes_port3,
ddr_rd_addr_port3,
ddr_rd_data_port3,
ddr_rd_bytes_port3,
ddr_wr_qos_port3,
ddr_rd_qos_port3
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn;
input sw_clk;
output ddr_wr_ack_port0;
input ddr_wr_dv_port0;
input ddr_rd_req_port0;
output ddr_rd_dv_port0;
input[addr_width-1:0] ddr_wr_addr_port0;
input[max_burst_bits-1:0] ddr_wr_data_port0;
input[max_burst_bytes_width:0] ddr_wr_bytes_port0;
input[addr_width-1:0] ddr_rd_addr_port0;
output[max_burst_bits-1:0] ddr_rd_data_port0;
input[max_burst_bytes_width:0] ddr_rd_bytes_port0;
input [axi_qos_width-1:0] ddr_wr_qos_port0;
input [axi_qos_width-1:0] ddr_rd_qos_port0;
output ddr_wr_ack_port1;
input ddr_wr_dv_port1;
input ddr_rd_req_port1;
output ddr_rd_dv_port1;
input[addr_width-1:0] ddr_wr_addr_port1;
input[max_burst_bits-1:0] ddr_wr_data_port1;
input[max_burst_bytes_width:0] ddr_wr_bytes_port1;
input[addr_width-1:0] ddr_rd_addr_port1;
output[max_burst_bits-1:0] ddr_rd_data_port1;
input[max_burst_bytes_width:0] ddr_rd_bytes_port1;
input[axi_qos_width-1:0] ddr_wr_qos_port1;
input[axi_qos_width-1:0] ddr_rd_qos_port1;
output ddr_wr_ack_port2;
input ddr_wr_dv_port2;
input ddr_rd_req_port2;
output ddr_rd_dv_port2;
input[addr_width-1:0] ddr_wr_addr_port2;
input[max_burst_bits-1:0] ddr_wr_data_port2;
input[max_burst_bytes_width:0] ddr_wr_bytes_port2;
input[addr_width-1:0] ddr_rd_addr_port2;
output[max_burst_bits-1:0] ddr_rd_data_port2;
input[max_burst_bytes_width:0] ddr_rd_bytes_port2;
input[axi_qos_width-1:0] ddr_wr_qos_port2;
input[axi_qos_width-1:0] ddr_rd_qos_port2;
output ddr_wr_ack_port3;
input ddr_wr_dv_port3;
input ddr_rd_req_port3;
output ddr_rd_dv_port3;
input[addr_width-1:0] ddr_wr_addr_port3;
input[max_burst_bits-1:0] ddr_wr_data_port3;
input[max_burst_bytes_width:0] ddr_wr_bytes_port3;
input[addr_width-1:0] ddr_rd_addr_port3;
output[max_burst_bits-1:0] ddr_rd_data_port3;
input[max_burst_bytes_width:0] ddr_rd_bytes_port3;
input[axi_qos_width-1:0] ddr_wr_qos_port3;
input[axi_qos_width-1:0] ddr_rd_qos_port3;
wire [axi_qos_width-1:0] wr_qos;
wire wr_req;
wire [max_burst_bits-1:0] wr_data;
wire [addr_width-1:0] wr_addr;
wire [max_burst_bytes_width:0] wr_bytes;
reg wr_ack;
wire [axi_qos_width-1:0] rd_qos;
reg [max_burst_bits-1:0] rd_data;
wire [addr_width-1:0] rd_addr;
wire [max_burst_bytes_width:0] rd_bytes;
reg rd_dv;
wire rd_req;
processing_system7_bfm_v2_0_5_arb_wr_4 ddr_write_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ddr_wr_qos_port0),
.qos2(ddr_wr_qos_port1),
.qos3(ddr_wr_qos_port2),
.qos4(ddr_wr_qos_port3),
.prt_dv1(ddr_wr_dv_port0),
.prt_dv2(ddr_wr_dv_port1),
.prt_dv3(ddr_wr_dv_port2),
.prt_dv4(ddr_wr_dv_port3),
.prt_data1(ddr_wr_data_port0),
.prt_data2(ddr_wr_data_port1),
.prt_data3(ddr_wr_data_port2),
.prt_data4(ddr_wr_data_port3),
.prt_addr1(ddr_wr_addr_port0),
.prt_addr2(ddr_wr_addr_port1),
.prt_addr3(ddr_wr_addr_port2),
.prt_addr4(ddr_wr_addr_port3),
.prt_bytes1(ddr_wr_bytes_port0),
.prt_bytes2(ddr_wr_bytes_port1),
.prt_bytes3(ddr_wr_bytes_port2),
.prt_bytes4(ddr_wr_bytes_port3),
.prt_ack1(ddr_wr_ack_port0),
.prt_ack2(ddr_wr_ack_port1),
.prt_ack3(ddr_wr_ack_port2),
.prt_ack4(ddr_wr_ack_port3),
.prt_qos(wr_qos),
.prt_req(wr_req),
.prt_data(wr_data),
.prt_addr(wr_addr),
.prt_bytes(wr_bytes),
.prt_ack(wr_ack)
);
processing_system7_bfm_v2_0_5_arb_rd_4 ddr_read_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ddr_rd_qos_port0),
.qos2(ddr_rd_qos_port1),
.qos3(ddr_rd_qos_port2),
.qos4(ddr_rd_qos_port3),
.prt_req1(ddr_rd_req_port0),
.prt_req2(ddr_rd_req_port1),
.prt_req3(ddr_rd_req_port2),
.prt_req4(ddr_rd_req_port3),
.prt_data1(ddr_rd_data_port0),
.prt_data2(ddr_rd_data_port1),
.prt_data3(ddr_rd_data_port2),
.prt_data4(ddr_rd_data_port3),
.prt_addr1(ddr_rd_addr_port0),
.prt_addr2(ddr_rd_addr_port1),
.prt_addr3(ddr_rd_addr_port2),
.prt_addr4(ddr_rd_addr_port3),
.prt_bytes1(ddr_rd_bytes_port0),
.prt_bytes2(ddr_rd_bytes_port1),
.prt_bytes3(ddr_rd_bytes_port2),
.prt_bytes4(ddr_rd_bytes_port3),
.prt_dv1(ddr_rd_dv_port0),
.prt_dv2(ddr_rd_dv_port1),
.prt_dv3(ddr_rd_dv_port2),
.prt_dv4(ddr_rd_dv_port3),
.prt_qos(rd_qos),
.prt_req(rd_req),
.prt_data(rd_data),
.prt_addr(rd_addr),
.prt_bytes(rd_bytes),
.prt_dv(rd_dv)
);
processing_system7_bfm_v2_0_5_sparse_mem ddr();
reg [1:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
wr_ack <= 0;
rd_dv <= 0;
state <= 2'd0;
end else begin
case(state)
0:begin
state <= 0;
wr_ack <= 0;
rd_dv <= 0;
if(wr_req) begin
ddr.write_mem(wr_data , wr_addr, wr_bytes);
wr_ack <= 1;
state <= 1;
end
if(rd_req) begin
ddr.read_mem(rd_data,rd_addr, rd_bytes);
rd_dv <= 1;
state <= 1;
end
end
1:begin
wr_ack <= 0;
rd_dv <= 0;
state <= 0;
end
endcase
end /// if
end// always
endmodule |
module processing_system7_bfm_v2_0_5_arb_rd(
rstn,
sw_clk,
qos1,
qos2,
prt_req1,
prt_req2,
prt_bytes1,
prt_bytes2,
prt_addr1,
prt_addr2,
prt_data1,
prt_data2,
prt_dv1,
prt_dv2,
prt_req,
prt_qos,
prt_addr,
prt_bytes,
prt_data,
prt_dv
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2;
input prt_req1, prt_req2;
input [addr_width-1:0] prt_addr1, prt_addr2;
input [max_burst_bytes_width:0] prt_bytes1, prt_bytes2;
output reg prt_dv1, prt_dv2;
output reg [max_burst_bits-1:0] prt_data1,prt_data2;
output reg prt_req;
output reg [axi_qos_width-1:0] prt_qos;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
input [max_burst_bits-1:0] prt_data;
input prt_dv;
parameter wait_req = 2'b00, serv_req1 = 2'b01, serv_req2 = 2'b10,wait_dv_low = 2'b11;
reg [1:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_req = 0;
if(prt_req1 && !prt_req2) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(!prt_req1 && prt_req2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req1 && prt_req2) begin
if(qos1 > qos2) begin
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else if(qos1 < qos2) begin
prt_req = 1;
prt_addr = prt_addr2;
prt_qos = qos2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req1:begin
state = serv_req1;
prt_dv2 = 1'b0;
if(prt_dv) begin
prt_dv1 = 1'b1;
prt_data1 = prt_data;
prt_req = 0;
if(prt_req2) begin
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
state = wait_dv_low;
//state = wait_req;
end
end
end
serv_req2:begin
state = serv_req2;
prt_dv1 = 1'b0;
if(prt_dv) begin
prt_dv2 = 1'b1;
prt_data2 = prt_data;
prt_req = 0;
if(prt_req1) begin
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else begin
state = wait_dv_low;
//state = wait_req;
end
end
end
wait_dv_low:begin
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
state = wait_dv_low;
if(!prt_dv)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule |
module axi_crossbar_v2_1_arbiter_resp #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_S = 4, // Number of requesting Slave ports = [2:16]
parameter integer C_NUM_S_LOG = 2, // Log2(C_NUM_S)
parameter integer C_GRANT_ENC = 0, // Enable encoded grant output
parameter integer C_GRANT_HOT = 1 // Enable 1-hot grant output
)
(
// Global Inputs
input wire ACLK,
input wire ARESET,
// Slave Ports
input wire [C_NUM_S-1:0] S_VALID, // Request from each slave
output wire [C_NUM_S-1:0] S_READY, // Grant response to each slave
// Master Ports
output wire [C_NUM_S_LOG-1:0] M_GRANT_ENC, // Granted slave index (encoded)
output wire [C_NUM_S-1:0] M_GRANT_HOT, // Granted slave index (1-hot)
output wire M_VALID, // Grant event
input wire M_READY
);
// Generates a binary coded from onehotone encoded
function [4:0] f_hot2enc
(
input [16:0] one_hot
);
begin
f_hot2enc[0] = |(one_hot & 17'b01010101010101010);
f_hot2enc[1] = |(one_hot & 17'b01100110011001100);
f_hot2enc[2] = |(one_hot & 17'b01111000011110000);
f_hot2enc[3] = |(one_hot & 17'b01111111100000000);
f_hot2enc[4] = |(one_hot & 17'b10000000000000000);
end
endfunction
(* use_clock_enable = "yes" *)
reg [C_NUM_S-1:0] chosen;
wire [C_NUM_S-1:0] grant_hot;
wire master_selected;
wire active_master;
wire need_arbitration;
wire m_valid_i;
wire [C_NUM_S-1:0] s_ready_i;
wire access_done;
reg [C_NUM_S-1:0] last_rr_hot;
wire [C_NUM_S-1:0] valid_rr;
reg [C_NUM_S-1:0] next_rr_hot;
reg [C_NUM_S*C_NUM_S-1:0] carry_rr;
reg [C_NUM_S*C_NUM_S-1:0] mask_rr;
integer i;
integer j;
integer n;
/////////////////////////////////////////////////////////////////////////////
//
// Implementation of the arbiter outputs independant of arbitration
//
/////////////////////////////////////////////////////////////////////////////
// Mask the current requests with the chosen master
assign grant_hot = chosen & S_VALID;
// See if we have a selected master
assign master_selected = |grant_hot[0+:C_NUM_S];
// See if we have current requests
assign active_master = |S_VALID;
// Access is completed
assign access_done = m_valid_i & M_READY;
// Need to handle if we drive S_ready combinatorial and without an IDLE state
// Drive S_READY on the master who has been chosen when we get a M_READY
assign s_ready_i = {C_NUM_S{M_READY}} & grant_hot[0+:C_NUM_S];
// Drive M_VALID if we have a selected master
assign m_valid_i = master_selected;
// If we have request and not a selected master, we need to arbitrate a new chosen
assign need_arbitration = (active_master & ~master_selected) | access_done;
// need internal signals of the output signals
assign M_VALID = m_valid_i;
assign S_READY = s_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Assign conditional onehot target output signal.
assign M_GRANT_HOT = (C_GRANT_HOT == 1) ? grant_hot[0+:C_NUM_S] : {C_NUM_S{1'b0}};
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded target output signal.
assign M_GRANT_ENC = (C_GRANT_ENC == 1) ? f_hot2enc(grant_hot) : {C_NUM_S_LOG{1'b0}};
/////////////////////////////////////////////////////////////////////////////
// Select a new chosen when we need to arbitrate
// If we don't have a new chosen, keep the old one since it's a good chance
// that it will do another request
always @(posedge ACLK)
begin
if (ARESET) begin
chosen <= {C_NUM_S{1'b0}};
last_rr_hot <= {1'b1, {C_NUM_S-1{1'b0}}};
end else if (need_arbitration) begin
chosen <= next_rr_hot;
if (|next_rr_hot) last_rr_hot <= next_rr_hot;
end
end
assign valid_rr = S_VALID;
/////////////////////////////////////////////////////////////////////////////
// Round-robin arbiter
// Selects next request to grant from among inputs with PRIO = 0, if any.
/////////////////////////////////////////////////////////////////////////////
always @ * begin
next_rr_hot = 0;
for (i=0;i<C_NUM_S;i=i+1) begin
n = (i>0) ? (i-1) : (C_NUM_S-1);
carry_rr[i*C_NUM_S] = last_rr_hot[n];
mask_rr[i*C_NUM_S] = ~valid_rr[n];
for (j=1;j<C_NUM_S;j=j+1) begin
n = (i-j > 0) ? (i-j-1) : (C_NUM_S+i-j-1);
carry_rr[i*C_NUM_S+j] = carry_rr[i*C_NUM_S+j-1] | (last_rr_hot[n] & mask_rr[i*C_NUM_S+j-1]);
if (j < C_NUM_S-1) begin
mask_rr[i*C_NUM_S+j] = mask_rr[i*C_NUM_S+j-1] & ~valid_rr[n];
end
end
next_rr_hot[i] = valid_rr[i] & carry_rr[(i+1)*C_NUM_S-1];
end
end
endmodule |
module axi_crossbar_v2_1_arbiter_resp #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_S = 4, // Number of requesting Slave ports = [2:16]
parameter integer C_NUM_S_LOG = 2, // Log2(C_NUM_S)
parameter integer C_GRANT_ENC = 0, // Enable encoded grant output
parameter integer C_GRANT_HOT = 1 // Enable 1-hot grant output
)
(
// Global Inputs
input wire ACLK,
input wire ARESET,
// Slave Ports
input wire [C_NUM_S-1:0] S_VALID, // Request from each slave
output wire [C_NUM_S-1:0] S_READY, // Grant response to each slave
// Master Ports
output wire [C_NUM_S_LOG-1:0] M_GRANT_ENC, // Granted slave index (encoded)
output wire [C_NUM_S-1:0] M_GRANT_HOT, // Granted slave index (1-hot)
output wire M_VALID, // Grant event
input wire M_READY
);
// Generates a binary coded from onehotone encoded
function [4:0] f_hot2enc
(
input [16:0] one_hot
);
begin
f_hot2enc[0] = |(one_hot & 17'b01010101010101010);
f_hot2enc[1] = |(one_hot & 17'b01100110011001100);
f_hot2enc[2] = |(one_hot & 17'b01111000011110000);
f_hot2enc[3] = |(one_hot & 17'b01111111100000000);
f_hot2enc[4] = |(one_hot & 17'b10000000000000000);
end
endfunction
(* use_clock_enable = "yes" *)
reg [C_NUM_S-1:0] chosen;
wire [C_NUM_S-1:0] grant_hot;
wire master_selected;
wire active_master;
wire need_arbitration;
wire m_valid_i;
wire [C_NUM_S-1:0] s_ready_i;
wire access_done;
reg [C_NUM_S-1:0] last_rr_hot;
wire [C_NUM_S-1:0] valid_rr;
reg [C_NUM_S-1:0] next_rr_hot;
reg [C_NUM_S*C_NUM_S-1:0] carry_rr;
reg [C_NUM_S*C_NUM_S-1:0] mask_rr;
integer i;
integer j;
integer n;
/////////////////////////////////////////////////////////////////////////////
//
// Implementation of the arbiter outputs independant of arbitration
//
/////////////////////////////////////////////////////////////////////////////
// Mask the current requests with the chosen master
assign grant_hot = chosen & S_VALID;
// See if we have a selected master
assign master_selected = |grant_hot[0+:C_NUM_S];
// See if we have current requests
assign active_master = |S_VALID;
// Access is completed
assign access_done = m_valid_i & M_READY;
// Need to handle if we drive S_ready combinatorial and without an IDLE state
// Drive S_READY on the master who has been chosen when we get a M_READY
assign s_ready_i = {C_NUM_S{M_READY}} & grant_hot[0+:C_NUM_S];
// Drive M_VALID if we have a selected master
assign m_valid_i = master_selected;
// If we have request and not a selected master, we need to arbitrate a new chosen
assign need_arbitration = (active_master & ~master_selected) | access_done;
// need internal signals of the output signals
assign M_VALID = m_valid_i;
assign S_READY = s_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Assign conditional onehot target output signal.
assign M_GRANT_HOT = (C_GRANT_HOT == 1) ? grant_hot[0+:C_NUM_S] : {C_NUM_S{1'b0}};
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded target output signal.
assign M_GRANT_ENC = (C_GRANT_ENC == 1) ? f_hot2enc(grant_hot) : {C_NUM_S_LOG{1'b0}};
/////////////////////////////////////////////////////////////////////////////
// Select a new chosen when we need to arbitrate
// If we don't have a new chosen, keep the old one since it's a good chance
// that it will do another request
always @(posedge ACLK)
begin
if (ARESET) begin
chosen <= {C_NUM_S{1'b0}};
last_rr_hot <= {1'b1, {C_NUM_S-1{1'b0}}};
end else if (need_arbitration) begin
chosen <= next_rr_hot;
if (|next_rr_hot) last_rr_hot <= next_rr_hot;
end
end
assign valid_rr = S_VALID;
/////////////////////////////////////////////////////////////////////////////
// Round-robin arbiter
// Selects next request to grant from among inputs with PRIO = 0, if any.
/////////////////////////////////////////////////////////////////////////////
always @ * begin
next_rr_hot = 0;
for (i=0;i<C_NUM_S;i=i+1) begin
n = (i>0) ? (i-1) : (C_NUM_S-1);
carry_rr[i*C_NUM_S] = last_rr_hot[n];
mask_rr[i*C_NUM_S] = ~valid_rr[n];
for (j=1;j<C_NUM_S;j=j+1) begin
n = (i-j > 0) ? (i-j-1) : (C_NUM_S+i-j-1);
carry_rr[i*C_NUM_S+j] = carry_rr[i*C_NUM_S+j-1] | (last_rr_hot[n] & mask_rr[i*C_NUM_S+j-1]);
if (j < C_NUM_S-1) begin
mask_rr[i*C_NUM_S+j] = mask_rr[i*C_NUM_S+j-1] & ~valid_rr[n];
end
end
next_rr_hot[i] = valid_rr[i] & carry_rr[(i+1)*C_NUM_S-1];
end
end
endmodule |
module processing_system7_bfm_v2_0_5_ocm_mem();
`include "processing_system7_bfm_v2_0_5_local_params.v"
parameter mem_size = 32'h4_0000; /// 256 KB
parameter mem_addr_width = clogb2(mem_size/mem_width);
reg [data_width-1:0] ocm_memory [0:(mem_size/mem_width)-1]; /// 256 KB memory
/* preload memory from file */
task automatic pre_load_mem_from_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
$readmemh(file_name,ocm_memory,start_addr>>shft_addr_bits);
endtask
/* preload memory with some random data */
task automatic pre_load_mem;
input [1:0] data_type;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
integer i;
reg [mem_addr_width-1:0] addr;
begin
addr = start_addr >> shft_addr_bits;
for (i = 0; i < no_of_bytes; i = i + mem_width) begin
case(data_type)
ALL_RANDOM : ocm_memory[addr] = $random;
ALL_ZEROS : ocm_memory[addr] = 32'h0000_0000;
ALL_ONES : ocm_memory[addr] = 32'hFFFF_FFFF;
default : ocm_memory[addr] = $random;
endcase
addr = addr+1;
end
end
endtask
/* Write memory */
task write_mem;
input [max_burst_bits-1 :0] data;
input [addr_width-1:0] start_addr;
input [max_burst_bytes_width:0] no_of_bytes;
reg [mem_addr_width-1:0] addr;
reg [max_burst_bits-1 :0] wr_temp_data;
reg [data_width-1:0] pre_pad_data,post_pad_data,temp_data;
integer bytes_left;
integer pre_pad_bytes;
integer post_pad_bytes;
begin
addr = start_addr >> shft_addr_bits;
wr_temp_data = data;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : Writing OCM Memory starting address (0x%0h) with %0d bytes.\n Data (0x%0h)",$time, DISP_INT_INFO, start_addr, no_of_bytes, data);
`endif
temp_data = wr_temp_data[data_width-1:0];
bytes_left = no_of_bytes;
/* when the no. of bytes to be updated is less than mem_width */
if(bytes_left < mem_width) begin
/* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
if(start_addr[shft_addr_bits-1:0] > 0) begin
temp_data = ocm_memory[addr];
pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
repeat(pre_pad_bytes) temp_data = temp_data << 8;
repeat(pre_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
wr_temp_data = wr_temp_data >> 8;
end
bytes_left = bytes_left + pre_pad_bytes;
end
/* This is needed for post padding the data ...*/
post_pad_bytes = mem_width - bytes_left;
post_pad_data = ocm_memory[addr];
repeat(post_pad_bytes) temp_data = temp_data << 8;
repeat(bytes_left) post_pad_data = post_pad_data >> 8;
repeat(post_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
post_pad_data = post_pad_data >> 8;
end
ocm_memory[addr] = temp_data;
end else begin
/* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
if(start_addr[shft_addr_bits-1:0] > 0) begin
temp_data = ocm_memory[addr];
pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
repeat(pre_pad_bytes) temp_data = temp_data << 8;
repeat(pre_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
wr_temp_data = wr_temp_data >> 8;
bytes_left = bytes_left -1;
end
end else begin
wr_temp_data = wr_temp_data >> data_width;
bytes_left = bytes_left - mem_width;
end
/* first data word end */
ocm_memory[addr] = temp_data;
addr = addr + 1;
while(bytes_left > (mem_width-1) ) begin /// for unaliged address necessary to check for mem_wd-1 , accordingly we have to pad post bytes.
ocm_memory[addr] = wr_temp_data[data_width-1:0];
addr = addr+1;
wr_temp_data = wr_temp_data >> data_width;
bytes_left = bytes_left - mem_width;
end
post_pad_data = ocm_memory[addr];
post_pad_bytes = mem_width - bytes_left;
/* This is needed for last transfer in unaliged burst */
if(bytes_left > 0) begin
temp_data = wr_temp_data[data_width-1:0];
repeat(post_pad_bytes) temp_data = temp_data << 8;
repeat(bytes_left) post_pad_data = post_pad_data >> 8;
repeat(post_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
post_pad_data = post_pad_data >> 8;
end
ocm_memory[addr] = temp_data;
end
end
`ifdef XLNX_INT_DBG $display("[%0d] : %0s : DONE -> Writing OCM Memory starting address (0x%0h)",$time, DISP_INT_INFO, start_addr );
`endif
end
endtask
/* read_memory */
task read_mem;
output[max_burst_bits-1 :0] data;
input [addr_width-1:0] start_addr;
input [max_burst_bytes_width:0] no_of_bytes;
integer i;
reg [mem_addr_width-1:0] addr;
reg [data_width-1:0] temp_rd_data;
reg [max_burst_bits-1:0] temp_data;
integer pre_bytes;
integer bytes_left;
begin
addr = start_addr >> shft_addr_bits;
pre_bytes = start_addr[shft_addr_bits-1:0];
bytes_left = no_of_bytes;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : Reading OCM Memory starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes );
`endif
/* Get first data ... if unaligned address */
temp_data[max_burst_bits-1 : max_burst_bits-data_width] = ocm_memory[addr];
if(no_of_bytes < mem_width ) begin
temp_data = temp_data >> (pre_bytes * 8);
repeat(max_burst_bytes - mem_width)
temp_data = temp_data >> 8;
end else begin
bytes_left = bytes_left - (mem_width - pre_bytes);
addr = addr+1;
/* Got first data */
while (bytes_left > (mem_width-1) ) begin
temp_data = temp_data >> data_width;
temp_data[max_burst_bits-1 : max_burst_bits-data_width] = ocm_memory[addr];
addr = addr+1;
bytes_left = bytes_left - mem_width;
end
/* Get last valid data in the burst*/
temp_rd_data = ocm_memory[addr];
while(bytes_left > 0) begin
temp_data = temp_data >> 8;
temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0];
temp_rd_data = temp_rd_data >> 8;
bytes_left = bytes_left - 1;
end
/* align to the brst_byte length */
repeat(max_burst_bytes - no_of_bytes)
temp_data = temp_data >> 8;
end
data = temp_data;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : DONE -> Reading OCM Memory starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data );
`endif
end
endtask
/* backdoor read to memory */
task peek_mem_to_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
integer rd_fd;
integer bytes;
reg [addr_width-1:0] addr;
reg [data_width-1:0] rd_data;
begin
rd_fd = $fopen(file_name,"w");
bytes = no_of_bytes;
addr = start_addr >> shft_addr_bits;
while (bytes > 0) begin
rd_data = ocm_memory[addr];
$fdisplayh(rd_fd,rd_data);
bytes = bytes - 4;
addr = addr + 1;
end
end
endtask
endmodule |
module processing_system7_bfm_v2_0_5_sparse_mem();
`include "processing_system7_bfm_v2_0_5_local_params.v"
parameter mem_size = 32'h4000_0000; /// 1GB mem size
parameter xsim_mem_size = 32'h1000_0000; ///256 MB mem size (x4 for XSIM/ISIM)
`ifdef XSIM_ISIM
reg [data_width-1:0] ddr_mem0 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
reg [data_width-1:0] ddr_mem1 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
reg [data_width-1:0] ddr_mem2 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
reg [data_width-1:0] ddr_mem3 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
`else
reg /*sparse*/ [data_width-1:0] ddr_mem [0:(mem_size/mem_width)-1]; // 'h10_0000 to 'h3FFF_FFFF - 1G mem
`endif
event mem_updated;
reg check_we;
reg [addr_width-1:0] check_up_add;
reg [data_width-1:0] updated_data;
/* preload memory from file */
task automatic pre_load_mem_from_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
`ifdef XSIM_ISIM
case(start_addr[31:28])
4'd0 : $readmemh(file_name,ddr_mem0,start_addr>>shft_addr_bits);
4'd1 : $readmemh(file_name,ddr_mem1,start_addr>>shft_addr_bits);
4'd2 : $readmemh(file_name,ddr_mem2,start_addr>>shft_addr_bits);
4'd3 : $readmemh(file_name,ddr_mem3,start_addr>>shft_addr_bits);
endcase
`else
$readmemh(file_name,ddr_mem,start_addr>>shft_addr_bits);
`endif
endtask
/* preload memory with some random data */
task automatic pre_load_mem;
input [1:0] data_type;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
integer i;
reg [addr_width-1:0] addr;
begin
addr = start_addr >> shft_addr_bits;
for (i = 0; i < no_of_bytes; i = i + mem_width) begin
case(data_type)
ALL_RANDOM : set_data(addr , $random);
ALL_ZEROS : set_data(addr , 32'h0000_0000);
ALL_ONES : set_data(addr , 32'hFFFF_FFFF);
default : set_data(addr , $random);
endcase
addr = addr+1;
end
end
endtask
/* wait for memory update at certain location */
task automatic wait_mem_update;
input[addr_width-1:0] address;
output[data_width-1:0] dataout;
begin
check_up_add = address >> shft_addr_bits;
check_we = 1;
@(mem_updated);
dataout = updated_data;
check_we = 0;
end
endtask
/* internal task to write data in memory */
task automatic set_data;
input [addr_width-1:0] addr;
input [data_width-1:0] data;
begin
if(check_we && (addr === check_up_add)) begin
updated_data = data;
-> mem_updated;
end
`ifdef XSIM_ISIM
case(addr[31:26])
6'd0 : ddr_mem0[addr[25:0]] = data;
6'd1 : ddr_mem1[addr[25:0]] = data;
6'd2 : ddr_mem2[addr[25:0]] = data;
6'd3 : ddr_mem3[addr[25:0]] = data;
endcase
`else
ddr_mem[addr] = data;
`endif
end
endtask
/* internal task to read data from memory */
task automatic get_data;
input [addr_width-1:0] addr;
output [data_width-1:0] data;
begin
`ifdef XSIM_ISIM
case(addr[31:26])
6'd0 : data = ddr_mem0[addr[25:0]];
6'd1 : data = ddr_mem1[addr[25:0]];
6'd2 : data = ddr_mem2[addr[25:0]];
6'd3 : data = ddr_mem3[addr[25:0]];
endcase
`else
data = ddr_mem[addr];
`endif
end
endtask
/* Write memory */
task write_mem;
input [max_burst_bits-1 :0] data;
input [addr_width-1:0] start_addr;
input [max_burst_bytes_width:0] no_of_bytes;
reg [addr_width-1:0] addr;
reg [max_burst_bits-1 :0] wr_temp_data;
reg [data_width-1:0] pre_pad_data,post_pad_data,temp_data;
integer bytes_left;
integer pre_pad_bytes;
integer post_pad_bytes;
begin
addr = start_addr >> shft_addr_bits;
wr_temp_data = data;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : Writing DDR Memory starting address (0x%0h) with %0d bytes.\n Data (0x%0h)",$time, DISP_INT_INFO, start_addr, no_of_bytes, data);
`endif
temp_data = wr_temp_data[data_width-1:0];
bytes_left = no_of_bytes;
/* when the no. of bytes to be updated is less than mem_width */
if(bytes_left < mem_width) begin
/* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
if(start_addr[shft_addr_bits-1:0] > 0) begin
//temp_data = ddr_mem[addr];
get_data(addr,temp_data);
pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
repeat(pre_pad_bytes) temp_data = temp_data << 8;
repeat(pre_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
wr_temp_data = wr_temp_data >> 8;
end
bytes_left = bytes_left + pre_pad_bytes;
end
/* This is needed for post padding the data ...*/
post_pad_bytes = mem_width - bytes_left;
//post_pad_data = ddr_mem[addr];
get_data(addr,post_pad_data);
repeat(post_pad_bytes) temp_data = temp_data << 8;
repeat(bytes_left) post_pad_data = post_pad_data >> 8;
repeat(post_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
post_pad_data = post_pad_data >> 8;
end
//ddr_mem[addr] = temp_data;
set_data(addr,temp_data);
end else begin
/* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
if(start_addr[shft_addr_bits-1:0] > 0) begin
//temp_data = ddr_mem[addr];
get_data(addr,temp_data);
pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
repeat(pre_pad_bytes) temp_data = temp_data << 8;
repeat(pre_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
wr_temp_data = wr_temp_data >> 8;
bytes_left = bytes_left -1;
end
end else begin
wr_temp_data = wr_temp_data >> data_width;
bytes_left = bytes_left - mem_width;
end
/* first data word end */
//ddr_mem[addr] = temp_data;
set_data(addr,temp_data);
addr = addr + 1;
while(bytes_left > (mem_width-1) ) begin /// for unaliged address necessary to check for mem_wd-1 , accordingly we have to pad post bytes.
//ddr_mem[addr] = wr_temp_data[data_width-1:0];
set_data(addr,wr_temp_data[data_width-1:0]);
addr = addr+1;
wr_temp_data = wr_temp_data >> data_width;
bytes_left = bytes_left - mem_width;
end
//post_pad_data = ddr_mem[addr];
get_data(addr,post_pad_data);
post_pad_bytes = mem_width - bytes_left;
/* This is needed for last transfer in unaliged burst */
if(bytes_left > 0) begin
temp_data = wr_temp_data[data_width-1:0];
repeat(post_pad_bytes) temp_data = temp_data << 8;
repeat(bytes_left) post_pad_data = post_pad_data >> 8;
repeat(post_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
post_pad_data = post_pad_data >> 8;
end
//ddr_mem[addr] = temp_data;
set_data(addr,temp_data);
end
end
`ifdef XLNX_INT_DBG $display("[%0d] : %0s : DONE -> Writing DDR Memory starting address (0x%0h)",$time, DISP_INT_INFO, start_addr );
`endif
end
endtask
/* read_memory */
task read_mem;
output[max_burst_bits-1 :0] data;
input [addr_width-1:0] start_addr;
input [max_burst_bytes_width :0] no_of_bytes;
integer i;
reg [addr_width-1:0] addr;
reg [data_width-1:0] temp_rd_data;
reg [max_burst_bits-1:0] temp_data;
integer pre_bytes;
integer bytes_left;
begin
addr = start_addr >> shft_addr_bits;
pre_bytes = start_addr[shft_addr_bits-1:0];
bytes_left = no_of_bytes;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : Reading DDR Memory starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes );
`endif
/* Get first data ... if unaligned address */
//temp_data[(max_burst * max_data_burst)-1 : (max_burst * max_data_burst)- data_width] = ddr_mem[addr];
get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]);
if(no_of_bytes < mem_width ) begin
temp_data = temp_data >> (pre_bytes * 8);
repeat(max_burst_bytes - mem_width)
temp_data = temp_data >> 8;
end else begin
bytes_left = bytes_left - (mem_width - pre_bytes);
addr = addr+1;
/* Got first data */
while (bytes_left > (mem_width-1) ) begin
temp_data = temp_data >> data_width;
//temp_data[(max_burst * max_data_burst)-1 : (max_burst * max_data_burst)- data_width] = ddr_mem[addr];
get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]);
addr = addr+1;
bytes_left = bytes_left - mem_width;
end
/* Get last valid data in the burst*/
//temp_rd_data = ddr_mem[addr];
get_data(addr,temp_rd_data);
while(bytes_left > 0) begin
temp_data = temp_data >> 8;
temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0];
temp_rd_data = temp_rd_data >> 8;
bytes_left = bytes_left - 1;
end
/* align to the brst_byte length */
repeat(max_burst_bytes - no_of_bytes)
temp_data = temp_data >> 8;
end
data = temp_data;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : DONE -> Reading DDR Memory starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data );
`endif
end
endtask
/* backdoor read to memory */
task peek_mem_to_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
integer rd_fd;
integer bytes;
reg [addr_width-1:0] addr;
reg [data_width-1:0] rd_data;
begin
rd_fd = $fopen(file_name,"w");
bytes = no_of_bytes;
addr = start_addr >> shft_addr_bits;
while (bytes > 0) begin
get_data(addr,rd_data);
$fdisplayh(rd_fd,rd_data);
bytes = bytes - 4;
addr = addr + 1;
end
end
endtask
endmodule |
module processing_system7_bfm_v2_0_5_sparse_mem();
`include "processing_system7_bfm_v2_0_5_local_params.v"
parameter mem_size = 32'h4000_0000; /// 1GB mem size
parameter xsim_mem_size = 32'h1000_0000; ///256 MB mem size (x4 for XSIM/ISIM)
`ifdef XSIM_ISIM
reg [data_width-1:0] ddr_mem0 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
reg [data_width-1:0] ddr_mem1 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
reg [data_width-1:0] ddr_mem2 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
reg [data_width-1:0] ddr_mem3 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
`else
reg /*sparse*/ [data_width-1:0] ddr_mem [0:(mem_size/mem_width)-1]; // 'h10_0000 to 'h3FFF_FFFF - 1G mem
`endif
event mem_updated;
reg check_we;
reg [addr_width-1:0] check_up_add;
reg [data_width-1:0] updated_data;
/* preload memory from file */
task automatic pre_load_mem_from_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
`ifdef XSIM_ISIM
case(start_addr[31:28])
4'd0 : $readmemh(file_name,ddr_mem0,start_addr>>shft_addr_bits);
4'd1 : $readmemh(file_name,ddr_mem1,start_addr>>shft_addr_bits);
4'd2 : $readmemh(file_name,ddr_mem2,start_addr>>shft_addr_bits);
4'd3 : $readmemh(file_name,ddr_mem3,start_addr>>shft_addr_bits);
endcase
`else
$readmemh(file_name,ddr_mem,start_addr>>shft_addr_bits);
`endif
endtask
/* preload memory with some random data */
task automatic pre_load_mem;
input [1:0] data_type;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
integer i;
reg [addr_width-1:0] addr;
begin
addr = start_addr >> shft_addr_bits;
for (i = 0; i < no_of_bytes; i = i + mem_width) begin
case(data_type)
ALL_RANDOM : set_data(addr , $random);
ALL_ZEROS : set_data(addr , 32'h0000_0000);
ALL_ONES : set_data(addr , 32'hFFFF_FFFF);
default : set_data(addr , $random);
endcase
addr = addr+1;
end
end
endtask
/* wait for memory update at certain location */
task automatic wait_mem_update;
input[addr_width-1:0] address;
output[data_width-1:0] dataout;
begin
check_up_add = address >> shft_addr_bits;
check_we = 1;
@(mem_updated);
dataout = updated_data;
check_we = 0;
end
endtask
/* internal task to write data in memory */
task automatic set_data;
input [addr_width-1:0] addr;
input [data_width-1:0] data;
begin
if(check_we && (addr === check_up_add)) begin
updated_data = data;
-> mem_updated;
end
`ifdef XSIM_ISIM
case(addr[31:26])
6'd0 : ddr_mem0[addr[25:0]] = data;
6'd1 : ddr_mem1[addr[25:0]] = data;
6'd2 : ddr_mem2[addr[25:0]] = data;
6'd3 : ddr_mem3[addr[25:0]] = data;
endcase
`else
ddr_mem[addr] = data;
`endif
end
endtask
/* internal task to read data from memory */
task automatic get_data;
input [addr_width-1:0] addr;
output [data_width-1:0] data;
begin
`ifdef XSIM_ISIM
case(addr[31:26])
6'd0 : data = ddr_mem0[addr[25:0]];
6'd1 : data = ddr_mem1[addr[25:0]];
6'd2 : data = ddr_mem2[addr[25:0]];
6'd3 : data = ddr_mem3[addr[25:0]];
endcase
`else
data = ddr_mem[addr];
`endif
end
endtask
/* Write memory */
task write_mem;
input [max_burst_bits-1 :0] data;
input [addr_width-1:0] start_addr;
input [max_burst_bytes_width:0] no_of_bytes;
reg [addr_width-1:0] addr;
reg [max_burst_bits-1 :0] wr_temp_data;
reg [data_width-1:0] pre_pad_data,post_pad_data,temp_data;
integer bytes_left;
integer pre_pad_bytes;
integer post_pad_bytes;
begin
addr = start_addr >> shft_addr_bits;
wr_temp_data = data;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : Writing DDR Memory starting address (0x%0h) with %0d bytes.\n Data (0x%0h)",$time, DISP_INT_INFO, start_addr, no_of_bytes, data);
`endif
temp_data = wr_temp_data[data_width-1:0];
bytes_left = no_of_bytes;
/* when the no. of bytes to be updated is less than mem_width */
if(bytes_left < mem_width) begin
/* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
if(start_addr[shft_addr_bits-1:0] > 0) begin
//temp_data = ddr_mem[addr];
get_data(addr,temp_data);
pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
repeat(pre_pad_bytes) temp_data = temp_data << 8;
repeat(pre_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
wr_temp_data = wr_temp_data >> 8;
end
bytes_left = bytes_left + pre_pad_bytes;
end
/* This is needed for post padding the data ...*/
post_pad_bytes = mem_width - bytes_left;
//post_pad_data = ddr_mem[addr];
get_data(addr,post_pad_data);
repeat(post_pad_bytes) temp_data = temp_data << 8;
repeat(bytes_left) post_pad_data = post_pad_data >> 8;
repeat(post_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
post_pad_data = post_pad_data >> 8;
end
//ddr_mem[addr] = temp_data;
set_data(addr,temp_data);
end else begin
/* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
if(start_addr[shft_addr_bits-1:0] > 0) begin
//temp_data = ddr_mem[addr];
get_data(addr,temp_data);
pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
repeat(pre_pad_bytes) temp_data = temp_data << 8;
repeat(pre_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
wr_temp_data = wr_temp_data >> 8;
bytes_left = bytes_left -1;
end
end else begin
wr_temp_data = wr_temp_data >> data_width;
bytes_left = bytes_left - mem_width;
end
/* first data word end */
//ddr_mem[addr] = temp_data;
set_data(addr,temp_data);
addr = addr + 1;
while(bytes_left > (mem_width-1) ) begin /// for unaliged address necessary to check for mem_wd-1 , accordingly we have to pad post bytes.
//ddr_mem[addr] = wr_temp_data[data_width-1:0];
set_data(addr,wr_temp_data[data_width-1:0]);
addr = addr+1;
wr_temp_data = wr_temp_data >> data_width;
bytes_left = bytes_left - mem_width;
end
//post_pad_data = ddr_mem[addr];
get_data(addr,post_pad_data);
post_pad_bytes = mem_width - bytes_left;
/* This is needed for last transfer in unaliged burst */
if(bytes_left > 0) begin
temp_data = wr_temp_data[data_width-1:0];
repeat(post_pad_bytes) temp_data = temp_data << 8;
repeat(bytes_left) post_pad_data = post_pad_data >> 8;
repeat(post_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
post_pad_data = post_pad_data >> 8;
end
//ddr_mem[addr] = temp_data;
set_data(addr,temp_data);
end
end
`ifdef XLNX_INT_DBG $display("[%0d] : %0s : DONE -> Writing DDR Memory starting address (0x%0h)",$time, DISP_INT_INFO, start_addr );
`endif
end
endtask
/* read_memory */
task read_mem;
output[max_burst_bits-1 :0] data;
input [addr_width-1:0] start_addr;
input [max_burst_bytes_width :0] no_of_bytes;
integer i;
reg [addr_width-1:0] addr;
reg [data_width-1:0] temp_rd_data;
reg [max_burst_bits-1:0] temp_data;
integer pre_bytes;
integer bytes_left;
begin
addr = start_addr >> shft_addr_bits;
pre_bytes = start_addr[shft_addr_bits-1:0];
bytes_left = no_of_bytes;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : Reading DDR Memory starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes );
`endif
/* Get first data ... if unaligned address */
//temp_data[(max_burst * max_data_burst)-1 : (max_burst * max_data_burst)- data_width] = ddr_mem[addr];
get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]);
if(no_of_bytes < mem_width ) begin
temp_data = temp_data >> (pre_bytes * 8);
repeat(max_burst_bytes - mem_width)
temp_data = temp_data >> 8;
end else begin
bytes_left = bytes_left - (mem_width - pre_bytes);
addr = addr+1;
/* Got first data */
while (bytes_left > (mem_width-1) ) begin
temp_data = temp_data >> data_width;
//temp_data[(max_burst * max_data_burst)-1 : (max_burst * max_data_burst)- data_width] = ddr_mem[addr];
get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]);
addr = addr+1;
bytes_left = bytes_left - mem_width;
end
/* Get last valid data in the burst*/
//temp_rd_data = ddr_mem[addr];
get_data(addr,temp_rd_data);
while(bytes_left > 0) begin
temp_data = temp_data >> 8;
temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0];
temp_rd_data = temp_rd_data >> 8;
bytes_left = bytes_left - 1;
end
/* align to the brst_byte length */
repeat(max_burst_bytes - no_of_bytes)
temp_data = temp_data >> 8;
end
data = temp_data;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : DONE -> Reading DDR Memory starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data );
`endif
end
endtask
/* backdoor read to memory */
task peek_mem_to_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
integer rd_fd;
integer bytes;
reg [addr_width-1:0] addr;
reg [data_width-1:0] rd_data;
begin
rd_fd = $fopen(file_name,"w");
bytes = no_of_bytes;
addr = start_addr >> shft_addr_bits;
while (bytes > 0) begin
get_data(addr,rd_data);
$fdisplayh(rd_fd,rd_data);
bytes = bytes - 4;
addr = addr + 1;
end
end
endtask
endmodule |
module processing_system7_bfm_v2_0_5_sparse_mem();
`include "processing_system7_bfm_v2_0_5_local_params.v"
parameter mem_size = 32'h4000_0000; /// 1GB mem size
parameter xsim_mem_size = 32'h1000_0000; ///256 MB mem size (x4 for XSIM/ISIM)
`ifdef XSIM_ISIM
reg [data_width-1:0] ddr_mem0 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
reg [data_width-1:0] ddr_mem1 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
reg [data_width-1:0] ddr_mem2 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
reg [data_width-1:0] ddr_mem3 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
`else
reg /*sparse*/ [data_width-1:0] ddr_mem [0:(mem_size/mem_width)-1]; // 'h10_0000 to 'h3FFF_FFFF - 1G mem
`endif
event mem_updated;
reg check_we;
reg [addr_width-1:0] check_up_add;
reg [data_width-1:0] updated_data;
/* preload memory from file */
task automatic pre_load_mem_from_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
`ifdef XSIM_ISIM
case(start_addr[31:28])
4'd0 : $readmemh(file_name,ddr_mem0,start_addr>>shft_addr_bits);
4'd1 : $readmemh(file_name,ddr_mem1,start_addr>>shft_addr_bits);
4'd2 : $readmemh(file_name,ddr_mem2,start_addr>>shft_addr_bits);
4'd3 : $readmemh(file_name,ddr_mem3,start_addr>>shft_addr_bits);
endcase
`else
$readmemh(file_name,ddr_mem,start_addr>>shft_addr_bits);
`endif
endtask
/* preload memory with some random data */
task automatic pre_load_mem;
input [1:0] data_type;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
integer i;
reg [addr_width-1:0] addr;
begin
addr = start_addr >> shft_addr_bits;
for (i = 0; i < no_of_bytes; i = i + mem_width) begin
case(data_type)
ALL_RANDOM : set_data(addr , $random);
ALL_ZEROS : set_data(addr , 32'h0000_0000);
ALL_ONES : set_data(addr , 32'hFFFF_FFFF);
default : set_data(addr , $random);
endcase
addr = addr+1;
end
end
endtask
/* wait for memory update at certain location */
task automatic wait_mem_update;
input[addr_width-1:0] address;
output[data_width-1:0] dataout;
begin
check_up_add = address >> shft_addr_bits;
check_we = 1;
@(mem_updated);
dataout = updated_data;
check_we = 0;
end
endtask
/* internal task to write data in memory */
task automatic set_data;
input [addr_width-1:0] addr;
input [data_width-1:0] data;
begin
if(check_we && (addr === check_up_add)) begin
updated_data = data;
-> mem_updated;
end
`ifdef XSIM_ISIM
case(addr[31:26])
6'd0 : ddr_mem0[addr[25:0]] = data;
6'd1 : ddr_mem1[addr[25:0]] = data;
6'd2 : ddr_mem2[addr[25:0]] = data;
6'd3 : ddr_mem3[addr[25:0]] = data;
endcase
`else
ddr_mem[addr] = data;
`endif
end
endtask
/* internal task to read data from memory */
task automatic get_data;
input [addr_width-1:0] addr;
output [data_width-1:0] data;
begin
`ifdef XSIM_ISIM
case(addr[31:26])
6'd0 : data = ddr_mem0[addr[25:0]];
6'd1 : data = ddr_mem1[addr[25:0]];
6'd2 : data = ddr_mem2[addr[25:0]];
6'd3 : data = ddr_mem3[addr[25:0]];
endcase
`else
data = ddr_mem[addr];
`endif
end
endtask
/* Write memory */
task write_mem;
input [max_burst_bits-1 :0] data;
input [addr_width-1:0] start_addr;
input [max_burst_bytes_width:0] no_of_bytes;
reg [addr_width-1:0] addr;
reg [max_burst_bits-1 :0] wr_temp_data;
reg [data_width-1:0] pre_pad_data,post_pad_data,temp_data;
integer bytes_left;
integer pre_pad_bytes;
integer post_pad_bytes;
begin
addr = start_addr >> shft_addr_bits;
wr_temp_data = data;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : Writing DDR Memory starting address (0x%0h) with %0d bytes.\n Data (0x%0h)",$time, DISP_INT_INFO, start_addr, no_of_bytes, data);
`endif
temp_data = wr_temp_data[data_width-1:0];
bytes_left = no_of_bytes;
/* when the no. of bytes to be updated is less than mem_width */
if(bytes_left < mem_width) begin
/* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
if(start_addr[shft_addr_bits-1:0] > 0) begin
//temp_data = ddr_mem[addr];
get_data(addr,temp_data);
pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
repeat(pre_pad_bytes) temp_data = temp_data << 8;
repeat(pre_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
wr_temp_data = wr_temp_data >> 8;
end
bytes_left = bytes_left + pre_pad_bytes;
end
/* This is needed for post padding the data ...*/
post_pad_bytes = mem_width - bytes_left;
//post_pad_data = ddr_mem[addr];
get_data(addr,post_pad_data);
repeat(post_pad_bytes) temp_data = temp_data << 8;
repeat(bytes_left) post_pad_data = post_pad_data >> 8;
repeat(post_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
post_pad_data = post_pad_data >> 8;
end
//ddr_mem[addr] = temp_data;
set_data(addr,temp_data);
end else begin
/* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
if(start_addr[shft_addr_bits-1:0] > 0) begin
//temp_data = ddr_mem[addr];
get_data(addr,temp_data);
pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
repeat(pre_pad_bytes) temp_data = temp_data << 8;
repeat(pre_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
wr_temp_data = wr_temp_data >> 8;
bytes_left = bytes_left -1;
end
end else begin
wr_temp_data = wr_temp_data >> data_width;
bytes_left = bytes_left - mem_width;
end
/* first data word end */
//ddr_mem[addr] = temp_data;
set_data(addr,temp_data);
addr = addr + 1;
while(bytes_left > (mem_width-1) ) begin /// for unaliged address necessary to check for mem_wd-1 , accordingly we have to pad post bytes.
//ddr_mem[addr] = wr_temp_data[data_width-1:0];
set_data(addr,wr_temp_data[data_width-1:0]);
addr = addr+1;
wr_temp_data = wr_temp_data >> data_width;
bytes_left = bytes_left - mem_width;
end
//post_pad_data = ddr_mem[addr];
get_data(addr,post_pad_data);
post_pad_bytes = mem_width - bytes_left;
/* This is needed for last transfer in unaliged burst */
if(bytes_left > 0) begin
temp_data = wr_temp_data[data_width-1:0];
repeat(post_pad_bytes) temp_data = temp_data << 8;
repeat(bytes_left) post_pad_data = post_pad_data >> 8;
repeat(post_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
post_pad_data = post_pad_data >> 8;
end
//ddr_mem[addr] = temp_data;
set_data(addr,temp_data);
end
end
`ifdef XLNX_INT_DBG $display("[%0d] : %0s : DONE -> Writing DDR Memory starting address (0x%0h)",$time, DISP_INT_INFO, start_addr );
`endif
end
endtask
/* read_memory */
task read_mem;
output[max_burst_bits-1 :0] data;
input [addr_width-1:0] start_addr;
input [max_burst_bytes_width :0] no_of_bytes;
integer i;
reg [addr_width-1:0] addr;
reg [data_width-1:0] temp_rd_data;
reg [max_burst_bits-1:0] temp_data;
integer pre_bytes;
integer bytes_left;
begin
addr = start_addr >> shft_addr_bits;
pre_bytes = start_addr[shft_addr_bits-1:0];
bytes_left = no_of_bytes;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : Reading DDR Memory starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes );
`endif
/* Get first data ... if unaligned address */
//temp_data[(max_burst * max_data_burst)-1 : (max_burst * max_data_burst)- data_width] = ddr_mem[addr];
get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]);
if(no_of_bytes < mem_width ) begin
temp_data = temp_data >> (pre_bytes * 8);
repeat(max_burst_bytes - mem_width)
temp_data = temp_data >> 8;
end else begin
bytes_left = bytes_left - (mem_width - pre_bytes);
addr = addr+1;
/* Got first data */
while (bytes_left > (mem_width-1) ) begin
temp_data = temp_data >> data_width;
//temp_data[(max_burst * max_data_burst)-1 : (max_burst * max_data_burst)- data_width] = ddr_mem[addr];
get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]);
addr = addr+1;
bytes_left = bytes_left - mem_width;
end
/* Get last valid data in the burst*/
//temp_rd_data = ddr_mem[addr];
get_data(addr,temp_rd_data);
while(bytes_left > 0) begin
temp_data = temp_data >> 8;
temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0];
temp_rd_data = temp_rd_data >> 8;
bytes_left = bytes_left - 1;
end
/* align to the brst_byte length */
repeat(max_burst_bytes - no_of_bytes)
temp_data = temp_data >> 8;
end
data = temp_data;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : DONE -> Reading DDR Memory starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data );
`endif
end
endtask
/* backdoor read to memory */
task peek_mem_to_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
integer rd_fd;
integer bytes;
reg [addr_width-1:0] addr;
reg [data_width-1:0] rd_data;
begin
rd_fd = $fopen(file_name,"w");
bytes = no_of_bytes;
addr = start_addr >> shft_addr_bits;
while (bytes > 0) begin
get_data(addr,rd_data);
$fdisplayh(rd_fd,rd_data);
bytes = bytes - 4;
addr = addr + 1;
end
end
endtask
endmodule |
module processing_system7_bfm_v2_0_5_sparse_mem();
`include "processing_system7_bfm_v2_0_5_local_params.v"
parameter mem_size = 32'h4000_0000; /// 1GB mem size
parameter xsim_mem_size = 32'h1000_0000; ///256 MB mem size (x4 for XSIM/ISIM)
`ifdef XSIM_ISIM
reg [data_width-1:0] ddr_mem0 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
reg [data_width-1:0] ddr_mem1 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
reg [data_width-1:0] ddr_mem2 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
reg [data_width-1:0] ddr_mem3 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
`else
reg /*sparse*/ [data_width-1:0] ddr_mem [0:(mem_size/mem_width)-1]; // 'h10_0000 to 'h3FFF_FFFF - 1G mem
`endif
event mem_updated;
reg check_we;
reg [addr_width-1:0] check_up_add;
reg [data_width-1:0] updated_data;
/* preload memory from file */
task automatic pre_load_mem_from_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
`ifdef XSIM_ISIM
case(start_addr[31:28])
4'd0 : $readmemh(file_name,ddr_mem0,start_addr>>shft_addr_bits);
4'd1 : $readmemh(file_name,ddr_mem1,start_addr>>shft_addr_bits);
4'd2 : $readmemh(file_name,ddr_mem2,start_addr>>shft_addr_bits);
4'd3 : $readmemh(file_name,ddr_mem3,start_addr>>shft_addr_bits);
endcase
`else
$readmemh(file_name,ddr_mem,start_addr>>shft_addr_bits);
`endif
endtask
/* preload memory with some random data */
task automatic pre_load_mem;
input [1:0] data_type;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
integer i;
reg [addr_width-1:0] addr;
begin
addr = start_addr >> shft_addr_bits;
for (i = 0; i < no_of_bytes; i = i + mem_width) begin
case(data_type)
ALL_RANDOM : set_data(addr , $random);
ALL_ZEROS : set_data(addr , 32'h0000_0000);
ALL_ONES : set_data(addr , 32'hFFFF_FFFF);
default : set_data(addr , $random);
endcase
addr = addr+1;
end
end
endtask
/* wait for memory update at certain location */
task automatic wait_mem_update;
input[addr_width-1:0] address;
output[data_width-1:0] dataout;
begin
check_up_add = address >> shft_addr_bits;
check_we = 1;
@(mem_updated);
dataout = updated_data;
check_we = 0;
end
endtask
/* internal task to write data in memory */
task automatic set_data;
input [addr_width-1:0] addr;
input [data_width-1:0] data;
begin
if(check_we && (addr === check_up_add)) begin
updated_data = data;
-> mem_updated;
end
`ifdef XSIM_ISIM
case(addr[31:26])
6'd0 : ddr_mem0[addr[25:0]] = data;
6'd1 : ddr_mem1[addr[25:0]] = data;
6'd2 : ddr_mem2[addr[25:0]] = data;
6'd3 : ddr_mem3[addr[25:0]] = data;
endcase
`else
ddr_mem[addr] = data;
`endif
end
endtask
/* internal task to read data from memory */
task automatic get_data;
input [addr_width-1:0] addr;
output [data_width-1:0] data;
begin
`ifdef XSIM_ISIM
case(addr[31:26])
6'd0 : data = ddr_mem0[addr[25:0]];
6'd1 : data = ddr_mem1[addr[25:0]];
6'd2 : data = ddr_mem2[addr[25:0]];
6'd3 : data = ddr_mem3[addr[25:0]];
endcase
`else
data = ddr_mem[addr];
`endif
end
endtask
/* Write memory */
task write_mem;
input [max_burst_bits-1 :0] data;
input [addr_width-1:0] start_addr;
input [max_burst_bytes_width:0] no_of_bytes;
reg [addr_width-1:0] addr;
reg [max_burst_bits-1 :0] wr_temp_data;
reg [data_width-1:0] pre_pad_data,post_pad_data,temp_data;
integer bytes_left;
integer pre_pad_bytes;
integer post_pad_bytes;
begin
addr = start_addr >> shft_addr_bits;
wr_temp_data = data;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : Writing DDR Memory starting address (0x%0h) with %0d bytes.\n Data (0x%0h)",$time, DISP_INT_INFO, start_addr, no_of_bytes, data);
`endif
temp_data = wr_temp_data[data_width-1:0];
bytes_left = no_of_bytes;
/* when the no. of bytes to be updated is less than mem_width */
if(bytes_left < mem_width) begin
/* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
if(start_addr[shft_addr_bits-1:0] > 0) begin
//temp_data = ddr_mem[addr];
get_data(addr,temp_data);
pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
repeat(pre_pad_bytes) temp_data = temp_data << 8;
repeat(pre_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
wr_temp_data = wr_temp_data >> 8;
end
bytes_left = bytes_left + pre_pad_bytes;
end
/* This is needed for post padding the data ...*/
post_pad_bytes = mem_width - bytes_left;
//post_pad_data = ddr_mem[addr];
get_data(addr,post_pad_data);
repeat(post_pad_bytes) temp_data = temp_data << 8;
repeat(bytes_left) post_pad_data = post_pad_data >> 8;
repeat(post_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
post_pad_data = post_pad_data >> 8;
end
//ddr_mem[addr] = temp_data;
set_data(addr,temp_data);
end else begin
/* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
if(start_addr[shft_addr_bits-1:0] > 0) begin
//temp_data = ddr_mem[addr];
get_data(addr,temp_data);
pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
repeat(pre_pad_bytes) temp_data = temp_data << 8;
repeat(pre_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
wr_temp_data = wr_temp_data >> 8;
bytes_left = bytes_left -1;
end
end else begin
wr_temp_data = wr_temp_data >> data_width;
bytes_left = bytes_left - mem_width;
end
/* first data word end */
//ddr_mem[addr] = temp_data;
set_data(addr,temp_data);
addr = addr + 1;
while(bytes_left > (mem_width-1) ) begin /// for unaliged address necessary to check for mem_wd-1 , accordingly we have to pad post bytes.
//ddr_mem[addr] = wr_temp_data[data_width-1:0];
set_data(addr,wr_temp_data[data_width-1:0]);
addr = addr+1;
wr_temp_data = wr_temp_data >> data_width;
bytes_left = bytes_left - mem_width;
end
//post_pad_data = ddr_mem[addr];
get_data(addr,post_pad_data);
post_pad_bytes = mem_width - bytes_left;
/* This is needed for last transfer in unaliged burst */
if(bytes_left > 0) begin
temp_data = wr_temp_data[data_width-1:0];
repeat(post_pad_bytes) temp_data = temp_data << 8;
repeat(bytes_left) post_pad_data = post_pad_data >> 8;
repeat(post_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
post_pad_data = post_pad_data >> 8;
end
//ddr_mem[addr] = temp_data;
set_data(addr,temp_data);
end
end
`ifdef XLNX_INT_DBG $display("[%0d] : %0s : DONE -> Writing DDR Memory starting address (0x%0h)",$time, DISP_INT_INFO, start_addr );
`endif
end
endtask
/* read_memory */
task read_mem;
output[max_burst_bits-1 :0] data;
input [addr_width-1:0] start_addr;
input [max_burst_bytes_width :0] no_of_bytes;
integer i;
reg [addr_width-1:0] addr;
reg [data_width-1:0] temp_rd_data;
reg [max_burst_bits-1:0] temp_data;
integer pre_bytes;
integer bytes_left;
begin
addr = start_addr >> shft_addr_bits;
pre_bytes = start_addr[shft_addr_bits-1:0];
bytes_left = no_of_bytes;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : Reading DDR Memory starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes );
`endif
/* Get first data ... if unaligned address */
//temp_data[(max_burst * max_data_burst)-1 : (max_burst * max_data_burst)- data_width] = ddr_mem[addr];
get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]);
if(no_of_bytes < mem_width ) begin
temp_data = temp_data >> (pre_bytes * 8);
repeat(max_burst_bytes - mem_width)
temp_data = temp_data >> 8;
end else begin
bytes_left = bytes_left - (mem_width - pre_bytes);
addr = addr+1;
/* Got first data */
while (bytes_left > (mem_width-1) ) begin
temp_data = temp_data >> data_width;
//temp_data[(max_burst * max_data_burst)-1 : (max_burst * max_data_burst)- data_width] = ddr_mem[addr];
get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]);
addr = addr+1;
bytes_left = bytes_left - mem_width;
end
/* Get last valid data in the burst*/
//temp_rd_data = ddr_mem[addr];
get_data(addr,temp_rd_data);
while(bytes_left > 0) begin
temp_data = temp_data >> 8;
temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0];
temp_rd_data = temp_rd_data >> 8;
bytes_left = bytes_left - 1;
end
/* align to the brst_byte length */
repeat(max_burst_bytes - no_of_bytes)
temp_data = temp_data >> 8;
end
data = temp_data;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : DONE -> Reading DDR Memory starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data );
`endif
end
endtask
/* backdoor read to memory */
task peek_mem_to_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
integer rd_fd;
integer bytes;
reg [addr_width-1:0] addr;
reg [data_width-1:0] rd_data;
begin
rd_fd = $fopen(file_name,"w");
bytes = no_of_bytes;
addr = start_addr >> shft_addr_bits;
while (bytes > 0) begin
get_data(addr,rd_data);
$fdisplayh(rd_fd,rd_data);
bytes = bytes - 4;
addr = addr + 1;
end
end
endtask
endmodule |
module wishbone_mem_interconnect (
//Control Signals
input clk,
input rst,
//Master Signals
input i_m_we,
input i_m_stb,
input i_m_cyc,
input [3:0] i_m_sel,
input [31:0] i_m_adr,
input [31:0] i_m_dat,
output reg [31:0] o_m_dat,
output reg o_m_ack,
output reg o_m_int,
//Slave 0
output o_s0_we,
output o_s0_cyc,
output o_s0_stb,
output [3:0] o_s0_sel,
input i_s0_ack,
output [31:0] o_s0_dat,
input [31:0] i_s0_dat,
output [31:0] o_s0_adr,
input i_s0_int
);
parameter MEM_SEL_0 = 0;
parameter MEM_OFFSET_0 = 0;
parameter MEM_SIZE_0 = 8388607;
reg [31:0] mem_select;
always @(rst or i_m_adr or mem_select) begin
if (rst) begin
//nothing selected
mem_select <= 32'hFFFFFFFF;
end
else begin
if ((i_m_adr >= MEM_OFFSET_0) && (i_m_adr < (MEM_OFFSET_0 + MEM_SIZE_0))) begin
mem_select <= MEM_SEL_0;
end
else begin
mem_select <= 32'hFFFFFFFF;
end
end
end
//data in from slave
always @ (mem_select or i_s0_dat) begin
case (mem_select)
MEM_SEL_0: begin
o_m_dat <= i_s0_dat;
end
default: begin
o_m_dat <= 32'h0000;
end
endcase
end
//ack in from mem slave
always @ (mem_select or i_s0_ack) begin
case (mem_select)
MEM_SEL_0: begin
o_m_ack <= i_s0_ack;
end
default: begin
o_m_ack <= 1'h0;
end
endcase
end
//int in from slave
always @ (mem_select or i_s0_int) begin
case (mem_select)
MEM_SEL_0: begin
o_m_int <= i_s0_int;
end
default: begin
o_m_int <= 1'h0;
end
endcase
end
assign o_s0_we = (mem_select == MEM_SEL_0) ? i_m_we: 1'b0;
assign o_s0_stb = (mem_select == MEM_SEL_0) ? i_m_stb: 1'b0;
assign o_s0_sel = (mem_select == MEM_SEL_0) ? i_m_sel: 4'b0;
assign o_s0_cyc = (mem_select == MEM_SEL_0) ? i_m_cyc: 1'b0;
assign o_s0_adr = (mem_select == MEM_SEL_0) ? i_m_adr: 32'h0;
assign o_s0_dat = (mem_select == MEM_SEL_0) ? i_m_dat: 32'h0;
endmodule |
module wishbone_mem_interconnect (
//Control Signals
input clk,
input rst,
//Master Signals
input i_m_we,
input i_m_stb,
input i_m_cyc,
input [3:0] i_m_sel,
input [31:0] i_m_adr,
input [31:0] i_m_dat,
output reg [31:0] o_m_dat,
output reg o_m_ack,
output reg o_m_int,
//Slave 0
output o_s0_we,
output o_s0_cyc,
output o_s0_stb,
output [3:0] o_s0_sel,
input i_s0_ack,
output [31:0] o_s0_dat,
input [31:0] i_s0_dat,
output [31:0] o_s0_adr,
input i_s0_int
);
parameter MEM_SEL_0 = 0;
parameter MEM_OFFSET_0 = 0;
parameter MEM_SIZE_0 = 8388607;
reg [31:0] mem_select;
always @(rst or i_m_adr or mem_select) begin
if (rst) begin
//nothing selected
mem_select <= 32'hFFFFFFFF;
end
else begin
if ((i_m_adr >= MEM_OFFSET_0) && (i_m_adr < (MEM_OFFSET_0 + MEM_SIZE_0))) begin
mem_select <= MEM_SEL_0;
end
else begin
mem_select <= 32'hFFFFFFFF;
end
end
end
//data in from slave
always @ (mem_select or i_s0_dat) begin
case (mem_select)
MEM_SEL_0: begin
o_m_dat <= i_s0_dat;
end
default: begin
o_m_dat <= 32'h0000;
end
endcase
end
//ack in from mem slave
always @ (mem_select or i_s0_ack) begin
case (mem_select)
MEM_SEL_0: begin
o_m_ack <= i_s0_ack;
end
default: begin
o_m_ack <= 1'h0;
end
endcase
end
//int in from slave
always @ (mem_select or i_s0_int) begin
case (mem_select)
MEM_SEL_0: begin
o_m_int <= i_s0_int;
end
default: begin
o_m_int <= 1'h0;
end
endcase
end
assign o_s0_we = (mem_select == MEM_SEL_0) ? i_m_we: 1'b0;
assign o_s0_stb = (mem_select == MEM_SEL_0) ? i_m_stb: 1'b0;
assign o_s0_sel = (mem_select == MEM_SEL_0) ? i_m_sel: 4'b0;
assign o_s0_cyc = (mem_select == MEM_SEL_0) ? i_m_cyc: 1'b0;
assign o_s0_adr = (mem_select == MEM_SEL_0) ? i_m_adr: 32'h0;
assign o_s0_dat = (mem_select == MEM_SEL_0) ? i_m_dat: 32'h0;
endmodule |
module wishbone_mem_interconnect (
//Control Signals
input clk,
input rst,
//Master Signals
input i_m_we,
input i_m_stb,
input i_m_cyc,
input [3:0] i_m_sel,
input [31:0] i_m_adr,
input [31:0] i_m_dat,
output reg [31:0] o_m_dat,
output reg o_m_ack,
output reg o_m_int,
//Slave 0
output o_s0_we,
output o_s0_cyc,
output o_s0_stb,
output [3:0] o_s0_sel,
input i_s0_ack,
output [31:0] o_s0_dat,
input [31:0] i_s0_dat,
output [31:0] o_s0_adr,
input i_s0_int
);
parameter MEM_SEL_0 = 0;
parameter MEM_OFFSET_0 = 0;
parameter MEM_SIZE_0 = 8388607;
reg [31:0] mem_select;
always @(rst or i_m_adr or mem_select) begin
if (rst) begin
//nothing selected
mem_select <= 32'hFFFFFFFF;
end
else begin
if ((i_m_adr >= MEM_OFFSET_0) && (i_m_adr < (MEM_OFFSET_0 + MEM_SIZE_0))) begin
mem_select <= MEM_SEL_0;
end
else begin
mem_select <= 32'hFFFFFFFF;
end
end
end
//data in from slave
always @ (mem_select or i_s0_dat) begin
case (mem_select)
MEM_SEL_0: begin
o_m_dat <= i_s0_dat;
end
default: begin
o_m_dat <= 32'h0000;
end
endcase
end
//ack in from mem slave
always @ (mem_select or i_s0_ack) begin
case (mem_select)
MEM_SEL_0: begin
o_m_ack <= i_s0_ack;
end
default: begin
o_m_ack <= 1'h0;
end
endcase
end
//int in from slave
always @ (mem_select or i_s0_int) begin
case (mem_select)
MEM_SEL_0: begin
o_m_int <= i_s0_int;
end
default: begin
o_m_int <= 1'h0;
end
endcase
end
assign o_s0_we = (mem_select == MEM_SEL_0) ? i_m_we: 1'b0;
assign o_s0_stb = (mem_select == MEM_SEL_0) ? i_m_stb: 1'b0;
assign o_s0_sel = (mem_select == MEM_SEL_0) ? i_m_sel: 4'b0;
assign o_s0_cyc = (mem_select == MEM_SEL_0) ? i_m_cyc: 1'b0;
assign o_s0_adr = (mem_select == MEM_SEL_0) ? i_m_adr: 32'h0;
assign o_s0_dat = (mem_select == MEM_SEL_0) ? i_m_dat: 32'h0;
endmodule |
module wishbone_mem_interconnect (
//Control Signals
input clk,
input rst,
//Master Signals
input i_m_we,
input i_m_stb,
input i_m_cyc,
input [3:0] i_m_sel,
input [31:0] i_m_adr,
input [31:0] i_m_dat,
output reg [31:0] o_m_dat,
output reg o_m_ack,
output reg o_m_int,
//Slave 0
output o_s0_we,
output o_s0_cyc,
output o_s0_stb,
output [3:0] o_s0_sel,
input i_s0_ack,
output [31:0] o_s0_dat,
input [31:0] i_s0_dat,
output [31:0] o_s0_adr,
input i_s0_int
);
parameter MEM_SEL_0 = 0;
parameter MEM_OFFSET_0 = 0;
parameter MEM_SIZE_0 = 8388607;
reg [31:0] mem_select;
always @(rst or i_m_adr or mem_select) begin
if (rst) begin
//nothing selected
mem_select <= 32'hFFFFFFFF;
end
else begin
if ((i_m_adr >= MEM_OFFSET_0) && (i_m_adr < (MEM_OFFSET_0 + MEM_SIZE_0))) begin
mem_select <= MEM_SEL_0;
end
else begin
mem_select <= 32'hFFFFFFFF;
end
end
end
//data in from slave
always @ (mem_select or i_s0_dat) begin
case (mem_select)
MEM_SEL_0: begin
o_m_dat <= i_s0_dat;
end
default: begin
o_m_dat <= 32'h0000;
end
endcase
end
//ack in from mem slave
always @ (mem_select or i_s0_ack) begin
case (mem_select)
MEM_SEL_0: begin
o_m_ack <= i_s0_ack;
end
default: begin
o_m_ack <= 1'h0;
end
endcase
end
//int in from slave
always @ (mem_select or i_s0_int) begin
case (mem_select)
MEM_SEL_0: begin
o_m_int <= i_s0_int;
end
default: begin
o_m_int <= 1'h0;
end
endcase
end
assign o_s0_we = (mem_select == MEM_SEL_0) ? i_m_we: 1'b0;
assign o_s0_stb = (mem_select == MEM_SEL_0) ? i_m_stb: 1'b0;
assign o_s0_sel = (mem_select == MEM_SEL_0) ? i_m_sel: 4'b0;
assign o_s0_cyc = (mem_select == MEM_SEL_0) ? i_m_cyc: 1'b0;
assign o_s0_adr = (mem_select == MEM_SEL_0) ? i_m_adr: 32'h0;
assign o_s0_dat = (mem_select == MEM_SEL_0) ? i_m_dat: 32'h0;
endmodule |
module */
/* Internal counters that are used as Read/Write pointers to the fifo's that store all the transaction info on all channles.
This parameter is used to define the width of these pointers --> depending on Maximum outstanding transactions supported.
1-bit extra width than the no.of.bits needed to represent the outstanding transactions
Extra bit helps in generating the empty and full flags
*/
parameter int_wr_cntr_width = clogb2(max_wr_outstanding_transactions+1);
parameter int_rd_cntr_width = clogb2(max_rd_outstanding_transactions+1);
/* RESP data */
parameter rsp_fifo_bits = axi_rsp_width+id_bus_width;
parameter rsp_lsb = 0;
parameter rsp_msb = axi_rsp_width-1;
parameter rsp_id_lsb = rsp_msb + 1;
parameter rsp_id_msb = rsp_id_lsb + id_bus_width-1;
input S_RESETN;
output S_ARREADY;
output S_AWREADY;
output S_BVALID;
output S_RLAST;
output S_RVALID;
output S_WREADY;
output [axi_rsp_width-1:0] S_BRESP;
output [axi_rsp_width-1:0] S_RRESP;
output [data_bus_width-1:0] S_RDATA;
output [id_bus_width-1:0] S_BID;
output [id_bus_width-1:0] S_RID;
input S_ACLK;
input S_ARVALID;
input S_AWVALID;
input S_BREADY;
input S_RREADY;
input S_WLAST;
input S_WVALID;
input [axi_brst_type_width-1:0] S_ARBURST;
input [axi_lock_width-1:0] S_ARLOCK;
input [axi_size_width-1:0] S_ARSIZE;
input [axi_brst_type_width-1:0] S_AWBURST;
input [axi_lock_width-1:0] S_AWLOCK;
input [axi_size_width-1:0] S_AWSIZE;
input [axi_prot_width-1:0] S_ARPROT;
input [axi_prot_width-1:0] S_AWPROT;
input [address_bus_width-1:0] S_ARADDR;
input [address_bus_width-1:0] S_AWADDR;
input [data_bus_width-1:0] S_WDATA;
input [axi_cache_width-1:0] S_ARCACHE;
input [axi_cache_width-1:0] S_ARLEN;
input [axi_qos_width-1:0] S_ARQOS;
input [axi_cache_width-1:0] S_AWCACHE;
input [axi_len_width-1:0] S_AWLEN;
input [axi_qos_width-1:0] S_AWQOS;
input [(data_bus_width/8)-1:0] S_WSTRB;
input [id_bus_width-1:0] S_ARID;
input [id_bus_width-1:0] S_AWID;
input [id_bus_width-1:0] S_WID;
input SW_CLK;
input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM;
output reg WR_DATA_VALID_DDR, WR_DATA_VALID_OCM;
output reg [max_burst_bits-1:0] WR_DATA;
output reg [addr_width-1:0] WR_ADDR;
output reg [max_burst_bytes_width:0] WR_BYTES;
output reg RD_REQ_OCM, RD_REQ_DDR, RD_REQ_REG;
output reg [addr_width-1:0] RD_ADDR;
input [max_burst_bits-1:0] RD_DATA_DDR,RD_DATA_OCM, RD_DATA_REG;
output reg[max_burst_bytes_width:0] RD_BYTES;
input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR, RD_DATA_VALID_REG;
output reg [axi_qos_width-1:0] WR_QOS, RD_QOS;
wire net_ARVALID;
wire net_AWVALID;
wire net_WVALID;
real s_aclk_period;
cdn_axi3_slave_bfm #(slave_name,
data_bus_width,
address_bus_width,
id_bus_width,
slave_base_address,
(slave_high_address- slave_base_address),
max_outstanding_transactions,
0, ///MEMORY_MODEL_MODE,
exclusive_access_supported)
slave (.ACLK (S_ACLK),
.ARESETn (S_RESETN), /// confirm this
// Write Address Channel
.AWID (S_AWID),
.AWADDR (S_AWADDR),
.AWLEN (S_AWLEN),
.AWSIZE (S_AWSIZE),
.AWBURST (S_AWBURST),
.AWLOCK (S_AWLOCK),
.AWCACHE (S_AWCACHE),
.AWPROT (S_AWPROT),
.AWVALID (net_AWVALID),
.AWREADY (S_AWREADY),
// Write Data Channel Signals.
.WID (S_WID),
.WDATA (S_WDATA),
.WSTRB (S_WSTRB),
.WLAST (S_WLAST),
.WVALID (net_WVALID),
.WREADY (S_WREADY),
// Write Response Channel Signals.
.BID (S_BID),
.BRESP (S_BRESP),
.BVALID (S_BVALID),
.BREADY (S_BREADY),
// Read Address Channel Signals.
.ARID (S_ARID),
.ARADDR (S_ARADDR),
.ARLEN (S_ARLEN),
.ARSIZE (S_ARSIZE),
.ARBURST (S_ARBURST),
.ARLOCK (S_ARLOCK),
.ARCACHE (S_ARCACHE),
.ARPROT (S_ARPROT),
.ARVALID (net_ARVALID),
.ARREADY (S_ARREADY),
// Read Data Channel Signals.
.RID (S_RID),
.RDATA (S_RDATA),
.RRESP (S_RRESP),
.RLAST (S_RLAST),
.RVALID (S_RVALID),
.RREADY (S_RREADY));
/* Latency type and Debug/Error Control */
reg[1:0] latency_type = RANDOM_CASE;
reg DEBUG_INFO = 1;
reg STOP_ON_ERROR = 1'b1;
/* WR_FIFO stores 32-bit address, valid data and valid bytes for each AXI Write burst transaction */
reg [wr_fifo_data_bits-1:0] wr_fifo [0:max_wr_outstanding_transactions-1];
reg [int_wr_cntr_width-1:0] wr_fifo_wr_ptr = 0, wr_fifo_rd_ptr = 0;
wire wr_fifo_empty;
/* Store the awvalid receive time --- necessary for calculating the latency in sending the bresp*/
reg [7:0] aw_time_cnt = 0, bresp_time_cnt = 0;
real awvalid_receive_time[0:max_wr_outstanding_transactions]; // store the time when a new awvalid is received
reg awvalid_flag[0:max_wr_outstanding_transactions]; // indicates awvalid is received
/* Address Write Channel handshake*/
reg[int_wr_cntr_width-1:0] aw_cnt = 0;// count of awvalid
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] awsize [0:max_wr_outstanding_transactions-1];
reg [axi_prot_width-1:0] awprot [0:max_wr_outstanding_transactions-1];
reg [axi_lock_width-1:0] awlock [0:max_wr_outstanding_transactions-1];
reg [axi_cache_width-1:0] awcache [0:max_wr_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] awbrst [0:max_wr_outstanding_transactions-1];
reg [axi_len_width-1:0] awlen [0:max_wr_outstanding_transactions-1];
reg aw_flag [0:max_wr_outstanding_transactions-1];
reg [addr_width-1:0] awaddr [0:max_wr_outstanding_transactions-1];
reg [id_bus_width-1:0] awid [0:max_wr_outstanding_transactions-1];
reg [axi_qos_width-1:0] awqos [0:max_wr_outstanding_transactions-1];
wire aw_fifo_full; // indicates awvalid_fifo is full (max outstanding transactions reached)
/* internal fifos to store burst write data, ID & strobes*/
reg [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_wr_outstanding_transactions-1];
reg [max_burst_bytes_width:0] burst_valid_bytes [0:max_wr_outstanding_transactions-1]; /// total valid bytes received in a complete burst transfer
reg wlast_flag [0:max_wr_outstanding_transactions-1]; // flag to indicate WLAST received
wire wd_fifo_full;
/* Write Data Channel and Write Response handshake signals*/
reg [int_wr_cntr_width-1:0] wd_cnt = 0;
reg [(data_bus_width*axi_burst_len)-1:0] aligned_wr_data;
reg [addr_width-1:0] aligned_wr_addr;
reg [max_burst_bytes_width:0] valid_data_bytes;
reg [int_wr_cntr_width-1:0] wr_bresp_cnt = 0;
reg [axi_rsp_width-1:0] bresp;
reg [rsp_fifo_bits-1:0] fifo_bresp [0:max_wr_outstanding_transactions-1]; // store the ID and its corresponding response
reg enable_write_bresp;
reg [int_wr_cntr_width-1:0] rd_bresp_cnt = 0;
integer wr_latency_count;
reg wr_delayed;
wire bresp_fifo_empty;
/* states for managing read/write to WR_FIFO */
parameter SEND_DATA = 0, WAIT_ACK = 1;
reg state;
/* Qos*/
reg [axi_qos_width-1:0] ar_qos, aw_qos;
initial begin
if(DEBUG_INFO) begin
if(enable_this_port)
$display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, slave_name);
else
$display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, slave_name);
end
end
initial slave.set_disable_reset_value_checks(1);
initial begin
repeat(2) @(posedge S_ACLK);
if(!enable_this_port) begin
slave.set_channel_level_info(0);
slave.set_function_level_info(0);
end
slave.RESPONSE_TIMEOUT = 0;
end
/*--------------------------------------------------------------------------------*/
/* Set Latency type to be used */
task set_latency_type;
input[1:0] lat;
begin
if(enable_this_port)
latency_type = lat;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'Latency Profile' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set ARQoS to be used */
task set_arqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
ar_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'ARQOS' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set AWQoS to be used */
task set_awqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
aw_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'AWQOS' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* get the wr latency number */
function [31:0] get_wr_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_min; else get_wr_lat_number = gp_wr_min;
AVG_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_avg; else get_wr_lat_number = gp_wr_avg;
WORST_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_max; else get_wr_lat_number = gp_wr_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2'b00 : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%10+ acp_wr_min); else get_wr_lat_number = ($random()%10+ gp_wr_min);
2'b01 : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%40+ acp_wr_avg); else get_wr_lat_number = ($random()%40+ gp_wr_avg);
default : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%60+ acp_wr_max); else get_wr_lat_number = ($random()%60+ gp_wr_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* get the rd latency number */
function [31:0] get_rd_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_min; else get_rd_lat_number = gp_rd_min;
AVG_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_avg; else get_rd_lat_number = gp_rd_avg;
WORST_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_max; else get_rd_lat_number = gp_rd_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2'b00 : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%10+ acp_rd_min); else get_rd_lat_number = ($random()%10+ gp_rd_min);
2'b01 : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%40+ acp_rd_avg); else get_rd_lat_number = ($random()%40+ gp_rd_avg);
default : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%60+ acp_rd_max); else get_rd_lat_number = ($random()%60+ gp_rd_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Store the Clock cycle time period */
always@(S_RESETN)
begin
if(S_RESETN) begin
@(posedge S_ACLK);
s_aclk_period = $time;
@(posedge S_ACLK);
s_aclk_period = $time - s_aclk_period;
end
end
/*--------------------------------------------------------------------------------*/
/* Check for any WRITE/READs when this port is disabled */
always@(S_AWVALID or S_WVALID or S_ARVALID)
begin
if((S_AWVALID | S_WVALID | S_ARVALID) && !enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. AXI transaction is initiated on this port ...\nSimulation will halt ..",$time, DISP_ERR, slave_name);
$stop;
end
end
/*--------------------------------------------------------------------------------*/
assign net_ARVALID = enable_this_port ? S_ARVALID : 1'b0;
assign net_AWVALID = enable_this_port ? S_AWVALID : 1'b0;
assign net_WVALID = enable_this_port ? S_WVALID : 1'b0;
assign wr_fifo_empty = (wr_fifo_wr_ptr === wr_fifo_rd_ptr)?1'b1: 1'b0;
assign aw_fifo_full = ((aw_cnt[int_wr_cntr_width-1] !== rd_bresp_cnt[int_wr_cntr_width-1]) && (aw_cnt[int_wr_cntr_width-2:0] === rd_bresp_cnt[int_wr_cntr_width-2:0]))?1'b1 :1'b0; /// complete this
assign wd_fifo_full = ((wd_cnt[int_wr_cntr_width-1] !== rd_bresp_cnt[int_wr_cntr_width-1]) && (wd_cnt[int_wr_cntr_width-2:0] === rd_bresp_cnt[int_wr_cntr_width-2:0]))?1'b1 :1'b0; /// complete this
assign bresp_fifo_empty = (wr_bresp_cnt === rd_bresp_cnt)?1'b1:1'b0;
/* Store the awvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or S_AWID or S_AWADDR or S_AWVALID )
begin
if(!S_RESETN)
aw_time_cnt = 0;
else begin
if(S_AWVALID) begin
awvalid_receive_time[aw_time_cnt] = $time;
awvalid_flag[aw_time_cnt] = 1'b1;
aw_time_cnt = aw_time_cnt + 1;
if(aw_time_cnt === max_wr_outstanding_transactions) aw_time_cnt = 0;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_AWVALID && S_AWREADY) begin
if(S_AWQOS === 0) awqos[aw_cnt[int_wr_cntr_width-2:0]] = aw_qos;
else awqos[aw_cnt[int_wr_cntr_width-2:0]] = S_AWQOS;
end
end
/*--------------------------------------------------------------------------------*/
always@(aw_fifo_full)
begin
if(aw_fifo_full && DEBUG_INFO)
$display("[%0d] : %0s : %0s : Reached the maximum outstanding Write transactions limit (%0d). Blocking all future Write transactions until at least 1 of the outstanding Write transaction has completed.",$time, DISP_INFO, slave_name,max_wr_outstanding_transactions);
end
/*--------------------------------------------------------------------------------*/
/* Address Write Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
aw_cnt = 0;
end else begin
if(!aw_fifo_full) begin
slave.RECEIVE_WRITE_ADDRESS(0,
id_invalid,
awaddr[aw_cnt[int_wr_cntr_width-2:0]],
awlen[aw_cnt[int_wr_cntr_width-2:0]],
awsize[aw_cnt[int_wr_cntr_width-2:0]],
awbrst[aw_cnt[int_wr_cntr_width-2:0]],
awlock[aw_cnt[int_wr_cntr_width-2:0]],
awcache[aw_cnt[int_wr_cntr_width-2:0]],
awprot[aw_cnt[int_wr_cntr_width-2:0]],
awid[aw_cnt[int_wr_cntr_width-2:0]]); /// sampled valid ID.
aw_flag[aw_cnt[int_wr_cntr_width-2:0]] = 1;
aw_cnt = aw_cnt + 1;
if(aw_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
aw_cnt[int_wr_cntr_width-1] = ~aw_cnt[int_wr_cntr_width-1];
aw_cnt[int_wr_cntr_width-2:0] = 0;
end
end // if (!aw_fifo_full)
end /// if else
end /// always
/*--------------------------------------------------------------------------------*/
/* Write Data Channel Handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wd_cnt = 0;
end else begin
if(!wd_fifo_full && S_WVALID) begin
slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID,
burst_data[wd_cnt[int_wr_cntr_width-2:0]],
burst_valid_bytes[wd_cnt[int_wr_cntr_width-2:0]]);
wlast_flag[wd_cnt[int_wr_cntr_width-2:0]] = 1'b1;
wd_cnt = wd_cnt + 1;
if(wd_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
wd_cnt[int_wr_cntr_width-1] = ~wd_cnt[int_wr_cntr_width-1];
wd_cnt[int_wr_cntr_width-2:0] = 0;
end
end /// if
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
/* Align the wrap data for write transaction */
task automatic get_wrap_aligned_wr_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
output [addr_width-1:0] start_addr; /// aligned start address
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
wrp_data = wrp_data << ((data_bus_width*axi_burst_len) - (v_bytes*8));
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data << 8;
temp_data[7:0] = wrp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8];
wrp_data = wrp_data << 8;
wrp_bytes = wrp_bytes - 1;
end
wrp_bytes = addr - start_addr;
wrp_data = b_data << (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
/* Calculate the Response for each read/write transaction */
function [axi_rsp_width-1:0] calculate_resp;
input rd_wr; // indicates Read(1) or Write(0) transaction
input [addr_width-1:0] awaddr;
input [axi_prot_width-1:0] awprot;
reg [axi_rsp_width-1:0] rsp;
begin
rsp = AXI_OK;
/* Address Decode */
if(decode_address(awaddr) === INVALID_MEM_TYPE) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) ",$time, DISP_ERR, slave_name, awaddr);
end
if(!rd_wr && decode_address(awaddr) === REG_MEM) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Write to Register Map(0x%0h) is not supported ",$time, DISP_ERR, slave_name, awaddr);
end
if(secure_access_enabled && awprot[1])
rsp = AXI_DEC_ERR; // decode error
calculate_resp = rsp;
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Store the Write response for each write transaction */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wr_bresp_cnt = 0;
wr_fifo_wr_ptr = 0;
end else begin
enable_write_bresp = aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] && wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]];
/* calculate bresp only when AWVALID && WLAST is received */
if(enable_write_bresp) begin
aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] = 0;
wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] = 0;
bresp = calculate_resp(1'b0, awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]],awprot[wr_bresp_cnt[int_wr_cntr_width-2:0]]);
fifo_bresp[wr_bresp_cnt[int_wr_cntr_width-2:0]] = {awid[wr_bresp_cnt[int_wr_cntr_width-2:0]],bresp};
/* Fill WR data FIFO */
if(bresp === AXI_OK) begin
if(awbrst[wr_bresp_cnt[int_wr_cntr_width-2:0]] === AXI_WRAP) begin /// wrap type? then align the data
get_wrap_aligned_wr_data(aligned_wr_data,aligned_wr_addr, awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_data[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-2:0]]); /// gives wrapped start address
end else begin
aligned_wr_data = burst_data[wr_bresp_cnt[int_wr_cntr_width-2:0]];
aligned_wr_addr = awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]] ;
end
valid_data_bytes = burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-2:0]];
end else
valid_data_bytes = 0;
wr_fifo[wr_fifo_wr_ptr[int_wr_cntr_width-2:0]] = {awqos[wr_bresp_cnt[int_wr_cntr_width-2:0]], aligned_wr_data, aligned_wr_addr, valid_data_bytes};
wr_fifo_wr_ptr = wr_fifo_wr_ptr + 1;
wr_bresp_cnt = wr_bresp_cnt+1;
if(wr_bresp_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
wr_bresp_cnt[int_wr_cntr_width-1] = ~ wr_bresp_cnt[int_wr_cntr_width-1];
wr_bresp_cnt[int_wr_cntr_width-2:0] = 0;
end
end
end // else
end // always
/*--------------------------------------------------------------------------------*/
/* Send Write Response Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
rd_bresp_cnt = 0;
wr_latency_count = get_wr_lat_number(1);
wr_delayed = 0;
bresp_time_cnt = 0;
end else begin
wr_delayed = 1'b0;
if(awvalid_flag[bresp_time_cnt] && (($time - awvalid_receive_time[bresp_time_cnt])/s_aclk_period >= wr_latency_count))
wr_delayed = 1;
if(!bresp_fifo_empty && wr_delayed) begin
slave.SEND_WRITE_RESPONSE(fifo_bresp[rd_bresp_cnt[int_wr_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb], // ID
fifo_bresp[rd_bresp_cnt[int_wr_cntr_width-2:0]][rsp_msb : rsp_lsb] // Response
);
wr_delayed = 0;
awvalid_flag[bresp_time_cnt] = 1'b0;
bresp_time_cnt = bresp_time_cnt+1;
rd_bresp_cnt = rd_bresp_cnt + 1;
if(rd_bresp_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
rd_bresp_cnt[int_wr_cntr_width-1] = ~ rd_bresp_cnt[int_wr_cntr_width-1];
rd_bresp_cnt[int_wr_cntr_width-2:0] = 0;
end
if(bresp_time_cnt === max_wr_outstanding_transactions) begin
bresp_time_cnt = 0;
end
wr_latency_count = get_wr_lat_number(1);
end
end // else
end//always
/*--------------------------------------------------------------------------------*/
/* Reading from the wr_fifo */
always@(negedge S_RESETN or posedge SW_CLK) begin
if(!S_RESETN) begin
WR_DATA_VALID_DDR = 1'b0;
WR_DATA_VALID_OCM = 1'b0;
wr_fifo_rd_ptr = 0;
state = SEND_DATA;
WR_QOS = 0;
end else begin
case(state)
SEND_DATA :begin
state = SEND_DATA;
WR_DATA_VALID_OCM = 0;
WR_DATA_VALID_DDR = 0;
if(!wr_fifo_empty) begin
WR_DATA = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_data_msb : wr_data_lsb];
WR_ADDR = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_addr_msb : wr_addr_lsb];
WR_BYTES = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_bytes_msb : wr_bytes_lsb];
WR_QOS = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_qos_msb : wr_qos_lsb];
state = WAIT_ACK;
case (decode_address(wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_addr_msb : wr_addr_lsb]))
OCM_MEM : WR_DATA_VALID_OCM = 1;
DDR_MEM : WR_DATA_VALID_DDR = 1;
default : state = SEND_DATA;
endcase
wr_fifo_rd_ptr = wr_fifo_rd_ptr+1;
end
end
WAIT_ACK :begin
state = WAIT_ACK;
if(WR_DATA_ACK_OCM | WR_DATA_ACK_DDR) begin
WR_DATA_VALID_OCM = 1'b0;
WR_DATA_VALID_DDR = 1'b0;
state = SEND_DATA;
end
end
endcase
end
end
/*--------------------------------------------------------------------------------*/
/*-------------------------------- WRITE HANDSHAKE END ----------------------------------------*/
/*-------------------------------- READ HANDSHAKE ---------------------------------------------*/
/* READ CHANNELS */
/* Store the arvalid receive time --- necessary for calculating latency in sending the rresp latency */
reg [7:0] ar_time_cnt = 0,rresp_time_cnt = 0;
real arvalid_receive_time[0:max_rd_outstanding_transactions]; // store the time when a new arvalid is received
reg arvalid_flag[0:max_rd_outstanding_transactions]; // store the time when a new arvalid is received
reg [int_rd_cntr_width-1:0] ar_cnt = 0; // counter for arvalid info
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] arsize [0:max_rd_outstanding_transactions-1];
reg [axi_prot_width-1:0] arprot [0:max_rd_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] arbrst [0:max_rd_outstanding_transactions-1];
reg [axi_len_width-1:0] arlen [0:max_rd_outstanding_transactions-1];
reg [axi_cache_width-1:0] arcache [0:max_rd_outstanding_transactions-1];
reg [axi_lock_width-1:0] arlock [0:max_rd_outstanding_transactions-1];
reg ar_flag [0:max_rd_outstanding_transactions-1];
reg [addr_width-1:0] araddr [0:max_rd_outstanding_transactions-1];
reg [id_bus_width-1:0] arid [0:max_rd_outstanding_transactions-1];
reg [axi_qos_width-1:0] arqos [0:max_rd_outstanding_transactions-1];
wire ar_fifo_full; // indicates arvalid_fifo is full (max outstanding transactions reached)
reg [int_rd_cntr_width-1:0] rd_cnt = 0;
reg [int_rd_cntr_width-1:0] wr_rresp_cnt = 0;
reg [axi_rsp_width-1:0] rresp;
reg [rsp_fifo_bits-1:0] fifo_rresp [0:max_rd_outstanding_transactions-1]; // store the ID and its corresponding response
/* Send Read Response & Data Channel handshake */
integer rd_latency_count;
reg rd_delayed;
reg [max_burst_bits-1:0] read_fifo [0:max_rd_outstanding_transactions-1]; /// Store only AXI Burst Data ..
reg [int_rd_cntr_width-1:0] rd_fifo_wr_ptr = 0, rd_fifo_rd_ptr = 0;
wire read_fifo_full;
assign read_fifo_full = (rd_fifo_wr_ptr[int_rd_cntr_width-1] !== rd_fifo_rd_ptr[int_rd_cntr_width-1] && rd_fifo_wr_ptr[int_rd_cntr_width-2:0] === rd_fifo_rd_ptr[int_rd_cntr_width-2:0])?1'b1: 1'b0;
assign read_fifo_empty = (rd_fifo_wr_ptr === rd_fifo_rd_ptr)?1'b1: 1'b0;
assign ar_fifo_full = ((ar_cnt[int_rd_cntr_width-1] !== rd_cnt[int_rd_cntr_width-1]) && (ar_cnt[int_rd_cntr_width-2:0] === rd_cnt[int_rd_cntr_width-2:0]))?1'b1 :1'b0;
/* Store the arvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or S_ARID or S_ARADDR or S_ARVALID )
begin
if(!S_RESETN)
ar_time_cnt = 0;
else begin
if(S_ARVALID) begin
arvalid_receive_time[ar_time_cnt] = $time;
arvalid_flag[ar_time_cnt] = 1'b1;
ar_time_cnt = ar_time_cnt + 1;
if(ar_time_cnt === max_rd_outstanding_transactions)
ar_time_cnt = 0;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_ARVALID && S_ARREADY) begin
if(S_ARQOS === 0) arqos[aw_cnt[int_rd_cntr_width-2:0]] = ar_qos;
else arqos[aw_cnt[int_rd_cntr_width-2:0]] = S_ARQOS;
end
end
/*--------------------------------------------------------------------------------*/
always@(ar_fifo_full)
begin
if(ar_fifo_full && DEBUG_INFO)
$display("[%0d] : %0s : %0s : Reached the maximum outstanding Read transactions limit (%0d). Blocking all future Read transactions until at least 1 of the outstanding Read transaction has completed.",$time, DISP_INFO, slave_name,max_rd_outstanding_transactions);
end
/*--------------------------------------------------------------------------------*/
/* Address Read Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
ar_cnt = 0;
end else begin
if(!ar_fifo_full) begin
slave.RECEIVE_READ_ADDRESS(0,
id_invalid,
araddr[ar_cnt[int_rd_cntr_width-2:0]],
arlen[ar_cnt[int_rd_cntr_width-2:0]],
arsize[ar_cnt[int_rd_cntr_width-2:0]],
arbrst[ar_cnt[int_rd_cntr_width-2:0]],
arlock[ar_cnt[int_rd_cntr_width-2:0]],
arcache[ar_cnt[int_rd_cntr_width-2:0]],
arprot[ar_cnt[int_rd_cntr_width-2:0]],
arid[ar_cnt[int_rd_cntr_width-2:0]]); /// sampled valid ID.
ar_flag[ar_cnt[int_rd_cntr_width-2:0]] = 1'b1;
ar_cnt = ar_cnt+1;
if(ar_cnt[int_rd_cntr_width-2:0] === max_rd_outstanding_transactions-1) begin
ar_cnt[int_rd_cntr_width-1] = ~ ar_cnt[int_rd_cntr_width-1];
ar_cnt[int_rd_cntr_width-2:0] = 0;
end
end /// if(!ar_fifo_full)
end /// if else
end /// always*/
/*--------------------------------------------------------------------------------*/
/* Align Wrap data for read transaction*/
task automatic get_wrap_aligned_rd_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [addr_width-1:0] start_addr;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data >> 8;
temp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8] = wrp_data[7:0];
wrp_data = wrp_data >> 8;
wrp_bytes = wrp_bytes - 1;
end
temp_data = temp_data >> ((data_bus_width*axi_burst_len) - (v_bytes*8));
wrp_bytes = addr - start_addr;
wrp_data = b_data >> (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
parameter RD_DATA_REQ = 1'b0, WAIT_RD_VALID = 1'b1;
reg [addr_width-1:0] temp_read_address;
reg [max_burst_bytes_width:0] temp_rd_valid_bytes;
reg rd_fifo_state;
reg invalid_rd_req;
/* get the data from memory && also calculate the rresp*/
always@(negedge S_RESETN or posedge SW_CLK)
begin
if(!S_RESETN)begin
rd_fifo_wr_ptr = 0;
wr_rresp_cnt =0;
rd_fifo_state = RD_DATA_REQ;
temp_rd_valid_bytes = 0;
temp_read_address = 0;
RD_REQ_DDR = 0;
RD_REQ_OCM = 0;
RD_REQ_REG = 0;
RD_QOS = 0;
invalid_rd_req = 0;
end else begin
case(rd_fifo_state)
RD_DATA_REQ : begin
rd_fifo_state = RD_DATA_REQ;
RD_REQ_DDR = 0;
RD_REQ_OCM = 0;
RD_REQ_REG = 0;
RD_QOS = 0;
if(ar_flag[wr_rresp_cnt[int_rd_cntr_width-2:0]] && !read_fifo_full) begin
ar_flag[wr_rresp_cnt[int_rd_cntr_width-2:0]] = 0;
rresp = calculate_resp(1'b1, araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]],arprot[wr_rresp_cnt[int_rd_cntr_width-2:0]]);
fifo_rresp[wr_rresp_cnt[int_rd_cntr_width-2:0]] = {arid[wr_rresp_cnt[int_rd_cntr_width-2:0]],rresp};
temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_rd_cntr_width-2:0]]+1)*(2**arsize[wr_rresp_cnt[int_rd_cntr_width-2:0]]);//data_bus_width/8;
if(arbrst[wr_rresp_cnt[int_rd_cntr_width-2:0]] === AXI_WRAP) /// wrap begin
temp_read_address = (araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes;
else
temp_read_address = araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]];
if(rresp === AXI_OK) begin
case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]);
OCM_MEM : RD_REQ_OCM = 1;
DDR_MEM : RD_REQ_DDR = 1;
REG_MEM : RD_REQ_REG = 1;
default : invalid_rd_req = 1;
endcase
end else
invalid_rd_req = 1;
RD_QOS = arqos[wr_rresp_cnt[int_rd_cntr_width-2:0]];
RD_ADDR = temp_read_address; ///araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]];
RD_BYTES = temp_rd_valid_bytes;
rd_fifo_state = WAIT_RD_VALID;
wr_rresp_cnt = wr_rresp_cnt + 1;
if(wr_rresp_cnt[int_rd_cntr_width-2:0] === max_rd_outstanding_transactions-1) begin
wr_rresp_cnt[int_rd_cntr_width-1] = ~ wr_rresp_cnt[int_rd_cntr_width-1];
wr_rresp_cnt[int_rd_cntr_width-2:0] = 0;
end
end
end
WAIT_RD_VALID : begin
rd_fifo_state = WAIT_RD_VALID;
if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | RD_DATA_VALID_REG | invalid_rd_req) begin ///temp_dec == 2'b11) begin
if(RD_DATA_VALID_DDR)
read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_DDR;
else if(RD_DATA_VALID_OCM)
read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_OCM;
else if(RD_DATA_VALID_REG)
read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_REG;
else
read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = 0;
rd_fifo_wr_ptr = rd_fifo_wr_ptr + 1;
RD_REQ_DDR = 0;
RD_REQ_OCM = 0;
RD_REQ_REG = 0;
RD_QOS = 0;
invalid_rd_req = 0;
rd_fifo_state = RD_DATA_REQ;
end
end
endcase
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
reg[max_burst_bytes_width:0] rd_v_b;
reg [(data_bus_width*axi_burst_len)-1:0] temp_read_data;
reg [(data_bus_width*axi_burst_len)-1:0] temp_wrap_data;
reg[(axi_rsp_width*axi_burst_len)-1:0] temp_read_rsp;
/* Read Data Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN)begin
rd_fifo_rd_ptr = 0;
rd_cnt = 0;
rd_latency_count = get_rd_lat_number(1);
rd_delayed = 0;
rresp_time_cnt = 0;
rd_v_b = 0;
end else begin
if(arvalid_flag[rresp_time_cnt] && ((($time - arvalid_receive_time[rresp_time_cnt])/s_aclk_period) >= rd_latency_count))
rd_delayed = 1;
if(!read_fifo_empty && rd_delayed)begin
rd_delayed = 0;
arvalid_flag[rresp_time_cnt] = 1'b0;
rd_v_b = ((arlen[rd_cnt[int_rd_cntr_width-2:0]]+1)*(2**arsize[rd_cnt[int_rd_cntr_width-2:0]]));
temp_read_data = read_fifo[rd_fifo_rd_ptr[int_rd_cntr_width-2:0]];
rd_fifo_rd_ptr = rd_fifo_rd_ptr+1;
if(arbrst[rd_cnt[int_rd_cntr_width-2:0]]=== AXI_WRAP) begin
get_wrap_aligned_rd_data(temp_wrap_data, araddr[rd_cnt[int_rd_cntr_width-2:0]], temp_read_data, rd_v_b);
temp_read_data = temp_wrap_data;
end
temp_read_rsp = 0;
repeat(axi_burst_len) begin
temp_read_rsp = temp_read_rsp >> axi_rsp_width;
temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = fifo_rresp[rd_cnt[int_rd_cntr_width-2:0]][rsp_msb : rsp_lsb];
end
slave.SEND_READ_BURST_RESP_CTRL(arid[rd_cnt[int_rd_cntr_width-2:0]],
araddr[rd_cnt[int_rd_cntr_width-2:0]],
arlen[rd_cnt[int_rd_cntr_width-2:0]],
arsize[rd_cnt[int_rd_cntr_width-2:0]],
arbrst[rd_cnt[int_rd_cntr_width-2:0]],
temp_read_data,
temp_read_rsp);
rd_cnt = rd_cnt + 1;
rresp_time_cnt = rresp_time_cnt+1;
if(rresp_time_cnt === max_rd_outstanding_transactions) rresp_time_cnt = 0;
if(rd_cnt[int_rd_cntr_width-2:0] === (max_rd_outstanding_transactions-1)) begin
rd_cnt[int_rd_cntr_width-1] = ~ rd_cnt[int_rd_cntr_width-1];
rd_cnt[int_rd_cntr_width-2:0] = 0;
end
rd_latency_count = get_rd_lat_number(1);
end
end /// else
end /// always
endmodule |
module */
/* Internal counters that are used as Read/Write pointers to the fifo's that store all the transaction info on all channles.
This parameter is used to define the width of these pointers --> depending on Maximum outstanding transactions supported.
1-bit extra width than the no.of.bits needed to represent the outstanding transactions
Extra bit helps in generating the empty and full flags
*/
parameter int_wr_cntr_width = clogb2(max_wr_outstanding_transactions+1);
parameter int_rd_cntr_width = clogb2(max_rd_outstanding_transactions+1);
/* RESP data */
parameter rsp_fifo_bits = axi_rsp_width+id_bus_width;
parameter rsp_lsb = 0;
parameter rsp_msb = axi_rsp_width-1;
parameter rsp_id_lsb = rsp_msb + 1;
parameter rsp_id_msb = rsp_id_lsb + id_bus_width-1;
input S_RESETN;
output S_ARREADY;
output S_AWREADY;
output S_BVALID;
output S_RLAST;
output S_RVALID;
output S_WREADY;
output [axi_rsp_width-1:0] S_BRESP;
output [axi_rsp_width-1:0] S_RRESP;
output [data_bus_width-1:0] S_RDATA;
output [id_bus_width-1:0] S_BID;
output [id_bus_width-1:0] S_RID;
input S_ACLK;
input S_ARVALID;
input S_AWVALID;
input S_BREADY;
input S_RREADY;
input S_WLAST;
input S_WVALID;
input [axi_brst_type_width-1:0] S_ARBURST;
input [axi_lock_width-1:0] S_ARLOCK;
input [axi_size_width-1:0] S_ARSIZE;
input [axi_brst_type_width-1:0] S_AWBURST;
input [axi_lock_width-1:0] S_AWLOCK;
input [axi_size_width-1:0] S_AWSIZE;
input [axi_prot_width-1:0] S_ARPROT;
input [axi_prot_width-1:0] S_AWPROT;
input [address_bus_width-1:0] S_ARADDR;
input [address_bus_width-1:0] S_AWADDR;
input [data_bus_width-1:0] S_WDATA;
input [axi_cache_width-1:0] S_ARCACHE;
input [axi_cache_width-1:0] S_ARLEN;
input [axi_qos_width-1:0] S_ARQOS;
input [axi_cache_width-1:0] S_AWCACHE;
input [axi_len_width-1:0] S_AWLEN;
input [axi_qos_width-1:0] S_AWQOS;
input [(data_bus_width/8)-1:0] S_WSTRB;
input [id_bus_width-1:0] S_ARID;
input [id_bus_width-1:0] S_AWID;
input [id_bus_width-1:0] S_WID;
input SW_CLK;
input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM;
output reg WR_DATA_VALID_DDR, WR_DATA_VALID_OCM;
output reg [max_burst_bits-1:0] WR_DATA;
output reg [addr_width-1:0] WR_ADDR;
output reg [max_burst_bytes_width:0] WR_BYTES;
output reg RD_REQ_OCM, RD_REQ_DDR, RD_REQ_REG;
output reg [addr_width-1:0] RD_ADDR;
input [max_burst_bits-1:0] RD_DATA_DDR,RD_DATA_OCM, RD_DATA_REG;
output reg[max_burst_bytes_width:0] RD_BYTES;
input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR, RD_DATA_VALID_REG;
output reg [axi_qos_width-1:0] WR_QOS, RD_QOS;
wire net_ARVALID;
wire net_AWVALID;
wire net_WVALID;
real s_aclk_period;
cdn_axi3_slave_bfm #(slave_name,
data_bus_width,
address_bus_width,
id_bus_width,
slave_base_address,
(slave_high_address- slave_base_address),
max_outstanding_transactions,
0, ///MEMORY_MODEL_MODE,
exclusive_access_supported)
slave (.ACLK (S_ACLK),
.ARESETn (S_RESETN), /// confirm this
// Write Address Channel
.AWID (S_AWID),
.AWADDR (S_AWADDR),
.AWLEN (S_AWLEN),
.AWSIZE (S_AWSIZE),
.AWBURST (S_AWBURST),
.AWLOCK (S_AWLOCK),
.AWCACHE (S_AWCACHE),
.AWPROT (S_AWPROT),
.AWVALID (net_AWVALID),
.AWREADY (S_AWREADY),
// Write Data Channel Signals.
.WID (S_WID),
.WDATA (S_WDATA),
.WSTRB (S_WSTRB),
.WLAST (S_WLAST),
.WVALID (net_WVALID),
.WREADY (S_WREADY),
// Write Response Channel Signals.
.BID (S_BID),
.BRESP (S_BRESP),
.BVALID (S_BVALID),
.BREADY (S_BREADY),
// Read Address Channel Signals.
.ARID (S_ARID),
.ARADDR (S_ARADDR),
.ARLEN (S_ARLEN),
.ARSIZE (S_ARSIZE),
.ARBURST (S_ARBURST),
.ARLOCK (S_ARLOCK),
.ARCACHE (S_ARCACHE),
.ARPROT (S_ARPROT),
.ARVALID (net_ARVALID),
.ARREADY (S_ARREADY),
// Read Data Channel Signals.
.RID (S_RID),
.RDATA (S_RDATA),
.RRESP (S_RRESP),
.RLAST (S_RLAST),
.RVALID (S_RVALID),
.RREADY (S_RREADY));
/* Latency type and Debug/Error Control */
reg[1:0] latency_type = RANDOM_CASE;
reg DEBUG_INFO = 1;
reg STOP_ON_ERROR = 1'b1;
/* WR_FIFO stores 32-bit address, valid data and valid bytes for each AXI Write burst transaction */
reg [wr_fifo_data_bits-1:0] wr_fifo [0:max_wr_outstanding_transactions-1];
reg [int_wr_cntr_width-1:0] wr_fifo_wr_ptr = 0, wr_fifo_rd_ptr = 0;
wire wr_fifo_empty;
/* Store the awvalid receive time --- necessary for calculating the latency in sending the bresp*/
reg [7:0] aw_time_cnt = 0, bresp_time_cnt = 0;
real awvalid_receive_time[0:max_wr_outstanding_transactions]; // store the time when a new awvalid is received
reg awvalid_flag[0:max_wr_outstanding_transactions]; // indicates awvalid is received
/* Address Write Channel handshake*/
reg[int_wr_cntr_width-1:0] aw_cnt = 0;// count of awvalid
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] awsize [0:max_wr_outstanding_transactions-1];
reg [axi_prot_width-1:0] awprot [0:max_wr_outstanding_transactions-1];
reg [axi_lock_width-1:0] awlock [0:max_wr_outstanding_transactions-1];
reg [axi_cache_width-1:0] awcache [0:max_wr_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] awbrst [0:max_wr_outstanding_transactions-1];
reg [axi_len_width-1:0] awlen [0:max_wr_outstanding_transactions-1];
reg aw_flag [0:max_wr_outstanding_transactions-1];
reg [addr_width-1:0] awaddr [0:max_wr_outstanding_transactions-1];
reg [id_bus_width-1:0] awid [0:max_wr_outstanding_transactions-1];
reg [axi_qos_width-1:0] awqos [0:max_wr_outstanding_transactions-1];
wire aw_fifo_full; // indicates awvalid_fifo is full (max outstanding transactions reached)
/* internal fifos to store burst write data, ID & strobes*/
reg [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_wr_outstanding_transactions-1];
reg [max_burst_bytes_width:0] burst_valid_bytes [0:max_wr_outstanding_transactions-1]; /// total valid bytes received in a complete burst transfer
reg wlast_flag [0:max_wr_outstanding_transactions-1]; // flag to indicate WLAST received
wire wd_fifo_full;
/* Write Data Channel and Write Response handshake signals*/
reg [int_wr_cntr_width-1:0] wd_cnt = 0;
reg [(data_bus_width*axi_burst_len)-1:0] aligned_wr_data;
reg [addr_width-1:0] aligned_wr_addr;
reg [max_burst_bytes_width:0] valid_data_bytes;
reg [int_wr_cntr_width-1:0] wr_bresp_cnt = 0;
reg [axi_rsp_width-1:0] bresp;
reg [rsp_fifo_bits-1:0] fifo_bresp [0:max_wr_outstanding_transactions-1]; // store the ID and its corresponding response
reg enable_write_bresp;
reg [int_wr_cntr_width-1:0] rd_bresp_cnt = 0;
integer wr_latency_count;
reg wr_delayed;
wire bresp_fifo_empty;
/* states for managing read/write to WR_FIFO */
parameter SEND_DATA = 0, WAIT_ACK = 1;
reg state;
/* Qos*/
reg [axi_qos_width-1:0] ar_qos, aw_qos;
initial begin
if(DEBUG_INFO) begin
if(enable_this_port)
$display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, slave_name);
else
$display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, slave_name);
end
end
initial slave.set_disable_reset_value_checks(1);
initial begin
repeat(2) @(posedge S_ACLK);
if(!enable_this_port) begin
slave.set_channel_level_info(0);
slave.set_function_level_info(0);
end
slave.RESPONSE_TIMEOUT = 0;
end
/*--------------------------------------------------------------------------------*/
/* Set Latency type to be used */
task set_latency_type;
input[1:0] lat;
begin
if(enable_this_port)
latency_type = lat;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'Latency Profile' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set ARQoS to be used */
task set_arqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
ar_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'ARQOS' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set AWQoS to be used */
task set_awqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
aw_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'AWQOS' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* get the wr latency number */
function [31:0] get_wr_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_min; else get_wr_lat_number = gp_wr_min;
AVG_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_avg; else get_wr_lat_number = gp_wr_avg;
WORST_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_max; else get_wr_lat_number = gp_wr_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2'b00 : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%10+ acp_wr_min); else get_wr_lat_number = ($random()%10+ gp_wr_min);
2'b01 : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%40+ acp_wr_avg); else get_wr_lat_number = ($random()%40+ gp_wr_avg);
default : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%60+ acp_wr_max); else get_wr_lat_number = ($random()%60+ gp_wr_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* get the rd latency number */
function [31:0] get_rd_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_min; else get_rd_lat_number = gp_rd_min;
AVG_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_avg; else get_rd_lat_number = gp_rd_avg;
WORST_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_max; else get_rd_lat_number = gp_rd_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2'b00 : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%10+ acp_rd_min); else get_rd_lat_number = ($random()%10+ gp_rd_min);
2'b01 : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%40+ acp_rd_avg); else get_rd_lat_number = ($random()%40+ gp_rd_avg);
default : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%60+ acp_rd_max); else get_rd_lat_number = ($random()%60+ gp_rd_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Store the Clock cycle time period */
always@(S_RESETN)
begin
if(S_RESETN) begin
@(posedge S_ACLK);
s_aclk_period = $time;
@(posedge S_ACLK);
s_aclk_period = $time - s_aclk_period;
end
end
/*--------------------------------------------------------------------------------*/
/* Check for any WRITE/READs when this port is disabled */
always@(S_AWVALID or S_WVALID or S_ARVALID)
begin
if((S_AWVALID | S_WVALID | S_ARVALID) && !enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. AXI transaction is initiated on this port ...\nSimulation will halt ..",$time, DISP_ERR, slave_name);
$stop;
end
end
/*--------------------------------------------------------------------------------*/
assign net_ARVALID = enable_this_port ? S_ARVALID : 1'b0;
assign net_AWVALID = enable_this_port ? S_AWVALID : 1'b0;
assign net_WVALID = enable_this_port ? S_WVALID : 1'b0;
assign wr_fifo_empty = (wr_fifo_wr_ptr === wr_fifo_rd_ptr)?1'b1: 1'b0;
assign aw_fifo_full = ((aw_cnt[int_wr_cntr_width-1] !== rd_bresp_cnt[int_wr_cntr_width-1]) && (aw_cnt[int_wr_cntr_width-2:0] === rd_bresp_cnt[int_wr_cntr_width-2:0]))?1'b1 :1'b0; /// complete this
assign wd_fifo_full = ((wd_cnt[int_wr_cntr_width-1] !== rd_bresp_cnt[int_wr_cntr_width-1]) && (wd_cnt[int_wr_cntr_width-2:0] === rd_bresp_cnt[int_wr_cntr_width-2:0]))?1'b1 :1'b0; /// complete this
assign bresp_fifo_empty = (wr_bresp_cnt === rd_bresp_cnt)?1'b1:1'b0;
/* Store the awvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or S_AWID or S_AWADDR or S_AWVALID )
begin
if(!S_RESETN)
aw_time_cnt = 0;
else begin
if(S_AWVALID) begin
awvalid_receive_time[aw_time_cnt] = $time;
awvalid_flag[aw_time_cnt] = 1'b1;
aw_time_cnt = aw_time_cnt + 1;
if(aw_time_cnt === max_wr_outstanding_transactions) aw_time_cnt = 0;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_AWVALID && S_AWREADY) begin
if(S_AWQOS === 0) awqos[aw_cnt[int_wr_cntr_width-2:0]] = aw_qos;
else awqos[aw_cnt[int_wr_cntr_width-2:0]] = S_AWQOS;
end
end
/*--------------------------------------------------------------------------------*/
always@(aw_fifo_full)
begin
if(aw_fifo_full && DEBUG_INFO)
$display("[%0d] : %0s : %0s : Reached the maximum outstanding Write transactions limit (%0d). Blocking all future Write transactions until at least 1 of the outstanding Write transaction has completed.",$time, DISP_INFO, slave_name,max_wr_outstanding_transactions);
end
/*--------------------------------------------------------------------------------*/
/* Address Write Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
aw_cnt = 0;
end else begin
if(!aw_fifo_full) begin
slave.RECEIVE_WRITE_ADDRESS(0,
id_invalid,
awaddr[aw_cnt[int_wr_cntr_width-2:0]],
awlen[aw_cnt[int_wr_cntr_width-2:0]],
awsize[aw_cnt[int_wr_cntr_width-2:0]],
awbrst[aw_cnt[int_wr_cntr_width-2:0]],
awlock[aw_cnt[int_wr_cntr_width-2:0]],
awcache[aw_cnt[int_wr_cntr_width-2:0]],
awprot[aw_cnt[int_wr_cntr_width-2:0]],
awid[aw_cnt[int_wr_cntr_width-2:0]]); /// sampled valid ID.
aw_flag[aw_cnt[int_wr_cntr_width-2:0]] = 1;
aw_cnt = aw_cnt + 1;
if(aw_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
aw_cnt[int_wr_cntr_width-1] = ~aw_cnt[int_wr_cntr_width-1];
aw_cnt[int_wr_cntr_width-2:0] = 0;
end
end // if (!aw_fifo_full)
end /// if else
end /// always
/*--------------------------------------------------------------------------------*/
/* Write Data Channel Handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wd_cnt = 0;
end else begin
if(!wd_fifo_full && S_WVALID) begin
slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID,
burst_data[wd_cnt[int_wr_cntr_width-2:0]],
burst_valid_bytes[wd_cnt[int_wr_cntr_width-2:0]]);
wlast_flag[wd_cnt[int_wr_cntr_width-2:0]] = 1'b1;
wd_cnt = wd_cnt + 1;
if(wd_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
wd_cnt[int_wr_cntr_width-1] = ~wd_cnt[int_wr_cntr_width-1];
wd_cnt[int_wr_cntr_width-2:0] = 0;
end
end /// if
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
/* Align the wrap data for write transaction */
task automatic get_wrap_aligned_wr_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
output [addr_width-1:0] start_addr; /// aligned start address
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
wrp_data = wrp_data << ((data_bus_width*axi_burst_len) - (v_bytes*8));
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data << 8;
temp_data[7:0] = wrp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8];
wrp_data = wrp_data << 8;
wrp_bytes = wrp_bytes - 1;
end
wrp_bytes = addr - start_addr;
wrp_data = b_data << (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
/* Calculate the Response for each read/write transaction */
function [axi_rsp_width-1:0] calculate_resp;
input rd_wr; // indicates Read(1) or Write(0) transaction
input [addr_width-1:0] awaddr;
input [axi_prot_width-1:0] awprot;
reg [axi_rsp_width-1:0] rsp;
begin
rsp = AXI_OK;
/* Address Decode */
if(decode_address(awaddr) === INVALID_MEM_TYPE) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) ",$time, DISP_ERR, slave_name, awaddr);
end
if(!rd_wr && decode_address(awaddr) === REG_MEM) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Write to Register Map(0x%0h) is not supported ",$time, DISP_ERR, slave_name, awaddr);
end
if(secure_access_enabled && awprot[1])
rsp = AXI_DEC_ERR; // decode error
calculate_resp = rsp;
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Store the Write response for each write transaction */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wr_bresp_cnt = 0;
wr_fifo_wr_ptr = 0;
end else begin
enable_write_bresp = aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] && wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]];
/* calculate bresp only when AWVALID && WLAST is received */
if(enable_write_bresp) begin
aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] = 0;
wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] = 0;
bresp = calculate_resp(1'b0, awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]],awprot[wr_bresp_cnt[int_wr_cntr_width-2:0]]);
fifo_bresp[wr_bresp_cnt[int_wr_cntr_width-2:0]] = {awid[wr_bresp_cnt[int_wr_cntr_width-2:0]],bresp};
/* Fill WR data FIFO */
if(bresp === AXI_OK) begin
if(awbrst[wr_bresp_cnt[int_wr_cntr_width-2:0]] === AXI_WRAP) begin /// wrap type? then align the data
get_wrap_aligned_wr_data(aligned_wr_data,aligned_wr_addr, awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_data[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-2:0]]); /// gives wrapped start address
end else begin
aligned_wr_data = burst_data[wr_bresp_cnt[int_wr_cntr_width-2:0]];
aligned_wr_addr = awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]] ;
end
valid_data_bytes = burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-2:0]];
end else
valid_data_bytes = 0;
wr_fifo[wr_fifo_wr_ptr[int_wr_cntr_width-2:0]] = {awqos[wr_bresp_cnt[int_wr_cntr_width-2:0]], aligned_wr_data, aligned_wr_addr, valid_data_bytes};
wr_fifo_wr_ptr = wr_fifo_wr_ptr + 1;
wr_bresp_cnt = wr_bresp_cnt+1;
if(wr_bresp_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
wr_bresp_cnt[int_wr_cntr_width-1] = ~ wr_bresp_cnt[int_wr_cntr_width-1];
wr_bresp_cnt[int_wr_cntr_width-2:0] = 0;
end
end
end // else
end // always
/*--------------------------------------------------------------------------------*/
/* Send Write Response Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
rd_bresp_cnt = 0;
wr_latency_count = get_wr_lat_number(1);
wr_delayed = 0;
bresp_time_cnt = 0;
end else begin
wr_delayed = 1'b0;
if(awvalid_flag[bresp_time_cnt] && (($time - awvalid_receive_time[bresp_time_cnt])/s_aclk_period >= wr_latency_count))
wr_delayed = 1;
if(!bresp_fifo_empty && wr_delayed) begin
slave.SEND_WRITE_RESPONSE(fifo_bresp[rd_bresp_cnt[int_wr_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb], // ID
fifo_bresp[rd_bresp_cnt[int_wr_cntr_width-2:0]][rsp_msb : rsp_lsb] // Response
);
wr_delayed = 0;
awvalid_flag[bresp_time_cnt] = 1'b0;
bresp_time_cnt = bresp_time_cnt+1;
rd_bresp_cnt = rd_bresp_cnt + 1;
if(rd_bresp_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
rd_bresp_cnt[int_wr_cntr_width-1] = ~ rd_bresp_cnt[int_wr_cntr_width-1];
rd_bresp_cnt[int_wr_cntr_width-2:0] = 0;
end
if(bresp_time_cnt === max_wr_outstanding_transactions) begin
bresp_time_cnt = 0;
end
wr_latency_count = get_wr_lat_number(1);
end
end // else
end//always
/*--------------------------------------------------------------------------------*/
/* Reading from the wr_fifo */
always@(negedge S_RESETN or posedge SW_CLK) begin
if(!S_RESETN) begin
WR_DATA_VALID_DDR = 1'b0;
WR_DATA_VALID_OCM = 1'b0;
wr_fifo_rd_ptr = 0;
state = SEND_DATA;
WR_QOS = 0;
end else begin
case(state)
SEND_DATA :begin
state = SEND_DATA;
WR_DATA_VALID_OCM = 0;
WR_DATA_VALID_DDR = 0;
if(!wr_fifo_empty) begin
WR_DATA = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_data_msb : wr_data_lsb];
WR_ADDR = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_addr_msb : wr_addr_lsb];
WR_BYTES = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_bytes_msb : wr_bytes_lsb];
WR_QOS = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_qos_msb : wr_qos_lsb];
state = WAIT_ACK;
case (decode_address(wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_addr_msb : wr_addr_lsb]))
OCM_MEM : WR_DATA_VALID_OCM = 1;
DDR_MEM : WR_DATA_VALID_DDR = 1;
default : state = SEND_DATA;
endcase
wr_fifo_rd_ptr = wr_fifo_rd_ptr+1;
end
end
WAIT_ACK :begin
state = WAIT_ACK;
if(WR_DATA_ACK_OCM | WR_DATA_ACK_DDR) begin
WR_DATA_VALID_OCM = 1'b0;
WR_DATA_VALID_DDR = 1'b0;
state = SEND_DATA;
end
end
endcase
end
end
/*--------------------------------------------------------------------------------*/
/*-------------------------------- WRITE HANDSHAKE END ----------------------------------------*/
/*-------------------------------- READ HANDSHAKE ---------------------------------------------*/
/* READ CHANNELS */
/* Store the arvalid receive time --- necessary for calculating latency in sending the rresp latency */
reg [7:0] ar_time_cnt = 0,rresp_time_cnt = 0;
real arvalid_receive_time[0:max_rd_outstanding_transactions]; // store the time when a new arvalid is received
reg arvalid_flag[0:max_rd_outstanding_transactions]; // store the time when a new arvalid is received
reg [int_rd_cntr_width-1:0] ar_cnt = 0; // counter for arvalid info
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] arsize [0:max_rd_outstanding_transactions-1];
reg [axi_prot_width-1:0] arprot [0:max_rd_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] arbrst [0:max_rd_outstanding_transactions-1];
reg [axi_len_width-1:0] arlen [0:max_rd_outstanding_transactions-1];
reg [axi_cache_width-1:0] arcache [0:max_rd_outstanding_transactions-1];
reg [axi_lock_width-1:0] arlock [0:max_rd_outstanding_transactions-1];
reg ar_flag [0:max_rd_outstanding_transactions-1];
reg [addr_width-1:0] araddr [0:max_rd_outstanding_transactions-1];
reg [id_bus_width-1:0] arid [0:max_rd_outstanding_transactions-1];
reg [axi_qos_width-1:0] arqos [0:max_rd_outstanding_transactions-1];
wire ar_fifo_full; // indicates arvalid_fifo is full (max outstanding transactions reached)
reg [int_rd_cntr_width-1:0] rd_cnt = 0;
reg [int_rd_cntr_width-1:0] wr_rresp_cnt = 0;
reg [axi_rsp_width-1:0] rresp;
reg [rsp_fifo_bits-1:0] fifo_rresp [0:max_rd_outstanding_transactions-1]; // store the ID and its corresponding response
/* Send Read Response & Data Channel handshake */
integer rd_latency_count;
reg rd_delayed;
reg [max_burst_bits-1:0] read_fifo [0:max_rd_outstanding_transactions-1]; /// Store only AXI Burst Data ..
reg [int_rd_cntr_width-1:0] rd_fifo_wr_ptr = 0, rd_fifo_rd_ptr = 0;
wire read_fifo_full;
assign read_fifo_full = (rd_fifo_wr_ptr[int_rd_cntr_width-1] !== rd_fifo_rd_ptr[int_rd_cntr_width-1] && rd_fifo_wr_ptr[int_rd_cntr_width-2:0] === rd_fifo_rd_ptr[int_rd_cntr_width-2:0])?1'b1: 1'b0;
assign read_fifo_empty = (rd_fifo_wr_ptr === rd_fifo_rd_ptr)?1'b1: 1'b0;
assign ar_fifo_full = ((ar_cnt[int_rd_cntr_width-1] !== rd_cnt[int_rd_cntr_width-1]) && (ar_cnt[int_rd_cntr_width-2:0] === rd_cnt[int_rd_cntr_width-2:0]))?1'b1 :1'b0;
/* Store the arvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or S_ARID or S_ARADDR or S_ARVALID )
begin
if(!S_RESETN)
ar_time_cnt = 0;
else begin
if(S_ARVALID) begin
arvalid_receive_time[ar_time_cnt] = $time;
arvalid_flag[ar_time_cnt] = 1'b1;
ar_time_cnt = ar_time_cnt + 1;
if(ar_time_cnt === max_rd_outstanding_transactions)
ar_time_cnt = 0;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_ARVALID && S_ARREADY) begin
if(S_ARQOS === 0) arqos[aw_cnt[int_rd_cntr_width-2:0]] = ar_qos;
else arqos[aw_cnt[int_rd_cntr_width-2:0]] = S_ARQOS;
end
end
/*--------------------------------------------------------------------------------*/
always@(ar_fifo_full)
begin
if(ar_fifo_full && DEBUG_INFO)
$display("[%0d] : %0s : %0s : Reached the maximum outstanding Read transactions limit (%0d). Blocking all future Read transactions until at least 1 of the outstanding Read transaction has completed.",$time, DISP_INFO, slave_name,max_rd_outstanding_transactions);
end
/*--------------------------------------------------------------------------------*/
/* Address Read Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
ar_cnt = 0;
end else begin
if(!ar_fifo_full) begin
slave.RECEIVE_READ_ADDRESS(0,
id_invalid,
araddr[ar_cnt[int_rd_cntr_width-2:0]],
arlen[ar_cnt[int_rd_cntr_width-2:0]],
arsize[ar_cnt[int_rd_cntr_width-2:0]],
arbrst[ar_cnt[int_rd_cntr_width-2:0]],
arlock[ar_cnt[int_rd_cntr_width-2:0]],
arcache[ar_cnt[int_rd_cntr_width-2:0]],
arprot[ar_cnt[int_rd_cntr_width-2:0]],
arid[ar_cnt[int_rd_cntr_width-2:0]]); /// sampled valid ID.
ar_flag[ar_cnt[int_rd_cntr_width-2:0]] = 1'b1;
ar_cnt = ar_cnt+1;
if(ar_cnt[int_rd_cntr_width-2:0] === max_rd_outstanding_transactions-1) begin
ar_cnt[int_rd_cntr_width-1] = ~ ar_cnt[int_rd_cntr_width-1];
ar_cnt[int_rd_cntr_width-2:0] = 0;
end
end /// if(!ar_fifo_full)
end /// if else
end /// always*/
/*--------------------------------------------------------------------------------*/
/* Align Wrap data for read transaction*/
task automatic get_wrap_aligned_rd_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [addr_width-1:0] start_addr;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data >> 8;
temp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8] = wrp_data[7:0];
wrp_data = wrp_data >> 8;
wrp_bytes = wrp_bytes - 1;
end
temp_data = temp_data >> ((data_bus_width*axi_burst_len) - (v_bytes*8));
wrp_bytes = addr - start_addr;
wrp_data = b_data >> (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
parameter RD_DATA_REQ = 1'b0, WAIT_RD_VALID = 1'b1;
reg [addr_width-1:0] temp_read_address;
reg [max_burst_bytes_width:0] temp_rd_valid_bytes;
reg rd_fifo_state;
reg invalid_rd_req;
/* get the data from memory && also calculate the rresp*/
always@(negedge S_RESETN or posedge SW_CLK)
begin
if(!S_RESETN)begin
rd_fifo_wr_ptr = 0;
wr_rresp_cnt =0;
rd_fifo_state = RD_DATA_REQ;
temp_rd_valid_bytes = 0;
temp_read_address = 0;
RD_REQ_DDR = 0;
RD_REQ_OCM = 0;
RD_REQ_REG = 0;
RD_QOS = 0;
invalid_rd_req = 0;
end else begin
case(rd_fifo_state)
RD_DATA_REQ : begin
rd_fifo_state = RD_DATA_REQ;
RD_REQ_DDR = 0;
RD_REQ_OCM = 0;
RD_REQ_REG = 0;
RD_QOS = 0;
if(ar_flag[wr_rresp_cnt[int_rd_cntr_width-2:0]] && !read_fifo_full) begin
ar_flag[wr_rresp_cnt[int_rd_cntr_width-2:0]] = 0;
rresp = calculate_resp(1'b1, araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]],arprot[wr_rresp_cnt[int_rd_cntr_width-2:0]]);
fifo_rresp[wr_rresp_cnt[int_rd_cntr_width-2:0]] = {arid[wr_rresp_cnt[int_rd_cntr_width-2:0]],rresp};
temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_rd_cntr_width-2:0]]+1)*(2**arsize[wr_rresp_cnt[int_rd_cntr_width-2:0]]);//data_bus_width/8;
if(arbrst[wr_rresp_cnt[int_rd_cntr_width-2:0]] === AXI_WRAP) /// wrap begin
temp_read_address = (araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes;
else
temp_read_address = araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]];
if(rresp === AXI_OK) begin
case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]);
OCM_MEM : RD_REQ_OCM = 1;
DDR_MEM : RD_REQ_DDR = 1;
REG_MEM : RD_REQ_REG = 1;
default : invalid_rd_req = 1;
endcase
end else
invalid_rd_req = 1;
RD_QOS = arqos[wr_rresp_cnt[int_rd_cntr_width-2:0]];
RD_ADDR = temp_read_address; ///araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]];
RD_BYTES = temp_rd_valid_bytes;
rd_fifo_state = WAIT_RD_VALID;
wr_rresp_cnt = wr_rresp_cnt + 1;
if(wr_rresp_cnt[int_rd_cntr_width-2:0] === max_rd_outstanding_transactions-1) begin
wr_rresp_cnt[int_rd_cntr_width-1] = ~ wr_rresp_cnt[int_rd_cntr_width-1];
wr_rresp_cnt[int_rd_cntr_width-2:0] = 0;
end
end
end
WAIT_RD_VALID : begin
rd_fifo_state = WAIT_RD_VALID;
if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | RD_DATA_VALID_REG | invalid_rd_req) begin ///temp_dec == 2'b11) begin
if(RD_DATA_VALID_DDR)
read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_DDR;
else if(RD_DATA_VALID_OCM)
read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_OCM;
else if(RD_DATA_VALID_REG)
read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_REG;
else
read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = 0;
rd_fifo_wr_ptr = rd_fifo_wr_ptr + 1;
RD_REQ_DDR = 0;
RD_REQ_OCM = 0;
RD_REQ_REG = 0;
RD_QOS = 0;
invalid_rd_req = 0;
rd_fifo_state = RD_DATA_REQ;
end
end
endcase
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
reg[max_burst_bytes_width:0] rd_v_b;
reg [(data_bus_width*axi_burst_len)-1:0] temp_read_data;
reg [(data_bus_width*axi_burst_len)-1:0] temp_wrap_data;
reg[(axi_rsp_width*axi_burst_len)-1:0] temp_read_rsp;
/* Read Data Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN)begin
rd_fifo_rd_ptr = 0;
rd_cnt = 0;
rd_latency_count = get_rd_lat_number(1);
rd_delayed = 0;
rresp_time_cnt = 0;
rd_v_b = 0;
end else begin
if(arvalid_flag[rresp_time_cnt] && ((($time - arvalid_receive_time[rresp_time_cnt])/s_aclk_period) >= rd_latency_count))
rd_delayed = 1;
if(!read_fifo_empty && rd_delayed)begin
rd_delayed = 0;
arvalid_flag[rresp_time_cnt] = 1'b0;
rd_v_b = ((arlen[rd_cnt[int_rd_cntr_width-2:0]]+1)*(2**arsize[rd_cnt[int_rd_cntr_width-2:0]]));
temp_read_data = read_fifo[rd_fifo_rd_ptr[int_rd_cntr_width-2:0]];
rd_fifo_rd_ptr = rd_fifo_rd_ptr+1;
if(arbrst[rd_cnt[int_rd_cntr_width-2:0]]=== AXI_WRAP) begin
get_wrap_aligned_rd_data(temp_wrap_data, araddr[rd_cnt[int_rd_cntr_width-2:0]], temp_read_data, rd_v_b);
temp_read_data = temp_wrap_data;
end
temp_read_rsp = 0;
repeat(axi_burst_len) begin
temp_read_rsp = temp_read_rsp >> axi_rsp_width;
temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = fifo_rresp[rd_cnt[int_rd_cntr_width-2:0]][rsp_msb : rsp_lsb];
end
slave.SEND_READ_BURST_RESP_CTRL(arid[rd_cnt[int_rd_cntr_width-2:0]],
araddr[rd_cnt[int_rd_cntr_width-2:0]],
arlen[rd_cnt[int_rd_cntr_width-2:0]],
arsize[rd_cnt[int_rd_cntr_width-2:0]],
arbrst[rd_cnt[int_rd_cntr_width-2:0]],
temp_read_data,
temp_read_rsp);
rd_cnt = rd_cnt + 1;
rresp_time_cnt = rresp_time_cnt+1;
if(rresp_time_cnt === max_rd_outstanding_transactions) rresp_time_cnt = 0;
if(rd_cnt[int_rd_cntr_width-2:0] === (max_rd_outstanding_transactions-1)) begin
rd_cnt[int_rd_cntr_width-1] = ~ rd_cnt[int_rd_cntr_width-1];
rd_cnt[int_rd_cntr_width-2:0] = 0;
end
rd_latency_count = get_rd_lat_number(1);
end
end /// else
end /// always
endmodule |
module generic_baseblocks_v2_1_command_fifo #
(
parameter C_FAMILY = "virtex6",
parameter integer C_ENABLE_S_VALID_CARRY = 0,
parameter integer C_ENABLE_REGISTERED_OUTPUT = 0,
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [4:5].
parameter integer C_FIFO_WIDTH = 64 // Width of payload [1:512]
)
(
// Global inputs
input wire ACLK, // Clock
input wire ARESET, // Reset
// Information
output wire EMPTY, // FIFO empty (all stages)
// Slave Port
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)
input wire S_VALID, // FIFO push
output wire S_READY, // FIFO not full
// Master Port
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload
output wire M_VALID, // FIFO not empty
input wire M_READY // FIFO pop
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for data vector.
genvar addr_cnt;
genvar bit_cnt;
integer index;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIFO_DEPTH_LOG-1:0] addr;
wire buffer_Full;
wire buffer_Empty;
wire next_Data_Exists;
reg data_Exists_I;
wire valid_Write;
wire new_write;
wire [C_FIFO_DEPTH_LOG-1:0] hsum_A;
wire [C_FIFO_DEPTH_LOG-1:0] sum_A;
wire [C_FIFO_DEPTH_LOG-1:0] addr_cy;
wire buffer_full_early;
wire [C_FIFO_WIDTH-1:0] M_MESG_I; // Payload
wire M_VALID_I; // FIFO not empty
wire M_READY_I; // FIFO pop
/////////////////////////////////////////////////////////////////////////////
// Create Flags
/////////////////////////////////////////////////////////////////////////////
assign buffer_full_early = ( (addr == {{C_FIFO_DEPTH_LOG-1{1'b1}}, 1'b0}) & valid_Write & ~M_READY_I ) |
( buffer_Full & ~M_READY_I );
assign S_READY = ~buffer_Full;
assign buffer_Empty = (addr == {C_FIFO_DEPTH_LOG{1'b0}});
assign next_Data_Exists = (data_Exists_I & ~buffer_Empty) |
(buffer_Empty & S_VALID) |
(data_Exists_I & ~(M_READY_I & data_Exists_I));
always @ (posedge ACLK) begin
if (ARESET) begin
data_Exists_I <= 1'b0;
end else begin
data_Exists_I <= next_Data_Exists;
end
end
assign M_VALID_I = data_Exists_I;
// Select RTL or FPGA optimized instatiations for critical parts.
generate
if ( C_FAMILY == "rtl" || C_ENABLE_S_VALID_CARRY == 0 ) begin : USE_RTL_VALID_WRITE
reg buffer_Full_q;
assign valid_Write = S_VALID & ~buffer_Full;
assign new_write = (S_VALID | ~buffer_Empty);
assign addr_cy[0] = valid_Write;
always @ (posedge ACLK) begin
if (ARESET) begin
buffer_Full_q <= 1'b0;
end else if ( data_Exists_I ) begin
buffer_Full_q <= buffer_full_early;
end
end
assign buffer_Full = buffer_Full_q;
end else begin : USE_FPGA_VALID_WRITE
wire s_valid_dummy1;
wire s_valid_dummy2;
wire sel_s_valid;
wire sel_new_write;
wire valid_Write_dummy1;
wire valid_Write_dummy2;
assign sel_s_valid = ~buffer_Full;
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) s_valid_dummy_inst1
(
.CIN(S_VALID),
.S(1'b1),
.COUT(s_valid_dummy1)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) s_valid_dummy_inst2
(
.CIN(s_valid_dummy1),
.S(1'b1),
.COUT(s_valid_dummy2)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_inst
(
.CIN(s_valid_dummy2),
.S(sel_s_valid),
.COUT(valid_Write)
);
assign sel_new_write = ~buffer_Empty;
generic_baseblocks_v2_1_carry_latch_or #
(
.C_FAMILY(C_FAMILY)
) new_write_inst
(
.CIN(valid_Write),
.I(sel_new_write),
.O(new_write)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst1
(
.CIN(valid_Write),
.S(1'b1),
.COUT(valid_Write_dummy1)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst2
(
.CIN(valid_Write_dummy1),
.S(1'b1),
.COUT(valid_Write_dummy2)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst3
(
.CIN(valid_Write_dummy2),
.S(1'b1),
.COUT(addr_cy[0])
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_I1 (
.Q(buffer_Full), // Data output
.C(ACLK), // Clock input
.CE(data_Exists_I), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(buffer_full_early) // Data input
);
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Create address pointer
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_ADDR
reg [C_FIFO_DEPTH_LOG-1:0] addr_q;
always @ (posedge ACLK) begin
if (ARESET) begin
addr_q <= {C_FIFO_DEPTH_LOG{1'b0}};
end else if ( data_Exists_I ) begin
if ( valid_Write & ~(M_READY_I & data_Exists_I) ) begin
addr_q <= addr_q + 1'b1;
end else if ( ~valid_Write & (M_READY_I & data_Exists_I) & ~buffer_Empty ) begin
addr_q <= addr_q - 1'b1;
end
else begin
addr_q <= addr_q;
end
end
else begin
addr_q <= addr_q;
end
end
assign addr = addr_q;
end else begin : USE_FPGA_ADDR
for (addr_cnt = 0; addr_cnt < C_FIFO_DEPTH_LOG ; addr_cnt = addr_cnt + 1) begin : ADDR_GEN
assign hsum_A[addr_cnt] = ((M_READY_I & data_Exists_I) ^ addr[addr_cnt]) & new_write;
// Don't need the last muxcy, addr_cy(last) is not used anywhere
if ( addr_cnt < C_FIFO_DEPTH_LOG - 1 ) begin : USE_MUXCY
MUXCY MUXCY_inst (
.DI(addr[addr_cnt]),
.CI(addr_cy[addr_cnt]),
.S(hsum_A[addr_cnt]),
.O(addr_cy[addr_cnt+1])
);
end
else begin : NO_MUXCY
end
XORCY XORCY_inst (
.LI(hsum_A[addr_cnt]),
.CI(addr_cy[addr_cnt]),
.O(sum_A[addr_cnt])
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(addr[addr_cnt]), // Data output
.C(ACLK), // Clock input
.CE(data_Exists_I), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(sum_A[addr_cnt]) // Data input
);
end // end for bit_cnt
end // C_FAMILY
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Data storage
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_FIFO
reg [C_FIFO_WIDTH-1:0] data_srl[2 ** C_FIFO_DEPTH_LOG-1:0];
always @ (posedge ACLK) begin
if ( valid_Write ) begin
for (index = 0; index < 2 ** C_FIFO_DEPTH_LOG-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= S_MESG;
end
end
assign M_MESG_I = data_srl[addr];
end else begin : USE_FPGA_FIFO
for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN
if ( C_FIFO_DEPTH_LOG == 5 ) begin : USE_32
SRLC32E # (
.INIT(32'h00000000) // Initial Value of Shift Register
) SRLC32E_inst (
.Q(M_MESG_I[bit_cnt]), // SRL data output
.Q31(), // SRL cascade output pin
.A(addr), // 5-bit shift depth select input
.CE(valid_Write), // Clock enable input
.CLK(ACLK), // Clock input
.D(S_MESG[bit_cnt]) // SRL data input
);
end else begin : USE_16
SRLC16E # (
.INIT(32'h00000000) // Initial Value of Shift Register
) SRLC16E_inst (
.Q(M_MESG_I[bit_cnt]), // SRL data output
.Q15(), // SRL cascade output pin
.A0(addr[0]), // 4-bit shift depth select input 0
.A1(addr[1]), // 4-bit shift depth select input 1
.A2(addr[2]), // 4-bit shift depth select input 2
.A3(addr[3]), // 4-bit shift depth select input 3
.CE(valid_Write), // Clock enable input
.CLK(ACLK), // Clock input
.D(S_MESG[bit_cnt]) // SRL data input
);
end // C_FIFO_DEPTH_LOG
end // end for bit_cnt
end // C_FAMILY
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Pipeline stage
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_ENABLE_REGISTERED_OUTPUT != 0 ) begin : USE_FF_OUT
wire [C_FIFO_WIDTH-1:0] M_MESG_FF; // Payload
wire M_VALID_FF; // FIFO not empty
// Select RTL or FPGA optimized instatiations for critical parts.
if ( C_FAMILY == "rtl" ) begin : USE_RTL_OUTPUT_PIPELINE
reg [C_FIFO_WIDTH-1:0] M_MESG_Q; // Payload
reg M_VALID_Q; // FIFO not empty
always @ (posedge ACLK) begin
if (ARESET) begin
M_MESG_Q <= {C_FIFO_WIDTH{1'b0}};
M_VALID_Q <= 1'b0;
end else begin
if ( M_READY_I ) begin
M_MESG_Q <= M_MESG_I;
M_VALID_Q <= M_VALID_I;
end
end
end
assign M_MESG_FF = M_MESG_Q;
assign M_VALID_FF = M_VALID_Q;
end else begin : USE_FPGA_OUTPUT_PIPELINE
reg [C_FIFO_WIDTH-1:0] M_MESG_CMB; // Payload
reg M_VALID_CMB; // FIFO not empty
always @ *
begin
if ( M_READY_I ) begin
M_MESG_CMB <= M_MESG_I;
M_VALID_CMB <= M_VALID_I;
end else begin
M_MESG_CMB <= M_MESG_FF;
M_VALID_CMB <= M_VALID_FF;
end
end
for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(M_MESG_FF[bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_MESG_CMB[bit_cnt]) // Data input
);
end // end for bit_cnt
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(M_VALID_FF), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_VALID_CMB) // Data input
);
end
assign EMPTY = ~M_VALID_I & ~M_VALID_FF;
assign M_MESG = M_MESG_FF;
assign M_VALID = M_VALID_FF;
assign M_READY_I = ( M_READY & M_VALID_FF ) | ~M_VALID_FF;
end else begin : NO_FF_OUT
assign EMPTY = ~M_VALID_I;
assign M_MESG = M_MESG_I;
assign M_VALID = M_VALID_I;
assign M_READY_I = M_READY;
end
endgenerate
endmodule |
module generic_baseblocks_v2_1_command_fifo #
(
parameter C_FAMILY = "virtex6",
parameter integer C_ENABLE_S_VALID_CARRY = 0,
parameter integer C_ENABLE_REGISTERED_OUTPUT = 0,
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [4:5].
parameter integer C_FIFO_WIDTH = 64 // Width of payload [1:512]
)
(
// Global inputs
input wire ACLK, // Clock
input wire ARESET, // Reset
// Information
output wire EMPTY, // FIFO empty (all stages)
// Slave Port
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)
input wire S_VALID, // FIFO push
output wire S_READY, // FIFO not full
// Master Port
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload
output wire M_VALID, // FIFO not empty
input wire M_READY // FIFO pop
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for data vector.
genvar addr_cnt;
genvar bit_cnt;
integer index;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIFO_DEPTH_LOG-1:0] addr;
wire buffer_Full;
wire buffer_Empty;
wire next_Data_Exists;
reg data_Exists_I;
wire valid_Write;
wire new_write;
wire [C_FIFO_DEPTH_LOG-1:0] hsum_A;
wire [C_FIFO_DEPTH_LOG-1:0] sum_A;
wire [C_FIFO_DEPTH_LOG-1:0] addr_cy;
wire buffer_full_early;
wire [C_FIFO_WIDTH-1:0] M_MESG_I; // Payload
wire M_VALID_I; // FIFO not empty
wire M_READY_I; // FIFO pop
/////////////////////////////////////////////////////////////////////////////
// Create Flags
/////////////////////////////////////////////////////////////////////////////
assign buffer_full_early = ( (addr == {{C_FIFO_DEPTH_LOG-1{1'b1}}, 1'b0}) & valid_Write & ~M_READY_I ) |
( buffer_Full & ~M_READY_I );
assign S_READY = ~buffer_Full;
assign buffer_Empty = (addr == {C_FIFO_DEPTH_LOG{1'b0}});
assign next_Data_Exists = (data_Exists_I & ~buffer_Empty) |
(buffer_Empty & S_VALID) |
(data_Exists_I & ~(M_READY_I & data_Exists_I));
always @ (posedge ACLK) begin
if (ARESET) begin
data_Exists_I <= 1'b0;
end else begin
data_Exists_I <= next_Data_Exists;
end
end
assign M_VALID_I = data_Exists_I;
// Select RTL or FPGA optimized instatiations for critical parts.
generate
if ( C_FAMILY == "rtl" || C_ENABLE_S_VALID_CARRY == 0 ) begin : USE_RTL_VALID_WRITE
reg buffer_Full_q;
assign valid_Write = S_VALID & ~buffer_Full;
assign new_write = (S_VALID | ~buffer_Empty);
assign addr_cy[0] = valid_Write;
always @ (posedge ACLK) begin
if (ARESET) begin
buffer_Full_q <= 1'b0;
end else if ( data_Exists_I ) begin
buffer_Full_q <= buffer_full_early;
end
end
assign buffer_Full = buffer_Full_q;
end else begin : USE_FPGA_VALID_WRITE
wire s_valid_dummy1;
wire s_valid_dummy2;
wire sel_s_valid;
wire sel_new_write;
wire valid_Write_dummy1;
wire valid_Write_dummy2;
assign sel_s_valid = ~buffer_Full;
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) s_valid_dummy_inst1
(
.CIN(S_VALID),
.S(1'b1),
.COUT(s_valid_dummy1)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) s_valid_dummy_inst2
(
.CIN(s_valid_dummy1),
.S(1'b1),
.COUT(s_valid_dummy2)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_inst
(
.CIN(s_valid_dummy2),
.S(sel_s_valid),
.COUT(valid_Write)
);
assign sel_new_write = ~buffer_Empty;
generic_baseblocks_v2_1_carry_latch_or #
(
.C_FAMILY(C_FAMILY)
) new_write_inst
(
.CIN(valid_Write),
.I(sel_new_write),
.O(new_write)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst1
(
.CIN(valid_Write),
.S(1'b1),
.COUT(valid_Write_dummy1)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst2
(
.CIN(valid_Write_dummy1),
.S(1'b1),
.COUT(valid_Write_dummy2)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst3
(
.CIN(valid_Write_dummy2),
.S(1'b1),
.COUT(addr_cy[0])
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_I1 (
.Q(buffer_Full), // Data output
.C(ACLK), // Clock input
.CE(data_Exists_I), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(buffer_full_early) // Data input
);
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Create address pointer
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_ADDR
reg [C_FIFO_DEPTH_LOG-1:0] addr_q;
always @ (posedge ACLK) begin
if (ARESET) begin
addr_q <= {C_FIFO_DEPTH_LOG{1'b0}};
end else if ( data_Exists_I ) begin
if ( valid_Write & ~(M_READY_I & data_Exists_I) ) begin
addr_q <= addr_q + 1'b1;
end else if ( ~valid_Write & (M_READY_I & data_Exists_I) & ~buffer_Empty ) begin
addr_q <= addr_q - 1'b1;
end
else begin
addr_q <= addr_q;
end
end
else begin
addr_q <= addr_q;
end
end
assign addr = addr_q;
end else begin : USE_FPGA_ADDR
for (addr_cnt = 0; addr_cnt < C_FIFO_DEPTH_LOG ; addr_cnt = addr_cnt + 1) begin : ADDR_GEN
assign hsum_A[addr_cnt] = ((M_READY_I & data_Exists_I) ^ addr[addr_cnt]) & new_write;
// Don't need the last muxcy, addr_cy(last) is not used anywhere
if ( addr_cnt < C_FIFO_DEPTH_LOG - 1 ) begin : USE_MUXCY
MUXCY MUXCY_inst (
.DI(addr[addr_cnt]),
.CI(addr_cy[addr_cnt]),
.S(hsum_A[addr_cnt]),
.O(addr_cy[addr_cnt+1])
);
end
else begin : NO_MUXCY
end
XORCY XORCY_inst (
.LI(hsum_A[addr_cnt]),
.CI(addr_cy[addr_cnt]),
.O(sum_A[addr_cnt])
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(addr[addr_cnt]), // Data output
.C(ACLK), // Clock input
.CE(data_Exists_I), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(sum_A[addr_cnt]) // Data input
);
end // end for bit_cnt
end // C_FAMILY
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Data storage
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_FIFO
reg [C_FIFO_WIDTH-1:0] data_srl[2 ** C_FIFO_DEPTH_LOG-1:0];
always @ (posedge ACLK) begin
if ( valid_Write ) begin
for (index = 0; index < 2 ** C_FIFO_DEPTH_LOG-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= S_MESG;
end
end
assign M_MESG_I = data_srl[addr];
end else begin : USE_FPGA_FIFO
for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN
if ( C_FIFO_DEPTH_LOG == 5 ) begin : USE_32
SRLC32E # (
.INIT(32'h00000000) // Initial Value of Shift Register
) SRLC32E_inst (
.Q(M_MESG_I[bit_cnt]), // SRL data output
.Q31(), // SRL cascade output pin
.A(addr), // 5-bit shift depth select input
.CE(valid_Write), // Clock enable input
.CLK(ACLK), // Clock input
.D(S_MESG[bit_cnt]) // SRL data input
);
end else begin : USE_16
SRLC16E # (
.INIT(32'h00000000) // Initial Value of Shift Register
) SRLC16E_inst (
.Q(M_MESG_I[bit_cnt]), // SRL data output
.Q15(), // SRL cascade output pin
.A0(addr[0]), // 4-bit shift depth select input 0
.A1(addr[1]), // 4-bit shift depth select input 1
.A2(addr[2]), // 4-bit shift depth select input 2
.A3(addr[3]), // 4-bit shift depth select input 3
.CE(valid_Write), // Clock enable input
.CLK(ACLK), // Clock input
.D(S_MESG[bit_cnt]) // SRL data input
);
end // C_FIFO_DEPTH_LOG
end // end for bit_cnt
end // C_FAMILY
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Pipeline stage
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_ENABLE_REGISTERED_OUTPUT != 0 ) begin : USE_FF_OUT
wire [C_FIFO_WIDTH-1:0] M_MESG_FF; // Payload
wire M_VALID_FF; // FIFO not empty
// Select RTL or FPGA optimized instatiations for critical parts.
if ( C_FAMILY == "rtl" ) begin : USE_RTL_OUTPUT_PIPELINE
reg [C_FIFO_WIDTH-1:0] M_MESG_Q; // Payload
reg M_VALID_Q; // FIFO not empty
always @ (posedge ACLK) begin
if (ARESET) begin
M_MESG_Q <= {C_FIFO_WIDTH{1'b0}};
M_VALID_Q <= 1'b0;
end else begin
if ( M_READY_I ) begin
M_MESG_Q <= M_MESG_I;
M_VALID_Q <= M_VALID_I;
end
end
end
assign M_MESG_FF = M_MESG_Q;
assign M_VALID_FF = M_VALID_Q;
end else begin : USE_FPGA_OUTPUT_PIPELINE
reg [C_FIFO_WIDTH-1:0] M_MESG_CMB; // Payload
reg M_VALID_CMB; // FIFO not empty
always @ *
begin
if ( M_READY_I ) begin
M_MESG_CMB <= M_MESG_I;
M_VALID_CMB <= M_VALID_I;
end else begin
M_MESG_CMB <= M_MESG_FF;
M_VALID_CMB <= M_VALID_FF;
end
end
for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(M_MESG_FF[bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_MESG_CMB[bit_cnt]) // Data input
);
end // end for bit_cnt
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(M_VALID_FF), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_VALID_CMB) // Data input
);
end
assign EMPTY = ~M_VALID_I & ~M_VALID_FF;
assign M_MESG = M_MESG_FF;
assign M_VALID = M_VALID_FF;
assign M_READY_I = ( M_READY & M_VALID_FF ) | ~M_VALID_FF;
end else begin : NO_FF_OUT
assign EMPTY = ~M_VALID_I;
assign M_MESG = M_MESG_I;
assign M_VALID = M_VALID_I;
assign M_READY_I = M_READY;
end
endgenerate
endmodule |
module generic_baseblocks_v2_1_command_fifo #
(
parameter C_FAMILY = "virtex6",
parameter integer C_ENABLE_S_VALID_CARRY = 0,
parameter integer C_ENABLE_REGISTERED_OUTPUT = 0,
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [4:5].
parameter integer C_FIFO_WIDTH = 64 // Width of payload [1:512]
)
(
// Global inputs
input wire ACLK, // Clock
input wire ARESET, // Reset
// Information
output wire EMPTY, // FIFO empty (all stages)
// Slave Port
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)
input wire S_VALID, // FIFO push
output wire S_READY, // FIFO not full
// Master Port
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload
output wire M_VALID, // FIFO not empty
input wire M_READY // FIFO pop
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for data vector.
genvar addr_cnt;
genvar bit_cnt;
integer index;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIFO_DEPTH_LOG-1:0] addr;
wire buffer_Full;
wire buffer_Empty;
wire next_Data_Exists;
reg data_Exists_I;
wire valid_Write;
wire new_write;
wire [C_FIFO_DEPTH_LOG-1:0] hsum_A;
wire [C_FIFO_DEPTH_LOG-1:0] sum_A;
wire [C_FIFO_DEPTH_LOG-1:0] addr_cy;
wire buffer_full_early;
wire [C_FIFO_WIDTH-1:0] M_MESG_I; // Payload
wire M_VALID_I; // FIFO not empty
wire M_READY_I; // FIFO pop
/////////////////////////////////////////////////////////////////////////////
// Create Flags
/////////////////////////////////////////////////////////////////////////////
assign buffer_full_early = ( (addr == {{C_FIFO_DEPTH_LOG-1{1'b1}}, 1'b0}) & valid_Write & ~M_READY_I ) |
( buffer_Full & ~M_READY_I );
assign S_READY = ~buffer_Full;
assign buffer_Empty = (addr == {C_FIFO_DEPTH_LOG{1'b0}});
assign next_Data_Exists = (data_Exists_I & ~buffer_Empty) |
(buffer_Empty & S_VALID) |
(data_Exists_I & ~(M_READY_I & data_Exists_I));
always @ (posedge ACLK) begin
if (ARESET) begin
data_Exists_I <= 1'b0;
end else begin
data_Exists_I <= next_Data_Exists;
end
end
assign M_VALID_I = data_Exists_I;
// Select RTL or FPGA optimized instatiations for critical parts.
generate
if ( C_FAMILY == "rtl" || C_ENABLE_S_VALID_CARRY == 0 ) begin : USE_RTL_VALID_WRITE
reg buffer_Full_q;
assign valid_Write = S_VALID & ~buffer_Full;
assign new_write = (S_VALID | ~buffer_Empty);
assign addr_cy[0] = valid_Write;
always @ (posedge ACLK) begin
if (ARESET) begin
buffer_Full_q <= 1'b0;
end else if ( data_Exists_I ) begin
buffer_Full_q <= buffer_full_early;
end
end
assign buffer_Full = buffer_Full_q;
end else begin : USE_FPGA_VALID_WRITE
wire s_valid_dummy1;
wire s_valid_dummy2;
wire sel_s_valid;
wire sel_new_write;
wire valid_Write_dummy1;
wire valid_Write_dummy2;
assign sel_s_valid = ~buffer_Full;
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) s_valid_dummy_inst1
(
.CIN(S_VALID),
.S(1'b1),
.COUT(s_valid_dummy1)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) s_valid_dummy_inst2
(
.CIN(s_valid_dummy1),
.S(1'b1),
.COUT(s_valid_dummy2)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_inst
(
.CIN(s_valid_dummy2),
.S(sel_s_valid),
.COUT(valid_Write)
);
assign sel_new_write = ~buffer_Empty;
generic_baseblocks_v2_1_carry_latch_or #
(
.C_FAMILY(C_FAMILY)
) new_write_inst
(
.CIN(valid_Write),
.I(sel_new_write),
.O(new_write)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst1
(
.CIN(valid_Write),
.S(1'b1),
.COUT(valid_Write_dummy1)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst2
(
.CIN(valid_Write_dummy1),
.S(1'b1),
.COUT(valid_Write_dummy2)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst3
(
.CIN(valid_Write_dummy2),
.S(1'b1),
.COUT(addr_cy[0])
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_I1 (
.Q(buffer_Full), // Data output
.C(ACLK), // Clock input
.CE(data_Exists_I), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(buffer_full_early) // Data input
);
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Create address pointer
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_ADDR
reg [C_FIFO_DEPTH_LOG-1:0] addr_q;
always @ (posedge ACLK) begin
if (ARESET) begin
addr_q <= {C_FIFO_DEPTH_LOG{1'b0}};
end else if ( data_Exists_I ) begin
if ( valid_Write & ~(M_READY_I & data_Exists_I) ) begin
addr_q <= addr_q + 1'b1;
end else if ( ~valid_Write & (M_READY_I & data_Exists_I) & ~buffer_Empty ) begin
addr_q <= addr_q - 1'b1;
end
else begin
addr_q <= addr_q;
end
end
else begin
addr_q <= addr_q;
end
end
assign addr = addr_q;
end else begin : USE_FPGA_ADDR
for (addr_cnt = 0; addr_cnt < C_FIFO_DEPTH_LOG ; addr_cnt = addr_cnt + 1) begin : ADDR_GEN
assign hsum_A[addr_cnt] = ((M_READY_I & data_Exists_I) ^ addr[addr_cnt]) & new_write;
// Don't need the last muxcy, addr_cy(last) is not used anywhere
if ( addr_cnt < C_FIFO_DEPTH_LOG - 1 ) begin : USE_MUXCY
MUXCY MUXCY_inst (
.DI(addr[addr_cnt]),
.CI(addr_cy[addr_cnt]),
.S(hsum_A[addr_cnt]),
.O(addr_cy[addr_cnt+1])
);
end
else begin : NO_MUXCY
end
XORCY XORCY_inst (
.LI(hsum_A[addr_cnt]),
.CI(addr_cy[addr_cnt]),
.O(sum_A[addr_cnt])
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(addr[addr_cnt]), // Data output
.C(ACLK), // Clock input
.CE(data_Exists_I), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(sum_A[addr_cnt]) // Data input
);
end // end for bit_cnt
end // C_FAMILY
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Data storage
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_FIFO
reg [C_FIFO_WIDTH-1:0] data_srl[2 ** C_FIFO_DEPTH_LOG-1:0];
always @ (posedge ACLK) begin
if ( valid_Write ) begin
for (index = 0; index < 2 ** C_FIFO_DEPTH_LOG-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= S_MESG;
end
end
assign M_MESG_I = data_srl[addr];
end else begin : USE_FPGA_FIFO
for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN
if ( C_FIFO_DEPTH_LOG == 5 ) begin : USE_32
SRLC32E # (
.INIT(32'h00000000) // Initial Value of Shift Register
) SRLC32E_inst (
.Q(M_MESG_I[bit_cnt]), // SRL data output
.Q31(), // SRL cascade output pin
.A(addr), // 5-bit shift depth select input
.CE(valid_Write), // Clock enable input
.CLK(ACLK), // Clock input
.D(S_MESG[bit_cnt]) // SRL data input
);
end else begin : USE_16
SRLC16E # (
.INIT(32'h00000000) // Initial Value of Shift Register
) SRLC16E_inst (
.Q(M_MESG_I[bit_cnt]), // SRL data output
.Q15(), // SRL cascade output pin
.A0(addr[0]), // 4-bit shift depth select input 0
.A1(addr[1]), // 4-bit shift depth select input 1
.A2(addr[2]), // 4-bit shift depth select input 2
.A3(addr[3]), // 4-bit shift depth select input 3
.CE(valid_Write), // Clock enable input
.CLK(ACLK), // Clock input
.D(S_MESG[bit_cnt]) // SRL data input
);
end // C_FIFO_DEPTH_LOG
end // end for bit_cnt
end // C_FAMILY
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Pipeline stage
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_ENABLE_REGISTERED_OUTPUT != 0 ) begin : USE_FF_OUT
wire [C_FIFO_WIDTH-1:0] M_MESG_FF; // Payload
wire M_VALID_FF; // FIFO not empty
// Select RTL or FPGA optimized instatiations for critical parts.
if ( C_FAMILY == "rtl" ) begin : USE_RTL_OUTPUT_PIPELINE
reg [C_FIFO_WIDTH-1:0] M_MESG_Q; // Payload
reg M_VALID_Q; // FIFO not empty
always @ (posedge ACLK) begin
if (ARESET) begin
M_MESG_Q <= {C_FIFO_WIDTH{1'b0}};
M_VALID_Q <= 1'b0;
end else begin
if ( M_READY_I ) begin
M_MESG_Q <= M_MESG_I;
M_VALID_Q <= M_VALID_I;
end
end
end
assign M_MESG_FF = M_MESG_Q;
assign M_VALID_FF = M_VALID_Q;
end else begin : USE_FPGA_OUTPUT_PIPELINE
reg [C_FIFO_WIDTH-1:0] M_MESG_CMB; // Payload
reg M_VALID_CMB; // FIFO not empty
always @ *
begin
if ( M_READY_I ) begin
M_MESG_CMB <= M_MESG_I;
M_VALID_CMB <= M_VALID_I;
end else begin
M_MESG_CMB <= M_MESG_FF;
M_VALID_CMB <= M_VALID_FF;
end
end
for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(M_MESG_FF[bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_MESG_CMB[bit_cnt]) // Data input
);
end // end for bit_cnt
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(M_VALID_FF), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_VALID_CMB) // Data input
);
end
assign EMPTY = ~M_VALID_I & ~M_VALID_FF;
assign M_MESG = M_MESG_FF;
assign M_VALID = M_VALID_FF;
assign M_READY_I = ( M_READY & M_VALID_FF ) | ~M_VALID_FF;
end else begin : NO_FF_OUT
assign EMPTY = ~M_VALID_I;
assign M_MESG = M_MESG_I;
assign M_VALID = M_VALID_I;
assign M_READY_I = M_READY;
end
endgenerate
endmodule |
module generic_baseblocks_v2_1_command_fifo #
(
parameter C_FAMILY = "virtex6",
parameter integer C_ENABLE_S_VALID_CARRY = 0,
parameter integer C_ENABLE_REGISTERED_OUTPUT = 0,
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [4:5].
parameter integer C_FIFO_WIDTH = 64 // Width of payload [1:512]
)
(
// Global inputs
input wire ACLK, // Clock
input wire ARESET, // Reset
// Information
output wire EMPTY, // FIFO empty (all stages)
// Slave Port
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)
input wire S_VALID, // FIFO push
output wire S_READY, // FIFO not full
// Master Port
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload
output wire M_VALID, // FIFO not empty
input wire M_READY // FIFO pop
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for data vector.
genvar addr_cnt;
genvar bit_cnt;
integer index;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIFO_DEPTH_LOG-1:0] addr;
wire buffer_Full;
wire buffer_Empty;
wire next_Data_Exists;
reg data_Exists_I;
wire valid_Write;
wire new_write;
wire [C_FIFO_DEPTH_LOG-1:0] hsum_A;
wire [C_FIFO_DEPTH_LOG-1:0] sum_A;
wire [C_FIFO_DEPTH_LOG-1:0] addr_cy;
wire buffer_full_early;
wire [C_FIFO_WIDTH-1:0] M_MESG_I; // Payload
wire M_VALID_I; // FIFO not empty
wire M_READY_I; // FIFO pop
/////////////////////////////////////////////////////////////////////////////
// Create Flags
/////////////////////////////////////////////////////////////////////////////
assign buffer_full_early = ( (addr == {{C_FIFO_DEPTH_LOG-1{1'b1}}, 1'b0}) & valid_Write & ~M_READY_I ) |
( buffer_Full & ~M_READY_I );
assign S_READY = ~buffer_Full;
assign buffer_Empty = (addr == {C_FIFO_DEPTH_LOG{1'b0}});
assign next_Data_Exists = (data_Exists_I & ~buffer_Empty) |
(buffer_Empty & S_VALID) |
(data_Exists_I & ~(M_READY_I & data_Exists_I));
always @ (posedge ACLK) begin
if (ARESET) begin
data_Exists_I <= 1'b0;
end else begin
data_Exists_I <= next_Data_Exists;
end
end
assign M_VALID_I = data_Exists_I;
// Select RTL or FPGA optimized instatiations for critical parts.
generate
if ( C_FAMILY == "rtl" || C_ENABLE_S_VALID_CARRY == 0 ) begin : USE_RTL_VALID_WRITE
reg buffer_Full_q;
assign valid_Write = S_VALID & ~buffer_Full;
assign new_write = (S_VALID | ~buffer_Empty);
assign addr_cy[0] = valid_Write;
always @ (posedge ACLK) begin
if (ARESET) begin
buffer_Full_q <= 1'b0;
end else if ( data_Exists_I ) begin
buffer_Full_q <= buffer_full_early;
end
end
assign buffer_Full = buffer_Full_q;
end else begin : USE_FPGA_VALID_WRITE
wire s_valid_dummy1;
wire s_valid_dummy2;
wire sel_s_valid;
wire sel_new_write;
wire valid_Write_dummy1;
wire valid_Write_dummy2;
assign sel_s_valid = ~buffer_Full;
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) s_valid_dummy_inst1
(
.CIN(S_VALID),
.S(1'b1),
.COUT(s_valid_dummy1)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) s_valid_dummy_inst2
(
.CIN(s_valid_dummy1),
.S(1'b1),
.COUT(s_valid_dummy2)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_inst
(
.CIN(s_valid_dummy2),
.S(sel_s_valid),
.COUT(valid_Write)
);
assign sel_new_write = ~buffer_Empty;
generic_baseblocks_v2_1_carry_latch_or #
(
.C_FAMILY(C_FAMILY)
) new_write_inst
(
.CIN(valid_Write),
.I(sel_new_write),
.O(new_write)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst1
(
.CIN(valid_Write),
.S(1'b1),
.COUT(valid_Write_dummy1)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst2
(
.CIN(valid_Write_dummy1),
.S(1'b1),
.COUT(valid_Write_dummy2)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst3
(
.CIN(valid_Write_dummy2),
.S(1'b1),
.COUT(addr_cy[0])
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_I1 (
.Q(buffer_Full), // Data output
.C(ACLK), // Clock input
.CE(data_Exists_I), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(buffer_full_early) // Data input
);
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Create address pointer
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_ADDR
reg [C_FIFO_DEPTH_LOG-1:0] addr_q;
always @ (posedge ACLK) begin
if (ARESET) begin
addr_q <= {C_FIFO_DEPTH_LOG{1'b0}};
end else if ( data_Exists_I ) begin
if ( valid_Write & ~(M_READY_I & data_Exists_I) ) begin
addr_q <= addr_q + 1'b1;
end else if ( ~valid_Write & (M_READY_I & data_Exists_I) & ~buffer_Empty ) begin
addr_q <= addr_q - 1'b1;
end
else begin
addr_q <= addr_q;
end
end
else begin
addr_q <= addr_q;
end
end
assign addr = addr_q;
end else begin : USE_FPGA_ADDR
for (addr_cnt = 0; addr_cnt < C_FIFO_DEPTH_LOG ; addr_cnt = addr_cnt + 1) begin : ADDR_GEN
assign hsum_A[addr_cnt] = ((M_READY_I & data_Exists_I) ^ addr[addr_cnt]) & new_write;
// Don't need the last muxcy, addr_cy(last) is not used anywhere
if ( addr_cnt < C_FIFO_DEPTH_LOG - 1 ) begin : USE_MUXCY
MUXCY MUXCY_inst (
.DI(addr[addr_cnt]),
.CI(addr_cy[addr_cnt]),
.S(hsum_A[addr_cnt]),
.O(addr_cy[addr_cnt+1])
);
end
else begin : NO_MUXCY
end
XORCY XORCY_inst (
.LI(hsum_A[addr_cnt]),
.CI(addr_cy[addr_cnt]),
.O(sum_A[addr_cnt])
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(addr[addr_cnt]), // Data output
.C(ACLK), // Clock input
.CE(data_Exists_I), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(sum_A[addr_cnt]) // Data input
);
end // end for bit_cnt
end // C_FAMILY
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Data storage
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_FIFO
reg [C_FIFO_WIDTH-1:0] data_srl[2 ** C_FIFO_DEPTH_LOG-1:0];
always @ (posedge ACLK) begin
if ( valid_Write ) begin
for (index = 0; index < 2 ** C_FIFO_DEPTH_LOG-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= S_MESG;
end
end
assign M_MESG_I = data_srl[addr];
end else begin : USE_FPGA_FIFO
for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN
if ( C_FIFO_DEPTH_LOG == 5 ) begin : USE_32
SRLC32E # (
.INIT(32'h00000000) // Initial Value of Shift Register
) SRLC32E_inst (
.Q(M_MESG_I[bit_cnt]), // SRL data output
.Q31(), // SRL cascade output pin
.A(addr), // 5-bit shift depth select input
.CE(valid_Write), // Clock enable input
.CLK(ACLK), // Clock input
.D(S_MESG[bit_cnt]) // SRL data input
);
end else begin : USE_16
SRLC16E # (
.INIT(32'h00000000) // Initial Value of Shift Register
) SRLC16E_inst (
.Q(M_MESG_I[bit_cnt]), // SRL data output
.Q15(), // SRL cascade output pin
.A0(addr[0]), // 4-bit shift depth select input 0
.A1(addr[1]), // 4-bit shift depth select input 1
.A2(addr[2]), // 4-bit shift depth select input 2
.A3(addr[3]), // 4-bit shift depth select input 3
.CE(valid_Write), // Clock enable input
.CLK(ACLK), // Clock input
.D(S_MESG[bit_cnt]) // SRL data input
);
end // C_FIFO_DEPTH_LOG
end // end for bit_cnt
end // C_FAMILY
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Pipeline stage
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_ENABLE_REGISTERED_OUTPUT != 0 ) begin : USE_FF_OUT
wire [C_FIFO_WIDTH-1:0] M_MESG_FF; // Payload
wire M_VALID_FF; // FIFO not empty
// Select RTL or FPGA optimized instatiations for critical parts.
if ( C_FAMILY == "rtl" ) begin : USE_RTL_OUTPUT_PIPELINE
reg [C_FIFO_WIDTH-1:0] M_MESG_Q; // Payload
reg M_VALID_Q; // FIFO not empty
always @ (posedge ACLK) begin
if (ARESET) begin
M_MESG_Q <= {C_FIFO_WIDTH{1'b0}};
M_VALID_Q <= 1'b0;
end else begin
if ( M_READY_I ) begin
M_MESG_Q <= M_MESG_I;
M_VALID_Q <= M_VALID_I;
end
end
end
assign M_MESG_FF = M_MESG_Q;
assign M_VALID_FF = M_VALID_Q;
end else begin : USE_FPGA_OUTPUT_PIPELINE
reg [C_FIFO_WIDTH-1:0] M_MESG_CMB; // Payload
reg M_VALID_CMB; // FIFO not empty
always @ *
begin
if ( M_READY_I ) begin
M_MESG_CMB <= M_MESG_I;
M_VALID_CMB <= M_VALID_I;
end else begin
M_MESG_CMB <= M_MESG_FF;
M_VALID_CMB <= M_VALID_FF;
end
end
for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(M_MESG_FF[bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_MESG_CMB[bit_cnt]) // Data input
);
end // end for bit_cnt
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(M_VALID_FF), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_VALID_CMB) // Data input
);
end
assign EMPTY = ~M_VALID_I & ~M_VALID_FF;
assign M_MESG = M_MESG_FF;
assign M_VALID = M_VALID_FF;
assign M_READY_I = ( M_READY & M_VALID_FF ) | ~M_VALID_FF;
end else begin : NO_FF_OUT
assign EMPTY = ~M_VALID_I;
assign M_MESG = M_MESG_I;
assign M_VALID = M_VALID_I;
assign M_READY_I = M_READY;
end
endgenerate
endmodule |
module generic_baseblocks_v2_1_command_fifo #
(
parameter C_FAMILY = "virtex6",
parameter integer C_ENABLE_S_VALID_CARRY = 0,
parameter integer C_ENABLE_REGISTERED_OUTPUT = 0,
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [4:5].
parameter integer C_FIFO_WIDTH = 64 // Width of payload [1:512]
)
(
// Global inputs
input wire ACLK, // Clock
input wire ARESET, // Reset
// Information
output wire EMPTY, // FIFO empty (all stages)
// Slave Port
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)
input wire S_VALID, // FIFO push
output wire S_READY, // FIFO not full
// Master Port
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload
output wire M_VALID, // FIFO not empty
input wire M_READY // FIFO pop
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for data vector.
genvar addr_cnt;
genvar bit_cnt;
integer index;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIFO_DEPTH_LOG-1:0] addr;
wire buffer_Full;
wire buffer_Empty;
wire next_Data_Exists;
reg data_Exists_I;
wire valid_Write;
wire new_write;
wire [C_FIFO_DEPTH_LOG-1:0] hsum_A;
wire [C_FIFO_DEPTH_LOG-1:0] sum_A;
wire [C_FIFO_DEPTH_LOG-1:0] addr_cy;
wire buffer_full_early;
wire [C_FIFO_WIDTH-1:0] M_MESG_I; // Payload
wire M_VALID_I; // FIFO not empty
wire M_READY_I; // FIFO pop
/////////////////////////////////////////////////////////////////////////////
// Create Flags
/////////////////////////////////////////////////////////////////////////////
assign buffer_full_early = ( (addr == {{C_FIFO_DEPTH_LOG-1{1'b1}}, 1'b0}) & valid_Write & ~M_READY_I ) |
( buffer_Full & ~M_READY_I );
assign S_READY = ~buffer_Full;
assign buffer_Empty = (addr == {C_FIFO_DEPTH_LOG{1'b0}});
assign next_Data_Exists = (data_Exists_I & ~buffer_Empty) |
(buffer_Empty & S_VALID) |
(data_Exists_I & ~(M_READY_I & data_Exists_I));
always @ (posedge ACLK) begin
if (ARESET) begin
data_Exists_I <= 1'b0;
end else begin
data_Exists_I <= next_Data_Exists;
end
end
assign M_VALID_I = data_Exists_I;
// Select RTL or FPGA optimized instatiations for critical parts.
generate
if ( C_FAMILY == "rtl" || C_ENABLE_S_VALID_CARRY == 0 ) begin : USE_RTL_VALID_WRITE
reg buffer_Full_q;
assign valid_Write = S_VALID & ~buffer_Full;
assign new_write = (S_VALID | ~buffer_Empty);
assign addr_cy[0] = valid_Write;
always @ (posedge ACLK) begin
if (ARESET) begin
buffer_Full_q <= 1'b0;
end else if ( data_Exists_I ) begin
buffer_Full_q <= buffer_full_early;
end
end
assign buffer_Full = buffer_Full_q;
end else begin : USE_FPGA_VALID_WRITE
wire s_valid_dummy1;
wire s_valid_dummy2;
wire sel_s_valid;
wire sel_new_write;
wire valid_Write_dummy1;
wire valid_Write_dummy2;
assign sel_s_valid = ~buffer_Full;
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) s_valid_dummy_inst1
(
.CIN(S_VALID),
.S(1'b1),
.COUT(s_valid_dummy1)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) s_valid_dummy_inst2
(
.CIN(s_valid_dummy1),
.S(1'b1),
.COUT(s_valid_dummy2)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_inst
(
.CIN(s_valid_dummy2),
.S(sel_s_valid),
.COUT(valid_Write)
);
assign sel_new_write = ~buffer_Empty;
generic_baseblocks_v2_1_carry_latch_or #
(
.C_FAMILY(C_FAMILY)
) new_write_inst
(
.CIN(valid_Write),
.I(sel_new_write),
.O(new_write)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst1
(
.CIN(valid_Write),
.S(1'b1),
.COUT(valid_Write_dummy1)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst2
(
.CIN(valid_Write_dummy1),
.S(1'b1),
.COUT(valid_Write_dummy2)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst3
(
.CIN(valid_Write_dummy2),
.S(1'b1),
.COUT(addr_cy[0])
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_I1 (
.Q(buffer_Full), // Data output
.C(ACLK), // Clock input
.CE(data_Exists_I), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(buffer_full_early) // Data input
);
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Create address pointer
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_ADDR
reg [C_FIFO_DEPTH_LOG-1:0] addr_q;
always @ (posedge ACLK) begin
if (ARESET) begin
addr_q <= {C_FIFO_DEPTH_LOG{1'b0}};
end else if ( data_Exists_I ) begin
if ( valid_Write & ~(M_READY_I & data_Exists_I) ) begin
addr_q <= addr_q + 1'b1;
end else if ( ~valid_Write & (M_READY_I & data_Exists_I) & ~buffer_Empty ) begin
addr_q <= addr_q - 1'b1;
end
else begin
addr_q <= addr_q;
end
end
else begin
addr_q <= addr_q;
end
end
assign addr = addr_q;
end else begin : USE_FPGA_ADDR
for (addr_cnt = 0; addr_cnt < C_FIFO_DEPTH_LOG ; addr_cnt = addr_cnt + 1) begin : ADDR_GEN
assign hsum_A[addr_cnt] = ((M_READY_I & data_Exists_I) ^ addr[addr_cnt]) & new_write;
// Don't need the last muxcy, addr_cy(last) is not used anywhere
if ( addr_cnt < C_FIFO_DEPTH_LOG - 1 ) begin : USE_MUXCY
MUXCY MUXCY_inst (
.DI(addr[addr_cnt]),
.CI(addr_cy[addr_cnt]),
.S(hsum_A[addr_cnt]),
.O(addr_cy[addr_cnt+1])
);
end
else begin : NO_MUXCY
end
XORCY XORCY_inst (
.LI(hsum_A[addr_cnt]),
.CI(addr_cy[addr_cnt]),
.O(sum_A[addr_cnt])
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(addr[addr_cnt]), // Data output
.C(ACLK), // Clock input
.CE(data_Exists_I), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(sum_A[addr_cnt]) // Data input
);
end // end for bit_cnt
end // C_FAMILY
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Data storage
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_FIFO
reg [C_FIFO_WIDTH-1:0] data_srl[2 ** C_FIFO_DEPTH_LOG-1:0];
always @ (posedge ACLK) begin
if ( valid_Write ) begin
for (index = 0; index < 2 ** C_FIFO_DEPTH_LOG-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= S_MESG;
end
end
assign M_MESG_I = data_srl[addr];
end else begin : USE_FPGA_FIFO
for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN
if ( C_FIFO_DEPTH_LOG == 5 ) begin : USE_32
SRLC32E # (
.INIT(32'h00000000) // Initial Value of Shift Register
) SRLC32E_inst (
.Q(M_MESG_I[bit_cnt]), // SRL data output
.Q31(), // SRL cascade output pin
.A(addr), // 5-bit shift depth select input
.CE(valid_Write), // Clock enable input
.CLK(ACLK), // Clock input
.D(S_MESG[bit_cnt]) // SRL data input
);
end else begin : USE_16
SRLC16E # (
.INIT(32'h00000000) // Initial Value of Shift Register
) SRLC16E_inst (
.Q(M_MESG_I[bit_cnt]), // SRL data output
.Q15(), // SRL cascade output pin
.A0(addr[0]), // 4-bit shift depth select input 0
.A1(addr[1]), // 4-bit shift depth select input 1
.A2(addr[2]), // 4-bit shift depth select input 2
.A3(addr[3]), // 4-bit shift depth select input 3
.CE(valid_Write), // Clock enable input
.CLK(ACLK), // Clock input
.D(S_MESG[bit_cnt]) // SRL data input
);
end // C_FIFO_DEPTH_LOG
end // end for bit_cnt
end // C_FAMILY
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Pipeline stage
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_ENABLE_REGISTERED_OUTPUT != 0 ) begin : USE_FF_OUT
wire [C_FIFO_WIDTH-1:0] M_MESG_FF; // Payload
wire M_VALID_FF; // FIFO not empty
// Select RTL or FPGA optimized instatiations for critical parts.
if ( C_FAMILY == "rtl" ) begin : USE_RTL_OUTPUT_PIPELINE
reg [C_FIFO_WIDTH-1:0] M_MESG_Q; // Payload
reg M_VALID_Q; // FIFO not empty
always @ (posedge ACLK) begin
if (ARESET) begin
M_MESG_Q <= {C_FIFO_WIDTH{1'b0}};
M_VALID_Q <= 1'b0;
end else begin
if ( M_READY_I ) begin
M_MESG_Q <= M_MESG_I;
M_VALID_Q <= M_VALID_I;
end
end
end
assign M_MESG_FF = M_MESG_Q;
assign M_VALID_FF = M_VALID_Q;
end else begin : USE_FPGA_OUTPUT_PIPELINE
reg [C_FIFO_WIDTH-1:0] M_MESG_CMB; // Payload
reg M_VALID_CMB; // FIFO not empty
always @ *
begin
if ( M_READY_I ) begin
M_MESG_CMB <= M_MESG_I;
M_VALID_CMB <= M_VALID_I;
end else begin
M_MESG_CMB <= M_MESG_FF;
M_VALID_CMB <= M_VALID_FF;
end
end
for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(M_MESG_FF[bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_MESG_CMB[bit_cnt]) // Data input
);
end // end for bit_cnt
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(M_VALID_FF), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_VALID_CMB) // Data input
);
end
assign EMPTY = ~M_VALID_I & ~M_VALID_FF;
assign M_MESG = M_MESG_FF;
assign M_VALID = M_VALID_FF;
assign M_READY_I = ( M_READY & M_VALID_FF ) | ~M_VALID_FF;
end else begin : NO_FF_OUT
assign EMPTY = ~M_VALID_I;
assign M_MESG = M_MESG_I;
assign M_VALID = M_VALID_I;
assign M_READY_I = M_READY;
end
endgenerate
endmodule |
module generic_baseblocks_v2_1_command_fifo #
(
parameter C_FAMILY = "virtex6",
parameter integer C_ENABLE_S_VALID_CARRY = 0,
parameter integer C_ENABLE_REGISTERED_OUTPUT = 0,
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [4:5].
parameter integer C_FIFO_WIDTH = 64 // Width of payload [1:512]
)
(
// Global inputs
input wire ACLK, // Clock
input wire ARESET, // Reset
// Information
output wire EMPTY, // FIFO empty (all stages)
// Slave Port
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)
input wire S_VALID, // FIFO push
output wire S_READY, // FIFO not full
// Master Port
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload
output wire M_VALID, // FIFO not empty
input wire M_READY // FIFO pop
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for data vector.
genvar addr_cnt;
genvar bit_cnt;
integer index;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIFO_DEPTH_LOG-1:0] addr;
wire buffer_Full;
wire buffer_Empty;
wire next_Data_Exists;
reg data_Exists_I;
wire valid_Write;
wire new_write;
wire [C_FIFO_DEPTH_LOG-1:0] hsum_A;
wire [C_FIFO_DEPTH_LOG-1:0] sum_A;
wire [C_FIFO_DEPTH_LOG-1:0] addr_cy;
wire buffer_full_early;
wire [C_FIFO_WIDTH-1:0] M_MESG_I; // Payload
wire M_VALID_I; // FIFO not empty
wire M_READY_I; // FIFO pop
/////////////////////////////////////////////////////////////////////////////
// Create Flags
/////////////////////////////////////////////////////////////////////////////
assign buffer_full_early = ( (addr == {{C_FIFO_DEPTH_LOG-1{1'b1}}, 1'b0}) & valid_Write & ~M_READY_I ) |
( buffer_Full & ~M_READY_I );
assign S_READY = ~buffer_Full;
assign buffer_Empty = (addr == {C_FIFO_DEPTH_LOG{1'b0}});
assign next_Data_Exists = (data_Exists_I & ~buffer_Empty) |
(buffer_Empty & S_VALID) |
(data_Exists_I & ~(M_READY_I & data_Exists_I));
always @ (posedge ACLK) begin
if (ARESET) begin
data_Exists_I <= 1'b0;
end else begin
data_Exists_I <= next_Data_Exists;
end
end
assign M_VALID_I = data_Exists_I;
// Select RTL or FPGA optimized instatiations for critical parts.
generate
if ( C_FAMILY == "rtl" || C_ENABLE_S_VALID_CARRY == 0 ) begin : USE_RTL_VALID_WRITE
reg buffer_Full_q;
assign valid_Write = S_VALID & ~buffer_Full;
assign new_write = (S_VALID | ~buffer_Empty);
assign addr_cy[0] = valid_Write;
always @ (posedge ACLK) begin
if (ARESET) begin
buffer_Full_q <= 1'b0;
end else if ( data_Exists_I ) begin
buffer_Full_q <= buffer_full_early;
end
end
assign buffer_Full = buffer_Full_q;
end else begin : USE_FPGA_VALID_WRITE
wire s_valid_dummy1;
wire s_valid_dummy2;
wire sel_s_valid;
wire sel_new_write;
wire valid_Write_dummy1;
wire valid_Write_dummy2;
assign sel_s_valid = ~buffer_Full;
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) s_valid_dummy_inst1
(
.CIN(S_VALID),
.S(1'b1),
.COUT(s_valid_dummy1)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) s_valid_dummy_inst2
(
.CIN(s_valid_dummy1),
.S(1'b1),
.COUT(s_valid_dummy2)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_inst
(
.CIN(s_valid_dummy2),
.S(sel_s_valid),
.COUT(valid_Write)
);
assign sel_new_write = ~buffer_Empty;
generic_baseblocks_v2_1_carry_latch_or #
(
.C_FAMILY(C_FAMILY)
) new_write_inst
(
.CIN(valid_Write),
.I(sel_new_write),
.O(new_write)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst1
(
.CIN(valid_Write),
.S(1'b1),
.COUT(valid_Write_dummy1)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst2
(
.CIN(valid_Write_dummy1),
.S(1'b1),
.COUT(valid_Write_dummy2)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst3
(
.CIN(valid_Write_dummy2),
.S(1'b1),
.COUT(addr_cy[0])
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_I1 (
.Q(buffer_Full), // Data output
.C(ACLK), // Clock input
.CE(data_Exists_I), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(buffer_full_early) // Data input
);
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Create address pointer
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_ADDR
reg [C_FIFO_DEPTH_LOG-1:0] addr_q;
always @ (posedge ACLK) begin
if (ARESET) begin
addr_q <= {C_FIFO_DEPTH_LOG{1'b0}};
end else if ( data_Exists_I ) begin
if ( valid_Write & ~(M_READY_I & data_Exists_I) ) begin
addr_q <= addr_q + 1'b1;
end else if ( ~valid_Write & (M_READY_I & data_Exists_I) & ~buffer_Empty ) begin
addr_q <= addr_q - 1'b1;
end
else begin
addr_q <= addr_q;
end
end
else begin
addr_q <= addr_q;
end
end
assign addr = addr_q;
end else begin : USE_FPGA_ADDR
for (addr_cnt = 0; addr_cnt < C_FIFO_DEPTH_LOG ; addr_cnt = addr_cnt + 1) begin : ADDR_GEN
assign hsum_A[addr_cnt] = ((M_READY_I & data_Exists_I) ^ addr[addr_cnt]) & new_write;
// Don't need the last muxcy, addr_cy(last) is not used anywhere
if ( addr_cnt < C_FIFO_DEPTH_LOG - 1 ) begin : USE_MUXCY
MUXCY MUXCY_inst (
.DI(addr[addr_cnt]),
.CI(addr_cy[addr_cnt]),
.S(hsum_A[addr_cnt]),
.O(addr_cy[addr_cnt+1])
);
end
else begin : NO_MUXCY
end
XORCY XORCY_inst (
.LI(hsum_A[addr_cnt]),
.CI(addr_cy[addr_cnt]),
.O(sum_A[addr_cnt])
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(addr[addr_cnt]), // Data output
.C(ACLK), // Clock input
.CE(data_Exists_I), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(sum_A[addr_cnt]) // Data input
);
end // end for bit_cnt
end // C_FAMILY
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Data storage
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_FIFO
reg [C_FIFO_WIDTH-1:0] data_srl[2 ** C_FIFO_DEPTH_LOG-1:0];
always @ (posedge ACLK) begin
if ( valid_Write ) begin
for (index = 0; index < 2 ** C_FIFO_DEPTH_LOG-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= S_MESG;
end
end
assign M_MESG_I = data_srl[addr];
end else begin : USE_FPGA_FIFO
for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN
if ( C_FIFO_DEPTH_LOG == 5 ) begin : USE_32
SRLC32E # (
.INIT(32'h00000000) // Initial Value of Shift Register
) SRLC32E_inst (
.Q(M_MESG_I[bit_cnt]), // SRL data output
.Q31(), // SRL cascade output pin
.A(addr), // 5-bit shift depth select input
.CE(valid_Write), // Clock enable input
.CLK(ACLK), // Clock input
.D(S_MESG[bit_cnt]) // SRL data input
);
end else begin : USE_16
SRLC16E # (
.INIT(32'h00000000) // Initial Value of Shift Register
) SRLC16E_inst (
.Q(M_MESG_I[bit_cnt]), // SRL data output
.Q15(), // SRL cascade output pin
.A0(addr[0]), // 4-bit shift depth select input 0
.A1(addr[1]), // 4-bit shift depth select input 1
.A2(addr[2]), // 4-bit shift depth select input 2
.A3(addr[3]), // 4-bit shift depth select input 3
.CE(valid_Write), // Clock enable input
.CLK(ACLK), // Clock input
.D(S_MESG[bit_cnt]) // SRL data input
);
end // C_FIFO_DEPTH_LOG
end // end for bit_cnt
end // C_FAMILY
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Pipeline stage
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_ENABLE_REGISTERED_OUTPUT != 0 ) begin : USE_FF_OUT
wire [C_FIFO_WIDTH-1:0] M_MESG_FF; // Payload
wire M_VALID_FF; // FIFO not empty
// Select RTL or FPGA optimized instatiations for critical parts.
if ( C_FAMILY == "rtl" ) begin : USE_RTL_OUTPUT_PIPELINE
reg [C_FIFO_WIDTH-1:0] M_MESG_Q; // Payload
reg M_VALID_Q; // FIFO not empty
always @ (posedge ACLK) begin
if (ARESET) begin
M_MESG_Q <= {C_FIFO_WIDTH{1'b0}};
M_VALID_Q <= 1'b0;
end else begin
if ( M_READY_I ) begin
M_MESG_Q <= M_MESG_I;
M_VALID_Q <= M_VALID_I;
end
end
end
assign M_MESG_FF = M_MESG_Q;
assign M_VALID_FF = M_VALID_Q;
end else begin : USE_FPGA_OUTPUT_PIPELINE
reg [C_FIFO_WIDTH-1:0] M_MESG_CMB; // Payload
reg M_VALID_CMB; // FIFO not empty
always @ *
begin
if ( M_READY_I ) begin
M_MESG_CMB <= M_MESG_I;
M_VALID_CMB <= M_VALID_I;
end else begin
M_MESG_CMB <= M_MESG_FF;
M_VALID_CMB <= M_VALID_FF;
end
end
for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(M_MESG_FF[bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_MESG_CMB[bit_cnt]) // Data input
);
end // end for bit_cnt
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(M_VALID_FF), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_VALID_CMB) // Data input
);
end
assign EMPTY = ~M_VALID_I & ~M_VALID_FF;
assign M_MESG = M_MESG_FF;
assign M_VALID = M_VALID_FF;
assign M_READY_I = ( M_READY & M_VALID_FF ) | ~M_VALID_FF;
end else begin : NO_FF_OUT
assign EMPTY = ~M_VALID_I;
assign M_MESG = M_MESG_I;
assign M_VALID = M_VALID_I;
assign M_READY_I = M_READY;
end
endgenerate
endmodule |
module generic_baseblocks_v2_1_comparator_sel_mask_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign m_local = M;
assign v_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b0 ) ) |
( ( ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule |
module generic_baseblocks_v2_1_comparator_sel_mask_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign m_local = M;
assign v_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b0 ) ) |
( ( ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule |
module generic_baseblocks_v2_1_comparator_sel_mask_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign m_local = M;
assign v_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b0 ) ) |
( ( ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule |
module axi_data_fifo_v2_1_axic_fifo #
(
parameter C_FAMILY = "virtex6",
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [5:9] when TYPE="lut",
// Range = [5:12] when TYPE="bram",
parameter integer C_FIFO_WIDTH = 64, // Width of payload [1:512]
parameter C_FIFO_TYPE = "lut" // "lut" = LUT (SRL) based,
// "bram" = BRAM based
)
(
// Global inputs
input wire ACLK, // Clock
input wire ARESET, // Reset
// Slave Port
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)
input wire S_VALID, // FIFO push
output wire S_READY, // FIFO not full
// Master Port
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload
output wire M_VALID, // FIFO not empty
input wire M_READY // FIFO pop
);
axi_data_fifo_v2_1_fifo_gen #(
.C_FAMILY(C_FAMILY),
.C_COMMON_CLOCK(1),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(C_FIFO_WIDTH),
.C_FIFO_TYPE(C_FIFO_TYPE))
inst (
.clk(ACLK),
.rst(ARESET),
.wr_clk(1'b0),
.wr_en(S_VALID),
.wr_ready(S_READY),
.wr_data(S_MESG),
.rd_clk(1'b0),
.rd_en(M_READY),
.rd_valid(M_VALID),
.rd_data(M_MESG));
endmodule |
module axi_data_fifo_v2_1_axic_fifo #
(
parameter C_FAMILY = "virtex6",
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [5:9] when TYPE="lut",
// Range = [5:12] when TYPE="bram",
parameter integer C_FIFO_WIDTH = 64, // Width of payload [1:512]
parameter C_FIFO_TYPE = "lut" // "lut" = LUT (SRL) based,
// "bram" = BRAM based
)
(
// Global inputs
input wire ACLK, // Clock
input wire ARESET, // Reset
// Slave Port
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)
input wire S_VALID, // FIFO push
output wire S_READY, // FIFO not full
// Master Port
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload
output wire M_VALID, // FIFO not empty
input wire M_READY // FIFO pop
);
axi_data_fifo_v2_1_fifo_gen #(
.C_FAMILY(C_FAMILY),
.C_COMMON_CLOCK(1),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(C_FIFO_WIDTH),
.C_FIFO_TYPE(C_FIFO_TYPE))
inst (
.clk(ACLK),
.rst(ARESET),
.wr_clk(1'b0),
.wr_en(S_VALID),
.wr_ready(S_READY),
.wr_data(S_MESG),
.rd_clk(1'b0),
.rd_en(M_READY),
.rd_valid(M_VALID),
.rd_data(M_MESG));
endmodule |
module axi_data_fifo_v2_1_axic_fifo #
(
parameter C_FAMILY = "virtex6",
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [5:9] when TYPE="lut",
// Range = [5:12] when TYPE="bram",
parameter integer C_FIFO_WIDTH = 64, // Width of payload [1:512]
parameter C_FIFO_TYPE = "lut" // "lut" = LUT (SRL) based,
// "bram" = BRAM based
)
(
// Global inputs
input wire ACLK, // Clock
input wire ARESET, // Reset
// Slave Port
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)
input wire S_VALID, // FIFO push
output wire S_READY, // FIFO not full
// Master Port
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload
output wire M_VALID, // FIFO not empty
input wire M_READY // FIFO pop
);
axi_data_fifo_v2_1_fifo_gen #(
.C_FAMILY(C_FAMILY),
.C_COMMON_CLOCK(1),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(C_FIFO_WIDTH),
.C_FIFO_TYPE(C_FIFO_TYPE))
inst (
.clk(ACLK),
.rst(ARESET),
.wr_clk(1'b0),
.wr_en(S_VALID),
.wr_ready(S_READY),
.wr_data(S_MESG),
.rd_clk(1'b0),
.rd_en(M_READY),
.rd_valid(M_VALID),
.rd_data(M_MESG));
endmodule |
module axi_data_fifo_v2_1_axic_fifo #
(
parameter C_FAMILY = "virtex6",
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [5:9] when TYPE="lut",
// Range = [5:12] when TYPE="bram",
parameter integer C_FIFO_WIDTH = 64, // Width of payload [1:512]
parameter C_FIFO_TYPE = "lut" // "lut" = LUT (SRL) based,
// "bram" = BRAM based
)
(
// Global inputs
input wire ACLK, // Clock
input wire ARESET, // Reset
// Slave Port
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)
input wire S_VALID, // FIFO push
output wire S_READY, // FIFO not full
// Master Port
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload
output wire M_VALID, // FIFO not empty
input wire M_READY // FIFO pop
);
axi_data_fifo_v2_1_fifo_gen #(
.C_FAMILY(C_FAMILY),
.C_COMMON_CLOCK(1),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(C_FIFO_WIDTH),
.C_FIFO_TYPE(C_FIFO_TYPE))
inst (
.clk(ACLK),
.rst(ARESET),
.wr_clk(1'b0),
.wr_en(S_VALID),
.wr_ready(S_READY),
.wr_data(S_MESG),
.rd_clk(1'b0),
.rd_en(M_READY),
.rd_valid(M_VALID),
.rd_data(M_MESG));
endmodule |
module axi_data_fifo_v2_1_axic_fifo #
(
parameter C_FAMILY = "virtex6",
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [5:9] when TYPE="lut",
// Range = [5:12] when TYPE="bram",
parameter integer C_FIFO_WIDTH = 64, // Width of payload [1:512]
parameter C_FIFO_TYPE = "lut" // "lut" = LUT (SRL) based,
// "bram" = BRAM based
)
(
// Global inputs
input wire ACLK, // Clock
input wire ARESET, // Reset
// Slave Port
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)
input wire S_VALID, // FIFO push
output wire S_READY, // FIFO not full
// Master Port
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload
output wire M_VALID, // FIFO not empty
input wire M_READY // FIFO pop
);
axi_data_fifo_v2_1_fifo_gen #(
.C_FAMILY(C_FAMILY),
.C_COMMON_CLOCK(1),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(C_FIFO_WIDTH),
.C_FIFO_TYPE(C_FIFO_TYPE))
inst (
.clk(ACLK),
.rst(ARESET),
.wr_clk(1'b0),
.wr_en(S_VALID),
.wr_ready(S_READY),
.wr_data(S_MESG),
.rd_clk(1'b0),
.rd_en(M_READY),
.rd_valid(M_VALID),
.rd_data(M_MESG));
endmodule |
module axi_data_fifo_v2_1_axic_fifo #
(
parameter C_FAMILY = "virtex6",
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [5:9] when TYPE="lut",
// Range = [5:12] when TYPE="bram",
parameter integer C_FIFO_WIDTH = 64, // Width of payload [1:512]
parameter C_FIFO_TYPE = "lut" // "lut" = LUT (SRL) based,
// "bram" = BRAM based
)
(
// Global inputs
input wire ACLK, // Clock
input wire ARESET, // Reset
// Slave Port
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)
input wire S_VALID, // FIFO push
output wire S_READY, // FIFO not full
// Master Port
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload
output wire M_VALID, // FIFO not empty
input wire M_READY // FIFO pop
);
axi_data_fifo_v2_1_fifo_gen #(
.C_FAMILY(C_FAMILY),
.C_COMMON_CLOCK(1),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(C_FIFO_WIDTH),
.C_FIFO_TYPE(C_FIFO_TYPE))
inst (
.clk(ACLK),
.rst(ARESET),
.wr_clk(1'b0),
.wr_en(S_VALID),
.wr_ready(S_READY),
.wr_data(S_MESG),
.rd_clk(1'b0),
.rd_en(M_READY),
.rd_valid(M_VALID),
.rd_data(M_MESG));
endmodule |
module axi_data_fifo_v2_1_axic_fifo #
(
parameter C_FAMILY = "virtex6",
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [5:9] when TYPE="lut",
// Range = [5:12] when TYPE="bram",
parameter integer C_FIFO_WIDTH = 64, // Width of payload [1:512]
parameter C_FIFO_TYPE = "lut" // "lut" = LUT (SRL) based,
// "bram" = BRAM based
)
(
// Global inputs
input wire ACLK, // Clock
input wire ARESET, // Reset
// Slave Port
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)
input wire S_VALID, // FIFO push
output wire S_READY, // FIFO not full
// Master Port
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload
output wire M_VALID, // FIFO not empty
input wire M_READY // FIFO pop
);
axi_data_fifo_v2_1_fifo_gen #(
.C_FAMILY(C_FAMILY),
.C_COMMON_CLOCK(1),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(C_FIFO_WIDTH),
.C_FIFO_TYPE(C_FIFO_TYPE))
inst (
.clk(ACLK),
.rst(ARESET),
.wr_clk(1'b0),
.wr_en(S_VALID),
.wr_ready(S_READY),
.wr_data(S_MESG),
.rd_clk(1'b0),
.rd_en(M_READY),
.rd_valid(M_VALID),
.rd_data(M_MESG));
endmodule |
module generic_baseblocks_v2_1_comparator_sel #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] V,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = V;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule |
module generic_baseblocks_v2_1_comparator_sel #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] V,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = V;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule |
module generic_baseblocks_v2_1_comparator_sel #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] V,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = V;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule |
module generic_baseblocks_v2_1_comparator_sel #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] V,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = V;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule |
module generic_baseblocks_v2_1_comparator_sel #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] V,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = V;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule |
module generic_baseblocks_v2_1_comparator_sel #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] V,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = V;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule |
module generic_baseblocks_v2_1_mux_enc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_RATIO = 4,
// Mux select ratio. Can be any binary value (>= 1)
parameter integer C_SEL_WIDTH = 2,
// Log2-ceiling of C_RATIO (>= 1)
parameter integer C_DATA_WIDTH = 1
// Data width for generic_baseblocks_v2_1_comparator (>= 1)
)
(
input wire [C_SEL_WIDTH-1:0] S,
input wire [C_RATIO*C_DATA_WIDTH-1:0] A,
output wire [C_DATA_WIDTH-1:0] O,
input wire OE
);
wire [C_DATA_WIDTH-1:0] o_i;
genvar bit_cnt;
function [C_DATA_WIDTH-1:0] f_mux
(
input [C_SEL_WIDTH-1:0] s,
input [C_RATIO*C_DATA_WIDTH-1:0] a
);
integer i;
reg [C_RATIO*C_DATA_WIDTH-1:0] carry;
begin
carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc
carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] =
carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |
({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);
end
f_mux = carry[C_DATA_WIDTH*C_RATIO-1:C_DATA_WIDTH*(C_RATIO-1)];
end
endfunction
function [C_DATA_WIDTH-1:0] f_mux4
(
input [1:0] s,
input [4*C_DATA_WIDTH-1:0] a
);
integer i;
reg [4*C_DATA_WIDTH-1:0] carry;
begin
carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];
for (i=1;i<4;i=i+1) begin : gen_carrychain_enc
carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] =
carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |
({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);
end
f_mux4 = carry[C_DATA_WIDTH*4-1:C_DATA_WIDTH*3];
end
endfunction
assign O = o_i & {C_DATA_WIDTH{OE}}; // OE is gated AFTER any MUXF7/8 (can only optimize forward into downstream logic)
generate
if ( C_RATIO < 2 ) begin : gen_bypass
assign o_i = A;
end else if ( C_FAMILY == "rtl" || C_RATIO < 5 ) begin : gen_rtl
assign o_i = f_mux(S, A);
end else begin : gen_fpga
wire [C_DATA_WIDTH-1:0] l;
wire [C_DATA_WIDTH-1:0] h;
wire [C_DATA_WIDTH-1:0] ll;
wire [C_DATA_WIDTH-1:0] lh;
wire [C_DATA_WIDTH-1:0] hl;
wire [C_DATA_WIDTH-1:0] hh;
case (C_RATIO)
1, 5, 9, 13:
assign hh = A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH];
2, 6, 10, 14:
assign hh = S[0] ?
A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ;
3, 7, 11, 15:
assign hh = S[1] ?
A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
(S[0] ?
A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] );
4, 8, 12, 16:
assign hh = S[1] ?
(S[0] ?
A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ) :
(S[0] ?
A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-4)*C_DATA_WIDTH +: C_DATA_WIDTH] );
17:
assign hh = S[1] ?
(S[0] ?
A[15*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[14*C_DATA_WIDTH +: C_DATA_WIDTH] ) :
(S[0] ?
A[13*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[12*C_DATA_WIDTH +: C_DATA_WIDTH] );
default:
assign hh = 0;
endcase
case (C_RATIO)
5, 6, 7, 8: begin
assign l = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_5_8
MUXF7 mux_s2_inst
(
.I0 (l[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[2]),
.O (o_i[bit_cnt])
);
end
end
9, 10, 11, 12: begin
assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_9_12
MUXF7 muxf_s2_low_inst
(
.I0 (ll[bit_cnt]),
.I1 (lh[bit_cnt]),
.S (S[2]),
.O (l[bit_cnt])
);
MUXF8 muxf_s3_inst
(
.I0 (l[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[3]),
.O (o_i[bit_cnt])
);
end
end
13,14,15,16: begin
assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_13_16
MUXF7 muxf_s2_low_inst
(
.I0 (ll[bit_cnt]),
.I1 (lh[bit_cnt]),
.S (S[2]),
.O (l[bit_cnt])
);
MUXF7 muxf_s2_hi_inst
(
.I0 (hl[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[2]),
.O (h[bit_cnt])
);
MUXF8 muxf_s3_inst
(
.I0 (l[bit_cnt]),
.I1 (h[bit_cnt]),
.S (S[3]),
.O (o_i[bit_cnt])
);
end
end
17: begin
assign ll = S[4] ? A[16*C_DATA_WIDTH +: C_DATA_WIDTH] : f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]); // 5-input mux
assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_17
MUXF7 muxf_s2_low_inst
(
.I0 (ll[bit_cnt]),
.I1 (lh[bit_cnt]),
.S (S[2]),
.O (l[bit_cnt])
);
MUXF7 muxf_s2_hi_inst
(
.I0 (hl[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[2]),
.O (h[bit_cnt])
);
MUXF8 muxf_s3_inst
(
.I0 (l[bit_cnt]),
.I1 (h[bit_cnt]),
.S (S[3]),
.O (o_i[bit_cnt])
);
end
end
default: // If RATIO > 17, use RTL
assign o_i = f_mux(S, A);
endcase
end // gen_fpga
endgenerate
endmodule |
module generic_baseblocks_v2_1_mux_enc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_RATIO = 4,
// Mux select ratio. Can be any binary value (>= 1)
parameter integer C_SEL_WIDTH = 2,
// Log2-ceiling of C_RATIO (>= 1)
parameter integer C_DATA_WIDTH = 1
// Data width for generic_baseblocks_v2_1_comparator (>= 1)
)
(
input wire [C_SEL_WIDTH-1:0] S,
input wire [C_RATIO*C_DATA_WIDTH-1:0] A,
output wire [C_DATA_WIDTH-1:0] O,
input wire OE
);
wire [C_DATA_WIDTH-1:0] o_i;
genvar bit_cnt;
function [C_DATA_WIDTH-1:0] f_mux
(
input [C_SEL_WIDTH-1:0] s,
input [C_RATIO*C_DATA_WIDTH-1:0] a
);
integer i;
reg [C_RATIO*C_DATA_WIDTH-1:0] carry;
begin
carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc
carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] =
carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |
({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);
end
f_mux = carry[C_DATA_WIDTH*C_RATIO-1:C_DATA_WIDTH*(C_RATIO-1)];
end
endfunction
function [C_DATA_WIDTH-1:0] f_mux4
(
input [1:0] s,
input [4*C_DATA_WIDTH-1:0] a
);
integer i;
reg [4*C_DATA_WIDTH-1:0] carry;
begin
carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];
for (i=1;i<4;i=i+1) begin : gen_carrychain_enc
carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] =
carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |
({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);
end
f_mux4 = carry[C_DATA_WIDTH*4-1:C_DATA_WIDTH*3];
end
endfunction
assign O = o_i & {C_DATA_WIDTH{OE}}; // OE is gated AFTER any MUXF7/8 (can only optimize forward into downstream logic)
generate
if ( C_RATIO < 2 ) begin : gen_bypass
assign o_i = A;
end else if ( C_FAMILY == "rtl" || C_RATIO < 5 ) begin : gen_rtl
assign o_i = f_mux(S, A);
end else begin : gen_fpga
wire [C_DATA_WIDTH-1:0] l;
wire [C_DATA_WIDTH-1:0] h;
wire [C_DATA_WIDTH-1:0] ll;
wire [C_DATA_WIDTH-1:0] lh;
wire [C_DATA_WIDTH-1:0] hl;
wire [C_DATA_WIDTH-1:0] hh;
case (C_RATIO)
1, 5, 9, 13:
assign hh = A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH];
2, 6, 10, 14:
assign hh = S[0] ?
A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ;
3, 7, 11, 15:
assign hh = S[1] ?
A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
(S[0] ?
A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] );
4, 8, 12, 16:
assign hh = S[1] ?
(S[0] ?
A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ) :
(S[0] ?
A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-4)*C_DATA_WIDTH +: C_DATA_WIDTH] );
17:
assign hh = S[1] ?
(S[0] ?
A[15*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[14*C_DATA_WIDTH +: C_DATA_WIDTH] ) :
(S[0] ?
A[13*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[12*C_DATA_WIDTH +: C_DATA_WIDTH] );
default:
assign hh = 0;
endcase
case (C_RATIO)
5, 6, 7, 8: begin
assign l = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_5_8
MUXF7 mux_s2_inst
(
.I0 (l[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[2]),
.O (o_i[bit_cnt])
);
end
end
9, 10, 11, 12: begin
assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_9_12
MUXF7 muxf_s2_low_inst
(
.I0 (ll[bit_cnt]),
.I1 (lh[bit_cnt]),
.S (S[2]),
.O (l[bit_cnt])
);
MUXF8 muxf_s3_inst
(
.I0 (l[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[3]),
.O (o_i[bit_cnt])
);
end
end
13,14,15,16: begin
assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_13_16
MUXF7 muxf_s2_low_inst
(
.I0 (ll[bit_cnt]),
.I1 (lh[bit_cnt]),
.S (S[2]),
.O (l[bit_cnt])
);
MUXF7 muxf_s2_hi_inst
(
.I0 (hl[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[2]),
.O (h[bit_cnt])
);
MUXF8 muxf_s3_inst
(
.I0 (l[bit_cnt]),
.I1 (h[bit_cnt]),
.S (S[3]),
.O (o_i[bit_cnt])
);
end
end
17: begin
assign ll = S[4] ? A[16*C_DATA_WIDTH +: C_DATA_WIDTH] : f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]); // 5-input mux
assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_17
MUXF7 muxf_s2_low_inst
(
.I0 (ll[bit_cnt]),
.I1 (lh[bit_cnt]),
.S (S[2]),
.O (l[bit_cnt])
);
MUXF7 muxf_s2_hi_inst
(
.I0 (hl[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[2]),
.O (h[bit_cnt])
);
MUXF8 muxf_s3_inst
(
.I0 (l[bit_cnt]),
.I1 (h[bit_cnt]),
.S (S[3]),
.O (o_i[bit_cnt])
);
end
end
default: // If RATIO > 17, use RTL
assign o_i = f_mux(S, A);
endcase
end // gen_fpga
endgenerate
endmodule |
module axi_data_fifo_v2_1_axic_reg_srl_fifo #
(
parameter C_FAMILY = "none", // FPGA Family
parameter integer C_FIFO_WIDTH = 1, // Width of S_MESG/M_MESG.
parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits
// the control logic can be used
// on before the control logic
// needs to be replicated.
parameter integer C_FIFO_DEPTH_LOG = 2, // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.
// The minimum size fifo generated is 4-deep.
parameter C_USE_FULL = 1 // Prevent overwrite by throttling S_READY.
)
(
input wire ACLK, // Clock
input wire ARESET, // Reset
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Input data
input wire S_VALID, // Input data valid
output wire S_READY, // Input data ready
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Output data
output wire M_VALID, // Output data valid
input wire M_READY // Output data ready
);
localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;
localparam P_EMPTY = {P_FIFO_DEPTH_LOG{1'b1}};
localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1'b0}};
localparam P_ALMOSTFULL_TEMP = {P_EMPTY, 1'b0};
localparam P_ALMOSTFULL = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];
localparam P_NUM_REPS = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?
(C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :
((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;
(* syn_keep = "1" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr;
(* syn_keep = "1" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;
genvar i;
genvar j;
reg m_valid_i;
reg s_ready_i;
wire push; // FIFO push
wire pop; // FIFO pop
reg areset_d1; // Reset delay register
reg [C_FIFO_WIDTH-1:0] storage_data1;
wire [C_FIFO_WIDTH-1:0] storage_data2; // Intermediate SRL data
reg load_s1;
wire load_s1_from_s2;
reg [1:0] state;
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
assign M_VALID = m_valid_i;
assign S_READY = C_USE_FULL ? s_ready_i : 1'b1;
assign push = (S_VALID & (C_USE_FULL ? s_ready_i : 1'b1) & (state == TWO)) | (~M_READY & S_VALID & (state == ONE));
assign pop = M_READY & (state == TWO);
assign M_MESG = storage_data1;
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_MESG;
end
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1'b1;
else
load_s1 = 1'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK)
begin
if (areset_d1) begin
state <= ZERO;
m_valid_i <= 1'b0;
end else begin
case (state)
// No transaction stored locally
ZERO: begin
if (S_VALID) begin
state <= ONE; // Got one so move to ONE
m_valid_i <= 1'b1;
end
end
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) begin
state <= ZERO; // Read out one so move to ZERO
m_valid_i <= 1'b0;
end else if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
m_valid_i <= 1'b1;
end
end
// TWO transaction stored locally
TWO: begin
if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTEMPTY) && pop && ~push) begin
state <= ONE; // Read out one so move to ONE
m_valid_i <= 1'b1;
end
end
endcase // case (state)
end
end // always @ (posedge ACLK)
generate
//---------------------------------------------------------------------------
// Create count of number of elements in FIFOs
//---------------------------------------------------------------------------
for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep
assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] =
push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;
always @(posedge ACLK) begin
if (ARESET)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
{P_FIFO_DEPTH_LOG{1'b1}};
else if (push ^ pop)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];
end
end
always @(posedge ACLK) begin
if (ARESET) begin
s_ready_i <= 1'b0;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else if (C_USE_FULL &&
((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTFULL) && push && ~pop)) begin
s_ready_i <= 1'b0;
end else if (C_USE_FULL && pop) begin
s_ready_i <= 1'b1;
end
end
//---------------------------------------------------------------------------
// Instantiate SRLs
//---------------------------------------------------------------------------
for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls
for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep
axi_data_fifo_v2_1_ndeep_srl #
(
.C_FAMILY (C_FAMILY),
.C_A_WIDTH (P_FIFO_DEPTH_LOG)
)
srl_nx1
(
.CLK (ACLK),
.A (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:
P_FIFO_DEPTH_LOG*(i)]),
.CE (push),
.D (S_MESG[i*C_MAX_CTRL_FANOUT+j]),
.Q (storage_data2[i*C_MAX_CTRL_FANOUT+j])
);
end
end
endgenerate
endmodule |
module axi_data_fifo_v2_1_axic_reg_srl_fifo #
(
parameter C_FAMILY = "none", // FPGA Family
parameter integer C_FIFO_WIDTH = 1, // Width of S_MESG/M_MESG.
parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits
// the control logic can be used
// on before the control logic
// needs to be replicated.
parameter integer C_FIFO_DEPTH_LOG = 2, // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.
// The minimum size fifo generated is 4-deep.
parameter C_USE_FULL = 1 // Prevent overwrite by throttling S_READY.
)
(
input wire ACLK, // Clock
input wire ARESET, // Reset
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Input data
input wire S_VALID, // Input data valid
output wire S_READY, // Input data ready
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Output data
output wire M_VALID, // Output data valid
input wire M_READY // Output data ready
);
localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;
localparam P_EMPTY = {P_FIFO_DEPTH_LOG{1'b1}};
localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1'b0}};
localparam P_ALMOSTFULL_TEMP = {P_EMPTY, 1'b0};
localparam P_ALMOSTFULL = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];
localparam P_NUM_REPS = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?
(C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :
((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;
(* syn_keep = "1" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr;
(* syn_keep = "1" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;
genvar i;
genvar j;
reg m_valid_i;
reg s_ready_i;
wire push; // FIFO push
wire pop; // FIFO pop
reg areset_d1; // Reset delay register
reg [C_FIFO_WIDTH-1:0] storage_data1;
wire [C_FIFO_WIDTH-1:0] storage_data2; // Intermediate SRL data
reg load_s1;
wire load_s1_from_s2;
reg [1:0] state;
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
assign M_VALID = m_valid_i;
assign S_READY = C_USE_FULL ? s_ready_i : 1'b1;
assign push = (S_VALID & (C_USE_FULL ? s_ready_i : 1'b1) & (state == TWO)) | (~M_READY & S_VALID & (state == ONE));
assign pop = M_READY & (state == TWO);
assign M_MESG = storage_data1;
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_MESG;
end
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1'b1;
else
load_s1 = 1'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK)
begin
if (areset_d1) begin
state <= ZERO;
m_valid_i <= 1'b0;
end else begin
case (state)
// No transaction stored locally
ZERO: begin
if (S_VALID) begin
state <= ONE; // Got one so move to ONE
m_valid_i <= 1'b1;
end
end
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) begin
state <= ZERO; // Read out one so move to ZERO
m_valid_i <= 1'b0;
end else if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
m_valid_i <= 1'b1;
end
end
// TWO transaction stored locally
TWO: begin
if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTEMPTY) && pop && ~push) begin
state <= ONE; // Read out one so move to ONE
m_valid_i <= 1'b1;
end
end
endcase // case (state)
end
end // always @ (posedge ACLK)
generate
//---------------------------------------------------------------------------
// Create count of number of elements in FIFOs
//---------------------------------------------------------------------------
for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep
assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] =
push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;
always @(posedge ACLK) begin
if (ARESET)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
{P_FIFO_DEPTH_LOG{1'b1}};
else if (push ^ pop)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];
end
end
always @(posedge ACLK) begin
if (ARESET) begin
s_ready_i <= 1'b0;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else if (C_USE_FULL &&
((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTFULL) && push && ~pop)) begin
s_ready_i <= 1'b0;
end else if (C_USE_FULL && pop) begin
s_ready_i <= 1'b1;
end
end
//---------------------------------------------------------------------------
// Instantiate SRLs
//---------------------------------------------------------------------------
for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls
for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep
axi_data_fifo_v2_1_ndeep_srl #
(
.C_FAMILY (C_FAMILY),
.C_A_WIDTH (P_FIFO_DEPTH_LOG)
)
srl_nx1
(
.CLK (ACLK),
.A (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:
P_FIFO_DEPTH_LOG*(i)]),
.CE (push),
.D (S_MESG[i*C_MAX_CTRL_FANOUT+j]),
.Q (storage_data2[i*C_MAX_CTRL_FANOUT+j])
);
end
end
endgenerate
endmodule |
module axi_data_fifo_v2_1_axic_reg_srl_fifo #
(
parameter C_FAMILY = "none", // FPGA Family
parameter integer C_FIFO_WIDTH = 1, // Width of S_MESG/M_MESG.
parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits
// the control logic can be used
// on before the control logic
// needs to be replicated.
parameter integer C_FIFO_DEPTH_LOG = 2, // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.
// The minimum size fifo generated is 4-deep.
parameter C_USE_FULL = 1 // Prevent overwrite by throttling S_READY.
)
(
input wire ACLK, // Clock
input wire ARESET, // Reset
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Input data
input wire S_VALID, // Input data valid
output wire S_READY, // Input data ready
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Output data
output wire M_VALID, // Output data valid
input wire M_READY // Output data ready
);
localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;
localparam P_EMPTY = {P_FIFO_DEPTH_LOG{1'b1}};
localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1'b0}};
localparam P_ALMOSTFULL_TEMP = {P_EMPTY, 1'b0};
localparam P_ALMOSTFULL = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];
localparam P_NUM_REPS = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?
(C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :
((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;
(* syn_keep = "1" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr;
(* syn_keep = "1" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;
genvar i;
genvar j;
reg m_valid_i;
reg s_ready_i;
wire push; // FIFO push
wire pop; // FIFO pop
reg areset_d1; // Reset delay register
reg [C_FIFO_WIDTH-1:0] storage_data1;
wire [C_FIFO_WIDTH-1:0] storage_data2; // Intermediate SRL data
reg load_s1;
wire load_s1_from_s2;
reg [1:0] state;
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
assign M_VALID = m_valid_i;
assign S_READY = C_USE_FULL ? s_ready_i : 1'b1;
assign push = (S_VALID & (C_USE_FULL ? s_ready_i : 1'b1) & (state == TWO)) | (~M_READY & S_VALID & (state == ONE));
assign pop = M_READY & (state == TWO);
assign M_MESG = storage_data1;
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_MESG;
end
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1'b1;
else
load_s1 = 1'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK)
begin
if (areset_d1) begin
state <= ZERO;
m_valid_i <= 1'b0;
end else begin
case (state)
// No transaction stored locally
ZERO: begin
if (S_VALID) begin
state <= ONE; // Got one so move to ONE
m_valid_i <= 1'b1;
end
end
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) begin
state <= ZERO; // Read out one so move to ZERO
m_valid_i <= 1'b0;
end else if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
m_valid_i <= 1'b1;
end
end
// TWO transaction stored locally
TWO: begin
if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTEMPTY) && pop && ~push) begin
state <= ONE; // Read out one so move to ONE
m_valid_i <= 1'b1;
end
end
endcase // case (state)
end
end // always @ (posedge ACLK)
generate
//---------------------------------------------------------------------------
// Create count of number of elements in FIFOs
//---------------------------------------------------------------------------
for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep
assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] =
push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;
always @(posedge ACLK) begin
if (ARESET)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
{P_FIFO_DEPTH_LOG{1'b1}};
else if (push ^ pop)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];
end
end
always @(posedge ACLK) begin
if (ARESET) begin
s_ready_i <= 1'b0;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else if (C_USE_FULL &&
((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTFULL) && push && ~pop)) begin
s_ready_i <= 1'b0;
end else if (C_USE_FULL && pop) begin
s_ready_i <= 1'b1;
end
end
//---------------------------------------------------------------------------
// Instantiate SRLs
//---------------------------------------------------------------------------
for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls
for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep
axi_data_fifo_v2_1_ndeep_srl #
(
.C_FAMILY (C_FAMILY),
.C_A_WIDTH (P_FIFO_DEPTH_LOG)
)
srl_nx1
(
.CLK (ACLK),
.A (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:
P_FIFO_DEPTH_LOG*(i)]),
.CE (push),
.D (S_MESG[i*C_MAX_CTRL_FANOUT+j]),
.Q (storage_data2[i*C_MAX_CTRL_FANOUT+j])
);
end
end
endgenerate
endmodule |
module axi_data_fifo_v2_1_axic_reg_srl_fifo #
(
parameter C_FAMILY = "none", // FPGA Family
parameter integer C_FIFO_WIDTH = 1, // Width of S_MESG/M_MESG.
parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits
// the control logic can be used
// on before the control logic
// needs to be replicated.
parameter integer C_FIFO_DEPTH_LOG = 2, // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.
// The minimum size fifo generated is 4-deep.
parameter C_USE_FULL = 1 // Prevent overwrite by throttling S_READY.
)
(
input wire ACLK, // Clock
input wire ARESET, // Reset
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Input data
input wire S_VALID, // Input data valid
output wire S_READY, // Input data ready
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Output data
output wire M_VALID, // Output data valid
input wire M_READY // Output data ready
);
localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;
localparam P_EMPTY = {P_FIFO_DEPTH_LOG{1'b1}};
localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1'b0}};
localparam P_ALMOSTFULL_TEMP = {P_EMPTY, 1'b0};
localparam P_ALMOSTFULL = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];
localparam P_NUM_REPS = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?
(C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :
((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;
(* syn_keep = "1" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr;
(* syn_keep = "1" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;
genvar i;
genvar j;
reg m_valid_i;
reg s_ready_i;
wire push; // FIFO push
wire pop; // FIFO pop
reg areset_d1; // Reset delay register
reg [C_FIFO_WIDTH-1:0] storage_data1;
wire [C_FIFO_WIDTH-1:0] storage_data2; // Intermediate SRL data
reg load_s1;
wire load_s1_from_s2;
reg [1:0] state;
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
assign M_VALID = m_valid_i;
assign S_READY = C_USE_FULL ? s_ready_i : 1'b1;
assign push = (S_VALID & (C_USE_FULL ? s_ready_i : 1'b1) & (state == TWO)) | (~M_READY & S_VALID & (state == ONE));
assign pop = M_READY & (state == TWO);
assign M_MESG = storage_data1;
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_MESG;
end
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1'b1;
else
load_s1 = 1'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK)
begin
if (areset_d1) begin
state <= ZERO;
m_valid_i <= 1'b0;
end else begin
case (state)
// No transaction stored locally
ZERO: begin
if (S_VALID) begin
state <= ONE; // Got one so move to ONE
m_valid_i <= 1'b1;
end
end
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) begin
state <= ZERO; // Read out one so move to ZERO
m_valid_i <= 1'b0;
end else if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
m_valid_i <= 1'b1;
end
end
// TWO transaction stored locally
TWO: begin
if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTEMPTY) && pop && ~push) begin
state <= ONE; // Read out one so move to ONE
m_valid_i <= 1'b1;
end
end
endcase // case (state)
end
end // always @ (posedge ACLK)
generate
//---------------------------------------------------------------------------
// Create count of number of elements in FIFOs
//---------------------------------------------------------------------------
for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep
assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] =
push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;
always @(posedge ACLK) begin
if (ARESET)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
{P_FIFO_DEPTH_LOG{1'b1}};
else if (push ^ pop)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];
end
end
always @(posedge ACLK) begin
if (ARESET) begin
s_ready_i <= 1'b0;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else if (C_USE_FULL &&
((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTFULL) && push && ~pop)) begin
s_ready_i <= 1'b0;
end else if (C_USE_FULL && pop) begin
s_ready_i <= 1'b1;
end
end
//---------------------------------------------------------------------------
// Instantiate SRLs
//---------------------------------------------------------------------------
for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls
for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep
axi_data_fifo_v2_1_ndeep_srl #
(
.C_FAMILY (C_FAMILY),
.C_A_WIDTH (P_FIFO_DEPTH_LOG)
)
srl_nx1
(
.CLK (ACLK),
.A (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:
P_FIFO_DEPTH_LOG*(i)]),
.CE (push),
.D (S_MESG[i*C_MAX_CTRL_FANOUT+j]),
.Q (storage_data2[i*C_MAX_CTRL_FANOUT+j])
);
end
end
endgenerate
endmodule |
module axi_data_fifo_v2_1_axic_reg_srl_fifo #
(
parameter C_FAMILY = "none", // FPGA Family
parameter integer C_FIFO_WIDTH = 1, // Width of S_MESG/M_MESG.
parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits
// the control logic can be used
// on before the control logic
// needs to be replicated.
parameter integer C_FIFO_DEPTH_LOG = 2, // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.
// The minimum size fifo generated is 4-deep.
parameter C_USE_FULL = 1 // Prevent overwrite by throttling S_READY.
)
(
input wire ACLK, // Clock
input wire ARESET, // Reset
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Input data
input wire S_VALID, // Input data valid
output wire S_READY, // Input data ready
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Output data
output wire M_VALID, // Output data valid
input wire M_READY // Output data ready
);
localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;
localparam P_EMPTY = {P_FIFO_DEPTH_LOG{1'b1}};
localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1'b0}};
localparam P_ALMOSTFULL_TEMP = {P_EMPTY, 1'b0};
localparam P_ALMOSTFULL = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];
localparam P_NUM_REPS = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?
(C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :
((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;
(* syn_keep = "1" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr;
(* syn_keep = "1" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;
genvar i;
genvar j;
reg m_valid_i;
reg s_ready_i;
wire push; // FIFO push
wire pop; // FIFO pop
reg areset_d1; // Reset delay register
reg [C_FIFO_WIDTH-1:0] storage_data1;
wire [C_FIFO_WIDTH-1:0] storage_data2; // Intermediate SRL data
reg load_s1;
wire load_s1_from_s2;
reg [1:0] state;
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
assign M_VALID = m_valid_i;
assign S_READY = C_USE_FULL ? s_ready_i : 1'b1;
assign push = (S_VALID & (C_USE_FULL ? s_ready_i : 1'b1) & (state == TWO)) | (~M_READY & S_VALID & (state == ONE));
assign pop = M_READY & (state == TWO);
assign M_MESG = storage_data1;
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_MESG;
end
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1'b1;
else
load_s1 = 1'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK)
begin
if (areset_d1) begin
state <= ZERO;
m_valid_i <= 1'b0;
end else begin
case (state)
// No transaction stored locally
ZERO: begin
if (S_VALID) begin
state <= ONE; // Got one so move to ONE
m_valid_i <= 1'b1;
end
end
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) begin
state <= ZERO; // Read out one so move to ZERO
m_valid_i <= 1'b0;
end else if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
m_valid_i <= 1'b1;
end
end
// TWO transaction stored locally
TWO: begin
if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTEMPTY) && pop && ~push) begin
state <= ONE; // Read out one so move to ONE
m_valid_i <= 1'b1;
end
end
endcase // case (state)
end
end // always @ (posedge ACLK)
generate
//---------------------------------------------------------------------------
// Create count of number of elements in FIFOs
//---------------------------------------------------------------------------
for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep
assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] =
push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;
always @(posedge ACLK) begin
if (ARESET)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
{P_FIFO_DEPTH_LOG{1'b1}};
else if (push ^ pop)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];
end
end
always @(posedge ACLK) begin
if (ARESET) begin
s_ready_i <= 1'b0;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else if (C_USE_FULL &&
((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTFULL) && push && ~pop)) begin
s_ready_i <= 1'b0;
end else if (C_USE_FULL && pop) begin
s_ready_i <= 1'b1;
end
end
//---------------------------------------------------------------------------
// Instantiate SRLs
//---------------------------------------------------------------------------
for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls
for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep
axi_data_fifo_v2_1_ndeep_srl #
(
.C_FAMILY (C_FAMILY),
.C_A_WIDTH (P_FIFO_DEPTH_LOG)
)
srl_nx1
(
.CLK (ACLK),
.A (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:
P_FIFO_DEPTH_LOG*(i)]),
.CE (push),
.D (S_MESG[i*C_MAX_CTRL_FANOUT+j]),
.Q (storage_data2[i*C_MAX_CTRL_FANOUT+j])
);
end
end
endgenerate
endmodule |
module axi_data_fifo_v2_1_axic_reg_srl_fifo #
(
parameter C_FAMILY = "none", // FPGA Family
parameter integer C_FIFO_WIDTH = 1, // Width of S_MESG/M_MESG.
parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits
// the control logic can be used
// on before the control logic
// needs to be replicated.
parameter integer C_FIFO_DEPTH_LOG = 2, // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.
// The minimum size fifo generated is 4-deep.
parameter C_USE_FULL = 1 // Prevent overwrite by throttling S_READY.
)
(
input wire ACLK, // Clock
input wire ARESET, // Reset
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Input data
input wire S_VALID, // Input data valid
output wire S_READY, // Input data ready
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Output data
output wire M_VALID, // Output data valid
input wire M_READY // Output data ready
);
localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;
localparam P_EMPTY = {P_FIFO_DEPTH_LOG{1'b1}};
localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1'b0}};
localparam P_ALMOSTFULL_TEMP = {P_EMPTY, 1'b0};
localparam P_ALMOSTFULL = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];
localparam P_NUM_REPS = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?
(C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :
((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;
(* syn_keep = "1" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr;
(* syn_keep = "1" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;
genvar i;
genvar j;
reg m_valid_i;
reg s_ready_i;
wire push; // FIFO push
wire pop; // FIFO pop
reg areset_d1; // Reset delay register
reg [C_FIFO_WIDTH-1:0] storage_data1;
wire [C_FIFO_WIDTH-1:0] storage_data2; // Intermediate SRL data
reg load_s1;
wire load_s1_from_s2;
reg [1:0] state;
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
assign M_VALID = m_valid_i;
assign S_READY = C_USE_FULL ? s_ready_i : 1'b1;
assign push = (S_VALID & (C_USE_FULL ? s_ready_i : 1'b1) & (state == TWO)) | (~M_READY & S_VALID & (state == ONE));
assign pop = M_READY & (state == TWO);
assign M_MESG = storage_data1;
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_MESG;
end
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1'b1;
else
load_s1 = 1'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK)
begin
if (areset_d1) begin
state <= ZERO;
m_valid_i <= 1'b0;
end else begin
case (state)
// No transaction stored locally
ZERO: begin
if (S_VALID) begin
state <= ONE; // Got one so move to ONE
m_valid_i <= 1'b1;
end
end
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) begin
state <= ZERO; // Read out one so move to ZERO
m_valid_i <= 1'b0;
end else if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
m_valid_i <= 1'b1;
end
end
// TWO transaction stored locally
TWO: begin
if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTEMPTY) && pop && ~push) begin
state <= ONE; // Read out one so move to ONE
m_valid_i <= 1'b1;
end
end
endcase // case (state)
end
end // always @ (posedge ACLK)
generate
//---------------------------------------------------------------------------
// Create count of number of elements in FIFOs
//---------------------------------------------------------------------------
for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep
assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] =
push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;
always @(posedge ACLK) begin
if (ARESET)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
{P_FIFO_DEPTH_LOG{1'b1}};
else if (push ^ pop)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];
end
end
always @(posedge ACLK) begin
if (ARESET) begin
s_ready_i <= 1'b0;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else if (C_USE_FULL &&
((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTFULL) && push && ~pop)) begin
s_ready_i <= 1'b0;
end else if (C_USE_FULL && pop) begin
s_ready_i <= 1'b1;
end
end
//---------------------------------------------------------------------------
// Instantiate SRLs
//---------------------------------------------------------------------------
for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls
for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep
axi_data_fifo_v2_1_ndeep_srl #
(
.C_FAMILY (C_FAMILY),
.C_A_WIDTH (P_FIFO_DEPTH_LOG)
)
srl_nx1
(
.CLK (ACLK),
.A (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:
P_FIFO_DEPTH_LOG*(i)]),
.CE (push),
.D (S_MESG[i*C_MAX_CTRL_FANOUT+j]),
.Q (storage_data2[i*C_MAX_CTRL_FANOUT+j])
);
end
end
endgenerate
endmodule |
module generic_baseblocks_v2_1_comparator_sel_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule |
module generic_baseblocks_v2_1_comparator_sel_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule |
module generic_baseblocks_v2_1_comparator_sel_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule |
module axi_data_fifo_v2_1_axic_srl_fifo #
(
parameter C_FAMILY = "none", // FPGA Family
parameter integer C_FIFO_WIDTH = 1, // Width of S_MESG/M_MESG.
parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits
// the control logic can be used
// on before the control logic
// needs to be replicated.
parameter integer C_FIFO_DEPTH_LOG = 2, // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.
// The minimum size fifo generated is 4-deep.
parameter C_USE_FULL = 1 // Prevent overwrite by throttling S_READY.
)
(
input wire ACLK, // Clock
input wire ARESET, // Reset
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Input data
input wire S_VALID, // Input data valid
output wire S_READY, // Input data ready
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Output data
output wire M_VALID, // Output data valid
input wire M_READY // Output data ready
);
localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;
localparam P_EMPTY = {P_FIFO_DEPTH_LOG{1'b1}};
localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1'b0}};
localparam P_ALMOSTFULL_TEMP = {P_EMPTY, 1'b0};
localparam P_ALMOSTFULL = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];
localparam P_NUM_REPS = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?
(C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :
((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;
(* syn_keep = "1" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr;
(* syn_keep = "1" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;
genvar i;
genvar j;
reg M_VALID_i;
reg S_READY_i;
wire push; // FIFO push
wire pop; // FIFO pop
reg areset_d1; // Reset delay register
wire [C_FIFO_WIDTH-1:0] m_axi_mesg_i; // Intermediate SRL data
assign M_VALID = M_VALID_i;
assign S_READY = C_USE_FULL ? S_READY_i : 1'b1;
assign M_MESG = m_axi_mesg_i;
assign push = S_VALID & (C_USE_FULL ? S_READY_i : 1'b1);
assign pop = M_VALID_i & M_READY;
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
generate
//---------------------------------------------------------------------------
// Create count of number of elements in FIFOs
//---------------------------------------------------------------------------
for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep
assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] =
push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;
always @(posedge ACLK) begin
if (ARESET)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
{P_FIFO_DEPTH_LOG{1'b1}};
else if (push ^ pop)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];
end
end
//---------------------------------------------------------------------------
// When FIFO is empty, reset master valid bit. When not empty set valid bit.
// When FIFO is full, reset slave ready bit. When not full set ready bit.
//---------------------------------------------------------------------------
always @(posedge ACLK) begin
if (ARESET) begin
M_VALID_i <= 1'b0;
end else if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTEMPTY) && pop && ~push) begin
M_VALID_i <= 1'b0;
end else if (push) begin
M_VALID_i <= 1'b1;
end
end
always @(posedge ACLK) begin
if (ARESET) begin
S_READY_i <= 1'b0;
end else if (areset_d1) begin
S_READY_i <= 1'b1;
end else if (C_USE_FULL &&
((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTFULL) && push && ~pop)) begin
S_READY_i <= 1'b0;
end else if (C_USE_FULL && pop) begin
S_READY_i <= 1'b1;
end
end
//---------------------------------------------------------------------------
// Instantiate SRLs
//---------------------------------------------------------------------------
for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls
for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep
axi_data_fifo_v2_1_ndeep_srl #
(
.C_FAMILY (C_FAMILY),
.C_A_WIDTH (P_FIFO_DEPTH_LOG)
)
srl_nx1
(
.CLK (ACLK),
.A (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:
P_FIFO_DEPTH_LOG*(i)]),
.CE (push),
.D (S_MESG[i*C_MAX_CTRL_FANOUT+j]),
.Q (m_axi_mesg_i[i*C_MAX_CTRL_FANOUT+j])
);
end
end
endgenerate
endmodule |
module axi_data_fifo_v2_1_axic_srl_fifo #
(
parameter C_FAMILY = "none", // FPGA Family
parameter integer C_FIFO_WIDTH = 1, // Width of S_MESG/M_MESG.
parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits
// the control logic can be used
// on before the control logic
// needs to be replicated.
parameter integer C_FIFO_DEPTH_LOG = 2, // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.
// The minimum size fifo generated is 4-deep.
parameter C_USE_FULL = 1 // Prevent overwrite by throttling S_READY.
)
(
input wire ACLK, // Clock
input wire ARESET, // Reset
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Input data
input wire S_VALID, // Input data valid
output wire S_READY, // Input data ready
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Output data
output wire M_VALID, // Output data valid
input wire M_READY // Output data ready
);
localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;
localparam P_EMPTY = {P_FIFO_DEPTH_LOG{1'b1}};
localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1'b0}};
localparam P_ALMOSTFULL_TEMP = {P_EMPTY, 1'b0};
localparam P_ALMOSTFULL = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];
localparam P_NUM_REPS = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?
(C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :
((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;
(* syn_keep = "1" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr;
(* syn_keep = "1" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;
genvar i;
genvar j;
reg M_VALID_i;
reg S_READY_i;
wire push; // FIFO push
wire pop; // FIFO pop
reg areset_d1; // Reset delay register
wire [C_FIFO_WIDTH-1:0] m_axi_mesg_i; // Intermediate SRL data
assign M_VALID = M_VALID_i;
assign S_READY = C_USE_FULL ? S_READY_i : 1'b1;
assign M_MESG = m_axi_mesg_i;
assign push = S_VALID & (C_USE_FULL ? S_READY_i : 1'b1);
assign pop = M_VALID_i & M_READY;
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
generate
//---------------------------------------------------------------------------
// Create count of number of elements in FIFOs
//---------------------------------------------------------------------------
for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep
assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] =
push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;
always @(posedge ACLK) begin
if (ARESET)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
{P_FIFO_DEPTH_LOG{1'b1}};
else if (push ^ pop)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];
end
end
//---------------------------------------------------------------------------
// When FIFO is empty, reset master valid bit. When not empty set valid bit.
// When FIFO is full, reset slave ready bit. When not full set ready bit.
//---------------------------------------------------------------------------
always @(posedge ACLK) begin
if (ARESET) begin
M_VALID_i <= 1'b0;
end else if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTEMPTY) && pop && ~push) begin
M_VALID_i <= 1'b0;
end else if (push) begin
M_VALID_i <= 1'b1;
end
end
always @(posedge ACLK) begin
if (ARESET) begin
S_READY_i <= 1'b0;
end else if (areset_d1) begin
S_READY_i <= 1'b1;
end else if (C_USE_FULL &&
((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTFULL) && push && ~pop)) begin
S_READY_i <= 1'b0;
end else if (C_USE_FULL && pop) begin
S_READY_i <= 1'b1;
end
end
//---------------------------------------------------------------------------
// Instantiate SRLs
//---------------------------------------------------------------------------
for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls
for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep
axi_data_fifo_v2_1_ndeep_srl #
(
.C_FAMILY (C_FAMILY),
.C_A_WIDTH (P_FIFO_DEPTH_LOG)
)
srl_nx1
(
.CLK (ACLK),
.A (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:
P_FIFO_DEPTH_LOG*(i)]),
.CE (push),
.D (S_MESG[i*C_MAX_CTRL_FANOUT+j]),
.Q (m_axi_mesg_i[i*C_MAX_CTRL_FANOUT+j])
);
end
end
endgenerate
endmodule |
module axi_data_fifo_v2_1_axic_srl_fifo #
(
parameter C_FAMILY = "none", // FPGA Family
parameter integer C_FIFO_WIDTH = 1, // Width of S_MESG/M_MESG.
parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits
// the control logic can be used
// on before the control logic
// needs to be replicated.
parameter integer C_FIFO_DEPTH_LOG = 2, // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.
// The minimum size fifo generated is 4-deep.
parameter C_USE_FULL = 1 // Prevent overwrite by throttling S_READY.
)
(
input wire ACLK, // Clock
input wire ARESET, // Reset
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Input data
input wire S_VALID, // Input data valid
output wire S_READY, // Input data ready
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Output data
output wire M_VALID, // Output data valid
input wire M_READY // Output data ready
);
localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;
localparam P_EMPTY = {P_FIFO_DEPTH_LOG{1'b1}};
localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1'b0}};
localparam P_ALMOSTFULL_TEMP = {P_EMPTY, 1'b0};
localparam P_ALMOSTFULL = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];
localparam P_NUM_REPS = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?
(C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :
((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;
(* syn_keep = "1" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr;
(* syn_keep = "1" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;
genvar i;
genvar j;
reg M_VALID_i;
reg S_READY_i;
wire push; // FIFO push
wire pop; // FIFO pop
reg areset_d1; // Reset delay register
wire [C_FIFO_WIDTH-1:0] m_axi_mesg_i; // Intermediate SRL data
assign M_VALID = M_VALID_i;
assign S_READY = C_USE_FULL ? S_READY_i : 1'b1;
assign M_MESG = m_axi_mesg_i;
assign push = S_VALID & (C_USE_FULL ? S_READY_i : 1'b1);
assign pop = M_VALID_i & M_READY;
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
generate
//---------------------------------------------------------------------------
// Create count of number of elements in FIFOs
//---------------------------------------------------------------------------
for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep
assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] =
push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;
always @(posedge ACLK) begin
if (ARESET)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
{P_FIFO_DEPTH_LOG{1'b1}};
else if (push ^ pop)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];
end
end
//---------------------------------------------------------------------------
// When FIFO is empty, reset master valid bit. When not empty set valid bit.
// When FIFO is full, reset slave ready bit. When not full set ready bit.
//---------------------------------------------------------------------------
always @(posedge ACLK) begin
if (ARESET) begin
M_VALID_i <= 1'b0;
end else if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTEMPTY) && pop && ~push) begin
M_VALID_i <= 1'b0;
end else if (push) begin
M_VALID_i <= 1'b1;
end
end
always @(posedge ACLK) begin
if (ARESET) begin
S_READY_i <= 1'b0;
end else if (areset_d1) begin
S_READY_i <= 1'b1;
end else if (C_USE_FULL &&
((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTFULL) && push && ~pop)) begin
S_READY_i <= 1'b0;
end else if (C_USE_FULL && pop) begin
S_READY_i <= 1'b1;
end
end
//---------------------------------------------------------------------------
// Instantiate SRLs
//---------------------------------------------------------------------------
for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls
for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep
axi_data_fifo_v2_1_ndeep_srl #
(
.C_FAMILY (C_FAMILY),
.C_A_WIDTH (P_FIFO_DEPTH_LOG)
)
srl_nx1
(
.CLK (ACLK),
.A (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:
P_FIFO_DEPTH_LOG*(i)]),
.CE (push),
.D (S_MESG[i*C_MAX_CTRL_FANOUT+j]),
.Q (m_axi_mesg_i[i*C_MAX_CTRL_FANOUT+j])
);
end
end
endgenerate
endmodule |
module axi_data_fifo_v2_1_axic_srl_fifo #
(
parameter C_FAMILY = "none", // FPGA Family
parameter integer C_FIFO_WIDTH = 1, // Width of S_MESG/M_MESG.
parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits
// the control logic can be used
// on before the control logic
// needs to be replicated.
parameter integer C_FIFO_DEPTH_LOG = 2, // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.
// The minimum size fifo generated is 4-deep.
parameter C_USE_FULL = 1 // Prevent overwrite by throttling S_READY.
)
(
input wire ACLK, // Clock
input wire ARESET, // Reset
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Input data
input wire S_VALID, // Input data valid
output wire S_READY, // Input data ready
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Output data
output wire M_VALID, // Output data valid
input wire M_READY // Output data ready
);
localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;
localparam P_EMPTY = {P_FIFO_DEPTH_LOG{1'b1}};
localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1'b0}};
localparam P_ALMOSTFULL_TEMP = {P_EMPTY, 1'b0};
localparam P_ALMOSTFULL = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];
localparam P_NUM_REPS = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?
(C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :
((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;
(* syn_keep = "1" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr;
(* syn_keep = "1" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;
genvar i;
genvar j;
reg M_VALID_i;
reg S_READY_i;
wire push; // FIFO push
wire pop; // FIFO pop
reg areset_d1; // Reset delay register
wire [C_FIFO_WIDTH-1:0] m_axi_mesg_i; // Intermediate SRL data
assign M_VALID = M_VALID_i;
assign S_READY = C_USE_FULL ? S_READY_i : 1'b1;
assign M_MESG = m_axi_mesg_i;
assign push = S_VALID & (C_USE_FULL ? S_READY_i : 1'b1);
assign pop = M_VALID_i & M_READY;
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
generate
//---------------------------------------------------------------------------
// Create count of number of elements in FIFOs
//---------------------------------------------------------------------------
for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep
assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] =
push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;
always @(posedge ACLK) begin
if (ARESET)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
{P_FIFO_DEPTH_LOG{1'b1}};
else if (push ^ pop)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];
end
end
//---------------------------------------------------------------------------
// When FIFO is empty, reset master valid bit. When not empty set valid bit.
// When FIFO is full, reset slave ready bit. When not full set ready bit.
//---------------------------------------------------------------------------
always @(posedge ACLK) begin
if (ARESET) begin
M_VALID_i <= 1'b0;
end else if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTEMPTY) && pop && ~push) begin
M_VALID_i <= 1'b0;
end else if (push) begin
M_VALID_i <= 1'b1;
end
end
always @(posedge ACLK) begin
if (ARESET) begin
S_READY_i <= 1'b0;
end else if (areset_d1) begin
S_READY_i <= 1'b1;
end else if (C_USE_FULL &&
((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTFULL) && push && ~pop)) begin
S_READY_i <= 1'b0;
end else if (C_USE_FULL && pop) begin
S_READY_i <= 1'b1;
end
end
//---------------------------------------------------------------------------
// Instantiate SRLs
//---------------------------------------------------------------------------
for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls
for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep
axi_data_fifo_v2_1_ndeep_srl #
(
.C_FAMILY (C_FAMILY),
.C_A_WIDTH (P_FIFO_DEPTH_LOG)
)
srl_nx1
(
.CLK (ACLK),
.A (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:
P_FIFO_DEPTH_LOG*(i)]),
.CE (push),
.D (S_MESG[i*C_MAX_CTRL_FANOUT+j]),
.Q (m_axi_mesg_i[i*C_MAX_CTRL_FANOUT+j])
);
end
end
endgenerate
endmodule |
module axi_data_fifo_v2_1_axic_srl_fifo #
(
parameter C_FAMILY = "none", // FPGA Family
parameter integer C_FIFO_WIDTH = 1, // Width of S_MESG/M_MESG.
parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits
// the control logic can be used
// on before the control logic
// needs to be replicated.
parameter integer C_FIFO_DEPTH_LOG = 2, // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.
// The minimum size fifo generated is 4-deep.
parameter C_USE_FULL = 1 // Prevent overwrite by throttling S_READY.
)
(
input wire ACLK, // Clock
input wire ARESET, // Reset
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Input data
input wire S_VALID, // Input data valid
output wire S_READY, // Input data ready
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Output data
output wire M_VALID, // Output data valid
input wire M_READY // Output data ready
);
localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;
localparam P_EMPTY = {P_FIFO_DEPTH_LOG{1'b1}};
localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1'b0}};
localparam P_ALMOSTFULL_TEMP = {P_EMPTY, 1'b0};
localparam P_ALMOSTFULL = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];
localparam P_NUM_REPS = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?
(C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :
((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;
(* syn_keep = "1" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr;
(* syn_keep = "1" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;
genvar i;
genvar j;
reg M_VALID_i;
reg S_READY_i;
wire push; // FIFO push
wire pop; // FIFO pop
reg areset_d1; // Reset delay register
wire [C_FIFO_WIDTH-1:0] m_axi_mesg_i; // Intermediate SRL data
assign M_VALID = M_VALID_i;
assign S_READY = C_USE_FULL ? S_READY_i : 1'b1;
assign M_MESG = m_axi_mesg_i;
assign push = S_VALID & (C_USE_FULL ? S_READY_i : 1'b1);
assign pop = M_VALID_i & M_READY;
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
generate
//---------------------------------------------------------------------------
// Create count of number of elements in FIFOs
//---------------------------------------------------------------------------
for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep
assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] =
push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;
always @(posedge ACLK) begin
if (ARESET)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
{P_FIFO_DEPTH_LOG{1'b1}};
else if (push ^ pop)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];
end
end
//---------------------------------------------------------------------------
// When FIFO is empty, reset master valid bit. When not empty set valid bit.
// When FIFO is full, reset slave ready bit. When not full set ready bit.
//---------------------------------------------------------------------------
always @(posedge ACLK) begin
if (ARESET) begin
M_VALID_i <= 1'b0;
end else if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTEMPTY) && pop && ~push) begin
M_VALID_i <= 1'b0;
end else if (push) begin
M_VALID_i <= 1'b1;
end
end
always @(posedge ACLK) begin
if (ARESET) begin
S_READY_i <= 1'b0;
end else if (areset_d1) begin
S_READY_i <= 1'b1;
end else if (C_USE_FULL &&
((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTFULL) && push && ~pop)) begin
S_READY_i <= 1'b0;
end else if (C_USE_FULL && pop) begin
S_READY_i <= 1'b1;
end
end
//---------------------------------------------------------------------------
// Instantiate SRLs
//---------------------------------------------------------------------------
for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls
for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep
axi_data_fifo_v2_1_ndeep_srl #
(
.C_FAMILY (C_FAMILY),
.C_A_WIDTH (P_FIFO_DEPTH_LOG)
)
srl_nx1
(
.CLK (ACLK),
.A (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:
P_FIFO_DEPTH_LOG*(i)]),
.CE (push),
.D (S_MESG[i*C_MAX_CTRL_FANOUT+j]),
.Q (m_axi_mesg_i[i*C_MAX_CTRL_FANOUT+j])
);
end
end
endgenerate
endmodule |
module axi_data_fifo_v2_1_axic_srl_fifo #
(
parameter C_FAMILY = "none", // FPGA Family
parameter integer C_FIFO_WIDTH = 1, // Width of S_MESG/M_MESG.
parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits
// the control logic can be used
// on before the control logic
// needs to be replicated.
parameter integer C_FIFO_DEPTH_LOG = 2, // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.
// The minimum size fifo generated is 4-deep.
parameter C_USE_FULL = 1 // Prevent overwrite by throttling S_READY.
)
(
input wire ACLK, // Clock
input wire ARESET, // Reset
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Input data
input wire S_VALID, // Input data valid
output wire S_READY, // Input data ready
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Output data
output wire M_VALID, // Output data valid
input wire M_READY // Output data ready
);
localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;
localparam P_EMPTY = {P_FIFO_DEPTH_LOG{1'b1}};
localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1'b0}};
localparam P_ALMOSTFULL_TEMP = {P_EMPTY, 1'b0};
localparam P_ALMOSTFULL = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];
localparam P_NUM_REPS = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?
(C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :
((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;
(* syn_keep = "1" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr;
(* syn_keep = "1" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;
genvar i;
genvar j;
reg M_VALID_i;
reg S_READY_i;
wire push; // FIFO push
wire pop; // FIFO pop
reg areset_d1; // Reset delay register
wire [C_FIFO_WIDTH-1:0] m_axi_mesg_i; // Intermediate SRL data
assign M_VALID = M_VALID_i;
assign S_READY = C_USE_FULL ? S_READY_i : 1'b1;
assign M_MESG = m_axi_mesg_i;
assign push = S_VALID & (C_USE_FULL ? S_READY_i : 1'b1);
assign pop = M_VALID_i & M_READY;
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
generate
//---------------------------------------------------------------------------
// Create count of number of elements in FIFOs
//---------------------------------------------------------------------------
for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep
assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] =
push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;
always @(posedge ACLK) begin
if (ARESET)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
{P_FIFO_DEPTH_LOG{1'b1}};
else if (push ^ pop)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];
end
end
//---------------------------------------------------------------------------
// When FIFO is empty, reset master valid bit. When not empty set valid bit.
// When FIFO is full, reset slave ready bit. When not full set ready bit.
//---------------------------------------------------------------------------
always @(posedge ACLK) begin
if (ARESET) begin
M_VALID_i <= 1'b0;
end else if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTEMPTY) && pop && ~push) begin
M_VALID_i <= 1'b0;
end else if (push) begin
M_VALID_i <= 1'b1;
end
end
always @(posedge ACLK) begin
if (ARESET) begin
S_READY_i <= 1'b0;
end else if (areset_d1) begin
S_READY_i <= 1'b1;
end else if (C_USE_FULL &&
((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTFULL) && push && ~pop)) begin
S_READY_i <= 1'b0;
end else if (C_USE_FULL && pop) begin
S_READY_i <= 1'b1;
end
end
//---------------------------------------------------------------------------
// Instantiate SRLs
//---------------------------------------------------------------------------
for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls
for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep
axi_data_fifo_v2_1_ndeep_srl #
(
.C_FAMILY (C_FAMILY),
.C_A_WIDTH (P_FIFO_DEPTH_LOG)
)
srl_nx1
(
.CLK (ACLK),
.A (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:
P_FIFO_DEPTH_LOG*(i)]),
.CE (push),
.D (S_MESG[i*C_MAX_CTRL_FANOUT+j]),
.Q (m_axi_mesg_i[i*C_MAX_CTRL_FANOUT+j])
);
end
end
endgenerate
endmodule |
module generic_baseblocks_v2_1_comparator_mask_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 3;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = C_VALUE;
assign m_local = M;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule |
module generic_baseblocks_v2_1_comparator_mask_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 3;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = C_VALUE;
assign m_local = M;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule |
module generic_baseblocks_v2_1_comparator #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 3;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule |
module generic_baseblocks_v2_1_comparator #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 3;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule |
module generic_baseblocks_v2_1_carry_latch_and #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign O = CIN & ~I;
end else begin : USE_FPGA
wire I_n;
assign I_n = ~I;
AND2B1L and2b1l_inst
(
.O(O),
.DI(CIN),
.SRI(I_n)
);
end
endgenerate
endmodule |
module generic_baseblocks_v2_1_carry_latch_and #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign O = CIN & ~I;
end else begin : USE_FPGA
wire I_n;
assign I_n = ~I;
AND2B1L and2b1l_inst
(
.O(O),
.DI(CIN),
.SRI(I_n)
);
end
endgenerate
endmodule |
module generic_baseblocks_v2_1_carry_latch_and #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign O = CIN & ~I;
end else begin : USE_FPGA
wire I_n;
assign I_n = ~I;
AND2B1L and2b1l_inst
(
.O(O),
.DI(CIN),
.SRI(I_n)
);
end
endgenerate
endmodule |
module generic_baseblocks_v2_1_carry_latch_and #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign O = CIN & ~I;
end else begin : USE_FPGA
wire I_n;
assign I_n = ~I;
AND2B1L and2b1l_inst
(
.O(O),
.DI(CIN),
.SRI(I_n)
);
end
endgenerate
endmodule |
module generic_baseblocks_v2_1_mux #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_SEL_WIDTH = 4,
// Data width for comparator.
parameter integer C_DATA_WIDTH = 2
// Data width for comparator.
)
(
input wire [C_SEL_WIDTH-1:0] S,
input wire [(2**C_SEL_WIDTH)*C_DATA_WIDTH-1:0] A,
output wire [C_DATA_WIDTH-1:0] O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" || C_SEL_WIDTH < 3 ) begin : USE_RTL
assign O = A[(S)*C_DATA_WIDTH +: C_DATA_WIDTH];
end else begin : USE_FPGA
wire [C_DATA_WIDTH-1:0] C;
wire [C_DATA_WIDTH-1:0] D;
// Lower half recursively.
generic_baseblocks_v2_1_mux #
(
.C_FAMILY (C_FAMILY),
.C_SEL_WIDTH (C_SEL_WIDTH-1),
.C_DATA_WIDTH (C_DATA_WIDTH)
) mux_c_inst
(
.S (S[C_SEL_WIDTH-2:0]),
.A (A[(2**(C_SEL_WIDTH-1))*C_DATA_WIDTH-1 : 0]),
.O (C)
);
// Upper half recursively.
generic_baseblocks_v2_1_mux #
(
.C_FAMILY (C_FAMILY),
.C_SEL_WIDTH (C_SEL_WIDTH-1),
.C_DATA_WIDTH (C_DATA_WIDTH)
) mux_d_inst
(
.S (S[C_SEL_WIDTH-2:0]),
.A (A[(2**C_SEL_WIDTH)*C_DATA_WIDTH-1 : (2**(C_SEL_WIDTH-1))*C_DATA_WIDTH]),
.O (D)
);
// Generate instantiated generic_baseblocks_v2_1_mux components as required.
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : NUM
if ( C_SEL_WIDTH == 4 ) begin : USE_F8
MUXF8 muxf8_inst
(
.I0 (C[bit_cnt]),
.I1 (D[bit_cnt]),
.S (S[C_SEL_WIDTH-1]),
.O (O[bit_cnt])
);
end else if ( C_SEL_WIDTH == 3 ) begin : USE_F7
MUXF7 muxf7_inst
(
.I0 (C[bit_cnt]),
.I1 (D[bit_cnt]),
.S (S[C_SEL_WIDTH-1]),
.O (O[bit_cnt])
);
end // C_SEL_WIDTH
end // end for bit_cnt
end
endgenerate
endmodule |
module generic_baseblocks_v2_1_mux #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_SEL_WIDTH = 4,
// Data width for comparator.
parameter integer C_DATA_WIDTH = 2
// Data width for comparator.
)
(
input wire [C_SEL_WIDTH-1:0] S,
input wire [(2**C_SEL_WIDTH)*C_DATA_WIDTH-1:0] A,
output wire [C_DATA_WIDTH-1:0] O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" || C_SEL_WIDTH < 3 ) begin : USE_RTL
assign O = A[(S)*C_DATA_WIDTH +: C_DATA_WIDTH];
end else begin : USE_FPGA
wire [C_DATA_WIDTH-1:0] C;
wire [C_DATA_WIDTH-1:0] D;
// Lower half recursively.
generic_baseblocks_v2_1_mux #
(
.C_FAMILY (C_FAMILY),
.C_SEL_WIDTH (C_SEL_WIDTH-1),
.C_DATA_WIDTH (C_DATA_WIDTH)
) mux_c_inst
(
.S (S[C_SEL_WIDTH-2:0]),
.A (A[(2**(C_SEL_WIDTH-1))*C_DATA_WIDTH-1 : 0]),
.O (C)
);
// Upper half recursively.
generic_baseblocks_v2_1_mux #
(
.C_FAMILY (C_FAMILY),
.C_SEL_WIDTH (C_SEL_WIDTH-1),
.C_DATA_WIDTH (C_DATA_WIDTH)
) mux_d_inst
(
.S (S[C_SEL_WIDTH-2:0]),
.A (A[(2**C_SEL_WIDTH)*C_DATA_WIDTH-1 : (2**(C_SEL_WIDTH-1))*C_DATA_WIDTH]),
.O (D)
);
// Generate instantiated generic_baseblocks_v2_1_mux components as required.
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : NUM
if ( C_SEL_WIDTH == 4 ) begin : USE_F8
MUXF8 muxf8_inst
(
.I0 (C[bit_cnt]),
.I1 (D[bit_cnt]),
.S (S[C_SEL_WIDTH-1]),
.O (O[bit_cnt])
);
end else if ( C_SEL_WIDTH == 3 ) begin : USE_F7
MUXF7 muxf7_inst
(
.I0 (C[bit_cnt]),
.I1 (D[bit_cnt]),
.S (S[C_SEL_WIDTH-1]),
.O (O[bit_cnt])
);
end // C_SEL_WIDTH
end // end for bit_cnt
end
endgenerate
endmodule |
module generic_baseblocks_v2_1_mux #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_SEL_WIDTH = 4,
// Data width for comparator.
parameter integer C_DATA_WIDTH = 2
// Data width for comparator.
)
(
input wire [C_SEL_WIDTH-1:0] S,
input wire [(2**C_SEL_WIDTH)*C_DATA_WIDTH-1:0] A,
output wire [C_DATA_WIDTH-1:0] O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" || C_SEL_WIDTH < 3 ) begin : USE_RTL
assign O = A[(S)*C_DATA_WIDTH +: C_DATA_WIDTH];
end else begin : USE_FPGA
wire [C_DATA_WIDTH-1:0] C;
wire [C_DATA_WIDTH-1:0] D;
// Lower half recursively.
generic_baseblocks_v2_1_mux #
(
.C_FAMILY (C_FAMILY),
.C_SEL_WIDTH (C_SEL_WIDTH-1),
.C_DATA_WIDTH (C_DATA_WIDTH)
) mux_c_inst
(
.S (S[C_SEL_WIDTH-2:0]),
.A (A[(2**(C_SEL_WIDTH-1))*C_DATA_WIDTH-1 : 0]),
.O (C)
);
// Upper half recursively.
generic_baseblocks_v2_1_mux #
(
.C_FAMILY (C_FAMILY),
.C_SEL_WIDTH (C_SEL_WIDTH-1),
.C_DATA_WIDTH (C_DATA_WIDTH)
) mux_d_inst
(
.S (S[C_SEL_WIDTH-2:0]),
.A (A[(2**C_SEL_WIDTH)*C_DATA_WIDTH-1 : (2**(C_SEL_WIDTH-1))*C_DATA_WIDTH]),
.O (D)
);
// Generate instantiated generic_baseblocks_v2_1_mux components as required.
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : NUM
if ( C_SEL_WIDTH == 4 ) begin : USE_F8
MUXF8 muxf8_inst
(
.I0 (C[bit_cnt]),
.I1 (D[bit_cnt]),
.S (S[C_SEL_WIDTH-1]),
.O (O[bit_cnt])
);
end else if ( C_SEL_WIDTH == 3 ) begin : USE_F7
MUXF7 muxf7_inst
(
.I0 (C[bit_cnt]),
.I1 (D[bit_cnt]),
.S (S[C_SEL_WIDTH-1]),
.O (O[bit_cnt])
);
end // C_SEL_WIDTH
end // end for bit_cnt
end
endgenerate
endmodule |
module generic_baseblocks_v2_1_mux #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_SEL_WIDTH = 4,
// Data width for comparator.
parameter integer C_DATA_WIDTH = 2
// Data width for comparator.
)
(
input wire [C_SEL_WIDTH-1:0] S,
input wire [(2**C_SEL_WIDTH)*C_DATA_WIDTH-1:0] A,
output wire [C_DATA_WIDTH-1:0] O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" || C_SEL_WIDTH < 3 ) begin : USE_RTL
assign O = A[(S)*C_DATA_WIDTH +: C_DATA_WIDTH];
end else begin : USE_FPGA
wire [C_DATA_WIDTH-1:0] C;
wire [C_DATA_WIDTH-1:0] D;
// Lower half recursively.
generic_baseblocks_v2_1_mux #
(
.C_FAMILY (C_FAMILY),
.C_SEL_WIDTH (C_SEL_WIDTH-1),
.C_DATA_WIDTH (C_DATA_WIDTH)
) mux_c_inst
(
.S (S[C_SEL_WIDTH-2:0]),
.A (A[(2**(C_SEL_WIDTH-1))*C_DATA_WIDTH-1 : 0]),
.O (C)
);
// Upper half recursively.
generic_baseblocks_v2_1_mux #
(
.C_FAMILY (C_FAMILY),
.C_SEL_WIDTH (C_SEL_WIDTH-1),
.C_DATA_WIDTH (C_DATA_WIDTH)
) mux_d_inst
(
.S (S[C_SEL_WIDTH-2:0]),
.A (A[(2**C_SEL_WIDTH)*C_DATA_WIDTH-1 : (2**(C_SEL_WIDTH-1))*C_DATA_WIDTH]),
.O (D)
);
// Generate instantiated generic_baseblocks_v2_1_mux components as required.
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : NUM
if ( C_SEL_WIDTH == 4 ) begin : USE_F8
MUXF8 muxf8_inst
(
.I0 (C[bit_cnt]),
.I1 (D[bit_cnt]),
.S (S[C_SEL_WIDTH-1]),
.O (O[bit_cnt])
);
end else if ( C_SEL_WIDTH == 3 ) begin : USE_F7
MUXF7 muxf7_inst
(
.I0 (C[bit_cnt]),
.I1 (D[bit_cnt]),
.S (S[C_SEL_WIDTH-1]),
.O (O[bit_cnt])
);
end // C_SEL_WIDTH
end // end for bit_cnt
end
endgenerate
endmodule |
module generic_baseblocks_v2_1_comparator_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 6;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule |
module generic_baseblocks_v2_1_comparator_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 6;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule |
module generic_baseblocks_v2_1_nto1_mux #
(
parameter integer C_RATIO = 1, // Range: >=1
parameter integer C_SEL_WIDTH = 1, // Range: >=1; recommended: ceil_log2(C_RATIO)
parameter integer C_DATAOUT_WIDTH = 1, // Range: >=1
parameter integer C_ONEHOT = 0 // Values: 0 = binary-encoded (use SEL); 1 = one-hot (use SEL_ONEHOT)
)
(
input wire [C_RATIO-1:0] SEL_ONEHOT, // One-hot generic_baseblocks_v2_1_mux select (only used if C_ONEHOT=1)
input wire [C_SEL_WIDTH-1:0] SEL, // Binary-encoded generic_baseblocks_v2_1_mux select (only used if C_ONEHOT=0)
input wire [C_RATIO*C_DATAOUT_WIDTH-1:0] IN, // Data input array (num_selections x data_width)
output wire [C_DATAOUT_WIDTH-1:0] OUT // Data output vector
);
wire [C_DATAOUT_WIDTH*C_RATIO-1:0] carry;
genvar i;
generate
if (C_ONEHOT == 0) begin : gen_encoded
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{(SEL==0)?1'b1:1'b0}} & IN[C_DATAOUT_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{(SEL==i)?1'b1:1'b0}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end else begin : gen_onehot
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{SEL_ONEHOT[0]}} & IN[C_DATAOUT_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_hot
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{SEL_ONEHOT[i]}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end
endgenerate
assign OUT = carry[C_DATAOUT_WIDTH*C_RATIO-1:
C_DATAOUT_WIDTH*(C_RATIO-1)];
endmodule |
module generic_baseblocks_v2_1_nto1_mux #
(
parameter integer C_RATIO = 1, // Range: >=1
parameter integer C_SEL_WIDTH = 1, // Range: >=1; recommended: ceil_log2(C_RATIO)
parameter integer C_DATAOUT_WIDTH = 1, // Range: >=1
parameter integer C_ONEHOT = 0 // Values: 0 = binary-encoded (use SEL); 1 = one-hot (use SEL_ONEHOT)
)
(
input wire [C_RATIO-1:0] SEL_ONEHOT, // One-hot generic_baseblocks_v2_1_mux select (only used if C_ONEHOT=1)
input wire [C_SEL_WIDTH-1:0] SEL, // Binary-encoded generic_baseblocks_v2_1_mux select (only used if C_ONEHOT=0)
input wire [C_RATIO*C_DATAOUT_WIDTH-1:0] IN, // Data input array (num_selections x data_width)
output wire [C_DATAOUT_WIDTH-1:0] OUT // Data output vector
);
wire [C_DATAOUT_WIDTH*C_RATIO-1:0] carry;
genvar i;
generate
if (C_ONEHOT == 0) begin : gen_encoded
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{(SEL==0)?1'b1:1'b0}} & IN[C_DATAOUT_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{(SEL==i)?1'b1:1'b0}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end else begin : gen_onehot
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{SEL_ONEHOT[0]}} & IN[C_DATAOUT_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_hot
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{SEL_ONEHOT[i]}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end
endgenerate
assign OUT = carry[C_DATAOUT_WIDTH*C_RATIO-1:
C_DATAOUT_WIDTH*(C_RATIO-1)];
endmodule |
module generic_baseblocks_v2_1_comparator_mask #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign m_local = M;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule |
module generic_baseblocks_v2_1_comparator_mask #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign m_local = M;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule |
module generic_baseblocks_v2_1_comparator_mask #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign m_local = M;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule |
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