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module usdrx1_spi (
spi_afe_csn,
spi_clk_csn,
spi_clk,
spi_mosi,
spi_miso,
spi_afe_sdio,
spi_clk_sdio);
// 4 wire
input [ 3:0] spi_afe_csn;
input spi_clk_csn;
input spi_clk;
input spi_mosi;
output spi_miso;
// 3 wire
inout spi_afe_sdio;
inout spi_clk_sdio;
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire [ 1:0] spi_csn_3_s;
wire spi_csn_s;
wire spi_enable_s;
wire spi_afe_miso_s;
wire spi_clk_miso_s;
// check on rising edge and change on falling edge
assign spi_csn_3_s[1] = & spi_afe_csn;
assign spi_csn_3_s[0] = spi_clk_csn;
assign spi_csn_s = & spi_csn_3_s;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= spi_count + 1'b1;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (((spi_count == 6'd16) && (spi_csn_3_s[1] == 1'b0)) ||
((spi_count == 6'd16) && (spi_csn_3_s[0] == 1'b0))) begin
spi_enable <= spi_rd_wr_n;
end
end
end
assign spi_miso = ((spi_afe_miso_s & ~spi_csn_3_s[1]) |
(spi_clk_miso_s & ~spi_csn_3_s[0]));
// io buffers
assign spi_afe_miso_s = spi_afe_sdio;
assign spi_afe_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;
assign spi_clk_miso_s = spi_clk_sdio;
assign spi_clk_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;
endmodule |
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_hdll__or4 dut (.A(A), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule |
module SysPLL(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire sdr_clk,
// interface 'outclk1'
output wire sys_clk,
// interface 'outclk2'
output wire vga_clk,
output wire pit_clk,
// interface 'locked'
output wire locked
);
wire [4:0] sub_wire0;
wire [0:0] sub_wire7 = 1'h0;
wire [0:0] sub_wire5;
wire [3:3] sub_wire4 = sub_wire0[3:3];
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
assign sdr_clk = sub_wire1;
assign sys_clk = sub_wire2;
assign vga_clk = sub_wire3;
assign pit_clk = sub_wire4;
assign sub_wire5 = refclk;
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
altpll altpll_component (
.inclk (sub_wire6),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (locked),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "-2727",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 2,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 1,
altpll_component.clk2_phase_shift = "0",
altpll_component.clk3_divide_by = 25000000,
altpll_component.clk3_duty_cycle = 50,
altpll_component.clk3_multiply_by = 596529,
altpll_component.clk3_phase_shift = "0",
altpll_component.compensate_clock = "CLK1",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "MAX 10",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll1",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule |
module spi_slave(
input clk,
input rst,
input ss,
input mosi,
output miso,
input sck,
output done,
input [7:0] din,
input din_update,
output [7:0] dout
);
reg mosi_d, mosi_q;
reg ss_d, ss_q;
reg sck_d, sck_q;
reg sck_old_d, sck_old_q;
reg [7:0] data_d, data_q;
reg done_d, done_q;
reg [2:0] bit_ct_d, bit_ct_q;
reg [7:0] dout_d, dout_q;
reg miso_d, miso_q;
assign miso = miso_q;
assign done = done_q;
assign dout = dout_q;
always @(*) begin
ss_d = ss;
mosi_d = mosi;
miso_d = miso_q;
sck_d = sck;
sck_old_d = sck_q;
data_d = data_q;
done_d = 1'b0;
bit_ct_d = bit_ct_q;
dout_d = dout_q;
if (ss_q) begin
bit_ct_d = 3'b0;
data_d = din;
miso_d = data_q[7];
end else begin
if (!sck_old_q && sck_q) begin // rising edge
miso_d = data_q[7];
data_d = {data_q[6:0], mosi_q};
bit_ct_d = bit_ct_q + 1'b1;
if (bit_ct_q == 3'b111) begin
dout_d = {data_q[6:0], mosi_q};
done_d = 1'b1;
data_d = din;
end
end else if (din_update) begin
data_d = din;
end
end
end
always @(posedge clk) begin
if (rst) begin
done_q <= 1'b0;
bit_ct_q <= 3'b0;
dout_q <= 8'b0;
miso_q <= 1'b1;
end else begin
done_q <= done_d;
bit_ct_q <= bit_ct_d;
dout_q <= dout_d;
miso_q <= miso_d;
end
sck_q <= sck_d;
mosi_q <= mosi_d;
ss_q <= ss_d;
data_q <= data_d;
sck_old_q <= sck_old_d;
end
endmodule |
module hw1_A (
input [15:0] data,
input [6:0] control,
input clk,
input rst_n,
output reg [15:0] R0,
output reg [15:0] R1,
output reg [15:0] R2,
output reg [15:0] R3
);
reg [15:0] tmpData;
reg [15:0] T0, T1, T2, T3;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
R0 <= 0;
R1 <= 0;
R2 <= 0;
R3 <= 0;
end else begin
R0 <= (control[0])?(tmpData):R0;
R1 <= (control[1])?(tmpData):R1;
R2 <= (control[2])?(tmpData):R2;
R3 <= (control[3])?(tmpData):R3;
end // end of if-else block
end // end of always
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
tmpData <= 0;
end // end of if (!rst_n)
case (control[6:4])
3'b000: tmpData <= R0;
3'b001: tmpData <= R1;
3'b010: tmpData <= R2;
3'b011: tmpData <= R3;
3'b111: tmpData <= data;
default: tmpData <= 0;
endcase // end of case (control)
end // end of always
endmodule |
module dly_16 #(
parameter WIDTH=1
)(
input clk,
input rst,
input [3:0] dly,
input [WIDTH-1:0] din,
output [WIDTH-1:0] dout
);
generate
genvar i;
for (i=0; i < WIDTH; i=i+1) begin: bit_block
dly01_16 dly01_16_i (
.clk(clk), // input
.rst(rst), // input
.dly(dly), // input[3:0]
.din(din[i]), // input
.dout(dout[i]) // output reg
);
end
endgenerate
endmodule |
module system_acl_iface_acl_kernel_interface_mm_interconnect_0 (
input wire kernel_clk_out_clk_clk, // kernel_clk_out_clk.clk
input wire address_span_extender_0_reset_reset_bridge_in_reset_reset, // address_span_extender_0_reset_reset_bridge_in_reset.reset
input wire kernel_cra_reset_reset_bridge_in_reset_reset, // kernel_cra_reset_reset_bridge_in_reset.reset
input wire [29:0] address_span_extender_0_expanded_master_address, // address_span_extender_0_expanded_master.address
output wire address_span_extender_0_expanded_master_waitrequest, // .waitrequest
input wire [0:0] address_span_extender_0_expanded_master_burstcount, // .burstcount
input wire [3:0] address_span_extender_0_expanded_master_byteenable, // .byteenable
input wire address_span_extender_0_expanded_master_read, // .read
output wire [31:0] address_span_extender_0_expanded_master_readdata, // .readdata
output wire address_span_extender_0_expanded_master_readdatavalid, // .readdatavalid
input wire address_span_extender_0_expanded_master_write, // .write
input wire [31:0] address_span_extender_0_expanded_master_writedata, // .writedata
output wire [29:0] kernel_cra_s0_address, // kernel_cra_s0.address
output wire kernel_cra_s0_write, // .write
output wire kernel_cra_s0_read, // .read
input wire [63:0] kernel_cra_s0_readdata, // .readdata
output wire [63:0] kernel_cra_s0_writedata, // .writedata
output wire [0:0] kernel_cra_s0_burstcount, // .burstcount
output wire [7:0] kernel_cra_s0_byteenable, // .byteenable
input wire kernel_cra_s0_readdatavalid, // .readdatavalid
input wire kernel_cra_s0_waitrequest, // .waitrequest
output wire kernel_cra_s0_debugaccess // .debugaccess
);
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_waitrequest; // address_span_extender_0_expanded_master_agent:av_waitrequest -> address_span_extender_0_expanded_master_translator:uav_waitrequest
wire [31:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdata; // address_span_extender_0_expanded_master_agent:av_readdata -> address_span_extender_0_expanded_master_translator:uav_readdata
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_debugaccess; // address_span_extender_0_expanded_master_translator:uav_debugaccess -> address_span_extender_0_expanded_master_agent:av_debugaccess
wire [29:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_address; // address_span_extender_0_expanded_master_translator:uav_address -> address_span_extender_0_expanded_master_agent:av_address
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_read; // address_span_extender_0_expanded_master_translator:uav_read -> address_span_extender_0_expanded_master_agent:av_read
wire [3:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_byteenable; // address_span_extender_0_expanded_master_translator:uav_byteenable -> address_span_extender_0_expanded_master_agent:av_byteenable
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdatavalid; // address_span_extender_0_expanded_master_agent:av_readdatavalid -> address_span_extender_0_expanded_master_translator:uav_readdatavalid
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_lock; // address_span_extender_0_expanded_master_translator:uav_lock -> address_span_extender_0_expanded_master_agent:av_lock
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_write; // address_span_extender_0_expanded_master_translator:uav_write -> address_span_extender_0_expanded_master_agent:av_write
wire [31:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_writedata; // address_span_extender_0_expanded_master_translator:uav_writedata -> address_span_extender_0_expanded_master_agent:av_writedata
wire [2:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_burstcount; // address_span_extender_0_expanded_master_translator:uav_burstcount -> address_span_extender_0_expanded_master_agent:av_burstcount
wire rsp_mux_src_valid; // rsp_mux:src_valid -> address_span_extender_0_expanded_master_agent:rp_valid
wire [100:0] rsp_mux_src_data; // rsp_mux:src_data -> address_span_extender_0_expanded_master_agent:rp_data
wire rsp_mux_src_ready; // address_span_extender_0_expanded_master_agent:rp_ready -> rsp_mux:src_ready
wire [0:0] rsp_mux_src_channel; // rsp_mux:src_channel -> address_span_extender_0_expanded_master_agent:rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> address_span_extender_0_expanded_master_agent:rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> address_span_extender_0_expanded_master_agent:rp_endofpacket
wire [63:0] kernel_cra_s0_agent_m0_readdata; // kernel_cra_s0_translator:uav_readdata -> kernel_cra_s0_agent:m0_readdata
wire kernel_cra_s0_agent_m0_waitrequest; // kernel_cra_s0_translator:uav_waitrequest -> kernel_cra_s0_agent:m0_waitrequest
wire kernel_cra_s0_agent_m0_debugaccess; // kernel_cra_s0_agent:m0_debugaccess -> kernel_cra_s0_translator:uav_debugaccess
wire [29:0] kernel_cra_s0_agent_m0_address; // kernel_cra_s0_agent:m0_address -> kernel_cra_s0_translator:uav_address
wire [7:0] kernel_cra_s0_agent_m0_byteenable; // kernel_cra_s0_agent:m0_byteenable -> kernel_cra_s0_translator:uav_byteenable
wire kernel_cra_s0_agent_m0_read; // kernel_cra_s0_agent:m0_read -> kernel_cra_s0_translator:uav_read
wire kernel_cra_s0_agent_m0_readdatavalid; // kernel_cra_s0_translator:uav_readdatavalid -> kernel_cra_s0_agent:m0_readdatavalid
wire kernel_cra_s0_agent_m0_lock; // kernel_cra_s0_agent:m0_lock -> kernel_cra_s0_translator:uav_lock
wire [63:0] kernel_cra_s0_agent_m0_writedata; // kernel_cra_s0_agent:m0_writedata -> kernel_cra_s0_translator:uav_writedata
wire kernel_cra_s0_agent_m0_write; // kernel_cra_s0_agent:m0_write -> kernel_cra_s0_translator:uav_write
wire [3:0] kernel_cra_s0_agent_m0_burstcount; // kernel_cra_s0_agent:m0_burstcount -> kernel_cra_s0_translator:uav_burstcount
wire kernel_cra_s0_agent_rf_source_valid; // kernel_cra_s0_agent:rf_source_valid -> kernel_cra_s0_agent_rsp_fifo:in_valid
wire [137:0] kernel_cra_s0_agent_rf_source_data; // kernel_cra_s0_agent:rf_source_data -> kernel_cra_s0_agent_rsp_fifo:in_data
wire kernel_cra_s0_agent_rf_source_ready; // kernel_cra_s0_agent_rsp_fifo:in_ready -> kernel_cra_s0_agent:rf_source_ready
wire kernel_cra_s0_agent_rf_source_startofpacket; // kernel_cra_s0_agent:rf_source_startofpacket -> kernel_cra_s0_agent_rsp_fifo:in_startofpacket
wire kernel_cra_s0_agent_rf_source_endofpacket; // kernel_cra_s0_agent:rf_source_endofpacket -> kernel_cra_s0_agent_rsp_fifo:in_endofpacket
wire kernel_cra_s0_agent_rsp_fifo_out_valid; // kernel_cra_s0_agent_rsp_fifo:out_valid -> kernel_cra_s0_agent:rf_sink_valid
wire [137:0] kernel_cra_s0_agent_rsp_fifo_out_data; // kernel_cra_s0_agent_rsp_fifo:out_data -> kernel_cra_s0_agent:rf_sink_data
wire kernel_cra_s0_agent_rsp_fifo_out_ready; // kernel_cra_s0_agent:rf_sink_ready -> kernel_cra_s0_agent_rsp_fifo:out_ready
wire kernel_cra_s0_agent_rsp_fifo_out_startofpacket; // kernel_cra_s0_agent_rsp_fifo:out_startofpacket -> kernel_cra_s0_agent:rf_sink_startofpacket
wire kernel_cra_s0_agent_rsp_fifo_out_endofpacket; // kernel_cra_s0_agent_rsp_fifo:out_endofpacket -> kernel_cra_s0_agent:rf_sink_endofpacket
wire address_span_extender_0_expanded_master_agent_cp_valid; // address_span_extender_0_expanded_master_agent:cp_valid -> router:sink_valid
wire [100:0] address_span_extender_0_expanded_master_agent_cp_data; // address_span_extender_0_expanded_master_agent:cp_data -> router:sink_data
wire address_span_extender_0_expanded_master_agent_cp_ready; // router:sink_ready -> address_span_extender_0_expanded_master_agent:cp_ready
wire address_span_extender_0_expanded_master_agent_cp_startofpacket; // address_span_extender_0_expanded_master_agent:cp_startofpacket -> router:sink_startofpacket
wire address_span_extender_0_expanded_master_agent_cp_endofpacket; // address_span_extender_0_expanded_master_agent:cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [100:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [0:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire kernel_cra_s0_agent_rp_valid; // kernel_cra_s0_agent:rp_valid -> router_001:sink_valid
wire [136:0] kernel_cra_s0_agent_rp_data; // kernel_cra_s0_agent:rp_data -> router_001:sink_data
wire kernel_cra_s0_agent_rp_ready; // router_001:sink_ready -> kernel_cra_s0_agent:rp_ready
wire kernel_cra_s0_agent_rp_startofpacket; // kernel_cra_s0_agent:rp_startofpacket -> router_001:sink_startofpacket
wire kernel_cra_s0_agent_rp_endofpacket; // kernel_cra_s0_agent:rp_endofpacket -> router_001:sink_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [100:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [0:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [100:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [0:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> kernel_cra_s0_cmd_width_adapter:in_valid
wire [100:0] cmd_mux_src_data; // cmd_mux:src_data -> kernel_cra_s0_cmd_width_adapter:in_data
wire cmd_mux_src_ready; // kernel_cra_s0_cmd_width_adapter:in_ready -> cmd_mux:src_ready
wire [0:0] cmd_mux_src_channel; // cmd_mux:src_channel -> kernel_cra_s0_cmd_width_adapter:in_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> kernel_cra_s0_cmd_width_adapter:in_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> kernel_cra_s0_cmd_width_adapter:in_endofpacket
wire kernel_cra_s0_cmd_width_adapter_src_valid; // kernel_cra_s0_cmd_width_adapter:out_valid -> kernel_cra_s0_agent:cp_valid
wire [136:0] kernel_cra_s0_cmd_width_adapter_src_data; // kernel_cra_s0_cmd_width_adapter:out_data -> kernel_cra_s0_agent:cp_data
wire kernel_cra_s0_cmd_width_adapter_src_ready; // kernel_cra_s0_agent:cp_ready -> kernel_cra_s0_cmd_width_adapter:out_ready
wire [0:0] kernel_cra_s0_cmd_width_adapter_src_channel; // kernel_cra_s0_cmd_width_adapter:out_channel -> kernel_cra_s0_agent:cp_channel
wire kernel_cra_s0_cmd_width_adapter_src_startofpacket; // kernel_cra_s0_cmd_width_adapter:out_startofpacket -> kernel_cra_s0_agent:cp_startofpacket
wire kernel_cra_s0_cmd_width_adapter_src_endofpacket; // kernel_cra_s0_cmd_width_adapter:out_endofpacket -> kernel_cra_s0_agent:cp_endofpacket
wire router_001_src_valid; // router_001:src_valid -> kernel_cra_s0_rsp_width_adapter:in_valid
wire [136:0] router_001_src_data; // router_001:src_data -> kernel_cra_s0_rsp_width_adapter:in_data
wire router_001_src_ready; // kernel_cra_s0_rsp_width_adapter:in_ready -> router_001:src_ready
wire [0:0] router_001_src_channel; // router_001:src_channel -> kernel_cra_s0_rsp_width_adapter:in_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> kernel_cra_s0_rsp_width_adapter:in_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> kernel_cra_s0_rsp_width_adapter:in_endofpacket
wire kernel_cra_s0_rsp_width_adapter_src_valid; // kernel_cra_s0_rsp_width_adapter:out_valid -> rsp_demux:sink_valid
wire [100:0] kernel_cra_s0_rsp_width_adapter_src_data; // kernel_cra_s0_rsp_width_adapter:out_data -> rsp_demux:sink_data
wire kernel_cra_s0_rsp_width_adapter_src_ready; // rsp_demux:sink_ready -> kernel_cra_s0_rsp_width_adapter:out_ready
wire [0:0] kernel_cra_s0_rsp_width_adapter_src_channel; // kernel_cra_s0_rsp_width_adapter:out_channel -> rsp_demux:sink_channel
wire kernel_cra_s0_rsp_width_adapter_src_startofpacket; // kernel_cra_s0_rsp_width_adapter:out_startofpacket -> rsp_demux:sink_startofpacket
wire kernel_cra_s0_rsp_width_adapter_src_endofpacket; // kernel_cra_s0_rsp_width_adapter:out_endofpacket -> rsp_demux:sink_endofpacket
wire kernel_cra_s0_agent_rdata_fifo_src_valid; // kernel_cra_s0_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
wire [65:0] kernel_cra_s0_agent_rdata_fifo_src_data; // kernel_cra_s0_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
wire kernel_cra_s0_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> kernel_cra_s0_agent:rdata_fifo_src_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> kernel_cra_s0_agent:rdata_fifo_sink_valid
wire [65:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> kernel_cra_s0_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // kernel_cra_s0_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> kernel_cra_s0_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) address_span_extender_0_expanded_master_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_read), // .read
.uav_write (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (address_span_extender_0_expanded_master_address), // avalon_anti_master_0.address
.av_waitrequest (address_span_extender_0_expanded_master_waitrequest), // .waitrequest
.av_burstcount (address_span_extender_0_expanded_master_burstcount), // .burstcount
.av_byteenable (address_span_extender_0_expanded_master_byteenable), // .byteenable
.av_read (address_span_extender_0_expanded_master_read), // .read
.av_readdata (address_span_extender_0_expanded_master_readdata), // .readdata
.av_readdatavalid (address_span_extender_0_expanded_master_readdatavalid), // .readdatavalid
.av_write (address_span_extender_0_expanded_master_write), // .write
.av_writedata (address_span_extender_0_expanded_master_writedata), // .writedata
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) kernel_cra_s0_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (kernel_cra_s0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (kernel_cra_s0_agent_m0_burstcount), // .burstcount
.uav_read (kernel_cra_s0_agent_m0_read), // .read
.uav_write (kernel_cra_s0_agent_m0_write), // .write
.uav_waitrequest (kernel_cra_s0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (kernel_cra_s0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (kernel_cra_s0_agent_m0_byteenable), // .byteenable
.uav_readdata (kernel_cra_s0_agent_m0_readdata), // .readdata
.uav_writedata (kernel_cra_s0_agent_m0_writedata), // .writedata
.uav_lock (kernel_cra_s0_agent_m0_lock), // .lock
.uav_debugaccess (kernel_cra_s0_agent_m0_debugaccess), // .debugaccess
.av_address (kernel_cra_s0_address), // avalon_anti_slave_0.address
.av_write (kernel_cra_s0_write), // .write
.av_read (kernel_cra_s0_read), // .read
.av_readdata (kernel_cra_s0_readdata), // .readdata
.av_writedata (kernel_cra_s0_writedata), // .writedata
.av_burstcount (kernel_cra_s0_burstcount), // .burstcount
.av_byteenable (kernel_cra_s0_byteenable), // .byteenable
.av_readdatavalid (kernel_cra_s0_readdatavalid), // .readdatavalid
.av_waitrequest (kernel_cra_s0_waitrequest), // .waitrequest
.av_debugaccess (kernel_cra_s0_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (100),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_QOS_H (85),
.PKT_QOS_L (85),
.PKT_DATA_SIDEBAND_H (83),
.PKT_DATA_SIDEBAND_L (83),
.PKT_ADDR_SIDEBAND_H (82),
.PKT_ADDR_SIDEBAND_L (82),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_CACHE_H (95),
.PKT_CACHE_L (92),
.PKT_THREAD_ID_H (88),
.PKT_THREAD_ID_L (88),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_TRANS_EXCLUSIVE (71),
.PKT_TRANS_LOCK (70),
.PKT_BEGIN_BURST (84),
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (72),
.PKT_ADDR_H (65),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (66),
.PKT_TRANS_POSTED (67),
.PKT_TRANS_WRITE (68),
.PKT_TRANS_READ (69),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (86),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (87),
.ST_DATA_W (101),
.ST_CHANNEL_W (1),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) address_span_extender_0_expanded_master_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_address), // av.address
.av_write (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_write), // .write
.av_read (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (address_span_extender_0_expanded_master_agent_cp_valid), // cp.valid
.cp_data (address_span_extender_0_expanded_master_agent_cp_data), // .data
.cp_startofpacket (address_span_extender_0_expanded_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (address_span_extender_0_expanded_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (address_span_extender_0_expanded_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (136),
.PKT_ORI_BURST_SIZE_L (134),
.PKT_RESPONSE_STATUS_H (133),
.PKT_RESPONSE_STATUS_L (132),
.PKT_BURST_SIZE_H (115),
.PKT_BURST_SIZE_L (113),
.PKT_TRANS_LOCK (106),
.PKT_BEGIN_BURST (120),
.PKT_PROTECTION_H (127),
.PKT_PROTECTION_L (125),
.PKT_BURSTWRAP_H (112),
.PKT_BURSTWRAP_L (112),
.PKT_BYTE_CNT_H (111),
.PKT_BYTE_CNT_L (108),
.PKT_ADDR_H (101),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (102),
.PKT_TRANS_POSTED (103),
.PKT_TRANS_WRITE (104),
.PKT_TRANS_READ (105),
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_SRC_ID_H (122),
.PKT_SRC_ID_L (122),
.PKT_DEST_ID_H (123),
.PKT_DEST_ID_L (123),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (1),
.ST_DATA_W (137),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) kernel_cra_s0_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (kernel_cra_s0_agent_m0_address), // m0.address
.m0_burstcount (kernel_cra_s0_agent_m0_burstcount), // .burstcount
.m0_byteenable (kernel_cra_s0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (kernel_cra_s0_agent_m0_debugaccess), // .debugaccess
.m0_lock (kernel_cra_s0_agent_m0_lock), // .lock
.m0_readdata (kernel_cra_s0_agent_m0_readdata), // .readdata
.m0_readdatavalid (kernel_cra_s0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (kernel_cra_s0_agent_m0_read), // .read
.m0_waitrequest (kernel_cra_s0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (kernel_cra_s0_agent_m0_writedata), // .writedata
.m0_write (kernel_cra_s0_agent_m0_write), // .write
.rp_endofpacket (kernel_cra_s0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (kernel_cra_s0_agent_rp_ready), // .ready
.rp_valid (kernel_cra_s0_agent_rp_valid), // .valid
.rp_data (kernel_cra_s0_agent_rp_data), // .data
.rp_startofpacket (kernel_cra_s0_agent_rp_startofpacket), // .startofpacket
.cp_ready (kernel_cra_s0_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (kernel_cra_s0_cmd_width_adapter_src_valid), // .valid
.cp_data (kernel_cra_s0_cmd_width_adapter_src_data), // .data
.cp_startofpacket (kernel_cra_s0_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (kernel_cra_s0_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (kernel_cra_s0_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (kernel_cra_s0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (kernel_cra_s0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (kernel_cra_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (kernel_cra_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (kernel_cra_s0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (kernel_cra_s0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (kernel_cra_s0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (kernel_cra_s0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (kernel_cra_s0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (kernel_cra_s0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (kernel_cra_s0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (kernel_cra_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (kernel_cra_s0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (138),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) kernel_cra_s0_agent_rsp_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (kernel_cra_s0_agent_rf_source_data), // in.data
.in_valid (kernel_cra_s0_agent_rf_source_valid), // .valid
.in_ready (kernel_cra_s0_agent_rf_source_ready), // .ready
.in_startofpacket (kernel_cra_s0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (kernel_cra_s0_agent_rf_source_endofpacket), // .endofpacket
.out_data (kernel_cra_s0_agent_rsp_fifo_out_data), // out.data
.out_valid (kernel_cra_s0_agent_rsp_fifo_out_valid), // .valid
.out_ready (kernel_cra_s0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (kernel_cra_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (kernel_cra_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_router router (
.sink_ready (address_span_extender_0_expanded_master_agent_cp_ready), // sink.ready
.sink_valid (address_span_extender_0_expanded_master_agent_cp_valid), // .valid
.sink_data (address_span_extender_0_expanded_master_agent_cp_data), // .data
.sink_startofpacket (address_span_extender_0_expanded_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_0_expanded_master_agent_cp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_router_001 router_001 (
.sink_ready (kernel_cra_s0_agent_rp_ready), // sink.ready
.sink_valid (kernel_cra_s0_agent_rp_valid), // .valid
.sink_data (kernel_cra_s0_agent_rp_data), // .data
.sink_startofpacket (kernel_cra_s0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cra_s0_agent_rp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_demux cmd_demux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_mux cmd_mux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_demux rsp_demux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (kernel_cra_s0_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (kernel_cra_s0_rsp_width_adapter_src_channel), // .channel
.sink_data (kernel_cra_s0_rsp_width_adapter_src_data), // .data
.sink_startofpacket (kernel_cra_s0_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cra_s0_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (kernel_cra_s0_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_rsp_mux rsp_mux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (65),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (75),
.IN_PKT_BYTE_CNT_L (72),
.IN_PKT_TRANS_COMPRESSED_READ (66),
.IN_PKT_TRANS_WRITE (68),
.IN_PKT_BURSTWRAP_H (76),
.IN_PKT_BURSTWRAP_L (76),
.IN_PKT_BURST_SIZE_H (79),
.IN_PKT_BURST_SIZE_L (77),
.IN_PKT_RESPONSE_STATUS_H (97),
.IN_PKT_RESPONSE_STATUS_L (96),
.IN_PKT_TRANS_EXCLUSIVE (71),
.IN_PKT_BURST_TYPE_H (81),
.IN_PKT_BURST_TYPE_L (80),
.IN_PKT_ORI_BURST_SIZE_L (98),
.IN_PKT_ORI_BURST_SIZE_H (100),
.IN_ST_DATA_W (101),
.OUT_PKT_ADDR_H (101),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (111),
.OUT_PKT_BYTE_CNT_L (108),
.OUT_PKT_TRANS_COMPRESSED_READ (102),
.OUT_PKT_BURST_SIZE_H (115),
.OUT_PKT_BURST_SIZE_L (113),
.OUT_PKT_RESPONSE_STATUS_H (133),
.OUT_PKT_RESPONSE_STATUS_L (132),
.OUT_PKT_TRANS_EXCLUSIVE (107),
.OUT_PKT_BURST_TYPE_H (117),
.OUT_PKT_BURST_TYPE_L (116),
.OUT_PKT_ORI_BURST_SIZE_L (134),
.OUT_PKT_ORI_BURST_SIZE_H (136),
.OUT_ST_DATA_W (137),
.ST_CHANNEL_W (1),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) kernel_cra_s0_cmd_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_src_valid), // sink.valid
.in_channel (cmd_mux_src_channel), // .channel
.in_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_src_ready), // .ready
.in_data (cmd_mux_src_data), // .data
.out_endofpacket (kernel_cra_s0_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (kernel_cra_s0_cmd_width_adapter_src_data), // .data
.out_channel (kernel_cra_s0_cmd_width_adapter_src_channel), // .channel
.out_valid (kernel_cra_s0_cmd_width_adapter_src_valid), // .valid
.out_ready (kernel_cra_s0_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (kernel_cra_s0_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (101),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (111),
.IN_PKT_BYTE_CNT_L (108),
.IN_PKT_TRANS_COMPRESSED_READ (102),
.IN_PKT_TRANS_WRITE (104),
.IN_PKT_BURSTWRAP_H (112),
.IN_PKT_BURSTWRAP_L (112),
.IN_PKT_BURST_SIZE_H (115),
.IN_PKT_BURST_SIZE_L (113),
.IN_PKT_RESPONSE_STATUS_H (133),
.IN_PKT_RESPONSE_STATUS_L (132),
.IN_PKT_TRANS_EXCLUSIVE (107),
.IN_PKT_BURST_TYPE_H (117),
.IN_PKT_BURST_TYPE_L (116),
.IN_PKT_ORI_BURST_SIZE_L (134),
.IN_PKT_ORI_BURST_SIZE_H (136),
.IN_ST_DATA_W (137),
.OUT_PKT_ADDR_H (65),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (75),
.OUT_PKT_BYTE_CNT_L (72),
.OUT_PKT_TRANS_COMPRESSED_READ (66),
.OUT_PKT_BURST_SIZE_H (79),
.OUT_PKT_BURST_SIZE_L (77),
.OUT_PKT_RESPONSE_STATUS_H (97),
.OUT_PKT_RESPONSE_STATUS_L (96),
.OUT_PKT_TRANS_EXCLUSIVE (71),
.OUT_PKT_BURST_TYPE_H (81),
.OUT_PKT_BURST_TYPE_L (80),
.OUT_PKT_ORI_BURST_SIZE_L (98),
.OUT_PKT_ORI_BURST_SIZE_H (100),
.OUT_ST_DATA_W (101),
.ST_CHANNEL_W (1),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) kernel_cra_s0_rsp_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_001_src_valid), // sink.valid
.in_channel (router_001_src_channel), // .channel
.in_startofpacket (router_001_src_startofpacket), // .startofpacket
.in_endofpacket (router_001_src_endofpacket), // .endofpacket
.in_ready (router_001_src_ready), // .ready
.in_data (router_001_src_data), // .data
.out_endofpacket (kernel_cra_s0_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (kernel_cra_s0_rsp_width_adapter_src_data), // .data
.out_channel (kernel_cra_s0_rsp_width_adapter_src_channel), // .channel
.out_valid (kernel_cra_s0_rsp_width_adapter_src_valid), // .valid
.out_ready (kernel_cra_s0_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (kernel_cra_s0_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (66),
.inUsePackets (0),
.inDataWidth (66),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (66),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (kernel_clk_out_clk_clk), // in_clk_0.clk
.in_rst_0_reset (kernel_cra_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (kernel_cra_s0_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (kernel_cra_s0_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (kernel_cra_s0_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
endmodule |
module SDRAM_clock (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module ramcon(
input reset_i,
input clk2x_i,
output [22:0] ram_adr_o,
inout [15:0] ram_dq_io,
output ram_ce_on,
output ram_adv_on,
output ram_oe_on,
output ram_we_on,
output ram_ub_on,
output ram_lb_on,
output ram_cre_o,
output ram_clk_o,
input ram_wait_i,
output wb_ack_o,
output [15:0] wb_dat_o,
input [15:0] wb_dat_i,
input [23:1] wb_adr_i,
input [1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
input wb_we_i,
output reset_o
);
wire ram_en_q;
wire ram_adv_o, ram_ce_o, ram_oe_o, ram_we_o, ram_be_valid;
wire dato_dq, dq_dati;
wire nt0, nt1, nt2, nt3, nt4, nt5;
reg t0, t1, t2, t3, t4, t5;
reg cfg;
wire cfg_o, adr_bcrcfg, clk_en;
// PSRAM power-on timing. Do not let the dogs out until
// the PSRAM chip has gone through its boot-up sequence.
// Wait 150us minimum, and to be conservative, a little
// extra. I've arbitrarily selected 32ms, assuming 50MHz
// input on clk2x_i.
reg [14:0] resetCounter;
always @(posedge clk2x_i) begin
if(reset_i) begin
resetCounter <= 0;
end
else begin
if(resetCounter[14]) begin
resetCounter <= resetCounter;
end
else begin
resetCounter <= resetCounter + 1;
end
end
end
wire reset_sans_cfg = ~resetCounter[14];
assign reset_o = reset_sans_cfg | cfg;
// Bus bridge random logic.
reg [15:0] wb_dat_or;
assign ram_adr_o = adr_bcrcfg ? `BCR_ADDR : wb_adr_i;
assign wb_dat_o = wb_dat_or;
always @(negedge clk2x_i) begin
if(dato_dq) wb_dat_or <= ram_dq_io;
end
assign ram_dq_io = dq_dati ? wb_dat_i : 16'hzzzz;
assign ram_clk_o = ~clk2x_i & clk_en;
// Bus bridge state Machine.
kseq ks(
.t5(t5),
.t4(t4),
.t3(t3),
.t2(t2),
.t1(t1),
.wb_we_i(wb_we_i),
.t0(t0),
.wb_cyc_i(wb_cyc_i),
.wb_stb_i(wb_stb_i),
.reset_i(reset_sans_cfg),
.wb_ack_o(wb_ack_o),
.dato_dq(dato_dq),
.dq_dati(dq_dati),
.ram_oe_o(ram_oe_o),
.ram_we_o(ram_we_o),
.ram_ce_o(ram_ce_o),
.ram_adv_o(ram_adv_o),
.ram_be_valid(ram_be_valid),
.nt5(nt5),
.nt4(nt4),
.nt3(nt3),
.nt2(nt2),
.nt1(nt1),
.nt0(nt0),
.adr_bcrcfg(adr_bcrcfg),
.ram_cre_o(ram_cre_o),
.cfg_o(cfg_o),
.cfg(cfg),
.clk_en(clk_en),
.ram_wait_i(ram_wait_i)
);
assign ram_adv_on = reset_sans_cfg | ~ram_adv_o;
assign ram_ce_on = reset_sans_cfg | ~ram_ce_o;
assign ram_oe_on = reset_sans_cfg | ~ram_oe_o;
assign ram_we_on = reset_sans_cfg | ~ram_we_o;
assign ram_ub_on = reset_sans_cfg | ~(ram_be_valid & wb_sel_i[1]);
assign ram_lb_on = reset_sans_cfg | ~(ram_be_valid & wb_sel_i[0]);
always @(posedge clk2x_i) begin
t0 <= nt0;
t1 <= nt1;
t2 <= nt2;
t3 <= nt3;
t4 <= nt4;
t5 <= nt5;
cfg <= cfg_o;
end
endmodule |
module sky130_fd_sc_hd__nand3_1 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hd__nand3_1 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule |
module sky130_fd_sc_ls__xnor2 (
//# {{data|Data Signals}}
input A ,
input B ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module top();
// Inputs are registered
reg A0;
reg A1;
reg A2;
reg A3;
reg S0;
reg S1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
S0 = 1'bX;
S1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 A2 = 1'b0;
#80 A3 = 1'b0;
#100 S0 = 1'b0;
#120 S1 = 1'b0;
#140 VGND = 1'b0;
#160 VNB = 1'b0;
#180 VPB = 1'b0;
#200 VPWR = 1'b0;
#220 A0 = 1'b1;
#240 A1 = 1'b1;
#260 A2 = 1'b1;
#280 A3 = 1'b1;
#300 S0 = 1'b1;
#320 S1 = 1'b1;
#340 VGND = 1'b1;
#360 VNB = 1'b1;
#380 VPB = 1'b1;
#400 VPWR = 1'b1;
#420 A0 = 1'b0;
#440 A1 = 1'b0;
#460 A2 = 1'b0;
#480 A3 = 1'b0;
#500 S0 = 1'b0;
#520 S1 = 1'b0;
#540 VGND = 1'b0;
#560 VNB = 1'b0;
#580 VPB = 1'b0;
#600 VPWR = 1'b0;
#620 VPWR = 1'b1;
#640 VPB = 1'b1;
#660 VNB = 1'b1;
#680 VGND = 1'b1;
#700 S1 = 1'b1;
#720 S0 = 1'b1;
#740 A3 = 1'b1;
#760 A2 = 1'b1;
#780 A1 = 1'b1;
#800 A0 = 1'b1;
#820 VPWR = 1'bx;
#840 VPB = 1'bx;
#860 VNB = 1'bx;
#880 VGND = 1'bx;
#900 S1 = 1'bx;
#920 S0 = 1'bx;
#940 A3 = 1'bx;
#960 A2 = 1'bx;
#980 A1 = 1'bx;
#1000 A0 = 1'bx;
end
sky130_fd_sc_ls__mux4 dut (.A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S0), .S1(S1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule |
module spi_slave(
clk,sck,mosi,miso,ssel,rst_n,recived_status
);
input clk;
input rst_n;
input sck,mosi,ssel;
output miso;
output recived_status;
reg recived_status;
reg[2:0] sckr;
reg[2:0] sselr;
reg[1:0] mosir;
reg[2:0] bitcnt;
reg[7:0] bytecnt;
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;
reg[7:0] received_memory;
reg [7:0] byte_data_sent;
reg [7:0] cnt;
wire ssel_active;
wire sck_risingedge;
wire sck_fallingedge;
wire ssel_startmessage;
wire ssel_endmessage;
wire mosi_data;
/*******************************************************************************
*detect the rising edge and falling edge of sck
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
sckr <= 3'h0;
else
sckr <= {sckr[1:0],sck};
end
assign sck_risingedge = (sckr[2:1] == 2'b01) ? 1'b1 : 1'b0;
assign sck_fallingedge = (sckr[2:1] == 2'b10) ? 1'b1 : 1'b0;
/*******************************************************************************
*detect starts at falling edge and stops at rising edge of ssel
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
sselr <= 3'h0;
else
sselr <= {sselr[1:0],ssel};
end
assign ssel_active = (~sselr[1]) ? 1'b1 : 1'b0; // SSEL is active low
assign ssel_startmessage = (sselr[2:1]==2'b10) ? 1'b1 : 1'b0; // message starts at falling edge
assign ssel_endmessage = (sselr[2:1]==2'b01) ? 1'b1 : 1'b0; // message stops at rising edge
/*******************************************************************************
*read from mosi
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
mosir <= 2'h0;
else
mosir <={mosir[0],mosi};
end
assign mosi_data = mosir[1];
/*******************************************************************************
*SPI slave reveive in 8-bits format
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
bitcnt <= 3'b000;
byte_data_received <= 8'h0;
end
else begin
if(~ssel_active)
bitcnt <= 3'b000;
else begin
if(sck_risingedge)begin
bitcnt <= bitcnt + 3'b001;
byte_data_received <= {byte_data_received[6:0], mosi_data};
end
else begin
bitcnt <= bitcnt;
byte_data_received <= byte_data_received;
end
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
byte_received <= 1'b0;
else
byte_received <= ssel_active && sck_risingedge && (bitcnt==3'b111);
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)begin
bytecnt <= 8'h0;
received_memory <= 8'h0;
end
else begin
if(byte_received) begin
bytecnt <= bytecnt + 1'b1;
received_memory <= (byte_data_received == bytecnt) ? (received_memory + 1'b1) : received_memory;
end
else begin
bytecnt <= bytecnt;
received_memory <= received_memory;
end
end
end
/*******************************************************************************
*SPI slave send date
*******************************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cnt<= 8'h0;
else begin
if(byte_received)
cnt<=cnt+8'h1; // count the messages
else
cnt<=cnt;
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
byte_data_sent <= 8'h0;
else begin
if(ssel_active && sck_fallingedge) begin
if(bitcnt==3'b001)
byte_data_sent <= cnt; // after that, we send 0s
else
byte_data_sent <= {byte_data_sent[6:0], 1'b0};
end
else
byte_data_sent <= byte_data_sent;
end
end
assign miso = byte_data_sent[7]; // send MSB first
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
recived_status <= 1'b0;
else
recived_status <= (received_memory == 8'd64) ? 1'b1 : 1'b0;
end
endmodule |
module ecc_merge_enc
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter CODE_WIDTH = 72,
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DATA_WIDTH = 64,
parameter DQ_WIDTH = 72,
parameter ECC_WIDTH = 8,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
mc_wrdata, mc_wrdata_mask,
// Inputs
clk, rst, wr_data, wr_data_mask, rd_merge_data, h_rows, raw_not_ecc
);
input clk;
input rst;
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data;
input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask;
input [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data_r;
reg [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask_r;
reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data_r;
always @(posedge clk) wr_data_r <= #TCQ wr_data;
always @(posedge clk) wr_data_mask_r <= #TCQ wr_data_mask;
always @(posedge clk) rd_merge_data_r <= #TCQ rd_merge_data;
// Merge new data with memory read data.
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] merged_data;
genvar h;
genvar i;
generate
for (h=0; h<2*nCK_PER_CLK; h=h+1) begin : merge_data_outer
for (i=0; i<DATA_WIDTH/8; i=i+1) begin : merge_data_inner
assign merged_data[h*PAYLOAD_WIDTH+i*8+:8] =
wr_data_mask_r[h*DATA_WIDTH/8+i]
? rd_merge_data_r[h*DATA_WIDTH+i*8+:8]
: wr_data_r[h*PAYLOAD_WIDTH+i*8+:8];
end
if (PAYLOAD_WIDTH > DATA_WIDTH)
assign merged_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH]=
wr_data_r[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH];
end
endgenerate
// Generate ECC and overlay onto mc_wrdata.
input [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
input [2*nCK_PER_CLK-1:0] raw_not_ecc;
reg [2*nCK_PER_CLK-1:0] raw_not_ecc_r;
always @(posedge clk) raw_not_ecc_r <= #TCQ raw_not_ecc;
output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata;
genvar j;
integer k;
generate
for (j=0; j<2*nCK_PER_CLK; j=j+1) begin : ecc_word
always @(/*AS*/h_rows or merged_data or raw_not_ecc_r) begin
mc_wrdata[j*DQ_WIDTH+:DQ_WIDTH] =
{{DQ_WIDTH-PAYLOAD_WIDTH{1'b0}},
merged_data[j*PAYLOAD_WIDTH+:PAYLOAD_WIDTH]};
for (k=0; k<ECC_WIDTH; k=k+1)
if (~raw_not_ecc_r[j])
mc_wrdata[j*DQ_WIDTH+CODE_WIDTH-k-1] =
^(merged_data[j*PAYLOAD_WIDTH+:DATA_WIDTH] &
h_rows[k*CODE_WIDTH+:DATA_WIDTH]);
end
end
endgenerate
// Set all DRAM masks to zero.
output wire[2*nCK_PER_CLK*DQ_WIDTH/8-1:0] mc_wrdata_mask;
assign mc_wrdata_mask = {2*nCK_PER_CLK*DQ_WIDTH/8{1'b0}};
endmodule |
module ALU16(A, B, sel, out);
input [15:0] A, B;
input [2:0] sel;
output [15:0] out;
assign less = 1'b0;;
//Still need to account for less
wire [15:0] c;
wire set;
alu_slice a1(A[0], B[0], sel[2], set, sel, c[0], out[0]);
alu_slice a2(A[1], B[1], c[0], less, sel, c[1], out[1]);
alu_slice a3(A[2], B[2], c[1], less, sel, c[2], out[2]);
alu_slice a4(A[3], B[3], c[2], less, sel, c[3], out[3]);
alu_slice a5(A[4], B[4], c[3], less, sel, c[4], out[4]);
alu_slice a6(A[5], B[5], c[4], less, sel, c[5], out[5]);
alu_slice a7(A[6], B[6], c[5], less, sel, c[6], out[6]);
alu_slice a8(A[7], B[7], c[6], less, sel, c[7], out[7]);
alu_slice a9(A[8], B[8], c[7], less, sel, c[8], out[8]);
alu_slice a10(A[9], B[9], c[8], less, sel, c[9], out[9]);
alu_slice a11(A[10], B[10], c[9], less, sel, c[10], out[10]);
alu_slice a12(A[11], B[11], c[10], less, sel, c[11], out[11]);
alu_slice a13(A[12], B[12], c[11], less, sel, c[12], out[12]);
alu_slice a14(A[13], B[13], c[12], less, sel, c[13], out[13]);
alu_slice a15(A[14], B[14], c[13], less, sel, c[14], out[14]);
alu_slice_msb a16(A[15], B[15], c[14], less, sel, c[15], out[15],set);
endmodule |
module image_to_ppfifo #(
parameter BUFFER_SIZE = 10
)(
input clk,
input rst,
input i_enable,
input i_hsync, // vga hsync signal
input i_vsync, // vga vsync signal
input [2:0] i_red, // vga red signal
input [2:0] i_green, // vga green signal
input [1:0] i_blue, // vga blue signal
output reg o_frame_finished,
//Memory FIFO Interface
output o_rfifo_ready,
input i_rfifo_activate,
input i_rfifo_strobe,
output [31:0] o_rfifo_data,
output [23:0] o_rfifo_size
);
//Local Parameters
localparam IDLE = 4'h0;
localparam PROCESS_IMAGE = 4'h1;
//Registers/Wires
reg r_prev_vsync;
wire w_neg_edge_vsync;
//ppfifo interface
wire [1:0] w_write_ready;
reg [1:0] r_write_activate;
wire [23:0] w_write_fifo_size;
reg r_write_strobe;
reg [23:0] r_write_count;
reg [31:0] r_write_data;
//Submodules
ppfifo p2m
#(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (BUFFER_SIZE )
)fifo (
//universal input
.reset (rst ),
//write side
.write_clock (clk ),
.write_ready (w_write_ready ),
.write_activate (r_write_activate ),
.write_fifo_size (w_write_fifo_size ),
.write_strobe (r_write_strobe ),
.write_data (r_write_data ),
// .inactive (w_inactive ),
//read side
.read_clock (clk ),
.read_strobe (i_rfifo_strobe ),
.read_ready (o_rfifo_ready ),
.read_activate (i_rfifo_activate ),
.read_count (o_rfifo_size ),
.read_data (o_rfifo_data )
);
//Asynchronous Logic
assign w_neg_edge_vsync = (r_prev_vsync & !i_vsync);
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
r_write_activate <= 0;
r_write_strobe <= 0;
r_write_count <= 0;
r_write_data <= 0;
o_frame_finished <= 0;
r_prev_vsync <= 0;
end
else begin
o_frame_finished <= 0;
r_write_strobe <= 0;
if (i_enable && (r_write_activate == 0) && (w_write_ready > 0)) begin
r_write_count <= 0;
if (w_write_ready[0]) begin
r_write_activate[0] <= 1;
end
else begin
r_write_activate[1] <= 1;
end
end
if (i_enable && (r_write_activate > 0)) begin
if (i_hsync) begin
r_write_data <= {24'h000000, i_red, i_green, i_blue};
r_write_strobe <= 1;
r_write_count <= r_write_count + 1;
if (r_write_count >= w_write_fifo_size - 1) begin
r_write_activate <= 0;
end
end
else if (!i_hsync) begin
r_write_activate <= 0;
end
if (w_neg_edge_vsync) begin
o_frame_finished <= 1;
end
end
r_prev_vsync <= i_vsync;
end
end
endmodule |
module sky130_fd_sc_ms__a221o_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ms__a221o_1 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule |
module cordic(
clk,
xI, // Input X value
yI, // Input Y Value
angle, // Rotation angle in radians
xO,
yO
);
// Bitness of all relevant buses
parameter WIDTH = 16;
parameter ANGLE_WIDTH = 32;
parameter ATAN_INITIAL_FILE = "../mems/atan16_32.hex";
// Inputs
/* verilator lint_off UNUSED */
input clk;
input signed[WIDTH-1:0] xI, yI;
input signed[ANGLE_WIDTH-1:0] angle;
/* verilator lint_on UNUSED */
// Outputs
output signed[WIDTH-1:0] xO, yO;
// Pipeline
reg signed[WIDTH-1:0] x_pl[WIDTH:0]; // X pipeline stages
reg signed[WIDTH-1:0] y_pl[WIDTH:0]; // Y pipeline stages
reg signed[ANGLE_WIDTH-1:0] a_pl[WIDTH:0]; // Angle pipeline stages
// atan_lut[i] is the result of atan(x) w/ x = 2^-i in radians
reg[ANGLE_WIDTH-1:0] atan_lut[WIDTH-1:0];
initial begin
$readmemh(ATAN_INITIAL_FILE, atan_lut);
end
// Result depends on angle > 0 for +/-
// xO = xI -/+ (yI >> i)
// yO = yI +/- (xI >> i)
wire[1:0] quadrant;
assign quadrant = angle[31:30];
integer i;
always @(posedge clk) begin
// Preprocess angle before entering pipeline.
case (quadrant)
2'b00, // Tangent is fine in this quadrants, no reflection
2'b11: begin
x_pl[0] <= xI;
y_pl[0] <= yI;
a_pl[0] <= angle;
end
2'b01: begin
x_pl[0] <= -yI;
y_pl[0] <= xI;
a_pl[0] <= {2'b00, angle[29:0]};
end
2'b10: begin
x_pl[0] <= yI;
y_pl[0] <= -xI;
a_pl[0] <= {2'b11, angle[29:0]};
end
endcase
// Generate pipeline stages. Might need to break this up if it synths to something awful.
// Will probably need an alway @(*) block if so to hold the combinational parts.
for(i = 0; i < WIDTH; i = i + 1) begin
x_pl[i+1] <= (a_pl[i] > 0) ? x_pl[i] - (y_pl[i] >>> i) : x_pl[i] + (y_pl[i] >>> i);
y_pl[i+1] <= (a_pl[i] > 0) ? y_pl[i] + (x_pl[i] >>> i) : y_pl[i] - (x_pl[i] >>> i);
a_pl[i+1] <= (a_pl[i] > 0) ? a_pl[i] - atan_lut[i] : a_pl[i] + atan_lut[i];
end
end
// Set the output. That sure looks like it means x[0] doesn't it? But it's xO...utput.
assign xO = x_pl[WIDTH-1];
assign yO = y_pl[WIDTH-1];
endmodule |
module gcd_zynq_snick_gcd_0_0(s_axi_gcd_bus_AWADDR,
s_axi_gcd_bus_AWVALID, s_axi_gcd_bus_AWREADY, s_axi_gcd_bus_WDATA, s_axi_gcd_bus_WSTRB,
s_axi_gcd_bus_WVALID, s_axi_gcd_bus_WREADY, s_axi_gcd_bus_BRESP, s_axi_gcd_bus_BVALID,
s_axi_gcd_bus_BREADY, s_axi_gcd_bus_ARADDR, s_axi_gcd_bus_ARVALID,
s_axi_gcd_bus_ARREADY, s_axi_gcd_bus_RDATA, s_axi_gcd_bus_RRESP, s_axi_gcd_bus_RVALID,
s_axi_gcd_bus_RREADY, ap_clk, ap_rst_n, interrupt)
/* synthesis syn_black_box black_box_pad_pin="s_axi_gcd_bus_AWADDR[5:0],s_axi_gcd_bus_AWVALID,s_axi_gcd_bus_AWREADY,s_axi_gcd_bus_WDATA[31:0],s_axi_gcd_bus_WSTRB[3:0],s_axi_gcd_bus_WVALID,s_axi_gcd_bus_WREADY,s_axi_gcd_bus_BRESP[1:0],s_axi_gcd_bus_BVALID,s_axi_gcd_bus_BREADY,s_axi_gcd_bus_ARADDR[5:0],s_axi_gcd_bus_ARVALID,s_axi_gcd_bus_ARREADY,s_axi_gcd_bus_RDATA[31:0],s_axi_gcd_bus_RRESP[1:0],s_axi_gcd_bus_RVALID,s_axi_gcd_bus_RREADY,ap_clk,ap_rst_n,interrupt" */;
input [5:0]s_axi_gcd_bus_AWADDR;
input s_axi_gcd_bus_AWVALID;
output s_axi_gcd_bus_AWREADY;
input [31:0]s_axi_gcd_bus_WDATA;
input [3:0]s_axi_gcd_bus_WSTRB;
input s_axi_gcd_bus_WVALID;
output s_axi_gcd_bus_WREADY;
output [1:0]s_axi_gcd_bus_BRESP;
output s_axi_gcd_bus_BVALID;
input s_axi_gcd_bus_BREADY;
input [5:0]s_axi_gcd_bus_ARADDR;
input s_axi_gcd_bus_ARVALID;
output s_axi_gcd_bus_ARREADY;
output [31:0]s_axi_gcd_bus_RDATA;
output [1:0]s_axi_gcd_bus_RRESP;
output s_axi_gcd_bus_RVALID;
input s_axi_gcd_bus_RREADY;
input ap_clk;
input ap_rst_n;
output interrupt;
endmodule |
module soc_system_pll_pwm(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("25.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(1),
.output_clock_frequency0("125.500000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule |
module sky130_fd_sc_hd__probe_p (
X ,
A ,
VGND,
VNB ,
VPB ,
VPWR
);
// Module ports
output X ;
input A ;
input VGND;
input VNB ;
input VPB ;
input VPWR;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule |
module sky130_fd_sc_hdll__tapvgnd2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module int16_float32_altbarrel_shift_gof
(
aclr,
clk_en,
clock,
data,
distance,
result) ;
input aclr;
input clk_en;
input clock;
input [15:0] data;
input [3:0] distance;
output [15:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [1:0] dir_pipe;
reg [15:0] sbit_piper1d;
reg [15:0] sbit_piper2d;
reg sel_pipec2r1d;
reg sel_pipec3r1d;
wire [4:0] dir_w;
wire direction_w;
wire [7:0] pad_w;
wire [79:0] sbit_w;
wire [3:0] sel_w;
wire [63:0] smux_w;
// synopsys translate_off
initial
dir_pipe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dir_pipe <= 2'b0;
else if (clk_en == 1'b1) dir_pipe <= {dir_w[3], dir_w[1]};
// synopsys translate_off
initial
sbit_piper1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper1d <= 16'b0;
else if (clk_en == 1'b1) sbit_piper1d <= smux_w[31:16];
// synopsys translate_off
initial
sbit_piper2d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper2d <= 16'b0;
else if (clk_en == 1'b1) sbit_piper2d <= smux_w[63:48];
// synopsys translate_off
initial
sel_pipec2r1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipec2r1d <= 1'b0;
else if (clk_en == 1'b1) sel_pipec2r1d <= distance[2];
// synopsys translate_off
initial
sel_pipec3r1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipec3r1d <= 1'b0;
else if (clk_en == 1'b1) sel_pipec3r1d <= distance[3];
assign
dir_w = {dir_pipe[1], dir_w[2], dir_pipe[0], dir_w[0], direction_w},
direction_w = 1'b0,
pad_w = {8{1'b0}},
result = sbit_w[79:64],
sbit_w = {sbit_piper2d, smux_w[47:32], sbit_piper1d, smux_w[15:0], data},
sel_w = {sel_pipec3r1d, sel_pipec2r1d, distance[1:0]},
smux_w = {((({16{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[55:48], pad_w[7:0]}) | ({16{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[63:56]})) | ({16{(~ sel_w[3])}} & sbit_w[63:48])), ((({16{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[43:32], pad_w[3:0]}) | ({16{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[47:36]})) | ({16{(~ sel_w[2])}} & sbit_w[47:32])), ((({16{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[29:16], pad_w[1:0]}) | ({16{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[31:18]})) | ({16{(~ sel_w[1])}} & sbit_w[31:16])), ((({16{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[14:0], pad_w[0]}) | ({16{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[15:1]})) | ({16{(~ sel_w[0])}} & sbit_w[15:0]))};
endmodule |
module int16_float32_altpriority_encoder_3v7
(
data,
q) ;
input [1:0] data;
output [0:0] q;
assign
q = {data[1]};
endmodule |
module int16_float32_altpriority_encoder_3e8
(
data,
q,
zero) ;
input [1:0] data;
output [0:0] q;
output zero;
assign
q = {data[1]},
zero = (~ (data[0] | data[1]));
endmodule |
module int16_float32_altpriority_encoder_6v7
(
data,
q) ;
input [3:0] data;
output [1:0] q;
wire [0:0] wire_altpriority_encoder10_q;
wire [0:0] wire_altpriority_encoder11_q;
wire wire_altpriority_encoder11_zero;
int16_float32_altpriority_encoder_3v7 altpriority_encoder10
(
.data(data[1:0]),
.q(wire_altpriority_encoder10_q));
int16_float32_altpriority_encoder_3e8 altpriority_encoder11
(
.data(data[3:2]),
.q(wire_altpriority_encoder11_q),
.zero(wire_altpriority_encoder11_zero));
assign
q = {(~ wire_altpriority_encoder11_zero), ((wire_altpriority_encoder11_zero & wire_altpriority_encoder10_q) | ((~ wire_altpriority_encoder11_zero) & wire_altpriority_encoder11_q))};
endmodule |
module int16_float32_altpriority_encoder_6e8
(
data,
q,
zero) ;
input [3:0] data;
output [1:0] q;
output zero;
wire [0:0] wire_altpriority_encoder12_q;
wire wire_altpriority_encoder12_zero;
wire [0:0] wire_altpriority_encoder13_q;
wire wire_altpriority_encoder13_zero;
int16_float32_altpriority_encoder_3e8 altpriority_encoder12
(
.data(data[1:0]),
.q(wire_altpriority_encoder12_q),
.zero(wire_altpriority_encoder12_zero));
int16_float32_altpriority_encoder_3e8 altpriority_encoder13
(
.data(data[3:2]),
.q(wire_altpriority_encoder13_q),
.zero(wire_altpriority_encoder13_zero));
assign
q = {(~ wire_altpriority_encoder13_zero), ((wire_altpriority_encoder13_zero & wire_altpriority_encoder12_q) | ((~ wire_altpriority_encoder13_zero) & wire_altpriority_encoder13_q))},
zero = (wire_altpriority_encoder12_zero & wire_altpriority_encoder13_zero);
endmodule |
module int16_float32_altpriority_encoder_bv7
(
data,
q) ;
input [7:0] data;
output [2:0] q;
wire [1:0] wire_altpriority_encoder8_q;
wire [1:0] wire_altpriority_encoder9_q;
wire wire_altpriority_encoder9_zero;
int16_float32_altpriority_encoder_6v7 altpriority_encoder8
(
.data(data[3:0]),
.q(wire_altpriority_encoder8_q));
int16_float32_altpriority_encoder_6e8 altpriority_encoder9
(
.data(data[7:4]),
.q(wire_altpriority_encoder9_q),
.zero(wire_altpriority_encoder9_zero));
assign
q = {(~ wire_altpriority_encoder9_zero), (({2{wire_altpriority_encoder9_zero}} & wire_altpriority_encoder8_q) | ({2{(~ wire_altpriority_encoder9_zero)}} & wire_altpriority_encoder9_q))};
endmodule |
module int16_float32_altpriority_encoder_be8
(
data,
q,
zero) ;
input [7:0] data;
output [2:0] q;
output zero;
wire [1:0] wire_altpriority_encoder14_q;
wire wire_altpriority_encoder14_zero;
wire [1:0] wire_altpriority_encoder15_q;
wire wire_altpriority_encoder15_zero;
int16_float32_altpriority_encoder_6e8 altpriority_encoder14
(
.data(data[3:0]),
.q(wire_altpriority_encoder14_q),
.zero(wire_altpriority_encoder14_zero));
int16_float32_altpriority_encoder_6e8 altpriority_encoder15
(
.data(data[7:4]),
.q(wire_altpriority_encoder15_q),
.zero(wire_altpriority_encoder15_zero));
assign
q = {(~ wire_altpriority_encoder15_zero), (({2{wire_altpriority_encoder15_zero}} & wire_altpriority_encoder14_q) | ({2{(~ wire_altpriority_encoder15_zero)}} & wire_altpriority_encoder15_q))},
zero = (wire_altpriority_encoder14_zero & wire_altpriority_encoder15_zero);
endmodule |
module int16_float32_altpriority_encoder_rb6
(
data,
q) ;
input [15:0] data;
output [3:0] q;
wire [2:0] wire_altpriority_encoder6_q;
wire [2:0] wire_altpriority_encoder7_q;
wire wire_altpriority_encoder7_zero;
int16_float32_altpriority_encoder_bv7 altpriority_encoder6
(
.data(data[7:0]),
.q(wire_altpriority_encoder6_q));
int16_float32_altpriority_encoder_be8 altpriority_encoder7
(
.data(data[15:8]),
.q(wire_altpriority_encoder7_q),
.zero(wire_altpriority_encoder7_zero));
assign
q = {(~ wire_altpriority_encoder7_zero), (({3{wire_altpriority_encoder7_zero}} & wire_altpriority_encoder6_q) | ({3{(~ wire_altpriority_encoder7_zero)}} & wire_altpriority_encoder7_q))};
endmodule |
module int16_float32_altfp_convert_bqm
(
clock,
dataa,
result) ;
input clock;
input [15:0] dataa;
output [31:0] result;
wire [15:0] wire_altbarrel_shift5_result;
wire [3:0] wire_altpriority_encoder2_q;
reg [7:0] exponent_bus_pre_reg;
reg [7:0] exponent_bus_pre_reg2;
reg [7:0] exponent_bus_pre_reg3;
reg [14:0] mag_int_a_reg;
reg [14:0] mag_int_a_reg2;
reg [23:0] mantissa_pre_round_reg;
reg [3:0] priority_encoder_reg;
reg [31:0] result_reg;
reg sign_int_a_reg1;
reg sign_int_a_reg2;
reg sign_int_a_reg3;
reg sign_int_a_reg4;
reg sign_int_a_reg5;
wire [14:0] wire_add_sub1_result;
wire [7:0] wire_add_sub3_result;
wire wire_cmpr4_alb;
wire aclr;
wire [7:0] bias_value_w;
wire clk_en;
wire [7:0] const_bias_value_add_width_int_w;
wire [7:0] exceptions_value;
wire [7:0] exponent_bus;
wire [7:0] exponent_bus_pre;
wire [7:0] exponent_output_w;
wire [7:0] exponent_rounded;
wire [7:0] exponent_zero_w;
wire [14:0] int_a;
wire [14:0] int_a_2s;
wire [14:0] invert_int_a;
wire [3:0] leading_zeroes;
wire [14:0] mag_int_a;
wire [22:0] mantissa_bus;
wire [23:0] mantissa_pre_round;
wire [23:0] mantissa_rounded;
wire max_neg_value_selector;
wire [7:0] max_neg_value_w;
wire [7:0] minus_leading_zero;
wire [15:0] prio_mag_int_a;
wire [31:0] result_w;
wire [14:0] shifted_mag_int_a;
wire sign_bus;
wire sign_int_a;
wire [3:0] zero_padding_w;
int16_float32_altbarrel_shift_gof altbarrel_shift5
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data({1'b0, mag_int_a_reg2}),
.distance(leading_zeroes),
.result(wire_altbarrel_shift5_result));
int16_float32_altpriority_encoder_rb6 altpriority_encoder2
(
.data(prio_mag_int_a),
.q(wire_altpriority_encoder2_q));
// synopsys translate_off
initial
exponent_bus_pre_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponent_bus_pre_reg <= 8'b0;
else if (clk_en == 1'b1) exponent_bus_pre_reg <= exponent_bus_pre_reg2;
// synopsys translate_off
initial
exponent_bus_pre_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponent_bus_pre_reg2 <= 8'b0;
else if (clk_en == 1'b1) exponent_bus_pre_reg2 <= exponent_bus_pre_reg3;
// synopsys translate_off
initial
exponent_bus_pre_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponent_bus_pre_reg3 <= 8'b0;
else if (clk_en == 1'b1) exponent_bus_pre_reg3 <= exponent_bus_pre;
// synopsys translate_off
initial
mag_int_a_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mag_int_a_reg <= 15'b0;
else if (clk_en == 1'b1) mag_int_a_reg <= mag_int_a;
// synopsys translate_off
initial
mag_int_a_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mag_int_a_reg2 <= 15'b0;
else if (clk_en == 1'b1) mag_int_a_reg2 <= mag_int_a_reg;
// synopsys translate_off
initial
mantissa_pre_round_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mantissa_pre_round_reg <= 24'b0;
else if (clk_en == 1'b1) mantissa_pre_round_reg <= mantissa_pre_round;
// synopsys translate_off
initial
priority_encoder_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) priority_encoder_reg <= 4'b0;
else if (clk_en == 1'b1) priority_encoder_reg <= wire_altpriority_encoder2_q;
// synopsys translate_off
initial
result_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) result_reg <= 32'b0;
else if (clk_en == 1'b1) result_reg <= result_w;
// synopsys translate_off
initial
sign_int_a_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg1 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg1 <= sign_int_a;
// synopsys translate_off
initial
sign_int_a_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg2 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg2 <= sign_int_a_reg1;
// synopsys translate_off
initial
sign_int_a_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg3 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg3 <= sign_int_a_reg2;
// synopsys translate_off
initial
sign_int_a_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg4 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg4 <= sign_int_a_reg3;
// synopsys translate_off
initial
sign_int_a_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg5 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg5 <= sign_int_a_reg4;
lpm_add_sub add_sub1
(
.cout(),
.dataa(invert_int_a),
.datab(15'b000000000000001),
.overflow(),
.result(wire_add_sub1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub1.lpm_direction = "ADD",
add_sub1.lpm_width = 15,
add_sub1.lpm_type = "lpm_add_sub",
add_sub1.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_add_sub add_sub3
(
.cout(),
.dataa(const_bias_value_add_width_int_w),
.datab(minus_leading_zero),
.overflow(),
.result(wire_add_sub3_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub3.lpm_direction = "SUB",
add_sub3.lpm_width = 8,
add_sub3.lpm_type = "lpm_add_sub",
add_sub3.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_compare cmpr4
(
.aeb(),
.agb(),
.ageb(),
.alb(wire_cmpr4_alb),
.aleb(),
.aneb(),
.dataa(exponent_output_w),
.datab(bias_value_w)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cmpr4.lpm_representation = "UNSIGNED",
cmpr4.lpm_width = 8,
cmpr4.lpm_type = "lpm_compare";
assign
aclr = 1'b0,
bias_value_w = 8'b01111111,
clk_en = 1'b1,
const_bias_value_add_width_int_w = 8'b10001101,
exceptions_value = (({8{(~ max_neg_value_selector)}} & exponent_zero_w) | ({8{max_neg_value_selector}} & max_neg_value_w)),
exponent_bus = exponent_rounded,
exponent_bus_pre = (({8{(~ wire_cmpr4_alb)}} & exponent_output_w) | ({8{wire_cmpr4_alb}} & exceptions_value)),
exponent_output_w = wire_add_sub3_result,
exponent_rounded = exponent_bus_pre_reg,
exponent_zero_w = {8{1'b0}},
int_a = dataa[14:0],
int_a_2s = wire_add_sub1_result,
invert_int_a = (~ int_a),
leading_zeroes = (~ priority_encoder_reg),
mag_int_a = (({15{(~ sign_int_a)}} & int_a) | ({15{sign_int_a}} & int_a_2s)),
mantissa_bus = mantissa_rounded[22:0],
mantissa_pre_round = {shifted_mag_int_a[14:0], {9{1'b0}}},
mantissa_rounded = mantissa_pre_round_reg,
max_neg_value_selector = (wire_cmpr4_alb & sign_int_a_reg2),
max_neg_value_w = 8'b10001110,
minus_leading_zero = {zero_padding_w, leading_zeroes},
prio_mag_int_a = {mag_int_a_reg, 1'b1},
result = result_reg,
result_w = {sign_bus, exponent_bus, mantissa_bus},
shifted_mag_int_a = wire_altbarrel_shift5_result[14:0],
sign_bus = sign_int_a_reg5,
sign_int_a = dataa[15],
zero_padding_w = {4{1'b0}};
endmodule |
module int16_float32 (
clock,
dataa,
result);
input clock;
input [15:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
int16_float32_altfp_convert_bqm int16_float32_altfp_convert_bqm_component (
.clock (clock),
.dataa (dataa),
.result (sub_wire0));
endmodule |
module full_adder (a0, b0, c0, a1, b1, c_out, s_out, s2, s3);
// Inputs_top
input a0;
input b0;
input c0;
input a1;
input b1;
// End of inputs_top
// Outputs_top
output c_out;
output s_out;
output s2;
output d1;
output s3;
// End of outputs_top
// Wires
wire c1;
wire c2;
wire s1;
wire d1;
wire c3;
// Some assignments
assign carry_out = c1 | c2;
assign s_out = s1;
//assign d_out = d1;
// Instantiating two half-adders to make the circuit.
// Module instantiation
half_adder u1_half_adder (
// Inputs
.in_x(a0),
.in_y(b0),
// End of inputs
// Outputs
.out_sum(s0),
.out_carry(c1)
// End of outputs
);
// Module instantiation
half_adder u2_half_adder (
// Inputs
.in_x(s0),
.in_y(c0),
// End of inputs
// Outputs
.out_sum(s1),
.out_carry(c2)
// End of outputs
);
// Module instantiation
test1 test1 (
// Inputs
.in_1(s1),
.in_2(s0),
.in_3(a1),
.in_4(b1),
// End of inputs
// Outputs
.out_1(s2),
.out_2(d1),
.out_3(c3)
// End of outputs
);
// Module instantiation
test2 test2 (
// Inputs
.in_1(d1),
.in_2(c3),
.in_3(b1),
// End of inputs
// Outputs
.out_1(s3)
// End of outputs
);
endmodule |
module sky130_fd_sc_lp__ha (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_COUT ;
wire pwrgood_pp0_out_COUT;
wire xor0_out_SUM ;
wire pwrgood_pp1_out_SUM ;
// Name Output Other arguments
and and0 (and0_out_COUT , A, B );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, and0_out_COUT, VPWR, VGND);
buf buf0 (COUT , pwrgood_pp0_out_COUT );
xor xor0 (xor0_out_SUM , B, A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf1 (SUM , pwrgood_pp1_out_SUM );
endmodule |
module ADT7310 (
(* intersynth_port = "Reset_n_i", src = "../../verilog/adt7310.v:3" *)
input Reset_n_i,
(* intersynth_port = "Clk_i", src = "../../verilog/adt7310.v:5" *)
input Clk_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIn_s", src = "../../verilog/adt7310.v:7" *)
input Enable_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIRQs_s", src = "../../verilog/adt7310.v:9" *)
output CpuIntr_o,
(* intersynth_conntype = "Bit", intersynth_port = "Outputs_o", src = "../../verilog/adt7310.v:11" *)
output ADT7310CS_n_o,
(* intersynth_conntype = "Byte", intersynth_port = "SPI_DataOut", src = "../../verilog/adt7310.v:13" *)
input[7:0] SPI_Data_i,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_Write", src = "../../verilog/adt7310.v:15" *)
output SPI_Write_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_ReadNext", src = "../../verilog/adt7310.v:17" *)
output SPI_ReadNext_o,
(* intersynth_conntype = "Byte", intersynth_port = "SPI_DataIn", src = "../../verilog/adt7310.v:19" *)
output[7:0] SPI_Data_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_FIFOFull", src = "../../verilog/adt7310.v:21" *)
input SPI_FIFOFull_i,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_FIFOEmpty", src = "../../verilog/adt7310.v:23" *)
input SPI_FIFOEmpty_i,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_Transmission", src = "../../verilog/adt7310.v:25" *)
input SPI_Transmission_i,
(* intersynth_conntype = "Word", intersynth_param = "SPICounterPresetH_i", src = "../../verilog/adt7310.v:27" *)
input[15:0] SPICounterPresetH_i,
(* intersynth_conntype = "Word", intersynth_param = "SPICounterPresetL_i", src = "../../verilog/adt7310.v:29" *)
input[15:0] SPICounterPresetL_i,
(* intersynth_conntype = "Word", intersynth_param = "Threshold_i", src = "../../verilog/adt7310.v:31" *)
input[15:0] Threshold_i,
(* intersynth_conntype = "Word", intersynth_param = "PeriodCounterPreset_i", src = "../../verilog/adt7310.v:33" *)
input[15:0] PeriodCounterPreset_i,
(* intersynth_conntype = "Word", intersynth_param = "SensorValue_o", src = "../../verilog/adt7310.v:35" *)
output[15:0] SensorValue_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_CPOL", src = "../../verilog/adt7310.v:37" *)
output SPI_CPOL_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_CPHA", src = "../../verilog/adt7310.v:39" *)
output SPI_CPHA_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_LSBFE", src = "../../verilog/adt7310.v:41" *)
output SPI_LSBFE_o
);
wire \$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2459 ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:12" *)
wire [15:0] \$techmap\SPIFSM_1.$extract$\Counter32_RV1_Timer$2533.DH_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:13" *)
wire [15:0] \$techmap\SPIFSM_1.$extract$\Counter32_RV1_Timer$2533.DL_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:14" *)
wire \$techmap\SPIFSM_1.$extract$\Counter32_RV1_Timer$2533.Overflow_s ;
wire \$techmap\SPIFSM_1.$procmux$297_CMP ;
wire \$techmap\SPIFSM_1.$procmux$302_CMP ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:8" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2538.Carry_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:7" *)
wire [15:0] \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2538.D_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:11" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2538.Overflow_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:10" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2538.Sign_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:9" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2538.Zero_s ;
(* src = "../../../../counter/verilog/counter_rv1.v:14" *)
wire [15:0] \$techmap\SensorFSM_1.$extract$\Counter_RV1_Timer$2532.D_s ;
(* src = "../../../../counter/verilog/counter_rv1.v:15" *)
wire \$techmap\SensorFSM_1.$extract$\Counter_RV1_Timer$2532.Overflow_s ;
(* src = "../../verilog/spifsm.v:45" *)
wire \SPIFSM_1.SPI_FSM_TimerEnable ;
(* src = "../../verilog/spifsm.v:43" *)
wire \SPIFSM_1.SPI_FSM_TimerOvfl ;
(* src = "../../verilog/spifsm.v:44" *)
wire \SPIFSM_1.SPI_FSM_TimerPreset ;
(* src = "../../verilog/spifsm.v:47" *)
wire \SPIFSM_1.SPI_FSM_Wr0 ;
(* src = "../../verilog/spifsm.v:46" *)
wire \SPIFSM_1.SPI_FSM_Wr1 ;
(* keep = 1, src = "../../verilog/adt7310.v:56" *)
wire [7:0] SPIFSM_Byte0_s;
(* keep = 1, src = "../../verilog/adt7310.v:58" *)
wire [7:0] SPIFSM_Byte1_s;
(* keep = 1, src = "../../verilog/adt7310.v:54" *)
wire SPIFSM_Done_s;
(* keep = 1, src = "../../verilog/adt7310.v:52" *)
wire SPIFSM_Start_s;
(* src = "../../verilog/sensorfsm.v:39" *)
wire [15:0] \SensorFSM_1.AbsDiffResult ;
(* src = "../../verilog/sensorfsm.v:33" *)
wire \SensorFSM_1.SensorFSM_StoreNewValue ;
(* src = "../../verilog/sensorfsm.v:31" *)
wire \SensorFSM_1.SensorFSM_TimerEnable ;
(* src = "../../verilog/sensorfsm.v:29" *)
wire \SensorFSM_1.SensorFSM_TimerOvfl ;
(* src = "../../verilog/sensorfsm.v:30" *)
wire \SensorFSM_1.SensorFSM_TimerPreset ;
(* src = "../../verilog/sensorfsm.v:37" *)
wire [15:0] \SensorFSM_1.SensorValue ;
wire SPIFSM_1_Out11_s;
wire SPIFSM_1_Out12_s;
wire SPIFSM_1_Out13_s;
wire SPIFSM_1_Out14_s;
wire SPIFSM_1_CfgMode_s;
wire SPIFSM_1_CfgClk_s;
wire SPIFSM_1_CfgShift_s;
wire SPIFSM_1_CfgDataIn_s;
wire SPIFSM_1_CfgDataOut_s;
wire SensorFSM_1_Out5_s;
wire SensorFSM_1_Out6_s;
wire SensorFSM_1_Out7_s;
wire SensorFSM_1_Out8_s;
wire SensorFSM_1_Out9_s;
wire SensorFSM_1_CfgMode_s;
wire SensorFSM_1_CfgClk_s;
wire SensorFSM_1_CfgShift_s;
wire SensorFSM_1_CfgDataIn_s;
wire SensorFSM_1_CfgDataOut_s;
Byte2Word \$extract$\Byte2Word$2543 (
.H_i(SPIFSM_Byte1_s),
.L_i(SPIFSM_Byte0_s),
.Y_o(\SensorFSM_1.SensorValue )
);
ByteMuxQuad \$techmap\SPIFSM_1.$extract$\ByteMuxQuad$2539 (
.A_i(8'b00001000),
.B_i(8'b11111111),
.C_i(8'b01010000),
.D_i(8'b00100000),
.SAB_i(\$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2459 ),
.SC_i(\$techmap\SPIFSM_1.$procmux$297_CMP ),
.SD_i(\$techmap\SPIFSM_1.$procmux$302_CMP ),
.Y_o(SPI_Data_o)
);
ByteRegister \$techmap\SPIFSM_1.$extract$\ByteRegister$2536 (
.Clk_i(Clk_i),
.D_i(SPI_Data_i),
.Enable_i(\SPIFSM_1.SPI_FSM_Wr0 ),
.Q_o(SPIFSM_Byte0_s),
.Reset_n_i(Reset_n_i)
);
ByteRegister \$techmap\SPIFSM_1.$extract$\ByteRegister$2537 (
.Clk_i(Clk_i),
.D_i(SPI_Data_i),
.Enable_i(\SPIFSM_1.SPI_FSM_Wr1 ),
.Q_o(SPIFSM_Byte1_s),
.Reset_n_i(Reset_n_i)
);
(* src = "../../../../counter32/verilog/counter32_rv1.v:19" *)
Counter32 \$techmap\SPIFSM_1.$extract$\Counter32_RV1_Timer$2533.ThisCounter (
.Clk_i(Clk_i),
.DH_o(\$techmap\SPIFSM_1.$extract$\Counter32_RV1_Timer$2533.DH_s ),
.DL_o(\$techmap\SPIFSM_1.$extract$\Counter32_RV1_Timer$2533.DL_s ),
.Direction_i(1'b1),
.Enable_i(\SPIFSM_1.SPI_FSM_TimerEnable ),
.Overflow_o(\$techmap\SPIFSM_1.$extract$\Counter32_RV1_Timer$2533.Overflow_s ),
.PresetValH_i(SPICounterPresetH_i),
.PresetValL_i(SPICounterPresetL_i),
.Preset_i(\SPIFSM_1.SPI_FSM_TimerPreset ),
.ResetSig_i(1'b0),
.Reset_n_i(Reset_n_i),
.Zero_o(\SPIFSM_1.SPI_FSM_TimerOvfl )
);
SPIFSM SPIFSM_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.In0_i(\SPIFSM_1.SPI_FSM_TimerOvfl ),
.In1_i(SPI_Transmission_i),
.In2_i(SPIFSM_Start_s),
.In3_i(1'b0),
.In4_i(1'b0),
.In5_i(1'b0),
.In6_i(1'b0),
.In7_i(1'b0),
.Out0_o(\$techmap\SPIFSM_1.$procmux$297_CMP ),
.Out1_o(\$techmap\SPIFSM_1.$procmux$302_CMP ),
.Out2_o(\SPIFSM_1.SPI_FSM_Wr0 ),
.Out3_o(\SPIFSM_1.SPI_FSM_Wr1 ),
.Out4_o(\$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2459 ),
.Out5_o(\SPIFSM_1.SPI_FSM_TimerEnable ),
.Out6_o(\SPIFSM_1.SPI_FSM_TimerPreset ),
.Out7_o(ADT7310CS_n_o),
.Out8_o(SPIFSM_Done_s),
.Out9_o(SPI_Write_o),
.Out10_o(SPI_ReadNext_o),
.Out11_o(SPIFSM_1_Out11_s),
.Out12_o(SPIFSM_1_Out12_s),
.Out13_o(SPIFSM_1_Out13_s),
.Out14_o(SPIFSM_1_Out14_s),
.CfgMode_i(SPIFSM_1_CfgMode_s),
.CfgClk_i(SPIFSM_1_CfgClk_s),
.CfgShift_i(SPIFSM_1_CfgShift_s),
.CfgDataIn_i(SPIFSM_1_CfgDataIn_s),
.CfgDataOut_o(SPIFSM_1_CfgDataOut_s)
);
AbsDiff \$techmap\SensorFSM_1.$extract$\AbsDiff$2534 (
.A_i(\SensorFSM_1.SensorValue ),
.B_i(SensorValue_o),
.D_o(\SensorFSM_1.AbsDiffResult )
);
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:13" *)
AddSubCmp \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2538.ThisAddSubCmp (
.A_i(\SensorFSM_1.AbsDiffResult ),
.AddOrSub_i(1'b1),
.B_i(Threshold_i),
.Carry_i(1'b0),
.Carry_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2538.Carry_s ),
.D_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2538.D_s ),
.Overflow_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2538.Overflow_s ),
.Sign_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2538.Sign_s ),
.Zero_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2538.Zero_s )
);
(* src = "../../../../counter/verilog/counter_rv1.v:20" *)
Counter \$techmap\SensorFSM_1.$extract$\Counter_RV1_Timer$2532.ThisCounter (
.Clk_i(Clk_i),
.D_o(\$techmap\SensorFSM_1.$extract$\Counter_RV1_Timer$2532.D_s ),
.Direction_i(1'b1),
.Enable_i(\SensorFSM_1.SensorFSM_TimerEnable ),
.Overflow_o(\$techmap\SensorFSM_1.$extract$\Counter_RV1_Timer$2532.Overflow_s ),
.PresetVal_i(PeriodCounterPreset_i),
.Preset_i(\SensorFSM_1.SensorFSM_TimerPreset ),
.ResetSig_i(1'b0),
.Reset_n_i(Reset_n_i),
.Zero_o(\SensorFSM_1.SensorFSM_TimerOvfl )
);
WordRegister \$techmap\SensorFSM_1.$extract$\WordRegister$2535 (
.Clk_i(Clk_i),
.D_i(\SensorFSM_1.SensorValue ),
.Enable_i(\SensorFSM_1.SensorFSM_StoreNewValue ),
.Q_o(SensorValue_o),
.Reset_n_i(Reset_n_i)
);
SensorFSM SensorFSM_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.In0_i(Enable_i),
.In1_i(SPIFSM_Done_s),
.In2_i(\SensorFSM_1.SensorFSM_TimerOvfl ),
.In3_i(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2538.Carry_s ),
.In4_i(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2538.Zero_s ),
.In5_i(1'b0),
.In6_i(1'b0),
.In7_i(1'b0),
.In8_i(1'b0),
.In9_i(1'b0),
.Out0_o(SPIFSM_Start_s),
.Out1_o(\SensorFSM_1.SensorFSM_StoreNewValue ),
.Out2_o(\SensorFSM_1.SensorFSM_TimerEnable ),
.Out3_o(\SensorFSM_1.SensorFSM_TimerPreset ),
.Out4_o(CpuIntr_o),
.Out5_o(SensorFSM_1_Out5_s),
.Out6_o(SensorFSM_1_Out6_s),
.Out7_o(SensorFSM_1_Out7_s),
.Out8_o(SensorFSM_1_Out8_s),
.Out9_o(SensorFSM_1_Out9_s),
.CfgMode_i(SensorFSM_1_CfgMode_s),
.CfgClk_i(SensorFSM_1_CfgClk_s),
.CfgShift_i(SensorFSM_1_CfgShift_s),
.CfgDataIn_i(SensorFSM_1_CfgDataIn_s),
.CfgDataOut_o(SensorFSM_1_CfgDataOut_s)
);
assign SPI_CPHA_o = 1'b1;
assign SPI_CPOL_o = 1'b1;
assign SPI_LSBFE_o = 1'b0;
assign SPIFSM_1_CfgMode_s = 1'b0;
assign SPIFSM_1_CfgClk_s = 1'b0;
assign SPIFSM_1_CfgShift_s = 1'b0;
assign SPIFSM_1_CfgDataIn_s = 1'b0;
assign SensorFSM_1_CfgMode_s = 1'b0;
assign SensorFSM_1_CfgClk_s = 1'b0;
assign SensorFSM_1_CfgShift_s = 1'b0;
assign SensorFSM_1_CfgDataIn_s = 1'b0;
endmodule |
module sky130_fd_sc_hd__mux4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_4to20_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_4to2 mux_4to20 (mux_4to20_out_X , A0, A1, A2, A3, S0, S1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_4to20_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule |
module FPU_PIPELINED_FPADDSUB_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [63:0] Data_X;
input [63:0] Data_Y;
output [63:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire intAS, SIGN_FLAG_EXP, OP_FLAG_EXP, ZERO_FLAG_EXP, SIGN_FLAG_SHT1,
OP_FLAG_SHT1, ZERO_FLAG_SHT1, left_right_SHT2, SIGN_FLAG_SHT2,
OP_FLAG_SHT2, ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2,
SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG, ZERO_FLAG_SFG,
inst_FSM_INPUT_ENABLE_state_next_1_, n1037, n1038, n1039, n1040,
n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050,
n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060,
n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070,
n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080,
n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090,
n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100,
n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110,
n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120,
n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130,
n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140,
n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150,
n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160,
n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170,
n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180,
n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190,
n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200,
n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210,
n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221,
n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231,
n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241,
n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251,
n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261,
n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271,
n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281,
n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291,
n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301,
n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311,
n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321,
n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331,
n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341,
n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351,
n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361,
n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371,
n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381,
n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391,
n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401,
n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411,
n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421,
n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431,
n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441,
n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451,
n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461,
n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471,
n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481,
n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491,
n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501,
n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511,
n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521,
n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531,
n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541,
n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551,
n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561,
n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571,
n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581,
n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591,
n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601,
n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611,
n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621,
n1622, n1623, n1624, n1625, n1626, n1628, n1629, n1630, n1631, n1632,
n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642,
n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652,
n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661, n1662,
n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671, n1672,
n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681, n1682,
n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692,
n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702,
n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712,
n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722,
n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732,
n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742,
n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752,
n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762,
n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772,
n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782,
n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792,
n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802,
n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812,
n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1822, n1823, n1824,
DP_OP_15J75_123_4372_n11, DP_OP_15J75_123_4372_n10,
DP_OP_15J75_123_4372_n9, DP_OP_15J75_123_4372_n8,
DP_OP_15J75_123_4372_n7, DP_OP_15J75_123_4372_n6, n1825, n1826, n1827,
n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837,
n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847,
n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857,
n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867,
n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877,
n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887,
n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897,
n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907,
n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917,
n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927,
n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937,
n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947,
n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957,
n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967,
n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977,
n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987,
n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997,
n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007,
n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017,
n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027,
n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037,
n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047,
n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057,
n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067,
n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077,
n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087,
n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097,
n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107,
n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117,
n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127,
n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137,
n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147,
n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155, n2156, n2157,
n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165, n2166, n2167,
n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175, n2176, n2177,
n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185, n2186, n2187,
n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195, n2196, n2197,
n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207,
n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217,
n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227,
n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237,
n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247,
n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257,
n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267,
n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277,
n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287,
n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297,
n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307,
n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317,
n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327,
n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337,
n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347,
n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357,
n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367,
n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377,
n2378, n2379, n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387,
n2388, n2389, n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397,
n2398, n2399, n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407,
n2408, n2409, n2410, n2411, n2412, n2413, n2414, n2415, n2416, n2417,
n2418, n2419, n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427,
n2428, n2429, n2430, n2431, n2432, n2433, n2434, n2435, n2436, n2437,
n2438, n2439, n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447,
n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457,
n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467,
n2468, n2469, n2470, n2471, n2472, n2473, n2474, n2475, n2476, n2477,
n2478, n2479, n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487,
n2488, n2489, n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497,
n2498, n2499, n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507,
n2508, n2509, n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517,
n2518, n2519, n2520, n2521, n2522, n2523, n2524, n2525, n2526, n2527,
n2528, n2529, n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2537,
n2538, n2539, n2540, n2541, n2542, n2543, n2544, n2545, n2546, n2547,
n2548, n2549, n2550, n2551, n2552, n2553, n2554, n2555, n2556, n2557,
n2558, n2559, n2560, n2561, n2562, n2563, n2564, n2565, n2566, n2567,
n2568, n2569, n2570, n2571, n2572, n2573, n2574, n2575, n2576, n2577,
n2578, n2579, n2580, n2581, n2582, n2583, n2584, n2585, n2586, n2587,
n2588, n2589, n2590, n2591, n2592, n2593, n2594, n2595, n2596, n2597,
n2598, n2599, n2600, n2601, n2602, n2603, n2604, n2605, n2606, n2607,
n2608, n2609, n2610, n2611, n2612, n2613, n2614, n2615, n2616, n2617,
n2618, n2619, n2620, n2621, n2622, n2623, n2624, n2625, n2626, n2627,
n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635, n2636, n2637,
n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645, n2646, n2647,
n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655, n2656, n2657,
n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665, n2666, n2667,
n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675, n2676, n2677,
n2678, n2679, n2680, n2681, n2682, n2683, n2684, n2685, n2686, n2687,
n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695, n2696, n2697,
n2698, n2699, n2700, n2701, n2702, n2703, n2704, n2705, n2706, n2707,
n2708, n2709, n2710, n2711, n2712, n2713, n2714, n2715, n2716, n2717,
n2718, n2719, n2720, n2721, n2722, n2723, n2724, n2725, n2726, n2727,
n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735, n2736, n2737,
n2738, n2739, n2740, n2741, n2742, n2743, n2744, n2745, n2746, n2747,
n2748, n2749, n2750, n2751, n2752, n2753, n2754, n2755, n2756, n2757,
n2758, n2759, n2760, n2761, n2762, n2763, n2764, n2765, n2766, n2767,
n2768, n2769, n2770, n2771, n2773, n2774, n2775, n2776, n2777, n2778,
n2779, n2780, n2781, n2782, n2783, n2784, n2785, n2786, n2787, n2788,
n2789, n2790, n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799,
n2800, n2801, n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809,
n2810, n2811, n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819,
n2820, n2821, n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829,
n2830, n2831, n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839,
n2840, n2841, n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849,
n2850, n2851, n2852, n2854, n2855, n2856, n2857, n2858, n2859, n2860,
n2861, n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870,
n2871, n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880,
n2881, n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890,
n2891, n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900,
n2901, n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910,
n2911, n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920,
n2921, n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930,
n2931, n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940,
n2941, n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950,
n2951, n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960,
n2961, n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970,
n2971, n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980,
n2981, n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990,
n2991, n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000,
n3001, n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010,
n3011, n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020,
n3021, n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030,
n3031, n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040,
n3041, n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050,
n3051, n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060,
n3061, n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070,
n3071, n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080,
n3081, n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090,
n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100,
n3101, n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110,
n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122,
n3123, n3124, n3125, n3126, n3127, n3128, n3130, n3131, n3132, n3133,
n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143,
n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153,
n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163,
n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173,
n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183,
n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193,
n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203,
n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213,
n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223,
n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233,
n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243,
n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3253, n3254,
n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263, n3264,
n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273, n3274,
n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283, n3284,
n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293, n3294,
n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303, n3304,
n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313, n3314,
n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323, n3324,
n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333, n3334,
n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343, n3344,
n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353, n3354,
n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363, n3364,
n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373, n3374,
n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383, n3384,
n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393, n3394,
n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403, n3404,
n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413, n3414,
n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423, n3424,
n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433, n3434,
n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443, n3444,
n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453, n3454,
n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463, n3464,
n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473, n3474,
n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483, n3484,
n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493, n3494,
n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503, n3504,
n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513, n3514,
n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523, n3524,
n3525, n3526, n3527, n3528, n3530;
wire [1:0] Shift_reg_FLAGS_7;
wire [63:0] intDX_EWSW;
wire [63:0] intDY_EWSW;
wire [62:0] DMP_EXP_EWSW;
wire [57:0] DmP_EXP_EWSW;
wire [62:0] DMP_SHT1_EWSW;
wire [51:1] DmP_mant_SHT1_SW;
wire [5:1] Shift_amount_SHT1_EWR;
wire [54:0] Raw_mant_NRM_SWR;
wire [34:0] Data_array_SWR;
wire [62:0] DMP_SHT2_EWSW;
wire [5:2] shift_value_SHT2_EWR;
wire [10:0] DMP_exp_NRM2_EW;
wire [10:0] DMP_exp_NRM_EW;
wire [5:0] LZD_output_NRM2_EW;
wire [5:1] exp_rslt_NRM2_EW1;
wire [62:0] DMP_SFG;
wire [45:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_6_ ( .D(n1822), .CK(clk), .RN(n3507), .Q(
n1832), .QN(n1997) );
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n1819), .CK(clk), .RN(n3471), .QN(
n1865) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1751), .CK(clk), .RN(n3492), .Q(
intAS) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(n3468), .CK(clk), .RN(n3494), .Q(ready) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_52_ ( .D(n1683), .CK(clk), .RN(n3486), .QN(
n1841) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_38_ ( .D(n1669), .CK(clk), .RN(n3477), .Q(
Data_array_SWR[20]), .QN(n3456) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_37_ ( .D(n1668), .CK(clk), .RN(n3486), .Q(
Data_array_SWR[19]), .QN(n3455) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_36_ ( .D(n1667), .CK(clk), .RN(n3477), .Q(
Data_array_SWR[18]), .QN(n3457) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_35_ ( .D(n1666), .CK(clk), .RN(n3478), .QN(
n1836) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_34_ ( .D(n1665), .CK(clk), .RN(n3477), .QN(
n1834) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_33_ ( .D(n1664), .CK(clk), .RN(n3477), .QN(
n1838) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_32_ ( .D(n1663), .CK(clk), .RN(n3477), .QN(
n1837) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_31_ ( .D(n1662), .CK(clk), .RN(n3517), .QN(
n1828) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_30_ ( .D(n1661), .CK(clk), .RN(n3478), .QN(
n1869) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_28_ ( .D(n1659), .CK(clk), .RN(n3478), .QN(
n1874) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n1653), .CK(clk), .RN(n3478), .QN(
n1879) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n1651), .CK(clk), .RN(n3478), .QN(
n1878) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n1649), .CK(clk), .RN(n3477), .QN(
n1830) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n1646), .CK(clk), .RN(n3517), .QN(
n1831) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n1645), .CK(clk), .RN(n3477), .QN(
n1842) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n1644), .CK(clk), .RN(n3478), .QN(
n1844) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n1643), .CK(clk), .RN(n3477), .QN(
n1843) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n1642), .CK(clk), .RN(n3477), .QN(
n1845) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n1641), .CK(clk), .RN(n3477), .QN(
n1846) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n1640), .CK(clk), .RN(n3494), .QN(
n1847) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n1639), .CK(clk), .RN(n3477), .QN(
n1848) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n1634), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[3]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_45_ ( .D(n1676), .CK(clk), .RN(n3482), .QN(
n1839) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1625), .CK(clk), .RN(n3484),
.QN(n1840) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1624), .CK(clk), .RN(n3525),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1623), .CK(clk), .RN(n3496),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1622), .CK(clk), .RN(n3519),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1621), .CK(clk), .RN(n3484),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_5_ ( .D(n1620), .CK(clk), .RN(n3522),
.Q(Shift_amount_SHT1_EWR[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_52_ ( .D(n1619), .CK(clk), .RN(n3514), .Q(
final_result_ieee[52]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_53_ ( .D(n1618), .CK(clk), .RN(n3508), .Q(
final_result_ieee[53]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_54_ ( .D(n1617), .CK(clk), .RN(n3514), .Q(
final_result_ieee[54]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_55_ ( .D(n1616), .CK(clk), .RN(n3508), .Q(
final_result_ieee[55]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_56_ ( .D(n1615), .CK(clk), .RN(n3484), .Q(
final_result_ieee[56]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_57_ ( .D(n1614), .CK(clk), .RN(n3521), .Q(
final_result_ieee[57]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_58_ ( .D(n1613), .CK(clk), .RN(n3511), .Q(
final_result_ieee[58]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_59_ ( .D(n1612), .CK(clk), .RN(n3484), .Q(
final_result_ieee[59]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_60_ ( .D(n1611), .CK(clk), .RN(n3521), .Q(
final_result_ieee[60]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_61_ ( .D(n1610), .CK(clk), .RN(n3510), .Q(
final_result_ieee[61]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_62_ ( .D(n1609), .CK(clk), .RN(n3511), .Q(
final_result_ieee[62]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n1608), .CK(clk), .RN(n3525), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n1607), .CK(clk), .RN(n3513), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n1606), .CK(clk), .RN(n3486), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n1605), .CK(clk), .RN(n3482), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n1604), .CK(clk), .RN(n3512), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n1603), .CK(clk), .RN(n3485), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n1602), .CK(clk), .RN(n3511), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n1601), .CK(clk), .RN(n3511), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n1600), .CK(clk), .RN(n3522), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n1599), .CK(clk), .RN(n3525), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n1598), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n1597), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n1596), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n1595), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n1594), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n1593), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n1592), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n1591), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n1590), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n1589), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n1588), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n1587), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n1586), .CK(clk), .RN(n3491), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_23_ ( .D(n1585), .CK(clk), .RN(n3483), .Q(
DMP_EXP_EWSW[23]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_24_ ( .D(n1584), .CK(clk), .RN(n3525), .Q(
DMP_EXP_EWSW[24]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_25_ ( .D(n1583), .CK(clk), .RN(n3483), .Q(
DMP_EXP_EWSW[25]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_26_ ( .D(n1582), .CK(clk), .RN(n3511), .Q(
DMP_EXP_EWSW[26]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n1581), .CK(clk), .RN(n3525), .Q(
DMP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n1580), .CK(clk), .RN(n3483), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n1579), .CK(clk), .RN(n3488), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n1578), .CK(clk), .RN(n3525), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_31_ ( .D(n1577), .CK(clk), .RN(n3482), .Q(
DMP_EXP_EWSW[31]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_32_ ( .D(n1576), .CK(clk), .RN(n3491), .Q(
DMP_EXP_EWSW[32]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_33_ ( .D(n1575), .CK(clk), .RN(n3525), .Q(
DMP_EXP_EWSW[33]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_34_ ( .D(n1574), .CK(clk), .RN(n3530), .Q(
DMP_EXP_EWSW[34]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_35_ ( .D(n1573), .CK(clk), .RN(n3485), .Q(
DMP_EXP_EWSW[35]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_36_ ( .D(n1572), .CK(clk), .RN(n3530), .Q(
DMP_EXP_EWSW[36]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_37_ ( .D(n1571), .CK(clk), .RN(n3488), .Q(
DMP_EXP_EWSW[37]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_38_ ( .D(n1570), .CK(clk), .RN(n3530), .Q(
DMP_EXP_EWSW[38]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_39_ ( .D(n1569), .CK(clk), .RN(n3483), .Q(
DMP_EXP_EWSW[39]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_40_ ( .D(n1568), .CK(clk), .RN(n3511), .Q(
DMP_EXP_EWSW[40]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_41_ ( .D(n1567), .CK(clk), .RN(n3514), .Q(
DMP_EXP_EWSW[41]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_42_ ( .D(n1566), .CK(clk), .RN(n3518), .Q(
DMP_EXP_EWSW[42]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_43_ ( .D(n1565), .CK(clk), .RN(n3516), .Q(
DMP_EXP_EWSW[43]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_44_ ( .D(n1564), .CK(clk), .RN(n3503), .Q(
DMP_EXP_EWSW[44]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_45_ ( .D(n1563), .CK(clk), .RN(n3530), .Q(
DMP_EXP_EWSW[45]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_46_ ( .D(n1562), .CK(clk), .RN(n3524), .Q(
DMP_EXP_EWSW[46]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_47_ ( .D(n1561), .CK(clk), .RN(n3481), .Q(
DMP_EXP_EWSW[47]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_48_ ( .D(n1560), .CK(clk), .RN(n3481), .Q(
DMP_EXP_EWSW[48]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_49_ ( .D(n1559), .CK(clk), .RN(n3524), .Q(
DMP_EXP_EWSW[49]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_50_ ( .D(n1558), .CK(clk), .RN(n3481), .Q(
DMP_EXP_EWSW[50]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_51_ ( .D(n1557), .CK(clk), .RN(n3524), .Q(
DMP_EXP_EWSW[51]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_58_ ( .D(n1550), .CK(clk), .RN(n3506), .Q(
DMP_EXP_EWSW[58]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_59_ ( .D(n1549), .CK(clk), .RN(n3479), .Q(
DMP_EXP_EWSW[59]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_60_ ( .D(n1548), .CK(clk), .RN(n3503), .Q(
DMP_EXP_EWSW[60]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_61_ ( .D(n1547), .CK(clk), .RN(n3475), .Q(
DMP_EXP_EWSW[61]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_62_ ( .D(n1546), .CK(clk), .RN(n3497), .Q(
DMP_EXP_EWSW[62]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1545), .CK(clk), .RN(n3498), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n1544), .CK(clk), .RN(n3492), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1543), .CK(clk), .RN(n3525), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1542), .CK(clk), .RN(n3505), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n1541), .CK(clk), .RN(n3472), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1539), .CK(clk), .RN(n3506), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n1538), .CK(clk), .RN(n3490), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1536), .CK(clk), .RN(n3500), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n1535), .CK(clk), .RN(n3517), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n1534), .CK(clk), .RN(n3481), .Q(
DMP_SFG[2]), .QN(n3466) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1533), .CK(clk), .RN(n3496), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n1532), .CK(clk), .RN(n3489), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1530), .CK(clk), .RN(n3524), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n1529), .CK(clk), .RN(n3499), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_4_ ( .D(n1528), .CK(clk), .RN(n3510), .QN(n1849) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1527), .CK(clk), .RN(n3500), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n1526), .CK(clk), .RN(n3522), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1524), .CK(clk), .RN(n3518), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n1523), .CK(clk), .RN(n3493), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_6_ ( .D(n1522), .CK(clk), .RN(n3515), .QN(n1880) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1521), .CK(clk), .RN(n3504), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n1520), .CK(clk), .RN(n3482), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1518), .CK(clk), .RN(n3492), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1517), .CK(clk), .RN(n3524), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1515), .CK(clk), .RN(n3518), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1514), .CK(clk), .RN(n3483), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1512), .CK(clk), .RN(n3483), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1511), .CK(clk), .RN(n3483), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1509), .CK(clk), .RN(n3483), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1508), .CK(clk), .RN(n3483), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1506), .CK(clk), .RN(n3483), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n1505), .CK(clk), .RN(n3483), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1503), .CK(clk), .RN(n3483), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n1502), .CK(clk), .RN(n3510), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1500), .CK(clk), .RN(n3521), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n1499), .CK(clk), .RN(n3484), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1497), .CK(clk), .RN(n3513), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n1496), .CK(clk), .RN(n3512), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1494), .CK(clk), .RN(n3511), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n1493), .CK(clk), .RN(n3510), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1491), .CK(clk), .RN(n3521), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1490), .CK(clk), .RN(n3508), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1488), .CK(clk), .RN(n3508), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1487), .CK(clk), .RN(n3480), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1485), .CK(clk), .RN(n3478), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1484), .CK(clk), .RN(n3477), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1482), .CK(clk), .RN(n3494), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1481), .CK(clk), .RN(n3487), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1479), .CK(clk), .RN(n3521), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1478), .CK(clk), .RN(n3485), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1476), .CK(clk), .RN(n3522), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1475), .CK(clk), .RN(n3486), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1473), .CK(clk), .RN(n3485), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1472), .CK(clk), .RN(n3522), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1470), .CK(clk), .RN(n3486), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1469), .CK(clk), .RN(n3485), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1467), .CK(clk), .RN(n3522), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1466), .CK(clk), .RN(n3485), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1464), .CK(clk), .RN(n3486), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1463), .CK(clk), .RN(n3485), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1461), .CK(clk), .RN(n3486), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1460), .CK(clk), .RN(n3485), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1458), .CK(clk), .RN(n3486), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1457), .CK(clk), .RN(n3485), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1455), .CK(clk), .RN(n3486), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1454), .CK(clk), .RN(n3519), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1452), .CK(clk), .RN(n3488), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1451), .CK(clk), .RN(n3519), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_31_ ( .D(n1449), .CK(clk), .RN(n3488), .Q(
DMP_SHT1_EWSW[31]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_31_ ( .D(n1448), .CK(clk), .RN(n3519), .Q(
DMP_SHT2_EWSW[31]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_32_ ( .D(n1446), .CK(clk), .RN(n3488), .Q(
DMP_SHT1_EWSW[32]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_32_ ( .D(n1445), .CK(clk), .RN(n3519), .Q(
DMP_SHT2_EWSW[32]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_33_ ( .D(n1443), .CK(clk), .RN(n3488), .Q(
DMP_SHT1_EWSW[33]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_33_ ( .D(n1442), .CK(clk), .RN(n3519), .Q(
DMP_SHT2_EWSW[33]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_34_ ( .D(n1440), .CK(clk), .RN(n3488), .Q(
DMP_SHT1_EWSW[34]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_34_ ( .D(n1439), .CK(clk), .RN(n3519), .Q(
DMP_SHT2_EWSW[34]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_35_ ( .D(n1437), .CK(clk), .RN(n3488), .Q(
DMP_SHT1_EWSW[35]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_35_ ( .D(n1436), .CK(clk), .RN(n3519), .Q(
DMP_SHT2_EWSW[35]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_36_ ( .D(n1434), .CK(clk), .RN(n3488), .Q(
DMP_SHT1_EWSW[36]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_36_ ( .D(n1433), .CK(clk), .RN(n3519), .Q(
DMP_SHT2_EWSW[36]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_37_ ( .D(n1431), .CK(clk), .RN(n3488), .Q(
DMP_SHT1_EWSW[37]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_37_ ( .D(n1430), .CK(clk), .RN(n3489), .Q(
DMP_SHT2_EWSW[37]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_38_ ( .D(n1428), .CK(clk), .RN(n3489), .Q(
DMP_SHT1_EWSW[38]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_38_ ( .D(n1427), .CK(clk), .RN(n3489), .Q(
DMP_SHT2_EWSW[38]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_39_ ( .D(n1425), .CK(clk), .RN(n3489), .Q(
DMP_SHT1_EWSW[39]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_39_ ( .D(n1424), .CK(clk), .RN(n3489), .Q(
DMP_SHT2_EWSW[39]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_40_ ( .D(n1422), .CK(clk), .RN(n3489), .Q(
DMP_SHT1_EWSW[40]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_40_ ( .D(n1421), .CK(clk), .RN(n3489), .Q(
DMP_SHT2_EWSW[40]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_41_ ( .D(n1419), .CK(clk), .RN(n3489), .Q(
DMP_SHT1_EWSW[41]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_41_ ( .D(n1418), .CK(clk), .RN(n3490), .Q(
DMP_SHT2_EWSW[41]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_42_ ( .D(n1416), .CK(clk), .RN(n3490), .Q(
DMP_SHT1_EWSW[42]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_42_ ( .D(n1415), .CK(clk), .RN(n3490), .Q(
DMP_SHT2_EWSW[42]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_43_ ( .D(n1413), .CK(clk), .RN(n3490), .Q(
DMP_SHT1_EWSW[43]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_43_ ( .D(n1412), .CK(clk), .RN(n3490), .Q(
DMP_SHT2_EWSW[43]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_44_ ( .D(n1410), .CK(clk), .RN(n3490), .Q(
DMP_SHT1_EWSW[44]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_44_ ( .D(n1409), .CK(clk), .RN(n3490), .Q(
DMP_SHT2_EWSW[44]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_45_ ( .D(n1407), .CK(clk), .RN(n3490), .Q(
DMP_SHT1_EWSW[45]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_45_ ( .D(n1406), .CK(clk), .RN(n3523), .Q(
DMP_SHT2_EWSW[45]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_46_ ( .D(n1404), .CK(clk), .RN(n3491), .Q(
DMP_SHT1_EWSW[46]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_46_ ( .D(n1403), .CK(clk), .RN(n3523), .Q(
DMP_SHT2_EWSW[46]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_47_ ( .D(n1401), .CK(clk), .RN(n3491), .Q(
DMP_SHT1_EWSW[47]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_47_ ( .D(n1400), .CK(clk), .RN(n3523), .Q(
DMP_SHT2_EWSW[47]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_48_ ( .D(n1398), .CK(clk), .RN(n3491), .Q(
DMP_SHT1_EWSW[48]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_48_ ( .D(n1397), .CK(clk), .RN(n3523), .Q(
DMP_SHT2_EWSW[48]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_49_ ( .D(n1395), .CK(clk), .RN(n3491), .Q(
DMP_SHT1_EWSW[49]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_49_ ( .D(n1394), .CK(clk), .RN(n3487), .Q(
DMP_SHT2_EWSW[49]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_50_ ( .D(n1392), .CK(clk), .RN(n3523), .Q(
DMP_SHT1_EWSW[50]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_50_ ( .D(n1391), .CK(clk), .RN(n3516), .Q(
DMP_SHT2_EWSW[50]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_51_ ( .D(n1389), .CK(clk), .RN(n3491), .Q(
DMP_SHT1_EWSW[51]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_51_ ( .D(n1388), .CK(clk), .RN(n3530), .Q(
DMP_SHT2_EWSW[51]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_52_ ( .D(n1386), .CK(clk), .RN(n3523), .Q(
DMP_SHT1_EWSW[52]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_52_ ( .D(n1385), .CK(clk), .RN(n3530), .Q(
DMP_SHT2_EWSW[52]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_52_ ( .D(n1384), .CK(clk), .RN(n3520), .Q(
DMP_SFG[52]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1383), .CK(clk), .RN(n3491), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_53_ ( .D(n1381), .CK(clk), .RN(n3493), .Q(
DMP_SHT1_EWSW[53]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_53_ ( .D(n1380), .CK(clk), .RN(n3515), .Q(
DMP_SHT2_EWSW[53]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_53_ ( .D(n1379), .CK(clk), .RN(n3504), .Q(
DMP_SFG[53]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1378), .CK(clk), .RN(n3482), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_54_ ( .D(n1376), .CK(clk), .RN(n3492), .Q(
DMP_SHT1_EWSW[54]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_54_ ( .D(n1375), .CK(clk), .RN(n3485), .Q(
DMP_SHT2_EWSW[54]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_54_ ( .D(n1374), .CK(clk), .RN(n3518), .Q(
DMP_SFG[54]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1373), .CK(clk), .RN(n3493), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_55_ ( .D(n1371), .CK(clk), .RN(n3515), .Q(
DMP_SHT1_EWSW[55]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_55_ ( .D(n1370), .CK(clk), .RN(n3504), .Q(
DMP_SHT2_EWSW[55]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_55_ ( .D(n1369), .CK(clk), .RN(n3482), .Q(
DMP_SFG[55]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1368), .CK(clk), .RN(n3492), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_56_ ( .D(n1366), .CK(clk), .RN(n3515), .Q(
DMP_SHT1_EWSW[56]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_56_ ( .D(n1365), .CK(clk), .RN(n3504), .Q(
DMP_SHT2_EWSW[56]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_56_ ( .D(n1364), .CK(clk), .RN(n3482), .Q(
DMP_SFG[56]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1363), .CK(clk), .RN(n3492), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_57_ ( .D(n1361), .CK(clk), .RN(n3486), .Q(
DMP_SHT1_EWSW[57]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_57_ ( .D(n1360), .CK(clk), .RN(n3518), .Q(
DMP_SHT2_EWSW[57]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_57_ ( .D(n1359), .CK(clk), .RN(n3493), .Q(
DMP_SFG[57]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1358), .CK(clk), .RN(n3515), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_58_ ( .D(n1356), .CK(clk), .RN(n3504), .Q(
DMP_SHT1_EWSW[58]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_58_ ( .D(n1355), .CK(clk), .RN(n3482), .Q(
DMP_SHT2_EWSW[58]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_58_ ( .D(n1354), .CK(clk), .RN(n3492), .Q(
DMP_SFG[58]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1353), .CK(clk), .RN(n3501), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_59_ ( .D(n1351), .CK(clk), .RN(n3515), .Q(
DMP_SHT1_EWSW[59]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_59_ ( .D(n1350), .CK(clk), .RN(n3504), .Q(
DMP_SHT2_EWSW[59]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_59_ ( .D(n1349), .CK(clk), .RN(n3482), .Q(
DMP_SFG[59]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1348), .CK(clk), .RN(n3492), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_60_ ( .D(n1346), .CK(clk), .RN(n3478), .Q(
DMP_SHT1_EWSW[60]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_60_ ( .D(n1345), .CK(clk), .RN(n3515), .Q(
DMP_SHT2_EWSW[60]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_60_ ( .D(n1344), .CK(clk), .RN(n3493), .Q(
DMP_SFG[60]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_8_ ( .D(n1343), .CK(clk), .RN(n3504), .Q(
DMP_exp_NRM_EW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_61_ ( .D(n1341), .CK(clk), .RN(n3482), .Q(
DMP_SHT1_EWSW[61]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_61_ ( .D(n1340), .CK(clk), .RN(n3492), .Q(
DMP_SHT2_EWSW[61]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_61_ ( .D(n1339), .CK(clk), .RN(n3507), .Q(
DMP_SFG[61]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_9_ ( .D(n1338), .CK(clk), .RN(n3493), .Q(
DMP_exp_NRM_EW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_62_ ( .D(n1336), .CK(clk), .RN(n3510), .Q(
DMP_SHT1_EWSW[62]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_62_ ( .D(n1335), .CK(clk), .RN(n3517), .Q(
DMP_SHT2_EWSW[62]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_62_ ( .D(n1334), .CK(clk), .RN(n3487), .Q(
DMP_SFG[62]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_10_ ( .D(n1333), .CK(clk), .RN(n3523), .Q(
DMP_exp_NRM_EW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n1331), .CK(clk), .RN(n3517), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1330), .CK(clk), .RN(n3523),
.QN(n1850) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n1329), .CK(clk), .RN(n3487), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n1327), .CK(clk), .RN(n3517), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n1325), .CK(clk), .RN(n3487), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n1323), .CK(clk), .RN(n3517), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1322), .CK(clk), .RN(n3489),
.QN(n1852) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n1321), .CK(clk), .RN(n3488), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1320), .CK(clk), .RN(n3521),
.QN(n1851) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n1319), .CK(clk), .RN(n3517), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n1317), .CK(clk), .RN(n3490), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1316), .CK(clk), .RN(n3517),
.QN(n1884) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n1315), .CK(clk), .RN(n3487), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n1313), .CK(clk), .RN(n3523), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n1311), .CK(clk), .RN(n3494), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n1309), .CK(clk), .RN(n3494), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n1307), .CK(clk), .RN(n3494), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1306), .CK(clk), .RN(n3494),
.QN(n1891) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n1305), .CK(clk), .RN(n3494), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n1303), .CK(clk), .RN(n3494), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n1301), .CK(clk), .RN(n3494), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1300), .CK(clk), .RN(n3494),
.QN(n1888) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n1299), .CK(clk), .RN(n3495), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n1297), .CK(clk), .RN(n3495), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n1295), .CK(clk), .RN(n3495), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n1293), .CK(clk), .RN(n3495), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1292), .CK(clk), .RN(n3495),
.QN(n1892) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n1291), .CK(clk), .RN(n3495), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n1289), .CK(clk), .RN(n3495), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1288), .CK(clk), .RN(n3495),
.QN(n1893) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n1287), .CK(clk), .RN(n3474), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_23_ ( .D(n1285), .CK(clk), .RN(n3473), .Q(
DmP_EXP_EWSW[23]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_24_ ( .D(n1283), .CK(clk), .RN(n3520), .Q(
DmP_EXP_EWSW[24]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_24_ ( .D(n1282), .CK(clk), .RN(n3513),
.QN(n1885) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_25_ ( .D(n1281), .CK(clk), .RN(n3512), .Q(
DmP_EXP_EWSW[25]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_26_ ( .D(n1279), .CK(clk), .RN(n3530), .Q(
DmP_EXP_EWSW[26]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_27_ ( .D(n1277), .CK(clk), .RN(n3524), .Q(
DmP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_28_ ( .D(n1275), .CK(clk), .RN(n3496), .Q(
DmP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_29_ ( .D(n1273), .CK(clk), .RN(n3496), .Q(
DmP_EXP_EWSW[29]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_29_ ( .D(n1272), .CK(clk), .RN(n3496),
.QN(n1894) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_30_ ( .D(n1271), .CK(clk), .RN(n3496), .Q(
DmP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_31_ ( .D(n1269), .CK(clk), .RN(n3496), .Q(
DmP_EXP_EWSW[31]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_32_ ( .D(n1267), .CK(clk), .RN(n3496), .Q(
DmP_EXP_EWSW[32]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_33_ ( .D(n1265), .CK(clk), .RN(n3496), .Q(
DmP_EXP_EWSW[33]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_34_ ( .D(n1263), .CK(clk), .RN(n3497), .Q(
DmP_EXP_EWSW[34]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_35_ ( .D(n1261), .CK(clk), .RN(n3497), .Q(
DmP_EXP_EWSW[35]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_36_ ( .D(n1259), .CK(clk), .RN(n3497), .Q(
DmP_EXP_EWSW[36]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_36_ ( .D(n1258), .CK(clk), .RN(n3497),
.QN(n1889) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_37_ ( .D(n1257), .CK(clk), .RN(n3497), .Q(
DmP_EXP_EWSW[37]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_38_ ( .D(n1255), .CK(clk), .RN(n3497), .Q(
DmP_EXP_EWSW[38]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_39_ ( .D(n1253), .CK(clk), .RN(n3497), .Q(
DmP_EXP_EWSW[39]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_40_ ( .D(n1251), .CK(clk), .RN(n3498), .Q(
DmP_EXP_EWSW[40]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_40_ ( .D(n1250), .CK(clk), .RN(n3498),
.QN(n1881) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_41_ ( .D(n1249), .CK(clk), .RN(n3498), .Q(
DmP_EXP_EWSW[41]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_42_ ( .D(n1246), .CK(clk), .RN(n3498),
.QN(n1882) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_43_ ( .D(n1245), .CK(clk), .RN(n3498), .Q(
DmP_EXP_EWSW[43]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_44_ ( .D(n1243), .CK(clk), .RN(n3498), .Q(
DmP_EXP_EWSW[44]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_44_ ( .D(n1242), .CK(clk), .RN(n3498),
.QN(n1883) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_45_ ( .D(n1241), .CK(clk), .RN(n3498), .Q(
DmP_EXP_EWSW[45]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_46_ ( .D(n1239), .CK(clk), .RN(n3482), .Q(
DmP_EXP_EWSW[46]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_46_ ( .D(n1238), .CK(clk), .RN(n3486),
.QN(n1890) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_47_ ( .D(n1237), .CK(clk), .RN(n3523), .Q(
DmP_EXP_EWSW[47]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_48_ ( .D(n1235), .CK(clk), .RN(n3509), .Q(
DmP_EXP_EWSW[48]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_48_ ( .D(n1234), .CK(clk), .RN(n3488),
.QN(n1895) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_49_ ( .D(n1233), .CK(clk), .RN(n3516), .Q(
DmP_EXP_EWSW[49]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_50_ ( .D(n1231), .CK(clk), .RN(n3493), .Q(
DmP_EXP_EWSW[50]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_51_ ( .D(n1229), .CK(clk), .RN(n3516), .Q(
DmP_EXP_EWSW[51]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1221), .CK(clk), .RN(n3500), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1220), .CK(clk), .RN(n3495), .Q(
overflow_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n1219), .CK(clk), .RN(n3499), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n1218), .CK(clk), .RN(n3500), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n1217), .CK(clk), .RN(n3495), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n1216), .CK(clk), .RN(n3499), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1215), .CK(clk), .RN(n3500),
.Q(ZERO_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1214), .CK(clk), .RN(n3496), .Q(
zero_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1213), .CK(clk), .RN(n3499), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1212), .CK(clk), .RN(n3500), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1210), .CK(clk), .RN(n3509), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1209), .CK(clk), .RN(n3499), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1208), .CK(clk), .RN(n3500), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1207), .CK(clk), .RN(n3495), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1206), .CK(clk), .RN(n3499),
.Q(SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_63_ ( .D(n1205), .CK(clk), .RN(n3500), .Q(
final_result_ieee[63]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_33_ ( .D(n1185), .CK(clk), .RN(n3502),
.QN(n1855) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_16_ ( .D(n1161), .CK(clk), .RN(n3508),
.Q(LZD_output_NRM2_EW[5]), .QN(n3406) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_15_ ( .D(n1155), .CK(clk), .RN(n3514),
.Q(LZD_output_NRM2_EW[4]), .QN(n3403) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1151), .CK(clk), .RN(n3508),
.Q(LZD_output_NRM2_EW[1]), .QN(n3371) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_14_ ( .D(n1148), .CK(clk), .RN(n3508),
.Q(LZD_output_NRM2_EW[3]), .QN(n3394) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1141), .CK(clk), .RN(n3472), .QN(
n1875) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_13_ ( .D(n1137), .CK(clk), .RN(n3514),
.Q(LZD_output_NRM2_EW[2]), .QN(n3395) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1134), .CK(clk), .RN(n3476), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_42_ ( .D(n1133), .CK(clk), .RN(n3475), .Q(
final_result_ieee[42]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1128), .CK(clk), .RN(n3497), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n1127), .CK(clk), .RN(n3476), .Q(
final_result_ieee[30]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n1126), .CK(clk), .RN(n3475), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_36_ ( .D(n1125), .CK(clk), .RN(n3503), .Q(
final_result_ieee[36]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1124), .CK(clk), .RN(n3473), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1123), .CK(clk), .RN(n3505), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n1121), .CK(clk), .RN(n3503), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_40_ ( .D(n1120), .CK(clk), .RN(n3472), .Q(
final_result_ieee[40]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n1119), .CK(clk), .RN(n3474), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1118), .CK(clk), .RN(n3506), .Q(
final_result_ieee[22]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1117), .CK(clk), .RN(n3472), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_38_ ( .D(n1116), .CK(clk), .RN(n3472), .Q(
final_result_ieee[38]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1115), .CK(clk), .RN(n3505), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1114), .CK(clk), .RN(n3505), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_41_ ( .D(n1113), .CK(clk), .RN(n3507), .Q(
final_result_ieee[41]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1112), .CK(clk), .RN(n3471), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_44_ ( .D(n1111), .CK(clk), .RN(n3469), .Q(
final_result_ieee[44]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1110), .CK(clk), .RN(n3507), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1109), .CK(clk), .RN(n3471), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1108), .CK(clk), .RN(n3469), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1107), .CK(clk), .RN(n3507), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_39_ ( .D(n1106), .CK(clk), .RN(n3471), .Q(
final_result_ieee[39]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_43_ ( .D(n1105), .CK(clk), .RN(n3469), .Q(
final_result_ieee[43]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1104), .CK(clk), .RN(n3507), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_46_ ( .D(n1103), .CK(clk), .RN(n3471), .Q(
final_result_ieee[46]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n1102), .CK(clk), .RN(n3469), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_32_ ( .D(n1101), .CK(clk), .RN(n3514), .Q(
final_result_ieee[32]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n1100), .CK(clk), .RN(n3508), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_34_ ( .D(n1099), .CK(clk), .RN(n3530), .Q(
final_result_ieee[34]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1098), .CK(clk), .RN(n3514), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1097), .CK(clk), .RN(n3508), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1096), .CK(clk), .RN(n3530), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n1095), .CK(clk), .RN(n3514), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_37_ ( .D(n1094), .CK(clk), .RN(n3508), .Q(
final_result_ieee[37]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_45_ ( .D(n1093), .CK(clk), .RN(n3530), .Q(
final_result_ieee[45]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n1092), .CK(clk), .RN(n3514), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_33_ ( .D(n1091), .CK(clk), .RN(n3508), .Q(
final_result_ieee[33]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1090), .CK(clk), .RN(n3514), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_48_ ( .D(n1089), .CK(clk), .RN(n3509), .Q(
final_result_ieee[48]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1088), .CK(clk), .RN(n3509), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n1087), .CK(clk), .RN(n3509), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n1086), .CK(clk), .RN(n3509), .Q(
final_result_ieee[31]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n1085), .CK(clk), .RN(n3509), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_35_ ( .D(n1084), .CK(clk), .RN(n3509), .Q(
final_result_ieee[35]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_47_ ( .D(n1083), .CK(clk), .RN(n3509), .Q(
final_result_ieee[47]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1082), .CK(clk), .RN(n3509), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1081), .CK(clk), .RN(n3509), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_49_ ( .D(n1080), .CK(clk), .RN(n3509), .Q(
final_result_ieee[49]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_50_ ( .D(n1079), .CK(clk), .RN(n3509), .Q(
final_result_ieee[50]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_51_ ( .D(n1078), .CK(clk), .RN(n3509), .Q(
final_result_ieee[51]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1075), .CK(clk), .RN(n3513), .Q(
DmP_mant_SFG_SWR[16]), .QN(n1989) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1074), .CK(clk), .RN(n3512), .Q(
DmP_mant_SFG_SWR[17]), .QN(n1990) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1073), .CK(clk), .RN(n3511), .Q(
DmP_mant_SFG_SWR[18]), .QN(n1992) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1072), .CK(clk), .RN(n3510), .Q(
DmP_mant_SFG_SWR[19]), .QN(n1993) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1071), .CK(clk), .RN(n3521), .Q(
DmP_mant_SFG_SWR[20]), .QN(n1994) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1070), .CK(clk), .RN(n3484), .Q(
DmP_mant_SFG_SWR[21]), .QN(n1971) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_32_ ( .D(n1059), .CK(clk), .RN(n3521), .Q(
DmP_mant_SFG_SWR[32]), .QN(n1973) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_33_ ( .D(n1058), .CK(clk), .RN(n3484), .Q(
DmP_mant_SFG_SWR[33]), .QN(n1974) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_34_ ( .D(n1057), .CK(clk), .RN(n3513), .Q(
DmP_mant_SFG_SWR[34]), .QN(n1975) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_35_ ( .D(n1056), .CK(clk), .RN(n3512), .Q(
DmP_mant_SFG_SWR[35]), .QN(n1976) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_36_ ( .D(n1055), .CK(clk), .RN(n3511), .Q(
DmP_mant_SFG_SWR[36]), .QN(n1977) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_38_ ( .D(n1053), .CK(clk), .RN(n3512), .Q(
DmP_mant_SFG_SWR[38]), .QN(n1981) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_43_ ( .D(n1048), .CK(clk), .RN(n3521),
.QN(n1856) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_44_ ( .D(n1047), .CK(clk), .RN(n3484),
.QN(n1859) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_46_ ( .D(n1045), .CK(clk), .RN(n3510),
.QN(n1864) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_47_ ( .D(n1044), .CK(clk), .RN(n3484),
.QN(n1866) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_48_ ( .D(n1043), .CK(clk), .RN(n3510),
.QN(n1867) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_49_ ( .D(n1042), .CK(clk), .RN(n3513),
.QN(n1868) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_50_ ( .D(n1041), .CK(clk), .RN(n3510),
.QN(n1870) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_51_ ( .D(n1040), .CK(clk), .RN(n3521),
.QN(n1871) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_52_ ( .D(n1039), .CK(clk), .RN(n3484),
.QN(n1876) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_53_ ( .D(n1038), .CK(clk), .RN(n3513),
.QN(n1877) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_54_ ( .D(n1037), .CK(clk), .RN(n3512),
.QN(n1886) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_55_ ( .D(n1760), .CK(clk), .RN(n3473),
.Q(intDX_EWSW[55]), .QN(n3465) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_53_ ( .D(n1762), .CK(clk), .RN(n3506),
.Q(intDX_EWSW[53]), .QN(n3464) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1135), .CK(clk), .RN(n3475), .Q(
Raw_mant_NRM_SWR[10]), .QN(n3460) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_26_ ( .D(n1192), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[26]), .QN(n3454) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n1742), .CK(clk), .RN(n3530),
.Q(intDY_EWSW[7]), .QN(n3453) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n1719), .CK(clk), .RN(n3514),
.Q(intDY_EWSW[30]), .QN(n3452) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n1748), .CK(clk), .RN(n3511),
.Q(intDY_EWSW[1]), .QN(n3449) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_44_ ( .D(n1705), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[44]), .QN(n3445) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_36_ ( .D(n1713), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[36]), .QN(n3442) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_34_ ( .D(n1715), .CK(clk), .RN(n3476),
.Q(intDY_EWSW[34]), .QN(n3441) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_38_ ( .D(n1711), .CK(clk), .RN(n3497),
.Q(intDY_EWSW[38]), .QN(n3440) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_39_ ( .D(n1710), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[39]), .QN(n3438) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_37_ ( .D(n1712), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[37]), .QN(n3437) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n1814), .CK(clk), .RN(n3507),
.Q(intDX_EWSW[1]), .QN(n3433) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_61_ ( .D(n1688), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[61]), .QN(n3432) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_54_ ( .D(n1685), .CK(clk), .RN(n3517), .Q(
Data_array_SWR[34]), .QN(n3429) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_53_ ( .D(n1684), .CK(clk), .RN(n3477), .Q(
Data_array_SWR[33]), .QN(n3428) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_51_ ( .D(n1682), .CK(clk), .RN(n3477), .Q(
Data_array_SWR[32]), .QN(n3427) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n1733), .CK(clk), .RN(n3488),
.Q(intDY_EWSW[16]), .QN(n3425) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_48_ ( .D(n1701), .CK(clk), .RN(n3479),
.Q(intDY_EWSW[48]), .QN(n3422) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_32_ ( .D(n1717), .CK(clk), .RN(n3522),
.Q(intDY_EWSW[32]), .QN(n3421) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n1721), .CK(clk), .RN(n3485),
.Q(intDY_EWSW[28]), .QN(n3420) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n1745), .CK(clk), .RN(n3488),
.Q(intDY_EWSW[4]), .QN(n3413) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n1728), .CK(clk), .RN(n3508),
.Q(intDY_EWSW[21]), .QN(n3411) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n1736), .CK(clk), .RN(n3530),
.Q(intDY_EWSW[13]), .QN(n3410) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n1739), .CK(clk), .RN(n3517),
.Q(intDY_EWSW[10]), .QN(n3408) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_59_ ( .D(n1756), .CK(clk), .RN(n3503),
.Q(intDX_EWSW[59]), .QN(n3404) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n1797), .CK(clk), .RN(n3507),
.Q(intDX_EWSW[18]), .QN(n3402) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n1789), .CK(clk), .RN(n3506),
.Q(intDX_EWSW[26]), .QN(n3401) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n1794), .CK(clk), .RN(n3469),
.Q(intDX_EWSW[21]), .QN(n3400) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1200), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[18]), .QN(n3399) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1199), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[19]), .QN(n3398) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_51_ ( .D(n1764), .CK(clk), .RN(n3472),
.Q(intDX_EWSW[51]), .QN(n3397) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_35_ ( .D(n1183), .CK(clk), .RN(n3530), .Q(
Raw_mant_NRM_SWR[35]), .QN(n3396) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_57_ ( .D(n1758), .CK(clk), .RN(n3503),
.Q(intDX_EWSW[57]), .QN(n3393) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n1807), .CK(clk), .RN(n3507),
.Q(intDX_EWSW[8]), .QN(n3392) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_49_ ( .D(n1766), .CK(clk), .RN(n3473),
.Q(intDX_EWSW[49]), .QN(n3391) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n1798), .CK(clk), .RN(n3469),
.Q(intDX_EWSW[17]), .QN(n3390) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n1790), .CK(clk), .RN(n3507),
.Q(intDX_EWSW[25]), .QN(n3389) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_45_ ( .D(n1770), .CK(clk), .RN(n3506),
.Q(intDX_EWSW[45]), .QN(n3388) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n1629), .CK(clk), .RN(n3479),
.Q(shift_value_SHT2_EWR[3]), .QN(n3386) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n1802), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[13]), .QN(n3384) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n1786), .CK(clk), .RN(n3503),
.Q(intDX_EWSW[29]), .QN(n3383) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_41_ ( .D(n1774), .CK(clk), .RN(n3503),
.Q(intDX_EWSW[41]), .QN(n3382) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_36_ ( .D(n1779), .CK(clk), .RN(n3506),
.Q(intDX_EWSW[36]), .QN(n3381) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n1793), .CK(clk), .RN(n3507),
.Q(intDX_EWSW[22]), .QN(n3380) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n1785), .CK(clk), .RN(n3472),
.Q(intDX_EWSW[30]), .QN(n3379) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n1795), .CK(clk), .RN(n3471),
.Q(intDX_EWSW[20]), .QN(n3378) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n1787), .CK(clk), .RN(n3472),
.Q(intDX_EWSW[28]), .QN(n3377) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_34_ ( .D(n1781), .CK(clk), .RN(n3503),
.Q(intDX_EWSW[34]), .QN(n3375) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_42_ ( .D(n1773), .CK(clk), .RN(n3503),
.Q(intDX_EWSW[42]), .QN(n3374) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_33_ ( .D(n1782), .CK(clk), .RN(n3472),
.Q(intDX_EWSW[33]), .QN(n3373) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n1812), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[3]), .QN(n3372) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n1804), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[11]), .QN(n3369) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n1801), .CK(clk), .RN(n3471),
.Q(intDX_EWSW[14]), .QN(n3368) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n1803), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[12]), .QN(n3367) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_46_ ( .D(n1769), .CK(clk), .RN(n3474),
.Q(intDX_EWSW[46]), .QN(n3366) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n1628), .CK(clk), .RN(n3501),
.Q(shift_value_SHT2_EWR[4]), .QN(n3363) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_27_ ( .D(n1191), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[27]), .QN(n3362) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_54_ ( .D(n1761), .CK(clk), .RN(n3472),
.Q(intDX_EWSW[54]), .QN(n3358) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n1718), .CK(clk), .RN(n3485),
.Q(intDY_EWSW[31]), .QN(n3348) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n1734), .CK(clk), .RN(n3486),
.Q(intDY_EWSW[15]), .QN(n3346) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_35_ ( .D(n1714), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[35]), .QN(n3342) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_33_ ( .D(n1716), .CK(clk), .RN(n3476),
.Q(intDY_EWSW[33]), .QN(n3341) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n1720), .CK(clk), .RN(n3522),
.Q(intDY_EWSW[29]), .QN(n3339) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n1744), .CK(clk), .RN(n3519),
.Q(intDY_EWSW[5]), .QN(n3334) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n3471), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n3332) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1146), .CK(clk), .RN(n3472), .Q(
Raw_mant_NRM_SWR[7]), .QN(n3330) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1153), .CK(clk), .RN(n3504), .Q(
Raw_mant_NRM_SWR[2]), .QN(n3328) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n1796), .CK(clk), .RN(n3507),
.Q(intDX_EWSW[19]), .QN(n3325) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n1788), .CK(clk), .RN(n3473),
.Q(intDX_EWSW[27]), .QN(n3324) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_50_ ( .D(n1765), .CK(clk), .RN(n3505),
.Q(intDX_EWSW[50]), .QN(n3322) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n1792), .CK(clk), .RN(n3469),
.Q(intDX_EWSW[23]), .QN(n3321) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n1784), .CK(clk), .RN(n3503),
.Q(intDX_EWSW[31]), .QN(n3320) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_35_ ( .D(n1780), .CK(clk), .RN(n3506),
.Q(intDX_EWSW[35]), .QN(n3319) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_43_ ( .D(n1772), .CK(clk), .RN(n3506),
.Q(intDX_EWSW[43]), .QN(n3318) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1142), .CK(clk), .RN(n3505), .Q(
Raw_mant_NRM_SWR[9]), .QN(n3317) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n1800), .CK(clk), .RN(n3471),
.Q(intDX_EWSW[15]), .QN(n3316) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_56_ ( .D(n1759), .CK(clk), .RN(n3505),
.Q(intDX_EWSW[56]), .QN(n3314) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1131), .CK(clk), .RN(n3476), .Q(
Raw_mant_NRM_SWR[8]), .QN(n3311) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_40_ ( .D(n1178), .CK(clk), .RN(n3472), .Q(
Raw_mant_NRM_SWR[40]), .QN(n3364) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_42_ ( .D(n1176), .CK(clk), .RN(n3506), .Q(
Raw_mant_NRM_SWR[42]), .QN(n3365) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1144), .CK(clk), .RN(n3505), .Q(
Raw_mant_NRM_SWR[4]), .QN(n3323) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_62_ ( .D(n1687), .CK(clk), .RN(n3522),
.Q(intDY_EWSW[62]), .QN(n3448) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_45_ ( .D(n1704), .CK(clk), .RN(n3476),
.Q(intDY_EWSW[45]), .QN(n3439) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n1726), .CK(clk), .RN(n3508),
.Q(intDY_EWSW[23]), .QN(n3347) );
DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_5_ ( .D(n1626), .CK(clk), .RN(n3492),
.Q(shift_value_SHT2_EWR[5]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1198), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n1810), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[5]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_47_ ( .D(n1171), .CK(clk), .RN(n3473), .Q(
Raw_mant_NRM_SWR[47]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1195), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[23]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_29_ ( .D(n1189), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[29]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1194), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[24]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1159), .CK(clk), .RN(n3492), .Q(
Raw_mant_NRM_SWR[1]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n1652), .CK(clk), .RN(n3478), .Q(
Data_array_SWR[11]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_26_ ( .D(n1657), .CK(clk), .RN(n3478), .Q(
Data_array_SWR[15]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1152), .CK(clk), .RN(n3474), .Q(
Raw_mant_NRM_SWR[3]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n1655), .CK(clk), .RN(n3478), .Q(
Data_array_SWR[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_38_ ( .D(n1777), .CK(clk), .RN(n3505),
.Q(intDX_EWSW[38]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_29_ ( .D(n1660), .CK(clk), .RN(n3478), .Q(
Data_array_SWR[17]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_44_ ( .D(n1771), .CK(clk), .RN(n3473),
.Q(intDX_EWSW[44]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_47_ ( .D(n1768), .CK(clk), .RN(n3474),
.Q(intDX_EWSW[47]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_39_ ( .D(n1179), .CK(clk), .RN(n3472), .Q(
Raw_mant_NRM_SWR[39]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_37_ ( .D(n1778), .CK(clk), .RN(n3505),
.Q(intDX_EWSW[37]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_52_ ( .D(n1763), .CK(clk), .RN(n3473),
.Q(intDX_EWSW[52]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_40_ ( .D(n1775), .CK(clk), .RN(n3474),
.Q(intDX_EWSW[40]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_48_ ( .D(n1767), .CK(clk), .RN(n3474),
.Q(intDX_EWSW[48]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n1805), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[10]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_32_ ( .D(n1186), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[32]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_45_ ( .D(n1173), .CK(clk), .RN(n3506), .Q(
Raw_mant_NRM_SWR[45]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n1808), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[7]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n1799), .CK(clk), .RN(n3507),
.Q(intDX_EWSW[16]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_32_ ( .D(n1783), .CK(clk), .RN(n3505),
.Q(intDX_EWSW[32]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n1813), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n1791), .CK(clk), .RN(n3507),
.Q(intDX_EWSW[24]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_36_ ( .D(n1182), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[36]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1202), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[16]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_28_ ( .D(n1190), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[28]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_43_ ( .D(n1175), .CK(clk), .RN(n3473), .Q(
Raw_mant_NRM_SWR[43]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1203), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[15]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n1654), .CK(clk), .RN(n3478), .Q(
Data_array_SWR[12]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1149), .CK(clk), .RN(n3503), .Q(
Raw_mant_NRM_SWR[5]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1140), .CK(clk), .RN(n3506), .Q(
Raw_mant_NRM_SWR[6]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_38_ ( .D(n1180), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[38]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_49_ ( .D(n1169), .CK(clk), .RN(n3503), .Q(
Raw_mant_NRM_SWR[49]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1201), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_39_ ( .D(n1670), .CK(clk), .RN(n3496), .Q(
Data_array_SWR[21]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n1815), .CK(clk), .RN(n3471),
.Q(intDX_EWSW[0]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_62_ ( .D(n1753), .CK(clk), .RN(n3520),
.Q(intDX_EWSW[62]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_61_ ( .D(n1754), .CK(clk), .RN(n3503),
.Q(intDX_EWSW[61]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_52_ ( .D(n1166), .CK(clk), .RN(n3480), .Q(
Raw_mant_NRM_SWR[52]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n1824), .CK(clk), .RN(
n3469), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1193), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[25]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_41_ ( .D(n1177), .CK(clk), .RN(n3506), .Q(
Raw_mant_NRM_SWR[41]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1197), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[21]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_47_ ( .D(n1678), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[28]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_49_ ( .D(n1680), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[30]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_41_ ( .D(n1672), .CK(clk), .RN(n3519), .Q(
Data_array_SWR[23]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_40_ ( .D(n1671), .CK(clk), .RN(n3525), .Q(
Data_array_SWR[22]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_42_ ( .D(n1673), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[24]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n1630), .CK(clk), .RN(n3509),
.Q(shift_value_SHT2_EWR[2]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_30_ ( .D(n1188), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[30]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_37_ ( .D(n1181), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[37]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_10_ ( .D(n1510), .CK(clk), .RN(n3483), .Q(
DMP_SFG[10]) );
DFFSX4TS inst_ShiftRegister_Q_reg_5_ ( .D(n1978), .CK(clk), .SN(n3469), .Q(
n3463), .QN(n3528) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n1513), .CK(clk), .RN(n3483), .Q(
DMP_SFG[9]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n1537), .CK(clk), .RN(n3524), .Q(
DMP_SFG[1]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_32_ ( .D(n1266), .CK(clk), .RN(n3496),
.Q(DmP_mant_SHT1_SW[32]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_23_ ( .D(n1284), .CK(clk), .RN(n3481),
.Q(DmP_mant_SHT1_SW[23]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1302), .CK(clk), .RN(n3494),
.Q(DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1310), .CK(clk), .RN(n3494),
.Q(DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_35_ ( .D(n1260), .CK(clk), .RN(n3497),
.Q(DmP_mant_SHT1_SW[35]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_30_ ( .D(n1270), .CK(clk), .RN(n3496),
.Q(DmP_mant_SHT1_SW[30]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_28_ ( .D(n1274), .CK(clk), .RN(n3496),
.Q(DmP_mant_SHT1_SW[28]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_26_ ( .D(n1278), .CK(clk), .RN(n3518),
.Q(DmP_mant_SHT1_SW[26]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1296), .CK(clk), .RN(n3495),
.Q(DmP_mant_SHT1_SW[17]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_63_ ( .D(n1752), .CK(clk), .RN(n3520),
.Q(intDX_EWSW[63]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_11_ ( .D(n1507), .CK(clk), .RN(n3483), .Q(
DMP_SFG[11]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n1519), .CK(clk), .RN(n3493), .Q(
DMP_SFG[7]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n1525), .CK(clk), .RN(n3504), .Q(
DMP_SFG[5]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n1723), .CK(clk), .RN(n3514),
.Q(intDY_EWSW[26]), .QN(n3419) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1147), .CK(clk), .RN(n3503), .Q(
DmP_mant_SFG_SWR[5]) );
DFFSX4TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1873), .CK(clk), .SN(n3499), .Q(
n3467), .QN(n3526) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1290), .CK(clk), .RN(n3495),
.Q(DmP_mant_SHT1_SW[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_38_ ( .D(n1254), .CK(clk), .RN(n3497),
.Q(DmP_mant_SHT1_SW[38]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_33_ ( .D(n1264), .CK(clk), .RN(n3496),
.Q(DmP_mant_SHT1_SW[33]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_31_ ( .D(n1268), .CK(clk), .RN(n3496),
.Q(DmP_mant_SHT1_SW[31]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_27_ ( .D(n1276), .CK(clk), .RN(n3499),
.Q(DmP_mant_SHT1_SW[27]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1286), .CK(clk), .RN(n3474),
.Q(DmP_mant_SHT1_SW[22]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1294), .CK(clk), .RN(n3495),
.Q(DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1308), .CK(clk), .RN(n3494),
.Q(DmP_mant_SHT1_SW[11]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n1516), .CK(clk), .RN(n3515), .Q(
DMP_SFG[8]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_52_ ( .D(n1227), .CK(clk), .RN(n3499), .Q(
DmP_EXP_EWSW[52]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1298), .CK(clk), .RN(n3495),
.Q(DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_34_ ( .D(n1262), .CK(clk), .RN(n3497),
.Q(DmP_mant_SHT1_SW[34]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_25_ ( .D(n1280), .CK(clk), .RN(n3518),
.Q(DmP_mant_SHT1_SW[25]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1304), .CK(clk), .RN(n3494),
.Q(DmP_mant_SHT1_SW[13]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1312), .CK(clk), .RN(n3517), .Q(
DmP_mant_SHT1_SW[9]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1318), .CK(clk), .RN(n3484), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1324), .CK(clk), .RN(n3517), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n1638), .CK(clk), .RN(n3494), .Q(
Data_array_SWR[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1326), .CK(clk), .RN(n3519), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1314), .CK(clk), .RN(n3521), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n1635), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n1636), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[5]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n1637), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[6]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_57_ ( .D(n1551), .CK(clk), .RN(n3481), .Q(
DMP_EXP_EWSW[57]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1328), .CK(clk), .RN(n3490), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_31_ ( .D(n1060), .CK(clk), .RN(n3510), .Q(
DmP_mant_SFG_SWR[31]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_30_ ( .D(n1061), .CK(clk), .RN(n3513), .Q(
DmP_mant_SFG_SWR[30]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_29_ ( .D(n1062), .CK(clk), .RN(n3512), .Q(
DmP_mant_SFG_SWR[29]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_28_ ( .D(n1063), .CK(clk), .RN(n3511), .Q(
DmP_mant_SFG_SWR[28]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_27_ ( .D(n1064), .CK(clk), .RN(n3521), .Q(
DmP_mant_SFG_SWR[27]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_26_ ( .D(n1065), .CK(clk), .RN(n3484), .Q(
DmP_mant_SFG_SWR[26]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1066), .CK(clk), .RN(n3510), .Q(
DmP_mant_SFG_SWR[25]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1067), .CK(clk), .RN(n3513), .Q(
DmP_mant_SFG_SWR[24]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1068), .CK(clk), .RN(n3512), .Q(
DmP_mant_SFG_SWR[23]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n1540), .CK(clk), .RN(n3479), .Q(
DMP_SFG[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1132), .CK(clk), .RN(n3476), .Q(
DmP_mant_SFG_SWR[8]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1139), .CK(clk), .RN(n3506), .Q(
DmP_mant_SFG_SWR[9]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1143), .CK(clk), .RN(n3473), .Q(
DmP_mant_SFG_SWR[7]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1145), .CK(clk), .RN(n3506), .Q(
DmP_mant_SFG_SWR[4]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1150), .CK(clk), .RN(n3474), .Q(
DmP_mant_SFG_SWR[3]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1154), .CK(clk), .RN(n3515), .Q(
DmP_mant_SFG_SWR[2]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_45_ ( .D(n1046), .CK(clk), .RN(n3511), .Q(
DmP_mant_SFG_SWR[45]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1157), .CK(clk), .RN(n3493), .Q(
DmP_mant_SFG_SWR[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1160), .CK(clk), .RN(n3504), .Q(
DmP_mant_SFG_SWR[1]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_27_ ( .D(n1658), .CK(clk), .RN(n3478), .Q(
Data_array_SWR[16]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_51_ ( .D(n1167), .CK(clk), .RN(n3518), .Q(
Raw_mant_NRM_SWR[51]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_51_ ( .D(n1387), .CK(clk), .RN(n3520), .Q(
DMP_SFG[51]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_50_ ( .D(n1390), .CK(clk), .RN(n3520), .Q(
DMP_SFG[50]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_49_ ( .D(n1393), .CK(clk), .RN(n3520), .Q(
DMP_SFG[49]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_48_ ( .D(n1396), .CK(clk), .RN(n3491), .Q(
DMP_SFG[48]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_47_ ( .D(n1399), .CK(clk), .RN(n3523), .Q(
DMP_SFG[47]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_46_ ( .D(n1402), .CK(clk), .RN(n3491), .Q(
DMP_SFG[46]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_45_ ( .D(n1405), .CK(clk), .RN(n3523), .Q(
DMP_SFG[45]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_44_ ( .D(n1408), .CK(clk), .RN(n3490), .Q(
DMP_SFG[44]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_43_ ( .D(n1411), .CK(clk), .RN(n3490), .Q(
DMP_SFG[43]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_42_ ( .D(n1414), .CK(clk), .RN(n3490), .Q(
DMP_SFG[42]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_41_ ( .D(n1417), .CK(clk), .RN(n3490), .Q(
DMP_SFG[41]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_40_ ( .D(n1420), .CK(clk), .RN(n3489), .Q(
DMP_SFG[40]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_39_ ( .D(n1423), .CK(clk), .RN(n3489), .Q(
DMP_SFG[39]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_24_ ( .D(n1468), .CK(clk), .RN(n3486), .Q(
DMP_SFG[24]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_23_ ( .D(n1471), .CK(clk), .RN(n3485), .Q(
DMP_SFG[23]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_22_ ( .D(n1474), .CK(clk), .RN(n3522), .Q(
DMP_SFG[22]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_21_ ( .D(n1477), .CK(clk), .RN(n3486), .Q(
DMP_SFG[21]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_20_ ( .D(n1480), .CK(clk), .RN(n3489), .Q(
DMP_SFG[20]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_19_ ( .D(n1483), .CK(clk), .RN(n3490), .Q(
DMP_SFG[19]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_18_ ( .D(n1486), .CK(clk), .RN(n3523), .Q(
DMP_SFG[18]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_17_ ( .D(n1489), .CK(clk), .RN(n3484), .Q(
DMP_SFG[17]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_16_ ( .D(n1492), .CK(clk), .RN(n3511), .Q(
DMP_SFG[16]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_15_ ( .D(n1495), .CK(clk), .RN(n3521), .Q(
DMP_SFG[15]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_14_ ( .D(n1498), .CK(clk), .RN(n3484), .Q(
DMP_SFG[14]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_13_ ( .D(n1501), .CK(clk), .RN(n3510), .Q(
DMP_SFG[13]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_12_ ( .D(n1504), .CK(clk), .RN(n3483), .Q(
DMP_SFG[12]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n1632), .CK(clk), .RN(n3491), .Q(
Data_array_SWR[1]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n1633), .CK(clk), .RN(n3525), .Q(
Data_array_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n1631), .CK(clk), .RN(n3485), .Q(
Data_array_SWR[0]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_34_ ( .D(n1184), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[34]), .QN(n1887) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n1731), .CK(clk), .RN(n3491),
.Q(intDY_EWSW[18]), .QN(n3416) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n1730), .CK(clk), .RN(n3530),
.Q(intDY_EWSW[19]), .QN(n3336) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_48_ ( .D(n1170), .CK(clk), .RN(n3474), .Q(
Raw_mant_NRM_SWR[48]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n1811), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[4]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_39_ ( .D(n1776), .CK(clk), .RN(n3474),
.Q(intDX_EWSW[39]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n1806), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[9]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_31_ ( .D(n1187), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[31]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1204), .CK(clk), .RN(n3500), .Q(
Raw_mant_NRM_SWR[14]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n1648), .CK(clk), .RN(n3477), .Q(
Data_array_SWR[9]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n1647), .CK(clk), .RN(n3523), .Q(
Data_array_SWR[8]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n1650), .CK(clk), .RN(n3478), .Q(
Data_array_SWR[10]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_53_ ( .D(n1165), .CK(clk), .RN(n3482), .Q(
Raw_mant_NRM_SWR[53]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n1809), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[6]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1196), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[22]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_44_ ( .D(n1675), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[26]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_46_ ( .D(n1677), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[27]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_43_ ( .D(n1674), .CK(clk), .RN(n3488), .Q(
Data_array_SWR[25]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_50_ ( .D(n1681), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[31]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_48_ ( .D(n1679), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[29]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_54_ ( .D(n1164), .CK(clk), .RN(n3492), .Q(
Raw_mant_NRM_SWR[54]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_44_ ( .D(n1174), .CK(clk), .RN(n3472), .Q(
Raw_mant_NRM_SWR[44]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_41_ ( .D(n1248), .CK(clk), .RN(n3498),
.Q(DmP_mant_SHT1_SW[41]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_43_ ( .D(n1244), .CK(clk), .RN(n3498),
.Q(DmP_mant_SHT1_SW[43]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_45_ ( .D(n1240), .CK(clk), .RN(n3498),
.Q(DmP_mant_SHT1_SW[45]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_49_ ( .D(n1232), .CK(clk), .RN(n3519),
.Q(DmP_mant_SHT1_SW[49]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_47_ ( .D(n1236), .CK(clk), .RN(n3520),
.Q(DmP_mant_SHT1_SW[47]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_37_ ( .D(n1256), .CK(clk), .RN(n3497),
.Q(DmP_mant_SHT1_SW[37]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_39_ ( .D(n1252), .CK(clk), .RN(n3497),
.Q(DmP_mant_SHT1_SW[39]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_3_ ( .D(n1531), .CK(clk), .RN(n3481), .Q(
DMP_SFG[3]), .QN(n3461) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_51_ ( .D(n1228), .CK(clk), .RN(n3487),
.Q(DmP_mant_SHT1_SW[51]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_50_ ( .D(n1230), .CK(clk), .RN(n3516),
.Q(DmP_mant_SHT1_SW[50]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1136), .CK(clk), .RN(n3475), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1130), .CK(clk), .RN(n3498), .Q(
DmP_mant_SFG_SWR[11]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1122), .CK(clk), .RN(n3506), .Q(
DmP_mant_SFG_SWR[12]), .QN(n1986) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n1741), .CK(clk), .RN(n3530),
.Q(intDY_EWSW[8]), .QN(n3414) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1377), .CK(clk), .RN(n3514), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1372), .CK(clk), .RN(n3493), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1367), .CK(clk), .RN(n3504), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1362), .CK(clk), .RN(n3515), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1357), .CK(clk), .RN(n3482), .Q(
DMP_exp_NRM2_EW[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_25_ ( .D(n1465), .CK(clk), .RN(n3522), .Q(
DMP_SFG[25]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_26_ ( .D(n1462), .CK(clk), .RN(n3522), .Q(
DMP_SFG[26]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_27_ ( .D(n1459), .CK(clk), .RN(n3522), .Q(
DMP_SFG[27]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_28_ ( .D(n1456), .CK(clk), .RN(n3522), .Q(
DMP_SFG[28]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_29_ ( .D(n1453), .CK(clk), .RN(n3487), .Q(
DMP_SFG[29]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_30_ ( .D(n1450), .CK(clk), .RN(n3487), .Q(
DMP_SFG[30]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_31_ ( .D(n1447), .CK(clk), .RN(n3487), .Q(
DMP_SFG[31]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_32_ ( .D(n1444), .CK(clk), .RN(n3487), .Q(
DMP_SFG[32]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_33_ ( .D(n1441), .CK(clk), .RN(n3487), .Q(
DMP_SFG[33]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_34_ ( .D(n1438), .CK(clk), .RN(n3487), .Q(
DMP_SFG[34]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_35_ ( .D(n1435), .CK(clk), .RN(n3487), .Q(
DMP_SFG[35]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_36_ ( .D(n1432), .CK(clk), .RN(n3487), .Q(
DMP_SFG[36]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_37_ ( .D(n1429), .CK(clk), .RN(n3489), .Q(
DMP_SFG[37]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_38_ ( .D(n1426), .CK(clk), .RN(n3489), .Q(
DMP_SFG[38]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_57_ ( .D(n1222), .CK(clk), .RN(n3499), .Q(
DmP_EXP_EWSW[57]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_63_ ( .D(n1686), .CK(clk), .RN(n3525),
.Q(intDY_EWSW[63]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1077), .CK(clk), .RN(n3521), .Q(
DmP_mant_SFG_SWR[14]), .QN(n1987) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_40_ ( .D(n1051), .CK(clk), .RN(n3512), .Q(
DmP_mant_SFG_SWR[40]), .QN(n1983) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_41_ ( .D(n1050), .CK(clk), .RN(n3511), .Q(
DmP_mant_SFG_SWR[41]), .QN(n1984) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1076), .CK(clk), .RN(n3484), .Q(
DmP_mant_SFG_SWR[15]), .QN(n1988) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1069), .CK(clk), .RN(n3511), .Q(
DmP_mant_SFG_SWR[22]), .QN(n1972) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_37_ ( .D(n1054), .CK(clk), .RN(n3510), .Q(
DmP_mant_SFG_SWR[37]), .QN(n1979) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_39_ ( .D(n1052), .CK(clk), .RN(n3513), .Q(
DmP_mant_SFG_SWR[39]), .QN(n1982) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_42_ ( .D(n1049), .CK(clk), .RN(n3521), .Q(
DmP_mant_SFG_SWR[42]), .QN(n1985) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1158), .CK(clk), .RN(n3508),
.Q(LZD_output_NRM2_EW[0]), .QN(n1995) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_46_ ( .D(n1172), .CK(clk), .RN(n3505), .Q(
Raw_mant_NRM_SWR[46]), .QN(n3376) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1332), .CK(clk), .RN(n3482),
.Q(DMP_exp_NRM2_EW[10]), .QN(n3459) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1337), .CK(clk), .RN(n3492), .Q(
DMP_exp_NRM2_EW[9]), .QN(n3435) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1342), .CK(clk), .RN(n3480), .Q(
DMP_exp_NRM2_EW[8]), .QN(n3436) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1352), .CK(clk), .RN(n3493), .Q(
DMP_exp_NRM2_EW[6]), .QN(n3405) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1382), .CK(clk), .RN(n3530), .Q(
DMP_exp_NRM2_EW[0]), .QN(n3370) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1156), .CK(clk), .RN(n3515), .Q(
Raw_mant_NRM_SWR[0]), .QN(n3329) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1138), .CK(clk), .RN(n3525), .Q(
Raw_mant_NRM_SWR[11]), .QN(n3308) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1129), .CK(clk), .RN(n3476), .Q(
Raw_mant_NRM_SWR[12]), .QN(n3327) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1162), .CK(clk), .RN(n3482), .Q(
Raw_mant_NRM_SWR[13]), .QN(n3315) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n1823), .CK(clk), .RN(
n3507), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n3431) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_52_ ( .D(n1556), .CK(clk), .RN(n3524), .Q(
DMP_EXP_EWSW[52]), .QN(n3458) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_60_ ( .D(n1755), .CK(clk), .RN(n3505),
.Q(intDX_EWSW[60]), .QN(n3385) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_58_ ( .D(n1757), .CK(clk), .RN(n3505),
.Q(intDX_EWSW[58]), .QN(n3326) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_58_ ( .D(n1691), .CK(clk), .RN(n3499),
.Q(intDY_EWSW[58]), .QN(n3424) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_57_ ( .D(n1692), .CK(clk), .RN(n3501),
.Q(intDY_EWSW[57]), .QN(n3409) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_40_ ( .D(n1709), .CK(clk), .RN(n3476),
.Q(intDY_EWSW[40]), .QN(n3443) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_55_ ( .D(n1694), .CK(clk), .RN(n3479),
.Q(intDY_EWSW[55]), .QN(n3309) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_53_ ( .D(n1696), .CK(clk), .RN(n3476),
.Q(intDY_EWSW[53]), .QN(n3313) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_56_ ( .D(n1693), .CK(clk), .RN(n3497),
.Q(intDY_EWSW[56]), .QN(n3310) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_50_ ( .D(n1699), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[50]), .QN(n3447) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_60_ ( .D(n1689), .CK(clk), .RN(n3498),
.Q(intDY_EWSW[60]), .QN(n3423) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_59_ ( .D(n1690), .CK(clk), .RN(n3524),
.Q(intDY_EWSW[59]), .QN(n3340) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_51_ ( .D(n1698), .CK(clk), .RN(n3503),
.Q(intDY_EWSW[51]), .QN(n3350) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_47_ ( .D(n1702), .CK(clk), .RN(n3476),
.Q(intDY_EWSW[47]), .QN(n3349) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_54_ ( .D(n1695), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[54]), .QN(n3312) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_49_ ( .D(n1700), .CK(clk), .RN(n3498),
.Q(intDY_EWSW[49]), .QN(n3430) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_42_ ( .D(n1707), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[42]), .QN(n3444) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_41_ ( .D(n1708), .CK(clk), .RN(n3492),
.Q(intDY_EWSW[41]), .QN(n3343) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n1743), .CK(clk), .RN(n3487),
.Q(intDY_EWSW[6]), .QN(n3352) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n1746), .CK(clk), .RN(n3488),
.Q(intDY_EWSW[3]), .QN(n3331) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n1747), .CK(clk), .RN(n3520),
.Q(intDY_EWSW[2]), .QN(n3412) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n1749), .CK(clk), .RN(n3520),
.Q(intDY_EWSW[0]), .QN(n3333) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_52_ ( .D(n1697), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[52]), .QN(n3434) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_46_ ( .D(n1703), .CK(clk), .RN(n3505),
.Q(intDY_EWSW[46]), .QN(n3446) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_43_ ( .D(n1706), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[43]), .QN(n3344) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_56_ ( .D(n1552), .CK(clk), .RN(n3481), .Q(
DMP_EXP_EWSW[56]), .QN(n3359) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_55_ ( .D(n1553), .CK(clk), .RN(n3524), .Q(
DMP_EXP_EWSW[55]), .QN(n3354) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_54_ ( .D(n1554), .CK(clk), .RN(n3481), .Q(
DMP_EXP_EWSW[54]), .QN(n3355) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_53_ ( .D(n1555), .CK(clk), .RN(n3524), .Q(
DMP_EXP_EWSW[53]), .QN(n3351) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_54_ ( .D(n1225), .CK(clk), .RN(n3499), .Q(
DmP_EXP_EWSW[54]), .QN(n3353) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_56_ ( .D(n1223), .CK(clk), .RN(n3500), .Q(
DmP_EXP_EWSW[56]), .QN(n3357) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_55_ ( .D(n1224), .CK(clk), .RN(n3530), .Q(
DmP_EXP_EWSW[55]), .QN(n3360) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_53_ ( .D(n1226), .CK(clk), .RN(n3499), .Q(
DmP_EXP_EWSW[53]), .QN(n3356) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n1722), .CK(clk), .RN(n3525),
.Q(intDY_EWSW[27]), .QN(n3338) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n1724), .CK(clk), .RN(n3517),
.Q(intDY_EWSW[25]), .QN(n3337) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n1725), .CK(clk), .RN(n3514),
.Q(intDY_EWSW[24]), .QN(n3418) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n1727), .CK(clk), .RN(n3500),
.Q(intDY_EWSW[22]), .QN(n3451) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n1729), .CK(clk), .RN(n3489),
.Q(intDY_EWSW[20]), .QN(n3417) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n1732), .CK(clk), .RN(n3523),
.Q(intDY_EWSW[17]), .QN(n3335) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n1735), .CK(clk), .RN(n3491),
.Q(intDY_EWSW[14]), .QN(n3450) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n1737), .CK(clk), .RN(n3484),
.Q(intDY_EWSW[12]), .QN(n3415) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n1738), .CK(clk), .RN(n3523),
.Q(intDY_EWSW[11]), .QN(n3345) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n1740), .CK(clk), .RN(n3510),
.Q(intDY_EWSW[9]), .QN(n3407) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n1656), .CK(clk), .RN(n3478), .Q(
Data_array_SWR[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_42_ ( .D(n1247), .CK(clk), .RN(n3498), .Q(
DmP_EXP_EWSW[42]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1163), .CK(clk), .RN(n3477), .Q(
DmP_mant_SFG_SWR[13]), .QN(n1980) );
ADDFX1TS DP_OP_15J75_123_4372_U11 ( .A(n3371), .B(DMP_exp_NRM2_EW[1]), .CI(
DP_OP_15J75_123_4372_n11), .CO(DP_OP_15J75_123_4372_n10), .S(
exp_rslt_NRM2_EW1[1]) );
ADDFX1TS DP_OP_15J75_123_4372_U10 ( .A(n3395), .B(DMP_exp_NRM2_EW[2]), .CI(
DP_OP_15J75_123_4372_n10), .CO(DP_OP_15J75_123_4372_n9), .S(
exp_rslt_NRM2_EW1[2]) );
ADDFX1TS DP_OP_15J75_123_4372_U9 ( .A(n3394), .B(DMP_exp_NRM2_EW[3]), .CI(
DP_OP_15J75_123_4372_n9), .CO(DP_OP_15J75_123_4372_n8), .S(
exp_rslt_NRM2_EW1[3]) );
ADDFX1TS DP_OP_15J75_123_4372_U8 ( .A(n3403), .B(DMP_exp_NRM2_EW[4]), .CI(
DP_OP_15J75_123_4372_n8), .CO(DP_OP_15J75_123_4372_n7), .S(
exp_rslt_NRM2_EW1[4]) );
ADDFX1TS DP_OP_15J75_123_4372_U7 ( .A(n3406), .B(DMP_exp_NRM2_EW[5]), .CI(
DP_OP_15J75_123_4372_n7), .CO(DP_OP_15J75_123_4372_n6), .S(
exp_rslt_NRM2_EW1[5]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1347), .CK(clk), .RN(n3518), .Q(
DMP_exp_NRM2_EW[7]), .QN(n3426) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_50_ ( .D(n1168), .CK(clk), .RN(n3472), .Q(
Raw_mant_NRM_SWR[50]), .QN(n3387) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n1817), .CK(clk), .RN(n3469), .Q(
Shift_reg_FLAGS_7[1]), .QN(n1969) );
DFFRX4TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n1750), .CK(clk), .RN(n3521),
.Q(left_right_SHT2), .QN(n3361) );
DFFRX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n1818), .CK(clk), .RN(n3469), .Q(
n1825), .QN(n3527) );
DFFSX4TS inst_ShiftRegister_Q_reg_4_ ( .D(n1991), .CK(clk), .SN(n3471), .Q(
n3462), .QN(busy) );
DFFRX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n1816), .CK(clk), .RN(n3507), .Q(
Shift_reg_FLAGS_7[0]), .QN(n1996) );
AOI222X1TS U1859 ( .A0(n2157), .A1(n3239), .B0(n3140), .B1(n3223), .C0(n3141), .C1(n3222), .Y(n3284) );
CMPR32X2TS U1860 ( .A(DMP_SFG[8]), .B(n3109), .C(n3108), .CO(n3101), .S(
n3110) );
CMPR32X2TS U1861 ( .A(n2981), .B(DMP_SFG[51]), .C(n2980), .CO(n2982), .S(
n2979) );
AOI222X1TS U1862 ( .A0(Raw_mant_NRM_SWR[41]), .A1(n2673), .B0(n2707), .B1(
n1922), .C0(n2644), .C1(DmP_mant_SHT1_SW[11]), .Y(n2578) );
AOI222X1TS U1863 ( .A0(Raw_mant_NRM_SWR[40]), .A1(n2673), .B0(n2707), .B1(
DmP_mant_SHT1_SW[13]), .C0(n2644), .C1(n1922), .Y(n2713) );
CMPR32X2TS U1864 ( .A(n2978), .B(DMP_SFG[50]), .C(n2977), .CO(n2980), .S(
n2976) );
CMPR32X2TS U1865 ( .A(n2975), .B(DMP_SFG[49]), .C(n2974), .CO(n2977), .S(
n2973) );
CMPR32X2TS U1866 ( .A(n2972), .B(DMP_SFG[48]), .C(n2971), .CO(n2974), .S(
n2001) );
CMPR32X2TS U1867 ( .A(n2969), .B(DMP_SFG[47]), .C(n2968), .CO(n2971), .S(
n2970) );
CMPR32X2TS U1868 ( .A(n2966), .B(DMP_SFG[46]), .C(n2965), .CO(n2968), .S(
n2967) );
CMPR32X2TS U1869 ( .A(n2963), .B(DMP_SFG[45]), .C(n2962), .CO(n2965), .S(
n2964) );
CMPR32X2TS U1870 ( .A(n2003), .B(DMP_SFG[44]), .C(n2002), .CO(n2962), .S(
n2004) );
CMPR32X2TS U1871 ( .A(n2960), .B(DMP_SFG[43]), .C(n2959), .CO(n2002), .S(
n2961) );
CMPR32X2TS U1872 ( .A(n2957), .B(DMP_SFG[42]), .C(n2956), .CO(n2959), .S(
n2958) );
CMPR32X2TS U1873 ( .A(n2954), .B(DMP_SFG[41]), .C(n2953), .CO(n2956), .S(
n2955) );
CMPR32X2TS U1874 ( .A(n2099), .B(DMP_SFG[17]), .C(n2098), .CO(n2898), .S(
n2100) );
CMPR32X2TS U1875 ( .A(n2096), .B(DMP_SFG[16]), .C(n2095), .CO(n2098), .S(
n2097) );
NOR2BX1TS U1876 ( .AN(n2762), .B(Raw_mant_NRM_SWR[34]), .Y(n2066) );
NOR2X1TS U1877 ( .A(n1857), .B(Raw_mant_NRM_SWR[35]), .Y(n2762) );
INVX4TS U1878 ( .A(n2554), .Y(n2570) );
OAI211XLTS U1879 ( .A0(n2596), .A1(n2570), .B0(n2595), .C0(n2594), .Y(n1656)
);
OAI211XLTS U1880 ( .A0(n2689), .A1(n2716), .B0(n2688), .C0(n2687), .Y(n1650)
);
OAI211XLTS U1881 ( .A0(n2629), .A1(n2716), .B0(n2564), .C0(n2563), .Y(n1637)
);
OAI211XLTS U1882 ( .A0(n2604), .A1(n2690), .B0(n2603), .C0(n2602), .Y(n1673)
);
OAI211XLTS U1883 ( .A0(n2682), .A1(n2716), .B0(n2660), .C0(n2659), .Y(n1670)
);
OAI211XLTS U1884 ( .A0(n2638), .A1(n2690), .B0(n2637), .C0(n2636), .Y(n1660)
);
OAI211XLTS U1885 ( .A0(n2725), .A1(n2670), .B0(n2552), .C0(n2551), .Y(n1682)
);
OAI211XLTS U1886 ( .A0(n2613), .A1(n2670), .B0(n2612), .C0(n2611), .Y(n1646)
);
OAI211XLTS U1887 ( .A0(n2617), .A1(n2570), .B0(n2598), .C0(n2597), .Y(n1665)
);
AOI2BB2XLTS U1888 ( .B0(Raw_mant_NRM_SWR[48]), .B1(n1826), .A0N(n2639),
.A1N(n2724), .Y(n2640) );
OAI211X1TS U1889 ( .A0(n2639), .A1(n2670), .B0(n2543), .C0(n2542), .Y(n1638)
);
AO22X1TS U1890 ( .A0(n3090), .A1(n2984), .B0(n3088), .B1(
Raw_mant_NRM_SWR[54]), .Y(n1164) );
INVX4TS U1891 ( .A(n1854), .Y(n1914) );
OR2X2TS U1892 ( .A(n2548), .B(n2777), .Y(n1854) );
NOR3X2TS U1893 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[3]), .C(n2058),
.Y(n2084) );
ADDFX1TS U1894 ( .A(n2009), .B(DMP_SFG[40]), .CI(n2008), .CO(n2953), .S(
n2010) );
NOR3X4TS U1895 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[7]), .C(n2055),
.Y(n2728) );
ADDFX1TS U1896 ( .A(n2951), .B(DMP_SFG[39]), .CI(n2950), .CO(n2008), .S(
n2952) );
NOR2X2TS U1897 ( .A(Raw_mant_NRM_SWR[10]), .B(n2027), .Y(n2727) );
ADDFX1TS U1898 ( .A(n2006), .B(DMP_SFG[38]), .CI(n2005), .CO(n2950), .S(
n2007) );
ADDFX1TS U1899 ( .A(n2948), .B(DMP_SFG[37]), .CI(n2947), .CO(n2005), .S(
n2949) );
ADDFX1TS U1900 ( .A(n2945), .B(DMP_SFG[36]), .CI(n2944), .CO(n2947), .S(
n2946) );
ADDFX1TS U1901 ( .A(n2942), .B(DMP_SFG[35]), .CI(n2941), .CO(n2944), .S(
n2943) );
ADDFX1TS U1902 ( .A(n2939), .B(DMP_SFG[34]), .CI(n2938), .CO(n2941), .S(
n2940) );
OAI211XLTS U1903 ( .A0(n1857), .A1(n3396), .B0(n2082), .C0(n2081), .Y(n2083)
);
ADDFX1TS U1904 ( .A(n2184), .B(DMP_SFG[33]), .CI(n2183), .CO(n2938), .S(
n2185) );
NOR2BX2TS U1905 ( .AN(n2053), .B(Raw_mant_NRM_SWR[15]), .Y(n2760) );
ADDFX1TS U1906 ( .A(n2936), .B(DMP_SFG[32]), .CI(n2935), .CO(n2183), .S(
n2937) );
ADDFX1TS U1907 ( .A(n2933), .B(DMP_SFG[31]), .CI(n2932), .CO(n2935), .S(
n2934) );
ADDFX1TS U1908 ( .A(n2930), .B(DMP_SFG[30]), .CI(n2929), .CO(n2932), .S(
n2931) );
INVX1TS U1909 ( .A(n2067), .Y(n2759) );
NAND2XLTS U1910 ( .A(n1857), .B(n1966), .Y(n1963) );
ADDFX1TS U1911 ( .A(n2927), .B(DMP_SFG[29]), .CI(n2926), .CO(n2929), .S(
n2928) );
ADDFX1TS U1912 ( .A(n2924), .B(DMP_SFG[28]), .CI(n2923), .CO(n2926), .S(
n2925) );
ADDFX1TS U1913 ( .A(n2920), .B(DMP_SFG[27]), .CI(n2919), .CO(n2923), .S(
n2922) );
ADDFX1TS U1914 ( .A(n2917), .B(DMP_SFG[26]), .CI(n2916), .CO(n2919), .S(
n2918) );
ADDFX1TS U1915 ( .A(n2133), .B(DMP_SFG[25]), .CI(n2132), .CO(n2916), .S(
n2134) );
ADDFX1TS U1916 ( .A(n2102), .B(DMP_SFG[24]), .CI(n2101), .CO(n2132), .S(
n2103) );
ADDFX1TS U1917 ( .A(n2914), .B(DMP_SFG[23]), .CI(n2913), .CO(n2101), .S(
n2915) );
ADDFX1TS U1918 ( .A(n2911), .B(DMP_SFG[22]), .CI(n2910), .CO(n2913), .S(
n2912) );
ADDFX1TS U1919 ( .A(n2908), .B(DMP_SFG[21]), .CI(n2907), .CO(n2910), .S(
n2909) );
ADDFX1TS U1920 ( .A(n2905), .B(DMP_SFG[20]), .CI(n2904), .CO(n2907), .S(
n2906) );
ADDFX1TS U1921 ( .A(n2902), .B(DMP_SFG[19]), .CI(n2901), .CO(n2904), .S(
n2903) );
ADDFX1TS U1922 ( .A(n2899), .B(DMP_SFG[18]), .CI(n2898), .CO(n2901), .S(
n2900) );
CLKINVX1TS U1923 ( .A(n2047), .Y(n2048) );
BUFX3TS U1924 ( .A(n2336), .Y(n2365) );
ADDFX1TS U1925 ( .A(n2896), .B(DMP_SFG[15]), .CI(n2895), .CO(n2095), .S(
n2897) );
ADDFX1TS U1926 ( .A(n2893), .B(DMP_SFG[14]), .CI(n2892), .CO(n2895), .S(
n2894) );
OAI211X1TS U1927 ( .A0(DMP_SFG[11]), .A1(n1896), .B0(DMP_SFG[10]), .C0(n3133), .Y(n2000) );
CLKINVX6TS U1928 ( .A(n2549), .Y(n2623) );
NOR2X2TS U1929 ( .A(Raw_mant_NRM_SWR[48]), .B(n2011), .Y(n2080) );
INVX3TS U1930 ( .A(n3117), .Y(n2142) );
CLKINVX6TS U1931 ( .A(n3232), .Y(n2127) );
CLKINVX6TS U1932 ( .A(n2128), .Y(n2159) );
NAND2X4TS U1933 ( .A(n1913), .B(n1996), .Y(n2852) );
INVX1TS U1934 ( .A(n2732), .Y(n2734) );
CLKBUFX2TS U1935 ( .A(Data_array_SWR[20]), .Y(n1935) );
CLKBUFX2TS U1936 ( .A(Data_array_SWR[18]), .Y(n1934) );
NOR2X6TS U1937 ( .A(shift_value_SHT2_EWR[2]), .B(n3386), .Y(n3080) );
OAI211X1TS U1938 ( .A0(n2709), .A1(n2724), .B0(n2676), .C0(n2675), .Y(n1676)
);
OAI211X1TS U1939 ( .A0(n2691), .A1(n2570), .B0(n2681), .C0(n2680), .Y(n1666)
);
OAI211X1TS U1940 ( .A0(n2608), .A1(n2690), .B0(n2600), .C0(n2599), .Y(n1671)
);
OAI211X1TS U1941 ( .A0(n2706), .A1(n2716), .B0(n2705), .C0(n2704), .Y(n1654)
);
OAI211X1TS U1942 ( .A0(n2698), .A1(n2716), .B0(n2697), .C0(n2696), .Y(n1641)
);
OAI211X1TS U1943 ( .A0(n2664), .A1(n2570), .B0(n2654), .C0(n2653), .Y(n1659)
);
OAI211X1TS U1944 ( .A0(n2634), .A1(n2690), .B0(n2633), .C0(n2632), .Y(n1681)
);
OAI211X1TS U1945 ( .A0(n2716), .A1(n2652), .B0(n2651), .C0(n2650), .Y(n1683)
);
OAI211X1TS U1946 ( .A0(n2702), .A1(n2570), .B0(n2701), .C0(n2700), .Y(n1663)
);
OAI211X1TS U1947 ( .A0(n2647), .A1(n2690), .B0(n2646), .C0(n2645), .Y(n1664)
);
OAI211X1TS U1948 ( .A0(n2607), .A1(n2670), .B0(n2606), .C0(n2605), .Y(n1651)
);
OAI211X1TS U1949 ( .A0(n2717), .A1(n2716), .B0(n2715), .C0(n2714), .Y(n1645)
);
OAI211X1TS U1950 ( .A0(n2586), .A1(n2690), .B0(n2585), .C0(n2584), .Y(n1677)
);
OAI211X1TS U1951 ( .A0(n2635), .A1(n2690), .B0(n2619), .C0(n2618), .Y(n1662)
);
OAI211X1TS U1952 ( .A0(n2699), .A1(n2716), .B0(n2666), .C0(n2665), .Y(n1661)
);
OAI211X1TS U1953 ( .A0(n2720), .A1(n2570), .B0(n2711), .C0(n2710), .Y(n1678)
);
OAI211X1TS U1954 ( .A0(n2686), .A1(n2716), .B0(n2663), .C0(n2662), .Y(n1648)
);
OAI211X1TS U1955 ( .A0(n2703), .A1(n2716), .B0(n2669), .C0(n2668), .Y(n1652)
);
OAI211X1TS U1956 ( .A0(n2685), .A1(n2716), .B0(n2684), .C0(n2683), .Y(n1672)
);
OAI211X1TS U1957 ( .A0(n2674), .A1(n2716), .B0(n2672), .C0(n2671), .Y(n1674)
);
OAI211X1TS U1958 ( .A0(n2626), .A1(n2670), .B0(n2625), .C0(n2624), .Y(n1655)
);
OAI211X1TS U1959 ( .A0(n2622), .A1(n2670), .B0(n2621), .C0(n2620), .Y(n1653)
);
OAI211X1TS U1960 ( .A0(n2694), .A1(n2724), .B0(n2693), .C0(n2692), .Y(n1668)
);
OAI211X1TS U1961 ( .A0(n2614), .A1(n2690), .B0(n2610), .C0(n2609), .Y(n1669)
);
OAI211X1TS U1962 ( .A0(n2658), .A1(n2570), .B0(n2657), .C0(n2656), .Y(n1657)
);
OAI211X1TS U1963 ( .A0(n2583), .A1(n2690), .B0(n2580), .C0(n2579), .Y(n1679)
);
OAI211X1TS U1964 ( .A0(n2601), .A1(n2690), .B0(n2572), .C0(n2571), .Y(n1675)
);
OAI211X1TS U1965 ( .A0(n2578), .A1(n2670), .B0(n2577), .C0(n2576), .Y(n1644)
);
OAI211X1TS U1966 ( .A0(n2589), .A1(n2716), .B0(n2566), .C0(n2565), .Y(n1647)
);
OAI211X1TS U1967 ( .A0(n2713), .A1(n2716), .B0(n2556), .C0(n2555), .Y(n1643)
);
BUFX4TS U1968 ( .A(n2570), .Y(n2724) );
OAI211X1TS U1969 ( .A0(n2642), .A1(n2716), .B0(n2561), .C0(n2560), .Y(n1634)
);
OAI211X1TS U1970 ( .A0(n2593), .A1(n2670), .B0(n2547), .C0(n2546), .Y(n1635)
);
OAI211X1TS U1971 ( .A0(n2539), .A1(n2670), .B0(n2538), .C0(n2537), .Y(n1632)
);
OAI211X1TS U1972 ( .A0(n2575), .A1(n2716), .B0(n2569), .C0(n2568), .Y(n1640)
);
INVX4TS U1973 ( .A(n1854), .Y(n1826) );
AND2X4TS U1974 ( .A(n2548), .B(n2667), .Y(n2559) );
OAI211X2TS U1975 ( .A0(Raw_mant_NRM_SWR[29]), .A1(n2766), .B0(n2062), .C0(
n2061), .Y(n2548) );
AOI222X1TS U1976 ( .A0(Raw_mant_NRM_SWR[28]), .A1(n2673), .B0(n2623), .B1(
DmP_mant_SHT1_SW[25]), .C0(n2644), .C1(n1921), .Y(n2655) );
AOI222X1TS U1977 ( .A0(Raw_mant_NRM_SWR[37]), .A1(n2673), .B0(n2623), .B1(
DmP_mant_SHT1_SW[16]), .C0(n2644), .C1(n1920), .Y(n2661) );
AOI222X1TS U1978 ( .A0(Raw_mant_NRM_SWR[44]), .A1(n2631), .B0(n2707), .B1(
DmP_mant_SHT1_SW[9]), .C0(n2630), .C1(DmP_mant_SHT1_SW[8]), .Y(n2695)
);
AOI222X1TS U1979 ( .A0(Raw_mant_NRM_SWR[39]), .A1(n2673), .B0(n2677), .B1(
DmP_mant_SHT1_SW[14]), .C0(n2644), .C1(DmP_mant_SHT1_SW[13]), .Y(n2613) );
AOI222X1TS U1980 ( .A0(Raw_mant_NRM_SWR[50]), .A1(n2631), .B0(n2707), .B1(
DmP_mant_SHT1_SW[3]), .C0(n2630), .C1(DmP_mant_SHT1_SW[2]), .Y(n2593)
);
AOI222X1TS U1981 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n2678), .B0(
Raw_mant_NRM_SWR[16]), .B1(n2667), .C0(n2623), .C1(n1918), .Y(n2691)
);
AOI222X1TS U1982 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n2678), .B0(n2677), .B1(
DmP_mant_SHT1_SW[39]), .C0(n2644), .C1(DmP_mant_SHT1_SW[38]), .Y(n2608) );
AOI222X1TS U1983 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n2678), .B0(
Raw_mant_NRM_SWR[14]), .B1(n2087), .C0(n2623), .C1(
DmP_mant_SHT1_SW[38]), .Y(n2694) );
AOI222X1TS U1984 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n2673), .B0(
Raw_mant_NRM_SWR[6]), .B1(n2087), .C0(n2707), .C1(n1917), .Y(n2709) );
AOI222X1TS U1985 ( .A0(Raw_mant_NRM_SWR[30]), .A1(n2667), .B0(
Raw_mant_NRM_SWR[31]), .B1(n2708), .C0(n2623), .C1(
DmP_mant_SHT1_SW[22]), .Y(n2703) );
AOI222X1TS U1986 ( .A0(Raw_mant_NRM_SWR[32]), .A1(n2667), .B0(n1950), .B1(
n2708), .C0(n2623), .C1(DmP_mant_SHT1_SW[20]), .Y(n2689) );
AOI222X1TS U1987 ( .A0(Raw_mant_NRM_SWR[46]), .A1(n2631), .B0(n2677), .B1(
n1924), .C0(n2630), .C1(DmP_mant_SHT1_SW[6]), .Y(n2629) );
AOI222X1TS U1988 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n2678), .B0(n2707), .B1(
DmP_mant_SHT1_SW[30]), .C0(n2630), .C1(n1919), .Y(n2635) );
AOI222X1TS U1989 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n2678), .B0(n2677), .B1(
DmP_mant_SHT1_SW[32]), .C0(n2630), .C1(DmP_mant_SHT1_SW[31]), .Y(n2647) );
AOI222X1TS U1990 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n2678), .B0(n2707), .B1(
DmP_mant_SHT1_SW[34]), .C0(n2630), .C1(DmP_mant_SHT1_SW[33]), .Y(n2679) );
AOI222X1TS U1991 ( .A0(Raw_mant_NRM_SWR[47]), .A1(n2631), .B0(n2707), .B1(
DmP_mant_SHT1_SW[6]), .C0(n2644), .C1(n1923), .Y(n2639) );
AOI222X1TS U1992 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n2678), .B0(
Raw_mant_NRM_SWR[23]), .B1(n2667), .C0(n2707), .C1(n1919), .Y(n2664)
);
AOI222X1TS U1993 ( .A0(Raw_mant_NRM_SWR[35]), .A1(n2673), .B0(
Raw_mant_NRM_SWR[34]), .B1(n2087), .C0(n2707), .C1(
DmP_mant_SHT1_SW[18]), .Y(n2686) );
AOI222X1TS U1994 ( .A0(Raw_mant_NRM_SWR[49]), .A1(n2631), .B0(n2677), .B1(
n1925), .C0(n2557), .C1(DmP_mant_SHT1_SW[3]), .Y(n2642) );
NAND3X1TS U1995 ( .A(n2084), .B(Raw_mant_NRM_SWR[1]), .C(n3328), .Y(n2736)
);
INVX1TS U1996 ( .A(n2728), .Y(n2729) );
AO21X1TS U1997 ( .A0(n3311), .A1(n3330), .B0(n2055), .Y(n2056) );
NAND3X1TS U1998 ( .A(n2020), .B(n2041), .C(n2746), .Y(n2021) );
NAND2X2TS U1999 ( .A(n2727), .B(n3317), .Y(n2055) );
NAND2X2TS U2000 ( .A(n2726), .B(n3308), .Y(n2027) );
NOR2X2TS U2001 ( .A(Raw_mant_NRM_SWR[12]), .B(n2771), .Y(n2726) );
OAI211X1TS U2002 ( .A0(n3362), .A1(n2072), .B0(n2071), .C0(n2737), .Y(n2073)
);
NAND2X2TS U2003 ( .A(n2070), .B(n3315), .Y(n2771) );
INVX1TS U2004 ( .A(n2043), .Y(n2060) );
NOR2X2TS U2005 ( .A(Raw_mant_NRM_SWR[16]), .B(n2043), .Y(n2053) );
NAND2X2TS U2006 ( .A(n2732), .B(n2733), .Y(n2043) );
CLKAND2X2TS U2007 ( .A(n1964), .B(n1965), .Y(n1966) );
NAND2BX2TS U2008 ( .AN(Raw_mant_NRM_SWR[21]), .B(n2014), .Y(n2067) );
NOR3BX2TS U2009 ( .AN(n2024), .B(Raw_mant_NRM_SWR[23]), .C(
Raw_mant_NRM_SWR[22]), .Y(n2014) );
NAND2XLTS U2010 ( .A(n2024), .B(Raw_mant_NRM_SWR[22]), .Y(n2768) );
NOR2BX2TS U2011 ( .AN(n2046), .B(Raw_mant_NRM_SWR[24]), .Y(n2024) );
NAND2XLTS U2012 ( .A(Raw_mant_NRM_SWR[25]), .B(n2019), .Y(n2746) );
OR2X4TS U2013 ( .A(n2884), .B(n2876), .Y(n2146) );
NOR2X2TS U2014 ( .A(Raw_mant_NRM_SWR[26]), .B(n2026), .Y(n2019) );
INVX1TS U2015 ( .A(n2748), .Y(n2065) );
NAND2BX2TS U2016 ( .AN(Raw_mant_NRM_SWR[30]), .B(n2025), .Y(n2748) );
NOR3X2TS U2017 ( .A(Raw_mant_NRM_SWR[32]), .B(Raw_mant_NRM_SWR[31]), .C(
n2064), .Y(n2025) );
INVX1TS U2018 ( .A(n2064), .Y(n2761) );
NAND2BX2TS U2019 ( .AN(n1950), .B(n2066), .Y(n2064) );
BUFX4TS U2020 ( .A(n2384), .Y(n1827) );
OR2X2TS U2021 ( .A(Raw_mant_NRM_SWR[36]), .B(n2047), .Y(n1857) );
NAND2X1TS U2022 ( .A(n2013), .B(n2745), .Y(n2047) );
NAND2X2TS U2023 ( .A(n2873), .B(n2326), .Y(n2336) );
OAI32X4TS U2024 ( .A0(n3128), .A1(n3127), .A2(n3126), .B0(n3232), .B1(n3128),
.Y(n3155) );
ADDFX1TS U2025 ( .A(DMP_SFG[13]), .B(n2890), .CI(n2889), .CO(n2892), .S(
n2891) );
ADDFX1TS U2026 ( .A(DMP_SFG[12]), .B(n2887), .CI(n2886), .CO(n2889), .S(
n2888) );
NOR2X6TS U2027 ( .A(left_right_SHT2), .B(n2127), .Y(n2156) );
INVX4TS U2028 ( .A(n2648), .Y(n2644) );
CLKINVX3TS U2029 ( .A(n3201), .Y(n2168) );
CLKBUFX2TS U2030 ( .A(Data_array_SWR[19]), .Y(n1936) );
INVX6TS U2031 ( .A(rst), .Y(n3530) );
NOR2BX2TS U2032 ( .AN(n2760), .B(Raw_mant_NRM_SWR[14]), .Y(n2070) );
NAND2X2TS U2033 ( .A(n2728), .B(n2731), .Y(n2058) );
AOI2BB2XLTS U2034 ( .B0(n3075), .B1(DmP_mant_SFG_SWR[25]), .A0N(
DmP_mant_SFG_SWR[25]), .A1N(n3076), .Y(n2914) );
AOI2BB2XLTS U2035 ( .B0(n3075), .B1(DmP_mant_SFG_SWR[28]), .A0N(
DmP_mant_SFG_SWR[28]), .A1N(n3076), .Y(n2917) );
NOR3X1TS U2036 ( .A(Raw_mant_NRM_SWR[44]), .B(Raw_mant_NRM_SWR[46]), .C(
Raw_mant_NRM_SWR[45]), .Y(n2023) );
AOI222X1TS U2037 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n2708), .B0(n2707), .B1(
DmP_mant_SHT1_SW[49]), .C0(n2644), .C1(n1916), .Y(n2634) );
AOI222X1TS U2038 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n2708), .B0(n2677), .B1(
DmP_mant_SHT1_SW[47]), .C0(n2644), .C1(n1917), .Y(n2583) );
AOI222X1TS U2039 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n2708), .B0(n2707), .B1(
DmP_mant_SHT1_SW[45]), .C0(n2644), .C1(n1928), .Y(n2586) );
AOI2BB2XLTS U2040 ( .B0(n1999), .B1(DmP_mant_SFG_SWR[30]), .A0N(
DmP_mant_SFG_SWR[30]), .A1N(n3075), .Y(n2924) );
AOI222X1TS U2041 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n2678), .B0(n2677), .B1(
DmP_mant_SHT1_SW[43]), .C0(n2644), .C1(n1929), .Y(n2601) );
AOI222X1TS U2042 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n2678), .B0(n2707), .B1(
DmP_mant_SHT1_SW[41]), .C0(n2644), .C1(n1930), .Y(n2604) );
AOI222X1TS U2043 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n2708), .B0(
Raw_mant_NRM_SWR[4]), .B1(n2087), .C0(n2677), .C1(n1916), .Y(n2720) );
AOI222X1TS U2044 ( .A0(Raw_mant_NRM_SWR[28]), .A1(n2667), .B0(
Raw_mant_NRM_SWR[29]), .B1(n2708), .C0(n2677), .C1(n1921), .Y(n2706)
);
AOI222X1TS U2045 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n2678), .B0(n2677), .B1(
DmP_mant_SHT1_SW[28]), .C0(n2630), .C1(DmP_mant_SHT1_SW[27]), .Y(n2638) );
AOI2BB2XLTS U2046 ( .B0(n1999), .B1(DmP_mant_SFG_SWR[24]), .A0N(
DmP_mant_SFG_SWR[24]), .A1N(n3075), .Y(n2911) );
AOI2BB2XLTS U2047 ( .B0(n1999), .B1(DmP_mant_SFG_SWR[27]), .A0N(
DmP_mant_SFG_SWR[27]), .A1N(n3075), .Y(n2133) );
AOI222X1TS U2048 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n2678), .B0(
Raw_mant_NRM_SWR[2]), .B1(n2667), .C0(DmP_mant_SHT1_SW[50]), .C1(n2707), .Y(n2725) );
AOI222X1TS U2049 ( .A0(Raw_mant_NRM_SWR[41]), .A1(n2667), .B0(
Raw_mant_NRM_SWR[42]), .B1(n2708), .C0(n2677), .C1(
DmP_mant_SHT1_SW[11]), .Y(n2698) );
AOI222X1TS U2050 ( .A0(Raw_mant_NRM_SWR[37]), .A1(n2667), .B0(
Raw_mant_NRM_SWR[38]), .B1(n2708), .C0(n2623), .C1(n1920), .Y(n2717)
);
AOI222X1TS U2051 ( .A0(Raw_mant_NRM_SWR[34]), .A1(n2673), .B0(n2707), .B1(
n1938), .C0(n2630), .C1(DmP_mant_SHT1_SW[18]), .Y(n2607) );
AOI222X1TS U2052 ( .A0(Raw_mant_NRM_SWR[32]), .A1(n2673), .B0(n2677), .B1(
n1937), .C0(n2630), .C1(DmP_mant_SHT1_SW[20]), .Y(n2622) );
AOI222X1TS U2053 ( .A0(Raw_mant_NRM_SWR[30]), .A1(n2673), .B0(n2677), .B1(
DmP_mant_SHT1_SW[23]), .C0(n2630), .C1(DmP_mant_SHT1_SW[22]), .Y(n2626) );
AOI222X1TS U2054 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n2667), .B0(
Raw_mant_NRM_SWR[26]), .B1(n2708), .C0(n2677), .C1(
DmP_mant_SHT1_SW[27]), .Y(n2658) );
AOI222X1TS U2055 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n2087), .B0(
Raw_mant_NRM_SWR[22]), .B1(n2708), .C0(n2707), .C1(
DmP_mant_SHT1_SW[31]), .Y(n2699) );
AOI222X1TS U2056 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n2087), .B0(
Raw_mant_NRM_SWR[20]), .B1(n2708), .C0(n2677), .C1(
DmP_mant_SHT1_SW[33]), .Y(n2702) );
CLKINVX6TS U2057 ( .A(n2810), .Y(n2719) );
NAND2BXLTS U2058 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n2221) );
NAND2X1TS U2059 ( .A(n2023), .B(n2080), .Y(n2012) );
NAND2BXLTS U2060 ( .AN(intDY_EWSW[47]), .B(intDX_EWSW[47]), .Y(n2269) );
AO22XLTS U2061 ( .A0(n3336), .A1(intDX_EWSW[19]), .B0(n3416), .B1(
intDX_EWSW[18]), .Y(n1872) );
NOR2BX2TS U2062 ( .AN(n2075), .B(Raw_mant_NRM_SWR[42]), .Y(n2015) );
NAND2BXLTS U2063 ( .AN(intDY_EWSW[62]), .B(intDX_EWSW[62]), .Y(n2266) );
NAND2BXLTS U2064 ( .AN(intDX_EWSW[62]), .B(intDY_EWSW[62]), .Y(n2264) );
AOI31XLTS U2065 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n2733), .A2(n3399), .B0(
n2083), .Y(n2085) );
AOI211X1TS U2066 ( .A0(shift_value_SHT2_EWR[5]), .A1(n1898), .B0(n3047),
.C0(n3046), .Y(n3244) );
AOI211X1TS U2067 ( .A0(shift_value_SHT2_EWR[5]), .A1(n1899), .B0(n3063),
.C0(n3062), .Y(n3214) );
AO21XLTS U2068 ( .A0(n1957), .A1(n3125), .B0(n3104), .Y(n1833) );
OAI31X1TS U2069 ( .A0(n2765), .A1(n2764), .A2(Raw_mant_NRM_SWR[48]), .B0(
n2763), .Y(n2767) );
NAND4X1TS U2070 ( .A(n2052), .B(n2051), .C(n2050), .D(n2049), .Y(n2756) );
OAI21XLTS U2071 ( .A0(Raw_mant_NRM_SWR[35]), .A1(Raw_mant_NRM_SWR[36]), .B0(
n2048), .Y(n2049) );
AOI2BB2XLTS U2072 ( .B0(n3075), .B1(DmP_mant_SFG_SWR[31]), .A0N(
DmP_mant_SFG_SWR[31]), .A1N(n3076), .Y(n2927) );
AOI222X1TS U2073 ( .A0(Raw_mant_NRM_SWR[27]), .A1(n2673), .B0(n2623), .B1(
DmP_mant_SHT1_SW[26]), .C0(n2630), .C1(DmP_mant_SHT1_SW[25]), .Y(n2596) );
AOI2BB2XLTS U2074 ( .B0(n3076), .B1(DmP_mant_SFG_SWR[29]), .A0N(
DmP_mant_SFG_SWR[29]), .A1N(n1999), .Y(n2920) );
AOI2BB2XLTS U2075 ( .B0(n3076), .B1(DmP_mant_SFG_SWR[23]), .A0N(
DmP_mant_SFG_SWR[23]), .A1N(n1999), .Y(n2908) );
AOI222X1TS U2076 ( .A0(n3036), .A1(DMP_SFG[1]), .B0(n3036), .B1(n3035), .C0(
DMP_SFG[1]), .C1(n3035), .Y(n3064) );
BUFX4TS U2077 ( .A(n2793), .Y(n2804) );
AOI2BB2XLTS U2078 ( .B0(n3076), .B1(DmP_mant_SFG_SWR[26]), .A0N(
DmP_mant_SFG_SWR[26]), .A1N(n1999), .Y(n2102) );
OAI211X1TS U2079 ( .A0(n1858), .A1(n3197), .B0(n3196), .C0(n3195), .Y(n3272)
);
OAI211X1TS U2080 ( .A0(n1858), .A1(n3242), .B0(n3193), .C0(n3192), .Y(n3264)
);
OAI211X1TS U2081 ( .A0(n3153), .A1(n3197), .B0(n3152), .C0(n3151), .Y(n3271)
);
OAI211X1TS U2082 ( .A0(n3153), .A1(n3242), .B0(n3147), .C0(n3146), .Y(n3265)
);
OAI211X1TS U2083 ( .A0(n1897), .A1(n3197), .B0(n3144), .C0(n3143), .Y(n3269)
);
OAI211X1TS U2084 ( .A0(n1897), .A1(n3242), .B0(n3139), .C0(n3138), .Y(n3267)
);
AO22XLTS U2085 ( .A0(n2760), .A1(Raw_mant_NRM_SWR[14]), .B0(
Raw_mant_NRM_SWR[20]), .B1(n2759), .Y(n2775) );
NAND4XLTS U2086 ( .A(n2086), .B(n2769), .C(n2031), .D(n2050), .Y(n2032) );
NAND4BXLTS U2087 ( .AN(n2738), .B(n2737), .C(n2736), .D(n2735), .Y(n2739) );
OAI31X1TS U2088 ( .A0(Raw_mant_NRM_SWR[16]), .A1(Raw_mant_NRM_SWR[14]), .A2(
n2734), .B0(n2733), .Y(n2735) );
BUFX4TS U2089 ( .A(n3462), .Y(n2859) );
BUFX6TS U2090 ( .A(n1933), .Y(n2386) );
AOI222X1TS U2091 ( .A0(Raw_mant_NRM_SWR[43]), .A1(n2673), .B0(n2707), .B1(
DmP_mant_SHT1_SW[10]), .C0(n2630), .C1(DmP_mant_SHT1_SW[9]), .Y(n2575)
);
AOI222X1TS U2092 ( .A0(Raw_mant_NRM_SWR[36]), .A1(n2673), .B0(n2623), .B1(
DmP_mant_SHT1_SW[17]), .C0(n2630), .C1(DmP_mant_SHT1_SW[16]), .Y(n2589) );
AOI222X1TS U2093 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n2678), .B0(n2677), .B1(
DmP_mant_SHT1_SW[35]), .C0(n2630), .C1(DmP_mant_SHT1_SW[34]), .Y(n2617) );
NAND3XLTS U2094 ( .A(Raw_mant_NRM_SWR[0]), .B(n2777), .C(n2549), .Y(n2652)
);
AO22XLTS U2095 ( .A0(n2808), .A1(Data_Y[63]), .B0(n2807), .B1(intDY_EWSW[63]), .Y(n1686) );
AO22XLTS U2096 ( .A0(n3297), .A1(DMP_SHT2_EWSW[38]), .B0(n2861), .B1(
DMP_SFG[38]), .Y(n1426) );
AO22XLTS U2097 ( .A0(n3292), .A1(DMP_SHT2_EWSW[37]), .B0(n2861), .B1(
DMP_SFG[37]), .Y(n1429) );
AO22XLTS U2098 ( .A0(n2858), .A1(DMP_SHT2_EWSW[36]), .B0(n2857), .B1(
DMP_SFG[36]), .Y(n1432) );
AO22XLTS U2099 ( .A0(n3297), .A1(DMP_SHT2_EWSW[35]), .B0(n2857), .B1(
DMP_SFG[35]), .Y(n1435) );
AO22XLTS U2100 ( .A0(n3292), .A1(DMP_SHT2_EWSW[34]), .B0(n2857), .B1(
DMP_SFG[34]), .Y(n1438) );
AO22XLTS U2101 ( .A0(n2858), .A1(DMP_SHT2_EWSW[33]), .B0(n2857), .B1(
DMP_SFG[33]), .Y(n1441) );
AO22XLTS U2102 ( .A0(n3297), .A1(DMP_SHT2_EWSW[32]), .B0(n2857), .B1(
DMP_SFG[32]), .Y(n1444) );
AO22XLTS U2103 ( .A0(n3292), .A1(DMP_SHT2_EWSW[31]), .B0(n2857), .B1(
DMP_SFG[31]), .Y(n1447) );
AO22XLTS U2104 ( .A0(n2858), .A1(DMP_SHT2_EWSW[30]), .B0(n2857), .B1(
DMP_SFG[30]), .Y(n1450) );
AO22XLTS U2105 ( .A0(n3292), .A1(DMP_SHT2_EWSW[29]), .B0(n2857), .B1(
DMP_SFG[29]), .Y(n1453) );
AO22XLTS U2106 ( .A0(n3297), .A1(DMP_SHT2_EWSW[28]), .B0(n2857), .B1(
DMP_SFG[28]), .Y(n1456) );
AO22XLTS U2107 ( .A0(n2858), .A1(DMP_SHT2_EWSW[27]), .B0(n2857), .B1(
DMP_SFG[27]), .Y(n1459) );
AO22XLTS U2108 ( .A0(n3297), .A1(DMP_SHT2_EWSW[26]), .B0(n2857), .B1(
DMP_SFG[26]), .Y(n1462) );
AO22XLTS U2109 ( .A0(n3292), .A1(DMP_SHT2_EWSW[25]), .B0(n2857), .B1(
DMP_SFG[25]), .Y(n1465) );
AO22XLTS U2110 ( .A0(n3261), .A1(n3154), .B0(n3130), .B1(
DmP_mant_SFG_SWR[11]), .Y(n1130) );
AO22XLTS U2111 ( .A0(n3261), .A1(n3113), .B0(n3130), .B1(
DmP_mant_SFG_SWR[10]), .Y(n1136) );
AO22XLTS U2112 ( .A0(n2880), .A1(DmP_EXP_EWSW[50]), .B0(n2877), .B1(
DmP_mant_SHT1_SW[50]), .Y(n1230) );
AO22XLTS U2113 ( .A0(n2880), .A1(DmP_EXP_EWSW[51]), .B0(n2877), .B1(
DmP_mant_SHT1_SW[51]), .Y(n1228) );
AO22XLTS U2114 ( .A0(n2880), .A1(DmP_EXP_EWSW[39]), .B0(n2870), .B1(
DmP_mant_SHT1_SW[39]), .Y(n1252) );
AO22XLTS U2115 ( .A0(n2880), .A1(DmP_EXP_EWSW[37]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[37]), .Y(n1256) );
AO22XLTS U2116 ( .A0(n2880), .A1(DmP_EXP_EWSW[47]), .B0(n2870), .B1(
DmP_mant_SHT1_SW[47]), .Y(n1236) );
AO22XLTS U2117 ( .A0(n2880), .A1(DmP_EXP_EWSW[49]), .B0(n2870), .B1(
DmP_mant_SHT1_SW[49]), .Y(n1232) );
AO22XLTS U2118 ( .A0(n2880), .A1(DmP_EXP_EWSW[45]), .B0(n2870), .B1(
DmP_mant_SHT1_SW[45]), .Y(n1240) );
AO22XLTS U2119 ( .A0(n2880), .A1(DmP_EXP_EWSW[43]), .B0(n2870), .B1(
DmP_mant_SHT1_SW[43]), .Y(n1244) );
AO22XLTS U2120 ( .A0(n2880), .A1(DmP_EXP_EWSW[41]), .B0(n2870), .B1(
DmP_mant_SHT1_SW[41]), .Y(n1248) );
AO22XLTS U2121 ( .A0(n1825), .A1(n2958), .B0(n3088), .B1(
Raw_mant_NRM_SWR[44]), .Y(n1174) );
AOI2BB2XLTS U2122 ( .B0(Raw_mant_NRM_SWR[5]), .B1(n1914), .A0N(n2634), .A1N(
n2570), .Y(n2579) );
AOI2BB2XLTS U2123 ( .B0(Raw_mant_NRM_SWR[3]), .B1(n1914), .A0N(n2649), .A1N(
n2724), .Y(n2632) );
AOI2BB2XLTS U2124 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[43]), .A0N(n2685),
.A1N(n2670), .Y(n2671) );
AOI2BB2XLTS U2125 ( .B0(Raw_mant_NRM_SWR[7]), .B1(n1914), .A0N(n2583), .A1N(
n2724), .Y(n2584) );
AOI2BB2XLTS U2126 ( .B0(Raw_mant_NRM_SWR[9]), .B1(n1914), .A0N(n2586), .A1N(
n2570), .Y(n2571) );
AO22XLTS U2127 ( .A0(n3090), .A1(n2906), .B0(n2921), .B1(
Raw_mant_NRM_SWR[22]), .Y(n1196) );
AO22XLTS U2128 ( .A0(n2805), .A1(Data_X[6]), .B0(n2797), .B1(intDX_EWSW[6]),
.Y(n1809) );
AO22XLTS U2129 ( .A0(n1825), .A1(n2979), .B0(n3088), .B1(
Raw_mant_NRM_SWR[53]), .Y(n1165) );
AOI2BB2XLTS U2130 ( .B0(n2721), .B1(n1938), .A0N(n2686), .A1N(n2719), .Y(
n2687) );
AOI2BB2XLTS U2131 ( .B0(n2718), .B1(DmP_mant_SHT1_SW[14]), .A0N(n2717),
.A1N(n2719), .Y(n2565) );
AOI2BB2XLTS U2132 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[17]), .A0N(n2661),
.A1N(n2719), .Y(n2662) );
AO22XLTS U2133 ( .A0(n1825), .A1(n2928), .B0(n3088), .B1(
Raw_mant_NRM_SWR[31]), .Y(n1187) );
AO22XLTS U2134 ( .A0(n2805), .A1(Data_X[9]), .B0(n2797), .B1(intDX_EWSW[9]),
.Y(n1806) );
AO22XLTS U2135 ( .A0(n2793), .A1(Data_X[39]), .B0(n2795), .B1(intDX_EWSW[39]), .Y(n1776) );
AO22XLTS U2136 ( .A0(n2805), .A1(Data_X[4]), .B0(n2803), .B1(intDX_EWSW[4]),
.Y(n1811) );
AO22XLTS U2137 ( .A0(n3090), .A1(n2967), .B0(n3088), .B1(
Raw_mant_NRM_SWR[48]), .Y(n1170) );
AOI2BB2XLTS U2138 ( .B0(n2718), .B1(DmP_mant_SHT1_SW[23]), .A0N(n2706),
.A1N(n2719), .Y(n2594) );
AO22XLTS U2139 ( .A0(n2858), .A1(DMP_SHT2_EWSW[12]), .B0(n2864), .B1(
DMP_SFG[12]), .Y(n1504) );
AO22XLTS U2140 ( .A0(n3297), .A1(DMP_SHT2_EWSW[13]), .B0(n2864), .B1(
DMP_SFG[13]), .Y(n1501) );
AO22XLTS U2141 ( .A0(n3297), .A1(DMP_SHT2_EWSW[14]), .B0(n2861), .B1(
DMP_SFG[14]), .Y(n1498) );
AO22XLTS U2142 ( .A0(n3292), .A1(DMP_SHT2_EWSW[15]), .B0(n2857), .B1(
DMP_SFG[15]), .Y(n1495) );
AO22XLTS U2143 ( .A0(n3292), .A1(DMP_SHT2_EWSW[16]), .B0(n3307), .B1(
DMP_SFG[16]), .Y(n1492) );
AO22XLTS U2144 ( .A0(n2858), .A1(DMP_SHT2_EWSW[17]), .B0(n3298), .B1(
DMP_SFG[17]), .Y(n1489) );
AO22XLTS U2145 ( .A0(n3297), .A1(DMP_SHT2_EWSW[18]), .B0(n2852), .B1(
DMP_SFG[18]), .Y(n1486) );
AO22XLTS U2146 ( .A0(n3292), .A1(DMP_SHT2_EWSW[19]), .B0(n2852), .B1(
DMP_SFG[19]), .Y(n1483) );
AO22XLTS U2147 ( .A0(n2858), .A1(DMP_SHT2_EWSW[20]), .B0(n2852), .B1(
DMP_SFG[20]), .Y(n1480) );
AO22XLTS U2148 ( .A0(n3297), .A1(DMP_SHT2_EWSW[21]), .B0(n2861), .B1(
DMP_SFG[21]), .Y(n1477) );
AO22XLTS U2149 ( .A0(n3292), .A1(DMP_SHT2_EWSW[22]), .B0(n2857), .B1(
DMP_SFG[22]), .Y(n1474) );
AO22XLTS U2150 ( .A0(n2858), .A1(DMP_SHT2_EWSW[23]), .B0(n3130), .B1(
DMP_SFG[23]), .Y(n1471) );
AO22XLTS U2151 ( .A0(n3297), .A1(DMP_SHT2_EWSW[24]), .B0(n2861), .B1(
DMP_SFG[24]), .Y(n1468) );
AO22XLTS U2152 ( .A0(n3306), .A1(DMP_SHT2_EWSW[39]), .B0(n2861), .B1(
DMP_SFG[39]), .Y(n1423) );
AO22XLTS U2153 ( .A0(n3306), .A1(DMP_SHT2_EWSW[40]), .B0(n2861), .B1(
DMP_SFG[40]), .Y(n1420) );
AO22XLTS U2154 ( .A0(n3306), .A1(DMP_SHT2_EWSW[41]), .B0(n2861), .B1(
DMP_SFG[41]), .Y(n1417) );
AO22XLTS U2155 ( .A0(n3306), .A1(DMP_SHT2_EWSW[42]), .B0(n2861), .B1(
DMP_SFG[42]), .Y(n1414) );
AO22XLTS U2156 ( .A0(n3306), .A1(DMP_SHT2_EWSW[43]), .B0(n2861), .B1(
DMP_SFG[43]), .Y(n1411) );
AO22XLTS U2157 ( .A0(n3306), .A1(DMP_SHT2_EWSW[44]), .B0(n2861), .B1(
DMP_SFG[44]), .Y(n1408) );
AO22XLTS U2158 ( .A0(n3306), .A1(DMP_SHT2_EWSW[45]), .B0(n2861), .B1(
DMP_SFG[45]), .Y(n1405) );
AO22XLTS U2159 ( .A0(n3306), .A1(DMP_SHT2_EWSW[46]), .B0(n2861), .B1(
DMP_SFG[46]), .Y(n1402) );
AO22XLTS U2160 ( .A0(n3306), .A1(DMP_SHT2_EWSW[47]), .B0(n2861), .B1(
DMP_SFG[47]), .Y(n1399) );
AO22XLTS U2161 ( .A0(n3306), .A1(DMP_SHT2_EWSW[48]), .B0(n3130), .B1(
DMP_SFG[48]), .Y(n1396) );
AO22XLTS U2162 ( .A0(n3306), .A1(DMP_SHT2_EWSW[49]), .B0(n2864), .B1(
DMP_SFG[49]), .Y(n1393) );
AO22XLTS U2163 ( .A0(n3306), .A1(DMP_SHT2_EWSW[50]), .B0(n3295), .B1(
DMP_SFG[50]), .Y(n1390) );
AO22XLTS U2164 ( .A0(n3306), .A1(DMP_SHT2_EWSW[51]), .B0(n2852), .B1(
DMP_SFG[51]), .Y(n1387) );
AO22XLTS U2165 ( .A0(n3024), .A1(n2973), .B0(n3088), .B1(
Raw_mant_NRM_SWR[51]), .Y(n1167) );
OAI211XLTS U2166 ( .A0(n2596), .A1(n2670), .B0(n2582), .C0(n2581), .Y(n1658)
);
AOI2BB2XLTS U2167 ( .B0(Raw_mant_NRM_SWR[26]), .B1(n1826), .A0N(n2638),
.A1N(n2724), .Y(n2581) );
AO22XLTS U2168 ( .A0(n3261), .A1(n3001), .B0(n3130), .B1(DmP_mant_SFG_SWR[1]), .Y(n1160) );
AO22XLTS U2169 ( .A0(n3261), .A1(n3010), .B0(n3130), .B1(DmP_mant_SFG_SWR[0]), .Y(n1157) );
AO22XLTS U2170 ( .A0(n3261), .A1(n3246), .B0(n3307), .B1(DmP_mant_SFG_SWR[2]), .Y(n1154) );
AO22XLTS U2171 ( .A0(n3306), .A1(DMP_SHT2_EWSW[0]), .B0(n3307), .B1(
DMP_SFG[0]), .Y(n1540) );
AO22XLTS U2172 ( .A0(n2866), .A1(DmP_EXP_EWSW[8]), .B0(n2879), .B1(
DmP_mant_SHT1_SW[8]), .Y(n1314) );
AO22XLTS U2173 ( .A0(n2868), .A1(DmP_EXP_EWSW[3]), .B0(n2865), .B1(
DmP_mant_SHT1_SW[3]), .Y(n1324) );
AO22XLTS U2174 ( .A0(n2866), .A1(DmP_EXP_EWSW[6]), .B0(n2879), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1318) );
AO22XLTS U2175 ( .A0(n2867), .A1(DmP_EXP_EWSW[9]), .B0(n2879), .B1(
DmP_mant_SHT1_SW[9]), .Y(n1312) );
AO22XLTS U2176 ( .A0(n2867), .A1(DmP_EXP_EWSW[13]), .B0(n2879), .B1(
DmP_mant_SHT1_SW[13]), .Y(n1304) );
AO22XLTS U2177 ( .A0(n2868), .A1(DmP_EXP_EWSW[25]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[25]), .Y(n1280) );
AO22XLTS U2178 ( .A0(n2878), .A1(DmP_EXP_EWSW[34]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[34]), .Y(n1262) );
AOI222X1TS U2179 ( .A0(n1827), .A1(intDX_EWSW[52]), .B0(DmP_EXP_EWSW[52]),
.B1(n1933), .C0(intDY_EWSW[52]), .C1(n2431), .Y(n2337) );
AO22XLTS U2180 ( .A0(n3297), .A1(DMP_SHT2_EWSW[8]), .B0(n2864), .B1(
DMP_SFG[8]), .Y(n1516) );
AO22XLTS U2181 ( .A0(n2868), .A1(DmP_EXP_EWSW[11]), .B0(n2879), .B1(
DmP_mant_SHT1_SW[11]), .Y(n1308) );
AO22XLTS U2182 ( .A0(n2866), .A1(DmP_EXP_EWSW[18]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[18]), .Y(n1294) );
AO22XLTS U2183 ( .A0(n2867), .A1(DmP_EXP_EWSW[22]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[22]), .Y(n1286) );
AO22XLTS U2184 ( .A0(n2878), .A1(DmP_EXP_EWSW[27]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[27]), .Y(n1276) );
AO22XLTS U2185 ( .A0(n2878), .A1(DmP_EXP_EWSW[31]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[31]), .Y(n1268) );
AO22XLTS U2186 ( .A0(n2878), .A1(DmP_EXP_EWSW[33]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[33]), .Y(n1264) );
AO22XLTS U2187 ( .A0(n2880), .A1(DmP_EXP_EWSW[38]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[38]), .Y(n1254) );
AO22XLTS U2188 ( .A0(n2858), .A1(DMP_SHT2_EWSW[5]), .B0(n2864), .B1(
DMP_SFG[5]), .Y(n1525) );
AO22XLTS U2189 ( .A0(n3292), .A1(DMP_SHT2_EWSW[7]), .B0(n2864), .B1(
DMP_SFG[7]), .Y(n1519) );
AO22XLTS U2190 ( .A0(n2858), .A1(DMP_SHT2_EWSW[11]), .B0(n2864), .B1(
DMP_SFG[11]), .Y(n1507) );
AO22XLTS U2191 ( .A0(n2794), .A1(Data_X[63]), .B0(n2807), .B1(intDX_EWSW[63]), .Y(n1752) );
AO22XLTS U2192 ( .A0(n3528), .A1(DmP_EXP_EWSW[17]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[17]), .Y(n1296) );
AO22XLTS U2193 ( .A0(n3528), .A1(DmP_EXP_EWSW[26]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[26]), .Y(n1278) );
AO22XLTS U2194 ( .A0(n2878), .A1(DmP_EXP_EWSW[28]), .B0(n2870), .B1(
DmP_mant_SHT1_SW[28]), .Y(n1274) );
AO22XLTS U2195 ( .A0(n2878), .A1(DmP_EXP_EWSW[30]), .B0(n2870), .B1(
DmP_mant_SHT1_SW[30]), .Y(n1270) );
AO22XLTS U2196 ( .A0(n2878), .A1(DmP_EXP_EWSW[35]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[35]), .Y(n1260) );
AO22XLTS U2197 ( .A0(n2867), .A1(DmP_EXP_EWSW[10]), .B0(n2879), .B1(
DmP_mant_SHT1_SW[10]), .Y(n1310) );
AO22XLTS U2198 ( .A0(n2868), .A1(DmP_EXP_EWSW[14]), .B0(n2879), .B1(
DmP_mant_SHT1_SW[14]), .Y(n1302) );
AO22XLTS U2199 ( .A0(n2867), .A1(DmP_EXP_EWSW[23]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[23]), .Y(n1284) );
AO22XLTS U2200 ( .A0(n2878), .A1(DmP_EXP_EWSW[32]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[32]), .Y(n1266) );
AO22XLTS U2201 ( .A0(n3297), .A1(DMP_SHT2_EWSW[1]), .B0(n2864), .B1(
DMP_SFG[1]), .Y(n1537) );
AO22XLTS U2202 ( .A0(n3292), .A1(DMP_SHT2_EWSW[9]), .B0(n2864), .B1(
DMP_SFG[9]), .Y(n1513) );
AO22XLTS U2203 ( .A0(n3292), .A1(DMP_SHT2_EWSW[10]), .B0(n2864), .B1(
DMP_SFG[10]), .Y(n1510) );
AO22XLTS U2204 ( .A0(n3136), .A1(n2943), .B0(n3088), .B1(
Raw_mant_NRM_SWR[37]), .Y(n1181) );
AO22XLTS U2205 ( .A0(n1825), .A1(n2925), .B0(n3134), .B1(
Raw_mant_NRM_SWR[30]), .Y(n1188) );
AOI2BB2XLTS U2206 ( .B0(Raw_mant_NRM_SWR[11]), .B1(n1914), .A0N(n2601),
.A1N(n2724), .Y(n2602) );
AOI2BB2XLTS U2207 ( .B0(Raw_mant_NRM_SWR[13]), .B1(n1914), .A0N(n2604),
.A1N(n2724), .Y(n2599) );
AOI2BB2XLTS U2208 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[41]), .A0N(n2682),
.A1N(n2719), .Y(n2683) );
OAI211XLTS U2209 ( .A0(n2725), .A1(n2724), .B0(n2723), .C0(n2722), .Y(n1680)
);
AOI2BB2XLTS U2210 ( .B0(DmP_mant_SHT1_SW[49]), .B1(n2721), .A0N(n2720),
.A1N(n2719), .Y(n2722) );
AOI2BB2XLTS U2211 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[47]), .A0N(n2709),
.A1N(n2719), .Y(n2710) );
AO22XLTS U2212 ( .A0(n3136), .A1(n2903), .B0(n2921), .B1(
Raw_mant_NRM_SWR[21]), .Y(n1197) );
AO22XLTS U2213 ( .A0(n1825), .A1(n2952), .B0(n3527), .B1(
Raw_mant_NRM_SWR[41]), .Y(n1177) );
AO22XLTS U2214 ( .A0(n3024), .A1(n2915), .B0(n2921), .B1(
Raw_mant_NRM_SWR[25]), .Y(n1193) );
AO22XLTS U2215 ( .A0(n3024), .A1(n2976), .B0(n3088), .B1(
Raw_mant_NRM_SWR[52]), .Y(n1166) );
AO22XLTS U2216 ( .A0(n2794), .A1(Data_X[61]), .B0(n2807), .B1(intDX_EWSW[61]), .Y(n1754) );
AO22XLTS U2217 ( .A0(n2794), .A1(Data_X[62]), .B0(n2795), .B1(intDX_EWSW[62]), .Y(n1753) );
AO22XLTS U2218 ( .A0(n2794), .A1(Data_X[0]), .B0(n2807), .B1(intDX_EWSW[0]),
.Y(n1815) );
AOI2BB2XLTS U2219 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[39]), .A0N(n2694),
.A1N(n2719), .Y(n2659) );
AO22XLTS U2220 ( .A0(n1825), .A1(n2897), .B0(n2921), .B1(
Raw_mant_NRM_SWR[17]), .Y(n1201) );
AO22XLTS U2221 ( .A0(n3024), .A1(n2970), .B0(n3088), .B1(
Raw_mant_NRM_SWR[49]), .Y(n1169) );
AO22XLTS U2222 ( .A0(n1825), .A1(n2946), .B0(n3088), .B1(
Raw_mant_NRM_SWR[38]), .Y(n1180) );
AO22XLTS U2223 ( .A0(n3090), .A1(n3089), .B0(n3088), .B1(Raw_mant_NRM_SWR[6]), .Y(n1140) );
AOI2BB2XLTS U2224 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[23]), .A0N(n2703),
.A1N(n2719), .Y(n2704) );
AO22XLTS U2225 ( .A0(n3024), .A1(n2891), .B0(n2921), .B1(
Raw_mant_NRM_SWR[15]), .Y(n1203) );
AO22XLTS U2226 ( .A0(n3136), .A1(n2955), .B0(n3088), .B1(
Raw_mant_NRM_SWR[43]), .Y(n1175) );
AO22XLTS U2227 ( .A0(n3090), .A1(n2918), .B0(n2921), .B1(
Raw_mant_NRM_SWR[28]), .Y(n1190) );
AO22XLTS U2228 ( .A0(n3024), .A1(n2894), .B0(n2921), .B1(
Raw_mant_NRM_SWR[16]), .Y(n1202) );
AO22XLTS U2229 ( .A0(n3090), .A1(n2940), .B0(n3088), .B1(
Raw_mant_NRM_SWR[36]), .Y(n1182) );
AO22XLTS U2230 ( .A0(n2796), .A1(Data_X[24]), .B0(n2131), .B1(intDX_EWSW[24]), .Y(n1791) );
AO22XLTS U2231 ( .A0(n2805), .A1(Data_X[2]), .B0(n2806), .B1(intDX_EWSW[2]),
.Y(n1813) );
AO22XLTS U2232 ( .A0(n2794), .A1(Data_X[32]), .B0(n2795), .B1(intDX_EWSW[32]), .Y(n1783) );
AO22XLTS U2233 ( .A0(n2796), .A1(Data_X[16]), .B0(n2800), .B1(intDX_EWSW[16]), .Y(n1799) );
AO22XLTS U2234 ( .A0(n2805), .A1(Data_X[7]), .B0(n2800), .B1(intDX_EWSW[7]),
.Y(n1808) );
AO22XLTS U2235 ( .A0(n3090), .A1(n2961), .B0(n3088), .B1(
Raw_mant_NRM_SWR[45]), .Y(n1173) );
AO22XLTS U2236 ( .A0(n3024), .A1(n2931), .B0(n3088), .B1(
Raw_mant_NRM_SWR[32]), .Y(n1186) );
AO22XLTS U2237 ( .A0(n2805), .A1(Data_X[10]), .B0(n2802), .B1(intDX_EWSW[10]), .Y(n1805) );
AO22XLTS U2238 ( .A0(n2794), .A1(Data_X[48]), .B0(n2807), .B1(intDX_EWSW[48]), .Y(n1767) );
AO22XLTS U2239 ( .A0(n2793), .A1(Data_X[40]), .B0(n2795), .B1(intDX_EWSW[40]), .Y(n1775) );
AO22XLTS U2240 ( .A0(n2798), .A1(Data_X[52]), .B0(n2807), .B1(intDX_EWSW[52]), .Y(n1763) );
AO22XLTS U2241 ( .A0(n2798), .A1(Data_X[37]), .B0(n2795), .B1(intDX_EWSW[37]), .Y(n1778) );
AO22XLTS U2242 ( .A0(n1825), .A1(n2949), .B0(n3088), .B1(
Raw_mant_NRM_SWR[39]), .Y(n1179) );
AO22XLTS U2243 ( .A0(n2794), .A1(Data_X[47]), .B0(n2807), .B1(intDX_EWSW[47]), .Y(n1768) );
AO22XLTS U2244 ( .A0(n2793), .A1(Data_X[44]), .B0(n2795), .B1(intDX_EWSW[44]), .Y(n1771) );
AOI2BB2XLTS U2245 ( .B0(Raw_mant_NRM_SWR[24]), .B1(n1826), .A0N(n2635),
.A1N(n2724), .Y(n2636) );
AO22XLTS U2246 ( .A0(n2793), .A1(Data_X[38]), .B0(n2795), .B1(intDX_EWSW[38]), .Y(n1777) );
AOI2BB2XLTS U2247 ( .B0(Raw_mant_NRM_SWR[29]), .B1(n1826), .A0N(n2655),
.A1N(n2724), .Y(n2624) );
AOI2BB2XLTS U2248 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[26]), .A0N(n2655),
.A1N(n2670), .Y(n2656) );
AOI2BB2XLTS U2249 ( .B0(n2721), .B1(n1937), .A0N(n2689), .A1N(n2719), .Y(
n2668) );
AO22XLTS U2250 ( .A0(n3024), .A1(n2922), .B0(n2921), .B1(
Raw_mant_NRM_SWR[29]), .Y(n1189) );
AO22XLTS U2251 ( .A0(n3090), .A1(n2909), .B0(n2921), .B1(
Raw_mant_NRM_SWR[23]), .Y(n1195) );
AO22XLTS U2252 ( .A0(n1825), .A1(n2964), .B0(n3088), .B1(
Raw_mant_NRM_SWR[47]), .Y(n1171) );
AO22XLTS U2253 ( .A0(n2805), .A1(Data_X[5]), .B0(n2806), .B1(intDX_EWSW[5]),
.Y(n1810) );
AO22XLTS U2254 ( .A0(n3090), .A1(n2900), .B0(n2921), .B1(
Raw_mant_NRM_SWR[20]), .Y(n1198) );
OAI222X1TS U2255 ( .A0(n2874), .A1(n3464), .B0(n3356), .B1(n2873), .C0(n3313), .C1(n2872), .Y(n1226) );
AO22XLTS U2256 ( .A0(n2790), .A1(n3136), .B0(n2792), .B1(n1913), .Y(n1818)
);
AO22XLTS U2257 ( .A0(n3134), .A1(Raw_mant_NRM_SWR[42]), .B0(n3090), .B1(
n2010), .Y(n1176) );
AO22XLTS U2258 ( .A0(n3134), .A1(Raw_mant_NRM_SWR[40]), .B0(n3090), .B1(
n2007), .Y(n1178) );
AO22XLTS U2259 ( .A0(n3134), .A1(Raw_mant_NRM_SWR[46]), .B0(n3136), .B1(
n2004), .Y(n1172) );
AO22XLTS U2260 ( .A0(n3088), .A1(Raw_mant_NRM_SWR[50]), .B0(n1825), .B1(
n2001), .Y(n1168) );
AO22XLTS U2261 ( .A0(n3134), .A1(Raw_mant_NRM_SWR[35]), .B0(n3024), .B1(
n2185), .Y(n1183) );
OAI21XLTS U2262 ( .A0(n2690), .A1(n2652), .B0(n2534), .Y(n1685) );
AO22XLTS U2263 ( .A0(n3253), .A1(n3301), .B0(final_result_ieee[51]), .B1(
n3225), .Y(n1078) );
AO22XLTS U2264 ( .A0(n3253), .A1(n3300), .B0(final_result_ieee[50]), .B1(
n3240), .Y(n1079) );
AO22XLTS U2265 ( .A0(n3253), .A1(n3299), .B0(final_result_ieee[49]), .B1(
n3225), .Y(n1080) );
AO22XLTS U2266 ( .A0(n3253), .A1(n3246), .B0(final_result_ieee[0]), .B1(
n3240), .Y(n1081) );
AO22XLTS U2267 ( .A0(n3253), .A1(n3245), .B0(final_result_ieee[1]), .B1(
n3225), .Y(n1082) );
AO22XLTS U2268 ( .A0(n3253), .A1(n3294), .B0(final_result_ieee[47]), .B1(
n3240), .Y(n1083) );
AO22XLTS U2269 ( .A0(n3253), .A1(n3215), .B0(final_result_ieee[3]), .B1(
n3225), .Y(n1088) );
AO22XLTS U2270 ( .A0(n3253), .A1(n3296), .B0(final_result_ieee[48]), .B1(
n3240), .Y(n1089) );
AO22XLTS U2271 ( .A0(n3253), .A1(n3212), .B0(final_result_ieee[2]), .B1(
n3225), .Y(n1090) );
AO22XLTS U2272 ( .A0(n3253), .A1(n3290), .B0(final_result_ieee[45]), .B1(
n3240), .Y(n1093) );
AO22XLTS U2273 ( .A0(n3253), .A1(n3272), .B0(final_result_ieee[29]), .B1(
n3240), .Y(n1096) );
AO22XLTS U2274 ( .A0(n3253), .A1(n3264), .B0(final_result_ieee[21]), .B1(
n3225), .Y(n1097) );
AO22XLTS U2275 ( .A0(n3253), .A1(n3187), .B0(final_result_ieee[5]), .B1(
n3240), .Y(n1098) );
AO22XLTS U2276 ( .A0(n3253), .A1(n3291), .B0(final_result_ieee[46]), .B1(
n3225), .Y(n1103) );
AO22XLTS U2277 ( .A0(n3172), .A1(n3171), .B0(final_result_ieee[4]), .B1(
n3240), .Y(n1104) );
AO22XLTS U2278 ( .A0(n3172), .A1(n3288), .B0(final_result_ieee[43]), .B1(
n3225), .Y(n1105) );
AO22XLTS U2279 ( .A0(n3172), .A1(n3270), .B0(final_result_ieee[27]), .B1(
n3240), .Y(n1108) );
AO22XLTS U2280 ( .A0(n3172), .A1(n3266), .B0(final_result_ieee[23]), .B1(
n3225), .Y(n1109) );
AO22XLTS U2281 ( .A0(n3172), .A1(n3160), .B0(final_result_ieee[7]), .B1(
n3240), .Y(n1110) );
AO22XLTS U2282 ( .A0(n3172), .A1(n3289), .B0(final_result_ieee[44]), .B1(
n3225), .Y(n1111) );
AO22XLTS U2283 ( .A0(n3172), .A1(n3157), .B0(final_result_ieee[6]), .B1(
n3240), .Y(n1112) );
AO22XLTS U2284 ( .A0(n3172), .A1(n3154), .B0(final_result_ieee[9]), .B1(
n3225), .Y(n1114) );
AO22XLTS U2285 ( .A0(n3172), .A1(n3271), .B0(final_result_ieee[28]), .B1(
n3240), .Y(n1117) );
AO22XLTS U2286 ( .A0(n3172), .A1(n3269), .B0(final_result_ieee[26]), .B1(
n3225), .Y(n1123) );
AO22XLTS U2287 ( .A0(n3172), .A1(n3267), .B0(final_result_ieee[24]), .B1(
n3240), .Y(n1124) );
AO22XLTS U2288 ( .A0(n3172), .A1(n3287), .B0(final_result_ieee[42]), .B1(
n3225), .Y(n1133) );
AO22XLTS U2289 ( .A0(n3253), .A1(n3113), .B0(final_result_ieee[8]), .B1(
n3240), .Y(n1134) );
AO22XLTS U2290 ( .A0(n3024), .A1(n2934), .B0(n3088), .B1(n1950), .Y(n1185)
);
AO22XLTS U2291 ( .A0(n2880), .A1(DmP_EXP_EWSW[48]), .B0(n2870), .B1(n1916),
.Y(n1234) );
AO22XLTS U2292 ( .A0(n2880), .A1(DmP_EXP_EWSW[46]), .B0(n2870), .B1(n1917),
.Y(n1238) );
AO22XLTS U2293 ( .A0(n2880), .A1(DmP_EXP_EWSW[44]), .B0(n2870), .B1(n1928),
.Y(n1242) );
AO22XLTS U2294 ( .A0(n2880), .A1(DmP_EXP_EWSW[42]), .B0(n2870), .B1(n1929),
.Y(n1246) );
AO22XLTS U2295 ( .A0(n2880), .A1(DmP_EXP_EWSW[40]), .B0(n2870), .B1(n1930),
.Y(n1250) );
AO22XLTS U2296 ( .A0(n2880), .A1(DmP_EXP_EWSW[36]), .B0(n2869), .B1(n1918),
.Y(n1258) );
AO22XLTS U2297 ( .A0(n2880), .A1(DmP_EXP_EWSW[29]), .B0(n2869), .B1(n1919),
.Y(n1272) );
AO22XLTS U2298 ( .A0(n3528), .A1(DmP_EXP_EWSW[21]), .B0(n2869), .B1(n1937),
.Y(n1288) );
AO22XLTS U2299 ( .A0(n2866), .A1(DmP_EXP_EWSW[19]), .B0(n2869), .B1(n1938),
.Y(n1292) );
AO22XLTS U2300 ( .A0(n2868), .A1(DmP_EXP_EWSW[15]), .B0(n2865), .B1(n1920),
.Y(n1300) );
AO22XLTS U2301 ( .A0(n2866), .A1(DmP_EXP_EWSW[12]), .B0(n2879), .B1(n1922),
.Y(n1306) );
AO22XLTS U2302 ( .A0(n2868), .A1(DmP_EXP_EWSW[7]), .B0(n2879), .B1(n1924),
.Y(n1316) );
AO22XLTS U2303 ( .A0(n2867), .A1(DmP_EXP_EWSW[5]), .B0(n2865), .B1(n1923),
.Y(n1320) );
AO22XLTS U2304 ( .A0(n2866), .A1(DmP_EXP_EWSW[4]), .B0(n2865), .B1(n1925),
.Y(n1322) );
AO22XLTS U2305 ( .A0(n2858), .A1(DMP_SHT2_EWSW[6]), .B0(n2864), .B1(n1931),
.Y(n1522) );
AO22XLTS U2306 ( .A0(n3292), .A1(DMP_SHT2_EWSW[4]), .B0(n2864), .B1(n1932),
.Y(n1528) );
AO22XLTS U2307 ( .A0(n2848), .A1(n2822), .B0(n2877), .B1(n1926), .Y(n1625)
);
AOI2BB2XLTS U2308 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[45]), .A0N(n2674),
.A1N(n2719), .Y(n2675) );
OAI211XLTS U2309 ( .A0(n2629), .A1(n2670), .B0(n2628), .C0(n2627), .Y(n1639)
);
AOI2BB2XLTS U2310 ( .B0(Raw_mant_NRM_SWR[45]), .B1(n1826), .A0N(n2695),
.A1N(n2724), .Y(n2627) );
AOI2BB2XLTS U2311 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[10]), .A0N(n2695),
.A1N(n2719), .Y(n2696) );
OAI211XLTS U2312 ( .A0(n2575), .A1(n2690), .B0(n2574), .C0(n2573), .Y(n1642)
);
AOI2BB2XLTS U2313 ( .B0(Raw_mant_NRM_SWR[42]), .B1(n1826), .A0N(n2578),
.A1N(n2570), .Y(n2573) );
AOI2BB2XLTS U2314 ( .B0(n2718), .B1(DmP_mant_SHT1_SW[10]), .A0N(n2698),
.A1N(n2719), .Y(n2555) );
AOI2BB2XLTS U2315 ( .B0(Raw_mant_NRM_SWR[40]), .B1(n1826), .A0N(n2613),
.A1N(n2570), .Y(n2576) );
AOI2BB2XLTS U2316 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[14]), .A0N(n2713),
.A1N(n2719), .Y(n2714) );
AOI2BB2XLTS U2317 ( .B0(Raw_mant_NRM_SWR[38]), .B1(n1826), .A0N(n2661),
.A1N(n2724), .Y(n2611) );
OAI211XLTS U2318 ( .A0(n2589), .A1(n2670), .B0(n2588), .C0(n2587), .Y(n1649)
);
AOI2BB2XLTS U2319 ( .B0(Raw_mant_NRM_SWR[35]), .B1(n1826), .A0N(n2607),
.A1N(n2724), .Y(n2587) );
AOI2BB2XLTS U2320 ( .B0(n1950), .B1(n1826), .A0N(n2622), .A1N(n2724), .Y(
n2605) );
AOI2BB2XLTS U2321 ( .B0(Raw_mant_NRM_SWR[31]), .B1(n1826), .A0N(n2626),
.A1N(n2724), .Y(n2620) );
AOI2BB2XLTS U2322 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[28]), .A0N(n2658),
.A1N(n2690), .Y(n2653) );
AOI2BB2XLTS U2323 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[30]), .A0N(n2664),
.A1N(n2670), .Y(n2665) );
AOI2BB2XLTS U2324 ( .B0(Raw_mant_NRM_SWR[22]), .B1(n1826), .A0N(n2647),
.A1N(n2724), .Y(n2618) );
AOI2BB2XLTS U2325 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[32]), .A0N(n2699),
.A1N(n2719), .Y(n2700) );
AOI2BB2XLTS U2326 ( .B0(Raw_mant_NRM_SWR[20]), .B1(n1914), .A0N(n2679),
.A1N(n2724), .Y(n2645) );
AOI2BB2XLTS U2327 ( .B0(n2718), .B1(DmP_mant_SHT1_SW[32]), .A0N(n2702),
.A1N(n2719), .Y(n2597) );
AOI2BB2XLTS U2328 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[35]), .A0N(n2679),
.A1N(n2719), .Y(n2680) );
OAI211XLTS U2329 ( .A0(n2617), .A1(n2690), .B0(n2616), .C0(n2615), .Y(n1667)
);
AOI2BB2XLTS U2330 ( .B0(Raw_mant_NRM_SWR[17]), .B1(n1914), .A0N(n2614),
.A1N(n2724), .Y(n2615) );
AOI2BB2XLTS U2331 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[37]), .A0N(n2691),
.A1N(n2690), .Y(n2692) );
AOI2BB2XLTS U2332 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n1914), .A0N(n2608),
.A1N(n2724), .Y(n2609) );
AOI2BB1XLTS U2333 ( .A0N(n2649), .A1N(n2690), .B0(n2721), .Y(n2650) );
AO22XLTS U2334 ( .A0(n2792), .A1(n2851), .B0(n2790), .B1(n1913), .Y(n1819)
);
OR2X1TS U2335 ( .A(n1872), .B(n1835), .Y(n1829) );
OR2X1TS U2336 ( .A(n1960), .B(n1961), .Y(n1835) );
AO22X1TS U2337 ( .A0(n1999), .A1(DmP_mant_SFG_SWR[13]), .B0(n1980), .B1(
n3037), .Y(n1853) );
OR2X1TS U2338 ( .A(n1967), .B(n1968), .Y(n1858) );
OA22X1TS U2339 ( .A0(shift_value_SHT2_EWR[4]), .A1(n2174), .B0(n3429), .B1(
n3058), .Y(n1860) );
OA22X1TS U2340 ( .A0(shift_value_SHT2_EWR[4]), .A1(n3210), .B0(n3427), .B1(
n3058), .Y(n1861) );
OA22X1TS U2341 ( .A0(shift_value_SHT2_EWR[4]), .A1(n3178), .B0(n3249), .B1(
n3058), .Y(n1862) );
OA22X1TS U2342 ( .A0(shift_value_SHT2_EWR[4]), .A1(n3220), .B0(n3428), .B1(
n3058), .Y(n1863) );
AOI22X1TS U2343 ( .A0(n3307), .A1(n3075), .B0(n2858), .B1(OP_FLAG_SHT2), .Y(
n1873) );
CLKINVX6TS U2344 ( .A(n1832), .Y(n1933) );
BUFX3TS U2345 ( .A(n3486), .Y(n3500) );
INVX4TS U2346 ( .A(n3527), .Y(n3024) );
CLKINVX6TS U2347 ( .A(n3298), .Y(n3261) );
OAI221X1TS U2348 ( .A0(n3338), .A1(intDX_EWSW[27]), .B0(n3419), .B1(
intDX_EWSW[26]), .C0(n2493), .Y(n2496) );
NOR2XLTS U2349 ( .A(n3464), .B(intDY_EWSW[53]), .Y(n2187) );
AOI222X4TS U2350 ( .A0(n2180), .A1(n3303), .B0(n2179), .B1(n3222), .C0(n3009), .C1(n3221), .Y(n3263) );
AOI222X1TS U2351 ( .A0(n2180), .A1(n3239), .B0(n2179), .B1(n2156), .C0(n3009), .C1(n3223), .Y(n3273) );
AOI222X4TS U2352 ( .A0(n3179), .A1(n3239), .B0(n3181), .B1(n2156), .C0(n3182), .C1(n3223), .Y(n3275) );
AOI222X1TS U2353 ( .A0(n3179), .A1(n3361), .B0(n3181), .B1(n3222), .C0(n3182), .C1(n3221), .Y(n3260) );
AOI222X4TS U2354 ( .A0(n3224), .A1(n3239), .B0(n3230), .B1(n2156), .C0(n3231), .C1(n3223), .Y(n3274) );
AOI222X1TS U2355 ( .A0(n3224), .A1(n3303), .B0(n3230), .B1(n3222), .C0(n3231), .C1(n3221), .Y(n3262) );
NAND4X1TS U2356 ( .A(n2086), .B(n2770), .C(n2085), .D(n2736), .Y(n2088) );
OAI21X1TS U2357 ( .A0(n3455), .A1(n3117), .B0(n3091), .Y(n3092) );
OAI211X1TS U2358 ( .A0(n2744), .A1(n2742), .B0(n2041), .C0(n2040), .Y(n2042)
);
NAND2X4TS U2359 ( .A(n2778), .B(Shift_reg_FLAGS_7[0]), .Y(n2784) );
CLKINVX6TS U2360 ( .A(n2799), .Y(n2795) );
BUFX4TS U2361 ( .A(n3516), .Y(n3489) );
BUFX4TS U2362 ( .A(n3525), .Y(n3519) );
BUFX4TS U2363 ( .A(n3516), .Y(n3487) );
BUFX4TS U2364 ( .A(n3499), .Y(n3488) );
INVX2TS U2365 ( .A(n1853), .Y(n1896) );
INVX2TS U2366 ( .A(n1833), .Y(n1897) );
AOI21X2TS U2367 ( .A0(n1956), .A1(n3125), .B0(n3118), .Y(n3153) );
OAI21X1TS U2368 ( .A0(n3457), .A1(n3117), .B0(n3116), .Y(n3118) );
BUFX4TS U2369 ( .A(n3492), .Y(n3498) );
BUFX4TS U2370 ( .A(n3510), .Y(n3522) );
BUFX4TS U2371 ( .A(n3511), .Y(n3486) );
BUFX4TS U2372 ( .A(n3510), .Y(n3485) );
BUFX4TS U2373 ( .A(n3508), .Y(n3495) );
BUFX4TS U2374 ( .A(n3508), .Y(n3480) );
BUFX4TS U2375 ( .A(n3519), .Y(n3494) );
BUFX4TS U2376 ( .A(n3519), .Y(n3517) );
BUFX4TS U2377 ( .A(n3516), .Y(n3490) );
BUFX4TS U2378 ( .A(n3472), .Y(n3491) );
BUFX4TS U2379 ( .A(n3516), .Y(n3523) );
BUFX4TS U2380 ( .A(n3514), .Y(n3496) );
BUFX4TS U2381 ( .A(n3514), .Y(n3509) );
BUFX4TS U2382 ( .A(n3492), .Y(n3497) );
BUFX4TS U2383 ( .A(n3482), .Y(n3483) );
CLKINVX6TS U2384 ( .A(n3056), .Y(n3115) );
BUFX4TS U2385 ( .A(n3485), .Y(n3479) );
BUFX4TS U2386 ( .A(n3485), .Y(n3525) );
BUFX4TS U2387 ( .A(n3481), .Y(n3492) );
BUFX4TS U2388 ( .A(n3509), .Y(n3482) );
BUFX3TS U2389 ( .A(n3480), .Y(n3518) );
BUFX4TS U2390 ( .A(n3530), .Y(n3508) );
BUFX4TS U2391 ( .A(n3530), .Y(n3514) );
BUFX4TS U2392 ( .A(n3491), .Y(n3478) );
BUFX4TS U2393 ( .A(n3491), .Y(n3477) );
BUFX4TS U2394 ( .A(n3517), .Y(n3501) );
BUFX4TS U2395 ( .A(n3522), .Y(n3499) );
XNOR2X2TS U2396 ( .A(DMP_exp_NRM2_EW[8]), .B(n2113), .Y(n2782) );
INVX2TS U2397 ( .A(n1863), .Y(n1898) );
INVX2TS U2398 ( .A(n1862), .Y(n1899) );
XNOR2X2TS U2399 ( .A(DMP_exp_NRM2_EW[0]), .B(n1995), .Y(n2779) );
XNOR2X2TS U2400 ( .A(DMP_exp_NRM2_EW[9]), .B(n2116), .Y(n2783) );
INVX2TS U2401 ( .A(n1860), .Y(n1900) );
INVX2TS U2402 ( .A(n1861), .Y(n1901) );
BUFX4TS U2403 ( .A(n3525), .Y(n3503) );
BUFX4TS U2404 ( .A(n3486), .Y(n3505) );
BUFX4TS U2405 ( .A(n3522), .Y(n3506) );
BUFX4TS U2406 ( .A(n3525), .Y(n3472) );
XNOR2X2TS U2407 ( .A(DMP_exp_NRM2_EW[6]), .B(DP_OP_15J75_123_4372_n6), .Y(
n2780) );
BUFX6TS U2408 ( .A(n2426), .Y(n2455) );
CLKINVX6TS U2409 ( .A(n3468), .Y(n3240) );
CLKINVX6TS U2410 ( .A(n3468), .Y(n3225) );
INVX2TS U2411 ( .A(n1886), .Y(n1902) );
INVX2TS U2412 ( .A(n1877), .Y(n1903) );
INVX2TS U2413 ( .A(n1876), .Y(n1904) );
INVX2TS U2414 ( .A(n1871), .Y(n1905) );
INVX2TS U2415 ( .A(n1870), .Y(n1906) );
INVX2TS U2416 ( .A(n1868), .Y(n1907) );
INVX2TS U2417 ( .A(n1867), .Y(n1908) );
INVX2TS U2418 ( .A(n1866), .Y(n1909) );
INVX2TS U2419 ( .A(n1864), .Y(n1910) );
INVX2TS U2420 ( .A(n1859), .Y(n1911) );
INVX2TS U2421 ( .A(n1856), .Y(n1912) );
INVX2TS U2422 ( .A(n1865), .Y(n1913) );
CLKINVX6TS U2423 ( .A(n2796), .Y(n2807) );
AOI2BB2X2TS U2424 ( .B0(DmP_mant_SFG_SWR[11]), .B1(n3526), .A0N(n2986),
.A1N(DmP_mant_SFG_SWR[11]), .Y(n3099) );
INVX2TS U2425 ( .A(n1875), .Y(n1915) );
CLKINVX6TS U2426 ( .A(n3527), .Y(n3136) );
INVX4TS U2427 ( .A(n3527), .Y(n3090) );
INVX2TS U2428 ( .A(n1895), .Y(n1916) );
INVX2TS U2429 ( .A(n1890), .Y(n1917) );
INVX2TS U2430 ( .A(n1889), .Y(n1918) );
INVX2TS U2431 ( .A(n1894), .Y(n1919) );
INVX2TS U2432 ( .A(n1888), .Y(n1920) );
AOI222X1TS U2433 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n2631), .B0(
DmP_mant_SHT1_SW[50]), .B1(n2644), .C0(n2623), .C1(
DmP_mant_SHT1_SW[51]), .Y(n2649) );
INVX2TS U2434 ( .A(n1885), .Y(n1921) );
INVX2TS U2435 ( .A(n1891), .Y(n1922) );
INVX2TS U2436 ( .A(n1851), .Y(n1923) );
INVX2TS U2437 ( .A(n1884), .Y(n1924) );
INVX2TS U2438 ( .A(n1852), .Y(n1925) );
INVX2TS U2439 ( .A(n1840), .Y(n1926) );
CLKINVX6TS U2440 ( .A(n3307), .Y(n3306) );
BUFX6TS U2441 ( .A(n3295), .Y(n3307) );
INVX2TS U2442 ( .A(n1850), .Y(n1927) );
INVX2TS U2443 ( .A(n1883), .Y(n1928) );
INVX2TS U2444 ( .A(n1882), .Y(n1929) );
INVX2TS U2445 ( .A(n1881), .Y(n1930) );
CLKINVX3TS U2446 ( .A(n2386), .Y(n2873) );
CLKINVX6TS U2447 ( .A(n2859), .Y(n2851) );
BUFX4TS U2448 ( .A(n2623), .Y(n2707) );
BUFX4TS U2449 ( .A(n2623), .Y(n2677) );
BUFX6TS U2450 ( .A(n2063), .Y(n2815) );
BUFX4TS U2451 ( .A(n3516), .Y(n3521) );
BUFX4TS U2452 ( .A(n3499), .Y(n3484) );
BUFX4TS U2453 ( .A(n3516), .Y(n3510) );
BUFX4TS U2454 ( .A(n3499), .Y(n3511) );
BUFX3TS U2455 ( .A(n3518), .Y(n3516) );
INVX2TS U2456 ( .A(n1880), .Y(n1931) );
INVX2TS U2457 ( .A(n1849), .Y(n1932) );
CLKBUFX2TS U2458 ( .A(n1997), .Y(n2845) );
INVX4TS U2459 ( .A(n2798), .Y(n2803) );
INVX4TS U2460 ( .A(n2798), .Y(n2806) );
CLKINVX3TS U2461 ( .A(n2877), .Y(n2850) );
CLKINVX3TS U2462 ( .A(n2877), .Y(n2848) );
BUFX4TS U2463 ( .A(n3481), .Y(n3475) );
BUFX3TS U2464 ( .A(n3517), .Y(n3524) );
CLKINVX6TS U2465 ( .A(left_right_SHT2), .Y(n3303) );
BUFX6TS U2466 ( .A(left_right_SHT2), .Y(n3239) );
INVX4TS U2467 ( .A(n2648), .Y(n2630) );
CLKINVX6TS U2468 ( .A(n3298), .Y(n3285) );
BUFX4TS U2469 ( .A(n2386), .Y(n2453) );
BUFX4TS U2470 ( .A(n2386), .Y(n2442) );
NOR2X8TS U2471 ( .A(n2716), .B(n2648), .Y(n2721) );
INVX3TS U2472 ( .A(n2859), .Y(n2882) );
BUFX4TS U2473 ( .A(n2811), .Y(n2819) );
CLKINVX6TS U2474 ( .A(n2336), .Y(n2435) );
INVX3TS U2475 ( .A(n2859), .Y(n2862) );
INVX3TS U2476 ( .A(n2842), .Y(n2456) );
INVX3TS U2477 ( .A(n2842), .Y(n2449) );
AOI222X4TS U2478 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n2678), .B0(n2677), .B1(
DmP_mant_SHT1_SW[37]), .C0(n2630), .C1(n1918), .Y(n2614) );
INVX2TS U2479 ( .A(n1893), .Y(n1937) );
INVX2TS U2480 ( .A(n1892), .Y(n1938) );
INVX2TS U2481 ( .A(n1848), .Y(n1939) );
INVX2TS U2482 ( .A(n1847), .Y(n1940) );
INVX2TS U2483 ( .A(n1846), .Y(n1941) );
INVX2TS U2484 ( .A(n1845), .Y(n1942) );
AOI211X1TS U2485 ( .A0(n2034), .A1(Raw_mant_NRM_SWR[44]), .B0(
Raw_mant_NRM_SWR[48]), .C0(Raw_mant_NRM_SWR[47]), .Y(n2037) );
NOR4X2TS U2486 ( .A(Raw_mant_NRM_SWR[54]), .B(Raw_mant_NRM_SWR[53]), .C(
Raw_mant_NRM_SWR[52]), .D(Raw_mant_NRM_SWR[51]), .Y(n2763) );
AOI22X2TS U2487 ( .A0(n1948), .A1(n2159), .B0(Data_array_SWR[29]), .B1(n3189), .Y(n3173) );
AOI22X2TS U2488 ( .A0(Data_array_SWR[34]), .A1(n2159), .B0(
Data_array_SWR[31]), .B1(n3189), .Y(n3213) );
INVX2TS U2489 ( .A(n1839), .Y(n1943) );
INVX2TS U2490 ( .A(n1844), .Y(n1944) );
INVX2TS U2491 ( .A(n1843), .Y(n1945) );
INVX2TS U2492 ( .A(n1831), .Y(n1946) );
INVX2TS U2493 ( .A(n1842), .Y(n1947) );
INVX2TS U2494 ( .A(n1841), .Y(n1948) );
OAI221X1TS U2495 ( .A0(n3453), .A1(intDX_EWSW[7]), .B0(n3352), .B1(
intDX_EWSW[6]), .C0(n2513), .Y(n2520) );
INVX2TS U2496 ( .A(n1836), .Y(n1949) );
INVX2TS U2497 ( .A(n1855), .Y(n1950) );
INVX2TS U2498 ( .A(n1830), .Y(n1951) );
INVX2TS U2499 ( .A(n1838), .Y(n1952) );
INVX2TS U2500 ( .A(n1834), .Y(n1953) );
INVX2TS U2501 ( .A(n1837), .Y(n1954) );
OAI221XLTS U2502 ( .A0(n3407), .A1(intDX_EWSW[9]), .B0(n3425), .B1(
intDX_EWSW[16]), .C0(n2508), .Y(n2509) );
AOI221X1TS U2503 ( .A0(n3440), .A1(intDX_EWSW[38]), .B0(intDX_EWSW[39]),
.B1(n3438), .C0(n2485), .Y(n2488) );
INVX2TS U2504 ( .A(n1828), .Y(n1955) );
AOI222X1TS U2505 ( .A0(intDX_EWSW[4]), .A1(n3413), .B0(intDX_EWSW[5]), .B1(
n3334), .C0(n2213), .C1(n2212), .Y(n2214) );
OAI221X1TS U2506 ( .A0(n3410), .A1(intDX_EWSW[13]), .B0(n3413), .B1(
intDX_EWSW[4]), .C0(n2506), .Y(n2511) );
INVX2TS U2507 ( .A(n1874), .Y(n1956) );
INVX2TS U2508 ( .A(n1869), .Y(n1957) );
INVX2TS U2509 ( .A(n1878), .Y(n1958) );
INVX2TS U2510 ( .A(n1879), .Y(n1959) );
NOR2XLTS U2511 ( .A(n3416), .B(intDX_EWSW[18]), .Y(n1960) );
NOR2XLTS U2512 ( .A(n3336), .B(intDX_EWSW[19]), .Y(n1961) );
NAND2X1TS U2513 ( .A(n1962), .B(n1963), .Y(n2752) );
INVX1TS U2514 ( .A(n2749), .Y(n1964) );
INVX2TS U2515 ( .A(n2750), .Y(n1965) );
NAND2X1TS U2516 ( .A(n1887), .B(n1966), .Y(n1962) );
OAI31X1TS U2517 ( .A0(n2745), .A1(n2744), .A2(n2743), .B0(n2766), .Y(n2750)
);
OAI221X1TS U2518 ( .A0(n3409), .A1(intDX_EWSW[57]), .B0(n3310), .B1(
intDX_EWSW[56]), .C0(n2463), .Y(n2470) );
OAI211XLTS U2519 ( .A0(n2593), .A1(n2570), .B0(n2592), .C0(n2591), .Y(n1633)
);
NOR4X2TS U2520 ( .A(n2188), .B(n2256), .C(n2268), .D(n2260), .Y(n2313) );
NOR2XLTS U2521 ( .A(n3125), .B(n3070), .Y(n1967) );
NOR2XLTS U2522 ( .A(Data_array_SWR[16]), .B(n3070), .Y(n1968) );
OAI211X2TS U2523 ( .A0(intDY_EWSW[20]), .A1(n3378), .B0(n2499), .C0(n2204),
.Y(n2242) );
OAI211X2TS U2524 ( .A0(intDY_EWSW[12]), .A1(n3367), .B0(n2505), .C0(n2205),
.Y(n2233) );
OAI211X2TS U2525 ( .A0(intDY_EWSW[28]), .A1(n3377), .B0(n2491), .C0(n2195),
.Y(n2250) );
XNOR2X2TS U2526 ( .A(DMP_exp_NRM2_EW[10]), .B(n2120), .Y(n2785) );
AOI2BB2X2TS U2527 ( .B0(DmP_mant_SFG_SWR[3]), .B1(n3526), .A0N(n3075), .A1N(
DmP_mant_SFG_SWR[3]), .Y(n3035) );
AOI2BB2X2TS U2528 ( .B0(DmP_mant_SFG_SWR[7]), .B1(n3526), .A0N(n3076), .A1N(
DmP_mant_SFG_SWR[7]), .Y(n3050) );
AOI2BB2X2TS U2529 ( .B0(DmP_mant_SFG_SWR[9]), .B1(n1999), .A0N(n3076), .A1N(
DmP_mant_SFG_SWR[9]), .Y(n3098) );
OAI211XLTS U2530 ( .A0(n2642), .A1(n2670), .B0(n2641), .C0(n2640), .Y(n1636)
);
CLKINVX6TS U2531 ( .A(n3467), .Y(n2986) );
BUFX4TS U2532 ( .A(Shift_reg_FLAGS_7[0]), .Y(n3468) );
BUFX4TS U2533 ( .A(n3513), .Y(n3507) );
AOI222X1TS U2534 ( .A0(n2157), .A1(n3303), .B0(n3140), .B1(n3221), .C0(n3141), .C1(n2156), .Y(n3145) );
AOI222X1TS U2535 ( .A0(n2178), .A1(n3303), .B0(n3148), .B1(n3221), .C0(n3149), .C1(n2156), .Y(n3254) );
AOI222X4TS U2536 ( .A0(n2182), .A1(n3361), .B0(n3163), .B1(n3221), .C0(n3164), .C1(n2156), .Y(n2985) );
AOI222X1TS U2537 ( .A0(n3204), .A1(n3303), .B0(n3203), .B1(n3221), .C0(n3202), .C1(n2156), .Y(n3255) );
AOI222X1TS U2538 ( .A0(n2182), .A1(n3239), .B0(n3163), .B1(n3223), .C0(n3164), .C1(n3222), .Y(n3283) );
AOI222X4TS U2539 ( .A0(n2178), .A1(n3239), .B0(n3148), .B1(n3223), .C0(n3149), .C1(n3222), .Y(n3282) );
AOI222X4TS U2540 ( .A0(n3204), .A1(n3239), .B0(n3203), .B1(n3223), .C0(n3202), .C1(n3222), .Y(n3281) );
BUFX4TS U2541 ( .A(n2145), .Y(n3222) );
BUFX4TS U2542 ( .A(n2798), .Y(n2808) );
BUFX6TS U2543 ( .A(n2799), .Y(n2798) );
INVX3TS U2544 ( .A(n3221), .Y(n3197) );
INVX3TS U2545 ( .A(n3223), .Y(n3242) );
XOR2X1TS U2546 ( .A(DMP_SFG[11]), .B(n2990), .Y(n2991) );
AOI222X4TS U2547 ( .A0(DMP_SFG[9]), .A1(n3099), .B0(DMP_SFG[9]), .B1(n2987),
.C0(n3099), .C1(n2987), .Y(n3131) );
OAI31XLTS U2548 ( .A0(n2847), .A1(n2532), .A2(n2874), .B0(n2531), .Y(n1543)
);
INVX3TS U2549 ( .A(n2395), .Y(n2874) );
INVX3TS U2550 ( .A(n2859), .Y(n2863) );
INVX4TS U2551 ( .A(n3463), .Y(n2880) );
INVX4TS U2552 ( .A(n3295), .Y(n2858) );
BUFX3TS U2553 ( .A(n2852), .Y(n3295) );
INVX2TS U2554 ( .A(n1969), .Y(n1970) );
NAND2X2TS U2555 ( .A(n2088), .B(Shift_reg_FLAGS_7[1]), .Y(n2777) );
NAND2X1TS U2556 ( .A(Shift_reg_FLAGS_7[1]), .B(n2548), .Y(n2776) );
NOR2X1TS U2557 ( .A(Raw_mant_NRM_SWR[37]), .B(Raw_mant_NRM_SWR[38]), .Y(
n2745) );
NAND2X2TS U2558 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n3117) );
AOI22X2TS U2559 ( .A0(Data_array_SWR[30]), .A1(n3115), .B0(
Data_array_SWR[33]), .B1(n3125), .Y(n3243) );
AOI22X2TS U2560 ( .A0(Data_array_SWR[28]), .A1(n3115), .B0(
Data_array_SWR[32]), .B1(n3125), .Y(n3205) );
AOI32X1TS U2561 ( .A0(Raw_mant_NRM_SWR[39]), .A1(n2015), .A2(n3364), .B0(
Raw_mant_NRM_SWR[41]), .B1(n2015), .Y(n2016) );
NAND2BX1TS U2562 ( .AN(Raw_mant_NRM_SWR[41]), .B(n2015), .Y(n2744) );
NOR2BX2TS U2563 ( .AN(n2019), .B(Raw_mant_NRM_SWR[25]), .Y(n2046) );
NOR2X2TS U2564 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n3431), .Y(n2786) );
OAI221X1TS U2565 ( .A0(n3432), .A1(intDX_EWSW[61]), .B0(n3423), .B1(
intDX_EWSW[60]), .C0(n2465), .Y(n2468) );
OAI221XLTS U2566 ( .A0(n3333), .A1(intDX_EWSW[0]), .B0(n3414), .B1(
intDX_EWSW[8]), .C0(n2516), .Y(n2517) );
NOR2X1TS U2567 ( .A(Raw_mant_NRM_SWR[6]), .B(Raw_mant_NRM_SWR[5]), .Y(n2731)
);
OAI2BB2XLTS U2568 ( .B0(n2058), .B1(n3323), .A0N(n2728), .A1N(
Raw_mant_NRM_SWR[6]), .Y(n2022) );
AOI32X1TS U2569 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n2728), .A2(n3323), .B0(
Raw_mant_NRM_SWR[5]), .B1(n2728), .Y(n2017) );
NOR2BX2TS U2570 ( .AN(n2018), .B(Raw_mant_NRM_SWR[43]), .Y(n2075) );
NOR3X2TS U2571 ( .A(Raw_mant_NRM_SWR[28]), .B(Raw_mant_NRM_SWR[29]), .C(
n2748), .Y(n2045) );
AOI211X1TS U2572 ( .A0(n2060), .A1(Raw_mant_NRM_SWR[16]), .B0(n2756), .C0(
n2740), .Y(n2061) );
OAI221XLTS U2573 ( .A0(n3335), .A1(intDX_EWSW[17]), .B0(n3418), .B1(
intDX_EWSW[24]), .C0(n2501), .Y(n2502) );
OAI221X1TS U2574 ( .A0(n3331), .A1(intDX_EWSW[3]), .B0(n3412), .B1(
intDX_EWSW[2]), .C0(n2515), .Y(n2518) );
OAI221X1TS U2575 ( .A0(n3337), .A1(intDX_EWSW[25]), .B0(n3421), .B1(
intDX_EWSW[32]), .C0(n2494), .Y(n2495) );
AOI211XLTS U2576 ( .A0(intDX_EWSW[16]), .A1(n3425), .B0(n2237), .C0(n2243),
.Y(n2234) );
OAI221X1TS U2577 ( .A0(n3408), .A1(intDX_EWSW[10]), .B0(n3415), .B1(
intDX_EWSW[12]), .C0(n2507), .Y(n2510) );
OAI221X1TS U2578 ( .A0(n3411), .A1(intDX_EWSW[21]), .B0(n3422), .B1(
intDX_EWSW[48]), .C0(n2500), .Y(n2503) );
AOI211X1TS U2579 ( .A0(intDX_EWSW[52]), .A1(n3434), .B0(n2187), .C0(n2302),
.Y(n2304) );
AOI221X1TS U2580 ( .A0(n3434), .A1(intDX_EWSW[52]), .B0(intDX_EWSW[53]),
.B1(n3313), .C0(n2461), .Y(n2473) );
AOI222X1TS U2581 ( .A0(n2435), .A1(intDX_EWSW[52]), .B0(DMP_EXP_EWSW[52]),
.B1(n1933), .C0(intDY_EWSW[52]), .C1(n1827), .Y(n2338) );
NOR3X1TS U2582 ( .A(Raw_mant_NRM_SWR[40]), .B(Raw_mant_NRM_SWR[39]), .C(
n2744), .Y(n2013) );
NOR2X2TS U2583 ( .A(Raw_mant_NRM_SWR[40]), .B(Raw_mant_NRM_SWR[39]), .Y(
n2742) );
AOI211X2TS U2584 ( .A0(intDX_EWSW[44]), .A1(n3445), .B0(n2270), .C0(n2279),
.Y(n2277) );
AOI21X2TS U2585 ( .A0(Data_array_SWR[17]), .A1(n3125), .B0(n3092), .Y(n3168)
);
OAI31X1TS U2586 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n2741), .A2(
Raw_mant_NRM_SWR[24]), .B0(n2046), .Y(n2051) );
NOR2X1TS U2587 ( .A(Raw_mant_NRM_SWR[47]), .B(n2012), .Y(n2018) );
OAI221XLTS U2588 ( .A0(n3334), .A1(intDX_EWSW[5]), .B0(n3420), .B1(
intDX_EWSW[28]), .C0(n2514), .Y(n2519) );
NOR3X2TS U2589 ( .A(Raw_mant_NRM_SWR[19]), .B(Raw_mant_NRM_SWR[20]), .C(
n2067), .Y(n2733) );
AO22XLTS U2590 ( .A0(n2792), .A1(n2453), .B0(n2877), .B1(n2790), .Y(n1978)
);
AO22XLTS U2591 ( .A0(n2792), .A1(n2877), .B0(n2859), .B1(n2790), .Y(n1991)
);
OAI21XLTS U2592 ( .A0(intDX_EWSW[1]), .A1(n3449), .B0(intDX_EWSW[0]), .Y(
n2208) );
NOR2XLTS U2593 ( .A(Raw_mant_NRM_SWR[46]), .B(Raw_mant_NRM_SWR[45]), .Y(
n2034) );
OAI21XLTS U2594 ( .A0(intDY_EWSW[33]), .A1(n3373), .B0(intDY_EWSW[32]), .Y(
n2287) );
NOR2XLTS U2595 ( .A(Raw_mant_NRM_SWR[52]), .B(Raw_mant_NRM_SWR[51]), .Y(
n2036) );
NOR2XLTS U2596 ( .A(n2270), .B(intDX_EWSW[44]), .Y(n2271) );
OAI21XLTS U2597 ( .A0(intDY_EWSW[29]), .A1(n3383), .B0(intDY_EWSW[28]), .Y(
n2194) );
OAI21XLTS U2598 ( .A0(n3457), .A1(n3056), .B0(n3055), .Y(n3057) );
NOR2XLTS U2599 ( .A(n2115), .B(n2783), .Y(n2118) );
INVX2TS U2600 ( .A(n2035), .Y(n2765) );
OAI21XLTS U2601 ( .A0(n3456), .A1(n3117), .B0(n3103), .Y(n3104) );
OAI211XLTS U2602 ( .A0(n3168), .A1(n2127), .B0(n3094), .C0(n3093), .Y(n3095)
);
NOR2XLTS U2603 ( .A(n2326), .B(n1933), .Y(n2327) );
OAI2BB1X1TS U2604 ( .A0N(Shift_amount_SHT1_EWR[1]), .A1N(n1969), .B0(n2776),
.Y(n2533) );
OAI21XLTS U2605 ( .A0(DmP_EXP_EWSW[55]), .A1(n3354), .B0(n2834), .Y(n2831)
);
OAI21XLTS U2606 ( .A0(n3021), .A1(DMP_SFG[0]), .B0(n3034), .Y(n3022) );
OAI21XLTS U2607 ( .A0(n3445), .A1(n2871), .B0(n2374), .Y(n1243) );
OAI21XLTS U2608 ( .A0(n3437), .A1(n2871), .B0(n2375), .Y(n1257) );
OAI21XLTS U2609 ( .A0(n3452), .A1(n2872), .B0(n2331), .Y(n1271) );
OAI21XLTS U2610 ( .A0(n3347), .A1(n2872), .B0(n2363), .Y(n1285) );
OAI21XLTS U2611 ( .A0(n3340), .A1(n2451), .B0(n2406), .Y(n1549) );
OAI21XLTS U2612 ( .A0(n3343), .A1(n2451), .B0(n2438), .Y(n1567) );
OAI21XLTS U2613 ( .A0(n3338), .A1(n2433), .B0(n2421), .Y(n1581) );
OAI21XLTS U2614 ( .A0(n3410), .A1(n2433), .B0(n2417), .Y(n1595) );
OAI21XLTS U2615 ( .A0(n3333), .A1(n2874), .B0(n2392), .Y(n1608) );
BUFX4TS U2616 ( .A(n3467), .Y(n3037) );
INVX4TS U2617 ( .A(n3467), .Y(n3075) );
INVX4TS U2618 ( .A(n3295), .Y(n3292) );
NOR2XLTS U2619 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n1998) );
AOI32X4TS U2620 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n1998), .B1(n3431), .Y(n2792)
);
BUFX4TS U2621 ( .A(n2386), .Y(n2529) );
BUFX3TS U2622 ( .A(n3463), .Y(n2877) );
INVX2TS U2623 ( .A(n2792), .Y(n2790) );
BUFX4TS U2624 ( .A(n3527), .Y(n3088) );
AOI2BB2XLTS U2625 ( .B0(n1906), .B1(n2986), .A0N(n2986), .A1N(n1906), .Y(
n2972) );
AOI2BB2XLTS U2626 ( .B0(n1907), .B1(n2986), .A0N(n2986), .A1N(n1907), .Y(
n2969) );
AOI2BB2XLTS U2627 ( .B0(n1908), .B1(n2986), .A0N(n2986), .A1N(n1908), .Y(
n2966) );
AOI2BB2XLTS U2628 ( .B0(n1909), .B1(n2986), .A0N(n2986), .A1N(n1909), .Y(
n2963) );
AOI2BB2XLTS U2629 ( .B0(n1910), .B1(n2986), .A0N(n2986), .A1N(n1910), .Y(
n2003) );
INVX4TS U2630 ( .A(n3467), .Y(n3076) );
AOI2BB2XLTS U2631 ( .B0(DmP_mant_SFG_SWR[45]), .B1(n3076), .A0N(n1999),
.A1N(DmP_mant_SFG_SWR[45]), .Y(n2960) );
AOI2BB2XLTS U2632 ( .B0(n1911), .B1(n3075), .A0N(n2986), .A1N(n1911), .Y(
n2957) );
AOI2BB2XLTS U2633 ( .B0(n1912), .B1(n3076), .A0N(n2986), .A1N(n1912), .Y(
n2954) );
INVX4TS U2634 ( .A(n3467), .Y(n1999) );
AOI22X1TS U2635 ( .A0(n1999), .A1(DmP_mant_SFG_SWR[42]), .B0(n1985), .B1(
n3037), .Y(n2009) );
AOI22X1TS U2636 ( .A0(n3075), .A1(DmP_mant_SFG_SWR[41]), .B0(n1984), .B1(
n3037), .Y(n2951) );
AOI22X1TS U2637 ( .A0(n3076), .A1(DmP_mant_SFG_SWR[40]), .B0(n1983), .B1(
n3037), .Y(n2006) );
AOI22X1TS U2638 ( .A0(n1999), .A1(DmP_mant_SFG_SWR[39]), .B0(n1982), .B1(
n3037), .Y(n2948) );
AOI22X1TS U2639 ( .A0(DmP_mant_SFG_SWR[38]), .A1(n3526), .B0(n3037), .B1(
n1981), .Y(n2945) );
AOI22X1TS U2640 ( .A0(DmP_mant_SFG_SWR[37]), .A1(n3526), .B0(n3037), .B1(
n1979), .Y(n2942) );
AOI22X1TS U2641 ( .A0(DmP_mant_SFG_SWR[36]), .A1(n3526), .B0(n3037), .B1(
n1977), .Y(n2939) );
AOI22X1TS U2642 ( .A0(DmP_mant_SFG_SWR[35]), .A1(n3526), .B0(n3037), .B1(
n1976), .Y(n2184) );
AOI22X1TS U2643 ( .A0(DmP_mant_SFG_SWR[34]), .A1(n3526), .B0(n3037), .B1(
n1975), .Y(n2936) );
AOI22X1TS U2644 ( .A0(DmP_mant_SFG_SWR[33]), .A1(n3526), .B0(n3037), .B1(
n1974), .Y(n2933) );
AOI22X1TS U2645 ( .A0(DmP_mant_SFG_SWR[32]), .A1(n3526), .B0(n3037), .B1(
n1973), .Y(n2930) );
AOI22X1TS U2646 ( .A0(DmP_mant_SFG_SWR[22]), .A1(n3526), .B0(n3467), .B1(
n1972), .Y(n2905) );
AOI22X1TS U2647 ( .A0(DmP_mant_SFG_SWR[21]), .A1(n3075), .B0(n3037), .B1(
n1971), .Y(n2902) );
AOI22X1TS U2648 ( .A0(DmP_mant_SFG_SWR[20]), .A1(n3076), .B0(n3467), .B1(
n1994), .Y(n2899) );
AOI22X1TS U2649 ( .A0(DmP_mant_SFG_SWR[19]), .A1(n1999), .B0(n3467), .B1(
n1993), .Y(n2099) );
AOI22X1TS U2650 ( .A0(DmP_mant_SFG_SWR[18]), .A1(n3075), .B0(n3467), .B1(
n1992), .Y(n2096) );
AOI22X1TS U2651 ( .A0(DmP_mant_SFG_SWR[17]), .A1(n3076), .B0(n3037), .B1(
n1990), .Y(n2896) );
AOI22X1TS U2652 ( .A0(DmP_mant_SFG_SWR[16]), .A1(n1999), .B0(n3037), .B1(
n1989), .Y(n2893) );
AOI22X1TS U2653 ( .A0(n3075), .A1(DmP_mant_SFG_SWR[15]), .B0(n1988), .B1(
n3037), .Y(n2890) );
AOI22X1TS U2654 ( .A0(n3076), .A1(DmP_mant_SFG_SWR[14]), .B0(n1987), .B1(
n3037), .Y(n2887) );
AOI22X2TS U2655 ( .A0(DmP_mant_SFG_SWR[12]), .A1(n3526), .B0(n3467), .B1(
n1986), .Y(n3133) );
OAI2BB1X1TS U2656 ( .A0N(n1896), .A1N(DMP_SFG[11]), .B0(n2000), .Y(n2886) );
BUFX4TS U2657 ( .A(n3527), .Y(n3134) );
NOR2X1TS U2658 ( .A(Shift_reg_FLAGS_7[1]), .B(n2882), .Y(n2063) );
BUFX4TS U2659 ( .A(n2815), .Y(n2712) );
NOR2X2TS U2660 ( .A(Shift_reg_FLAGS_7[1]), .B(n2859), .Y(n2818) );
AOI22X1TS U2661 ( .A0(n2712), .A1(shift_value_SHT2_EWR[3]), .B0(n2818), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n2033) );
NOR2X1TS U2662 ( .A(Raw_mant_NRM_SWR[18]), .B(Raw_mant_NRM_SWR[17]), .Y(
n2732) );
NOR2X1TS U2663 ( .A(Raw_mant_NRM_SWR[50]), .B(Raw_mant_NRM_SWR[49]), .Y(
n2035) );
NAND2X1TS U2664 ( .A(n2035), .B(n2763), .Y(n2011) );
NAND2X2TS U2665 ( .A(n2045), .B(n3362), .Y(n2026) );
NAND2X1TS U2666 ( .A(Raw_mant_NRM_SWR[21]), .B(n2014), .Y(n2751) );
OAI211X1TS U2667 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n2017), .B0(n2751), .C0(
n2016), .Y(n2074) );
AOI32X1TS U2668 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n2727), .A2(n3311), .B0(
Raw_mant_NRM_SWR[9]), .B1(n2727), .Y(n2020) );
NAND2X1TS U2669 ( .A(Raw_mant_NRM_SWR[43]), .B(n2018), .Y(n2041) );
AOI21X1TS U2670 ( .A0(n2024), .A1(Raw_mant_NRM_SWR[23]), .B0(n2021), .Y(
n2086) );
OAI31X1TS U2671 ( .A0(Raw_mant_NRM_SWR[42]), .A1(n2022), .A2(
Raw_mant_NRM_SWR[40]), .B0(n2075), .Y(n2769) );
NOR3BX1TS U2672 ( .AN(n2080), .B(n2023), .C(Raw_mant_NRM_SWR[47]), .Y(n2030)
);
OAI2BB1X1TS U2673 ( .A0N(n2025), .A1N(Raw_mant_NRM_SWR[30]), .B0(n2768), .Y(
n2757) );
OAI2BB2XLTS U2674 ( .B0(n3454), .B1(n2026), .A0N(Raw_mant_NRM_SWR[24]),
.A1N(n2046), .Y(n2029) );
OAI22X1TS U2675 ( .A0(n3311), .A1(n2055), .B0(n3460), .B1(n2027), .Y(n2028)
);
NOR4X1TS U2676 ( .A(n2030), .B(n2757), .C(n2029), .D(n2028), .Y(n2031) );
OAI21X1TS U2677 ( .A0(Raw_mant_NRM_SWR[19]), .A1(Raw_mant_NRM_SWR[20]), .B0(
n2759), .Y(n2050) );
OAI21X1TS U2678 ( .A0(n2074), .A1(n2032), .B0(Shift_reg_FLAGS_7[1]), .Y(
n2758) );
NAND2X1TS U2679 ( .A(n2033), .B(n2758), .Y(n1629) );
NAND2X1TS U2680 ( .A(n2065), .B(Raw_mant_NRM_SWR[28]), .Y(n2766) );
OR2X1TS U2681 ( .A(Raw_mant_NRM_SWR[54]), .B(Raw_mant_NRM_SWR[53]), .Y(n2038) );
OAI32X1TS U2682 ( .A0(n2038), .A1(n2037), .A2(n2765), .B0(n2036), .B1(n2038),
.Y(n2039) );
INVX2TS U2683 ( .A(n2039), .Y(n2040) );
INVX2TS U2684 ( .A(n2042), .Y(n2062) );
OR2X1TS U2685 ( .A(Raw_mant_NRM_SWR[32]), .B(Raw_mant_NRM_SWR[31]), .Y(n2044) );
AOI22X1TS U2686 ( .A0(Raw_mant_NRM_SWR[27]), .A1(n2045), .B0(n2761), .B1(
n2044), .Y(n2052) );
INVX2TS U2687 ( .A(n2084), .Y(n2753) );
NOR4X2TS U2688 ( .A(Raw_mant_NRM_SWR[1]), .B(Raw_mant_NRM_SWR[2]), .C(n2753),
.D(n3329), .Y(n2741) );
NOR2XLTS U2689 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[3]), .Y(n2059)
);
NAND2X1TS U2690 ( .A(Raw_mant_NRM_SWR[15]), .B(n2053), .Y(n2081) );
AOI32X1TS U2691 ( .A0(n2081), .A1(n3308), .A2(n3327), .B0(n2771), .B1(n2081),
.Y(n2054) );
INVX2TS U2692 ( .A(n2054), .Y(n2057) );
OAI211X1TS U2693 ( .A0(n2059), .A1(n2058), .B0(n2057), .C0(n2056), .Y(n2740)
);
BUFX3TS U2694 ( .A(n2063), .Y(n2811) );
NOR2BX4TS U2695 ( .AN(n2533), .B(n2811), .Y(n2554) );
OR2X1TS U2696 ( .A(Raw_mant_NRM_SWR[28]), .B(n2748), .Y(n2072) );
NOR3BX1TS U2697 ( .AN(Raw_mant_NRM_SWR[31]), .B(Raw_mant_NRM_SWR[32]), .C(
n2064), .Y(n2069) );
AOI22X1TS U2698 ( .A0(n1950), .A1(n2066), .B0(n2065), .B1(
Raw_mant_NRM_SWR[29]), .Y(n2747) );
OAI31X1TS U2699 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n3398), .A2(n2067), .B0(
n2747), .Y(n2068) );
AOI211X1TS U2700 ( .A0(Raw_mant_NRM_SWR[47]), .A1(n2080), .B0(n2069), .C0(
n2068), .Y(n2071) );
NAND2X1TS U2701 ( .A(Raw_mant_NRM_SWR[13]), .B(n2070), .Y(n2737) );
AOI211X1TS U2702 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n2726), .B0(n2074), .C0(
n2073), .Y(n2770) );
NAND4XLTS U2703 ( .A(n2742), .B(n2075), .C(Raw_mant_NRM_SWR[37]), .D(n3365),
.Y(n2078) );
AOI21X1TS U2704 ( .A0(Raw_mant_NRM_SWR[49]), .A1(n3387), .B0(
Raw_mant_NRM_SWR[51]), .Y(n2076) );
AOI2BB1XLTS U2705 ( .A0N(Raw_mant_NRM_SWR[52]), .A1N(n2076), .B0(
Raw_mant_NRM_SWR[53]), .Y(n2077) );
OAI22X1TS U2706 ( .A0(Raw_mant_NRM_SWR[38]), .A1(n2078), .B0(
Raw_mant_NRM_SWR[54]), .B1(n2077), .Y(n2079) );
AOI31XLTS U2707 ( .A0(Raw_mant_NRM_SWR[45]), .A1(n2080), .A2(n3376), .B0(
n2079), .Y(n2082) );
INVX2TS U2708 ( .A(n2777), .Y(n2087) );
INVX4TS U2709 ( .A(n2777), .Y(n2667) );
NAND2X1TS U2710 ( .A(n1926), .B(n1969), .Y(n2549) );
AOI22X1TS U2711 ( .A0(Raw_mant_NRM_SWR[51]), .A1(n2667), .B0(n2623), .B1(
DmP_mant_SHT1_SW[1]), .Y(n2090) );
NOR2X2TS U2712 ( .A(n1969), .B(n2088), .Y(n2553) );
BUFX3TS U2713 ( .A(n2553), .Y(n2631) );
NOR2X1TS U2714 ( .A(Shift_reg_FLAGS_7[1]), .B(n1926), .Y(n2557) );
INVX2TS U2715 ( .A(n2557), .Y(n2648) );
AOI22X1TS U2716 ( .A0(Raw_mant_NRM_SWR[52]), .A1(n2631), .B0(n2644), .B1(
n1927), .Y(n2089) );
NAND2X1TS U2717 ( .A(n2090), .B(n2089), .Y(n2590) );
AOI22X1TS U2718 ( .A0(n2815), .A1(Data_array_SWR[0]), .B0(n2554), .B1(n2590),
.Y(n2092) );
AOI22X1TS U2719 ( .A0(Raw_mant_NRM_SWR[54]), .A1(n2631), .B0(
Raw_mant_NRM_SWR[53]), .B1(n1914), .Y(n2091) );
NAND2X1TS U2720 ( .A(n2092), .B(n2091), .Y(n1631) );
BUFX3TS U2721 ( .A(n3499), .Y(n3493) );
BUFX3TS U2722 ( .A(n3518), .Y(n3520) );
BUFX3TS U2723 ( .A(n3485), .Y(n3512) );
BUFX3TS U2724 ( .A(n3516), .Y(n3513) );
BUFX3TS U2725 ( .A(n3495), .Y(n3515) );
BUFX3TS U2726 ( .A(n3519), .Y(n3481) );
BUFX3TS U2727 ( .A(n3512), .Y(n3504) );
BUFX3TS U2728 ( .A(n3512), .Y(n3469) );
BUFX3TS U2729 ( .A(n3530), .Y(n3502) );
BUFX3TS U2730 ( .A(n3525), .Y(n3474) );
BUFX3TS U2731 ( .A(n3481), .Y(n3476) );
BUFX3TS U2732 ( .A(n3491), .Y(n3473) );
BUFX3TS U2733 ( .A(n3520), .Y(n3471) );
BUFX3TS U2734 ( .A(n3473), .Y(n3470) );
AO22XLTS U2735 ( .A0(n1970), .A1(ZERO_FLAG_NRM), .B0(n1969), .B1(
ZERO_FLAG_SHT1SHT2), .Y(n1215) );
AO22XLTS U2736 ( .A0(n1970), .A1(SIGN_FLAG_NRM), .B0(n1969), .B1(
SIGN_FLAG_SHT1SHT2), .Y(n1206) );
BUFX4TS U2737 ( .A(n3527), .Y(n2921) );
AO22XLTS U2738 ( .A0(n1825), .A1(DMP_SFG[57]), .B0(n2921), .B1(
DMP_exp_NRM_EW[5]), .Y(n1358) );
AO22XLTS U2739 ( .A0(n3090), .A1(DMP_SFG[56]), .B0(n2921), .B1(
DMP_exp_NRM_EW[4]), .Y(n1363) );
AO22XLTS U2740 ( .A0(n1825), .A1(ZERO_FLAG_SFG), .B0(n2921), .B1(
ZERO_FLAG_NRM), .Y(n1216) );
AO22XLTS U2741 ( .A0(n3090), .A1(DMP_SFG[59]), .B0(n2921), .B1(
DMP_exp_NRM_EW[7]), .Y(n1348) );
AO22XLTS U2742 ( .A0(n3136), .A1(DMP_SFG[60]), .B0(n2921), .B1(
DMP_exp_NRM_EW[8]), .Y(n1343) );
AO22XLTS U2743 ( .A0(n1825), .A1(DMP_SFG[58]), .B0(n2921), .B1(
DMP_exp_NRM_EW[6]), .Y(n1353) );
AO22XLTS U2744 ( .A0(n3024), .A1(DMP_SFG[62]), .B0(n2921), .B1(
DMP_exp_NRM_EW[10]), .Y(n1333) );
AO22XLTS U2745 ( .A0(n1825), .A1(DMP_SFG[55]), .B0(n2921), .B1(
DMP_exp_NRM_EW[3]), .Y(n1368) );
AO22XLTS U2746 ( .A0(n3024), .A1(SIGN_FLAG_SFG), .B0(n2921), .B1(
SIGN_FLAG_NRM), .Y(n1207) );
AOI2BB2X1TS U2747 ( .B0(n1915), .B1(n3075), .A0N(n2986), .A1N(n1915), .Y(
n3087) );
OAI211XLTS U2748 ( .A0(DMP_SFG[5]), .A1(n3050), .B0(n1932), .C0(n3087), .Y(
n2093) );
OAI2BB1X1TS U2749 ( .A0N(n3050), .A1N(DMP_SFG[5]), .B0(n2093), .Y(n3074) );
AOI2BB2X1TS U2750 ( .B0(DmP_mant_SFG_SWR[8]), .B1(n1999), .A0N(n3075), .A1N(
DmP_mant_SFG_SWR[8]), .Y(n3096) );
AO22XLTS U2751 ( .A0(n3527), .A1(Raw_mant_NRM_SWR[8]), .B0(n3136), .B1(n2094), .Y(n1131) );
AO22XLTS U2752 ( .A0(n3134), .A1(Raw_mant_NRM_SWR[18]), .B0(n3136), .B1(
n2097), .Y(n1200) );
AO22XLTS U2753 ( .A0(n3134), .A1(Raw_mant_NRM_SWR[19]), .B0(n3136), .B1(
n2100), .Y(n1199) );
AO22XLTS U2754 ( .A0(n3134), .A1(Raw_mant_NRM_SWR[26]), .B0(n1825), .B1(
n2103), .Y(n1192) );
INVX2TS U2755 ( .A(DP_OP_15J75_123_4372_n6), .Y(n2104) );
NAND2X1TS U2756 ( .A(n3405), .B(n2104), .Y(n2110) );
INVX2TS U2757 ( .A(n2110), .Y(n2105) );
NAND2X1TS U2758 ( .A(n3426), .B(n2105), .Y(n2113) );
NOR2XLTS U2759 ( .A(n2779), .B(exp_rslt_NRM2_EW1[1]), .Y(n2108) );
INVX2TS U2760 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n2107) );
INVX2TS U2761 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n2106) );
NAND4BXLTS U2762 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n2108), .C(n2107), .D(n2106), .Y(n2109) );
NOR2XLTS U2763 ( .A(n2109), .B(exp_rslt_NRM2_EW1[5]), .Y(n2112) );
XNOR2X1TS U2764 ( .A(DMP_exp_NRM2_EW[7]), .B(n2110), .Y(n2781) );
INVX2TS U2765 ( .A(n2781), .Y(n2124) );
INVX2TS U2766 ( .A(n2780), .Y(n2111) );
NAND4BXLTS U2767 ( .AN(n2782), .B(n2112), .C(n2124), .D(n2111), .Y(n2115) );
INVX2TS U2768 ( .A(n2113), .Y(n2114) );
NAND2X1TS U2769 ( .A(n3436), .B(n2114), .Y(n2116) );
INVX2TS U2770 ( .A(n2116), .Y(n2117) );
NAND2X1TS U2771 ( .A(n3435), .B(n2117), .Y(n2120) );
NOR2BX1TS U2772 ( .AN(n2118), .B(n2785), .Y(n2119) );
INVX2TS U2773 ( .A(n2119), .Y(n2778) );
INVX2TS U2774 ( .A(n2778), .Y(n2884) );
INVX2TS U2775 ( .A(n2120), .Y(n2121) );
CLKAND2X2TS U2776 ( .A(n3459), .B(n2121), .Y(n2126) );
NAND4XLTS U2777 ( .A(exp_rslt_NRM2_EW1[3]), .B(exp_rslt_NRM2_EW1[2]), .C(
n2779), .D(exp_rslt_NRM2_EW1[1]), .Y(n2122) );
NAND4BXLTS U2778 ( .AN(n2122), .B(n2780), .C(exp_rslt_NRM2_EW1[5]), .D(
exp_rslt_NRM2_EW1[4]), .Y(n2123) );
NOR3BXLTS U2779 ( .AN(n2782), .B(n2124), .C(n2123), .Y(n2125) );
NAND4XLTS U2780 ( .A(n2783), .B(n2126), .C(n2785), .D(n2125), .Y(n2883) );
NAND2X1TS U2781 ( .A(n3468), .B(n2883), .Y(n2876) );
INVX4TS U2782 ( .A(n2146), .Y(n3172) );
NAND2X1TS U2783 ( .A(shift_value_SHT2_EWR[2]), .B(n3386), .Y(n2128) );
NOR2X1TS U2784 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n2158) );
INVX2TS U2785 ( .A(n2158), .Y(n3056) );
AOI222X4TS U2786 ( .A0(Data_array_SWR[28]), .A1(n2159), .B0(
Data_array_SWR[25]), .B1(n3115), .C0(Data_array_SWR[32]), .C1(n3080),
.Y(n3156) );
NOR2X2TS U2787 ( .A(n3363), .B(shift_value_SHT2_EWR[5]), .Y(n3232) );
NAND2BX2TS U2788 ( .AN(shift_value_SHT2_EWR[5]), .B(n3363), .Y(n2152) );
NOR2BX1TS U2789 ( .AN(n3080), .B(n2152), .Y(n2147) );
BUFX3TS U2790 ( .A(n2147), .Y(n3198) );
NOR2X1TS U2791 ( .A(n3056), .B(n2152), .Y(n2996) );
BUFX3TS U2792 ( .A(n2996), .Y(n3229) );
AOI22X1TS U2793 ( .A0(n1949), .A1(n3198), .B0(Data_array_SWR[16]), .B1(n3229), .Y(n2130) );
NOR2X1TS U2794 ( .A(n2152), .B(n3117), .Y(n2135) );
BUFX3TS U2795 ( .A(n2135), .Y(n3180) );
NOR2X1TS U2796 ( .A(n2152), .B(n2128), .Y(n2136) );
CLKBUFX3TS U2797 ( .A(n2136), .Y(n3122) );
AOI22X1TS U2798 ( .A0(Data_array_SWR[21]), .A1(n3180), .B0(n1955), .B1(n3122), .Y(n2129) );
OAI211X1TS U2799 ( .A0(n3156), .A1(n2127), .B0(n2130), .C0(n2129), .Y(n3268)
);
AO22XLTS U2800 ( .A0(n3172), .A1(n3268), .B0(final_result_ieee[25]), .B1(
n3240), .Y(n1115) );
AOI22X1TS U2801 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n2786), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n3332), .Y(n2789) );
NAND2X1TS U2802 ( .A(beg_OP), .B(n2789), .Y(n2131) );
INVX2TS U2803 ( .A(n2131), .Y(n2799) );
BUFX4TS U2804 ( .A(n2799), .Y(n2793) );
AO22XLTS U2805 ( .A0(n2793), .A1(Data_X[42]), .B0(n2795), .B1(intDX_EWSW[42]), .Y(n1773) );
AO22XLTS U2806 ( .A0(n2793), .A1(Data_X[41]), .B0(n2795), .B1(intDX_EWSW[41]), .Y(n1774) );
AO22XLTS U2807 ( .A0(n2798), .A1(Data_X[34]), .B0(n2795), .B1(intDX_EWSW[34]), .Y(n1781) );
AO22XLTS U2808 ( .A0(n2793), .A1(Data_X[43]), .B0(n2795), .B1(intDX_EWSW[43]), .Y(n1772) );
AO22XLTS U2809 ( .A0(n2798), .A1(Data_X[35]), .B0(n2795), .B1(intDX_EWSW[35]), .Y(n1780) );
AO22XLTS U2810 ( .A0(n2798), .A1(Data_X[36]), .B0(n2795), .B1(intDX_EWSW[36]), .Y(n1779) );
AO22XLTS U2811 ( .A0(n2803), .A1(intDY_EWSW[55]), .B0(n2793), .B1(Data_Y[55]), .Y(n1694) );
AO22XLTS U2812 ( .A0(n2803), .A1(intDY_EWSW[40]), .B0(n2794), .B1(Data_Y[40]), .Y(n1709) );
AO22XLTS U2813 ( .A0(n2806), .A1(intDY_EWSW[57]), .B0(n2793), .B1(Data_Y[57]), .Y(n1692) );
AO22XLTS U2814 ( .A0(n2806), .A1(intDY_EWSW[58]), .B0(n2793), .B1(Data_Y[58]), .Y(n1691) );
AO22XLTS U2815 ( .A0(n2806), .A1(intDY_EWSW[53]), .B0(n2793), .B1(Data_Y[53]), .Y(n1696) );
AO22XLTS U2816 ( .A0(n3134), .A1(Raw_mant_NRM_SWR[27]), .B0(n3024), .B1(
n2134), .Y(n1191) );
AO22XLTS U2817 ( .A0(n2803), .A1(intDY_EWSW[41]), .B0(n2808), .B1(Data_Y[41]), .Y(n1708) );
AO22XLTS U2818 ( .A0(n2803), .A1(intDY_EWSW[42]), .B0(n2808), .B1(Data_Y[42]), .Y(n1707) );
AOI222X4TS U2819 ( .A0(Data_array_SWR[30]), .A1(n2159), .B0(n1943), .B1(
n3115), .C0(Data_array_SWR[33]), .C1(n3080), .Y(n3169) );
NAND2X2TS U2820 ( .A(n3363), .B(shift_value_SHT2_EWR[5]), .Y(n3201) );
BUFX3TS U2821 ( .A(n2135), .Y(n3228) );
AOI22X1TS U2822 ( .A0(Data_array_SWR[11]), .A1(n3198), .B0(
Data_array_SWR[14]), .B1(n3228), .Y(n2138) );
BUFX3TS U2823 ( .A(n2136), .Y(n3227) );
AOI22X1TS U2824 ( .A0(Data_array_SWR[9]), .A1(n3227), .B0(n1944), .B1(n3229),
.Y(n2137) );
OAI211X1TS U2825 ( .A0(n3169), .A1(n3201), .B0(n2138), .C0(n2137), .Y(n2182)
);
AOI22X1TS U2826 ( .A0(Data_array_SWR[30]), .A1(n3080), .B0(
Data_array_SWR[33]), .B1(n2142), .Y(n2140) );
BUFX4TS U2827 ( .A(n2159), .Y(n3125) );
INVX4TS U2828 ( .A(n3056), .Y(n3189) );
AOI22X1TS U2829 ( .A0(n1943), .A1(n3125), .B0(Data_array_SWR[23]), .B1(n3189), .Y(n2139) );
NAND2X2TS U2830 ( .A(n2140), .B(n2139), .Y(n3163) );
NOR2XLTS U2831 ( .A(n2152), .B(left_right_SHT2), .Y(n2141) );
BUFX3TS U2832 ( .A(n2141), .Y(n3223) );
BUFX3TS U2833 ( .A(n2142), .Y(n3054) );
BUFX4TS U2834 ( .A(n3080), .Y(n3188) );
AOI22X1TS U2835 ( .A0(Data_array_SWR[23]), .A1(n3054), .B0(n1936), .B1(n3188), .Y(n2144) );
AOI22X1TS U2836 ( .A0(n1952), .A1(n3125), .B0(Data_array_SWR[17]), .B1(n3189), .Y(n2143) );
NAND2X1TS U2837 ( .A(n2144), .B(n2143), .Y(n3164) );
NOR2XLTS U2838 ( .A(n3361), .B(n2127), .Y(n2145) );
OAI2BB2XLTS U2839 ( .B0(n3283), .B1(n2146), .A0N(final_result_ieee[39]),
.A1N(n1996), .Y(n1106) );
AOI222X4TS U2840 ( .A0(n1948), .A1(n3188), .B0(Data_array_SWR[29]), .B1(
n2159), .C0(Data_array_SWR[26]), .C1(n3189), .Y(n3137) );
BUFX3TS U2841 ( .A(n2147), .Y(n3226) );
AOI22X1TS U2842 ( .A0(n1945), .A1(n3229), .B0(n1958), .B1(n3226), .Y(n2149)
);
AOI22X1TS U2843 ( .A0(Data_array_SWR[8]), .A1(n3227), .B0(Data_array_SWR[13]), .B1(n3228), .Y(n2148) );
OAI211X1TS U2844 ( .A0(n3137), .A1(n3201), .B0(n2149), .C0(n2148), .Y(n2157)
);
AOI22X1TS U2845 ( .A0(Data_array_SWR[34]), .A1(n2142), .B0(
Data_array_SWR[31]), .B1(n3188), .Y(n2151) );
AOI22X1TS U2846 ( .A0(Data_array_SWR[27]), .A1(n2159), .B0(
Data_array_SWR[24]), .B1(n3115), .Y(n2150) );
NAND2X2TS U2847 ( .A(n2151), .B(n2150), .Y(n3140) );
NOR2XLTS U2848 ( .A(n3361), .B(n2152), .Y(n2153) );
BUFX3TS U2849 ( .A(n2153), .Y(n3221) );
AOI22X1TS U2850 ( .A0(Data_array_SWR[22]), .A1(n2142), .B0(n1934), .B1(n3080), .Y(n2155) );
AOI22X1TS U2851 ( .A0(n1954), .A1(n2159), .B0(n1956), .B1(n3115), .Y(n2154)
);
NAND2X1TS U2852 ( .A(n2155), .B(n2154), .Y(n3141) );
OAI2BB2XLTS U2853 ( .B0(n3145), .B1(n2146), .A0N(final_result_ieee[10]),
.A1N(n1996), .Y(n1121) );
OAI2BB2XLTS U2854 ( .B0(n3284), .B1(n2146), .A0N(final_result_ieee[40]),
.A1N(n1996), .Y(n1120) );
AOI222X4TS U2855 ( .A0(Data_array_SWR[34]), .A1(n3080), .B0(
Data_array_SWR[31]), .B1(n2159), .C0(Data_array_SWR[27]), .C1(n2158),
.Y(n3158) );
AOI22X1TS U2856 ( .A0(n1947), .A1(n3229), .B0(n1959), .B1(n3226), .Y(n2161)
);
AOI22X1TS U2857 ( .A0(Data_array_SWR[15]), .A1(n3180), .B0(n1951), .B1(n3227), .Y(n2160) );
OAI211X1TS U2858 ( .A0(n3158), .A1(n3201), .B0(n2161), .C0(n2160), .Y(n2178)
);
AOI22X1TS U2859 ( .A0(n1948), .A1(n3054), .B0(Data_array_SWR[29]), .B1(n3188), .Y(n2163) );
AOI22X1TS U2860 ( .A0(Data_array_SWR[26]), .A1(n2159), .B0(
Data_array_SWR[22]), .B1(n3189), .Y(n2162) );
NAND2X2TS U2861 ( .A(n2163), .B(n2162), .Y(n3148) );
AOI22X1TS U2862 ( .A0(Data_array_SWR[24]), .A1(n3054), .B0(n1935), .B1(n3080), .Y(n2165) );
AOI22X1TS U2863 ( .A0(n1957), .A1(n3115), .B0(n1953), .B1(n3125), .Y(n2164)
);
NAND2X1TS U2864 ( .A(n2165), .B(n2164), .Y(n3149) );
OAI2BB2XLTS U2865 ( .B0(n3282), .B1(n2146), .A0N(final_result_ieee[38]),
.A1N(n1996), .Y(n1116) );
AOI22X1TS U2866 ( .A0(Data_array_SWR[31]), .A1(n2142), .B0(
Data_array_SWR[27]), .B1(n3188), .Y(n2166) );
OAI21XLTS U2867 ( .A0(n3456), .A1(n3056), .B0(n2166), .Y(n2167) );
AOI21X1TS U2868 ( .A0(Data_array_SWR[24]), .A1(n3125), .B0(n2167), .Y(n2174)
);
AOI22X1TS U2869 ( .A0(Data_array_SWR[15]), .A1(n3227), .B0(n1959), .B1(n3229), .Y(n2171) );
NAND2X1TS U2870 ( .A(n3115), .B(n2168), .Y(n3216) );
OAI2BB2XLTS U2871 ( .B0(n3429), .B1(n3216), .A0N(n1957), .A1N(n3226), .Y(
n2169) );
AOI21X1TS U2872 ( .A0(n1953), .A1(n3228), .B0(n2169), .Y(n2170) );
OAI211X1TS U2873 ( .A0(n2174), .A1(n2127), .B0(n2171), .C0(n2170), .Y(n2180)
);
INVX2TS U2874 ( .A(n3173), .Y(n2179) );
AOI22X1TS U2875 ( .A0(Data_array_SWR[26]), .A1(n3054), .B0(
Data_array_SWR[22]), .B1(n3188), .Y(n2173) );
AOI22X1TS U2876 ( .A0(n1954), .A1(n3115), .B0(n1934), .B1(n3125), .Y(n2172)
);
NAND2X1TS U2877 ( .A(n2173), .B(n2172), .Y(n3009) );
OAI2BB2XLTS U2878 ( .B0(n3273), .B1(n2146), .A0N(final_result_ieee[30]),
.A1N(n1996), .Y(n1127) );
NOR2X2TS U2879 ( .A(shift_value_SHT2_EWR[5]), .B(n3303), .Y(n3236) );
NAND2X1TS U2880 ( .A(shift_value_SHT2_EWR[4]), .B(n3189), .Y(n3058) );
AOI22X1TS U2881 ( .A0(Data_array_SWR[13]), .A1(n3198), .B0(n1958), .B1(n3227), .Y(n2177) );
AOI22X1TS U2882 ( .A0(n1956), .A1(n3180), .B0(Data_array_SWR[8]), .B1(n3229),
.Y(n2176) );
AOI22X1TS U2883 ( .A0(n3232), .A1(n3009), .B0(n2168), .B1(n2179), .Y(n2175)
);
NAND3XLTS U2884 ( .A(n2177), .B(n2176), .C(n2175), .Y(n2181) );
AOI22X1TS U2885 ( .A0(n3236), .A1(n1900), .B0(n3303), .B1(n2181), .Y(n3256)
);
OAI2BB2XLTS U2886 ( .B0(n3256), .B1(n2146), .A0N(final_result_ieee[14]),
.A1N(n1996), .Y(n1126) );
OAI2BB2XLTS U2887 ( .B0(n3254), .B1(n2146), .A0N(final_result_ieee[12]),
.A1N(n1996), .Y(n1119) );
OAI2BB2XLTS U2888 ( .B0(n3263), .B1(n2146), .A0N(final_result_ieee[20]),
.A1N(n1996), .Y(n1128) );
NOR2X2TS U2889 ( .A(shift_value_SHT2_EWR[5]), .B(left_right_SHT2), .Y(n3237)
);
AOI22X1TS U2890 ( .A0(n3239), .A1(n2181), .B0(n3237), .B1(n1900), .Y(n3280)
);
OAI2BB2XLTS U2891 ( .B0(n3280), .B1(n2146), .A0N(final_result_ieee[36]),
.A1N(n1996), .Y(n1125) );
OAI2BB2XLTS U2892 ( .B0(n2985), .B1(n2146), .A0N(final_result_ieee[11]),
.A1N(n1996), .Y(n1107) );
AO22XLTS U2893 ( .A0(n2803), .A1(intDY_EWSW[46]), .B0(n2804), .B1(Data_Y[46]), .Y(n1703) );
AO22XLTS U2894 ( .A0(n2803), .A1(intDY_EWSW[43]), .B0(n2804), .B1(Data_Y[43]), .Y(n1706) );
AO22XLTS U2895 ( .A0(n2806), .A1(intDY_EWSW[45]), .B0(n2804), .B1(Data_Y[45]), .Y(n1704) );
AO22XLTS U2896 ( .A0(n2803), .A1(intDY_EWSW[44]), .B0(n2804), .B1(Data_Y[44]), .Y(n1705) );
BUFX4TS U2897 ( .A(n2793), .Y(n2796) );
AO22XLTS U2898 ( .A0(n2803), .A1(intDY_EWSW[50]), .B0(n2796), .B1(Data_Y[50]), .Y(n1699) );
AO22XLTS U2899 ( .A0(n2806), .A1(intDY_EWSW[56]), .B0(n2796), .B1(Data_Y[56]), .Y(n1693) );
BUFX3TS U2900 ( .A(n2793), .Y(n2801) );
AO22XLTS U2901 ( .A0(n2803), .A1(intDY_EWSW[51]), .B0(n2801), .B1(Data_Y[51]), .Y(n1698) );
AO22XLTS U2902 ( .A0(n2806), .A1(intDY_EWSW[59]), .B0(n2801), .B1(Data_Y[59]), .Y(n1690) );
AO22XLTS U2903 ( .A0(n2806), .A1(intDY_EWSW[62]), .B0(n2801), .B1(Data_Y[62]), .Y(n1687) );
AO22XLTS U2904 ( .A0(n2806), .A1(intDY_EWSW[60]), .B0(n2801), .B1(Data_Y[60]), .Y(n1689) );
AO22XLTS U2905 ( .A0(n2803), .A1(intDY_EWSW[47]), .B0(n2801), .B1(Data_Y[47]), .Y(n1702) );
AO22XLTS U2906 ( .A0(n2806), .A1(intDY_EWSW[61]), .B0(n2801), .B1(Data_Y[61]), .Y(n1688) );
AO22XLTS U2907 ( .A0(n2803), .A1(intDY_EWSW[48]), .B0(n2801), .B1(Data_Y[48]), .Y(n1701) );
AO22XLTS U2908 ( .A0(n2806), .A1(intDX_EWSW[1]), .B0(n2801), .B1(Data_X[1]),
.Y(n1814) );
INVX4TS U2909 ( .A(n2804), .Y(n2802) );
AO22XLTS U2910 ( .A0(n2793), .A1(Data_X[13]), .B0(n2802), .B1(intDX_EWSW[13]), .Y(n1802) );
INVX4TS U2911 ( .A(n2796), .Y(n2800) );
AO22XLTS U2912 ( .A0(n2793), .A1(Data_X[14]), .B0(n2800), .B1(intDX_EWSW[14]), .Y(n1801) );
OAI21XLTS U2913 ( .A0(n2882), .A1(n3303), .B0(n1969), .Y(n1750) );
AOI2BB2XLTS U2914 ( .B0(beg_OP), .B1(n3332), .A0N(n3332), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n2186) );
NAND3XLTS U2915 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n3332), .C(
n3431), .Y(n2787) );
OAI21XLTS U2916 ( .A0(n2786), .A1(n2186), .B0(n2787), .Y(n1823) );
OAI22X1TS U2917 ( .A0(n3465), .A1(intDY_EWSW[55]), .B0(intDY_EWSW[54]), .B1(
n3358), .Y(n2302) );
NOR2BX1TS U2918 ( .AN(intDX_EWSW[56]), .B(intDY_EWSW[56]), .Y(n2188) );
NOR2X1TS U2919 ( .A(n3393), .B(intDY_EWSW[57]), .Y(n2256) );
NAND2X1TS U2920 ( .A(n3432), .B(intDX_EWSW[61]), .Y(n2262) );
OAI211X1TS U2921 ( .A0(intDY_EWSW[60]), .A1(n3385), .B0(n2266), .C0(n2262),
.Y(n2268) );
NAND2BXLTS U2922 ( .AN(intDY_EWSW[59]), .B(intDX_EWSW[59]), .Y(n2258) );
OAI21X1TS U2923 ( .A0(intDY_EWSW[58]), .A1(n3326), .B0(n2258), .Y(n2260) );
NOR2X1TS U2924 ( .A(n3391), .B(intDY_EWSW[49]), .Y(n2305) );
NAND2BXLTS U2925 ( .AN(intDY_EWSW[51]), .B(intDX_EWSW[51]), .Y(n2307) );
OAI21X1TS U2926 ( .A0(intDY_EWSW[50]), .A1(n3322), .B0(n2307), .Y(n2311) );
AOI211X1TS U2927 ( .A0(intDX_EWSW[48]), .A1(n3422), .B0(n2305), .C0(n2311),
.Y(n2189) );
NAND3X1TS U2928 ( .A(n2304), .B(n2313), .C(n2189), .Y(n2321) );
NOR2BX1TS U2929 ( .AN(intDX_EWSW[39]), .B(intDY_EWSW[39]), .Y(n2296) );
AOI21X1TS U2930 ( .A0(intDX_EWSW[38]), .A1(n3440), .B0(n2296), .Y(n2295) );
NAND2X1TS U2931 ( .A(n3437), .B(intDX_EWSW[37]), .Y(n2284) );
OAI211X1TS U2932 ( .A0(intDY_EWSW[36]), .A1(n3381), .B0(n2295), .C0(n2284),
.Y(n2286) );
NOR2X1TS U2933 ( .A(n3388), .B(intDY_EWSW[45]), .Y(n2270) );
OAI21X1TS U2934 ( .A0(intDY_EWSW[46]), .A1(n3366), .B0(n2269), .Y(n2279) );
OA22X1TS U2935 ( .A0(n3374), .A1(intDY_EWSW[42]), .B0(n3318), .B1(
intDY_EWSW[43]), .Y(n2275) );
NAND2BXLTS U2936 ( .AN(intDY_EWSW[41]), .B(intDX_EWSW[41]), .Y(n2191) );
NAND2BXLTS U2937 ( .AN(intDY_EWSW[40]), .B(intDX_EWSW[40]), .Y(n2190) );
NAND4XLTS U2938 ( .A(n2277), .B(n2275), .C(n2191), .D(n2190), .Y(n2319) );
NAND2BXLTS U2939 ( .AN(intDY_EWSW[32]), .B(intDX_EWSW[32]), .Y(n2192) );
OA22X1TS U2940 ( .A0(n3375), .A1(intDY_EWSW[34]), .B0(n3319), .B1(
intDY_EWSW[35]), .Y(n2290) );
OAI211XLTS U2941 ( .A0(n3373), .A1(intDY_EWSW[33]), .B0(n2192), .C0(n2290),
.Y(n2193) );
NOR4X1TS U2942 ( .A(n2321), .B(n2286), .C(n2319), .D(n2193), .Y(n2325) );
OA22X1TS U2943 ( .A0(n3379), .A1(intDY_EWSW[30]), .B0(n3320), .B1(
intDY_EWSW[31]), .Y(n2491) );
OAI2BB2XLTS U2944 ( .B0(intDX_EWSW[28]), .B1(n2194), .A0N(intDY_EWSW[29]),
.A1N(n3383), .Y(n2203) );
NAND2BXLTS U2945 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n2197) );
OAI21X1TS U2946 ( .A0(intDY_EWSW[26]), .A1(n3401), .B0(n2197), .Y(n2251) );
NAND2BXLTS U2947 ( .AN(intDY_EWSW[29]), .B(intDX_EWSW[29]), .Y(n2195) );
NOR2X1TS U2948 ( .A(n3389), .B(intDY_EWSW[25]), .Y(n2248) );
NOR2XLTS U2949 ( .A(n2248), .B(intDX_EWSW[24]), .Y(n2196) );
AOI22X1TS U2950 ( .A0(n2196), .A1(intDY_EWSW[24]), .B0(intDY_EWSW[25]), .B1(
n3389), .Y(n2199) );
AOI32X1TS U2951 ( .A0(n3401), .A1(n2197), .A2(intDY_EWSW[26]), .B0(
intDY_EWSW[27]), .B1(n3324), .Y(n2198) );
OAI32X1TS U2952 ( .A0(n2251), .A1(n2250), .A2(n2199), .B0(n2198), .B1(n2250),
.Y(n2202) );
OAI21XLTS U2953 ( .A0(intDY_EWSW[31]), .A1(n3320), .B0(intDY_EWSW[30]), .Y(
n2200) );
OAI2BB2XLTS U2954 ( .B0(intDX_EWSW[30]), .B1(n2200), .A0N(intDY_EWSW[31]),
.A1N(n3320), .Y(n2201) );
AOI211X1TS U2955 ( .A0(n2491), .A1(n2203), .B0(n2202), .C0(n2201), .Y(n2255)
);
OA22X1TS U2956 ( .A0(n3380), .A1(intDY_EWSW[22]), .B0(n3321), .B1(
intDY_EWSW[23]), .Y(n2499) );
NAND2BXLTS U2957 ( .AN(intDY_EWSW[21]), .B(intDX_EWSW[21]), .Y(n2204) );
OA22X1TS U2958 ( .A0(n3368), .A1(intDY_EWSW[14]), .B0(n3316), .B1(
intDY_EWSW[15]), .Y(n2505) );
NAND2BXLTS U2959 ( .AN(intDY_EWSW[13]), .B(intDX_EWSW[13]), .Y(n2205) );
OAI2BB1X1TS U2960 ( .A0N(n3334), .A1N(intDX_EWSW[5]), .B0(intDY_EWSW[4]),
.Y(n2206) );
OAI22X1TS U2961 ( .A0(intDX_EWSW[4]), .A1(n2206), .B0(n3334), .B1(
intDX_EWSW[5]), .Y(n2216) );
OAI2BB1X1TS U2962 ( .A0N(n3453), .A1N(intDX_EWSW[7]), .B0(intDY_EWSW[6]),
.Y(n2207) );
OAI22X1TS U2963 ( .A0(intDX_EWSW[6]), .A1(n2207), .B0(n3453), .B1(
intDX_EWSW[7]), .Y(n2215) );
NAND2BXLTS U2964 ( .AN(intDY_EWSW[2]), .B(intDX_EWSW[2]), .Y(n2210) );
AOI2BB2XLTS U2965 ( .B0(intDX_EWSW[1]), .B1(n3449), .A0N(intDY_EWSW[0]),
.A1N(n2208), .Y(n2209) );
OAI211XLTS U2966 ( .A0(n3372), .A1(intDY_EWSW[3]), .B0(n2210), .C0(n2209),
.Y(n2213) );
OAI21XLTS U2967 ( .A0(intDY_EWSW[3]), .A1(n3372), .B0(intDY_EWSW[2]), .Y(
n2211) );
AOI2BB2XLTS U2968 ( .B0(intDY_EWSW[3]), .B1(n3372), .A0N(intDX_EWSW[2]),
.A1N(n2211), .Y(n2212) );
AOI22X1TS U2969 ( .A0(intDX_EWSW[7]), .A1(n3453), .B0(intDX_EWSW[6]), .B1(
n3352), .Y(n2513) );
OAI32X1TS U2970 ( .A0(n2216), .A1(n2215), .A2(n2214), .B0(n2513), .B1(n2215),
.Y(n2232) );
NAND2BXLTS U2971 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n2220) );
NOR2X1TS U2972 ( .A(n3369), .B(intDY_EWSW[11]), .Y(n2218) );
AOI21X1TS U2973 ( .A0(intDX_EWSW[10]), .A1(n3408), .B0(n2218), .Y(n2223) );
OAI211XLTS U2974 ( .A0(intDY_EWSW[8]), .A1(n3392), .B0(n2220), .C0(n2223),
.Y(n2231) );
OAI21XLTS U2975 ( .A0(intDY_EWSW[13]), .A1(n3384), .B0(intDY_EWSW[12]), .Y(
n2217) );
OAI2BB2XLTS U2976 ( .B0(intDX_EWSW[12]), .B1(n2217), .A0N(intDY_EWSW[13]),
.A1N(n3384), .Y(n2229) );
NOR2XLTS U2977 ( .A(n2218), .B(intDX_EWSW[10]), .Y(n2219) );
AOI22X1TS U2978 ( .A0(intDY_EWSW[11]), .A1(n3369), .B0(intDY_EWSW[10]), .B1(
n2219), .Y(n2225) );
NAND3XLTS U2979 ( .A(n3392), .B(n2220), .C(intDY_EWSW[8]), .Y(n2222) );
AOI21X1TS U2980 ( .A0(n2222), .A1(n2221), .B0(n2233), .Y(n2224) );
OAI2BB2XLTS U2981 ( .B0(n2225), .B1(n2233), .A0N(n2224), .A1N(n2223), .Y(
n2228) );
OAI21XLTS U2982 ( .A0(intDY_EWSW[15]), .A1(n3316), .B0(intDY_EWSW[14]), .Y(
n2226) );
OAI2BB2XLTS U2983 ( .B0(intDX_EWSW[14]), .B1(n2226), .A0N(intDY_EWSW[15]),
.A1N(n3316), .Y(n2227) );
AOI211X1TS U2984 ( .A0(n2505), .A1(n2229), .B0(n2228), .C0(n2227), .Y(n2230)
);
OAI31X1TS U2985 ( .A0(n2233), .A1(n2232), .A2(n2231), .B0(n2230), .Y(n2235)
);
NOR2X1TS U2986 ( .A(n3390), .B(intDY_EWSW[17]), .Y(n2237) );
NAND2BXLTS U2987 ( .AN(intDY_EWSW[19]), .B(intDX_EWSW[19]), .Y(n2239) );
OAI21X1TS U2988 ( .A0(intDY_EWSW[18]), .A1(n3402), .B0(n2239), .Y(n2243) );
NAND3BXLTS U2989 ( .AN(n2242), .B(n2235), .C(n2234), .Y(n2254) );
OAI21XLTS U2990 ( .A0(intDY_EWSW[21]), .A1(n3400), .B0(intDY_EWSW[20]), .Y(
n2236) );
OAI2BB2XLTS U2991 ( .B0(intDX_EWSW[20]), .B1(n2236), .A0N(intDY_EWSW[21]),
.A1N(n3400), .Y(n2247) );
NOR2XLTS U2992 ( .A(n2237), .B(intDX_EWSW[16]), .Y(n2238) );
AOI22X1TS U2993 ( .A0(n2238), .A1(intDY_EWSW[16]), .B0(intDY_EWSW[17]), .B1(
n3390), .Y(n2241) );
AOI32X1TS U2994 ( .A0(n3402), .A1(n2239), .A2(intDY_EWSW[18]), .B0(
intDY_EWSW[19]), .B1(n3325), .Y(n2240) );
OAI32X1TS U2995 ( .A0(n2243), .A1(n2242), .A2(n2241), .B0(n2240), .B1(n2242),
.Y(n2246) );
OAI21XLTS U2996 ( .A0(intDY_EWSW[23]), .A1(n3321), .B0(intDY_EWSW[22]), .Y(
n2244) );
OAI2BB2XLTS U2997 ( .B0(intDX_EWSW[22]), .B1(n2244), .A0N(intDY_EWSW[23]),
.A1N(n3321), .Y(n2245) );
AOI211X1TS U2998 ( .A0(n2499), .A1(n2247), .B0(n2246), .C0(n2245), .Y(n2253)
);
NOR2BX1TS U2999 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n2249) );
OR4X2TS U3000 ( .A(n2251), .B(n2250), .C(n2249), .D(n2248), .Y(n2252) );
AOI32X1TS U3001 ( .A0(n2255), .A1(n2254), .A2(n2253), .B0(n2252), .B1(n2255),
.Y(n2324) );
NOR2XLTS U3002 ( .A(n2256), .B(intDX_EWSW[56]), .Y(n2257) );
AOI22X1TS U3003 ( .A0(intDY_EWSW[57]), .A1(n3393), .B0(intDY_EWSW[56]), .B1(
n2257), .Y(n2261) );
AOI32X1TS U3004 ( .A0(n3326), .A1(n2258), .A2(intDY_EWSW[58]), .B0(
intDY_EWSW[59]), .B1(n3404), .Y(n2259) );
OA21XLTS U3005 ( .A0(n2261), .A1(n2260), .B0(n2259), .Y(n2267) );
NAND3XLTS U3006 ( .A(n3385), .B(n2262), .C(intDY_EWSW[60]), .Y(n2263) );
OAI211XLTS U3007 ( .A0(intDX_EWSW[61]), .A1(n3432), .B0(n2264), .C0(n2263),
.Y(n2265) );
OAI2BB2XLTS U3008 ( .B0(n2268), .B1(n2267), .A0N(n2266), .A1N(n2265), .Y(
n2323) );
NOR2BX1TS U3009 ( .AN(n2269), .B(intDX_EWSW[46]), .Y(n2283) );
AOI22X1TS U3010 ( .A0(intDY_EWSW[45]), .A1(n3388), .B0(intDY_EWSW[44]), .B1(
n2271), .Y(n2280) );
OAI21XLTS U3011 ( .A0(intDY_EWSW[41]), .A1(n3382), .B0(intDY_EWSW[40]), .Y(
n2272) );
OAI2BB2XLTS U3012 ( .B0(intDX_EWSW[40]), .B1(n2272), .A0N(intDY_EWSW[41]),
.A1N(n3382), .Y(n2276) );
OAI21XLTS U3013 ( .A0(intDY_EWSW[43]), .A1(n3318), .B0(intDY_EWSW[42]), .Y(
n2273) );
OAI2BB2XLTS U3014 ( .B0(intDX_EWSW[42]), .B1(n2273), .A0N(intDY_EWSW[43]),
.A1N(n3318), .Y(n2274) );
AOI32X1TS U3015 ( .A0(n2277), .A1(n2276), .A2(n2275), .B0(n2274), .B1(n2277),
.Y(n2278) );
OAI21XLTS U3016 ( .A0(n2280), .A1(n2279), .B0(n2278), .Y(n2282) );
NOR2BX1TS U3017 ( .AN(intDY_EWSW[47]), .B(intDX_EWSW[47]), .Y(n2281) );
AOI211XLTS U3018 ( .A0(intDY_EWSW[46]), .A1(n2283), .B0(n2282), .C0(n2281),
.Y(n2320) );
NAND3XLTS U3019 ( .A(n3381), .B(n2284), .C(intDY_EWSW[36]), .Y(n2285) );
OAI21XLTS U3020 ( .A0(intDX_EWSW[37]), .A1(n3437), .B0(n2285), .Y(n2294) );
INVX2TS U3021 ( .A(n2286), .Y(n2292) );
OAI2BB2XLTS U3022 ( .B0(intDX_EWSW[32]), .B1(n2287), .A0N(intDY_EWSW[33]),
.A1N(n3373), .Y(n2291) );
OAI21XLTS U3023 ( .A0(intDY_EWSW[35]), .A1(n3319), .B0(intDY_EWSW[34]), .Y(
n2288) );
OAI2BB2XLTS U3024 ( .B0(intDX_EWSW[34]), .B1(n2288), .A0N(intDY_EWSW[35]),
.A1N(n3319), .Y(n2289) );
AOI32X1TS U3025 ( .A0(n2292), .A1(n2291), .A2(n2290), .B0(n2289), .B1(n2292),
.Y(n2293) );
OAI2BB1X1TS U3026 ( .A0N(n2295), .A1N(n2294), .B0(n2293), .Y(n2300) );
NOR2BX1TS U3027 ( .AN(intDY_EWSW[39]), .B(intDX_EWSW[39]), .Y(n2299) );
NOR3X1TS U3028 ( .A(n3440), .B(n2296), .C(intDX_EWSW[38]), .Y(n2298) );
INVX2TS U3029 ( .A(n2321), .Y(n2297) );
OAI31X1TS U3030 ( .A0(n2300), .A1(n2299), .A2(n2298), .B0(n2297), .Y(n2318)
);
OAI21XLTS U3031 ( .A0(intDY_EWSW[53]), .A1(n3464), .B0(intDY_EWSW[52]), .Y(
n2301) );
AOI2BB2XLTS U3032 ( .B0(intDY_EWSW[53]), .B1(n3464), .A0N(intDX_EWSW[52]),
.A1N(n2301), .Y(n2303) );
NOR2XLTS U3033 ( .A(n2303), .B(n2302), .Y(n2316) );
INVX2TS U3034 ( .A(n2304), .Y(n2310) );
NOR2XLTS U3035 ( .A(n2305), .B(intDX_EWSW[48]), .Y(n2306) );
AOI22X1TS U3036 ( .A0(intDY_EWSW[49]), .A1(n3391), .B0(intDY_EWSW[48]), .B1(
n2306), .Y(n2309) );
AOI32X1TS U3037 ( .A0(n3322), .A1(n2307), .A2(intDY_EWSW[50]), .B0(
intDY_EWSW[51]), .B1(n3397), .Y(n2308) );
OAI32X1TS U3038 ( .A0(n2311), .A1(n2310), .A2(n2309), .B0(n2308), .B1(n2310),
.Y(n2315) );
OAI21XLTS U3039 ( .A0(intDY_EWSW[55]), .A1(n3465), .B0(intDY_EWSW[54]), .Y(
n2312) );
OAI2BB2XLTS U3040 ( .B0(intDX_EWSW[54]), .B1(n2312), .A0N(intDY_EWSW[55]),
.A1N(n3465), .Y(n2314) );
OAI31X1TS U3041 ( .A0(n2316), .A1(n2315), .A2(n2314), .B0(n2313), .Y(n2317)
);
OAI221XLTS U3042 ( .A0(n2321), .A1(n2320), .B0(n2319), .B1(n2318), .C0(n2317), .Y(n2322) );
AOI211X1TS U3043 ( .A0(n2325), .A1(n2324), .B0(n2323), .C0(n2322), .Y(n2326)
);
CLKBUFX2TS U3044 ( .A(n2327), .Y(n2384) );
AOI22X1TS U3045 ( .A0(intDX_EWSW[10]), .A1(n1827), .B0(DmP_EXP_EWSW[10]),
.B1(n2442), .Y(n2328) );
OAI21XLTS U3046 ( .A0(n3408), .A1(n2365), .B0(n2328), .Y(n1311) );
AOI22X1TS U3047 ( .A0(intDX_EWSW[22]), .A1(n1827), .B0(DmP_EXP_EWSW[22]),
.B1(n2453), .Y(n2329) );
OAI21XLTS U3048 ( .A0(n3451), .A1(n2336), .B0(n2329), .Y(n1287) );
BUFX3TS U3049 ( .A(n2336), .Y(n2842) );
BUFX4TS U3050 ( .A(n2842), .Y(n2871) );
AOI22X1TS U3051 ( .A0(intDX_EWSW[26]), .A1(n2384), .B0(DmP_EXP_EWSW[26]),
.B1(n2442), .Y(n2330) );
OAI21XLTS U3052 ( .A0(n3419), .A1(n2871), .B0(n2330), .Y(n1279) );
BUFX4TS U3053 ( .A(n2842), .Y(n2872) );
AOI22X1TS U3054 ( .A0(intDX_EWSW[30]), .A1(n1827), .B0(DmP_EXP_EWSW[30]),
.B1(n2442), .Y(n2331) );
AOI22X1TS U3055 ( .A0(DmP_EXP_EWSW[57]), .A1(n2442), .B0(intDX_EWSW[57]),
.B1(n1827), .Y(n2332) );
OAI21XLTS U3056 ( .A0(n3409), .A1(n2872), .B0(n2332), .Y(n1222) );
AOI22X1TS U3057 ( .A0(intDX_EWSW[28]), .A1(n2384), .B0(DmP_EXP_EWSW[28]),
.B1(n2386), .Y(n2333) );
OAI21XLTS U3058 ( .A0(n3420), .A1(n2872), .B0(n2333), .Y(n1275) );
AOI22X1TS U3059 ( .A0(intDX_EWSW[7]), .A1(n1827), .B0(DmP_EXP_EWSW[7]), .B1(
n2386), .Y(n2334) );
OAI21XLTS U3060 ( .A0(n3453), .A1(n2365), .B0(n2334), .Y(n1317) );
AOI22X1TS U3061 ( .A0(intDX_EWSW[8]), .A1(n1827), .B0(DmP_EXP_EWSW[8]), .B1(
n2453), .Y(n2335) );
OAI21XLTS U3062 ( .A0(n3414), .A1(n2365), .B0(n2335), .Y(n1315) );
INVX4TS U3063 ( .A(n2336), .Y(n2431) );
INVX2TS U3064 ( .A(n2337), .Y(n1227) );
INVX2TS U3065 ( .A(n2338), .Y(n1556) );
BUFX4TS U3066 ( .A(n1827), .Y(n2373) );
AOI22X1TS U3067 ( .A0(intDX_EWSW[15]), .A1(n2373), .B0(DmP_EXP_EWSW[15]),
.B1(n2442), .Y(n2339) );
OAI21XLTS U3068 ( .A0(n3346), .A1(n2365), .B0(n2339), .Y(n1301) );
BUFX4TS U3069 ( .A(n1827), .Y(n2380) );
AOI22X1TS U3070 ( .A0(intDX_EWSW[14]), .A1(n2380), .B0(DmP_EXP_EWSW[14]),
.B1(n2453), .Y(n2340) );
OAI21XLTS U3071 ( .A0(n3450), .A1(n2365), .B0(n2340), .Y(n1303) );
AOI22X1TS U3072 ( .A0(intDX_EWSW[12]), .A1(n2380), .B0(DmP_EXP_EWSW[12]),
.B1(n2453), .Y(n2341) );
OAI21XLTS U3073 ( .A0(n3415), .A1(n2365), .B0(n2341), .Y(n1307) );
AOI22X1TS U3074 ( .A0(intDX_EWSW[51]), .A1(n2373), .B0(DmP_EXP_EWSW[51]),
.B1(n2529), .Y(n2342) );
OAI21XLTS U3075 ( .A0(n3350), .A1(n2842), .B0(n2342), .Y(n1229) );
AOI22X1TS U3076 ( .A0(intDX_EWSW[49]), .A1(n2373), .B0(DmP_EXP_EWSW[49]),
.B1(n2529), .Y(n2343) );
OAI21XLTS U3077 ( .A0(n3430), .A1(n2842), .B0(n2343), .Y(n1233) );
AOI22X1TS U3078 ( .A0(intDX_EWSW[50]), .A1(n2373), .B0(DmP_EXP_EWSW[50]),
.B1(n2529), .Y(n2344) );
OAI21XLTS U3079 ( .A0(n3447), .A1(n2842), .B0(n2344), .Y(n1231) );
AOI22X1TS U3080 ( .A0(intDX_EWSW[35]), .A1(n2380), .B0(DmP_EXP_EWSW[35]),
.B1(n2386), .Y(n2345) );
OAI21XLTS U3081 ( .A0(n3342), .A1(n2872), .B0(n2345), .Y(n1261) );
AOI22X1TS U3082 ( .A0(intDX_EWSW[42]), .A1(n2373), .B0(DmP_EXP_EWSW[42]),
.B1(n2453), .Y(n2346) );
OAI21XLTS U3083 ( .A0(n3444), .A1(n2871), .B0(n2346), .Y(n1247) );
AOI22X1TS U3084 ( .A0(intDX_EWSW[34]), .A1(n2380), .B0(DmP_EXP_EWSW[34]),
.B1(n2386), .Y(n2347) );
OAI21XLTS U3085 ( .A0(n3441), .A1(n2872), .B0(n2347), .Y(n1263) );
AOI22X1TS U3086 ( .A0(intDX_EWSW[45]), .A1(n2373), .B0(DmP_EXP_EWSW[45]),
.B1(n2529), .Y(n2348) );
OAI21XLTS U3087 ( .A0(n3439), .A1(n2871), .B0(n2348), .Y(n1241) );
AOI22X1TS U3088 ( .A0(intDX_EWSW[41]), .A1(n2380), .B0(DmP_EXP_EWSW[41]),
.B1(n2386), .Y(n2349) );
OAI21XLTS U3089 ( .A0(n3343), .A1(n2871), .B0(n2349), .Y(n1249) );
AOI22X1TS U3090 ( .A0(intDX_EWSW[31]), .A1(n2380), .B0(DmP_EXP_EWSW[31]),
.B1(n2386), .Y(n2350) );
OAI21XLTS U3091 ( .A0(n3348), .A1(n2872), .B0(n2350), .Y(n1269) );
AOI22X1TS U3092 ( .A0(intDX_EWSW[43]), .A1(n2373), .B0(DmP_EXP_EWSW[43]),
.B1(n2442), .Y(n2351) );
OAI21XLTS U3093 ( .A0(n3344), .A1(n2871), .B0(n2351), .Y(n1245) );
AOI22X1TS U3094 ( .A0(intDX_EWSW[29]), .A1(n2373), .B0(DmP_EXP_EWSW[29]),
.B1(n2386), .Y(n2352) );
OAI21XLTS U3095 ( .A0(n3339), .A1(n2872), .B0(n2352), .Y(n1273) );
AOI22X1TS U3096 ( .A0(intDX_EWSW[25]), .A1(n2380), .B0(DmP_EXP_EWSW[25]),
.B1(n2845), .Y(n2353) );
OAI21XLTS U3097 ( .A0(n3337), .A1(n2871), .B0(n2353), .Y(n1281) );
AOI22X1TS U3098 ( .A0(intDX_EWSW[33]), .A1(n2380), .B0(DmP_EXP_EWSW[33]),
.B1(n2386), .Y(n2354) );
OAI21XLTS U3099 ( .A0(n3341), .A1(n2872), .B0(n2354), .Y(n1265) );
AOI22X1TS U3100 ( .A0(intDX_EWSW[27]), .A1(n2373), .B0(DmP_EXP_EWSW[27]),
.B1(n2453), .Y(n2355) );
OAI21XLTS U3101 ( .A0(n3338), .A1(n2872), .B0(n2355), .Y(n1277) );
AOI22X1TS U3102 ( .A0(intDX_EWSW[36]), .A1(n2380), .B0(DmP_EXP_EWSW[36]),
.B1(n2386), .Y(n2356) );
OAI21XLTS U3103 ( .A0(n3442), .A1(n2871), .B0(n2356), .Y(n1259) );
AOI22X1TS U3104 ( .A0(intDX_EWSW[46]), .A1(n2373), .B0(DmP_EXP_EWSW[46]),
.B1(n1933), .Y(n2357) );
OAI21XLTS U3105 ( .A0(n3446), .A1(n2871), .B0(n2357), .Y(n1239) );
AOI22X1TS U3106 ( .A0(intDX_EWSW[18]), .A1(n2373), .B0(DmP_EXP_EWSW[18]),
.B1(n2442), .Y(n2358) );
OAI21XLTS U3107 ( .A0(n3416), .A1(n2872), .B0(n2358), .Y(n1295) );
AOI22X1TS U3108 ( .A0(intDX_EWSW[19]), .A1(n2380), .B0(DmP_EXP_EWSW[19]),
.B1(n2845), .Y(n2359) );
OAI21XLTS U3109 ( .A0(n3336), .A1(n2871), .B0(n2359), .Y(n1293) );
AOI22X1TS U3110 ( .A0(intDX_EWSW[17]), .A1(n2380), .B0(DmP_EXP_EWSW[17]),
.B1(n2453), .Y(n2360) );
OAI21XLTS U3111 ( .A0(n3335), .A1(n2872), .B0(n2360), .Y(n1297) );
AOI22X1TS U3112 ( .A0(intDX_EWSW[21]), .A1(n2373), .B0(DmP_EXP_EWSW[21]),
.B1(n1933), .Y(n2361) );
OAI21XLTS U3113 ( .A0(n3411), .A1(n2872), .B0(n2361), .Y(n1289) );
AOI22X1TS U3114 ( .A0(intDX_EWSW[20]), .A1(n2373), .B0(DmP_EXP_EWSW[20]),
.B1(n2529), .Y(n2362) );
OAI21XLTS U3115 ( .A0(n3417), .A1(n2871), .B0(n2362), .Y(n1291) );
AOI22X1TS U3116 ( .A0(intDX_EWSW[23]), .A1(n2373), .B0(DmP_EXP_EWSW[23]),
.B1(n2453), .Y(n2363) );
AOI22X1TS U3117 ( .A0(intDX_EWSW[16]), .A1(n2380), .B0(DmP_EXP_EWSW[16]),
.B1(n2845), .Y(n2364) );
OAI21XLTS U3118 ( .A0(n3425), .A1(n2365), .B0(n2364), .Y(n1299) );
AOI22X1TS U3119 ( .A0(intDX_EWSW[24]), .A1(n2380), .B0(DmP_EXP_EWSW[24]),
.B1(n2529), .Y(n2366) );
OAI21XLTS U3120 ( .A0(n3418), .A1(n2872), .B0(n2366), .Y(n1283) );
AOI22X1TS U3121 ( .A0(intDX_EWSW[48]), .A1(n2373), .B0(DmP_EXP_EWSW[48]),
.B1(n2453), .Y(n2367) );
OAI21XLTS U3122 ( .A0(n3422), .A1(n2842), .B0(n2367), .Y(n1235) );
AOI22X1TS U3123 ( .A0(intDX_EWSW[32]), .A1(n2380), .B0(DmP_EXP_EWSW[32]),
.B1(n2386), .Y(n2368) );
OAI21XLTS U3124 ( .A0(n3421), .A1(n2872), .B0(n2368), .Y(n1267) );
AOI22X1TS U3125 ( .A0(intDX_EWSW[39]), .A1(n2373), .B0(DmP_EXP_EWSW[39]),
.B1(n2386), .Y(n2369) );
OAI21XLTS U3126 ( .A0(n3438), .A1(n2871), .B0(n2369), .Y(n1253) );
AOI22X1TS U3127 ( .A0(intDX_EWSW[47]), .A1(n2373), .B0(DmP_EXP_EWSW[47]),
.B1(n2442), .Y(n2370) );
OAI21XLTS U3128 ( .A0(n3349), .A1(n2871), .B0(n2370), .Y(n1237) );
AOI22X1TS U3129 ( .A0(intDX_EWSW[40]), .A1(n2380), .B0(DmP_EXP_EWSW[40]),
.B1(n2386), .Y(n2371) );
OAI21XLTS U3130 ( .A0(n3443), .A1(n2871), .B0(n2371), .Y(n1251) );
AOI22X1TS U3131 ( .A0(intDX_EWSW[38]), .A1(n2380), .B0(DmP_EXP_EWSW[38]),
.B1(n2386), .Y(n2372) );
OAI21XLTS U3132 ( .A0(n3440), .A1(n2871), .B0(n2372), .Y(n1255) );
AOI22X1TS U3133 ( .A0(intDX_EWSW[44]), .A1(n2373), .B0(DmP_EXP_EWSW[44]),
.B1(n1933), .Y(n2374) );
AOI22X1TS U3134 ( .A0(intDX_EWSW[37]), .A1(n2380), .B0(DmP_EXP_EWSW[37]),
.B1(n2386), .Y(n2375) );
AOI22X1TS U3135 ( .A0(intDX_EWSW[5]), .A1(n1827), .B0(DmP_EXP_EWSW[5]), .B1(
n2453), .Y(n2376) );
OAI21XLTS U3136 ( .A0(n3334), .A1(n2365), .B0(n2376), .Y(n1321) );
AOI22X1TS U3137 ( .A0(intDX_EWSW[4]), .A1(n1827), .B0(DmP_EXP_EWSW[4]), .B1(
n2442), .Y(n2377) );
OAI21XLTS U3138 ( .A0(n3413), .A1(n2365), .B0(n2377), .Y(n1323) );
AOI22X1TS U3139 ( .A0(intDX_EWSW[1]), .A1(n1827), .B0(DmP_EXP_EWSW[1]), .B1(
n2453), .Y(n2378) );
OAI21XLTS U3140 ( .A0(n3449), .A1(n2872), .B0(n2378), .Y(n1329) );
AOI22X1TS U3141 ( .A0(intDX_EWSW[9]), .A1(n1827), .B0(DmP_EXP_EWSW[9]), .B1(
n2442), .Y(n2379) );
OAI21XLTS U3142 ( .A0(n3407), .A1(n2365), .B0(n2379), .Y(n1313) );
AOI22X1TS U3143 ( .A0(intDX_EWSW[13]), .A1(n2380), .B0(DmP_EXP_EWSW[13]),
.B1(n2453), .Y(n2381) );
OAI21XLTS U3144 ( .A0(n3410), .A1(n2365), .B0(n2381), .Y(n1305) );
AOI22X1TS U3145 ( .A0(intDX_EWSW[11]), .A1(n1827), .B0(DmP_EXP_EWSW[11]),
.B1(n2442), .Y(n2382) );
OAI21XLTS U3146 ( .A0(n3345), .A1(n2365), .B0(n2382), .Y(n1309) );
AOI22X1TS U3147 ( .A0(intDX_EWSW[6]), .A1(n2384), .B0(DmP_EXP_EWSW[6]), .B1(
n2442), .Y(n2383) );
OAI21XLTS U3148 ( .A0(n3352), .A1(n2365), .B0(n2383), .Y(n1319) );
AOI22X1TS U3149 ( .A0(intDX_EWSW[3]), .A1(n2384), .B0(DmP_EXP_EWSW[3]), .B1(
n2442), .Y(n2385) );
OAI21XLTS U3150 ( .A0(n3331), .A1(n2336), .B0(n2385), .Y(n1325) );
AOI22X1TS U3151 ( .A0(intDX_EWSW[0]), .A1(n1827), .B0(DmP_EXP_EWSW[0]), .B1(
n2453), .Y(n2387) );
OAI21XLTS U3152 ( .A0(n3333), .A1(n2336), .B0(n2387), .Y(n1331) );
AOI22X1TS U3153 ( .A0(intDX_EWSW[2]), .A1(n1827), .B0(DmP_EXP_EWSW[2]), .B1(
n2529), .Y(n2388) );
OAI21XLTS U3154 ( .A0(n3412), .A1(n2336), .B0(n2388), .Y(n1327) );
CLKBUFX2TS U3155 ( .A(n1827), .Y(n2395) );
AOI22X1TS U3156 ( .A0(intDX_EWSW[58]), .A1(n2449), .B0(DMP_EXP_EWSW[58]),
.B1(n2529), .Y(n2389) );
OAI21XLTS U3157 ( .A0(n3424), .A1(n2874), .B0(n2389), .Y(n1550) );
AOI22X1TS U3158 ( .A0(intDX_EWSW[60]), .A1(n2449), .B0(DMP_EXP_EWSW[60]),
.B1(n2529), .Y(n2390) );
OAI21XLTS U3159 ( .A0(n3423), .A1(n2874), .B0(n2390), .Y(n1548) );
AOI22X1TS U3160 ( .A0(intDX_EWSW[62]), .A1(n2456), .B0(DMP_EXP_EWSW[62]),
.B1(n2845), .Y(n2391) );
OAI21XLTS U3161 ( .A0(n3448), .A1(n2874), .B0(n2391), .Y(n1546) );
AOI22X1TS U3162 ( .A0(intDX_EWSW[0]), .A1(n2431), .B0(DMP_EXP_EWSW[0]), .B1(
n1933), .Y(n2392) );
INVX4TS U3163 ( .A(n2395), .Y(n2433) );
AOI22X1TS U3164 ( .A0(intDX_EWSW[7]), .A1(n2435), .B0(DMP_EXP_EWSW[7]), .B1(
n1933), .Y(n2393) );
OAI21XLTS U3165 ( .A0(n3453), .A1(n2433), .B0(n2393), .Y(n1601) );
INVX4TS U3166 ( .A(n2395), .Y(n2451) );
CLKBUFX2TS U3167 ( .A(n2529), .Y(n2426) );
AOI22X1TS U3168 ( .A0(intDX_EWSW[10]), .A1(n2435), .B0(DMP_EXP_EWSW[10]),
.B1(n2455), .Y(n2394) );
OAI21XLTS U3169 ( .A0(n3408), .A1(n2451), .B0(n2394), .Y(n1598) );
INVX4TS U3170 ( .A(n2395), .Y(n2458) );
AOI22X1TS U3171 ( .A0(intDX_EWSW[31]), .A1(n2456), .B0(DMP_EXP_EWSW[31]),
.B1(n2455), .Y(n2396) );
OAI21XLTS U3172 ( .A0(n3348), .A1(n2458), .B0(n2396), .Y(n1577) );
AOI22X1TS U3173 ( .A0(intDX_EWSW[38]), .A1(n2456), .B0(DMP_EXP_EWSW[38]),
.B1(n2453), .Y(n2397) );
OAI21XLTS U3174 ( .A0(n3440), .A1(n2458), .B0(n2397), .Y(n1570) );
AOI22X1TS U3175 ( .A0(intDX_EWSW[30]), .A1(n2431), .B0(DMP_EXP_EWSW[30]),
.B1(n2455), .Y(n2398) );
OAI21XLTS U3176 ( .A0(n3452), .A1(n2458), .B0(n2398), .Y(n1578) );
AOI22X1TS U3177 ( .A0(intDX_EWSW[4]), .A1(n2435), .B0(DMP_EXP_EWSW[4]), .B1(
n1933), .Y(n2399) );
OAI21XLTS U3178 ( .A0(n3413), .A1(n2451), .B0(n2399), .Y(n1604) );
AOI22X1TS U3179 ( .A0(intDX_EWSW[16]), .A1(n2435), .B0(DMP_EXP_EWSW[16]),
.B1(n2455), .Y(n2400) );
OAI21XLTS U3180 ( .A0(n3425), .A1(n2433), .B0(n2400), .Y(n1592) );
AOI22X1TS U3181 ( .A0(intDX_EWSW[37]), .A1(n2456), .B0(DMP_EXP_EWSW[37]),
.B1(n2455), .Y(n2401) );
OAI21XLTS U3182 ( .A0(n3437), .A1(n2458), .B0(n2401), .Y(n1571) );
AOI22X1TS U3183 ( .A0(intDX_EWSW[61]), .A1(n2449), .B0(DMP_EXP_EWSW[61]),
.B1(n2529), .Y(n2402) );
OAI21XLTS U3184 ( .A0(n3432), .A1(n2451), .B0(n2402), .Y(n1547) );
AOI22X1TS U3185 ( .A0(intDX_EWSW[1]), .A1(n2435), .B0(DMP_EXP_EWSW[1]), .B1(
n1933), .Y(n2403) );
OAI21XLTS U3186 ( .A0(n3449), .A1(n2458), .B0(n2403), .Y(n1607) );
AOI22X1TS U3187 ( .A0(intDX_EWSW[23]), .A1(n2431), .B0(DMP_EXP_EWSW[23]),
.B1(n2455), .Y(n2404) );
OAI21XLTS U3188 ( .A0(n3347), .A1(n2433), .B0(n2404), .Y(n1585) );
AOI22X1TS U3189 ( .A0(intDX_EWSW[5]), .A1(n2435), .B0(DMP_EXP_EWSW[5]), .B1(
n1933), .Y(n2405) );
OAI21XLTS U3190 ( .A0(n3334), .A1(n2458), .B0(n2405), .Y(n1603) );
AOI22X1TS U3191 ( .A0(intDX_EWSW[59]), .A1(n2449), .B0(DMP_EXP_EWSW[59]),
.B1(n2453), .Y(n2406) );
AOI22X1TS U3192 ( .A0(intDX_EWSW[22]), .A1(n2431), .B0(DMP_EXP_EWSW[22]),
.B1(n2455), .Y(n2407) );
OAI21XLTS U3193 ( .A0(n3451), .A1(n2433), .B0(n2407), .Y(n1586) );
AOI22X1TS U3194 ( .A0(intDX_EWSW[14]), .A1(n2435), .B0(DMP_EXP_EWSW[14]),
.B1(n2386), .Y(n2408) );
OAI21XLTS U3195 ( .A0(n3450), .A1(n2458), .B0(n2408), .Y(n1594) );
AOI22X1TS U3196 ( .A0(intDX_EWSW[15]), .A1(n2435), .B0(DMP_EXP_EWSW[15]),
.B1(n2455), .Y(n2409) );
OAI21XLTS U3197 ( .A0(n3346), .A1(n2433), .B0(n2409), .Y(n1593) );
AOI22X1TS U3198 ( .A0(intDX_EWSW[44]), .A1(n2449), .B0(DMP_EXP_EWSW[44]),
.B1(n2442), .Y(n2410) );
OAI21XLTS U3199 ( .A0(n3445), .A1(n2451), .B0(n2410), .Y(n1564) );
AOI22X1TS U3200 ( .A0(intDX_EWSW[48]), .A1(n2449), .B0(DMP_EXP_EWSW[48]),
.B1(n2442), .Y(n2411) );
OAI21XLTS U3201 ( .A0(n3422), .A1(n2451), .B0(n2411), .Y(n1560) );
AOI22X1TS U3202 ( .A0(intDX_EWSW[6]), .A1(n2435), .B0(DMP_EXP_EWSW[6]), .B1(
n1933), .Y(n2412) );
OAI21XLTS U3203 ( .A0(n3352), .A1(n2433), .B0(n2412), .Y(n1602) );
AOI22X1TS U3204 ( .A0(intDX_EWSW[11]), .A1(n2435), .B0(DMP_EXP_EWSW[11]),
.B1(n2455), .Y(n2413) );
OAI21XLTS U3205 ( .A0(n3345), .A1(n2458), .B0(n2413), .Y(n1597) );
AOI22X1TS U3206 ( .A0(intDX_EWSW[3]), .A1(n2435), .B0(DMP_EXP_EWSW[3]), .B1(
n1933), .Y(n2414) );
OAI21XLTS U3207 ( .A0(n3331), .A1(n2433), .B0(n2414), .Y(n1605) );
AOI22X1TS U3208 ( .A0(intDX_EWSW[2]), .A1(n2435), .B0(DMP_EXP_EWSW[2]), .B1(
n1933), .Y(n2415) );
OAI21XLTS U3209 ( .A0(n3412), .A1(n2451), .B0(n2415), .Y(n1606) );
AOI22X1TS U3210 ( .A0(intDX_EWSW[8]), .A1(n2435), .B0(DMP_EXP_EWSW[8]), .B1(
n2426), .Y(n2416) );
OAI21XLTS U3211 ( .A0(n3414), .A1(n2451), .B0(n2416), .Y(n1600) );
AOI22X1TS U3212 ( .A0(intDX_EWSW[13]), .A1(n2435), .B0(DMP_EXP_EWSW[13]),
.B1(n2426), .Y(n2417) );
AOI22X1TS U3213 ( .A0(intDX_EWSW[12]), .A1(n2435), .B0(DMP_EXP_EWSW[12]),
.B1(n2426), .Y(n2418) );
OAI21XLTS U3214 ( .A0(n3415), .A1(n2458), .B0(n2418), .Y(n1596) );
AOI22X1TS U3215 ( .A0(intDX_EWSW[18]), .A1(n2435), .B0(DMP_EXP_EWSW[18]),
.B1(n2455), .Y(n2419) );
OAI21XLTS U3216 ( .A0(n3416), .A1(n2433), .B0(n2419), .Y(n1590) );
AOI22X1TS U3217 ( .A0(intDX_EWSW[9]), .A1(n2435), .B0(DMP_EXP_EWSW[9]), .B1(
n1933), .Y(n2420) );
OAI21XLTS U3218 ( .A0(n3407), .A1(n2451), .B0(n2420), .Y(n1599) );
AOI22X1TS U3219 ( .A0(intDX_EWSW[27]), .A1(n2431), .B0(DMP_EXP_EWSW[27]),
.B1(n2455), .Y(n2421) );
AOI22X1TS U3220 ( .A0(intDX_EWSW[17]), .A1(n2435), .B0(DMP_EXP_EWSW[17]),
.B1(n2455), .Y(n2422) );
OAI21XLTS U3221 ( .A0(n3335), .A1(n2433), .B0(n2422), .Y(n1591) );
AOI22X1TS U3222 ( .A0(intDX_EWSW[19]), .A1(n2431), .B0(DMP_EXP_EWSW[19]),
.B1(n2455), .Y(n2423) );
OAI21XLTS U3223 ( .A0(n3336), .A1(n2433), .B0(n2423), .Y(n1589) );
AOI22X1TS U3224 ( .A0(intDX_EWSW[24]), .A1(n2431), .B0(DMP_EXP_EWSW[24]),
.B1(n2455), .Y(n2424) );
OAI21XLTS U3225 ( .A0(n3418), .A1(n2433), .B0(n2424), .Y(n1584) );
AOI22X1TS U3226 ( .A0(intDX_EWSW[20]), .A1(n2431), .B0(DMP_EXP_EWSW[20]),
.B1(n2426), .Y(n2425) );
OAI21XLTS U3227 ( .A0(n3417), .A1(n2433), .B0(n2425), .Y(n1588) );
AOI22X1TS U3228 ( .A0(intDX_EWSW[21]), .A1(n2431), .B0(DMP_EXP_EWSW[21]),
.B1(n2426), .Y(n2427) );
OAI21XLTS U3229 ( .A0(n3411), .A1(n2433), .B0(n2427), .Y(n1587) );
AOI22X1TS U3230 ( .A0(intDX_EWSW[29]), .A1(n2431), .B0(DMP_EXP_EWSW[29]),
.B1(n2455), .Y(n2428) );
OAI21XLTS U3231 ( .A0(n3339), .A1(n2458), .B0(n2428), .Y(n1579) );
AOI22X1TS U3232 ( .A0(intDX_EWSW[28]), .A1(n2431), .B0(DMP_EXP_EWSW[28]),
.B1(n2455), .Y(n2429) );
OAI21XLTS U3233 ( .A0(n3420), .A1(n2433), .B0(n2429), .Y(n1580) );
AOI22X1TS U3234 ( .A0(intDX_EWSW[25]), .A1(n2431), .B0(DMP_EXP_EWSW[25]),
.B1(n2529), .Y(n2430) );
OAI21XLTS U3235 ( .A0(n3337), .A1(n2433), .B0(n2430), .Y(n1583) );
AOI22X1TS U3236 ( .A0(intDX_EWSW[26]), .A1(n2431), .B0(DMP_EXP_EWSW[26]),
.B1(n2455), .Y(n2432) );
OAI21XLTS U3237 ( .A0(n3419), .A1(n2433), .B0(n2432), .Y(n1582) );
AOI22X1TS U3238 ( .A0(intDX_EWSW[32]), .A1(n2456), .B0(DMP_EXP_EWSW[32]),
.B1(n2455), .Y(n2434) );
OAI21XLTS U3239 ( .A0(n3421), .A1(n2458), .B0(n2434), .Y(n1576) );
AOI22X1TS U3240 ( .A0(DMP_EXP_EWSW[57]), .A1(n2386), .B0(intDX_EWSW[57]),
.B1(n2435), .Y(n2436) );
OAI21XLTS U3241 ( .A0(n3409), .A1(n2451), .B0(n2436), .Y(n1551) );
AOI22X1TS U3242 ( .A0(intDX_EWSW[49]), .A1(n2449), .B0(DMP_EXP_EWSW[49]),
.B1(n1933), .Y(n2437) );
OAI21XLTS U3243 ( .A0(n3430), .A1(n2451), .B0(n2437), .Y(n1559) );
AOI22X1TS U3244 ( .A0(intDX_EWSW[41]), .A1(n2456), .B0(DMP_EXP_EWSW[41]),
.B1(n2453), .Y(n2438) );
AOI22X1TS U3245 ( .A0(intDX_EWSW[46]), .A1(n2449), .B0(DMP_EXP_EWSW[46]),
.B1(n2442), .Y(n2439) );
OAI21XLTS U3246 ( .A0(n3446), .A1(n2451), .B0(n2439), .Y(n1562) );
AOI22X1TS U3247 ( .A0(intDX_EWSW[39]), .A1(n2456), .B0(DMP_EXP_EWSW[39]),
.B1(n2442), .Y(n2440) );
OAI21XLTS U3248 ( .A0(n3438), .A1(n2458), .B0(n2440), .Y(n1569) );
AOI22X1TS U3249 ( .A0(intDX_EWSW[42]), .A1(n2456), .B0(DMP_EXP_EWSW[42]),
.B1(n1933), .Y(n2441) );
OAI21XLTS U3250 ( .A0(n3444), .A1(n2451), .B0(n2441), .Y(n1566) );
AOI22X1TS U3251 ( .A0(intDX_EWSW[50]), .A1(n2449), .B0(DMP_EXP_EWSW[50]),
.B1(n2529), .Y(n2443) );
OAI21XLTS U3252 ( .A0(n3447), .A1(n2458), .B0(n2443), .Y(n1558) );
AOI22X1TS U3253 ( .A0(intDX_EWSW[33]), .A1(n2456), .B0(DMP_EXP_EWSW[33]),
.B1(n2845), .Y(n2444) );
OAI21XLTS U3254 ( .A0(n3341), .A1(n2458), .B0(n2444), .Y(n1575) );
AOI22X1TS U3255 ( .A0(intDX_EWSW[43]), .A1(n2449), .B0(DMP_EXP_EWSW[43]),
.B1(n2529), .Y(n2445) );
OAI21XLTS U3256 ( .A0(n3344), .A1(n2451), .B0(n2445), .Y(n1565) );
AOI22X1TS U3257 ( .A0(intDX_EWSW[51]), .A1(n2449), .B0(DMP_EXP_EWSW[51]),
.B1(n2529), .Y(n2446) );
OAI21XLTS U3258 ( .A0(n3350), .A1(n2451), .B0(n2446), .Y(n1557) );
AOI22X1TS U3259 ( .A0(intDX_EWSW[35]), .A1(n2456), .B0(DMP_EXP_EWSW[35]),
.B1(n2455), .Y(n2447) );
OAI21XLTS U3260 ( .A0(n3342), .A1(n2458), .B0(n2447), .Y(n1573) );
AOI22X1TS U3261 ( .A0(intDX_EWSW[47]), .A1(n2449), .B0(DMP_EXP_EWSW[47]),
.B1(n2529), .Y(n2448) );
OAI21XLTS U3262 ( .A0(n3349), .A1(n2451), .B0(n2448), .Y(n1561) );
AOI22X1TS U3263 ( .A0(intDX_EWSW[45]), .A1(n2456), .B0(DMP_EXP_EWSW[45]),
.B1(n2453), .Y(n2450) );
OAI21XLTS U3264 ( .A0(n3439), .A1(n2451), .B0(n2450), .Y(n1563) );
AOI22X1TS U3265 ( .A0(intDX_EWSW[36]), .A1(n2456), .B0(DMP_EXP_EWSW[36]),
.B1(n2442), .Y(n2452) );
OAI21XLTS U3266 ( .A0(n3442), .A1(n2458), .B0(n2452), .Y(n1572) );
AOI22X1TS U3267 ( .A0(intDX_EWSW[40]), .A1(n2449), .B0(DMP_EXP_EWSW[40]),
.B1(n2529), .Y(n2454) );
OAI21XLTS U3268 ( .A0(n3443), .A1(n2458), .B0(n2454), .Y(n1568) );
AOI22X1TS U3269 ( .A0(intDX_EWSW[34]), .A1(n2456), .B0(DMP_EXP_EWSW[34]),
.B1(n2455), .Y(n2457) );
OAI21XLTS U3270 ( .A0(n3441), .A1(n2458), .B0(n2457), .Y(n1574) );
AOI22X1TS U3271 ( .A0(n3345), .A1(intDX_EWSW[11]), .B0(n3430), .B1(
intDX_EWSW[49]), .Y(n2459) );
OAI221XLTS U3272 ( .A0(n3345), .A1(intDX_EWSW[11]), .B0(n3430), .B1(
intDX_EWSW[49]), .C0(n2459), .Y(n2460) );
AOI221X1TS U3273 ( .A0(intDY_EWSW[1]), .A1(n3433), .B0(n3449), .B1(
intDX_EWSW[1]), .C0(n2460), .Y(n2474) );
OAI22X1TS U3274 ( .A0(n3434), .A1(intDX_EWSW[52]), .B0(n3313), .B1(
intDX_EWSW[53]), .Y(n2461) );
OAI22X1TS U3275 ( .A0(n3447), .A1(intDX_EWSW[50]), .B0(n3350), .B1(
intDX_EWSW[51]), .Y(n2462) );
AOI221X1TS U3276 ( .A0(n3447), .A1(intDX_EWSW[50]), .B0(intDX_EWSW[51]),
.B1(n3350), .C0(n2462), .Y(n2472) );
AOI22X1TS U3277 ( .A0(n3409), .A1(intDX_EWSW[57]), .B0(n3310), .B1(
intDX_EWSW[56]), .Y(n2463) );
AOI22X1TS U3278 ( .A0(n3309), .A1(intDX_EWSW[55]), .B0(n3312), .B1(
intDX_EWSW[54]), .Y(n2464) );
OAI221XLTS U3279 ( .A0(n3309), .A1(intDX_EWSW[55]), .B0(n3312), .B1(
intDX_EWSW[54]), .C0(n2464), .Y(n2469) );
AOI22X1TS U3280 ( .A0(n3432), .A1(intDX_EWSW[61]), .B0(n3423), .B1(
intDX_EWSW[60]), .Y(n2465) );
AOI22X1TS U3281 ( .A0(n3340), .A1(intDX_EWSW[59]), .B0(n3424), .B1(
intDX_EWSW[58]), .Y(n2466) );
OAI221XLTS U3282 ( .A0(n3340), .A1(intDX_EWSW[59]), .B0(n3424), .B1(
intDX_EWSW[58]), .C0(n2466), .Y(n2467) );
NOR4X1TS U3283 ( .A(n2470), .B(n2469), .C(n2468), .D(n2467), .Y(n2471) );
NAND4XLTS U3284 ( .A(n2474), .B(n2473), .C(n2472), .D(n2471), .Y(n2528) );
OAI22X1TS U3285 ( .A0(n3444), .A1(intDX_EWSW[42]), .B0(n3344), .B1(
intDX_EWSW[43]), .Y(n2475) );
AOI221X1TS U3286 ( .A0(n3444), .A1(intDX_EWSW[42]), .B0(intDX_EWSW[43]),
.B1(n3344), .C0(n2475), .Y(n2482) );
OAI22X1TS U3287 ( .A0(n3443), .A1(intDX_EWSW[40]), .B0(n3343), .B1(
intDX_EWSW[41]), .Y(n2476) );
AOI221X1TS U3288 ( .A0(n3443), .A1(intDX_EWSW[40]), .B0(intDX_EWSW[41]),
.B1(n3343), .C0(n2476), .Y(n2481) );
OAI22X1TS U3289 ( .A0(n3446), .A1(intDX_EWSW[46]), .B0(n3349), .B1(
intDX_EWSW[47]), .Y(n2477) );
AOI221X1TS U3290 ( .A0(n3446), .A1(intDX_EWSW[46]), .B0(intDX_EWSW[47]),
.B1(n3349), .C0(n2477), .Y(n2480) );
OAI22X1TS U3291 ( .A0(n3445), .A1(intDX_EWSW[44]), .B0(n3439), .B1(
intDX_EWSW[45]), .Y(n2478) );
AOI221X1TS U3292 ( .A0(n3445), .A1(intDX_EWSW[44]), .B0(intDX_EWSW[45]),
.B1(n3439), .C0(n2478), .Y(n2479) );
NAND4XLTS U3293 ( .A(n2482), .B(n2481), .C(n2480), .D(n2479), .Y(n2527) );
OAI22X1TS U3294 ( .A0(n3441), .A1(intDX_EWSW[34]), .B0(n3342), .B1(
intDX_EWSW[35]), .Y(n2483) );
AOI221X1TS U3295 ( .A0(n3441), .A1(intDX_EWSW[34]), .B0(intDX_EWSW[35]),
.B1(n3342), .C0(n2483), .Y(n2490) );
OAI22X1TS U3296 ( .A0(n3448), .A1(intDX_EWSW[62]), .B0(n3341), .B1(
intDX_EWSW[33]), .Y(n2484) );
AOI221X1TS U3297 ( .A0(n3448), .A1(intDX_EWSW[62]), .B0(intDX_EWSW[33]),
.B1(n3341), .C0(n2484), .Y(n2489) );
OAI22X1TS U3298 ( .A0(n3440), .A1(intDX_EWSW[38]), .B0(n3438), .B1(
intDX_EWSW[39]), .Y(n2485) );
OAI22X1TS U3299 ( .A0(n3442), .A1(intDX_EWSW[36]), .B0(n3437), .B1(
intDX_EWSW[37]), .Y(n2486) );
AOI221X1TS U3300 ( .A0(n3442), .A1(intDX_EWSW[36]), .B0(intDX_EWSW[37]),
.B1(n3437), .C0(n2486), .Y(n2487) );
NAND4XLTS U3301 ( .A(n2490), .B(n2489), .C(n2488), .D(n2487), .Y(n2526) );
OAI221XLTS U3302 ( .A0(n3348), .A1(intDX_EWSW[31]), .B0(n3452), .B1(
intDX_EWSW[30]), .C0(n2491), .Y(n2498) );
AOI22X1TS U3303 ( .A0(n3339), .A1(intDX_EWSW[29]), .B0(n3417), .B1(
intDX_EWSW[20]), .Y(n2492) );
OAI221XLTS U3304 ( .A0(n3339), .A1(intDX_EWSW[29]), .B0(n3417), .B1(
intDX_EWSW[20]), .C0(n2492), .Y(n2497) );
AOI22X1TS U3305 ( .A0(n3338), .A1(intDX_EWSW[27]), .B0(n3419), .B1(
intDX_EWSW[26]), .Y(n2493) );
AOI22X1TS U3306 ( .A0(n3337), .A1(intDX_EWSW[25]), .B0(n3421), .B1(
intDX_EWSW[32]), .Y(n2494) );
NOR4X1TS U3307 ( .A(n2495), .B(n2497), .C(n2496), .D(n2498), .Y(n2524) );
OAI221XLTS U3308 ( .A0(n3347), .A1(intDX_EWSW[23]), .B0(n3451), .B1(
intDX_EWSW[22]), .C0(n2499), .Y(n2504) );
AOI22X1TS U3309 ( .A0(n3411), .A1(intDX_EWSW[21]), .B0(n3422), .B1(
intDX_EWSW[48]), .Y(n2500) );
AOI22X1TS U3310 ( .A0(n3335), .A1(intDX_EWSW[17]), .B0(n3418), .B1(
intDX_EWSW[24]), .Y(n2501) );
NOR4X1TS U3311 ( .A(n2503), .B(n2504), .C(n1829), .D(n2502), .Y(n2523) );
OAI221XLTS U3312 ( .A0(n3346), .A1(intDX_EWSW[15]), .B0(n3450), .B1(
intDX_EWSW[14]), .C0(n2505), .Y(n2512) );
AOI22X1TS U3313 ( .A0(n3410), .A1(intDX_EWSW[13]), .B0(n3413), .B1(
intDX_EWSW[4]), .Y(n2506) );
AOI22X1TS U3314 ( .A0(n3408), .A1(intDX_EWSW[10]), .B0(n3415), .B1(
intDX_EWSW[12]), .Y(n2507) );
AOI22X1TS U3315 ( .A0(n3407), .A1(intDX_EWSW[9]), .B0(n3425), .B1(
intDX_EWSW[16]), .Y(n2508) );
NOR4X1TS U3316 ( .A(n2511), .B(n2512), .C(n2510), .D(n2509), .Y(n2522) );
AOI22X1TS U3317 ( .A0(n3334), .A1(intDX_EWSW[5]), .B0(n3420), .B1(
intDX_EWSW[28]), .Y(n2514) );
AOI22X1TS U3318 ( .A0(n3331), .A1(intDX_EWSW[3]), .B0(n3412), .B1(
intDX_EWSW[2]), .Y(n2515) );
AOI22X1TS U3319 ( .A0(n3333), .A1(intDX_EWSW[0]), .B0(n3414), .B1(
intDX_EWSW[8]), .Y(n2516) );
NOR4X1TS U3320 ( .A(n2520), .B(n2519), .C(n2518), .D(n2517), .Y(n2521) );
NAND4XLTS U3321 ( .A(n2524), .B(n2523), .C(n2522), .D(n2521), .Y(n2525) );
NOR4X1TS U3322 ( .A(n2528), .B(n2527), .C(n2526), .D(n2525), .Y(n2847) );
CLKXOR2X2TS U3323 ( .A(intDY_EWSW[63]), .B(intAS), .Y(n2844) );
INVX2TS U3324 ( .A(n2844), .Y(n2532) );
OAI21XLTS U3325 ( .A0(n2532), .A1(n1933), .B0(n2871), .Y(n2530) );
AOI22X1TS U3326 ( .A0(intDX_EWSW[63]), .A1(n2530), .B0(SIGN_FLAG_EXP), .B1(
n2529), .Y(n2531) );
NOR2X4TS U3327 ( .A(n2533), .B(n2811), .Y(n2810) );
BUFX4TS U3328 ( .A(n2719), .Y(n2690) );
NOR2X8TS U3329 ( .A(n2648), .B(n2719), .Y(n2718) );
AOI21X1TS U3330 ( .A0(n2811), .A1(Data_array_SWR[34]), .B0(n2718), .Y(n2534)
);
AOI22X1TS U3331 ( .A0(Raw_mant_NRM_SWR[53]), .A1(n2631), .B0(n2677), .B1(
n1927), .Y(n2539) );
BUFX4TS U3332 ( .A(n2719), .Y(n2670) );
AOI22X1TS U3333 ( .A0(Raw_mant_NRM_SWR[50]), .A1(n2667), .B0(n2623), .B1(
DmP_mant_SHT1_SW[2]), .Y(n2536) );
AOI22X1TS U3334 ( .A0(Raw_mant_NRM_SWR[51]), .A1(n2631), .B0(n2644), .B1(
DmP_mant_SHT1_SW[1]), .Y(n2535) );
NAND2X1TS U3335 ( .A(n2536), .B(n2535), .Y(n2558) );
AOI22X1TS U3336 ( .A0(n2815), .A1(Data_array_SWR[1]), .B0(n2554), .B1(n2558),
.Y(n2538) );
NAND2X1TS U3337 ( .A(Raw_mant_NRM_SWR[52]), .B(n1914), .Y(n2537) );
AOI22X1TS U3338 ( .A0(Raw_mant_NRM_SWR[44]), .A1(n2667), .B0(n2623), .B1(
DmP_mant_SHT1_SW[8]), .Y(n2541) );
AOI22X1TS U3339 ( .A0(Raw_mant_NRM_SWR[45]), .A1(n2631), .B0(n2644), .B1(
n1924), .Y(n2540) );
NAND2X1TS U3340 ( .A(n2541), .B(n2540), .Y(n2567) );
AOI22X1TS U3341 ( .A0(n2712), .A1(Data_array_SWR[7]), .B0(n2554), .B1(n2567),
.Y(n2543) );
NAND2X1TS U3342 ( .A(Raw_mant_NRM_SWR[46]), .B(n1914), .Y(n2542) );
AOI22X1TS U3343 ( .A0(Raw_mant_NRM_SWR[47]), .A1(n2667), .B0(n2623), .B1(
n1923), .Y(n2545) );
AOI22X1TS U3344 ( .A0(Raw_mant_NRM_SWR[48]), .A1(n2631), .B0(n2644), .B1(
n1925), .Y(n2544) );
NAND2X1TS U3345 ( .A(n2545), .B(n2544), .Y(n2562) );
AOI22X1TS U3346 ( .A0(n2819), .A1(Data_array_SWR[4]), .B0(n2554), .B1(n2562),
.Y(n2547) );
NAND2X1TS U3347 ( .A(Raw_mant_NRM_SWR[49]), .B(n1826), .Y(n2546) );
BUFX3TS U3348 ( .A(n2553), .Y(n2678) );
BUFX3TS U3349 ( .A(n2559), .Y(n2643) );
AOI22X1TS U3350 ( .A0(n2811), .A1(Data_array_SWR[32]), .B0(
Raw_mant_NRM_SWR[0]), .B1(n2643), .Y(n2552) );
AOI22X1TS U3351 ( .A0(n2631), .A1(Raw_mant_NRM_SWR[1]), .B0(
DmP_mant_SHT1_SW[51]), .B1(n1969), .Y(n2550) );
NAND2X1TS U3352 ( .A(n2550), .B(n2549), .Y(n2809) );
AOI22X1TS U3353 ( .A0(n2554), .A1(n2809), .B0(DmP_mant_SHT1_SW[49]), .B1(
n2718), .Y(n2551) );
BUFX3TS U3354 ( .A(n2553), .Y(n2673) );
BUFX4TS U3355 ( .A(n2570), .Y(n2716) );
AOI22X1TS U3356 ( .A0(n2712), .A1(n1945), .B0(Raw_mant_NRM_SWR[39]), .B1(
n2559), .Y(n2556) );
BUFX4TS U3357 ( .A(n2553), .Y(n2708) );
AOI22X1TS U3358 ( .A0(n2815), .A1(Data_array_SWR[3]), .B0(n2810), .B1(n2558),
.Y(n2561) );
NAND2X1TS U3359 ( .A(Raw_mant_NRM_SWR[48]), .B(n2643), .Y(n2560) );
AOI22X1TS U3360 ( .A0(n2819), .A1(Data_array_SWR[6]), .B0(n2810), .B1(n2562),
.Y(n2564) );
NAND2X1TS U3361 ( .A(Raw_mant_NRM_SWR[45]), .B(n2559), .Y(n2563) );
AOI22X1TS U3362 ( .A0(n2712), .A1(Data_array_SWR[8]), .B0(
Raw_mant_NRM_SWR[35]), .B1(n2559), .Y(n2566) );
AOI22X1TS U3363 ( .A0(n2712), .A1(n1940), .B0(n2810), .B1(n2567), .Y(n2569)
);
NAND2X1TS U3364 ( .A(Raw_mant_NRM_SWR[42]), .B(n2559), .Y(n2568) );
AOI22X1TS U3365 ( .A0(n2815), .A1(Data_array_SWR[26]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n2643), .Y(n2572) );
AOI22X1TS U3366 ( .A0(n2712), .A1(n1942), .B0(Raw_mant_NRM_SWR[40]), .B1(
n2559), .Y(n2574) );
AOI22X1TS U3367 ( .A0(n2712), .A1(n1944), .B0(Raw_mant_NRM_SWR[38]), .B1(
n2559), .Y(n2577) );
AOI22X1TS U3368 ( .A0(n2811), .A1(Data_array_SWR[29]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n2559), .Y(n2580) );
AOI22X1TS U3369 ( .A0(n2819), .A1(Data_array_SWR[16]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n2643), .Y(n2582) );
AOI22X1TS U3370 ( .A0(n2815), .A1(Data_array_SWR[27]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n2643), .Y(n2585) );
AOI22X1TS U3371 ( .A0(n2712), .A1(n1951), .B0(n1950), .B1(n2559), .Y(n2588)
);
AOI22X1TS U3372 ( .A0(n2712), .A1(Data_array_SWR[2]), .B0(n2810), .B1(n2590),
.Y(n2592) );
NAND2X1TS U3373 ( .A(Raw_mant_NRM_SWR[49]), .B(n2559), .Y(n2591) );
AOI22X1TS U3374 ( .A0(n2819), .A1(Data_array_SWR[14]), .B0(
Raw_mant_NRM_SWR[26]), .B1(n2559), .Y(n2595) );
AOI22X1TS U3375 ( .A0(n2819), .A1(n1953), .B0(Raw_mant_NRM_SWR[17]), .B1(
n2643), .Y(n2598) );
AOI22X1TS U3376 ( .A0(n2815), .A1(Data_array_SWR[22]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n2643), .Y(n2600) );
AOI22X1TS U3377 ( .A0(n2815), .A1(Data_array_SWR[24]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n2643), .Y(n2603) );
AOI22X1TS U3378 ( .A0(n2712), .A1(n1958), .B0(Raw_mant_NRM_SWR[31]), .B1(
n2559), .Y(n2606) );
AOI22X1TS U3379 ( .A0(n2815), .A1(n1935), .B0(Raw_mant_NRM_SWR[13]), .B1(
n2643), .Y(n2610) );
AOI22X1TS U3380 ( .A0(n2712), .A1(n1946), .B0(Raw_mant_NRM_SWR[36]), .B1(
n2559), .Y(n2612) );
AOI22X1TS U3381 ( .A0(n2815), .A1(n1934), .B0(Raw_mant_NRM_SWR[15]), .B1(
n2643), .Y(n2616) );
AOI22X1TS U3382 ( .A0(n2819), .A1(n1955), .B0(Raw_mant_NRM_SWR[20]), .B1(
n2643), .Y(n2619) );
AOI22X1TS U3383 ( .A0(n2712), .A1(n1959), .B0(Raw_mant_NRM_SWR[29]), .B1(
n2559), .Y(n2621) );
AOI22X1TS U3384 ( .A0(n2819), .A1(Data_array_SWR[13]), .B0(
Raw_mant_NRM_SWR[27]), .B1(n2559), .Y(n2625) );
AOI22X1TS U3385 ( .A0(n2815), .A1(n1939), .B0(Raw_mant_NRM_SWR[43]), .B1(
n2559), .Y(n2628) );
AOI22X1TS U3386 ( .A0(n2811), .A1(Data_array_SWR[31]), .B0(
Raw_mant_NRM_SWR[1]), .B1(n2559), .Y(n2633) );
AOI22X1TS U3387 ( .A0(n2819), .A1(Data_array_SWR[17]), .B0(
Raw_mant_NRM_SWR[22]), .B1(n2643), .Y(n2637) );
AOI22X1TS U3388 ( .A0(n2815), .A1(Data_array_SWR[5]), .B0(
Raw_mant_NRM_SWR[46]), .B1(n2559), .Y(n2641) );
AOI22X1TS U3389 ( .A0(n2819), .A1(n1952), .B0(Raw_mant_NRM_SWR[18]), .B1(
n2643), .Y(n2646) );
AOI22X1TS U3390 ( .A0(n2811), .A1(n1948), .B0(Raw_mant_NRM_SWR[1]), .B1(
n1826), .Y(n2651) );
AOI22X1TS U3391 ( .A0(n2819), .A1(n1956), .B0(n2718), .B1(
DmP_mant_SHT1_SW[26]), .Y(n2654) );
AOI22X1TS U3392 ( .A0(n2819), .A1(Data_array_SWR[15]), .B0(
Raw_mant_NRM_SWR[27]), .B1(n1914), .Y(n2657) );
AOI222X1TS U3393 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n2087), .B0(
Raw_mant_NRM_SWR[13]), .B1(n2708), .C0(n2623), .C1(n1930), .Y(n2682)
);
AOI22X1TS U3394 ( .A0(n2815), .A1(Data_array_SWR[21]), .B0(n2718), .B1(
DmP_mant_SHT1_SW[37]), .Y(n2660) );
AOI22X1TS U3395 ( .A0(n2712), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[36]), .B1(n1914), .Y(n2663) );
AOI22X1TS U3396 ( .A0(n2819), .A1(n1957), .B0(n2718), .B1(
DmP_mant_SHT1_SW[28]), .Y(n2666) );
AOI22X1TS U3397 ( .A0(n2712), .A1(Data_array_SWR[11]), .B0(n2718), .B1(n1938), .Y(n2669) );
AOI222X1TS U3398 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n2087), .B0(
Raw_mant_NRM_SWR[9]), .B1(n2708), .C0(n2623), .C1(n1928), .Y(n2674) );
AOI22X1TS U3399 ( .A0(n2815), .A1(Data_array_SWR[25]), .B0(n2718), .B1(
DmP_mant_SHT1_SW[41]), .Y(n2672) );
AOI222X1TS U3400 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n2667), .B0(
Raw_mant_NRM_SWR[11]), .B1(n2708), .C0(n2623), .C1(n1929), .Y(n2685)
);
AOI22X1TS U3401 ( .A0(n2815), .A1(n1943), .B0(n2718), .B1(
DmP_mant_SHT1_SW[43]), .Y(n2676) );
AOI22X1TS U3402 ( .A0(n2815), .A1(n1949), .B0(Raw_mant_NRM_SWR[18]), .B1(
n1914), .Y(n2681) );
AOI22X1TS U3403 ( .A0(n2815), .A1(Data_array_SWR[23]), .B0(n2718), .B1(
DmP_mant_SHT1_SW[39]), .Y(n2684) );
AOI22X1TS U3404 ( .A0(n2712), .A1(Data_array_SWR[10]), .B0(n2718), .B1(
DmP_mant_SHT1_SW[17]), .Y(n2688) );
AOI22X1TS U3405 ( .A0(n2815), .A1(n1936), .B0(n2718), .B1(
DmP_mant_SHT1_SW[35]), .Y(n2693) );
AOI22X1TS U3406 ( .A0(n2712), .A1(n1941), .B0(Raw_mant_NRM_SWR[43]), .B1(
n1826), .Y(n2697) );
AOI22X1TS U3407 ( .A0(n2819), .A1(n1954), .B0(n2718), .B1(
DmP_mant_SHT1_SW[30]), .Y(n2701) );
AOI22X1TS U3408 ( .A0(n2819), .A1(Data_array_SWR[12]), .B0(n2718), .B1(n1937), .Y(n2705) );
AOI22X1TS U3409 ( .A0(n2815), .A1(Data_array_SWR[28]), .B0(n2718), .B1(
DmP_mant_SHT1_SW[45]), .Y(n2711) );
AOI22X1TS U3410 ( .A0(n2712), .A1(n1947), .B0(Raw_mant_NRM_SWR[39]), .B1(
n1914), .Y(n2715) );
AOI22X1TS U3411 ( .A0(n2811), .A1(Data_array_SWR[30]), .B0(
DmP_mant_SHT1_SW[47]), .B1(n2718), .Y(n2723) );
NAND2X1TS U3412 ( .A(n3370), .B(LZD_output_NRM2_EW[0]), .Y(
DP_OP_15J75_123_4372_n11) );
MX2X1TS U3413 ( .A(DMP_exp_NRM2_EW[10]), .B(DMP_exp_NRM_EW[10]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1332) );
MX2X1TS U3414 ( .A(DMP_exp_NRM2_EW[9]), .B(DMP_exp_NRM_EW[9]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1337) );
MX2X1TS U3415 ( .A(DMP_exp_NRM2_EW[8]), .B(DMP_exp_NRM_EW[8]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1342) );
MX2X1TS U3416 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1347) );
MX2X1TS U3417 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1352) );
MX2X1TS U3418 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1357) );
MX2X1TS U3419 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(n1970),
.Y(n1362) );
MX2X1TS U3420 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n1970),
.Y(n1367) );
MX2X1TS U3421 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(n1970),
.Y(n1372) );
MX2X1TS U3422 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(n1970),
.Y(n1377) );
MX2X1TS U3423 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1382) );
AOI22X1TS U3424 ( .A0(Raw_mant_NRM_SWR[9]), .A1(n2727), .B0(
Raw_mant_NRM_SWR[10]), .B1(n2726), .Y(n2730) );
AOI32X1TS U3425 ( .A0(n2731), .A1(n2730), .A2(n3328), .B0(n2729), .B1(n2730),
.Y(n2738) );
OAI31X1TS U3426 ( .A0(n2741), .A1(n2740), .A2(n2739), .B0(
Shift_reg_FLAGS_7[1]), .Y(n2820) );
OAI2BB1X1TS U3427 ( .A0N(LZD_output_NRM2_EW[5]), .A1N(n1969), .B0(n2820),
.Y(n1161) );
NOR2XLTS U3428 ( .A(Raw_mant_NRM_SWR[2]), .B(Raw_mant_NRM_SWR[1]), .Y(n2754)
);
INVX2TS U3429 ( .A(n2742), .Y(n2743) );
OAI211XLTS U3430 ( .A0(n3454), .A1(n2748), .B0(n2747), .C0(n2746), .Y(n2749)
);
OAI211XLTS U3431 ( .A0(n2754), .A1(n2753), .B0(n2752), .C0(n2751), .Y(n2755)
);
OAI31X1TS U3432 ( .A0(n2757), .A1(n2756), .A2(n2755), .B0(
Shift_reg_FLAGS_7[1]), .Y(n2816) );
OAI2BB1X1TS U3433 ( .A0N(LZD_output_NRM2_EW[4]), .A1N(n1969), .B0(n2816),
.Y(n1155) );
OAI2BB1X1TS U3434 ( .A0N(LZD_output_NRM2_EW[3]), .A1N(n1969), .B0(n2758),
.Y(n1148) );
AO22XLTS U3435 ( .A0(n2762), .A1(Raw_mant_NRM_SWR[34]), .B0(
Raw_mant_NRM_SWR[32]), .B1(n2761), .Y(n2764) );
OAI211XLTS U3436 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n2768), .B0(n2767), .C0(
n2766), .Y(n2774) );
OAI211XLTS U3437 ( .A0(n3327), .A1(n2771), .B0(n2770), .C0(n2769), .Y(n2773)
);
OAI31X1TS U3438 ( .A0(n2775), .A1(n2774), .A2(n2773), .B0(
Shift_reg_FLAGS_7[1]), .Y(n2813) );
OAI2BB1X1TS U3439 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n1969), .B0(n2813),
.Y(n1137) );
OAI2BB1X1TS U3440 ( .A0N(LZD_output_NRM2_EW[1]), .A1N(n1969), .B0(n2776),
.Y(n1151) );
OAI2BB1X1TS U3441 ( .A0N(LZD_output_NRM2_EW[0]), .A1N(n1969), .B0(n2777),
.Y(n1158) );
OA22X1TS U3442 ( .A0(n2784), .A1(n2779), .B0(n3468), .B1(
final_result_ieee[52]), .Y(n1619) );
OA22X1TS U3443 ( .A0(n2784), .A1(exp_rslt_NRM2_EW1[1]), .B0(n3468), .B1(
final_result_ieee[53]), .Y(n1618) );
OA22X1TS U3444 ( .A0(n2784), .A1(exp_rslt_NRM2_EW1[2]), .B0(n3468), .B1(
final_result_ieee[54]), .Y(n1617) );
OA22X1TS U3445 ( .A0(n2784), .A1(exp_rslt_NRM2_EW1[3]), .B0(n3468), .B1(
final_result_ieee[55]), .Y(n1616) );
OA22X1TS U3446 ( .A0(n2784), .A1(exp_rslt_NRM2_EW1[4]), .B0(n3468), .B1(
final_result_ieee[56]), .Y(n1615) );
OA22X1TS U3447 ( .A0(n2784), .A1(exp_rslt_NRM2_EW1[5]), .B0(n3468), .B1(
final_result_ieee[57]), .Y(n1614) );
OA22X1TS U3448 ( .A0(n2784), .A1(n2780), .B0(n3468), .B1(
final_result_ieee[58]), .Y(n1613) );
OA22X1TS U3449 ( .A0(n2784), .A1(n2781), .B0(n3468), .B1(
final_result_ieee[59]), .Y(n1612) );
OA22X1TS U3450 ( .A0(n2784), .A1(n2782), .B0(n3468), .B1(
final_result_ieee[60]), .Y(n1611) );
OA22X1TS U3451 ( .A0(n2784), .A1(n2783), .B0(n3468), .B1(
final_result_ieee[61]), .Y(n1610) );
INVX4TS U3452 ( .A(n2146), .Y(n3253) );
AO22XLTS U3453 ( .A0(n3253), .A1(n2785), .B0(n3225), .B1(
final_result_ieee[62]), .Y(n1609) );
INVX2TS U3454 ( .A(n2786), .Y(n2788) );
AOI22X1TS U3455 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n2788), .B1(n3332), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U3456 ( .A(n2788), .B(n2787), .Y(n1824) );
AO22XLTS U3457 ( .A0(n2790), .A1(n2873), .B0(n2792), .B1(n2789), .Y(n1822)
);
AOI22X1TS U3458 ( .A0(n2792), .A1(n3134), .B0(n1969), .B1(n2790), .Y(n1817)
);
AOI22X1TS U3459 ( .A0(n2792), .A1(n1969), .B0(n3240), .B1(n2790), .Y(n1816)
);
BUFX4TS U3460 ( .A(n2799), .Y(n2794) );
BUFX3TS U3461 ( .A(n2793), .Y(n2805) );
AO22XLTS U3462 ( .A0(n2799), .A1(Data_X[3]), .B0(n2806), .B1(intDX_EWSW[3]),
.Y(n1812) );
INVX4TS U3463 ( .A(n2796), .Y(n2797) );
AO22XLTS U3464 ( .A0(n2805), .A1(Data_X[8]), .B0(n2802), .B1(intDX_EWSW[8]),
.Y(n1807) );
AO22XLTS U3465 ( .A0(n2805), .A1(Data_X[11]), .B0(n2800), .B1(intDX_EWSW[11]), .Y(n1804) );
AO22XLTS U3466 ( .A0(n2805), .A1(Data_X[12]), .B0(n2797), .B1(intDX_EWSW[12]), .Y(n1803) );
AO22XLTS U3467 ( .A0(n2794), .A1(Data_X[15]), .B0(n2802), .B1(intDX_EWSW[15]), .Y(n1800) );
AO22XLTS U3468 ( .A0(n2796), .A1(Data_X[17]), .B0(n2797), .B1(intDX_EWSW[17]), .Y(n1798) );
AO22XLTS U3469 ( .A0(n2796), .A1(Data_X[18]), .B0(n2802), .B1(intDX_EWSW[18]), .Y(n1797) );
AO22XLTS U3470 ( .A0(n2796), .A1(Data_X[19]), .B0(n2803), .B1(intDX_EWSW[19]), .Y(n1796) );
AO22XLTS U3471 ( .A0(n2796), .A1(Data_X[20]), .B0(n2806), .B1(intDX_EWSW[20]), .Y(n1795) );
AO22XLTS U3472 ( .A0(n2796), .A1(Data_X[21]), .B0(n2800), .B1(intDX_EWSW[21]), .Y(n1794) );
AO22XLTS U3473 ( .A0(n2796), .A1(Data_X[22]), .B0(n2797), .B1(intDX_EWSW[22]), .Y(n1793) );
AO22XLTS U3474 ( .A0(n2796), .A1(Data_X[23]), .B0(n2131), .B1(intDX_EWSW[23]), .Y(n1792) );
AO22XLTS U3475 ( .A0(n2796), .A1(Data_X[25]), .B0(n2800), .B1(intDX_EWSW[25]), .Y(n1790) );
AO22XLTS U3476 ( .A0(n2805), .A1(Data_X[26]), .B0(n2797), .B1(intDX_EWSW[26]), .Y(n1789) );
AO22XLTS U3477 ( .A0(n2794), .A1(Data_X[27]), .B0(n2803), .B1(intDX_EWSW[27]), .Y(n1788) );
AO22XLTS U3478 ( .A0(n2794), .A1(Data_X[28]), .B0(n2806), .B1(intDX_EWSW[28]), .Y(n1787) );
AO22XLTS U3479 ( .A0(n2794), .A1(Data_X[29]), .B0(n2803), .B1(intDX_EWSW[29]), .Y(n1786) );
AO22XLTS U3480 ( .A0(n2794), .A1(Data_X[30]), .B0(n2795), .B1(intDX_EWSW[30]), .Y(n1785) );
AO22XLTS U3481 ( .A0(n2794), .A1(Data_X[31]), .B0(n2802), .B1(intDX_EWSW[31]), .Y(n1784) );
AO22XLTS U3482 ( .A0(n2794), .A1(Data_X[33]), .B0(n2795), .B1(intDX_EWSW[33]), .Y(n1782) );
AO22XLTS U3483 ( .A0(n2793), .A1(Data_X[45]), .B0(n2807), .B1(intDX_EWSW[45]), .Y(n1770) );
AO22XLTS U3484 ( .A0(n2793), .A1(Data_X[46]), .B0(n2807), .B1(intDX_EWSW[46]), .Y(n1769) );
AO22XLTS U3485 ( .A0(n2794), .A1(Data_X[49]), .B0(n2807), .B1(intDX_EWSW[49]), .Y(n1766) );
AO22XLTS U3486 ( .A0(n2798), .A1(Data_X[50]), .B0(n2807), .B1(intDX_EWSW[50]), .Y(n1765) );
AO22XLTS U3487 ( .A0(n2798), .A1(Data_X[51]), .B0(n2807), .B1(intDX_EWSW[51]), .Y(n1764) );
AO22XLTS U3488 ( .A0(n2797), .A1(intDX_EWSW[53]), .B0(n2808), .B1(Data_X[53]), .Y(n1762) );
AO22XLTS U3489 ( .A0(n2797), .A1(intDX_EWSW[54]), .B0(n2808), .B1(Data_X[54]), .Y(n1761) );
AO22XLTS U3490 ( .A0(n2797), .A1(intDX_EWSW[55]), .B0(n2808), .B1(Data_X[55]), .Y(n1760) );
AO22XLTS U3491 ( .A0(n2797), .A1(intDX_EWSW[56]), .B0(n2808), .B1(Data_X[56]), .Y(n1759) );
AO22XLTS U3492 ( .A0(n2798), .A1(Data_X[57]), .B0(n2807), .B1(intDX_EWSW[57]), .Y(n1758) );
AO22XLTS U3493 ( .A0(n2798), .A1(Data_X[58]), .B0(n2807), .B1(intDX_EWSW[58]), .Y(n1757) );
AO22XLTS U3494 ( .A0(n2798), .A1(Data_X[59]), .B0(n2807), .B1(intDX_EWSW[59]), .Y(n1756) );
AO22XLTS U3495 ( .A0(n2798), .A1(Data_X[60]), .B0(n2807), .B1(intDX_EWSW[60]), .Y(n1755) );
AO22XLTS U3496 ( .A0(n2794), .A1(add_subt), .B0(n2795), .B1(intAS), .Y(n1751) );
AO22XLTS U3497 ( .A0(n2795), .A1(intDY_EWSW[0]), .B0(n2808), .B1(Data_Y[0]),
.Y(n1749) );
AO22XLTS U3498 ( .A0(n2795), .A1(intDY_EWSW[1]), .B0(n2808), .B1(Data_Y[1]),
.Y(n1748) );
AO22XLTS U3499 ( .A0(n2807), .A1(intDY_EWSW[2]), .B0(n2808), .B1(Data_Y[2]),
.Y(n1747) );
AO22XLTS U3500 ( .A0(n2795), .A1(intDY_EWSW[3]), .B0(n2808), .B1(Data_Y[3]),
.Y(n1746) );
AO22XLTS U3501 ( .A0(n2807), .A1(intDY_EWSW[4]), .B0(n2808), .B1(Data_Y[4]),
.Y(n1745) );
AO22XLTS U3502 ( .A0(n2807), .A1(intDY_EWSW[5]), .B0(n2808), .B1(Data_Y[5]),
.Y(n1744) );
AO22XLTS U3503 ( .A0(n2807), .A1(intDY_EWSW[6]), .B0(n2808), .B1(Data_Y[6]),
.Y(n1743) );
AO22XLTS U3504 ( .A0(n2795), .A1(intDY_EWSW[7]), .B0(n2808), .B1(Data_Y[7]),
.Y(n1742) );
AO22XLTS U3505 ( .A0(n2797), .A1(intDY_EWSW[8]), .B0(n2796), .B1(Data_Y[8]),
.Y(n1741) );
AO22XLTS U3506 ( .A0(n2797), .A1(intDY_EWSW[9]), .B0(n2798), .B1(Data_Y[9]),
.Y(n1740) );
AO22XLTS U3507 ( .A0(n2797), .A1(intDY_EWSW[10]), .B0(n2798), .B1(Data_Y[10]), .Y(n1739) );
AO22XLTS U3508 ( .A0(n2797), .A1(intDY_EWSW[11]), .B0(n2798), .B1(Data_Y[11]), .Y(n1738) );
AO22XLTS U3509 ( .A0(n2797), .A1(intDY_EWSW[12]), .B0(n2804), .B1(Data_Y[12]), .Y(n1737) );
AO22XLTS U3510 ( .A0(n2797), .A1(intDY_EWSW[13]), .B0(n2796), .B1(Data_Y[13]), .Y(n1736) );
AO22XLTS U3511 ( .A0(n2797), .A1(intDY_EWSW[14]), .B0(n2796), .B1(Data_Y[14]), .Y(n1735) );
AO22XLTS U3512 ( .A0(n2797), .A1(intDY_EWSW[15]), .B0(n2798), .B1(Data_Y[15]), .Y(n1734) );
AO22XLTS U3513 ( .A0(n2800), .A1(intDY_EWSW[16]), .B0(n2804), .B1(Data_Y[16]), .Y(n1733) );
AO22XLTS U3514 ( .A0(n2800), .A1(intDY_EWSW[17]), .B0(n2798), .B1(Data_Y[17]), .Y(n1732) );
AO22XLTS U3515 ( .A0(n2800), .A1(intDY_EWSW[18]), .B0(n2804), .B1(Data_Y[18]), .Y(n1731) );
AO22XLTS U3516 ( .A0(n2800), .A1(intDY_EWSW[19]), .B0(n2798), .B1(Data_Y[19]), .Y(n1730) );
AO22XLTS U3517 ( .A0(n2800), .A1(intDY_EWSW[20]), .B0(n2808), .B1(Data_Y[20]), .Y(n1729) );
AO22XLTS U3518 ( .A0(n2800), .A1(intDY_EWSW[21]), .B0(n2804), .B1(Data_Y[21]), .Y(n1728) );
AO22XLTS U3519 ( .A0(n2800), .A1(intDY_EWSW[22]), .B0(n2804), .B1(Data_Y[22]), .Y(n1727) );
AO22XLTS U3520 ( .A0(n2800), .A1(intDY_EWSW[23]), .B0(n2804), .B1(Data_Y[23]), .Y(n1726) );
AO22XLTS U3521 ( .A0(n2800), .A1(intDY_EWSW[24]), .B0(n2804), .B1(Data_Y[24]), .Y(n1725) );
AO22XLTS U3522 ( .A0(n2800), .A1(intDY_EWSW[25]), .B0(n2804), .B1(Data_Y[25]), .Y(n1724) );
AO22XLTS U3523 ( .A0(n2800), .A1(intDY_EWSW[26]), .B0(n2799), .B1(Data_Y[26]), .Y(n1723) );
AO22XLTS U3524 ( .A0(n2800), .A1(intDY_EWSW[27]), .B0(n2804), .B1(Data_Y[27]), .Y(n1722) );
AO22XLTS U3525 ( .A0(n2802), .A1(intDY_EWSW[28]), .B0(n2801), .B1(Data_Y[28]), .Y(n1721) );
AO22XLTS U3526 ( .A0(n2802), .A1(intDY_EWSW[29]), .B0(n2801), .B1(Data_Y[29]), .Y(n1720) );
AO22XLTS U3527 ( .A0(n2802), .A1(intDY_EWSW[30]), .B0(n2804), .B1(Data_Y[30]), .Y(n1719) );
AO22XLTS U3528 ( .A0(n2802), .A1(intDY_EWSW[31]), .B0(n2801), .B1(Data_Y[31]), .Y(n1718) );
AO22XLTS U3529 ( .A0(n2802), .A1(intDY_EWSW[32]), .B0(n2801), .B1(Data_Y[32]), .Y(n1717) );
AO22XLTS U3530 ( .A0(n2802), .A1(intDY_EWSW[33]), .B0(n2801), .B1(Data_Y[33]), .Y(n1716) );
AO22XLTS U3531 ( .A0(n2802), .A1(intDY_EWSW[34]), .B0(n2794), .B1(Data_Y[34]), .Y(n1715) );
AO22XLTS U3532 ( .A0(n2802), .A1(intDY_EWSW[35]), .B0(n2808), .B1(Data_Y[35]), .Y(n1714) );
AO22XLTS U3533 ( .A0(n2802), .A1(intDY_EWSW[36]), .B0(n2794), .B1(Data_Y[36]), .Y(n1713) );
AO22XLTS U3534 ( .A0(n2802), .A1(intDY_EWSW[37]), .B0(n2801), .B1(Data_Y[37]), .Y(n1712) );
AO22XLTS U3535 ( .A0(n2802), .A1(intDY_EWSW[38]), .B0(n2805), .B1(Data_Y[38]), .Y(n1711) );
AO22XLTS U3536 ( .A0(n2802), .A1(intDY_EWSW[39]), .B0(n2799), .B1(Data_Y[39]), .Y(n1710) );
AO22XLTS U3537 ( .A0(n2803), .A1(intDY_EWSW[49]), .B0(n2805), .B1(Data_Y[49]), .Y(n1700) );
AO22XLTS U3538 ( .A0(n2806), .A1(intDY_EWSW[52]), .B0(n2804), .B1(Data_Y[52]), .Y(n1697) );
AO22XLTS U3539 ( .A0(n2806), .A1(intDY_EWSW[54]), .B0(n2805), .B1(Data_Y[54]), .Y(n1695) );
AOI22X1TS U3540 ( .A0(n2811), .A1(Data_array_SWR[33]), .B0(n2810), .B1(n2809), .Y(n2812) );
OAI2BB1X1TS U3541 ( .A0N(Raw_mant_NRM_SWR[0]), .A1N(n1826), .B0(n2812), .Y(
n1684) );
AOI22X1TS U3542 ( .A0(n2819), .A1(shift_value_SHT2_EWR[2]), .B0(
Shift_amount_SHT1_EWR[2]), .B1(n2818), .Y(n2814) );
NAND2X1TS U3543 ( .A(n2814), .B(n2813), .Y(n1630) );
AOI22X1TS U3544 ( .A0(n2815), .A1(shift_value_SHT2_EWR[4]), .B0(n2818), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n2817) );
NAND2X1TS U3545 ( .A(n2817), .B(n2816), .Y(n1628) );
AOI22X1TS U3546 ( .A0(n2819), .A1(shift_value_SHT2_EWR[5]), .B0(n2818), .B1(
Shift_amount_SHT1_EWR[5]), .Y(n2821) );
NAND2X1TS U3547 ( .A(n2821), .B(n2820), .Y(n1626) );
NAND2X1TS U3548 ( .A(DmP_EXP_EWSW[52]), .B(n3458), .Y(n2826) );
OAI21XLTS U3549 ( .A0(DmP_EXP_EWSW[52]), .A1(n3458), .B0(n2826), .Y(n2822)
);
NAND2X1TS U3550 ( .A(DmP_EXP_EWSW[53]), .B(n3351), .Y(n2825) );
OAI21XLTS U3551 ( .A0(DmP_EXP_EWSW[53]), .A1(n3351), .B0(n2825), .Y(n2823)
);
XNOR2X1TS U3552 ( .A(n2826), .B(n2823), .Y(n2824) );
BUFX3TS U3553 ( .A(n2877), .Y(n2849) );
AO22XLTS U3554 ( .A0(n2848), .A1(n2824), .B0(n2849), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n1624) );
AOI22X1TS U3555 ( .A0(DMP_EXP_EWSW[53]), .A1(n3356), .B0(n2826), .B1(n2825),
.Y(n2829) );
NOR2X1TS U3556 ( .A(n3353), .B(DMP_EXP_EWSW[54]), .Y(n2830) );
AOI21X1TS U3557 ( .A0(DMP_EXP_EWSW[54]), .A1(n3353), .B0(n2830), .Y(n2827)
);
XNOR2X1TS U3558 ( .A(n2829), .B(n2827), .Y(n2828) );
AO22XLTS U3559 ( .A0(n2848), .A1(n2828), .B0(n2849), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n1623) );
OAI22X1TS U3560 ( .A0(n2830), .A1(n2829), .B0(DmP_EXP_EWSW[54]), .B1(n3355),
.Y(n2833) );
NAND2X1TS U3561 ( .A(DmP_EXP_EWSW[55]), .B(n3354), .Y(n2834) );
XNOR2X1TS U3562 ( .A(n2833), .B(n2831), .Y(n2832) );
AO22XLTS U3563 ( .A0(n2848), .A1(n2832), .B0(n2849), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n1622) );
AOI22X1TS U3564 ( .A0(DMP_EXP_EWSW[55]), .A1(n3360), .B0(n2834), .B1(n2833),
.Y(n2837) );
NOR2X1TS U3565 ( .A(n3357), .B(DMP_EXP_EWSW[56]), .Y(n2838) );
AOI21X1TS U3566 ( .A0(DMP_EXP_EWSW[56]), .A1(n3357), .B0(n2838), .Y(n2835)
);
XNOR2X1TS U3567 ( .A(n2837), .B(n2835), .Y(n2836) );
AO22XLTS U3568 ( .A0(n2848), .A1(n2836), .B0(n2849), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n1621) );
OAI22X1TS U3569 ( .A0(n2838), .A1(n2837), .B0(DmP_EXP_EWSW[56]), .B1(n3359),
.Y(n2840) );
XNOR2X1TS U3570 ( .A(DmP_EXP_EWSW[57]), .B(DMP_EXP_EWSW[57]), .Y(n2839) );
XOR2XLTS U3571 ( .A(n2840), .B(n2839), .Y(n2841) );
AO22XLTS U3572 ( .A0(n2848), .A1(n2841), .B0(n2849), .B1(
Shift_amount_SHT1_EWR[5]), .Y(n1620) );
OAI222X1TS U3573 ( .A0(n2842), .A1(n3464), .B0(n3351), .B1(n2873), .C0(n3313), .C1(n2874), .Y(n1555) );
OAI222X1TS U3574 ( .A0(n2842), .A1(n3358), .B0(n3355), .B1(n2873), .C0(n3312), .C1(n2874), .Y(n1554) );
OAI222X1TS U3575 ( .A0(n2842), .A1(n3465), .B0(n3354), .B1(n2873), .C0(n3309), .C1(n2874), .Y(n1553) );
OAI222X1TS U3576 ( .A0(n2871), .A1(n3314), .B0(n3359), .B1(n2873), .C0(n3310), .C1(n2874), .Y(n1552) );
OAI21XLTS U3577 ( .A0(n2844), .A1(intDX_EWSW[63]), .B0(n2873), .Y(n2843) );
AOI21X1TS U3578 ( .A0(n2844), .A1(intDX_EWSW[63]), .B0(n2843), .Y(n2846) );
AO21XLTS U3579 ( .A0(OP_FLAG_EXP), .A1(n1997), .B0(n2846), .Y(n1545) );
AO22XLTS U3580 ( .A0(n2847), .A1(n2846), .B0(ZERO_FLAG_EXP), .B1(n1933), .Y(
n1544) );
AO22XLTS U3581 ( .A0(n2848), .A1(DMP_EXP_EWSW[0]), .B0(n2849), .B1(
DMP_SHT1_EWSW[0]), .Y(n1542) );
AO22XLTS U3582 ( .A0(n2851), .A1(DMP_SHT1_EWSW[0]), .B0(n3462), .B1(
DMP_SHT2_EWSW[0]), .Y(n1541) );
AO22XLTS U3583 ( .A0(n2848), .A1(DMP_EXP_EWSW[1]), .B0(n2849), .B1(
DMP_SHT1_EWSW[1]), .Y(n1539) );
AO22XLTS U3584 ( .A0(n2851), .A1(DMP_SHT1_EWSW[1]), .B0(n2859), .B1(
DMP_SHT2_EWSW[1]), .Y(n1538) );
INVX2TS U3585 ( .A(n3295), .Y(n2854) );
BUFX3TS U3586 ( .A(n3295), .Y(n2864) );
AO22XLTS U3587 ( .A0(n2848), .A1(DMP_EXP_EWSW[2]), .B0(n2849), .B1(
DMP_SHT1_EWSW[2]), .Y(n1536) );
AO22XLTS U3588 ( .A0(n2851), .A1(DMP_SHT1_EWSW[2]), .B0(n2859), .B1(
DMP_SHT2_EWSW[2]), .Y(n1535) );
INVX4TS U3589 ( .A(n3295), .Y(n3297) );
AO22XLTS U3590 ( .A0(n2852), .A1(DMP_SFG[2]), .B0(n2858), .B1(
DMP_SHT2_EWSW[2]), .Y(n1534) );
AO22XLTS U3591 ( .A0(n2848), .A1(DMP_EXP_EWSW[3]), .B0(n2849), .B1(
DMP_SHT1_EWSW[3]), .Y(n1533) );
AO22XLTS U3592 ( .A0(n2851), .A1(DMP_SHT1_EWSW[3]), .B0(n2859), .B1(
DMP_SHT2_EWSW[3]), .Y(n1532) );
CLKBUFX2TS U3593 ( .A(n2852), .Y(n3279) );
BUFX4TS U3594 ( .A(n3279), .Y(n3293) );
AO22XLTS U3595 ( .A0(n3293), .A1(DMP_SFG[3]), .B0(n2854), .B1(
DMP_SHT2_EWSW[3]), .Y(n1531) );
AO22XLTS U3596 ( .A0(n2848), .A1(DMP_EXP_EWSW[4]), .B0(n2849), .B1(
DMP_SHT1_EWSW[4]), .Y(n1530) );
AO22XLTS U3597 ( .A0(n2851), .A1(DMP_SHT1_EWSW[4]), .B0(n2859), .B1(
DMP_SHT2_EWSW[4]), .Y(n1529) );
AO22XLTS U3598 ( .A0(n2848), .A1(DMP_EXP_EWSW[5]), .B0(n2849), .B1(
DMP_SHT1_EWSW[5]), .Y(n1527) );
AO22XLTS U3599 ( .A0(n2851), .A1(DMP_SHT1_EWSW[5]), .B0(n2859), .B1(
DMP_SHT2_EWSW[5]), .Y(n1526) );
AO22XLTS U3600 ( .A0(n2850), .A1(DMP_EXP_EWSW[6]), .B0(n2849), .B1(
DMP_SHT1_EWSW[6]), .Y(n1524) );
AO22XLTS U3601 ( .A0(n2851), .A1(DMP_SHT1_EWSW[6]), .B0(n2859), .B1(
DMP_SHT2_EWSW[6]), .Y(n1523) );
AO22XLTS U3602 ( .A0(n2850), .A1(DMP_EXP_EWSW[7]), .B0(n2849), .B1(
DMP_SHT1_EWSW[7]), .Y(n1521) );
AO22XLTS U3603 ( .A0(n2851), .A1(DMP_SHT1_EWSW[7]), .B0(n2859), .B1(
DMP_SHT2_EWSW[7]), .Y(n1520) );
AO22XLTS U3604 ( .A0(n2850), .A1(DMP_EXP_EWSW[8]), .B0(n2849), .B1(
DMP_SHT1_EWSW[8]), .Y(n1518) );
AO22XLTS U3605 ( .A0(n2851), .A1(DMP_SHT1_EWSW[8]), .B0(n2859), .B1(
DMP_SHT2_EWSW[8]), .Y(n1517) );
BUFX3TS U3606 ( .A(n3463), .Y(n2855) );
BUFX3TS U3607 ( .A(n2855), .Y(n2856) );
AO22XLTS U3608 ( .A0(n2850), .A1(DMP_EXP_EWSW[9]), .B0(n2856), .B1(
DMP_SHT1_EWSW[9]), .Y(n1515) );
AO22XLTS U3609 ( .A0(n2851), .A1(DMP_SHT1_EWSW[9]), .B0(n2859), .B1(
DMP_SHT2_EWSW[9]), .Y(n1514) );
AO22XLTS U3610 ( .A0(n2850), .A1(DMP_EXP_EWSW[10]), .B0(n2855), .B1(
DMP_SHT1_EWSW[10]), .Y(n1512) );
AO22XLTS U3611 ( .A0(n2851), .A1(DMP_SHT1_EWSW[10]), .B0(n2859), .B1(
DMP_SHT2_EWSW[10]), .Y(n1511) );
AO22XLTS U3612 ( .A0(n2850), .A1(DMP_EXP_EWSW[11]), .B0(n2855), .B1(
DMP_SHT1_EWSW[11]), .Y(n1509) );
AO22XLTS U3613 ( .A0(n2851), .A1(DMP_SHT1_EWSW[11]), .B0(n3462), .B1(
DMP_SHT2_EWSW[11]), .Y(n1508) );
AO22XLTS U3614 ( .A0(n2850), .A1(DMP_EXP_EWSW[12]), .B0(n2856), .B1(
DMP_SHT1_EWSW[12]), .Y(n1506) );
AO22XLTS U3615 ( .A0(n2851), .A1(DMP_SHT1_EWSW[12]), .B0(n3462), .B1(
DMP_SHT2_EWSW[12]), .Y(n1505) );
AO22XLTS U3616 ( .A0(n2850), .A1(DMP_EXP_EWSW[13]), .B0(n2856), .B1(
DMP_SHT1_EWSW[13]), .Y(n1503) );
AO22XLTS U3617 ( .A0(n2851), .A1(DMP_SHT1_EWSW[13]), .B0(n3462), .B1(
DMP_SHT2_EWSW[13]), .Y(n1502) );
AO22XLTS U3618 ( .A0(n2850), .A1(DMP_EXP_EWSW[14]), .B0(n3463), .B1(
DMP_SHT1_EWSW[14]), .Y(n1500) );
AO22XLTS U3619 ( .A0(n2851), .A1(DMP_SHT1_EWSW[14]), .B0(n3462), .B1(
DMP_SHT2_EWSW[14]), .Y(n1499) );
BUFX3TS U3620 ( .A(n3307), .Y(n2861) );
AO22XLTS U3621 ( .A0(n2850), .A1(DMP_EXP_EWSW[15]), .B0(n2855), .B1(
DMP_SHT1_EWSW[15]), .Y(n1497) );
AO22XLTS U3622 ( .A0(n2851), .A1(DMP_SHT1_EWSW[15]), .B0(n3462), .B1(
DMP_SHT2_EWSW[15]), .Y(n1496) );
BUFX3TS U3623 ( .A(n3307), .Y(n2857) );
AO22XLTS U3624 ( .A0(n2850), .A1(DMP_EXP_EWSW[16]), .B0(n2855), .B1(
DMP_SHT1_EWSW[16]), .Y(n1494) );
AO22XLTS U3625 ( .A0(n2851), .A1(DMP_SHT1_EWSW[16]), .B0(n3462), .B1(
DMP_SHT2_EWSW[16]), .Y(n1493) );
AO22XLTS U3626 ( .A0(n2850), .A1(DMP_EXP_EWSW[17]), .B0(n2855), .B1(
DMP_SHT1_EWSW[17]), .Y(n1491) );
AO22XLTS U3627 ( .A0(n2851), .A1(DMP_SHT1_EWSW[17]), .B0(n3462), .B1(
DMP_SHT2_EWSW[17]), .Y(n1490) );
INVX4TS U3628 ( .A(n2877), .Y(n2866) );
AO22XLTS U3629 ( .A0(n2866), .A1(DMP_EXP_EWSW[18]), .B0(n2855), .B1(
DMP_SHT1_EWSW[18]), .Y(n1488) );
AO22XLTS U3630 ( .A0(n2851), .A1(DMP_SHT1_EWSW[18]), .B0(n3462), .B1(
DMP_SHT2_EWSW[18]), .Y(n1487) );
AO22XLTS U3631 ( .A0(n2866), .A1(DMP_EXP_EWSW[19]), .B0(n2855), .B1(
DMP_SHT1_EWSW[19]), .Y(n1485) );
AO22XLTS U3632 ( .A0(busy), .A1(DMP_SHT1_EWSW[19]), .B0(n3462), .B1(
DMP_SHT2_EWSW[19]), .Y(n1484) );
AO22XLTS U3633 ( .A0(n2866), .A1(DMP_EXP_EWSW[20]), .B0(n2855), .B1(
DMP_SHT1_EWSW[20]), .Y(n1482) );
AO22XLTS U3634 ( .A0(busy), .A1(DMP_SHT1_EWSW[20]), .B0(n3462), .B1(
DMP_SHT2_EWSW[20]), .Y(n1481) );
AO22XLTS U3635 ( .A0(n2866), .A1(DMP_EXP_EWSW[21]), .B0(n2855), .B1(
DMP_SHT1_EWSW[21]), .Y(n1479) );
AO22XLTS U3636 ( .A0(busy), .A1(DMP_SHT1_EWSW[21]), .B0(n3462), .B1(
DMP_SHT2_EWSW[21]), .Y(n1478) );
AO22XLTS U3637 ( .A0(n2866), .A1(DMP_EXP_EWSW[22]), .B0(n2855), .B1(
DMP_SHT1_EWSW[22]), .Y(n1476) );
AO22XLTS U3638 ( .A0(busy), .A1(DMP_SHT1_EWSW[22]), .B0(n3462), .B1(
DMP_SHT2_EWSW[22]), .Y(n1475) );
AO22XLTS U3639 ( .A0(n2866), .A1(DMP_EXP_EWSW[23]), .B0(n2855), .B1(
DMP_SHT1_EWSW[23]), .Y(n1473) );
AO22XLTS U3640 ( .A0(busy), .A1(DMP_SHT1_EWSW[23]), .B0(n3462), .B1(
DMP_SHT2_EWSW[23]), .Y(n1472) );
BUFX3TS U3641 ( .A(n3295), .Y(n3130) );
AO22XLTS U3642 ( .A0(n2866), .A1(DMP_EXP_EWSW[24]), .B0(n2855), .B1(
DMP_SHT1_EWSW[24]), .Y(n1470) );
BUFX4TS U3643 ( .A(n3462), .Y(n2860) );
AO22XLTS U3644 ( .A0(busy), .A1(DMP_SHT1_EWSW[24]), .B0(n2860), .B1(
DMP_SHT2_EWSW[24]), .Y(n1469) );
AO22XLTS U3645 ( .A0(n2866), .A1(DMP_EXP_EWSW[25]), .B0(n2855), .B1(
DMP_SHT1_EWSW[25]), .Y(n1467) );
AO22XLTS U3646 ( .A0(busy), .A1(DMP_SHT1_EWSW[25]), .B0(n2860), .B1(
DMP_SHT2_EWSW[25]), .Y(n1466) );
AO22XLTS U3647 ( .A0(n2866), .A1(DMP_EXP_EWSW[26]), .B0(n2856), .B1(
DMP_SHT1_EWSW[26]), .Y(n1464) );
AO22XLTS U3648 ( .A0(busy), .A1(DMP_SHT1_EWSW[26]), .B0(n2860), .B1(
DMP_SHT2_EWSW[26]), .Y(n1463) );
AO22XLTS U3649 ( .A0(n2866), .A1(DMP_EXP_EWSW[27]), .B0(n2856), .B1(
DMP_SHT1_EWSW[27]), .Y(n1461) );
AO22XLTS U3650 ( .A0(n2862), .A1(DMP_SHT1_EWSW[27]), .B0(n2860), .B1(
DMP_SHT2_EWSW[27]), .Y(n1460) );
AO22XLTS U3651 ( .A0(n2866), .A1(DMP_EXP_EWSW[28]), .B0(n2856), .B1(
DMP_SHT1_EWSW[28]), .Y(n1458) );
AO22XLTS U3652 ( .A0(n2862), .A1(DMP_SHT1_EWSW[28]), .B0(n2860), .B1(
DMP_SHT2_EWSW[28]), .Y(n1457) );
AO22XLTS U3653 ( .A0(n2866), .A1(DMP_EXP_EWSW[29]), .B0(n2856), .B1(
DMP_SHT1_EWSW[29]), .Y(n1455) );
AO22XLTS U3654 ( .A0(n2862), .A1(DMP_SHT1_EWSW[29]), .B0(n2860), .B1(
DMP_SHT2_EWSW[29]), .Y(n1454) );
INVX4TS U3655 ( .A(n2877), .Y(n2868) );
AO22XLTS U3656 ( .A0(n2868), .A1(DMP_EXP_EWSW[30]), .B0(n2856), .B1(
DMP_SHT1_EWSW[30]), .Y(n1452) );
AO22XLTS U3657 ( .A0(n2862), .A1(DMP_SHT1_EWSW[30]), .B0(n2860), .B1(
DMP_SHT2_EWSW[30]), .Y(n1451) );
AO22XLTS U3658 ( .A0(n2868), .A1(DMP_EXP_EWSW[31]), .B0(n2856), .B1(
DMP_SHT1_EWSW[31]), .Y(n1449) );
AO22XLTS U3659 ( .A0(n2862), .A1(DMP_SHT1_EWSW[31]), .B0(n2860), .B1(
DMP_SHT2_EWSW[31]), .Y(n1448) );
AO22XLTS U3660 ( .A0(n2868), .A1(DMP_EXP_EWSW[32]), .B0(n2856), .B1(
DMP_SHT1_EWSW[32]), .Y(n1446) );
AO22XLTS U3661 ( .A0(n2862), .A1(DMP_SHT1_EWSW[32]), .B0(n2860), .B1(
DMP_SHT2_EWSW[32]), .Y(n1445) );
AO22XLTS U3662 ( .A0(n2868), .A1(DMP_EXP_EWSW[33]), .B0(n2856), .B1(
DMP_SHT1_EWSW[33]), .Y(n1443) );
AO22XLTS U3663 ( .A0(n2862), .A1(DMP_SHT1_EWSW[33]), .B0(n2860), .B1(
DMP_SHT2_EWSW[33]), .Y(n1442) );
AO22XLTS U3664 ( .A0(n2868), .A1(DMP_EXP_EWSW[34]), .B0(n2856), .B1(
DMP_SHT1_EWSW[34]), .Y(n1440) );
AO22XLTS U3665 ( .A0(n2862), .A1(DMP_SHT1_EWSW[34]), .B0(n2860), .B1(
DMP_SHT2_EWSW[34]), .Y(n1439) );
AO22XLTS U3666 ( .A0(n2868), .A1(DMP_EXP_EWSW[35]), .B0(n2856), .B1(
DMP_SHT1_EWSW[35]), .Y(n1437) );
AO22XLTS U3667 ( .A0(n2862), .A1(DMP_SHT1_EWSW[35]), .B0(n2860), .B1(
DMP_SHT2_EWSW[35]), .Y(n1436) );
AO22XLTS U3668 ( .A0(n2868), .A1(DMP_EXP_EWSW[36]), .B0(n2856), .B1(
DMP_SHT1_EWSW[36]), .Y(n1434) );
AO22XLTS U3669 ( .A0(n2862), .A1(DMP_SHT1_EWSW[36]), .B0(n2860), .B1(
DMP_SHT2_EWSW[36]), .Y(n1433) );
BUFX3TS U3670 ( .A(n3463), .Y(n2865) );
AO22XLTS U3671 ( .A0(n2868), .A1(DMP_EXP_EWSW[37]), .B0(n3463), .B1(
DMP_SHT1_EWSW[37]), .Y(n1431) );
AO22XLTS U3672 ( .A0(n2862), .A1(DMP_SHT1_EWSW[37]), .B0(n2860), .B1(
DMP_SHT2_EWSW[37]), .Y(n1430) );
AO22XLTS U3673 ( .A0(n2868), .A1(DMP_EXP_EWSW[38]), .B0(n3463), .B1(
DMP_SHT1_EWSW[38]), .Y(n1428) );
AO22XLTS U3674 ( .A0(n2862), .A1(DMP_SHT1_EWSW[38]), .B0(n2860), .B1(
DMP_SHT2_EWSW[38]), .Y(n1427) );
AO22XLTS U3675 ( .A0(n2868), .A1(DMP_EXP_EWSW[39]), .B0(n3463), .B1(
DMP_SHT1_EWSW[39]), .Y(n1425) );
AO22XLTS U3676 ( .A0(n2862), .A1(DMP_SHT1_EWSW[39]), .B0(n2860), .B1(
DMP_SHT2_EWSW[39]), .Y(n1424) );
AO22XLTS U3677 ( .A0(n2868), .A1(DMP_EXP_EWSW[40]), .B0(n3463), .B1(
DMP_SHT1_EWSW[40]), .Y(n1422) );
AO22XLTS U3678 ( .A0(n2863), .A1(DMP_SHT1_EWSW[40]), .B0(n2860), .B1(
DMP_SHT2_EWSW[40]), .Y(n1421) );
AO22XLTS U3679 ( .A0(n2868), .A1(DMP_EXP_EWSW[41]), .B0(n3463), .B1(
DMP_SHT1_EWSW[41]), .Y(n1419) );
AO22XLTS U3680 ( .A0(n2863), .A1(DMP_SHT1_EWSW[41]), .B0(n2860), .B1(
DMP_SHT2_EWSW[41]), .Y(n1418) );
INVX4TS U3681 ( .A(n2865), .Y(n2867) );
AO22XLTS U3682 ( .A0(n2867), .A1(DMP_EXP_EWSW[42]), .B0(n3463), .B1(
DMP_SHT1_EWSW[42]), .Y(n1416) );
AO22XLTS U3683 ( .A0(n2863), .A1(DMP_SHT1_EWSW[42]), .B0(n2860), .B1(
DMP_SHT2_EWSW[42]), .Y(n1415) );
AO22XLTS U3684 ( .A0(n2867), .A1(DMP_EXP_EWSW[43]), .B0(n3463), .B1(
DMP_SHT1_EWSW[43]), .Y(n1413) );
AO22XLTS U3685 ( .A0(n2863), .A1(DMP_SHT1_EWSW[43]), .B0(n2860), .B1(
DMP_SHT2_EWSW[43]), .Y(n1412) );
AO22XLTS U3686 ( .A0(n2867), .A1(DMP_EXP_EWSW[44]), .B0(n3463), .B1(
DMP_SHT1_EWSW[44]), .Y(n1410) );
BUFX4TS U3687 ( .A(n3462), .Y(n2881) );
AO22XLTS U3688 ( .A0(n2863), .A1(DMP_SHT1_EWSW[44]), .B0(n2881), .B1(
DMP_SHT2_EWSW[44]), .Y(n1409) );
AO22XLTS U3689 ( .A0(n2867), .A1(DMP_EXP_EWSW[45]), .B0(n3463), .B1(
DMP_SHT1_EWSW[45]), .Y(n1407) );
AO22XLTS U3690 ( .A0(n2863), .A1(DMP_SHT1_EWSW[45]), .B0(n2881), .B1(
DMP_SHT2_EWSW[45]), .Y(n1406) );
AO22XLTS U3691 ( .A0(n2867), .A1(DMP_EXP_EWSW[46]), .B0(n3463), .B1(
DMP_SHT1_EWSW[46]), .Y(n1404) );
AO22XLTS U3692 ( .A0(n2863), .A1(DMP_SHT1_EWSW[46]), .B0(n2881), .B1(
DMP_SHT2_EWSW[46]), .Y(n1403) );
AO22XLTS U3693 ( .A0(n2867), .A1(DMP_EXP_EWSW[47]), .B0(n3463), .B1(
DMP_SHT1_EWSW[47]), .Y(n1401) );
AO22XLTS U3694 ( .A0(n2863), .A1(DMP_SHT1_EWSW[47]), .B0(n2881), .B1(
DMP_SHT2_EWSW[47]), .Y(n1400) );
BUFX4TS U3695 ( .A(n2877), .Y(n2879) );
AO22XLTS U3696 ( .A0(n2867), .A1(DMP_EXP_EWSW[48]), .B0(n2879), .B1(
DMP_SHT1_EWSW[48]), .Y(n1398) );
AO22XLTS U3697 ( .A0(n2863), .A1(DMP_SHT1_EWSW[48]), .B0(n2881), .B1(
DMP_SHT2_EWSW[48]), .Y(n1397) );
AO22XLTS U3698 ( .A0(n2867), .A1(DMP_EXP_EWSW[49]), .B0(n2879), .B1(
DMP_SHT1_EWSW[49]), .Y(n1395) );
AO22XLTS U3699 ( .A0(n2863), .A1(DMP_SHT1_EWSW[49]), .B0(n2881), .B1(
DMP_SHT2_EWSW[49]), .Y(n1394) );
AO22XLTS U3700 ( .A0(n2867), .A1(DMP_EXP_EWSW[50]), .B0(n2879), .B1(
DMP_SHT1_EWSW[50]), .Y(n1392) );
AO22XLTS U3701 ( .A0(n2862), .A1(DMP_SHT1_EWSW[50]), .B0(n2881), .B1(
DMP_SHT2_EWSW[50]), .Y(n1391) );
AO22XLTS U3702 ( .A0(n2867), .A1(DMP_EXP_EWSW[51]), .B0(n2879), .B1(
DMP_SHT1_EWSW[51]), .Y(n1389) );
AO22XLTS U3703 ( .A0(n2863), .A1(DMP_SHT1_EWSW[51]), .B0(n2881), .B1(
DMP_SHT2_EWSW[51]), .Y(n1388) );
AO22XLTS U3704 ( .A0(n2867), .A1(DMP_EXP_EWSW[52]), .B0(n2879), .B1(
DMP_SHT1_EWSW[52]), .Y(n1386) );
AO22XLTS U3705 ( .A0(n2863), .A1(DMP_SHT1_EWSW[52]), .B0(n2881), .B1(
DMP_SHT2_EWSW[52]), .Y(n1385) );
CLKBUFX2TS U3706 ( .A(n2852), .Y(n3298) );
AO22XLTS U3707 ( .A0(n3261), .A1(DMP_SHT2_EWSW[52]), .B0(n3295), .B1(
DMP_SFG[52]), .Y(n1384) );
AO22XLTS U3708 ( .A0(n3136), .A1(DMP_SFG[52]), .B0(n3088), .B1(
DMP_exp_NRM_EW[0]), .Y(n1383) );
AO22XLTS U3709 ( .A0(n2867), .A1(DMP_EXP_EWSW[53]), .B0(n2879), .B1(
DMP_SHT1_EWSW[53]), .Y(n1381) );
AO22XLTS U3710 ( .A0(n2863), .A1(DMP_SHT1_EWSW[53]), .B0(n3462), .B1(
DMP_SHT2_EWSW[53]), .Y(n1380) );
AO22XLTS U3711 ( .A0(n3261), .A1(DMP_SHT2_EWSW[53]), .B0(n3295), .B1(
DMP_SFG[53]), .Y(n1379) );
AO22XLTS U3712 ( .A0(n3136), .A1(DMP_SFG[53]), .B0(n3527), .B1(
DMP_exp_NRM_EW[1]), .Y(n1378) );
AO22XLTS U3713 ( .A0(n3528), .A1(DMP_EXP_EWSW[54]), .B0(n2879), .B1(
DMP_SHT1_EWSW[54]), .Y(n1376) );
AO22XLTS U3714 ( .A0(n2863), .A1(DMP_SHT1_EWSW[54]), .B0(n3462), .B1(
DMP_SHT2_EWSW[54]), .Y(n1375) );
AO22XLTS U3715 ( .A0(n3261), .A1(DMP_SHT2_EWSW[54]), .B0(n3295), .B1(
DMP_SFG[54]), .Y(n1374) );
AO22XLTS U3716 ( .A0(n3024), .A1(DMP_SFG[54]), .B0(n3527), .B1(
DMP_exp_NRM_EW[2]), .Y(n1373) );
AO22XLTS U3717 ( .A0(n3528), .A1(DMP_EXP_EWSW[55]), .B0(n2879), .B1(
DMP_SHT1_EWSW[55]), .Y(n1371) );
AO22XLTS U3718 ( .A0(n2882), .A1(DMP_SHT1_EWSW[55]), .B0(n2881), .B1(
DMP_SHT2_EWSW[55]), .Y(n1370) );
AO22XLTS U3719 ( .A0(n3261), .A1(DMP_SHT2_EWSW[55]), .B0(n3130), .B1(
DMP_SFG[55]), .Y(n1369) );
AO22XLTS U3720 ( .A0(n3528), .A1(DMP_EXP_EWSW[56]), .B0(n2879), .B1(
DMP_SHT1_EWSW[56]), .Y(n1366) );
AO22XLTS U3721 ( .A0(n2882), .A1(DMP_SHT1_EWSW[56]), .B0(n2881), .B1(
DMP_SHT2_EWSW[56]), .Y(n1365) );
AO22XLTS U3722 ( .A0(n3261), .A1(DMP_SHT2_EWSW[56]), .B0(n2864), .B1(
DMP_SFG[56]), .Y(n1364) );
AO22XLTS U3723 ( .A0(n3528), .A1(DMP_EXP_EWSW[57]), .B0(n2879), .B1(
DMP_SHT1_EWSW[57]), .Y(n1361) );
AO22XLTS U3724 ( .A0(n2882), .A1(DMP_SHT1_EWSW[57]), .B0(n2881), .B1(
DMP_SHT2_EWSW[57]), .Y(n1360) );
AO22XLTS U3725 ( .A0(n3261), .A1(DMP_SHT2_EWSW[57]), .B0(n3130), .B1(
DMP_SFG[57]), .Y(n1359) );
AO22XLTS U3726 ( .A0(n3528), .A1(DMP_EXP_EWSW[58]), .B0(n2865), .B1(
DMP_SHT1_EWSW[58]), .Y(n1356) );
AO22XLTS U3727 ( .A0(n2882), .A1(DMP_SHT1_EWSW[58]), .B0(n2881), .B1(
DMP_SHT2_EWSW[58]), .Y(n1355) );
AO22XLTS U3728 ( .A0(n3261), .A1(DMP_SHT2_EWSW[58]), .B0(n2864), .B1(
DMP_SFG[58]), .Y(n1354) );
AO22XLTS U3729 ( .A0(n3528), .A1(DMP_EXP_EWSW[59]), .B0(n2865), .B1(
DMP_SHT1_EWSW[59]), .Y(n1351) );
AO22XLTS U3730 ( .A0(n2882), .A1(DMP_SHT1_EWSW[59]), .B0(n2881), .B1(
DMP_SHT2_EWSW[59]), .Y(n1350) );
AO22XLTS U3731 ( .A0(n3261), .A1(DMP_SHT2_EWSW[59]), .B0(n3130), .B1(
DMP_SFG[59]), .Y(n1349) );
AO22XLTS U3732 ( .A0(n3528), .A1(DMP_EXP_EWSW[60]), .B0(n2865), .B1(
DMP_SHT1_EWSW[60]), .Y(n1346) );
AO22XLTS U3733 ( .A0(n2882), .A1(DMP_SHT1_EWSW[60]), .B0(n2881), .B1(
DMP_SHT2_EWSW[60]), .Y(n1345) );
AO22XLTS U3734 ( .A0(n3261), .A1(DMP_SHT2_EWSW[60]), .B0(n3130), .B1(
DMP_SFG[60]), .Y(n1344) );
AO22XLTS U3735 ( .A0(n3528), .A1(DMP_EXP_EWSW[61]), .B0(n2865), .B1(
DMP_SHT1_EWSW[61]), .Y(n1341) );
AO22XLTS U3736 ( .A0(n2882), .A1(DMP_SHT1_EWSW[61]), .B0(n2881), .B1(
DMP_SHT2_EWSW[61]), .Y(n1340) );
AO22XLTS U3737 ( .A0(n3261), .A1(DMP_SHT2_EWSW[61]), .B0(n3130), .B1(
DMP_SFG[61]), .Y(n1339) );
AO22XLTS U3738 ( .A0(n3090), .A1(DMP_SFG[61]), .B0(n2921), .B1(
DMP_exp_NRM_EW[9]), .Y(n1338) );
AO22XLTS U3739 ( .A0(n3528), .A1(DMP_EXP_EWSW[62]), .B0(n2865), .B1(
DMP_SHT1_EWSW[62]), .Y(n1336) );
AO22XLTS U3740 ( .A0(n2882), .A1(DMP_SHT1_EWSW[62]), .B0(n2881), .B1(
DMP_SHT2_EWSW[62]), .Y(n1335) );
AO22XLTS U3741 ( .A0(n3261), .A1(DMP_SHT2_EWSW[62]), .B0(n3130), .B1(
DMP_SFG[62]), .Y(n1334) );
AO22XLTS U3742 ( .A0(n3528), .A1(DmP_EXP_EWSW[0]), .B0(n2865), .B1(n1927),
.Y(n1330) );
AO22XLTS U3743 ( .A0(n3528), .A1(DmP_EXP_EWSW[1]), .B0(n2865), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1328) );
AO22XLTS U3744 ( .A0(n3528), .A1(DmP_EXP_EWSW[2]), .B0(n2865), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1326) );
AO22XLTS U3745 ( .A0(n3528), .A1(DmP_EXP_EWSW[16]), .B0(n2865), .B1(
DmP_mant_SHT1_SW[16]), .Y(n1298) );
BUFX3TS U3746 ( .A(n3463), .Y(n2870) );
BUFX4TS U3747 ( .A(n2870), .Y(n2869) );
AO22XLTS U3748 ( .A0(n3528), .A1(DmP_EXP_EWSW[20]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[20]), .Y(n1290) );
AO22XLTS U3749 ( .A0(n3528), .A1(DmP_EXP_EWSW[24]), .B0(n2869), .B1(n1921),
.Y(n1282) );
INVX2TS U3750 ( .A(n3463), .Y(n2878) );
OAI222X1TS U3751 ( .A0(n2874), .A1(n3358), .B0(n3353), .B1(n2873), .C0(n3312), .C1(n2871), .Y(n1225) );
OAI222X1TS U3752 ( .A0(n2874), .A1(n3465), .B0(n3360), .B1(n2873), .C0(n3309), .C1(n2872), .Y(n1224) );
OAI222X1TS U3753 ( .A0(n2874), .A1(n3314), .B0(n3357), .B1(n2873), .C0(n3310), .C1(n2872), .Y(n1223) );
NAND2X1TS U3754 ( .A(n3468), .B(n2884), .Y(n2875) );
OAI2BB1X1TS U3755 ( .A0N(underflow_flag), .A1N(n3225), .B0(n2875), .Y(n1221)
);
OA21XLTS U3756 ( .A0(n3468), .A1(overflow_flag), .B0(n2876), .Y(n1220) );
AO22XLTS U3757 ( .A0(n2878), .A1(ZERO_FLAG_EXP), .B0(n3463), .B1(
ZERO_FLAG_SHT1), .Y(n1219) );
AO22XLTS U3758 ( .A0(n2882), .A1(ZERO_FLAG_SHT1), .B0(n2881), .B1(
ZERO_FLAG_SHT2), .Y(n1218) );
AO22XLTS U3759 ( .A0(n3261), .A1(ZERO_FLAG_SHT2), .B0(n3130), .B1(
ZERO_FLAG_SFG), .Y(n1217) );
AO22XLTS U3760 ( .A0(n3468), .A1(ZERO_FLAG_SHT1SHT2), .B0(n3225), .B1(
zero_flag), .Y(n1214) );
AO22XLTS U3761 ( .A0(n2878), .A1(OP_FLAG_EXP), .B0(n2877), .B1(OP_FLAG_SHT1),
.Y(n1213) );
AO22XLTS U3762 ( .A0(n2882), .A1(OP_FLAG_SHT1), .B0(n2881), .B1(OP_FLAG_SHT2), .Y(n1212) );
AO22XLTS U3763 ( .A0(n2880), .A1(SIGN_FLAG_EXP), .B0(n2879), .B1(
SIGN_FLAG_SHT1), .Y(n1210) );
AO22XLTS U3764 ( .A0(n2882), .A1(SIGN_FLAG_SHT1), .B0(n2881), .B1(
SIGN_FLAG_SHT2), .Y(n1209) );
AO22XLTS U3765 ( .A0(n3261), .A1(SIGN_FLAG_SHT2), .B0(n3130), .B1(
SIGN_FLAG_SFG), .Y(n1208) );
OAI211XLTS U3766 ( .A0(n2884), .A1(SIGN_FLAG_SHT1SHT2), .B0(n3468), .C0(
n2883), .Y(n2885) );
OAI2BB1X1TS U3767 ( .A0N(final_result_ieee[63]), .A1N(n3225), .B0(n2885),
.Y(n1205) );
AO22XLTS U3768 ( .A0(n3527), .A1(Raw_mant_NRM_SWR[14]), .B0(n3090), .B1(
n2888), .Y(n1204) );
AO22XLTS U3769 ( .A0(n3134), .A1(Raw_mant_NRM_SWR[24]), .B0(n3136), .B1(
n2912), .Y(n1194) );
AO22XLTS U3770 ( .A0(n3527), .A1(Raw_mant_NRM_SWR[34]), .B0(n3136), .B1(
n2937), .Y(n1184) );
AOI2BB2XLTS U3771 ( .B0(n1905), .B1(n1999), .A0N(n2986), .A1N(n1905), .Y(
n2975) );
AOI2BB2XLTS U3772 ( .B0(n1904), .B1(n3076), .A0N(n2986), .A1N(n1904), .Y(
n2978) );
AOI2BB2XLTS U3773 ( .B0(n1903), .B1(n1999), .A0N(n2986), .A1N(n1903), .Y(
n2981) );
AOI2BB2XLTS U3774 ( .B0(n1902), .B1(n3076), .A0N(n2986), .A1N(n1902), .Y(
n2983) );
XNOR2X1TS U3775 ( .A(n2983), .B(n2982), .Y(n2984) );
AOI22X1TS U3776 ( .A0(n3285), .A1(n2985), .B0(n3293), .B1(n1980), .Y(n1163)
);
AOI2BB2X1TS U3777 ( .B0(DmP_mant_SFG_SWR[10]), .B1(n2986), .A0N(n2986),
.A1N(DmP_mant_SFG_SWR[10]), .Y(n3109) );
CLKAND2X2TS U3778 ( .A(n3109), .B(DMP_SFG[8]), .Y(n2987) );
INVX2TS U3779 ( .A(n3131), .Y(n2988) );
AOI222X1TS U3780 ( .A0(n3133), .A1(n2988), .B0(n3133), .B1(DMP_SFG[10]),
.C0(n2988), .C1(DMP_SFG[10]), .Y(n2989) );
XOR2XLTS U3781 ( .A(n1896), .B(n2989), .Y(n2990) );
AOI22X1TS U3782 ( .A0(n3090), .A1(n2991), .B0(n3315), .B1(n3134), .Y(n1162)
);
AOI22X1TS U3783 ( .A0(n1943), .A1(n3054), .B0(Data_array_SWR[23]), .B1(n3188), .Y(n2993) );
AOI22X1TS U3784 ( .A0(n1936), .A1(n2159), .B0(n1952), .B1(n3189), .Y(n2992)
);
NAND2X1TS U3785 ( .A(n2993), .B(n2992), .Y(n3231) );
AOI22X1TS U3786 ( .A0(Data_array_SWR[14]), .A1(n3080), .B0(
Data_array_SWR[17]), .B1(n2142), .Y(n2995) );
AOI22X1TS U3787 ( .A0(Data_array_SWR[11]), .A1(n2159), .B0(Data_array_SWR[9]), .B1(n3189), .Y(n2994) );
AOI21X1TS U3788 ( .A0(n2995), .A1(n2994), .B0(n2127), .Y(n3000) );
NAND2X1TS U3789 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[5]),
.Y(n3018) );
BUFX3TS U3790 ( .A(n2996), .Y(n3247) );
AOI22X1TS U3791 ( .A0(n1944), .A1(n3228), .B0(Data_array_SWR[1]), .B1(n3247),
.Y(n2998) );
AOI22X1TS U3792 ( .A0(n1940), .A1(n3198), .B0(Data_array_SWR[5]), .B1(n3227),
.Y(n2997) );
OAI211XLTS U3793 ( .A0(n3243), .A1(n3018), .B0(n2998), .C0(n2997), .Y(n2999)
);
AOI211X1TS U3794 ( .A0(n2168), .A1(n3231), .B0(n3000), .C0(n2999), .Y(n3251)
);
NAND2X1TS U3795 ( .A(left_right_SHT2), .B(n3247), .Y(n3033) );
OAI22X1TS U3796 ( .A0(n3239), .A1(n3251), .B0(n3428), .B1(n3033), .Y(n3001)
);
AOI2BB2XLTS U3797 ( .B0(DmP_mant_SFG_SWR[1]), .B1(n3467), .A0N(n3037), .A1N(
DmP_mant_SFG_SWR[1]), .Y(n3002) );
AOI2BB2XLTS U3798 ( .B0(n3090), .B1(n3002), .A0N(Raw_mant_NRM_SWR[1]), .A1N(
n1825), .Y(n1159) );
AOI22X1TS U3799 ( .A0(n1956), .A1(n3054), .B0(Data_array_SWR[13]), .B1(n3188), .Y(n3004) );
AOI22X1TS U3800 ( .A0(Data_array_SWR[8]), .A1(n3115), .B0(n1958), .B1(n3125),
.Y(n3003) );
AOI21X1TS U3801 ( .A0(n3004), .A1(n3003), .B0(n2127), .Y(n3008) );
AOI22X1TS U3802 ( .A0(n1945), .A1(n3180), .B0(Data_array_SWR[0]), .B1(n3247),
.Y(n3006) );
AOI22X1TS U3803 ( .A0(n1939), .A1(n3198), .B0(Data_array_SWR[4]), .B1(n3122),
.Y(n3005) );
OAI211XLTS U3804 ( .A0(n3173), .A1(n3018), .B0(n3006), .C0(n3005), .Y(n3007)
);
AOI211X1TS U3805 ( .A0(n2168), .A1(n3009), .B0(n3008), .C0(n3007), .Y(n3304)
);
OAI22X1TS U3806 ( .A0(n3239), .A1(n3304), .B0(n3429), .B1(n3033), .Y(n3010)
);
AOI2BB2XLTS U3807 ( .B0(DmP_mant_SFG_SWR[0]), .B1(n3467), .A0N(n3467), .A1N(
DmP_mant_SFG_SWR[0]), .Y(n3011) );
AOI22X1TS U3808 ( .A0(n1825), .A1(n3011), .B0(n3329), .B1(n3134), .Y(n1156)
);
AOI22X1TS U3809 ( .A0(Data_array_SWR[27]), .A1(n3054), .B0(
Data_array_SWR[24]), .B1(n3188), .Y(n3013) );
AOI22X1TS U3810 ( .A0(n1953), .A1(n3115), .B0(n1935), .B1(n3125), .Y(n3012)
);
NAND2X1TS U3811 ( .A(n3013), .B(n3012), .Y(n3182) );
AOI22X1TS U3812 ( .A0(n1957), .A1(n3054), .B0(Data_array_SWR[15]), .B1(n3188), .Y(n3015) );
AOI22X1TS U3813 ( .A0(n1959), .A1(n2159), .B0(n1951), .B1(n3189), .Y(n3014)
);
AOI21X1TS U3814 ( .A0(n3015), .A1(n3014), .B0(n2127), .Y(n3020) );
AOI22X1TS U3815 ( .A0(n1947), .A1(n3180), .B0(Data_array_SWR[2]), .B1(n3247),
.Y(n3017) );
AOI22X1TS U3816 ( .A0(n1941), .A1(n3198), .B0(Data_array_SWR[6]), .B1(n3122),
.Y(n3016) );
OAI211XLTS U3817 ( .A0(n3213), .A1(n3018), .B0(n3017), .C0(n3016), .Y(n3019)
);
AOI211X1TS U3818 ( .A0(n2168), .A1(n3182), .B0(n3020), .C0(n3019), .Y(n3250)
);
INVX2TS U3819 ( .A(n1948), .Y(n3249) );
OAI22X1TS U3820 ( .A0(n3239), .A1(n3250), .B0(n3249), .B1(n3033), .Y(n3246)
);
AOI2BB2X1TS U3821 ( .B0(DmP_mant_SFG_SWR[2]), .B1(n3526), .A0N(n3075), .A1N(
DmP_mant_SFG_SWR[2]), .Y(n3021) );
NAND2X1TS U3822 ( .A(n3021), .B(DMP_SFG[0]), .Y(n3034) );
AOI22X1TS U3823 ( .A0(n3024), .A1(n3022), .B0(n3328), .B1(n3134), .Y(n1153)
);
XNOR2X1TS U3824 ( .A(DMP_SFG[1]), .B(n3034), .Y(n3023) );
XNOR2X1TS U3825 ( .A(n3023), .B(n3035), .Y(n3025) );
AOI2BB2XLTS U3826 ( .B0(n1825), .B1(n3025), .A0N(Raw_mant_NRM_SWR[3]), .A1N(
n3136), .Y(n1152) );
AOI22X1TS U3827 ( .A0(Data_array_SWR[28]), .A1(n3054), .B0(
Data_array_SWR[25]), .B1(n3188), .Y(n3026) );
OAI2BB1X1TS U3828 ( .A0N(Data_array_SWR[21]), .A1N(n3125), .B0(n3026), .Y(
n3027) );
AOI21X1TS U3829 ( .A0(n1949), .A1(n3115), .B0(n3027), .Y(n3210) );
AO22XLTS U3830 ( .A0(Data_array_SWR[7]), .A1(n3122), .B0(Data_array_SWR[3]),
.B1(n3247), .Y(n3032) );
AOI22X1TS U3831 ( .A0(n1955), .A1(n3054), .B0(Data_array_SWR[16]), .B1(n3188), .Y(n3030) );
AOI22X1TS U3832 ( .A0(n1946), .A1(n3180), .B0(n1942), .B1(n3226), .Y(n3029)
);
AOI22X1TS U3833 ( .A0(Data_array_SWR[12]), .A1(n2159), .B0(
Data_array_SWR[10]), .B1(n3189), .Y(n3028) );
AOI32X1TS U3834 ( .A0(n3030), .A1(n3029), .A2(n3028), .B0(n2127), .B1(n3029),
.Y(n3031) );
AOI211X1TS U3835 ( .A0(shift_value_SHT2_EWR[5]), .A1(n1901), .B0(n3032),
.C0(n3031), .Y(n3248) );
OAI22X1TS U3836 ( .A0(left_right_SHT2), .A1(n3248), .B0(n3427), .B1(n3033),
.Y(n3245) );
AO22XLTS U3837 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[3]), .B0(n2854), .B1(n3245), .Y(n1150) );
AOI2BB2X1TS U3838 ( .B0(DmP_mant_SFG_SWR[4]), .B1(n3467), .A0N(n3467), .A1N(
DmP_mant_SFG_SWR[4]), .Y(n3065) );
INVX2TS U3839 ( .A(n3034), .Y(n3036) );
AOI2BB2X2TS U3840 ( .B0(DmP_mant_SFG_SWR[5]), .B1(n3467), .A0N(n3037), .A1N(
DmP_mant_SFG_SWR[5]), .Y(n3049) );
AOI2BB2XLTS U3841 ( .B0(DMP_SFG[3]), .B1(n3049), .A0N(n3049), .A1N(
DMP_SFG[3]), .Y(n3038) );
XNOR2X1TS U3842 ( .A(n3039), .B(n3038), .Y(n3040) );
AOI2BB2XLTS U3843 ( .B0(n3024), .B1(n3040), .A0N(Raw_mant_NRM_SWR[5]), .A1N(
n3136), .Y(n1149) );
AOI22X1TS U3844 ( .A0(Data_array_SWR[30]), .A1(n3054), .B0(n1943), .B1(n3188), .Y(n3041) );
OAI21XLTS U3845 ( .A0(n3455), .A1(n3056), .B0(n3041), .Y(n3042) );
AOI21X1TS U3846 ( .A0(Data_array_SWR[23]), .A1(n3125), .B0(n3042), .Y(n3220)
);
AO22XLTS U3847 ( .A0(n1940), .A1(n3122), .B0(Data_array_SWR[5]), .B1(n3247),
.Y(n3047) );
AOI22X1TS U3848 ( .A0(n1952), .A1(n3054), .B0(Data_array_SWR[17]), .B1(n3188), .Y(n3045) );
AOI22X1TS U3849 ( .A0(Data_array_SWR[9]), .A1(n3180), .B0(n1944), .B1(n3226),
.Y(n3044) );
AOI22X1TS U3850 ( .A0(Data_array_SWR[11]), .A1(n3115), .B0(
Data_array_SWR[14]), .B1(n3125), .Y(n3043) );
AOI32X1TS U3851 ( .A0(n3045), .A1(n3044), .A2(n3043), .B0(n2127), .B1(n3044),
.Y(n3046) );
OAI22X1TS U3852 ( .A0(n3243), .A1(n3197), .B0(n3239), .B1(n3244), .Y(n3215)
);
AO22XLTS U3853 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[5]), .B0(n3297), .B1(n3215), .Y(n1147) );
NAND2BXLTS U3854 ( .AN(n3065), .B(DMP_SFG[2]), .Y(n3048) );
AOI222X1TS U3855 ( .A0(n3461), .A1(n3049), .B0(n3461), .B1(n3048), .C0(n3049), .C1(n3048), .Y(n3086) );
XNOR2X1TS U3856 ( .A(DMP_SFG[5]), .B(n3050), .Y(n3051) );
XOR2X1TS U3857 ( .A(n3052), .B(n3051), .Y(n3053) );
AOI22X1TS U3858 ( .A0(n3136), .A1(n3053), .B0(n3330), .B1(n3134), .Y(n1146)
);
AOI22X1TS U3859 ( .A0(Data_array_SWR[29]), .A1(n3054), .B0(
Data_array_SWR[26]), .B1(n3188), .Y(n3055) );
AOI21X1TS U3860 ( .A0(Data_array_SWR[22]), .A1(n3125), .B0(n3057), .Y(n3178)
);
AO22XLTS U3861 ( .A0(n1939), .A1(n3122), .B0(Data_array_SWR[4]), .B1(n3247),
.Y(n3063) );
AOI22X1TS U3862 ( .A0(n1954), .A1(n2142), .B0(n1956), .B1(n3080), .Y(n3061)
);
AOI22X1TS U3863 ( .A0(Data_array_SWR[8]), .A1(n3180), .B0(n1945), .B1(n3226),
.Y(n3060) );
AOI22X1TS U3864 ( .A0(Data_array_SWR[13]), .A1(n2159), .B0(n1958), .B1(n3189), .Y(n3059) );
AOI32X1TS U3865 ( .A0(n3061), .A1(n3060), .A2(n3059), .B0(n2127), .B1(n3060),
.Y(n3062) );
OAI22X1TS U3866 ( .A0(left_right_SHT2), .A1(n3214), .B0(n3213), .B1(n3197),
.Y(n3212) );
AO22XLTS U3867 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[4]), .B0(n2854), .B1(n3212), .Y(n1145) );
CMPR32X2TS U3868 ( .A(n3466), .B(n3065), .C(n3064), .CO(n3039), .S(n3066) );
AOI22X1TS U3869 ( .A0(n3136), .A1(n3066), .B0(n3323), .B1(n3134), .Y(n1144)
);
AOI22X1TS U3870 ( .A0(Data_array_SWR[28]), .A1(n3080), .B0(
Data_array_SWR[32]), .B1(n2142), .Y(n3068) );
AOI22X1TS U3871 ( .A0(Data_array_SWR[25]), .A1(n2159), .B0(
Data_array_SWR[21]), .B1(n3189), .Y(n3067) );
NAND2X2TS U3872 ( .A(n3068), .B(n3067), .Y(n3203) );
AOI22X1TS U3873 ( .A0(Data_array_SWR[12]), .A1(n3115), .B0(n1949), .B1(n2142), .Y(n3069) );
OAI2BB1X1TS U3874 ( .A0N(n1955), .A1N(n3080), .B0(n3069), .Y(n3070) );
AOI22X1TS U3875 ( .A0(n1946), .A1(n3198), .B0(n1942), .B1(n3122), .Y(n3072)
);
AOI22X1TS U3876 ( .A0(Data_array_SWR[10]), .A1(n3180), .B0(Data_array_SWR[7]), .B1(n3247), .Y(n3071) );
OAI211XLTS U3877 ( .A0(n1858), .A1(n2127), .B0(n3072), .C0(n3071), .Y(n3073)
);
AOI21X1TS U3878 ( .A0(n2168), .A1(n3203), .B0(n3073), .Y(n3206) );
OAI22X1TS U3879 ( .A0(left_right_SHT2), .A1(n3206), .B0(n3205), .B1(n3197),
.Y(n3187) );
AO22XLTS U3880 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[7]), .B0(n3292), .B1(n3187), .Y(n1143) );
CMPR32X2TS U3881 ( .A(n1931), .B(n3074), .C(n3096), .CO(n3078), .S(n2094) );
XNOR2X1TS U3882 ( .A(DMP_SFG[7]), .B(n3098), .Y(n3077) );
XOR2X1TS U3883 ( .A(n3078), .B(n3077), .Y(n3079) );
AOI22X1TS U3884 ( .A0(n3136), .A1(n3079), .B0(n3317), .B1(n3134), .Y(n1142)
);
AO22XLTS U3885 ( .A0(n1941), .A1(n3122), .B0(Data_array_SWR[6]), .B1(n3247),
.Y(n3085) );
AOI22X1TS U3886 ( .A0(n1957), .A1(n3080), .B0(n1953), .B1(n2142), .Y(n3083)
);
AOI22X1TS U3887 ( .A0(n1947), .A1(n3198), .B0(n1951), .B1(n3228), .Y(n3082)
);
AOI22X1TS U3888 ( .A0(Data_array_SWR[15]), .A1(n2159), .B0(n1959), .B1(n3189), .Y(n3081) );
AOI32X1TS U3889 ( .A0(n3083), .A1(n3082), .A2(n3081), .B0(n2127), .B1(n3082),
.Y(n3084) );
AOI211X1TS U3890 ( .A0(shift_value_SHT2_EWR[5]), .A1(n1900), .B0(n3085),
.C0(n3084), .Y(n3174) );
OAI22X1TS U3891 ( .A0(n3239), .A1(n3174), .B0(n3173), .B1(n3197), .Y(n3171)
);
AO22XLTS U3892 ( .A0(n3307), .A1(n1915), .B0(n3292), .B1(n3171), .Y(n1141)
);
CMPR32X2TS U3893 ( .A(n1932), .B(n3087), .C(n3086), .CO(n3052), .S(n3089) );
AOI22X1TS U3894 ( .A0(Data_array_SWR[14]), .A1(n3115), .B0(n1952), .B1(n3188), .Y(n3091) );
AOI22X1TS U3895 ( .A0(Data_array_SWR[9]), .A1(n3198), .B0(n1944), .B1(n3122),
.Y(n3094) );
AOI22X1TS U3896 ( .A0(Data_array_SWR[11]), .A1(n3180), .B0(n1940), .B1(n3247), .Y(n3093) );
AOI21X1TS U3897 ( .A0(n2168), .A1(n3163), .B0(n3095), .Y(n3170) );
OAI22X1TS U3898 ( .A0(n3239), .A1(n3170), .B0(n3169), .B1(n3197), .Y(n3160)
);
AO22XLTS U3899 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[9]), .B0(n2854), .B1(n3160), .Y(n1139) );
OAI211XLTS U3900 ( .A0(DMP_SFG[7]), .A1(n3098), .B0(n1931), .C0(n3096), .Y(
n3097) );
OAI2BB1X1TS U3901 ( .A0N(n3098), .A1N(DMP_SFG[7]), .B0(n3097), .Y(n3108) );
XNOR2X1TS U3902 ( .A(DMP_SFG[9]), .B(n3099), .Y(n3100) );
XOR2X1TS U3903 ( .A(n3101), .B(n3100), .Y(n3102) );
AOI22X1TS U3904 ( .A0(n3136), .A1(n3102), .B0(n3308), .B1(n3134), .Y(n1138)
);
AOI22X1TS U3905 ( .A0(n1953), .A1(n3080), .B0(Data_array_SWR[15]), .B1(n3115), .Y(n3103) );
AOI22X1TS U3906 ( .A0(n1947), .A1(n3227), .B0(n1951), .B1(n3226), .Y(n3106)
);
AOI22X1TS U3907 ( .A0(n1941), .A1(n3229), .B0(n1959), .B1(n3228), .Y(n3105)
);
OAI211XLTS U3908 ( .A0(n1897), .A1(n2127), .B0(n3106), .C0(n3105), .Y(n3107)
);
AOI21X1TS U3909 ( .A0(n2168), .A1(n3140), .B0(n3107), .Y(n3114) );
OAI22X1TS U3910 ( .A0(n3239), .A1(n3114), .B0(n3137), .B1(n3197), .Y(n3113)
);
AO22XLTS U3911 ( .A0(n3527), .A1(Raw_mant_NRM_SWR[10]), .B0(n3136), .B1(
n3110), .Y(n1135) );
OAI22X1TS U3912 ( .A0(n3114), .A1(n3303), .B0(n3137), .B1(n3242), .Y(n3287)
);
AOI22X1TS U3913 ( .A0(n1954), .A1(n3188), .B0(Data_array_SWR[13]), .B1(n3115), .Y(n3116) );
AOI22X1TS U3914 ( .A0(Data_array_SWR[8]), .A1(n3198), .B0(n1945), .B1(n3122),
.Y(n3120) );
AOI22X1TS U3915 ( .A0(n1958), .A1(n3180), .B0(n1939), .B1(n3247), .Y(n3119)
);
OAI211XLTS U3916 ( .A0(n3153), .A1(n2127), .B0(n3120), .C0(n3119), .Y(n3121)
);
AOI21X1TS U3917 ( .A0(n2168), .A1(n3148), .B0(n3121), .Y(n3159) );
OAI22X1TS U3918 ( .A0(n3239), .A1(n3159), .B0(n3158), .B1(n3197), .Y(n3157)
);
AO22XLTS U3919 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[8]), .B0(n2858), .B1(n3157), .Y(n1132) );
AOI22X1TS U3920 ( .A0(Data_array_SWR[10]), .A1(n3198), .B0(n1946), .B1(n3122), .Y(n3124) );
AOI22X1TS U3921 ( .A0(Data_array_SWR[12]), .A1(n3180), .B0(n1942), .B1(n3229), .Y(n3123) );
OAI211X1TS U3922 ( .A0(n3156), .A1(n3201), .B0(n3124), .C0(n3123), .Y(n3128)
);
AO22XLTS U3923 ( .A0(Data_array_SWR[21]), .A1(n2142), .B0(n1949), .B1(n3080),
.Y(n3127) );
AO22XLTS U3924 ( .A0(n1955), .A1(n3125), .B0(Data_array_SWR[16]), .B1(n3189),
.Y(n3126) );
OAI22X1TS U3925 ( .A0(n3239), .A1(n3155), .B0(n3156), .B1(n3197), .Y(n3154)
);
XNOR2X1TS U3926 ( .A(DMP_SFG[10]), .B(n3131), .Y(n3132) );
XNOR2X1TS U3927 ( .A(n3133), .B(n3132), .Y(n3135) );
AOI22X1TS U3928 ( .A0(n1825), .A1(n3135), .B0(n3327), .B1(n3134), .Y(n1129)
);
INVX2TS U3929 ( .A(n3137), .Y(n3142) );
AOI22X1TS U3930 ( .A0(n3221), .A1(n3141), .B0(n3222), .B1(n3142), .Y(n3139)
);
NAND2X1TS U3931 ( .A(n2156), .B(n3140), .Y(n3138) );
AOI22X1TS U3932 ( .A0(n3223), .A1(n3141), .B0(n3222), .B1(n3140), .Y(n3144)
);
NAND2X1TS U3933 ( .A(n2156), .B(n3142), .Y(n3143) );
AOI22X1TS U3934 ( .A0(n3285), .A1(n3145), .B0(n1986), .B1(n3293), .Y(n1122)
);
INVX2TS U3935 ( .A(n3158), .Y(n3150) );
AOI22X1TS U3936 ( .A0(n3221), .A1(n3149), .B0(n3222), .B1(n3150), .Y(n3147)
);
NAND2X1TS U3937 ( .A(n2156), .B(n3148), .Y(n3146) );
AO22XLTS U3938 ( .A0(n3172), .A1(n3265), .B0(final_result_ieee[22]), .B1(
n3225), .Y(n1118) );
AOI22X1TS U3939 ( .A0(n3223), .A1(n3149), .B0(n3222), .B1(n3148), .Y(n3152)
);
NAND2X1TS U3940 ( .A(n2156), .B(n3150), .Y(n3151) );
OAI22X1TS U3941 ( .A0(n3156), .A1(n3242), .B0(n3155), .B1(n3303), .Y(n3286)
);
AO22XLTS U3942 ( .A0(n3172), .A1(n3286), .B0(final_result_ieee[41]), .B1(
n3240), .Y(n1113) );
OAI22X1TS U3943 ( .A0(n3159), .A1(n3361), .B0(n3158), .B1(n3242), .Y(n3289)
);
INVX2TS U3944 ( .A(n3169), .Y(n3165) );
AOI22X1TS U3945 ( .A0(n3221), .A1(n3164), .B0(n3222), .B1(n3165), .Y(n3162)
);
NAND2X1TS U3946 ( .A(n2156), .B(n3163), .Y(n3161) );
OAI211X1TS U3947 ( .A0(n3168), .A1(n3242), .B0(n3162), .C0(n3161), .Y(n3266)
);
AOI22X1TS U3948 ( .A0(n3223), .A1(n3164), .B0(n3222), .B1(n3163), .Y(n3167)
);
NAND2X1TS U3949 ( .A(n2156), .B(n3165), .Y(n3166) );
OAI211X1TS U3950 ( .A0(n3168), .A1(n3197), .B0(n3167), .C0(n3166), .Y(n3270)
);
OAI22X1TS U3951 ( .A0(n3170), .A1(n3361), .B0(n3169), .B1(n3242), .Y(n3288)
);
OAI22X1TS U3952 ( .A0(n3174), .A1(n3303), .B0(n3173), .B1(n3242), .Y(n3291)
);
AOI22X1TS U3953 ( .A0(Data_array_SWR[13]), .A1(n3227), .B0(n1958), .B1(n3247), .Y(n3177) );
OAI2BB2XLTS U3954 ( .B0(n3249), .B1(n3216), .A0N(n1956), .A1N(n3226), .Y(
n3175) );
AOI21X1TS U3955 ( .A0(n1954), .A1(n3228), .B0(n3175), .Y(n3176) );
OAI211X1TS U3956 ( .A0(n3178), .A1(n2127), .B0(n3177), .C0(n3176), .Y(n3179)
);
INVX2TS U3957 ( .A(n3213), .Y(n3181) );
BUFX3TS U3958 ( .A(n2146), .Y(n3241) );
OAI2BB2XLTS U3959 ( .B0(n3260), .B1(n3241), .A0N(final_result_ieee[18]),
.A1N(n1996), .Y(n1102) );
OAI2BB2XLTS U3960 ( .B0(n3275), .B1(n3241), .A0N(final_result_ieee[32]),
.A1N(n1996), .Y(n1101) );
AOI22X1TS U3961 ( .A0(Data_array_SWR[15]), .A1(n3198), .B0(n1959), .B1(n3227), .Y(n3185) );
AOI22X1TS U3962 ( .A0(n1957), .A1(n3180), .B0(n1951), .B1(n3229), .Y(n3184)
);
AOI22X1TS U3963 ( .A0(n3232), .A1(n3182), .B0(n2168), .B1(n3181), .Y(n3183)
);
NAND3XLTS U3964 ( .A(n3185), .B(n3184), .C(n3183), .Y(n3186) );
AOI22X1TS U3965 ( .A0(n3236), .A1(n1899), .B0(n3303), .B1(n3186), .Y(n3258)
);
OAI2BB2XLTS U3966 ( .B0(n3258), .B1(n3241), .A0N(final_result_ieee[16]),
.A1N(n1996), .Y(n1100) );
AOI22X1TS U3967 ( .A0(n3239), .A1(n3186), .B0(n3237), .B1(n1899), .Y(n3277)
);
OAI2BB2XLTS U3968 ( .B0(n3277), .B1(n3241), .A0N(final_result_ieee[34]),
.A1N(n1996), .Y(n1099) );
AOI22X1TS U3969 ( .A0(Data_array_SWR[25]), .A1(n2142), .B0(
Data_array_SWR[21]), .B1(n3188), .Y(n3191) );
AOI22X1TS U3970 ( .A0(n1949), .A1(n2159), .B0(n1955), .B1(n3189), .Y(n3190)
);
NAND2X1TS U3971 ( .A(n3191), .B(n3190), .Y(n3202) );
INVX2TS U3972 ( .A(n3205), .Y(n3194) );
AOI22X1TS U3973 ( .A0(n3221), .A1(n3202), .B0(n3222), .B1(n3194), .Y(n3193)
);
NAND2X1TS U3974 ( .A(n2156), .B(n3203), .Y(n3192) );
AOI22X1TS U3975 ( .A0(n3223), .A1(n3202), .B0(n3222), .B1(n3203), .Y(n3196)
);
NAND2X1TS U3976 ( .A(n2156), .B(n3194), .Y(n3195) );
AOI22X1TS U3977 ( .A0(Data_array_SWR[12]), .A1(n3198), .B0(n1946), .B1(n3229), .Y(n3200) );
AOI22X1TS U3978 ( .A0(Data_array_SWR[10]), .A1(n3227), .B0(
Data_array_SWR[16]), .B1(n3228), .Y(n3199) );
OAI211X1TS U3979 ( .A0(n3205), .A1(n3201), .B0(n3200), .C0(n3199), .Y(n3204)
);
OAI2BB2XLTS U3980 ( .B0(n3255), .B1(n3241), .A0N(final_result_ieee[13]),
.A1N(n3225), .Y(n1095) );
OAI2BB2XLTS U3981 ( .B0(n3281), .B1(n3241), .A0N(final_result_ieee[37]),
.A1N(n1996), .Y(n1094) );
OAI22X1TS U3982 ( .A0(n3206), .A1(n3303), .B0(n3205), .B1(n3242), .Y(n3290)
);
AOI22X1TS U3983 ( .A0(Data_array_SWR[12]), .A1(n3227), .B0(
Data_array_SWR[10]), .B1(n3229), .Y(n3209) );
OAI2BB2XLTS U3984 ( .B0(n3427), .B1(n3216), .A0N(Data_array_SWR[16]), .A1N(
n3226), .Y(n3207) );
AOI21X1TS U3985 ( .A0(n1955), .A1(n3228), .B0(n3207), .Y(n3208) );
OAI211X1TS U3986 ( .A0(n3210), .A1(n2127), .B0(n3209), .C0(n3208), .Y(n3211)
);
AOI22X1TS U3987 ( .A0(n3236), .A1(n1901), .B0(n3303), .B1(n3211), .Y(n3259)
);
OAI2BB2XLTS U3988 ( .B0(n3259), .B1(n3241), .A0N(final_result_ieee[17]),
.A1N(n3240), .Y(n1092) );
AOI22X1TS U3989 ( .A0(n3239), .A1(n3211), .B0(n3237), .B1(n1901), .Y(n3276)
);
OAI2BB2XLTS U3990 ( .B0(n3276), .B1(n3241), .A0N(final_result_ieee[33]),
.A1N(n1996), .Y(n1091) );
OAI22X1TS U3991 ( .A0(n3214), .A1(n3303), .B0(n3213), .B1(n3242), .Y(n3296)
);
AOI22X1TS U3992 ( .A0(Data_array_SWR[11]), .A1(n3229), .B0(
Data_array_SWR[14]), .B1(n3227), .Y(n3219) );
OAI2BB2XLTS U3993 ( .B0(n3428), .B1(n3216), .A0N(Data_array_SWR[17]), .A1N(
n3226), .Y(n3217) );
AOI21X1TS U3994 ( .A0(n1952), .A1(n3228), .B0(n3217), .Y(n3218) );
OAI211X1TS U3995 ( .A0(n3220), .A1(n2127), .B0(n3219), .C0(n3218), .Y(n3224)
);
INVX2TS U3996 ( .A(n3243), .Y(n3230) );
OAI2BB2XLTS U3997 ( .B0(n3262), .B1(n3241), .A0N(final_result_ieee[19]),
.A1N(n3225), .Y(n1087) );
OAI2BB2XLTS U3998 ( .B0(n3274), .B1(n3241), .A0N(final_result_ieee[31]),
.A1N(n1996), .Y(n1086) );
AOI22X1TS U3999 ( .A0(Data_array_SWR[11]), .A1(n3227), .B0(
Data_array_SWR[14]), .B1(n3226), .Y(n3235) );
AOI22X1TS U4000 ( .A0(Data_array_SWR[9]), .A1(n3229), .B0(Data_array_SWR[17]), .B1(n3228), .Y(n3234) );
AOI22X1TS U4001 ( .A0(n3232), .A1(n3231), .B0(n2168), .B1(n3230), .Y(n3233)
);
NAND3XLTS U4002 ( .A(n3235), .B(n3234), .C(n3233), .Y(n3238) );
AOI22X1TS U4003 ( .A0(n3236), .A1(n1898), .B0(n3303), .B1(n3238), .Y(n3257)
);
OAI2BB2XLTS U4004 ( .B0(n3257), .B1(n3241), .A0N(final_result_ieee[15]),
.A1N(n1996), .Y(n1085) );
AOI22X1TS U4005 ( .A0(n3239), .A1(n3238), .B0(n3237), .B1(n1898), .Y(n3278)
);
OAI2BB2XLTS U4006 ( .B0(n3278), .B1(n3241), .A0N(final_result_ieee[35]),
.A1N(n3240), .Y(n1084) );
OAI22X1TS U4007 ( .A0(n3244), .A1(n3303), .B0(n3243), .B1(n3242), .Y(n3294)
);
NAND2X1TS U4008 ( .A(n3247), .B(n3303), .Y(n3302) );
OAI22X1TS U4009 ( .A0(n3248), .A1(n3361), .B0(n3427), .B1(n3302), .Y(n3299)
);
OAI22X1TS U4010 ( .A0(n3250), .A1(n3361), .B0(n3249), .B1(n3302), .Y(n3300)
);
OAI22X1TS U4011 ( .A0(n3251), .A1(n3361), .B0(n3428), .B1(n3302), .Y(n3301)
);
AOI22X1TS U4012 ( .A0(n3285), .A1(n3254), .B0(n1987), .B1(n2852), .Y(n1077)
);
AOI22X1TS U4013 ( .A0(n3285), .A1(n3255), .B0(n3293), .B1(n1988), .Y(n1076)
);
AOI22X1TS U4014 ( .A0(n3285), .A1(n3256), .B0(n3293), .B1(n1989), .Y(n1075)
);
AOI22X1TS U4015 ( .A0(n3285), .A1(n3257), .B0(n3293), .B1(n1990), .Y(n1074)
);
AOI22X1TS U4016 ( .A0(n3285), .A1(n3258), .B0(n3293), .B1(n1992), .Y(n1073)
);
AOI22X1TS U4017 ( .A0(n3285), .A1(n3259), .B0(n3293), .B1(n1993), .Y(n1072)
);
AOI22X1TS U4018 ( .A0(n3285), .A1(n3260), .B0(n2852), .B1(n1994), .Y(n1071)
);
AOI22X1TS U4019 ( .A0(n3285), .A1(n3262), .B0(n3279), .B1(n1971), .Y(n1070)
);
AOI22X1TS U4020 ( .A0(n3285), .A1(n3263), .B0(n1972), .B1(n2852), .Y(n1069)
);
AO22XLTS U4021 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[23]), .B0(n2858), .B1(
n3264), .Y(n1068) );
AO22XLTS U4022 ( .A0(n3293), .A1(DmP_mant_SFG_SWR[24]), .B0(n2854), .B1(
n3265), .Y(n1067) );
AO22XLTS U4023 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[25]), .B0(n3297), .B1(
n3266), .Y(n1066) );
AO22XLTS U4024 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[26]), .B0(n2854), .B1(
n3267), .Y(n1065) );
AO22XLTS U4025 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[27]), .B0(n3292), .B1(
n3268), .Y(n1064) );
AO22XLTS U4026 ( .A0(n3293), .A1(DmP_mant_SFG_SWR[28]), .B0(n2854), .B1(
n3269), .Y(n1063) );
AO22XLTS U4027 ( .A0(n3293), .A1(DmP_mant_SFG_SWR[29]), .B0(n3297), .B1(
n3270), .Y(n1062) );
AO22XLTS U4028 ( .A0(n3293), .A1(DmP_mant_SFG_SWR[30]), .B0(n2854), .B1(
n3271), .Y(n1061) );
AO22XLTS U4029 ( .A0(n3293), .A1(DmP_mant_SFG_SWR[31]), .B0(n2854), .B1(
n3272), .Y(n1060) );
AOI22X1TS U4030 ( .A0(n3285), .A1(n3273), .B0(n2852), .B1(n1973), .Y(n1059)
);
AOI22X1TS U4031 ( .A0(n3285), .A1(n3274), .B0(n3279), .B1(n1974), .Y(n1058)
);
AOI22X1TS U4032 ( .A0(n3285), .A1(n3275), .B0(n3279), .B1(n1975), .Y(n1057)
);
AOI22X1TS U4033 ( .A0(n3285), .A1(n3276), .B0(n2852), .B1(n1976), .Y(n1056)
);
AOI22X1TS U4034 ( .A0(n3285), .A1(n3277), .B0(n3279), .B1(n1977), .Y(n1055)
);
AOI22X1TS U4035 ( .A0(n3261), .A1(n3278), .B0(n1979), .B1(n3298), .Y(n1054)
);
AOI22X1TS U4036 ( .A0(n3285), .A1(n3280), .B0(n3279), .B1(n1981), .Y(n1053)
);
AOI22X1TS U4037 ( .A0(n3285), .A1(n3281), .B0(n2852), .B1(n1982), .Y(n1052)
);
AOI22X1TS U4038 ( .A0(n3261), .A1(n3282), .B0(n1983), .B1(n3298), .Y(n1051)
);
AOI22X1TS U4039 ( .A0(n3285), .A1(n3283), .B0(n1984), .B1(n2852), .Y(n1050)
);
AOI22X1TS U4040 ( .A0(n3285), .A1(n3284), .B0(n2852), .B1(n1985), .Y(n1049)
);
AO22XLTS U4041 ( .A0(n3293), .A1(n1912), .B0(n3297), .B1(n3286), .Y(n1048)
);
AO22XLTS U4042 ( .A0(n3293), .A1(n1911), .B0(n2858), .B1(n3287), .Y(n1047)
);
AO22XLTS U4043 ( .A0(n3293), .A1(DmP_mant_SFG_SWR[45]), .B0(n2858), .B1(
n3288), .Y(n1046) );
AO22XLTS U4044 ( .A0(n3293), .A1(n1910), .B0(n3306), .B1(n3289), .Y(n1045)
);
AO22XLTS U4045 ( .A0(n3293), .A1(n1909), .B0(n3292), .B1(n3290), .Y(n1044)
);
AO22XLTS U4046 ( .A0(n3293), .A1(n1908), .B0(n3297), .B1(n3291), .Y(n1043)
);
AO22XLTS U4047 ( .A0(n3295), .A1(n1907), .B0(n3306), .B1(n3294), .Y(n1042)
);
AO22XLTS U4048 ( .A0(n3298), .A1(n1906), .B0(n2858), .B1(n3296), .Y(n1041)
);
AO22XLTS U4049 ( .A0(n3307), .A1(n1905), .B0(n3306), .B1(n3299), .Y(n1040)
);
AO22XLTS U4050 ( .A0(n2852), .A1(n1904), .B0(n3306), .B1(n3300), .Y(n1039)
);
AO22XLTS U4051 ( .A0(n2852), .A1(n1903), .B0(n3306), .B1(n3301), .Y(n1038)
);
OAI22X1TS U4052 ( .A0(n3304), .A1(n3303), .B0(n3429), .B1(n3302), .Y(n3305)
);
AO22XLTS U4053 ( .A0(n3307), .A1(n1902), .B0(n3306), .B1(n3305), .Y(n1037)
);
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk30.tcl_ETAIIN16Q4_syn.sdf");
endmodule |
module sky130_fd_sc_ls__or4bb (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module sky130_fd_sc_ms__mux2i (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module decoder(
input i_clk,
input i_reset,
input i_ready,
input[31:0] i_data,
output[1:0] o_instr_size);
string mnemonic;
reg[31:0] opcode;
reg[1:0] instr_size;
assign o_instr_size = instr_size;
reg[`SIZE_DECODE_REG-1:0] decode_reg;
reg[`SIZE_DECODE_REG-1:0] decode_tmp_reg;
reg[`SIZE_DECODE_REG-1:0] decode_hold_reg;
reg[3:0] count_bytes_in_hold_reg;
reg[3:0] count_bytes_in_decode_reg;
reg[3:0] count_bytes_instr;
reg[2:0] count_bytes_in_prefix;
reg[2:0] data_size;
reg[2:0] direction;
reg[3:0] minRequiredBytes;
reg isImmediate;
reg hasStartAddress;
reg isRegImplicit;
reg[2:0] implicitRegVal;
reg[31:0] last_address;
reg process_modrm;
string non_modrm = "";
initial begin
decode_reg = `SIZE_DECODE_REG'b0;
decode_tmp_reg = `SIZE_DECODE_REG'b0;
decode_hold_reg = `SIZE_DECODE_REG'b0;
count_bytes_in_hold_reg = 4'h0;
count_bytes_in_decode_reg = 4'h0;
count_bytes_instr = 4'h0;
count_bytes_in_prefix = 3'b0;
data_size = `DATA_SIZE_32;
direction = `DIR_L2R;
isImmediate = 1'b0;
hasStartAddress = 1'b0;
isRegImplicit = 1'b0;
implicitRegVal = 3'b000;
end
always @(i_reset or i_data) begin
if (i_reset) begin
decode_reg = `SIZE_DECODE_REG'b0;
decode_tmp_reg = `SIZE_DECODE_REG'b0;
decode_hold_reg = `SIZE_DECODE_REG'b0;
count_bytes_in_hold_reg = 4'h0;
count_bytes_in_decode_reg = 4'h0;
count_bytes_instr = 4'h0;
count_bytes_in_prefix = 3'b0;
data_size = `DATA_SIZE_32;
direction = `DIR_R2L;
isImmediate = 1'b0;
hasStartAddress = 1'b0;
isRegImplicit = 1'b0;
implicitRegVal = 3'b000;
end
if (!i_reset && i_ready && !hasStartAddress) begin
hasStartAddress <= 1'b1;
last_address <= i_data;
$display("Got address");
end
if (!i_reset && i_ready && hasStartAddress) begin
decode_tmp_reg = i_data;
decode_reg = (decode_hold_reg | (decode_tmp_reg<<(8*count_bytes_in_hold_reg)));
decode_hold_reg = decode_reg; // keep a copy here.
count_bytes_in_decode_reg = count_bytes_in_hold_reg + 4; // Every time we get a 32 bit input from memory
count_bytes_in_hold_reg = count_bytes_in_decode_reg;
count_bytes_instr = 4'h0;
count_bytes_in_prefix = 3'b0;
process_modrm = 1'b1;
non_modrm = "";
direction = `DIR_R2L;
isImmediate = 1'b0;
isRegImplicit = 1'b0;
implicitRegVal = 3'b000;
/******* Start of Prefix Decoding ********/
if (decode_reg[7:0] == 8'hf0) begin // LOCK
count_bytes_in_prefix = 1;
end
decode_reg = (decode_hold_reg >> (8*count_bytes_in_prefix));
if ((decode_reg[7:0] == 8'hf3) || (decode_reg[7:0] == 8'hf2)) begin // String prefixes
count_bytes_in_prefix = count_bytes_in_prefix + 1;
end
decode_reg = (decode_hold_reg >> (8*count_bytes_in_prefix));
case(decode_reg[7:0]) //Segment override TODO: Not handling segment override for now
8'h2e: count_bytes_in_prefix = count_bytes_in_prefix + 1; // CS
8'h36: count_bytes_in_prefix = count_bytes_in_prefix + 1; // SS
8'h3e: count_bytes_in_prefix = count_bytes_in_prefix + 1; // DS
8'h26: count_bytes_in_prefix = count_bytes_in_prefix + 1; // ES
8'h64: count_bytes_in_prefix = count_bytes_in_prefix + 1; // FS
8'h65: count_bytes_in_prefix = count_bytes_in_prefix + 1; // GS
endcase
decode_reg = (decode_hold_reg >> (8*count_bytes_in_prefix));
if (decode_reg[7:0] == 8'h66) begin // Operand Override
count_bytes_in_prefix = count_bytes_in_prefix + 1;
data_size = `DATA_SIZE_16;
end
decode_reg = (decode_hold_reg >> (8*count_bytes_in_prefix));
if (decode_reg[7:0] == 8'h67) begin // Address Override TODO: Not supporting this
count_bytes_in_prefix = count_bytes_in_prefix + 1;
end
decode_reg = (decode_hold_reg >> (8*count_bytes_in_prefix));
/******* End of Prefix Decoding ********/
count_bytes_instr = count_bytes_in_prefix;
if (count_bytes_instr < count_bytes_in_decode_reg) begin // We start the decoding only if we have enough bytes in decode reg
if (decode_reg[7:0] == 8'h0f) begin // 2 Byte opcode
count_bytes_instr = count_bytes_instr + 1;
decode_reg = (decode_hold_reg >> (8*count_bytes_instr));
//TODO: Decode 2 byte opcode..not doing this for now
end
else begin // 1 byte opcode
if ((decode_reg[7:0] == 8'h00) ||
(decode_reg[7:0] == 8'h01) ||
(decode_reg[7:0] == 8'h02) ||
(decode_reg[7:0] == 8'h03) ||
(decode_reg[7:0] == 8'h04) ||
(decode_reg[7:0] == 8'h05) ||
(decode_reg[7:0] == 8'h80) ||
(decode_reg[7:0] == 8'h81) ||
(decode_reg[7:0] == 8'h83)) begin
mnemonic = "add";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'h28) ||
(decode_reg[7:0] == 8'h29) ||
(decode_reg[7:0] == 8'h2a) ||
(decode_reg[7:0] == 8'h2b) ||
(decode_reg[7:0] == 8'h2c) ||
(decode_reg[7:0] == 8'h2d) ||
(decode_reg[7:0] == 8'h80) ||
(decode_reg[7:0] == 8'h81) ||
(decode_reg[7:0] == 8'h83)) begin
mnemonic = "sub";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'h20) ||
(decode_reg[7:0] == 8'h21) ||
(decode_reg[7:0] == 8'h22) ||
(decode_reg[7:0] == 8'h23) ||
(decode_reg[7:0] == 8'h24) ||
(decode_reg[7:0] == 8'h25) ||
(decode_reg[7:0] == 8'h80) ||
(decode_reg[7:0] == 8'h81) ||
(decode_reg[7:0] == 8'h83)) begin
mnemonic = "and";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'h3a) ||
(decode_reg[7:0] == 8'h3b) ||
(decode_reg[7:0] == 8'h3c) ||
(decode_reg[7:0] == 8'h3d) ||
(decode_reg[7:0] == 8'h38) ||
(decode_reg[7:0] == 8'h39) ||
(decode_reg[7:0] == 8'h80) ||
(decode_reg[7:0] == 8'h81) ||
(decode_reg[7:0] == 8'h83)) begin
mnemonic = "cmp";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'h30) ||
(decode_reg[7:0] == 8'h31) ||
(decode_reg[7:0] == 8'h32) ||
(decode_reg[7:0] == 8'h33) ||
(decode_reg[7:0] == 8'h34) ||
(decode_reg[7:0] == 8'h35) ||
(decode_reg[7:0] == 8'h80) ||
(decode_reg[7:0] == 8'h81) ||
(decode_reg[7:0] == 8'h83)) begin
mnemonic = "xor";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'h86) ||
(decode_reg[7:0] == 8'h87) ||
(decode_reg[7:0] == 8'h90) ||
(decode_reg[7:0] == 8'h91)) begin
mnemonic = "xchg";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'h07) ||
(decode_reg[7:0] == 8'h17) ||
(decode_reg[7:0] == 8'h1f) ||
(decode_reg[7:0] == 8'h58) ||
(decode_reg[7:0] == 8'h8f) ||
(decode_reg[7:0] == 8'h0f) ||
(decode_reg[7:4] == 4'h5 && decode_reg[3] == 1'b1)) begin
mnemonic = "pop";// TODO: Some opcode handline is missing here
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[7:4] == 4'h5 && decode_reg[3] == 1'b1) begin
isRegImplicit = 1'b1;
implicitRegVal = decode_reg[2:0];
minRequiredBytes = count_bytes_instr;
end
else if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
else if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
else if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'h0e) ||
(decode_reg[7:0] == 8'h16) ||
(decode_reg[7:0] == 8'h1e) ||
(decode_reg[7:0] == 8'h06) ||
(decode_reg[7:0] == 8'h0f) ||
(decode_reg[7:0] == 8'h68) ||
(decode_reg[7:0] == 8'h6A) ||
(decode_reg[7:4] == 4'h5 && decode_reg[3] == 1'b0)) begin
mnemonic = "push";// TODO: Some opcode handline is missing here
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[7:4] == 4'h5 && decode_reg[3] == 1'b0) begin
isRegImplicit = 1'b1;
implicitRegVal = decode_reg[2:0];
minRequiredBytes = count_bytes_instr;
end
else if (decode_reg[7:0] == 8'h68) begin
count_bytes_instr = count_bytes_instr + 4;
minRequiredBytes = count_bytes_instr;
process_modrm = 1'b0;
if (count_bytes_instr <= count_bytes_in_decode_reg) begin
$sformat(non_modrm, "$0x%x", decode_reg[39:8]);
end
end
else if (decode_reg[7:0] == 8'h6A) begin
count_bytes_instr = count_bytes_instr + 2;
minRequiredBytes = count_bytes_instr;
process_modrm = 1'b0;
if (count_bytes_instr <= count_bytes_in_decode_reg) begin
$sformat(non_modrm, "$0x%x", decode_reg[23:8]);
end
end
end
else if ((decode_reg[7:0] == 8'hfe) ||
(decode_reg[7:0] == 8'h48)) begin
mnemonic = "dec";// TODO: Some opcode handline is missing here
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'hf6) ||
(decode_reg[7:0] == 8'hf7)) begin
mnemonic = "div";// TODO: Some opcode handline is missing here
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'ha0) ||
(decode_reg[7:0] == 8'ha1) ||
(decode_reg[7:0] == 8'ha2) ||
(decode_reg[7:0] == 8'ha3) ||
(decode_reg[7:0] == 8'hb0) ||
(decode_reg[7:0] == 8'hb8) ||
(decode_reg[7:0] == 8'hc6) ||
(decode_reg[7:0] == 8'hc7) ||
(decode_reg[7:0] == 8'h8a) ||
(decode_reg[7:0] == 8'h8b) ||
(decode_reg[7:0] == 8'h8c) ||
(decode_reg[7:0] == 8'h8e) ||
(decode_reg[7:0] == 8'h88) ||
(decode_reg[7:0] == 8'h89)) begin
mnemonic = "mov";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
/*if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end*/
end
else if (decode_reg[7:0] == 8'h8d) begin
mnemonic = "lea";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'he8) ||
(decode_reg[7:0] == 8'hff) ||
(decode_reg[7:0] == 8'h9a)) begin
mnemonic = "call";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[7:0] == 8'he8) begin
count_bytes_instr = count_bytes_instr + 4;
minRequiredBytes = count_bytes_instr;
process_modrm = 1'b0;
if (count_bytes_instr <= count_bytes_in_decode_reg) begin
$sformat(non_modrm, "$0x%x", decode_reg[39:8]);
end
end
else begin
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
end
else if ((decode_reg[7:0] == 8'hea) ||
(decode_reg[7:0] == 8'heb) ||
(decode_reg[7:0] == 8'he9)) begin
mnemonic = "jmp"; // TODO: handle 8/16/32 bit jmp for now all are 32
count_bytes_instr = count_bytes_instr + 1;
count_bytes_instr = count_bytes_instr + 4;
minRequiredBytes = count_bytes_instr;
process_modrm = 1'b0;
if (count_bytes_instr <= count_bytes_in_decode_reg) begin
$sformat(non_modrm, "$0x%x", decode_reg[39:8]);
end
end
else if ((decode_reg[7:0] == 8'hc2) ||
(decode_reg[7:0] == 8'hc3) ||
(decode_reg[7:0] == 8'hca) ||
(decode_reg[7:0] == 8'hcb)) begin
mnemonic = "ret";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[7:0] == 8'hc3 || decode_reg[7:0] == 8'hcb) begin
end
else begin
count_bytes_instr = count_bytes_instr + 2; // 2 byte immediate
$sformat(non_modrm, "$0x%x", decode_reg[23:8]);
end
minRequiredBytes = count_bytes_instr;
process_modrm = 1'b0;
end
else if (decode_reg[7:0] == 8'hf4) begin
mnemonic = "hlt";
count_bytes_instr = count_bytes_instr + 1;
minRequiredBytes = count_bytes_instr;
process_modrm = 1'b0;
end
else begin
$display("Unidentified instr %x", decode_reg);
end
if (isRegImplicit == 1'b1) begin
if (count_bytes_instr <= count_bytes_in_decode_reg) begin
display(last_address, get_code(decode_reg, minRequiredBytes), mnemonic, get_reg(implicitRegVal));
prepare_for_next_instr(decode_reg, decode_hold_reg, minRequiredBytes, count_bytes_in_hold_reg, count_bytes_in_decode_reg, last_address);
end
end
else if (process_modrm) begin
if (count_bytes_instr < count_bytes_in_decode_reg) begin // This means it has the mod/rm byte
minRequiredBytes = (count_bytes_instr + 1 + instruction_length(decode_reg[15:8], data_size, direction, isImmediate));
if (minRequiredBytes <= count_bytes_in_decode_reg) begin
display(last_address, get_code(decode_reg, minRequiredBytes), mnemonic, decode_mod_reg_rm(decode_reg, data_size, direction, isImmediate));
prepare_for_next_instr(decode_reg, decode_hold_reg, minRequiredBytes, count_bytes_in_hold_reg, count_bytes_in_decode_reg, last_address);
end
end
end
else begin
if (count_bytes_instr <= count_bytes_in_decode_reg) begin
display(last_address, get_code(decode_reg, minRequiredBytes), mnemonic, non_modrm);
prepare_for_next_instr(decode_reg, decode_hold_reg, minRequiredBytes, count_bytes_in_hold_reg, count_bytes_in_decode_reg, last_address);
end
end
$display("decode reg curr val %x", decode_reg);
end
end
end
else begin
instr_size <= 1'bx;
end
end
// Shift data in decode register by appropriate bytes and tranfer the same to the hold register to be processed with next instruction
// and simulataneously update the respective byte counters.
task prepare_for_next_instr(
inout[`SIZE_DECODE_REG - 1: 0] decode_reg,
inout[`SIZE_DECODE_REG - 1: 0] decode_hold_reg,
reg[3:0] minRequiredBytes,
inout[3:0] count_bytes_in_hold_reg,
inout[3:0] count_bytes_in_decode_reg,
inout[31:0] last_address);
decode_reg = (decode_hold_reg >> (8*minRequiredBytes));
decode_hold_reg = decode_reg;
count_bytes_in_decode_reg = count_bytes_in_hold_reg - minRequiredBytes; // No need to do this only need to update the hold reg count val
count_bytes_in_hold_reg = count_bytes_in_decode_reg;
last_address = last_address + minRequiredBytes;
endtask
task display(
input[31:0] instr_address,
string bytes,
string opcode,
string operands);
$display("%x:\t%-24s\t %-5s %s", last_address, bytes, opcode, operands);
endtask
function string get_code(input[`SIZE_DECODE_REG-1:0] data, reg[3:0] num_bytes);
string result = "";
string tmpStr = "";
reg[3:0] byte_index;
reg[`SIZE_DECODE_REG-1:0] tmp;
result = "";
for (byte_index = 0; byte_index < num_bytes; byte_index = byte_index + 1) begin
tmp = data >> (byte_index * 8);
tmpStr = result;
$sformat(result, "%s %x", tmpStr, tmp[7:0]);
end
return result;
endfunction
//TODO: Not supporting immediate data mode for 00, 01 and 10 cases
function string decode_mod_reg_rm(input[63:0] data, reg[1:0] data_size, reg[1:0] direction, reg isImmediate); // Assuming instr length 1 byte and 1 byte for mod-rm and max 4 byte displacement
string result = "";
string srcImmediate = "";
case(data[15:14]) // Mod bits
2'b00: begin // Indirect addressing mode
if (data[10:8] == 3'b100) begin // SIB Addressing mode
if (data[23:22] > 0) // scaling present, TODO - verify 32 but displacement
$sformat(result, "%s, (%s, %s*%d+%x)", get_reg(data[13:11], data_size), get_reg(data[18:16], data_size), get_reg(data[21:19], data_size), get_scale(data[23:22]), data[55:24]);
else
$sformat(result, "%s, (%s, %s+%x)", get_reg(data[13:11], data_size), get_reg(data[18:16], data_size), get_reg(data[21:19], data_size), data[55:24]);
end
else if (data[10:8] == 3'b101) begin // Displacement mode
$sformat(result, "%x", data[47:16]);
end
else begin
result = {"(", get_reg(data[10:8], data_size), ")", ", ", get_reg(data[13:11], data_size)};
end
end
2'b01: begin // Same as above but with 8 bit displacement
if (data[10:8] == 3'b100) begin // SIB Addressing mode
if (data[23:22] > 0) // scaling present
$sformat(result, "%s, (%s,%s*%d+%x)", get_reg(data[13:11], data_size), get_reg(data[18:16], data_size), get_reg(data[21:19], data_size), get_scale(data[23:22]), data[31:24]);
else
$sformat(result, "%s, (%s, %s+%x)", get_reg(data[13:11], data_size), get_reg(data[18:16], data_size), get_reg(data[21:19], data_size), data[31:24]);
end
else if (data[10:8] == 3'b101) begin // Displacement mode
$sformat(result, "%x", data[23:16]);
end
else begin
result = {"(", get_reg(data[10:8], data_size), ")", ", ", get_reg(data[13:11], data_size)};
end
end
2'b10: begin // 32-bit Displacement will be added to reg directly, TODO - Verify 32 bit displacement
$sformat(result, "(%s+%x)", get_reg(data[10:8], data_size), data[47:16]);
end
2'b11: begin // Direct addressing
if (isImmediate == 1'b0) begin
result = {get_reg(data[13:11], data_size), ", ", get_reg(data[10:8], data_size)};
end
else begin
if (data_size == `DATA_SIZE_8 || direction == 1'b1) begin
$sformat(srcImmediate, "$0x%x", data[23:16]); // 8 bit immediate data
end
else if (data_size == `DATA_SIZE_16)
$sformat(srcImmediate, "$0x%x", data[31:16]); // 16 bit immediate data
else
$sformat(srcImmediate, "$0x%x", data[47:16]); // 32 bit immediate data
result = {srcImmediate, ",", get_reg(data[10:8], data_size)};
end
end
endcase
return result;
endfunction
function [3:0] get_scale(input[1:0] scale_bits); // Scale value corresponding to scale bits
case(scale_bits)
2'b00: get_scale = 4'h1;
2'b01: get_scale = 4'h2;
2'b10: get_scale = 4'h4;
2'b11: get_scale = 4'h8;
endcase
endfunction
function [3:0] instruction_length(input[7:0] modrm, reg[1:0] data_size, reg[1:0] direction, reg isImmediate); // nstruction length apart from prefix, opcode and mod/rm length
reg[3:0] count_sib = 0;
reg[3:0] count_displacement = 0;
reg[3:0] count_immediate = 0;
count_sib = 0;
count_displacement = 0;
count_immediate = 0;
case(modrm[7:6]) // mod bits
2'b00: begin
if (modrm[2:0] == 3'b100) begin
count_sib = 31'd1;
count_displacement = 31'd4;
end
else if (modrm[2:0] == 3'b101) begin
count_displacement = 31'd4;
end
end
2'b01: begin
if (modrm[2:0] == 3'b100) begin
count_sib = 31'd1;
count_displacement = 31'd1;
end
else if (modrm[2:0] == 3'b101) begin
count_displacement = 31'd1;
end
end
2'b10: begin
count_displacement = 31'd4;
end
2'b11: begin
if (isImmediate == 1'b1) begin
if (data_size == `DATA_SIZE_8 || direction == 1'b1) begin
count_immediate = 1;
end
else if (data_size == `DATA_SIZE_16)
count_immediate = 2;
else
count_immediate = 4;
end
end
endcase
instruction_length = count_sib + count_displacement + count_immediate;
endfunction
function string get_reg(input[2:0] code, input[1:0] data_size = `DATA_SIZE_32);
case (code)
3'b000: begin
if (data_size == `DATA_SIZE_8)
get_reg = "%al";
else if (data_size == `DATA_SIZE_16)
get_reg = "%ax";
else
get_reg = "%eax";
end
3'b001: begin
if (data_size == `DATA_SIZE_8)
get_reg = "%cl";
else if (data_size == `DATA_SIZE_16)
get_reg = "%cx";
else
get_reg = "%ecx";
end
3'b010: begin
if (data_size == `DATA_SIZE_8)
get_reg = "%dl";
else if (data_size == `DATA_SIZE_16)
get_reg = "%dx";
else
get_reg = "%edx";
end
3'b011: begin
if (data_size == `DATA_SIZE_8)
get_reg = "%bl";
else if (data_size == `DATA_SIZE_16)
get_reg = "%bx";
else
get_reg = "%ebx";
end
3'b100: begin
if (data_size == `DATA_SIZE_8)
get_reg = "%ah";
else if (data_size == `DATA_SIZE_16)
get_reg = "%sp";
else
get_reg = "%esp";
end
3'b101: begin
if (data_size == `DATA_SIZE_8)
get_reg = "%ch";
else if (data_size == `DATA_SIZE_16)
get_reg = "%bp";
else
get_reg = "%ebp";
end
3'b110: begin
if (data_size == `DATA_SIZE_8)
get_reg = "%dh";
else if (data_size == `DATA_SIZE_16)
get_reg = "%si";
else
get_reg = "%esi";
end
3'b111: begin
if (data_size == `DATA_SIZE_8)
get_reg = "%bh";
else if (data_size == `DATA_SIZE_16)
get_reg = "%di";
else
get_reg = "%edi";
end
endcase
endfunction
endmodule |
module t_ram (
aclr,
clock,
data,
rdaddress,
rden,
wraddress,
wren,
q);
input aclr;
input clock;
input [26:0] data;
input [14:0] rdaddress;
input rden;
input [14:0] wraddress;
input wren;
output [26:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clock;
tri1 rden;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [26:0] sub_wire0;
wire [26:0] q = sub_wire0[26:0];
altsyncram altsyncram_component (
.aclr0 (aclr),
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.rden_b (rden),
.wren_a (wren),
.q_b (sub_wire0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({27{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "CLEAR0",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
/*
`ifdef MODEL_TECH
altsyncram_component.init_file = "../sim/t_ram_test.hex",
`endif //MODEL_TECH
*/
altsyncram_component.intended_device_family = "Arria V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 20480,
altsyncram_component.numwords_b = 20480,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "CLEAR0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.rdcontrol_reg_b = "CLOCK0",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 15,
altsyncram_component.widthad_b = 15,
altsyncram_component.width_a = 27,
altsyncram_component.width_b = 27,
altsyncram_component.width_byteena_a = 1;
endmodule |
module axi_slave_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 11
)
(
// Users to add ports here
// Passthrough signals
output wire S_AXI_ACLK,
output wire S_AXI_ARESETN,
output wire [C_S00_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
output wire [2 : 0] S_AXI_AWPROT,
output wire S_AXI_AWVALID,
input wire S_AXI_AWREADY,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
output wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
output wire S_AXI_WVALID,
input wire S_AXI_WREADY,
input wire [1 : 0] S_AXI_BRESP,
input wire S_AXI_BVALID,
output wire S_AXI_BREADY,
output wire [C_S00_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
output wire [2 : 0] S_AXI_ARPROT,
output wire S_AXI_ARVALID,
input wire S_AXI_ARREADY,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
input wire [1 : 0] S_AXI_RRESP,
input wire S_AXI_RVALID,
output wire S_AXI_RREADY,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Add user logic here
assign S_AXI_ACLK = s00_axi_aclk;
assign S_AXI_ARESETN = s00_axi_aresetn;
assign S_AXI_AWADDR = s00_axi_awaddr;
assign S_AXI_AWPROT = s00_axi_awprot;
assign S_AXI_AWVALID = s00_axi_awvalid;
assign s00_axi_awready = S_AXI_AWREADY;
assign S_AXI_WDATA = s00_axi_wdata;
assign S_AXI_WSTRB = s00_axi_wstrb;
assign S_AXI_WVALID = s00_axi_wvalid;
assign s00_axi_wready = S_AXI_WREADY;
assign s00_axi_bresp = S_AXI_BRESP;
assign s00_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s00_axi_bready;
assign S_AXI_ARADDR = s00_axi_araddr;
assign S_AXI_ARPROT = s00_axi_arprot;
assign S_AXI_ARVALID = s00_axi_arvalid;
assign s00_axi_arready = S_AXI_ARREADY;
assign s00_axi_rdata = S_AXI_RDATA;
assign s00_axi_rresp = S_AXI_RRESP;
assign s00_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s00_axi_rready;
// User logic ends
endmodule |
module sky130_fd_sc_ms__nand4b_2 (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ms__nand4b_2 (
Y ,
A_N,
B ,
C ,
D
);
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule |
module sbn (clk, state, PC, a, b);
parameter fwidth = 8; // field width of sbn operand
parameter dwidth = 32;
input clk;
output [2:0] state;
output [fwidth-1:0] PC;
output [dwidth-1:0] a, b;
parameter iwidth = 4 * fwidth;
reg [iwidth-1:0] imem[0:((1<<fwidth)-1)];
reg [dwidth-1:0] dmem[0:((1<<fwidth)-1)];
reg [dwidth-1:0] X, Y;
reg [fwidth-1:0] PC;
reg [iwidth-1:0] IR;
wire [iwidth-1:0] insn;
wire [dwidth-1:0] data, asubb;
wire [fwidth-1:0] addr, PCp1, A, B, C, D;
wire altb, stp;
reg [1:0] da;
reg [2:0] state, nextstate;
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
parameter S3 = 3'b011;
parameter S4 = 3'b100;
parameter S5 = 3'b101;
parameter S6 = 3'b111;
// datapath
assign insn = imem[PC];
assign data = dmem[addr];
assign a = X; // for monitoring
assign b = Y; // for monitoring
assign asubb = X - Y;
assign altb = asubb[dwidth-1];
assign PCp1 = PC + 1;
assign A = IR[(4*fwidth-1):(3*fwidth)];
assign B = IR[(3*fwidth-1):(2*fwidth)];
assign C = IR[(2*fwidth-1):fwidth];
assign D = IR[fwidth-1:0];
assign stp = (C == ~{fwidth{1'b0}}) ? 1 : 0;
assign addr = (da == 2'b00) ? A : ((da == 2'b01) ? B : C);
always @ (posedge clk)
case (state) // action at end of state cycle
S0: begin
IR <= insn;
da <= 2'b00;
end
S1: begin
X <= data;
da <= 2'b01;
end
S2: begin
Y <= data;
da <= 2'b10;
end
S3: begin
dmem[addr] <= asubb;
$display("mw:DMEM,%h,%h", addr, asubb);
end
S4: PC <= D;
S5: PC <= PCp1;
S6: begin
// $display("program caused halt with value %d\n",asubb);
$finish;
end
endcase
// state register
always @ (posedge clk)
state <= nextstate;
// next state logic
always @ (state or altb or stp)
case (state)
S0: nextstate = S1;
S1: nextstate = S2;
S2: if (stp ) nextstate = S6;
else nextstate = S3;
S3: if (altb) nextstate = S4;
else nextstate = S5;
default: nextstate = S0;
endcase
initial begin
$readmemh(%PROG%, imem);
$readmemh(%DATA%, dmem);
PC = 0;
state = 0;
$monitor("%d:%b:%h,%h,%h,%h,%h,%h,%h,%h,%h,%h,%h,%h",
$time, clk, PC, X, Y, A, B, C, D, insn, addr, asubb, PCp1, PC);
end // initial begin
endmodule |
module top;
parameter fwidth = 8; // field width of sbn operand
parameter dwidth = 32;
parameter maximum = %MAX_STEPS%;
parameter maxmone = maximum - 1;
parameter step = 10;
reg clk;
wire [2:0] state;
wire [fwidth-1:0] pc;
wire [dwidth-1:0] a, b;
sbn #(fwidth,dwidth) mach1 (clk, state, pc, a, b);
initial begin
$display("=== start ===");
clk = 0;
#maxmone $display("=== end ===");
#1 $finish;
end
always
#step clk = ~clk;
endmodule |
module uart_fifo_64x128 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [7:0] q = sub_wire0[7:0];
wire rdempty = sub_wire1;
wire wrfull = sub_wire2;
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.wrfull (sub_wire2),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Cyclone V",
dcfifo_component.lpm_numwords = 128,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 8,
dcfifo_component.lpm_widthu = 7,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule |
module BRAMFIFO
#(
parameter p1width = 32,
parameter p2depth = 1024,
parameter p3cntr_width = 10
)
(
input CLK,
input RST_N,
input [p1width-1:0] D_IN,
output [p1width-1:0] D_OUT,
input ENQ,
input DEQ,
output EMPTY_N,
output FULL_N,
output [p3cntr_width-1:0] COUNT,
input CLR
);
reg [p3cntr_width-1:0] wptr, wptr_d, wptr_p1; // reg
reg [p3cntr_width-1:0] rptr, rptr_d, rptr_p1; // reg
reg [p3cntr_width-1:0] dcount, dcount_d; // reg
(* ram_style = "block" *) reg [p1width-1:0] mem [p2depth-1:0];
reg [p1width-1:0] mem_d; // comb
reg [p1width-1:0] dout_r; // register
reg inhibit, inhibit_d;
reg mem_wen; // comb
reg nempty, nempty_d;
reg nfull, nfull_d;
always@(posedge CLK) begin
if(RST_N && !CLR) begin
wptr <= wptr_d;
rptr <= rptr_d;
nfull <= nfull_d;
nempty <= nempty_d;
inhibit <= inhibit_d;
dcount <= dcount_d;
if(mem_wen) mem[wptr] <= D_IN;
end
else begin
rptr <= {p3cntr_width{1'b0}};
wptr <= {p3cntr_width{1'b0}};
nfull <= 1'b1;
nempty <= 1'b0;
inhibit <= 1'b0;
dcount <= {p3cntr_width{1'b0}};
end
end
always@(*) begin
wptr_d = wptr;
rptr_d = rptr;
nfull_d = nfull;
nempty_d = nempty;
mem_wen = 1'b0;
inhibit_d = 1'b0;
wptr_p1 = (wptr + 1) % p2depth;
rptr_p1 = (rptr + 1) % p2depth;
dcount_d = dcount;
if(ENQ) begin
wptr_d = wptr_p1;
mem_wen = 1'b1;
end
if(DEQ) begin
rptr_d = rptr_p1;
end
if(ENQ && DEQ) begin
nfull_d = nfull;
nempty_d = nempty;
if(wptr == rptr) inhibit_d = 1'b1;
end
else if(DEQ && !ENQ) begin
nfull_d = 1'b1;
nempty_d = rptr_p1 != wptr;
dcount_d = dcount-1;
end
else if(ENQ && !DEQ) begin
nfull_d = wptr_p1 != rptr;
nempty_d = 1'b1;
dcount_d = dcount+1;
end
end
assign D_OUT = mem[rptr];
assign EMPTY_N = nempty && !inhibit;
assign FULL_N = nfull;
assign COUNT = dcount;
//synopsys translate off
always@(negedge CLK) begin
if(RST_N) begin
if(ENQ && !FULL_N) begin
$display("ERROR, enqueuing to full BRAMFIFO");
$finish(0);
end
if(DEQ && !EMPTY_N) begin
$display("ERROR, dequeuing to empty BRAMFIFO");
$finish(0);
end
end
end
//synopsys translate on
endmodule |
module top();
// Inputs are registered
reg D;
reg SET_B;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SET_B = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 RESET_B = 1'b1;
#200 SET_B = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 RESET_B = 1'b0;
#340 SET_B = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SET_B = 1'b1;
#540 RESET_B = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SET_B = 1'bx;
#680 RESET_B = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__dfbbp dut (.D(D), .SET_B(SET_B), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule |
module sky130_fd_sc_ls__dlygate4sd3 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule |
module sky130_fd_sc_ls__fill_diode_2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__fill_diode base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ls__fill_diode_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__fill_diode base ();
endmodule |
module zynq_design_1_rst_ps7_0_100M_1(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule |
module pll (
inclk0,
c0,
c2,
locked);
input inclk0;
output c0;
output c2;
output locked;
wire [5:0] sub_wire0;
wire sub_wire3;
wire [0:0] sub_wire6 = 1'h0;
wire [2:2] sub_wire2 = sub_wire0[2:2];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c2 = sub_wire2;
wire locked = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.inclk (sub_wire5),
.clk (sub_wire0),
.locked (sub_wire3),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk2_divide_by = 10,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 13,
altpll_component.clk2_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.gate_lock_signal = "NO",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone II",
altpll_component.invalid_lock_multiplier = 5,
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.valid_lock_multiplier = 1;
endmodule |
module attosoc (
input clk,
input reset,
output reg [7:0] led
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk) begin
if (reset)
reset_cnt <= 0;
else
reset_cnt <= reset_cnt + !resetn;
end
parameter integer MEM_WORDS = 256;
parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000; // ROM at 0x0
parameter integer ROM_WORDS = 64;
reg [31:0] rom [0:ROM_WORDS-1];
wire [31:0] rom_rdata = rom[mem_addr[31:2]];
initial $readmemh("firmware.hex", rom);
wire mem_valid;
wire mem_instr;
wire mem_ready;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [3:0] mem_wstrb;
wire [31:0] mem_rdata;
wire rom_ready = mem_valid && mem_addr[31:24] == 8'h00;
wire iomem_valid;
wire iomem_ready;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
wire [3:0] iomem_wstrb;
wire [31:0] iomem_rdata;
assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01);
assign iomem_ready = 1'b1;
assign iomem_wstrb = mem_wstrb;
assign iomem_addr = mem_addr;
assign iomem_wdata = mem_wdata;
wire [31:0] spimemio_cfgreg_do;
always @(posedge clk)
if (iomem_valid && iomem_wstrb[0])
led <= iomem_wdata[7:0];
assign mem_ready = (iomem_valid && iomem_ready) || rom_ready;
assign mem_rdata = rom_rdata;
picorv32 #(
.STACKADDR(STACKADDR),
.PROGADDR_RESET(PROGADDR_RESET),
.PROGADDR_IRQ(32'h 0000_0000),
.BARREL_SHIFTER(0),
.COMPRESSED_ISA(0),
.ENABLE_MUL(0),
.ENABLE_DIV(0),
.ENABLE_IRQ(0),
.ENABLE_IRQ_QREGS(0),
.ENABLE_COUNTERS(0),
.TWO_STAGE_SHIFT(0),
.ENABLE_REGS_16_31(0)
) cpu (
.clk (clk ),
.resetn (resetn ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata )
);
endmodule |
module picosoc_regs (
input clk, wen,
input [5:0] waddr,
input [5:0] raddr1,
input [5:0] raddr2,
input [31:0] wdata,
output [31:0] rdata1,
output [31:0] rdata2
);
reg [31:0] regs [0:31];
always @(posedge clk)
if (wen) regs[waddr[4:0]] <= wdata;
assign rdata1 = regs[raddr1[4:0]];
assign rdata2 = regs[raddr2[4:0]];
endmodule |
module sky130_fd_sc_hs__or3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule |
module axis_eth_fcs_check_64
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [63:0] s_axis_tdata,
input wire [7:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire s_axis_tuser,
/*
* AXI output
*/
output wire [63:0] m_axis_tdata,
output wire [7:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire m_axis_tuser,
/*
* Status
*/
output wire busy,
output wire error_bad_fcs
);
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_PAYLOAD = 2'd1,
STATE_LAST = 2'd2;
reg [1:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg reset_crc;
reg update_crc;
reg shift_in;
reg shift_reset;
reg [7:0] last_cycle_tkeep_reg = 8'd0, last_cycle_tkeep_next;
reg last_cycle_tuser_reg = 1'b0, last_cycle_tuser_next;
reg [63:0] s_axis_tdata_d0 = 64'd0;
reg [7:0] s_axis_tkeep_d0 = 8'd0;
reg s_axis_tvalid_d0 = 1'b0;
reg s_axis_tuser_d0 = 1'b0;
reg busy_reg = 1'b0;
reg error_bad_fcs_reg = 1'b0, error_bad_fcs_next;
reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
reg [31:0] crc_state = 32'hFFFFFFFF;
reg [31:0] crc_state3 = 32'hFFFFFFFF;
wire [31:0] crc_next0;
wire [31:0] crc_next1;
wire [31:0] crc_next2;
wire [31:0] crc_next3;
wire [31:0] crc_next7;
wire crc_valid0 = crc_next0 == ~32'h2144df1c;
wire crc_valid1 = crc_next1 == ~32'h2144df1c;
wire crc_valid2 = crc_next2 == ~32'h2144df1c;
wire crc_valid3 = crc_next3 == ~32'h2144df1c;
// internal datapath
reg [63:0] m_axis_tdata_int;
reg [7:0] m_axis_tkeep_int;
reg m_axis_tvalid_int;
reg m_axis_tready_int_reg = 1'b0;
reg m_axis_tlast_int;
reg m_axis_tuser_int;
wire m_axis_tready_int_early;
assign s_axis_tready = s_axis_tready_reg;
assign busy = busy_reg;
assign error_bad_fcs = error_bad_fcs_reg;
wire last_cycle = state_reg == STATE_LAST;
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(8),
.STYLE("AUTO")
)
eth_crc_8 (
.data_in(last_cycle ? s_axis_tdata_d0[39:32] : s_axis_tdata[7:0]),
.state_in(last_cycle ? crc_state3 : crc_state),
.data_out(),
.state_out(crc_next0)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(16),
.STYLE("AUTO")
)
eth_crc_16 (
.data_in(last_cycle ? s_axis_tdata_d0[47:32] : s_axis_tdata[15:0]),
.state_in(last_cycle ? crc_state3 : crc_state),
.data_out(),
.state_out(crc_next1)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(24),
.STYLE("AUTO")
)
eth_crc_24 (
.data_in(last_cycle ? s_axis_tdata_d0[55:32] : s_axis_tdata[23:0]),
.state_in(last_cycle ? crc_state3 : crc_state),
.data_out(),
.state_out(crc_next2)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_32 (
.data_in(last_cycle ? s_axis_tdata_d0[63:32] : s_axis_tdata[31:0]),
.state_in(last_cycle ? crc_state3 : crc_state),
.data_out(),
.state_out(crc_next3)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(64),
.STYLE("AUTO")
)
eth_crc_64 (
.data_in(s_axis_tdata[63:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next7)
);
always @* begin
state_next = STATE_IDLE;
reset_crc = 1'b0;
update_crc = 1'b0;
shift_in = 1'b0;
shift_reset = 1'b0;
last_cycle_tkeep_next = last_cycle_tkeep_reg;
last_cycle_tuser_next = last_cycle_tuser_reg;
s_axis_tready_next = 1'b0;
m_axis_tdata_int = 64'd0;
m_axis_tkeep_int = 8'd0;
m_axis_tvalid_int = 1'b0;
m_axis_tlast_int = 1'b0;
m_axis_tuser_int = 1'b0;
error_bad_fcs_next = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
s_axis_tready_next = m_axis_tready_int_early;
reset_crc = 1'b1;
m_axis_tdata_int = s_axis_tdata_d0;
m_axis_tkeep_int = s_axis_tkeep_d0;
m_axis_tvalid_int = s_axis_tvalid_d0 && s_axis_tvalid;
m_axis_tlast_int = 1'b0;
m_axis_tuser_int = 1'b0;
if (s_axis_tready && s_axis_tvalid) begin
shift_in = 1'b1;
reset_crc = 1'b0;
update_crc = 1'b1;
if (s_axis_tlast) begin
if (s_axis_tkeep[7:4] == 0) begin
shift_reset = 1'b1;
reset_crc = 1'b1;
m_axis_tlast_int = 1'b1;
m_axis_tuser_int = s_axis_tuser;
m_axis_tkeep_int = {s_axis_tkeep[3:0], 4'b1111};
if ((s_axis_tkeep[3:0] == 4'b0001 && crc_valid0) ||
(s_axis_tkeep[3:0] == 4'b0011 && crc_valid1) ||
(s_axis_tkeep[3:0] == 4'b0111 && crc_valid2) ||
(s_axis_tkeep[3:0] == 4'b1111 && crc_valid3)) begin
// CRC valid
end else begin
m_axis_tuser_int = 1'b1;
error_bad_fcs_next = 1'b1;
end
s_axis_tready_next = m_axis_tready_int_early;
state_next = STATE_IDLE;
end else begin
last_cycle_tkeep_next = {4'b0000, s_axis_tkeep[7:4]};
last_cycle_tuser_next = s_axis_tuser;
s_axis_tready_next = 1'b0;
state_next = STATE_LAST;
end
end else begin
state_next = STATE_PAYLOAD;
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_PAYLOAD: begin
// transfer payload
s_axis_tready_next = m_axis_tready_int_early;
m_axis_tdata_int = s_axis_tdata_d0;
m_axis_tkeep_int = s_axis_tkeep_d0;
m_axis_tvalid_int = s_axis_tvalid_d0 && s_axis_tvalid;
m_axis_tlast_int = 1'b0;
m_axis_tuser_int = 1'b0;
if (s_axis_tready && s_axis_tvalid) begin
shift_in = 1'b1;
update_crc = 1'b1;
if (s_axis_tlast) begin
if (s_axis_tkeep[7:4] == 0) begin
shift_reset = 1'b1;
reset_crc = 1'b1;
m_axis_tlast_int = 1'b1;
m_axis_tuser_int = s_axis_tuser;
m_axis_tkeep_int = {s_axis_tkeep[3:0], 4'b1111};
if ((s_axis_tkeep[3:0] == 4'b0001 && crc_valid0) ||
(s_axis_tkeep[3:0] == 4'b0011 && crc_valid1) ||
(s_axis_tkeep[3:0] == 4'b0111 && crc_valid2) ||
(s_axis_tkeep[3:0] == 4'b1111 && crc_valid3)) begin
// CRC valid
end else begin
m_axis_tuser_int = 1'b1;
error_bad_fcs_next = 1'b1;
end
s_axis_tready_next = m_axis_tready_int_early;
state_next = STATE_IDLE;
end else begin
last_cycle_tkeep_next = {4'b0000, s_axis_tkeep[7:4]};
last_cycle_tuser_next = s_axis_tuser;
s_axis_tready_next = 1'b0;
state_next = STATE_LAST;
end
end else begin
state_next = STATE_PAYLOAD;
end
end else begin
state_next = STATE_PAYLOAD;
end
end
STATE_LAST: begin
// last cycle
s_axis_tready_next = 1'b0;
m_axis_tdata_int = s_axis_tdata_d0;
m_axis_tkeep_int = last_cycle_tkeep_reg;
m_axis_tvalid_int = s_axis_tvalid_d0;
m_axis_tlast_int = 1'b1;
m_axis_tuser_int = last_cycle_tuser_reg;
if ((s_axis_tkeep_d0[7:4] == 4'b0001 && crc_valid0) ||
(s_axis_tkeep_d0[7:4] == 4'b0011 && crc_valid1) ||
(s_axis_tkeep_d0[7:4] == 4'b0111 && crc_valid2) ||
(s_axis_tkeep_d0[7:4] == 4'b1111 && crc_valid3)) begin
// CRC valid
end else begin
m_axis_tuser_int = 1'b1;
error_bad_fcs_next = 1'b1;
end
if (m_axis_tready_int_reg) begin
shift_reset = 1'b1;
reset_crc = 1'b1;
s_axis_tready_next = m_axis_tready_int_early;
state_next = STATE_IDLE;
end else begin
state_next = STATE_LAST;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
s_axis_tready_reg <= 1'b0;
busy_reg <= 1'b0;
error_bad_fcs_reg <= 1'b0;
s_axis_tvalid_d0 <= 1'b0;
crc_state <= 32'hFFFFFFFF;
crc_state3 <= 32'hFFFFFFFF;
end else begin
state_reg <= state_next;
s_axis_tready_reg <= s_axis_tready_next;
busy_reg <= state_next != STATE_IDLE;
error_bad_fcs_reg <= error_bad_fcs_next;
// datapath
if (reset_crc) begin
crc_state <= 32'hFFFFFFFF;
crc_state3 <= 32'hFFFFFFFF;
end else if (update_crc) begin
crc_state <= crc_next7;
crc_state3 <= crc_next3;
end
if (shift_reset) begin
s_axis_tvalid_d0 <= 1'b0;
end else if (shift_in) begin
s_axis_tvalid_d0 <= s_axis_tvalid;
end
end
last_cycle_tkeep_reg <= last_cycle_tkeep_next;
last_cycle_tuser_reg <= last_cycle_tuser_next;
if (shift_in) begin
s_axis_tdata_d0 <= s_axis_tdata;
s_axis_tkeep_d0 <= s_axis_tkeep;
s_axis_tuser_d0 <= s_axis_tuser;
end
end
// output datapath logic
reg [63:0] m_axis_tdata_reg = 64'd0;
reg [7:0] m_axis_tkeep_reg = 8'd0;
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg m_axis_tuser_reg = 1'b0;
reg [63:0] temp_m_axis_tdata_reg = 64'd0;
reg [7:0] temp_m_axis_tkeep_reg = 8'd0;
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0;
reg temp_m_axis_tuser_reg = 1'b0;
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tkeep = m_axis_tkeep_reg;
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = m_axis_tlast_reg;
assign m_axis_tuser = m_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_axis_tready_int_reg) begin
// input is ready
if (m_axis_tready || !m_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_axis_tready) begin
// input is not ready, but output is ready
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_axis_tvalid_reg <= 1'b0;
m_axis_tready_int_reg <= 1'b0;
temp_m_axis_tvalid_reg <= 1'b0;
end else begin
m_axis_tvalid_reg <= m_axis_tvalid_next;
m_axis_tready_int_reg <= m_axis_tready_int_early;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_axis_tdata_reg <= m_axis_tdata_int;
m_axis_tkeep_reg <= m_axis_tkeep_int;
m_axis_tlast_reg <= m_axis_tlast_int;
m_axis_tuser_reg <= m_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_axis_tdata_reg <= m_axis_tdata_int;
temp_m_axis_tkeep_reg <= m_axis_tkeep_int;
temp_m_axis_tlast_reg <= m_axis_tlast_int;
temp_m_axis_tuser_reg <= m_axis_tuser_int;
end
end
endmodule |
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg SET_B;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 SET_B = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 D = 1'b1;
#220 RESET_B = 1'b1;
#240 SCD = 1'b1;
#260 SCE = 1'b1;
#280 SET_B = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 D = 1'b0;
#400 RESET_B = 1'b0;
#420 SCD = 1'b0;
#440 SCE = 1'b0;
#460 SET_B = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 SET_B = 1'b1;
#660 SCE = 1'b1;
#680 SCD = 1'b1;
#700 RESET_B = 1'b1;
#720 D = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 SET_B = 1'bx;
#840 SCE = 1'bx;
#860 SCD = 1'bx;
#880 RESET_B = 1'bx;
#900 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hdll__sdfbbp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule |
module sky130_fd_sc_ms__fa (
COUT,
SUM ,
A ,
B ,
CIN
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire nor0_out ;
wire nor1_out ;
wire or1_out_COUT;
wire or2_out_SUM ;
// Name Output Other arguments
or or0 (or0_out , CIN, B );
and and0 (and0_out , or0_out, A );
and and1 (and1_out , B, CIN );
or or1 (or1_out_COUT, and1_out, and0_out);
buf buf0 (COUT , or1_out_COUT );
and and2 (and2_out , CIN, A, B );
nor nor0 (nor0_out , A, or0_out );
nor nor1 (nor1_out , nor0_out, COUT );
or or2 (or2_out_SUM , nor1_out, and2_out);
buf buf1 (SUM , or2_out_SUM );
endmodule |
module tb_USER_LOGIC();
reg CLK, RST;
wire chnl_rx_clk;
wire chnl_rx;
wire chnl_rx_ack;
wire chnl_rx_last;
wire [31:0] chnl_rx_len;
wire [30:0] chnl_rx_off;
wire [128-1:0] chnl_rx_data;
wire chnl_rx_data_valid;
wire chnl_rx_data_ren;
wire chnl_tx_clk;
wire chnl_tx;
wire chnl_tx_ack;
wire chnl_tx_last;
wire [31:0] chnl_tx_len;
wire [30:0] chnl_tx_off;
wire [128-1:0] chnl_tx_data;
wire chnl_tx_data_vaild;
wire chnl_tx_data_ren = 1;
wire d_busy;
wire d_w;
wire [`DRAMW-1:0] d_din;
wire [`DRAMW-1:0] d_dout;
wire d_douten;
wire [1:0] d_req; // DRAM access request (read/write)
wire [31:0] d_initadr; // dram initial address for the access
wire [31:0] d_blocks; // the number of blocks per one access(read/write)
reg sortdone;
initial begin CLK=0; forever #50 CLK=~CLK; end
initial begin RST=1; #400 RST=0; end
reg [31:0] cnt;
always @(posedge CLK) cnt <= (RST) ? 0 : cnt + 1;
reg [31:0] cnt0, cnt1, cnt2, cnt3, cnt4, cnt5, cnt6, cnt7, cnt8, cnt9;
always @(posedge CLK) cnt0 <= (RST) ? 0 : (u.core.phase_a==0) ? cnt0 + 1 : cnt0;
always @(posedge CLK) cnt1 <= (RST) ? 0 : (u.core.phase_a==1) ? cnt1 + 1 : cnt1;
always @(posedge CLK) cnt2 <= (RST) ? 0 : (u.core.phase_a==2) ? cnt2 + 1 : cnt2;
always @(posedge CLK) cnt3 <= (RST) ? 0 : (u.core.phase_a==3) ? cnt3 + 1 : cnt3;
always @(posedge CLK) cnt4 <= (RST) ? 0 : (u.core.phase_a==4) ? cnt4 + 1 : cnt4;
always @(posedge CLK) cnt5 <= (RST) ? 0 : (u.core.phase_a==5) ? cnt5 + 1 : cnt5;
always @(posedge CLK) cnt6 <= (RST) ? 0 : (u.core.phase_a==6) ? cnt6 + 1 : cnt6;
always @(posedge CLK) cnt7 <= (RST) ? 0 : (u.core.phase_a==7) ? cnt7 + 1 : cnt7;
always @(posedge CLK) cnt8 <= (RST) ? 0 : (u.core.phase_a==8) ? cnt8 + 1 : cnt8;
always @(posedge CLK) cnt9 <= (RST) ? 0 : (u.core.phase_a==9) ? cnt9 + 1 : cnt9;
reg [31:0] rslt_cnt;
always @(posedge CLK) begin
if (RST) begin
rslt_cnt <= 0;
end else begin
if (chnl_tx_data_vaild) rslt_cnt <= rslt_cnt + 4;
end
end
always @(posedge CLK) begin
if (RST) sortdone <= 0;
else if (rslt_cnt == `SORT_ELM) sortdone <= 1;
end
// Debug Info
always @(posedge CLK) begin
if (!RST) begin
$write("%d|%d|Pa%dPb%d|%d%d%d|%d", cnt[19:0], u.core.elem_a, u.core.phase_a[2:0], u.core.phase_b[2:0], u.core.iter_done_a, u.core.pchange_a, u.core.irst_a, u.core.ecnt_a);
$write("|");
if (d_douten) $write("%08x %08x ", d_dout[63:32], d_dout[31:0]); else $write(" ");
// $write("%d %d %x ", u.rState, u.rx_wait, u.core.req_pzero);
// if (u.idata_valid) $write("%08x %08x ", u.idata[63:32], u.idata[31:0]); else $write(" ");
// $write("|");
// if (u.core.doen_t) $write("%08x %08x ", u.core.dout_t[63:32], u.core.dout_t[31:0]); else $write(" ");
// $write("|");
// if (u.core.doen_tc) $write("%08x %08x ", u.core.dout_tc[63:32], u.core.dout_tc[31:0]); else $write(" ");
$write("|");
$write("(%d)", u.core.state);
$write("| %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d| %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d|",
u.core.im00_a.imf.cnt, u.core.im01_a.imf.cnt, u.core.im02_a.imf.cnt, u.core.im03_a.imf.cnt,
u.core.im04_a.imf.cnt, u.core.im05_a.imf.cnt, u.core.im06_a.imf.cnt, u.core.im07_a.imf.cnt,
u.core.im08_a.imf.cnt, u.core.im09_a.imf.cnt, u.core.im10_a.imf.cnt, u.core.im11_a.imf.cnt,
u.core.im12_a.imf.cnt, u.core.im13_a.imf.cnt, u.core.im14_a.imf.cnt, u.core.im15_a.imf.cnt,
u.core.im00_b.imf.cnt, u.core.im01_b.imf.cnt, u.core.im02_b.imf.cnt, u.core.im03_b.imf.cnt,
u.core.im04_b.imf.cnt, u.core.im05_b.imf.cnt, u.core.im06_b.imf.cnt, u.core.im07_b.imf.cnt,
u.core.im08_b.imf.cnt, u.core.im09_b.imf.cnt, u.core.im10_b.imf.cnt, u.core.im11_b.imf.cnt,
u.core.im12_b.imf.cnt, u.core.im13_b.imf.cnt, u.core.im14_b.imf.cnt, u.core.im15_b.imf.cnt);
if (u.core.im00_b.imf.cnt > 128) begin $write("\noverflow at im00_b"); $finish(); end
if (u.core.im01_b.imf.cnt > 128) begin $write("\noverflow at im01_b"); $finish(); end
if (u.core.im02_b.imf.cnt > 128) begin $write("\noverflow at im02_b"); $finish(); end
if (u.core.im03_b.imf.cnt > 128) begin $write("\noverflow at im03_b"); $finish(); end
if (u.core.im04_b.imf.cnt > 128) begin $write("\noverflow at im04_b"); $finish(); end
if (u.core.im05_b.imf.cnt > 128) begin $write("\noverflow at im05_b"); $finish(); end
if (u.core.im06_b.imf.cnt > 128) begin $write("\noverflow at im06_b"); $finish(); end
if (u.core.im07_b.imf.cnt > 128) begin $write("\noverflow at im07_b"); $finish(); end
if (u.core.im08_b.imf.cnt > 128) begin $write("\noverflow at im08_b"); $finish(); end
if (u.core.im09_b.imf.cnt > 128) begin $write("\noverflow at im09_b"); $finish(); end
if (u.core.im10_b.imf.cnt > 128) begin $write("\noverflow at im10_b"); $finish(); end
if (u.core.im11_b.imf.cnt > 128) begin $write("\noverflow at im11_b"); $finish(); end
if (u.core.im12_b.imf.cnt > 128) begin $write("\noverflow at im12_b"); $finish(); end
if (u.core.im13_b.imf.cnt > 128) begin $write("\noverflow at im13_b"); $finish(); end
if (u.core.im14_b.imf.cnt > 128) begin $write("\noverflow at im14_b"); $finish(); end
if (u.core.im15_b.imf.cnt > 128) begin $write("\noverflow at im15_b"); $finish(); end
$write(" ");
if (u.core.F01_deq_a) $write("%08x %08x %08x %08x ", u.core.F01_dot_a[127:96], u.core.F01_dot_a[95:64], u.core.F01_dot_a[63:32], u.core.F01_dot_a[31:0]); else $write(" ");
if (u.core.F01_deq_b) $write("%08x %08x %08x %08x ", u.core.F01_dot_b[127:96], u.core.F01_dot_b[95:64], u.core.F01_dot_b[63:32], u.core.F01_dot_b[31:0]); else $write(" ");
// $write("| ");
// $write("%d", u.core.dcnt);
if (d.app_wdf_wren) $write(" |M%d %d ", d_din[63:32], d_din[31:0]);
$write("\n");
$fflush();
end
end
// checking the result
generate
if (`INITTYPE=="sorted" || `INITTYPE=="reverse") begin
reg [`MERGW-1:0] check_cnt;
always @(posedge CLK) begin
if (RST) begin
check_cnt[31 : 0] <= 1;
check_cnt[63 :32] <= 2;
check_cnt[95 :64] <= 3;
check_cnt[127:96] <= 4;
end else begin
if (chnl_tx_data_vaild) begin
if (check_cnt != chnl_tx_data) begin
$write("Error in sorter.v: %d %d\n", chnl_tx_data, check_cnt); // for simulation
$finish(); // for simulation
end
check_cnt[31 : 0] <= check_cnt[31 : 0] + 4;
check_cnt[63 :32] <= check_cnt[63 :32] + 4;
check_cnt[95 :64] <= check_cnt[95 :64] + 4;
check_cnt[127:96] <= check_cnt[127:96] + 4;
end
end
end
end else if (`INITTYPE=="xorshift") begin
integer fp;
initial begin fp = $fopen("log.txt", "w"); end
always @(posedge CLK) begin
if (chnl_tx_data_vaild) begin
$fwrite(fp, "%08x\n", chnl_tx_data[31:0]);
$fwrite(fp, "%08x\n", chnl_tx_data[63:32]);
$fwrite(fp, "%08x\n", chnl_tx_data[95:64]);
$fwrite(fp, "%08x\n", chnl_tx_data[127:96]);
$fflush();
end
if (sortdone) $fclose(fp);
end
end else begin
always @(posedge CLK) begin
$write("Error! INITTYPE is wrong.\n");
$write("Please make sure src/define.vh\n");
$finish();
end
end
endgenerate
// Show the elapsed cycles
always @(posedge CLK) begin
if(sortdone) begin : simulation_finish
$write("\nIt takes %d cycles\n", cnt);
$write("phase0: %d cycles\n", cnt0);
$write("phase1: %d cycles\n", cnt1);
$write("phase2: %d cycles\n", cnt2);
$write("phase3: %d cycles\n", cnt3);
$write("phase4: %d cycles\n", cnt4);
$write("phase5: %d cycles\n", cnt5);
$write("phase6: %d cycles\n", cnt6);
$write("phase7: %d cycles\n", cnt7);
$write("phase8: %d cycles\n", cnt8);
$write("phase9: %d cycles\n", cnt9);
$write("Sorting finished!\n");
$finish();
end
end
// Stub modules
/**********************************************************************************************/
Host_to_FPGA h2f(CLK, RST, chnl_rx_data_ren, chnl_rx, chnl_rx_data, chnl_rx_data_valid, chnl_rx_len);
DRAM d(CLK, RST, d_req, d_initadr, d_blocks, d_din, d_w, d_dout, d_douten, d_busy);
/***** Core Module Instantiation *****/
/**********************************************************************************************/
USER_LOGIC u(CLK,
RST,
chnl_rx_clk,
chnl_rx,
chnl_rx_ack,
chnl_rx_last,
chnl_rx_len,
chnl_rx_off,
chnl_rx_data,
chnl_rx_data_valid,
chnl_rx_data_ren,
chnl_tx_clk,
chnl_tx,
chnl_tx_ack,
chnl_tx_last,
chnl_tx_len,
chnl_tx_off,
chnl_tx_data,
chnl_tx_data_vaild,
chnl_tx_data_ren,
d_busy, // DRAM busy
d_din, // DRAM data in
d_w, // DRAM write flag
d_dout, // DRAM data out
d_douten, // DRAM data out enable
d_req, // DRAM REQ access request (read/write)
d_initadr, // DRAM REQ initial address for the access
d_blocks // DRAM REQ the number of blocks per one access
);
endmodule |
module XORSHIFT #(parameter WIDTH = 32,
parameter SEED = 1)
(input wire CLK,
input wire RST,
input wire EN,
output wire [WIDTH-1:0] RAND_VAL);
reg [WIDTH-1:0] x;
reg [WIDTH-1:0] y;
reg [WIDTH-1:0] z;
reg [WIDTH-1:0] w;
wire [WIDTH-1:0] t = x^(x<<11);
// Mask MSB for not generating the maximum value
assign RAND_VAL = {1'b0, w[WIDTH-2:0]};
reg ocen;
always @(posedge CLK) ocen <= RST;
always @(posedge CLK) begin
if (RST) begin
x <= 123456789;
y <= 362436069;
z <= 521288629;
w <= 88675123 ^ SEED;
end else begin
if (EN || ocen) begin
x <= y;
y <= z;
z <= w;
w <= (w^(w>>19))^(t^(t>>8));
end
end
end
endmodule |
module Host_to_FPGA(input wire CLK,
input wire RST,
input wire ren,
output reg chnl_rx,
output wire [`MERGW-1:0] dot,
output wire doten,
output wire [31:0] length);
reg rst_buf; always @(posedge CLK) rst_buf <= RST;
wire enq;
wire deq;
wire [`MERGW-1:0] din;
wire emp;
wire ful;
wire [4:0] cnt;
reg [`SORTW-1:0] i_d,i_c,i_b,i_a;
reg onetime;
reg [31:0] enqcnt;
reg enqstop;
wire [`SORTW-1:0] r15,r14,r13,r12,r11,r10,r09,r08,r07,r06,r05,r04,r03,r02,r01,r00;
reg [1:0] selector;
wire [`MERGW-1:0] din_xorshift = (selector == 0) ? {r03,r02,r01,r00} :
(selector == 1) ? {r07,r06,r05,r04} :
(selector == 2) ? {r11,r10,r09,r08} :
(selector == 3) ? {r15,r14,r13,r12} : 0;
SRL_FIFO #(4, `MERGW) fifo(CLK, rst_buf, enq, deq, din, dot, emp, ful, cnt);
assign enq = (!enqstop && !ful);
assign deq = (ren && !emp);
assign din = (`INITTYPE=="xorshift") ? din_xorshift : {i_d,i_c,i_b,i_a};
assign doten = deq;
assign length = `SORT_ELM;
always @(posedge CLK) begin
if (rst_buf) begin
chnl_rx <= 0;
onetime <= 1;
end else begin
chnl_rx <= onetime;
onetime <= 0;
end
end
always @(posedge CLK) begin
if (rst_buf) enqcnt <= 0;
else if (enq) enqcnt <= enqcnt + 4;
end
always @(posedge CLK) begin
if (rst_buf) enqstop <= 0;
else if (enq && (enqcnt == `SORT_ELM-4)) enqstop <= 1;
end
always @(posedge CLK) begin
if (rst_buf) selector <= 0;
else if (enq) selector <= selector + 1;
end
generate
if (`INITTYPE=="sorted") begin
always @(posedge CLK) begin
if (rst_buf) begin
i_a <= 1;
i_b <= 2;
i_c <= 3;
i_d <= 4;
end else begin
if (enq) begin
i_a <= i_a+4;
i_b <= i_b+4;
i_c <= i_c+4;
i_d <= i_d+4;
end
end
end
end else if (`INITTYPE=="reverse") begin
always @(posedge CLK) begin
if (rst_buf) begin
i_a <= `SORT_ELM;
i_b <= `SORT_ELM-1;
i_c <= `SORT_ELM-2;
i_d <= `SORT_ELM-3;
end else begin
if (enq) begin
i_a <= i_a-4;
i_b <= i_b-4;
i_c <= i_c-4;
i_d <= i_d-4;
end
end
end
end else if (`INITTYPE=="xorshift") begin
XORSHIFT #(`SORTW, 32'h00000001) xorshift00(CLK, RST, (enq && selector == 0), r00);
XORSHIFT #(`SORTW, 32'h00000002) xorshift01(CLK, RST, (enq && selector == 0), r01);
XORSHIFT #(`SORTW, 32'h00000004) xorshift02(CLK, RST, (enq && selector == 0), r02);
XORSHIFT #(`SORTW, 32'h00000008) xorshift03(CLK, RST, (enq && selector == 0), r03);
XORSHIFT #(`SORTW, 32'h00000010) xorshift04(CLK, RST, (enq && selector == 1), r04);
XORSHIFT #(`SORTW, 32'h00000020) xorshift05(CLK, RST, (enq && selector == 1), r05);
XORSHIFT #(`SORTW, 32'h00000040) xorshift06(CLK, RST, (enq && selector == 1), r06);
XORSHIFT #(`SORTW, 32'h00000080) xorshift07(CLK, RST, (enq && selector == 1), r07);
XORSHIFT #(`SORTW, 32'h00000100) xorshift08(CLK, RST, (enq && selector == 2), r08);
XORSHIFT #(`SORTW, 32'h00000200) xorshift09(CLK, RST, (enq && selector == 2), r09);
XORSHIFT #(`SORTW, 32'h00000400) xorshift10(CLK, RST, (enq && selector == 2), r10);
XORSHIFT #(`SORTW, 32'h00000800) xorshift11(CLK, RST, (enq && selector == 2), r11);
XORSHIFT #(`SORTW, 32'h00001000) xorshift12(CLK, RST, (enq && selector == 3), r12);
XORSHIFT #(`SORTW, 32'h00002000) xorshift13(CLK, RST, (enq && selector == 3), r13);
XORSHIFT #(`SORTW, 32'h00004000) xorshift14(CLK, RST, (enq && selector == 3), r14);
XORSHIFT #(`SORTW, 32'h00008000) xorshift15(CLK, RST, (enq && selector == 3), r15);
end
endgenerate
endmodule |
module DRAM(input wire CLK, //
input wire RST, //
input wire [1:0] D_REQ, // dram request, load or store
input wire [31:0] D_INITADR, // dram request, initial address
input wire [31:0] D_ELEM, // dram request, the number of elements
input wire [`DRAMW-1:0] D_DIN, //
output wire D_W, //
output reg [`DRAMW-1:0] D_DOUT, //
output reg D_DOUTEN, //
output wire D_BUSY); //
/******* DRAM ******************************************************/
localparam M_REQ = 0;
localparam M_WRITE = 1;
localparam M_READ = 2;
///////////////////////////////////////////////////////////////////////////////////
reg [`DDR3_CMD] app_cmd;
reg app_en;
wire [`DRAMW-1:0] app_wdf_data;
reg app_wdf_wren;
wire app_wdf_end = app_wdf_wren;
// outputs of u_dram
wire [`DRAMW-1:0] app_rd_data;
wire app_rd_data_end;
wire app_rd_data_valid=1; // in simulation, always ready !!
wire app_rdy = 1; // in simulation, always ready !!
wire app_wdf_rdy = 1; // in simulation, always ready !!
wire ui_clk = CLK;
reg [1:0] mode;
reg [`DRAMW-1:0] app_wdf_data_buf;
reg [31:0] caddr; // check address
reg [31:0] remain, remain2; //
reg [7:0] req_state; //
///////////////////////////////////////////////////////////////////////////////////
reg [`DRAMW-1:0] mem [`DRAM_SIZE-1:0];
reg [31:0] app_addr;
reg [31:0] dram_addr;
always @(posedge CLK) dram_addr <= app_addr;
always @(posedge CLK) begin /***** DRAM WRITE *****/
if (RST) begin end
else if(app_wdf_wren) mem[dram_addr[27:3]] <= app_wdf_data;
end
assign app_rd_data = mem[app_addr[27:3]];
assign app_wdf_data = D_DIN;
assign D_BUSY = (mode!=M_REQ); // DRAM busy
assign D_W = (mode==M_WRITE && app_rdy && app_wdf_rdy); // store one element
///// READ & WRITE PORT CONTROL (begin) ////////////////////////////////////////////
always @(posedge ui_clk) begin
if (RST) begin
mode <= M_REQ;
{app_addr, app_cmd, app_en, app_wdf_wren} <= 0;
{D_DOUT, D_DOUTEN} <= 0;
{caddr, remain, remain2, req_state} <= 0;
end else begin
case (mode)
///////////////////////////////////////////////////////////////// request
M_REQ: begin
D_DOUTEN <= 0;
if(D_REQ==`DRAM_REQ_WRITE) begin ///// WRITE or STORE request
app_cmd <= `DRAM_CMD_WRITE;
mode <= M_WRITE;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // the number of blocks to be written
end
else if(D_REQ==`DRAM_REQ_READ) begin ///// READ or LOAD request
app_cmd <= `DRAM_CMD_READ;
mode <= M_READ;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // param, the number of blocks to be read
remain2 <= D_ELEM; // param, the number of blocks to be read
end
else begin
app_wdf_wren <= 0;
app_en <= 0;
end
end
//////////////////////////////////////////////////////////////////// read
M_READ: begin
if (app_rdy) begin // read request is accepted.
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain2 <= remain2 - 1;
if(remain2==1) app_en <= 0;
end
D_DOUTEN <= app_rd_data_valid; // dram data_out enable
if (app_rd_data_valid) begin
D_DOUT <= app_rd_data;
caddr <= (caddr==`MEM_LAST_ADDR) ? 0 : caddr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
end
end
end
/////////////////////////////////////////////////////////////////// write
M_WRITE: begin
if (app_rdy && app_wdf_rdy) begin
app_wdf_wren <= 1;
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
app_en <= 0;
end
end
else app_wdf_wren <= 0;
end
endcase
end
end
///// READ & WRITE PORT CONTROL (end) //////////////////////////////////////
endmodule |
module sky130_fd_sc_hdll__a211o_2 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hdll__a211o_2 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule |
module sky130_fd_sc_lp__sregsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
ASYNC,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input ASYNC;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire set ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire ASYNC_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (set , ASYNC_delayed );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, set, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( ASYNC_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( ASYNC === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule |
module DE4_BERI (
////// clock inputs
//input GCLKIN,
//output GCLKOUT_FPGA,
//inout [2:0] MAX_CONF_D,
//output [2:0] MAX_PLL_D,
input OSC_50_Bank2,
input OSC_50_Bank3,
input OSC_50_Bank4,
input OSC_50_Bank5,
input OSC_50_Bank6,
//input OSC_50_Bank7,
//input PLL_CLKIN_p,
`ifdef ENABLE_LED
output [7:0] LED, // 8x LEDs
`endif
`ifdef ENABLE_BUTTONS
input [3:0] BUTTON, // 4x buttons
`endif
input CPU_RESET_n,
//inout EXT_IO,
`ifdef ENABLE_ETHERNET
////// Ethernet MAC x 4
input [3:0] ETH_INT_n,
output [3:0] ETH_MDC,
inout [3:0] ETH_MDIO,
output ETH_RST_n,
input [3:0] ETH_RX_p,
output [3:0] ETH_TX_p,
`endif
`ifdef ENABLE_SDCARD
////// SD card socket
output SD_CLK,
inout SD_CMD,
inout [3:0] SD_DAT,
input SD_WP_n,
`endif
`ifdef ENABLE_UART
////// UART
output UART_TXD,
input UART_CTS,
input UART_RXD,
output UART_RTS,
`endif
`ifdef ENABLE_DDR2_1
////// DDR2 SODIMM 1
output [15:0] M1_DDR2_addr,
output [2:0] M1_DDR2_ba,
output M1_DDR2_cas_n,
output [1:0] M1_DDR2_cke,
inout [1:0] M1_DDR2_clk,
inout [1:0] M1_DDR2_clk_n,
output [1:0] M1_DDR2_cs_n,
output [7:0] M1_DDR2_dm,
inout [63:0] M1_DDR2_dq,
inout [7:0] M1_DDR2_dqs,
inout [7:0] M1_DDR2_dqsn,
output [1:0] M1_DDR2_odt,
output M1_DDR2_ras_n,
output [1:0] M1_DDR2_SA,
output M1_DDR2_SCL,
inout M1_DDR2_SDA,
output M1_DDR2_we_n,
`endif
`ifdef ENABLE_DDR2_2
////// DDR2 SODIMM 2
output [15:0] M2_DDR2_addr,
output [2:0] M2_DDR2_ba,
output M2_DDR2_cas_n,
output [1:0] M2_DDR2_cke,
inout [1:0] M2_DDR2_clk,
inout [1:0] M2_DDR2_clk_n,
output [1:0] M2_DDR2_cs_n,
output [7:0] M2_DDR2_dm,
inout [63:0] M2_DDR2_dq,
inout [7:0] M2_DDR2_dqs,
inout [7:0] M2_DDR2_dqsn,
output [1:0] M2_DDR2_odt,
output M2_DDR2_ras_n,
output [1:0] M2_DDR2_SA,
output M2_DDR2_SCL,
inout M2_DDR2_SDA,
output M2_DDR2_we_n,
`endif
`ifndef DISABLE_TERMINATION
// termination for DDR2 DIMMs
input termination_blk0_rup_pad,
input termination_blk0_rdn_pad,
`endif
`ifdef ENABLE_DIP
input [7:0] SW, // 8x DIP switches
`endif
`ifdef ENABLE_SLIDE
input [3:0] SLIDE_SW, // 4x slide switches
`endif
`ifdef ENABLE_SEG
// 2x 7-segment displays
output [6:0] SEG0_D,
output SEG0_DP,
output [6:0] SEG1_D,
output SEG1_DP,
`endif
`ifdef ENABLE_TEMP
// temperature sensors
input TEMP_INT_n,
output TEMP_SMCLK,
inout TEMP_SMDAT,
`endif
`ifdef ENABLE_CSENSE
// current sensors
output CSENSE_ADC_FO,
output [1:0] CSENSE_CS_n,
output CSENSE_SCK,
output CSENSE_SDI,
input CSENSE_SDO,
`endif
output FAN_CTRL, // fan control
`ifndef DISABLE_FSM
// flash and SRAM shared data bus
output [25:1] FSM_A,
inout [15:0] FSM_D,
`endif
`ifdef ENABLE_FLASH
// Flash memory
output FLASH_ADV_n,
output FLASH_CE_n,
output FLASH_CLK,
output FLASH_OE_n,
output FLASH_RESET_n,
input FLASH_RYBY_n,
output FLASH_WE_n,
`endif
`ifdef ENABLE_SSRAM
// synchronous SRAM
output SSRAM_ADV,
output SSRAM_BWA_n,
output SSRAM_BWB_n,
output SSRAM_CE_n,
output SSRAM_CKE_n,
output SSRAM_CLK,
output SSRAM_OE_n,
output SSRAM_WE_n,
`endif
// HSMC port A and B
`ifdef ENABLE_HDMI
// HDMI interface board on HSMC port A
//inout HDMI_SDA,
//output HDMI_SCL,
output [11:0] HDMI_TX_RD,
output [11:0] HDMI_TX_GD,
inout HDMI_TX_PCSCL,
inout HDMI_TX_PCSDA,
output HDMI_TX_RST_N,
input HDMI_TX_INT_N,
output [3:0] HDMI_TX_DSD_L,
output [3:0] HDMI_TX_DSD_R,
output [11:0] HDMI_TX_BD,
output HDMI_TX_PCLK,
output HDMI_TX_DCLK,
output HDMI_TX_SCK,
output HDMI_TX_WS,
output HDMI_TX_MCLK,
output [3:0] HDMI_TX_I2S,
output HDMI_TX_DE,
output HDMI_TX_VS,
output HDMI_TX_HS,
output HDMI_TX_SPDIF,
inout HDMI_TX_CEC,
`endif
// GPIO port 0
input [31:0] GPIO0_D,
`ifdef ENABLE_USB
output [17:1] OTG_A,
output OTG_CS_n,
inout [31:0] OTG_D,
output OTG_DC_DACK,
input OTG_DC_DREQ,
input OTG_DC_IRQ,
output OTG_HC_DACK,
input OTG_HC_DREQ,
input OTG_HC_IRQ,
output OTG_OE_n,
output OTG_RESET_n,
output OTG_WE_n
`endif
`ifdef ENABLE_MTL
// GPIO port 1 connect to MTL capacitive touch screen
output mtl_dclk,
output [7:0] mtl_r,
output [7:0] mtl_g,
output [7:0] mtl_b,
output mtl_hsd,
output mtl_vsd,
output mtl_touch_i2cscl,
inout mtl_touch_i2csda,
input mtl_touch_int
`endif
`ifdef ENABLE_PCIE
,
//PCI Express
input PCIE_PREST_n,
input PCIE_REFCLK_p,
//input HSMA_REFCLK_p,
input [3:0] PCIE_RX_p,
input PCIE_SMBCLK,
inout PCIE_SMBDAT,
output [3:0] PCIE_TX_p,
output PCIE_WAKE_n
`endif
);
wire global_reset_n;
wire enet_reset_n;
//// Ethernet
wire enet_mdc;
wire enet_mdio_in;
wire enet_mdio_oen;
wire enet_mdio_out;
wire enet_refclk_125MHz;
wire lvds_rxp;
wire lvds_txp;
wire enet1_mdc;
wire enet1_mdio_in;
wire enet1_mdio_oen;
wire enet1_mdio_out;
wire lvds_rxp1;
wire lvds_txp1;
// Assign outputs that are not used to 0
//assign MAX_PLL_D = 3'b0;
//assign ETH_MDC[3:1] = 3'b0;
assign M1_DDR2_SA = 1'b0;
assign CSENSE_CS_n = 1'b0;
assign CSENSE_ADC_FO = 1'b0;
assign CSENSE_SCK = 1'b0;
assign CSENSE_SDI = 1'b0;
//assign GCLKOUT_FPGA = 1'b0;
assign M1_DDR2_SCL = 1'b0;
//// Ethernet
assign ETH_RST_n = rstn;
assign ETH_TX_p[3:2] = 2'b0;
assign lvds_rxp = ETH_RX_p[0];
assign ETH_TX_p[0] = lvds_txp;
assign lvds_rxp1 = ETH_RX_p[1];
assign ETH_TX_p[1] = lvds_txp1;
assign enet_mdio_in = ETH_MDIO[0];
assign enet1_mdio_in = ETH_MDIO[1];
assign ETH_MDIO[0] = (!enet_mdio_oen ? enet_mdio_out : 1'bz);
assign ETH_MDIO[1] = (!enet1_mdio_oen ? enet1_mdio_out : 1'bz);
// Allow the other two tri-state interfaces to float.
assign ETH_MDIO[2] = 1'bz;
assign ETH_MDIO[3] = 1'bz;
assign ETH_MDC[0] = enet_mdc;
assign ETH_MDC[1] = enet1_mdc;
// Set unused interface clocks to high.
assign ETH_MDC[2] = 1'b1;
assign ETH_MDC[3] = 1'b1;
wire clk100;
wire [7:0] LED_n;
assign LED = ~LED_n;
reg [31:0] LED_reg;
//assign LED = LED_reg[31:24];
always @(posedge HDMI_TX_PCLK)
begin
LED_reg <= LED_reg + 1;
end
// === Ethernet clock PLL
pll_125 pll_125_ins (
.inclk0(OSC_50_Bank2),
.c0(enet_refclk_125MHz)
);
// === System clock PLL
wire qsys_sysclk;
wire qsys_50_clk;
assign qsys_50_clk = OSC_50_Bank6;
`ifdef ENABLE_PCIE
wire clk125;
//PCI Express clock
pll_125 pll_125_pcie (
.inclk0(OSC_50_Bank2),
.c0(clk125)
);
assign reconfig_clk = OSC_50_Bank3;
wire reconfig_fromgxb;
wire reconfig_togxb;
wire reconfig_busy;
altgx_reconfig altgx_reconfig_pcie (
.reconfig_clk(reconfig_clk),
.reconfig_fromgxb(reconfig_fromgxb),
.busy(reconfig_busy),
.reconfig_togxb(reconfig_togxb)
);
`endif
wire qsys_sysreset_n;
//wire sramClk;
assign SSRAM_CLK = qsys_sysclk;
(* keep = 1 *) wire clk27;
display_pll display_pll_ins (
.inclk0(OSC_50_Bank2),
.c0(clk27)
);
// synchronize reset signal
reg rstn, rstn_metastable;
always @(posedge qsys_50_clk)
begin
rstn_metastable <= CPU_RESET_n && GPIO0_D[2];
rstn <= rstn_metastable;
end
reg rstn100, rstn100_metastable;
always @(posedge qsys_sysclk)
begin
rstn100_metastable <= CPU_RESET_n && GPIO0_D[2];
rstn100 <= rstn100_metastable;
end
(* noprune *) reg rstn27;
reg rstn27sample;
always @(posedge clk27)
begin
rstn27sample <= rstn;
rstn27 <= rstn27sample;
end
reg [7:0] SW_P;
always @(posedge qsys_50_clk) SW_P <= ~SW; // positive version of DIP switches
assign SEG1_DP = ~1'b0;
assign SEG0_DP = ~1'b0;
reg [3:0] slide_sw_metastable, slide_sw_sync;
always @(posedge qsys_50_clk)
begin
slide_sw_metastable <= SLIDE_SW;
slide_sw_sync <= slide_sw_metastable;
end
// assign PCIE_WAKE_n = 1'b0;
// assign PCIE_SMBDATA = 1'bz;
/* signals for the old Terasic resistive touch screen (currently unused)
wire [7:0] vga_R, vga_G, vga_B;
wire vga_DEN, vga_HD, vga_VD;
assign vga_DEN = 1'b0;
assign vga_HD = 1'b0;
assign vga_VD = 1'b0;
assign vga_R = 8'd0;
assign vga_G = 8'd0;
assign vga_B = 8'd0;
assign lcdtouchLTM_R = vga_R;
assign lcdtouchLTM_G = vga_G;
assign lcdtouchLTM_B = vga_B;
assign lcdtouchLTM_DEN = vga_DEN;
assign lcdtouchLTM_HD = vga_HD;
assign lcdtouchLTM_VD = vga_VD;
assign lcdtouchLTM_GREST = rstn27;
assign lcdtouchLTM_NCLK = clk27;
assign lcdtouchLTM_SCEN = 1'b1;
assign lcdtouchLTM_ADC_DCLK = 1'b1;
assign lcdtouchLTM_ADC_DIN = 1'b1;*/
// clock for multitouch screen
assign mtl_dclk = clk27;
(* keep = 1 *) wire ssram_data_outen;
(* keep = 1 *) wire [15:0] ssram_data_out;
// instantiate the touch screen controller provided by Terasic (encrypted block)
reg touch_ready_0;
reg [9:0] touch_x1_0, touch_x2_0;
reg [8:0] touch_y1_0, touch_y2_0;
reg [1:0] touch_count_0;
reg [7:0] touch_gesture_0;
reg touch_ready_1;
reg [9:0] touch_x1_1, touch_x2_1;
reg [8:0] touch_y1_1, touch_y2_1;
reg [1:0] touch_count_1;
reg [7:0] touch_gesture_1;
wire touch_ready_2;
wire [9:0] touch_x1_2, touch_x2_2;
wire [8:0] touch_y1_2, touch_y2_2;
wire [1:0] touch_count_2;
wire [7:0] touch_gesture_2;
// i2c_touch_config touch(
// .iCLK(qsys_50_clk),
// .iRSTN(rstn),
// .iTRIG(!mtl_touch_int), // note that this signal is inverted
// .oREADY(touch_ready_2),
// .oREG_X1(touch_x1_2),
// .oREG_Y1(touch_y1_2),
// .oREG_X2(touch_x2_2),
// .oREG_Y2(touch_y2_2),
// .oREG_TOUCH_COUNT(touch_count_2),
// .oREG_GESTURE(touch_gesture_2),
// .I2C_SCLK(mtl_touch_i2cscl),
// .I2C_SDAT(mtl_touch_i2csda));
// synchronize signals to qsys system clock
always @(posedge qsys_sysclk)
begin
touch_ready_1 <= touch_ready_2;
touch_x1_1 <= touch_x1_2;
touch_y1_1 <= touch_y1_2;
touch_x2_1 <= touch_x2_2;
touch_y2_1 <= touch_y2_2;
touch_count_1 <= touch_count_2;
touch_gesture_1 <= touch_gesture_2;
touch_ready_0 <= touch_ready_1;
touch_x1_0 <= touch_x1_1;
touch_y1_0 <= touch_y1_1;
touch_x2_0 <= touch_x2_1;
touch_y2_0 <= touch_y2_1;
touch_count_0 <= touch_count_1;
touch_gesture_0 <= touch_gesture_1;
end
// touch screen controller end
wire i2c_scl_oe_n;
wire i2c_scl_o;
wire i2c_scl_i = HDMI_TX_PCSCL;
wire i2c_sda_oe_n;
wire i2c_sda_o;
wire i2c_sda_i = HDMI_TX_PCSDA;
// tristate buffers
assign HDMI_TX_PCSCL = i2c_scl_oe_n==1'b0 ? i2c_scl_o : 1'bz;
assign HDMI_TX_PCSDA = i2c_sda_oe_n==1'b0 ? i2c_sda_o : 1'bz;
//wire gen_sck;
//wire gen_i2s;
//wire gen_ws;
assign HDMI_TX_SCK = 1'b0;
assign HDMI_TX_I2S = 4'b0;//{gen_i2s, gen_i2s, gen_i2s, gen_i2s};
assign HDMI_TX_WS = 1'b0;//gen_ws;
wire [31:0] otg_dout;
assign OTG_D = (!OTG_CS_n & OTG_OE_n) ? otg_dout : 32'hzzzzzzzz;
wire [16:0] otg_a_temp;
assign OTG_A[17:1] = otg_a_temp[16:0];
DE4_SOC DE4_SOC_inst(
// 1) global signals:
.clk_50_clk(qsys_50_clk),
.clk_50_ddr_clk(OSC_50_Bank4),
.clk_125_clk(enet_refclk_125MHz),
.reset_reset_n(rstn),
.sysclk_clk(qsys_sysclk),
//.sysreset_reset_n(qsys_sysreset_n),
.leds_external_connection_export(LED_n),
// the_ddr2
.ddr2_global_reset_reset_n(),
.memory_mem_cke (M1_DDR2_cke), // ddr2.cke
.memory_mem_ck_n (M1_DDR2_clk_n), // .ck_n
.memory_mem_cas_n (M1_DDR2_cas_n), // .cas_n
.memory_mem_dq (M1_DDR2_dq), // .dq
.memory_mem_dqs (M1_DDR2_dqs), // .dqs
.memory_mem_odt (M1_DDR2_odt), // .odt
.memory_mem_cs_n (M1_DDR2_cs_n), // .cs_n
.memory_mem_ba (M1_DDR2_ba), // .ba
.memory_mem_dm (M1_DDR2_dm), // .dm
.memory_mem_we_n (M1_DDR2_we_n), // .we_n
.memory_mem_dqs_n (M1_DDR2_dqsn), // .dqs_n
.memory_mem_ras_n (M1_DDR2_ras_n), // .ras_n
.memory_mem_ck (M1_DDR2_clk), // .ck
.memory_mem_a (M1_DDR2_addr), // .a
.oct_rup (termination_blk0_rup_pad), // .oct_rup
.oct_rdn (termination_blk0_rdn_pad), // .oct_rdn
// ddr2 psd i2c
// .out_port_from_the_ddr2_i2c_scl(M1_DDR2_SCL),
// .out_port_from_the_ddr2_i2c_sa(M1_DDR2_SA),
// .bidir_port_to_and_from_the_ddr2_i2c_sda(M1_DDR2_SDA)
// ---------------------------------------------------------------------
// MAC (TSE) 0
.mac_mac_mdio_mdc (enet_mdc), // mac_mac_mdio.mdc
.mac_mac_mdio_mdio_in (enet_mdio_in), // .mdio_in
.mac_mac_mdio_mdio_out (enet_mdio_out), // .mdio_out
.mac_mac_mdio_mdio_oen (enet_mdio_oen), // .mdio_oen
//.mac_mac_misc_xon_gen, (/* input */) // mac_mac_misc.xon_gen
//.mac_mac_misc_xoff_gen, (/* input */) // .xoff_gen
//.mac_mac_misc_magic_wakeup, (/* output */) // .magic_wakeup
//.mac_mac_misc_magic_sleep_n, (/* input */) // .magic_sleep_n
//.mac_mac_misc_ff_tx_crc_fwd, (/* input */) // .ff_tx_crc_fwd
//.mac_mac_misc_ff_tx_septy, (/* output */) // .ff_tx_septy
//.mac_mac_misc_tx_ff_uflow, (/* output */) // .tx_ff_uflow
//.mac_mac_misc_ff_tx_a_full, (/* output */) // .ff_tx_a_full
//.mac_mac_misc_ff_tx_a_empty, (/* output */) // .ff_tx_a_empty
//.mac_mac_misc_rx_err_stat, (/* output[17:0] */) // .rx_err_stat
//.mac_mac_misc_rx_frm_type, (/* output[3:0] */) // .rx_frm_type
//.mac_mac_misc_ff_rx_dsav, (/* output */) // .ff_rx_dsav
//.mac_mac_misc_ff_rx_a_full, (/* output */) // .ff_rx_a_full
//.mac_mac_misc_ff_rx_a_empty, (/* output */) // .ff_rx_a_empty
//.mac_status_led_crs, (/* output */) // mac_status_led.crs
//.mac_status_led_link, (/* output */) // .link
//.mac_status_led_col, (/* output */) // .col
//.mac_status_led_an, (/* output */) // .an
//.mac_status_led_char_err, (/* output */) // .char_err
//.mac_status_led_disp_err, (/* output */) // .disp_err
//.mac_serdes_control_export, (/* output */) // mac_serdes_control.export
.mac_serial_txp (lvds_txp), // mac_serial.txp
.mac_serial_rxp (lvds_rxp), // .rxp
// ---------------------------------------------------------------------
// MAC (TSE) 1
.mac1_mac_mdio_mdc (enet1_mdc), // mac1_mac_mdio.mdc
.mac1_mac_mdio_mdio_in (enet1_mdio_in), // .mdio_in
.mac1_mac_mdio_mdio_out (enet1_mdio_out), // .mdio_out
.mac1_mac_mdio_mdio_oen (enet1_mdio_oen), // .mdio_oen
//.mac1_mac_misc_xon_gen, ( input ) // mac1_mac_misc.xon_gen
//.mac1_mac_misc_xoff_gen, ( input ) // .xoff_gen
//.mac1_mac_misc_magic_wakeup, ( output ) // .magic_wakeup
//.mac1_mac_misc_magic_sleep_n, ( input ) // .magic_sleep_n
//.mac1_mac_misc_ff_tx_crc_fwd, ( input ) // .ff_tx_crc_fwd
//.mac1_mac_misc_ff_tx_septy, ( output ) // .ff_tx_septy
//.mac1_mac_misc_tx_ff_uflow, ( output ) // .tx_ff_uflow
//.mac1_mac_misc_ff_tx_a_full, ( output ) // .ff_tx_a_full
//.mac1_mac_misc_ff_tx_a_empty, ( output ) // .ff_tx_a_empty
//.mac1_mac_misc_rx_err_stat, ( output[17:0] ) // .rx_err_stat
//.mac1_mac_misc_rx_frm_type, ( output[3:0] ) // .rx_frm_type
//.mac1_mac_misc_ff_rx_dsav, ( output ) // .ff_rx_dsav
//.mac1_mac_misc_ff_rx_a_full, ( output ) // .ff_rx_a_full
//.mac1_mac_misc_ff_rx_a_empty, ( output ) // .ff_rx_a_empty
//.mac1_status_led_crs, ( output ) // mac1_status_led.crs
//.mac1_status_led_link, ( output ) // .link
//.mac1_status_led_col, ( output ) // .col
//.mac1_status_led_an, ( output ) // .an
//.mac1_status_led_char_err, ( output ) // .char_err
//.mac1_status_led_disp_err, ( output ) // .disp_err
//.mac1_serdes_control_export, ( output ) // mac1_serdes_control.export
.mac1_serial_txp (lvds_txp1), // mac1_serial.txp
.mac1_serial_rxp (lvds_rxp1), // .rxp
// ---------------------------------------------------------------------/
`ifdef ENABLE_SDCARD
.sd_b_SD_cmd (SD_CMD), // sd.b_SD_cmd
.sd_b_SD_dat (SD_DAT[0]), // .b_SD_dat
.sd_b_SD_dat3 (SD_DAT[3]), // .b_SD_dat3
.sd_o_SD_clock (SD_CLK), // .o_SD_clock
`endif
`ifdef ENABLE_SSRAM
.mem_ssram_adv (SSRAM_ADV), // fbssram_1.ssram_adv
.mem_ssram_bwa_n (SSRAM_BWA_n), // .ssram_bwa_n
.mem_ssram_bwb_n (SSRAM_BWB_n), // .ssram_bwb_n
.mem_ssram_ce_n (SSRAM_CE_n), // .ssram_ce_n
.mem_ssram_cke_n (SSRAM_CKE_n), // .ssram_cke_n
.mem_ssram_oe_n (SSRAM_OE_n), // .ssram_oe_n
.mem_ssram_we_n (SSRAM_WE_n), // .ssram_we_n
.mem_fsm_a (FSM_A), // .fsm_a
.mem_fsm_d_out (ssram_data_out), // .fsm_d_out
.mem_fsm_d_in (FSM_D), // .fsm_d_in
.mem_fsm_dout_req (ssram_data_outen), // .fsm_dout_req
.mem_flash_adv_n (FLASH_ADV_n),
.mem_flash_ce_n (FLASH_CE_n),
.mem_flash_clk (FLASH_CLK),
.mem_flash_oe_n (FLASH_OE_n),
.mem_flash_we_n (FLASH_WE_n),
.touch_x1 (touch_x1_0), // .touch_x1
.touch_y1 (touch_y1_0), // .touch_y1
.touch_x2 (touch_x2_0), // .touch_x2
.touch_y2 (touch_y2_0), // .touch_y2
.touch_count_gesture ({touch_count_0,touch_gesture_0}), // .touch_count_gesture
.touch_touch_valid (touch_ready_0), // .touch_touch_valid
// .sram_clk_clk (SSRAM_CLK)
// .display_clk_clk (clk27),
/*.coe_hdmi_r(HDMI_TX_RD),
.coe_hdmi_g(HDMI_TX_GD),
.coe_hdmi_b(HDMI_TX_BD),
.coe_hdmi_hsd(HDMI_TX_HS),
.coe_hdmi_vsd(HDMI_TX_VS),
.coe_hdmi_de(HDMI_TX_DE),*/
.coe_tpadlcd_mtl_r(mtl_r),
.coe_tpadlcd_mtl_g(mtl_g),
.coe_tpadlcd_mtl_b(mtl_b),
.coe_tpadlcd_mtl_hsd(mtl_hsd),
.coe_tpadlcd_mtl_vsd(mtl_vsd),
.clk_27_clk (clk27),
.coe_i2c_scl_i (i2c_scl_i),
.coe_i2c_scl_o (i2c_scl_o),
.coe_i2c_scl_oe_n (i2c_scl_oe_n),
.coe_i2c_sda_i (i2c_sda_i),
.coe_i2c_sda_o (i2c_sda_o),
.coe_i2c_sda_oe_n (i2c_sda_oe_n),
.hdmi_tx_reset_n_external_connection_export (HDMI_TX_RST_N),
// .i2s_tx_conduit_end_sck (gen_sck), // i2s_tx_conduit_end.sck
// .i2s_tx_conduit_end_ws (gen_ws), // .ws
// .i2s_tx_conduit_end_sd (gen_i2s),
`endif
.usb_coe_cs_n (OTG_CS_n), // usb.coe_cs_n
.usb_coe_rd_n (OTG_OE_n), // .coe_rd_n
.usb_coe_din (OTG_D), // .coe_din
.usb_coe_dout (otg_dout), // .coe_dout
.usb_coe_a (otg_a_temp), // .coe_a
.usb_coe_dc_irq_in (OTG_DC_IRQ), // .coe_dc_irq_in
.usb_coe_hc_irq_in (OTG_HC_IRQ), // .coe_hc_irq_in
//.usb_coe_dc_dreq_in (OTG_DC_DREQ), // .coe_dc_dreq_in
//.usb_coe_hc_dreq_in (OTG_HC_DREQ), // .coe_hc_dreq_in
//.usb_coe_dc_dack (OTG_DC_DACK), // .coe_dc_dack
//.usb_coe_hc_dack (OTG_HC_DACK), // .coe_hc_dack
.usb_coe_wr_n (OTG_WE_n), // .coe_wr_n
.fan_fan_on_pwm (FAN_CTRL), //
.fan_temp_lower_seg_n (SEG0_D), // .temp_lower_seg_n
.fan_temp_upper_seg_n (SEG1_D), // .temp_upper_seg_n.
.switches_export ({SLIDE_SW[3:0], BUTTON[3:0], SW_P[7:0]}),
`ifdef ENABLE_UART
.rs232_stx_pad_o (UART_TXD), // rs232.stx_pad_o
.rs232_srx_pad_i (UART_RXD), // .srx_pad_i
.rs232_rts_pad_o (UART_RTS), // .rts_pad_o
.rs232_cts_pad_i (UART_CTS), // .cts_pad_i
.rs232_dtr_pad_o (), // .dtr_pad_o
// I have no idea what these should be by default. Should see Simon's example project.
.rs232_dsr_pad_i (1'b1), // .dsr_pad_i
.rs232_ri_pad_i (1'b1), // .ri_pad_i
.rs232_dcd_pad_i (1'b1), // .dcd_pad_i
`endif
`ifdef ENABLE_HDMI
.hdmi_vid_clock_clk (HDMI_TX_PCLK), // hdmi_vid_clock.clk
.hdmi_ref_clock_clk (OSC_50_Bank5), // hdmi_ref_clock.clk
.hdmi_r (HDMI_TX_RD), // hdmi.r
.hdmi_g (HDMI_TX_GD), // .g
.hdmi_b (HDMI_TX_BD), // .b
.hdmi_hsd (HDMI_TX_HS), // .hsd
.hdmi_vsd (HDMI_TX_VS), // .vsd
.hdmi_de (HDMI_TX_DE)
`endif
`ifdef ENABLE_PCIE
,
.pciexpressstream_0_refclk_export (PCIE_REFCLK_p),
.pciexpressstream_0_fixedclk_clk (clk125),
.pciexpressstream_0_cal_blk_clk_clk (reconfig_clk),
.pciexpressstream_0_reconfig_gxbclk_clk (reconfig_clk),
.pciexpressstream_0_reconfig_togxb_data (reconfig_togxb),
.pciexpressstream_0_reconfig_fromgxb_0_data (reconfig_fromgxb),
.pciexpressstream_0_reconfig_busy_busy_altgxb_reconfig (reconfig_busy),
.pciexpressstream_0_pcie_rstn_export (PCIE_PREST_n),
.pciexpressstream_0_rx_in_rx_datain_0 (PCIE_RX_p[0]),
.pciexpressstream_0_rx_in_rx_datain_1 (PCIE_RX_p[1]),
.pciexpressstream_0_rx_in_rx_datain_2 (PCIE_RX_p[2]),
.pciexpressstream_0_rx_in_rx_datain_3 (PCIE_RX_p[3]),
.pciexpressstream_0_tx_out_tx_dataout_0 (PCIE_TX_p[0]),
.pciexpressstream_0_tx_out_tx_dataout_1 (PCIE_TX_p[1]),
.pciexpressstream_0_tx_out_tx_dataout_2 (PCIE_TX_p[2]),
.pciexpressstream_0_tx_out_tx_dataout_3 (PCIE_TX_p[3])
`endif
);
// handle USB (OTG) reset signal
assign OTG_RESET_n = rstn100;
// handle unused flash reset signal
assign FLASH_RESET_n = rstn100;
// handle tristate ssram data bus
assign FSM_D = ssram_data_outen ? ssram_data_out : 16'bzzzzzzzzzzzzzzzz;
endmodule |
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
iic_scl,
iic_sda,
rx_ref_clk_p,
rx_ref_clk_n,
rx_sysref_p,
rx_sysref_n,
rx_sync_p,
rx_sync_n,
rx_data_p,
rx_data_n,
adc_oen,
adc_sela,
adc_selb,
adc_s0,
adc_s1,
adc_resetb,
adc_agc1,
adc_agc2,
adc_agc3,
adc_agc4,
spi_csn,
spi_clk,
spi_mosi,
spi_miso);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [14:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [23:0] hdmi_data;
output spdif;
inout iic_scl;
inout iic_sda;
input rx_ref_clk_p;
input rx_ref_clk_n;
output rx_sysref_p;
output rx_sysref_n;
output rx_sync_p;
output rx_sync_n;
input [ 1:0] rx_data_p;
input [ 1:0] rx_data_n;
inout adc_oen;
inout adc_sela;
inout adc_selb;
inout adc_s0;
inout adc_s1;
inout adc_resetb;
inout adc_agc1;
inout adc_agc2;
inout adc_agc3;
inout adc_agc4;
output spi_csn;
output spi_clk;
output spi_mosi;
input spi_miso;
// internal registers
reg adc_dwr = 'd0;
reg [63:0] adc_ddata = 'd0;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 2:0] spi0_csn;
wire spi0_clk;
wire spi0_mosi;
wire spi0_miso;
wire [ 2:0] spi1_csn;
wire spi1_clk;
wire spi1_mosi;
wire spi1_miso;
wire rx_ref_clk;
wire rx_sysref;
wire rx_sync;
wire adc_clk;
wire adc_enable_a;
wire [31:0] adc_data_a;
wire adc_enable_b;
wire [31:0] adc_data_b;
// pack & unpack here
always @(posedge adc_clk) begin
case ({adc_enable_b, adc_enable_a})
2'b11: begin
adc_dwr <= 1'b1;
adc_ddata[63:48] <= adc_data_b[31:16];
adc_ddata[47:32] <= adc_data_a[31:16];
adc_ddata[31:16] <= adc_data_b[15: 0];
adc_ddata[15: 0] <= adc_data_a[15: 0];
end
2'b10: begin
adc_dwr <= ~adc_dwr;
adc_ddata[63:48] <= adc_data_b[31:16];
adc_ddata[47:32] <= adc_data_b[15: 0];
adc_ddata[31:16] <= adc_ddata[63:48];
adc_ddata[15: 0] <= adc_ddata[47:32];
end
2'b01: begin
adc_dwr <= ~adc_dwr;
adc_ddata[63:48] <= adc_data_a[31:16];
adc_ddata[47:32] <= adc_data_a[15: 0];
adc_ddata[31:16] <= adc_ddata[63:48];
adc_ddata[15: 0] <= adc_ddata[47:32];
end
default: begin
adc_dwr <= 1'b0;
adc_ddata[63:48] <= 16'd0;
adc_ddata[47:32] <= 16'd0;
adc_ddata[31:16] <= 16'd0;
adc_ddata[15: 0] <= 16'd0;
end
endcase
end
// instantiations
IBUFDS_GTE2 i_ibufds_rx_ref_clk (
.CEB (1'd0),
.I (rx_ref_clk_p),
.IB (rx_ref_clk_n),
.O (rx_ref_clk),
.ODIV2 ());
OBUFDS i_obufds_rx_sysref (
.I (rx_sysref),
.O (rx_sysref_p),
.OB (rx_sysref_n));
OBUFDS i_obufds_rx_sync (
.I (rx_sync),
.O (rx_sync_p),
.OB (rx_sync_n));
assign spi_csn = spi0_csn[0];
assign spi_clk = spi0_clk;
assign spi_mosi = spi0_mosi;
assign spi0_miso = spi_miso;
ad_iobuf #(.DATA_WIDTH(10)) i_iobuf (
.dio_t (gpio_t[41:32]),
.dio_i (gpio_o[41:32]),
.dio_o (gpio_i[41:32]),
.dio_p ({ adc_oen,
adc_sela,
adc_selb,
adc_s0,
adc_s1,
adc_resetb,
adc_agc1,
adc_agc2,
adc_agc3,
adc_agc4}));
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
.dio_t (gpio_t[14:0]),
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),
.dio_p (gpio_bd));
system_wrapper i_system_wrapper (
.adc_clk (adc_clk),
.adc_data_a (adc_data_a),
.adc_data_b (adc_data_b),
.adc_ddata (adc_ddata),
.adc_dsync (1'b1),
.adc_dwr (adc_dwr),
.adc_enable_a (adc_enable_a),
.adc_enable_b (adc_enable_b),
.adc_valid_a (),
.adc_valid_b (),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.ps_intr_12 (1'b0),
.rx_data_n (rx_data_n),
.rx_data_p (rx_data_p),
.rx_ref_clk (rx_ref_clk),
.rx_sync (rx_sync),
.rx_sysref (rx_sysref),
.spdif (spdif),
.spi0_clk_i (spi0_clk),
.spi0_clk_o (spi0_clk),
.spi0_csn_0_o (spi0_csn[0]),
.spi0_csn_1_o (spi0_csn[1]),
.spi0_csn_2_o (spi0_csn[2]),
.spi0_csn_i (1'b1),
.spi0_sdi_i (spi0_miso),
.spi0_sdo_i (spi0_mosi),
.spi0_sdo_o (spi0_mosi),
.spi1_clk_i (spi1_clk),
.spi1_clk_o (spi1_clk),
.spi1_csn_0_o (spi1_csn[0]),
.spi1_csn_1_o (spi1_csn[1]),
.spi1_csn_2_o (spi1_csn[2]),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b1),
.spi1_sdo_i (spi1_mosi),
.spi1_sdo_o (spi1_mosi));
endmodule |
module tcp_ip_wrapper (
input aclk,
input aresetn,
input[47:0] myMacAddress,
input[31:0] inputIpAddress,
input dhcpEnable,
output[31:0] ipAddressout,
output[15:0] regSessionCount,
output[15:0] relSessionCount,
// Debug signals for the session lookup //
output upd_req_TVALID_out,
output upd_req_TREADY_out,
output upd_req_TDATA_out,
output upd_rsp_TVALID_out,
output upd_rsp_TREADY_out,
// network interface streams
output AXI_M_Stream_TVALID,
input AXI_M_Stream_TREADY,
output[63:0] AXI_M_Stream_TDATA,
output[7:0] AXI_M_Stream_TKEEP,
output AXI_M_Stream_TLAST,
input AXI_S_Stream_TVALID,
output AXI_S_Stream_TREADY,
input[63:0] AXI_S_Stream_TDATA,
input[7:0] AXI_S_Stream_TKEEP,
input AXI_S_Stream_TLAST,
// Debug streams
output[7:0] axi_debug1_tkeep,
output[63:0] axi_debug1_tdata,
output axi_debug1_tvalid,
output axi_debug1_tready,
output axi_debug1_tlast,
output[7:0] axi_debug2_tkeep,
output[63:0] axi_debug2_tdata,
output axi_debug2_tvalid,
output axi_debug2_tready,
output axi_debug2_tlast,
// memory rx cmd streams
output m_axis_rxread_cmd_TVALID,
input m_axis_rxread_cmd_TREADY,
output[71:0] m_axis_rxread_cmd_TDATA,
output m_axis_rxwrite_cmd_TVALID,
input m_axis_rxwrite_cmd_TREADY,
output[71:0] m_axis_rxwrite_cmd_TDATA,
// memory rx sts streams
//input s_axis_rxread_sts_TVALID,
//output s_axis_rxread_sts_TREADY,
//input[7:0] s_axis_rxread_sts_TDATA,
input s_axis_rxwrite_sts_TVALID,
output s_axis_rxwrite_sts_TREADY,
input[7:0] s_axis_rxwrite_sts_TDATA,
// memory rx data streams - Read status signals are not used
input s_axis_rxread_data_TVALID,
output s_axis_rxread_data_TREADY,
input[63:0] s_axis_rxread_data_TDATA,
input[7:0] s_axis_rxread_data_TKEEP,
input s_axis_rxread_data_TLAST,
output m_axis_rxwrite_data_TVALID,
input m_axis_rxwrite_data_TREADY,
output[63:0] m_axis_rxwrite_data_TDATA,
output[7:0] m_axis_rxwrite_data_TKEEP,
output m_axis_rxwrite_data_TLAST,
// memory tx cmd streams
output m_axis_txread_cmd_TVALID,
input m_axis_txread_cmd_TREADY,
output[71:0] m_axis_txread_cmd_TDATA,
output m_axis_txwrite_cmd_TVALID,
input m_axis_txwrite_cmd_TREADY,
output[71:0] m_axis_txwrite_cmd_TDATA,
// memory tx sts streams - Read status signals are not used
//input s_axis_txread_sts_TVALID,
//output s_axis_txread_sts_TREADY,
//input[7:0] s_axis_txread_sts_TDATA,
input s_axis_txwrite_sts_TVALID,
output s_axis_txwrite_sts_TREADY,
input[7:0] s_axis_txwrite_sts_TDATA,
// memory tx data streams
input s_axis_txread_data_TVALID,
output s_axis_txread_data_TREADY,
input[63:0] s_axis_txread_data_TDATA,
input[7:0] s_axis_txread_data_TKEEP,
input s_axis_txread_data_TLAST,
output m_axis_txwrite_data_TVALID,
input m_axis_txwrite_data_TREADY,
output[63:0] m_axis_txwrite_data_TDATA,
output[7:0] m_axis_txwrite_data_TKEEP,
output m_axis_txwrite_data_TLAST,
//application interface streams
output m_axis_listen_port_status_TVALID,
input m_axis_listen_port_status_TREADY,
output[7:0] m_axis_listen_port_status_TDATA,
output m_axis_notifications_TVALID,
input m_axis_notifications_TREADY,
output[87:0] m_axis_notifications_TDATA,
output m_axis_open_status_TVALID,
input m_axis_open_status_TREADY,
output[23:0] m_axis_open_status_TDATA,
output m_axis_rx_data_TVALID,
input m_axis_rx_data_TREADY,
output[63:0] m_axis_rx_data_TDATA,
output[7:0] m_axis_rx_data_TKEEP,
output m_axis_rx_data_TLAST,
output m_axis_rx_metadata_TVALID,
input m_axis_rx_metadata_TREADY,
output[15:0] m_axis_rx_metadata_TDATA,
output m_axis_tx_status_TVALID,
input m_axis_tx_status_TREADY,
output[23:0] m_axis_tx_status_TDATA,
input s_axis_listen_port_TVALID,
output s_axis_listen_port_TREADY,
input[15:0] s_axis_listen_port_TDATA,
//input s_axis_close_port_TVALID,
//output s_axis_close_port_TREADY,
//input[15:0] s_axis_close_port_TDATA,
input s_axis_close_connection_TVALID,
output s_axis_close_connection_TREADY,
input[15:0] s_axis_close_connection_TDATA,
input s_axis_open_connection_TVALID,
output s_axis_open_connection_TREADY,
input[47:0] s_axis_open_connection_TDATA,
input s_axis_read_package_TVALID,
output s_axis_read_package_TREADY,
input[31:0] s_axis_read_package_TDATA,
input s_axis_tx_data_TVALID,
output s_axis_tx_data_TREADY,
input[63:0] s_axis_tx_data_TDATA,
input[7:0] s_axis_tx_data_TKEEP,
input s_axis_tx_data_TLAST,
input s_axis_tx_metadata_TVALID,
output s_axis_tx_metadata_TREADY,
input[15:0] s_axis_tx_metadata_TDATA, //change to 15?
// Session Counter Output //
output[15:0] regSessionCount_V,
output regSessionCount_V_ap_vld,
// UDP App Mux to UDP Loopback signals //
output lbPortOpenReplyIn_TVALID, // output wire portOpenReplyIn_TVALID
input lbPortOpenReplyIn_TREADY, // input wire portOpenReplyIn_TREADY
output[7:0] lbPortOpenReplyIn_TDATA, // output wire [7 : 0] portOpenReplyIn_TDATA
input lbRequestPortOpenOut_TVALID, // input wire requestPortOpenOut_TVALID
output lbRequestPortOpenOut_TREADY, // output wire requestPortOpenOut_TREADY
input[15:0] lbRequestPortOpenOut_TDATA, // input wire [15 : 0] requestPortOpenOut_TDATA
output lbRxDataIn_TVALID, // output wire rxDataIn_TVALID
input lbRxDataIn_TREADY, // input wire rxDataIn_TREADY
output[63:0] lbRxDataIn_TDATA, // output wire [63 : 0] rxDataIn_TDATA
output[7:0] lbRxDataIn_TKEEP, // output wire [7 : 0] rxDataIn_TKEEP
output lbRxDataIn_TLAST, // output wire [0 : 0] rxDataIn_TLAST
output lbRxMetadataIn_TVALID, // output wire rxMetadataIn_TVALID
input lbRxMetadataIn_TREADY, // input wire rxMetadataIn_TREADY
output[95:0] lbRxMetadataIn_TDATA, // output wire [95 : 0] rxMetadataIn_TDATA
input lbTxDataOut_TVALID, // input wire txDataOut_TVALID
output lbTxDataOut_TREADY, // output wire txDataOut_TREADY
input[63:0] lbTxDataOut_TDATA, // input wire [63 : 0] txDataOut_TDATA
input[7:0] lbTxDataOut_TKEEP, // input wire [7 : 0] txDataOut_TKEEP
input lbTxDataOut_TLAST, // input wire [0 : 0] txDataOut_TLAST
input lbTxLengthOut_TVALID, // input wire txLengthOut_TVALID
output lbTxLengthOut_TREADY, // output wire txLengthOut_TREADY
input[15:0] lbTxLengthOut_TDATA, // input wire [15 : 0] txLengthOut_TDATA
input lbTxMetadataOut_TVALID, // input wire txMetadataOut_TVALID
output lbTxMetadataOut_TREADY, // output wire txMetadataOut_TREADY
input[95:0] lbTxMetadataOut_TDATA, // input wire [95 : 0] txMetadataOut_TDATA
// Debug signals //
output[99:0] metadataFifo_din, // [99:0]
output metadataFifo_full,
output metadataFifo_write,
output[15:0] metadataHandlerFifo_din, // [15:0]
output metadataHandlerFifo_full,
output metadataHandlerFifo_write
////////////////////
);
// IP Handler Outputs
wire axi_iph_to_arp_slice_tvalid;
wire axi_iph_to_arp_slice_tready;
wire[63:0] axi_iph_to_arp_slice_tdata;
wire[7:0] axi_iph_to_arp_slice_tkeep;
wire axi_iph_to_arp_slice_tlast;
wire axi_iph_to_icmp_slice_tvalid;
wire axi_iph_to_icmp_slice_tready;
wire[63:0] axi_iph_to_icmp_slice_tdata;
wire[7:0] axi_iph_to_icmp_slice_tkeep;
wire axi_iph_to_icmp_slice_tlast;
//Slice connections on RX path
wire axi_arp_slice_to_arp_tvalid;
wire axi_arp_slice_to_arp_tready;
wire[63:0] axi_arp_slice_to_arp_tdata;
wire[7:0] axi_arp_slice_to_arp_tkeep;
wire axi_arp_slice_to_arp_tlast;
wire axi_icmp_slice_to_icmp_tvalid;
wire axi_icmp_slice_to_icmp_tready;
wire[63:0] axi_icmp_slice_to_icmp_tdata;
wire[7:0] axi_icmp_slice_to_icmp_tkeep;
wire axi_icmp_slice_to_icmp_tlast;
wire axi_iph_to_toe_tvalid;
wire axi_iph_to_toe_tready;
wire[63:0] axi_iph_to_toe_tdata;
wire[7:0] axi_iph_to_toe_tkeep;
wire axi_iph_to_toe_tlast;
// MAC-IP Encode Inputs
wire axi_intercon_to_mie_tvalid;
wire axi_intercon_to_mie_tready;
wire[63:0] axi_intercon_to_mie_tdata;
wire[7:0] axi_intercon_to_mie_tkeep;
wire axi_intercon_to_mie_tlast;
wire axi_mie_to_intercon_tvalid;
wire axi_mie_to_intercon_tready;
wire[63:0] axi_mie_to_intercon_tdata;
wire[7:0] axi_mie_to_intercon_tkeep;
wire axi_mie_to_intercon_tlast;
//Slice connections on RX path
wire axi_arp_to_arp_slice_tvalid;
wire axi_arp_to_arp_slice_tready;
wire[63:0] axi_arp_to_arp_slice_tdata;
wire[7:0] axi_arp_to_arp_slice_tkeep;
wire axi_arp_to_arp_slice_tlast;
wire axi_icmp_to_icmp_slice_tvalid;
wire axi_icmp_to_icmp_slice_tready;
wire[63:0] axi_icmp_to_icmp_slice_tdata;
wire[7:0] axi_icmp_to_icmp_slice_tkeep;
wire axi_icmp_to_icmp_slice_tlast;
wire axi_udp_to_merge_tvalid;
wire axi_udp_to_merge_tready;
wire[63:0] axi_udp_to_merge_tdata;
wire[7:0] axi_udp_to_merge_tkeep;
wire axi_udp_to_merge_tlast;
wire axi_iph_to_udp_tvalid;
wire axi_iph_to_udp_tready;
wire[63:0] axi_iph_to_udp_tdata;
wire[7:0] axi_iph_to_udp_tkeep;
wire axi_iph_to_udp_tlast;
wire axis_udp_to_icmp_tready;
wire axis_udp_to_icmp_tvalid;
wire[63:0] axis_udp_to_icmp_tdata;
wire[7:0] axis_udp_to_icmp_tkeep;
wire axis_udp_to_icmp_tlast;
wire axis_ttl_to_icmp_tready;
wire axis_ttl_to_icmp_tvalid;
wire[63:0] axis_ttl_to_icmp_tdata;
wire[7:0] axis_ttl_to_icmp_tkeep;
wire axis_ttl_to_icmp_tlast;
/// TOE Outputs ///
wire axi_toe_to_toe_slice_tvalid; // output AXI_M_Stream_TVALID
wire axi_toe_to_toe_slice_tready; // input AXI_M_Stream_TREADY
wire[63:0] axi_toe_to_toe_slice_tdata; // output [63 : 0] AXI_M_Stream_TDATA
wire[7:0] axi_toe_to_toe_slice_tkeep; // output [7 : 0] AXI_M_Stream_TSTRB
wire axi_toe_to_toe_slice_tlast; // output [0 : 0] AXI_M_Stream_TLAST
/// UDP-to-App Mux Signals ///
wire udp2muxRxDataIn_TVALID;
wire udp2muxRxDataIn_TREADY;
wire[63:0] udp2muxRxDataIn_TDATA;
wire udp2muxRxDataIn_TLAST;
wire[7:0] udp2muxRxDataIn_TKEEP;
wire mux2dhcpRxDataIn_TVALID;
wire mux2dhcpRxDataIn_TREADY;
wire[63:0] mux2dhcpRxDataIn_TDATA;
wire mux2dhcpRxDataIn_TLAST;
wire[7:0] mux2dhcpRxDataIn_TKEEP;
/// Rx Side Metadata
wire udp2muxRxMetadataIn_V_TVALID;
wire udp2muxRxMetadataIn_V_TREADY;
wire[95:0] udp2muxRxMetadataIn_V_TDATA;
wire mux2dhcpRxMetadataIn_V_TVALID;
wire mux2dhcpRxMetadataIn_V_TREADY;
wire[95:0] mux2dhcpRxMetadataIn_V_TDATA;
/// Signals for opening ports ///
wire mux2udp_requestPortOpenOut_V_TVALID;
wire mux2udp_requestPortOpenOut_V_TREADY;
wire[15:0] mux2udp_requestPortOpenOut_V_TDATA; // OK
wire udp2mux_portOpenReplyIn_V_V_TVALID;
wire udp2mux_portOpenReplyIn_V_V_TREADY;
wire[7:0] udp2mux_portOpenReplyIn_V_V_TDATA; // OK
wire dhcp2mux_requestPortOpenOut_V_TVALID;
wire dhcp2mux_requestPortOpenOut_V_TREADY;
wire[15:0] dhcp2mux_requestPortOpenOut_V_TDATA;
wire mux2dhcp_portOpenReplyIn_V_V_TVALID;
wire mux2dhcp_portOpenReplyIn_V_V_TREADY;
wire[7:0] mux2dhcp_portOpenReplyIn_V_V_TDATA;
wire mcd_to_shim_TVALID;
wire mcd_to_shim_TREADY;
wire[63:0] mcd_to_shim_TDATA;
wire[7:0] mcd_to_shim_TKEEP;
wire mcd_to_shim_TLAST;
wire[111:0] mcd_to_shim_TUSER;
/// Signals for connecting the data i/o's to the mux
wire dhcp2mux_TVALID;
wire dhcp2mux_TREADY;
wire[63:0] dhcp2mux_TDATA;
wire[7:0] dhcp2mux_TKEEP;
wire dhcp2mux_TLAST;
wire mux2udp_TVALID;
wire mux2udp_TREADY;
wire[63:0] mux2udp_TDATA;
wire[7:0] mux2udp_TKEEP;
wire mux2udp_TLAST;
//// Tx Side Metadata
wire mux2udpTxMetadataOut_V_TVALID;
wire mux2udpTxMetadataOut_V_TREADY;
wire[95:0] mux2udpTxMetadataOut_V_TDATA;
wire dhcp2muxTxMetadataOut_V_TVALID;
wire dhcp2muxTxMetadataOut_V_TREADY;
wire[95:0] dhcp2muxTxMetadataOut_V_TDATA;
/// Tx Side Packet Length
wire mux2udpTxLengthOut_V_V_TVALID;
wire mux2udpTxLengthOut_V_V_TREADY;
wire[15:0] mux2udpTxLengthOut_V_V_TDATA;
wire dhcp2muxTxLengthOut_V_V_TVALID;
wire dhcp2muxTxLengthOut_V_V_TREADY;
wire[15:0] dhcp2muxTxLengthOut_V_V_TDATA;
// TCP Offload SmartCAM signals //
wire upd_req_TVALID;
wire upd_req_TREADY;
wire[111:0] upd_req_TDATA; //(1 + 1 + 14 + 96) - 1 = 111
wire upd_rsp_TVALID;
wire upd_rsp_TREADY;
wire[15:0] upd_rsp_TDATA;
wire ins_req_TVALID;
wire ins_req_TREADY;
wire[111:0] ins_req_TDATA;
wire del_req_TVALID;
wire del_req_TREADY;
wire[111:0] del_req_TDATA;
wire lup_req_TVALID;
wire lup_req_TREADY;
wire[97:0] lup_req_TDATA; //should be 96, also wrong in SmartCam
wire lup_rsp_TVALID;
wire lup_rsp_TREADY;
wire[15:0] lup_rsp_TDATA;
// DHCP Client IP address output //
wire[31:0] dhcpAddressOut;
// because read status is not used
assign axis_rxread_sts_TREADY = 1'b1;
assign axis_txread_sts_TREADY = 1'b1;
toe_ip toe_inst (
// Data output
.m_axis_tcp_data_TVALID(axi_toe_to_toe_slice_tvalid), // output AXI_M_Stream_TVALID
.m_axis_tcp_data_TREADY(axi_toe_to_toe_slice_tready), // input AXI_M_Stream_TREADY
.m_axis_tcp_data_TDATA(axi_toe_to_toe_slice_tdata), // output [63 : 0] AXI_M_Stream_TDATA
.m_axis_tcp_data_TKEEP(axi_toe_to_toe_slice_tkeep), // output [7 : 0] AXI_M_Stream_TSTRB
.m_axis_tcp_data_TLAST(axi_toe_to_toe_slice_tlast), // output [0 : 0] AXI_M_Stream_TLAST
// Data input
.s_axis_tcp_data_TVALID(axi_iph_to_toe_tvalid), // input AXI_S_Stream_TVALID
.s_axis_tcp_data_TREADY(axi_iph_to_toe_tready), // output AXI_S_Stream_TREADY
.s_axis_tcp_data_TDATA(axi_iph_to_toe_tdata), // input [63 : 0] AXI_S_Stream_TDATA
.s_axis_tcp_data_TKEEP(axi_iph_to_toe_tkeep), // input [7 : 0] AXI_S_Stream_TKEEP
.s_axis_tcp_data_TLAST(axi_iph_to_toe_tlast), // input [0 : 0] AXI_S_Stream_TLAST
// rx read commands
.m_axis_rxread_cmd_TVALID(m_axis_rxread_cmd_TVALID),
.m_axis_rxread_cmd_TREADY(m_axis_rxread_cmd_TREADY),
.m_axis_rxread_cmd_TDATA(m_axis_rxread_cmd_TDATA),
// rx write commands
.m_axis_rxwrite_cmd_TVALID(m_axis_rxwrite_cmd_TVALID),
.m_axis_rxwrite_cmd_TREADY(m_axis_rxwrite_cmd_TREADY),
.m_axis_rxwrite_cmd_TDATA(m_axis_rxwrite_cmd_TDATA),
// rx write status
.s_axis_rxwrite_sts_TVALID(s_axis_rxwrite_sts_TVALID),
.s_axis_rxwrite_sts_TREADY(s_axis_rxwrite_sts_TREADY),
.s_axis_rxwrite_sts_TDATA(s_axis_rxwrite_sts_TDATA),
// rx buffer read path
.s_axis_rxread_data_TVALID(s_axis_rxread_data_TVALID),
.s_axis_rxread_data_TREADY(s_axis_rxread_data_TREADY),
.s_axis_rxread_data_TDATA(s_axis_rxread_data_TDATA),
.s_axis_rxread_data_TKEEP(s_axis_rxread_data_TKEEP),
.s_axis_rxread_data_TLAST(s_axis_rxread_data_TLAST),
// rx buffer write path
.m_axis_rxwrite_data_TVALID(m_axis_rxwrite_data_TVALID),
.m_axis_rxwrite_data_TREADY(m_axis_rxwrite_data_TREADY),
.m_axis_rxwrite_data_TDATA(m_axis_rxwrite_data_TDATA),
.m_axis_rxwrite_data_TKEEP(m_axis_rxwrite_data_TKEEP),
.m_axis_rxwrite_data_TLAST(m_axis_rxwrite_data_TLAST),
// tx read commands
.m_axis_txread_cmd_TVALID(m_axis_txread_cmd_TVALID),
.m_axis_txread_cmd_TREADY(m_axis_txread_cmd_TREADY),
.m_axis_txread_cmd_TDATA(m_axis_txread_cmd_TDATA),
//tx write commands
.m_axis_txwrite_cmd_TVALID(m_axis_txwrite_cmd_TVALID),
.m_axis_txwrite_cmd_TREADY(m_axis_txwrite_cmd_TREADY),
.m_axis_txwrite_cmd_TDATA(m_axis_txwrite_cmd_TDATA),
// tx write status
.s_axis_txwrite_sts_TVALID(s_axis_txwrite_sts_TVALID),
.s_axis_txwrite_sts_TREADY(s_axis_txwrite_sts_TREADY),
.s_axis_txwrite_sts_TDATA(s_axis_txwrite_sts_TDATA),
// tx read path
.s_axis_txread_data_TVALID(s_axis_txread_data_TVALID),
.s_axis_txread_data_TREADY(s_axis_txread_data_TREADY),
.s_axis_txread_data_TDATA(s_axis_txread_data_TDATA),
.s_axis_txread_data_TKEEP(s_axis_txread_data_TKEEP),
.s_axis_txread_data_TLAST(s_axis_txread_data_TLAST),
// tx write path
.m_axis_txwrite_data_TVALID(m_axis_txwrite_data_TVALID),
.m_axis_txwrite_data_TREADY(m_axis_txwrite_data_TREADY),
.m_axis_txwrite_data_TDATA(m_axis_txwrite_data_TDATA),
.m_axis_txwrite_data_TKEEP(m_axis_txwrite_data_TKEEP),
.m_axis_txwrite_data_TLAST(m_axis_txwrite_data_TLAST),
/// SmartCAM I/F ///
.m_axis_session_upd_req_TVALID(upd_req_TVALID),
.m_axis_session_upd_req_TREADY(upd_req_TREADY),
.m_axis_session_upd_req_TDATA(upd_req_TDATA),
//.m_axis_session_del_req_TVALID(del_req_TVALID), // output m_axis_session_del_req_TVALID
//.m_axis_session_del_req_TREADY(del_req_TREADY), // input m_axis_session_del_req_TREADY
//.m_axis_session_del_req_TDATA(del_req_TDATA), // output [111 : 0] m_axis_session_del_req_TDATA
//.m_axis_session_ins_req_TVALID(ins_req_TVALID), // output m_axis_session_ins_req_TVALID
//.m_axis_session_ins_req_TREADY(ins_req_TREADY), // input m_axis_session_ins_req_TREADY
//.m_axis_session_ins_req_TDATA(ins_req_TDATA), // output [111 : 0] m_axis_session_ins_req_TDATA
.s_axis_session_upd_rsp_TVALID(upd_rsp_TVALID),
.s_axis_session_upd_rsp_TREADY(upd_rsp_TREADY),
.s_axis_session_upd_rsp_TDATA(upd_rsp_TDATA),
.m_axis_session_lup_req_TVALID(lup_req_TVALID),
.m_axis_session_lup_req_TREADY(lup_req_TREADY),
.m_axis_session_lup_req_TDATA(lup_req_TDATA),
.s_axis_session_lup_rsp_TVALID(lup_rsp_TVALID),
.s_axis_session_lup_rsp_TREADY(lup_rsp_TREADY),
.s_axis_session_lup_rsp_TDATA(lup_rsp_TDATA),
/* Application Interface */
// listen&close port
.s_axis_listen_port_req_TVALID(s_axis_listen_port_TVALID),
.s_axis_listen_port_req_TREADY(s_axis_listen_port_TREADY),
.s_axis_listen_port_req_TDATA(s_axis_listen_port_TDATA),
.m_axis_listen_port_rsp_TVALID(m_axis_listen_port_status_TVALID),
.m_axis_listen_port_rsp_TREADY(m_axis_listen_port_status_TREADY),
.m_axis_listen_port_rsp_TDATA(m_axis_listen_port_status_TDATA),
//.s_axis_close_port_TVALID(s_axis_close_port_TVALID),
//.s_axis_close_port_TREADY(s_axis_close_port_TREADY),
//.s_axis_close_port_TDATA(s_axis_close_port_TDATA),
// notification & read request
.m_axis_notification_TVALID(m_axis_notifications_TVALID),
.m_axis_notification_TREADY(m_axis_notifications_TREADY),
.m_axis_notification_TDATA(m_axis_notifications_TDATA),
.s_axis_rx_data_req_TVALID(s_axis_read_package_TVALID),
.s_axis_rx_data_req_TREADY(s_axis_read_package_TREADY),
.s_axis_rx_data_req_TDATA(s_axis_read_package_TDATA),
// open&close connection
.s_axis_open_conn_req_TVALID(s_axis_open_connection_TVALID),
.s_axis_open_conn_req_TREADY(s_axis_open_connection_TREADY),
.s_axis_open_conn_req_TDATA(s_axis_open_connection_TDATA),
.m_axis_open_conn_rsp_TVALID(m_axis_open_status_TVALID),
.m_axis_open_conn_rsp_TREADY(m_axis_open_status_TREADY),
.m_axis_open_conn_rsp_TDATA(m_axis_open_status_TDATA),
.s_axis_close_conn_req_TVALID(s_axis_close_connection_TVALID),//axis_close_connection_TVALID
.s_axis_close_conn_req_TREADY(s_axis_close_connection_TREADY),
.s_axis_close_conn_req_TDATA(s_axis_close_connection_TDATA),
// rx data
.m_axis_rx_data_rsp_metadata_TVALID(m_axis_rx_metadata_TVALID),
.m_axis_rx_data_rsp_metadata_TREADY(m_axis_rx_metadata_TREADY),
.m_axis_rx_data_rsp_metadata_TDATA(m_axis_rx_metadata_TDATA),
.m_axis_rx_data_rsp_TVALID(m_axis_rx_data_TVALID),
.m_axis_rx_data_rsp_TREADY(m_axis_rx_data_TREADY),
.m_axis_rx_data_rsp_TDATA(m_axis_rx_data_TDATA),
.m_axis_rx_data_rsp_TKEEP(m_axis_rx_data_TKEEP),
.m_axis_rx_data_rsp_TLAST(m_axis_rx_data_TLAST),
// tx data
.s_axis_tx_data_req_metadata_TVALID(s_axis_tx_metadata_TVALID),
.s_axis_tx_data_req_metadata_TREADY(s_axis_tx_metadata_TREADY),
.s_axis_tx_data_req_metadata_TDATA(s_axis_tx_metadata_TDATA),
.s_axis_tx_data_req_TVALID(s_axis_tx_data_TVALID),
.s_axis_tx_data_req_TREADY(s_axis_tx_data_TREADY),
.s_axis_tx_data_req_TDATA(s_axis_tx_data_TDATA),
.s_axis_tx_data_req_TKEEP(s_axis_tx_data_TKEEP),
.s_axis_tx_data_req_TLAST(s_axis_tx_data_TLAST),
.m_axis_tx_data_rsp_TVALID(m_axis_tx_status_TVALID),
.m_axis_tx_data_rsp_TREADY(m_axis_tx_status_TREADY),
.m_axis_tx_data_rsp_TDATA(m_axis_tx_status_TDATA),
// Debug signals //
//.rxEng2eventEng_data(rxEng2eventEng_data),
//.rxEng2eventEng_write(rxEng2eventEng_write),
//.rxEng2eventEng_full(rxEng2eventEng_full),
//.eventEng2txEng_data(eventEng2txEng_data),
//.eventEng2txEng_write(eventEng2txEng_write),
//.eventEng2txEng_full(eventEng2txEng_full),
//.metadataFifo_din(metadataFifo_din),
//.metadataFifo_full(metadataFifo_full),
//.metadataFifo_write(metadataFifo_write),
//.metadataHandlerFifo_din(metadataHandlerFifo_din),
//.metadataHandlerFifo_full(metadataHandlerFifo_full),
//.metadataHandlerFifo_write(metadataHandlerFifo_write),
////////////////////
.regIpAddress_V(32'h01010101), // input wire [31 : 0] regIpAddress_V
.relSessionCount_V(relSessionCount), // output wire [15 : 0] relSessionCount_V
.regSessionCount_V(regSessionCount), // output wire [15 : 0] regSessionCount_V
.aclk(aclk), // input aclk
.aresetn(aresetn) // input aresetn
);
SmartCamCtl SmartCamCtl_inst
(
.clk(aclk),
.rst(~aresetn),
.led0(sc_led0),
.led1(sc_led1),
.cam_ready(cam_ready),
.lup_req_valid(lup_req_TVALID),
.lup_req_ready(lup_req_TREADY),
.lup_req_din(lup_req_TDATA),
.lup_rsp_valid(lup_rsp_TVALID),
.lup_rsp_ready(lup_rsp_TREADY),
.lup_rsp_dout(lup_rsp_TDATA),
.upd_req_valid(upd_req_TVALID),
.upd_req_ready(upd_req_TREADY),
.upd_req_din(upd_req_TDATA),
.upd_rsp_valid(upd_rsp_TVALID),
.upd_rsp_ready(upd_rsp_TREADY),
.upd_rsp_dout(upd_rsp_TDATA),
.debug()
);
// UDP Offload Engine
udp_0 myUDP (
.inputPathInData_TVALID(axi_iph_to_udp_tvalid), // input wire inputPathInData_TVALID
.inputPathInData_TREADY(axi_iph_to_udp_tready), // output wire inputPathInData_TREADY
.inputPathInData_TDATA(axi_iph_to_udp_tdata), // input wire [63 : 0] inputPathInData_TDATA
.inputPathInData_TKEEP(axi_iph_to_udp_tkeep), // input wire [7 : 0] inputPathInData_TKEEP
.inputPathInData_TLAST(axi_iph_to_udp_tlast), // input wire [0 : 0] inputPathInData_TLAST
.inputpathOutData_TVALID(udp2muxRxDataIn_TVALID), // output wire inputpathOutData_V_TVALID
.inputpathOutData_TREADY(udp2muxRxDataIn_TREADY), // input wire inputpathOutData_V_TREADY
.inputpathOutData_TDATA(udp2muxRxDataIn_TDATA), // output wire [63 : 0] inputpathOutData_V_TDATA
.inputpathOutData_TKEEP(udp2muxRxDataIn_TKEEP), // output wire [7:0]
.inputpathOutData_TLAST(udp2muxRxDataIn_TLAST), // output wire
.openPort_TVALID(mux2udp_requestPortOpenOut_V_TVALID), // input wire openPort_V_TVALID
.openPort_TREADY(mux2udp_requestPortOpenOut_V_TREADY), // output wire openPort_V_TREADY
.openPort_TDATA(mux2udp_requestPortOpenOut_V_TDATA), // input wire [7 : 0] openPort_V_TDATA
.confirmPortStatus_TVALID(udp2mux_portOpenReplyIn_V_V_TVALID), // output wire confirmPortStatus_V_V_TVALID
.confirmPortStatus_TREADY(udp2mux_portOpenReplyIn_V_V_TREADY), // input wire confirmPortStatus_V_V_TREADY
.confirmPortStatus_TDATA(udp2mux_portOpenReplyIn_V_V_TDATA), // output wire [15 : 0] confirmPortStatus_V_V_TDATA
.inputPathOutputMetadata_TVALID(udp2muxRxMetadataIn_V_TVALID), // output wire inputPathOutputMetadata_V_TVALID
.inputPathOutputMetadata_TREADY(udp2muxRxMetadataIn_V_TREADY), // input wire inputPathOutputMetadata_V_TREADY
.inputPathOutputMetadata_TDATA(udp2muxRxMetadataIn_V_TDATA), // output wire [95 : 0] inputPathOutputMetadata_V_TDATA
.portRelease_TVALID(1'b0), // input wire portRelease_V_V_TVALID
.portRelease_TREADY(), // output wire portRelease_V_V_TREADY
.portRelease_TDATA(15'b0), // input wire [15 : 0] portRelease_V_V_TDATA
.outputPathInData_TVALID(mux2udp_TVALID), // input wire outputPathInData_V_TVALID
.outputPathInData_TREADY(mux2udp_TREADY), // output wire outputPathInData_V_TREADY
.outputPathInData_TDATA(mux2udp_TDATA), // input wire [71 : 0] outputPathInData_V_TDATA
.outputPathInData_TKEEP(mux2udp_TKEEP), // input wire [7 : 0] outputPathInData_TKEEP
.outputPathInData_TLAST(mux2udp_TLAST), // input wire [0 : 0] outputPathInData_TLAST
.outputPathOutData_TVALID(axi_udp_to_merge_tvalid), // output wire outputPathOutData_TVALID
.outputPathOutData_TREADY(axi_udp_to_merge_tready), // input wire outputPathOutData_TREADY
.outputPathOutData_TDATA(axi_udp_to_merge_tdata), // output wire [63 : 0] outputPathOutData_TDATA
.outputPathOutData_TKEEP(axi_udp_to_merge_tkeep), // output wire [7 : 0] outputPathOutData_TKEEP
.outputPathOutData_TLAST(axi_udp_to_merge_tlast), // output wire [0 : 0] outputPathOutData_TLAST
.outputPathInMetadata_TVALID(mux2udpTxMetadataOut_V_TVALID), // input wire outputPathInMetadata_V_TVALID
.outputPathInMetadata_TREADY(mux2udpTxMetadataOut_V_TREADY), // output wire outputPathInMetadata_V_TREADY
.outputPathInMetadata_TDATA(mux2udpTxMetadataOut_V_TDATA), // input wire [95 : 0] outputPathInMetadata_V_TDATA
.outputpathInLength_TVALID(mux2udpTxLengthOut_V_V_TVALID), // input wire outputpathInLength_V_V_TVALID
.outputpathInLength_TREADY(mux2udpTxLengthOut_V_V_TREADY), // output wire outputpathInLength_V_V_TREADY
.outputpathInLength_TDATA(mux2udpTxLengthOut_V_V_TDATA), // input wire [15 : 0] outputpathInLength_V_V_TDATA
.inputPathPortUnreachable_TVALID(axis_udp_to_icmp_tvalid), // output wire inputPathPortUnreachable_TVALID
.inputPathPortUnreachable_TREADY(axis_udp_to_icmp_tready), // input wire inputPathPortUnreachable_TREADY
.inputPathPortUnreachable_TDATA(axis_udp_to_icmp_tdata), // output wire [63 : 0] inputPathPortUnreachable_TDATA
.inputPathPortUnreachable_TKEEP(axis_udp_to_icmp_tkeep), // output wire [7 : 0] inputPathPortUnreachable_TKEEP
.inputPathPortUnreachable_TLAST(axis_udp_to_icmp_tlast), // output wire [0 : 0] inputPathPortUnreachable_TLAST
//.ap_start(1'b1), // input wire ap_start
//.ap_ready(), // output wire ap_ready
//.ap_done(), // output wire ap_done
//.ap_idle(), // output wire ap_idle
.aclk(aclk), // input wire ap_clk
.aresetn(aresetn) // input wire ap_rst_n
);
ip_handler_ip ip_handler_inst (
.dataIn_TVALID(AXI_S_Stream_TVALID), // input wire dataIn_TVALID
.dataIn_TREADY(AXI_S_Stream_TREADY), // output wire dataIn_TREADY
.dataIn_TDATA(AXI_S_Stream_TDATA), // input wire [63 : 0] dataIn_TDATA
.dataIn_TKEEP(AXI_S_Stream_TKEEP), // input wire [7 : 0] dataIn_TKEEP
.dataIn_TLAST(AXI_S_Stream_TLAST), // input wire [0 : 0] dataIn_TLAST
.ARPdataOut_TVALID(axi_iph_to_arp_slice_tvalid), // output wire ARPdataOut_TVALID
.ARPdataOut_TREADY(axi_iph_to_arp_slice_tready), // input wire ARPdataOut_TREADY
.ARPdataOut_TDATA(axi_iph_to_arp_slice_tdata), // output wire [63 : 0] ARPdataOut_TDATA
.ARPdataOut_TKEEP(axi_iph_to_arp_slice_tkeep), // output wire [7 : 0] ARPdataOut_TKEEP
.ARPdataOut_TLAST(axi_iph_to_arp_slice_tlast), // output wire [0 : 0] ARPdataOut_TLAST
.ICMPdataOut_TVALID(axi_iph_to_icmp_slice_tvalid), // output wire ICMPdataOut_TVALID
.ICMPdataOut_TREADY(axi_iph_to_icmp_slice_tready), // input wire ICMPdataOut_TREADY
.ICMPdataOut_TDATA(axi_iph_to_icmp_slice_tdata), // output wire [63 : 0] ICMPdataOut_TDATA
.ICMPdataOut_TKEEP(axi_iph_to_icmp_slice_tkeep), // output wire [7 : 0] ICMPdataOut_TKEEP
.ICMPdataOut_TLAST(axi_iph_to_icmp_slice_tlast), // output wire [0 : 0] ICMPdataOut_TLAST
.ICMPexpDataOut_TVALID(axis_ttl_to_icmp_tvalid), // output wire ICMPexpDataOut_TVALID
.ICMPexpDataOut_TREADY(axis_ttl_to_icmp_tready), // input wire ICMPexpDataOut_TREADY
.ICMPexpDataOut_TDATA(axis_ttl_to_icmp_tdata), // output wire [63 : 0] ICMPexpDataOut_TDATA
.ICMPexpDataOut_TKEEP(axis_ttl_to_icmp_tkeep), // output wire [7 : 0] ICMPexpDataOut_TKEEP
.ICMPexpDataOut_TLAST(axis_ttl_to_icmp_tlast), // output wire [0 : 0] ICMPexpDataOut_TLAST
.UDPdataOut_TVALID(axi_iph_to_udp_tvalid), // output wire UDPdataOut_TVALID
.UDPdataOut_TREADY(axi_iph_to_udp_tready), // input wire UDPdataOut_TREADY
.UDPdataOut_TDATA(axi_iph_to_udp_tdata), // output wire [63 : 0] UDPdataOut_TDATA
.UDPdataOut_TKEEP(axi_iph_to_udp_tkeep), // output wire [7 : 0] UDPdataOut_TKEEP
.UDPdataOut_TLAST(axi_iph_to_udp_tlast), // output wire [0 : 0] UDPdataOut_TLAST
.TCPdataOut_TVALID(axi_iph_to_toe_tvalid), // output wire TCPdataOut_TVALID
.TCPdataOut_TREADY(axi_iph_to_toe_tready), // input wire TCPdataOut_TREADY
.TCPdataOut_TDATA(axi_iph_to_toe_tdata), // output wire [63 : 0] TCPdataOut_TDATA
.TCPdataOut_TKEEP(axi_iph_to_toe_tkeep), // output wire [7 : 0] TCPdataOut_TKEEP
.TCPdataOut_TLAST(axi_iph_to_toe_tlast), // output wire [0 : 0] TCPdataOut_TLAST
.regIpAddress_V(32'h01010101), // input wire [31 : 0] regIpAddress_V
.myMacAddress_V(myMacAddress), // input wire [47 : 0] myMacAddress_V
.ap_clk(aclk), // input wire ap_clk
.ap_rst_n(aresetn) // input wire ap_rst_n
);
// ARP lookup
wire axis_arp_lookup_request_TVALID;
wire axis_arp_lookup_request_TREADY;
wire[31:0] axis_arp_lookup_request_TDATA;
wire axis_arp_lookup_reply_TVALID;
wire axis_arp_lookup_reply_TREADY;
wire[55:0] axis_arp_lookup_reply_TDATA;
mac_ip_encode_ip mac_ip_encode_inst (
.dataIn_TVALID(axi_intercon_to_mie_tvalid), // input wire dataIn_TVALID
.dataIn_TREADY(axi_intercon_to_mie_tready), // output wire dataIn_TREADY
.dataIn_TDATA(axi_intercon_to_mie_tdata), // input wire [63 : 0] dataIn_TDATA
.dataIn_TKEEP(axi_intercon_to_mie_tkeep), // input wire [7 : 0] dataIn_TKEEP
.dataIn_TLAST(axi_intercon_to_mie_tlast), // input wire [0 : 0] dataIn_TLAST
.arpTableIn_V_TVALID(axis_arp_lookup_reply_TVALID), // input wire arpTableIn_V_TVALID
.arpTableIn_V_TREADY(axis_arp_lookup_reply_TREADY), // output wire arpTableIn_V_TREADY
.arpTableIn_V_TDATA(axis_arp_lookup_reply_TDATA), // input wire [55 : 0] arpTableIn_V_TDATA
.dataOut_TVALID(axi_mie_to_intercon_tvalid), // output wire dataOut_TVALID
.dataOut_TREADY(axi_mie_to_intercon_tready), // input wire dataOut_TREADY
.dataOut_TDATA(axi_mie_to_intercon_tdata), // output wire [63 : 0] dataOut_TDATA
.dataOut_TKEEP(axi_mie_to_intercon_tkeep), // output wire [7 : 0] dataOut_TKEEP
.dataOut_TLAST(axi_mie_to_intercon_tlast), // output wire [0 : 0] dataOut_TLAST
.arpTableOut_V_V_TVALID(axis_arp_lookup_request_TVALID), // output wire arpTableOut_V_V_TVALID
.arpTableOut_V_V_TREADY(axis_arp_lookup_request_TREADY), // input wire arpTableOut_V_V_TREADY
.arpTableOut_V_V_TDATA(axis_arp_lookup_request_TDATA), // output wire [31 : 0] arpTableOut_V_V_TDATA
.regSubNetMask_V(32'h00FFFFFF), // input wire [31 : 0] regSubNetMask_V
.regDefaultGateway_V(32'h01010101), // input wire [31 : 0] regDefaultGateway_V
.myMacAddress_V(myMacAddress), // input wire [47 : 0] myMacAddress_V
.ap_clk(aclk), // input wire ap_clk
.ap_rst_n(aresetn) // input wire ap_rst_n
);
// merges icmp and tcp
axis_interconnect_3to1 ip_merger (
.ACLK(aclk), // input wire ACLK
.ARESETN(aresetn), // input wire ARESETN
.S00_AXIS_ACLK(aclk), // input wire S00_AXIS_ACLK
.S01_AXIS_ACLK(aclk), // input wire S01_AXIS_ACLK
.S02_AXIS_ACLK(aclk), // input wire S02_AXIS_ACLK
.S00_AXIS_ARESETN(aresetn), // input wire S00_AXIS_ARESETN
.S01_AXIS_ARESETN(aresetn), // input wire S01_AXIS_ARESETN
.S02_AXIS_ARESETN(aresetn), // input wire S02_AXIS_ARESETN
.S00_AXIS_TVALID(axi_icmp_to_icmp_slice_tvalid), // input wire S00_AXIS_TVALID
.S01_AXIS_TVALID(axi_udp_to_merge_tvalid), // input wire S01_AXIS_TVALID
.S02_AXIS_TVALID(axi_toe_to_toe_slice_tvalid), // input wire S02_AXIS_TVALID
.S00_AXIS_TREADY(axi_icmp_to_icmp_slice_tready), // output wire S00_AXIS_TREADY
.S01_AXIS_TREADY(axi_udp_to_merge_tready), // output wire S01_AXIS_TREADY
.S02_AXIS_TREADY(axi_toe_to_toe_slice_tready), // output wire S02_AXIS_TREADY
.S00_AXIS_TDATA(axi_icmp_to_icmp_slice_tdata), // input wire [63 : 0] S00_AXIS_TDATA
.S01_AXIS_TDATA(axi_udp_to_merge_tdata), // input wire [63 : 0] S01_AXIS_TDATA
.S02_AXIS_TDATA(axi_toe_to_toe_slice_tdata), // input wire [63 : 0] S02_AXIS_TDATA
.S00_AXIS_TKEEP(axi_icmp_to_icmp_slice_tkeep), // input wire [7 : 0] S00_AXIS_TKEEP
.S01_AXIS_TKEEP(axi_udp_to_merge_tkeep), // input wire [7 : 0] S01_AXIS_TKEEP
.S02_AXIS_TKEEP(axi_toe_to_toe_slice_tkeep), // input wire [7 : 0] S02_AXIS_TKEEP
.S00_AXIS_TLAST(axi_icmp_to_icmp_slice_tlast), // input wire S00_AXIS_TLAST
.S01_AXIS_TLAST(axi_udp_to_merge_tlast), // input wire S01_AXIS_TLAST
.S02_AXIS_TLAST(axi_toe_to_toe_slice_tlast), // input wire S02_AXIS_TLAST
.M00_AXIS_ACLK(aclk), // input wire M00_AXIS_ACLK
.M00_AXIS_ARESETN(aresetn), // input wire M00_AXIS_ARESETN
.M00_AXIS_TVALID(axi_intercon_to_mie_tvalid), // output wire M00_AXIS_TVALID
.M00_AXIS_TREADY(axi_intercon_to_mie_tready), // input wire M00_AXIS_TREADY
.M00_AXIS_TDATA(axi_intercon_to_mie_tdata), // output wire [63 : 0] M00_AXIS_TDATA
.M00_AXIS_TKEEP(axi_intercon_to_mie_tkeep), // output wire [7 : 0] M00_AXIS_TKEEP
.M00_AXIS_TLAST(axi_intercon_to_mie_tlast), // output wire M00_AXIS_TLAST
.S00_ARB_REQ_SUPPRESS(1'b0), // input wire S00_ARB_REQ_SUPPRESS
.S01_ARB_REQ_SUPPRESS(1'b0), // input wire S01_ARB_REQ_SUPPRESS
.S02_ARB_REQ_SUPPRESS(1'b0) // input wire S02_ARB_REQ_SUPPRESS
);
// merges ip and arp
axis_interconnect_2to1 mac_merger (
.ACLK(aclk), // input ACLK
.ARESETN(aresetn), // input ARESETN
.S00_AXIS_ACLK(aclk), // input S00_AXIS_ACLK
.S01_AXIS_ACLK(aclk), // input S01_AXIS_ACLK
.S00_AXIS_ARESETN(aresetn), // input S00_AXIS_ARESETN
.S01_AXIS_ARESETN(aresetn), // input S01_AXIS_ARESETN
.S00_AXIS_TVALID(axi_arp_to_arp_slice_tvalid), // input S00_AXIS_TVALID
.S01_AXIS_TVALID(axi_mie_to_intercon_tvalid), // input S01_AXIS_TVALID
.S00_AXIS_TREADY(axi_arp_to_arp_slice_tready), // output S00_AXIS_TREADY
.S01_AXIS_TREADY(axi_mie_to_intercon_tready), // output S01_AXIS_TREADY
.S00_AXIS_TDATA(axi_arp_to_arp_slice_tdata), // input [63 : 0] S00_AXIS_TDATA
.S01_AXIS_TDATA(axi_mie_to_intercon_tdata), // input [63 : 0] S01_AXIS_TDATA
.S00_AXIS_TKEEP(axi_arp_to_arp_slice_tkeep), // input [7 : 0] S00_AXIS_TKEEP
.S01_AXIS_TKEEP(axi_mie_to_intercon_tkeep), // input [7 : 0] S01_AXIS_TKEEP
.S00_AXIS_TLAST(axi_arp_to_arp_slice_tlast), // input S00_AXIS_TLAST
.S01_AXIS_TLAST(axi_mie_to_intercon_tlast), // input S01_AXIS_TLAST
.M00_AXIS_ACLK(aclk), // input M00_AXIS_ACLK
.M00_AXIS_ARESETN(aresetn), // input M00_AXIS_ARESETN
.M00_AXIS_TVALID(AXI_M_Stream_TVALID), // output M00_AXIS_TVALID
.M00_AXIS_TREADY(AXI_M_Stream_TREADY), // input M00_AXIS_TREADY
.M00_AXIS_TDATA(AXI_M_Stream_TDATA), // output [63 : 0] M00_AXIS_TDATA
.M00_AXIS_TKEEP(AXI_M_Stream_TKEEP), // output [7 : 0] M00_AXIS_TKEEP
.M00_AXIS_TLAST(AXI_M_Stream_TLAST), // output M00_AXIS_TLAST
.S00_ARB_REQ_SUPPRESS(1'b0), // input S00_ARB_REQ_SUPPRESS
.S01_ARB_REQ_SUPPRESS(1'b0) // input S01_ARB_REQ_SUPPRESS
);
arpServerWrapper arpServerInst (
.axi_arp_to_arp_slice_tvalid(axi_arp_to_arp_slice_tvalid),
.axi_arp_to_arp_slice_tready(axi_arp_to_arp_slice_tready),
.axi_arp_to_arp_slice_tdata(axi_arp_to_arp_slice_tdata),
.axi_arp_to_arp_slice_tkeep(axi_arp_to_arp_slice_tkeep),
.axi_arp_to_arp_slice_tlast(axi_arp_to_arp_slice_tlast),
.axis_arp_lookup_reply_TVALID(axis_arp_lookup_reply_TVALID),
.axis_arp_lookup_reply_TREADY(axis_arp_lookup_reply_TREADY),
.axis_arp_lookup_reply_TDATA(axis_arp_lookup_reply_TDATA),
.axi_arp_slice_to_arp_tvalid(axi_arp_slice_to_arp_tvalid),
.axi_arp_slice_to_arp_tready(axi_arp_slice_to_arp_tready),
.axi_arp_slice_to_arp_tdata(axi_arp_slice_to_arp_tdata),
.axi_arp_slice_to_arp_tkeep(axi_arp_slice_to_arp_tkeep),
.axi_arp_slice_to_arp_tlast(axi_arp_slice_to_arp_tlast),
.axis_arp_lookup_request_TVALID(axis_arp_lookup_request_TVALID),
.axis_arp_lookup_request_TREADY(axis_arp_lookup_request_TREADY),
.axis_arp_lookup_request_TDATA(axis_arp_lookup_request_TDATA),
.myMacAddress(myMacAddress),
.myIpAddress(32'h01010101),
.aclk(aclk), // input aclk
.aresetn(aresetn)); // input aresetn
assign axi_debug1_tkeep = axi_toe_to_toe_slice_tkeep;
assign axi_debug1_tdata = axi_toe_to_toe_slice_tdata;
assign axi_debug1_tvalid = axi_toe_to_toe_slice_tvalid;
assign axi_debug1_tready = axi_toe_to_toe_slice_tready;
assign axi_debug1_tlast = axi_toe_to_toe_slice_tlast;
assign axi_debug2_tkeep = axi_iph_to_toe_tkeep;
assign axi_debug2_tdata = axi_iph_to_toe_tdata;
assign axi_debug2_tvalid = axi_iph_to_toe_tvalid;
assign axi_debug2_tready = axi_iph_to_toe_tready;
assign axi_debug2_tlast = axi_iph_to_toe_tlast;
icmp_server_ip icmp_server_inst (
.dataIn_TVALID(axi_icmp_slice_to_icmp_tvalid), // input wire dataIn_TVALID
.dataIn_TREADY(axi_icmp_slice_to_icmp_tready), // output wire dataIn_TREADY
.dataIn_TDATA(axi_icmp_slice_to_icmp_tdata), // input wire [63 : 0] dataIn_TDATA
.dataIn_TKEEP(axi_icmp_slice_to_icmp_tkeep), // input wire [7 : 0] dataIn_TKEEP
.dataIn_TLAST(axi_icmp_slice_to_icmp_tlast), // input wire [0 : 0] dataIn_TLAST
.udpIn_TVALID(axis_udp_to_icmp_tvalid), // input wire udpIn_TVALID
.udpIn_TREADY(axis_udp_to_icmp_tready), // output wire udpIn_TREADY
.udpIn_TDATA(axis_udp_to_icmp_tdata), // input wire [63 : 0] udpIn_TDATA
.udpIn_TKEEP(axis_udp_to_icmp_tkeep), // input wire [7 : 0] udpIn_TKEEP
.udpIn_TLAST(axis_udp_to_icmp_tlast), // input wire [0 : 0] udpIn_TLAST
.ttlIn_TVALID(axis_ttl_to_icmp_tvalid), // input wire ttlIn_TVALID
.ttlIn_TREADY(axis_ttl_to_icmp_tready), // output wire ttlIn_TREADY
.ttlIn_TDATA(axis_ttl_to_icmp_tdata), // input wire [63 : 0] ttlIn_TDATA
.ttlIn_TKEEP(axis_ttl_to_icmp_tkeep), // input wire [7 : 0] ttlIn_TKEEP
.ttlIn_TLAST(axis_ttl_to_icmp_tlast), // input wire [0 : 0] ttlIn_TLAST
.dataOut_TVALID(axi_icmp_to_icmp_slice_tvalid), // output wire dataOut_TVALID
.dataOut_TREADY(axi_icmp_to_icmp_slice_tready), // input wire dataOut_TREADY
.dataOut_TDATA(axi_icmp_to_icmp_slice_tdata), // output wire [63 : 0] dataOut_TDATA
.dataOut_TKEEP(axi_icmp_to_icmp_slice_tkeep), // output wire [7 : 0] dataOut_TKEEP
.dataOut_TLAST(axi_icmp_to_icmp_slice_tlast), // output wire [0 : 0] dataOut_TLAST
.ap_clk(aclk), // input wire ap_clk
.ap_rst_n(aresetn) // input wire ap_rst_n
);
/*
* Slices
*/
// ARP Input Slice
axis_register_slice_64 axis_register_arp_in_slice(
.aclk(aclk),
.aresetn(aresetn),
.s_axis_tvalid(axi_iph_to_arp_slice_tvalid),
.s_axis_tready(axi_iph_to_arp_slice_tready),
.s_axis_tdata(axi_iph_to_arp_slice_tdata),
.s_axis_tkeep(axi_iph_to_arp_slice_tkeep),
.s_axis_tlast(axi_iph_to_arp_slice_tlast),
.m_axis_tvalid(axi_arp_slice_to_arp_tvalid),
.m_axis_tready(axi_arp_slice_to_arp_tready),
.m_axis_tdata(axi_arp_slice_to_arp_tdata),
.m_axis_tkeep(axi_arp_slice_to_arp_tkeep),
.m_axis_tlast(axi_arp_slice_to_arp_tlast)
);
// ICMP Input Slice
axis_register_slice_64 axis_register_icmp_in_slice(
.aclk(aclk),
.aresetn(aresetn),
.s_axis_tvalid(axi_iph_to_icmp_slice_tvalid),
.s_axis_tready(axi_iph_to_icmp_slice_tready),
.s_axis_tdata(axi_iph_to_icmp_slice_tdata),
.s_axis_tkeep(axi_iph_to_icmp_slice_tkeep),
.s_axis_tlast(axi_iph_to_icmp_slice_tlast),
.m_axis_tvalid(axi_icmp_slice_to_icmp_tvalid),
.m_axis_tready(axi_icmp_slice_to_icmp_tready),
.m_axis_tdata(axi_icmp_slice_to_icmp_tdata),
.m_axis_tkeep(axi_icmp_slice_to_icmp_tkeep),
.m_axis_tlast(axi_icmp_slice_to_icmp_tlast)
);
udpAppMux_0 myAppMux (
.portOpenReplyIn_TVALID(udp2mux_portOpenReplyIn_V_V_TVALID), // input wire portOpenReplyIn_TVALID
.portOpenReplyIn_TREADY(udp2mux_portOpenReplyIn_V_V_TREADY), // output wire portOpenReplyIn_TREADY
.portOpenReplyIn_TDATA(udp2mux_portOpenReplyIn_V_V_TDATA), // input wire [7 : 0] portOpenReplyIn_TDATA
.requestPortOpenOut_TVALID(mux2udp_requestPortOpenOut_V_TVALID), // output wire requestPortOpenOut_TVALID
.requestPortOpenOut_TREADY(mux2udp_requestPortOpenOut_V_TREADY), // input wire requestPortOpenOut_TREADY
.requestPortOpenOut_TDATA(mux2udp_requestPortOpenOut_V_TDATA), // output wire [15 : 0] requestPortOpenOut_TDATA
.portOpenReplyOutApp_TVALID(lbPortOpenReplyIn_TVALID), // output wire portOpenReplyOutApp_TVALID
.portOpenReplyOutApp_TREADY(lbPortOpenReplyIn_TREADY), // input wire portOpenReplyOutApp_TREADY
.portOpenReplyOutApp_TDATA(lbPortOpenReplyIn_TDATA), // output wire [7 : 0] portOpenReplyOutApp_TDATA
.requestPortOpenInApp_TVALID(lbRequestPortOpenOut_TVALID), // input wire requestPortOpenInApp_TVALID
.requestPortOpenInApp_TREADY(lbRequestPortOpenOut_TREADY), // output wire requestPortOpenInApp_TREADY
.requestPortOpenInApp_TDATA(lbRequestPortOpenOut_TDATA), // input wire [15 : 0] requestPortOpenInApp_TDATA
.portOpenReplyOutDhcp_TVALID(mux2dhcp_portOpenReplyIn_V_V_TVALID), // output wire portOpenReplyOutDhcp_TVALID
.portOpenReplyOutDhcp_TREADY(mux2dhcp_portOpenReplyIn_V_V_TREADY), // input wire portOpenReplyOutDhcp_TREADY
.portOpenReplyOutDhcp_TDATA(mux2dhcp_portOpenReplyIn_V_V_TDATA), // output wire [7 : 0] portOpenReplyOutDhcp_TDATA
.requestPortOpenInDhcp_TVALID(dhcp2mux_requestPortOpenOut_V_TVALID), // input wire requestPortOpenInDhcp_TVALID
.requestPortOpenInDhcp_TREADY(dhcp2mux_requestPortOpenOut_V_TREADY), // output wire requestPortOpenInDhcp_TREADY
.requestPortOpenInDhcp_TDATA(dhcp2mux_requestPortOpenOut_V_TDATA), // input wire [15 : 0] requestPortOpenInDhcp_TDATA
.rxDataIn_TVALID(udp2muxRxDataIn_TVALID), // input wire rxDataIn_TVALID
.rxDataIn_TREADY(udp2muxRxDataIn_TREADY), // output wire rxDataIn_TREADY
.rxDataIn_TDATA(udp2muxRxDataIn_TDATA), // input wire [63 : 0] rxDataIn_TDATA
.rxDataIn_TKEEP(udp2muxRxDataIn_TKEEP), // input wire [7 : 0] rxDataIn_TKEEP
.rxDataIn_TLAST(udp2muxRxDataIn_TLAST), // input wire [0 : 0] rxDataIn_TLAST
.rxDataOutApp_TVALID(lbRxDataIn_TVALID), // output wire rxDataOutApp_TVALID
.rxDataOutApp_TREADY(lbRxDataIn_TREADY), // input wire rxDataOutApp_TREADY
.rxDataOutApp_TDATA(lbRxDataIn_TDATA), // output wire [63 : 0] rxDataOutApp_TDATA
.rxDataOutApp_TKEEP(lbRxDataIn_TKEEP), // output wire [7 : 0] rxDataOutApp_TKEEP
.rxDataOutApp_TLAST(lbRxDataIn_TLAST), // output wire [0 : 0] rxDataOutApp_TLAST
.rxDataOutDhcp_TVALID(mux2dhcpRxDataIn_TVALID), // output wire rxDataOutDhcp_TVALID
.rxDataOutDhcp_TREADY(mux2dhcpRxDataIn_TREADY), // input wire rxDataOutDhcp_TREADY
.rxDataOutDhcp_TDATA(mux2dhcpRxDataIn_TDATA), // output wire [63 : 0] rxDataOutDhcp_TDATA
.rxDataOutDhcp_TKEEP(mux2dhcpRxDataIn_TKEEP), // output wire [7 : 0] rxDataOutDhcp_TKEEP
.rxDataOutDhcp_TLAST(mux2dhcpRxDataIn_TLAST), // output wire [0 : 0] rxDataOutDhcp_TLAST
.rxMetadataIn_TVALID(udp2muxRxMetadataIn_V_TVALID), // input wire rxMetadataIn_TVALID
.rxMetadataIn_TREADY(udp2muxRxMetadataIn_V_TREADY), // output wire rxMetadataIn_TREADY
.rxMetadataIn_TDATA(udp2muxRxMetadataIn_V_TDATA), // input wire [95 : 0] rxMetadataIn_TDATA
.rxMetadataOutApp_TVALID(lbRxMetadataIn_TVALID), // output wire rxMetadataOutApp_TVALID
.rxMetadataOutApp_TREADY(lbRxMetadataIn_TREADY), // input wire rxMetadataOutApp_TREADY
.rxMetadataOutApp_TDATA(lbRxMetadataIn_TDATA), // output wire [95 : 0] rxMetadataOutApp_TDATA
.rxMetadataOutDhcp_TVALID(mux2dhcpRxMetadataIn_V_TVALID), // output wire rxMetadataOutDhcp_TVALID
.rxMetadataOutDhcp_TREADY(mux2dhcpRxMetadataIn_V_TREADY), // input wire rxMetadataOutDhcp_TREADY
.rxMetadataOutDhcp_TDATA(mux2dhcpRxMetadataIn_V_TDATA), // output wire [95 : 0] rxMetadataOutDhcp_TDATA
.txDataInApp_TVALID(lbTxDataOut_TVALID), // input wire txDataInApp_TVALID
.txDataInApp_TREADY(lbTxDataOut_TREADY), // output wire txDataInApp_TREADY
.txDataInApp_TDATA(lbTxDataOut_TDATA), // input wire [63 : 0] txDataInApp_TDATA
.txDataInApp_TKEEP(lbTxDataOut_TKEEP), // input wire [7 : 0] txDataInApp_TKEEP
.txDataInApp_TLAST(lbTxDataOut_TLAST), // input wire [0 : 0] txDataInApp_TLAST
.txDataInDhcp_TVALID(dhcp2mux_TVALID), // input wire txDataInDhcp_TVALID
.txDataInDhcp_TREADY(dhcp2mux_TREADY), // output wire txDataInDhcp_TREADY
.txDataInDhcp_TDATA(dhcp2mux_TDATA), // input wire [63 : 0] txDataInDhcp_TDATA
.txDataInDhcp_TKEEP(dhcp2mux_TKEEP), // input wire [7 : 0] txDataInDhcp_TKEEP
.txDataInDhcp_TLAST(dhcp2mux_TLAST), // input wire [0 : 0] txDataInDhcp_TLAST
.txDataOut_TVALID(mux2udp_TVALID), // output wire txDataOut_TVALID
.txDataOut_TREADY(mux2udp_TREADY), // input wire txDataOut_TREADY
.txDataOut_TDATA(mux2udp_TDATA), // output wire [63 : 0] txDataOut_TDATA
.txDataOut_TKEEP(mux2udp_TKEEP), // output wire [7 : 0] txDataOut_TKEEP
.txDataOut_TLAST(mux2udp_TLAST), // output wire [0 : 0] txDataOut_TLAST
.txLengthInApp_TVALID(lbTxLengthOut_TVALID), // input wire txLengthInApp_TVALID
.txLengthInApp_TREADY(lbTxLengthOut_TREADY), // output wire txLengthInApp_TREADY
.txLengthInApp_TDATA(lbTxLengthOut_TDATA), // input wire [15 : 0] txLengthInApp_TDATA
.txLengthInDhcp_TVALID(dhcp2muxTxLengthOut_V_V_TVALID), // input wire txLengthInDhcp_TVALID
.txLengthInDhcp_TREADY(dhcp2muxTxLengthOut_V_V_TREADY), // output wire txLengthInDhcp_TREADY
.txLengthInDhcp_TDATA(dhcp2muxTxLengthOut_V_V_TDATA), // input wire [15 : 0] txLengthInDhcp_TDATA
.txLengthOut_TVALID(mux2udpTxLengthOut_V_V_TVALID), // output wire txLengthOut_TVALID
.txLengthOut_TREADY(mux2udpTxLengthOut_V_V_TREADY), // input wire txLengthOut_TREADY
.txLengthOut_TDATA(mux2udpTxLengthOut_V_V_TDATA), // output wire [15 : 0] txLengthOut_TDATA
.txMetadataInApp_TVALID(lbTxMetadataOut_TVALID), // input wire txMetadataInApp_TVALID
.txMetadataInApp_TREADY(lbTxMetadataOut_TREADY), // output wire txMetadataInApp_TREADY
.txMetadataInApp_TDATA(lbTxMetadataOut_TDATA), // input wire [95 : 0] txMetadataInApp_TDATA
.txMetadataInDhcp_TVALID(dhcp2muxTxMetadataOut_V_TVALID), // input wire txMetadataInDhcp_TVALID
.txMetadataInDhcp_TREADY(dhcp2muxTxMetadataOut_V_TREADY), // output wire txMetadataInDhcp_TREADY
.txMetadataInDhcp_TDATA(dhcp2muxTxMetadataOut_V_TDATA), // input wire [95 : 0] txMetadataInDhcp_TDATA
.txMetadataOut_TVALID(mux2udpTxMetadataOut_V_TVALID), // output wire txMetadataOut_TVALID
.txMetadataOut_TREADY(mux2udpTxMetadataOut_V_TREADY), // input wire txMetadataOut_TREADY
.txMetadataOut_TDATA(mux2udpTxMetadataOut_V_TDATA), // output wire [95 : 0] txMetadataOut_TDATA
.aclk(aclk), // input wire aclk
.aresetn(aresetn) // input wire aresetn
);
dhcp_client_0 myDhcpClient (
.dhcpEnable_V(dhcpEnable), // input wire [0 : 0] dhcpEnable_V
.inputIpAddress_V(inputIpAddress), // input wire [31 : 0] inputIpAddress_V
.dhcpIpAddressOut_V(dhcpAddressOut), // output wire [31 : 0] dhcpIpAddressOut_V
.myMacAddress_V(myMacAddress), // input wire [47 : 0] myMacAddress_V
.m_axis_open_port_TVALID(dhcp2mux_requestPortOpenOut_V_TVALID), // output wire m_axis_open_port_TVALID
.m_axis_open_port_TREADY(dhcp2mux_requestPortOpenOut_V_TREADY), // input wire m_axis_open_port_TREADY
.m_axis_open_port_TDATA(dhcp2mux_requestPortOpenOut_V_TDATA), // output wire [15 : 0] m_axis_open_port_TDATA
.m_axis_tx_data_TVALID(dhcp2mux_TVALID), // output wire m_axis_tx_data_TVALID
.m_axis_tx_data_TREADY(dhcp2mux_TREADY), // input wire m_axis_tx_data_TREADY
.m_axis_tx_data_TDATA(dhcp2mux_TDATA), // output wire [63 : 0] m_axis_tx_data_TDATA
.m_axis_tx_data_TKEEP(dhcp2mux_TKEEP), // output wire [7 : 0] m_axis_tx_data_TKEEP
.m_axis_tx_data_TLAST(dhcp2mux_TLAST), // output wire [0 : 0] m_axis_tx_data_TLAST
.m_axis_tx_length_TVALID(dhcp2muxTxLengthOut_V_V_TVALID), // output wire m_axis_tx_length_TVALID
.m_axis_tx_length_TREADY(dhcp2muxTxLengthOut_V_V_TREADY), // input wire m_axis_tx_length_TREADY
.m_axis_tx_length_TDATA(dhcp2muxTxLengthOut_V_V_TDATA), // output wire [15 : 0] m_axis_tx_length_TDATA
.m_axis_tx_metadata_TVALID(dhcp2muxTxMetadataOut_V_TVALID), // output wire m_axis_tx_metadata_TVALID
.m_axis_tx_metadata_TREADY(dhcp2muxTxMetadataOut_V_TREADY), // input wire m_axis_tx_metadata_TREADY
.m_axis_tx_metadata_TDATA(dhcp2muxTxMetadataOut_V_TDATA), // output wire [95 : 0] m_axis_tx_metadata_TDATA
.s_axis_open_port_status_TVALID(mux2dhcp_portOpenReplyIn_V_V_TVALID), // input wire s_axis_open_port_status_TVALID
.s_axis_open_port_status_TREADY(mux2dhcp_portOpenReplyIn_V_V_TREADY), // output wire s_axis_open_port_status_TREADY
.s_axis_open_port_status_TDATA(mux2dhcp_portOpenReplyIn_V_V_TDATA), // input wire [7 : 0] s_axis_open_port_status_TDATA
.s_axis_rx_data_TVALID(mux2dhcpRxDataIn_TVALID), // input wire s_axis_rx_data_TVALID
.s_axis_rx_data_TREADY(mux2dhcpRxDataIn_TREADY), // output wire s_axis_rx_data_TREADY
.s_axis_rx_data_TDATA(mux2dhcpRxDataIn_TDATA), // input wire [63 : 0] s_axis_rx_data_TDATA
.s_axis_rx_data_TKEEP(mux2dhcpRxDataIn_TKEEP), // input wire [7 : 0] s_axis_rx_data_TKEEP
.s_axis_rx_data_TLAST(mux2dhcpRxDataIn_TLAST), // input wire [0 : 0] s_axis_rx_data_TLAST
.s_axis_rx_metadata_TVALID(mux2dhcpRxMetadataIn_V_TVALID), // input wire s_axis_rx_metadata_TVALID
.s_axis_rx_metadata_TREADY(mux2dhcpRxMetadataIn_V_TREADY), // output wire s_axis_rx_metadata_TREADY
.s_axis_rx_metadata_TDATA(mux2dhcpRxMetadataIn_V_TDATA), // input wire [95 : 0] s_axis_rx_metadata_TDATA
.aclk(aclk), // input wire aclk
.aresetn(aresetn) // input wire aresetn
);
assign ipAddressOut = dhcpAddressOut;
assign upd_req_TVALID_out = upd_req_TVALID;
assign upd_req_TREADY_out = upd_req_TREADY;
assign upd_req_TDATA_out = upd_req_TDATA[1];
assign upd_rsp_TVALID_out = upd_rsp_TVALID;
assign upd_rsp_TREADY_out = upd_rsp_TREADY;
endmodule |
module sky130_fd_sc_lp__isobufsrc (
X ,
SLEEP,
A
);
output X ;
input SLEEP;
input A ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module KeyPadInterpreter(
input Clock,
input ResetButton,
input KeyRead,
input [3:0] RowDataIn,
output KeyReady,
output [3:0] DataOut,
output [3:0] ColDataOut,
output [3:0] PressCount
);
//The keypad interpreter accepts typical inputs...
// Clock, Reset
//As well as KeyPad input/output connections...
// RowDataIn, ColDataOut
//Important Outputs...
// KeyReady, PressCount, DataOut
// KeyReady goes high when a key is ready
// to be read and does not go down
// until KeyRead goes high.
// PressCout is the single hexadigit
// value describing the number of
// times a key has been pressed
// DataOut is the single hexadigit
// value describing the button
// most recently pressed.
//Important Inputs...
// KeyRead must be asserted high for the
// scanner to continue. The KeyRead
// signal may only stay high for 8ms
// at most, it is recommended that the
// signal not remain high for longer
// than 4ms.
wire [3:0] KeyCode;
wire LFSRRst;
wire LFSRFlg;
LFSR25000 LFSR (Clock, LFSRRst, LFSRFlg);
KeyPadScanner Scanner (ResetButton, Clock, RowDataIn, ColDataOut, LFSRRst, LFSRFlg, KeyCode, KeyReady, KeyRead);
PulseCounter Count (ResetButton, Clock, KeyReady, PressCount);
KeyPadDecoder Decoder (KeyCode , DataOut);
endmodule |
module sirv_qspi_physical_2(
input clock,
input reset,
output io_port_sck,
input io_port_dq_0_i,
output io_port_dq_0_o,
output io_port_dq_0_oe,
input io_port_dq_1_i,
output io_port_dq_1_o,
output io_port_dq_1_oe,
input io_port_dq_2_i,
output io_port_dq_2_o,
output io_port_dq_2_oe,
input io_port_dq_3_i,
output io_port_dq_3_o,
output io_port_dq_3_oe,
output io_port_cs_0,
input [11:0] io_ctrl_sck_div,
input io_ctrl_sck_pol,
input io_ctrl_sck_pha,
input [1:0] io_ctrl_fmt_proto,
input io_ctrl_fmt_endian,
input io_ctrl_fmt_iodir,
output io_op_ready,
input io_op_valid,
input io_op_bits_fn,
input io_op_bits_stb,
input [7:0] io_op_bits_cnt,
input [7:0] io_op_bits_data,
output io_rx_valid,
output [7:0] io_rx_bits
);
reg [11:0] ctrl_sck_div;
reg [31:0] GEN_2;
reg ctrl_sck_pol;
reg [31:0] GEN_31;
reg ctrl_sck_pha;
reg [31:0] GEN_52;
reg [1:0] ctrl_fmt_proto;
reg [31:0] GEN_67;
reg ctrl_fmt_endian;
reg [31:0] GEN_68;
reg ctrl_fmt_iodir;
reg [31:0] GEN_69;
wire proto_0;
wire proto_1;
wire proto_2;
wire accept;
wire sample;
wire setup;
wire last;
reg setup_d;
reg [31:0] GEN_70;
reg T_119;
reg [31:0] GEN_71;
reg T_120;
reg [31:0] GEN_72;
reg sample_d;
reg [31:0] GEN_73;
reg T_122;
reg [31:0] GEN_74;
reg T_123;
reg [31:0] GEN_75;
reg last_d;
reg [31:0] GEN_76;
reg [7:0] scnt;
reg [31:0] GEN_77;
reg [11:0] tcnt;
reg [31:0] GEN_78;
wire stop;
wire beat;
wire [11:0] T_127;
wire [12:0] T_129;
wire [11:0] decr;
wire sched;
wire [11:0] T_130;
reg sck;
reg [31:0] GEN_79;
reg cref;
reg [31:0] GEN_80;
wire cinv;
wire [1:0] T_133;
wire [1:0] T_134;
wire [3:0] rxd;
wire samples_0;
wire [1:0] samples_1;
reg [7:0] buffer;
reg [31:0] GEN_81;
wire T_135;
wire T_136;
wire T_137;
wire T_138;
wire T_139;
wire T_140;
wire T_141;
wire T_142;
wire T_143;
wire [1:0] T_144;
wire [1:0] T_145;
wire [3:0] T_146;
wire [1:0] T_147;
wire [1:0] T_148;
wire [3:0] T_149;
wire [7:0] T_150;
wire [7:0] buffer_in;
wire T_151;
wire shift;
wire [6:0] T_152;
wire [6:0] T_153;
wire [6:0] T_154;
wire T_155;
wire T_157;
wire [7:0] T_158;
wire [5:0] T_159;
wire [5:0] T_160;
wire [5:0] T_161;
wire [1:0] T_162;
wire [1:0] T_163;
wire [7:0] T_164;
wire [3:0] T_165;
wire [3:0] T_166;
wire [3:0] T_167;
wire [3:0] T_169;
wire [7:0] T_170;
wire [7:0] T_172;
wire [7:0] T_174;
wire [7:0] T_176;
wire [7:0] T_178;
wire [7:0] T_179;
wire [7:0] T_180;
reg [3:0] txd;
reg [31:0] GEN_82;
wire [3:0] T_182;
wire [3:0] txd_in;
wire [1:0] T_184;
wire txd_sel_0;
wire txd_sel_1;
wire txd_sel_2;
wire txd_shf_0;
wire [1:0] txd_shf_1;
wire T_186;
wire [1:0] T_188;
wire [3:0] T_190;
wire [1:0] GEN_65;
wire [1:0] T_192;
wire [3:0] GEN_66;
wire [3:0] T_193;
wire [3:0] T_194;
wire [3:0] GEN_0;
wire T_195;
wire T_196;
wire txen_1;
wire txen_0;
wire T_202_0;
wire T_206;
wire T_207;
wire T_208;
wire T_209;
reg done;
reg [31:0] GEN_83;
wire T_212;
wire T_213;
wire T_215;
wire T_216;
wire T_217;
wire T_218;
wire T_219;
wire T_220;
wire T_221;
wire [1:0] T_222;
wire [1:0] T_223;
wire [3:0] T_224;
wire [1:0] T_225;
wire [1:0] T_226;
wire [3:0] T_227;
wire [7:0] T_228;
wire [7:0] T_229;
reg xfr;
reg [31:0] GEN_84;
wire GEN_1;
wire T_234;
wire T_236;
wire T_237;
wire GEN_3;
wire GEN_4;
wire GEN_5;
wire [11:0] GEN_6;
wire GEN_7;
wire GEN_8;
wire GEN_9;
wire GEN_10;
wire [11:0] GEN_11;
wire GEN_12;
wire GEN_13;
wire GEN_14;
wire GEN_15;
wire [11:0] GEN_16;
wire T_243;
wire T_244;
wire T_245;
wire T_248;
wire GEN_17;
wire GEN_18;
wire GEN_19;
wire GEN_20;
wire GEN_21;
wire GEN_22;
wire GEN_23;
wire T_251;
wire [1:0] GEN_24;
wire GEN_25;
wire GEN_26;
wire T_254;
wire T_257;
wire [7:0] GEN_27;
wire GEN_28;
wire GEN_29;
wire GEN_30;
wire GEN_32;
wire [11:0] GEN_33;
wire GEN_34;
wire GEN_35;
wire GEN_36;
wire [11:0] GEN_37;
wire GEN_38;
wire GEN_39;
wire [11:0] GEN_40;
wire [1:0] GEN_41;
wire GEN_42;
wire GEN_43;
wire GEN_44;
wire [7:0] GEN_45;
wire GEN_46;
wire GEN_47;
wire GEN_48;
wire [11:0] GEN_49;
wire GEN_50;
wire GEN_51;
wire [11:0] GEN_53;
wire [1:0] GEN_54;
wire GEN_55;
wire GEN_56;
wire GEN_57;
wire [7:0] GEN_58;
wire GEN_59;
wire GEN_60;
wire GEN_61;
wire [11:0] GEN_62;
wire GEN_63;
wire GEN_64;
assign io_port_sck = sck;
assign io_port_dq_0_o = T_206;
assign io_port_dq_0_oe = txen_0;
assign io_port_dq_1_o = T_207;
assign io_port_dq_1_oe = txen_1;
assign io_port_dq_2_o = T_208;
assign io_port_dq_2_oe = T_196;
assign io_port_dq_3_o = T_209;
assign io_port_dq_3_oe = io_port_dq_2_oe;
assign io_port_cs_0 = T_202_0;
assign io_op_ready = T_251;
assign io_rx_valid = done;
assign io_rx_bits = T_229;
assign proto_0 = 2'h0 == ctrl_fmt_proto;
assign proto_1 = 2'h1 == ctrl_fmt_proto;
assign proto_2 = 2'h2 == ctrl_fmt_proto;
assign accept = GEN_21;
assign sample = GEN_14;
assign setup = GEN_60;
assign last = GEN_20;
assign stop = scnt == 8'h0;
assign beat = tcnt == 12'h0;
assign T_127 = beat ? {{4'd0}, scnt} : tcnt;
assign T_129 = T_127 - 12'h1;
assign decr = T_129[11:0];
assign sched = GEN_1;
assign T_130 = sched ? ctrl_sck_div : decr;
assign cinv = ctrl_sck_pha ^ ctrl_sck_pol;
assign T_133 = {io_port_dq_1_i,io_port_dq_0_i};
assign T_134 = {io_port_dq_3_i,io_port_dq_2_i};
assign rxd = {T_134,T_133};
assign samples_0 = rxd[1];
assign samples_1 = rxd[1:0];
assign T_135 = io_ctrl_fmt_endian == 1'h0;
assign T_136 = io_op_bits_data[0];
assign T_137 = io_op_bits_data[1];
assign T_138 = io_op_bits_data[2];
assign T_139 = io_op_bits_data[3];
assign T_140 = io_op_bits_data[4];
assign T_141 = io_op_bits_data[5];
assign T_142 = io_op_bits_data[6];
assign T_143 = io_op_bits_data[7];
assign T_144 = {T_142,T_143};
assign T_145 = {T_140,T_141};
assign T_146 = {T_145,T_144};
assign T_147 = {T_138,T_139};
assign T_148 = {T_136,T_137};
assign T_149 = {T_148,T_147};
assign T_150 = {T_149,T_146};
assign buffer_in = T_135 ? io_op_bits_data : T_150;
assign T_151 = sample_d & stop;
assign shift = setup_d | T_151;
assign T_152 = buffer[6:0];
assign T_153 = buffer[7:1];
assign T_154 = shift ? T_152 : T_153;
assign T_155 = buffer[0];
assign T_157 = sample_d ? samples_0 : T_155;
assign T_158 = {T_154,T_157};
assign T_159 = buffer[5:0];
assign T_160 = buffer[7:2];
assign T_161 = shift ? T_159 : T_160;
assign T_162 = buffer[1:0];
assign T_163 = sample_d ? samples_1 : T_162;
assign T_164 = {T_161,T_163};
assign T_165 = buffer[3:0];
assign T_166 = buffer[7:4];
assign T_167 = shift ? T_165 : T_166;
assign T_169 = sample_d ? rxd : T_165;
assign T_170 = {T_167,T_169};
assign T_172 = proto_0 ? T_158 : 8'h0;
assign T_174 = proto_1 ? T_164 : 8'h0;
assign T_176 = proto_2 ? T_170 : 8'h0;
assign T_178 = T_172 | T_174;
assign T_179 = T_178 | T_176;
assign T_180 = T_179;
assign T_182 = buffer_in[7:4];
assign txd_in = accept ? T_182 : T_166;
assign T_184 = accept ? io_ctrl_fmt_proto : ctrl_fmt_proto;
assign txd_sel_0 = 2'h0 == T_184;
assign txd_sel_1 = 2'h1 == T_184;
assign txd_sel_2 = 2'h2 == T_184;
assign txd_shf_0 = txd_in[3];
assign txd_shf_1 = txd_in[3:2];
assign T_186 = txd_sel_0 ? txd_shf_0 : 1'h0;
assign T_188 = txd_sel_1 ? txd_shf_1 : 2'h0;
assign T_190 = txd_sel_2 ? txd_in : 4'h0;
assign GEN_65 = {{1'd0}, T_186};
assign T_192 = GEN_65 | T_188;
assign GEN_66 = {{2'd0}, T_192};
assign T_193 = GEN_66 | T_190;
assign T_194 = T_193;
assign GEN_0 = setup ? T_194 : txd;
assign T_195 = proto_1 & ctrl_fmt_iodir;
assign T_196 = proto_2 & ctrl_fmt_iodir;
assign txen_1 = T_195 | T_196;
assign txen_0 = proto_0 | txen_1;
assign T_202_0 = 1'h1;
assign T_206 = txd[0];
assign T_207 = txd[1];
assign T_208 = txd[2];
assign T_209 = txd[3];
assign T_212 = done | last_d;
assign T_213 = ctrl_fmt_endian == 1'h0;
assign T_215 = buffer[1];
assign T_216 = buffer[2];
assign T_217 = buffer[3];
assign T_218 = buffer[4];
assign T_219 = buffer[5];
assign T_220 = buffer[6];
assign T_221 = buffer[7];
assign T_222 = {T_220,T_221};
assign T_223 = {T_218,T_219};
assign T_224 = {T_223,T_222};
assign T_225 = {T_216,T_217};
assign T_226 = {T_155,T_215};
assign T_227 = {T_226,T_225};
assign T_228 = {T_227,T_224};
assign T_229 = T_213 ? buffer : T_228;
assign GEN_1 = stop ? 1'h1 : beat;
assign T_234 = stop == 1'h0;
assign T_236 = cref == 1'h0;
assign T_237 = cref ^ cinv;
assign GEN_3 = xfr ? T_237 : sck;
assign GEN_4 = xfr ? cref : 1'h0;
assign GEN_5 = xfr ? T_236 : 1'h0;
assign GEN_6 = T_236 ? decr : {{4'd0}, scnt};
assign GEN_7 = beat ? T_236 : cref;
assign GEN_8 = beat ? GEN_3 : sck;
assign GEN_9 = beat ? GEN_4 : 1'h0;
assign GEN_10 = beat ? GEN_5 : 1'h0;
assign GEN_11 = beat ? GEN_6 : {{4'd0}, scnt};
assign GEN_12 = T_234 ? GEN_7 : cref;
assign GEN_13 = T_234 ? GEN_8 : sck;
assign GEN_14 = T_234 ? GEN_9 : 1'h0;
assign GEN_15 = T_234 ? GEN_10 : 1'h0;
assign GEN_16 = T_234 ? GEN_11 : {{4'd0}, scnt};
assign T_243 = scnt == 8'h1;
assign T_244 = beat & cref;
assign T_245 = T_244 & xfr;
assign T_248 = beat & T_236;
assign GEN_17 = T_248 ? 1'h1 : stop;
assign GEN_18 = T_248 ? 1'h0 : GEN_15;
assign GEN_19 = T_248 ? ctrl_sck_pol : GEN_13;
assign GEN_20 = T_243 ? T_245 : 1'h0;
assign GEN_21 = T_243 ? GEN_17 : stop;
assign GEN_22 = T_243 ? GEN_18 : GEN_15;
assign GEN_23 = T_243 ? GEN_19 : GEN_13;
assign T_251 = accept & done;
assign GEN_24 = io_op_bits_stb ? io_ctrl_fmt_proto : ctrl_fmt_proto;
assign GEN_25 = io_op_bits_stb ? io_ctrl_fmt_endian : ctrl_fmt_endian;
assign GEN_26 = io_op_bits_stb ? io_ctrl_fmt_iodir : ctrl_fmt_iodir;
assign T_254 = 1'h0 == io_op_bits_fn;
assign T_257 = io_op_bits_cnt == 8'h0;
assign GEN_27 = T_254 ? buffer_in : T_180;
assign GEN_28 = T_254 ? cinv : GEN_23;
assign GEN_29 = T_254 ? 1'h1 : GEN_22;
assign GEN_30 = T_254 ? T_257 : T_212;
assign GEN_32 = io_op_bits_stb ? io_ctrl_sck_pol : GEN_28;
assign GEN_33 = io_op_bits_stb ? io_ctrl_sck_div : ctrl_sck_div;
assign GEN_34 = io_op_bits_stb ? io_ctrl_sck_pol : ctrl_sck_pol;
assign GEN_35 = io_op_bits_stb ? io_ctrl_sck_pha : ctrl_sck_pha;
assign GEN_36 = io_op_bits_fn ? GEN_32 : GEN_28;
assign GEN_37 = io_op_bits_fn ? GEN_33 : ctrl_sck_div;
assign GEN_38 = io_op_bits_fn ? GEN_34 : ctrl_sck_pol;
assign GEN_39 = io_op_bits_fn ? GEN_35 : ctrl_sck_pha;
assign GEN_40 = io_op_valid ? {{4'd0}, io_op_bits_cnt} : GEN_16;
assign GEN_41 = io_op_valid ? GEN_24 : ctrl_fmt_proto;
assign GEN_42 = io_op_valid ? GEN_25 : ctrl_fmt_endian;
assign GEN_43 = io_op_valid ? GEN_26 : ctrl_fmt_iodir;
assign GEN_44 = io_op_valid ? T_254 : xfr;
assign GEN_45 = io_op_valid ? GEN_27 : T_180;
assign GEN_46 = io_op_valid ? GEN_36 : GEN_23;
assign GEN_47 = io_op_valid ? GEN_29 : GEN_22;
assign GEN_48 = io_op_valid ? GEN_30 : T_212;
assign GEN_49 = io_op_valid ? GEN_37 : ctrl_sck_div;
assign GEN_50 = io_op_valid ? GEN_38 : ctrl_sck_pol;
assign GEN_51 = io_op_valid ? GEN_39 : ctrl_sck_pha;
assign GEN_53 = T_251 ? GEN_40 : GEN_16;
assign GEN_54 = T_251 ? GEN_41 : ctrl_fmt_proto;
assign GEN_55 = T_251 ? GEN_42 : ctrl_fmt_endian;
assign GEN_56 = T_251 ? GEN_43 : ctrl_fmt_iodir;
assign GEN_57 = T_251 ? GEN_44 : xfr;
assign GEN_58 = T_251 ? GEN_45 : T_180;
assign GEN_59 = T_251 ? GEN_46 : GEN_23;
assign GEN_60 = T_251 ? GEN_47 : GEN_22;
assign GEN_61 = T_251 ? GEN_48 : T_212;
assign GEN_62 = T_251 ? GEN_49 : ctrl_sck_div;
assign GEN_63 = T_251 ? GEN_50 : ctrl_sck_pol;
assign GEN_64 = T_251 ? GEN_51 : ctrl_sck_pha;
always @(posedge clock or posedge reset)
if (reset) begin
ctrl_sck_div <= 12'b0;
ctrl_sck_pol <= 1'b0;
ctrl_sck_pha <= 1'b0;
ctrl_fmt_proto <= 2'b0;
ctrl_fmt_endian <= 1'b0;
ctrl_fmt_iodir <= 1'b0;
setup_d <= 1'b0;
tcnt <= 12'b0;
sck <= 1'b0;
buffer <= 8'b0;
xfr <= 1'b0;
end
else begin
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_div <= io_ctrl_sck_div;
end
end
end
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_pol <= io_ctrl_sck_pol;
end
end
end
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_pha <= io_ctrl_sck_pha;
end
end
end
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_proto <= io_ctrl_fmt_proto;
end
end
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_endian <= io_ctrl_fmt_endian;
end
end
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_iodir <= io_ctrl_fmt_iodir;
end
end
end
setup_d <= setup;
if (sched) begin
tcnt <= ctrl_sck_div;
end else begin
tcnt <= decr;
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
sck <= io_ctrl_sck_pol;
end else begin
if (T_254) begin
sck <= cinv;
end else begin
if (T_243) begin
if (T_248) begin
sck <= ctrl_sck_pol;
end else begin
if (T_234) begin
if (beat) begin
if (xfr) begin
sck <= T_237;
end
end
end
end
end else begin
if (T_234) begin
if (beat) begin
if (xfr) begin
sck <= T_237;
end
end
end
end
end
end
end else begin
if (T_254) begin
sck <= cinv;
end else begin
if (T_243) begin
if (T_248) begin
sck <= ctrl_sck_pol;
end else begin
if (T_234) begin
if (beat) begin
if (xfr) begin
sck <= T_237;
end
end
end
end
end else begin
if (T_234) begin
if (beat) begin
if (xfr) begin
sck <= T_237;
end
end
end
end
end
end
end else begin
if (T_243) begin
if (T_248) begin
sck <= ctrl_sck_pol;
end else begin
sck <= GEN_13;
end
end else begin
sck <= GEN_13;
end
end
end else begin
if (T_243) begin
if (T_248) begin
sck <= ctrl_sck_pol;
end else begin
sck <= GEN_13;
end
end else begin
sck <= GEN_13;
end
end
if (T_251) begin
if (io_op_valid) begin
if (T_254) begin
if (T_135) begin
buffer <= io_op_bits_data;
end else begin
buffer <= T_150;
end
end else begin
buffer <= T_180;
end
end else begin
buffer <= T_180;
end
end else begin
buffer <= T_180;
end
if (T_251) begin
if (io_op_valid) begin
xfr <= T_254;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
cref <= 1'h1;
end else begin
if (T_234) begin
if (beat) begin
cref <= T_236;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
txd <= 4'h0;
end else begin
if (setup) begin
txd <= T_194;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
done <= 1'h1;
end else begin
if (T_251) begin
if (io_op_valid) begin
if (T_254) begin
done <= T_257;
end else begin
done <= T_212;
end
end else begin
done <= T_212;
end
end else begin
done <= T_212;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
T_119 <= 1'h0;
end else begin
T_119 <= sample;
end
always @(posedge clock or posedge reset)
if (reset) begin
T_120 <= 1'h0;
end else begin
T_120 <= T_119;
end
always @(posedge clock or posedge reset)
if (reset) begin
sample_d <= 1'h0;
end else begin
sample_d <= T_120;
end
always @(posedge clock or posedge reset)
if (reset) begin
T_122 <= 1'h0;
end else begin
T_122 <= last;
end
always @(posedge clock or posedge reset)
if (reset) begin
T_123 <= 1'h0;
end else begin
T_123 <= T_122;
end
always @(posedge clock or posedge reset)
if (reset) begin
last_d <= 1'h0;
end else begin
last_d <= T_123;
end
always @(posedge clock or posedge reset)
if (reset) begin
scnt <= 8'h0;
end else begin
scnt <= GEN_53[7:0];
end
endmodule |
module fpgaTop(
input wire sys0_clkp, // sys0 Clock +
input wire sys0_clkn, // sys0 Clock -
input wire pci0_clkp, // PCIe Clock +
input wire pci0_clkn, // PCIe Clock -
input wire pci0_reset_n, // PCIe Reset
output wire [7:0] pci_exp_txp, // PCIe lanes...
output wire [7:0] pci_exp_txn,
input wire [7:0] pci_exp_rxp,
input wire [7:0] pci_exp_rxn,
output wire [2:0] led, // LEDs ml555
input wire ppsExtIn, // PPS in
output wire ppsOut // PPS out
);
// Instance and connect mkFTop...
mkFTop_sp605 ftop(
.sys0_clkp (sys0_clkp),
.sys0_clkn (sys0_clkn),
.pci0_clkp (pci0_clkp),
.pci0_clkn (pci0_clkn),
.pci0_rstn (pci0_reset_n),
.pcie_rxp_i (pci_exp_rxp),
.pcie_rxn_i (pci_exp_rxn),
.pcie_txp (pci_exp_txp),
.pcie_txn (pci_exp_txn),
.led (led),
.gps_ppsSyncIn_x (ppsExtIn),
.gps_ppsSyncOut (ppsOut)
);
endmodule |
module Sobel_cache (
input clk,
input rst,
input start,
input [ADD_WIDTH-1:0] base_add,
input [13:0] rdaddress,
output wire [12:0] valid_lines,
input free_line,
output wire [ 7:0] q,
output wire [ADD_WIDTH-1:0] ram_r_address,
input ram_r_waitrequest,
input ram_r_readdatavalid,
output wire [BYTE_ENABLE_WIDTH-1:0] ram_r_byteenable,
output wire ram_r_read,
input [DATA_WIDTH-1:0] ram_r_readdata,
output wire [BURST_WIDTH_R-1:0] ram_r_burstcount
);
parameter DATA_WIDTH=32;
parameter ADD_WIDTH = 32;
parameter BYTE_ENABLE_WIDTH = 4;
parameter BURST_WIDTH_R = 6;
parameter MAX_BURST_COUNT_R = 32;
reg [ADD_WIDTH-1:0] read_address;
reg [ADD_WIDTH-1:0] write_address;
reg [12:0] used_cache_pixels;
reg [31:0] in_n;
always @(posedge clk or posedge rst) begin
if (rst == 1) begin
in_n <= 0;
end else begin
if (start == 1) begin
in_n <= 384000;
end else begin
if (read_burst_end == 1) begin
in_n <= in_n - MAX_BURST_COUNT_R;
end
end
end
end
always @(posedge clk) begin
if (start == 1) begin
read_address <= base_add;
end else begin
if (read_burst_end == 1) begin
read_address <= read_address + MAX_BURST_COUNT_R * BYTE_ENABLE_WIDTH;
end
end
end
// reg [ 3:0] valid;
always @(posedge clk) begin
if (start == 1) begin
used_cache_pixels <= 0;
end else begin
if (read_complete == 1) begin
if (free_line == 0) begin
used_cache_pixels <= used_cache_pixels + 1;
end else begin
used_cache_pixels <= used_cache_pixels - 799;
end
end else begin
if (free_line == 1) begin
used_cache_pixels <= used_cache_pixels - 800;
end
end
end
end
assign valid_lines = used_cache_pixels;
reg [31:0] reads_pending;
always @ (posedge clk) begin
if (start == 1) begin
reads_pending <= 0;
end else begin
if(read_burst_end == 1) begin
if(read_complete == 0) begin
reads_pending <= reads_pending + MAX_BURST_COUNT_R;
end else begin
reads_pending <= reads_pending + MAX_BURST_COUNT_R - 1;
end
end else begin
if(read_complete == 0) begin
reads_pending <= reads_pending;
end else begin
reads_pending <= reads_pending - 1;
end
end
end
end
reg [31:0] next_r;
always @ (posedge clk) begin
if (start == 1) begin
next_r <= 0;
end else begin
if(read_burst_end == 1) begin
next_r <= 0;
end else begin
if (ram_r_read == 1) begin
next_r <= 1;
end
end
end
end
always @(posedge clk) begin
if (start == 1) begin
write_address <= 0;
end else begin
if (read_complete == 1) begin
if (write_address == 7999) begin
write_address <= 0;
end else begin
write_address <= write_address + 1;
end
end
end
end
altsyncram altsyncram_component (
.clock0 (clk),
.data_a (ram_r_readdata[7:0]),
.address_a (write_address),
.wren_a (read_complete),
.address_b (rdaddress),
.q_b (q),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({8{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 8192,
altsyncram_component.numwords_b = 8192,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 13,
altsyncram_component.widthad_b = 13,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1;
assign read_complete = (ram_r_readdatavalid == 1);
assign read_burst_end = (ram_r_waitrequest == 0) & (next_r == 1);
assign too_many_reads_pending = (reads_pending + used_cache_pixels) > (8000 - MAX_BURST_COUNT_R);
assign ram_r_address = read_address;
assign ram_r_read = (too_many_reads_pending == 0) & (in_n != 0);
assign ram_r_byteenable = {BYTE_ENABLE_WIDTH{1'b1}};
assign ram_r_burstcount = MAX_BURST_COUNT_R;
endmodule |
module lf_edge_detect(input clk, input [7:0] adc_d, input [7:0] lf_ed_threshold,
output [7:0] max, output [7:0] min,
output [7:0] high_threshold, output [7:0] highz_threshold,
output [7:0] lowz_threshold, output [7:0] low_threshold,
output edge_state, output edge_toggle);
min_max_tracker tracker(clk, adc_d, lf_ed_threshold, min, max);
// auto-tune
assign high_threshold = (max + min) / 2 + (max - min) / 4;
assign highz_threshold = (max + min) / 2 + (max - min) / 8;
assign lowz_threshold = (max + min) / 2 - (max - min) / 8;
assign low_threshold = (max + min) / 2 - (max - min) / 4;
// heuristic to see if it makes sense to try to detect an edge
wire enabled =
(high_threshold > highz_threshold)
& (highz_threshold > lowz_threshold)
& (lowz_threshold > low_threshold)
& ((high_threshold - highz_threshold) > 8)
& ((highz_threshold - lowz_threshold) > 16)
& ((lowz_threshold - low_threshold) > 8);
// Toggle the output with hysteresis
// Set to high if the ADC value is above the threshold
// Set to low if the ADC value is below the threshold
reg is_high = 0;
reg is_low = 0;
reg is_zero = 0;
reg trigger_enabled = 1;
reg output_edge = 0;
reg output_state;
always @(posedge clk)
begin
is_high <= (adc_d >= high_threshold);
is_low <= (adc_d <= low_threshold);
is_zero <= ((adc_d > lowz_threshold) & (adc_d < highz_threshold));
end
// all edges detection
always @(posedge clk)
if (enabled) begin
// To enable detecting two consecutive peaks at the same level
// (low or high) we check whether or not we went back near 0 in-between.
// This extra check is necessary to prevent from noise artifacts
// around the threshold values.
if (trigger_enabled & (is_high | is_low)) begin
output_edge <= ~output_edge;
trigger_enabled <= 0;
end else
trigger_enabled <= trigger_enabled | is_zero;
end
// edge states
always @(posedge clk)
if (enabled) begin
if (is_high)
output_state <= 1'd1;
else if (is_low)
output_state <= 1'd0;
end
assign edge_state = output_state;
assign edge_toggle = output_edge;
endmodule |
module sky130_fd_sc_lp__sdfrtp_ov2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_lp__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule |
module top();
// Inputs are registered
reg A_N;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A_N = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A_N = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A_N = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A_N = 1'bx;
end
sky130_fd_sc_hdll__and3b dut (.A_N(A_N), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule |
module sky130_fd_sc_hdll__or3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A, C );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule |
module sky130_fd_sc_hd__nor4b (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D_N ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module wrap_ref_chroma (
clk ,
rstn ,
wrif_en_i ,
wrif_addr_i ,
wrif_data_i ,
rdif_en_i ,
rdif_addr_i ,
rdif_pdata_o
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input [1-1:0] clk ; // clk signal
input [1-1:0] rstn ; // asynchronous reset
input [1-1:0] wrif_en_i ; // write enabel signal
input [6-1:0] wrif_addr_i ; // mem addr (0 - 95)
input [48*`PIXEL_WIDTH-1:0] wrif_data_i ; // write pixel data (8 pixels)
input [1-1:0] rdif_en_i ; // read referrence pixels enable signale
input [6-1:0] rdif_addr_i ; // search window x position (0 - 32 )
output [48*`PIXEL_WIDTH-1:0] rdif_pdata_o ; // referrence pixles data
// ********************************************
//
// Wire DECLARATION
//
// ********************************************
wire [6-1:0] ref_addr;
assign ref_addr = (wrif_en_i) ? wrif_addr_i : rdif_addr_i;
// ********************************************
//
// MEM INSTANCE DECLARATION
//
// ********************************************
rf_1p #(.Addr_Width(6),.Word_Width(`PIXEL_WIDTH*48))
wrap (
.clk (clk),
.cen_i(1'b0),
.wen_i(~wrif_en_i),
.addr_i(ref_addr),
.data_i(wrif_data_i),
.data_o(rdif_pdata_o)
);
endmodule |
module LUT4(input A, B, C, D, output Z);
parameter INIT = "0x0000";
`include "parse_init.vh"
localparam initp = parse_init(INIT);
wire [7:0] s3 = D ? initp[15:8] : initp[7:0];
wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0];
wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0];
assign Z = A ? s1[1] : s1[0];
// Per-input delay differences are considered 'interconnect'
// so not known yet
specify
(A => Z) = 233;
(B => Z) = 233;
(C => Z) = 233;
(D => Z) = 233;
endspecify
endmodule |
module \$__ABC9_LUT5 (input SEL, D, C, B, A, output Z);
specify
(SEL => Z) = 171;
(D => Z) = 303;
(C => Z) = 311;
(B => Z) = 309;
(A => Z) = 306;
endspecify
endmodule |
module WIDEFN9(input A0, B0, C0, D0, A1, B1, C1, D1, SEL, output Z);
parameter INIT0 = "0x0000";
parameter INIT1 = "0x0000";
wire z0, z1;
LUT4 #(.INIT(INIT0)) lut4_0 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(z0));
LUT4 #(.INIT(INIT1)) lut4_1 (.A(A1), .B(B1), .C(C1), .D(D1), .Z(z1));
assign Z = SEL ? z1 : z0;
endmodule |
module INV(input A, output Z);
assign Z = !A;
specify
(A => Z) = 10;
endspecify
endmodule |
module BB(input T, I, output O,
(* iopad_external_pin *) inout B);
assign B = T ? 1'bz : O;
assign I = B;
endmodule |
module IB(
(* iopad_external_pin *) input I,
output O);
assign O = I;
endmodule |
module OB(input I,
(* iopad_external_pin *) output O);
assign O = I;
endmodule |
module OBZ(input I, T,
(* iopad_external_pin *) output O);
assign O = T ? 1'bz : I;
endmodule |
module VLO(output Z);
assign Z = 1'b0;
endmodule |
module VHI(output Z);
assign Z = 1'b1;
endmodule |
module FD1P3BX(input D, CK, SP, PD, output reg Q);
parameter GSR = "DISABLED";
initial Q = 1'b1;
always @(posedge CK or posedge PD)
if (PD)
Q <= 1'b1;
else if (SP)
Q <= D;
specify
$setup(D, posedge CK, 0);
$setup(SP, posedge CK, 212);
$setup(PD, posedge CK, 224);
`ifndef YOSYS
if (PD) (posedge CLK => (Q : 1)) = 0;
`else
if (PD) (PD => Q) = 0; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
if (!PD && SP) (posedge CK => (Q : D)) = 336;
endspecify
endmodule |
module FD1P3DX(input D, CK, SP, CD, output reg Q);
parameter GSR = "DISABLED";
initial Q = 1'b0;
always @(posedge CK or posedge CD)
if (CD)
Q <= 1'b0;
else if (SP)
Q <= D;
specify
$setup(D, posedge CK, 0);
$setup(SP, posedge CK, 212);
$setup(CD, posedge CK, 224);
`ifndef YOSYS
if (CD) (posedge CLK => (Q : 0)) = 0;
`else
if (CD) (CD => Q) = 0; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
if (!CD && SP) (posedge CK => (Q : D)) = 336;
endspecify
endmodule |
module FD1P3IX(input D, CK, SP, CD, output reg Q);
parameter GSR = "DISABLED";
initial Q = 1'b0;
always @(posedge CK)
if (CD)
Q <= 1'b0;
else if (SP)
Q <= D;
specify
$setup(D, posedge CK, 0);
$setup(SP, posedge CK, 212);
$setup(CD, posedge CK, 224);
if (!CD && SP) (posedge CK => (Q : D)) = 336;
endspecify
endmodule |
module FD1P3JX(input D, CK, SP, PD, output reg Q);
parameter GSR = "DISABLED";
initial Q = 1'b1;
always @(posedge CK)
if (PD)
Q <= 1'b1;
else if (SP)
Q <= D;
specify
$setup(D, posedge CK, 0);
$setup(SP, posedge CK, 212);
$setup(PD, posedge CK, 224);
if (!PD && SP) (posedge CK => (Q : D)) = 336;
endspecify
endmodule |
module LUT4_3(input A, B, C, D, output Z, Z3);
parameter INIT = "0x0000";
`include "parse_init.vh"
localparam initp = parse_init(INIT);
wire [7:0] s3 = D ? initp[15:8] : initp[7:0];
wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0];
wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0];
assign Z = A ? s1[1] : s1[0];
wire [3:0] s2_3 = C ? initp[ 7:4] : initp[3:0];
wire [1:0] s1_3 = B ? s2_3[ 3:2] : s2_3[1:0];
assign Z3 = A ? s1_3[1] : s1_3[0];
endmodule |
module CCU2(
(* abc9_carry *) input CIN,
input A1, B1, C1, D1, A0, B0, C0, D0,
output S1, S0,
(* abc9_carry *) output COUT);
parameter INJECT = "YES";
parameter INIT0 = "0x0000";
parameter INIT1 = "0x1111";
localparam inject_p = (INJECT == "YES") ? 1'b1 : 1'b0;
wire LUT3_0, LUT4_0, LUT3_1, LUT4_1, carry_0;
LUT4_3 #(.INIT(INIT0)) lut0 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0), .Z3(LUT3_0));
LUT4_3 #(.INIT(INIT1)) lut1 (.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1), .Z3(LUT3_1));
assign S0 = LUT4_0 ^ (CIN & ~inject_p);
assign carry_0 = LUT4_0 ? CIN : (LUT3_0 & ~inject_p);
assign S1 = LUT4_1 ^ (carry_0 & ~inject_p);
assign COUT = LUT4_1 ? carry_0 : (LUT3_1 & ~inject_p);
specify
(A0 => S0) = 233;
(B0 => S0) = 233;
(C0 => S0) = 233;
(D0 => S0) = 233;
(CIN => S0) = 228;
(A0 => S1) = 481;
(B0 => S1) = 481;
(C0 => S1) = 481;
(D0 => S1) = 481;
(A1 => S1) = 233;
(B1 => S1) = 233;
(C1 => S1) = 233;
(D1 => S1) = 233;
(CIN => S1) = 307;
(A0 => COUT) = 347;
(B0 => COUT) = 347;
(C0 => COUT) = 347;
(D0 => COUT) = 347;
(A1 => COUT) = 347;
(B1 => COUT) = 347;
(C1 => COUT) = 347;
(D1 => COUT) = 347;
(CIN => COUT) = 59;
endspecify
endmodule |
module OXIDE_FF(input CLK, LSR, CE, DI, M, output reg Q);
parameter GSR = "ENABLED";
parameter [127:0] CEMUX = "1";
parameter CLKMUX = "CLK";
parameter LSRMUX = "LSR";
parameter REGDDR = "DISABLED";
parameter SRMODE = "LSR_OVER_CE";
parameter REGSET = "RESET";
parameter [127:0] LSRMODE = "LSR";
wire muxce;
generate
case (CEMUX)
"1": assign muxce = 1'b1;
"0": assign muxce = 1'b0;
"INV": assign muxce = ~CE;
default: assign muxce = CE;
endcase
endgenerate
wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
wire srval;
generate
if (LSRMODE == "PRLD")
assign srval = M;
else
assign srval = (REGSET == "SET") ? 1'b1 : 1'b0;
endgenerate
initial Q = srval;
generate
if (REGDDR == "ENABLED") begin
if (SRMODE == "ASYNC") begin
always @(posedge muxclk, negedge muxclk, posedge muxlsr)
if (muxlsr)
Q <= srval;
else if (muxce)
Q <= DI;
end else begin
always @(posedge muxclk, negedge muxclk)
if (muxlsr)
Q <= srval;
else if (muxce)
Q <= DI;
end
end else begin
if (SRMODE == "ASYNC") begin
always @(posedge muxclk, posedge muxlsr)
if (muxlsr)
Q <= srval;
else if (muxce)
Q <= DI;
end else begin
always @(posedge muxclk)
if (muxlsr)
Q <= srval;
else if (muxce)
Q <= DI;
end
end
endgenerate
endmodule |
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