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module beh_vlog_ff_ce_clr_v8_3 (Q, C, CE, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CE, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q <= 1'b0;
else if (CE)
Q <= #FLOP_DELAY D;
endmodule |
module write_netlist_v8_3
#(
parameter C_AXI_TYPE = 0
)
(
S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,
w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,
S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c
);
input S_ACLK;
input S_ARESETN;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input S_AXI_BREADY;
input w_last_c;
input bready_timeout_c;
output aw_ready_r;
output S_AXI_WREADY;
output S_AXI_BVALID;
output S_AXI_WR_EN;
output addr_en_c;
output incr_addr_c;
output bvalid_c;
//-------------------------------------------------------------------------
//AXI LITE
//-------------------------------------------------------------------------
generate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm
wire w_ready_r_7;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSignal_bvalid_c;
wire NlwRenamedSignal_incr_addr_c;
wire present_state_FSM_FFd3_13;
wire present_state_FSM_FFd2_14;
wire present_state_FSM_FFd1_15;
wire present_state_FSM_FFd4_16;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd4_In1_21;
wire [0:0] Mmux_aw_ready_c ;
begin
assign
S_AXI_WREADY = w_ready_r_7,
S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,
S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,
incr_addr_c = NlwRenamedSignal_incr_addr_c,
bvalid_c = NlwRenamedSignal_bvalid_c;
assign NlwRenamedSignal_incr_addr_c = 1'b0;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
aw_ready_r_2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
w_ready_r (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_7)
);
beh_vlog_ff_pre_v8_3 #(
.INIT (1'b1))
present_state_FSM_FFd4 (
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_16)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd3 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_13)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_15)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000055554440))
present_state_FSM_FFd3_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000088880800))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_AWVALID),
.I1 ( S_AXI_WVALID),
.I2 ( bready_timeout_c),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000AAAA2000))
Mmux_addr_en_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_WVALID),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( addr_en_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hF5F07570F5F05500))
Mmux_w_ready_c_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( w_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd3_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd1_15),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( present_state_FSM_FFd3_13),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSignal_bvalid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h2F0F27072F0F2200))
present_state_FSM_FFd4_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( present_state_FSM_FFd4_In1_21)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000F8))
present_state_FSM_FFd4_In2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_In1_21),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h7535753575305500))
Mmux_aw_ready_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_WVALID),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 ( present_state_FSM_FFd2_14),
.O ( Mmux_aw_ready_c[0])
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000F8))
Mmux_aw_ready_c_0_2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( Mmux_aw_ready_c[0]),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( aw_ready_c)
);
end
end
endgenerate
//---------------------------------------------------------------------
// AXI FULL
//---------------------------------------------------------------------
generate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm
wire w_ready_r_8;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSig_OI_bvalid_c;
wire present_state_FSM_FFd1_16;
wire present_state_FSM_FFd4_17;
wire present_state_FSM_FFd3_18;
wire present_state_FSM_FFd2_19;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd2_In1_24;
wire present_state_FSM_FFd4_In1_25;
wire N2;
wire N4;
begin
assign
S_AXI_WREADY = w_ready_r_8,
bvalid_c = NlwRenamedSig_OI_bvalid_c,
S_AXI_BVALID = 1'b0;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
aw_ready_r_2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
w_ready_r
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_8)
);
beh_vlog_ff_pre_v8_3 #(
.INIT (1'b1))
present_state_FSM_FFd4
(
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_17)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd3
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_18)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_19)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_16)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000005540))
present_state_FSM_FFd3_In1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd4_17),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hBF3FBB33AF0FAA00))
Mmux_aw_ready_c_0_2
(
.I0 ( S_AXI_BREADY),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd1_16),
.I4 ( present_state_FSM_FFd4_17),
.I5 ( NlwRenamedSig_OI_bvalid_c),
.O ( aw_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hAAAAAAAA20000000))
Mmux_addr_en_c_0_1
(
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( S_AXI_WVALID),
.I4 ( w_last_c),
.I5 ( present_state_FSM_FFd4_17),
.O ( addr_en_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_19),
.I2 ( present_state_FSM_FFd3_18),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( S_AXI_WR_EN)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000002220))
Mmux_incr_addr_c_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( incr_addr_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000008880))
Mmux_aw_ready_c_0_11
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSig_OI_bvalid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000000000D5C0))
present_state_FSM_FFd2_In1
(
.I0 ( w_last_c),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In1_24)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFFFFAAAA08AAAAAA))
present_state_FSM_FFd2_In2
(
.I0 ( present_state_FSM_FFd2_19),
.I1 ( S_AXI_AWVALID),
.I2 ( bready_timeout_c),
.I3 ( w_last_c),
.I4 ( S_AXI_WVALID),
.I5 ( present_state_FSM_FFd2_In1_24),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00C0004000C00000))
present_state_FSM_FFd4_In1
(
.I0 ( S_AXI_AWVALID),
.I1 ( w_last_c),
.I2 ( S_AXI_WVALID),
.I3 ( bready_timeout_c),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( present_state_FSM_FFd4_In1_25)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000FFFF88F8))
present_state_FSM_FFd4_In2
(
.I0 ( present_state_FSM_FFd1_16),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( S_AXI_AWVALID),
.I4 ( present_state_FSM_FFd4_In1_25),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000007))
Mmux_w_ready_c_0_SW0
(
.I0 ( w_last_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N2)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFABAFABAFAAAF000))
Mmux_w_ready_c_0_Q
(
.I0 ( N2),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd4_17),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( w_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000008))
Mmux_aw_ready_c_0_11_SW0
(
.I0 ( bready_timeout_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N4)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1
(
.I0 ( w_last_c),
.I1 ( N4),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 ( present_state_FSM_FFd1_16),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
end
end
endgenerate
endmodule |
module read_netlist_v8_3 #(
parameter C_AXI_TYPE = 1,
parameter C_ADDRB_WIDTH = 12
) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,
S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,
S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,
S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);
input S_AXI_R_LAST_INT;
input S_ACLK;
input S_ARESETN;
input S_AXI_ARVALID;
input S_AXI_RREADY;
output S_AXI_INCR_ADDR;
output S_AXI_ADDR_EN;
output S_AXI_SINGLE_TRANS;
output S_AXI_MUX_SEL;
output S_AXI_R_LAST;
output S_AXI_ARREADY;
output S_AXI_RLAST;
output S_AXI_RVALID;
output S_AXI_RD_EN;
input [7:0] S_AXI_ARLEN;
wire present_state_FSM_FFd1_13 ;
wire present_state_FSM_FFd2_14 ;
wire gaxi_full_sm_outstanding_read_r_15 ;
wire gaxi_full_sm_ar_ready_r_16 ;
wire gaxi_full_sm_r_last_r_17 ;
wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ;
wire gaxi_full_sm_r_valid_c ;
wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ;
wire gaxi_full_sm_ar_ready_c ;
wire gaxi_full_sm_outstanding_read_c ;
wire NlwRenamedSig_OI_S_AXI_R_LAST ;
wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ;
wire present_state_FSM_FFd2_In ;
wire present_state_FSM_FFd1_In ;
wire Mmux_S_AXI_R_LAST13 ;
wire N01 ;
wire N2 ;
wire Mmux_gaxi_full_sm_ar_ready_c11 ;
wire N4 ;
wire N8 ;
wire N9 ;
wire N10 ;
wire N11 ;
wire N12 ;
wire N13 ;
assign
S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,
S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,
S_AXI_RLAST = gaxi_full_sm_r_last_r_17,
S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_outstanding_read_r (
.C (S_ACLK),
.CLR(S_ARESETN),
.D(gaxi_full_sm_outstanding_read_c),
.Q(gaxi_full_sm_outstanding_read_r_15)
);
beh_vlog_ff_ce_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_r_valid_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (gaxi_full_sm_r_valid_c),
.Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_ar_ready_r (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (gaxi_full_sm_ar_ready_c),
.Q (gaxi_full_sm_ar_ready_r_16)
);
beh_vlog_ff_ce_clr_v8_3 #(
.INIT(1'b0))
gaxi_full_sm_r_last_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (NlwRenamedSig_OI_S_AXI_R_LAST),
.Q (gaxi_full_sm_r_last_r_17)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (present_state_FSM_FFd1_In),
.Q (present_state_FSM_FFd1_13)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000000000000B))
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (
.I0 ( S_AXI_RREADY),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000008))
Mmux_S_AXI_SINGLE_TRANS11 (
.I0 (S_AXI_ARVALID),
.I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_SINGLE_TRANS)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000004))
Mmux_S_AXI_ADDR_EN11 (
.I0 (present_state_FSM_FFd1_13),
.I1 (S_AXI_ARVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_ADDR_EN)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hECEE2022EEEE2022))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_ARVALID),
.I1 ( present_state_FSM_FFd1_13),
.I2 ( S_AXI_RREADY),
.I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000044440444))
Mmux_S_AXI_R_LAST131 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_RREADY),
.I5 (1'b0),
.O ( Mmux_S_AXI_R_LAST13)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h4000FFFF40004000))
Mmux_S_AXI_INCR_ADDR11 (
.I0 ( S_AXI_R_LAST_INT),
.I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( Mmux_S_AXI_R_LAST13),
.O ( S_AXI_INCR_ADDR)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000FE))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (
.I0 ( S_AXI_ARLEN[2]),
.I1 ( S_AXI_ARLEN[1]),
.I2 ( S_AXI_ARLEN[0]),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N01)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000001))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (
.I0 ( S_AXI_ARLEN[7]),
.I1 ( S_AXI_ARLEN[6]),
.I2 ( S_AXI_ARLEN[5]),
.I3 ( S_AXI_ARLEN[4]),
.I4 ( S_AXI_ARLEN[3]),
.I5 ( N01),
.O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000007))
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 ( 1'b0),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N2)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0020000002200200))
Mmux_gaxi_full_sm_outstanding_read_c1 (
.I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd1_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( gaxi_full_sm_outstanding_read_r_15),
.I5 ( N2),
.O ( gaxi_full_sm_outstanding_read_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000004555))
Mmux_gaxi_full_sm_ar_ready_c12 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( Mmux_gaxi_full_sm_ar_ready_c11)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000EF))
Mmux_S_AXI_R_LAST11_SW0 (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N4)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFCAAFC0A00AA000A))
Mmux_S_AXI_R_LAST11 (
.I0 ( S_AXI_ARVALID),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( N4),
.I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.O ( gaxi_full_sm_r_valid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000AAAAAA08))
S_AXI_MUX_SEL1 (
.I0 (present_state_FSM_FFd1_13),
.I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (S_AXI_RREADY),
.I3 (present_state_FSM_FFd2_14),
.I4 (gaxi_full_sm_outstanding_read_r_15),
.I5 (1'b0),
.O (S_AXI_MUX_SEL)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hF3F3F755A2A2A200))
Mmux_S_AXI_RD_EN11 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 ( S_AXI_RREADY),
.I3 ( gaxi_full_sm_outstanding_read_r_15),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( S_AXI_ARVALID),
.O ( S_AXI_RD_EN)
);
beh_vlog_muxf7_v8_3 present_state_FSM_FFd1_In3 (
.I0 ( N8),
.I1 ( N9),
.S ( present_state_FSM_FFd1_13),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000005410F4F0))
present_state_FSM_FFd1_In3_F (
.I0 ( S_AXI_RREADY),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( S_AXI_ARVALID),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( 1'b0),
.O ( N8)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000072FF7272))
present_state_FSM_FFd1_In3_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N9)
);
beh_vlog_muxf7_v8_3 Mmux_gaxi_full_sm_ar_ready_c14 (
.I0 ( N10),
.I1 ( N11),
.S ( present_state_FSM_FFd1_13),
.O ( gaxi_full_sm_ar_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000FFFF88A8))
Mmux_gaxi_full_sm_ar_ready_c14_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( Mmux_gaxi_full_sm_ar_ready_c11),
.I5 ( 1'b0),
.O ( N10)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000008D008D8D))
Mmux_gaxi_full_sm_ar_ready_c14_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N11)
);
beh_vlog_muxf7_v8_3 Mmux_S_AXI_R_LAST1 (
.I0 ( N12),
.I1 ( N13),
.S ( present_state_FSM_FFd1_13),
.O ( NlwRenamedSig_OI_S_AXI_R_LAST)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000088088888))
Mmux_S_AXI_R_LAST1_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N12)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000E400E4E4))
Mmux_S_AXI_R_LAST1_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( S_AXI_R_LAST_INT),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N13)
);
endmodule |
module blk_mem_axi_write_wrapper_beh_v8_3
# (
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface
parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full;
parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
parameter C_WRITE_DEPTH_A = 0,
parameter C_AXI_AWADDR_WIDTH = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_WDATA_WIDTH = 32,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
// AXI OUTSTANDING WRITES
parameter C_AXI_OS_WR = 2
)
(
// AXI Global Signals
input S_ACLK,
input S_ARESETN,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,
input [8-1:0] S_AXI_AWLEN,
input [2:0] S_AXI_AWSIZE,
input [1:0] S_AXI_AWBURST,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
input S_AXI_WVALID,
output S_AXI_WREADY,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,
output S_AXI_BVALID,
input S_AXI_BREADY,
// Signals for BMG interface
output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,
output S_AXI_WR_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:
((C_AXI_WDATA_WIDTH==16)?1:
((C_AXI_WDATA_WIDTH==32)?2:
((C_AXI_WDATA_WIDTH==64)?3:
((C_AXI_WDATA_WIDTH==128)?4:
((C_AXI_WDATA_WIDTH==256)?5:0))))));
wire bvalid_c ;
reg bready_timeout_c = 0;
wire [1:0] bvalid_rd_cnt_c;
reg bvalid_r = 0;
reg [2:0] bvalid_count_r = 0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;
reg [1:0] bvalid_wr_cnt_r = 0;
reg [1:0] bvalid_rd_cnt_r = 0;
wire w_last_c ;
wire addr_en_c ;
wire incr_addr_c ;
wire aw_ready_r ;
wire dec_alen_c ;
reg bvalid_d1_c = 0;
reg [7:0] awlen_cntr_r = 0;
reg [7:0] awlen_int = 0;
reg [1:0] awburst_int = 0;
integer total_bytes = 0;
integer wrap_boundary = 0;
integer wrap_base_addr = 0;
integer num_of_bytes_c = 0;
integer num_of_bytes_r = 0;
// Array to store BIDs
reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;
wire S_AXI_BVALID_axi_wr_fsm;
//-------------------------------------
//AXI WRITE FSM COMPONENT INSTANTIATION
//-------------------------------------
write_netlist_v8_3 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm
(
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
.S_AXI_AWVALID(S_AXI_AWVALID),
.aw_ready_r(aw_ready_r),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_WR_EN(S_AXI_WR_EN),
.w_last_c(w_last_c),
.bready_timeout_c(bready_timeout_c),
.addr_en_c(addr_en_c),
.incr_addr_c(incr_addr_c),
.bvalid_c(bvalid_c),
.S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm)
);
//Wrap Address boundary calculation
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);
total_bytes = (num_of_bytes_r)*(awlen_int+1);
wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);
wrap_boundary = wrap_base_addr+total_bytes;
end
//-------------------------------------------------------------------------
// BMG address generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awaddr_reg <= 0;
num_of_bytes_r <= 0;
awburst_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);
end else if (incr_addr_c == 1'b1) begin
if (awburst_int == 2'b10) begin
if(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin
awaddr_reg <= wrap_base_addr;
end else begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end
end
end
assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);
//-------------------------------------------------------------------------
// AXI wlast generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awlen_cntr_r <= 0;
awlen_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
end else if (dec_alen_c == 1'b1) begin
awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ;
end
end
end
assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;
assign dec_alen_c = (incr_addr_c | w_last_c);
//-------------------------------------------------------------------------
// Generation of bvalid counter for outstanding transactions
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_count_r <= 0;
end else begin
// bvalid_count_r generation
if (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r ;
end else if (bvalid_c == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ;
end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ;
end
end
end
//-------------------------------------------------------------------------
// Generation of bvalid when BID is used
//-------------------------------------------------------------------------
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
bvalid_d1_c <= 0;
end else begin
// Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
//external bvalid signal generation
if (bvalid_d1_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of bvalid when BID is not used
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
end else begin
//external bvalid signal generation
if (bvalid_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of Bready timeout
//-------------------------------------------------------------------------
always @(bvalid_count_r) begin
// bready_timeout_c generation
if(bvalid_count_r == C_AXI_OS_WR-1) begin
bready_timeout_c <= 1'b1;
end else begin
bready_timeout_c <= 1'b0;
end
end
//-------------------------------------------------------------------------
// Generation of BID
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_wr_cnt_r <= 0;
bvalid_rd_cnt_r <= 0;
end else begin
// STORE AWID IN AN ARRAY
if(bvalid_c == 1'b1) begin
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1;
end
// generate BID FROM AWID ARRAY
bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;
S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c];
end
end
assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;
//-------------------------------------------------------------------------
// Storing AWID for generation of BID
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if(S_ARESETN == 1'b1) begin
axi_bid_array[0] = 0;
axi_bid_array[1] = 0;
axi_bid_array[2] = 0;
axi_bid_array[3] = 0;
end else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin
axi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;
end
end
end
endgenerate
assign S_AXI_BVALID = bvalid_r;
assign S_AXI_AWREADY = aw_ready_r;
endmodule |
module blk_mem_axi_read_wrapper_beh_v8_3
# (
//// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_WRITE_WIDTH_A = 4,
parameter C_WRITE_DEPTH_A = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_PIPELINE_STAGES = 0,
parameter C_AXI_ARADDR_WIDTH = 12,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_ADDRB_WIDTH = 12
)
(
//// AXI Global Signals
input S_ACLK,
input S_ARESETN,
//// AXI Full/Lite Slave Read (Read side)
input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,
input [7:0] S_AXI_ARLEN,
input [2:0] S_AXI_ARSIZE,
input [1:0] S_AXI_ARBURST,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
output S_AXI_RLAST,
output S_AXI_RVALID,
input S_AXI_RREADY,
input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,
//// AXI Full/Lite Read Address Signals to BRAM
output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,
output S_AXI_RD_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:
((C_WRITE_WIDTH_A==16)?1:
((C_WRITE_WIDTH_A==32)?2:
((C_WRITE_WIDTH_A==64)?3:
((C_WRITE_WIDTH_A==128)?4:
((C_WRITE_WIDTH_A==256)?5:0))))));
reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;
wire addr_en_c;
wire rd_en_c;
wire incr_addr_c;
wire single_trans_c;
wire dec_alen_c;
wire mux_sel_c;
wire r_last_c;
wire r_last_int_c;
wire [C_ADDRB_WIDTH-1 : 0] araddr_out;
reg [7:0] arlen_int_r=0;
reg [7:0] arlen_cntr=8'h01;
reg [1:0] arburst_int_c=0;
reg [1:0] arburst_int_r=0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;
integer num_of_bytes_c = 0;
integer total_bytes = 0;
integer num_of_bytes_r = 0;
integer wrap_base_addr_r = 0;
integer wrap_boundary_r = 0;
reg [7:0] arlen_int_c=0;
integer total_bytes_c = 0;
integer wrap_base_addr_c = 0;
integer wrap_boundary_c = 0;
assign dec_alen_c = incr_addr_c | r_last_int_c;
read_netlist_v8_3
#(.C_AXI_TYPE (1),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_read_fsm (
.S_AXI_INCR_ADDR(incr_addr_c),
.S_AXI_ADDR_EN(addr_en_c),
.S_AXI_SINGLE_TRANS(single_trans_c),
.S_AXI_MUX_SEL(mux_sel_c),
.S_AXI_R_LAST(r_last_c),
.S_AXI_R_LAST_INT(r_last_int_c),
//// AXI Global Signals
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
//// AXI Full/Lite Slave Read (Read side)
.S_AXI_ARLEN(S_AXI_ARLEN),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RLAST(S_AXI_RLAST),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
//// AXI Full/Lite Read Address Signals to BRAM
.S_AXI_RD_EN(rd_en_c)
);
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);
total_bytes = (num_of_bytes_r)*(arlen_int_r+1);
wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);
wrap_boundary_r = wrap_base_addr_r+total_bytes;
//////// combinatorial from interface
arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);
total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1);
wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);
wrap_boundary_c = wrap_base_addr_c+total_bytes_c;
arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);
end
////-------------------------------------------------------------------------
//// BMG address generation
////-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
araddr_reg <= 0;
arburst_int_r <= 0;
num_of_bytes_r <= 0;
end else begin
if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
if (arburst_int_c == 2'b10) begin
if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin
araddr_reg <= wrap_base_addr_c;
end else begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (addr_en_c == 1'b1) begin
araddr_reg <= S_AXI_ARADDR;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
end else if (incr_addr_c == 1'b1) begin
if (arburst_int_r == 2'b10) begin
if(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin
araddr_reg <= wrap_base_addr_r;
end else begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end
end
end
assign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);
////-----------------------------------------------------------------------
//// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
////-----------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
arlen_cntr <= 8'h01;
arlen_int_r <= 0;
end else begin
if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= S_AXI_ARLEN - 1'b1;
end else if (addr_en_c == 1'b1) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
end else if (dec_alen_c == 1'b1) begin
arlen_cntr <= arlen_cntr - 1'b1 ;
end
else begin
arlen_cntr <= arlen_cntr;
end
end
end
assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;
////------------------------------------------------------------------------
//// AXI FULL FSM
//// Mux Selection of ARADDR
//// ARADDR is driven out from the read fsm based on the mux_sel_c
//// Based on mux_sel either ARADDR is given out or the latched ARADDR is
//// given out to BRAM
////------------------------------------------------------------------------
assign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;
////------------------------------------------------------------------------
//// Assign output signals - AXI FULL FSM
////------------------------------------------------------------------------
assign S_AXI_RD_EN = rd_en_c;
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
S_AXI_RID <= 0;
ar_id_r <= 0;
end else begin
if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin
ar_id_r <= S_AXI_ARID;
end else if (rd_en_c == 1'b1) begin
S_AXI_RID <= ar_id_r;
end
end
end
end
endgenerate
endmodule |
module blk_mem_axi_regs_fwd_v8_3
#(parameter C_DATA_WIDTH = 8
)(
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
wire S_READY_I;
reg M_VALID_I;
reg [1:0] ARESET_D;
//assign local signal to its output signal
assign S_READY = S_READY_I;
assign M_VALID = M_VALID_I;
always @(posedge ACLK) begin
ARESET_D <= {ARESET_D[0], ARESET};
end
//Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK or ARESET) begin
if (ARESET == 1'b1) begin
STORAGE_DATA <= 0;
end else begin
if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin
STORAGE_DATA <= S_PAYLOAD_DATA;
end
end
end
always @(posedge ACLK) begin
M_PAYLOAD_DATA = STORAGE_DATA;
end
//M_Valid set to high when we have a completed transfer on slave side
//Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK or ARESET_D) begin
if (ARESET_D != 2'b00) begin
M_VALID_I <= 1'b0;
end else begin
if (S_VALID == 1'b1) begin
//Always set M_VALID_I when slave side is valid
M_VALID_I <= 1'b1;
end else if (M_READY == 1'b1 ) begin
//Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= 1'b0;
end
end
end
//Slave Ready is either when Master side drives M_READY or we have space in our storage data
assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
endmodule |
module blk_mem_gen_v8_3_5_output_stage
#(parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RST = 0,
parameter C_RSTRAM = 0,
parameter C_RST_PRIORITY = "CE",
parameter C_INIT_VAL = "0",
parameter C_HAS_EN = 0,
parameter C_HAS_REGCE = 0,
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_MEM_OUTPUT_REGS = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter NUM_STAGES = 1,
parameter C_EN_ECC_PIPE = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input RST,
input EN,
input REGCE,
input [C_DATA_WIDTH-1:0] DIN_I,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN_I,
input DBITERR_IN_I,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN_I,
input ECCPIPECE,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RST : Determines the presence of the RST port
// C_RSTRAM : Determines if special reset behavior is used
// C_RST_PRIORITY : Determines the priority between CE and SR
// C_INIT_VAL : Initialization value
// C_HAS_EN : Determines the presence of the EN port
// C_HAS_REGCE : Determines the presence of the REGCE port
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// NUM_STAGES : Determines the number of output stages
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// RST : Reset input to reset memory outputs to a user-defined
// reset state
// EN : Enable all read and write operations
// REGCE : Register Clock Enable to control each pipeline output
// register stages
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
// Fix for CR-509792
localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;
// Declare the pipeline registers
// (includes mem output reg, mux pipeline stages, and mux output reg)
reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;
reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;
reg [REG_STAGES-1:0] sbiterr_regs;
reg [REG_STAGES-1:0] dbiterr_regs;
reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL;
reg [C_DATA_WIDTH-1:0] init_val ;
//*********************************************
// Wire off optional inputs based on parameters
//*********************************************
wire en_i;
wire regce_i;
wire rst_i;
// Internal signals
reg [C_DATA_WIDTH-1:0] DIN;
reg [C_ADDRB_WIDTH-1:0] RDADDRECC_IN;
reg SBITERR_IN;
reg DBITERR_IN;
// Internal enable for output registers is tied to user EN or '1' depending
// on parameters
assign en_i = (C_HAS_EN==0 || EN);
// Internal register enable for output registers is tied to user REGCE, EN or
// '1' depending on parameters
// For V4 ECC, REGCE is always 1
// Virtex-4 ECC Not Yet Supported
assign regce_i = ((C_HAS_REGCE==1) && REGCE) ||
((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));
//Internal SRR is tied to user RST or '0' depending on parameters
assign rst_i = (C_HAS_RST==1) && RST;
//****************************************************
// Power on: load up the output registers and latches
//****************************************************
initial begin
if (!($sscanf(init_str, "%h", init_val))) begin
init_val = 0;
end
DOUT = init_val;
RDADDRECC = 0;
SBITERR = 1'b0;
DBITERR = 1'b0;
DIN = {(C_DATA_WIDTH){1'b0}};
RDADDRECC_IN = 0;
SBITERR_IN = 0;
DBITERR_IN = 0;
// This will be one wider than need, but 0 is an error
out_regs = {(REG_STAGES+1){init_val}};
rdaddrecc_regs = 0;
sbiterr_regs = {(REG_STAGES+1){1'b0}};
dbiterr_regs = {(REG_STAGES+1){1'b0}};
end
//***********************************************
// NUM_STAGES = 0 (No output registers. RAM only)
//***********************************************
generate if (NUM_STAGES == 0) begin : zero_stages
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg
always @* begin
DIN = DIN_I;
SBITERR_IN = SBITERR_IN_I;
DBITERR_IN = DBITERR_IN_I;
RDADDRECC_IN = RDADDRECC_IN_I;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg
always @(posedge CLK) begin
if(ECCPIPECE == 1) begin
DIN <= #FLOP_DELAY DIN_I;
SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;
DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;
RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;
end
end
end
endgenerate
//***********************************************
// NUM_STAGES = 1
// (Mem Output Reg only or Mux Output Reg only)
//***********************************************
// Possible valid combinations:
// Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
// +-----------------------------------------+
// | C_RSTRAM_* | Reset Behavior |
// +----------------+------------------------+
// | 0 | Normal Behavior |
// +----------------+------------------------+
// | 1 | Special Behavior |
// +----------------+------------------------+
//
// Normal = REGCE gates reset, as in the case of all families except S3ADSP.
// Special = EN gates reset, as in the case of S3ADSP.
generate if (NUM_STAGES == 1 &&
(C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) ||
C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))
begin : one_stages_norm
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end //end Priority conditions
end //end RST Type conditions
end //end one_stages_norm generate statement
endgenerate
// Special Reset Behavior for S3ADSP
generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp"))
begin : one_stage_splbhv
always @(posedge CLK) begin
if (en_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
end else if (regce_i && !rst_i) begin
DOUT <= #FLOP_DELAY DIN;
end //Output signal assignments
end //end CLK
end //end one_stage_splbhv generate statement
endgenerate
//************************************************************
// NUM_STAGES > 1
// Mem Output Reg + Mux Output Reg
// or
// Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
// or
// Mux Pipeline Stages (>0) + Mux Output Reg
//*************************************************************
generate if (NUM_STAGES > 1) begin : multi_stage
//Asynchronous Reset
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end //end Priority conditions
// Shift the data through the output stages
if (en_i) begin
out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;
rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;
sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;
dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;
end
end //end CLK
end //end multi_stage generate statement
endgenerate
endmodule |
module blk_mem_gen_v8_3_5_softecc_output_reg_stage
#(parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input [C_DATA_WIDTH-1:0] DIN,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
reg [C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule |
module
//***************************************************************
// Port A
assign rsta_outp_stage = RSTA & (~SLEEP);
blk_mem_gen_v8_3_5_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTA),
.C_RSTRAM (C_RSTRAM_A),
.C_RST_PRIORITY (C_RST_PRIORITY_A),
.C_INIT_VAL (C_INITA_VAL),
.C_HAS_EN (C_HAS_ENA),
.C_HAS_REGCE (C_HAS_REGCEA),
.C_DATA_WIDTH (C_READ_WIDTH_A),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_A),
.C_EN_ECC_PIPE (0),
.FLOP_DELAY (FLOP_DELAY))
reg_a
(.CLK (CLKA),
.RST (rsta_outp_stage),//(RSTA),
.EN (ENA),
.REGCE (REGCEA),
.DIN_I (memory_out_a),
.DOUT (DOUTA),
.SBITERR_IN_I (1'b0),
.DBITERR_IN_I (1'b0),
.SBITERR (),
.DBITERR (),
.RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),
.ECCPIPECE (1'b0),
.RDADDRECC ()
);
assign rstb_outp_stage = RSTB & (~SLEEP);
// Port B
blk_mem_gen_v8_3_5_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTB),
.C_RSTRAM (C_RSTRAM_B),
.C_RST_PRIORITY (C_RST_PRIORITY_B),
.C_INIT_VAL (C_INITB_VAL),
.C_HAS_EN (C_HAS_ENB),
.C_HAS_REGCE (C_HAS_REGCEB),
.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_B),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.FLOP_DELAY (FLOP_DELAY))
reg_b
(.CLK (CLKB),
.RST (rstb_outp_stage),//(RSTB),
.EN (ENB),
.REGCE (REGCEB),
.DIN_I (memory_out_b),
.DOUT (dout_i),
.SBITERR_IN_I (sbiterr_in),
.DBITERR_IN_I (dbiterr_in),
.SBITERR (sbiterr_i),
.DBITERR (dbiterr_i),
.RDADDRECC_IN_I (rdaddrecc_in),
.ECCPIPECE (ECCPIPECE),
.RDADDRECC (rdaddrecc_i)
);
//***************************************************************
// Instantiate the Input and Output register stages
//***************************************************************
blk_mem_gen_v8_3_5_softecc_output_reg_stage
#(.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.FLOP_DELAY (FLOP_DELAY))
has_softecc_output_reg_stage
(.CLK (CLKB),
.DIN (dout_i),
.DOUT (DOUTB),
.SBITERR_IN (sbiterr_i),
.DBITERR_IN (dbiterr_i),
.SBITERR (sbiterr_sdp),
.DBITERR (dbiterr_sdp),
.RDADDRECC_IN (rdaddrecc_i),
.RDADDRECC (rdaddrecc_sdp)
);
//****************************************************
// Synchronous collision checks
//****************************************************
// CR 780544 : To make verilog model's collison warnings in consistant with
// vhdl model, the non-blocking assignments are replaced with blocking
// assignments.
generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision = 0;
end
end else begin
is_collision = 0;
end
// If the write port is in READ_FIRST mode, there is no collision
if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin
is_collision = 0;
end
if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin
is_collision = 0;
end
// Only flag if one of the accesses is a write
if (is_collision && (wea_i || web_i)) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B %0s address: %0h\n",
wea_i ? "write" : "read", ADDRA,
web_i ? "write" : "read", ADDRB);
end
end
//****************************************************
// Asynchronous collision checks
//****************************************************
end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll
// Delay A and B addresses in order to mimic setup/hold times
wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA;
wire [0:0] #COLL_DELAY wea_delay = wea_i;
wire #COLL_DELAY ena_delay = ena_i;
wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB;
wire [0:0] #COLL_DELAY web_delay = web_i;
wire #COLL_DELAY enb_delay = enb_i;
// Do the checks w/rt A
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_a = 0;
end
end else begin
is_collision_a = 0;
end
if (ena_i && enb_delay) begin
if(wea_i || web_delay) begin
is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,
web_delay);
end else begin
is_collision_delay_a = 0;
end
end else begin
is_collision_delay_a = 0;
end
// Only flag if B access is a write
if (is_collision_a && web_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, ADDRB);
end else if (is_collision_delay_a && web_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, addrb_delay);
end
end
// Do the checks w/rt B
always @(posedge CLKB) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_b = 0;
end
end else begin
is_collision_b = 0;
end
if (ena_delay && enb_i) begin
if (wea_delay || web_i) begin
is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,
web_i);
end else begin
is_collision_delay_b = 0;
end
end else begin
is_collision_delay_b = 0;
end
// Only flag if A access is a write
if (is_collision_b && wea_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
ADDRA, web_i ? "write" : "read", ADDRB);
end else if (is_collision_delay_b && wea_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
addra_delay, web_i ? "write" : "read", ADDRB);
end
end
end
endgenerate
endmodule |
module blk_mem_gen_v8_3_5
#(parameter C_CORENAME = "blk_mem_gen_v8_3_5",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_ELABORATION_DIR = "",
parameter C_INTERFACE_TYPE = 0,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_CTRL_ECC_ALGO = "NONE",
parameter C_ENABLE_32BIT_ADDRESS = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
//parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_SLEEP_PIN = 0,
parameter C_USE_URAM = 0,
parameter C_EN_RDADDRA_CHG = 0,
parameter C_EN_RDADDRB_CHG = 0,
parameter C_EN_DEEPSLEEP_PIN = 0,
parameter C_EN_SHUTDOWN_PIN = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_COUNT_36K_BRAM = "",
parameter C_COUNT_18K_BRAM = "",
parameter C_EST_POWER_SUMMARY = "",
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input clka,
input rsta,
input ena,
input regcea,
input [C_WEA_WIDTH-1:0] wea,
input [C_ADDRA_WIDTH-1:0] addra,
input [C_WRITE_WIDTH_A-1:0] dina,
output [C_READ_WIDTH_A-1:0] douta,
input clkb,
input rstb,
input enb,
input regceb,
input [C_WEB_WIDTH-1:0] web,
input [C_ADDRB_WIDTH-1:0] addrb,
input [C_WRITE_WIDTH_B-1:0] dinb,
output [C_READ_WIDTH_B-1:0] doutb,
input injectsbiterr,
input injectdbiterr,
output sbiterr,
output dbiterr,
output [C_ADDRB_WIDTH-1:0] rdaddrecc,
input eccpipece,
input sleep,
input deepsleep,
input shutdown,
output rsta_busy,
output rstb_busy,
//AXI BMG Input and Output Port Declarations
//AXI Global Signals
input s_aclk,
input s_aresetn,
//AXI Full/lite slave write (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [31:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input s_axi_awvalid,
output s_axi_awready,
input [C_WRITE_WIDTH_A-1:0] s_axi_wdata,
input [C_WEA_WIDTH-1:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
//AXI Full/lite slave read (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [31:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_WRITE_WIDTH_B-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
input s_axi_rready,
//AXI Full/lite sideband signals
input s_axi_injectsbiterr,
input s_axi_injectdbiterr,
output s_axi_sbiterr,
output s_axi_dbiterr,
output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_HAS_SOFTECC_INPUT_REGS_A :
// C_HAS_SOFTECC_OUTPUT_REGS_B :
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
wire SBITERR;
wire DBITERR;
wire S_AXI_AWREADY;
wire S_AXI_WREADY;
wire S_AXI_BVALID;
wire S_AXI_ARREADY;
wire S_AXI_RLAST;
wire S_AXI_RVALID;
wire S_AXI_SBITERR;
wire S_AXI_DBITERR;
wire [C_WEA_WIDTH-1:0] WEA = wea;
wire [C_ADDRA_WIDTH-1:0] ADDRA = addra;
wire [C_WRITE_WIDTH_A-1:0] DINA = dina;
wire [C_READ_WIDTH_A-1:0] DOUTA;
wire [C_WEB_WIDTH-1:0] WEB = web;
wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb;
wire [C_WRITE_WIDTH_B-1:0] DINB = dinb;
wire [C_READ_WIDTH_B-1:0] DOUTB;
wire [C_ADDRB_WIDTH-1:0] RDADDRECC;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid;
wire [31:0] S_AXI_AWADDR = s_axi_awaddr;
wire [7:0] S_AXI_AWLEN = s_axi_awlen;
wire [2:0] S_AXI_AWSIZE = s_axi_awsize;
wire [1:0] S_AXI_AWBURST = s_axi_awburst;
wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata;
wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [1:0] S_AXI_BRESP;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid;
wire [31:0] S_AXI_ARADDR = s_axi_araddr;
wire [7:0] S_AXI_ARLEN = s_axi_arlen;
wire [2:0] S_AXI_ARSIZE = s_axi_arsize;
wire [1:0] S_AXI_ARBURST = s_axi_arburst;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA;
wire [1:0] S_AXI_RRESP;
wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC;
// Added to fix the simulation warning #CR731605
wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0;
wire ECCPIPECE;
wire SLEEP;
reg RSTA_BUSY = 0;
reg RSTB_BUSY = 0;
// Declaration of internal signals to avoid warnings #927399
wire CLKA;
wire RSTA;
wire ENA;
wire REGCEA;
wire CLKB;
wire RSTB;
wire ENB;
wire REGCEB;
wire INJECTSBITERR;
wire INJECTDBITERR;
wire S_ACLK;
wire S_ARESETN;
wire S_AXI_AWVALID;
wire S_AXI_WLAST;
wire S_AXI_WVALID;
wire S_AXI_BREADY;
wire S_AXI_ARVALID;
wire S_AXI_RREADY;
wire S_AXI_INJECTSBITERR;
wire S_AXI_INJECTDBITERR;
assign CLKA = clka;
assign RSTA = rsta;
assign ENA = ena;
assign REGCEA = regcea;
assign CLKB = clkb;
assign RSTB = rstb;
assign ENB = enb;
assign REGCEB = regceb;
assign INJECTSBITERR = injectsbiterr;
assign INJECTDBITERR = injectdbiterr;
assign ECCPIPECE = eccpipece;
assign SLEEP = sleep;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr;
assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr;
assign s_axi_sbiterr = S_AXI_SBITERR;
assign s_axi_dbiterr = S_AXI_DBITERR;
assign rsta_busy = RSTA_BUSY;
assign rstb_busy = RSTB_BUSY;
assign doutb = DOUTB;
assign douta = DOUTA;
assign rdaddrecc = RDADDRECC;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_rdaddrecc = S_AXI_RDADDRECC;
localparam FLOP_DELAY = 100; // 100 ps
reg injectsbiterr_in;
reg injectdbiterr_in;
reg rsta_in;
reg ena_in;
reg regcea_in;
reg [C_WEA_WIDTH-1:0] wea_in;
reg [C_ADDRA_WIDTH-1:0] addra_in;
reg [C_WRITE_WIDTH_A-1:0] dina_in;
wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;
wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;
wire s_axi_wr_en_c;
wire s_axi_rd_en_c;
wire s_aresetn_a_c;
wire [7:0] s_axi_arlen_c ;
wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;
wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;
wire [1:0] s_axi_rresp_c;
wire s_axi_rlast_c;
wire s_axi_rvalid_c;
wire s_axi_rready_c;
wire regceb_c;
localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;
wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;
wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;
// Safety logic related signals
reg [4:0] RSTA_SHFT_REG = 0;
reg POR_A = 0;
reg [4:0] RSTB_SHFT_REG = 0;
reg POR_B = 0;
reg ENA_dly = 0;
reg ENA_dly_D = 0;
reg ENB_dly = 0;
reg ENB_dly_D = 0;
wire RSTA_I_SAFE;
wire RSTB_I_SAFE;
wire ENA_I_SAFE;
wire ENB_I_SAFE;
reg ram_rstram_a_busy = 0;
reg ram_rstreg_a_busy = 0;
reg ram_rstram_b_busy = 0;
reg ram_rstreg_b_busy = 0;
reg ENA_dly_reg = 0;
reg ENB_dly_reg = 0;
reg ENA_dly_reg_D = 0;
reg ENB_dly_reg_D = 0;
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//**************
// log2int
//**************
function integer log2int (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
cnt= data_value;
for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin
width = width + 1;
end //loop
log2int = width;
end //log2int
endfunction
//**************************************************************************
// FUNCTION : divroundup
// Returns the ceiling value of the division
// Data_value - the quantity to be divided, dividend
// Divisor - the value to divide the data_value by
//**************************************************************************
function integer divroundup (input integer data_value,input integer divisor);
integer div;
begin
div = data_value/divisor;
if ((data_value % divisor) != 0) begin
div = div+1;
end //if
divroundup = div;
end //if
endfunction
localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);
localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB;
//Data Width Number of LSB address bits to be discarded
//1 to 16 1
//17 to 32 2
//33 to 64 3
//65 to 128 4
//129 to 256 5
//257 to 512 6
//513 to 1024 7
// The following two constants determine this.
localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);
localparam C_AXI_OS_WR = 2;
//***********************************************
// INPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage
always @* begin
injectsbiterr_in = INJECTSBITERR;
injectdbiterr_in = INJECTDBITERR;
rsta_in = RSTA;
ena_in = ENA;
regcea_in = REGCEA;
wea_in = WEA;
addra_in = ADDRA;
dina_in = DINA;
end //end always
end //end no_softecc_input_reg_stage
endgenerate
generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage
always @(posedge CLKA) begin
injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;
injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;
rsta_in <= #FLOP_DELAY RSTA;
ena_in <= #FLOP_DELAY ENA;
regcea_in <= #FLOP_DELAY REGCEA;
wea_in <= #FLOP_DELAY WEA;
addra_in <= #FLOP_DELAY ADDRA;
dina_in <= #FLOP_DELAY DINA;
end //end always
end //end input_reg_stages generate statement
endgenerate
//**************************************************************************
// NO SAFETY LOGIC
//**************************************************************************
generate
if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN
assign ENA_I_SAFE = ena_in;
assign ENB_I_SAFE = ENB;
assign RSTA_I_SAFE = rsta_in;
assign RSTB_I_SAFE = RSTB;
end
endgenerate
//***************************************************************************
// SAFETY LOGIC
// Power-ON Reset Generation
//***************************************************************************
generate
if (C_EN_SAFETY_CKT == 1) begin
always @(posedge clka) RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;
always @(posedge clka) POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];
always @(posedge clkb) RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;
always @(posedge clkb) POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0];
assign RSTA_I_SAFE = rsta_in | POR_A;
assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);
end
endgenerate
//-----------------------------------------------------------------------------
// -- RSTA/B_BUSY Generation
//-----------------------------------------------------------------------------
generate
if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG
always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;
always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG
always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;
always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;
end
endgenerate
generate
if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY
always @(*) RSTB_BUSY = 1'b0;
end
endgenerate
generate
if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_NO_REG
always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;
always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG
always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;
always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;
end
endgenerate
//-----------------------------------------------------------------------------
// -- ENA/ENB Generation
//-----------------------------------------------------------------------------
generate
if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG
always @(posedge clka) begin
ENA_dly <= #FLOP_DELAY RSTA_I_SAFE;
ENA_dly_D <= #FLOP_DELAY ENA_dly;
end
assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);
end
endgenerate
generate
if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG
always @(posedge clka) begin
ENA_dly_reg <= #FLOP_DELAY RSTA_I_SAFE;
ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;
end
assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);
end
endgenerate
generate
if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB
assign ENB_I_SAFE = 1'b0;
end
endgenerate
generate
if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG
always @(posedge clkb) begin : PROC_ENB_GEN
ENB_dly <= #FLOP_DELAY RSTB_I_SAFE;
ENB_dly_D <= #FLOP_DELAY ENB_dly;
end
assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG
always @(posedge clkb) begin : PROC_ENB_GEN
ENB_dly_reg <= #FLOP_DELAY RSTB_I_SAFE;
ENB_dly_reg_D <= #FLOP_DELAY ENB_dly_reg;
end
assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);
end
endgenerate
generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module
blk_mem_gen_v8_3_5_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_ALGORITHM (C_ALGORITHM),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_5_inst
(.CLKA (CLKA),
.RSTA (RSTA_I_SAFE),//(rsta_in),
.ENA (ENA_I_SAFE),//(ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB_I_SAFE),//(RSTB),
.ENB (ENB_I_SAFE),//(ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module
localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);
localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);
localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
// localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);
// localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);
localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB;
localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB;
// Data Width Number of LSB address bits to be discarded
// 1 to 16 1
// 17 to 32 2
// 33 to 64 3
// 65 to 128 4
// 129 to 256 5
// 257 to 512 6
// 513 to 1024 7
// The following two constants determine this.
localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;
localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;
wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;
wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;
wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;
assign msb_zero_i = 0;
assign lsb_zero_i = 0;
assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i};
blk_mem_gen_v8_3_5_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_5_inst
(.CLKA (CLKA),
.RSTA (RSTA_I_SAFE),//(rsta_in),
.ENA (ENA_I_SAFE),//(ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB_I_SAFE),//(RSTB),
.ENB (ENB_I_SAFE),//(ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (rdaddrecc_i)
);
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RLAST = s_axi_rlast_c;
assign S_AXI_RVALID = s_axi_rvalid_c;
assign S_AXI_RID = s_axi_rid_c;
assign S_AXI_RRESP = s_axi_rresp_c;
assign s_axi_rready_c = S_AXI_RREADY;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb
assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb
assign regceb_c = REGCEB;
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd
blk_mem_axi_regs_fwd_v8_3
#(.C_DATA_WIDTH (C_AXI_PAYLOAD))
axi_regs_inst (
.ACLK (S_ACLK),
.ARESET (s_aresetn_a_c),
.S_VALID (s_axi_rvalid_c),
.S_READY (s_axi_rready_c),
.S_PAYLOAD_DATA (s_axi_payload_c),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY),
.M_PAYLOAD_DATA (m_axi_payload_c)
);
end
endgenerate
generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module
assign s_aresetn_a_c = !S_ARESETN;
assign S_AXI_BRESP = 2'b00;
assign s_axi_rresp_c = 2'b00;
assign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;
blk_mem_axi_write_wrapper_beh_v8_3
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A),
.C_AXI_OS_WR (C_AXI_OS_WR))
axi_wr_fsm (
// AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
// AXI Full/Lite Slave Write interface
.S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
.S_AXI_BID (S_AXI_BID),
// Signals for BRAM interfac(
.S_AXI_AWADDR_OUT (s_axi_awaddr_out_c),
.S_AXI_WR_EN (s_axi_wr_en_c)
);
blk_mem_axi_read_wrapper_beh_v8_3
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_PIPELINE_STAGES (1),
.C_AXI_ARADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_rd_sm(
//AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
//AXI Full/Lite Read Side
.S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_ARLEN (s_axi_arlen_c),
.S_AXI_ARSIZE (S_AXI_ARSIZE),
.S_AXI_ARBURST (S_AXI_ARBURST),
.S_AXI_ARVALID (S_AXI_ARVALID),
.S_AXI_ARREADY (S_AXI_ARREADY),
.S_AXI_RLAST (s_axi_rlast_c),
.S_AXI_RVALID (s_axi_rvalid_c),
.S_AXI_RREADY (s_axi_rready_c),
.S_AXI_ARID (S_AXI_ARID),
.S_AXI_RID (s_axi_rid_c),
//AXI Full/Lite Read FSM Outputs
.S_AXI_ARADDR_OUT (s_axi_araddr_out_c),
.S_AXI_RD_EN (s_axi_rd_en_c)
);
blk_mem_gen_v8_3_5_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (1),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (1),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (1),
.C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_BYTE_WEB (1),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (0),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (0),
.C_HAS_MUX_OUTPUT_REGS_B (0),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (0),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_5_inst
(.CLKA (S_ACLK),
.RSTA (s_aresetn_a_c),
.ENA (s_axi_wr_en_c),
.REGCEA (regcea_in),
.WEA (S_AXI_WSTRB),
.ADDRA (s_axi_awaddr_out_c),
.DINA (S_AXI_WDATA),
.DOUTA (DOUTA),
.CLKB (S_ACLK),
.RSTB (s_aresetn_a_c),
.ENB (s_axi_rd_en_c),
.REGCEB (regceb_c),
.WEB (WEB_parameterized),
.ADDRB (s_axi_araddr_out_c),
.DINB (DINB),
.DOUTB (s_axi_rdata_c),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.ECCPIPECE (1'b0),
.SLEEP (1'b0),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
endmodule |
module STATE_LOGIC_v8_3 (O, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
input I0, I1, I2, I3, I4, I5;
output O;
reg O;
reg tmp;
always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin
tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5;
if ( tmp == 0 || tmp == 1)
O = INIT[{I5, I4, I3, I2, I1, I0}];
end
endmodule |
module beh_vlog_muxf7_v8_3 (O, I0, I1, S);
output O;
reg O;
input I0, I1, S;
always @(I0 or I1 or S)
if (S)
O = I1;
else
O = I0;
endmodule |
module beh_vlog_ff_clr_v8_3 (Q, C, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q<= 1'b0;
else
Q<= #FLOP_DELAY D;
endmodule |
module beh_vlog_ff_pre_v8_3 (Q, C, D, PRE);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, D, PRE;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (PRE)
Q <= 1'b1;
else
Q <= #FLOP_DELAY D;
endmodule |
module beh_vlog_ff_ce_clr_v8_3 (Q, C, CE, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CE, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q <= 1'b0;
else if (CE)
Q <= #FLOP_DELAY D;
endmodule |
module write_netlist_v8_3
#(
parameter C_AXI_TYPE = 0
)
(
S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,
w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,
S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c
);
input S_ACLK;
input S_ARESETN;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input S_AXI_BREADY;
input w_last_c;
input bready_timeout_c;
output aw_ready_r;
output S_AXI_WREADY;
output S_AXI_BVALID;
output S_AXI_WR_EN;
output addr_en_c;
output incr_addr_c;
output bvalid_c;
//-------------------------------------------------------------------------
//AXI LITE
//-------------------------------------------------------------------------
generate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm
wire w_ready_r_7;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSignal_bvalid_c;
wire NlwRenamedSignal_incr_addr_c;
wire present_state_FSM_FFd3_13;
wire present_state_FSM_FFd2_14;
wire present_state_FSM_FFd1_15;
wire present_state_FSM_FFd4_16;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd4_In1_21;
wire [0:0] Mmux_aw_ready_c ;
begin
assign
S_AXI_WREADY = w_ready_r_7,
S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,
S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,
incr_addr_c = NlwRenamedSignal_incr_addr_c,
bvalid_c = NlwRenamedSignal_bvalid_c;
assign NlwRenamedSignal_incr_addr_c = 1'b0;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
aw_ready_r_2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
w_ready_r (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_7)
);
beh_vlog_ff_pre_v8_3 #(
.INIT (1'b1))
present_state_FSM_FFd4 (
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_16)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd3 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_13)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_15)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000055554440))
present_state_FSM_FFd3_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000088880800))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_AWVALID),
.I1 ( S_AXI_WVALID),
.I2 ( bready_timeout_c),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000AAAA2000))
Mmux_addr_en_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_WVALID),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( addr_en_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hF5F07570F5F05500))
Mmux_w_ready_c_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( w_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd3_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd1_15),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( present_state_FSM_FFd3_13),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSignal_bvalid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h2F0F27072F0F2200))
present_state_FSM_FFd4_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( present_state_FSM_FFd4_In1_21)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000F8))
present_state_FSM_FFd4_In2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_In1_21),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h7535753575305500))
Mmux_aw_ready_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_WVALID),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 ( present_state_FSM_FFd2_14),
.O ( Mmux_aw_ready_c[0])
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000F8))
Mmux_aw_ready_c_0_2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( Mmux_aw_ready_c[0]),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( aw_ready_c)
);
end
end
endgenerate
//---------------------------------------------------------------------
// AXI FULL
//---------------------------------------------------------------------
generate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm
wire w_ready_r_8;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSig_OI_bvalid_c;
wire present_state_FSM_FFd1_16;
wire present_state_FSM_FFd4_17;
wire present_state_FSM_FFd3_18;
wire present_state_FSM_FFd2_19;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd2_In1_24;
wire present_state_FSM_FFd4_In1_25;
wire N2;
wire N4;
begin
assign
S_AXI_WREADY = w_ready_r_8,
bvalid_c = NlwRenamedSig_OI_bvalid_c,
S_AXI_BVALID = 1'b0;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
aw_ready_r_2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
w_ready_r
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_8)
);
beh_vlog_ff_pre_v8_3 #(
.INIT (1'b1))
present_state_FSM_FFd4
(
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_17)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd3
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_18)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_19)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_16)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000005540))
present_state_FSM_FFd3_In1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd4_17),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hBF3FBB33AF0FAA00))
Mmux_aw_ready_c_0_2
(
.I0 ( S_AXI_BREADY),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd1_16),
.I4 ( present_state_FSM_FFd4_17),
.I5 ( NlwRenamedSig_OI_bvalid_c),
.O ( aw_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hAAAAAAAA20000000))
Mmux_addr_en_c_0_1
(
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( S_AXI_WVALID),
.I4 ( w_last_c),
.I5 ( present_state_FSM_FFd4_17),
.O ( addr_en_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_19),
.I2 ( present_state_FSM_FFd3_18),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( S_AXI_WR_EN)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000002220))
Mmux_incr_addr_c_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( incr_addr_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000008880))
Mmux_aw_ready_c_0_11
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSig_OI_bvalid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000000000D5C0))
present_state_FSM_FFd2_In1
(
.I0 ( w_last_c),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In1_24)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFFFFAAAA08AAAAAA))
present_state_FSM_FFd2_In2
(
.I0 ( present_state_FSM_FFd2_19),
.I1 ( S_AXI_AWVALID),
.I2 ( bready_timeout_c),
.I3 ( w_last_c),
.I4 ( S_AXI_WVALID),
.I5 ( present_state_FSM_FFd2_In1_24),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00C0004000C00000))
present_state_FSM_FFd4_In1
(
.I0 ( S_AXI_AWVALID),
.I1 ( w_last_c),
.I2 ( S_AXI_WVALID),
.I3 ( bready_timeout_c),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( present_state_FSM_FFd4_In1_25)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000FFFF88F8))
present_state_FSM_FFd4_In2
(
.I0 ( present_state_FSM_FFd1_16),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( S_AXI_AWVALID),
.I4 ( present_state_FSM_FFd4_In1_25),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000007))
Mmux_w_ready_c_0_SW0
(
.I0 ( w_last_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N2)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFABAFABAFAAAF000))
Mmux_w_ready_c_0_Q
(
.I0 ( N2),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd4_17),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( w_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000008))
Mmux_aw_ready_c_0_11_SW0
(
.I0 ( bready_timeout_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N4)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1
(
.I0 ( w_last_c),
.I1 ( N4),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 ( present_state_FSM_FFd1_16),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
end
end
endgenerate
endmodule |
module read_netlist_v8_3 #(
parameter C_AXI_TYPE = 1,
parameter C_ADDRB_WIDTH = 12
) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,
S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,
S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,
S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);
input S_AXI_R_LAST_INT;
input S_ACLK;
input S_ARESETN;
input S_AXI_ARVALID;
input S_AXI_RREADY;
output S_AXI_INCR_ADDR;
output S_AXI_ADDR_EN;
output S_AXI_SINGLE_TRANS;
output S_AXI_MUX_SEL;
output S_AXI_R_LAST;
output S_AXI_ARREADY;
output S_AXI_RLAST;
output S_AXI_RVALID;
output S_AXI_RD_EN;
input [7:0] S_AXI_ARLEN;
wire present_state_FSM_FFd1_13 ;
wire present_state_FSM_FFd2_14 ;
wire gaxi_full_sm_outstanding_read_r_15 ;
wire gaxi_full_sm_ar_ready_r_16 ;
wire gaxi_full_sm_r_last_r_17 ;
wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ;
wire gaxi_full_sm_r_valid_c ;
wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ;
wire gaxi_full_sm_ar_ready_c ;
wire gaxi_full_sm_outstanding_read_c ;
wire NlwRenamedSig_OI_S_AXI_R_LAST ;
wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ;
wire present_state_FSM_FFd2_In ;
wire present_state_FSM_FFd1_In ;
wire Mmux_S_AXI_R_LAST13 ;
wire N01 ;
wire N2 ;
wire Mmux_gaxi_full_sm_ar_ready_c11 ;
wire N4 ;
wire N8 ;
wire N9 ;
wire N10 ;
wire N11 ;
wire N12 ;
wire N13 ;
assign
S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,
S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,
S_AXI_RLAST = gaxi_full_sm_r_last_r_17,
S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_outstanding_read_r (
.C (S_ACLK),
.CLR(S_ARESETN),
.D(gaxi_full_sm_outstanding_read_c),
.Q(gaxi_full_sm_outstanding_read_r_15)
);
beh_vlog_ff_ce_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_r_valid_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (gaxi_full_sm_r_valid_c),
.Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_ar_ready_r (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (gaxi_full_sm_ar_ready_c),
.Q (gaxi_full_sm_ar_ready_r_16)
);
beh_vlog_ff_ce_clr_v8_3 #(
.INIT(1'b0))
gaxi_full_sm_r_last_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (NlwRenamedSig_OI_S_AXI_R_LAST),
.Q (gaxi_full_sm_r_last_r_17)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (present_state_FSM_FFd1_In),
.Q (present_state_FSM_FFd1_13)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000000000000B))
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (
.I0 ( S_AXI_RREADY),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000008))
Mmux_S_AXI_SINGLE_TRANS11 (
.I0 (S_AXI_ARVALID),
.I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_SINGLE_TRANS)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000004))
Mmux_S_AXI_ADDR_EN11 (
.I0 (present_state_FSM_FFd1_13),
.I1 (S_AXI_ARVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_ADDR_EN)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hECEE2022EEEE2022))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_ARVALID),
.I1 ( present_state_FSM_FFd1_13),
.I2 ( S_AXI_RREADY),
.I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000044440444))
Mmux_S_AXI_R_LAST131 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_RREADY),
.I5 (1'b0),
.O ( Mmux_S_AXI_R_LAST13)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h4000FFFF40004000))
Mmux_S_AXI_INCR_ADDR11 (
.I0 ( S_AXI_R_LAST_INT),
.I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( Mmux_S_AXI_R_LAST13),
.O ( S_AXI_INCR_ADDR)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000FE))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (
.I0 ( S_AXI_ARLEN[2]),
.I1 ( S_AXI_ARLEN[1]),
.I2 ( S_AXI_ARLEN[0]),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N01)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000001))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (
.I0 ( S_AXI_ARLEN[7]),
.I1 ( S_AXI_ARLEN[6]),
.I2 ( S_AXI_ARLEN[5]),
.I3 ( S_AXI_ARLEN[4]),
.I4 ( S_AXI_ARLEN[3]),
.I5 ( N01),
.O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000007))
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 ( 1'b0),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N2)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0020000002200200))
Mmux_gaxi_full_sm_outstanding_read_c1 (
.I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd1_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( gaxi_full_sm_outstanding_read_r_15),
.I5 ( N2),
.O ( gaxi_full_sm_outstanding_read_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000004555))
Mmux_gaxi_full_sm_ar_ready_c12 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( Mmux_gaxi_full_sm_ar_ready_c11)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000EF))
Mmux_S_AXI_R_LAST11_SW0 (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N4)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFCAAFC0A00AA000A))
Mmux_S_AXI_R_LAST11 (
.I0 ( S_AXI_ARVALID),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( N4),
.I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.O ( gaxi_full_sm_r_valid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000AAAAAA08))
S_AXI_MUX_SEL1 (
.I0 (present_state_FSM_FFd1_13),
.I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (S_AXI_RREADY),
.I3 (present_state_FSM_FFd2_14),
.I4 (gaxi_full_sm_outstanding_read_r_15),
.I5 (1'b0),
.O (S_AXI_MUX_SEL)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hF3F3F755A2A2A200))
Mmux_S_AXI_RD_EN11 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 ( S_AXI_RREADY),
.I3 ( gaxi_full_sm_outstanding_read_r_15),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( S_AXI_ARVALID),
.O ( S_AXI_RD_EN)
);
beh_vlog_muxf7_v8_3 present_state_FSM_FFd1_In3 (
.I0 ( N8),
.I1 ( N9),
.S ( present_state_FSM_FFd1_13),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000005410F4F0))
present_state_FSM_FFd1_In3_F (
.I0 ( S_AXI_RREADY),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( S_AXI_ARVALID),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( 1'b0),
.O ( N8)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000072FF7272))
present_state_FSM_FFd1_In3_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N9)
);
beh_vlog_muxf7_v8_3 Mmux_gaxi_full_sm_ar_ready_c14 (
.I0 ( N10),
.I1 ( N11),
.S ( present_state_FSM_FFd1_13),
.O ( gaxi_full_sm_ar_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000FFFF88A8))
Mmux_gaxi_full_sm_ar_ready_c14_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( Mmux_gaxi_full_sm_ar_ready_c11),
.I5 ( 1'b0),
.O ( N10)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000008D008D8D))
Mmux_gaxi_full_sm_ar_ready_c14_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N11)
);
beh_vlog_muxf7_v8_3 Mmux_S_AXI_R_LAST1 (
.I0 ( N12),
.I1 ( N13),
.S ( present_state_FSM_FFd1_13),
.O ( NlwRenamedSig_OI_S_AXI_R_LAST)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000088088888))
Mmux_S_AXI_R_LAST1_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N12)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000E400E4E4))
Mmux_S_AXI_R_LAST1_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( S_AXI_R_LAST_INT),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N13)
);
endmodule |
module blk_mem_axi_write_wrapper_beh_v8_3
# (
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface
parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full;
parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
parameter C_WRITE_DEPTH_A = 0,
parameter C_AXI_AWADDR_WIDTH = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_WDATA_WIDTH = 32,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
// AXI OUTSTANDING WRITES
parameter C_AXI_OS_WR = 2
)
(
// AXI Global Signals
input S_ACLK,
input S_ARESETN,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,
input [8-1:0] S_AXI_AWLEN,
input [2:0] S_AXI_AWSIZE,
input [1:0] S_AXI_AWBURST,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
input S_AXI_WVALID,
output S_AXI_WREADY,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,
output S_AXI_BVALID,
input S_AXI_BREADY,
// Signals for BMG interface
output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,
output S_AXI_WR_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:
((C_AXI_WDATA_WIDTH==16)?1:
((C_AXI_WDATA_WIDTH==32)?2:
((C_AXI_WDATA_WIDTH==64)?3:
((C_AXI_WDATA_WIDTH==128)?4:
((C_AXI_WDATA_WIDTH==256)?5:0))))));
wire bvalid_c ;
reg bready_timeout_c = 0;
wire [1:0] bvalid_rd_cnt_c;
reg bvalid_r = 0;
reg [2:0] bvalid_count_r = 0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;
reg [1:0] bvalid_wr_cnt_r = 0;
reg [1:0] bvalid_rd_cnt_r = 0;
wire w_last_c ;
wire addr_en_c ;
wire incr_addr_c ;
wire aw_ready_r ;
wire dec_alen_c ;
reg bvalid_d1_c = 0;
reg [7:0] awlen_cntr_r = 0;
reg [7:0] awlen_int = 0;
reg [1:0] awburst_int = 0;
integer total_bytes = 0;
integer wrap_boundary = 0;
integer wrap_base_addr = 0;
integer num_of_bytes_c = 0;
integer num_of_bytes_r = 0;
// Array to store BIDs
reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;
wire S_AXI_BVALID_axi_wr_fsm;
//-------------------------------------
//AXI WRITE FSM COMPONENT INSTANTIATION
//-------------------------------------
write_netlist_v8_3 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm
(
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
.S_AXI_AWVALID(S_AXI_AWVALID),
.aw_ready_r(aw_ready_r),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_WR_EN(S_AXI_WR_EN),
.w_last_c(w_last_c),
.bready_timeout_c(bready_timeout_c),
.addr_en_c(addr_en_c),
.incr_addr_c(incr_addr_c),
.bvalid_c(bvalid_c),
.S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm)
);
//Wrap Address boundary calculation
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);
total_bytes = (num_of_bytes_r)*(awlen_int+1);
wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);
wrap_boundary = wrap_base_addr+total_bytes;
end
//-------------------------------------------------------------------------
// BMG address generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awaddr_reg <= 0;
num_of_bytes_r <= 0;
awburst_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);
end else if (incr_addr_c == 1'b1) begin
if (awburst_int == 2'b10) begin
if(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin
awaddr_reg <= wrap_base_addr;
end else begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end
end
end
assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);
//-------------------------------------------------------------------------
// AXI wlast generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awlen_cntr_r <= 0;
awlen_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
end else if (dec_alen_c == 1'b1) begin
awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ;
end
end
end
assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;
assign dec_alen_c = (incr_addr_c | w_last_c);
//-------------------------------------------------------------------------
// Generation of bvalid counter for outstanding transactions
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_count_r <= 0;
end else begin
// bvalid_count_r generation
if (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r ;
end else if (bvalid_c == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ;
end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ;
end
end
end
//-------------------------------------------------------------------------
// Generation of bvalid when BID is used
//-------------------------------------------------------------------------
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
bvalid_d1_c <= 0;
end else begin
// Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
//external bvalid signal generation
if (bvalid_d1_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of bvalid when BID is not used
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
end else begin
//external bvalid signal generation
if (bvalid_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of Bready timeout
//-------------------------------------------------------------------------
always @(bvalid_count_r) begin
// bready_timeout_c generation
if(bvalid_count_r == C_AXI_OS_WR-1) begin
bready_timeout_c <= 1'b1;
end else begin
bready_timeout_c <= 1'b0;
end
end
//-------------------------------------------------------------------------
// Generation of BID
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_wr_cnt_r <= 0;
bvalid_rd_cnt_r <= 0;
end else begin
// STORE AWID IN AN ARRAY
if(bvalid_c == 1'b1) begin
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1;
end
// generate BID FROM AWID ARRAY
bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;
S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c];
end
end
assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;
//-------------------------------------------------------------------------
// Storing AWID for generation of BID
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if(S_ARESETN == 1'b1) begin
axi_bid_array[0] = 0;
axi_bid_array[1] = 0;
axi_bid_array[2] = 0;
axi_bid_array[3] = 0;
end else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin
axi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;
end
end
end
endgenerate
assign S_AXI_BVALID = bvalid_r;
assign S_AXI_AWREADY = aw_ready_r;
endmodule |
module blk_mem_axi_read_wrapper_beh_v8_3
# (
//// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_WRITE_WIDTH_A = 4,
parameter C_WRITE_DEPTH_A = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_PIPELINE_STAGES = 0,
parameter C_AXI_ARADDR_WIDTH = 12,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_ADDRB_WIDTH = 12
)
(
//// AXI Global Signals
input S_ACLK,
input S_ARESETN,
//// AXI Full/Lite Slave Read (Read side)
input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,
input [7:0] S_AXI_ARLEN,
input [2:0] S_AXI_ARSIZE,
input [1:0] S_AXI_ARBURST,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
output S_AXI_RLAST,
output S_AXI_RVALID,
input S_AXI_RREADY,
input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,
//// AXI Full/Lite Read Address Signals to BRAM
output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,
output S_AXI_RD_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:
((C_WRITE_WIDTH_A==16)?1:
((C_WRITE_WIDTH_A==32)?2:
((C_WRITE_WIDTH_A==64)?3:
((C_WRITE_WIDTH_A==128)?4:
((C_WRITE_WIDTH_A==256)?5:0))))));
reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;
wire addr_en_c;
wire rd_en_c;
wire incr_addr_c;
wire single_trans_c;
wire dec_alen_c;
wire mux_sel_c;
wire r_last_c;
wire r_last_int_c;
wire [C_ADDRB_WIDTH-1 : 0] araddr_out;
reg [7:0] arlen_int_r=0;
reg [7:0] arlen_cntr=8'h01;
reg [1:0] arburst_int_c=0;
reg [1:0] arburst_int_r=0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;
integer num_of_bytes_c = 0;
integer total_bytes = 0;
integer num_of_bytes_r = 0;
integer wrap_base_addr_r = 0;
integer wrap_boundary_r = 0;
reg [7:0] arlen_int_c=0;
integer total_bytes_c = 0;
integer wrap_base_addr_c = 0;
integer wrap_boundary_c = 0;
assign dec_alen_c = incr_addr_c | r_last_int_c;
read_netlist_v8_3
#(.C_AXI_TYPE (1),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_read_fsm (
.S_AXI_INCR_ADDR(incr_addr_c),
.S_AXI_ADDR_EN(addr_en_c),
.S_AXI_SINGLE_TRANS(single_trans_c),
.S_AXI_MUX_SEL(mux_sel_c),
.S_AXI_R_LAST(r_last_c),
.S_AXI_R_LAST_INT(r_last_int_c),
//// AXI Global Signals
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
//// AXI Full/Lite Slave Read (Read side)
.S_AXI_ARLEN(S_AXI_ARLEN),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RLAST(S_AXI_RLAST),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
//// AXI Full/Lite Read Address Signals to BRAM
.S_AXI_RD_EN(rd_en_c)
);
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);
total_bytes = (num_of_bytes_r)*(arlen_int_r+1);
wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);
wrap_boundary_r = wrap_base_addr_r+total_bytes;
//////// combinatorial from interface
arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);
total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1);
wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);
wrap_boundary_c = wrap_base_addr_c+total_bytes_c;
arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);
end
////-------------------------------------------------------------------------
//// BMG address generation
////-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
araddr_reg <= 0;
arburst_int_r <= 0;
num_of_bytes_r <= 0;
end else begin
if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
if (arburst_int_c == 2'b10) begin
if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin
araddr_reg <= wrap_base_addr_c;
end else begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (addr_en_c == 1'b1) begin
araddr_reg <= S_AXI_ARADDR;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
end else if (incr_addr_c == 1'b1) begin
if (arburst_int_r == 2'b10) begin
if(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin
araddr_reg <= wrap_base_addr_r;
end else begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end
end
end
assign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);
////-----------------------------------------------------------------------
//// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
////-----------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
arlen_cntr <= 8'h01;
arlen_int_r <= 0;
end else begin
if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= S_AXI_ARLEN - 1'b1;
end else if (addr_en_c == 1'b1) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
end else if (dec_alen_c == 1'b1) begin
arlen_cntr <= arlen_cntr - 1'b1 ;
end
else begin
arlen_cntr <= arlen_cntr;
end
end
end
assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;
////------------------------------------------------------------------------
//// AXI FULL FSM
//// Mux Selection of ARADDR
//// ARADDR is driven out from the read fsm based on the mux_sel_c
//// Based on mux_sel either ARADDR is given out or the latched ARADDR is
//// given out to BRAM
////------------------------------------------------------------------------
assign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;
////------------------------------------------------------------------------
//// Assign output signals - AXI FULL FSM
////------------------------------------------------------------------------
assign S_AXI_RD_EN = rd_en_c;
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
S_AXI_RID <= 0;
ar_id_r <= 0;
end else begin
if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin
ar_id_r <= S_AXI_ARID;
end else if (rd_en_c == 1'b1) begin
S_AXI_RID <= ar_id_r;
end
end
end
end
endgenerate
endmodule |
module blk_mem_axi_regs_fwd_v8_3
#(parameter C_DATA_WIDTH = 8
)(
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
wire S_READY_I;
reg M_VALID_I;
reg [1:0] ARESET_D;
//assign local signal to its output signal
assign S_READY = S_READY_I;
assign M_VALID = M_VALID_I;
always @(posedge ACLK) begin
ARESET_D <= {ARESET_D[0], ARESET};
end
//Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK or ARESET) begin
if (ARESET == 1'b1) begin
STORAGE_DATA <= 0;
end else begin
if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin
STORAGE_DATA <= S_PAYLOAD_DATA;
end
end
end
always @(posedge ACLK) begin
M_PAYLOAD_DATA = STORAGE_DATA;
end
//M_Valid set to high when we have a completed transfer on slave side
//Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK or ARESET_D) begin
if (ARESET_D != 2'b00) begin
M_VALID_I <= 1'b0;
end else begin
if (S_VALID == 1'b1) begin
//Always set M_VALID_I when slave side is valid
M_VALID_I <= 1'b1;
end else if (M_READY == 1'b1 ) begin
//Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= 1'b0;
end
end
end
//Slave Ready is either when Master side drives M_READY or we have space in our storage data
assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
endmodule |
module blk_mem_gen_v8_3_5_output_stage
#(parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RST = 0,
parameter C_RSTRAM = 0,
parameter C_RST_PRIORITY = "CE",
parameter C_INIT_VAL = "0",
parameter C_HAS_EN = 0,
parameter C_HAS_REGCE = 0,
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_MEM_OUTPUT_REGS = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter NUM_STAGES = 1,
parameter C_EN_ECC_PIPE = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input RST,
input EN,
input REGCE,
input [C_DATA_WIDTH-1:0] DIN_I,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN_I,
input DBITERR_IN_I,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN_I,
input ECCPIPECE,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RST : Determines the presence of the RST port
// C_RSTRAM : Determines if special reset behavior is used
// C_RST_PRIORITY : Determines the priority between CE and SR
// C_INIT_VAL : Initialization value
// C_HAS_EN : Determines the presence of the EN port
// C_HAS_REGCE : Determines the presence of the REGCE port
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// NUM_STAGES : Determines the number of output stages
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// RST : Reset input to reset memory outputs to a user-defined
// reset state
// EN : Enable all read and write operations
// REGCE : Register Clock Enable to control each pipeline output
// register stages
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
// Fix for CR-509792
localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;
// Declare the pipeline registers
// (includes mem output reg, mux pipeline stages, and mux output reg)
reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;
reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;
reg [REG_STAGES-1:0] sbiterr_regs;
reg [REG_STAGES-1:0] dbiterr_regs;
reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL;
reg [C_DATA_WIDTH-1:0] init_val ;
//*********************************************
// Wire off optional inputs based on parameters
//*********************************************
wire en_i;
wire regce_i;
wire rst_i;
// Internal signals
reg [C_DATA_WIDTH-1:0] DIN;
reg [C_ADDRB_WIDTH-1:0] RDADDRECC_IN;
reg SBITERR_IN;
reg DBITERR_IN;
// Internal enable for output registers is tied to user EN or '1' depending
// on parameters
assign en_i = (C_HAS_EN==0 || EN);
// Internal register enable for output registers is tied to user REGCE, EN or
// '1' depending on parameters
// For V4 ECC, REGCE is always 1
// Virtex-4 ECC Not Yet Supported
assign regce_i = ((C_HAS_REGCE==1) && REGCE) ||
((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));
//Internal SRR is tied to user RST or '0' depending on parameters
assign rst_i = (C_HAS_RST==1) && RST;
//****************************************************
// Power on: load up the output registers and latches
//****************************************************
initial begin
if (!($sscanf(init_str, "%h", init_val))) begin
init_val = 0;
end
DOUT = init_val;
RDADDRECC = 0;
SBITERR = 1'b0;
DBITERR = 1'b0;
DIN = {(C_DATA_WIDTH){1'b0}};
RDADDRECC_IN = 0;
SBITERR_IN = 0;
DBITERR_IN = 0;
// This will be one wider than need, but 0 is an error
out_regs = {(REG_STAGES+1){init_val}};
rdaddrecc_regs = 0;
sbiterr_regs = {(REG_STAGES+1){1'b0}};
dbiterr_regs = {(REG_STAGES+1){1'b0}};
end
//***********************************************
// NUM_STAGES = 0 (No output registers. RAM only)
//***********************************************
generate if (NUM_STAGES == 0) begin : zero_stages
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg
always @* begin
DIN = DIN_I;
SBITERR_IN = SBITERR_IN_I;
DBITERR_IN = DBITERR_IN_I;
RDADDRECC_IN = RDADDRECC_IN_I;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg
always @(posedge CLK) begin
if(ECCPIPECE == 1) begin
DIN <= #FLOP_DELAY DIN_I;
SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;
DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;
RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;
end
end
end
endgenerate
//***********************************************
// NUM_STAGES = 1
// (Mem Output Reg only or Mux Output Reg only)
//***********************************************
// Possible valid combinations:
// Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
// +-----------------------------------------+
// | C_RSTRAM_* | Reset Behavior |
// +----------------+------------------------+
// | 0 | Normal Behavior |
// +----------------+------------------------+
// | 1 | Special Behavior |
// +----------------+------------------------+
//
// Normal = REGCE gates reset, as in the case of all families except S3ADSP.
// Special = EN gates reset, as in the case of S3ADSP.
generate if (NUM_STAGES == 1 &&
(C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) ||
C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))
begin : one_stages_norm
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end //end Priority conditions
end //end RST Type conditions
end //end one_stages_norm generate statement
endgenerate
// Special Reset Behavior for S3ADSP
generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp"))
begin : one_stage_splbhv
always @(posedge CLK) begin
if (en_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
end else if (regce_i && !rst_i) begin
DOUT <= #FLOP_DELAY DIN;
end //Output signal assignments
end //end CLK
end //end one_stage_splbhv generate statement
endgenerate
//************************************************************
// NUM_STAGES > 1
// Mem Output Reg + Mux Output Reg
// or
// Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
// or
// Mux Pipeline Stages (>0) + Mux Output Reg
//*************************************************************
generate if (NUM_STAGES > 1) begin : multi_stage
//Asynchronous Reset
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end //end Priority conditions
// Shift the data through the output stages
if (en_i) begin
out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;
rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;
sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;
dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;
end
end //end CLK
end //end multi_stage generate statement
endgenerate
endmodule |
module blk_mem_gen_v8_3_5_softecc_output_reg_stage
#(parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input [C_DATA_WIDTH-1:0] DIN,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
reg [C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule |
module
//***************************************************************
// Port A
assign rsta_outp_stage = RSTA & (~SLEEP);
blk_mem_gen_v8_3_5_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTA),
.C_RSTRAM (C_RSTRAM_A),
.C_RST_PRIORITY (C_RST_PRIORITY_A),
.C_INIT_VAL (C_INITA_VAL),
.C_HAS_EN (C_HAS_ENA),
.C_HAS_REGCE (C_HAS_REGCEA),
.C_DATA_WIDTH (C_READ_WIDTH_A),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_A),
.C_EN_ECC_PIPE (0),
.FLOP_DELAY (FLOP_DELAY))
reg_a
(.CLK (CLKA),
.RST (rsta_outp_stage),//(RSTA),
.EN (ENA),
.REGCE (REGCEA),
.DIN_I (memory_out_a),
.DOUT (DOUTA),
.SBITERR_IN_I (1'b0),
.DBITERR_IN_I (1'b0),
.SBITERR (),
.DBITERR (),
.RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),
.ECCPIPECE (1'b0),
.RDADDRECC ()
);
assign rstb_outp_stage = RSTB & (~SLEEP);
// Port B
blk_mem_gen_v8_3_5_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTB),
.C_RSTRAM (C_RSTRAM_B),
.C_RST_PRIORITY (C_RST_PRIORITY_B),
.C_INIT_VAL (C_INITB_VAL),
.C_HAS_EN (C_HAS_ENB),
.C_HAS_REGCE (C_HAS_REGCEB),
.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_B),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.FLOP_DELAY (FLOP_DELAY))
reg_b
(.CLK (CLKB),
.RST (rstb_outp_stage),//(RSTB),
.EN (ENB),
.REGCE (REGCEB),
.DIN_I (memory_out_b),
.DOUT (dout_i),
.SBITERR_IN_I (sbiterr_in),
.DBITERR_IN_I (dbiterr_in),
.SBITERR (sbiterr_i),
.DBITERR (dbiterr_i),
.RDADDRECC_IN_I (rdaddrecc_in),
.ECCPIPECE (ECCPIPECE),
.RDADDRECC (rdaddrecc_i)
);
//***************************************************************
// Instantiate the Input and Output register stages
//***************************************************************
blk_mem_gen_v8_3_5_softecc_output_reg_stage
#(.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.FLOP_DELAY (FLOP_DELAY))
has_softecc_output_reg_stage
(.CLK (CLKB),
.DIN (dout_i),
.DOUT (DOUTB),
.SBITERR_IN (sbiterr_i),
.DBITERR_IN (dbiterr_i),
.SBITERR (sbiterr_sdp),
.DBITERR (dbiterr_sdp),
.RDADDRECC_IN (rdaddrecc_i),
.RDADDRECC (rdaddrecc_sdp)
);
//****************************************************
// Synchronous collision checks
//****************************************************
// CR 780544 : To make verilog model's collison warnings in consistant with
// vhdl model, the non-blocking assignments are replaced with blocking
// assignments.
generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision = 0;
end
end else begin
is_collision = 0;
end
// If the write port is in READ_FIRST mode, there is no collision
if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin
is_collision = 0;
end
if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin
is_collision = 0;
end
// Only flag if one of the accesses is a write
if (is_collision && (wea_i || web_i)) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B %0s address: %0h\n",
wea_i ? "write" : "read", ADDRA,
web_i ? "write" : "read", ADDRB);
end
end
//****************************************************
// Asynchronous collision checks
//****************************************************
end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll
// Delay A and B addresses in order to mimic setup/hold times
wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA;
wire [0:0] #COLL_DELAY wea_delay = wea_i;
wire #COLL_DELAY ena_delay = ena_i;
wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB;
wire [0:0] #COLL_DELAY web_delay = web_i;
wire #COLL_DELAY enb_delay = enb_i;
// Do the checks w/rt A
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_a = 0;
end
end else begin
is_collision_a = 0;
end
if (ena_i && enb_delay) begin
if(wea_i || web_delay) begin
is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,
web_delay);
end else begin
is_collision_delay_a = 0;
end
end else begin
is_collision_delay_a = 0;
end
// Only flag if B access is a write
if (is_collision_a && web_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, ADDRB);
end else if (is_collision_delay_a && web_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, addrb_delay);
end
end
// Do the checks w/rt B
always @(posedge CLKB) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_b = 0;
end
end else begin
is_collision_b = 0;
end
if (ena_delay && enb_i) begin
if (wea_delay || web_i) begin
is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,
web_i);
end else begin
is_collision_delay_b = 0;
end
end else begin
is_collision_delay_b = 0;
end
// Only flag if A access is a write
if (is_collision_b && wea_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
ADDRA, web_i ? "write" : "read", ADDRB);
end else if (is_collision_delay_b && wea_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
addra_delay, web_i ? "write" : "read", ADDRB);
end
end
end
endgenerate
endmodule |
module blk_mem_gen_v8_3_5
#(parameter C_CORENAME = "blk_mem_gen_v8_3_5",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_ELABORATION_DIR = "",
parameter C_INTERFACE_TYPE = 0,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_CTRL_ECC_ALGO = "NONE",
parameter C_ENABLE_32BIT_ADDRESS = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
//parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_SLEEP_PIN = 0,
parameter C_USE_URAM = 0,
parameter C_EN_RDADDRA_CHG = 0,
parameter C_EN_RDADDRB_CHG = 0,
parameter C_EN_DEEPSLEEP_PIN = 0,
parameter C_EN_SHUTDOWN_PIN = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_COUNT_36K_BRAM = "",
parameter C_COUNT_18K_BRAM = "",
parameter C_EST_POWER_SUMMARY = "",
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input clka,
input rsta,
input ena,
input regcea,
input [C_WEA_WIDTH-1:0] wea,
input [C_ADDRA_WIDTH-1:0] addra,
input [C_WRITE_WIDTH_A-1:0] dina,
output [C_READ_WIDTH_A-1:0] douta,
input clkb,
input rstb,
input enb,
input regceb,
input [C_WEB_WIDTH-1:0] web,
input [C_ADDRB_WIDTH-1:0] addrb,
input [C_WRITE_WIDTH_B-1:0] dinb,
output [C_READ_WIDTH_B-1:0] doutb,
input injectsbiterr,
input injectdbiterr,
output sbiterr,
output dbiterr,
output [C_ADDRB_WIDTH-1:0] rdaddrecc,
input eccpipece,
input sleep,
input deepsleep,
input shutdown,
output rsta_busy,
output rstb_busy,
//AXI BMG Input and Output Port Declarations
//AXI Global Signals
input s_aclk,
input s_aresetn,
//AXI Full/lite slave write (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [31:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input s_axi_awvalid,
output s_axi_awready,
input [C_WRITE_WIDTH_A-1:0] s_axi_wdata,
input [C_WEA_WIDTH-1:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
//AXI Full/lite slave read (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [31:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_WRITE_WIDTH_B-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
input s_axi_rready,
//AXI Full/lite sideband signals
input s_axi_injectsbiterr,
input s_axi_injectdbiterr,
output s_axi_sbiterr,
output s_axi_dbiterr,
output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_HAS_SOFTECC_INPUT_REGS_A :
// C_HAS_SOFTECC_OUTPUT_REGS_B :
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
wire SBITERR;
wire DBITERR;
wire S_AXI_AWREADY;
wire S_AXI_WREADY;
wire S_AXI_BVALID;
wire S_AXI_ARREADY;
wire S_AXI_RLAST;
wire S_AXI_RVALID;
wire S_AXI_SBITERR;
wire S_AXI_DBITERR;
wire [C_WEA_WIDTH-1:0] WEA = wea;
wire [C_ADDRA_WIDTH-1:0] ADDRA = addra;
wire [C_WRITE_WIDTH_A-1:0] DINA = dina;
wire [C_READ_WIDTH_A-1:0] DOUTA;
wire [C_WEB_WIDTH-1:0] WEB = web;
wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb;
wire [C_WRITE_WIDTH_B-1:0] DINB = dinb;
wire [C_READ_WIDTH_B-1:0] DOUTB;
wire [C_ADDRB_WIDTH-1:0] RDADDRECC;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid;
wire [31:0] S_AXI_AWADDR = s_axi_awaddr;
wire [7:0] S_AXI_AWLEN = s_axi_awlen;
wire [2:0] S_AXI_AWSIZE = s_axi_awsize;
wire [1:0] S_AXI_AWBURST = s_axi_awburst;
wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata;
wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [1:0] S_AXI_BRESP;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid;
wire [31:0] S_AXI_ARADDR = s_axi_araddr;
wire [7:0] S_AXI_ARLEN = s_axi_arlen;
wire [2:0] S_AXI_ARSIZE = s_axi_arsize;
wire [1:0] S_AXI_ARBURST = s_axi_arburst;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA;
wire [1:0] S_AXI_RRESP;
wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC;
// Added to fix the simulation warning #CR731605
wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0;
wire ECCPIPECE;
wire SLEEP;
reg RSTA_BUSY = 0;
reg RSTB_BUSY = 0;
// Declaration of internal signals to avoid warnings #927399
wire CLKA;
wire RSTA;
wire ENA;
wire REGCEA;
wire CLKB;
wire RSTB;
wire ENB;
wire REGCEB;
wire INJECTSBITERR;
wire INJECTDBITERR;
wire S_ACLK;
wire S_ARESETN;
wire S_AXI_AWVALID;
wire S_AXI_WLAST;
wire S_AXI_WVALID;
wire S_AXI_BREADY;
wire S_AXI_ARVALID;
wire S_AXI_RREADY;
wire S_AXI_INJECTSBITERR;
wire S_AXI_INJECTDBITERR;
assign CLKA = clka;
assign RSTA = rsta;
assign ENA = ena;
assign REGCEA = regcea;
assign CLKB = clkb;
assign RSTB = rstb;
assign ENB = enb;
assign REGCEB = regceb;
assign INJECTSBITERR = injectsbiterr;
assign INJECTDBITERR = injectdbiterr;
assign ECCPIPECE = eccpipece;
assign SLEEP = sleep;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr;
assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr;
assign s_axi_sbiterr = S_AXI_SBITERR;
assign s_axi_dbiterr = S_AXI_DBITERR;
assign rsta_busy = RSTA_BUSY;
assign rstb_busy = RSTB_BUSY;
assign doutb = DOUTB;
assign douta = DOUTA;
assign rdaddrecc = RDADDRECC;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_rdaddrecc = S_AXI_RDADDRECC;
localparam FLOP_DELAY = 100; // 100 ps
reg injectsbiterr_in;
reg injectdbiterr_in;
reg rsta_in;
reg ena_in;
reg regcea_in;
reg [C_WEA_WIDTH-1:0] wea_in;
reg [C_ADDRA_WIDTH-1:0] addra_in;
reg [C_WRITE_WIDTH_A-1:0] dina_in;
wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;
wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;
wire s_axi_wr_en_c;
wire s_axi_rd_en_c;
wire s_aresetn_a_c;
wire [7:0] s_axi_arlen_c ;
wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;
wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;
wire [1:0] s_axi_rresp_c;
wire s_axi_rlast_c;
wire s_axi_rvalid_c;
wire s_axi_rready_c;
wire regceb_c;
localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;
wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;
wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;
// Safety logic related signals
reg [4:0] RSTA_SHFT_REG = 0;
reg POR_A = 0;
reg [4:0] RSTB_SHFT_REG = 0;
reg POR_B = 0;
reg ENA_dly = 0;
reg ENA_dly_D = 0;
reg ENB_dly = 0;
reg ENB_dly_D = 0;
wire RSTA_I_SAFE;
wire RSTB_I_SAFE;
wire ENA_I_SAFE;
wire ENB_I_SAFE;
reg ram_rstram_a_busy = 0;
reg ram_rstreg_a_busy = 0;
reg ram_rstram_b_busy = 0;
reg ram_rstreg_b_busy = 0;
reg ENA_dly_reg = 0;
reg ENB_dly_reg = 0;
reg ENA_dly_reg_D = 0;
reg ENB_dly_reg_D = 0;
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//**************
// log2int
//**************
function integer log2int (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
cnt= data_value;
for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin
width = width + 1;
end //loop
log2int = width;
end //log2int
endfunction
//**************************************************************************
// FUNCTION : divroundup
// Returns the ceiling value of the division
// Data_value - the quantity to be divided, dividend
// Divisor - the value to divide the data_value by
//**************************************************************************
function integer divroundup (input integer data_value,input integer divisor);
integer div;
begin
div = data_value/divisor;
if ((data_value % divisor) != 0) begin
div = div+1;
end //if
divroundup = div;
end //if
endfunction
localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);
localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB;
//Data Width Number of LSB address bits to be discarded
//1 to 16 1
//17 to 32 2
//33 to 64 3
//65 to 128 4
//129 to 256 5
//257 to 512 6
//513 to 1024 7
// The following two constants determine this.
localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);
localparam C_AXI_OS_WR = 2;
//***********************************************
// INPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage
always @* begin
injectsbiterr_in = INJECTSBITERR;
injectdbiterr_in = INJECTDBITERR;
rsta_in = RSTA;
ena_in = ENA;
regcea_in = REGCEA;
wea_in = WEA;
addra_in = ADDRA;
dina_in = DINA;
end //end always
end //end no_softecc_input_reg_stage
endgenerate
generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage
always @(posedge CLKA) begin
injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;
injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;
rsta_in <= #FLOP_DELAY RSTA;
ena_in <= #FLOP_DELAY ENA;
regcea_in <= #FLOP_DELAY REGCEA;
wea_in <= #FLOP_DELAY WEA;
addra_in <= #FLOP_DELAY ADDRA;
dina_in <= #FLOP_DELAY DINA;
end //end always
end //end input_reg_stages generate statement
endgenerate
//**************************************************************************
// NO SAFETY LOGIC
//**************************************************************************
generate
if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN
assign ENA_I_SAFE = ena_in;
assign ENB_I_SAFE = ENB;
assign RSTA_I_SAFE = rsta_in;
assign RSTB_I_SAFE = RSTB;
end
endgenerate
//***************************************************************************
// SAFETY LOGIC
// Power-ON Reset Generation
//***************************************************************************
generate
if (C_EN_SAFETY_CKT == 1) begin
always @(posedge clka) RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;
always @(posedge clka) POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];
always @(posedge clkb) RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;
always @(posedge clkb) POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0];
assign RSTA_I_SAFE = rsta_in | POR_A;
assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);
end
endgenerate
//-----------------------------------------------------------------------------
// -- RSTA/B_BUSY Generation
//-----------------------------------------------------------------------------
generate
if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG
always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;
always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG
always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;
always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;
end
endgenerate
generate
if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY
always @(*) RSTB_BUSY = 1'b0;
end
endgenerate
generate
if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_NO_REG
always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;
always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG
always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;
always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;
end
endgenerate
//-----------------------------------------------------------------------------
// -- ENA/ENB Generation
//-----------------------------------------------------------------------------
generate
if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG
always @(posedge clka) begin
ENA_dly <= #FLOP_DELAY RSTA_I_SAFE;
ENA_dly_D <= #FLOP_DELAY ENA_dly;
end
assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);
end
endgenerate
generate
if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG
always @(posedge clka) begin
ENA_dly_reg <= #FLOP_DELAY RSTA_I_SAFE;
ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;
end
assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);
end
endgenerate
generate
if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB
assign ENB_I_SAFE = 1'b0;
end
endgenerate
generate
if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG
always @(posedge clkb) begin : PROC_ENB_GEN
ENB_dly <= #FLOP_DELAY RSTB_I_SAFE;
ENB_dly_D <= #FLOP_DELAY ENB_dly;
end
assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG
always @(posedge clkb) begin : PROC_ENB_GEN
ENB_dly_reg <= #FLOP_DELAY RSTB_I_SAFE;
ENB_dly_reg_D <= #FLOP_DELAY ENB_dly_reg;
end
assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);
end
endgenerate
generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module
blk_mem_gen_v8_3_5_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_ALGORITHM (C_ALGORITHM),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_5_inst
(.CLKA (CLKA),
.RSTA (RSTA_I_SAFE),//(rsta_in),
.ENA (ENA_I_SAFE),//(ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB_I_SAFE),//(RSTB),
.ENB (ENB_I_SAFE),//(ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module
localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);
localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);
localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
// localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);
// localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);
localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB;
localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB;
// Data Width Number of LSB address bits to be discarded
// 1 to 16 1
// 17 to 32 2
// 33 to 64 3
// 65 to 128 4
// 129 to 256 5
// 257 to 512 6
// 513 to 1024 7
// The following two constants determine this.
localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;
localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;
wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;
wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;
wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;
assign msb_zero_i = 0;
assign lsb_zero_i = 0;
assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i};
blk_mem_gen_v8_3_5_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_5_inst
(.CLKA (CLKA),
.RSTA (RSTA_I_SAFE),//(rsta_in),
.ENA (ENA_I_SAFE),//(ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB_I_SAFE),//(RSTB),
.ENB (ENB_I_SAFE),//(ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (rdaddrecc_i)
);
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RLAST = s_axi_rlast_c;
assign S_AXI_RVALID = s_axi_rvalid_c;
assign S_AXI_RID = s_axi_rid_c;
assign S_AXI_RRESP = s_axi_rresp_c;
assign s_axi_rready_c = S_AXI_RREADY;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb
assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb
assign regceb_c = REGCEB;
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd
blk_mem_axi_regs_fwd_v8_3
#(.C_DATA_WIDTH (C_AXI_PAYLOAD))
axi_regs_inst (
.ACLK (S_ACLK),
.ARESET (s_aresetn_a_c),
.S_VALID (s_axi_rvalid_c),
.S_READY (s_axi_rready_c),
.S_PAYLOAD_DATA (s_axi_payload_c),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY),
.M_PAYLOAD_DATA (m_axi_payload_c)
);
end
endgenerate
generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module
assign s_aresetn_a_c = !S_ARESETN;
assign S_AXI_BRESP = 2'b00;
assign s_axi_rresp_c = 2'b00;
assign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;
blk_mem_axi_write_wrapper_beh_v8_3
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A),
.C_AXI_OS_WR (C_AXI_OS_WR))
axi_wr_fsm (
// AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
// AXI Full/Lite Slave Write interface
.S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
.S_AXI_BID (S_AXI_BID),
// Signals for BRAM interfac(
.S_AXI_AWADDR_OUT (s_axi_awaddr_out_c),
.S_AXI_WR_EN (s_axi_wr_en_c)
);
blk_mem_axi_read_wrapper_beh_v8_3
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_PIPELINE_STAGES (1),
.C_AXI_ARADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_rd_sm(
//AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
//AXI Full/Lite Read Side
.S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_ARLEN (s_axi_arlen_c),
.S_AXI_ARSIZE (S_AXI_ARSIZE),
.S_AXI_ARBURST (S_AXI_ARBURST),
.S_AXI_ARVALID (S_AXI_ARVALID),
.S_AXI_ARREADY (S_AXI_ARREADY),
.S_AXI_RLAST (s_axi_rlast_c),
.S_AXI_RVALID (s_axi_rvalid_c),
.S_AXI_RREADY (s_axi_rready_c),
.S_AXI_ARID (S_AXI_ARID),
.S_AXI_RID (s_axi_rid_c),
//AXI Full/Lite Read FSM Outputs
.S_AXI_ARADDR_OUT (s_axi_araddr_out_c),
.S_AXI_RD_EN (s_axi_rd_en_c)
);
blk_mem_gen_v8_3_5_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (1),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (1),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (1),
.C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_BYTE_WEB (1),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (0),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (0),
.C_HAS_MUX_OUTPUT_REGS_B (0),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (0),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_5_inst
(.CLKA (S_ACLK),
.RSTA (s_aresetn_a_c),
.ENA (s_axi_wr_en_c),
.REGCEA (regcea_in),
.WEA (S_AXI_WSTRB),
.ADDRA (s_axi_awaddr_out_c),
.DINA (S_AXI_WDATA),
.DOUTA (DOUTA),
.CLKB (S_ACLK),
.RSTB (s_aresetn_a_c),
.ENB (s_axi_rd_en_c),
.REGCEB (regceb_c),
.WEB (WEB_parameterized),
.ADDRB (s_axi_araddr_out_c),
.DINB (DINB),
.DOUTB (s_axi_rdata_c),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.ECCPIPECE (1'b0),
.SLEEP (1'b0),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
endmodule |
module axi_data_fifo_v2_1_ndeep_srl #
(
parameter C_FAMILY = "rtl", // FPGA Family
parameter C_A_WIDTH = 1 // Address Width (>= 1)
)
(
input wire CLK, // Clock
input wire [C_A_WIDTH-1:0] A, // Address
input wire CE, // Clock Enable
input wire D, // Input Data
output wire Q // Output Data
);
localparam integer P_SRLASIZE = 5;
localparam integer P_SRLDEPTH = 32;
localparam integer P_NUMSRLS = (C_A_WIDTH>P_SRLASIZE) ? (2**(C_A_WIDTH-P_SRLASIZE)) : 1;
localparam integer P_SHIFT_DEPTH = 2**C_A_WIDTH;
wire [P_NUMSRLS:0] d_i;
wire [P_NUMSRLS-1:0] q_i;
wire [(C_A_WIDTH>P_SRLASIZE) ? (C_A_WIDTH-1) : (P_SRLASIZE-1) : 0] a_i;
genvar i;
// Instantiate SRLs in carry chain format
assign d_i[0] = D;
assign a_i = A;
generate
if (C_FAMILY == "rtl") begin : gen_rtl_shifter
if (C_A_WIDTH <= P_SRLASIZE) begin : gen_inferred_srl
reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};
always @(posedge CLK)
if (CE)
shift_reg <= {shift_reg[P_SRLDEPTH-2:0], D};
assign Q = shift_reg[a_i];
end else begin : gen_logic_shifter // Very wasteful
reg [P_SHIFT_DEPTH-1:0] shift_reg = {P_SHIFT_DEPTH{1'b0}};
always @(posedge CLK)
if (CE)
shift_reg <= {shift_reg[P_SHIFT_DEPTH-2:0], D};
assign Q = shift_reg[a_i];
end
end else begin : gen_primitive_shifter
for (i=0;i<P_NUMSRLS;i=i+1) begin : gen_srls
SRLC32E
srl_inst
(
.CLK (CLK),
.A (a_i[P_SRLASIZE-1:0]),
.CE (CE),
.D (d_i[i]),
.Q (q_i[i]),
.Q31 (d_i[i+1])
);
end
if (C_A_WIDTH>P_SRLASIZE) begin : gen_srl_mux
generic_baseblocks_v2_1_nto1_mux #
(
.C_RATIO (2**(C_A_WIDTH-P_SRLASIZE)),
.C_SEL_WIDTH (C_A_WIDTH-P_SRLASIZE),
.C_DATAOUT_WIDTH (1),
.C_ONEHOT (0)
)
srl_q_mux_inst
(
.SEL_ONEHOT ({2**(C_A_WIDTH-P_SRLASIZE){1'b0}}),
.SEL (a_i[C_A_WIDTH-1:P_SRLASIZE]),
.IN (q_i),
.OUT (Q)
);
end else begin : gen_no_srl_mux
assign Q = q_i[0];
end
end
endgenerate
endmodule |
module axi_data_fifo_v2_1_ndeep_srl #
(
parameter C_FAMILY = "rtl", // FPGA Family
parameter C_A_WIDTH = 1 // Address Width (>= 1)
)
(
input wire CLK, // Clock
input wire [C_A_WIDTH-1:0] A, // Address
input wire CE, // Clock Enable
input wire D, // Input Data
output wire Q // Output Data
);
localparam integer P_SRLASIZE = 5;
localparam integer P_SRLDEPTH = 32;
localparam integer P_NUMSRLS = (C_A_WIDTH>P_SRLASIZE) ? (2**(C_A_WIDTH-P_SRLASIZE)) : 1;
localparam integer P_SHIFT_DEPTH = 2**C_A_WIDTH;
wire [P_NUMSRLS:0] d_i;
wire [P_NUMSRLS-1:0] q_i;
wire [(C_A_WIDTH>P_SRLASIZE) ? (C_A_WIDTH-1) : (P_SRLASIZE-1) : 0] a_i;
genvar i;
// Instantiate SRLs in carry chain format
assign d_i[0] = D;
assign a_i = A;
generate
if (C_FAMILY == "rtl") begin : gen_rtl_shifter
if (C_A_WIDTH <= P_SRLASIZE) begin : gen_inferred_srl
reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};
always @(posedge CLK)
if (CE)
shift_reg <= {shift_reg[P_SRLDEPTH-2:0], D};
assign Q = shift_reg[a_i];
end else begin : gen_logic_shifter // Very wasteful
reg [P_SHIFT_DEPTH-1:0] shift_reg = {P_SHIFT_DEPTH{1'b0}};
always @(posedge CLK)
if (CE)
shift_reg <= {shift_reg[P_SHIFT_DEPTH-2:0], D};
assign Q = shift_reg[a_i];
end
end else begin : gen_primitive_shifter
for (i=0;i<P_NUMSRLS;i=i+1) begin : gen_srls
SRLC32E
srl_inst
(
.CLK (CLK),
.A (a_i[P_SRLASIZE-1:0]),
.CE (CE),
.D (d_i[i]),
.Q (q_i[i]),
.Q31 (d_i[i+1])
);
end
if (C_A_WIDTH>P_SRLASIZE) begin : gen_srl_mux
generic_baseblocks_v2_1_nto1_mux #
(
.C_RATIO (2**(C_A_WIDTH-P_SRLASIZE)),
.C_SEL_WIDTH (C_A_WIDTH-P_SRLASIZE),
.C_DATAOUT_WIDTH (1),
.C_ONEHOT (0)
)
srl_q_mux_inst
(
.SEL_ONEHOT ({2**(C_A_WIDTH-P_SRLASIZE){1'b0}}),
.SEL (a_i[C_A_WIDTH-1:P_SRLASIZE]),
.IN (q_i),
.OUT (Q)
);
end else begin : gen_no_srl_mux
assign Q = q_i[0];
end
end
endgenerate
endmodule |
module axi_data_fifo_v2_1_ndeep_srl #
(
parameter C_FAMILY = "rtl", // FPGA Family
parameter C_A_WIDTH = 1 // Address Width (>= 1)
)
(
input wire CLK, // Clock
input wire [C_A_WIDTH-1:0] A, // Address
input wire CE, // Clock Enable
input wire D, // Input Data
output wire Q // Output Data
);
localparam integer P_SRLASIZE = 5;
localparam integer P_SRLDEPTH = 32;
localparam integer P_NUMSRLS = (C_A_WIDTH>P_SRLASIZE) ? (2**(C_A_WIDTH-P_SRLASIZE)) : 1;
localparam integer P_SHIFT_DEPTH = 2**C_A_WIDTH;
wire [P_NUMSRLS:0] d_i;
wire [P_NUMSRLS-1:0] q_i;
wire [(C_A_WIDTH>P_SRLASIZE) ? (C_A_WIDTH-1) : (P_SRLASIZE-1) : 0] a_i;
genvar i;
// Instantiate SRLs in carry chain format
assign d_i[0] = D;
assign a_i = A;
generate
if (C_FAMILY == "rtl") begin : gen_rtl_shifter
if (C_A_WIDTH <= P_SRLASIZE) begin : gen_inferred_srl
reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};
always @(posedge CLK)
if (CE)
shift_reg <= {shift_reg[P_SRLDEPTH-2:0], D};
assign Q = shift_reg[a_i];
end else begin : gen_logic_shifter // Very wasteful
reg [P_SHIFT_DEPTH-1:0] shift_reg = {P_SHIFT_DEPTH{1'b0}};
always @(posedge CLK)
if (CE)
shift_reg <= {shift_reg[P_SHIFT_DEPTH-2:0], D};
assign Q = shift_reg[a_i];
end
end else begin : gen_primitive_shifter
for (i=0;i<P_NUMSRLS;i=i+1) begin : gen_srls
SRLC32E
srl_inst
(
.CLK (CLK),
.A (a_i[P_SRLASIZE-1:0]),
.CE (CE),
.D (d_i[i]),
.Q (q_i[i]),
.Q31 (d_i[i+1])
);
end
if (C_A_WIDTH>P_SRLASIZE) begin : gen_srl_mux
generic_baseblocks_v2_1_nto1_mux #
(
.C_RATIO (2**(C_A_WIDTH-P_SRLASIZE)),
.C_SEL_WIDTH (C_A_WIDTH-P_SRLASIZE),
.C_DATAOUT_WIDTH (1),
.C_ONEHOT (0)
)
srl_q_mux_inst
(
.SEL_ONEHOT ({2**(C_A_WIDTH-P_SRLASIZE){1'b0}}),
.SEL (a_i[C_A_WIDTH-1:P_SRLASIZE]),
.IN (q_i),
.OUT (Q)
);
end else begin : gen_no_srl_mux
assign Q = q_i[0];
end
end
endgenerate
endmodule |
module axi_data_fifo_v2_1_ndeep_srl #
(
parameter C_FAMILY = "rtl", // FPGA Family
parameter C_A_WIDTH = 1 // Address Width (>= 1)
)
(
input wire CLK, // Clock
input wire [C_A_WIDTH-1:0] A, // Address
input wire CE, // Clock Enable
input wire D, // Input Data
output wire Q // Output Data
);
localparam integer P_SRLASIZE = 5;
localparam integer P_SRLDEPTH = 32;
localparam integer P_NUMSRLS = (C_A_WIDTH>P_SRLASIZE) ? (2**(C_A_WIDTH-P_SRLASIZE)) : 1;
localparam integer P_SHIFT_DEPTH = 2**C_A_WIDTH;
wire [P_NUMSRLS:0] d_i;
wire [P_NUMSRLS-1:0] q_i;
wire [(C_A_WIDTH>P_SRLASIZE) ? (C_A_WIDTH-1) : (P_SRLASIZE-1) : 0] a_i;
genvar i;
// Instantiate SRLs in carry chain format
assign d_i[0] = D;
assign a_i = A;
generate
if (C_FAMILY == "rtl") begin : gen_rtl_shifter
if (C_A_WIDTH <= P_SRLASIZE) begin : gen_inferred_srl
reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};
always @(posedge CLK)
if (CE)
shift_reg <= {shift_reg[P_SRLDEPTH-2:0], D};
assign Q = shift_reg[a_i];
end else begin : gen_logic_shifter // Very wasteful
reg [P_SHIFT_DEPTH-1:0] shift_reg = {P_SHIFT_DEPTH{1'b0}};
always @(posedge CLK)
if (CE)
shift_reg <= {shift_reg[P_SHIFT_DEPTH-2:0], D};
assign Q = shift_reg[a_i];
end
end else begin : gen_primitive_shifter
for (i=0;i<P_NUMSRLS;i=i+1) begin : gen_srls
SRLC32E
srl_inst
(
.CLK (CLK),
.A (a_i[P_SRLASIZE-1:0]),
.CE (CE),
.D (d_i[i]),
.Q (q_i[i]),
.Q31 (d_i[i+1])
);
end
if (C_A_WIDTH>P_SRLASIZE) begin : gen_srl_mux
generic_baseblocks_v2_1_nto1_mux #
(
.C_RATIO (2**(C_A_WIDTH-P_SRLASIZE)),
.C_SEL_WIDTH (C_A_WIDTH-P_SRLASIZE),
.C_DATAOUT_WIDTH (1),
.C_ONEHOT (0)
)
srl_q_mux_inst
(
.SEL_ONEHOT ({2**(C_A_WIDTH-P_SRLASIZE){1'b0}}),
.SEL (a_i[C_A_WIDTH-1:P_SRLASIZE]),
.IN (q_i),
.OUT (Q)
);
end else begin : gen_no_srl_mux
assign Q = q_i[0];
end
end
endgenerate
endmodule |
module axi_protocol_converter_v2_1_b2s #(
parameter C_S_AXI_PROTOCOL = 0,
// Width of all master and slave ID signals.
// Range: >= 1.
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 30,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire aclk ,
input wire aresetn ,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr ,
input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [2:0] s_axi_awsize ,
input wire [1:0] s_axi_awburst ,
input wire [2:0] s_axi_awprot ,
input wire s_axi_awvalid ,
output wire s_axi_awready ,
// Slave Interface Write Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata ,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb ,
input wire s_axi_wlast ,
input wire s_axi_wvalid ,
output wire s_axi_wready ,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid ,
output wire [1:0] s_axi_bresp ,
output wire s_axi_bvalid ,
input wire s_axi_bready ,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr ,
input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [2:0] s_axi_arsize ,
input wire [1:0] s_axi_arburst ,
input wire [2:0] s_axi_arprot ,
input wire s_axi_arvalid ,
output wire s_axi_arready ,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid ,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata ,
output wire [1:0] s_axi_rresp ,
output wire s_axi_rlast ,
output wire s_axi_rvalid ,
input wire s_axi_rready ,
// Slave Interface Write Address Ports
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr ,
output wire [2:0] m_axi_awprot ,
output wire m_axi_awvalid ,
input wire m_axi_awready ,
// Slave Interface Write Data Ports
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata ,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb ,
output wire m_axi_wvalid ,
input wire m_axi_wready ,
// Slave Interface Write Response Ports
input wire [1:0] m_axi_bresp ,
input wire m_axi_bvalid ,
output wire m_axi_bready ,
// Slave Interface Read Address Ports
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr ,
output wire [2:0] m_axi_arprot ,
output wire m_axi_arvalid ,
input wire m_axi_arready ,
// Slave Interface Read Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata ,
input wire [1:0] m_axi_rresp ,
input wire m_axi_rvalid ,
output wire m_axi_rready
);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
reg areset_d1;
always @(posedge aclk)
areset_d1 <= ~aresetn;
// AW/W/B channel internal communication
wire b_push;
wire [C_AXI_ID_WIDTH-1:0] b_awid;
wire [7:0] b_awlen;
wire b_full;
wire [C_AXI_ID_WIDTH-1:0] si_rs_awid;
wire [C_AXI_ADDR_WIDTH-1:0] si_rs_awaddr;
wire [8-1:0] si_rs_awlen;
wire [3-1:0] si_rs_awsize;
wire [2-1:0] si_rs_awburst;
wire [3-1:0] si_rs_awprot;
wire si_rs_awvalid;
wire si_rs_awready;
wire [C_AXI_DATA_WIDTH-1:0] si_rs_wdata;
wire [C_AXI_DATA_WIDTH/8-1:0] si_rs_wstrb;
wire si_rs_wlast;
wire si_rs_wvalid;
wire si_rs_wready;
wire [C_AXI_ID_WIDTH-1:0] si_rs_bid;
wire [2-1:0] si_rs_bresp;
wire si_rs_bvalid;
wire si_rs_bready;
wire [C_AXI_ID_WIDTH-1:0] si_rs_arid;
wire [C_AXI_ADDR_WIDTH-1:0] si_rs_araddr;
wire [8-1:0] si_rs_arlen;
wire [3-1:0] si_rs_arsize;
wire [2-1:0] si_rs_arburst;
wire [3-1:0] si_rs_arprot;
wire si_rs_arvalid;
wire si_rs_arready;
wire [C_AXI_ID_WIDTH-1:0] si_rs_rid;
wire [C_AXI_DATA_WIDTH-1:0] si_rs_rdata;
wire [2-1:0] si_rs_rresp;
wire si_rs_rlast;
wire si_rs_rvalid;
wire si_rs_rready;
wire [C_AXI_ADDR_WIDTH-1:0] rs_mi_awaddr;
wire rs_mi_awvalid;
wire rs_mi_awready;
wire [C_AXI_DATA_WIDTH-1:0] rs_mi_wdata;
wire [C_AXI_DATA_WIDTH/8-1:0] rs_mi_wstrb;
wire rs_mi_wvalid;
wire rs_mi_wready;
wire [2-1:0] rs_mi_bresp;
wire rs_mi_bvalid;
wire rs_mi_bready;
wire [C_AXI_ADDR_WIDTH-1:0] rs_mi_araddr;
wire rs_mi_arvalid;
wire rs_mi_arready;
wire [C_AXI_DATA_WIDTH-1:0] rs_mi_rdata;
wire [2-1:0] rs_mi_rresp;
wire rs_mi_rvalid;
wire rs_mi_rready;
axi_register_slice_v2_1_axi_register_slice #(
.C_AXI_PROTOCOL ( C_S_AXI_PROTOCOL ) ,
.C_AXI_ID_WIDTH ( C_AXI_ID_WIDTH ) ,
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_AXI_DATA_WIDTH ( C_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_USER_SIGNALS ( 0 ) ,
.C_AXI_AWUSER_WIDTH ( 1 ) ,
.C_AXI_ARUSER_WIDTH ( 1 ) ,
.C_AXI_WUSER_WIDTH ( 1 ) ,
.C_AXI_RUSER_WIDTH ( 1 ) ,
.C_AXI_BUSER_WIDTH ( 1 ) ,
.C_REG_CONFIG_AW ( 1 ) ,
.C_REG_CONFIG_AR ( 1 ) ,
.C_REG_CONFIG_W ( 0 ) ,
.C_REG_CONFIG_R ( 1 ) ,
.C_REG_CONFIG_B ( 1 )
) SI_REG (
.aresetn ( aresetn ) ,
.aclk ( aclk ) ,
.s_axi_awid ( s_axi_awid ) ,
.s_axi_awaddr ( s_axi_awaddr ) ,
.s_axi_awlen ( s_axi_awlen ) ,
.s_axi_awsize ( s_axi_awsize ) ,
.s_axi_awburst ( s_axi_awburst ) ,
.s_axi_awlock ( {((C_S_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}} ) ,
.s_axi_awcache ( 4'h0 ) ,
.s_axi_awprot ( s_axi_awprot ) ,
.s_axi_awqos ( 4'h0 ) ,
.s_axi_awuser ( 1'b0 ) ,
.s_axi_awvalid ( s_axi_awvalid ) ,
.s_axi_awready ( s_axi_awready ) ,
.s_axi_awregion ( 4'h0 ) ,
.s_axi_wid ( {C_AXI_ID_WIDTH{1'b0}} ) ,
.s_axi_wdata ( s_axi_wdata ) ,
.s_axi_wstrb ( s_axi_wstrb ) ,
.s_axi_wlast ( s_axi_wlast ) ,
.s_axi_wuser ( 1'b0 ) ,
.s_axi_wvalid ( s_axi_wvalid ) ,
.s_axi_wready ( s_axi_wready ) ,
.s_axi_bid ( s_axi_bid ) ,
.s_axi_bresp ( s_axi_bresp ) ,
.s_axi_buser ( ) ,
.s_axi_bvalid ( s_axi_bvalid ) ,
.s_axi_bready ( s_axi_bready ) ,
.s_axi_arid ( s_axi_arid ) ,
.s_axi_araddr ( s_axi_araddr ) ,
.s_axi_arlen ( s_axi_arlen ) ,
.s_axi_arsize ( s_axi_arsize ) ,
.s_axi_arburst ( s_axi_arburst ) ,
.s_axi_arlock ( {((C_S_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}} ) ,
.s_axi_arcache ( 4'h0 ) ,
.s_axi_arprot ( s_axi_arprot ) ,
.s_axi_arqos ( 4'h0 ) ,
.s_axi_aruser ( 1'b0 ) ,
.s_axi_arvalid ( s_axi_arvalid ) ,
.s_axi_arready ( s_axi_arready ) ,
.s_axi_arregion ( 4'h0 ) ,
.s_axi_rid ( s_axi_rid ) ,
.s_axi_rdata ( s_axi_rdata ) ,
.s_axi_rresp ( s_axi_rresp ) ,
.s_axi_rlast ( s_axi_rlast ) ,
.s_axi_ruser ( ) ,
.s_axi_rvalid ( s_axi_rvalid ) ,
.s_axi_rready ( s_axi_rready ) ,
.m_axi_awid ( si_rs_awid ) ,
.m_axi_awaddr ( si_rs_awaddr ) ,
.m_axi_awlen ( si_rs_awlen[((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] ) ,
.m_axi_awsize ( si_rs_awsize ) ,
.m_axi_awburst ( si_rs_awburst ) ,
.m_axi_awlock ( ) ,
.m_axi_awcache ( ) ,
.m_axi_awprot ( si_rs_awprot ) ,
.m_axi_awqos ( ) ,
.m_axi_awuser ( ) ,
.m_axi_awvalid ( si_rs_awvalid ) ,
.m_axi_awready ( si_rs_awready ) ,
.m_axi_awregion ( ) ,
.m_axi_wid ( ) ,
.m_axi_wdata ( si_rs_wdata ) ,
.m_axi_wstrb ( si_rs_wstrb ) ,
.m_axi_wlast ( si_rs_wlast ) ,
.m_axi_wuser ( ) ,
.m_axi_wvalid ( si_rs_wvalid ) ,
.m_axi_wready ( si_rs_wready ) ,
.m_axi_bid ( si_rs_bid ) ,
.m_axi_bresp ( si_rs_bresp ) ,
.m_axi_buser ( 1'b0 ) ,
.m_axi_bvalid ( si_rs_bvalid ) ,
.m_axi_bready ( si_rs_bready ) ,
.m_axi_arid ( si_rs_arid ) ,
.m_axi_araddr ( si_rs_araddr ) ,
.m_axi_arlen ( si_rs_arlen[((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] ) ,
.m_axi_arsize ( si_rs_arsize ) ,
.m_axi_arburst ( si_rs_arburst ) ,
.m_axi_arlock ( ) ,
.m_axi_arcache ( ) ,
.m_axi_arprot ( si_rs_arprot ) ,
.m_axi_arqos ( ) ,
.m_axi_aruser ( ) ,
.m_axi_arvalid ( si_rs_arvalid ) ,
.m_axi_arready ( si_rs_arready ) ,
.m_axi_arregion ( ) ,
.m_axi_rid ( si_rs_rid ) ,
.m_axi_rdata ( si_rs_rdata ) ,
.m_axi_rresp ( si_rs_rresp ) ,
.m_axi_rlast ( si_rs_rlast ) ,
.m_axi_ruser ( 1'b0 ) ,
.m_axi_rvalid ( si_rs_rvalid ) ,
.m_axi_rready ( si_rs_rready )
);
generate
if (C_AXI_SUPPORTS_WRITE == 1) begin : WR
axi_protocol_converter_v2_1_b2s_aw_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH ),
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
aw_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_awid ( si_rs_awid ) ,
.s_awaddr ( si_rs_awaddr ) ,
.s_awlen ( (C_S_AXI_PROTOCOL == 1) ? {4'h0,si_rs_awlen[3:0]} : si_rs_awlen),
.s_awsize ( si_rs_awsize ) ,
.s_awburst ( si_rs_awburst ) ,
.s_awvalid ( si_rs_awvalid ) ,
.s_awready ( si_rs_awready ) ,
.m_awvalid ( rs_mi_awvalid ) ,
.m_awaddr ( rs_mi_awaddr ) ,
.m_awready ( rs_mi_awready ) ,
.b_push ( b_push ) ,
.b_awid ( b_awid ) ,
.b_awlen ( b_awlen ) ,
.b_full ( b_full )
);
axi_protocol_converter_v2_1_b2s_b_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH )
)
b_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_bid ( si_rs_bid ) ,
.s_bresp ( si_rs_bresp ) ,
.s_bvalid ( si_rs_bvalid ) ,
.s_bready ( si_rs_bready ) ,
.m_bready ( rs_mi_bready ) ,
.m_bvalid ( rs_mi_bvalid ) ,
.m_bresp ( rs_mi_bresp ) ,
.b_push ( b_push ) ,
.b_awid ( b_awid ) ,
.b_awlen ( b_awlen ) ,
.b_full ( b_full ) ,
.b_resp_rdy ( si_rs_awready )
);
assign rs_mi_wdata = si_rs_wdata;
assign rs_mi_wstrb = si_rs_wstrb;
assign rs_mi_wvalid = si_rs_wvalid;
assign si_rs_wready = rs_mi_wready;
end else begin : NO_WR
assign rs_mi_awaddr = {C_AXI_ADDR_WIDTH{1'b0}};
assign rs_mi_awvalid = 1'b0;
assign si_rs_awready = 1'b0;
assign rs_mi_wdata = {C_AXI_DATA_WIDTH{1'b0}};
assign rs_mi_wstrb = {C_AXI_DATA_WIDTH/8{1'b0}};
assign rs_mi_wvalid = 1'b0;
assign si_rs_wready = 1'b0;
assign rs_mi_bready = 1'b0;
assign si_rs_bvalid = 1'b0;
assign si_rs_bresp = 2'b00;
assign si_rs_bid = {C_AXI_ID_WIDTH{1'b0}};
end
endgenerate
// AR/R channel communication
wire r_push ;
wire [C_AXI_ID_WIDTH-1:0] r_arid ;
wire r_rlast ;
wire r_full ;
generate
if (C_AXI_SUPPORTS_READ == 1) begin : RD
axi_protocol_converter_v2_1_b2s_ar_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH ),
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
ar_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_arid ( si_rs_arid ) ,
.s_araddr ( si_rs_araddr ) ,
.s_arlen ( (C_S_AXI_PROTOCOL == 1) ? {4'h0,si_rs_arlen[3:0]} : si_rs_arlen),
.s_arsize ( si_rs_arsize ) ,
.s_arburst ( si_rs_arburst ) ,
.s_arvalid ( si_rs_arvalid ) ,
.s_arready ( si_rs_arready ) ,
.m_arvalid ( rs_mi_arvalid ) ,
.m_araddr ( rs_mi_araddr ) ,
.m_arready ( rs_mi_arready ) ,
.r_push ( r_push ) ,
.r_arid ( r_arid ) ,
.r_rlast ( r_rlast ) ,
.r_full ( r_full )
);
axi_protocol_converter_v2_1_b2s_r_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH ),
.C_DATA_WIDTH ( C_AXI_DATA_WIDTH )
)
r_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_rid ( si_rs_rid ) ,
.s_rdata ( si_rs_rdata ) ,
.s_rresp ( si_rs_rresp ) ,
.s_rlast ( si_rs_rlast ) ,
.s_rvalid ( si_rs_rvalid ) ,
.s_rready ( si_rs_rready ) ,
.m_rvalid ( rs_mi_rvalid ) ,
.m_rready ( rs_mi_rready ) ,
.m_rdata ( rs_mi_rdata ) ,
.m_rresp ( rs_mi_rresp ) ,
.r_push ( r_push ) ,
.r_full ( r_full ) ,
.r_arid ( r_arid ) ,
.r_rlast ( r_rlast )
);
end else begin : NO_RD
assign rs_mi_araddr = {C_AXI_ADDR_WIDTH{1'b0}};
assign rs_mi_arvalid = 1'b0;
assign si_rs_arready = 1'b0;
assign si_rs_rlast = 1'b1;
assign si_rs_rdata = {C_AXI_DATA_WIDTH{1'b0}};
assign si_rs_rvalid = 1'b0;
assign si_rs_rresp = 2'b00;
assign si_rs_rid = {C_AXI_ID_WIDTH{1'b0}};
assign rs_mi_rready = 1'b0;
end
endgenerate
axi_register_slice_v2_1_axi_register_slice #(
.C_AXI_PROTOCOL ( 2 ) ,
.C_AXI_ID_WIDTH ( 1 ) ,
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_AXI_DATA_WIDTH ( C_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_USER_SIGNALS ( 0 ) ,
.C_AXI_AWUSER_WIDTH ( 1 ) ,
.C_AXI_ARUSER_WIDTH ( 1 ) ,
.C_AXI_WUSER_WIDTH ( 1 ) ,
.C_AXI_RUSER_WIDTH ( 1 ) ,
.C_AXI_BUSER_WIDTH ( 1 ) ,
.C_REG_CONFIG_AW ( 0 ) ,
.C_REG_CONFIG_AR ( 0 ) ,
.C_REG_CONFIG_W ( 0 ) ,
.C_REG_CONFIG_R ( 0 ) ,
.C_REG_CONFIG_B ( 0 )
) MI_REG (
.aresetn ( aresetn ) ,
.aclk ( aclk ) ,
.s_axi_awid ( 1'b0 ) ,
.s_axi_awaddr ( rs_mi_awaddr ) ,
.s_axi_awlen ( 8'h00 ) ,
.s_axi_awsize ( 3'b000 ) ,
.s_axi_awburst ( 2'b01 ) ,
.s_axi_awlock ( 1'b0 ) ,
.s_axi_awcache ( 4'h0 ) ,
.s_axi_awprot ( si_rs_awprot ) ,
.s_axi_awqos ( 4'h0 ) ,
.s_axi_awuser ( 1'b0 ) ,
.s_axi_awvalid ( rs_mi_awvalid ) ,
.s_axi_awready ( rs_mi_awready ) ,
.s_axi_awregion ( 4'h0 ) ,
.s_axi_wid ( 1'b0 ) ,
.s_axi_wdata ( rs_mi_wdata ) ,
.s_axi_wstrb ( rs_mi_wstrb ) ,
.s_axi_wlast ( 1'b1 ) ,
.s_axi_wuser ( 1'b0 ) ,
.s_axi_wvalid ( rs_mi_wvalid ) ,
.s_axi_wready ( rs_mi_wready ) ,
.s_axi_bid ( ) ,
.s_axi_bresp ( rs_mi_bresp ) ,
.s_axi_buser ( ) ,
.s_axi_bvalid ( rs_mi_bvalid ) ,
.s_axi_bready ( rs_mi_bready ) ,
.s_axi_arid ( 1'b0 ) ,
.s_axi_araddr ( rs_mi_araddr ) ,
.s_axi_arlen ( 8'h00 ) ,
.s_axi_arsize ( 3'b000 ) ,
.s_axi_arburst ( 2'b01 ) ,
.s_axi_arlock ( 1'b0 ) ,
.s_axi_arcache ( 4'h0 ) ,
.s_axi_arprot ( si_rs_arprot ) ,
.s_axi_arqos ( 4'h0 ) ,
.s_axi_aruser ( 1'b0 ) ,
.s_axi_arvalid ( rs_mi_arvalid ) ,
.s_axi_arready ( rs_mi_arready ) ,
.s_axi_arregion ( 4'h0 ) ,
.s_axi_rid ( ) ,
.s_axi_rdata ( rs_mi_rdata ) ,
.s_axi_rresp ( rs_mi_rresp ) ,
.s_axi_rlast ( ) ,
.s_axi_ruser ( ) ,
.s_axi_rvalid ( rs_mi_rvalid ) ,
.s_axi_rready ( rs_mi_rready ) ,
.m_axi_awid ( ) ,
.m_axi_awaddr ( m_axi_awaddr ) ,
.m_axi_awlen ( ) ,
.m_axi_awsize ( ) ,
.m_axi_awburst ( ) ,
.m_axi_awlock ( ) ,
.m_axi_awcache ( ) ,
.m_axi_awprot ( m_axi_awprot ) ,
.m_axi_awqos ( ) ,
.m_axi_awuser ( ) ,
.m_axi_awvalid ( m_axi_awvalid ) ,
.m_axi_awready ( m_axi_awready ) ,
.m_axi_awregion ( ) ,
.m_axi_wid ( ) ,
.m_axi_wdata ( m_axi_wdata ) ,
.m_axi_wstrb ( m_axi_wstrb ) ,
.m_axi_wlast ( ) ,
.m_axi_wuser ( ) ,
.m_axi_wvalid ( m_axi_wvalid ) ,
.m_axi_wready ( m_axi_wready ) ,
.m_axi_bid ( 1'b0 ) ,
.m_axi_bresp ( m_axi_bresp ) ,
.m_axi_buser ( 1'b0 ) ,
.m_axi_bvalid ( m_axi_bvalid ) ,
.m_axi_bready ( m_axi_bready ) ,
.m_axi_arid ( ) ,
.m_axi_araddr ( m_axi_araddr ) ,
.m_axi_arlen ( ) ,
.m_axi_arsize ( ) ,
.m_axi_arburst ( ) ,
.m_axi_arlock ( ) ,
.m_axi_arcache ( ) ,
.m_axi_arprot ( m_axi_arprot ) ,
.m_axi_arqos ( ) ,
.m_axi_aruser ( ) ,
.m_axi_arvalid ( m_axi_arvalid ) ,
.m_axi_arready ( m_axi_arready ) ,
.m_axi_arregion ( ) ,
.m_axi_rid ( 1'b0 ) ,
.m_axi_rdata ( m_axi_rdata ) ,
.m_axi_rresp ( m_axi_rresp ) ,
.m_axi_rlast ( 1'b1 ) ,
.m_axi_ruser ( 1'b0 ) ,
.m_axi_rvalid ( m_axi_rvalid ) ,
.m_axi_rready ( m_axi_rready )
);
endmodule |
module axi_protocol_converter_v2_1_b2s #(
parameter C_S_AXI_PROTOCOL = 0,
// Width of all master and slave ID signals.
// Range: >= 1.
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 30,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire aclk ,
input wire aresetn ,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr ,
input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [2:0] s_axi_awsize ,
input wire [1:0] s_axi_awburst ,
input wire [2:0] s_axi_awprot ,
input wire s_axi_awvalid ,
output wire s_axi_awready ,
// Slave Interface Write Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata ,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb ,
input wire s_axi_wlast ,
input wire s_axi_wvalid ,
output wire s_axi_wready ,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid ,
output wire [1:0] s_axi_bresp ,
output wire s_axi_bvalid ,
input wire s_axi_bready ,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr ,
input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [2:0] s_axi_arsize ,
input wire [1:0] s_axi_arburst ,
input wire [2:0] s_axi_arprot ,
input wire s_axi_arvalid ,
output wire s_axi_arready ,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid ,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata ,
output wire [1:0] s_axi_rresp ,
output wire s_axi_rlast ,
output wire s_axi_rvalid ,
input wire s_axi_rready ,
// Slave Interface Write Address Ports
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr ,
output wire [2:0] m_axi_awprot ,
output wire m_axi_awvalid ,
input wire m_axi_awready ,
// Slave Interface Write Data Ports
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata ,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb ,
output wire m_axi_wvalid ,
input wire m_axi_wready ,
// Slave Interface Write Response Ports
input wire [1:0] m_axi_bresp ,
input wire m_axi_bvalid ,
output wire m_axi_bready ,
// Slave Interface Read Address Ports
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr ,
output wire [2:0] m_axi_arprot ,
output wire m_axi_arvalid ,
input wire m_axi_arready ,
// Slave Interface Read Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata ,
input wire [1:0] m_axi_rresp ,
input wire m_axi_rvalid ,
output wire m_axi_rready
);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
reg areset_d1;
always @(posedge aclk)
areset_d1 <= ~aresetn;
// AW/W/B channel internal communication
wire b_push;
wire [C_AXI_ID_WIDTH-1:0] b_awid;
wire [7:0] b_awlen;
wire b_full;
wire [C_AXI_ID_WIDTH-1:0] si_rs_awid;
wire [C_AXI_ADDR_WIDTH-1:0] si_rs_awaddr;
wire [8-1:0] si_rs_awlen;
wire [3-1:0] si_rs_awsize;
wire [2-1:0] si_rs_awburst;
wire [3-1:0] si_rs_awprot;
wire si_rs_awvalid;
wire si_rs_awready;
wire [C_AXI_DATA_WIDTH-1:0] si_rs_wdata;
wire [C_AXI_DATA_WIDTH/8-1:0] si_rs_wstrb;
wire si_rs_wlast;
wire si_rs_wvalid;
wire si_rs_wready;
wire [C_AXI_ID_WIDTH-1:0] si_rs_bid;
wire [2-1:0] si_rs_bresp;
wire si_rs_bvalid;
wire si_rs_bready;
wire [C_AXI_ID_WIDTH-1:0] si_rs_arid;
wire [C_AXI_ADDR_WIDTH-1:0] si_rs_araddr;
wire [8-1:0] si_rs_arlen;
wire [3-1:0] si_rs_arsize;
wire [2-1:0] si_rs_arburst;
wire [3-1:0] si_rs_arprot;
wire si_rs_arvalid;
wire si_rs_arready;
wire [C_AXI_ID_WIDTH-1:0] si_rs_rid;
wire [C_AXI_DATA_WIDTH-1:0] si_rs_rdata;
wire [2-1:0] si_rs_rresp;
wire si_rs_rlast;
wire si_rs_rvalid;
wire si_rs_rready;
wire [C_AXI_ADDR_WIDTH-1:0] rs_mi_awaddr;
wire rs_mi_awvalid;
wire rs_mi_awready;
wire [C_AXI_DATA_WIDTH-1:0] rs_mi_wdata;
wire [C_AXI_DATA_WIDTH/8-1:0] rs_mi_wstrb;
wire rs_mi_wvalid;
wire rs_mi_wready;
wire [2-1:0] rs_mi_bresp;
wire rs_mi_bvalid;
wire rs_mi_bready;
wire [C_AXI_ADDR_WIDTH-1:0] rs_mi_araddr;
wire rs_mi_arvalid;
wire rs_mi_arready;
wire [C_AXI_DATA_WIDTH-1:0] rs_mi_rdata;
wire [2-1:0] rs_mi_rresp;
wire rs_mi_rvalid;
wire rs_mi_rready;
axi_register_slice_v2_1_axi_register_slice #(
.C_AXI_PROTOCOL ( C_S_AXI_PROTOCOL ) ,
.C_AXI_ID_WIDTH ( C_AXI_ID_WIDTH ) ,
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_AXI_DATA_WIDTH ( C_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_USER_SIGNALS ( 0 ) ,
.C_AXI_AWUSER_WIDTH ( 1 ) ,
.C_AXI_ARUSER_WIDTH ( 1 ) ,
.C_AXI_WUSER_WIDTH ( 1 ) ,
.C_AXI_RUSER_WIDTH ( 1 ) ,
.C_AXI_BUSER_WIDTH ( 1 ) ,
.C_REG_CONFIG_AW ( 1 ) ,
.C_REG_CONFIG_AR ( 1 ) ,
.C_REG_CONFIG_W ( 0 ) ,
.C_REG_CONFIG_R ( 1 ) ,
.C_REG_CONFIG_B ( 1 )
) SI_REG (
.aresetn ( aresetn ) ,
.aclk ( aclk ) ,
.s_axi_awid ( s_axi_awid ) ,
.s_axi_awaddr ( s_axi_awaddr ) ,
.s_axi_awlen ( s_axi_awlen ) ,
.s_axi_awsize ( s_axi_awsize ) ,
.s_axi_awburst ( s_axi_awburst ) ,
.s_axi_awlock ( {((C_S_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}} ) ,
.s_axi_awcache ( 4'h0 ) ,
.s_axi_awprot ( s_axi_awprot ) ,
.s_axi_awqos ( 4'h0 ) ,
.s_axi_awuser ( 1'b0 ) ,
.s_axi_awvalid ( s_axi_awvalid ) ,
.s_axi_awready ( s_axi_awready ) ,
.s_axi_awregion ( 4'h0 ) ,
.s_axi_wid ( {C_AXI_ID_WIDTH{1'b0}} ) ,
.s_axi_wdata ( s_axi_wdata ) ,
.s_axi_wstrb ( s_axi_wstrb ) ,
.s_axi_wlast ( s_axi_wlast ) ,
.s_axi_wuser ( 1'b0 ) ,
.s_axi_wvalid ( s_axi_wvalid ) ,
.s_axi_wready ( s_axi_wready ) ,
.s_axi_bid ( s_axi_bid ) ,
.s_axi_bresp ( s_axi_bresp ) ,
.s_axi_buser ( ) ,
.s_axi_bvalid ( s_axi_bvalid ) ,
.s_axi_bready ( s_axi_bready ) ,
.s_axi_arid ( s_axi_arid ) ,
.s_axi_araddr ( s_axi_araddr ) ,
.s_axi_arlen ( s_axi_arlen ) ,
.s_axi_arsize ( s_axi_arsize ) ,
.s_axi_arburst ( s_axi_arburst ) ,
.s_axi_arlock ( {((C_S_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}} ) ,
.s_axi_arcache ( 4'h0 ) ,
.s_axi_arprot ( s_axi_arprot ) ,
.s_axi_arqos ( 4'h0 ) ,
.s_axi_aruser ( 1'b0 ) ,
.s_axi_arvalid ( s_axi_arvalid ) ,
.s_axi_arready ( s_axi_arready ) ,
.s_axi_arregion ( 4'h0 ) ,
.s_axi_rid ( s_axi_rid ) ,
.s_axi_rdata ( s_axi_rdata ) ,
.s_axi_rresp ( s_axi_rresp ) ,
.s_axi_rlast ( s_axi_rlast ) ,
.s_axi_ruser ( ) ,
.s_axi_rvalid ( s_axi_rvalid ) ,
.s_axi_rready ( s_axi_rready ) ,
.m_axi_awid ( si_rs_awid ) ,
.m_axi_awaddr ( si_rs_awaddr ) ,
.m_axi_awlen ( si_rs_awlen[((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] ) ,
.m_axi_awsize ( si_rs_awsize ) ,
.m_axi_awburst ( si_rs_awburst ) ,
.m_axi_awlock ( ) ,
.m_axi_awcache ( ) ,
.m_axi_awprot ( si_rs_awprot ) ,
.m_axi_awqos ( ) ,
.m_axi_awuser ( ) ,
.m_axi_awvalid ( si_rs_awvalid ) ,
.m_axi_awready ( si_rs_awready ) ,
.m_axi_awregion ( ) ,
.m_axi_wid ( ) ,
.m_axi_wdata ( si_rs_wdata ) ,
.m_axi_wstrb ( si_rs_wstrb ) ,
.m_axi_wlast ( si_rs_wlast ) ,
.m_axi_wuser ( ) ,
.m_axi_wvalid ( si_rs_wvalid ) ,
.m_axi_wready ( si_rs_wready ) ,
.m_axi_bid ( si_rs_bid ) ,
.m_axi_bresp ( si_rs_bresp ) ,
.m_axi_buser ( 1'b0 ) ,
.m_axi_bvalid ( si_rs_bvalid ) ,
.m_axi_bready ( si_rs_bready ) ,
.m_axi_arid ( si_rs_arid ) ,
.m_axi_araddr ( si_rs_araddr ) ,
.m_axi_arlen ( si_rs_arlen[((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] ) ,
.m_axi_arsize ( si_rs_arsize ) ,
.m_axi_arburst ( si_rs_arburst ) ,
.m_axi_arlock ( ) ,
.m_axi_arcache ( ) ,
.m_axi_arprot ( si_rs_arprot ) ,
.m_axi_arqos ( ) ,
.m_axi_aruser ( ) ,
.m_axi_arvalid ( si_rs_arvalid ) ,
.m_axi_arready ( si_rs_arready ) ,
.m_axi_arregion ( ) ,
.m_axi_rid ( si_rs_rid ) ,
.m_axi_rdata ( si_rs_rdata ) ,
.m_axi_rresp ( si_rs_rresp ) ,
.m_axi_rlast ( si_rs_rlast ) ,
.m_axi_ruser ( 1'b0 ) ,
.m_axi_rvalid ( si_rs_rvalid ) ,
.m_axi_rready ( si_rs_rready )
);
generate
if (C_AXI_SUPPORTS_WRITE == 1) begin : WR
axi_protocol_converter_v2_1_b2s_aw_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH ),
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
aw_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_awid ( si_rs_awid ) ,
.s_awaddr ( si_rs_awaddr ) ,
.s_awlen ( (C_S_AXI_PROTOCOL == 1) ? {4'h0,si_rs_awlen[3:0]} : si_rs_awlen),
.s_awsize ( si_rs_awsize ) ,
.s_awburst ( si_rs_awburst ) ,
.s_awvalid ( si_rs_awvalid ) ,
.s_awready ( si_rs_awready ) ,
.m_awvalid ( rs_mi_awvalid ) ,
.m_awaddr ( rs_mi_awaddr ) ,
.m_awready ( rs_mi_awready ) ,
.b_push ( b_push ) ,
.b_awid ( b_awid ) ,
.b_awlen ( b_awlen ) ,
.b_full ( b_full )
);
axi_protocol_converter_v2_1_b2s_b_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH )
)
b_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_bid ( si_rs_bid ) ,
.s_bresp ( si_rs_bresp ) ,
.s_bvalid ( si_rs_bvalid ) ,
.s_bready ( si_rs_bready ) ,
.m_bready ( rs_mi_bready ) ,
.m_bvalid ( rs_mi_bvalid ) ,
.m_bresp ( rs_mi_bresp ) ,
.b_push ( b_push ) ,
.b_awid ( b_awid ) ,
.b_awlen ( b_awlen ) ,
.b_full ( b_full ) ,
.b_resp_rdy ( si_rs_awready )
);
assign rs_mi_wdata = si_rs_wdata;
assign rs_mi_wstrb = si_rs_wstrb;
assign rs_mi_wvalid = si_rs_wvalid;
assign si_rs_wready = rs_mi_wready;
end else begin : NO_WR
assign rs_mi_awaddr = {C_AXI_ADDR_WIDTH{1'b0}};
assign rs_mi_awvalid = 1'b0;
assign si_rs_awready = 1'b0;
assign rs_mi_wdata = {C_AXI_DATA_WIDTH{1'b0}};
assign rs_mi_wstrb = {C_AXI_DATA_WIDTH/8{1'b0}};
assign rs_mi_wvalid = 1'b0;
assign si_rs_wready = 1'b0;
assign rs_mi_bready = 1'b0;
assign si_rs_bvalid = 1'b0;
assign si_rs_bresp = 2'b00;
assign si_rs_bid = {C_AXI_ID_WIDTH{1'b0}};
end
endgenerate
// AR/R channel communication
wire r_push ;
wire [C_AXI_ID_WIDTH-1:0] r_arid ;
wire r_rlast ;
wire r_full ;
generate
if (C_AXI_SUPPORTS_READ == 1) begin : RD
axi_protocol_converter_v2_1_b2s_ar_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH ),
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
ar_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_arid ( si_rs_arid ) ,
.s_araddr ( si_rs_araddr ) ,
.s_arlen ( (C_S_AXI_PROTOCOL == 1) ? {4'h0,si_rs_arlen[3:0]} : si_rs_arlen),
.s_arsize ( si_rs_arsize ) ,
.s_arburst ( si_rs_arburst ) ,
.s_arvalid ( si_rs_arvalid ) ,
.s_arready ( si_rs_arready ) ,
.m_arvalid ( rs_mi_arvalid ) ,
.m_araddr ( rs_mi_araddr ) ,
.m_arready ( rs_mi_arready ) ,
.r_push ( r_push ) ,
.r_arid ( r_arid ) ,
.r_rlast ( r_rlast ) ,
.r_full ( r_full )
);
axi_protocol_converter_v2_1_b2s_r_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH ),
.C_DATA_WIDTH ( C_AXI_DATA_WIDTH )
)
r_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_rid ( si_rs_rid ) ,
.s_rdata ( si_rs_rdata ) ,
.s_rresp ( si_rs_rresp ) ,
.s_rlast ( si_rs_rlast ) ,
.s_rvalid ( si_rs_rvalid ) ,
.s_rready ( si_rs_rready ) ,
.m_rvalid ( rs_mi_rvalid ) ,
.m_rready ( rs_mi_rready ) ,
.m_rdata ( rs_mi_rdata ) ,
.m_rresp ( rs_mi_rresp ) ,
.r_push ( r_push ) ,
.r_full ( r_full ) ,
.r_arid ( r_arid ) ,
.r_rlast ( r_rlast )
);
end else begin : NO_RD
assign rs_mi_araddr = {C_AXI_ADDR_WIDTH{1'b0}};
assign rs_mi_arvalid = 1'b0;
assign si_rs_arready = 1'b0;
assign si_rs_rlast = 1'b1;
assign si_rs_rdata = {C_AXI_DATA_WIDTH{1'b0}};
assign si_rs_rvalid = 1'b0;
assign si_rs_rresp = 2'b00;
assign si_rs_rid = {C_AXI_ID_WIDTH{1'b0}};
assign rs_mi_rready = 1'b0;
end
endgenerate
axi_register_slice_v2_1_axi_register_slice #(
.C_AXI_PROTOCOL ( 2 ) ,
.C_AXI_ID_WIDTH ( 1 ) ,
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_AXI_DATA_WIDTH ( C_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_USER_SIGNALS ( 0 ) ,
.C_AXI_AWUSER_WIDTH ( 1 ) ,
.C_AXI_ARUSER_WIDTH ( 1 ) ,
.C_AXI_WUSER_WIDTH ( 1 ) ,
.C_AXI_RUSER_WIDTH ( 1 ) ,
.C_AXI_BUSER_WIDTH ( 1 ) ,
.C_REG_CONFIG_AW ( 0 ) ,
.C_REG_CONFIG_AR ( 0 ) ,
.C_REG_CONFIG_W ( 0 ) ,
.C_REG_CONFIG_R ( 0 ) ,
.C_REG_CONFIG_B ( 0 )
) MI_REG (
.aresetn ( aresetn ) ,
.aclk ( aclk ) ,
.s_axi_awid ( 1'b0 ) ,
.s_axi_awaddr ( rs_mi_awaddr ) ,
.s_axi_awlen ( 8'h00 ) ,
.s_axi_awsize ( 3'b000 ) ,
.s_axi_awburst ( 2'b01 ) ,
.s_axi_awlock ( 1'b0 ) ,
.s_axi_awcache ( 4'h0 ) ,
.s_axi_awprot ( si_rs_awprot ) ,
.s_axi_awqos ( 4'h0 ) ,
.s_axi_awuser ( 1'b0 ) ,
.s_axi_awvalid ( rs_mi_awvalid ) ,
.s_axi_awready ( rs_mi_awready ) ,
.s_axi_awregion ( 4'h0 ) ,
.s_axi_wid ( 1'b0 ) ,
.s_axi_wdata ( rs_mi_wdata ) ,
.s_axi_wstrb ( rs_mi_wstrb ) ,
.s_axi_wlast ( 1'b1 ) ,
.s_axi_wuser ( 1'b0 ) ,
.s_axi_wvalid ( rs_mi_wvalid ) ,
.s_axi_wready ( rs_mi_wready ) ,
.s_axi_bid ( ) ,
.s_axi_bresp ( rs_mi_bresp ) ,
.s_axi_buser ( ) ,
.s_axi_bvalid ( rs_mi_bvalid ) ,
.s_axi_bready ( rs_mi_bready ) ,
.s_axi_arid ( 1'b0 ) ,
.s_axi_araddr ( rs_mi_araddr ) ,
.s_axi_arlen ( 8'h00 ) ,
.s_axi_arsize ( 3'b000 ) ,
.s_axi_arburst ( 2'b01 ) ,
.s_axi_arlock ( 1'b0 ) ,
.s_axi_arcache ( 4'h0 ) ,
.s_axi_arprot ( si_rs_arprot ) ,
.s_axi_arqos ( 4'h0 ) ,
.s_axi_aruser ( 1'b0 ) ,
.s_axi_arvalid ( rs_mi_arvalid ) ,
.s_axi_arready ( rs_mi_arready ) ,
.s_axi_arregion ( 4'h0 ) ,
.s_axi_rid ( ) ,
.s_axi_rdata ( rs_mi_rdata ) ,
.s_axi_rresp ( rs_mi_rresp ) ,
.s_axi_rlast ( ) ,
.s_axi_ruser ( ) ,
.s_axi_rvalid ( rs_mi_rvalid ) ,
.s_axi_rready ( rs_mi_rready ) ,
.m_axi_awid ( ) ,
.m_axi_awaddr ( m_axi_awaddr ) ,
.m_axi_awlen ( ) ,
.m_axi_awsize ( ) ,
.m_axi_awburst ( ) ,
.m_axi_awlock ( ) ,
.m_axi_awcache ( ) ,
.m_axi_awprot ( m_axi_awprot ) ,
.m_axi_awqos ( ) ,
.m_axi_awuser ( ) ,
.m_axi_awvalid ( m_axi_awvalid ) ,
.m_axi_awready ( m_axi_awready ) ,
.m_axi_awregion ( ) ,
.m_axi_wid ( ) ,
.m_axi_wdata ( m_axi_wdata ) ,
.m_axi_wstrb ( m_axi_wstrb ) ,
.m_axi_wlast ( ) ,
.m_axi_wuser ( ) ,
.m_axi_wvalid ( m_axi_wvalid ) ,
.m_axi_wready ( m_axi_wready ) ,
.m_axi_bid ( 1'b0 ) ,
.m_axi_bresp ( m_axi_bresp ) ,
.m_axi_buser ( 1'b0 ) ,
.m_axi_bvalid ( m_axi_bvalid ) ,
.m_axi_bready ( m_axi_bready ) ,
.m_axi_arid ( ) ,
.m_axi_araddr ( m_axi_araddr ) ,
.m_axi_arlen ( ) ,
.m_axi_arsize ( ) ,
.m_axi_arburst ( ) ,
.m_axi_arlock ( ) ,
.m_axi_arcache ( ) ,
.m_axi_arprot ( m_axi_arprot ) ,
.m_axi_arqos ( ) ,
.m_axi_aruser ( ) ,
.m_axi_arvalid ( m_axi_arvalid ) ,
.m_axi_arready ( m_axi_arready ) ,
.m_axi_arregion ( ) ,
.m_axi_rid ( 1'b0 ) ,
.m_axi_rdata ( m_axi_rdata ) ,
.m_axi_rresp ( m_axi_rresp ) ,
.m_axi_rlast ( 1'b1 ) ,
.m_axi_ruser ( 1'b0 ) ,
.m_axi_rvalid ( m_axi_rvalid ) ,
.m_axi_rready ( m_axi_rready )
);
endmodule |
module axi_protocol_converter_v2_1_b2s #(
parameter C_S_AXI_PROTOCOL = 0,
// Width of all master and slave ID signals.
// Range: >= 1.
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 30,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire aclk ,
input wire aresetn ,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr ,
input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [2:0] s_axi_awsize ,
input wire [1:0] s_axi_awburst ,
input wire [2:0] s_axi_awprot ,
input wire s_axi_awvalid ,
output wire s_axi_awready ,
// Slave Interface Write Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata ,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb ,
input wire s_axi_wlast ,
input wire s_axi_wvalid ,
output wire s_axi_wready ,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid ,
output wire [1:0] s_axi_bresp ,
output wire s_axi_bvalid ,
input wire s_axi_bready ,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr ,
input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [2:0] s_axi_arsize ,
input wire [1:0] s_axi_arburst ,
input wire [2:0] s_axi_arprot ,
input wire s_axi_arvalid ,
output wire s_axi_arready ,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid ,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata ,
output wire [1:0] s_axi_rresp ,
output wire s_axi_rlast ,
output wire s_axi_rvalid ,
input wire s_axi_rready ,
// Slave Interface Write Address Ports
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr ,
output wire [2:0] m_axi_awprot ,
output wire m_axi_awvalid ,
input wire m_axi_awready ,
// Slave Interface Write Data Ports
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata ,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb ,
output wire m_axi_wvalid ,
input wire m_axi_wready ,
// Slave Interface Write Response Ports
input wire [1:0] m_axi_bresp ,
input wire m_axi_bvalid ,
output wire m_axi_bready ,
// Slave Interface Read Address Ports
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr ,
output wire [2:0] m_axi_arprot ,
output wire m_axi_arvalid ,
input wire m_axi_arready ,
// Slave Interface Read Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata ,
input wire [1:0] m_axi_rresp ,
input wire m_axi_rvalid ,
output wire m_axi_rready
);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
reg areset_d1;
always @(posedge aclk)
areset_d1 <= ~aresetn;
// AW/W/B channel internal communication
wire b_push;
wire [C_AXI_ID_WIDTH-1:0] b_awid;
wire [7:0] b_awlen;
wire b_full;
wire [C_AXI_ID_WIDTH-1:0] si_rs_awid;
wire [C_AXI_ADDR_WIDTH-1:0] si_rs_awaddr;
wire [8-1:0] si_rs_awlen;
wire [3-1:0] si_rs_awsize;
wire [2-1:0] si_rs_awburst;
wire [3-1:0] si_rs_awprot;
wire si_rs_awvalid;
wire si_rs_awready;
wire [C_AXI_DATA_WIDTH-1:0] si_rs_wdata;
wire [C_AXI_DATA_WIDTH/8-1:0] si_rs_wstrb;
wire si_rs_wlast;
wire si_rs_wvalid;
wire si_rs_wready;
wire [C_AXI_ID_WIDTH-1:0] si_rs_bid;
wire [2-1:0] si_rs_bresp;
wire si_rs_bvalid;
wire si_rs_bready;
wire [C_AXI_ID_WIDTH-1:0] si_rs_arid;
wire [C_AXI_ADDR_WIDTH-1:0] si_rs_araddr;
wire [8-1:0] si_rs_arlen;
wire [3-1:0] si_rs_arsize;
wire [2-1:0] si_rs_arburst;
wire [3-1:0] si_rs_arprot;
wire si_rs_arvalid;
wire si_rs_arready;
wire [C_AXI_ID_WIDTH-1:0] si_rs_rid;
wire [C_AXI_DATA_WIDTH-1:0] si_rs_rdata;
wire [2-1:0] si_rs_rresp;
wire si_rs_rlast;
wire si_rs_rvalid;
wire si_rs_rready;
wire [C_AXI_ADDR_WIDTH-1:0] rs_mi_awaddr;
wire rs_mi_awvalid;
wire rs_mi_awready;
wire [C_AXI_DATA_WIDTH-1:0] rs_mi_wdata;
wire [C_AXI_DATA_WIDTH/8-1:0] rs_mi_wstrb;
wire rs_mi_wvalid;
wire rs_mi_wready;
wire [2-1:0] rs_mi_bresp;
wire rs_mi_bvalid;
wire rs_mi_bready;
wire [C_AXI_ADDR_WIDTH-1:0] rs_mi_araddr;
wire rs_mi_arvalid;
wire rs_mi_arready;
wire [C_AXI_DATA_WIDTH-1:0] rs_mi_rdata;
wire [2-1:0] rs_mi_rresp;
wire rs_mi_rvalid;
wire rs_mi_rready;
axi_register_slice_v2_1_axi_register_slice #(
.C_AXI_PROTOCOL ( C_S_AXI_PROTOCOL ) ,
.C_AXI_ID_WIDTH ( C_AXI_ID_WIDTH ) ,
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_AXI_DATA_WIDTH ( C_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_USER_SIGNALS ( 0 ) ,
.C_AXI_AWUSER_WIDTH ( 1 ) ,
.C_AXI_ARUSER_WIDTH ( 1 ) ,
.C_AXI_WUSER_WIDTH ( 1 ) ,
.C_AXI_RUSER_WIDTH ( 1 ) ,
.C_AXI_BUSER_WIDTH ( 1 ) ,
.C_REG_CONFIG_AW ( 1 ) ,
.C_REG_CONFIG_AR ( 1 ) ,
.C_REG_CONFIG_W ( 0 ) ,
.C_REG_CONFIG_R ( 1 ) ,
.C_REG_CONFIG_B ( 1 )
) SI_REG (
.aresetn ( aresetn ) ,
.aclk ( aclk ) ,
.s_axi_awid ( s_axi_awid ) ,
.s_axi_awaddr ( s_axi_awaddr ) ,
.s_axi_awlen ( s_axi_awlen ) ,
.s_axi_awsize ( s_axi_awsize ) ,
.s_axi_awburst ( s_axi_awburst ) ,
.s_axi_awlock ( {((C_S_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}} ) ,
.s_axi_awcache ( 4'h0 ) ,
.s_axi_awprot ( s_axi_awprot ) ,
.s_axi_awqos ( 4'h0 ) ,
.s_axi_awuser ( 1'b0 ) ,
.s_axi_awvalid ( s_axi_awvalid ) ,
.s_axi_awready ( s_axi_awready ) ,
.s_axi_awregion ( 4'h0 ) ,
.s_axi_wid ( {C_AXI_ID_WIDTH{1'b0}} ) ,
.s_axi_wdata ( s_axi_wdata ) ,
.s_axi_wstrb ( s_axi_wstrb ) ,
.s_axi_wlast ( s_axi_wlast ) ,
.s_axi_wuser ( 1'b0 ) ,
.s_axi_wvalid ( s_axi_wvalid ) ,
.s_axi_wready ( s_axi_wready ) ,
.s_axi_bid ( s_axi_bid ) ,
.s_axi_bresp ( s_axi_bresp ) ,
.s_axi_buser ( ) ,
.s_axi_bvalid ( s_axi_bvalid ) ,
.s_axi_bready ( s_axi_bready ) ,
.s_axi_arid ( s_axi_arid ) ,
.s_axi_araddr ( s_axi_araddr ) ,
.s_axi_arlen ( s_axi_arlen ) ,
.s_axi_arsize ( s_axi_arsize ) ,
.s_axi_arburst ( s_axi_arburst ) ,
.s_axi_arlock ( {((C_S_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}} ) ,
.s_axi_arcache ( 4'h0 ) ,
.s_axi_arprot ( s_axi_arprot ) ,
.s_axi_arqos ( 4'h0 ) ,
.s_axi_aruser ( 1'b0 ) ,
.s_axi_arvalid ( s_axi_arvalid ) ,
.s_axi_arready ( s_axi_arready ) ,
.s_axi_arregion ( 4'h0 ) ,
.s_axi_rid ( s_axi_rid ) ,
.s_axi_rdata ( s_axi_rdata ) ,
.s_axi_rresp ( s_axi_rresp ) ,
.s_axi_rlast ( s_axi_rlast ) ,
.s_axi_ruser ( ) ,
.s_axi_rvalid ( s_axi_rvalid ) ,
.s_axi_rready ( s_axi_rready ) ,
.m_axi_awid ( si_rs_awid ) ,
.m_axi_awaddr ( si_rs_awaddr ) ,
.m_axi_awlen ( si_rs_awlen[((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] ) ,
.m_axi_awsize ( si_rs_awsize ) ,
.m_axi_awburst ( si_rs_awburst ) ,
.m_axi_awlock ( ) ,
.m_axi_awcache ( ) ,
.m_axi_awprot ( si_rs_awprot ) ,
.m_axi_awqos ( ) ,
.m_axi_awuser ( ) ,
.m_axi_awvalid ( si_rs_awvalid ) ,
.m_axi_awready ( si_rs_awready ) ,
.m_axi_awregion ( ) ,
.m_axi_wid ( ) ,
.m_axi_wdata ( si_rs_wdata ) ,
.m_axi_wstrb ( si_rs_wstrb ) ,
.m_axi_wlast ( si_rs_wlast ) ,
.m_axi_wuser ( ) ,
.m_axi_wvalid ( si_rs_wvalid ) ,
.m_axi_wready ( si_rs_wready ) ,
.m_axi_bid ( si_rs_bid ) ,
.m_axi_bresp ( si_rs_bresp ) ,
.m_axi_buser ( 1'b0 ) ,
.m_axi_bvalid ( si_rs_bvalid ) ,
.m_axi_bready ( si_rs_bready ) ,
.m_axi_arid ( si_rs_arid ) ,
.m_axi_araddr ( si_rs_araddr ) ,
.m_axi_arlen ( si_rs_arlen[((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] ) ,
.m_axi_arsize ( si_rs_arsize ) ,
.m_axi_arburst ( si_rs_arburst ) ,
.m_axi_arlock ( ) ,
.m_axi_arcache ( ) ,
.m_axi_arprot ( si_rs_arprot ) ,
.m_axi_arqos ( ) ,
.m_axi_aruser ( ) ,
.m_axi_arvalid ( si_rs_arvalid ) ,
.m_axi_arready ( si_rs_arready ) ,
.m_axi_arregion ( ) ,
.m_axi_rid ( si_rs_rid ) ,
.m_axi_rdata ( si_rs_rdata ) ,
.m_axi_rresp ( si_rs_rresp ) ,
.m_axi_rlast ( si_rs_rlast ) ,
.m_axi_ruser ( 1'b0 ) ,
.m_axi_rvalid ( si_rs_rvalid ) ,
.m_axi_rready ( si_rs_rready )
);
generate
if (C_AXI_SUPPORTS_WRITE == 1) begin : WR
axi_protocol_converter_v2_1_b2s_aw_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH ),
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
aw_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_awid ( si_rs_awid ) ,
.s_awaddr ( si_rs_awaddr ) ,
.s_awlen ( (C_S_AXI_PROTOCOL == 1) ? {4'h0,si_rs_awlen[3:0]} : si_rs_awlen),
.s_awsize ( si_rs_awsize ) ,
.s_awburst ( si_rs_awburst ) ,
.s_awvalid ( si_rs_awvalid ) ,
.s_awready ( si_rs_awready ) ,
.m_awvalid ( rs_mi_awvalid ) ,
.m_awaddr ( rs_mi_awaddr ) ,
.m_awready ( rs_mi_awready ) ,
.b_push ( b_push ) ,
.b_awid ( b_awid ) ,
.b_awlen ( b_awlen ) ,
.b_full ( b_full )
);
axi_protocol_converter_v2_1_b2s_b_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH )
)
b_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_bid ( si_rs_bid ) ,
.s_bresp ( si_rs_bresp ) ,
.s_bvalid ( si_rs_bvalid ) ,
.s_bready ( si_rs_bready ) ,
.m_bready ( rs_mi_bready ) ,
.m_bvalid ( rs_mi_bvalid ) ,
.m_bresp ( rs_mi_bresp ) ,
.b_push ( b_push ) ,
.b_awid ( b_awid ) ,
.b_awlen ( b_awlen ) ,
.b_full ( b_full ) ,
.b_resp_rdy ( si_rs_awready )
);
assign rs_mi_wdata = si_rs_wdata;
assign rs_mi_wstrb = si_rs_wstrb;
assign rs_mi_wvalid = si_rs_wvalid;
assign si_rs_wready = rs_mi_wready;
end else begin : NO_WR
assign rs_mi_awaddr = {C_AXI_ADDR_WIDTH{1'b0}};
assign rs_mi_awvalid = 1'b0;
assign si_rs_awready = 1'b0;
assign rs_mi_wdata = {C_AXI_DATA_WIDTH{1'b0}};
assign rs_mi_wstrb = {C_AXI_DATA_WIDTH/8{1'b0}};
assign rs_mi_wvalid = 1'b0;
assign si_rs_wready = 1'b0;
assign rs_mi_bready = 1'b0;
assign si_rs_bvalid = 1'b0;
assign si_rs_bresp = 2'b00;
assign si_rs_bid = {C_AXI_ID_WIDTH{1'b0}};
end
endgenerate
// AR/R channel communication
wire r_push ;
wire [C_AXI_ID_WIDTH-1:0] r_arid ;
wire r_rlast ;
wire r_full ;
generate
if (C_AXI_SUPPORTS_READ == 1) begin : RD
axi_protocol_converter_v2_1_b2s_ar_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH ),
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
ar_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_arid ( si_rs_arid ) ,
.s_araddr ( si_rs_araddr ) ,
.s_arlen ( (C_S_AXI_PROTOCOL == 1) ? {4'h0,si_rs_arlen[3:0]} : si_rs_arlen),
.s_arsize ( si_rs_arsize ) ,
.s_arburst ( si_rs_arburst ) ,
.s_arvalid ( si_rs_arvalid ) ,
.s_arready ( si_rs_arready ) ,
.m_arvalid ( rs_mi_arvalid ) ,
.m_araddr ( rs_mi_araddr ) ,
.m_arready ( rs_mi_arready ) ,
.r_push ( r_push ) ,
.r_arid ( r_arid ) ,
.r_rlast ( r_rlast ) ,
.r_full ( r_full )
);
axi_protocol_converter_v2_1_b2s_r_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH ),
.C_DATA_WIDTH ( C_AXI_DATA_WIDTH )
)
r_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_rid ( si_rs_rid ) ,
.s_rdata ( si_rs_rdata ) ,
.s_rresp ( si_rs_rresp ) ,
.s_rlast ( si_rs_rlast ) ,
.s_rvalid ( si_rs_rvalid ) ,
.s_rready ( si_rs_rready ) ,
.m_rvalid ( rs_mi_rvalid ) ,
.m_rready ( rs_mi_rready ) ,
.m_rdata ( rs_mi_rdata ) ,
.m_rresp ( rs_mi_rresp ) ,
.r_push ( r_push ) ,
.r_full ( r_full ) ,
.r_arid ( r_arid ) ,
.r_rlast ( r_rlast )
);
end else begin : NO_RD
assign rs_mi_araddr = {C_AXI_ADDR_WIDTH{1'b0}};
assign rs_mi_arvalid = 1'b0;
assign si_rs_arready = 1'b0;
assign si_rs_rlast = 1'b1;
assign si_rs_rdata = {C_AXI_DATA_WIDTH{1'b0}};
assign si_rs_rvalid = 1'b0;
assign si_rs_rresp = 2'b00;
assign si_rs_rid = {C_AXI_ID_WIDTH{1'b0}};
assign rs_mi_rready = 1'b0;
end
endgenerate
axi_register_slice_v2_1_axi_register_slice #(
.C_AXI_PROTOCOL ( 2 ) ,
.C_AXI_ID_WIDTH ( 1 ) ,
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_AXI_DATA_WIDTH ( C_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_USER_SIGNALS ( 0 ) ,
.C_AXI_AWUSER_WIDTH ( 1 ) ,
.C_AXI_ARUSER_WIDTH ( 1 ) ,
.C_AXI_WUSER_WIDTH ( 1 ) ,
.C_AXI_RUSER_WIDTH ( 1 ) ,
.C_AXI_BUSER_WIDTH ( 1 ) ,
.C_REG_CONFIG_AW ( 0 ) ,
.C_REG_CONFIG_AR ( 0 ) ,
.C_REG_CONFIG_W ( 0 ) ,
.C_REG_CONFIG_R ( 0 ) ,
.C_REG_CONFIG_B ( 0 )
) MI_REG (
.aresetn ( aresetn ) ,
.aclk ( aclk ) ,
.s_axi_awid ( 1'b0 ) ,
.s_axi_awaddr ( rs_mi_awaddr ) ,
.s_axi_awlen ( 8'h00 ) ,
.s_axi_awsize ( 3'b000 ) ,
.s_axi_awburst ( 2'b01 ) ,
.s_axi_awlock ( 1'b0 ) ,
.s_axi_awcache ( 4'h0 ) ,
.s_axi_awprot ( si_rs_awprot ) ,
.s_axi_awqos ( 4'h0 ) ,
.s_axi_awuser ( 1'b0 ) ,
.s_axi_awvalid ( rs_mi_awvalid ) ,
.s_axi_awready ( rs_mi_awready ) ,
.s_axi_awregion ( 4'h0 ) ,
.s_axi_wid ( 1'b0 ) ,
.s_axi_wdata ( rs_mi_wdata ) ,
.s_axi_wstrb ( rs_mi_wstrb ) ,
.s_axi_wlast ( 1'b1 ) ,
.s_axi_wuser ( 1'b0 ) ,
.s_axi_wvalid ( rs_mi_wvalid ) ,
.s_axi_wready ( rs_mi_wready ) ,
.s_axi_bid ( ) ,
.s_axi_bresp ( rs_mi_bresp ) ,
.s_axi_buser ( ) ,
.s_axi_bvalid ( rs_mi_bvalid ) ,
.s_axi_bready ( rs_mi_bready ) ,
.s_axi_arid ( 1'b0 ) ,
.s_axi_araddr ( rs_mi_araddr ) ,
.s_axi_arlen ( 8'h00 ) ,
.s_axi_arsize ( 3'b000 ) ,
.s_axi_arburst ( 2'b01 ) ,
.s_axi_arlock ( 1'b0 ) ,
.s_axi_arcache ( 4'h0 ) ,
.s_axi_arprot ( si_rs_arprot ) ,
.s_axi_arqos ( 4'h0 ) ,
.s_axi_aruser ( 1'b0 ) ,
.s_axi_arvalid ( rs_mi_arvalid ) ,
.s_axi_arready ( rs_mi_arready ) ,
.s_axi_arregion ( 4'h0 ) ,
.s_axi_rid ( ) ,
.s_axi_rdata ( rs_mi_rdata ) ,
.s_axi_rresp ( rs_mi_rresp ) ,
.s_axi_rlast ( ) ,
.s_axi_ruser ( ) ,
.s_axi_rvalid ( rs_mi_rvalid ) ,
.s_axi_rready ( rs_mi_rready ) ,
.m_axi_awid ( ) ,
.m_axi_awaddr ( m_axi_awaddr ) ,
.m_axi_awlen ( ) ,
.m_axi_awsize ( ) ,
.m_axi_awburst ( ) ,
.m_axi_awlock ( ) ,
.m_axi_awcache ( ) ,
.m_axi_awprot ( m_axi_awprot ) ,
.m_axi_awqos ( ) ,
.m_axi_awuser ( ) ,
.m_axi_awvalid ( m_axi_awvalid ) ,
.m_axi_awready ( m_axi_awready ) ,
.m_axi_awregion ( ) ,
.m_axi_wid ( ) ,
.m_axi_wdata ( m_axi_wdata ) ,
.m_axi_wstrb ( m_axi_wstrb ) ,
.m_axi_wlast ( ) ,
.m_axi_wuser ( ) ,
.m_axi_wvalid ( m_axi_wvalid ) ,
.m_axi_wready ( m_axi_wready ) ,
.m_axi_bid ( 1'b0 ) ,
.m_axi_bresp ( m_axi_bresp ) ,
.m_axi_buser ( 1'b0 ) ,
.m_axi_bvalid ( m_axi_bvalid ) ,
.m_axi_bready ( m_axi_bready ) ,
.m_axi_arid ( ) ,
.m_axi_araddr ( m_axi_araddr ) ,
.m_axi_arlen ( ) ,
.m_axi_arsize ( ) ,
.m_axi_arburst ( ) ,
.m_axi_arlock ( ) ,
.m_axi_arcache ( ) ,
.m_axi_arprot ( m_axi_arprot ) ,
.m_axi_arqos ( ) ,
.m_axi_aruser ( ) ,
.m_axi_arvalid ( m_axi_arvalid ) ,
.m_axi_arready ( m_axi_arready ) ,
.m_axi_arregion ( ) ,
.m_axi_rid ( 1'b0 ) ,
.m_axi_rdata ( m_axi_rdata ) ,
.m_axi_rresp ( m_axi_rresp ) ,
.m_axi_rlast ( 1'b1 ) ,
.m_axi_ruser ( 1'b0 ) ,
.m_axi_rvalid ( m_axi_rvalid ) ,
.m_axi_rready ( m_axi_rready )
);
endmodule |
module Add_Subt
#(parameter SWR=26) (
input wire clk,
input wire rst,
input wire load_i,//Reg load input
input wire Add_Sub_op_i,
input wire [SWR-1:0] Data_A_i,
input wire [SWR-1:0] PreData_B_i,
/////////////////////////////////////////////////////////////
output wire [SWR-1:0] Data_Result_o,
//output wire [SWR-1:0] P_o,
//output wire [SWR-1:1] Cn_o,
output wire FSM_C_o
);
wire [SWR-1:0] Data_B;
wire [SWR:0] S_to_D;
wire [SWR-1:0] P_to_D;
wire [SWR-1:1] C_to_D;
wire Co_to_D;
//wire Co_to_gate;
/*
/////////////////////////////////////////7
genvar j;
for (j=0; j<SWR; j=j+1)begin
assign Data_B[j] = PreData_B_i[j] ^ Add_Sub_op_i;
end
Full_Adder_PG #(.SWR(SWR)) AS_Module(
.clk(clk),
.rst(rst),
.Op_A_i(Data_A_i),
.Op_B_i(Data_B),
.C_i(Add_Sub_op_i), //Carry in
.S_o(S_to_D), // Solution out
.Cn_o(C_to_D),
.C_o(Co_to_gate), //Carry out
.P_o(P_o) //Propagate (for LZA)
);*/
add_sub_carry_out #(.W(SWR)) Sgf_AS (
.op_mode(Add_Sub_op_i),
.Data_A(Data_A_i),
.Data_B(PreData_B_i),
.Data_S(S_to_D)
);
assign Co_to_D = S_to_D[SWR] & ~Add_Sub_op_i;
RegisterAdd #(.W(SWR)) Add_Subt_Result(
.clk (clk),
.rst (rst),
.load (load_i),
.D (S_to_D[SWR-1:0]),
.Q (Data_Result_o)
);
/*RegisterAdd #(.W(SWR)) P_Result(
.clk (clk),
.rst (rst),
.load (load_i),
.D (P_to_D),
.Q (P_o)
);*/
/*RegisterAdd #(.W(SWR-1)) C_Result(
.clk (clk),
.rst (rst),
.load (load_i),
.D (C_to_D),
.Q (Cn_o)
);*/
RegisterAdd #(.W(1)) Add_overflow_Result(
.clk (clk),
.rst (rst),
.load (load_i),
.D (S_to_D[SWR]),
.Q (FSM_C_o)
);
endmodule |
module processing_system7_v5_5_trace_buffer #
(
parameter integer FIFO_SIZE = 128,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_DELAY_CLKS = 12
)
(
input wire TRACE_CLK,
input wire RST,
input wire TRACE_VALID_IN,
input wire [3:0] TRACE_ATID_IN,
input wire [31:0] TRACE_DATA_IN,
output wire TRACE_VALID_OUT,
output wire [3:0] TRACE_ATID_OUT,
output wire [31:0] TRACE_DATA_OUT
);
//------------------------------------------------------------
// Architecture section
//------------------------------------------------------------
// function called clogb2 that returns an integer which has the
// value of the ceiling of the log base 2.
function integer clogb2 (input integer bit_depth);
integer i;
integer temp_log;
begin
temp_log = 0;
for(i=bit_depth; i > 0; i = i>>1)
clogb2 = temp_log;
temp_log=temp_log+1;
end
endfunction
localparam DEPTH = clogb2(FIFO_SIZE-1);
wire [31:0] reset_zeros;
reg [31:0] trace_pedge; // write enable for FIFO
reg [31:0] ti;
reg [31:0] tom;
reg [3:0] atid;
reg [31:0] trace_fifo [FIFO_SIZE-1:0];//Memory
reg [4:0] dly_ctr;
reg [DEPTH-1:0] fifo_wp;
reg [DEPTH-1:0] fifo_rp;
reg fifo_re;
wire fifo_empty;
wire fifo_full;
reg fifo_full_reg;
assign reset_zeros = 32'h0;
// Pipeline Stage for Traceport ATID ports
always @(posedge TRACE_CLK) begin
// process pedge_ti
// rising clock edge
if((RST == 1'b1)) begin
atid <= reset_zeros;
end
else begin
atid <= TRACE_ATID_IN;
end
end
assign TRACE_ATID_OUT = atid;
/////////////////////////////////////////////
// Generate FIFO data based on TRACE_VALID_IN
/////////////////////////////////////////////
generate
if (USE_TRACE_DATA_EDGE_DETECTOR == 0) begin : gen_no_data_edge_detector
/////////////////////////////////////////////
// memory update process
// Update memory when positive edge detected and FIFO not full
always @(posedge TRACE_CLK) begin
if (TRACE_VALID_IN == 1'b1 && fifo_full_reg != 1'b1) begin
trace_fifo[fifo_wp] <= TRACE_DATA_IN;
end
end
// fifo write pointer
always @(posedge TRACE_CLK) begin
// process
if(RST == 1'b1) begin
fifo_wp <= {DEPTH{1'b0}};
end
else if(TRACE_VALID_IN ) begin
if(fifo_wp == (FIFO_SIZE - 1)) begin
if (fifo_empty) begin
fifo_wp <= {DEPTH{1'b0}};
end
end
else begin
fifo_wp <= fifo_wp + 1;
end
end
end
/////////////////////////////////////////////
// Generate FIFO data based on data edge
/////////////////////////////////////////////
end else begin : gen_data_edge_detector
/////////////////////////////////////////////
// purpose: check for pos edge on any trace input
always @(posedge TRACE_CLK) begin
// process pedge_ti
// rising clock edge
if((RST == 1'b1)) begin
ti <= reset_zeros;
trace_pedge <= reset_zeros;
end
else begin
ti <= TRACE_DATA_IN;
trace_pedge <= (~ti & TRACE_DATA_IN);
//trace_pedge <= ((~ti ^ TRACE_DATA_IN)) & ~ti;
// posedge only
end
end
// memory update process
// Update memory when positive edge detected and FIFO not full
always @(posedge TRACE_CLK) begin
if(|(trace_pedge) == 1'b1 && fifo_full_reg != 1'b1) begin
trace_fifo[fifo_wp] <= trace_pedge;
end
end
// fifo write pointer
always @(posedge TRACE_CLK) begin
// process
if(RST == 1'b1) begin
fifo_wp <= {DEPTH{1'b0}};
end
else if(|(trace_pedge) == 1'b1) begin
if(fifo_wp == (FIFO_SIZE - 1)) begin
if (fifo_empty) begin
fifo_wp <= {DEPTH{1'b0}};
end
end
else begin
fifo_wp <= fifo_wp + 1;
end
end
end
end
endgenerate
always @(posedge TRACE_CLK) begin
tom <= trace_fifo[fifo_rp] ;
end
// // fifo write pointer
// always @(posedge TRACE_CLK) begin
// // process
// if(RST == 1'b1) begin
// fifo_wp <= {DEPTH{1'b0}};
// end
// else if(|(trace_pedge) == 1'b1) begin
// if(fifo_wp == (FIFO_SIZE - 1)) begin
// fifo_wp <= {DEPTH{1'b0}};
// end
// else begin
// fifo_wp <= fifo_wp + 1;
// end
// end
// end
// fifo read pointer update
always @(posedge TRACE_CLK) begin
if(RST == 1'b1) begin
fifo_rp <= {DEPTH{1'b0}};
fifo_re <= 1'b0;
end
else if(fifo_empty != 1'b1 && dly_ctr == 5'b00000 && fifo_re == 1'b0) begin
fifo_re <= 1'b1;
if(fifo_rp == (FIFO_SIZE - 1)) begin
fifo_rp <= {DEPTH{1'b0}};
end
else begin
fifo_rp <= fifo_rp + 1;
end
end
else begin
fifo_re <= 1'b0;
end
end
// delay counter update
always @(posedge TRACE_CLK) begin
if(RST == 1'b1) begin
dly_ctr <= 5'h0;
end
else if (fifo_re == 1'b1) begin
dly_ctr <= C_DELAY_CLKS-1;
end
else if(dly_ctr != 5'h0) begin
dly_ctr <= dly_ctr - 1;
end
end
// fifo empty update
assign fifo_empty = (fifo_wp == fifo_rp) ? 1'b1 : 1'b0;
// fifo full update
assign fifo_full = (fifo_wp == FIFO_SIZE-1)? 1'b1 : 1'b0;
always @(posedge TRACE_CLK) begin
if(RST == 1'b1) begin
fifo_full_reg <= 1'b0;
end
else if (fifo_empty) begin
fifo_full_reg <= 1'b0;
end else begin
fifo_full_reg <= fifo_full;
end
end
// always @(posedge TRACE_CLK) begin
// if(RST == 1'b1) begin
// fifo_full_reg <= 1'b0;
// end
// else if ((fifo_wp == FIFO_SIZE-1) && (|(trace_pedge) == 1'b1)) begin
// fifo_full_reg <= 1'b1;
// end
// else begin
// fifo_full_reg <= 1'b0;
// end
// end
//
assign TRACE_DATA_OUT = tom;
assign TRACE_VALID_OUT = fifo_re;
endmodule |
module processing_system7_v5_5_trace_buffer #
(
parameter integer FIFO_SIZE = 128,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_DELAY_CLKS = 12
)
(
input wire TRACE_CLK,
input wire RST,
input wire TRACE_VALID_IN,
input wire [3:0] TRACE_ATID_IN,
input wire [31:0] TRACE_DATA_IN,
output wire TRACE_VALID_OUT,
output wire [3:0] TRACE_ATID_OUT,
output wire [31:0] TRACE_DATA_OUT
);
//------------------------------------------------------------
// Architecture section
//------------------------------------------------------------
// function called clogb2 that returns an integer which has the
// value of the ceiling of the log base 2.
function integer clogb2 (input integer bit_depth);
integer i;
integer temp_log;
begin
temp_log = 0;
for(i=bit_depth; i > 0; i = i>>1)
clogb2 = temp_log;
temp_log=temp_log+1;
end
endfunction
localparam DEPTH = clogb2(FIFO_SIZE-1);
wire [31:0] reset_zeros;
reg [31:0] trace_pedge; // write enable for FIFO
reg [31:0] ti;
reg [31:0] tom;
reg [3:0] atid;
reg [31:0] trace_fifo [FIFO_SIZE-1:0];//Memory
reg [4:0] dly_ctr;
reg [DEPTH-1:0] fifo_wp;
reg [DEPTH-1:0] fifo_rp;
reg fifo_re;
wire fifo_empty;
wire fifo_full;
reg fifo_full_reg;
assign reset_zeros = 32'h0;
// Pipeline Stage for Traceport ATID ports
always @(posedge TRACE_CLK) begin
// process pedge_ti
// rising clock edge
if((RST == 1'b1)) begin
atid <= reset_zeros;
end
else begin
atid <= TRACE_ATID_IN;
end
end
assign TRACE_ATID_OUT = atid;
/////////////////////////////////////////////
// Generate FIFO data based on TRACE_VALID_IN
/////////////////////////////////////////////
generate
if (USE_TRACE_DATA_EDGE_DETECTOR == 0) begin : gen_no_data_edge_detector
/////////////////////////////////////////////
// memory update process
// Update memory when positive edge detected and FIFO not full
always @(posedge TRACE_CLK) begin
if (TRACE_VALID_IN == 1'b1 && fifo_full_reg != 1'b1) begin
trace_fifo[fifo_wp] <= TRACE_DATA_IN;
end
end
// fifo write pointer
always @(posedge TRACE_CLK) begin
// process
if(RST == 1'b1) begin
fifo_wp <= {DEPTH{1'b0}};
end
else if(TRACE_VALID_IN ) begin
if(fifo_wp == (FIFO_SIZE - 1)) begin
if (fifo_empty) begin
fifo_wp <= {DEPTH{1'b0}};
end
end
else begin
fifo_wp <= fifo_wp + 1;
end
end
end
/////////////////////////////////////////////
// Generate FIFO data based on data edge
/////////////////////////////////////////////
end else begin : gen_data_edge_detector
/////////////////////////////////////////////
// purpose: check for pos edge on any trace input
always @(posedge TRACE_CLK) begin
// process pedge_ti
// rising clock edge
if((RST == 1'b1)) begin
ti <= reset_zeros;
trace_pedge <= reset_zeros;
end
else begin
ti <= TRACE_DATA_IN;
trace_pedge <= (~ti & TRACE_DATA_IN);
//trace_pedge <= ((~ti ^ TRACE_DATA_IN)) & ~ti;
// posedge only
end
end
// memory update process
// Update memory when positive edge detected and FIFO not full
always @(posedge TRACE_CLK) begin
if(|(trace_pedge) == 1'b1 && fifo_full_reg != 1'b1) begin
trace_fifo[fifo_wp] <= trace_pedge;
end
end
// fifo write pointer
always @(posedge TRACE_CLK) begin
// process
if(RST == 1'b1) begin
fifo_wp <= {DEPTH{1'b0}};
end
else if(|(trace_pedge) == 1'b1) begin
if(fifo_wp == (FIFO_SIZE - 1)) begin
if (fifo_empty) begin
fifo_wp <= {DEPTH{1'b0}};
end
end
else begin
fifo_wp <= fifo_wp + 1;
end
end
end
end
endgenerate
always @(posedge TRACE_CLK) begin
tom <= trace_fifo[fifo_rp] ;
end
// // fifo write pointer
// always @(posedge TRACE_CLK) begin
// // process
// if(RST == 1'b1) begin
// fifo_wp <= {DEPTH{1'b0}};
// end
// else if(|(trace_pedge) == 1'b1) begin
// if(fifo_wp == (FIFO_SIZE - 1)) begin
// fifo_wp <= {DEPTH{1'b0}};
// end
// else begin
// fifo_wp <= fifo_wp + 1;
// end
// end
// end
// fifo read pointer update
always @(posedge TRACE_CLK) begin
if(RST == 1'b1) begin
fifo_rp <= {DEPTH{1'b0}};
fifo_re <= 1'b0;
end
else if(fifo_empty != 1'b1 && dly_ctr == 5'b00000 && fifo_re == 1'b0) begin
fifo_re <= 1'b1;
if(fifo_rp == (FIFO_SIZE - 1)) begin
fifo_rp <= {DEPTH{1'b0}};
end
else begin
fifo_rp <= fifo_rp + 1;
end
end
else begin
fifo_re <= 1'b0;
end
end
// delay counter update
always @(posedge TRACE_CLK) begin
if(RST == 1'b1) begin
dly_ctr <= 5'h0;
end
else if (fifo_re == 1'b1) begin
dly_ctr <= C_DELAY_CLKS-1;
end
else if(dly_ctr != 5'h0) begin
dly_ctr <= dly_ctr - 1;
end
end
// fifo empty update
assign fifo_empty = (fifo_wp == fifo_rp) ? 1'b1 : 1'b0;
// fifo full update
assign fifo_full = (fifo_wp == FIFO_SIZE-1)? 1'b1 : 1'b0;
always @(posedge TRACE_CLK) begin
if(RST == 1'b1) begin
fifo_full_reg <= 1'b0;
end
else if (fifo_empty) begin
fifo_full_reg <= 1'b0;
end else begin
fifo_full_reg <= fifo_full;
end
end
// always @(posedge TRACE_CLK) begin
// if(RST == 1'b1) begin
// fifo_full_reg <= 1'b0;
// end
// else if ((fifo_wp == FIFO_SIZE-1) && (|(trace_pedge) == 1'b1)) begin
// fifo_full_reg <= 1'b1;
// end
// else begin
// fifo_full_reg <= 1'b0;
// end
// end
//
assign TRACE_DATA_OUT = tom;
assign TRACE_VALID_OUT = fifo_re;
endmodule |
module processing_system7_v5_5_trace_buffer #
(
parameter integer FIFO_SIZE = 128,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_DELAY_CLKS = 12
)
(
input wire TRACE_CLK,
input wire RST,
input wire TRACE_VALID_IN,
input wire [3:0] TRACE_ATID_IN,
input wire [31:0] TRACE_DATA_IN,
output wire TRACE_VALID_OUT,
output wire [3:0] TRACE_ATID_OUT,
output wire [31:0] TRACE_DATA_OUT
);
//------------------------------------------------------------
// Architecture section
//------------------------------------------------------------
// function called clogb2 that returns an integer which has the
// value of the ceiling of the log base 2.
function integer clogb2 (input integer bit_depth);
integer i;
integer temp_log;
begin
temp_log = 0;
for(i=bit_depth; i > 0; i = i>>1)
clogb2 = temp_log;
temp_log=temp_log+1;
end
endfunction
localparam DEPTH = clogb2(FIFO_SIZE-1);
wire [31:0] reset_zeros;
reg [31:0] trace_pedge; // write enable for FIFO
reg [31:0] ti;
reg [31:0] tom;
reg [3:0] atid;
reg [31:0] trace_fifo [FIFO_SIZE-1:0];//Memory
reg [4:0] dly_ctr;
reg [DEPTH-1:0] fifo_wp;
reg [DEPTH-1:0] fifo_rp;
reg fifo_re;
wire fifo_empty;
wire fifo_full;
reg fifo_full_reg;
assign reset_zeros = 32'h0;
// Pipeline Stage for Traceport ATID ports
always @(posedge TRACE_CLK) begin
// process pedge_ti
// rising clock edge
if((RST == 1'b1)) begin
atid <= reset_zeros;
end
else begin
atid <= TRACE_ATID_IN;
end
end
assign TRACE_ATID_OUT = atid;
/////////////////////////////////////////////
// Generate FIFO data based on TRACE_VALID_IN
/////////////////////////////////////////////
generate
if (USE_TRACE_DATA_EDGE_DETECTOR == 0) begin : gen_no_data_edge_detector
/////////////////////////////////////////////
// memory update process
// Update memory when positive edge detected and FIFO not full
always @(posedge TRACE_CLK) begin
if (TRACE_VALID_IN == 1'b1 && fifo_full_reg != 1'b1) begin
trace_fifo[fifo_wp] <= TRACE_DATA_IN;
end
end
// fifo write pointer
always @(posedge TRACE_CLK) begin
// process
if(RST == 1'b1) begin
fifo_wp <= {DEPTH{1'b0}};
end
else if(TRACE_VALID_IN ) begin
if(fifo_wp == (FIFO_SIZE - 1)) begin
if (fifo_empty) begin
fifo_wp <= {DEPTH{1'b0}};
end
end
else begin
fifo_wp <= fifo_wp + 1;
end
end
end
/////////////////////////////////////////////
// Generate FIFO data based on data edge
/////////////////////////////////////////////
end else begin : gen_data_edge_detector
/////////////////////////////////////////////
// purpose: check for pos edge on any trace input
always @(posedge TRACE_CLK) begin
// process pedge_ti
// rising clock edge
if((RST == 1'b1)) begin
ti <= reset_zeros;
trace_pedge <= reset_zeros;
end
else begin
ti <= TRACE_DATA_IN;
trace_pedge <= (~ti & TRACE_DATA_IN);
//trace_pedge <= ((~ti ^ TRACE_DATA_IN)) & ~ti;
// posedge only
end
end
// memory update process
// Update memory when positive edge detected and FIFO not full
always @(posedge TRACE_CLK) begin
if(|(trace_pedge) == 1'b1 && fifo_full_reg != 1'b1) begin
trace_fifo[fifo_wp] <= trace_pedge;
end
end
// fifo write pointer
always @(posedge TRACE_CLK) begin
// process
if(RST == 1'b1) begin
fifo_wp <= {DEPTH{1'b0}};
end
else if(|(trace_pedge) == 1'b1) begin
if(fifo_wp == (FIFO_SIZE - 1)) begin
if (fifo_empty) begin
fifo_wp <= {DEPTH{1'b0}};
end
end
else begin
fifo_wp <= fifo_wp + 1;
end
end
end
end
endgenerate
always @(posedge TRACE_CLK) begin
tom <= trace_fifo[fifo_rp] ;
end
// // fifo write pointer
// always @(posedge TRACE_CLK) begin
// // process
// if(RST == 1'b1) begin
// fifo_wp <= {DEPTH{1'b0}};
// end
// else if(|(trace_pedge) == 1'b1) begin
// if(fifo_wp == (FIFO_SIZE - 1)) begin
// fifo_wp <= {DEPTH{1'b0}};
// end
// else begin
// fifo_wp <= fifo_wp + 1;
// end
// end
// end
// fifo read pointer update
always @(posedge TRACE_CLK) begin
if(RST == 1'b1) begin
fifo_rp <= {DEPTH{1'b0}};
fifo_re <= 1'b0;
end
else if(fifo_empty != 1'b1 && dly_ctr == 5'b00000 && fifo_re == 1'b0) begin
fifo_re <= 1'b1;
if(fifo_rp == (FIFO_SIZE - 1)) begin
fifo_rp <= {DEPTH{1'b0}};
end
else begin
fifo_rp <= fifo_rp + 1;
end
end
else begin
fifo_re <= 1'b0;
end
end
// delay counter update
always @(posedge TRACE_CLK) begin
if(RST == 1'b1) begin
dly_ctr <= 5'h0;
end
else if (fifo_re == 1'b1) begin
dly_ctr <= C_DELAY_CLKS-1;
end
else if(dly_ctr != 5'h0) begin
dly_ctr <= dly_ctr - 1;
end
end
// fifo empty update
assign fifo_empty = (fifo_wp == fifo_rp) ? 1'b1 : 1'b0;
// fifo full update
assign fifo_full = (fifo_wp == FIFO_SIZE-1)? 1'b1 : 1'b0;
always @(posedge TRACE_CLK) begin
if(RST == 1'b1) begin
fifo_full_reg <= 1'b0;
end
else if (fifo_empty) begin
fifo_full_reg <= 1'b0;
end else begin
fifo_full_reg <= fifo_full;
end
end
// always @(posedge TRACE_CLK) begin
// if(RST == 1'b1) begin
// fifo_full_reg <= 1'b0;
// end
// else if ((fifo_wp == FIFO_SIZE-1) && (|(trace_pedge) == 1'b1)) begin
// fifo_full_reg <= 1'b1;
// end
// else begin
// fifo_full_reg <= 1'b0;
// end
// end
//
assign TRACE_DATA_OUT = tom;
assign TRACE_VALID_OUT = fifo_re;
endmodule |
module processing_system7_v5_5_trace_buffer #
(
parameter integer FIFO_SIZE = 128,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_DELAY_CLKS = 12
)
(
input wire TRACE_CLK,
input wire RST,
input wire TRACE_VALID_IN,
input wire [3:0] TRACE_ATID_IN,
input wire [31:0] TRACE_DATA_IN,
output wire TRACE_VALID_OUT,
output wire [3:0] TRACE_ATID_OUT,
output wire [31:0] TRACE_DATA_OUT
);
//------------------------------------------------------------
// Architecture section
//------------------------------------------------------------
// function called clogb2 that returns an integer which has the
// value of the ceiling of the log base 2.
function integer clogb2 (input integer bit_depth);
integer i;
integer temp_log;
begin
temp_log = 0;
for(i=bit_depth; i > 0; i = i>>1)
clogb2 = temp_log;
temp_log=temp_log+1;
end
endfunction
localparam DEPTH = clogb2(FIFO_SIZE-1);
wire [31:0] reset_zeros;
reg [31:0] trace_pedge; // write enable for FIFO
reg [31:0] ti;
reg [31:0] tom;
reg [3:0] atid;
reg [31:0] trace_fifo [FIFO_SIZE-1:0];//Memory
reg [4:0] dly_ctr;
reg [DEPTH-1:0] fifo_wp;
reg [DEPTH-1:0] fifo_rp;
reg fifo_re;
wire fifo_empty;
wire fifo_full;
reg fifo_full_reg;
assign reset_zeros = 32'h0;
// Pipeline Stage for Traceport ATID ports
always @(posedge TRACE_CLK) begin
// process pedge_ti
// rising clock edge
if((RST == 1'b1)) begin
atid <= reset_zeros;
end
else begin
atid <= TRACE_ATID_IN;
end
end
assign TRACE_ATID_OUT = atid;
/////////////////////////////////////////////
// Generate FIFO data based on TRACE_VALID_IN
/////////////////////////////////////////////
generate
if (USE_TRACE_DATA_EDGE_DETECTOR == 0) begin : gen_no_data_edge_detector
/////////////////////////////////////////////
// memory update process
// Update memory when positive edge detected and FIFO not full
always @(posedge TRACE_CLK) begin
if (TRACE_VALID_IN == 1'b1 && fifo_full_reg != 1'b1) begin
trace_fifo[fifo_wp] <= TRACE_DATA_IN;
end
end
// fifo write pointer
always @(posedge TRACE_CLK) begin
// process
if(RST == 1'b1) begin
fifo_wp <= {DEPTH{1'b0}};
end
else if(TRACE_VALID_IN ) begin
if(fifo_wp == (FIFO_SIZE - 1)) begin
if (fifo_empty) begin
fifo_wp <= {DEPTH{1'b0}};
end
end
else begin
fifo_wp <= fifo_wp + 1;
end
end
end
/////////////////////////////////////////////
// Generate FIFO data based on data edge
/////////////////////////////////////////////
end else begin : gen_data_edge_detector
/////////////////////////////////////////////
// purpose: check for pos edge on any trace input
always @(posedge TRACE_CLK) begin
// process pedge_ti
// rising clock edge
if((RST == 1'b1)) begin
ti <= reset_zeros;
trace_pedge <= reset_zeros;
end
else begin
ti <= TRACE_DATA_IN;
trace_pedge <= (~ti & TRACE_DATA_IN);
//trace_pedge <= ((~ti ^ TRACE_DATA_IN)) & ~ti;
// posedge only
end
end
// memory update process
// Update memory when positive edge detected and FIFO not full
always @(posedge TRACE_CLK) begin
if(|(trace_pedge) == 1'b1 && fifo_full_reg != 1'b1) begin
trace_fifo[fifo_wp] <= trace_pedge;
end
end
// fifo write pointer
always @(posedge TRACE_CLK) begin
// process
if(RST == 1'b1) begin
fifo_wp <= {DEPTH{1'b0}};
end
else if(|(trace_pedge) == 1'b1) begin
if(fifo_wp == (FIFO_SIZE - 1)) begin
if (fifo_empty) begin
fifo_wp <= {DEPTH{1'b0}};
end
end
else begin
fifo_wp <= fifo_wp + 1;
end
end
end
end
endgenerate
always @(posedge TRACE_CLK) begin
tom <= trace_fifo[fifo_rp] ;
end
// // fifo write pointer
// always @(posedge TRACE_CLK) begin
// // process
// if(RST == 1'b1) begin
// fifo_wp <= {DEPTH{1'b0}};
// end
// else if(|(trace_pedge) == 1'b1) begin
// if(fifo_wp == (FIFO_SIZE - 1)) begin
// fifo_wp <= {DEPTH{1'b0}};
// end
// else begin
// fifo_wp <= fifo_wp + 1;
// end
// end
// end
// fifo read pointer update
always @(posedge TRACE_CLK) begin
if(RST == 1'b1) begin
fifo_rp <= {DEPTH{1'b0}};
fifo_re <= 1'b0;
end
else if(fifo_empty != 1'b1 && dly_ctr == 5'b00000 && fifo_re == 1'b0) begin
fifo_re <= 1'b1;
if(fifo_rp == (FIFO_SIZE - 1)) begin
fifo_rp <= {DEPTH{1'b0}};
end
else begin
fifo_rp <= fifo_rp + 1;
end
end
else begin
fifo_re <= 1'b0;
end
end
// delay counter update
always @(posedge TRACE_CLK) begin
if(RST == 1'b1) begin
dly_ctr <= 5'h0;
end
else if (fifo_re == 1'b1) begin
dly_ctr <= C_DELAY_CLKS-1;
end
else if(dly_ctr != 5'h0) begin
dly_ctr <= dly_ctr - 1;
end
end
// fifo empty update
assign fifo_empty = (fifo_wp == fifo_rp) ? 1'b1 : 1'b0;
// fifo full update
assign fifo_full = (fifo_wp == FIFO_SIZE-1)? 1'b1 : 1'b0;
always @(posedge TRACE_CLK) begin
if(RST == 1'b1) begin
fifo_full_reg <= 1'b0;
end
else if (fifo_empty) begin
fifo_full_reg <= 1'b0;
end else begin
fifo_full_reg <= fifo_full;
end
end
// always @(posedge TRACE_CLK) begin
// if(RST == 1'b1) begin
// fifo_full_reg <= 1'b0;
// end
// else if ((fifo_wp == FIFO_SIZE-1) && (|(trace_pedge) == 1'b1)) begin
// fifo_full_reg <= 1'b1;
// end
// else begin
// fifo_full_reg <= 1'b0;
// end
// end
//
assign TRACE_DATA_OUT = tom;
assign TRACE_VALID_OUT = fifo_re;
endmodule |
module processing_system7_v5_5_trace_buffer #
(
parameter integer FIFO_SIZE = 128,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_DELAY_CLKS = 12
)
(
input wire TRACE_CLK,
input wire RST,
input wire TRACE_VALID_IN,
input wire [3:0] TRACE_ATID_IN,
input wire [31:0] TRACE_DATA_IN,
output wire TRACE_VALID_OUT,
output wire [3:0] TRACE_ATID_OUT,
output wire [31:0] TRACE_DATA_OUT
);
//------------------------------------------------------------
// Architecture section
//------------------------------------------------------------
// function called clogb2 that returns an integer which has the
// value of the ceiling of the log base 2.
function integer clogb2 (input integer bit_depth);
integer i;
integer temp_log;
begin
temp_log = 0;
for(i=bit_depth; i > 0; i = i>>1)
clogb2 = temp_log;
temp_log=temp_log+1;
end
endfunction
localparam DEPTH = clogb2(FIFO_SIZE-1);
wire [31:0] reset_zeros;
reg [31:0] trace_pedge; // write enable for FIFO
reg [31:0] ti;
reg [31:0] tom;
reg [3:0] atid;
reg [31:0] trace_fifo [FIFO_SIZE-1:0];//Memory
reg [4:0] dly_ctr;
reg [DEPTH-1:0] fifo_wp;
reg [DEPTH-1:0] fifo_rp;
reg fifo_re;
wire fifo_empty;
wire fifo_full;
reg fifo_full_reg;
assign reset_zeros = 32'h0;
// Pipeline Stage for Traceport ATID ports
always @(posedge TRACE_CLK) begin
// process pedge_ti
// rising clock edge
if((RST == 1'b1)) begin
atid <= reset_zeros;
end
else begin
atid <= TRACE_ATID_IN;
end
end
assign TRACE_ATID_OUT = atid;
/////////////////////////////////////////////
// Generate FIFO data based on TRACE_VALID_IN
/////////////////////////////////////////////
generate
if (USE_TRACE_DATA_EDGE_DETECTOR == 0) begin : gen_no_data_edge_detector
/////////////////////////////////////////////
// memory update process
// Update memory when positive edge detected and FIFO not full
always @(posedge TRACE_CLK) begin
if (TRACE_VALID_IN == 1'b1 && fifo_full_reg != 1'b1) begin
trace_fifo[fifo_wp] <= TRACE_DATA_IN;
end
end
// fifo write pointer
always @(posedge TRACE_CLK) begin
// process
if(RST == 1'b1) begin
fifo_wp <= {DEPTH{1'b0}};
end
else if(TRACE_VALID_IN ) begin
if(fifo_wp == (FIFO_SIZE - 1)) begin
if (fifo_empty) begin
fifo_wp <= {DEPTH{1'b0}};
end
end
else begin
fifo_wp <= fifo_wp + 1;
end
end
end
/////////////////////////////////////////////
// Generate FIFO data based on data edge
/////////////////////////////////////////////
end else begin : gen_data_edge_detector
/////////////////////////////////////////////
// purpose: check for pos edge on any trace input
always @(posedge TRACE_CLK) begin
// process pedge_ti
// rising clock edge
if((RST == 1'b1)) begin
ti <= reset_zeros;
trace_pedge <= reset_zeros;
end
else begin
ti <= TRACE_DATA_IN;
trace_pedge <= (~ti & TRACE_DATA_IN);
//trace_pedge <= ((~ti ^ TRACE_DATA_IN)) & ~ti;
// posedge only
end
end
// memory update process
// Update memory when positive edge detected and FIFO not full
always @(posedge TRACE_CLK) begin
if(|(trace_pedge) == 1'b1 && fifo_full_reg != 1'b1) begin
trace_fifo[fifo_wp] <= trace_pedge;
end
end
// fifo write pointer
always @(posedge TRACE_CLK) begin
// process
if(RST == 1'b1) begin
fifo_wp <= {DEPTH{1'b0}};
end
else if(|(trace_pedge) == 1'b1) begin
if(fifo_wp == (FIFO_SIZE - 1)) begin
if (fifo_empty) begin
fifo_wp <= {DEPTH{1'b0}};
end
end
else begin
fifo_wp <= fifo_wp + 1;
end
end
end
end
endgenerate
always @(posedge TRACE_CLK) begin
tom <= trace_fifo[fifo_rp] ;
end
// // fifo write pointer
// always @(posedge TRACE_CLK) begin
// // process
// if(RST == 1'b1) begin
// fifo_wp <= {DEPTH{1'b0}};
// end
// else if(|(trace_pedge) == 1'b1) begin
// if(fifo_wp == (FIFO_SIZE - 1)) begin
// fifo_wp <= {DEPTH{1'b0}};
// end
// else begin
// fifo_wp <= fifo_wp + 1;
// end
// end
// end
// fifo read pointer update
always @(posedge TRACE_CLK) begin
if(RST == 1'b1) begin
fifo_rp <= {DEPTH{1'b0}};
fifo_re <= 1'b0;
end
else if(fifo_empty != 1'b1 && dly_ctr == 5'b00000 && fifo_re == 1'b0) begin
fifo_re <= 1'b1;
if(fifo_rp == (FIFO_SIZE - 1)) begin
fifo_rp <= {DEPTH{1'b0}};
end
else begin
fifo_rp <= fifo_rp + 1;
end
end
else begin
fifo_re <= 1'b0;
end
end
// delay counter update
always @(posedge TRACE_CLK) begin
if(RST == 1'b1) begin
dly_ctr <= 5'h0;
end
else if (fifo_re == 1'b1) begin
dly_ctr <= C_DELAY_CLKS-1;
end
else if(dly_ctr != 5'h0) begin
dly_ctr <= dly_ctr - 1;
end
end
// fifo empty update
assign fifo_empty = (fifo_wp == fifo_rp) ? 1'b1 : 1'b0;
// fifo full update
assign fifo_full = (fifo_wp == FIFO_SIZE-1)? 1'b1 : 1'b0;
always @(posedge TRACE_CLK) begin
if(RST == 1'b1) begin
fifo_full_reg <= 1'b0;
end
else if (fifo_empty) begin
fifo_full_reg <= 1'b0;
end else begin
fifo_full_reg <= fifo_full;
end
end
// always @(posedge TRACE_CLK) begin
// if(RST == 1'b1) begin
// fifo_full_reg <= 1'b0;
// end
// else if ((fifo_wp == FIFO_SIZE-1) && (|(trace_pedge) == 1'b1)) begin
// fifo_full_reg <= 1'b1;
// end
// else begin
// fifo_full_reg <= 1'b0;
// end
// end
//
assign TRACE_DATA_OUT = tom;
assign TRACE_VALID_OUT = fifo_re;
endmodule |
module.
// 1 => FWD_REV = Both FWD and REV (fully-registered)
// 2 => FWD = The master VALID and payload signals are registrated.
// 3 => REV = The slave ready signal is registrated
// 4 => RESERVED (all outputs driven to 0).
// 5 => RESERVED (all outputs driven to 0).
// 6 => INPUTS = Slave and Master side inputs are registrated.
// 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
(* use_clock_enable = "yes" *)
generate
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 0
// Bypass mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000) begin
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 1 (or 8)
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin
reg [C_DATA_WIDTH-1:0] m_payload_i;
reg [C_DATA_WIDTH-1:0] skid_buffer;
reg s_ready_i;
reg m_valid_i;
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign M_PAYLOAD_DATA = m_payload_i;
reg [1:0] aresetn_d = 2'b00; // Reset delay shifter
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
always @(posedge ACLK) begin
if (~aresetn_d[0]) begin
s_ready_i <= 1'b0;
end else begin
s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);
end
if (~aresetn_d[1]) begin
m_valid_i <= 1'b0;
end else begin
m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);
end
if (M_READY | ~m_valid_i) begin
m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;
end
if (s_ready_i) begin
skid_buffer <= S_PAYLOAD_DATA;
end
end
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 2
// Only FWD mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000002)
begin
reg [C_DATA_WIDTH-1:0] storage_data;
wire s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg aresetn_d = 1'b0; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 1'b0;
end else begin
aresetn_d <= ~ARESET;
end
end
// Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK)
begin
if (S_VALID & s_ready_i)
storage_data <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data;
// M_Valid set to high when we have a completed transfer on slave side
// Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK)
begin
if (~aresetn_d)
m_valid_i <= 1'b0;
else
if (S_VALID) // Always set m_valid_i when slave side is valid
m_valid_i <= 1'b1;
else
if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready
m_valid_i <= 1'b0;
end // always @ (posedge ACLK)
// Slave Ready is either when Master side drives M_Ready or we have space in our storage data
assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;
end // if (C_REG_CONFIG == 2)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 3
// Only REV mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000003)
begin
reg [C_DATA_WIDTH-1:0] storage_data;
reg s_ready_i; //local signal of output
reg has_valid_storage_i;
reg has_valid_storage;
reg [1:0] aresetn_d = 2'b00; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
// Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK)
begin
if (S_VALID & s_ready_i)
storage_data <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;
// Need to determine when we need to save a payload
// Need a combinatorial signals since it will also effect S_READY
always @ *
begin
// Set the value if we have a slave transaction but master side is not ready
if (S_VALID & s_ready_i & ~M_READY)
has_valid_storage_i = 1'b1;
// Clear the value if it's set and Master side completes the transaction but we don't have a new slave side
// transaction
else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))
has_valid_storage_i = 1'b0;
else
has_valid_storage_i = has_valid_storage;
end // always @ *
always @(posedge ACLK)
begin
if (~aresetn_d[0])
has_valid_storage <= 1'b0;
else
has_valid_storage <= has_valid_storage_i;
end
// S_READY is either clocked M_READY or that we have room in local storage
always @(posedge ACLK)
begin
if (~aresetn_d[0])
s_ready_i <= 1'b0;
else
s_ready_i <= M_READY | ~has_valid_storage_i;
end
// assign local signal to its output signal
assign S_READY = s_ready_i;
// M_READY is either combinatorial S_READY or that we have valid data in local storage
assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];
end // if (C_REG_CONFIG == 3)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED
//
////////////////////////////////////////////////////////////////////
else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))
begin
// synthesis translate_off
initial begin
$display ("ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.");
end
// synthesis translate_on
assign M_PAYLOAD_DATA = 0;
assign M_VALID = 1'b0;
assign S_READY = 1'b0;
end
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 6
// INPUTS mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000006)
begin
reg [1:0] state;
reg [1:0] next_state;
localparam [1:0]
ZERO = 2'b00,
ONE = 2'b01,
TWO = 2'b11;
reg [C_DATA_WIDTH-1:0] storage_data1;
reg [C_DATA_WIDTH-1:0] storage_data2;
reg s_valid_d;
reg s_ready_d;
reg m_ready_d;
reg m_valid_d;
reg load_s2;
reg sel_s2;
wire new_access;
wire access_done;
wire s_ready_i; //local signal of output
reg s_ready_ii;
reg m_valid_i; //local signal of output
reg [1:0] aresetn_d = 2'b00; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign s_ready_i = s_ready_ii & aresetn_d[1];
// Registrate input control signals
always @(posedge ACLK)
begin
if (~aresetn_d[0]) begin
s_valid_d <= 1'b0;
s_ready_d <= 1'b0;
m_ready_d <= 1'b0;
end else begin
s_valid_d <= S_VALID;
s_ready_d <= s_ready_i;
m_ready_d <= M_READY;
end
end // always @ (posedge ACLK)
// Load storage1 with slave side payload data when slave side ready is high
always @(posedge ACLK)
begin
if (s_ready_i)
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with storage data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= storage_data1;
end
always @(posedge ACLK)
begin
if (~aresetn_d[0])
m_valid_d <= 1'b0;
else
m_valid_d <= m_valid_i;
end
// Local help signals
assign new_access = s_ready_d & s_valid_d;
assign access_done = m_ready_d & m_valid_d;
// State Machine for handling output signals
always @*
begin
next_state = state; // Stay in the same state unless we need to move to another state
load_s2 = 0;
sel_s2 = 0;
m_valid_i = 0;
s_ready_ii = 0;
case (state)
// No transaction stored locally
ZERO: begin
load_s2 = 0;
sel_s2 = 0;
m_valid_i = 0;
s_ready_ii = 1;
if (new_access) begin
next_state = ONE; // Got one so move to ONE
load_s2 = 1;
m_valid_i = 0;
end
else begin
next_state = next_state;
load_s2 = load_s2;
m_valid_i = m_valid_i;
end
end // case: ZERO
// One transaction stored locally
ONE: begin
load_s2 = 0;
sel_s2 = 1;
m_valid_i = 1;
s_ready_ii = 1;
if (~new_access & access_done) begin
next_state = ZERO; // Read out one so move to ZERO
m_valid_i = 0;
end
else if (new_access & ~access_done) begin
next_state = TWO; // Got another one so move to TWO
s_ready_ii = 0;
end
else if (new_access & access_done) begin
load_s2 = 1;
sel_s2 = 0;
end
else begin
load_s2 = load_s2;
sel_s2 = sel_s2;
end
end // case: ONE
// TWO transaction stored locally
TWO: begin
load_s2 = 0;
sel_s2 = 1;
m_valid_i = 1;
s_ready_ii = 0;
if (access_done) begin
next_state = ONE; // Read out one so move to ONE
s_ready_ii = 1;
load_s2 = 1;
sel_s2 = 0;
end
else begin
next_state = next_state;
s_ready_ii = s_ready_ii;
load_s2 = load_s2;
sel_s2 = sel_s2;
end
end // case: TWO
endcase // case (state)
end // always @ *
// State Machine for handling output signals
always @(posedge ACLK)
begin
if (~aresetn_d[0])
state <= ZERO;
else
state <= next_state; // Stay in the same state unless we need to move to another state
end
// Master Payload mux
assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;
end // if (C_REG_CONFIG == 6)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 7
// Light-weight mode.
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000007) begin
reg [C_DATA_WIDTH-1:0] m_payload_i;
reg s_ready_i;
reg m_valid_i;
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign M_PAYLOAD_DATA = m_payload_i;
reg [1:0] aresetn_d = 2'b00; // Reset delay shifter
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
always @(posedge ACLK) begin
if (~aresetn_d[0]) begin
s_ready_i <= 1'b0;
end else if (~aresetn_d[1]) begin
s_ready_i <= 1'b1;
end else begin
s_ready_i <= m_valid_i ? M_READY : ~S_VALID;
end
if (~aresetn_d[1]) begin
m_valid_i <= 1'b0;
end else begin
m_valid_i <= s_ready_i ? S_VALID : ~M_READY;
end
if (~m_valid_i) begin
m_payload_i <= S_PAYLOAD_DATA;
end
end
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule |
module.
// 1 => FWD_REV = Both FWD and REV (fully-registered)
// 2 => FWD = The master VALID and payload signals are registrated.
// 3 => REV = The slave ready signal is registrated
// 4 => RESERVED (all outputs driven to 0).
// 5 => RESERVED (all outputs driven to 0).
// 6 => INPUTS = Slave and Master side inputs are registrated.
// 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
(* use_clock_enable = "yes" *)
generate
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 0
// Bypass mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000) begin
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 1 (or 8)
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin
reg [C_DATA_WIDTH-1:0] m_payload_i;
reg [C_DATA_WIDTH-1:0] skid_buffer;
reg s_ready_i;
reg m_valid_i;
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign M_PAYLOAD_DATA = m_payload_i;
reg [1:0] aresetn_d = 2'b00; // Reset delay shifter
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
always @(posedge ACLK) begin
if (~aresetn_d[0]) begin
s_ready_i <= 1'b0;
end else begin
s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);
end
if (~aresetn_d[1]) begin
m_valid_i <= 1'b0;
end else begin
m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);
end
if (M_READY | ~m_valid_i) begin
m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;
end
if (s_ready_i) begin
skid_buffer <= S_PAYLOAD_DATA;
end
end
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 2
// Only FWD mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000002)
begin
reg [C_DATA_WIDTH-1:0] storage_data;
wire s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg aresetn_d = 1'b0; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 1'b0;
end else begin
aresetn_d <= ~ARESET;
end
end
// Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK)
begin
if (S_VALID & s_ready_i)
storage_data <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data;
// M_Valid set to high when we have a completed transfer on slave side
// Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK)
begin
if (~aresetn_d)
m_valid_i <= 1'b0;
else
if (S_VALID) // Always set m_valid_i when slave side is valid
m_valid_i <= 1'b1;
else
if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready
m_valid_i <= 1'b0;
end // always @ (posedge ACLK)
// Slave Ready is either when Master side drives M_Ready or we have space in our storage data
assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;
end // if (C_REG_CONFIG == 2)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 3
// Only REV mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000003)
begin
reg [C_DATA_WIDTH-1:0] storage_data;
reg s_ready_i; //local signal of output
reg has_valid_storage_i;
reg has_valid_storage;
reg [1:0] aresetn_d = 2'b00; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
// Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK)
begin
if (S_VALID & s_ready_i)
storage_data <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;
// Need to determine when we need to save a payload
// Need a combinatorial signals since it will also effect S_READY
always @ *
begin
// Set the value if we have a slave transaction but master side is not ready
if (S_VALID & s_ready_i & ~M_READY)
has_valid_storage_i = 1'b1;
// Clear the value if it's set and Master side completes the transaction but we don't have a new slave side
// transaction
else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))
has_valid_storage_i = 1'b0;
else
has_valid_storage_i = has_valid_storage;
end // always @ *
always @(posedge ACLK)
begin
if (~aresetn_d[0])
has_valid_storage <= 1'b0;
else
has_valid_storage <= has_valid_storage_i;
end
// S_READY is either clocked M_READY or that we have room in local storage
always @(posedge ACLK)
begin
if (~aresetn_d[0])
s_ready_i <= 1'b0;
else
s_ready_i <= M_READY | ~has_valid_storage_i;
end
// assign local signal to its output signal
assign S_READY = s_ready_i;
// M_READY is either combinatorial S_READY or that we have valid data in local storage
assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];
end // if (C_REG_CONFIG == 3)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED
//
////////////////////////////////////////////////////////////////////
else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))
begin
// synthesis translate_off
initial begin
$display ("ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.");
end
// synthesis translate_on
assign M_PAYLOAD_DATA = 0;
assign M_VALID = 1'b0;
assign S_READY = 1'b0;
end
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 6
// INPUTS mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000006)
begin
reg [1:0] state;
reg [1:0] next_state;
localparam [1:0]
ZERO = 2'b00,
ONE = 2'b01,
TWO = 2'b11;
reg [C_DATA_WIDTH-1:0] storage_data1;
reg [C_DATA_WIDTH-1:0] storage_data2;
reg s_valid_d;
reg s_ready_d;
reg m_ready_d;
reg m_valid_d;
reg load_s2;
reg sel_s2;
wire new_access;
wire access_done;
wire s_ready_i; //local signal of output
reg s_ready_ii;
reg m_valid_i; //local signal of output
reg [1:0] aresetn_d = 2'b00; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign s_ready_i = s_ready_ii & aresetn_d[1];
// Registrate input control signals
always @(posedge ACLK)
begin
if (~aresetn_d[0]) begin
s_valid_d <= 1'b0;
s_ready_d <= 1'b0;
m_ready_d <= 1'b0;
end else begin
s_valid_d <= S_VALID;
s_ready_d <= s_ready_i;
m_ready_d <= M_READY;
end
end // always @ (posedge ACLK)
// Load storage1 with slave side payload data when slave side ready is high
always @(posedge ACLK)
begin
if (s_ready_i)
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with storage data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= storage_data1;
end
always @(posedge ACLK)
begin
if (~aresetn_d[0])
m_valid_d <= 1'b0;
else
m_valid_d <= m_valid_i;
end
// Local help signals
assign new_access = s_ready_d & s_valid_d;
assign access_done = m_ready_d & m_valid_d;
// State Machine for handling output signals
always @*
begin
next_state = state; // Stay in the same state unless we need to move to another state
load_s2 = 0;
sel_s2 = 0;
m_valid_i = 0;
s_ready_ii = 0;
case (state)
// No transaction stored locally
ZERO: begin
load_s2 = 0;
sel_s2 = 0;
m_valid_i = 0;
s_ready_ii = 1;
if (new_access) begin
next_state = ONE; // Got one so move to ONE
load_s2 = 1;
m_valid_i = 0;
end
else begin
next_state = next_state;
load_s2 = load_s2;
m_valid_i = m_valid_i;
end
end // case: ZERO
// One transaction stored locally
ONE: begin
load_s2 = 0;
sel_s2 = 1;
m_valid_i = 1;
s_ready_ii = 1;
if (~new_access & access_done) begin
next_state = ZERO; // Read out one so move to ZERO
m_valid_i = 0;
end
else if (new_access & ~access_done) begin
next_state = TWO; // Got another one so move to TWO
s_ready_ii = 0;
end
else if (new_access & access_done) begin
load_s2 = 1;
sel_s2 = 0;
end
else begin
load_s2 = load_s2;
sel_s2 = sel_s2;
end
end // case: ONE
// TWO transaction stored locally
TWO: begin
load_s2 = 0;
sel_s2 = 1;
m_valid_i = 1;
s_ready_ii = 0;
if (access_done) begin
next_state = ONE; // Read out one so move to ONE
s_ready_ii = 1;
load_s2 = 1;
sel_s2 = 0;
end
else begin
next_state = next_state;
s_ready_ii = s_ready_ii;
load_s2 = load_s2;
sel_s2 = sel_s2;
end
end // case: TWO
endcase // case (state)
end // always @ *
// State Machine for handling output signals
always @(posedge ACLK)
begin
if (~aresetn_d[0])
state <= ZERO;
else
state <= next_state; // Stay in the same state unless we need to move to another state
end
// Master Payload mux
assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;
end // if (C_REG_CONFIG == 6)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 7
// Light-weight mode.
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000007) begin
reg [C_DATA_WIDTH-1:0] m_payload_i;
reg s_ready_i;
reg m_valid_i;
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign M_PAYLOAD_DATA = m_payload_i;
reg [1:0] aresetn_d = 2'b00; // Reset delay shifter
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
always @(posedge ACLK) begin
if (~aresetn_d[0]) begin
s_ready_i <= 1'b0;
end else if (~aresetn_d[1]) begin
s_ready_i <= 1'b1;
end else begin
s_ready_i <= m_valid_i ? M_READY : ~S_VALID;
end
if (~aresetn_d[1]) begin
m_valid_i <= 1'b0;
end else begin
m_valid_i <= s_ready_i ? S_VALID : ~M_READY;
end
if (~m_valid_i) begin
m_payload_i <= S_PAYLOAD_DATA;
end
end
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule |
module.
// 1 => FWD_REV = Both FWD and REV (fully-registered)
// 2 => FWD = The master VALID and payload signals are registrated.
// 3 => REV = The slave ready signal is registrated
// 4 => RESERVED (all outputs driven to 0).
// 5 => RESERVED (all outputs driven to 0).
// 6 => INPUTS = Slave and Master side inputs are registrated.
// 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
(* use_clock_enable = "yes" *)
generate
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 0
// Bypass mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000) begin
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 1 (or 8)
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin
reg [C_DATA_WIDTH-1:0] m_payload_i;
reg [C_DATA_WIDTH-1:0] skid_buffer;
reg s_ready_i;
reg m_valid_i;
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign M_PAYLOAD_DATA = m_payload_i;
reg [1:0] aresetn_d = 2'b00; // Reset delay shifter
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
always @(posedge ACLK) begin
if (~aresetn_d[0]) begin
s_ready_i <= 1'b0;
end else begin
s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);
end
if (~aresetn_d[1]) begin
m_valid_i <= 1'b0;
end else begin
m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);
end
if (M_READY | ~m_valid_i) begin
m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;
end
if (s_ready_i) begin
skid_buffer <= S_PAYLOAD_DATA;
end
end
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 2
// Only FWD mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000002)
begin
reg [C_DATA_WIDTH-1:0] storage_data;
wire s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg aresetn_d = 1'b0; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 1'b0;
end else begin
aresetn_d <= ~ARESET;
end
end
// Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK)
begin
if (S_VALID & s_ready_i)
storage_data <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data;
// M_Valid set to high when we have a completed transfer on slave side
// Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK)
begin
if (~aresetn_d)
m_valid_i <= 1'b0;
else
if (S_VALID) // Always set m_valid_i when slave side is valid
m_valid_i <= 1'b1;
else
if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready
m_valid_i <= 1'b0;
end // always @ (posedge ACLK)
// Slave Ready is either when Master side drives M_Ready or we have space in our storage data
assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;
end // if (C_REG_CONFIG == 2)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 3
// Only REV mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000003)
begin
reg [C_DATA_WIDTH-1:0] storage_data;
reg s_ready_i; //local signal of output
reg has_valid_storage_i;
reg has_valid_storage;
reg [1:0] aresetn_d = 2'b00; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
// Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK)
begin
if (S_VALID & s_ready_i)
storage_data <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;
// Need to determine when we need to save a payload
// Need a combinatorial signals since it will also effect S_READY
always @ *
begin
// Set the value if we have a slave transaction but master side is not ready
if (S_VALID & s_ready_i & ~M_READY)
has_valid_storage_i = 1'b1;
// Clear the value if it's set and Master side completes the transaction but we don't have a new slave side
// transaction
else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))
has_valid_storage_i = 1'b0;
else
has_valid_storage_i = has_valid_storage;
end // always @ *
always @(posedge ACLK)
begin
if (~aresetn_d[0])
has_valid_storage <= 1'b0;
else
has_valid_storage <= has_valid_storage_i;
end
// S_READY is either clocked M_READY or that we have room in local storage
always @(posedge ACLK)
begin
if (~aresetn_d[0])
s_ready_i <= 1'b0;
else
s_ready_i <= M_READY | ~has_valid_storage_i;
end
// assign local signal to its output signal
assign S_READY = s_ready_i;
// M_READY is either combinatorial S_READY or that we have valid data in local storage
assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];
end // if (C_REG_CONFIG == 3)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED
//
////////////////////////////////////////////////////////////////////
else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))
begin
// synthesis translate_off
initial begin
$display ("ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.");
end
// synthesis translate_on
assign M_PAYLOAD_DATA = 0;
assign M_VALID = 1'b0;
assign S_READY = 1'b0;
end
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 6
// INPUTS mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000006)
begin
reg [1:0] state;
reg [1:0] next_state;
localparam [1:0]
ZERO = 2'b00,
ONE = 2'b01,
TWO = 2'b11;
reg [C_DATA_WIDTH-1:0] storage_data1;
reg [C_DATA_WIDTH-1:0] storage_data2;
reg s_valid_d;
reg s_ready_d;
reg m_ready_d;
reg m_valid_d;
reg load_s2;
reg sel_s2;
wire new_access;
wire access_done;
wire s_ready_i; //local signal of output
reg s_ready_ii;
reg m_valid_i; //local signal of output
reg [1:0] aresetn_d = 2'b00; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign s_ready_i = s_ready_ii & aresetn_d[1];
// Registrate input control signals
always @(posedge ACLK)
begin
if (~aresetn_d[0]) begin
s_valid_d <= 1'b0;
s_ready_d <= 1'b0;
m_ready_d <= 1'b0;
end else begin
s_valid_d <= S_VALID;
s_ready_d <= s_ready_i;
m_ready_d <= M_READY;
end
end // always @ (posedge ACLK)
// Load storage1 with slave side payload data when slave side ready is high
always @(posedge ACLK)
begin
if (s_ready_i)
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with storage data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= storage_data1;
end
always @(posedge ACLK)
begin
if (~aresetn_d[0])
m_valid_d <= 1'b0;
else
m_valid_d <= m_valid_i;
end
// Local help signals
assign new_access = s_ready_d & s_valid_d;
assign access_done = m_ready_d & m_valid_d;
// State Machine for handling output signals
always @*
begin
next_state = state; // Stay in the same state unless we need to move to another state
load_s2 = 0;
sel_s2 = 0;
m_valid_i = 0;
s_ready_ii = 0;
case (state)
// No transaction stored locally
ZERO: begin
load_s2 = 0;
sel_s2 = 0;
m_valid_i = 0;
s_ready_ii = 1;
if (new_access) begin
next_state = ONE; // Got one so move to ONE
load_s2 = 1;
m_valid_i = 0;
end
else begin
next_state = next_state;
load_s2 = load_s2;
m_valid_i = m_valid_i;
end
end // case: ZERO
// One transaction stored locally
ONE: begin
load_s2 = 0;
sel_s2 = 1;
m_valid_i = 1;
s_ready_ii = 1;
if (~new_access & access_done) begin
next_state = ZERO; // Read out one so move to ZERO
m_valid_i = 0;
end
else if (new_access & ~access_done) begin
next_state = TWO; // Got another one so move to TWO
s_ready_ii = 0;
end
else if (new_access & access_done) begin
load_s2 = 1;
sel_s2 = 0;
end
else begin
load_s2 = load_s2;
sel_s2 = sel_s2;
end
end // case: ONE
// TWO transaction stored locally
TWO: begin
load_s2 = 0;
sel_s2 = 1;
m_valid_i = 1;
s_ready_ii = 0;
if (access_done) begin
next_state = ONE; // Read out one so move to ONE
s_ready_ii = 1;
load_s2 = 1;
sel_s2 = 0;
end
else begin
next_state = next_state;
s_ready_ii = s_ready_ii;
load_s2 = load_s2;
sel_s2 = sel_s2;
end
end // case: TWO
endcase // case (state)
end // always @ *
// State Machine for handling output signals
always @(posedge ACLK)
begin
if (~aresetn_d[0])
state <= ZERO;
else
state <= next_state; // Stay in the same state unless we need to move to another state
end
// Master Payload mux
assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;
end // if (C_REG_CONFIG == 6)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 7
// Light-weight mode.
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000007) begin
reg [C_DATA_WIDTH-1:0] m_payload_i;
reg s_ready_i;
reg m_valid_i;
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign M_PAYLOAD_DATA = m_payload_i;
reg [1:0] aresetn_d = 2'b00; // Reset delay shifter
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
always @(posedge ACLK) begin
if (~aresetn_d[0]) begin
s_ready_i <= 1'b0;
end else if (~aresetn_d[1]) begin
s_ready_i <= 1'b1;
end else begin
s_ready_i <= m_valid_i ? M_READY : ~S_VALID;
end
if (~aresetn_d[1]) begin
m_valid_i <= 1'b0;
end else begin
m_valid_i <= s_ready_i ? S_VALID : ~M_READY;
end
if (~m_valid_i) begin
m_payload_i <= S_PAYLOAD_DATA;
end
end
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule |
module.
// 1 => FWD_REV = Both FWD and REV (fully-registered)
// 2 => FWD = The master VALID and payload signals are registrated.
// 3 => REV = The slave ready signal is registrated
// 4 => RESERVED (all outputs driven to 0).
// 5 => RESERVED (all outputs driven to 0).
// 6 => INPUTS = Slave and Master side inputs are registrated.
// 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
(* use_clock_enable = "yes" *)
generate
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 0
// Bypass mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000) begin
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 1 (or 8)
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin
reg [C_DATA_WIDTH-1:0] m_payload_i;
reg [C_DATA_WIDTH-1:0] skid_buffer;
reg s_ready_i;
reg m_valid_i;
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign M_PAYLOAD_DATA = m_payload_i;
reg [1:0] aresetn_d = 2'b00; // Reset delay shifter
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
always @(posedge ACLK) begin
if (~aresetn_d[0]) begin
s_ready_i <= 1'b0;
end else begin
s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);
end
if (~aresetn_d[1]) begin
m_valid_i <= 1'b0;
end else begin
m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);
end
if (M_READY | ~m_valid_i) begin
m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;
end
if (s_ready_i) begin
skid_buffer <= S_PAYLOAD_DATA;
end
end
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 2
// Only FWD mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000002)
begin
reg [C_DATA_WIDTH-1:0] storage_data;
wire s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg aresetn_d = 1'b0; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 1'b0;
end else begin
aresetn_d <= ~ARESET;
end
end
// Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK)
begin
if (S_VALID & s_ready_i)
storage_data <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data;
// M_Valid set to high when we have a completed transfer on slave side
// Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK)
begin
if (~aresetn_d)
m_valid_i <= 1'b0;
else
if (S_VALID) // Always set m_valid_i when slave side is valid
m_valid_i <= 1'b1;
else
if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready
m_valid_i <= 1'b0;
end // always @ (posedge ACLK)
// Slave Ready is either when Master side drives M_Ready or we have space in our storage data
assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;
end // if (C_REG_CONFIG == 2)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 3
// Only REV mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000003)
begin
reg [C_DATA_WIDTH-1:0] storage_data;
reg s_ready_i; //local signal of output
reg has_valid_storage_i;
reg has_valid_storage;
reg [1:0] aresetn_d = 2'b00; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
// Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK)
begin
if (S_VALID & s_ready_i)
storage_data <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;
// Need to determine when we need to save a payload
// Need a combinatorial signals since it will also effect S_READY
always @ *
begin
// Set the value if we have a slave transaction but master side is not ready
if (S_VALID & s_ready_i & ~M_READY)
has_valid_storage_i = 1'b1;
// Clear the value if it's set and Master side completes the transaction but we don't have a new slave side
// transaction
else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))
has_valid_storage_i = 1'b0;
else
has_valid_storage_i = has_valid_storage;
end // always @ *
always @(posedge ACLK)
begin
if (~aresetn_d[0])
has_valid_storage <= 1'b0;
else
has_valid_storage <= has_valid_storage_i;
end
// S_READY is either clocked M_READY or that we have room in local storage
always @(posedge ACLK)
begin
if (~aresetn_d[0])
s_ready_i <= 1'b0;
else
s_ready_i <= M_READY | ~has_valid_storage_i;
end
// assign local signal to its output signal
assign S_READY = s_ready_i;
// M_READY is either combinatorial S_READY or that we have valid data in local storage
assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];
end // if (C_REG_CONFIG == 3)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED
//
////////////////////////////////////////////////////////////////////
else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))
begin
// synthesis translate_off
initial begin
$display ("ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.");
end
// synthesis translate_on
assign M_PAYLOAD_DATA = 0;
assign M_VALID = 1'b0;
assign S_READY = 1'b0;
end
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 6
// INPUTS mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000006)
begin
reg [1:0] state;
reg [1:0] next_state;
localparam [1:0]
ZERO = 2'b00,
ONE = 2'b01,
TWO = 2'b11;
reg [C_DATA_WIDTH-1:0] storage_data1;
reg [C_DATA_WIDTH-1:0] storage_data2;
reg s_valid_d;
reg s_ready_d;
reg m_ready_d;
reg m_valid_d;
reg load_s2;
reg sel_s2;
wire new_access;
wire access_done;
wire s_ready_i; //local signal of output
reg s_ready_ii;
reg m_valid_i; //local signal of output
reg [1:0] aresetn_d = 2'b00; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign s_ready_i = s_ready_ii & aresetn_d[1];
// Registrate input control signals
always @(posedge ACLK)
begin
if (~aresetn_d[0]) begin
s_valid_d <= 1'b0;
s_ready_d <= 1'b0;
m_ready_d <= 1'b0;
end else begin
s_valid_d <= S_VALID;
s_ready_d <= s_ready_i;
m_ready_d <= M_READY;
end
end // always @ (posedge ACLK)
// Load storage1 with slave side payload data when slave side ready is high
always @(posedge ACLK)
begin
if (s_ready_i)
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with storage data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= storage_data1;
end
always @(posedge ACLK)
begin
if (~aresetn_d[0])
m_valid_d <= 1'b0;
else
m_valid_d <= m_valid_i;
end
// Local help signals
assign new_access = s_ready_d & s_valid_d;
assign access_done = m_ready_d & m_valid_d;
// State Machine for handling output signals
always @*
begin
next_state = state; // Stay in the same state unless we need to move to another state
load_s2 = 0;
sel_s2 = 0;
m_valid_i = 0;
s_ready_ii = 0;
case (state)
// No transaction stored locally
ZERO: begin
load_s2 = 0;
sel_s2 = 0;
m_valid_i = 0;
s_ready_ii = 1;
if (new_access) begin
next_state = ONE; // Got one so move to ONE
load_s2 = 1;
m_valid_i = 0;
end
else begin
next_state = next_state;
load_s2 = load_s2;
m_valid_i = m_valid_i;
end
end // case: ZERO
// One transaction stored locally
ONE: begin
load_s2 = 0;
sel_s2 = 1;
m_valid_i = 1;
s_ready_ii = 1;
if (~new_access & access_done) begin
next_state = ZERO; // Read out one so move to ZERO
m_valid_i = 0;
end
else if (new_access & ~access_done) begin
next_state = TWO; // Got another one so move to TWO
s_ready_ii = 0;
end
else if (new_access & access_done) begin
load_s2 = 1;
sel_s2 = 0;
end
else begin
load_s2 = load_s2;
sel_s2 = sel_s2;
end
end // case: ONE
// TWO transaction stored locally
TWO: begin
load_s2 = 0;
sel_s2 = 1;
m_valid_i = 1;
s_ready_ii = 0;
if (access_done) begin
next_state = ONE; // Read out one so move to ONE
s_ready_ii = 1;
load_s2 = 1;
sel_s2 = 0;
end
else begin
next_state = next_state;
s_ready_ii = s_ready_ii;
load_s2 = load_s2;
sel_s2 = sel_s2;
end
end // case: TWO
endcase // case (state)
end // always @ *
// State Machine for handling output signals
always @(posedge ACLK)
begin
if (~aresetn_d[0])
state <= ZERO;
else
state <= next_state; // Stay in the same state unless we need to move to another state
end
// Master Payload mux
assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;
end // if (C_REG_CONFIG == 6)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 7
// Light-weight mode.
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000007) begin
reg [C_DATA_WIDTH-1:0] m_payload_i;
reg s_ready_i;
reg m_valid_i;
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign M_PAYLOAD_DATA = m_payload_i;
reg [1:0] aresetn_d = 2'b00; // Reset delay shifter
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
always @(posedge ACLK) begin
if (~aresetn_d[0]) begin
s_ready_i <= 1'b0;
end else if (~aresetn_d[1]) begin
s_ready_i <= 1'b1;
end else begin
s_ready_i <= m_valid_i ? M_READY : ~S_VALID;
end
if (~aresetn_d[1]) begin
m_valid_i <= 1'b0;
end else begin
m_valid_i <= s_ready_i ? S_VALID : ~M_READY;
end
if (~m_valid_i) begin
m_payload_i <= S_PAYLOAD_DATA;
end
end
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule |
module.
// 1 => FWD_REV = Both FWD and REV (fully-registered)
// 2 => FWD = The master VALID and payload signals are registrated.
// 3 => REV = The slave ready signal is registrated
// 4 => RESERVED (all outputs driven to 0).
// 5 => RESERVED (all outputs driven to 0).
// 6 => INPUTS = Slave and Master side inputs are registrated.
// 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
(* use_clock_enable = "yes" *)
generate
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 0
// Bypass mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000) begin
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 1 (or 8)
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin
reg [C_DATA_WIDTH-1:0] m_payload_i;
reg [C_DATA_WIDTH-1:0] skid_buffer;
reg s_ready_i;
reg m_valid_i;
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign M_PAYLOAD_DATA = m_payload_i;
reg [1:0] aresetn_d = 2'b00; // Reset delay shifter
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
always @(posedge ACLK) begin
if (~aresetn_d[0]) begin
s_ready_i <= 1'b0;
end else begin
s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);
end
if (~aresetn_d[1]) begin
m_valid_i <= 1'b0;
end else begin
m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);
end
if (M_READY | ~m_valid_i) begin
m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;
end
if (s_ready_i) begin
skid_buffer <= S_PAYLOAD_DATA;
end
end
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 2
// Only FWD mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000002)
begin
reg [C_DATA_WIDTH-1:0] storage_data;
wire s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg aresetn_d = 1'b0; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 1'b0;
end else begin
aresetn_d <= ~ARESET;
end
end
// Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK)
begin
if (S_VALID & s_ready_i)
storage_data <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data;
// M_Valid set to high when we have a completed transfer on slave side
// Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK)
begin
if (~aresetn_d)
m_valid_i <= 1'b0;
else
if (S_VALID) // Always set m_valid_i when slave side is valid
m_valid_i <= 1'b1;
else
if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready
m_valid_i <= 1'b0;
end // always @ (posedge ACLK)
// Slave Ready is either when Master side drives M_Ready or we have space in our storage data
assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;
end // if (C_REG_CONFIG == 2)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 3
// Only REV mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000003)
begin
reg [C_DATA_WIDTH-1:0] storage_data;
reg s_ready_i; //local signal of output
reg has_valid_storage_i;
reg has_valid_storage;
reg [1:0] aresetn_d = 2'b00; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
// Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK)
begin
if (S_VALID & s_ready_i)
storage_data <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;
// Need to determine when we need to save a payload
// Need a combinatorial signals since it will also effect S_READY
always @ *
begin
// Set the value if we have a slave transaction but master side is not ready
if (S_VALID & s_ready_i & ~M_READY)
has_valid_storage_i = 1'b1;
// Clear the value if it's set and Master side completes the transaction but we don't have a new slave side
// transaction
else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))
has_valid_storage_i = 1'b0;
else
has_valid_storage_i = has_valid_storage;
end // always @ *
always @(posedge ACLK)
begin
if (~aresetn_d[0])
has_valid_storage <= 1'b0;
else
has_valid_storage <= has_valid_storage_i;
end
// S_READY is either clocked M_READY or that we have room in local storage
always @(posedge ACLK)
begin
if (~aresetn_d[0])
s_ready_i <= 1'b0;
else
s_ready_i <= M_READY | ~has_valid_storage_i;
end
// assign local signal to its output signal
assign S_READY = s_ready_i;
// M_READY is either combinatorial S_READY or that we have valid data in local storage
assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];
end // if (C_REG_CONFIG == 3)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED
//
////////////////////////////////////////////////////////////////////
else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))
begin
// synthesis translate_off
initial begin
$display ("ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.");
end
// synthesis translate_on
assign M_PAYLOAD_DATA = 0;
assign M_VALID = 1'b0;
assign S_READY = 1'b0;
end
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 6
// INPUTS mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000006)
begin
reg [1:0] state;
reg [1:0] next_state;
localparam [1:0]
ZERO = 2'b00,
ONE = 2'b01,
TWO = 2'b11;
reg [C_DATA_WIDTH-1:0] storage_data1;
reg [C_DATA_WIDTH-1:0] storage_data2;
reg s_valid_d;
reg s_ready_d;
reg m_ready_d;
reg m_valid_d;
reg load_s2;
reg sel_s2;
wire new_access;
wire access_done;
wire s_ready_i; //local signal of output
reg s_ready_ii;
reg m_valid_i; //local signal of output
reg [1:0] aresetn_d = 2'b00; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign s_ready_i = s_ready_ii & aresetn_d[1];
// Registrate input control signals
always @(posedge ACLK)
begin
if (~aresetn_d[0]) begin
s_valid_d <= 1'b0;
s_ready_d <= 1'b0;
m_ready_d <= 1'b0;
end else begin
s_valid_d <= S_VALID;
s_ready_d <= s_ready_i;
m_ready_d <= M_READY;
end
end // always @ (posedge ACLK)
// Load storage1 with slave side payload data when slave side ready is high
always @(posedge ACLK)
begin
if (s_ready_i)
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with storage data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= storage_data1;
end
always @(posedge ACLK)
begin
if (~aresetn_d[0])
m_valid_d <= 1'b0;
else
m_valid_d <= m_valid_i;
end
// Local help signals
assign new_access = s_ready_d & s_valid_d;
assign access_done = m_ready_d & m_valid_d;
// State Machine for handling output signals
always @*
begin
next_state = state; // Stay in the same state unless we need to move to another state
load_s2 = 0;
sel_s2 = 0;
m_valid_i = 0;
s_ready_ii = 0;
case (state)
// No transaction stored locally
ZERO: begin
load_s2 = 0;
sel_s2 = 0;
m_valid_i = 0;
s_ready_ii = 1;
if (new_access) begin
next_state = ONE; // Got one so move to ONE
load_s2 = 1;
m_valid_i = 0;
end
else begin
next_state = next_state;
load_s2 = load_s2;
m_valid_i = m_valid_i;
end
end // case: ZERO
// One transaction stored locally
ONE: begin
load_s2 = 0;
sel_s2 = 1;
m_valid_i = 1;
s_ready_ii = 1;
if (~new_access & access_done) begin
next_state = ZERO; // Read out one so move to ZERO
m_valid_i = 0;
end
else if (new_access & ~access_done) begin
next_state = TWO; // Got another one so move to TWO
s_ready_ii = 0;
end
else if (new_access & access_done) begin
load_s2 = 1;
sel_s2 = 0;
end
else begin
load_s2 = load_s2;
sel_s2 = sel_s2;
end
end // case: ONE
// TWO transaction stored locally
TWO: begin
load_s2 = 0;
sel_s2 = 1;
m_valid_i = 1;
s_ready_ii = 0;
if (access_done) begin
next_state = ONE; // Read out one so move to ONE
s_ready_ii = 1;
load_s2 = 1;
sel_s2 = 0;
end
else begin
next_state = next_state;
s_ready_ii = s_ready_ii;
load_s2 = load_s2;
sel_s2 = sel_s2;
end
end // case: TWO
endcase // case (state)
end // always @ *
// State Machine for handling output signals
always @(posedge ACLK)
begin
if (~aresetn_d[0])
state <= ZERO;
else
state <= next_state; // Stay in the same state unless we need to move to another state
end
// Master Payload mux
assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;
end // if (C_REG_CONFIG == 6)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 7
// Light-weight mode.
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000007) begin
reg [C_DATA_WIDTH-1:0] m_payload_i;
reg s_ready_i;
reg m_valid_i;
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign M_PAYLOAD_DATA = m_payload_i;
reg [1:0] aresetn_d = 2'b00; // Reset delay shifter
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
always @(posedge ACLK) begin
if (~aresetn_d[0]) begin
s_ready_i <= 1'b0;
end else if (~aresetn_d[1]) begin
s_ready_i <= 1'b1;
end else begin
s_ready_i <= m_valid_i ? M_READY : ~S_VALID;
end
if (~aresetn_d[1]) begin
m_valid_i <= 1'b0;
end else begin
m_valid_i <= s_ready_i ? S_VALID : ~M_READY;
end
if (~m_valid_i) begin
m_payload_i <= S_PAYLOAD_DATA;
end
end
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule |
module.
// 1 => FWD_REV = Both FWD and REV (fully-registered)
// 2 => FWD = The master VALID and payload signals are registrated.
// 3 => REV = The slave ready signal is registrated
// 4 => RESERVED (all outputs driven to 0).
// 5 => RESERVED (all outputs driven to 0).
// 6 => INPUTS = Slave and Master side inputs are registrated.
// 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
(* use_clock_enable = "yes" *)
generate
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 0
// Bypass mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000) begin
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 1 (or 8)
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin
reg [C_DATA_WIDTH-1:0] m_payload_i;
reg [C_DATA_WIDTH-1:0] skid_buffer;
reg s_ready_i;
reg m_valid_i;
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign M_PAYLOAD_DATA = m_payload_i;
reg [1:0] aresetn_d = 2'b00; // Reset delay shifter
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
always @(posedge ACLK) begin
if (~aresetn_d[0]) begin
s_ready_i <= 1'b0;
end else begin
s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);
end
if (~aresetn_d[1]) begin
m_valid_i <= 1'b0;
end else begin
m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);
end
if (M_READY | ~m_valid_i) begin
m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;
end
if (s_ready_i) begin
skid_buffer <= S_PAYLOAD_DATA;
end
end
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 2
// Only FWD mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000002)
begin
reg [C_DATA_WIDTH-1:0] storage_data;
wire s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg aresetn_d = 1'b0; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 1'b0;
end else begin
aresetn_d <= ~ARESET;
end
end
// Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK)
begin
if (S_VALID & s_ready_i)
storage_data <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data;
// M_Valid set to high when we have a completed transfer on slave side
// Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK)
begin
if (~aresetn_d)
m_valid_i <= 1'b0;
else
if (S_VALID) // Always set m_valid_i when slave side is valid
m_valid_i <= 1'b1;
else
if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready
m_valid_i <= 1'b0;
end // always @ (posedge ACLK)
// Slave Ready is either when Master side drives M_Ready or we have space in our storage data
assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;
end // if (C_REG_CONFIG == 2)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 3
// Only REV mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000003)
begin
reg [C_DATA_WIDTH-1:0] storage_data;
reg s_ready_i; //local signal of output
reg has_valid_storage_i;
reg has_valid_storage;
reg [1:0] aresetn_d = 2'b00; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
// Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK)
begin
if (S_VALID & s_ready_i)
storage_data <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;
// Need to determine when we need to save a payload
// Need a combinatorial signals since it will also effect S_READY
always @ *
begin
// Set the value if we have a slave transaction but master side is not ready
if (S_VALID & s_ready_i & ~M_READY)
has_valid_storage_i = 1'b1;
// Clear the value if it's set and Master side completes the transaction but we don't have a new slave side
// transaction
else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))
has_valid_storage_i = 1'b0;
else
has_valid_storage_i = has_valid_storage;
end // always @ *
always @(posedge ACLK)
begin
if (~aresetn_d[0])
has_valid_storage <= 1'b0;
else
has_valid_storage <= has_valid_storage_i;
end
// S_READY is either clocked M_READY or that we have room in local storage
always @(posedge ACLK)
begin
if (~aresetn_d[0])
s_ready_i <= 1'b0;
else
s_ready_i <= M_READY | ~has_valid_storage_i;
end
// assign local signal to its output signal
assign S_READY = s_ready_i;
// M_READY is either combinatorial S_READY or that we have valid data in local storage
assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];
end // if (C_REG_CONFIG == 3)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED
//
////////////////////////////////////////////////////////////////////
else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))
begin
// synthesis translate_off
initial begin
$display ("ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.");
end
// synthesis translate_on
assign M_PAYLOAD_DATA = 0;
assign M_VALID = 1'b0;
assign S_READY = 1'b0;
end
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 6
// INPUTS mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000006)
begin
reg [1:0] state;
reg [1:0] next_state;
localparam [1:0]
ZERO = 2'b00,
ONE = 2'b01,
TWO = 2'b11;
reg [C_DATA_WIDTH-1:0] storage_data1;
reg [C_DATA_WIDTH-1:0] storage_data2;
reg s_valid_d;
reg s_ready_d;
reg m_ready_d;
reg m_valid_d;
reg load_s2;
reg sel_s2;
wire new_access;
wire access_done;
wire s_ready_i; //local signal of output
reg s_ready_ii;
reg m_valid_i; //local signal of output
reg [1:0] aresetn_d = 2'b00; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign s_ready_i = s_ready_ii & aresetn_d[1];
// Registrate input control signals
always @(posedge ACLK)
begin
if (~aresetn_d[0]) begin
s_valid_d <= 1'b0;
s_ready_d <= 1'b0;
m_ready_d <= 1'b0;
end else begin
s_valid_d <= S_VALID;
s_ready_d <= s_ready_i;
m_ready_d <= M_READY;
end
end // always @ (posedge ACLK)
// Load storage1 with slave side payload data when slave side ready is high
always @(posedge ACLK)
begin
if (s_ready_i)
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with storage data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= storage_data1;
end
always @(posedge ACLK)
begin
if (~aresetn_d[0])
m_valid_d <= 1'b0;
else
m_valid_d <= m_valid_i;
end
// Local help signals
assign new_access = s_ready_d & s_valid_d;
assign access_done = m_ready_d & m_valid_d;
// State Machine for handling output signals
always @*
begin
next_state = state; // Stay in the same state unless we need to move to another state
load_s2 = 0;
sel_s2 = 0;
m_valid_i = 0;
s_ready_ii = 0;
case (state)
// No transaction stored locally
ZERO: begin
load_s2 = 0;
sel_s2 = 0;
m_valid_i = 0;
s_ready_ii = 1;
if (new_access) begin
next_state = ONE; // Got one so move to ONE
load_s2 = 1;
m_valid_i = 0;
end
else begin
next_state = next_state;
load_s2 = load_s2;
m_valid_i = m_valid_i;
end
end // case: ZERO
// One transaction stored locally
ONE: begin
load_s2 = 0;
sel_s2 = 1;
m_valid_i = 1;
s_ready_ii = 1;
if (~new_access & access_done) begin
next_state = ZERO; // Read out one so move to ZERO
m_valid_i = 0;
end
else if (new_access & ~access_done) begin
next_state = TWO; // Got another one so move to TWO
s_ready_ii = 0;
end
else if (new_access & access_done) begin
load_s2 = 1;
sel_s2 = 0;
end
else begin
load_s2 = load_s2;
sel_s2 = sel_s2;
end
end // case: ONE
// TWO transaction stored locally
TWO: begin
load_s2 = 0;
sel_s2 = 1;
m_valid_i = 1;
s_ready_ii = 0;
if (access_done) begin
next_state = ONE; // Read out one so move to ONE
s_ready_ii = 1;
load_s2 = 1;
sel_s2 = 0;
end
else begin
next_state = next_state;
s_ready_ii = s_ready_ii;
load_s2 = load_s2;
sel_s2 = sel_s2;
end
end // case: TWO
endcase // case (state)
end // always @ *
// State Machine for handling output signals
always @(posedge ACLK)
begin
if (~aresetn_d[0])
state <= ZERO;
else
state <= next_state; // Stay in the same state unless we need to move to another state
end
// Master Payload mux
assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;
end // if (C_REG_CONFIG == 6)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 7
// Light-weight mode.
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000007) begin
reg [C_DATA_WIDTH-1:0] m_payload_i;
reg s_ready_i;
reg m_valid_i;
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign M_PAYLOAD_DATA = m_payload_i;
reg [1:0] aresetn_d = 2'b00; // Reset delay shifter
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
always @(posedge ACLK) begin
if (~aresetn_d[0]) begin
s_ready_i <= 1'b0;
end else if (~aresetn_d[1]) begin
s_ready_i <= 1'b1;
end else begin
s_ready_i <= m_valid_i ? M_READY : ~S_VALID;
end
if (~aresetn_d[1]) begin
m_valid_i <= 1'b0;
end else begin
m_valid_i <= s_ready_i ? S_VALID : ~M_READY;
end
if (~m_valid_i) begin
m_payload_i <= S_PAYLOAD_DATA;
end
end
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule |
module.
// 1 => FWD_REV = Both FWD and REV (fully-registered)
// 2 => FWD = The master VALID and payload signals are registrated.
// 3 => REV = The slave ready signal is registrated
// 4 => RESERVED (all outputs driven to 0).
// 5 => RESERVED (all outputs driven to 0).
// 6 => INPUTS = Slave and Master side inputs are registrated.
// 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
(* use_clock_enable = "yes" *)
generate
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 0
// Bypass mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000) begin
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 1 (or 8)
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin
reg [C_DATA_WIDTH-1:0] m_payload_i;
reg [C_DATA_WIDTH-1:0] skid_buffer;
reg s_ready_i;
reg m_valid_i;
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign M_PAYLOAD_DATA = m_payload_i;
reg [1:0] aresetn_d = 2'b00; // Reset delay shifter
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
always @(posedge ACLK) begin
if (~aresetn_d[0]) begin
s_ready_i <= 1'b0;
end else begin
s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);
end
if (~aresetn_d[1]) begin
m_valid_i <= 1'b0;
end else begin
m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);
end
if (M_READY | ~m_valid_i) begin
m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;
end
if (s_ready_i) begin
skid_buffer <= S_PAYLOAD_DATA;
end
end
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 2
// Only FWD mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000002)
begin
reg [C_DATA_WIDTH-1:0] storage_data;
wire s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg aresetn_d = 1'b0; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 1'b0;
end else begin
aresetn_d <= ~ARESET;
end
end
// Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK)
begin
if (S_VALID & s_ready_i)
storage_data <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data;
// M_Valid set to high when we have a completed transfer on slave side
// Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK)
begin
if (~aresetn_d)
m_valid_i <= 1'b0;
else
if (S_VALID) // Always set m_valid_i when slave side is valid
m_valid_i <= 1'b1;
else
if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready
m_valid_i <= 1'b0;
end // always @ (posedge ACLK)
// Slave Ready is either when Master side drives M_Ready or we have space in our storage data
assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;
end // if (C_REG_CONFIG == 2)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 3
// Only REV mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000003)
begin
reg [C_DATA_WIDTH-1:0] storage_data;
reg s_ready_i; //local signal of output
reg has_valid_storage_i;
reg has_valid_storage;
reg [1:0] aresetn_d = 2'b00; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
// Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK)
begin
if (S_VALID & s_ready_i)
storage_data <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;
// Need to determine when we need to save a payload
// Need a combinatorial signals since it will also effect S_READY
always @ *
begin
// Set the value if we have a slave transaction but master side is not ready
if (S_VALID & s_ready_i & ~M_READY)
has_valid_storage_i = 1'b1;
// Clear the value if it's set and Master side completes the transaction but we don't have a new slave side
// transaction
else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))
has_valid_storage_i = 1'b0;
else
has_valid_storage_i = has_valid_storage;
end // always @ *
always @(posedge ACLK)
begin
if (~aresetn_d[0])
has_valid_storage <= 1'b0;
else
has_valid_storage <= has_valid_storage_i;
end
// S_READY is either clocked M_READY or that we have room in local storage
always @(posedge ACLK)
begin
if (~aresetn_d[0])
s_ready_i <= 1'b0;
else
s_ready_i <= M_READY | ~has_valid_storage_i;
end
// assign local signal to its output signal
assign S_READY = s_ready_i;
// M_READY is either combinatorial S_READY or that we have valid data in local storage
assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];
end // if (C_REG_CONFIG == 3)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED
//
////////////////////////////////////////////////////////////////////
else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))
begin
// synthesis translate_off
initial begin
$display ("ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.");
end
// synthesis translate_on
assign M_PAYLOAD_DATA = 0;
assign M_VALID = 1'b0;
assign S_READY = 1'b0;
end
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 6
// INPUTS mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000006)
begin
reg [1:0] state;
reg [1:0] next_state;
localparam [1:0]
ZERO = 2'b00,
ONE = 2'b01,
TWO = 2'b11;
reg [C_DATA_WIDTH-1:0] storage_data1;
reg [C_DATA_WIDTH-1:0] storage_data2;
reg s_valid_d;
reg s_ready_d;
reg m_ready_d;
reg m_valid_d;
reg load_s2;
reg sel_s2;
wire new_access;
wire access_done;
wire s_ready_i; //local signal of output
reg s_ready_ii;
reg m_valid_i; //local signal of output
reg [1:0] aresetn_d = 2'b00; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign s_ready_i = s_ready_ii & aresetn_d[1];
// Registrate input control signals
always @(posedge ACLK)
begin
if (~aresetn_d[0]) begin
s_valid_d <= 1'b0;
s_ready_d <= 1'b0;
m_ready_d <= 1'b0;
end else begin
s_valid_d <= S_VALID;
s_ready_d <= s_ready_i;
m_ready_d <= M_READY;
end
end // always @ (posedge ACLK)
// Load storage1 with slave side payload data when slave side ready is high
always @(posedge ACLK)
begin
if (s_ready_i)
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with storage data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= storage_data1;
end
always @(posedge ACLK)
begin
if (~aresetn_d[0])
m_valid_d <= 1'b0;
else
m_valid_d <= m_valid_i;
end
// Local help signals
assign new_access = s_ready_d & s_valid_d;
assign access_done = m_ready_d & m_valid_d;
// State Machine for handling output signals
always @*
begin
next_state = state; // Stay in the same state unless we need to move to another state
load_s2 = 0;
sel_s2 = 0;
m_valid_i = 0;
s_ready_ii = 0;
case (state)
// No transaction stored locally
ZERO: begin
load_s2 = 0;
sel_s2 = 0;
m_valid_i = 0;
s_ready_ii = 1;
if (new_access) begin
next_state = ONE; // Got one so move to ONE
load_s2 = 1;
m_valid_i = 0;
end
else begin
next_state = next_state;
load_s2 = load_s2;
m_valid_i = m_valid_i;
end
end // case: ZERO
// One transaction stored locally
ONE: begin
load_s2 = 0;
sel_s2 = 1;
m_valid_i = 1;
s_ready_ii = 1;
if (~new_access & access_done) begin
next_state = ZERO; // Read out one so move to ZERO
m_valid_i = 0;
end
else if (new_access & ~access_done) begin
next_state = TWO; // Got another one so move to TWO
s_ready_ii = 0;
end
else if (new_access & access_done) begin
load_s2 = 1;
sel_s2 = 0;
end
else begin
load_s2 = load_s2;
sel_s2 = sel_s2;
end
end // case: ONE
// TWO transaction stored locally
TWO: begin
load_s2 = 0;
sel_s2 = 1;
m_valid_i = 1;
s_ready_ii = 0;
if (access_done) begin
next_state = ONE; // Read out one so move to ONE
s_ready_ii = 1;
load_s2 = 1;
sel_s2 = 0;
end
else begin
next_state = next_state;
s_ready_ii = s_ready_ii;
load_s2 = load_s2;
sel_s2 = sel_s2;
end
end // case: TWO
endcase // case (state)
end // always @ *
// State Machine for handling output signals
always @(posedge ACLK)
begin
if (~aresetn_d[0])
state <= ZERO;
else
state <= next_state; // Stay in the same state unless we need to move to another state
end
// Master Payload mux
assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;
end // if (C_REG_CONFIG == 6)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 7
// Light-weight mode.
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000007) begin
reg [C_DATA_WIDTH-1:0] m_payload_i;
reg s_ready_i;
reg m_valid_i;
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign M_PAYLOAD_DATA = m_payload_i;
reg [1:0] aresetn_d = 2'b00; // Reset delay shifter
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
always @(posedge ACLK) begin
if (~aresetn_d[0]) begin
s_ready_i <= 1'b0;
end else if (~aresetn_d[1]) begin
s_ready_i <= 1'b1;
end else begin
s_ready_i <= m_valid_i ? M_READY : ~S_VALID;
end
if (~aresetn_d[1]) begin
m_valid_i <= 1'b0;
end else begin
m_valid_i <= s_ready_i ? S_VALID : ~M_READY;
end
if (~m_valid_i) begin
m_payload_i <= S_PAYLOAD_DATA;
end
end
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule |
module fifo_1kx16 (
aclr,
clock,
data,
rdreq,
wrreq,
almost_empty,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [15:0] data;
input rdreq;
input wrreq;
output almost_empty;
output empty;
output full;
output [15:0] q;
output [9:0] usedw;
wire [9:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [15:0] sub_wire3;
wire sub_wire4;
wire [9:0] usedw = sub_wire0[9:0];
wire empty = sub_wire1;
wire almost_empty = sub_wire2;
wire [15:0] q = sub_wire3[15:0];
wire full = sub_wire4;
scfifo scfifo_component (
.rdreq (rdreq),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.almost_empty (sub_wire2),
.q (sub_wire3),
.full (sub_wire4)
// synopsys translate_off
,
.sclr (),
.almost_full ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.almost_empty_value = 504,
scfifo_component.intended_device_family = "Cyclone",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
scfifo_component.lpm_numwords = 1024,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 16,
scfifo_component.lpm_widthu = 10,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule |
module fifo_1kx16 (
aclr,
clock,
data,
rdreq,
wrreq,
almost_empty,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [15:0] data;
input rdreq;
input wrreq;
output almost_empty;
output empty;
output full;
output [15:0] q;
output [9:0] usedw;
wire [9:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [15:0] sub_wire3;
wire sub_wire4;
wire [9:0] usedw = sub_wire0[9:0];
wire empty = sub_wire1;
wire almost_empty = sub_wire2;
wire [15:0] q = sub_wire3[15:0];
wire full = sub_wire4;
scfifo scfifo_component (
.rdreq (rdreq),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.almost_empty (sub_wire2),
.q (sub_wire3),
.full (sub_wire4)
// synopsys translate_off
,
.sclr (),
.almost_full ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.almost_empty_value = 504,
scfifo_component.intended_device_family = "Cyclone",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
scfifo_component.lpm_numwords = 1024,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 16,
scfifo_component.lpm_widthu = 10,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule |
module fifo_1kx16 (
aclr,
clock,
data,
rdreq,
wrreq,
almost_empty,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [15:0] data;
input rdreq;
input wrreq;
output almost_empty;
output empty;
output full;
output [15:0] q;
output [9:0] usedw;
wire [9:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [15:0] sub_wire3;
wire sub_wire4;
wire [9:0] usedw = sub_wire0[9:0];
wire empty = sub_wire1;
wire almost_empty = sub_wire2;
wire [15:0] q = sub_wire3[15:0];
wire full = sub_wire4;
scfifo scfifo_component (
.rdreq (rdreq),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.almost_empty (sub_wire2),
.q (sub_wire3),
.full (sub_wire4)
// synopsys translate_off
,
.sclr (),
.almost_full ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.almost_empty_value = 504,
scfifo_component.intended_device_family = "Cyclone",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
scfifo_component.lpm_numwords = 1024,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 16,
scfifo_component.lpm_widthu = 10,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule |
module fifo_1kx16 (
aclr,
clock,
data,
rdreq,
wrreq,
almost_empty,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [15:0] data;
input rdreq;
input wrreq;
output almost_empty;
output empty;
output full;
output [15:0] q;
output [9:0] usedw;
wire [9:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [15:0] sub_wire3;
wire sub_wire4;
wire [9:0] usedw = sub_wire0[9:0];
wire empty = sub_wire1;
wire almost_empty = sub_wire2;
wire [15:0] q = sub_wire3[15:0];
wire full = sub_wire4;
scfifo scfifo_component (
.rdreq (rdreq),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.almost_empty (sub_wire2),
.q (sub_wire3),
.full (sub_wire4)
// synopsys translate_off
,
.sclr (),
.almost_full ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.almost_empty_value = 504,
scfifo_component.intended_device_family = "Cyclone",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
scfifo_component.lpm_numwords = 1024,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 16,
scfifo_component.lpm_widthu = 10,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule |
module master_control_multi
( input master_clk, input usbclk,
input wire [6:0] serial_addr, input wire [31:0] serial_data, input wire serial_strobe,
input wire rx_slave_sync,
output tx_bus_reset, output rx_bus_reset,
output wire tx_dsp_reset, output wire rx_dsp_reset,
output wire enable_tx, output wire enable_rx,
output wire sync_rx,
output wire [7:0] interp_rate, output wire [7:0] decim_rate,
output tx_sample_strobe, output strobe_interp,
output rx_sample_strobe, output strobe_decim,
input tx_empty,
input wire [15:0] debug_0,input wire [15:0] debug_1,input wire [15:0] debug_2,input wire [15:0] debug_3,
output wire [15:0] reg_0, output wire [15:0] reg_1, output wire [15:0] reg_2, output wire [15:0] reg_3
);
wire [15:0] reg_1_std;
master_control master_control_standard
( .master_clk(master_clk),.usbclk(usbclk),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
.tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
.enable_tx(enable_tx),.enable_rx(enable_rx),
.interp_rate(interp_rate),.decim_rate(decim_rate),
.tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
.rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
.tx_empty(tx_empty),
.debug_0(debug_0),.debug_1(debug_1),
.debug_2(debug_2),.debug_3(debug_3),
.reg_0(reg_0),.reg_1(reg_1_std),.reg_2(reg_2),.reg_3(reg_3) );
// FIXME need a separate reset for all control settings
// Master/slave Controls assignments
wire [7:0] rx_master_slave_controls;
setting_reg_masked #(`FR_RX_MASTER_SLAVE) sr_rx_mstr_slv_ctrl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rx_master_slave_controls));
assign sync_rx = rx_master_slave_controls[`bitnoFR_RX_SYNC] | (rx_master_slave_controls[`bitnoFR_RX_SYNC_SLAVE] & rx_slave_sync);
//sync if we are told by master_control or if we get a hardware slave sync
//TODO There can be a one sample difference between master and slave sync.
// Maybe use a register for sync_rx which uses the (neg or pos) edge of master_clock and/or rx_slave_sync to trigger
// Or even use a seperate sync_rx_out and sync_rx_internal (which lags behind)
//TODO make output pin not hardwired
assign reg_1 ={(rx_master_slave_controls[`bitnoFR_RX_SYNC_MASTER])? sync_rx:reg_1_std[15],reg_1_std[14:0]};
endmodule |
module master_control_multi
( input master_clk, input usbclk,
input wire [6:0] serial_addr, input wire [31:0] serial_data, input wire serial_strobe,
input wire rx_slave_sync,
output tx_bus_reset, output rx_bus_reset,
output wire tx_dsp_reset, output wire rx_dsp_reset,
output wire enable_tx, output wire enable_rx,
output wire sync_rx,
output wire [7:0] interp_rate, output wire [7:0] decim_rate,
output tx_sample_strobe, output strobe_interp,
output rx_sample_strobe, output strobe_decim,
input tx_empty,
input wire [15:0] debug_0,input wire [15:0] debug_1,input wire [15:0] debug_2,input wire [15:0] debug_3,
output wire [15:0] reg_0, output wire [15:0] reg_1, output wire [15:0] reg_2, output wire [15:0] reg_3
);
wire [15:0] reg_1_std;
master_control master_control_standard
( .master_clk(master_clk),.usbclk(usbclk),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
.tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
.enable_tx(enable_tx),.enable_rx(enable_rx),
.interp_rate(interp_rate),.decim_rate(decim_rate),
.tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
.rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
.tx_empty(tx_empty),
.debug_0(debug_0),.debug_1(debug_1),
.debug_2(debug_2),.debug_3(debug_3),
.reg_0(reg_0),.reg_1(reg_1_std),.reg_2(reg_2),.reg_3(reg_3) );
// FIXME need a separate reset for all control settings
// Master/slave Controls assignments
wire [7:0] rx_master_slave_controls;
setting_reg_masked #(`FR_RX_MASTER_SLAVE) sr_rx_mstr_slv_ctrl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rx_master_slave_controls));
assign sync_rx = rx_master_slave_controls[`bitnoFR_RX_SYNC] | (rx_master_slave_controls[`bitnoFR_RX_SYNC_SLAVE] & rx_slave_sync);
//sync if we are told by master_control or if we get a hardware slave sync
//TODO There can be a one sample difference between master and slave sync.
// Maybe use a register for sync_rx which uses the (neg or pos) edge of master_clock and/or rx_slave_sync to trigger
// Or even use a seperate sync_rx_out and sync_rx_internal (which lags behind)
//TODO make output pin not hardwired
assign reg_1 ={(rx_master_slave_controls[`bitnoFR_RX_SYNC_MASTER])? sync_rx:reg_1_std[15],reg_1_std[14:0]};
endmodule |
module t (clk);
input clk;
reg [0:0] d1;
reg [2:0] d3;
reg [7:0] d8;
wire [0:0] q1;
wire [2:0] q3;
wire [7:0] q8;
// verilator lint_off UNOPTFLAT
reg ena;
// verilator lint_on UNOPTFLAT
condff #(12) condff
(.clk(clk), .sen(1'b0), .ena(ena),
.d({d8,d3,d1}),
.q({q8,q3,q1}));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
//$write("%x %x %x %x\n", cyc, q8, q3, q1);
cyc <= cyc + 1;
if (cyc==1) begin
d1 <= 1'b1; d3<=3'h1; d8<=8'h11;
ena <= 1'b1;
end
if (cyc==2) begin
d1 <= 1'b0; d3<=3'h2; d8<=8'h33;
ena <= 1'b0;
end
if (cyc==3) begin
d1 <= 1'b1; d3<=3'h3; d8<=8'h44;
ena <= 1'b1;
if (q8 != 8'h11) $stop;
end
if (cyc==4) begin
d1 <= 1'b1; d3<=3'h4; d8<=8'h77;
ena <= 1'b1;
if (q8 != 8'h11) $stop;
end
if (cyc==5) begin
d1 <= 1'b1; d3<=3'h0; d8<=8'h88;
ena <= 1'b1;
if (q8 != 8'h44) $stop;
end
if (cyc==6) begin
if (q8 != 8'h77) $stop;
end
if (cyc==7) begin
if (q8 != 8'h88) $stop;
end
//
if (cyc==20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule |
module condff (clk, sen, ena, d, q);
parameter WIDTH = 1;
input clk;
input sen;
input ena;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
condffimp #(.WIDTH(WIDTH))
imp (.clk(clk), .sen(sen), .ena(ena), .d(d), .q(q));
endmodule |
module condffimp (clk, sen, ena, d, q);
parameter WIDTH = 1;
input clk;
input sen;
input ena;
input [WIDTH-1:0] d;
output reg [WIDTH-1:0] q;
wire gatedclk;
clockgate clockgate (.clk(clk), .sen(sen), .ena(ena), .gatedclk(gatedclk));
always @(posedge gatedclk) begin
if (gatedclk === 1'bX) begin
q <= {WIDTH{1'bX}};
end
else begin
q <= d;
end
end
endmodule |
module clockgate (clk, sen, ena, gatedclk);
input clk;
input sen;
input ena;
output gatedclk;
reg ena_b;
wire gatedclk = clk & ena_b;
// verilator lint_off COMBDLY
always @(clk or ena or sen) begin
if (~clk) begin
ena_b <= ena | sen;
end
else begin
if ((clk^sen)===1'bX) ena_b <= 1'bX;
end
end
// verilator lint_on COMBDLY
endmodule |
module t (clk);
input clk;
reg [0:0] d1;
reg [2:0] d3;
reg [7:0] d8;
wire [0:0] q1;
wire [2:0] q3;
wire [7:0] q8;
// verilator lint_off UNOPTFLAT
reg ena;
// verilator lint_on UNOPTFLAT
condff #(12) condff
(.clk(clk), .sen(1'b0), .ena(ena),
.d({d8,d3,d1}),
.q({q8,q3,q1}));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
//$write("%x %x %x %x\n", cyc, q8, q3, q1);
cyc <= cyc + 1;
if (cyc==1) begin
d1 <= 1'b1; d3<=3'h1; d8<=8'h11;
ena <= 1'b1;
end
if (cyc==2) begin
d1 <= 1'b0; d3<=3'h2; d8<=8'h33;
ena <= 1'b0;
end
if (cyc==3) begin
d1 <= 1'b1; d3<=3'h3; d8<=8'h44;
ena <= 1'b1;
if (q8 != 8'h11) $stop;
end
if (cyc==4) begin
d1 <= 1'b1; d3<=3'h4; d8<=8'h77;
ena <= 1'b1;
if (q8 != 8'h11) $stop;
end
if (cyc==5) begin
d1 <= 1'b1; d3<=3'h0; d8<=8'h88;
ena <= 1'b1;
if (q8 != 8'h44) $stop;
end
if (cyc==6) begin
if (q8 != 8'h77) $stop;
end
if (cyc==7) begin
if (q8 != 8'h88) $stop;
end
//
if (cyc==20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule |
module condff (clk, sen, ena, d, q);
parameter WIDTH = 1;
input clk;
input sen;
input ena;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
condffimp #(.WIDTH(WIDTH))
imp (.clk(clk), .sen(sen), .ena(ena), .d(d), .q(q));
endmodule |
module condffimp (clk, sen, ena, d, q);
parameter WIDTH = 1;
input clk;
input sen;
input ena;
input [WIDTH-1:0] d;
output reg [WIDTH-1:0] q;
wire gatedclk;
clockgate clockgate (.clk(clk), .sen(sen), .ena(ena), .gatedclk(gatedclk));
always @(posedge gatedclk) begin
if (gatedclk === 1'bX) begin
q <= {WIDTH{1'bX}};
end
else begin
q <= d;
end
end
endmodule |
module clockgate (clk, sen, ena, gatedclk);
input clk;
input sen;
input ena;
output gatedclk;
reg ena_b;
wire gatedclk = clk & ena_b;
// verilator lint_off COMBDLY
always @(clk or ena or sen) begin
if (~clk) begin
ena_b <= ena | sen;
end
else begin
if ((clk^sen)===1'bX) ena_b <= 1'bX;
end
end
// verilator lint_on COMBDLY
endmodule |
module t (clk);
input clk;
reg [0:0] d1;
reg [2:0] d3;
reg [7:0] d8;
wire [0:0] q1;
wire [2:0] q3;
wire [7:0] q8;
// verilator lint_off UNOPTFLAT
reg ena;
// verilator lint_on UNOPTFLAT
condff #(12) condff
(.clk(clk), .sen(1'b0), .ena(ena),
.d({d8,d3,d1}),
.q({q8,q3,q1}));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
//$write("%x %x %x %x\n", cyc, q8, q3, q1);
cyc <= cyc + 1;
if (cyc==1) begin
d1 <= 1'b1; d3<=3'h1; d8<=8'h11;
ena <= 1'b1;
end
if (cyc==2) begin
d1 <= 1'b0; d3<=3'h2; d8<=8'h33;
ena <= 1'b0;
end
if (cyc==3) begin
d1 <= 1'b1; d3<=3'h3; d8<=8'h44;
ena <= 1'b1;
if (q8 != 8'h11) $stop;
end
if (cyc==4) begin
d1 <= 1'b1; d3<=3'h4; d8<=8'h77;
ena <= 1'b1;
if (q8 != 8'h11) $stop;
end
if (cyc==5) begin
d1 <= 1'b1; d3<=3'h0; d8<=8'h88;
ena <= 1'b1;
if (q8 != 8'h44) $stop;
end
if (cyc==6) begin
if (q8 != 8'h77) $stop;
end
if (cyc==7) begin
if (q8 != 8'h88) $stop;
end
//
if (cyc==20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule |
module condff (clk, sen, ena, d, q);
parameter WIDTH = 1;
input clk;
input sen;
input ena;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
condffimp #(.WIDTH(WIDTH))
imp (.clk(clk), .sen(sen), .ena(ena), .d(d), .q(q));
endmodule |
module condffimp (clk, sen, ena, d, q);
parameter WIDTH = 1;
input clk;
input sen;
input ena;
input [WIDTH-1:0] d;
output reg [WIDTH-1:0] q;
wire gatedclk;
clockgate clockgate (.clk(clk), .sen(sen), .ena(ena), .gatedclk(gatedclk));
always @(posedge gatedclk) begin
if (gatedclk === 1'bX) begin
q <= {WIDTH{1'bX}};
end
else begin
q <= d;
end
end
endmodule |
module clockgate (clk, sen, ena, gatedclk);
input clk;
input sen;
input ena;
output gatedclk;
reg ena_b;
wire gatedclk = clk & ena_b;
// verilator lint_off COMBDLY
always @(clk or ena or sen) begin
if (~clk) begin
ena_b <= ena | sen;
end
else begin
if ((clk^sen)===1'bX) ena_b <= 1'bX;
end
end
// verilator lint_on COMBDLY
endmodule |
module t (clk);
input clk;
reg [0:0] d1;
reg [2:0] d3;
reg [7:0] d8;
wire [0:0] q1;
wire [2:0] q3;
wire [7:0] q8;
// verilator lint_off UNOPTFLAT
reg ena;
// verilator lint_on UNOPTFLAT
condff #(12) condff
(.clk(clk), .sen(1'b0), .ena(ena),
.d({d8,d3,d1}),
.q({q8,q3,q1}));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
//$write("%x %x %x %x\n", cyc, q8, q3, q1);
cyc <= cyc + 1;
if (cyc==1) begin
d1 <= 1'b1; d3<=3'h1; d8<=8'h11;
ena <= 1'b1;
end
if (cyc==2) begin
d1 <= 1'b0; d3<=3'h2; d8<=8'h33;
ena <= 1'b0;
end
if (cyc==3) begin
d1 <= 1'b1; d3<=3'h3; d8<=8'h44;
ena <= 1'b1;
if (q8 != 8'h11) $stop;
end
if (cyc==4) begin
d1 <= 1'b1; d3<=3'h4; d8<=8'h77;
ena <= 1'b1;
if (q8 != 8'h11) $stop;
end
if (cyc==5) begin
d1 <= 1'b1; d3<=3'h0; d8<=8'h88;
ena <= 1'b1;
if (q8 != 8'h44) $stop;
end
if (cyc==6) begin
if (q8 != 8'h77) $stop;
end
if (cyc==7) begin
if (q8 != 8'h88) $stop;
end
//
if (cyc==20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule |
module condff (clk, sen, ena, d, q);
parameter WIDTH = 1;
input clk;
input sen;
input ena;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
condffimp #(.WIDTH(WIDTH))
imp (.clk(clk), .sen(sen), .ena(ena), .d(d), .q(q));
endmodule |
module condffimp (clk, sen, ena, d, q);
parameter WIDTH = 1;
input clk;
input sen;
input ena;
input [WIDTH-1:0] d;
output reg [WIDTH-1:0] q;
wire gatedclk;
clockgate clockgate (.clk(clk), .sen(sen), .ena(ena), .gatedclk(gatedclk));
always @(posedge gatedclk) begin
if (gatedclk === 1'bX) begin
q <= {WIDTH{1'bX}};
end
else begin
q <= d;
end
end
endmodule |
module clockgate (clk, sen, ena, gatedclk);
input clk;
input sen;
input ena;
output gatedclk;
reg ena_b;
wire gatedclk = clk & ena_b;
// verilator lint_off COMBDLY
always @(clk or ena or sen) begin
if (~clk) begin
ena_b <= ena | sen;
end
else begin
if ((clk^sen)===1'bX) ena_b <= 1'bX;
end
end
// verilator lint_on COMBDLY
endmodule |
module t (clk);
input clk;
reg [0:0] d1;
reg [2:0] d3;
reg [7:0] d8;
wire [0:0] q1;
wire [2:0] q3;
wire [7:0] q8;
// verilator lint_off UNOPTFLAT
reg ena;
// verilator lint_on UNOPTFLAT
condff #(12) condff
(.clk(clk), .sen(1'b0), .ena(ena),
.d({d8,d3,d1}),
.q({q8,q3,q1}));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
//$write("%x %x %x %x\n", cyc, q8, q3, q1);
cyc <= cyc + 1;
if (cyc==1) begin
d1 <= 1'b1; d3<=3'h1; d8<=8'h11;
ena <= 1'b1;
end
if (cyc==2) begin
d1 <= 1'b0; d3<=3'h2; d8<=8'h33;
ena <= 1'b0;
end
if (cyc==3) begin
d1 <= 1'b1; d3<=3'h3; d8<=8'h44;
ena <= 1'b1;
if (q8 != 8'h11) $stop;
end
if (cyc==4) begin
d1 <= 1'b1; d3<=3'h4; d8<=8'h77;
ena <= 1'b1;
if (q8 != 8'h11) $stop;
end
if (cyc==5) begin
d1 <= 1'b1; d3<=3'h0; d8<=8'h88;
ena <= 1'b1;
if (q8 != 8'h44) $stop;
end
if (cyc==6) begin
if (q8 != 8'h77) $stop;
end
if (cyc==7) begin
if (q8 != 8'h88) $stop;
end
//
if (cyc==20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule |
module condff (clk, sen, ena, d, q);
parameter WIDTH = 1;
input clk;
input sen;
input ena;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
condffimp #(.WIDTH(WIDTH))
imp (.clk(clk), .sen(sen), .ena(ena), .d(d), .q(q));
endmodule |
module condffimp (clk, sen, ena, d, q);
parameter WIDTH = 1;
input clk;
input sen;
input ena;
input [WIDTH-1:0] d;
output reg [WIDTH-1:0] q;
wire gatedclk;
clockgate clockgate (.clk(clk), .sen(sen), .ena(ena), .gatedclk(gatedclk));
always @(posedge gatedclk) begin
if (gatedclk === 1'bX) begin
q <= {WIDTH{1'bX}};
end
else begin
q <= d;
end
end
endmodule |
module clockgate (clk, sen, ena, gatedclk);
input clk;
input sen;
input ena;
output gatedclk;
reg ena_b;
wire gatedclk = clk & ena_b;
// verilator lint_off COMBDLY
always @(clk or ena or sen) begin
if (~clk) begin
ena_b <= ena | sen;
end
else begin
if ((clk^sen)===1'bX) ena_b <= 1'bX;
end
end
// verilator lint_on COMBDLY
endmodule |
module fifo_4kx16_dc (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
endmodule |
module fifo_4kx16_dc (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
endmodule |
module fifo_4kx16_dc (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
endmodule |
module fifo_4kx16_dc (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
endmodule |
module fifo_4kx16_dc (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
endmodule |
module
// signal to increment to the next mc transaction
input wire next ,
// signal to the fsm there is another transaction required
output reg next_pending
);
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
reg sel_first;
wire [11:0] axaddr_i;
wire [3:0] axlen_i;
reg [11:0] wrap_boundary_axaddr;
reg [3:0] axaddr_offset;
reg [3:0] wrap_second_len;
reg [11:0] wrap_boundary_axaddr_r;
reg [3:0] axaddr_offset_r;
reg [3:0] wrap_second_len_r;
reg [4:0] axlen_cnt;
reg [4:0] wrap_cnt_r;
wire [4:0] wrap_cnt;
reg [11:0] axaddr_wrap;
reg next_pending_r;
localparam L_AXI_ADDR_LOW_BIT = (C_AXI_ADDR_WIDTH >= 12) ? 12 : 11;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
generate
if (C_AXI_ADDR_WIDTH > 12) begin : ADDR_GT_4K
assign cmd_byte_addr = (sel_first) ? axaddr : {axaddr[C_AXI_ADDR_WIDTH-1:L_AXI_ADDR_LOW_BIT],axaddr_wrap[11:0]};
end else begin : ADDR_4K
assign cmd_byte_addr = (sel_first) ? axaddr : axaddr_wrap[11:0];
end
endgenerate
assign axaddr_i = axaddr[11:0];
assign axlen_i = axlen[3:0];
// Mask bits based on transaction length to get wrap boundary low address
// Offset used to calculate the length of each transaction
always @( * ) begin
if(axhandshake) begin
wrap_boundary_axaddr = axaddr_i & ~(axlen_i << axsize[1:0]);
axaddr_offset = axaddr_i[axsize[1:0] +: 4] & axlen_i;
end else begin
wrap_boundary_axaddr = wrap_boundary_axaddr_r;
axaddr_offset = axaddr_offset_r;
end
end
// case (axsize[1:0])
// 2'b00 : axaddr_offset = axaddr_i[4:0] & axlen_i;
// 2'b01 : axaddr_offset = axaddr_i[5:1] & axlen_i;
// 2'b10 : axaddr_offset = axaddr_i[6:2] & axlen_i;
// 2'b11 : axaddr_offset = axaddr_i[7:3] & axlen_i;
// default : axaddr_offset = axaddr_i[7:3] & axlen_i;
// endcase
// The first and the second command from the wrap transaction could
// be of odd length or even length with address offset. This will be
// an issue with BL8, extra transactions have to be issued.
// Rounding up the length to account for extra transactions.
always @( * ) begin
if(axhandshake) begin
wrap_second_len = (axaddr_offset >0) ? axaddr_offset - 1 : 0;
end else begin
wrap_second_len = wrap_second_len_r;
end
end
// registering to be used in the combo logic.
always @(posedge clk) begin
wrap_boundary_axaddr_r <= wrap_boundary_axaddr;
axaddr_offset_r <= axaddr_offset;
wrap_second_len_r <= wrap_second_len;
end
// determining if extra data is required for even offsets
// wrap_cnt used to switch the address for first and second transaction.
assign wrap_cnt = {1'b0, wrap_second_len + {3'b000, (|axaddr_offset)}};
always @(posedge clk)
wrap_cnt_r <= wrap_cnt;
always @(posedge clk) begin
if (axhandshake) begin
axaddr_wrap <= axaddr[11:0];
end if(next)begin
if(axlen_cnt == wrap_cnt_r) begin
axaddr_wrap <= wrap_boundary_axaddr_r;
end else begin
axaddr_wrap <= axaddr_wrap + (1 << axsize[1:0]);
end
end
end
// Even numbber of transactions with offset, inc len by 2 for BL8
always @(posedge clk) begin
if (axhandshake)begin
axlen_cnt <= axlen_i;
next_pending_r <= axlen_i >= 1;
end else if (next) begin
if (axlen_cnt > 1) begin
axlen_cnt <= axlen_cnt - 1;
next_pending_r <= (axlen_cnt - 1) >= 1;
end else begin
axlen_cnt <= 5'd0;
next_pending_r <= 1'b0;
end
end
end
always @( * ) begin
if (axhandshake)begin
next_pending = axlen_i >= 1;
end else if (next) begin
if (axlen_cnt > 1) begin
next_pending = (axlen_cnt - 1) >= 1;
end else begin
next_pending = 1'b0;
end
end else begin
next_pending = next_pending_r;
end
end
// last and ignore signals to data channel. These signals are used for
// BL8 to ignore and insert data for even len transactions with offset
// and odd len transactions
// For odd len transactions with no offset the last read is ignored and
// last write is masked
// For odd len transactions with offset the first read is ignored and
// first write is masked
// For even len transactions with offset the last & first read is ignored and
// last& first write is masked
// For even len transactions no ingnores or masks.
// Indicates if we are on the first transaction of a mc translation with more
// than 1 transaction.
always @(posedge clk) begin
if (reset | axhandshake) begin
sel_first <= 1'b1;
end else if (next) begin
sel_first <= 1'b0;
end
end
endmodule |
module processing_system7_v5_5_w_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_WUSER_WIDTH = 1
// Width of AWUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface (In)
input wire cmd_w_valid,
input wire cmd_w_check,
input wire [C_AXI_ID_WIDTH-1:0] cmd_w_id,
output wire cmd_w_ready,
// Command Interface (Out)
output wire cmd_b_push,
output wire cmd_b_error,
output reg [C_AXI_ID_WIDTH-1:0] cmd_b_id,
input wire cmd_b_full,
// Slave Interface Write Port
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Detecttion.
wire any_strb_deasserted;
wire incoming_strb_issue;
reg first_word;
reg strb_issue;
// Data flow.
wire data_pop;
wire cmd_b_push_blocked;
reg cmd_b_push_i;
/////////////////////////////////////////////////////////////////////////////
// Detect error:
//
// Detect and accumulate error when a transaction shall be scanned for
// potential issues.
// Accumulation of error is restarted for each ne transaction.
//
/////////////////////////////////////////////////////////////////////////////
// Check stobe information
assign any_strb_deasserted = ( S_AXI_WSTRB != {C_AXI_DATA_WIDTH/8{1'b1}} );
assign incoming_strb_issue = cmd_w_valid & S_AXI_WVALID & cmd_w_check & any_strb_deasserted;
// Keep track of first word in a transaction.
always @ (posedge ACLK) begin
if (ARESET) begin
first_word <= 1'b1;
end else if ( data_pop ) begin
first_word <= S_AXI_WLAST;
end
end
// Keep track of error status.
always @ (posedge ACLK) begin
if (ARESET) begin
strb_issue <= 1'b0;
cmd_b_id <= {C_AXI_ID_WIDTH{1'b0}};
end else if ( data_pop ) begin
if ( first_word ) begin
strb_issue <= incoming_strb_issue;
end else begin
strb_issue <= incoming_strb_issue | strb_issue;
end
cmd_b_id <= cmd_w_id;
end
end
assign cmd_b_error = strb_issue;
/////////////////////////////////////////////////////////////////////////////
// Control command queue to B:
//
// Push command to B queue when all data for the transaction has flowed
// through.
// Delay pipelined command until there is room in the Queue.
//
/////////////////////////////////////////////////////////////////////////////
// Detect when data is popped.
assign data_pop = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Push command when last word in transfered (pipelined).
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_push_i <= 1'b0;
end else begin
cmd_b_push_i <= ( S_AXI_WLAST & data_pop ) | cmd_b_push_blocked;
end
end
// Detect if pipelined push is blocked.
assign cmd_b_push_blocked = cmd_b_push_i & cmd_b_full;
// Assign output.
assign cmd_b_push = cmd_b_push_i & ~cmd_b_full;
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Stall commands if FIFO is full or there is no valid command information
// from AW.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign M_AXI_WVALID = S_AXI_WVALID & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Return ready with push back.
assign S_AXI_WREADY = M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// End of burst.
assign cmd_w_ready = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked & S_AXI_WLAST;
/////////////////////////////////////////////////////////////////////////////
// Write propagation:
//
// All information is simply forwarded on from the SI- to MI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
endmodule |
module processing_system7_v5_5_w_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_WUSER_WIDTH = 1
// Width of AWUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface (In)
input wire cmd_w_valid,
input wire cmd_w_check,
input wire [C_AXI_ID_WIDTH-1:0] cmd_w_id,
output wire cmd_w_ready,
// Command Interface (Out)
output wire cmd_b_push,
output wire cmd_b_error,
output reg [C_AXI_ID_WIDTH-1:0] cmd_b_id,
input wire cmd_b_full,
// Slave Interface Write Port
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Detecttion.
wire any_strb_deasserted;
wire incoming_strb_issue;
reg first_word;
reg strb_issue;
// Data flow.
wire data_pop;
wire cmd_b_push_blocked;
reg cmd_b_push_i;
/////////////////////////////////////////////////////////////////////////////
// Detect error:
//
// Detect and accumulate error when a transaction shall be scanned for
// potential issues.
// Accumulation of error is restarted for each ne transaction.
//
/////////////////////////////////////////////////////////////////////////////
// Check stobe information
assign any_strb_deasserted = ( S_AXI_WSTRB != {C_AXI_DATA_WIDTH/8{1'b1}} );
assign incoming_strb_issue = cmd_w_valid & S_AXI_WVALID & cmd_w_check & any_strb_deasserted;
// Keep track of first word in a transaction.
always @ (posedge ACLK) begin
if (ARESET) begin
first_word <= 1'b1;
end else if ( data_pop ) begin
first_word <= S_AXI_WLAST;
end
end
// Keep track of error status.
always @ (posedge ACLK) begin
if (ARESET) begin
strb_issue <= 1'b0;
cmd_b_id <= {C_AXI_ID_WIDTH{1'b0}};
end else if ( data_pop ) begin
if ( first_word ) begin
strb_issue <= incoming_strb_issue;
end else begin
strb_issue <= incoming_strb_issue | strb_issue;
end
cmd_b_id <= cmd_w_id;
end
end
assign cmd_b_error = strb_issue;
/////////////////////////////////////////////////////////////////////////////
// Control command queue to B:
//
// Push command to B queue when all data for the transaction has flowed
// through.
// Delay pipelined command until there is room in the Queue.
//
/////////////////////////////////////////////////////////////////////////////
// Detect when data is popped.
assign data_pop = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Push command when last word in transfered (pipelined).
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_push_i <= 1'b0;
end else begin
cmd_b_push_i <= ( S_AXI_WLAST & data_pop ) | cmd_b_push_blocked;
end
end
// Detect if pipelined push is blocked.
assign cmd_b_push_blocked = cmd_b_push_i & cmd_b_full;
// Assign output.
assign cmd_b_push = cmd_b_push_i & ~cmd_b_full;
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Stall commands if FIFO is full or there is no valid command information
// from AW.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign M_AXI_WVALID = S_AXI_WVALID & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Return ready with push back.
assign S_AXI_WREADY = M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// End of burst.
assign cmd_w_ready = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked & S_AXI_WLAST;
/////////////////////////////////////////////////////////////////////////////
// Write propagation:
//
// All information is simply forwarded on from the SI- to MI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
endmodule |
module processing_system7_v5_5_w_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_WUSER_WIDTH = 1
// Width of AWUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface (In)
input wire cmd_w_valid,
input wire cmd_w_check,
input wire [C_AXI_ID_WIDTH-1:0] cmd_w_id,
output wire cmd_w_ready,
// Command Interface (Out)
output wire cmd_b_push,
output wire cmd_b_error,
output reg [C_AXI_ID_WIDTH-1:0] cmd_b_id,
input wire cmd_b_full,
// Slave Interface Write Port
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Detecttion.
wire any_strb_deasserted;
wire incoming_strb_issue;
reg first_word;
reg strb_issue;
// Data flow.
wire data_pop;
wire cmd_b_push_blocked;
reg cmd_b_push_i;
/////////////////////////////////////////////////////////////////////////////
// Detect error:
//
// Detect and accumulate error when a transaction shall be scanned for
// potential issues.
// Accumulation of error is restarted for each ne transaction.
//
/////////////////////////////////////////////////////////////////////////////
// Check stobe information
assign any_strb_deasserted = ( S_AXI_WSTRB != {C_AXI_DATA_WIDTH/8{1'b1}} );
assign incoming_strb_issue = cmd_w_valid & S_AXI_WVALID & cmd_w_check & any_strb_deasserted;
// Keep track of first word in a transaction.
always @ (posedge ACLK) begin
if (ARESET) begin
first_word <= 1'b1;
end else if ( data_pop ) begin
first_word <= S_AXI_WLAST;
end
end
// Keep track of error status.
always @ (posedge ACLK) begin
if (ARESET) begin
strb_issue <= 1'b0;
cmd_b_id <= {C_AXI_ID_WIDTH{1'b0}};
end else if ( data_pop ) begin
if ( first_word ) begin
strb_issue <= incoming_strb_issue;
end else begin
strb_issue <= incoming_strb_issue | strb_issue;
end
cmd_b_id <= cmd_w_id;
end
end
assign cmd_b_error = strb_issue;
/////////////////////////////////////////////////////////////////////////////
// Control command queue to B:
//
// Push command to B queue when all data for the transaction has flowed
// through.
// Delay pipelined command until there is room in the Queue.
//
/////////////////////////////////////////////////////////////////////////////
// Detect when data is popped.
assign data_pop = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Push command when last word in transfered (pipelined).
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_push_i <= 1'b0;
end else begin
cmd_b_push_i <= ( S_AXI_WLAST & data_pop ) | cmd_b_push_blocked;
end
end
// Detect if pipelined push is blocked.
assign cmd_b_push_blocked = cmd_b_push_i & cmd_b_full;
// Assign output.
assign cmd_b_push = cmd_b_push_i & ~cmd_b_full;
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Stall commands if FIFO is full or there is no valid command information
// from AW.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign M_AXI_WVALID = S_AXI_WVALID & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Return ready with push back.
assign S_AXI_WREADY = M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// End of burst.
assign cmd_w_ready = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked & S_AXI_WLAST;
/////////////////////////////////////////////////////////////////////////////
// Write propagation:
//
// All information is simply forwarded on from the SI- to MI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
endmodule |
module processing_system7_v5_5_w_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_WUSER_WIDTH = 1
// Width of AWUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface (In)
input wire cmd_w_valid,
input wire cmd_w_check,
input wire [C_AXI_ID_WIDTH-1:0] cmd_w_id,
output wire cmd_w_ready,
// Command Interface (Out)
output wire cmd_b_push,
output wire cmd_b_error,
output reg [C_AXI_ID_WIDTH-1:0] cmd_b_id,
input wire cmd_b_full,
// Slave Interface Write Port
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Detecttion.
wire any_strb_deasserted;
wire incoming_strb_issue;
reg first_word;
reg strb_issue;
// Data flow.
wire data_pop;
wire cmd_b_push_blocked;
reg cmd_b_push_i;
/////////////////////////////////////////////////////////////////////////////
// Detect error:
//
// Detect and accumulate error when a transaction shall be scanned for
// potential issues.
// Accumulation of error is restarted for each ne transaction.
//
/////////////////////////////////////////////////////////////////////////////
// Check stobe information
assign any_strb_deasserted = ( S_AXI_WSTRB != {C_AXI_DATA_WIDTH/8{1'b1}} );
assign incoming_strb_issue = cmd_w_valid & S_AXI_WVALID & cmd_w_check & any_strb_deasserted;
// Keep track of first word in a transaction.
always @ (posedge ACLK) begin
if (ARESET) begin
first_word <= 1'b1;
end else if ( data_pop ) begin
first_word <= S_AXI_WLAST;
end
end
// Keep track of error status.
always @ (posedge ACLK) begin
if (ARESET) begin
strb_issue <= 1'b0;
cmd_b_id <= {C_AXI_ID_WIDTH{1'b0}};
end else if ( data_pop ) begin
if ( first_word ) begin
strb_issue <= incoming_strb_issue;
end else begin
strb_issue <= incoming_strb_issue | strb_issue;
end
cmd_b_id <= cmd_w_id;
end
end
assign cmd_b_error = strb_issue;
/////////////////////////////////////////////////////////////////////////////
// Control command queue to B:
//
// Push command to B queue when all data for the transaction has flowed
// through.
// Delay pipelined command until there is room in the Queue.
//
/////////////////////////////////////////////////////////////////////////////
// Detect when data is popped.
assign data_pop = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Push command when last word in transfered (pipelined).
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_push_i <= 1'b0;
end else begin
cmd_b_push_i <= ( S_AXI_WLAST & data_pop ) | cmd_b_push_blocked;
end
end
// Detect if pipelined push is blocked.
assign cmd_b_push_blocked = cmd_b_push_i & cmd_b_full;
// Assign output.
assign cmd_b_push = cmd_b_push_i & ~cmd_b_full;
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Stall commands if FIFO is full or there is no valid command information
// from AW.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign M_AXI_WVALID = S_AXI_WVALID & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Return ready with push back.
assign S_AXI_WREADY = M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// End of burst.
assign cmd_w_ready = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked & S_AXI_WLAST;
/////////////////////////////////////////////////////////////////////////////
// Write propagation:
//
// All information is simply forwarded on from the SI- to MI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
endmodule |
module processing_system7_v5_5_w_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_WUSER_WIDTH = 1
// Width of AWUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface (In)
input wire cmd_w_valid,
input wire cmd_w_check,
input wire [C_AXI_ID_WIDTH-1:0] cmd_w_id,
output wire cmd_w_ready,
// Command Interface (Out)
output wire cmd_b_push,
output wire cmd_b_error,
output reg [C_AXI_ID_WIDTH-1:0] cmd_b_id,
input wire cmd_b_full,
// Slave Interface Write Port
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Detecttion.
wire any_strb_deasserted;
wire incoming_strb_issue;
reg first_word;
reg strb_issue;
// Data flow.
wire data_pop;
wire cmd_b_push_blocked;
reg cmd_b_push_i;
/////////////////////////////////////////////////////////////////////////////
// Detect error:
//
// Detect and accumulate error when a transaction shall be scanned for
// potential issues.
// Accumulation of error is restarted for each ne transaction.
//
/////////////////////////////////////////////////////////////////////////////
// Check stobe information
assign any_strb_deasserted = ( S_AXI_WSTRB != {C_AXI_DATA_WIDTH/8{1'b1}} );
assign incoming_strb_issue = cmd_w_valid & S_AXI_WVALID & cmd_w_check & any_strb_deasserted;
// Keep track of first word in a transaction.
always @ (posedge ACLK) begin
if (ARESET) begin
first_word <= 1'b1;
end else if ( data_pop ) begin
first_word <= S_AXI_WLAST;
end
end
// Keep track of error status.
always @ (posedge ACLK) begin
if (ARESET) begin
strb_issue <= 1'b0;
cmd_b_id <= {C_AXI_ID_WIDTH{1'b0}};
end else if ( data_pop ) begin
if ( first_word ) begin
strb_issue <= incoming_strb_issue;
end else begin
strb_issue <= incoming_strb_issue | strb_issue;
end
cmd_b_id <= cmd_w_id;
end
end
assign cmd_b_error = strb_issue;
/////////////////////////////////////////////////////////////////////////////
// Control command queue to B:
//
// Push command to B queue when all data for the transaction has flowed
// through.
// Delay pipelined command until there is room in the Queue.
//
/////////////////////////////////////////////////////////////////////////////
// Detect when data is popped.
assign data_pop = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Push command when last word in transfered (pipelined).
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_push_i <= 1'b0;
end else begin
cmd_b_push_i <= ( S_AXI_WLAST & data_pop ) | cmd_b_push_blocked;
end
end
// Detect if pipelined push is blocked.
assign cmd_b_push_blocked = cmd_b_push_i & cmd_b_full;
// Assign output.
assign cmd_b_push = cmd_b_push_i & ~cmd_b_full;
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Stall commands if FIFO is full or there is no valid command information
// from AW.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign M_AXI_WVALID = S_AXI_WVALID & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Return ready with push back.
assign S_AXI_WREADY = M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// End of burst.
assign cmd_w_ready = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked & S_AXI_WLAST;
/////////////////////////////////////////////////////////////////////////////
// Write propagation:
//
// All information is simply forwarded on from the SI- to MI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
endmodule |
module lo_simulate(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
divisor
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input [7:0] divisor;
// No logic, straight through.
assign pwr_oe3 = 1'b0;
assign pwr_oe1 = ssp_dout;
assign pwr_oe2 = ssp_dout;
assign pwr_oe4 = ssp_dout;
assign ssp_clk = cross_lo;
assign pwr_lo = 1'b0;
assign pwr_hi = 1'b0;
assign dbg = ssp_frame;
// Divide the clock to be used for the ADC
reg [7:0] pck_divider;
reg clk_state;
always @(posedge pck0)
begin
if(pck_divider == divisor[7:0])
begin
pck_divider <= 8'd0;
clk_state = !clk_state;
end
else
begin
pck_divider <= pck_divider + 1;
end
end
assign adc_clk = ~clk_state;
// Toggle the output with hysteresis
// Set to high if the ADC value is above 200
// Set to low if the ADC value is below 64
reg is_high;
reg is_low;
reg output_state;
always @(posedge pck0)
begin
if((pck_divider == 8'd7) && !clk_state) begin
is_high = (adc_d >= 8'd200);
is_low = (adc_d <= 8'd64);
end
end
always @(posedge is_high or posedge is_low)
begin
if(is_high)
output_state <= 1'd1;
else if(is_low)
output_state <= 1'd0;
end
assign ssp_frame = output_state;
endmodule |
module lo_simulate(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
divisor
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input [7:0] divisor;
// No logic, straight through.
assign pwr_oe3 = 1'b0;
assign pwr_oe1 = ssp_dout;
assign pwr_oe2 = ssp_dout;
assign pwr_oe4 = ssp_dout;
assign ssp_clk = cross_lo;
assign pwr_lo = 1'b0;
assign pwr_hi = 1'b0;
assign dbg = ssp_frame;
// Divide the clock to be used for the ADC
reg [7:0] pck_divider;
reg clk_state;
always @(posedge pck0)
begin
if(pck_divider == divisor[7:0])
begin
pck_divider <= 8'd0;
clk_state = !clk_state;
end
else
begin
pck_divider <= pck_divider + 1;
end
end
assign adc_clk = ~clk_state;
// Toggle the output with hysteresis
// Set to high if the ADC value is above 200
// Set to low if the ADC value is below 64
reg is_high;
reg is_low;
reg output_state;
always @(posedge pck0)
begin
if((pck_divider == 8'd7) && !clk_state) begin
is_high = (adc_d >= 8'd200);
is_low = (adc_d <= 8'd64);
end
end
always @(posedge is_high or posedge is_low)
begin
if(is_high)
output_state <= 1'd1;
else if(is_low)
output_state <= 1'd0;
end
assign ssp_frame = output_state;
endmodule |
module lo_simulate(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
divisor
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input [7:0] divisor;
// No logic, straight through.
assign pwr_oe3 = 1'b0;
assign pwr_oe1 = ssp_dout;
assign pwr_oe2 = ssp_dout;
assign pwr_oe4 = ssp_dout;
assign ssp_clk = cross_lo;
assign pwr_lo = 1'b0;
assign pwr_hi = 1'b0;
assign dbg = ssp_frame;
// Divide the clock to be used for the ADC
reg [7:0] pck_divider;
reg clk_state;
always @(posedge pck0)
begin
if(pck_divider == divisor[7:0])
begin
pck_divider <= 8'd0;
clk_state = !clk_state;
end
else
begin
pck_divider <= pck_divider + 1;
end
end
assign adc_clk = ~clk_state;
// Toggle the output with hysteresis
// Set to high if the ADC value is above 200
// Set to low if the ADC value is below 64
reg is_high;
reg is_low;
reg output_state;
always @(posedge pck0)
begin
if((pck_divider == 8'd7) && !clk_state) begin
is_high = (adc_d >= 8'd200);
is_low = (adc_d <= 8'd64);
end
end
always @(posedge is_high or posedge is_low)
begin
if(is_high)
output_state <= 1'd1;
else if(is_low)
output_state <= 1'd0;
end
assign ssp_frame = output_state;
endmodule |
module FSM_Add_Subtract
(
//INPUTS
input wire clk, //system clock
input wire rst, //system reset
input wire rst_FSM,
input wire beg_FSM, //Begin Finite State Machine
//**REVISAD
//////////////////////////////////////////////////////////////////////////////
//Oper_Start_In evaluation signals
input wire zero_flag_i,
//Exp_operation evaluation signals
input wire norm_iteration_i,
//Barrel_Shifter evaluation signals
//None
//Add_Subt_Sgf evaluation signals
input wire add_overflow_i,
//LZA evaluation signals
//None
//Deco_round evaluation Signals
input wire round_i,
//Final_result evaluation signals
//None
//OUTPUT SIGNALS
////////////////////////////////////////////////////////////////////////////////////
//Oper_Start_In control signals
output wire load_1_o,//Enable input registers
output wire load_2_o,//Enable output registers
//Exp_operation control signals
output reg load_3_o, //Enable Output registers
output reg load_8_o,
output reg A_S_op_o, //Select operation for exponent normalization(Subt for left shift, Add for right shift)
//Barrel shifter control signals
output reg load_4_o, //Enable Output registers
output reg left_right_o, //Select direction shift (right=0, left=1)
output reg bit_shift_o, //bit input for shifts fills
//Add_Subt_sgf control signals
output reg load_5_o, //Enables Output registers
//LZA control signals
output reg load_6_o, //Enables Output registers
//Deco_Round control signals
//None
//Final_Result control signals
output reg load_7_o,
///////////////////////////////\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
//Multiplexer selector for Exp_operation's OPER_A
output reg ctrl_a_o,
//Multiplexer selector for Exp_operation's OPER_B & Barrel_Shifter's Shift value
output reg [1:0] ctrl_b_o,
output reg ctrl_b_load_o,
//Multiplexer selector for Data shift
output reg ctrl_c_o,
//Multiplexer selector for Add_Subt_Sgf's inputs
output reg ctrl_d_o,
//Internal reset signal
output reg rst_int,
//Ready Signal
output reg ready
);
localparam [3:0]
//First I'm going to declarate the registers of the first phase of execution
start = 4'd0, //This state evaluates the beg_FSM to begin operations
load_oper = 4'd1, //This state enables the registers that contains
//both operands and the operator
zero_info_state = 4'd2, //Evaluate zero condition
load_diff_exp = 4'd3, //Enable registers for the exponent on the small value normalization and for the first
//result normalization
extra1_64= 4'd4,
norm_sgf_first= 4'd5, //Enable the barrel shifter's registers and evaluate if it's the first time (small operand) or the
//second time (result normalization)
add_subt = 4'd6, //Enable the add_subt_sgf's registers
add_subt_r = 4'd7, //Enable the add_subt_sgf's registers for round condition
overflow_add = 4'd8,
round_sgf = 4'd9, //Evaluate the significand round condition
overflow_add_r = 4'd10,
extra2_64= 4'd11, //Enable registers for the exponent normalization on round condition
norm_sgf_r = 4'd12, //Enable the barrel shifter's registers for round condition
load_final_result = 4'd13, //Load the final_result's register with the result
ready_flag = 4'd14; //Enable the ready flag with the final result
//**********************REVISADO
reg [3:0] state_reg, state_next ; //state registers declaration
////////////////////////Logic outputs///////////////77
assign load_1_o= (state_reg==load_oper);
assign load_2_o= (state_reg==zero_info_state);
////
always @(posedge clk, posedge rst)
if (rst) begin
state_reg <= start;
end
else begin
state_reg <= state_next;
end
///
always @*
begin
state_next = state_reg;
rst_int = 0;
//Oper_Start_In control signals
//load_1_o=0;
//load_2_o=0;
//Exp_operation control signals
load_3_o=0;
load_8_o=0;
A_S_op_o=1;
//Barrel shifter control signals
load_4_o=0;
left_right_o=0;
bit_shift_o=0; //bit input for shifts fills
//Add_Subt_sgf control signals
load_5_o=0;
//LZA control signals
load_6_o=0;
//Deco_Round control signals
//None
//Final_Result control signals
load_7_o=0;
///////////////////////////////\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
//Multiplexer selector for Exp_operation's OPER_A
ctrl_a_o=0;
//Multiplexer selector for Exp_operation's OPER_B
ctrl_b_o=2'b00;
ctrl_b_load_o=0;
//Multiplexer selector for Barrel_Shifter's Data shift
ctrl_c_o=0;
//Multiplexer selector for Barrel_Shifter's Shift value
//Multiplexer selector for Add_Subt_Sgf's inputs
ctrl_d_o=0;
//Ready Phase
ready = 0;
//**REVISADO
rst_int = 0;
case(state_reg)
//FPU reset
start: begin
rst_int=1;
if(beg_FSM) begin
state_next = load_oper;
end
end
load_oper: //Load input registers for Oper_star in evaluation
begin
// load_1_o = 1;
state_next = zero_info_state;
end
zero_info_state: //In case of zero condition, go to final result for ready flag. Else, continue with the calculation
begin
if (zero_flag_i)begin
state_next = ready_flag;end
else begin
//load_2_o = 1;
state_next = load_diff_exp;end
end
load_diff_exp: //in first instance, Calculate DMP - DmP exponents, in other iteration, evaluation in
begin
load_3_o = 1;
/*
if ()*/
state_next = extra1_64;
end
extra1_64:
begin
load_3_o = 1;
if (norm_iteration_i)begin
load_8_o=1;
if(add_overflow_i)begin
A_S_op_o=0;
left_right_o=0;
bit_shift_o=1;
end
else begin
A_S_op_o=1;
left_right_o=1;
bit_shift_o=0;
end
end
state_next = norm_sgf_first;
end
norm_sgf_first: //
begin
load_4_o = 1;
if (norm_iteration_i)begin
if(add_overflow_i)begin
left_right_o=0;
bit_shift_o=1;
state_next = round_sgf;
end
else begin
left_right_o=1;
bit_shift_o=0;
state_next = round_sgf;end
end
else
state_next = add_subt;
end
add_subt:
begin
//Reg enables
load_5_o = 1;
ctrl_c_o = 1;
state_next = overflow_add;
end
overflow_add:
begin
//Reg enables/Disables
load_6_o=1;
ctrl_b_load_o=1;
if ( add_overflow_i)begin
ctrl_b_o=2'b10;
end
else begin
A_S_op_o=1;
ctrl_b_o=2'b01;
end
//state_next = load_exp_oper_over;
state_next = extra1_64;
end
round_sgf:
begin
load_4_o = 0;
if(round_i) begin
ctrl_d_o =1;
ctrl_a_o = 1;
state_next = add_subt_r; end
else begin
state_next = load_final_result; end
end
add_subt_r:
begin
load_5_o = 1;
state_next = overflow_add_r;
end
overflow_add_r:
begin
ctrl_b_load_o=1;
if ( add_overflow_i)begin
ctrl_b_o=2'b10;
end
else begin
ctrl_b_o=2'b11;
end
state_next = extra2_64;
end
extra2_64:
begin
load_3_o = 1;
load_8_o = 1;
if ( add_overflow_i)begin
A_S_op_o=0;
bit_shift_o=1;
end
state_next = norm_sgf_r;
end
norm_sgf_r:
begin
load_4_o = 1;
if ( add_overflow_i)begin
left_right_o=0;
bit_shift_o=1;
end
state_next = load_final_result;
end
load_final_result:
begin
load_7_o = 1;
state_next = ready_flag;
end
ready_flag:
begin
ready = 1;
if(rst_FSM) begin
state_next = start;end
end
default:
begin
state_next =start;end
endcase
end
endmodule |
module FSM_Add_Subtract
(
//INPUTS
input wire clk, //system clock
input wire rst, //system reset
input wire rst_FSM,
input wire beg_FSM, //Begin Finite State Machine
//**REVISAD
//////////////////////////////////////////////////////////////////////////////
//Oper_Start_In evaluation signals
input wire zero_flag_i,
//Exp_operation evaluation signals
input wire norm_iteration_i,
//Barrel_Shifter evaluation signals
//None
//Add_Subt_Sgf evaluation signals
input wire add_overflow_i,
//LZA evaluation signals
//None
//Deco_round evaluation Signals
input wire round_i,
//Final_result evaluation signals
//None
//OUTPUT SIGNALS
////////////////////////////////////////////////////////////////////////////////////
//Oper_Start_In control signals
output wire load_1_o,//Enable input registers
output wire load_2_o,//Enable output registers
//Exp_operation control signals
output reg load_3_o, //Enable Output registers
output reg load_8_o,
output reg A_S_op_o, //Select operation for exponent normalization(Subt for left shift, Add for right shift)
//Barrel shifter control signals
output reg load_4_o, //Enable Output registers
output reg left_right_o, //Select direction shift (right=0, left=1)
output reg bit_shift_o, //bit input for shifts fills
//Add_Subt_sgf control signals
output reg load_5_o, //Enables Output registers
//LZA control signals
output reg load_6_o, //Enables Output registers
//Deco_Round control signals
//None
//Final_Result control signals
output reg load_7_o,
///////////////////////////////\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
//Multiplexer selector for Exp_operation's OPER_A
output reg ctrl_a_o,
//Multiplexer selector for Exp_operation's OPER_B & Barrel_Shifter's Shift value
output reg [1:0] ctrl_b_o,
output reg ctrl_b_load_o,
//Multiplexer selector for Data shift
output reg ctrl_c_o,
//Multiplexer selector for Add_Subt_Sgf's inputs
output reg ctrl_d_o,
//Internal reset signal
output reg rst_int,
//Ready Signal
output reg ready
);
localparam [3:0]
//First I'm going to declarate the registers of the first phase of execution
start = 4'd0, //This state evaluates the beg_FSM to begin operations
load_oper = 4'd1, //This state enables the registers that contains
//both operands and the operator
zero_info_state = 4'd2, //Evaluate zero condition
load_diff_exp = 4'd3, //Enable registers for the exponent on the small value normalization and for the first
//result normalization
extra1_64= 4'd4,
norm_sgf_first= 4'd5, //Enable the barrel shifter's registers and evaluate if it's the first time (small operand) or the
//second time (result normalization)
add_subt = 4'd6, //Enable the add_subt_sgf's registers
add_subt_r = 4'd7, //Enable the add_subt_sgf's registers for round condition
overflow_add = 4'd8,
round_sgf = 4'd9, //Evaluate the significand round condition
overflow_add_r = 4'd10,
extra2_64= 4'd11, //Enable registers for the exponent normalization on round condition
norm_sgf_r = 4'd12, //Enable the barrel shifter's registers for round condition
load_final_result = 4'd13, //Load the final_result's register with the result
ready_flag = 4'd14; //Enable the ready flag with the final result
//**********************REVISADO
reg [3:0] state_reg, state_next ; //state registers declaration
////////////////////////Logic outputs///////////////77
assign load_1_o= (state_reg==load_oper);
assign load_2_o= (state_reg==zero_info_state);
////
always @(posedge clk, posedge rst)
if (rst) begin
state_reg <= start;
end
else begin
state_reg <= state_next;
end
///
always @*
begin
state_next = state_reg;
rst_int = 0;
//Oper_Start_In control signals
//load_1_o=0;
//load_2_o=0;
//Exp_operation control signals
load_3_o=0;
load_8_o=0;
A_S_op_o=1;
//Barrel shifter control signals
load_4_o=0;
left_right_o=0;
bit_shift_o=0; //bit input for shifts fills
//Add_Subt_sgf control signals
load_5_o=0;
//LZA control signals
load_6_o=0;
//Deco_Round control signals
//None
//Final_Result control signals
load_7_o=0;
///////////////////////////////\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
//Multiplexer selector for Exp_operation's OPER_A
ctrl_a_o=0;
//Multiplexer selector for Exp_operation's OPER_B
ctrl_b_o=2'b00;
ctrl_b_load_o=0;
//Multiplexer selector for Barrel_Shifter's Data shift
ctrl_c_o=0;
//Multiplexer selector for Barrel_Shifter's Shift value
//Multiplexer selector for Add_Subt_Sgf's inputs
ctrl_d_o=0;
//Ready Phase
ready = 0;
//**REVISADO
rst_int = 0;
case(state_reg)
//FPU reset
start: begin
rst_int=1;
if(beg_FSM) begin
state_next = load_oper;
end
end
load_oper: //Load input registers for Oper_star in evaluation
begin
// load_1_o = 1;
state_next = zero_info_state;
end
zero_info_state: //In case of zero condition, go to final result for ready flag. Else, continue with the calculation
begin
if (zero_flag_i)begin
state_next = ready_flag;end
else begin
//load_2_o = 1;
state_next = load_diff_exp;end
end
load_diff_exp: //in first instance, Calculate DMP - DmP exponents, in other iteration, evaluation in
begin
load_3_o = 1;
/*
if ()*/
state_next = extra1_64;
end
extra1_64:
begin
load_3_o = 1;
if (norm_iteration_i)begin
load_8_o=1;
if(add_overflow_i)begin
A_S_op_o=0;
left_right_o=0;
bit_shift_o=1;
end
else begin
A_S_op_o=1;
left_right_o=1;
bit_shift_o=0;
end
end
state_next = norm_sgf_first;
end
norm_sgf_first: //
begin
load_4_o = 1;
if (norm_iteration_i)begin
if(add_overflow_i)begin
left_right_o=0;
bit_shift_o=1;
state_next = round_sgf;
end
else begin
left_right_o=1;
bit_shift_o=0;
state_next = round_sgf;end
end
else
state_next = add_subt;
end
add_subt:
begin
//Reg enables
load_5_o = 1;
ctrl_c_o = 1;
state_next = overflow_add;
end
overflow_add:
begin
//Reg enables/Disables
load_6_o=1;
ctrl_b_load_o=1;
if ( add_overflow_i)begin
ctrl_b_o=2'b10;
end
else begin
A_S_op_o=1;
ctrl_b_o=2'b01;
end
//state_next = load_exp_oper_over;
state_next = extra1_64;
end
round_sgf:
begin
load_4_o = 0;
if(round_i) begin
ctrl_d_o =1;
ctrl_a_o = 1;
state_next = add_subt_r; end
else begin
state_next = load_final_result; end
end
add_subt_r:
begin
load_5_o = 1;
state_next = overflow_add_r;
end
overflow_add_r:
begin
ctrl_b_load_o=1;
if ( add_overflow_i)begin
ctrl_b_o=2'b10;
end
else begin
ctrl_b_o=2'b11;
end
state_next = extra2_64;
end
extra2_64:
begin
load_3_o = 1;
load_8_o = 1;
if ( add_overflow_i)begin
A_S_op_o=0;
bit_shift_o=1;
end
state_next = norm_sgf_r;
end
norm_sgf_r:
begin
load_4_o = 1;
if ( add_overflow_i)begin
left_right_o=0;
bit_shift_o=1;
end
state_next = load_final_result;
end
load_final_result:
begin
load_7_o = 1;
state_next = ready_flag;
end
ready_flag:
begin
ready = 1;
if(rst_FSM) begin
state_next = start;end
end
default:
begin
state_next =start;end
endcase
end
endmodule |
module FSM_Add_Subtract
(
//INPUTS
input wire clk, //system clock
input wire rst, //system reset
input wire rst_FSM,
input wire beg_FSM, //Begin Finite State Machine
//**REVISAD
//////////////////////////////////////////////////////////////////////////////
//Oper_Start_In evaluation signals
input wire zero_flag_i,
//Exp_operation evaluation signals
input wire norm_iteration_i,
//Barrel_Shifter evaluation signals
//None
//Add_Subt_Sgf evaluation signals
input wire add_overflow_i,
//LZA evaluation signals
//None
//Deco_round evaluation Signals
input wire round_i,
//Final_result evaluation signals
//None
//OUTPUT SIGNALS
////////////////////////////////////////////////////////////////////////////////////
//Oper_Start_In control signals
output wire load_1_o,//Enable input registers
output wire load_2_o,//Enable output registers
//Exp_operation control signals
output reg load_3_o, //Enable Output registers
output reg load_8_o,
output reg A_S_op_o, //Select operation for exponent normalization(Subt for left shift, Add for right shift)
//Barrel shifter control signals
output reg load_4_o, //Enable Output registers
output reg left_right_o, //Select direction shift (right=0, left=1)
output reg bit_shift_o, //bit input for shifts fills
//Add_Subt_sgf control signals
output reg load_5_o, //Enables Output registers
//LZA control signals
output reg load_6_o, //Enables Output registers
//Deco_Round control signals
//None
//Final_Result control signals
output reg load_7_o,
///////////////////////////////\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
//Multiplexer selector for Exp_operation's OPER_A
output reg ctrl_a_o,
//Multiplexer selector for Exp_operation's OPER_B & Barrel_Shifter's Shift value
output reg [1:0] ctrl_b_o,
output reg ctrl_b_load_o,
//Multiplexer selector for Data shift
output reg ctrl_c_o,
//Multiplexer selector for Add_Subt_Sgf's inputs
output reg ctrl_d_o,
//Internal reset signal
output reg rst_int,
//Ready Signal
output reg ready
);
localparam [3:0]
//First I'm going to declarate the registers of the first phase of execution
start = 4'd0, //This state evaluates the beg_FSM to begin operations
load_oper = 4'd1, //This state enables the registers that contains
//both operands and the operator
zero_info_state = 4'd2, //Evaluate zero condition
load_diff_exp = 4'd3, //Enable registers for the exponent on the small value normalization and for the first
//result normalization
extra1_64= 4'd4,
norm_sgf_first= 4'd5, //Enable the barrel shifter's registers and evaluate if it's the first time (small operand) or the
//second time (result normalization)
add_subt = 4'd6, //Enable the add_subt_sgf's registers
add_subt_r = 4'd7, //Enable the add_subt_sgf's registers for round condition
overflow_add = 4'd8,
round_sgf = 4'd9, //Evaluate the significand round condition
overflow_add_r = 4'd10,
extra2_64= 4'd11, //Enable registers for the exponent normalization on round condition
norm_sgf_r = 4'd12, //Enable the barrel shifter's registers for round condition
load_final_result = 4'd13, //Load the final_result's register with the result
ready_flag = 4'd14; //Enable the ready flag with the final result
//**********************REVISADO
reg [3:0] state_reg, state_next ; //state registers declaration
////////////////////////Logic outputs///////////////77
assign load_1_o= (state_reg==load_oper);
assign load_2_o= (state_reg==zero_info_state);
////
always @(posedge clk, posedge rst)
if (rst) begin
state_reg <= start;
end
else begin
state_reg <= state_next;
end
///
always @*
begin
state_next = state_reg;
rst_int = 0;
//Oper_Start_In control signals
//load_1_o=0;
//load_2_o=0;
//Exp_operation control signals
load_3_o=0;
load_8_o=0;
A_S_op_o=1;
//Barrel shifter control signals
load_4_o=0;
left_right_o=0;
bit_shift_o=0; //bit input for shifts fills
//Add_Subt_sgf control signals
load_5_o=0;
//LZA control signals
load_6_o=0;
//Deco_Round control signals
//None
//Final_Result control signals
load_7_o=0;
///////////////////////////////\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
//Multiplexer selector for Exp_operation's OPER_A
ctrl_a_o=0;
//Multiplexer selector for Exp_operation's OPER_B
ctrl_b_o=2'b00;
ctrl_b_load_o=0;
//Multiplexer selector for Barrel_Shifter's Data shift
ctrl_c_o=0;
//Multiplexer selector for Barrel_Shifter's Shift value
//Multiplexer selector for Add_Subt_Sgf's inputs
ctrl_d_o=0;
//Ready Phase
ready = 0;
//**REVISADO
rst_int = 0;
case(state_reg)
//FPU reset
start: begin
rst_int=1;
if(beg_FSM) begin
state_next = load_oper;
end
end
load_oper: //Load input registers for Oper_star in evaluation
begin
// load_1_o = 1;
state_next = zero_info_state;
end
zero_info_state: //In case of zero condition, go to final result for ready flag. Else, continue with the calculation
begin
if (zero_flag_i)begin
state_next = ready_flag;end
else begin
//load_2_o = 1;
state_next = load_diff_exp;end
end
load_diff_exp: //in first instance, Calculate DMP - DmP exponents, in other iteration, evaluation in
begin
load_3_o = 1;
/*
if ()*/
state_next = extra1_64;
end
extra1_64:
begin
load_3_o = 1;
if (norm_iteration_i)begin
load_8_o=1;
if(add_overflow_i)begin
A_S_op_o=0;
left_right_o=0;
bit_shift_o=1;
end
else begin
A_S_op_o=1;
left_right_o=1;
bit_shift_o=0;
end
end
state_next = norm_sgf_first;
end
norm_sgf_first: //
begin
load_4_o = 1;
if (norm_iteration_i)begin
if(add_overflow_i)begin
left_right_o=0;
bit_shift_o=1;
state_next = round_sgf;
end
else begin
left_right_o=1;
bit_shift_o=0;
state_next = round_sgf;end
end
else
state_next = add_subt;
end
add_subt:
begin
//Reg enables
load_5_o = 1;
ctrl_c_o = 1;
state_next = overflow_add;
end
overflow_add:
begin
//Reg enables/Disables
load_6_o=1;
ctrl_b_load_o=1;
if ( add_overflow_i)begin
ctrl_b_o=2'b10;
end
else begin
A_S_op_o=1;
ctrl_b_o=2'b01;
end
//state_next = load_exp_oper_over;
state_next = extra1_64;
end
round_sgf:
begin
load_4_o = 0;
if(round_i) begin
ctrl_d_o =1;
ctrl_a_o = 1;
state_next = add_subt_r; end
else begin
state_next = load_final_result; end
end
add_subt_r:
begin
load_5_o = 1;
state_next = overflow_add_r;
end
overflow_add_r:
begin
ctrl_b_load_o=1;
if ( add_overflow_i)begin
ctrl_b_o=2'b10;
end
else begin
ctrl_b_o=2'b11;
end
state_next = extra2_64;
end
extra2_64:
begin
load_3_o = 1;
load_8_o = 1;
if ( add_overflow_i)begin
A_S_op_o=0;
bit_shift_o=1;
end
state_next = norm_sgf_r;
end
norm_sgf_r:
begin
load_4_o = 1;
if ( add_overflow_i)begin
left_right_o=0;
bit_shift_o=1;
end
state_next = load_final_result;
end
load_final_result:
begin
load_7_o = 1;
state_next = ready_flag;
end
ready_flag:
begin
ready = 1;
if(rst_FSM) begin
state_next = start;end
end
default:
begin
state_next =start;end
endcase
end
endmodule |
module FSM_Add_Subtract
(
//INPUTS
input wire clk, //system clock
input wire rst, //system reset
input wire rst_FSM,
input wire beg_FSM, //Begin Finite State Machine
//**REVISAD
//////////////////////////////////////////////////////////////////////////////
//Oper_Start_In evaluation signals
input wire zero_flag_i,
//Exp_operation evaluation signals
input wire norm_iteration_i,
//Barrel_Shifter evaluation signals
//None
//Add_Subt_Sgf evaluation signals
input wire add_overflow_i,
//LZA evaluation signals
//None
//Deco_round evaluation Signals
input wire round_i,
//Final_result evaluation signals
//None
//OUTPUT SIGNALS
////////////////////////////////////////////////////////////////////////////////////
//Oper_Start_In control signals
output wire load_1_o,//Enable input registers
output wire load_2_o,//Enable output registers
//Exp_operation control signals
output reg load_3_o, //Enable Output registers
output reg load_8_o,
output reg A_S_op_o, //Select operation for exponent normalization(Subt for left shift, Add for right shift)
//Barrel shifter control signals
output reg load_4_o, //Enable Output registers
output reg left_right_o, //Select direction shift (right=0, left=1)
output reg bit_shift_o, //bit input for shifts fills
//Add_Subt_sgf control signals
output reg load_5_o, //Enables Output registers
//LZA control signals
output reg load_6_o, //Enables Output registers
//Deco_Round control signals
//None
//Final_Result control signals
output reg load_7_o,
///////////////////////////////\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
//Multiplexer selector for Exp_operation's OPER_A
output reg ctrl_a_o,
//Multiplexer selector for Exp_operation's OPER_B & Barrel_Shifter's Shift value
output reg [1:0] ctrl_b_o,
output reg ctrl_b_load_o,
//Multiplexer selector for Data shift
output reg ctrl_c_o,
//Multiplexer selector for Add_Subt_Sgf's inputs
output reg ctrl_d_o,
//Internal reset signal
output reg rst_int,
//Ready Signal
output reg ready
);
localparam [3:0]
//First I'm going to declarate the registers of the first phase of execution
start = 4'd0, //This state evaluates the beg_FSM to begin operations
load_oper = 4'd1, //This state enables the registers that contains
//both operands and the operator
zero_info_state = 4'd2, //Evaluate zero condition
load_diff_exp = 4'd3, //Enable registers for the exponent on the small value normalization and for the first
//result normalization
extra1_64= 4'd4,
norm_sgf_first= 4'd5, //Enable the barrel shifter's registers and evaluate if it's the first time (small operand) or the
//second time (result normalization)
add_subt = 4'd6, //Enable the add_subt_sgf's registers
add_subt_r = 4'd7, //Enable the add_subt_sgf's registers for round condition
overflow_add = 4'd8,
round_sgf = 4'd9, //Evaluate the significand round condition
overflow_add_r = 4'd10,
extra2_64= 4'd11, //Enable registers for the exponent normalization on round condition
norm_sgf_r = 4'd12, //Enable the barrel shifter's registers for round condition
load_final_result = 4'd13, //Load the final_result's register with the result
ready_flag = 4'd14; //Enable the ready flag with the final result
//**********************REVISADO
reg [3:0] state_reg, state_next ; //state registers declaration
////////////////////////Logic outputs///////////////77
assign load_1_o= (state_reg==load_oper);
assign load_2_o= (state_reg==zero_info_state);
////
always @(posedge clk, posedge rst)
if (rst) begin
state_reg <= start;
end
else begin
state_reg <= state_next;
end
///
always @*
begin
state_next = state_reg;
rst_int = 0;
//Oper_Start_In control signals
//load_1_o=0;
//load_2_o=0;
//Exp_operation control signals
load_3_o=0;
load_8_o=0;
A_S_op_o=1;
//Barrel shifter control signals
load_4_o=0;
left_right_o=0;
bit_shift_o=0; //bit input for shifts fills
//Add_Subt_sgf control signals
load_5_o=0;
//LZA control signals
load_6_o=0;
//Deco_Round control signals
//None
//Final_Result control signals
load_7_o=0;
///////////////////////////////\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
//Multiplexer selector for Exp_operation's OPER_A
ctrl_a_o=0;
//Multiplexer selector for Exp_operation's OPER_B
ctrl_b_o=2'b00;
ctrl_b_load_o=0;
//Multiplexer selector for Barrel_Shifter's Data shift
ctrl_c_o=0;
//Multiplexer selector for Barrel_Shifter's Shift value
//Multiplexer selector for Add_Subt_Sgf's inputs
ctrl_d_o=0;
//Ready Phase
ready = 0;
//**REVISADO
rst_int = 0;
case(state_reg)
//FPU reset
start: begin
rst_int=1;
if(beg_FSM) begin
state_next = load_oper;
end
end
load_oper: //Load input registers for Oper_star in evaluation
begin
// load_1_o = 1;
state_next = zero_info_state;
end
zero_info_state: //In case of zero condition, go to final result for ready flag. Else, continue with the calculation
begin
if (zero_flag_i)begin
state_next = ready_flag;end
else begin
//load_2_o = 1;
state_next = load_diff_exp;end
end
load_diff_exp: //in first instance, Calculate DMP - DmP exponents, in other iteration, evaluation in
begin
load_3_o = 1;
/*
if ()*/
state_next = extra1_64;
end
extra1_64:
begin
load_3_o = 1;
if (norm_iteration_i)begin
load_8_o=1;
if(add_overflow_i)begin
A_S_op_o=0;
left_right_o=0;
bit_shift_o=1;
end
else begin
A_S_op_o=1;
left_right_o=1;
bit_shift_o=0;
end
end
state_next = norm_sgf_first;
end
norm_sgf_first: //
begin
load_4_o = 1;
if (norm_iteration_i)begin
if(add_overflow_i)begin
left_right_o=0;
bit_shift_o=1;
state_next = round_sgf;
end
else begin
left_right_o=1;
bit_shift_o=0;
state_next = round_sgf;end
end
else
state_next = add_subt;
end
add_subt:
begin
//Reg enables
load_5_o = 1;
ctrl_c_o = 1;
state_next = overflow_add;
end
overflow_add:
begin
//Reg enables/Disables
load_6_o=1;
ctrl_b_load_o=1;
if ( add_overflow_i)begin
ctrl_b_o=2'b10;
end
else begin
A_S_op_o=1;
ctrl_b_o=2'b01;
end
//state_next = load_exp_oper_over;
state_next = extra1_64;
end
round_sgf:
begin
load_4_o = 0;
if(round_i) begin
ctrl_d_o =1;
ctrl_a_o = 1;
state_next = add_subt_r; end
else begin
state_next = load_final_result; end
end
add_subt_r:
begin
load_5_o = 1;
state_next = overflow_add_r;
end
overflow_add_r:
begin
ctrl_b_load_o=1;
if ( add_overflow_i)begin
ctrl_b_o=2'b10;
end
else begin
ctrl_b_o=2'b11;
end
state_next = extra2_64;
end
extra2_64:
begin
load_3_o = 1;
load_8_o = 1;
if ( add_overflow_i)begin
A_S_op_o=0;
bit_shift_o=1;
end
state_next = norm_sgf_r;
end
norm_sgf_r:
begin
load_4_o = 1;
if ( add_overflow_i)begin
left_right_o=0;
bit_shift_o=1;
end
state_next = load_final_result;
end
load_final_result:
begin
load_7_o = 1;
state_next = ready_flag;
end
ready_flag:
begin
ready = 1;
if(rst_FSM) begin
state_next = start;end
end
default:
begin
state_next =start;end
endcase
end
endmodule |
module FSM_Add_Subtract
(
//INPUTS
input wire clk, //system clock
input wire rst, //system reset
input wire rst_FSM,
input wire beg_FSM, //Begin Finite State Machine
//**REVISAD
//////////////////////////////////////////////////////////////////////////////
//Oper_Start_In evaluation signals
input wire zero_flag_i,
//Exp_operation evaluation signals
input wire norm_iteration_i,
//Barrel_Shifter evaluation signals
//None
//Add_Subt_Sgf evaluation signals
input wire add_overflow_i,
//LZA evaluation signals
//None
//Deco_round evaluation Signals
input wire round_i,
//Final_result evaluation signals
//None
//OUTPUT SIGNALS
////////////////////////////////////////////////////////////////////////////////////
//Oper_Start_In control signals
output wire load_1_o,//Enable input registers
output wire load_2_o,//Enable output registers
//Exp_operation control signals
output reg load_3_o, //Enable Output registers
output reg load_8_o,
output reg A_S_op_o, //Select operation for exponent normalization(Subt for left shift, Add for right shift)
//Barrel shifter control signals
output reg load_4_o, //Enable Output registers
output reg left_right_o, //Select direction shift (right=0, left=1)
output reg bit_shift_o, //bit input for shifts fills
//Add_Subt_sgf control signals
output reg load_5_o, //Enables Output registers
//LZA control signals
output reg load_6_o, //Enables Output registers
//Deco_Round control signals
//None
//Final_Result control signals
output reg load_7_o,
///////////////////////////////\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
//Multiplexer selector for Exp_operation's OPER_A
output reg ctrl_a_o,
//Multiplexer selector for Exp_operation's OPER_B & Barrel_Shifter's Shift value
output reg [1:0] ctrl_b_o,
output reg ctrl_b_load_o,
//Multiplexer selector for Data shift
output reg ctrl_c_o,
//Multiplexer selector for Add_Subt_Sgf's inputs
output reg ctrl_d_o,
//Internal reset signal
output reg rst_int,
//Ready Signal
output reg ready
);
localparam [3:0]
//First I'm going to declarate the registers of the first phase of execution
start = 4'd0, //This state evaluates the beg_FSM to begin operations
load_oper = 4'd1, //This state enables the registers that contains
//both operands and the operator
zero_info_state = 4'd2, //Evaluate zero condition
load_diff_exp = 4'd3, //Enable registers for the exponent on the small value normalization and for the first
//result normalization
extra1_64= 4'd4,
norm_sgf_first= 4'd5, //Enable the barrel shifter's registers and evaluate if it's the first time (small operand) or the
//second time (result normalization)
add_subt = 4'd6, //Enable the add_subt_sgf's registers
add_subt_r = 4'd7, //Enable the add_subt_sgf's registers for round condition
overflow_add = 4'd8,
round_sgf = 4'd9, //Evaluate the significand round condition
overflow_add_r = 4'd10,
extra2_64= 4'd11, //Enable registers for the exponent normalization on round condition
norm_sgf_r = 4'd12, //Enable the barrel shifter's registers for round condition
load_final_result = 4'd13, //Load the final_result's register with the result
ready_flag = 4'd14; //Enable the ready flag with the final result
//**********************REVISADO
reg [3:0] state_reg, state_next ; //state registers declaration
////////////////////////Logic outputs///////////////77
assign load_1_o= (state_reg==load_oper);
assign load_2_o= (state_reg==zero_info_state);
////
always @(posedge clk, posedge rst)
if (rst) begin
state_reg <= start;
end
else begin
state_reg <= state_next;
end
///
always @*
begin
state_next = state_reg;
rst_int = 0;
//Oper_Start_In control signals
//load_1_o=0;
//load_2_o=0;
//Exp_operation control signals
load_3_o=0;
load_8_o=0;
A_S_op_o=1;
//Barrel shifter control signals
load_4_o=0;
left_right_o=0;
bit_shift_o=0; //bit input for shifts fills
//Add_Subt_sgf control signals
load_5_o=0;
//LZA control signals
load_6_o=0;
//Deco_Round control signals
//None
//Final_Result control signals
load_7_o=0;
///////////////////////////////\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
//Multiplexer selector for Exp_operation's OPER_A
ctrl_a_o=0;
//Multiplexer selector for Exp_operation's OPER_B
ctrl_b_o=2'b00;
ctrl_b_load_o=0;
//Multiplexer selector for Barrel_Shifter's Data shift
ctrl_c_o=0;
//Multiplexer selector for Barrel_Shifter's Shift value
//Multiplexer selector for Add_Subt_Sgf's inputs
ctrl_d_o=0;
//Ready Phase
ready = 0;
//**REVISADO
rst_int = 0;
case(state_reg)
//FPU reset
start: begin
rst_int=1;
if(beg_FSM) begin
state_next = load_oper;
end
end
load_oper: //Load input registers for Oper_star in evaluation
begin
// load_1_o = 1;
state_next = zero_info_state;
end
zero_info_state: //In case of zero condition, go to final result for ready flag. Else, continue with the calculation
begin
if (zero_flag_i)begin
state_next = ready_flag;end
else begin
//load_2_o = 1;
state_next = load_diff_exp;end
end
load_diff_exp: //in first instance, Calculate DMP - DmP exponents, in other iteration, evaluation in
begin
load_3_o = 1;
/*
if ()*/
state_next = extra1_64;
end
extra1_64:
begin
load_3_o = 1;
if (norm_iteration_i)begin
load_8_o=1;
if(add_overflow_i)begin
A_S_op_o=0;
left_right_o=0;
bit_shift_o=1;
end
else begin
A_S_op_o=1;
left_right_o=1;
bit_shift_o=0;
end
end
state_next = norm_sgf_first;
end
norm_sgf_first: //
begin
load_4_o = 1;
if (norm_iteration_i)begin
if(add_overflow_i)begin
left_right_o=0;
bit_shift_o=1;
state_next = round_sgf;
end
else begin
left_right_o=1;
bit_shift_o=0;
state_next = round_sgf;end
end
else
state_next = add_subt;
end
add_subt:
begin
//Reg enables
load_5_o = 1;
ctrl_c_o = 1;
state_next = overflow_add;
end
overflow_add:
begin
//Reg enables/Disables
load_6_o=1;
ctrl_b_load_o=1;
if ( add_overflow_i)begin
ctrl_b_o=2'b10;
end
else begin
A_S_op_o=1;
ctrl_b_o=2'b01;
end
//state_next = load_exp_oper_over;
state_next = extra1_64;
end
round_sgf:
begin
load_4_o = 0;
if(round_i) begin
ctrl_d_o =1;
ctrl_a_o = 1;
state_next = add_subt_r; end
else begin
state_next = load_final_result; end
end
add_subt_r:
begin
load_5_o = 1;
state_next = overflow_add_r;
end
overflow_add_r:
begin
ctrl_b_load_o=1;
if ( add_overflow_i)begin
ctrl_b_o=2'b10;
end
else begin
ctrl_b_o=2'b11;
end
state_next = extra2_64;
end
extra2_64:
begin
load_3_o = 1;
load_8_o = 1;
if ( add_overflow_i)begin
A_S_op_o=0;
bit_shift_o=1;
end
state_next = norm_sgf_r;
end
norm_sgf_r:
begin
load_4_o = 1;
if ( add_overflow_i)begin
left_right_o=0;
bit_shift_o=1;
end
state_next = load_final_result;
end
load_final_result:
begin
load_7_o = 1;
state_next = ready_flag;
end
ready_flag:
begin
ready = 1;
if(rst_FSM) begin
state_next = start;end
end
default:
begin
state_next =start;end
endcase
end
endmodule |
module
input wire r_push ,
output wire r_full ,
// length not needed. Can be removed.
input wire [C_ID_WIDTH-1:0] r_arid ,
input wire r_rlast
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_WIDTH = 1+C_ID_WIDTH;
localparam P_DEPTH = 32;
localparam P_AWIDTH = 5;
localparam P_D_WIDTH = C_DATA_WIDTH + 2;
// rd data FIFO depth varies based on burst length.
// For Bl8 it is two times the size of transaction FIFO.
// Only in 2:1 mode BL8 transactions will happen which results in
// two beats of read data per read transaction.
localparam P_D_DEPTH = 32;
localparam P_D_AWIDTH = 5;
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
wire [C_ID_WIDTH+1-1:0] trans_in;
wire [C_ID_WIDTH+1-1:0] trans_out;
wire tr_empty;
wire rhandshake;
wire r_valid_i;
wire [P_D_WIDTH-1:0] rd_data_fifo_in;
wire [P_D_WIDTH-1:0] rd_data_fifo_out;
wire rd_en;
wire rd_full;
wire rd_empty;
wire rd_a_full;
wire fifo_a_full;
reg [C_ID_WIDTH-1:0] r_arid_r;
reg r_rlast_r;
reg r_push_r;
wire fifo_full;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
assign s_rresp = rd_data_fifo_out[P_D_WIDTH-1:C_DATA_WIDTH];
assign s_rid = trans_out[1+:C_ID_WIDTH];
assign s_rdata = rd_data_fifo_out[C_DATA_WIDTH-1:0];
assign s_rlast = trans_out[0];
assign s_rvalid = ~rd_empty & ~tr_empty;
// assign MCB outputs
assign rd_en = rhandshake & (~rd_empty);
assign rhandshake =(s_rvalid & s_rready);
// register for timing
always @(posedge clk) begin
r_arid_r <= r_arid;
r_rlast_r <= r_rlast;
r_push_r <= r_push;
end
assign trans_in[0] = r_rlast_r;
assign trans_in[1+:C_ID_WIDTH] = r_arid_r;
// rd data fifo
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_D_WIDTH),
.C_AWIDTH (P_D_AWIDTH),
.C_DEPTH (P_D_DEPTH)
)
rd_data_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( m_rvalid & m_rready ) ,
.rd_en ( rd_en ) ,
.din ( rd_data_fifo_in ) ,
.dout ( rd_data_fifo_out ) ,
.a_full ( rd_a_full ) ,
.full ( rd_full ) ,
.a_empty ( ) ,
.empty ( rd_empty )
);
assign rd_data_fifo_in = {m_rresp, m_rdata};
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_WIDTH),
.C_AWIDTH (P_AWIDTH),
.C_DEPTH (P_DEPTH)
)
transaction_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( r_push_r ) ,
.rd_en ( rd_en ) ,
.din ( trans_in ) ,
.dout ( trans_out ) ,
.a_full ( fifo_a_full ) ,
.full ( ) ,
.a_empty ( ) ,
.empty ( tr_empty )
);
assign fifo_full = fifo_a_full | rd_a_full ;
assign r_full = fifo_full ;
assign m_rready = ~rd_a_full;
endmodule |
module
input wire r_push ,
output wire r_full ,
// length not needed. Can be removed.
input wire [C_ID_WIDTH-1:0] r_arid ,
input wire r_rlast
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_WIDTH = 1+C_ID_WIDTH;
localparam P_DEPTH = 32;
localparam P_AWIDTH = 5;
localparam P_D_WIDTH = C_DATA_WIDTH + 2;
// rd data FIFO depth varies based on burst length.
// For Bl8 it is two times the size of transaction FIFO.
// Only in 2:1 mode BL8 transactions will happen which results in
// two beats of read data per read transaction.
localparam P_D_DEPTH = 32;
localparam P_D_AWIDTH = 5;
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
wire [C_ID_WIDTH+1-1:0] trans_in;
wire [C_ID_WIDTH+1-1:0] trans_out;
wire tr_empty;
wire rhandshake;
wire r_valid_i;
wire [P_D_WIDTH-1:0] rd_data_fifo_in;
wire [P_D_WIDTH-1:0] rd_data_fifo_out;
wire rd_en;
wire rd_full;
wire rd_empty;
wire rd_a_full;
wire fifo_a_full;
reg [C_ID_WIDTH-1:0] r_arid_r;
reg r_rlast_r;
reg r_push_r;
wire fifo_full;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
assign s_rresp = rd_data_fifo_out[P_D_WIDTH-1:C_DATA_WIDTH];
assign s_rid = trans_out[1+:C_ID_WIDTH];
assign s_rdata = rd_data_fifo_out[C_DATA_WIDTH-1:0];
assign s_rlast = trans_out[0];
assign s_rvalid = ~rd_empty & ~tr_empty;
// assign MCB outputs
assign rd_en = rhandshake & (~rd_empty);
assign rhandshake =(s_rvalid & s_rready);
// register for timing
always @(posedge clk) begin
r_arid_r <= r_arid;
r_rlast_r <= r_rlast;
r_push_r <= r_push;
end
assign trans_in[0] = r_rlast_r;
assign trans_in[1+:C_ID_WIDTH] = r_arid_r;
// rd data fifo
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_D_WIDTH),
.C_AWIDTH (P_D_AWIDTH),
.C_DEPTH (P_D_DEPTH)
)
rd_data_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( m_rvalid & m_rready ) ,
.rd_en ( rd_en ) ,
.din ( rd_data_fifo_in ) ,
.dout ( rd_data_fifo_out ) ,
.a_full ( rd_a_full ) ,
.full ( rd_full ) ,
.a_empty ( ) ,
.empty ( rd_empty )
);
assign rd_data_fifo_in = {m_rresp, m_rdata};
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_WIDTH),
.C_AWIDTH (P_AWIDTH),
.C_DEPTH (P_DEPTH)
)
transaction_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( r_push_r ) ,
.rd_en ( rd_en ) ,
.din ( trans_in ) ,
.dout ( trans_out ) ,
.a_full ( fifo_a_full ) ,
.full ( ) ,
.a_empty ( ) ,
.empty ( tr_empty )
);
assign fifo_full = fifo_a_full | rd_a_full ;
assign r_full = fifo_full ;
assign m_rready = ~rd_a_full;
endmodule |
module
input wire r_push ,
output wire r_full ,
// length not needed. Can be removed.
input wire [C_ID_WIDTH-1:0] r_arid ,
input wire r_rlast
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_WIDTH = 1+C_ID_WIDTH;
localparam P_DEPTH = 32;
localparam P_AWIDTH = 5;
localparam P_D_WIDTH = C_DATA_WIDTH + 2;
// rd data FIFO depth varies based on burst length.
// For Bl8 it is two times the size of transaction FIFO.
// Only in 2:1 mode BL8 transactions will happen which results in
// two beats of read data per read transaction.
localparam P_D_DEPTH = 32;
localparam P_D_AWIDTH = 5;
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
wire [C_ID_WIDTH+1-1:0] trans_in;
wire [C_ID_WIDTH+1-1:0] trans_out;
wire tr_empty;
wire rhandshake;
wire r_valid_i;
wire [P_D_WIDTH-1:0] rd_data_fifo_in;
wire [P_D_WIDTH-1:0] rd_data_fifo_out;
wire rd_en;
wire rd_full;
wire rd_empty;
wire rd_a_full;
wire fifo_a_full;
reg [C_ID_WIDTH-1:0] r_arid_r;
reg r_rlast_r;
reg r_push_r;
wire fifo_full;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
assign s_rresp = rd_data_fifo_out[P_D_WIDTH-1:C_DATA_WIDTH];
assign s_rid = trans_out[1+:C_ID_WIDTH];
assign s_rdata = rd_data_fifo_out[C_DATA_WIDTH-1:0];
assign s_rlast = trans_out[0];
assign s_rvalid = ~rd_empty & ~tr_empty;
// assign MCB outputs
assign rd_en = rhandshake & (~rd_empty);
assign rhandshake =(s_rvalid & s_rready);
// register for timing
always @(posedge clk) begin
r_arid_r <= r_arid;
r_rlast_r <= r_rlast;
r_push_r <= r_push;
end
assign trans_in[0] = r_rlast_r;
assign trans_in[1+:C_ID_WIDTH] = r_arid_r;
// rd data fifo
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_D_WIDTH),
.C_AWIDTH (P_D_AWIDTH),
.C_DEPTH (P_D_DEPTH)
)
rd_data_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( m_rvalid & m_rready ) ,
.rd_en ( rd_en ) ,
.din ( rd_data_fifo_in ) ,
.dout ( rd_data_fifo_out ) ,
.a_full ( rd_a_full ) ,
.full ( rd_full ) ,
.a_empty ( ) ,
.empty ( rd_empty )
);
assign rd_data_fifo_in = {m_rresp, m_rdata};
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_WIDTH),
.C_AWIDTH (P_AWIDTH),
.C_DEPTH (P_DEPTH)
)
transaction_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( r_push_r ) ,
.rd_en ( rd_en ) ,
.din ( trans_in ) ,
.dout ( trans_out ) ,
.a_full ( fifo_a_full ) ,
.full ( ) ,
.a_empty ( ) ,
.empty ( tr_empty )
);
assign fifo_full = fifo_a_full | rd_a_full ;
assign r_full = fifo_full ;
assign m_rready = ~rd_a_full;
endmodule |
module
input wire r_push ,
output wire r_full ,
// length not needed. Can be removed.
input wire [C_ID_WIDTH-1:0] r_arid ,
input wire r_rlast
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_WIDTH = 1+C_ID_WIDTH;
localparam P_DEPTH = 32;
localparam P_AWIDTH = 5;
localparam P_D_WIDTH = C_DATA_WIDTH + 2;
// rd data FIFO depth varies based on burst length.
// For Bl8 it is two times the size of transaction FIFO.
// Only in 2:1 mode BL8 transactions will happen which results in
// two beats of read data per read transaction.
localparam P_D_DEPTH = 32;
localparam P_D_AWIDTH = 5;
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
wire [C_ID_WIDTH+1-1:0] trans_in;
wire [C_ID_WIDTH+1-1:0] trans_out;
wire tr_empty;
wire rhandshake;
wire r_valid_i;
wire [P_D_WIDTH-1:0] rd_data_fifo_in;
wire [P_D_WIDTH-1:0] rd_data_fifo_out;
wire rd_en;
wire rd_full;
wire rd_empty;
wire rd_a_full;
wire fifo_a_full;
reg [C_ID_WIDTH-1:0] r_arid_r;
reg r_rlast_r;
reg r_push_r;
wire fifo_full;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
assign s_rresp = rd_data_fifo_out[P_D_WIDTH-1:C_DATA_WIDTH];
assign s_rid = trans_out[1+:C_ID_WIDTH];
assign s_rdata = rd_data_fifo_out[C_DATA_WIDTH-1:0];
assign s_rlast = trans_out[0];
assign s_rvalid = ~rd_empty & ~tr_empty;
// assign MCB outputs
assign rd_en = rhandshake & (~rd_empty);
assign rhandshake =(s_rvalid & s_rready);
// register for timing
always @(posedge clk) begin
r_arid_r <= r_arid;
r_rlast_r <= r_rlast;
r_push_r <= r_push;
end
assign trans_in[0] = r_rlast_r;
assign trans_in[1+:C_ID_WIDTH] = r_arid_r;
// rd data fifo
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_D_WIDTH),
.C_AWIDTH (P_D_AWIDTH),
.C_DEPTH (P_D_DEPTH)
)
rd_data_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( m_rvalid & m_rready ) ,
.rd_en ( rd_en ) ,
.din ( rd_data_fifo_in ) ,
.dout ( rd_data_fifo_out ) ,
.a_full ( rd_a_full ) ,
.full ( rd_full ) ,
.a_empty ( ) ,
.empty ( rd_empty )
);
assign rd_data_fifo_in = {m_rresp, m_rdata};
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_WIDTH),
.C_AWIDTH (P_AWIDTH),
.C_DEPTH (P_DEPTH)
)
transaction_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( r_push_r ) ,
.rd_en ( rd_en ) ,
.din ( trans_in ) ,
.dout ( trans_out ) ,
.a_full ( fifo_a_full ) ,
.full ( ) ,
.a_empty ( ) ,
.empty ( tr_empty )
);
assign fifo_full = fifo_a_full | rd_a_full ;
assign r_full = fifo_full ;
assign m_rready = ~rd_a_full;
endmodule |
module
input wire r_push ,
output wire r_full ,
// length not needed. Can be removed.
input wire [C_ID_WIDTH-1:0] r_arid ,
input wire r_rlast
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_WIDTH = 1+C_ID_WIDTH;
localparam P_DEPTH = 32;
localparam P_AWIDTH = 5;
localparam P_D_WIDTH = C_DATA_WIDTH + 2;
// rd data FIFO depth varies based on burst length.
// For Bl8 it is two times the size of transaction FIFO.
// Only in 2:1 mode BL8 transactions will happen which results in
// two beats of read data per read transaction.
localparam P_D_DEPTH = 32;
localparam P_D_AWIDTH = 5;
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
wire [C_ID_WIDTH+1-1:0] trans_in;
wire [C_ID_WIDTH+1-1:0] trans_out;
wire tr_empty;
wire rhandshake;
wire r_valid_i;
wire [P_D_WIDTH-1:0] rd_data_fifo_in;
wire [P_D_WIDTH-1:0] rd_data_fifo_out;
wire rd_en;
wire rd_full;
wire rd_empty;
wire rd_a_full;
wire fifo_a_full;
reg [C_ID_WIDTH-1:0] r_arid_r;
reg r_rlast_r;
reg r_push_r;
wire fifo_full;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
assign s_rresp = rd_data_fifo_out[P_D_WIDTH-1:C_DATA_WIDTH];
assign s_rid = trans_out[1+:C_ID_WIDTH];
assign s_rdata = rd_data_fifo_out[C_DATA_WIDTH-1:0];
assign s_rlast = trans_out[0];
assign s_rvalid = ~rd_empty & ~tr_empty;
// assign MCB outputs
assign rd_en = rhandshake & (~rd_empty);
assign rhandshake =(s_rvalid & s_rready);
// register for timing
always @(posedge clk) begin
r_arid_r <= r_arid;
r_rlast_r <= r_rlast;
r_push_r <= r_push;
end
assign trans_in[0] = r_rlast_r;
assign trans_in[1+:C_ID_WIDTH] = r_arid_r;
// rd data fifo
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_D_WIDTH),
.C_AWIDTH (P_D_AWIDTH),
.C_DEPTH (P_D_DEPTH)
)
rd_data_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( m_rvalid & m_rready ) ,
.rd_en ( rd_en ) ,
.din ( rd_data_fifo_in ) ,
.dout ( rd_data_fifo_out ) ,
.a_full ( rd_a_full ) ,
.full ( rd_full ) ,
.a_empty ( ) ,
.empty ( rd_empty )
);
assign rd_data_fifo_in = {m_rresp, m_rdata};
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_WIDTH),
.C_AWIDTH (P_AWIDTH),
.C_DEPTH (P_DEPTH)
)
transaction_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( r_push_r ) ,
.rd_en ( rd_en ) ,
.din ( trans_in ) ,
.dout ( trans_out ) ,
.a_full ( fifo_a_full ) ,
.full ( ) ,
.a_empty ( ) ,
.empty ( tr_empty )
);
assign fifo_full = fifo_a_full | rd_a_full ;
assign r_full = fifo_full ;
assign m_rready = ~rd_a_full;
endmodule |
module
input wire r_push ,
output wire r_full ,
// length not needed. Can be removed.
input wire [C_ID_WIDTH-1:0] r_arid ,
input wire r_rlast
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_WIDTH = 1+C_ID_WIDTH;
localparam P_DEPTH = 32;
localparam P_AWIDTH = 5;
localparam P_D_WIDTH = C_DATA_WIDTH + 2;
// rd data FIFO depth varies based on burst length.
// For Bl8 it is two times the size of transaction FIFO.
// Only in 2:1 mode BL8 transactions will happen which results in
// two beats of read data per read transaction.
localparam P_D_DEPTH = 32;
localparam P_D_AWIDTH = 5;
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
wire [C_ID_WIDTH+1-1:0] trans_in;
wire [C_ID_WIDTH+1-1:0] trans_out;
wire tr_empty;
wire rhandshake;
wire r_valid_i;
wire [P_D_WIDTH-1:0] rd_data_fifo_in;
wire [P_D_WIDTH-1:0] rd_data_fifo_out;
wire rd_en;
wire rd_full;
wire rd_empty;
wire rd_a_full;
wire fifo_a_full;
reg [C_ID_WIDTH-1:0] r_arid_r;
reg r_rlast_r;
reg r_push_r;
wire fifo_full;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
assign s_rresp = rd_data_fifo_out[P_D_WIDTH-1:C_DATA_WIDTH];
assign s_rid = trans_out[1+:C_ID_WIDTH];
assign s_rdata = rd_data_fifo_out[C_DATA_WIDTH-1:0];
assign s_rlast = trans_out[0];
assign s_rvalid = ~rd_empty & ~tr_empty;
// assign MCB outputs
assign rd_en = rhandshake & (~rd_empty);
assign rhandshake =(s_rvalid & s_rready);
// register for timing
always @(posedge clk) begin
r_arid_r <= r_arid;
r_rlast_r <= r_rlast;
r_push_r <= r_push;
end
assign trans_in[0] = r_rlast_r;
assign trans_in[1+:C_ID_WIDTH] = r_arid_r;
// rd data fifo
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_D_WIDTH),
.C_AWIDTH (P_D_AWIDTH),
.C_DEPTH (P_D_DEPTH)
)
rd_data_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( m_rvalid & m_rready ) ,
.rd_en ( rd_en ) ,
.din ( rd_data_fifo_in ) ,
.dout ( rd_data_fifo_out ) ,
.a_full ( rd_a_full ) ,
.full ( rd_full ) ,
.a_empty ( ) ,
.empty ( rd_empty )
);
assign rd_data_fifo_in = {m_rresp, m_rdata};
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_WIDTH),
.C_AWIDTH (P_AWIDTH),
.C_DEPTH (P_DEPTH)
)
transaction_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( r_push_r ) ,
.rd_en ( rd_en ) ,
.din ( trans_in ) ,
.dout ( trans_out ) ,
.a_full ( fifo_a_full ) ,
.full ( ) ,
.a_empty ( ) ,
.empty ( tr_empty )
);
assign fifo_full = fifo_a_full | rd_a_full ;
assign r_full = fifo_full ;
assign m_rready = ~rd_a_full;
endmodule |
module axi_data_fifo_v2_1_fifo_gen #(
parameter C_FAMILY = "virtex7",
parameter integer C_COMMON_CLOCK = 1,
parameter integer C_SYNCHRONIZER_STAGE = 3,
parameter integer C_FIFO_DEPTH_LOG = 5,
parameter integer C_FIFO_WIDTH = 64,
parameter C_FIFO_TYPE = "lut"
)(
clk,
rst,
wr_clk,
wr_en,
wr_ready,
wr_data,
rd_clk,
rd_en,
rd_valid,
rd_data);
input clk;
input wr_clk;
input rd_clk;
input rst;
input [C_FIFO_WIDTH-1 : 0] wr_data;
input wr_en;
input rd_en;
output [C_FIFO_WIDTH-1 : 0] rd_data;
output wr_ready;
output rd_valid;
wire full;
wire empty;
wire rd_valid = ~empty;
wire wr_ready = ~full;
localparam C_MEMORY_TYPE = (C_FIFO_TYPE == "bram")? 1 : 2;
localparam C_IMPLEMENTATION_TYPE = (C_COMMON_CLOCK == 1)? 0 : 2;
fifo_generator_v12_0 #(
.C_COMMON_CLOCK(C_COMMON_CLOCK),
.C_DIN_WIDTH(C_FIFO_WIDTH),
.C_DOUT_WIDTH(C_FIFO_WIDTH),
.C_FAMILY(C_FAMILY),
.C_IMPLEMENTATION_TYPE(C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE(C_MEMORY_TYPE),
.C_RD_DEPTH(1<<C_FIFO_DEPTH_LOG),
.C_RD_PNTR_WIDTH(C_FIFO_DEPTH_LOG),
.C_WR_DEPTH(1<<C_FIFO_DEPTH_LOG),
.C_WR_PNTR_WIDTH(C_FIFO_DEPTH_LOG),
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(2),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(6),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(31),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(30),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(6),
.C_RD_FREQ(1),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(0),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(6),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1)
)
fifo_gen_inst (
.clk(clk),
.din(wr_data),
.dout(rd_data),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_en(wr_en),
.almost_empty(),
.almost_full(),
.axi_ar_data_count(),
.axi_ar_dbiterr(),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(),
.axi_ar_prog_empty(),
.axi_ar_prog_empty_thresh(4'b0),
.axi_ar_prog_full(),
.axi_ar_prog_full_thresh(4'b0),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_underflow(),
.axi_ar_wr_data_count(),
.axi_aw_data_count(),
.axi_aw_dbiterr(),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(),
.axi_aw_prog_empty(),
.axi_aw_prog_empty_thresh(4'b0),
.axi_aw_prog_full(),
.axi_aw_prog_full_thresh(4'b0),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_underflow(),
.axi_aw_wr_data_count(),
.axi_b_data_count(),
.axi_b_dbiterr(),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(),
.axi_b_prog_empty(),
.axi_b_prog_empty_thresh(4'b0),
.axi_b_prog_full(),
.axi_b_prog_full_thresh(4'b0),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_underflow(),
.axi_b_wr_data_count(),
.axi_r_data_count(),
.axi_r_dbiterr(),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(),
.axi_r_prog_empty(),
.axi_r_prog_empty_thresh(10'b0),
.axi_r_prog_full(),
.axi_r_prog_full_thresh(10'b0),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_underflow(),
.axi_r_wr_data_count(),
.axi_w_data_count(),
.axi_w_dbiterr(),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(),
.axi_w_prog_empty(),
.axi_w_prog_empty_thresh(10'b0),
.axi_w_prog_full(),
.axi_w_prog_full_thresh(10'b0),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_underflow(),
.axi_w_wr_data_count(),
.axis_data_count(),
.axis_dbiterr(),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(),
.axis_prog_empty(),
.axis_prog_empty_thresh(10'b0),
.axis_prog_full(),
.axis_prog_full_thresh(10'b0),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_underflow(),
.axis_wr_data_count(),
.backup(1'b0),
.backup_marker(1'b0),
.data_count(),
.dbiterr(),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(),
.m_axi_arburst(),
.m_axi_arcache(),
.m_axi_arid(),
.m_axi_arlen(),
.m_axi_arlock(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arready(1'b0),
.m_axi_arregion(),
.m_axi_arsize(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_awaddr(),
.m_axi_awburst(),
.m_axi_awcache(),
.m_axi_awid(),
.m_axi_awlen(),
.m_axi_awlock(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awready(1'b0),
.m_axi_awregion(),
.m_axi_awsize(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_bid(4'b0),
.m_axi_bready(),
.m_axi_bresp(2'b0),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata(64'b0),
.m_axi_rid(4'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(),
.m_axi_rresp(2'b0),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(),
.m_axi_wid(),
.m_axi_wlast(),
.m_axi_wready(1'b0),
.m_axi_wstrb(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axis_tdata(),
.m_axis_tdest(),
.m_axis_tid(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tready(1'b0),
.m_axis_tstrb(),
.m_axis_tuser(),
.m_axis_tvalid(),
.overflow(),
.prog_empty(),
.prog_empty_thresh(5'b0),
.prog_empty_thresh_assert(5'b0),
.prog_empty_thresh_negate(5'b0),
.prog_full(),
.prog_full_thresh(5'b0),
.prog_full_thresh_assert(5'b0),
.prog_full_thresh_negate(5'b0),
.rd_data_count(),
.rd_rst(1'b0),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr(32'b0),
.s_axi_arburst(2'b0),
.s_axi_arcache(4'b0),
.s_axi_arid(4'b0),
.s_axi_arlen(8'b0),
.s_axi_arlock(2'b0),
.s_axi_arprot(3'b0),
.s_axi_arqos(4'b0),
.s_axi_arready(),
.s_axi_arregion(4'b0),
.s_axi_arsize(3'b0),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr(32'b0),
.s_axi_awburst(2'b0),
.s_axi_awcache(4'b0),
.s_axi_awid(4'b0),
.s_axi_awlen(8'b0),
.s_axi_awlock(2'b0),
.s_axi_awprot(3'b0),
.s_axi_awqos(4'b0),
.s_axi_awready(),
.s_axi_awregion(4'b0),
.s_axi_awsize(3'b0),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(),
.s_axi_bready(1'b0),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_rdata(),
.s_axi_rid(),
.s_axi_rlast(),
.s_axi_rready(1'b0),
.s_axi_rresp(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_wdata(64'b0),
.s_axi_wid(4'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(),
.s_axi_wstrb(8'b0),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata(64'b0),
.s_axis_tdest(4'b0),
.s_axis_tid(8'b0),
.s_axis_tkeep(4'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(),
.s_axis_tstrb(4'b0),
.s_axis_tuser(4'b0),
.s_axis_tvalid(1'b0),
.sbiterr(),
.srst(1'b0),
.underflow(),
.valid(),
.wr_ack(),
.wr_data_count(),
.wr_rst(1'b0),
.wr_rst_busy(),
.rd_rst_busy(),
.sleep(1'b0)
);
endmodule |
module axi_data_fifo_v2_1_fifo_gen #(
parameter C_FAMILY = "virtex7",
parameter integer C_COMMON_CLOCK = 1,
parameter integer C_SYNCHRONIZER_STAGE = 3,
parameter integer C_FIFO_DEPTH_LOG = 5,
parameter integer C_FIFO_WIDTH = 64,
parameter C_FIFO_TYPE = "lut"
)(
clk,
rst,
wr_clk,
wr_en,
wr_ready,
wr_data,
rd_clk,
rd_en,
rd_valid,
rd_data);
input clk;
input wr_clk;
input rd_clk;
input rst;
input [C_FIFO_WIDTH-1 : 0] wr_data;
input wr_en;
input rd_en;
output [C_FIFO_WIDTH-1 : 0] rd_data;
output wr_ready;
output rd_valid;
wire full;
wire empty;
wire rd_valid = ~empty;
wire wr_ready = ~full;
localparam C_MEMORY_TYPE = (C_FIFO_TYPE == "bram")? 1 : 2;
localparam C_IMPLEMENTATION_TYPE = (C_COMMON_CLOCK == 1)? 0 : 2;
fifo_generator_v12_0 #(
.C_COMMON_CLOCK(C_COMMON_CLOCK),
.C_DIN_WIDTH(C_FIFO_WIDTH),
.C_DOUT_WIDTH(C_FIFO_WIDTH),
.C_FAMILY(C_FAMILY),
.C_IMPLEMENTATION_TYPE(C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE(C_MEMORY_TYPE),
.C_RD_DEPTH(1<<C_FIFO_DEPTH_LOG),
.C_RD_PNTR_WIDTH(C_FIFO_DEPTH_LOG),
.C_WR_DEPTH(1<<C_FIFO_DEPTH_LOG),
.C_WR_PNTR_WIDTH(C_FIFO_DEPTH_LOG),
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(2),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(6),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(31),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(30),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(6),
.C_RD_FREQ(1),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(0),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(6),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1)
)
fifo_gen_inst (
.clk(clk),
.din(wr_data),
.dout(rd_data),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_en(wr_en),
.almost_empty(),
.almost_full(),
.axi_ar_data_count(),
.axi_ar_dbiterr(),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(),
.axi_ar_prog_empty(),
.axi_ar_prog_empty_thresh(4'b0),
.axi_ar_prog_full(),
.axi_ar_prog_full_thresh(4'b0),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_underflow(),
.axi_ar_wr_data_count(),
.axi_aw_data_count(),
.axi_aw_dbiterr(),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(),
.axi_aw_prog_empty(),
.axi_aw_prog_empty_thresh(4'b0),
.axi_aw_prog_full(),
.axi_aw_prog_full_thresh(4'b0),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_underflow(),
.axi_aw_wr_data_count(),
.axi_b_data_count(),
.axi_b_dbiterr(),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(),
.axi_b_prog_empty(),
.axi_b_prog_empty_thresh(4'b0),
.axi_b_prog_full(),
.axi_b_prog_full_thresh(4'b0),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_underflow(),
.axi_b_wr_data_count(),
.axi_r_data_count(),
.axi_r_dbiterr(),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(),
.axi_r_prog_empty(),
.axi_r_prog_empty_thresh(10'b0),
.axi_r_prog_full(),
.axi_r_prog_full_thresh(10'b0),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_underflow(),
.axi_r_wr_data_count(),
.axi_w_data_count(),
.axi_w_dbiterr(),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(),
.axi_w_prog_empty(),
.axi_w_prog_empty_thresh(10'b0),
.axi_w_prog_full(),
.axi_w_prog_full_thresh(10'b0),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_underflow(),
.axi_w_wr_data_count(),
.axis_data_count(),
.axis_dbiterr(),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(),
.axis_prog_empty(),
.axis_prog_empty_thresh(10'b0),
.axis_prog_full(),
.axis_prog_full_thresh(10'b0),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_underflow(),
.axis_wr_data_count(),
.backup(1'b0),
.backup_marker(1'b0),
.data_count(),
.dbiterr(),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(),
.m_axi_arburst(),
.m_axi_arcache(),
.m_axi_arid(),
.m_axi_arlen(),
.m_axi_arlock(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arready(1'b0),
.m_axi_arregion(),
.m_axi_arsize(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_awaddr(),
.m_axi_awburst(),
.m_axi_awcache(),
.m_axi_awid(),
.m_axi_awlen(),
.m_axi_awlock(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awready(1'b0),
.m_axi_awregion(),
.m_axi_awsize(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_bid(4'b0),
.m_axi_bready(),
.m_axi_bresp(2'b0),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata(64'b0),
.m_axi_rid(4'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(),
.m_axi_rresp(2'b0),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(),
.m_axi_wid(),
.m_axi_wlast(),
.m_axi_wready(1'b0),
.m_axi_wstrb(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axis_tdata(),
.m_axis_tdest(),
.m_axis_tid(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tready(1'b0),
.m_axis_tstrb(),
.m_axis_tuser(),
.m_axis_tvalid(),
.overflow(),
.prog_empty(),
.prog_empty_thresh(5'b0),
.prog_empty_thresh_assert(5'b0),
.prog_empty_thresh_negate(5'b0),
.prog_full(),
.prog_full_thresh(5'b0),
.prog_full_thresh_assert(5'b0),
.prog_full_thresh_negate(5'b0),
.rd_data_count(),
.rd_rst(1'b0),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr(32'b0),
.s_axi_arburst(2'b0),
.s_axi_arcache(4'b0),
.s_axi_arid(4'b0),
.s_axi_arlen(8'b0),
.s_axi_arlock(2'b0),
.s_axi_arprot(3'b0),
.s_axi_arqos(4'b0),
.s_axi_arready(),
.s_axi_arregion(4'b0),
.s_axi_arsize(3'b0),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr(32'b0),
.s_axi_awburst(2'b0),
.s_axi_awcache(4'b0),
.s_axi_awid(4'b0),
.s_axi_awlen(8'b0),
.s_axi_awlock(2'b0),
.s_axi_awprot(3'b0),
.s_axi_awqos(4'b0),
.s_axi_awready(),
.s_axi_awregion(4'b0),
.s_axi_awsize(3'b0),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(),
.s_axi_bready(1'b0),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_rdata(),
.s_axi_rid(),
.s_axi_rlast(),
.s_axi_rready(1'b0),
.s_axi_rresp(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_wdata(64'b0),
.s_axi_wid(4'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(),
.s_axi_wstrb(8'b0),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata(64'b0),
.s_axis_tdest(4'b0),
.s_axis_tid(8'b0),
.s_axis_tkeep(4'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(),
.s_axis_tstrb(4'b0),
.s_axis_tuser(4'b0),
.s_axis_tvalid(1'b0),
.sbiterr(),
.srst(1'b0),
.underflow(),
.valid(),
.wr_ack(),
.wr_data_count(),
.wr_rst(1'b0),
.wr_rst_busy(),
.rd_rst_busy(),
.sleep(1'b0)
);
endmodule |
module axi_protocol_converter_v2_1_b2s_b_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk,
input wire reset,
// AXI signals
output wire [C_ID_WIDTH-1:0] s_bid,
output wire [1:0] s_bresp,
output wire s_bvalid,
input wire s_bready,
input wire [1:0] m_bresp,
input wire m_bvalid,
output wire m_bready,
// Signals to/from the axi_protocol_converter_v2_1_b2s_aw_channel modules
input wire b_push,
input wire [C_ID_WIDTH-1:0] b_awid,
input wire [7:0] b_awlen,
input wire b_resp_rdy,
output wire b_full
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// AXI protocol responses:
localparam [1:0] LP_RESP_OKAY = 2'b00;
localparam [1:0] LP_RESP_EXOKAY = 2'b01;
localparam [1:0] LP_RESP_SLVERROR = 2'b10;
localparam [1:0] LP_RESP_DECERR = 2'b11;
// FIFO settings
localparam P_WIDTH = C_ID_WIDTH + 8;
localparam P_DEPTH = 4;
localparam P_AWIDTH = 2;
localparam P_RWIDTH = 2;
localparam P_RDEPTH = 4;
localparam P_RAWIDTH = 2;
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
reg bvalid_i;
wire [C_ID_WIDTH-1:0] bid_i;
wire shandshake;
reg shandshake_r;
wire mhandshake;
reg mhandshake_r;
wire b_empty;
wire bresp_full;
wire bresp_empty;
wire [7:0] b_awlen_i;
reg [7:0] bresp_cnt;
reg [1:0] s_bresp_acc;
wire [1:0] s_bresp_acc_r;
reg [1:0] s_bresp_i;
wire need_to_update_bresp;
wire bresp_push;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// assign AXI outputs
assign s_bid = bid_i;
assign s_bresp = s_bresp_acc_r;
assign s_bvalid = bvalid_i;
assign shandshake = s_bvalid & s_bready;
assign mhandshake = m_bvalid & m_bready;
always @(posedge clk) begin
if (reset | shandshake) begin
bvalid_i <= 1'b0;
end else if (~b_empty & ~shandshake_r & ~bresp_empty) begin
bvalid_i <= 1'b1;
end
end
always @(posedge clk) begin
shandshake_r <= shandshake;
mhandshake_r <= mhandshake;
end
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_WIDTH),
.C_AWIDTH (P_AWIDTH),
.C_DEPTH (P_DEPTH)
)
bid_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( b_push ) ,
.rd_en ( shandshake_r ) ,
.din ( {b_awid, b_awlen} ) ,
.dout ( {bid_i, b_awlen_i}) ,
.a_full ( ) ,
.full ( b_full ) ,
.a_empty ( ) ,
.empty ( b_empty )
);
assign m_bready = ~mhandshake_r & bresp_empty;
/////////////////////////////////////////////////////////////////////////////
// Update if more critical.
assign need_to_update_bresp = ( m_bresp > s_bresp_acc );
// Select accumultated or direct depending on setting.
always @( * ) begin
if ( need_to_update_bresp ) begin
s_bresp_i = m_bresp;
end else begin
s_bresp_i = s_bresp_acc;
end
end
/////////////////////////////////////////////////////////////////////////////
// Accumulate MI-side BRESP.
always @ (posedge clk) begin
if (reset | bresp_push ) begin
s_bresp_acc <= LP_RESP_OKAY;
end else if ( mhandshake ) begin
s_bresp_acc <= s_bresp_i;
end
end
assign bresp_push = ( mhandshake_r ) & (bresp_cnt == b_awlen_i) & ~b_empty;
always @ (posedge clk) begin
if (reset | bresp_push ) begin
bresp_cnt <= 8'h00;
end else if ( mhandshake_r ) begin
bresp_cnt <= bresp_cnt + 1'b1;
end
end
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_RWIDTH),
.C_AWIDTH (P_RAWIDTH),
.C_DEPTH (P_RDEPTH)
)
bresp_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( bresp_push ) ,
.rd_en ( shandshake_r ) ,
.din ( s_bresp_acc ) ,
.dout ( s_bresp_acc_r) ,
.a_full ( ) ,
.full ( bresp_full ) ,
.a_empty ( ) ,
.empty ( bresp_empty )
);
endmodule |
module axi_protocol_converter_v2_1_b2s_b_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk,
input wire reset,
// AXI signals
output wire [C_ID_WIDTH-1:0] s_bid,
output wire [1:0] s_bresp,
output wire s_bvalid,
input wire s_bready,
input wire [1:0] m_bresp,
input wire m_bvalid,
output wire m_bready,
// Signals to/from the axi_protocol_converter_v2_1_b2s_aw_channel modules
input wire b_push,
input wire [C_ID_WIDTH-1:0] b_awid,
input wire [7:0] b_awlen,
input wire b_resp_rdy,
output wire b_full
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// AXI protocol responses:
localparam [1:0] LP_RESP_OKAY = 2'b00;
localparam [1:0] LP_RESP_EXOKAY = 2'b01;
localparam [1:0] LP_RESP_SLVERROR = 2'b10;
localparam [1:0] LP_RESP_DECERR = 2'b11;
// FIFO settings
localparam P_WIDTH = C_ID_WIDTH + 8;
localparam P_DEPTH = 4;
localparam P_AWIDTH = 2;
localparam P_RWIDTH = 2;
localparam P_RDEPTH = 4;
localparam P_RAWIDTH = 2;
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
reg bvalid_i;
wire [C_ID_WIDTH-1:0] bid_i;
wire shandshake;
reg shandshake_r;
wire mhandshake;
reg mhandshake_r;
wire b_empty;
wire bresp_full;
wire bresp_empty;
wire [7:0] b_awlen_i;
reg [7:0] bresp_cnt;
reg [1:0] s_bresp_acc;
wire [1:0] s_bresp_acc_r;
reg [1:0] s_bresp_i;
wire need_to_update_bresp;
wire bresp_push;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// assign AXI outputs
assign s_bid = bid_i;
assign s_bresp = s_bresp_acc_r;
assign s_bvalid = bvalid_i;
assign shandshake = s_bvalid & s_bready;
assign mhandshake = m_bvalid & m_bready;
always @(posedge clk) begin
if (reset | shandshake) begin
bvalid_i <= 1'b0;
end else if (~b_empty & ~shandshake_r & ~bresp_empty) begin
bvalid_i <= 1'b1;
end
end
always @(posedge clk) begin
shandshake_r <= shandshake;
mhandshake_r <= mhandshake;
end
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_WIDTH),
.C_AWIDTH (P_AWIDTH),
.C_DEPTH (P_DEPTH)
)
bid_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( b_push ) ,
.rd_en ( shandshake_r ) ,
.din ( {b_awid, b_awlen} ) ,
.dout ( {bid_i, b_awlen_i}) ,
.a_full ( ) ,
.full ( b_full ) ,
.a_empty ( ) ,
.empty ( b_empty )
);
assign m_bready = ~mhandshake_r & bresp_empty;
/////////////////////////////////////////////////////////////////////////////
// Update if more critical.
assign need_to_update_bresp = ( m_bresp > s_bresp_acc );
// Select accumultated or direct depending on setting.
always @( * ) begin
if ( need_to_update_bresp ) begin
s_bresp_i = m_bresp;
end else begin
s_bresp_i = s_bresp_acc;
end
end
/////////////////////////////////////////////////////////////////////////////
// Accumulate MI-side BRESP.
always @ (posedge clk) begin
if (reset | bresp_push ) begin
s_bresp_acc <= LP_RESP_OKAY;
end else if ( mhandshake ) begin
s_bresp_acc <= s_bresp_i;
end
end
assign bresp_push = ( mhandshake_r ) & (bresp_cnt == b_awlen_i) & ~b_empty;
always @ (posedge clk) begin
if (reset | bresp_push ) begin
bresp_cnt <= 8'h00;
end else if ( mhandshake_r ) begin
bresp_cnt <= bresp_cnt + 1'b1;
end
end
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_RWIDTH),
.C_AWIDTH (P_RAWIDTH),
.C_DEPTH (P_RDEPTH)
)
bresp_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( bresp_push ) ,
.rd_en ( shandshake_r ) ,
.din ( s_bresp_acc ) ,
.dout ( s_bresp_acc_r) ,
.a_full ( ) ,
.full ( bresp_full ) ,
.a_empty ( ) ,
.empty ( bresp_empty )
);
endmodule |
module axi_protocol_converter_v2_1_b2s_b_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk,
input wire reset,
// AXI signals
output wire [C_ID_WIDTH-1:0] s_bid,
output wire [1:0] s_bresp,
output wire s_bvalid,
input wire s_bready,
input wire [1:0] m_bresp,
input wire m_bvalid,
output wire m_bready,
// Signals to/from the axi_protocol_converter_v2_1_b2s_aw_channel modules
input wire b_push,
input wire [C_ID_WIDTH-1:0] b_awid,
input wire [7:0] b_awlen,
input wire b_resp_rdy,
output wire b_full
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// AXI protocol responses:
localparam [1:0] LP_RESP_OKAY = 2'b00;
localparam [1:0] LP_RESP_EXOKAY = 2'b01;
localparam [1:0] LP_RESP_SLVERROR = 2'b10;
localparam [1:0] LP_RESP_DECERR = 2'b11;
// FIFO settings
localparam P_WIDTH = C_ID_WIDTH + 8;
localparam P_DEPTH = 4;
localparam P_AWIDTH = 2;
localparam P_RWIDTH = 2;
localparam P_RDEPTH = 4;
localparam P_RAWIDTH = 2;
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
reg bvalid_i;
wire [C_ID_WIDTH-1:0] bid_i;
wire shandshake;
reg shandshake_r;
wire mhandshake;
reg mhandshake_r;
wire b_empty;
wire bresp_full;
wire bresp_empty;
wire [7:0] b_awlen_i;
reg [7:0] bresp_cnt;
reg [1:0] s_bresp_acc;
wire [1:0] s_bresp_acc_r;
reg [1:0] s_bresp_i;
wire need_to_update_bresp;
wire bresp_push;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// assign AXI outputs
assign s_bid = bid_i;
assign s_bresp = s_bresp_acc_r;
assign s_bvalid = bvalid_i;
assign shandshake = s_bvalid & s_bready;
assign mhandshake = m_bvalid & m_bready;
always @(posedge clk) begin
if (reset | shandshake) begin
bvalid_i <= 1'b0;
end else if (~b_empty & ~shandshake_r & ~bresp_empty) begin
bvalid_i <= 1'b1;
end
end
always @(posedge clk) begin
shandshake_r <= shandshake;
mhandshake_r <= mhandshake;
end
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_WIDTH),
.C_AWIDTH (P_AWIDTH),
.C_DEPTH (P_DEPTH)
)
bid_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( b_push ) ,
.rd_en ( shandshake_r ) ,
.din ( {b_awid, b_awlen} ) ,
.dout ( {bid_i, b_awlen_i}) ,
.a_full ( ) ,
.full ( b_full ) ,
.a_empty ( ) ,
.empty ( b_empty )
);
assign m_bready = ~mhandshake_r & bresp_empty;
/////////////////////////////////////////////////////////////////////////////
// Update if more critical.
assign need_to_update_bresp = ( m_bresp > s_bresp_acc );
// Select accumultated or direct depending on setting.
always @( * ) begin
if ( need_to_update_bresp ) begin
s_bresp_i = m_bresp;
end else begin
s_bresp_i = s_bresp_acc;
end
end
/////////////////////////////////////////////////////////////////////////////
// Accumulate MI-side BRESP.
always @ (posedge clk) begin
if (reset | bresp_push ) begin
s_bresp_acc <= LP_RESP_OKAY;
end else if ( mhandshake ) begin
s_bresp_acc <= s_bresp_i;
end
end
assign bresp_push = ( mhandshake_r ) & (bresp_cnt == b_awlen_i) & ~b_empty;
always @ (posedge clk) begin
if (reset | bresp_push ) begin
bresp_cnt <= 8'h00;
end else if ( mhandshake_r ) begin
bresp_cnt <= bresp_cnt + 1'b1;
end
end
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_RWIDTH),
.C_AWIDTH (P_RAWIDTH),
.C_DEPTH (P_RDEPTH)
)
bresp_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( bresp_push ) ,
.rd_en ( shandshake_r ) ,
.din ( s_bresp_acc ) ,
.dout ( s_bresp_acc_r) ,
.a_full ( ) ,
.full ( bresp_full ) ,
.a_empty ( ) ,
.empty ( bresp_empty )
);
endmodule |