rtl-llm
/

qwen2.5coder-7b-origen-verilog-vhdl-vhdl-truncate

Text Generation

text-generation-inference

Model card Files Files and versions Community

qwen2.5coder-7b-origen-verilog-vhdl-vhdl-truncate

Ctrl+K

Ctrl+K

1 contributor

History: 1 commit

charleshong3's picture

initial commit

8047c7f verified 27 days ago

.gitattributes

1.52 kB

initial commit 27 days ago