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shailja
/
fine-tuned-codegen-16B-Verilog
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15
Text Generation
Transformers
PyTorch
shailja/Verilog_GitHub
codegen
code
Eval Results
arxiv:
2212.11140
License:
bigcode-openrail-m
Model card
Files
Files and versions
xet
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3
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c3b0acc
fine-tuned-codegen-16B-Verilog
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2 contributors
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1 commit
shailja
initial commit
c3b0acc
over 2 years ago
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over 2 years ago
README.md
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initial commit
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