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Ticket Name: How to configure Ethernet MAC interface to MII mode of Ethernet in Vision SDK for Tda2x?
Query Text:
Other Parts Discussed in Thread: DP83865, DP83848Q-Q1, TDA2 Hi, For Tda2x EVM, it used Gig Phyter (DP83865 Gig PHYTER V10/100/1000 Ethernet Physical Layer) and Vision SDK was set to RGMII mode for Ethernet. Our EVM use Mig Phyter (DP83848Q-Q1 PHYTERTM Extended-Temperature, Single-Port 10/100-Mbps Ethernet Physical Layer Transceiver) for Ethernet. So I must configure Ethernet MAC interface to MII mode in Vision SDK. I list my modification as follow: 1. according to HW schematics, I modified some pin mux setting in file VISION_SDK_02_10_00_00/ti_components/drivers/starterware_01_06_00_16/bootloader/sbl_utils/src/sbl_utils_tda2xx.c Phy Pin name ball Pad Name Offset Register Value MDC EPHY_MDC O D3 VIN2A_D10 0x190 0x4000F MDIO EPHY_MDIO I/O F6 VIN2A_D11 0x194 0x4000F RXD_1 EPHY_RXD I V6 RGMII0_TXD1 0x260 0x40003 RXD_2 EPHY_RXD I V9 RGMII0_TXCTL 0x254 0x40003 RXD_3 EPHY_RXD I W9 RGMII0_TXC 0x250 0x40003 RXD_0 EPHY_RXD I U6 RGMII0_TXD0 0x264 0x40003 RX_CLK EPHY_RXC I Y1 UART3_TXD 0x24C 0xE0003 RX_DV EPHY_RXDV I V2 UART3_RXD 0x248 0xC0003 TX_CLK EPHY_TXC I U5 RGMII0_RXC 0x268 0x60003 TXD_0 EPHY_TXD O W2 RGMII0_RXD0 0x27C 0x10003 TXD_1 EPHY_TXD O Y2 RGMII0_RXD1 0x278 0x10003 TXD_2 EPHY_TXD O V4 RGMII0_RXD3 0x270 0x10003 TXD_3 EPHY_TXD O V5 RGMII0_RXCTL 0x26C 0x10003 TX_ER EPHY_TXER I U4 MDIO_D 0x240 0x90003 RX_ER EPHY_RXER I U7 RGMII0_TXD2 0x25C 0x40003 COL EPHY_COL I V1 MDIO_MCLK 0x23C 0xC0003 CRS EPHY_CRS I V7 RGMII0_TXD3 0x258 0x40003 TX_EN EPHY_TXEN O V3 RGMII0_RXD2 0x274 0x10003 2. Remove this function. If not, system will restore to RGMII configure after booting. VISION_SDK_02_10_00_00/ti_components/drivers/starterware_01_06_00_16/platform/platform_tda2xx_pad_config.c void PlatformRGMIISetPinMux(void) { // PlatformRGMII0SetPinMux(); } After Booting, system still can't get IP from DHCP server. Are there any settings I need to do more?
Responses:
Hi, Any update? 3. I also set (#define PAB_MII (1)) in VISION_SDK_02_10_00_00/vision_sdk/src/utils_common/src/ndk/ndk_nsp_hooks.c But EVM still can't get IP.
Hi Eric, Vision SDK team has been notified to comment. Best regards Lucy
Hello Eric, PAD configuration looks correct for MII mode, where do you calling PAD config function in VSDK? Also when you run application, do you see Link up and speed message on console? I would suggest to use standalone NSP application to get PHY up in MII mode as it would be simpler. You can gel files to configure PAD and run NSP test from CCS. Regards, Prasad
PAD configuration function was setted in Line:557 and was called in SblUtilsConfigPadMux functino of the file VISION_SDK_02_10_00_00/ti_components/drivers/starterware_01_06_00_16/bootloader/sbl_utils/src/sbl_utils_tda2xx.c I set boot mode to sd card, so it was ran in MLO file. Is the standalone NSP application "VISION_SDK_02_10_00_00/ti_components/networking/nsp_gmacsw_4_14_00_00/packages/ti/ndk/vayu/examples_ipu1/helloWorld"??
Hello Eric, In addition to PAD configuration SBL also configures IO delay for RGMII PADS. These delay setting are not correct for MII mode. Also this delay configuration code will set PAD mux back to RGMII. If you have debug access through CCS, you can check values of PAD registers if they are correctly configured. Running standalone test would remove dependency on SBL. You can run either helloWorld or client app though client is recommended. You can refer to NSP user guide for building & running this app in the CCS. Just make sure you modify gel files to run TDA2xx_PAD_PAB_MII_Config function instead of TDA2xx_PAD_EVM_RGMII_Config. Please cross check the values configured in the TDA2xx_PAD_PAB_MII_Config function are as per your board layout. Please share your application log once you run it. Regards, Prasad
Hi Prasad, I followed NSP user guide for importing client app to CCS: Step1: Copy nsp_gmacsw_4_14_00_00 folder from VISION_SDK_02_10_00_00 to workspace_v5_4 folder. Step2: Import Existing CCS Eclipse Project. Detail Step: Open CCSv5 and create a new workspace. From within the C/C++ View, select the menu option "Project -> Import Existing CCS/CCE Eclipse Project" In the window that appears, click "Select Archive File", then click the "browse" button. Navigate to the location where you installed the nsp_gmacsw_4_14_00_00 package. If you installed the NSP into C:\ti, then navigate to: C:\ti\nsp_gmacsw_4_14_00_00\packages\ti\ndk\vayu\examples Once in the examples directory, you will see the example directories for MPU & IPU1: Choose the desired directory and click open Under "Discovered Projects" you should see the examples listed. Click "Finish" to import the examples. You may now build the NDK examples within CCSv5 ------------ But I get this error message: See details below. Error: Import failed for project 'client' because its meta-data cannot be interpreted. Please contact support. ------------ I ever tried to install different versions of CCS (CCS5.4.0.00091_linux, CCS5.5.0.00077_linux and CCS6.1.3.00034_linux) and switch to different workspaces (workspace_v5_4, workspace_v5_5 and workspace_v6_1, refer to e2e Forum: delete ".metadata" folder), but the result is the same. Any idea?
Eric, You should use CCSv6 as these applications are not compatible with older CCSv5. You should not see this issue on CCSv6. Below are modified steps Open CCSv6 and create a new workspace. Select View -> Project explorer. In project explorer, right click and select the menu option "Import-> CCS projects" In the window that appears, click "Select Search Directory", then click the "browse" button. Navigate to the location where you installed the nsp_gmacsw_4_14_00_00 package. If you installed the NSP into C:\ti, then navigate to: C:\ti\nsp_gmacsw_4_14_00_00\packages\ti\ndk\vayu\examples Once in the examples directory, you will see the example directories for MPU & IPU1: Choose the desired directory and click open Under "Discovered Projects" you should see the examples listed. Click "Finish" to import the examples. Sorry for user-guide issue. I will update it.
Hi Prasad, After fixed some compiling issues(XDCTools, uia, SYS/BIOS packages), I can compile and execute "client" application in (VISION_SDK_02_10_00_00/ti_components/networking/nsp_gmacsw_4_14_00_00/packages/ti/ndk/vayu/examples_ipu1/client). At first, I try to run "client" application on Ti EVM for RGMII mode. It can get IP address from DHCP server. Log as follow: ------------------------------------------------------------------------------------------ [Cortex_M4_IPU1_C0] MAC Port 0 Address: d4-f5-13-b4-62-90 MAC Port 1 Address: d4-f5-13-b4-62-91 GMACSW has been started successfully Registration of the GMACSW Successful Service Status: DHCPC : Enabled : : 000 Service Status: Telnet : Enabled : : 000 Service Status: HTTP : Enabled : : 000 Service Status: HTTP : Enabled : : 000 Service Status: DHCPC : Enabled : Running : 000 PHY: 2, NegMode 01E1, NWAYadvertise 01E1, NWAYREadvertise 43E1 Negotiated connection: FullDuplex 100 Mbs Link Status: 100Mb/s Full Duplex on PHY 2 Network Added: If-1:192.168.213.7 Service Status: DHCPC : Enabled : Running : 017 ------------------------------------------------------------------------------------------ Then, for my board, log as follow: ------------------------------------------------------------------------------------------ [Cortex_M4_IPU1_C0] MAC Port 0 Address: d0-b5-c2-5b-42-ee MAC Port 1 Address: d0-b5-c2-5b-42-ef GMACSW has been started successfully Registration of the GMACSW Successful Service Status: DHCPC : Enabled : : 000 Service Status: Telnet : Enabled : : 000 Service Status: HTTP : Enabled : : 000 Service Status: HTTP : Enabled : : 000 Service Status: DHCPC : Enabled : Running : 000 <- hang on this ------------------------------------------------------------------------------------------ I list my modification for some code slice and gel file for compiling "client" application. 1. For running MII mode configuration. Line 48, 65 : TDA2xx_PAD_PAB_MII_Config.gel 2. For MDIO_MCLK and MDIO_D Line 3445~3460:TDA2xx_pad_config.gel 3. For I/O delay: vayu_init.c Line 72: #define PAB_MII (1) Line 101~106, 121~126: for I/O delay register. Line 353~418 of vayu_init function: for delay value. I am not sure these delay values are correct or not. Can you help me to check these modifications? I attach all files I described: TDA2xx_startup_common.gel TDA2xx_pad_config.gel NSPLog.txt ---------------------------------------------------------------------------------Ti EVM
Log:
[Cortex_M4_IPU1_C0]
MAC Port 0 Address:
d4-f5-13-b4-62-90
MAC Port 1 Address:
d4-f5-13-b4-62-91
GMACSW has been started successfully
Registration of the GMACSW Successful
Service Status: DHCPC : Enabled : : 000
Service Status: Telnet : Enabled : : 000
Service Status: HTTP : Enabled : : 000
Service Status: HTTP : Enabled : : 000
Service Status: DHCPC : Enabled : Running : 000
PHY: 2, NegMode 01E1, NWAYadvertise 01E1, NWAYREadvertise 43E1
Negotiated connection: FullDuplex 100 Mbs
Link Status: 100Mb/s Full Duplex on PHY 2
Network Added: If-1:192.168.213.7
Service Status: DHCPC : Enabled : Running : 017
---------------------------------------------------------------------------------Eric EVM: MII mode for dp83848q Phy
[Cortex_M4_IPU1_C0]
MAC Port 0 Address:
d0-b5-c2-5b-42-ee
MAC Port 1 Address:
d0-b5-c2-5b-42-ef
GMACSW has been started successfully
Registration of the GMACSW Successful
Service Status: DHCPC : Enabled : : 000
Service Status: Telnet : Enabled : : 000
Service Status: HTTP : Enabled : : 000
Service Status: HTTP : Enabled : : 000
Service Status: DHCPC : Enabled : Running : 000
---------------------------------------------------------------------------------Eric EVM: CCS Log for running gel file
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA2xx Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA2xx Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> TDA2xx Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> TDA2xx Cortex M4 Startup Sequence DONE! <<<---
C66xx_DSP1: GEL Output: --->>> TDA2xx C66x DSP Startup Sequence In Progress... <<<---
C66xx_DSP1: GEL Output: --->>> TDA2xx C66x DSP Startup Sequence DONE! <<<---
C66xx_DSP2: GEL Output: --->>> TDA2xx C66x DSP Startup Sequence In Progress... <<<---
C66xx_DSP2: GEL Output: --->>> TDA2xx C66x DSP Startup Sequence DONE! <<<---
CortexA15_0: GEL Output: --->>> TDA2xx Cortex A15 Startup Sequence In Progress... <<<---
CortexA15_0: GEL Output: --->>> TDA2xx Cortex A15 Startup Sequence DONE! <<<---
ARP32_EVE_1: GEL Output: --->>> Configuring EVE Memory Map <<<---
ARP32_EVE_1: GEL Output: --->>> EVE Memory Map Done! <<<---
ARP32_EVE_2: GEL Output: --->>> Configuring EVE Memory Map <<<---
ARP32_EVE_2: GEL Output: --->>> EVE Memory Map Done! <<<---
ARP32_EVE_3: GEL Output: --->>> Configuring EVE Memory Map <<<---
ARP32_EVE_3: GEL Output: --->>> EVE Memory Map Done! <<<---
ARP32_EVE_4: GEL Output: --->>> Configuring EVE Memory Map <<<---
ARP32_EVE_4: GEL Output: --->>> EVE Memory Map Done! <<<---
IcePick_D: GEL Output: Ipu RTOS is released from Wait-In-Reset.
IcePick_D: GEL Output: Ipu SIMCOP is released from Wait-In-Reset.
IcePick_D: GEL Output: IVAHD C66 is released from Wait-In-Reset.
IcePick_D: GEL Output: IVAHD ICONT1 is released from Wait-In-Reset.
IcePick_D: GEL Output: IVAHD ICONT2 is released from Wait-In-Reset.
CS_DAP_DebugSS: GEL Output: --->>> CONFIGURE DEBUG DPLL settings to 1.9 GHZs <<<---
CS_DAP_DebugSS: GEL Output: > Setup DebugSS 1.9GHz in progress...
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS PLL Clocking 1.9GHz
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS ATB Clocking 380MHz
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz
CS_DAP_DebugSS: GEL Output: --->>> TURNING ON L3_INSTR and L3_3 clocks required for debug instrumention <<<<<<----
CS_DAP_DebugSS: GEL Output: ---<<< L3 instrumentation clocks are enabled >>>> ---
CS_DAP_DebugSS: GEL Output: --->>> Mapping TIMER supsend sources to default cores <<<<<<----
CS_DAP_PC: GEL Output: Cortex-A15 1 is not in WIR mode so nothing to do.
CortexA15_0: GEL Output: --->>> TDA2xx Target Connect Sequence Begins ... <<<---
CortexA15_0: GEL Output: --->>> TDA2xx PG1.0 GP device <<<---
CortexA15_0: GEL Output: --->>> The core is in non-SECURE state. <<<---
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<---
CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: Cortex A15 DPLL is already locked, now unlocking...
CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: IVA DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: IVA DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: PER DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: PER DPLL already locked, now unlocking
CortexA15_0: GEL Output: PER DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: CORE DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: CORE DPLL OPP already locked, now unlocking....
CortexA15_0: GEL Output: CORE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: ABE DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: ABE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: GMAC DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: GMAC DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: GPU DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: GPU DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: DSP DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: DSP DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: EVE DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: EVE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<---
CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in progress...
CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in DONE!
CortexA15_0: GEL Output: Launch full leveling
CortexA15_0: GEL Output: Updating slave ratios in PHY_STATUSx registers
CortexA15_0: GEL Output: as per HW leveling output
CortexA15_0: GEL Output: HW leveling is now disabled. Using slave ratios from
CortexA15_0: GEL Output: PHY_STATUSx registers
CortexA15_0: GEL Output: Launch full leveling
CortexA15_0: GEL Output: Updating slave ratios in PHY_STATUSx registers
CortexA15_0: GEL Output: as per HW leveling output
CortexA15_0: GEL Output: HW leveling is now disabled. Using slave ratios from
CortexA15_0: GEL Output: PHY_STATUSx registers
CortexA15_0: GEL Output: One EMIF - 512MB total memory
CortexA15_0: GEL Output: Same memory mapped at 0x80000000 and 0xA0000000
CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> TDA2xx Begin All Pad Configuration for PAB MII Usage <<<---
CortexA15_0: GEL Output: --->>> TDA2xx Begin GMAC_SW MDIO Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> TDA2xx End GMAC_SW MDIO Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> TDA2xx Begin GMAC_SW MII0 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> TDA2xx End GMAC_SW MII0 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> TDA2xx Begin GMAC_SW MII1 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> TDA2xx End GMAC_SW MII1 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> TDA2xx End All Pad Configuration for PAB MII Usage <<<---
CortexA15_0: GEL Output: --->>> TDA2xx Target Connect Sequence DONE !!!!! <<<---
Cortex_M4_IPU1_C0: Error connecting to the target: (Error -1266 @ 0x0) Device is held in reset. Take the device out of reset, and retry the operation. (Emulation package 6.0.407.3)
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ...
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ...
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful!
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ...
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ...
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful!
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> EVE1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ...
CortexA15_0: GEL Output: DEBUG: Resetting EVE MMU ...
CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 1: 0x00000000 --> 0x80000000
CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 2: 0x80000000 --> 0x80000000
CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 3: 0x40000000 --> 0x40000000
CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 4: 0x48000000 --> 0x48000000
CortexA15_0: GEL Output: DEBUG: EVE0 MMU0 configured as per VisionSDK requirements!!!!
CortexA15_0: GEL Output: --->>> EVE1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> EVE2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ...
CortexA15_0: GEL Output: DEBUG: Resetting EVE MMU ...
CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 1: 0x00000000 --> 0x81000000
CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 2: 0x81000000 --> 0x81000000
CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 3: 0x40000000 --> 0x40000000
CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 4: 0x48000000 --> 0x48000000
CortexA15_0: GEL Output: DEBUG: EVE0 MMU0 configured as per VisionSDK requirements!!!!
CortexA15_0: GEL Output: --->>> EVE2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> EVE3SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ...
CortexA15_0: GEL Output: DEBUG: Resetting EVE MMU ...
CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 1: 0x00000000 --> 0x82000000
CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 2: 0x82000000 --> 0x82000000
CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 3: 0x40000000 --> 0x40000000
CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 4: 0x48000000 --> 0x48000000
CortexA15_0: GEL Output: DEBUG: EVE0 MMU0 configured as per VisionSDK requirements!!!!
CortexA15_0: GEL Output: --->>> EVE3SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> EVE4SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ...
CortexA15_0: GEL Output: DEBUG: Resetting EVE MMU ...
CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 1: 0x00000000 --> 0x83000000
CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 2: 0x83000000 --> 0x83000000
CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 3: 0x40000000 --> 0x40000000
CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 4: 0x48000000 --> 0x48000000
CortexA15_0: GEL Output: DEBUG: EVE0 MMU0 configured as per VisionSDK requirements!!!!
CortexA15_0: GEL Output: --->>> EVE4SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ...
CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---
vayu_init.c /*
* Copyright (C) 2013, Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file vayu_init.c
*
* @brief
* Do all necessary board level initialization for NDK example.
*
*/
/*---------------------------------------------------------------------------*\
| Header Files |
\*---------------------------------------------------------------------------*/
/* Standard language headers */
#include <stddef.h>
#include <stdio.h>
#include <inttypes.h>
#include <string.h>
/* OS/Posix headers */
/* NDK Dependencies */
#include <ti/ndk/inc/netmain.h>
/* NSP Dependencies */
#include <ti/nsp/drv/inc/gmacsw_config.h>
/* Project dependency headers */
/*---------------------------------------------------------------------------*\
| Extern Declarations |
\*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*\
| Local Macros/Defines |
\*---------------------------------------------------------------------------*/
#define PAB_MII (1) /* Eric: Modify for MII mode: #define PAB_MII (0) */
#define PAB_RMII (0)
/* Ethernet MAC ID registers(Devcice configuration) from EFuse */
#define MAC_ID0_LO (*(volatile uint32_t*)0x4A002514)
#define MAC_ID0_HI (*(volatile uint32_t*)0x4A002518)
#define MAC_ID1_LO (*(volatile uint32_t*)0x4A00251C)
#define MAC_ID1_HI (*(volatile uint32_t*)0x4A002520)
/* I/O Delay related registers */
#define CFG_IO_DELAY_UNLOCK_KEY (0x0000AAAA)
#define CFG_IO_DELAY_LOCK_KEY (0x0000AAAB)
#define CFG_IO_DELAY_ACCESS_PATTERN (0x00029000)
#define CFG_IO_DELAY_LOCK_MASK (0x400)
#define CFG_IO_DELAY_BASE (0x4844A000)
#define CFG_IO_DELAY_LOCK (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0x02C))
#define CFG_RGMII0_TXCTL_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0x74C))
#define CFG_RGMII0_TXD0_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0x758))
#define CFG_RGMII0_TXD1_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0x764))
#define CFG_RGMII0_TXD2_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0x770))
#define CFG_RGMII0_TXD3_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0x77C))
#define CFG_VIN2A_D13_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0xA7C))
#define CFG_VIN2A_D17_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0xAAC))
#define CFG_VIN2A_D16_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0xAA0))
#define CFG_VIN2A_D15_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0xA94))
#define CFG_VIN2A_D14_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0xA88))
/* Eric: Add for MII mode */
#define CFG_RGMII0_RXD2_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0x728)) // MII0:TX_EN
#define CFG_RGMII0_RXD0_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0x710)) // MII0:TXD_0
#define CFG_RGMII0_RXD1_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0x71C)) // MII0:TXD_1
#define CFG_RGMII0_RXD3_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0x734)) // MII0:TXD_2
#define CFG_RGMII0_RXCTL_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0x704)) // MII0:TXD_3
/* PAD Configuration Registers */
#define SYSCFG_PAD_RGMII0_TXCTL (*(volatile uint32_t*)(0x4A003654))
#define SYSCFG_PAD_RGMII0_TXD3 (*(volatile uint32_t*)(0x4A003658))
#define SYSCFG_PAD_RGMII0_TXD2 (*(volatile uint32_t*)(0x4A00365C))
#define SYSCFG_PAD_RGMII0_TXD1 (*(volatile uint32_t*)(0x4A003660))
#define SYSCFG_PAD_RGMII0_TXD0 (*(volatile uint32_t*)(0x4A003664))
#define SYSCFG_PAD_VIN2A_D13 (*(volatile uint32_t*)(0x4A00359C))
#define SYSCFG_PAD_VIN2A_D14 (*(volatile uint32_t*)(0x4A0035A0))
#define SYSCFG_PAD_VIN2A_D15 (*(volatile uint32_t*)(0x4A0035A4))
#define SYSCFG_PAD_VIN2A_D16 (*(volatile uint32_t*)(0x4A0035A8))
#define SYSCFG_PAD_VIN2A_D17 (*(volatile uint32_t*)(0x4A0035AC))
/* Eric: Add for MII mode */
#define SYSCFG_PAD_RGMII0_RXD2 (*(volatile uint32_t*)(0x4A003674)) // MII0:TX_EN
#define SYSCFG_PAD_RGMII0_RXD0 (*(volatile uint32_t*)(0x4A00367C)) // MII0:TXD_0
#define SYSCFG_PAD_RGMII0_RXD1 (*(volatile uint32_t*)(0x4A003678)) // MII0:TXD_1
#define SYSCFG_PAD_RGMII0_RXD3 (*(volatile uint32_t*)(0x4A003670)) // MII0:TXD_2
#define SYSCFG_PAD_RGMII0_RXCTL (*(volatile uint32_t*)(0x4A00366C)) // MII0:TXD_3
#define CTRL_MODULE_CTRL_WKUP_ID_CODE (*(volatile uint32_t*)(0x4AE0C204))
#define CTRL_MODULE_CTRL_CORE_SMA_SW_1 (*(volatile uint32_t*) (0x4A002534))
/*---------------------------------------------------------------------------*\
| Local Typedefs/Enums |
\*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*\
| Local Function Declarations |
\*---------------------------------------------------------------------------*/
static void LOCAL_linkStatus( uint32_t phy, uint32_t linkStatus );
/*---------------------------------------------------------------------------*\
| Local Variable Declarations |
\*---------------------------------------------------------------------------*/
/* This string array corresponds to link state */
static char *LinkStr[] = { "No Link",
"None",
"10Mb/s Half Duplex",
"10Mb/s Full Duplex",
"100Mb/s Half Duplex",
"100Mb/s Full Duplex",
"1000Mb/s Half Duplex", /*not suported*/
"1000Mb/s Full Duplex"};
/*---------------------------------------------------------------------------*\
| Global Variable Declarations |
\*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*\
| Local Function Definitions |
\*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*\
| Global Function Definitions |
\*---------------------------------------------------------------------------*/
/**
* \brief This API provides the Silicon Rev Value.
*
* \param None.
*
* \return Silicon Revision.
*
* \note For TDA2xx
* 0: Silicon Rev 1.0
* 1: Silicon Rev 1.1
* 2: Silicon Rev 2.0
* For TDA3xx
* 0: Silicon Rev 1.0
**/
uint32_t PlatformGetSiliconRev(void)
{
uint32_t siliconRev;
siliconRev = CTRL_MODULE_CTRL_WKUP_ID_CODE;
siliconRev = (siliconRev & 0xF0000000U) >> 28U;
return (siliconRev);
}
/*
* We changed our CFG file to point call this private init
* function. Here we initialize our some particulars for
* our board/device.
*/
void vayu_init( void )
{
#if ((PAB_MII != 1) && (PAB_RMII != 1))
uint32_t regValue, delta, coarse, fine;
/*
* We do I/O delay adjustments only if GMAC internal delays are enabled.
* With TDA2xx & TDA2EX PG2.0 the option of disabling internal delays is
* added. SBL will disable the internal delays if siliconRev is 2 so no need
* to adjust I/O delay here.
*/
if (2U != PlatformGetSiliconRev())
{
/*
* Adjust I/O delays on the Tx control and data lines of each MAC port. This is
* a workaround in order to work properly with the DP83865 PHYs on the EVM. In 3COM
* RGMII mode this PHY applies it's own internal clock delay, so we essentially need to
* counteract the DRA7xx internal delay, and we do this by delaying the control and
* data lines. If not using this PHY, you probably don't need to do this stuff!
*/
/* Global unlock for I/O Delay registers */
CFG_IO_DELAY_LOCK = CFG_IO_DELAY_UNLOCK_KEY;
/* Tweaks to RGMII0 Tx Control and Data */
CFG_RGMII0_TXCTL_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
SYSCFG_PAD_RGMII0_TXCTL = (SYSCFG_PAD_RGMII0_TXCTL & ~0xF) | 0x0;
delta = (0x3 << 5) + 0x8; /* Delay value to add to calibrated value */
regValue = CFG_RGMII0_TXCTL_OUT & ~0xFFFFFC00;
coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
fine = (regValue & 0x1F) + (delta & 0x1F);
fine = (fine > 0x1F) ? (0x1F) : (fine);
regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
CFG_RGMII0_TXCTL_OUT = regValue;
CFG_RGMII0_TXD0_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
SYSCFG_PAD_RGMII0_TXD0 = (SYSCFG_PAD_RGMII0_TXD0 & ~0xF) | 0x0;
delta = (0x3 << 5) + 0x8; /* Delay value to add to calibrated value */
regValue = CFG_RGMII0_TXD0_OUT & ~0xFFFFFC00;
coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
fine = (regValue & 0x1F) + (delta & 0x1F);
fine = (fine > 0x1F) ? (0x1F) : (fine);
regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
CFG_RGMII0_TXD0_OUT = regValue;
CFG_RGMII0_TXD1_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
SYSCFG_PAD_RGMII0_TXD1 = (SYSCFG_PAD_RGMII0_TXD1 & ~0xF) | 0x0;
delta = (0x3 << 5) + 0x2; /* Delay value to add to calibrated value */
regValue = CFG_RGMII0_TXD1_OUT & ~0xFFFFFC00;
coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
fine = (regValue & 0x1F) + (delta & 0x1F);
fine = (fine > 0x1F) ? (0x1F) : (fine);
regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
CFG_RGMII0_TXD1_OUT = regValue;
CFG_RGMII0_TXD2_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
SYSCFG_PAD_RGMII0_TXD2 = (SYSCFG_PAD_RGMII0_TXD2 & ~0xF) | 0x0;
delta = (0x4 << 5) + 0x0; /* Delay value to add to calibrated value */
regValue = CFG_RGMII0_TXD2_OUT & ~0xFFFFFC00;
coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
fine = (regValue & 0x1F) + (delta & 0x1F);
fine = (fine > 0x1F) ? (0x1F) : (fine);
regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
CFG_RGMII0_TXD2_OUT = regValue;
CFG_RGMII0_TXD3_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
SYSCFG_PAD_RGMII0_TXD3 = (SYSCFG_PAD_RGMII0_TXD3 & ~0xF) | 0x0;
delta = (0x4 << 5) + 0x0; /* Delay value to add to calibrated value */
regValue = CFG_RGMII0_TXD3_OUT & ~0xFFFFFC00;
coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
fine = (regValue & 0x1F) + (delta & 0x1F);
fine = (fine > 0x1F) ? (0x1F) : (fine);
regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
CFG_RGMII0_TXD3_OUT = regValue;
/* Tweaks to RGMII1 Tx Control and Data */
CFG_VIN2A_D13_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
SYSCFG_PAD_VIN2A_D13 = (SYSCFG_PAD_VIN2A_D13 & ~0xF) | 0x3;
delta = (0x3 << 5) + 0x8; /* Delay value to add to calibrated value */
regValue = CFG_VIN2A_D13_OUT & ~0xFFFFFC00;
coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
fine = (regValue & 0x1F) + (delta & 0x1F);
fine = (fine > 0x1F) ? (0x1F) : (fine);
regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
CFG_VIN2A_D13_OUT = regValue;
CFG_VIN2A_D17_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
SYSCFG_PAD_VIN2A_D17 = (SYSCFG_PAD_VIN2A_D17 & ~0xF) | 0x3;
delta = (0x3 << 5) + 0x8;
regValue = CFG_VIN2A_D17_OUT & ~0xFFFFFC00;
coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
fine = (regValue & 0x1F) + (delta & 0x1F);
fine = (fine > 0x1F) ? (0x1F) : (fine);
regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
CFG_VIN2A_D17_OUT = regValue;
CFG_VIN2A_D16_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
SYSCFG_PAD_VIN2A_D16 = (SYSCFG_PAD_VIN2A_D16 & ~0xF) | 0x3;
delta = (0x3 << 5) + 0x2;
regValue = CFG_VIN2A_D16_OUT & ~0xFFFFFC00;
coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
fine = (regValue & 0x1F) + (delta & 0x1F);
fine = (fine > 0x1F) ? (0x1F) : (fine);
regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
CFG_VIN2A_D16_OUT = regValue;
CFG_VIN2A_D15_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
SYSCFG_PAD_VIN2A_D15 = (SYSCFG_PAD_VIN2A_D15 & ~0xF) | 0x3;
delta = (0x4 << 5) + 0x0;
regValue = CFG_VIN2A_D15_OUT & ~0xFFFFFC00;
coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
fine = (regValue & 0x1F) + (delta & 0x1F);
fine = (fine > 0x1F) ? (0x1F) : (fine);
regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
CFG_VIN2A_D15_OUT = regValue;
CFG_VIN2A_D14_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
SYSCFG_PAD_VIN2A_D14 = (SYSCFG_PAD_VIN2A_D14 & ~0xF) | 0x3;
delta = (0x4 << 5) + 0x0;
regValue = CFG_VIN2A_D14_OUT & ~0xFFFFFC00;
coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
fine = (regValue & 0x1F) + (delta & 0x1F);
fine = (fine > 0x1F) ? (0x1F) : (fine);
regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
CFG_VIN2A_D14_OUT = regValue;
/* Global lock */
CFG_IO_DELAY_LOCK = CFG_IO_DELAY_LOCK_KEY;
}
else
{
/* Disable RGMII half cycle delay for ES2.0 silicon */
regValue = CTRL_MODULE_CTRL_CORE_SMA_SW_1;
/* Disable half cycle delay for RGMII0 */
regValue |= (0x1 << 25U);
/* Disable half cycle delay for RGMII1 */
regValue |= (0x1 << 26U);
CTRL_MODULE_CTRL_CORE_SMA_SW_1 = regValue;
}
#endif
/* Eric: Add for MII mode start */
#if (PAB_MII == 1)
uint32_t regValue, delta, coarse, fine;
/* Global unlock for I/O Delay registers */
CFG_IO_DELAY_LOCK = CFG_IO_DELAY_UNLOCK_KEY;
/* Tweaks to RGMII0 Tx Control and Data */
CFG_RGMII0_RXD2_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
SYSCFG_PAD_RGMII0_RXD2 = (SYSCFG_PAD_RGMII0_RXD2 & ~0xF) | 0x3; /* 0x3: mii0_txen */
delta = (0x3 << 5) + 0x8; /* Delay value to add to calibrated value */
regValue = CFG_RGMII0_RXD2_OUT & ~0xFFFFFC00;
coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
fine = (regValue & 0x1F) + (delta & 0x1F);
fine = (fine > 0x1F) ? (0x1F) : (fine);
regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
CFG_RGMII0_RXD2_OUT = regValue;
CFG_RGMII0_RXD0_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
SYSCFG_PAD_RGMII0_RXD0 = (SYSCFG_PAD_RGMII0_RXD0 & ~0xF) | 0x3; /* 0x3: mii0_txd0 */
delta = (0x3 << 5) + 0x8; /* Delay value to add to calibrated value */
regValue = CFG_RGMII0_RXD0_OUT & ~0xFFFFFC00;
coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
fine = (regValue & 0x1F) + (delta & 0x1F);
fine = (fine > 0x1F) ? (0x1F) : (fine);
regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
CFG_RGMII0_RXD0_OUT = regValue;
CFG_RGMII0_RXD1_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
SYSCFG_PAD_RGMII0_RXD1 = (SYSCFG_PAD_RGMII0_RXD1 & ~0xF) | 0x3; /* 0x3: mii0_txd1 */
delta = (0x3 << 5) + 0x2; /* Delay value to add to calibrated value */
regValue = CFG_RGMII0_RXD1_OUT & ~0xFFFFFC00;
coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
fine = (regValue & 0x1F) + (delta & 0x1F);
fine = (fine > 0x1F) ? (0x1F) : (fine);
regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
CFG_RGMII0_RXD1_OUT = regValue;
CFG_RGMII0_RXD3_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
SYSCFG_PAD_RGMII0_RXD3 = (SYSCFG_PAD_RGMII0_RXD3 & ~0xF) | 0x3; /* 0x3: mii0_txd2 */
delta = (0x4 << 5) + 0x0; /* Delay value to add to calibrated value */
regValue = CFG_RGMII0_RXD3_OUT & ~0xFFFFFC00;
coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
fine = (regValue & 0x1F) + (delta & 0x1F);
fine = (fine > 0x1F) ? (0x1F) : (fine);
regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
CFG_RGMII0_RXD3_OUT = regValue;
CFG_RGMII0_RXCTL_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
SYSCFG_PAD_RGMII0_RXCTL = (SYSCFG_PAD_RGMII0_RXCTL & ~0xF) | 0x3; /* 0x3: mii0_txd3 */
delta = (0x4 << 5) + 0x0; /* Delay value to add to calibrated value */
regValue = CFG_RGMII0_RXCTL_OUT & ~0xFFFFFC00;
coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
fine = (regValue & 0x1F) + (delta & 0x1F);
fine = (fine > 0x1F) ? (0x1F) : (fine);
regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
CFG_RGMII0_RXCTL_OUT = regValue;
/* Global lock */
CFG_IO_DELAY_LOCK = CFG_IO_DELAY_LOCK_KEY;
/* Eric: Add for MII mode End */
#endif
}
/*
* GMACSW_getConfig()
*
* This is a callback from the Ethernet driver. This function
* is used by the driver to an application-specific config structure
* for the GMACSW driver. Typically it will be used to provide the
* MAC address(es) and the link status update callback function.
*/
GMACSW_Config *GMACSW_getConfig(void)
{
int i = 0;
uint8_t macAddr[6];
/* Get digital loopback starting config */
GMACSW_Config *pGMACSWConfig = GMACSW_CONFIG_getDefaultConfig();
/* Update default config with the correct MAC addresses */
for(i=0; i<(pGMACSWConfig->activeMACPortCount); i++)
{
if (0==i)
{
/* Get the MAC Address from control module register space */
macAddr[5] = (uint8_t)((MAC_ID0_LO & 0x000000FFu) >> 0u );
macAddr[4] = (uint8_t)((MAC_ID0_LO & 0x0000FF00u) >> 8u );
macAddr[3] = (uint8_t)((MAC_ID0_LO & 0x00FF0000u) >> 16u);
macAddr[2] = (uint8_t)((MAC_ID0_HI & 0x000000FFu) >> 0u );
macAddr[1] = (uint8_t)((MAC_ID0_HI & 0x0000FF00u) >> 8u );
macAddr[0] = (uint8_t)((MAC_ID0_HI & 0x00FF0000u) >> 16u);
}
else
{
/* Get the MAC Address from control module register space */
macAddr[5] = (uint8_t)((MAC_ID1_LO & 0x000000FFu) >> 0u );
macAddr[4] = (uint8_t)((MAC_ID1_LO & 0x0000FF00u) >> 8u );
macAddr[3] = (uint8_t)((MAC_ID1_LO & 0x00FF0000u) >> 16u);
macAddr[2] = (uint8_t)((MAC_ID1_HI & 0x000000FFu) >> 0u );
macAddr[1] = (uint8_t)((MAC_ID1_HI & 0x0000FF00u) >> 8u );
macAddr[0] = (uint8_t)((MAC_ID1_HI & 0x00FF0000u) >> 16u);
}
printf("\nMAC Port %d Address:\n\t%02x-%02x-%02x-%02x-%02x-%02x\n", i,
macAddr[0], macAddr[1], macAddr[2],
macAddr[3], macAddr[4], macAddr[5]);
/* Copy the correct MAC address into the driver config */
memcpy( (void *)&(pGMACSWConfig->macInitCfg[i].macAddr[0]), (void *)&macAddr[0], 6 );
#if ((PAB_MII == 1) || (PAB_RMII == 1))
/*
* Adjust the PHY mask numbers for the Vayu PAB. The first MAC
* port is connected to a PHY with address = 3, the second MAC
* port is connected to a PHY with address = 2.
*/
pGMACSWConfig->macInitCfg[i].phyMask = 0x1 << (3 - i);
#else
/*
* Adjust the PHY mask numbers for the Vayu EVM. The first MAC
* port is connected to a PHY with address = 2, the second MAC
* port is connected to a PHY with address = 3.
*/
pGMACSWConfig->macInitCfg[i].phyMask = 0x1 << (2 + i);
#endif
#if (PAB_MII == 1)
pGMACSWConfig->macInitCfg[i].macConnectionType =
MAC_CONNECTION_TYPE_MII_100;
#elif (PAB_RMII == 1)
pGMACSWConfig->macInitCfg[i].macConnectionType =
MAC_CONNECTION_TYPE_RMII_100;
#else
/*
* National PHY on Vayu EVM does not work with the default INBAND detection mode.
* It would seem the Rx clock from the PHY is not generated unless the Tx clock
* from the Vayu device is present. So set the mode to force 1Gbps to start.
*/
pGMACSWConfig->macInitCfg[i].macConnectionType =
MAC_CONNECTION_TYPE_RGMII_FORCE_1000_FULL;
#endif
}
pGMACSWConfig->linkStatusCallback = &LOCAL_linkStatus;
/* Return the config */
return pGMACSWConfig;
}
/*---------------------------------------------------------------------------*\
| Local Function Definitions |
\*---------------------------------------------------------------------------*/
/*
* LOCAL_linkStatus()
*
* This is a callback from the Ethernet driver. This function
* is called whenever there is a change in link state. The
* current PHY and current link state are passed as parameters.
*/
static void LOCAL_linkStatus( uint32_t phy, uint32_t linkStatus )
{
printf("Link Status: %s on PHY %" PRIu32 "\n",LinkStr[linkStatus],phy);
}
/*---------------------------------------------------------------------------*\
| End of File |
\*---------------------------------------------------------------------------*/
Hello Eric, Thanks for very details information. It is very much useful. I reviewed your PAD config and NSP data log files. As I see in the NSP log, the MDIO is not detecting the MII PHYs. And this is because PAD configuration for MDIO PADs not happening correctly. If you see in the gel file "TDA2xx_PAD_GmacSw_EVM_MDIO_Config" configures SYSCFG_PAD_MDIO_MCLK(line 3446) and SYSCFG_PAD_MDIO_D(3454) but these PADs you are also using for MII mode. So you will need to modify this function for adding configuration VIN2A_D10 (line 1458) and VIN2A_D11(line 1469) which on your board you are using for MDIO. Once you do this please check if you are able to detect PHY when run NSP application. You should see something like below message Link Status: 100Mb/s Full Duplex on PHY 2 Once this is done, we can see if data transfer is happening correctly. If not, we can check stats registers to see what kind of errors are coming on receive. Also I see you have made changes for IO delay in MII mode. I am assuming you are using these values from correct Data manual for SR you are using. Also you are applying delays only for RX data lines. Let me know.
Hi Prasad, I modified this configuration MDIO_MCLK and MDIO_D in the function "TDA2xx_PAD_GmacSw_PAB_MDIO_Config" with SYSCFG_PAD_VIN2A_D10 (L:3446) and SYSCFG_PAD_VIN2A_D11(L:3454) hotmenu TDA2xx_PAD_GmacSw_PAB_MDIO_Config() { GEL_TextOut("\t--->>> TDA2xx Begin GMAC_SW MDIO Pad Configuration <<<---\n"); /* MDIO (2 pads) */ SYSCFG_WR_CFG_PAD (SYSCFG_PAD_VIN2A_D10, SYSCFG_PAD_VIN2A_D10_MDIO_MCLK, SYSCFG_PULLUD_ENABLE_ENABLE, SYSCFG_PULLTYPE_SELECT_PULLUP, SYSCFG_INPUT_ENABLE_DISABLE, SYSCFG_SLEW_CONTROL_NA, SYSCFG_WAKEUP_ENABLE_DISABLE); SYSCFG_WR_CFG_PAD (SYSCFG_PAD_VIN2A_D11, SYSCFG_PAD_VIN2A_D11_MDIO_D, SYSCFG_PULLUD_ENABLE_ENABLE, SYSCFG_PULLTYPE_SELECT_PULLUP, SYSCFG_INPUT_ENABLE_ENABLE, SYSCFG_SLEW_CONTROL_NA, SYSCFG_WAKEUP_ENABLE_DISABLE); GEL_TextOut("\t--->>> TDA2xx End GMAC_SW MDIO Pad Configuration <<<---\n"); } Log that apply VIN2A_D10 and VIN2A_D11: [Cortex_M4_IPU1_C0] MAC Port 0 Address: d0-b5-c2-5b-42-ee MAC Port 1 Address: d0-b5-c2-5b-42-ef GMACSW has been started successfully Registration of the GMACSW Successful Service Status: DHCPC : Enabled : : 000 Service Status: Telnet : Enabled : : 000 Service Status: HTTP : Enabled : : 000 Service Status: HTTP : Enabled : : 000 Service Status: DHCPC : Enabled : Running : 000 Service Status: DHCPC : Enabled : Fault : 002 <- New log But, I can not see this line. Link Status: 100Mb/s Full Duplex on PHY 2 Which register I should check for error status? ------------------------------------------------------------------------------------------------------------- About I/O delay setting, I see only "Tx Control and Data" was set for RGMII mode in vayu_init.c. CFG_RGMII0_TXCTL_OUT //RGMII: rgmii0_txctl CFG_RGMII0_TXD0_OUT //RMIII: rgmii0_txd0 CFG_RGMII0_TXD1_OUT //RMIII: rgmii0_txd1 CFG_RGMII0_TXD2_OUT //RMIII: rgmii0_txd2 CFG_RGMII0_TXD3_OUT //RMIII: rgmii0_txd3 So, I also only set I/O delay for Tx Control and Data for MII mode in my board. But "I/O delay value" should be wrong. CFG_RGMII0_RXD2_OUT //MII: mii0_txen delta = (0x3 << 5) + 0x8; /* Delay value to add to calibrated value */ CFG_RGMII0_RXD0_OUT //MII: mii0_txd0 delta = (0x3 << 5) + 0x8; /* Delay value to add to calibrated value */ CFG_RGMII0_RXD1_OUT //MII:mii0_txd1 delta = (0x3 << 5) + 0x2; /* Delay value to add to calibrated value */ CFG_RGMII0_RXD3_OUT //MII: mii0_txd2 delta = (0x4 << 5) + 0x0; /* Delay value to add to calibrated value */ CFG_RGMII0_RXCTL_OUT //MII: mii0_txd3 delta = (0x4 << 5) + 0x0; /* Delay value to add to calibrated value */ My board used dp83848q(in attachment) as Ethernet phy. Which pin I need to set for I/O delay value? 4174.TDA2xx_pad_config.gel NSPLog2.txt [Cortex_M4_IPU1_C0]
MAC Port 0 Address:
d0-b5-c2-5b-42-ee
MAC Port 1 Address:
d0-b5-c2-5b-42-ef
GMACSW has been started successfully
Registration of the GMACSW Successful
Service Status: DHCPC : Enabled : : 000
Service Status: Telnet : Enabled : : 000
Service Status: HTTP : Enabled : : 000
Service Status: HTTP : Enabled : : 000
Service Status: DHCPC : Enabled : Running : 000
Service Status: DHCPC : Enabled : Fault : 002
dp83848q-q1.pdf
Hello Eric, The MDIO PHY link status and PHY_ALIVE registers will tell you if PHYs are detected. Check for 0x4848_5008 and 0x4848_500C for it. 0x4848_5008 should have bit set to 1 for your PHY address. If this bit is not set then issue is in PAD config or MDIO wiring on EVM. Now if bit is set then calculate PHY address and modify NSP vayu_init.c line 486 for that PHY address mask. This should enable the PHY detect print. #if ((PAB_MII == 1) || (PAB_RMII == 1)) /* * Adjust the PHY mask numbers for the Vayu PAB. The first MAC * port is connected to a PHY with address = 3, the second MAC * port is connected to a PHY with address = 2. */ pGMACSWConfig->macInitCfg[i].phyMask = 0x1 << (3 - i); #else Now coming to delay we have delay only for TX due to PHY issue on TDA2 EVM so only delay applied on TX. As of now i would suggest you to remove all delays altogether for MII. Once we get PHY detected and data transfer happening, i will tell the stats addresses to look if we'll need any delay
Hi Prasad, I dump 0x4848_5008 and 0x4848_500C register. These values are show as follow: 0x4848_5008 register value is 00000001 0x4848_500C register value is 00000001 I also modified vayu_init.c as follow. 2744.vayu_init.c /*
* Copyright (C) 2013, Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file vayu_init.c
*
* @brief
* Do all necessary board level initialization for NDK example.
*
*/
/*---------------------------------------------------------------------------*\
| Header Files |
\*---------------------------------------------------------------------------*/
/* Standard language headers */
#include <stddef.h>
#include <stdio.h>
#include <inttypes.h>
#include <string.h>
/* OS/Posix headers */
/* NDK Dependencies */
#include <ti/ndk/inc/netmain.h>
/* NSP Dependencies */
#include <ti/nsp/drv/inc/gmacsw_config.h>
/* Project dependency headers */
/*---------------------------------------------------------------------------*\
| Extern Declarations |
\*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*\
| Local Macros/Defines |
\*---------------------------------------------------------------------------*/
#define PAB_MII (1) /* Eric: Modify for MII mode: #define PAB_MII (0) */
#define PAB_RMII (0)
/* Ethernet MAC ID registers(Devcice configuration) from EFuse */
#define MAC_ID0_LO (*(volatile uint32_t*)0x4A002514)
#define MAC_ID0_HI (*(volatile uint32_t*)0x4A002518)
#define MAC_ID1_LO (*(volatile uint32_t*)0x4A00251C)
#define MAC_ID1_HI (*(volatile uint32_t*)0x4A002520)
/* I/O Delay related registers */
#define CFG_IO_DELAY_UNLOCK_KEY (0x0000AAAA)
#define CFG_IO_DELAY_LOCK_KEY (0x0000AAAB)
#define CFG_IO_DELAY_ACCESS_PATTERN (0x00029000)
#define CFG_IO_DELAY_LOCK_MASK (0x400)
#define CFG_IO_DELAY_BASE (0x4844A000)
#define CFG_IO_DELAY_LOCK (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0x02C))
#define CFG_RGMII0_TXCTL_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0x74C))
#define CFG_RGMII0_TXD0_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0x758))
#define CFG_RGMII0_TXD1_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0x764))
#define CFG_RGMII0_TXD2_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0x770))
#define CFG_RGMII0_TXD3_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0x77C))
#define CFG_VIN2A_D13_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0xA7C))
#define CFG_VIN2A_D17_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0xAAC))
#define CFG_VIN2A_D16_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0xAA0))
#define CFG_VIN2A_D15_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0xA94))
#define CFG_VIN2A_D14_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0xA88))
///* Eric: Add for MII mode */
//#define CFG_RGMII0_RXD2_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0x728)) // MII0:TX_EN
//#define CFG_RGMII0_RXD0_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0x710)) // MII0:TXD_0
//#define CFG_RGMII0_RXD1_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0x71C)) // MII0:TXD_1
//#define CFG_RGMII0_RXD3_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0x734)) // MII0:TXD_2
//#define CFG_RGMII0_RXCTL_OUT (*(volatile uint32_t*)(CFG_IO_DELAY_BASE + 0x704)) // MII0:TXD_3
/* PAD Configuration Registers */
#define SYSCFG_PAD_RGMII0_TXCTL (*(volatile uint32_t*)(0x4A003654))
#define SYSCFG_PAD_RGMII0_TXD3 (*(volatile uint32_t*)(0x4A003658))
#define SYSCFG_PAD_RGMII0_TXD2 (*(volatile uint32_t*)(0x4A00365C))
#define SYSCFG_PAD_RGMII0_TXD1 (*(volatile uint32_t*)(0x4A003660))
#define SYSCFG_PAD_RGMII0_TXD0 (*(volatile uint32_t*)(0x4A003664))
#define SYSCFG_PAD_VIN2A_D13 (*(volatile uint32_t*)(0x4A00359C))
#define SYSCFG_PAD_VIN2A_D14 (*(volatile uint32_t*)(0x4A0035A0))
#define SYSCFG_PAD_VIN2A_D15 (*(volatile uint32_t*)(0x4A0035A4))
#define SYSCFG_PAD_VIN2A_D16 (*(volatile uint32_t*)(0x4A0035A8))
#define SYSCFG_PAD_VIN2A_D17 (*(volatile uint32_t*)(0x4A0035AC))
///* Eric: Add for MII mode */
//#define SYSCFG_PAD_RGMII0_RXD2 (*(volatile uint32_t*)(0x4A003674)) // MII0:TX_EN
//#define SYSCFG_PAD_RGMII0_RXD0 (*(volatile uint32_t*)(0x4A00367C)) // MII0:TXD_0
//#define SYSCFG_PAD_RGMII0_RXD1 (*(volatile uint32_t*)(0x4A003678)) // MII0:TXD_1
//#define SYSCFG_PAD_RGMII0_RXD3 (*(volatile uint32_t*)(0x4A003670)) // MII0:TXD_2
//#define SYSCFG_PAD_RGMII0_RXCTL (*(volatile uint32_t*)(0x4A00366C)) // MII0:TXD_3
#define CTRL_MODULE_CTRL_WKUP_ID_CODE (*(volatile uint32_t*)(0x4AE0C204))
#define CTRL_MODULE_CTRL_CORE_SMA_SW_1 (*(volatile uint32_t*) (0x4A002534))
/*---------------------------------------------------------------------------*\
| Local Typedefs/Enums |
\*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*\
| Local Function Declarations |
\*---------------------------------------------------------------------------*/
static void LOCAL_linkStatus( uint32_t phy, uint32_t linkStatus );
/*---------------------------------------------------------------------------*\
| Local Variable Declarations |
\*---------------------------------------------------------------------------*/
/* This string array corresponds to link state */
static char *LinkStr[] = { "No Link",
"None",
"10Mb/s Half Duplex",
"10Mb/s Full Duplex",
"100Mb/s Half Duplex",
"100Mb/s Full Duplex",
"1000Mb/s Half Duplex", /*not suported*/
"1000Mb/s Full Duplex"};
/*---------------------------------------------------------------------------*\
| Global Variable Declarations |
\*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*\
| Local Function Definitions |
\*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*\
| Global Function Definitions |
\*---------------------------------------------------------------------------*/
/**
* \brief This API provides the Silicon Rev Value.
*
* \param None.
*
* \return Silicon Revision.
*
* \note For TDA2xx
* 0: Silicon Rev 1.0
* 1: Silicon Rev 1.1
* 2: Silicon Rev 2.0
* For TDA3xx
* 0: Silicon Rev 1.0
**/
uint32_t PlatformGetSiliconRev(void)
{
uint32_t siliconRev;
siliconRev = CTRL_MODULE_CTRL_WKUP_ID_CODE;
siliconRev = (siliconRev & 0xF0000000U) >> 28U;
return (siliconRev);
}
/*
* We changed our CFG file to point call this private init
* function. Here we initialize our some particulars for
* our board/device.
*/
void vayu_init( void )
{
#if ((PAB_MII != 1) && (PAB_RMII != 1))
uint32_t regValue, delta, coarse, fine;
/*
* We do I/O delay adjustments only if GMAC internal delays are enabled.
* With TDA2xx & TDA2EX PG2.0 the option of disabling internal delays is
* added. SBL will disable the internal delays if siliconRev is 2 so no need
* to adjust I/O delay here.
*/
if (2U != PlatformGetSiliconRev())
{
/*
* Adjust I/O delays on the Tx control and data lines of each MAC port. This is
* a workaround in order to work properly with the DP83865 PHYs on the EVM. In 3COM
* RGMII mode this PHY applies it's own internal clock delay, so we essentially need to
* counteract the DRA7xx internal delay, and we do this by delaying the control and
* data lines. If not using this PHY, you probably don't need to do this stuff!
*/
/* Global unlock for I/O Delay registers */
CFG_IO_DELAY_LOCK = CFG_IO_DELAY_UNLOCK_KEY;
/* Tweaks to RGMII0 Tx Control and Data */
CFG_RGMII0_TXCTL_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
SYSCFG_PAD_RGMII0_TXCTL = (SYSCFG_PAD_RGMII0_TXCTL & ~0xF) | 0x0;
delta = (0x3 << 5) + 0x8; /* Delay value to add to calibrated value */
regValue = CFG_RGMII0_TXCTL_OUT & ~0xFFFFFC00;
coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
fine = (regValue & 0x1F) + (delta & 0x1F);
fine = (fine > 0x1F) ? (0x1F) : (fine);
regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
CFG_RGMII0_TXCTL_OUT = regValue;
CFG_RGMII0_TXD0_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
SYSCFG_PAD_RGMII0_TXD0 = (SYSCFG_PAD_RGMII0_TXD0 & ~0xF) | 0x0;
delta = (0x3 << 5) + 0x8; /* Delay value to add to calibrated value */
regValue = CFG_RGMII0_TXD0_OUT & ~0xFFFFFC00;
coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
fine = (regValue & 0x1F) + (delta & 0x1F);
fine = (fine > 0x1F) ? (0x1F) : (fine);
regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
CFG_RGMII0_TXD0_OUT = regValue;
CFG_RGMII0_TXD1_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
SYSCFG_PAD_RGMII0_TXD1 = (SYSCFG_PAD_RGMII0_TXD1 & ~0xF) | 0x0;
delta = (0x3 << 5) + 0x2; /* Delay value to add to calibrated value */
regValue = CFG_RGMII0_TXD1_OUT & ~0xFFFFFC00;
coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
fine = (regValue & 0x1F) + (delta & 0x1F);
fine = (fine > 0x1F) ? (0x1F) : (fine);
regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
CFG_RGMII0_TXD1_OUT = regValue;
CFG_RGMII0_TXD2_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
SYSCFG_PAD_RGMII0_TXD2 = (SYSCFG_PAD_RGMII0_TXD2 & ~0xF) | 0x0;
delta = (0x4 << 5) + 0x0; /* Delay value to add to calibrated value */
regValue = CFG_RGMII0_TXD2_OUT & ~0xFFFFFC00;
coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
fine = (regValue & 0x1F) + (delta & 0x1F);
fine = (fine > 0x1F) ? (0x1F) : (fine);
regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
CFG_RGMII0_TXD2_OUT = regValue;
CFG_RGMII0_TXD3_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
SYSCFG_PAD_RGMII0_TXD3 = (SYSCFG_PAD_RGMII0_TXD3 & ~0xF) | 0x0;
delta = (0x4 << 5) + 0x0; /* Delay value to add to calibrated value */
regValue = CFG_RGMII0_TXD3_OUT & ~0xFFFFFC00;
coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
fine = (regValue & 0x1F) + (delta & 0x1F);
fine = (fine > 0x1F) ? (0x1F) : (fine);
regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
CFG_RGMII0_TXD3_OUT = regValue;
/* Tweaks to RGMII1 Tx Control and Data */
CFG_VIN2A_D13_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
SYSCFG_PAD_VIN2A_D13 = (SYSCFG_PAD_VIN2A_D13 & ~0xF) | 0x3;
delta = (0x3 << 5) + 0x8; /* Delay value to add to calibrated value */
regValue = CFG_VIN2A_D13_OUT & ~0xFFFFFC00;
coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
fine = (regValue & 0x1F) + (delta & 0x1F);
fine = (fine > 0x1F) ? (0x1F) : (fine);
regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
CFG_VIN2A_D13_OUT = regValue;
CFG_VIN2A_D17_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
SYSCFG_PAD_VIN2A_D17 = (SYSCFG_PAD_VIN2A_D17 & ~0xF) | 0x3;
delta = (0x3 << 5) + 0x8;
regValue = CFG_VIN2A_D17_OUT & ~0xFFFFFC00;
coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
fine = (regValue & 0x1F) + (delta & 0x1F);
fine = (fine > 0x1F) ? (0x1F) : (fine);
regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
CFG_VIN2A_D17_OUT = regValue;
CFG_VIN2A_D16_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
SYSCFG_PAD_VIN2A_D16 = (SYSCFG_PAD_VIN2A_D16 & ~0xF) | 0x3;
delta = (0x3 << 5) + 0x2;
regValue = CFG_VIN2A_D16_OUT & ~0xFFFFFC00;
coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
fine = (regValue & 0x1F) + (delta & 0x1F);
fine = (fine > 0x1F) ? (0x1F) : (fine);
regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
CFG_VIN2A_D16_OUT = regValue;
CFG_VIN2A_D15_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
SYSCFG_PAD_VIN2A_D15 = (SYSCFG_PAD_VIN2A_D15 & ~0xF) | 0x3;
delta = (0x4 << 5) + 0x0;
regValue = CFG_VIN2A_D15_OUT & ~0xFFFFFC00;
coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
fine = (regValue & 0x1F) + (delta & 0x1F);
fine = (fine > 0x1F) ? (0x1F) : (fine);
regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
CFG_VIN2A_D15_OUT = regValue;
CFG_VIN2A_D14_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
SYSCFG_PAD_VIN2A_D14 = (SYSCFG_PAD_VIN2A_D14 & ~0xF) | 0x3;
delta = (0x4 << 5) + 0x0;
regValue = CFG_VIN2A_D14_OUT & ~0xFFFFFC00;
coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
fine = (regValue & 0x1F) + (delta & 0x1F);
fine = (fine > 0x1F) ? (0x1F) : (fine);
regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
CFG_VIN2A_D14_OUT = regValue;
/* Global lock */
CFG_IO_DELAY_LOCK = CFG_IO_DELAY_LOCK_KEY;
}
else
{
/* Disable RGMII half cycle delay for ES2.0 silicon */
regValue = CTRL_MODULE_CTRL_CORE_SMA_SW_1;
/* Disable half cycle delay for RGMII0 */
regValue |= (0x1 << 25U);
/* Disable half cycle delay for RGMII1 */
regValue |= (0x1 << 26U);
CTRL_MODULE_CTRL_CORE_SMA_SW_1 = regValue;
}
#endif
// /* Eric: Add for MII mode start */
//#if (PAB_MII == 1)
//
// uint32_t regValue, delta, coarse, fine;
//
// /* Global unlock for I/O Delay registers */
// CFG_IO_DELAY_LOCK = CFG_IO_DELAY_UNLOCK_KEY;
//
// /* Tweaks to RGMII0 Tx Control and Data */
// CFG_RGMII0_RXD2_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
// SYSCFG_PAD_RGMII0_RXD2 = (SYSCFG_PAD_RGMII0_RXD2 & ~0xF) | 0x3; /* 0x3: mii0_txen */
// delta = (0x3 << 5) + 0x8; /* Delay value to add to calibrated value */
// regValue = CFG_RGMII0_RXD2_OUT & ~0xFFFFFC00;
// coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
// coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
// fine = (regValue & 0x1F) + (delta & 0x1F);
// fine = (fine > 0x1F) ? (0x1F) : (fine);
// regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
// CFG_RGMII0_RXD2_OUT = regValue;
//
// CFG_RGMII0_RXD0_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
// SYSCFG_PAD_RGMII0_RXD0 = (SYSCFG_PAD_RGMII0_RXD0 & ~0xF) | 0x3; /* 0x3: mii0_txd0 */
// delta = (0x3 << 5) + 0x8; /* Delay value to add to calibrated value */
// regValue = CFG_RGMII0_RXD0_OUT & ~0xFFFFFC00;
// coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
// coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
// fine = (regValue & 0x1F) + (delta & 0x1F);
// fine = (fine > 0x1F) ? (0x1F) : (fine);
// regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
// CFG_RGMII0_RXD0_OUT = regValue;
//
// CFG_RGMII0_RXD1_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
// SYSCFG_PAD_RGMII0_RXD1 = (SYSCFG_PAD_RGMII0_RXD1 & ~0xF) | 0x3; /* 0x3: mii0_txd1 */
// delta = (0x3 << 5) + 0x2; /* Delay value to add to calibrated value */
// regValue = CFG_RGMII0_RXD1_OUT & ~0xFFFFFC00;
// coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
// coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
// fine = (regValue & 0x1F) + (delta & 0x1F);
// fine = (fine > 0x1F) ? (0x1F) : (fine);
// regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
// CFG_RGMII0_RXD1_OUT = regValue;
//
// CFG_RGMII0_RXD3_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
// SYSCFG_PAD_RGMII0_RXD3 = (SYSCFG_PAD_RGMII0_RXD3 & ~0xF) | 0x3; /* 0x3: mii0_txd2 */
// delta = (0x4 << 5) + 0x0; /* Delay value to add to calibrated value */
// regValue = CFG_RGMII0_RXD3_OUT & ~0xFFFFFC00;
// coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
// coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
// fine = (regValue & 0x1F) + (delta & 0x1F);
// fine = (fine > 0x1F) ? (0x1F) : (fine);
// regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
// CFG_RGMII0_RXD3_OUT = regValue;
//
// CFG_RGMII0_RXCTL_OUT = (CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK);
// SYSCFG_PAD_RGMII0_RXCTL = (SYSCFG_PAD_RGMII0_RXCTL & ~0xF) | 0x3; /* 0x3: mii0_txd3 */
// delta = (0x4 << 5) + 0x0; /* Delay value to add to calibrated value */
// regValue = CFG_RGMII0_RXCTL_OUT & ~0xFFFFFC00;
// coarse = ((regValue >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
// coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
// fine = (regValue & 0x1F) + (delta & 0x1F);
// fine = (fine > 0x1F) ? (0x1F) : (fine);
// regValue = CFG_IO_DELAY_ACCESS_PATTERN | CFG_IO_DELAY_LOCK_MASK | ((coarse << 5) | (fine));
// CFG_RGMII0_RXCTL_OUT = regValue;
//
// /* Global lock */
// CFG_IO_DELAY_LOCK = CFG_IO_DELAY_LOCK_KEY;
//
// /* Eric: Add for MII mode End */
//#endif
}
/*
* GMACSW_getConfig()
*
* This is a callback from the Ethernet driver. This function
* is used by the driver to an application-specific config structure
* for the GMACSW driver. Typically it will be used to provide the
* MAC address(es) and the link status update callback function.
*/
GMACSW_Config *GMACSW_getConfig(void)
{
int i = 0;
uint8_t macAddr[6];
/* Get digital loopback starting config */
GMACSW_Config *pGMACSWConfig = GMACSW_CONFIG_getDefaultConfig();
/* Update default config with the correct MAC addresses */
for(i=0; i<(pGMACSWConfig->activeMACPortCount); i++)
{
if (0==i)
{
/* Get the MAC Address from control module register space */
macAddr[5] = (uint8_t)((MAC_ID0_LO & 0x000000FFu) >> 0u );
macAddr[4] = (uint8_t)((MAC_ID0_LO & 0x0000FF00u) >> 8u );
macAddr[3] = (uint8_t)((MAC_ID0_LO & 0x00FF0000u) >> 16u);
macAddr[2] = (uint8_t)((MAC_ID0_HI & 0x000000FFu) >> 0u );
macAddr[1] = (uint8_t)((MAC_ID0_HI & 0x0000FF00u) >> 8u );
macAddr[0] = (uint8_t)((MAC_ID0_HI & 0x00FF0000u) >> 16u);
}
else
{
/* Get the MAC Address from control module register space */
macAddr[5] = (uint8_t)((MAC_ID1_LO & 0x000000FFu) >> 0u );
macAddr[4] = (uint8_t)((MAC_ID1_LO & 0x0000FF00u) >> 8u );
macAddr[3] = (uint8_t)((MAC_ID1_LO & 0x00FF0000u) >> 16u);
macAddr[2] = (uint8_t)((MAC_ID1_HI & 0x000000FFu) >> 0u );
macAddr[1] = (uint8_t)((MAC_ID1_HI & 0x0000FF00u) >> 8u );
macAddr[0] = (uint8_t)((MAC_ID1_HI & 0x00FF0000u) >> 16u);
}
printf("\nMAC Port %d Address:\n\t%02x-%02x-%02x-%02x-%02x-%02x\n", i,
macAddr[0], macAddr[1], macAddr[2],
macAddr[3], macAddr[4], macAddr[5]);
/* Copy the correct MAC address into the driver config */
memcpy( (void *)&(pGMACSWConfig->macInitCfg[i].macAddr[0]), (void *)&macAddr[0], 6 );
#if ((PAB_MII == 1) || (PAB_RMII == 1))
/*
* Adjust the PHY mask numbers for the Vayu PAB. The first MAC
* port is connected to a PHY with address = 3, the second MAC
* port is connected to a PHY with address = 2.
*/
// pGMACSWConfig->macInitCfg[i].phyMask = 0x1 << (3 - i);
pGMACSWConfig->macInitCfg[i].phyMask = 0x1 << (2 - i);
#else
/*
* Adjust the PHY mask numbers for the Vayu EVM. The first MAC
* port is connected to a PHY with address = 2, the second MAC
* port is connected to a PHY with address = 3.
*/
// pGMACSWConfig->macInitCfg[i].phyMask = 0x1 << (2 + i);
pGMACSWConfig->macInitCfg[i].phyMask = 0x1 << (3 + i);
#endif
#if (PAB_MII == 1)
pGMACSWConfig->macInitCfg[i].macConnectionType =
MAC_CONNECTION_TYPE_MII_100;
#elif (PAB_RMII == 1)
pGMACSWConfig->macInitCfg[i].macConnectionType =
MAC_CONNECTION_TYPE_RMII_100;
#else
/*
* National PHY on Vayu EVM does not work with the default INBAND detection mode.
* It would seem the Rx clock from the PHY is not generated unless the Tx clock
* from the Vayu device is present. So set the mode to force 1Gbps to start.
*/
pGMACSWConfig->macInitCfg[i].macConnectionType =
MAC_CONNECTION_TYPE_RGMII_FORCE_1000_FULL;
#endif
}
pGMACSWConfig->linkStatusCallback = &LOCAL_linkStatus;
/* Return the config */
return pGMACSWConfig;
}
/*---------------------------------------------------------------------------*\
| Local Function Definitions |
\*---------------------------------------------------------------------------*/
/*
* LOCAL_linkStatus()
*
* This is a callback from the Ethernet driver. This function
* is called whenever there is a change in link state. The
* current PHY and current link state are passed as parameters.
*/
static void LOCAL_linkStatus( uint32_t phy, uint32_t linkStatus )
{
printf("Link Status: %s on PHY %" PRIu32 "\n",LinkStr[linkStatus],phy);
}
/*---------------------------------------------------------------------------*\
| End of File |
\*---------------------------------------------------------------------------*/
Due to I defined PAB_MII to 1 in Line72, the code slice(Line473~Line489) should be executed in "#if" section, not "#else" section. 1. #define PAB_MII (1) /* Eric: Modify for MII mode: #define PAB_MII (0) */ 2. #if ((PAB_MII == 1) || (PAB_RMII == 1)) /* * Adjust the PHY mask numbers for the Vayu PAB. The first MAC * port is connected to a PHY with address = 3, the second MAC * port is connected to a PHY with address = 2. */ // pGMACSWConfig->macInitCfg[i].phyMask = 0x1 << (3 - i); pGMACSWConfig->macInitCfg[i].phyMask = 0x1 << (2 - i); #else /* * Adjust the PHY mask numbers for the Vayu EVM. The first MAC * port is connected to a PHY with address = 2, the second MAC * port is connected to a PHY with address = 3. */ // pGMACSWConfig->macInitCfg[i].phyMask = 0x1 << (2 + i); pGMACSWConfig->macInitCfg[i].phyMask = 0x1 << (3 + i); #endif 3. remove all i/o delay setting for MII. I try to set PHY address mask to 2 or 3 (Line479 and Line480). But the result is the same. No PHY detect print. Are there any other registers I need to check?
Hello Eric, As registers shows your PHY is getting detected but NSP not able to detect PHY due to incorrect PHY mask. Change your PHY mask setting in vayu_init() to below pGMACSWConfig->macInitCfg[i].phyMask = 0x1 << i; This will set PHY correct PHY mask as your PHY address is 0 (first bit)
Hi Prasad, After change PHY mask setting in vayu_init.c pGMACSWConfig->macInitCfg[i].phyMask = 0x1 << i; Application can print PHY detect status. Log as follow: ----------------------------------------------------------------------------------My Board [Cortex_M4_IPU1_C0] MAC Port 0 Address: d0-b5-c2-5b-42-ee MAC Port 1 Address: d0-b5-c2-5b-42-ef GMACSW has been started successfully Registration of the GMACSW Successful Service Status: DHCPC : Enabled : : 000 Service Status: Telnet : Enabled : : 000 Service Status: HTTP : Enabled : : 000 Service Status: HTTP : Enabled : : 000 Service Status: DHCPC : Enabled : Running : 000 PHY: 0, NegMode 01E1, NWAYadvertise 01E1, NWAYREadvertise 43E1 Negotiated connection: FullDuplex 100 Mbs Link Status: 100Mb/s Full Duplex on PHY 0 <--------wait 50 seconds..... Service Status: DHCPC : Enabled : Fault : 002 <--------hang on this point. ---------------------------------------------------------------------------------Ti EVM [Cortex_M4_IPU1_C0] MAC Port 0 Address: d4-f5-13-b4-62-90 MAC Port 1 Address: d4-f5-13-b4-62-91 GMACSW has been started successfully Registration of the GMACSW Successful Service Status: DHCPC : Enabled : : 000 Service Status: Telnet : Enabled : : 000 Service Status: HTTP : Enabled : : 000 Service Status: HTTP : Enabled : : 000 Service Status: DHCPC : Enabled : Running : 000 PHY: 2, NegMode 01E1, NWAYadvertise 01E1, NWAYREadvertise 43E1 Negotiated connection: FullDuplex 100 Mbs Link Status: 100Mb/s Full Duplex on PHY 2 Network Added: If-1:192.168.213.7 <--------------Get IP from DHCP Service Status: DHCPC : Enabled : Running : 017 How can my board get IP from DHCP server like Ti EVM? Any register I need to set?
Eric, Ok, now that we are able to detect PHY, we can go ahead with data transfer debug. From logs as DHCP is faulting Rx/Tx is not happening correctly. Can you let me know contents of register 0x4848_4900 till 0x4848_498c (snapshot should be fine)
Hi Prasad, snapshot as follow:
Hello Eric, Data movement is not happening at all. This may be because of PAD not configured correctly or some board issue. Can you please cross check PAD values are correctly programmed in registers? Next step would be to probe rx/tx signals if any toggles happening there. Meanwhile check contents of registers 0x4848_4D84, 0x4848_4D88 & 0x4848_4DC4 & 0x4848_4DC8
Hi Prasad, I check PAD value. These setting are from TDA2xx_PAD_GmacSw_PAB_MDIO_Config and TDA2xx_PAD_GmacSw_PAB_MII0_Config in TDA2xx_pad_config.gel. It seems ok. ------------------------------------------------------------------------------------------- dp83848q tda2x pad Addr value MDC CTRL_CORE_PAD_VIN2A_D10 RW 32 0x0000 1590 0x4A00 3590 0x00030003 MDIO CTRL_CORE_PAD_VIN2A_D11 RW 32 0x0000 1594 0x4A00 3594 0x00070003 TXD_0 CTRL_CORE_PAD_RGMII0_RXD0 RW 32 0x0000 167C 0x4A00 367C 0x00010003 TXD_1 CTRL_CORE_PAD_RGMII0_RXD1 RW 32 0x0000 1678 0x4A00 3678 0x00010003 TXD_2 CTRL_CORE_PAD_RGMII0_RXD3 RW 32 0x0000 1670 0x4A00 3670 0x00010003 TXD_3 CTRL_CORE_PAD_RGMII0_RXCTL RW 32 0x0000 166C 0x4A00 366C 0x00010003 TX_EN CTRL_CORE_PAD_RGMII0_RXD2 RW 32 0x0000 1674 0x4A00 3674 0x00010003 TX_CLK CTRL_CORE_PAD_RGMII0_RXC RW 32 0x0000 1668 0x4A00 3668 0x00060003 TX_ER CTRL_CORE_PAD_MDIO_D RW 32 0x0000 1640 0x4A00 3640 0x00090003 RXD_0 CTRL_CORE_PAD_RGMII0_TXD0 RW 32 0x0000 1664 0x4A00 3664 0x00040003 RXD_1 CTRL_CORE_PAD_RGMII0_TXD1 RW 32 0x0000 1660 0x4A00 3660 0x00040003 RXD_3 CTRL_CORE_PAD_RGMII0_TXCTL RW 32 0x0000 1654 0x4A00 3654 0x00040003 RXD_3 CTRL_CORE_PAD_RGMII0_TXC RW 32 0x0000 1650 0x4A00 3650 0x00040003 RX_DV CTRL_CORE_PAD_UART3_RXD RW 32 0x0000 1648 0x4A00 3648 0x000C0003 CRS CTRL_CORE_PAD_RGMII0_TXD3 RW 32 0x0000 1658 0x4A00 3658 0x00040003 RX_CLK CTRL_CORE_PAD_UART3_TXD RW 32 0x0000 164C 0x4A00 364C 0x000E0003 RX_ER CTRL_CORE_PAD_RGMII0_TXD2 RW 32 0x0000 165C 0x4A00 365C 0x00040003 COL CTRL_CORE_PAD_MDIO_MCLK RW 32 0x0000 163C 0x4A00 363C 0x000C0003 The first column is PHY name and the second column is tda2xx pad name. --------------------------------------------------------------------------------- After connect Target(ran gel file) After ran client application. 0x4848_4D84 0x00000000 0x00008039 0x4848_4D88 0x80000000 0x00000000 0x4848_4DC4 0x00000000 0x00000039 0x4848_4DC8 0x80000000 0x00000000 I also attach pad register snapshot. I also probe dp83848q pin signal. I list it as follow: Signal MDC High/Low toggle MDIO High/Low toggle TXD_0 Low TXD_1 Low TXD_2 Low TXD_3 Low TX_EN Low TX_CLK High TX_ER xxx RXD_0 Low RXD_1 Low RXD_3 Low RXD_3 Low RX_DV Low CRS Low RX_CLK High RX_ER High COL Low
Hello Eric, 0x4848_4D88 should become non-zero after initialization. Only reason i see for that not happening is all pins not connected correctly. The signals you have probed are during idle time. What you have to do is run NSP example, put trigger for TX_EN and RX_DV and probe all other signals. See which all are toggling and which are not. I guess one of Pin might not be connected correctly or might have signal integrity issue etc. Are you using TDA2 EVM with MII PHY daughter board? Also what is your end application? is this for industrial use-case? Let me know. Meanwhile I will see if we can move this post to private E2E so i can share some NDA files for debug. Will let you know.
Hi Prasad, About Pin connection issue, I will re-probe these pins (TX_EN and RX_DV and probe all other signals) from the "client" application start state to idle state and attach later. Are you using TDA2 EVM with MII PHY daughter board? Also what is your end application? is this for industrial use-case? -> No, I am using my board (our EE member design) with tda2xx and MII PHY. Not TDA2x EVM. -> For AVM application. ->No, for automotive. Meanwhile I will see if we can move this post to private E2E so i can share some NDA files for debug. Will let you know. -> Yes, but how?
Hello Eric, Thanks for info. Though none of my concern I was wondering why in Automotive use-case you are using MII mode. Please confirm in schematic if all MII signals are connected correctly on your board. From my earlier experience this kind of issue can only come because of two reasons. 1. PAD Cfg not correct, which you have cross checked. 2. Board connection for data/control pin not done correctly. The CRC, alignment errors are due the delays and link stability but in your case we dont see any packet movement happening so we are not at this place yet. Anyway can you please contact your FAE/TI sales Support to get private E2E support? I have Ethernet debug test with which we can connect to Wireshark and analyse packet contents i can share.
Hi Prasad, Attach the wave form of each pin for MII mode. I probed these pins from "client" application start to "client" application enter idle state. Except MDC and MDIO show H/L toggle, the other pin have no change and keep the same state. Phy pin Signal MDC High/Low toggle MDIO High/Low toggle TXD_0 Low TXD_1 Low TXD_2 Low TXD_3 Low TX_EN Low TX_CLK High TX_ER xxx RXD_0 Low RXD_1 Low RXD_3 Low RXD_3 Low RX_DV Low CRS Low RX_CLK High RX_ER High COL Low
Hello Eric, MII data pins not toggling only suggests that board has some routing issue and signal not reaching PHY. At what point you are probing these signals? At PHY boundary or at TDA2 boundary? Also for enabling error frames processing add below line in vayu_init.c in function GMACSW_getConfig (line 472) pGMACSWConfig->macInitCfg[i].macModeFlags |= MAC_CONFIG_MODEFLG_PASSERROR | /* enable RX_CMF*/ MAC_CONFIG_MODEFLG_PASSCONTROL; /* enable RX_CSF,RX_CEF*/ Please check contents of 0x4848_4900 after this change. Many chances that it will be still non-zero but let us see. Also you can remove MDIO pins from probes as we know those are working. Regards, Prasad
Hi Prasad, I probe these signals at PHY boundary. I also enable error frames processing in line 472. 0x4848_4900 have no change (at before and after running client application and idle state).
Eric, You should probe signals at TDA2 boundary. I am suspecting the signal not reaching to PHY from TDA2 (issue in routing between TDA2 to PHY). Also I have asked your FAE if you can share board schematic.
Hi Prasad, I will ask our EE member to probe PHY boundary. About board schematic, I mail to you.
Just to confirm you mean TDA2 boundary right?
Hi Prasad, This is Jack and I would like to show you the presence of the resistors on the board via a picture. regards, Jack
Hello Jack, You can send picture on my mail id. Regards, Prasad
Hello Eric, The DP83848 PHY when not configured through bootstraping for changing PHY address, takes PHY address 0 as default address. Also when all PHY ADDR bit (PHY_ADR0/4) are zero it works in MII isolate mode. This is causing data transfer not to happen. Change PHY address to 0x1 or any non-zero to remove MII isolate mode. This can be also be done through MDIO but through bootstraping is preferable.
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