| Ticket Name: TDA2SX: Interfacing ADV7393 with TDA2x DSS | |
| Query Text: | |
| Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi, I want to use ADV7393 to get PAL output at my video output port from TDA2x DSS. I have made the schematics. I just want to get a review of this schematic. I have connected D0 to D15 to P0 to P15 of the encoder. The reset I am using is generated by a programmable delay IC. HS is directly from VOUT1 to HS of ADV. As far as VS is concerned, I have added the D-FLIP FLOPs (to delay FLD) as suggested by appnote and connected the output to VS of ADV. Kindly review my schematics (I have attached) and suggest any change (if any) so that I could finalize my design. | |
| Responses: | |
| Could you clarify which application note you are referring (for delayed FLD)? | |
| DSS BT656 Workaround for TDA2x https://www.ti.com/lit/pdf/sprac23 | |
| Are you using RGB565? Need to verify the data bits assignments are aligned. For the processor I believe organization is: For transceiver: | |
| Ad App note suggests, use RGB565 with R on 0 to 4, G on 5 to 10 and B on 11:15 on Adv7393 side. On Tda2x DSS side, I will send BGR16_565. The format will be interlaced. | |
| On the ADV device R is 0 to 4, on the TI side R is 11 to 15. So D0 will not connect to D0. Does your schematic account for this? | |
| As you see app note says connect lower 16 lines for RGB565. Now as far as DSS is concerned, I'll send BGR565. BGR565 means R is on 0 to 4. | |
| This is the table I'm referring to in the TDA2 TRM: | |
| That's exactly I'm saying that's for RGB, for BGR it would be reverse. When you send BGR it should be R on 0 to 4, G on 5 to 10, and B on 11 to 15. I'm intending to send BGR16_565 from DSS inside my chains_common.c | |
| Hi Assad, I think since the bit size is same, it does not matter as long as RGB data lines are correctly connected to the expected data lines of ADV, isn't it? Regards, Brijesh | |
| I'm confused on some points. Let's dicsuss one by one: 1. DSS workaround for tda2x says that send RGB565 over the DSS. Now RGB565 configuration is B[0:4], G[5:10], R[11:15]. On Adv7393 side, it says send R on 0 to 4, G on 5 to 10 and B on 11 to 15. Now what should I do, should I connect it like this? DSS - > Adv7393 D0:4 -> P11:15 D5:10 -> P5:10 D11:15 - > P0:4 Or should I connect D0:15 to P0:15 one to one and send BGR16_565 from DSS. Can I do that from DSS Point of view? Pls answer regarding both situations? I'm finalizing after your input. | |
| Hi, You should do connection based on the correct component ordering, which i think is #1 above. DSS - > Adv7393 D0:4 -> P11:15 D5:10 -> P5:10 D11:15 - > P0:4 Regards, Brijesh | |
| Thanks, I will modify it. 2. The delay circuit which I have used to delay FLD signals. Is this routed correctly. As app note says the delay cct is for adv7343 but we're using adv7393. So it will work in the same scheme as adv7343 right? | |
| Assad Sultan said: 2. The delay circuit which I have used to delay FLD signals. Is this routed correctly. As app note says the delay cct is for adv7343 but we're using adv7393. So it will work in the same scheme as adv7343 right? I think so. If i remember, we checked it sometimes back and even ADV7343 requires slight delay. Regards, Brijesh | |
| Thanks. I'm left with configuration in vision sdk. I am trying to test pipeline on EVM just to see if there's no error thrown (I'll bypass the i2c part) when I run the application ( I know there will be no output as EVM doesn't have this IC). I'll report back here tomorrow. 3) I'll use the following setting: (chains_common.c) Data format: RGb16_565 IF width: 16 bit Interlaced and standard PAL Sync: Discrete Sync (Is there any additional setting required?) 4) But I have a confusion. Where can I set tftdatalines (in register programming - appnote) inside vision sdk. I can't find the relevant section of code. Can you tell me where I need to modify the disp control register and which setting exactly to cater TFtDatalines and colorenvenable? | |
| Assad Sultan said: Sync: Discrete Sync (Is there any additional setting required?) Yes, because output interface is discrete sync interface with RGB565, isn't it? Assad Sultan said: 4) But I have a confusion. Where can I set tftdatalines (in register programming - appnote) inside vision sdk. I can't find the relevant section of code. Can you tell me where I need to modify the disp control register and which setting exactly to cater TFtDatalines and colorenvenable? I think this is somewhere in the chains_common.c file, where display controller is configured. There should be an ioctl for overlay manager to allow configuring tdm mode. Regards, Brijesh | |
| As far as TDM configuration is concerned it's inside displayCtrlLink_drv.c file where it can be set. But I'm confused about tftdatalines. I can't find any trace to set it. Do I have to set it manually to 0x1 (As app note says it). Or is it somewhere set on a higher level and catered by driver itself? See attachment: | |
| You can directly write to register or use driver ioctl interface to write in this file. Regards, Brijesh | |
| How can I directly write? WHERE is that source file located? I tried, I couldn't find. | |
| I think the application note also provides the driver example setting. Plese use this in chains_main.c or displayctrl_link.c file to enable TDM mode. Regards, Brijesh | |
| Hi Brijesh? As I said that I know the place where I could enable Tdm mode. But in section 2.1.3.1 Register Programming, it's asking for tftdatalines to set 0x1. But displayCtrlLink_drv.c doesn't have such thing as said in appnote. | |
| Hi, The API DisplayCtrlLink_drvSetConfig in the displayCtrl_drv.c file can be used for this purpose. This API calls both the ioctls, IOCTL_VPS_DCTRL_SET_VENC_OUTPUT, where we can set the output information and IOCTL_VPS_DCTRL_DSS_SET_ADV_VENC_TDM_PARAMS, where we can enable TDM. Regards, Brijesh | |
| Sorry if I'm not conveying what I want to say. I know where I can enable Tdm. There's another thing which is TFtdatalines which is to be set to 0x1. It's not in driver file. I'm asking about that. As you can see the register programing section below. I am asking about the first two lines. Where I can set them? DISP_CONFIG1.TFTDATALINES = 0x1; DISP_CONFIG1.COLORENVENABLWE=0x0; These two. | |
| Hi, Tftdatalines is set to 1 when VideoIfWidth is set to 16bit in the output information structure. Regards, Brijesh | |
| Okay. This section of register programming isn't applicable. I just have to change driver related setting related to IFwidth and tdm setting. Right? | |
| Hi, Yep that's correct. Please use driver interface, then you dont need to write directly to register(s). Regards, Brijesh | |
| I'll test the application flow on Evm and report back. | |
| Sure thanks, i will move this ticket to waiting state. To reopen, simply reply on the ticket. | |
| Hi Brijesh! My next question is: Inside chains_common.c where we set the parameters. Now my data scan format is set to interlaced and I'm using custom standard. clock is 27 mhz and width height is 720x576. Mode is RGB16_565. But I'm confused regrading these parameters that how can I set these values? fps = 30U; hFrontPorch = 40u; hBackPorch = 40u; hSyncLen = 48u; vFrontPorch = 13u; vBackPorch = 29u; vSyncLen = 3u; Note : These values are just take from LCD7 inch setting. | |
| Hi, Please refer to blanking timing in LCD specs and set the same in these fields. Regards, Brijesh | |
| Which LCD? Sorry I didn't understand. Do you mean copy the values from lcd7 inch code? | |
| Assad Sultan said: Note : These values are just take from LCD7 inch setting. Please refer to the specs of this LCD. it should have timing in it and that you need to use configure here. Regards, Brijesh | |
| But I'm not using that lcd, I'm configuring it for adv7393. Will it work? | |
| Well these are configurable parameters and please check with your receiver device, what's its requirement. I can't tell what needs to be configured, so can't help you further in this case. Regards, Brijesh | |
| I always study the background and then ask here. As there are some confusion points I wanted to clear. I'll set these parameters by hit and trial as adv7393 datasheet doesn't have any information regarding those. There's one more thing I need your input. As the app note says use timing mode 1 and delay Fid signal. I studied this thing and consulted with the vendor for register setting of adv7393. I have attched the table of setting for SD input mode with RGb16 input. It says Set timing mode to 2 where HSync and Vsync are used but app note says otherwise (using delayed fid and timing mode 1). So is thing tested with rgb input and timing mode 1? pls guide. | |
| I would suggest to go by what ADV says. Regards, Brijesh | |
| Hi Brijesh! Thanks for getting back. If I use mode 2, there's the confusion. Mode 2 uses HSync and Vsync while mode 1 uses hsync and fid. So in mode 2 case, delay of fid and then using it on vsync would not work. In that case, I need to delay Vsync signal coming from DSS. What do you say? | |
| Hi, But HS and VS output is not compatible with the requirement. DSS cannot generate the VS as required for the interlaced output. So please use mode-1 only, where ADV uses HS and FID input signal. Regards, Brijesh | |
| I'll take a note of it. I'll use HS from DSS directly and fid delayed to vs. And try to set the register to mode 1. I'll see if I get the output. Pls confirm that Hs will be tied directly to Hs right? that's all for now. When I get my HW ready, I'll open a thread then. Thanks | |
| Yep, HS should be directly connected. Regards, Brijesh | |