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| gpl-2.0 | 60c056b5abda067aa4c7796ab5260183 | 0.924254 | 1.90882 | false | false | false | false |
notti/dis_se | vhdl/complex_alu.vhd | 1 | 3,203 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.procedures.all;
entity complex_alu is
port(
clk : in std_logic;
a : in t_data;
b : in t_data;
op : in std_logic_vector(2 downto 0);
point : in std_logic_vector(2 downto 0);
c : out t_data
);
end complex_alu;
architecture Structural of complex_alu is
signal imm_c : t_data;
signal umul_c : t_data;
signal smul_c : t_data;
signal umul : std_logic_vector(t_data'high*2+1 downto 0);
signal smul : std_logic_vector(t_data'high*2+1 downto 0);
signal umulshift : std_logic_vector(t_data'high*2+1 downto 0);
signal smulshift : std_logic_vector(t_data'high*2+1 downto 0);
signal point_1 : std_logic_vector(2 downto 0);
signal op_1 : std_logic_vector(2 downto 0);
signal umul_p : unsigned(0 downto 0);
signal smul_p : unsigned(0 downto 0);
begin
p: process(clk)
begin
if rising_edge(clk) then
point_1 <= point;
op_1 <= op;
end if;
end process p;
ashift: entity work.shift_ra
port map(
a => smul,
b => point_1,
c => smulshift
);
lshift: entity work.shift_rl
port map(
a => umul,
b => point_1,
c => umulshift
);
umul_p(0) <= umul(6) when point_1 = "111" else
umul(5) when point_1 = "110" else
umul(4) when point_1 = "101" else
umul(3) when point_1 = "100" else
umul(2) when point_1 = "011" else
umul(1) when point_1 = "010" else
umul(0) when point_1 = "001" else
'0';
smul_p(0) <= smul(6) when point_1 = "111" else
smul(5) when point_1 = "110" else
smul(4) when point_1 = "101" else
smul(3) when point_1 = "100" else
smul(2) when point_1 = "011" else
smul(1) when point_1 = "010" else
smul(0) when point_1 = "001" else
'0';
umul_c <= std_logic_vector(unsigned(umulshift(t_data'range)) + umul_p);
smul_c <= std_logic_vector(unsigned(smulshift(t_data'range)) + smul_p);
alu: process(clk)
begin
if rising_edge(clk) then
umul <= std_logic_vector(unsigned(a) * unsigned(b));
smul <= std_logic_vector(signed(a) * signed(b));
case op is
when CALU_ADD =>
imm_c <= std_logic_vector(unsigned(a) + unsigned(b));
when CALU_SUB =>
imm_c <= std_logic_vector(unsigned(a) - unsigned(b));
when CALU_AND =>
imm_c <= a and b;
when CALU_OR =>
imm_c <= a or b;
when CALU_XOR =>
imm_c <= a xor b;
when others =>
imm_c <= (others => '0');
end case;
case op_1 is
when CALU_ADD | CALU_SUB | CALU_AND | CALU_OR | CALU_XOR =>
c <= imm_c;
when CALU_UMUL =>
c <= umul_c;
when CALU_SMUL =>
c <= smul_c;
when others =>
c <= (others => '0');
end case;
end if;
end process alu;
end Structural;
| bsd-2-clause | ab4a514fa72e48fee27bf3149fdeba3c | 0.511708 | 3.16815 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab2/Combined[old]/DC_CTL.vhd | 1 | 2,240 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:52:59 03/25/2016
-- Design Name:
-- Module Name: DC_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DC_CTL is
Port ( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (3 downto 0);
RB : in STD_LOGIC_VECTOR (3 downto 0);
RA0 : in STD_LOGIC_VECTOR (3 downto 0);
RA1 : in STD_LOGIC_VECTOR (3 downto 0);
RA2 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB0 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB1 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB2 : in STD_LOGIC_VECTOR (3 downto 0);
OPC : in STD_LOGIC_VECTOR (3 downto 0);
OP1_SEL : out STD_LOGIC_VECTOR (1 downto 0);
OP2_SEL : out STD_LOGIC_VECTOR (1 downto 0));
end DC_CTL;
architecture Mixed of DC_CTL is
signal OP1, OP2 : STD_LOGIC_VECTOR (1 downto 0) := (OTHERS => '0');
begin
process(RA, RB, RA0, RA1, RA2)
begin
-- if (rising_edge(CLK)) then
if (RA = RA0) then
OP1 <= "01";
-- OP1_SEL <= OP1;
elsif (RA = RA1) then
OP1 <= "10";
-- OP1_SEL <= OP1;
elsif (RA = RA2) then
OP1 <= "11";
-- OP1_SEL <= OP1;
else
OP1 <= "00";
-- OP1_SEL <= OP1;
end if;
-- OP1_SEL <= OP1;
if (RB = RA0) then
OP2 <= "01";
elsif (RB = RA1) then
OP2 <= "10";
elsif (RB = RA2) then
OP2 <= "11";
else
OP2 <= "00";
end if;
-- end if;
end process;
OP1_SEL <= OP1;
with OPC select OP2_SEL <=
OP2 when "0000" | "0001" | "0010" | "0011" | "0100",
"00" when OTHERS;
end Mixed;
| gpl-3.0 | ee6d5c4434ab8aad24afde4480d43db6 | 0.523214 | 2.966887 | false | false | false | false |
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`protect end_protected
| gpl-2.0 | 27e97a708910c674aa8d0f40c49e3e68 | 0.928092 | 1.897737 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/floating_point_v7_0/hdl/flt_sqrt/flt_sqrt.vhd | 2 | 21,736 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 14352)
`protect data_block
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`protect end_protected
| gpl-2.0 | 87ce883563b0b7e474b2c2b456993cc8 | 0.942078 | 1.851133 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xfft_v9_0/hdl/r22_twos_comp_mux.vhd | 3 | 10,258 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5856)
`protect data_block
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`protect end_protected
| gpl-2.0 | 49e0e0ba73fad28302f15bde9cc47ae1 | 0.926301 | 1.891573 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/multi_fft/xbip_utils_v3_0/hdl/xbip_utils_v3_0_pkg.vhd | 14 | 141,590 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 103072)
`protect data_block
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`protect end_protected
| gpl-2.0 | 90e91bac88a28ff32afc2526fcd73784 | 0.953711 | 1.812654 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/floating_point_v7_0/hdl/flt_log/flt_log_single_one_detect.vhd | 2 | 9,764 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5488)
`protect data_block
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`protect end_protected
| gpl-2.0 | 52ca021741901f3c72b0d79ecf1eacc5 | 0.923699 | 1.91978 | false | false | false | false |
mcoughli/root_of_trust | experiments/secure_filesystem/secure_filesystem_hls/solution1/syn/vhdl/filesystem_encrypt.vhd | 1 | 563,411 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity filesystem_encrypt is
generic (
C_M_AXI_BUFFER_V_ADDR_WIDTH : INTEGER := 32;
C_M_AXI_BUFFER_V_ID_WIDTH : INTEGER := 1;
C_M_AXI_BUFFER_V_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUFFER_V_DATA_WIDTH : INTEGER := 128;
C_M_AXI_BUFFER_V_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUFFER_V_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUFFER_V_RUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUFFER_V_BUSER_WIDTH : INTEGER := 1;
C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_AXILITES_DATA_WIDTH : INTEGER := 32;
C_M_AXI_BUFFER_V_CACHE_VALUE : INTEGER := 3;
C_M_AXI_BUFFER_V_USER_VALUE : INTEGER := 0;
C_M_AXI_BUFFER_V_PROT_VALUE : INTEGER := 0;
C_M_AXI_BUFFER_V_TARGET_ADDR : INTEGER := 0 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
m_axi_buffer_V_AWVALID : OUT STD_LOGIC;
m_axi_buffer_V_AWREADY : IN STD_LOGIC;
m_axi_buffer_V_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_BUFFER_V_ADDR_WIDTH-1 downto 0);
m_axi_buffer_V_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_BUFFER_V_ID_WIDTH-1 downto 0);
m_axi_buffer_V_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
m_axi_buffer_V_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_buffer_V_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_buffer_V_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_buffer_V_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_buffer_V_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_buffer_V_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_buffer_V_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_buffer_V_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_BUFFER_V_AWUSER_WIDTH-1 downto 0);
m_axi_buffer_V_WVALID : OUT STD_LOGIC;
m_axi_buffer_V_WREADY : IN STD_LOGIC;
m_axi_buffer_V_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_BUFFER_V_DATA_WIDTH-1 downto 0);
m_axi_buffer_V_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_BUFFER_V_DATA_WIDTH/8-1 downto 0);
m_axi_buffer_V_WLAST : OUT STD_LOGIC;
m_axi_buffer_V_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_BUFFER_V_ID_WIDTH-1 downto 0);
m_axi_buffer_V_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_BUFFER_V_WUSER_WIDTH-1 downto 0);
m_axi_buffer_V_ARVALID : OUT STD_LOGIC;
m_axi_buffer_V_ARREADY : IN STD_LOGIC;
m_axi_buffer_V_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_BUFFER_V_ADDR_WIDTH-1 downto 0);
m_axi_buffer_V_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_BUFFER_V_ID_WIDTH-1 downto 0);
m_axi_buffer_V_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
m_axi_buffer_V_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_buffer_V_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_buffer_V_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_buffer_V_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_buffer_V_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_buffer_V_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_buffer_V_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_buffer_V_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_BUFFER_V_ARUSER_WIDTH-1 downto 0);
m_axi_buffer_V_RVALID : IN STD_LOGIC;
m_axi_buffer_V_RREADY : OUT STD_LOGIC;
m_axi_buffer_V_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_BUFFER_V_DATA_WIDTH-1 downto 0);
m_axi_buffer_V_RLAST : IN STD_LOGIC;
m_axi_buffer_V_RID : IN STD_LOGIC_VECTOR (C_M_AXI_BUFFER_V_ID_WIDTH-1 downto 0);
m_axi_buffer_V_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUFFER_V_RUSER_WIDTH-1 downto 0);
m_axi_buffer_V_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_buffer_V_BVALID : IN STD_LOGIC;
m_axi_buffer_V_BREADY : OUT STD_LOGIC;
m_axi_buffer_V_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_buffer_V_BID : IN STD_LOGIC_VECTOR (C_M_AXI_BUFFER_V_ID_WIDTH-1 downto 0);
m_axi_buffer_V_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUFFER_V_BUSER_WIDTH-1 downto 0);
key_V : IN STD_LOGIC_VECTOR (127 downto 0);
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH/8-1 downto 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0) );
end;
architecture behav of filesystem_encrypt is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"filesystem_encrypt,hls_ip_2017_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xczu9eg-ffvb1156-1-i-es1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.750000,HLS_SYN_LAT=78850,HLS_SYN_TPT=none,HLS_SYN_MEM=116,HLS_SYN_DSP=0,HLS_SYN_FF=7073,HLS_SYN_LUT=17302}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000001";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000010";
constant ap_ST_fsm_pp0_stage1 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000100";
constant ap_ST_fsm_pp0_stage2 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000001000";
constant ap_ST_fsm_pp0_stage3 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000010000";
constant ap_ST_fsm_pp0_stage4 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000100000";
constant ap_ST_fsm_pp0_stage5 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000001000000";
constant ap_ST_fsm_pp0_stage6 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000010000000";
constant ap_ST_fsm_pp0_stage7 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000100000000";
constant ap_ST_fsm_pp0_stage8 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000001000000000";
constant ap_ST_fsm_pp0_stage9 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000010000000000";
constant ap_ST_fsm_pp0_stage10 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000100000000000";
constant ap_ST_fsm_pp0_stage11 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000001000000000000";
constant ap_ST_fsm_pp0_stage12 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000010000000000000";
constant ap_ST_fsm_pp0_stage13 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000100000000000000";
constant ap_ST_fsm_pp0_stage14 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001000000000000000";
constant ap_ST_fsm_pp0_stage15 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000000000000000010000000000000000";
constant ap_ST_fsm_pp0_stage16 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000000000000000100000000000000000";
constant ap_ST_fsm_pp0_stage17 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000000000000001000000000000000000";
constant ap_ST_fsm_pp0_stage18 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000000000000010000000000000000000";
constant ap_ST_fsm_pp0_stage19 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000000000000100000000000000000000";
constant ap_ST_fsm_pp0_stage20 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000000000001000000000000000000000";
constant ap_ST_fsm_pp0_stage21 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000000000010000000000000000000000";
constant ap_ST_fsm_pp0_stage22 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000000000100000000000000000000000";
constant ap_ST_fsm_pp0_stage23 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000000001000000000000000000000000";
constant ap_ST_fsm_pp0_stage24 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000000010000000000000000000000000";
constant ap_ST_fsm_pp0_stage25 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000000100000000000000000000000000";
constant ap_ST_fsm_pp0_stage26 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000001000000000000000000000000000";
constant ap_ST_fsm_pp0_stage27 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000010000000000000000000000000000";
constant ap_ST_fsm_pp0_stage28 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000100000000000000000000000000000";
constant ap_ST_fsm_pp0_stage29 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000001000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage30 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000010000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage31 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000100000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage32 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000001000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage33 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000010000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage34 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000100000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage35 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000001000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage36 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000010000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage37 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000100000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage38 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000001000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage39 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000010000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage40 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000100000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage41 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000001000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage42 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000010000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage43 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000100000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage44 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000001000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage45 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000010000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage46 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000100000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage47 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000001000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage48 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000010000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage49 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000100000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage50 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000001000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage51 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000010000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage52 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000100000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage53 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000001000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage54 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000010000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage55 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000100000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage56 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000001000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage57 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000010000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage58 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000100000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage59 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000001000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage60 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000010000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage61 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000100000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage62 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000001000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage63 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000010000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage64 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000100000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage65 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000001000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage66 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000010000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage67 : STD_LOGIC_VECTOR (78 downto 0) := "0000000000100000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage68 : STD_LOGIC_VECTOR (78 downto 0) := "0000000001000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage69 : STD_LOGIC_VECTOR (78 downto 0) := "0000000010000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage70 : STD_LOGIC_VECTOR (78 downto 0) := "0000000100000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage71 : STD_LOGIC_VECTOR (78 downto 0) := "0000001000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage72 : STD_LOGIC_VECTOR (78 downto 0) := "0000010000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage73 : STD_LOGIC_VECTOR (78 downto 0) := "0000100000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage74 : STD_LOGIC_VECTOR (78 downto 0) := "0001000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage75 : STD_LOGIC_VECTOR (78 downto 0) := "0010000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage76 : STD_LOGIC_VECTOR (78 downto 0) := "0100000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_state80 : STD_LOGIC_VECTOR (78 downto 0) := "1000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011";
constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100";
constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_21 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100001";
constant ap_const_lv32_22 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100010";
constant ap_const_lv32_23 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100011";
constant ap_const_lv32_24 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100100";
constant ap_const_lv32_25 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100101";
constant ap_const_lv32_26 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100110";
constant ap_const_lv32_27 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100111";
constant ap_const_lv32_28 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101000";
constant ap_const_lv32_29 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101001";
constant ap_const_lv32_2A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101010";
constant ap_const_lv32_2B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101011";
constant ap_const_lv32_2C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101100";
constant ap_const_lv32_2D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101101";
constant ap_const_lv32_2E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101110";
constant ap_const_lv32_2F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101111";
constant ap_const_lv32_30 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110000";
constant ap_const_lv32_31 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110001";
constant ap_const_lv32_32 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110010";
constant ap_const_lv32_33 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110011";
constant ap_const_lv32_34 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110100";
constant ap_const_lv32_35 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110101";
constant ap_const_lv32_36 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110110";
constant ap_const_lv32_37 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110111";
constant ap_const_lv32_38 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111000";
constant ap_const_lv32_39 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111001";
constant ap_const_lv32_3A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111010";
constant ap_const_lv32_3B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111011";
constant ap_const_lv32_3C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111100";
constant ap_const_lv32_3D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111101";
constant ap_const_lv32_3E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111110";
constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111";
constant ap_const_lv32_40 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000000";
constant ap_const_lv32_41 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000001";
constant ap_const_lv32_42 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000010";
constant ap_const_lv32_43 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000011";
constant ap_const_lv32_44 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000100";
constant ap_const_lv32_45 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000101";
constant ap_const_lv32_46 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000110";
constant ap_const_lv32_47 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000111";
constant ap_const_lv32_48 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001000";
constant ap_const_lv32_49 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001001";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant C_M_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_4D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001101";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_lv64_2 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000010";
constant ap_const_lv64_3 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000011";
constant ap_const_lv64_4 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000100";
constant ap_const_lv64_5 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000101";
constant ap_const_lv64_6 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000110";
constant ap_const_lv64_7 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000111";
constant ap_const_lv64_8 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001000";
constant ap_const_lv64_9 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001001";
constant ap_const_lv64_A : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001010";
constant ap_const_lv64_B : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001011";
constant ap_const_lv64_C : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001100";
constant ap_const_lv64_D : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001101";
constant ap_const_lv64_E : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001110";
constant ap_const_lv64_F : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001111";
constant ap_const_lv64_10 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010000";
constant ap_const_lv64_11 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010001";
constant ap_const_lv64_12 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010010";
constant ap_const_lv64_13 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010011";
constant ap_const_lv64_14 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010100";
constant ap_const_lv64_15 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010101";
constant ap_const_lv64_16 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010110";
constant ap_const_lv64_17 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010111";
constant ap_const_lv64_18 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000011000";
constant ap_const_lv64_19 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000011001";
constant ap_const_lv64_1A : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000011010";
constant ap_const_lv64_1B : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000011011";
constant ap_const_lv64_1C : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000011100";
constant ap_const_lv64_1D : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000011101";
constant ap_const_lv64_1E : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000011110";
constant ap_const_lv64_1F : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000011111";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv16_FFFF : STD_LOGIC_VECTOR (15 downto 0) := "1111111111111111";
constant ap_const_lv15_1 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000001";
constant ap_const_lv15_2 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000010";
constant ap_const_lv15_3 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000011";
constant ap_const_lv15_4 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000100";
constant ap_const_lv15_5 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000101";
constant ap_const_lv15_6 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000110";
constant ap_const_lv15_7 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000111";
constant ap_const_lv15_8 : STD_LOGIC_VECTOR (14 downto 0) := "000000000001000";
constant ap_const_lv15_9 : STD_LOGIC_VECTOR (14 downto 0) := "000000000001001";
constant ap_const_lv15_A : STD_LOGIC_VECTOR (14 downto 0) := "000000000001010";
constant ap_const_lv15_B : STD_LOGIC_VECTOR (14 downto 0) := "000000000001011";
constant ap_const_lv15_C : STD_LOGIC_VECTOR (14 downto 0) := "000000000001100";
constant ap_const_lv15_D : STD_LOGIC_VECTOR (14 downto 0) := "000000000001101";
constant ap_const_lv15_E : STD_LOGIC_VECTOR (14 downto 0) := "000000000001110";
constant ap_const_lv15_F : STD_LOGIC_VECTOR (14 downto 0) := "000000000001111";
constant ap_const_lv15_10 : STD_LOGIC_VECTOR (14 downto 0) := "000000000010000";
constant ap_const_lv15_11 : STD_LOGIC_VECTOR (14 downto 0) := "000000000010001";
constant ap_const_lv15_12 : STD_LOGIC_VECTOR (14 downto 0) := "000000000010010";
constant ap_const_lv15_13 : STD_LOGIC_VECTOR (14 downto 0) := "000000000010011";
constant ap_const_lv15_14 : STD_LOGIC_VECTOR (14 downto 0) := "000000000010100";
constant ap_const_lv15_15 : STD_LOGIC_VECTOR (14 downto 0) := "000000000010101";
constant ap_const_lv15_16 : STD_LOGIC_VECTOR (14 downto 0) := "000000000010110";
constant ap_const_lv15_17 : STD_LOGIC_VECTOR (14 downto 0) := "000000000010111";
constant ap_const_lv15_18 : STD_LOGIC_VECTOR (14 downto 0) := "000000000011000";
constant ap_const_lv15_19 : STD_LOGIC_VECTOR (14 downto 0) := "000000000011001";
constant ap_const_lv15_1A : STD_LOGIC_VECTOR (14 downto 0) := "000000000011010";
constant ap_const_lv15_1B : STD_LOGIC_VECTOR (14 downto 0) := "000000000011011";
constant ap_const_lv15_1C : STD_LOGIC_VECTOR (14 downto 0) := "000000000011100";
constant ap_const_lv15_1D : STD_LOGIC_VECTOR (14 downto 0) := "000000000011101";
constant ap_const_lv15_1E : STD_LOGIC_VECTOR (14 downto 0) := "000000000011110";
constant ap_const_lv15_1F : STD_LOGIC_VECTOR (14 downto 0) := "000000000011111";
constant ap_const_lv16_20 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000100000";
constant ap_const_lv32_4E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001110";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (78 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal iv_V : STD_LOGIC_VECTOR (127 downto 0);
signal length_r : STD_LOGIC_VECTOR (31 downto 0);
signal length_r_preg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal length_r_ap_vld : STD_LOGIC;
signal length_r_in_sig : STD_LOGIC_VECTOR (31 downto 0);
signal length_r_ap_vld_preg : STD_LOGIC := '0';
signal length_r_ap_vld_in_sig : STD_LOGIC;
signal buffer_V_blk_n_AR : STD_LOGIC;
signal ap_CS_fsm_pp0_stage1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage1 : signal is "none";
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal ap_block_pp0_stage1_flag00000000 : BOOLEAN;
signal tmp_reg_1932 : STD_LOGIC_VECTOR (0 downto 0);
signal buffer_V_blk_n_R : STD_LOGIC;
signal ap_CS_fsm_pp0_stage8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage8 : signal is "none";
signal ap_block_pp0_stage8_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage9 : signal is "none";
signal ap_block_pp0_stage9_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage10 : signal is "none";
signal ap_block_pp0_stage10_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage11 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage11 : signal is "none";
signal ap_block_pp0_stage11_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage12 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage12 : signal is "none";
signal ap_block_pp0_stage12_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage13 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage13 : signal is "none";
signal ap_block_pp0_stage13_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage14 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage14 : signal is "none";
signal ap_block_pp0_stage14_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage15 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage15 : signal is "none";
signal ap_block_pp0_stage15_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage16 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage16 : signal is "none";
signal ap_block_pp0_stage16_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage17 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage17 : signal is "none";
signal ap_block_pp0_stage17_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage18 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage18 : signal is "none";
signal ap_block_pp0_stage18_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage19 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage19 : signal is "none";
signal ap_block_pp0_stage19_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage20 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage20 : signal is "none";
signal ap_block_pp0_stage20_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage21 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage21 : signal is "none";
signal ap_block_pp0_stage21_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage22 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage22 : signal is "none";
signal ap_block_pp0_stage22_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage23 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage23 : signal is "none";
signal ap_block_pp0_stage23_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage24 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage24 : signal is "none";
signal ap_block_pp0_stage24_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage25 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage25 : signal is "none";
signal ap_block_pp0_stage25_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage26 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage26 : signal is "none";
signal ap_block_pp0_stage26_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage27 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage27 : signal is "none";
signal ap_block_pp0_stage27_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage28 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage28 : signal is "none";
signal ap_block_pp0_stage28_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage29 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage29 : signal is "none";
signal ap_block_pp0_stage29_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage30 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage30 : signal is "none";
signal ap_block_pp0_stage30_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage31 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage31 : signal is "none";
signal ap_block_pp0_stage31_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage32 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage32 : signal is "none";
signal ap_block_pp0_stage32_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage33 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage33 : signal is "none";
signal ap_block_pp0_stage33_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage34 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage34 : signal is "none";
signal ap_block_pp0_stage34_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage35 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage35 : signal is "none";
signal ap_block_pp0_stage35_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage36 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage36 : signal is "none";
signal ap_block_pp0_stage36_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage37 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage37 : signal is "none";
signal ap_block_pp0_stage37_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage38 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage38 : signal is "none";
signal ap_block_pp0_stage38_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage39 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage39 : signal is "none";
signal ap_block_pp0_stage39_flag00000000 : BOOLEAN;
signal buffer_V_blk_n_AW : STD_LOGIC;
signal ap_CS_fsm_pp0_stage40 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage40 : signal is "none";
signal ap_block_pp0_stage40_flag00000000 : BOOLEAN;
signal buffer_V_blk_n_W : STD_LOGIC;
signal ap_CS_fsm_pp0_stage41 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage41 : signal is "none";
signal ap_block_pp0_stage41_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage42 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage42 : signal is "none";
signal ap_block_pp0_stage42_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage43 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage43 : signal is "none";
signal ap_block_pp0_stage43_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage44 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage44 : signal is "none";
signal ap_block_pp0_stage44_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage45 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage45 : signal is "none";
signal ap_block_pp0_stage45_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage46 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage46 : signal is "none";
signal ap_block_pp0_stage46_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage47 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage47 : signal is "none";
signal ap_block_pp0_stage47_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage48 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage48 : signal is "none";
signal ap_block_pp0_stage48_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage49 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage49 : signal is "none";
signal ap_block_pp0_stage49_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage50 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage50 : signal is "none";
signal ap_block_pp0_stage50_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage51 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage51 : signal is "none";
signal ap_block_pp0_stage51_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage52 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage52 : signal is "none";
signal ap_block_pp0_stage52_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage53 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage53 : signal is "none";
signal ap_block_pp0_stage53_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage54 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage54 : signal is "none";
signal ap_block_pp0_stage54_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage55 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage55 : signal is "none";
signal ap_block_pp0_stage55_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage56 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage56 : signal is "none";
signal ap_block_pp0_stage56_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage57 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage57 : signal is "none";
signal ap_block_pp0_stage57_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage58 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage58 : signal is "none";
signal ap_block_pp0_stage58_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage59 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage59 : signal is "none";
signal ap_block_pp0_stage59_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage60 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage60 : signal is "none";
signal ap_block_pp0_stage60_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage61 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage61 : signal is "none";
signal ap_block_pp0_stage61_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage62 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage62 : signal is "none";
signal ap_block_pp0_stage62_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage63 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage63 : signal is "none";
signal ap_block_pp0_stage63_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage64 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage64 : signal is "none";
signal ap_block_pp0_stage64_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage65 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage65 : signal is "none";
signal ap_block_pp0_stage65_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage66 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage66 : signal is "none";
signal ap_block_pp0_stage66_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage67 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage67 : signal is "none";
signal ap_block_pp0_stage67_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage68 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage68 : signal is "none";
signal ap_block_pp0_stage68_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage69 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage69 : signal is "none";
signal ap_block_pp0_stage69_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage70 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage70 : signal is "none";
signal ap_block_pp0_stage70_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage71 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage71 : signal is "none";
signal ap_block_pp0_stage71_flag00000000 : BOOLEAN;
signal ap_CS_fsm_pp0_stage72 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage72 : signal is "none";
signal ap_block_pp0_stage72_flag00000000 : BOOLEAN;
signal buffer_V_blk_n_B : STD_LOGIC;
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_block_pp0_stage0_flag00000000 : BOOLEAN;
signal length_r_blk_n : STD_LOGIC;
signal buffer_V_AWVALID : STD_LOGIC;
signal buffer_V_AWREADY : STD_LOGIC;
signal buffer_V_WVALID : STD_LOGIC;
signal buffer_V_WREADY : STD_LOGIC;
signal buffer_V_WDATA : STD_LOGIC_VECTOR (127 downto 0);
signal buffer_V_ARVALID : STD_LOGIC;
signal buffer_V_ARREADY : STD_LOGIC;
signal buffer_V_ARADDR : STD_LOGIC_VECTOR (31 downto 0);
signal buffer_V_RVALID : STD_LOGIC;
signal buffer_V_RREADY : STD_LOGIC;
signal buffer_V_RDATA : STD_LOGIC_VECTOR (127 downto 0);
signal buffer_V_RLAST : STD_LOGIC;
signal buffer_V_RID : STD_LOGIC_VECTOR (0 downto 0);
signal buffer_V_RUSER : STD_LOGIC_VECTOR (0 downto 0);
signal buffer_V_RRESP : STD_LOGIC_VECTOR (1 downto 0);
signal buffer_V_BVALID : STD_LOGIC;
signal buffer_V_BREADY : STD_LOGIC;
signal buffer_V_BRESP : STD_LOGIC_VECTOR (1 downto 0);
signal buffer_V_BID : STD_LOGIC_VECTOR (0 downto 0);
signal buffer_V_BUSER : STD_LOGIC_VECTOR (0 downto 0);
signal i_op_assign_reg_732 : STD_LOGIC_VECTOR (15 downto 0);
signal reg_752 : STD_LOGIC_VECTOR (127 downto 0);
signal ap_block_state10_pp0_stage8_iter0 : BOOLEAN;
signal ap_block_pp0_stage8_flag00011001 : BOOLEAN;
signal ap_block_state13_pp0_stage11_iter0 : BOOLEAN;
signal ap_block_pp0_stage11_flag00011001 : BOOLEAN;
signal ap_block_state16_pp0_stage14_iter0 : BOOLEAN;
signal ap_block_pp0_stage14_flag00011001 : BOOLEAN;
signal ap_block_state19_pp0_stage17_iter0 : BOOLEAN;
signal ap_block_pp0_stage17_flag00011001 : BOOLEAN;
signal ap_block_state22_pp0_stage20_iter0 : BOOLEAN;
signal ap_block_pp0_stage20_flag00011001 : BOOLEAN;
signal ap_block_state25_pp0_stage23_iter0 : BOOLEAN;
signal ap_block_pp0_stage23_flag00011001 : BOOLEAN;
signal ap_block_state28_pp0_stage26_iter0 : BOOLEAN;
signal ap_block_pp0_stage26_flag00011001 : BOOLEAN;
signal ap_block_state31_pp0_stage29_iter0 : BOOLEAN;
signal ap_block_pp0_stage29_flag00011001 : BOOLEAN;
signal ap_block_state34_pp0_stage32_iter0 : BOOLEAN;
signal ap_block_pp0_stage32_flag00011001 : BOOLEAN;
signal ap_block_state37_pp0_stage35_iter0 : BOOLEAN;
signal ap_block_pp0_stage35_flag00011001 : BOOLEAN;
signal ap_block_state40_pp0_stage38_iter0 : BOOLEAN;
signal ap_block_pp0_stage38_flag00011001 : BOOLEAN;
signal reg_756 : STD_LOGIC_VECTOR (127 downto 0);
signal ap_block_state11_pp0_stage9_iter0 : BOOLEAN;
signal ap_block_pp0_stage9_flag00011001 : BOOLEAN;
signal ap_block_state14_pp0_stage12_iter0 : BOOLEAN;
signal ap_block_pp0_stage12_flag00011001 : BOOLEAN;
signal ap_block_state17_pp0_stage15_iter0 : BOOLEAN;
signal ap_block_pp0_stage15_flag00011001 : BOOLEAN;
signal ap_block_state20_pp0_stage18_iter0 : BOOLEAN;
signal ap_block_pp0_stage18_flag00011001 : BOOLEAN;
signal ap_block_state23_pp0_stage21_iter0 : BOOLEAN;
signal ap_block_pp0_stage21_flag00011001 : BOOLEAN;
signal ap_block_state26_pp0_stage24_iter0 : BOOLEAN;
signal ap_block_pp0_stage24_flag00011001 : BOOLEAN;
signal ap_block_state29_pp0_stage27_iter0 : BOOLEAN;
signal ap_block_pp0_stage27_flag00011001 : BOOLEAN;
signal ap_block_state32_pp0_stage30_iter0 : BOOLEAN;
signal ap_block_pp0_stage30_flag00011001 : BOOLEAN;
signal ap_block_state35_pp0_stage33_iter0 : BOOLEAN;
signal ap_block_pp0_stage33_flag00011001 : BOOLEAN;
signal ap_block_state38_pp0_stage36_iter0 : BOOLEAN;
signal ap_block_pp0_stage36_flag00011001 : BOOLEAN;
signal ap_block_state41_pp0_stage39_iter0 : BOOLEAN;
signal ap_block_pp0_stage39_flag00011001 : BOOLEAN;
signal reg_760 : STD_LOGIC_VECTOR (127 downto 0);
signal ap_block_state12_pp0_stage10_iter0 : BOOLEAN;
signal ap_block_pp0_stage10_flag00011001 : BOOLEAN;
signal ap_block_state15_pp0_stage13_iter0 : BOOLEAN;
signal ap_block_pp0_stage13_flag00011001 : BOOLEAN;
signal ap_block_state18_pp0_stage16_iter0 : BOOLEAN;
signal ap_block_pp0_stage16_flag00011001 : BOOLEAN;
signal ap_block_state21_pp0_stage19_iter0 : BOOLEAN;
signal ap_block_pp0_stage19_flag00011001 : BOOLEAN;
signal ap_block_state24_pp0_stage22_iter0 : BOOLEAN;
signal ap_block_pp0_stage22_flag00011001 : BOOLEAN;
signal ap_block_state27_pp0_stage25_iter0 : BOOLEAN;
signal ap_block_pp0_stage25_flag00011001 : BOOLEAN;
signal ap_block_state30_pp0_stage28_iter0 : BOOLEAN;
signal ap_block_pp0_stage28_flag00011001 : BOOLEAN;
signal ap_block_state33_pp0_stage31_iter0 : BOOLEAN;
signal ap_block_pp0_stage31_flag00011001 : BOOLEAN;
signal ap_block_state36_pp0_stage34_iter0 : BOOLEAN;
signal ap_block_pp0_stage34_flag00011001 : BOOLEAN;
signal ap_block_state39_pp0_stage37_iter0 : BOOLEAN;
signal ap_block_pp0_stage37_flag00011001 : BOOLEAN;
signal buffer_temp_out_V_q1 : STD_LOGIC_VECTOR (127 downto 0);
signal reg_764 : STD_LOGIC_VECTOR (127 downto 0);
signal buffer_temp_out_V_q0 : STD_LOGIC_VECTOR (127 downto 0);
signal ap_block_state43_pp0_stage41_iter0 : BOOLEAN;
signal ap_sig_ioackin_buffer_V_WREADY : STD_LOGIC;
signal ap_block_state43_io : BOOLEAN;
signal ap_block_pp0_stage41_flag00011001 : BOOLEAN;
signal reg_770 : STD_LOGIC_VECTOR (127 downto 0);
signal ap_block_state44_pp0_stage42_iter0 : BOOLEAN;
signal ap_block_state44_io : BOOLEAN;
signal ap_block_pp0_stage42_flag00011001 : BOOLEAN;
signal reg_775 : STD_LOGIC_VECTOR (127 downto 0);
signal ap_block_state45_pp0_stage43_iter0 : BOOLEAN;
signal ap_block_state45_io : BOOLEAN;
signal ap_block_pp0_stage43_flag00011001 : BOOLEAN;
signal reg_780 : STD_LOGIC_VECTOR (127 downto 0);
signal ap_block_state46_pp0_stage44_iter0 : BOOLEAN;
signal ap_block_state46_io : BOOLEAN;
signal ap_block_pp0_stage44_flag00011001 : BOOLEAN;
signal ap_block_state1 : BOOLEAN;
signal tmp_fu_809_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_state2_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state79_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_pp0_stage0_flag00011001 : BOOLEAN;
signal tmp_66_fu_821_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_66_reg_1936 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_98_fu_826_p1 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_98_reg_1940 : STD_LOGIC_VECTOR (14 downto 0);
signal ap_block_state3_pp0_stage1_iter0 : BOOLEAN;
signal ap_sig_ioackin_buffer_V_ARREADY : STD_LOGIC;
signal ap_block_state3_io : BOOLEAN;
signal ap_block_pp0_stage1_flag00011001 : BOOLEAN;
signal tmp_1_fu_830_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_1_reg_1974 : STD_LOGIC_VECTOR (63 downto 0);
signal buffer_V_addr_reg_1979 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_fu_841_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_4_reg_1985 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_5_1_fu_861_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_1_reg_1991 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_6_fu_866_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_6_reg_1995 : STD_LOGIC_VECTOR (14 downto 0);
signal ap_CS_fsm_pp0_stage2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage2 : signal is "none";
signal ap_block_state4_pp0_stage2_iter0 : BOOLEAN;
signal ap_block_pp0_stage2_flag00011001 : BOOLEAN;
signal tmp_5_2_fu_884_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_2_reg_2001 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_fu_889_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_8_reg_2005 : STD_LOGIC_VECTOR (14 downto 0);
signal ap_CS_fsm_pp0_stage3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage3 : signal is "none";
signal ap_block_state5_pp0_stage3_iter0 : BOOLEAN;
signal ap_block_pp0_stage3_flag00011001 : BOOLEAN;
signal tmp_5_3_fu_907_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_3_reg_2011 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_s_fu_912_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_s_reg_2015 : STD_LOGIC_VECTOR (14 downto 0);
signal ap_CS_fsm_pp0_stage4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage4 : signal is "none";
signal ap_block_state6_pp0_stage4_iter0 : BOOLEAN;
signal ap_block_pp0_stage4_flag00011001 : BOOLEAN;
signal tmp_5_4_fu_930_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_4_reg_2021 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_fu_935_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_11_reg_2025 : STD_LOGIC_VECTOR (14 downto 0);
signal ap_CS_fsm_pp0_stage5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage5 : signal is "none";
signal ap_block_state7_pp0_stage5_iter0 : BOOLEAN;
signal ap_block_pp0_stage5_flag00011001 : BOOLEAN;
signal tmp_5_5_fu_953_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_5_reg_2031 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_13_fu_958_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_13_reg_2035 : STD_LOGIC_VECTOR (14 downto 0);
signal ap_CS_fsm_pp0_stage6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage6 : signal is "none";
signal ap_block_state8_pp0_stage6_iter0 : BOOLEAN;
signal ap_block_pp0_stage6_flag00011001 : BOOLEAN;
signal tmp_5_6_fu_976_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_6_reg_2041 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_fu_981_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_15_reg_2045 : STD_LOGIC_VECTOR (14 downto 0);
signal ap_CS_fsm_pp0_stage7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage7 : signal is "none";
signal ap_block_state9_pp0_stage7_iter0 : BOOLEAN;
signal ap_block_pp0_stage7_flag00011001 : BOOLEAN;
signal tmp_5_7_fu_999_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_7_reg_2051 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_17_fu_1004_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_17_reg_2055 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_5_8_fu_1022_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_8_reg_2061 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_fu_1027_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_19_reg_2065 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_5_9_fu_1045_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_9_reg_2071 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_21_fu_1050_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_21_reg_2075 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_5_s_fu_1068_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_s_reg_2081 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_23_fu_1073_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_23_reg_2085 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_25_fu_1082_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_25_reg_2091 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_27_fu_1091_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_27_reg_2097 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_29_fu_1100_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_29_reg_2103 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_31_fu_1109_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_31_reg_2109 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_33_fu_1118_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_33_reg_2115 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_35_fu_1127_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_35_reg_2121 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_37_fu_1136_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_37_reg_2127 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_39_fu_1145_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_39_reg_2133 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_41_fu_1154_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_41_reg_2139 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_43_fu_1163_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_43_reg_2145 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_45_fu_1172_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_45_reg_2151 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_47_fu_1181_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_47_reg_2157 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_49_fu_1190_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_49_reg_2163 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_51_fu_1199_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_51_reg_2169 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_53_fu_1208_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_53_reg_2175 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_55_fu_1217_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_55_reg_2181 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_57_fu_1226_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_57_reg_2187 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_59_fu_1235_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_59_reg_2193 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_61_fu_1244_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_61_reg_2199 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_63_fu_1253_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_63_reg_2205 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_5_10_fu_1271_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_10_reg_2211 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_11_fu_1276_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_11_reg_2215 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_12_fu_1281_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_12_reg_2219 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_13_fu_1286_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_13_reg_2223 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_14_fu_1291_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_14_reg_2227 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_15_fu_1296_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_15_reg_2231 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_16_fu_1301_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_16_reg_2235 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_17_fu_1306_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_17_reg_2239 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_18_fu_1311_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_18_reg_2243 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_19_fu_1316_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_19_reg_2247 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_20_fu_1321_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_20_reg_2251 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_21_fu_1326_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_21_reg_2255 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_22_fu_1331_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_22_reg_2259 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_23_fu_1336_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_23_reg_2263 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_24_fu_1341_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_24_reg_2267 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_25_fu_1346_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_25_reg_2271 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_26_fu_1351_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_26_reg_2275 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_27_fu_1356_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_27_reg_2279 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_28_fu_1361_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_28_reg_2283 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_29_fu_1366_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_29_reg_2287 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_30_fu_1371_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_30_reg_2291 : STD_LOGIC_VECTOR (0 downto 0);
signal i_fu_1389_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal i_reg_2295 : STD_LOGIC_VECTOR (15 downto 0);
signal buffer_temp_out_V_lo_4_reg_2300 : STD_LOGIC_VECTOR (127 downto 0);
signal buffer_temp_out_V_lo_5_reg_2305 : STD_LOGIC_VECTOR (127 downto 0);
signal buffer_temp_out_V_lo_6_reg_2310 : STD_LOGIC_VECTOR (127 downto 0);
signal buffer_temp_out_V_lo_7_reg_2315 : STD_LOGIC_VECTOR (127 downto 0);
signal buffer_temp_out_V_lo_8_reg_2320 : STD_LOGIC_VECTOR (127 downto 0);
signal buffer_temp_out_V_lo_9_reg_2325 : STD_LOGIC_VECTOR (127 downto 0);
signal buffer_temp_out_V_lo_10_reg_2330 : STD_LOGIC_VECTOR (127 downto 0);
signal buffer_temp_out_V_lo_11_reg_2335 : STD_LOGIC_VECTOR (127 downto 0);
signal buffer_temp_out_V_lo_12_reg_2340 : STD_LOGIC_VECTOR (127 downto 0);
signal buffer_temp_out_V_lo_13_reg_2345 : STD_LOGIC_VECTOR (127 downto 0);
signal buffer_temp_out_V_lo_14_reg_2350 : STD_LOGIC_VECTOR (127 downto 0);
signal buffer_temp_out_V_lo_15_reg_2355 : STD_LOGIC_VECTOR (127 downto 0);
signal buffer_temp_out_V_lo_16_reg_2360 : STD_LOGIC_VECTOR (127 downto 0);
signal buffer_temp_out_V_lo_17_reg_2365 : STD_LOGIC_VECTOR (127 downto 0);
signal buffer_temp_out_V_lo_18_reg_2370 : STD_LOGIC_VECTOR (127 downto 0);
signal buffer_temp_out_V_lo_19_reg_2375 : STD_LOGIC_VECTOR (127 downto 0);
signal buffer_temp_out_V_lo_20_reg_2380 : STD_LOGIC_VECTOR (127 downto 0);
signal buffer_temp_out_V_lo_21_reg_2385 : STD_LOGIC_VECTOR (127 downto 0);
signal buffer_temp_out_V_lo_22_reg_2390 : STD_LOGIC_VECTOR (127 downto 0);
signal buffer_temp_out_V_lo_23_reg_2395 : STD_LOGIC_VECTOR (127 downto 0);
signal buffer_temp_out_V_lo_24_reg_2400 : STD_LOGIC_VECTOR (127 downto 0);
signal buffer_temp_out_V_lo_25_reg_2405 : STD_LOGIC_VECTOR (127 downto 0);
signal buffer_temp_out_V_lo_26_reg_2410 : STD_LOGIC_VECTOR (127 downto 0);
signal buffer_temp_out_V_lo_27_reg_2415 : STD_LOGIC_VECTOR (127 downto 0);
signal ap_block_state42_pp0_stage40_iter0 : BOOLEAN;
signal ap_sig_ioackin_buffer_V_AWREADY : STD_LOGIC;
signal ap_block_state42_io : BOOLEAN;
signal ap_block_pp0_stage40_flag00011001 : BOOLEAN;
signal ap_block_pp0_stage0_flag00011011 : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state2 : STD_LOGIC;
signal ap_block_state78_pp0_stage76_iter0 : BOOLEAN;
signal ap_block_pp0_stage76_flag00011011 : BOOLEAN;
signal ap_CS_fsm_pp0_stage76 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage76 : signal is "none";
signal buffer_temp_out_V_address0 : STD_LOGIC_VECTOR (4 downto 0);
signal buffer_temp_out_V_ce0 : STD_LOGIC;
signal buffer_temp_out_V_we0 : STD_LOGIC;
signal buffer_temp_out_V_d0 : STD_LOGIC_VECTOR (127 downto 0);
signal buffer_temp_out_V_address1 : STD_LOGIC_VECTOR (4 downto 0);
signal buffer_temp_out_V_ce1 : STD_LOGIC;
signal buffer_temp_out_V_we1 : STD_LOGIC;
signal buffer_temp_out_V_d1 : STD_LOGIC_VECTOR (127 downto 0);
signal grp_aestest_fu_744_ap_start : STD_LOGIC;
signal grp_aestest_fu_744_ap_done : STD_LOGIC;
signal grp_aestest_fu_744_ap_idle : STD_LOGIC;
signal grp_aestest_fu_744_ap_ready : STD_LOGIC;
signal grp_aestest_fu_744_ap_ce : STD_LOGIC;
signal grp_aestest_fu_744_inptext_V_read : STD_LOGIC_VECTOR (127 downto 0);
signal grp_aestest_fu_744_ap_return : STD_LOGIC_VECTOR (127 downto 0);
signal ap_predicate_op143_call_state3 : BOOLEAN;
signal ap_predicate_op307_call_state13 : BOOLEAN;
signal ap_predicate_op152_call_state4 : BOOLEAN;
signal ap_predicate_op370_call_state14 : BOOLEAN;
signal ap_predicate_op162_call_state5 : BOOLEAN;
signal ap_predicate_op392_call_state15 : BOOLEAN;
signal ap_predicate_op173_call_state6 : BOOLEAN;
signal ap_predicate_op414_call_state16 : BOOLEAN;
signal ap_predicate_op185_call_state7 : BOOLEAN;
signal ap_predicate_op436_call_state17 : BOOLEAN;
signal ap_predicate_op198_call_state8 : BOOLEAN;
signal ap_predicate_op458_call_state18 : BOOLEAN;
signal ap_predicate_op212_call_state9 : BOOLEAN;
signal ap_predicate_op480_call_state19 : BOOLEAN;
signal ap_predicate_op227_call_state10 : BOOLEAN;
signal ap_predicate_op502_call_state20 : BOOLEAN;
signal ap_predicate_op243_call_state11 : BOOLEAN;
signal ap_predicate_op524_call_state21 : BOOLEAN;
signal ap_predicate_op260_call_state12 : BOOLEAN;
signal ap_predicate_op546_call_state22 : BOOLEAN;
signal ap_predicate_op324_call_state13 : BOOLEAN;
signal ap_predicate_op568_call_state23 : BOOLEAN;
signal ap_predicate_op387_call_state14 : BOOLEAN;
signal ap_predicate_op590_call_state24 : BOOLEAN;
signal ap_predicate_op409_call_state15 : BOOLEAN;
signal ap_predicate_op612_call_state25 : BOOLEAN;
signal ap_predicate_op431_call_state16 : BOOLEAN;
signal ap_predicate_op634_call_state26 : BOOLEAN;
signal ap_predicate_op453_call_state17 : BOOLEAN;
signal ap_predicate_op656_call_state27 : BOOLEAN;
signal ap_predicate_op475_call_state18 : BOOLEAN;
signal ap_predicate_op678_call_state28 : BOOLEAN;
signal ap_predicate_op497_call_state19 : BOOLEAN;
signal ap_predicate_op700_call_state29 : BOOLEAN;
signal ap_predicate_op519_call_state20 : BOOLEAN;
signal ap_predicate_op722_call_state30 : BOOLEAN;
signal ap_predicate_op541_call_state21 : BOOLEAN;
signal ap_predicate_op744_call_state31 : BOOLEAN;
signal ap_predicate_op563_call_state22 : BOOLEAN;
signal ap_predicate_op766_call_state32 : BOOLEAN;
signal ap_predicate_op585_call_state23 : BOOLEAN;
signal ap_predicate_op788_call_state33 : BOOLEAN;
signal ap_predicate_op607_call_state24 : BOOLEAN;
signal ap_predicate_op810_call_state34 : BOOLEAN;
signal ap_predicate_op629_call_state25 : BOOLEAN;
signal ap_predicate_op832_call_state35 : BOOLEAN;
signal ap_predicate_op651_call_state26 : BOOLEAN;
signal ap_predicate_op851_call_state36 : BOOLEAN;
signal ap_predicate_op673_call_state27 : BOOLEAN;
signal ap_predicate_op869_call_state37 : BOOLEAN;
signal ap_predicate_op695_call_state28 : BOOLEAN;
signal ap_predicate_op886_call_state38 : BOOLEAN;
signal ap_predicate_op717_call_state29 : BOOLEAN;
signal ap_predicate_op902_call_state39 : BOOLEAN;
signal ap_predicate_op739_call_state30 : BOOLEAN;
signal ap_predicate_op917_call_state40 : BOOLEAN;
signal ap_predicate_op761_call_state31 : BOOLEAN;
signal ap_predicate_op931_call_state41 : BOOLEAN;
signal ap_predicate_op783_call_state32 : BOOLEAN;
signal ap_predicate_op943_call_state42 : BOOLEAN;
signal ap_predicate_op805_call_state33 : BOOLEAN;
signal ap_predicate_op955_call_state43 : BOOLEAN;
signal ap_predicate_op827_call_state34 : BOOLEAN;
signal ap_predicate_op969_call_state44 : BOOLEAN;
signal i_op_assign_phi_fu_736_p4 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_grp_aestest_fu_744_ap_start : STD_LOGIC := '0';
signal ap_predicate_op143_call_state3_state2 : BOOLEAN;
signal ap_predicate_op152_call_state4_state3 : BOOLEAN;
signal ap_predicate_op162_call_state5_state4 : BOOLEAN;
signal ap_predicate_op173_call_state6_state5 : BOOLEAN;
signal ap_predicate_op185_call_state7_state6 : BOOLEAN;
signal ap_predicate_op198_call_state8_state7 : BOOLEAN;
signal ap_predicate_op212_call_state9_state8 : BOOLEAN;
signal ap_predicate_op227_call_state10_state9 : BOOLEAN;
signal ap_predicate_op243_call_state11_state10 : BOOLEAN;
signal ap_predicate_op260_call_state12_state11 : BOOLEAN;
signal ap_predicate_op324_call_state13_state12 : BOOLEAN;
signal ap_predicate_op387_call_state14_state13 : BOOLEAN;
signal ap_predicate_op409_call_state15_state14 : BOOLEAN;
signal ap_predicate_op431_call_state16_state15 : BOOLEAN;
signal ap_predicate_op453_call_state17_state16 : BOOLEAN;
signal ap_predicate_op475_call_state18_state17 : BOOLEAN;
signal ap_predicate_op497_call_state19_state18 : BOOLEAN;
signal ap_predicate_op519_call_state20_state19 : BOOLEAN;
signal ap_predicate_op541_call_state21_state20 : BOOLEAN;
signal ap_predicate_op563_call_state22_state21 : BOOLEAN;
signal ap_predicate_op585_call_state23_state22 : BOOLEAN;
signal ap_predicate_op607_call_state24_state23 : BOOLEAN;
signal ap_predicate_op629_call_state25_state24 : BOOLEAN;
signal ap_predicate_op651_call_state26_state25 : BOOLEAN;
signal ap_predicate_op673_call_state27_state26 : BOOLEAN;
signal ap_predicate_op695_call_state28_state27 : BOOLEAN;
signal ap_predicate_op717_call_state29_state28 : BOOLEAN;
signal ap_predicate_op739_call_state30_state29 : BOOLEAN;
signal ap_predicate_op761_call_state31_state30 : BOOLEAN;
signal ap_predicate_op783_call_state32_state31 : BOOLEAN;
signal ap_predicate_op805_call_state33_state32 : BOOLEAN;
signal ap_predicate_op827_call_state34_state33 : BOOLEAN;
signal counter_V_fu_855_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal counter_V_0_1_fu_878_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal ap_block_pp0_stage2_flag00000000 : BOOLEAN;
signal counter_V_0_2_fu_901_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal ap_block_pp0_stage3_flag00000000 : BOOLEAN;
signal counter_V_0_3_fu_924_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal ap_block_pp0_stage4_flag00000000 : BOOLEAN;
signal counter_V_0_4_fu_947_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal ap_block_pp0_stage5_flag00000000 : BOOLEAN;
signal counter_V_0_5_fu_970_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal ap_block_pp0_stage6_flag00000000 : BOOLEAN;
signal counter_V_0_6_fu_993_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal ap_block_pp0_stage7_flag00000000 : BOOLEAN;
signal counter_V_0_7_fu_1016_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal counter_V_0_8_fu_1039_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal counter_V_0_9_fu_1062_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal counter_V_0_s_fu_1265_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal counter_V_0_10_fu_1383_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal counter_V_0_11_fu_1402_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal counter_V_0_12_fu_1415_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal counter_V_0_13_fu_1428_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal counter_V_0_14_fu_1441_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal counter_V_0_15_fu_1454_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal counter_V_0_16_fu_1467_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal counter_V_0_17_fu_1480_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal counter_V_0_18_fu_1493_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal counter_V_0_19_fu_1506_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal counter_V_0_20_fu_1519_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal counter_V_0_21_fu_1532_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal counter_V_0_22_fu_1545_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal counter_V_0_23_fu_1558_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal counter_V_0_24_fu_1571_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal counter_V_0_25_fu_1584_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal counter_V_0_26_fu_1597_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal counter_V_0_27_fu_1610_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal counter_V_0_28_fu_1623_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal counter_V_0_29_fu_1636_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal counter_V_0_30_fu_1649_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_5_fu_1376_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_7_fu_1395_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_9_fu_1408_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_10_fu_1421_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_fu_1434_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_fu_1447_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_16_fu_1460_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_18_fu_1473_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_20_fu_1486_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_22_fu_1499_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_24_fu_1512_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_26_fu_1525_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_28_fu_1538_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_30_fu_1551_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_32_fu_1564_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_34_fu_1577_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_36_fu_1590_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_38_fu_1603_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_40_fu_1616_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_42_fu_1629_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_44_fu_1642_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_46_fu_1655_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_48_fu_1659_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_50_fu_1663_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_52_fu_1667_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_54_fu_1671_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_56_fu_1675_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_58_fu_1679_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_60_fu_1683_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_62_fu_1687_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_64_fu_1691_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_reg_ioackin_buffer_V_ARREADY : STD_LOGIC := '0';
signal ap_block_pp0_stage1_flag00001001 : BOOLEAN;
signal ap_reg_ioackin_buffer_V_AWREADY : STD_LOGIC := '0';
signal ap_block_pp0_stage40_flag00001001 : BOOLEAN;
signal ap_reg_ioackin_buffer_V_WREADY : STD_LOGIC := '0';
signal ap_block_pp0_stage41_flag00001001 : BOOLEAN;
signal ap_block_pp0_stage42_flag00001001 : BOOLEAN;
signal ap_block_pp0_stage43_flag00001001 : BOOLEAN;
signal ap_block_pp0_stage44_flag00001001 : BOOLEAN;
signal ap_block_state47_pp0_stage45_iter0 : BOOLEAN;
signal ap_block_pp0_stage45_flag00001001 : BOOLEAN;
signal ap_block_state47_io : BOOLEAN;
signal ap_block_pp0_stage45_flag00011001 : BOOLEAN;
signal ap_block_state48_pp0_stage46_iter0 : BOOLEAN;
signal ap_block_pp0_stage46_flag00001001 : BOOLEAN;
signal ap_block_state48_io : BOOLEAN;
signal ap_block_pp0_stage46_flag00011001 : BOOLEAN;
signal ap_block_state49_pp0_stage47_iter0 : BOOLEAN;
signal ap_block_pp0_stage47_flag00001001 : BOOLEAN;
signal ap_block_state49_io : BOOLEAN;
signal ap_block_pp0_stage47_flag00011001 : BOOLEAN;
signal ap_block_state50_pp0_stage48_iter0 : BOOLEAN;
signal ap_block_pp0_stage48_flag00001001 : BOOLEAN;
signal ap_block_state50_io : BOOLEAN;
signal ap_block_pp0_stage48_flag00011001 : BOOLEAN;
signal ap_block_state51_pp0_stage49_iter0 : BOOLEAN;
signal ap_block_pp0_stage49_flag00001001 : BOOLEAN;
signal ap_block_state51_io : BOOLEAN;
signal ap_block_pp0_stage49_flag00011001 : BOOLEAN;
signal ap_block_state52_pp0_stage50_iter0 : BOOLEAN;
signal ap_block_pp0_stage50_flag00001001 : BOOLEAN;
signal ap_block_state52_io : BOOLEAN;
signal ap_block_pp0_stage50_flag00011001 : BOOLEAN;
signal ap_block_state53_pp0_stage51_iter0 : BOOLEAN;
signal ap_block_pp0_stage51_flag00001001 : BOOLEAN;
signal ap_block_state53_io : BOOLEAN;
signal ap_block_pp0_stage51_flag00011001 : BOOLEAN;
signal ap_block_state54_pp0_stage52_iter0 : BOOLEAN;
signal ap_block_pp0_stage52_flag00001001 : BOOLEAN;
signal ap_block_state54_io : BOOLEAN;
signal ap_block_pp0_stage52_flag00011001 : BOOLEAN;
signal ap_block_state55_pp0_stage53_iter0 : BOOLEAN;
signal ap_block_pp0_stage53_flag00001001 : BOOLEAN;
signal ap_block_state55_io : BOOLEAN;
signal ap_block_pp0_stage53_flag00011001 : BOOLEAN;
signal ap_block_state56_pp0_stage54_iter0 : BOOLEAN;
signal ap_block_pp0_stage54_flag00001001 : BOOLEAN;
signal ap_block_state56_io : BOOLEAN;
signal ap_block_pp0_stage54_flag00011001 : BOOLEAN;
signal ap_block_state57_pp0_stage55_iter0 : BOOLEAN;
signal ap_block_pp0_stage55_flag00001001 : BOOLEAN;
signal ap_block_state57_io : BOOLEAN;
signal ap_block_pp0_stage55_flag00011001 : BOOLEAN;
signal ap_block_state58_pp0_stage56_iter0 : BOOLEAN;
signal ap_block_pp0_stage56_flag00001001 : BOOLEAN;
signal ap_block_state58_io : BOOLEAN;
signal ap_block_pp0_stage56_flag00011001 : BOOLEAN;
signal ap_block_state59_pp0_stage57_iter0 : BOOLEAN;
signal ap_block_pp0_stage57_flag00001001 : BOOLEAN;
signal ap_block_state59_io : BOOLEAN;
signal ap_block_pp0_stage57_flag00011001 : BOOLEAN;
signal ap_block_state60_pp0_stage58_iter0 : BOOLEAN;
signal ap_block_pp0_stage58_flag00001001 : BOOLEAN;
signal ap_block_state60_io : BOOLEAN;
signal ap_block_pp0_stage58_flag00011001 : BOOLEAN;
signal ap_block_state61_pp0_stage59_iter0 : BOOLEAN;
signal ap_block_pp0_stage59_flag00001001 : BOOLEAN;
signal ap_block_state61_io : BOOLEAN;
signal ap_block_pp0_stage59_flag00011001 : BOOLEAN;
signal ap_block_state62_pp0_stage60_iter0 : BOOLEAN;
signal ap_block_pp0_stage60_flag00001001 : BOOLEAN;
signal ap_block_state62_io : BOOLEAN;
signal ap_block_pp0_stage60_flag00011001 : BOOLEAN;
signal ap_block_state63_pp0_stage61_iter0 : BOOLEAN;
signal ap_block_pp0_stage61_flag00001001 : BOOLEAN;
signal ap_block_state63_io : BOOLEAN;
signal ap_block_pp0_stage61_flag00011001 : BOOLEAN;
signal ap_block_state64_pp0_stage62_iter0 : BOOLEAN;
signal ap_block_pp0_stage62_flag00001001 : BOOLEAN;
signal ap_block_state64_io : BOOLEAN;
signal ap_block_pp0_stage62_flag00011001 : BOOLEAN;
signal ap_block_state65_pp0_stage63_iter0 : BOOLEAN;
signal ap_block_pp0_stage63_flag00001001 : BOOLEAN;
signal ap_block_state65_io : BOOLEAN;
signal ap_block_pp0_stage63_flag00011001 : BOOLEAN;
signal ap_block_state66_pp0_stage64_iter0 : BOOLEAN;
signal ap_block_pp0_stage64_flag00001001 : BOOLEAN;
signal ap_block_state66_io : BOOLEAN;
signal ap_block_pp0_stage64_flag00011001 : BOOLEAN;
signal ap_block_state67_pp0_stage65_iter0 : BOOLEAN;
signal ap_block_pp0_stage65_flag00001001 : BOOLEAN;
signal ap_block_state67_io : BOOLEAN;
signal ap_block_pp0_stage65_flag00011001 : BOOLEAN;
signal ap_block_state68_pp0_stage66_iter0 : BOOLEAN;
signal ap_block_pp0_stage66_flag00001001 : BOOLEAN;
signal ap_block_state68_io : BOOLEAN;
signal ap_block_pp0_stage66_flag00011001 : BOOLEAN;
signal ap_block_state69_pp0_stage67_iter0 : BOOLEAN;
signal ap_block_pp0_stage67_flag00001001 : BOOLEAN;
signal ap_block_state69_io : BOOLEAN;
signal ap_block_pp0_stage67_flag00011001 : BOOLEAN;
signal ap_block_state70_pp0_stage68_iter0 : BOOLEAN;
signal ap_block_pp0_stage68_flag00001001 : BOOLEAN;
signal ap_block_state70_io : BOOLEAN;
signal ap_block_pp0_stage68_flag00011001 : BOOLEAN;
signal ap_block_state71_pp0_stage69_iter0 : BOOLEAN;
signal ap_block_pp0_stage69_flag00001001 : BOOLEAN;
signal ap_block_state71_io : BOOLEAN;
signal ap_block_pp0_stage69_flag00011001 : BOOLEAN;
signal ap_block_state72_pp0_stage70_iter0 : BOOLEAN;
signal ap_block_pp0_stage70_flag00001001 : BOOLEAN;
signal ap_block_state72_io : BOOLEAN;
signal ap_block_pp0_stage70_flag00011001 : BOOLEAN;
signal ap_block_state73_pp0_stage71_iter0 : BOOLEAN;
signal ap_block_pp0_stage71_flag00001001 : BOOLEAN;
signal ap_block_state73_io : BOOLEAN;
signal ap_block_pp0_stage71_flag00011001 : BOOLEAN;
signal ap_block_state74_pp0_stage72_iter0 : BOOLEAN;
signal ap_block_pp0_stage72_flag00001001 : BOOLEAN;
signal ap_block_state74_io : BOOLEAN;
signal ap_block_pp0_stage72_flag00011001 : BOOLEAN;
signal grp_fu_786_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal grp_fu_794_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal grp_fu_802_p2 : STD_LOGIC_VECTOR (127 downto 0);
signal i_op_assign_cast1_fu_817_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_fu_851_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_4_cast_fu_847_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_cast_6_fu_875_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_6_cast_fu_871_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_1_cast_fu_898_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_8_cast_fu_894_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_2_cast_fu_921_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_cast_fu_917_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_3_cast_fu_944_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_11_cast_fu_940_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_4_cast_fu_967_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_13_cast_fu_963_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_5_cast_fu_990_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_15_cast_fu_986_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_6_cast_fu_1013_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_17_cast_fu_1009_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_7_cast_fu_1036_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_19_cast_fu_1032_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_8_cast_fu_1059_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_21_cast_fu_1055_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_9_cast_fu_1262_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_23_cast_fu_1078_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_25_cast_fu_1087_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_27_cast_fu_1096_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_29_cast_fu_1105_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_31_cast_fu_1114_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_33_cast_fu_1123_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_35_cast_fu_1132_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_37_cast_fu_1141_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_39_cast_fu_1150_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_41_cast_fu_1159_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_43_cast_fu_1168_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_45_cast_fu_1177_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_47_cast_fu_1186_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_49_cast_fu_1195_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_51_cast_fu_1204_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_53_cast_fu_1213_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_55_cast_fu_1222_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_57_cast_fu_1231_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_59_cast_fu_1240_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_61_cast_fu_1249_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_63_cast_fu_1258_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_10_cast_fu_1380_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_8_11_cast_fu_1399_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_8_12_cast_fu_1412_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_8_13_cast_fu_1425_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_8_14_cast_fu_1438_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_8_15_cast_fu_1451_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_8_16_cast_fu_1464_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_8_17_cast_fu_1477_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_8_18_cast_fu_1490_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_8_19_cast_fu_1503_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_8_20_cast_fu_1516_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_8_21_cast_fu_1529_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_8_22_cast_fu_1542_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_8_23_cast_fu_1555_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_8_24_cast_fu_1568_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_8_25_cast_fu_1581_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_8_26_cast_fu_1594_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_8_27_cast_fu_1607_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_8_28_cast_fu_1620_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_8_29_cast_fu_1633_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal tmp_8_30_cast_fu_1646_p1 : STD_LOGIC_VECTOR (127 downto 0);
signal ap_CS_fsm_state80 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state80 : signal is "none";
signal ap_NS_fsm : STD_LOGIC_VECTOR (78 downto 0);
signal ap_block_pp0_stage1_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage2_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage3_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage4_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage5_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage6_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage7_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage8_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage9_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage10_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage11_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage12_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage13_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage14_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage15_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage16_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage17_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage18_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage19_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage20_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage21_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage22_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage23_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage24_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage25_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage26_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage27_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage28_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage29_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage30_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage31_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage32_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage33_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage34_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage35_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage36_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage37_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage38_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage39_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage40_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage41_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage42_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage43_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage44_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage45_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage46_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage47_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage48_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage49_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage50_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage51_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage52_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage53_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage54_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage55_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage56_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage57_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage58_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage59_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage60_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage61_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage62_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage63_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage64_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage65_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage66_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage67_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage68_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage69_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage70_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage71_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage72_flag00011011 : BOOLEAN;
signal ap_block_state75_pp0_stage73_iter0 : BOOLEAN;
signal ap_block_pp0_stage73_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage73_flag00011001 : BOOLEAN;
signal ap_block_state76_pp0_stage74_iter0 : BOOLEAN;
signal ap_block_pp0_stage74_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage74_flag00011001 : BOOLEAN;
signal ap_block_state77_pp0_stage75_iter0 : BOOLEAN;
signal ap_block_pp0_stage75_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage75_flag00011001 : BOOLEAN;
signal ap_block_pp0_stage76_flag00011001 : BOOLEAN;
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
signal ap_condition_7926 : BOOLEAN;
signal ap_condition_7931 : BOOLEAN;
signal ap_condition_7969 : BOOLEAN;
signal ap_condition_7973 : BOOLEAN;
signal ap_condition_7977 : BOOLEAN;
signal ap_condition_7981 : BOOLEAN;
signal ap_condition_7985 : BOOLEAN;
signal ap_condition_7989 : BOOLEAN;
signal ap_condition_7993 : BOOLEAN;
signal ap_condition_7997 : BOOLEAN;
signal ap_condition_8001 : BOOLEAN;
signal ap_condition_8005 : BOOLEAN;
signal ap_condition_8008 : BOOLEAN;
signal ap_condition_8011 : BOOLEAN;
signal ap_condition_8014 : BOOLEAN;
signal ap_condition_8017 : BOOLEAN;
signal ap_condition_8020 : BOOLEAN;
signal ap_condition_8023 : BOOLEAN;
signal ap_condition_8026 : BOOLEAN;
signal ap_condition_8029 : BOOLEAN;
signal ap_condition_8032 : BOOLEAN;
signal ap_condition_8035 : BOOLEAN;
signal ap_condition_8038 : BOOLEAN;
signal ap_condition_8041 : BOOLEAN;
signal ap_condition_8044 : BOOLEAN;
signal ap_condition_8047 : BOOLEAN;
signal ap_condition_8050 : BOOLEAN;
signal ap_condition_8053 : BOOLEAN;
signal ap_condition_8056 : BOOLEAN;
signal ap_condition_8059 : BOOLEAN;
signal ap_condition_8062 : BOOLEAN;
signal ap_condition_8065 : BOOLEAN;
signal ap_condition_8068 : BOOLEAN;
signal ap_condition_8071 : BOOLEAN;
component aestest IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_ce : IN STD_LOGIC;
inptext_V_read : IN STD_LOGIC_VECTOR (127 downto 0);
key_V_read : IN STD_LOGIC_VECTOR (127 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (127 downto 0) );
end component;
component filesystem_encrypbkb IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (4 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (127 downto 0);
q0 : OUT STD_LOGIC_VECTOR (127 downto 0);
address1 : IN STD_LOGIC_VECTOR (4 downto 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR (127 downto 0);
q1 : OUT STD_LOGIC_VECTOR (127 downto 0) );
end component;
component filesystem_encrypt_AXILiteS_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
iv_V : OUT STD_LOGIC_VECTOR (127 downto 0);
length_r : OUT STD_LOGIC_VECTOR (31 downto 0);
length_r_ap_vld : OUT STD_LOGIC );
end component;
component filesystem_encrypt_buffer_V_m_axi IS
generic (
USER_DW : INTEGER;
USER_AW : INTEGER;
USER_MAXREQS : INTEGER;
NUM_READ_OUTSTANDING : INTEGER;
NUM_WRITE_OUTSTANDING : INTEGER;
MAX_READ_BURST_LENGTH : INTEGER;
MAX_WRITE_BURST_LENGTH : INTEGER;
C_M_AXI_ID_WIDTH : INTEGER;
C_M_AXI_ADDR_WIDTH : INTEGER;
C_M_AXI_DATA_WIDTH : INTEGER;
C_M_AXI_AWUSER_WIDTH : INTEGER;
C_M_AXI_ARUSER_WIDTH : INTEGER;
C_M_AXI_WUSER_WIDTH : INTEGER;
C_M_AXI_RUSER_WIDTH : INTEGER;
C_M_AXI_BUSER_WIDTH : INTEGER;
C_TARGET_ADDR : INTEGER;
C_USER_VALUE : INTEGER;
C_PROT_VALUE : INTEGER;
C_CACHE_VALUE : INTEGER );
port (
AWVALID : OUT STD_LOGIC;
AWREADY : IN STD_LOGIC;
AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
WVALID : OUT STD_LOGIC;
WREADY : IN STD_LOGIC;
WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : OUT STD_LOGIC;
WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
ARVALID : OUT STD_LOGIC;
ARREADY : IN STD_LOGIC;
ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
RVALID : IN STD_LOGIC;
RREADY : OUT STD_LOGIC;
RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
RLAST : IN STD_LOGIC;
RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
BVALID : IN STD_LOGIC;
BREADY : OUT STD_LOGIC;
BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
I_ARVALID : IN STD_LOGIC;
I_ARREADY : OUT STD_LOGIC;
I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
I_RVALID : OUT STD_LOGIC;
I_RREADY : IN STD_LOGIC;
I_RDATA : OUT STD_LOGIC_VECTOR (127 downto 0);
I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
I_RLAST : OUT STD_LOGIC;
I_AWVALID : IN STD_LOGIC;
I_AWREADY : OUT STD_LOGIC;
I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
I_WVALID : IN STD_LOGIC;
I_WREADY : OUT STD_LOGIC;
I_WDATA : IN STD_LOGIC_VECTOR (127 downto 0);
I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
I_WLAST : IN STD_LOGIC;
I_WSTRB : IN STD_LOGIC_VECTOR (15 downto 0);
I_BVALID : OUT STD_LOGIC;
I_BREADY : IN STD_LOGIC;
I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
begin
filesystem_encrypt_AXILiteS_s_axi_U : component filesystem_encrypt_AXILiteS_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_AXILITES_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_AXILITES_DATA_WIDTH)
port map (
AWVALID => s_axi_AXILiteS_AWVALID,
AWREADY => s_axi_AXILiteS_AWREADY,
AWADDR => s_axi_AXILiteS_AWADDR,
WVALID => s_axi_AXILiteS_WVALID,
WREADY => s_axi_AXILiteS_WREADY,
WDATA => s_axi_AXILiteS_WDATA,
WSTRB => s_axi_AXILiteS_WSTRB,
ARVALID => s_axi_AXILiteS_ARVALID,
ARREADY => s_axi_AXILiteS_ARREADY,
ARADDR => s_axi_AXILiteS_ARADDR,
RVALID => s_axi_AXILiteS_RVALID,
RREADY => s_axi_AXILiteS_RREADY,
RDATA => s_axi_AXILiteS_RDATA,
RRESP => s_axi_AXILiteS_RRESP,
BVALID => s_axi_AXILiteS_BVALID,
BREADY => s_axi_AXILiteS_BREADY,
BRESP => s_axi_AXILiteS_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
iv_V => iv_V,
length_r => length_r,
length_r_ap_vld => length_r_ap_vld);
filesystem_encrypt_buffer_V_m_axi_U : component filesystem_encrypt_buffer_V_m_axi
generic map (
USER_DW => 128,
USER_AW => 32,
USER_MAXREQS => 5,
NUM_READ_OUTSTANDING => 16,
NUM_WRITE_OUTSTANDING => 16,
MAX_READ_BURST_LENGTH => 16,
MAX_WRITE_BURST_LENGTH => 16,
C_M_AXI_ID_WIDTH => C_M_AXI_BUFFER_V_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_BUFFER_V_ADDR_WIDTH,
C_M_AXI_DATA_WIDTH => C_M_AXI_BUFFER_V_DATA_WIDTH,
C_M_AXI_AWUSER_WIDTH => C_M_AXI_BUFFER_V_AWUSER_WIDTH,
C_M_AXI_ARUSER_WIDTH => C_M_AXI_BUFFER_V_ARUSER_WIDTH,
C_M_AXI_WUSER_WIDTH => C_M_AXI_BUFFER_V_WUSER_WIDTH,
C_M_AXI_RUSER_WIDTH => C_M_AXI_BUFFER_V_RUSER_WIDTH,
C_M_AXI_BUSER_WIDTH => C_M_AXI_BUFFER_V_BUSER_WIDTH,
C_TARGET_ADDR => C_M_AXI_BUFFER_V_TARGET_ADDR,
C_USER_VALUE => C_M_AXI_BUFFER_V_USER_VALUE,
C_PROT_VALUE => C_M_AXI_BUFFER_V_PROT_VALUE,
C_CACHE_VALUE => C_M_AXI_BUFFER_V_CACHE_VALUE)
port map (
AWVALID => m_axi_buffer_V_AWVALID,
AWREADY => m_axi_buffer_V_AWREADY,
AWADDR => m_axi_buffer_V_AWADDR,
AWID => m_axi_buffer_V_AWID,
AWLEN => m_axi_buffer_V_AWLEN,
AWSIZE => m_axi_buffer_V_AWSIZE,
AWBURST => m_axi_buffer_V_AWBURST,
AWLOCK => m_axi_buffer_V_AWLOCK,
AWCACHE => m_axi_buffer_V_AWCACHE,
AWPROT => m_axi_buffer_V_AWPROT,
AWQOS => m_axi_buffer_V_AWQOS,
AWREGION => m_axi_buffer_V_AWREGION,
AWUSER => m_axi_buffer_V_AWUSER,
WVALID => m_axi_buffer_V_WVALID,
WREADY => m_axi_buffer_V_WREADY,
WDATA => m_axi_buffer_V_WDATA,
WSTRB => m_axi_buffer_V_WSTRB,
WLAST => m_axi_buffer_V_WLAST,
WID => m_axi_buffer_V_WID,
WUSER => m_axi_buffer_V_WUSER,
ARVALID => m_axi_buffer_V_ARVALID,
ARREADY => m_axi_buffer_V_ARREADY,
ARADDR => m_axi_buffer_V_ARADDR,
ARID => m_axi_buffer_V_ARID,
ARLEN => m_axi_buffer_V_ARLEN,
ARSIZE => m_axi_buffer_V_ARSIZE,
ARBURST => m_axi_buffer_V_ARBURST,
ARLOCK => m_axi_buffer_V_ARLOCK,
ARCACHE => m_axi_buffer_V_ARCACHE,
ARPROT => m_axi_buffer_V_ARPROT,
ARQOS => m_axi_buffer_V_ARQOS,
ARREGION => m_axi_buffer_V_ARREGION,
ARUSER => m_axi_buffer_V_ARUSER,
RVALID => m_axi_buffer_V_RVALID,
RREADY => m_axi_buffer_V_RREADY,
RDATA => m_axi_buffer_V_RDATA,
RLAST => m_axi_buffer_V_RLAST,
RID => m_axi_buffer_V_RID,
RUSER => m_axi_buffer_V_RUSER,
RRESP => m_axi_buffer_V_RRESP,
BVALID => m_axi_buffer_V_BVALID,
BREADY => m_axi_buffer_V_BREADY,
BRESP => m_axi_buffer_V_BRESP,
BID => m_axi_buffer_V_BID,
BUSER => m_axi_buffer_V_BUSER,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
I_ARVALID => buffer_V_ARVALID,
I_ARREADY => buffer_V_ARREADY,
I_ARADDR => buffer_V_ARADDR,
I_ARID => ap_const_lv1_0,
I_ARLEN => ap_const_lv32_20,
I_ARSIZE => ap_const_lv3_0,
I_ARLOCK => ap_const_lv2_0,
I_ARCACHE => ap_const_lv4_0,
I_ARQOS => ap_const_lv4_0,
I_ARPROT => ap_const_lv3_0,
I_ARUSER => ap_const_lv1_0,
I_ARBURST => ap_const_lv2_0,
I_ARREGION => ap_const_lv4_0,
I_RVALID => buffer_V_RVALID,
I_RREADY => buffer_V_RREADY,
I_RDATA => buffer_V_RDATA,
I_RID => buffer_V_RID,
I_RUSER => buffer_V_RUSER,
I_RRESP => buffer_V_RRESP,
I_RLAST => buffer_V_RLAST,
I_AWVALID => buffer_V_AWVALID,
I_AWREADY => buffer_V_AWREADY,
I_AWADDR => buffer_V_addr_reg_1979,
I_AWID => ap_const_lv1_0,
I_AWLEN => ap_const_lv32_20,
I_AWSIZE => ap_const_lv3_0,
I_AWLOCK => ap_const_lv2_0,
I_AWCACHE => ap_const_lv4_0,
I_AWQOS => ap_const_lv4_0,
I_AWPROT => ap_const_lv3_0,
I_AWUSER => ap_const_lv1_0,
I_AWBURST => ap_const_lv2_0,
I_AWREGION => ap_const_lv4_0,
I_WVALID => buffer_V_WVALID,
I_WREADY => buffer_V_WREADY,
I_WDATA => buffer_V_WDATA,
I_WID => ap_const_lv1_0,
I_WUSER => ap_const_lv1_0,
I_WLAST => ap_const_logic_0,
I_WSTRB => ap_const_lv16_FFFF,
I_BVALID => buffer_V_BVALID,
I_BREADY => buffer_V_BREADY,
I_BRESP => buffer_V_BRESP,
I_BID => buffer_V_BID,
I_BUSER => buffer_V_BUSER);
buffer_temp_out_V_U : component filesystem_encrypbkb
generic map (
DataWidth => 128,
AddressRange => 32,
AddressWidth => 5)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => buffer_temp_out_V_address0,
ce0 => buffer_temp_out_V_ce0,
we0 => buffer_temp_out_V_we0,
d0 => buffer_temp_out_V_d0,
q0 => buffer_temp_out_V_q0,
address1 => buffer_temp_out_V_address1,
ce1 => buffer_temp_out_V_ce1,
we1 => buffer_temp_out_V_we1,
d1 => buffer_temp_out_V_d1,
q1 => buffer_temp_out_V_q1);
grp_aestest_fu_744 : component aestest
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => grp_aestest_fu_744_ap_start,
ap_done => grp_aestest_fu_744_ap_done,
ap_idle => grp_aestest_fu_744_ap_idle,
ap_ready => grp_aestest_fu_744_ap_ready,
ap_ce => grp_aestest_fu_744_ap_ce,
inptext_V_read => grp_aestest_fu_744_inptext_V_read,
key_V_read => key_V,
ap_return => grp_aestest_fu_744_ap_return);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = length_r_ap_vld_in_sig))))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2) and (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) or ((ap_block_pp0_stage76_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage76))))) then
ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state2 xor ap_const_logic_1);
elsif ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) or ((ap_block_pp0_stage76_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage76)))) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = length_r_ap_vld_in_sig))))) then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_reg_grp_aestest_fu_744_ap_start_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_grp_aestest_fu_744_ap_start <= ap_const_logic_0;
else
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op143_call_state3_state2)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op152_call_state4_state3)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op162_call_state5_state4)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op173_call_state6_state5)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op185_call_state7_state6)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op198_call_state8_state7)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op212_call_state9_state8)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op227_call_state10_state9)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op243_call_state11_state10)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op260_call_state12_state11)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op324_call_state13_state12)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op387_call_state14_state13)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op409_call_state15_state14)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op431_call_state16_state15)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op453_call_state17_state16)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op475_call_state18_state17)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op497_call_state19_state18)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op519_call_state20_state19)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op541_call_state21_state20)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op563_call_state22_state21)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op585_call_state23_state22)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op607_call_state24_state23)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op629_call_state25_state24)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op651_call_state26_state25)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op673_call_state27_state26)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op695_call_state28_state27)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op717_call_state29_state28)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op739_call_state30_state29)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op761_call_state31_state30)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op783_call_state32_state31)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op805_call_state33_state32)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op827_call_state34_state33)))) then
ap_reg_grp_aestest_fu_744_ap_start <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_aestest_fu_744_ap_ready)) then
ap_reg_grp_aestest_fu_744_ap_start <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_reg_ioackin_buffer_V_ARREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_buffer_V_ARREADY <= ap_const_logic_0;
else
if ((ap_condition_7926 = ap_const_boolean_1)) then
if ((ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) then
ap_reg_ioackin_buffer_V_ARREADY <= ap_const_logic_0;
elsif (((ap_const_logic_1 = buffer_V_ARREADY) and (ap_block_pp0_stage1_flag00001001 = ap_const_boolean_0))) then
ap_reg_ioackin_buffer_V_ARREADY <= ap_const_logic_1;
end if;
end if;
end if;
end if;
end process;
ap_reg_ioackin_buffer_V_AWREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_buffer_V_AWREADY <= ap_const_logic_0;
else
if ((ap_condition_7931 = ap_const_boolean_1)) then
if ((ap_block_pp0_stage40_flag00011001 = ap_const_boolean_0)) then
ap_reg_ioackin_buffer_V_AWREADY <= ap_const_logic_0;
elsif (((ap_const_logic_1 = buffer_V_AWREADY) and (ap_block_pp0_stage40_flag00001001 = ap_const_boolean_0))) then
ap_reg_ioackin_buffer_V_AWREADY <= ap_const_logic_1;
end if;
end if;
end if;
end if;
end process;
ap_reg_ioackin_buffer_V_WREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_buffer_V_WREADY <= ap_const_logic_0;
else
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage64) and (ap_block_pp0_stage64_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage65) and (ap_block_pp0_stage65_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage66) and (ap_block_pp0_stage66_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage67) and (ap_block_pp0_stage67_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage68) and (ap_block_pp0_stage68_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage69) and (ap_block_pp0_stage69_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage70) and (ap_block_pp0_stage70_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage71) and (ap_block_pp0_stage71_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage72) and (ap_block_pp0_stage72_flag00011001 = ap_const_boolean_0)))) then
ap_reg_ioackin_buffer_V_WREADY <= ap_const_logic_0;
elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage41_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage42_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage43_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage44_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage45_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage46_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage47_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage48_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage49_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage50_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage51_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage52_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage53_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage54_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage55_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage56_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage57_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage58_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage59_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage60_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage61_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage62_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage63_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage64) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage64_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage65) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage65_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage66) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage66_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage67) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage67_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage68) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage68_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage69) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage69_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage70) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage70_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage71) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage71_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage72) and (ap_const_logic_1 = buffer_V_WREADY) and (ap_block_pp0_stage72_flag00001001 = ap_const_boolean_0)))) then
ap_reg_ioackin_buffer_V_WREADY <= ap_const_logic_1;
end if;
end if;
end if;
end process;
length_r_ap_vld_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
length_r_ap_vld_preg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_CS_fsm_state80)) then
length_r_ap_vld_preg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = length_r_ap_vld) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))))) then
length_r_ap_vld_preg <= length_r_ap_vld;
end if;
end if;
end if;
end process;
length_r_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
length_r_preg <= ap_const_lv32_0;
else
if (((ap_const_logic_1 = length_r_ap_vld) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))))) then
length_r_preg <= length_r;
end if;
end if;
end if;
end process;
i_op_assign_reg_732_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
i_op_assign_reg_732 <= i_reg_2295;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = length_r_ap_vld_in_sig))))) then
i_op_assign_reg_732 <= ap_const_lv16_0;
end if;
end if;
end process;
reg_764_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0))) then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00011001 = ap_const_boolean_0))) then
reg_764 <= buffer_temp_out_V_q0;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0))) then
reg_764 <= buffer_temp_out_V_q1;
end if;
end if;
end if;
end process;
reg_780_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0))) then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00011001 = ap_const_boolean_0))) then
reg_780 <= buffer_temp_out_V_q1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0))) then
reg_780 <= buffer_temp_out_V_q0;
end if;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0))) then
buffer_V_addr_reg_1979(15 downto 0) <= tmp_1_fu_830_p1(32 - 1 downto 0)(15 downto 0);
tmp_1_reg_1974(15 downto 0) <= tmp_1_fu_830_p1(15 downto 0);
tmp_4_reg_1985(14 downto 1) <= tmp_4_fu_841_p2(14 downto 1);
tmp_98_reg_1940 <= tmp_98_fu_826_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0))) then
buffer_temp_out_V_lo_10_reg_2330 <= buffer_temp_out_V_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0))) then
buffer_temp_out_V_lo_11_reg_2335 <= buffer_temp_out_V_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0))) then
buffer_temp_out_V_lo_12_reg_2340 <= buffer_temp_out_V_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0))) then
buffer_temp_out_V_lo_13_reg_2345 <= buffer_temp_out_V_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0))) then
buffer_temp_out_V_lo_14_reg_2350 <= buffer_temp_out_V_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0))) then
buffer_temp_out_V_lo_15_reg_2355 <= buffer_temp_out_V_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0))) then
buffer_temp_out_V_lo_16_reg_2360 <= buffer_temp_out_V_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0))) then
buffer_temp_out_V_lo_17_reg_2365 <= buffer_temp_out_V_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0))) then
buffer_temp_out_V_lo_18_reg_2370 <= buffer_temp_out_V_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00011001 = ap_const_boolean_0))) then
buffer_temp_out_V_lo_19_reg_2375 <= buffer_temp_out_V_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00011001 = ap_const_boolean_0))) then
buffer_temp_out_V_lo_20_reg_2380 <= buffer_temp_out_V_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00011001 = ap_const_boolean_0))) then
buffer_temp_out_V_lo_21_reg_2385 <= buffer_temp_out_V_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00011001 = ap_const_boolean_0))) then
buffer_temp_out_V_lo_22_reg_2390 <= buffer_temp_out_V_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00011001 = ap_const_boolean_0))) then
buffer_temp_out_V_lo_23_reg_2395 <= buffer_temp_out_V_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00011001 = ap_const_boolean_0))) then
buffer_temp_out_V_lo_24_reg_2400 <= buffer_temp_out_V_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00011001 = ap_const_boolean_0))) then
buffer_temp_out_V_lo_25_reg_2405 <= buffer_temp_out_V_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00011001 = ap_const_boolean_0))) then
buffer_temp_out_V_lo_26_reg_2410 <= buffer_temp_out_V_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00011001 = ap_const_boolean_0))) then
buffer_temp_out_V_lo_27_reg_2415 <= buffer_temp_out_V_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0))) then
buffer_temp_out_V_lo_4_reg_2300 <= buffer_temp_out_V_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0))) then
buffer_temp_out_V_lo_5_reg_2305 <= buffer_temp_out_V_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0))) then
buffer_temp_out_V_lo_6_reg_2310 <= buffer_temp_out_V_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0))) then
buffer_temp_out_V_lo_7_reg_2315 <= buffer_temp_out_V_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0))) then
buffer_temp_out_V_lo_8_reg_2320 <= buffer_temp_out_V_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0))) then
buffer_temp_out_V_lo_9_reg_2325 <= buffer_temp_out_V_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0))) then
i_reg_2295 <= i_fu_1389_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00011001 = ap_const_boolean_0)))) then
reg_752 <= buffer_V_RDATA;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00011001 = ap_const_boolean_0)))) then
reg_756 <= buffer_V_RDATA;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00011001 = ap_const_boolean_0)))) then
reg_760 <= buffer_V_RDATA;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00011001 = ap_const_boolean_0)))) then
reg_770 <= buffer_temp_out_V_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00011001 = ap_const_boolean_0)))) then
reg_775 <= buffer_temp_out_V_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0))) then
tmp_11_reg_2025(1) <= tmp_11_fu_935_p2(1); tmp_11_reg_2025(14 downto 3) <= tmp_11_fu_935_p2(14 downto 3);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0))) then
tmp_13_reg_2035(0) <= tmp_13_fu_958_p2(0); tmp_13_reg_2035(14 downto 3) <= tmp_13_fu_958_p2(14 downto 3);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0))) then
tmp_15_reg_2045(14 downto 3) <= tmp_15_fu_981_p2(14 downto 3);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0))) then
tmp_17_reg_2055(2 downto 0) <= tmp_17_fu_1004_p2(2 downto 0); tmp_17_reg_2055(14 downto 4) <= tmp_17_fu_1004_p2(14 downto 4);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0))) then
tmp_19_reg_2065(2 downto 1) <= tmp_19_fu_1027_p2(2 downto 1); tmp_19_reg_2065(14 downto 4) <= tmp_19_fu_1027_p2(14 downto 4);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0))) then
tmp_21_reg_2075(0) <= tmp_21_fu_1050_p2(0); tmp_21_reg_2075(2) <= tmp_21_fu_1050_p2(2); tmp_21_reg_2075(14 downto 4) <= tmp_21_fu_1050_p2(14 downto 4);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0))) then
tmp_23_reg_2085(2) <= tmp_23_fu_1073_p2(2); tmp_23_reg_2085(14 downto 4) <= tmp_23_fu_1073_p2(14 downto 4);
tmp_25_reg_2091(1 downto 0) <= tmp_25_fu_1082_p2(1 downto 0); tmp_25_reg_2091(14 downto 4) <= tmp_25_fu_1082_p2(14 downto 4);
tmp_27_reg_2097(1) <= tmp_27_fu_1091_p2(1); tmp_27_reg_2097(14 downto 4) <= tmp_27_fu_1091_p2(14 downto 4);
tmp_29_reg_2103(0) <= tmp_29_fu_1100_p2(0); tmp_29_reg_2103(14 downto 4) <= tmp_29_fu_1100_p2(14 downto 4);
tmp_31_reg_2109(14 downto 4) <= tmp_31_fu_1109_p2(14 downto 4);
tmp_33_reg_2115(3 downto 0) <= tmp_33_fu_1118_p2(3 downto 0); tmp_33_reg_2115(14 downto 5) <= tmp_33_fu_1118_p2(14 downto 5);
tmp_35_reg_2121(3 downto 1) <= tmp_35_fu_1127_p2(3 downto 1); tmp_35_reg_2121(14 downto 5) <= tmp_35_fu_1127_p2(14 downto 5);
tmp_37_reg_2127(0) <= tmp_37_fu_1136_p2(0); tmp_37_reg_2127(3 downto 2) <= tmp_37_fu_1136_p2(3 downto 2); tmp_37_reg_2127(14 downto 5) <= tmp_37_fu_1136_p2(14 downto 5);
tmp_39_reg_2133(3 downto 2) <= tmp_39_fu_1145_p2(3 downto 2); tmp_39_reg_2133(14 downto 5) <= tmp_39_fu_1145_p2(14 downto 5);
tmp_41_reg_2139(1 downto 0) <= tmp_41_fu_1154_p2(1 downto 0); tmp_41_reg_2139(3) <= tmp_41_fu_1154_p2(3); tmp_41_reg_2139(14 downto 5) <= tmp_41_fu_1154_p2(14 downto 5);
tmp_43_reg_2145(1) <= tmp_43_fu_1163_p2(1); tmp_43_reg_2145(3) <= tmp_43_fu_1163_p2(3); tmp_43_reg_2145(14 downto 5) <= tmp_43_fu_1163_p2(14 downto 5);
tmp_45_reg_2151(0) <= tmp_45_fu_1172_p2(0); tmp_45_reg_2151(3) <= tmp_45_fu_1172_p2(3); tmp_45_reg_2151(14 downto 5) <= tmp_45_fu_1172_p2(14 downto 5);
tmp_47_reg_2157(3) <= tmp_47_fu_1181_p2(3); tmp_47_reg_2157(14 downto 5) <= tmp_47_fu_1181_p2(14 downto 5);
tmp_49_reg_2163(2 downto 0) <= tmp_49_fu_1190_p2(2 downto 0); tmp_49_reg_2163(14 downto 5) <= tmp_49_fu_1190_p2(14 downto 5);
tmp_51_reg_2169(2 downto 1) <= tmp_51_fu_1199_p2(2 downto 1); tmp_51_reg_2169(14 downto 5) <= tmp_51_fu_1199_p2(14 downto 5);
tmp_53_reg_2175(0) <= tmp_53_fu_1208_p2(0); tmp_53_reg_2175(2) <= tmp_53_fu_1208_p2(2); tmp_53_reg_2175(14 downto 5) <= tmp_53_fu_1208_p2(14 downto 5);
tmp_55_reg_2181(2) <= tmp_55_fu_1217_p2(2); tmp_55_reg_2181(14 downto 5) <= tmp_55_fu_1217_p2(14 downto 5);
tmp_57_reg_2187(1 downto 0) <= tmp_57_fu_1226_p2(1 downto 0); tmp_57_reg_2187(14 downto 5) <= tmp_57_fu_1226_p2(14 downto 5);
tmp_59_reg_2193(1) <= tmp_59_fu_1235_p2(1); tmp_59_reg_2193(14 downto 5) <= tmp_59_fu_1235_p2(14 downto 5);
tmp_61_reg_2199(0) <= tmp_61_fu_1244_p2(0); tmp_61_reg_2199(14 downto 5) <= tmp_61_fu_1244_p2(14 downto 5);
tmp_63_reg_2205(14 downto 5) <= tmp_63_fu_1253_p2(14 downto 5);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081))) then
tmp_5_10_reg_2211 <= tmp_5_10_fu_1271_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_fu_1271_p2))) then
tmp_5_11_reg_2215 <= tmp_5_11_fu_1276_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_fu_1271_p2) and (ap_const_lv1_1 = tmp_5_11_fu_1276_p2))) then
tmp_5_12_reg_2219 <= tmp_5_12_fu_1281_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_fu_1271_p2) and (ap_const_lv1_1 = tmp_5_11_fu_1276_p2) and (ap_const_lv1_1 = tmp_5_12_fu_1281_p2))) then
tmp_5_13_reg_2223 <= tmp_5_13_fu_1286_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_fu_1271_p2) and (ap_const_lv1_1 = tmp_5_11_fu_1276_p2) and (ap_const_lv1_1 = tmp_5_12_fu_1281_p2) and (ap_const_lv1_1 = tmp_5_13_fu_1286_p2))) then
tmp_5_14_reg_2227 <= tmp_5_14_fu_1291_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_fu_1271_p2) and (ap_const_lv1_1 = tmp_5_11_fu_1276_p2) and (ap_const_lv1_1 = tmp_5_12_fu_1281_p2) and (ap_const_lv1_1 = tmp_5_13_fu_1286_p2) and (ap_const_lv1_1 = tmp_5_14_fu_1291_p2))) then
tmp_5_15_reg_2231 <= tmp_5_15_fu_1296_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_fu_1271_p2) and (ap_const_lv1_1 = tmp_5_11_fu_1276_p2) and (ap_const_lv1_1 = tmp_5_12_fu_1281_p2) and (ap_const_lv1_1 = tmp_5_13_fu_1286_p2) and (ap_const_lv1_1 = tmp_5_14_fu_1291_p2) and (ap_const_lv1_1 = tmp_5_15_fu_1296_p2))) then
tmp_5_16_reg_2235 <= tmp_5_16_fu_1301_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_fu_1271_p2) and (ap_const_lv1_1 = tmp_5_11_fu_1276_p2) and (ap_const_lv1_1 = tmp_5_12_fu_1281_p2) and (ap_const_lv1_1 = tmp_5_13_fu_1286_p2) and (ap_const_lv1_1 = tmp_5_14_fu_1291_p2) and (ap_const_lv1_1 = tmp_5_15_fu_1296_p2) and (ap_const_lv1_1 = tmp_5_16_fu_1301_p2))) then
tmp_5_17_reg_2239 <= tmp_5_17_fu_1306_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_fu_1271_p2) and (ap_const_lv1_1 = tmp_5_11_fu_1276_p2) and (ap_const_lv1_1 = tmp_5_12_fu_1281_p2) and (ap_const_lv1_1 = tmp_5_13_fu_1286_p2) and (ap_const_lv1_1 = tmp_5_14_fu_1291_p2) and (ap_const_lv1_1 = tmp_5_15_fu_1296_p2) and (ap_const_lv1_1 = tmp_5_16_fu_1301_p2) and (ap_const_lv1_1 = tmp_5_17_fu_1306_p2))) then
tmp_5_18_reg_2243 <= tmp_5_18_fu_1311_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_fu_1271_p2) and (ap_const_lv1_1 = tmp_5_11_fu_1276_p2) and (ap_const_lv1_1 = tmp_5_12_fu_1281_p2) and (ap_const_lv1_1 = tmp_5_13_fu_1286_p2) and (ap_const_lv1_1 = tmp_5_14_fu_1291_p2) and (ap_const_lv1_1 = tmp_5_15_fu_1296_p2) and (ap_const_lv1_1 = tmp_5_16_fu_1301_p2) and (ap_const_lv1_1 = tmp_5_17_fu_1306_p2) and (ap_const_lv1_1 = tmp_5_18_fu_1311_p2))) then
tmp_5_19_reg_2247 <= tmp_5_19_fu_1316_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (tmp_66_reg_1936 = ap_const_lv1_1))) then
tmp_5_1_reg_1991 <= tmp_5_1_fu_861_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_fu_1271_p2) and (ap_const_lv1_1 = tmp_5_11_fu_1276_p2) and (ap_const_lv1_1 = tmp_5_12_fu_1281_p2) and (ap_const_lv1_1 = tmp_5_13_fu_1286_p2) and (ap_const_lv1_1 = tmp_5_14_fu_1291_p2) and (ap_const_lv1_1 = tmp_5_15_fu_1296_p2) and (ap_const_lv1_1 = tmp_5_16_fu_1301_p2) and (ap_const_lv1_1 = tmp_5_17_fu_1306_p2) and (ap_const_lv1_1 = tmp_5_18_fu_1311_p2) and (ap_const_lv1_1 = tmp_5_19_fu_1316_p2))) then
tmp_5_20_reg_2251 <= tmp_5_20_fu_1321_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_fu_1271_p2) and (ap_const_lv1_1 = tmp_5_11_fu_1276_p2) and (ap_const_lv1_1 = tmp_5_12_fu_1281_p2) and (ap_const_lv1_1 = tmp_5_13_fu_1286_p2) and (ap_const_lv1_1 = tmp_5_14_fu_1291_p2) and (ap_const_lv1_1 = tmp_5_15_fu_1296_p2) and (ap_const_lv1_1 = tmp_5_16_fu_1301_p2) and (ap_const_lv1_1 = tmp_5_17_fu_1306_p2) and (ap_const_lv1_1 = tmp_5_18_fu_1311_p2) and (ap_const_lv1_1 = tmp_5_19_fu_1316_p2) and (ap_const_lv1_1 = tmp_5_20_fu_1321_p2))) then
tmp_5_21_reg_2255 <= tmp_5_21_fu_1326_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_fu_1271_p2) and (ap_const_lv1_1 = tmp_5_11_fu_1276_p2) and (ap_const_lv1_1 = tmp_5_12_fu_1281_p2) and (ap_const_lv1_1 = tmp_5_13_fu_1286_p2) and (ap_const_lv1_1 = tmp_5_14_fu_1291_p2) and (ap_const_lv1_1 = tmp_5_15_fu_1296_p2) and (ap_const_lv1_1 = tmp_5_16_fu_1301_p2) and (ap_const_lv1_1 = tmp_5_17_fu_1306_p2) and (ap_const_lv1_1 = tmp_5_18_fu_1311_p2) and (ap_const_lv1_1 = tmp_5_19_fu_1316_p2) and (ap_const_lv1_1 = tmp_5_20_fu_1321_p2) and (ap_const_lv1_1 = tmp_5_21_fu_1326_p2))) then
tmp_5_22_reg_2259 <= tmp_5_22_fu_1331_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_fu_1271_p2) and (ap_const_lv1_1 = tmp_5_11_fu_1276_p2) and (ap_const_lv1_1 = tmp_5_12_fu_1281_p2) and (ap_const_lv1_1 = tmp_5_13_fu_1286_p2) and (ap_const_lv1_1 = tmp_5_14_fu_1291_p2) and (ap_const_lv1_1 = tmp_5_15_fu_1296_p2) and (ap_const_lv1_1 = tmp_5_16_fu_1301_p2) and (ap_const_lv1_1 = tmp_5_17_fu_1306_p2) and (ap_const_lv1_1 = tmp_5_18_fu_1311_p2) and (ap_const_lv1_1 = tmp_5_19_fu_1316_p2) and (ap_const_lv1_1 = tmp_5_20_fu_1321_p2) and (ap_const_lv1_1 = tmp_5_21_fu_1326_p2) and (ap_const_lv1_1 = tmp_5_22_fu_1331_p2))) then
tmp_5_23_reg_2263 <= tmp_5_23_fu_1336_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_fu_1271_p2) and (ap_const_lv1_1 = tmp_5_11_fu_1276_p2) and (ap_const_lv1_1 = tmp_5_12_fu_1281_p2) and (ap_const_lv1_1 = tmp_5_13_fu_1286_p2) and (ap_const_lv1_1 = tmp_5_14_fu_1291_p2) and (ap_const_lv1_1 = tmp_5_15_fu_1296_p2) and (ap_const_lv1_1 = tmp_5_16_fu_1301_p2) and (ap_const_lv1_1 = tmp_5_17_fu_1306_p2) and (ap_const_lv1_1 = tmp_5_18_fu_1311_p2) and (ap_const_lv1_1 = tmp_5_19_fu_1316_p2) and (ap_const_lv1_1 = tmp_5_20_fu_1321_p2) and (ap_const_lv1_1 = tmp_5_21_fu_1326_p2) and (ap_const_lv1_1 = tmp_5_22_fu_1331_p2) and (ap_const_lv1_1 = tmp_5_23_fu_1336_p2))) then
tmp_5_24_reg_2267 <= tmp_5_24_fu_1341_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_fu_1271_p2) and (ap_const_lv1_1 = tmp_5_11_fu_1276_p2) and (ap_const_lv1_1 = tmp_5_12_fu_1281_p2) and (ap_const_lv1_1 = tmp_5_13_fu_1286_p2) and (ap_const_lv1_1 = tmp_5_14_fu_1291_p2) and (ap_const_lv1_1 = tmp_5_15_fu_1296_p2) and (ap_const_lv1_1 = tmp_5_16_fu_1301_p2) and (ap_const_lv1_1 = tmp_5_17_fu_1306_p2) and (ap_const_lv1_1 = tmp_5_18_fu_1311_p2) and (ap_const_lv1_1 = tmp_5_19_fu_1316_p2) and (ap_const_lv1_1 = tmp_5_20_fu_1321_p2) and (ap_const_lv1_1 = tmp_5_21_fu_1326_p2) and (ap_const_lv1_1 = tmp_5_22_fu_1331_p2) and (ap_const_lv1_1 = tmp_5_23_fu_1336_p2) and (ap_const_lv1_1 = tmp_5_24_fu_1341_p2))) then
tmp_5_25_reg_2271 <= tmp_5_25_fu_1346_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_fu_1271_p2) and (ap_const_lv1_1 = tmp_5_11_fu_1276_p2) and (ap_const_lv1_1 = tmp_5_12_fu_1281_p2) and (ap_const_lv1_1 = tmp_5_13_fu_1286_p2) and (ap_const_lv1_1 = tmp_5_14_fu_1291_p2) and (ap_const_lv1_1 = tmp_5_15_fu_1296_p2) and (ap_const_lv1_1 = tmp_5_16_fu_1301_p2) and (ap_const_lv1_1 = tmp_5_17_fu_1306_p2) and (ap_const_lv1_1 = tmp_5_18_fu_1311_p2) and (ap_const_lv1_1 = tmp_5_19_fu_1316_p2) and (ap_const_lv1_1 = tmp_5_20_fu_1321_p2) and (ap_const_lv1_1 = tmp_5_21_fu_1326_p2) and (ap_const_lv1_1 = tmp_5_22_fu_1331_p2) and (ap_const_lv1_1 = tmp_5_23_fu_1336_p2) and (ap_const_lv1_1 = tmp_5_24_fu_1341_p2) and (ap_const_lv1_1 = tmp_5_25_fu_1346_p2))) then
tmp_5_26_reg_2275 <= tmp_5_26_fu_1351_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_fu_1271_p2) and (ap_const_lv1_1 = tmp_5_11_fu_1276_p2) and (ap_const_lv1_1 = tmp_5_12_fu_1281_p2) and (ap_const_lv1_1 = tmp_5_13_fu_1286_p2) and (ap_const_lv1_1 = tmp_5_14_fu_1291_p2) and (ap_const_lv1_1 = tmp_5_15_fu_1296_p2) and (ap_const_lv1_1 = tmp_5_16_fu_1301_p2) and (ap_const_lv1_1 = tmp_5_17_fu_1306_p2) and (ap_const_lv1_1 = tmp_5_18_fu_1311_p2) and (ap_const_lv1_1 = tmp_5_19_fu_1316_p2) and (ap_const_lv1_1 = tmp_5_20_fu_1321_p2) and (ap_const_lv1_1 = tmp_5_21_fu_1326_p2) and (ap_const_lv1_1 = tmp_5_22_fu_1331_p2) and (ap_const_lv1_1 = tmp_5_23_fu_1336_p2) and (ap_const_lv1_1 = tmp_5_24_fu_1341_p2) and (ap_const_lv1_1 = tmp_5_25_fu_1346_p2) and (ap_const_lv1_1 = tmp_5_26_fu_1351_p2))) then
tmp_5_27_reg_2279 <= tmp_5_27_fu_1356_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_fu_1271_p2) and (ap_const_lv1_1 = tmp_5_11_fu_1276_p2) and (ap_const_lv1_1 = tmp_5_12_fu_1281_p2) and (ap_const_lv1_1 = tmp_5_13_fu_1286_p2) and (ap_const_lv1_1 = tmp_5_14_fu_1291_p2) and (ap_const_lv1_1 = tmp_5_15_fu_1296_p2) and (ap_const_lv1_1 = tmp_5_16_fu_1301_p2) and (ap_const_lv1_1 = tmp_5_17_fu_1306_p2) and (ap_const_lv1_1 = tmp_5_18_fu_1311_p2) and (ap_const_lv1_1 = tmp_5_19_fu_1316_p2) and (ap_const_lv1_1 = tmp_5_20_fu_1321_p2) and (ap_const_lv1_1 = tmp_5_21_fu_1326_p2) and (ap_const_lv1_1 = tmp_5_22_fu_1331_p2) and (ap_const_lv1_1 = tmp_5_23_fu_1336_p2) and (ap_const_lv1_1 = tmp_5_24_fu_1341_p2) and (ap_const_lv1_1 = tmp_5_25_fu_1346_p2) and (ap_const_lv1_1 = tmp_5_26_fu_1351_p2) and (ap_const_lv1_1 = tmp_5_27_fu_1356_p2))) then
tmp_5_28_reg_2283 <= tmp_5_28_fu_1361_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_fu_1271_p2) and (ap_const_lv1_1 = tmp_5_11_fu_1276_p2) and (ap_const_lv1_1 = tmp_5_12_fu_1281_p2) and (ap_const_lv1_1 = tmp_5_13_fu_1286_p2) and (ap_const_lv1_1 = tmp_5_14_fu_1291_p2) and (ap_const_lv1_1 = tmp_5_15_fu_1296_p2) and (ap_const_lv1_1 = tmp_5_16_fu_1301_p2) and (ap_const_lv1_1 = tmp_5_17_fu_1306_p2) and (ap_const_lv1_1 = tmp_5_18_fu_1311_p2) and (ap_const_lv1_1 = tmp_5_19_fu_1316_p2) and (ap_const_lv1_1 = tmp_5_20_fu_1321_p2) and (ap_const_lv1_1 = tmp_5_21_fu_1326_p2) and (ap_const_lv1_1 = tmp_5_22_fu_1331_p2) and (ap_const_lv1_1 = tmp_5_23_fu_1336_p2) and (ap_const_lv1_1 = tmp_5_24_fu_1341_p2) and (ap_const_lv1_1 = tmp_5_25_fu_1346_p2) and (ap_const_lv1_1 = tmp_5_26_fu_1351_p2) and (ap_const_lv1_1 = tmp_5_27_fu_1356_p2) and (ap_const_lv1_1 = tmp_5_28_fu_1361_p2))) then
tmp_5_29_reg_2287 <= tmp_5_29_fu_1366_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (tmp_5_1_reg_1991 = ap_const_lv1_1))) then
tmp_5_2_reg_2001 <= tmp_5_2_fu_884_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_fu_1271_p2) and (ap_const_lv1_1 = tmp_5_11_fu_1276_p2) and (ap_const_lv1_1 = tmp_5_12_fu_1281_p2) and (ap_const_lv1_1 = tmp_5_13_fu_1286_p2) and (ap_const_lv1_1 = tmp_5_14_fu_1291_p2) and (ap_const_lv1_1 = tmp_5_15_fu_1296_p2) and (ap_const_lv1_1 = tmp_5_16_fu_1301_p2) and (ap_const_lv1_1 = tmp_5_17_fu_1306_p2) and (ap_const_lv1_1 = tmp_5_18_fu_1311_p2) and (ap_const_lv1_1 = tmp_5_19_fu_1316_p2) and (ap_const_lv1_1 = tmp_5_20_fu_1321_p2) and (ap_const_lv1_1 = tmp_5_21_fu_1326_p2) and (ap_const_lv1_1 = tmp_5_22_fu_1331_p2) and (ap_const_lv1_1 = tmp_5_23_fu_1336_p2) and (ap_const_lv1_1 = tmp_5_24_fu_1341_p2) and (ap_const_lv1_1 = tmp_5_25_fu_1346_p2) and (ap_const_lv1_1 = tmp_5_26_fu_1351_p2) and (ap_const_lv1_1 = tmp_5_27_fu_1356_p2) and (ap_const_lv1_1 = tmp_5_28_fu_1361_p2) and (ap_const_lv1_1 = tmp_5_29_fu_1366_p2))) then
tmp_5_30_reg_2291 <= tmp_5_30_fu_1371_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_1 = tmp_5_2_reg_2001))) then
tmp_5_3_reg_2011 <= tmp_5_3_fu_907_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_1 = tmp_5_3_reg_2011))) then
tmp_5_4_reg_2021 <= tmp_5_4_fu_930_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_1 = tmp_5_4_reg_2021))) then
tmp_5_5_reg_2031 <= tmp_5_5_fu_953_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_1 = tmp_5_5_reg_2031))) then
tmp_5_6_reg_2041 <= tmp_5_6_fu_976_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_1 = tmp_5_6_reg_2041))) then
tmp_5_7_reg_2051 <= tmp_5_7_fu_999_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051))) then
tmp_5_8_reg_2061 <= tmp_5_8_fu_1022_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061))) then
tmp_5_9_reg_2071 <= tmp_5_9_fu_1045_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071))) then
tmp_5_s_reg_2081 <= tmp_5_s_fu_1068_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = tmp_fu_809_p3))) then
tmp_66_reg_1936 <= tmp_66_fu_821_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
tmp_6_reg_1995(0) <= tmp_6_fu_866_p2(0); tmp_6_reg_1995(14 downto 2) <= tmp_6_fu_866_p2(14 downto 2);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0))) then
tmp_8_reg_2005(14 downto 2) <= tmp_8_fu_889_p2(14 downto 2);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
tmp_reg_1932 <= i_op_assign_phi_fu_736_p4(15 downto 15);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0))) then
tmp_s_reg_2015(1 downto 0) <= tmp_s_fu_912_p2(1 downto 0); tmp_s_reg_2015(14 downto 3) <= tmp_s_fu_912_p2(14 downto 3);
end if;
end if;
end process;
tmp_1_reg_1974(63 downto 16) <= "000000000000000000000000000000000000000000000000";
buffer_V_addr_reg_1979(31 downto 16) <= "0000000000000000";
tmp_4_reg_1985(0) <= '1';
tmp_6_reg_1995(1) <= '1';
tmp_8_reg_2005(1 downto 0) <= "11";
tmp_s_reg_2015(2) <= '1';
tmp_11_reg_2025(0) <= '1';
tmp_11_reg_2025(2) <= '1';
tmp_13_reg_2035(2 downto 1) <= "11";
tmp_15_reg_2045(2 downto 0) <= "111";
tmp_17_reg_2055(3) <= '1';
tmp_19_reg_2065(0) <= '1';
tmp_19_reg_2065(3) <= '1';
tmp_21_reg_2075(1) <= '1';
tmp_21_reg_2075(3) <= '1';
tmp_23_reg_2085(1 downto 0) <= "11";
tmp_23_reg_2085(3) <= '1';
tmp_25_reg_2091(3 downto 2) <= "11";
tmp_27_reg_2097(0) <= '1';
tmp_27_reg_2097(3 downto 2) <= "11";
tmp_29_reg_2103(3 downto 1) <= "111";
tmp_31_reg_2109(3 downto 0) <= "1111";
tmp_33_reg_2115(4) <= '1';
tmp_35_reg_2121(0) <= '1';
tmp_35_reg_2121(4) <= '1';
tmp_37_reg_2127(1) <= '1';
tmp_37_reg_2127(4) <= '1';
tmp_39_reg_2133(1 downto 0) <= "11";
tmp_39_reg_2133(4) <= '1';
tmp_41_reg_2139(2) <= '1';
tmp_41_reg_2139(4) <= '1';
tmp_43_reg_2145(0) <= '1';
tmp_43_reg_2145(2 downto 2) <= "1";
tmp_43_reg_2145(4) <= '1';
tmp_45_reg_2151(2 downto 1) <= "11";
tmp_45_reg_2151(4) <= '1';
tmp_47_reg_2157(2 downto 0) <= "111";
tmp_47_reg_2157(4) <= '1';
tmp_49_reg_2163(4 downto 3) <= "11";
tmp_51_reg_2169(0) <= '1';
tmp_51_reg_2169(4 downto 3) <= "11";
tmp_53_reg_2175(1) <= '1';
tmp_53_reg_2175(4 downto 3) <= "11";
tmp_55_reg_2181(1 downto 0) <= "11";
tmp_55_reg_2181(4 downto 3) <= "11";
tmp_57_reg_2187(4 downto 2) <= "111";
tmp_59_reg_2193(0) <= '1';
tmp_59_reg_2193(4 downto 2) <= "111";
tmp_61_reg_2199(4 downto 1) <= "1111";
tmp_63_reg_2205(4 downto 0) <= "11111";
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, length_r_ap_vld_in_sig, ap_enable_reg_pp0_iter0, tmp_fu_809_p3, ap_block_pp0_stage0_flag00011011, ap_block_pp0_stage76_flag00011011, ap_block_pp0_stage1_flag00011011, ap_block_pp0_stage2_flag00011011, ap_block_pp0_stage3_flag00011011, ap_block_pp0_stage4_flag00011011, ap_block_pp0_stage5_flag00011011, ap_block_pp0_stage6_flag00011011, ap_block_pp0_stage7_flag00011011, ap_block_pp0_stage8_flag00011011, ap_block_pp0_stage9_flag00011011, ap_block_pp0_stage10_flag00011011, ap_block_pp0_stage11_flag00011011, ap_block_pp0_stage12_flag00011011, ap_block_pp0_stage13_flag00011011, ap_block_pp0_stage14_flag00011011, ap_block_pp0_stage15_flag00011011, ap_block_pp0_stage16_flag00011011, ap_block_pp0_stage17_flag00011011, ap_block_pp0_stage18_flag00011011, ap_block_pp0_stage19_flag00011011, ap_block_pp0_stage20_flag00011011, ap_block_pp0_stage21_flag00011011, ap_block_pp0_stage22_flag00011011, ap_block_pp0_stage23_flag00011011, ap_block_pp0_stage24_flag00011011, ap_block_pp0_stage25_flag00011011, ap_block_pp0_stage26_flag00011011, ap_block_pp0_stage27_flag00011011, ap_block_pp0_stage28_flag00011011, ap_block_pp0_stage29_flag00011011, ap_block_pp0_stage30_flag00011011, ap_block_pp0_stage31_flag00011011, ap_block_pp0_stage32_flag00011011, ap_block_pp0_stage33_flag00011011, ap_block_pp0_stage34_flag00011011, ap_block_pp0_stage35_flag00011011, ap_block_pp0_stage36_flag00011011, ap_block_pp0_stage37_flag00011011, ap_block_pp0_stage38_flag00011011, ap_block_pp0_stage39_flag00011011, ap_block_pp0_stage40_flag00011011, ap_block_pp0_stage41_flag00011011, ap_block_pp0_stage42_flag00011011, ap_block_pp0_stage43_flag00011011, ap_block_pp0_stage44_flag00011011, ap_block_pp0_stage45_flag00011011, ap_block_pp0_stage46_flag00011011, ap_block_pp0_stage47_flag00011011, ap_block_pp0_stage48_flag00011011, ap_block_pp0_stage49_flag00011011, ap_block_pp0_stage50_flag00011011, ap_block_pp0_stage51_flag00011011, ap_block_pp0_stage52_flag00011011, ap_block_pp0_stage53_flag00011011, ap_block_pp0_stage54_flag00011011, ap_block_pp0_stage55_flag00011011, ap_block_pp0_stage56_flag00011011, ap_block_pp0_stage57_flag00011011, ap_block_pp0_stage58_flag00011011, ap_block_pp0_stage59_flag00011011, ap_block_pp0_stage60_flag00011011, ap_block_pp0_stage61_flag00011011, ap_block_pp0_stage62_flag00011011, ap_block_pp0_stage63_flag00011011, ap_block_pp0_stage64_flag00011011, ap_block_pp0_stage65_flag00011011, ap_block_pp0_stage66_flag00011011, ap_block_pp0_stage67_flag00011011, ap_block_pp0_stage68_flag00011011, ap_block_pp0_stage69_flag00011011, ap_block_pp0_stage70_flag00011011, ap_block_pp0_stage71_flag00011011, ap_block_pp0_stage72_flag00011011, ap_block_pp0_stage73_flag00011011, ap_block_pp0_stage74_flag00011011, ap_block_pp0_stage75_flag00011011)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = length_r_ap_vld_in_sig))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_pp0_stage0 =>
if (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (tmp_fu_809_p3 = ap_const_lv1_1))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (tmp_fu_809_p3 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state80;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage1 =>
if ((ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
end if;
when ap_ST_fsm_pp0_stage2 =>
if ((ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
end if;
when ap_ST_fsm_pp0_stage3 =>
if ((ap_block_pp0_stage3_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
end if;
when ap_ST_fsm_pp0_stage4 =>
if ((ap_block_pp0_stage4_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
end if;
when ap_ST_fsm_pp0_stage5 =>
if ((ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage6;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
end if;
when ap_ST_fsm_pp0_stage6 =>
if ((ap_block_pp0_stage6_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage7;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage6;
end if;
when ap_ST_fsm_pp0_stage7 =>
if ((ap_block_pp0_stage7_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage8;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage7;
end if;
when ap_ST_fsm_pp0_stage8 =>
if ((ap_block_pp0_stage8_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage9;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage8;
end if;
when ap_ST_fsm_pp0_stage9 =>
if ((ap_block_pp0_stage9_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage10;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage9;
end if;
when ap_ST_fsm_pp0_stage10 =>
if ((ap_block_pp0_stage10_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage11;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage10;
end if;
when ap_ST_fsm_pp0_stage11 =>
if ((ap_block_pp0_stage11_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage12;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage11;
end if;
when ap_ST_fsm_pp0_stage12 =>
if ((ap_block_pp0_stage12_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage13;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage12;
end if;
when ap_ST_fsm_pp0_stage13 =>
if ((ap_block_pp0_stage13_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage14;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage13;
end if;
when ap_ST_fsm_pp0_stage14 =>
if ((ap_block_pp0_stage14_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage15;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage14;
end if;
when ap_ST_fsm_pp0_stage15 =>
if ((ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage16;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage15;
end if;
when ap_ST_fsm_pp0_stage16 =>
if ((ap_block_pp0_stage16_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage17;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage16;
end if;
when ap_ST_fsm_pp0_stage17 =>
if ((ap_block_pp0_stage17_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage18;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage17;
end if;
when ap_ST_fsm_pp0_stage18 =>
if ((ap_block_pp0_stage18_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage19;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage18;
end if;
when ap_ST_fsm_pp0_stage19 =>
if ((ap_block_pp0_stage19_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage20;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage19;
end if;
when ap_ST_fsm_pp0_stage20 =>
if ((ap_block_pp0_stage20_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage21;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage20;
end if;
when ap_ST_fsm_pp0_stage21 =>
if ((ap_block_pp0_stage21_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage22;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage21;
end if;
when ap_ST_fsm_pp0_stage22 =>
if ((ap_block_pp0_stage22_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage23;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage22;
end if;
when ap_ST_fsm_pp0_stage23 =>
if ((ap_block_pp0_stage23_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage24;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage23;
end if;
when ap_ST_fsm_pp0_stage24 =>
if ((ap_block_pp0_stage24_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage25;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage24;
end if;
when ap_ST_fsm_pp0_stage25 =>
if ((ap_block_pp0_stage25_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage26;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage25;
end if;
when ap_ST_fsm_pp0_stage26 =>
if ((ap_block_pp0_stage26_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage27;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage26;
end if;
when ap_ST_fsm_pp0_stage27 =>
if ((ap_block_pp0_stage27_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage28;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage27;
end if;
when ap_ST_fsm_pp0_stage28 =>
if ((ap_block_pp0_stage28_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage29;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage28;
end if;
when ap_ST_fsm_pp0_stage29 =>
if ((ap_block_pp0_stage29_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage30;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage29;
end if;
when ap_ST_fsm_pp0_stage30 =>
if ((ap_block_pp0_stage30_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage31;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage30;
end if;
when ap_ST_fsm_pp0_stage31 =>
if ((ap_block_pp0_stage31_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage32;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage31;
end if;
when ap_ST_fsm_pp0_stage32 =>
if ((ap_block_pp0_stage32_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage33;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage32;
end if;
when ap_ST_fsm_pp0_stage33 =>
if ((ap_block_pp0_stage33_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage34;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage33;
end if;
when ap_ST_fsm_pp0_stage34 =>
if ((ap_block_pp0_stage34_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage35;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage34;
end if;
when ap_ST_fsm_pp0_stage35 =>
if ((ap_block_pp0_stage35_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage36;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage35;
end if;
when ap_ST_fsm_pp0_stage36 =>
if ((ap_block_pp0_stage36_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage37;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage36;
end if;
when ap_ST_fsm_pp0_stage37 =>
if ((ap_block_pp0_stage37_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage38;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage37;
end if;
when ap_ST_fsm_pp0_stage38 =>
if ((ap_block_pp0_stage38_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage39;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage38;
end if;
when ap_ST_fsm_pp0_stage39 =>
if ((ap_block_pp0_stage39_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage40;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage39;
end if;
when ap_ST_fsm_pp0_stage40 =>
if ((ap_block_pp0_stage40_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage41;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage40;
end if;
when ap_ST_fsm_pp0_stage41 =>
if ((ap_block_pp0_stage41_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage42;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage41;
end if;
when ap_ST_fsm_pp0_stage42 =>
if ((ap_block_pp0_stage42_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage43;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage42;
end if;
when ap_ST_fsm_pp0_stage43 =>
if ((ap_block_pp0_stage43_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage44;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage43;
end if;
when ap_ST_fsm_pp0_stage44 =>
if ((ap_block_pp0_stage44_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage45;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage44;
end if;
when ap_ST_fsm_pp0_stage45 =>
if ((ap_block_pp0_stage45_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage46;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage45;
end if;
when ap_ST_fsm_pp0_stage46 =>
if ((ap_block_pp0_stage46_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage47;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage46;
end if;
when ap_ST_fsm_pp0_stage47 =>
if ((ap_block_pp0_stage47_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage48;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage47;
end if;
when ap_ST_fsm_pp0_stage48 =>
if ((ap_block_pp0_stage48_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage49;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage48;
end if;
when ap_ST_fsm_pp0_stage49 =>
if ((ap_block_pp0_stage49_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage50;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage49;
end if;
when ap_ST_fsm_pp0_stage50 =>
if ((ap_block_pp0_stage50_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage51;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage50;
end if;
when ap_ST_fsm_pp0_stage51 =>
if ((ap_block_pp0_stage51_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage52;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage51;
end if;
when ap_ST_fsm_pp0_stage52 =>
if ((ap_block_pp0_stage52_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage53;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage52;
end if;
when ap_ST_fsm_pp0_stage53 =>
if ((ap_block_pp0_stage53_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage54;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage53;
end if;
when ap_ST_fsm_pp0_stage54 =>
if ((ap_block_pp0_stage54_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage55;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage54;
end if;
when ap_ST_fsm_pp0_stage55 =>
if ((ap_block_pp0_stage55_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage56;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage55;
end if;
when ap_ST_fsm_pp0_stage56 =>
if ((ap_block_pp0_stage56_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage57;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage56;
end if;
when ap_ST_fsm_pp0_stage57 =>
if ((ap_block_pp0_stage57_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage58;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage57;
end if;
when ap_ST_fsm_pp0_stage58 =>
if ((ap_block_pp0_stage58_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage59;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage58;
end if;
when ap_ST_fsm_pp0_stage59 =>
if ((ap_block_pp0_stage59_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage60;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage59;
end if;
when ap_ST_fsm_pp0_stage60 =>
if ((ap_block_pp0_stage60_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage61;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage60;
end if;
when ap_ST_fsm_pp0_stage61 =>
if ((ap_block_pp0_stage61_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage62;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage61;
end if;
when ap_ST_fsm_pp0_stage62 =>
if ((ap_block_pp0_stage62_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage63;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage62;
end if;
when ap_ST_fsm_pp0_stage63 =>
if ((ap_block_pp0_stage63_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage64;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage63;
end if;
when ap_ST_fsm_pp0_stage64 =>
if ((ap_block_pp0_stage64_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage65;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage64;
end if;
when ap_ST_fsm_pp0_stage65 =>
if ((ap_block_pp0_stage65_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage66;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage65;
end if;
when ap_ST_fsm_pp0_stage66 =>
if ((ap_block_pp0_stage66_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage67;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage66;
end if;
when ap_ST_fsm_pp0_stage67 =>
if ((ap_block_pp0_stage67_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage68;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage67;
end if;
when ap_ST_fsm_pp0_stage68 =>
if ((ap_block_pp0_stage68_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage69;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage68;
end if;
when ap_ST_fsm_pp0_stage69 =>
if ((ap_block_pp0_stage69_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage70;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage69;
end if;
when ap_ST_fsm_pp0_stage70 =>
if ((ap_block_pp0_stage70_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage71;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage70;
end if;
when ap_ST_fsm_pp0_stage71 =>
if ((ap_block_pp0_stage71_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage72;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage71;
end if;
when ap_ST_fsm_pp0_stage72 =>
if ((ap_block_pp0_stage72_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage73;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage72;
end if;
when ap_ST_fsm_pp0_stage73 =>
if ((ap_block_pp0_stage73_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage74;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage73;
end if;
when ap_ST_fsm_pp0_stage74 =>
if ((ap_block_pp0_stage74_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage75;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage74;
end if;
when ap_ST_fsm_pp0_stage75 =>
if ((ap_block_pp0_stage75_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage76;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage75;
end if;
when ap_ST_fsm_pp0_stage76 =>
if ((ap_block_pp0_stage76_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage76;
end if;
when ap_ST_fsm_state80 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(1);
ap_CS_fsm_pp0_stage1 <= ap_CS_fsm(2);
ap_CS_fsm_pp0_stage10 <= ap_CS_fsm(11);
ap_CS_fsm_pp0_stage11 <= ap_CS_fsm(12);
ap_CS_fsm_pp0_stage12 <= ap_CS_fsm(13);
ap_CS_fsm_pp0_stage13 <= ap_CS_fsm(14);
ap_CS_fsm_pp0_stage14 <= ap_CS_fsm(15);
ap_CS_fsm_pp0_stage15 <= ap_CS_fsm(16);
ap_CS_fsm_pp0_stage16 <= ap_CS_fsm(17);
ap_CS_fsm_pp0_stage17 <= ap_CS_fsm(18);
ap_CS_fsm_pp0_stage18 <= ap_CS_fsm(19);
ap_CS_fsm_pp0_stage19 <= ap_CS_fsm(20);
ap_CS_fsm_pp0_stage2 <= ap_CS_fsm(3);
ap_CS_fsm_pp0_stage20 <= ap_CS_fsm(21);
ap_CS_fsm_pp0_stage21 <= ap_CS_fsm(22);
ap_CS_fsm_pp0_stage22 <= ap_CS_fsm(23);
ap_CS_fsm_pp0_stage23 <= ap_CS_fsm(24);
ap_CS_fsm_pp0_stage24 <= ap_CS_fsm(25);
ap_CS_fsm_pp0_stage25 <= ap_CS_fsm(26);
ap_CS_fsm_pp0_stage26 <= ap_CS_fsm(27);
ap_CS_fsm_pp0_stage27 <= ap_CS_fsm(28);
ap_CS_fsm_pp0_stage28 <= ap_CS_fsm(29);
ap_CS_fsm_pp0_stage29 <= ap_CS_fsm(30);
ap_CS_fsm_pp0_stage3 <= ap_CS_fsm(4);
ap_CS_fsm_pp0_stage30 <= ap_CS_fsm(31);
ap_CS_fsm_pp0_stage31 <= ap_CS_fsm(32);
ap_CS_fsm_pp0_stage32 <= ap_CS_fsm(33);
ap_CS_fsm_pp0_stage33 <= ap_CS_fsm(34);
ap_CS_fsm_pp0_stage34 <= ap_CS_fsm(35);
ap_CS_fsm_pp0_stage35 <= ap_CS_fsm(36);
ap_CS_fsm_pp0_stage36 <= ap_CS_fsm(37);
ap_CS_fsm_pp0_stage37 <= ap_CS_fsm(38);
ap_CS_fsm_pp0_stage38 <= ap_CS_fsm(39);
ap_CS_fsm_pp0_stage39 <= ap_CS_fsm(40);
ap_CS_fsm_pp0_stage4 <= ap_CS_fsm(5);
ap_CS_fsm_pp0_stage40 <= ap_CS_fsm(41);
ap_CS_fsm_pp0_stage41 <= ap_CS_fsm(42);
ap_CS_fsm_pp0_stage42 <= ap_CS_fsm(43);
ap_CS_fsm_pp0_stage43 <= ap_CS_fsm(44);
ap_CS_fsm_pp0_stage44 <= ap_CS_fsm(45);
ap_CS_fsm_pp0_stage45 <= ap_CS_fsm(46);
ap_CS_fsm_pp0_stage46 <= ap_CS_fsm(47);
ap_CS_fsm_pp0_stage47 <= ap_CS_fsm(48);
ap_CS_fsm_pp0_stage48 <= ap_CS_fsm(49);
ap_CS_fsm_pp0_stage49 <= ap_CS_fsm(50);
ap_CS_fsm_pp0_stage5 <= ap_CS_fsm(6);
ap_CS_fsm_pp0_stage50 <= ap_CS_fsm(51);
ap_CS_fsm_pp0_stage51 <= ap_CS_fsm(52);
ap_CS_fsm_pp0_stage52 <= ap_CS_fsm(53);
ap_CS_fsm_pp0_stage53 <= ap_CS_fsm(54);
ap_CS_fsm_pp0_stage54 <= ap_CS_fsm(55);
ap_CS_fsm_pp0_stage55 <= ap_CS_fsm(56);
ap_CS_fsm_pp0_stage56 <= ap_CS_fsm(57);
ap_CS_fsm_pp0_stage57 <= ap_CS_fsm(58);
ap_CS_fsm_pp0_stage58 <= ap_CS_fsm(59);
ap_CS_fsm_pp0_stage59 <= ap_CS_fsm(60);
ap_CS_fsm_pp0_stage6 <= ap_CS_fsm(7);
ap_CS_fsm_pp0_stage60 <= ap_CS_fsm(61);
ap_CS_fsm_pp0_stage61 <= ap_CS_fsm(62);
ap_CS_fsm_pp0_stage62 <= ap_CS_fsm(63);
ap_CS_fsm_pp0_stage63 <= ap_CS_fsm(64);
ap_CS_fsm_pp0_stage64 <= ap_CS_fsm(65);
ap_CS_fsm_pp0_stage65 <= ap_CS_fsm(66);
ap_CS_fsm_pp0_stage66 <= ap_CS_fsm(67);
ap_CS_fsm_pp0_stage67 <= ap_CS_fsm(68);
ap_CS_fsm_pp0_stage68 <= ap_CS_fsm(69);
ap_CS_fsm_pp0_stage69 <= ap_CS_fsm(70);
ap_CS_fsm_pp0_stage7 <= ap_CS_fsm(8);
ap_CS_fsm_pp0_stage70 <= ap_CS_fsm(71);
ap_CS_fsm_pp0_stage71 <= ap_CS_fsm(72);
ap_CS_fsm_pp0_stage72 <= ap_CS_fsm(73);
ap_CS_fsm_pp0_stage76 <= ap_CS_fsm(77);
ap_CS_fsm_pp0_stage8 <= ap_CS_fsm(9);
ap_CS_fsm_pp0_stage9 <= ap_CS_fsm(10);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state80 <= ap_CS_fsm(78);
ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011001_assign_proc : process(tmp_reg_1932, ap_enable_reg_pp0_iter1, buffer_V_BVALID)
begin
ap_block_pp0_stage0_flag00011001 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = buffer_V_BVALID));
end process;
ap_block_pp0_stage0_flag00011011_assign_proc : process(tmp_reg_1932, ap_enable_reg_pp0_iter1, buffer_V_BVALID)
begin
ap_block_pp0_stage0_flag00011011 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = buffer_V_BVALID));
end process;
ap_block_pp0_stage10_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage10_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage10_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage10_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage10_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage11_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage11_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage11_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage11_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage11_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage12_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage12_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage12_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage12_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage12_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage13_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage13_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage13_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage13_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage13_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage14_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage14_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage14_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage14_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage14_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage15_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage15_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage15_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage15_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage15_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage16_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage16_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage16_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage16_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage16_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage17_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage17_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage17_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage17_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage17_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage18_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage18_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage18_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage18_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage18_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage19_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage19_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage19_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage19_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage19_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage1_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state3_io)
begin
ap_block_pp0_stage1_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state3_io));
end process;
ap_block_pp0_stage1_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state3_io)
begin
ap_block_pp0_stage1_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state3_io));
end process;
ap_block_pp0_stage20_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage20_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage20_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage20_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage20_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage21_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage21_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage21_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage21_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage21_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage22_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage22_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage22_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage22_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage22_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage23_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage23_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage23_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage23_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage23_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage24_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage24_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage24_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage24_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage24_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage25_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage25_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage25_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage25_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage25_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage26_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage26_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage26_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage26_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage26_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage27_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage27_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage27_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage27_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage27_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage28_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage28_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage28_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage28_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage28_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage29_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage29_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage29_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage29_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage29_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage2_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage30_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage30_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage30_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage30_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage30_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage31_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage31_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage31_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage31_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage31_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage32_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage32_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage32_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage32_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage32_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage33_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage33_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage33_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage33_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage33_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage34_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage34_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage34_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage34_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage34_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage35_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage35_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage35_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage35_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage35_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage36_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage36_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage36_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage36_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage36_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage37_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage37_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage37_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage37_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage37_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage38_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage38_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage38_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage38_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage38_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage39_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage39_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage39_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage39_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage39_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage3_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage40_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage40_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage40_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state42_io)
begin
ap_block_pp0_stage40_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state42_io));
end process;
ap_block_pp0_stage40_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state42_io)
begin
ap_block_pp0_stage40_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state42_io));
end process;
ap_block_pp0_stage41_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage41_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage41_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state43_io)
begin
ap_block_pp0_stage41_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state43_io));
end process;
ap_block_pp0_stage41_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state43_io)
begin
ap_block_pp0_stage41_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state43_io));
end process;
ap_block_pp0_stage42_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage42_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage42_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state44_io)
begin
ap_block_pp0_stage42_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state44_io));
end process;
ap_block_pp0_stage42_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state44_io)
begin
ap_block_pp0_stage42_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state44_io));
end process;
ap_block_pp0_stage43_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage43_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage43_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state45_io)
begin
ap_block_pp0_stage43_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state45_io));
end process;
ap_block_pp0_stage43_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state45_io)
begin
ap_block_pp0_stage43_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state45_io));
end process;
ap_block_pp0_stage44_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage44_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage44_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state46_io)
begin
ap_block_pp0_stage44_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state46_io));
end process;
ap_block_pp0_stage44_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state46_io)
begin
ap_block_pp0_stage44_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state46_io));
end process;
ap_block_pp0_stage45_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage45_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage45_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state47_io)
begin
ap_block_pp0_stage45_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state47_io));
end process;
ap_block_pp0_stage45_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state47_io)
begin
ap_block_pp0_stage45_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state47_io));
end process;
ap_block_pp0_stage46_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage46_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage46_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state48_io)
begin
ap_block_pp0_stage46_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state48_io));
end process;
ap_block_pp0_stage46_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state48_io)
begin
ap_block_pp0_stage46_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state48_io));
end process;
ap_block_pp0_stage47_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage47_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage47_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state49_io)
begin
ap_block_pp0_stage47_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state49_io));
end process;
ap_block_pp0_stage47_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state49_io)
begin
ap_block_pp0_stage47_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state49_io));
end process;
ap_block_pp0_stage48_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage48_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage48_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state50_io)
begin
ap_block_pp0_stage48_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state50_io));
end process;
ap_block_pp0_stage48_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state50_io)
begin
ap_block_pp0_stage48_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state50_io));
end process;
ap_block_pp0_stage49_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage49_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage49_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state51_io)
begin
ap_block_pp0_stage49_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state51_io));
end process;
ap_block_pp0_stage49_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state51_io)
begin
ap_block_pp0_stage49_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state51_io));
end process;
ap_block_pp0_stage4_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage50_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage50_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage50_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state52_io)
begin
ap_block_pp0_stage50_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state52_io));
end process;
ap_block_pp0_stage50_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state52_io)
begin
ap_block_pp0_stage50_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state52_io));
end process;
ap_block_pp0_stage51_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage51_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage51_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state53_io)
begin
ap_block_pp0_stage51_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state53_io));
end process;
ap_block_pp0_stage51_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state53_io)
begin
ap_block_pp0_stage51_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state53_io));
end process;
ap_block_pp0_stage52_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage52_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage52_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state54_io)
begin
ap_block_pp0_stage52_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state54_io));
end process;
ap_block_pp0_stage52_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state54_io)
begin
ap_block_pp0_stage52_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state54_io));
end process;
ap_block_pp0_stage53_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage53_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage53_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state55_io)
begin
ap_block_pp0_stage53_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state55_io));
end process;
ap_block_pp0_stage53_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state55_io)
begin
ap_block_pp0_stage53_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state55_io));
end process;
ap_block_pp0_stage54_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage54_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage54_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state56_io)
begin
ap_block_pp0_stage54_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state56_io));
end process;
ap_block_pp0_stage54_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state56_io)
begin
ap_block_pp0_stage54_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state56_io));
end process;
ap_block_pp0_stage55_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage55_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage55_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state57_io)
begin
ap_block_pp0_stage55_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state57_io));
end process;
ap_block_pp0_stage55_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state57_io)
begin
ap_block_pp0_stage55_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state57_io));
end process;
ap_block_pp0_stage56_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage56_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage56_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state58_io)
begin
ap_block_pp0_stage56_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state58_io));
end process;
ap_block_pp0_stage56_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state58_io)
begin
ap_block_pp0_stage56_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state58_io));
end process;
ap_block_pp0_stage57_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage57_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage57_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state59_io)
begin
ap_block_pp0_stage57_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state59_io));
end process;
ap_block_pp0_stage57_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state59_io)
begin
ap_block_pp0_stage57_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state59_io));
end process;
ap_block_pp0_stage58_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage58_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage58_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state60_io)
begin
ap_block_pp0_stage58_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state60_io));
end process;
ap_block_pp0_stage58_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state60_io)
begin
ap_block_pp0_stage58_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state60_io));
end process;
ap_block_pp0_stage59_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage59_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage59_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state61_io)
begin
ap_block_pp0_stage59_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state61_io));
end process;
ap_block_pp0_stage59_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state61_io)
begin
ap_block_pp0_stage59_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state61_io));
end process;
ap_block_pp0_stage5_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage60_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage60_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage60_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state62_io)
begin
ap_block_pp0_stage60_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state62_io));
end process;
ap_block_pp0_stage60_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state62_io)
begin
ap_block_pp0_stage60_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state62_io));
end process;
ap_block_pp0_stage61_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage61_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage61_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state63_io)
begin
ap_block_pp0_stage61_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state63_io));
end process;
ap_block_pp0_stage61_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state63_io)
begin
ap_block_pp0_stage61_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state63_io));
end process;
ap_block_pp0_stage62_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage62_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage62_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state64_io)
begin
ap_block_pp0_stage62_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state64_io));
end process;
ap_block_pp0_stage62_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state64_io)
begin
ap_block_pp0_stage62_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state64_io));
end process;
ap_block_pp0_stage63_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage63_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage63_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state65_io)
begin
ap_block_pp0_stage63_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state65_io));
end process;
ap_block_pp0_stage63_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state65_io)
begin
ap_block_pp0_stage63_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state65_io));
end process;
ap_block_pp0_stage64_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage64_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage64_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state66_io)
begin
ap_block_pp0_stage64_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state66_io));
end process;
ap_block_pp0_stage64_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state66_io)
begin
ap_block_pp0_stage64_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state66_io));
end process;
ap_block_pp0_stage65_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage65_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage65_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state67_io)
begin
ap_block_pp0_stage65_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state67_io));
end process;
ap_block_pp0_stage65_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state67_io)
begin
ap_block_pp0_stage65_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state67_io));
end process;
ap_block_pp0_stage66_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage66_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage66_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state68_io)
begin
ap_block_pp0_stage66_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state68_io));
end process;
ap_block_pp0_stage66_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state68_io)
begin
ap_block_pp0_stage66_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state68_io));
end process;
ap_block_pp0_stage67_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage67_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage67_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state69_io)
begin
ap_block_pp0_stage67_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state69_io));
end process;
ap_block_pp0_stage67_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state69_io)
begin
ap_block_pp0_stage67_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state69_io));
end process;
ap_block_pp0_stage68_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage68_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage68_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state70_io)
begin
ap_block_pp0_stage68_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state70_io));
end process;
ap_block_pp0_stage68_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state70_io)
begin
ap_block_pp0_stage68_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state70_io));
end process;
ap_block_pp0_stage69_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage69_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage69_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state71_io)
begin
ap_block_pp0_stage69_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state71_io));
end process;
ap_block_pp0_stage69_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state71_io)
begin
ap_block_pp0_stage69_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state71_io));
end process;
ap_block_pp0_stage6_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage70_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage70_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage70_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state72_io)
begin
ap_block_pp0_stage70_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state72_io));
end process;
ap_block_pp0_stage70_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state72_io)
begin
ap_block_pp0_stage70_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state72_io));
end process;
ap_block_pp0_stage71_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage71_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage71_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state73_io)
begin
ap_block_pp0_stage71_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state73_io));
end process;
ap_block_pp0_stage71_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state73_io)
begin
ap_block_pp0_stage71_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state73_io));
end process;
ap_block_pp0_stage72_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage72_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage72_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state74_io)
begin
ap_block_pp0_stage72_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state74_io));
end process;
ap_block_pp0_stage72_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state74_io)
begin
ap_block_pp0_stage72_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state74_io));
end process;
ap_block_pp0_stage73_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage73_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage74_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage74_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage75_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage75_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage76_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage76_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage8_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage8_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage8_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage8_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage8_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage9_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage9_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage9_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_pp0_stage9_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_pp0_stage9_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state1_assign_proc : process(ap_start, length_r_ap_vld_in_sig)
begin
ap_block_state1 <= ((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = length_r_ap_vld_in_sig));
end process;
ap_block_state10_pp0_stage8_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state10_pp0_stage8_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state11_pp0_stage9_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state11_pp0_stage9_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state12_pp0_stage10_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state12_pp0_stage10_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state13_pp0_stage11_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state13_pp0_stage11_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state14_pp0_stage12_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state14_pp0_stage12_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state15_pp0_stage13_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state15_pp0_stage13_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state16_pp0_stage14_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state16_pp0_stage14_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state17_pp0_stage15_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state17_pp0_stage15_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state18_pp0_stage16_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state18_pp0_stage16_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state19_pp0_stage17_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state19_pp0_stage17_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state20_pp0_stage18_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state20_pp0_stage18_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state21_pp0_stage19_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state21_pp0_stage19_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state22_pp0_stage20_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state22_pp0_stage20_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state23_pp0_stage21_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state23_pp0_stage21_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state24_pp0_stage22_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state24_pp0_stage22_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state25_pp0_stage23_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state25_pp0_stage23_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state26_pp0_stage24_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state26_pp0_stage24_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state27_pp0_stage25_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state27_pp0_stage25_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state28_pp0_stage26_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state28_pp0_stage26_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state29_pp0_stage27_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state29_pp0_stage27_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state2_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state30_pp0_stage28_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state30_pp0_stage28_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state31_pp0_stage29_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state31_pp0_stage29_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state32_pp0_stage30_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state32_pp0_stage30_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state33_pp0_stage31_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state33_pp0_stage31_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state34_pp0_stage32_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state34_pp0_stage32_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state35_pp0_stage33_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state35_pp0_stage33_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state36_pp0_stage34_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state36_pp0_stage34_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state37_pp0_stage35_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state37_pp0_stage35_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state38_pp0_stage36_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state38_pp0_stage36_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state39_pp0_stage37_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state39_pp0_stage37_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state3_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_ARREADY)
begin
ap_block_state3_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_ARREADY));
end process;
ap_block_state3_pp0_stage1_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state40_pp0_stage38_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state40_pp0_stage38_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state41_pp0_stage39_iter0_assign_proc : process(tmp_reg_1932, buffer_V_RVALID)
begin
ap_block_state41_pp0_stage39_iter0 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_RVALID));
end process;
ap_block_state42_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_AWREADY)
begin
ap_block_state42_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_AWREADY));
end process;
ap_block_state42_pp0_stage40_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state43_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state43_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state43_pp0_stage41_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state44_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state44_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state44_pp0_stage42_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state45_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state45_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state45_pp0_stage43_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state46_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state46_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state46_pp0_stage44_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state47_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state47_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state47_pp0_stage45_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state48_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state48_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state48_pp0_stage46_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state49_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state49_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state49_pp0_stage47_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage2_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state50_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state50_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state50_pp0_stage48_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state51_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state51_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state51_pp0_stage49_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state52_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state52_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state52_pp0_stage50_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state53_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state53_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state53_pp0_stage51_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state54_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state54_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state54_pp0_stage52_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state55_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state55_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state55_pp0_stage53_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state56_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state56_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state56_pp0_stage54_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state57_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state57_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state57_pp0_stage55_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state58_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state58_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state58_pp0_stage56_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state59_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state59_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state59_pp0_stage57_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state5_pp0_stage3_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state60_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state60_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state60_pp0_stage58_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state61_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state61_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state61_pp0_stage59_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state62_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state62_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state62_pp0_stage60_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state63_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state63_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state63_pp0_stage61_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state64_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state64_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state64_pp0_stage62_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state65_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state65_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state65_pp0_stage63_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state66_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state66_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state66_pp0_stage64_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state67_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state67_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state67_pp0_stage65_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state68_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state68_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state68_pp0_stage66_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state69_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state69_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state69_pp0_stage67_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp0_stage4_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state70_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state70_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state70_pp0_stage68_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state71_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state71_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state71_pp0_stage69_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state72_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state72_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state72_pp0_stage70_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state73_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state73_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state73_pp0_stage71_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state74_io_assign_proc : process(tmp_reg_1932, ap_sig_ioackin_buffer_V_WREADY)
begin
ap_block_state74_io <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_buffer_V_WREADY));
end process;
ap_block_state74_pp0_stage72_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state75_pp0_stage73_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state76_pp0_stage74_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state77_pp0_stage75_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state78_pp0_stage76_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state79_pp0_stage0_iter1_assign_proc : process(tmp_reg_1932, buffer_V_BVALID)
begin
ap_block_state79_pp0_stage0_iter1 <= ((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_0 = buffer_V_BVALID));
end process;
ap_block_state7_pp0_stage5_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage6_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp0_stage7_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_condition_7926_assign_proc : process(ap_CS_fsm_pp0_stage1, ap_enable_reg_pp0_iter0, tmp_reg_1932)
begin
ap_condition_7926 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0));
end process;
ap_condition_7931_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, ap_CS_fsm_pp0_stage40)
begin
ap_condition_7931 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40));
end process;
ap_condition_7969_assign_proc : process(ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00000000, ap_predicate_op143_call_state3)
begin
ap_condition_7969 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op143_call_state3));
end process;
ap_condition_7973_assign_proc : process(ap_CS_fsm_pp0_stage2, ap_predicate_op152_call_state4, ap_block_pp0_stage2_flag00000000)
begin
ap_condition_7973 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_boolean_1 = ap_predicate_op152_call_state4) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0));
end process;
ap_condition_7977_assign_proc : process(ap_CS_fsm_pp0_stage3, ap_predicate_op162_call_state5, ap_block_pp0_stage3_flag00000000)
begin
ap_condition_7977 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_boolean_1 = ap_predicate_op162_call_state5) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0));
end process;
ap_condition_7981_assign_proc : process(ap_CS_fsm_pp0_stage4, ap_predicate_op173_call_state6, ap_block_pp0_stage4_flag00000000)
begin
ap_condition_7981 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_boolean_1 = ap_predicate_op173_call_state6) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0));
end process;
ap_condition_7985_assign_proc : process(ap_CS_fsm_pp0_stage5, ap_predicate_op185_call_state7, ap_block_pp0_stage5_flag00000000)
begin
ap_condition_7985 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_boolean_1 = ap_predicate_op185_call_state7) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0));
end process;
ap_condition_7989_assign_proc : process(ap_CS_fsm_pp0_stage6, ap_predicate_op198_call_state8, ap_block_pp0_stage6_flag00000000)
begin
ap_condition_7989 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_boolean_1 = ap_predicate_op198_call_state8) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0));
end process;
ap_condition_7993_assign_proc : process(ap_CS_fsm_pp0_stage7, ap_predicate_op212_call_state9, ap_block_pp0_stage7_flag00000000)
begin
ap_condition_7993 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_boolean_1 = ap_predicate_op212_call_state9) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0));
end process;
ap_condition_7997_assign_proc : process(ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00000000, ap_predicate_op227_call_state10)
begin
ap_condition_7997 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op227_call_state10));
end process;
ap_condition_8001_assign_proc : process(ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00000000, ap_predicate_op243_call_state11)
begin
ap_condition_8001 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op243_call_state11));
end process;
ap_condition_8005_assign_proc : process(ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00000000, ap_predicate_op260_call_state12)
begin
ap_condition_8005 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op260_call_state12));
end process;
ap_condition_8008_assign_proc : process(ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00000000, ap_predicate_op324_call_state13)
begin
ap_condition_8008 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op324_call_state13));
end process;
ap_condition_8011_assign_proc : process(ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00000000, ap_predicate_op387_call_state14)
begin
ap_condition_8011 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op387_call_state14));
end process;
ap_condition_8014_assign_proc : process(ap_CS_fsm_pp0_stage13, ap_block_pp0_stage13_flag00000000, ap_predicate_op409_call_state15)
begin
ap_condition_8014 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op409_call_state15));
end process;
ap_condition_8017_assign_proc : process(ap_CS_fsm_pp0_stage14, ap_block_pp0_stage14_flag00000000, ap_predicate_op431_call_state16)
begin
ap_condition_8017 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op431_call_state16));
end process;
ap_condition_8020_assign_proc : process(ap_CS_fsm_pp0_stage15, ap_block_pp0_stage15_flag00000000, ap_predicate_op453_call_state17)
begin
ap_condition_8020 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op453_call_state17));
end process;
ap_condition_8023_assign_proc : process(ap_CS_fsm_pp0_stage16, ap_block_pp0_stage16_flag00000000, ap_predicate_op475_call_state18)
begin
ap_condition_8023 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op475_call_state18));
end process;
ap_condition_8026_assign_proc : process(ap_CS_fsm_pp0_stage17, ap_block_pp0_stage17_flag00000000, ap_predicate_op497_call_state19)
begin
ap_condition_8026 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op497_call_state19));
end process;
ap_condition_8029_assign_proc : process(ap_CS_fsm_pp0_stage18, ap_block_pp0_stage18_flag00000000, ap_predicate_op519_call_state20)
begin
ap_condition_8029 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op519_call_state20));
end process;
ap_condition_8032_assign_proc : process(ap_CS_fsm_pp0_stage19, ap_block_pp0_stage19_flag00000000, ap_predicate_op541_call_state21)
begin
ap_condition_8032 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op541_call_state21));
end process;
ap_condition_8035_assign_proc : process(ap_CS_fsm_pp0_stage20, ap_block_pp0_stage20_flag00000000, ap_predicate_op563_call_state22)
begin
ap_condition_8035 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op563_call_state22));
end process;
ap_condition_8038_assign_proc : process(ap_CS_fsm_pp0_stage21, ap_block_pp0_stage21_flag00000000, ap_predicate_op585_call_state23)
begin
ap_condition_8038 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op585_call_state23));
end process;
ap_condition_8041_assign_proc : process(ap_CS_fsm_pp0_stage22, ap_block_pp0_stage22_flag00000000, ap_predicate_op607_call_state24)
begin
ap_condition_8041 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op607_call_state24));
end process;
ap_condition_8044_assign_proc : process(ap_CS_fsm_pp0_stage23, ap_block_pp0_stage23_flag00000000, ap_predicate_op629_call_state25)
begin
ap_condition_8044 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op629_call_state25));
end process;
ap_condition_8047_assign_proc : process(ap_CS_fsm_pp0_stage24, ap_block_pp0_stage24_flag00000000, ap_predicate_op651_call_state26)
begin
ap_condition_8047 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op651_call_state26));
end process;
ap_condition_8050_assign_proc : process(ap_CS_fsm_pp0_stage25, ap_block_pp0_stage25_flag00000000, ap_predicate_op673_call_state27)
begin
ap_condition_8050 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op673_call_state27));
end process;
ap_condition_8053_assign_proc : process(ap_CS_fsm_pp0_stage26, ap_block_pp0_stage26_flag00000000, ap_predicate_op695_call_state28)
begin
ap_condition_8053 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op695_call_state28));
end process;
ap_condition_8056_assign_proc : process(ap_CS_fsm_pp0_stage27, ap_block_pp0_stage27_flag00000000, ap_predicate_op717_call_state29)
begin
ap_condition_8056 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op717_call_state29));
end process;
ap_condition_8059_assign_proc : process(ap_CS_fsm_pp0_stage28, ap_block_pp0_stage28_flag00000000, ap_predicate_op739_call_state30)
begin
ap_condition_8059 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op739_call_state30));
end process;
ap_condition_8062_assign_proc : process(ap_CS_fsm_pp0_stage29, ap_block_pp0_stage29_flag00000000, ap_predicate_op761_call_state31)
begin
ap_condition_8062 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op761_call_state31));
end process;
ap_condition_8065_assign_proc : process(ap_CS_fsm_pp0_stage30, ap_block_pp0_stage30_flag00000000, ap_predicate_op783_call_state32)
begin
ap_condition_8065 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op783_call_state32));
end process;
ap_condition_8068_assign_proc : process(ap_CS_fsm_pp0_stage31, ap_block_pp0_stage31_flag00000000, ap_predicate_op805_call_state33)
begin
ap_condition_8068 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op805_call_state33));
end process;
ap_condition_8071_assign_proc : process(ap_CS_fsm_pp0_stage32, ap_block_pp0_stage32_flag00000000, ap_predicate_op827_call_state34)
begin
ap_condition_8071 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op827_call_state34));
end process;
ap_condition_pp0_exit_iter0_state2_assign_proc : process(tmp_fu_809_p3)
begin
if ((tmp_fu_809_p3 = ap_const_lv1_1)) then
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_CS_fsm_state80)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state80)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_predicate_op143_call_state3_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936)
begin
ap_predicate_op143_call_state3 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1));
end process;
ap_predicate_op143_call_state3_state2_assign_proc : process(tmp_fu_809_p3, tmp_66_fu_821_p2)
begin
ap_predicate_op143_call_state3_state2 <= ((ap_const_lv1_0 = tmp_fu_809_p3) and (tmp_66_fu_821_p2 = ap_const_lv1_1));
end process;
ap_predicate_op152_call_state4_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991)
begin
ap_predicate_op152_call_state4 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1));
end process;
ap_predicate_op152_call_state4_state3_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_fu_861_p2)
begin
ap_predicate_op152_call_state4_state3 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_fu_861_p2 = ap_const_lv1_1));
end process;
ap_predicate_op162_call_state5_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001)
begin
ap_predicate_op162_call_state5 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001));
end process;
ap_predicate_op162_call_state5_state4_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_fu_884_p2)
begin
ap_predicate_op162_call_state5_state4 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_fu_884_p2));
end process;
ap_predicate_op173_call_state6_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011)
begin
ap_predicate_op173_call_state6 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011));
end process;
ap_predicate_op173_call_state6_state5_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_fu_907_p2)
begin
ap_predicate_op173_call_state6_state5 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_fu_907_p2));
end process;
ap_predicate_op185_call_state7_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021)
begin
ap_predicate_op185_call_state7 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021));
end process;
ap_predicate_op185_call_state7_state6_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_fu_930_p2)
begin
ap_predicate_op185_call_state7_state6 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_fu_930_p2));
end process;
ap_predicate_op198_call_state8_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031)
begin
ap_predicate_op198_call_state8 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031));
end process;
ap_predicate_op198_call_state8_state7_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_fu_953_p2)
begin
ap_predicate_op198_call_state8_state7 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_fu_953_p2));
end process;
ap_predicate_op212_call_state9_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041)
begin
ap_predicate_op212_call_state9 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041));
end process;
ap_predicate_op212_call_state9_state8_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_fu_976_p2)
begin
ap_predicate_op212_call_state9_state8 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_fu_976_p2));
end process;
ap_predicate_op227_call_state10_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051)
begin
ap_predicate_op227_call_state10 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051));
end process;
ap_predicate_op227_call_state10_state9_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_fu_999_p2)
begin
ap_predicate_op227_call_state10_state9 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_fu_999_p2));
end process;
ap_predicate_op243_call_state11_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061)
begin
ap_predicate_op243_call_state11 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061));
end process;
ap_predicate_op243_call_state11_state10_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_fu_1022_p2)
begin
ap_predicate_op243_call_state11_state10 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_fu_1022_p2));
end process;
ap_predicate_op260_call_state12_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071)
begin
ap_predicate_op260_call_state12 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071));
end process;
ap_predicate_op260_call_state12_state11_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_fu_1045_p2)
begin
ap_predicate_op260_call_state12_state11 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_fu_1045_p2));
end process;
ap_predicate_op307_call_state13_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936)
begin
ap_predicate_op307_call_state13 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1));
end process;
ap_predicate_op324_call_state13_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081)
begin
ap_predicate_op324_call_state13 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081));
end process;
ap_predicate_op324_call_state13_state12_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_fu_1068_p2)
begin
ap_predicate_op324_call_state13_state12 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_fu_1068_p2));
end process;
ap_predicate_op370_call_state14_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991)
begin
ap_predicate_op370_call_state14 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1));
end process;
ap_predicate_op387_call_state14_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211)
begin
ap_predicate_op387_call_state14 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211));
end process;
ap_predicate_op387_call_state14_state13_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_fu_1271_p2)
begin
ap_predicate_op387_call_state14_state13 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_fu_1271_p2));
end process;
ap_predicate_op392_call_state15_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001)
begin
ap_predicate_op392_call_state15 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001));
end process;
ap_predicate_op409_call_state15_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215)
begin
ap_predicate_op409_call_state15 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215));
end process;
ap_predicate_op409_call_state15_state14_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215)
begin
ap_predicate_op409_call_state15_state14 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215));
end process;
ap_predicate_op414_call_state16_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011)
begin
ap_predicate_op414_call_state16 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011));
end process;
ap_predicate_op431_call_state16_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219)
begin
ap_predicate_op431_call_state16 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219));
end process;
ap_predicate_op431_call_state16_state15_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219)
begin
ap_predicate_op431_call_state16_state15 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219));
end process;
ap_predicate_op436_call_state17_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021)
begin
ap_predicate_op436_call_state17 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021));
end process;
ap_predicate_op453_call_state17_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223)
begin
ap_predicate_op453_call_state17 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223));
end process;
ap_predicate_op453_call_state17_state16_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223)
begin
ap_predicate_op453_call_state17_state16 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223));
end process;
ap_predicate_op458_call_state18_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031)
begin
ap_predicate_op458_call_state18 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031));
end process;
ap_predicate_op475_call_state18_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227)
begin
ap_predicate_op475_call_state18 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227));
end process;
ap_predicate_op475_call_state18_state17_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227)
begin
ap_predicate_op475_call_state18_state17 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227));
end process;
ap_predicate_op480_call_state19_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041)
begin
ap_predicate_op480_call_state19 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041));
end process;
ap_predicate_op497_call_state19_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231)
begin
ap_predicate_op497_call_state19 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231));
end process;
ap_predicate_op497_call_state19_state18_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231)
begin
ap_predicate_op497_call_state19_state18 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231));
end process;
ap_predicate_op502_call_state20_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051)
begin
ap_predicate_op502_call_state20 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051));
end process;
ap_predicate_op519_call_state20_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235)
begin
ap_predicate_op519_call_state20 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235));
end process;
ap_predicate_op519_call_state20_state19_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235)
begin
ap_predicate_op519_call_state20_state19 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235));
end process;
ap_predicate_op524_call_state21_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061)
begin
ap_predicate_op524_call_state21 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061));
end process;
ap_predicate_op541_call_state21_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239)
begin
ap_predicate_op541_call_state21 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239));
end process;
ap_predicate_op541_call_state21_state20_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239)
begin
ap_predicate_op541_call_state21_state20 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239));
end process;
ap_predicate_op546_call_state22_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071)
begin
ap_predicate_op546_call_state22 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071));
end process;
ap_predicate_op563_call_state22_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243)
begin
ap_predicate_op563_call_state22 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243));
end process;
ap_predicate_op563_call_state22_state21_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243)
begin
ap_predicate_op563_call_state22_state21 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243));
end process;
ap_predicate_op568_call_state23_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081)
begin
ap_predicate_op568_call_state23 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081));
end process;
ap_predicate_op585_call_state23_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247)
begin
ap_predicate_op585_call_state23 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247));
end process;
ap_predicate_op585_call_state23_state22_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247)
begin
ap_predicate_op585_call_state23_state22 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247));
end process;
ap_predicate_op590_call_state24_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211)
begin
ap_predicate_op590_call_state24 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211));
end process;
ap_predicate_op607_call_state24_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251)
begin
ap_predicate_op607_call_state24 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251));
end process;
ap_predicate_op607_call_state24_state23_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251)
begin
ap_predicate_op607_call_state24_state23 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251));
end process;
ap_predicate_op612_call_state25_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215)
begin
ap_predicate_op612_call_state25 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215));
end process;
ap_predicate_op629_call_state25_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255)
begin
ap_predicate_op629_call_state25 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255));
end process;
ap_predicate_op629_call_state25_state24_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255)
begin
ap_predicate_op629_call_state25_state24 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255));
end process;
ap_predicate_op634_call_state26_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219)
begin
ap_predicate_op634_call_state26 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219));
end process;
ap_predicate_op651_call_state26_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255, tmp_5_22_reg_2259)
begin
ap_predicate_op651_call_state26 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255) and (ap_const_lv1_1 = tmp_5_22_reg_2259));
end process;
ap_predicate_op651_call_state26_state25_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255, tmp_5_22_reg_2259)
begin
ap_predicate_op651_call_state26_state25 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255) and (ap_const_lv1_1 = tmp_5_22_reg_2259));
end process;
ap_predicate_op656_call_state27_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223)
begin
ap_predicate_op656_call_state27 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223));
end process;
ap_predicate_op673_call_state27_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255, tmp_5_22_reg_2259, tmp_5_23_reg_2263)
begin
ap_predicate_op673_call_state27 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255) and (ap_const_lv1_1 = tmp_5_22_reg_2259) and (ap_const_lv1_1 = tmp_5_23_reg_2263));
end process;
ap_predicate_op673_call_state27_state26_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255, tmp_5_22_reg_2259, tmp_5_23_reg_2263)
begin
ap_predicate_op673_call_state27_state26 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255) and (ap_const_lv1_1 = tmp_5_22_reg_2259) and (ap_const_lv1_1 = tmp_5_23_reg_2263));
end process;
ap_predicate_op678_call_state28_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227)
begin
ap_predicate_op678_call_state28 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227));
end process;
ap_predicate_op695_call_state28_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255, tmp_5_22_reg_2259, tmp_5_23_reg_2263, tmp_5_24_reg_2267)
begin
ap_predicate_op695_call_state28 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255) and (ap_const_lv1_1 = tmp_5_22_reg_2259) and (ap_const_lv1_1 = tmp_5_23_reg_2263) and (ap_const_lv1_1 = tmp_5_24_reg_2267));
end process;
ap_predicate_op695_call_state28_state27_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255, tmp_5_22_reg_2259, tmp_5_23_reg_2263, tmp_5_24_reg_2267)
begin
ap_predicate_op695_call_state28_state27 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255) and (ap_const_lv1_1 = tmp_5_22_reg_2259) and (ap_const_lv1_1 = tmp_5_23_reg_2263) and (ap_const_lv1_1 = tmp_5_24_reg_2267));
end process;
ap_predicate_op700_call_state29_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231)
begin
ap_predicate_op700_call_state29 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231));
end process;
ap_predicate_op717_call_state29_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255, tmp_5_22_reg_2259, tmp_5_23_reg_2263, tmp_5_24_reg_2267, tmp_5_25_reg_2271)
begin
ap_predicate_op717_call_state29 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255) and (ap_const_lv1_1 = tmp_5_22_reg_2259) and (ap_const_lv1_1 = tmp_5_23_reg_2263) and (ap_const_lv1_1 = tmp_5_24_reg_2267) and (ap_const_lv1_1 = tmp_5_25_reg_2271));
end process;
ap_predicate_op717_call_state29_state28_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255, tmp_5_22_reg_2259, tmp_5_23_reg_2263, tmp_5_24_reg_2267, tmp_5_25_reg_2271)
begin
ap_predicate_op717_call_state29_state28 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255) and (ap_const_lv1_1 = tmp_5_22_reg_2259) and (ap_const_lv1_1 = tmp_5_23_reg_2263) and (ap_const_lv1_1 = tmp_5_24_reg_2267) and (ap_const_lv1_1 = tmp_5_25_reg_2271));
end process;
ap_predicate_op722_call_state30_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235)
begin
ap_predicate_op722_call_state30 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235));
end process;
ap_predicate_op739_call_state30_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255, tmp_5_22_reg_2259, tmp_5_23_reg_2263, tmp_5_24_reg_2267, tmp_5_25_reg_2271, tmp_5_26_reg_2275)
begin
ap_predicate_op739_call_state30 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255) and (ap_const_lv1_1 = tmp_5_22_reg_2259) and (ap_const_lv1_1 = tmp_5_23_reg_2263) and (ap_const_lv1_1 = tmp_5_24_reg_2267) and (ap_const_lv1_1 = tmp_5_25_reg_2271) and (ap_const_lv1_1 = tmp_5_26_reg_2275));
end process;
ap_predicate_op739_call_state30_state29_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255, tmp_5_22_reg_2259, tmp_5_23_reg_2263, tmp_5_24_reg_2267, tmp_5_25_reg_2271, tmp_5_26_reg_2275)
begin
ap_predicate_op739_call_state30_state29 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255) and (ap_const_lv1_1 = tmp_5_22_reg_2259) and (ap_const_lv1_1 = tmp_5_23_reg_2263) and (ap_const_lv1_1 = tmp_5_24_reg_2267) and (ap_const_lv1_1 = tmp_5_25_reg_2271) and (ap_const_lv1_1 = tmp_5_26_reg_2275));
end process;
ap_predicate_op744_call_state31_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239)
begin
ap_predicate_op744_call_state31 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239));
end process;
ap_predicate_op761_call_state31_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255, tmp_5_22_reg_2259, tmp_5_23_reg_2263, tmp_5_24_reg_2267, tmp_5_25_reg_2271, tmp_5_26_reg_2275, tmp_5_27_reg_2279)
begin
ap_predicate_op761_call_state31 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255) and (ap_const_lv1_1 = tmp_5_22_reg_2259) and (ap_const_lv1_1 = tmp_5_23_reg_2263) and (ap_const_lv1_1 = tmp_5_24_reg_2267) and (ap_const_lv1_1 = tmp_5_25_reg_2271) and (ap_const_lv1_1 = tmp_5_26_reg_2275) and (ap_const_lv1_1 = tmp_5_27_reg_2279));
end process;
ap_predicate_op761_call_state31_state30_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255, tmp_5_22_reg_2259, tmp_5_23_reg_2263, tmp_5_24_reg_2267, tmp_5_25_reg_2271, tmp_5_26_reg_2275, tmp_5_27_reg_2279)
begin
ap_predicate_op761_call_state31_state30 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255) and (ap_const_lv1_1 = tmp_5_22_reg_2259) and (ap_const_lv1_1 = tmp_5_23_reg_2263) and (ap_const_lv1_1 = tmp_5_24_reg_2267) and (ap_const_lv1_1 = tmp_5_25_reg_2271) and (ap_const_lv1_1 = tmp_5_26_reg_2275) and (ap_const_lv1_1 = tmp_5_27_reg_2279));
end process;
ap_predicate_op766_call_state32_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243)
begin
ap_predicate_op766_call_state32 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243));
end process;
ap_predicate_op783_call_state32_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255, tmp_5_22_reg_2259, tmp_5_23_reg_2263, tmp_5_24_reg_2267, tmp_5_25_reg_2271, tmp_5_26_reg_2275, tmp_5_27_reg_2279, tmp_5_28_reg_2283)
begin
ap_predicate_op783_call_state32 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255) and (ap_const_lv1_1 = tmp_5_22_reg_2259) and (ap_const_lv1_1 = tmp_5_23_reg_2263) and (ap_const_lv1_1 = tmp_5_24_reg_2267) and (ap_const_lv1_1 = tmp_5_25_reg_2271) and (ap_const_lv1_1 = tmp_5_26_reg_2275) and (ap_const_lv1_1 = tmp_5_27_reg_2279) and (ap_const_lv1_1 = tmp_5_28_reg_2283));
end process;
ap_predicate_op783_call_state32_state31_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255, tmp_5_22_reg_2259, tmp_5_23_reg_2263, tmp_5_24_reg_2267, tmp_5_25_reg_2271, tmp_5_26_reg_2275, tmp_5_27_reg_2279, tmp_5_28_reg_2283)
begin
ap_predicate_op783_call_state32_state31 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255) and (ap_const_lv1_1 = tmp_5_22_reg_2259) and (ap_const_lv1_1 = tmp_5_23_reg_2263) and (ap_const_lv1_1 = tmp_5_24_reg_2267) and (ap_const_lv1_1 = tmp_5_25_reg_2271) and (ap_const_lv1_1 = tmp_5_26_reg_2275) and (ap_const_lv1_1 = tmp_5_27_reg_2279) and (ap_const_lv1_1 = tmp_5_28_reg_2283));
end process;
ap_predicate_op788_call_state33_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247)
begin
ap_predicate_op788_call_state33 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247));
end process;
ap_predicate_op805_call_state33_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255, tmp_5_22_reg_2259, tmp_5_23_reg_2263, tmp_5_24_reg_2267, tmp_5_25_reg_2271, tmp_5_26_reg_2275, tmp_5_27_reg_2279, tmp_5_28_reg_2283, tmp_5_29_reg_2287)
begin
ap_predicate_op805_call_state33 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255) and (ap_const_lv1_1 = tmp_5_22_reg_2259) and (ap_const_lv1_1 = tmp_5_23_reg_2263) and (ap_const_lv1_1 = tmp_5_24_reg_2267) and (ap_const_lv1_1 = tmp_5_25_reg_2271) and (ap_const_lv1_1 = tmp_5_26_reg_2275) and (ap_const_lv1_1 = tmp_5_27_reg_2279) and (ap_const_lv1_1 = tmp_5_28_reg_2283) and (ap_const_lv1_1 = tmp_5_29_reg_2287));
end process;
ap_predicate_op805_call_state33_state32_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255, tmp_5_22_reg_2259, tmp_5_23_reg_2263, tmp_5_24_reg_2267, tmp_5_25_reg_2271, tmp_5_26_reg_2275, tmp_5_27_reg_2279, tmp_5_28_reg_2283, tmp_5_29_reg_2287)
begin
ap_predicate_op805_call_state33_state32 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255) and (ap_const_lv1_1 = tmp_5_22_reg_2259) and (ap_const_lv1_1 = tmp_5_23_reg_2263) and (ap_const_lv1_1 = tmp_5_24_reg_2267) and (ap_const_lv1_1 = tmp_5_25_reg_2271) and (ap_const_lv1_1 = tmp_5_26_reg_2275) and (ap_const_lv1_1 = tmp_5_27_reg_2279) and (ap_const_lv1_1 = tmp_5_28_reg_2283) and (ap_const_lv1_1 = tmp_5_29_reg_2287));
end process;
ap_predicate_op810_call_state34_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251)
begin
ap_predicate_op810_call_state34 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251));
end process;
ap_predicate_op827_call_state34_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255, tmp_5_22_reg_2259, tmp_5_23_reg_2263, tmp_5_24_reg_2267, tmp_5_25_reg_2271, tmp_5_26_reg_2275, tmp_5_27_reg_2279, tmp_5_28_reg_2283, tmp_5_29_reg_2287, tmp_5_30_reg_2291)
begin
ap_predicate_op827_call_state34 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255) and (ap_const_lv1_1 = tmp_5_22_reg_2259) and (ap_const_lv1_1 = tmp_5_23_reg_2263) and (ap_const_lv1_1 = tmp_5_24_reg_2267) and (ap_const_lv1_1 = tmp_5_25_reg_2271) and (ap_const_lv1_1 = tmp_5_26_reg_2275) and (ap_const_lv1_1 = tmp_5_27_reg_2279) and (ap_const_lv1_1 = tmp_5_28_reg_2283) and (ap_const_lv1_1 = tmp_5_29_reg_2287) and (ap_const_lv1_1 = tmp_5_30_reg_2291));
end process;
ap_predicate_op827_call_state34_state33_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255, tmp_5_22_reg_2259, tmp_5_23_reg_2263, tmp_5_24_reg_2267, tmp_5_25_reg_2271, tmp_5_26_reg_2275, tmp_5_27_reg_2279, tmp_5_28_reg_2283, tmp_5_29_reg_2287, tmp_5_30_reg_2291)
begin
ap_predicate_op827_call_state34_state33 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255) and (ap_const_lv1_1 = tmp_5_22_reg_2259) and (ap_const_lv1_1 = tmp_5_23_reg_2263) and (ap_const_lv1_1 = tmp_5_24_reg_2267) and (ap_const_lv1_1 = tmp_5_25_reg_2271) and (ap_const_lv1_1 = tmp_5_26_reg_2275) and (ap_const_lv1_1 = tmp_5_27_reg_2279) and (ap_const_lv1_1 = tmp_5_28_reg_2283) and (ap_const_lv1_1 = tmp_5_29_reg_2287) and (ap_const_lv1_1 = tmp_5_30_reg_2291));
end process;
ap_predicate_op832_call_state35_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255)
begin
ap_predicate_op832_call_state35 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255));
end process;
ap_predicate_op851_call_state36_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255, tmp_5_22_reg_2259)
begin
ap_predicate_op851_call_state36 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255) and (ap_const_lv1_1 = tmp_5_22_reg_2259));
end process;
ap_predicate_op869_call_state37_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255, tmp_5_22_reg_2259, tmp_5_23_reg_2263)
begin
ap_predicate_op869_call_state37 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255) and (ap_const_lv1_1 = tmp_5_22_reg_2259) and (ap_const_lv1_1 = tmp_5_23_reg_2263));
end process;
ap_predicate_op886_call_state38_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255, tmp_5_22_reg_2259, tmp_5_23_reg_2263, tmp_5_24_reg_2267)
begin
ap_predicate_op886_call_state38 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255) and (ap_const_lv1_1 = tmp_5_22_reg_2259) and (ap_const_lv1_1 = tmp_5_23_reg_2263) and (ap_const_lv1_1 = tmp_5_24_reg_2267));
end process;
ap_predicate_op902_call_state39_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255, tmp_5_22_reg_2259, tmp_5_23_reg_2263, tmp_5_24_reg_2267, tmp_5_25_reg_2271)
begin
ap_predicate_op902_call_state39 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255) and (ap_const_lv1_1 = tmp_5_22_reg_2259) and (ap_const_lv1_1 = tmp_5_23_reg_2263) and (ap_const_lv1_1 = tmp_5_24_reg_2267) and (ap_const_lv1_1 = tmp_5_25_reg_2271));
end process;
ap_predicate_op917_call_state40_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255, tmp_5_22_reg_2259, tmp_5_23_reg_2263, tmp_5_24_reg_2267, tmp_5_25_reg_2271, tmp_5_26_reg_2275)
begin
ap_predicate_op917_call_state40 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255) and (ap_const_lv1_1 = tmp_5_22_reg_2259) and (ap_const_lv1_1 = tmp_5_23_reg_2263) and (ap_const_lv1_1 = tmp_5_24_reg_2267) and (ap_const_lv1_1 = tmp_5_25_reg_2271) and (ap_const_lv1_1 = tmp_5_26_reg_2275));
end process;
ap_predicate_op931_call_state41_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255, tmp_5_22_reg_2259, tmp_5_23_reg_2263, tmp_5_24_reg_2267, tmp_5_25_reg_2271, tmp_5_26_reg_2275, tmp_5_27_reg_2279)
begin
ap_predicate_op931_call_state41 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255) and (ap_const_lv1_1 = tmp_5_22_reg_2259) and (ap_const_lv1_1 = tmp_5_23_reg_2263) and (ap_const_lv1_1 = tmp_5_24_reg_2267) and (ap_const_lv1_1 = tmp_5_25_reg_2271) and (ap_const_lv1_1 = tmp_5_26_reg_2275) and (ap_const_lv1_1 = tmp_5_27_reg_2279));
end process;
ap_predicate_op943_call_state42_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255, tmp_5_22_reg_2259, tmp_5_23_reg_2263, tmp_5_24_reg_2267, tmp_5_25_reg_2271, tmp_5_26_reg_2275, tmp_5_27_reg_2279, tmp_5_28_reg_2283)
begin
ap_predicate_op943_call_state42 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255) and (ap_const_lv1_1 = tmp_5_22_reg_2259) and (ap_const_lv1_1 = tmp_5_23_reg_2263) and (ap_const_lv1_1 = tmp_5_24_reg_2267) and (ap_const_lv1_1 = tmp_5_25_reg_2271) and (ap_const_lv1_1 = tmp_5_26_reg_2275) and (ap_const_lv1_1 = tmp_5_27_reg_2279) and (ap_const_lv1_1 = tmp_5_28_reg_2283));
end process;
ap_predicate_op955_call_state43_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255, tmp_5_22_reg_2259, tmp_5_23_reg_2263, tmp_5_24_reg_2267, tmp_5_25_reg_2271, tmp_5_26_reg_2275, tmp_5_27_reg_2279, tmp_5_28_reg_2283, tmp_5_29_reg_2287)
begin
ap_predicate_op955_call_state43 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255) and (ap_const_lv1_1 = tmp_5_22_reg_2259) and (ap_const_lv1_1 = tmp_5_23_reg_2263) and (ap_const_lv1_1 = tmp_5_24_reg_2267) and (ap_const_lv1_1 = tmp_5_25_reg_2271) and (ap_const_lv1_1 = tmp_5_26_reg_2275) and (ap_const_lv1_1 = tmp_5_27_reg_2279) and (ap_const_lv1_1 = tmp_5_28_reg_2283) and (ap_const_lv1_1 = tmp_5_29_reg_2287));
end process;
ap_predicate_op969_call_state44_assign_proc : process(tmp_reg_1932, tmp_66_reg_1936, tmp_5_1_reg_1991, tmp_5_2_reg_2001, tmp_5_3_reg_2011, tmp_5_4_reg_2021, tmp_5_5_reg_2031, tmp_5_6_reg_2041, tmp_5_7_reg_2051, tmp_5_8_reg_2061, tmp_5_9_reg_2071, tmp_5_s_reg_2081, tmp_5_10_reg_2211, tmp_5_11_reg_2215, tmp_5_12_reg_2219, tmp_5_13_reg_2223, tmp_5_14_reg_2227, tmp_5_15_reg_2231, tmp_5_16_reg_2235, tmp_5_17_reg_2239, tmp_5_18_reg_2243, tmp_5_19_reg_2247, tmp_5_20_reg_2251, tmp_5_21_reg_2255, tmp_5_22_reg_2259, tmp_5_23_reg_2263, tmp_5_24_reg_2267, tmp_5_25_reg_2271, tmp_5_26_reg_2275, tmp_5_27_reg_2279, tmp_5_28_reg_2283, tmp_5_29_reg_2287, tmp_5_30_reg_2291)
begin
ap_predicate_op969_call_state44 <= ((tmp_reg_1932 = ap_const_lv1_0) and (tmp_66_reg_1936 = ap_const_lv1_1) and (tmp_5_1_reg_1991 = ap_const_lv1_1) and (ap_const_lv1_1 = tmp_5_2_reg_2001) and (ap_const_lv1_1 = tmp_5_3_reg_2011) and (ap_const_lv1_1 = tmp_5_4_reg_2021) and (ap_const_lv1_1 = tmp_5_5_reg_2031) and (ap_const_lv1_1 = tmp_5_6_reg_2041) and (ap_const_lv1_1 = tmp_5_7_reg_2051) and (ap_const_lv1_1 = tmp_5_8_reg_2061) and (ap_const_lv1_1 = tmp_5_9_reg_2071) and (ap_const_lv1_1 = tmp_5_s_reg_2081) and (ap_const_lv1_1 = tmp_5_10_reg_2211) and (ap_const_lv1_1 = tmp_5_11_reg_2215) and (ap_const_lv1_1 = tmp_5_12_reg_2219) and (ap_const_lv1_1 = tmp_5_13_reg_2223) and (ap_const_lv1_1 = tmp_5_14_reg_2227) and (ap_const_lv1_1 = tmp_5_15_reg_2231) and (ap_const_lv1_1 = tmp_5_16_reg_2235) and (ap_const_lv1_1 = tmp_5_17_reg_2239) and (ap_const_lv1_1 = tmp_5_18_reg_2243) and (ap_const_lv1_1 = tmp_5_19_reg_2247) and (ap_const_lv1_1 = tmp_5_20_reg_2251) and (ap_const_lv1_1 = tmp_5_21_reg_2255) and (ap_const_lv1_1 = tmp_5_22_reg_2259) and (ap_const_lv1_1 = tmp_5_23_reg_2263) and (ap_const_lv1_1 = tmp_5_24_reg_2267) and (ap_const_lv1_1 = tmp_5_25_reg_2271) and (ap_const_lv1_1 = tmp_5_26_reg_2275) and (ap_const_lv1_1 = tmp_5_27_reg_2279) and (ap_const_lv1_1 = tmp_5_28_reg_2283) and (ap_const_lv1_1 = tmp_5_29_reg_2287) and (ap_const_lv1_1 = tmp_5_30_reg_2291));
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state80)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state80)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
ap_sig_ioackin_buffer_V_ARREADY_assign_proc : process(buffer_V_ARREADY, ap_reg_ioackin_buffer_V_ARREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_buffer_V_ARREADY)) then
ap_sig_ioackin_buffer_V_ARREADY <= buffer_V_ARREADY;
else
ap_sig_ioackin_buffer_V_ARREADY <= ap_const_logic_1;
end if;
end process;
ap_sig_ioackin_buffer_V_AWREADY_assign_proc : process(buffer_V_AWREADY, ap_reg_ioackin_buffer_V_AWREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_buffer_V_AWREADY)) then
ap_sig_ioackin_buffer_V_AWREADY <= buffer_V_AWREADY;
else
ap_sig_ioackin_buffer_V_AWREADY <= ap_const_logic_1;
end if;
end process;
ap_sig_ioackin_buffer_V_WREADY_assign_proc : process(buffer_V_WREADY, ap_reg_ioackin_buffer_V_WREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY)) then
ap_sig_ioackin_buffer_V_WREADY <= buffer_V_WREADY;
else
ap_sig_ioackin_buffer_V_WREADY <= ap_const_logic_1;
end if;
end process;
buffer_V_ARADDR <= tmp_1_fu_830_p1(32 - 1 downto 0);
buffer_V_ARVALID_assign_proc : process(ap_CS_fsm_pp0_stage1, ap_enable_reg_pp0_iter0, tmp_reg_1932, ap_reg_ioackin_buffer_V_ARREADY, ap_block_pp0_stage1_flag00001001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_block_pp0_stage1_flag00001001 = ap_const_boolean_0) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_ARREADY))) then
buffer_V_ARVALID <= ap_const_logic_1;
else
buffer_V_ARVALID <= ap_const_logic_0;
end if;
end process;
buffer_V_AWVALID_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, ap_CS_fsm_pp0_stage40, ap_reg_ioackin_buffer_V_AWREADY, ap_block_pp0_stage40_flag00001001)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00001001 = ap_const_boolean_0) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_AWREADY))) then
buffer_V_AWVALID <= ap_const_logic_1;
else
buffer_V_AWVALID <= ap_const_logic_0;
end if;
end process;
buffer_V_BREADY_assign_proc : process(tmp_reg_1932, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001)
begin
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
buffer_V_BREADY <= ap_const_logic_1;
else
buffer_V_BREADY <= ap_const_logic_0;
end if;
end process;
buffer_V_RREADY_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage16, ap_CS_fsm_pp0_stage17, ap_CS_fsm_pp0_stage18, ap_CS_fsm_pp0_stage19, ap_CS_fsm_pp0_stage20, ap_CS_fsm_pp0_stage21, ap_CS_fsm_pp0_stage22, ap_CS_fsm_pp0_stage23, ap_CS_fsm_pp0_stage24, ap_CS_fsm_pp0_stage25, ap_CS_fsm_pp0_stage26, ap_CS_fsm_pp0_stage27, ap_CS_fsm_pp0_stage28, ap_CS_fsm_pp0_stage29, ap_CS_fsm_pp0_stage30, ap_CS_fsm_pp0_stage31, ap_CS_fsm_pp0_stage32, ap_CS_fsm_pp0_stage33, ap_CS_fsm_pp0_stage34, ap_CS_fsm_pp0_stage35, ap_CS_fsm_pp0_stage36, ap_CS_fsm_pp0_stage37, ap_CS_fsm_pp0_stage38, ap_CS_fsm_pp0_stage39, ap_block_pp0_stage8_flag00011001, ap_block_pp0_stage11_flag00011001, ap_block_pp0_stage14_flag00011001, ap_block_pp0_stage17_flag00011001, ap_block_pp0_stage20_flag00011001, ap_block_pp0_stage23_flag00011001, ap_block_pp0_stage26_flag00011001, ap_block_pp0_stage29_flag00011001, ap_block_pp0_stage32_flag00011001, ap_block_pp0_stage35_flag00011001, ap_block_pp0_stage38_flag00011001, ap_block_pp0_stage9_flag00011001, ap_block_pp0_stage12_flag00011001, ap_block_pp0_stage15_flag00011001, ap_block_pp0_stage18_flag00011001, ap_block_pp0_stage21_flag00011001, ap_block_pp0_stage24_flag00011001, ap_block_pp0_stage27_flag00011001, ap_block_pp0_stage30_flag00011001, ap_block_pp0_stage33_flag00011001, ap_block_pp0_stage36_flag00011001, ap_block_pp0_stage39_flag00011001, ap_block_pp0_stage10_flag00011001, ap_block_pp0_stage13_flag00011001, ap_block_pp0_stage16_flag00011001, ap_block_pp0_stage19_flag00011001, ap_block_pp0_stage22_flag00011001, ap_block_pp0_stage25_flag00011001, ap_block_pp0_stage28_flag00011001, ap_block_pp0_stage31_flag00011001, ap_block_pp0_stage34_flag00011001, ap_block_pp0_stage37_flag00011001)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00011001 = ap_const_boolean_0)))) then
buffer_V_RREADY <= ap_const_logic_1;
else
buffer_V_RREADY <= ap_const_logic_0;
end if;
end process;
buffer_V_WDATA_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, ap_CS_fsm_pp0_stage41, ap_CS_fsm_pp0_stage42, ap_CS_fsm_pp0_stage43, ap_CS_fsm_pp0_stage44, ap_CS_fsm_pp0_stage45, ap_CS_fsm_pp0_stage46, ap_CS_fsm_pp0_stage47, ap_CS_fsm_pp0_stage48, ap_CS_fsm_pp0_stage49, ap_CS_fsm_pp0_stage50, ap_CS_fsm_pp0_stage51, ap_CS_fsm_pp0_stage52, ap_CS_fsm_pp0_stage53, ap_CS_fsm_pp0_stage54, ap_CS_fsm_pp0_stage55, ap_CS_fsm_pp0_stage56, ap_CS_fsm_pp0_stage57, ap_CS_fsm_pp0_stage58, ap_CS_fsm_pp0_stage59, ap_CS_fsm_pp0_stage60, ap_CS_fsm_pp0_stage61, ap_CS_fsm_pp0_stage62, ap_CS_fsm_pp0_stage63, ap_CS_fsm_pp0_stage64, ap_CS_fsm_pp0_stage65, ap_CS_fsm_pp0_stage66, ap_CS_fsm_pp0_stage67, ap_CS_fsm_pp0_stage68, ap_CS_fsm_pp0_stage69, ap_CS_fsm_pp0_stage70, ap_CS_fsm_pp0_stage71, ap_CS_fsm_pp0_stage72, reg_764, reg_770, reg_775, reg_780, buffer_temp_out_V_lo_4_reg_2300, buffer_temp_out_V_lo_5_reg_2305, buffer_temp_out_V_lo_6_reg_2310, buffer_temp_out_V_lo_7_reg_2315, buffer_temp_out_V_lo_8_reg_2320, buffer_temp_out_V_lo_9_reg_2325, buffer_temp_out_V_lo_10_reg_2330, buffer_temp_out_V_lo_11_reg_2335, buffer_temp_out_V_lo_12_reg_2340, buffer_temp_out_V_lo_13_reg_2345, buffer_temp_out_V_lo_14_reg_2350, buffer_temp_out_V_lo_15_reg_2355, buffer_temp_out_V_lo_16_reg_2360, buffer_temp_out_V_lo_17_reg_2365, buffer_temp_out_V_lo_18_reg_2370, buffer_temp_out_V_lo_19_reg_2375, buffer_temp_out_V_lo_20_reg_2380, buffer_temp_out_V_lo_21_reg_2385, buffer_temp_out_V_lo_22_reg_2390, buffer_temp_out_V_lo_23_reg_2395, buffer_temp_out_V_lo_24_reg_2400, buffer_temp_out_V_lo_25_reg_2405, buffer_temp_out_V_lo_26_reg_2410, buffer_temp_out_V_lo_27_reg_2415, ap_reg_ioackin_buffer_V_WREADY, ap_block_pp0_stage41_flag00001001, ap_block_pp0_stage42_flag00001001, ap_block_pp0_stage43_flag00001001, ap_block_pp0_stage44_flag00001001, ap_block_pp0_stage45_flag00001001, ap_block_pp0_stage46_flag00001001, ap_block_pp0_stage47_flag00001001, ap_block_pp0_stage48_flag00001001, ap_block_pp0_stage49_flag00001001, ap_block_pp0_stage50_flag00001001, ap_block_pp0_stage51_flag00001001, ap_block_pp0_stage52_flag00001001, ap_block_pp0_stage53_flag00001001, ap_block_pp0_stage54_flag00001001, ap_block_pp0_stage55_flag00001001, ap_block_pp0_stage56_flag00001001, ap_block_pp0_stage57_flag00001001, ap_block_pp0_stage58_flag00001001, ap_block_pp0_stage59_flag00001001, ap_block_pp0_stage60_flag00001001, ap_block_pp0_stage61_flag00001001, ap_block_pp0_stage62_flag00001001, ap_block_pp0_stage63_flag00001001, ap_block_pp0_stage64_flag00001001, ap_block_pp0_stage65_flag00001001, ap_block_pp0_stage66_flag00001001, ap_block_pp0_stage67_flag00001001, ap_block_pp0_stage68_flag00001001, ap_block_pp0_stage69_flag00001001, ap_block_pp0_stage70_flag00001001, ap_block_pp0_stage71_flag00001001, ap_block_pp0_stage72_flag00001001)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage68) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage68_flag00001001 = ap_const_boolean_0))) then
buffer_V_WDATA <= buffer_temp_out_V_lo_27_reg_2415;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage67) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage67_flag00001001 = ap_const_boolean_0))) then
buffer_V_WDATA <= buffer_temp_out_V_lo_26_reg_2410;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage66) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage66_flag00001001 = ap_const_boolean_0))) then
buffer_V_WDATA <= buffer_temp_out_V_lo_25_reg_2405;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage65) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage65_flag00001001 = ap_const_boolean_0))) then
buffer_V_WDATA <= buffer_temp_out_V_lo_24_reg_2400;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage64) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage64_flag00001001 = ap_const_boolean_0))) then
buffer_V_WDATA <= buffer_temp_out_V_lo_23_reg_2395;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage63_flag00001001 = ap_const_boolean_0))) then
buffer_V_WDATA <= buffer_temp_out_V_lo_22_reg_2390;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage62_flag00001001 = ap_const_boolean_0))) then
buffer_V_WDATA <= buffer_temp_out_V_lo_21_reg_2385;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage61_flag00001001 = ap_const_boolean_0))) then
buffer_V_WDATA <= buffer_temp_out_V_lo_20_reg_2380;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage60_flag00001001 = ap_const_boolean_0))) then
buffer_V_WDATA <= buffer_temp_out_V_lo_19_reg_2375;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage59_flag00001001 = ap_const_boolean_0))) then
buffer_V_WDATA <= buffer_temp_out_V_lo_18_reg_2370;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage58_flag00001001 = ap_const_boolean_0))) then
buffer_V_WDATA <= buffer_temp_out_V_lo_17_reg_2365;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage57_flag00001001 = ap_const_boolean_0))) then
buffer_V_WDATA <= buffer_temp_out_V_lo_16_reg_2360;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage56_flag00001001 = ap_const_boolean_0))) then
buffer_V_WDATA <= buffer_temp_out_V_lo_15_reg_2355;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage55_flag00001001 = ap_const_boolean_0))) then
buffer_V_WDATA <= buffer_temp_out_V_lo_14_reg_2350;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage54_flag00001001 = ap_const_boolean_0))) then
buffer_V_WDATA <= buffer_temp_out_V_lo_13_reg_2345;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage53_flag00001001 = ap_const_boolean_0))) then
buffer_V_WDATA <= buffer_temp_out_V_lo_12_reg_2340;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage52_flag00001001 = ap_const_boolean_0))) then
buffer_V_WDATA <= buffer_temp_out_V_lo_11_reg_2335;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage51_flag00001001 = ap_const_boolean_0))) then
buffer_V_WDATA <= buffer_temp_out_V_lo_10_reg_2330;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage50_flag00001001 = ap_const_boolean_0))) then
buffer_V_WDATA <= buffer_temp_out_V_lo_9_reg_2325;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage49_flag00001001 = ap_const_boolean_0))) then
buffer_V_WDATA <= buffer_temp_out_V_lo_8_reg_2320;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage48_flag00001001 = ap_const_boolean_0))) then
buffer_V_WDATA <= buffer_temp_out_V_lo_7_reg_2315;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage47_flag00001001 = ap_const_boolean_0))) then
buffer_V_WDATA <= buffer_temp_out_V_lo_6_reg_2310;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage46_flag00001001 = ap_const_boolean_0))) then
buffer_V_WDATA <= buffer_temp_out_V_lo_5_reg_2305;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage45_flag00001001 = ap_const_boolean_0))) then
buffer_V_WDATA <= buffer_temp_out_V_lo_4_reg_2300;
elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage44_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage72) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage72_flag00001001 = ap_const_boolean_0)))) then
buffer_V_WDATA <= reg_780;
elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage43_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage71) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage71_flag00001001 = ap_const_boolean_0)))) then
buffer_V_WDATA <= reg_775;
elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage42_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage70) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage70_flag00001001 = ap_const_boolean_0)))) then
buffer_V_WDATA <= reg_770;
elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00001001 = ap_const_boolean_0) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage69) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage69_flag00001001 = ap_const_boolean_0)))) then
buffer_V_WDATA <= reg_764;
else
buffer_V_WDATA <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
buffer_V_WVALID_assign_proc : process(ap_enable_reg_pp0_iter0, tmp_reg_1932, ap_CS_fsm_pp0_stage41, ap_CS_fsm_pp0_stage42, ap_CS_fsm_pp0_stage43, ap_CS_fsm_pp0_stage44, ap_CS_fsm_pp0_stage45, ap_CS_fsm_pp0_stage46, ap_CS_fsm_pp0_stage47, ap_CS_fsm_pp0_stage48, ap_CS_fsm_pp0_stage49, ap_CS_fsm_pp0_stage50, ap_CS_fsm_pp0_stage51, ap_CS_fsm_pp0_stage52, ap_CS_fsm_pp0_stage53, ap_CS_fsm_pp0_stage54, ap_CS_fsm_pp0_stage55, ap_CS_fsm_pp0_stage56, ap_CS_fsm_pp0_stage57, ap_CS_fsm_pp0_stage58, ap_CS_fsm_pp0_stage59, ap_CS_fsm_pp0_stage60, ap_CS_fsm_pp0_stage61, ap_CS_fsm_pp0_stage62, ap_CS_fsm_pp0_stage63, ap_CS_fsm_pp0_stage64, ap_CS_fsm_pp0_stage65, ap_CS_fsm_pp0_stage66, ap_CS_fsm_pp0_stage67, ap_CS_fsm_pp0_stage68, ap_CS_fsm_pp0_stage69, ap_CS_fsm_pp0_stage70, ap_CS_fsm_pp0_stage71, ap_CS_fsm_pp0_stage72, ap_reg_ioackin_buffer_V_WREADY, ap_block_pp0_stage41_flag00001001, ap_block_pp0_stage42_flag00001001, ap_block_pp0_stage43_flag00001001, ap_block_pp0_stage44_flag00001001, ap_block_pp0_stage45_flag00001001, ap_block_pp0_stage46_flag00001001, ap_block_pp0_stage47_flag00001001, ap_block_pp0_stage48_flag00001001, ap_block_pp0_stage49_flag00001001, ap_block_pp0_stage50_flag00001001, ap_block_pp0_stage51_flag00001001, ap_block_pp0_stage52_flag00001001, ap_block_pp0_stage53_flag00001001, ap_block_pp0_stage54_flag00001001, ap_block_pp0_stage55_flag00001001, ap_block_pp0_stage56_flag00001001, ap_block_pp0_stage57_flag00001001, ap_block_pp0_stage58_flag00001001, ap_block_pp0_stage59_flag00001001, ap_block_pp0_stage60_flag00001001, ap_block_pp0_stage61_flag00001001, ap_block_pp0_stage62_flag00001001, ap_block_pp0_stage63_flag00001001, ap_block_pp0_stage64_flag00001001, ap_block_pp0_stage65_flag00001001, ap_block_pp0_stage66_flag00001001, ap_block_pp0_stage67_flag00001001, ap_block_pp0_stage68_flag00001001, ap_block_pp0_stage69_flag00001001, ap_block_pp0_stage70_flag00001001, ap_block_pp0_stage71_flag00001001, ap_block_pp0_stage72_flag00001001)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00001001 = ap_const_boolean_0) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage42_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage43_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage44_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage45_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage46_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage47_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage48_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage49_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage50_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage51_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage52_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage53_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage54_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage55_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage56_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage57_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage58_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage59_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage60_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage61_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage62_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage63_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage64) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage64_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage65) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage65_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage66) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage66_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage67) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage67_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage68) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage68_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage69) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage69_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage70) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage70_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage71) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage71_flag00001001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage72) and (ap_const_logic_0 = ap_reg_ioackin_buffer_V_WREADY) and (ap_block_pp0_stage72_flag00001001 = ap_const_boolean_0)))) then
buffer_V_WVALID <= ap_const_logic_1;
else
buffer_V_WVALID <= ap_const_logic_0;
end if;
end process;
buffer_V_blk_n_AR_assign_proc : process(m_axi_buffer_V_ARREADY, ap_CS_fsm_pp0_stage1, ap_enable_reg_pp0_iter0, ap_block_pp0_stage1_flag00000000, tmp_reg_1932)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0) and (tmp_reg_1932 = ap_const_lv1_0))) then
buffer_V_blk_n_AR <= m_axi_buffer_V_ARREADY;
else
buffer_V_blk_n_AR <= ap_const_logic_1;
end if;
end process;
buffer_V_blk_n_AW_assign_proc : process(m_axi_buffer_V_AWREADY, ap_enable_reg_pp0_iter0, tmp_reg_1932, ap_CS_fsm_pp0_stage40, ap_block_pp0_stage40_flag00000000)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00000000 = ap_const_boolean_0))) then
buffer_V_blk_n_AW <= m_axi_buffer_V_AWREADY;
else
buffer_V_blk_n_AW <= ap_const_logic_1;
end if;
end process;
buffer_V_blk_n_B_assign_proc : process(m_axi_buffer_V_BVALID, tmp_reg_1932, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000)
begin
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
buffer_V_blk_n_B <= m_axi_buffer_V_BVALID;
else
buffer_V_blk_n_B <= ap_const_logic_1;
end if;
end process;
buffer_V_blk_n_R_assign_proc : process(m_axi_buffer_V_RVALID, ap_enable_reg_pp0_iter0, tmp_reg_1932, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00000000, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00000000, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00000000, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00000000, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00000000, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage13_flag00000000, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage14_flag00000000, ap_CS_fsm_pp0_stage15, ap_block_pp0_stage15_flag00000000, ap_CS_fsm_pp0_stage16, ap_block_pp0_stage16_flag00000000, ap_CS_fsm_pp0_stage17, ap_block_pp0_stage17_flag00000000, ap_CS_fsm_pp0_stage18, ap_block_pp0_stage18_flag00000000, ap_CS_fsm_pp0_stage19, ap_block_pp0_stage19_flag00000000, ap_CS_fsm_pp0_stage20, ap_block_pp0_stage20_flag00000000, ap_CS_fsm_pp0_stage21, ap_block_pp0_stage21_flag00000000, ap_CS_fsm_pp0_stage22, ap_block_pp0_stage22_flag00000000, ap_CS_fsm_pp0_stage23, ap_block_pp0_stage23_flag00000000, ap_CS_fsm_pp0_stage24, ap_block_pp0_stage24_flag00000000, ap_CS_fsm_pp0_stage25, ap_block_pp0_stage25_flag00000000, ap_CS_fsm_pp0_stage26, ap_block_pp0_stage26_flag00000000, ap_CS_fsm_pp0_stage27, ap_block_pp0_stage27_flag00000000, ap_CS_fsm_pp0_stage28, ap_block_pp0_stage28_flag00000000, ap_CS_fsm_pp0_stage29, ap_block_pp0_stage29_flag00000000, ap_CS_fsm_pp0_stage30, ap_block_pp0_stage30_flag00000000, ap_CS_fsm_pp0_stage31, ap_block_pp0_stage31_flag00000000, ap_CS_fsm_pp0_stage32, ap_block_pp0_stage32_flag00000000, ap_CS_fsm_pp0_stage33, ap_block_pp0_stage33_flag00000000, ap_CS_fsm_pp0_stage34, ap_block_pp0_stage34_flag00000000, ap_CS_fsm_pp0_stage35, ap_block_pp0_stage35_flag00000000, ap_CS_fsm_pp0_stage36, ap_block_pp0_stage36_flag00000000, ap_CS_fsm_pp0_stage37, ap_block_pp0_stage37_flag00000000, ap_CS_fsm_pp0_stage38, ap_block_pp0_stage38_flag00000000, ap_CS_fsm_pp0_stage39, ap_block_pp0_stage39_flag00000000)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00000000 = ap_const_boolean_0)))) then
buffer_V_blk_n_R <= m_axi_buffer_V_RVALID;
else
buffer_V_blk_n_R <= ap_const_logic_1;
end if;
end process;
buffer_V_blk_n_W_assign_proc : process(m_axi_buffer_V_WREADY, ap_enable_reg_pp0_iter0, tmp_reg_1932, ap_CS_fsm_pp0_stage41, ap_block_pp0_stage41_flag00000000, ap_CS_fsm_pp0_stage42, ap_block_pp0_stage42_flag00000000, ap_CS_fsm_pp0_stage43, ap_block_pp0_stage43_flag00000000, ap_CS_fsm_pp0_stage44, ap_block_pp0_stage44_flag00000000, ap_CS_fsm_pp0_stage45, ap_block_pp0_stage45_flag00000000, ap_CS_fsm_pp0_stage46, ap_block_pp0_stage46_flag00000000, ap_CS_fsm_pp0_stage47, ap_block_pp0_stage47_flag00000000, ap_CS_fsm_pp0_stage48, ap_block_pp0_stage48_flag00000000, ap_CS_fsm_pp0_stage49, ap_block_pp0_stage49_flag00000000, ap_CS_fsm_pp0_stage50, ap_block_pp0_stage50_flag00000000, ap_CS_fsm_pp0_stage51, ap_block_pp0_stage51_flag00000000, ap_CS_fsm_pp0_stage52, ap_block_pp0_stage52_flag00000000, ap_CS_fsm_pp0_stage53, ap_block_pp0_stage53_flag00000000, ap_CS_fsm_pp0_stage54, ap_block_pp0_stage54_flag00000000, ap_CS_fsm_pp0_stage55, ap_block_pp0_stage55_flag00000000, ap_CS_fsm_pp0_stage56, ap_block_pp0_stage56_flag00000000, ap_CS_fsm_pp0_stage57, ap_block_pp0_stage57_flag00000000, ap_CS_fsm_pp0_stage58, ap_block_pp0_stage58_flag00000000, ap_CS_fsm_pp0_stage59, ap_block_pp0_stage59_flag00000000, ap_CS_fsm_pp0_stage60, ap_block_pp0_stage60_flag00000000, ap_CS_fsm_pp0_stage61, ap_block_pp0_stage61_flag00000000, ap_CS_fsm_pp0_stage62, ap_block_pp0_stage62_flag00000000, ap_CS_fsm_pp0_stage63, ap_block_pp0_stage63_flag00000000, ap_CS_fsm_pp0_stage64, ap_block_pp0_stage64_flag00000000, ap_CS_fsm_pp0_stage65, ap_block_pp0_stage65_flag00000000, ap_CS_fsm_pp0_stage66, ap_block_pp0_stage66_flag00000000, ap_CS_fsm_pp0_stage67, ap_block_pp0_stage67_flag00000000, ap_CS_fsm_pp0_stage68, ap_block_pp0_stage68_flag00000000, ap_CS_fsm_pp0_stage69, ap_block_pp0_stage69_flag00000000, ap_CS_fsm_pp0_stage70, ap_block_pp0_stage70_flag00000000, ap_CS_fsm_pp0_stage71, ap_block_pp0_stage71_flag00000000, ap_CS_fsm_pp0_stage72, ap_block_pp0_stage72_flag00000000)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage64) and (ap_block_pp0_stage64_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage65) and (ap_block_pp0_stage65_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage66) and (ap_block_pp0_stage66_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage67) and (ap_block_pp0_stage67_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage68) and (ap_block_pp0_stage68_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage69) and (ap_block_pp0_stage69_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage70) and (ap_block_pp0_stage70_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage71) and (ap_block_pp0_stage71_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage72) and (ap_block_pp0_stage72_flag00000000 = ap_const_boolean_0)))) then
buffer_V_blk_n_W <= m_axi_buffer_V_WREADY;
else
buffer_V_blk_n_W <= ap_const_logic_1;
end if;
end process;
buffer_temp_out_V_address0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00000000, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00000000, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage13_flag00000000, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage14_flag00000000, ap_CS_fsm_pp0_stage15, ap_block_pp0_stage15_flag00000000, ap_CS_fsm_pp0_stage16, ap_block_pp0_stage16_flag00000000, ap_CS_fsm_pp0_stage17, ap_block_pp0_stage17_flag00000000, ap_CS_fsm_pp0_stage18, ap_block_pp0_stage18_flag00000000, ap_CS_fsm_pp0_stage19, ap_block_pp0_stage19_flag00000000, ap_CS_fsm_pp0_stage20, ap_block_pp0_stage20_flag00000000, ap_CS_fsm_pp0_stage21, ap_block_pp0_stage21_flag00000000, ap_CS_fsm_pp0_stage22, ap_block_pp0_stage22_flag00000000, ap_CS_fsm_pp0_stage23, ap_block_pp0_stage23_flag00000000, ap_CS_fsm_pp0_stage24, ap_block_pp0_stage24_flag00000000, ap_CS_fsm_pp0_stage25, ap_block_pp0_stage25_flag00000000, ap_CS_fsm_pp0_stage26, ap_block_pp0_stage26_flag00000000, ap_CS_fsm_pp0_stage27, ap_block_pp0_stage27_flag00000000, ap_CS_fsm_pp0_stage28, ap_block_pp0_stage28_flag00000000, ap_CS_fsm_pp0_stage29, ap_block_pp0_stage29_flag00000000, ap_CS_fsm_pp0_stage30, ap_block_pp0_stage30_flag00000000, ap_CS_fsm_pp0_stage31, ap_block_pp0_stage31_flag00000000, ap_CS_fsm_pp0_stage32, ap_block_pp0_stage32_flag00000000, ap_CS_fsm_pp0_stage33, ap_block_pp0_stage33_flag00000000, ap_CS_fsm_pp0_stage34, ap_block_pp0_stage34_flag00000000, ap_CS_fsm_pp0_stage35, ap_block_pp0_stage35_flag00000000, ap_CS_fsm_pp0_stage36, ap_block_pp0_stage36_flag00000000, ap_CS_fsm_pp0_stage37, ap_block_pp0_stage37_flag00000000, ap_CS_fsm_pp0_stage38, ap_block_pp0_stage38_flag00000000, ap_CS_fsm_pp0_stage39, ap_block_pp0_stage39_flag00000000, ap_CS_fsm_pp0_stage40, ap_block_pp0_stage40_flag00000000, ap_CS_fsm_pp0_stage41, ap_block_pp0_stage41_flag00000000, ap_CS_fsm_pp0_stage42, ap_block_pp0_stage42_flag00000000, tmp_1_reg_1974, tmp_5_fu_1376_p1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_1E(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_1D(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_1C(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_1B(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_1A(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_19(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_18(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_17(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_16(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_15(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_14(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_13(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_12(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_11(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_10(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_F(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_E(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_D(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_C(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_B(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_A(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_9(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_8(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_7(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_6(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_5(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_4(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_3(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_2(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= ap_const_lv64_1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= tmp_5_fu_1376_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address0 <= tmp_1_reg_1974(5 - 1 downto 0);
else
buffer_temp_out_V_address0 <= "XXXXX";
end if;
else
buffer_temp_out_V_address0 <= "XXXXX";
end if;
end process;
buffer_temp_out_V_address1_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00000000, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage13_flag00000000, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage14_flag00000000, ap_CS_fsm_pp0_stage15, ap_block_pp0_stage15_flag00000000, ap_CS_fsm_pp0_stage16, ap_block_pp0_stage16_flag00000000, ap_CS_fsm_pp0_stage17, ap_block_pp0_stage17_flag00000000, ap_CS_fsm_pp0_stage18, ap_block_pp0_stage18_flag00000000, ap_CS_fsm_pp0_stage19, ap_block_pp0_stage19_flag00000000, ap_CS_fsm_pp0_stage20, ap_block_pp0_stage20_flag00000000, ap_CS_fsm_pp0_stage21, ap_block_pp0_stage21_flag00000000, ap_CS_fsm_pp0_stage22, ap_block_pp0_stage22_flag00000000, ap_CS_fsm_pp0_stage23, ap_block_pp0_stage23_flag00000000, ap_CS_fsm_pp0_stage24, ap_block_pp0_stage24_flag00000000, ap_CS_fsm_pp0_stage25, ap_block_pp0_stage25_flag00000000, ap_CS_fsm_pp0_stage26, ap_block_pp0_stage26_flag00000000, ap_CS_fsm_pp0_stage27, ap_block_pp0_stage27_flag00000000, ap_CS_fsm_pp0_stage28, ap_block_pp0_stage28_flag00000000, ap_CS_fsm_pp0_stage29, ap_block_pp0_stage29_flag00000000, ap_CS_fsm_pp0_stage30, ap_block_pp0_stage30_flag00000000, ap_CS_fsm_pp0_stage31, ap_block_pp0_stage31_flag00000000, ap_CS_fsm_pp0_stage32, ap_block_pp0_stage32_flag00000000, ap_CS_fsm_pp0_stage33, ap_block_pp0_stage33_flag00000000, ap_CS_fsm_pp0_stage34, ap_block_pp0_stage34_flag00000000, ap_CS_fsm_pp0_stage35, ap_block_pp0_stage35_flag00000000, ap_CS_fsm_pp0_stage36, ap_block_pp0_stage36_flag00000000, ap_CS_fsm_pp0_stage37, ap_block_pp0_stage37_flag00000000, ap_CS_fsm_pp0_stage38, ap_block_pp0_stage38_flag00000000, ap_CS_fsm_pp0_stage39, ap_block_pp0_stage39_flag00000000, ap_CS_fsm_pp0_stage40, ap_block_pp0_stage40_flag00000000, ap_CS_fsm_pp0_stage41, ap_block_pp0_stage41_flag00000000, ap_CS_fsm_pp0_stage42, ap_block_pp0_stage42_flag00000000, ap_CS_fsm_pp0_stage43, ap_block_pp0_stage43_flag00000000, tmp_7_fu_1395_p1, tmp_9_fu_1408_p1, tmp_10_fu_1421_p1, tmp_12_fu_1434_p1, tmp_14_fu_1447_p1, tmp_16_fu_1460_p1, tmp_18_fu_1473_p1, tmp_20_fu_1486_p1, tmp_22_fu_1499_p1, tmp_24_fu_1512_p1, tmp_26_fu_1525_p1, tmp_28_fu_1538_p1, tmp_30_fu_1551_p1, tmp_32_fu_1564_p1, tmp_34_fu_1577_p1, tmp_36_fu_1590_p1, tmp_38_fu_1603_p1, tmp_40_fu_1616_p1, tmp_42_fu_1629_p1, tmp_44_fu_1642_p1, tmp_46_fu_1655_p1, tmp_48_fu_1659_p1, tmp_50_fu_1663_p1, tmp_52_fu_1667_p1, tmp_54_fu_1671_p1, tmp_56_fu_1675_p1, tmp_58_fu_1679_p1, tmp_60_fu_1683_p1, tmp_62_fu_1687_p1, tmp_64_fu_1691_p1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= ap_const_lv64_1F(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_64_fu_1691_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_62_fu_1687_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_60_fu_1683_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_58_fu_1679_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_56_fu_1675_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_54_fu_1671_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_52_fu_1667_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_50_fu_1663_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_48_fu_1659_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_46_fu_1655_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_44_fu_1642_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_42_fu_1629_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_40_fu_1616_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_38_fu_1603_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_36_fu_1590_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_34_fu_1577_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_32_fu_1564_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_30_fu_1551_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_28_fu_1538_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_26_fu_1525_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_24_fu_1512_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_22_fu_1499_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_20_fu_1486_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_18_fu_1473_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_16_fu_1460_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_14_fu_1447_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_12_fu_1434_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_10_fu_1421_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_9_fu_1408_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= tmp_7_fu_1395_p1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_address1 <= ap_const_lv64_0(5 - 1 downto 0);
else
buffer_temp_out_V_address1 <= "XXXXX";
end if;
else
buffer_temp_out_V_address1 <= "XXXXX";
end if;
end process;
buffer_temp_out_V_ce0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage16, ap_CS_fsm_pp0_stage17, ap_CS_fsm_pp0_stage18, ap_CS_fsm_pp0_stage19, ap_CS_fsm_pp0_stage20, ap_CS_fsm_pp0_stage21, ap_CS_fsm_pp0_stage22, ap_CS_fsm_pp0_stage23, ap_CS_fsm_pp0_stage24, ap_CS_fsm_pp0_stage25, ap_CS_fsm_pp0_stage26, ap_CS_fsm_pp0_stage27, ap_CS_fsm_pp0_stage28, ap_CS_fsm_pp0_stage29, ap_CS_fsm_pp0_stage30, ap_CS_fsm_pp0_stage31, ap_CS_fsm_pp0_stage32, ap_CS_fsm_pp0_stage33, ap_CS_fsm_pp0_stage34, ap_CS_fsm_pp0_stage35, ap_CS_fsm_pp0_stage36, ap_CS_fsm_pp0_stage37, ap_CS_fsm_pp0_stage38, ap_CS_fsm_pp0_stage39, ap_CS_fsm_pp0_stage40, ap_CS_fsm_pp0_stage41, ap_CS_fsm_pp0_stage42, ap_block_pp0_stage11_flag00011001, ap_block_pp0_stage14_flag00011001, ap_block_pp0_stage17_flag00011001, ap_block_pp0_stage20_flag00011001, ap_block_pp0_stage23_flag00011001, ap_block_pp0_stage26_flag00011001, ap_block_pp0_stage29_flag00011001, ap_block_pp0_stage32_flag00011001, ap_block_pp0_stage35_flag00011001, ap_block_pp0_stage38_flag00011001, ap_block_pp0_stage12_flag00011001, ap_block_pp0_stage15_flag00011001, ap_block_pp0_stage18_flag00011001, ap_block_pp0_stage21_flag00011001, ap_block_pp0_stage24_flag00011001, ap_block_pp0_stage27_flag00011001, ap_block_pp0_stage30_flag00011001, ap_block_pp0_stage33_flag00011001, ap_block_pp0_stage36_flag00011001, ap_block_pp0_stage39_flag00011001, ap_block_pp0_stage13_flag00011001, ap_block_pp0_stage16_flag00011001, ap_block_pp0_stage19_flag00011001, ap_block_pp0_stage22_flag00011001, ap_block_pp0_stage25_flag00011001, ap_block_pp0_stage28_flag00011001, ap_block_pp0_stage31_flag00011001, ap_block_pp0_stage34_flag00011001, ap_block_pp0_stage37_flag00011001, ap_block_pp0_stage41_flag00011001, ap_block_pp0_stage42_flag00011001, ap_block_pp0_stage40_flag00011001)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00011001 = ap_const_boolean_0)))) then
buffer_temp_out_V_ce0 <= ap_const_logic_1;
else
buffer_temp_out_V_ce0 <= ap_const_logic_0;
end if;
end process;
buffer_temp_out_V_ce1_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage16, ap_CS_fsm_pp0_stage17, ap_CS_fsm_pp0_stage18, ap_CS_fsm_pp0_stage19, ap_CS_fsm_pp0_stage20, ap_CS_fsm_pp0_stage21, ap_CS_fsm_pp0_stage22, ap_CS_fsm_pp0_stage23, ap_CS_fsm_pp0_stage24, ap_CS_fsm_pp0_stage25, ap_CS_fsm_pp0_stage26, ap_CS_fsm_pp0_stage27, ap_CS_fsm_pp0_stage28, ap_CS_fsm_pp0_stage29, ap_CS_fsm_pp0_stage30, ap_CS_fsm_pp0_stage31, ap_CS_fsm_pp0_stage32, ap_CS_fsm_pp0_stage33, ap_CS_fsm_pp0_stage34, ap_CS_fsm_pp0_stage35, ap_CS_fsm_pp0_stage36, ap_CS_fsm_pp0_stage37, ap_CS_fsm_pp0_stage38, ap_CS_fsm_pp0_stage39, ap_CS_fsm_pp0_stage40, ap_CS_fsm_pp0_stage41, ap_CS_fsm_pp0_stage42, ap_CS_fsm_pp0_stage43, ap_block_pp0_stage14_flag00011001, ap_block_pp0_stage17_flag00011001, ap_block_pp0_stage20_flag00011001, ap_block_pp0_stage23_flag00011001, ap_block_pp0_stage26_flag00011001, ap_block_pp0_stage29_flag00011001, ap_block_pp0_stage32_flag00011001, ap_block_pp0_stage35_flag00011001, ap_block_pp0_stage38_flag00011001, ap_block_pp0_stage12_flag00011001, ap_block_pp0_stage15_flag00011001, ap_block_pp0_stage18_flag00011001, ap_block_pp0_stage21_flag00011001, ap_block_pp0_stage24_flag00011001, ap_block_pp0_stage27_flag00011001, ap_block_pp0_stage30_flag00011001, ap_block_pp0_stage33_flag00011001, ap_block_pp0_stage36_flag00011001, ap_block_pp0_stage39_flag00011001, ap_block_pp0_stage13_flag00011001, ap_block_pp0_stage16_flag00011001, ap_block_pp0_stage19_flag00011001, ap_block_pp0_stage22_flag00011001, ap_block_pp0_stage25_flag00011001, ap_block_pp0_stage28_flag00011001, ap_block_pp0_stage31_flag00011001, ap_block_pp0_stage34_flag00011001, ap_block_pp0_stage37_flag00011001, ap_block_pp0_stage41_flag00011001, ap_block_pp0_stage42_flag00011001, ap_block_pp0_stage43_flag00011001, ap_block_pp0_stage40_flag00011001)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00011001 = ap_const_boolean_0)))) then
buffer_temp_out_V_ce1 <= ap_const_logic_1;
else
buffer_temp_out_V_ce1 <= ap_const_logic_0;
end if;
end process;
buffer_temp_out_V_d0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00000000, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00000000, grp_fu_786_p2, grp_fu_794_p2)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_d0 <= grp_fu_794_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
buffer_temp_out_V_d0 <= grp_fu_786_p2;
else
buffer_temp_out_V_d0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
buffer_temp_out_V_d0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
buffer_temp_out_V_d1_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage13_flag00000000, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage14_flag00000000, ap_CS_fsm_pp0_stage15, ap_block_pp0_stage15_flag00000000, ap_CS_fsm_pp0_stage16, ap_block_pp0_stage16_flag00000000, ap_CS_fsm_pp0_stage17, ap_block_pp0_stage17_flag00000000, ap_CS_fsm_pp0_stage18, ap_block_pp0_stage18_flag00000000, ap_CS_fsm_pp0_stage19, ap_block_pp0_stage19_flag00000000, ap_CS_fsm_pp0_stage20, ap_block_pp0_stage20_flag00000000, ap_CS_fsm_pp0_stage21, ap_block_pp0_stage21_flag00000000, ap_CS_fsm_pp0_stage22, ap_block_pp0_stage22_flag00000000, ap_CS_fsm_pp0_stage23, ap_block_pp0_stage23_flag00000000, ap_CS_fsm_pp0_stage24, ap_block_pp0_stage24_flag00000000, ap_CS_fsm_pp0_stage25, ap_block_pp0_stage25_flag00000000, ap_CS_fsm_pp0_stage26, ap_block_pp0_stage26_flag00000000, ap_CS_fsm_pp0_stage27, ap_block_pp0_stage27_flag00000000, ap_CS_fsm_pp0_stage28, ap_block_pp0_stage28_flag00000000, ap_CS_fsm_pp0_stage29, ap_block_pp0_stage29_flag00000000, ap_CS_fsm_pp0_stage30, ap_block_pp0_stage30_flag00000000, ap_CS_fsm_pp0_stage31, ap_block_pp0_stage31_flag00000000, ap_CS_fsm_pp0_stage32, ap_block_pp0_stage32_flag00000000, ap_CS_fsm_pp0_stage33, ap_block_pp0_stage33_flag00000000, ap_CS_fsm_pp0_stage34, ap_block_pp0_stage34_flag00000000, ap_CS_fsm_pp0_stage35, ap_block_pp0_stage35_flag00000000, ap_CS_fsm_pp0_stage36, ap_block_pp0_stage36_flag00000000, ap_CS_fsm_pp0_stage37, ap_block_pp0_stage37_flag00000000, ap_CS_fsm_pp0_stage38, ap_block_pp0_stage38_flag00000000, ap_CS_fsm_pp0_stage39, ap_block_pp0_stage39_flag00000000, ap_CS_fsm_pp0_stage40, ap_block_pp0_stage40_flag00000000, ap_CS_fsm_pp0_stage41, ap_block_pp0_stage41_flag00000000, ap_CS_fsm_pp0_stage42, ap_block_pp0_stage42_flag00000000, grp_fu_786_p2, grp_fu_794_p2, grp_fu_802_p2)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00000000 = ap_const_boolean_0)))) then
buffer_temp_out_V_d1 <= grp_fu_794_p2;
elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00000000 = ap_const_boolean_0)))) then
buffer_temp_out_V_d1 <= grp_fu_786_p2;
elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00000000 = ap_const_boolean_0)))) then
buffer_temp_out_V_d1 <= grp_fu_802_p2;
else
buffer_temp_out_V_d1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
buffer_temp_out_V_we0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage11_flag00011001, ap_block_pp0_stage12_flag00011001, ap_predicate_op307_call_state13, ap_predicate_op370_call_state14)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op307_call_state13)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op370_call_state14)))) then
buffer_temp_out_V_we0 <= ap_const_logic_1;
else
buffer_temp_out_V_we0 <= ap_const_logic_0;
end if;
end process;
buffer_temp_out_V_we1_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage16, ap_CS_fsm_pp0_stage17, ap_CS_fsm_pp0_stage18, ap_CS_fsm_pp0_stage19, ap_CS_fsm_pp0_stage20, ap_CS_fsm_pp0_stage21, ap_CS_fsm_pp0_stage22, ap_CS_fsm_pp0_stage23, ap_CS_fsm_pp0_stage24, ap_CS_fsm_pp0_stage25, ap_CS_fsm_pp0_stage26, ap_CS_fsm_pp0_stage27, ap_CS_fsm_pp0_stage28, ap_CS_fsm_pp0_stage29, ap_CS_fsm_pp0_stage30, ap_CS_fsm_pp0_stage31, ap_CS_fsm_pp0_stage32, ap_CS_fsm_pp0_stage33, ap_CS_fsm_pp0_stage34, ap_CS_fsm_pp0_stage35, ap_CS_fsm_pp0_stage36, ap_CS_fsm_pp0_stage37, ap_CS_fsm_pp0_stage38, ap_CS_fsm_pp0_stage39, ap_CS_fsm_pp0_stage40, ap_CS_fsm_pp0_stage41, ap_CS_fsm_pp0_stage42, ap_block_pp0_stage14_flag00011001, ap_block_pp0_stage17_flag00011001, ap_block_pp0_stage20_flag00011001, ap_block_pp0_stage23_flag00011001, ap_block_pp0_stage26_flag00011001, ap_block_pp0_stage29_flag00011001, ap_block_pp0_stage32_flag00011001, ap_block_pp0_stage35_flag00011001, ap_block_pp0_stage38_flag00011001, ap_block_pp0_stage15_flag00011001, ap_block_pp0_stage18_flag00011001, ap_block_pp0_stage21_flag00011001, ap_block_pp0_stage24_flag00011001, ap_block_pp0_stage27_flag00011001, ap_block_pp0_stage30_flag00011001, ap_block_pp0_stage33_flag00011001, ap_block_pp0_stage36_flag00011001, ap_block_pp0_stage39_flag00011001, ap_block_pp0_stage13_flag00011001, ap_block_pp0_stage16_flag00011001, ap_block_pp0_stage19_flag00011001, ap_block_pp0_stage22_flag00011001, ap_block_pp0_stage25_flag00011001, ap_block_pp0_stage28_flag00011001, ap_block_pp0_stage31_flag00011001, ap_block_pp0_stage34_flag00011001, ap_block_pp0_stage37_flag00011001, ap_block_pp0_stage41_flag00011001, ap_block_pp0_stage42_flag00011001, ap_block_pp0_stage40_flag00011001, ap_predicate_op392_call_state15, ap_predicate_op414_call_state16, ap_predicate_op436_call_state17, ap_predicate_op458_call_state18, ap_predicate_op480_call_state19, ap_predicate_op502_call_state20, ap_predicate_op524_call_state21, ap_predicate_op546_call_state22, ap_predicate_op568_call_state23, ap_predicate_op590_call_state24, ap_predicate_op612_call_state25, ap_predicate_op634_call_state26, ap_predicate_op656_call_state27, ap_predicate_op678_call_state28, ap_predicate_op700_call_state29, ap_predicate_op722_call_state30, ap_predicate_op744_call_state31, ap_predicate_op766_call_state32, ap_predicate_op788_call_state33, ap_predicate_op810_call_state34, ap_predicate_op832_call_state35, ap_predicate_op851_call_state36, ap_predicate_op869_call_state37, ap_predicate_op886_call_state38, ap_predicate_op902_call_state39, ap_predicate_op917_call_state40, ap_predicate_op931_call_state41, ap_predicate_op943_call_state42, ap_predicate_op955_call_state43, ap_predicate_op969_call_state44)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op392_call_state15)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op414_call_state16)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op436_call_state17)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op458_call_state18)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op480_call_state19)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op502_call_state20)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op524_call_state21)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op546_call_state22)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op568_call_state23)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op590_call_state24)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op612_call_state25)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op634_call_state26)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op656_call_state27)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op678_call_state28)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op700_call_state29)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op722_call_state30)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op744_call_state31)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op766_call_state32)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op788_call_state33)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op810_call_state34)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op832_call_state35)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op851_call_state36)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op869_call_state37)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op886_call_state38)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op902_call_state39)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op917_call_state40)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op931_call_state41)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op943_call_state42)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op955_call_state43)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op969_call_state44)))) then
buffer_temp_out_V_we1 <= ap_const_logic_1;
else
buffer_temp_out_V_we1 <= ap_const_logic_0;
end if;
end process;
counter_V_0_10_fu_1383_p2 <= std_logic_vector(unsigned(tmp_8_10_cast_fu_1380_p1) + unsigned(iv_V));
counter_V_0_11_fu_1402_p2 <= std_logic_vector(unsigned(tmp_8_11_cast_fu_1399_p1) + unsigned(iv_V));
counter_V_0_12_fu_1415_p2 <= std_logic_vector(unsigned(tmp_8_12_cast_fu_1412_p1) + unsigned(iv_V));
counter_V_0_13_fu_1428_p2 <= std_logic_vector(unsigned(tmp_8_13_cast_fu_1425_p1) + unsigned(iv_V));
counter_V_0_14_fu_1441_p2 <= std_logic_vector(unsigned(tmp_8_14_cast_fu_1438_p1) + unsigned(iv_V));
counter_V_0_15_fu_1454_p2 <= std_logic_vector(unsigned(tmp_8_15_cast_fu_1451_p1) + unsigned(iv_V));
counter_V_0_16_fu_1467_p2 <= std_logic_vector(unsigned(tmp_8_16_cast_fu_1464_p1) + unsigned(iv_V));
counter_V_0_17_fu_1480_p2 <= std_logic_vector(unsigned(tmp_8_17_cast_fu_1477_p1) + unsigned(iv_V));
counter_V_0_18_fu_1493_p2 <= std_logic_vector(unsigned(tmp_8_18_cast_fu_1490_p1) + unsigned(iv_V));
counter_V_0_19_fu_1506_p2 <= std_logic_vector(unsigned(tmp_8_19_cast_fu_1503_p1) + unsigned(iv_V));
counter_V_0_1_fu_878_p2 <= std_logic_vector(unsigned(tmp_8_cast_6_fu_875_p1) + unsigned(iv_V));
counter_V_0_20_fu_1519_p2 <= std_logic_vector(unsigned(tmp_8_20_cast_fu_1516_p1) + unsigned(iv_V));
counter_V_0_21_fu_1532_p2 <= std_logic_vector(unsigned(tmp_8_21_cast_fu_1529_p1) + unsigned(iv_V));
counter_V_0_22_fu_1545_p2 <= std_logic_vector(unsigned(tmp_8_22_cast_fu_1542_p1) + unsigned(iv_V));
counter_V_0_23_fu_1558_p2 <= std_logic_vector(unsigned(tmp_8_23_cast_fu_1555_p1) + unsigned(iv_V));
counter_V_0_24_fu_1571_p2 <= std_logic_vector(unsigned(tmp_8_24_cast_fu_1568_p1) + unsigned(iv_V));
counter_V_0_25_fu_1584_p2 <= std_logic_vector(unsigned(tmp_8_25_cast_fu_1581_p1) + unsigned(iv_V));
counter_V_0_26_fu_1597_p2 <= std_logic_vector(unsigned(tmp_8_26_cast_fu_1594_p1) + unsigned(iv_V));
counter_V_0_27_fu_1610_p2 <= std_logic_vector(unsigned(tmp_8_27_cast_fu_1607_p1) + unsigned(iv_V));
counter_V_0_28_fu_1623_p2 <= std_logic_vector(unsigned(tmp_8_28_cast_fu_1620_p1) + unsigned(iv_V));
counter_V_0_29_fu_1636_p2 <= std_logic_vector(unsigned(tmp_8_29_cast_fu_1633_p1) + unsigned(iv_V));
counter_V_0_2_fu_901_p2 <= std_logic_vector(unsigned(tmp_8_1_cast_fu_898_p1) + unsigned(iv_V));
counter_V_0_30_fu_1649_p2 <= std_logic_vector(unsigned(tmp_8_30_cast_fu_1646_p1) + unsigned(iv_V));
counter_V_0_3_fu_924_p2 <= std_logic_vector(unsigned(tmp_8_2_cast_fu_921_p1) + unsigned(iv_V));
counter_V_0_4_fu_947_p2 <= std_logic_vector(unsigned(tmp_8_3_cast_fu_944_p1) + unsigned(iv_V));
counter_V_0_5_fu_970_p2 <= std_logic_vector(unsigned(tmp_8_4_cast_fu_967_p1) + unsigned(iv_V));
counter_V_0_6_fu_993_p2 <= std_logic_vector(unsigned(tmp_8_5_cast_fu_990_p1) + unsigned(iv_V));
counter_V_0_7_fu_1016_p2 <= std_logic_vector(unsigned(tmp_8_6_cast_fu_1013_p1) + unsigned(iv_V));
counter_V_0_8_fu_1039_p2 <= std_logic_vector(unsigned(tmp_8_7_cast_fu_1036_p1) + unsigned(iv_V));
counter_V_0_9_fu_1062_p2 <= std_logic_vector(unsigned(tmp_8_8_cast_fu_1059_p1) + unsigned(iv_V));
counter_V_0_s_fu_1265_p2 <= std_logic_vector(unsigned(tmp_8_9_cast_fu_1262_p1) + unsigned(iv_V));
counter_V_fu_855_p2 <= std_logic_vector(unsigned(tmp_2_fu_851_p1) + unsigned(iv_V));
grp_aestest_fu_744_ap_ce_assign_proc : process(ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage16, ap_CS_fsm_pp0_stage17, ap_CS_fsm_pp0_stage18, ap_CS_fsm_pp0_stage19, ap_CS_fsm_pp0_stage20, ap_CS_fsm_pp0_stage21, ap_CS_fsm_pp0_stage22, ap_CS_fsm_pp0_stage23, ap_CS_fsm_pp0_stage24, ap_CS_fsm_pp0_stage25, ap_CS_fsm_pp0_stage26, ap_CS_fsm_pp0_stage27, ap_CS_fsm_pp0_stage28, ap_CS_fsm_pp0_stage29, ap_CS_fsm_pp0_stage30, ap_CS_fsm_pp0_stage31, ap_CS_fsm_pp0_stage32, ap_CS_fsm_pp0_stage33, ap_CS_fsm_pp0_stage34, ap_CS_fsm_pp0_stage35, ap_CS_fsm_pp0_stage36, ap_CS_fsm_pp0_stage37, ap_CS_fsm_pp0_stage38, ap_CS_fsm_pp0_stage39, ap_CS_fsm_pp0_stage40, ap_CS_fsm_pp0_stage41, ap_CS_fsm_pp0_stage42, ap_block_pp0_stage8_flag00011001, ap_block_pp0_stage11_flag00011001, ap_block_pp0_stage14_flag00011001, ap_block_pp0_stage17_flag00011001, ap_block_pp0_stage20_flag00011001, ap_block_pp0_stage23_flag00011001, ap_block_pp0_stage26_flag00011001, ap_block_pp0_stage29_flag00011001, ap_block_pp0_stage32_flag00011001, ap_block_pp0_stage35_flag00011001, ap_block_pp0_stage38_flag00011001, ap_block_pp0_stage9_flag00011001, ap_block_pp0_stage12_flag00011001, ap_block_pp0_stage15_flag00011001, ap_block_pp0_stage18_flag00011001, ap_block_pp0_stage21_flag00011001, ap_block_pp0_stage24_flag00011001, ap_block_pp0_stage27_flag00011001, ap_block_pp0_stage30_flag00011001, ap_block_pp0_stage33_flag00011001, ap_block_pp0_stage36_flag00011001, ap_block_pp0_stage39_flag00011001, ap_block_pp0_stage10_flag00011001, ap_block_pp0_stage13_flag00011001, ap_block_pp0_stage16_flag00011001, ap_block_pp0_stage19_flag00011001, ap_block_pp0_stage22_flag00011001, ap_block_pp0_stage25_flag00011001, ap_block_pp0_stage28_flag00011001, ap_block_pp0_stage31_flag00011001, ap_block_pp0_stage34_flag00011001, ap_block_pp0_stage37_flag00011001, ap_block_pp0_stage41_flag00011001, ap_block_pp0_stage42_flag00011001, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_block_pp0_stage40_flag00011001)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00011001 = ap_const_boolean_0)))) then
grp_aestest_fu_744_ap_ce <= ap_const_logic_1;
else
grp_aestest_fu_744_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_aestest_fu_744_ap_start <= ap_reg_grp_aestest_fu_744_ap_start;
grp_aestest_fu_744_inptext_V_read_assign_proc : process(ap_enable_reg_pp0_iter0, counter_V_fu_855_p2, counter_V_0_1_fu_878_p2, counter_V_0_2_fu_901_p2, counter_V_0_3_fu_924_p2, counter_V_0_4_fu_947_p2, counter_V_0_5_fu_970_p2, counter_V_0_6_fu_993_p2, counter_V_0_7_fu_1016_p2, counter_V_0_8_fu_1039_p2, counter_V_0_9_fu_1062_p2, counter_V_0_s_fu_1265_p2, counter_V_0_10_fu_1383_p2, counter_V_0_11_fu_1402_p2, counter_V_0_12_fu_1415_p2, counter_V_0_13_fu_1428_p2, counter_V_0_14_fu_1441_p2, counter_V_0_15_fu_1454_p2, counter_V_0_16_fu_1467_p2, counter_V_0_17_fu_1480_p2, counter_V_0_18_fu_1493_p2, counter_V_0_19_fu_1506_p2, counter_V_0_20_fu_1519_p2, counter_V_0_21_fu_1532_p2, counter_V_0_22_fu_1545_p2, counter_V_0_23_fu_1558_p2, counter_V_0_24_fu_1571_p2, counter_V_0_25_fu_1584_p2, counter_V_0_26_fu_1597_p2, counter_V_0_27_fu_1610_p2, counter_V_0_28_fu_1623_p2, counter_V_0_29_fu_1636_p2, counter_V_0_30_fu_1649_p2, ap_condition_7969, ap_condition_7973, ap_condition_7977, ap_condition_7981, ap_condition_7985, ap_condition_7989, ap_condition_7993, ap_condition_7997, ap_condition_8001, ap_condition_8005, ap_condition_8008, ap_condition_8011, ap_condition_8014, ap_condition_8017, ap_condition_8020, ap_condition_8023, ap_condition_8026, ap_condition_8029, ap_condition_8032, ap_condition_8035, ap_condition_8038, ap_condition_8041, ap_condition_8044, ap_condition_8047, ap_condition_8050, ap_condition_8053, ap_condition_8056, ap_condition_8059, ap_condition_8062, ap_condition_8065, ap_condition_8068, ap_condition_8071)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if ((ap_condition_8071 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_30_fu_1649_p2;
elsif ((ap_condition_8068 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_29_fu_1636_p2;
elsif ((ap_condition_8065 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_28_fu_1623_p2;
elsif ((ap_condition_8062 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_27_fu_1610_p2;
elsif ((ap_condition_8059 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_26_fu_1597_p2;
elsif ((ap_condition_8056 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_25_fu_1584_p2;
elsif ((ap_condition_8053 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_24_fu_1571_p2;
elsif ((ap_condition_8050 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_23_fu_1558_p2;
elsif ((ap_condition_8047 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_22_fu_1545_p2;
elsif ((ap_condition_8044 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_21_fu_1532_p2;
elsif ((ap_condition_8041 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_20_fu_1519_p2;
elsif ((ap_condition_8038 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_19_fu_1506_p2;
elsif ((ap_condition_8035 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_18_fu_1493_p2;
elsif ((ap_condition_8032 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_17_fu_1480_p2;
elsif ((ap_condition_8029 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_16_fu_1467_p2;
elsif ((ap_condition_8026 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_15_fu_1454_p2;
elsif ((ap_condition_8023 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_14_fu_1441_p2;
elsif ((ap_condition_8020 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_13_fu_1428_p2;
elsif ((ap_condition_8017 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_12_fu_1415_p2;
elsif ((ap_condition_8014 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_11_fu_1402_p2;
elsif ((ap_condition_8011 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_10_fu_1383_p2;
elsif ((ap_condition_8008 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_s_fu_1265_p2;
elsif ((ap_condition_8005 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_9_fu_1062_p2;
elsif ((ap_condition_8001 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_8_fu_1039_p2;
elsif ((ap_condition_7997 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_7_fu_1016_p2;
elsif ((ap_condition_7993 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_6_fu_993_p2;
elsif ((ap_condition_7989 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_5_fu_970_p2;
elsif ((ap_condition_7985 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_4_fu_947_p2;
elsif ((ap_condition_7981 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_3_fu_924_p2;
elsif ((ap_condition_7977 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_2_fu_901_p2;
elsif ((ap_condition_7973 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_0_1_fu_878_p2;
elsif ((ap_condition_7969 = ap_const_boolean_1)) then
grp_aestest_fu_744_inptext_V_read <= counter_V_fu_855_p2;
else
grp_aestest_fu_744_inptext_V_read <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_aestest_fu_744_inptext_V_read <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_786_p2 <= (reg_752 xor grp_aestest_fu_744_ap_return);
grp_fu_794_p2 <= (reg_756 xor grp_aestest_fu_744_ap_return);
grp_fu_802_p2 <= (reg_760 xor grp_aestest_fu_744_ap_return);
i_fu_1389_p2 <= std_logic_vector(unsigned(i_op_assign_reg_732) + unsigned(ap_const_lv16_20));
i_op_assign_cast1_fu_817_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_op_assign_phi_fu_736_p4),32));
i_op_assign_phi_fu_736_p4_assign_proc : process(tmp_reg_1932, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000, i_op_assign_reg_732, i_reg_2295)
begin
if (((tmp_reg_1932 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
i_op_assign_phi_fu_736_p4 <= i_reg_2295;
else
i_op_assign_phi_fu_736_p4 <= i_op_assign_reg_732;
end if;
end process;
length_r_ap_vld_in_sig_assign_proc : process(length_r_ap_vld, length_r_ap_vld_preg)
begin
if ((ap_const_logic_1 = length_r_ap_vld)) then
length_r_ap_vld_in_sig <= length_r_ap_vld;
else
length_r_ap_vld_in_sig <= length_r_ap_vld_preg;
end if;
end process;
length_r_blk_n_assign_proc : process(ap_start, ap_CS_fsm_state1, length_r_ap_vld)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
length_r_blk_n <= length_r_ap_vld;
else
length_r_blk_n <= ap_const_logic_1;
end if;
end process;
length_r_in_sig_assign_proc : process(length_r, length_r_preg, length_r_ap_vld)
begin
if ((ap_const_logic_1 = length_r_ap_vld)) then
length_r_in_sig <= length_r;
else
length_r_in_sig <= length_r_preg;
end if;
end process;
tmp_10_fu_1421_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_s_reg_2015),64));
tmp_11_cast_fu_940_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_fu_935_p2),32));
tmp_11_fu_935_p2 <= (tmp_98_reg_1940 or ap_const_lv15_5);
tmp_12_fu_1434_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_reg_2025),64));
tmp_13_cast_fu_963_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_13_fu_958_p2),32));
tmp_13_fu_958_p2 <= (tmp_98_reg_1940 or ap_const_lv15_6);
tmp_14_fu_1447_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_13_reg_2035),64));
tmp_15_cast_fu_986_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_15_fu_981_p2),32));
tmp_15_fu_981_p2 <= (tmp_98_reg_1940 or ap_const_lv15_7);
tmp_16_fu_1460_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_15_reg_2045),64));
tmp_17_cast_fu_1009_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_17_fu_1004_p2),32));
tmp_17_fu_1004_p2 <= (tmp_98_reg_1940 or ap_const_lv15_8);
tmp_18_fu_1473_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_17_reg_2055),64));
tmp_19_cast_fu_1032_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_19_fu_1027_p2),32));
tmp_19_fu_1027_p2 <= (tmp_98_reg_1940 or ap_const_lv15_9);
tmp_1_fu_830_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_op_assign_reg_732),64));
tmp_20_fu_1486_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_19_reg_2065),64));
tmp_21_cast_fu_1055_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_21_fu_1050_p2),32));
tmp_21_fu_1050_p2 <= (tmp_98_reg_1940 or ap_const_lv15_A);
tmp_22_fu_1499_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_21_reg_2075),64));
tmp_23_cast_fu_1078_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_23_fu_1073_p2),32));
tmp_23_fu_1073_p2 <= (tmp_98_reg_1940 or ap_const_lv15_B);
tmp_24_fu_1512_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_23_reg_2085),64));
tmp_25_cast_fu_1087_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_25_fu_1082_p2),32));
tmp_25_fu_1082_p2 <= (tmp_98_reg_1940 or ap_const_lv15_C);
tmp_26_fu_1525_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_25_reg_2091),64));
tmp_27_cast_fu_1096_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_27_fu_1091_p2),32));
tmp_27_fu_1091_p2 <= (tmp_98_reg_1940 or ap_const_lv15_D);
tmp_28_fu_1538_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_27_reg_2097),64));
tmp_29_cast_fu_1105_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_29_fu_1100_p2),32));
tmp_29_fu_1100_p2 <= (tmp_98_reg_1940 or ap_const_lv15_E);
tmp_2_fu_851_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_op_assign_reg_732),128));
tmp_30_fu_1551_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_29_reg_2103),64));
tmp_31_cast_fu_1114_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_31_fu_1109_p2),32));
tmp_31_fu_1109_p2 <= (tmp_98_reg_1940 or ap_const_lv15_F);
tmp_32_fu_1564_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_31_reg_2109),64));
tmp_33_cast_fu_1123_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_33_fu_1118_p2),32));
tmp_33_fu_1118_p2 <= (tmp_98_reg_1940 or ap_const_lv15_10);
tmp_34_fu_1577_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_33_reg_2115),64));
tmp_35_cast_fu_1132_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_35_fu_1127_p2),32));
tmp_35_fu_1127_p2 <= (tmp_98_reg_1940 or ap_const_lv15_11);
tmp_36_fu_1590_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_35_reg_2121),64));
tmp_37_cast_fu_1141_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_37_fu_1136_p2),32));
tmp_37_fu_1136_p2 <= (tmp_98_reg_1940 or ap_const_lv15_12);
tmp_38_fu_1603_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_37_reg_2127),64));
tmp_39_cast_fu_1150_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_39_fu_1145_p2),32));
tmp_39_fu_1145_p2 <= (tmp_98_reg_1940 or ap_const_lv15_13);
tmp_40_fu_1616_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_39_reg_2133),64));
tmp_41_cast_fu_1159_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_41_fu_1154_p2),32));
tmp_41_fu_1154_p2 <= (tmp_98_reg_1940 or ap_const_lv15_14);
tmp_42_fu_1629_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_41_reg_2139),64));
tmp_43_cast_fu_1168_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_43_fu_1163_p2),32));
tmp_43_fu_1163_p2 <= (tmp_98_reg_1940 or ap_const_lv15_15);
tmp_44_fu_1642_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_43_reg_2145),64));
tmp_45_cast_fu_1177_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_45_fu_1172_p2),32));
tmp_45_fu_1172_p2 <= (tmp_98_reg_1940 or ap_const_lv15_16);
tmp_46_fu_1655_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_45_reg_2151),64));
tmp_47_cast_fu_1186_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_47_fu_1181_p2),32));
tmp_47_fu_1181_p2 <= (tmp_98_reg_1940 or ap_const_lv15_17);
tmp_48_fu_1659_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_47_reg_2157),64));
tmp_49_cast_fu_1195_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_49_fu_1190_p2),32));
tmp_49_fu_1190_p2 <= (tmp_98_reg_1940 or ap_const_lv15_18);
tmp_4_cast_fu_847_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_4_fu_841_p2),32));
tmp_4_fu_841_p2 <= (tmp_98_fu_826_p1 or ap_const_lv15_1);
tmp_50_fu_1663_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_49_reg_2163),64));
tmp_51_cast_fu_1204_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_51_fu_1199_p2),32));
tmp_51_fu_1199_p2 <= (tmp_98_reg_1940 or ap_const_lv15_19);
tmp_52_fu_1667_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_51_reg_2169),64));
tmp_53_cast_fu_1213_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_53_fu_1208_p2),32));
tmp_53_fu_1208_p2 <= (tmp_98_reg_1940 or ap_const_lv15_1A);
tmp_54_fu_1671_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_53_reg_2175),64));
tmp_55_cast_fu_1222_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_55_fu_1217_p2),32));
tmp_55_fu_1217_p2 <= (tmp_98_reg_1940 or ap_const_lv15_1B);
tmp_56_fu_1675_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_55_reg_2181),64));
tmp_57_cast_fu_1231_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_57_fu_1226_p2),32));
tmp_57_fu_1226_p2 <= (tmp_98_reg_1940 or ap_const_lv15_1C);
tmp_58_fu_1679_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_57_reg_2187),64));
tmp_59_cast_fu_1240_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_59_fu_1235_p2),32));
tmp_59_fu_1235_p2 <= (tmp_98_reg_1940 or ap_const_lv15_1D);
tmp_5_10_fu_1271_p2 <= "1" when (unsigned(tmp_23_cast_fu_1078_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_11_fu_1276_p2 <= "1" when (unsigned(tmp_25_cast_fu_1087_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_12_fu_1281_p2 <= "1" when (unsigned(tmp_27_cast_fu_1096_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_13_fu_1286_p2 <= "1" when (unsigned(tmp_29_cast_fu_1105_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_14_fu_1291_p2 <= "1" when (unsigned(tmp_31_cast_fu_1114_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_15_fu_1296_p2 <= "1" when (unsigned(tmp_33_cast_fu_1123_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_16_fu_1301_p2 <= "1" when (unsigned(tmp_35_cast_fu_1132_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_17_fu_1306_p2 <= "1" when (unsigned(tmp_37_cast_fu_1141_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_18_fu_1311_p2 <= "1" when (unsigned(tmp_39_cast_fu_1150_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_19_fu_1316_p2 <= "1" when (unsigned(tmp_41_cast_fu_1159_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_1_fu_861_p2 <= "1" when (unsigned(tmp_4_cast_fu_847_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_20_fu_1321_p2 <= "1" when (unsigned(tmp_43_cast_fu_1168_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_21_fu_1326_p2 <= "1" when (unsigned(tmp_45_cast_fu_1177_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_22_fu_1331_p2 <= "1" when (unsigned(tmp_47_cast_fu_1186_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_23_fu_1336_p2 <= "1" when (unsigned(tmp_49_cast_fu_1195_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_24_fu_1341_p2 <= "1" when (unsigned(tmp_51_cast_fu_1204_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_25_fu_1346_p2 <= "1" when (unsigned(tmp_53_cast_fu_1213_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_26_fu_1351_p2 <= "1" when (unsigned(tmp_55_cast_fu_1222_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_27_fu_1356_p2 <= "1" when (unsigned(tmp_57_cast_fu_1231_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_28_fu_1361_p2 <= "1" when (unsigned(tmp_59_cast_fu_1240_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_29_fu_1366_p2 <= "1" when (unsigned(tmp_61_cast_fu_1249_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_2_fu_884_p2 <= "1" when (unsigned(tmp_6_cast_fu_871_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_30_fu_1371_p2 <= "1" when (unsigned(tmp_63_cast_fu_1258_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_3_fu_907_p2 <= "1" when (unsigned(tmp_8_cast_fu_894_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_4_fu_930_p2 <= "1" when (unsigned(tmp_cast_fu_917_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_5_fu_953_p2 <= "1" when (unsigned(tmp_11_cast_fu_940_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_6_fu_976_p2 <= "1" when (unsigned(tmp_13_cast_fu_963_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_7_fu_999_p2 <= "1" when (unsigned(tmp_15_cast_fu_986_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_8_fu_1022_p2 <= "1" when (unsigned(tmp_17_cast_fu_1009_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_9_fu_1045_p2 <= "1" when (unsigned(tmp_19_cast_fu_1032_p1) < unsigned(length_r_in_sig)) else "0";
tmp_5_fu_1376_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_4_reg_1985),64));
tmp_5_s_fu_1068_p2 <= "1" when (unsigned(tmp_21_cast_fu_1055_p1) < unsigned(length_r_in_sig)) else "0";
tmp_60_fu_1683_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_59_reg_2193),64));
tmp_61_cast_fu_1249_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_61_fu_1244_p2),32));
tmp_61_fu_1244_p2 <= (tmp_98_reg_1940 or ap_const_lv15_1E);
tmp_62_fu_1687_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_61_reg_2199),64));
tmp_63_cast_fu_1258_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_63_fu_1253_p2),32));
tmp_63_fu_1253_p2 <= (tmp_98_reg_1940 or ap_const_lv15_1F);
tmp_64_fu_1691_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_63_reg_2205),64));
tmp_66_fu_821_p2 <= "1" when (unsigned(i_op_assign_cast1_fu_817_p1) < unsigned(length_r_in_sig)) else "0";
tmp_6_cast_fu_871_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_6_fu_866_p2),32));
tmp_6_fu_866_p2 <= (tmp_98_reg_1940 or ap_const_lv15_2);
tmp_7_fu_1395_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_6_reg_1995),64));
tmp_8_10_cast_fu_1380_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_23_reg_2085),128));
tmp_8_11_cast_fu_1399_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_25_reg_2091),128));
tmp_8_12_cast_fu_1412_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_27_reg_2097),128));
tmp_8_13_cast_fu_1425_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_29_reg_2103),128));
tmp_8_14_cast_fu_1438_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_31_reg_2109),128));
tmp_8_15_cast_fu_1451_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_33_reg_2115),128));
tmp_8_16_cast_fu_1464_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_35_reg_2121),128));
tmp_8_17_cast_fu_1477_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_37_reg_2127),128));
tmp_8_18_cast_fu_1490_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_39_reg_2133),128));
tmp_8_19_cast_fu_1503_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_41_reg_2139),128));
tmp_8_1_cast_fu_898_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_6_reg_1995),128));
tmp_8_20_cast_fu_1516_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_43_reg_2145),128));
tmp_8_21_cast_fu_1529_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_45_reg_2151),128));
tmp_8_22_cast_fu_1542_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_47_reg_2157),128));
tmp_8_23_cast_fu_1555_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_49_reg_2163),128));
tmp_8_24_cast_fu_1568_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_51_reg_2169),128));
tmp_8_25_cast_fu_1581_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_53_reg_2175),128));
tmp_8_26_cast_fu_1594_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_55_reg_2181),128));
tmp_8_27_cast_fu_1607_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_57_reg_2187),128));
tmp_8_28_cast_fu_1620_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_59_reg_2193),128));
tmp_8_29_cast_fu_1633_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_61_reg_2199),128));
tmp_8_2_cast_fu_921_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_8_reg_2005),128));
tmp_8_30_cast_fu_1646_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_63_reg_2205),128));
tmp_8_3_cast_fu_944_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_s_reg_2015),128));
tmp_8_4_cast_fu_967_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_reg_2025),128));
tmp_8_5_cast_fu_990_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_13_reg_2035),128));
tmp_8_6_cast_fu_1013_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_15_reg_2045),128));
tmp_8_7_cast_fu_1036_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_17_reg_2055),128));
tmp_8_8_cast_fu_1059_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_19_reg_2065),128));
tmp_8_9_cast_fu_1262_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_21_reg_2075),128));
tmp_8_cast_6_fu_875_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_4_reg_1985),128));
tmp_8_cast_fu_894_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_8_fu_889_p2),32));
tmp_8_fu_889_p2 <= (tmp_98_reg_1940 or ap_const_lv15_3);
tmp_98_fu_826_p1 <= i_op_assign_reg_732(15 - 1 downto 0);
tmp_9_fu_1408_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_8_reg_2005),64));
tmp_cast_fu_917_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_s_fu_912_p2),32));
tmp_fu_809_p3 <= i_op_assign_phi_fu_736_p4(15 downto 15);
tmp_s_fu_912_p2 <= (tmp_98_reg_1940 or ap_const_lv15_4);
end behav;
| gpl-3.0 | d80f8d49df732fa530b83076a886c663 | 0.665038 | 2.538299 | false | false | false | false |
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`protect end_protected
| gpl-2.0 | ec42bfc18c696a332196f2a9e8c2944e | 0.928806 | 1.907723 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/xfft_v9_0/hdl/mux_bus4.vhd | 2 | 20,743 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13616)
`protect data_block
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`protect end_protected
| gpl-2.0 | 7ee4f03f969aafcd887b7267ccf6c461 | 0.939642 | 1.840224 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xfft_v9_0/hdl/adder.vhd | 3 | 8,876 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4832)
`protect data_block
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`protect end_protected
| gpl-2.0 | 48ce75e8ba7f925c08ac9e7dab7c7c50 | 0.921699 | 1.910049 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/shared/addsub_logic.vhd | 3 | 27,248 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18432)
`protect data_block
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`protect end_protected
| gpl-2.0 | 72c4341a4e0b9abd0e17b1b1a43e5710 | 0.944326 | 1.839465 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/c_reg_fd_v12_0/hdl/c_reg_fd_v12_0_comp.vhd | 3 | 7,819 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4048)
`protect data_block
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`protect end_protected
| gpl-2.0 | 39778b8c6fa291561ad5623e6774da62 | 0.913416 | 1.924914 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/floating_point_v7_0/hdl/flt_add/flt_add_lat_norm.vhd | 2 | 25,238 | `protect begin_protected
`protect version = 1
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16944)
`protect data_block
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`protect end_protected
| gpl-2.0 | b2d149fa78f73c8fd078a77f362d929b | 0.943815 | 1.84219 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/bram/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2_synth.vhd | 11 | 75,944 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 54480)
`protect data_block
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`protect end_protected
| gpl-2.0 | 4e47178c7efb0898cf1a6f5dabdee187 | 0.953123 | 1.823955 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab2/Shadow_Register/Lab04/ipcore_dir/DEBUG_RAM.vhd | 2 | 5,784 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file DEBUG_RAM.vhd when simulating
-- the core, DEBUG_RAM. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY DEBUG_RAM IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END DEBUG_RAM;
ARCHITECTURE DEBUG_RAM_a OF DEBUG_RAM IS
-- synthesis translate_off
COMPONENT wrapped_DEBUG_RAM
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_DEBUG_RAM USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 4,
c_addrb_width => 8,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "20",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 1,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 16,
c_read_depth_b => 256,
c_read_width_a => 64,
c_read_width_b => 4,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 16,
c_write_depth_b => 256,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 64,
c_write_width_b => 4,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_DEBUG_RAM
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
addrb => addrb,
doutb => doutb
);
-- synthesis translate_on
END DEBUG_RAM_a;
| gpl-3.0 | af27d0bce01bc4fe222bf58dc0de52de | 0.533195 | 3.916046 | false | false | false | false |
UVVM/UVVM_All | bitvis_vip_spi/src/transaction_pkg.vhd | 1 | 5,783 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package transaction_pkg is
--===============================================================================================
-- t_operation
-- - Bitvis defined BFM operations
--===============================================================================================
type t_operation is (
-- UVVM common
NO_OPERATION,
AWAIT_COMPLETION,
AWAIT_ANY_COMPLETION,
ENABLE_LOG_MSG,
DISABLE_LOG_MSG,
FLUSH_COMMAND_QUEUE,
FETCH_RESULT,
INSERT_DELAY,
TERMINATE_CURRENT_COMMAND,
-- VVC local
MASTER_TRANSMIT_AND_RECEIVE, MASTER_TRANSMIT_AND_CHECK, MASTER_TRANSMIT_ONLY, MASTER_RECEIVE_ONLY, MASTER_CHECK_ONLY,
SLAVE_TRANSMIT_AND_RECEIVE, SLAVE_TRANSMIT_AND_CHECK, SLAVE_TRANSMIT_ONLY, SLAVE_RECEIVE_ONLY, SLAVE_CHECK_ONLY);
constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300;
constant C_VVC_CMD_DATA_MAX_LENGTH : natural := 32;
constant C_VVC_CMD_MAX_WORDS : natural := C_SPI_VVC_DATA_ARRAY_WIDTH;
--==========================================================================================
--
-- Transaction info types, constants and global signal
--
--==========================================================================================
-- Transaction status
type t_transaction_status is (INACTIVE, IN_PROGRESS, FAILED, SUCCEEDED);
constant C_TRANSACTION_STATUS_DEFAULT : t_transaction_status := INACTIVE;
-- VVC Meta
type t_vvc_meta is record
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
cmd_idx : integer;
end record;
constant C_VVC_META_DEFAULT : t_vvc_meta := (
msg => (others => ' '),
cmd_idx => -1
);
-- Base transaction
type t_base_transaction is record
operation : t_operation;
data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
num_words : natural;
word_length : natural;
when_to_start_transfer : t_when_to_start_transfer;
action_when_transfer_is_done : t_action_when_transfer_is_done;
action_between_words : t_action_between_words;
vvc_meta : t_vvc_meta;
transaction_status : t_transaction_status;
end record;
constant C_BASE_TRANSACTION_SET_DEFAULT : t_base_transaction := (
operation => NO_OPERATION,
data => (others => (others => '0')),
data_exp => (others => (others => '0')),
num_words => 0,
word_length => 0,
when_to_start_transfer => START_TRANSFER_IMMEDIATE,
action_when_transfer_is_done => RELEASE_LINE_AFTER_TRANSFER,
action_between_words => HOLD_LINE_BETWEEN_WORDS,
vvc_meta => C_VVC_META_DEFAULT,
transaction_status => C_TRANSACTION_STATUS_DEFAULT
);
-- Transaction group
type t_transaction_group is record
bt : t_base_transaction;
end record;
constant C_TRANSACTION_GROUP_DEFAULT : t_transaction_group := (
bt => C_BASE_TRANSACTION_SET_DEFAULT
);
-- Global transaction info trigger signal
type t_spi_transaction_trigger_array is array (natural range <>) of std_logic;
signal global_spi_vvc_transaction_trigger : t_spi_transaction_trigger_array(0 to C_MAX_VVC_INSTANCE_NUM-1) :=
(others => '0');
-- Type is defined as array to coincide with channel based VVCs
type t_spi_transaction_group_array is array (natural range <>) of t_transaction_group;
-- Shared transaction info variable
shared variable shared_spi_vvc_transaction_info : t_spi_transaction_group_array(0 to C_MAX_VVC_INSTANCE_NUM-1) :=
(others => C_TRANSACTION_GROUP_DEFAULT);
end package transaction_pkg; | mit | 4bac092891a94ae95f503da03d234b7f | 0.501124 | 4.847443 | false | false | false | false |
amerryfellow/dlx | packages/rwcache.vhd | 1 | 4,202 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use ieee.std_logic_misc.all;
package RWCACHE_PKG is
constant RWCACHE_WAYS : natural := 2;
constant RWCACHE_NUMSETS : natural := 4; --Depth of ICache
constant RWCACHE_WORDS : natural := 2;
constant DATA_SIZE : natural := 32;
constant RWCACHE_SETINDEXSIZE : natural := 2;
constant RWCACHE_NUMLINES : natural := RWCACHE_WAYS;
constant RWCACHE_INDEXSIZE : natural := 1;
constant RWCACHE_TAGSIZE : natural := DATA_SIZE - RWCACHE_INDEXSIZE - RWCACHE_SETINDEXSIZE;
constant RWCACHE_TAGOFFSET : natural := DATA_SIZE - RWCACHE_TAGSIZE;
constant RWCACHE_SETOFFSET : natural := RWCACHE_TAGOFFSET - RWCACHE_SETINDEXSIZE;
constant RWCACHE_INDEXOFFSET : natural := RWCACHE_INDEXSIZE;
constant RWCACHE_COUNTERSIZE : natural := 8;
subtype RWCACHE_LINES is natural range 0 to RWCACHE_NUMLINES - 1;
subtype RWCACHE_SETS is natural range 0 to 2**RWCACHE_SETINDEXSIZE - 1;
subtype RWCACHE_INDEX is natural range 0 to 2**RWCACHE_INDEXSIZE - 1;
type DATA_WORDS is array (RWCACHE_INDEX) of std_logic_vector(DATA_SIZE - 1 downto 0);
type RWCACHE_RECORD is
record
tag : std_logic_vector(RWCACHE_TAGSIZE-1 downto 0);
words : DATA_WORDS;
counter : integer range 0 to 2**RWCACHE_COUNTERSIZE;
valid : std_logic;
end record;
type RWCACHE_LINE is array (RWCACHE_LINES) of RWCACHE_RECORD;
type RWCACHE_TYPE is array (RWCACHE_SETS) of RWCACHE_LINE;
subtype state_type is std_logic_vector(2 downto 0);
constant STATE_FLUSH_MEM : state_type := "000";
constant STATE_MISS : state_type := "001";
constant STATE_COMPARE_TAGS : state_type := "010";
constant STATE_WRITE_MISS : state_type := "011";
constant STATE_IDLE : state_type := "100";
function COMPARE_TAGS(
x : std_logic_vector(RWCACHE_TAGSIZE - 1 downto 0 );
y : std_logic_vector(RWCACHE_TAGSIZE - 1 downto 0 )
) return std_logic;
function GET_SET(
x : std_logic_vector(DATA_SIZE - 1 downto 0)
) return integer;
function GET_REPLACEMENT_LINE(
pc : std_logic_vector(DATA_SIZE - 1 downto 0);
cache: RWCACHE_TYPE
) return natural;
end RWCACHE_PKG;
package body RWCACHE_PKG is
function COMPARE_TAGS(
x : std_logic_vector(RWCACHE_TAGSIZE-1 downto 0);
y : std_logic_vector(RWCACHE_TAGSIZE-1 downto 0)
) return std_logic is
begin
return and_reduce(x xnor y);
end COMPARE_TAGS;
function GET_SET (
x : std_logic_vector(DATA_SIZE - 1 downto 0)
) return integer is
variable ret : integer :=0;
variable y : std_logic_vector(RWCACHE_TAGOFFSET-1 downto RWCACHE_SETOFFSET);
begin
y := x(RWCACHE_TAGOFFSET-1 downto RWCACHE_SETOFFSET);
ret := conv_integer(unsigned (y));
return ret;
end GET_SET;
function GET_REPLACEMENT_LINE (
pc : std_logic_vector(DATA_SIZE - 1 downto 0);
cache: RWCACHE_TYPE
) return natural is
variable count : natural range 0 to 2**RWCACHE_COUNTERSIZE;
variable min_found : std_logic;
variable i : natural := 0;
variable to_evict : natural range 0 to 2**RWCACHE_COUNTERSIZE;
variable countValid : std_logic;
begin
-- count := cache( GET_SET(pc) )(i).counter;
to_evict := i;
countValid := '0';
count:=0;
-- Iterate
-- while i < (RWCACHE_NUMLINES - 2) loop
-- Check counter value
-- if(cache( GET_SET(pc) )(i+1).valid = '0') then
-- to_evict := i + 1;
-- exit;
-- elsif(cache( GET_SET(pc) )(i+1).counter < count) then
-- -- New least frequently used -> save its index and counter value
-- count := cache( GET_SET(pc) )(i+1).counter;
-- to_evict := i + 1;
-- end if;
-- i := i + 1 ;
-- end loop;
-- Iterate
for i in 0 to RWCACHE_NUMLINES - 1 loop
-- If not valid -> USE IT
if(cache( GET_SET(pc) )(i).valid = '0') then
to_evict := i;
exit;
-- Line is busy, but counter not initialized
elsif(countValid = '0') then
count := cache(GET_SET(pc))(i).counter;
countValid := '1';
to_evict := i;
-- Line is busy, and counter initialized: check if lower
elsif(cache( GET_SET(pc) )(i).counter < count) then
-- New least frequently used -> save its index and counter value
count := cache( GET_SET(pc) )(i).counter;
to_evict := i;
end if;
end loop;
return to_evict;
end GET_REPLACEMENT_LINE;
end package body;
| gpl-3.0 | 9ebbdb956663d532b342e32c02f48b1a | 0.683722 | 2.880055 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/clk_108MHz/clk_108MHz_clk_wiz.vhd | 3 | 7,419 | -- file: clk_108MHz_clk_wiz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___108.000______0.000______50.0______127.691_____97.646
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_____________100____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_108MHz_clk_wiz is
port
(-- Clock in ports
clk_100MHz : in std_logic;
-- Clock out ports
clk_108MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_108MHz_clk_wiz;
architecture xilinx of clk_108MHz_clk_wiz is
-- Input clock buffering / unused connectors
signal clk_100MHz_clk_108MHz : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout_clk_108MHz : std_logic;
signal clkfbout_buf_clk_108MHz : std_logic;
signal clkfboutb_unused : std_logic;
signal clk_108MHz_clk_108MHz : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
signal locked_int : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_ibufg : IBUF
port map
(O => clk_100MHz_clk_108MHz,
I => clk_100MHz);
-- Clocking PRIMITIVE
--------------------------------------
-- Instantiation of the MMCM PRIMITIVE
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 10.125,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 9.375,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(
CLKFBOUT => clkfbout_clk_108MHz,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clk_108MHz_clk_108MHz,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf_clk_108MHz,
CLKIN1 => clk_100MHz_clk_108MHz,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => locked_int,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => '0');
locked <= locked_int;
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf_clk_108MHz,
I => clkfbout_clk_108MHz);
clkout1_buf : BUFG
port map
(O => clk_108MHz,
I => clk_108MHz_clk_108MHz);
end xilinx;
| gpl-2.0 | b9edd5aa9bd91cb43d1d9ebe4c100d3d | 0.57164 | 4.251576 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab2/Shadow_Reg_No_VGA/Shadow_EX_NoVGA/ipcore_dir/EXTERNAL_MEMORY/example_design/EXTERNAL_MEMORY_exdes.vhd | 2 | 4,655 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: EXTERNAL_MEMORY_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY EXTERNAL_MEMORY_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END EXTERNAL_MEMORY_exdes;
ARCHITECTURE xilinx OF EXTERNAL_MEMORY_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT EXTERNAL_MEMORY IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : EXTERNAL_MEMORY
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| gpl-3.0 | 8263b6f91ba04511106e576029b0bf40 | 0.570999 | 4.774359 | false | false | false | false |
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| gpl-2.0 | a407a024da259959550f5c330faddb60 | 0.940379 | 1.86066 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_7/part_1/ip/clk_base/clk_base_clk_wiz.vhd | 10 | 7,703 | -- file: clk_base_clk_wiz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___100.000______0.000______50.0______130.958_____98.575
-- CLK_OUT2___250.000______0.000______50.0______110.209_____98.575
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_base_clk_wiz is
port
(-- Clock in ports
clk_raw : in std_logic;
-- Clock out ports
clk_100MHz : out std_logic;
clk_250MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_base_clk_wiz;
architecture xilinx of clk_base_clk_wiz is
-- Input clock buffering / unused connectors
signal clk_raw_clk_base : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout_clk_base : std_logic;
signal clkfbout_buf_clk_base : std_logic;
signal clkfboutb_unused : std_logic;
signal clk_100MHz_clk_base : std_logic;
signal clkout0b_unused : std_logic;
signal clk_250MHz_clk_base : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
signal locked_int : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_ibufg : IBUF
port map
(O => clk_raw_clk_base,
I => clk_raw);
-- Clocking PRIMITIVE
--------------------------------------
-- Instantiation of the MMCM PRIMITIVE
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 10.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 10.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 4,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(
CLKFBOUT => clkfbout_clk_base,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clk_100MHz_clk_base,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clk_250MHz_clk_base,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf_clk_base,
CLKIN1 => clk_raw_clk_base,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => locked_int,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => '0');
locked <= locked_int;
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf_clk_base,
I => clkfbout_clk_base);
clkout1_buf : BUFG
port map
(O => clk_100MHz,
I => clk_100MHz_clk_base);
clkout2_buf : BUFG
port map
(O => clk_250MHz,
I => clk_250MHz_clk_base);
end xilinx;
| gpl-2.0 | a091f78a81804a3c52fa72f1efee2518 | 0.567831 | 4.159287 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fir/fir_compiler_v7_1/hdl/dpr_mem.vhd | 2 | 19,986 | `protect begin_protected
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`protect end_protected
| gpl-2.0 | 49f991fad6609d6dbe686f02291aafbb | 0.941209 | 1.8564 | false | false | false | false |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/axi_utils_v2_0/17fb2e9a/hdl/axi_utils_v2_0_vh_rfs.vhd | 2 | 291,505 | `protect begin_protected
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| mit | f0dad70f8ff625cae4fd9404bf1b2c4b | 0.955548 | 1.810444 | false | false | false | false |
UVVM/UVVM_All | bitvis_vip_scoreboard/src/predefined_sb.vhd | 1 | 3,995 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
-- Inspired by similar functionality in SystemVerilog/UVM and OSVVM.
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Local package
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
package local_pkg is
function slv_to_string(
constant value : in std_logic_vector
) return string;
end package local_pkg;
package body local_pkg is
function slv_to_string(
constant value : in std_logic_vector
) return string is
begin
return to_string(value, HEX, KEEP_LEADING_0, INCL_RADIX);
end function;
end package body local_pkg;
------------------------------------------------------------------------------------------
--
-- slv_sb_pkg
--
-- Predefined scoreboard package for std_logic_vector. Vector length is defined by
-- the constant C_SB_SLV_WIDTH located under scoreboard adaptions in adaptions_pkg.
--
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
use work.local_pkg.all;
-- WARNING! The slv_sb_pkg will be deprecated
package slv_sb_pkg is new work.generic_sb_pkg
generic map (t_element => std_logic_vector(C_SB_SLV_WIDTH-1 downto 0),
element_match => std_match,
to_string_element => slv_to_string);
------------------------------------------------------------------------------------------
--
-- slv8_sb_pkg
--
-- Predefined scoreboard package for std_logic_vector(7 downto 0).
--
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
use work.local_pkg.all;
package slv8_sb_pkg is new work.generic_sb_pkg
generic map (t_element => std_logic_vector(7 downto 0),
element_match => std_match,
to_string_element => slv_to_string);
------------------------------------------------------------------------------------------
--
-- int_sb_pkg
--
-- Predefined scoreboard package for integer.
--
------------------------------------------------------------------------------------------
package int_sb_pkg is new work.generic_sb_pkg
generic map (t_element => integer,
element_match => "=",
to_string_element => to_string); | mit | f131d38583a6e8a45196ecf5b7be51ca | 0.474343 | 5.115237 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/dds/dds_compiler_v6_0/hdl/dither_wrap.vhd | 6 | 23,856 | `protect begin_protected
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`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15920)
`protect data_block
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`protect end_protected
| gpl-2.0 | f346b7516abad413a963040d2b2fc2c1 | 0.942027 | 1.83649 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/xfft_v9_0/hdl/tw_addr_gen.vhd | 2 | 10,323 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5904)
`protect data_block
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| gpl-2.0 | 6df8b52424539adcaade73af6a1bdfc9 | 0.925022 | 1.908839 | false | false | false | false |
r2t2sdr/r2t2 | fpga/modules/r2t2/adc/adc_lvds_if.vhdl | 1 | 4,020 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.NUMERIC_STD.all;
LIBRARY unisim;
USE unisim.VCOMPONENTS.all;
ENTITY adc_lvds_if IS
PORT(
LVDS_ADC_A_D0_N : IN std_logic;
LVDS_ADC_A_D0_P : IN std_logic;
LVDS_ADC_A_D1_N : IN std_logic;
LVDS_ADC_A_D1_P : IN std_logic;
LVDS_ADC_B_D0_N : IN std_logic;
LVDS_ADC_B_D0_P : IN std_logic;
LVDS_ADC_B_D1_N : IN std_logic;
LVDS_ADC_B_D1_P : IN std_logic;
LVDS_ADC_DCO_N : IN std_logic;
LVDS_ADC_DCO_P : IN std_logic;
LVDS_ADC_FCO_N : IN std_logic;
LVDS_ADC_FCO_P : IN std_logic;
resetn : IN std_logic;
clk200Mhz : IN std_logic;
pl_clk : IN std_logic;
M_AXIS_ACD_A_tdata : OUT std_logic_vector(15 DOWNTO 0);
M_AXIS_ACD_A_tvalid : OUT std_logic;
M_AXIS_ACD_B_tdata : OUT std_logic_vector(15 DOWNTO 0);
M_AXIS_ACD_B_tvalid : OUT std_logic
);
END ENTITY adc_lvds_if ;
ARCHITECTURE struct OF adc_lvds_if IS
SIGNAL adc_clk_div : std_logic;
SIGNAL bitslip : std_logic;
SIGNAL adc_clk : std_logic;
SIGNAL adc_A_tdata : std_logic_vector(15 DOWNTO 0);
SIGNAL adc_B_tdata : std_logic_vector(15 DOWNTO 0);
COMPONENT adc_data_channel
PORT (
LVDS_ADC_D0_N : IN std_logic;
LVDS_ADC_D0_P : IN std_logic;
LVDS_ADC_D1_N : IN std_logic;
LVDS_ADC_D1_P : IN std_logic;
adc_clk : IN std_logic;
adc_clk_div : IN std_logic;
bitslip : IN std_logic;
reset : IN std_logic;
adc_data : OUT std_logic_vector (15 DOWNTO 0)
);
END COMPONENT adc_data_channel;
COMPONENT adc_dco_alignment
PORT (
LVDS_ADC_DCO_N : IN std_logic ;
LVDS_ADC_DCO_P : IN std_logic ;
adc_clk : OUT std_logic ;
adc_clk_div : OUT std_logic
);
END COMPONENT adc_dco_alignment;
COMPONENT adc_fco_alignment
PORT (
LVDS_ADC_FCO_N : IN std_logic;
LVDS_ADC_FCO_P : IN std_logic;
adc_clk : IN std_logic;
adc_clk_div : IN std_logic;
reset : IN std_logic;
clk200Mhz : IN std_logic;
bitslip : OUT std_logic
);
END COMPONENT adc_fco_alignment;
BEGIN
M_AXIS_ACD_A_tdata <= adc_A_tdata;
M_AXIS_ACD_B_tdata <= adc_B_tdata;
M_AXIS_ACD_A_tvalid <= '1';
M_AXIS_ACD_B_tvalid <= '1';
DCO_alignment : adc_dco_alignment
PORT MAP (
LVDS_ADC_DCO_N => LVDS_ADC_DCO_N,
LVDS_ADC_DCO_P => LVDS_ADC_DCO_P,
adc_clk => adc_clk,
adc_clk_div => adc_clk_div
);
FCO_alignment : adc_fco_alignment
PORT MAP (
LVDS_ADC_FCO_N => LVDS_ADC_FCO_N,
LVDS_ADC_FCO_P => LVDS_ADC_FCO_P,
adc_clk => adc_clk,
adc_clk_div => adc_clk_div,
reset => resetn,
clk200Mhz => clk200Mhz,
bitslip => bitslip
);
Data_ChannelA : adc_data_channel
PORT MAP (
LVDS_ADC_D0_N => LVDS_ADC_A_D0_N,
LVDS_ADC_D0_P => LVDS_ADC_A_D0_P,
LVDS_ADC_D1_N => LVDS_ADC_A_D1_N,
LVDS_ADC_D1_P => LVDS_ADC_A_D1_P,
adc_clk => adc_clk,
adc_clk_div => adc_clk_div,
bitslip => bitslip,
reset => resetn,
adc_data => adc_A_tdata
);
Data_ChannelB : adc_data_channel
PORT MAP (
LVDS_ADC_D0_N => LVDS_ADC_B_D0_N,
LVDS_ADC_D0_P => LVDS_ADC_B_D0_P,
LVDS_ADC_D1_N => LVDS_ADC_B_D1_N,
LVDS_ADC_D1_P => LVDS_ADC_B_D1_P,
adc_clk => adc_clk,
adc_clk_div => adc_clk_div,
bitslip => bitslip,
reset => resetn,
adc_data => adc_B_tdata
);
END ARCHITECTURE struct;
| gpl-3.0 | aaa5e0d585c740e30399634e7e37e1f2 | 0.503234 | 2.938596 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab2/Shadow_Register/Lab04/Instruction_Memory.vhd | 12 | 5,844 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file Instruction_Memory.vhd when simulating
-- the core, Instruction_Memory. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY Instruction_Memory IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END Instruction_Memory;
ARCHITECTURE Instruction_Memory_a OF Instruction_Memory IS
-- synthesis translate_off
COMPONENT wrapped_Instruction_Memory
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_Instruction_Memory USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 5,
c_addrb_width => 5,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "Instruction_Memory.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 20,
c_read_depth_b => 20,
c_read_width_a => 16,
c_read_width_b => 16,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 20,
c_write_depth_b => 20,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 16,
c_write_width_b => 16,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_Instruction_Memory
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END Instruction_Memory_a;
| gpl-3.0 | 9b13b2e7c39b3c3f052d728089a1f3d0 | 0.526352 | 3.980926 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/floating_point_v7_0_comp.vhd | 3 | 21,412 | `protect begin_protected
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`protect end_protected
| gpl-2.0 | cc4e8275bcde8d4bf53320a829995aac | 0.939473 | 1.839677 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/cmpy_v6_0/hdl/cmpy_xfft_so_sync.vhd | 2 | 10,801 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6256)
`protect data_block
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`protect end_protected
| gpl-2.0 | da11fd0750e62215b29b9c78a7b512a9 | 0.928895 | 1.886967 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/flt_recip/flt_recip_approx.vhd | 3 | 16,419 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10416)
`protect data_block
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`protect end_protected
| gpl-2.0 | 8f37d7e62480d658cec02ebfb8b87015 | 0.936415 | 1.834115 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab2/ProgramCounter/ProgramCounter/ipcore_dir/Instr_Mem/example_design/Instr_Mem_exdes.vhd | 6 | 4,617 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
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-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Instr_Mem_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY Instr_Mem_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END Instr_Mem_exdes;
ARCHITECTURE xilinx OF Instr_Mem_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT Instr_Mem IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : Instr_Mem
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| gpl-3.0 | e44798d340e60546522889526e703bbc | 0.567468 | 4.735385 | false | false | false | false |
UVVM/uvvm_vvc_framework | bitvis_uart/src/uart.vhd | 2 | 3,591 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.uart_pif_pkg.all;
entity uart is
generic (
GC_START_BIT : std_logic := '0';
GC_STOP_BIT : std_logic := '1';
GC_CLOCKS_PER_BIT : integer := 16;
GC_MIN_EQUAL_SAMPLES_PER_BIT : integer := 15); -- Number of equal samples needed for valid bit, uart samples on every clock
port(
-- DSP interface and general control signals
clk : in std_logic;
arst : in std_logic;
-- CPU interface
cs : in std_logic;
addr : in unsigned(2 downto 0);
wr : in std_logic;
rd : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0) := (others => '0');
-- UART related signals
rx_a : in std_logic;
tx : out std_logic
);
begin
assert GC_MIN_EQUAL_SAMPLES_PER_BIT > GC_CLOCKS_PER_BIT/2 and GC_MIN_EQUAL_SAMPLES_PER_BIT < GC_CLOCKS_PER_BIT
report "GC_MIN_EQUAL_SAMPLES_PER_BIT must be between GC_CLOCKS_PER_BIT/2 and GC_CLOCKS_PER_BIT"
severity FAILURE;
end uart;
architecture rtl of uart is
-- PIF-core interface
signal p2c : t_p2c; --
signal c2p : t_c2p; --
begin
i_uart_pif : entity work.uart_pif
port map (
arst => arst, --
clk => clk, --
-- CPU interface
cs => cs, --
addr => addr, --
wr => wr, --
rd => rd, --
wdata => wdata, --
rdata => rdata, --
--
p2c => p2c, --
c2p => c2p --
);
i_uart_core : entity work.uart_core
generic map(
GC_START_BIT => GC_START_BIT,
GC_STOP_BIT => GC_STOP_BIT,
GC_CLOCKS_PER_BIT => GC_CLOCKS_PER_BIT,
GC_MIN_EQUAL_SAMPLES_PER_BIT => GC_MIN_EQUAL_SAMPLES_PER_BIT
)
port map (
clk => clk, --
arst => arst, --
-- PIF-core interface
p2c => p2c, --
c2p => c2p, --
-- Interrupt related signals
rx_a => rx_a, --
tx => tx
);
end rtl;
| mit | 29164a1bf8116e6b5ef5ca477b2c14c9 | 0.465887 | 4.214789 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/clk_108MHz/clk_108MHz.vhd | 2 | 4,576 | -- file: clk_108MHz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___108.000______0.000______50.0______127.691_____97.646
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_108MHz is
port
(-- Clock in ports
clk_100MHz : in std_logic;
-- Clock out ports
clk_108MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_108MHz;
architecture xilinx of clk_108MHz is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_108MHz,clk_wiz_v5_1,{component_name=clk_108MHz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component clk_108MHz_clk_wiz
port
(-- Clock in ports
clk_100MHz : in std_logic;
-- Clock out ports
clk_108MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end component;
begin
U0: clk_108MHz_clk_wiz
port map (
-- Clock in ports
clk_100MHz => clk_100MHz,
-- Clock out ports
clk_108MHz => clk_108MHz,
-- Status and control signals
locked => locked
);
end xilinx;
| gpl-2.0 | 2853e33ca15dcc01b59be6d4a2f98d14 | 0.634834 | 4.190476 | false | false | false | false |
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| gpl-2.0 | 0b2a32934c988c022c4d081bfcc741b0 | 0.932739 | 1.881323 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab2/NewCombined/DC_CTL.vhd | 1 | 2,585 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:52:59 03/25/2016
-- Design Name:
-- Module Name: DC_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DC_CTL is
Port ( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (3 downto 0);
RB : in STD_LOGIC_VECTOR (3 downto 0);
RA0 : in STD_LOGIC_VECTOR (3 downto 0);
RA1 : in STD_LOGIC_VECTOR (3 downto 0);
RA2 : in STD_LOGIC_VECTOR (3 downto 0);
OPC0 : in STD_LOGIC_VECTOR (3 downto 0);
OPC1 : in STD_LOGIC_VECTOR (3 downto 0);
OPC2 : in STD_LOGIC_VECTOR (3 downto 0);
OPC : in STD_LOGIC_VECTOR (3 downto 0);
OP1_SEL : out STD_LOGIC_VECTOR (2 downto 0);
OP2_SEL : out STD_LOGIC_VECTOR (1 downto 0));
end DC_CTL;
architecture Mixed of DC_CTL is
signal OP1 : STD_LOGIC_VECTOR (2 downto 0) := (OTHERS => '0');
signal OP2 : STD_LOGIC_VECTOR (1 downto 0) := (OTHERS => '0');
begin
process(RA, RB, RA0, RA1, RA2)
begin
-- if (rising_edge(CLK)) then
if(OPC = "1111") then
OP1 <= "100";
elsif (RA = RA0 and OPC0(3 downto 2) /= "11") then
OP1 <= "001";
-- OP1_SEL <= OP1;
elsif (RA = RA1 and OPC1(3 downto 2) /= "11") then
OP1 <= "010";
-- OP1_SEL <= OP1;
elsif (RA = RA2 and OPC1(3 downto 2) /= "11") then
OP1 <= "011";
-- OP1_SEL <= OP1;
else
OP1 <= "000";
-- OP1_SEL <= OP1;
end if;
-- OP1_SEL <= OP1;
if (RB = RA0 and OPC0(3 downto 2) /= "11") then
OP2 <= "01";
elsif (RB = RA1 and OPC1(3 downto 2) /= "11") then
OP2 <= "10";
elsif (RB = RA2 and OPC2(3 downto 2) /= "11") then
OP2 <= "11";
else
OP2 <= "00";
end if;
-- end if;
end process;
OP1_SEL <= OP1;
with OPC select OP2_SEL <=
OP2 when "0000" | "0001" | "0010" | "0011" | "0100",
"00" when "0101" | "0110" | "0111" | "1000" | "1001" | "1010",
"00" when OTHERS;
end Mixed;
| gpl-3.0 | dd02bbcb1ad95322cd1c8db0b7f386d9 | 0.529207 | 2.920904 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xfft_v9_0/hdl/arith_shift1.vhd | 3 | 7,754 | `protect begin_protected
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| gpl-2.0 | 0a2c998f86916c748f9b13abc94033f8 | 0.913722 | 1.921685 | false | false | false | false |
amerryfellow/dlx | packages/aluTypes.vhd | 1 | 1,686 | library ieee;
use ieee.std_logic_1164.all;
package alu_types is
subtype TYPE_OP is std_logic_vector(4 downto 0);
constant ALUADD : TYPE_OP:="00001";
constant ALUSUB : TYPE_OP:="00010";
constant ALUAND : TYPE_OP:="00011";
constant ALUOR : TYPE_OP:="00100";
constant ALUXOR : TYPE_OP:="00101";
constant ALUSLL : TYPE_OP:="00110";
constant ALUSRL : TYPE_OP:="00111";
constant ALUSRA : TYPE_OP:="01000";
constant ALUSEQ : TYPE_OP:="01001";
constant ALUSNE : TYPE_OP:="01010";
constant ALUSGEU : TYPE_OP:="01011";
constant ALUSGTU : TYPE_OP:="01100";
constant ALUSLEU : TYPE_OP:="01101";
constant ALUSLTU : TYPE_OP:="01110";
constant ALUSGE : TYPE_OP:="01111";
constant ALUSGT : TYPE_OP:="10000";
constant ALUSLE : TYPE_OP:="10001";
constant ALUSLT : TYPE_OP:="10010";
constant NSUMG : integer := 32;--Number of bit for the sum generator
constant NRCA : integer:= 4;--Number of bit for the RCA BLOCK
constant NCSBLOCK : integer :=NRCA;--Number of bit for each carry select blocks
constant NCSUMG : integer := NSUMG/4;--Number of bit for the carry in for sum generator
constant NMUX : integer := NRCA;--Number of bit for the MUX in the carry select block
function LOG(x: integer) return integer;
--constant adderBits : integer := 2*NSUMG;
end alu_types;
package body alu_types is
--Calculate the logarithm in base 2 of the number in input.
function LOG(x: integer) return integer is
variable power: integer:=0;
variable index: integer;
begin
index := x;
while index > 1 loop
power := power + 1;
index := index/2;
end loop;
return power;
end LOG;
end package body;
| gpl-3.0 | 74c322c78bc65f82417896ccb7bd6cec | 0.669632 | 3.048825 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab1/Poject_Lab01/Project1/Instruction_Memory_TL.vhd | 1 | 2,004 | -- Company: Team 5
-- Engineer:
-- -Timothy Doucette Jr
-- -Robert Mushrall III
-- -Christopher Parks
--
-- Create Date: 14:26:47 03/31/2016
-- Design Name:
-- Module Name: Instruction_Memory_TL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Instruction_Memory_TL is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
RA : out STD_LOGIC_VECTOR (3 downto 0);
RB : out STD_LOGIC_VECTOR (3 downto 0);
OP : out STD_LOGIC_VECTOR (3 downto 0);
IMM : out STD_LOGIC_VECTOR (7 downto 0));
end Instruction_Memory_TL;
architecture Structural of Instruction_Memory_TL is
--Program counter
signal EN : STD_LOGIC := '1';
--signal RST : STD_LOGIC := '0';
signal INSADR :STD_LOGIC_VECTOR (4 downto 0) := (OTHERS => '0');
--INSTRUCTION MEMORY--
signal ADDRA : STD_LOGIC_VECTOR (4 downto 0) := (OTHERS => '0');
signal DINA : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal WEA: STD_LOGIC := '0';
signal DOUTA : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
begin
OP <= DOUTA(15 downto 12);
RA <= DOUTA(11 downto 8);
RB <= DOUTA(7 downto 4);
IMM <= DOUTA(7 downto 0);
U1: entity work.programCounter
generic map(PCWIDTH => 5)
port map(CLK => CLK,
EN => EN,
RST => RST,
INSADR => ADDRA);
U2: entity work.Instr_Mem
port map(CLKA => not CLK,
ADDRA => ADDRA ,
DINA => DINA,
WEA(0) => WEA,
DOUTA => DOUTA);
end Structural; | gpl-3.0 | 8a4cb92f4f71e50c7a9797cbfc43d38f | 0.610778 | 3.312397 | false | false | false | false |
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`protect end_protected
| gpl-2.0 | 3babe78ad4de1cf6a9d09be4891d2f16 | 0.918115 | 1.913024 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xfft_v9_0/hdl/r22_tw_gen.vhd | 3 | 15,535 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9760)
`protect data_block
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`protect end_protected
| gpl-2.0 | 89ed43636ff8fbc5de0495636d625c12 | 0.935436 | 1.858921 | false | false | false | false |
notti/dis_se | vhdl/clkgen.vhd | 1 | 1,497 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.procedures.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity clkgen is
port(
rsti : in std_logic;
clki : in std_logic;
rsto : out std_logic;
clko : out std_logic;
clk2xo : out std_logic
);
end clkgen;
architecture Structural of clkgen is
signal locked : std_logic;
signal clk_i : std_logic;
signal clk_ubuf : std_logic;
signal clk2x_ubuf : std_logic;
begin
clk2x_buffer: BUFG
port map(
I => clk2x_ubuf,
O => clk2xo
);
clk_buffer: BUFG
port map(
I => clk_ubuf,
O => clk_i
);
DCM_SP_inst : DCM_SP
generic map (
CLKIN_PERIOD => 20.0,
CLK_FEEDBACK => "1X",
DFS_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => FALSE,
DLL_FREQUENCY_MODE => "LOW")
port map (
CLK0 => clk_ubuf,
CLK180 => open,
CLK270 => open,
CLK2X => clk2x_ubuf,
CLK2X180 => open,
CLK90 => open,
CLKDV => open,
CLKFX => open,
CLKFX180 => open,
LOCKED => locked,
PSDONE => open,
STATUS => open,
CLKFB => clk_i,
CLKIN => clki,
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
RST => '0',
DSSEN => '0'
);
rsto <= rsti or not locked;
clko <= clk_i;
end Structural;
| bsd-2-clause | 19929e983874ceb940edd02b5853f3e5 | 0.507014 | 3.425629 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_7/part_1/ip/clk_base/clk_base_funcsim.vhdl | 10 | 8,525 | -- Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
-- Date : Sat Mar 15 17:18:29 2014
-- Host : macbook running 64-bit Arch Linux
-- Command : write_vhdl -force -mode funcsim
-- /home/keith/Documents/VHDL-lib/top/lab_2/part_1/build/lab2_part1.srcs/sources_1/ip/clk_base/clk_base_funcsim.vhdl
-- Design : clk_base
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity clk_baseclk_base_clk_wiz is
port (
clk_raw : in STD_LOGIC;
clk_100MHz : out STD_LOGIC;
clk_250MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
end clk_baseclk_base_clk_wiz;
architecture STRUCTURE of clk_baseclk_base_clk_wiz is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal clk_100MHz_clk_base : STD_LOGIC;
signal clk_250MHz_clk_base : STD_LOGIC;
signal clk_raw_clk_base : STD_LOGIC;
signal clkfbout_buf_clk_base : STD_LOGIC;
signal clkfbout_clk_base : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute box_type : string;
attribute box_type of clkf_buf : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute box_type of clkin1_ibufg : label is "PRIMITIVE";
attribute box_type of clkout1_buf : label is "PRIMITIVE";
attribute box_type of clkout2_buf : label is "PRIMITIVE";
attribute box_type of mmcm_adv_inst : label is "PRIMITIVE";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_clk_base,
O => clkfbout_buf_clk_base
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_raw,
O => clk_raw_clk_base
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_100MHz_clk_base,
O => clk_100MHz
);
clkout2_buf: unisim.vcomponents.BUFG
port map (
I => clk_250MHz_clk_base,
O => clk_250MHz
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 10.000000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 10.000000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 4,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.000000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_clk_base,
CLKFBOUT => clkfbout_clk_base,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_raw_clk_base,
CLKIN2 => \<const0>\,
CLKINSEL => \<const1>\,
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_100MHz_clk_base,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => clk_250MHz_clk_base,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6) => \<const0>\,
DADDR(5) => \<const0>\,
DADDR(4) => \<const0>\,
DADDR(3) => \<const0>\,
DADDR(2) => \<const0>\,
DADDR(1) => \<const0>\,
DADDR(0) => \<const0>\,
DCLK => \<const0>\,
DEN => \<const0>\,
DI(15) => \<const0>\,
DI(14) => \<const0>\,
DI(13) => \<const0>\,
DI(12) => \<const0>\,
DI(11) => \<const0>\,
DI(10) => \<const0>\,
DI(9) => \<const0>\,
DI(8) => \<const0>\,
DI(7) => \<const0>\,
DI(6) => \<const0>\,
DI(5) => \<const0>\,
DI(4) => \<const0>\,
DI(3) => \<const0>\,
DI(2) => \<const0>\,
DI(1) => \<const0>\,
DI(0) => \<const0>\,
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => \<const0>\,
LOCKED => locked,
PSCLK => \<const0>\,
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => \<const0>\,
PSINCDEC => \<const0>\,
PWRDWN => \<const0>\,
RST => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity clk_base is
port (
clk_raw : in STD_LOGIC;
clk_100MHz : out STD_LOGIC;
clk_250MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of clk_base : entity is true;
attribute core_generation_info : string;
attribute core_generation_info of clk_base : entity is "clk_base,clk_wiz_v5_1,{component_name=clk_base,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
end clk_base;
architecture STRUCTURE of clk_base is
begin
U0: entity work.clk_baseclk_base_clk_wiz
port map (
clk_100MHz => clk_100MHz,
clk_250MHz => clk_250MHz,
clk_raw => clk_raw,
locked => locked
);
end STRUCTURE;
| gpl-2.0 | a766393e8ecc603d95e062556391b14e | 0.624282 | 3.294049 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xbip_bram18k_v3_0/hdl/xbip_bram18k_v3_0.vhd | 12 | 8,791 | `protect begin_protected
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`protect end_protected
| gpl-2.0 | 0b1374b6a7b0c67477ea0276acd99cd6 | 0.923331 | 1.917757 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/flt_add/flt_add_logic.vhd | 3 | 31,681 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 21712)
`protect data_block
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`protect end_protected
| gpl-2.0 | c8cf807a4681de359133e6daa36184e7 | 0.947129 | 1.841919 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/flt_fma/flt_fma_specialcase.vhd | 3 | 15,965 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
| gpl-2.0 | 99c1b35180de1bb5ec5e2038698c7a57 | 0.937426 | 1.874266 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/bram/blk_mem_gen_v8_2/hdl/blk_mem_axi_write_fsm.vhd | 11 | 61,464 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 43760)
`protect data_block
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| gpl-2.0 | 083b071981a2be610cff658d9f0551d4 | 0.952037 | 1.823425 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/synth/fft.vhd | 2 | 11,309 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xfft:9.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY xfft_v9_0;
USE xfft_v9_0.xfft_v9_0;
ENTITY fft IS
PORT (
aclk : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_frame_started : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC;
event_status_channel_halt : OUT STD_LOGIC;
event_data_in_channel_halt : OUT STD_LOGIC;
event_data_out_channel_halt : OUT STD_LOGIC
);
END fft;
ARCHITECTURE fft_arch OF fft IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fft_arch: ARCHITECTURE IS "yes";
COMPONENT xfft_v9_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_S_AXIS_CONFIG_TDATA_WIDTH : INTEGER;
C_S_AXIS_DATA_TDATA_WIDTH : INTEGER;
C_M_AXIS_DATA_TDATA_WIDTH : INTEGER;
C_M_AXIS_DATA_TUSER_WIDTH : INTEGER;
C_M_AXIS_STATUS_TDATA_WIDTH : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_CHANNELS : INTEGER;
C_NFFT_MAX : INTEGER;
C_ARCH : INTEGER;
C_HAS_NFFT : INTEGER;
C_USE_FLT_PT : INTEGER;
C_INPUT_WIDTH : INTEGER;
C_TWIDDLE_WIDTH : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_HAS_SCALING : INTEGER;
C_HAS_BFP : INTEGER;
C_HAS_ROUNDING : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_HAS_OVFLO : INTEGER;
C_HAS_NATURAL_INPUT : INTEGER;
C_HAS_NATURAL_OUTPUT : INTEGER;
C_HAS_CYCLIC_PREFIX : INTEGER;
C_HAS_XK_INDEX : INTEGER;
C_DATA_MEM_TYPE : INTEGER;
C_TWIDDLE_MEM_TYPE : INTEGER;
C_BRAM_STAGES : INTEGER;
C_REORDER_MEM_TYPE : INTEGER;
C_USE_HYBRID_RAM : INTEGER;
C_OPTIMIZE_GOAL : INTEGER;
C_CMPY_TYPE : INTEGER;
C_BFLY_TYPE : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_status_tdata : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_status_tvalid : OUT STD_LOGIC;
m_axis_status_tready : IN STD_LOGIC;
event_frame_started : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC;
event_fft_overflow : OUT STD_LOGIC;
event_status_channel_halt : OUT STD_LOGIC;
event_data_in_channel_halt : OUT STD_LOGIC;
event_data_out_channel_halt : OUT STD_LOGIC
);
END COMPONENT xfft_v9_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF fft_arch: ARCHITECTURE IS "xfft_v9_0,Vivado 2013.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF fft_arch : ARCHITECTURE IS "fft,xfft_v9_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF fft_arch: ARCHITECTURE IS "fft,xfft_v9_0,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xfft,x_ipVersion=9.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,C_XDEVICEFAMILY=zynq,C_S_AXIS_CONFIG_TDATA_WIDTH=8,C_S_AXIS_DATA_TDATA_WIDTH=32,C_M_AXIS_DATA_TDATA_WIDTH=64,C_M_AXIS_DATA_TUSER_WIDTH=16,C_M_AXIS_STATUS_TDATA_WIDTH=1,C_THROTTLE_SCHEME=1,C_CHANNELS=1,C_NFFT_MAX=12,C_ARCH=1,C_HAS_NFFT=0,C_USE_FLT_PT=0,C_INPUT_WIDTH=16,C_TWIDDLE_WIDTH=16,C_OUTPUT_WIDTH=29,C_HAS_SCALING=0,C_HAS_BFP=0,C_HAS_ROUNDING=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_HAS_OVFLO=0,C_HAS_NATURAL_INPUT=1,C_HAS_NATURAL_OUTPUT=1,C_HAS_CYCLIC_PREFIX=0,C_HAS_XK_INDEX=1,C_DATA_MEM_TYPE=1,C_TWIDDLE_MEM_TYPE=1,C_BRAM_STAGES=0,C_REORDER_MEM_TYPE=1,C_USE_HYBRID_RAM=0,C_OPTIMIZE_GOAL=0,C_CMPY_TYPE=1,C_BFLY_TYPE=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_config_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CONFIG TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_config_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CONFIG TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_config_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CONFIG TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TLAST";
ATTRIBUTE X_INTERFACE_INFO OF event_frame_started: SIGNAL IS "xilinx.com:signal:interrupt:1.0 event_frame_started_intf INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF event_tlast_unexpected: SIGNAL IS "xilinx.com:signal:interrupt:1.0 event_tlast_unexpected_intf INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF event_tlast_missing: SIGNAL IS "xilinx.com:signal:interrupt:1.0 event_tlast_missing_intf INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF event_status_channel_halt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 event_status_channel_halt_intf INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF event_data_in_channel_halt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 event_data_in_channel_halt_intf INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF event_data_out_channel_halt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 event_data_out_channel_halt_intf INTERRUPT";
BEGIN
U0 : xfft_v9_0
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_S_AXIS_CONFIG_TDATA_WIDTH => 8,
C_S_AXIS_DATA_TDATA_WIDTH => 32,
C_M_AXIS_DATA_TDATA_WIDTH => 64,
C_M_AXIS_DATA_TUSER_WIDTH => 16,
C_M_AXIS_STATUS_TDATA_WIDTH => 1,
C_THROTTLE_SCHEME => 1,
C_CHANNELS => 1,
C_NFFT_MAX => 12,
C_ARCH => 1,
C_HAS_NFFT => 0,
C_USE_FLT_PT => 0,
C_INPUT_WIDTH => 16,
C_TWIDDLE_WIDTH => 16,
C_OUTPUT_WIDTH => 29,
C_HAS_SCALING => 0,
C_HAS_BFP => 0,
C_HAS_ROUNDING => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_HAS_OVFLO => 0,
C_HAS_NATURAL_INPUT => 1,
C_HAS_NATURAL_OUTPUT => 1,
C_HAS_CYCLIC_PREFIX => 0,
C_HAS_XK_INDEX => 1,
C_DATA_MEM_TYPE => 1,
C_TWIDDLE_MEM_TYPE => 1,
C_BRAM_STAGES => 0,
C_REORDER_MEM_TYPE => 1,
C_USE_HYBRID_RAM => 0,
C_OPTIMIZE_GOAL => 0,
C_CMPY_TYPE => 1,
C_BFLY_TYPE => 0
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_config_tdata => s_axis_config_tdata,
s_axis_config_tvalid => s_axis_config_tvalid,
s_axis_config_tready => s_axis_config_tready,
s_axis_data_tdata => s_axis_data_tdata,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => s_axis_data_tlast,
m_axis_data_tdata => m_axis_data_tdata,
m_axis_data_tuser => m_axis_data_tuser,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => m_axis_data_tready,
m_axis_data_tlast => m_axis_data_tlast,
m_axis_status_tready => '1',
event_frame_started => event_frame_started,
event_tlast_unexpected => event_tlast_unexpected,
event_tlast_missing => event_tlast_missing,
event_status_channel_halt => event_status_channel_halt,
event_data_in_channel_halt => event_data_in_channel_halt,
event_data_out_channel_halt => event_data_out_channel_halt
);
END fft_arch;
| gpl-2.0 | 66b02defeb3f612add72032acb3693ce | 0.688125 | 3.193731 | false | true | false | false |
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`protect end_protected
| gpl-2.0 | 5ab8f2c3ee70ffe534732d4cb9e40300 | 0.952549 | 1.816275 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/dds/xbip_dsp48_multadd_v3_0/hdl/xbip_dsp48_multadd_synth.vhd | 4 | 16,010 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10112)
`protect data_block
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| gpl-2.0 | 1b63fc42c7e46b43858cef8f8ae92a4a | 0.935166 | 1.861411 | false | false | false | false |
mcoughli/root_of_trust | operational_os/hls/contact_discovery_axi_one_db_load/solution1/syn/vhdl/contact_discovery_AXILiteS_s_axi.vhd | 3 | 34,997 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_AXILiteS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 15;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
operation :out STD_LOGIC_VECTOR(31 downto 0);
operation_ap_vld :out STD_LOGIC;
contact_in_address0 :in STD_LOGIC_VECTOR(5 downto 0);
contact_in_ce0 :in STD_LOGIC;
contact_in_q0 :out STD_LOGIC_VECTOR(7 downto 0);
database_in_address0 :in STD_LOGIC_VECTOR(5 downto 0);
database_in_ce0 :in STD_LOGIC;
database_in_q0 :out STD_LOGIC_VECTOR(7 downto 0);
matched_out_address0 :in STD_LOGIC_VECTOR(12 downto 0);
matched_out_ce0 :in STD_LOGIC;
matched_out_we0 :in STD_LOGIC;
matched_out_d0 :in STD_LOGIC_VECTOR(0 downto 0);
matched_finished :in STD_LOGIC_VECTOR(31 downto 0);
error_out :in STD_LOGIC_VECTOR(31 downto 0);
database_size_out :in STD_LOGIC_VECTOR(31 downto 0);
contacts_size_out :in STD_LOGIC_VECTOR(31 downto 0)
);
end entity contact_discovery_AXILiteS_s_axi;
-- ------------------------Address Info-------------------
-- 0x0000 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x0004 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x0008 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x000c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0010 : Data signal of operation
-- bit 31~0 - operation[31:0] (Read/Write)
-- 0x0014 : Control signal of operation
-- bit 0 - operation_ap_vld (Read/Write/SC)
-- others - reserved
-- 0x4000 : Data signal of matched_finished
-- bit 31~0 - matched_finished[31:0] (Read)
-- 0x4004 : reserved
-- 0x4008 : Data signal of error_out
-- bit 31~0 - error_out[31:0] (Read)
-- 0x400c : reserved
-- 0x4010 : Data signal of database_size_out
-- bit 31~0 - database_size_out[31:0] (Read)
-- 0x4014 : reserved
-- 0x4018 : Data signal of contacts_size_out
-- bit 31~0 - contacts_size_out[31:0] (Read)
-- 0x401c : reserved
-- 0x0040 ~
-- 0x007f : Memory 'contact_in' (64 * 8b)
-- Word n : bit [ 7: 0] - contact_in[4n]
-- bit [15: 8] - contact_in[4n+1]
-- bit [23:16] - contact_in[4n+2]
-- bit [31:24] - contact_in[4n+3]
-- 0x0080 ~
-- 0x00bf : Memory 'database_in' (64 * 8b)
-- Word n : bit [ 7: 0] - database_in[4n]
-- bit [15: 8] - database_in[4n+1]
-- bit [23:16] - database_in[4n+2]
-- bit [31:24] - database_in[4n+3]
-- 0x2000 ~
-- 0x3fff : Memory 'matched_out' (7500 * 1b)
-- Word n : bit [ 0: 0] - matched_out[4n]
-- bit [ 8: 8] - matched_out[4n+1]
-- bit [16:16] - matched_out[4n+2]
-- bit [24:24] - matched_out[4n+3]
-- others - reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of contact_discovery_AXILiteS_s_axi is
type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset); -- read and write fsm states
signal wstate : states := wrreset;
signal rstate : states := rdreset;
signal wnext, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#0000#;
constant ADDR_GIE : INTEGER := 16#0004#;
constant ADDR_IER : INTEGER := 16#0008#;
constant ADDR_ISR : INTEGER := 16#000c#;
constant ADDR_OPERATION_DATA_0 : INTEGER := 16#0010#;
constant ADDR_OPERATION_CTRL : INTEGER := 16#0014#;
constant ADDR_MATCHED_FINISHED_DATA_0 : INTEGER := 16#4000#;
constant ADDR_MATCHED_FINISHED_CTRL : INTEGER := 16#4004#;
constant ADDR_ERROR_OUT_DATA_0 : INTEGER := 16#4008#;
constant ADDR_ERROR_OUT_CTRL : INTEGER := 16#400c#;
constant ADDR_DATABASE_SIZE_OUT_DATA_0 : INTEGER := 16#4010#;
constant ADDR_DATABASE_SIZE_OUT_CTRL : INTEGER := 16#4014#;
constant ADDR_CONTACTS_SIZE_OUT_DATA_0 : INTEGER := 16#4018#;
constant ADDR_CONTACTS_SIZE_OUT_CTRL : INTEGER := 16#401c#;
constant ADDR_CONTACT_IN_BASE : INTEGER := 16#0040#;
constant ADDR_CONTACT_IN_HIGH : INTEGER := 16#007f#;
constant ADDR_DATABASE_IN_BASE : INTEGER := 16#0080#;
constant ADDR_DATABASE_IN_HIGH : INTEGER := 16#00bf#;
constant ADDR_MATCHED_OUT_BASE : INTEGER := 16#2000#;
constant ADDR_MATCHED_OUT_HIGH : INTEGER := 16#3fff#;
constant ADDR_BITS : INTEGER := 15;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC := '0';
signal int_ap_start : STD_LOGIC := '0';
signal int_auto_restart : STD_LOGIC := '0';
signal int_gie : STD_LOGIC := '0';
signal int_ier : UNSIGNED(1 downto 0) := (others => '0');
signal int_isr : UNSIGNED(1 downto 0) := (others => '0');
signal int_operation : UNSIGNED(31 downto 0) := (others => '0');
signal int_operation_ap_vld : STD_LOGIC := '0';
signal int_matched_finished : UNSIGNED(31 downto 0) := (others => '0');
signal int_error_out : UNSIGNED(31 downto 0) := (others => '0');
signal int_database_size_out : UNSIGNED(31 downto 0) := (others => '0');
signal int_contacts_size_out : UNSIGNED(31 downto 0) := (others => '0');
-- memory signals
signal int_contact_in_address0 : UNSIGNED(3 downto 0);
signal int_contact_in_ce0 : STD_LOGIC;
signal int_contact_in_we0 : STD_LOGIC;
signal int_contact_in_be0 : UNSIGNED(3 downto 0);
signal int_contact_in_d0 : UNSIGNED(31 downto 0);
signal int_contact_in_q0 : UNSIGNED(31 downto 0);
signal int_contact_in_address1 : UNSIGNED(3 downto 0);
signal int_contact_in_ce1 : STD_LOGIC;
signal int_contact_in_we1 : STD_LOGIC;
signal int_contact_in_be1 : UNSIGNED(3 downto 0);
signal int_contact_in_d1 : UNSIGNED(31 downto 0);
signal int_contact_in_q1 : UNSIGNED(31 downto 0);
signal int_contact_in_read : STD_LOGIC;
signal int_contact_in_write : STD_LOGIC;
signal int_contact_in_shift : UNSIGNED(1 downto 0);
signal int_database_in_address0 : UNSIGNED(3 downto 0);
signal int_database_in_ce0 : STD_LOGIC;
signal int_database_in_we0 : STD_LOGIC;
signal int_database_in_be0 : UNSIGNED(3 downto 0);
signal int_database_in_d0 : UNSIGNED(31 downto 0);
signal int_database_in_q0 : UNSIGNED(31 downto 0);
signal int_database_in_address1 : UNSIGNED(3 downto 0);
signal int_database_in_ce1 : STD_LOGIC;
signal int_database_in_we1 : STD_LOGIC;
signal int_database_in_be1 : UNSIGNED(3 downto 0);
signal int_database_in_d1 : UNSIGNED(31 downto 0);
signal int_database_in_q1 : UNSIGNED(31 downto 0);
signal int_database_in_read : STD_LOGIC;
signal int_database_in_write : STD_LOGIC;
signal int_database_in_shift : UNSIGNED(1 downto 0);
signal int_matched_out_address0 : UNSIGNED(10 downto 0);
signal int_matched_out_ce0 : STD_LOGIC;
signal int_matched_out_we0 : STD_LOGIC;
signal int_matched_out_be0 : UNSIGNED(3 downto 0);
signal int_matched_out_d0 : UNSIGNED(31 downto 0);
signal int_matched_out_q0 : UNSIGNED(31 downto 0);
signal int_matched_out_address1 : UNSIGNED(10 downto 0);
signal int_matched_out_ce1 : STD_LOGIC;
signal int_matched_out_we1 : STD_LOGIC;
signal int_matched_out_be1 : UNSIGNED(3 downto 0);
signal int_matched_out_d1 : UNSIGNED(31 downto 0);
signal int_matched_out_q1 : UNSIGNED(31 downto 0);
signal int_matched_out_read : STD_LOGIC;
signal int_matched_out_write : STD_LOGIC;
signal int_matched_out_shift : UNSIGNED(1 downto 0);
component contact_discovery_AXILiteS_s_axi_ram is
generic (
BYTES : INTEGER :=4;
DEPTH : INTEGER :=256;
AWIDTH : INTEGER :=8);
port (
clk0 : in STD_LOGIC;
address0: in UNSIGNED(AWIDTH-1 downto 0);
ce0 : in STD_LOGIC;
we0 : in STD_LOGIC;
be0 : in UNSIGNED(BYTES-1 downto 0);
d0 : in UNSIGNED(BYTES*8-1 downto 0);
q0 : out UNSIGNED(BYTES*8-1 downto 0);
clk1 : in STD_LOGIC;
address1: in UNSIGNED(AWIDTH-1 downto 0);
ce1 : in STD_LOGIC;
we1 : in STD_LOGIC;
be1 : in UNSIGNED(BYTES-1 downto 0);
d1 : in UNSIGNED(BYTES*8-1 downto 0);
q1 : out UNSIGNED(BYTES*8-1 downto 0));
end component contact_discovery_AXILiteS_s_axi_ram;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 1;
m := 2;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
begin
-- ----------------------- Instantiation------------------
-- int_contact_in
int_contact_in : contact_discovery_AXILiteS_s_axi_ram
generic map (
BYTES => 4,
DEPTH => 16,
AWIDTH => log2(16))
port map (
clk0 => ACLK,
address0 => int_contact_in_address0,
ce0 => int_contact_in_ce0,
we0 => int_contact_in_we0,
be0 => int_contact_in_be0,
d0 => int_contact_in_d0,
q0 => int_contact_in_q0,
clk1 => ACLK,
address1 => int_contact_in_address1,
ce1 => int_contact_in_ce1,
we1 => int_contact_in_we1,
be1 => int_contact_in_be1,
d1 => int_contact_in_d1,
q1 => int_contact_in_q1);
-- int_database_in
int_database_in : contact_discovery_AXILiteS_s_axi_ram
generic map (
BYTES => 4,
DEPTH => 16,
AWIDTH => log2(16))
port map (
clk0 => ACLK,
address0 => int_database_in_address0,
ce0 => int_database_in_ce0,
we0 => int_database_in_we0,
be0 => int_database_in_be0,
d0 => int_database_in_d0,
q0 => int_database_in_q0,
clk1 => ACLK,
address1 => int_database_in_address1,
ce1 => int_database_in_ce1,
we1 => int_database_in_we1,
be1 => int_database_in_be1,
d1 => int_database_in_d1,
q1 => int_database_in_q1);
-- int_matched_out
int_matched_out : contact_discovery_AXILiteS_s_axi_ram
generic map (
BYTES => 4,
DEPTH => 1875,
AWIDTH => log2(1875))
port map (
clk0 => ACLK,
address0 => int_matched_out_address0,
ce0 => int_matched_out_ce0,
we0 => int_matched_out_we0,
be0 => int_matched_out_be0,
d0 => int_matched_out_d0,
q0 => int_matched_out_q0,
clk1 => ACLK,
address1 => int_matched_out_address1,
ce1 => int_matched_out_ce1,
we1 => int_matched_out_we1,
be1 => int_matched_out_be1,
d1 => int_matched_out_d1,
q1 => int_matched_out_q1);
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wrreset;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) and (int_contact_in_read = '0') and (int_database_in_read = '0') and (int_matched_out_read = '0') else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdreset;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_OPERATION_DATA_0 =>
rdata_data <= RESIZE(int_operation(31 downto 0), 32);
when ADDR_OPERATION_CTRL =>
rdata_data <= (0 => int_operation_ap_vld, others => '0');
when ADDR_MATCHED_FINISHED_DATA_0 =>
rdata_data <= RESIZE(int_matched_finished(31 downto 0), 32);
when ADDR_ERROR_OUT_DATA_0 =>
rdata_data <= RESIZE(int_error_out(31 downto 0), 32);
when ADDR_DATABASE_SIZE_OUT_DATA_0 =>
rdata_data <= RESIZE(int_database_size_out(31 downto 0), 32);
when ADDR_CONTACTS_SIZE_OUT_DATA_0 =>
rdata_data <= RESIZE(int_contacts_size_out(31 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
elsif (int_contact_in_read = '1') then
rdata_data <= int_contact_in_q1;
elsif (int_database_in_read = '1') then
rdata_data <= int_database_in_q1;
elsif (int_matched_out_read = '1') then
rdata_data <= int_matched_out_q1;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
operation <= STD_LOGIC_VECTOR(int_operation);
operation_ap_vld <= int_operation_ap_vld;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_OPERATION_DATA_0) then
int_operation(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_operation(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_operation_ap_vld <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_OPERATION_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_operation_ap_vld <= '1';
else
int_operation_ap_vld <= '0'; -- self clear
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_matched_finished <= (others => '0');
elsif (ACLK_EN = '1') then
if (true) then
int_matched_finished <= UNSIGNED(matched_finished); -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_error_out <= (others => '0');
elsif (ACLK_EN = '1') then
if (true) then
int_error_out <= UNSIGNED(error_out); -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_database_size_out <= (others => '0');
elsif (ACLK_EN = '1') then
if (true) then
int_database_size_out <= UNSIGNED(database_size_out); -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_contacts_size_out <= (others => '0');
elsif (ACLK_EN = '1') then
if (true) then
int_contacts_size_out <= UNSIGNED(contacts_size_out); -- clear on read
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
-- contact_in
int_contact_in_address0 <= SHIFT_RIGHT(UNSIGNED(contact_in_address0), 2)(3 downto 0);
int_contact_in_ce0 <= contact_in_ce0;
int_contact_in_we0 <= '0';
int_contact_in_be0 <= (others => '0');
int_contact_in_d0 <= (others => '0');
contact_in_q0 <= STD_LOGIC_VECTOR(SHIFT_RIGHT(int_contact_in_q0, TO_INTEGER(int_contact_in_shift) * 8)(7 downto 0));
int_contact_in_address1 <= raddr(5 downto 2) when ar_hs = '1' else waddr(5 downto 2);
int_contact_in_ce1 <= '1' when ar_hs = '1' or (int_contact_in_write = '1' and WVALID = '1') else '0';
int_contact_in_we1 <= '1' when int_contact_in_write = '1' and WVALID = '1' else '0';
int_contact_in_be1 <= UNSIGNED(WSTRB);
int_contact_in_d1 <= UNSIGNED(WDATA);
-- database_in
int_database_in_address0 <= SHIFT_RIGHT(UNSIGNED(database_in_address0), 2)(3 downto 0);
int_database_in_ce0 <= database_in_ce0;
int_database_in_we0 <= '0';
int_database_in_be0 <= (others => '0');
int_database_in_d0 <= (others => '0');
database_in_q0 <= STD_LOGIC_VECTOR(SHIFT_RIGHT(int_database_in_q0, TO_INTEGER(int_database_in_shift) * 8)(7 downto 0));
int_database_in_address1 <= raddr(5 downto 2) when ar_hs = '1' else waddr(5 downto 2);
int_database_in_ce1 <= '1' when ar_hs = '1' or (int_database_in_write = '1' and WVALID = '1') else '0';
int_database_in_we1 <= '1' when int_database_in_write = '1' and WVALID = '1' else '0';
int_database_in_be1 <= UNSIGNED(WSTRB);
int_database_in_d1 <= UNSIGNED(WDATA);
-- matched_out
int_matched_out_address0 <= SHIFT_RIGHT(UNSIGNED(matched_out_address0), 2)(10 downto 0);
int_matched_out_ce0 <= matched_out_ce0;
int_matched_out_we0 <= matched_out_we0;
int_matched_out_be0 <= SHIFT_LEFT(TO_UNSIGNED(1, 4), TO_INTEGER(UNSIGNED(matched_out_address0(1 downto 0))));
int_matched_out_d0 <= UNSIGNED(RESIZE(UNSIGNED(matched_out_d0), 8)) & UNSIGNED(RESIZE(UNSIGNED(matched_out_d0), 8)) & UNSIGNED(RESIZE(UNSIGNED(matched_out_d0), 8)) & UNSIGNED(RESIZE(UNSIGNED(matched_out_d0), 8));
int_matched_out_address1 <= raddr(12 downto 2) when ar_hs = '1' else waddr(12 downto 2);
int_matched_out_ce1 <= '1' when ar_hs = '1' or (int_matched_out_write = '1' and WVALID = '1') else '0';
int_matched_out_we1 <= '1' when int_matched_out_write = '1' and WVALID = '1' else '0';
int_matched_out_be1 <= UNSIGNED(WSTRB);
int_matched_out_d1 <= UNSIGNED(WDATA);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_contact_in_read <= '0';
elsif (ACLK_EN = '1') then
if (ar_hs = '1' and raddr >= ADDR_CONTACT_IN_BASE and raddr <= ADDR_CONTACT_IN_HIGH) then
int_contact_in_read <= '1';
else
int_contact_in_read <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_contact_in_write <= '0';
elsif (ACLK_EN = '1') then
if (aw_hs = '1' and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) >= ADDR_CONTACT_IN_BASE and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) <= ADDR_CONTACT_IN_HIGH) then
int_contact_in_write <= '1';
elsif (WVALID = '1') then
int_contact_in_write <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (contact_in_ce0 = '1') then
int_contact_in_shift <= UNSIGNED(contact_in_address0(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_database_in_read <= '0';
elsif (ACLK_EN = '1') then
if (ar_hs = '1' and raddr >= ADDR_DATABASE_IN_BASE and raddr <= ADDR_DATABASE_IN_HIGH) then
int_database_in_read <= '1';
else
int_database_in_read <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_database_in_write <= '0';
elsif (ACLK_EN = '1') then
if (aw_hs = '1' and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) >= ADDR_DATABASE_IN_BASE and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) <= ADDR_DATABASE_IN_HIGH) then
int_database_in_write <= '1';
elsif (WVALID = '1') then
int_database_in_write <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (database_in_ce0 = '1') then
int_database_in_shift <= UNSIGNED(database_in_address0(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_matched_out_read <= '0';
elsif (ACLK_EN = '1') then
if (ar_hs = '1' and raddr >= ADDR_MATCHED_OUT_BASE and raddr <= ADDR_MATCHED_OUT_HIGH) then
int_matched_out_read <= '1';
else
int_matched_out_read <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_matched_out_write <= '0';
elsif (ACLK_EN = '1') then
if (aw_hs = '1' and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) >= ADDR_MATCHED_OUT_BASE and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) <= ADDR_MATCHED_OUT_HIGH) then
int_matched_out_write <= '1';
elsif (WVALID = '1') then
int_matched_out_write <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (matched_out_ce0 = '1') then
int_matched_out_shift <= UNSIGNED(matched_out_address0(1 downto 0));
end if;
end if;
end if;
end process;
end architecture behave;
library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity contact_discovery_AXILiteS_s_axi_ram is
generic (
BYTES : INTEGER :=4;
DEPTH : INTEGER :=256;
AWIDTH : INTEGER :=8);
port (
clk0 : in STD_LOGIC;
address0: in UNSIGNED(AWIDTH-1 downto 0);
ce0 : in STD_LOGIC;
we0 : in STD_LOGIC;
be0 : in UNSIGNED(BYTES-1 downto 0);
d0 : in UNSIGNED(BYTES*8-1 downto 0);
q0 : out UNSIGNED(BYTES*8-1 downto 0);
clk1 : in STD_LOGIC;
address1: in UNSIGNED(AWIDTH-1 downto 0);
ce1 : in STD_LOGIC;
we1 : in STD_LOGIC;
be1 : in UNSIGNED(BYTES-1 downto 0);
d1 : in UNSIGNED(BYTES*8-1 downto 0);
q1 : out UNSIGNED(BYTES*8-1 downto 0));
end entity contact_discovery_AXILiteS_s_axi_ram;
architecture behave of contact_discovery_AXILiteS_s_axi_ram is
signal address0_tmp : UNSIGNED(AWIDTH-1 downto 0);
signal address1_tmp : UNSIGNED(AWIDTH-1 downto 0);
type RAM_T is array (0 to DEPTH - 1) of UNSIGNED(BYTES*8 - 1 downto 0);
shared variable mem : RAM_T := (others => (others => '0'));
begin
process (address0)
begin
address0_tmp <= address0;
--synthesis translate_off
if (address0 > DEPTH-1) then
address0_tmp <= (others => '0');
else
address0_tmp <= address0;
end if;
--synthesis translate_on
end process;
process (address1)
begin
address1_tmp <= address1;
--synthesis translate_off
if (address1 > DEPTH-1) then
address1_tmp <= (others => '0');
else
address1_tmp <= address1;
end if;
--synthesis translate_on
end process;
--read port 0
process (clk0) begin
if (clk0'event and clk0 = '1') then
if (ce0 = '1') then
q0 <= mem(to_integer(address0_tmp));
end if;
end if;
end process;
--read port 1
process (clk1) begin
if (clk1'event and clk1 = '1') then
if (ce1 = '1') then
q1 <= mem(to_integer(address1_tmp));
end if;
end if;
end process;
gen_write : for i in 0 to BYTES - 1 generate
begin
--write port 0
process (clk0)
begin
if (clk0'event and clk0 = '1') then
if (ce0 = '1' and we0 = '1' and be0(i) = '1') then
mem(to_integer(address0_tmp))(8*i+7 downto 8*i) := d0(8*i+7 downto 8*i);
end if;
end if;
end process;
--write port 1
process (clk1)
begin
if (clk1'event and clk1 = '1') then
if (ce1 = '1' and we1 = '1' and be1(i) = '1') then
mem(to_integer(address1_tmp))(8*i+7 downto 8*i) := d1(8*i+7 downto 8*i);
end if;
end if;
end process;
end generate;
end architecture behave;
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`protect end_protected
| gpl-2.0 | aee6562c4b2b6c6142fd48ca3a792864 | 0.943591 | 1.834253 | false | false | false | false |
notti/dis_se | vhdl/procedures.vhd | 1 | 15,742 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;
package procedures is
subtype t_data is std_logic_vector(7 downto 0);
subtype t_data2 is std_logic_vector(15 downto 0);
type t_data_array is array(natural range <>) of t_data;
type t_data2_array is array(natural range <>) of t_data2;
type t_2array is array(natural range <>) of std_logic_vector(1 downto 0);
type t_3array is array(natural range <>) of std_logic_vector(2 downto 0);
type t_4array is array(natural range <>) of std_logic_vector(3 downto 0);
constant ARG_NONE : std_logic_vector(1 downto 0) := "00";
constant ARG_REG : std_logic_vector(1 downto 0) := "01";
constant ARG_MEM : std_logic_vector(1 downto 0) := "10";
constant ARG_IMM : std_logic_vector(1 downto 0) := "11";
constant CALU_NOOP : std_logic_vector(2 downto 0) := "000";
constant CALU_ADD : std_logic_vector(2 downto 0) := "001";
constant CALU_SUB : std_logic_vector(2 downto 0) := "010";
constant CALU_UMUL : std_logic_vector(2 downto 0) := "011";
constant CALU_SMUL : std_logic_vector(2 downto 0) := "100";
constant CALU_AND : std_logic_vector(2 downto 0) := "101";
constant CALU_OR : std_logic_vector(2 downto 0) := "110";
constant CALU_XOR : std_logic_vector(2 downto 0) := "111";
constant SALU_NOOP : std_logic_vector(2 downto 0) := "000";
constant SALU_ADD : std_logic_vector(2 downto 0) := "001";
constant SALU_SUB : std_logic_vector(2 downto 0) := "010";
constant SALU_SAR : std_logic_vector(2 downto 0) := "011";
constant SALU_SLR : std_logic_vector(2 downto 0) := "100";
constant SALU_AND : std_logic_vector(2 downto 0) := "101";
constant SALU_OR : std_logic_vector(2 downto 0) := "110";
constant SALU_XOR : std_logic_vector(2 downto 0) := "111";
constant ALUIN_0 : std_logic_vector(2 downto 0) := "110";
constant ALUIN_1 : std_logic_vector(2 downto 0) := "111";
type t_vliw is
record
-- fetch_decode
arg_type : t_2array(5 downto 0);
arg_memchunk : t_2array(5 downto 0);
-- indirect_fetch
arg_val : std_logic_vector(5 downto 0);
arg_assign : t_3array(5 downto 0);
mem_fetch : std_logic_vector(5 downto 0);
mem_memchunk : t_2array(5 downto 0);
-- stage 1
s1_in1a : std_logic_vector(2 downto 0);
s1_in1b : std_logic_vector(2 downto 0);
s1_op1 : std_logic_vector(2 downto 0);
s1_point1 : std_logic_vector(2 downto 0);
s1_out1 : std_logic_vector(2 downto 0);
s1_in2a : std_logic_vector(2 downto 0);
s1_in2b : std_logic_vector(2 downto 0);
s1_op2 : std_logic_vector(2 downto 0);
s1_point2 : std_logic_vector(2 downto 0);
s1_out2 : std_logic_vector(2 downto 0);
-- stage 2
s2_in1a : std_logic_vector(2 downto 0);
s2_in1b : std_logic_vector(2 downto 0);
s2_op1 : std_logic_vector(2 downto 0);
s2_out1 : std_logic_vector(2 downto 0);
s2_in2a : std_logic_vector(2 downto 0);
s2_in2b : std_logic_vector(2 downto 0);
s2_op2 : std_logic_vector(2 downto 0);
s2_out2 : std_logic_vector(2 downto 0);
-- stage 3
s3_in1a : std_logic_vector(2 downto 0);
s3_in1b : std_logic_vector(2 downto 0);
s3_op1 : std_logic_vector(2 downto 0);
s3_out1 : std_logic_vector(2 downto 0);
s3_in2a : std_logic_vector(2 downto 0);
s3_in2b : std_logic_vector(2 downto 0);
s3_op2 : std_logic_vector(2 downto 0);
s3_out2 : std_logic_vector(2 downto 0);
-- writeback
wb : std_logic_vector(5 downto 0);
wb_memchunk : t_2array(5 downto 0);
wb_bitrev : t_3array(5 downto 0);
wb_assign : t_4array(5 downto 0);
wb_val : t_3array(5 downto 0);
-- ctrl
noop : std_logic;
end record;
constant empty_vliw : t_vliw := (
arg_type => (others => (others => '0')),
arg_memchunk => (others => (others => '0')),
arg_assign => (others => (others => '0')),
arg_val => (others => '0'),
mem_fetch => (others => '0'),
mem_memchunk => (others => (others => '0')),
s1_in1a => (others => '0'),
s1_in1b => (others => '0'),
s1_op1 => (others => '0'),
s1_point1 => (others => '0'),
s1_out1 => (others => '0'),
s1_in2a => (others => '0'),
s1_in2b => (others => '0'),
s1_op2 => (others => '0'),
s1_point2 => (others => '0'),
s1_out2 => (others => '0'),
s2_in1a => (others => '0'),
s2_in1b => (others => '0'),
s2_op1 => (others => '0'),
s2_out1 => (others => '0'),
s2_in2a => (others => '0'),
s2_in2b => (others => '0'),
s2_op2 => (others => '0'),
s2_out2 => (others => '0'),
s3_in1a => (others => '0'),
s3_in1b => (others => '0'),
s3_op1 => (others => '0'),
s3_out1 => (others => '0'),
s3_in2a => (others => '0'),
s3_in2b => (others => '0'),
s3_op2 => (others => '0'),
s3_out2 => (others => '0'),
wb => (others => '0'),
wb_assign => (others => (others => '0')),
wb_bitrev => (others => (others => '0')),
wb_memchunk => (others => (others => '0')),
wb_val => (others => (others => '0')),
noop => '1'
);
constant VLIW_HIGH : natural := 221;
function index2val(signal val: in t_data_array(5 downto 0);
signal index: in std_logic_vector(2 downto 0)) return t_data;
function slv2vliw(slv: in std_logic_vector(VLIW_HIGH downto 0)) return t_vliw;
function vliw2slv(vliw: in t_vliw) return std_logic_vector;
function bitrev(a: in t_data; b: in std_logic_vector(2 downto 0)) return t_data;
end package;
package body procedures is
function index2val(signal val: in t_data_array(5 downto 0);
signal index: in std_logic_vector(2 downto 0)) return t_data is
variable res : t_data;
begin
case to_integer(unsigned(index)) is
when 0 to 5 => res := val(to_integer(unsigned(index)));
when 6 => res := (0 => '1', others => '0');
when others => res := (others => '0');
end case;
return res;
end function;
function slv2vliw(slv: in std_logic_vector(VLIW_HIGH downto 0)) return t_vliw is
variable ret : t_vliw;
begin
ret.arg_type(0) := slv(1 downto 0);
ret.arg_type(1) := slv(3 downto 2);
ret.arg_type(2) := slv(5 downto 4);
ret.arg_type(3) := slv(7 downto 6);
ret.arg_type(4) := slv(9 downto 8);
ret.arg_type(5) := slv(11 downto 10);
ret.arg_memchunk(0) := slv(13 downto 12);
ret.arg_memchunk(1) := slv(15 downto 14);
ret.arg_memchunk(2) := slv(17 downto 16);
ret.arg_memchunk(3) := slv(19 downto 18);
ret.arg_memchunk(4) := slv(21 downto 20);
ret.arg_memchunk(5) := slv(23 downto 22);
ret.arg_val := slv(29 downto 24);
ret.arg_assign(0) := slv(32 downto 30);
ret.arg_assign(1) := slv(35 downto 33);
ret.arg_assign(2) := slv(38 downto 36);
ret.arg_assign(3) := slv(41 downto 39);
ret.arg_assign(4) := slv(44 downto 42);
ret.arg_assign(5) := slv(47 downto 45);
ret.mem_fetch := slv(53 downto 48);
ret.mem_memchunk(0) := slv(55 downto 54);
ret.mem_memchunk(1) := slv(57 downto 56);
ret.mem_memchunk(2) := slv(59 downto 58);
ret.mem_memchunk(3) := slv(61 downto 60);
ret.mem_memchunk(4) := slv(63 downto 62);
ret.mem_memchunk(5) := slv(65 downto 64);
ret.s1_in1a := slv(68 downto 66);
ret.s1_in1b := slv(71 downto 69);
ret.s1_op1 := slv(74 downto 72);
ret.s1_point1 := slv(77 downto 75);
ret.s1_out1 := slv(80 downto 78);
ret.s1_in2a := slv(83 downto 81);
ret.s1_in2b := slv(86 downto 84);
ret.s1_op2 := slv(89 downto 87);
ret.s1_point2 := slv(92 downto 90);
ret.s1_out2 := slv(95 downto 93);
ret.s2_in1a := slv(98 downto 96);
ret.s2_in1b := slv(101 downto 99);
ret.s2_op1 := slv(104 downto 102);
ret.s2_out1 := slv(107 downto 105);
ret.s2_in2a := slv(110 downto 108);
ret.s2_in2b := slv(113 downto 111);
ret.s2_op2 := slv(116 downto 114);
ret.s2_out2 := slv(119 downto 117);
ret.s3_in1a := slv(122 downto 120);
ret.s3_in1b := slv(125 downto 123);
ret.s3_op1 := slv(128 downto 126);
ret.s3_out1 := slv(131 downto 129);
ret.s3_in2a := slv(134 downto 132);
ret.s3_in2b := slv(137 downto 135);
ret.s3_op2 := slv(140 downto 138);
ret.s3_out2 := slv(143 downto 141);
ret.wb := slv(149 downto 144);
ret.wb_memchunk(0) := slv(151 downto 150);
ret.wb_memchunk(1) := slv(153 downto 152);
ret.wb_memchunk(2) := slv(155 downto 154);
ret.wb_memchunk(3) := slv(157 downto 156);
ret.wb_memchunk(4) := slv(159 downto 158);
ret.wb_memchunk(5) := slv(161 downto 160);
ret.wb_bitrev(0) := slv(164 downto 162);
ret.wb_bitrev(1) := slv(167 downto 165);
ret.wb_bitrev(2) := slv(170 downto 168);
ret.wb_bitrev(3) := slv(173 downto 171);
ret.wb_bitrev(4) := slv(176 downto 174);
ret.wb_bitrev(5) := slv(179 downto 177);
ret.wb_assign(0) := slv(183 downto 180);
ret.wb_assign(1) := slv(187 downto 184);
ret.wb_assign(2) := slv(191 downto 188);
ret.wb_assign(3) := slv(195 downto 192);
ret.wb_assign(4) := slv(199 downto 196);
ret.wb_assign(5) := slv(203 downto 200);
ret.wb_val(0) := slv(206 downto 204);
ret.wb_val(1) := slv(209 downto 207);
ret.wb_val(2) := slv(212 downto 210);
ret.wb_val(3) := slv(215 downto 213);
ret.wb_val(4) := slv(218 downto 216);
ret.wb_val(5) := slv(221 downto 219);
ret.noop := '0';
return ret;
end function;
function vliw2slv(vliw: in t_vliw) return std_logic_vector is
variable ret : std_logic_vector(VLIW_HIGH downto 0);
begin
ret(1 downto 0) := vliw.arg_type(0);
ret(3 downto 2) := vliw.arg_type(1);
ret(5 downto 4) := vliw.arg_type(2);
ret(7 downto 6) := vliw.arg_type(3);
ret(9 downto 8) := vliw.arg_type(4);
ret(11 downto 10) := vliw.arg_type(5);
ret(13 downto 12) := vliw.arg_memchunk(0);
ret(15 downto 14) := vliw.arg_memchunk(1);
ret(17 downto 16) := vliw.arg_memchunk(2);
ret(19 downto 18) := vliw.arg_memchunk(3);
ret(21 downto 20) := vliw.arg_memchunk(4);
ret(23 downto 22) := vliw.arg_memchunk(5);
ret(29 downto 24) := vliw.arg_val;
ret(32 downto 30) := vliw.arg_assign(0);
ret(35 downto 33) := vliw.arg_assign(1);
ret(38 downto 36) := vliw.arg_assign(2);
ret(41 downto 39) := vliw.arg_assign(3);
ret(44 downto 42) := vliw.arg_assign(4);
ret(47 downto 45) := vliw.arg_assign(5);
ret(53 downto 48) := vliw.mem_fetch;
ret(55 downto 54) := vliw.mem_memchunk(0);
ret(57 downto 56) := vliw.mem_memchunk(1);
ret(59 downto 58) := vliw.mem_memchunk(2);
ret(61 downto 60) := vliw.mem_memchunk(3);
ret(63 downto 62) := vliw.mem_memchunk(4);
ret(65 downto 64) := vliw.mem_memchunk(5);
ret(68 downto 66) := vliw.s1_in1a;
ret(71 downto 69) := vliw.s1_in1b;
ret(74 downto 72) := vliw.s1_op1;
ret(77 downto 75) := vliw.s1_point1;
ret(80 downto 78) := vliw.s1_out1;
ret(83 downto 81) := vliw.s1_in2a;
ret(86 downto 84) := vliw.s1_in2b;
ret(89 downto 87) := vliw.s1_op2;
ret(92 downto 90) := vliw.s1_point2;
ret(95 downto 93) := vliw.s1_out2;
ret(98 downto 96) := vliw.s2_in1a;
ret(101 downto 99) := vliw.s2_in1b;
ret(104 downto 102) := vliw.s2_op1;
ret(107 downto 105) := vliw.s2_out1;
ret(110 downto 108) := vliw.s2_in2a;
ret(113 downto 111) := vliw.s2_in2b;
ret(116 downto 114) := vliw.s2_op2;
ret(119 downto 117) := vliw.s2_out2;
ret(122 downto 120) := vliw.s3_in1a;
ret(125 downto 123) := vliw.s3_in1b;
ret(128 downto 126) := vliw.s3_op1;
ret(131 downto 129) := vliw.s3_out1;
ret(134 downto 132) := vliw.s3_in2a;
ret(137 downto 135) := vliw.s3_in2b;
ret(140 downto 138) := vliw.s3_op2;
ret(143 downto 141) := vliw.s3_out2;
ret(149 downto 144) := vliw.wb;
ret(151 downto 150) := vliw.wb_memchunk(0);
ret(153 downto 152) := vliw.wb_memchunk(1);
ret(155 downto 154) := vliw.wb_memchunk(2);
ret(157 downto 156) := vliw.wb_memchunk(3);
ret(159 downto 158) := vliw.wb_memchunk(4);
ret(161 downto 160) := vliw.wb_memchunk(5);
ret(164 downto 162) := vliw.wb_bitrev(0);
ret(167 downto 165) := vliw.wb_bitrev(1);
ret(170 downto 168) := vliw.wb_bitrev(2);
ret(173 downto 171) := vliw.wb_bitrev(3);
ret(176 downto 174) := vliw.wb_bitrev(4);
ret(179 downto 177) := vliw.wb_bitrev(5);
ret(183 downto 180) := vliw.wb_assign(0);
ret(187 downto 184) := vliw.wb_assign(1);
ret(191 downto 188) := vliw.wb_assign(2);
ret(195 downto 192) := vliw.wb_assign(3);
ret(199 downto 196) := vliw.wb_assign(4);
ret(203 downto 200) := vliw.wb_assign(5);
ret(206 downto 204) := vliw.wb_val(0);
ret(209 downto 207) := vliw.wb_val(1);
ret(212 downto 210) := vliw.wb_val(2);
ret(215 downto 213) := vliw.wb_val(3);
ret(218 downto 216) := vliw.wb_val(4);
ret(221 downto 219) := vliw.wb_val(5);
return ret;
end function;
function bitrev(a: in t_data; b: in std_logic_vector(2 downto 0)) return t_data is
variable ret : t_data;
begin
case b is
when "000" => ret := a;
when "001" => ret := (0 => a(1), 1 => a(0), others => '0');
when "010" => ret := (0 => a(2), 1 => a(1), 2 => a(0), others => '0');
when "011" => ret := (0 => a(3), 1 => a(2), 2 => a(1), 3 => a(0), others => '0');
when "100" => ret := (0 => a(4), 1 => a(3), 2 => a(2), 3 => a(1), 4 => a(0), others => '0');
when "101" => ret := (0 => a(5), 1 => a(4), 2 => a(3), 3 => a(2), 4 => a(1), 5 => a(0), others => '0');
when "110" => ret := (0 => a(6), 1 => a(5), 2 => a(4), 3 => a(3), 4 => a(2), 5 => a(1), 6 => a(0), others => '0');
when others => ret := (0 => a(7), 1 => a(6), 2 => a(5), 3 => a(4), 4 => a(3), 5 => a(2), 6 => a(1), 7 => a(0));
end case;
return ret;
end function;
end procedures;
| bsd-2-clause | 17fb8a96b2c3d72df6d5082f56acb53f | 0.509084 | 2.992776 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/cmpy_v6_0/hdl/cmpy_3_mult18_lut.vhd | 2 | 47,633 | `protect begin_protected
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| gpl-2.0 | 421d04828a2c23024ba7b82d5f386340 | 0.949321 | 1.825509 | false | false | false | false |
UVVM/UVVM_All | bitvis_vip_rgmii/src/vvc_cmd_pkg.vhd | 1 | 6,923 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
---------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.transaction_pkg.all;
--==========================================================================================
--==========================================================================================
package vvc_cmd_pkg is
alias t_operation is work.transaction_pkg.t_operation;
--==========================================================================================
-- t_vvc_cmd_record
-- - Record type used for communication with the VVC
--==========================================================================================
type t_vvc_cmd_record is record
-- VVC dedicated fields
data_array : t_byte_array(0 to C_VVC_CMD_DATA_MAX_BYTES-1);
data_array_length : natural;
-- Common VVC fields
operation : t_operation;
proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
data_routing : t_data_routing;
cmd_idx : natural;
command_type : t_immediate_or_queued;
msg_id : t_msg_id;
gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed
gen_boolean : boolean; -- Generic boolean
timeout : time;
alert_level : t_alert_level;
delay : time;
quietness : t_quietness;
parent_msg_id_panel : t_msg_id_panel;
end record;
constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := (
data_array => (others => (others => '0')),
data_array_length => 0,
-- Common VVC fields
operation => NO_OPERATION,
proc_call => (others => NUL),
msg => (others => NUL),
data_routing => NA,
cmd_idx => 0,
command_type => NO_COMMAND_TYPE,
msg_id => NO_ID,
gen_integer_array => (others => -1),
gen_boolean => false,
timeout => 0 ns,
alert_level => FAILURE,
delay => 0 ns,
quietness => NON_QUIET,
parent_msg_id_panel => C_UNUSED_MSG_ID_PANEL
);
--==========================================================================================
-- shared_vvc_cmd
-- - Shared variable used for transmitting VVC commands
--==========================================================================================
shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
--==========================================================================================
-- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response :
--
-- - Used for storing the result of a BFM procedure called by the VVC,
-- so that the result can be transported from the VVC to for example a sequencer via
-- fetch_result() as described in uvvm_vvc_framework/Common_VVC_Methods QuickRef.
-- - t_vvc_result includes the return value of the procedure in the BFM. It can also
-- be defined as a record if multiple values shall be transported from the BFM
--==========================================================================================
type t_vvc_result is record
data_array : t_byte_array(0 to C_VVC_CMD_DATA_MAX_BYTES-1);
data_array_length : natural;
end record;
type t_vvc_result_queue_element is record
cmd_idx : natural; -- from UVVM handshake mechanism
result : t_vvc_result;
end record;
type t_vvc_response is record
fetch_is_accepted : boolean;
transaction_result : t_transaction_result;
result : t_vvc_result;
end record;
shared variable shared_vvc_response : t_vvc_response;
--==========================================================================================
-- t_last_received_cmd_idx :
-- - Used to store the last queued cmd in VVC interpreter.
--==========================================================================================
type t_last_received_cmd_idx is array (t_channel range <>,natural range <>) of integer;
--==========================================================================================
-- shared_vvc_last_received_cmd_idx
-- - Shared variable used to get last queued index from VVC to sequencer
--==========================================================================================
shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => (others => -1));
--==========================================================================================
-- Procedures
--==========================================================================================
function to_string(
result : t_vvc_result
) return string;
end package vvc_cmd_pkg;
package body vvc_cmd_pkg is
-- Custom to_string overload needed when result is of a record type
function to_string(
result : t_vvc_result
) return string is
begin
return to_string(result.data_array'length) & " Bytes";
end;
end package body vvc_cmd_pkg; | mit | ffe44a53c7ea3cd5c1267aaa02a4c1e8 | 0.450238 | 5.13195 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab1/VGA_Debug_Unit/ipcore_dir/Instr_Mem.vhd | 1 | 5,745 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file Instr_Mem.vhd when simulating
-- the core, Instr_Mem. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY Instr_Mem IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END Instr_Mem;
ARCHITECTURE Instr_Mem_a OF Instr_Mem IS
-- synthesis translate_off
COMPONENT wrapped_Instr_Mem
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_Instr_Mem USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 5,
c_addrb_width => 5,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "Instr_Mem.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 32,
c_read_depth_b => 32,
c_read_width_a => 16,
c_read_width_b => 16,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 32,
c_write_depth_b => 32,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 16,
c_write_width_b => 16,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_Instr_Mem
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END Instr_Mem_a;
| gpl-3.0 | 3ca0a3cf41691158c9a517369d768567 | 0.51819 | 3.913488 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab1/Poject_Lab01/RegisterBank2/RegisterBank_tb.vhd | 1 | 3,993 | --------------------------------------------------------------------------------
-- Company: UMASS DARTMOUTH
-- Engineer: Christopher Parks
--
-- Create Date: 13:20:29 03/25/2016
-- Design Name:
-- Module Name: Z:/Xilinx/RegisterBank2/RegisterBank_tb.vhd
-- Project Name: RegisterBank
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: RegisterBank
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY RegisterBank_tb IS
END RegisterBank_tb;
ARCHITECTURE behavior OF RegisterBank_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RegisterBank
PORT(
RAddr : IN std_logic_vector(3 downto 0);
RBddr : IN std_logic_vector(3 downto 0);
RWddr : IN std_logic_vector(3 downto 0);
DATAIN : IN std_logic_vector(15 downto 0);
clk : IN std_logic;
R : IN std_logic;
W : IN std_logic;
RAout : OUT std_logic_vector(15 downto 0);
RBout : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal RAddr : std_logic_vector(3 downto 0) := (others => '0');
signal RBddr : std_logic_vector(3 downto 0) := (others => '0');
signal RWddr : std_logic_vector(3 downto 0) := (others => '0');
signal DATAIN : std_logic_vector(15 downto 0) := (others => '0');
signal clk : std_logic := '0';
signal R : std_logic := '0';
signal W : std_logic := '0';
--Outputs
signal RAout : std_logic_vector(15 downto 0);
signal RBout : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RegisterBank PORT MAP (
RAddr => RAddr,
RBddr => RBddr,
RWddr => RWddr,
DATAIN => DATAIN,
clk => clk,
R => R,
W => W,
RAout => RAout,
RBout => RBout
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
W <= '1'; -- Enable write
wait for clk_period; -- Write data in
for i in 0 to 15 loop
RWddr <= std_logic_vector(to_unsigned(i, RWddr'length));
wait for clk_period;
DATAIN <= std_logic_vector(to_unsigned(i,DATAIN'length));
wait for clk_period;
end loop;
W <= '0';
R <= '1'; -- Read in all written data
wait for clk_period;
for i in 0 to 14 loop
RAddr <= std_logic_vector(to_unsigned(i,RAddr'length));
RBddr <= std_logic_vector(to_unsigned(i+1,RBddr'length));
wait for clk_period;
end loop;
-- W <= '1'; -- Read AND Write
-- wait for clk_period;
--
-- for i in 0 to 15 loop
-- RAddr <= std_logic_vector(to_unsigned(i,RAddr'length));
-- RBddr <= std_logic_vector(to_unsigned(i-1,RBddr'length));
-- RWddr <= std_logic_vector(to_unsigned(i+1));
-- wait for clk_period;
-- end loop;
wait;
end process;
END;
| gpl-3.0 | b8a463901bb32580a591dd1b90120767 | 0.57125 | 3.521164 | false | false | false | false |
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`protect end_protected
| gpl-2.0 | 3cfc3dcdfcbd3efbbd772a8c78ea0f8e | 0.920115 | 1.892615 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/dds/dds_compiler_v6_0/hdl/sin_cos.vhd | 6 | 98,404 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 71104)
`protect data_block
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`protect end_protected
| gpl-2.0 | a4d2ee32299ead74132637769604f21f | 0.952319 | 1.814233 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/shared/lead_zero_encode.vhd | 3 | 31,657 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 21696)
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`protect end_protected
| gpl-2.0 | 6e439ca70819b48eec7ca7dcf4f973eb | 0.945383 | 1.833913 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/mult_fft/synth/mult_fft.vhd | 2 | 5,611 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mult_gen:12.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mult_gen_v12_0;
USE mult_gen_v12_0.mult_gen_v12_0;
ENTITY mult_fft IS
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(27 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(27 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(55 DOWNTO 0)
);
END mult_fft;
ARCHITECTURE mult_fft_arch OF mult_fft IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mult_fft_arch: ARCHITECTURE IS "yes";
COMPONENT mult_gen_v12_0 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_MODEL_TYPE : INTEGER;
C_OPTIMIZE_GOAL : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_CE : INTEGER;
C_HAS_SCLR : INTEGER;
C_LATENCY : INTEGER;
C_A_WIDTH : INTEGER;
C_A_TYPE : INTEGER;
C_B_WIDTH : INTEGER;
C_B_TYPE : INTEGER;
C_OUT_HIGH : INTEGER;
C_OUT_LOW : INTEGER;
C_MULT_TYPE : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_CCM_IMP : INTEGER;
C_B_VALUE : STRING;
C_HAS_ZERO_DETECT : INTEGER;
C_ROUND_OUTPUT : INTEGER;
C_ROUND_PT : INTEGER
);
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(27 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(27 DOWNTO 0);
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
P : OUT STD_LOGIC_VECTOR(55 DOWNTO 0)
);
END COMPONENT mult_gen_v12_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF mult_fft_arch: ARCHITECTURE IS "mult_gen_v12_0,Vivado 2013.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF mult_fft_arch : ARCHITECTURE IS "mult_fft,mult_gen_v12_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF mult_fft_arch: ARCHITECTURE IS "mult_fft,mult_gen_v12_0,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=zynq,C_HAS_CE=0,C_HAS_SCLR=0,C_LATENCY=5,C_A_WIDTH=28,C_A_TYPE=0,C_B_WIDTH=28,C_B_TYPE=0,C_OUT_HIGH=55,C_OUT_LOW=0,C_MULT_TYPE=0,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA";
BEGIN
U0 : mult_gen_v12_0
GENERIC MAP (
C_VERBOSITY => 0,
C_MODEL_TYPE => 0,
C_OPTIMIZE_GOAL => 1,
C_XDEVICEFAMILY => "zynq",
C_HAS_CE => 0,
C_HAS_SCLR => 0,
C_LATENCY => 5,
C_A_WIDTH => 28,
C_A_TYPE => 0,
C_B_WIDTH => 28,
C_B_TYPE => 0,
C_OUT_HIGH => 55,
C_OUT_LOW => 0,
C_MULT_TYPE => 0,
C_CE_OVERRIDES_SCLR => 0,
C_CCM_IMP => 0,
C_B_VALUE => "10000001",
C_HAS_ZERO_DETECT => 0,
C_ROUND_OUTPUT => 0,
C_ROUND_PT => 0
)
PORT MAP (
CLK => CLK,
A => A,
B => B,
CE => '1',
SCLR => '0',
P => P
);
END mult_fft_arch;
| gpl-2.0 | b1040cfb21d9e4c77ce86429f5cd196b | 0.677776 | 3.392382 | false | false | false | false |
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dphc7ne6hCo5+r+58GFA22johyxtnyar01jCmelR1wGffB/AtAMtbwOaIsm/6D6gUrF/jpj6LJ8p
iY8AHL5KjPAlDDNgJ4jPb1w6CJKIPFdzgdc3Z9LnF3P/cHcbPVkR3ZaNwB1bKYTVLoII6n2z8YH+
JTd+EsAidX39PhYADl/pwQwxv6c+biPEPO1QsZXFbd4i51lm2Pfyt8BTMBWqyNn8pJ5C/0Rdl0pl
EUghhxNN2imgynIfmRCnmXM7OI1Lxkfy5ltzRJE9bQrEzH3vwOlSZgaduu7Cao1xU4vMJIAobu3d
V0JjCSWt4o8OAt5CrJv0JpRI3GBNw2RDdjAV44q6BSTOl7lNpdzn3QYyw+RQ728SwBkHenEUnJdx
`protect end_protected
| gpl-2.0 | c34d7099ab076786731145104de7ae14 | 0.951017 | 1.824759 | false | false | false | false |
r2t2sdr/r2t2 | fpga/bd/hdl/ps_wrapper.vhd | 1 | 15,146 | --Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2017.1 (lin64) Build 1846317 Fri Apr 14 18:54:47 MDT 2017
--Date : Mon May 15 23:35:17 2017
--Host : beta running 64-bit Arch Linux
--Command : generate_target ps_wrapper.bd
--Design : ps_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ps_wrapper is
port (
DB : out STD_LOGIC_VECTOR ( 13 downto 0 );
DCLKIO : in STD_LOGIC;
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
I2S_bclk : out STD_LOGIC_VECTOR ( 0 to 0 );
I2S_lrclk : out STD_LOGIC_VECTOR ( 0 to 0 );
I2S_sdata_in : in STD_LOGIC_VECTOR ( 0 to 0 );
I2S_sdata_out : out STD_LOGIC_VECTOR ( 0 to 0 );
LVDS_ADC_A_D0_N : in STD_LOGIC;
LVDS_ADC_A_D0_P : in STD_LOGIC;
LVDS_ADC_A_D1_N : in STD_LOGIC;
LVDS_ADC_A_D1_P : in STD_LOGIC;
LVDS_ADC_B_D0_N : in STD_LOGIC;
LVDS_ADC_B_D0_P : in STD_LOGIC;
LVDS_ADC_B_D1_N : in STD_LOGIC;
LVDS_ADC_B_D1_P : in STD_LOGIC;
LVDS_ADC_DCO_N : in STD_LOGIC;
LVDS_ADC_DCO_P : in STD_LOGIC;
LVDS_ADC_FCO_N : in STD_LOGIC;
LVDS_ADC_FCO_P : in STD_LOGIC;
PHY_LED0 : out STD_LOGIC;
PHY_LED1 : out STD_LOGIC;
PHY_LED2 : out STD_LOGIC;
PL_PIN_K16 : in STD_LOGIC;
PL_PIN_K19 : in STD_LOGIC;
PL_PIN_K20 : out STD_LOGIC;
PL_PIN_L16 : out STD_LOGIC;
PL_PIN_M15 : in STD_LOGIC;
PL_PIN_N15 : in STD_LOGIC;
PL_PIN_N22 : out STD_LOGIC;
PL_PIN_P16 : in STD_LOGIC;
PL_PIN_P22 : in STD_LOGIC;
clk_12mhz : out STD_LOGIC_VECTOR ( 0 to 0 );
clk_idelayctrl : out STD_LOGIC;
gpio_tri_io : inout STD_LOGIC_VECTOR ( 11 downto 0 );
hdmi_out_clk : out STD_LOGIC;
hdmi_out_data : out STD_LOGIC_VECTOR ( 11 downto 0 );
hdmi_out_de : out STD_LOGIC;
hdmi_out_hsync : out STD_LOGIC;
hdmi_out_vsync : out STD_LOGIC;
i2s_mdk : out STD_LOGIC;
iic_0_scl_io : inout STD_LOGIC;
iic_0_sda_io : inout STD_LOGIC;
pl_clk : in STD_LOGIC;
sys_clk : out STD_LOGIC
);
end ps_wrapper;
architecture STRUCTURE of ps_wrapper is
component ps is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
IIC_0_sda_i : in STD_LOGIC;
IIC_0_sda_o : out STD_LOGIC;
IIC_0_sda_t : out STD_LOGIC;
IIC_0_scl_i : in STD_LOGIC;
IIC_0_scl_o : out STD_LOGIC;
IIC_0_scl_t : out STD_LOGIC;
GPIO_tri_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
GPIO_tri_o : out STD_LOGIC_VECTOR ( 11 downto 0 );
GPIO_tri_t : out STD_LOGIC_VECTOR ( 11 downto 0 );
I2S_bclk : out STD_LOGIC_VECTOR ( 0 to 0 );
I2S_lrclk : out STD_LOGIC_VECTOR ( 0 to 0 );
I2S_sdata_out : out STD_LOGIC_VECTOR ( 0 to 0 );
I2S_sdata_in : in STD_LOGIC_VECTOR ( 0 to 0 );
hdmi_out_de : out STD_LOGIC;
hdmi_out_clk : out STD_LOGIC;
hdmi_out_vsync : out STD_LOGIC;
hdmi_out_data : out STD_LOGIC_VECTOR ( 11 downto 0 );
hdmi_out_hsync : out STD_LOGIC;
sys_clk : out STD_LOGIC;
PL_PIN_K16 : in STD_LOGIC;
PL_PIN_K19 : in STD_LOGIC;
PL_PIN_M15 : in STD_LOGIC;
PL_PIN_N15 : in STD_LOGIC;
PL_PIN_P16 : in STD_LOGIC;
PL_PIN_P22 : in STD_LOGIC;
PL_PIN_L16 : out STD_LOGIC;
PL_PIN_K20 : out STD_LOGIC;
PL_PIN_N22 : out STD_LOGIC;
PHY_LED0 : out STD_LOGIC;
PHY_LED1 : out STD_LOGIC;
PHY_LED2 : out STD_LOGIC;
clk_idelayctrl : out STD_LOGIC;
pl_clk : in STD_LOGIC;
LVDS_ADC_A_D0_N : in STD_LOGIC;
LVDS_ADC_A_D0_P : in STD_LOGIC;
LVDS_ADC_A_D1_N : in STD_LOGIC;
LVDS_ADC_A_D1_P : in STD_LOGIC;
LVDS_ADC_B_D0_P : in STD_LOGIC;
LVDS_ADC_B_D0_N : in STD_LOGIC;
LVDS_ADC_B_D1_N : in STD_LOGIC;
LVDS_ADC_B_D1_P : in STD_LOGIC;
LVDS_ADC_DCO_N : in STD_LOGIC;
LVDS_ADC_DCO_P : in STD_LOGIC;
LVDS_ADC_FCO_N : in STD_LOGIC;
LVDS_ADC_FCO_P : in STD_LOGIC;
DCLKIO : in STD_LOGIC;
DB : out STD_LOGIC_VECTOR ( 13 downto 0 );
i2s_mdk : out STD_LOGIC;
clk_12mhz : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component ps;
component IOBUF is
port (
I : in STD_LOGIC;
O : out STD_LOGIC;
T : in STD_LOGIC;
IO : inout STD_LOGIC
);
end component IOBUF;
signal gpio_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal gpio_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal gpio_tri_i_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal gpio_tri_i_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal gpio_tri_i_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal gpio_tri_i_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal gpio_tri_i_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal gpio_tri_i_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal gpio_tri_i_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal gpio_tri_i_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal gpio_tri_i_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal gpio_tri_i_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal gpio_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal gpio_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal gpio_tri_io_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal gpio_tri_io_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal gpio_tri_io_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal gpio_tri_io_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal gpio_tri_io_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal gpio_tri_io_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal gpio_tri_io_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal gpio_tri_io_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal gpio_tri_io_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal gpio_tri_io_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal gpio_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal gpio_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal gpio_tri_o_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal gpio_tri_o_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal gpio_tri_o_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal gpio_tri_o_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal gpio_tri_o_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal gpio_tri_o_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal gpio_tri_o_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal gpio_tri_o_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal gpio_tri_o_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal gpio_tri_o_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal gpio_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal gpio_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal gpio_tri_t_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal gpio_tri_t_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal gpio_tri_t_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal gpio_tri_t_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal gpio_tri_t_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal gpio_tri_t_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal gpio_tri_t_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal gpio_tri_t_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal gpio_tri_t_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal gpio_tri_t_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal iic_0_scl_i : STD_LOGIC;
signal iic_0_scl_o : STD_LOGIC;
signal iic_0_scl_t : STD_LOGIC;
signal iic_0_sda_i : STD_LOGIC;
signal iic_0_sda_o : STD_LOGIC;
signal iic_0_sda_t : STD_LOGIC;
begin
gpio_tri_iobuf_0: component IOBUF
port map (
I => gpio_tri_o_0(0),
IO => gpio_tri_io(0),
O => gpio_tri_i_0(0),
T => gpio_tri_t_0(0)
);
gpio_tri_iobuf_1: component IOBUF
port map (
I => gpio_tri_o_1(1),
IO => gpio_tri_io(1),
O => gpio_tri_i_1(1),
T => gpio_tri_t_1(1)
);
gpio_tri_iobuf_10: component IOBUF
port map (
I => gpio_tri_o_10(10),
IO => gpio_tri_io(10),
O => gpio_tri_i_10(10),
T => gpio_tri_t_10(10)
);
gpio_tri_iobuf_11: component IOBUF
port map (
I => gpio_tri_o_11(11),
IO => gpio_tri_io(11),
O => gpio_tri_i_11(11),
T => gpio_tri_t_11(11)
);
gpio_tri_iobuf_2: component IOBUF
port map (
I => gpio_tri_o_2(2),
IO => gpio_tri_io(2),
O => gpio_tri_i_2(2),
T => gpio_tri_t_2(2)
);
gpio_tri_iobuf_3: component IOBUF
port map (
I => gpio_tri_o_3(3),
IO => gpio_tri_io(3),
O => gpio_tri_i_3(3),
T => gpio_tri_t_3(3)
);
gpio_tri_iobuf_4: component IOBUF
port map (
I => gpio_tri_o_4(4),
IO => gpio_tri_io(4),
O => gpio_tri_i_4(4),
T => gpio_tri_t_4(4)
);
gpio_tri_iobuf_5: component IOBUF
port map (
I => gpio_tri_o_5(5),
IO => gpio_tri_io(5),
O => gpio_tri_i_5(5),
T => gpio_tri_t_5(5)
);
gpio_tri_iobuf_6: component IOBUF
port map (
I => gpio_tri_o_6(6),
IO => gpio_tri_io(6),
O => gpio_tri_i_6(6),
T => gpio_tri_t_6(6)
);
gpio_tri_iobuf_7: component IOBUF
port map (
I => gpio_tri_o_7(7),
IO => gpio_tri_io(7),
O => gpio_tri_i_7(7),
T => gpio_tri_t_7(7)
);
gpio_tri_iobuf_8: component IOBUF
port map (
I => gpio_tri_o_8(8),
IO => gpio_tri_io(8),
O => gpio_tri_i_8(8),
T => gpio_tri_t_8(8)
);
gpio_tri_iobuf_9: component IOBUF
port map (
I => gpio_tri_o_9(9),
IO => gpio_tri_io(9),
O => gpio_tri_i_9(9),
T => gpio_tri_t_9(9)
);
iic_0_scl_iobuf: component IOBUF
port map (
I => iic_0_scl_o,
IO => iic_0_scl_io,
O => iic_0_scl_i,
T => iic_0_scl_t
);
iic_0_sda_iobuf: component IOBUF
port map (
I => iic_0_sda_o,
IO => iic_0_sda_io,
O => iic_0_sda_i,
T => iic_0_sda_t
);
ps_i: component ps
port map (
DB(13 downto 0) => DB(13 downto 0),
DCLKIO => DCLKIO,
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
GPIO_tri_i(11) => gpio_tri_i_11(11),
GPIO_tri_i(10) => gpio_tri_i_10(10),
GPIO_tri_i(9) => gpio_tri_i_9(9),
GPIO_tri_i(8) => gpio_tri_i_8(8),
GPIO_tri_i(7) => gpio_tri_i_7(7),
GPIO_tri_i(6) => gpio_tri_i_6(6),
GPIO_tri_i(5) => gpio_tri_i_5(5),
GPIO_tri_i(4) => gpio_tri_i_4(4),
GPIO_tri_i(3) => gpio_tri_i_3(3),
GPIO_tri_i(2) => gpio_tri_i_2(2),
GPIO_tri_i(1) => gpio_tri_i_1(1),
GPIO_tri_i(0) => gpio_tri_i_0(0),
GPIO_tri_o(11) => gpio_tri_o_11(11),
GPIO_tri_o(10) => gpio_tri_o_10(10),
GPIO_tri_o(9) => gpio_tri_o_9(9),
GPIO_tri_o(8) => gpio_tri_o_8(8),
GPIO_tri_o(7) => gpio_tri_o_7(7),
GPIO_tri_o(6) => gpio_tri_o_6(6),
GPIO_tri_o(5) => gpio_tri_o_5(5),
GPIO_tri_o(4) => gpio_tri_o_4(4),
GPIO_tri_o(3) => gpio_tri_o_3(3),
GPIO_tri_o(2) => gpio_tri_o_2(2),
GPIO_tri_o(1) => gpio_tri_o_1(1),
GPIO_tri_o(0) => gpio_tri_o_0(0),
GPIO_tri_t(11) => gpio_tri_t_11(11),
GPIO_tri_t(10) => gpio_tri_t_10(10),
GPIO_tri_t(9) => gpio_tri_t_9(9),
GPIO_tri_t(8) => gpio_tri_t_8(8),
GPIO_tri_t(7) => gpio_tri_t_7(7),
GPIO_tri_t(6) => gpio_tri_t_6(6),
GPIO_tri_t(5) => gpio_tri_t_5(5),
GPIO_tri_t(4) => gpio_tri_t_4(4),
GPIO_tri_t(3) => gpio_tri_t_3(3),
GPIO_tri_t(2) => gpio_tri_t_2(2),
GPIO_tri_t(1) => gpio_tri_t_1(1),
GPIO_tri_t(0) => gpio_tri_t_0(0),
I2S_bclk(0) => I2S_bclk(0),
I2S_lrclk(0) => I2S_lrclk(0),
I2S_sdata_in(0) => I2S_sdata_in(0),
I2S_sdata_out(0) => I2S_sdata_out(0),
IIC_0_scl_i => iic_0_scl_i,
IIC_0_scl_o => iic_0_scl_o,
IIC_0_scl_t => iic_0_scl_t,
IIC_0_sda_i => iic_0_sda_i,
IIC_0_sda_o => iic_0_sda_o,
IIC_0_sda_t => iic_0_sda_t,
LVDS_ADC_A_D0_N => LVDS_ADC_A_D0_N,
LVDS_ADC_A_D0_P => LVDS_ADC_A_D0_P,
LVDS_ADC_A_D1_N => LVDS_ADC_A_D1_N,
LVDS_ADC_A_D1_P => LVDS_ADC_A_D1_P,
LVDS_ADC_B_D0_N => LVDS_ADC_B_D0_N,
LVDS_ADC_B_D0_P => LVDS_ADC_B_D0_P,
LVDS_ADC_B_D1_N => LVDS_ADC_B_D1_N,
LVDS_ADC_B_D1_P => LVDS_ADC_B_D1_P,
LVDS_ADC_DCO_N => LVDS_ADC_DCO_N,
LVDS_ADC_DCO_P => LVDS_ADC_DCO_P,
LVDS_ADC_FCO_N => LVDS_ADC_FCO_N,
LVDS_ADC_FCO_P => LVDS_ADC_FCO_P,
PHY_LED0 => PHY_LED0,
PHY_LED1 => PHY_LED1,
PHY_LED2 => PHY_LED2,
PL_PIN_K16 => PL_PIN_K16,
PL_PIN_K19 => PL_PIN_K19,
PL_PIN_K20 => PL_PIN_K20,
PL_PIN_L16 => PL_PIN_L16,
PL_PIN_M15 => PL_PIN_M15,
PL_PIN_N15 => PL_PIN_N15,
PL_PIN_N22 => PL_PIN_N22,
PL_PIN_P16 => PL_PIN_P16,
PL_PIN_P22 => PL_PIN_P22,
clk_12mhz(0) => clk_12mhz(0),
clk_idelayctrl => clk_idelayctrl,
hdmi_out_clk => hdmi_out_clk,
hdmi_out_data(11 downto 0) => hdmi_out_data(11 downto 0),
hdmi_out_de => hdmi_out_de,
hdmi_out_hsync => hdmi_out_hsync,
hdmi_out_vsync => hdmi_out_vsync,
i2s_mdk => i2s_mdk,
pl_clk => pl_clk,
sys_clk => sys_clk
);
end STRUCTURE;
| gpl-3.0 | 42996a4f7e77a66ba81e271b53e7f693 | 0.561072 | 2.565814 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xbip_dsp48_wrapper_v3_0/hdl/xbip_dsp48_wrapper_v3_0.vhd | 7 | 18,733 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12128)
`protect data_block
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`protect end_protected
| gpl-2.0 | c49cd3ea3d959d2614470142619adaca | 0.941814 | 1.85917 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/mult_gen_v12_0/hdl/cc_compare.vhd | 12 | 10,907 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6336)
`protect data_block
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`protect end_protected
| gpl-2.0 | 46c5c8aeddd946e1e48a808f8cd03768 | 0.927753 | 1.907819 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/fir_lp_54kHz/fir_compiler_v7_1/hdl/ext_mult.vhd | 8 | 22,040 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 14576)
`protect data_block
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`protect end_protected
| gpl-2.0 | 504c44b0143867a9e9ada4f97431b91b | 0.941425 | 1.853814 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/cmpy_v6_0/hdl/cmpy_v6_0_comp.vhd | 2 | 12,982 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7872)
`protect data_block
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`protect end_protected
| gpl-2.0 | 411666532b269383a12b9bac2eea27c4 | 0.932599 | 1.881995 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab2/ProgramCounter/ProgramCounter/ipcore_dir/Instr_Mem/example_design/Instr_Mem_prod.vhd | 5 | 10,082 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
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--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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--
--------------------------------------------------------------------------------
--
-- Filename: Instr_Mem_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3e
-- C_XDEVICEFAMILY : spartan3e
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : Instr_Mem.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : READ_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 32
-- C_READ_DEPTH_A : 32
-- C_ADDRA_WIDTH : 5
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 32
-- C_READ_DEPTH_B : 32
-- C_ADDRB_WIDTH : 5
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY Instr_Mem_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END Instr_Mem_prod;
ARCHITECTURE xilinx OF Instr_Mem_prod IS
COMPONENT Instr_Mem_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : Instr_Mem_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| gpl-3.0 | e3ad5cf5b2b6e95fc0949ecefd671494 | 0.492958 | 3.826186 | false | false | false | false |
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`protect end_protected
| gpl-2.0 | d7c324c26950353c308c82da36a62e12 | 0.955169 | 1.80701 | false | false | false | false |
fafaldo/ethernet | ethernet4b/MAC_source.vhd | 1 | 1,636 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MAC_source is
port( data_in : in std_logic_vector(7 downto 0);
enable : in std_logic;
reset : in std_logic;
clk : in std_logic;
source_MAC : out std_logic_vector(47 downto 0);
test : out std_logic_vector(7 downto 0)
);
end MAC_source;
architecture Behavioral of MAC_source is
signal address_counter : std_logic_vector(10 downto 0) := (others=>'0');
signal temp : std_logic_vector(47 downto 0);
begin
source_MAC <= temp;
test <= temp(47 downto 40);
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
address_counter <= (others=>'0');
elsif enable = '1' then
address_counter <= address_counter+1;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
temp <= (others=>'0');
elsif address_counter = 7 then
temp(47 downto 40) <= data_in;
elsif address_counter = 8 then
temp(39 downto 32) <= data_in;
elsif address_counter = 9 then
temp(31 downto 24) <= data_in;
elsif address_counter = 10 then
temp(23 downto 16) <= data_in;
elsif address_counter = 11 then
temp(15 downto 8) <= data_in;
elsif address_counter = 12 then
temp(7 downto 0) <= data_in;
end if;
end if;
end process;
end Behavioral; | apache-2.0 | 6c6a435936dd7f0109fea740b5b20dde | 0.672372 | 3.176699 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/c_mux_bit_v12_0/hdl/c_mux_bit_v12_0_comp.vhd | 3 | 10,258 | `protect begin_protected
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`protect end_protected
| gpl-2.0 | 62cdd8f0010cdc505362b666a56a744b | 0.926789 | 1.911666 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/multi_fft/xbip_bram18k_v3_0/hdl/xbip_bram18k_rtl.vhd | 12 | 22,883 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15200)
`protect data_block
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`protect end_protected
| gpl-2.0 | 9a7d1db16057be8dbb1aa10a7e53c98a | 0.940786 | 1.842432 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xfft_v9_0/hdl/cmpy.vhd | 3 | 11,750 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6960)
`protect data_block
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`protect end_protected
| gpl-2.0 | 70b0033147824cd357ebb7bdcc0d70c3 | 0.927915 | 1.885733 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xfft_v9_0/hdl/xfft_v9_0_b.vhd | 3 | 58,761 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 41760)
`protect data_block
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| gpl-2.0 | fc8da56a95e9fd002cb70b0b5690cead | 0.95143 | 1.81917 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab2/NewCombined/ipcore_dir/instruction_memory/example_design/instruction_memory_exdes.vhd | 5 | 4,671 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: instruction_memory_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY instruction_memory_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END instruction_memory_exdes;
ARCHITECTURE xilinx OF instruction_memory_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT instruction_memory IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : instruction_memory
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| gpl-3.0 | 75f854c08da7c21843e0bb8273890244 | 0.572468 | 4.790769 | false | false | false | false |
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| gpl-2.0 | 7dbb8eea5743329b7fd018dc7b04dc53 | 0.930128 | 1.890283 | false | false | false | false |
UVVM/UVVM_All | bitvis_vip_ethernet/src/vvc_cmd_pkg.vhd | 1 | 7,300 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
---------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.support_pkg.all;
use work.transaction_pkg.all;
--==========================================================================================
--==========================================================================================
package vvc_cmd_pkg is
alias t_operation is work.transaction_pkg.t_operation;
--==========================================================================================
-- t_vvc_cmd_record
-- - Record type used for communication with the VVC
--==========================================================================================
type t_vvc_cmd_record is record
-- VVC dedicated fields
mac_destination : unsigned(47 downto 0);
mac_source : unsigned(47 downto 0);
payload_length : natural range 0 to C_MAX_PAYLOAD_LENGTH;
payload : t_byte_array(0 to C_MAX_PAYLOAD_LENGTH-1);
-- Common VVC fields
operation : t_operation;
proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
data_routing : t_data_routing;
cmd_idx : natural;
command_type : t_immediate_or_queued;
msg_id : t_msg_id;
gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed
gen_boolean : boolean; -- Generic boolean
timeout : time;
alert_level : t_alert_level;
delay : time;
quietness : t_quietness;
parent_msg_id_panel : t_msg_id_panel;
end record;
constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := (
-- VVC dedicated fields
mac_destination => (others => '0'),
mac_source => (others => '0'),
payload_length => 0,
payload => (others => (others => '0')),
-- Common VVC fields
operation => NO_OPERATION,
proc_call => (others => NUL),
msg => (others => NUL),
data_routing => NA,
cmd_idx => 0,
command_type => NO_COMMAND_TYPE,
msg_id => NO_ID,
gen_integer_array => (others => -1),
gen_boolean => false,
timeout => 0 ns,
alert_level => FAILURE,
delay => 0 ns,
quietness => NON_QUIET,
parent_msg_id_panel => C_UNUSED_MSG_ID_PANEL
);
--==========================================================================================
-- shared_vvc_cmd
-- - Shared variable used for transmitting VVC commands
--==========================================================================================
shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
--==========================================================================================
-- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response :
--
-- - Used for storing the result of a BFM procedure called by the VVC,
-- so that the result can be transported from the VVC to for example a sequencer via
-- fetch_result() as described in uvvm_vvc_framework/Common_VVC_Methods QuickRef.
-- - t_vvc_result includes the return value of the procedure in the BFM. It can also
-- be defined as a record if multiple values shall be transported from the BFM
--==========================================================================================
type t_vvc_result is record
ethernet_frame : t_ethernet_frame;
ethernet_frame_status : t_ethernet_frame_status;
end record t_vvc_result;
type t_vvc_result_queue_element is record
cmd_idx : natural; -- from UVVM handshake mechanism
result : t_vvc_result;
end record;
type t_vvc_response is record
fetch_is_accepted : boolean;
transaction_result : t_transaction_result;
result : t_vvc_result;
end record;
shared variable shared_vvc_response : t_vvc_response;
--==========================================================================================
-- t_last_received_cmd_idx :
-- - Used to store the last queued cmd in VVC interpreter.
--==========================================================================================
type t_last_received_cmd_idx is array (t_channel range <>,natural range <>) of integer;
--==========================================================================================
-- shared_vvc_last_received_cmd_idx
-- - Shared variable used to get last queued index from VVC to sequencer
--==========================================================================================
shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => (others => -1));
--==========================================================================================
-- Procedures
--==========================================================================================
function to_string(
result : t_vvc_result
) return string;
end package vvc_cmd_pkg;
package body vvc_cmd_pkg is
-- Custom to_string overload needed when result is of a record type
function to_string(
result : t_vvc_result
) return string is
begin
return to_string(result.ethernet_frame, HEADER) &
LF & " FCS error: " & to_string(result.ethernet_frame_status.fcs_error);
end;
end package body vvc_cmd_pkg; | mit | 95bfa1d2b3028470cde1fe5bdde3b3e2 | 0.455616 | 5.112045 | false | false | false | false |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/xbip_bram18k_v3_0/902b235a/hdl/xbip_bram18k_v3_0_vh_rfs.vhd | 2 | 96,005 | `protect begin_protected
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| mit | a54e6b1b724633709e2d1dd40ac13a97 | 0.952711 | 1.816316 | false | false | false | false |
keith-epidev/VHDL-lib | src/components/n_register/n_register.vhd | 1 | 619 | library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.VHDL_lib.all;
entity n_register is
generic (
width:integer := 8
);
port (
input : in std_logic_vector(width-1 downto 0);
output : out std_logic_vector(width-1 downto 0);
clk : in std_logic;
rst : in std_logic
);
end n_register;
architecture arch of n_register is
signal data : std_logic_vector(width-1 downto 0);
begin
output <= data;
latch: process (clk,input,rst)
begin
if (rst = '1') then
data <= (others=>'0');
else if (clk'event and clk = '1') then
data <= input;
end if;
end if;
end process ;
end arch;
| gpl-2.0 | 28156a5027ff6e7aded77db1e05c99bb | 0.662359 | 2.714912 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_7/part_3/ip/dds/demo_tb/tb_dds.vhd | 1 | 9,630 | --------------------------------------------------------------------------------
-- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Description:
-- This is an example testbench for the DDS Compiler IP core.
-- The testbench has been generated by Vivado to accompany the IP core
-- instance you have generated.
--
-- This testbench is for demonstration purposes only. See note below for
-- instructions on how to use it with your core.
--
-- See the DDS Compiler product guide for further information
-- about this core.
--
--------------------------------------------------------------------------------
-- Using this testbench
--
-- This testbench instantiates your generated DDS Compiler core
-- instance named "dds".
--
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
-- documentation for details.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity tb_dds is
end tb_dds;
architecture tb of tb_dds is
-----------------------------------------------------------------------
-- Timing constants
-----------------------------------------------------------------------
constant CLOCK_PERIOD : time := 100 ns;
constant T_HOLD : time := 10 ns;
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
-----------------------------------------------------------------------
-- DUT input signals
-----------------------------------------------------------------------
-- General inputs
signal aclk : std_logic := '0'; -- the master clock
-- Phase slave channel signals
signal s_axis_phase_tvalid : std_logic := '0'; -- payload is valid
signal s_axis_phase_tdata : std_logic_vector(23 downto 0) := (others => '0'); -- data payload
-- Data master channel signals
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal m_axis_data_tdata : std_logic_vector(31 downto 0) := (others => '0'); -- data payload
-- Phase master channel signals
signal m_axis_phase_tvalid : std_logic := '0'; -- payload is valid
signal m_axis_phase_tdata : std_logic_vector(23 downto 0) := (others => '0'); -- data payload
-----------------------------------------------------------------------
-- Aliases for AXI channel TDATA and TUSER fields
-- These are a convenience for viewing data in a simulator waveform viewer.
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
-- to prevent the simulator optimizing away these signals.
-----------------------------------------------------------------------
-- Phase slave channel alias signals
signal s_axis_phase_tdata_inc : std_logic_vector(21 downto 0) := (others => '0');
-- Data master channel alias signals
signal m_axis_data_tdata_cosine : std_logic_vector(15 downto 0) := (others => '0');
signal m_axis_data_tdata_sine : std_logic_vector(15 downto 0) := (others => '0');
-- Phase master channel alias signals
signal m_axis_phase_tdata_phase : std_logic_vector(21 downto 0) := (others => '0');
signal end_of_simulation : boolean := false;
begin
-----------------------------------------------------------------------
-- Instantiate the DUT
-----------------------------------------------------------------------
dut : entity work.dds
port map (
aclk => aclk
,s_axis_phase_tvalid => s_axis_phase_tvalid
,s_axis_phase_tdata => s_axis_phase_tdata
,m_axis_data_tvalid => m_axis_data_tvalid
,m_axis_data_tdata => m_axis_data_tdata
,m_axis_phase_tvalid => m_axis_phase_tvalid
,m_axis_phase_tdata => m_axis_phase_tdata
);
-----------------------------------------------------------------------
-- Generate clock
-----------------------------------------------------------------------
clock_gen : process
begin
aclk <= '0';
if (end_of_simulation) then
wait;
else
wait for CLOCK_PERIOD;
loop
aclk <= '0';
wait for CLOCK_PERIOD/2;
aclk <= '1';
wait for CLOCK_PERIOD/2;
end loop;
end if;
end process clock_gen;
-----------------------------------------------------------------------
-- Generate inputs
-----------------------------------------------------------------------
stimuli : process
begin
-- Drive inputs T_HOLD time after rising edge of clock
wait until rising_edge(aclk);
wait for T_HOLD;
-- Input a constant phase increment each cycle, and run for long enough to produce 5 periods of outputs
for cycle in 0 to 159 loop
s_axis_phase_tvalid <= '1';
s_axis_phase_tdata <= (others => '0'); -- set unused TDATA bits to zero
s_axis_phase_tdata(21 downto 0) <= "0000000000000000000000"; -- constant phase increment
wait for CLOCK_PERIOD;
end loop;
s_axis_phase_tvalid <= '0';
-- End of test
end_of_simulation <= true;
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
wait;
end process stimuli;
-----------------------------------------------------------------------
-- Check outputs
-----------------------------------------------------------------------
check_outputs : process
variable check_ok : boolean := true;
begin
-- Check outputs T_STROBE time after rising edge of clock
wait until rising_edge(aclk);
wait for T_STROBE;
-- Do not check the output payload values, as this requires the behavioral model
-- which would make this demonstration testbench unwieldy.
-- Instead, check the protocol of the data and phase master channels:
-- check that the payload is valid (not X) when TVALID is high
if m_axis_data_tvalid = '1' then
if is_x(m_axis_data_tdata) then
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
check_ok := false;
end if;
end if;
if m_axis_phase_tvalid = '1' then
if is_x(m_axis_phase_tdata) then
report "ERROR: m_axis_phase_tdata is invalid when m_axis_phase_tvalid is high" severity error;
check_ok := false;
end if;
end if;
assert check_ok
report "ERROR: terminating test with failures." severity failure;
end process check_outputs;
-----------------------------------------------------------------------
-- Assign TDATA fields to aliases, for easy simulator waveform viewing
-----------------------------------------------------------------------
-- Phase slave channel alias signals
s_axis_phase_tdata_inc <= s_axis_phase_tdata(21 downto 0);
-- Data master channel alias signals: update these only when they are valid
m_axis_data_tdata_cosine <= m_axis_data_tdata(15 downto 0) when m_axis_data_tvalid = '1';
m_axis_data_tdata_sine <= m_axis_data_tdata(31 downto 16) when m_axis_data_tvalid = '1';
-- Phase master channel alias signals: update these only when they are valid
m_axis_phase_tdata_phase <= m_axis_phase_tdata(21 downto 0) when m_axis_phase_tvalid = '1';
end tb;
| gpl-2.0 | 417af0d5088f77d04445e317f613855c | 0.566667 | 4.674757 | false | false | false | false |
skordal/potato | src/pp_counter.vhd | 1 | 995 | -- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 -2015 <[email protected]>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pp_counter is
generic(
COUNTER_WIDTH : natural := 64;
COUNTER_STEP : natural := 1
);
port(
clk : in std_logic;
reset : in std_logic;
count : out std_logic_vector(COUNTER_WIDTH - 1 downto 0);
increment : in std_logic
);
end entity pp_counter;
architecture behaviour of pp_counter is
signal current_count : std_logic_vector(COUNTER_WIDTH - 1 downto 0);
begin
count <= current_count;
counter: process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
current_count <= (others => '0');
elsif increment = '1' then
current_count <= std_logic_vector(unsigned(current_count) + COUNTER_STEP);
end if;
end if;
end process counter;
end architecture behaviour;
| bsd-3-clause | e4b1f387c125c84eaa5b21c53083c69e | 0.694472 | 3.148734 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/floating_point_v7_0/hdl/shared/lead_zero_encode.vhd | 2 | 31,657 | `protect begin_protected
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 21696)
`protect data_block
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`protect end_protected
| gpl-2.0 | 4788db7db207afa4de70ff4f97c2fef9 | 0.945099 | 1.837959 | false | false | false | false |
UVVM/UVVM_All | bitvis_uart/src/uart.vhd | 1 | 3,756 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.uart_pif_pkg.all;
entity uart is
generic (
GC_START_BIT : std_logic := '0';
GC_STOP_BIT : std_logic := '1';
GC_CLOCKS_PER_BIT : integer := 16;
GC_MIN_EQUAL_SAMPLES_PER_BIT : integer := 15); -- Number of equal samples needed for valid bit, uart samples on every clock
port(
-- DSP interface and general control signals
clk : in std_logic;
arst : in std_logic;
-- CPU interface
cs : in std_logic;
addr : in unsigned(2 downto 0);
wr : in std_logic;
rd : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0) := (others => '0');
-- UART related signals
rx_a : in std_logic;
tx : out std_logic
);
begin
assert GC_MIN_EQUAL_SAMPLES_PER_BIT > GC_CLOCKS_PER_BIT/2 and GC_MIN_EQUAL_SAMPLES_PER_BIT < GC_CLOCKS_PER_BIT
report "GC_MIN_EQUAL_SAMPLES_PER_BIT must be between GC_CLOCKS_PER_BIT/2 and GC_CLOCKS_PER_BIT"
severity FAILURE;
end uart;
architecture rtl of uart is
-- PIF-core interface
signal p2c : t_p2c; --
signal c2p : t_c2p; --
begin
i_uart_pif : entity work.uart_pif
port map (
arst => arst, --
clk => clk, --
-- CPU interface
cs => cs, --
addr => addr, --
wr => wr, --
rd => rd, --
wdata => wdata, --
rdata => rdata, --
--
p2c => p2c, --
c2p => c2p --
);
i_uart_core : entity work.uart_core
generic map(
GC_START_BIT => GC_START_BIT,
GC_STOP_BIT => GC_STOP_BIT,
GC_CLOCKS_PER_BIT => GC_CLOCKS_PER_BIT,
GC_MIN_EQUAL_SAMPLES_PER_BIT => GC_MIN_EQUAL_SAMPLES_PER_BIT
)
port map (
clk => clk, --
arst => arst, --
-- PIF-core interface
p2c => p2c, --
c2p => c2p, --
-- Interrupt related signals
rx_a => rx_a, --
tx => tx
);
end rtl;
| mit | df083dd158e1d191b26cdbf31b8ed01b | 0.45181 | 4.398126 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab1/VGA_Debug_Unit/alu_toplevel.vhd | 1 | 3,063 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:18:02 03/28/2016
-- Design Name:
-- Module Name: ALU_Toplevel - Dataflow
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU_Toplevel is
Port ( RA : in STD_LOGIC_VECTOR (15 downto 0);
RB : in STD_LOGIC_VECTOR (15 downto 0);
OP : in STD_LOGIC_VECTOR (3 downto 0);
CLK : IN STD_LOGIC;
ALU_OUT : out STD_LOGIC_VECTOR (15 downto 0);
SREG : out STD_LOGIC_VECTOR (3 downto 0);
LDST_DAT : out STD_LOGIC_VECTOR (15 downto 0);
LDST_ADR : out STD_LOGIC_VECTOR (15 downto 0));
end ALU_Toplevel;
architecture Structural of ALU_Toplevel is
signal ARITH : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal SREG_AR : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal LOGIC : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal SREG_LG : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal SHIFT : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal SREG_SH : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal LD_MEM : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal WORD_OUT : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
begin
arith_unit: entity work.arith_unit
port map( RA => RA,
RB => RB,
OP => OP(2 downto 0),
AR_OUT => ARITH);
logical_unit: entity work.logical_unit
port map( RA => RA,
RB => RB,
OP => OP(2 downto 0),
LOG_OUT => LOGIC,
SREG_OUT => SREG_LG);
shift_unit: entity work.shift_unit
port map( RA => RA,
SHIFT => RB(7 downto 0),
OP => OP(3),
SHIFT_OUT => SHIFT,
SREG_OUT => SREG_SH);
word_unit: entity work.word_unit
port map( DATAIN => RA,
IMMAddr => RB(7 downto 0),
CLK => CLK,
OP => OP,
RESULT => WORD_OUT);
with OP select
ALU_OUT <=
ARITH when "0000", -- ADD (ARITHMETIC)
ARITH when "0001", -- SUB (ARITHMETIC)
LOGIC when "0010", -- AND (LOGICAL)
LOGIC when "0011", -- OR (LOGICAL)
LOGIC when "0100", -- MOV (LOGICAL)
ARITH when "0101", -- ADDI (ARITHMETIC)
LOGIC when "0110",--, -- ANDI (LOGICAL)
SHIFT when "0111", -- SL (SHIFT)
SHIFT when "1000",--, -- SR (SHIFT)
X"0001" when "1001", -- LW (WORD)
RA when "1010", -- SW (WORD)
X"0000" when OTHERS;
end Structural;
| gpl-3.0 | cabcedcb43f0453b4a6fbe4230af73ce | 0.568723 | 3.053838 | false | false | false | false |
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LL713A==
`protect end_protected
| gpl-2.0 | 2d265b3245a651de97f143264b6a2336 | 0.937244 | 1.859593 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/xfft_v9_0/hdl/butterfly_dsp48e_bypass.vhd | 2 | 44,236 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 31008)
`protect data_block
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`protect end_protected
| gpl-2.0 | 88f69a5639129342c3497857f19515b3 | 0.950267 | 1.828916 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/floating_point_v7_0/hdl/shared/twos_comp.vhd | 2 | 9,914 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5600)
`protect data_block
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`protect end_protected
| gpl-2.0 | 08c28eb32c363c02a3e7dacb86c83bfe | 0.924652 | 1.905805 | false | false | false | false |
skordal/potato | soc/pp_soc_uart.vhd | 1 | 10,895 | -- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2016 <[email protected]>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! @brief Simple UART module.
--! The following registers are defined:
--! |--------------------|--------------------------------------------|
--! | Address | Description |
--! |--------------------|--------------------------------------------|
--! | 0x00 | Transmit register (write-only) |
--! | 0x04 | Receive register (read-only) |
--! | 0x08 | Status register (read-only) |
--! | 0x0c | Sample clock divisor register (read/write) |
--! | 0x10 | Interrupt enable register (read/write) |
--! |--------------------|--------------------------------------------|
--!
--! The status register contains the following bits:
--! - Bit 0: receive buffer empty
--! - Bit 1: transmit buffer empty
--! - Bit 2: receive buffer full
--! - Bit 3: transmit buffer full
--!
--! The sample clock divisor should be set according to the formula:
--! sample_clk = (f_clk / (baudrate * 16)) - 1
--!
--! If the sample clock divisor register is set to 0, the sample clock
--! is stopped.
--!
--! Interrupts are enabled by setting the corresponding bit in the interrupt
--! enable register. The following bits are available:
--! - Bit 0: data received (receive buffer not empty)
--! - Bit 1: ready to send data (transmit buffer empty)
entity pp_soc_uart is
generic(
FIFO_DEPTH : natural := 64 --! Depth of the input and output FIFOs.
);
port(
clk : in std_logic;
reset : in std_logic;
-- UART ports:
txd : out std_logic;
rxd : in std_logic;
-- Interrupt signal:
irq : out std_logic;
-- Wishbone ports:
wb_adr_in : in std_logic_vector(11 downto 0);
wb_dat_in : in std_logic_vector( 7 downto 0);
wb_dat_out : out std_logic_vector( 7 downto 0);
wb_we_in : in std_logic;
wb_cyc_in : in std_logic;
wb_stb_in : in std_logic;
wb_ack_out : out std_logic
);
end entity pp_soc_uart;
architecture behaviour of pp_soc_uart is
subtype bitnumber is natural range 0 to 7; --! Type representing the index of a bit.
-- UART sample clock signals:
signal sample_clk : std_logic;
signal sample_clk_divisor : std_logic_vector(7 downto 0);
signal sample_clk_counter : std_logic_vector(sample_clk_divisor'range);
-- UART receive process signals:
type rx_state_type is (IDLE, RECEIVE, STARTBIT, STOPBIT);
signal rx_state : rx_state_type;
signal rx_byte : std_logic_vector(7 downto 0);
signal rx_current_bit : bitnumber;
subtype rx_sample_counter_type is natural range 0 to 15;
signal rx_sample_counter : rx_sample_counter_type;
signal rx_sample_value : rx_sample_counter_type;
subtype rx_sample_delay_type is natural range 0 to 7;
signal rx_sample_delay : rx_sample_delay_type;
-- UART transmit process signals:
type tx_state_type is (IDLE, TRANSMIT, STOPBIT);
signal tx_state : tx_state_type;
signal tx_byte : std_logic_vector(7 downto 0);
signal tx_current_bit : bitnumber;
-- UART transmit clock:
subtype uart_tx_counter_type is natural range 0 to 15;
signal uart_tx_counter : uart_tx_counter_type := 0;
signal uart_tx_clk : std_logic;
-- Buffer signals:
signal send_buffer_full, send_buffer_empty : std_logic;
signal recv_buffer_full, recv_buffer_empty : std_logic;
signal send_buffer_input, send_buffer_output : std_logic_vector(7 downto 0);
signal recv_buffer_input, recv_buffer_output : std_logic_vector(7 downto 0);
signal send_buffer_push, send_buffer_pop : std_logic := '0';
signal recv_buffer_push, recv_buffer_pop : std_logic := '0';
-- IRQ enable signals:
signal irq_recv_enable, irq_tx_ready_enable : std_logic := '0';
-- Wishbone signals:
type wb_state_type is (IDLE, WRITE_ACK, READ_ACK);
signal wb_state : wb_state_type;
signal wb_ack : std_logic; --! Wishbone acknowledge signal
begin
irq <= (irq_recv_enable and (not recv_buffer_empty))
or (irq_tx_ready_enable and send_buffer_empty);
---------- UART receive ----------
recv_buffer_input <= rx_byte;
uart_receive: process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
rx_state <= IDLE;
recv_buffer_push <= '0';
else
case rx_state is
when IDLE =>
if recv_buffer_push = '1' then
recv_buffer_push <= '0';
end if;
if sample_clk = '1' and rxd = '0' then
rx_sample_value <= rx_sample_counter;
rx_sample_delay <= 0;
rx_current_bit <= 0;
rx_state <= STARTBIT;
end if;
when STARTBIT =>
if sample_clk = '1' then
if rx_sample_delay = 7 then
rx_state <= RECEIVE;
rx_sample_value <= rx_sample_counter;
rx_sample_delay <= 0;
else
rx_sample_delay <= rx_sample_delay + 1;
end if;
end if;
when RECEIVE =>
if sample_clk = '1' and rx_sample_counter = rx_sample_value then
if rx_current_bit /= 7 then
rx_byte(rx_current_bit) <= rxd;
rx_current_bit <= rx_current_bit + 1;
else
rx_byte(rx_current_bit) <= rxd;
rx_state <= STOPBIT;
end if;
end if;
when STOPBIT =>
if sample_clk = '1' and rx_sample_counter = rx_sample_value then
rx_state <= IDLE;
if recv_buffer_full = '0' then
recv_buffer_push <= '1';
end if;
end if;
end case;
end if;
end if;
end process uart_receive;
sample_counter: process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
rx_sample_counter <= 0;
elsif sample_clk = '1' then
if rx_sample_counter = 15 then
rx_sample_counter <= 0;
else
rx_sample_counter <= rx_sample_counter + 1;
end if;
end if;
end if;
end process sample_counter;
---------- UART transmit ----------
tx_byte <= send_buffer_output;
uart_transmit: process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
txd <= '1';
tx_state <= IDLE;
send_buffer_pop <= '0';
tx_current_bit <= 0;
else
case tx_state is
when IDLE =>
if send_buffer_empty = '0' and uart_tx_clk = '1' then
txd <= '0';
send_buffer_pop <= '1';
tx_current_bit <= 0;
tx_state <= TRANSMIT;
elsif uart_tx_clk = '1' then
txd <= '1';
end if;
when TRANSMIT =>
if send_buffer_pop = '1' then
send_buffer_pop <= '0';
elsif uart_tx_clk = '1' and tx_current_bit = 7 then
txd <= tx_byte(tx_current_bit);
tx_state <= STOPBIT;
elsif uart_tx_clk = '1' then
txd <= tx_byte(tx_current_bit);
tx_current_bit <= tx_current_bit + 1;
end if;
when STOPBIT =>
if uart_tx_clk = '1' then
txd <= '1';
tx_state <= IDLE;
end if;
end case;
end if;
end if;
end process uart_transmit;
uart_tx_clock_generator: process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
uart_tx_counter <= 0;
uart_tx_clk <= '0';
else
if sample_clk = '1' then
if uart_tx_counter = 15 then
uart_tx_counter <= 0;
uart_tx_clk <= '1';
else
uart_tx_counter <= uart_tx_counter + 1;
uart_tx_clk <= '0';
end if;
else
uart_tx_clk <= '0';
end if;
end if;
end if;
end process uart_tx_clock_generator;
---------- Sample clock generator ----------
sample_clock_generator: process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
sample_clk_counter <= (others => '0');
sample_clk <= '0';
else
if sample_clk_divisor /= x"00" then
if sample_clk_counter = sample_clk_divisor then
sample_clk_counter <= (others => '0');
sample_clk <= '1';
else
sample_clk_counter <= std_logic_vector(unsigned(sample_clk_counter) + 1);
sample_clk <= '0';
end if;
end if;
end if;
end if;
end process sample_clock_generator;
---------- Data Buffers ----------
send_buffer: entity work.pp_fifo
generic map(
DEPTH => FIFO_DEPTH,
WIDTH => 8
) port map(
clk => clk,
reset => reset,
full => send_buffer_full,
empty => send_buffer_empty,
data_in => send_buffer_input,
data_out => send_buffer_output,
push => send_buffer_push,
pop => send_buffer_pop
);
recv_buffer: entity work.pp_fifo
generic map(
DEPTH => FIFO_DEPTH,
WIDTH => 8
) port map(
clk => clk,
reset => reset,
full => recv_buffer_full,
empty => recv_buffer_empty,
data_in => recv_buffer_input,
data_out => recv_buffer_output,
push => recv_buffer_push,
pop => recv_buffer_pop
);
---------- Wishbone Interface ----------
wb_ack_out <= wb_ack and wb_cyc_in and wb_stb_in;
wishbone: process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
wb_ack <= '0';
wb_state <= IDLE;
send_buffer_push <= '0';
recv_buffer_pop <= '0';
sample_clk_divisor <= (others => '0');
irq_recv_enable <= '0';
irq_tx_ready_enable <= '0';
else
case wb_state is
when IDLE =>
if wb_cyc_in = '1' and wb_stb_in = '1' then
if wb_we_in = '1' then -- Write to register
if wb_adr_in = x"000" then
send_buffer_input <= wb_dat_in;
send_buffer_push <= '1';
elsif wb_adr_in = x"00c" then
sample_clk_divisor <= wb_dat_in;
elsif wb_adr_in = x"010" then
irq_recv_enable <= wb_dat_in(0);
irq_tx_ready_enable <= wb_dat_in(1);
end if;
-- Invalid writes are acked and ignored.
wb_ack <= '1';
wb_state <= WRITE_ACK;
else -- Read from register
if wb_adr_in = x"004" then
recv_buffer_pop <= '1';
elsif wb_adr_in = x"008" then
wb_dat_out <= x"0" & send_buffer_full & recv_buffer_full & send_buffer_empty & recv_buffer_empty;
wb_ack <= '1';
elsif wb_adr_in = x"00c" then
wb_dat_out <= sample_clk_divisor;
wb_ack <= '1';
elsif wb_adr_in = x"010" then
wb_dat_out <= (0 => irq_recv_enable, 1 => irq_tx_ready_enable, others => '0');
wb_ack <= '1';
else
wb_dat_out <= (others => '0');
wb_ack <= '1';
end if;
wb_state <= READ_ACK;
end if;
end if;
when WRITE_ACK =>
send_buffer_push <= '0';
if wb_stb_in = '0' then
wb_ack <= '0';
wb_state <= IDLE;
end if;
when READ_ACK =>
if recv_buffer_pop = '1' then
recv_buffer_pop <= '0';
else
wb_dat_out <= recv_buffer_output;
wb_ack <= '1';
end if;
if wb_stb_in = '0' then
wb_ack <= '0';
wb_state <= IDLE;
end if;
end case;
end if;
end if;
end process wishbone;
end architecture behaviour;
| bsd-3-clause | 12487c955a753fc6acdfcb2747b25fe7 | 0.571638 | 3.062114 | false | false | false | false |
freecores/light8080 | vhdl/test/light8080_tb1.vhdl | 1 | 20,395 | --------------------------------------------------------------------------------
-- Generated from template tb_template.vhdl by hexconv.pl
--------------------------------------------------------------------------------
-- Light8080 simulation test bench.
--------------------------------------------------------------------------------
-- Source for the 8080 program is in asm\tb1.asm
--------------------------------------------------------------------------------
--
-- This test bench provides a simulated CPU system to test programs. This test
-- bench does not do any assertions or checks, all assertions are left to the
-- software.
--
-- The simulated environment has 2KB of RAM, mirror-mapped to all the memory
-- map of the 8080, initialized with the test program object code. See the perl
-- script 'util\hexconv.pl' and BAT files in the asm directory.
--
-- Besides, it provides some means to trigger hardware irq from software,
-- including the specification of the instructions fed to the CPU as interrupt
-- vectors during inta cycles.
--
-- We will simulate 8 possible irq sources. The software can trigger any one of
-- them by writing at registers 0x010 and 0x011. Register 0x010 holds the irq
-- source to be triggered (0 to 7) and register 0x011 holds the number of clock
-- cycles that will elapse from the end of the instruction that writes to the
-- register to the assertion of intr.
--
-- When the interrupt is acknowledged and inta is asserted, the test bench reads
-- the value at register 0x010 as the irq source, and feeds an instruction to
-- the CPU starting from the RAM address 0040h+source*4.
-- That is, address range 0040h-005fh is reserved for the simulated 'interrupt
-- vectors', a total of 4 bytes for each of the 8 sources. This allows the
-- software to easily test different interrupt vectors without any hand
-- assembly. All of this is strictly simulation-only stuff.
--
--
-- Upon completion, the software must write a value to register 0x020. Writing
-- a 0x055 means 'success', writing a 0x0aa means 'failure'. Success and
-- failure conditions are defined by the software.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.ALL;
entity light8080_tb1 is
end entity light8080_tb1;
architecture behavior of light8080_tb1 is
--------------------------------------------------------------------------------
-- Simulation parameters
-- T: simulated clock period
constant T : time := 100 ns;
-- MAX_SIM_LENGTH: maximum simulation time
constant MAX_SIM_LENGTH : time := T*5000;
--------------------------------------------------------------------------------
-- Component Declaration for the Unit Under Test (UUT)
component light8080
port (
addr_out : out std_logic_vector(15 downto 0);
inta : out std_logic;
inte : out std_logic;
halt : out std_logic;
intr : in std_logic;
vma : out std_logic;
io : out std_logic;
rd : out std_logic;
wr : out std_logic;
fetch : out std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
clk : in std_logic;
reset : in std_logic );
end component;
signal data_i : std_logic_vector(7 downto 0) := (others=>'0');
signal vma_o : std_logic;
signal rd_o : std_logic;
signal wr_o : std_logic;
signal io_o : std_logic;
signal data_o : std_logic_vector(7 downto 0);
signal data_mem : std_logic_vector(7 downto 0);
signal addr_o : std_logic_vector(15 downto 0);
signal fetch_o : std_logic;
signal inta_o : std_logic;
signal inte_o : std_logic;
signal intr_i : std_logic := '0';
signal halt_o : std_logic;
signal reset : std_logic := '0';
signal clk : std_logic := '1';
signal done : std_logic := '0';
type t_rom is array(0 to 2047) of std_logic_vector(7 downto 0);
signal rom : t_rom := (
X"c3",X"60",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"c6",X"07",X"fb",X"c9",X"00",X"00",X"00",X"00",
X"47",X"c9",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"3c",X"00",X"00",X"00",X"cf",X"00",X"00",X"00",
X"23",X"00",X"00",X"00",X"3e",X"42",X"00",X"00",
X"21",X"34",X"12",X"00",X"c3",X"10",X"01",X"00",
X"cd",X"15",X"01",X"00",X"cd",X"18",X"01",X"00",
X"31",X"5b",X"01",X"3e",X"13",X"e7",X"fe",X"1a",
X"c2",X"0b",X"01",X"3e",X"00",X"d3",X"10",X"fb",
X"3e",X"14",X"d3",X"11",X"3e",X"27",X"00",X"00",
X"00",X"00",X"fe",X"28",X"c2",X"0b",X"01",X"3e",
X"01",X"d3",X"10",X"fb",X"3e",X"14",X"d3",X"11",
X"3e",X"20",X"00",X"00",X"00",X"00",X"fe",X"27",
X"c2",X"0b",X"01",X"21",X"ff",X"13",X"3e",X"02",
X"d3",X"10",X"fb",X"3e",X"04",X"d3",X"11",X"00",
X"00",X"7d",X"fe",X"00",X"c2",X"0b",X"01",X"7c",
X"fe",X"14",X"c2",X"0b",X"01",X"3e",X"03",X"d3",
X"10",X"fb",X"3e",X"04",X"d3",X"11",X"00",X"00",
X"fe",X"42",X"c2",X"0b",X"01",X"3e",X"04",X"d3",
X"10",X"fb",X"3e",X"04",X"d3",X"11",X"00",X"00",
X"7c",X"fe",X"12",X"c2",X"0b",X"01",X"7d",X"fe",
X"34",X"c2",X"0b",X"01",X"3e",X"05",X"d3",X"10",
X"fb",X"3e",X"04",X"d3",X"11",X"00",X"00",X"fe",
X"79",X"c2",X"0b",X"01",X"3e",X"06",X"d3",X"10",
X"fb",X"3e",X"04",X"d3",X"11",X"3c",X"00",X"fe",
X"05",X"c2",X"0b",X"01",X"78",X"fe",X"19",X"c2",
X"0b",X"01",X"f3",X"3e",X"07",X"d3",X"10",X"3e",
X"04",X"d3",X"11",X"00",X"00",X"00",X"3e",X"55",
X"d3",X"20",X"76",X"3e",X"aa",X"d3",X"20",X"76",
X"3e",X"79",X"c3",X"df",X"00",X"06",X"19",X"c9",
X"c3",X"0b",X"01",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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signal irq_vector_byte: std_logic_vector(7 downto 0);
signal irq_source : integer range 0 to 7;
signal cycles_to_intr : integer range -10 to 255;
signal int_vector_index : integer range 0 to 3;
signal addr_vector_table: integer range 0 to 65535;
begin
-- Instantiate the Unit Under Test (UUT)
uut: light8080 PORT MAP(
clk => clk,
reset => reset,
vma => vma_o,
rd => rd_o,
wr => wr_o,
io => io_o,
fetch => fetch_o,
addr_out => addr_o,
data_in => data_i,
data_out => data_o,
intr => intr_i,
inte => inte_o,
inta => inta_o,
halt => halt_o
);
-- clock: run clock until test is done
clock:
process(done, clk)
begin
if done = '0' then
clk <= not clk after T/2;
end if;
end process clock;
-- Drive reset and done
main_test:
process
begin
-- Assert reset for at least one full clk period
reset <= '1';
wait until clk = '1';
wait for T/2;
reset <= '0';
-- Remember to 'cut away' the preceding 3 clk semiperiods from
-- the wait statement...
wait for (MAX_SIM_LENGTH - T*1.5);
-- Maximum sim time elapsed, assume the program ran away and
-- stop the clk process asserting 'done' (which will stop the simulation)
done <= '1';
assert (done = '1')
report "Test timed out."
severity failure;
wait;
end process main_test;
-- Synchronous RAM; 2KB mirrored everywhere
synchronous_ram:
process(clk)
begin
if (clk'event and clk='1') then
data_mem <= rom(conv_integer(addr_o(10 downto 0)));
if wr_o = '1' and addr_o(15 downto 11)="00000" then
rom(conv_integer(addr_o(10 downto 0))) <= data_o;
end if;
end if;
end process synchronous_ram;
irq_trigger_register:
process(clk)
begin
if (clk'event and clk='1') then
if reset='1' then
cycles_to_intr <= -10; -- meaning no interrupt pending
intr_i <= '0';
else
if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"11" then
cycles_to_intr <= conv_integer(data_o) + 1;
else
if cycles_to_intr >= 0 then
cycles_to_intr <= cycles_to_intr - 1;
end if;
if cycles_to_intr = 0 then
intr_i <= '1';
else
intr_i <= '0';
end if;
end if;
end if;
end if;
end process irq_trigger_register;
irq_source_register:
process(clk)
begin
if (clk'event and clk='1') then
if reset='1' then
irq_source <= 0;
else
if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"10" then
irq_source <= conv_integer(data_o(2 downto 0));
end if;
end if;
end if;
end process irq_source_register;
-- 'interrupt vector' logic.
irq_vector_table:
process(clk)
begin
if (clk'event and clk='1') then
if vma_o = '1' and rd_o='1' then
if inta_o = '1' then
int_vector_index <= int_vector_index + 1;
else
int_vector_index <= 0;
end if;
end if;
-- this is the address of the byte we'll feed to the CPU
addr_vector_table <= 64+irq_source*4+int_vector_index;
end if;
end process irq_vector_table;
irq_vector_byte <= rom(addr_vector_table);
data_i <= data_mem when inta_o='0' else irq_vector_byte;
test_outcome_register:
process(clk)
variable outcome : std_logic_vector(7 downto 0);
begin
if (clk'event and clk='1') then
if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"20" then
assert (data_o /= X"55") report "Software reports SUCCESS" severity failure;
assert (data_o /= X"aa") report "Software reports FAILURE" severity failure;
assert ((data_o = X"aa") or (data_o = X"55"))
report "Software reports unexpected outcome value."
severity failure;
end if;
end if;
end process test_outcome_register;
end;
| gpl-3.0 | 964f8ceb036af0c080ff7e28facef604 | 0.529443 | 1.898799 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_7/part_3/ip/clk_182/clk_182.vhd | 1 | 4,552 | -- file: clk_182.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___182.500______0.000______50.0______121.506____104.359
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_182 is
port
(-- Clock in ports
clk_200MHz : in std_logic;
-- Clock out ports
clk_182MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_182;
architecture xilinx of clk_182 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_182,clk_wiz_v5_1,{component_name=clk_182,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component clk_182_clk_wiz
port
(-- Clock in ports
clk_200MHz : in std_logic;
-- Clock out ports
clk_182MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end component;
begin
U0: clk_182_clk_wiz
port map (
-- Clock in ports
clk_200MHz => clk_200MHz,
-- Clock out ports
clk_182MHz => clk_182MHz,
-- Status and control signals
locked => locked
);
end xilinx;
| gpl-2.0 | 15e070d7166214520f2f802de3dcbe7e | 0.633128 | 4.199262 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xbip_dsp48_addsub_v3_0/hdl/xbip_dsp48_addsub_rtl.vhd | 7 | 22,928 | `protect begin_protected
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`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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| gpl-2.0 | 09de764b1e2d16858cd92491a61c6ed3 | 0.942254 | 1.845015 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab2/Shadow_Register/Lab04/alu_toplevel.vhd | 5 | 3,690 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:18:02 03/28/2016
-- Design Name:
-- Module Name: ALU_Toplevel - Dataflow
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU_Toplevel is
Port ( RA : in STD_LOGIC_VECTOR (15 downto 0);
RB : in STD_LOGIC_VECTOR (15 downto 0);
OP : in STD_LOGIC_VECTOR (3 downto 0);
CLK : IN STD_LOGIC;
ALU_OUT : out STD_LOGIC_VECTOR (15 downto 0);
SREG : out STD_LOGIC_VECTOR (3 downto 0);
LDST_DAT : out STD_LOGIC_VECTOR (15 downto 0);
LDST_ADR : out STD_LOGIC_VECTOR (15 downto 0));
end ALU_Toplevel;
architecture Structural of ALU_Toplevel is
signal ARITH : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal SREG_AR : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal LOGIC : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal SREG_LG : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal SHIFT : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal SREG_SH : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal LD_MEM : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal WORD_OUT : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal LDST_ADR_8 : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
begin
LDST_ADR <= X"00" & LDST_ADR_8;
arith_unit: entity work.arith_unit
port map( RA => RA,
RB => RB,
OP => OP(2 downto 0),
AR_OUT => ARITH,
SREG_OUT => SREG_AR);
logical_unit: entity work.logical_unit
port map( RA => RA,
RB => RB,
OP => OP(2 downto 0),
LOG_OUT => LOGIC,
SREG_OUT => SREG_LG);
shift_unit: entity work.shift_unit
port map( RA => RA,
SHIFT => RB(7 downto 0),
OP => OP(3),
SHIFT_OUT => SHIFT,
SREG_OUT => SREG_SH);
word_unit: entity work.word_unit
port map( DATAIN => RA,
IMMAddr => RB(7 downto 0),
CLK => CLK,
OP => OP,
RESULT => WORD_OUT,
DST_ADR => LDST_ADR_8,
STORE_DATA => LDST_DAT);
with OP select
ALU_OUT <=
ARITH when "0000", -- ADD (ARITHMETIC)
ARITH when "0001", -- SUB (ARITHMETIC)
LOGIC when "0010", -- AND (LOGICAL)
LOGIC when "0011", -- OR (LOGICAL)
LOGIC when "0100", -- MOV (LOGICAL)
ARITH when "0101", -- ADDI (ARITHMETIC)
LOGIC when "0110",--, -- ANDI (LOGICAL)
SHIFT when "0111", -- SL (SHIFT)
SHIFT when "1000",--, -- SR (SHIFT)
WORD_OUT when "1001", -- LW (WORD)
RA when "1010", -- SW (WORD)
X"0000" when OTHERS;
with OP select
SREG <=
SREG_AR when "0000", -- ADD (ARITHMETIC)
SREG_AR when "0001", -- SUB (ARITHMETIC)
SREG_LG when "0010", -- AND (LOGICAL)
SREG_LG when "0011", -- OR (LOGICAL)
SREG_LG when "0100", -- MOV (LOGICAL)
SREG_AR when "0101", -- ADDI (ARITHMETIC)
SREG_LG when "0110",--, -- ANDI (LOGICAL)
SREG_SH when "0111", -- SL (SHIFT)
SREG_SH when "1000",--, -- SR (SHIFT)
X"0" when OTHERS;
end Structural;
| gpl-3.0 | 54f0b145fcdfd3939ad14c474d30856a | 0.568022 | 2.944932 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab1/Part1/FetchModule.vhd | 1 | 1,611 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:50:57 03/11/2016
-- Design Name:
-- Module Name: FetchModule - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FetchModule is
generic(PCWIDTH:integer:=16);
generic(ADDRWIDTH:integer:=16);
generic(DATAWIDTH:integer:=16);
Port ( PRGMADR : in STD_LOGIC_VECTOR (PCWIDTH-1 downto 0);
EN : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
ADDR : out STD_LOGIC_VECTOR (ADDRWIDTH-1 downto 0);
DATA : in STD_LOGIC_VECTOR (DATAWIDTH-1 downto 0);
RAADR : out STD_LOGIC_VECTOR (DATAWIDTH-1 downto 0);
RBADR : out STD_LOGIC_VECTOR ( downto 0);
OPCODE : out STD_LOGIC_VECTOR (3 downto 0);
IMMDATA : out STD_LOGIC_VECTOR (0 downto 0));
end FetchModule;
architecture Behavioral of FetchModule is
begin
process(CLK,RST)
begin
if(RST = '1')then
ADDR <= (OTHERS => '0');
elsif (
end Behavioral;
| gpl-3.0 | f66a342fc276361f89cb484db514c3e9 | 0.584109 | 3.817536 | false | false | false | false |
keith-epidev/VHDL-lib | src/components/adc/adc.vhd | 1 | 3,358 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06.03.2014 15:08:57
-- Design Name:
-- Module Name: cro - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.VHDL_lib.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity adc is
port (
clk_250MHz : in std_logic;
adc_clk_in_p: in std_logic;
adc_clk_in_n: in std_logic;
adc_data_in_p: in std_logic_vector(7 downto 0);
adc_data_in_n: in std_logic_vector(7 downto 0);
adc_data: out std_logic_vector(15 downto 0)
);
end adc;
architecture Behavioral of adc is
signal adc_data_ddr,od,ev: std_logic_vector(7 downto 0) := (others=>'0');
signal adc_clk_lock: std_logic := '0';
signal adc_datab,adc_data_buf0, adc_data_buf1, adc_data_buf2, adc_data_buf3: std_logic_vector(15 downto 0) := (others=>'0');
signal dc_value: signed(15 downto 0) := (others=>'0');
signal accumulator: signed(28 downto 0) := (others=>'0');
signal n: std_logic_vector(12 downto 0) := (others=>'0');
begin
adc_data <= adc_datab;
Bufgen:
for i in 0 to 7 generate
begin
ibuf_data_in : IBUFDS
generic map (
DIFF_TERM => TRUE,
IBUF_LOW_PWR => FALSE,
IOSTANDARD => "LVDS_25"
)
port map (
O => adc_data_ddr(i),
I => adc_data_in_p(i),
IB => adc_data_in_n(i)
);
IDDR_inst : IDDR
generic map (
DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE", "SAME_EDGE" -- or "SAME_EDGE_PIPELINED"
INIT_Q1 => '0', -- Initial value of Q1: '0' or '1'
INIT_Q2 => '0', -- Initial value of Q2: '0' or '1'
SRTYPE => "ASYNC") -- Set/Reset type: "SYNC" or "ASYNC"
port map (
Q1 => od(i), -- 1-bit output for positive edge of clock
Q2 => ev(i), -- 1-bit output for negative edge of clock
C => clk_250MHz, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D => adc_data_ddr(i), -- 1-bit DDR data input
R => '0', -- 1-bit reset
S => '0' -- 1-bit set
);
end generate;
process(clk_250MHz)
begin
if(clk_250MHz'event and clk_250MHz='1')then
adc_data_buf0(15 downto 8) <= od(7) & ev(7) & od(6) & ev(6) & od(5) & ev(5) & od(4) & ev(4);
adc_data_buf0(7 downto 0) <= od(3) & ev(3) & od(2) & ev(2) & od(1) & ev(1) & od(0) & ev(0);
adc_data_buf1 <= adc_data_buf0;
adc_data_buf2 <= std_logic_vector(signed(adc_data_buf1- 32768));
end if;
end process;
process(clk_250MHz)
begin
if(clk_250MHz'event and clk_250MHz='1')then
adc_data_buf3 <= std_logic_vector(signed(adc_data_buf2) - dc_value);
if(n < 2048)then
accumulator <= accumulator + signed(adc_data_buf2);
n <= n + 1;
else
n <= (others=>'0');
accumulator <= (others=>'0');
dc_value <= resize(shift_right(accumulator,11),16); --divide by 2048
end if;
adc_datab <= adc_data_buf3;
end if;
end process;
end Behavioral;
| gpl-2.0 | 7164cdf03567323bf8dc6b6c1bad4cb2 | 0.567898 | 2.870085 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/clk_108MHz/clk_108MHz.vhd | 3 | 4,576 | -- file: clk_108MHz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___108.000______0.000______50.0______127.691_____97.646
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_____________100____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_108MHz is
port
(-- Clock in ports
clk_100MHz : in std_logic;
-- Clock out ports
clk_108MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_108MHz;
architecture xilinx of clk_108MHz is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_108MHz,clk_wiz_v5_1,{component_name=clk_108MHz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component clk_108MHz_clk_wiz
port
(-- Clock in ports
clk_100MHz : in std_logic;
-- Clock out ports
clk_108MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end component;
begin
U0: clk_108MHz_clk_wiz
port map (
-- Clock in ports
clk_100MHz => clk_100MHz,
-- Clock out ports
clk_108MHz => clk_108MHz,
-- Status and control signals
locked => locked
);
end xilinx;
| gpl-2.0 | 62c02018922bb402bac6911cdec58f05 | 0.634178 | 4.198165 | false | false | false | false |
fafaldo/ethernet | ethernet4b/Ethertype.vhd | 1 | 1,225 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Ethertype is
port( data_in : in std_logic_vector(7 downto 0);
enable : in std_logic;
reset : in std_logic;
clk : in std_logic;
ethertype : out std_logic_vector(15 downto 0)
);
end Ethertype;
architecture Behavioral of Ethertype is
signal address_counter : std_logic_vector(10 downto 0) := (others=>'0');
begin
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
address_counter <= (others=>'0');
elsif enable = '1' then
address_counter <= address_counter+1;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
ethertype <= (others=>'0');
elsif address_counter = 13 then
ethertype(15 downto 8) <= data_in;
elsif address_counter = 14 then
ethertype(7 downto 0) <= data_in;
end if;
end if;
end process;
end Behavioral; | apache-2.0 | d95a64febb6be1e222025af24ec5a8b7 | 0.689796 | 3.23219 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/cmpy_v6_0/hdl/cmpy_v6_0.vhd | 2 | 16,743 | `protect begin_protected
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`protect end_protected
| gpl-2.0 | c9c1ec72f5cbdf33fac3669a74b41e2c | 0.937705 | 1.860127 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab2/Shadow_Reg_No_VGA/Shadow_EX_NoVGA/ipcore_dir/Instr_Mem1/example_design/Instr_Mem1_prod.vhd | 2 | 10,090 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: Instr_Mem1_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3e
-- C_XDEVICEFAMILY : spartan3e
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : Instr_Mem1.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 32
-- C_READ_DEPTH_A : 32
-- C_ADDRA_WIDTH : 5
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 32
-- C_READ_DEPTH_B : 32
-- C_ADDRB_WIDTH : 5
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY Instr_Mem1_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END Instr_Mem1_prod;
ARCHITECTURE xilinx OF Instr_Mem1_prod IS
COMPONENT Instr_Mem1_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : Instr_Mem1_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| gpl-3.0 | 123df39bd03ea07c39cff81845f538b7 | 0.49336 | 3.819076 | false | false | false | false |
Subsets and Splits