repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/mult_gen_v12_0/hdl/dsp_pkg.vhd | 12 | 142,648 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
peElgUBnFYE95eKYTfZrpnIvdxmsESRHI8KsUslKl3wxGUHo4Q350QpQ5Daeisknn0jkGzHu55GX
rcWj5kY+nA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
foXL846WnMuQyS+KnySX+Um8/BzYDJh1L/Vkuxz872SKIxAGcCGxqYVxF57yWDQolsPqtbmbTxiD
2XI0fyevzAuClOgGeMP5ZM88Vm9zUmlH4Rixwqs38I9V1l2L8Gvg+NRN95ddYuuiy10Q/Pt4UEEs
qCjQhrRbXX1UTL3tnew=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
S7LVSqsd7mNTg02/lZZbRNeWCeanJptVPdmW2TYWEaUfEG0f3QgDXN6cw/ZtDCxyH7QM4o1eCLDV
RxW6Rj+XGbob/LSYNDUSrRqgqf3cilsMzV16ouyMdQzKDi+/yGo5EbTxg3o3GyQMx7rclF1gU476
Kqle5cy0G5goKQaLHYAtAcuu5IyFw62vJJCwLKeyLk89phhJigrHhEAfHWqibymGa90qdDo172bZ
wzci461C/JZoOjYiTJSPfBMtWF+CQn60xf/t2CPjlSGdrCt+lEUMkQNtZUjOFas7Z2ND5N0JOffg
Oby33ERGSw64g78gh717FBsgC3DWgp1tEQ+Pcw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
DE4yvRnHc7oO0HWP5V28l9C8UDq2AHTE+Xd/v7COjBqDFLp+G8yc4rfOTqjOcSMNsttRrOwsbcba
7YcOCAiaOLriUv1Gry3a7kcYiqvBODr6cEj4nGbLinNtjT5raCIA9alFqfNOgSGkheyTfqzDuGa0
z/F1Lzh+WG6J9HzTI58=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
reCKS58wk9DvCHzX2jTuq4IGql4vvQcZraOqLFE0gj+VqiVbOC7zHTOkYlRpG5HtC3W3yZbAF4YB
CbsiltQhm3AfPuNR3vYI2FGLfud7FKeiL++y6CbzGTaysnARY7/FTuNDhCX5jAVm3MFsFVB0Fn6h
m/iRfUJGvHOI4Maw+HD9o9rbNphlJF5aOxGMoI+JxKNMsk7o7W1F5Ce7gh/sReh39pbvT1zX2rjZ
sSrRI1kvWPBRd5pNUI0fINF9C/+wgu+qPRNx6NKuNsUKzV9LjYwEHd2rmNuPVZ2NADQdFTsgp0aa
4oOnxY0X3MMLNsSk5palQw8GZMQRc0Ls0J4dUg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 103856)
`protect data_block
2SL1HOB6XgboWv1VFRDStWRlAKGMbHbk/5iiClYFox0GSbSNI8E0Jga6Tlg+4qTcb72LHcmGwBeh
JjchL4v2t3NVuLhIphCefaiVM9oDO12qHvILHf5GetQBzARStpUIofQECvmlP9f9MSBqVu5/OhlO
56BWK3hRl0iFR3ognZk5M+Wd+GYAlF6f7PIr7DgjzySCoWSzW/tQ0Cp2/ChUu+OYQkPTP6jMNglq
k9u+4WBRv2dqeT8H7cOHE/tvYdKlo02jxzlULC3tlLEQZOyf5zF1XmekoqliMM7qjWagZmUBoLjW
0zbnZYzXksX22Mt7iAqEqO0Cf/v5bC3Q8+KyMNzyt8lIHeKcMheuO7eL5rl8G1iX+OcV27R8qxqT
BM5JIixUKCwcdezToqAdTibJgZxrwdNpZloV+oTm0dC6cYWKCqi0wPJSSzJB0/+1xMZpHQzlbDdz
nxOdVJir/WoBRH5JOOeH+kam2R6NDWDSPb6nmn5DDJkGHtfSZQ3KdA3HtnNORuC/Q33L2owJq6FO
ZDK6idZczP+Zj25OCG2Zh+fgkjf8KzzCQK/qOLHSMcpDU0GGbkRC8IpiiOcxd1yWFGzGNgja3Am6
VnbU5PBbiocQpQuuLGnYCTFsIgQS+HVfQ1/RpkIippBzGLyMfNO9izIlHf5Wm6V9duc/KaFix2UM
b8K76hback4pl62qCgNJGUCL9kwMddkSdl2natCVQk1IlEJ8nw1w8NiJIYXv4wmwiQq7T+VclC2r
G49rp1Rv3CZphS6ZH8DKcXQQyzHy0hWI/X/VuefOx252EJFhOA9bvLzqanezBO+7QzHA6bYGr/Do
MnAHUR/bkma7ymXpdRry7SZsyss4VKTbPbpv8XQz30AIGE5tjw0KrHOyF+n+X4BHNcXetRELCWY7
Pi7fthaCDfqq35RcXqY6f4rEO2rEVQUUOmZ8TQxd4TpdcCBcGLEQNoxBf6cN3CsmsDljoNDzFmx1
NPHFcVn+R26x+BDjpa4pe8lnODsblABxI+zXqpKn31mdmvMib0hziViraOCEC6GGw1eOWmnnnMVo
WRoRA99OmlMZBRZwG+VZVOg0NR3zZc4nfHhuGxpPw4jEjfxAXkUSaHS4vmzHg5K/Qp910BMD6OSB
lhhCcMIBWLG6g0Q4Y4g0lDrU7qBFAOfp0zKvypledlCwqq716epeF4bRc0DXimEpVQs8DH6Mnuuv
Ze/RiWS/TZfMHWmUqtCAQ/Hq5u3KklXyo8+FB1GpmowggB8ZuZgZ/t7OngOCkBFo1azSa+6uiTa/
HSKzL7l8WuyuCiVKfew4k/naNo7XQJEAe4q2tNlztC/1ue4sdcSDP0xbo8piQagcrn24QYxxC/Ir
bqM27PN/vECTvArF0Ryfv855u5aSb5d4S67F4f3m8QWGB2W4CW+Hy/Cz3THB9T+5UeGSk90+WC1U
z92+iCa0tcpttptGYOH7FXIyms7kfxJYXcAC0BDaHnYTgWJYoj4kaAw26Hs4d+lN9VIJqqreHEhs
iuafwwJ5bAy06JhH+0NWg72QFJ+RlABivF59xGmogU42v8homq2q0Tld0Z8o+sxn5DsMWAjJXpm9
eM986HllQK+BxUVduue5Z4atP0zt36/NAGfSl0Sc27RnQVg84KQY1VZC0SNj6vJqubIWtu+kP8rW
w9ROVvZf86SIq4qjg1D8QZMY+nOo7jNL6djac9Ei/6jZG5TYBtwRVZfxyO1ZyI97xAkKxq5UWtVZ
uzOOL+AqODR4/Ze8cmhigF1r1+FPEq9jOT1/94MD9RyUg7yt91R10QYDqma+ZpW70nFoR5C/h1Tn
rmoj1ABlD0nywt46GtC9jUxPU1HJPx5aylkKs0ULF0AdF98vYwWiJwXCjDijzW9ESDHgh+bZ6CZU
mOyYCHzAG2JvWsT9/zk65yKZNI8KREC6JQeRFA6c3SlpJTZ59Faoj7VQ1gXjwvnGmzgY4Q0rAY+f
IyK53fCqhB7vp4B+F9I4UkCZxiYIJlPyJq+rse/8C9KypCWSnKdtZZgJCutdfBljjr+aSoBvdM6c
FaNX4zLKgram8WwOyoNTJl9An7bFMAyfr9xvkBYdw76y2tq3okbxhUPOoSRLscWUu3st94SOsafF
9mGppX+4mETM9wNjz8UwfOFnR5uP0A8M8iBj8+14bDy6D2KZ5eGNesALtnfO1jZbwJBuGHBCE/jo
ystyQRAwSCRAYAi0+uVsRtQdEP9IQFlsdyvSaAEn9QTm5NsuKzAhgN8D5v7kQCFbEN2XwqZxL68g
9Po6rkYpBh9LCrpBH06J/Ucde/HLn3kB7JWNBhpkK5S+loHZqT+80KH3/9iHaBbYeqvxgjRfsRMG
a01ZNEuTzWsjeONgD/CYBjg/SOer8/dCqs51wa2nFRGYVTU2v47Rjj8assV7HLOEZNoeGXb3/aqr
+O42VFxnDG9CYay1KU8Tb8PjfKfbngciVKk3grnpbBZ7lzZ2hofrauUpWmwShIkYPgCWvC3JRksr
C4njak62b+MqF2l+SxUFfkh5EbR+Ijs5fd2vZy4d1HCAqMkCXwxfwsGeXVMfuyrmS/yoZy+OO7C5
fndTnCZv1MpfsHESPP++BYrGL7MLEx7EtEfomq6w51CB/+mKwJgI2S6nCmwB9bsjkLPNaNd5MzE+
ikIn+JOSa5/BNi+B2jOwZT/TFgZvKXtLoNdOJklS4lJ7/++38vejSSwKqz2LATlEjLWJuTxVCffQ
bkU8VILwM9UxKlHB1zi4Lmx8F6kAx5gG+Og615wAxI7800GF3pzZZIdJDloJOa9apHtkV/7WKjbE
rsF2i9CMeO9wGsG6sCfV8HYOUh0a1LHve/dMvp2DMt4dG4jQ/QsuAY+g83nmMEkyCdpVpq1QUc2e
dNS6OqvU2ePMwbP9ItvfkBvWuJOKlJcu+uZ6vBNEJAnw8d/8Kb3VbCwv9WOe8tbdnbFUe7flB0bm
mRyl8r/+5EnvYGlsDi9GWcjsezdpLmsMNAKkKQpxzvqwddLT/9obcHV3Bfex6pTNBgMPv5o6APiA
rU+XuzImof6FMMN4VaXNwLjN/ZIBYEIht5U5vqXuSoT4YD5MswSN7ngrsTWXVZ0Yma3+io71YSl5
q8Tm0arLBoN7kmp9QmYNW2OllaFAOgpYK+aHcbCdlcDEVvjr+1ApCY8NY9OVRsXMpSfg6l0ZO6I3
WBU1js4WYirweNO0i6VjTde2VOPOOcxUeaPqIeTxwiXImQ2WSUoPDDvOB8Kbrvm1SLkFIZ1Tflrb
678+UTaSTS8t8Y0w50wIBgHahdqeJqsmXWpKtcH5L3yOSSb17DXJdnotQLy8maxgvHGDqpEZvICj
YRVQCEsfWl2j738RJfMkUQsR2Gg4VDDnzgUP1PQR2xneGmD7eFUeV77+IhSOKIEWRe2v5toMWhZB
E3uU+U/gu/xuYlWjiYJlD1HL7dgmi/4kkborBMwwgnVggOVkUmTe5lAjxdFDErqAGNtMl5VTNia7
sWIdrrWFZFYvOK63rtf0Ieq8MHIYm5rs+ncFA6vzD0b+l5dGDpzfU7cewSCWBMXoJFxxlBrJ8w0q
w1K+SDTDRh+nQD73iin4rzqsoWDNoxAdDDwa7pfwmlDYRRRScphxaSUZ0oXTC8poWmK+ZRYDw7wj
51m5kCZbnejns4J/vMtn5X502dTE6MhBLL7+imi9+GfijGe4ZqmreveBliDym4udl0ra+BT8s4Lz
srpFGbWMLXoOSntq+Vrjzq2dJly61YlBL5Xoj7EJb+NBd+p/4RvuZwi4NAZ4974ND/fPI4Vdgdbv
6DfY44noqCMiuw8SLOkFIggxofA5nycK5nt3I0CyodMPeCC0uhIaZnMxOL6Y+1YAzRLeoOk0Q30m
D+GgPWj2K0zMtUmmkwXXaAA1azfWbmn4fYdHw6XF1UCIEW9dtZw08Cb/3AW00Rm+xY/Y66p1RCeI
2oh9x/nbppzP62FUVlguqx8A7jXOC6Lr2GMlQ6imVwuYtm1nx1WRHX3uxWbWF5soT73lzGjrST1J
REnH/Qy9GL+e/WnWZWAwaeuUqcZL+jgFWfDmZIvzdtRfjvIhFCf6gzLuy+r1DdJ3cB68P8unI37i
0icX/MPtkVzqxyVrCPXvpyhQhWeST58z1TE1sbnj/H/tkvpyf3uF2PVCP2QoCUIi8BKrbfJhF695
vE9nBtzxigbgm/ApG/tSv7CtnSaxUj7KVXe1w7NBUXT15igqjjIHgxdeNSXTzDaEz4bNSc5tabpO
zDImICW9A9lAxlxtyNhVrY7O8ipR+TRemFQi22oRj6S463XpH83K/gvJULb6HGCBHLgh5k4T5z1l
g7yAxC4gYwsltNoS15D6NB9ltk+9Ho1jvJxzfmRjFm/56lv8fYgl5Z+jORsI9kvfICjBnVrGpbxo
BQeNigs/oNAs8EigF+iwKvW1WmJEASd3HefmAMbG7Y14RXkdkIzePBQv0+0dS112pE52O+9QFMNs
/OhH+JiLolomShrfE+JT/ahPdTnMNxz+ajWpLJcoG4WTnUV2uW0ezss5obHxxud5zAwbrEJQAUXr
KBd1GCNCWjv6JefxxwP0kj+lus1gLy3aQJmoBTc/5NJ+n76DWm95Ahbv8fwDlE4VS4Fs4oSofWrL
T0rdJTF09+4eUv1j/FWKjPjGmh/iai0Ad18PgDPaabIkVXxxozNIMqqKMQHInJFKiHWk0aCn5Isw
TSXifCPz/2CH2o27jy/x42IxcEu7V4rMuwSrIqHe02tO9ZWDu3OmxR5uzKMNwkKuNYncUmG/BmQg
F7Gebva5Y0olVjglYPW+IsCf/CPS6HIrZGVGBffG6ATjkuWfSh2dkpEBPc4wAlMpiZXqge6TRioL
dQCtbdrLWipC4exBejBWFvr8pNDHoELDW2ld5WvgpYns1kKnoXg7Ub+T12lfXogc6mBkOje0dQUJ
N1ISUM2fBXB4sarnPxhpJQlEWvm/3tezCUIVYauNuIot8U30xhhgGPD37L90MHvEy1i+KE22iU+U
O7igciA/m97DIGJ9Q1WsMOamSZOVEMn90NuTUayvJHYLLrh0SvurvxkXlAcewAQNuDaw3usAlb0o
6pMT50dnEKOpOWLFhxXaP2ZozZgu/GAqMo5wVIMHPTd3E27AIdkyD2UVqMIt0bZbB4Bim4SkNSwj
2a2ziyjqPginkN/80pdd+SFzMzsKTFxK8H5V8RnDKNMtXhCyXecThpXdwP5IgA+0BfwoYq/LGMrf
5WYExboH5zF0b4XHg1lJ7PRVmCSBTzxX+r4mbJJsib3+DOpB/ntpKp8I1+n0IYGLPZvLcj8BON0z
N4HHai2fmzh73MskUOphZcedXRe5wTeQ29T7s2sAdbliLUOu5GE4yaPvQAWgXEbBKk7U/pvTlJMe
cZms2exIrp0MD/t/BBuGNhUPJ1wp9pI6d/l/BIb9FCe54jjoyw8N1C0PvXbwjwrdDCOprHwcUVDz
Xar/v7HJRG1Dvv3DC/n5eBdUzfo7AO0+jNx5U53dmf+aUWniG/z7nL3cZ8atIO9sueHPS4ghTdGl
E2iQV9NYcBb5iqgrYwypDQLp8OMN4JmU/eM59ElfrOclFDBfkKScvqO1biQhXo6FgnUJNL6GKlHL
60OffyLYUIS3xPHN29lm8irFiA9wLTjSjNW+jBJHe0Lh3SG3FQX5XHzUNE/p3as7oMZewToR/Kbe
uJNGqOgFZT4zvFnGT06Qjw3TYLTciXe7LClXGRQ7J9Zzbb83c6MUMQQRRhWiSYyHrvdHepuPPuIu
oi7DVHU3tqnYQOuhLiXdivMwTIkuYIOhfjzhzAvpeqm9BeR5zDXUEK3Cgeqjt+/5/7rYNPsxU+/J
78bqz71nI1uYTEoe6PKLT4sv3nCi8HakObPXi7JDU8mvzQseBB2nK0upFi5V4nrMQBVvwyMMOpQS
VeGFjfTHD9cGtcO7/js6psKNR/GQActxAaaop5ERWUKsYtp3OQ9pwlHTtvkOMxC6sf5FU2JClFfs
IpNSylox9h9AzFCi2GmsLAJGWjqLntdHfCRULt7gacitMeqUnzZMo4j31wO4slv+BfQxlyNN7QeC
xKcE+0nv5E41gr+ZxRyoOMmIoqDPuRaxnb/l6Z0PZJzJA9/74bdA/Kvw00h8hmuyQZjuzjPtaClA
AF3wfHXYE4PPEk6Nhu679mDj0kBvsJlu3SCCuUAbxHvgWsXMzKy1Db7gkaJeMA7YjBOv3V6JmwRu
uRXrpWXED8b5Ho+DuoM2XuYgXyg2dTs8ZjTB3OsDkur/T8Lo1d3PneyNyl1CIGVCqjwQ0S/gu5fO
IberFSJN3EB0DPHdt0n4Qfm52roGIo3t1MYBMH0ArZHQT2f9vpeDsZM52s9w9vI9gyc9MAVsDad1
YF6kLZmzSojb+k1gyPu0VBAWHTComVCXFSJJFhH0mb/T07sLfRSkEcKLxwwY8bi+qhNWh10OUoz6
BYG7x5uneJNVE2zSBqP/M7n0434NqF7A1HvjCnuyiHUGI4zqt3UXIPZzzczKaIqAz4m36dSoJqoP
sVRmn0eFddudpSU4eA40lRouhSNpvOo+3cupkUJ6YE2hj+phRPsGTmHDyhlPj8exw8pzBVvw1wU2
kMCvSlSQe/NSbZODdNYN/WPEg0TAHNvSh1RTLcOZOCZ9K7+pDD0B1HE4JHk8iOyv325cyNLch3lY
yv6mJMZ+eCn+t/Byi3fIEy3Cl6MUAcDvpaxoDSatb9/hrJX9oOp7WXvd3zIWXLdxJjZR11sWHMXm
qbtQCubQ1csCPZe3Bq3nzlp3w/r/vQHKubMKtufBPumjR5//Vm0lnVMTbn1hErRMYGySJJjIh1am
aqOkhS1ZqnEuZwW7lp8wx8wHUW6XQi87R3uNhb5Ljvd0+yehczVurBZBqC3n+3JLnhIy+cQSK5ks
FjAS3u+V33nmBn3uPEVG+llzO0Ig1blpv9i5A8iScnamPNef19N5qT78HbYeq7y5xJtl9QtO1mfD
do8eXyJXas6xmh6UQYlP5n6tC1WO9kDp+tjypVVu/prZ1K5XxodiiWTfIuiXPD6+m+hobt4bTmya
hs5p2RVIA7e+NNCuQQ/301QaDGfHWngdkReuhe9vRsMSFtuRnTwJvssXpqlehRBinc2YtNrXdsY6
InBNjH07gV8HdBUr5dAyUBROvsWoClqtelojCpdjU//6X4mxsF9dh6/7zHVIRaWtDqCyy15GjAbM
g0YlIn1qAhiUZGGJrptXU2OvIHRcogW3lad10ggYFMhAcedyFMShYhOt7klU4zdeFPSwK03dVi53
HEFAzrqZPs/W4STois/5hN//CzM2M9RVEUO3Rve2U1MQtnYgGgJ2mOXtoedSrzhxPkcZgk+jt4EN
nFHWKF9UcxoDpikeQqgnSglr8PD10RAuYQsFiWq34KWVHU+w3Gsh8tHSWWTdhajh7MMUpPDm+k92
MKDMYXGonZwHgmKScZQXebVKg+d8mo2gZQZxDKQIB55xKqX19bCpXvXPglj8NHUcZ+4/0Waexm+8
RUf7XOzyIKZH+7ELNzHWKaoe48FHnRU0ti04iiauQLflinGkOay4bYdJhcpkDj+sr5FWKAXiuTsz
5GpZTqJBq+Obzagfzkl3dZ6qf2MYQg1q3BJi9CwnXUDObC75VL7Xr7LYJuiK57xGsuRDCopJHUjv
+SaRe890tW7YbrNouG93WtcM3xbzKgqFrusfJIUZ8y4QN3LK3SW496JfS3R3UqgHbqQVz9YvFZiH
LEMIVRDepezAPosNTT6/4IuNwlGpBeBpSuNeggEViIStFZFB1EfrL93AkHqYQrmh2wFVyijAy8zg
qb56iUMIydLPwP2PXpQXAxNzahDOcahOuDa//cjeVGHfaf5ANQEiF6ABOfQ9f3OjFwRdYVFv9PUn
Mz7uRgVEDGv8l3dR8ZRiKGeoO+54Bsr6M/7FC1/bAV/MI6axYnnu8Qp9bBQMAZyZ66NME6pu6j67
dSEUKt19QsizYGwCAi5ri+VMy/CYHGzcV6b0QOUpvPbA6PUoihZKu0ck4lIzVPJHzrKJSWo95lfU
YCGMyZuFYlDmiCVgad9tjo9uhxJlGcUpWrOlBvYDTZLYjTERDudeGYn/tMDlw05HGZNemds/qwr5
Zov/gAamrIZh1ThoQ6InK0+4nMR5edExFlOPuBn/jNsBk2bGmEKzB9uxhfRP1Dq9pnOxjjFTZ8pu
4X3U4bCIE0VgIdl+VhA2cVXaJ83a63UKHO/Jqt98uMv1MOE4IlWH7UuXCO4JLWqHI6eZoA7cFFN6
tOQzKSsHEY+t+OcVZwbYOax1KJrsuFQ4XilW6k4I9SHnzchEkk8WBZzkiw1Qg2eoWOqu1af72Aey
DLxB/zounKqEZxAPmaJbRN8PW5CE3A/8InZt630+Xx3/jdt+x0j9UPEf0ISi/ChedN/5qr2oKzVL
DlPKkviZEYPci5VXaJO7OzYDtl6Ku8m7RQ9+elsKDdvQbF3zs5ceBclr8fmJm5oYxshw597Q174D
y39LxgFseYnZyZfvvZ2eQubblzktPpc1l5E3SaXgl4BTY9KGtn4SmWUgVPvrMlyRFDPVbQSG7dY1
7RfH9+BtHmV/Xrru/BtpLAfmTchvwcvuo9jRFtMBRSqDuUXvqnvVQZWE6teDKfwg6lao+tifYaUh
hqNC+e3l/d8NwMbfolBb5Ds/xrtei64FWxGD/IdJbyAdQloyxbDTA4Od9wfn2nrdEugqTv4BctRZ
lBieNOMIrIbcJPX/UC6KBaD1qg9sjPKo+4U1+45uJhmC6I0xOWqok5EeTOFlSaUZ/0vJP5gUV0Jq
Kch6cQiUPqiL2BZD0GEuRlKmLZjmXhCcqJ+qrV32BioexgN8Zw6jjCHH3vZgd8qkHHSrU+6iqLKw
ea1xTIMYvM9mBWG02PTM+1Igj131dVxUGC1hI+oUrc88eE9M8k/nZQuZ6HlemyF320L12jqXe0Df
oDHhpK5Hs1ctPSPtCXzWIFQJkU7HVfpcKL5mBr4cfL460vdWgwZ5MqAuiZeBCDvtZQB3AdJ2ytke
Ge2c0jaabuCUD0MrFq5IfGPhSchBcYNJUVYJsyL165/I/rciCCsF9md030RFxQuBKfJSJs8Yis9c
mRpnTB7SRohCqHqWVvU7KptR1S4mlZfnzMbArpduvcvPHcNutvysc2cDPkTkvW3SPOlgQCr7fxsA
Q89IZPI/9XLyTFmrlTGagMHM2Tos5zWAjfLi+0VjYO4f7taQC6KgpNSDC6sNpaDb2ttDE8u/kw8L
Tpfj1B6sGvxasEpcUGVsxjxOEG5ytk9s/a8iyZliViGXKqbY44tyhv21CU++TBFBS/5PW9iMneqw
Gz+smzlKgR0Rly/Q0GVfSIvEPm83TtU+5QdJsmwMAxHcD3hEDzvhw+alr/6zDcgG0xqxOpLNFx1P
ANwdUVIfnhkA3E6+D6iyxZKGpD4FFXs/++2D7M16ex0ZXlqpZ7VoRvb9o7fkUtf68L+o2cyIkKF3
dPEmqt8nZXJ0NDzJtZlbPI+3zMi/QhnTTd4rdLhixCiO990MiTmdRvD+FtNhqAGzQ76uK4XIBefi
K3X5qD/GEt0QPPgYgXeQrBzgGmN1XFhornqH4vJoqzqMlVWKrwS6vWa/Y9JfYN3RNwG+t+J4eUkz
j62NW03nX/P2ro0B2Q3pvYCHglTyO5wcwLAyGCGnUbDNJQPd8dvgnHiAe6m1ZDNpJR9YUPVUEU1E
MzPm1BKfZUsRDxrmmZ90CKyvvkdWP1XkeIJnj1qKA3k0tRQrYiM9BRdYMbeuX3gz3sNcPTbUxG2U
LXzvZ4LOVo2TGafxRwtwaRStgW2q3WH+7HBx4WIcaY2Uwb/ybGCO6P3WombKC+8jPOYCp6m75NLR
tEgx0EXMsgNfnFhli+fRfJn+Pt/ovS8vYvwUwLOjr5W8jxsTXltFqXVJ3YdfBYMN6MddqwLCVvZP
2YB826NhGMQz4BNkKPC3yXnIGCLhc1gpoE7NGdIpAjpEyC6uJ2Cqg6clmqO32KHojTpCJWbF4Oqw
UWCejt6nFacPdRuMO2/5CEthN5PRKowQA6BVAN/H2B6SnT9ggWa1Z8ER0fEkYXCn5O4zyWBjPCKQ
TWx3VjgTBpWXaNGAcMUWNDzEkz1W0K4+fGG46eMHVAa91RAjxTLFp5CLoIH41XyXfXxHIphlFuSD
mSJDeh0dKPYGcyf0Cuf3Gka9muJIgzJbn4jhL1wKJcr7H/YOp1zWALM6b9hSUaluBhDafYmZHhXn
WJgOHVlF04M+c6OeTuMDhpiFNpkBozcAwMxfCVeDG+ObEC3w2a+P2x2uAS8cPx5zkJ7bcoIvAM38
bEJMzQBwCcR/pg0VDrVNf/xWF5ptxlbUxFioORKsS5LdjDmrWScT9Q+KVxtHa3OMoOLHYSO/DQf5
gwMCWjZace8P158dRbF7UScfVd+ovJ2rOQWyfxvfKdbXGyReh8E1sKiAQaUVVYWEsLX8+PZfugoM
DBvCHwXNFaFlsEWy/Sw+/wXELi9fl+3n8DT0YwYHUKXbaqSA3B8YkgqmACzfuOTQ0k+BPetVYkdX
iQfdET4wLH3hmu85St8TuhgZFejs0klPUeVDaKVLWM6jC9q67RVbyoz5KA83aR4VAVRZhgXAixvS
Vay1mCQT0cxUeE4rmNgY8Dtf6pWu8WoTI1O/4uQuVVdBmrZ/FMEHai8eRW/IrVy0vI0fsQCtOQQ7
+EBdC9eR+nSJcjRrfNBoHKLWc5gi8/1zyqyfAUW9+OYNr62Em/24IFPD2f3edMnZgqH7A1U2MI5r
QXYUegP4d4vkYrPMjJyntF4AFVCmpvkxeWWWbgxQ7zMjkiT2m0AptOgz3jt0h/HERLgLZGJDLNk6
e8i2HNmm00loHoXOlAmMsSGVLcIOXYbgF5/aXwQoRWte09Mqjj6GvQzwAN6OMAV18uBlKElm1G3L
KtBphYGgnB+Z423gC3PvqEebDFxvcVlHgjOKQqCqOSTwrxE1NZZw/vKmHt+bCUlBeRjXeXFYVNf5
QG7HBRXbj9k/BicMMHYg5FwxuFcKvJxU1HlyXGxuAgV15BPwta1MK0Y2q+E2G6zfk5Yz3oW/ukg5
wzTlcGSTcSiwjYD+c1cTO3i+Rhay7onbRdLO7ItPHvOOxHWejOBJFoV8Rf0HWZE9XE8VCgR+LhXw
DqhLalR7ViLWMenSjfM17VepfM8e5agcFc+Ocnb7fLJM5EKfMd7B2caTX6DLGovz3jSHTSXtMt+P
RxALRjuQ+ZnnWhtt2PEf3kESH2wQTlcd8tHgYQU6XCfjf04rVqXWOO75DZv3e29AJoKtt7eyQil0
k4Rk9Z1hHbdf9twfDp/FqrURfoSw/5DG4u1XLmiFf9M6ccG9j7c+fACzi9W2dfoS+ESYF4cyfXBz
kyWv/1BSh0HWYFGq6cjjQX3p50k5EclaewRvdOSe295g6K/ZoH6xXlwPSpcAxFJ2cq4umq02CBm8
9PT9K5V+xYsKUvFY1iqxm57ESsiYzDjWXUic4OIgQP7YPYPq9bKIN+yBxHAccEVbr5kFr/EQTD7g
yaohQOlI6r3LdmPtqEO91KoGM6k9XyOVhiKKvBJC8gOlxK1+QydI0c4fF3eyKB6LE9upszqYBlbM
Ld7/smjAs3ZHBqO6Oj6LNjMcorfhNifWPXBj891BsoE9+MlhR8YRz9Qinca9jQlic2zEBzuWKuHi
m+mYTeMEwMUWC1ftybQob1Tcv32S9a+bbeMoaY0DSY7ogXIhD+pdV+omQX5tck+RKcJO8xrCBUF7
EljzlJfUPaxcoJUbCuLxWBubh/geIeWCQcbF3CHug7YcQUE4TiKoCReJbaVBSxpAD0p3+o1poHz2
WrcnDIXTQ8EQ7bssIUpBQZtWaHiCu9daqW3muL1pbihUY/7V6m7gIGhuewqD1mjHh7gHz2B3oPVo
72tqI+Sw5sFku+DK/3A/Ds+aFhRvtSjUokd/llb0R0jdGmvqocxtx0c0kzFWb4mKaAolhe1kW2WG
lLM87VkLTgMebK/jDpZMaDYCjll4AKvIi9u7IwpQAzRk2WiRf2jmpmK/e8N7+IDdaTN+4rqmChZl
anD/WBqwPZq3MeBUpeArK3J/IFFNGLEW/346uX6/FyOJCqDoVK65a4xmMjcjudVsL7O6JG1qnUYf
7hg7990c1WkOKSYFs2Z0wtxgvBdpKZJ4g7M5LFkoyFIlnXsD4ugx5MzgCLHyAZkE9FRV7ObK5Ib+
+cZZ7v/sungt3fHtJ6OM21XW3tRpfj9chC41PIHDAhZS0+NUQ/da4AGAudv7vw0z3vXLmcyL/inl
wLSDBseri2EwyEictzcGZ0abw7z9bNKyV4nyk/pBusp2eYR3qFgn6jyWrLEou79M+h/dhwbY0bdt
XPghaiXVxC1fbQn87JFFz6ATM9HfQiUMb2V7lk8JdFFr4c+lR9u1I7fHijxbQPOWA+IHPaZZqEgT
3XE9zDErio4YASIofcSVfEF9rWx3vUs344vblIasoOWraMcYGAaCGt5sBAlhGEqEBDbg8JKR+h6n
QmSF59Ejm7K6A7TEwrLQQFLFKyxa3KnsTVRQhqnnLxE5uV8+W3ro/1nY8DKkcm3a2d7qRGWowuQ5
+tGyWHbjoVGlYwrJhuKiinS2/19V9AZwfXyUU5lIKUSlftaOJDVM6YwwYidcU1in1NYYaZm6N1f9
lA3+AVf65dbew8RY4Dn4+h7uicP87VUBojll34Pp9Tm78uUQLM5Ps0A8d1E6e4HMaHOM05zgd91/
/kQVJW2PSgyS8++Hf5ykEzucFOqGHKoXX51sjb5bgJj5jMYBicqR0M5noe9dy6KuIHAasBVE9o2V
QLasms4eejnESE8oiah3UjYUCPlFE0WBKQcrVkbMoa21BEsGCDMrEcImSB7GJCkIgiSxi6GHPXv9
/1FPWauACTTE2+ru84wMeQZqWpcZuQLsa34RF6VWFaAFXUQdjw0ywg0zJ5YQJeuduh1/pZK4j4qk
KAQl0AOVuWQUImDNeDrhKXMkTF1x3B40GfQegYS+HIT4aZ30Yi0tTeTv1wTarrwZ+WKskTZCymz7
QkZB2pblKFLmyHhPZnSlX5sV+TGymcqcuGEbOSIhqzjfg2AA4v5AmTdHa4j41VAbasOZOz+M0kbU
xG96vY4slJoghwJvKJPBsvFnyD9LSB5pWifWxT14Xd3ouunwoxCzUmDZysWkddpcWQgZ9zQBCUKN
2cnY/eVpwaHNYbgKqtYh2zf6AZ5+F3TLRToHxjMQFttq/JioC1EtiemapZnMfHdrwYCdEur3kVGS
yytuXqGVS2IeWlLa3aC1u2/kd0CkbUTmi1wao81zL+gT00mxod2Z0rChxAiAnPeQDEo20By5+Fik
iiZf7BMlyyx7o/oRcPj3VdwzjHyXrBiHJKChO0lA29hrpYHk7ZXqwRWyt3+YiqXjsrbvRR3eZXG6
vaVo1Y7kmSLdY4R++220r0hoHljsfGiO0bdaXaB0a5zaGV28do5fG7m9PpugtvddPSN+IVJi96mh
hmM5hGhJQcfRZ+PiQ+u8l3dVbgRUck/xbp+X9dWdLOpVz36AemyKUumASP2g6fR9s0vWqQZF8uFI
tMiKNpsy6/yX0BqWgc7lQoF4UvFXy8RH3NfsOkqtBLPJpUaZnB9GF3aj+xKbwUKgM29k7l4LDSpf
uvai86DSbJDj794h1V6+BqeoC+03JzAzOzOGEW7pl/9djFLq635i6q/WDQWP3QbSW4bwajcGLfhu
LppN6y3iNg8OvZnMvx+/ngMC5a9yA/pyYBJ7DRwatng7VIRW5t/E9HlwlzNprVmzYMlFlCm90/0z
6hMB9F5jXxTRt1n10AVwaBcWUvm9Es3V80XoH09hHBf0BRSpTq2M7DCijuOxjM1j5M6OJSzgsICv
2ac2RgsD0/0IXuGSDDF66zL8Fqt3ms6p20Tb8To6+jh1wVUG0RYBSNbJ+1sb9SLVtroEz6Iv9A28
La+FEfWiULwiWkBItLgwNhJxzuGEXh0ajoTYdp9jvHT+sXfWqahD1ZoIjljYt8xvjshQmu8yQuwL
/F+Fat2HbHP0RXGkv4Rtt7QOM4D1UQpcmff/8tc2Ig0QKO6UF19FpCCbCYr/BjL2ubkkRLIYYt2D
agbWlWR/miuXKZyr0Ho5udBj83oRLCkrSVIjWAs7PEPkn7QFf2mYjV8B/TmJFZQhgy/SGcjUN9va
F/0wYrjFwVouXgKkCal0Hw0m3KSHHlhM35ESwaLqPbQhGDJP3Hi6I+wTboUKeqFn14Cs+16QH8PN
YFbSvErS5W1nm/g6hrbv5bvv7vwIcpWCkjDppbImKjAkoE3NcBHcsJgltTFqMqWLbWGRqiUmShEO
sWBJ5719Gbr4IUc03rJaq3rFbqc+xOGW49ZdCIHF5nhj8pruaoFXqWliZ/h12ZogIuJdM5yMMELe
jHwnbO+iS9FsY3f1pz7pWll40vVtC1yK8OHLBnDOJ8Y29g5CFTJ8NgyYW+aNUYU1D3xBfbOU0Yji
RAWDY2/yE80ClvgfT6M6ONn3yjaocEVEyY/ARVYKJ0xEOIzE6vf0d883TGE/QSnOOAbnUaSScSHF
MwIgvm2fa2r/DQSDTuXpchb4qKeiWqMHw5hMfm6BUnYjBZFRvMrs9zWJLFBGvtN1vHRZYzTHrlGF
l4yeEEX8uYKY6KABxGovo8EKa3M0n+Rma/FTvq4Ro/4I9mRYCxWX1FeGBhhp3fimFZL3Bx8MwCbp
V8Y2asg+Sv5lhSSW8GXspTniYUAEaQUwJgdE7ODyR5KANaSAP9IjL+PardpSw3hJwGav/95LtLzn
ffl04ukOVCSXzbotJBt8Ypqy8SPg1ZSxKHqWo+OAf/TrRGRLq2Who0AzkGFRAjeUs/7/6oocqbji
9gJJaOltIArSEcFOsbVp5wiGBQ3xO3lOwDTRsmA8cPMkadnMARkSiW/xN2H9zU325R4sZfgztDNR
zPpq0XLoqutsnb3KRPKUq5FoyIfjnhDo9ifdoKRkVThE6MnCG0XVOvuBPOYJAgBpy7NpQrrkbDMm
qmnwcl95GXPnAK5H3gKcW9q40dQdLcIBWtXNaKaJtQ7vdqi7tAdGEWewQE+sqnJwVc/c1koTsgKe
6psXNe3rpRMeub8GlbFiO0ZOOHjRkTcnFf6ppbzgNMb9tEy+0tFjkSjWdezV4E0maPRyo6v40/7X
dLpZhR9pmc2o/1ZWhf0cKFmw2EzOlKQzR9hD3uMFJ99WWwgLQTWsNAdRKVmgwc7Jpb6HmWzy7Mww
4krG/cTlot7d5yz/Hzen47wPt3VxMfA/fBRo8DOwcwYAWaDvQRRY9ep8Pc9VkQL88L/G+kcMNJcP
vQdS8umpO8bI4rRWKEIzj+JLcJTY270Br1iFOrO3G44AuXnwYnBDeX9lk0cEOiN5DQQ/P9mrK7ig
/n71GwG0nius05M6gc8HWeANx/vHB5hzG4YFPHh8CPPNCv7mqABLYzY8AZtztq6IX/Z7VwnIWbMG
AvmgQpysIDUyOetOgO2IBxPq7LTnkaSF7MhGqjDo3k/eJuFtklGNXTFZltTITUGovWpaMIRMegKv
hme9IAFzrGYbCEJNez/wZBHu640l/eOQzkdDfFknN3GWQMepk1rtnkwrE8cP0N0psMIKahEKbZVa
/FMBIsahrz7F5UyuPu48z9hjsVXQuajS9t92WI3XoBfcPmSggNA1Ril5B4+6fN477gK5KFd8OBOk
5sEo5FceP4A2PlJ5GpmOFU0CK6/4FU3ZWiuWkZd83aBcatJGcALlsjhe8D/93ZX4jMqUHg+dQg/a
CULlsf1lCX2KORAIGWEQyp/5h3Gzk3kCS0+jCmXRCbvgTc38QHyjFBwumj5y9o0vj+xJNB4j2lCn
8SX8tp6HJnUNkvyXv1l7r2yb3wHyrhGDkoJq6ttPBuNVFlTFkbLPPOlC+NXvj+d7udv/dz+2U8tQ
UIzwHGodZv60QneSfMlX+GCKjuZt8dyKWLGwzpyL1y0giY3jXoG84BNLALryjSJ5zLYm3jsRSOpZ
LF1UCXVEE2V9B3mcEK4P3o1xF95WOJzD6TxkeHLssskFuR12+b17Gt3/8wlSY+FZ7SRFICXYnYHK
u3BnZYA3kzGvvrnomxO+G/YLBDDRLK4AgMYi6pNXOkaBljoK6epsOf2708AYV0MWDBLe03TehKWb
OKYkopFexxCLYpdE2U+hrLbW+Xvdo++ZBofZQxbYOmaz3yaIuBMXJYHG3qIPlgYAxlCT/ipxLnlU
luHHWGcaZN8woCE2Cpc7Oa3iDt6eDz6P102qO05n2a7WBvldHPiDIwDy8jZwskZlTr/XzLgSMzzf
R0NaNqLY5nnNOa7mHuMPxsnQXIw3pzgkn1T96xzBtTkBFUQEQPvpBK+blNVfYZ0lTGHRHbbhQXhe
DmyjCVsxHNllPJpDCaRx/gTaV03y1vtA/OjxMQW+JAsy5UVG2OxlQgr9SKHkFTzLFnCkBgzedaCk
+3cN6FVEuBhVTbTa5Rv5HxoJUiurB9b6YVqb1hKhh7POEKUL57ylNiByNirXE5DqB7qpp6SSinn6
TbNw7wGiw9qOrcNx9VRvecOw+bO/GWWzSdaT6jZPDqCH5iwEHDV8nl3DTiXynkDynXyTCSfIIbpm
kNwM6qXMi8flVA0IMmBarSMM0yKjJuykK01o/7BObkN4Q0A77lRmhWrBc7ptbO+2l5jGVu/qAvrt
Noe7wF5py7r91dZD2/DQ3pAXnRVs9e1+a2Xdy5hiNIuAgaWrrY97a4Vjcjk6Vh163eTFHWXOsI9y
s62hsmE8CH4s42JlYJRERqyHbkIxv67k2W5d3KZcsFPkO52WSkKHL/rG5iR03I2zmaXFZwHLvyQl
45tU0w+kPRjG/G0zB3zvs4sDYm5y5gviP5w/XQzyl+Dp2lqF8OoEoKRqGHa8JSFVxx2uQ6N5wJyj
1kLLKz1jRQAIEOdyUHSvnjMuioUDp/bgTPNs0D3Wxonq52r+clgMhFHffx7D6Aph/elUcj3mGy82
73fFgTkfWQb0LiGxo+HqR9XckvUt1lfZPVasxL9JvfYYdW0u2yvBufdYxqh6hORngbBkNczw6ESN
bXYS8IAGdjn7yLYGs7JfL9+Y/l3ZYnB95DSUUkeEYfcK1pZ8TgtZN97YwR+40WoZ6tSNhHuQUp4g
ZDzwoebpXymVaqyH2p5hIO5iHUENwHGlOufJJ9gCDoF9WTGPbIpPMmAStVrx6SovDR0lSeKuqlt6
Y4mY6aXhd5iOYSj25etTu7gDTwP7ur4T6Q4Io/Aj+jp8WHt5Q3QU1e83aYk0M5mp4vFi5xbSAify
MYjIf1kM8GDO97J9HMw0lvxeGzCiuPx6QhjqBth/JVIJtp+pdhcGHmtX2oIO5H94CSnGVsXc8NSE
Nc4lsleqpkduRbD+hSEfrHspthcPha3VGJnIE4coRDwddsaIIPVbyaQWF+Nndqmdb0xaua7Ur/h1
/V99iQr9O9q8ty39QPNcQhgsG7BfoBK0eHu5cEhaUj42CQmCTeUNW9qoW8hQYJxM4ZbOeq/CC8rJ
rw5NxidsJY0s8eRXmlvSLvNBPDG+wCc/x8glSlUOTiWaRlhWb73DtlSRZmh77vlU+Qvp7wlJF2yw
+2dQM/bII2Q3YpSGs3YujQIEXeqI8ZfcqqIp2UCHgdt3028i4dZrEp4VMUZs8KEQsft47O881/3G
hZEuQrBo0JxvKqG+Y4LnG1SwhLnzm/mZrF/APtIr2yiC/9OXrJdWXdcamKwSopHJc7D15zXwUwxk
zIGVuVHNNymymbEh8OcLLS4X7aBHhHTkQVEPi+zU3l5hhukz++WU8zcOIPmLGSCaIvu86wsFCnh7
GFvzncjAO9pczL/oWEHQAhe5xgM4zW6vxy5A5ObW3HRc8ZUGmNBCYcC22NvzcPJQrjLcb4mBxumL
m9tc95Hl9+eUeUTrp5YUGVMDolKsTkNHM1F1WxpX6XNYlywhD7KxZByYn2sFwDpcXWsBuNW5leDD
odGCt4RDomTUARFg3yNtmUqmVwOvu5Vy2atJK2pwbCdaHMhWdpy3a8gM5aWI2Zp5rRxk9+17evCP
DvlIoEqVqg60c4ODDijClDQhiW31PoiYsMUJTWpDITrFH4S6FhwdgQJ8SnMaY1YCrYT+JJVI6ufY
YX5chOpGJB6Yw6VnUU91Msmvpv0Ahlt4TB9CRavGwJv06YQ0mkFFiXREmFRr9r/80A6cO/B4Sk4P
yS3k/mOyAjOAjEVOz96uI11RrriqRuiB0KqM5nkcrb+Mus+qXI3YaH+4N4y1swzxWivLHAx/th1u
hsoii8QMBC4L/Sed0is9YVP2/lVoFLdA0CXgPi2o09p6B65KCNdFdTLw8/2fxDreuJP/ZXZpofqw
vQ2/8aveYOLdn293t3JHF2z/BH0ro1qguJDj2Tz1N7T5nFa2PUcAzEQ12aj+fpdZMa/fv/FCJ4HD
JIoeywSoE5j+g1Hjw5XqKyZYsvSb7Lk4HlSZyVEC+uLuLbDSWu9/l0BQxnrYlw+gQA5EmziOL7Cr
gUkLHZTX3b8WJNNNMdzdS0BBKk4l3VtmPwY2ezVYJwaC9aIWNPS92m4BZgGsUiV3HDbVKzSuzLBW
QQBbZ1xOYTiuPK8aB6VK229/jYXybmG+wDesYOt4pQDm8gQTOLhItGeAhP5MdGcqwMqpAcL0YwES
HfaP2ooePuBFmrbfL+67a3sYEaB02coQ3ht3o/W3qsRsafZBKOkV2iV1WXy+cjhKU3owfJ9/VWij
jzpcsp2c5Arvn35EjQo3iOdZmjX70qS3pyzni6xMEV52TSPwq8YMJqaXLSmxEcaarKOT/sP63OLu
7sXuLMsCzhJeRag5KLCq6BHJ2Ltp23bAaJLLeEJ9vqXi2kQgMq+mCElysoEFIIleFclJJFuBF0zh
i8YxXAc7a4I+KWyE2RfHmZaZ8qenTseAHcgvwQ6O0d4mB4aFcvB53qFid+0nb7Z5XKdzDQbCM2Dq
0K6w5LSCa+at/uzPe8mVXMoJRZh1fS70rLAXYrTosF+lQILrGXRNO1BJZe+htDwdIKa9AAiO7r0X
S9ughyULmAV2rCs5kOLpfYCBW/EOvMB0lEwKvElClfLMNwyYqIM8mfFh1jABmzYtZg4AHWVsEMF9
DOns9+p/7FuHkv3xsmRvP4R/7e9yev2e6jL3IqJ2aj2AhVZvAjFMGQtFrKCyP7ofTu0xO352CmHW
6OsTxjaVZV9AqeRrXqJ6YKoRE7kxyzc2B37p7ZkoB38IcVKSiWCzeG+uFtbg5j2+GEl3D1W0K+eT
dhFxqfarmm2yMt4bnq5uzJ1WFP8WG0jCGm5h/mx8jZxooDtdM9nUjRqgn8hzJoq2ZzubXnd4betB
vd0y7Jy2RzisLQCZ9i2h67RJicaYsJOE/9doqW+9HRyGrv63AUwJEtGEAVcM486up/VJV0Rcfifb
6RGpGkrplvmAHuiUVSwMibOH2fTyUNtnGFJIuZKFTesPiCtS6yn8jRxUehOq0oG7KiBjq3fiQHWn
0K1QnpQp9qD6JVMvCE37LDeODvWZD1lLQv3nrq5Qyee51h46Tj/vG2P5tBssdTeHydi7zgcgu3vm
PSfR1PcGAH3gpnFOQQwV5YgvQ05UhSrkL/XEpKHZJTNCS9JSqWLQSMSRuUA7RpAVNXyOGM3e0mUE
XFTr+Foh10UgQ+AywwNWN5jRin3bE4o2lmG0zPTPsU49JOJ6zAs2WP0tP0+uetAKnh8KiRMYHzjr
1+D0Kj3rG3cw4KM8GastqNYcibjh0O65rz7WcWLaZaCMiDUA7XXhuHlvaNkDeZ5+ZKmgsMVxP7L0
+UPA+DlWdzj6dmFU/08kzxyyRmvclpfkT7K83PsFhHZUzCnIH/C8+cd6x8NkeVpN/O+vLQLh62hr
/eq8zHmXGge1vN/0T9B74XXpALPjRzyxYQg/1iHMoWlfAR8kGH9vh7W5CG74Xqkr5SBOfukZgp0+
MiBNdpqbVWzQzO8YDHyi086lY1owi3VUSZBThbn7wabCb76TR5QHQ1N0afTTXB6Qj3Fn7PlIjQTP
EEt0Uva1SPw+sV9LRZCguL0zRD59rTJ3rPJrVMgQhE/HiQm1ZwJEtNQESaJjy53SOZePAnFajKe1
td7EP32/q7aYI8xbrbbxn1jnGe8JHJpwIDF3rNc8cKOsoOkcsT6FuHwrvQBs1TXPHbDL7RfMziUN
t3PBOiJgRlSrve7LsEdmiC0uhUqEqHa0AKMzr7t9MwvxqUYmT2kCCEhz9Ozv9Vw1EMIwYH5rYWkm
uTMgr6VQQ2MaT9emxMBN1leftqnSKsIEF6l+o/E6BsTSUoo4HvEBb4x68g4c9a4wtFDq493IJ+XN
13Q5skRsMctICSljvMVM10fcVELtHYJIzUT7woMSwWbth/KvPeUEE+nNs69bw7NDK30+ngTbM95q
w4b+VZZhgMNz/bYbwpWee6Eh4tF7jKJY1lVq6IDusHuxymFK4lDncbDY73Xl7Jxr4sN4FlpfYQ+1
2Tiz6yT2VEbt9z83g6TzOY7DStcVOPDSTp8PGA2o384/1vmTkjIXhfYhPpiAlh5z+m5ZaH6tsiY6
MWLbB5U5DhBJTE1yExeafhM4+Y/y6gZkyeRqTJeFYsTMTqqG93BUm9BxJqhTdXfA8cLIWgUCnfls
zQr6lsNFfvBjxH+e2agq3BPcLBX7Xvv5QoxzymRIBD/ayTAvCbmd8e6sf8PTYXx420nLhhddUPTV
2MA0NVaOLoAyEllbeUA0etaCEfjceKJ7f31eux/lN1WhNFKoXIiDL8FsSzB30ZISq8vG+LBOHFJ+
pS+qtAZHBZw/AIRfoiHyZzFfNFBpzNe1fqaZ2U8x9XrQGYXGqpwwJ08OjJT47WBSVcU+ob3xJ4vy
r5R8mzW5MM1qXMuJ1zA69hZDaqX8O2VMliOwePySN6vveqFOSUv8Eiw8AjWM0beLH3q4NsOD3dhM
ONGyqT5QQ1qqai8/Hm2mJIhagTJpbjRtlrz5auMUwcnUv5WrAwpCzFIyFremyHdJbzxMhPn3vhkV
wuXiraBTQY8YfmcIUyfkzrt5sjr+NftCwSV41Apf9TYxUBHt9RC/f7okVEwSqP/vFqnXm74hnk6a
LiL2I2criUYAFOFfPUtDy9eZXXVPAjqxL31O9ZyYQtLSvt26KJdZzzlRwAqXoobZr0a4hYs/YUal
mmH51MuNQnyvsReoepcOYrufM12rsxAuRt0TWoizPD/o6z7MMaVx1WxmsyR97OxewkjGxCfE5Od9
Dq8ReWrRS66nJodTxvSeBFlCPVTL20QIRFHnGiqf/yUopJPy6xVJ8hF/SE6+B47jN1q/TWB4Ferp
Uj8OyxCNg6NJYwiMD/GWpfGNdUWNVx0NKtvEFl+Y4gssaQn2kEN9Icpar5RJ+F7yrAXaIRu2Xmoj
XH8yT7qIOK29tAHp5SyBzhq2Dkc6WmCEp2kTTMnV7hTAEPQrf8QhZKcoIlFqhkqAB01EA2xfopyt
oQn+e6NDe14S6aII38uCRShcQNVjMoivVQfABtAv9gk3cVIUZeM6MbXj/h0IJ2HnOQNcBGU1J1At
4wPbdmeocDihPIiQQa1NoFOgRDZUZKYwinSr+2AHKe/N3+3jTrF/n4dxeV/8ksoGC4WBERV05ywv
8m6UhTnfMuq2FneEgl9GqK05yDZvoNEQoQMdsKY3wZcd6BaZTtHahTmISHc/SP1CTYl836ddEYhK
f2d17HqXW0irDCjj6hTIS1CtMjKiCKkgNhKK2tuFxzJew/rnAra7EE885jQnxFQU5qz3Q9ocuLIg
zZFbocveOjy/dfgysLBAlQ0O3iQv0NO+i+F2pLtKtS6oy68/VqjIkFu78Q7/XHjBo5Ho+0LO+6hl
EZOlSuWa76epXbNqyCiMCyHFvhpZpUDaUd2P40pAsAdryd9xLP7EcdJ0dQvXprdHcdQPWkw8PkJX
d4VD6pIRbvgPtrxZt//ijwF4F1iYJ8wSXqwHkb7cW2ks/G3N/IWXoUwKTVOHTI44XbSrnEI+Mvoh
EFw49TlezOFGI/mQIxpF4Ju7D9OBEyZYKMuO7FdsTrGsKRBv5kRQgysC6zl9ClTXAqamKSScAgPm
3X5I0DbilJ/V1EfuSqozesgTmgWoBuVeYoUAtLHxjPM7siOZExsf927Vp79E+O4iCLzXV+CI0J4I
7TU9Ir2dBLEprmAP7bKJafoD00yrS7lrNfcRnkeOw/pDyzrgEH2nMcikZWmiAzQqC1EzbDWcqPsA
XqLtzLy9xnyYdToScMKiZpWls08lY7Y3Wjmy7FcLM/eHzTeVQgfXEP4bcul9qVplcIOQqbReV6d9
qYYR9HHwNSiPnkFWhR+6AwKx9tcbaCh7j20il/fJEwI2jMk5yAI/sT73Q9x8MaSzcPN/ovRLMRY7
cX/EmUoTyGs97A+xLW2ytkW2TbSYfu/nD0wllDGEv9JHFzsyvCP8jFnLCzMGOxBuG9o3XQPzDe0g
2ihPeYLW7wDPMYqSUA2KqULKizPuTpuEhfOefTowoGss5MOj2FNDgJfIceZVOiOQrKv7oy/5ra1m
hfmeMb5clN5Ep/JVhxj1jaG1miBzOZaTsErrOGq2Gq01TkxfprP6CPzZS/9u9Lxirqjxcz4run3W
eX3y2YNt0M+a/dcU996pTHLQBsSBz44Pgxl7uKBp2/pVUcewPYOAtSNwuQUn8RquhFyZPghB0y9v
pj1VykBZ346hmmWeHkDKhIT/DlnXeGKSTPtHwTpkWA6eAWzltIpF+8znRGNGlzu8u+vGjgWYRYzG
iZFlKftQhjFhwq2KzynXVMk4x7S43xoh8KTQOWhIOYXuKGMgYcRXQYaY5x3J7mdjQg8p2t2vMb4g
2V5V0Wq67DMmhdoWasgU9/R3n+7bUD1eUai0E4viHBtj1c44pQ4JIgRS9o9JcF9gUr60++sQ8Alq
xr8QFKsBadClYkizD76wMNVpsTt2LkP3adW9P2Qztb96GGiLTYtjPW4x5XQp7gJkGU9odz+z+Op0
a/vWauPXnnf1zMG51jfW6DQgO/ZdKb8sq4e15r9o8/w3WEI7u+tEaxICb6Dsdi/4ytqTfsDSfLJZ
LK2fRd0DVIV9goRGAOBOJfCyPbKh2h8UIfdNTw9mH8vqzOoznNO5CUkUoWPpM6PNcaVgnHwgEoRu
6nPNE3KLYb8KDmDhq3zPP5feGA8NT5KIfFwg4FCko9Vz6wBbO8zIwO8p/ZB48RlV7MCSThd6jqca
MxmN15eqDactn+9baLC4qfyES/QlPUoWuQGzY2Ye+rMi0dL+1Lr1b5M6CPmGwZdXDCJlVNXCal3o
c9pVvOAkOZ1f5/ZE1qSCJcbVPobzb5FasXp6NlydAgBVc1xUfwDMOxV9faiuJK62oLWVzu16lmMW
z6bI8ve7zpoRSfOGFzUqUx6DhPNMs5IMkwaqV+KdPridpSh7BaN/cg9Ff3pHdfriPe9B4hn8di5z
2CGUkA/AeNgwg+RB4NgDAh5dQTdvNR3szAP6eTWO93GSCaGgzQuE62VQKh4BRMMOe4d9MlocUc/s
50e0rahrcRCqOk7D+qDOuPfOOcHq0HVH83UjR0IIhg1HGqzRNn4Lj7Hj0R4P48x7wnuKFG/HONqT
cEaLMJmhsIWQkHD5qeOX+aAx842e83lcLVa2V8b5rf9z6YfmMQOoK+jTrRZdHqDVMOKbW9zdSDh6
q1TjIoIwUbT+wJqMWWmVqDsSVTKxBRyLNb0LDsKdtxRkMrzuTpzP8bNKK6oiHB/xE44Ew0IeibpN
lA+OR5j7mI2D+vFE+m6cJ5Pagy7w0gt1ss+VKqWzrcFiJKaTfeF6r0UCiaBPjX3xmtZgw0SVVwZU
jJxFIw3baTSp8vVKL5jLoiTBjYIT1e/Dc1Lr3A8y94JgsBLp2Ms9WrEu0UuOxcQYD23NnMETmq+N
BcE8knCq1XIZR514FtCNd8XF3PWgB5gfvMqDcB9svGECM96Ls+FW/vXdOIxSu0uYl0KDRRnc1kZi
GSbPfU1i7iCs3gIvqhlIq7n4u18XoauEC8X3Kp0LcbtBPrpx1FFQD7LCGcu+IkhDYukoAuyjymxV
1PE91GpF2pd8E6zK6pfvVZWGuzw4GnQbPA8h7BTrAXRdCQZjILd68KYD3PR3p82hGtbU3dkimUFc
SRZ0Vlf3b6dKwsvof5wEH3vyq2RDvoUrBgfxnZxNROmHEza2rPQDCXrpMF6QPn2A1c3sX2ZjX7oq
BVY5v5vTnNIgnke0VTcR+xhtSjMId5FVw0ymZgYEpImKFsOJGVa81qStc3uqlMfDIBKhYn04DuLb
MpOf0uvGYQgn99/eb1/x8k8A2Pb/3uGKk9kXw84W35FYAgah0awPj+zWTlMBVn92ONukQI0bBxXk
UjpHzX+RjPGYSXv1Am3DivHGDvmMeZfvA1irZ3Y47dqzG3y+q8QRxfT2vlPyoQI/Pdus0o6HqG7u
jhXN6AiNEQ8qWaYUf7OsA3raVYRIvPd9F9jOb7y3Q7T8rRb/3Fevm7NQskiCRiEBzPMUtIZF0NWj
svQdVHWG4eWLDuOrGhTo6o/20I7XO6b+K3PHft6aFopIl1vv1dsyMyAaq4AT/FEL1m3k4VThay+2
GqOJ2noZXIFXtkEOZA4P7x7ukA2juY0mOELL0yeRrnlrI5x+w2pVPPwBjtcSyp98AQOoMjNhGlCQ
DoT5JG1bzjYXhLMyQdwyzbjuzLmn4duDYwzsqBM9wN0xUi916cfrgptNhrmTyM08X6UWhefFpc1I
hR/Nvbk9O/5URH14Ew1uEJKqoQb1JjJaAA/OCN8M1gkQcTRC9goCX6lG3ezkv4/PASNGSRQVt8xR
3jtu98bi6QPDp2uBKT47epIxiqZ1c2BWNaq6ROu/slpEr4t+XAaC3oiVlrCxAu6Im4UaA4ucPeHn
Wq+4XmTzSEa2c4hupAn+I+HdqHWgae8MOV/jTfzTm85TTSndOaRkLHFacDqo5vxV/ynQ/wDScZ5d
mUGT5zzTYFPrRuRf1DQcB1bC5ofVccBn1+KnI2m2o3UODzqhxUz6VgA2vk1v7ECa+UKRcl0QDU3+
stI12/qYWqJoSfcynXt6v2DjKX1wkgjz+bEs0e1nZpVWiSXsVLoA9xsRbDGAIm7wX60LQJDkMFZ3
weIsN1EQvaIFK8/Rl94iB+WRIFdiC5LENiBMZ4HYGOyPF6KBIU/SGoJKS4jdfOi6pDhrZy/rPgNt
yiQUwmA+NLnE7rtJQhmtVHjSfolu37DIgU36rTA5tOVxnrchTuq8NiMjeDIDqXp4/O8gQXsdYrSt
RFcx23qAN6hafgGAXTVg5BFQ4b4n2aBWiQW+LSsPL7FSMeaz8XzJLmjuREkFStnduu9wKPpw8fIb
NjK7yOWCEeb1/eA6Y6tqM1m8VRvsJBmFJhlX7JVI/Ph6AecxwN98WmzA2tPZpM+fVHEs8vGAr2pI
03s9LJk916kpyjBjW+LJdxWhEAnHiGRvSYodWeoYqQ9hgQt3pLf4r6qE82AW7UTiCLvsZQUIDk5m
54U6QC3VqDreWZlRAlgVlHPBZ0bNCoZp1cjWgr0qcMStYKqCAx1rG+LJzsFRp5Z7fGCEEanMuXRy
1p+VSil3bfo9BQvi3TeE/BDoCgycLo9j59cCFYIH9AKKJivHi37WvCjbaLL0lURnPVYD2HxOy0t3
hE2cegyy+SWyYH8kcF4FTKsGbGU3AfUKeyRWOSlyMHQrKVWiixb0ngZqQgdhOac2vlhiWkpZWtMJ
ZM/E8zurIAev3BNWDV4xobA8B2LPWP2gDo1Itv//BvE28YRrh8NuuQkn/FHgMwVZLDJJL8CViZlX
D9i94f5YaPj/5eQYDSEjlX8SNr2eYbfBui2RHTkXpGPfX9CGCzj4PmiuQaWpV9LYu6iMOEGQNEr/
SthCRZAIF7aHF+iQJKJnR3fs36PcOy8RgTu27/8JjNfr4ZNEFI32kjYvQ2y8YS7+3gAutrHHzrY1
Sqg3nM1nh/7L8UNhwQUVLNAgo3Y5Su6ir1gnf+2yEGOHjXskE4YceU6tbZ+1glUPNYKN9sopS7D9
QAngvSzn66cYNLX9FRBY8Nt3wsXMkL0cx/HVLsFFU12SCgXPl5uFmLEpB6PYHiaEhzrq3JdOXp8+
ggzC16zCuiSPYfWDtV1PzDUCdmHS+feY2SP7OUC0JNeySPQV/D+dlWxYKxuQJ6uToKLb/KsdmMnH
1EqqXQOpgCSam68WbFegq/xLNOaHS8/XcUXNh3zJSO9UPmXiM2hIeJgtjsVCz+FGD1eoNTIJ4VCT
5rcSgAS1FKoXTn7C2EG2p0bvr7sM+ptolgvumMNHu5DTeNy7xV1/5MDAQBX4RwsDsxok9QCY66lo
XyPL/G7UAnf/4Zu6pOyjGalIMNggiinxL/i97ochUAPhtZFG9hjagBRFHgpKIfDAd8RIpqtatcI6
xOX4HHoaiO9sY+lJ4pkqz9MUuHn4gHgklrvzi6XRx5C8PFZWBMUWTCSmDDfx0zoRNO7nTh+PUaeh
ck2rF5QPT7DFV1d8nPd1GcgEcBpsjTCeb23JZ1zZxmABWKyxXcluCc5oYVrdBotsLOsMMp/7Ifuf
g4L3EN8dGcSLD3M/i1B0sLI65i1vAj6asIwQrMDC0v1G0Bo+vd9JnqmLpWjO7qah6ZAQUNZH+P8F
lcGtjFyPXMXcHgD6f5RkhW2AHqQGkHae1NEYQJyS7B51PIUYPKPpHFVgygiPlar3fDVyAzR7fcZ6
1kRsCmuyZoNni9VUlhilZKmdZ/saZiqIrOym5+SNlupcdeN8HZolQODHxrRl53QpgBWo0brB/BzO
Rr62xC7KjMKg21Qfj8QJRcR4sfj9x4BFXu05sIyW6NjpV9bY9t64T2aRwIzWaznNeCjkWBmh0qLy
idPHxjphVX8ZPe+VK1WxVnNBxgetIwH36lh/E1gpGGTPyuaT7WlyOW+JZbI751hh/fy2rordsOh7
8IezUF7lzaEHDAh4HAtNCQ8QEWU9Qac6zc4lZ/cjh6qGz7qa/3O7FSsKbz6w/+BQarhY+gYsy/DK
HLiGw3/WnBUmwpXvyI1ELLmDuaoegLv/17ZktDDv/aCFpAm0WdNgF2PVLHcO5DVO6wnUcGNBB5B6
2haADHiyG5w16oPePUKrzBa7zQKMI3oJifsezreNO6blTZDa1rk+NZ6LGAFOQ/KxDoS2K4DD95eK
WX+wVQl5pIXuNcFKvCYyEsudThCenYNLdq9i8mWlgFhSuYA/Bhw3Y21UgJu9UthKdKIfxPDwoKOA
oxKgHMou5zGQSZszuy/D7awBYVtWHLIYqYyYmFEz9OZOCOSlOz/4WNYZA0AKHOEzRgc+Ea7XNRgZ
BSsKlA80T6H6kqUZ90L6AUXt//8T4QGNYnEm5dAyK4/u2DSXzVH8Ngcfb+GOsrubMYGu0NsU8UMT
FCBFLYxExGyWcu73CL2eVHQGi5qZkO0Z/0nQd4lCebGoQOPe/ApPvVHob6d3Iszy2tU/M1xwO/Jv
JDonUIAuIovExV/DUJ4qZtUmyVLPk1mGI2EkjXzA1Dtfsb/zb3YkBJsDlMudSTnLN3IRbMVf5XTR
ecVJzlAcyzq9qc772L7IjXD9QbPB072dAT7ABfMxwh7entK2OFb70JcDtzJYzKKV872K/FCRCbeH
6Ho+uOI3RvUB7YXW40P2JX6FxbHGqXrYSaAuQN4E9Z2HbcgRScIarKMiTL02swXXIYKV/7WhnOt5
oRk+KZ8TF9R1qOp6poHo0TOomU/ccmBKk/8OtvE7MTsRYcfYGPjEy8edBsjmOlS9d1LF4TEPc+CH
LOed4z6v5nhNgghejAyTPYP5KxV42ot5BerF/JUxMEq9BPw5/2KlLa7RYnP3D4StOIqbIdXjdj3M
2cPviAd42Ed0okistiWzS/Ou8pMi3MTARVOmErD212377ocVS0o1lKfLRJkSvZu4AEUjvsuo6EWP
zWmNm4rdeNo9HBBUQq6tHRZXXlMx/QIoRXoDA3UliG25x9RC1XA+DDnwhl7jtrYntTFD4Ro013ZZ
mpF/jJRweU+O/xD7SwHarezqqIKDUUPNPpJlrEkltE/lNuJlkjA2ps1IHe/qxI5b/wKoD9YMLIwA
TqZsKv610GWiUrTou1UHIRtr+gqDfCODeum6KxcevbdDJ03neu8GdQRx3jfW2QGSPeV9m/Ttc7Jn
lTbGo9xJYKFbHnBu0uYwsKOKOMWc67MO7iVbbKAgnph9VB3KWO6ChI0hpMIAd5gKZxovzhkVXkAk
8xpfFyoUHOt51v7DM2Fw+C2uCser7gjNNJeSc3XnasJqvBTensl7t7z88/q+Kv2N4dXiPMuuuVqR
7X4sbDn2NrTyMND3fLPWfxlOcR+znE0yWFXY5HD44daqhZF9GFG249MdWqtKd5bQWEHSss93YPi3
18FiDVIWtB28XSYvsleSYpdSTMC8oQUsl0TlVXNEiAUqPTpRuld2Mmzk2xKGRdWVFGuSn8rSMR5Q
Oaf5BstcTjEZ5ePMtfCRUncFrgiQc6H6c9mJfFpsitHpiBcj2ZI+eVkCN4/erXggNmOgE36/zaw9
dNJjuwXY1/zfftTqLL6oNYYNqWJ0NtUjwEm+CrrV6BTW8gk9asKGnHxUPrR//hn5NqqacqRECTZD
0SqpOKkI++50ZetqWsLDfxXTOFJPiySzx6CNhZtWQbfjp7D/UBgq9jWiwbiC+mIMN3u6rSe1iyUh
SBoTf/lY+pCjpcUL82W2C6yqwHoIQIl+T4TozlUEtmh4yWuZbF+5ZgNWsgn6CqLTU9KLjgbHczMj
BbkRs1v9w06f3z899xGjhthp20nuCRVTUDo0seO4pKaqUR6032xI9Icff4DlUUnwH8a/7zt+6J4P
vPCldkWudfna9L7MpsaYso8EV0iKAaMABeWQMCAT4iXnNFC8Lp+K7ofOFUYzkRNQYdUKMoTNLlKB
++2b+iEKsddbumuCgua5Gol+6SMs1DbslIeTM8VYshH8BN/mpCF5V7wKjV4eQdlpJqGy7GC5Ok1w
ct/rPzRQ/O86pve4ob5gQ9ZLLf/x/Jo5RioLbocCYnSuS8LYTJ6aOPxftEgM1Rxsx5utVZtGrnhF
UmlCnHN4fm1zWvTRzOMFz9dw0MaI5mC1vdwMTgslKR2vMi7fLfeI1rg/VlsrrG1RfoXQM28LldF3
IXyKMKZN+F1hrkuZxStaJCoJC2ZIEtNQhU544GQ40qdhfFmZWtVnt8KylQjnYskBJ99eAy0UD2Sc
79HhIXmg9mMJAYjrDT03LhNLKcQL/TOYFsmnGOsAUGEjebSS6U2KXJ36iDfy45HcEVf5gMc/vGgW
Zehue8EN95hk7ttkgrrTmabx4ydWmI97FEgdVecqaZaF0B0ENYpCRGVSAtyLNLTdRcI8AiXpOloW
CZTUcHVsw/T1LNUGBjomkzyDomgMZv/sjC7ydkNW11zMU0ZfZe7MJC4tXjI6DHwxAm5odmjp+bV0
Jss0js+9xRgPaVdtmR+ej8vkjJR/nAiyqkCh7SU4lvE01+nVIVTbTIJ2pqYJZ19U4YphecNmDLC6
ZXPeW/mxkaHWzfoU7Y23wczTsmKE9QQ5ztZyrEOP69ugUNJkRrM4aEQHgcmMZBiaypJONmutEu7f
GujisbYubkVal7OZxe5A8wnxvaH14ZbR3RhP1rbk1zO618u4B6MkZTU30BeBxzDiKGGs5U9O9QDo
M6UNsIrDQtjjhTibrMr+ls6Z+u/5Z/4txLOfSIWbL8X68G/Y4qMubAUgwM9V9RkABgDv6qiuF3uF
lTAGDKdfZqKZSvkcDDuSY9FgeV1Gd3EMc+3E+XLKf88x5cpQX4avAQKF8siWa1+F24KuxK2ebPW+
3z4pY64bsquoTNquDXave0RRDLrgUpw9xs/NiP7xt4kuGLekbf1xRzRqDiAK/v1HwCLgwXEqrk7w
XHXKZOemKtQ5Pgh9uvtLKGEepTPwjv0LI0pwkh4CfaoVgT9WoXwSImLLAp+U+AB7nmMstxCzQrNP
ZVQ9yTVFWxSDRS0TkeHkig9faswturTShGSiRnIf1chgm+7OrWlgrODFma7tzjcdWZ1Ee5mHqokX
NHMZxCg2JjVQooTp6Qx+3e0/yiWt+qlJsUl6r2JUnQdq6lXQR6D4ZRGScs+iwoqwXm5CvTf4btMZ
1P6oos+Y3egrPgjGonZ6IbQeNE5R6vdLCM4g1WO06dlv1nqgCbzJr2prUDyzpGuA1dT9J8x5udwW
W1pgENV5DgFIhbAuaSldRix6dXnspXGTPzAz4BvfwDU2TAA+WSnxu3b/md6Bep68glVT1im9Ph3T
cdvHRcof3leBsDi7OYACwYIA79vCz4KMHQ1Wm4vHJc+mo5F61dYPBtQrDKNUSDa0+sJ9tUPUKOUa
kpBzf7HAiSSMTMdj/23QIZ5zfnWJuAZ3mU9QEhCik1MpsID3eRFtZIWXrWCRsyrsUOOmCtpmITOz
Ip28tmgaic2BkfgQtZNaUS4KtNd1bNalb0TrNbJD8ABL93XtTKl4qM9GMoAHSWSVPtXXNwiKsdec
hpvsDdIi8KuypPlxOjl6Qyt/SPYZOajGz/CIPe3IatrIy1p+yj1oKZvVXzfVeUh808CLk4EoTCNo
r04ZQNWQBKRXtYzB8UoJXbv1nSS/Td3Cev0ohQQiyRUA+1C/KZhWsuQF3hrq3U5RKlsPUKpeMSyj
rQWMoVhTClTHgudqu+YJJsix1bEit5ytFAR4lkZ7QcEHUFFBCoPPUKknMAdoKZ2A6VvJliLnJY61
NYcMPyuwfjtM2ArRJtxe9pSMY6uSDjZXrUXh78xbTctlXHzTg4nhv4FHIAGg1zhwhNJRiNPsketm
Mg2iuj+7L77gkgQJclcHA41kJXk5qoW/aeRvf81IB2gb/64XpCjrzOCCKLxY4BFKTqszYcXRiVfU
SQaLOF0Jw5UPct/20XeW9AS5PpSwF50Yyr9GtfTFq8TM/FcbWwfw56J0Qilah0DHsJpOm5cEfcMY
R/k9oz5fxjVbBX3q2petNnUdkA11AEVcluP6KIQlAvmGaZPCafAYvL8+7Q855SIpdr8wXjdi2oCW
r5U1JCQNCL7Dt/4K8GNtYrnWRrA35Wc3v7P+WkBCqAvVSCao/6qKqF8oG7bq6VMYh8Kpj6NjodZo
Y8CWxam8BURdKk4ep25wwroFeiUq3U0PzN3oBQyImVmr1EOHViWSXhkGTNnqsQ29z2KdQEM5qLwO
zSsGlQg2AyBAyUsWAoVZvyZgPco6Kwh5vms/xM/kqf760sJWPxQlTiqXBqw6ZpZduSm4FqkuXbAw
4+X/L8JmbyGCSl1w1i6LS34JYGgWtC56NF/frf7QFWlwixvqxSCgkxgi1Wtv8RggTGiGpZIPp7UX
dWZmHFtBMsli7azy/+V8oWU7qSwrodFdzyxr5fzAthIf6zZpk7ZTGZqN1jCh+YKmc40+JNUdnKcQ
UQ4cLYcYccC6GK7RAwlbjQpsJg3NMGBk+kB5bIyA/hUfiJC2I/pIcxKF5aIeiLLmPocmzpMDldSv
K2DSpjQkPlP+OMxXzlQ5pcTS9DF0cpMFt839PCTAIskzfpqK19J5R7jChK/0kpg2uo7Zjd+ssi2p
0UZpt2IgZJOu9hWwPBGhCTgllkN6xEU9gc3vjahOlatoWiIf72hoJ9Gjq3elkDSYA32IsCzLaAPk
jkKpvGeJ7YYiQOQojFrMxcOPsCUS32EwNWNIfuytOezZXrWoQWnC/0t6ddOOp/eEQo3iN16k06Em
LUD22lq0Z80AmvlBvQkUOSiKBygUJ5txxLk/CoBMv+pMNNHGnC86AA+nax+OReL/SDbtmQX0VojR
vAuXf7ttj8GMZIp3EIAb6WvDoiyclegvgfo7yLCCWZe97TXBO759UD8XmmA2BnV1ekIVR0AJA0R2
ck4fTCJgdgT9xStxtxHkS5n8I8GJwSjIWZ0/qu3K8uZ5zYFgwphMqKnsfT2vzXsEF+CprwmQ1JF0
vro0WjA5SvoTPaqzgeGx1NEUx/e9mBxm7XWGoMWEVWVqznvnT/GesnMyFXvFA6adCt9jAICsUAfL
9Su0lQhqDylEfrax+phiOo3FQNYGVhow94nqAljq8bMhnyELYVOlxtkOmnl+QAknHFYgM4x9XAvw
Ypph3C9cEeEYSY3t4DLq+qUSMCltS5M90jESaHGMgC/6d8baDsZwuoJkXLFSA9/77vCz8t/lnX1+
etjbwjgkYinNsqmMC56kWcQjvqYlqb3FYPN9WzNiLDkBRa8d5FCV3jEv1c1B2DSO2Q6iW9Eo/lqt
ArMr0uCT+b0z1CPt+UTNktBc3DS/QowvxWdSV+lrBE09Zo+aiKQIE6I942tm6+QVrO1vIhHoAzvp
k1ZbOJDn4htRZu7ShFUHx1lJZMA1+c29XCvo07mGYRH23COaDFN/ZfQVWVAJlvXMrnr/aTMhiksA
YkBWv7P+m3cvvKG07/7KMgQ4pppF6YrHSb4VfIYAF6cDptRPQ1C86QzKOTAwYs5SCQk7vXbUPVLa
ay2MDjyNCMy9UqRDchgadeJ+wT1UcSGqri6rrfb2ZpVljcqpuOugT050XvAUbSeHZzcxo/dzWmm4
5Pu9/CyRER+zGoJZIRUOOZXDtvlOl4Lyvo+gyFmE7vOvGbeWWbYkNCLEg19JLP8T2RZ71HHLX6SY
v/wu+JA4aJtwAMm7eqfT514DJd9df93noEGz4QbVOoOu6Etlu0FDV3heYnz3wCba6cmVWEyhte4l
6RhHtwJdRBHNo4qblW+shCJKt2h4WAP5pjToC9ILLX+3a5epw3QYMstICjBJ4BTdkNuBJXZ00P3r
ca8l+Ku9RNnqkwrP0NZK1WftyTjaxj+zi510l7a2Dqw408FKqBggi7/wx/ESlheFQ3qbLjmFqz0t
h+KPIKrqa2R2A6WitVrW8TveqKAPpysVoivt0EchtTmVdck4FPPKtQ9y6vfAkviEl6OBOViNlY7A
P+/ZyjpUgWGp8935Y5TUDqXM0fPJYV+Mh0QEHAYjiLu7ba5c3uCXGCQKLued5Yn9Z5JrDw72fDjc
MmffQWjwxRKOmw5E1ktRbfsFCkF0dVwMWTbJQn8GwTOK1IE50L5cdSyHaoFqpBVocZutK59c0fJw
y0OF21ycS0BEOcudukaNjB6701TOH1d5FjcPTOgAxEurOJex+B4QBEP9VKgKRszawO+1x9EOUWJm
iN9EavyujgBCMMlsQxsq0z7TVElVaEBbJe3JCZMNZmrL8wzX7VVp5N3ji5Jf/niBrC6Z2MAljAwx
UyGBM8l/ABJqWrOrinanPaCom5qKMREORHQf+3FzQwnZe/ReTFMwsLa7sZC2soBCzToqekpX5u+5
edi26aGee1r+Yt9rsxr+yI/dWk21I4dE7bw0ALSkUGscWDTlFj3Gp9VmSizJ8Qt6Y9mTitzb9meT
jw/bRdowdsRW5RbcxilKWOBosfZye77Q8SN8fxkRCnxYXmd84aFM5346p7Jwioj6vk/1RhyUDWoB
Zgh7GDVODOY09jCGc0u2lpR4s4O4sS/KprwUVa9B1sAhm7QuTXavPWlHmfX3Gxc3lljyBwl5Hm27
Z8I12xHNlmOijHIQ3ye48DZkxLbsusha/1yTaeXm+zQCreT6oyKGQvXYIGyt49I2D9RKei1AfUGO
M/EOfyO+X5n6yoANzw0n51UhpbM+GE6wyug8l/cbE+F1Vr1UMeYD4MyU+KniFPuEJiY5FDHXzs/6
3xEXa1xLWU3YB9jIzQW6f5vlKo914ZzSjYbdZNEaAZkXwm95n3+q7/93piNYOsoK2QomLMaKwgmO
B3b42RGSaNkZrIL6iioyMrd1S4OWcpX7D3aj1UMgcyN2W1Ul8j41Cr+ggOeTHBc3gBronTmBBi1/
MeQ6yGie4Kc+Oj8iiRF8eECc42jhctxnbJgCf9GGS26LIuPWo5MwbCffB+e3wiydvtotjViKifvu
/ePW+dJ7CU2puqF17OVeJQe9C857DJ9doYo8U9fXdfvb5uIehgoeqXUWiXXV8Bbk8TKBMUUX2Epj
biMw3y9vvq2F2IMxjzm0DWTl6LurdHmij3vDpDJog9yCLZ5AzXr7EvApq39X0ByNAOv31q2PdMTO
3xcg04u3NNkIY9C0YWm/6ZxBDkCqgGWvzDQ5yMJWZJyM2lGURTVEYjgo/ONQvKyTrv0eosRKhPTe
8QoSnnFnylrqpWcvVI6oibIQhRZXl/uCWqRGlOUokwX9xlu38kl4ECwSeuArJ4oy6qqqhnsBwbWl
kHNfomk3dCOiMUMReoGp/MTlxg4u4EHyGh35hbRwv6AwYABYpq4xIqIR55lkWlHqqCC6ICTvsRL8
JREHcOuQgJV/AwnEfXacb0yji62+Fqr/gPn/yt86aCnasi+VndXEv6FRVAJCBi7K2kKuWQ5v8VSG
aYokduknnGJh9EmoampzkTI+Z1nSSEtVVFu4HsyeDmb396AYGm4zRQQk5WadhJIdYmyydVWCzuHb
HfE+3/RgRkOh/GG+7k/uuVrjP6vFdTUp4+lcowsmZ8xehvsaO5cQs51Mp2201RNYfU6CVshpoQw6
xPtVF3dmj6SzweLRbx4C+39DUnh+lRGAHzlRVgEyKXSCKj76FXW65AEudjp9f5vkLYkApHgEW+4+
6DgpPSdwu38C9jHf2EFuKiQD0aZfZNtU8rD7Tr8porrYt9EHwAxU6HUSzcvK2CiSkE9ERc5mR93o
n7onK4SJ00SNz4AQRVQXediOMeB/NXg1VP1BTdTGaqCsBTFtm+tVPVjwRBGGxbMuQK8jxnGtfDnq
5YyG95QplU/W5brrebetge5SdonTInX0Co8AnR8xvURoTGbtz0n8352GUXxTRAB4WXQlk0noqyxh
hyGIN2hzrWjnltHR22yqJWI0xuPUHfGNXSsCrIwvEsXcxHJUe5uIgv/bgtGCb5SD0KoGQLUe/EX7
3QmU3m62W+YaRLJfJ4c3GjxCUHWxsyvTaUH6SLJd02lZFUooXPQG/OuDCpynpFK8xinpnvGIYDvJ
SQKY8DV3fDpMXBbHU+HLLWoZVtPFnIIwuJZdbFo2vT/sbK1vS+qBX4zoVsCmS0aGnX+0FF++QAp/
ONkSWNl2K5sL2FKjF2+mBNHPX7MvX4Q4L21SyDdkQDkwOujl3F/nG8ikAENJAQkTUxxfbiADmMlz
KB3wLvHsAUlT1m5ZcJxDC2aVPA0zD25s1jw6cVMjJRVsC/NBx42nfgSxfXalU4LSBFX2WMQ82wdx
ruqvh86bHlmLmVIuCP0AEzW5b1wAutTniKUw4sFOn0tftPLZlGVqGaTvQbLfLVpjsGtW7V8R+Kis
s19eDMhKrouk7qsVngBAbAUZt9L0GYyw0zmPQmh+uWmHn90rSuU7oKpwZI4IaghrtS0XcobH1Chs
sBASjApXy41haPuLhbgR3MGT3QsOwCf5YkfZgKdictbDNHPbkCZ3u5k58I6SJUxCghMqS1mnR3FZ
ag2ZuV9CQRSuGKw5d62n7D7icuN7N33Yu1/E2hLGo5XzilHoW/C0oN3y8tJz/VzwYQunjPvOlR1+
5Uatw59v95mZ/qKNZt5hQc6hU8JTLtM1Tr8gHepa4cgfznGFMas6vOeTU/YZSpQzCzevqjWCZX6m
p1mvjG755vzM0k4PAuSp4qavoI4P/PrT8xMLZJqhfVjmPKmcfgEKr8O2GxM24af0MT690f3drFtE
x11Eh/jUOMhYGSdtFw4viC39GX3oAXwbxxbKueYThmo0TOXaJROjouCMtbnja4FMUKdODLa6hZzM
iwWoIEePDmZ4mvtRZPGK43EZDwHBOEyTZbiPxmUYLZVhb6PWB9q02SoN7ffPe2lnMqCTYKqutqTD
UQgR9uLyvOQhagBqhhcpSmUzYAWnJy2yMHANBIjcuTn/pZuBhboMBEn6sJTjMZfIBQVXk7LDd9fu
iJQBGaC5nddpt6quQYjFUM3Jg5EEJ4VHRY+Cofc98ZizxZ9rGyfPpxMWFATIuoRzNHhhQGwUUu0h
TZBB0J+J6Gxfzed7g840IBaNy/6LuixysSswBc5uo9D83acYjh8LkXBTgIQyal0fxGK1DhvJo6+u
opg4Cgc3DWnw+UMSr4qkZLK2ik4z4Bpg+DwzU9WbwDiN5CftXe+Us/vhDy+VHKbIHrR6UFpsm5C2
/0NB4F2dt9Gh5ayToaDb64uPetvA8bZQnCGDsJ2KJQ1QqaeSJHnywJcaIxm82Pudv/zPY6tOcrmw
XeTYz6YewrEVL54w3bD+TKYiSuz0YaF/OKUwgE3F+21xUkNixodFDWLMMR/sTDrWX3tw+s7jXPNH
PNJx86EJRV+SNA0laJFoVighw1IuaEf3mj0aM9Bc8a+dbRom40IT+llQ/S849z5+UwQ0hF59ZaVL
MXsXV3Tv3zGYXIah8StTalDaGUFuMuRf5yCb8T90DBLzBy/qJxUqBDIjI5SrunTPtVMp+y8jo2XJ
4E9PnDovrUetg2vjgdpPmrlikvIinC5Zc0Nbd+yOAqPECc2+GaJy9Cg5Z+7mkm1/XgfS6PVs+Li4
DGnS3okHR4+6PBkewKLClW2ZmFRJeQa6i3UtxK/VhRiCOapIRFrhK6A/9NiqZEHxDUW7jiWY407a
E6cTM7CY5IJKaH0VEMn2d/N91q6hotVx4VyLda70Drw2ywEt/Qd5VYG6SRChp2Ux3gGL6vjR5/aO
tZXWDBbAZ4amKzIPv5Rc7jlxGBfX0I20dV8vT5Pz7r0MLpq1Z4EjaO3Ecg4QpM89Z++/kAulQh83
WRyDx3EdLpw3ZHlHKftmSy5fziYbZ6VYkOZUdiS5oXg8EtksEVpZpxkQS2x/gmDT5LZIEVtbwUdn
xtnf6aQieDAM3BN9H3HghWs40pcLI48ma9SIG6yqYZAi46UbnpvfVeU7SaAypV7ic7Bz5TTzYQFo
9vJVqmPPJPRizAWqFCa9usMNpu6nIDFVkr0Ad2c8JDSSmki/YrH7dJ+HqZCvgcWnv6CWCvHMkHTA
KV0hjXLhxwpzT8JusiKoWsNWtNQbuGkholaQNrBKtO5utY5oHr8Mvx9Hf8EbldF1XTU9DMA0lB4T
2RDk9OBERBhDIefB7UegbSIHFZo27mjDo7zaXsNYWCBeMEYiZ8PLKa9egVsJsXQOcWGA0ZXExoJU
qKIsuwCRZ2Fs2KA1CrsjoCuuaFLUe8F9/44dDhncdJoErsunBfgNvwEkF8YZv7nEL65U92OTw5+P
ZSsh1/aVve0DJL0xCwY1RsciMYPmC5PzopR84QJnSj4El2zqQvcWvDFZ2xO0w6nH4Nf3PSwrYjza
LxGRgv5XYNl1OrWWyMIrQeemGMYdeyqyHgyGmojBSGSvouTpqkyRkg3HTf9Uzmoi2EkAd0Swi13x
36lscNB/1WobIH6RU/ELFW+U5hBYr9vb8w0SS9YN38pBpdSQy1opb7BlAyNa3Y82kjwSWSdYAAF+
f0eRL7uhJJr8xayhSYVbstYd+xrowT4nCmqrYczyWv4zUjxjuh9r80B0pzw5hxVVI1QTmlHVbLp0
A+SMWatPBWdEJf5t0WlTg8ZDhGaUwYxDT6kzsuxlsCbK3KVL+TyuIj9eBaemd542810leab6bhR7
Z7sHII7Ay2Kg7CiVqjUK33NevaTi0Gho3dN+qjrkTBc1OxeggCq+xDTOJ5Ukcuhw61FriwOGeuj8
d6gUnJduiUuJMg/gLeDUfMMuC2mCHAZlGG2Az/GgpuTV7aekFFnsYSPyO2QUqDo9jYfoTVuLj7l4
F7Kpn5N9wtyY2o9/0JZxe1q1rrecH0a1B9NmSYPlAxYIgg8w+0bK9Db5CzN3mbNpzgGyv93rv3Rt
z/dxZ5ML7BBJlNHohJyS5ILxYfR1t1g/Ht2h7Y64Fs1xjS0YkC1mn0NrLQ+zegPGeVBiplZRwkEb
P6YRHWN2jjnNw5rvYp23MbRzNHXtmTywBRhhBJrm0XewybH7vVVd4Ej/N3OLmLcm4HKbtg0J8NpR
ECp9aj6WZlecocrtH+3gGJPXeHh59ZFjANev8nNm62iiWt/7g152wT+UQfo7lEKbmykJQfmpiIeu
B04vdb8dWCXRJ4NsfnXPbT6LF5a8/qD+h7vgvf9F4mm4xSU57pj17pf1A/dKofLuYlAaxKnbM7Js
JtVjAYECYM7n+d2tkq7MCN3keE/5xh4KttWCbUNHBLDtS7vPzAf+wJMSXVjV5Fg8xq1nE2IQNlCM
XobGokFFWCFsXApoppRdVWVz04smzEO0wW6kHdzSTVuW97EMSu1/CcgURrQNqc0++cSG4KLbgB0c
1It0hUUkDF0AAUleCnABiKX4Vkfo+ItsJHDHv/eyJ4fmoUNRlWwCLDlKPwF+NfXbzYAot8uQncie
fcOjvWgaeeIuL2mmIEf6oQp4isp8FQwqf8oV6Sn7U8wv8TP/m0uoBGTZ83OeccKWDaPfp07Ysg2O
6wmfeT/j3gHwghSMuNlr8DjtyhFcojbpljTbOjA7o2Nugf3cXoc+xs763KOw6bREv54ZPFylqg41
0U43Odn7h4FfUwiiGgOl6X6luc+v0m2++ccNeFn/eAsE/9T0TlBNaAtbPwVXo4V+1aVNEBVFgcbJ
Qi4G65FRy7P084+EvgckWTeOCzt73tvia5svlCN3Et9wJ/C1TYABzToBwP+NSo4oYMF9LdBPCbgp
miyeF2oxxVD441QWodYuH+k325LgDYtcZ/EtbGeDMjFDWZZi9lMALQIqSrFRTT8dedO3Wkj/0f8/
bxT3cI4k2pKwXtBiiPn/Sm9rSSkHVzh15f/qOBFSM/a0Bvun1RT+wRT3rdEs60Ah6QQBJAh6DX3i
rF8S9vNvrDACwsMqN4uXR/BVTNoS0ydKcrn3GK1gBqqfRjO6eR/36U3UUZl0RXze9Ysp9M1OgGGW
bKD6IbDYcb9xLjL29E2lZNv5KYNBpBlF2Xymi0shckxwHGu5bVtTqyyVvFJ+qBRpqpadwzaTbAYp
xzqqm0FwR4WGmNcIKqsE9QbKECjacTMUwcDMqz2zkV8sDiCsVUTcYPuLOfzGKyGpZlVscghIKtjg
31TALGEIbnmHGx0uTlww5gPtUPVibtGFNgxIeTw6k45G2nW+d1ZZNNcXQK/qLGFvBGLUK8Ub3SHe
ABvLKrXa6+Dd5lKYfdjNEGVjiCUzGEXQz70WNdqNQ4X+Z8DwUQlY8SN+E6KlV6E+Xv70+CtsKaOw
X3/T3IAvMapIT2dORcKKnwErgpE052yPzRcta9Pm/vZ3GyuVYBCWfJbj6rn4CX7Kc2XezNvJJPhM
CKepJaBIFKoX7T1BrzA24u3oxcPjFX/dMKdan3b6mzVN4Tof70O++ZPuwn7UTzApsn/mbARlXFC+
+SUTkaPG9BSmyb3nkXsc9TLysGx0d3XjLOhDi81WVpP1sUj3LZGP13Q4ptFg7V14xbLWcnSDPU6q
amRfkvaIAcNasQtWc1C+pi76aMMhOG/B/JBrGxxCJsYEp56hyRiig7v4YOuFzdlbhRwnvRCiX7wT
z1qLRYVajUCXaFallVGE7RbcxDMfDmgM7iWkzqDXBI2a6K7fnLSoJcIYDWz4YSDWcDacx7lXACRR
MdZaAILzlvZZbghoYD5uw/whAUxm9utRshiudzovfGoPfVDaZ4ocBWHIBwBq/Or/29tG+iqZFOK+
T/DUDcdJ/PBBFN3YsOplWeHqE5PSRm2swGaofKHMED+gmH7hl9FCSK0f+zuMs7GuXiGBsmnmrUU8
si69B7AQc81LRXgDAKK7O8KO8HkT3VrdmfWmV6Q4uDPz9mhOpRFKGBwnkHF7r19JoGprzoQQyq4o
ttUjHVZRdNpTlmnnouW1V8tEtxF/n8+qc2tQxjA98RWcu6reBjuxudtStdk7OswdupJlSf0n0bKL
k4FTugZmo4Lg0rehK6wXs+2XDZLhdk5TI0F5KwdToFRo4XZ6M/sOsBqIaRd+ZyFO1uA9S5aie+a0
YPpfo7G1zUROAiT/ywqKbmJCC4PBImWU6fSpQaDPVtSeaxYk9t/t2H5fGD1YmmYs9LOpGx6492KA
5SYHT/FncTJh9QtHYBeN0D6LDWBZoKhdeQg+xsOsHNWwgzFN1lQHDCkV6aKhH3TY0TrA/RCkW8qy
OvVYIXH8IToKU63cLVWVs3Q+v+vpPyGsrMYkZ75kM4kM1X6cXfMRFB43qg02cku76x4nVnOugQWy
7YOXPbMucyRBQgJifBuXkbx82ptCHvCQIphcEB6BaCqhbK1aoYyOrW0OuCmH6J1ioinccReNlrb+
UYO8KTNAX+I+/2kqJ6wLfdAFfEMzBZiStD0l76WMs2RtNprayI7IBCEB0dvUV1ggrqOY9zOrlJsO
/i7UrW0lnw/nQ7kMCU2yI1TqMPGCG0KYzDwpq4tUNNLIh2qjdlaijPaDbMlf4N606ogE8ucefVAs
xFwCrIthQ6jP6ZRLw0x51H9pg1c3N5FJUnumysw98tD8UnNBQxCJM2bm01jzF0maiBYmH+/D2i6I
unRPO6n8Nfa1Q08a6mCdsqz9MX+HuFP+ifwboedhI7VXG9pYLs4DxrgzAps2xMs7E1BsuTTf4wpq
TFPK6WvWFpuYzCkFCXSzC14IAQ9k5f9ibd69uQu/SvhfVLKntX2pXJo1KNyRIiOaBtBtygKOUqnU
9CBMbsonovhzx3w83mHBTsD4ZIij0BnKI2ABTWe2oBcGbVt7opqLHRS+OSfMoRX+QaaDyZl4MKwA
rm5P2BYBkLyedmznyadXvGjDlQxDL9sfqendvFQFcYWRIBZHxztT3AklbA/vEDa9zcF5A1Nv/S21
lZgalSWtvbhjr8n9WUFcM1uyG/PNSU8QSbR9DFf4ikY1are3ePtsmbs4bQ6u5wt6Mid/L6LuoRmm
tvraN4dPP81m0eKQWTP8Uyom9FWQlkJW1To3jra+2gTOdB7POn4ivK6uQjtz/azwwRcPsY6wrgVB
TIiOdWIbHayY6IbmKirdLAb/tCWePaeQyfHzPgVkuPL/H8uJkcpmQxULnzLBSJmwC4+yQzhnWMmC
sw1+H7pe38+zEz93c5wpd9rm9F380zrexue3EpV2sIXV/c6peB0TmBPkEmHB/BPafDsCSXQ8thKp
OImX41Y2zBAsl9Bc/DL90YSDE4jcmXc0o2UsokhRJh8bViVao3QzO3LhPd4rNnJt1qGyXVVrEcvp
zVm7caz9Na/vBfA/IKLWdqpV4cgauPhAm1yqG0YRMIyrk37f3NtqIMLFgdMXh5O1DazwVlvnJIpp
iu/A5kGUVhV2paWWTS94IdE0IxSoxzKi8YbSJkSnymbNe9wzn2YmFBVFliFIy7TnOKXkvgJuYRvj
3hSEd11EFb+0IedAHn0+SPdNkYkCWEVZTSx5VVfDis4RT0b5CiVJ7DKmJl+SBL5NULgBWS0mu/bV
Y5d0teq48SKb2LyExNxnoFAUZfNKn/rwpHh5BhfXH1VwaUKI/MuPT2Gk2SfwSl/HEVf3WP607H0k
//3xB+MPVeGT99WrtEGtqICNo2XnRhWEBSsjypEEPYuHiRYNIUtiohUgx0wR1ItmAW6cVU6ZVI3w
xxCenVA/HzmGbVkgBL3cwZU5ADJTtB+47qEO6bVKTVQuD/hTvvmW4QiOv7yiw//6c5u81vvLUlJv
BRqCWiUG8RCcSo+wwoHlvo6Z7goqdoIBhITum7y9MNJjocpUPrCSZKrJelOVtJ0e7B/8JGV0MtHJ
LrkDcUpDRXnQ3QJS57fs503GiB3jgJfsJHxAre8k/z6kc38+8t6POcap6bGpDw5aKPfxVEovuy6O
es0oBBVBqqpzqG5bWkVuvkNmIF2jnfdsnBSw/G0cw6UFu/Dbyb/cBZ5xFu+hjsWzoZPmqcDTBSEi
DnIG8U4gF255xlAcFqTHUoEp6uZEmo3oNBAbanzuf3t4MItha5Ved0Cvv303vAMqdG6bGVTUupdc
MKGz7qgpEuhulFO3q0mfMavLBChibQZkV41qShig0KMXdvtZbxcoW4s6tc6F5L54YPzMHiF4Dso6
ExGqkINI7Y72O8WjPSiwDb1fW2RTIY3/lQeu0omBZddwx3cTKmwQp2DOpRjwx6zC7hJxEgWPwLvc
x5jkGcLV4ttpZDZYPENC7j+M1Ay7gBnGYdhEaPDRnnda0JXIeOiL2oQykBGKG39VsETin/oQHPAu
Kh8Sp5cH09PSdtmqm/KKatyFOHoR3JB1YZ/8Km51DKVM9lKGFqDB4l04doEe/ryzSWAz6y0kU2LM
mWLm6Ti5w9aHwvAiuJfHa7wkGhjecqkM2TYKEZ7+lpIVPinTu5WkUMqfGaKKYyll+0HKQLd8H9/L
FBarM0rcAupLKiaRgQ6moOHqtsVVch/HumXSulYwIgV5XBXoRsDY6AMYEmLgA8aQqRSJ8ryjFV9g
qgDMmfDEhSm24zxLhb+WiHHwgQaMUUR0+PGKV2r26xs3BiB6PMwbXXnMXf5E+2n8D0w4diG7jMoc
EgKs+Zri1uUaXfPsdON5FcjbWIOvqtYsULxD8W/+lQAZW8wxl/602WQ6HhzLlvDdHFaHdUE2ZNGR
Hp6DqFcjSLGpMjXkrjan8xWZePIIGCFO2r0E9nOuj6N4zIa961BrgyM6WenpRxvXXWuqZ0jvGqCu
Q3wZgekwQC76xtOKzPDdScSeyXUu5PcHu01a8p/qJJdD+OVoKIJZU0FLIhOHd7MrXCPbzpcUfVem
Fd97fKztl+RvKZgYKMk1mxjLUfAnpZiB6m2iqn7JwnLJZTgEsUD5zllCFMVvw8gVxgcnflc2ivG3
3SMzxrTLYwEFxRQyDv5Up60w2DycshsOrHpf/0Qx1lJMyjq6NxKZ03a0twCqaeRw81xNcPKIF+Lg
f42Ag9RPq561WvZ2BD8TTrZQ3LjnaJHxf6l5O/c+8pEAV80+VgfRTwhE8qtzINlgYy+JQ7i/97Cu
2dfpmWoFQri2T7x8wM8rnjuORGKNvxLVSveuOqbxUO/Xhpw8QsGfK8dX/qNo07X6op46r0bLlQU0
bpQ4QpEKDMQ4DSEEELx6Ula1FTpTaxCy31uU3IsWGG1Y4WEY50SJXo7sUidqy6Yo4jA2vveA8QFC
/k+EhgLtQ+Wrj9ZLXaXsgQguoElB5aflaAxz8WmqNoGy0Qt3RcnSlMFNvUHNUNy6SH7ATtfKV94d
bZLg6IyVfkLr2s50//vXJVy0LVYzvabCeIWQjspy/61Cd9Him1nr87MXLJsPt049Qb5Qn1Qf96TA
agOMLm8BiYToxXOBxsvUbsA6tk3zH9atWXQWYCnamPTwweWvjkKIL6JmQb0qYq1qL5Z4dJ1SU3Ru
eSs3YfNb+r2P6s/XWLWpTZILJNX2Ws7yWJjD9TTIr2cMRZitpUGtQpIU0HUe6kHuQrkWZaoQydTo
zac2VC4ALTgIAGLMyG8GzzROGUCVas90HkzRsVQJLAVzhAc9oPzbksUOVv8xoN+C9YwxCxoWUaFv
iZQuzs5utlgaMQaYeOwe4s4wbZ3FxyH/JR0OrV3EnoBOrjaFUaBGpxeHAWJCG8zN/9P0t11L+yvU
D1cpWJJNJ1iuRi04RnE2hw3b1IAchNmGYdvGbpat3RymbQQeK43sINF5ZG6iudQxYXFsFLKZCThX
KvIyVyfTWsyIrRXGtE91cSEJXZDFEtoNdxwwkDMIkBKmETZAjd0FdUXIvd4Z/ynWdWI04sxynFh5
UvupS+qsQDC1a2yV8ETBLqdEPWdGEilxbVi7TUpT+IhMeH2rvbgsfgD5BbvvyoAtDR/TpsFl/R7Y
GnhyrgYFgiMmVz5ffCuCyu72rfuB77EH1HztWEq0JUmPAmNM1jGE/0riP6RZWWlTJkIFPaKMIhJF
B+GLfIWjbTo6VR7jKLINGCpCvKICdVxaBTnhkfUCsYmsQ+GfYz9ukMFwvf0+Umx1Mkw/ql9exIKu
68jAUrOyJjq2rmbHBTDpdbfzgXaZrROZdIRxvHidC6yvkazapPn4AXhM7fGTLZQ0oe2fzmAKkxdS
JobAUL10y4c3COIPdwHhbBV9TC+UBdksZSYjAf84HOHk+9OklIl3yRERm8LUUWnmP1FRZlC3D/O3
QvLWuXpb5xRgFChL6GgBcGFJmplTsKUfekcLeVwEeZl/iuhO5ejTCSgTCRdYPSJjQ1HEfH18K5sq
3OeZnLsu3JNd2hKLEa7MM5841mPA6bEz2FG5FX7zHoxsGH9ivm0Drj0TlJGibN9zXn8gqIrk5pIM
VzEILEmiZx7fbbRK9u5akthahVmMe1pQX9QhnJpEM3M2RZaYpXG6sQVe/QtPFS8jf2UIrQD3ku83
rhpmE/Fo6sEcBbO/XhEklqUaKTneAxUpbeijex5UuHO+clWSuXKydlXJpx1MNB+w/ALAiREXZC63
5fx3qm0HApSHZtEK+Q/7po+t89+UGiz/9zMiwPlpbvEEVYEKxTMtFGYQfmKfrwGZ7pEFZ5qK0Mw4
ckU++99Uov+YA+Q+jVmD5pFIrr8KUqrKY/r/31uMvrgyj79CbIzIk9eErfZrvdTR/d2tpeL2pVPK
DdHzvk+bWeNA/Le64rLa7m0HlWdWXc0Vgf8AF4EbY5XSq3H2QX1G0O0LhBWLCFHkqmng+3rEzMnM
jICti994Grfps33SpPXhYUd4db2z440JM92gKgEb8Vap2cbuFp51u1I2zS0IgcEJ4UBVsvqmClvR
s+lUmTwkjHcFFq2Pg5IAsBwdDwe3IjK3Ypi2BEYFEZR3xEkwdbG5QFZrSDB1XGLfPgaQ0TGl4A2l
hePmrk7Rw1f8I+fVIH4fiuOI9YD7U1vl2CR5YUfZfFrsZiE05Kb8FpHcMCf7XG22/DBalE3EWnEM
tekdk9hyZRsl7kFEoEPzKywuSmROf37Ziy34rhqCcESBuWcUnpGTO1gCxuML4elX4XGVJ4KwQajO
zxiO8PRJTBMAL5aTaCL0QJrzfDj3trzWkjqOB4KlIBAlLg1Vh0mJgE99E5gDKtcsQL3/qvPuLccH
GT4pSFHmlQuEVks5e3UJ/WdmeKs+2ywdR4/3vMu9yVh3nX4NkYdSDd19wzry7ZcNhgCyqpAS5SlN
r6xWTHTpT0N/t6k+AWSyu87ru0JqL5y8duuRLWYvDcowiftzCpLnqWDf8YN6IEqPnSl+qbctAnam
d6ucfNatacKNTIdh1tV4TIZz/V58OHU2QF0xVNa/ciYatXY/O8WDcSvAly/kpgkcTzB8fW1rf0fl
MGiLcmwjuQI1xXISLSwqHsNGdycdHtOZh4bRscEGqPdtBz6XilNaLs+bOP44rrjCS5hQ7y8EwBRa
jW5tMTlaFY0XPC+qnEu8ylp8U/oj0d/UAr7kHsbxNqgtev+fAhbRxExYJkoScDPJLUhOJQPZpZUY
9Qk9Iq9Fpz+knodry5OWz4dbh/P4Fp97OcZ2g+FV6SfT3Vf8mN5SqhQjud+SzS2CKY5dmGUfjatk
D35vvjN0q0z57sWCs+VY2UbPcOcY6R2fUmTdf9OxxS37y9VoZeNWWnV3Q8yhB/oxgcw8qhTy4c6I
N5vwWBrkGnhGTdMZ9pN1tTlcA8xhCIx4GekJTZ9+xYXdzWVFmb5/Jw+imPXSAIqsqx5A0Jpv08aB
RflsgsfH7hyaoU/tCez3zT14Ip4lpQcGla3qKqt5f9mlc6Ka3EdRvo+aL4s+Pq/5VwRZJ6m8yep8
V7jEdpogKYpow6cbPeD7/UDjexFR4vdW7r73vHQ83qOZMYXDyQfQ79nAL3j8X3oTZDK5Ahh/OSlu
xU8WGlau+2em+4bwKY9aqkVEF9TFukAPywpGW9XwJN6WKz+3Wk8+vJDXsEJuw0nZIHPYYt8LZloI
yL1dQePPayep3rksQp8fTjYSIRb6p2pL8WquNABexaALgcubbegYdcYHPmnWq0ZogyPcXdQa6YM+
Y6wCIJWZOklQNUkdv7XqGtpFVUrrLyhKnX5KB/8ILCRFnVPkCr/uxB/yWdYNeDuVKWT6+pYeQcXs
8eiNkBXyc0aAa14EfCQWFKOOX0FUIXJxZTfCJfIzykMDGRb1I73HuKq3nZ91o6rwY+HNrR8ryxrV
vvP1+bijPmTYWCp1Il8+HZ7+vanKipyf4TmejtPcwM72VOuYksr2kmEXJ7dfwliNVT0dOwAh3+Jf
1/D/OfRvmrVwFc5WnlfJJVoAWTW9Vt7PJTA5Q9xsrFnZP7Rbe0hhou/AQZhkKxVQHH14xMwGC+CW
RILJycaKuCSyYzI7rofpkDbj3lM6RlRIZAwCenc/ZEVpl14yFcJ59maI4BH74YpkUqavHsczGfuV
+yMnK/f2VjwQV9sRqZxYeK5lOrCPY4+ryG5nEic0l8x1jL/HHQ9gbgLQ214Pkr4CLEckY5XyFzEM
baw9vRbVnroem9AIohh1CEdN3dnXFOOnMvxpwFWPxcRDOlZy5h0LBFq+TlW2nqYFBPKthiSMR37z
vWmRpZrW4VHX6bOFe3OUNqNX/bOmtYyvygglLRPV2cH1F5r4xX7h/W5w6qESjI3WpcWqRvOXg+1p
ShESP2Gwoef5fmtzFfryw3xnS727ayarHq2AiYeVJdiCEeVqTqGxC410Pv5x+q24PcdFnKiXtB4d
EYj+sxgLUR4QeeDkWYOs/wH5ivhOfKgV8qb/lGF5bX6UxtYiPv65jEg0m1oACR6gBDlpXNY0JASf
B+a17YD/AN2iZ5ncNMf6rkBV7PtasPkMMPWG3F2swozFYdD+oDYTwvy1J9M49uiMinWkx/Q89MVH
Y6zv37a9cuKZ40xengF0/RslrzHdKkTeB9ay4UA+dSR5rh4D2j/X63iU9aaJg5XZqmCdC5HZDsrB
3x5RhsHeUVpHMu20P4SmGnLa35qnezh0v8UCXpbSDdaS9GX5EeqU79OFMphUaIBKiE6FlJZ3yssq
jzgLloBhvHcVIkv0zM32j7CMmgp/Qo5xb8MiItGFcqqHVBP9R8ABf1Sqocd0LHPd38eQHq3TZJ/G
3mjeHcqNMtGdIzOiXRN62aR3HleZ7PXnP052+ioV6vix+SesPfKcw0WGkCAPvd74QXZNI1hfy8c9
cM5GMZNyCiIKJ02+3abDo4W9RPog+KUYcQPZ869SBt9d/qbtqzQIXDH8Ak8SyFwdMAu9aGdTb8PN
u43qoRLWYNYX9roFKJHZFrhLx6eiqoKGlbfw2s6pcSB9VEqocD3ASyPCS77AoBZSxtuf+NYF7YYy
ZovUkAldigWeUdhHW9u+T+vs9taJXz4y139Jr2WFG1cNWz2o7mzIN5sF+lpXafvyIfEgTAKcRJjQ
QnUMIyNwM+b+cjc5Ui5c9/Mi42IttUiqCsIGJF3wLMo3ID8E/bdxbm5s/pP8Cjhr2CWagEgBiNM8
FRYgdTclShI8m+uA1fKULg+EnNqVA+UFzZujjGEVe9K+9RECKK5pWokFvXQ9FdMYaqfLE7Kw3tdd
JXFZhc9H5aw+qI9qtmubkmpybiol514+DPRZXu7N7TTx8jXNx9/wjFQEy0trUVWySNEqtwVh3i4i
kNn+NUDO73gU95QhY0wUfU5TJ47lBOeL1BMZTyVxfW8DgVo5RSqMt4ZKXJwoW3D678Nl5qNd8iEF
7D9qDENE105xvC+ZGXB9HLL+HUy44Fiq0pzIGAS8j3eVCWghHWaZ+BCcEKwaHCoJe0prOEaQV4n3
8oRrm90zgPYbcMt29bt9yQjt4FEkVZy0kedO4BNIbb4xAOkTXFh+J7HStl3q2R6Q5+Fiyg11tmqO
hl9SIxTDmdAFv46FS5VZyMuGY46gFz/+3rheKgvI8+O3zQXzVV/nnPyCmGMaBbWpocTJAqF34URz
LwQOwQi0cOuw2OLOAkvi3QO85VWOxHxRP8duQruAB7ZsaBvUAmSug75yrDXnQxer/RwN87kHWZJ9
lUwRuKjmYexixIcnoKzjT81bxXt4Rs47lAp3XGBVoAgi3t61ecI4P1F9TAvMGJRRjf00sHhRPM75
mVc+o0izLbtrjLvm4UKlogmWPGwYB3/mkHFPnuu7KK0GZIr+lC0T7SKQLNPMe4jAByWVvD16jilN
YXStj99HZxkpw7rcdqGrflDaPB2qntkPLimLeHnlAwuTXMADh0ETrga0hdOkmfjomg4WiB4yNASW
g5xC7stxdebWf46clHgjlvFjjZ31mGerJVuv3GCIFWdWFLs4dUPc95rL942uXBmRu67vaZ2rkuw0
wDcXhHq3eDisLeuVZNoJMAXpaJM0Kh3hOd8ABlhhR2q3IE0trkUb+6YlpsulCUOjBvR+QlXftnT8
COWOOQeI/ZqVBTi+3HEzMEquO26uv/zvqDrEYwcKdSNjvhRVc5NXz5QIe6DEsdU1KvQUYWzo8uDR
vB8XAlnG4RzEhXKtLe/NYH5eXmiOMEW4gWRDf95M0V/rI+YlJR7YQEMP5oR6ApfOg9+lwm/v6eXm
odMi1o3XlPmCZI7J+Y2+kEENBMh3NxdPRRKbFY9yNmRWpvra2sNRYsMNZ5uCoTKMJv2qVyeS1Fpy
7GV4MeNX6hlC/jCN8MOA6fxt8N+zXSeAlxW7TRCixA4hVd2jubS9+gpRPQ3se9BS4YNn4nulz2/q
3R7o2WC0nrYTZCHXbWcjSq1ZR3NjgqnZdBrhtZu4j8Ep0ghMmayAk8nreqsOUJ1Id/xL2jWDm59M
hoCHzUyyXIja4xWUHYETZavviN4Y8vsZVPy3q2rF2Aotiw4Ow09cALnHPDA1SCrnnTM9q/69nRSo
3KsKoiXjS6n37XT6097veqza27lOOjLxxrkBLiCL1W+Gndqac29UQ/BZOFldcTsWlhxRPWt0ROJB
kk3IFamfemm3DkRsl4FiIX+JdtrGX0xylwNcE65NZrE9mhQLaWFmTSxAPlXsvpKoR9Og+vSpE8CB
VPA/12yrCdMxRcYiNi0khQ8b4KDjMQpaNXANxCrVOW+/bDFIKvOwNMCaCJJbnbgG3Ua5qOdhL7nw
OjeVj4SEXJ8SWL7xa0pIQHVi2w7ObiEp5G0NuuwIif4d//vGlIwXBR3TuAr/oNIOU8+AovkkvUFL
blSoK4SJ5g3y5bNPoItrQaA5R0yEmGSFJpia5BZzhZOygHJRr+0JQjklrTjy9sGuRz4V/nL9pucH
OkVJ1RAt9goilCL5q/vbd7tb3AZTHjjJeGZxCBH2+zdlULKCzXWFcZTI2d245COlJJYL0OohI5fj
5ponlkT4XoYDNXtJIaiMlNNMJMumptFyEgltcC8JrX6zY+D7d4B9dOA1JrR6sb8B3PReRjJX2XIa
Zwp8mc1m/WlSt1mHgO+b+YVlEelwc6Rlh8NQ9LGfwSK/Xq9LFHPxYPUjtwOLuCHJq6aQDzs6f+7u
ViE4r5ysUwsW5MgYbzdHJZoafTczs6dlUNpVTMYBQDJbf08imnnDaIOYVz0zx5robHBBSg9U1nCp
C0Xg61Q362ZHyq70kKZ3rK3ixZnWEwYy0VGPXhGdVFXnqoCrNJLJd0ZsfC//vA+McNLO8wz0wR6E
GeEzOVTkuTiIF27/wRH6aMK13gAPHuLglH/6HXN230ctpxA5FF4XWwxs1Hh8bE7oDdf6KDfTeD0B
6bRXPc2jIANU+hlSEVprDxz60ncTie+9AU6+J89d7VAhg+AOetnQLPKaq6Oka5BtH7SwqmB3MVLE
iBCVm2oX8/7zLZEwMM7MhjNdWw9fup6GQIKQcKi8OeK049KtX1l9vq/nn1M0FbMSFAeXjkpXHlQm
2TJz5Y4w4F+1JJWYsQIM4/fukmCAEqyjzeNOomRdAGbaV3u3bIejHJxeiL1WG7v3wHepC/JeiMxx
bbRQ1E0Rl3ZnxbYKAbpWnBWqdUdhK0Mu71WPhVs8b4GtBApwvpRa3OJSu/rhUjB22lgi9E/PGDJR
znut9ztyItugSn1v9EJU7JxbplcLKTH6V8hY2qG6TZus6vBKKhyQ4cA21rlTNQbrr/q6Bb18lwSJ
44CM7qCeRfy56pXppYJfmjnu0Ssm61gNAHRxfLDGJrEufomjuqVboNc9AJvqJx63jILg3pUdMthm
lDfE2bKt8Z82NWRWtVV86/DDj1/EZ+70881qnIZnfCqEQxYRon/GvR+WHL2C0g9EyceMOWq+KkSb
tYckfHjsD445mpIPo1rNlte35Szyud7wa/iPlrDHhvE/8JfLIVmF7TTm1bipyFlM58zMuPM2KUp2
i0XBliRTFY7ip2xOXto52He9muTmYhZx04Qg4tnh2Rbm6yDQWRUURo1PhGsnQjTpjSF3ysuGSVOq
FaVvjst8JPwppSVnGPEviqculIueAAyG1oBFDxslQVup8+ytqYwTjkeUh2et6XUCEApLqVbsyRdC
ZqjXYIRDIN+zjqwO3nB6Wz3JwG6+ZOj02xHNK8DZeMu/pkDC+5vGMnm565hnF5/oAs4Wb1xJgLkB
FYxBGqP2JVpf937hGhuL5n7y2vEGkXqRA8tugBAwOwVyNgR3V3ljPnk/HnnLZIOno7aABIYZTkDV
6Qohkyy0fSazdOzI1RmnFxyD7Qqi7j5fVE/73V7/9t0+eLq6gNjvyPzbgeqJhDeqFsdp8kJptp0x
P4As1FxsMBahfRwwTeicDHVz+88UmUQvjsl9zdT2x6lsBtAG6UBithIB0bCcZ+8j51fCh0CFn5Wg
rU7NgdQ6u4sZEed9WhPWYBSWYt44vPdT6w0cxNxitfrqyqOGqWusWuJ013DHQjntAyw7i9czxC9y
o60zoRI+zzICq0tntdFKbmSNwguP6ZIy1QZfFprEPKj+sqwbqS6uULNpiNzHp8ARI/CV2CWxqmhe
rt4NeRyLJCwEljTnlLJFWUlHoEaqe0qzN904BYTb2kxS3gdeVQAE/huHMp+ilk6OHgepXuRIdj7T
BcZbfMUV5MBpp1d6t2d85JJuejDFDzYx/Bc3jnVsjuTey6EplDH0Swr7+bi7j80jKQLhTQunLH7L
bsSs84f6vUm2ZkFMGpKdeHdXX509snfyyepLwC8Iz32ukh/UseE4IHBIIqpBulwNwQKGXfgowwpX
133AP+mdpfs01xC6GRBzM1YjMbzR2LDYDAsryv9imbgRtYgvYf6PxpIae7iHWvcRlz3vPg6gz2gr
881zMmJ1FQ8SjRpMycz6j3QGidlL1KJpQYoi7vR8eP5VuFmos5QM1ZQAch09ZH2NcIF0cvqwaAkF
Ew3nduOyqmZyLHCoV54vm9w7JMox7FXwTTVmSN6b+mCb0AuyIWOY9WHLdPso/eNHvbfCWfO8NAAd
vK6u8NCOGIkjt8GLLXdn9uEkyUEnaHBx1uNCGtasFe3Omkl9ejvGZx7D6HbdnPjF+jESoI224kiC
YZ48DC0pZ0JyR5oyoQMT9oLuaQL5wYEy+PADTdp4IoxgEBD7Ig4BVkVS2tXPpR27svTEnU/lLu5C
izkh98abT0iKtVznJEKC4ovJJlUQ5mmOzuFmUVqzF3RoX3d7dhT2OWBqpRbcGqt7fsUZ1sZm5B4g
IFtWEgNhYJrFtGNMKYHaBqLF2O3PwZ1bDYYFtNio/mGHj9M1//iOQdsv7ztkyaL/stJBPdnItBS1
Jqv1ZkqJO7nTsgfFcoTCM/pHx7d8uwhVUHXbh01DacAS7/sbqGOGWtR6nQgr555rpPQ5uhH4Z3Xt
BAaOG17pkImjSQo1Yg9nQA5JpYtxkXVrZ+lEnEJK11Qxd+khlTfEcFHTZymts4DIWvleFlngjvqf
OuZsqZnIhiXODFEIx8aTwFDeLBNJa9PhVnWMRITvj5C8shHx5Vy5G5FmnEhygogqPBonEpSXztlw
vCOVS17RItnyXEx083r3zY0/PzfAlQbynBBVNfpSu+TwCZNFF5E55NkXEUKNihHti/c9huECBd3D
9PaFH3KTgp1dG6mmnjglPD5pb4gLbEzCY4/wwP81MUHXsWdXKlmU8vryGTPzYmwnBsbauYgds7/Y
a9Lo3nloQ5Iyfco5n5zNI/lBXKCxPpj9unJSVFLxB8Rix2rFRg7FlIArYouUXxPqdkUVdqfDjnrK
gQsr4UCsVVoYi+/3f0cLrwDHJEhEJb6wxq5o/eogF7BfWOTRpmH9gOq9Gfjszpn9alecz+lt8ZWW
4vQgZcE6ZOR+h3b1m1xQNLrluA9/mCrjigrXzvC2S7Vzoy3iO8fUHLs/wMQum5WNgy+gRCW0Av62
LK3BLYWYEYnrB2/D/YFTV3SqLx3FVTEF5g/jZ0/4GMPyGS4I5/L+TKDMpOYCCQyJie1QeI2JeBfw
qAuJHSqHWgsZM94BvPEWA9nsX0xt9IKj9bNYdA6jIN4lx6cRZKveG3QjvrD+cQDn6zEn3yOKSjoP
eYQSRrWa8F2LqVum9cN4SsqlaUCc8WQmhOnmatSquQZ0wt94BE4zD5uNcBeMJSv6Cf6jOpxH2izG
VJmWvslNiA2baWCzfDJkRet86Zf/Q68n6sMF+uhyrXJtjtYr/Gq7RKNVuIZHUel1iiQM091hHC4p
+LXkTbPWFPHENbC3yMaL5nHfej521PrzctYHOAeNGOurS2Z0cY82pFPf/CtympbDXw/fn0SlI/Kk
X0L5vkRVD5kUkaqspfIIxiboZ5oTcCIWhubQP6JDrtm7apWeizhOuSKFlzaFkQar8/Jt5I1+umq4
9lOJFMU0jRys6uwt9Wi9AHOnmBUqw9HsBK0rAK0f2rDIEMGj9UM1gBnNmMEjIfkgKbnmkQHczf4N
gl9IgzMY2OYeAqu1ENCC3q6QoGZBDDrf5KlAXPGwbtz0O3GgoNkVzbrUmozM9ltk/N8fLOH0XuRn
Kf4a7vJmPXTZqjvb3t7S82ZLUuCqmmESyZSWZKld1++VyfXfytxPWofQkdm3YMtl6FPU/+g90DNr
bPeUuJga9e5B1haf63+aywlP6ezY0DYEfyqR2Ip7BlaQwvpeD+lLOhfRxmb/B92s2o2ab2XqtcuV
PN6LECK96dBadAVHmgfLvVafc9t6U1wxHuCDKxLE1cAC4GKMebz9tewhOnhTQsqa1ma6wilPBRaz
WYPead8GJzJ+bsri8yXxKQcBHO69nU85/3e4xQqKhtRH4hPEgWIpthkqguO5Ih3IcKakWC+724pk
3TA1It9wDOI14fGVrDgCp9wW0P9VSwK05Tw6hN4I/8RJ/oDjXJareYhXuWnpf1yhLoUNHD8MmwKj
7LQUqrkCdRjVblKYrBY/m39P+3dxLuE6kTMNn4EHb+Ta4HgcoNaFi2FpchdJoLYWodSQLuSFVo2F
FDtso8rfFgW+r97MlOMlW+konvMw/L1PfhC3tsbGdGx7LuJ39RwbAPUb/35G5897lUvPZGKYOmPb
yoKMvTgvU8woISJ8p4w971viydWOv7N142+UIrlYPurCyfsT6mavdiYUZZe8KflM2f7pjWf9eM/M
PA1TkwjC2hw5dv/UfypOR4RCc3b1nJExJamzMTzdGcnaOI46nrokaBPsOempqqdbR20mh+XQmny/
gyhBx5BfOXiittD7ytFnn47XHHeuh6dyqa8wLLBoGGdjPNCXoM1KchXulsC2rrMNvzDYxGrDXbWI
qydTHygGpt8+2oN2GTNzrRiR1VN3SSIs2tqXxugODBEUq22G2yg3ysY5LJfygmNu04mcgQJ9yLGo
Jsd0Ep9EHvc9jjgsmNkKOgYZ86RnfAZOqz5J6d12jpt9SmxB066e0n7Df1lXY/mSFtcXboLyKCBq
B+vQ9YjxurD0uY9SAYlMfSbsMUFUI0yf1L1cddZCedvW0vwKUrnZMCigL9QoGTuRD3GbB0zk4t2W
lX/LM1vsNfAkLHK/d7hT0xe/HKKD2YdzjjaTQ0zVOXTYY66BlGfkKyNcZTEIzjIoNu8MGnilHDXb
Ykp5mHqqQ6OP14ZJNmArXXMrokMGvgWHCEMGZOtxJJMaCPMsmI5O4xbttIDQF8rm41q3SH2Gbkrp
NPWQRsT9Ilp9vTGY3xlZoU2KgXtIH+M1o8QAdmxCREef4cNo7kTyq+zFWWTeAwY2Pxr4gWIwux2i
FFW9Ocdur7kEYz2XHgvxA1BuxqO/yM/UrD4I7LJD9XPoe6F8jBkBj2fzFzdQUgzDcPABKePQOn9l
pQBBT1HuwyhD5VECXtjIaqLpJOOhvOTW6Qab8w5vzFtSrJBT8i0tbXynrXoQYz1eWzXDkCmze+1a
7Ap33Sb6QFQEx34C/kKQ6C/raWgyqOXfH3f7VsQzkavyjnteSfxdz24wUvSZrVkDgRHstiQ16uRd
RWx6utyCPBUyBcEDPcPAEK3YdVN/g06VP7bMnzwfOfEup1zRwzIkv1ZCmI+tHMDoL+REMeCxiTNY
Gq3VpKVxGVOfVgICMWoaafdoX8Nf03RTJ+YB4XvQIFZ25mQFbssDUyNdLUE4VNxMjYC4jTsjTmL+
k1LiVhx4kd5npuagS8umF2fWLESyqIYdNdvLFUxw0Up5UJ6zJJe6wBfHSijMYbpXPDDAZALEtKj8
rd3qcFluCuDiVXIEeKxGFjUtg5QhZDP410RfO2/QkTpJR/RA3bJZO4N8yTgC4LEFYGqQ1Ned/c9k
lEzgL/ktmZFHAzaBBusu9a6abFow9Nhu0vg0QQootqldoRP2In/UjO9qPreHrAe7T2kosA+P6ctc
uEeb2O3Bu42RRNiOSCMAaUzv/VeKsNDF3IEYd0ghqWLkUSdqPPq2oi7m6McBcHQvcpH/FBNnzOEK
wFz3TOGWYa9TAbE1fEKTdyjU7/SxtNpouhPO8E2tcFHKaSl5JpWhojTkDLfBrHkEpWmZrD993Wgr
Y6QWocHGY4Pp4ToYh9NlCpE0BRIfZK6JZh43kZy1DKWyU+xv8FFidNa5b6HdlTqTDwPOB/164qXg
xclccJVtsOZZMH/+Zmz5Tviygrmo02maeFZRB3TtUGhzis+4MUzJgJiA4ZjLcWl8yV+JAxcwZOQU
H75YY/6SGK73zFnZg18o3y49ZDQDpOfgozbgNYW+GhcNw9VobSx/wMvrzd1habg5XQLZPv7YdwX7
OeqY2xVirhNSmU3AYh4/SnBs0EuVEp/SrkvuIylGEvvLiG5Oq1Rrhqkl9AteMxwJYyyBFuV9GsSZ
5dvGNiz3AEfNe+udivVlg/HI6tplZ2PlIvSbQ3vzm9ipJyLfnD7y7iEt+KYBn0KrJXwjV90OF870
raIsxyYVOF8SdPhTMoWjI1a/GnwaMvtpuEbNwe5Fi2It9BKjN4jiKopFjFspszEvIDZ2rmIFs1ve
urvk9UZuVO+oyA4Elmig/PUcixUs4BcrJDuKiBZViEpeFpO4pzkwbl4yVP0eGqnPmkYhOS1AK6X4
lfbnFGcfMGClAYex0uQu7ZFXHQcQI3778qVMsAsH7/XDm5nJqBF59vGcayoVCR81Gne0xpi4oRaZ
5p0AgMjrhlN/7BSfGyU6SEa9VR4RyuImghA6X2fsgvAOKoEy+oGbKyDXS9pVuesC2k9gq7k8P1OZ
S3A3lBlWkUqiYKIEfRfU6GGiys2/OyxnuihXf72Zudd0TM0ldKaok/yQpBVDhbJJz2BkkyFP5qQP
OTzKWPZQHprIQS5CSxXWy5VzXyQ+28G5yYo8D/p+DanpsviVkLQKoCcTCdgQZ26gPGcUhYy/tMmr
POgerG4BYVVcHYkYzvGmBPuA+nWdqBva97dXjdd1l1qjB/8tAOlxlfysXeea5zJhWk+E/bN40HG8
7jW1wzobiBdRWioVwBBa4v1i148/UuHjZJc0Pz6/eaXSWb2ajvjnNX7EiX9uYlrtQbynxTiAaJQA
K+tgEJ8exO7g8TcNSDBfBKJrMhBvtWEG1Dxi1K5hkeiTVdxExgHgKiNT1Xs9Y+KZbktAgFnNKELt
c1UYzKP9tVBwJxjo5NEdI4VpkYMufCBMgE/QFAEe0EsFf2FUtyqQX9t3nlSb7gmIQVdxynmmt4cW
57KXwBVU/AALO+SLdb4Bjp+pZs7Sz/CWCJ82CcDLokKQT81waTES84aYvntdw1n4bSG36LfOKlSY
Yg0tDEZyWD6QvcOFMhxafI0gJtitj4LiaEs/aDIeiRn4J+/9A7yw4hi+DR03CQcIFGuZr7cNkEY5
E2ce0QPhiO7JMoQkx4vHY84Y6yjb/7dSGbS8COd+o0MDQOVlrnA5aIZxNPdO5Yz/t7SMShI1vTgd
NQ+yV74qEQHpX4wu6h+b25YwN2hkZkJAS8m2f5+rxxUyDuvAMM+YCc74SeIZiukXXbC9Fd/rrfR/
k5bENl11JEwhe5wsvXyKI+eEObkGI2HyLpwtEjBWMdhXCHsKQhVFstsyWVFTOxqUuT+aRtPAorzZ
cGt0odwvx1TiJm6+KcwObZ5qboXhwPGfnZLgQt266EySWvYatDPk5hw0qi20VUWk4TJotp6GfFVM
QIRI6+IZt9HGOX5tqzQlvJRn/kRuSWQ1/RSwclaIJCEfi7W4GPPFM0gFuhWK3HKBuQpT8QzRl7Tt
2rdJeZpp8CsM3VZYOOgNBMq8y5sy76zW/fwNFE9ngggK9sAv6zPKWBuXXqzBImUv+2li1nEgpJQL
k4qb/5CofAJ/6iDp3XsvBD6pRUcsHC1EcqiAkqop3PhzUrhe6x2xIy5oUTZk23yI4UPdbHe3VDYG
0X+PuKJDPEARElQvAfEnhVrUYWJpP0u9eAaUEQyTsuSSsiGN2ktWcIBTglxAWMLvv/2nJO52JNSF
KlfK8yR8gnC6jZtTH3BqgKNohQ1vrnmOhtXObconl6cPNaIUpNNzANhyFwH+wE9OhkF8jq4+dbIb
Nqq/x0+PbF9zRnwRo19lYBRHhufNN3JhxaDcKXhMXQhbu0M1nqpEu3R9FyARtPpWGurmTGFZqpES
akmaY838uiWTORfcnAMEUuhoqt4CbwblI9msydlEEdOpAgahXMlwFYsrPAztvoYhzyPUHAacjrJb
J1n05wcRSgBZ9jNn53s6+NEZXlivq+We0HJCWyBtYqqKV8hQlCD7w7MFAMmxOTATXuQW1QR9Yah3
KDGx4lV2npo2+JYcB8HqLRirgw1nil1cnL4C1y4pRL6ghty5ZQbPQ/QBRyS+0P+6xYZ9QpYDytsm
6+IAwwSX99dOH1+rf5ejt+z7vyOEX7KC8+ryPEjnWLc2fpUVCpU8DkrarweRMRtyq3kcGFNBo+20
rKW5VLF+JDyNryIdYbcnmYrk0+l9ONY6W4Invotp1FAa62DxN1BYm08UrNiCSsiwgUAKyi1QTW9D
s3CQdY9xwaSUe49+DLGiYUmHGe4MuDX1hwwOMM7WUdApan6Stzyo/uVs4+jF+URVztqFChxBio0z
Iz2A/wc1nAILzcmLr8+m+dD7Vi+mNPGDHREx4iOFjTs48az6PP4/lMDwOBYT3X6nl3eEYC2knQp6
o7tSr3j1iEpL9Njw8unnmtmYJB16d3SCltorZpHICI6/ZSaT8WaSNSCOQp0DpDP9C2IE8nnZXpYI
vLvn+BRLR+mB8m7lUxO+znvoAeHLYrmjCK9hXekEaQjWFA3tYsNH5Q/vtdhuIw8GAMzauXSUVET2
IizAZLR13EPCXeP8I88N18thr2qycayMBF2vV6AKjR+i53N/kKppADxzHyitiWuF9+9Qbe8UMhKA
AcwOPGpPVo8y1ZVSvVlDd+cQmH+j36kA3Xrgw09G7Bhws4ZGrtbtSpwRPyY2ELL109VZ7ngDYTh5
YfnsSrbRR4NOEgNPXuYb024k7l51/BgYFAuFAJhjBPad3+RAbNsW0BJFpK2QnBxQdFEpdk4hHJdx
y7HYlPVT8ii+qZDRtLCglIr1RxvqVqoxBCNein6NZg9EMLtmCqAhDDv4LwTEcypvVmZ6qD0/f9jK
4IHAy7VvlKLYdptSMsPfOuleasoOeH4oetMwFDZqqTMxBglQ6ts0RqzkOSlkYo1UJ7cZUJJIZ4fP
tALIa2QInCmbmPGFM73s/zDksRTsK40PpkPo3Bo67qFuItM/+XIxRyw1jG7rLIkpdHnd85P8ls0Z
l6xRR2j3WlwfULBbRW/KegVVAiXJpQtpXP2hlKxaPt4PvhsJ39iJK+h2bxtEdM7yVAZUuHydfXmw
dB9W+AVrIbJwPA4N82cQEDQGi1vTQfqApa2NfX1RgHqFItUBB/HHvGb6HqrGoCLihKMQ4WkirfJu
luaLd+uljv2QCAn3jmsAjaxXf5rNB9Ofm2IqT0yAcxJ0XExdIsFhaeae7DB9J/p9mRdydEjlEPmN
GBOAiZhoNFPuzV1hES2xdv3utjWxii64KkwFGn0mSAnSG68fz9zFJkUVjWKzZaB/mgqH1m62E/cD
B0YK35ENDM6CobkM9LKVeY6g3q5n9AuvKGo2E3MHcIDdRGsqcwvVEJHgZe5AhtEkICE1D0C+0vyG
0vqdQw1jDrrHxXbgeDZivXMVEZgf9lWYuDQpXXBXb5JhGpa4JRGhHH480fNE4uLl0/m4+cSKsOuR
pEljW1gM/B5rWl6OihoyP0BngHlRUDDmHG/GpyAgV0A0F+Tyc4hisb5+jH8sIL5HmIzxYBl0TSvU
CTvUQk/aB2QmlXH1JHtQY0QFmH41lnFjrkUwAWZ75F0VRFTI+5bw3kG+mSdtY6VDdPd3zyKplIhw
MTGV295pRpMfr8yD726f4l+f7nzjXbH2H5213lkf7HxAIORtaVPBxUtWTn+CC92l2Ubh4o3f0Yh2
L6peDUf7uInpsre6RF2rYNbxKQ65aGygWSeBkOL3h9PuZRfp58KIEMcCEbP2Se9qbbLwZrVFYiGm
N++cNSa39siJiX6HQonhn0spSzy636Oy/O1ZfCspwoJdsyl0R+9paQsPYicMhZ3cUzjKugto2bSj
iTv9xBxsbgPiY2PgAtdrl7Wd8mye/gD6Spt6REB/zLNxETK6kF1Wl/Ki4E1ubaWnff8zH6sOfthj
6ABUdSa85H50wXfWSQLuX+PtHQ0kL1q58AtGgmnMJ54J7dJPdnePA5lLROklM1ixCM9GhhuGi3iF
sdeaXirbszLM1TLpdLoPQRCJlJh43Tt6zSwCClPO8feW5GZRyyvnYAzFLb42XHG6ug70lW3eI7h9
eUwjrFlSueSnSM66S9lPch+/eExuYJQYnaF7TetNzj2UqaeDuxUFgC8a/lawo7L/ZElmQFYD0IaK
NVN8IXPsKPRSopjJdTDN0KZCFx2LGnnSACRsWZfDmF9oE+CPyAuZnavnzxwBrOhyMFSRBmHMtQJX
FD3Jipfz81gvqPoa10zWOI26dRXtpa9yeIBA90S6YlAHAxH/X4TFHda+0Z/h2fIHOwOkH6YIZgsO
aetcxsf1YjyruNeaA2I5TMiehKkaPR4cAv/SSqEQMd2vXT/O7zcuWsixWp7uav6QwBmmlOnz8q0G
d9wQAtpuuT283zVp05CmBnM4xzuP8iaSUT4Tpzh0InF/fWNFIyMhMCI5J+ZshqoDehk7mMgmy8df
0GE1NFeWfR31JRzxSlInylRZ5yE9f6gJkQo36m9Cbh7ZR4+sRnteVOEpQuT9Lv44T3yYNhA97Jec
9+RWy0HwDPLJtQEAysRbs/CO6GFsZkSZjdJo7+5wwH60CQFHIsTXOY1z69y5uJxg3z/USds0yaz2
6JLSFT40ZpA7t3fD+pZPBTUt4IXTLZzV2y8o5OEGcEXKoCKlDddQ2lzB0Ykz65R0JHiGdWx46Uvr
BcO1uhLH5nG+PLlOOiJ2z3y1B7raVRSBshrofQjSkRk2H0uocYH+1nQeZg8x773JKBc6C5NkVBEB
Tzm5TmUPS9b/BC+Ae6TtxThV3xJhusb5vvDtopycgmfh0y8acpc2HTWP5IPI1oZo4m/uCdqlo9F0
6iQxqu2t4c5edMsK7rnTJ8DZ0YzVWo4gwrw07Tlb+lWHraCtEuaRg16OP41DUI/uC+YMP/nbclrt
GIzvgvRGWpZVTB6r6IhBbfeV+x/K9vB+wymB8Pvb/bQZcBQM3MMhSgPgJhj8M4LKPgJ9HGDmQVXz
EV3yfRhRTQydp4mBVbP4DvbZFy0t4PYH0HDw9O/0QtiSWVtynvrdP/6fJAwvPqXB/5Ft1VTBs0ST
ObXd0VHFxPFznhC38ssyBLj/xBMos+vhKSFuhllS+PqnDxArow4tiy0/b+mwms2Lokvftpa5zdaN
Rx+yoK808V26y4fVqaaZ9Sgc+EU3b1YfQ62jw3TOOrZ6lZTSPandu++V9jFKKW7tPcY4s5lurANt
ME3zEoopbpu1nqFomAcA+VnbXhiXv5Jg6lhWwPhz/nIu/ja1CIsSC2XmmOh8lDdSQjwrXCSQwzhX
Dsfav+go9G+oAOxyxBC/S8tAR9FlmQkHJAa5P0bUZzrz0GAa7i8/6cvN9CC4iFC3ZKmHDXgs0bIl
pFe+jaSjTF0YqaRLFqYLPNxWsLVqWAO+s6je99ZxGEmi/pS8A875mmiEtXZkq/7l1kmNkV74Jbab
4toz5t0Dg524yNwrl6K8VcdXU8tf/kYfX2ymcnAHoeqgprt73D6UVAxhXpstwfJ0CyrI0/PVY8ZU
sQWkIZI35K2DybXNpST8PtrLgq/NsBxHYfwwXoo+0EIW1gxUllq6PJKzf8+KYbuRrOdJtC1mN8Kh
GQzjozRKpBi1gI22blxMT4ymFSFkSRTtq5AIESb0cCbMiUqNBEEaFLzx5TsmQEYVQhCnBX4S+WSX
U5fj1g8BzpAShleAxgyzbLr/aauwrvHWZGN0LoqFkuSgbI9k4IasuCcqw76HN8h45Cbapez9k56D
KkUzHBy/XDLEqO3qKlJkN1g2DxXOkrtGKp77AAEU3RxckqyEvUWBKMUbrIcEJASemUpEaCasd6+F
YFneQ1TUJz/wUuBQBwNzC7+/0wG/KBdYnztYOcem0XrX58+O0jMghuaDrS8BTtlzhVtWebh5OGk5
sDTDVqsIMsxjn0SfxlmVjDCPF5vxBNgQvetJb1yVTebEC1eXUGeRBvJnIDWKp3Ab/yQbuTCS+Q42
vqgBb1GYDz7jRvLfIfbyMPwlfyVIT2Pfw68zfg+CNQZgSV3PGa4TW3jDhSpYrbjfBICbqtBiyfuK
Rlw4xJPXnpNJCYqIttlWo9sMALqno7NYtgBl7WcTX3o3++1XrLIyNdkITdvy2Dx9cEC44AehvJOf
KAjy72dZhCrUqni3cv5KNF1XAa+n3ADhs+0ITelywFDJpVv9LXhSS+a14cHk+FVNcHN/gXq13q5I
5MwwryTDoZr/2Sj2OjxmC3fmnUy/ER1DGvTt7tAs74WUxa0FESwD4QowAiwtdMGxs3HsQRXgG5Cx
fTHs5uZNu/ZL76yT8jiFxp4ckK8NSIthppezRpAn7VNq8ws6BY9jWKuKwwklWJZQXAlyZcobcXKU
ZdGVf8u+5QFHtNFlTUVNVuhk25hy2yYAi/E5pAPb4LJtrlEIYKNrPS2qpjy+lQ9wfsusdDCPdlwU
H6pLGN7cAMUeo3widQ5DyuqdeAlJ3Vq8ZeCE+Sz9xZa/PalSJhhPmkroKZfzIWIaOGRgvZdVRzFm
oDIkefbS1n2YiBaevzqJGzaFl0BuyANXtg9aavk7X/nkBeqTEJ1q7IwKPHsWAsUJQfSwQ021ldB5
wC08apiUuEp2HYbPqU+hyUn221QXhIJ+M+sSg/PrKxnk1P4Bm04wzudMFAg7JuqW/vnMtAQtWLIX
/0Pk3RbTSGAvOBgw6iujAgWeCi2EDRHHZTE62gHFR/gdEGj5wySSe5XIOJs6rOm40kPOlIJw3WVn
SvIb4VIFR4rJapOWeK16PCUV+TeIWPK+X0JWyxEq+7VgvaMH3NbfXqom4tIW9j7w4GpCGeZQ3/+Q
NtnZZCVlHZQBBJfeDpvg5PUIugiwCjLgk6Kl5+rNDsvnb0uwNE8HPxDQga8dTShg5GAnQpCLcYxN
EXcpM49TJWpaEKhQFzXgRYcrKdpLSZCfSp99gcoEXGqmAEK9l3g9tVDlg0QGupAhoa79aIoJzv6i
mAsqXgXd3gU8Qbbrlq5Wj/3QDo2bQArwiCrd8anc/4nAyqhPT0y5RN8bA3y41o0C0dj/TpwTOaYd
LEPsOAHjEuoJ/0vz4n8UmtuSONmGukL7l6gw+3PKGEMMol9KMTTaYrER/QAw6PlgcLVQ20zQ2hb7
X/aH5014ovILMxE/055PX+RDyra9pLbwinh2rY8uH66ZanwnK/ORRfmQ79haaBvo58nEXNOJgk9/
31QGp4TbOfnXPEDcaGSlZZK01b5mXcgQTM3csDXAUSmDNhPRYLfMSMEegOqXY6trGkj+bzcLMyFk
QyjUGb6zlXfk9/kmIflu7W0cbtiS8UVKvchPK9wsFull+TrS/MW0rMsLli2GKbgyVBgMSB+glfL0
/YjLA2xHO234Qhs2w5YyeV634vGPws1cxYKnY6lDsh0rnrUtQO7cYd8QdOZgPQdOworz338vGCgc
Rnl6XvDoxV8YMH9Z08VhZdvmaqO6q4Ewoi+Usa3rvPO2jMtZ9ukdXtEl3Vvx8kTbeeoSdzdXluZj
HfbSwPbTty382BBaEGH5FD4KjbPe4LUlVoIsrqCHnC0kyVSsS7k0Tb7TeAr3MtShcEaejfHw/927
01tdo+ua0TdK8zomQeFAVSa2hVnvKNybExL2Cfja4B6WoxXTOvFUX1WUh63tjmDa1Q5P0jOZ1pvU
Q9Igsxpq+QuWuUJl4/7csqTRKK9y3AJlRMvc6EY1SKjtISkfVAsZc23OtHG4C8wU3oQFBCxzDNyq
8LUV/suANdNaUDw690kE6dDc8KU+83qTgSq4UQQb6/zOm/xaG76jT5uMqaNfZ0mUxVGXnnm3YvY9
wNCgbacI4HtBzInFyJJFI9tUubucn3rauVxuSto8/Gzncr7q0j8lwZhAJr0QPhrLwUBdUByAuypC
a/0ydjgItLn6xKsBXYDWsQ3xLAjK28ZEkFJgNxrussWeMT+41rLZnZ7LA5dwaojIt647KGCxtZos
jmA6VwdyhB6Mj3jUiweV+mxOqboVbXO94GJJ6T/IjRyVgj433BrXisd8ux6P2GSOyNEzPCaRZWjv
KGpZi0nKAe25yFaEwsmLAg0deouUZ05GgZfxjyBDXhAqoa3t6TGuXM2jApMxnB0EbCqgf5Hm52WX
DbQ5m5xupzL0JZUcv/NGMXGcbW6AgFB2O6zk0T/JHc/UcD45TyyyFOXceuJruIYVLNYlZZfFKFuj
0NX7MR92STodmWA4e9IKnD7g/IKnxsL8v4DR1u9cmelMnM8fZ08Qk9RUmLEpE5/I4cIMzjiMG/4t
RYTE9nJFZvuUdR2XGeVEOXVlwQexnsxWTimKKvJsw7HAdjsEA0tdgzPUgQ0LUEodlz2auIeThNpb
+CzcPr/MtHOTrmtz6NLh5KsBk3bMl0Xmr13RVW6sshCDca3RCXpAn4Lvhh8uboseuucrHdnw7Cd5
nZgwUiHHwKouN8SnaJ6z+XtKoXSxxN9wV+2P1bBSqAU7KMlKEQT6xVNr8tJTy5G673otB6JPaJ/a
IpzPMGBnIa8+gth8Gt4ECVmt02MK2nkPprPRqqdJ1umpLRHW5ct04k4F84FJyGj4OY6vVtwg3OFP
vdji6ah6AAKUuz97CXQPJTEIpNfXmhO6M8bHwEn7yhu5eQm+nPHn4KVOLtN0lI/48KBlVpkiEyEl
f6bG/BdvYXWz9mYIAAgR1eWJeOnXYNsBqNtfKYxYFus1TjpndBJBIJT+Sw8Qw7pHWvVCSs4EaUJ/
f7aEZppNhurwVoMr72GGKj+2MjZsxDXzwZNbkMG1mOrCJR0SXTGKFfVdS3pUAaHmYYbtAB/Y3a5Q
JiFXOZeLF4WViZP4BEoZnuEB9UORHpHJAnrTexRRJr4hTfU/oKRSN+CGGgNN2PFJFJmgFYSgwJ8e
LCdULckXZjbC+HV0OeHC0f12iiUyqXKLekDVEWpwws5l6CNrZddF188e4rLLJZES3zfytzBQKz9L
d/CtSAj1LsSusB5Z6QuYq3BV62ms/bIeMGTjk9AL7kn//FpxyEJkSLQhli91s45KUcbwoWsvmvD+
wxc/yJFIBhNgLbCB5NysN1+soAmrxfEVngwQkd13d6BORSv4YhyiFNfMiy9KyLXYWHCOOuEw2n3l
s66u332lVQKTLr+J0ykmW9HyY+ehrJfvyuZplmvY/xfrs9ibys6K01APFFZarW9vZDi/BxTKrAyg
j3Mwa+RUvzzIqKjOprCUwAqVUMUEDX7B1zgSI2Ii8QbniuX5JnXp8sIAfC+K2CW5I7IgLSmPQeSl
+j01a937vfEUbD3Ch4xDHbcjTSLrVsniSdmqxhL6wwJ10bpNE+pEt0ehVfIjn/Flup3hz3UmtKCI
36NCjz+7ZiQK/pTi2e/KJ6e8B+fxKQs+w0bEz4VE1JwaiYa1OEHf3leD6685bf+AjfjmwNCAjvmP
8FAhOdt9HFMSZQGw2I36/fdSnKVNI+B7RGpM5GCUbAGN/1whOatinEN/hIvK/EwiCOS9Yo/mWjGc
lqTdpvOoou7IVRBzCWH2ZWsDMv5Yw4A6TzzJPVulCszIeelUUpWdcpOtEtHw+4lbAcNGpWdx69FC
LuUBi0ZI1B3tNMVNFYS3IEDOwLrg32+cK0U3G2cFv1eyMy3YbDyrcZT42bj/pEHppHSm47xvnlDl
Z3WVK0YsilPxUyMY0QP0myjV+PYqjLe/iJIagh+agE/FQNPGDWOW68/DOCDb7tfKqWB8IHOhgWPQ
bes4sQesHHqWiOVARKOkwQdX1CoARRBPHb0mJndvCYIxdXGsysawZkxbXdux46ORrBwdQM8/YzVz
rw5j9qiSvJnf1jaZLRrEZSIdMA3f0Q4Tck11qYWZOflRV6zgePJ9o1vQupNUmVsfMlfurZeo1WuP
4psr1Jls5FMuP7r1iCdsHt9ZRSn8hHT+KajpiPtFr87kS8CXxhC53rNhHn2X1TM9DEZkePkm3MLO
7KT+L3ZkqnF8SlFcJHqAEdsjPrrdecvtf68WE2EfzLFPEb7KYkLKw2Ul9+7ujcPna1yfmZ6+q3yj
a+hTlxoxS5nYT0E8CTh11nxbzNGI9ZqP9GvGXllpQ4kLwCV4pGSezJAqmQ2cIo9OSZsybRL3+hZY
S+UMoJpoPj3YY3eA/KqpOLr2xUkYuYSQkN8D079Ttj860b0lhUdJgW0R/u4QPF96l1d4O9NcugGC
9aIcFDxiGMlgYPuTz02tmD295xc9RBIH49sk/5hu9R0H50e1Ox3vwzfGrwdi/Y9mCFiERy9+mNgP
oCiJn35jfsqm3MB1elDlT6qK3cDb7vhkQcV0BCFwy6HgJ73Aq6Yfo3xiCoVIrL5PM2gZsiC7Rkur
UM7CeAPn/c/rBlUs+NdeUVG/xyBwpr7oLFsMmLt2XK5TYe1pWRgwQR8gYfEEgqeQWl08grfwlG2e
mQoXuDcyZp7Jp+qGJgzn3mZ9vSbYrEWUxn4VjVru2qZHqoRK8C8VEABKzvqQtV7/0QUidGtFr5J/
kyx1PGLI2aN6LLwDEIVFN5gh/3ej3duHjv4m/4VaW+iL01PSLw707OXRllKRki2EPY3Rb4EFMDwG
gI0/ch1k2+wEjEvpS2c05Uv3b5lwDKiVQYe2xyc4Xj+8fLctTUaPIyuc6LeYeBTpVhtdAZ6gKBdG
qlFq4iEScRaFyBLewDQ+jjeRAopF+Z9DQfAC2OrEvfPNA/O71A5hv7SdQhRGpaNgydGkbKcCvZiK
aBu+AJAKSw1Ja0jB5GevVxzDRFVA4AoesO560wJ7fEK7CAzmA2oCguTR0EKzCO2I/m+QbFCWu7Bq
ifGbDar6J8CwXDQEdXMFe5AlAg+HtNA7ua3vupjI9kmroLd1reTcudLpwLhX6waavM+AX9FL9nDj
WQK7cDZfy6UMuKin23y94Jsq0Xfe+MrR5gGgVG2cysNmin1yD73HronCUVgwYOA8CwzhZl2+c2w6
kvGHR4gt6tvu3NnOv031/N0nxYCI8Jw+2ayYXQS82dGB96db9LcK5vQ4AuqVNh/dSlodL6bC6Cb8
UnInSAbkcplJ/JDKh1U/SbkglJsVRLUXdIeYOld4zmPlpOxqYhK910A8bziUx/okqYf1nZ77JPFZ
ghWcOqi8MV8de9hsMsWEL/4HddQsBKSnFT4L6vnZyQPuapbUQSwNsud0hrPPmMcOcvCoimlG5Rc8
OA4e5uMP6Bdge5jkQcQ/MiJ+PCPHd34zGiZ1qeazgE4F2DKbCO2KUR4RIi4uG3P3upW+IuYhZrKP
tr+4uZUpaKpGAINgLy4RaphkRWTdp+cf7QNoUpSHsmCspXQ0dF8cagVDL9ArUIDBd/2zoOXre2lL
L2MM9M2sjsFBkutUXsNYewgMkya+9fFpERLH9pn9OBpD3wBPURXNiUr8OleBsnBVslLO5Ez1hdFI
/hZKC+dOQhboEBmByJm4Xb81cJOCVDmQWJiMjc44/JNHeFYbnBwv9AuCFW4hu6ac0uqNyYmbS4sv
A0oaQ+mdNzf9T0chJ8/J+FAq1CFVlL3WueeFbUnsLfnrll7hx8lsxY5383Gnt/5+NGUZO+wKxoMq
bGX7N2uK21RTNEmw0B4o/AtbAPd5DOE4zSkYYWLtGNbChsURt7bzLUx0e0mo1plEvXlg/QP6pHFo
5xYnJbWber0zf/Ujl0M7UyQlUnlY2qrOkvE8lnXJYEwrOb82P19EdfZLShuq6Lkb+7CiIfAdTKGK
zaNbOtEa1QOWcyaVV/wDs1iA/4DZ5D1OT5xmWFg0Zvq7QGHMawVlc89VCyLSsx/bQwrN1CikWwjc
LaDwZwmpl1am2qhjLaLHEErvBE60eCV//79zL64X+mosZS4O7ygLHiqvLnjKGQKrhudBxTeUn0m5
qH9GrOuU6jfssZz4jrGz40GAdXAy3NPuICWm+msCzeyk8sb+US97NfEZSQn7Mr5dgbTV8Y2pzRd9
tfhM9dCldAK3OVJVHTazvZk5y8/bSSsfy7vAhJrVj2GI6BWR+FGldcPgNrKR5hWyZpIakByrpe7h
wxiy9BXpx6rHnc0CzQqvP6JZ3NmKKG3z1IJkrCnh78QGaVxzeIAEDEAEpZrjO1TMoEnXREJc2EJQ
b6yBnXJQ5j8p3uS2AfpoQtCGCxG0lIWf2nRnsYdAP90jPnCYplkMh00H7Ygq1FpqKA47iBxZ5HsI
CmKTRVmCzE8G7OR04dbATWLeIlJjV567TYMvPyzeIxWjCuuGGY+/FDcaWk4yV9XhEsGX36lL57cP
YiRrmARxmMUQxs1r5jPlAabd/+aUOXqfQHQJtsmNBzl15dFF/SdJcX5fZ6TYk+JIxebFndkrI50n
X7B3ORZ0bnwASXiPNVWeVR5Eh354j2N6l0Oz6eT/fo1iGEJBhBLg0AQKHsoZ/pX2voHibvadZLbm
irllDtrBT2IdSDqTbvZm692f5c2EX1Rhg6N1GQvA9XkS1Qx8//qngfLyyk1FVvQOWFChm4JTRS1j
6qL6nT3VacMHkwvYm37WbHHJ1rGbz/KN2d6QUXgOlQkSq56BLUeteAgLG9k5kag7kp24H5YfuwM8
2/SP0fdBzbsS+2bw1yx87rCpQXkS2i64HyTlEtSq5QbrqBDlHZAAb+SJBVjNUdn9mRiVUvySiNy+
mBUuPCh3O28357N0X23X1KpRrOkTLmRSyE52QZWUS7VkkFsmnvjOqTIEsNYMZ5fubXSLpH4uYSNC
qAz4Cq4Evdojj2fi1dBxBLd2pdKz/8y9DAWRT1kzDAklvyc6gDl81SuqyhubKAYtJNYKXKRohJus
4AD4/Q+VsnND/7RuJ5oRgAXCRHiL5/fJx5w2uBHPa8XLt0S/E0eAmhmkabk3dF61sAn2Xjglx1l0
600eRx62NRSWLEbQ2dO8Z5h55KkJV+2B5zLXFXzfhifU0+7xF6hkEAuJE2vipCU6uPR8I8nTmDGr
P01Ec1ldj/n5f0596FKSSbSOn2mUvLGq4GKCNatFrBNDBIIDoVeAi3UW6G+CZE6H3QNhVaIYlnZx
WqNJd2SFsEcR9el7H3stP3DIRg0vnZDS3p4VEij9RxU7AdPaRlC63886xSFJF4MRRxc5ZiLOoOCW
SPDl7YjWTKNWVtEVUQswYN4JqZuc0KYpehlVu98WDzLpwokAdJaPco+bQaPSh3sBjA+yoS/2+2kF
IzQTMY6h0L+CFPIv7qk6p7pLsG4CDLaQ9SlgMDCPT+H+8Nvw5UA958hMoPJS6JF4xR3aAC9oAMu8
jW4kz6bpy2fTxSikxrQvrrAmQE1jLcP9YWa8y8DgAywnFBkNZdyDO4AUTSCFSE/Ga4kOAt5M0frF
KiaLS5Z+WPLGrgVlxiO6nYLHx7t6TNJkBTdmL7HJud+yOyFXwQ8/CNmxITk4DttoNwL2SJxjQ9kZ
SHRc5FRmSmT9JgYH+2D7iuVt3nHPqpK038Oi+eu0SOcbbgJwf74yHUMBUveZ/8llRnMygoZPb8hx
fGMMX/KTmNBk1L1eibJV3Xy0Wm1ychajT7lssLjK/g9EQasPArc2JAV/63OBqYLvA/aLz3jQ37mJ
tKbnEr50EGC347BkX+hse4g//hE8+6887W3hHLUYVGcX3lDmHd9qAcswclsEn7rumQaUQWBZFKBl
uAklGCr8fMeJ+/GgiGRuo6m71oMabGasCC7mrKT+3XfSVtnEQzNWgebhyHtI8XdRmoxcGBWMXiQD
slQB4TTzWoAMuOU68QcNKzlBHMJ5qPtEIyscT6r9wlQqstVYCWbWKQWSBXbWp0KDnZXVXTuVaQB1
J3eUGfcFKKNcWHSKqiP962s/Eu8bhs2x++2zHxXDrdc2a7ClBU/MftdsWK396Tnnkj15p+vLQOeO
OfWJ2KhHR7lTzWG9+SEnaFT5Ko5pOcXIHPUGBInNoIWoiCPGcP4DPcmkQVnRQIjKlqe5PndjHHZx
RGsDpHwQBsQn21ktdDqatWtH7SNaKUuFNDSUlqRL0CNJK8RIoGH9J1dEYNUM8S9pASmNzk8g1+Hm
rKOzz8Y4xb6W0nShJvmhmMLLWwOEQ2G0W2qJM1Kogv1AeISVclyWV2qokJuGbXHbl+cJNgLfhIg0
O2/jv8kyH7mvJD8nzq5O0/A+iYbvrQMKjLGjiu7La9/Mw9SikjrAbbzOws/X8BXvXc2Fyjf/Xbpi
DzLmp87q4WSkAECWeLcEQkViWofVPJBJpnGfSFtjIRFUygR3G+laxM8a/H94+nxwBAIarojYPB/h
zPFa2xYugoJX+5uEOaVKxDmVaGMNG0IPTwMW143PEw+Z+jCQFD82iU72IFQwQuRM7L/ik8ch2DfJ
vlvvAi8olcYz84ipE3/gRLDtmcDEN+WWvL+KyQMRJIxWdvn1z9OdyoQPMLeuk8PDUsxkaECQaDeL
xgXg5UkLtgfOpDUbFcLArlNuR1o8P7+mpNXOZJReASFsiq419cAOfUC9L3s8cSKynpClJddKa+5S
q/o9paK7eIgG2dx+Xa6k66vg9KHCUUzwp3rZN/0CGfOJudj4ZVCkexP96xrHIQsYFeIA9gaWip7k
EhwY9DRwqIVCnossrun1RoBMMh9PHmYB66n1UK01nQhQHcQm/71FpzOA80FtvzmHCSjHMsNHBVkB
DLYhyaIwBeX8Et1mljrpzX8bMWWgIcjI/RyjsAVpy6/zyAcctGyPK4Omin4hjCcQqiuFqV252fmm
9qGXoZxjbRsDj6RiHBAW4bKa1+qIfcajvysd5tNuHK6cJCrr2Jhs+lFXdovIByr6ftQidfrvcn2I
cG/IXpB0owQk2JyJVJYXL263e/w5va8jnMJmye4IDO3Ay8klqgNWS+JOr52uJC+GGIMcDin1xmhP
wbCdM4TIRvuXk1yRCXf6+SuKZaoz1ZIFT6rCRWYEikJrp9f4edEFwitAVnNgA/FHwOqx82AjdkNk
pEwYcSxDGIuamXUZKWnoFRf+CVX5dBRlNuvdRE1fPKJ/V6RwOIT2EWjcKPcRNLYd7kpfgI3dPLrE
bkcbGpIJTCedPdg1ubG+hCTEzP/4DhwUJIM4kxirMa/AJj1aG3W9oxxCMeGRW7jRRlNdpRVg0+ls
Mh62CuraBx0ANuKF4T55NE3P4kPO0cfzskPChfOgaqEbR/R/gE+Jwd9xOL2jCIgI+y7QnhDvvSLs
Deb7+UdnUyevBfyHxH3LPUDOKbw6d1q7+MlSodo49S9zYluRPYUmqWYrMGvzVTz3Hc7BDCByYn9x
r5WL4iMarB1cwBiPO8+tzgXbmi5H7XH2Mkwv/lPQgqycbfQAeLFnngXuuOJLc/goTgcYpS5y5i2d
s0cyEIMW1RtiNlytkAOqYpcbgtmbIcpG3vUyYCncW7UNOXGa5ILo369qi39ZfsNd4QcCPiOHAPPX
XGN4lceCPHOo5hSu3iUfF9zgrSOJ4xCmL0oZBAgrxwUSzInHootASN+0NZ5P0U8N4ZDsyPt4/cfZ
cwbSkD3mJghRD/UCVeyRSB4CdXctXn2ttxg6wtFtbo0KBL+EhTyN/G0Lo49UuGOGaBZsNu5fvU1m
4ipiikSZZeFJ5uGp1Op+3gimU0i2asZ02+AUlhe0kb6VVK2k9z5oE5KlIObDMOHRcIIq+FArLit4
wOg/V8dHvbNJhiLQOiSQL85qBwKh32qI/r8jEg1xAIF845HxTKTeT+jA/ZGKQsF8L64Dfxern45G
i46EHcmykQQ+DHo1C1OPn0u3dDbjlhCp6cNSEJM4dSxjLRCWMEarouisH3taL+MGHxyye9DCYvYz
+9zS4NqeeB5oStvROlvx7k6cBTAGrSgPXGPEsploFLScYPLEbQfHwth3j2k0hXTpTth2E13r8os9
gBZ3bqk0SEN2N0EUi6+kBijAsXGJhGMdrxLTwmDHKhrXMb1MnPmNHhOWql9oFQyb9W1KgvorUdMx
ieES4IwQq9nCCahUoZgP6kd+ahsvzYreEODybuxkw4p9kerzp8sXvs2WWZki57Jl6xtzoROC/HXo
k5bG4f3V2lf65JGJp2jS43k6jR7opX5m2X7FSwTfLmAgt353VoNtT+ycWyt11aFFe3O0KwnWokb8
61TXtI23h+5oTqXy43kwt40u03FWrSw/AmoAKvpYXsjHS+H3hU49f+79yXcExPMf6HyfRE0xGdWi
OcWkiPK5O4iD9G51V/nql0VE7FMYIgTbCXKsNk8CvCvATK+7PCbnymMAaRoyKIkLpIajOYub4Jae
4MUIVNtlUifbR58bq5o9Vp/nPoar+5ChkxVW5XUgVALKJo6MUkCLiWHVQGiin4tGSIP5btYjcJqY
w0KRmfWv3rlqmZpeKUv7v4mYKd/1nljPZLjnXqa2A8aa/sfnPmbWmZuNe7iDildUGR6WzRn7lB90
ifVaf3Iq1NSZlRJ/MW7MhNhF4Iwz1Wr0om2z1ojkMhY82GeckMFe6G6zpOw7lcgS0O/j0Ic/v22k
oCIg0emNFdmnE7DS4P0UBDvhLn9v/1Kwo7PchYa6ZlAlmOf1k0TApnKQbJK2rEaUfWXmO3Ogjdbp
hXK69Fu7aEL+OB0b8NjPjQoORgu5v+bdPXCQ1wWsbphTjH+oxv697+Vr+1aCpXhsz4Hjvp8fG+gI
Q8yUEDCgZJ75x+NvZ3a9PePwk6ZxI9xumYMnVff2NhfbqMBLaqq/HdL/SviQQ+REHm9H3ifObbjU
M+5OpCbl31T/2SIvfaUnQOmJTannqHSWS0QF9fkuuLoL7xM0kZoxa+wQFa5OgfC9UiLsujraGq2X
LEvY/nn66Pak+S9mFbpM+YjiIV9g9eni1witfpGrQ4U94DnC7ZkM2lQ8ah2Ut5XVf5DorQfErdN3
hlBWwZPcVT3bYxkN+3qWL67YUj87beBAzZ+rDQarLpJHP7jGRiYmGeVybC8Zl5otkeuzw78rIsMz
wmVnoBPs9LDvx+pUytDq5zyvDXjfzZd2BBPUT7TstG/DgHS8YbOoza4wgJYSDenbIULUOwDGEq/f
AaqKN/eu9f1gA4xohuRyYxAe8jARzrqJkOSz7zmyWqcOAI7XIh6nC9eqsz2wn7MgTze4VBykV5qG
vylmJRy4UOOJCsCmkP2T5CIf4PXFFySeHdnNJOAhQQ/amxFTTDdq9W5AiteHJwQyUHnrXE+mqOxs
fDJ/WKNNMJEfofAPQZPubLU4s6x6d4UwmVfSVJBITx9ETn1nQLUgthu14mWA6DzAnCJslmmV96Yl
tk3DzpsgmzR1zHmy+hy/m7smSaYGNR6KKsFZetlgx5yIgsI2XfpdJajRFGWiZyQYjNTUmvQPgGrt
xgP6gIz3VWcPfovJw76KsQ1CJ0j/K0mkRt+d+ODYFltcce3bs824sK53CXNX6wFaicsgSjkF2jN4
DsX4IgcCkHJXd0CBgQ9Oakv9l070hQ+rXyaRdiyfizH/oJ0ADU2eGffMEb24c74l8IMM0i1AAmgX
IYvsDa826DOz9b8CKt/7cLvsEFbGt2KZkMiT9bGE5Kb66ZBF2nZt119Q9hVQjC2PzNSSWgOfIWPL
lCib7GR4z4EsWuIht8PS8erlAHeAU3i6oL07ahDV1APgsSS7OSOEQcwcMVXm4p044O70z0nrBT5H
Rj+PKrtghINIJf3ZrW4XQ2ODD8xLoz0B4DWaQzrTGPRH8n/oAStt9v3tv6B8dACi2b/u8QIPHsA3
scPgN3hmfHhQmjlMhg4mp4thCyhx1YY8woyE0ijZVwGeiXg1/89FrIngTcALiOiPNP6Jlak2AbaP
0su+guiavq4+bSIo0tW0WD5PpgBZ716bPpMZRytSfLR6Y2HzW4jtApc2a1Rfen5RhSjd44AZCFyz
zxpf4dl/5MPyXZ/Ni0KHUnbN7MAq9w8Yo+TF2PIEnaJb/kR5b7jLM2N8XekjfjEGWXlKLFbn4Dl/
juwhGhjx0a3VrkUoCt11Vef+aRbGYJehNhdvmRzshrzwnBpK87qQJSznYje5wvSLZtbpmnIT76ID
kpkYd2G0eZlsJYkwsSwNm1+9iNp3DGGBQnfl9kx+LDb4sjjalElPPLg1U5RMu7RwdjdISCBF8EHf
4yKxVNYGLTcpOYbcewrUAbSDbKQzGtQjCgErM0uDvYkgUCQuOZQVjrZDYYvdVH5gy3sPWPQvxuP5
fwxoWU1eqIkei8LORBmb398wjaK6C0ux/HjyW2YHBv0kKJyuNRP/rv2BCwDg0WILMz8woKTFvvN8
h39zf4U3rg0xPa+qf7oH9LSFSNV1bhZ0FUjObhP+ndv4iSvPjmEW+McaohUlAi3YSc+S8Far0ML7
pmly7lIlKfOQnpJF2Q3IZOMMR7Bej60I0ANuUvLssfTn22dbK8mCpalzxCwPsmbGtYwbbF4jW2ef
AuPms1GH0D/GgYq6v2dUTOW6a9wH11OL9yX9tEUAechIVdM5QH35/OZSDfI6izyXpwI6IegX6OxS
iXo/MS3YpXPggFbpFC/AuONdWgeYf8YU7tq+jG6xgSwDqKE/DM/MpjVNjrs1eVafIAabf6zuLVd2
R70TXFGmn91Zo4DNB7XMp8Zr86bvK45EeQmNQvvKX4+Ro0gJ9Q8CcpkXdYQ5DwmWyDWToZAuM27K
Yp4PhVW7LZhIw0XSVJtE+AsJAV/2HjtlvY8HPYdwdUiuqZ4Lhjs/eSbr6omi9E4tPV8N74RKKAap
VlcRM4Z9Z0WqNVbp6W41uuwxi3I0lewYzGm1czKO92zBiKx20dWoVfeeo8nLhlJOgwKGtnLUxt6a
I77pY+Ao2JK59OrBt+NnjAtGR8y4dXfh8uWcD59ttye+mZyDnCWXi9o2+wQMG4akFvCMKoTXM01I
eCrfRko5FvArLCKUlu/gVF2RzJux1BxrhyuH+f+Ys4rL5lwy2HW1wtODNUTtGU+z9sxrdYsiUzTr
BJRRiW2srVAJ8meDYxFTbmUiwnC+nNsy9lab3B08tyjc0yiXxch9PmMMu/tQIj0SiSJTCrZzugBb
8o5Ahd7r7Q+5ZRyyF0fyzQE2PGaLfv5QE8zP2hu3ISP1hFJXvPFHI0Gd9k8zaISaN8mG4VVL7gZt
l2CTX2jp+PMp67B/Nd49kvNN3h/ophDLDUyGClFjpjLHvfcvkGnw0fBIqfIllNkjQlhxGiDffUO4
Z9QOrBERQgVTicyeytzZwym+lzWUmJWu+ijoxFcIiskacONlEtgwoHQrFLMmD/2HKcE5wtxiFyC9
B9S0USNvKnEct0XRvLl6/LWfILnZs7RcPekfIox5wmPvLGDrdUt4k2jBZxR20rYT8vah0ubpjWZR
Xq4ZErEhHLGY1M+80Pj/QoPws0MbaxEK7BWu18sgKQOojzyapTNkfEYljMaCJLcoBFRi7kRzc2+7
TrYQNGrHfX+q6gwL2vWZuWTO0tl6YBNgwCL4Jly/XmbekmoYyk6NqPUilZeF1ns7RDiMZ78SG/7q
w26dgPaTOaqqYfSDm4XkUJFM0ZW782Lwv9BNHCKe2wmrvCW/Xfn5z2gl7Ls2agxvPyyndgI7blx/
+6jmvQpzvskTNHOFmtNQ/JfUuV+kxi6EQBPq7ZM1SA+5L0C5o1JdFoW8M9s6fiu1TroV4xibx8hw
0Ue9zg+0fwTj7kHHfBmJ0v2X9i5A6N33fJK96/q34jzByvKZZU4S+CSB1scnzIfR3KM46k5/8gw7
zF+krUfD3IUBnTybQvgP08fS02hdW/TSyfzTo99uJBboYIVrwKDrbi/ls3rvzwUW9UI+BRqQJPF8
tiKBmKFjq4fLyywqGAH7bS4E0z65x5JBaXVhC8O811I7NaIu88JuedvWZ9UqFSNGo6MRmE7I1Qnf
O6KwiQP+uOoBqz6HXaNHJNh2j4SiruMsl8HzxrFDlRluFtsoeHtlhMxXRbLqnk5n5mwl4fxbenvW
kc8zmITEKUU59AVapAGjovnRVAy2+uDEXvw9iKevj32mB852R2i8CosXT9J+AyalI5f6QqMflhlT
5/4dRKPHJF4VvqZMHLLTq7Ecr/aBNRIOdX4A55Ziao/9X9OKr/sK9aiHYWg3KHoB64wKq27v7GqK
1OyXSvmxu0fUZTTaQGJXkxVU4q9Nru47WCPDlwzDITseOJkaRsU8h7yZrOZt6ibab9tgINpNjvFy
9WwEosHQOL/ZKcmjbkNzA9HO7R4/e47UNLp2gR8wWz7wneovMYhFvYDOPTWJkrvOHBbgmH5gL8Wu
nsa7XopaBw3Xcqif/S8Z4oDgDfjgpBu5uo5+bfIP5kVqZEY3rAQGpj8ft9GkQHRr4ampBQwY/p2x
67KA2QJhntfja3HueP0ZnGW2sLx/xHLfMiH1e+JH7T19VDVic6+/cnSTyR3+6lIE02QCjvLZO5Dm
YCqcoeLvjXP2d/oJsg9gmA5tNYzWlZqiXABzjR/hpErNG8EVE+53PmodCNlv6UGdYtiNuDgrLpjc
skNWYl4bj625ny2bKoUvUYVya3OZn1Tzkx4u7JB8MYSRgDx9ciEy8XTL+gqkFA4UsD4yOyF9giyi
f7T4kv/w8aNRCIVXCZAGGNtoJhaoiQIpOw1uP2JheNoyPSF5GKaAEGdgkdULxkdxY0mFXl2p+8pe
y7CuIg8UwKotelXYLTDXYaGRmoRtpZv5es/7bPlhLe4ItvvEKfN+oyEl/5IzKT6tMpfkQy7DR7OJ
7pkuoDhlN712Jya9sQW/S0A1+OxrBydsQBMoQyNSLKqUkwfTG6ipfx/Wh1uDtDJ6zd7C0J7WEeiE
HThDbC1/pX2WMNCMNhfNOvmTA4SzoopHtXKTwpwqVcOuJ3uHxxBmKgzq/bBdfSQ9N0oNqgXcSdl/
nad4J8glgWAHpwpsCqYXZT9RDH2nmUoXFa1v2kjR6DgUM6IxRcZojO8VyhQ1p5Qj5xa/REd4LNAT
bCF0yewIYZKsATh7c27jrjZGO8Aw+fCfVHReIT5Fff3GeRQM7RtJGYBU53RVuaDFPfHnl9SmOto7
zrApfwjzg1Xb45RX/TZ0XOww/GUeN1pClizKoieSM1LjKBL1NERh3Fpyjhj5p3UM+iOrLay01SPP
0iVHBeNo3XcfA3ZcJCgp8E6r+nwzdDDMucWqq/eXsoWwfe0pVor324F2ORlpi6HS2Ovbsub0D4a1
YvbD7RDlXjw/n1ciE3fh14ZgtmJBHpjm72G4yKyVt55lUM2HmRG9HnH0GP2p7PyhW9I/PM/4nqjb
cNqgCwOMNXQKLSNAMPWpk664s+nPsOcmgw8toQzHh4/mM2sPGZjvw/NYeglTpAjSlBFMl3+kC7VL
gKrGb5flYUOBIdT52zBnnJnkh21XIc/iib5q3MpY/R+kk4yzca2guhUfkMoqLUhVzeCnc2ED3kJ1
AGDs5LBVEFpxRN4WNB8sCZ7fBNF445Z3Gr/jyiGSA/3uibAQF8vokPPKXQgSrOrQvAERueJlPK+C
vrz0pPg55xQyuhCEG+62XvGgpgNe3SdrVHZYKdsSiLYuvX9kNtySTwfh4/SWq/QbHyq0S3kDmMI5
H9NLBeftoBlXu2s5uVt77R0G7Fk5CklwvilNYa9FRFu9Q7ncjlBR0IcZy3AowD75cCuj7svRuiDk
0P2Z3kIv+UlUiJmdSFl9NMiirK4wY85EgcR2JijaqJe9Fq2FdruNiWXfm9CLvHIfkyrmlvoLtJWY
Fmq4Lg6YO5HvxSTZ0KqOYPtLX5LQeydVF9m1zJnyeSiMm2EhYPxOGN2YNcC7sKtOslxjyEWI+nGc
hBqJ1FAR96SYjtScclz0zuCNYY2lfLKpNeKbQMrYviNgv5UpWaOJoz7qEv3p8Ly/8Ae/qwPwNSi+
w4K3ITJbi0Vq+zdHWwCTrNCqWqZnpLPHHJ6+3aqH9I56dlFCEkzijLRbJPBbr92etvRQozb7tjZ5
OugpPuzwzgoUxyQLIZJrAnni2IdnIE1eH/qcpcjQJ8epHByTszXKTMpcWxQfvHfgNgKO2V2RM4tI
CWTUcee00xv3JnyKaJu2Bl7hp8ANR51z0AuoGR4aV16timozug2/oXj1ga23hA5XPHnSd5jglbHz
Vm33X6jKbexd+mvr3Ecf7KedK/BjT+PLaZTSasMHMtR6tl643iC6kqvFV47YTOtBOGY/YNlz8/+J
yWJUwwyTiDED0eHrJgtUkyDoYrU4UpTU9Hh23Px1gf5Jc0CLRLhyOA/6WyE++Chyu+6NExXo3P04
nHe+aMSh8AxPJ1GRQj4uzts+HMM1vNwplLZUN8eGdrmi8P8jCWJbpY6/+WWbKayaNuvkyp+ru5oH
oc91Qd2KUG6z6bcMLpLo+pjdLtBrBsfWJYJ3JWEc9EKyCJ5vrHs1pnbC6uW/vYd1KSmhq8H2Dce5
VhDfWYuvSl9w2ytZSwQNeJ67nZ7L9ZJf7Ux2D61fLMietuDg19e62DXI3m1Qlz6STBxgBBAohRd1
I7SdQAyfvjks4Qp/yKCsdkQv0XBFnNyDERQsefOa4PgnQQFrxejf/HDJyaFz0DQc0RaAsd5wT8Sb
evalI3p9Vme6YGkbJjZOsJY7P8a0objmcBNXeuPSUdQ2piJf34ZK6ytfvnDJOpNTyY2NWl+8ahv2
JBvuDaRRqwBJI6ghF3+R4J3abbtmKahXZe09nPM1cN3FtP32GoH4Rku/JHqv80Q9V4DUA2BGYlAX
kUEOYzUQwTyqeVzOpop+yi4rwiLTC7Ox+rqQPkYN1q9ofUFT3j455TJyAk87zYCIoxvI+/+T3k1E
RUyfARCT4Do+QUV2lFKy9ZY7HPt+mRQrkAR26IhHI+y1Cd7a3vJrtU4vl/qIQ2ClfopMBY105oha
09feVNKUvV8Zjr+DUQcy4W9lIo8sr5KmEW+h7xJwsXXlYWeA71tVTwjerjdZMcJmUdt2EwSlfnhU
uoJc1hu8mkmDSSgU34hrnfig0Eci5snSlpRw2KjdGYs0AMViCtsmYrYv+Lg7kJeek2/ij4QmcENg
bRMwyAgDwzrDSW/QzTebtdNLitiERZib3vDd9VTdcFd4Vz7mCP1GjKnbNwho28k2cQWxkqPukm/m
vSrW8MbxBBWt+CRiW5T6awTtfxbiUPGFsM4gw8cKi/Ti4u0RYtghljf9YwgZwlYqBCTHaGfd6sok
WrigK+LfRAbAkw4JMftbJx55kQ0qyubpbqFiWJrVaq0YshuJa+i6SwWbUpj0v7skxTuxc4peLrpb
PukgzrnCabFNtEAD67s5QqllrLyWDTgM2MrcjCd9gn2XfauyEIKMW0pu3hfsNhaTQqPOvU75v3Q1
YP3IprSoL4xy6h8wJfeT+LVARxoJUJQ+NSmaeGG/8SG4QXem8yqC+0cr1E9e6NtRF+XgLZa34mgW
gcEU1CV8WgSWc4iKiuRmkJ2AfydblibeQrk16+JMbMIz727WIyIHztvnzmmn8ce91yIaCigb7UTI
GBOozmFYVf+iqz0/0bX0f3dI3EZGg9oKKIHoM48ff67CT957YEX0QSZszRYktEkgftdnYcB/xy64
cScB25i+CbCfbGGoc8sEQ02VV5B+fkM06mZi2FwxwzyFDmKhV/ClO12H1m/KnP8JpgpByms1NNvW
oiOXswKJgQ3bvIrNHmFneV3tzXzwurtPqY7emrgL54p7Fnm+nSJ1z+jPbAYJG7rz8flCZwkvaSfu
nV6ML/1F8GRMY4m2g/VYty5+Q4MAmA20iW5+lrn92w59oJPqVskzVCNyaX9n+ANwVhtVRTFtJTBD
ckuj7V0VzzeAPSIEVuurM84XQDpZY64hHBbK4sAUoqKV8XtD+0z3Bxkh9N76l5MpN/Wd6uZ3LqdQ
+IEjgH1gFQ8rS7OgUhlg2is9hgjqzOlVCnrsIU8nIsUEEV3jWyzpISS+RXBzyTVOGiZrdOMPTndr
o3iKcF4HRQXFeBzVKfos2tGN4qX7XFcTo4qx8V0Yme4D1MoO7gIef8eKoRVPmbbLeLwFOVkgdng9
K1uSBBT2C7ZHU8HzhH3S4D5kwmfvzhltpUE+zjVtaa6/3O6bdwRYv2BDx74jXrBebir0c/EtM8zX
x5yL1t0pGkiHkNBEtph7DV1WxRIxYykWH5QKrgZBW6PKFKeZb1qNONJkGsucrE7D1BA/jlwBqQV3
Zv9BMYMn2Yf3bMXvNmTqL7gDoSRSnjjsAaPlJvbL+21gXMRq3me1+PjzAv3bMMNNX2+d/tOwfTNL
541nrLBwzvEgQhGHKfrEG0tnFFd5vp1m3w6lbeBRWNqz4nvdvq95idbcccTcxRb2uVhJdUrV+1pA
xG8FjKzv5bBFADez94fsL2izxLfypUdgoJTjz65sLtHNT9CRSb1SYGMGB0Xu4jsHoa8mq+TTHKxK
o77+qmQenYLxxszXhvgAOWofs6V/JUHYGaruPWl3JZlIl7MBEqMNOA1oiROErLtqvDTurDX/2dMi
fMligMtM70bcV8XX6nAELM7Jr4A0X+cgHSpFCi8upwjJwPltaqpJow8sfprGFTejjxzLJjfEVWoT
sgC2m1kCA8NIbpckiVvu+aEjJjzDIFqO6/dhsG+KEEQ3nnj5iXxaupcTOEq74DFTsV/b1s77HthT
+3rfAQpTYHgEotm0N9MM80mPicCmF3hoKyw70xz31J+GtowRgl653mH2KmJdwD6avde/Cf0GrCc8
55Z3yn54qg4SaJfbCoZmGRYbhyfZCbhJ2cbCFkjFJJRfRIt0sNaVlpA+7yHvLUNs51Gn8n+vBHCF
+zccsRm0nBedEaLRo7HMSiFcy7EpC99niEFquMadjAzAxx2QFCju7nxmXhN1lxPHqhn1+z5yH6vz
jRtRq9Lc1sHMkSqhH8qdRvGrmeDh2hzlkLVbdN5HKqRC04UkiqWpIwXMJoyTGIlqXUz7ZVfY6jKe
Wu/Z4lL2/JFdu+TvBDMZM6Ov/G2OMYw1wBh90h9Khy+3tiyHllgxtLRQf7Ut4oGDE0Ie6pY5eY+D
WMJHMWowvaYsCwkhcrXxNZgaHV9kpfbzsJ/YbTYVspMFqE67n+yTJnva4xLnwkrW2ubXX8rQan5X
dskzZATm5eg1QmXgtG2AnfZUD1Gf/eT2DRUi2qY4oJqJ9fLqN2CaXvqnQr7A152rF64D6wZFhhAX
uu3uyrMTb3m2JDzCSGG3Xs37T4fkS6UqGXsDwBnonyG7lwUFHfztMlzWomsjcFfLy9Uf1e0FGS0e
JRVlRppXuqxAuGAZ0uKcEAQJV+OsmEOxfuKHxEAWvH7gLd7d2GbixW0wnw6DfEeUafMm0GiQk3P0
08m03VrW+SVk5y32tokABw0jU7Gqb5I1DzXagFPhn8KEtDAFq7CORuo0I3gGg02v2ZGULqNUag7V
tVSc6B2P2hqFQlJiHYbnnNo3xTu496Xf7duMG6YK+/gODNk6gFyD++CMrHPDn08k4wq+sLj8lUmd
YPuOV/g6EZqCGe/psMuc8hXyLQZdqHlkcf6OvkuRCFn7ke3b8BDeqShhXUSwgLaLSzFzIcp9HSYy
HuqdvkVWyaJkIGnlcQKCa6XIaUvRpsrcSMZqhe4Jmtdnzf2mhI7/X+xgGf2/vl+AZCQJr/cggyvW
GNZ8lRyzWHLoMPjB8M472geeQXGgMQ/NWjV2ArpMC2+CvaNzuE7oCbSLfYH1g3vbzDUub2PinShH
Nz5j4W2XoMXW2EBNSp27Kz1HhQqaZP/k56hh+XwOiccWK3/kpJq+l/J33zOJZE9xKteNMnwsMBYl
EdO3IWobOrv2/Y7tToIBbp8QFt8QQiNA0zBaJkeF8EPjKzUCS1SM2gkkM/LyiOxXiFkUHjgWUzWK
7FsqHh5XUtU1KZjiZM8uclr1RxpmOhikiNU33KMC/O/DKGrpITd6mQjM+UiA3VxVYBB9Qs6jVWEE
YfoV0a6gHSHpk35iVwPvMJcbBRx2VOi2ZNlsxrupPt3O9c1T1k9jlaHQu0p/IDvTHNdGXRdl7cfD
UDHSvygZULMo0l0GjQ1LPLu2GIYrpquHqAPsV+PFFeYC0xAPqEsfe4zy4psfaDVyh1p0DoKXHYpw
vrSVBCRPG/XCS9BYFIyXgIXa4WQyrFcFi+Wa8wwxOsq1I1TmUXo09+K+VxPfNhTAx63eq7XfzHdq
x3cJxh1eDyCda6GhDIdnOOtJJrpFvft3ahipphx7BA/uo8FiUDL2cxgcXDhwkoc8AJBz3M6QTm6C
V74bAO3W57+Hg/5x9Jy+KFBbMKZLwn8wNHYb+OTtKnAwk/ohd4xDC/YharzRfjyUYHRJB7hgWpJI
kafG3DBwSXqpxBdMsoI5wqh11NaFwUUmQxiftuOZMcIP9+filn1a2LllA3zHhz3B5ywQQv8KUQwT
Lerg/lkOt/8WqS402AdW0P41ekiU5a8W0oER8cv53kI0LN8zA+0OYr4eJUunlVBuZlYDEji0UlKy
OgwdG9VTdxUVmBoBV2OET0x+F51sCQXvD336loCKj+Jfel85E+puq+gtpzK4X35WNNu+s4eNfxb4
/sqrclXQ/14H/QnV9ExyDE0sSQxIWXLPbg/H6KYlp+KcLjLbBjMuVwJ9kbfi3DWYPAPpGAx0+cUh
a0FoLxv/2oJBVvI1TOpIdhLj5hW2XzObczUdRSIWRYt7w0cOvs93QoSNTfdnZhUbel/XuWW+1yrd
jtA+NkieJ5uKRVM4rkLShXfGXXSWwE6cWgInSrHMxsbbA9Bw8/X+RJZv0/B4NRyUNeIUr1YObDWe
nKAGqi4R8Xs1oHx1GyFSPa5KU30QfSXwEYwIFgYmgG2+zbr73hJInKi1sPkm8cbPBS08GrDb2kfH
hqgEK2kF7VwGDACrZyCMaZmiINGRaY2zgMG/p/v3u0GXiUKPuqIv/obh8d7GwPOabw5QvTc9cZi8
ifG7YKbOjjJ/XEUJtjdrAuYacRV8GAOAJQM9x3v5jrgLH5LR9dO2TtwJIm2bG0sNxpWLL0jdgx4y
UMcN0qfUotgNdvuhkjnbYykhvnVxduYn9P6lwKHUhBmZwSdLojlqeaJN3R5FlMiVM5jHt9wzOsPB
EfVUibngYkSFquQ/g5xNi69wLBmoo5+YSoBCHIRA9TTQxMba96PheKSPQj/ToEB1UWF32t7nm904
z+av+2aBXcbNgFTaXabOu2wN+EHvS4zFeCQ4Wy5B+xkZQ/IhT/VFbu03ijN+xmZB5Pir5RWwbDFQ
Kxc7MjUNMEwFqzWsBcQfeuys6vfsatmMZGhPOYCSNmzRzfFBrTXpcO2FZ5L2f+3fLZN01qQVU1UM
6c34e92+KHsrR1Hh4fOOkpzngD8ANnvU1RmD2H2qsBsMkP/VsHzieD9eK5zPI+K37PRFoTPV5DGn
5JF6DMmuIgknsTUJpCN7WVUB8jtCVYjFcGfi4aWOHkznjdKS/ARj8lKmGwXtGl5vhWF3aKD46AN4
KW2PvkbCLgH3O5579De0B3ccfwUSz/C4P1ULpzg2hqPYYTne9h0QTnVIkTGhy1gHZ8NbjnZFfwha
ui1PG57jkP0Gzg7RX63WIhxSqIboc8uOEhQcawlBS775HnRCtl67xgBds/jPLGXh44Ct1JRf5Ls6
qLgl87oWIc/32CpWyA8bc/hhp6IbONCdTEKrXzeB8Y9qheQgLgJCVoAdEQNWZkqzfrlsr1WkeuQf
nL3441c9SS+i9YhOeNrmPzIDRjNV+Z4SzPnoC2mmSI/ycY4s5q6AX0YEUR8GytvZwa4PkoQHdJfo
lzk91MXywoOUwwwKzoLPV0xwqlrpnb59Q0TMg8o99uZ44pRZQxz1b4XoiAxjuYVrs4yOD/FXvXUT
bOzRl1ccsiIxSEZ6W6ImzLCXb+MqRGSVTT6ZDn4G8MKdpU0kkT3oWThrRCLSgXnSFTbJWwlYrI5n
kkDQky3gk02qVPgZhSclZvIJUaJt00rV0PV83OwfQVCSN0rHb+H5N4GcoWeZcufoVP9rzHPQ3eIq
sMJxc79wl3am3CLj4OuhxShhFueqoJ/E021IVEyEdOSYbLVpeoUo86GTkG2P64WZPx6gtLfIHXtf
VEHITWvuR9OK7R0DyAlVNy0s2SZPE+ltj0IaqJLJq4zfNDRWQrmCx6w+LjhAX1F/vOJO6/aSUzaA
GW1eZWTfr8nqyXUl4athr9VJIkH5riEhil9yFX/zuyIav0plQeS9c8qDuQh8Bo6TSpmu2YOU2bq1
2tmjJgPOpovOyPOaTwQjSyTm0OlGcGQjy3BZ36SUYBZ51jZGYDa4aLnNSoiyF0UFK24UvJgC5ulm
hrodLMT9v+i8nxilbqbTgYUfl+RT9KTc6Y/JF5eVLh9DNczt7o8BrJyttS5u3aaF4JMY1YKMinn7
NN8mwVpOLNpoqB3L3SND3TFnqWEyMRx4467W9E6RBGjHeaKnFKkzPFp4x0yzAFXqtoczGymx4YOB
SaZgUZ5gDqZokaTrACF+dPhc/lRkBJD0h2ddI1zTypjEGOWmXh0GwCh3eb9LX8zsmoLWJblsd35P
UQZpXSv8k9sLthoyB7V/yChuMZJicqxm8QSVO8PYpJMS2bp5SF+3MDU/h+Y8aFmKladGwMRbFUqu
XVe/LXvjKFOflUQn3d/Ev6a7YeW+nkuotKW2Edt4NJlo7QY8tcNtpzYU0SKyiPKULF1fNBLBMhcu
8QOsksHvtnhs0tDKeUVL1jcnL2mury+ZaaZ0wiHyIEZAdXOZKH4AFBxdILCHxYIzKEXEWf6TZBLN
hzxYY89nVp0W1ByXbfEQVN2XKwO5QAKekrStoX021IBLvoOx40eAHS3Kwa8cM4S9/z0VYU1hivY0
xvLNb3at5QwRNwNQ2NHJoA5xC5o+kA/wDlJki2feYjQNYSr3fISRjM9dI63uuUz9XmEDyy/5o2oo
nMDKXK+wPESB3SSvqd3VbfxttsMhdZ2qokFVDGEmke+YBExcC3qfA3cYWGvFzKLIpTnVoSPqB3kw
F4Vz6zBfM8jgbXaWEs/+gelENozL3eoAEZa61wwUMga60vk2HJY9UKUMwcbtsluuOtx344XMBPMN
iDGSWv/UNEUF6yF72cc5d1O/k5u4s1Zu8SEWmyMXf7058uJ+vYJ2fszd066XwbqsWhpNfrPwzgVk
voZz2pXI3dBKm6f6Kr5Pz5m5rmQKsBJMJCQzE2hbgjRPCVYFHVpCYOIShAqYpixfAjP3/fcxql//
IPUsKAg5zz+19W235KxHmw7mV1IyF8mLpn+8uAD+e1oV8GGcnt3BfBZLqyoly68waxTU3Se5Tq7v
9a2t251t4fcLNAuK9j2oq1C3uvAZvDEdK9TotXne8aZly96hYQHAgQQEUm8t+ul7McaSe7uYiV/+
2PJtvWaumXhBA0TYG9kaNcD2Z/uHYxIpB2y8GsG3re8OA5z/BT7/2nd6GWiOcRdUizG96JX8+HsG
sLkxXinRNWV7tFHAiRGjWh5dH+1evJ5P/tkNloRFHpWE6Iv/eVPZ1UpD5+dVZyQp7Yecg3dWxOiX
L0Pnj5de7jgDCU7ddFcsTVREnxrm0r6P+rclQkVwqSutihJEDhjpehb7SryDQo+A+Oyq7hBkiyE1
zNqJUGkxG+MsFtQkmWdb39Rdj87SgywhbIHkOhyD36fmZDccjILmn3LJHdP1Bfm57bd6Auk+J9pG
4Xxkg2CQKsqMQIdBo7p7UZhS/znfRihysNYiE02O8zcQPT7llZeM8e5VSCFXJ96MQxnkZqEPoRIC
NyQ3pO68mTQuK1PevC632yfvBB0Rtal4/RiUzs87StmNST0kjgHO1CjsCS06HwaNWf3HMdtSVT+Q
0svZxT7vRKeJjbrIZYE2FqjtNkdTUexNQE7KptUvGgFI07nDZYsrUsoZWQivpyRYxGVIKmFNxuKr
ffpawjazsT52/kVbt6JfHiqBE/RYvaW6sTXKGqxffy7UdC+jjUoiXQNMwix+W7Ao6BCiUe9WVjcQ
nZFMNcZnbJSF3HrORF8WfzdWfIrMp47I1FWabIYVUYrEndn+r4wIFS1v/n22YcJp0mHYTi9oI2mA
ICDn+LtyXjhkmFD7bIU8ksMsTIjcY2KHUwWpDz+83IB/hRS+vWhyyuWbluzsac+ep5bwgxBxOn+v
tro5oWIXzbNj+BcMahN39na7Z16dB2eIgt94WRNMksu7VRRAJCkewl2DRakO1QXaikbcyd+UrPB4
CKTghChc7ObdpVsfTVrxHbitmJvQkDC8wf0PHkyMuqxr00tD3Vumhmjq4e44gi7c0DTs7PaUOgqy
Ax2S4XH2YEX2cLLlOFTMl3RpoLs25O4s+XeCgAMEHT6w+ZmGYSn2WvjCG2J0uZkAuCkcd8n7TuyT
nfX6iKWaOWLm4TSLaL7WirKYNkDS6a/KUlfb2N+XLz7aZOxresnCGHSHecrP5QkSmurVSUYhIbuh
4iovw7+rKYLi8UV0trvRGMkqYrWXdx4zkzKpe4WDR/1FLRfiHX2F65LPYkq9ojphIbWgFmGSZ2Cb
rvwgiEqW7ukDDvVgkro6bSnJToYQA5/rsCm5ZptjByiGAsTUrlXHBH5zgFRjt/NRExNHLenFryGF
QXxaIBHL6yGPJRBqONfZ6XeLx9wtQulPPXX7ZLidfd4vhNA18ZMCgnF1QtqvFN4tOIRS/cZPQ6q0
aduno2ritfnpzmPYR7vkbQSvFID0adrx7UQU7NanV8lO7Xgx1lLYOsmhsf+j2Qgt/nfeac2U1Cxg
Br5zpSbRVsfrKGlgLWLHQ0WMeeii+w72l0rHhoBwNJ5VyszROwy2Wy19QltdYt2JFl4GFv+iGmbK
LeMMF+lFp9CCtN1fYx/4FLNCWiD+OSQlY3k9DWXiiOrOrfOxobqHJ75FAAU/F8sbXPNdWdI7xtnT
aDyPE2BKFRgx6hHx+CdjSOr9LyWAWXQbzIGKEPtwJX3/cyDeBnExd+ffnHZ/XsjqS448t8ZhIf4p
1Fzf/DSQqGl+EScbZd6TeA13ojpwybRe1zmQ4G5NgmXVxcTjkvsXNhWohIBA92aCFkDfdA0RWKaD
wualtdwAc9YmEKR+qq7NWHJA8D6iCG857hIreEDqGcRy6gC2J7ZkTw3VOvLixbeyn69FwOl90jon
4WUjLurZp+nllaicxQC2QxxHf6T4H2BpA/eyiCV2uBwTJZEL02h6SXmakg4aXaBiESy6xZW+5yTG
ZYawEFIVI06hcnD7IBnIuvVLIUgOJLCmawuS55RoAp/0UU+1DoNRA0kNKV6hldu456TaBORHotmN
G3vUhfEHWerCMdHwTaCJhcKxXpCiC0iurUfGF2LCpCGiuHTl8pnHzUrSZaLEIuhnR2aey7BLTvj6
wApDoH9XT0gXHtRuLqU5AkFZWFoJ1SE/9aWSdTCY2sKEtV8f8zA1hDxheBy6aeHaRk9/NwuGletX
AdKZtg4OcmDCMQALF1DbIn4TDaPlb0xBrdyY4Y4pEzNfMHBCBIsiEEqK1t7qT1GLms5X3nIvDhm7
3Lw1hB+uCc8105ilNmBh+x/TVGM9LIpr9w8veJwrBmuPWo29wguVSufenWLrjHI37PA51Z6XfEVx
ES7UC38zYbMYG6yFy8wZcjMk8QkRVDmdv3FU2S+d84h+EvONu0qGRkgXhjGTWkeItcqs0tgTCezp
Tz4Cdrc1D/kXsiPuLPjMSbYzu8wkkwQ3iffTSgk0onsDIYsQIG7jIFtZ2i/bhifnKol8pqY4kmSz
+HYhL1Ke2th/r1zOJ+PmM+Wx4K8vGksNFlJl1VHQpFXac7mkiHTGkHe1wlxRcvCI0LWwfdk5de6T
6Zipk9AKZK45vzdK7cmlUHoSUPXTNTef57mcjz+HOdGYXWj3nc3OfoB7Z1tyBBbnjhe+c0KTwD2q
0jTDDm1vrIX6c2/SV4da3vL061gTUbCuRIaSucxE+TMT34VkY9GPBqhXTIGTxgYsKOTTo5uLBTcx
JcGmYDg1dFH1zT5iDuckDBrm5TgmIWkP7hdQj9G3B6iYqI33RMW20qUY5NDHuBVlhzCriHXSpCef
WNkjM5OoE32P9PF6ZIq18QsAieOUxffbsIz+QEy8Bfe9yMyJWdtSiDDBphYZCTBBwbAMD7hvWAcd
hAlE5ZnQvzEYgXjqziFVlugFMVo59pB5SImw20o8jeig3/jtvGYoQa1fei4rniCmNK/hRU5WsSvX
RfRIYLfgEpIJBLukHkV0FG7r+YtxwdYB/TMkVrLA5Z8JveCrDbxmEcMytN5gB/XDBrENsttkItLp
jYR+UZDvekCRZto7FghEBh+BBPqoC/y7d4SZodrwLTkP8E93QehtolWNJ0Hf7+CqbKWuADkCZYLb
bNIgFY7q/5B6HsPuYMA1z3nP+PfrFCgrcBYrViiETqmbMqsJyJ31muQ10cF1/dZ5A6+DLuEFpJzI
dXy6AiOZXazPXqPXxOKxJs0exmBSlmeUkj8/QEpwejbnXmfrsvt8OzQLAISwWL/zFx+x5K+XCEe+
n9P+glHA1YTBpYlnDgzyNDYas8a5UtGGDUZg31Pa5HifwocmwzNmgAFztQBOH44i0nSFoF3qelgV
BOaS4e1DDnO8+AAZqLTfYrThU0OYQE0+rNo6MLGC6ys8Lk/0pvnPVK9sMVJLlrBW8zZ/ATJveGRQ
4eAyccvEjg8gLFo6cylvMY/jd9HKiQurZ44SX8eVjym0T983kRXVt6a5Hmf3/WCvj0GyRXkw/am9
JrJwVVqORZc0Jix0Qi5nFNNlIa3/IMmzQAMKBX5sHFYTyf1EXvK8KrWB5yC3xMNagBRsuvh901Pe
kAPQ/TgEksd1Fe5pOQZHrhQb2ZY03544ldIc1JPgC1JaL9G4Cf9K9mOsD13uDO9O0Z5N/Kv+4nqX
cRX4eVJqI/iJDXXY/JgufBmHNZp4b+cmiwkczANg/c0GD+JJUEIvaK3y21a8OYuftfWJoEweq78F
eKuQXo34DzwmcN7lRlAz7KN6em3XUFvuDvgwSfdTY4LdN+vSN3SBy6DePB7GMtNvp0yQNgH/D19W
hKTgxKwmR4vCM14EdVkyLRN+8t2caKjnWmToH8ML5UxYhwZGcyYUr27knWSGP2d5vMl4HO4y86q2
V1MKVK/rUL5ShZHa0D1qeRIIACtwOZQTIGjhqPD7khKvC2e2chZbLQ+lNtjGwN1sEgGXh6N7v/KO
yflmV2xt56V5BjiJ1qOYzz9QHR5TFV1tdi0jWsfsB1+L5WRBFkNAZgA4Io6gKnbrmB5WhDl0AV22
sWWcuSjeJSKJNemBh+wR6mwQnvSfBBVrwHBbR5V51atsK/NNmKZhacAo+2UPI6lW5vAZ+whFurq1
jog+1CyYil8aAVDLIYlO/pUJuqr7jNJqvwP8sUvqj6GRE6qDgOfW8aeQZHcLmp2vC5RFveB0TU9c
uUfvgsCSFsRxnoCNDUzL8AVd76BoNwF6Y21UnngmI6rvI5y6rwTE7eG1a+MMLojaQOa8RT5K2tiq
jCtCVOfz5tIcVSkCrbrFeukROrJ3xcGdl9SvlTPtHvxSpCZftgjzklbFGLX81eoLxtdPoP/85wu3
bosZlciaZBTJi2Bj/+QqIWzjs6qlXzDZD6upCfySotBNqz2xyZGuZ+axSern9Dt+k2BTdkw7Plz7
RFmXAPzeIZTetg4JThut+eDd+2zlnu5lELB1XJzNQv/1WC5i8/hEtmJKzZLf9xXkB2n1MNVfvE2a
0KmREy388FM/lue0jcD/0UUb/nh/rsedytPSY0Jj8uqR5jyJqlgbm0AFOV1XKKsgtbGk5ScSR3Cy
hA0KysrBvycUHFB7KfL1HqoF2Oz8qZ0oS3kZCCdxEQwhPuxHrksojXDevzUtxzqJn5Z6vG59Ua0W
LjYSjDoP6OQAy4gpUirbPtV1PGPfmpcHbvKAGnihJZaBwu1pHjPeN3BCXtydhwon8H69xPVvSf5+
BdC3HWHjZGSV+vD0mLUzeOk3s+6P+Nyzsqs9UmPSZCW3j5XZLZZJ5MGJ/T7eNDhlcUntp9LzJIHJ
+OlviBkWQJdWSTFgCOWwP+vtJusirLmI7B8P7nVLAEZQW0PYf+VY7P8+AEc8/07ux6i1JsA83GxW
flADGrQy4uxFZa+ZU12wyAPPz5ye0v6m3xpx7FIEsbss5sD3eiBLOmMXPvxUep8KIXqsS5MKAy1N
qSAiwq8Jhvflb9IfTiLkL1W19iV5f9KtWsQe0wtyOX15YbOT93bknxdvnKKPpd5JAwChlHzOt8/k
7RiJIRqlX4CW6Ve5x0k/2FtdPypbcewmyLyrJNPg0TP3Q4EAwv8cClWdB19ONnl5aPYRzcOlVEV5
LA0Gx/IcW2g7ZNoKuN62WNMPsBYzHIe7dKmwRQjzFxMySRNXRb4yIfJsDOdxESPEFs84io8Kmsmu
8FQoq08g+ey+JZJi+0jJy6vz+Hem/a1rbmuqsNauiXgKl9KFRPCnjAcU8ej6qUrTt2dY8c8envLk
Py7v4i5ygVe13PnF19L7axbd4NdgYoJ/dOdszLVQObgWyoNu1obAjgKE0opD8Pb9KtsNM2RwVx8d
wbpz/QV+EAiwkMn4TDfC/vk+3FQOXLK3tpFzRb8toepeQp7XFljEG5n0YGbd7lPXlXPcoOk01WLf
/GAPQeYUbkFAC7UcFZaho60tlI4wHGi838f2EOu0YT2liBo/ZCrf0k5yeUPIWuRygpaX51i20DWM
r1ViTZZZJELM+Cty4vg3/6notRTXEde6PIXD+HxlY+PE6iOJEZunMfIUCjmpT3GLZ4r3F4CublRp
hmJzAXr4eI98wICOnULJ/1bRkurbUpOhhe5c2a80mAo+2O2q0qt6W2hyCYntrvSTIfbGs03xugNe
U9OI32qMH7yyitTuuFrfG2qKYY/oW7fZGRvbwpwv4VeI9MqEeB/zS2Z+Z566N0gruJpylcPwMHuM
mAIPKp8iw8JU3OhSAPC8aXqmVVvy+wjpxTNusHgQLgXbCGOmQPSvcT+Tzf6dvYF0sTLObE/HvcYh
x3OMWwEeMpSa+gEd2pGQdW9Bz1KGXwjQ0iInNbySCAXrboyT6jxro7IwN/gL17IjQTo+BUcS/6mt
Gatllo2TSqQDknHESBOZfEwwif2gXeK915iZZYiHWFpOw/3jXh3sS+J7P4cmEGCmdja5zhZ2OAWm
9HD8Wr0GJXD510ZIeWiNAb/yMHAIdvzaFhwhZ6qf8g5WagSg3OAqBDpop8HJ9IfViwx66uvitJlA
jTkPg1EOE7hTYKFd8qGKrC9G4iyq6MuTFfC1D2orZZVUBT2Ud/hWKB7gWnscp9XdlB1tM0chPPF/
2PBD4XGkSLpAsYl1/gNQmZz1R0I6JxM6wlsnRuISGK2eX51Idz25HQ2p7eOIaZfudPmI/yoCu91C
f+8RKcAXKuX1YQzZ16K6PEo/tu2T1PYGgCs4SKJUIRuxZmnhcqxTMf2fRjugSIG5PPVQKsitLDDr
btLLyYr63KlZmzoEww7eRk6Ans/XGH9pjNjmiTNsxET6NAVs04Je191twpLV4K002YewW1gaWR1k
Gi7WaUCXKjSPELv4XihAFe+c4tYLn5yvAD5DmuhSMRAL4meQA1wO2tZKxIKQorI8dd5JxzcxAjrX
1mCk8om+yAvH9AMDEnJVWn1FGvSB7TqhvOjpnXAS3rMyb90WMfW+TSRuzyusxbHRWMBolSDL7hfG
/7iNfNxNKQ5WeOWztKGxnxVPgYI5kBv/lgF3wcodQX/kL/LqDIu9cqcgKZON1Gxamfmf0A+MyrBj
pYRjwp+jMjYuvA/E8AueJ/PUMK5g4E/TpmU15gx/nMEUngCYHKFBGfvW6kkICwWV7riw8fGxjxyq
sHAsArTWi/GfaaVwBqTXwWo7G8LSeRvaFFAN9nZie0Vzw9Tczm6IXFTCoWsH5xyuNChCTP3+BFxI
6gwhE/6aCEH32kE7AAasoIyhVP0EOTGMOQl+a3HW5jSaN/ytEnre8FaFSux+sZZQspS95zOvu8Zo
BgPHAPepPbjj/PvRGjORY9VWptNusjYM18AamXERSTWUlFhGKEBjJ2YG7fP+cGVZRjxFY3CmhfW/
C0N4ESPBpRyYsGw1WRtPXoifhxzYVrKKwzjatmfvT+fJ7IRlyeDMhyyxfLX5AV7ZOaINDoxMgVj2
pzZdaktYGCPvwzPwleuWMZMEjJSO3lq/YOfX1D+GKePba5svJPcVcIfAAwVRIf61VXmv2gO1hWi6
ouhV1tqSFKFhEbMe9PO+vc3drO8MtNUq8B0ISMOM5QqBLKVVFf2yzKUJJWsv2ShnZ+DEicgmtdYb
Bgxaj5zZDigZNbsIipJpv8tLXVI8gm9K0pHmDf7J7Rdw2xga9gDLxaV4VunhMGaagwQDAvGVqaXJ
s8qIkEc1TEoyGh3UrW6qq8FyAbp7glAPMahWfaH+VqhV/z+FAJaQNpfRb6oKM/w/LGh3Z9Bg/6nh
5ZPaa+uOXN2qc9Ru3wQute/ZvMIi6Q3hiOyvF7ATUQAjADDKdy3ClBDu/s7b50b5TT4Q1n0VcAni
sE9f+MCgG8VGumJhM+EXF9GKvuqVoUkU3h7kphVkeHUxHTVNB2gJrxtwRBZnN8ju555V/7dtsqRr
Z+J3Gm8kry2HKRX+nuwF4efUqMszeRlzyug9JbrTekjpdIeCHj+A/6PgV8QkDpKRGqOlem1CRq3z
ThRGbME2nJ/MJFa0/GXtD9U3VRDx0UE5cQ47OsWumBgV2BWsRNQaDgjEH1AsShzC5NAcVT3xNsrt
7sUrO2snFZ1/MyYfpQRqSca69My8UpRfSey/nR3aMMinH2n//0TjmIC3iJF5skX7grybm4lx47IK
zanxBZ1aWZYyEXjBhgSH+xgsX0G2rK5NLQEnQDEoa+dI0x2IBhpxm25Xiqru39rcEUg8wZ6RHcRx
XbGYjlCf8IK1aQsacI65qK5sz1pMmRlFWSJxrXLly39Awfa14jshAEZL/+iKOLaRAioC/JH0b2Kg
34lP7mvaXMe4yptCq3fQsQpYHrVG1ZuxlEBnhZAyh6tGdOrCILIJeVXvbM26Xb4yKuLwbCFTFT3f
f/Yn9MqFw8LRhLPFuaw55+W3IeyJ+Sf+tbFqt9GLLllSX5CRNO34n6Gh0x080vx66ODWmZu5NIH9
zNz8iySH4EeJGbMKh0pVpRM+/Me2lb2An0AG9TulJ3TRfObjpoDuKJQLZGAO/mRWqtRqSYgw/xw/
RYosTVcHwqPXNjCuLXgtt1uYdZKVoEQVudncIHcMGUjFABEPAovC2xVVJBykE0zZrXQW0aYrVgu1
kDfX+G4KjkEZuKD4rpmXDaY50Pa/wFprbj0ThQVVcpJo/DkGLU1uqc128f29UOToWWEJcp83ySBL
St7wlHDb3cAXM49q+vbODBQ5ibyZIWpoX/b1+9M2h2S0NUst6jZKnUuEBYSG+QwhycxiHWvLwich
1u0ioRxS702WLnGafZwzuCNt8o5Cz0qtc2AExGM4WnagIF5k8204EDGB1TwmTsEtoW3nJ4RIatLQ
SIJj4i60YL8Ev1G4plY9qg57mALV0w6dQWu5UDa7kJSmTFcdLPly7IneS0LyQimDfZ63VB/D0zQl
rj1trEcA0KLWGtO8H5T9rn5Onhmhoo9eyXpZ95IgdEoSnJBIm1IDYj+1ghy+HwBE4u4K+gub77bn
VuQWxqU7Gv782p8uAJkO7SeX+arp73ZmkjWn5A5IsIEJzLkpCeUBQKBia2FxVUiw3uWUnBp8SWzT
yr2Ib//FYT4fM6wcGIdjmZk3/MeyXeDVPbaGiPcs14StEDgqgw4qXqxi1o9oxbTnRJberMrxAflH
S1Sk8bgCy8Dl1YufJ2QBBEAH/qvqus+eTLrChPF0rOwMrZm8br73/rWUMenwM9QTPIjhGUyvVk9x
oBHnIw4i5tcBkjAQ5L8T3KdPt9x8zFo56JrI2mA+5IUkcgoesjNw+ak0xHVk7KvcX/457PN4NfmV
SJuTHrPK0CF/wZEqBj1+j7QCFie2ka9tI6j+0ixRLsv3JMADerzHjVODhaZH+iGbMNsAGMPKBIPV
lg/ME2xBh+fo7AtL6PxpmrthxXsx9EXQREas48td8TN6R7tpX4xFY2QDIfk+jNFI2KwLPJ7r+yHT
tMHJ+wl5RmluvyrVP6LmD17eJUC13O6zVaTbQqqh5DtKD+nnnNz1IGyvu3EfEn5MFa4OVsDpSW7N
gl7F/JfnATUcyvc37MeTcjhKTS9tpXmE7WBHeeZU1e3q2VXTTJn2L6Nw1JF8HHk6r5KygG7HLszt
RPf0jS45XQYQaDoMCf15zf6sc2+HwbXEuZ42KFdtnbj/ROvzX/MZHRGAmayLxEaP6zfk3mxp6WFJ
nyYXzuHayrO87RnzjjOin5EPHgwISuNegzLSpD6QcTonHf51ZK5N8Mu1XVkG2jlu1dm1kwroPM+T
Z3KyzeAvR7AxhkoSVhUDKDIiIFtQJnkub2bXQeVUvbILSGV+wkH5JAiFCjfIZkvljT4d9OeSj3aE
Ts9rosiw/ljbRccfrEwautKKMACXxBYPtMZEcT+saHqjcIgUGiQOge4i7Xtd0zN6dB8gGcNSkXwg
yU/SvZCgh58XVeKd3UdNNGiv/E94aOyDb1/wbJ9dFQ9pnJWlZlSXzaYadp3jbmTFzXQyCo4gbPHw
1UMe5SHSxPUOQ9AlGvTFMz6Bycst53gDtHoJusDUq1VSZdpmyk/hMTx/8z5IF+v6ONJpWx0zAn4R
Qz18Mu24o6eAhlxpIJ92c8g3AQechsLdEewFX+QqAnRx50PHD/xCGOcueY5vAXZC1OvS5Wwee90G
tSGeEBHACIhdZeI5vqUhFRWXGHINbUGG4AampzJinWak84UXo9LQIWCjXEvjMUpYHzN/H6A281bN
nsQKLK4yE6eS2PEfSJaSoGC5RkvPolgETU8OS8IpUvonRnEg0AZp1bVlPPX5fW4KxGM4zoeOjH08
sj1frSoe9NCEkU18BiUUTpwrrzh4TcXrtNvhDWkMI2VHsjLiZPyAgzPqwhWk8WJV1eksjIL9Uyup
VnRc3O5Ic10aZ4UUXq3QsifBSVV1GwyXULKu6ZadwWe7dhOaIfGz8W9Lk9PO8DxrCFDOxcAe1nm4
tkUP+0go46uoeIJKa0Oopwlc4xHKpb+j4j7LKcX/WAW6EWL5y9qQnuWfRBMzzwYhVliWxr/opu2r
FHDFl0fOsaSnXst1kjLYsuReZFxuYqDs8txHy4WaCWsaRAUxGXAOhsLtY/Bo1XPrVdMGl0uFx+k/
khUUoLNizqApSBl4Oxsgz4oiq3oBoFtOTWrwfx+QLC9JdXQ/Lm36adIlYpe1gRYAT432krkUyrif
BUV5HNN6EvxI03a60oAbH1QxMcZwCDp4K7it0fi4S0s7IR+RbPT3Heg28r3RfcEN6cZzLWtSHJpO
o4z86766m9q4MK68EFBj4waVL8xSZ81DWiuA8H3ZsnvzmRDjlHSk5UXDUt2I0ERPQ2BskW4/NcTf
+YwZllFMa+05E23LrVrQ6fnS8bZoKy4+a6C6aKTYKJR3oZH/vRCgcPckoI0QomWBXE2QT5lE0z8n
Iu7r22pllEIV38BvT8p7UyarDglHPCwTKlDw1j/hi8ypUAzp6QmXflO6cADxVuD3AUGiQ0Z19hF/
sQDj+lhfXADKmhsKr/b6jdEP12Pq3i9fSLs19Qobhxrr8FJaLkqziPiiJX+3BiFWp0rzt1Xkdi4s
A2rnG/agmX6uPujirlE7n+8mGVm5zWIy/crAJjEbE0JqER9z5s2WaIWzJ0sLT3g5J8Rx6mH4ATY1
Jha6+6PeqmDarWbXrL0MfmmmXSCwQ+djuMsXz6EtyLMe7SZLWFaU/No2+PIXvA+yYAO4pav0LBBL
vvg+L+UHQrP9lG2YbGgH5zpS7y2jxthyGTcbxtnu1u8p5SJhJjMme2IilVEiDIGqEusN6R64Ecym
HY1SQ+UyBHI0m0k4aylvT6ejfc1it7PlxVgGU84GLyk4lT8qLqYyTJEwFfNCaJ0wbpmzkUVgkBnD
qb3/4cxGTGVxz120sHKc2EHol2GeqXC0UYfrOv7a5hlE1RrDz/Kn9I6zhfNDisEKnGo82uot4Om0
R5yziKOHWe5QCgKt4fsHzl6NV3ZxvY8pvfgmIzTnUYfOklXflCMtQBEu8xtOomXKuy6qlNcpWQlK
6fEoBYY8iIzURg4c5FywNOl6W+qCMkJ9/OjLtJCi/c7FwmyujLY8LP4wxE0Ucr+lHDO84t1ZKpoU
IqpbyeqxuvcmdTuG2tLDDnNjvT1+IhU447U4y5XgyOnHx4+K50LzVvrsJ0hrjHueRePRqhNAWJdn
fXR/BA1EsS4Gk6ZMHxG18jYt7un3efYUZSd6lCKKyh3gFFJUINcwfsATTUlWZMGOCCk5aNCiZ0cq
iSh7ADnT4CoxiBhMS0nNdBffvntpulx2AV05Y8dHFH8nRVeOPADEYbVJkmNlbbHo5fS7PLR0fRmk
UUt0Y2Iwmy2+FMtkvp1V3kNcz3n68gjAXx3DGs1YZCDqfoTmtT4PXj9qV15V3X3lWq/cl9D1OfUk
UU91T028ycan4z3YOG63gcQjYyhE3EEn7qeDFQ/K7bvpNQZhtxTCdcxycgGHjTiLCOmVM+aywn+h
CcdZfxpnk1PVvfFQR42Ekjq76OK60HtO+iL8btda3fvqGyQdD916focNRp1cBR6ct0wNxFCYnAH2
iqetan/CmK+O21kDGrFaQftPOCV6TAB8kDsPHlXZNjo/QnzKP/XKoixzfc40wFyICU2wHxCEvM7l
3KkM+hsKz2D4PDzLldBcU7NMifn74IdmKGfhXbqxQwRTeKPq7azoa5M6XLAFSXhq0dhpiwA6tD8x
Y4H590N4fALIliC5c+iyL4TsnU00m3qr/7l1mYpgk2tKBMChYtYT0DQMfrY54vPX28ADpvEIreTo
ezR3/Bncah7fNpp9hh75OUFsukifaAYWn9RXreSp13wchdhw8vSsWhMKhRTSy8JuMfTqm9sb/wty
0tKjXGaq4rcxDU3t0jq5jX5oEFVcySA0y+QArGD3AGZtVUvKt4WjC+Lp/Q2Z8xgiPLpg67rXDzO5
l6syjLjG1mXAl9myWGQeW115qtnxaltkfHdgcWRsmPqpFO+TGmShRfDOsJP6O+A1TFsKlheVX1Cc
ZE2MmnM8ucmbYQWRPQmB4G3Tf+mkxQmsKUi8dARGyrgW3/BXwD/pAI3979B7VCt1bOHqM5TYQ87W
pi9F9vk1x4rUd6/8Bp9J6Bp6I+LyE9DQ3SoI7xp+A877Kwz6mEiydbCw9zAyQUnNmEhzSPrH0+3T
ylHYCf7kA9S2O1XfnfRTkXfceeNGV4DnP4YtkVLVeemkx8OB3XxxPdm901B0aujiJbm+SMtP3qL0
fLuT1q+iT+4UYSRaN/oeOaN1bHABGl3aQY8OPI5LvzaXu2nNK+caSr/RnB3Zsq7uKIEj6Nkjeb6D
jAz/UmjDo9WCHYMUNPCGA523Bko+9pTZIWYU9TWIQiWru2IgDZIgbbEwGPiEf7LNlIhFekeysEBy
0fuMrr7nUZbeQNnnw2tQ2PVAYz4r0mVJ1SSCx+SBmTbnnPFVwTQrNHzgQEF8d1zZdTwP1bDEABsB
0gT9gxo0mfejwFAvAtnUPPdCRvHqO0OcTBhXkGC2lXutHfLyyqGwBZ4Bgha8PaPkVLE+ZubJwtJ2
t2Y3LWSSNoE9oVtHWBno9MK/1qBKM4dDVBjmO4tF/A+zDNoHX+85cY3wHWArtYcZrvvkxDxgOAfj
DFMP98VfW0mYETJweR+cMPCxcTj/6oLW9WICaJ+4VR+293pUISD8u4L677uJKuR910M+9mJnvs31
IjfY6XLFCBIbKnuGahX74+C+LgTdebXHH42HxU43ATRuTgBiYWbXN1XC3zd/vky0nLRjbKIT+ei+
BCYlKOQQQ0VY7AKvShohrVEwr0mpSJWfdiFS4BpJrUTgsqg0n+Jh9fviewcztQjia9uGj8uap1kA
LZbCjHmhiiQm6vNZBT+XbUS1kZmIW3lfv9e3e6c9zPBA6YtpnwJEDdHT5a9kFSBQghw5NOQD2h/z
EpDG2A5mVAWE4Cu8eMYo4kefrWLjlEFi/7fwUAbfsg6wgcbvcWIJwzA3u6o4EiYZJCOsxe6EVOrG
C+xpnUclABqCyVAmsZQzP7BGfDzMlJfSrVF3XtjX7r+x+ertKv5TsQPsOKMxG6jBpDTXKydCMbKs
m9pF69I67R2Algl7bHJBoDZjHvZVfs6TadMHWJd1+Wj4Tt1f2DNtdR/+H42lcWZnweab9erIfKr8
0GSsZD8KpQAxhTxd6fm3EijjNVXNSE7h9qD4+ZaMOK6CBAqkKHfpppg4IYBW0hijv1YBq+WzMP5S
ROH9e50sJN7HNuzq4UFY+mG1eRNWiCHSqDhnR7BGa9BZ3rxR+SgjH6pn5PnZt3YCynH7Yami7e0v
TaMXKKPefaWYEU5yIEiRVgqerCxNj58B+mXUh93+MaUqHfplzKMyTgAIc1ozjE0gl1ymjzP+mdCe
q8voOliIE1dHUCtXUHdVWapKYSp5YcZaVccZMnp0sH6VXyt6CB83qaw+xJ4x6cXMXtIrqKLrDfKa
P5iafNv+xQl0fdUs9iMksEgrEg2FvPrNilAZ439fi32t337om3/np5Z7ESeDKnhpOJtwzMVkcDoG
/COuPDd90yBTaQ3KcM4kJSIDem3dlT2Z3tG9J+1M2XBS9/6bRg7sMLdwqQ5oce01EYBd1CiOEBET
BT2MKRnKuheUhAy04hCh/xNzDSEmaKR5CgoJ4eUcOdvD6gabS/1xc+QBhY3ge/v+slhK1dntdCXO
zq3wfQ5GVwCSmWbL5d+nm3HG481J4nGD9zIHL1FCdGcLjNYe5VDeMuX74iVmlU1wWJ6n8HVwrxwg
e88XpK50J5ahO0KU7uH+ZxdIK+he8yK96dKzEzz/XmkEm/oFT4QeienrCVaVlGgTbRDglg/jF76G
8D1nrEXoCdteo7+2udpiPn/KJ2rnfdVKT0Vf4pe19qRhgeiCuFERB0pbm07OSzRL/8Akk/jq7g49
S1Lq8kBo2dTrLfLYnVFCNLmuwgOL563s+S4jXy7RWx9B7CvEv2VG5TmHYGIRzh4E0boy1XWr5kDo
o5Se9n9T8+aRpvISgG8T6SiHcB4bHTt+dlX4vAnT9rptDIXUryD2GMs1oOIweX6Ug7DJZ00qxiD4
QsvGWZgnnKT0Ok3/HJ99jr1iZREdgwuAi2h19fgWHQyu+l3Wm8prCih4wrE75TnhCjnKKTuMxa6N
CyYU0Cyi+QjFzZSLShy8sk3MPr9vZgjqzBsyetHD023zmYLNcw/MM/AxMloEp4g4PwAgLNhEGsrX
yB9sXkfCh71zCLZnL4Eb+zMLTJB4c9t7bwKDo1DTyb0x/qTRC+BDzqeBRcvlsD2damy/LAFWzg5N
rquTh8VqbX0WTeCluqtWhyW3G2nDJEBHhpCzmyFDEhZbQkoCk9fqyS6ZY/YdTuw7BqWPjipGoNFe
HT4Mbwy663vd+MI5I05dZxzNp2RplRkMgpi0biLEwyq3op2qzLwCmqzrjW413kuqEGbepUxNbHe9
bSmiGjVkTLSmnpRjtFQFCvZ+x7Gm/pyIeUr6ZLNSYorGnLq6MU9H6gBL6Jk6+ZViUP4zbjnEA5jG
+yzcTykeLfywW7ab2P0D1Ot4EXaw7K9eOLX/x+tCAmBa0G1rKkDhF9qgljA8ZGjNZS8yADgIye4m
PxLKPDQoJHjFewAIrSsY2RK+JHwZAHzFIBA0m+3ktSkw6eGhA6dHGu09AeSyCN6AHQNCZWpGGTTu
2IDxahp5sJEFY9X6aht8bRmnByHQxE+ZPD6nrCY7ImPtQ7RKFpTfB4Qdzqc1XMXkvTGytAvgDkQU
IV2Y+N7fANLMEeQnqoLP5mffzmpjmWWX3NJrFcuF5EVgV/GrgzqjzbTqVh3vaxc5fYLDsJ6tp23y
UNNV5bWpmhNWCIW/fVJ4uoWAiZVCKWu99aWfUclVcT51WmIIifw03KB4o62w9N74YdnAFyBjBrQ1
nXxENmPlqwhp3uatv+aSRKlu6fe/S0H6h4X6WTDxhjUTofqnhT5C/41CaCnkGV5IhyGN2EjsnA3C
8mK3ibSslOgjFofJAELJ+Adaw88l7arOr0kYghBvb9W59TwSWr81Dcf51fdJ5pHP0hjeDnVJcDmQ
p18kq854Mm/Ufjw88LzCdY3olOZiRGAaQyFuSELlta/YFvjDLlPZwhJuO7Zu74pJPuiVCHbg4rtG
QrO5CiAUZpxH6At76tO31GKdhgolir3cz4Vusa30OV0ip9f0v0atUQaqoAWllHsifz4WPH+Qdw1s
ysgab8loQtDcB9ZPmfQ2URkvRasEPBxx/sLnGUzrKLw5FJSsbG3HA8LgFJvyLBtcUN/EMtuHhhiY
gVEwdXqlPiwz8x1uzKDmoUqQdLV3uvDfKyt4KkhWNF1gIMUkZT2aptOcGzJ8Sjai9+evPj1OVJ0j
ALqT3aFJrVnMn06AU8DQGxascZfT2XJaiG+vr/i8q84SMKsR0EmXwHHH6s/FhmK1LfRUfUJl3pC9
GQgTpP/sA7ngZAQLUH3/wWR1GhP61XTAY6g/tRdmQ5IXGdRSycGw36lxN8lxwIvSNq86wFw6rIZE
SEZWSQKZGLwl8QsGwjgNNNc27rIa1FpUg5Y5WznZluagAKo6SPvKlV+pLe2WKAkV9iRMnPbnZYv/
aapzTidI3iMmy09/xCOyl6prbOiy3rVZnhL4VL/7S7/KkVkkyilTKfhTE1u/l7BRYeek64FwhUor
vKxc9XBIywXMqKTifYPJFgz/+CwCCbuZkV9ZBEytMv15uz2Vgl0zuN6s7f7zXkBMNx4GCcY/286e
MUnyyFE1hc3jCipkOR93PrPkX5iVO0IjGbBbvqKpRZd14npB52mc6028lwAam0dy6Gcepdto4Mwt
ZKntMBaPujvOf+MU4z+9/1Xyg/dY4ACGUA31hXogWmM5JY/dwFfMrTyGw4vXgsb286ejmG2iYK0j
APlaeQuu4pve8C5xso5T9j+pbJpZctghVShbg9LNwFKWUoQ+oM3XHY8dj5h662TCnRS7YnUJqpEF
3E8jTrezb0kSmQDrC8e6glUU3GEcZCKwmEu6/CiTBuuydHjQOE6is6TEkrDy/13ZCrBMLA/DF4UM
AjYxOPQRNBvoIBmwg4JVNpNr49tQMMzqBvzc3MgjlYwAoTPmy5vTkNYA66jiM95cr2k422Zh8EYd
5O91ha2tbxz0T7S8oCuSkdcBohT4ZFS0GU2W7zHc8cfshY6eSh2/1NJgIRBPIRiJvp1BkUZgw8DM
5XPXHGLKLFu0iMWTisEQ5xY3yLUICHkXfWiXVrr0VcZUM55LtsvXMRCoSZ+vRo/tkTIRur0QdjpX
X8QW4auj7VXGsIX8M+SmOkFDCAvArl2AqNzWvqh5ttcrfdxfPajWKYfzOroPp6ujpkXpb817G338
laJZh2EItAj3zGSkk3jcdpi4YRK1jdJzx49SRGkPOePPwRo79vq/Kd18RWidXmLOpksTQW/lpAfh
SQlY9f9LU56HVXqWiGx8jNxgFQp9fIloof5jA61xb7D6Cxuj7IDfhq+XJ0q0PcBQwuO1UFZ9AomR
I8pGejGB0fiyMFeX8BfPony2tmfc5H80uXn9aDserD21lUwGyIP0uPhwoBkiDKRPUq/7uqatIHzk
7szz7YvuMKDzJBgzbO7lyAiOCDmVFFONgJc4xutm4FwUCzaEy9XuSRoX+BAvQIkMXZ8YoaLcXD/s
SjwXAr3+PwJj7jxGx2jCF70X2fj8k8ucnWO+ukB8ukveBnzMwqBBa0imPNXmCcQIXT48Q+Iwpduv
nXrYrwV2P2dgQU/yW+eGDRTt4aJ2fhstoT4PtOsBST7trIMhE+ner/e6iZfP73PDKrGL+SFxE+S+
pHihPZAGJTZvfJEXhABdi1z6Udw5H7D4NzRQF1p6DR5QEQsvg4fqjQpjjaO4o/uuDoEIWxzUJtzu
pLALM4yqoR3M4kmHxQCaVbHuSyFZoXtdTD9nRSMiB/pNsGxZGH9ZKgaR4TZueMs4tSM/KAVRu3oX
1QbyO5OhUTz2z7Z5CEFLE+hzfSvSh8Kx/T2OBsV5GF4SUfuH2DT7baeZqAmT33pJzOjFEYz1EMoY
IDQIIh/r48y+Ae/LC75g4PTsgsoEhPyxHgKXGcZyiV7s2ovK087ksHeWts9gWgkzglYFcwZgUN1A
PD4BkPImtR7s/lCEuc+xQQbz6SBEiB6VfmpLzJj/WnROwbhH3MdaxFdKv8OuY+okIbna56oIdlLB
c53USQy+GjcRoHcS3uwD43v9L4FdVujL4If1RSJsvMDsQcaQNGbU0dYMnUCM8tuJU9rJTawNMxBw
XF+Fb91YIdKp1zmMcywDScn1Dl+vTnFKdVxz0sn68G2WohVe95jpFVkSSyya3gB3ncUrFNiRHPQU
f8NMenqP9ezi0hsFUDWwU+MGyCwgEHHtgCmRq8v3m/53Mu0juz/y/hzXjDit+yuntzNfPSAlJ6kr
tfj1LGv6gUgMABA0q1SQEIktlwDNWG5NmDgeeVjIZPQrLs+ZLpqbaytK6Xuh5SYtSAaFt+tdfYMW
VIcgpIlIMSONbQc1rAdrEtSteuJVLnn3yWz2damsMZuT1MBo778C8S3E/J6Vx51aeyyWkZyFIdwQ
hUTviIIX7jb/kZw3R1+YEqJ4SoP71jACzSL6e5yo5FYt47N0eXLWij2wYUz98jofz4FDOcrFBjSa
Gy51xLM67sTW/i2ybl1xkVKtO8CQF7Ra5Z6hOUniOKAnlzee9WgrDoBa640ZB8xNBX+KDgxsUdiv
5UnnqZq7ZTMMiRHLw/xq63wvnAyqjbNEj3jqZZblGHtziEposLruz7ATwjwwbNbEc/NIloBBdFh7
L+vMKJbkVKBOaIHNYwKWGtp1xmMYy/gTTD31pB1TsmA1ZKy+gd/1nObLodxKhcnmzt8Lhirp86uV
Rswrx4C96RjBz0kfs4rZn/UKqrnCvfsrUdvThUrv9/FTk2EfS321kjLyaIlfzNvyH5D8H/3R17lr
OJM3AwpP+n7udauKd6vdm0kpDecJBM1ijd2WAbsEW2bK7gSaqG5S3fVDlfATDfey5cO9Hq4HDKAb
eYvu9hqrDgomu6uVPWwq+eYbCJ21sj1g8veaur0lyalkZwkucDaLzZ1dYvu9kSg0zY8kjDaVVe9b
BQQIJr3SwvGLUvGeNsqRVMA1BA7YQ6RK47aOpnaZxdLpIjHoumzI5BwMA1UGvkAadvumwF1VOikK
V5o5AVjFhWVn0/9tH4cSVaOe0koCnEuBKw4o+R9jZ27QfEsNWbIDXJF1guW8SbmdTfKol5ZJxSP6
KcwtQqaBvBXy2FG2l6c0Xnav4yR/DDGra66kI6geu4dnWJPEXbVrpxTl+PgOc/P5CjKSt/CSR/Oa
IoDoWgHwj8lj3h2tNk2lFoTcWqI0sy2r7JE3ybZXwhARYalzRMzexCS1oagfeibj2TWiunduW74g
WMQruLCfgkFNFFGOlTVyU/Y5ed0uBMkbbK8Du4nwWcfFQGnKz8IsBrMJMV/91tdj3pUVcqO7bVwy
DOs5RPIOQvT5BsnZ5/W4n5BQKh1fpnqzgimoRhcXd5rxw2oqbO+lBK0SuCoa58h84yfZzWcof0sY
rcQRR4rjZFzt61z6L7HEMngK1pjjbnC9pqXKup9bg5ONL5gsos1+cgNhowToqfe48B2RpO5uoT/F
8W6FDM4LBC/ix5cvAen/PnCpmXGFAQaBeNv0iRrugmT024URBtg3U90OtEtv9rqSSz4+MWwi7VUz
Mawh0MbS/pVW7xODQdh2zmzKjHwwEQhuVzuyRPM6XeaywdS/nvgWwNuorZFWrR31JY1pDlaBv3TI
lrx22/Xed+oQ/SDjEr0mOwjCSR/JWF+sxYrptWvedjWuSGxPpoq7laufbvSy6o0HxVBOAqfvfozc
Rdb8rTWNGkVMLH7Pw6e4tQxXM03GuN+6RtnPY3Epp/T17B0QDMXCdeJ2nAXZkB74VkO/WVnjHtFD
xRufL0t6TXNWZiAgi+OH7kqGjZqcFze1DHafX5vTps1I1cfrww14hNKL8Kzi5KCn+ICdHr4QyaQo
x0JD/5fAKP1fQT2tsoCUPMb+ruRLkda2sV5d77o4d5zEx5SKKpuCnEe5qLL+Kte5OCE+VtA4k3OH
reqGpD8XT1ydDOGvXmIjU4N4jk+sReiDl69ydNvJBzKbf77WZDn1MJU49aJrGunWZanZkAxiNZhF
A2gHzU5JfrJ8xGW3t2WxUUwiQPo/UoltJv4ERjPdXnKWimWshSUbNOM4BEzDHsJYt+zV4IaTffeq
NciTEjXP/7kvsUeyLRnu7P9gvyQILgJUslgPezbEkNUMQzTTgF8eqmfz+jvNQHPuhIc1J28ixAHb
/8ip4CP7Ym6zUlpWGhfy2O7R1w1xraSr8+dIMhWPY6NdZxdjgSxg8hV1v7+UHiXmvAcfUTZCMs0v
Xhl8L1SJNwN0o1xdwsCokMC+8KLLuxyULIlFy4pGhai6Foylc+SGLen/NsNOJHAkAI17/RQHFiJY
7Zq2C/JORWKvK+jkuqwYFWqe3RRkQ3XsEQGgi6LsMAH5dedqGlM9yUTdasauez5bfhPIR4WLXQIH
KuCHaijBNBRFEtntXCgv7AlXNglr5dmN2dCzgewpNjDBP+gb8DmLAZ4xUoQbkwhPnG/Cyy17GStn
QwnUyF8zr2BG5b3GJdQnwwvi+DB7vnKvCemC33sa97Vn0sJ/vtNquT0/pLAeYMLS+XL9W8Lvlmx7
1wZ9V3ScJdmR9E/RtzHSTahyOxaODnVRp99soU41VvT64Y7YuHm/iO2kft1xEyVtLULMVKqCORdX
31eWN4jyMfZlDjBLNAsdcB845jMbty2hDlG2O7aokmmBr8hfEwxRhrKQ3qrXz0hL687p0fhuz6B4
PCCvXOgA3oN5qiR3zyRTOsUO3TgwtcmTgomw/Ho0CEp73cQOL+LRkznMTKGTllvxAw9AYz5qf32k
pSlUjb6fgXpFaoimTh6EOdGsxi3r+foOoynR8SYfupQ34iwEDywgutxvNoqDWxhP5ZptkIBBAiRP
RAJinROnJBbkaStSocKVWq2toN19XHOhfrzQUckLd4b3vEycWzDWsevmTkn8kZz4YhXXv4aw/82L
78YOePUC5yut8Cuz9nBo77DX+CW5ksfDLlfriiSSb+LfkimIJj8HYah+GBALqmsu5Qk488noKkSr
uu+BWuknI1iSNslndsS4hyBgt5k3xz/lM74oPrpSsqgF2H7estuL2oipHJd8zF0f+u3wwFK4WC3m
R8HlF6IwGAZmkv3OVlND5eLEIABbDqp72Eo9ntdrh2V27GJFnNy3OoHSfXfjojDrm3waVD0ar0QN
49wOEg9yOhobd4123W4sBztPr1YRGBkrKstX/5cHm60qbtfsDMuEWgkieIKBKxgK58pfY3tHpI8A
PUn5tUgZq8XPkIJ8a2krXofmnGpgrmHk/yNmsfECt3Q92mAm6gHrr09l+dC5UQAQoGlmboc242Ke
wOb1Jn42HKVZB+5HG03ErxlPkG9Wrkde3fj3aIpiH5znX6IX9Yh06IGf2XGlZ8fHt8rk1J67UvjA
VOb6wtyRyiQibyzaMfY7eNngy6lPTYarx7eSkZqdMZAnw6dlypS/Dp0yYlXlQA7MFKKxieTDiuHh
vGpOinQjBBHd54A6agHakT4aliPfG4wOQevlcAR32IE21vcXn8xAzfJgvMBzRmMvQHtrY8s5csOR
UlwTmoZgbYTODRumnxsVbGyvwcb2XDT1BHN6OoBjPFj9XmaC/6zR9CVAwjg4sTxN8gS2HLoOYP5g
ruADWkWMgBHs7XBwzKMk9nZz+1S6R9HEAk4Z1YdDySRAPCBG8DWcb6v5aPHEl6+Z4fA24h46VcHR
1nnFcxCHqNdrGo1iKGqxPO3tCj5qlmmm5EPB67JNIj8AtViD2uOpNLYqkW5+gRJhjYv8eruIokFt
3iR0Upe5lTVjvwvAKcWCe3mTw+38mtKeKr89w92YR9EsfS2zq3ofLDG/d4DvbR1oSDwG+QCoQZbM
oaGcJD1MmxaFOeV2a4A2rQ9P7jIz6/Qaq3KHX2RDssgV4iJ6DnlH5QYqV8HGM8kmEHOO01ldyTOR
Ywfd9iZZAxrj8YFF3qzP9GaUwgOn/llxX+T3zXoCIp8OUwh5FNUdi2nxONQNvpRTI6GVkiulCCVM
01+QAzEN7JDn1qQt+WQGBEncoIc2xqnCjHT3yvuu/lzhyDScMzDi0axV0iGAkvl5tzDB7g8R7i+9
t8NufSD13q18x5K/HGqtiiMXx53SJr7/B9M4rqwkFu+Y5jYecHbknS2x8hF3JtRoc3lu6FSzf0Bw
7bLl76bX1R3Xi7IyKnKEKtgIZWVIUK/okhcHS5PLGlVyjxU56lCRnHZghBKm0i0AhRiS1f63KT+D
G+LYJQCko14HzcIoByXeXlVkbJ7bPZHpazAy68ekxsCMjPEys/VkuE1zqi6Z11qFVqTenAqE0oR6
jSdRQmFkxzMsmQGN8vbUhFdBoicOMT7HtCkLf40porWWvYMa3JG1ZMgNnzmYeG0CB/OtYF1ax3vT
YOu0AJQPMc4CucZk1lltwMg6x8IdrE9cs9qiVg1eG/HvWDK9cSoQceEWQrr4Qr2iCaRIQWpekFM7
Dq0dY78vy6tLdakaQAdXGjUiQN1DLNG0c4xWBSOtgL/qz1T14n58NnBWIuVAq3jWeOFuHo7jY/Jt
WI8dfDtkzj8CLPGwaZdSXGjZ08uZgdNtXZNgvKCU8yIiACq+6Gj3VtTiOhQH5Nkb+7LAl6mHUtBF
Adqwu2sBCKhWFnPtH4KdQEFqfMzjs/P2j22RdmF1E79q/2llt0FF7p5VQHn3QWQS795TVdMmiKkc
jwxTLKD4PKSbROe8leklQYXQgMvp1OUKNmwnsRC7PYRNmqQw0l8kz1gpfMhb03m00Q+6CKK91ktY
zlHdTG+DkwRibI0JL3mOW8G/fmXjn4a/+9c8ACsSuMgvxW8wc+TMQOzdb1lcnW5lNlQgPO1Dtjpq
HcV1BhCUxujocEZuAo6FOJ4yplRX11XsXVbvv2lGhjL97mFI+PedYU50KIHdtsWUB3ULHZXpvLHf
iYHFblfpNvrw292QTC2NxO+8D5c20jBGopMXZArLJJaN+RnLQ04o50HoXFJqnfN7taOLXiQ9UHcP
I7ioUnDBwllXfxf0ZPMf5dwl6O3Mk44JNUnZsLj0/1CBo2vmp4SawMGJhRXJzFxt5mJqP6ieqvhB
DPE1OkNspPkTUrIMp6kAJr+aWdLds/afsEJcUjPtJiy47qf7EQMSzURdVf2ERDKBp+7cofo5LUKF
5WyyWAg7EuXoq+E5zd1Bnj4df3VdGDVPpFthIVfVWDhK9cMmf2Rhx+eY2BXz9+1TlYHbQUsNTQxV
b/9cwMATVIBh0en4T0oZb3aqRlNxsXlvNMojYE91O9gqv60DbnUkbmEkfoI4H1Bbmi2SlySjjeJK
kN9P9ZHpjNM3+xE9Al0916nYbEKEuwYXWOfn9IsK5Ji9Y4SDLx9HEFV3JgGbbBmQ+lwax0b5VhE5
zOzfujl/P1QpCPoq1Bju8IGhCYglJZkPSSs4tKVtBtaY5wKulUsnzKTr7yR9MDwVg3PfwIaUJ6NS
RbzuU7BaRf4mP/Fp+5vXnNiEEdzT9rf6VPfkJrLEjAAsUukaIAUZXwWlXAkdoWf5iIhfzXZvfldv
8YCOG7beFJ4H5eFOf/z2xckRr4EgHtC9kA7m7nOfL9Z3r46/BKeWEl5Q0l4Uc9Tf13hILbUlpowm
JsSoHoQpvWBBKQdOXN+J4JokTHjURG9WbafnY+DQS91Rx2IMgvVXQULVdCqTnXCZpkMuDU0vmNO0
e8gkkHQys4pml4RnNsHWj28xKn6Q600bwgN1/WapZGqunTKSXFuz71/ULOW310hhSl5uEaW8v0Dt
1CYYQVuKFLlfwypJkNM8ead+78yz84TadtqIsFUXoOywqVOSiI89eYztsL9g5O5Mi1oHTlLEzQBk
QgzsTSNIbNp5LrcTP5zaTnbAOEqW0eK5eZtzv6h8GqxrA2hyw1YbOldJT4Gr0VOfdesRm0JfGq9q
lnedUi9LOQ5W6VBLYOqWybfR0Xcq7djoLTSRGV+tAGv1KDp1VVppf6ebetzDwtNKHLSOk8Cy1wlT
hKM/6VeM2Z00lJsyU/NpZvxm0Os2mcIoiUH2ssO2LF4OG1c/m5wZ9shm4ZUxOrcUVWbu12uIlYDS
cWGdGzN1chD+5velXHIg+ONydhBNq4eu33BXtB+J4f/MHAIVXng4FD+I5Av9U21OB8OeBWEokSxX
VWlZq11V3hcvoF3mblfbSzr7/cpNbkNSCEwNqvCihynA2LvgVwaC5Viol62wBl6gQ7UkjOLoAdUk
uE5bMz8yxnZeEFL8kTQ/OWESsQIjqvdJEUzSQNkDZaQ2QvSiLwrKSiNdsPhYYRD/5LyDvSAHRkBy
/1N8+Pb5hissZeWngLElsUr8yE92WAW6WhUbgQBSfxD4lWA6iSqkEnxw22LAzCShf75wmf4NQfyB
V4409ySjJS65oIvnt832DCs+SYamASASO4ZOjzPinPa+Yy8iigjaLA7QXoXJoYCzJLNBBSIlULBO
6m8oUmzuXyZXRmhZjYqRquG4r6/jR6W8CY/D5M4zZ76KU4fD9GnZwrHtlV3V8r/20ObEYQDqGoLS
dnkHb7lkk4PJUgGX34VY/EK1eW+u1R+0YFywjxD99a1LEYRA/FrLAdJ4Sj1JsrONavJU0qoU0ofe
2yaav30QY90xfEn0RYn7NNTNCLALRcY3/iYqpgHeI65wdI5fG0Dtj2RhvLgegV7+H0XipxsujRPU
dnT4WH1RE/0UdQXvPu8PHUDHUYPjxFyF2z0VlYjo52Zcg3wXrucmEl674mjCHjZohhKYWps1gXSq
LQfFympqlLwOeWitzIMFqPz4+NbmbYR/G7iwtDq7vyETe9N+t9Fk0bqk19km2B3RHMNOJsbv0Hca
JuysgNXee/Zbehv312DojzF/igaeHILUWDp3ymDfTZXHvguKsAC1oLA18cPjVTqTNirxb/cMVv/S
2CWbZkxhGLmbKMAcb/pEf/jlr+snqN2pIbPAqdEdiM8GtdU60wg3ax3YqvM0mzG5TA/eXw/pNVS0
gMd30bDlgY0mTBwwE2emRTcFozlQ4U0Jhesobj4fqRh19Tg/A5uElgnPpvKUP1Z0gJEcFyorUyz2
o2k+H9XLUohI9TxK7cHKPo1Ag88uPJQDz4r1xduOE5QscdOJOVY0duceKpc29Wp1QWf/qn88ZYXX
QKv2GNvouoxIZSA77GDA+DC1orsBdWs+MUzt5XQkLi5GHAd4LQ5sz8kVuepqJUS0tIPzUHFxeNso
wNs4NDN5SCwBkhULxVpP4H5O7Y3ZyB13VoivFhEBD99dJpjQw867KijbE7Yp8uw7rwor6UFkljjo
ZVIi3c6nUWpLaN51G1CMyzPQKFH+MHLAMQikfmvWDQbWW9IqVTYNts9fuHJ5zpYCFgevRu4jXP0Z
47vyMtAqIIXVdgRRYqDz1EihpWB/w1rwB9cTo383+qPF4C4fxl2n6rW0gg+ScR5Y2oF30bnT1gZ8
vEwBOm3P1XknmoBLtfm4OVytlCOK3at11nWgJGGU+PzGEFBWwrf+v0KjCzpr6EmLL3fNTtgi+vYD
fKdXR3U6dLLxJMuWc/DODv9JuPkwi4/+oXYUndT6ZYjX34K5sZjHEIpfapuMjuZgicHwv04tAQAY
xSN9+DhzXR/IO//sEn2Trrhm9AaL0sd1bduEaOLe99S/rtjmkPfbVjpAhhacrlFVYXbcDDxPjFNq
c2wkgbUmc2/qksNifvJq7dEGgtVViU2k1C2X8NA0r3Ohsh5iOVIhKH/ckofEzO/IcbX0Du5IlR7A
zh5k9QaYgH8qQ6sqLi12oyF3tfftFFx8HeiRFRfHGvadsqbxJShz0iyvlPmAAFhc/A+PuK0YsMOz
wukDCkTEXD3zVZWTW++6mH1ATHGkbRNtSZ2367Q+oNjh1GLK3lAuZ16LQSl+DXjce8ihW1STindt
Q9+DoL5fEAxy4nvU/S4YCzW3nmmJl1Tj43RUr+jqM6oOiHZwLCgyTV7rTKHu1Qy2gdn0kkMg/Ic9
mqxpvYnTu0EEE06SqpQFcbIPk2uhUk4vl+WnMN9XScMu/19ToWPPoVXHfTiowhWRwkQvx0gGCy2j
QQ234UZvxGLuBUbr0+KkMZHQsjRjlJb0kWrkJV4oOQR1zUHDJnC8dLcSA7dY+ARpGS2tjxgdf/JR
sQCMJiUlFrcwsgMg5DJgXR3apfX6gT7DBezMFXWnxHr1gnFb1I+VwZ2W/PI+hxsvVKwUST9vvJXb
G4bnVBJVK9hwHFAJsHR/e7E0kfBQZpphThmLSJf4mHGY5A1b9CYAJCnTGZRDxqnNkCMKQ2QHnpUW
BVGZ9BNrlVUgTFaFmUh5jDEg2b5PrHltJaBEjC2fTuHC9gcsXqQYg2ev5I+SJS5ZCr4XLs0jScEx
eIpjH/vGOo6IqDPfrh2GAUB1fJ9f+DM0fUHd8s3njPM5P57kQ7CIbZO1or5kdTKA9ueD1/dFpIR/
zV1mJsvTINkPk2dm7SGWEyq6RgZ87b/sgjzo9ztJP85zyONXUBuK5VB7LHOSfsc2doxmPOORoNjs
t0S+RD70RATpKLD9TfoGwJWNSChmJL96iYRnP9c+/fL+3ChOxjkoocWCkeGS3N0dI/bcMMTkhFFx
Ne29KUghWsYj4jOE9nXTYax0Q7K25/lw7/N3P+1QrmRImcxcuFsw8Iv6C5xmx49/yJSgQbLd2/dM
6p9Ykw+gj5ItmYiQ8pIP0frbkErSzynGc+MKUdZJUh3tZnExU0I4hiF0S+vtXzdIhTiqQOkSbGh+
mvjSgsTYYSkjtRFiAFjOZeNcTJNQqQ+OSIaQvnpCPXUaHoG+VKmKEkr1R94U5KjcoPTF0GQ/Io+6
y7DNdm3VIS08AVX6Cof6hozU6A3g2pYOjdD6PZpqRsBv9osa2bLaPZyU5UZ9e6mstmeloX9EqfkJ
GzKu4YVtJVWv6gOhtG5V/7k3cgiuHA1CSjp6zyKl/wX/tFyVd/x/pMPkbKeLtJlvJPL9V1hsQqLj
G6zmD29DXrSwBqj5tYoqwB4F0Zr5yPBVhM3y6UYQuhAk+uD/41YZUI7MrbmqevKmY/Ur34uimZQ1
MbeEOKjsRAltC9PQKO76LbmDbYxbqZaUTyS1RK4LDIfevAyT/n4ixkUBigSJcwXrRjlaqfBFcZcG
UmrtkpoZiQ4JfsigOgemWrYdFxHG7Mdns0C4LXfGa1KWjmvvhWFeusINgtAyczzjZtDKlbt90QHQ
ZNr4qrrrVVEb5v61xyjqj3/b1cAr9fezneKLItPOVm9JIEH6DsRK+diTY1MyKfqiLdYVanXRwFzZ
V0Xi8FQ957y6ENLav8UV4K0WaUvRWsKul88Ocq7mJDexpyY/+6pjCq1YOmjj9dJN2JmLvKJOPriP
r87eSRGpgCIQjZ9tJo89056TpuminJAC2VOwA92cg/NXoLtZteZ/ThRQ6plKPKg35KVL0UruNKIv
zxPFchZm6dUdknP/6Cvcn4/mWbZ4OQKyIoJR1apn7/FxN9+01XOIuuvla7RODbEMryQ+CWkqoYs5
7RdJZ0x626GbgFP7FFXQBu8nFFTepQJSf9PK09ThZv0WQwRllJivGu4MPqRzE4t8deHmNGWit+sn
jUH62Vr/Rvylf1s5TbrCHHzIz/KOQvkexZiUBdT9aaFubKReUiHRAB3ARFkYtz0jWUKV2coP8Afm
dhCq+Lc29CY4HxfVG3ffeEPKFImmU/HBt3KInqRdCcvC0FjhKCSZc88CSGNRRiWNYnFyM7XJdyU/
7G4XeQuN+KhQb/dv2EMMucGidL+3vTDgRP55qpS3s2bgMK1uyu9/4Ro0NpMZjxYlD9pttERFv+/7
UpYSfzn2UK9XRGWP+1RhAGMrX0yqyZYGA7Vb09+Rm4y+9l+x9lAggclc1FJLEN8EpiR14tnqtMoC
WzNyxp3bqQMszt73PzYtBuMhg9LtUmA4k7AWuGL8o0EE+7acLgeztAFcov8PNZqpAEgFwMvPBQY/
PZMUYPYaQ+DigMhtgtG7hcaef/PJ7uZfwx638mrSq9c6KncHp5eXWYA7p8IhtuewP2gbanRDdwEm
XamLV+M6m0BWOJpZLp9Tzp/DbBF9P+qJcRxlgsf+sJt3aF8PHH0vgpXWeLg6TrKULMR5p//iFXuI
WDskedziJi51G/SJwVZFJxY/QxjJqXiQ96XxSUA4vSWw73G8438FK1L8HixHWajGRL0FyiEFAq6k
A7fhD2dFf7sCFRLsMO3SvwFtEhtdoo14NmnXWeCGHVzYddzfSIt2KlAimYwiQo8dI/f/rjaduyPE
Nf6LP+7fh7oOkbMw2gZFhqn2DMnD+UDtWRNDAKVpEStPUN/A+BWWD9N93mvl4gmGgxyBXpQlt7QX
A/5gXLymP1KVzQ8zr2yMr9PjR72WcWnpQJOOwvv+uaj8jgizn0+7TGWfbJIz3zWWHyK/NCu2hVyU
BNea4FnqbrMhEYhMTItVXUxy+W8PBerJttQsjpgoh5A5ESonSdB9nM8OZC2HPkSYr23dTWbAQLg5
5sMc2mHJNziEv3M/C770nxExDbPocg+IXxhC2D9XqY4KhVrGO2cMcxKMKk59L45ZAfxbW8dz7zOS
OePgdowCinPcLMawgytTi6TrpXVjMlb0euFGJFGgdAvOJ6q1bDJJZ8oGfyv2CQFk5fHdYkIWKqp7
QMFYa2dZUHao170vpXtu3ShSRBRiYJ0E9fgTaY2tRHf3Gt5GkfBq6NPqAbbNCPiBeHJEgmR4D1Ol
//qb8O0O5Q4ASu8vOFz4tWBOy3G/mp0oinwbQ3PxWhPpLMCx0/R7yUEFT94VeIYpA79048OJwASH
49VapLqGZPhPMB4270RHGTITPvuoMt/xu6axK109vtPFPtBXhnGnqLo6g6LE0kHJIgtks31Xsmvb
P9UdHYrE0aT+64gQffMowfiGYkSZxOaa31mxrR/kamUzmBdVf4DtVvnZYof+eyffsAlVadpO/ZAd
MBTCrUKGvnkjrSNFkqKsBixodGkkSQqbloTTWtinwcabEsmVeDZutuOPxiO3zM+++2ndwD8LA9J6
LuENRoixy9KdJA3xJH/ziIm+VYJlGsTF0gFAvFeYz3x4GOf9oxNx7c10sENpc1xfVm5jzVA9i4NX
b2yaAq//Ct7l8G5Z2QPNYZ1KShcZdJOij3l4z6AObzPAnRx9V9HBgyJKiw5a/49sc3CPFgfLS/JT
YHSiovsyK3hzWhHmrHU79xQ6VMqCaYXNe/fcsOAGmK56Q/R9AY9pELu1MJIe4IOpZCmCwOPxGx1j
RtUawU5rjQ8bO10xfEuR10t2iONIRwvx9yXcUHcqztb8EXwXoqjqbNQEtQ5GhmSubamXuIaLJGsC
9u+pg1+eyQDxooAsCptwguNV3eXLlZu/QRg8qYh8rXdb8dvs6hm5Juz9GyljnmpDwyhdEZLuFXql
wFWouBMUREmplsCGtqWfEUa9NsSNoWFxuM2HohNXMiQdD1n8AtJqBzz7ConwVSJx4FWSB/jBg8X1
aJWaeOfl+88p3Q8TOXPG3JRfum7GgbVS3p5BpwQizTDOJJaGYx/X6jQgKebCc7ika1kVL+gmg+cz
iShUix1Ipsr7iPaoA5p+YSDBIZSZjgvW8Sm3O/3wp6wdLDmhrUtCM1bE900SPQNxWIE2GKLyofyH
QiVcNRV+PSAZD4oQ3YTuNFDVzUqORBvthBrI1n4vmsrLrZavVHIfQVq7fgjUtN+d5szUxSxioflf
28FjiV1ETt55nkXvcsjUsAQ7Ih4z/msSYV7672qrdjJff7DoeNHLzDSNWzPsbAlshn7FFirtSIjK
z4iF2KAZGV2BOJBvKDFypA8Ye4gEB3W9L6FuzxDDPvYZXpi21ptVZVUCLCNt/jCVs/wgJjUOSEUD
+erQ78zjDW4L5fdJpvd3YSVq7Kub+Ai0t0BBLIwEHeFoCAS3E47K2dicoYyltQzFv6kAYE/Weoow
SPwkOlX/WP5xlI0f27S1cVlIS2AlqmSQkyHnHnQ/M6INNu0UPkz5baeZFkmz4DcvecvEK37umElp
867MnuqicqHNoDWlb5TFbVS3jrLvgEADO/j9NQDo1cslQ1uPgzAro/NyJ9CXnze9QtkcsHbYPIU+
AXOYDT3wwA2Xfc6F1XKgYWDCFNboxDmE5pagEdLX4AoYeGmg9qqj/QFTkhqv0RZKI8lEx71jBha5
xxJ9wO3ms6mOn13Qmj7kiWE/kna+lhv+lQZkAsbJjmx3YVsNT5JIKC9I0J8UcYiUbk4BZ9dC4iZg
jEauzKeLMTqjfol6rB49jFPATt4PQIKAuNXBEAhO+qz+L/dfZVpdbrffMookkxUmhHaxejBGq4l8
pCqeJsqXfyOHoTi8pTBJEHkHOzMB3dRYVLN5LAV9w28W59ZLb+VzQrNk6+THOKjwwty5CGXTh/V6
296KHqXT7QRogDlBPq5SFAwpX5gEiCgkUFvdl7fKEn/+ic6s59fwXzsvLRljx21DLNymbSiCWT3Q
jx7JBMikwfRMWcthsaFFfpmtXJ1fgewOqwbEnx7+gdHJrrtZ7Z8CMLtT0oWLX5q0s5wP8ycW1KCL
A0LoIzZkJ4GORRLh090RMFFWEyMT8G0Z52b92kaCZwpBKHU/Itcdofbq1dUs0/TvNu/+/JMfyqzi
pHUBI/ocnCLUClXCN8PRIMFHadgQcSoDfttHva45DAU1FY5vvgbrlPgEIkju20Oq2yjeO/irGIve
R6Bs7qvNHWqgR8RXUbYe+Gnw9HaSEZhcHKdgzzVSWPsZNSI18gwOALJHg7Al2KXuAyeJQmRfnu5N
oEg8s/Zd/8xL9c/cepuSVwQ8SF7Ws2OFARSB4GwUAqJGBs2GuTlS5vylpytmWvDasxJ1Tjl6gVo/
3faL9JZ/HWQOXT8GJz4FjMRR+G89FuJC3O6TLhxm5oEn6KefsYnNgCbAtl4vZm4q3SqyKzTfDXXL
X6vx5c8wtE20Db8cuB1cuj1eTPwYAvvv17uwNHsoDdPNSDFSSlxB+IuaROO1LGdQgHRsESqMnJLB
U8WmUzt4b4/zQwhUPMyWaqBHgCXzpdQYFii6AXZQsw3zD1sD8jEeViyqOwbOwV5u1pqO9MW+4hat
xPiejArRD0qYvFyndTud/umPGHQslaB4GkY9HFgQQSMc5uWqZqfjt37cbJ600tEjWXytcHKTIYQX
Km5ExEXrR6bO7yvTsltXoSZOQvNgwjWdq2syfgooIFdEIh/tBnCvlJ1sbhzE++Lgc+8sqGekDwtl
2qd25utjD9oCqegdeg8GluNHId3r4blfOfbgycHSU7OCXNvRHsIt0iNE5rNW8v/AP4eqfYSZuaaH
srxlZVSagsh/YweUxvKtEREFAvNUSwK/T5aqBNYToUbeDPEy52Rcc5vfkpKvuszPH74kUrolLTm8
CB5KaipngfDnfB/32dE3xCumenvtykdYfx4+ZrWcUQM6sHujk2ePZhjGD982Pr4gDATtu8cjqIvP
ephq1vLgq/AtpQQQKKzDwjdvQCuwt65H9LwgJx64m5aZcfrVkpDKqnwibwXs5/rDz7bmpOMK/tzZ
mvRebR3oNZiElwIg9T+OzkPmg+2/0GA13eMpwrwavRa44JhnWZIxhl9Vb8NFi0JyQtwYTRGxRPBU
BIgmrEURn6VHCGdqBgu2+wDpy6NZMAA5uVNJlnVeys+F8G9u2cz0jwnV6Gi3KZkAn/cfIBRKngSf
p8X0prfyG/7yXcie1KkkIn8Zy2YBaruTRuVshXNQjDkISZmMN06NwdzGM9yeRDlkaEnKQbEz9pDw
ISbFr1iZRidLOUQHmBW5HafcNZmg4cOCjBWFVB1St3wKaAWBnY5IFuLdmS0DgnbAMW0o3e8GJabU
6kn5tGbVizktnkQkawfsWtcM/BMtifMWskAcC+VTTG70+H0F1OQtuoyPAwI1DPVOmcRiI553Mev0
lBRfXG6wdZdhhhENf25zjQS/iABgc0GD+1ZKbxrJLkSrtdyOn6x+vqbav/Sye3TJWj2YxNfyTk/Q
3mVXskiP4iQnZzbEHLzxuNFwFeyou+nNcQ+fNSDIexiC87On3v8mOvGYALwbMZKS8WkMJ0z7GLxc
S9MD/Qnf9W45wbobILvnx5YEl/H9tEZeQdaxv4p0/wrICnHMB4+/4Tt2QUF58cAbbLubqp3bAYW2
VUjd34A9nX9nFEDtaMPQBmVMLllLy1+dP9kLGPQrmS3f5mWNWBsaPrMAMmmv5nQY/GB7UFgkvz8c
qm1pNMtBu7JmZKCkf+AyjkeHpcpeR9HP0TyJIQr5WsdJJihnTW7UwDAC4CpT0SJ79kMR0+mTSO4G
IUXpYcrA3lizi+wXpcUcmqLgVsGaZKfsanwxIgRcM4afviEORirYU38emHG3A3NaQMDBkTbjEoTg
Xh+3bNhvD/g2qHpqNdKC0igQnPRvCJWI+ZGQK7BLvLofwAQ8z3p5Tbo81570WRzhC47jReVsssHg
l7Erg96NcVrtcuxnSf8lJhen6zE0kQLF2UFLoTjhUsIAYrmQ4PM4NjZz2kpedLOxgyhfl/m/v18w
klrCE2201d5rSxTz7/kIpCVHxdE3CptwFfDJIgKR2pHRrI2a3T3qs/3vXCGWA8iEiJ6AIvMlVeli
jMtkzQdMQlopnjlm7VowDsi0ZO+b8vaRfpc0NSz2p9UzvDAIBAN8bwmzkQW/Slymndxc9ua35nQP
liJLExt/1vmZ15+o9ZCAjBZl5t4G5EOeEROhiMhaqwMd+FJ0ziXnDE3Q2ia22DyoyttTTyj/iyb9
NedjsXahd7UMOezfVjZkPp+Xt0rR6/5bEWMZtBX7e29mNyaxeriLsjAQUNFP+FhxPWx1o5RuyPNz
VRs7BTh/2Iw+vUrDE8YRWoZy38eA8vkKWA+Z1vKbrW7V+4Vaj7lZGxBs+mTXvqS0RnYFvvoZ6qVl
E8MKxJHwbH3bZ9luSmBxBu/dbI84b1xgWEQLy+ex+u8W+vOKPxxz45Lw7biPGNbYct2SlDXuQoV9
RuR5DaRI69NyH9H3Q0Tjo0NTZqoRBnA9aSS8uheKWvb+dTOIXB9HHg7DGEltPStC2DLcYBWsWipH
x5xk5XunhCAroCmZdjjjD7Np0BZYCTRSsmp/dt1VOPX26PPAtEggGQaIgQ7M+thF5R/bLMEVNpoK
4KEQTxP4/PZauoQmTrrNNQtiF6Jx9N46FjuDzECSNzCQLRhtYWxA6a7yvOerKIaFRZFbt0kR6MHP
g4kdEomdl/vufu2ZcDiobXo2hoJwHes8yN9pww85DFe1Jv36n9ykQfhDK96AhMskaoFv4HK+0lJc
ItBfoGsnJA4yxnIQKQ5V1pqvd+joxCZtj1kx78hbX1AEicOEZimVq9gXwpusVb1oQOGtBO4zt4yP
fD81CoUe7jmfHmegKDBhzM3TQcf44yc1eCWbb3NIbAzq8nNjPKSZ8xoRW6x+3BUPqHUBguYCMbKG
AaCApWPYRf+XTRgO40UoqcjrEEJmoQhZotNdTHT7kschI67NWwUaF3HCG1AEH3s1nxTHAaRfKCVt
ZHBeW0wUxKhpis5veHiPU04aKfeQhBwH1mM46TDal0qbiaKb1/2KMjX+Afqeh2nzSzgWRds0LDz7
4rHFf0h6S8MBcawwm6pq0d1TZSWElYEvHQ8nswrX9P1tkG/8fuJcJzbwBFxzGzSFaSAP5jPPXhIE
qc8hoRqB8hi486BCkz7WQnYhLa9cXCG5NmL2++h2xhDqSpC+NnUfWM544EpiNHwF47MYurLWRdey
3immRmMOWe489pUaIWbTa/w9m4RmTIfa+VIQWd2FLd7dqTsITqNaYS2zHekMnNHxVto7t3S+bGKf
iXorCgY0NYJGgktmuakyMMKqio8kBCgAWySjtnqv2illNYTkmEaQvLKXY7v2ge0xj1sZMW9B9aQp
lIino0tU3QybOF/FVuNwg0oshxNi2ye6fvvJxLxXSEKfEwqHc7Wul9ghFUKv3lDJu35vobpTzcO3
sxVrVqD/UvQUhtgkaCDiDAw+g96AVxwlND7ib0KDAdYJNJ3EL1dBfAN/BLAPu+CJCavOQvew8BpZ
JJmxwEXEgsVqp/weKFzMWiBgdDF/exN9Ktu/EjGTZBJCXpGYhqaZCux/OXqx1ORf5rKwVcDquojX
ZQjQ871sucvZjiNvH5eONq7O3flw81deQJ60eO6qCI0agjJfUWB+GU4527NdGHoWcBrVhGSyF5GX
GeSblhEhVPKjWSFru+s0tIk+cZYqrgpVoshHCEJ0xNfFDQQRDCMKhQLeskfJ13cK8rEclyQOPsx8
Xsmmy4LnVTDj+dgJGdTCWy0vNH+Lnf5PZboPpAwr6mye0rT0XcwgaXFNkbDZoZ9AUnU4GcILZyN3
gHvBeY0UCnGGNKrbZVGF/EoF8Twf6QDIcauydtDAWvmVHEFJlAc7zRcQLCQuSYwGEJ/E6hza61MK
iEyiGLl/prgLNtMVlta+CyY7hoUQJ1gq/OARnKAOxyLpuB+JT7KG0Y1Jx9OvqqyP2gX2uILs6en4
6uS+n5JcbpJkW4u5WAb9VmBeShXIAGAwI5gtqlrmBp5dR/BvDNc6H5rF11izG3OvY3kAsX/pLQzh
3mnzynsKaxySj09FmNUf5luIXbP7kioDPUOoadc61HTqPCIbukNxjMzvZOCv8Lq8JOkB+luXt3KU
JKBRC4EvZXBLQUHIKa5DYH86sH9olpPNTyuvZycQPW5vg6LNMFFvwZTGQLGlBXGpqc5L9Rr8NDF6
aQ9vgjFq3ROV06aYj63Ld5IqPnH9hsZmO7A2GqDjBaFctLkG2J5scEL4OJtf2LGXauNclq2zZ9ax
lM75mLdatcNuoOLUKDvXUYB6KtlFLNKI8nMCnO2me2rWSKtCsCVriDrusB4P71nv63C+3HoQ/WYA
Vn3jioxvKDF6Tg1bFnx/kN6trQwk2G4VUs/pqOpa29pRGb1a29hsxhIYCuxoPdyBZ0mboKdyq0zh
u/Q1daoaPZUMNkImh1y30HXFl81TJeb/2bu/olUrriZQZ/mmuSaxgRQtd0iYTdEAJvK4gxAs9I6d
8LJIsf3ROU6I8jh9jQB/avMiXFdAJ5sHKa14WRYSsSrWHsHM0XRIgSbdc5rml1mMPRzMF+Rm766i
7kVhUuA124OUakfDG3ZDed/BJa0Mf/4TiFGk6g1B+4YeyQfsbOFZdMpK+k7vjhsTlJx88NbaNiB7
I4oh60mY11TpwyxN+UwP1pGf6+LDXpbLjz/2XIfG5Vg/jiwqxY+T7Tgg674BVPxVApyc9wvrgsw0
wkZZot2Nnnx6/VShcDBGIRHn92nnkpRO9HOycexsPsX78KZMa6H2SHg93v3CFXWND0+eyOD/FOIZ
B2FnX7oToX+1uMdsG+eDG6HXuHMW51zgB2RYIqfMAr9x3guzYKJFQUtYi/KoD488Ns5nnRWT0x/k
UIlHltFKAbSXsG7+XSoqqYzcG1q5DEdiu2NWYrtD/zftTAjLAE2ZN4PP+RNZ1JiwKOz7jtEy9NFM
ghxOYqcfnVwUWBFTv/KaAajLTGjzBEj9P6EtbkqzJ3d0DPREYhKbL205+zG4LdOJnq846OIkpUgJ
74KDsdffV5qZ+tJvm2HCo713dScLLAFcJmdLOA233GxAlV7DhxkBkaiOim+exvKdiK2MfPHo9nHo
E9YxQDCgSbpnAL3Yz8x5quwUG7g5kA2pmvMozm7IJYG0auMye1hCsI6l891Xlz2OLu7THL0UDrBA
/TuKz5P4FNnylxB2AKQNy1odlni4Vi6W+xfEd33MBbvR9wywkgQkAnvIJ7OGhINNdWXnMpEBLWOf
gVok7K6bQeYeF8QpyoBOTcDluAl9s7WbChfXKgZEnryicopkYRFrjGM36WxCL/xduM7RgEetdpbe
U9jKo8vhHkcX+j7YO01FhOGJXd6+7hHoDOSa6Uo3hhNgrW8I/bje98OH7l3r3wUOMxKR8tVXGUbT
QnDPzG1NP/kWpwzWkkeGazQW26e/tfUIAuNT2Oatmn+I48P313HmOYw2KtKlq6o0XX+5w1wfRprZ
YRYLynZ83E8myq6mEE1hBcUsErssKHRsKBesShcCl0+ZVK54fadOLlg2oST5PX+nK6b/xn+xw3Pa
UXUJVrrvSEI+Ks7p46xvhAQtCyDwn01+wm89YQWlo4h7/NcUi74Q5n+Z5jL+YR25Qb+WFBccMtUs
fFtPs0+3oj27nPcaBc69pOclXS7mg7FjOUptHOzvCSYZj7rNgpaj95kX4+MTe5sn5Gd1u8SvI2j5
dbmBokaBmuF/XBMa4fHFMNj44ArRvA6vmbegCiEsV9qx2qrYsFGxkc8kTtM/SW8cNntKNbVLq4V0
Ou1ICeZI7nxdfSLrOgijr39ITcmhfI5CsLd7FLGSWCtt/uqy+R581hgfDex5F0sXv0rIkG+CKbMI
fv4UhOkKbZjQtAR3werACBbrVgkTp2xItR6Jo3fZSp9PYzgtjVGwasfE9HWA7Ta2j7YGtJEuQTBE
BK2Mekb5cx5N5RbMr7Af4X1ASCYrIrm5KrkVwSvGKHrujH6MVxt2L4k9Eu/bW8YAZzBVHscwPtiC
hfJjj2Y2UbubN8C1n7nWYKQKqC+oL3h+ZLPBCW04RIHs5OPYCuguRdR6w3stwHgn2XrFCAxuBke9
vrWLBk5ADwppbNl3rnold6jqAzI/vw1pEAYb8b2pQ9/PZXfzZqH2fD71vJ/bZuyFDsGRZiqigTkF
0QN3X4fhYy1JcxZ8otgE0S5d17yD7Ft5LHJBVfCUQHG+mPauvglVqBIiTbOaMM7BGPuOnflT8Vjk
HyTWslyeQTAXcKd20Pa8/pKWZwiwxI3k/gAwLbbw5rb0Lz3it1AgRvNq7I2lIJQ/o3r0NELJ6On9
0FojPmpx3lxDaG+G/7aJru9OPsE5dbdBoru8KCVrlAX/UOperbBgzAlPVyNzCq4Lm0judpzErv4Y
txlOkNTWkONzhPiNBbNsQJeQ6RWLBPd0JKLViJm8mWuhqaHB2bF2tTHejbHSxu5e262srbTIIqlA
HhE85w0VA/dGgJ03/1noJWMaeGq+I1PUIzc7ridxYxmAZPhpGRdZLXeW8GcyG5GmGp00kV4sHipr
lHWJWl+ikDLeCfGIg4/+uM7RubEEMM3Wpn7zSWHjGy48es4oIG1O9zvvrJgGCLdw/g86BelQ4bGR
aZCjQTKzU61VE5+QZwXX3zBO4H8feM7gQddJcJv4snrced0YbdARHLspEU2xxiGqc8J4PC53sgrC
D4CkmqTX45LEHZ4cFViYiHZT006UE59JL/8x6M/V6vy3Tr1wUBvvcWStw5t8WU8jRPyvqwVRJ4FA
8ZfO3yNEhiWeR6Wj9Tkz02OCYvDm0FtUj01tqr9kXfEbMZ+/gRuy2M5QInTcMhmb8kk8gRzNqOWZ
jTj0pCZcvSV2um0KYS4Z6olOmULlKxur9wAdBUGZ0165f90Wug+M9MivMJ6HlZPMZ0cQcRTaKP3g
19reT5srt4uYlVUTNO7Lxdd9jipAbQw01yaSNTMful99iOwVcYauGMcoIAFClkyp0R2QuSigE8Wz
tayqh6XeLGX8kQGPYA6XshEn71DkMW+ERCFhcege0m9RkU4o7zxUHP97V5D9/RrchfDRMdqCgjKH
UGBgxSDmK5MN+BY7VfEiG9ookJm/a7DQUZVlvqC7cJUWFqawNiD70lEDl+yNcPy5KU90qtA58VJY
kfX54a1PaeKLh/74LxXTj+6tAI7i5DR5MmXS2QdlkwnvLsEP6/rEcBIwzpywvUTsX+Mh6OfmUI3Z
qjsSshbLIvNgI7I9HVtcJROjohCzwOblz/r0iHwkYwAwAH3tKtgwHpw9vp44qGMLmiG18JHOLr40
OzEp1PHbavkRrZMGsyvtY8PAae1ORzdk9AkKEFl1AmhLJJwGCgkq7AsEowWct8IdHN4A9M0RVCqO
GrrrBFPjuGirwfEo5GGYdW2ypfH5jHqWEEYEDTYgk25+QMX3qUUJAUzY0S+ss4d9MYBYSNGIPsF2
Rkturhf+KvwovK0nsVPx3yKI0q75d3FhijLWs0YZ+Pw/D5z8yPUCVVi9urcOBeJEHwFaI6NYyj9E
yvkTx5zDVyDjBAfDAiCSHJljwYGNYNv5TgYfspwU1LlCzg/2knYg6Vg7HMm/I3AbzbQgpCEfitLy
WSMd+HjZEex8qOV8yK9wmngS0M1e/ez4PR8efxVOcM8g49th0jzLagtpOY0tCLkBpytJqrOruwGZ
rsHTg0TGhs1BicDE02dET0IK7hy7P9dgPk08wdHAgK8VOfQzoV9l86LCZxE3VzsaBSQaicAaGg7N
p+OxTJLWwM0zSSoWFocthtnGyRwgmRhZz3HwMDjA1tYGJ9CgN3aTL0kTh+cRPvZB7GbgJ0godXnV
DA1IE8abcvQASgxRXVtT/qJB/n8ftcKV9pTKMq57LRkGUTLdT6gIerqllDXt40l+SiHI8H18gKfK
hciqC02WaXm/BAXrf3ZH91WIFfLM89IPAf3gsprTmGHXA7F4ki4yMKdHHqtU2smncRv6/jTIU0r4
3Ge9KhUDMcm2Q5QaEsLXSlBzaUR/HGYOqm05Oq7bJHBBjbLfWp3cYfYHApoIfOqqjzVG4Kmm1vGS
U0dm0vGgu37JuMl6GXfOeSy8y5SyddE2NjL2V8YSu4VqlbxEnGfoPEMONEFbSYIQrcW5GTAueMUV
7Zrve5cz8+OjQEU33ADqJ+esAWQ9xv9zp6ZNvTJKaSVvnwNXtiTK6d3ibcjLPeT/ME9ZMyYvpUPJ
OE84l3LQNoNPYe77s5ae1c0QK4thT/JA/jEPNni6RAgGD1tCRJSnfZOgluEOl6tLcikKezzrJ77D
gzPMTMhw8BPnglARXIuwEEw2JTudoHh31h0uF2pwhsH8jJdmZxkPUVxLESssngt4AuCp036tYXaH
fBRU3s+6If525hoH8PIvGEm/I9tPreiH7aWQx0g+lu1uLgNjBwAxDPrklk6DjXMj3RYEg0Vh2kVG
vrSKZtCN9s1Lgo2brgBlmslHPixn4ZQ+b7ym/rrb3M0hivjhDpdFp+V9XTcum9/tj8xCnz3dyKBb
ggixacU+TxBjKTWMZJJ/ILa1lqmtoQ4Vv2F8AJGW3GfLRruRPxUQmXFmoi+89hFs96jZtwYOuDZP
9NqjkZdl6hGFeSLJGxcQiM+GxyZFgvUNCjyQYOSHAN715GYTdJMSiKZgQnU5IAMF279QdBpjT+XU
gjyuRTnQ8uCe9NOSqLwLf9lydFzBDLMuDlse3Vlw9+avMepT+b/RF5TMugwIDODR/QFnxhOKL2NB
JlLhwMzPjTVOe7ae1zzCnBiIpnVPPsCelX+NmxOPsbVWxH7FuZCxnZfIvWEFdxwWVWj7LZm6pqdh
OtHzMYdULPJ5+wiewdPXR4SIkn9S6sV0WN7wJYFMD2RysOz1RlFYDMzK1pi9N99VeRVEWarBqviQ
VjMyUuInLdd/qyLJ5VAHr0OWDqu71URkwicNyN6n2hgeYJsQIl6ymQZACWW2v3jRLfUrShUzgGUM
sol/ROqk28mGw9BgZQlS6PC17F2vHCEdYHxi+UFlBEIepcbHHGn/wqk37GgC/xpfH8ZFz1rF6zjp
oJQ7xv4riUAIhwcjW3foPqmt8bUG2xrWnu0vlh6lc/lmUkhq8g4X1vYv1zDtUjamt+JNpVzUVJBu
zhwWeGPYHoV1mZM4Ii/JQXYO85xUdhmBNfNy88j/fhURUe5aT0otPcJko20vS+NxqkuU5qYIpi/c
kadiYNdXshUbD3jBWaqpNG8Sz4QXTrZG/1xjUb2OcQOjEsQ4P2OQFIj70TzJmd2OWKbFapp97hiK
AhSL7H7k3GeeNpk2Q5m47npThs032kIHJaySybTwmNV5hIvrF+6KhIPMAx3XKP895ntRyBC6kLby
ZIURyUGhLZ3KwXpkXAShPP+YOU3t8Zny6aMIIMSM7zszvmnNQSof8VPicL17FwW410eLPyuCL7G4
LA92uzojGIGHKLq6Lh+qCNRdsbFYLdMgcOrGo+EeFBNsPDaFvGf6lDCtitzuT5HHyIu8dEPhcRvi
ceEDZ8J50DEc7zIjJMy0ncUNRzsPPlCZQs+oRbMbROo5xkQ7GC0CitnArFnx1gBDwVcvW27NPR2d
X0Ps+klNuHIioeaqjIht4ksBd1VHyvE7npnl5T4ZrfRcx2wc3B3aWPaOZdyEv1Pc6d/mHOmrYUPv
9OehHE04ZrzYtmEwKtj5wAp0F+IWXX38yf2OYfI4QGMDjLz8pzDS3kunCFrIeENykkDjkQdJksMJ
59b7N+JKXT1pjPNXkZcGfdAzTQ2oxgoBC/HGI0AS4jV+5nbarZymOi1eHxIuC1CB2L3gNUY5tMw2
dqpsFSAFMLpe2NJwOcOP8BRNS2cxQJrIFajvkE0wy0QGTw++29DYlpNW8dPo+luui1PUDVzcc2eH
YSoig+lD9IwHTy+7rF64qKwS6ay6xPloWblg4UGMnRMYY+JmG2ni3rTRrGx5QkuPVJXjp8KCe8Mb
R2yNZqFaH0jr8r7vmXXgmu6zYcRs34gJaRL70/KfiHnr3Su1L+pE2xfZyBdefhdnya5JEFPqSTLr
n5FJJUsM70wbUp3fLm6gGtoVY+9w7bJt3nW1Ns/bwrJRR+S/3cIaTWCKk6amWYfokfHqU18TPweP
pZCxVI1Ugm16S99NrT5pntkMT7z1rggRMVS1uH4WstVbAgAAVzZI43JM5rmebzJ4YNysePfQfBDP
lBJ8GNXdn1sFc2oMxj7OqjGh5UwDwSlCdfQZJt9MTcW9AIFPTkrMMC5fjs6UOJeml5ZH3Gc06S64
HN4afG/o7gqvp9EXaxLmUo7QAdxCT1EBYtPVtVXAMTImf855rFhNxLL1nRTYKvblRQLSDJmQzJL8
2Ahmqhvqfte/G+pRf7XaK02QKMOV7GmYZQ/GagBs5SVTVPOmJwXvmLyiTgZ0FLqry7z0T2gukFpC
WN9o0810KKzX48JOlvmLyysRNpusHmU58WfKdnABuICRaCj0rFkJBZ8yoHO3gy4WVcU/UsxhlmPx
AdMKsdQBIEpDZQsto7rYkbDQyAoMWu+siJRN2wqzFMPZU1c1FutV7s/dLM0uXg9fKwdxbRYQdi9R
2jP1vO5/qHKbzWMQwO/JoWd07miJnCICMpoq0eB84O1VSP7eFlQkC5Aok7H6hO13F6BKU9ZmCyru
kzeZhwKOohSChjuEqw/PBwIIbSgJOqPI9DhFdBML6Ij2oKDzSFaEjp1qeHbVeIVUV31TXkGwcqbr
Wwbj8eQnw22M0Pw7i6fdyFiqZi2HWkWK/XmnT1igRD9VwtSWI6Pk7UdBtPLr2eChZpDfRCnoZ3iT
uw3UtVYBclZ1rofBRNDCNOCubPiaBjotRWdTp0fyHP3ciflq7XCvzs3cX5rUcnbn2CIs642i0XMa
+Z8IjF9LGznPQwrga/HzG2qsrHbs3g5E9H7WcAYq02YIvwbGXhApWiuioFSTlshGqb0L81uy50OZ
lBHkhLtuXmiLglkCC4V5w8pmLZshRNuUwbLkAVFxT5t8TL3A+e4TF4+dhLLDDGVTszUXUlvvtX3U
kOYCCJ+bnDGg5PSz4M0+t/uUEy0myL04gDdd/ey7jLSGU3E9XRlLEfTsKXbCt85fhjlTGKy5KqJn
ldmZdYQ96F/TKZRUIG4xL5P4E+tZqucWtzVOG86R87p440skS+URvmRHvoTsXQmGlvcFd8xfzfL9
VrOFFXIeBiH9yikiYcn5CAH3bPr6g+KDX0DdyFmZnGJAoshD2+G0VGHPFnfjN5xxdol445OMHqnI
Nhma3CDas9KGjoCd0c+Nd838hAto3d380W1NTR5HBDqYWts3gDDMibKb/tZ0gPlapWGvYohpIXOO
lTTQsFJLX6uuuwCdc+2MFpEuFwJYPnXjz2XyupqKK1+X18TdTEeSTirwtBx03YqfgWHEme6a3gos
SjRxHdxZQ+dbCH6JWAThNtnbCaBU9lSHp75aDQY2Ky78OE7+EfvO1jA0KpNe0rsgGOBrGHD+UXU9
hCESwIFoN5J09oi6x/cohfQxEtsQa4seRDkWhPp5iQGL2+Z8VDKqOT8gn66Ak12ZS3/1oXdIB58C
IegIwKHKXxEwpZ3R9CmQwaEQMb04ffm/5ilN8epYiY4X5qjCWieidLsJIYiDSMs+wKqkPR0YQBu0
j02nBt2hVZGba0xEyzVpJDtA8eevk9UuyyJM3hkRinH9Yc3jWJNnJl/WO/suRG+Cpdp7MgY7VScc
Wj0Fc/hEK0wZXVexdSVh+GpZ1L00NVXyQBRzsCJgRSpdUUza6SrgVPcMZGgOa7rMyRiERD8tuxcY
ZGyeRcCPsJDdHXMLfR/iW35mwgcyFc4Q0Jq2tFXwSw9h1fHmeHHx3uLEZJvdeYrUdlP9+oN6nbG9
x+PeVBYQrG2VX9xGW4kLYxP/6e6GyoI7rQ1a4RM6z/rjU7GxNl42dS5apnUQjvzVnOwLg8hrXoMB
ST154GxAJa6O5xqrEH+47PKDDuxvS36yijUjcLpWnQzSXhSAP0x4HfEMwDlPRJojoA8ADoGQ10Dk
UO+VJlAPw97KjAGcD4Hhfs3fdKXlHEGmakt6725e3icfsFq7Mppcp6fufLFrhQVgBndpD2DSXUOD
GgBtW2eBw56jZaCQzHK1H/4IRQdTcBe8+yxsuHWBgOAIvC2+f7a/LXIs3wf2daaVvEeBg/Ni460D
pyC19L68dig/HcyLZDGSMlB0EGr46CE0B3k+2iAJ++aoh5xMNMhQN5GFXSsKHCbgM7Gsdr6JnzI/
xjld8A8cAAzS7M8NpgGO95kV7pHPMqaAJgU2qAMaVwg8LycHIO6C1Yvz6oPeBJnJFcY+UWDuJ4Yv
YQgyhnyVDeBfTfj9dr8xu3xe3j1EGjiZ2w0qMuwdMJ6xN/W2Uv/dEavEhjYhFy2erPdf1sVipxiY
LIxOE9yXsl/pOJia+C3TGp9ZNYsEwIxB0qajCKBQj7kG9Lb5Y9lviGywvQ1cLtOSdGI8N0zY9OW3
E980hoaM+RIJhlvwhnNfEW7/Jm/fuX9xLTDtYb0DUAe/1F6eJB2YPqw6PfmemxFfNp6sz8IH2EXI
dZSYSOXgw/ZtMXye7yvIwugh6wY7AQ8Bw/w96LBLVMsDpsKvDkZ1fi4JySYLkWWAextXmX+Ay4tV
Fp+PYdMNfEVPq4vGaR+INRl4hP20DB6m6xXWl0Fq9BSx8Kx/J0HtO9UOHbw4rilHCJDbDAZK9aKC
S2GE81YsnxtK9w0Vr8Kcod3vi09/Sz/oXBTZm43dYnRTGOckNA1qDiAJBFBkWTpmjGBAQJ65FX18
9Lad46xKF0zCA/FGcU0bF5gUkChpZldFNNARx4VLko56nz52O8X2ePX+I0HB1H3GV7gFddbr6nrL
8oEMF5YzYupOXylngjoLhlmYJrwl5E91lt8a5fWQsP8jqT++wc+fSKXIzPXDFZewDm5chvpw4Uca
C8baxh/1xkjCVU+2ARXY2nOgTLE6Mm4bQ5l5ig3DDbLe12SVeqluJsI71A19RxkUR7PWLUr6sUzR
OccxKw6YmLwHnnzMDW7fENU8VvYxGiwRnfkblsVbK9RgnztfsYPrpuLXcjyas/yDD50ZxPfDTcNa
MEDyZYLlI1ohrGLW11NLFAPmOMb+Fi3R8hhP+XIxgw3gdJL6RS2JprPC9WJxGBH+tHd5eARjBEEW
KMrhp0zsBb9J3032u3tq5+PsdmuJdQVw6uDEajTllHRXvqRwsLJ9GaBKD0ZInvrU/cqmlh5dvxww
awQ3WUYxzzVbyVhE8RnVSBMoqzgCkYQNNPeYUrNBPKwCA82JuzHCZ5QEMO41nDcHTWdM7BIvVeBO
7CJtxh1EqzWKrwvYi+IlGpGAjjbjiG/GYan8u8HMRByW0ieT8XWhIVzcA/sfsXWS9nP+ed0GDzrl
Yut0v4WC+FhBYtkwHjGaTOnG5aMKlquZvJOL7C7Q50cqujUpkYLuslnUZeqQPCL+QAz6H9nOmshJ
yP4yZ1NxHgvRRqNPpJVinlp6e6madn/wlEQjG7FtfMYhd3QDJ/bGHhNAIyBbiAyYRvXa8RmJuWuQ
VuNz2FgCRcCAMX3avLMkpvtZHHWYSyrHUejNcQx2CMGEygBaLWXDtd4zoWLesZr+wzcJZ1CGuiX0
bKdJyAWj4GnifFS3cIJaeV0mFoqjEiOvrCvofu0hj+JkXMgRfUzP5IP4nTDVbGag+bgnQdBQOA24
ZVHxcjB4tMq3QaNmeeblVsowamsMQlxMNs4NQVsMt84NGMQ7jZwHgMKGQBouz9ftnRS2fjB9pfzA
nYeyy7eKlG8eAFHCplyth8z3F0a+Wmev5SuZfOstHWAFbnYu7i98sGwrYDV3lycHBjEyevalbj5j
Tvt0Y2II7OrgDinjK0dWdGGbyJ+1PE8B7rf0bNueXqhlASYnqa5C96ooxUdOaZx1RRt/FWiz6QMh
wQekU0vpuKgzu4jrgiHeyDjHj7XOBsTyMuJBs3ulXKhvKwhB/k1OqeX5xdvNg5oDnWsknQ/jmt3S
nDnRSZO3/yMUaRK12z/BIN1WHllAlP+E/am+uknXVU2l+YmQ1P3IIW7b5ey81ZgNpZ0Ylsy9F4C9
NQL8gtqoOYlMypvGXCBERnabzUTTatzL29Bd4iLeXFPnhM3pPj09zl5yTzpO02xaxIqWPnIbsjWh
eyz1xv2piALTICVW/uBLpCybYh9K12Cs1ZZrG29HUawfjWCJLG8p+0fqvJhSDAfOFIIClRwZ20qo
KHzzN5lpe4nio4wPp+idzEs/PwY7bSPj3RUL3YFtGm6SdAn+ZgiAUz35HbZE8y+O32vGyCE5dbIq
NssKxuNZ/MUdYiOISRMXYt5Bzdl/+PC5XAx++Z1zIXd9fwiPnEjiLX8FXC4XstUcdWiPj3zSRXp8
mgbzh22tut0DDbOdfaWL77o9ujQIlb+XSENVPqcWrsqSgi9m4e91y2Tj67UEYRP2lf9R+D9qsjyc
eEo40LQYdU/XIEOVcAa+9y5izomMbzMp6ioJulv/CiT31Lo/jCxrpX3yEuarCcGlcFYuQVFB+K/j
YZtq2prdKfRntQONA4QEea7KWGm5GZfs/qgBMiMbFgWAuGHMYWZwYdybsI7Il8QXmsw3LJtjcuaP
EIJYAx6aur7zWXuigOAxaIl6PjLMeolEZ7TZI5hc1aPLZT2bAUq90S9xe/azX8hL+jMuZLngmzal
TdFNkWavOUY4k+wXmPcYNij5VMvQTPkzXk2oLm7hr+0IHnhIipskOKZqyfrLt8XfX4wenPrNfDX1
n9r2rMvg72iXZqcrsdmPQlj1yAys5GET4xpFpq/Q8P7Epa26SFiHsAJuZtqesnDaZF3gvKbLQVPl
OMMbefC3xcQK1O3uQPABJOwIy7CTTS9jdjYxZxP7hGSmbb/Mo2Z097jyvqijO3bZOLtibAWZtfeJ
2I4kaPFQbHG3yhg5Q1nFB+rsAqXrFSg7tOYwR8UzJKbrGeouZ2nv/p2/e0bkLFyKaPgCl3/3osG8
LlORIfY7RVRC3Lf2MyNZ2SH1ehJSajvkZD5jPiepiFuk9kQlNwtpCfVPnTbYaO4wkP2qJ83vyiw0
efMIz/uIqzAt6Si22C7lIiygKA3+3godIFqN4bYUvdlyW6JLyfECetMFgpCz7z9fLZUAHJkgdA3Z
C2MM6P3DT0/FTiS6s2W/I8DAQhUTM/jQUkhmai5g45im1COynaXsWF/lq7CxRnRKVTuequUt/BYE
M7n2E4v2O7hK1YquAlpq83Fbo1ClTPwMRJSkQdoznd9W19M19/QUMJ1eM8mQe1CfLdtSgW0qpaz+
aSW9B22bTLM1pn8A+yjtYqMkmFc2k7CAyo/D6XKB8eNAlScqMn9kis8ycZv8iNYP4tKcUTUvrdnZ
slqrUPL5m++lZpN3v68k1gzog4exNVoT4KUTgk4/kZNzdYan2yaGrEXESxhA1lBuYFvZhd+cjUKD
pZkfRprzuB5inyc3dwrzEPDo+36bLDswLT9XMbmuxgAEC8SWecdEeWaBOvtOjGl2J5j1wfCwpet9
F2aaUqgvqSlz0yTqUHla8/wcFXSntgWmOO/VALtZ92NcG8wdDqne9NH2La/9cEoQGW7DxCUHxM0o
fYcT5ptyRjyV9ApLIS8Jo07VsHR2b/CeH+hGHkxtPtGfpR4gD+pvPh9JdRCvKzQ+pTY66PYFbswV
AkDAB57ZItFJGPjnow49oQI6tYueT0a4jQIzXQaDI8rC+1C4ChAY7H4Wd3qzK3VNe54uwu9IwfMB
PLJgMi3M3qREHJVutcvTLthCM968+nnZTbUFF9tTi+xUuou+Yynyvxmtoy/84ejlEJT/3q/JVtXf
JtQ3SVvL1cAsmGQe0XhOki21EkUE9xFelSYgHWgh3QVzsiAaLsPkO4hCsmDfF9BN7qlWlpg18epr
XGuaVaOWfAsCG78Or54BokjzbPN4sSnWDWO0FMmL9sK4PD+Uk8Ino/oDIVLkEHa3hi7xGiXayBG2
2PD45G5J3QEo6kQuxFmVYA4yL0HyahcQB2XRXRsuZkz3JoDxM35p3LF2zlqDCsn1aDrMvq5X1Ak9
k7LCqH09jYdxfzCW7aLPqR7EXnEBJ1vTxFd43pjdx6ze7ZBnXdnI8Y362QZCodrX5S+7ye7Pl4io
Bp3Z1WIITUmx5nf37+KxZwssbD42nPxCNsGXc7eukD0l9jjEtkPeL09QXpdnpwX2VZRPc+uVNMyi
ziFGHe9Nhpz+4EJ5kbOofm8OFsEUwHWIkV9+UHMu66LIzil1BsW2cSA4F7XnOB6C4kKWP6BDJhbk
zcjCM6kpOuC2+MbydOSLq9uOm0JkTo3rgYatifzrV58qqt6zhIZFdF327/SYlOkhKvZvtZ21o4aL
VIrUtWxabMReLIUP41uBHnHGsbbIpnlVIPzOQOOwa0lE6DfKf7DHeSIwoMkCHv/2fEB3TkgLfBKs
n3Rsnuijlk/XlPQpVqnWzkp+BiwRZZcmUC4nPx4bhgs2duLKALBMRrQWm9ObnzgQ8btNnNlQot9O
b5yhs5Dhl6YuoW1X82jiU5eG9VkVDNQLpje59j9EYsyz46OrfklSAt4qDEGoGg1WN9leQzyk1L9p
5DAhE1kX8AyGAjhJn30FhF2aCmYGsgmRU8wopGoCb8056UV/0dG0RSnoaxAH55VmNnJhrEa8BhuY
YwEyOO2J0V7NdNAmn21YAQ2JBSOy1Gxhd5sifzs5RPZ6EXJuXwNwXM7gTv+4WjEZYuZlRbO1oYOM
VACHnyJlVJMduDNcio93I7C2AbMu9yaKC7Fbl6G+qOL/vJWOcl71odX+3p/yV8MNbYKhjPkUeCz2
v/pad7juYbhI44fmdK3d6ZUTEpDVzRmaJhH+Znm3H4dg1KscOtFvsx4lUJTN8bgEJsy3Soigoxb9
xTdolvo/VlePmXuCtV34K+ZOaeGMEKPF8TiI5ymrtxT02c1IFgVvaXVVg8W7otuO8MkFYdoLQ+//
bl6viWNRWxV1b56HOZgTA+UESaUQWEiM8928zPoz3uqXFo605Jo3xA2G1VUojA5yo7m5sDQJJ6A0
aHycDU3CeAvbRX5tSWC3cv+t3uEOKka8lIPe0YE6Wa/cXJO1hfujmtefxVtRIWH6w+9x9AOPTG9N
JF86K1wetASOeF3qjSIyYYYJWp0FPGlt8/b24apv9Zl8d+9HnamUt1ZFycsgKiJpxDhByF/7otG8
Txd1e7xSkyMzrkN0d1JVKK4MedsTdzVj/4/BPT0DmSu6A3UzNI0Pro4D7MpcADCbeZcuM/eNsXK4
HncYI5IHocgjwPJMRDXKte+m5YELS4GDRa4bKzT208oK3FoT5i9Hm3Fy0wX42K2h+WqM5x9Ru1C9
WFRJ+h0nRloqAjTrtnb5/5llzP1L2dvs2z5AeqPgrdeM7kpO7eZVyOVszWMHHFYAQyDFzjG6KACL
o7jrxicLliCJz6FEmqpkaxM6gZ27zeOWhDTS217KysKBTFuzzSDWnV6gyiGi0VVE8ZaEKqiQvZVk
N2DJ7HHYmEotkQQ0jHtwRinRjYGxrd0lqRlX/Yy3hcqqTfLZXf66wSsra+sgktGGijHh4sQpGBNQ
wFw/hoeQe/yjQpQhFdTq67XIJS5Ye3wFEpNLJwqlxL3AeZUJDnhf+zZD4w8acsF1CFlN9DJSUzLn
keFWroGDDf7mSae6IQeEoxHMPkAYxz5KgNZHaOodO03FtHdhTgDoswLTYjhNw94ALi73Ze4i8prP
bdk1oWdDPy33FIWcKw+f6cK+RQTRGPsErRwYg1YxqMtIerS9SEuo16rtwbThaIa/WV1U4LVSJN2X
LJul7S2Z3Lgg7EhgB+u6FxQWvAIqsZciyAfhy3YNafOxfayw14PaTtlHVRt3CqiGgLRCXPdYx7ZV
K9sBae1dVeOYxh/hwI4tw8FqHoJvQvM03kd6nO5GatM6jFWZDcLw0BGc6Dg7LZ2Yz6RgOhsagwMh
EQKTSr+l09UEK+fhcIHPCcLTUjvD126rLcvQt9tVYZFZ3Xvsl/2JtY4va+e4UG9Q5PRrDI5K3ddI
oum0K4inaN8qoKbcMI6BLziZNey/3T095HSOxYwpojDLXed0FRKSkv8vEHNLEAdYwTofZujXsKsn
ivu9GoGkU9DD8t0Nm25AtSxoN/HRDzaDfeznDu/0judGesqqIgy+y79HR66Of87v68knApa9be+0
QC3EgjQzzS2cUK2o6LVt4noqdQfD/6mjfE7lRTOz1arUXiJWuowBs8VeR+KA04GFHO+WQUC/w34k
VKS17yFgF9dWKWj8UfBPi/ajlcnPdMCnAwXwGKhHiYL1W12gml+yWJ/UpYidDvOpK5hidxHdx4B2
u9Fs0siaenOHtCajMv150mg++yVsKmH0rWl1nb/TD4FTBLkx1b64pGkAntep3IbHOBOPCED1I+W+
n8EhDV2cbNbStGZ/C43+PdXm61pOZRO2EPOa2Vhfvw8y1Dz1hTJqXgZLX4VBwkjsI+EwDpIdx0ay
QhU7dx4UHC2keRWFebyTx55YFxyO+vyGS2cjquCEg7lpdKxtTuATxi081oxuLGEebrDWF89iz7zx
jOGebNrsiSBl4EFvCurFSeDi3sH6XhppsQU5T2P/VrVSItYgJCfws9O1OVPU0fQ17UnpAUG0m6R/
IYE2NR8pnELQGGwwW0UNZzO3lQ78D+vNF1FGeQOkuVcvYyYZCsRRo3/04WlzD7hroYLOYGV1ij6N
OZG3GKPLs/TI80H7CTvh7OYrZu7EowuM6uuM2Z22k7ehCunaxe6udMw5f6ZEL9DNnkPmfc++SX9F
5NPiFwHe2in/DO6+EinzBJSH79+JsNOpAyxSGBYXKd343/Ir+LvmCtVMmAUzeL3orNrrjz+yzQ6d
KjPBl2Jcl/4hszdVSlFjfh4x+VIZ5yHPI08jq2EloqyqvezOt4MMXxyhxQDUa/rqpzf9qMaUMJXJ
sOAn3wqToC7AWbdKjo0cH3Zw9X6b6fzhr4Ebh+xQ9iINMySiwLQIWvZBcQ9CRZSZ8IuWl0dxq0f6
EpZto63Zo942doN0ntVcGQ4H48KfYr8hWUi68Qm+mk48hai+EP05FBiMiwv2aub2EsvAm41SOFvf
aU1WK5MrIsJ3Ft3bq1jhdZm4vbzpJ8OOo6B4EG+4A/W0pdHperko7prD/7B/XghUJQ2p+8yfMlKw
PlVpOlh8ZwIROnl0LI416SzPOJQ5tOFrGnRnkMqGFQqnVjzJKEaz/qeX3IY5swDXtFh1FgPaRAwf
7en0tWIulqe0m+AzxqEmSpQH1U6oPc4xuf9WO0xO4X50roxks3BEMthnO4fLhjOTYhh9eTr0EXdl
kAjELZKylXLsTjsU7Nz63xQ9b2OmdgyOwna+vBSlOMCxu2VDRYlWHHMUEbGCmCSq2SOkYKy5uSQE
iekJ2gWKLTmUJ6A6Ywzfipz4d47gNlJrGa2eDWp2TilMiurBwNzL6PcML8KHeriF6v2bVKJj2q9W
T4V1lBtql/RSAGuKW61T715/6vY4jZDP599B101X5pkKSet1C7TPEg5QQEWe+ejTvnKDIm44buOt
PmSISLuqNdsuMbAcbEGcC7+3eNGCGyhxqgzbNeQxZm0x/B0RuDvwPpGonMcAByjBuRfuP+zd5oS0
3rQ16nnbfqPspTizJVNpBD6IaV6GLo6KollB0qkhjZA4bKzLgbxDiT7UZ/UYoQnVMv8MHjlBnIYq
VChmy42PqV4HKdYzhtXzvELAebIlSX+Usqgnclpk9E7KgZng4BVJuETd0OIZ8XNZHLsw/6Qdo9ot
2EoJGjpbNVOR9woIYtVu4+TcdYL9d287aZHwCp0Cg2yUr4oDkTVA7GzojFWL8PNyvjgy3RpjV7mO
F/j+6cnG9NgV6IlEhxIBHJ99JYbP1ju8fhog/cD/2ND/0JvcF1dKKPkoyXBBIIXXR2g2ybX/YYQX
A1LxcBCp7KFbvtOPFOY3jDUcMn1E8cEYJXw6dOgy62bnBNRid34FS2J5Sf82XNztWaQlkdlOitdx
UbijoGpZ5WjP88qvLpiSx+lOq3U8go+5L8NkhwywCCEvUHCvG7Qj9fYMFhOLx2MwM8ICnIdWK29t
qGXMxQzrXRepQyfdJausxSHQfJShx0stAf1BiQJlVPbUNqQxVpk8rw9jTTXpzvFt792i2O1Phvqe
m+qCEMKl8OKdLA7zS8cUTcuj4BhBICrBeARqLy4vW2lgKte95utVSvgESn3Wj8Ou+UZZ9PYHi5rH
WuLrquztfv3BzwE6HMg/H5B1ry2iSKKbQD9coxWVZZbL6lBgG/Zh3U4mL1R/AIhlI3Q3StoOSkkR
CbZxLhHblejzpWHmk3iCjbsXKQMGiWG95CNj8tSdR8I99R1zjEq/FTeOQJ5jGl1fL0UflL14tnG3
SDNCEczxu+S7ziNa2DaUsRe0iDRYLkC7niQ8vZVsorPorB6yH6z+BRwT8Wn+6hEf6PMZZFtP/VZC
lng9jcH1RXpVwfZj7roSOy2CRq4ZvtxfonsmnGz48kc2wQx6HsV943uVQCat8HNYYu9bFjv3CaJw
MO+6FjDVJ+Qv0I1YQj0dG6LWLKAj0jMxojxCjwKBvxO+Msy3fHOer2RZ+DNg/LxApWIGm1xnAQy5
H+k2zXMZHI/Al0oawhrsnn5z4N7pWgABcNMqCJeIvJEX6KqrgtQVMRWBSuGTZjwAXg2JoSfuDr1K
mhc8bLZEEL0fGkm0ItV6Pe9FvSaSM/gQCBGDXPliwtbtlhxUmi2BGVTOegAiCVL6XzGVOomnrj9l
4oOFLDKAV1tS4ASM2Ql0MkreVGKxWobuq78RhtjHKyRxDXWNFSVQvneAvQkwLVwT0e42HLN4JjOr
sGyVJwONFrzUF2/hULDdd1S85qbDFD89Z8H+57KL/51t0AYwtIjbTbY4iPYnDTPvZiiiIK6929GT
Fkk3mDI8dIUgF4HIv83fTNl8nHUsCoI4/KtVJVyGvEyjVMNe5KlQgg6bBN+nw5sGYcXm0L55qJie
iinbNqwC1uJtELqRYg83Qz2YN39orPw2hrKCQmlg5oEhxCQhx3W02dFVrUMzhYW0bRGGGpGq1BOW
CRRudEf+UxS15ZJ2bwdz1TjHwSybcNMcKY3siebgiRflrV57aNFfDH/rC3KNgl4kG+8oXlAuu8Gh
HwK5F2n/iT4CC1a/Db3t/kKOd9xIqg8rWHMCM3DW7EUcC8WncmuTftndvs0WjRG/yz5Q8mgB0AUT
pKqN57srm9SA21GrtxrvIjCIEPpWQfQq0lWkm0z3wnrrXH+OuAHysLRT2AfqeIAHz8zCUu8n1ukg
qBYX0+hskc8bENz1CzZs/aeCxwE6kfh4pLRq4fK5NNsx6rIoZ0Djmzm+w36A7BQSNldjKJV3Czmi
IBeVVYOR7Uh3GbvY7NZmslqvTUhr/twEIKI3W2KizHIGguzRMCVDzAgrw2Z0glXJvYjhnvk92hG6
wrMu16qCrcCmTklc052guJFI+ZMvBRuAuQII8M+b69+stKqbPh+bViyx/E+nabxzpyLFrU7ptnNE
9qRbioPP1R4hyLayTF8iWXjKZ+tidqMj9CH4pE8f75BE1YViXeQcRULhLRkU8t3y8gdhQXmk4sLA
+3D3ERi4CiT4Kp/mqs3PtMqnwfszZASspAqhDvh6vnUow0mGzpTgC25xyJNeFwZCBcqywuhbyus6
nLq7X03nEIKfUnWhOi7wtVEK3MNopgVosel9qhr6ugnw+LgL5prcYTaWqtwywoLA7pt5Lr7UBLI2
q5IhcNeLMNkX9r3f647QjFGvO7L7kZJLOoVVpqVApf6gx9uZOYDoYyFynadX2SFJbX9hKRfgf9hx
dOXftfHKq1g2RuhqRZwFc0VCUegeqVtgDJilBHve0X4TxeVz57LewLXbyglmFg/EQTW+LPY5baVp
GeTnFNlNtZiq7fx5rjBCfMCtXP8X2Oc72K9m/san0Vl2eyd5ABBEDwDStb06cflFAWexGD2utSZt
kjqyZKiVXpmKO4Q5m63pH9DCi3qvTzS22WLtXH38v/3E7E46vM/tLPa2meJ9IK8xPBBztGXXhkfk
SVQeo+j+uQ0Z0zKo4IweT5/mxEQySQBjzKDwc5OYkCNT0JLODJMlQY9JIc1BgcI7R1flVU9rVd9h
EJSSFv/A2DKanorkpIiF8JuaF2QLZBjS5Fpe/MLzV+jTGBkdGcQKQejZHhSMxQe5wLgWh+sEW4tn
p4x6yzdbUIjdqvi00PlCWuUuhr7FOeAENiYF/ATOWXtRsDypaWqh+TMa03pOI64ZjyNK6ncXTWdr
cg08dXsFquPC7oFm8bR3Ja9cy75PZErQagIcSDOtFw6s0Q1yUNQNOfe/AtafqYamsXbgLNvDc0FX
bm8mUfZS+ynIzCySlrn8LUtz48NSrQPmjopQE+geP/QVNCjjQ5hlr5GvHZXmgrilcZMZtYZT0zrd
F+2AMGJDD77puwDkKotq+z7MZ8UGYDXOaotPvZrwMwnoNMkwbn2tnNKrl652xnQAkO0+6V2DCv6O
lZT9MfnOLD/MVTS4rSp57rKxjrcnZAnPPpxlHN+d5Ook5t0FnJtldO4W0EAATFzRX4yfo8aRvmgG
j6uFb6jbKGZxL+Prln1kr3bm5hkUtOZNyrpJIKgxXZOkQUBgbsXMDXsfc4mxEEe1/CSqLIh5FZyM
WWm33jk8Mpup4E+7vs8jNeFAWGRZ0NFUy2aTyGPM65SeRw09SGIuBLaTh+IR6+OZ1w7OdaojBPra
tCubf8kbIgs1etegw6ij6m+moSvSlWxf/FwP7uV8VifjSDXXQnFhYO+aka44BNLrfjuZKUCdrkv3
OI4t/PQEz419zSdyTD02jxS5VO19w3cNZtoq7U3oNQraj2tnvy0Tt20XHOJHvuoHNy0I63iNBWs+
bBgDK39NGW0tCm8vo1LEfbUXX8UI+cm2ZjMEz/Du8ahkBmaitl4Nk5G+NqMiZbPPW1uptBcvIRjF
gVRH8azGQbBgDPESWfdkt39S/ZcfUWAw85OcoMff8fHNmST2e43d0h6/vwcU3xzI0Xlr72dAPxpu
RufRRFU+AV0i3EgR1ixhNIQjfCX5xHvmYrZpYrACDA8+I9sO4bZE15Sjwtd41txGDyRUJrpHDqp2
S2kkqAHDa8NiASMbFJHM2N8W2sEGXu/LYkWSaSZj5W05ROFAiNpE8HgmvhIPfNwgDB/L50fsX/Vt
iJBLOJLRk/ALyyVlWJVddd2ZUD++9jZZyspiwcFWWJQR8Hdiguv1RFnD8ffd0J9osGhfu5YxGYN+
sNXrf/kt8kxm2sI4LDj79p7H8MUy0i5Pxl+1HbwxDiPR9XNbQAzZuHcua3zBpqGWYWypEpZZ5PL5
QMTgbEPCSVimN28FW5VKYyuHrav9eho3+yzWxKwxkMi+STpsZ+p/kAVdW6+lBfaDyWPe0Wmjgou3
fzERD/Toh+F63rW/IKloCBROPqKdjRPKu4p3QuredYq+9sitJjTQx63IWH3IbapZTN9O1ui851Tl
+LPKc/ssTc8yf+lAMBgA2L+adGtgd4eAFFX5yOh8P3Vs6VJDyj03K1UnoHKaSn6l/6ZHz8/R4Gkb
C/aIzSstKWSCgqsFzqEcB8eRS9N5Q4zaIPmBvzk81IoaiISTtk6XwUapg6gFFo6bZXnnQ5YcIVIP
oJrMYrPnHbWe5qjcr2a/9PU8BFHFeLa0GrmB67/pwVv6EHyImqtO2FAVebiYNkoaVAnn0uElPoEC
Rbtxl+VuCpO/y6pgE/KUxnvvq/UoUt6DLCtT4+NWJZ/m8YViaOO0/Y+A+bS7ummux4xPZblucgn2
tpIpFWq5i1bpVGWHd4W35mPWZ8bK8pqCqmCR0FeZGzb+vtnQYACUmyCO36boadKpWCpIt8yrHr0Y
Ri8wTTVpOiGTJiT8jmQ6RFXaP3ZER07pD8lG438Yw7fG19OI3lIFOr8zR3NIOWqopLAg0LmBydqJ
nGq/2xJJnDUoiXss7CTOdACBdEf/q64O+LeWB2SWtSqCJImvbfrr7eUVcmISMUv0Xk6Xmo7YQlX1
kb8+eCsl8teSfBQHkadCwfaU/U98Rb0dBPw6gclGE0dcrvPA1l/7B6V7w8S+CW0xeK9mP3NtLkUN
+LL4WV6/WVzxiG7fM/FNLbQ3bf40II66vezk2CDegSSzq7l0j4IW4sOmpa1fb/ZJ2R4NM2nCx8Lq
nTms9tPS4cfZe+PxuuMHwA2q+x6ncTqHeraUwFPwXf2IEkG8Bc3oc7eAwGUrR5bjBomzxNU0XrtM
Gaf9HVb1EEZmNQCjMThtrPgtQIsHZBMkjVC/GAEhzpoctnm46SsXGgg21Vx5OHYpncEosoWdJZ7i
3kcDu3M6nUqtl8OnhmRi1uswuR3oysDR5Bg1cAKHgLcYuyHP0T0XRMWPrXngrCOIywxdX8dPDEiX
psCK3orD8sdgKJ9gm3f4U4v1U58xd57VvPu5mwV8bIM/DiVQNECtjzVXwpZ3qZMEzu5koZT1CHKx
4UgfBmvGelbtaOYp9ZZlKz2BtRddwoG2CPP7yqofw5Lc5AuUSgQYXy48K9eT+OiY5Oc0HCmOh+TX
hcE4h9r6D1QXhtto9VgXcRE0idUlarloJwIu5RgTdIGdb6jbp3Hhix70Vmxg+YXIkLd95XWqF05N
vczV1xGLReaSVsBH2XLbusPjcUIbFtPxgLEhntxX5betBR57sJSrd83aViBMku0U3DfWYonp1sBu
ct01TKkFG8KAe3ZdyRjVuw0C3bGJByIxXi1MyMieojARKtaW+dcI59p2dZG24jKc69jePmuXbolD
0ehjyAMVryQHaBF8GMit5RGovFSE/NDTJCnC6e3H2JvmJCNTWYI5kIJ+dkIpto/Lse9PJ+LxNial
hkDNncy0legd4qsGVkB+OLUjc6QzYTi9niHP+z/LhanSIDRMxuR5mTAi5woT28mhzmJQ9oyZySRd
SqjIS8e/Fq1CqEYXL9K4Czny+JQJdJl8kltY6HdxDzPL7mTpANwqOa34bQxXOYWqF2GbePLHSV6B
G7Y=
`protect end_protected
| gpl-2.0 | 6e0ad1923eb83e882a1b29ff77344093 | 0.954419 | 1.815645 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab2/Shadow_Reg_No_VGA/Shadow_EX_NoVGA/ipcore_dir/EXTERNAL_MEMORY/simulation/EXTERNAL_MEMORY_tb.vhd | 2 | 4,364 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: EXTERNAL_MEMORY_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY EXTERNAL_MEMORY_tb IS
END ENTITY;
ARCHITECTURE EXTERNAL_MEMORY_tb_ARCH OF EXTERNAL_MEMORY_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
EXTERNAL_MEMORY_synth_inst:ENTITY work.EXTERNAL_MEMORY_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| gpl-3.0 | 5e23896ccb2e6ecc5a9cea2e70b7b546 | 0.622823 | 4.692473 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/floating_point_v7_0/hdl/flt_sqrt/flt_sqrt_exp.vhd | 2 | 21,801 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
oPdBddhbhlsu9qkjSpo59ntmnhmYX1HVAqhYT8Mlh0NJxZ6mrxazKls2UdPEfdQAAL2ZEqi4jRGf
nc/1BUe1HQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
fDfqQqjdwp2w3i0XJE5P79OYvXAkWDy1W1Xzv848AZxe6lvV/DywwpK8LSVbTjHWfI3plSeI1Xqs
lZQVFgd9gIFOJwFfEOcJpy8dL9JfmY0CHYIg96R2Ro//MohshWz3uAdLoEm5bFyM14n4E+G6qv9b
C2xTVQ8M3mHryFBQ0oQ=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
dTL8bHjxWVcMzlJIxs4BB01f/kCUirCj2PUDBeUlSWl+tgi1L6qboNDGLGdrFnJQECducwM41F/o
ZPgqzASGdPPOQtrIwWnlN8Otiw8HWnNgRH2Dp06PJVcIe8Z7HApE3aTD2p3nBUyH/ZBQTQskowQJ
gpTkb8l+yS6TG6sPNEbyrkSse6uuiUo1inSsgALzXOt9S8mqKmeC3HsFcQRwTPX8J3iBKWBmHjBP
jtaqUOcZXUYU+lg+yZNxqMAqCRVq7w7yhcOLYiv14ltAZoLCj+eeTGTRJVQ+EVpJlsAKF9L1S895
J41MNFOyYY3jb6GiIlkyd1/l2B46ImJRVoJpdA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
fLIZJnELwUyQjHxn1vXMQ/A3u7XEAQYagl0Ht3J8aD0BPMB0KHg5JsP4KAxenxalnHGLsh63UQKF
JvAdlflRHyeJF11jki9weGljZhvLvKaFD5m9Pmzg3/Pux18iMwiCa3pTo/RdeIkSGzhpbhr8Lzkc
m/3UlfHsimgpcNQg7TY=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
s8I/S9jQewsf29DPh70+wirkBVzR9Gw2yyHhCkiElaojDvP8o6rckDKELXDqYrt/cBmJHUSjkimG
JiIbfaiOI7LWM2jnMtS/vC298NCYJ9f/nGLgM93gbsKds6HuES/ks/Db30ktR2oW/mFelgnU+HUy
xy02RGqgJPM/rpQ1i2nj1/+dlpqDaCHjvzxEuA6nPSYUWME0/+JwGqC4px2SbeLwhdhkTYbt0cmN
CekV+0qH5poHdvpYRyBMWJ0IKsOP80RBIKgsGM2o5oPOpp/oewPe1MaCC1I6moaJwUaud1ClzQHp
P6tVYXtz8nUrChHssw8yRGgUkXPWWsqTlQOWvg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 14400)
`protect data_block
wtnAgesA6Fwd9+b1tAtEPcrry396AQ+ej/wsAPSYj7sK0+Aybhh7eyeF2ZYMyNc99jdMPpLvMiUb
qUkUMxadm8fXWTSakICTo5or8zXLrG4vtwsK5NSHtWZuex7tod1rH5KUvqDVyPB647vG/bLtbWd3
Sh6sp5bAeMdHRFyFz2SJhffoKh/v56yBCsE714w2AHinkwUx9F/LwyPxWUEKyLCn7B9zfwncYHTG
IcOrYIGRxVvmVHS/LaYcluIxUgaxdCtD3+9ApyT17ZlIplavc+q0xUi9FQluDuQkc/xuuGTEyPtZ
KbZZFSDUVheFhWki0ewtvFG12siAmy/fEVM+SVnAkD6v0in7F+aK8CpQNSOF6gFRTzjENEP9S7aC
i7VmB9W+YkN4nxgljIxe/oAxeIAVUNcvExn695XHi0ABtbPT79pERo3M6pR8mgHxuXzuUZOgg7bD
VLzAOlzNCK9Vxsi70nICMfYOXFmuCk/sQ+dItbe2MuWB9/4HcMGvKsinuF/Cfp9PnQ0kc6z4FItN
Covc/P/9766SUGNVk3i7ibB8r34WU43Ziv7jJ9qw8ZPDf0jmlsmUlbqDoRjO8ivT6YvqmHcQjdWv
/thM1RU/wnk1KeICh19zb59iU3TMWeA0QOz/u/4Vb0u3804zLnRVOM1+f22H+EM8a8VILNY4RadZ
zkU7dYOT8ESXrtU1cEuMPIrU0Lyd2o1LSYMg+f/7Ew3/+ZzE5tubkglOo82m+wuBD4T7HRM7gonM
0JGroRCIgitO5xm1GkZEeMBJDNuAYklx3dHsDX79+BulzJVA7hho66OHDeyw4OPVdDKX2y+yOqza
pTZ2vLO35O4LI68tBuF/B8HIEQjJHMYBDZyjJ4rbeNC99hKGmI24uIvPQywBgdVYH1fkNxmwzNqS
NMmSEu0A7YpUXw91qhBXx9IlR/yHiDbpSS/AHDH71YCzqivAaxt2qC78PkoqCEFT9nrqa433OA+G
eLKRLMAu5hy+XYBXgj9Cp9fWTkS5XnbmWs8mFS+oGvpzO35IJjfl0QFqdl/rxNKQC8Rge9AYRKhw
TSem/Fq32aXeUVQCxwwZKqCrfkUONUOFyt+hdStQo+Q8IwVHQGM0l0DakBUpr7lgVug0uYmxtE5m
zgpRhoi99Z5OYguqXtv/bL1opcomIa6uGaFnHn5aN/0nxVEvwfbfe/uBz2QBC9DJQBCkmPCMfX/I
G3L6B6Z5bNZdUOhYi/QcnS5ECb5lpG+ajVGvWzA7phNDhUkyV0bUqEKqri+CYdfdcsZT6KA7ZL/5
YhjDAasptw1KvL8MMIMLz+qSK/TF9OWhq0fWW7yymhpq2IvkTeFlRJ5vc/yeDSeYMEQvmTA4H5GM
jIqRGe8UxPwyamB4Rk2B2yVguj7smLObHByxitVMIyw2aQ7CHT71P+TolY4zvUdYPU39d5p+QTbE
NrMuYZ87uXVbKjDnZDl12pq/3v5Ua32YqVw3wMFHKlJPqI7oZgSgz6hXUsED/isOaQA1Vh1WcBZX
5hx4DF1UOG8Dky97tk7lf5T9MmGPhNWxomqCr5gfqVQoYdcuhaGfuqQWCqJB83/fU0mOep5xbxga
xckF1zvCga/J5w/dSjd0NLM+l9ZsuS0IiGWmGuN7fPjFRipU/pL+bANglm+QEawyuxuAqtS3Av49
SAuZgqBEdNE7fzPs8B53vbHk6MIwgm+bs5vRWt7Gfauh7/bEpS8ytOBsSTPMaJkYITbn7RePrFQI
qm6lEI7EVfByZzKu1eD8sqpXK0/QC+3tdxwRw4WAC9hcZJ9uWJByVmljZO48Y4ozK8XWerlUzTeU
S6USoGXJ5+GlbaT40f9OtGQDGe8ws7d6VFmCjB9XDt0iciwEhBCK6haBczXNsArNFGHsHsbuoot1
8rfkcKLGA2m5Cq8vvPgMNjzjpwf9njqN4R8luKMWweKm9y4lu39cezQBJP5LP6KLgrwUyDrednfd
UwhnrdzfLJ5/kwwptSREJY0r5QDylhZ4XMebzdAdghOky4LTmNyvV6dsL1CI+WilKGRBAwOpLvHd
tVUqqERW28IXEmctVyXfclsK3XSG8A2dJCfuHu6fWbIzlrAhjUkXIfZI9uENWUGDndxb4BUqshyU
4Gxqc0M2KoNjopCZxOvVyDthOj/a8ef8ZBs43DcjIME9cWiidFTNTsQauh23HkuQKIe3Xe6PzTYT
jcQjSag/rMQjAicJDbThXDLQOb+JixcRV3Vqpj8It5dsW2jLdp9UYUtS2bzwnPyQdf8A0e1IHvVX
7RAOuk0JThxDiV6g2Joi36nP1wV02BO588OiAf/BvWAKIJ4qVHOzBPoD+DKFtGPSWMd69ljeSBxQ
tGe39x/i21MH9LhDB3FnDiO/dOmDYeYeUkf7ZNwLpbw33XlRDfmqjOjSZwl3d52M2wPENtKmJlbE
7Yb+MVpPhdxdh4ite7yKpMcl7RBjhdkmgx3L/B8V87g1MRvhJ8o9wVuvWHkOn0AWTkfo7Xcg9So1
QoIgJ9drwSOIQGA5MRoRIci7hRtQ3CFdJKGJZMCN7DizO27Ub6s0r/UzkKfDLbvA+1bpETtSRcOI
d5O/mTkVJVV0iRbzpiVe1VZpzGs4oRukWqxW4+TZzEI/9hxMqcLmfRjLBpI9q1HwkEXlpI1W5b6y
fb7vE0U2/9yawC0iLsyV6/Cf1lia+2B4dt/yzFvscW4RPWRSWtevfwRLN3lcM1HTlzsiuR78mnKT
up/sNaO71+Jl+dx4YkuxeRtdOfcUEktNPXkGyNJkDAV0g0P9w45w06eYvm8DSrIZ/P5eNgWLP9Vi
T5QHzLHqdrrw1QgJ8EeCHRkX+TLw8tpE6zDuhQjpsUBGSK8Kgn2OShLSLtuAEK9rQNiV4q/7RLD3
6r6/ZCrrp7B/hHumLfKjTPW2p5nJ6NZ7zAY/dHhI38WtYKV7jHmoyWL6ajqrs1/jOpNToM84qB2+
GFjidk4X91w3yhLnMGyTiwsiNZyc/8QH71Pfa5b7+RwXLD1xrcWr8bv4bWLWRvR7LaZLFsfZzWeh
UzBfAwr713maMF4llAF8DkQv9wQNTj0eevPyDlln9/0MmAUYdGj3Uh4MTfFqO623RWSJ7wKs8Y02
ge+H5C1o955kTbZ9TPal5sBHakUAU3JfLXa63R+Z7vwXwNnuUR9OWxTsjWBuT5aISrehX23lKCfx
imZpwnD671wfK0dudVI/Uc3bPKLi5jnoUElkbi6znQ6VyUiVMeo31+Cns+VEJUqa/LRsyYpWfP7p
PB7Wx3EMxNm6F8xV3Fc0PKPkNohncpt3ozsnv2KmAHmzIUiOSng5bvRRBQrnXpd+ttqUJMtmncLs
XAQ4QQyetmU4geEps1OhYh+8kUUOolLJ1nFMYP5Knj1GyTLxaQIEsG66AZGO9+mdjTfxjCt2U0Ea
HHTtP1TLRu/WOnXlte9hW3x+t4hOtyZnIFFMHqTZsplpH0IubPD1BXMawbgFnpvX+qEpg4P8ZKJp
guJ62amZqEUaI0jo+5FvBoMFGbtfUoypzp7r9la9nSJB+M9LHeAb3ItMMMB5d6M5eSihG9iPe7dT
UPg9W1oHJZUpFG69dQVYDk5byNI8jyzoIY9tR8eoVEI9eYeo7I1oLxxYdJ4N17Wp5nMNN6NRb+1b
RheFXBr4FoEj2MC7SyahCMVAUi9ouwS/uIb0+hqSrIbjBN365SCu5IKDNIbqEKOHwX4byj920uVt
FjnO/gN9rsrFSPMcy9jvg24BxsbJvw1RWFlVjNNJY9TFnTqRwowqO9Bzm1v5IUc617s6txUl3bdp
1IijPlygE89fi80OPi/H0Z6kFDJmaRcMix2iCSIP7R1ZnOeIAw/RTCPobYOs1iI8XfWoqqVhPckr
FVQkc1RvQJSdpf4UkV7CbpOeBgwZU70sGjEJvgVFIyaJYPWsWUBkxHckgWIH9LEgNvSQgJSIXblf
n2JI7yON5euPtyb1XOP593dTpi/hkM4ZpEX0d7FOo8CXNB0XE0GP1136qD2hTj9n2UhtuzSO2A0A
OuXJFGtmVQO3M1Om0rkBA+MMz5nk+cYhk2xlhx8xkm8YRhFYB+qKCfqlUQZaPWd0XNhBmIYa9P4g
l8Z/ppz0t/pTLXJvbjrFY4rptBjYZNUfm8HfJmlCHstzCv9M5zFD7YhmuyER5rO8MogRn9p8c5Ur
L4bCiww8USm1x/cDCanHpYanAiMlS1cCfueNnczFa7igU702N2S6LOV0iNOVpIxuVWgcc+QQJKw2
Snjj7uui0vvFe3UxoF4mtWN9G8lwCra+1jfMVRzCO2nxzAIFiNESqdMMH01hs8IAuXI0yI35Hudb
+Jmc0U9sowMakSoBFTvGPUS4HA0YtfJUnoy9aGWnFp7CtRAVPIjLeZyfjdJEWs8JaHdEAZ89U2pe
GBN16qmy/iPARUdUhA24YsDAaDO1hDxp69qJvxrEGYsnOHHz6yEhX2QyeYgZw7qQWv8f0K/rhwW8
ro5HK4V4TwAH/RnxyhkSS3oc+kM24XoVUVS2liqaPdvCklOuJNY7/wICPMaBMlYy5oTlJvBlGasx
kRZ8toTFHtsQg9mYnaK+OHpVfchL6sX3UDN31603I6qhFUmPnpPePCIoxXpLuh5GPbFBWnqdy0Ej
2Rhy0c2Pn4ZLqe4sY8X18AIKlAB0RMcsegngFBAfgW9ZwsHEkXe1GNSPhcPnxZYTlGsWC2qJDdPr
FAujflIZgvBtRPxWCQYtDLCxFYwBG1nKaeBnBiFfN5xGyNc2cbIrBxqgxlA7anDwsAgWiTn/nMCw
0C/ODSEY3NzZqT4kXZKy6RT14ra9AunMw87qMPjZQuymnD2SLHYDuvgDxhf/ehAcsoUfv9scGx8k
6qRxG65Tme6CIG9Qs/auuFJpc6uhacpQxKanjmDGWvoqM9IJ9nHJeEILXLHumdot7OFdCeXcOZ3Q
GLOHm0n74/Mzjqmc6T9WA08IW1sMuQ79diAke/qZvheeFOIjgV7B94vlHRiGg1J8HKwiGE/hKMha
LCC7G173QKIRT+ukYp73i4oX33jtIHv7yydDFd8Opezs3zsE8Jg3hIhd1vdtc9IJZGKAv8IyPpwb
XLtu8lHn2KQiCGS2ZLGskq6UcSf3TrtmpijfdhW+BddwmeMsB3bDhSKN/po5XSpl+hsyixRdpuSS
N+Fmk8twabpfaHT7vV8ATs9f8jUKGDyuh1dJDSdVvdiMQo4oa9jTEq7F8gzlkbz02fHqtitht91M
bvCr3BB4zr1+O9YU6BthEbXKW66VD5Xc6tArw3LBnpyZzSX4mU4KoofgS3Y2t/N6Snvo0QBjZIMK
4EyV0mavxIh9aucuI2tKqIC8trrRuDG5YGBZ4VOBbeuK6cTnn5ceITguX6LKCLdm/UrlKL3C9br/
GTinmW7Wnczuy4yuuk5E2Dns5SeUL7VRlSCglPVmtlE6fUIN7wv7OyUE79ZNOBXoeHmUqWa/uU4K
/aaD6UweMypNM6ducVYZqml/7utcNuje/Yrp++3D65Qpf3ewwy9+jP28NlaOTRCywC8ABVZ/HyvK
yyBtdi6mdsFkasofOgPB55GCV7ctIXdQlJOsQ0sWA3Vtkj4V/IfR9Dy5RpEyp47+Fc2pWTeMnx7j
KWmJboixgEWrG1zV3udonkh4B3C8FOxALBd/uctwfz80jxmha3D19IUYelZMs1F8+gmnxy9Yw7QV
hC6tekcQ5iGmHi5gcwkCEMR0Wp/PLSaRgEq3UZV1Y8okgOYDyKepsbfdcJ5OLTA3Qdcy2ek0lem8
7AYtFbYhs8wI8Z78oHDY5TVrg8EoaubkwFamabsYxJNocMaCsaX55Blu5cFvOUanjqU5gMLdP6WL
5vF6qFmYG7QPm0mlP4RwCSj/3Ul0jmCuIgd1/4wXz3kqWLZKSZWCqCL66ZiIMHEtSz1hXvoEMuJn
UIxAovcQds+alXBKnaGTYHyfpR0rbGKMsr4VrLx0gVLHKXjWIlS6emxMoThIkAEKkA47yYbL0Rff
ssBeNtXyCyPFEw6Hs12b8BkXSHHQA8v4JdQwiax6Iny5vilmPW6aDRCQ3wJLxN+1jmJ8RpBUPXc0
LCbhtW4eYh54HpCxN/4w70gC2FV8c2b1FCP86OLW/06NTkc9t8OEORUYLf/T/WW4qFE582E2DvbP
5EkDviZqewh0P912xxO21PANV0xByUbMC2/eaYUiPdGSsm7K7A/nlOdWI72iYo3Gg5Dlvt+ZnDLG
WOTojFmnU4MZ07cXLtCmmWix4kR61CYuSaN0H8f+gwtquAt+bKV7Jao6FZ+J+iat4d9Kav1jlWtL
R72oK2uP4gvMQTmFK0vmmD9LRHcjPYKPc87RLZuZJy9d+hgNQhAF/QjH7FzcyTZdp42/eM52QIF6
RwN+8g6ZEeiryM32F0okeX1Sv5Z/sbE8iUkXXpn+StvaZZdQsVJBWMCriwv8Ejpo2fluVvQh+Xk/
xZheT6AblMM+JmKhyxnEOEvvwe3K0j9PUzrRodFbJ+SX0rVIOXqG8Ecuv8h6ZSkC71v4VtSv8v/3
lqZYoroyk3SdKxnRDDjn59l0+Ttuy1prRKu72RRmmf2+n5hNR/dDe/8QqxJ/l+DsMgAZdjRv7CMf
yQI+Tv9B9zNwnGxEdoY/qhh7eeRJRed6MLq16rekYe9XR6tV5S7S2bnSREumk1xhU70QAkAvVsCu
d2YZ4qdXBTRj0kt2lhgi9Sd/NWqRqSNeqE1SpWEzd3KAjl+b2XJJnoMI8UIoTP/XFteL8AQmCBRr
SPpy65vc8hh2mwdMTB6xW9W1YmNxOAyqP+ZXmwPqE+LU0EDKOdiP1afqdrjaIY+253dQ9uPdLo0L
3HComKOrxu43ZM/jS1AH8ndaisXkTcuy7yZEJE/hekqSEquwrkv6eXR1nhkCd5huPXAhX3DwXKv+
RufADAr76O9bovcshIKOf7OsgG3QHUvbulATbO78+zIErlTlnKnLymlpvHDlxPOmG0s2+5X5jyWl
vFmrubcD2m8vuevVOQJQ3qrck2/b32awxqxx7NPb1e6QhUgAjGCZVIKFQUK5fphv60G4LOyYZIPE
ZJrvLS8CC9xLZrN21x9vaM7NCG3tpz7F4OJ819H9hL+pskES7P6xw8MwIt2jU+dYAsUSK9S12k8n
zIEaSQiyIyi7vmovtoMJComdikdO5lcyQmmQYaIh9xKn3jNj9U04TdRpEcPE637z3XECrWNLZD6k
5FcOn8BstMChFGB11DVJgsP44u7uvFKYoHzTHo+u7kBusia+RYQEkZoVBI85pbku4KHXzt2cwN/e
EDN1ARIpM8Y9tkZ7gDi3ZM8RsZ1RdJty0MhsTVXwIFR/l76f2TZM0yDKuUChuzobr0tauAxPf6Hj
ywimrHUbhm6PTZ6wp3FggkG/UkjgR7aMIoQrJPhbONzHxU+kdtfXRKvLSIUpf/SpmX03Gbh69bx3
rsrqTBSY0xQj4Cr2QRKfSfbcFaOn0C99Zvak4M2HQ0q+F8u6X7osRYjc6HRKJeBXrBeuC6MuYxmK
ltMo1RCUVSI+GAvey4K2GyConlE8L+Ry+OjNnLlA5RFzmQ9idZ86thKK3ZYd3aSVxPm7nqZCTrgJ
ho8L1kxomfDn+A53mNAqPXUewuHXo1RnNID0pfjGtz0JpnBdltYRtd4nhOct7RmITlIx42EW0OiK
KEyJPdeURN3Xu22yG/jMoYbEs7Aa9IijV4Xj/vBXYMu3m+xyJ4ze9wlHjQ5j5Xc+7N7O0hNUa45x
hWLai7OmO5NXwivwRAf0xXVnIM2GCYIU0DZX9WHd/GKBpLkm06ejaPu9yvrySRnu14oXzGBuDb3l
yaBofkkNIMaA51AMxcQYBPiqo8GqiuSjMbVoDx2q0UYUG2p9rKN+haJB9uariSwjvR1vL3wF7l6p
UT/gBK1Sk9bSUXQzzCf6T2zWQf7srh/NTyTdGVPFOTlrq0iQ5xa/FQdOwu74a370j/maNmXyU36W
S2N4WQ4vFL3HJpb2cA+AWX2OOPDFG9SvYlWlOOI00lAhCjTO2p3zoKaYJg2Sz0+rE0NHKo4L/JUU
Md3Hfbaz2W2Shp2r9NYwknMF76JjmQMMtXg3K39ZEu9L4teQ8a/b8WWIazvGSi/it60NImISXstr
TQ4wD7K+hHz5ZV10NLYjl54p9neMq9mRTCT/QHGR2tR8MJ6SiYWI9qt3FuX6eQd0A4HlOltofyFx
Yhnw9tW3PIMI4uufTKK8N2kIFko+BhOzeHaybN50NlGmcb4ZhriyB9R9w149I0LQ5oJc2NTJE7fn
G+DCJSPT2ImbjeSRJiTDXIyT+uOITO1b9h/N5HW7NzmCUf2wqqAstgMbj/tec2gEITZ1SFGS763f
SPGbE1eM0/CJ1RtZxijm9YVg5YCBM5bUFOY+mjltL7tWAaMu/ImIYeoSfNrHjsbFVYR7OuqvZDMU
XBYP12zDh6EP5TgOajMTt8StYe6ONkRggea1DQ9JVh/oXwDrJAZvLrJyUEkXGZrndRffZIye4Hph
07A6cL6kjEEVVdR87b11LEb1oo1Zy135CXSXiufHtX5s+ArmwMbyzqjfZWgadeR3R0VcYxQXiGWo
WEUj4NaP0R2JVugAYg6JtRSeJLmX30jilBNVT9oOTJQiYW6mHelknbpLbEQykhuR73vhYvDvEgSB
ZZU2n4hDIjepCbobYy465XjGz/DJcjsf0zTrY2e1kqIfhTPn5WhBA6zzUWL2MMMS9EFb+lE3howC
XzgNW/9aWo+2i1m50H8fuTVlwMv1utDA4LD1H3spf5iGC5Z8/h1Kicgl/UpGZZ4DdALR/qLe3G74
d7GgEhhGGUadCEMkYkuSGuPyVPsm5rnk2tLAVieWD1H9PI06Q+1kE0EoAqZYU60+jkWX3BtTyOKR
YVqmRjaRg6rQM1I+NYlknfiNwk+FGoNUPxgWiP78be2Mxa2H7iM22cYNr1CZwHJ/0aUsy7ucx0wZ
pLVzQEFYFOnOmJdpiVmYQOi5868J42Ibbv22zTt2Zvhz7M81v47voEvy8D0wvrfbsaNZTYjiz2zA
YzmvQu8NM6lESVjpDG23PjjGOAl3+a3hbNV9M/6YavdDaTbFJksggyEx2yNJEYQ98OHH/AhqSBwc
A3nju/eDJYlpc4H9dPAUMEFgyusNWkDY/HM2rZDUNI08iYEYf2KM4iA7ozY5OlztgsdCuI6KZAmD
9dHxvVnicfLWD4K5W01cc90D804Ikdyzn3LMInT5SgEZpB8GQQEwEMbwaFRegoMP0NrusRSyiYpz
uprRWZEd5BHcNIxpL2JYXo9GMHlWQ8YDc7tju12Q72Pc/LDUpixLcYozHQoSjgED2HABR69MIjq1
4R4zJY/xXldBrV9rFRfPVRpXX7Pmr8HY2FM2Iso7IV/9961peJovYpsYxt4UNVFXEtW4U5pXeI0d
r6xRqTCFwOUFo3e3KFax32nGJtOWx2HljqljF/OjJRQiaraCcAO9ZnG0KgOjRcYpyn/6ToVlnuz2
gxf+83zsBI9YnjUxkFo4nlTdrPxZx9blEwvCuC/yGlcfM1cd6sTr9qkqvtFuImQqEftYxHthU1ev
z8xOhEq9mAx1Tt8hetDNwzRAAGPMDqojMS073XCLVsPepCtVVAK8crKZ2Yez4dgiuRBbb6nujox4
RzKyuoo7K8fkIVxQisT75kUFGVoz7mw9kGcX1kggzr+ET0N/+jcuIMjw41nqFCLsjSv6rRcTmq8S
PnQ1QVbwnhV96sKdG6e39eDjh0wdQYrDMscnDkiH0nm2+p21IYLcKJWaCjPMBHlu2qzGFH7GGERp
438WvRAnWtMgJUqnukEzLH+UNXbsnXdmCiWbXxbNnU0oADRI3hVTToCQUL15VXBXwBIcNiB3Qc30
EtLT8VcvmXxdutI03n93+KIDioUMr8cHacY9RUoXXbl+vpinE8OL2yoO3g6ySkEGsNwghjn94NMR
8eqyMZVvKNPedpGZ42yffL09uCK13EO9TAoNWEhGzRMOI16zcT82umu/vMTePttnzR9UuD1w4/JE
AWz07Oe0njhZ7gBZnA8qMSoEUVo6ojGUeHS26gVuUwdziFz6rljtVhfHPd3FdpjO7K+01pXCqA2t
y9DfkjBhjNeLKQwJLkxHFgEFbdMKu+zDoB6/esXn05fb1Sm/Ta9AEcF7U6rIdh5ddQZ0lE6e5Ct9
pCBGtLohFLwbsaGTw8icFMt7YJVMOq/B7EKH/R0Jy6veN0kzEE6SSzhPy9CligVnubSWtCR1uQ5s
YCwEKHfPGzKoJOVKQ4uUvPkowko6ja18pha+s3Rg2QGiWc69Rygv5phiSGASX0pFvAveJQykruey
Vp8r9Dno4riC9ijqm+0u2KC1PvFHho6XKMcyRLjviLV8bvP/iNSEmQ1b4h5nGI6mAnmlcvPVQhS9
jCtxrZ0kwabbns1y3jStYLARZhr9Km6xoK/ZfnjJdJw2ggIlJGMQ0AIpe8k1G1UDFtCcONvBADxI
5COIa42aNPCQ0AUsy9yibJkGeEqBMco9tMgaiU82zvvT19dxvenvV95b3iCwc0JdANUQ3f1XN4hF
6Ag8N32T5ijrB8+IxqWAfpsW6k4fX1rofln84Hh4t8Lnu2TmhB1ITZzJ6WAbSPrL8iVA3blYCL03
H7DNbeEifHCahwXQGybhOMa/IMWwt2vJ+niFabhR5WNakBjW8M5XnI62S5zBceDAxDZBunaqLGpG
ERY5dPw1xx41C7tMgrrFSQqV5BHWGWfEJxyW3q+3o5imjosnGC7gmt8t366rNo0AEFXTqQ9Abp4/
87ERMf3AzvytBmwb1NcH4o7NhCm+HeKSbESKfcPtXCiojINhx3vKfY1/XoyRtm5/RkqHV8fZrC+C
2pGpc8CzdpMK6+5TP4xNu/7vi+AN+GaE3uvUUJdTo8/He7nBFTlqMCdF1KA0wVoaOD0UxjPXHbFV
8PaKejgbMlGL7RWrWCxZpd+gdh3TapuwrG8WpBJtpSx8qWs78tXoctW1ZtLuzRhDDWVvY+aKAkUg
ayJiB2EAjWKBqnph17NBmbnBtKY6u+ZsLIJLKpf70hn9ODFivNEKseVGn5/K6mjobl6ya6yijTcv
sSXZhLIagMtxzQiXVPTj6+VC7X1iySsrdTto+olKBqLsHbClltQhOeXnaGONK14sfhhUPqSHnoUr
BG/cYbCixXoI2ujV3gxWeluTvzdB14bdUAyWmKUZLEjkQmrWjCIirvQ89bE97DDxiST6z5rPu7q+
9JdpVGfbksl7xZZ+afRq3xRBoYV6SBaj4cU4y6UuUmN3Bv9hcmR//PbaJGFrGmL/nsWuvBZvKPG3
iX76PWooayBR7pCy3fHwroGnEhVER2HgrVQiWH8YQ/b+Yma6WwD8LSWANViZmnOTM9X2pwtFZOE2
H8DMA0hRuL49F1aQnVryaKrfIE+c0MllQLZaai1haUV8tqAnrW3XsBlTkQ5YAisctAssWo+6ubey
cyBvwpYgTjp57GjKPCoEc21IZ9luSZIsY+/yRgMlCHa8+UJEOpBOmQqeFeWCOL61yy0AbZ024FTF
ev/ODX1b/dBfYPHpUhr4lmyTWBeEfcjSfkuoj7tvoRn5kVFFB4ZsJ6nN48QX+bsZzMvB0vzhgAv1
ba7613HI3MTlK5L/mysqROwepHEQ93YgGLI2oXQBkZISFPwiRQovRo8WWPH8nVzWW8pTFSY3dGeV
kwuvKgVw4Jon7JEV4Ha9FFunmwRY+vvgJQ0+RNvXM6tt4fRzh8ivIoSPmfS4HROZTuP0PZVQmtTP
NR624/enwHpTxjjr8rDl4OMNHdeXLwzwq+1Yai+kc9JBePrFBDx9KJQDUvT6JrCuUK0XEwncNLVD
EuCXlcY8mHFEKXDeZ7aSOEZexhY+vXsP1HWkh4NG2yVhk2Qr8X2HiJrKu+MKBCCDzjXbH8YBl0oN
jZf1MO0oZnBMUBwS2Mf11kiqctUoFeWe+Vc91TEwbYPJImqfsJE9gfGsFe98vH1tE03gBAu9pC7T
f+KQtkwZ0HDrWayrlJHvUKmw8mK8CMcePBsWLdtgStyrPTAGxsWiLbh/8WP2mSMBlGmBtVKeCZxf
nOa6EhE97iwgUj/gpAEGxGRJuZFIG7uOXNdbeOgcOcN64BQcgbOhIybFFf6ONMRQho+EcRxSLy4W
GTUcdldJi2N0E4Zt6Uq/0yC/unpSS0Nja0mbIW66KxV0pIkBXWTxLBhCRUdlM7QiTH9DyfV7pApj
1/YNVADQz3+/rVMmRp/NLNJYB3W9Si3RosoUTOLRN31OBmfd/9k+0d/MTgqKkDTjDlZe7T+GvhXP
nRtUmuCCg+BqeSsUHOZ+iszb+RLLIEaZP5liikGcYrLG4XCGHET1S6Xt8BGkdl3DuKD5zBOQd39/
BGzPgoSB2MEiLTIjRbKXov9KQwzp1jUITudKGMHVSdewiHx+zda+2O6b7TGbH07SAogdrru7U7mJ
TDOPOq/Sb0b0hqBh/U/iO4a+4gWoZlwYFe0aC7wLyfJai8FPA3v674fM9O+QoMfXAneq+Jkjfob3
3LV/AZPpHXvLwWUfGPjQRLgLgupWtUJglmsxX/VZUvSRwGEn+h55VQDtdbwlScRvCbRIoNUlRGtL
2Awhtm2Dz7KNKi57RKLop8HFG2MHx46SEjQqa1cS7qwixApZy2dVCcIovaqGZgYVFkGAMEqcxETA
GkD1TPAA+ScVMg7M8o3SZVpb1zs0Rk72XDX9koN5vcE8Z28kMbQtOO5eRpIuideBVxgnTF7CogoW
/kP9HxUjENMo5PAAe6dGPWKGlZnRAuaOpLxfyH+T6u38Ku+E8Fw7lc9XNDDP+aWaafjdKMfxpfIU
8d/RuW/wAorV93mxeSFfxHaEqchW+AsrVERZ8SeVRFeagouLIq8ILg0M2BjtCH7Ttgj4ckBd0cEl
ePtYaVAgepMP3Xh3hZINg0bxcj1z3ylOnmkNRTJ31/E/L8E/fKpWzxEzt5CGcUEgkOUK72JMMJCC
THpuzx7Cg7L4x7Mu97X9CPdZ4ib9ruMiFUr4yqID6TZA+uFTjlWBjy9LVy1x5UaLcUUI3+rLCYAV
kNhIUEGywkJcbbWZka83dIpJdgsrAXbikBArC6YjhOklk2CESGdIW+6OhZBdzkKDxmupXY70Lu4T
vgUrIt9/L7TmtBPVpLhCnDtUpmpWXGYpKFja9HxrqSC+sDtV/GLvqz6avWG7RH8lZlEqK4txK6TL
a7RdM4yiyb5yGZsu8dwP8c1yThT+0Ur6sWF5bMr1+2wShnKn3JSXNTi0d9OCqMFCj+sRgyVpwGRw
LqtSRAgS5LF88ePahF2MVheuObsor30xuJx7eB7D8aOf8w29vp6W1n9Xi31E+dFtM+fXLbwkq5B/
8l83TdD0dLfOe68xErb3pA5KfNdHZYgpVbqNwOlS+nyyRIeX9W9KZMrhP4yK2R2Dn25tMV9H8LvG
aaG3zVnzHYO2RUdbXgmKZVUP84yNZN0DyBENAViUD7UX+xibDNS8wfQSBy0KVB9T0kE31K3ar2vp
jwqUvjjV05+BqsLPCiRCrGT/KVt05ax66M1ukz+I0E6BouEezYUCPf8V07GjfeQvwvoO/QXXm6zV
urp3+2s6ammkSe8VYywu8hJjxLs919sfqJgeauwTuIfzDjBNZbIYTiL7XK0tKd8ENzEiLvakBKKm
Ljy2RG9TV/fbYPe0Yv1xT3POryJU5xsPQL1Wwn5ATbCfLdLc5rLF7msm8qwxjbniyu7AMtIRYuUn
Ts7GnyE1UYw7HPhxoKcdQQgvERy3Yjc2Bpvy4VVamoTmXkLmwNyrxXQ65tkZ5ncAuEWEN//MywYx
KuujMvGcM0j1kU21hFbcS7AaHS0JsyqtD87SjtSb0IDhJ7K/rgBQtma3Q69yyK7OOWDWQKBpFq9a
vTMQcDLs0/nJk/lrLjfloqP82rKxP+RFKybKovNyPXXhzSDeRYLK3gGYgzjkwDi7k0Ltt4/8oF3b
u0Dc7Cu1t/il3mBJTypE7fuap6lY6o4CWOvl+eUob0e5QPu398TvxeqWx07djWwSy/l1uMikb78K
2S7rcrIYhpej4otr39D8foEWNKLwPph1RoUTmRPVA8MelkZzCM92G5Xofry0CHRPNV7ffWlgchat
/soUIoFed2T/XyGxTWPSUhi227cq+8UMbLhcUuMybcQeGiBBlH2bKG1ks6mjSO9ZjpwBqN6v83i5
/b0Bj+tKEFO1xI0Amory/bf3OCWdH+myBYwLcA3fk5z9BV79nd0aDinHY8kIGP6XIFCg47EKMnaq
RDqap4QTcePV/i5/fe7AHdtN/K7VvUBfqGq3vTwJ1dQxKjtmdO5b8ONuNo4WBafIZzBqxJfaILCn
W8tmXlN8fERIqo5534u29y6K8ANYysM+xTn84mEj9xXctEAzXswxlL6UW4GMx/PWum43aHhVRD2+
mVwXnpFr3j8MLXm849HrdhrRtiqPjHczyg77Y7z5Nidkrr5UNM0g2E6oYZ+miAVyhx4K1YKgJoV0
nhldjn/EsLaHY7fgbyMNsFNpCbwapT1Wpy+XokyCKyhVDaTk7MsEQ2gTjVbqpH/gqm4ybguaCeEZ
bneOccWOAy+k+692QATp/lINfsUUipe5CgjGBw9b/GIokMwcbvoB8DdAH7vloeSDtcW84uTo15GU
ZSlKl8gWo5rVNgw5EtxvmJSHqVQ7RgR7ecnPlYPBkKlTnzExJAZYgB2jJKX+jlvNHNCX0p5bVKhF
Px2ymPgODiECFiRzIpdmvfjsbduDMYqAjdFSlTegShSN1kE0VveYl0+uDbscBIJVX8rVagQa3GFk
ub5FTwAc/1XHkRqqLvwn3plBVADXGoTPKjgZIFldMdRVBB8865JMspUwStQHRIGaASsi0ELOe9x3
e97VgJDkrSJY9RWJxgJcar68IenwBIf3FoVti4hycw+Zu8EpKf2q7Pf3g5XG+gC+1GyYGGy0SfyJ
dobQxtWnU3h0SPjzfjdopXJgmvzZUcAQi2trvc/hccm6fisj7djkEKgNUZkSjpUwqIEUDTaRm+pY
1bxviH9C2aytwTdawj5u2F78f6EEupMS4D7M1FagNo9fwks6h5tGFtzuaCWbojnJcWpqf++mjoqi
1Jfhifr7T/k5cLffP1IMZCqNUj41Qqpf3SlhE4UiWxUG+XqQwYvipfIv8CMB1PuAcs2iDj7/2gwD
NIWaro9HYzRITpoyVj0gLhNuerwDG20txEAC5n2Gq10BENgRDpPc+uWagK8QKEM/mOkQ2jLIcPEb
Qw7G6foHXurGj3Y0uylghDB8AFIFBN2GwJht5tMQwE53ws2AZYtkBgKAz9sBSUNGnh9eA9yI9imm
tnlzfjbxusezW6HqHTTVyKaJXIHQmN89wlCNSRv27bmZLE4VNvri6VTsQELo5IMDkXJ/sq+sH/mg
A/dVYGcc8OLcL8KSa8wiTk5NH1Wsq4MfWtynj87e1LrfLtx/kyTiYZAbkLZ4g2OIHFeAw87LsIbT
2YDrspWfDhk1uYMGKEsZNUB5b2wqt5wAG4km+isgN5f9DGo/nSFbtQbDxxKHrQyarK8n2C8JzqFD
fzNBahSb8Hr8qR2dp6i659czpeBSoHVJF8YQCTfNR3tBIZQ72t+teFSfPjAwMeCHMebm0tSI96XR
dhNIaBtYBrLoFFfZXLl+aHclr77CZskIedkk2b+QBdJQTNMg3lRF0J0hZ3lTUH9hhtyTBvfzUmOU
MRDoKj4hlAXA612ft4/iBDDSMm+QkiDdkx2f2Rb4uFnJrD9bcgScoiFc0MkIQZw3ifdJ0+F0FZ6b
IrW3RG0rubbBbhpD6dYCr2AiSQL1zDfp5yxux6OhWmPB6fdDdUt/twEc0x/4ML0+1Dv61xRqVzjS
ERi/+50SFOJB1Ut2X7W4CJ8zFEYnxAwY7qKS8qV9b1xfbBG0wqsU9MN+IvID1pr23IVKFe1IFQ5D
F86dmxm9tbWXoWOj7enrjOOHflp/rKSN2qeVmKDLIdAZtNSH61GDOS3ogfXhYStIGPqNo7Zc98wT
SrXNatRbQZ+hQ6mDPMLMVItVx4cReAPqvM1Hoh9B+OwnzTs7T7RJDj01vhZ+z/8lP6f9ljL2FyJ/
fDiAyenKMdbcc/85iKuphdgW34ARdCEUutroEhTb/k0RZbaS5XtOrljtwEon1r7CgxVkpNefEQ1G
LvAmzkjCSxSyFAmIIVdQxk4fGtDetmK/xVLzrlaT0af8q3MQxhbgK1Xj71vWfYOp4gCdWdQ6Xo2Y
FXa9zMWsAN0RBEpmsCRTbwKt6OUh6hKR/hJMDG9oBJ0TrlPspQFibWYumMurSls02Mq78kiQJVmx
Gdx2FsD26J6L8fOwtbsXvCD/GBbNWcHyyYi1oZaUuldX4+Rb2dPVnd5xSzzvCYWae/lW52QTf78p
q3HGv+KMVkcJi/u3FrxLs1l4eopI0ToL7EW62N/GE/s9vADKq2Rorr6+//3BhSlzKdPqRDtbi3Pb
JJmy6auMlzu1Jet2GwK8JartTVpXm+ivcu5gvsaD0s+uI+10wnrfIfFImMkFmorjpqtXtto0f3VO
JDwFRdpcB4ieEnn9i/zEgmKVak/7Kjpipumyb9e7E0xnmxnAdZMrCOrnTK/el0QtIX/Yk1L2Yf64
a/UXRBKrkqyGnXbHvLq0zEPPGbxP5biDuWVKynnDUYpWYZJfhBdB7BEJCQ0w4+CijPzF2kWtlvyq
SJJFw3CgI8zb3l0wGS8BfQC7tufEoVBKaruR+fgLqgGOPXqmTGFDBpL6mPKdjeGn3em3JVshbtG8
HLlU5+j7tSKOuY1z2eyhAiydUfvUnH0/cR2V0qEAdaKZydvaaCN8fSAXldf53Yqaoi+pvAQFtj87
5Ke5EYnGLPCuiO9u25+AXiVZpLeK+4KZqIw2riENsj3LVLL2g7jcRR16PZXR9ClGR4X3byyQnKcl
oknqnYOfCx3JVmVXPqeWGEfEVGqI5UxN8EbxGG6H0x6msI52tZsFeygNnVUTNHMk37ZWwUItIlBP
jyMuQMUQ7+jy2eEwol3tqt43v8x2qH3BQPsFf8KBd2JkLdJZVI/0uBoCBI5wtdRb3qf1svFZJmig
3wttYp/xPpTgvQJUneMTeeXsBieMVBNRqK0MoyEZI/FbBWDXfbgzJ3S0sGlW4S8Yb6ERi704Os90
4rvLIHjzzRN5BPZ7WaGNrlRjokHDEgBeecuUhyiMxJS1UQA8ruzLGW+LLYJ9GGIVl9CajIWt2y5a
VF6+iaxmkKkpyMiQOtdKQ7LgeX8HnplZGu5wf2N7P0Xzb38xT4hKlwKwFU+dsTd21iXFk3i3AIcn
LcKMF8sor8oyreXaM/zFCrAWFko2XERx5gl1zvNPF1hSkdApkWCfHDFWVAALutgB18kCyjXWoLmO
pLVHdWNA8vyzy6R+4VUDDxL/t2vC1EMgBFZ+qGciP7BGTH8jXJO0WZDOt7g9rZhDtFmREOH7x96s
d7cC9kafOIzwlhxiQ5hQTaGT9tIAp0UHS7QhAo6uIVk2Cou9RCp10wIz7hVuQ/E2u5Y7h9jEjwun
hyycI8SrSPgOhyvrQh6sct96x6uFRJFVuDvrvwGWgQxaoDANVM/abwTC0zpbrkO/G0gasWdxksQw
bydQmV1D9NLHo6hRSWTW3O/nNWf1vJA8Sz0uaO24pQEvKIu2eL4z9/2PP2qtdguIdFeS+4Wmy2KW
0n6KXU+zrdfbPlzdgsntg1rCsrp5a/pDOORY0r/bmoBzPMD8gdgtD1b1sZd52ZhJJLw5K5kNF3dL
HOYZehAekMiOXARhSnD3shDNh1db5qgDE+pi2GMyH4qk/h5lGLQj/XjE+YK9wqrnWoAwoc3R79Ln
2tCdNZM5RVjFKeFoOu3VNZoaYKggPPQbs1zo6CmXl3ta9DU1mwpsA41sEOVUFM59jBq/qwDYcTeU
8G+WEXnn6Mw43blsTBhD+r+bM6hI3zpzug3cUo7c51iSA4JoOvYfkYVXYn0BPL6k+LfXbaVM1D1d
u52XgjyaPA0tlpTKpd1AMJjR6gGsLObNnatYUrN9SvUivpfQfgI8mflx7Ej2/S5nEAXF/XarKtqG
EUt9LFpdRCsGTHmUXNYlzuNX0+ivsuO6FmTi/PKlRS3l3yQJ7HcHfBiVBkkHAtCzbXyeyAyMNAdq
/xVYO0yRmPqr3L1MWU157I2kjxjSKtfQ1t8DmD5qU60IldaJZShQ/lbqb79xnb1Xr7oLrOWe7k6/
CI4IYN/+Fl+9K8zwWmq8npAP2xoywknliyIXOl+UyLx+jriSsKqCh6J9tAfYE6hfUc/P6VAhBl3W
XimcUsfEZNoLF7ljeLY75NI1JF3HvfTCR7+0HpjIqbtr1oSwqIXO1UYJaMzGNSXjQT2GE3sMqR/l
ztDaYuRQvRiY02DE3rSaIuE+N9ZpVaecxOY/iMO1Yje/tE5dLhkcKGT1d9hvmNYKqil8Dxhox9IW
f70eRhT2AbnHAHepCiNA0aS7pF7cuQ5O2J70BejV9FmFvPCBjypurGV0EUhAs1Imj+8M7c2TRt6i
QShgvkFkZpTIESKSUgvQJBf4z/Q5MxOFVuYRedNjpB79EtJmkrgjlRpKr9k5SzI1vMGqEV3orI7u
A1EuP0y6/n+ocdHQ3R6S/M9N1bMsewLPzaqr+L+AmLJdx5XGf2/W09IIgf/koWVNDXcijXU96w1I
J/dPCz/HlkYLfXyQaaK4F6UzdizazsJPA0fUw0zRYzeMzysSpCp5iF0Q+DyEg+QqnG/sd5a9Z6hT
7xxdmJrAYKf7VWPGGDSbnF59YAclchJOlA8jPP5k3tBRlugyLffHXf+avkTu6HvavRgXebJFNAaT
t7dLA5jeU5w0tAsJiokCDHJMrVMLyNealzIVQTes9BIFPDkdqa5EUT216NiwzUcgvywISJj90WhF
ecqo7DLJzy1DDtXsEvYbrZAojpokrOnywdPMMyyzq7vjsqxaRgtVPDdiBHBeXWYulJxYM9ruWbOl
/1YmffY+UUvomPFv5W6Nkv5X0vxun4ON4B76jDYemntcXPkunz6PCYwvkGUfqA9BwrlizWzsHtl5
pS2sGlRX35CH75qYvXO3RHfsMIR0wsjrcTLWrirD0yqKPCqjzakII+hxEN/FFWq8IQmjXAPgVfao
HYVqqwEgEhlhMNd+aFjF1uaYl162WXr/SAOk2PA9nXpOynRS
`protect end_protected
| gpl-2.0 | f5f44470891f5cd3b0e2b04ca1f22274 | 0.942938 | 1.845822 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/cmpy_v6_0/hdl/cmpy_xfft_so_sync.vhd | 3 | 10,801 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
TM0bSlc+lXOt14BQuxaXRDy0VMRN0kZ8+RWuRC4pBK4rtjiIxt+eWU47N2r/prNJVwALaYsI9N4n
6V9bnEOwTA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
BWeZbDAHV+nOV0p6coeAYaN0pFmkxpnQqws1OdfbtDHq75gQFEFOGNz/eiG42OgFU3afr9At+Jst
C7ShHK6hpzH6q+hwbJ4L/vz8W/JLsm9/ZBd84op0eGKN/AUSc+4Z5ujjaze9iKeSnyme3TJOEdY1
7CyU6Npw0dyCtJ1NlRA=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
IBFNSD7hxg5OKYvqUf+qg3qdy/Uk+LWWe65uk9NASq1fgC+c2EDKP3yDmNqs1UDtcCNIIGFtAAFY
czldjbDux6yuiH0p5vY4lSmxvAD6Th1Gefi7x9Uiq1TfWp/okhnbBZkaCF2ag/hdCHF4bDyhOJFM
5TdZMCFRe8JLCW00AL56dkqqud5MZgHWbA45r/y6206uj56DtezcA27ixck9jB7ekrfohVlQ5uBA
ajV3yKy3xmqvvEWIdWoD8bE1W98QLFIAuq2qDvXN7XSBbd4HrgrVz+pGfweZOcjkxW7DrUt5zVWe
At8TjdONLn9/kJK07hL4xiufVtjtpZznJR13Mw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
IDCpVunbjdoCIh71yMtX3OyNxQ5ZA88Voh8oV8rovYSo9KUxiLl/iqWp6QCs/nmGTbyN9ywyw5G4
f9DcOX7KZpGCCTzfNHzL0o+0Kjfxvhlml/s/0By26F2JXd4Fmp1aa/LSoV3hcEhAp5pKFSGijYie
CQssaL/BUOi3rMV/Ouk=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
oV3fi2SwH8HHB1GqV7KwIagagoRNRikyXV3EmPibvV2zksVawfM9/GMrae7iIq0IEnRBHj9sWvUj
bREKs9/3bOLT64iVPDVIkYEtooSBhTTnXY9KIFfiS6/fBtR3k+1QD8p3iDUmJXMe1BTcUUPGsMPy
npb/pp/QQdssACIHYgxm0eFA+4FZ74duOTWZRtCXGdJ4SXDOaro536uQ1U2bA3ptLIEtaGuB281t
RFV1HbCu6NtUKuAjMn2F9PD8xvtR1Awbi+Ho8EalJrQS/Znru7W+xvvHeRNHjriPNA0KZylj84Oq
F0TyuaxkGyxE2s23FQM6WYCcY0Llh6798dyN9g==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6256)
`protect data_block
m9Z2IzezjuOcpG9iL1ntrRbiexM232reOHtcZJOUFHJwGhGgXHurUCKfh3yJpux6xnTDpHe6w7jc
CEt9yrHPWElBrhil54K9S18bugEhZj2/npqKDinMyh5ewR/onbfznHDE0/4MDSh5r3fbllZ2TJid
PfncaJ3o7HWE96rMPTNOG1MFn8fFNYlBCaeHQolY6FsIJu1Xqw6F0NpDh1IXtKua6pe7j1k77ZZZ
S+Zo0PAf/vRC/bAUDC9Mhx2nFKffBcnpr4Q8y95YDUCnDyR+c69RRCGccBOHNw1A0roKRNU2BmJM
pELoP0ahvXrDMK12P/eWDCihAfOUCGV0D5nI3NELPZzsch87FBb7D69SUhVz7FNb/ryelUeiTrYJ
qiLSyvJZb2L46WQpLTJ5N4VT+SbMEH+0dCMQOPOAhzoseMQQ2/Btz6PX0jW+SBznAIutOT+3N/pf
VSasONoEn6R21qyXrAlvP13GreYvoD5qREMyG4kd1HxZGOVBIT/pBBeS9DkvkzTJNdKSUVt2DyFw
LGftWqoLRXXRwcGDAjgdYob58dIhX1VDRSS8jA1xCU5M3cRKL01iJPGtOW7INNu4R/BHeRLVzMa9
OLWg0oj79F6h8CeoEBm1i/nN+uCPRSP2LrHsbeYCANUR7ffw+cpNYxEWvIapaDO+zBBKUt1jXPxT
3h0D6hgHOrHh8Its3CMLBawr2++nBaYtGTqmDQ/dcYtpJnkG47nHJH+6T8zUBJsfaFtwV2GZws4G
Dt/nnMPOBAcwWUJFD/qC6Wd34a1jsAKCJCVrjBPiKsMRVGvrHDx6isLKf9y9Ym+V96mla/IO3xWe
nX/ECWkxCIvGnejXPBNDMEB13aUPmaHnYHSx1UpUb8LOS2eKx2xvmpmuYHr87UwwnqrX0alsjK7K
vpxi221dXnWghsPmZLmpcVCcSWcZXPyBZSqSjUkvz2rx5zDq6b6hgaS2jwd4Dsz4HYrdRAVm86IT
4xKx0K/KnMesjZIF3JaR654iF5i6q8Azlj/ptpVR8S78qy3W6tSd4pbsj1aKZXUPfrK8TaMA4WXW
oQMpVmMnseNmD/V95zK8r6mVhF8uudP2sGfOsc8QyCk2qj2VcWFovB+cA9HWLWzjdNLe/drrVEjc
B6Eeac7Qc3SXgK/k0erv0/wZkgrADq8c2lTv4gDHXmuT6XSMRyP2kSTSeOeVpN1+wj40eOAc3qAa
QqtTrDcpM5jckSrGgaUPupSU2cIRu9Ti19YHNk8R/Dhmz2AhGunymm1eeS16NAcpKYJUTI9hwFvO
fAVLfh1HVwM8RPFl3XUMTdxeynu3Qfn7E0Jbegev1YsobZdE0zcyP6Hrdw2m/vU0XLlJO6oId5EN
MJ3dd/az0r+vy7jhuOXVhYfnxJM3wYuO15SUz8ZPGkqJG51XDJ0ZaOpl33SdvvwKFjPnCF4QZV4L
gljLy/KD6guq2cwWWp+Mz3dPAfFH3m2K51CleIexu9sJDhSVn46BoGKwz90O7rVLeUq8vFaUBh18
8PUs/APnbk+HK/9wLdm/jk1SawjP8j5sNEBHBmosq2VbFyag8zisFcr8OOsqKIMAhIp42nswO4Ok
Ns0QCNtdUqzR5zqOAoEIu2gLym8SXXIDNAsG++tWsvuawgUuwocK3hK+57foqeHs6VySyp5jWBZp
EFcJTT7JewHw4YCUKgSf6DWK8TYi3J7XC90zNZAkfrKSRmEHHNomPPB9r2o28MtyKk/Bg3qdoHe7
7pGSxrLmaU7ENCWliqaEwa5gZcSAKagUbYSSG87Uw+pOg38MLMYRX1oJaq6dRCgwH2UcVRSQD7Fc
YaA+pwuofnnim4frNn5woYPTKP6CL1AillarHn5j44xqg9HyaoKBn0XMN8wWbAcaotJq9spGVFSX
i8edI+pAn2C4YFy/xQPp0CAZQfI32xKPfs9CVw2vgzH5wCWnJoAATDrs6DIPz3lkn2E2qAwbL28j
G/NXzJQgdJXa7SQKioo3JhYZBNnIgwo88pgbW1DqEAYCw43pO1cDN+FGJgXc8Sdg11rdXb4zacAp
LxgEpdaMqvjDjaKLtGhTIv6u3kCECKWwkLLmH0FCa5NEorzzhPLNOsepGfn3aSMjYiw8B/56AfCk
Kgq2JFVuIn7INJuaSiw5SIoGdmfbCtwp8YTiCISk4YjxuVN5K83lPlDWMMD6NI3T1Ef7i+8Y8W7K
hI5vyLhp7Z2C+ZuN920/5xaehHyPU4NX61B9hL3/ZZHnUiwUIfMjx7L/y9fla52fySKok2fWZyDa
JuFIgO+CLDtEewlvhGMKaK3CA7c6G9nsklQEqLpbZ9dUNU80RZpc88p8oJka+FBTQVUY9VaWmC4t
oULllvwpNSruI1byFWGxHfXCEW3f9r6rFBbKOtguW2IFOH+8DcnrSRq99aiNWKUflcJxCv7qfqLl
5Hqopeb6AKanKDxXnHvUFSGiuCe0oiQheLChncvwbKAV76MDuphJT4AGEQGBk5dbkknz+b+z2Q/b
iEGCEwvcPuH4vG9CpwjaEkIMgMuKYA7SfqhSwHRYSesq1MIBxJxCPFMi3C8H5DlFYjgtNlEUx0kE
xt8s3/q6SWNVjMHFgmLVoU8BqETbiOn5lgo/clsssQCsb3LPyIUm6fxMlfWA4d0TNW7UcFzVInKz
+cvYGb/S9F/vDjKi2mvNXbW5UKwiNraOmGvCF5U3wn1ED00BQb1fMGJCg46UCB1cqehgVL5Uijp0
EB1pMdgbYJ6OD9jgO9+/RImomFbeg5EaPgDh6RxGuaVWtiZXqiJjKZLuf/8ZTc99bYRvlgXoYBJ1
qjskX9UKbAx71ch7dJXeEiusS8JuWLwmJikIEIkTg/RztREJY1nbiw3H+ZmAWpkB91eqeM/I3kJn
iPS46vo94LMU6uxS8xrAApFa+qtBvrCz4I6RiAO2pPyScSj9FimRKLvRctoB6R8HVW/f7qyhcqwz
OH/k1su1FK5NMto142yANppeeDykfRTiNLhh8lfxal0swVoEbQkbTRV4t1I0ItKw4MAYoICDn3jx
0FWSeRrlhgH+PlWrL+OmBRcq5vfXMsAqXsJXPnO1mecPYINa5RTi680+F/LClqulnggiZoxn84WZ
MOLPCVxcbSvh3zL2DUD+j4+GTE4wUgcPN0EQMxO7gWKJVbu3kWNNuTBBM2PNW8qOTGVb4CyA+RBM
rsX8mwQWougBH79i8GWYFU7gnPBdNwEts8/+yt/fKXpPc46b3zwlG+Y4TIxHCNeXsjhB1ztxyD4Z
JaKSUqsD+aMXsPjQq60ghpXaphYOBz4CF3Bj9MVR47wU6f3G+Cw44Q3/dzHF0Mb7qoXe/7q0jQVu
iQNTPlMgZ3zdZdk0MdsvXSdcLmJyjvxBknhzoISVX72vWoh88wukngd3tBYIbP8v9KpL9ObFyvX9
+fU8SjUHi0wIbYz9r8qli3V5JNVFRPmyKJVWanhGV+8AjpsGe54Vk+5roHxF+RLBcfADXPhSkfqW
u2Vzgj3U3liOX4wRvfwuRafhIBIfSFprkwZQ/Uf7wmtxThKxWvNhldAJQvptK+xyQtZ3tMNrhcMe
xqFUWLFnQpqFWXbVhfnojKvQrWLpMUVqwcyZ1Btj9WzfD/3d4IT8jUFhSjNE0cOfsynkyq8sU9Yy
+GEcRCmtAu17k3EPInc75tJkSGaO6BevtCLF8eWisod4LGGMZMFYQvzjYdGFx/bNDNcbXk9tSDma
m3nCer+ENGXjuibnmUB3VhcWVstydtBVj4ltatWN21Oh3YMzHP5N/IKpR95ucNtjwBlK5UxPpX1b
qSnwpKnObRX8U1GR5ay8ERCYmccZmRgt+YuknPN/CGUzybNdk6U15JGOjE6iFa3FXw70pd7aAMtT
ZaiJ3b4R8DsL6m4gNBRKatJetR4EF50dpdZZOIUnVrPoEf6eZyoCrsyMNCCoWvTCSebnXm5GQlU+
JxBYSYZ7pjtjwnD7D60jvMNhTYjd/t/3Sog2Ek7rrDwkdk6kQ/4QPydseaZ4zwqjQ6IXf7Cff4V4
UubCf5xG5F0UJU7FukeTVrhZOzrLn0VDFXkAi1aND49YTt8lds9ltVhCZtPP723o8jrwSk+ALK1r
1pqHnvRmXPJRsZ9gVLB+jDUia499A4cd9dBfHKR2BAWEe8PBLaX+3WBUHVcKcTtU+7GqSlUe3eBr
4XJ6iH8oE85N5p6EBEhzBJBLL4Bnizw0gGLpLagVfn2CbkUT2h6FG2YPMO5XqV6gHUiHTl2HFoXA
b1kRklQvUP1sOsAC1G45G8O4TUX6xdhPLu+CH2WOvjGoXH/ZObhsXbcZUaXxPCJNXl6Ciw3d5NPl
nyU6WDGl44l0lUItJ2bdYusxZjkK/Y/wG9weJNV4QYcGrwD1twVZqZGOVF84vJgHyx/zLLDL0f6O
b7j8I+qNT+SqP+24pqTmc24mXKdrQq/xXCfFjw81JQLxqHFZhjNzD2sOSev+5NNY54inCIsnZdG/
SwzL5VeQ33y8eiFw0MnkNycOR5EuAfQfuUVCTHNVTCuxgGXiM4+Z2MfXyEemr9dbUe6u+4kPhfXK
dGlCSXke/DtLbmp09k/A6dBlI5eRF64yvMHBKT5+7eyE94mb9a3UZY7QwNE+iQLWavaYCfjMD8Qs
Dm/Bp7WGJx0TGx3x3swZMHdMNFeKHX2zqnGpCoNaOaI63V7vJsPyh0TlnY6DgBU9ffxXcoU/+QVx
ufJJ+HbKu4KvIgxN8Nu3sez5CufrcloKq7qdn5CBj7bZr1YhQtfaw0OfbH3lWzC7FSQPEcQIjWsJ
uAhg4/Grbp3NX8Wlkftb/WXm1lhOLGWxe4P/pqf30T8vl9McciFGqDgaFzuIWGfH56J3C4RsvMJw
hAUHsETlYTwS0Thsmup33dzwWFg8jtGT7XaorhQPEs0LeCVXF6blX4y3iBxuWOym1+lrxJWGAgKY
54KtUcvXXricQ7I8fUqp25p6ATytyVNBwnMwK8Q2ZDczVa+KIIduTqY3I2lV0C4paY2AUgB0bj/X
VII/oVBz3Q5urb+ixFHxSWi44CBhcpKFUu4pbb7UMOxDetK+AEn1KSNvJRChcWrhoSs7/k/Scm8L
7IH2Q99HcjzM8RlbrBzd8hHW0zXtdDa+mYHVy9730tUPqmpkUrzkgKbfzIElPUO/CNlBe2sDoOJT
uwX54TknVagJgOgI0Yw+W7uZRuN7yHdYQB0VTVnh3J5A0amgz0phY6o7EoNwZp71/70LVYR+0Wxg
fQ8C7pAieTkZy827TGJe7NYGb4hBr/iAmy47XX9xWxQCVAUQfsxKXR0l8bKFiA/WHW0UV6MNaOV7
xVLum1q/xLhQHvU6i2kJmmFxVt+oyUVdx3m/yk7gQdbkV4BO34CMQzw7UgniDza/ptafXI4amoNU
XdsYkvXtBPz7qK4LcrAu7kWC2d8yCrhlJqsxU7t/6XVCt8FUlZ3W6FFWJbggUOD056UWh0SqbE9v
o1g0KzyoTpwFsjbISp5lR4ANDJlEuzUOsBokFB8wv1sQIjwPLvJnWdVdCzCQT6CbXFztVl+7NEgv
7IYgiKuhu2/GRDhO/e9z8F+qQM3/l6Jc1SZbtv8daN8yjUF1gHAwCgHyoqyAmEobQMLttl7SEG1s
4LLOcnGu0ynlqjiXWw7oJ6kRVRHspGWVo8phfV7AZbQmraR0j4+OgyqWWIxP0LrnvtVu4MANnost
dzJHlfCbOOOhjuP7CPwVTo4IwTzVuX9265rpYMt686jKOcvaZEhzmYbOiXCSElTe3nmBjjdUY5YA
xiXr4Yb9cps6fN2pkOVt3Otf25R0Q/Oo8JoLW/kZja26P1n88OY0Ev7tKzGUpl0EExHHJuVStwpf
tQbftSQfA8ThggANQIA1s64X7Q8pUwmaIXdP29j3JMDerZVPGPFoaNU3pZ4wQMW7aZDmwXDDoYOK
/HueqP6ZPwf1nIKR/CVQtlfn2Wxa2lrt/x3MBTQzxROFdaVRqDXdMK7AeJbMTMDEUeDITf79DFlq
nwzhx1iFPR0SasSmqRd1QMvzIMur+gc4FnDqUAim4XfA/OX9TeZTrC7HGVJf06eXF7Ua9caHnkN7
wNuX9GKXxp/tlVCDBIfexhYyLofp/naOzj4EKZ+Vk7d3EBl9dx60Qmr+2xgWnXK02iJodgdjohAb
bwQpNORjqnsd/s5So+WVXtDRDYjqr42D/tIbqRydDtlEmCMkCVr4OA8phXDvRA/mvN1AYz3hn/ZO
OY+s20IPD6AVAHhGx4Jx0E3gSRLwBI3RcNyelsadF+TUJHsoQsojOQsyiqTwY1iFyWrC4G5rtbxz
BSKHJpn+8FePMSZqsaKCVqirKq6YvKNWXvOihpPlQ+sF1KY70fTMiRhTRot6vf5whmKCuLiuwEDn
g+aYULuStmX+g+6eWJ90DaB5IEYq0YOnbTqJA+sixlXBlo9r5HQCp2UozxqxMQGpUd8UY8tRy+lg
V9qpTNahYsicfEGFwD445du4v6OiMSdlTcPx29MAeDyJJmkMpo71MtuTpLMK1E35r79PRk7Z8XV+
v6t/K0317OVLSsyAVr21CatXGnDbuceyUJk3A5gfCDI7Y8egag/AJsIrqQx65eL/Xw3SpyxwLDrc
GuKMd9BAcdhOPqZ4jd6KoneD8xrv9Wjy7TI8M+Ig8pzI3owVPb4ooRh28B5WvnTowMiwgzTJ45FY
4HMvDIYB8DzQ0I6GPlKhg2ELtJSXyO3V0pbLJHPQ1MKkZqWxAodCt8Z+bAYbNAqWv4oFXbWI1EMM
N7P/DBPz0sIEXb5uFFYvT+m3B1mfeYUDGJ9OpbsH7dxBu5fdSN+5W16dzxo9uYqUltVvq2obcYHJ
OWjSeqtsqyqHUcORbypWb1nfw+ZPcX20sxnupPKHRovq9kAv8QuVmlCJmLx6BcjENQAD+iUPkcxm
o4/t6YlrSCnKBbk6aY5MT2mk1GrcFK8Pi0Tq2A/Oo0GzhJWusCD8vlYEXoCcGmfBJ6RjCGmJGMb0
vztf+/6B9fLSnUHiZv5LJ1WgfM2OSQGfl3jf3KsglgyLYgPTvLbDFrXqbOLCymn+gUejsR4RTnSJ
FtEW+rvmwlAuDw3xEQUdEQCgfdUQOMWbls238jePN2yywBMO7blo1bxihfT5Q9s/IGuydAEa45Tc
BGOXk20UxmUJWdwWP8FQ9Bksm/4fEV9xQoChfN/gWciDZB48en060W+D6N3l2/d6dgIP3qTguhQb
BKc0A4oTnfKL7h5E3GeHDP+8ujlUSUkXITyIpAqHcjKaNAsdy2IF0PCzTlLtF8qf/NqxVVYqa+zh
wfBDWSw7eBVAq4htCrePCQ+ZW5h5tiNOdUKfvBPmchElr3gFGuc6YK2yz6vJyU3YJWPisclxk0Gq
a2rzGhWTXu51GXu2gCszuOvygweXr2cDa+uRxlZFum6wUZE2k8uszWHCOTOw2pHHsgiUmk4q/oNG
1GB7bx6LUyKss20XhYQF/KL0VjqI0oqc0DOK7UiDCROs4PXryS9Ci2I7WYQKKRnl5SzmAofqf+dA
M2yL68psdrqBIl/StY6tM4uoLiFUKpMuySRLg2A9UIj1OO9jRaWbxOku0ZIN0q8pkkNHMQrWbx6P
tqnYX1FE/f/1H+671HLR6tex6ATcrVrIuh/nniyHi8KqNN1bIRrSUQNIfxccgngy3hbkO9GfEDio
Uy6MN48JZfDHwUBQu8j34qG4JJA5kuLMamCJBLxOyR3ZcpFAU8QbjZw8baP9fwAe8eUJjYz+FVDp
E0QpCpVGDXBCRNgSkh5eHeSqbeBlkPoXzurPOwar5lz8RzrbtxX2sQ+BIwdfydpmXeCWT0mxW9wD
N4D/R1XXHJ55itoGptKUP+Fqy2WWkiG8opc5UV78yIi2c3YMiOWEGFjFTQ5+RVCKlRJ+DiHEfSUC
m4gsZXmV/CJkZR6C6cJyRVWd3eHrAtM/V4xT3SlACMFHdB/DUD6W5v6AI+wHPZKQiUFy27jrY+rs
g6VZm6CsaKs9C3aH1RmuCCPrbI7YmC1raCfnZAvTm6V5dN4ELNxbEm7Zb5Wsf3SP/KDu1ynTy6Zm
dbv+Rvn9Xg1KC4MOXVxbzge5wTwVHhrDW758rahvIp7mqjClACIpSosY+07hcfgwFq4rIqSZUZeJ
psnj42AAAX67k/IU6YWDvpoAtA1BKJD+d3GcCzghhzZ4AnBRtIKTzhAMmzeyb2W8LXkVzKDX5iY8
RskIEcqpvKnasA2JNdmAOHKVXe+R1KHIi66rebBbWcjlTxuM6yc6snj8gtcEoT0+VA8uzXvQWSRc
gzsLDM0wd8NAdLDR6HGYrXiep6ASf+1viZpZ3dEUHCbrWaPpzGvDbMUyFw==
`protect end_protected
| gpl-2.0 | c7b3f72be3d5a1439e645598c9e190c6 | 0.927507 | 1.900581 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_2/part_4/ip/dds/dds_funcsim.vhdl | 1 | 76,044 | -- Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
-- Date : Thu Mar 20 00:59:05 2014
-- Host : macbook running 64-bit Arch Linux
-- Command : write_vhdl -force -mode funcsim /home/keith/Documents/VHDL-lib/top/lab_2/part_4/ip/dds/dds_funcsim.vhdl
-- Design : dds
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddspipe_add__parameterized0\ is
port (
temp : out STD_LOGIC_VECTOR ( 10 downto 0 );
L : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddspipe_add__parameterized0\ : entity is "pipe_add";
end \ddspipe_add__parameterized0\;
architecture STRUCTURE of \ddspipe_add__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q[35]_i_4\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q_reg[35]_i_1\ : STD_LOGIC;
signal \n_0_opt_has_pipe.first_q_reg[39]_i_1\ : STD_LOGIC;
signal \n_1_opt_has_pipe.first_q_reg[35]_i_1\ : STD_LOGIC;
signal \n_1_opt_has_pipe.first_q_reg[39]_i_1\ : STD_LOGIC;
signal \n_2_opt_has_pipe.first_q_reg[35]_i_1\ : STD_LOGIC;
signal \n_2_opt_has_pipe.first_q_reg[39]_i_1\ : STD_LOGIC;
signal \n_3_opt_has_pipe.first_q_reg[35]_i_1\ : STD_LOGIC;
signal \n_3_opt_has_pipe.first_q_reg[39]_i_1\ : STD_LOGIC;
signal \n_3_opt_has_pipe.first_q_reg[42]_i_1\ : STD_LOGIC;
signal \NLW_opt_has_pipe.first_q_reg[42]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_opt_has_pipe.first_q_reg[42]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\opt_has_pipe.first_q[35]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => L(1),
O => \n_0_opt_has_pipe.first_q[35]_i_4\
);
\opt_has_pipe.first_q_reg[35]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \<const0>\,
CO(3) => \n_0_opt_has_pipe.first_q_reg[35]_i_1\,
CO(2) => \n_1_opt_has_pipe.first_q_reg[35]_i_1\,
CO(1) => \n_2_opt_has_pipe.first_q_reg[35]_i_1\,
CO(0) => \n_3_opt_has_pipe.first_q_reg[35]_i_1\,
CYINIT => \<const0>\,
DI(3) => \<const0>\,
DI(2) => \<const0>\,
DI(1) => L(1),
DI(0) => \<const0>\,
O(3 downto 0) => temp(3 downto 0),
S(3 downto 2) => L(3 downto 2),
S(1) => \n_0_opt_has_pipe.first_q[35]_i_4\,
S(0) => L(0)
);
\opt_has_pipe.first_q_reg[39]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_opt_has_pipe.first_q_reg[35]_i_1\,
CO(3) => \n_0_opt_has_pipe.first_q_reg[39]_i_1\,
CO(2) => \n_1_opt_has_pipe.first_q_reg[39]_i_1\,
CO(1) => \n_2_opt_has_pipe.first_q_reg[39]_i_1\,
CO(0) => \n_3_opt_has_pipe.first_q_reg[39]_i_1\,
CYINIT => \<const0>\,
DI(3) => \<const0>\,
DI(2) => \<const0>\,
DI(1) => \<const0>\,
DI(0) => \<const0>\,
O(3 downto 0) => temp(7 downto 4),
S(3 downto 0) => L(7 downto 4)
);
\opt_has_pipe.first_q_reg[42]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_opt_has_pipe.first_q_reg[39]_i_1\,
CO(3) => \NLW_opt_has_pipe.first_q_reg[42]_i_1_CO_UNCONNECTED\(3),
CO(2) => temp(10),
CO(1) => \NLW_opt_has_pipe.first_q_reg[42]_i_1_CO_UNCONNECTED\(1),
CO(0) => \n_3_opt_has_pipe.first_q_reg[42]_i_1\,
CYINIT => \<const0>\,
DI(3) => \<const0>\,
DI(2) => \<const0>\,
DI(1) => \<const0>\,
DI(0) => \<const0>\,
O(3 downto 2) => \NLW_opt_has_pipe.first_q_reg[42]_i_1_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => temp(9 downto 8),
S(3) => \<const0>\,
S(2) => \<const1>\,
S(1 downto 0) => L(9 downto 8)
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity ddsxbip_pipe_v3_0_viv is
port (
aclk : in STD_LOGIC
);
end ddsxbip_pipe_v3_0_viv;
architecture STRUCTURE of ddsxbip_pipe_v3_0_viv is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal first_q : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of first_q : signal is "true";
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \<const0>\,
Q => first_q,
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity ddsxbip_pipe_v3_0_viv_0 is
port (
m_axis_data_tvalid : out STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ddsxbip_pipe_v3_0_viv_0 : entity is "xbip_pipe_v3_0_viv";
end ddsxbip_pipe_v3_0_viv_0;
architecture STRUCTURE of ddsxbip_pipe_v3_0_viv_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal first_q : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of first_q : signal is "true";
signal \pipe[2]\ : STD_LOGIC;
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \<const1>\,
Q => first_q,
R => \<const0>\
);
\opt_has_pipe.i_pipe[2].pipe_reg[2][0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q,
Q => \pipe[2]\,
R => \<const0>\
);
\opt_has_pipe.i_pipe[3].pipe_reg[3][0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \pipe[2]\,
Q => m_axis_data_tvalid,
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized1\ is
port (
aclk : in STD_LOGIC;
mutant_x_op : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized1\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized1\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized1\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal first_q : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of first_q : signal is "true";
signal pre_rdy : STD_LOGIC;
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\opt_has_pipe.first_q[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => mutant_x_op(0),
I1 => mutant_x_op(1),
O => pre_rdy
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => pre_rdy,
Q => first_q,
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized11\ is
port (
aclk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized11\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized11\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized11\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[8]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => D(0),
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => D(1),
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => D(2),
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => D(3),
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => D(4),
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => D(5),
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => D(6),
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => D(7),
Q => first_q(7),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \<const1>\,
Q => first_q(8),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized11_1\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
aclk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized11_1\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized11_1\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized11_1\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[8]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(8),
O => \out\(8)
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(7),
O => \out\(7)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(6),
O => \out\(6)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(5),
O => \out\(5)
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(4),
O => \out\(4)
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(3),
O => \out\(3)
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(2),
O => \out\(2)
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(1),
O => \out\(1)
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(0),
O => \out\(0)
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => D(0),
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => D(1),
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => D(2),
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => D(3),
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => D(4),
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => D(5),
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => D(6),
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => D(7),
Q => first_q(7),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \<const0>\,
Q => first_q(8),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsxbip_pipe_v3_0_viv__parameterized7\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
L : out STD_LOGIC_VECTOR ( 8 downto 0 );
temp : in STD_LOGIC_VECTOR ( 10 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized7\ : entity is "xbip_pipe_v3_0_viv";
end \ddsxbip_pipe_v3_0_viv__parameterized7\;
architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized7\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal first_q : STD_LOGIC_VECTOR ( 42 downto 0 );
attribute keep : string;
attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[10]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[11]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[12]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[13]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[14]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[15]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[16]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[17]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[18]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[19]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[20]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[21]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[22]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[23]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[24]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[25]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[26]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[27]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[28]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[29]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[30]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[31]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[32]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[33]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[34]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[35]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[36]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[37]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[38]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[39]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[40]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[41]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[42]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[8]\ : label is "yes";
attribute keep of \opt_has_pipe.first_q_reg[9]\ : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(41),
O => \out\(8)
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(40),
O => \out\(7)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(39),
O => \out\(6)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(38),
O => \out\(5)
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(37),
O => \out\(4)
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(36),
O => \out\(3)
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(35),
O => \out\(2)
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(34),
O => \out\(1)
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(33),
O => \out\(0)
);
\opt_has_pipe.first_q[35]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(35),
O => L(2)
);
\opt_has_pipe.first_q[35]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(34),
O => L(1)
);
\opt_has_pipe.first_q[35]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(32),
O => L(0)
);
\opt_has_pipe.first_q[39]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(39),
O => L(6)
);
\opt_has_pipe.first_q[39]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(38),
O => L(5)
);
\opt_has_pipe.first_q[39]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(37),
O => L(4)
);
\opt_has_pipe.first_q[39]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(36),
O => L(3)
);
\opt_has_pipe.first_q[42]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(41),
O => L(8)
);
\opt_has_pipe.first_q[42]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => first_q(40),
O => L(7)
);
\opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(0),
Q => first_q(0),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(10),
Q => first_q(10),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(11),
Q => first_q(11),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(12),
Q => first_q(12),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(13),
Q => first_q(13),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(14),
Q => first_q(14),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(15),
Q => first_q(15),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(16),
Q => first_q(16),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(17),
Q => first_q(17),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(18),
Q => first_q(18),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(19),
Q => first_q(19),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(1),
Q => first_q(1),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(20),
Q => first_q(20),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(21),
Q => first_q(21),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(22),
Q => first_q(22),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(23),
Q => first_q(23),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(24),
Q => first_q(24),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(25),
Q => first_q(25),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(26),
Q => first_q(26),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(27),
Q => first_q(27),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(28),
Q => first_q(28),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(29),
Q => first_q(29),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(2),
Q => first_q(2),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(30),
Q => first_q(30),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(31),
Q => first_q(31),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => temp(0),
Q => first_q(32),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => temp(1),
Q => first_q(33),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => temp(2),
Q => first_q(34),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => temp(3),
Q => first_q(35),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => temp(4),
Q => first_q(36),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => temp(5),
Q => first_q(37),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => temp(6),
Q => first_q(38),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => temp(7),
Q => first_q(39),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(3),
Q => first_q(3),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => temp(8),
Q => first_q(40),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => temp(9),
Q => first_q(41),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => temp(10),
Q => first_q(42),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(4),
Q => first_q(4),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(5),
Q => first_q(5),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(6),
Q => first_q(6),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(7),
Q => first_q(7),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(8),
Q => first_q(8),
R => \<const0>\
);
\opt_has_pipe.first_q_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => first_q(9),
Q => first_q(9),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity ddsaccum is
port (
\out\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
aclk : in STD_LOGIC
);
end ddsaccum;
architecture STRUCTURE of ddsaccum is
signal \n_10_i_fabric.i_common.i_phase_acc\ : STD_LOGIC;
signal \n_11_i_fabric.i_common.i_phase_acc\ : STD_LOGIC;
signal \n_12_i_fabric.i_common.i_phase_acc\ : STD_LOGIC;
signal \n_13_i_fabric.i_common.i_phase_acc\ : STD_LOGIC;
signal \n_14_i_fabric.i_common.i_phase_acc\ : STD_LOGIC;
signal \n_15_i_fabric.i_common.i_phase_acc\ : STD_LOGIC;
signal \n_16_i_fabric.i_common.i_phase_acc\ : STD_LOGIC;
signal \n_17_i_fabric.i_common.i_phase_acc\ : STD_LOGIC;
signal \n_8_i_fabric.i_common.i_phase_acc\ : STD_LOGIC;
signal \n_9_i_fabric.i_common.i_phase_acc\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 42 downto 32 );
begin
\i_fabric.i_common.i_phase_acc\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized7\
port map (
L(8) => \n_9_i_fabric.i_common.i_phase_acc\,
L(7) => \n_10_i_fabric.i_common.i_phase_acc\,
L(6) => \n_11_i_fabric.i_common.i_phase_acc\,
L(5) => \n_12_i_fabric.i_common.i_phase_acc\,
L(4) => \n_13_i_fabric.i_common.i_phase_acc\,
L(3) => \n_14_i_fabric.i_common.i_phase_acc\,
L(2) => \n_15_i_fabric.i_common.i_phase_acc\,
L(1) => \n_16_i_fabric.i_common.i_phase_acc\,
L(0) => \n_17_i_fabric.i_common.i_phase_acc\,
aclk => aclk,
\out\(8 downto 1) => \out\(7 downto 0),
\out\(0) => \n_8_i_fabric.i_common.i_phase_acc\,
temp(10 downto 0) => p_0_in(42 downto 32)
);
\i_fabric.i_one_channel.i_accum\: entity work.\ddspipe_add__parameterized0\
port map (
L(9) => \n_9_i_fabric.i_common.i_phase_acc\,
L(8) => \n_10_i_fabric.i_common.i_phase_acc\,
L(7) => \n_11_i_fabric.i_common.i_phase_acc\,
L(6) => \n_12_i_fabric.i_common.i_phase_acc\,
L(5) => \n_13_i_fabric.i_common.i_phase_acc\,
L(4) => \n_14_i_fabric.i_common.i_phase_acc\,
L(3) => \n_15_i_fabric.i_common.i_phase_acc\,
L(2) => \n_16_i_fabric.i_common.i_phase_acc\,
L(1) => \n_8_i_fabric.i_common.i_phase_acc\,
L(0) => \n_17_i_fabric.i_common.i_phase_acc\,
temp(10 downto 0) => p_0_in(42 downto 32)
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity ddsdds_compiler_v6_0_rdy is
port (
aclk : in STD_LOGIC
);
end ddsdds_compiler_v6_0_rdy;
architecture STRUCTURE of ddsdds_compiler_v6_0_rdy is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal mutant_x_op : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \n_0_mutant_x_op[0]_i_1\ : STD_LOGIC;
signal \n_0_mutant_x_op[1]_i_1\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \mutant_x_op[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \mutant_x_op[1]_i_1\ : label is "soft_lutpair0";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\i_single_channel.i_non_trivial_lat.i_rdy\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized1\
port map (
aclk => aclk,
mutant_x_op(1 downto 0) => mutant_x_op(1 downto 0)
);
\mutant_x_op[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mutant_x_op(1),
I1 => mutant_x_op(0),
O => \n_0_mutant_x_op[0]_i_1\
);
\mutant_x_op[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => mutant_x_op(1),
I1 => mutant_x_op(0),
O => \n_0_mutant_x_op[1]_i_1\
);
\mutant_x_op_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \<const1>\,
D => \n_0_mutant_x_op[0]_i_1\,
Q => mutant_x_op(0),
R => \<const0>\
);
\mutant_x_op_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => \<const1>\,
D => \n_0_mutant_x_op[1]_i_1\,
Q => mutant_x_op(1),
R => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddssin_cos__parameterized0\ is
port (
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
aclk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddssin_cos__parameterized0\ : entity is "sin_cos";
end \ddssin_cos__parameterized0\;
architecture STRUCTURE of \ddssin_cos__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal Q : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 8 );
signal \NLW_i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\ : label is "{SYNTH-6 {cell inst1}}";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of \i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\ : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of \i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\ : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of \i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\ : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of \i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\ : label is 35;
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\i_rtl.i_double_table.i_addr_reg_a\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized11_1\
port map (
D(7 downto 0) => D(7 downto 0),
aclk => aclk,
\out\(8 downto 0) => Q(8 downto 0)
);
\i_rtl.i_double_table.i_addr_reg_b\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized11\
port map (
D(7 downto 0) => D(7 downto 0),
aclk => aclk
);
\i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"002F002C0029002600230020001D001A001700140011000E000B000800050002",
INIT_01 => X"0058005600530051004F004C004A004700450042003F003D003A003700340032",
INIT_02 => X"0074007300710070006E006D006B006A00680066006400620060005E005C005A",
INIT_03 => X"007E007E007E007E007D007D007C007C007B007B007A00790078007700760075",
INIT_04 => X"00750076007700780079007A007B007B007C007C007D007D007E007E007E007E",
INIT_05 => X"005A005C005E00600062006400660068006A006B006D006E0070007100730074",
INIT_06 => X"003200340037003A003D003F004200450047004A004C004F0051005300560058",
INIT_07 => X"000200050008000B000E001100140017001A001D0020002300260029002C002F",
INIT_08 => X"00D100D400D700DA00DD00E000E300E600E900EC00EF00F200F500F800FB00FE",
INIT_09 => X"00A800AA00AD00AF00B100B400B600B900BB00BE00C100C300C600C900CC00CE",
INIT_0A => X"008C008D008F009000920093009500960098009A009C009E00A000A200A400A6",
INIT_0B => X"00820082008200820083008300840084008500850086008700880089008A008B",
INIT_0C => X"008B008A00890088008700860085008500840084008300830082008200820082",
INIT_0D => X"00A600A400A200A0009E009C009A009800960095009300920090008F008D008C",
INIT_0E => X"00CE00CC00C900C600C300C100BE00BB00B900B600B400B100AF00AD00AA00A8",
INIT_0F => X"00FE00FB00F800F500F200EF00EC00E900E600E300E000DD00DA00D700D400D1",
INIT_10 => X"00750076007700780079007A007B007B007C007C007D007D007E007E007E007E",
INIT_11 => X"005A005C005E00600062006400660068006A006B006D006E0070007100730074",
INIT_12 => X"003200340037003A003D003F004200450047004A004C004F0051005300560058",
INIT_13 => X"000200050008000B000E001100140017001A001D0020002300260029002C002F",
INIT_14 => X"00D100D400D700DA00DD00E000E300E600E900EC00EF00F200F500F800FB00FE",
INIT_15 => X"00A800AA00AD00AF00B100B400B600B900BB00BE00C100C300C600C900CC00CE",
INIT_16 => X"008C008D008F009000920093009500960098009A009C009E00A000A200A400A6",
INIT_17 => X"00820082008200820083008300840084008500850086008700880089008A008B",
INIT_18 => X"008B008A00890088008700860085008500840084008300830082008200820082",
INIT_19 => X"00A600A400A200A0009E009C009A009800960095009300920090008F008D008C",
INIT_1A => X"00CE00CC00C900C600C300C100BE00BB00B900B600B400B100AF00AD00AA00A8",
INIT_1B => X"00FE00FB00F800F500F200EF00EC00E900E600E300E000DD00DA00D700D400D1",
INIT_1C => X"002F002C0029002600230020001D001A001700140011000E000B000800050002",
INIT_1D => X"0058005600530051004F004C004A004700450042003F003D003A003700340032",
INIT_1E => X"0074007300710070006E006D006B006A00680066006400620060005E005C005A",
INIT_1F => X"007E007E007E007E007D007D007C007C007B007B007A00790078007700760075",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
READ_WIDTH_A => 18,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13) => \<const0>\,
ADDRARDADDR(12 downto 4) => Q(8 downto 0),
ADDRARDADDR(3) => \<const0>\,
ADDRARDADDR(2) => \<const0>\,
ADDRARDADDR(1) => \<const0>\,
ADDRARDADDR(0) => \<const0>\,
ADDRBWRADDR(13) => \<const1>\,
ADDRBWRADDR(12) => \<const1>\,
ADDRBWRADDR(11) => \<const1>\,
ADDRBWRADDR(10) => \<const1>\,
ADDRBWRADDR(9) => \<const1>\,
ADDRBWRADDR(8) => \<const1>\,
ADDRBWRADDR(7) => \<const1>\,
ADDRBWRADDR(6) => \<const1>\,
ADDRBWRADDR(5) => \<const1>\,
ADDRBWRADDR(4) => \<const1>\,
ADDRBWRADDR(3) => \<const1>\,
ADDRBWRADDR(2) => \<const1>\,
ADDRBWRADDR(1) => \<const1>\,
ADDRBWRADDR(0) => \<const1>\,
CLKARDCLK => aclk,
CLKBWRCLK => \<const0>\,
DIADI(15) => \<const0>\,
DIADI(14) => \<const0>\,
DIADI(13) => \<const0>\,
DIADI(12) => \<const0>\,
DIADI(11) => \<const0>\,
DIADI(10) => \<const0>\,
DIADI(9) => \<const0>\,
DIADI(8) => \<const0>\,
DIADI(7) => \<const1>\,
DIADI(6) => \<const1>\,
DIADI(5) => \<const1>\,
DIADI(4) => \<const1>\,
DIADI(3) => \<const1>\,
DIADI(2) => \<const1>\,
DIADI(1) => \<const1>\,
DIADI(0) => \<const1>\,
DIBDI(15) => \<const1>\,
DIBDI(14) => \<const1>\,
DIBDI(13) => \<const1>\,
DIBDI(12) => \<const1>\,
DIBDI(11) => \<const1>\,
DIBDI(10) => \<const1>\,
DIBDI(9) => \<const1>\,
DIBDI(8) => \<const1>\,
DIBDI(7) => \<const1>\,
DIBDI(6) => \<const1>\,
DIBDI(5) => \<const1>\,
DIBDI(4) => \<const1>\,
DIBDI(3) => \<const1>\,
DIBDI(2) => \<const1>\,
DIBDI(1) => \<const1>\,
DIBDI(0) => \<const1>\,
DIPADIP(1) => \<const0>\,
DIPADIP(0) => \<const0>\,
DIPBDIP(1) => \<const1>\,
DIPBDIP(0) => \<const1>\,
DOADO(15 downto 8) => \NLW_i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_DOADO_UNCONNECTED\(15 downto 8),
DOADO(7 downto 0) => m_axis_data_tdata(7 downto 0),
DOBDO(15 downto 0) => \NLW_i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => \<const1>\,
ENBWREN => \<const0>\,
REGCEAREGCE => \<const0>\,
REGCEB => \<const0>\,
RSTRAMARSTRAM => \<const0>\,
RSTRAMB => \<const0>\,
RSTREGARSTREG => \<const0>\,
RSTREGB => \<const0>\,
WEA(1) => \<const0>\,
WEA(0) => \<const0>\,
WEBWE(3) => \<const0>\,
WEBWE(2) => \<const0>\,
WEBWE(1) => \<const0>\,
WEBWE(0) => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity ddsdds_compiler_v6_0_core is
port (
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
aclk : in STD_LOGIC
);
end ddsdds_compiler_v6_0_core;
architecture STRUCTURE of ddsdds_compiler_v6_0_core is
signal acc_phase_shaped : STD_LOGIC_VECTOR ( 41 downto 34 );
begin
\I_PHASEGEN.i_conventional_accum.i_accum\: entity work.ddsaccum
port map (
aclk => aclk,
\out\(7 downto 0) => acc_phase_shaped(41 downto 34)
);
\I_SINCOS.i_std_rom.i_rom\: entity work.\ddssin_cos__parameterized0\
port map (
D(7 downto 0) => acc_phase_shaped(41 downto 34),
aclk => aclk,
m_axis_data_tdata(7 downto 0) => m_axis_data_tdata(7 downto 0)
);
\i_rdy.rdy_logic\: entity work.ddsdds_compiler_v6_0_rdy
port map (
aclk => aclk
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsdds_compiler_v6_0_viv__parameterized0\ is
port (
aclk : in STD_LOGIC;
aclken : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tready : out STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_phase_tlast : in STD_LOGIC;
s_axis_phase_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_config_tvalid : in STD_LOGIC;
s_axis_config_tready : out STD_LOGIC;
s_axis_config_tdata : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_config_tlast : in STD_LOGIC;
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tready : in STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_data_tlast : out STD_LOGIC;
m_axis_data_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_phase_tvalid : out STD_LOGIC;
m_axis_phase_tready : in STD_LOGIC;
m_axis_phase_tdata : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_phase_tlast : out STD_LOGIC;
m_axis_phase_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
event_pinc_invalid : out STD_LOGIC;
event_poff_invalid : out STD_LOGIC;
event_phase_in_invalid : out STD_LOGIC;
event_s_phase_tlast_missing : out STD_LOGIC;
event_s_phase_tlast_unexpected : out STD_LOGIC;
event_s_phase_chanid_incorrect : out STD_LOGIC;
event_s_config_tlast_missing : out STD_LOGIC;
event_s_config_tlast_unexpected : out STD_LOGIC;
debug_axi_pinc_in : out STD_LOGIC_VECTOR ( 41 downto 0 );
debug_axi_poff_in : out STD_LOGIC_VECTOR ( 41 downto 0 );
debug_axi_resync_in : out STD_LOGIC;
debug_axi_chan_in : out STD_LOGIC_VECTOR ( 0 to 0 );
debug_core_nd : out STD_LOGIC;
debug_phase : out STD_LOGIC_VECTOR ( 41 downto 0 );
debug_phase_nd : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "dds_compiler_v6_0_viv";
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "zynq";
attribute C_MODE_OF_OPERATION : integer;
attribute C_MODE_OF_OPERATION of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_MODULUS : integer;
attribute C_MODULUS of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 9;
attribute C_ACCUMULATOR_WIDTH : integer;
attribute C_ACCUMULATOR_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 42;
attribute C_CHANNELS : integer;
attribute C_CHANNELS of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_HAS_PHASE_OUT : integer;
attribute C_HAS_PHASE_OUT of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_PHASEGEN : integer;
attribute C_HAS_PHASEGEN of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_HAS_SINCOS : integer;
attribute C_HAS_SINCOS of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_LATENCY : integer;
attribute C_LATENCY of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 3;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_NEGATIVE_COSINE : integer;
attribute C_NEGATIVE_COSINE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_NEGATIVE_SINE : integer;
attribute C_NEGATIVE_SINE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_NOISE_SHAPING : integer;
attribute C_NOISE_SHAPING of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_OUTPUTS_REQUIRED : integer;
attribute C_OUTPUTS_REQUIRED of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_OUTPUT_FORM : integer;
attribute C_OUTPUT_FORM of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_OUTPUT_WIDTH : integer;
attribute C_OUTPUT_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 8;
attribute C_PHASE_ANGLE_WIDTH : integer;
attribute C_PHASE_ANGLE_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 8;
attribute C_PHASE_INCREMENT : integer;
attribute C_PHASE_INCREMENT of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 2;
attribute C_PHASE_INCREMENT_VALUE : string;
attribute C_PHASE_INCREMENT_VALUE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "1000000000000000000000000000000000,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_RESYNC : integer;
attribute C_RESYNC of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_PHASE_OFFSET : integer;
attribute C_PHASE_OFFSET of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_PHASE_OFFSET_VALUE : string;
attribute C_PHASE_OFFSET_VALUE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_OPTIMISE_GOAL : integer;
attribute C_OPTIMISE_GOAL of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_USE_DSP48 : integer;
attribute C_USE_DSP48 of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_POR_MODE : integer;
attribute C_POR_MODE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_AMPLITUDE : integer;
attribute C_AMPLITUDE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_TLAST : integer;
attribute C_HAS_TLAST of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_TREADY : integer;
attribute C_HAS_TREADY of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_HAS_S_PHASE : integer;
attribute C_HAS_S_PHASE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_S_PHASE_TDATA_WIDTH : integer;
attribute C_S_PHASE_TDATA_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_S_PHASE_HAS_TUSER : integer;
attribute C_S_PHASE_HAS_TUSER of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_S_PHASE_TUSER_WIDTH : integer;
attribute C_S_PHASE_TUSER_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_HAS_S_CONFIG : integer;
attribute C_HAS_S_CONFIG of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_S_CONFIG_SYNC_MODE : integer;
attribute C_S_CONFIG_SYNC_MODE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_S_CONFIG_TDATA_WIDTH : integer;
attribute C_S_CONFIG_TDATA_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_HAS_M_DATA : integer;
attribute C_HAS_M_DATA of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_M_DATA_TDATA_WIDTH : integer;
attribute C_M_DATA_TDATA_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 8;
attribute C_M_DATA_HAS_TUSER : integer;
attribute C_M_DATA_HAS_TUSER of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_M_DATA_TUSER_WIDTH : integer;
attribute C_M_DATA_TUSER_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_HAS_M_PHASE : integer;
attribute C_HAS_M_PHASE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_M_PHASE_TDATA_WIDTH : integer;
attribute C_M_PHASE_TDATA_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_M_PHASE_HAS_TUSER : integer;
attribute C_M_PHASE_HAS_TUSER of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_M_PHASE_TUSER_WIDTH : integer;
attribute C_M_PHASE_TUSER_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute C_DEBUG_INTERFACE : integer;
attribute C_DEBUG_INTERFACE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0;
attribute C_CHAN_WIDTH : integer;
attribute C_CHAN_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "yes";
end \ddsdds_compiler_v6_0_viv__parameterized0\;
architecture STRUCTURE of \ddsdds_compiler_v6_0_viv__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
begin
debug_axi_chan_in(0) <= \<const0>\;
debug_axi_pinc_in(41) <= \<const0>\;
debug_axi_pinc_in(40) <= \<const0>\;
debug_axi_pinc_in(39) <= \<const0>\;
debug_axi_pinc_in(38) <= \<const0>\;
debug_axi_pinc_in(37) <= \<const0>\;
debug_axi_pinc_in(36) <= \<const0>\;
debug_axi_pinc_in(35) <= \<const0>\;
debug_axi_pinc_in(34) <= \<const0>\;
debug_axi_pinc_in(33) <= \<const0>\;
debug_axi_pinc_in(32) <= \<const0>\;
debug_axi_pinc_in(31) <= \<const0>\;
debug_axi_pinc_in(30) <= \<const0>\;
debug_axi_pinc_in(29) <= \<const0>\;
debug_axi_pinc_in(28) <= \<const0>\;
debug_axi_pinc_in(27) <= \<const0>\;
debug_axi_pinc_in(26) <= \<const0>\;
debug_axi_pinc_in(25) <= \<const0>\;
debug_axi_pinc_in(24) <= \<const0>\;
debug_axi_pinc_in(23) <= \<const0>\;
debug_axi_pinc_in(22) <= \<const0>\;
debug_axi_pinc_in(21) <= \<const0>\;
debug_axi_pinc_in(20) <= \<const0>\;
debug_axi_pinc_in(19) <= \<const0>\;
debug_axi_pinc_in(18) <= \<const0>\;
debug_axi_pinc_in(17) <= \<const0>\;
debug_axi_pinc_in(16) <= \<const0>\;
debug_axi_pinc_in(15) <= \<const0>\;
debug_axi_pinc_in(14) <= \<const0>\;
debug_axi_pinc_in(13) <= \<const0>\;
debug_axi_pinc_in(12) <= \<const0>\;
debug_axi_pinc_in(11) <= \<const0>\;
debug_axi_pinc_in(10) <= \<const0>\;
debug_axi_pinc_in(9) <= \<const0>\;
debug_axi_pinc_in(8) <= \<const0>\;
debug_axi_pinc_in(7) <= \<const0>\;
debug_axi_pinc_in(6) <= \<const0>\;
debug_axi_pinc_in(5) <= \<const0>\;
debug_axi_pinc_in(4) <= \<const0>\;
debug_axi_pinc_in(3) <= \<const0>\;
debug_axi_pinc_in(2) <= \<const0>\;
debug_axi_pinc_in(1) <= \<const0>\;
debug_axi_pinc_in(0) <= \<const0>\;
debug_axi_poff_in(41) <= \<const0>\;
debug_axi_poff_in(40) <= \<const0>\;
debug_axi_poff_in(39) <= \<const0>\;
debug_axi_poff_in(38) <= \<const0>\;
debug_axi_poff_in(37) <= \<const0>\;
debug_axi_poff_in(36) <= \<const0>\;
debug_axi_poff_in(35) <= \<const0>\;
debug_axi_poff_in(34) <= \<const0>\;
debug_axi_poff_in(33) <= \<const0>\;
debug_axi_poff_in(32) <= \<const0>\;
debug_axi_poff_in(31) <= \<const0>\;
debug_axi_poff_in(30) <= \<const0>\;
debug_axi_poff_in(29) <= \<const0>\;
debug_axi_poff_in(28) <= \<const0>\;
debug_axi_poff_in(27) <= \<const0>\;
debug_axi_poff_in(26) <= \<const0>\;
debug_axi_poff_in(25) <= \<const0>\;
debug_axi_poff_in(24) <= \<const0>\;
debug_axi_poff_in(23) <= \<const0>\;
debug_axi_poff_in(22) <= \<const0>\;
debug_axi_poff_in(21) <= \<const0>\;
debug_axi_poff_in(20) <= \<const0>\;
debug_axi_poff_in(19) <= \<const0>\;
debug_axi_poff_in(18) <= \<const0>\;
debug_axi_poff_in(17) <= \<const0>\;
debug_axi_poff_in(16) <= \<const0>\;
debug_axi_poff_in(15) <= \<const0>\;
debug_axi_poff_in(14) <= \<const0>\;
debug_axi_poff_in(13) <= \<const0>\;
debug_axi_poff_in(12) <= \<const0>\;
debug_axi_poff_in(11) <= \<const0>\;
debug_axi_poff_in(10) <= \<const0>\;
debug_axi_poff_in(9) <= \<const0>\;
debug_axi_poff_in(8) <= \<const0>\;
debug_axi_poff_in(7) <= \<const0>\;
debug_axi_poff_in(6) <= \<const0>\;
debug_axi_poff_in(5) <= \<const0>\;
debug_axi_poff_in(4) <= \<const0>\;
debug_axi_poff_in(3) <= \<const0>\;
debug_axi_poff_in(2) <= \<const0>\;
debug_axi_poff_in(1) <= \<const0>\;
debug_axi_poff_in(0) <= \<const0>\;
debug_axi_resync_in <= \<const0>\;
debug_core_nd <= \<const0>\;
debug_phase(41) <= \<const0>\;
debug_phase(40) <= \<const0>\;
debug_phase(39) <= \<const0>\;
debug_phase(38) <= \<const0>\;
debug_phase(37) <= \<const0>\;
debug_phase(36) <= \<const0>\;
debug_phase(35) <= \<const0>\;
debug_phase(34) <= \<const0>\;
debug_phase(33) <= \<const0>\;
debug_phase(32) <= \<const0>\;
debug_phase(31) <= \<const0>\;
debug_phase(30) <= \<const0>\;
debug_phase(29) <= \<const0>\;
debug_phase(28) <= \<const0>\;
debug_phase(27) <= \<const0>\;
debug_phase(26) <= \<const0>\;
debug_phase(25) <= \<const0>\;
debug_phase(24) <= \<const0>\;
debug_phase(23) <= \<const0>\;
debug_phase(22) <= \<const0>\;
debug_phase(21) <= \<const0>\;
debug_phase(20) <= \<const0>\;
debug_phase(19) <= \<const0>\;
debug_phase(18) <= \<const0>\;
debug_phase(17) <= \<const0>\;
debug_phase(16) <= \<const0>\;
debug_phase(15) <= \<const0>\;
debug_phase(14) <= \<const0>\;
debug_phase(13) <= \<const0>\;
debug_phase(12) <= \<const0>\;
debug_phase(11) <= \<const0>\;
debug_phase(10) <= \<const0>\;
debug_phase(9) <= \<const0>\;
debug_phase(8) <= \<const0>\;
debug_phase(7) <= \<const0>\;
debug_phase(6) <= \<const0>\;
debug_phase(5) <= \<const0>\;
debug_phase(4) <= \<const0>\;
debug_phase(3) <= \<const0>\;
debug_phase(2) <= \<const0>\;
debug_phase(1) <= \<const0>\;
debug_phase(0) <= \<const0>\;
debug_phase_nd <= \<const0>\;
event_phase_in_invalid <= \<const0>\;
event_pinc_invalid <= \<const0>\;
event_poff_invalid <= \<const0>\;
event_s_config_tlast_missing <= \<const0>\;
event_s_config_tlast_unexpected <= \<const0>\;
event_s_phase_chanid_incorrect <= \<const0>\;
event_s_phase_tlast_missing <= \<const0>\;
event_s_phase_tlast_unexpected <= \<const0>\;
m_axis_data_tlast <= \<const0>\;
m_axis_data_tuser(0) <= \<const0>\;
m_axis_phase_tdata(0) <= \<const0>\;
m_axis_phase_tlast <= \<const0>\;
m_axis_phase_tuser(0) <= \<const0>\;
m_axis_phase_tvalid <= \<const0>\;
s_axis_config_tready <= \<const0>\;
s_axis_phase_tready <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_dds: entity work.ddsdds_compiler_v6_0_core
port map (
aclk => aclk,
m_axis_data_tdata(7 downto 0) => m_axis_data_tdata(7 downto 0)
);
\i_has_nd_rdy_pipe.channel_pipe\: entity work.ddsxbip_pipe_v3_0_viv
port map (
aclk => aclk
);
\i_has_nd_rdy_pipe.valid_phase_read_del\: entity work.ddsxbip_pipe_v3_0_viv_0
port map (
aclk => aclk,
m_axis_data_tvalid => m_axis_data_tvalid
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity \ddsdds_compiler_v6_0__parameterized0\ is
port (
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsdds_compiler_v6_0__parameterized0\ : entity is "dds_compiler_v6_0";
end \ddsdds_compiler_v6_0__parameterized0\;
architecture STRUCTURE of \ddsdds_compiler_v6_0__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal NLW_i_synth_debug_axi_resync_in_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_debug_core_nd_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_debug_phase_nd_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_phase_in_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_pinc_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_poff_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_phase_chanid_incorrect_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_phase_tlast_missing_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_phase_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_m_axis_data_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_m_axis_phase_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_m_axis_phase_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_s_axis_config_tready_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_s_axis_phase_tready_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_debug_axi_chan_in_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_i_synth_debug_axi_pinc_in_UNCONNECTED : STD_LOGIC_VECTOR ( 41 downto 0 );
signal NLW_i_synth_debug_axi_poff_in_UNCONNECTED : STD_LOGIC_VECTOR ( 41 downto 0 );
signal NLW_i_synth_debug_phase_UNCONNECTED : STD_LOGIC_VECTOR ( 41 downto 0 );
signal NLW_i_synth_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_i_synth_m_axis_phase_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_i_synth_m_axis_phase_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ACCUMULATOR_WIDTH : integer;
attribute C_ACCUMULATOR_WIDTH of i_synth : label is 42;
attribute C_AMPLITUDE : integer;
attribute C_AMPLITUDE of i_synth : label is 0;
attribute C_CHANNELS : integer;
attribute C_CHANNELS of i_synth : label is 1;
attribute C_CHAN_WIDTH : integer;
attribute C_CHAN_WIDTH of i_synth : label is 1;
attribute C_DEBUG_INTERFACE : integer;
attribute C_DEBUG_INTERFACE of i_synth : label is 0;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of i_synth : label is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of i_synth : label is 0;
attribute C_HAS_M_DATA : integer;
attribute C_HAS_M_DATA of i_synth : label is 1;
attribute C_HAS_M_PHASE : integer;
attribute C_HAS_M_PHASE of i_synth : label is 0;
attribute C_HAS_PHASEGEN : integer;
attribute C_HAS_PHASEGEN of i_synth : label is 1;
attribute C_HAS_PHASE_OUT : integer;
attribute C_HAS_PHASE_OUT of i_synth : label is 0;
attribute C_HAS_SINCOS : integer;
attribute C_HAS_SINCOS of i_synth : label is 1;
attribute C_HAS_S_CONFIG : integer;
attribute C_HAS_S_CONFIG of i_synth : label is 0;
attribute C_HAS_S_PHASE : integer;
attribute C_HAS_S_PHASE of i_synth : label is 0;
attribute C_HAS_TLAST : integer;
attribute C_HAS_TLAST of i_synth : label is 0;
attribute C_HAS_TREADY : integer;
attribute C_HAS_TREADY of i_synth : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of i_synth : label is 3;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of i_synth : label is 1;
attribute C_MODE_OF_OPERATION : integer;
attribute C_MODE_OF_OPERATION of i_synth : label is 0;
attribute C_MODULUS : integer;
attribute C_MODULUS of i_synth : label is 9;
attribute C_M_DATA_HAS_TUSER : integer;
attribute C_M_DATA_HAS_TUSER of i_synth : label is 0;
attribute C_M_DATA_TDATA_WIDTH : integer;
attribute C_M_DATA_TDATA_WIDTH of i_synth : label is 8;
attribute C_M_DATA_TUSER_WIDTH : integer;
attribute C_M_DATA_TUSER_WIDTH of i_synth : label is 1;
attribute C_M_PHASE_HAS_TUSER : integer;
attribute C_M_PHASE_HAS_TUSER of i_synth : label is 0;
attribute C_M_PHASE_TDATA_WIDTH : integer;
attribute C_M_PHASE_TDATA_WIDTH of i_synth : label is 1;
attribute C_M_PHASE_TUSER_WIDTH : integer;
attribute C_M_PHASE_TUSER_WIDTH of i_synth : label is 1;
attribute C_NEGATIVE_COSINE : integer;
attribute C_NEGATIVE_COSINE of i_synth : label is 0;
attribute C_NEGATIVE_SINE : integer;
attribute C_NEGATIVE_SINE of i_synth : label is 0;
attribute C_NOISE_SHAPING : integer;
attribute C_NOISE_SHAPING of i_synth : label is 0;
attribute C_OPTIMISE_GOAL : integer;
attribute C_OPTIMISE_GOAL of i_synth : label is 0;
attribute C_OUTPUTS_REQUIRED : integer;
attribute C_OUTPUTS_REQUIRED of i_synth : label is 0;
attribute C_OUTPUT_FORM : integer;
attribute C_OUTPUT_FORM of i_synth : label is 0;
attribute C_OUTPUT_WIDTH : integer;
attribute C_OUTPUT_WIDTH of i_synth : label is 8;
attribute C_PHASE_ANGLE_WIDTH : integer;
attribute C_PHASE_ANGLE_WIDTH of i_synth : label is 8;
attribute C_PHASE_INCREMENT : integer;
attribute C_PHASE_INCREMENT of i_synth : label is 2;
attribute C_PHASE_INCREMENT_VALUE : string;
attribute C_PHASE_INCREMENT_VALUE of i_synth : label is "1000000000000000000000000000000000,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_PHASE_OFFSET : integer;
attribute C_PHASE_OFFSET of i_synth : label is 0;
attribute C_PHASE_OFFSET_VALUE : string;
attribute C_PHASE_OFFSET_VALUE of i_synth : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_POR_MODE : integer;
attribute C_POR_MODE of i_synth : label is 0;
attribute C_RESYNC : integer;
attribute C_RESYNC of i_synth : label is 0;
attribute C_S_CONFIG_SYNC_MODE : integer;
attribute C_S_CONFIG_SYNC_MODE of i_synth : label is 0;
attribute C_S_CONFIG_TDATA_WIDTH : integer;
attribute C_S_CONFIG_TDATA_WIDTH of i_synth : label is 1;
attribute C_S_PHASE_HAS_TUSER : integer;
attribute C_S_PHASE_HAS_TUSER of i_synth : label is 0;
attribute C_S_PHASE_TDATA_WIDTH : integer;
attribute C_S_PHASE_TDATA_WIDTH of i_synth : label is 1;
attribute C_S_PHASE_TUSER_WIDTH : integer;
attribute C_S_PHASE_TUSER_WIDTH of i_synth : label is 1;
attribute C_USE_DSP48 : integer;
attribute C_USE_DSP48 of i_synth : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of i_synth : label is "zynq";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of i_synth : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
i_synth: entity work.\ddsdds_compiler_v6_0_viv__parameterized0\
port map (
aclk => aclk,
aclken => \<const1>\,
aresetn => \<const1>\,
debug_axi_chan_in(0) => NLW_i_synth_debug_axi_chan_in_UNCONNECTED(0),
debug_axi_pinc_in(41 downto 0) => NLW_i_synth_debug_axi_pinc_in_UNCONNECTED(41 downto 0),
debug_axi_poff_in(41 downto 0) => NLW_i_synth_debug_axi_poff_in_UNCONNECTED(41 downto 0),
debug_axi_resync_in => NLW_i_synth_debug_axi_resync_in_UNCONNECTED,
debug_core_nd => NLW_i_synth_debug_core_nd_UNCONNECTED,
debug_phase(41 downto 0) => NLW_i_synth_debug_phase_UNCONNECTED(41 downto 0),
debug_phase_nd => NLW_i_synth_debug_phase_nd_UNCONNECTED,
event_phase_in_invalid => NLW_i_synth_event_phase_in_invalid_UNCONNECTED,
event_pinc_invalid => NLW_i_synth_event_pinc_invalid_UNCONNECTED,
event_poff_invalid => NLW_i_synth_event_poff_invalid_UNCONNECTED,
event_s_config_tlast_missing => NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED,
event_s_config_tlast_unexpected => NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED,
event_s_phase_chanid_incorrect => NLW_i_synth_event_s_phase_chanid_incorrect_UNCONNECTED,
event_s_phase_tlast_missing => NLW_i_synth_event_s_phase_tlast_missing_UNCONNECTED,
event_s_phase_tlast_unexpected => NLW_i_synth_event_s_phase_tlast_unexpected_UNCONNECTED,
m_axis_data_tdata(7 downto 0) => m_axis_data_tdata(7 downto 0),
m_axis_data_tlast => NLW_i_synth_m_axis_data_tlast_UNCONNECTED,
m_axis_data_tready => \<const0>\,
m_axis_data_tuser(0) => NLW_i_synth_m_axis_data_tuser_UNCONNECTED(0),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_phase_tdata(0) => NLW_i_synth_m_axis_phase_tdata_UNCONNECTED(0),
m_axis_phase_tlast => NLW_i_synth_m_axis_phase_tlast_UNCONNECTED,
m_axis_phase_tready => \<const0>\,
m_axis_phase_tuser(0) => NLW_i_synth_m_axis_phase_tuser_UNCONNECTED(0),
m_axis_phase_tvalid => NLW_i_synth_m_axis_phase_tvalid_UNCONNECTED,
s_axis_config_tdata(0) => \<const0>\,
s_axis_config_tlast => \<const0>\,
s_axis_config_tready => NLW_i_synth_s_axis_config_tready_UNCONNECTED,
s_axis_config_tvalid => \<const0>\,
s_axis_phase_tdata(0) => \<const0>\,
s_axis_phase_tlast => \<const0>\,
s_axis_phase_tready => NLW_i_synth_s_axis_phase_tready_UNCONNECTED,
s_axis_phase_tuser(0) => \<const0>\,
s_axis_phase_tvalid => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity dds is
port (
aclk : in STD_LOGIC;
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of dds : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of dds : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of dds : entity is "dds_compiler_v6_0,Vivado 2013.4";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of dds : entity is "dds,dds_compiler_v6_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of dds : entity is "dds,dds_compiler_v6_0,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dds_compiler,x_ipVersion=6.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,C_XDEVICEFAMILY=zynq,C_MODE_OF_OPERATION=0,C_MODULUS=9,C_ACCUMULATOR_WIDTH=42,C_CHANNELS=1,C_HAS_PHASE_OUT=0,C_HAS_PHASEGEN=1,C_HAS_SINCOS=1,C_LATENCY=3,C_MEM_TYPE=1,C_NEGATIVE_COSINE=0,C_NEGATIVE_SINE=0,C_NOISE_SHAPING=0,C_OUTPUTS_REQUIRED=0,C_OUTPUT_FORM=0,C_OUTPUT_WIDTH=8,C_PHASE_ANGLE_WIDTH=8,C_PHASE_INCREMENT=2,C_PHASE_INCREMENT_VALUE=1000000000000000000000000000000000_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_RESYNC=0,C_PHASE_OFFSET=0,C_PHASE_OFFSET_VALUE=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_OPTIMISE_GOAL=0,C_USE_DSP48=0,C_POR_MODE=0,C_AMPLITUDE=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_HAS_TLAST=0,C_HAS_TREADY=0,C_HAS_S_PHASE=0,C_S_PHASE_TDATA_WIDTH=1,C_S_PHASE_HAS_TUSER=0,C_S_PHASE_TUSER_WIDTH=1,C_HAS_S_CONFIG=0,C_S_CONFIG_SYNC_MODE=0,C_S_CONFIG_TDATA_WIDTH=1,C_HAS_M_DATA=1,C_M_DATA_TDATA_WIDTH=8,C_M_DATA_HAS_TUSER=0,C_M_DATA_TUSER_WIDTH=1,C_HAS_M_PHASE=0,C_M_PHASE_TDATA_WIDTH=1,C_M_PHASE_HAS_TUSER=0,C_M_PHASE_TUSER_WIDTH=1,C_DEBUG_INTERFACE=0,C_CHAN_WIDTH=1}";
end dds;
architecture STRUCTURE of dds is
begin
U0: entity work.\ddsdds_compiler_v6_0__parameterized0\
port map (
aclk => aclk,
m_axis_data_tdata(7 downto 0) => m_axis_data_tdata(7 downto 0),
m_axis_data_tvalid => m_axis_data_tvalid
);
end STRUCTURE;
| gpl-2.0 | eaf942b672e98f52264dad4c367939b7 | 0.610357 | 2.939694 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab1/Poject_Lab01/RegisterBank2/RegisterBank.vhd | 1 | 5,441 | ----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH
-- Engineer: CHRISTOPHER PARKS ([email protected])
--
-- Create Date: 15:33:22 03/11/2016
-- Module Name: PipelineRegisters - Behavioral
-- Target Devices: SPARTAN XC3S500E
-- Description: SYNCHRONOUS REGISTER BANK TO BE USED IN PIPELINE DEVICE THAT USES GENERAL PURPOSE REGISTERS FOR PIPELINE USE
--
-- Dependencies: IEEE.STD_LOGIC_1164
--
-- Revision 0.01 - File Created
-- Revision 0.02 - (3/31/16) Comments added, verified address selection worked as Dan's compiler expected.
--
-- Additional Comments: Signals in this module are used as data storage registers,
-- going from R0 up to R15. Faulty addresses are handled by
-- not handling them. This means that when a faulty address
-- is given, the old data is left on the output value.
-- EXAMPLE: RAout assigned 12 previously. New RAddr is faulty.
-- RAout remains as assigned 12.
--
-- The register bank is synchronous, meaning it will read data
-- into a register on the rising edge and then output data on
-- the RAout/RBout lines on the falling edge of clk.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RegisterBank is
Port ( RAddr : in STD_LOGIC_VECTOR (3 downto 0); -- Address for register to put out to RAout
RBddr : in STD_LOGIC_VECTOR (3 downto 0); -- Address for register to put out to RBout
RWddr : in STD_LOGIC_VECTOR (3 downto 0); -- Address for register to write to
DATAIN : in STD_LOGIC_VECTOR (15 downto 0); -- Data to write to register
clk : in STD_LOGIC; -- Clock. Register bank is synchronous. Read on rising edge, Write on falling edge.
R : in STD_LOGIC; -- Read enable (Enables register bank to put out data)
W : in STD_LOGIC; -- Write enable (Enables register bank to take in data)
RAout : out STD_LOGIC_VECTOR (15 downto 0); -- Puts out data based on register selection using RAddr
RBout : out STD_LOGIC_VECTOR (15 downto 0)); -- Puts out data based on register selection using RBddr
end RegisterBank;
architecture Behavioral of RegisterBank is
signal R0dat, R1dat, R2dat, R3dat, R4dat, R5dat, R6dat, R7dat, R8dat, R9dat,
R10dat, R11dat, R12dat, R13dat, R14dat, R15dat : STD_LOGIC_VECTOR(15 downto 0) := x"0000";
begin
process(clk) -- Synchronous register bank
begin
if(rising_edge(clk) and R = '1') then -- Synchronous data read when read line enabled on rising edge (before write back)
case RAddr is -- Address selection for RA
when x"0" => RAout <= R0dat;
when x"1" => RAout <= R1dat;
when x"2" => RAout <= R2dat;
when x"3" => RAout <= R3dat;
when x"4" => RAout <= R4dat;
when x"5" => RAout <= R5dat;
when x"6" => RAout <= R6dat;
when x"7" => RAout <= R7dat;
when x"8" => RAout <= R8dat;
when x"9" => RAout <= R9dat;
when x"A" => RAout <= R10dat;
when x"B" => RAout <= R11dat;
when x"C" => RAout <= R12dat;
when x"D" => RAout <= R13dat;
when x"E" => RAout <= R14dat;
when x"F" => RAout <= R15dat;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS. THIS CAUSES THE PREVIOUS DATA TO REMAIN FOR A FAULTY ADDRESS!
end case; -- (3/31/16): Verified RegisterBank address selection matched up with what Dan Noyes' compiler expects.
case RBddr is -- Address selection for RB
when x"0" => RBout <= R0dat;
when x"1" => RBout <= R1dat;
when x"2" => RBout <= R2dat;
when x"3" => RBout <= R3dat;
when x"4" => RBout <= R4dat;
when x"5" => RBout <= R5dat;
when x"6" => RBout <= R6dat;
when x"7" => RBout <= R7dat;
when x"8" => RBout <= R8dat;
when x"9" => RBout <= R9dat;
when x"A" => RBout <= R10dat;
when x"B" => RBout <= R11dat;
when x"C" => RBout <= R12dat;
when x"D" => RBout <= R13dat;
when x"E" => RBout <= R14dat;
when x"F" => RBout <= R15dat;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS. THIS CAUSES THE PREVIOUS DATA TO REMAIN FOR A FAULTY ADDRESS!
end case; -- (3/31/16): Verified RegisterBank address selection matched up with what Dan Noyes' compiler expects.
end if;
if(falling_edge(clk) and W = '1') then -- Synchronous data latching when write line enabled (after data read)
case RWddr is
when x"0" => R0dat <= DATAIN;
when x"1" => R1dat <= DATAIN;
when x"2" => R2dat <= DATAIN;
when x"3" => R3dat <= DATAIN;
when x"4" => R4dat <= DATAIN;
when x"5" => R5dat <= DATAIN;
when x"6" => R6dat <= DATAIN;
when x"7" => R7dat <= DATAIN;
when x"8" => R8dat <= DATAIN;
when x"9" => R9dat <= DATAIN;
when x"A" => R10dat <= DATAIN;
when x"B" => R11dat <= DATAIN;
when x"C" => R12dat <= DATAIN;
when x"D" => R13dat <= DATAIN;
when x"E" => R14dat <= DATAIN;
when x"F" => R15dat <= DATAIN;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS. THIS CAUSES THE PREVIOUS DATA TO REMAIN FOR FAULTY ADDRESS!
end case; -- (3/31/16): Verified RegisterBank address selection matched up with what Dan Noyes' compiler expects.
end if;
end process;
end Behavioral;
| gpl-3.0 | dd2d54e0801eb5e83595d6f5912c673f | 0.601176 | 3.187463 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/vm2/xMult.vhd | 3 | 21,436 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
prDLBAuaZRUeM+1/XIDsYaJCgjaUSJMWEoZwNsAN8Ze0s78nLFc7XU/atQG0XtTnwZ7ZvE9ToIlz
X6Te0v5qtw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
WQPBOntDW4W4/l9+n8gHRqacjFo18pxvwHAHNi7SKq9KVvnXDv95yB/jDp22XbJqyQJnrvc19xDE
sWCjY4YJHX2d6P92UNL6a7U+u4aO3PETIDDoiqc7418PD06Lk3SKkJaN2Tnl84Kb76QAUscHuoBc
4MsLUaYdyipZcV2GhRM=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
oXUpmJ2/cDzk2L1l2LiipKm55jQQpt8KlJ3rw2M3qwsbbsu0LeMrEFKPqUZSsItDiNWFqK0Zonjv
pWgIh2eh1g91duMTrRKgZxNqo1h4mQZX6plY/gCi9/iBwaCN4gjGCij1RvET/Flp2u4f5qUos2yj
rRbbO2JOaTkzMHdXd//h7DfPdEdXfUatbe9c0VK4XmIVuRSDkkEjMpO0CMQ6MAQZ+uyVtPkcIpYx
Gcx1dNUtW0gyfktz3TYftW8AHETMEi7ogHpiOOcurJaRFbI0/M73OW/h0y6DweFqd2IQMwSSLkQB
9mG4+mEum08vmSUZ+WSDJs9xe23ZhKjgu0cs5g==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Gah91k4xJl343rLNu56lOVQeIJawoX6eRDhMHRfseZpy5pXSrJiVq3I6MGWlcLteijLI/k/KCvgd
Eh43fPRZn2TW+I9DFVQbDR4OhnooU2KQyGUuB6/9fLJok02ABlZCdYscu+A6gERm8xZ+E7kqiBdc
BBroSum9fhzHnc7Uogs=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
fjS/YFI2KHIpw2UhUc5SGzkRmOSExbNhKCuOGDhw4c2O2pYXUInbd6f+OaoKCLBjf+SCgcjG+5CL
HisytuAqN9RG3pOTcmeJWs0CYOJwesZ923zUBXUxSUUu63nyTjZy+cd6s7zJZElPPADyvbRlcLFK
kPF6hFJGOppTJYJt1a60kEiX7XNDkXUq6Jvgv2JKK2PM0X0DxZTpuG3Br784A9OugeCFVg1Eft1f
ofdPzjxkESSggMOse80kFvy02KebFzN2R0UFlzxWROOgpCuB2djRe4Nco7ScIvcenNGZOxlkDEmu
PEe3OoDxVBKIqKY06ZZu/sNd4vwgs+z9CSEsjg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 14128)
`protect data_block
U84wBwDOj5h/quLH4FQGel1YOw3YlSC4t2aTedBA0w4q6ipyX3BwiA7zFrpwwGkxtS2aYoHQu4Qy
fZ35dAchtsuxSsAm0x1Gf1ClEL46c6Emj5lxxmm1u0heMwt1a4Y3oT/vMTARFXF5tI0+riRS29O+
iUHWOgA0Ignsmp+tVSgdiOIALD8/oczCmAR8CcrYQ9/W9m62ekgNUY+EIrD5UtIMhzC4uO88qf/6
m7R9vCWpSmCzlOgpKCZPfm6XwDnLmPdH2+TxW2qUmrVDu8BKWMBukknm5P8jc3COFn5LDWJnffXz
J0+IE28QnpH88rW/KXS5WKvH35CKeffLM+qP/Au6fuarCDyX/slcnDVTbRkW/6pwsOIGwAuGZIfz
EKRmmhFfUSQuCHkWQsHE00M7OIWBgZUkjVmidYk8znwrT2r7Js656RQw1lvH5mPnRHx5KsLN9wfm
2tVu008EoUYlRRKqdsSWU4VKG8zI8RFkNOPNsxUjMBOcpm7dGdg45WDaNEA41cygfHn08nAeTISC
vn11X8qwaq+FAXey/n7Ng6YNtuwgIWQ11Lhw+9Y5gSbgYRKe6NfqWeudnDJ7umrIYSa8QgOwcxUm
lyTx/Fa7cXwKiEHvnrG/ttUvWWiPdWQYTNaDD+1tZcHolf95pl4UB4NfAEqFSbL1MMdtU78KOpRf
+qpWxNhIIQu9Yq+IRzlYfiBrwTJbJXMKVwz5Q6wFoeJ41NrDGD0+0dEE44ftX2J9tpFicWuR1EBx
DNsPWTdTMRtujjAE8wAV2HRyq7vfRxtSUnzbBBVZVgokuUuZlBjFm1uaYVywLp3y2TFcy7zcCXB1
EJLZaEvCmGjbgG3MSg5fi1Wv1MB/3DlbRe9aDZZJ4x8Yg8qhF735yDvZj0lK/oP5F72oyQgoKAfQ
sMzYoCYliCmV1kj3ciw49gTsm59kf9xfB89P9kSWlhpMn/TVRtDCv8eVVinE73bs4DcibaHRsCH4
zFKCnzK5DM85pdw2y/yMRYAxpMj3I/J5U4cuifsHzLLQyDjiGsXQ+h3NkyOQjnFMrB6OWQAJyNj+
1uuyzkF3R/7ZYvDu3QPBK/IcrsSX0E7pRHxzjt3JhsK0uJvlxLs4Zy7nhyi2fxyhGe+dSkFYkhyh
TScv/lt6N1bRQkEmlgjpwX3gKTK9KxTKf3okUjo4eFedjgb9LGkSrqNKieQmuVCMysxnUhaSqfbU
mZHWw1vl6OQgZYNCxezAsvpVwj0f+52XSkncX1pDx6s2dlkmAKz5XQsok2SQ9kuzdQPD+bb06vjO
L5+vKFNO7922yEZfBqtB+jzjhkuQCupN/NuM4Zzbq+Mt8gKrhzgdTNXdCamBliV+BopkV7p7QYQ0
3mB0J1KQG9YsjTNbRd2LXVquHAxGlR6g3M+Kv9g2pbPGruqxhfuhc+diZ0O6lMHX+XFJfpRzK10P
r4vjHppYnXY/z+Mxu3DcPRTRDEmbFOpf88RbznIiTG4P7NDHmCiQyKJCEbSV3vn3C5fbE869Qxf0
UYVVE2oM8BuX4YwIbiujwzj4Q61X0q8TS+xB81n99fqLynAw4YCPkpm93WF4f1HTBtD4CVwu+MWl
yRE7X476wq6+379YL7LpEaEeHP8B0DXOpHijmjGs+Z5avEoTGwfs6ySRkZic/C9/2Y7JmwhwQffn
koGq/f3kW6BZ3CgamNhtWKil8uKBwy2HDET4JncB9IZ+iwXxTCHQkF0y98qPN1NzxKiTfFIx/zW2
DiNgQm/s5c4Eu5jGRk9aB9NhFVuTg3FT/S/c+Lb2O8Js7JTMoVN8D4FtoITbpCfgxyiue/QylXx8
4QWhhhcDUAu/OLX2j/zKEYMCy2u6QiY0f7PVeK0WdEMfcpVKL+y5YshDhxnkQwDJ05Ft0BdxNi9C
nV0twqNPu6xud5VXIX9xRsW6EZICUYD/gJLXrTyMlpTKiD6DU0aqW1PQCbvlaHVX3lZQZXyhjQu5
BLY4H2gn+8LMIssH7GdfQCKndGk1H+NvPA4aeYMAKNSfEBADQL/wzSbsIG6CmaGdvEH+1B0jJ7/X
2TcVRAfrIghyRAzrbCHvorvP5FF2oQRnPseZ2I85trG+ABGRxsfaqSaDRQapdUyz3dREUm+CHwpy
8LzJEc9jlFGp8SDYyn+ka4fh71tn6MDHTB7ZrZvd99LO4gSgWmC5PrEVKioTZEjx/Ki3xbduh27s
Z2trAOma4S4pTSvJ8E9xHZq05f0LL4Q9+fs2635Sn4sc8crCBIljjFhIXBSBOUV5jVN9NEWGH5QX
6nfGmHard3mH5EI6oFEdxE2m4D03rbEP28S3phOmSLDMnmB4TdHJw3MclyVxgUw2YSS6++wNZGXX
ppGGkI/q9F5qNZx/vvnbl1JKbLywJ0L8+W7RHAOqmSESlmZzsPzJ204LldU/umWUzYSvleCH5WA7
d2Wcugx93daHTPLAPPxyTs87D51Ozwjn4pZKoEehtamWs2MWp96mJh/dsL1QQDGNKX9cpYksRySN
LGDHiwzAg0TXp/uQlaY184iyveSbpiPVZNIW+ExnSxD+FUyn4WXLBF87KLY6o+fq/BdXNx2/ZGGF
vkIvbw+vWK61B1pwRy63FCPaBhn6NGQ1ZYiINEF+9a3Ed+UN2X2gC0wRyZVuhb67T/Ucr6NupBqD
fdC7+uMeKA7JI7wakgAJbZGxQ0nv2TrGOU+YnSR26wNQ9thvx5hCyoPU/kHVHxHuNpwcRBKLnQ1Q
pz60hYnf//q3d9M4cITQTxD7IXljqgFcSD1qCKFj6PMEL12Sc84eNoo/lbrKrviUPr11ENzY1dPb
lph3Gi0vjmMDJnktmTGBtJ9UKaV6CcGT2jOyn3aiFUFQQJ3oTCZ7CrEfo9UH9foRqDefaieQI2MB
SzINMrP02xizWYwZ/Opn8gjwJGr6mZTQkXsT01ijSOXwIoqlV05K5WJ8mRvCnJ6ROtS5ehyb+ceb
eVNB3XrD+UvvbEhNb/hjLUFLugUNMHS3CKrbfG2io+BbqvthmxaFe50UzJsS+saPXKKbdb9vflfl
xB8U1ejtszOMMv/e0sDYzUbXfFTFFGCH/icXftPdiPby0TcRtCfnPeCvlhbWGIOO/Zx9KIiVX8ZM
IKw+d0zJaC0SOeZmX13gr7do7YYublYYahXVqvLiXUQSphTr4AmIoyMERiO6TiSbgu5qbiN45aIj
htFx/gCiPUfdNE8MMbCfxRnTQq8mwbCUKS2IM6e1rJEG6gtFL1h2aY6lUbtM+a+LdBnRPE4aq4oL
UPHYPm0qWLpad74O/CApqMj0rQZzkcJ3SxkxWmdToGdl7eG4E5+Qe0dsom4qH3UQmviK9VD1aIFz
DamovBOUC8KjCnriPFVE0pkTMrOtagjyfhZgKqfmKc3MUJ8OfQVrrfD8YVLSKK3lVZ3lwHDni/uO
e+6DtyodGoF7rRTKg+KTmDVYAT1YXHF1mjl3IKmV9w74qseu2oP5O06bgYPfkeDUVMEngimQ34ey
hHXMJI068mM+g8pbxwPcgq3dbf2SHk0S6+fpTPaS8gCnB5U8CkgsHOwHe+r5l3z8flTPrhykq83Q
kFUBCxF67pIzIFetKQk8sf2E0/UhpwBj7bMW/hBNuX56cTES7/Fiau6PlHA5PY+AbPTNFlSVmW2L
sREUYVYr8wEhPh+6j20As7yoyiC/uqlnGYHKy718A/zhS40PvnuntjO5RIT3oRoVhKcLOsnwioaj
jhVKZ4NznayAjDtal80Aydo69hmPYmqONWb7pU+KJ9Rp6xzaSDw21sy0aJcHKA5MdvO+gEnDy1ZD
P/3rXp2Qz5Qs3dxzRySNMYE9EE7XTIU7biaYHMqMqfSZ3dEpscF4t/qRwNXKLVlqy4KURAyOk8+U
+Evxd9QAXejMOGZfYK32SZXnh7LcPYYnvO+AkxmOX+15CDW2OP42AveygwnqvGlLNArr9l6injgs
4AB9TBRFtd/qMEIYLMNS+z2xF3qPH6OLfU0x8agEV+MmHllW3oQrAvGo2r7DDun2HppvcZ/7Woqf
Ruj04yvSWxFckTWnZX+884k9V/6sEq4gljgruUWunuxQ/vvgEhAeIEK6c5xJCNnknsTXzx9iCATy
iVq03hNxI9VK6lHd7UW0v+Z6g4ytRuA7BbpEho/L2qorYb3G+18idlV07qSLBDlGEi3fTInGgroQ
NGjs5QjL0YogYWKhmxRorbBUCd2RokkXgRLWLzkpST2Bdupi+1bvH765/gSTEw8q7jL6JlKYfkxl
EpUzO3cOBckHUE2mKOvOeKo9l0vM/PQ130tRyyGX75SpNoqtg1moOwexV47YSTC3mf+8EC6lX3uE
+oDmtxKyIAGoV9v0PbtSADmAny1uvXfGVedDy0NMykPYFHXdbJW4Vt1Y7zFGwGQmndumkOOVMXK5
C6TYAk35bOlCkm1ShIOkmDQ0WWOm8JpIWE6M3EgpTS6C0a2YoSk0I84qecgy66Mz/a3WIIiJK75r
5HBefZqwqeojpAQuL3jn7Mh/aCTXF+o/ulmrIIvQkXFwbiXvEbkFpxlpk9SkhJelb5Pcfzi1BPvn
Fhpqg69TKIg+5bhnHhVpSAT3ksdCVGzemZfLcnXcqqWdK32IR0PkpiNaeX4DNTCIFrvkdsV5ITiH
SCHaC4sUtWVCzoB3KMDQCKMd4h6Utc4BYfje9TphS5VcDuqCh/lYa1wttgHLXZm4II4sxs8ZMoaY
J3VCf0kX2yFSXtEx44GzCfzZVj/E045im2SYpnBzlG4xOqSLsbmL68VDq677RvQkoQoP3Ch73oyj
9plLXqQsD1M3Rvk00v+DiruZ53tT8HMybmdKcpDqeUe/DHPpZSeBzXuSo4/ht1k1BaczVursihRa
O9Zbk2Gq3ptIdBH0M+iZwpyiy5cqaPV78qBn1Mkx9BV2wwhuLfqtthOBAglwRPWEQTmX29PosCwP
8e5kUluPcMWV/VjYCO4I6uhocO9J48NQ0U6cRJKCYwhFJp0PIYS+kWpQhEdT6/K8vghPsOwjnbP0
Rtf+VN2e46WljErbB82ap3hmDJZs9ORtGRHI+qHgXEg0LdRhXHbeOj1cqwd1bJcOS4cqrILQEfle
oElu7FqkDaB5iLrSED6TAKUzhdeSbMvsTin9Zh5jr0A+TqVbp4CATRPle3OibdQmOAJ0vKQ92ric
+tNg25B2o7h24utEnxPmXJF9UtH4pdoKrZLw4di0saBaIUDolFEYxewRtxiy7lUa5+dThN6+Q60G
IbQwj2uhfRyAANG9E9x7Ql8fAh+opoM4doVCixGMzNysQCrBF9H6FXPtXeeDDhE5kNZwQgedSoNw
UP2M8pZk48IS3TqxivE6p3KsBm5Ujvv46oL/O1uotNTCwMVyd7dC7x0F47K4LY0nhTnnXJYc8T2P
85WKt7xtxGvuOw2Aq2jZe8Ra6kSHVHAXZFtfDms8N0/3DpVfzTMl28M3hOvNN1LcM5oxhxnluZgD
30iPXsMAmYAqZU5MgztUofxOUkCAwwrdTLdIuh8PQef5+Zf8vtPloI6gpmG/oruqvRwE4R0duP0C
PlC0mH+8MWNd9eGfLqvxwDVPUZgIcFWsptUdBz+ris2toJc1taetUeEnSttqqi+V+4bV2ZXZKeVl
Uonb+BgzUPUh21nN8H9AAXhqroSYdjj46WntF0ryKm1wZ/jWWmSPhowCdryZNNG9RrabPWFYvBdb
nW/bSpmmnbxQyYDk34mkqyhFW2t/kosPv4QJq6Y8JBKomZrWMmXUp/oDw2sUK1iKf6hONOm0EQrh
5LtpdUEmiZmTugmudw05dAmJZNEkZKJqHaoSjjtHmzp8Fni3XkYkv82b8BZ4bHh0mF/KQy99Eu07
GvZTWI6DA33f7XINfO1SL4wCEdxijPNz+aXyRckBf09nvU/ztupoSS/fsdAntER7nSiZhr3Q0Odl
TmZ35J0z6CfdXRNw8IKJZ1hnn4EzF07ZK7pCc3ULMtMwMH8lcy1cng57p2QGXNlA2Ypl1wM6c+W0
qhh7GNSI4T8ZM1EQncvrjIs6XftmadwSgNjEceqTeTXJDP/b5TO4FQ3rwHsVDh312mdEfA9tO1a7
l8elQttvH6g62tsMIdlmioZ4QS1I+/rxTIDDYvlYwcLju2ifdJateJtypJ2o1jUKxW2jKBJyT+bs
O5cLED5chk/SKay0eNZGQ/z96jWbZH/D1rLshJWrzynRYwEQXt3RezVLjggr2egxBpEx8T86tAUU
v4p/XGADfX8AGV1DvostEMRSZq6z3xzIAqhxxGrQSP5DDBaqpiHfy0qTce363aUX0cAmPnYvfFuu
ZnNJXtFtckD58I/Lc5q6XkI2hcqtFkfL7asfNbTY5GDlym+lJOvXececF1JRjxbR1Mps6bxawJXU
WXztTliLpzHQ+zXL8QmST56iemms9Qk4BKuEGCGQVNY8RXYnN/5xrp5zPn1R0xrPnmlG4I2UljwN
/UsTUhalVpgUuqsO/LrDJ7EvucXHnaIrFO0JLC3Iea6yTmqxFYItTM8UOwD8aX5MaKFknRa6mneV
YmsoXscZaRlwJ0v31GSAZUpI6g9J7TLGnAuZIL+XU9EgtuX1Gr3Mgw7kInJIrddIp+WE8Bmlcff4
DV2Pe4frqnePfD8byTQgAB5nWKUWZNiBTWTQkeCq6zkIsD7g40q5P3S5t/ABPYC/fdxXGp3FU/Dl
/Vh/SnRaENP3afiV3aQIih9z9tihqszJvBpY3p/ryPLUV8xVG3BwjXC/tlu49VLwrZyhkWWJ02cG
vlBpoW5seuKPvlZasaEcWGudUO/Qq6GzRcDAVFMaqJryquV8P9Cm9BgmpPCcuVla8QUMpMIinX+6
XCNXLG127erz288N1vd/0M5IpiXapL+9RM/gFSudXuXuInRPx55aZRu9lHAG6sDNAPD/8uzGfU6O
p+o+w1jzKgSEXhjzD6x/crWYfzDhtPQY0rwxZ2xAQ1hqtiUe0X4+8feDzkYb5qDAFHT2HbVSx42R
IplplNDI77zTYp58TB9uDaboLnqJvu0e4fxkCkpwwiL0wZpMCcTP1VjsG3gtJ2k7E2+Qmdj5XQB5
O4Ognhxhab6q6Mj5GsjfUfNAhVX+AI86GQzGrv14SNMpBQoP8sAfvpkLAuavsyy6ymZNIKgsc3kQ
gA0MVxm17iLikoiWBYYnlxMpAk00XFWuukjHLM0uiGo2YpDGF05+EiEnefLwEUSJSCI2mtEO0Tl3
I/qeCC6qxoWcmEDHz1wsrTQrJBZSROBYJ21Ucvy2AXQ5YSFUG9P3jyRIYjvcwP6a6r0+7TjXcDeX
BZukGeDk+gFdHZYflJ9oDqSmF2P22N9sluI7NT4LQkAMDFn833lKd+aY00Zj4tm6V7fNM3q4ZbOG
QIz/xD0BU69t98uIjYx+0kdjLBUdMk63AVzbEQU+0aiePYUpTdUIHVrDznztfFaze9vhTrKION1h
GVempVYLn9qY9kD5XJbl2MB9TA8wD9UbSQZ5cw83XNa1QOQxjw5OeJU8eb6J1UTug5su9fda0YkY
2T0lO9uIXEaZpksdJKvBKv+Apm+Vl0p4kyoKzCw5pQ0ezjrca3pXtNnU4oh26bntT4COsQG0KOOI
wSKBTVNbmfzT0SDU+nw2sL9Rv8XtP3PQLnQF/S6iTk65rUyoE8p5tRg7USreAo/kHQTV5m+S9Q+1
PiHuYStiE+Y2ZYDnYyPJ5tLRHtBg1OiCybOusx/8BGnYY4xkvMLYskuElAiUgX32miDfY6nLq+b/
DSn/8dUKYi6y0fByE1a5d9Sbx7V8vFKVq0T7NG8GvT10nI/jM6zd+I2Zae/KiZ8yk50qaHneENeL
F1LPxtwrYREZ8q5Yl3EzJi5UiIhLmaXA88oexY+Sa4W2w+Z/mdkZK9qD0skoyiyMty4o9MJrXO/B
yq4yVul+8RQ0UJP0pixooy6cbGmulD/cd/txxlEL/50276hwgGmZblG3CPdLKPrR4rjEns5ielgX
ACoXZuzVgDI64tyLEQc/sjQ9yMWJRluGWqw7VB/ipVIkgLM6MjfsF/5/wcdxM7LO+840hYRuhndL
r4py6qiFzU/ZVxyRRXD8l8fNrvk8xKH805IYcZHx33k3VyOFTB/WATpi2xV3zLHuGvIhajkvAw7F
pVLbJLyBXbfyd+t1qEJqJ/ECp8uYT/9fzLC6ZqX9MEB2jTMCvsBeixu1Q5S3X3N/HCAFUPAADcgl
+Qmi8TEyAMBD/zCPwqw6YNpLlr4DdyvE1TngLeXYpqHlqdmyCcYeigKx6doLluSIbeqa1Qf6p9cC
gu+MKTgsnwg+7gsfJpkf58nmegUmtPoT92UypxQOqXtemla8e4tSEL1LPVyL12cy7o8UCwmCwDUv
PuMGsvou9jtIvbnF7AMCOm+z0czvEEPN04G/EnwvU9gAqmbV2UDICtgkmK5ZMHYKZmnut4Z99d6A
1B830Xvdc0QzWSh4kxEUeRxPy/nmkYXmz6tgSsNd3KpZIB9zrYKYM6sgKrDBF+oeOXmw+lWGwCXt
58xwEOQ6n+nQZ6Bqhvd4n699CLnNViqy41mXql5g1f+SLtSB5RQDcgsr3qjOA5qtNXsu74BWjcqK
3tmWjCFX3Y0asgQXkLDeZL1XBR7ehGW50AjGT2dJBtcvYfwQiASU+WYVMtB6Ofr3S5ksYXTkvs/e
OXQkcI43e1yoTc3orpLnTNVrj7uq+51vD2ChiCC5DN1kGDiXYf7hGi33v4vp3CEznpzUKOmAW+S7
IicC+w5KFMb7ibMBhmR2hZym6fN+30dW1nzei37Z0fwKu7MRgaN3p2n/5XpEYeIhsYtxVEgI6Bqs
6g+85aM85HaSxctChaEsn70DLe+NDeTV4VljsSSjHLxqnc7FVkg+8dEII/m1seIK/ib9nJHxcPvL
B0kyuQEoosZT22LWW5SP+EiselmGt1U6tr00Y4DtI4Yh95H2ZGSWRE4RkL8zj+FUI7X0nNASCkh7
ifAug4d54pCq5xx0GUPQy2Ad22cON5tB2cyO7WTyH5YusrOXBzRj6O1Uai2n+xOXQtM35d0MEilf
VX8GXjOmx+rULekL6P0OU5BW9jv3Ve9wWtnA0/GHdMFXnBVrjKN0U6746x8sTOeMQXCfcMpGVz63
eW8RvS1EV8dJB+0BbUr6V3t9mF+Xh2dZpvsP3kNUmFaJMUPr3wVOLKvXaRJRK98BRs89LX57zX92
naRuB9sHNVWU+EgWvQWmEALq5Yu6fCJVAUcQIjYOCfGCNh9AS6B7vugsns1g1Zof9R1DkKg8VzBV
Q9q0J8Dn3Z2Tz3UojbqukpjR9XnYWCi7I7MlaSOQS+wcgXGrikV5q3Mc3jytzOisxs7rwOKhMmJV
V6iv2lXtUBKogq0ikLiu4d1yywbTym5qCreRde3yn9TXLV0oa5CdoLXkZn3GhJNMh/SjUCfPbS7b
UZL2JhacALySrTOMUUnf46tufhfO5FVxGvWoyZqyKzXedpWu10F3WEgV68AbXEfG6Bkp6c3DQXY1
rUwpNeEuWoC0z5kGdi5/HfEqhJll8kHlkOknZnb0eLKDoB3DjqeStgLWsBvbT8unQGNiQaBASyNB
xO/NkiqEJjxIWUm0aU6naAiElkFOV+CoE3qA8ceAHgLZz3GKqVRxqIoW0U06r6NgDuOLkkMBnhSd
DlUR+FYFpUgg9U5tHlORZE8Nu4bcAgeN3LvSpfH0P4P7x0x8yGECLJWDQddvVY/t2MWRDazb/qtr
Fw2Cu0IPQjJ4R+IhzS2a39fCngOq+1YxpmZSNuZDRXBudjFrA4tBf9Ma8Jy4AswE/dE5E1lb6a9B
DuvA2YJMJTPtqeEsnGpekaa3YUgdnVpDkS4ydnjrVG7IrMFkTqJtx2lH/+SKFG+TdayqSQjxSwXV
698NqhsxraBknoIZ7AVw9g91cUVn65Yae50Tm9PU3FPuJ9G0Z8TeCqUh0wXum+aDlRJysjAylWqq
95Ev0KMY7/oIQlgjrCdxAlKCxx8OizsowwQAbSyHfpBZmhjlMBjsri018uY5rlI11v5gWha6t0Px
f8ZpzwJskUwNGKTv2DRF2dLqgWOGoJPLoHHAi/xihGZSgxvOals+pDFyLESJVfS4odv5dput+Weu
NjJ2FlYiXvqcH2+DiY7nGySblCAszSawrreGPHOJi10RLnAErYFShowm7HrDVi3jfckiRm51VtbN
6l8Q4UCElDn5AQQCF1NrWlbEX53GhOVbjFefG0MmwbrVznjpQWZNlDBi+L5I+XycTz37+mcNbt+D
gBQXQGaAGc2jcjLvA8qakPnZ4PbSCORX++O2xPD9iHzZy13VxzyI6sVjH9RI3Js2C7N6N7/Z85PQ
zp83SfQ4Buh1R528TIlndrwqQF1QFyU0d/w/msSnmWkCkY3lQGGx0IQQZBlCAmn0/k8bjQwgMGwY
fzB3/iX4RQci5jm63X3mtyq0mCFLk2TiIGOcc3b9lbSm0V/bjcJ5pUNSun+oI1VV9M5NNbMlXmdY
4VDVrNDXexHJzX3/tTVDqU4nUspDij7c4DA+2G06gWJMS5g+v/FpQW3zZWXOQyeEjmktBwPiAyaN
ueV7dbRYwLCOFADoYACH6OvzJnUekYhmAhAkj2QYrZKf6a0VFQGNxRRDGKiXPqtANYW6/nqWkA7M
lLs1CWqDVfn2+yGzW5MtMEUJkkE5vzh1eIs3st2W1FPHdEoEYiZ6YL8j8hB2jVQk2qpQtZUaTU62
vTrZNz+um/eyuTcPHOZfBxIUBUx3xquLMP+CD4Sy+KC6IWY8H5o2bhT2Dl88+a02BLfrKBj6g33+
/yTxPzA363oRHxwaaVXQoHpo4YpQqwUlZnBFVhxJiYd2TFjcFT0GgIx8uMKgbzhr1njRey6IiCTO
CkA3at295LN3HkxV0dN33TXnA7x9eWUdChybXKPRjmTcv6+Yvdwg3FN9xdPooraJZxOZn/Ajk/Da
iF40mtpOpHvVaM4gEK7Uwpbel+aftpB5273dv5olHEauZ45jvB56xT71VG94GWaXrG8wV3iIGOsK
VBXhh9sWT+mu1z37RDQmI8iEz619O/znxlUd2RHgcw6jJ8ZWUO2Awv4MuFR8yCN+nguAwSsp4qut
3mo5C2hqhC1qho/HCT7cL8U8IzhsNgIPlyvNcD/fkKYX7okn/dnJLnol8pJvvyjpikN125TN2ocX
IT7OgcoAn8cA98iaIQbN23Y2DOjCprl3GaKuYM++nY46efWuBKyrnyKjl/va0foaQ1pMms86L5Ku
3Su6nfDygdHoBc5ZBtdV9ln0fGiwoRlnylJj8cHOJWZObyXaY29HG2EC3pnNownzev9FYigZ98+r
38Y8jrgs70Ag8L/8Ex9mx58eWZDqkynIeb2CCQsm1y40WO6NiB0ekAzLyB8o5sz/UkL4ibmzRwK0
VXDTNsYKuFV2kgWxdOSNxu4RRUz2yKJ6TQlFoYeH5UalIfVsrf/BRuifTsqL1A7qvaBuhFzI1IND
EdvWYP0l5kJKuWvusXv6yZmCE4XRJt8U89xkPefQahZmAbKm1m4vZk8tfA+GSt8pUVakS+Y4JRAp
KVjZ90qXJkK3EFfRHb8amNn7f8yk1E3W9cn9HIvQO6U7ycyDVYUeVc+1wi1TeVY/BMvHO8xX0ILG
qe70P2WSovgggr50IKuKIJzSx9Cq4nwsJXuLGm4udwtQYfVGINEOrBgkOSYEtGkRru7dYnhDc/LO
ZBntzTXgtw443NNlUeU6ohboUyzWNlbzJ/nrvCgQVdW4F8G0GLCy0XjQcZs+wiYqqGZcuhWG5Fcb
bhsro2ayiVLcvf+grCW3a5gOmSah5I5pS8EeVNTJ2ucsohtUgkuRK9GW6dTqFBR3ZDHRC/DvMwj8
B1A5hpW6E9R3PkNxfeXep4PPmaW3zjqrVIleuJIv4DmdAzeO/O4t6TuLBFtnrWI/hxdmNpCbNdwQ
6k1qeBTjW/4gI69S7J9/45EOGrnp6jqA1SWkr2BrZhynqfnYg/vs29cACl6M9dHwhT4R7nznOS0U
tTqMiegiXUhMcbe7SfoHv+/VtTr9yobcHNBG0SsPfiiHqaHZBgHmjXKVNQfJ90GTrfcsNsYD8kxW
aYnR5S782IiSc3EdNNgtnEL93cIhQMoscRdOLbH2tBempLwGrvsxgb4BQA+lo8CLpzjLO91YniYv
13TpEts8fllqbFY64nNAVDbMbPcS/+8piNAcXIfCzP7eGFh7pQGK1l9RQOx/mUnV9LO1Nh4OnWFr
SidnyZxa8zwme2G0XrSGbJNWX+aPIBv+xltPqAVrzPV9a4lp1FtX+UbbDCAh7i3ugyv/NBezNv0u
OPkrrqviwxbDkKTEjfC5PKoYyk9XkSv2QOfJZEJJNgQ7A+2m46uZ8RFq7kWwemcwVgSozqJKdfCl
v0nr7MdCjfhzGi9xERQub8V2LhdLyyA4qmVS/6aixx9dEjP89QqGcV8dZOi4O7iVUDh2fMG4Pqtn
QTk9JpRSmN2FSIcCVHbkQk6xvSlxQRbuLlQwz5ukvHKQuwQ21Wk5ZXZ2y7Z/lBy9WJN4aIgAUC+h
1kof1p/d+bGwNYCROU3k27i7+SUYw1jxUeUVnrx5NvV7U08CciqF850x+qs+zLahpQ929eLIFXWk
dY4PHq6Nyq/XGYSGsG4adEhp3W3TCfzNRgS/r+i4i3FLmwRQD7fee61FPJ3rLkpTUskjumPv+MJZ
1mP0AedrWeM+oouuMiTK5TydV2PSzACbGRpV98c1Trj0HDKRf2zQPZZA2WeC0tX3bVgmC2scUX52
Ai+qlacM7ch+AHGCers1RiRRhxJ+D8Swtxj850Og+BjX2FCbvuglg/RXMbi4z6JMTOqeR9ICTc1N
FcC+uDS1m9uJuXfpmK+xh7HL+Cir47jBU36Varjvl+ecG99iOCujijNRKtwwUqbFFVkmnS3jecVK
nSHZOolsX3le8xIKXjB8Ub7omcI2v5rtdGWSKV7gCEz27I2QPAPBeQUklX31eCnmUmZIxtQlDjx2
X5PgVYvB5pxiyG8JQqLnG+tyAZJMA6AT9siwbp3oDWFvf3BNZnRhxy3qWvZeXmCaB759LVsOP/tr
RmRMXkbOu23fFXNX/JxEMumkpIxbAChy033aJ/nq4miL9fb0X0v50C8aCqGeRVdh+qek/Ke2jhzh
5giWdrUw6GFCNVL6hHvnkcbze0gUKFmNXbBw6efNI2ICQXR6TgVb4nlm1CSdwdnNAB49WYrme2yH
5kFu+8JdTZHsnPdCpxcnsXhNJW1kOcsbIHNb9T4vQBRHo4n4KCMsxIB5bLO5c4OaE9c6+41zrwRR
NQ+6vQAB4VaarPJSwMOc1QbTojRCPuQD3jfhmhZs1GzUquTVE8lYkZotb0LsfOHt82kh8AesRAfB
uXrn8T5WXZzuXfE5btDPhaOhlDCVZ1dkoyEvZ9lY5DuEclS4IP9OxzZQ50qOackliwXSIHtqK0oR
rPZ1Vp5ExEPEeeWEUc3pbzIMuQ33fGmS0mFEBmblt/tNTxuvCOSHcJS/reQo39AsWh1LqsHqEEe5
PbigytfND2VxjjS7GcsRDjDiHesZ0N/UphMBM83VeBg2nDpF/rDIjxb83iL9+sBvo/+895Z6KHtd
MLRFgZJCxwv5SQOGJFyK/XUvgDOWJrTm9/Atr016r6xkkCvmq/mB4yPjo0Jio8NWxN5xppshjygE
M0pzEBpySIbsLi514w6Ww63biuFQzfb+nD6xokCI5mm1B4jA2BPc6EzB+5pj4mbg/+CUONqN7qFq
rzNqEfEimw0VZytFmXfi9hogTk84OtcZvEFVIQYw8SjpjpRDKbz6hoekJuAAfbQ3/ZX0K91IMeuQ
xTqvyygpDG2W5B8zVxLiBrRygfr33AVB6KAoWTV5JeKlSflwLrrrHcK3+NMkmf84FkzEzukfuXjt
pQp21y6o4ZPzCingNgQky2yM8Zmzj1M9TR3zG8cUrFz06HBj+lnUP5ngkRdTocziWD1RENoJ/xzW
f8QPxo8rkXkdJnnSRTuaUyyKwpnn3bdxCJ36axr8YPTBo8D3wLnHyPu2/MuPGtZLxKyddc1eV8+q
uPIXQWp1JZVcv7124FfuGfIwz6f92sjjZvBcszlGEjKw6/TWNKTuMMOBJtl+J5UN9Utf9My3TF6Y
H4B3zB6sMQoDuvkw7jPkGVXNZwGt3cKHbwiudI4waL1OyudfLJboIG+t415oKhvuPzc0rntdoaYA
1B2707ufuRG9hFQjkumnepbi7fMl8KLJN76q2+312aNR0F/eith6BgID4Ohfi9l5GS2LGCRDqIN8
3AEQHjqyNYBSO47vhxovPDgL+seW+ykQcBwykGqXjfvBMn5IrwHtHFNwelV7rWVNWvxNND2zdPC3
8SAeaHhNRCQsO/l5pTs5pO0o3wVofKFkXOmycHtZ7ZdzJUZLuorwoCTFtt0QBMQk6ghSCVkXqPfH
Bu65TBqj/ULO9xq6vWCDYJ0G4av5vIsGS3c5xBeHTJiwM4OkpqC0GI14K0KXPk8laVEiAGOjPAJC
m7ggC7ShEHxLoQL/S5IYT/u21HW4iHGwb1/AUsjRmYb9YT0l4zmYt3UkkHbbgMCFHVKh0O2r8uGE
ujnWgr2xbzhuIzGOPOCGzZmCI4TmCLfQzv3xhTVbKEqbA4LeJsZntJmibCPBLdjZxetgjXgC4N1l
GGVJQkQovjfsfObB8NQonvz46cxD7ulmYreYZVf8W16wDdGCnMfzWfLtkKj48Mwi049yOfOWXKGn
5YF2R4N6e6ANgcTxp6glJO3wko0QD5XshJ/Bdz4PGFBDlhUMbtJZY9Y0eZmuDavUKSkMRT+o6j9y
z2jDMBr73blyzAH9LSlTnXxAoS6d9hCq+lfjozSdAMLm8JVSzIe2TR+VTgaW3ORy1r4OLzKgzgX6
Vpaa4MdCDjrA/HzQKTim61a3wwo4klW09R0IqpD9cizJJl3av2gOrrxbJZDFHrcQ4BdI9kwUUfYH
iidLTdXt7zyBPcZQI//YuAU/ohq/CkyZD8rML8Fr5N05QVj0lcfSdvfGYUAAUJ6zG8UkIJdUKX/9
R18qICM6W7kvZuQN14oHpUa2oH9QLfCbJPdvljAfTn85SzJF1YnyfKPh82BqBgBcunUWuFoa5UiS
ZA5WIBggAbAxar2y07My9GLipMPDNfErKsNoKyCYjb7+lHA5HsmIS6l6cxzZLXWCXX9IFA3g7PFf
nnQqnSOFMhUjOAVbZ8/5ws42/ZOfkovQHVlZSG25KAgIHuVaVJm+Gfi6cTpkUTg52KjSQQAAoMUd
oHkI3sU+smqcAtwqH49mCbFHlcZerWtKYyJZQo/6KmGr3vyRPTFCHCIpEmUU4qXMKyGeF6BXbuME
7bAh0wV+NdGc2tO2jaDhjp37rvIyv+az1YngiehFwdWB6WnO3rr9bc8Ek1MS5btIPRjmc6ZaH9QV
AZ+0g6bIOpBpKLJwF9x+lg15S0X4HRg6aytL4KUOLs7qovNhGaB736u8eNY3O5k9xciteh8Tvi/2
7dr80CLRWvT2MnEHcZPNhhRhFyE9z62Q59lBbdO8PZOQVDkNF4m59y+fEm1eKOFBWzhI3pmdj7bP
V4PcGQ9wVy3xcuU6wqaUlw4u8i60cQV+8LhPWnSl4Xgvc5nVPnd6vl9oppUIFZVowyR5pbYXA6d3
OxGfN7vN6FMZDk3PSLz6pIEw5ynuZwJgTXsie27+/mQmakMAkDidAShQxJVT929GenDarYa/U5RT
5GzliIt1F7ILRVSEqgDryNe1DS+FmAGoWxgQKxJwnlKydTlEOZ0ksbiaI6li6Y7H/77U5yd+B6+V
1l7TW/SzNOseY6/SqTLbpC6rBd21dbNUXEF1rFH660/EI/Duzph1aOsx0xXI0dhaBrkjV6YXOoFH
z6lG/L+W1CoeyTyOT4l3PjU5CKe79xUhgqEGZf337Q8CECoWmo8YjNichQx7LB5WQn2V2xG07pXw
Na3jEwrnYE8UJ4STaWPEEycZKBAie44ageXpWC4f1k6Q3ptVUjhgaP6PcrVKBrUPLQP0oe0wKwXQ
jHNQn7oykOmxtragtst4WX3GE0kuNwoU7DCgdePoNdtRZJr9LgfohmgbFUSvWaEO5zYKhrsd9IZL
oki0aD6DFLY+f84nU1CtZJqm0vqaWnILWVhtlUPzk5oxONnxz9y90pixgdaVgrLCGbUAimhVdWQv
E/3PQwVxsW6or/zz8wX/5L1h9jYDeKVeNbEyTO14gtkYcE6bXQ1/sqqRebT4ds+PePnAzTs7RhvH
5g9YXGZaepKOXchMzN5msqx0SNCpN6yADpXHXY0RdP9/CTz2CdjkxZJsDsDuCjhFfFR7lJTl3M9G
oE8YCBAtn+Q/60Pl4tl5nx2QDTCYekiWZlGCSKFBMFkOYgmTPpmFTpgfew01KgVqmrM98PCXbrDk
Kcl5J1i2S1S4cFfJms2PaVCvCZXmA8XtjlwdKbCJgfQtRdlU44sKSsmuqx93Vkg6X5ps5tM9geNW
C1OON7qVhh6Wuu49eKjTSaOzCmNyfKk8txLfQ4ceb8vV1HdY3h2U6XpDDlpSqUpW/My/zZGiPa5L
XWVjSnMEru0GlwgESnvYBkH9rnIHT3ea7PqX07P6VZw9iuI/v+ajXGsL77Kfzt68U+US/6rHxiI6
LDJM/SctdQCNtlkFNYy8IX6Je0P8tuwErYe1UWCk8lqWXFJVpRz68miWtrYdt0pf2Lyjl08rMgTp
obGH2ab5zXNLd3rftIUYZgFl/9eG9QR2zl8MBeCtRwqqZ86RicQQ4uls5HHpiQU1lSo5fTJ/ui0O
cTTLitmDNa5UYgaF+N5BfmRcIG2gmJOUWm3/t8oHATvQvnB3Eq6GvkhIo2btQ7pki2ubPmujzTRY
IefpjOOW1LIpp26v042033M4c0gvSafeAvMnSdBtH797oR0xUa9B3/KlVvWGQWg6yq5Uu0+PGuva
YsjyMGQf+CkMmBWo6REcoLWmJPmHOdhsm9iUWAYbyemMXBynE5gnHGwhZ3iaKYocYpVDqIZsXYZu
RYFVfpipTtmUNCEgd1gZMFjSRKDmSAjBLmeoGgU6f+zsTFNzOrPkDMV65FGef6WckxQvpE+TRYZx
audpAus66Jv60GAyKfnNiEgXrLQm17IM4jMNMe5cX229aS/Mc4ybyiRFwIDkQgX3F8jOL3VKonBm
KXYSI2atqHPM4IHVUtw2/0twgy16Z/BSg86ApZVBcUTZ2P8k40p7HAqTU8hRvUIKfocAXJB3EdDJ
/TnGC5pFC+8tyoEqCSU1Oxv+0lbnzqY07yCUZKT5KHXpi+vfdUPdr9cvf+b7F1pd6khpzU5oM3Gh
goPZFt73lQm0cOgV5zSufYUJ2GL8a/dHEam52Wi6TbmpcmPQaoBziOG+wft8uoUGc788p3+2GKr0
J4sYDbPcuORIbREyYTULSCV/sf8AGlcsjP7dvFWaOq4zO9uwNO4T3mmYc8g+Qbs84XgH0kj59WML
KyJgjwsoaQ8I6sn+MHbtV1vAVN6xYemDrcJ8W3+2E3M+sxNhYaIf5VHDcla5PJAYSIsl0+LL0Uf/
dM/fDv/Wpjk15T5xclaslnegqRfVHITTeKBMQ6/Lvh7VE38jZvz0ehAfgpe5xYHwKRY8ZaBUZzzH
lpXXRuK74a4bKkA0ycNeW33w/SxpN52RzF5qDKiypHE+BGi88FSFi2SflJtrGV0nO8DUuWFaFWyB
7mBEzR1KSvTeqZiV0OGgZ9mlCP4g7kCyc7I2s5qRI1t8HtEr8j924e+AcRJOPS3pIJ29nRy8ljKh
jNL1OALhkkiul/2mlIzReb/jNXYz9FZlxefVKV5sDjzLKMU6VYPIkctpZA8uiHD+SZyj+p5DkWOy
BobWUa/HVswvl5uIWJ1jU83CqegT8TmOAVxiVQ6Atm4BrxmYemuRKMnBNTHATK0yMcWtjq5a1beP
nRvhCWFBMMScj2AVI0yuMnsj7oAwpS780W+1e4kSJcSIjAVeKNgt7dzZP/6U0gg93J1S9ME4HgZm
vWRIeU3oRoaYivjkprzI4/yfwWQdaNiotsBWtxjSwm5Zcp8kZOU8ynk5QfwGHla69K10R9dwOlPz
KKEFTNNn1YbN1pr4BeF7JV3EIHo0mWCZiuUaC1QdyoId7PjoxYI6G+e+Tw2Ik3BFLviOLYqxmHpr
0DCylN7jEuyYGqG7hPmuPfDmepK8XQo+rxWcbD1WgWS9HCj29gYbl8HaO58HZRiBJxuzXeMS7qBh
C2NUKD73l2T5kGJXzgCKhMVN2gDX9kNcVzHC9S8VVKFhydQYe7rMXpcQaVsoKH4GAMrByvlyKmkq
3sHxHcE+Q4qUBgtQuamMV0c6NYJwL5oFabXAZ+62TVgmhiBp1+dqFvQeeJny9wM6u684g8psxvAV
ODln/KiWrFYX+vYtNFJ5AuXJ44a4uwMW6KcKAQSVPLQKZVCUDcwG8mSh0h3XQ+6zgQbUPzPKyppx
M3hNtLYqcFac6BDkrudjFaC8mmkCY8FulUv4jQh/4qq1fxQFfDyYYge4O4kjdAupRBdos8Ses68M
RGqvRZaWDCnTxdahTD1DOUwf4UzcJbuOXTT0frmbb2ONvJld7ThY2oouBXigbrQ4Et+RkE/ij3+T
NfFHsckyRtPbnGUeVOfsSVZ77v2MTJ6uxO2Ui24DfvM1FcierxHKcnkDZ3hKAyguOFqWB53ftIGx
ufVlyYqAeZ7ID+qukPdXAEAp8TituVwRY94MLkLmtjWdZTC/fYiRcS2orMw4bBU+HyLlhG6Z9gWO
H3w1P6CgL/hbx+12/Wan0815p3lgUOm4WRKDFW7frszYLmRrsPTwB/JN/irKHIZdkQ==
`protect end_protected
| gpl-2.0 | 9fb45c6dd5613f25bebeb549b38a8172 | 0.942853 | 1.849047 | false | false | false | false |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/xbip_bram18k_v3_0/902b235a/hdl/xbip_bram18k_v3_0.vhd | 2 | 8,791 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ncUawuo3vR1ZycZF8xtqqfVI6gCrdI+PWd72xdzgvbKVjiUqedCWSUEBFuuQDLCwTlT4hYrqtcoA
k+jkF6hUqA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
N3KVU8m7dp9m/o5klJahn6JrAp4dPvJ5px8Qjfdd/9teg+MgeqRSyR4a+nedbYovR1iG1M+OV4GZ
eedyUHeQwlftb33WHTgiSQcQOeDYQHOhB1q+SjuhN26SLFWK3YFERu3kL1tM5w3W0nuFqj+bXHZu
R4gQdtVWH/+OjyCytQw=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ZuxsHcVs7eB3t+mMECRU+c4tWaV00xKC1y8JMSw6ZK4lGIrGd9iKbAKZ3Blwh1vsVCQb3NTC7N3r
Y605Rnu1VKPlFpM556/vIzoPVRgcSvlo0qBj3oTSzlA5eJk5FVF3mP4v0RD6iY8xceU38ESPNbz9
tslYUbhOJVSsY7yCjCM7p+456bByCG6ed5+0nGONoXPAT0zF3Hxdnq8qgQDMjEIvOsaFSADZUSxL
WwjD6WPmcry72t5+zgCtiIUOoGhbFWqTndKP66O5YJAWE6dVlP4zMLQZZAfmdfQyazOsgs1uciSH
+eAOcN/r5BkNmFBVWZOF8biq4mt3PmniNwcfbg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
ygy9fvZbqToh8lhxP+oGEoqQi72mLbOonZqXDBQOfdz3oQWE3Hi1Zc2hfB1uR17TPoqAq2eJIm6k
q8c0om7asQ06vgODSHayDyQ+hyxq53TnIlLVx1AtJPfm0kI21kep00Mfc/Dwi7Qyt/ia2tlS/tQw
4OktcMlj77AyGCR8zdc=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
mcqNli4YixoMqmYwzxOZ0byTQYAQvCZuCaZ7iJ4keY79GxqKVx5edvY5HqwqCRXfHCDzwy4qGKcN
pXmE+CGNG2mMTGEfU6W2QQ+HDW5dsb4d7quBuFh6+SnA7XZEst6UjKRr26YyBGTL5qgiRLyYbkFW
QKRK7TmdgdCAj37TPbTPR6zjrQ3PTlWUwzVToIPxndDd6Jgk0ZyBHqXveC/6PEihQuzGKgS5GKHX
85sYZQakcEpa7RtFdztUyxh1/Do/cjYhmERWgZJD9wSCPweFJCsvo6MP2JripEEkasaBYRqfxMPN
DPHGfcHemBvMggmA1I4jVeD0GpW65Lo9IxE2YQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4768)
`protect data_block
SzsPkdK/1I7crNTpc3RI4SlFdfDTvHkI9YdUtuGjuvthNHkbB0O41/ot4CgBke7A2quFEZYstPKr
6MuV/JZ5j+1RMNw8eLlIz1UbBFygHXbeTyAoBP6UXh48TAe+3D5L+/auSgirevMCE8g2JjLbmB7Q
fcBHvrbSIcOt13ahrGX4FmrDGpF4rrtZYU+hW1vMQvNSOlpoI3Ek9LPv7Le609r03/Gk/Je8wBdE
DKIMSylF5uIM8oH+tlC3CLmMydxc/g98hchIrm7YEdVgq4o8k0KHsGCsirVkD/UEDKmjo8pN8r00
ysj2yz8AqWFkqjbqVhHycznA6w9TQAmauXtFvmWRowVoqS59IyWpCuMMqX0BHYtgEaxrtk6RGm1j
PSGPlNzwVcpqST9V4SaWO8s+MMwem1/hsjxeNx5fngKytc4QrbFMm+U1JdDCLicUJ8NYAoMjruic
i7knXm6kbIu9h1hYkNjgx1p/3T4E6yKRw3GkAPm3NFTYdL4AqmZItKzN/zE4inC/qlcRbKmsCqgq
+42cBP+c6Bcs2nCke9IXUYLCAeQJoCOWyLuJ6FIFUpS1zBEV1l6Zz+xjmjqNffnUQUWHNDEIw3Sp
gwEE3vZK0bqnxP3g1rCAxzwukXO0aXFhEBsrESh1KNy4jAbeJVanMxx4OYoTS9FiJv/ENksYgQAP
3dIDn7GLTkZ95mDiu4a6Ajwa8lkKumB1uUjAwg3jOVRJhjYdPhxMurOzbRo06c8j8dLKXCtf+cQ2
FuPYfzuaXBIzck6ahWRIY2fdZx+5mvDNEqAQ3BhvhaYovQhAonaWKbZ34OGn/Y45df903ceqJs7x
um3cFuEUjWWIQUgLOKmQ/YH5QYPAGhz06c9MOwCDS0pZCHWQcKvcenrxCyF1MQksQ51U6TVvOt3H
mpxnyZPr0giKF/VDSbH8B6TK41nx0LmGyXoj4JhGWsJ360hiz7oLpeLgAfSCT7ClLVoV2Lrc3yjA
G34SeEqZDeiTVEdKtFmpkRcfXQjaKs+4byZi9r4bfjeb9RHaleS15hv0WE0AWggANpmdTeUgpm/H
0yLqNNryCBrWBP3/1WPRHZPiEgUNl5J/Lsg7QSNImaVNk4nuHK+Od3NecXE1SmZT+JYhRmPt+PaF
AXhHcMzZuV28TykQj/XXYGStDvbdU5VtTjHxFlBNjaa4reEzmzhh9FT77UvxxQxeiVTsTOstP788
JMSSvaCFcfBUnt2IQ4WAQff0DUEJgzUlT9BR4o8mzW6IuOX20QFtKGLRtO4BR76gQSOTrC1cQQW/
XOfqIgud2uZS0j/WN8fIRjgwP/jzzbjfekt3puw2V1wTit79d+jSsyu6c5KNBf5GH0mRXH9UCnsU
6yeuNZKkVLIcT8upizM39lpvJhN9NpkNKQdmCdP3MBw0fQjlfEPBiu0rPAnD+0cMRMobOkUmS1Er
bB81HzXhZFhGYHCrCIGJZegMeWEfOgv2eHQB9ID00lS+4xWa3oiKliCbvb6yPsr7K/YQDlmLj6Gl
p8CRspNnjSRAsYWaNy9YfNgorzR+bC1ymwF2H4f4p/PTeY/w/7IK5FEXv/bHlt/32v26nHRrf2n/
zZiDpYI3LDyAbZMV9QUvRpcDDpnk8r8O7CiQ0yJt3+EPXXtWnUELsh/bx6iRLeC6WIog7MN6mS+o
Jxrbs4fKJe6WLr/1x9LJRPvnWf7n5A9l6UPi35IKauOgc1bCT4QJ9Dm9arEfQbWicVCmVf1c5mX1
FvJAb6ceL+6ngf70zBMaUmE1kWUk8mP44s7Y6VZyCdmx3Cl1V8gtETy9/81bePHp+2vQTSCXUPfh
jscD1TCxxICI238mWBtoIrPs8SvmikOPRBQzVg7IPS5aOAzA8TEXFMCXdicQqNdAch+W1HMW/E5m
YwH05SDI9pq+Z+gkZQqVR85Jl15eSIFeEQRHe57LqkMogX/461jeW4yhXPL/U3zfYQFocfiLUOuD
of7RIZItTp6rgqpjSYlnnCqVJrOR0t+UlgvCEEk9ccl+X61uTtGbCaQzOXjCGw/vATgcWh0HtRrW
UHoxDCT6u4jRgWmOrv7+VEF4bfs1SbwShVRyrhHFDFMbaqQlqcoCkApAGB85/h2PnPqwETH0wOTp
bY6P6NDRqQbCj/HvxHBel+WGkLewhWfZR7hCf69lf3KUOkj5EUTHEC1abwW5WMGrEtcnz75KWv02
LabCUwardxDJ3Thj9sgRamy8NEDyyTmUOCeevRDRVekHc2aA0gRbhD+udJwRcPnGBqYt/pS6RR8l
hG19MSO8ig9RyED+GyWb5Bfq09MwZDiDyKCH0n1rtK3MsAV1pCEovLBm2ujJZzRCmPpCZfuM6EL9
bwb3DnQxK0VP9lxs1e9epLgkRiskWYLTO/eLuVMTrGqHlwD7z3Xf0Xc9dwZhhP2+SIQOJOCGar0p
8eKPlrcGzFoOfq2WyEMMLUPWwJwIoM4wnTONW32+tdrAKfgyu1e6tK2csp4EP/ygw54P/64kGzUH
SFjHw3dT8YEEXnWWmN1Mo7XvMbGzaU0l+pJOh+r6upYR1c4w2EF+V5LSddKRtb5aCVX8H4ZcrviK
zymaC7IOJ5cIaN8U16P3lPIYcOlBSNSUlHCXNO5Q3EEwM6cO/5xphJh9yBq0HAqsibpOre+uTVok
LxZc/6s+8+ncKKBhkWwzPfEh2Ru1lEZRuASOBWF7kc5H3rZbjmMnBi391fYn10jd2n40xgj7GY+6
0yXoMPFbKycSJwOa8noGkvcTwwCNoUq9vjr94/6wPwEYqE0FjzAFObBk1z80kg53QPrwO56n2iHb
bKSvrkJ7M2KPRZXQYceVwfeie743Q1FBwYKWO5IZkiR5fAZ6pHSmB3VNhvbH2nMZlVMTrAhqXeh0
cdt7T7n3aYGjfbwEvBhx6Tm2jUZpIoi4uu8okotH/LdhOotG8GoB6JJSZCy5oZM7ueBwqdoqV4kE
fDOfaNvXkVeyrLAMwfzf5Dtq5CXrBnakfMRKpn3tDhNXlJKqXwmi/wdgmg1iO3ooNd1mBYBFkIzc
W82EOSq2V5ZTtxZLhHMWYyepHi/bf+9Vy0C3mxuXZAteOBW96vdk4q7CukhYNOi0UQxObn5QsSCM
EGBpULRAC4fqoP3oOuKN/HsoI4l22rteK8Vks7WiijF+fiTUWWvH3FLGfiOqY3ZyA6Y8KYSpZCu5
l9pBS6xKV0m9d3cqM8Ln8OTyG4jijWGekoRTnOROMWMYHnv0SUc8i921m4yRIj1ECFUDLTIj1Bdz
0QdbTNitqUtAv2aXoZr75aeuvbgrdthkG11zl0Yu9rBl8wZkCQZjws7s09oYJ/ibQAj1HgzgM0qw
rHct/PkPVb5LY+49mvYMqNXQIo0ijmxmtYUzcDNN6JrJkEGYI52i3c+4zZWMAn53P/qtvumvJ57j
feMQJc1ftZ/rUn6VHn2uE30W7UiYLX2ZutsIAS3Fa1JK3AmdjWZJtYik2PHuAhJLEVg3v8493LSH
IQihS9Zy9VCO3z4vd7lceax1Gjkv1Lo3jab9MITC/TJeGe69XqRBPb7XjInlBu7FvC/ci12dXGDm
PtPirOrzn1amGr19/CTcx65Kxw0SOpW4GUgsRdN2gd5To1Ho8tGiE2JqhcPtFE83MkUzAiOyuOEK
uerzKaSVrbAoYKPPVG6xFxJjk0puxqVEmlTafxs7ZjHvdWf7g5QLvft/awnVz4G7NdkO3LDJ41nr
xN2si6RXiKQ4j75yJ3Nn26jNWiIJQMkHSNqVlyb8NXdwvEDK2e0BoaFSXX+3h50C/ZXuPA406XBK
3WdJ4W8XaCWAiDnrycPzKwFFOo3GgrkYh+eLZtTRTvs3VpmfU+9XfrWeazDe++DLQfZm7xoiY/4i
zDo7DQKh2o/djhd0UcEFjQCBuseRfRARZUzuRNyvxXeN7Z23LFS3OQR2efGhEK3OxjTEpBNMb/sj
KcMnnRkZfAOCriU1GHtfjt/MDNCBXvsc+MGexF8wXA9sPvHRE/ygEZ11V3AsXAnDjq3N9JoBLlfW
N0nCuv5hgLU2eeKWl51lYDLb141fqyTeoZK4n9Y5068i5iTugyutyg2/xqW/Q9NmaP+N1QdP4nBc
zgUWlcgYko88mvq9Uyg1sI6tz1Ln0k7q8F+gtjwPzgR5VA40TayZ2BKNB5FKSIijZA+9K4Vsgfvg
vGqQgXVEoGWcTPrvbmOOkZSfMj4tgpNaXbF51KPLfH//PMhK6VgBVSWOFxNTOjRwXC4x8zD9UYYT
sylCN0oZS5TUiQ3JnnlLKa5+fPyC5EVZFgO5RPdPZ5UhJkEvPbrGtsTNBKghWgLWPGmDl1OLqZx+
g+SN3GrW4POHYlIyMIjmGoOGQ8vDJ7WcEbElmvfqXUpWLa0XdV2ndYE/k7gA7o9q9tdQkCPwzTu8
3vXnH186ZBLw2rBspzje+tNWt13xye+fo/mKxP6jpk7SbctGtaaCuZ9xfZ6UzuEueEXJ3IeRywoS
CK6ilIBbuwGL8BWBBBkwnDo+RC0ENL+7qXrwSzMyrrKS9iPHaG3RFC5869cAA4IF2IYNRAC/fmSA
TEen26NbvAFn6iPk8oHq0SauJJ6qSdK24XczHhe2Z7sO4SCWQMgdRhituuleK/kA3d+8BB6tEh9S
P5+kv+vh08bWEzXYUwRT4CILLva12hzDZmqGKM7DDOoW2nVNZ5uVFOCZro9VkLrFSW+7tiDCcfhR
FYWuGBErrlPd88TsVW3/VthYcixuTJ+Da4Nzi/YkPCjgYE/0JBhnzLLm/XEaEj4T2aUdnlzxt1MT
OyojtsS9AvyKCENTf/BbJ7487EuSsiXt2kjSQbRfUoaR6BJTH07LV/tljgmerJrAGx/pEznd0WOm
Wd1IAZR7Vb3NzjqLOdYOa3vvNoaFRpiEi/jx2SClO4rER8oeFWyoFVIdox1VW7rcM6pGfVkP3buU
riu627i7TNpYySca+q6jJZ/CiTXgQ4jHaBQDdIHpDi25kaPL7WUH/zmgMEiL/8NqZIC2SVytncsN
E92EERDjqdD+l/M/kusV/CKkoUWFQyL3sVLdkrFHq+JtAlRFZbqifh/7ogv0pYB+igyuKYY1e3fQ
0vUcCqw7WWQ7ddkROIvevCQ1P7JvfVXNhRSLl82N7xQYqcxekRXs6HllJThZfUiIQGPVvOkOpvZO
pwyAlFDmF5sq5ScrIrMqIRqf+p3yjS9mTeLonlTC1NuXLcgLVj1ncI86sFnSaw5gYvov1uO3IuUg
/d1PNg2cpKvBTb78VP0Ez/z+AnhkpMTWJekkFU9SU7Y4D25ID1CfkS9K+WkQAtveyhQaWcUXae8V
8VPMlG59RxiD5wGPDE3oZDqRoICa7ygJC0vzM9/2XLKprDc5dVxTVEOqGraM2hLCWep50vNZCv63
IMooVyubohxpD1N7ATy5jABldkrFL5hGH5mnjgSLMZ/Ea/7wOsoIyDHrJnbqsMAuO6Fe8U0byK6K
FyddyPN0QSuXVrm8oLFZCOU/0pXlkvHvANx/MzSaGOj+/5mtfTbuSYB68pyJevseyCNDKd3939k5
6/mNJOm3GGhQIlT8sMldxlBjo3OmMbgsBWhfB27LgXi6aFClULENSLmCLWyBMa3UTPtRsFJwLZKT
kRtVk454OqAmLW8PenhlUJsNdsmO3jFR3QAukXgzK+xoADUE+vXd81z0rgzxI/Y3MXS4ELlYMga8
7B5wnd4zGeXFOLMWg/VhPYOUws76Zbg02nodUyo8JGMjeo2dc0IAtGK1AdrwP8xXchVeMFLvY4Yj
6VxmhtxiGJw27H8exS7EbtUzpP8KjiJmePKorZEuMSOmuKa1FqB8mOL6PqA/IO3VANQGZM+AkTA2
i8QsBmVRr0FbZyQsitzhyO1c/GqPyBUBKPbg4jtxLzEJlcdv7E3IR3/x7dlmdbu20+H+Iab5mVo8
Qg2JfT8P6mPhPMLN9FwW0rzN0kK9hknU+kxsorpBcz1+r8hUIuHDK+c9X5/2H1sNd7PXgJEk36Js
DhIyEkab+96cM2/w5F3zfg8ZWt/OsTOsbZBWFqA2I1tH2CXw6/H9lR08WAjToLu9fiCSJyJ7Az6D
1TNnRsOK7cjVA+4HGxw9yw9pFs1AsV4Mna2F3av7e/mKsuFLQnuFdEN2yLIPhs2BnUWfzcxA7FaW
WvbCFtHLMuAwN0179Td8VScY+m6euXi0KQAes4YMdp2mbtr8wxdqzNh2UXPDfcU2pArGxokjywaT
Mv/5tiHNbuzV6pYOtme5Cz1SapOozbODOcjwZ1n6i/GfVr3ZrtV0hIBZXiXnKlv5mK7NvyW8GiSX
t7tOeRpJg8Mtyt2gW/7pxg2J+Rr+ZSK+XwXhwfYbcMfpZsQihw==
`protect end_protected
| mit | fb1216be2936dd1646989d0840299af9 | 0.920828 | 1.919013 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/keyboard/ps2.vhd | 1 | 4,601 | -- #####################################################################################
--
-- #### #### #####
-- ## ## ##
-- ## ## ##### ## ## ##### ## ###### ##### ##### ##### ## ##
-- ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ##
-- ## ## ## ## ## ## ## ## ##### ## ## ## ## ## ## ## ##
-- ## ## ## ## ## ## ###### ## ###### ###### ## ## ######
-- ## ## ## ## ## ## ## ## ## ## ## ## ##
-- ## ## ## ## ## ### ## ## ## ## ## ## ## ## ## ## ## ## ##
-- #### ######## ##### # ##### ##### ## ##### ##### ##### #####
--
-- #####################################################################################
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ps2 is
generic (FilterSize : positive := 3);
port(
CLK : in std_logic;
RESET : in std_logic;
PS2_CLK : in std_logic;
PS2_DATA : in std_logic;
CODE : out std_logic_vector(7 downto 0);
DONE : out std_logic;
ERROR : out std_logic );
end ps2;
architecture rtl of ps2 is
signal Filter : unsigned(FilterSize-1 downto 0);
signal Filter_High : unsigned(FilterSize-1 downto 0);
signal Filter_Low : unsigned(FilterSize-1 downto 0);
signal PS2_CLK_LOCK : std_logic;
signal PS2_CLK_TICK : std_logic;
signal shift_state : unsigned(3 downto 0);
signal CODE_TEMP : std_logic_vector(7 downto 0);
signal parity : std_logic;
begin
Filter_High <= (others=>'1');
Filter_Low <= (others=>'0');
clockfilter : process (CLK) -- PS2 Clock Filter
begin
if rising_edge(CLK) then
if RESET = '1' then
Filter <= (others=>'0');
PS2_CLK_LOCK <= '0';
PS2_CLK_TICK <= '1';
else
PS2_CLK_TICK <= '1';
if PS2_CLK = '0' then
if Filter /= Filter_High then
Filter <= Filter + 1;
else
PS2_CLK_LOCK <= '1';
if PS2_CLK_LOCK = '0' then
PS2_CLK_TICK <= '0';
end if;
end if;
else
if Filter /= Filter_Low then
Filter <= Filter - 1;
else
PS2_CLK_LOCK <= '0';
end if;
end if;
end if;
end if;
end process;
shiftregister : process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
shift_state <= "0000";
CODE_TEMP <= "00000000";
DONE <= '0';
ERROR <= '0';
else
DONE <= '0';
ERROR <= '0';
if PS2_CLK_TICK = '0' then -- PS2 Clock Detected
case to_integer(shift_state) is
when 0 => -- start bit
if PS2_DATA = '0' then
shift_state <= "0001";
parity <= '1';
else
shift_state <= "0000"; -- error
ERROR <= '1';
end if;
when 1 to 8 => -- data bits
CODE_TEMP(to_integer(shift_state-1)) <= PS2_DATA;
shift_state <= shift_state + 1;
parity <= parity xor PS2_DATA;
when 9 => -- parity bit
if parity = PS2_DATA then
shift_state <= shift_state + 1;
else
shift_state <= "0000"; -- error
ERROR <= '1';
end if;
when 10 => -- stop bit
if PS2_DATA = '1' then
DONE <= '1';
CODE <= CODE_TEMP;
shift_state <= "0000";
else
shift_state <= "0000"; -- error
ERROR <= '1';
end if;
when others => null;
end case;
end if;
end if;
end if;
end process;
end rtl;
| gpl-3.0 | 987595206caa6dea845eb421bf733fbe | 0.309498 | 4.39446 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/antic_counter.vhdl | 1 | 1,698 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Counter where only some bits are incremented - done in antic to save using larger adders I guess
ENTITY antic_counter IS
generic
(
STORE_WIDTH : natural := 1;
COUNT_WIDTH : natural := 1
);
PORT
(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
increment : in std_logic;
load : IN STD_LOGIC;
load_value : in std_logic_vector(STORE_WIDTH-1 downto 0);
current_value : out std_logic_vector(STORE_WIDTH-1 downto 0)
);
END antic_counter;
ARCHITECTURE vhdl OF antic_counter IS
signal value_next : std_logic_vector(STORE_WIDTH-1 downto 0);
signal value_reg : std_logic_vector(STORE_WIDTH-1 downto 0);
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
value_reg <= (others=>'0');
elsif (clk'event and clk='1') then
value_reg <= value_next;
end if;
end process;
-- next state
process(increment, value_reg, load, load_value)
begin
value_next <= value_reg;
if (increment = '1') then
value_next <= value_reg(STORE_WIDTH-1 downto COUNT_WIDTH)&std_logic_vector(unsigned(value_reg(COUNT_WIDTH-1 downto 0)) + 1);
end if;
if (load = '1') then
value_next <= load_value;
end if;
end process;
-- output
current_value <= value_reg;
END vhdl;
| gpl-3.0 | aa46e3dae36a13dce938dc75ede433a9 | 0.63192 | 3.290698 | false | false | false | false |
APastorG/APG | complex_const_multiplier/complex_const_mult.vhd | 1 | 8,014 |
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Xilinx's Vivado
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.common_pkg.all;
use work.common_data_types_pkg.all;
use work.fixed_generic_pkg.all;
use work.fixed_float_types.all;
use work.complex_const_mult_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity complex_const_mult is
generic(
UNSIGNED_2COMP_opt : boolean := false; --default
SPEED_opt : T_speed := t_exc; --exception: value not set
ROUND_STYLE_opt : T_round_style := fixed_truncate; --default
ROUND_TO_BIT_opt : integer_exc := integer'low; --exception: value not set
MAX_ERROR_PCT_opt : real_exc := real'low; --exception: value not set
MIN_OUTPUT_BIT : integer := integer'low; --exception: value not set
MAX_OUTPUT_BIT : integer := integer'low; --exception: value not set
MULTIPLICAND_REAL : real; --compulsory
MULTIPLICAND_IMAG : real --compulsory
);
port(
input_real : in std_ulogic_vector;
input_imag : in std_ulogic_vector;
clk : in std_ulogic;
valid_input : in std_ulogic;
output_real : out std_ulogic_vector;
output_imag : out std_ulogic_vector;
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture complex_const_mult_1 of complex_const_mult is
--assumed that both real and imag inputs have the same size
constant NORM_IN_HIGH : integer := input_real'high - SULV_NEW_ZERO;
constant NORM_IN_LOW : integer := input_real'low - SULV_NEW_ZERO;
--constant CHECKS : integer := real_const_mult_CHECKS(input'high,
-- input'low,
-- UNSIGNED_2COMP_opt,
-- ROUND_TO_BIT_opt,
-- MAX_ERROR_PCT_opt,
-- MULTIPLICANDS);
constant NORM_OUT_HIGH : integer := complex_const_mult_OH(ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
MAX_OUTPUT_BIT,
(1 => MULTIPLICAND_REAL,
2 => MULTIPLICAND_IMAG),
NORM_IN_HIGH,
NORM_IN_LOW,
not UNSIGNED_2COMP_opt);
constant NORM_OUT_LOW : integer := complex_const_mult_OL(ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
MIN_OUTPUT_BIT,
(1 => MULTIPLICAND_REAL,
2 => MULTIPLICAND_IMAG),
NORM_IN_LOW,
not UNSIGNED_2COMP_opt);
constant OUT_HIGH : natural := NORM_OUT_HIGH + SULV_NEW_ZERO;
constant OUT_LOW : natural := NORM_OUT_LOW + SULV_NEW_ZERO;
signal aux_input_real_s : u_sfixed(NORM_IN_HIGH downto NORM_IN_LOW);
signal aux_input_imag_s : u_sfixed(NORM_IN_HIGH downto NORM_IN_LOW);
signal aux_output_real_s : u_sfixed(NORM_OUT_HIGH downto NORM_OUT_LOW);
signal aux_output_imag_s : u_sfixed(NORM_OUT_HIGH downto NORM_OUT_LOW);
signal aux_input_real_u : u_ufixed(NORM_IN_HIGH downto NORM_IN_LOW);
signal aux_input_imag_u : u_ufixed(NORM_IN_HIGH downto NORM_IN_LOW);
signal aux_output_real_u : u_ufixed(NORM_OUT_HIGH downto NORM_OUT_LOW);
signal aux_output_imag_u : u_ufixed(NORM_OUT_HIGH downto NORM_OUT_LOW);
/*================================================================================================*/
/*================================================================================================*/
begin
generate_real_const_mult:
if UNSIGNED_2COMP_opt generate
begin
--aux_input_real_u <= to_ufixed(input_real, aux_input_real_u);
--aux_input_imag_u <= to_ufixed(input_imag, aux_input_imag_u);
--complex_const_mult_u_1:
--entity work.complex_const_mult_u
-- generic map(
-- SPEED_opt => SPEED_opt,
-- ROUND_STYLE_opt => ROUND_STYLE_opt,
-- ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
-- MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
-- MULTIPLICAND_REAL => MULTIPLICAND_REAL,
-- MULTIPLICAND_IMAG => MULTIPLICAND_IMAG
-- )
-- port map(
-- input_real => aux_input_real_u,
-- input_imag => aux_input_imag_u,
-- clk => clk,
-- valid_input => valid_input,
-- output_real => aux_output_real_u,
-- output_imag => aux_output_imag_u,
-- valid_output => valid_output
-- );
--output_real <= to_std_ulogic_vector(aux_output_real_u, output_real);
--output_imag <= to_std_ulogic_vector(aux_output_imag_u, output_imag);
end;
else generate
begin
aux_input_real_s <= to_sfixed(input_real, aux_input_real_s);
aux_input_imag_s <= to_sfixed(input_imag, aux_input_imag_s);
complex_const_mult_s_1:
entity work.complex_const_mult_s
generic map(
SPEED_opt => SPEED_opt,
ROUND_STYLE_opt => ROUND_STYLE_opt,
ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
MIN_OUTPUT_BIT => MIN_OUTPUT_BIT,
MULTIPLICAND_REAL => MULTIPLICAND_REAL,
MULTIPLICAND_IMAG => MULTIPLICAND_IMAG
)
port map(
input_real => aux_input_real_s,
input_imag => aux_input_imag_s,
clk => clk,
valid_input => valid_input,
output_real => aux_output_real_s,
output_imag => aux_output_imag_s,
valid_output => valid_output
);
output_real <= to_std_ulogic_vector(aux_output_real_s);
output_imag <= to_std_ulogic_vector(aux_output_imag_s);
end;
end generate;
end architecture; | mit | 36ca1b29332409b60a5397f1af872c73 | 0.415915 | 4.334601 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_06500_good.vhd | 1 | 3,437 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-09 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_06500_good.vhd
-- File Creation date : 2015-04-09
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Counters end of counting: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_06500_good is
port (
i_Clock : in std_logic; -- Main clock signal
i_Reset_n : in std_logic; -- Main reset signal
i_Enable : in std_logic; -- Enables the counter
i_Length : in std_logic_vector(3 downto 0); -- Unsigned Value for Counter Period
o_Count : out std_logic_vector(3 downto 0) -- Counter (unsigned value)
);
end STD_06500_good;
--CODE
architecture Behavioral of STD_06500_good is
signal Count : unsigned(3 downto 0); -- Counter output signal (unsigned converted)
signal Count_Length : unsigned(3 downto 0); -- Length input signal (unsigned converted)
begin
Count_Length <= unsigned(i_Length);
-- Will count undefinitely from 0 to i_Length while i_Enable is asserted
P_Count : process(i_Reset_n, i_Clock)
begin
if (i_Reset_n = '0') then
Count <= (others => '0');
elsif (rising_edge(i_Clock)) then
if (Count >= Count_Length) then -- Counter restarts from 0
Count <= (others => '0');
elsif (i_Enable = '1') then -- Increment counter value
Count <= Count + 1;
end if;
end if;
end process;
o_Count <= std_logic_vector(Count);
end Behavioral;
--CODE
| gpl-3.0 | f88cbf233bb9695d8403e0b224201fce | 0.509165 | 4.522368 | false | false | false | false |
sonologic/gmzpu | vhdl/testbenches/zpu_wishbone_WBOPRT08.vhdl | 1 | 5,715 | ------------------------------------------------------------------------------
---- ----
---- Tewb_stbench for the ZPU Wishbone bridge ----
---- ----
---- Description: ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Koen Martens, gmc sonologic.nl ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c)
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit:
---- File name:
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA:
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: N/A ----
---- Simulation tools:
---- Text editor:
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library zpu;
use zpu.wishbone.all;
library wb_slaves;
use wb_slaves.tutorial.all;
entity zpu_wishbone_WBOPRT08_tb is
end entity zpu_wishbone_WBOPRT08_tb;
architecture Behave of zpu_wishbone_WBOPRT08_tb is
constant DATA_WIDTH : natural:=8; -- 32 bits data path
constant ADR_MSB : natural:=31;
constant ADR_LSB : natural:=2;
constant D_CARE_VAL : std_logic:='0'; -- Fill value
constant CLK_FREQ : positive:=50; -- 50 MHz clock
constant CLK_S_PER : time:=1 us/(2.0*real(CLK_FREQ)); -- Clock semi period
-- tewb_stbench
signal break : std_logic:='0';
signal gpio : std_logic_vector(7 downto 0);
--
signal clk : std_logic;
signal dat_i : std_logic_vector(DATA_WIDTH-1 downto 0);
signal dat_o : std_logic_vector(DATA_WIDTH-1 downto 0);
signal rst : std_logic;
-- data tagging
signal tgd_i : std_logic_vector(DATA_WIDTH-1 downto 0);
signal tgd_o : std_logic_vector(DATA_WIDTH-1 downto 0);
-- MASTER signals
signal wb_ack : std_logic;
signal adr_o : std_logic_vector(ADR_MSB downto ADR_LSB);
signal cyc_o : std_logic;
signal stall_i : std_logic;
signal err_i : std_logic;
signal lock_o : std_logic;
signal rty_i : std_logic;
signal sel_o : std_logic_vector(DATA_WIDTH-1 downto 0);
signal wb_stb : std_logic;
signal tga_o : std_logic_vector(ADR_MSB downto ADR_LSB);
signal tgc_o : std_logic_vector(DATA_WIDTH-1 downto 0); -- size correct?
signal wb_we : std_logic;
begin
wb_br : zpu_wishbone_bridge
generic map(
DATA_WIDTH => DATA_WIDTH,
ADR_MSB => ADR_MSB,
ADR_LSB => ADR_LSB
)
port map(
clk_i => clk,
dat_i => dat_i,
dat_o => dat_o,
rst_i => rst,
tgd_i => tgd_i,
tgd_o => tgd_o,
ack_i => wb_ack,
cyc_o => cyc_o,
stall_i => stall_i,
err_i => err_i,
lock_o => lock_o,
rty_i => rty_i,
sel_o => sel_o,
stb_o => wb_stb,
tga_o => tga_o,
tgc_o => tgc_o,
we_o => wb_we
);
wb_slave : WBOPRT08
port map(
-- wishbone bus
ACK_O => wb_ack,
CLK_I => clk,
DAT_I => dat_i,
DAT_O => dat_o,
RST_I => rst,
STB_I => wb_stb,
WE_I => wb_we,
-- output port
PRT_O => gpio
);
do_clock:
process
begin
clk <= '0';
wait for CLK_S_PER;
clk <= '1';
wait for CLK_S_PER;
if break='1' then
-- print("* Break asserted, end of test");
wait;
end if;
end process do_clock;
do_reset:
process
begin
wait until rising_edge(clk);
rst <= '0';
wait for 9.2345 us;
rst <= '1';
wait for 9.395 us;
rst <= '0';
end process do_reset;
end architecture Behave; -- Entity: zpu_wishbone_WBOPRT08_tb
| bsd-3-clause | 3c08d2e4f9596357601aa3724cc81344 | 0.338758 | 4.71924 | false | false | false | false |
APastorG/APG | general/tb_pkg.vhd | 1 | 6,675 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Vivado by Xilinx
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This package contains functions and utilities that are used in testbenches
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.common_pkg.all;
use work.fixed_generic_pkg.all;
use work.common_data_types_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
package tb_pkg is
function exception_value(
arg : positive_exc)
return integer;
function exception_value(
arg : positive_exc)
return positive_exc;
function exception_value(
arg : natural_exc)
return integer;
function exception_value(
arg : natural_exc)
return natural_exc;
function exception_value(
arg : integer_exc)
return integer_exc;
function exception_value(
arg : real_exc)
return real_exc;
function exception_value(
arg : boolean_exc)
return boolean_exc;
----------------------------------------------------------------------------------------------------
function value_used(
arg : positive_exc_tb)
return positive_exc;
function value_used(
arg : natural_exc_tb)
return natural_exc;
function value_used(
arg : integer_exc_tb)
return integer_exc;
function value_used(
arg : real_exc_tb)
return real_exc;
function value_used(
arg : boolean_exc_tb)
return boolean_exc;
function value_used(
arg : T_speed_tb)
return T_speed;
----------------------------------------------------------------------------------------------------
function value_used(
arg : boolean_tb;
default_value : boolean)
return boolean;
function value_used(
arg : integer_tb;
default_value : integer)
return integer;
function value_used(
arg : real_tb;
default_value : real)
return real;
function value_used(
arg : T_round_style_tb;
default_value : T_round_style)
return T_round_style;
end package;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
Package body tb_pkg is
function exception_value(
arg : positive_exc)
return integer is
begin
return integer(arg'subtype'low);
end function;
function exception_value(
arg : positive_exc)
return positive_exc is
begin
return arg'subtype'low;
end function;
function exception_value(
arg : natural_exc)
return integer is
begin
return integer(arg'subtype'low);
end function;
function exception_value(
arg : natural_exc)
return natural_exc is
begin
return arg'subtype'low;
end function;
function exception_value(
arg : integer_exc)
return integer_exc is
begin
return arg'subtype'low;
end function;
function exception_value(
arg : real_exc)
return real_exc is
begin
return arg'subtype'low;
end function;
function exception_value(
arg : boolean_exc)
return boolean_exc is
begin
return arg'subtype'low;
end function;
----------------------------------------------------------------------------------------------------
function value_used(
arg : positive_exc_tb)
return positive_exc is
begin
if arg.is_defined then
return arg.value;
else
return exception_value(arg.value);
end if;
end function;
function value_used(
arg : natural_exc_tb)
return natural_exc is
begin
if arg.is_defined then
return arg.value;
else
return exception_value(arg.value);
end if;
end function;
function value_used(
arg : integer_exc_tb)
return integer_exc is
begin
if arg.is_defined then
return arg.value;
else
return exception_value(arg.value);
end if;
end function;
function value_used(
arg : real_exc_tb)
return real_exc is
begin
if arg.is_defined then
return arg.value;
else
return exception_value(arg.value);
end if;
end function;
function value_used(
arg : boolean_exc_tb)
return boolean_exc is
begin
if arg.is_defined then
return arg.value;
else
return exception_value(arg.value);
end if;
end function;
function value_used(
arg : T_speed_tb)
return T_speed is
begin
if arg.is_defined then
return arg.value;
else
return t_exc;
end if;
end function;
----------------------------------------------------------------------------------------------------
function value_used(
arg : boolean_tb;
default_value : boolean)
return boolean is
begin
if arg.is_defined then
return arg.value;
else
return default_value;
end if;
end function;
function value_used(
arg : integer_tb;
default_value : integer)
return integer is
begin
if arg.is_defined then
return arg.value;
else
return default_value;
end if;
end function;
function value_used(
arg : real_tb;
default_value : real)
return real is
begin
if arg.is_defined then
return arg.value;
else
return default_value;
end if;
end function;
function value_used(
arg : T_round_style_tb;
default_value : T_round_style)
return T_round_style is
begin
if arg.is_defined then
return arg.value;
else
return default_value;
end if;
end function;
end package body; | mit | b77dcf92e17d1f63f867390df1525f9a | 0.494052 | 4.542408 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/pokey_poly_4.vhdl | 1 | 1,272 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY pokey_poly_4 IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INIT : IN STD_LOGIC;
BIT_OUT : OUT STD_LOGIC
);
END pokey_poly_4;
ARCHITECTURE vhdl OF pokey_poly_4 IS
signal shift_reg: std_logic_vector(3 downto 0);
signal shift_next: std_logic_vector(3 downto 0);
BEGIN
-- register
process(clk, reset_n)
begin
if (reset_n = '0') then
shift_reg <= "1010";
elsif (clk'event and clk='1') then
shift_reg <= shift_next;
end if;
end process;
-- next state
process(shift_reg,enable,init)
begin
shift_next <= shift_reg;
if (enable = '1') then
shift_next <= ((shift_reg(1) xnor shift_reg(0)) and not(init))&shift_reg(3 downto 1);
end if;
end process;
-- output
bit_out <= not(shift_reg(0));
END vhdl;
| gpl-3.0 | 898a37e9f29b1ca0574c0e97432c93e8 | 0.597484 | 3.18797 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/service/src/clock/clock.vhd | 1 | 6,679 | -- file: clock.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.000______0.000______50.0______200.000____150.000
-- CLK_OUT2____25.000______0.000______50.0______300.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________50____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clock is
port
(-- Clock in ports
CLK50 : in std_logic;
-- Clock out ports
CLK : out std_logic;
VGA_CLK : out std_logic;
-- Status and control signals
LOCKED : out std_logic
);
end clock;
architecture xilinx of clock is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clock,clk_wiz_v3_3,{component_name=clock,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=2,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clk_out1_internal : std_logic;
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkdv : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK50);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => open,
CLKFX180 => open,
CLKDV => clkdv,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
LOCKED <= locked_internal;
-- Output buffering
-------------------------------------
clkfb <= clk_out1_internal;
clkout1_buf : BUFG
port map
(O => clk_out1_internal,
I => clk0);
CLK <= clk_out1_internal;
clkout2_buf : BUFG
port map
(O => VGA_CLK,
I => clkdv);
end xilinx;
| gpl-3.0 | 2dc27cd43f24bf9c40fa7986295082db | 0.555622 | 4.219204 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_04000_good.vhd | 1 | 4,946 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1.1
-- Version history :
-- V1 : 2015-04-13 : Mickael Carl (CNES): Creation
-- V1.1 : 2016-05-03 : F.Manni (CNES) : add initialization trough reset for Raz, enable and Count_Length
-------------------------------------------------------------------------------------------------
-- File name : STD_04000_good.vhd
-- File Creation date : 2015-04-13
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: State machine case enumeration completion: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_04000_good is
port (
i_Clock : in std_logic; -- Clock input
i_Reset_n : in std_logic; -- Reset input
i_Start : in std_logic; -- Start counter signal
i_Stop : in std_logic -- Stop counter signal
);
end STD_04000_good;
--CODE
architecture Behavioral of STD_04000_good is
constant c_Length : std_logic_vector(3 downto 0) := (others => '1'); -- How long we should count
type t_state is (init, loading, enabled, finished); -- Enumerated type for state encoding
signal sm_State : t_state; -- State signal
signal Raz : std_logic; -- Load the length value and initialize the counter
signal Enable : std_logic; -- Counter enable signal
signal Count_Length : std_logic_vector(3 downto 0); -- Counter length for counting
signal End_Count : std_logic; -- End signal of counter
begin
-- A simple counter with loading length and enable signal
Counter : Counter
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_Raz => Raz,
i_Enable => Enable,
i_Length => Count_Length,
o_Done => End_Count
);
-- FSM process controlling the counter. Start or stop it in function of the input (i_Start & i_Stop),
-- load the length value, and wait for it to finish
P_FSM : process(i_Reset_n, i_Clock)
begin
if (i_Reset_n = '0') then
sm_State <= init;
Raz <= '0';
Enable <= '0';
Count_Length <= (others=>'0');
elsif (rising_edge(i_Clock)) then
case sm_State is
when init =>
-- Set the length value
Count_Length <= c_Length;
sm_State <= loading;
when loading =>
-- Load the counter and initialize it
Raz <= '1';
sm_State <= enabled;
when enabled =>
-- Start or stop counting depending on inputs until it finishes
Raz <= '0';
if (End_Count = '0') then
-- The counter has not finished, wait
Enable <= i_Start xor not i_Stop;
sm_State <= Enabled;
else
-- The counter has finished, nothing else to do
Enable <= '0';
sm_State <= finished;
end if;
when others =>
sm_State <= init;
end case;
end if;
end process;
end Behavioral;
--CODE
| gpl-3.0 | 1d829e1ca45afecd1d98ed36cae4cb91 | 0.489486 | 4.639775 | false | false | false | false |
APastorG/APG | permutation/perm_ss.vhd | 1 | 5,385 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented by
/ Altera and Xilinx in their software.
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
library work;
use work.common_pkg.all;
use work.common_data_types_pkg.all;
use work.counter_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity perm_ss is
generic(
indexes : integer_v(1 to 2);
dimensions : positive
);
port(
clk : in std_ulogic;
start : in std_ulogic;
input : in sulv_v;
finish : out std_ulogic;
output : out sulv_v
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture perm_ss_1 of perm_ss is
--highest serial index
constant J : positive := maximum(indexes(1), indexes(2));
--lowest serial index
constant K : positive := minimum(indexes(1), indexes(2));
--parallel dimensions
constant P : natural := integer(log2(real(input'length)));
--serial dimensions
constant S : natural := dimensions - P;
constant LATENCY : positive := integer((2.0**J-2**K)/(2.0*P));
signal count_is_not_zero : std_ulogic;
signal counter_out : std_ulogic;
signal count : std_ulogic_vector(counter_CW(true, --UNSIGNED_2COMP_opt,
0, --COUNTER_WIDTH_dep,
true, --TARGET_MODE,
(2 ** S)- 1, --TARGET_dep,
true, --TARGET_WITH_COUNT_opt = t_true,
false, --USE_SET,
1) - 1 --SET_TO_dep)
downto 0); --only the serial indexes (N downto P) mapped to downto 0
signal control : std_ulogic;
signal start_delayed : std_ulogic_vector(0 to LATENCY);
/*================================================================================================*/
/*================================================================================================*/
begin
count_is_not_zero <= unsigned(count) ?/= 0;
counter:
entity work.counter
generic map(
UNSIGNED_2COMP_opt => true,
OVERFLOW_BEHAVIOR_opt => t_wrap,
--COUNT_MODE_opt => t_up,
--COUNTER_WIDTH_dep => ,
TARGET_MODE => true,
TARGET_dep => (2 ** S)- 1,
TARGET_WITH_COUNT_opt => t_true,
TARGET_BLOCKING_opt => t_false,
USE_SET => false,
--SET_TO_dep => ,
USE_RESET => true,
--SET_RESET_PRIORITY_opt => ,
USE_LOAD => false
)
port map(
clk => clk,
enable => count_is_not_zero or start_delayed(0),
--set => ,
reset => counter_out,
--load => ,
--count_mode_signal => ,
--value_to_load => ,
count => count,
count_is_TARGET(1) => counter_out
);
control <= not(count(J-P)) or count(K-P);
generate_serial_serial_permutation:
for i in input'range generate
signal inter : sulv_v(0 to LATENCY-1)(input(input'left)'range);
begin
process(clk) is
begin
if rising_edge(clk) then
inter(0) <= inter(LATENCY-1) when control='0' else
input(i);
end if;
end process;
output(i) <= input(i) when control='0' else
inter(LATENCY-1);
more_than_one_register:
if LATENCY > 1 generate
begin
process (clk) is
begin
if rising_edge(clk) then
inter(1 to LATENCY-1) <= inter(0 to LATENCY-2);
end if;
end process;
end;
end generate;
end;
end generate;
finish <= start_delayed(LATENCY);
start_delayed(0) <= start;
process (clk) is
begin
if rising_edge(clk) then
if LATENCY > 0 then
start_delayed(1 to LATENCY) <= start_delayed(0 to LATENCY-1);
END IF;
end if;
end process;
end architecture; | mit | 6d7a1d99c2bbdbaed1e0518f6a7e2bad | 0.389834 | 4.653043 | false | false | false | false |
sonologic/gmzpu | vhdl/zpu_medium.vhdl | 1 | 53,073 | ------------------------------------------------------------------------------
---- ----
---- ZPU Medium ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is the medium size version. ----
---- Supports external memories. ----
---- Modified to support the interrupt line. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- - Koen Martens, gmc sonologic.nl ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: ZPUMediumCore(Behave) (Entity and architecture) ----
---- File name: zpu_medium.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- zpu.zpupkg ----
---- Target FPGA: Spartan 3 (XC3S400-4-FT256) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
--
-- write_en_o - set to '1' for a single cycle to send off a write request.
-- data_o is valid only while write_en_o='1'.
-- read_en_o - set to '1' for a single cycle to send off a read request.
-- mem_busy_i - It is illegal to send off a read/write request when
-- mem_busy_i='1'.
-- Set to '0' when data_i is valid after a read request.
-- If it goes to '1'(busy), it is on the cycle after read/
-- write_en_o is '1'.
-- addr_o - address for read/write request
-- data_i - read data. Valid only on the cycle after mem_busy_i='0'
-- after read_en_o='1' for a single cycle.
-- data_o - data to write
-- break_o - set to '1' when CPU hits break instruction
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library zpu;
use zpu.zpupkg.all;
entity ZPUMediumCore is
generic(
WORD_SIZE : integer:=32; -- 16/32 (2**wordPower)
ADDR_W : integer:=16; -- Total address space width (incl. I/O)
MEM_W : integer:=15; -- Memory (prog+data+stack) width
D_CARE_VAL : std_logic:='X'; -- Value used to fill the unsused bits
MULT_PIPE : boolean:=false; -- Pipeline multiplication
BINOP_PIPE : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)
ENA_LEVEL0 : boolean:=true; -- eq, loadb, neqbranch and pushspadd
ENA_LEVEL1 : boolean:=true; -- lessthan, ulessthan, mult, storeb, callpcrel and sub
ENA_LEVEL2 : boolean:=false; -- lessthanorequal, ulessthanorequal, call and poppcrel
ENA_LSHR : boolean:=true; -- lshiftright
ENA_IDLE : boolean:=false; -- Enable the enable_i input
FAST_FETCH : boolean:=true); -- Merge the st_fetch with the st_execute states
port(
clk_i : in std_logic; -- CPU Clock
reset_i : in std_logic; -- Sync Reset
interrupt_i : in std_logic; -- Interrupt
enable_i : in std_logic; -- Hold the CPU (after reset)
break_o : out std_logic; -- Break instruction executed
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- Memory interface
mem_busy_i : in std_logic; -- Memory is busy
data_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from mem
data_o : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem
addr_o : out unsigned(ADDR_W-1 downto 0); -- Memory address
write_en_o : out std_logic; -- Memory write enable
read_en_o : out std_logic); -- Memory read enable
end entity ZPUMediumCore;
architecture Behave of ZPUMediumCore is
constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes
constant WORD_BYTES : integer:=WORD_SIZE/OPCODE_W;
constant MAX_ADDR_BIT : integer:=ADDR_W-2;
-- Stack Pointer initial value: BRAM size-8
constant SP_START_1 : unsigned(ADDR_W-1 downto 0):=to_unsigned((2**MEM_W)-8,ADDR_W);
constant SP_START : unsigned(ADDR_W-1 downto BYTE_BITS):=
SP_START_1(ADDR_W-1 downto BYTE_BITS);
-- Update [SP+1]. We hold it in b_r, this writes the value to memory.
procedure FlushB(signal we : out std_logic;
signal addr : out unsigned(ADDR_W-1 downto BYTE_BITS);
signal inc_sp : in unsigned(ADDR_W-1 downto BYTE_BITS);
signal data : out unsigned(WORD_SIZE-1 downto 0);
signal b : in unsigned(WORD_SIZE-1 downto 0)) is
begin
we <= '1';
addr <= inc_sp;
data <= b;
end procedure FlushB;
-- Do a simple stack push, it is performed in the internal cache registers,
-- not in the real memory.
procedure Push(signal sp : inout unsigned(ADDR_W-1 downto BYTE_BITS);
signal a : in unsigned(WORD_SIZE-1 downto 0);
signal b : out unsigned(WORD_SIZE-1 downto 0)) is
begin
b <= a; -- Update cache [SP+1]=[SP]
sp <= sp-1;
end procedure Push;
-- Do a simple stack pop, it is performed in the internal cache registers,
-- not in the real memory.
procedure Pop(signal sp : inout unsigned(ADDR_W-1 downto BYTE_BITS);
signal a : out unsigned(WORD_SIZE-1 downto 0);
signal b : in unsigned(WORD_SIZE-1 downto 0)) is
begin
a <= b; -- Update cache [SP]=[SP+1]
sp <= sp+1;
end procedure Pop;
-- Expand a PC value to WORD_SIZE
function ExpandPC(v : unsigned(ADDR_W-1 downto 0)) return unsigned is
variable nv : unsigned(WORD_SIZE-1 downto 0);
begin
nv:=(others => '0');
nv(ADDR_W-1 downto 0):=v;
return nv;
end function ExpandPC;
-- Program counter
signal pc_r : unsigned(ADDR_W-1 downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(ADDR_W-1 downto BYTE_BITS):=SP_START;
-- SP+1, SP+2 and SP-1 are very used, these are shortcuts
signal inc_sp : unsigned(ADDR_W-1 downto BYTE_BITS);
signal inc_inc_sp : unsigned(ADDR_W-1 downto BYTE_BITS);
-- a_r is a cache for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_r : unsigned(WORD_SIZE-1 downto 0);
-- b_r is a cache for the next value in the stack [SP+1]
signal b_r : unsigned(WORD_SIZE-1 downto 0);
signal bin_op_res1_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
signal bin_op_res2_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
signal mult_res1_r : unsigned(WORD_SIZE-1 downto 0);
signal mult_res2_r : unsigned(WORD_SIZE-1 downto 0);
signal mult_res3_r : unsigned(WORD_SIZE-1 downto 0);
signal mult_a_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
signal mult_b_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
signal idim_r : std_logic;
signal write_en_r : std_logic;
signal read_en_r : std_logic;
signal addr_r : unsigned(ADDR_W-1 downto BYTE_BITS):=(others => '0');
signal fetched_w_r : unsigned(WORD_SIZE-1 downto 0);
-- IRQ flag
signal in_irq_r : std_logic:='0';
type state_t is(st_load2, st_popped, st_load_sp2, st_load_sp3, st_add_sp2,
st_fetch, st_execute, st_decode, st_decode2, st_resync,
st_store_sp2, st_resync2, st_resync3, st_loadb2, st_storeb2,
st_mult2, st_mult3, st_mult5, st_mult4, st_binary_op_res2,
st_binary_op_res, st_idle);
signal state : state_t:=st_resync;
-- Go to st_fetch state or just do its work
procedure DoFetch(constant FAST : boolean;
signal state : out state_t;
signal addr : out unsigned(ADDR_W-1 downto BYTE_BITS);
signal pc : in unsigned(ADDR_W-1 downto 0);
signal re : out std_logic;
signal busy : in std_logic) is
begin
if FAST then
-- Equivalent to st_fetch
if busy='0' then
addr <= pc(ADDR_W-1 downto BYTE_BITS);
re <= '1';
state <= st_decode;
end if;
else
state <= st_fetch;
end if;
end procedure DoFetch;
-- Perform a "binary operation" (2 operands)
procedure DoBinOp(result : in unsigned(WORD_SIZE-1 downto 0);
signal state : out state_t;
signal sp : inout unsigned(ADDR_W-1 downto BYTE_BITS);
signal addr : out unsigned(ADDR_W-1 downto BYTE_BITS);
signal re : out std_logic;
signal dest : out unsigned(WORD_SIZE-1 downto 0);
signal dest_p : out unsigned(WORD_SIZE-1 downto 0);
constant DEPTH : natural) is
begin
if DEPTH=2 then
-- 2 clocks: st_binary_op_res+st_binary_op_res2
state <= st_binary_op_res;
dest_p <= result;
elsif DEPTH=1 then
-- 1 clock: st_binary_op_res2
state <= st_binary_op_res2;
dest_p <= result;
else -- 0 clocks
re <= '1';
addr <= sp+2;
sp <= sp+1;
dest <= result;
state <= st_popped;
end if;
end procedure DoBinOp;
-- Perform a boolean "binary operation" (2 operands)
procedure DoBinOpBool(result : in boolean;
signal state : out state_t;
signal sp : inout unsigned(ADDR_W-1 downto BYTE_BITS);
signal addr : out unsigned(ADDR_W-1 downto BYTE_BITS);
signal re : out std_logic;
signal dest : out unsigned(WORD_SIZE-1 downto 0);
signal dest_p : out unsigned(WORD_SIZE-1 downto 0);
constant DEPTH : natural) is
variable res : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
begin
if result then
res(0):='1';
end if;
DoBinOp(res,state,sp,addr,re,dest,dest_p,DEPTH);
end procedure DoBinOpBool;
type insn_t is (dec_add_top, dec_dup, dec_dup_stk_b, dec_pop, dec_add,
dec_or, dec_and, dec_store, dec_add_sp, dec_shift, dec_nop,
dec_im, dec_load_sp, dec_store_sp, dec_emulate, dec_load,
dec_push_sp, dec_pop_pc, dec_pop_pc_rel, dec_not, dec_flip,
dec_pop_sp, dec_neq_branch, dec_eq, dec_loadb, dec_mult,
dec_less_than, dec_less_than_or_equal, dec_lshr,
dec_u_less_than_or_equal, dec_u_less_than, dec_push_sp_add,
dec_call, dec_call_pc_rel, dec_sub, dec_break, dec_storeb,
dec_insn_fetch, dec_pop_down, dec_interrupt);
signal insn : insn_t;
type insn_array_t is array(0 to WORD_BYTES-1) of insn_t;
signal insns : insn_array_t;
type opcode_array_t is array(0 to WORD_BYTES-1) of unsigned(OPCODE_W-1 downto 0);
signal opcode_r : opcode_array_t;
begin
-- the memory subsystem will tell us one cycle later whether or
-- not it is busy
write_en_o <= write_en_r;
read_en_o <= read_en_r;
addr_o(ADDR_W-1 downto BYTE_BITS) <= addr_r;
addr_o(BYTE_BITS-1 downto 0) <= (others => '0');
-- SP+1 and +2
inc_sp <= sp_r+1;
inc_inc_sp <= sp_r+2;
opcode_control:
process (clk_i)
variable topcode : unsigned(OPCODE_W-1 downto 0);
variable ex_opcode : unsigned(OPCODE_W-1 downto 0);
variable sp_offset : unsigned(4 downto 0);
variable tsp_offset : unsigned(4 downto 0);
variable next_pc : unsigned(ADDR_W-1 downto 0);
variable tdecoded : insn_t;
variable tinsns : insn_array_t;
variable mult_res : unsigned(WORD_SIZE*2-1 downto 0);
variable ipc_low : integer range 0 to 3; -- Address inside a word (pc_r)
variable inpc_low : integer range 0 to 3; -- Address inside a word (next_pc)
variable h_bit : integer;
variable l_bit : integer;
variable not_lshr : std_logic:='1';
begin
if rising_edge(clk_i) then
break_o <= '0';
if reset_i='1' then
if ENA_IDLE then
state <= st_idle;
else
state <= st_resync;
end if;
sp_r <= SP_START;
pc_r <= (others => '0');
idim_r <= '0';
in_irq_r <= '0';
write_en_r <= '0';
read_en_r <= '0';
mult_a_r <= (others => '0');
mult_b_r <= (others => '0');
dbg_o.b_inst <= '0';
-- Reseting add_r here makes XST fail to use BRAMs ?!
else -- reset_i='1'
if MULT_PIPE then
-- We must multiply unconditionally to get pipelined multiplication
mult_res:=mult_a_r*mult_b_r;
mult_res1_r <= mult_res(WORD_SIZE-1 downto 0);
mult_res2_r <= mult_res1_r;
mult_res3_r <= mult_res2_r;
mult_a_r <= (others => D_CARE_VAL);
mult_b_r <= (others => D_CARE_VAL);
end if;
if BINOP_PIPE=2 then
bin_op_res2_r <= bin_op_res1_r; -- pipeline a bit.
end if;
read_en_r <='0';
write_en_r <='0';
-- Allow synthesis tools to load bogus values when we don't
-- care about the address and output data.
addr_r <= (others => D_CARE_VAL);
data_o <= (others => D_CARE_VAL);
if (write_en_r='1') and (read_en_r='1') then
report "read/write collision" severity failure;
end if;
ipc_low:=to_integer(pc_r(BYTE_BITS-1 downto 0));
sp_offset(4):=not opcode_r(ipc_low)(4);
sp_offset(3 downto 0):=opcode_r(ipc_low)(3 downto 0);
next_pc:=pc_r+1;
if interrupt_i='0' then
in_irq_r <= '0'; -- nolonger in an interrupt
end if;
-- Prepare trace snapshot
dbg_o.opcode <= opcode_r(ipc_low);
dbg_o.pc <= resize(pc_r,32);
dbg_o.stk_a <= resize(a_r,32);
dbg_o.stk_b <= resize(b_r,32);
dbg_o.b_inst <= '0';
dbg_o.sp <= (others => '0');
dbg_o.sp(ADDR_W-1 downto BYTE_BITS) <= sp_r;
case state is
when st_idle =>
if enable_i='1' then
state <= st_resync;
end if;
-- Initial state of ZPU, fetch top of stack (A/B) + first instruction
when st_resync =>
if mem_busy_i='0' then
addr_r <= sp_r;
read_en_r <= '1';
state <= st_resync2;
end if;
when st_resync2 =>
if mem_busy_i='0' then
a_r <= data_i;
addr_r <= inc_sp;
read_en_r <= '1';
state <= st_resync3;
end if;
when st_resync3 =>
if mem_busy_i='0' then
b_r <= data_i;
addr_r <= pc_r(ADDR_W-1 downto BYTE_BITS);
read_en_r <= '1';
state <= st_decode;
end if;
when st_decode =>
if mem_busy_i='0' then
-- Here we latch the fetched word to give one full clock
-- cycle to the instruction decoder. This could be removed
-- if using BRAMs and the decoder delay isn't important.
fetched_w_r <= data_i;
state <= st_decode2;
end if;
when st_decode2 =>
if interrupt_i='1' and in_irq_r='0' then
-- if interrupt asserted, execute interrupt
tinsns(0):=dec_interrupt;
tinsns(1):=dec_interrupt;
tinsns(2):=dec_interrupt;
tinsns(3):=dec_interrupt;
insn <= tinsns(ipc_low);
-- once we wrap, we need to fetch
-- tinsns(0):=dec_insn_fetch;
insns <= tinsns;
state <= st_execute;
in_irq_r <= '1';
else
-- decode 4 instructions in parallel
for i in 0 to WORD_BYTES-1 loop
topcode:=fetched_w_r((WORD_BYTES-1-i+1)*8-1 downto (WORD_BYTES-1-i)*8);
tsp_offset(4):=not topcode(4);
tsp_offset(3 downto 0):=topcode(3 downto 0);
opcode_r(i) <= topcode;
if topcode(7 downto 7)=OPCODE_IM then
tdecoded:=dec_im;
elsif topcode(7 downto 5)=OPCODE_STORESP then
if tsp_offset=0 then
-- Special case, we can avoid a write
tdecoded:=dec_pop;
elsif tsp_offset=1 then
-- Special case, collision
tdecoded:=dec_pop_down;
else
tdecoded:=dec_store_sp;
end if;
elsif topcode(7 downto 5)=OPCODE_LOADSP then
if tsp_offset=0 then
tdecoded:=dec_dup;
elsif tsp_offset=1 then
tdecoded:=dec_dup_stk_b;
else
tdecoded:=dec_load_sp;
end if;
elsif topcode(7 downto 5)=OPCODE_EMULATE then
tdecoded:=dec_emulate;
if ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_NEQBRANCH then
tdecoded:=dec_neq_branch;
elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_EQ then
tdecoded:=dec_eq;
elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_LOADB then
tdecoded:=dec_loadb;
elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_PUSHSPADD then
tdecoded:=dec_push_sp_add;
elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_LESSTHAN then
tdecoded:=dec_less_than;
elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_ULESSTHAN then
tdecoded:=dec_u_less_than;
elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_MULT then
tdecoded:=dec_mult;
elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_STOREB then
tdecoded:=dec_storeb;
elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_CALLPCREL then
tdecoded:=dec_call_pc_rel;
elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_SUB then
tdecoded:=dec_sub;
elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_LESSTHANOREQUAL then
tdecoded:=dec_less_than_or_equal;
elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_ULESSTHANOREQUAL then
tdecoded:=dec_u_less_than_or_equal;
elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_CALL then
tdecoded:=dec_call;
elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_POPPCREL then
tdecoded:=dec_pop_pc_rel;
elsif ENA_LSHR and topcode(5 downto 0)=OPCODE_LSHIFTRIGHT then
tdecoded:=dec_lshr;
end if;
elsif topcode(7 downto 4)=OPCODE_ADDSP then
if tsp_offset=0 then
tdecoded:=dec_shift;
elsif tsp_offset=1 then
tdecoded:=dec_add_top;
else
tdecoded:=dec_add_sp;
end if;
else -- OPCODE_SHORT
case topcode(3 downto 0) is
when OPCODE_BREAK =>
tdecoded:=dec_break;
when OPCODE_PUSHSP =>
tdecoded:=dec_push_sp;
when OPCODE_POPPC =>
tdecoded:=dec_pop_pc;
when OPCODE_ADD =>
tdecoded:=dec_add;
when OPCODE_OR =>
tdecoded:=dec_or;
when OPCODE_AND =>
tdecoded:=dec_and;
when OPCODE_LOAD =>
tdecoded:=dec_load;
when OPCODE_NOT =>
tdecoded:=dec_not;
when OPCODE_FLIP =>
tdecoded:=dec_flip;
when OPCODE_STORE =>
tdecoded:=dec_store;
when OPCODE_POPSP =>
tdecoded:=dec_pop_sp;
when others => -- OPCODE_NOP and others
tdecoded:=dec_nop;
end case;
end if;
tinsns(i):=tdecoded;
end loop;
insn <= tinsns(ipc_low);
-- once we wrap, we need to fetch
tinsns(0):=dec_insn_fetch;
insns <= tinsns;
state <= st_execute;
end if;
-- Each instruction must:
--
-- 1. increase pc_r if applicable
-- 2. set next state if applicable
-- 3. do it's operation
when st_execute =>
-- Some shortcut to make the code readable:
inpc_low:=to_integer(next_pc(BYTE_BITS-1 downto 0));
ex_opcode:=opcode_r(ipc_low);
insn <= insns(inpc_low);
-- Defaults used by most instructions
if insn/=dec_insn_fetch and insn/=dec_im then
dbg_o.b_inst <= '1';
idim_r <= '0';
end if;
case insn is
when dec_interrupt =>
-- Not a real instruction, interrupt
-- Push(PC); PC=32
-- sp_r <= sp_r-1;
-- a_addr_r <= sp_r-1;
-- a_we_r <= '1';
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
a_r <= (others => D_CARE_VAL);
a_r(ADDR_W-1 downto 0) <= pc_r;
Push(sp_r,a_r,b_r);
pc_r <= to_unsigned(32,ADDR_W); -- interrupt address
report "ZPU jumped to interrupt!" severity note;
-- TODO: force fetch
insn <= dec_insn_fetch;
when dec_insn_fetch =>
-- Not a real instruction, fetch new instructions
DoFetch(FAST_FETCH,state,addr_r,pc_r,read_en_r,mem_busy_i);
when dec_im =>
-- Push(immediate value), IDIM=1
-- if IDIM=0 Push(signed(opcode & 0x7F)) else
-- Push((Pop()<<7)|(opcode&0x7F))
if mem_busy_i='0' then
dbg_o.b_inst <= '1';
idim_r <= '1';
pc_r <= pc_r+1;
if idim_r='1' then
-- We already started an IM sequence
-- Shift left 7 bits
a_r(WORD_SIZE-1 downto 7) <= a_r(WORD_SIZE-8 downto 0);
-- Put the new value
a_r(6 downto 0) <= ex_opcode(6 downto 0);
else
-- First IM, push the value sign extended
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
a_r <= unsigned(resize(signed(ex_opcode(6 downto 0)),WORD_SIZE));
Push(sp_r,a_r,b_r);
end if;
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
if mem_busy_i='0' then
write_en_r <= '1';
addr_r <= sp_r+sp_offset;
data_o <= a_r;
Pop(sp_r,a_r,b_r);
-- We need to fetch B
state <= st_store_sp2;
end if;
when dec_load_sp =>
-- Push([SP+Offset])
if mem_busy_i='0' then
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
Push(sp_r,a_r,b_r);
-- We are flushing B cache, so we need more time to
-- read the value.
state <= st_load_sp2;
end if;
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
if mem_busy_i='0' then
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
state <= st_fetch;
a_r <= ExpandPC(pc_r+1);
Push(sp_r,a_r,b_r);
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= ex_opcode(4 downto 0);
end if;
when dec_call_pc_rel =>
-- t=Pop(), Push(PC+1), PC=PC+t
if mem_busy_i='0' and ENA_LEVEL1 then
state <= st_fetch;
a_r <= ExpandPC(pc_r+1);
pc_r <= pc_r+a_r(ADDR_W-1 downto 0);
end if;
when dec_call =>
-- t=Pop(), Push(PC+1), PC=t
if mem_busy_i='0' and ENA_LEVEL2 then
state <= st_fetch;
a_r <= ExpandPC(pc_r+1);
pc_r <= a_r(ADDR_W-1 downto 0);
end if;
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
if mem_busy_i='0' then
-- Read SP+Offset
state <= st_add_sp2;
read_en_r <= '1';
addr_r <= sp_r+sp_offset;
pc_r <= pc_r+1;
end if;
when dec_push_sp =>
-- Push(SP)
if mem_busy_i='0' then
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
pc_r <= pc_r+1;
a_r <= (others => '0');
a_r(ADDR_W-1 downto BYTE_BITS) <= sp_r;
Push(sp_r,a_r,b_r);
end if;
when dec_pop_pc =>
-- PC=Pop() (return)
if mem_busy_i='0' then
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
state <= st_resync;
pc_r <= a_r(ADDR_W-1 downto 0);
sp_r <= inc_sp;
end if;
when dec_pop_pc_rel =>
-- PC=PC+Pop()
if mem_busy_i='0' and ENA_LEVEL2 then
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
state <= st_resync;
pc_r <= a_r(ADDR_W-1 downto 0)+pc_r;
sp_r <= inc_sp;
end if;
when dec_add =>
-- Push(Pop()+Pop()) [A=A+B, SP++, update B]
if mem_busy_i='0' then
state <= st_popped;
a_r <= a_r+b_r;
read_en_r <= '1';
addr_r <= inc_inc_sp;
sp_r <= inc_sp;
end if;
when dec_sub =>
-- a=Pop(), b=Pop(), Push(b-a)
if mem_busy_i='0' and ENA_LEVEL1 then
DoBinOp(b_r-a_r,state,sp_r,addr_r,read_en_r,
a_r,bin_op_res1_r,BINOP_PIPE);
end if;
when dec_pop =>
-- Pop()
if mem_busy_i='0' then
state <= st_popped;
addr_r <= inc_inc_sp;
read_en_r <= '1';
Pop(sp_r,a_r,b_r);
end if;
when dec_pop_down =>
-- t=Pop(), Pop(), Push(t)
if mem_busy_i='0' then
-- PopDown leaves top of stack unchanged
state <= st_popped;
addr_r <= inc_inc_sp;
read_en_r <= '1';
sp_r <= inc_sp;
end if;
when dec_or =>
-- Push(Pop() or Pop())
if mem_busy_i='0' then
state <= st_popped;
a_r <= a_r or b_r;
read_en_r <= '1';
addr_r <= inc_inc_sp;
sp_r <= inc_sp;
end if;
when dec_and =>
-- Push(Pop() and Pop())
if mem_busy_i='0' then
state <= st_popped;
a_r <= a_r and b_r;
read_en_r <= '1';
addr_r <= inc_inc_sp;
sp_r <= inc_sp;
end if;
when dec_eq =>
-- a=Pop(), b=Pop(), Push(a=b ? 1 : 0)
if mem_busy_i='0' and ENA_LEVEL0 then
DoBinOpBool(a_r=b_r,state,sp_r,addr_r,read_en_r,
a_r,bin_op_res1_r,BINOP_PIPE);
end if;
when dec_u_less_than =>
-- a=Pop(), b=Pop(), Push(a<b ? 1 : 0)
if mem_busy_i='0' and ENA_LEVEL1 then
DoBinOpBool(a_r<b_r,state,sp_r,addr_r,read_en_r,
a_r,bin_op_res1_r,BINOP_PIPE);
end if;
when dec_u_less_than_or_equal =>
-- a=Pop(), b=Pop(), Push(a<=b ? 1 : 0)
if mem_busy_i='0' and ENA_LEVEL2 then
DoBinOpBool(a_r<=b_r,state,sp_r,addr_r,read_en_r,
a_r,bin_op_res1_r,BINOP_PIPE);
end if;
when dec_less_than =>
-- a=signed(Pop()), b=signed(Pop()), Push(a<b ? 1 : 0)
if mem_busy_i='0' and ENA_LEVEL1 then
DoBinOpBool(signed(a_r)<signed(b_r),state,sp_r,
addr_r,read_en_r,a_r,bin_op_res1_r,
BINOP_PIPE);
end if;
when dec_less_than_or_equal =>
-- a=signed(Pop()), b=signed(Pop()), Push(a<=b ? 1 : 0)
if mem_busy_i='0' and ENA_LEVEL2 then
DoBinOpBool(signed(a_r)<=signed(b_r),state,sp_r,
addr_r,read_en_r,a_r,bin_op_res1_r,
BINOP_PIPE);
end if;
when dec_load =>
-- Push([Pop()])
if mem_busy_i='0' then
state <= st_load2;
addr_r <= a_r(ADDR_W-1 downto BYTE_BITS);
read_en_r <= '1';
pc_r <= pc_r+1;
end if;
when dec_dup =>
-- t=Pop(), Push(t), Push(t)
if mem_busy_i='0' then
pc_r <= pc_r+1;
-- A is dupped, no change
Push(sp_r,a_r,b_r);
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
end if;
when dec_dup_stk_b =>
-- Pop(), t=Pop(), Push(t), Push(t), Push(t)
if mem_busy_i='0' then
pc_r <= pc_r+1;
a_r <= b_r;
-- B goes to A
Push(sp_r,a_r,b_r);
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
end if;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
if mem_busy_i='0' then
state <= st_resync;
pc_r <= pc_r+1;
addr_r <= a_r(ADDR_W-1 downto BYTE_BITS);
data_o <= b_r;
write_en_r <= '1';
sp_r <= inc_inc_sp;
end if;
when dec_pop_sp =>
-- SP=Pop()
if mem_busy_i='0' then
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
state <= st_resync;
pc_r <= pc_r+1;
sp_r <= a_r(ADDR_W-1 downto BYTE_BITS);
end if;
when dec_nop =>
pc_r <= pc_r+1;
when dec_not =>
-- Push(not(Pop()))
pc_r <= pc_r+1;
a_r <= not a_r;
when dec_flip =>
-- Push(flip(Pop()))
pc_r <= pc_r+1;
for i in 0 to WORD_SIZE-1 loop
a_r(i) <= a_r(WORD_SIZE-1-i);
end loop;
when dec_add_top =>
-- a=Pop(), b=Pop(), Push(b), Push(a+b)
pc_r <= pc_r+1;
a_r <= a_r+b_r;
when dec_shift =>
-- Push(Pop()<<1) [equivalent to a=Pop(), Push(a+a)]
pc_r <= pc_r+1;
a_r(WORD_SIZE-1 downto 1) <= a_r(WORD_SIZE-2 downto 0);
a_r(0) <= '0';
when dec_push_sp_add =>
-- Push(Pop()+SP)
if ENA_LEVEL0 then
pc_r <= pc_r+1;
a_r <= (others => '0');
a_r(ADDR_W-1 downto BYTE_BITS) <=
a_r(ADDR_W-1-BYTE_BITS downto 0)+sp_r;
end if;
when dec_neq_branch =>
-- a=Pop(), b=Pop(), PC+=b==0 ? 1 : a
-- Branches are almost always taken as they form loops
if ENA_LEVEL0 then
sp_r <= inc_inc_sp;
-- Need to fetch stack again.
state <= st_resync;
if b_r/=0 then
pc_r <= a_r(ADDR_W-1 downto 0)+pc_r;
else
pc_r <= pc_r+1;
end if;
end if;
when dec_mult =>
-- Push(Pop()*Pop())
if ENA_LEVEL1 then
if MULT_PIPE then
mult_a_r <= a_r;
mult_b_r <= b_r;
state <= st_mult2;
else
mult_res:=a_r*b_r;
mult_res1_r <= mult_res(WORD_SIZE-1 downto 0);
state <= st_mult5;
end if;
end if;
when dec_break =>
-- Assert the break_o signal
--report "Break instruction encountered" severity failure;
break_o <= '1';
pc_r <= pc_r+1;
when dec_loadb =>
-- Push([Pop()] & 0xFF) (byte address)
if mem_busy_i='0' and ENA_LEVEL0 then
state <= st_loadb2;
addr_r <= a_r(ADDR_W-1 downto BYTE_BITS);
read_en_r <= '1';
pc_r <= pc_r+1;
end if;
when dec_storeb =>
-- [Pop()]=Pop() & 0xFF (byte address)
if mem_busy_i='0' and ENA_LEVEL1 then
state <= st_storeb2;
addr_r <= a_r(ADDR_W-1 downto BYTE_BITS);
read_en_r <= '1';
pc_r <= pc_r+1;
end if;
when dec_lshr =>
-- a=Pop(), b=Pop(), Push(b>>(a&0x3F))
if ENA_LSHR then
-- This instruction takes more than one cycle.
-- We must avoid duplications in the trace log.
dbg_o.b_inst <= not_lshr;
not_lshr:='0';
if a_r(5 downto 0)=0 then -- Only 6 bits used
-- No more shifts
if mem_busy_i='0' then
state <= st_popped;
a_r <= b_r;
read_en_r <= '1';
addr_r <= inc_inc_sp;
sp_r <= inc_sp;
not_lshr:='1';
end if;
else -- More shifts needed
b_r <= "0"&b_r(WORD_SIZE-1 downto 1);
a_r(5 downto 0) <= a_r(5 downto 0)-1;
insn <= insn;
end if;
end if;
when others =>
-- Undefined behavior, we shouldn't get here.
-- It only helps synthesis tools.
sp_r <= (others => D_CARE_VAL);
report "Illegal decode instruction?!" severity failure;
--break_o <= '1';
end case;
-- The followup of operations that takes more than one execution clock
when st_store_sp2 =>
if mem_busy_i='0' then
addr_r <= inc_sp;
read_en_r <= '1';
state <= st_popped;
end if;
when st_load_sp2 =>
if mem_busy_i='0' then
state <= st_load_sp3;
-- Now we can read SP+Offset (SP already decremented)
read_en_r <= '1';
addr_r <= sp_r+sp_offset+1;
end if;
when st_load_sp3 =>
if mem_busy_i='0' then
-- Note: We can't increment PC in the decode stage
-- because it will modify sp_offset.
pc_r <= pc_r+1;
-- Finally we have the result in A
state <= st_execute;
a_r <= data_i;
end if;
when st_add_sp2 =>
if mem_busy_i='0' then
state <= st_execute;
a_r <= a_r+data_i;
end if;
when st_load2 =>
if mem_busy_i='0' then
a_r <= data_i;
state <= st_execute;
end if;
when st_loadb2 =>
if mem_busy_i='0' then
a_r <= (others => '0');
-- Select the source bits using the less significant bits (byte address)
h_bit:=(WORD_BYTES-to_integer(a_r(BYTE_BITS-1 downto 0)))*8-1;
l_bit:=h_bit-7;
a_r(7 downto 0) <= data_i(h_bit downto l_bit);
state <= st_execute;
end if;
when st_storeb2 =>
if mem_busy_i='0' then
addr_r <= a_r(ADDR_W-1 downto BYTE_BITS);
data_o <= data_i;
-- Select the source bits using the less significant bits (byte address)
h_bit:=(WORD_BYTES-to_integer(a_r(BYTE_BITS-1 downto 0)))*8-1;
l_bit:=h_bit-7;
data_o(h_bit downto l_bit) <= b_r(7 downto 0);
write_en_r <= '1';
sp_r <= inc_inc_sp;
state <= st_resync;
end if;
when st_fetch =>
if mem_busy_i='0' then
addr_r <= pc_r(ADDR_W-1 downto BYTE_BITS);
read_en_r <= '1';
state <= st_decode;
end if;
-- The following states can be used to leave cycles free for
-- tools that can automagically decompose the multiplication
-- in various stages. Xilinx tools can do it to increase the
-- multipliers performance.
when st_mult2 =>
state <= st_mult3;
when st_mult3 =>
state <= st_mult4;
when st_mult4 =>
state <= st_mult5;
when st_mult5 =>
if mem_busy_i='0' then
if MULT_PIPE then
a_r <= mult_res3_r;
else
a_r <= mult_res1_r;
end if;
read_en_r <= '1';
addr_r <= inc_inc_sp;
sp_r <= inc_sp;
state <= st_popped;
end if;
when st_binary_op_res =>
-- BINOP_PIPE=2
state <= st_binary_op_res2;
when st_binary_op_res2 =>
-- BINOP_PIPE>=1
read_en_r <= '1';
addr_r <= inc_inc_sp;
sp_r <= inc_sp;
state <= st_popped;
if BINOP_PIPE=2 then
a_r <= bin_op_res2_r;
else -- 1
a_r <= bin_op_res1_r;
end if;
when st_popped =>
if mem_busy_i='0' then
-- Note: Moving this PC++ to the decoder seems to
-- consume more LUTs.
pc_r <= pc_r+1;
b_r <= data_i;
state <= st_execute;
end if;
when others =>
-- Undefined behavior, we shouldn't get here.
-- It only helps synthesis tools.
sp_r <= (others => D_CARE_VAL);
report "Illegal state?!" severity failure;
--break_o <= '1';
end case; -- state
end if; -- else reset_i='1'
end if; -- rising_edge(clk_i)
end process opcode_control;
end architecture Behave; -- Entity: ZPUMediumCore
| bsd-3-clause | 0ac7053e2821e050ef7e6a027cc3e113 | 0.347559 | 4.692573 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/korvet/src/mapper/mapper.vhd | 1 | 5,434 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file mapper.vhd when simulating
-- the core, mapper. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY mapper IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END mapper;
ARCHITECTURE mapper_a OF mapper IS
-- synthesis translate_off
COMPONENT wrapped_mapper
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_mapper USE ENTITY XilinxCoreLib.blk_mem_gen_v6_3(behavioral)
GENERIC MAP (
c_addra_width => 13,
c_addrb_width => 13,
c_algorithm => 0,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "mapper.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 8192,
c_read_depth_b => 8192,
c_read_width_a => 3,
c_read_width_b => 3,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 8192,
c_write_depth_b => 8192,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 3,
c_write_width_b => 3,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_mapper
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END mapper_a;
| gpl-3.0 | ed8b4f9d258601e23e018f320c620a43 | 0.515274 | 4.001473 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/speccy/src/keyboard/keyboard.vhd | 1 | 6,262 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity keyboard is
port(
CLK : in std_logic;
RESET : in std_logic;
PS2_CLK : in std_logic;
PS2_DATA : in std_logic;
KEYB_ADDR : in std_logic_vector(7 downto 0);
KEYB_DATA : out std_logic_vector(4 downto 0);
RESET_TICK : out std_logic;
NMI_TICK : out std_logic );
end keyboard;
architecture rtl of keyboard is
signal CODE : std_logic_vector(7 downto 0); -- Scancode recieved from keyboard
signal DONE : std_logic; -- Current scancode valid
signal ERROR : std_logic; -- Current scancode corrupted
signal LOOKUP : std_logic_vector(7 downto 0); -- bits 7-5 - A8..A15, bits 4-0 - D4..D0
signal RELEASED_KEY : std_logic;
signal EXTENDED_KEY : std_logic;
type MATRIX_IMAGE is array (natural range <>) of std_logic_vector(4 downto 0);
signal MATRIX : MATRIX_IMAGE(0 to 7); -- Speccy keyboard matrix
begin
u_PS2 : entity work.ps2
port map(
CLK => CLK,
RESET => RESET,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
CODE => CODE,
DONE => DONE,
ERROR => ERROR );
decoder : process (CODE)
begin
case CODE is
when X"12" => LOOKUP <= "00000001"; -- left/caps shift
when X"1a" => LOOKUP <= "00000010"; -- z
when X"22" => LOOKUP <= "00000100"; -- x
when X"21" => LOOKUP <= "00001000"; -- c
when X"2a" => LOOKUP <= "00010000"; -- v
when X"1c" => LOOKUP <= "00100001"; -- a
when X"1b" => LOOKUP <= "00100010"; -- s
when X"23" => LOOKUP <= "00100100"; -- d
when X"2b" => LOOKUP <= "00101000"; -- f
when X"34" => LOOKUP <= "00110000"; -- g
when X"15" => LOOKUP <= "01000001"; -- q
when X"1d" => LOOKUP <= "01000010"; -- w
when X"24" => LOOKUP <= "01000100"; -- e
when X"2d" => LOOKUP <= "01001000"; -- r
when X"2c" => LOOKUP <= "01010000"; -- t
when X"16" => LOOKUP <= "01100001"; -- 1
when X"69" => LOOKUP <= "01100001"; -- 1
when X"1e" => LOOKUP <= "01100010"; -- 2
when X"72" => LOOKUP <= "01100010"; -- 2
when X"26" => LOOKUP <= "01100100"; -- 3
when X"7a" => LOOKUP <= "01100100"; -- 3
when X"25" => LOOKUP <= "01101000"; -- 4
when X"6b" => LOOKUP <= "01101000"; -- 4
when X"2e" => LOOKUP <= "01110000"; -- 5
when X"73" => LOOKUP <= "01110000"; -- 5
when X"45" => LOOKUP <= "10000001"; -- 0
when X"70" => LOOKUP <= "10000001"; -- 0
when X"46" => LOOKUP <= "10000010"; -- 9
when X"7d" => LOOKUP <= "10000010"; -- 9
when X"3e" => LOOKUP <= "10000100"; -- 8
when X"75" => LOOKUP <= "10000100"; -- 8
when X"3d" => LOOKUP <= "10001000"; -- 7
when X"6c" => LOOKUP <= "10001000"; -- 7
when X"36" => LOOKUP <= "10010000"; -- 6
when X"74" => LOOKUP <= "10010000"; -- 6
when X"4d" => LOOKUP <= "10100001"; -- p
when X"44" => LOOKUP <= "10100010"; -- o
when X"43" => LOOKUP <= "10100100"; -- i
when X"3c" => LOOKUP <= "10101000"; -- u
when X"35" => LOOKUP <= "10110000"; -- y
when X"5a" => LOOKUP <= "11000001"; -- return
when X"4b" => LOOKUP <= "11000010"; -- l
when X"42" => LOOKUP <= "11000100"; -- k
when X"3b" => LOOKUP <= "11001000"; -- j
when X"33" => LOOKUP <= "11010000"; -- h
when X"29" => LOOKUP <= "11100001"; -- Space
when X"59" => LOOKUP <= "11100010"; -- right/symbol shift
when X"3a" => LOOKUP <= "11100100"; -- m
when X"31" => LOOKUP <= "11101000"; -- n
when X"32" => LOOKUP <= "11110000"; -- b
when others => LOOKUP <= "00000000";
end case;
end process;
main : process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
MATRIX <= (others => (others => '0'));
RELEASED_KEY <= '0';
EXTENDED_KEY <= '0';
RESET_TICK <= '0';
NMI_TICK <= '0';
else
RESET_TICK <= '0';
NMI_TICK <= '0';
if ERROR = '1' then
MATRIX <= (others => (others => '0'));
RELEASED_KEY <= '0';
EXTENDED_KEY <= '0';
elsif DONE = '1' then
if CODE = X"F0" then
RELEASED_KEY <= '1';
elsif CODE = X"E0" then
EXTENDED_KEY <= '1';
elsif CODE = X"07" and RELEASED_KEY = '1' then
RESET_TICK <= '1';
elsif CODE = X"78" and RELEASED_KEY = '1' then
NMI_TICK <= '1';
else
RELEASED_KEY <= '0';
EXTENDED_KEY <= '0';
-- if LOOKUP /= "00000000" then
if RELEASED_KEY = '0' then
MATRIX(to_integer(unsigned(LOOKUP(7 downto 5)))) <= MATRIX(to_integer(unsigned(LOOKUP(7 downto 5)))) or std_logic_vector(unsigned(LOOKUP(4 downto 0)));
else
MATRIX(to_integer(unsigned(LOOKUP(7 downto 5)))) <= MATRIX(to_integer(unsigned(LOOKUP(7 downto 5)))) and std_logic_vector(not unsigned(LOOKUP(4 downto 0)));
end if;
-- end if;
end if;
end if;
end if;
end if;
end process;
keyboard_output : for i in 0 to 4 generate
KEYB_DATA(i) <= not ((MATRIX(0)(i) and not KEYB_ADDR(0)) or
(MATRIX(1)(i) and not KEYB_ADDR(1)) or
(MATRIX(2)(i) and not KEYB_ADDR(2)) or
(MATRIX(3)(i) and not KEYB_ADDR(3)) or
(MATRIX(4)(i) and not KEYB_ADDR(4)) or
(MATRIX(5)(i) and not KEYB_ADDR(5)) or
(MATRIX(6)(i) and not KEYB_ADDR(6)) or
(MATRIX(7)(i) and not KEYB_ADDR(7)) );
end generate;
end; | gpl-3.0 | da390703ca646b220818c57d8696da46 | 0.457042 | 3.644936 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/bashkiria-2m/src/clock/clk50m.vhd | 1 | 6,557 | -- file: clk50m.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.000______0.000______50.0______200.000____150.000
-- CLK_OUT2____20.000______0.000______50.0_____1200.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________50____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk50m is
port
(-- Clock in ports
inclk0 : in std_logic;
-- Clock out ports
c0 : out std_logic;
c1 : out std_logic
);
end clk50m;
architecture xilinx of clk50m is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk50m,clk_wiz_v3_6,{component_name=clk50m,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=2,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clk_out1_internal : std_logic;
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => inclk0);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.500,
CLKFX_DIVIDE => 5,
CLKFX_MULTIPLY => 2,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
clkfb <= clk_out1_internal;
clkout1_buf : BUFG
port map
(O => clk_out1_internal,
I => clk0);
c0 <= clk_out1_internal;
clkout2_buf : BUFG
port map
(O => c1,
I => clkfx);
end xilinx;
| gpl-3.0 | d10ed59db8bb0b9586e0c05dded1f29c | 0.55681 | 4.173775 | false | false | false | false |
seiken-chuouniv/ecorun | ecorun_fi_hardware/fi_timer/FiTimer/SerialReceiver.vhd | 1 | 1,429 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:49:01 03/15/2015
-- Design Name:
-- Module Name: SerialReceiver - RTL
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity SerialReceiver is
port(
clk : in std_logic;
rx : in std_logic := '1';
data : out std_logic_vector(7 downto 0) := (others => '0')
);
end SerialReceiver;
architecture RTL of SerialReceiver is
type state_type is (idle, receiving, stopbit);
signal state : state_type := idle;
signal temp_data : std_logic_vector(7 downto 0);
signal bit_pos : integer range 0 to 7 := 0;
begin
process(clk) begin
if (clk'event and clk = '1') then
-- serial receive
-- XgbvrbgÅcounter_matchªXV
if ((state = idle) and rx = '0') then
bit_pos <= 0;
state <= receiving;
elsif (state = receiving) then
temp_data <= rx & temp_data(7 downto 1);
bit_pos <= bit_pos + 1;
if (bit_pos = 7) then
state <= stopbit;
end if;
elsif (state = stopbit) then
if (rx = '1') then
data <= temp_data;
state <= idle;
end if;
end if;
end if;
end process;
end RTL;
| bsd-3-clause | b2510980d4d70a842a54725bf8998903 | 0.539538 | 3.189732 | false | false | false | false |
APastorG/APG | pipelines/pipelines.vhd | 1 | 1,845 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented by
/ Altera and Xilinx in their software.
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity pipelines is
generic(
LENGTH : natural
);
port(
clk : in std_ulogic;
input : in std_ulogic_vector;
output : out std_ulogic_vector
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture pipelines_1 of pipelines is
begin
pipelines_core_1:
entity work.pipelines_core
generic map(
LENGTH => LENGTH,
INPUT_HIGH => input'high,
INPUT_LOW => input'low
)
port map(
clk => clk,
input => input,
output => output
);
end architecture; | mit | ea3221fe6b85f4193eda4105d753668c | 0.309221 | 5.357988 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/cham_rom/cham_rom/example_design/cham_rom_prod.vhd | 1 | 9,910 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: cham_rom_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : cham_rom.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 16384
-- C_READ_DEPTH_A : 16384
-- C_ADDRA_WIDTH : 14
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 16384
-- C_READ_DEPTH_B : 16384
-- C_ADDRB_WIDTH : 14
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY cham_rom_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END cham_rom_prod;
ARCHITECTURE xilinx OF cham_rom_prod IS
COMPONENT cham_rom_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : cham_rom_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| gpl-3.0 | 6e3453d0b3877f579463b11cf58fc942 | 0.49445 | 3.824778 | false | false | false | false |
freecores/lq057q3dc02 | design/enab_control.vhd | 1 | 4,699 | ------------------------------------------------------------------------------
-- Copyright (C) 2007 Jonathon W. Donaldson
-- jwdonal a t opencores DOT org
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
------------------------------------------------------------------------------
--
-- $Id: enab_control.vhd,v 1.1 2008-11-07 00:48:12 jwdonal Exp $
--
-- Description:
-- This file controls ENAB. ENAB is dependent upon both HSYNCx, VSYNCx, and
-- the number of CLK_LCD cycles that have passed. ENAB "tells" (i.e.
-- "enables") the shift registers inside the LCD to start accepting data.
--
-- Structure:
-- - xupv2p.ucf
-- - components.vhd
-- - lq057q3dc02_tb.vhd
-- - lq057q3dc02.vhd
-- - dcm_sys_to_lcd.xaw
-- - video_controller.vhd
-- - enab_control.vhd
-- - hsyncx_control.vhd
-- - vsyncx_control.vhd
-- - clk_lcd_cyc_cntr.vhd
-- - image_gen_bram.vhd
-- - image_gen_bram_red.xco
-- - image_gen_bram_green.xco
-- - image_gen_bram_blue.xco
--
------------------------------------------------------------------------------
--
-- Naming Conventions:
-- active low signals "*x"
-- clock signal "CLK_*"
-- reset signal "RST"
-- generic/constant "C_*"
-- user defined type "TYPE_*"
-- state machine next state "*_ns"
-- state machine current state "*_cs""
-- pipelined signals "*_d#"
-- register delay signals "*_p#"
-- signal "*_sig"
-- variable "*_var"
-- storage register "*_reg"
-- clock enable signals "*_ce"
-- internal version of output port used as connecting wire "*_wire"
-- input/output port "ALL_CAPS"
-- process "*_PROC"
--
------------------------------------------------------------------------------
--////////////////////--
-- LIBRARY INCLUSIONS --
--////////////////////--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--////////////////////--
-- ENTITY DECLARATION --
--////////////////////--
ENTITY enab_control IS
generic (
C_VSYNC_TVS,
C_CLK_LCD_CYC_NUM_WIDTH,
C_ENAB_TEP,
C_ENAB_THE : POSITIVE
);
port (
RSTx,
CLK_LCD : IN std_logic;
CLK_LCD_CYC_NUM : IN std_logic_vector(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0);
ENAB : OUT std_logic
);
END ENTITY enab_control;
--////////////////////////--
-- ARCHITECTURE OF ENTITY --
--////////////////////////--
ARCHITECTURE enab_control_arch OF enab_control IS
begin
------------------------------------------------------------------
-- Process Description:
-- This process enables/disables the ENAB output signal depending
-- on the value of the pixel/enab cycle counter and the user-defined
-- timing parameters.
--
-- Inputs:
-- RSTx
-- CLK_LCD
--
-- Outputs:
-- ENAB
--
-- Notes:
-- N/A
------------------------------------------------------------------
ENAB_cntrl_PROC : process( RSTx, CLK_LCD )
begin
if( RSTx = '0' ) then
ENAB <= '0';
elsif( CLK_LCD'event and CLK_LCD = '1' ) then
if( CLK_LCD_CYC_NUM >= (C_ENAB_THE - 1) and --start
CLK_LCD_CYC_NUM < (C_ENAB_THE + C_ENAB_TEP - 1) ) then --stop
ENAB <= '1'; --active
else
ENAB <= '0';
end if;
end if;
end process ENAB_cntrl_PROC;
END ARCHITECTURE enab_control_arch;
| gpl-2.0 | 40813ab88a920c1eb9fba7c77fca4020 | 0.453501 | 4.203041 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk01/src/ppi/i8255.vhd | 2 | 2,925 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i8255 is
port (
CLK : in std_logic;
RESET : in std_logic;
A : in std_logic_vector(1 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
WR : in std_logic;
PAI : in std_logic_vector(7 downto 0);
PAO : out std_logic_vector(7 downto 0);
PBI : in std_logic_vector(7 downto 0);
PBO : out std_logic_vector(7 downto 0);
PCI : in std_logic_vector(7 downto 0);
PCO : out std_logic_vector(7 downto 0));
end i8255;
architecture Behavioral of i8255 is
signal PORTA : std_logic_vector(7 downto 0);
signal PORTB : std_logic_vector(7 downto 0);
signal PORTC : std_logic_vector(7 downto 0);
signal CONTROL : std_logic_vector(7 downto 0);
begin
DO <= PAI when A = "00" and CONTROL(4) = '1' else
PORTA when A = "00" and CONTROL(4) = '0' else
PBI when A = "01" and CONTROL(1) = '1' else
PORTB when A = "01" and CONTROL(1) = '0' else
PCI when A = "10" and CONTROL(0) = '1' and CONTROL(3) = '1' else
PORTC when A = "10" and CONTROL(0) = '0' and CONTROL(3) = '0' else
PCI(7 downto 4) & PORTC(3 downto 0) when A = "10" and CONTROL(0) = '1' and CONTROL(3) = '0' else
PORTC(7 downto 4) & PCI(3 downto 0) when A = "10" and CONTROL(0) = '0' and CONTROL(3) = '1' else
CONTROL;
PAO <= PORTA;
PBO <= PORTB;
PCO <= PORTC;
registers_write : process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
CONTROL <= "10011011";
PORTA <= "00000000";
PORTB <= "00000000";
PORTC <= "00000000";
else
if WR = '1' then
case A is
when "00" => PORTA <= DI;
when "01" => PORTB <= DI;
when "10" => PORTC <= DI;
when others => CONTROL <= DI;
if DI(7) = '0' then -- Bit set/reset
case DI(3 downto 1) is
when "000" => PORTC(0) <= DI(0);
when "001" => PORTC(1) <= DI(0);
when "010" => PORTC(2) <= DI(0);
when "011" => PORTC(3) <= DI(0);
when "100" => PORTC(4) <= DI(0);
when "101" => PORTC(5) <= DI(0);
when "110" => PORTC(6) <= DI(0);
when others => PORTC(7) <= DI(0);
end case;
end if;
end case;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | aa6d3401f98a5180446fb13f20ede1d7 | 0.439316 | 3.53688 | false | false | false | false |
223323/lab2 | HDL/source/rtl/vhdl/counter.vhd | 1 | 1,583 | -------------------------------------------------------------------------------
-- Odsek za racunarsku tehniku i medjuracunarske komunikacije
-- Autor: LPRS2 <[email protected]>
--
-- Ime modula: timer_counter
--
-- Opis:
--
-- Modul broji sekunde i prikazuje na LED diodama
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY counter IS
GENERIC (
WIDTH : positive := 10
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
cnt_rst_i : IN STD_LOGIC;
cnt_en_i : IN STD_LOGIC;
cnt_o : out std_logic_vector(WIDTH-1 downto 0)
);
END counter;
ARCHITECTURE rtl OF counter IS
signal cnt : std_logic_vector(WIDTH-1 downto 0);
BEGIN
process(clk_i,rst_i,cnt_rst_i) begin
if rst_i = '0' or cnt_rst_i = '0' then
cnt <= (others => '0');
elsif rising_edge(clk_i) and cnt_en_i = '1' then
cnt <= cnt + 1;
end if;
end process;
cnt_o <= cnt;
END rtl;
| mit | 3227d6b2f63abdcc863f9614ff53c741 | 0.353127 | 4.255376 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/components/complete_address_decoder.vhdl | 1 | 1,551 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY complete_address_decoder IS
generic (width : natural := 1);
PORT
(
addr_in : in std_logic_vector(width-1 downto 0);
addr_decoded : out std_logic_vector((2**width)-1 downto 0)
);
END complete_address_decoder;
--ARCHITECTURE vhdl OF complete_address_decoder IS
--BEGIN
-- comp_gen:
-- for i in 0 to ((2**width)-1) generate
-- addr_decoded(i) <= '1' when i=to_integer(unsigned(addr_in)) else '0';
-- end generate;
--end vhdl;
architecture tree of complete_address_decoder is
constant STAGE : natural:=width;
type std_logic_2d is array (natural range <>,natural range <>) of std_logic;
signal p: std_logic_2d(stage downto 0,2**stage-1 downto 0);
signal a: std_logic_vector(width-1 downto 0) ;
begin
a<=addr_in;
process(a,p)
begin
p(stage,0) <= '1';
for s in stage downto 1 loop
for r in 0 to (2**(stage-s)-1) loop
p(s-1,2*r) <= (not a(s-1)) and p(s,r);
p(s-1,2*r+1) <= a(s-1) and p(s,r);
end loop;
end loop;
for i in 0 to (2**stage-1) loop
addr_decoded(i) <= p(0,i);
end loop;
end process;
end tree; | gpl-3.0 | 34e9e98cd068813a6950b2e0aa559c4b | 0.604771 | 3.059172 | false | false | false | false |
APastorG/APG | rotator/rotator_s.vhd | 1 | 7,863 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented by
/ Altera and Xilinx in their software.
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.fixed_generic_pkg.all;
use work.fixed_float_types.all;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.complex_const_mult_pkg.all;
use work.real_const_mult_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity rotator_s is
generic(
SPEED_opt : T_speed := t_exc;
ROUND_STYLE_opt : T_round_style := fixed_truncate;
ROUND_TO_BIT_opt : integer_exc := integer'low;
MAX_ERROR_PCT_opt : real_exc := real'low;
MIN_OUTPUT_BIT : integer_exc := integer'low;
MAX_OUTPUT_BIT : integer_exc := integer'low;
ANGLE_DEGREES : real
);
port(
clk : in std_ulogic;
input_real : in u_sfixed;
input_imag : in u_sfixed;
valid_input : in std_ulogic;
output_real : out u_sfixed;
output_imag : out u_sfixed;
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture rotator_s_1 of rotator_s is
signal inter_real : u_sfixed(complex_const_mult_OH(round_style_opt => ROUND_STYLE_OPT,
round_to_bit_opt => ROUND_TO_BIT_OPT,
max_error_pct_opt => MAX_ERROR_PCT_OPT,
max_output_bit => MAX_OUTPUT_BIT,
constants => (cos(ANGLE_DEGREES*MATH_PI/180.0),
sin(ANGLE_DEGREES*MATH_PI/180.0)),
input_high => input_real'high,
input_low => input_real'low,
is_signed => true)
downto
complex_const_mult_OL(round_style_opt => ROUND_STYLE_OPT,
round_to_bit_opt => ROUND_TO_BIT_OPT,
max_error_pct_opt => MAX_ERROR_PCT_OPT,
min_output_bit => MIN_OUTPUT_BIT,
constants => (cos(ANGLE_DEGREES*MATH_PI/180.0),
sin(ANGLE_DEGREES*MATH_PI/180.0)),
input_low => input_real'low,
is_signed => true)
);
signal inter_imag : u_sfixed(inter_real'range);
/*================================================================================================*/
/*================================================================================================*/
begin
complex_const_mult_core_s_1:
entity work.complex_const_mult_core_s
generic map(
SPEED_opt => SPEED_opt,
ROUND_STYLE_opt => ROUND_STYLE_opt,
ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
MIN_OUTPUT_BIT => MIN_OUTPUT_BIT,
MAX_OUTPUT_BIT => MAX_OUTPUT_BIT,
MULTIPLICAND_REAL => cos(ANGLE_DEGREES*MATH_PI/180.0),
MULTIPLICAND_IMAG => sin(ANGLE_DEGREES*MATH_PI/180.0),
INPUT_HIGH => input_real'high,
INPUT_LOW => input_real'low
)
port map(
clk => clk,
input_real => input_real,
input_imag => input_imag,
valid_input => valid_input,
output_real => inter_real,
output_imag => inter_imag,
valid_output => valid_output
);
truncate_min_exists:
if MIN_OUTPUT_BIT /= integer'low generate
truncate_max_exists:
if MAX_OUTPUT_BIT /= integer'low generate
max_needed:
if MAX_OUTPUT_BIT < inter_real'high generate
min_needed:
if MIN_OUTPUT_BIT > inter_real'low generate
output_real(MAX_OUTPUT_BIT downto MIN_OUTPUT_BIT) <= inter_real(MAX_OUTPUT_BIT downto MIN_OUTPUT_BIT);
output_imag(MAX_OUTPUT_BIT downto MIN_OUTPUT_BIT) <= inter_imag(MAX_OUTPUT_BIT downto MIN_OUTPUT_BIT);
else generate
output_real(MAX_OUTPUT_BIT downto inter_real'low) <= inter_real(MAX_OUTPUT_BIT downto inter_real'low);
output_imag(MAX_OUTPUT_BIT downto inter_real'low) <= inter_imag(MAX_OUTPUT_BIT downto inter_real'low);
end generate;
else generate
min_needed:
if MIN_OUTPUT_BIT > inter_real'low generate
output_real(inter_real'high downto MIN_OUTPUT_BIT) <= inter_real(inter_real'high downto MIN_OUTPUT_BIT);
output_imag(inter_real'high downto MIN_OUTPUT_BIT) <= inter_imag(inter_real'high downto MIN_OUTPUT_BIT);
else generate
output_real <= inter_real(output_real'high downto output_real'low);
output_imag <= inter_imag(output_imag'high downto output_imag'low);
end generate;
end generate;
else generate
truncate_max_exists:
if MIN_OUTPUT_BIT /= integer'low generate
min_needed:
if MIN_OUTPUT_BIT > inter_real'low generate
output_real <= inter_real(output_real'high downto MIN_OUTPUT_BIT);
output_imag <= inter_imag(output_imag'high downto MIN_OUTPUT_BIT);
else generate
output_real <= inter_real;
output_imag <= inter_imag;
end generate;
else generate
output_real <= inter_real;
output_imag <= inter_imag;
end generate;
end generate;
else generate
truncate_max_exists:
if MAX_OUTPUT_BIT /= integer'low generate
max_needed:
if MAX_OUTPUT_BIT < inter_real'high generate
output_real(MAX_OUTPUT_BIT downto inter_real'low) <= inter_real(MAX_OUTPUT_BIT downto inter_real'low);
output_imag(MAX_OUTPUT_BIT downto inter_real'low) <= inter_imag(MAX_OUTPUT_BIT downto inter_real'low);
else generate
output_real <= inter_real;
output_imag <= inter_imag;
end generate;
else generate
output_real <= inter_real;
output_imag <= inter_imag;
end generate;
end generate;
end architecture; | mit | ce7168b8a1d494a2c435723991507211 | 0.438753 | 4.486533 | false | false | false | false |
APastorG/APG | counter/counter_core.vhd | 1 | 10,937 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented by
/ Altera and Xilinx in their software.
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is a design of a counter that implements different features like reset, enable, load,
/ set, and the direction of counting (up, down, or indicated by an input signal). Additionaly it
/ allows to select the overflow behavior (saturate or wrap), and offers a mode called TARGET_count.
/ This mode outputs only a bit, which indicates when the count reaches a desired value, with the
/ possibility to block it when reaching said value.
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.counter_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity counter_core is
generic(
UNSIGNED_2COMP_opt : boolean;
OVERFLOW_BEHAVIOR_opt : T_overflow_behavior;
COUNT_MODE_opt : T_count_mode;
COUNTER_WIDTH_dep : positive_exc;
TARGET_MODE : boolean;
TARGET_dep : integer_exc;
TARGET_WITH_COUNT_opt : boolean_exc;
TARGET_BLOCKING_opt : boolean_exc;
USE_SET : boolean;
SET_TO_dep : integer_exc;
USE_RESET : boolean;
SET_RESET_PRIORITY_opt : T_set_reset_priority;
USE_LOAD : boolean
);
port(
clk : in std_ulogic;
enable : in std_ulogic;
count_mode_signal : in std_ulogic;
set : in std_ulogic;
reset : in std_ulogic;
load : in std_ulogic;
value_to_load : in std_ulogic_vector(counter_CIW(UNSIGNED_2COMP_opt,
COUNTER_WIDTH_dep,
TARGET_MODE,
TARGET_dep,
USE_SET,
SET_TO_dep)
downto 1);
count : out std_ulogic_vector(counter_CW(UNSIGNED_2COMP_opt,
COUNTER_WIDTH_dep,
TARGET_MODE,
TARGET_dep,
TARGET_WITH_COUNT_opt = t_true,
USE_SET,
SET_TO_dep)
downto 1);
count_is_TARGET : out std_ulogic_vector(ite(TARGET_MODE, 1, 0) downto 1)
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture counter_core1 of counter_core is
/* constants */
/**************************************************************************************************/
constant TARGET_WITH_COUNT : boolean := TARGET_WITH_COUNT_opt = t_true; --default : false
constant TARGET_BLOCKING : boolean := TARGET_BLOCKING_opt = t_true; --default : false
constant MIN_WIDTH_COUNTER_GM : positive := counter_MWCG(UNSIGNED_2COMP_opt,
TARGET_dep,
USE_SET,
SET_TO_dep);
--counter width
constant COUNT_INTER_WIDTH : natural := counter_CIW(UNSIGNED_2COMP_opt,
COUNTER_WIDTH_dep,
TARGET_MODE,
TARGET_dep,
USE_SET,
SET_TO_dep);
--used counter width, that is 0 when in target mode and TARGET_WITH_COUNT is false,
--COUNT_INTER_WIDTH otherwise
constant COUNT_WIDTH : natural :=counter_CW(UNSIGNED_2COMP_opt,
COUNTER_WIDTH_dep,
TARGET_MODE,
TARGET_dep,
TARGET_WITH_COUNT,
USE_SET,
SET_TO_dep);
constant COUNTER_WIDTH : integer := integer(COUNTER_WIDTH_dep);
constant TARGET : integer := integer(TARGET_dep);
/* signals */
/**************************************************************************************************/
signal count_inter : std_ulogic_vector(COUNT_INTER_WIDTH downto 1) := (others => '0');
/* procedures to update the value of the count */
/**************************************************************************************************/
procedure set_routine (
signal counter : inout std_ulogic_vector) is
begin
counter <= sulv_from_int(SET_TO_dep, not UNSIGNED_2COMP_opt, COUNT_INTER_WIDTH);
end procedure;
procedure reset_routine (
signal counter : inout std_ulogic_vector) is
begin
counter <= sulv_from_int(0, not UNSIGNED_2COMP_opt, COUNT_INTER_WIDTH);
end procedure;
procedure load_routine (
signal counter : inout std_ulogic_vector;
signal value_to_load : in std_ulogic_vector) is
begin
counter <= value_to_load;
end procedure;
procedure count_routine (
signal count : inout std_ulogic_vector;
signal count_mode_signal : in std_ulogic) is
begin--count upwards
if COUNT_MODE_opt = t_up
or
(COUNT_MODE_opt = t_input_signal and count_mode_signal = '1')
then
--count when not on the upper limit or when behavior is to wrap
if count /= max_vec(count, not UNSIGNED_2COMP_opt)
or
OVERFLOW_BEHAVIOR_opt = t_wrap
then
--increase count
if UNSIGNED_2COMP_opt then
count <= unsigned(count) + 1;
else
count <= signed(count) + 1;
end if;
end if;
--count downwards
else
--count when not on the lower limit or when behavior is to wrap
if count /= min_vec(count, not UNSIGNED_2COMP_opt)
or
OVERFLOW_BEHAVIOR_opt = t_wrap
then
--decrease count
if UNSIGNED_2COMP_opt then
count <= unsigned(count) - 1;
else
count <= signed(count) - 1;
end if;
end if;
end if;
end procedure;
/*================================================================================================*/
/*================================================================================================*/
begin
/* generate the count value and count_is_TARGET if in TARGET mode */
/**************************************************************************************************/
generate_count_value:
if TARGET_MODE generate
begin
count_is_TARGET(1) <= count_inter ?= sulv_from_int(TARGET,
not UNSIGNED_2COMP_opt,
count_inter'length);
generate_count_in_TARGET_mode:
if TARGET_WITH_COUNT generate
begin
count <= count_inter;
end;
end generate;
end;
else generate
begin
count <= count_inter;
end;
end generate;
/* update the count value (count_inter) */
/**************************************************************************************************/
process (clk)
begin
if rising_edge(clk) then
--1st: set if there's no reset or if set has priority
if USE_SET and set='1' and
((USE_RESET and SET_RESET_PRIORITY_opt=t_set) or not USE_RESET) then
set_routine(count_inter);
--2nd: reset
elsif USE_RESET and reset='1' then
reset_routine(count_inter);
--3rd: set if there's reset and it has priority
elsif USE_SET and set='1' and
(USE_RESET and SET_RESET_PRIORITY_opt=t_reset) then
set_routine(count_inter);
--4th: load
elsif USE_LOAD and load='1' then
load_routine(count_inter, value_to_load);
--5th: increase count (unless we are in TARGET mode, the count is TARGET and the behavior is
-- blocking)
elsif (enable='1' and not(TARGET_MODE
and count_inter = sulv_from_int(TARGET,
not UNSIGNED_2COMP_opt,
count_inter'length)
and TARGET_BLOCKING)) then
if COUNT_WIDTH = 1 then
count_inter <= not count_inter;
else
count_routine(count_inter, count_mode_signal);
end if;
end if;
end if;
end process;
end architecture; | mit | d0231879931a92da2986c2982a784dee | 0.38439 | 5.467904 | false | false | false | false |
seiken-chuouniv/ecorun | ecorun_fi_hardware/fi_timer/FiTimer/Stepper.vhd | 1 | 1,413 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:49:32 06/15/2015
-- Design Name:
-- Module Name: Stepper - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity Stepper is
port(
iac_pulse : in std_logic := '0';
iac_clockwise : in std_logic := '0';
iac_out : out std_logic_vector(7 downto 0) := (others => '0')
);
end Stepper;
architecture Behavioral of Stepper is
signal phase : std_logic_vector(1 downto 0) := (others => '0');
begin
process(iac_pulse) begin
if (falling_edge(iac_pulse)) then
if (iac_clockwise = '1') then
phase <= phase + 1;
else
phase <= phase - 1;
end if;
end if;
if (iac_pulse = '1') then
case phase is
when "00" => iac_out <= "10010000";
when "01" => iac_out <= "00001001";
when "10" => iac_out <= "01100000";
when "11" => iac_out <= "00000110";
when others => iac_out <= (others => '0');
end case;
else
iac_out <= (others => '0');
end if;
end process;
end Behavioral;
| bsd-3-clause | 7fddc05dda542fbe15c9374f2545792f | 0.532909 | 3.119205 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/sram_statemachine_old.vhd | 1 | 6,246 | ---------------------------------------------------------------------------
-- SRAM memory controller
---------------------------------------------------------------------------
-- This file is a part of "Aeon Lite" project
-- Dmitriy Schapotschkin aka ILoveSpeccy '2014
-- [email protected]
-- Project homepage: www.speccyland.net
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY sram_statemachine IS
PORT (
CLK : in std_logic;
RESET_N : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
ADDRESS_IN : in std_logic_vector(22 downto 0);
WRITE_EN : in std_logic;
REQUEST : in std_logic;
BYTE_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0111, if 1=1011. Data fields valid:7 downto 0.
WORD_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0011, if 1=1001. Data fields valid:15 downto 0.
LONGWORD_ACCESS : in std_logic; -- a(0) ignored. lqdm/udqm mask is 0000
COMPLETE : out std_logic;
DATA_OUT : out std_logic_vector(31 downto 0);
SRAM_ADDR : out std_logic_vector(17 downto 0);
SRAM_DQ : inout std_logic_vector(15 downto 0);
SRAM_WE_N : out std_logic;
SRAM_OE_N : out std_logic;
SRAM_UB_N : out std_logic;
SRAM_LB_N : out std_logic;
SRAM_CE0_N : out std_logic;
SRAM_CE1_N : out std_logic );
END sram_statemachine;
ARCHITECTURE vhdl OF sram_statemachine IS
function REPEAT(N: natural; B: std_logic)
return std_logic_vector
is
variable RESULT: std_logic_vector(1 to N);
begin
for i in 1 to N loop
RESULT(i) := B;
end loop;
return RESULT;
end;
signal SRAM_DI : std_logic_vector(15 downto 0);
signal SRAM_DO : std_logic_vector(15 downto 0);
signal DATA_OUT_REG : std_logic_vector(31 downto 0);
signal MASK : std_logic_vector(3 downto 0);
type STATES is (ST_IDLE, ST_READ0, ST_READ1, ST_READ2, ST_WRITE0, ST_WRITE1, ST_WRITE2);
signal STATE : STATES;
BEGIN
SRAM_DQ <= SRAM_DI;
SRAM_DO <= SRAM_DQ;
DATA_OUT <= DATA_OUT_REG;
COMPLETE <= '1' when STATE = ST_IDLE and REQUEST = '0' else '0';
process(CLK, RESET_N)
begin
if RESET_N = '0' then
SRAM_DI <= (OTHERS=>'Z');
SRAM_WE_N <= '1';
SRAM_OE_N <= '1';
SRAM_CE0_N <= '1';
SRAM_CE1_N <= '1';
SRAM_LB_N <= '1';
SRAM_UB_N <= '1';
STATE <= ST_IDLE;
else
if rising_edge(CLK) then
case STATE is
when ST_IDLE =>
SRAM_DI <= (OTHERS=>'Z');
SRAM_WE_N <= '1';
SRAM_OE_N <= '1';
SRAM_LB_N <= '1';
SRAM_UB_N <= '1';
if REQUEST = '1' then
MASK(0) <= (BYTE_ACCESS or WORD_ACCESS) and ADDRESS_IN(0); -- masked on misaligned byte or word
MASK(1) <= (BYTE_ACCESS) and not(address_in(0)); -- masked on aligned byte only
MASK(2) <= BYTE_ACCESS or (WORD_ACCESS and not(ADDRESS_IN(0))); -- masked on aligned word or byte
MASK(3) <= not(LONGWORD_ACCESS); -- masked for everything except long word access
SRAM_ADDR <= ADDRESS_IN(18 downto 1);
SRAM_CE0_N <= ADDRESS_IN(19);
SRAM_CE1_N <= not ADDRESS_IN(19);
if WRITE_EN = '1' then
STATE <= ST_WRITE0;
else
STATE <= ST_READ0;
end if;
end if;
when ST_WRITE0 =>
SRAM_LB_N <= MASK(0);
SRAM_UB_N <= MASK(1);
SRAM_DI(7 downto 0) <= DATA_IN(7 downto 0);
SRAM_DI(15 downto 8) <= (DATA_IN(15 downto 8) and not(repeat(8,MASK(0)))) or (DATA_IN(7 downto 0) and repeat(8,MASK(0)));
SRAM_WE_N <= '0';
STATE <= ST_WRITE1;
when ST_WRITE1 =>
SRAM_WE_N <= '1';
STATE <= ST_WRITE2;
when ST_WRITE2 =>
SRAM_ADDR <= std_logic_vector(unsigned(ADDRESS_IN(18 downto 1)) + 1);
SRAM_DI(7 downto 0) <= (DATA_IN(23 downto 16) and not(repeat(8,MASK(0)))) or (DATA_IN(15 downto 8) and repeat(8,MASK(0)));
SRAM_DI(15 downto 8) <= DATA_IN(31 downto 24);
SRAM_LB_N <= MASK(2);
SRAM_UB_N <= MASK(3);
SRAM_WE_N <= '0';
STATE <= ST_IDLE;
when ST_READ0 =>
SRAM_LB_N <= MASK(0);
SRAM_UB_N <= MASK(1);
SRAM_OE_N <= '0';
STATE <= ST_READ1;
when ST_READ1 =>
DATA_OUT_REG(7 downto 0) <= (SRAM_DO(7 downto 0) and not(repeat(8,MASK(0)))) or (SRAM_DO(15 downto 8) and repeat(8,MASK(0)));
DATA_OUT_REG(15 downto 8) <= SRAM_DO(15 downto 8);
SRAM_ADDR <= std_logic_vector(unsigned(ADDRESS_IN(18 downto 1)) + 1);
SRAM_LB_N <= MASK(2);
SRAM_UB_N <= MASK(3);
STATE <= ST_READ2;
when ST_READ2 =>
DATA_OUT_REG(15 downto 8 ) <= (SRAM_DO(7 downto 0) and repeat(8,MASK(0))) or (DATA_OUT_REG(15 downto 8) and not(repeat(8,MASK(0))));
DATA_OUT_REG(31 downto 16) <= SRAM_DO(15 downto 0);
STATE <= ST_IDLE;
when OTHERS =>
STATE <= ST_IDLE;
end case;
end if;
end if;
end process;
END vhdl;
| gpl-3.0 | 8e9c6c791344b4f4923982e11aafc50d | 0.439641 | 3.764919 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_05100_good.vhd | 1 | 2,943 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-07 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_05100_good.vhd
-- File Creation date : 2015-04-07
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Metastability management: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--CODE
entity STD_05100_good is
port (
i_Reset : in std_logic; -- Reset signal
i_Clock : in std_logic; -- Clock signal
i_A : in std_logic; -- Some async signal
o_A : out std_logic -- Synchronized signal
);
end STD_05100_good;
architecture Behavioral of STD_05100_good is
signal A_r : std_logic; -- Used to synchronize i_A
signal A_r2 : std_logic; -- Module output
begin
-- Double registration of signal A to synchronize it and avoid metastability
P_Register2 : process(i_Reset, i_Clock)
begin
if (i_Reset = '1') then
A_r <= '0';
A_r2 <= '0';
elsif (rising_edge(i_Clock)) then
A_r <= i_A;
A_r2 <= A_r;
end if;
end process;
o_A <= A_r2;
end Behavioral;
--CODE
| gpl-3.0 | b2792750dbc22965f752d5ae0eec015a | 0.476724 | 4.520737 | false | false | false | false |
vvk/sysrek | skin_color_segm/ipcore_dir/delayLineBRAM/simulation/bmg_stim_gen.vhd | 2 | 7,570 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(17,17);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(9 DOWNTO 0) <= WRITE_ADDR(9 DOWNTO 0);
READ_ADDR_INT(9 DOWNTO 0) <= READ_ADDR(9 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 1024
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 1024 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 17,
DOUT_WIDTH => 17,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
| gpl-2.0 | 9d87674cda46cf3c8293e43da6c9f8c0 | 0.558124 | 3.775561 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/host/VGA Console/fontrom/fontrom/simulation/bmg_tb_synth.vhd | 1 | 6,168 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_TB IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE BMG_TB_ARCH OF BMG_TB IS
COMPONENT fontrom_top
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC;
SIGNAL RESET_SYNC_R2 : STD_LOGIC;
SIGNAL RESET_SYNC_R3 : STD_LOGIC;
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
clk_buf: bufg
PORT map(
i => CLK_IN,
o => clk_in_i
);
CLKA <= clk_in_i;
RSTA <= RESET_IN;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => CLK_IN,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
BMG_PORT: fontrom_top PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| gpl-3.0 | b45eff99f8f55b50bacd742fc6a39fde | 0.589981 | 3.855 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/speccy/src/cpu/T80_Pack.vhd | 2 | 8,666 | -- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
XY_State : in std_logic_vector(1 downto 0);
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
XYbit_undoc : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;
| gpl-3.0 | d63a26d6c0749634522592d3c3b2ff8d | 0.529887 | 3.438889 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_03100_bad.vhd | 1 | 2,913 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-02 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_03100_bad.vhd
-- File Creation date : 2015-04-02
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description: Handbook example: Dead VHDL code: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_03100_bad is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
-- i_Enable : in std_logic; -- Enable signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end STD_03100_bad;
--CODE
architecture Behavioral of STD_03100_bad is
signal Q : std_logic; -- D Flip-Flop output
begin
-- D FlipFlop process
P_FlipFlop : process(i_Clock, i_Reset_n)
begin
if (i_Reset_n = '0') then
Q <= '0';
elsif (rising_edge(i_Clock)) then
--if (i_Enable='1') then -- If the flip-flop is enabled
Q <= i_D;
--end if;
end if;
end process;
o_Q <= Q;
end Behavioral;
--CODE
| gpl-3.0 | 83aa4566193d3b8f8e4b6d002a7a3227 | 0.471335 | 4.502318 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/components/scandoubler.vhdl | 1 | 9,447 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY scandoubler IS
GENERIC
(
video_bits : integer := 4
);
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
VGA : IN STD_LOGIC;
COMPOSITE_ON_HSYNC : in std_logic;
colour_enable : in std_logic;
doubled_enable : in std_logic;
scanlines_on : in std_logic := '0';
-- GTIA interface
colour_in : in std_logic_vector(7 downto 0);
vsync_in : in std_logic;
hsync_in : in std_logic;
-- TO TV...
R : OUT STD_LOGIC_vector(video_bits-1 downto 0);
G : OUT STD_LOGIC_vector(video_bits-1 downto 0);
B : OUT STD_LOGIC_vector(video_bits-1 downto 0);
VSYNC : out std_logic;
HSYNC : out std_logic
);
END scandoubler;
ARCHITECTURE vhdl OF scandoubler IS
COMPONENT gtia_palette IS
PORT
(
ATARI_COLOUR : IN STD_LOGIC_VECTOR(7 downto 0);
R_next : OUT STD_LOGIC_VECTOR(7 downto 0);
G_next : OUT STD_LOGIC_VECTOR(7 downto 0);
B_next : OUT STD_LOGIC_VECTOR(7 downto 0)
);
END component;
-- component reg_file IS
-- generic
-- (
-- BYTES : natural := 1;
-- WIDTH : natural := 1
-- );
-- PORT
-- (
-- CLK : IN STD_LOGIC;
-- ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
-- DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- WR_EN : IN STD_LOGIC;
--
-- DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
-- );
-- END component;
component scandouble_ram_infer IS
PORT
(
clock: IN std_logic;
data: IN std_logic_vector (7 DOWNTO 0);
address: IN integer RANGE 0 to 1824;
we: IN std_logic;
q: OUT std_logic_vector (7 DOWNTO 0)
);
END component;
component delay_line IS
generic(COUNT : natural := 1);
PORT
(
CLK : IN STD_LOGIC;
SYNC_RESET : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC;
ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
RESET_N : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC
);
END component;
signal colour_next : std_logic_vector(7 downto 0);
signal colour_reg : std_logic_vector(7 downto 0);
signal vsync_next : std_logic;
signal vsync_reg : std_logic;
signal hsync_next : std_logic;
signal hsync_reg : std_logic;
signal r_next : std_logic_vector(7 downto 0);
signal g_next : std_logic_vector(7 downto 0);
signal b_next : std_logic_vector(7 downto 0);
signal r_reg : std_logic_vector(7 downto 0);
signal g_reg : std_logic_vector(7 downto 0);
signal b_reg : std_logic_vector(7 downto 0);
signal linea_address : std_logic_vector(10 downto 0);
signal linea_write_enable : std_logic;
signal linea_out : std_logic_vector(7 downto 0);
signal lineb_address : std_logic_vector(10 downto 0);
signal lineb_write_enable : std_logic;
signal lineb_out : std_logic_vector(7 downto 0);
signal input_address_next : std_logic_vector(10 downto 0);
signal input_address_reg : std_logic_vector(10 downto 0);
signal output_address_next : std_logic_vector(10 downto 0);
signal output_address_reg : std_logic_vector(10 downto 0);
signal buffer_select_next : std_logic;
signal buffer_select_reg : std_logic;
signal hsync_in_reg : std_logic;
signal vga_hsync_next : std_logic;
signal vga_hsync_reg : std_logic;
signal vga_hsync_start : std_logic;
signal vga_hsync_end : std_logic;
signal vga_odd_reg : std_logic;
signal vga_odd_next : std_logic;
begin
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
r_reg <= (others=>'0');
g_reg <= (others=>'0');
b_reg <= (others=>'0');
colour_reg <= (others=>'0');
hsync_reg <= '0';
vsync_reg <= '0';
input_address_reg <= (others=>'0');
output_address_reg <= (others=>'0');
buffer_select_reg <= '0';
vga_hsync_reg <= '0';
vga_odd_reg <= '0';
elsif (clk'event and clk='1') then
r_reg <= r_next;
g_reg <= g_next;
b_reg <= b_next;
colour_reg <= colour_next;
hsync_reg <= hsync_next;
vsync_reg <= vsync_next;
input_address_reg <= input_address_next;
output_address_reg <= output_address_next;
buffer_select_reg <= buffer_select_next;
hsync_in_reg <= hsync_in;
vga_hsync_reg <= vga_hsync_next;
vga_odd_reg <= vga_odd_next;
end if;
end process;
-- TODO - these should use FPGA RAM - at present about 50% of FPGA is taken by these!!!
-- linea : reg_file
--generic map (BYTES=>456,WIDTH=>9)
--port map (clk=>clk,addr=>linea_address,wr_en=>linea_write_enable,data_in=>colour_in,data_out=>linea_out);
--lineb : reg_file
-- generic map (BYTES=>456,WIDTH=>9)
-- port map (clk=>clk,addr=>lineb_address,wr_en=>lineb_write_enable,data_in=>colour_in,data_out=>lineb_out);
linea : scandouble_ram_infer
port map (clock=>clk,address=>to_integer(unsigned(linea_address)),we=>linea_write_enable,data=>colour_in,q=>linea_out);
lineb : scandouble_ram_infer
port map (clock=>clk,address=>to_integer(unsigned(lineb_address)),we=>lineb_write_enable,data=>colour_in,q=>lineb_out);
-- capture
process(input_address_reg,colour_enable,hsync_in,hsync_in_reg,buffer_select_reg)
begin
input_address_next <= input_address_reg;
buffer_select_next <= buffer_select_reg;
linea_write_enable <= '0';
lineb_write_enable <= '0';
if (colour_enable = '1') then
input_address_next <= std_logic_vector(unsigned(input_address_reg)+1);
linea_write_enable <= buffer_select_reg;
lineb_write_enable <= not(buffer_select_reg);
end if;
if (hsync_in = '1' and hsync_in_reg = '0') then
input_address_next <= (others=>'0');
buffer_select_next <= not(buffer_select_reg);
end if;
end process;
-- output
process(vga_hsync_reg,vga_hsync_end,output_address_reg,doubled_enable,vga_odd_reg)
begin
output_address_next <= output_address_reg;
vga_hsync_start<='0';
vga_hsync_next <= vga_hsync_reg;
vga_odd_next <= vga_odd_reg;
if (doubled_enable = '1') then
output_address_next <= std_logic_vector(unsigned(output_address_reg)+1);
if (output_address_reg = "111"&X"1F") then
output_address_next <= (others=>'0');
vga_hsync_start <= '1';
vga_hsync_next <= '1';
end if;
end if;
if (vga_hsync_end = '1') then
vga_hsync_next <= '0';
vga_odd_next <= not(vga_odd_reg);
end if;
end process;
linea_address <= input_address_reg when buffer_select_reg='1' else output_address_reg;
lineb_address <= input_address_reg when buffer_select_reg='0' else output_address_reg;
hsync_delay : delay_line
generic map (COUNT=>128)
port map(clk=>clk,sync_reset=>'0',data_in=>vga_hsync_start,enable=>doubled_enable,reset_n=>reset_n,data_out=>vga_hsync_end);
-- display
process(colour_reg,vsync_reg,vga_hsync_reg,hsync_reg,colour_in,vsync_in,hsync_in,colour_enable,doubled_enable,vga,composite_on_hsync,buffer_select_reg,linea_out,lineb_out, scanlines_on, vga_odd_reg)
begin
colour_next <= colour_reg;
vsync_next <= vsync_reg;
hsync_next <= hsync_reg;
if (vga = '0') then
-- non-vga mode - pass through
colour_next <= colour_in;
vsync_next <= not(vsync_in);
--hsync_next <= not(hsync_in or vsync_in);
if (composite_on_hsync = '1') then
hsync_next <= not(hsync_in xor vsync_in);
else
hsync_next <= not(hsync_in);
end if;
else
-- vga mode, store all inputs - then play back!
if (buffer_select_reg = '0') then
if (scanlines_on ='1' and vga_odd_reg='1') then
colour_next(7 downto 4) <= linea_out(7 downto 4);
colour_next(3) <= '0';
colour_next(2 downto 0) <= linea_out(3 downto 1);
else
colour_next <= linea_out;
end if;
else
if (scanlines_on ='1' and vga_odd_reg='1') then
colour_next(7 downto 4) <= lineb_out(7 downto 4);
colour_next(3) <= '0';
colour_next(2 downto 0) <= lineb_out(3 downto 1);
else
colour_next <= lineb_out;
end if;
end if;
vsync_next <= not(vsync_in);
--hsync_next <= not(vga_hsync_reg);
if (composite_on_hsync = '1') then
hsync_next <= not(vga_hsync_reg xor vsync_in);
else
hsync_next <= not(vga_hsync_reg);
end if;
end if;
end process;
-- colour palette
-- Color Value Color Value
--Black 0, 0 Medium blue 8, 128
--Rust 1, 16 Dark blue 9, 144
--Red-orange 2, 32 Blue-grey 10, 160
--Dark orange 3, 48 Olive green 11, 176
--Red 4, 64 Medium green 12, 192
--Dk lavender 5, 80 Dark green 13, 208
--Cobalt blue 6, 96 Orange-green 14, 224
--Ultramarine 7, 112 Orange 15, 240
-- from altirra
palette1 : entity work.gtia_palette(altirra)
port map (ATARI_COLOUR=>colour_reg, R_next=>R_next, G_next=>G_next, B_next=>B_next);
-- from lao
-- palette2 : entity work.gtia_palette(laoo)
-- port map (ATARI_COLOUR=>COLOUR, R_next=>R_next, G_next=>G_next, B_next=>B_next);
-- output
-- TODO - for DE2, output full 8 bits
R <= R_reg(7 downto 8-video_bits);
G <= G_reg(7 downto 8-video_bits);
B <= B_reg(7 downto 8-video_bits);
vsync<=vsync_reg;
hsync<=hsync_reg;
end vhdl;
| gpl-3.0 | 9f1f9fd1b0dadcbd9555e9250cbaf6e2 | 0.622737 | 2.837789 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_06100_bad.vhd | 1 | 3,435 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-08 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_06100_bad.vhd
-- File Creation date : 2015-04-08
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Range direction for std_logic_vector: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--CODE
entity STD_06100_bad is
port (
i_Clock : in std_logic; -- Main clock signal
i_Reset_n : in std_logic; -- Main reset signal
i_Enable : in std_logic; -- Enables the counter
i_Length : in std_logic_vector(0 downto 3); -- Unsigned Value for Counter Period
o_Count : out std_logic_vector(0 downto 3) -- Counter (unsigned value)
);
end STD_06100_bad;
architecture Behavioral of STD_06100_bad is
signal Count : unsigned(0 to 3); -- Counter output signal (unsigned converted)
signal Count_Length : unsigned(0 to 3); -- Length input signal (unsigned converted)
begin
--CODE
Count_Length <= unsigned(i_Length);
-- Will count undefinitely from 0 to i_Length while i_Enable is asserted
P_Count : process(i_Reset_n, i_Clock)
begin
if (i_Reset_n = '0') then
Count <= (others => '0');
elsif (rising_edge(i_Clock)) then
if (Count >= Count_Length) then -- Counter restarts from 0
Count <= (others => '0');
elsif (i_Enable = '1') then -- Increment counter value
Count <= Count + 1;
end if;
end if;
end process;
o_Count <= std_logic_vector(Count);
end Behavioral;
| gpl-3.0 | 87f4a5dcf1cedabe08a3659ecb102fe1 | 0.508588 | 4.496073 | false | false | false | false |
APastorG/APG | average_calculator/average_calculator_core_u.vhd | 1 | 7,367 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Vivado by Xilinx
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is the interface between the instantiation of an adder an its core. It exists to make it
/ possible to use external std_ulogic_vector which contain the numeric values while having modules
/ which are able to manipulate this data as fixed point types (either u_ufixed or u_sfixed).
/ As std_ulogic_vector have a natural range and the u_ufixed and u_sfixed types have an integer
/ range ('high downto 0 is the integer part and -1 downto 'low is the fractional part) it is needed
/ a solution so as to represent the negative indexes in the std_ulogic_vector. A solution is
/ adopted where the integer indexes of the fixed point types are moved to the natural space with a
/ transformation. This consists in limiting the indexes of the fixed point data to +-2**30 and
/ adding 2**30 to obtain the std_ulogic_vector's indexes. [-2**30, 2**30]->[0, 2**31]. For example,
/ fixed point indexes (3 donwto -2) would become (1073741827, 1073741822) in a std_ulogic_vector
/ Additionally, the generics' consistency and correctness are checked in here.
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.adder_pkg.all;
use work.fixed_generic_pkg.all;
use work.average_calculator_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity average_calculator_core_u is
generic(
DATA_IMM_AFTER_START_opt : boolean;
SPEED_opt : T_speed;
ROUND_STYLE_opt : T_round_style;
ROUND_TO_BIT_opt : integer_exc;
MAX_ERROR_PCT_opt : real_exc;
S : positive;
P : positive;
input_high : integer;
input_low : integer
);
port(
input : in u_ufixed_v(1 to P);
clk : in std_ulogic;
start : in std_ulogic;
valid_input : in std_ulogic;
output : out u_ufixed(average_calculator_OH(true, --UNSIGNED_2COMP_opt,
ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
S,
P,
input_high,
input_low)
downto
average_calculator_OL(true, --UNSIGNED_2COMP_opt,
ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
S,
P,
input_high,
input_low)
);
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture average_calculator_core_u1 of average_calculator_core_u is
constant INTER_HIGH : integer := average_calculator_IH(S,
P,
input_high);
constant INTER_LOW : integer := average_calculator_IL(ROUND_TO_BIT_opt,
input_low);
constant OUT_HIGH : integer := average_calculator_OH(true, --UNSIGNED_2COMP_opt,
ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
S,
P,
input_high,
input_low);
constant OUT_LOW : integer := average_calculator_OL(true, --UNSIGNED_2COMP_opt,
ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
S,
P,
input_high,
input_low);
signal inter : u_ufixed(INTER_HIGH downto INTER_LOW);
signal valid_output_inter : std_ulogic;
/*================================================================================================*/
/*================================================================================================*/
begin
adder_u1:
entity work.adder_u
generic map(
DATA_IMM_AFTER_START_opt => DATA_IMM_AFTER_START_opt,
SPEED_opt => SPEED_opt,
--MAX_POSSIBLE_BIT_opt => ,
TRUNCATE_TO_BIT_opt => ROUND_TO_BIT_opt,
S => S
)
port map(
input => input,
clk => clk,
start => start,
valid_input => valid_input,
output => inter,
valid_output => valid_output_inter
);
real_const_mult_u1:
entity work.real_const_mult_u
generic map(
SPEED_opt => SPEED_opt,
ROUND_STYLE_opt => ROUND_STYLE_opt,
ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
MULTIPLICANDS => (1 => 1.0/(S*P))
)
port map(
input => inter,
clk => clk,
valid_input => valid_output_inter,
output(1) => output,
valid_output => valid_output
);
end architecture; | mit | b243ff1a396bd5a0c643d81ae4932433 | 0.366562 | 5.340859 | false | false | false | false |
vvk/sysrek | skin_color_segm/ipcore_dir/LUT/simulation/LUT_tb_synth.vhd | 6 | 7,026 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: LUT_tb_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.LUT_TB_PKG.ALL;
ENTITY LUT_tb_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 0
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END LUT_tb_synth;
ARCHITECTURE LUT_synth_ARCH OF LUT_tb_synth IS
COMPONENT LUT_exdes
PORT (
CLK : IN STD_LOGIC := '0';
QSPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
A : IN STD_LOGIC_VECTOR(8-1-(4*0*boolean'pos(8>4)) downto 0)
:= (OTHERS => '0')
);
END COMPONENT;
CONSTANT STIM_CNT : INTEGER := if_then_else(C_ROM_SYNTH = 0, 8, 22);
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i : STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ADDR: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDR_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL QSPO: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL QSPO_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
LUT_TB_STIM_GEN_INST:ENTITY work.LUT_TB_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
A => ADDR,
DATA_IN => QSPO_R,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(STIM_CNT);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDR(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW + 1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
QSPO_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
QSPO_R <= QSPO AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDR_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDR_R <= ADDR AFTER 50 ns;
END IF;
END IF;
END PROCESS;
DMG_PORT: LUT_exdes PORT MAP (
CLK => CLKA,
QSPO => QSPO,
A => ADDR_R
);
END ARCHITECTURE;
| gpl-2.0 | b41e0164fd8041f6935dd3209078375b | 0.567179 | 3.814332 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/nes_gamepad.vhd | 2 | 4,740 | ---------------------------------------------------------------------------
-- NES-Controller Module
---------------------------------------------------------------------------
-- This file is a part of "Aeon Lite" project
-- Dmitriy Schapotschkin aka ILoveSpeccy '2014
-- [email protected]
-- Project homepage: www.speccyland.net
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
------------------
-- Bit - Button --
-- (1 = pressed)
------------------
-- 7 A
-- 6 B
-- 5 Select
-- 4 Start
-- 3 Up
-- 2 Down
-- 1 Left
-- 0 Right
------------------
entity nes_gamepad is
generic (
CLK_FREQ : integer := 25000000;
TICK_FREQ : integer := 20000 );
port (
CLK : in std_logic;
RESET : in std_logic;
JOY_CLK : out std_logic;
JOY_LOAD : out std_logic;
JOY_DATA0 : in std_logic;
JOY_DATA1 : in std_logic;
JOY0_BUTTONS : out std_logic_vector(7 downto 0);
JOY1_BUTTONS : out std_logic_vector(7 downto 0);
JOY0_CONNECTED : out std_logic; -- 1 when gamepad connected
JOY1_CONNECTED : out std_logic );
end nes_gamepad;
architecture RTL of nes_gamepad is
signal TICK : integer range 0 to (CLK_FREQ / TICK_FREQ);
signal STATE : integer range 0 to 17;
signal DATA0 : std_logic_vector(7 downto 0);
signal DATA1 : std_logic_vector(7 downto 0);
begin
process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
STATE <= 0;
JOY_CLK <= '0';
JOY_LOAD <= '0';
TICK <= 0;
JOY0_BUTTONS <= "00000000";
JOY0_BUTTONS <= "00000000";
JOY0_CONNECTED <= '0';
JOY1_CONNECTED <= '0';
else
TICK <= TICK + 1;
if TICK = (CLK_FREQ / TICK_FREQ) then
TICK <= 0;
STATE <= STATE + 1;
case STATE is
when 0 =>
JOY_LOAD <= '1';
when 1 =>
JOY_LOAD <= '0';
DATA0(7) <= JOY_DATA0;
DATA1(7) <= JOY_DATA1;
when 2 | 4 | 6 | 8 | 10 | 12 | 14 | 16 =>
JOY_CLK <= '1';
when 3 =>
JOY_CLK <= '0';
DATA0(6) <= JOY_DATA0;
DATA1(6) <= JOY_DATA1;
when 5 =>
JOY_CLK <= '0';
DATA0(5) <= JOY_DATA0;
DATA1(5) <= JOY_DATA1;
when 7 =>
JOY_CLK <= '0';
DATA0(4) <= JOY_DATA0;
DATA1(4) <= JOY_DATA1;
when 9 =>
JOY_CLK <= '0';
DATA0(3) <= JOY_DATA0;
DATA1(3) <= JOY_DATA1;
when 11 =>
JOY_CLK <= '0';
DATA0(2) <= JOY_DATA0;
DATA1(2) <= JOY_DATA1;
when 13 =>
JOY_CLK <= '0';
DATA0(1) <= JOY_DATA0;
DATA1(1) <= JOY_DATA1;
when 15 =>
JOY_CLK <= '0';
DATA0(0) <= JOY_DATA0;
DATA1(0) <= JOY_DATA1;
when 17 =>
JOY_CLK <= '0';
JOY0_BUTTONS <= "00000000";
JOY1_BUTTONS <= "00000000";
JOY0_CONNECTED <= '0';
JOY1_CONNECTED <= '0';
STATE <= 0;
if DATA0 /= "00000000" then -- gamepad connected
JOY0_BUTTONS <= not DATA0;
JOY0_CONNECTED <= '1';
end if;
if DATA1 /= "00000000" then -- gamepad connected
JOY1_BUTTONS <= not DATA1;
JOY1_CONNECTED <= '1';
end if;
when OTHERS =>
NULL;
end case;
end if;
end if;
end if;
end process;
end RTL;
| gpl-3.0 | 2914b1f6ff32d399633ce8d0bce8b49b | 0.335021 | 4.467484 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_00700_bad.vhd | 1 | 3,125 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-01 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_00700_bad.vhd
-- File Creation date : 2015-04-01
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Preservation of signal name: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pkg_HBK.all;
entity STD_00700_bad is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end STD_00700_bad;
--CODE
architecture Behavioral of STD_00700_bad is
signal temp : std_logic; -- D Flip-Flop input signal
signal D : std_logic; -- First Flip-Flop output
signal Q : std_logic; -- Block output
begin
temp <= i_D;
DFlipFlop1 : DFlipFlop
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_D => temp,
o_Q => D,
o_Q_n => open
);
P_FlipFlop : process(i_Reset_n, i_Clock)
begin
if (i_Reset_n = '0') then
Q <= '0';
elsif (rising_edge(i_Clock)) then
Q <= D;
end if;
end process;
end Behavioral;
--CODE
| gpl-3.0 | 05675d60be1746170e772c389d84af0c | 0.46848 | 4.426346 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/zpu/tb/zpucore_tb.vhd | 1 | 2,125 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std_developerskit ; -- used for to_string
-- use std_developerskit.std_iopak.all;
entity zpucore_tb is
end;
architecture rtl of zpucore_tb is
constant CLK_A_PERIOD : time := 1 us / (1.79*32);
signal CLK_A : std_logic;
signal reset_n : std_logic;
signal ZPU_FETCH : std_logic;
signal ZPU_32BIT_WRITE_ENABLE : std_logic;
signal ZPU_16BIT_WRITE_ENABLE : std_logic;
signal ZPU_8BIT_WRITE_ENABLE : std_logic;
signal ZPU_READ_ENABLE : std_logic;
signal ZPU_MEMORY_DATA : std_logic_vector(31 downto 0);
signal ZPU_MEMORY_READY : std_logic;
signal ZPU_ADDR_ROM : std_logic_vector(15 downto 0);
signal ZPU_ROM_DATA : std_logic_vector(31 downto 0);
begin
p_clk_gen_a : process
begin
clk_a <= '1';
wait for CLK_A_PERIOD/2;
clk_a <= '0';
wait for CLK_A_PERIOD - (CLK_A_PERIOD/2 );
end process;
reset_n <= '0', '1' after 1000ns;
zpu1 : entity work.zpucore
GENERIC MAP
(
platform => 42
)
PORT MAP
(
CLK => CLK_A,
RESET_N => RESET_N,
-- TODO - wire up a simple ram...
ZPU_FETCH => ZPU_FETCH,
ZPU_32BIT_WRITE_ENABLE => ZPU_32BIT_WRITE_ENABLE,
ZPU_16BIT_WRITE_ENABLE => ZPU_16BIT_WRITE_ENABLE,
ZPU_8BIT_WRITE_ENABLE => ZPU_8BIT_WRITE_ENABLE,
ZPU_READ_ENABLE => ZPU_READ_ENABLE,
ZPU_MEMORY_DATA => ZPU_MEMORY_DATA,
ZPU_MEMORY_READY => ZPU_MEMORY_READY,
-- TODO - wire up a simple rom
ZPU_ADDR_ROM => ZPU_ADDR_ROM,
ZPU_ROM_DATA => ZPU_ROM_DATA,
ZPU_SD_DAT0 => '1',
ZPU_SD_CLK => open,
ZPU_SD_CMD => open,
ZPU_SD_DAT3 => open,
-- SIO
ZPU_POKEY_ENABLE => '1',
ZPU_SIO_TXD => open,
ZPU_SIO_RXD => '1',
ZPU_SIO_COMMAND => '1',
-- external control
ZPU_IN1 => x"11345678",
ZPU_IN2 => x"22345678",
ZPU_IN3 => x"33345678",
ZPU_IN4 => x"44345678",
-- ouputs - e.g. Atari system control, halt, throttle, rom select
ZPU_OUT1 => open,
ZPU_OUT2 => open,
ZPU_OUT3 => open,
ZPU_OUT4 => open
);
end rtl;
| gpl-3.0 | 584ebd0f8d0b91a390c74af0e284ee9c | 0.621647 | 2.607362 | false | false | false | false |
APastorG/APG | real_const_mult/mmcm_pkg.vhd | 1 | 72,023 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented by
/ Altera and Xilinx in their software.
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ Package to implement the multiplierless multiple constant multiplier proposed by Voronenko and
/ Püschel. The solutions are written to a file during simulation and read from that file during
/ synthesis.
/
**************************************************************************************************/
library std;
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.fixed_float_types.all;
use work.fixed_generic_pkg.all;
use work.real_const_mult_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
package mmcm_pkg is
generic(
MAX_TARGET : positive; --the highest constant
FILE_PATH : string); --the name of the file where the solution will be saved
constant UPPER_BITS : positive := 1+integer(ceil(log2(real(MAX_TARGET))));
constant UPPER_LIMIT : positive := positive(2.0**(UPPER_BITS)-1);
/* data structures 0 */
/**************************************************************************************************/
--vertex node type: used to describe the solution
--one node: u<<l1 + (-1)^s*v<<l2 = w
type vertex_node;
type vertex_node_access is access vertex_node;
type vertex_node is record
w : positive;
u : positive;
l1 : natural;
v : positive;
l2 : natural;
s : boolean; --true for +, false for -
next_node : vertex_node_access;
end record;
--vertex type
type vertex;
type vertex_access is access vertex;
type vertex is record
size : natural;
head : vertex_node_access;
tail : vertex_node_access;
end record;
----------------------------------------------------------------------------------------------------
--binary search tree node type
type bst_node;
type bst_node_access is access bst_node;
type bst_node is record
value : positive;
left : bst_node_access;
right : bst_node_access;
end record;
--binary search tree type
type bst;
type bst_access is access bst;
type bst is record
size : natural; --number of elements
root : bst_node_access;
end record;
----------------------------------------------------------------------------------------------------
--linked list node type
type llist_node;
type llist_node_access is access llist_node;
type llist_node is record
value : positive;
next_node : llist_node_access;
end record;
--linked list type
type llist;
type llist_access is access llist;
type llist is record
head : llist_node_access;
tail : llist_node_access;
end record;
----------------------------------------------------------------------------------------------------
--line access types
type line_access is access line;
type line_access_v is array (integer range <>) of line_access;
/* binary search trees procedures 1 */
/**************************************************************************************************/
--insert a value in a subtree
procedure insert(
node : inout bst_node_access;
new_value : in positive);
--inserts a value in a tree
procedure insert(
tree : inout bst_access;
new_value : in positive);
--rotates pointed node to the left of its right child
procedure rotate_left(
subtree : inout bst_node_access);
--rotates pointed node to the right of its left child
procedure rotate_right(
subtree : inout bst_node_access);
--deletes only one node, reconnecting its children to the rest of the tree
procedure delete_node(
node : inout bst_node_access);
procedure delete_left(
node : inout bst_node_access);
procedure delete_right(
node : inout bst_node_access);
--deletes the first node it finds whose value is the same as the one given
procedure delete_value(
tree : inout bst_access;
value : in positive);
--deletes the selected node and all its children
procedure delete_subtree(
node : inout bst_node_access);
--deletes a whole tree
procedure delete_tree(
tree : inout bst_access);
--looks for a value in a subtree, returns 0 in variable value if not found
procedure search(
variable node : in bst_node_access;
value : inout natural);
--looks for a value in a tree, returns 0 in variable value if not found
procedure search(
variable tree : in bst_access;
value : inout natural);
--returns the maximum value in a tree; 0 if it is empty
procedure max(
variable node : in bst_node_access;
max : out natural);
--calculates the height of a subtree
procedure height(
variable subtree : in bst_node_access;
variable actual : in natural; --must be 1 when called
variable max : inout natural);
--calculates the height of a tree
procedure height(
variable tree : in bst_access;
variable max_height : inout natural);
/* linked lists procedures 3 */
/**************************************************************************************************/
procedure insert_in_position( --inserts new value before the specified node
node : inout llist_node_access;
new_value : in positive);
procedure insert( --inserts new value in the tail position
llist : inout llist_access;
new_value : in positive);
procedure insert_ordered( --without repetitions
llist : inout llist_access;
new_value : in positive);
procedure delete_node( --deletes the assigned node of a linked list
node : inout llist_node_access);
procedure delete_value(
llist : inout llist_access;
value : in positive);
--returns 0 in in_value if not found, it leaves it unchanged if found
procedure search(
variable llist : in llist_access;
in_value : inout natural);
procedure empty( --empties a llist
llist : inout llist_access);
procedure union(
dest : inout llist_access;
variable orig : in llist_access);
procedure difference( --deletes the values in a which are also in b
a : inout llist_access;
variable b : in llist_access);
/* message procedures 4 */
/**************************************************************************************************/
procedure write_bst_recursive(
variable tree : in bst_node_access;
max_height : in positive;
h_actual : inout natural; --height_iterator
msg_v : inout line_access_v);
procedure write(
message : inout line;
variable node : in bst_node_access;
max_height : in positive);
procedure write(
message : inout line;
variable tree : in bst_access);
procedure msg_debug(
variable tree : in bst_access;
name : in string);
----------------------------------------------------------------------------------------------------
procedure write(
message : inout line;
variable node : in llist_node_access);
procedure write(
message : inout line;
variable list : in llist_access);
procedure msg_debug(
variable list : in llist_access;
name : in string);
----------------------------------------------------------------------------------------------------
procedure msg_separator;
/* MMCM procedures 5 */
/**************************************************************************************************/
procedure VorPus(
target : positive_v);
end package;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
Package body mmcm_pkg is
/********************************************************************************************** 1 */
procedure insert(
node : inout bst_node_access;
new_value : in positive)
is
begin
if node = null then
node := new bst_node'(new_value, null, null);
else
if new_value > node.value then
if node.right = null then
node.right := new bst_node'(new_value, null, null);
else
node := node.right;
insert(node, new_value);
end if;
elsif new_value < node.value then
if node.left = null then
node.left := new bst_node'(new_value, null, null);
else
node := node.left;
insert(node, new_value);
end if;
else
node := null; --if nothing is inserted return null pointer
return;
end if;
end if;
end procedure;
procedure insert(
tree : inout bst_access;
new_value : in positive)
is
variable aux : bst_node_access := tree.root;
begin
insert(aux, new_value);
if aux /= null then --if the value was inserted (it wasn't already in the tree)
tree.size := tree.size + 1;
if tree.root = null then --inserted into an empty tree
tree.root := aux;
end if;
end if;
end procedure;
procedure insert(
tree : inout bst_access;
variable list : in llist_access)
is
variable iter : llist_node_access;
begin
if tree /= null then
if list /= null then
iter := list.head;
while iter /= null loop
insert(tree, iter.value);
iter := iter.next_node;
end loop;
end if;
end if;
end procedure;
procedure rotate_left(
subtree : inout bst_node_access)
is
variable aux : bst_node_access;
begin
if subtree /= null then
if subtree.right /= null then
aux := subtree.right;
subtree.right := aux.left;
aux.left := subtree;
subtree := aux;
end if;
end if;
end procedure;
procedure rotate_right(
subtree : inout bst_node_access)
is
variable aux : bst_node_access;
begin
if subtree /= null then
if subtree.left /= null then
aux := subtree.left;
subtree.left := aux.right;
aux.right := subtree;
subtree := aux;
end if;
end if;
end procedure;
procedure delete_node(
node : inout bst_node_access)
is
variable aux : bst_node_access;
begin
if node.left = null and node.right = null then --if no children, delete node
deallocate(node);
node := null;
elsif node.left = null then --right child replaces parent if left child doesn't exist
aux := node;
node := node.right;
deallocate(aux);
elsif node.right = null then --left child replaces parent if left child doesn't exist
aux := node;
node := node.left;
deallocate(aux);
else --both children are present: introduce rightmost from the left subtree
aux := node.left;
if aux.right = null then --left child doesn't have right child
aux.right := node.right;
deallocate(node);
node := aux;
else --move to the right child until the node before the last
while aux.right.right /= null loop
aux := aux.right;
end loop;
node.value := aux.right.value;
aux.right := aux.right.left;
deallocate(aux.right);
end if;
end if;
end procedure;
procedure delete_left(
node : inout bst_node_access) --the real pointer from the linked list(not a copy)
is
begin
delete_node(node.left);
end procedure;
procedure delete_right(
node : inout bst_node_access) --the real pointer from the linked list(not a copy)
is
variable aux : bst_node_access;
begin
delete_node(node.right);
end procedure;
procedure delete_value(
tree : inout bst_access;
value : in positive)
is
variable parent : bst_node_access;
variable node : bst_node_access;
variable dir : integer := 0;
begin
if tree /= null then
node := tree.root;
while node /= null loop --while tree is not empty
if node.value = value then
if parent = null then --if deleting root
if node.right /= null then --if right child exists
node.value:= node.right.value; --put its value in root
delete_node(node.right); --and delete right child
tree.size := tree.size - 1;
elsif node.left /= null then --if left child exists
node.value:= node.left.value; --put its value in root
delete_node(node.left); --and delete left child
tree.size := tree.size - 1;
else --if there are no more nodes in the tree
deallocate(tree.root);
tree.size := 0;
tree.root := null; --delete everything
end if;
else
if dir = -1 then
delete_left(parent);
tree.size := tree.size - 1;
else --dir=1
delete_right(parent);
tree.size := tree.size - 1;
end if;
return;
end if;
elsif node.value < value then --not deleting the root
parent := parent.left when dir=-1 else
parent.right when dir=1 else
tree.root;
node := node.right;
dir := 1;
else
parent := parent.left when dir=-1 else
parent.right when dir=1 else
tree.root;
node := node.left;
dir := -1;
end if;
end loop;
elsif DEBUGGING then
report "delete_value(tree, value) couldn't find the value to delete (" & image(value) & ")."
severity warning;
end if;
end procedure;
--doesn't update the value of tree.size (not possible from within)
procedure delete_subtree(
node : inout bst_node_access)
is
begin
if node.left /= null then --post-order traversal: delete only when all descendents are deleted
delete_subtree(node.left);
end if;
if node.right /= null then
delete_subtree(node.right);
end if;
delete_node(node);
end procedure;
procedure delete_tree(
tree : inout bst_access)
is
begin
delete_subtree(tree.root);
tree.size := 0;
end procedure;
--looks for a value in a subtree, returns 0 in variable value if not found
procedure search(
variable node : in bst_node_access;
value : inout natural)
is
begin
if node = null then
value := 0;
return;
elsif value > node.value then
search(node.right, value);
elsif value < node.value then
search(node.left, value);
else
return;
end if;
end procedure;
--looks for a value in a tree, returns 0 in variable value if not found
procedure search(
variable tree : in bst_access;
value : inout natural)
is
variable aux : bst_node_access;
begin
if tree /= null then
aux := tree.root;
search(aux, value); --after this, value is 0 if not found
end if;
end procedure;
--returns the biggest number in the subtree, 0 if the subtree is empty
procedure max(
variable node : in bst_node_access;
max : out natural)
is
variable node_ite : bst_node_access := node;
begin
max := 0;
while node_ite /= null loop
max := node_ite.value;
node_ite := node_ite.right;
end loop;
end procedure;
procedure height(
variable subtree : in bst_node_access;
variable actual : in natural;
variable max : inout natural)
is
variable aux : natural;
begin
if subtree /= null then
if subtree.left /= null then
aux := actual + 1;
if aux > max then
max := aux;
end if;
height(subtree.left, aux, max);
end if;
if subtree.right /= null then
aux := actual + 1;
if aux > max then
max := aux;
end if;
height(subtree.right, aux, max);
end if;
end if;
end procedure;
procedure height(
variable tree : in bst_access;
variable max_height : inout natural)
is
variable max : natural := 0;
variable actual : natural;
begin
if tree /= null then
if tree.root /= null then
actual := 1;
max := 1;
height(tree.root, actual, max);
end if;
end if;
max_height := max;
end procedure;
/********************************************************************************************** 3 */
--inserts before the assigned node
procedure insert_in_position(
node : inout llist_node_access;
new_value : in positive)
is
variable aux : llist_node_access;
begin
if node = null then
report "insert_in_position(llist_node_access, positive) : llist_node_access is null"
severity warning;
else
aux := new llist_node'(node.value, node.next_node);
node.value := new_value;
node.next_node := aux;
end if;
end procedure;
--inserts new value in the tail
procedure insert(
llist : inout llist_access;
new_value : in positive)
is
begin
if llist.head = null then
llist.head := new llist_node'(new_value, null);
llist.tail := llist.head;
else
llist.tail.next_node := new llist_node'(new_value, null);
llist.tail := llist.tail.next_node;
end if;
end procedure;
--inserts all values in a positive vector into a linked list without repetitions
procedure insert(
llist : inout llist_access;
vector : in positive_v)
is
begin
for i in vector'range loop
insert_ordered(llist, vector(i));
end loop;
end procedure;
procedure insert_ordered( --without repetitions, ordered from lowest(head) to highest(tail)
llist : inout llist_access;
new_value : in positive)
is
variable node_ite : llist_node_access := llist.head;
begin
while1:
while node_ite /= null loop
if node_ite.value > new_value then
exit while1;
elsif node_ite.value = new_value then
return;
end if;
node_ite := node_ite.next_node;
end loop;
if node_ite /= null then --if not last position (=> at least one element)
insert_in_position(node_ite, new_value);
if llist.tail.next_node /= null then --if the tail is not in the tail anymore
llist.tail := llist.tail.next_node;
end if;
if llist.head = llist.tail then --if the list only had one element
llist.tail := llist.head.next_node;
end if;
else --insert in the tail
insert(llist, new_value); --this automatically updates .tail
end if;
end procedure;
--deleted a node and returns the pointer to the next one (or null if it was the tail)
procedure delete_node( --deletes the given node (must be the access variable of the previous node)
node : inout llist_node_access)
is
variable aux : llist_node_access;
begin
aux := node;
node := node.next_node;
deallocate(aux);
end procedure;
procedure delete_value( --deletes a value in a linked list, warns if it doesn't exist
llist : inout llist_access;
value : in positive)
is
variable aux : llist_node_access;
variable node_ite : llist_node_access := llist.head;
begin
if node_ite = null then --if empty list
msg_debug("delete_value(llist, value) couldn't find the value to delete (" & image(value) & ").");
return;
end if;
--value found in the first node
if llist.head.value = value then --the value is in the first node
if llist.head.next_node = null then --the list has only one node
deallocate(llist.head);
llist.head := null;
llist.tail := null;
return;
else --the list has more than a node
aux := llist.head;
llist.head := llist.head.next_node;
deallocate(aux);
return;
end if;
end if;
--traverse the list until finding the desired value
while node_ite.next_node /= null loop --the real access variable(needed to re-establish the connection)
if node_ite.next_node.value = value then
delete_node(node_ite.next_node);
if node_ite.next_node = null then --if we deleted the last node, update tail
llist.tail := node_ite;
end if;
return;
end if;
node_ite:= node_ite.next_node;
end loop;
msg_debug("delete_value(llist, value) couldn't find the value to delete (" & image(value) & ").");
end procedure;
procedure search( --changes in_value parameter to 0 if the element is not in the linked list
variable llist : in llist_access;
in_value : inout natural)
is
variable node_ite : llist_node_access := llist.head;
begin
while node_ite /= null loop
if node_ite.value = in_value then
return; --value in the linked list
end if;
node_ite := node_ite.next_node;
end loop;
in_value := 0; --value not in the linked list
end procedure;
procedure empty( --empty a llist
llist : inout llist_access)
is
variable node_ite : llist_node_access := llist.head;
variable aux : llist_node_access;
begin
if llist.head.next_node = null then
deallocate(llist.head);
llist.head := null;
llist.tail := null;
return;
end if;
while node_ite.next_node /= null loop
aux := node_ite;
node_ite := node_ite.next_node;
deallocate(aux);
end loop;
deallocate(node_ite);
llist.head := null;
llist.tail := null;
end procedure;
procedure union( --adds the values in orig to dest
dest : inout llist_access;
variable orig : in llist_access)
is
variable orig_ite : llist_node_access := orig.head;
begin
while orig_ite /= null loop
insert_ordered(dest, orig_ite.value);
orig_ite := orig_ite.next_node;
end loop;
end procedure;
procedure difference( --deletes the values in a which are also in b
a : inout llist_access;
variable b : in llist_access)
is
variable a_ite : llist_node_access := a.head;
variable b_ite : llist_node_access := b.head;
begin
if a_ite /= null then
--check from the second to the tail
aloop: while a_ite.next_node /= null loop
while b_ite /= null loop
if a_ite.next_node.value = b_ite.value then
delete_value(a, b_ite.value);
next aloop; --next loop of a without getting next node
end if;
b_ite := b_ite.next_node;
end loop;
a_ite := a_ite.next_node;
end loop;
end if;
--check head node
b_ite := b.head;
if b_ite /= null then
if a.head.value = b_ite.value then
delete_value(a, b_ite.value);
end if;
end if;
end procedure;
/********************************************************************************************** 4 */
procedure write(
message : inout line;
variable node : in vertex_node_access)
is
begin
if node /= null then
if node.w=1 then
write(message, string'("1") & LF);
else
write(message, string'( image(node.w) & " = " &
image(node.u) & ite(node.l1=0, " ","<<" & image(node.l1)) &
ite(node.s, " - ", " + ") &
image(node.v) & ite(node.l2=0, " ", "<<" & image(node.l2))
)
);
if node.next_node /= null then
write(message, LF);
end if;
end if;
else
write(message, string'("-> empty vertex"));
end if;
end procedure;
procedure write(
message : inout line;
variable vertex : in vertex_access)
is
variable ite : vertex_node_access;
begin
if vertex /= null then
ite := vertex.head;
while ite /= null loop
write(message, ite);
ite := ite.next_node;
end loop;
end if;
end procedure;
procedure msg_debug(
variable vertex : in vertex_access;
name : in string)
is
variable message : line;
begin
if DEBUGGING then
write(message, "**************************" & LF);
write(message, name & LF);
write(message, vertex);
writeline(OUTPUT, message);
end if;
end procedure;
procedure msg(
variable vertex : in vertex_access;
name : in string)
is
variable message : line;
begin
write(message, "**************************" & LF);
write(message, name & LF);
write(message, vertex);
writeline(OUTPUT, message);
end procedure;
----------------------------------------------------------------------------------------------------
function length(
number : positive)
return positive is
begin
return positive(ceil(log10(real(number+1))));
end function;
procedure write_bst_recursive(
variable tree : in bst_node_access;
max_height : in positive;
h_actual : inout natural; --height_iterator
msg_v : inout line_access_v)
is
variable x : natural;
begin
if tree /= null then
if tree.left /= null then
x := h_actual + 1;
write_bst_recursive(tree.left, max_height, x, msg_v);
end if;
for i in 1 to max_height loop
if i = h_actual then
write(msg_v(i).all, to_string(tree.value));
else
for j in 1 to length(tree.value) loop
write(msg_v(i).all, string'(" "));
end loop;
end if;
end loop;
if tree.right /= null then
x := h_actual + 1;
write_bst_recursive(tree.right, max_height, x, msg_v);
end if;
end if;
end procedure;
procedure write(
message : inout line;
variable node : in bst_node_access;
max_height : in positive)
is
variable h_actual : natural := 1;
variable message_v : line_access_v(1 to max_height);
begin
if node = null then
write(message, string'("empty tree"));
else
for i in 1 to max_height loop
message_v(i) := new line;
end loop;
write_bst_recursive(node, max_height, h_actual, message_v);
for i in 1 to max_height loop
write(message, message_v(i).all.all);
if i /= max_height then
write(message, LF);
end if;
end loop;
end if;
end procedure;
procedure write(
message : inout line;
variable tree : in bst_access)
is
variable max_height : positive;
begin
if tree /= null then
height(tree, max_height);
write(message, tree.root, max_height);
end if;
end procedure;
procedure msg_debug(
variable tree : in bst_access;
name : in string)
is
variable message : line;
begin
if DEBUGGING then
write(message, "**************************" & LF);
write(message, name & " (size " & image(tree.size) & ")" & LF);
if tree.root /= null then
write(message, tree);
else
write(message, string'("(empty)"));
end if;
writeline(OUTPUT, message);
end if;
end procedure;
procedure msg(
variable tree : in bst_access;
name : in string)
is
variable message : line;
begin
write(message, "**************************" & LF);
write(message, name & " (size " & image(tree.size) & ")" & LF);
if tree.root /= null then
write(message, tree);
else
write(message, string'("(empty)"));
end if;
writeline(OUTPUT, message);
end procedure;
----------------------------------------------------------------------------------------------------
procedure write(
message : inout line;
variable node : in llist_node_access)
is
variable ite : llist_node_access := node;
begin
if node /= null then
while ite /= null loop
write(message, string'(" -> ") & image(ite.value));
ite := ite.next_node;
end loop;
else
write(message, string'("-> empty list"));
end if;
end procedure;
procedure write(
message : inout line;
variable list : in llist_access)
is
begin
write(message, list.head);
end procedure;
procedure msg_debug(
variable list : in llist_access;
name : in string)
is
variable message : line;
begin
if DEBUGGING then
write(message, "**************************" & LF);
write(message, name & LF);
write(message, list);
writeline(OUTPUT, message);
end if;
end procedure;
procedure msg(
variable list : in llist_access;
name : in string)
is
variable message : line;
begin
write(message, "**************************" & LF);
write(message, name & LF);
write(message, list);
writeline(OUTPUT, message);
end procedure;
----------------------------------------------------------------------------------------------------
procedure msg_separator
is
variable message : line;
begin
write(message, string'("**************************"));
writeline(OUTPUT, message);
end procedure;
/********************************************************************************************** 5 */
function number_of_iterations(
a : positive;
b : positive)
return positive is
begin
return maximum(integer(floor(log2((0.000000001+real(UPPER_LIMIT+a))/real(b)))), 1);
--0.000000001 added because function log2 sometimes returns something like log2(128)=6.999999999
end function;
--generates the A_* (R,W) : vertex fundamental set
-- it directly generates the ordered linked list that contains the values of C^1
procedure generateC1(
result : inout llist_access)
is
variable aux : integer;
begin
for i in 1 to number_of_iterations(1, 1) loop--start at 1 instead of 0 because values when i=0 are included in i=1
-- (just number 1) and we avoid having to discard even values as they all will be odd
aux := integer(2.0**i) - 1;
insert_ordered(result, aux);
aux := aux + 2; -- = integer(2.0**i) + 1
if aux< UPPER_LIMIT then
insert_ordered(result, aux);
end if;
end loop;
end procedure;
--generates the S U A_*(R,W)-W : vertex fundamental set
procedure compute_d1_successors(
s_set : inout bst_access;
variable r_set : in llist_access;
variable w_set : in llist_access)
is
variable r_ite : llist_node_access := r_set.head;
variable w_ite : llist_node_access := w_set.head;
variable aux : natural;
variable r : positive;
variable w : positive;
variable iterations : positive;
begin
while r_ite /= null loop
while w_ite /= null loop
r := r_ite.value;
w := w_ite.value;
iterations := number_of_iterations(w, r);
for i in 0 to iterations loop
aux := w + r*integer(2.0**i);
if aux < UPPER_LIMIT then
aux := reduce_to_odd(aux);
insert(s_set, aux);
end if;
aux := abs(integer(w) - integer(r*integer(2.0**i)));
if aux /= 0 then
insert(s_set, reduce_to_odd(aux)); --reduce_to_odd is here to prevent reduce_to_odd(0)
end if;
end loop;
if r /= w then
iterations := number_of_iterations(r, w);
for i in 0 to iterations loop
aux := r + w*integer(2.0**i);
if aux < UPPER_LIMIT then
aux := reduce_to_odd(aux);
insert(s_set, aux);
end if;
aux := abs(integer(r) - integer(w*integer(2.0**i)));
if aux /= 0 then
insert(s_set, reduce_to_odd(aux)); --reduce_to_odd is here to prevent reduce_to_odd(0)
end if;
end loop;
end if;
w_ite := w_ite.next_node;
end loop;
w_ite := w_set.head;
r_ite := r_ite.next_node;
end loop;
--delete W from S
w_ite := r_set.head;
while w_ite /= null loop
delete_value(s_set, w_ite.value);
w_ite := w_ite.next_node;
end loop;
end procedure;
--modified Day-Stout-Warren algorithm to balance a binary search tree
--it only performs the second part of the algorithm (we assume the received tree is already a listlike tree)
--it will be used only after inserting C1 and at the end it performs an additional rotate left compared with
-- the original algorithm so as to compensate the fact that the inserted values are biased towards low values
--With this change, after inserting successive successors, the tree will be more balanced
procedure dsw(
s_set : inout bst_access;
n : in natural)
is
variable s_ite : bst_node_access;
variable m : natural;
variable aux : natural := 0;
begin
if s_set /= null then
m := natural((2.0**log2(real(n)+1))-1);
rotate_left(s_set.root);
aux := aux + 1;
if n > m + 1 then
for i in 1 to n - m - 1 loop
s_ite := s_set.root;
for j in 1 to i loop
s_ite := s_ite.right;
end loop;
rotate_left(s_ite.right);
aux := aux + 1;
end loop;
end if;
m := m - aux;
m := natural(floor(real(m)/2));
while m > 1 loop
for i in 1 to m loop
if i = 1 then
rotate_left(s_set.root);
elsif i = 2 then
rotate_left(s_set.root.right);
else
s_ite := s_set.root;
for j in 1 to i-2 loop
s_ite := s_ite.right;
end loop;
rotate_left(s_ite.right);
end if;
end loop;
m := natural(floor(real(m)/2));
end loop;
if s_ite /= null then
rotate_left(s_ite.right);
end if;
end if;
end procedure;
----------------------------------------------------------------------------------------------------
--test1, distance-1, (t/C1 = s)
procedure test_1(
variable C1 : in llist_access;
s : in positive;
t : in positive;
result : out boolean)
is
variable value : natural;
begin
if t mod s = 0 then --only if the division is exact
value := t / s;
search(C1, value);
if value /= 0 then --it was found
result := true;
return;
end if;
end if;
result := false;
end procedure;
--test2, distance-2, (A_*(t,R) = s)
procedure test_2(
variable r_set : in llist_access;
s : in positive;
t : in positive;
result : out boolean)
is
variable r_ite : llist_node_access := r_set.head;
variable aux : natural;
variable r : positive;
variable iterations : positive;
begin
while r_ite /= null loop
r := r_ite.value;
iterations := number_of_iterations(t, r);
for i in 0 to iterations loop
aux := t + r*integer(2.0**i);
if aux < UPPER_LIMIT then
aux := reduce_to_odd(aux);
if aux = s then
result := true;
return;
end if;
end if;
aux := abs(integer(t) - integer(r*integer(2.0**i)));
if aux /= 0 then
aux := reduce_to_odd(aux); --reduce_to_odd is here to prevent reduce_to_odd(0)
if aux = s then
result := true;
return;
end if;
end if;
end loop;
if r /= t then
iterations := number_of_iterations(r, t);
for i in 0 to iterations loop
aux := r + t*integer(2.0**i);
if aux < UPPER_LIMIT then
aux := reduce_to_odd(aux);
if aux = s then
result := true;
return;
end if;
end if;
aux := abs(integer(r) - integer(t*integer(2.0**i)));
if aux /= 0 then
aux := reduce_to_odd(aux); --reduce_to_odd is here to prevent reduce_to_odd(0)
if aux = s then
result := true;
return;
end if;
end if;
end loop;
end if;
r_ite := r_ite.next_node;
end loop;
result := false;
end procedure;
--test3, distance-3, (t/C2 = s)
procedure test_3(
variable C1 : in llist_access;
s : in positive;
t : in positive;
result : out boolean)
is
variable value : natural;
variable aux : natural;
variable ite : llist_node_access := C1.head;
begin
if t mod s = 0 then --only if the division is exact
value := t / s;
while ite /= null loop
if value mod ite.value = 0 then
aux := value/ite.value;
search(C1, aux);
if aux /= 0 then --it was found
result := true;
return;
end if;
end if;
ite := ite.next_node;
end loop;
end if;
result := false;
end procedure;
--test4, distance-3, (A_*(t/C1,R) = s)
procedure test_4(
variable C1 : in llist_access;
variable r_set : in llist_access;
s : in positive;
t : in positive;
result : out boolean)
is
variable r_ite : llist_node_access := r_set.head;
variable c1_ite : llist_node_access := C1.head;
variable aux1, aux2 : natural;
variable r, c : positive;
variable iterations : positive;
begin
while r_ite /= null loop
r := r_ite.value;
while c1_ite /= null loop
c := c1_ite.value;
if t mod c = 0 then
aux1 := t/c;
iterations := number_of_iterations(aux1, r);
for i in 0 to iterations loop
aux2 := aux1 + r*integer(2.0**i);
if aux2 < UPPER_LIMIT then
aux2 := reduce_to_odd(aux2);
if aux2 = s then
result := true;
return;
end if;
end if;
aux2 := abs(integer(aux1) - integer(r*integer(2.0**i)));
if aux2 /= 0 then
aux2 := reduce_to_odd(aux2); --reduce_to_odd is here to prevent reduce_to_odd(0)
if aux2 = s then
result := true;
return;
end if;
end if;
end loop;
if r /= aux1 then
iterations := number_of_iterations(r, aux1);
for i in 0 to iterations loop
aux2 := r + aux1*integer(2.0**i);
if aux2 < UPPER_LIMIT then
aux2 := reduce_to_odd(aux2);
if aux2 = s then
result := true;
return;
end if;
end if;
aux2 := abs(integer(r) - integer(aux1*integer(2.0**i)));
if aux2 /= 0 then
aux2 := reduce_to_odd(aux2); --reduce_to_odd is here to prevent reduce_to_odd(0)
if aux2 = s then
result := true;
return;
end if;
end if;
end loop;
end if;
end if;
c1_ite := c1_ite.next_node;
end loop;
r_ite := r_ite.next_node;
end loop;
result := false;
end procedure;
--test5, distance-3, (A_*(t,R)/C1 = s)
procedure test_5(
variable C1 : in llist_access;
variable r_set : in llist_access;
s : in positive;
t : in positive;
result : out boolean)
is
variable r_ite : llist_node_access := r_set.head;
variable c1_ite : llist_node_access := C1.head;
variable aux : natural;
variable r, c : positive;
variable iterations : positive;
begin
while r_ite /= null loop
r := r_ite.value;
iterations := number_of_iterations(t, r);
for i in 0 to iterations loop
aux := t + r*integer(2.0**i);
while c1_ite /= null loop
c := c1_ite.value;
if aux mod c = 0 then
c := aux / c;
if c < UPPER_LIMIT then
c := reduce_to_odd(c);
if c = s then
result := true;
return;
end if;
end if;
end if;
c1_ite := c1_ite.next_node;
end loop;
c1_ite := C1.head;
aux := abs(integer(t) - integer(r*integer(2.0**i)));
if aux /= 0 then
while c1_ite /= null loop
c := c1_ite.value;
if aux mod c = 0 then
c := aux / c;
if c < UPPER_LIMIT then
c := reduce_to_odd(c);
if c = s then
result := true;
return;
end if;
end if;
end if;
c1_ite := c1_ite.next_node;
end loop;
end if;
c1_ite := C1.head;
end loop;
if r /= t then
iterations := number_of_iterations(r, t);
for i in 0 to iterations loop
aux := r + t*integer(2.0**i);
while c1_ite /= null loop
c := c1_ite.value;
if aux mod c = 0 then
c := aux / c;
if c < UPPER_LIMIT then
c := reduce_to_odd(c);
if c = s then
result := true;
return;
end if;
end if;
end if;
c1_ite := c1_ite.next_node;
end loop;
c1_ite := C1.head;
aux := abs(integer(r) - integer(t*integer(2.0**i)));
if aux /= 0 then
while c1_ite /= null loop
c := c1_ite.value;
if aux mod c = 0 then
c := aux / c;
if c < UPPER_LIMIT then
c := reduce_to_odd(c);
if c = s then
result := true;
return;
end if;
end if;
end if;
c1_ite := c1_ite.next_node;
end loop;
end if;
end loop;
end if;
r_ite := r_ite.next_node;
end loop;
result := false;
end procedure;
--test6, distance-3, (A_*(s, t) intersetion S)
procedure test_6(
variable s_set : in bst_access;
s : in positive;
t : in positive;
result : out boolean)
is
variable aux : natural;
variable iterations : positive;
begin
iterations := number_of_iterations(t, s);
for i in 0 to iterations loop
aux := t + s*integer(2.0**i);
if aux < UPPER_LIMIT then
aux := reduce_to_odd(aux);
search(s_set, aux);
if aux /= 0 then
result := true;
return;
end if;
end if;
aux := abs(integer(t) - integer(s*integer(2.0**i)));
if aux /= 0 then
aux := reduce_to_odd(aux);
search(s_set, aux);
if aux /= 0 then
result := true;
return;
end if;
end if;
end loop;
if s /= t then
iterations := number_of_iterations(s, t);
for i in 0 to iterations loop
aux := s + t*integer(2.0**i);
if aux < UPPER_LIMIT then
aux := reduce_to_odd(aux);
search(s_set, aux);
if aux /= 0 then
result := true;
return;
end if;
end if;
aux := abs(integer(s) - integer(t*integer(2.0**i)));
if aux /= 0 then
aux := reduce_to_odd(aux);
search(s_set, aux);
if aux /= 0 then
result := true;
return;
end if;
end if;
end loop;
end if;
result := false;
end procedure;
----------------------------------------------------------------------------------------------------
function csd_cost(
number : positive)
return positive is
constant number_uf : u_ufixed := to_ufixed(real(number), min_bits(number), 0);
variable number_csd : T_csd(number_uf'range) := to_csd(number_uf);
variable result : natural := 0;
begin
for i in number_csd'range loop
if number_csd(i) /= "00" then
result := result + 1;
end if;
end loop;
return ite(result=1, result, result - 1); --one shift and the unshifted signal can be added together
end function;
procedure distance_estimation(
variable C1 : in llist_access;
s : in positive;
t : in positive;
Est : inout natural) --must be the previous dist_Rt when called
is
variable c1_ite : llist_node_access := C1.head;
variable term1, term2, c : positive;
variable aux : natural;
variable E1 : positive;
variable iterations : positive;
begin
--estimator 1: E1=1+Est(A_*(s, t))
term1 := s;
term2 := t;
iterations := number_of_iterations(term1, term2);
for i in 0 to iterations loop
aux := term1 + term2*integer(2.0**i);
if aux < UPPER_LIMIT then
aux := 1 + csd_cost(reduce_to_odd(aux));
if aux < Est then
Est := aux;
end if;
end if;
aux := abs(integer(term1) - integer(term2*integer(2.0**i)));
if aux /= 0 and aux < UPPER_LIMIT then
aux := 1 + csd_cost(reduce_to_odd(aux));
if aux < Est then
Est := aux;
end if;
end if;
end loop;
iterations := number_of_iterations(term2, term1);
for i in 0 to iterations loop
aux := term2 + term1*integer(2.0**i);
if aux < UPPER_LIMIT then
aux := 1 + csd_cost(reduce_to_odd(aux));
if aux < Est then
Est := aux;
end if;
end if;
aux := abs(integer(term2) - integer(term1*integer(2.0**i)));
if aux /= 0 and aux < UPPER_LIMIT then
aux := 1 + csd_cost(reduce_to_odd(aux));
if aux < Est then
Est := aux;
end if;
end if;
end loop;
--estimator 2: E2=2+Est(A_*(s, t/C1))
term1 := s;
while c1_ite /= null loop
c := c1_ite.value;
if t mod c = 0 then
term2 := t/c;
iterations := number_of_iterations(term1, term2);
for i in 0 to iterations loop
aux := term1 + term2*integer(2.0**i);
if aux < UPPER_LIMIT then
aux := 2 + csd_cost(reduce_to_odd(aux));
if aux < Est then
Est := aux;
end if;
end if;
aux := abs(integer(term1) - integer(term2*integer(2.0**i)));
if aux /= 0 then
aux := 2 + csd_cost(reduce_to_odd(aux));
if aux < Est then
Est := aux;
end if;
end if;
end loop;
iterations := number_of_iterations(term2, term1);
for i in 0 to iterations loop
aux := term2 + term1*integer(2.0**i);
if aux < UPPER_LIMIT then
aux := 2 + csd_cost(reduce_to_odd(aux));
if aux < Est then
Est := aux;
end if;
end if;
aux := abs(integer(term2) - integer(term1*integer(2.0**i)));
if aux /= 0 and aux < UPPER_LIMIT then
aux := 2 + csd_cost(reduce_to_odd(aux));
if aux < Est then
Est := aux;
end if;
end if;
end loop;
end if;
c1_ite := c1_ite.next_node;
end loop;
--estimator 3: E3=2+Est(A_*(C1*s, t))
c1_ite := c1.head;
term1 := t;
loopw: while c1_ite /= null loop
c := c1_ite.value;
term2 := s*c;
if s*c > UPPER_LIMIT then
exit loopw;
else
iterations := number_of_iterations(term1, term2);
for i in 0 to iterations loop
aux := term1 + term2*integer(2.0**i);
if aux < UPPER_LIMIT then
aux := 2 + csd_cost(reduce_to_odd(aux));
if aux < Est then
Est := aux;
end if;
end if;
aux := abs(integer(term1) - integer(term2*integer(2.0**i)));
if aux /= 0 then
aux := 2 + csd_cost(reduce_to_odd(aux));
if aux < Est then
Est := aux;
end if;
end if;
end loop;
iterations := number_of_iterations(term2, term1);
for i in 0 to iterations loop
aux := term2 + term1*integer(2.0**i);
if aux < UPPER_LIMIT then
aux := 2 + csd_cost(reduce_to_odd(aux));
if aux < Est then
Est := aux;
end if;
end if;
aux := abs(integer(term2) - integer(term1*integer(2.0**i)));
if aux /= 0 and aux < UPPER_LIMIT then
aux := 2 + csd_cost(reduce_to_odd(aux));
if aux < Est then
Est := aux;
end if;
end if;
end loop;
end if;
c1_ite := c1_ite.next_node;
end loop;
end procedure;
procedure calculate_first_dist_Rt(
variable C1 : in llist_access;
variable t_set : in llist_access;
dist : out natural)
is
variable aux : natural := 0;
variable top : natural;
variable iter : llist_node_access;
begin
if t_set /= null then
iter := t_set.head;
while iter /= null loop
top := natural'high;
distance_estimation(C1, 1, iter.value, top);
aux := aux + top;
iter := iter.next_node;
end loop;
dist := aux;
end if;
end procedure;
procedure update_dist_Rt(
dist_Rt : inout positive;
variable C1 : in llist_access;
variable r_set : in llist_access;
variable s_set : in bst_access;
s : in positive;
variable t_set : in llist_access)
is
variable t_ite : llist_node_access;
variable t : positive;
variable bool : boolean;
variable result : natural := natural'high;
variable Est : positive;
begin
if t_set /= null then
t_ite := t_set.head;
--only update dist_Rt when taking an s whose distance has been estimated
while t_ite /= null loop
t := t_ite.value;
if t = s then
return;
end if;
test_1(C1, s, t, bool);
if bool then
return;
end if;
test_2(r_set, s, t, bool);
if bool then
return;
end if;
test_3(C1, s, t, bool);
if bool then
return;
end if;
test_4(C1, r_set, s, t, bool);
if bool then
return;
end if;
test_5(C1, r_set, s, t, bool);
if bool then
return;
end if;
test_6(s_set, s, t, bool);
if bool then
return;
end if;
Est := dist_Rt;
distance_estimation(C1, s, t, Est);
if Est < result then
result := Est;
end if;
t_ite := t_ite.next_node;
end loop;
dist_Rt := Est;
end if;
end procedure;
procedure distance(
variable C1 : in llist_access;
variable r_set : in llist_access;
variable s_set : in bst_access;
s : in positive;
t : in positive;
dist_Rt : inout positive;
dist_Rst : out positive)
is
variable bool : boolean;
variable Est : positive := dist_Rt;
begin
test_1(C1, s, t, bool);
if bool then
dist_Rt := 2;
dist_Rst := dist_Rt-1;
return;
end if;
test_2(r_set, s, t, bool);
if bool then
dist_Rt := 2;
dist_Rst := dist_Rt - 1;
return;
end if;
test_3(C1, s, t, bool);
if bool then
dist_Rt := 3;
dist_Rst := dist_Rt - 1;
return;
end if;
test_4(C1, r_set, s, t, bool);
if bool then
dist_Rt := 3;
dist_Rst := dist_Rt - 1;
return;
end if;
test_5(C1, r_set, s, t, bool);
if bool then
dist_Rt := 3;
dist_Rst := dist_Rt - 1;
return;
end if;
test_6(s_set, s, t, bool);
if bool then
dist_Rt := 3;
dist_Rst := dist_Rt - 1;
return;
end if;
distance_estimation(C1, s, t, Est);
dist_Rst := Est;
end procedure;
function benefit(
dist_Rt : positive;
dist_Rst : positive)
return real is
begin
return real(dist_Rt-dist_Rst)*(10.0**(-dist_Rst));
end function;
procedure Hcub(
variable C1 : in llist_access;
variable r_set : in llist_access;
variable s_set : in bst_access;
s_node : inout bst_node_access;
variable t_set : in llist_access;
dist_Rt : in positive;
bits : inout natural;
max : inout real;
solution : inout natural)
is
variable dist_Rst_aux : positive;
variable dist_Rt_aux : positive;
variable sum : real := 0.0;
variable bits_actual : positive;
variable t_ite : llist_node_access := t_set.head;
begin
if s_node = null then
solution := 0;
else
if s_node.left /= null then
Hcub(C1, r_set, s_set, s_node.left, t_set, dist_Rt, bits, max, solution);
end if;
while t_ite /= null loop
dist_Rt_aux := dist_Rt;
distance(C1, r_set, s_set, s_node.value, t_ite.value, dist_Rt_aux, dist_Rst_aux);
sum := sum + benefit(dist_Rt_aux, dist_Rst_aux);
t_ite := t_ite.next_node;
end loop;
if sum > max then
max := sum;
solution := s_node.value;
bits := min_bits(s_node.value);
elsif sum = max then
bits_actual := min_bits(s_node.value);
if bits_actual < bits then
bits := bits_actual;
solution := s_node.value;
end if;
end if;
if s_node.right /= null then
Hcub(C1, r_set, s_set, s_node.right, t_set, dist_Rt, bits, max, solution);
end if;
end if;
end procedure;
procedure Hcub(
variable C1 : in llist_access;
variable r_set : in llist_access;
variable s_set : in bst_access;
variable t_set : in llist_access;
dist_Rt : in positive;
solution : out natural)
is
variable s_node : bst_node_access;
variable max : real := 0.0;
variable bits : natural := natural'high;
begin
if s_set.root /= null and r_set.head /= null and t_set.head /= null then
s_node := s_set.root;
Hcub(C1, r_set, s_set, s_node, t_set, dist_Rt, bits, max, solution);
else
solution := 0;
end if;
end procedure;
----------------------------------------------------------------------------------------------------
procedure insert(
graph : inout vertex_access;
variable new_node : in vertex_node_access)
is
begin
if graph /= null then
if new_node /= null then
if graph.head = null then
graph.head := new_node;
graph.tail := new_node;
else
graph.tail.next_node := new_node;
graph.tail := new_node;
end if;
graph.size := graph.size + 1;
else
msg_debug("insert<vertex_access, vertex_node_access> : null vertex_node_access");
end if;
else
msg_debug("insert<vertex_access, vertex_node_access> : null vertex_access");
end if;
end procedure;
--this procedure receives the fundamental to synthesize next and calculates the combination of the
--previously synthesized fundamentals that result in the new one, and adds this information to a
--vertex_node which is then returned
procedure insert(
vertex : inout vertex_node_access;
variable r_set : in llist_access;
fundamental : in positive)
is
variable ite1, ite2 : llist_node_access;
variable aux : integer;
variable exponent : natural;
begin
if vertex /= null then
if r_set /= null then
ite1 := r_set.head;
while ite1 /= null loop
ite2 := r_set.head;
while ite2 /= null loop
exponent := 0;
aux := 0;
while aux <= fundamental loop
aux := ite1.value*(2**exponent) - ite2.value;
if fundamental = aux then --u^exp-v=w
vertex.w := fundamental;
vertex.u := ite1.value;
vertex.v := ite2.value;
vertex.l1 := exponent;
vertex.l2 := 0;
vertex.s := true;
return;
elsif fundamental = abs(aux) then --u-v^exp=w
vertex.w := fundamental;
vertex.u := ite2.value;
vertex.v := ite1.value;
vertex.l1 := 0;
vertex.l2 := exponent;
vertex.s := true;
return;
elsif fundamental = aux + 2*ite2.value then --u^exp+v=w
vertex.w := fundamental;
vertex.u := ite1.value;
vertex.v := ite2.value;
vertex.l1 := exponent;
vertex.l2 := 0;
vertex.s := false;
return;
end if;
exponent := exponent + 1;
end loop;
ite2 := ite2.next_node;
end loop;
ite1 := ite1.next_node;
end loop;
else
msg_debug("insert(vertex_node_access, bst_access, positive) : bst_access is null");
end if;
else
msg_debug("insert(vertex_node_access, bst_access, positive) : vertex_node_access is null");
end if;
end procedure;
procedure synthesize(
number : in positive;
variable r_set : in llist_access;
variable s_set : in bst_access;
t_set : inout llist_access;
w_set : inout llist_access;
solution_graph : inout vertex_access)
is
variable node : vertex_node_access;
begin
insert(w_set, number); -- W <- W+{number}
delete_value(t_set, number); -- T <- T-{number}
--create node with the vertex information and insert it into solution graph
node := new vertex_node;
insert(node, r_set, number);
insert(solution_graph, node);
end procedure;
procedure synthesize1(
solution_graph : inout vertex_access;
t_set : inout llist_access)
is
variable node : vertex_node_access;
begin
node := new vertex_node'(w => 1, u =>1, l1 =>0, v =>1, l2 => 0, s => true, next_node => null);
insert(solution_graph, node);
delete_value(t_set, 1);
end procedure;
procedure search_and_synthesize(
variable r_set : in llist_access;
s_set : inout bst_access;
t_set : inout llist_access;
w_set : inout llist_access;
solution_graph : inout vertex_access)
is
variable to_synth : llist_access := new llist;
variable iter : llist_node_access;
variable t : natural;
begin
if s_set /= null then
if t_set /= null then
if w_set /= null then
--save found values into a linked list
iter := t_set.head;
while iter /= null loop
t := iter.value;
search(s_set, t);
if t /= 0 then
insert(to_synth, t);
end if;
iter := iter.next_node;
end loop;
--synthesize the saved values
iter := to_synth.head;
if iter /= null then
while iter /= null loop
t := iter.value;
synthesize(t, r_set, s_set, t_set, w_set, solution_graph);
iter := iter.next_node;
end loop;
end if;
end if;
end if;
end if;
end procedure;
procedure generate_solution_file(
variable solution_graph : in vertex_access)
is
file solution_output : text;
variable current_line : line;
variable ite : vertex_node_access;
begin
file_open(solution_output, FILE_PATH, WRITE_MODE);
if solution_graph /= null then
write(current_line, image(solution_graph.size) & LF);
ite := solution_graph.head;
while ite /= null loop
write(current_line, image(ite.w));
write(current_line, string'(" "));
write(current_line, image(ite.u));
write(current_line, string'(" "));
write(current_line, image(ite.l1));
write(current_line, string'(" "));
write(current_line, image(ite.v));
write(current_line, string'(" "));
write(current_line, image(ite.l2));
write(current_line, string'(" "));
if ite.s then
write(current_line, string'("0"));
else
write(current_line, string'("1"));
end if;
writeline(solution_output, current_line);
ite := ite.next_node;
end loop;
end if;
file_close(solution_output);
end procedure;
----------------------------------------------------------------------------------------------------
procedure VorPus(
target : positive_v)
is
-- possible use of hash table for search [variable successor_hash_table : bit_vector (1 to 2^(UPPER_BITS + 1)) := (others => '0');]
variable C1 : llist_access := new llist'(null, null);
variable dist_Rt : natural;
variable target_set : llist_access := new llist'(null, null);
variable ready_set : llist_access := new llist'(null, null);
variable working_set : llist_access := new llist'(null, null);
variable successor_set : bst_access := new bst'(0, null);
variable first_iteration : boolean := true;
variable t : natural;
variable solution_graph : vertex_access := new vertex'(0, null, null);
begin
generateC1(C1);
----------------------------------------------------------------------------------------------
--Voronenko -Püschel algorithm
----------------------------------------------------------------------------------------------
insert(target_set, target); --inserts all values in the input positive vector to the linked list target_set
insert(ready_set, 1);
insert(working_set, 1);
insert(successor_set, 1);
--synthesize value 1
synthesize1(solution_graph, target_set);
calculate_first_dist_Rt(C1, target_set, dist_Rt);
msg_debug(image(MAX_TARGET));
msg_debug(target_set, "target_set");
msg_debug(working_set, "working_set");
msg_debug(ready_set, "ready_set");
msg_debug(successor_set, "successor_set");
msg_debug(C1, "C1");
t_loop:
while target_set.head /= null loop
--OPTIMAL PART
while working_set.head /= null loop
--R <- (R union W)
union(ready_set, working_set);
--S <- (S union A^*(R, W))-W
if first_iteration then --in the first iteration the values in the successor set are
--the same as those in C^1, so we just copy them from the already existing C^1 list
insert(successor_set, C1);
delete_value(successor_set, 1);
--balance the binary search tree
dsw(successor_set, successor_set.size);
else
compute_d1_successors(successor_set, ready_set, working_set);
end if;
--W <- Ø
empty(working_set);
--for t € (S intersection T) synthesize(t)
search_and_synthesize(ready_set, successor_set, target_set, working_set, solution_graph);
first_iteration := false;
msg_debug(target_set, "target_set");
msg_debug(working_set, "working_set");
msg_debug(ready_set, "ready_set");
msg_debug(successor_set, "successor_set");
msg_debug("dist_Rt = " & image(dist_Rt));
end loop;
--HEURISTIC PART
if target_set.head /= null then
Hcub(C1, ready_set, successor_set, target_set, dist_Rt, t);
synthesize(t, ready_set, successor_set, target_set, working_set, solution_graph);
update_dist_Rt(dist_Rt, C1, ready_set, successor_set, t, target_set);
msg_debug(target_set, "target_set");
msg_debug(working_set, "working_set");
msg_debug(ready_set, "ready_set");
msg_debug(successor_set, "successor_set");
msg_debug(solution_graph, "solution graph");
msg_debug("dist_Rt = " & image(dist_Rt));
end if;
end loop;
----------------------------------------------------------------------------------------------------
generate_solution_file(solution_graph);
msg_debug(successor_set, "successor_set");
msg_debug(working_set, "working_set");
msg_debug(ready_set, "ready_set");
msg_debug(target_set, "target_set");
msg_debug(string'("targets:"));
msg_debug(target, ", ");
msg_debug(solution_graph, "solution graph");
end procedure;
end package body; | mit | 17da2b10965c57911b84125815522079 | 0.476009 | 4.253871 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/speccy/src/ay8910/ay8910.vhd | 2 | 14,079 | -- #####################################################################################
--
-- #### #### #####
-- ## ## ## ##
-- ## ## ##### ## ## ##### ## ###### ##### ##### ##### ## ##
-- ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ##
-- ## ## ## ## ## ## ## ## ##### ## ## ## ## ## ## ## ##
-- ## ## ## ## ## ## ###### ## ###### ###### ## ## ######
-- ## ## ## ## ## ## ## ## ## ## ## ## ##
-- ## ## ## ## ## ### ## ## ## ## ## ## ## ## ## ## ## ## ##
-- #### ######## ##### # ##### ##### ## ##### ##### ##### #####
--
-- #####################################################################################
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ay8910 is
port( -----------------------------------------
CLK : in std_logic; -- System Clock
CLC : in std_logic; -- PSG Clock
RESET : in std_logic; -- Chip Reset (set all Registers to '0', active low)
BDIR : in std_logic; -- Bus Direction (0 - read , 1 - write)
CS : in std_logic; -- Chip Select (active low)
BC : in std_logic; -- Bus control
DI : in std_logic_vector(7 downto 0); -- Data In
DO : out std_logic_vector(7 downto 0); -- Data Out
OUT_A : out std_logic_vector(7 downto 0); -- PSG Output channel A
OUT_B : out std_logic_vector(7 downto 0); -- PSG Output channel B
OUT_C : out std_logic_vector(7 downto 0) -- PSG Output channel C
); -----------------------------------------
end ay8910;
architecture rtl of ay8910 is
signal ClockDiv : unsigned (3 downto 0); -- Divide CLC
----------------------- AY Registers ----------------------
signal Period_A : std_logic_vector (11 downto 0); -- Channel A Tone Period (R1:R0)
signal Period_B : std_logic_vector (11 downto 0); -- Channel B Tone Period (R3:R2)
signal Period_C : std_logic_vector (11 downto 0); -- Channel C Tone Period (R5:R4)
signal Period_N : std_logic_vector (4 downto 0); -- Noise Period (R6)
signal Enable : std_logic_vector (7 downto 0); -- Enable (R7)
signal Volume_A : std_logic_vector (4 downto 0); -- Channel A Amplitude (R10)
signal Volume_B : std_logic_vector (4 downto 0); -- Channel B Amplitude (R11)
signal Volume_C : std_logic_vector (4 downto 0); -- Channel C Amplitude (R12)
signal Period_E : std_logic_vector (15 downto 0); -- Envelope Period (R14:R13)
signal Shape : std_logic_vector (3 downto 0); -- Envelope Shape/Cycle (R15)
signal Port_A : std_logic_vector (7 downto 0); -- I/O Port A Data Store (R16)
signal Port_B : std_logic_vector (7 downto 0); -- I/O Port B Data Store (R17)
-----------------------------------------------------------
signal Address : std_logic_vector (3 downto 0); -- Selected Register
alias Continue : std_logic is Shape(3); ------------- Envelope Control
alias Attack : std_logic is Shape(2); --
alias Alternate : std_logic is Shape(1); --
alias Hold : std_logic is Shape(0); -------------
signal Reset_Req : std_logic; ------------------------- Envelope Reset Required
signal Reset_Ack : std_logic; ------------------------- Envelope Reset Acknoledge
signal Volume_E : std_logic_vector (3 downto 0); -- Envelope Volume
signal Freq_A : std_logic; -- Tone Generator A Output
signal Freq_B : std_logic; -- Tone Generator B Output
signal Freq_C : std_logic; -- Tone Generator C Output
signal Freq_N : std_logic; -- Noise Generator Output
function VolumeTable (value : std_logic_vector(3 downto 0)) return std_logic_vector is
variable result : std_logic_vector (7 downto 0);
begin
case value is ----------------------------------- Volume Table
when "1111" => result := "11111111";
when "1110" => result := "10110100";
when "1101" => result := "01111111";
when "1100" => result := "01011010";
when "1011" => result := "00111111";
when "1010" => result := "00101101";
when "1001" => result := "00011111";
when "1000" => result := "00010110";
when "0111" => result := "00001111";
when "0110" => result := "00001011";
when "0101" => result := "00000111";
when "0100" => result := "00000101";
when "0011" => result := "00000011";
when "0010" => result := "00000010";
when "0001" => result := "00000001";
when "0000" => result := "00000000";
when others => null;---------------------------
end case;
return result;
end VolumeTable;
begin
------------------------- Write to AY ---------------------
process (RESET , CLK)
begin
if RESET = '0' then
Address <= "0000";
Period_A <= "000000000000";
Period_B <= "000000000000";
Period_C <= "000000000000";
Period_N <= "00000";
Enable <= "00000000";
Volume_A <= "00000";
Volume_B <= "00000";
Volume_C <= "00000";
Period_E <= "0000000000000000";
Shape <= "0000";
Port_A <= "00000000";
Port_B <= "00000000";
Reset_Req <= '0';
elsif rising_edge(CLK) then
if CS = '0' and BDIR = '1' then
if BC = '1' then
Address <= DI (3 downto 0); ----------------- Latch Address
else
case Address is ------------------------------- Latch Registers
when "0000" => Period_A (7 downto 0) <= DI;
when "0001" => Period_A (11 downto 8) <= DI (3 downto 0);
when "0010" => Period_B (7 downto 0) <= DI;
when "0011" => Period_B (11 downto 8) <= DI (3 downto 0);
when "0100" => Period_C (7 downto 0) <= DI;
when "0101" => Period_C (11 downto 8) <= DI (3 downto 0);
when "0110" => Period_N <= DI (4 downto 0);
when "0111" => Enable <= DI;
when "1000" => Volume_A <= DI (4 downto 0);
when "1001" => Volume_B <= DI (4 downto 0);
when "1010" => Volume_C <= DI (4 downto 0);
when "1011" => Period_E (7 downto 0) <= DI;
when "1100" => Period_E (15 downto 8) <= DI;
when "1101" => Shape <= DI (3 downto 0);
Reset_Req <= not Reset_Ack; -- Reset Envelope Generator
when "1110" => Port_A <= DI;
when "1111" => Port_B <= DI;
when others => null;
end case;
end if;
end if;
end if;
end process;
------------------------- Read from AY --------------------
DO <= Period_A (7 downto 0) when Address = "0000" and CS = '0' and BDIR = '0' and BC = '1' else
"0000" & Period_A (11 downto 8) when Address = "0001" and CS = '0' and BDIR = '0' and BC = '1' else
Period_B (7 downto 0) when Address = "0010" and CS = '0' and BDIR = '0' and BC = '1' else
"0000" & Period_B (11 downto 8) when Address = "0011" and CS = '0' and BDIR = '0' and BC = '1' else
Period_C (7 downto 0) when Address = "0100" and CS = '0' and BDIR = '0' and BC = '1' else
"0000" & Period_C (11 downto 8) when Address = "0101" and CS = '0' and BDIR = '0' and BC = '1' else
"000" & Period_N when Address = "0110" and CS = '0' and BDIR = '0' and BC = '1' else
Enable when Address = "0111" and CS = '0' and BDIR = '0' and BC = '1' else
"000" & Volume_A when Address = "1000" and CS = '0' and BDIR = '0' and BC = '1' else
"000" & Volume_B when Address = "1001" and CS = '0' and BDIR = '0' and BC = '1' else
"000" & Volume_C when Address = "1010" and CS = '0' and BDIR = '0' and BC = '1' else
Period_E (7 downto 0) when Address = "1011" and CS = '0' and BDIR = '0' and BC = '1' else
Period_E (15 downto 8) when Address = "1100" and CS = '0' and BDIR = '0' and BC = '1' else
"0000" & Shape when Address = "1101" and CS = '0' and BDIR = '0' and BC = '1' else
-- Port_A when Address = "1110" and CS = '0' and BDIR = '0' and BC = '1' else
-- Port_B when Address = "1111" and CS = '0' and BDIR = '0' and BC = '1' else
"11111111";
-------------------------- Divide CLC ---------------------
process (RESET , CLK)
begin
if RESET = '0' then
ClockDiv <= "0000";
elsif rising_edge(CLK) then
if CLC = '1' then
ClockDiv <= ClockDiv - 1;
end if;
end if;
end process;
------------------------ Tone Generator -------------------
process (RESET , CLK)
variable Counter_A : unsigned (11 downto 0);
variable Counter_B : unsigned (11 downto 0);
variable Counter_C : unsigned (11 downto 0);
begin
if RESET = '0' then
Counter_A := "000000000000";
Counter_B := "000000000000";
Counter_C := "000000000000";
Freq_A <= '0';
Freq_B <= '0';
Freq_C <= '0';
elsif rising_edge(CLK) then
if ClockDiv(2 downto 0) = "000" and CLC = '1' then
-- Channel A Counter
if (Counter_A /= X"000") then
Counter_A := Counter_A - 1;
elsif (Period_A /= X"000") then
Counter_A := unsigned(Period_A) - 1;
end if;
if (Counter_A = X"000") then
Freq_A <= not Freq_A;
end if;
-- Channel B Counter
if (Counter_B /= X"000") then
Counter_B := Counter_B - 1;
elsif (Period_B /= X"000") then
Counter_B := unsigned(Period_B) - 1;
end if;
if (Counter_B = X"000") then
Freq_B <= not Freq_B;
end if;
-- Channel C Counter
if (Counter_C /= X"000") then
Counter_C := Counter_C - 1;
elsif (Period_C /= X"000") then
Counter_C := unsigned(Period_C) - 1;
end if;
if (Counter_C = X"000") then
Freq_C <= not Freq_C;
end if;
end if;
end if;
end process;
----------------------- Noise Generator -------------------
process (RESET , CLK)
variable NoiseShift : unsigned (16 downto 0);
variable Counter_N : unsigned (4 downto 0);
begin
if RESET = '0' then
Counter_N := "00000";
NoiseShift := "00000000000000001";
elsif rising_edge(CLK) then
if ClockDiv(2 downto 0) = "000" and CLC = '1' then
if (Counter_N /= "00000") then
Counter_N := Counter_N - 1;
elsif (Period_N /= "00000") then
Counter_N := unsigned(Period_N) - 1;
end if;
if Counter_N = "00000" then
NoiseShift := (NoiseShift(0) xor NoiseShift(2)) & NoiseShift(16 downto 1);
end if;
Freq_N <= NoiseShift(0);
end if;
end if;
end process;
---------------------- Envelope Generator -----------------
process (RESET , CLK)
variable EnvCounter : unsigned(15 downto 0);
variable EnvWave : unsigned(4 downto 0);
begin
if RESET = '0' then
EnvCounter := "0000000000000000";
EnvWave := "11111";
Volume_E <= "0000";
Reset_Ack <= '0';
elsif rising_edge(CLK) then
if ClockDiv = "0000" and CLC = '1' then
------------ Envelope Period Counter -----------
if (EnvCounter /= X"0000" and Reset_Req = Reset_Ack) then
EnvCounter := EnvCounter - 1;
elsif (Period_E /= X"0000") then
EnvCounter := unsigned(Period_E) - 1;
end if;
------------ Envelope Phase Counter ------------
if (Reset_Req /= Reset_Ack) then
EnvWave := (others => '1');
elsif (EnvCounter = X"0000" and (EnvWave(4) = '1' or (Hold = '0' and Continue = '1'))) then
EnvWave := EnvWave - 1;
end if;
---------- Envelope Amplitude Counter ----------
for I in 3 downto 0 loop
if (EnvWave(4) = '0' and Continue = '0') then
Volume_E(I) <= '0';
elsif (EnvWave(4) = '1' or (Alternate xor Hold) = '0') then
Volume_E(I) <= EnvWave(I) xor Attack;
else
Volume_E(I) <= EnvWave(I) xor Attack xor '1';
end if;
end loop;
Reset_Ack <= Reset_Req;
end if;
end if;
end process;
--------------------------- Mixer -------------------------
process (RESET , CLK)
begin
if RESET = '0' then
OUT_A <= "00000000";
OUT_B <= "00000000";
OUT_C <= "00000000";
elsif rising_edge(CLK) then
if CLC = '1' then
if (((Enable(0) or Freq_A) and (Enable(3) or Freq_N)) = '0') then
OUT_A <= "00000000";
elsif (Volume_A(4) = '0') then
OUT_A <= VolumeTable(Volume_A(3 downto 0));
else
OUT_A <= VolumeTable(Volume_E);
end if;
if (((Enable(1) or Freq_B) and (Enable(4) or Freq_N)) = '0') then
OUT_B <= "00000000";
elsif (Volume_B(4) = '0') then
OUT_B <= VolumeTable(Volume_B(3 downto 0));
else
OUT_B <= VolumeTable(Volume_E);
end if;
if (((Enable(2) or Freq_C) and (Enable(5) or Freq_N)) = '0') then
OUT_C <= "00000000";
elsif (Volume_C(4) = '0') then
OUT_C <= VolumeTable(Volume_C(3 downto 0));
else
OUT_C <= VolumeTable(Volume_E);
end if;
end if;
end if;
end process;
end rtl;
| gpl-3.0 | e998f789b44221273dbf66e3f2ac44c0 | 0.449038 | 3.640807 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/service/src/video.vhd | 1 | 5,623 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity video is
port (
CLK : in std_logic;
VGA_CLK : in std_logic;
RESET : in std_logic;
VA : in std_logic_vector(11 downto 0);
VDI : in std_logic_vector(7 downto 0);
VDO : out std_logic_vector(15 downto 0);
VWR : in std_logic;
VATTR : in std_logic_vector(7 downto 0);
VGA_R : out std_logic_vector(3 downto 0);
VGA_G : out std_logic_vector(3 downto 0);
VGA_B : out std_logic_vector(3 downto 0);
VGA_HSYNC : out std_logic;
VGA_VSYNC : out std_logic
);
end video;
architecture Behavioral of video is
signal V_COUNTER : unsigned(9 downto 0); -- Vertical Counter
signal H_COUNTER : unsigned(11 downto 0); -- Horizontal Counter
signal PAPER : std_logic;
signal PAPER_ENA : std_logic;
signal PIX : std_logic_vector(7 downto 0);
signal PIX_LT : std_logic_vector(7 downto 0);
signal ATTR : std_logic_vector(7 downto 0);
signal ATTR_LT : std_logic_vector(7 downto 0);
constant HSIZE : integer := 640; -- Paper H_size --1024
constant VSIZE : integer := 480; -- Paper V_size --768
constant HFP : integer := 16; --24;
constant HS : integer := 96; --136;
constant HB : integer := 48; --160;
constant VFP : integer := 19; --3;
constant VS : integer := 2; --6;
constant VB : integer := 33; --29;
signal FONTROM_A : std_logic_vector(11 downto 0);
signal FONTROM_DO : std_logic_vector(7 downto 0);
signal VRAM_WR : std_logic_vector(0 downto 0);
signal VRAM_RA : std_logic_vector(11 downto 0);
signal VRAM_RDO : std_logic_vector(15 downto 0);
begin
--##########################
VRAM_WR <= "1" when VWR = '1' else "0";
u_FONTROM : entity work.fontrom
port map(
clka => VGA_CLK,
addra => FONTROM_A,
douta => FONTROM_DO );
u_VRAM : entity work.vram
port map(
clka => CLK,
wea => VRAM_WR,
addra => VA,
dina => VATTR & VDI,
douta => VDO,
clkb => VGA_CLK,
web => "0",
addrb => VRAM_RA,
dinb => X"0000",
doutb => VRAM_RDO );
process (VGA_CLK)
begin
if rising_edge(VGA_CLK) then
if RESET = '1' then
H_COUNTER <= (others=>'0');
V_COUNTER <= (others=>'0');
else
H_COUNTER <= H_COUNTER + 1;
if H_COUNTER = (HSIZE + HFP + HS + HB - 1) then
H_COUNTER <= (others=>'0');
V_COUNTER <= V_COUNTER + 1;
if V_COUNTER = (VSIZE + VFP + VS + VB - 1) then
V_COUNTER <= (others=>'0');
end if;
end if;
end if;
VGA_HSYNC <= '1';
VGA_VSYNC <= '1';
PAPER <= '0';
if H_COUNTER >= (HSIZE + HFP) and H_COUNTER < (HSIZE + HFP + HS)then
VGA_HSYNC <= '0';
end if;
if V_COUNTER >= (VSIZE + VFP) and V_COUNTER < (VSIZE + VFP + VS)then
VGA_VSYNC <= '0';
end if;
if H_COUNTER < HSIZE and V_COUNTER < VSIZE then
PAPER <= '1';
end if;
end if;
end process;
process (VGA_CLK)
begin
if rising_edge(VGA_CLK) then
case H_COUNTER(2 downto 0) is
when "000" =>
VRAM_RA <= std_logic_vector(V_COUNTER(8 downto 4)) & std_logic_vector(H_COUNTER(9 downto 3));
when "010" =>
FONTROM_A <= VRAM_RDO(7 downto 0) & std_logic_vector(V_COUNTER(3 downto 0));
ATTR <= VRAM_RDO(15 downto 8);
when "100" =>
PIX <= FONTROM_DO;
when "111" =>
PAPER_ENA <= PAPER;
PIX_LT <= PIX;
ATTR_LT <= ATTR;
when others => NULL;
end case;
end if;
end process;
process (VGA_CLK)
begin
if rising_edge(VGA_CLK) then
if PAPER_ENA = '1' then
if PIX_LT(7 - to_integer(H_COUNTER(2 downto 0))) = '1' then
VGA_R(3) <= ATTR_LT(2);
VGA_R(2) <= ATTR_LT(2) and ATTR_LT(3);
VGA_R(1) <= ATTR_LT(2) and ATTR_LT(3);
VGA_R(0) <= ATTR_LT(2);
VGA_G(3) <= ATTR_LT(1);
VGA_G(2) <= ATTR_LT(1) and ATTR_LT(3);
VGA_G(1) <= ATTR_LT(1) and ATTR_LT(3);
VGA_G(0) <= ATTR_LT(1);
VGA_B(3) <= ATTR_LT(0);
VGA_B(2) <= ATTR_LT(0) and ATTR_LT(3);
VGA_B(1) <= ATTR_LT(0) and ATTR_LT(3);
VGA_B(0) <= ATTR_LT(0);
else
VGA_R(3) <= ATTR_LT(6);
VGA_R(2) <= ATTR_LT(6) and ATTR_LT(7);
VGA_R(1) <= ATTR_LT(6) and ATTR_LT(7);
VGA_R(0) <= ATTR_LT(6);
VGA_G(3) <= ATTR_LT(5);
VGA_G(2) <= ATTR_LT(5) and ATTR_LT(7);
VGA_G(1) <= ATTR_LT(5) and ATTR_LT(7);
VGA_G(0) <= ATTR_LT(5);
VGA_B(3) <= ATTR_LT(4);
VGA_B(2) <= ATTR_LT(4) and ATTR_LT(7);
VGA_B(1) <= ATTR_LT(4) and ATTR_LT(7);
VGA_B(0) <= ATTR_LT(4);
end if;
else
VGA_G <= "0000";
VGA_R <= "0000";
VGA_B <= "0000";
end if;
end if;
end process;
--process (VGA_CLK)
--begin
-- if rising_edge(VGA_CLK) then
-- VGA_R <= "0000";
-- VGA_G <= "0000";
-- VGA_B <= "0000";
-- if PAPER = '1' then
-- VGA_B <= "1111";
-- end if;
-- end if;
--end process;
end Behavioral;
| gpl-3.0 | 1eebbf873dfc4688797e9ed8d460b3d0 | 0.472346 | 3.087864 | false | false | false | false |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/sim/vhdl/ip/xil_defaultlib/sin_taylor_series_ap_dsub_3_full_dsp_64.vhd | 6 | 10,830 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY sin_taylor_series_ap_dsub_3_full_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END sin_taylor_series_ap_dsub_3_full_dsp_64;
ARCHITECTURE sin_taylor_series_ap_dsub_3_full_dsp_64_arch OF sin_taylor_series_ap_dsub_3_full_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sin_taylor_series_ap_dsub_3_full_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 1,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END sin_taylor_series_ap_dsub_3_full_dsp_64_arch;
| mit | 992fae592e8e53bcf160713e93d91377 | 0.632595 | 3.20509 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/ps2_to_atari800.vhdl | 1 | 7,483 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- (ILoveSpeccy) Added PS2_KEYS Output
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY ps2_to_atari800 IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
PS2_CLK : IN STD_LOGIC;
PS2_DAT : IN STD_LOGIC;
KEYBOARD_SCAN : IN STD_LOGIC_VECTOR(5 downto 0);
KEYBOARD_RESPONSE : OUT STD_LOGIC_VECTOR(1 downto 0);
CONSOL_START : OUT STD_LOGIC;
CONSOL_SELECT : OUT STD_LOGIC;
CONSOL_OPTION : OUT STD_LOGIC;
FKEYS : OUT STD_LOGIC_VECTOR(11 downto 0);
PS2_KEYS : OUT STD_LOGIC_VECTOR(511 downto 0)
);
END ps2_to_atari800;
ARCHITECTURE vhdl OF ps2_to_atari800 IS
signal ps2_keys_next : std_logic_vector(511 downto 0);
signal ps2_keys_reg : std_logic_vector(511 downto 0);
signal key_event : std_logic;
signal key_value : std_logic_vector(7 downto 0);
signal key_extended : std_logic;
signal key_up : std_logic;
signal CONSOL_START_INT : std_logic;
signal CONSOL_SELECT_INT : std_logic;
signal CONSOL_OPTION_INT : std_logic;
signal FKEYS_INT : std_logic_vector(11 downto 0);
signal atari_keyboard : std_logic_vector(63 downto 0);
SIGNAL SHIFT_PRESSED : STD_LOGIC;
SIGNAL BREAK_PRESSED : STD_LOGIC;
SIGNAL CONTROL_PRESSED : STD_LOGIC;
BEGIN
PS2_KEYS <= ps2_keys_reg;
keyboard1: entity work.ps2_keyboard
PORT MAP
(
CLK => CLK,
RESET_N => RESET_N,
PS2_CLK => PS2_CLK,
PS2_DAT => PS2_DAT,
KEY_EVENT => KEY_EVENT,
KEY_VALUE => KEY_VALUE,
KEY_EXTENDED => KEY_EXTENDED,
KEY_UP => KEY_UP
-- KEY_EVENT : OUT STD_LOGIC; -- high for 1 cycle on new key pressed(or repeated)/released
-- KEY_VALUE : OUT STD_LOGIC_VECTOR(7 downto 0); -- valid on event, raw scan code
-- KEY_EXTENDED : OUT STD_LOGIC; -- valid on event, if scan code extended
-- KEY_UP : OUT STD_LOGIC -- value on event, if key released
);
process(clk,reset_n)
begin
if (reset_n='0') then
ps2_keys_reg <= (others=>'0');
elsif (clk'event and clk='1') then
ps2_keys_reg <= ps2_keys_next;
end if;
end process;
-- 1 bit per PS2 key
process(KEY_EVENT, KEY_VALUE, KEY_EXTENDED, KEY_UP, ps2_keys_reg)
begin
ps2_keys_next <= ps2_keys_reg;
if (key_event = '1') then
ps2_keys_next(to_integer(unsigned(KEY_EXTENDED&KEY_VALUE))) <= NOT(KEY_UP);
end if;
end process;
-- map to atari key code
process(ps2_keys_reg)
begin
atari_keyboard <= (others=>'0');
shift_pressed <= '0';
control_pressed <= '0';
break_pressed <= '0';
consol_start_int <= '0';
consol_select_int <= '0';
consol_option_int <= '0';
atari_keyboard(63)<=ps2_keys_reg(16#1C#);
atari_keyboard(21)<=ps2_keys_reg(16#32#);
atari_keyboard(18)<=ps2_keys_reg(16#21#);
atari_keyboard(58)<=ps2_keys_reg(16#23#);
atari_keyboard(42)<=ps2_keys_reg(16#24#);
atari_keyboard(56)<=ps2_keys_reg(16#2B#);
atari_keyboard(61)<=ps2_keys_reg(16#34#);
atari_keyboard(57)<=ps2_keys_reg(16#33#);
atari_keyboard(13)<=ps2_keys_reg(16#43#);
atari_keyboard(1)<=ps2_keys_reg(16#3B#);
atari_keyboard(5)<=ps2_keys_reg(16#42#);
atari_keyboard(0)<=ps2_keys_reg(16#4B#);
atari_keyboard(37)<=ps2_keys_reg(16#3A#);
atari_keyboard(35)<=ps2_keys_reg(16#31#);
atari_keyboard(8)<=ps2_keys_reg(16#44#);
atari_keyboard(10)<=ps2_keys_reg(16#4D#);
atari_keyboard(47)<=ps2_keys_reg(16#15#);
atari_keyboard(40)<=ps2_keys_reg(16#2D#);
atari_keyboard(62)<=ps2_keys_reg(16#1B#);
atari_keyboard(45)<=ps2_keys_reg(16#2C#);
atari_keyboard(11)<=ps2_keys_reg(16#3C#);
atari_keyboard(16)<=ps2_keys_reg(16#2A#);
atari_keyboard(46)<=ps2_keys_reg(16#1D#);
atari_keyboard(22)<=ps2_keys_reg(16#22#);
atari_keyboard(43)<=ps2_keys_reg(16#35#);
atari_keyboard(23)<=ps2_keys_reg(16#1A#);
atari_keyboard(50)<=ps2_keys_reg(16#45#);
atari_keyboard(31)<=ps2_keys_reg(16#16#);
atari_keyboard(30)<=ps2_keys_reg(16#1E#);
atari_keyboard(26)<=ps2_keys_reg(16#26#);
atari_keyboard(24)<=ps2_keys_reg(16#25#);
atari_keyboard(29)<=ps2_keys_reg(16#2E#);
atari_keyboard(27)<=ps2_keys_reg(16#36#);
atari_keyboard(51)<=ps2_keys_reg(16#3D#);
atari_keyboard(53)<=ps2_keys_reg(16#3E#);
atari_keyboard(48)<=ps2_keys_reg(16#46#);
--atari_keyboard(17)<=ps2_keys_reg(16#ec#);
--atari_keyboard(17)<=ps2_keys_reg(16#16c#);
atari_keyboard(17)<=ps2_keys_reg(16#16c#) or ps2_keys_reg(16#03#);
atari_keyboard(52)<=ps2_keys_reg(16#66#);
atari_keyboard(28)<=ps2_keys_reg(16#76#);
--atari_keyboard(39)<=ps2_keys_reg(16#91#);
atari_keyboard(39)<=ps2_keys_reg(16#111#);
atari_keyboard(60)<=ps2_keys_reg(16#58#);
atari_keyboard(44)<=ps2_keys_reg(16#0D#);
atari_keyboard(12)<=ps2_keys_reg(16#5A#);
atari_keyboard(33)<=ps2_keys_reg(16#29#);
atari_keyboard(54)<=ps2_keys_reg(16#4E#);
atari_keyboard(55)<=ps2_keys_reg(16#55#);
atari_keyboard(15)<=ps2_keys_reg(16#5B#);
atari_keyboard(14)<=ps2_keys_reg(16#54#);
atari_keyboard(6)<=ps2_keys_reg(16#52#);
atari_keyboard(7)<=ps2_keys_reg(16#5D#);
atari_keyboard(38)<=ps2_keys_reg(16#4A#);
atari_keyboard(2)<=ps2_keys_reg(16#4C#);
atari_keyboard(32)<=ps2_keys_reg(16#41#);
atari_keyboard(34)<=ps2_keys_reg(16#49#);
atari_keyboard(3)<=ps2_keys_reg(16#05#);
atari_keyboard(4)<=ps2_keys_reg(16#06#);
atari_keyboard(19)<=ps2_keys_reg(16#04#);
atari_keyboard(20)<=ps2_keys_reg(16#0c#);
consol_start_int<=ps2_keys_reg(16#0B#);
consol_select_int<=ps2_keys_reg(16#83#);
consol_option_int<=ps2_keys_reg(16#0a#);
shift_pressed<=ps2_keys_reg(16#12#) or ps2_keys_reg(16#59#);
--control_pressed<=ps2_keys_reg(16#14#) or ps2_keys_reg(16#94#);
control_pressed<=ps2_keys_reg(16#14#) or ps2_keys_reg(16#114#);
break_pressed<=ps2_keys_reg(16#77#);
fkeys_int(0)<=ps2_keys_reg(16#05#);
fkeys_int(1)<=ps2_keys_reg(16#06#);
fkeys_int(2)<=ps2_keys_reg(16#04#);
fkeys_int(3)<=ps2_keys_reg(16#0C#);
fkeys_int(4)<=ps2_keys_reg(16#03#);
fkeys_int(5)<=ps2_keys_reg(16#0B#);
fkeys_int(6)<=ps2_keys_reg(16#83#);
fkeys_int(7)<=ps2_keys_reg(16#0a#);
fkeys_int(8)<=ps2_keys_reg(16#01#);
fkeys_int(9)<=ps2_keys_reg(16#09#);
fkeys_int(10)<=ps2_keys_reg(16#78#);
fkeys_int(11)<=ps2_keys_reg(16#07#);
end process;
-- provide results as if we were a grid to pokey...
process(keyboard_scan, atari_keyboard, control_pressed, shift_pressed, break_pressed)
begin
keyboard_response <= (others=>'1');
if (atari_keyboard(to_integer(unsigned(not(keyboard_scan)))) = '1') then
keyboard_response(0) <= '0';
end if;
if (keyboard_scan(5 downto 4)="00" and break_pressed = '1') then
keyboard_response(1) <= '0';
end if;
if (keyboard_scan(5 downto 4)="10" and shift_pressed = '1') then
keyboard_response(1) <= '0';
end if;
if (keyboard_scan(5 downto 4)="11" and control_pressed = '1') then
keyboard_response(1) <= '0';
end if;
end process;
-- outputs
CONSOL_START <= CONSOL_START_INT;
CONSOL_SELECT <= CONSOL_SELECT_INT;
CONSOL_OPTION <= CONSOL_OPTION_INT;
FKEYS <= FKEYS_INT;
END vhdl;
| gpl-3.0 | ed3327d66cb24ec1897119debae40a81 | 0.629293 | 2.511917 | false | false | false | false |
APastorG/APG | permutation/perm_pp.vhd | 1 | 2,660 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented by
/ Altera and Xilinx in their software.
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
library work;
use work.common_pkg.all;
use work.common_data_types_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity perm_pp is
generic(
indexes : integer_v(1 to 2)
);
port(
input : in sulv_v;
start : in std_ulogic;
output : out sulv_v;
finish : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture perm_pp_1 of perm_pp is
--parallel dimensions
constant P : natural := integer(log2(real(input'length)));
constant INDEX1 : integer := indexes(1);
constant INDEX2 : integer := indexes(2);
/*================================================================================================*/
/*================================================================================================*/
begin
--control part
finish <= start;
--data part
for_every_index:
for i in input'range generate
constant aux : std_ulogic_vector(P-1 downto 0) := std_logic_vector(to_unsigned(i, P));
signal result : std_ulogic_vector(P-1 downto 0);
begin
generate_signals_permutation:
for j in result'range generate
result(j) <= aux(INDEX2) when j = INDEX1 else
aux(INDEX1) when j = INDEX2 else
aux(j);
end generate;
output(i) <= input(to_integer(unsigned(result)));
end;
end generate;
end architecture; | mit | 302b85adc2ebf65077b0a22a114b865f | 0.359482 | 4.982922 | false | false | false | false |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/syn/vhdl/sin_taylor_seriesbkb.vhd | 4 | 3,083 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity sin_taylor_seriesbkb is
generic (
ID : integer := 1;
NUM_STAGE : integer := 6;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of sin_taylor_seriesbkb is
--------------------- Component ---------------------
component sin_taylor_series_ap_dmul_4_max_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
sin_taylor_series_ap_dmul_4_max_dsp_64_u : component sin_taylor_series_ap_dmul_4_max_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| mit | 019cfd79279fe91fcc19dcd87549a3ed | 0.480376 | 3.670238 | false | false | false | false |
sonologic/gmzpu | vhdl/devices/gpio.vhdl | 1 | 2,690 | --
-- this module desribes a simple GPIO interface
--
-- data on port_in is synhronized to clk_i and can be read at
-- address 0
--
-- any write to address 0 is mapped to port_out
--
-- at address 1 is a direction register (port_dir)
-- initialized with '1's, what mean direction = in
-- this register is useful for bidirectional pins, e.g. headers
--
--
-- some examples:
--
-- to connect 4 buttons:
-- port_in( 3 downto 0) <= gpio_button;
--
--
-- to connect 8 LEDs:
-- gpio_led <= port_out(7 downto 0);
--
--
-- to connect 2 bidirectional header pins:
-- port_in(8) <= gpio_pin(0);
-- gpio_pin(0) <= port_out(8) when port_dir(8) = '0' else 'Z';
--
-- port_in(9) <= gpio_pin(1);
-- gpio_pin(1) <= port_out(9) when port_dir(9) = '0' else 'Z';
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gpio is
port(
clk_i : in std_logic;
reset_i : in std_logic;
--
we_i : in std_logic;
data_i : in unsigned(31 downto 0);
addr_i : in unsigned( 0 downto 0);
data_o : out unsigned(31 downto 0);
--
port_in : in std_logic_vector(31 downto 0);
port_out : out std_logic_vector(31 downto 0);
port_dir : out std_logic_vector(31 downto 0)
);
end entity gpio;
architecture rtl of gpio is
signal port_in_reg : std_logic_vector(31 downto 0);
signal port_in_sync : std_logic_vector(31 downto 0);
--
signal direction : std_logic_vector(31 downto 0) := (others => '1');
begin
process
begin
wait until rising_edge( clk_i);
-- synchronize all inputs with two registers
-- to avoid metastability
port_in_reg <= port_in;
port_in_sync <= port_in_reg;
-- write access to gpio
if we_i = '1' then
-- data
if addr_i = "0" then
port_out <= std_logic_vector( data_i);
end if;
-- direction
if addr_i = "1" then
direction <= std_logic_vector( data_i);
end if;
end if;
-- read access to gpio
-- data
if addr_i = "0" then
data_o <= unsigned( port_in_sync);
end if;
-- direction
if addr_i = "1" then
data_o <= unsigned( direction);
end if;
-- outputs
port_dir <= direction;
-- sync reset
if reset_i = '1' then
direction <= (others => '1');
port_in_reg <= (others => '0');
port_in_sync <= (others => '0');
port_out <= (others => '0');
end if;
end process;
end architecture rtl;
| bsd-3-clause | 67c29cf93548977fe56b306577396b37 | 0.527509 | 3.375157 | false | false | false | false |
APastorG/APG | adder/adder.vhd | 1 | 7,644 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Vivado by Xilinx
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is the interface between the instantiation of an adder an its core. It exists to make it
/ possible to use external std_ulogic_vector which contain the numeric values while having modules
/ which are able to manipulate this data as fixed point types (either u_ufixed or u_sfixed).
/ As std_ulogic_vector have a natural range and the u_ufixed and u_sfixed types have an integer
/ range ('high downto 0 is the integer part and -1 downto 'low is the fractional part) it is needed
/ a solution so as to represent the negative indexes in the std_ulogic_vector. A solution is
/ adopted where the integer indexes of the fixed point types are moved to the natural space with a
/ transformation. This consists in limiting the indexes of the fixed point data to +-2**30 and
/ adding 2**30 to obtain the std_ulogic_vector's indexes. [-2**30, 2**30]->[0, 2**31]. For example,
/ fixed point indexes (3 donwto -2) would become (1073741827, 1073741822) in a std_ulogic_vector
/ Additionally, the generics' consistency and correctness are checked in here.
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.adder_pkg.all;
use work.fixed_generic_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity adder is
generic(
UNSIGNED_2COMP_opt : boolean := false; --default
DATA_IMM_AFTER_START_opt : boolean := false; --default
SPEED_opt : T_speed := t_min; --exception: value not set
MAX_POSSIBLE_BIT_opt : integer_exc := integer'low; --exception: value not set
TRUNCATE_TO_BIT_opt : integer_exc := integer'low; --exception: value not set
S : positive --compulsory
);
port(
input : in sulv_v; --unconstrained array
clk : in std_ulogic;
start : in std_ulogic;
valid_input : in std_ulogic;
output : out std_ulogic_vector; --unconstrained array
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture adder_1 of adder is
constant P : positive := input'length(1);
constant CHECKS : integer := adder_CHECKS(MAX_POSSIBLE_BIT_opt,
TRUNCATE_TO_BIT_opt,
S,
P,
input(1)'high-SULV_NEW_ZERO,
input(1)'low-SULV_NEW_ZERO);
constant NORM_IN_HIGH : integer := input(1)'high-SULV_NEW_ZERO;
constant NORM_IN_LOW : integer := input(1)'low-SULV_NEW_ZERO;
constant NORM_OUT_HIGH : integer := adder_OH(MAX_POSSIBLE_BIT_opt,
S,
P,
NORM_IN_HIGH);
constant NORM_OUT_LOW : integer := adder_OL(TRUNCATE_TO_BIT_opt,
NORM_IN_LOW);
constant OUT_HIGH : natural := NORM_OUT_HIGH + SULV_NEW_ZERO;
constant OUT_LOW : natural := NORM_OUT_LOW + SULV_NEW_ZERO;
signal aux_input_s : u_sfixed_v(1 to P)(NORM_IN_HIGH downto NORM_IN_LOW);
signal aux_output_s : u_sfixed(NORM_OUT_HIGH downto NORM_OUT_LOW);
signal aux_input_u : u_ufixed_v(1 to P)(NORM_IN_HIGH downto NORM_IN_LOW);
signal aux_output_u : u_ufixed(NORM_OUT_HIGH downto NORM_OUT_LOW);
/*================================================================================================*/
/*================================================================================================*/
begin
msg_debug("adder_NORM_IN_HIGH: " & image(NORM_IN_HIGH));
msg_debug("adder_NORM_IN_LOW: " & image(NORM_IN_LOW));
msg_debug("adder_NORM_OUT_HIGH: " & image(NORM_OUT_HIGH));
msg_debug("adder_NORM_OUT_LOW: " & image(NORM_OUT_LOW));
msg_debug("adder_OUT_HIGH: " & image(OUT_HIGH));
msg_debug("adder_OUT_LOW: " & image(OUT_LOW));
msg_debug("adder_UNSIGNED_2COMP_opt: " & image(UNSIGNED_2COMP_opt));
adder_selection:
if UNSIGNED_2COMP_opt generate
begin
generate_input:
for i in 1 to P generate
begin
aux_input_u(i) <= to_ufixed(unsigned(input(i)), aux_input_u(i));
end;
end generate;
output(OUT_HIGH downto OUT_LOW)
<= to_sulv(aux_output_u);
adder_u_1:
entity work.adder_u
generic map(
DATA_IMM_AFTER_START_opt => DATA_IMM_AFTER_START_opt,
SPEED_opt => SPEED_opt,
MAX_POSSIBLE_BIT_opt => MAX_POSSIBLE_BIT_opt,
TRUNCATE_TO_BIT_opt => TRUNCATE_TO_BIT_opt,
S => S
)
port map(
clk => clk,
input => aux_input_u,
valid_input => valid_input,
start => start,
output => aux_output_u,
valid_output => valid_output
);
end;
else generate
begin
generate_input:
for i in 1 to P generate
begin
aux_input_s(i) <= to_sfixed(signed(input(i)), aux_input_s(i));
end;
end generate;
output(OUT_HIGH downto OUT_LOW)
<= to_sulv(aux_output_s);
adder_s_1:
entity work.adder_s
generic map(
DATA_IMM_AFTER_START_opt => DATA_IMM_AFTER_START_opt,
SPEED_opt => SPEED_opt,
MAX_POSSIBLE_BIT_opt => MAX_POSSIBLE_BIT_opt,
TRUNCATE_TO_BIT_opt => TRUNCATE_TO_BIT_opt,
S => S
)
port map(
clk => clk,
input => aux_input_s,
valid_input => valid_input,
start => start,
output => aux_output_s,
valid_output => valid_output
);
end;
end generate;
end architecture;
| mit | c28afd12d0efb970a9be9e3297c0c125 | 0.443101 | 4.294582 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/gtia_player.vhdl | 1 | 3,217 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY gtia_player IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : in std_logic;
COLOUR_ENABLE : IN STD_LOGIC;
LIVE_POSITION : in std_logic_vector(7 downto 0); -- counter ticks as display is drawn
PLAYER_POSITION : in std_logic_vector(7 downto 0); -- requested position
SIZE : in std_logic_vector(1 downto 0);
bitmap : in std_logic_vector(7 downto 0);
output : out std_logic
);
END gtia_player;
ARCHITECTURE vhdl OF gtia_player IS
-- pmgs
signal shift_next : std_logic_vector(7 downto 0);
signal shift_reg : std_logic_vector(7 downto 0);
signal count_next : std_logic_vector(1 downto 0);
signal count_reg : std_logic_vector(1 downto 0);
begin
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
shift_reg <= (others=>'0');
count_reg <= (others=>'0');
elsif (clk'event and clk='1') then
shift_reg <= shift_next;
count_reg <= count_next;
end if;
end process;
process(shift_next,COLOUR_ENABLE, live_position, player_position, size, bitmap, shift_reg, count_reg)
begin
-- size is 2 bits (00 normal, 01 twice, 10 normal(bugged), 11 four times)
-- grafp0 is 8 bits of data (2 bits for missiles)
-- hposp0_reg is position - 0x30 is left side of normal playfield, 0xd0 is right size of normal playfield
-- 'or' into shift register, so if not empty we get extra pixels
-- counter before we shift
shift_next <= shift_reg;
count_next <= count_reg;
output <= shift_next(7);
if (COLOUR_ENABLE = '1') then
case size is
when "00" => -- normal size
count_next <= "00";
shift_next <= shift_reg(6 downto 0) &'0';
when "10" => -- normal size (with bug)
case count_reg is
when "00"|"11" =>
count_next <= "00";
shift_next <= shift_reg(6 downto 0) &'0';
when "01"|"10" =>
count_next <= "10";
when others=>
--hang!
end case;
when "01" =>
case count_reg is
when "01"|"11" =>
count_next <= "00";
shift_next <= shift_reg(6 downto 0) &'0';
when "00"|"10" =>
count_next <= "01";
when others=>
--hang!
end case;
when "11" =>
case count_reg is
when "00" =>
count_next <= "01";
when "01" =>
count_next <= "10";
when "10" =>
count_next <= "11";
when "11" =>
shift_next <= shift_reg(6 downto 0) &'0';
count_next <= "00";
when others=>
--hang!
end case;
when others=>
--hang!
end case;
if (live_position = player_position) then
shift_next <= shift_reg(6 downto 0) &'0' or bitmap;
count_next <= (others=>'0');
end if;
end if;
end process;
end vhdl;
| gpl-3.0 | bc139f45812466f3c26b4d88c926cb68 | 0.563569 | 3.210579 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/host/VGA Console/video.vhd | 1 | 5,640 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity mips_video is
port (
CLK : in std_logic;
VGA_CLK : in std_logic;
RESET : in std_logic;
VA : in std_logic_vector(11 downto 0);
VDI : in std_logic_vector(7 downto 0);
VDO : out std_logic_vector(15 downto 0);
VWR : in std_logic;
VATTR : in std_logic_vector(7 downto 0);
VGA_R : out std_logic_vector(3 downto 0);
VGA_G : out std_logic_vector(3 downto 0);
VGA_B : out std_logic_vector(3 downto 0);
VGA_HSYNC : out std_logic;
VGA_VSYNC : out std_logic
);
end mips_video;
architecture Behavioral of mips_video is
signal V_COUNTER : unsigned(9 downto 0); -- Vertical Counter
signal H_COUNTER : unsigned(11 downto 0); -- Horizontal Counter
signal PAPER : std_logic;
signal PAPER_ENA : std_logic;
signal PIX : std_logic_vector(7 downto 0);
signal PIX_LT : std_logic_vector(7 downto 0);
signal ATTR : std_logic_vector(7 downto 0);
signal ATTR_LT : std_logic_vector(7 downto 0);
constant HSIZE : integer := 640; -- Paper H_size --1024
constant VSIZE : integer := 480; -- Paper V_size --768
constant HFP : integer := 16; --24;
constant HS : integer := 96; --136;
constant HB : integer := 48; --160;
constant VFP : integer := 19; --3;
constant VS : integer := 2; --6;
constant VB : integer := 33; --29;
signal FONTROM_A : std_logic_vector(11 downto 0);
signal FONTROM_DO : std_logic_vector(7 downto 0);
signal VRAM_WR : std_logic_vector(0 downto 0);
signal VRAM_RA : std_logic_vector(11 downto 0);
signal VRAM_RDO : std_logic_vector(15 downto 0);
begin
--##########################
VRAM_WR <= "1" when VWR = '1' else "0";
u_FONTROM : entity work.fontrom
port map(
clka => VGA_CLK,
addra => FONTROM_A,
douta => FONTROM_DO );
u_VRAM : entity work.mips_vram
port map(
clka => CLK,
wea => VRAM_WR,
addra => VA,
dina => VATTR & VDI,
douta => VDO,
clkb => VGA_CLK,
web => "0",
addrb => VRAM_RA,
dinb => X"0000",
doutb => VRAM_RDO );
process (VGA_CLK)
begin
if rising_edge(VGA_CLK) then
if RESET = '1' then
H_COUNTER <= (others=>'0');
V_COUNTER <= (others=>'0');
else
H_COUNTER <= H_COUNTER + 1;
if H_COUNTER = (HSIZE + HFP + HS + HB - 1) then
H_COUNTER <= (others=>'0');
V_COUNTER <= V_COUNTER + 1;
if V_COUNTER = (VSIZE + VFP + VS + VB - 1) then
V_COUNTER <= (others=>'0');
end if;
end if;
end if;
VGA_HSYNC <= '1';
VGA_VSYNC <= '1';
PAPER <= '0';
if H_COUNTER >= (HSIZE + HFP) and H_COUNTER < (HSIZE + HFP + HS)then
VGA_HSYNC <= '0';
end if;
if V_COUNTER >= (VSIZE + VFP) and V_COUNTER < (VSIZE + VFP + VS)then
VGA_VSYNC <= '0';
end if;
if H_COUNTER < HSIZE and V_COUNTER < VSIZE then
PAPER <= '1';
end if;
end if;
end process;
process (VGA_CLK)
begin
if rising_edge(VGA_CLK) then
case H_COUNTER(2 downto 0) is
when "000" =>
VRAM_RA <= std_logic_vector(V_COUNTER(8 downto 4)) & std_logic_vector(H_COUNTER(9 downto 3));
when "010" =>
FONTROM_A <= VRAM_RDO(7 downto 0) & std_logic_vector(V_COUNTER(3 downto 0));
ATTR <= VRAM_RDO(15 downto 8);
when "100" =>
PIX <= FONTROM_DO;
when "111" =>
PAPER_ENA <= PAPER;
PIX_LT <= PIX;
ATTR_LT <= ATTR;
when others => NULL;
end case;
end if;
end process;
process (VGA_CLK)
begin
if rising_edge(VGA_CLK) then
if PAPER_ENA = '1' then
if PIX_LT(7 - to_integer(H_COUNTER(2 downto 0))) = '1' then
VGA_R(3) <= ATTR_LT(2);
VGA_R(2) <= ATTR_LT(2) and ATTR_LT(3);
VGA_R(1) <= ATTR_LT(2) and ATTR_LT(3);
VGA_R(0) <= ATTR_LT(2);
VGA_G(3) <= ATTR_LT(1);
VGA_G(2) <= ATTR_LT(1) and ATTR_LT(3);
VGA_G(1) <= ATTR_LT(1) and ATTR_LT(3);
VGA_G(0) <= ATTR_LT(1);
VGA_B(3) <= ATTR_LT(0);
VGA_B(2) <= ATTR_LT(0) and ATTR_LT(3);
VGA_B(1) <= ATTR_LT(0) and ATTR_LT(3);
VGA_B(0) <= ATTR_LT(0);
else
VGA_R(3) <= ATTR_LT(6);
VGA_R(2) <= ATTR_LT(6) and ATTR_LT(7);
VGA_R(1) <= ATTR_LT(6) and ATTR_LT(7);
VGA_R(0) <= ATTR_LT(6);
VGA_G(3) <= ATTR_LT(5);
VGA_G(2) <= ATTR_LT(5) and ATTR_LT(7);
VGA_G(1) <= ATTR_LT(5) and ATTR_LT(7);
VGA_G(0) <= ATTR_LT(5);
VGA_B(3) <= ATTR_LT(4);
VGA_B(2) <= ATTR_LT(4) and ATTR_LT(7);
VGA_B(1) <= ATTR_LT(4) and ATTR_LT(7);
VGA_B(0) <= ATTR_LT(4);
end if;
else
VGA_G <= "0000";
VGA_R <= "0000";
VGA_B <= "0000";
end if;
end if;
end process;
--process (VGA_CLK)
--begin
-- if rising_edge(VGA_CLK) then
-- VGA_R <= "0000";
-- VGA_G <= "0000";
-- VGA_B <= "0000";
-- if PAPER = '1' then
-- VGA_B <= "1111";
-- end if;
-- end if;
--end process;
end Behavioral;
| gpl-3.0 | 3bd29109c7f4d474f28b45abe0ff43ea | 0.473759 | 3.083652 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk01/src/clock/clock.vhd | 1 | 6,339 | -- file: clock.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____32.500______0.000______50.0______815.385____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________50____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clock is
port
(-- Clock in ports
CLK_IN : in std_logic;
-- Clock out ports
CLK_OUT : out std_logic
);
end clock;
architecture xilinx of clock is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clock,clk_wiz_v3_6,{component_name=clock,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 20,
CLKFX_MULTIPLY => 13,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfb,
I => clk0);
clkout1_buf : BUFG
port map
(O => CLK_OUT,
I => clkfx);
end xilinx;
| gpl-3.0 | 7213e666f0407e33606ad00e0ac4aa1e | 0.556712 | 4.274444 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk01/src/xsd/xsd_rom.vhd | 1 | 5,512 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file xsd_rom.vhd when simulating
-- the core, xsd_rom. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY xsd_rom IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END xsd_rom;
ARCHITECTURE xsd_rom_a OF xsd_rom IS
-- synthesis translate_off
COMPONENT wrapped_xsd_rom
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_xsd_rom USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 11,
c_addrb_width => 11,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "xsd_rom.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 2048,
c_read_depth_b => 2048,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 2048,
c_write_depth_b => 2048,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_xsd_rom
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END xsd_rom_a;
| gpl-3.0 | 93b89784f322326ca541bf6eb19a5815 | 0.514151 | 3.914773 | false | false | false | false |
APastorG/APG | rotator/rotator_tb.vhd | 1 | 5,876 |
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Xilinx's Vivado
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.common_pkg.all;
use work.common_data_types_pkg.all;
use work.fixed_generic_pkg.all;
use work.fixed_float_types.all;
use work.complex_const_mult_pkg.all;
use work.real_const_mult_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity rotator_tb is
port(
input_real : in u_sfixed(5 downto -2);
input_imag : in u_sfixed(5 downto -2);
clk : in std_ulogic;
valid_input : in std_ulogic;
output_real : out u_sfixed(complex_const_mult_OH(round_style_opt => fixed_truncate,
round_to_bit_opt => integer'low,
max_error_pct_opt => 0.05,
max_output_bit => integer'low,
constants => (cos(80.0*MATH_PI/180.0),
sin(80.0*MATH_PI/180.0)),
input_high => 5,
input_low => -2,
is_signed => true)
downto
complex_const_mult_OL(round_style_opt => fixed_truncate,
round_to_bit_opt => integer'low,
max_error_pct_opt => 0.05,
min_output_bit => -12,
constants => (cos(80.0*MATH_PI/180.0),
sin(80.0*MATH_PI/180.0)),
input_low => -2,
is_signed => true)
);
output_imag : out u_sfixed(complex_const_mult_OH(round_style_opt => fixed_truncate,
round_to_bit_opt => integer'low,
max_error_pct_opt => 0.05,
max_output_bit => integer'low,
constants => (cos(80.0*MATH_PI/180.0),
sin(80.0*MATH_PI/180.0)),
input_high => 5,
input_low => -2,
is_signed => true)
downto
complex_const_mult_OL(round_style_opt => fixed_truncate,
round_to_bit_opt => integer'low,
max_error_pct_opt => 0.05,
min_output_bit => -12,
constants => (cos(80.0*MATH_PI/180.0),
sin(80.0*MATH_PI/180.0)),
input_low => -2,
is_signed => true)
);
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture rotator_tb_1 of rotator_tb is
/*================================================================================================*/
/*================================================================================================*/
begin
rotator_s_1:
entity work.rotator_s
generic map(
SPEED_opt => t_min,
ROUND_STYLE_opt => fixed_truncate,
--ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => 0.05,
MIN_OUTPUT_BIT => -12,
MAX_OUTPUT_BIT => 5,
ANGLE_DEGREES => 80.0
)
port map(
input_real => input_real,
input_imag => input_imag,
clk => clk,
valid_input => valid_input,
output_real => output_real,
output_imag => output_imag,
valid_output => valid_output
);
end architecture; | mit | 70c8a888ea80c2d478ae27d23c2d4a34 | 0.278501 | 5.537441 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_04200_good.vhd | 1 | 4,264 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-08 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_04200_good.vhd
-- File Creation date : 2015-04-08
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook exemple: Clock domain crossing handshake based: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--CODE
entity STD_04200_good is
generic (g_Width : positive := 4);
port (
-- A clock domain (Source)
i_ClockA : in std_logic; -- First clock signal
i_ResetA_n : in std_logic; -- Reset signal
i_Data : in std_logic_vector(g_Width-1 downto 0); -- Data from source
i_Request : in std_logic; -- Request from source
o_Grant : out std_logic; -- Acknowledge synced to source
-- B clock domain (Destination)
i_ClockB : in std_logic; -- Second clock signal
i_ResetB_n : in std_logic; -- Reset signal
o_Data : out std_logic_vector(g_Width-1 downto 0); -- Data to destination
o_Request_r2 : out std_logic; -- Request synced to destination
i_Grant : in std_logic -- Acknowledge from destination
);
end STD_04200_good;
architecture Behavioral of STD_04200_good is
signal Request_r1 : std_logic; -- Request signal registered 1 time
signal Request_r2 : std_logic; -- Request signal registered 2 times
signal Grant_r1 : std_logic; -- Grant signal registered 1 time
signal Grant_r2 : std_logic; -- Grant signal registered 2 times
begin
P_Source_Domain : process(i_ResetA_n, i_ClockA)
begin
if (i_ResetA_n = '0') then
Grant_r1 <= '0';
Grant_r2 <= '0';
elsif (rising_edge(i_ClockA)) then
-- Synchronize i_Grant to i_ClockA domain
Grant_r1 <= i_Grant;
Grant_r2 <= Grant_r1;
end if;
end process;
P_Destination_Domain : process(i_ResetB_n, i_ClockB)
begin
if (i_ResetB_n = '0') then
Request_r1 <= '0';
Request_r2 <= '0';
elsif (rising_edge(i_ClockB)) then
-- Synchronize i_Request to i_ClockB domain
-- Data is valid when Request_r2 is asserted
Request_r1 <= i_Request;
Request_r2 <= Request_r1;
end if;
end process;
o_Request_r2 <= Request_r2;
o_Data <= i_Data;
o_Grant <= Grant_r2;
end Behavioral;
--CODE
| gpl-3.0 | ce6ccb27dec891b99fbbf28fcbf25da0 | 0.516417 | 4.16 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_01300_bad.vhd | 1 | 2,583 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-02 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_01300_bad.vhd
-- File Creation date : 2015-04-02
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Number of ports declaration per line: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.pkg_HBK.all;
--CODE
entity STD_01300_bad is
port (
i_Clock, i_Reset_n, i_D : in std_logic; -- Clock, reset & D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end STD_01300_bad;
architecture Behavioral of STD_01300_bad is
begin
DFlipFlop1 : DFlipFlop
port map (
i_Clock => i_Clock, i_Reset_n => i_Reset_n, i_D => i_D, o_Q => o_Q, o_Q_n => open
);
end Behavioral;
--CODE
| gpl-3.0 | f88abb58b54d99def6da7fc559b4b05d | 0.476578 | 4.587922 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/korvet/src/cache/cache.vhd | 1 | 1,163 | library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity cache is
port
(
CLK : in std_logic;
AI : in std_logic_vector(5 downto 0);
DI : in std_logic_vector(31 downto 0);
WE : in std_logic := '1';
AO : in std_logic_vector(5 downto 0);
DO : out std_logic_vector(31 downto 0);
CACHE : in std_logic
);
end cache;
architecture rtl of cache is
signal CACHE_ACTIVE : std_logic := '0';
subtype word_t is std_logic_vector(31 downto 0);
type memory_t is array(0 to 127) of word_t;
shared variable ram : memory_t;
begin
process(CLK)
begin
if rising_edge(CLK) then
if CACHE = '1' then
CACHE_ACTIVE <= not CACHE_ACTIVE;
end if;
end if;
end process;
process(CLK)
begin
if rising_edge(CLK) then
if WE = '1' then
ram(to_integer(unsigned(CACHE_ACTIVE & AI))) := DI;
end if;
end if;
end process;
process(CLK)
begin
if rising_edge(CLK) then
DO <= ram(to_integer(unsigned(not CACHE_ACTIVE & AO)));
end if;
end process;
end rtl;
| gpl-3.0 | c4029d4f52468240564ca35b91e64632 | 0.563199 | 3.410557 | false | false | false | false |
sonologic/gmzpu | vhdl/roms/zwc_test.vhdl | 1 | 68,688 | ------------------------------------------------------------------------------
---- ----
---- Single Port RAM that maps to a Xilinx BRAM ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- This is a program+data memory for the ZPU. It maps to a Xilinx BRAM ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: SinglePortRAM(Xilinx) (Entity and architecture) ----
---- File name: rom_s.in.vhdl (template used) ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity SinglePortRAM is
generic(
WORD_SIZE : integer:=32; -- Word Size 16/32
BYTE_BITS : integer:=2; -- Bits used to address bytes
BRAM_W : integer:=15); -- Address Width
port(
clk_i : in std_logic;
we_i : in std_logic;
re_i : in std_logic;
addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
write_i : in unsigned(WORD_SIZE-1 downto 0);
read_o : out unsigned(WORD_SIZE-1 downto 0);
busy_o : out std_logic);
end entity SinglePortRAM;
architecture Xilinx of SinglePortRAM is
type ram_type is array(natural range 0 to ((2**BRAM_W)/4)-1) of unsigned(WORD_SIZE-1 downto 0);
signal addr_r : unsigned(BRAM_W-1 downto BYTE_BITS);
signal ram : ram_type :=
(
0 => x"0b0b0b0b",
1 => x"82700b0b",
2 => x"80d1b80c",
3 => x"3a0b0b80",
4 => x"c9ab0400",
5 => x"00000000",
6 => x"00000000",
7 => x"00000000",
8 => x"0b0b0b89",
9 => x"90040000",
10 => x"00000000",
11 => x"00000000",
12 => x"00000000",
13 => x"00000000",
14 => x"00000000",
15 => x"00000000",
16 => x"71fd0608",
17 => x"72830609",
18 => x"81058205",
19 => x"832b2a83",
20 => x"ffff0652",
21 => x"04000000",
22 => x"00000000",
23 => x"00000000",
24 => x"71fd0608",
25 => x"83ffff73",
26 => x"83060981",
27 => x"05820583",
28 => x"2b2b0906",
29 => x"7383ffff",
30 => x"0b0b0b0b",
31 => x"83a70400",
32 => x"72098105",
33 => x"72057373",
34 => x"09060906",
35 => x"73097306",
36 => x"070a8106",
37 => x"53510400",
38 => x"00000000",
39 => x"00000000",
40 => x"72722473",
41 => x"732e0753",
42 => x"51040000",
43 => x"00000000",
44 => x"00000000",
45 => x"00000000",
46 => x"00000000",
47 => x"00000000",
48 => x"71737109",
49 => x"71068106",
50 => x"30720a10",
51 => x"0a720a10",
52 => x"0a31050a",
53 => x"81065151",
54 => x"53510400",
55 => x"00000000",
56 => x"72722673",
57 => x"732e0753",
58 => x"51040000",
59 => x"00000000",
60 => x"00000000",
61 => x"00000000",
62 => x"00000000",
63 => x"00000000",
64 => x"00000000",
65 => x"00000000",
66 => x"00000000",
67 => x"00000000",
68 => x"00000000",
69 => x"00000000",
70 => x"00000000",
71 => x"00000000",
72 => x"0b0b0b88",
73 => x"c4040000",
74 => x"00000000",
75 => x"00000000",
76 => x"00000000",
77 => x"00000000",
78 => x"00000000",
79 => x"00000000",
80 => x"720a722b",
81 => x"0a535104",
82 => x"00000000",
83 => x"00000000",
84 => x"00000000",
85 => x"00000000",
86 => x"00000000",
87 => x"00000000",
88 => x"72729f06",
89 => x"0981050b",
90 => x"0b0b88a7",
91 => x"05040000",
92 => x"00000000",
93 => x"00000000",
94 => x"00000000",
95 => x"00000000",
96 => x"72722aff",
97 => x"739f062a",
98 => x"0974090a",
99 => x"8106ff05",
100 => x"06075351",
101 => x"04000000",
102 => x"00000000",
103 => x"00000000",
104 => x"71715351",
105 => x"020d0406",
106 => x"73830609",
107 => x"81058205",
108 => x"832b0b2b",
109 => x"0772fc06",
110 => x"0c515104",
111 => x"00000000",
112 => x"72098105",
113 => x"72050970",
114 => x"81050906",
115 => x"0a810653",
116 => x"51040000",
117 => x"00000000",
118 => x"00000000",
119 => x"00000000",
120 => x"72098105",
121 => x"72050970",
122 => x"81050906",
123 => x"0a098106",
124 => x"53510400",
125 => x"00000000",
126 => x"00000000",
127 => x"00000000",
128 => x"71098105",
129 => x"52040000",
130 => x"00000000",
131 => x"00000000",
132 => x"00000000",
133 => x"00000000",
134 => x"00000000",
135 => x"00000000",
136 => x"72720981",
137 => x"05055351",
138 => x"04000000",
139 => x"00000000",
140 => x"00000000",
141 => x"00000000",
142 => x"00000000",
143 => x"00000000",
144 => x"72097206",
145 => x"73730906",
146 => x"07535104",
147 => x"00000000",
148 => x"00000000",
149 => x"00000000",
150 => x"00000000",
151 => x"00000000",
152 => x"71fc0608",
153 => x"72830609",
154 => x"81058305",
155 => x"1010102a",
156 => x"81ff0652",
157 => x"04000000",
158 => x"00000000",
159 => x"00000000",
160 => x"71fc0608",
161 => x"0b0b80d0",
162 => x"ec738306",
163 => x"10100508",
164 => x"060b0b0b",
165 => x"88aa0400",
166 => x"00000000",
167 => x"00000000",
168 => x"0b0b0b88",
169 => x"f8040000",
170 => x"00000000",
171 => x"00000000",
172 => x"00000000",
173 => x"00000000",
174 => x"00000000",
175 => x"00000000",
176 => x"0b0b0b88",
177 => x"e0040000",
178 => x"00000000",
179 => x"00000000",
180 => x"00000000",
181 => x"00000000",
182 => x"00000000",
183 => x"00000000",
184 => x"72097081",
185 => x"0509060a",
186 => x"8106ff05",
187 => x"70547106",
188 => x"73097274",
189 => x"05ff0506",
190 => x"07515151",
191 => x"04000000",
192 => x"72097081",
193 => x"0509060a",
194 => x"098106ff",
195 => x"05705471",
196 => x"06730972",
197 => x"7405ff05",
198 => x"06075151",
199 => x"51040000",
200 => x"05ff0504",
201 => x"00000000",
202 => x"00000000",
203 => x"00000000",
204 => x"00000000",
205 => x"00000000",
206 => x"00000000",
207 => x"00000000",
208 => x"810b0b0b",
209 => x"80d1b40c",
210 => x"51040000",
211 => x"00000000",
212 => x"00000000",
213 => x"00000000",
214 => x"00000000",
215 => x"00000000",
216 => x"71810552",
217 => x"04000000",
218 => x"00000000",
219 => x"00000000",
220 => x"00000000",
221 => x"00000000",
222 => x"00000000",
223 => x"00000000",
224 => x"00000000",
225 => x"00000000",
226 => x"00000000",
227 => x"00000000",
228 => x"00000000",
229 => x"00000000",
230 => x"00000000",
231 => x"00000000",
232 => x"02840572",
233 => x"10100552",
234 => x"04000000",
235 => x"00000000",
236 => x"00000000",
237 => x"00000000",
238 => x"00000000",
239 => x"00000000",
240 => x"00000000",
241 => x"00000000",
242 => x"00000000",
243 => x"00000000",
244 => x"00000000",
245 => x"00000000",
246 => x"00000000",
247 => x"00000000",
248 => x"717105ff",
249 => x"05715351",
250 => x"020d0400",
251 => x"00000000",
252 => x"00000000",
253 => x"00000000",
254 => x"00000000",
255 => x"00000000",
256 => x"83853f80",
257 => x"c8b93f04",
258 => x"10101010",
259 => x"10101010",
260 => x"10101010",
261 => x"10101010",
262 => x"10101010",
263 => x"10101010",
264 => x"10101010",
265 => x"10101053",
266 => x"51047381",
267 => x"ff067383",
268 => x"06098105",
269 => x"83051010",
270 => x"102b0772",
271 => x"fc060c51",
272 => x"51043c04",
273 => x"72728072",
274 => x"8106ff05",
275 => x"09720605",
276 => x"71105272",
277 => x"0a100a53",
278 => x"72ed3851",
279 => x"51535104",
280 => x"b008b408",
281 => x"b8087575",
282 => x"90db2d50",
283 => x"50b00856",
284 => x"b80cb40c",
285 => x"b00c5104",
286 => x"b008b408",
287 => x"b8087575",
288 => x"8fa92d50",
289 => x"50b00856",
290 => x"b80cb40c",
291 => x"b00c5104",
292 => x"b008b408",
293 => x"b8088bb6",
294 => x"2db80cb4",
295 => x"0cb00c04",
296 => x"fe3d0d0b",
297 => x"0b80e1a4",
298 => x"08538413",
299 => x"0870882a",
300 => x"70810651",
301 => x"52527080",
302 => x"2ef03871",
303 => x"81ff06b0",
304 => x"0c843d0d",
305 => x"04ff3d0d",
306 => x"0b0b80e1",
307 => x"a4085271",
308 => x"0870882a",
309 => x"81327081",
310 => x"06515151",
311 => x"70f13873",
312 => x"720c833d",
313 => x"0d0480d1",
314 => x"b408802e",
315 => x"a43880d1",
316 => x"b808822e",
317 => x"bd388380",
318 => x"800b0b0b",
319 => x"80e1a40c",
320 => x"82a0800b",
321 => x"80e1a80c",
322 => x"8290800b",
323 => x"80e1ac0c",
324 => x"04f88080",
325 => x"80a40b0b",
326 => x"0b80e1a4",
327 => x"0cf88080",
328 => x"82800b80",
329 => x"e1a80cf8",
330 => x"80808480",
331 => x"0b80e1ac",
332 => x"0c0480c0",
333 => x"a8808c0b",
334 => x"0b0b80e1",
335 => x"a40c80c0",
336 => x"a880940b",
337 => x"80e1a80c",
338 => x"80d0fc0b",
339 => x"80e1ac0c",
340 => x"04ff3d0d",
341 => x"80e1b033",
342 => x"5170a738",
343 => x"80d1c008",
344 => x"70085252",
345 => x"70802e94",
346 => x"38841280",
347 => x"d1c00c70",
348 => x"2d80d1c0",
349 => x"08700852",
350 => x"5270ee38",
351 => x"810b80e1",
352 => x"b034833d",
353 => x"0d040480",
354 => x"3d0d0b0b",
355 => x"80e1a008",
356 => x"802e8e38",
357 => x"0b0b0b0b",
358 => x"800b802e",
359 => x"09810685",
360 => x"38823d0d",
361 => x"040b0b80",
362 => x"e1a0510b",
363 => x"0b0bf4d0",
364 => x"3f823d0d",
365 => x"0404803d",
366 => x"0d80e1bc",
367 => x"08811180",
368 => x"e1bc0c51",
369 => x"823d0d04",
370 => x"f73d0d7b",
371 => x"54870b89",
372 => x"3d80d1c4",
373 => x"08585855",
374 => x"7417748f",
375 => x"06175353",
376 => x"71337334",
377 => x"73842aff",
378 => x"16565474",
379 => x"8025e938",
380 => x"800b8b3d",
381 => x"34765189",
382 => x"853f8b3d",
383 => x"0d04e13d",
384 => x"0d80e1bc",
385 => x"089f3d9d",
386 => x"3d9b3d99",
387 => x"3d973d95",
388 => x"3d8c8080",
389 => x"088c8084",
390 => x"088e8080",
391 => x"0880d194",
392 => x"5b415f57",
393 => x"5f5f5f5f",
394 => x"5f5f5288",
395 => x"d13f7154",
396 => x"870b80d1",
397 => x"c4085755",
398 => x"741e748f",
399 => x"06175353",
400 => x"71337334",
401 => x"73842aff",
402 => x"16565474",
403 => x"8025e938",
404 => x"800ba13d",
405 => x"347d5188",
406 => x"a53f80d1",
407 => x"9851889e",
408 => x"3f765487",
409 => x"0b80d1c4",
410 => x"08575574",
411 => x"1d748f06",
412 => x"17545772",
413 => x"33773473",
414 => x"842aff16",
415 => x"56547480",
416 => x"25e93880",
417 => x"0b9e3d34",
418 => x"7c5187f2",
419 => x"3f80d19c",
420 => x"5187eb3f",
421 => x"7754870b",
422 => x"80d1c408",
423 => x"5755741c",
424 => x"748f0617",
425 => x"53587133",
426 => x"78347384",
427 => x"2aff1656",
428 => x"54748025",
429 => x"e938800b",
430 => x"9b3d347b",
431 => x"5187bf3f",
432 => x"f8bb9586",
433 => x"a10b8c80",
434 => x"800c8191",
435 => x"d1acf80b",
436 => x"8c80840c",
437 => x"f9d5f3bd",
438 => x"f00b8e80",
439 => x"800c8c80",
440 => x"80088c80",
441 => x"84088e80",
442 => x"800880d1",
443 => x"94545a58",
444 => x"55878b3f",
445 => x"7454870b",
446 => x"80d1c408",
447 => x"5755741b",
448 => x"748f0617",
449 => x"53537133",
450 => x"73347384",
451 => x"2aff1656",
452 => x"54748025",
453 => x"e938800b",
454 => x"983d347a",
455 => x"5186df3f",
456 => x"80d19851",
457 => x"86d83f76",
458 => x"54870b80",
459 => x"d1c40857",
460 => x"55741a74",
461 => x"8f061754",
462 => x"57723377",
463 => x"3473842a",
464 => x"ff165654",
465 => x"748025e9",
466 => x"38800b95",
467 => x"3d347951",
468 => x"86ac3f80",
469 => x"d19c5186",
470 => x"a53f7754",
471 => x"870b80d1",
472 => x"c4085755",
473 => x"7419748f",
474 => x"06175358",
475 => x"71337834",
476 => x"73842aff",
477 => x"16565474",
478 => x"8025e938",
479 => x"800b923d",
480 => x"34785185",
481 => x"f93f8c80",
482 => x"80088c80",
483 => x"84088e80",
484 => x"800880d1",
485 => x"94545a58",
486 => x"5285e33f",
487 => x"7154870b",
488 => x"80d1c408",
489 => x"5755fd90",
490 => x"39bc0802",
491 => x"bc0cf93d",
492 => x"0d800bbc",
493 => x"08fc050c",
494 => x"bc088805",
495 => x"088025ab",
496 => x"38bc0888",
497 => x"050830bc",
498 => x"0888050c",
499 => x"800bbc08",
500 => x"f4050cbc",
501 => x"08fc0508",
502 => x"8838810b",
503 => x"bc08f405",
504 => x"0cbc08f4",
505 => x"0508bc08",
506 => x"fc050cbc",
507 => x"088c0508",
508 => x"8025ab38",
509 => x"bc088c05",
510 => x"0830bc08",
511 => x"8c050c80",
512 => x"0bbc08f0",
513 => x"050cbc08",
514 => x"fc050888",
515 => x"38810bbc",
516 => x"08f0050c",
517 => x"bc08f005",
518 => x"08bc08fc",
519 => x"050c8053",
520 => x"bc088c05",
521 => x"0852bc08",
522 => x"88050851",
523 => x"81a73fb0",
524 => x"0870bc08",
525 => x"f8050c54",
526 => x"bc08fc05",
527 => x"08802e8c",
528 => x"38bc08f8",
529 => x"050830bc",
530 => x"08f8050c",
531 => x"bc08f805",
532 => x"0870b00c",
533 => x"54893d0d",
534 => x"bc0c04bc",
535 => x"0802bc0c",
536 => x"fb3d0d80",
537 => x"0bbc08fc",
538 => x"050cbc08",
539 => x"88050880",
540 => x"259338bc",
541 => x"08880508",
542 => x"30bc0888",
543 => x"050c810b",
544 => x"bc08fc05",
545 => x"0cbc088c",
546 => x"05088025",
547 => x"8c38bc08",
548 => x"8c050830",
549 => x"bc088c05",
550 => x"0c8153bc",
551 => x"088c0508",
552 => x"52bc0888",
553 => x"050851ad",
554 => x"3fb00870",
555 => x"bc08f805",
556 => x"0c54bc08",
557 => x"fc050880",
558 => x"2e8c38bc",
559 => x"08f80508",
560 => x"30bc08f8",
561 => x"050cbc08",
562 => x"f8050870",
563 => x"b00c5487",
564 => x"3d0dbc0c",
565 => x"04bc0802",
566 => x"bc0cfd3d",
567 => x"0d810bbc",
568 => x"08fc050c",
569 => x"800bbc08",
570 => x"f8050cbc",
571 => x"088c0508",
572 => x"bc088805",
573 => x"0827ac38",
574 => x"bc08fc05",
575 => x"08802ea3",
576 => x"38800bbc",
577 => x"088c0508",
578 => x"249938bc",
579 => x"088c0508",
580 => x"10bc088c",
581 => x"050cbc08",
582 => x"fc050810",
583 => x"bc08fc05",
584 => x"0cc939bc",
585 => x"08fc0508",
586 => x"802e80c9",
587 => x"38bc088c",
588 => x"0508bc08",
589 => x"88050826",
590 => x"a138bc08",
591 => x"880508bc",
592 => x"088c0508",
593 => x"31bc0888",
594 => x"050cbc08",
595 => x"f80508bc",
596 => x"08fc0508",
597 => x"07bc08f8",
598 => x"050cbc08",
599 => x"fc050881",
600 => x"2abc08fc",
601 => x"050cbc08",
602 => x"8c050881",
603 => x"2abc088c",
604 => x"050cffaf",
605 => x"39bc0890",
606 => x"0508802e",
607 => x"8f38bc08",
608 => x"88050870",
609 => x"bc08f405",
610 => x"0c518d39",
611 => x"bc08f805",
612 => x"0870bc08",
613 => x"f4050c51",
614 => x"bc08f405",
615 => x"08b00c85",
616 => x"3d0dbc0c",
617 => x"04fc3d0d",
618 => x"7670797b",
619 => x"55555555",
620 => x"8f72278c",
621 => x"38727507",
622 => x"83065170",
623 => x"802ea738",
624 => x"ff125271",
625 => x"ff2e9838",
626 => x"72708105",
627 => x"54337470",
628 => x"81055634",
629 => x"ff125271",
630 => x"ff2e0981",
631 => x"06ea3874",
632 => x"b00c863d",
633 => x"0d047451",
634 => x"72708405",
635 => x"54087170",
636 => x"8405530c",
637 => x"72708405",
638 => x"54087170",
639 => x"8405530c",
640 => x"72708405",
641 => x"54087170",
642 => x"8405530c",
643 => x"72708405",
644 => x"54087170",
645 => x"8405530c",
646 => x"f0125271",
647 => x"8f26c938",
648 => x"83722795",
649 => x"38727084",
650 => x"05540871",
651 => x"70840553",
652 => x"0cfc1252",
653 => x"718326ed",
654 => x"387054ff",
655 => x"8339f73d",
656 => x"0d7c7052",
657 => x"5380c83f",
658 => x"7254b008",
659 => x"5580d1a0",
660 => x"568157b0",
661 => x"0881055a",
662 => x"8b3de411",
663 => x"59538259",
664 => x"f413527b",
665 => x"88110852",
666 => x"5381833f",
667 => x"b0083070",
668 => x"b008079f",
669 => x"2c8a07b0",
670 => x"0c538b3d",
671 => x"0d04ff3d",
672 => x"0d735280",
673 => x"d1c80851",
674 => x"ffb43f83",
675 => x"3d0d04fd",
676 => x"3d0d7570",
677 => x"71830653",
678 => x"555270b8",
679 => x"38717008",
680 => x"7009f7fb",
681 => x"fdff1206",
682 => x"70f88482",
683 => x"81800651",
684 => x"51525370",
685 => x"9d388413",
686 => x"70087009",
687 => x"f7fbfdff",
688 => x"120670f8",
689 => x"84828180",
690 => x"06515152",
691 => x"5370802e",
692 => x"e5387252",
693 => x"71335170",
694 => x"802e8a38",
695 => x"81127033",
696 => x"525270f8",
697 => x"38717431",
698 => x"b00c853d",
699 => x"0d04f23d",
700 => x"0d606288",
701 => x"11087057",
702 => x"575f5a74",
703 => x"802e818f",
704 => x"388c1a22",
705 => x"70832a81",
706 => x"32708106",
707 => x"51555873",
708 => x"8638901a",
709 => x"08913879",
710 => x"5190a13f",
711 => x"ff54b008",
712 => x"80ed388c",
713 => x"1a22587d",
714 => x"08578078",
715 => x"83ffff06",
716 => x"70812a70",
717 => x"81065156",
718 => x"57557375",
719 => x"2e80d738",
720 => x"74903876",
721 => x"08841808",
722 => x"88195956",
723 => x"5974802e",
724 => x"f2387454",
725 => x"88807527",
726 => x"84388880",
727 => x"54735378",
728 => x"529c1a08",
729 => x"51a41a08",
730 => x"54732d80",
731 => x"0bb00825",
732 => x"82e638b0",
733 => x"081975b0",
734 => x"08317f88",
735 => x"0508b008",
736 => x"31706188",
737 => x"050c5656",
738 => x"5973ffb4",
739 => x"38805473",
740 => x"b00c903d",
741 => x"0d047581",
742 => x"32708106",
743 => x"76415154",
744 => x"73802e81",
745 => x"c1387490",
746 => x"38760884",
747 => x"18088819",
748 => x"59565974",
749 => x"802ef238",
750 => x"881a0878",
751 => x"83ffff06",
752 => x"70892a70",
753 => x"81065156",
754 => x"59567380",
755 => x"2e82fa38",
756 => x"7575278d",
757 => x"3877872a",
758 => x"70810651",
759 => x"547382b5",
760 => x"38747627",
761 => x"83387456",
762 => x"75537852",
763 => x"79085185",
764 => x"823f881a",
765 => x"08763188",
766 => x"1b0c7908",
767 => x"167a0c74",
768 => x"56751975",
769 => x"77317f88",
770 => x"05087831",
771 => x"70618805",
772 => x"0c565659",
773 => x"73802efe",
774 => x"f4388c1a",
775 => x"2258ff86",
776 => x"39777854",
777 => x"79537b52",
778 => x"5684c83f",
779 => x"881a0878",
780 => x"31881b0c",
781 => x"7908187a",
782 => x"0c7c7631",
783 => x"5d7c8e38",
784 => x"79518fdb",
785 => x"3fb00881",
786 => x"8f38b008",
787 => x"5f751975",
788 => x"77317f88",
789 => x"05087831",
790 => x"70618805",
791 => x"0c565659",
792 => x"73802efe",
793 => x"a8387481",
794 => x"83387608",
795 => x"84180888",
796 => x"19595659",
797 => x"74802ef2",
798 => x"3874538a",
799 => x"52785182",
800 => x"d33fb008",
801 => x"79318105",
802 => x"5db00884",
803 => x"3881155d",
804 => x"815f7c58",
805 => x"747d2783",
806 => x"38745894",
807 => x"1a08881b",
808 => x"0811575c",
809 => x"807a085c",
810 => x"54901a08",
811 => x"7b278338",
812 => x"81547578",
813 => x"25843873",
814 => x"ba387b78",
815 => x"24fee238",
816 => x"7b537852",
817 => x"9c1a0851",
818 => x"a41a0854",
819 => x"732db008",
820 => x"56b00880",
821 => x"24fee238",
822 => x"8c1a2280",
823 => x"c0075473",
824 => x"8c1b23ff",
825 => x"5473b00c",
826 => x"903d0d04",
827 => x"7effa338",
828 => x"ff873975",
829 => x"5378527a",
830 => x"5182f83f",
831 => x"7908167a",
832 => x"0c79518e",
833 => x"9a3fb008",
834 => x"cf387c76",
835 => x"315d7cfe",
836 => x"bc38feac",
837 => x"39901a08",
838 => x"7a087131",
839 => x"76117056",
840 => x"5a575280",
841 => x"d1c80851",
842 => x"848c3fb0",
843 => x"08802eff",
844 => x"a738b008",
845 => x"901b0cb0",
846 => x"08167a0c",
847 => x"77941b0c",
848 => x"74881b0c",
849 => x"7456fd99",
850 => x"39790858",
851 => x"901a0878",
852 => x"27833881",
853 => x"54757527",
854 => x"843873b3",
855 => x"38941a08",
856 => x"56757526",
857 => x"80d33875",
858 => x"5378529c",
859 => x"1a0851a4",
860 => x"1a085473",
861 => x"2db00856",
862 => x"b0088024",
863 => x"fd83388c",
864 => x"1a2280c0",
865 => x"0754738c",
866 => x"1b23ff54",
867 => x"fed73975",
868 => x"53785277",
869 => x"5181dc3f",
870 => x"7908167a",
871 => x"0c79518c",
872 => x"fe3fb008",
873 => x"802efcd9",
874 => x"388c1a22",
875 => x"80c00754",
876 => x"738c1b23",
877 => x"ff54fead",
878 => x"39747554",
879 => x"79537852",
880 => x"5681b03f",
881 => x"881a0875",
882 => x"31881b0c",
883 => x"7908157a",
884 => x"0cfcae39",
885 => x"fa3d0d7a",
886 => x"79028805",
887 => x"a7053356",
888 => x"52538373",
889 => x"278a3870",
890 => x"83065271",
891 => x"802ea838",
892 => x"ff135372",
893 => x"ff2e9738",
894 => x"70335273",
895 => x"722e9138",
896 => x"8111ff14",
897 => x"545172ff",
898 => x"2e098106",
899 => x"eb388051",
900 => x"70b00c88",
901 => x"3d0d0470",
902 => x"72575583",
903 => x"51758280",
904 => x"2914ff12",
905 => x"52567080",
906 => x"25f33883",
907 => x"7327bf38",
908 => x"74087632",
909 => x"7009f7fb",
910 => x"fdff1206",
911 => x"70f88482",
912 => x"81800651",
913 => x"51517080",
914 => x"2e993874",
915 => x"51805270",
916 => x"33577377",
917 => x"2effb938",
918 => x"81118113",
919 => x"53518372",
920 => x"27ed38fc",
921 => x"13841656",
922 => x"53728326",
923 => x"c3387451",
924 => x"fefe39fa",
925 => x"3d0d787a",
926 => x"7c727272",
927 => x"57575759",
928 => x"56567476",
929 => x"27b23876",
930 => x"15517571",
931 => x"27aa3870",
932 => x"7717ff14",
933 => x"54555371",
934 => x"ff2e9638",
935 => x"ff14ff14",
936 => x"54547233",
937 => x"7434ff12",
938 => x"5271ff2e",
939 => x"098106ec",
940 => x"3875b00c",
941 => x"883d0d04",
942 => x"768f2697",
943 => x"38ff1252",
944 => x"71ff2eed",
945 => x"38727081",
946 => x"05543374",
947 => x"70810556",
948 => x"34eb3974",
949 => x"76078306",
950 => x"5170e238",
951 => x"75755451",
952 => x"72708405",
953 => x"54087170",
954 => x"8405530c",
955 => x"72708405",
956 => x"54087170",
957 => x"8405530c",
958 => x"72708405",
959 => x"54087170",
960 => x"8405530c",
961 => x"72708405",
962 => x"54087170",
963 => x"8405530c",
964 => x"f0125271",
965 => x"8f26c938",
966 => x"83722795",
967 => x"38727084",
968 => x"05540871",
969 => x"70840553",
970 => x"0cfc1252",
971 => x"718326ed",
972 => x"387054ff",
973 => x"8839ef3d",
974 => x"0d636567",
975 => x"405d427b",
976 => x"802e84fa",
977 => x"386151a5",
978 => x"b43ff81c",
979 => x"70841208",
980 => x"70fc0670",
981 => x"628b0570",
982 => x"f8064159",
983 => x"455b5c41",
984 => x"57967427",
985 => x"82c33880",
986 => x"7b247e7c",
987 => x"26075980",
988 => x"5478742e",
989 => x"09810682",
990 => x"a938777b",
991 => x"2581fc38",
992 => x"771780d9",
993 => x"840b8805",
994 => x"085e567c",
995 => x"762e84bd",
996 => x"38841608",
997 => x"70fe0617",
998 => x"84110881",
999 => x"06515555",
1000 => x"73828b38",
1001 => x"74fc0659",
1002 => x"7c762e84",
1003 => x"dd387719",
1004 => x"5f7e7b25",
1005 => x"81fd3879",
1006 => x"81065473",
1007 => x"82bf3876",
1008 => x"77083184",
1009 => x"1108fc06",
1010 => x"565a7580",
1011 => x"2e91387c",
1012 => x"762e84ea",
1013 => x"38741918",
1014 => x"59787b25",
1015 => x"84893879",
1016 => x"802e8299",
1017 => x"38771556",
1018 => x"7a762482",
1019 => x"90388c1a",
1020 => x"08881b08",
1021 => x"718c120c",
1022 => x"88120c55",
1023 => x"79765957",
1024 => x"881761fc",
1025 => x"05575975",
1026 => x"a42685ef",
1027 => x"387b7955",
1028 => x"55937627",
1029 => x"80c9387b",
1030 => x"7084055d",
1031 => x"087c5679",
1032 => x"0c747084",
1033 => x"0556088c",
1034 => x"180c9017",
1035 => x"549b7627",
1036 => x"ae387470",
1037 => x"84055608",
1038 => x"740c7470",
1039 => x"84055608",
1040 => x"94180c98",
1041 => x"1754a376",
1042 => x"27953874",
1043 => x"70840556",
1044 => x"08740c74",
1045 => x"70840556",
1046 => x"089c180c",
1047 => x"a0175474",
1048 => x"70840556",
1049 => x"08747084",
1050 => x"05560c74",
1051 => x"70840556",
1052 => x"08747084",
1053 => x"05560c74",
1054 => x"08740c77",
1055 => x"7b315675",
1056 => x"8f2680c9",
1057 => x"38841708",
1058 => x"81067807",
1059 => x"84180c77",
1060 => x"17841108",
1061 => x"81078412",
1062 => x"0c546151",
1063 => x"a2e03f88",
1064 => x"175473b0",
1065 => x"0c933d0d",
1066 => x"04905bfd",
1067 => x"ba397856",
1068 => x"fe85398c",
1069 => x"16088817",
1070 => x"08718c12",
1071 => x"0c88120c",
1072 => x"557e707c",
1073 => x"3157588f",
1074 => x"7627ffb9",
1075 => x"387a1784",
1076 => x"18088106",
1077 => x"7c078419",
1078 => x"0c768107",
1079 => x"84120c76",
1080 => x"11841108",
1081 => x"81078412",
1082 => x"0c558805",
1083 => x"5261518c",
1084 => x"f63f6151",
1085 => x"a2883f88",
1086 => x"1754ffa6",
1087 => x"397d5261",
1088 => x"5194f53f",
1089 => x"b00859b0",
1090 => x"08802e81",
1091 => x"a338b008",
1092 => x"f8056084",
1093 => x"0508fe06",
1094 => x"61055557",
1095 => x"76742e83",
1096 => x"e638fc18",
1097 => x"5675a426",
1098 => x"81aa387b",
1099 => x"b0085555",
1100 => x"93762780",
1101 => x"d8387470",
1102 => x"84055608",
1103 => x"b0087084",
1104 => x"05b00c0c",
1105 => x"b0087570",
1106 => x"84055708",
1107 => x"71708405",
1108 => x"530c549b",
1109 => x"7627b638",
1110 => x"74708405",
1111 => x"56087470",
1112 => x"8405560c",
1113 => x"74708405",
1114 => x"56087470",
1115 => x"8405560c",
1116 => x"a3762799",
1117 => x"38747084",
1118 => x"05560874",
1119 => x"70840556",
1120 => x"0c747084",
1121 => x"05560874",
1122 => x"70840556",
1123 => x"0c747084",
1124 => x"05560874",
1125 => x"70840556",
1126 => x"0c747084",
1127 => x"05560874",
1128 => x"70840556",
1129 => x"0c740874",
1130 => x"0c7b5261",
1131 => x"518bb83f",
1132 => x"6151a0ca",
1133 => x"3f785473",
1134 => x"b00c933d",
1135 => x"0d047d52",
1136 => x"615193b4",
1137 => x"3fb008b0",
1138 => x"0c933d0d",
1139 => x"04841608",
1140 => x"55fbd139",
1141 => x"75537b52",
1142 => x"b00851ef",
1143 => x"c83f7b52",
1144 => x"61518b83",
1145 => x"3fca398c",
1146 => x"16088817",
1147 => x"08718c12",
1148 => x"0c88120c",
1149 => x"558c1a08",
1150 => x"881b0871",
1151 => x"8c120c88",
1152 => x"120c5579",
1153 => x"795957fb",
1154 => x"f7397719",
1155 => x"901c5555",
1156 => x"737524fb",
1157 => x"a2387a17",
1158 => x"7080d984",
1159 => x"0b88050c",
1160 => x"757c3181",
1161 => x"0784120c",
1162 => x"5d841708",
1163 => x"81067b07",
1164 => x"84180c61",
1165 => x"519fc73f",
1166 => x"881754fc",
1167 => x"e5397419",
1168 => x"18901c55",
1169 => x"5d737d24",
1170 => x"fb95388c",
1171 => x"1a08881b",
1172 => x"08718c12",
1173 => x"0c88120c",
1174 => x"55881a61",
1175 => x"fc055759",
1176 => x"75a42681",
1177 => x"ae387b79",
1178 => x"55559376",
1179 => x"2780c938",
1180 => x"7b708405",
1181 => x"5d087c56",
1182 => x"790c7470",
1183 => x"84055608",
1184 => x"8c1b0c90",
1185 => x"1a549b76",
1186 => x"27ae3874",
1187 => x"70840556",
1188 => x"08740c74",
1189 => x"70840556",
1190 => x"08941b0c",
1191 => x"981a54a3",
1192 => x"76279538",
1193 => x"74708405",
1194 => x"5608740c",
1195 => x"74708405",
1196 => x"56089c1b",
1197 => x"0ca01a54",
1198 => x"74708405",
1199 => x"56087470",
1200 => x"8405560c",
1201 => x"74708405",
1202 => x"56087470",
1203 => x"8405560c",
1204 => x"7408740c",
1205 => x"7a1a7080",
1206 => x"d9840b88",
1207 => x"050c7d7c",
1208 => x"31810784",
1209 => x"120c5484",
1210 => x"1a088106",
1211 => x"7b07841b",
1212 => x"0c61519e",
1213 => x"893f7854",
1214 => x"fdbd3975",
1215 => x"537b5278",
1216 => x"51eda23f",
1217 => x"faf53984",
1218 => x"1708fc06",
1219 => x"18605858",
1220 => x"fae93975",
1221 => x"537b5278",
1222 => x"51ed8a3f",
1223 => x"7a1a7080",
1224 => x"d9840b88",
1225 => x"050c7d7c",
1226 => x"31810784",
1227 => x"120c5484",
1228 => x"1a088106",
1229 => x"7b07841b",
1230 => x"0cffb639",
1231 => x"fa3d0d78",
1232 => x"80d1c808",
1233 => x"5455b813",
1234 => x"08802e81",
1235 => x"b5388c15",
1236 => x"227083ff",
1237 => x"ff067083",
1238 => x"2a813270",
1239 => x"81065155",
1240 => x"55567280",
1241 => x"2e80dc38",
1242 => x"73842a81",
1243 => x"32810657",
1244 => x"ff537680",
1245 => x"f6387382",
1246 => x"2a708106",
1247 => x"51537280",
1248 => x"2eb938b0",
1249 => x"15085473",
1250 => x"802e9c38",
1251 => x"80c01553",
1252 => x"73732e8f",
1253 => x"38735280",
1254 => x"d1c80851",
1255 => x"87c93f8c",
1256 => x"15225676",
1257 => x"b0160c75",
1258 => x"db065372",
1259 => x"8c162380",
1260 => x"0b84160c",
1261 => x"90150875",
1262 => x"0c725675",
1263 => x"88075372",
1264 => x"8c162390",
1265 => x"1508802e",
1266 => x"80c0388c",
1267 => x"15227081",
1268 => x"06555373",
1269 => x"9d387281",
1270 => x"2a708106",
1271 => x"51537285",
1272 => x"38941508",
1273 => x"54738816",
1274 => x"0c805372",
1275 => x"b00c883d",
1276 => x"0d04800b",
1277 => x"88160c94",
1278 => x"15083098",
1279 => x"160c8053",
1280 => x"ea397251",
1281 => x"82fb3ffe",
1282 => x"c5397451",
1283 => x"8ce83f8c",
1284 => x"15227081",
1285 => x"06555373",
1286 => x"802effba",
1287 => x"38d439f8",
1288 => x"3d0d7a58",
1289 => x"77802e81",
1290 => x"993880d1",
1291 => x"c80854b8",
1292 => x"1408802e",
1293 => x"80ed388c",
1294 => x"18227090",
1295 => x"2b70902c",
1296 => x"70832a81",
1297 => x"3281065c",
1298 => x"51575478",
1299 => x"80cd3890",
1300 => x"18085776",
1301 => x"802e80c3",
1302 => x"38770877",
1303 => x"3177790c",
1304 => x"7683067a",
1305 => x"58555573",
1306 => x"85389418",
1307 => x"08567588",
1308 => x"190c8075",
1309 => x"25a53874",
1310 => x"5376529c",
1311 => x"180851a4",
1312 => x"18085473",
1313 => x"2d800bb0",
1314 => x"082580c9",
1315 => x"38b00817",
1316 => x"75b00831",
1317 => x"56577480",
1318 => x"24dd3880",
1319 => x"0bb00c8a",
1320 => x"3d0d0473",
1321 => x"5181da3f",
1322 => x"8c182270",
1323 => x"902b7090",
1324 => x"2c70832a",
1325 => x"81328106",
1326 => x"5c515754",
1327 => x"78dd38ff",
1328 => x"8e39a89f",
1329 => x"5280d1c8",
1330 => x"085189f1",
1331 => x"3fb008b0",
1332 => x"0c8a3d0d",
1333 => x"048c1822",
1334 => x"80c00754",
1335 => x"738c1923",
1336 => x"ff0bb00c",
1337 => x"8a3d0d04",
1338 => x"803d0d72",
1339 => x"5180710c",
1340 => x"800b8412",
1341 => x"0c800b88",
1342 => x"120c028e",
1343 => x"05228c12",
1344 => x"23029205",
1345 => x"228e1223",
1346 => x"800b9012",
1347 => x"0c800b94",
1348 => x"120c800b",
1349 => x"98120c70",
1350 => x"9c120c80",
1351 => x"c4b30ba0",
1352 => x"120c80c4",
1353 => x"ff0ba412",
1354 => x"0c80c5fb",
1355 => x"0ba8120c",
1356 => x"80c6cc0b",
1357 => x"ac120c82",
1358 => x"3d0d04fa",
1359 => x"3d0d7970",
1360 => x"80dc298c",
1361 => x"11547a53",
1362 => x"56578cac",
1363 => x"3fb008b0",
1364 => x"085556b0",
1365 => x"08802ea2",
1366 => x"38b0088c",
1367 => x"0554800b",
1368 => x"b0080c76",
1369 => x"b0088405",
1370 => x"0c73b008",
1371 => x"88050c74",
1372 => x"53805273",
1373 => x"5197f73f",
1374 => x"755473b0",
1375 => x"0c883d0d",
1376 => x"04fc3d0d",
1377 => x"76ad940b",
1378 => x"bc120c55",
1379 => x"810bb816",
1380 => x"0c800b84",
1381 => x"dc160c83",
1382 => x"0b84e016",
1383 => x"0c84e815",
1384 => x"84e4160c",
1385 => x"74548053",
1386 => x"84528415",
1387 => x"0851feb8",
1388 => x"3f745481",
1389 => x"53895288",
1390 => x"150851fe",
1391 => x"ab3f7454",
1392 => x"82538a52",
1393 => x"8c150851",
1394 => x"fe9e3f86",
1395 => x"3d0d04f9",
1396 => x"3d0d7980",
1397 => x"d1c80854",
1398 => x"57b81308",
1399 => x"802e80c8",
1400 => x"3884dc13",
1401 => x"56881608",
1402 => x"841708ff",
1403 => x"05555580",
1404 => x"74249f38",
1405 => x"8c152270",
1406 => x"902b7090",
1407 => x"2c515458",
1408 => x"72802e80",
1409 => x"ca3880dc",
1410 => x"15ff1555",
1411 => x"55738025",
1412 => x"e3387508",
1413 => x"5372802e",
1414 => x"9f387256",
1415 => x"88160884",
1416 => x"1708ff05",
1417 => x"5555c839",
1418 => x"7251fed5",
1419 => x"3f80d1c8",
1420 => x"0884dc05",
1421 => x"56ffae39",
1422 => x"84527651",
1423 => x"fdfd3fb0",
1424 => x"08760cb0",
1425 => x"08802e80",
1426 => x"c038b008",
1427 => x"56ce3981",
1428 => x"0b8c1623",
1429 => x"72750c72",
1430 => x"88160c72",
1431 => x"84160c72",
1432 => x"90160c72",
1433 => x"94160c72",
1434 => x"98160cff",
1435 => x"0b8e1623",
1436 => x"72b0160c",
1437 => x"72b4160c",
1438 => x"7280c416",
1439 => x"0c7280c8",
1440 => x"160c74b0",
1441 => x"0c893d0d",
1442 => x"048c770c",
1443 => x"800bb00c",
1444 => x"893d0d04",
1445 => x"ff3d0da8",
1446 => x"9f527351",
1447 => x"869f3f83",
1448 => x"3d0d0480",
1449 => x"3d0d80d1",
1450 => x"c80851e8",
1451 => x"3f823d0d",
1452 => x"04fb3d0d",
1453 => x"77705256",
1454 => x"96c33f80",
1455 => x"d9840b88",
1456 => x"05088411",
1457 => x"08fc0670",
1458 => x"7b319fef",
1459 => x"05e08006",
1460 => x"e0800556",
1461 => x"5653a080",
1462 => x"74249438",
1463 => x"80527551",
1464 => x"969d3f80",
1465 => x"d98c0815",
1466 => x"5372b008",
1467 => x"2e8f3875",
1468 => x"51968b3f",
1469 => x"805372b0",
1470 => x"0c873d0d",
1471 => x"04733052",
1472 => x"755195fb",
1473 => x"3fb008ff",
1474 => x"2ea83880",
1475 => x"d9840b88",
1476 => x"05087575",
1477 => x"31810784",
1478 => x"120c5380",
1479 => x"d8c80874",
1480 => x"3180d8c8",
1481 => x"0c755195",
1482 => x"d53f810b",
1483 => x"b00c873d",
1484 => x"0d048052",
1485 => x"755195c7",
1486 => x"3f80d984",
1487 => x"0b880508",
1488 => x"b0087131",
1489 => x"56538f75",
1490 => x"25ffa438",
1491 => x"b00880d8",
1492 => x"f8083180",
1493 => x"d8c80c74",
1494 => x"81078414",
1495 => x"0c755195",
1496 => x"9d3f8053",
1497 => x"ff9039f6",
1498 => x"3d0d7c7e",
1499 => x"545b7280",
1500 => x"2e828338",
1501 => x"7a519585",
1502 => x"3ff81384",
1503 => x"110870fe",
1504 => x"06701384",
1505 => x"1108fc06",
1506 => x"5d585954",
1507 => x"5880d98c",
1508 => x"08752e82",
1509 => x"de387884",
1510 => x"160c8073",
1511 => x"8106545a",
1512 => x"727a2e81",
1513 => x"d5387815",
1514 => x"84110881",
1515 => x"06515372",
1516 => x"a0387817",
1517 => x"577981e6",
1518 => x"38881508",
1519 => x"537280d9",
1520 => x"8c2e82f9",
1521 => x"388c1508",
1522 => x"708c150c",
1523 => x"7388120c",
1524 => x"56768107",
1525 => x"84190c76",
1526 => x"1877710c",
1527 => x"53798191",
1528 => x"3883ff77",
1529 => x"2781c838",
1530 => x"76892a77",
1531 => x"832a5653",
1532 => x"72802ebf",
1533 => x"3876862a",
1534 => x"b8055584",
1535 => x"7327b438",
1536 => x"80db1355",
1537 => x"947327ab",
1538 => x"38768c2a",
1539 => x"80ee0555",
1540 => x"80d47327",
1541 => x"9e38768f",
1542 => x"2a80f705",
1543 => x"5582d473",
1544 => x"27913876",
1545 => x"922a80fc",
1546 => x"05558ad4",
1547 => x"73278438",
1548 => x"80fe5574",
1549 => x"10101080",
1550 => x"d9840588",
1551 => x"11085556",
1552 => x"73762e82",
1553 => x"b3388414",
1554 => x"08fc0653",
1555 => x"7673278d",
1556 => x"38881408",
1557 => x"5473762e",
1558 => x"098106ea",
1559 => x"388c1408",
1560 => x"708c1a0c",
1561 => x"74881a0c",
1562 => x"7888120c",
1563 => x"56778c15",
1564 => x"0c7a5193",
1565 => x"893f8c3d",
1566 => x"0d047708",
1567 => x"78713159",
1568 => x"77058819",
1569 => x"08545772",
1570 => x"80d98c2e",
1571 => x"80e0388c",
1572 => x"1808708c",
1573 => x"150c7388",
1574 => x"120c56fe",
1575 => x"89398815",
1576 => x"088c1608",
1577 => x"708c130c",
1578 => x"5788170c",
1579 => x"fea33976",
1580 => x"832a7054",
1581 => x"55807524",
1582 => x"81983872",
1583 => x"822c8171",
1584 => x"2b80d988",
1585 => x"080780d9",
1586 => x"840b8405",
1587 => x"0c537410",
1588 => x"101080d9",
1589 => x"84058811",
1590 => x"08555675",
1591 => x"8c190c73",
1592 => x"88190c77",
1593 => x"88170c77",
1594 => x"8c150cff",
1595 => x"8439815a",
1596 => x"fdb43978",
1597 => x"17738106",
1598 => x"54577298",
1599 => x"38770878",
1600 => x"71315977",
1601 => x"058c1908",
1602 => x"881a0871",
1603 => x"8c120c88",
1604 => x"120c5757",
1605 => x"76810784",
1606 => x"190c7780",
1607 => x"d9840b88",
1608 => x"050c80d9",
1609 => x"80087726",
1610 => x"fec73880",
1611 => x"d8fc0852",
1612 => x"7a51fafd",
1613 => x"3f7a5191",
1614 => x"c53ffeba",
1615 => x"3981788c",
1616 => x"150c7888",
1617 => x"150c738c",
1618 => x"1a0c7388",
1619 => x"1a0c5afd",
1620 => x"80398315",
1621 => x"70822c81",
1622 => x"712b80d9",
1623 => x"88080780",
1624 => x"d9840b84",
1625 => x"050c5153",
1626 => x"74101010",
1627 => x"80d98405",
1628 => x"88110855",
1629 => x"56fee439",
1630 => x"74538075",
1631 => x"24a73872",
1632 => x"822c8171",
1633 => x"2b80d988",
1634 => x"080780d9",
1635 => x"840b8405",
1636 => x"0c53758c",
1637 => x"190c7388",
1638 => x"190c7788",
1639 => x"170c778c",
1640 => x"150cfdcd",
1641 => x"39831570",
1642 => x"822c8171",
1643 => x"2b80d988",
1644 => x"080780d9",
1645 => x"840b8405",
1646 => x"0c5153d6",
1647 => x"39f93d0d",
1648 => x"797b5853",
1649 => x"800b80d1",
1650 => x"c8085356",
1651 => x"72722e80",
1652 => x"c03884dc",
1653 => x"13557476",
1654 => x"2eb73888",
1655 => x"15088416",
1656 => x"08ff0554",
1657 => x"54807324",
1658 => x"9d388c14",
1659 => x"2270902b",
1660 => x"70902c51",
1661 => x"53587180",
1662 => x"d83880dc",
1663 => x"14ff1454",
1664 => x"54728025",
1665 => x"e5387408",
1666 => x"5574d038",
1667 => x"80d1c808",
1668 => x"5284dc12",
1669 => x"5574802e",
1670 => x"b1388815",
1671 => x"08841608",
1672 => x"ff055454",
1673 => x"8073249c",
1674 => x"388c1422",
1675 => x"70902b70",
1676 => x"902c5153",
1677 => x"5871ad38",
1678 => x"80dc14ff",
1679 => x"14545472",
1680 => x"8025e638",
1681 => x"74085574",
1682 => x"d13875b0",
1683 => x"0c893d0d",
1684 => x"04735176",
1685 => x"2d75b008",
1686 => x"0780dc15",
1687 => x"ff155555",
1688 => x"56ff9e39",
1689 => x"7351762d",
1690 => x"75b00807",
1691 => x"80dc15ff",
1692 => x"15555556",
1693 => x"ca39ea3d",
1694 => x"0d688c11",
1695 => x"2270812a",
1696 => x"81065758",
1697 => x"567480e4",
1698 => x"388e1622",
1699 => x"70902b70",
1700 => x"902c5155",
1701 => x"58807424",
1702 => x"b138983d",
1703 => x"c4055373",
1704 => x"5280d1c8",
1705 => x"085192ac",
1706 => x"3f800bb0",
1707 => x"08249738",
1708 => x"7983e080",
1709 => x"06547380",
1710 => x"c0802e81",
1711 => x"8f387382",
1712 => x"80802e81",
1713 => x"91388c16",
1714 => x"22577690",
1715 => x"80075473",
1716 => x"8c172388",
1717 => x"805280d1",
1718 => x"c8085181",
1719 => x"9b3fb008",
1720 => x"9d388c16",
1721 => x"22820754",
1722 => x"738c1723",
1723 => x"80c31670",
1724 => x"770c9017",
1725 => x"0c810b94",
1726 => x"170c983d",
1727 => x"0d0480d1",
1728 => x"c808ad94",
1729 => x"0bbc120c",
1730 => x"548c1622",
1731 => x"81800754",
1732 => x"738c1723",
1733 => x"b008760c",
1734 => x"b0089017",
1735 => x"0c88800b",
1736 => x"94170c74",
1737 => x"802ed338",
1738 => x"8e162270",
1739 => x"902b7090",
1740 => x"2c535558",
1741 => x"98ae3fb0",
1742 => x"08802eff",
1743 => x"bd388c16",
1744 => x"22810754",
1745 => x"738c1723",
1746 => x"983d0d04",
1747 => x"810b8c17",
1748 => x"225855fe",
1749 => x"f539a816",
1750 => x"0880c5fb",
1751 => x"2e098106",
1752 => x"fee4388c",
1753 => x"16228880",
1754 => x"0754738c",
1755 => x"17238880",
1756 => x"0b80cc17",
1757 => x"0cfedc39",
1758 => x"f33d0d7f",
1759 => x"618b1170",
1760 => x"f8065c55",
1761 => x"555e7296",
1762 => x"26833890",
1763 => x"59807924",
1764 => x"747a2607",
1765 => x"53805472",
1766 => x"742e0981",
1767 => x"0680cb38",
1768 => x"7d518cd9",
1769 => x"3f7883f7",
1770 => x"2680c638",
1771 => x"78832a70",
1772 => x"10101080",
1773 => x"d984058c",
1774 => x"11085959",
1775 => x"5a76782e",
1776 => x"83b03884",
1777 => x"1708fc06",
1778 => x"568c1708",
1779 => x"88180871",
1780 => x"8c120c88",
1781 => x"120c5875",
1782 => x"17841108",
1783 => x"81078412",
1784 => x"0c537d51",
1785 => x"8c983f88",
1786 => x"175473b0",
1787 => x"0c8f3d0d",
1788 => x"0478892a",
1789 => x"79832a5b",
1790 => x"5372802e",
1791 => x"bf387886",
1792 => x"2ab8055a",
1793 => x"847327b4",
1794 => x"3880db13",
1795 => x"5a947327",
1796 => x"ab38788c",
1797 => x"2a80ee05",
1798 => x"5a80d473",
1799 => x"279e3878",
1800 => x"8f2a80f7",
1801 => x"055a82d4",
1802 => x"73279138",
1803 => x"78922a80",
1804 => x"fc055a8a",
1805 => x"d4732784",
1806 => x"3880fe5a",
1807 => x"79101010",
1808 => x"80d98405",
1809 => x"8c110858",
1810 => x"5576752e",
1811 => x"a3388417",
1812 => x"08fc0670",
1813 => x"7a315556",
1814 => x"738f2488",
1815 => x"d5387380",
1816 => x"25fee638",
1817 => x"8c170857",
1818 => x"76752e09",
1819 => x"8106df38",
1820 => x"811a5a80",
1821 => x"d9940857",
1822 => x"7680d98c",
1823 => x"2e82c038",
1824 => x"841708fc",
1825 => x"06707a31",
1826 => x"5556738f",
1827 => x"2481f938",
1828 => x"80d98c0b",
1829 => x"80d9980c",
1830 => x"80d98c0b",
1831 => x"80d9940c",
1832 => x"738025fe",
1833 => x"b23883ff",
1834 => x"762783df",
1835 => x"3875892a",
1836 => x"76832a55",
1837 => x"5372802e",
1838 => x"bf387586",
1839 => x"2ab80554",
1840 => x"847327b4",
1841 => x"3880db13",
1842 => x"54947327",
1843 => x"ab38758c",
1844 => x"2a80ee05",
1845 => x"5480d473",
1846 => x"279e3875",
1847 => x"8f2a80f7",
1848 => x"055482d4",
1849 => x"73279138",
1850 => x"75922a80",
1851 => x"fc05548a",
1852 => x"d4732784",
1853 => x"3880fe54",
1854 => x"73101010",
1855 => x"80d98405",
1856 => x"88110856",
1857 => x"5874782e",
1858 => x"86cf3884",
1859 => x"1508fc06",
1860 => x"53757327",
1861 => x"8d388815",
1862 => x"08557478",
1863 => x"2e098106",
1864 => x"ea388c15",
1865 => x"0880d984",
1866 => x"0b840508",
1867 => x"718c1a0c",
1868 => x"76881a0c",
1869 => x"7888130c",
1870 => x"788c180c",
1871 => x"5d587953",
1872 => x"807a2483",
1873 => x"e6387282",
1874 => x"2c81712b",
1875 => x"5c537a7c",
1876 => x"26819838",
1877 => x"7b7b0653",
1878 => x"7282f138",
1879 => x"79fc0684",
1880 => x"055a7a10",
1881 => x"707d0654",
1882 => x"5b7282e0",
1883 => x"38841a5a",
1884 => x"f1398817",
1885 => x"8c110858",
1886 => x"5876782e",
1887 => x"098106fc",
1888 => x"c238821a",
1889 => x"5afdec39",
1890 => x"78177981",
1891 => x"0784190c",
1892 => x"7080d998",
1893 => x"0c7080d9",
1894 => x"940c80d9",
1895 => x"8c0b8c12",
1896 => x"0c8c1108",
1897 => x"88120c74",
1898 => x"81078412",
1899 => x"0c741175",
1900 => x"710c5153",
1901 => x"7d5188c6",
1902 => x"3f881754",
1903 => x"fcac3980",
1904 => x"d9840b84",
1905 => x"05087a54",
1906 => x"5c798025",
1907 => x"fef83882",
1908 => x"da397a09",
1909 => x"7c067080",
1910 => x"d9840b84",
1911 => x"050c5c7a",
1912 => x"105b7a7c",
1913 => x"2685387a",
1914 => x"85b83880",
1915 => x"d9840b88",
1916 => x"05087084",
1917 => x"1208fc06",
1918 => x"707c317c",
1919 => x"72268f72",
1920 => x"25075757",
1921 => x"5c5d5572",
1922 => x"802e80db",
1923 => x"38797a16",
1924 => x"80d8fc08",
1925 => x"1b90115a",
1926 => x"55575b80",
1927 => x"d8f808ff",
1928 => x"2e8838a0",
1929 => x"8f13e080",
1930 => x"06577652",
1931 => x"7d5187cf",
1932 => x"3fb00854",
1933 => x"b008ff2e",
1934 => x"9038b008",
1935 => x"76278299",
1936 => x"387480d9",
1937 => x"842e8291",
1938 => x"3880d984",
1939 => x"0b880508",
1940 => x"55841508",
1941 => x"fc06707a",
1942 => x"317a7226",
1943 => x"8f722507",
1944 => x"52555372",
1945 => x"83e63874",
1946 => x"79810784",
1947 => x"170c7916",
1948 => x"7080d984",
1949 => x"0b88050c",
1950 => x"75810784",
1951 => x"120c547e",
1952 => x"525786fa",
1953 => x"3f881754",
1954 => x"fae03975",
1955 => x"832a7054",
1956 => x"54807424",
1957 => x"819b3872",
1958 => x"822c8171",
1959 => x"2b80d988",
1960 => x"08077080",
1961 => x"d9840b84",
1962 => x"050c7510",
1963 => x"101080d9",
1964 => x"84058811",
1965 => x"08585a5d",
1966 => x"53778c18",
1967 => x"0c748818",
1968 => x"0c768819",
1969 => x"0c768c16",
1970 => x"0cfcf339",
1971 => x"797a1010",
1972 => x"1080d984",
1973 => x"05705759",
1974 => x"5d8c1508",
1975 => x"5776752e",
1976 => x"a3388417",
1977 => x"08fc0670",
1978 => x"7a315556",
1979 => x"738f2483",
1980 => x"ca387380",
1981 => x"25848138",
1982 => x"8c170857",
1983 => x"76752e09",
1984 => x"8106df38",
1985 => x"8815811b",
1986 => x"70830655",
1987 => x"5b5572c9",
1988 => x"387c8306",
1989 => x"5372802e",
1990 => x"fdb838ff",
1991 => x"1df81959",
1992 => x"5d881808",
1993 => x"782eea38",
1994 => x"fdb53983",
1995 => x"1a53fc96",
1996 => x"39831470",
1997 => x"822c8171",
1998 => x"2b80d988",
1999 => x"08077080",
2000 => x"d9840b84",
2001 => x"050c7610",
2002 => x"101080d9",
2003 => x"84058811",
2004 => x"08595b5e",
2005 => x"5153fee1",
2006 => x"3980d8c8",
2007 => x"081758b0",
2008 => x"08762e81",
2009 => x"8d3880d8",
2010 => x"f808ff2e",
2011 => x"83ec3873",
2012 => x"76311880",
2013 => x"d8c80c73",
2014 => x"87067057",
2015 => x"5372802e",
2016 => x"88388873",
2017 => x"31701555",
2018 => x"5676149f",
2019 => x"ff06a080",
2020 => x"71311770",
2021 => x"547f5357",
2022 => x"5384e43f",
2023 => x"b00853b0",
2024 => x"08ff2e81",
2025 => x"a03880d8",
2026 => x"c8081670",
2027 => x"80d8c80c",
2028 => x"747580d9",
2029 => x"840b8805",
2030 => x"0c747631",
2031 => x"18708107",
2032 => x"51555658",
2033 => x"7b80d984",
2034 => x"2e839c38",
2035 => x"798f2682",
2036 => x"cb38810b",
2037 => x"84150c84",
2038 => x"1508fc06",
2039 => x"707a317a",
2040 => x"72268f72",
2041 => x"25075255",
2042 => x"5372802e",
2043 => x"fcf93880",
2044 => x"db39b008",
2045 => x"9fff0653",
2046 => x"72feeb38",
2047 => x"7780d8c8",
2048 => x"0c80d984",
2049 => x"0b880508",
2050 => x"7b188107",
2051 => x"84120c55",
2052 => x"80d8f408",
2053 => x"78278638",
2054 => x"7780d8f4",
2055 => x"0c80d8f0",
2056 => x"087827fc",
2057 => x"ac387780",
2058 => x"d8f00c84",
2059 => x"1508fc06",
2060 => x"707a317a",
2061 => x"72268f72",
2062 => x"25075255",
2063 => x"5372802e",
2064 => x"fca53888",
2065 => x"39807454",
2066 => x"56fedb39",
2067 => x"7d5183ae",
2068 => x"3f800bb0",
2069 => x"0c8f3d0d",
2070 => x"04735380",
2071 => x"7424a938",
2072 => x"72822c81",
2073 => x"712b80d9",
2074 => x"88080770",
2075 => x"80d9840b",
2076 => x"84050c5d",
2077 => x"53778c18",
2078 => x"0c748818",
2079 => x"0c768819",
2080 => x"0c768c16",
2081 => x"0cf9b739",
2082 => x"83147082",
2083 => x"2c81712b",
2084 => x"80d98808",
2085 => x"077080d9",
2086 => x"840b8405",
2087 => x"0c5e5153",
2088 => x"d4397b7b",
2089 => x"065372fc",
2090 => x"a338841a",
2091 => x"7b105c5a",
2092 => x"f139ff1a",
2093 => x"8111515a",
2094 => x"f7b93978",
2095 => x"17798107",
2096 => x"84190c8c",
2097 => x"18088819",
2098 => x"08718c12",
2099 => x"0c88120c",
2100 => x"597080d9",
2101 => x"980c7080",
2102 => x"d9940c80",
2103 => x"d98c0b8c",
2104 => x"120c8c11",
2105 => x"0888120c",
2106 => x"74810784",
2107 => x"120c7411",
2108 => x"75710c51",
2109 => x"53f9bd39",
2110 => x"75178411",
2111 => x"08810784",
2112 => x"120c538c",
2113 => x"17088818",
2114 => x"08718c12",
2115 => x"0c88120c",
2116 => x"587d5181",
2117 => x"e93f8817",
2118 => x"54f5cf39",
2119 => x"7284150c",
2120 => x"f41af806",
2121 => x"70841e08",
2122 => x"81060784",
2123 => x"1e0c701d",
2124 => x"545b850b",
2125 => x"84140c85",
2126 => x"0b88140c",
2127 => x"8f7b27fd",
2128 => x"cf38881c",
2129 => x"527d51ec",
2130 => x"9e3f80d9",
2131 => x"840b8805",
2132 => x"0880d8c8",
2133 => x"085955fd",
2134 => x"b7397780",
2135 => x"d8c80c73",
2136 => x"80d8f80c",
2137 => x"fc913972",
2138 => x"84150cfd",
2139 => x"a339fc3d",
2140 => x"0d767971",
2141 => x"028c059f",
2142 => x"05335755",
2143 => x"53558372",
2144 => x"278a3874",
2145 => x"83065170",
2146 => x"802ea238",
2147 => x"ff125271",
2148 => x"ff2e9338",
2149 => x"73737081",
2150 => x"055534ff",
2151 => x"125271ff",
2152 => x"2e098106",
2153 => x"ef3874b0",
2154 => x"0c863d0d",
2155 => x"04747488",
2156 => x"2b750770",
2157 => x"71902b07",
2158 => x"5154518f",
2159 => x"7227a538",
2160 => x"72717084",
2161 => x"05530c72",
2162 => x"71708405",
2163 => x"530c7271",
2164 => x"70840553",
2165 => x"0c727170",
2166 => x"8405530c",
2167 => x"f0125271",
2168 => x"8f26dd38",
2169 => x"83722790",
2170 => x"38727170",
2171 => x"8405530c",
2172 => x"fc125271",
2173 => x"8326f238",
2174 => x"7053ff90",
2175 => x"390404fd",
2176 => x"3d0d800b",
2177 => x"80e1c00c",
2178 => x"765184ee",
2179 => x"3fb00853",
2180 => x"b008ff2e",
2181 => x"883872b0",
2182 => x"0c853d0d",
2183 => x"0480e1c0",
2184 => x"08547380",
2185 => x"2ef03875",
2186 => x"74710c52",
2187 => x"72b00c85",
2188 => x"3d0d04f9",
2189 => x"3d0d797c",
2190 => x"557b548e",
2191 => x"11227090",
2192 => x"2b70902c",
2193 => x"555780d1",
2194 => x"c8085358",
2195 => x"5683f33f",
2196 => x"b0085780",
2197 => x"0bb00824",
2198 => x"933880d0",
2199 => x"1608b008",
2200 => x"0580d017",
2201 => x"0c76b00c",
2202 => x"893d0d04",
2203 => x"8c162283",
2204 => x"dfff0655",
2205 => x"748c1723",
2206 => x"76b00c89",
2207 => x"3d0d04fa",
2208 => x"3d0d788c",
2209 => x"11227088",
2210 => x"2a708106",
2211 => x"51575856",
2212 => x"74a9388c",
2213 => x"162283df",
2214 => x"ff065574",
2215 => x"8c17237a",
2216 => x"5479538e",
2217 => x"16227090",
2218 => x"2b70902c",
2219 => x"545680d1",
2220 => x"c8085256",
2221 => x"81b23f88",
2222 => x"3d0d0482",
2223 => x"5480538e",
2224 => x"16227090",
2225 => x"2b70902c",
2226 => x"545680d1",
2227 => x"c8085257",
2228 => x"82b83f8c",
2229 => x"162283df",
2230 => x"ff065574",
2231 => x"8c17237a",
2232 => x"5479538e",
2233 => x"16227090",
2234 => x"2b70902c",
2235 => x"545680d1",
2236 => x"c8085256",
2237 => x"80f23f88",
2238 => x"3d0d04f9",
2239 => x"3d0d797c",
2240 => x"557b548e",
2241 => x"11227090",
2242 => x"2b70902c",
2243 => x"555780d1",
2244 => x"c8085358",
2245 => x"5681f33f",
2246 => x"b00857b0",
2247 => x"08ff2e99",
2248 => x"388c1622",
2249 => x"a0800755",
2250 => x"748c1723",
2251 => x"b00880d0",
2252 => x"170c76b0",
2253 => x"0c893d0d",
2254 => x"048c1622",
2255 => x"83dfff06",
2256 => x"55748c17",
2257 => x"2376b00c",
2258 => x"893d0d04",
2259 => x"fe3d0d74",
2260 => x"8e112270",
2261 => x"902b7090",
2262 => x"2c555151",
2263 => x"5380d1c8",
2264 => x"0851bd3f",
2265 => x"843d0d04",
2266 => x"fb3d0d80",
2267 => x"0b80e1c0",
2268 => x"0c7a5379",
2269 => x"52785182",
2270 => x"fb3fb008",
2271 => x"55b008ff",
2272 => x"2e883874",
2273 => x"b00c873d",
2274 => x"0d0480e1",
2275 => x"c0085675",
2276 => x"802ef038",
2277 => x"7776710c",
2278 => x"5474b00c",
2279 => x"873d0d04",
2280 => x"fd3d0d80",
2281 => x"0b80e1c0",
2282 => x"0c765184",
2283 => x"d03fb008",
2284 => x"53b008ff",
2285 => x"2e883872",
2286 => x"b00c853d",
2287 => x"0d0480e1",
2288 => x"c0085473",
2289 => x"802ef038",
2290 => x"7574710c",
2291 => x"5272b00c",
2292 => x"853d0d04",
2293 => x"fc3d0d80",
2294 => x"0b80e1c0",
2295 => x"0c785277",
2296 => x"5186b83f",
2297 => x"b00854b0",
2298 => x"08ff2e88",
2299 => x"3873b00c",
2300 => x"863d0d04",
2301 => x"80e1c008",
2302 => x"5574802e",
2303 => x"f0387675",
2304 => x"710c5373",
2305 => x"b00c863d",
2306 => x"0d04fb3d",
2307 => x"0d800b80",
2308 => x"e1c00c7a",
2309 => x"53795278",
2310 => x"5184943f",
2311 => x"b00855b0",
2312 => x"08ff2e88",
2313 => x"3874b00c",
2314 => x"873d0d04",
2315 => x"80e1c008",
2316 => x"5675802e",
2317 => x"f0387776",
2318 => x"710c5474",
2319 => x"b00c873d",
2320 => x"0d04fb3d",
2321 => x"0d800b80",
2322 => x"e1c00c7a",
2323 => x"53795278",
2324 => x"5182993f",
2325 => x"b00855b0",
2326 => x"08ff2e88",
2327 => x"3874b00c",
2328 => x"873d0d04",
2329 => x"80e1c008",
2330 => x"5675802e",
2331 => x"f0387776",
2332 => x"710c5474",
2333 => x"b00c873d",
2334 => x"0d04fe3d",
2335 => x"0d80e1b4",
2336 => x"0851708a",
2337 => x"3880e1c4",
2338 => x"7080e1b4",
2339 => x"0c517075",
2340 => x"125252ff",
2341 => x"537087fb",
2342 => x"80802688",
2343 => x"387080e1",
2344 => x"b40c7153",
2345 => x"72b00c84",
2346 => x"3d0d04fd",
2347 => x"3d0d800b",
2348 => x"80d1b808",
2349 => x"54547281",
2350 => x"2e9c3873",
2351 => x"80e1b80c",
2352 => x"c0a43fff",
2353 => x"beba3f80",
2354 => x"e18c5281",
2355 => x"51c2af3f",
2356 => x"b0085185",
2357 => x"c63f7280",
2358 => x"e1b80cc0",
2359 => x"893fffbe",
2360 => x"9f3f80e1",
2361 => x"8c528151",
2362 => x"c2943fb0",
2363 => x"085185ab",
2364 => x"3f00ff39",
2365 => x"f53d0d7e",
2366 => x"6080e1b8",
2367 => x"08705b58",
2368 => x"5b5b7580",
2369 => x"c538777a",
2370 => x"25a23877",
2371 => x"1b703370",
2372 => x"81ff0658",
2373 => x"5859758a",
2374 => x"2e993876",
2375 => x"81ff0651",
2376 => x"ffbfa23f",
2377 => x"81185879",
2378 => x"7824e038",
2379 => x"79b00c8d",
2380 => x"3d0d048d",
2381 => x"51ffbf8d",
2382 => x"3f783370",
2383 => x"81ff0652",
2384 => x"57ffbf81",
2385 => x"3f811858",
2386 => x"de397955",
2387 => x"7a547d53",
2388 => x"85528d3d",
2389 => x"fc0551ff",
2390 => x"bde83fb0",
2391 => x"085684b4",
2392 => x"3f7bb008",
2393 => x"0c75b00c",
2394 => x"8d3d0d04",
2395 => x"f63d0d7d",
2396 => x"7f80e1b8",
2397 => x"08705b58",
2398 => x"5a5a7580",
2399 => x"c4387779",
2400 => x"25b638ff",
2401 => x"be9a3fb0",
2402 => x"0881ff06",
2403 => x"708d3270",
2404 => x"30709f2a",
2405 => x"51515757",
2406 => x"768a2e80",
2407 => x"c6387580",
2408 => x"2e80c038",
2409 => x"771a5676",
2410 => x"76347651",
2411 => x"ffbe963f",
2412 => x"81185878",
2413 => x"7824cc38",
2414 => x"775675b0",
2415 => x"0c8c3d0d",
2416 => x"04785579",
2417 => x"547c5384",
2418 => x"528c3dfc",
2419 => x"0551ffbc",
2420 => x"f13fb008",
2421 => x"5683bd3f",
2422 => x"7ab0080c",
2423 => x"75b00c8c",
2424 => x"3d0d0477",
2425 => x"1a568a76",
2426 => x"34811858",
2427 => x"8d51ffbd",
2428 => x"d43f8a51",
2429 => x"ffbdce3f",
2430 => x"7756ffbe",
2431 => x"39fb3d0d",
2432 => x"80e1b808",
2433 => x"70565473",
2434 => x"883874b0",
2435 => x"0c873d0d",
2436 => x"04775383",
2437 => x"52873dfc",
2438 => x"0551ffbc",
2439 => x"a53fb008",
2440 => x"5482f13f",
2441 => x"75b0080c",
2442 => x"73b00c87",
2443 => x"3d0d04fa",
2444 => x"3d0d80e1",
2445 => x"b808802e",
2446 => x"a3387a55",
2447 => x"79547853",
2448 => x"8652883d",
2449 => x"fc0551ff",
2450 => x"bbf83fb0",
2451 => x"085682c4",
2452 => x"3f76b008",
2453 => x"0c75b00c",
2454 => x"883d0d04",
2455 => x"82b63f9d",
2456 => x"0bb0080c",
2457 => x"ff0bb00c",
2458 => x"883d0d04",
2459 => x"fb3d0d77",
2460 => x"79565680",
2461 => x"70545473",
2462 => x"75259f38",
2463 => x"74101010",
2464 => x"f8055272",
2465 => x"16703370",
2466 => x"742b7607",
2467 => x"8116f816",
2468 => x"56565651",
2469 => x"51747324",
2470 => x"ea3873b0",
2471 => x"0c873d0d",
2472 => x"04fc3d0d",
2473 => x"76785555",
2474 => x"bc538052",
2475 => x"7351f5be",
2476 => x"3f845274",
2477 => x"51ffb53f",
2478 => x"b0087423",
2479 => x"84528415",
2480 => x"51ffa93f",
2481 => x"b0088215",
2482 => x"23845288",
2483 => x"1551ff9c",
2484 => x"3fb00884",
2485 => x"150c8452",
2486 => x"8c1551ff",
2487 => x"8f3fb008",
2488 => x"88152384",
2489 => x"52901551",
2490 => x"ff823fb0",
2491 => x"088a1523",
2492 => x"84529415",
2493 => x"51fef53f",
2494 => x"b0088c15",
2495 => x"23845298",
2496 => x"1551fee8",
2497 => x"3fb0088e",
2498 => x"15238852",
2499 => x"9c1551fe",
2500 => x"db3fb008",
2501 => x"90150c86",
2502 => x"3d0d04e9",
2503 => x"3d0d6a80",
2504 => x"e1b80857",
2505 => x"57759338",
2506 => x"80c0800b",
2507 => x"84180c75",
2508 => x"ac180c75",
2509 => x"b00c993d",
2510 => x"0d04893d",
2511 => x"70556a54",
2512 => x"558a5299",
2513 => x"3dffbc05",
2514 => x"51ffb9f6",
2515 => x"3fb00877",
2516 => x"53755256",
2517 => x"fecb3fbc",
2518 => x"3f77b008",
2519 => x"0c75b00c",
2520 => x"993d0d04",
2521 => x"fc3d0d81",
2522 => x"5480e1b8",
2523 => x"08883873",
2524 => x"b00c863d",
2525 => x"0d047653",
2526 => x"97b95286",
2527 => x"3dfc0551",
2528 => x"ffb9bf3f",
2529 => x"b008548c",
2530 => x"3f74b008",
2531 => x"0c73b00c",
2532 => x"863d0d04",
2533 => x"80d1c808",
2534 => x"b00c04f7",
2535 => x"3d0d7b80",
2536 => x"d1c80882",
2537 => x"c811085a",
2538 => x"545a7780",
2539 => x"2e80da38",
2540 => x"81881884",
2541 => x"1908ff05",
2542 => x"81712b59",
2543 => x"55598074",
2544 => x"2480ea38",
2545 => x"807424b5",
2546 => x"3873822b",
2547 => x"78118805",
2548 => x"56568180",
2549 => x"19087706",
2550 => x"5372802e",
2551 => x"b6387816",
2552 => x"70085353",
2553 => x"79517408",
2554 => x"53722dff",
2555 => x"14fc17fc",
2556 => x"1779812c",
2557 => x"5a575754",
2558 => x"738025d6",
2559 => x"38770858",
2560 => x"77ffad38",
2561 => x"80d1c808",
2562 => x"53bc1308",
2563 => x"a5387951",
2564 => x"f9df3f74",
2565 => x"0853722d",
2566 => x"ff14fc17",
2567 => x"fc177981",
2568 => x"2c5a5757",
2569 => x"54738025",
2570 => x"ffa838d1",
2571 => x"398057ff",
2572 => x"93397251",
2573 => x"bc130853",
2574 => x"722d7951",
2575 => x"f9b33fff",
2576 => x"3d0d80e1",
2577 => x"940bfc05",
2578 => x"70085252",
2579 => x"70ff2e91",
2580 => x"38702dfc",
2581 => x"12700852",
2582 => x"5270ff2e",
2583 => x"098106f1",
2584 => x"38833d0d",
2585 => x"0404ffb9",
2586 => x"e83f0400",
2587 => x"00ffffff",
2588 => x"ff00ffff",
2589 => x"ffff00ff",
2590 => x"ffffff00",
2591 => x"00000040",
2592 => x"30313233",
2593 => x"34353637",
2594 => x"38396162",
2595 => x"63646566",
2596 => x"00000000",
2597 => x"633a0000",
2598 => x"733a0000",
2599 => x"623a0000",
2600 => x"0a000000",
2601 => x"43000000",
2602 => x"64756d6d",
2603 => x"792e6578",
2604 => x"65000000",
2605 => x"00000000",
2606 => x"00000000",
2607 => x"00000000",
2608 => x"0000309c",
2609 => x"00002880",
2610 => x"000028cc",
2611 => x"00000000",
2612 => x"00002b34",
2613 => x"00002b90",
2614 => x"00002bec",
2615 => x"00000000",
2616 => x"00000000",
2617 => x"00000000",
2618 => x"00000000",
2619 => x"00000000",
2620 => x"00000000",
2621 => x"00000000",
2622 => x"00000000",
2623 => x"00000000",
2624 => x"000028a4",
2625 => x"00000000",
2626 => x"00000000",
2627 => x"00000000",
2628 => x"00000000",
2629 => x"00000000",
2630 => x"00000000",
2631 => x"00000000",
2632 => x"00000000",
2633 => x"00000000",
2634 => x"00000000",
2635 => x"00000000",
2636 => x"00000000",
2637 => x"00000000",
2638 => x"00000000",
2639 => x"00000000",
2640 => x"00000000",
2641 => x"00000000",
2642 => x"00000000",
2643 => x"00000000",
2644 => x"00000000",
2645 => x"00000000",
2646 => x"00000000",
2647 => x"00000000",
2648 => x"00000000",
2649 => x"00000000",
2650 => x"00000000",
2651 => x"00000000",
2652 => x"00000000",
2653 => x"00000001",
2654 => x"330eabcd",
2655 => x"1234e66d",
2656 => x"deec0005",
2657 => x"000b0000",
2658 => x"00000000",
2659 => x"00000000",
2660 => x"00000000",
2661 => x"00000000",
2662 => x"00000000",
2663 => x"00000000",
2664 => x"00000000",
2665 => x"00000000",
2666 => x"00000000",
2667 => x"00000000",
2668 => x"00000000",
2669 => x"00000000",
2670 => x"00000000",
2671 => x"00000000",
2672 => x"00000000",
2673 => x"00000000",
2674 => x"00000000",
2675 => x"00000000",
2676 => x"00000000",
2677 => x"00000000",
2678 => x"00000000",
2679 => x"00000000",
2680 => x"00000000",
2681 => x"00000000",
2682 => x"00000000",
2683 => x"00000000",
2684 => x"00000000",
2685 => x"00000000",
2686 => x"00000000",
2687 => x"00000000",
2688 => x"00000000",
2689 => x"00000000",
2690 => x"00000000",
2691 => x"00000000",
2692 => x"00000000",
2693 => x"00000000",
2694 => x"00000000",
2695 => x"00000000",
2696 => x"00000000",
2697 => x"00000000",
2698 => x"00000000",
2699 => x"00000000",
2700 => x"00000000",
2701 => x"00000000",
2702 => x"00000000",
2703 => x"00000000",
2704 => x"00000000",
2705 => x"00000000",
2706 => x"00000000",
2707 => x"00000000",
2708 => x"00000000",
2709 => x"00000000",
2710 => x"00000000",
2711 => x"00000000",
2712 => x"00000000",
2713 => x"00000000",
2714 => x"00000000",
2715 => x"00000000",
2716 => x"00000000",
2717 => x"00000000",
2718 => x"00000000",
2719 => x"00000000",
2720 => x"00000000",
2721 => x"00000000",
2722 => x"00000000",
2723 => x"00000000",
2724 => x"00000000",
2725 => x"00000000",
2726 => x"00000000",
2727 => x"00000000",
2728 => x"00000000",
2729 => x"00000000",
2730 => x"00000000",
2731 => x"00000000",
2732 => x"00000000",
2733 => x"00000000",
2734 => x"00000000",
2735 => x"00000000",
2736 => x"00000000",
2737 => x"00000000",
2738 => x"00000000",
2739 => x"00000000",
2740 => x"00000000",
2741 => x"00000000",
2742 => x"00000000",
2743 => x"00000000",
2744 => x"00000000",
2745 => x"00000000",
2746 => x"00000000",
2747 => x"00000000",
2748 => x"00000000",
2749 => x"00000000",
2750 => x"00000000",
2751 => x"00000000",
2752 => x"00000000",
2753 => x"00000000",
2754 => x"00000000",
2755 => x"00000000",
2756 => x"00000000",
2757 => x"00000000",
2758 => x"00000000",
2759 => x"00000000",
2760 => x"00000000",
2761 => x"00000000",
2762 => x"00000000",
2763 => x"00000000",
2764 => x"00000000",
2765 => x"00000000",
2766 => x"00000000",
2767 => x"00000000",
2768 => x"00000000",
2769 => x"00000000",
2770 => x"00000000",
2771 => x"00000000",
2772 => x"00000000",
2773 => x"00000000",
2774 => x"00000000",
2775 => x"00000000",
2776 => x"00000000",
2777 => x"00000000",
2778 => x"00000000",
2779 => x"00000000",
2780 => x"00000000",
2781 => x"00000000",
2782 => x"00000000",
2783 => x"00000000",
2784 => x"00000000",
2785 => x"00000000",
2786 => x"00000000",
2787 => x"00000000",
2788 => x"00000000",
2789 => x"00000000",
2790 => x"00000000",
2791 => x"00000000",
2792 => x"00000000",
2793 => x"00000000",
2794 => x"00000000",
2795 => x"00000000",
2796 => x"00000000",
2797 => x"00000000",
2798 => x"00000000",
2799 => x"00000000",
2800 => x"00000000",
2801 => x"00000000",
2802 => x"00000000",
2803 => x"00000000",
2804 => x"00000000",
2805 => x"00000000",
2806 => x"00000000",
2807 => x"00000000",
2808 => x"00000000",
2809 => x"00000000",
2810 => x"00000000",
2811 => x"00000000",
2812 => x"00000000",
2813 => x"00000000",
2814 => x"00000000",
2815 => x"00000000",
2816 => x"00000000",
2817 => x"00000000",
2818 => x"00000000",
2819 => x"00000000",
2820 => x"00000000",
2821 => x"00000000",
2822 => x"00000000",
2823 => x"00000000",
2824 => x"00000000",
2825 => x"00000000",
2826 => x"00000000",
2827 => x"00000000",
2828 => x"00000000",
2829 => x"00000000",
2830 => x"00000000",
2831 => x"00000000",
2832 => x"00000000",
2833 => x"00000000",
2834 => x"00000000",
2835 => x"00000000",
2836 => x"00000000",
2837 => x"00000000",
2838 => x"00000000",
2839 => x"00000000",
2840 => x"00000000",
2841 => x"00000000",
2842 => x"00000000",
2843 => x"00000000",
2844 => x"00000000",
2845 => x"00000000",
2846 => x"ffffffff",
2847 => x"00000000",
2848 => x"00020000",
2849 => x"00000000",
2850 => x"00000000",
2851 => x"00002c84",
2852 => x"00002c84",
2853 => x"00002c8c",
2854 => x"00002c8c",
2855 => x"00002c94",
2856 => x"00002c94",
2857 => x"00002c9c",
2858 => x"00002c9c",
2859 => x"00002ca4",
2860 => x"00002ca4",
2861 => x"00002cac",
2862 => x"00002cac",
2863 => x"00002cb4",
2864 => x"00002cb4",
2865 => x"00002cbc",
2866 => x"00002cbc",
2867 => x"00002cc4",
2868 => x"00002cc4",
2869 => x"00002ccc",
2870 => x"00002ccc",
2871 => x"00002cd4",
2872 => x"00002cd4",
2873 => x"00002cdc",
2874 => x"00002cdc",
2875 => x"00002ce4",
2876 => x"00002ce4",
2877 => x"00002cec",
2878 => x"00002cec",
2879 => x"00002cf4",
2880 => x"00002cf4",
2881 => x"00002cfc",
2882 => x"00002cfc",
2883 => x"00002d04",
2884 => x"00002d04",
2885 => x"00002d0c",
2886 => x"00002d0c",
2887 => x"00002d14",
2888 => x"00002d14",
2889 => x"00002d1c",
2890 => x"00002d1c",
2891 => x"00002d24",
2892 => x"00002d24",
2893 => x"00002d2c",
2894 => x"00002d2c",
2895 => x"00002d34",
2896 => x"00002d34",
2897 => x"00002d3c",
2898 => x"00002d3c",
2899 => x"00002d44",
2900 => x"00002d44",
2901 => x"00002d4c",
2902 => x"00002d4c",
2903 => x"00002d54",
2904 => x"00002d54",
2905 => x"00002d5c",
2906 => x"00002d5c",
2907 => x"00002d64",
2908 => x"00002d64",
2909 => x"00002d6c",
2910 => x"00002d6c",
2911 => x"00002d74",
2912 => x"00002d74",
2913 => x"00002d7c",
2914 => x"00002d7c",
2915 => x"00002d84",
2916 => x"00002d84",
2917 => x"00002d8c",
2918 => x"00002d8c",
2919 => x"00002d94",
2920 => x"00002d94",
2921 => x"00002d9c",
2922 => x"00002d9c",
2923 => x"00002da4",
2924 => x"00002da4",
2925 => x"00002dac",
2926 => x"00002dac",
2927 => x"00002db4",
2928 => x"00002db4",
2929 => x"00002dbc",
2930 => x"00002dbc",
2931 => x"00002dc4",
2932 => x"00002dc4",
2933 => x"00002dcc",
2934 => x"00002dcc",
2935 => x"00002dd4",
2936 => x"00002dd4",
2937 => x"00002ddc",
2938 => x"00002ddc",
2939 => x"00002de4",
2940 => x"00002de4",
2941 => x"00002dec",
2942 => x"00002dec",
2943 => x"00002df4",
2944 => x"00002df4",
2945 => x"00002dfc",
2946 => x"00002dfc",
2947 => x"00002e04",
2948 => x"00002e04",
2949 => x"00002e0c",
2950 => x"00002e0c",
2951 => x"00002e14",
2952 => x"00002e14",
2953 => x"00002e1c",
2954 => x"00002e1c",
2955 => x"00002e24",
2956 => x"00002e24",
2957 => x"00002e2c",
2958 => x"00002e2c",
2959 => x"00002e34",
2960 => x"00002e34",
2961 => x"00002e3c",
2962 => x"00002e3c",
2963 => x"00002e44",
2964 => x"00002e44",
2965 => x"00002e4c",
2966 => x"00002e4c",
2967 => x"00002e54",
2968 => x"00002e54",
2969 => x"00002e5c",
2970 => x"00002e5c",
2971 => x"00002e64",
2972 => x"00002e64",
2973 => x"00002e6c",
2974 => x"00002e6c",
2975 => x"00002e74",
2976 => x"00002e74",
2977 => x"00002e7c",
2978 => x"00002e7c",
2979 => x"00002e84",
2980 => x"00002e84",
2981 => x"00002e8c",
2982 => x"00002e8c",
2983 => x"00002e94",
2984 => x"00002e94",
2985 => x"00002e9c",
2986 => x"00002e9c",
2987 => x"00002ea4",
2988 => x"00002ea4",
2989 => x"00002eac",
2990 => x"00002eac",
2991 => x"00002eb4",
2992 => x"00002eb4",
2993 => x"00002ebc",
2994 => x"00002ebc",
2995 => x"00002ec4",
2996 => x"00002ec4",
2997 => x"00002ecc",
2998 => x"00002ecc",
2999 => x"00002ed4",
3000 => x"00002ed4",
3001 => x"00002edc",
3002 => x"00002edc",
3003 => x"00002ee4",
3004 => x"00002ee4",
3005 => x"00002eec",
3006 => x"00002eec",
3007 => x"00002ef4",
3008 => x"00002ef4",
3009 => x"00002efc",
3010 => x"00002efc",
3011 => x"00002f04",
3012 => x"00002f04",
3013 => x"00002f0c",
3014 => x"00002f0c",
3015 => x"00002f14",
3016 => x"00002f14",
3017 => x"00002f1c",
3018 => x"00002f1c",
3019 => x"00002f24",
3020 => x"00002f24",
3021 => x"00002f2c",
3022 => x"00002f2c",
3023 => x"00002f34",
3024 => x"00002f34",
3025 => x"00002f3c",
3026 => x"00002f3c",
3027 => x"00002f44",
3028 => x"00002f44",
3029 => x"00002f4c",
3030 => x"00002f4c",
3031 => x"00002f54",
3032 => x"00002f54",
3033 => x"00002f5c",
3034 => x"00002f5c",
3035 => x"00002f64",
3036 => x"00002f64",
3037 => x"00002f6c",
3038 => x"00002f6c",
3039 => x"00002f74",
3040 => x"00002f74",
3041 => x"00002f7c",
3042 => x"00002f7c",
3043 => x"00002f84",
3044 => x"00002f84",
3045 => x"00002f8c",
3046 => x"00002f8c",
3047 => x"00002f94",
3048 => x"00002f94",
3049 => x"00002f9c",
3050 => x"00002f9c",
3051 => x"00002fa4",
3052 => x"00002fa4",
3053 => x"00002fac",
3054 => x"00002fac",
3055 => x"00002fb4",
3056 => x"00002fb4",
3057 => x"00002fbc",
3058 => x"00002fbc",
3059 => x"00002fc4",
3060 => x"00002fc4",
3061 => x"00002fcc",
3062 => x"00002fcc",
3063 => x"00002fd4",
3064 => x"00002fd4",
3065 => x"00002fdc",
3066 => x"00002fdc",
3067 => x"00002fe4",
3068 => x"00002fe4",
3069 => x"00002fec",
3070 => x"00002fec",
3071 => x"00002ff4",
3072 => x"00002ff4",
3073 => x"00002ffc",
3074 => x"00002ffc",
3075 => x"00003004",
3076 => x"00003004",
3077 => x"0000300c",
3078 => x"0000300c",
3079 => x"00003014",
3080 => x"00003014",
3081 => x"0000301c",
3082 => x"0000301c",
3083 => x"00003024",
3084 => x"00003024",
3085 => x"0000302c",
3086 => x"0000302c",
3087 => x"00003034",
3088 => x"00003034",
3089 => x"0000303c",
3090 => x"0000303c",
3091 => x"00003044",
3092 => x"00003044",
3093 => x"0000304c",
3094 => x"0000304c",
3095 => x"00003054",
3096 => x"00003054",
3097 => x"0000305c",
3098 => x"0000305c",
3099 => x"00003064",
3100 => x"00003064",
3101 => x"0000306c",
3102 => x"0000306c",
3103 => x"00003074",
3104 => x"00003074",
3105 => x"0000307c",
3106 => x"0000307c",
3107 => x"000028a8",
3108 => x"ffffffff",
3109 => x"00000000",
3110 => x"ffffffff",
3111 => x"00000000",
others => x"00000000"
);
begin
busy_o <= re_i; -- we're done on the cycle after we serve the read request
do_ram:
process (clk_i)
variable iaddr : integer;
begin
if rising_edge(clk_i) then
if we_i='1' then
ram(to_integer(addr_i)) <= write_i;
end if;
addr_r <= addr_i;
end if;
end process do_ram;
read_o <= ram(to_integer(addr_r));
end architecture Xilinx; -- Entity: SinglePortRAM
| bsd-3-clause | 120e4b1327d73064a92ab73aec0442a8 | 0.592971 | 2.27504 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_01300_good.vhd | 1 | 2,723 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-02 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_01300_good.vhd
-- File Creation date : 2015-04-02
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Number of ports declaration per line: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.pkg_HBK.all;
--CODE
entity STD_01300_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end STD_01300_good;
architecture Behavioral of STD_01300_good is
begin
DFlipFlop1 : DFlipFlop
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_D => i_D,
o_Q => o_Q,
o_Q_n => open
);
end Behavioral;
--CODE
| gpl-3.0 | 5db651902eaa6f3791e9142585562d02 | 0.465663 | 4.607445 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/zpu/zpu_glue.vhdl | 1 | 14,150 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_MISC.all;
library work;
use work.zpupkg.all;
ENTITY zpu_glue IS
PORT
(
CLK : in std_logic;
RESET : in std_logic;
PAUSE : in std_logic;
ZPU_DI : in std_logic_vector(31 downto 0); -- response from general memory - for areas that only support 8/16 bit set top bits to 0
ZPU_ROM_DI : in std_logic_vector(31 downto 0); -- response from own program memory
ZPU_RAM_DI : in std_logic_vector(31 downto 0); -- response from own stack
ZPU_CONFIG_DI : in std_logic_vector(31 downto 0); -- response from config registers
ZPU_DO : out std_logic_vector(31 downto 0);
ZPU_ADDR_ROM_RAM : out std_logic_vector(15 downto 0); -- direct from zpu, for short paths
ZPU_ADDR_FETCH : out std_logic_vector(23 downto 0); -- clk->q, for longer paths
-- request
MEMORY_FETCH : out std_logic;
ZPU_READ_ENABLE : out std_logic;
ZPU_32BIT_WRITE_ENABLE : out std_logic; -- common case
ZPU_16BIT_WRITE_ENABLE : out std_logic; -- for sram (never happens yet!)
ZPU_8BIT_WRITE_ENABLE : out std_logic; -- for hardware regs
-- config
ZPU_CONFIG_WRITE : out std_logic;
-- stack request
ZPU_STACK_WRITE : out std_logic_vector(3 downto 0);
-- write to ROM!!
ZPU_ROM_WREN : out std_logic;
-- response
MEMORY_READY : in std_logic
);
END zpu_glue;
architecture sticky of zpu_glue is
component ZPUMediumCore is
generic(
WORD_SIZE : integer:=32; -- 16/32 (2**wordPower)
ADDR_W : integer:=24; -- Total address space width (incl. I/O)
MEM_W : integer:=16; -- Memory (prog+data+stack) width - stack at end of memory - so end of sdram. 32K ROM, 32K RAM (MAX)
D_CARE_VAL : std_logic:='X'; -- Value used to fill the unsused bits
MULT_PIPE : boolean:=false; -- Pipeline multiplication
BINOP_PIPE : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)
ENA_LEVEL0 : boolean:=true; -- eq, loadb, neqbranch and pushspadd
ENA_LEVEL1 : boolean:=true; -- lessthan, ulessthan, mult, storeb, callpcrel and sub
ENA_LEVEL2 : boolean:=true; -- lessthanorequal, ulessthanorequal, call and poppcrel
ENA_LSHR : boolean:=true; -- lshiftright
ENA_IDLE : boolean:=false; -- Enable the enable_i input
FAST_FETCH : boolean:=true); -- Merge the st_fetch with the st_execute states
port(
clk_i : in std_logic; -- CPU Clock
reset_i : in std_logic; -- Sync Reset
enable_i : in std_logic; -- Hold the CPU (after reset)
break_o : out std_logic; -- Break instruction executed
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- Memory interface
mem_busy_i : in std_logic; -- Memory is busy
data_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from mem
data_o : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem
addr_o : out unsigned(ADDR_W-1 downto 0); -- Memory address
write_en_o : out std_logic; -- Memory write enable (32-bit)
read_en_o : out std_logic; -- Memory read enable (32-bit)
byte_read_o : out std_logic;
byte_write_o : out std_logic;
short_write_o: out std_logic); -- never happens
end component;
signal zpu_addr_unsigned : unsigned(23 downto 0);
signal zpu_do_unsigned : unsigned(31 downto 0);
signal ZPU_DI_unsigned : unsigned(31 downto 0);
signal zpu_break : std_logic;
signal zpu_debug : zpu_dbgo_t;
signal zpu_mem_busy : std_logic;
signal zpu_memory_fetch_pending_next : std_logic;
signal zpu_memory_fetch_pending_reg : std_logic;
signal ZPU_32bit_READ_ENABLE_temp : std_logic;
signal ZPU_8bit_READ_ENABLE_temp : std_logic;
signal ZPU_READ_temp : std_logic;
signal ZPU_32BIT_WRITE_ENABLE_temp : std_logic;
signal ZPU_16BIT_WRITE_ENABLE_temp : std_logic;
signal ZPU_8BIT_WRITE_ENABLE_temp : std_logic;
signal ZPU_WRITE_temp : std_logic;
signal ZPU_32BIT_WRITE_ENABLE_next : std_logic;
signal ZPU_16BIT_WRITE_ENABLE_next : std_logic;
signal ZPU_8BIT_WRITE_ENABLE_next : std_logic;
signal ZPU_READ_next : std_logic;
signal ZPU_32BIT_WRITE_ENABLE_reg : std_logic;
signal ZPU_16BIT_WRITE_ENABLE_reg : std_logic;
signal ZPU_8BIT_WRITE_ENABLE_reg : std_logic;
signal ZPU_READ_reg : std_logic;
signal block_mem : std_logic;
signal config_mem : std_logic;
signal special_mem : std_logic;
signal result_next : std_logic_vector(4 downto 0);
signal result_reg : std_logic_vector(4 downto 0);
constant result_external : std_logic_vector(4 downto 0) := "00000";
constant result_ram : std_logic_vector(4 downto 0) := "00001";
constant result_ram_8bit_0 : std_logic_vector(4 downto 0) := "00010";
constant result_ram_8bit_1 : std_logic_vector(4 downto 0) := "00011";
constant result_ram_8bit_2 : std_logic_vector(4 downto 0) := "00100";
constant result_ram_8bit_3 : std_logic_vector(4 downto 0) := "00101";
constant result_rom : std_logic_vector(4 downto 0) := "00110";
constant result_rom_8bit_0 : std_logic_vector(4 downto 0) := "00111";
constant result_rom_8bit_1 : std_logic_vector(4 downto 0) := "01000";
constant result_rom_8bit_2 : std_logic_vector(4 downto 0) := "01001";
constant result_rom_8bit_3 : std_logic_vector(4 downto 0) := "01010";
constant result_config : std_logic_vector(4 downto 0) := "01011";
constant result_external_special : std_logic_vector(4 downto 0) := "01100";
signal request_type : std_logic_vector(4 downto 0);
signal zpu_di_use : std_logic_vector(31 downto 0);
signal memORY_ACCESS : std_logic;
-- 1 cycle delay on memory read - needed to allow running at higher clock
signal zpu_di_next : std_logic_vector(31 downto 0);
signal zpu_di_reg : std_logic_vector(31 downto 0);
signal memory_ready_next : std_logic;
signal memory_ready_reg : std_logic;
signal zpu_enable : std_logic;
signal zpu_addr_next : std_logic_vector(23 downto 0);
signal zpu_addr_reg : std_logic_vector(23 downto 0);
signal ZPU_DO_next : std_logic_vector(31 downto 0);
signal ZPU_DO_reg : std_logic_vector(31 downto 0);
begin
-- register
process(clk,reset)
begin
if (reset='1') then
zpu_memory_fetch_pending_reg <= '0';
result_reg <= result_rom;
zpu_di_reg <= (others=>'0');
zpu_do_reg <= (others=>'0');
memory_ready_reg <= '0';
zpu_addr_reg <= (others=>'0');
ZPU_32BIT_WRITE_ENABLE_reg <= '0';
ZPU_16BIT_WRITE_ENABLE_reg <= '0';
ZPU_8BIT_WRITE_ENABLE_reg <= '0';
ZPU_READ_reg <= '0';
elsif (clk'event and clk='1') then
zpu_memory_fetch_pending_reg <= zpu_memory_fetch_pending_next;
result_reg <= result_next;
zpu_di_reg <= zpu_di_next;
zpu_do_reg <= zpu_do_next;
memory_ready_reg <= memORY_READY_next;
zpu_addr_reg <=zpu_addr_next;
ZPU_32BIT_WRITE_ENABLE_reg <= ZPU_32BIT_WRITE_ENABLE_next;
ZPU_16BIT_WRITE_ENABLE_reg <= ZPU_16BIT_WRITE_ENABLE_next;
ZPU_8BIT_WRITE_ENABLE_reg <= ZPU_8BIT_WRITE_ENABLE_next;
ZPU_READ_reg <= ZPU_READ_next;
end if;
end process;
-- a little glue
process(zpu_ADDR_unsigned)
begin
block_mem <= '0';
config_mem <= '0';
special_mem <= '0';
-- $00000-$0FFFF = Own ROM/RAM
-- $10000-$1FFFF = Atari
-- $20000-$2FFFF = Atari - savestate (gtia/antic/pokey have memory behind them)
-- $40000-$4FFFF = Config area
if (or_reduce(std_logic_vector(zpu_ADDR_unsigned(23 downto 21))) = '0') then -- special area
block_mem <= not(zpu_addr_unsigned(18) or zpu_addr_unsigned(17) or zpu_addr_unsigned(16));
config_mem <= zpu_addr_unsigned(18);
special_mem <= zpu_addr_unsigned(17);
end if;
end process;
ZPU_READ_TEMP <= zpu_32bit_read_enable_temp or zpu_8BIT_read_enable_temp;
ZPU_WRITE_TEMP<= zpu_32BIT_WRITE_ENABLE_temp or zpu_16BIT_WRITE_ENABLE_temp or zpu_8BIT_WRITE_ENABLE_temp;
process(zpu_addr_reg,pause,memory_ready,zpu_memory_fetch_pending_next,request_type, zpu_memory_fetch_pending_reg, memory_ready_reg, zpu_ADDR_unsigned, zpu_8bit_read_enable_temp, zpu_write_temp, result_reg, block_mem, config_mem, special_mem, memORY_ACCESS,
zpu_read_reg,zpu_8BIT_WRITE_ENABLE_reg, zpu_16BIT_WRITE_ENABLE_reg, zpu_32BIT_WRITE_ENABLE_reg,
zpu_read_temp,zpu_8BIT_WRITE_ENABLE_temp, zpu_16BIT_WRITE_ENABLE_temp, zpu_32BIT_WRITE_ENABLE_temp,
zpu_do_unsigned, zpu_do_reg
)
begin
zpu_memory_fetch_pending_next <= zpu_memory_fetch_pending_reg;
result_next <= result_reg;
memory_ready_next <= memory_ready;
zpu_stACK_WRITE <= (others=>'0');
ZPU_ROM_WREN <= '0';
ZPU_config_write <= '0';
zpu_addr_next <= zpu_addr_reg;
zpu_do_next <= zpu_do_reg;
ZPU_MEM_BUSY <= pause;
MEMORY_ACCESS <= zpu_READ_temp or ZPU_WRITE_temp;
if (memory_access = '1') then
zpu_do_next <= std_logic_vector(zpu_do_unsigned);
end if;
memory_fetch <= zpu_memory_fetch_pending_reg;
zpu_read_next <= zpu_read_reg;
zpu_8bit_write_enable_next <= zpu_8bit_write_enable_reg;
zpu_16bit_write_enable_next <= zpu_16bit_write_enable_reg;
zpu_32bit_write_enable_next <= zpu_32bit_write_enable_reg;
request_type <= config_mem&block_mem&zpu_addr_unsigned(15)&memORY_ACCESS&zpu_memory_fetch_pending_reg;
case request_type is
when "00010"|"00110" =>
zpu_memory_fetch_pending_next <= '1';
if (special_mem='0') then
result_next <= result_external;
else
result_next <= result_external_special;
end if;
ZPU_MEM_BUSY <= '1';
zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
zpu_read_next <= zpu_read_temp;
zpu_8bit_write_enable_next <= zpu_8bit_write_enable_temp;
zpu_16bit_write_enable_next <= zpu_16bit_write_enable_temp;
zpu_32bit_write_enable_next <= zpu_32bit_write_enable_temp;
when "01010" =>
if (zpu_8bit_read_enable_temp='1') then
case (zpu_addr_unsigned(1 downto 0)) is
when "00" =>
result_next <= result_rom_8bit_3;
when "01" =>
result_next <= result_rom_8bit_2;
when "10" =>
result_next <= result_rom_8bit_1;
when "11" =>
result_next <= result_rom_8bit_0;
when others =>
--nop
end case;
else
result_next <= result_rom;
end if;
ZPU_ROM_WREN <= ZPU_WRITE_TEMP;
ZPU_MEM_BUSY <= '1';
zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
when "01110" =>
if (zpu_8bit_read_enable_temp='1' or zpu_8BIT_WRITE_ENABLE_temp='1') then
case (zpu_addr_unsigned(1 downto 0)) is
when "00" =>
result_next <= result_ram_8bit_3;
ZPU_STACK_WRITE(3) <= zpu_8BIT_write_enable_temp;
when "01" =>
result_next <= result_ram_8bit_2;
ZPU_STACK_WRITE(2) <= zpu_8BIT_write_enable_temp;
when "10" =>
result_next <= result_ram_8bit_1;
ZPU_STACK_WRITE(1) <= zpu_8BIT_write_enable_temp;
when "11" =>
result_next <= result_ram_8bit_0;
ZPU_STACK_WRITE(0) <= zpu_8BIT_write_enable_temp;
when others =>
--nop
end case;
else
result_next <= result_ram;
ZPU_STACK_WRITE <= (others=>zpu_write_temp);
end if;
ZPU_MEM_BUSY <= '1';
zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
when "10110"|"10010" =>
result_next <= result_config;
ZPU_MEM_BUSY <= '1';
ZPU_config_write <= ZPU_WRITE_temp;
zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
when "00001"|"00011"|"00101"|"00111"|"01001"|"01011"|"01101"|"01111"|
"10001"|"10011"|"10101"|"10111"|"11001"|"11011"|"11101"|"11111"|"00X01" =>
ZPU_MEM_BUSY <= not(memORY_READY_reg) or pause;
zpu_memory_fetch_pending_next <= not(memORY_READY);
when others =>
-- nop
end case;
end process;
zpu_di_next <= zpu_di;
process(result_reg, zpu_di_reg, zpu_rom_di, zpu_ram_di, zpu_config_di)
begin
zpu_di_use <= (others=>'0');
case result_reg is
when result_external =>
zpu_di_use <= zpu_di_reg;
when result_external_special =>
zpu_di_use(7 downto 0) <= zpu_di_reg(15 downto 8);
when result_rom =>
zpu_di_use <= zpu_rom_DI;
when result_rom_8bit_0 =>
zpu_di_use(7 downto 0) <= zpu_rom_DI(7 downto 0);
when result_rom_8bit_1 =>
zpu_di_use(7 downto 0) <= zpu_rom_DI(15 downto 8);
when result_rom_8bit_2 =>
zpu_di_use(7 downto 0) <= zpu_rom_DI(23 downto 16);
when result_rom_8bit_3 =>
zpu_di_use(7 downto 0) <= zpu_rom_DI(31 downto 24);
when result_ram =>
zpu_di_use <= zpu_ram_DI;
when result_ram_8bit_0 =>
zpu_di_use(7 downto 0) <= zpu_ram_DI(7 downto 0);
when result_ram_8bit_1 =>
zpu_di_use(7 downto 0) <= zpu_ram_DI(15 downto 8);
when result_ram_8bit_2 =>
zpu_di_use(7 downto 0) <= zpu_ram_DI(23 downto 16);
when result_ram_8bit_3 =>
zpu_di_use(7 downto 0) <= zpu_ram_DI(31 downto 24);
when result_config =>
zpu_di_use <= zpu_config_di;
when others =>
-- nothing
end case;
end process;
-- zpu itself
--zpu_enable <= enable and not(pause);
zpu_enable <= '1'; -- does nothing useful...
myzpu: ZPUMediumCore
port map (clk_i=>clk, reset_i=>reset,enable_i=>zpu_enable,break_o=>zpu_break,dbg_o=>zpu_debug,mem_busy_i=>ZPU_MEM_BUSY,
data_i=>zpu_di_unsigned,data_o=>zpu_do_unsigned,addr_o=>zpu_addr_unsigned,write_en_o=>zpu_32bit_write_enable_temp,read_en_o=>zpu_32bit_read_enable_temp,
byte_read_o=>zpu_8bit_read_enable_temp, byte_write_o=>zpu_8bit_write_enable_temp,short_write_o=>zpu_16bit_write_enable_temp);
zpu_di_unsigned <= unsigned(zpu_di_use);
zpu_do <= zpu_do_next;
ZPU_ADDR_ROM_RAM <= zpu_addr_next(15 downto 0);
ZPU_ADDR_FETCH <= zpu_addr_reg;
zpu_read_enable <= zpu_read_reg;
zpu_8bit_write_enable <= zpu_8bit_write_enable_reg;
zpu_16bit_write_enable <= zpu_16bit_write_enable_reg;
zpu_32bit_write_enable <= zpu_32bit_write_enable_reg;
end sticky;
| gpl-3.0 | b8592705a12fdfabd458868ec7db0f20 | 0.647067 | 2.800871 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_03800_bad.vhd | 1 | 3,006 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1.1
-- Version history :
-- V1 : 2015-04-07 : Mickael Carl (CNES): Creation
-- V1.1 : 2016-05-03 : F.MAnni (CNES) : remove i_Reset_n from process sensitivity list
-------------------------------------------------------------------------------------------------
-- File name : STD_03800_bad.vhd
-- File Creation date : 2015-04-07
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Synchronous elements initialization: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_03800_bad is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic; -- D Flip-Flop output signal
o_Q_n : out std_logic -- D Flip-Flop output signal, inverted
);
end STD_03800_bad;
--CODE
architecture Behavioral of STD_03800_bad is
signal Q : std_logic := '0'; -- D Flip-Flop output
signal Q_n : std_logic := '1'; -- Same as Q, inverted
begin
-- D FlipFlop process
P_FlipFlop : process(i_Clock)
begin
if (rising_edge(i_Clock)) then
Q <= i_D;
Q_n <= not i_D;
end if;
end process;
o_Q <= Q;
o_Q_n <= Q_n;
end Behavioral;
--CODE
| gpl-3.0 | 52b1aaa24eb55e4ab9d56222053f8de2 | 0.481371 | 4.369186 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/service/src/keyboard.vhd | 1 | 5,357 | -- ###################################################################################
--
-- #### #### #####
-- ## ## ##### ## ## ##### ## ###### ##### ##### ##### ## ##
-- ## ## ## ## ## ## ## ## ##### ## ## ## ## ## ## ## ##
-- ## ## ## ## ## ## ###### ## ###### ###### ## ## ######
-- ## ## ## ## ### ## ## ## ## ## ## ##
-- #### ######## ##### # ##### ##### ## ##### ##### ##### #####
--
-- ###################################################################################
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity keyboard is
generic (FilterSize : positive := 10);
port(
clk : in std_logic;
reset : in std_logic;
PS2_Clk : in std_logic;
PS2_Data : in std_logic;
Key_Data : out std_logic_vector(7 downto 0) );
end keyboard;
architecture Behavioral of keyboard is
signal PS2_Datr : std_logic;
signal DoRead : std_logic; -- From outside when reading the scan code
signal Scan_Err : std_logic; -- To outside : Parity or Overflow error
signal Scan_Code : std_logic_vector(7 downto 0); -- Eight bits Data Out
signal Filter : std_logic_vector(FilterSize-1 downto 0);
signal Filter_t0 : std_logic_vector(FilterSize-1 downto 0);
signal Filter_t1 : std_logic_vector(FilterSize-1 downto 0);
signal Fall_Clk : std_logic;
signal Bit_Cnt : unsigned (3 downto 0);
signal Parity : std_logic;
signal S_Reg : std_logic_vector(8 downto 0);
signal PS2_Clk_f : std_logic; signal Code_Readed : std_logic;
signal Key_Released : std_logic;
signal Extend_Key : std_logic;
signal Matrix : std_logic_vector(7 downto 0);
Type State_t is (Idle, Shifting);
signal State : State_t;
begin
Filter_t0 <= (others=>'0');
Filter_t1 <= (others=>'1');
process (Clk,Reset)
begin
if Reset='1' then
PS2_Datr <= '0';
PS2_Clk_f <= '0';
Filter <= (others=>'0');
Fall_Clk <= '0';
elsif rising_edge (Clk) then
PS2_Datr <= PS2_Data and PS2_Data; -- also turns 'H' into '1'
Fall_Clk <= '0';
Filter <= (PS2_Clk and PS2_CLK) & Filter(Filter'high downto 1);
if Filter = Filter_t1 then
PS2_Clk_f <= '1';
elsif Filter = Filter_t0 then
PS2_Clk_f <= '0';
if PS2_Clk_f = '1' then
Fall_Clk <= '1';
end if;
end if;
end if;
end process;
process(Clk,Reset)
begin
if Reset='1' then
State <= Idle;
Bit_Cnt <= (others => '0');
S_Reg <= (others => '0');
Scan_Code <= (others => '0');
Parity <= '0';
Scan_Err <= '0';
Code_Readed <= '0';
elsif rising_edge (Clk) then
Code_Readed <= '0';
case State is
when Idle =>
Parity <= '0';
Bit_Cnt <= (others => '0');
-- note that we dont need to clear the Shift Register
if Fall_Clk='1' and PS2_Datr='0' then -- Start bit
Scan_Err <= '0';
State <= Shifting;
end if;
when Shifting =>
if Bit_Cnt >= 9 then
if Fall_Clk='1' then -- Stop Bit
-- Error is (wrong Parity) or (Stop='0') or Overflow
Scan_Err <= (not Parity) or (not PS2_Datr);
Scan_Code <= S_Reg(7 downto 0);
Code_Readed <= '1';
State <= Idle;
end if;
elsif Fall_Clk='1' then
Bit_Cnt <= Bit_Cnt + 1;
S_Reg <= PS2_Datr & S_Reg (S_Reg'high downto 1); -- Shift right
Parity <= Parity xor PS2_Datr;
end if;
when others => -- never reached
State <= Idle;
end case;
--Scan_Err <= '0'; -- to create an on-purpose error on Scan_Err !
end if;
end process;
process(Clk,Reset)
variable aaa : std_logic_vector(7 downto 0);
begin
if Reset='1' then
Matrix <= (others => '0');
Key_Released <= '0';
Extend_Key <= '0';
elsif rising_edge (Clk) then
if Code_Readed = '1' then -- ScanCode is Readed
if Scan_Code = x"F0" then -- Key is Released
Key_Released <= '1';
elsif Scan_Code = x"E0" then -- Extended Key Pressed
Extend_Key <= '1';
else -- Analyse
aaa := (others=>'0');
case Scan_Code is
when x"76" => aaa := "00000001"; -- ESC
when x"5A" => aaa := "00000010"; -- ENTER
when x"75" =>
if Extend_Key = '1' then
aaa := "00000100"; -- UP
end if;
when x"6B" =>
if Extend_Key = '1' then
aaa := "00001000"; -- LEFT
end if;
when x"72" =>
if Extend_Key = '1' then
aaa := "00010000"; -- DOWN
end if;
when x"74" =>
if Extend_Key = '1' then
aaa := "00100000"; -- RIGHT
end if;
when others => null;
end case;
if Key_Released = '0' then
Matrix <= Matrix or aaa;
else
Matrix <= Matrix and not aaa;
end if;
Key_Released <= '0';
Extend_Key <= '0';
end if;
end if;
end if;
end process;
Key_Data <= Matrix;
end Behavioral;
| gpl-3.0 | a40abb616b383e8fea845c937eec355d | 0.451745 | 3.512787 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_07100_bad.vhd | 1 | 3,510 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-10 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_07100_bad.vhd
-- File Creation date : 2015-04-10
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Simulation ending: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_07100_bad is
end STD_07100_bad;
architecture Simulation of STD_07100_bad is
-- All signals for tested modules inputs/outputs
signal Clock : std_logic := '0';
signal Reset_n : std_logic;
signal D_Signal : std_logic;
signal Q_Signal : std_logic;
component DFlipFlop
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic; -- D Flip-Flop output signal
o_Q_n : out std_logic -- D Flip-Flop output signal, inverted
);
end component;
begin
-- The D Flip-Flop to test
T_DFlipFlop : DFlipFlop
port map (
i_Clock => Clock,
i_Reset_n => Reset_n,
i_D => D_Signal,
o_Q => Q_Signal,
o_Q_n => open
);
--CODE
-- Clock process
P_Clock : process
begin
Clock <= not Clock after 5 ns;
end process;
-- Test process
P_Test : process
begin
Reset_n <= '0';
D_Signal <= '0';
wait until rising_edge(Clock);
Reset_n <= '1';
wait until rising_edge(Clock);
D_Signal <= '1';
wait until rising_edge(Clock);
D_Signal <= '0';
wait;
end process;
--CODE
end Simulation;
| gpl-3.0 | 2d14d54cbc84a36868eba05e3064e833 | 0.487179 | 4.398496 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_03200_good.vhd | 1 | 2,741 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-03 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_03200_good.vhd
-- File Creation date : 2015-04-03
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Unused output ports components management: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pkg_HBK.all;
entity STD_03200_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end STD_03200_good;
--CODE
architecture Behavioral of STD_03200_good is
begin
FlipFlop : DFlipFlop
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_D => i_D,
o_Q => o_Q,
o_Q_n => open
);
end Behavioral;
--CODE
| gpl-3.0 | 468ae61b36d2536f750523c358d2e6fb | 0.468077 | 4.583612 | false | false | false | false |
APastorG/APG | average_calculator/average_calculator_tb.vhd | 1 | 6,574 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Xilinx's Vivado
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is a testbench generated for the real_const_multiplier module.
/
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.common_pkg.all;
use work.common_data_types_pkg.all;
use work.fixed_generic_pkg.all;
use work.tb_pkg.all;
use work.real_const_mult_pkg.all;
use work.average_calculator_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity average_calculator_tb is
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture average_calculator_tb1 of average_calculator_tb is
/* generics' constants 1 */
/**************************************************************************************************/
constant UNSIGNED_2COMP_opt : boolean_tb := (true, true); --default
constant DATA_IMM_AFTER_START_opt : boolean_tb := (false, false); --default
constant SPEED_opt : T_speed_tb := (t_max, false); --exception: value not set
constant ROUND_STYLE_opt : T_round_style_tb := (fixed_round, false); --default
constant ROUND_TO_BIT_opt : integer_exc_tb := (-2, false); --exception: value not set
constant MAX_ERROR_PCT_opt : real_exc_tb := (0.01, false); --exception: value not set
constant S : positive := 2; --compulsory
constant used_UNSIGNED_2COMP_opt : boolean := value_used(UNSIGNED_2COMP_opt, false);
constant used_DATA_IMM_AFTER_START_opt : boolean := value_used(DATA_IMM_AFTER_START_opt, true);
constant used_SPEED_opt : T_speed := value_used(SPEED_opt);
constant used_ROUND_STYLE_opt : T_round_style := value_used(ROUND_STYLE_opt, fixed_truncate);
constant used_ROUND_TO_BIT_opt : integer_exc := value_used(ROUND_TO_BIT_opt);
constant used_MAX_ERROR_PCT_opt : real_exc := value_used(MAX_ERROR_PCT_opt);
constant used_S : positive := S;
/* constants 2 */
/**************************************************************************************************/
constant P : positive := 1;
constant NORM_IN_HIGH : integer := 3;
constant NORM_IN_LOW : integer := -3;
constant IN_HIGH : integer := NORM_IN_HIGH + SULV_NEW_ZERO;
constant IN_LOW : integer := NORM_IN_LOW + SULV_NEW_ZERO;
constant NORM_OUT_HIGH : integer := average_calculator_OH(used_UNSIGNED_2COMP_opt,
used_ROUND_STYLE_opt,
used_ROUND_TO_BIT_opt,
used_MAX_ERROR_PCT_opt,
used_S,
P,
NORM_IN_HIGH,
NORM_IN_LOW);
constant NORM_OUT_LOW : integer := average_calculator_OL(used_UNSIGNED_2COMP_opt,
used_ROUND_STYLE_opt,
used_ROUND_TO_BIT_opt,
used_MAX_ERROR_PCT_opt,
used_S,
P,
NORM_IN_HIGH,
NORM_IN_LOW);
constant OUT_HIGH : integer := SULV_NEW_ZERO + NORM_OUT_HIGH;
constant OUT_LOW : integer := SULV_NEW_ZERO + NORM_OUT_LOW;
/* signals 3 */
/**************************************************************************************************/
--IN
signal input : sulv_v(1 to P)(IN_HIGH DOWNTO IN_LOW);
signal clk : std_ulogic;
signal start : std_ulogic;
signal valid_input : std_ulogic;
--OUT
signal output : std_ulogic_vector(OUT_HIGH downto OUT_LOW);
signal valid_output : std_ulogic;
/*================================================================================================*/
/*================================================================================================*/
begin
average_calculator_1:
entity work.average_calculator
generic map(
UNSIGNED_2COMP_opt => used_UNSIGNED_2COMP_opt,
DATA_IMM_AFTER_START_opt => used_DATA_IMM_AFTER_START_opt,
SPEED_opt => used_SPEED_opt,
ROUND_STYLE_opt => used_ROUND_STYLE_opt,
ROUND_TO_BIT_opt => used_ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => used_MAX_ERROR_PCT_opt,
S => used_S)
port map(
input => input,
clk => clk,
start => start,
valid_input => valid_input,
output => output,
valid_output => valid_output
);
end architecture; | mit | 8cf09f23e9af514bd0ca8395b6eae4f2 | 0.364985 | 5.034642 | false | false | false | false |
sonologic/gmzpu | vhdl/devices/br_gen.vhdl | 1 | 4,728 | ------------------------------------------------------------------------------
---- ----
---- RS-232 baudrate generator ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- This counter is a parametrizable clock divider. The count value is ----
---- the generic parameter COUNT. It has a chip enable ce_i input. ----
---- (will count only if CE is high). ----
---- When it overflows, will emit a pulse on o_o. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Philippe Carton, philippe.carton2 libertysurf.fr ----
---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2001-2003 Philippe Carton ----
---- Copyright (c) 2005 Juan Pablo Daniel Borgna ----
---- Copyright (c) 2005-2008 Salvador E. Tropea ----
---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: BRGen(Behaviour) (Entity and architecture) ----
---- File name: br_gen.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- Target FPGA: Spartan ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity BRGen is
generic(
COUNT : integer range 0 to 65535);-- Count revolution
port (
clk_i : in std_logic; -- Clock
reset_i : in std_logic; -- Reset input
ce_i : in std_logic; -- Chip Enable
o_o : out std_logic); -- Output
end entity BRGen;
architecture Behaviour of BRGen is
begin
CountGen:
if COUNT/=1 generate
Counter:
process (clk_i)
variable cnt : integer range 0 to COUNT-1;
begin
if rising_edge(clk_i) then
o_o <= '0';
if reset_i='1' then
cnt:=COUNT-1;
elsif ce_i='1' then
if cnt=0 then
o_o <= '1';
cnt:=COUNT-1;
else
cnt:=cnt-1;
end if; -- cnt/=0
end if; -- ce_i='1'
end if; -- rising_edge(clk_i)
end process Counter;
end generate CountGen;
CountWire:
if COUNT=1 generate
o_o <= '0' when reset_i='1' else ce_i;
end generate CountWire;
end architecture Behaviour; -- Entity: BRGen
| bsd-3-clause | 73b978cec269f94e89846f394edfc982 | 0.289975 | 5.902622 | false | false | false | false |
sonologic/gmzpu | vhdl/ZetaIO/interrupt/interrupt.vhdl | 1 | 14,161 | ------------------------------------------------------------------------------
---- ----
---- Programmable Interrupt Controller (PIC) ----
---- ----
---- http://github.com/sonologic/gmzpu ----
---- ----
---- Description: ----
---- gmZPU interrupt controller. Parametrised design to create ----
---- a PIC with a number of N_BANKS registers. Each bank ----
---- has the full set of ICR, IMR, ITR and IER registers for ----
---- DATA_WIDTH interrupt lines. ----
---- ----
---- Author: ----
---- - "Koen Martens" <gmc sonologic.nl> ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2014 Koen Martens ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: interrupt_controller ----
---- File name: interrupt.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: gmzpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: N/A ----
---- Language: VHDL ----
---- Wishbone: Yes ----
---- Synthesis tools: ModelSim ----
---- Simulation tools: ModelSim ----
---- Text editor: vim ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity interrupt_line is
port (
clk_i : in std_logic; -- system clock
int_i : in std_logic; -- input line
irq_o : out std_logic; -- interrupt request
icr_o : out std_logic; -- interrupt cause out
icr_i : in std_logic; -- interrupt cause reset (qualified by we_i)
imr_i : in std_logic; -- interrupt mask
ier_i : in std_logic; -- interrupt edge type, 0=rising, 1=falling
itr_i : in std_logic; -- interrupt type, 0=edge trig, 1=level trig
we_i : in std_logic -- write enable (qualifies icr_i)
);
end entity interrupt_line;
architecture rtl of interrupt_line is
signal q : std_logic;
signal sample_r : std_logic;
begin
edge_triggered:
process(clk_i)
variable rising_r : std_logic;
variable falling_r : std_logic;
variable level_r : std_logic;
begin
rising_r := '0';
falling_r := '0';
if we_i='0' then
if sample_r='0' then
if int_i='1' then
rising_r := '1';
end if;
else
if int_i='0' then
falling_r := '1';
end if;
end if;
level_r := itr_i and int_i;
if itr_i='0' then
if rising_r='1' and ier_i='0' then
q <= '1';
elsif falling_r='1' and ier_i='1' then
q <= '1';
end if;
else --if itr='1' then
if level_r='1' then
q <= '1';
else
q <= '0';
end if;
end if;
else
-- we_i='1'
if icr_i='0' then
q <= '0';
end if;
end if;
sample_r <= int_i;
end process;
-- output
icr_o <= q;
irq_o <= q and imr_i;
end architecture rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity interrupt_regs is
generic (
DATA_WIDTH : natural:=32
);
port (
rst_i : in std_logic;
clk_i : in std_logic;
int_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
adr_i : in unsigned(1 downto 0);
dat_i : in unsigned(DATA_WIDTH-1 downto 0);
dat_o : out unsigned(DATA_WIDTH-1 downto 0);
we_i : in std_logic;
en_i : in std_logic;
ready_o : out std_logic;
irq_o : out std_logic
);
end entity interrupt_regs;
architecture rtl of interrupt_regs is
component interrupt_line is
port (
clk_i : in std_logic; -- system clock
int_i : in std_logic; -- input line
irq_o : out std_logic; -- interrupt request
icr_o : out std_logic; -- interrupt cause out
icr_i : in std_logic; -- interrupt cause reset (qualified by we_i)
imr_i : in std_logic; -- interrupt mask
ier_i : in std_logic; -- interrupt edge type, 0=rising, 1=falling
itr_i : in std_logic; -- interrupt type, 0=edge trig, 1=level trig
we_i : in std_logic -- write enable (qualifies icr_i)
);
end component interrupt_line;
-- cause, 0=deasserted, 1=asserted, write only resets, 1's are ignored
signal ICR : std_logic_vector(DATA_WIDTH-1 downto 0);
-- mask, 0=do not assert irq, 1=do assert irq
signal IMR : std_logic_vector(DATA_WIDTH-1 downto 0);
-- type, 0=edge, 1=level
signal ITR : std_logic_vector(DATA_WIDTH-1 downto 0);
-- edge, 0=rising, 1=falling
signal IER : std_logic_vector(DATA_WIDTH-1 downto 0);
signal irq : std_logic_vector(DATA_WIDTH-1 downto 0);
signal icr_we : std_logic;
--signal reading_r : std_logic;
signal ready_r : std_logic;
signal dat_r : unsigned(DATA_WIDTH-1 downto 0);
begin
-- we to interrupt lines when upstream we or reset
icr_we <= (en_i and we_i) or (rst_i);
dat_r <= dat_i when rst_i='0' else (dat_r'range => '0');
icr_generator:
for i in DATA_WIDTH-1 downto 0 generate
ICRX : interrupt_line
port map (
clk_i => clk_i,
int_i => int_i(i),
irq_o => irq(i),
icr_o => ICR(i),
icr_i => dat_r(i),
imr_i => IMR(i),
ier_i => IER(i),
itr_i => ITR(i),
we_i => icr_we
);
end generate icr_generator;
irq_o <= '0' when irq=(irq'range => '0') else '1';
data_out:
process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i='1' then
dat_o <= (others => 'Z');
IMR <= (others => '0');
ITR <= (others => '0');
IER <= (others => '0');
elsif en_i='1' then
dat_o <= (others => 'Z');
if ready_r='0' then
if we_i='1' then
case adr_i is
when "00" => null;
when "01" => IMR <= std_logic_vector(dat_i);
when "10" => ITR <= std_logic_vector(dat_i);
when others => IER <= std_logic_vector(dat_i);
end case;
else
case adr_i is
when "00" => dat_o <= unsigned(ICR);
when "01" => dat_o <= unsigned(IMR);
when "10" => dat_o <= unsigned(ITR);
when others => dat_o <= unsigned(IER);
end case;
end if;
end if;
else
dat_o <= (others => 'Z');
end if;
end if;
end process;
memory_timing:
process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i='1' then
ready_r <= '0';
elsif en_i='1' then
if ready_r='1' then
ready_r <= '0';
else
ready_r <= '1';
end if;
else
-- en_i='0'
ready_r <= '0';
end if; -- en_i='1'
end if; -- rising_edge(clk_i)
end process;
ready_o <= en_i and ready_r;
end architecture rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity interrupt_controller is
generic(
-- address width (truncated to DATA_WIDTH)
ADR_WIDTH : natural:=16;
-- data bus width
DATA_WIDTH : natural:=16;
-- number of interrupt banks (each bank is DATA_WIDTH interrupt lines)
N_BANKS : natural:=2
);
port (
irq_o : out std_logic;
-- interrupt lines
int_i : in std_logic_vector((N_BANKS*DATA_WIDTH)-1 downto 0);
-- wishbone bus
rst_i : in std_logic;
clk_i : in std_logic;
wb_dat_o : out unsigned(DATA_WIDTH-1 downto 0);
wb_dat_i : in unsigned(DATA_WIDTH-1 downto 0);
wb_tgd_o : out unsigned(DATA_WIDTH-1 downto 0);
wb_tgd_i : in unsigned(DATA_WIDTH-1 downto 0);
wb_ack_o : out std_logic;
wb_adr_i : in unsigned(ADR_WIDTH-1 downto 0);
wb_cyc_i : in std_logic;
wb_stall_o : out std_logic;
wb_err_o : out std_logic;
wb_lock_i : in std_logic;
wb_rty_o : out std_logic;
wb_sel_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
wb_stb_i : in std_logic;
wb_tga_i : in unsigned(ADR_WIDTH-1 downto 0);
wb_tgc_i : in unsigned(DATA_WIDTH-1 downto 0); -- size correct?
wb_we_i : in std_logic
);
end entity interrupt_controller;
architecture rtl of interrupt_controller is
component interrupt_regs is
generic (
DATA_WIDTH : natural:=32
);
port (
rst_i : in std_logic;
clk_i : in std_logic;
int_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
adr_i : in unsigned(1 downto 0);
dat_i : in unsigned(DATA_WIDTH-1 downto 0);
dat_o : out unsigned(DATA_WIDTH-1 downto 0);
we_i : in std_logic;
en_i : in std_logic;
irq_o : out std_logic;
ready_o : out std_logic
);
end component interrupt_regs;
signal regen_r : std_logic_vector(N_BANKS-1 downto 0);
signal ready_r : std_logic_vector(N_BANKS-1 downto 0);
signal irq_r : std_logic_vector(N_BANKS-1 downto 0);
signal cs_r : unsigned(ADR_WIDTH-5 downto 0);
signal adr_r : unsigned(1 downto 0);
signal ack_r : std_logic;
begin
-- TODO: assert on address width < 6 (6 depends on N_BANKS)
-- unsupported signals
wb_tgd_o <= (others => '0') when wb_cyc_i='1' else (others => 'Z');
wb_stall_o <= '0' when wb_cyc_i='1' else 'Z';
wb_err_o <= '0' when wb_cyc_i='1' else 'Z';
wb_rty_o <= '0' when wb_cyc_i='1' else 'Z';
-- split address bus in cs (msb) and adr (lsb)
cs_r <= wb_adr_i(ADR_WIDTH-1 downto 4);
-- strip trailing byte addresses as reg address 32-bit words
adr_r <= wb_adr_i(3 downto 2);
-- ack propagation
ack_r <= '0' when ready_r=(ready_r'range=>'0') else '1';
wb_ack_o <= wb_cyc_i and ack_r;
-- aggregate bank irq's into irq_o
irq_o <= '0' when irq_r=(irq_r'range => '0') else '1';
-- register generator, create N_BANKS regs
reg_generator:
for i in N_BANKS-1 downto 0 generate
regsX : interrupt_regs
generic map (
DATA_WIDTH => DATA_WIDTH
)
port map (
rst_i => rst_i, clk_i => clk_i,
adr_i => adr_r, dat_i => wb_dat_i, dat_o => wb_dat_o,
we_i => wb_we_i, en_i => regen_r(i), ready_o => ready_r(i), irq_o => irq_r(i),
int_i => int_i(((i+1)*DATA_WIDTH)-1 downto i*DATA_WIDTH)
);
end generate reg_generator;
process(wb_cyc_i,cs_r,rst_i)
begin
if rst_i='1' then
regen_r <= (others => '0');
else
regen_r <= (others => '0');
if wb_cyc_i='1' then
-- decode address
for i in N_BANKS-1 downto 0 loop
if cs_r = to_unsigned(i, cs_r'length) then
regen_r(i) <= '1';
end if;
end loop;
end if;
end if;
end process;
end architecture rtl;
| bsd-3-clause | cdbb8305fa1fa5298866572dc1206152 | 0.402161 | 4.11657 | false | false | false | false |
223323/lab2 | HDL/source/rtl/vhdl/vga_top.vhd | 1 | 12,479 | -------------------------------------------------------------------------------
-- Department of Computer Engineering and Communications
-- Author: LPRS2 <[email protected]>
--
-- Module Name: vga_top
--
-- Description:
--
-- Top of VGA control with graphics and text
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity vga_top is
generic (
H_RES : natural := 640;
V_RES : natural := 480;
MEM_ADDR_WIDTH : natural := 32;
GRAPH_MEM_ADDR_WIDTH : natural := 32;
TEXT_MEM_DATA_WIDTH : natural := 32;
GRAPH_MEM_DATA_WIDTH : natural := 32;
RES_TYPE : natural := 0;
MEM_SIZE : natural := 4800
);
port (
clk_i : in std_logic;
reset_n_i : in std_logic;
--
direct_mode_i : in std_logic; -- 0 - text and graphics interface mode, 1 - direct mode (direct force RGB component)
dir_red_i : in std_logic_vector(7 downto 0);
dir_green_i : in std_logic_vector(7 downto 0);
dir_blue_i : in std_logic_vector(7 downto 0);
dir_pixel_column_o : out std_logic_vector(10 downto 0);
dir_pixel_row_o : out std_logic_vector(10 downto 0);
-- mode interface
display_mode_i : in std_logic_vector(1 downto 0); -- 01 - text mode, 10 - graphics mode, 11 - text and graphics
-- text mode interface
text_addr_i : in std_logic_vector(MEM_ADDR_WIDTH-1 downto 0);
text_data_i : in std_logic_vector(TEXT_MEM_DATA_WIDTH-1 downto 0);
text_we_i : in std_logic;
-- graphics mode interface
graph_addr_i : in std_logic_vector(GRAPH_MEM_ADDR_WIDTH-1 downto 0);
graph_data_i : in std_logic_vector(GRAPH_MEM_DATA_WIDTH-1 downto 0);
graph_we_i : in std_logic;
-- cfg
font_size_i : in std_logic_vector(3 downto 0);
show_frame_i : in std_logic;
foreground_color_i : in std_logic_vector(23 downto 0);
background_color_i : in std_logic_vector(23 downto 0);
frame_color_i : in std_logic_vector(23 downto 0);
-- vga
vga_hsync_o : out std_logic;
vga_vsync_o : out std_logic;
blank_o : out std_logic;
pix_clock_o : out std_logic;
vga_rst_n_o : out std_logic;
psave_o : out std_logic;
sync_o : out std_logic;
red_o : out std_logic_vector(7 downto 0);
green_o : out std_logic_vector(7 downto 0);
blue_o : out std_logic_vector(7 downto 0)
);
end vga_top;
architecture rtl of vga_top is
component vga is generic (
RESOLUTION_TYPE : natural := 0;
H_RES : natural := 640;
V_RES : natural := 480
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
--
direct_mode_i : in std_logic; -- 0 - text and graphics interface mode, 1 - direct mode (direct force RGB component)
dir_red_i : in std_logic_vector(7 downto 0);
dir_green_i : in std_logic_vector(7 downto 0);
dir_blue_i : in std_logic_vector(7 downto 0);
-- cfg
show_frame_i : in std_logic;
active_pixel_i : in std_logic;
foreground_color_i : in std_logic_vector(23 downto 0);
background_color_i : in std_logic_vector(23 downto 0);
frame_color_i : in std_logic_vector(23 downto 0);
-- vga
red_o : out std_logic_vector(7 downto 0);
green_o : out std_logic_vector(7 downto 0);
blue_o : out std_logic_vector(7 downto 0);
pixel_row_o : out std_logic_vector(10 downto 0);
pixel_column_o : out std_logic_vector(10 downto 0);
hsync_o : out std_logic;
vsync_o : out std_logic;
psave_o : out std_logic;
blank_o : out std_logic;
vga_pix_clk_o : out std_logic;
vga_rst_n_o : out std_logic;
sync_o : out std_logic
);
end component vga;
component char_rom
is port (
clk_i : in std_logic;
character_address_i : in std_logic_vector (5 downto 0);
font_row_i : in std_logic_vector (2 downto 0);
font_col_i : in std_logic_vector (2 downto 0);
rom_mux_output_o : out std_logic
);
end component char_rom;
component text_mem
generic(
MEM_ADDR_WIDTH : natural := 20;
MEM_DATA_WIDTH : natural := 32;
MEM_SIZE : natural := 4800
);
port(
clk_i : in std_logic;
reset_n_i : in std_logic;
--
wr_addr_i : in std_logic_vector(MEM_ADDR_WIDTH-1 downto 0);
rd_addr_i : in std_logic_vector(MEM_ADDR_WIDTH-1 downto 0);
wr_data_i : in std_logic_vector(MEM_DATA_WIDTH-1 downto 0);
we_i : in std_logic;
rd_data_o : out std_logic_vector(MEM_DATA_WIDTH-1 downto 0)
);
end component;
component graphics_mem is
generic(
MEM_ADDR_WIDTH : natural := 32;
MEM_DATA_WIDTH : natural := 32;
MEM_SIZE : natural := 4800
);
port(
clk_i : in std_logic;
reset_n_i : in std_logic;
--
wr_addr_i : in std_logic_vector(MEM_ADDR_WIDTH-1 downto 0);
rd_addr_i : in std_logic_vector(MEM_ADDR_WIDTH-1 downto 0);
wr_data_i : in std_logic_vector(MEM_DATA_WIDTH-1 downto 0);
we_i : in std_logic;
rd_data_o : out std_logic
);
end component;
-- rezolucija ekrana
signal horizontal_res : std_logic_vector(11-1 downto 0);
signal horizontal_res_c : std_logic_vector(11-1 downto 0);
signal vertical_res : std_logic_vector(11-1 downto 0);
signal grid_size : integer; -- size of step based on char size
signal pix_clk_s : std_logic;
signal vga_rst_n_s : std_logic;
signal pixel_row_s : std_logic_vector(11-1 downto 0);
signal pixel_column_s : std_logic_vector(11-1 downto 0);
signal pixel_row_c : std_logic_vector(11-1 downto 0);
signal pixel_column_c : std_logic_vector(11-1 downto 0);
-- char rom
signal char_addr_s : std_logic_vector(TEXT_MEM_DATA_WIDTH-1 downto 0);
signal font_col_s : std_logic_vector(2 downto 0);
signal font_row_s : std_logic_vector(2 downto 0);
signal rom_out_s : std_logic;
-- tx_rom
signal txt_rom_addr_c : std_logic_vector(2*11-1 downto 0);
signal txt_ram_addr_s : std_logic_vector(MEM_ADDR_WIDTH-1 downto 0);
signal graph_pixel_addr_c : std_logic_vector(2*11-1 downto 0);
signal graph_pixel_addr_s : std_logic_vector(GRAPH_MEM_ADDR_WIDTH-1 downto 0);
signal graph_pixel_s : std_logic;
signal active_pixel_s : std_logic;
begin
vga_i:vga
generic map(
RESOLUTION_TYPE => RES_TYPE,
H_RES => H_RES,
V_RES => V_RES
)
port map (
clk_i => clk_i,
rst_n_i => reset_n_i,
--
direct_mode_i => direct_mode_i,
dir_red_i => dir_red_i,
dir_green_i => dir_green_i,
dir_blue_i => dir_blue_i,
-- cfg
show_frame_i => show_frame_i,
active_pixel_i => active_pixel_s,
foreground_color_i => foreground_color_i,
background_color_i => background_color_i,
frame_color_i => frame_color_i,
-- vga
red_o => red_o,
green_o => green_o,
blue_o => blue_o,
pixel_row_o => pixel_row_s,
pixel_column_o => pixel_column_s,
hsync_o => vga_hsync_o,
vsync_o => vga_vsync_o,
psave_o => psave_o,
blank_o => blank_o,
vga_pix_clk_o => pix_clk_s,
vga_rst_n_o => vga_rst_n_s,
sync_o => sync_o
);
dir_pixel_column_o <= pixel_column_s;
dir_pixel_row_o <= pixel_row_s;
-- multiplex source
active_pixel_s <= rom_out_s when (display_mode_i = "01") else
graph_pixel_s when (display_mode_i = "10") else
rom_out_s xor graph_pixel_s when (display_mode_i = "11");
char_rom_i:char_rom
port map(
clk_i => pix_clk_s,
character_address_i => char_addr_s, -- char address
font_row_i => font_row_s, -- font size
font_col_i => font_col_s, -- font size
rom_mux_output_o => rom_out_s -- char pixel value
);
text_mem_i:text_mem
generic map(
MEM_ADDR_WIDTH => MEM_ADDR_WIDTH,
MEM_DATA_WIDTH => TEXT_MEM_DATA_WIDTH,
MEM_SIZE => MEM_SIZE
)
port map(
clk_i => pix_clk_s,
reset_n_i => vga_rst_n_s,
--
wr_addr_i => text_addr_i,
wr_data_i => text_data_i,
we_i => text_we_i,
rd_addr_i => txt_ram_addr_s,
rd_data_o => char_addr_s
);
graphics_mem_i:graphics_mem
generic map(
MEM_ADDR_WIDTH => GRAPH_MEM_ADDR_WIDTH,
MEM_DATA_WIDTH => GRAPH_MEM_DATA_WIDTH,
MEM_SIZE => MEM_SIZE*8*8--full size per pixel (MEM_SIZE is defined per char)
)
port map(
clk_i => pix_clk_s,
reset_n_i => vga_rst_n_s,
--
wr_addr_i => graph_addr_i,
wr_data_i => graph_data_i,
we_i => graph_we_i,
rd_addr_i => graph_pixel_addr_s,
rd_data_o => graph_pixel_s
);
graph_pixel_addr_c <= pixel_row_s*horizontal_res + pixel_column_s;
graph_pixel_addr_s <= graph_pixel_addr_c(GRAPH_MEM_ADDR_WIDTH-1 downto 0);
--txt_ram_addr_s <= pixel_row_s/grid_size *horizontal_res/grid_size + pixel_column_s/grid_size;
txt_rom_addr_c <= pixel_row_c*horizontal_res_c + pixel_column_c;
txt_ram_addr_s <= txt_rom_addr_c(MEM_ADDR_WIDTH-1 downto 0);
-- get pixel row and column range according selected font size
pixel_row_c <= "000000" & pixel_row_s(pixel_row_s'length-1 downto 6) when (font_size_i = 3) else
"00000" & pixel_row_s(pixel_row_s'length-1 downto 5) when (font_size_i = 2) else
"0000" & pixel_row_s(pixel_row_s'length-1 downto 4) when (font_size_i = 1) else
"000" & pixel_row_s(pixel_row_s'length-1 downto 3);
pixel_column_c <= "000000" & pixel_column_s(pixel_column_s'length-1 downto 6) when (font_size_i = 3) else
"00000" & pixel_column_s(pixel_column_s'length-1 downto 5) when (font_size_i = 2) else
"0000" & pixel_column_s(pixel_column_s'length-1 downto 4) when (font_size_i = 1) else
"000" & pixel_column_s(pixel_column_s'length-1 downto 3);
horizontal_res <= conv_std_logic_vector(H_RES, 11);
horizontal_res_c <= "000000" & horizontal_res(horizontal_res'length-1 downto 6) when (font_size_i = 3) else
"00000" & horizontal_res(horizontal_res'length-1 downto 5) when (font_size_i = 2) else
"0000" & horizontal_res(horizontal_res'length-1 downto 4) when (font_size_i = 1) else
"000" & horizontal_res(horizontal_res'length-1 downto 3);
font_row_s <= pixel_row_s(5 downto 3) when (font_size_i = 3) else
pixel_row_s(4 downto 2) when (font_size_i = 2) else
pixel_row_s(3 downto 1) when (font_size_i = 1) else
pixel_row_s(2 downto 0);
font_col_s <= pixel_column_s(5 downto 3) when (font_size_i = 3) else
pixel_column_s(4 downto 2) when (font_size_i = 2) else
pixel_column_s(3 downto 1) when (font_size_i = 1) else
pixel_column_s(2 downto 0)-1;-- because of synchronous memory read there is one cycle delay with char_addr_s, so font_col and font_row should be delayed also
grid_size <= 64 when (font_size_i = 3) else
32 when (font_size_i = 2) else
16 when (font_size_i = 1) else
8;
pix_clock_o <= pix_clk_s;
vga_rst_n_o <= vga_rst_n_s;
end rtl; | mit | c2e52f5f993d4b45521bee953ae0f2cf | 0.528969 | 3.212925 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/pokey_poly_17_9.vhdl | 1 | 1,712 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY pokey_poly_17_9 IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
SELECT_9_17 : IN STD_LOGIC; -- 9 high, 17 low
INIT : IN STD_LOGIC;
BIT_OUT : OUT STD_LOGIC;
RAND_OUT : OUT std_logic_vector(7 downto 0)
);
END pokey_poly_17_9;
ARCHITECTURE vhdl OF pokey_poly_17_9 IS
signal shift_reg: std_logic_vector(16 downto 0);
signal shift_next: std_logic_vector(16 downto 0);
signal feedback : std_logic;
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
shift_reg <= "01010101010101010";
elsif (clk'event and clk='1') then
shift_reg <= shift_next;
end if;
end process;
-- next state (as pokey decap)
feedback <= shift_reg(13) xnor shift_reg(8);
process(enable,shift_reg,feedback,select_9_17,init)
begin
shift_next <= shift_reg;
if (enable = '1') then
shift_next(15 downto 8) <= shift_reg(16 downto 9);
shift_next(7) <= feedback;
shift_next(6 downto 0) <= shift_reg(7 downto 1);
shift_next(16) <= ((feedback and select_9_17) or (shift_reg(0) and not(select_9_17))) and not(init);
end if;
end process;
-- output
bit_out <= shift_reg(9);
RAND_OUT(7 downto 0) <= not(shift_reg(15 downto 8));
END vhdl;
| gpl-3.0 | e95391e5352d3afb7769deb00c27b89c | 0.614486 | 3.062612 | false | false | false | false |
APastorG/APG | adder/adder_core_u.vhd | 1 | 30,695 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Vivado by Xilinx
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is a design of a parameterized adder which allows the addition of signed numbers
/ with high fexibility and control over the way data is introduced and the level of pipelining it
/ will be used
/ ┌ ┌───────┐
/ │ │ i e a │
/ input: P│ │ j f b │ _______
/ │ │ k g c │ ----> | adder | ----> result
/ │ │ l h d │ ───────
/ └ └───────┘
/ └───────┘
/ S
/ The clock cycles it takes to produce a result from the input can also be specified with the
/ SPEED_opt parameter. The higher this parameter, the shorter, in general, the delay path
/ between each register and thus, the higher the frequency the design is able to reach.
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.adder_pkg.all;
use work.counter_pkg.all;
use work.fixed_generic_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity adder_core_u is
generic(
DATA_IMM_AFTER_START_opt : boolean := false; --default
SPEED_opt : T_speed := t_min; --exception: value not set
MAX_POSSIBLE_BIT_opt : integer_exc := integer'low; --exception: value not set
TRUNCATE_TO_BIT_opt : integer_exc := integer'low; --exception: value not set
S : positive; --compulsory
P : positive; --compulsory
input_high : integer;
input_low : integer
);
port(
input : in u_ufixed_v(1 to P); --unconstrained array
clk : in std_ulogic;
start : in std_ulogic;
valid_input : in std_ulogic;
output : out u_ufixed(adder_OH(MAX_POSSIBLE_BIT_opt,
S,
P,
input_high)
downto
adder_OL(TRUNCATE_TO_BIT_opt,
input_low)
);
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture adder_core_u_1 of adder_core_u is
/* corrected generics and internal/external ports' sizes */
/**************************************************************************************************/
constant CHECKS : integer := adder_CHECKS(MAX_POSSIBLE_BIT_opt,
TRUNCATE_TO_BIT_opt,
S,
P,
input(1)'high,
input(1)'low);
constant DATA_WIDTH : positive := input(1)'length;
constant DATA_HIGH : integer := input(1)'high;
constant DATA_LOW : integer := input(1)'low;
constant OUTPUT_HIGH : integer := adder_OH(MAX_POSSIBLE_BIT_opt,
S,
P,
DATA_HIGH);
constant OUTPUT_LOW : integer := adder_OL(TRUNCATE_TO_BIT_opt,
DATA_LOW);
constant DATA_IMM_AFTER_START : boolean := DATA_IMM_AFTER_START_opt;
constant MAX_POSSIBLE_BIT : integer := ite(MAX_POSSIBLE_BIT_opt=integer'low,
integer'high - SULV_NEW_ZERO,
MAX_POSSIBLE_BIT_opt);
constant ADD_LEVELS : positive := 1 + log2ceil(P);
constant PIPELINE_POSITIONS : natural := ite(S = 1,
ADD_LEVELS,
ADD_LEVELS + 1);
constant PIPELINES_2_INTRODUCE : natural := number_of_pipelines(PIPELINE_POSITIONS,
SPEED_opt);
constant CONDITION_EXC : boolean := (not DATA_IMM_AFTER_START)
and
((S = 1 and PIPELINES_2_INTRODUCE=0)
or
PIPELINES_2_INTRODUCE < 2);
function is_pipelines_exc(
s : positive;
pipeline_positions : natural)
return boolean_v is
variable result : boolean_v(1 to pipeline_positions) := (others => false);
begin
result(ite(s = 1,
pipeline_positions,
pipeline_positions-1)) := true;
return result;
end function;
constant IS_PIPELINED_EXC : boolean_v := is_pipelines_exc(S,
PIPELINE_POSITIONS);
constant IS_PIPELINED : boolean_v := ite(CONDITION_EXC,
IS_PIPELINED_EXC,
generate_pipelines(PIPELINE_POSITIONS,
SPEED_opt)
);
constant OUTPUT_BUFFER : boolean := ite(S = 1,
false,
ite(CONDITION_EXC,
false,
IS_PIPELINED(PIPELINE_POSITIONS))
);
constant ACC_PIPELINES : natural := S - 1;
constant ADD_PIPELINES : natural := ite(CONDITION_EXC,
1,
PIPELINES_2_INTRODUCE - ite(OUTPUT_BUFFER, 1, 0)
);
constant PIPELINES : natural := ADD_PIPELINES + ACC_PIPELINES + ite(OUTPUT_BUFFER,
1,
0);
/* other constants */
/**************************************************************************************************/
constant INTER_HIGH : integer := minimum(DATA_HIGH + log2ceil(P),
MAX_POSSIBLE_BIT);
/* data signals */
/**************************************************************************************************/
signal input_resolved : ufixed_v(1 to P)(input(1)'range); --where the input is converted to resolved
signal inter : u_ufixed(INTER_HIGH downto DATA_LOW);
signal output_inter : u_ufixed(OUTPUT_HIGH downto DATA_LOW);
signal start_sh : std_ulogic_vector(1 to ADD_PIPELINES);
signal valid_input_sh : std_ulogic_vector(1 to ADD_PIPELINES);
/* control signals */
/**************************************************************************************************/
signal start_delayed : std_ulogic;
signal valid_input_delayed : std_ulogic;
signal counter_out : std_ulogic;
/* structures to store and manipulate data of the adder tree (ADD) */
/**************************************************************************************************/
function T_ADD_state_data_high(
index : natural)
return integer is
begin
if DATA_HIGH+index > MAX_POSSIBLE_BIT then
return MAX_POSSIBLE_BIT;
else
return DATA_HIGH + index;
end if;
end function;
type T_ADD_state is record
level0 : ufixed_v(1 to signals_per_level(P, 0 ))(T_ADD_state_data_high(0) downto DATA_LOW);
level1 : ufixed_v(1 to signals_per_level(P, 1 ))(T_ADD_state_data_high(1) downto DATA_LOW);
level2 : ufixed_v(1 to signals_per_level(P, 2 ))(T_ADD_state_data_high(2) downto DATA_LOW);
level3 : ufixed_v(1 to signals_per_level(P, 3 ))(T_ADD_state_data_high(3) downto DATA_LOW);
level4 : ufixed_v(1 to signals_per_level(P, 4 ))(T_ADD_state_data_high(4) downto DATA_LOW);
level5 : ufixed_v(1 to signals_per_level(P, 5 ))(T_ADD_state_data_high(5) downto DATA_LOW);
level6 : ufixed_v(1 to signals_per_level(P, 6 ))(T_ADD_state_data_high(6) downto DATA_LOW);
level7 : ufixed_v(1 to signals_per_level(P, 7 ))(T_ADD_state_data_high(7) downto DATA_LOW);
level8 : ufixed_v(1 to signals_per_level(P, 8 ))(T_ADD_state_data_high(8) downto DATA_LOW);
level9 : ufixed_v(1 to signals_per_level(P, 9 ))(T_ADD_state_data_high(9) downto DATA_LOW);
level10 : ufixed_v(1 to signals_per_level(P, 10))(T_ADD_state_data_high(10)downto DATA_LOW);
level11 : ufixed_v(1 to signals_per_level(P, 11))(T_ADD_state_data_high(11)downto DATA_LOW);
end record;
-- in Vivado and ModelSim
-- this constant is used because even driving only one member of a structure implies driving the
-- whole structure. So with resolved signals the analysis takes places without problems and the
-- subsequent synthesis generates the desired structure.
constant ADD_Z : T_ADD_state:=(level0 => (others=>(others=>'Z')),
level1 => (others=>(others=>'Z')),
level2 => (others=>(others=>'Z')),
level3 => (others=>(others=>'Z')),
level4 => (others=>(others=>'Z')),
level5 => (others=>(others=>'Z')),
level6 => (others=>(others=>'Z')),
level7 => (others=>(others=>'Z')),
level8 => (others=>(others=>'Z')),
level9 => (others=>(others=>'Z')),
level10 => (others=>(others=>'Z')),
level11 => (others=>(others=>'Z')));
-- ADD_in stores the signals entering the levels of the adder tree
-- ADD_out stores the signals leaving
signal ADD_in : T_ADD_state := ADD_Z;
signal ADD_out : T_ADD_state := ADD_Z;
/* functions to read and procedures to write from/to T_ADD_state */
/**************************************************************************************************/
function T_ADD_state_read(
state : T_ADD_state;
level : natural)
return ufixed_v is
begin
case level is
when 0 => return state.level0;
when 1 => return state.level1;
when 2 => return state.level2;
when 3 => return state.level3;
when 4 => return state.level4;
when 5 => return state.level5;
when 6 => return state.level6;
when 7 => return state.level7;
when 8 => return state.level8;
when 9 => return state.level9;
when 10 => return state.level10;
when others => return state.level11;
end case;
end function;
function T_ADD_state_read(
state : T_ADD_state;
level : natural;
signal_number : integer)
return u_ufixed is
begin
case level is
when 0 => return state.level0(signal_number);
when 1 => return state.level1(signal_number);
when 2 => return state.level2(signal_number);
when 3 => return state.level3(signal_number);
when 4 => return state.level4(signal_number);
when 5 => return state.level5(signal_number);
when 6 => return state.level6(signal_number);
when 7 => return state.level7(signal_number);
when 8 => return state.level8(signal_number);
when 9 => return state.level9(signal_number);
when 10 => return state.level10(signal_number);
when others => return state.level11(signal_number);
end case;
end function;
procedure T_ADD_state_write(
signal state : inout T_ADD_state;
constant level : in natural;
constant new_value : in ufixed_v) is
begin
--for loop introduced because of obscure error in Active-HDL:
--Error DAGGEN_0700: Fatal error : INTERNAL CODE GENERATOR ERROR
for i in new_value'range loop
case level is
when 0 => state.level0(i) <= new_value(i);
when 1 => state.level1(i) <= new_value(i);
when 2 => state.level2(i) <= new_value(i);
when 3 => state.level3(i) <= new_value(i);
when 4 => state.level4(i) <= new_value(i);
when 5 => state.level5(i) <= new_value(i);
when 6 => state.level6(i) <= new_value(i);
when 7 => state.level7(i) <= new_value(i);
when 8 => state.level8(i) <= new_value(i);
when 9 => state.level9(i) <= new_value(i);
when 10 => state.level10(i) <= new_value(i);
when others => state.level11(i) <= new_value(i);
end case;
end loop;
end procedure;
procedure T_ADD_state_write(
signal state : inout T_ADD_state;
constant level : in natural;
constant signal_number : in integer;
constant new_value : in ufixed) is
begin
case level is
when 0 => state.level0(signal_number) <= new_value;
when 1 => state.level1(signal_number) <= new_value;
when 2 => state.level2(signal_number) <= new_value;
when 3 => state.level3(signal_number) <= new_value;
when 4 => state.level4(signal_number) <= new_value;
when 5 => state.level5(signal_number) <= new_value;
when 6 => state.level6(signal_number) <= new_value;
when 7 => state.level7(signal_number) <= new_value;
when 8 => state.level8(signal_number) <= new_value;
when 9 => state.level9(signal_number) <= new_value;
when 10 => state.level10(signal_number) <= new_value;
when others => state.level11(signal_number) <= new_value;
end case;
end procedure;
procedure T_ADD_state_copy(
signal from_state : in T_ADD_state;
signal to_state : inout T_ADD_state;
constant level : in natural) is
begin
case level is
when 0 => to_state.level0 <= from_state.level0;
when 1 => to_state.level1 <= from_state.level1;
when 2 => to_state.level2 <= from_state.level2;
when 3 => to_state.level3 <= from_state.level3;
when 4 => to_state.level4 <= from_state.level4;
when 5 => to_state.level5 <= from_state.level5;
when 6 => to_state.level6 <= from_state.level6;
when 7 => to_state.level7 <= from_state.level7;
when 8 => to_state.level8 <= from_state.level8;
when 9 => to_state.level9 <= from_state.level9;
when 10 => to_state.level10 <= from_state.level10;
when others => to_state.level11 <= from_state.level11;
end case;
end procedure;
/*================================================================================================*/
/*================================================================================================*/
begin
msg_debug("adder_core_s : OUTPUT_HIGH: " & image(OUTPUT_HIGH));
msg_debug("adder_core_s : OUTPUT_LOW: " & image(OUTPUT_LOW));
msg_debug("adder_core_s : DATA_HIGH: " & image(DATA_HIGH));
msg_debug("adder_core_s : DATA_LOW: " & image(DATA_LOW));
msg_debug("adder_core_s : MAX_POSSIBLE_BIT_opt: " & image(MAX_POSSIBLE_BIT_opt));
msg_debug("adder_core_s : MAX_POSSIBLE_BIT: " & image(MAX_POSSIBLE_BIT));
/* Introduction of the input to the ADD structure, and extraction of the signal inter from it */
/**************************************************************************************************/
generate_input_resolved_signal:
for i in 1 to P generate
begin
input_resolved(i) <= input(i);
end;
end generate;
T_ADD_state_write(ADD_in, 0, input_resolved);
inter <= T_ADD_state_read(ADD_out, ADD_LEVELS-1, 1);
/* Generation and management of the control signals */
/**************************************************************************************************/
generate_start_control:
if ADD_PIPELINES>0 generate
begin
start_delayed <= start_sh(ADD_PIPELINES);
process (clk) is
begin
if rising_edge(clk) then
start_sh(1) <= start;
if ADD_PIPELINES>1 then
start_sh(2 to ADD_PIPELINES) <= start_sh(1 to ADD_PIPELINES-1);
end if;
end if;
end process;
end;
else generate
begin
start_delayed <= start;
end;
end generate;
generate_valid_input_control:
if DATA_IMM_AFTER_START=false generate
begin
when_ADD_PIPELINES_is_0:
if ADD_PIPELINES=0 generate
begin
valid_input_delayed<= valid_input;
end;
else generate
begin
valid_input_delayed <= valid_input_sh(ADD_PIPELINES);
process (clk) is
begin
if rising_edge(clk) then
valid_input_sh(1) <= valid_input;
if ADD_PIPELINES>1 then
valid_input_sh(2 to ADD_PIPELINES) <= valid_input_sh(1 to ADD_PIPELINES-1);
end if;
end if;
end process;
end;
end generate;
end;
end generate;
when_ACC_PIPELINES_greater_than_0:
if S>1 generate
begin
generate_counter:
if DATA_IMM_AFTER_START generate
signal aux : std_ulogic;
signal count : std_ulogic_vector(counter_CW(true, --UNSIGNED_2COMP_opt,
0, --COUNTER_WIDTH_dep,
true, --TARGET_MODE,
ACC_PIPELINES, --TARGET_dep,
true, --TARGET_WITH_COUNT_opt = t_true,
true, --USE_SET,
1) --SET_TO_dep)
downto 1);
begin
aux <= unsigned(count) ?/= 0;
counter:
entity work.counter
generic map(
UNSIGNED_2COMP_opt => true,
OVERFLOW_BEHAVIOR_opt => t_wrap,
--COUNT_MODE_opt => t_up,
--COUNTER_WIDTH_dep => ,
TARGET_MODE => true,
TARGET_dep => ACC_PIPELINES,
TARGET_WITH_COUNT_opt => t_true,
TARGET_BLOCKING_opt => t_false,
USE_SET => true,
SET_TO_dep => 1,
USE_RESET => true,
SET_RESET_PRIORITY_opt => t_set,
USE_LOAD => false
)
port map(
clk => clk,
enable => aux,
set => start_delayed,
reset => counter_out,
--load => ,
--count_mode_signal => ,
--value_to_load => ,
count => count,
count_is_TARGET(1) => counter_out
);
end;
else generate
signal count : std_ulogic_vector(counter_CW(true, --UNSIGNED_2COMP_opt,
0, --COUNTER_WIDTH_dep,
true, --TARGET_MODE,
ACC_PIPELINES, --TARGET_dep,
false, --TARGET_WITH_COUNT_opt = t_true,
true, --USE_SET,
1) --SET_TO_dep)
downto 1);
begin
counter:
entity work.counter
generic map(
UNSIGNED_2COMP_opt => true,
OVERFLOW_BEHAVIOR_opt => t_saturate,
--COUNT_MODE_opt => t_up,
--COUNTER_WIDTH_dep => ,
TARGET_MODE => true,
TARGET_dep => ACC_PIPELINES,
TARGET_WITH_COUNT_opt => t_false,
TARGET_BLOCKING_opt => t_true,
USE_SET => true,
SET_TO_dep => 1,
USE_RESET => true,
SET_RESET_PRIORITY_opt => t_set,
USE_LOAD => false
)
port map(
clk => clk,
enable => valid_input_delayed,
set => start_delayed,
reset => counter_out and valid_input_delayed,
--load => ,
--count_mode_signal => ,
--value_to_load => ,
count => count, --not used
count_is_TARGET(1) => counter_out
);
end;
end generate;
end;
elsif DATA_IMM_AFTER_START generate
begin
counter_out <= start_delayed;
end;
else generate
begin
counter_out <= valid_input_delayed;
end;
end generate;
generate_valid_output:
if OUTPUT_BUFFER generate
begin
process (clk) is
begin
if rising_edge(clk) then
if DATA_IMM_AFTER_START then
valid_output <= counter_out;
else
valid_output <= counter_out and valid_input_delayed;
end if;
end if;
end process;
end;
elsif DATA_IMM_AFTER_START generate
begin
valid_output <= counter_out;
end;
else generate
begin
valid_output <= counter_out and valid_input_delayed;
end;
end generate;
/* Generation of the adder tree */
/**************************************************************************************************/
generate_ADD_PIPELINES:
for level in 0 to ADD_LEVELS-1 generate
begin
except_in_first_level:
if level > 0 generate
begin
when_more_than_two_signals:
if signals_per_level(P, level-1) > 1 generate
begin
add_pairs:
for i in 1 to integer(floor(real(signals_per_level(P, level-1))/2.0)) generate
begin
T_ADD_state_write(ADD_in,
level,
i,
resize(T_ADD_state_read(ADD_out,
level-1,
2*i-1)
+
T_ADD_state_read(ADD_out,
level-1,
2*i),
minimum(DATA_HIGH+level,
MAX_POSSIBLE_BIT),
DATA_LOW));
end;
end generate;
end;
end generate;
transport_last_signal_when_odd_number_of_signals:
if (signals_per_level(P, level-1) mod 2)=1 generate
begin
T_ADD_state_write(ADD_in,
level,
signals_per_level(P, level),
resize(T_ADD_state_read(ADD_out,
level-1,
signals_per_level(P, level-1)),
minimum(DATA_HIGH+level,
MAX_POSSIBLE_BIT),
DATA_LOW));
end;
end generate;
end;
end generate;
generate_pipelines_or_connect_cables:
if IS_PIPELINED(level+1) generate
begin
process (clk) is
begin
if rising_edge(clk) then
T_ADD_state_copy(from_state=>ADD_in, to_state=>ADD_out, level=>level);
end if;
end process;
end;
else generate
begin
T_ADD_state_copy(from_state=>ADD_in, to_state=>ADD_out, level=>level);
end;
end generate;
end;
end generate;
/* Generation of the accumulator */
/**************************************************************************************************/
generate_accumulator:
if S>1 generate
signal previous_output_inter : u_ufixed(output_inter'range);
signal inter_resized : u_ufixed(output_inter'range);
signal addition : u_ufixed(output_inter'range);
signal selector : std_ulogic;
begin
inter_resized <= resize(inter, output_inter);
addition <= resize(previous_output_inter + inter_resized, addition);
output_inter <= addition when selector='0' else
inter_resized when selector='1' else
(others => 'X');
selector <= start_delayed;
process (clk) is
begin
if rising_edge(clk) then
if DATA_IMM_AFTER_START=false then
if valid_input_delayed = '1' then
previous_output_inter <= output_inter;
end if;
else
previous_output_inter <= output_inter;
end if;
end if;
end process;
end;
else generate
begin
output_inter <= inter;
end;
end generate;
/* Generation of the output pipeline */
/**************************************************************************************************/
generate_output_pipeline:
if OUTPUT_BUFFER generate
begin
process (clk)
begin
if rising_edge(clk) then
if OUTPUT_LOW<DATA_LOW then
output <= resize(output_inter, OUTPUT_HIGH, OUTPUT_LOW);
else
output <= (OUTPUT_HIGH downto OUTPUT_LOW =>
output_inter(OUTPUT_HIGH downto OUTPUT_LOW));
end if;
end if;
end process;
end;
else generate
begin
generate_no_output_pipeline:
if OUTPUT_LOW<DATA_LOW generate
begin
output <= resize(output_inter, OUTPUT_HIGH, OUTPUT_LOW);
end;
else generate
begin
output <= (OUTPUT_HIGH downto OUTPUT_LOW =>
output_inter(OUTPUT_HIGH downto OUTPUT_LOW));
end;
end generate;
end;
end generate;
end architecture;
| mit | e970a3819886d31cece75d359df169cb | 0.403959 | 4.887272 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/host/plasma v3.0/mlite_pack.vhd | 1 | 19,674 | ---------------------------------------------------------------------
-- TITLE: Plasma Misc. Package
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_pack.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Data types, constants, and add functions needed for the Plasma CPU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package mlite_pack is
constant ZERO : std_logic_vector(31 downto 0) :=
"00000000000000000000000000000000";
constant ONES : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
--make HIGH_Z equal to ZERO if compiler complains
constant HIGH_Z : std_logic_vector(31 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
subtype alu_function_type is std_logic_vector(3 downto 0);
constant ALU_NOTHING : alu_function_type := "0000";
constant ALU_ADD : alu_function_type := "0001";
constant ALU_SUBTRACT : alu_function_type := "0010";
constant ALU_LESS_THAN : alu_function_type := "0011";
constant ALU_LESS_THAN_SIGNED : alu_function_type := "0100";
constant ALU_OR : alu_function_type := "0101";
constant ALU_AND : alu_function_type := "0110";
constant ALU_XOR : alu_function_type := "0111";
constant ALU_NOR : alu_function_type := "1000";
subtype shift_function_type is std_logic_vector(1 downto 0);
constant SHIFT_NOTHING : shift_function_type := "00";
constant SHIFT_LEFT_UNSIGNED : shift_function_type := "01";
constant SHIFT_RIGHT_SIGNED : shift_function_type := "11";
constant SHIFT_RIGHT_UNSIGNED : shift_function_type := "10";
subtype mult_function_type is std_logic_vector(3 downto 0);
constant MULT_NOTHING : mult_function_type := "0000";
constant MULT_READ_LO : mult_function_type := "0001";
constant MULT_READ_HI : mult_function_type := "0010";
constant MULT_WRITE_LO : mult_function_type := "0011";
constant MULT_WRITE_HI : mult_function_type := "0100";
constant MULT_MULT : mult_function_type := "0101";
constant MULT_SIGNED_MULT : mult_function_type := "0110";
constant MULT_DIVIDE : mult_function_type := "0111";
constant MULT_SIGNED_DIVIDE : mult_function_type := "1000";
subtype a_source_type is std_logic_vector(1 downto 0);
constant A_FROM_REG_SOURCE : a_source_type := "00";
constant A_FROM_IMM10_6 : a_source_type := "01";
constant A_FROM_PC : a_source_type := "10";
subtype b_source_type is std_logic_vector(1 downto 0);
constant B_FROM_REG_TARGET : b_source_type := "00";
constant B_FROM_IMM : b_source_type := "01";
constant B_FROM_SIGNED_IMM : b_source_type := "10";
constant B_FROM_IMMX4 : b_source_type := "11";
subtype c_source_type is std_logic_vector(2 downto 0);
constant C_FROM_NULL : c_source_type := "000";
constant C_FROM_ALU : c_source_type := "001";
constant C_FROM_SHIFT : c_source_type := "001"; --same as alu
constant C_FROM_MULT : c_source_type := "001"; --same as alu
constant C_FROM_MEMORY : c_source_type := "010";
constant C_FROM_PC : c_source_type := "011";
constant C_FROM_PC_PLUS4 : c_source_type := "100";
constant C_FROM_IMM_SHIFT16: c_source_type := "101";
constant C_FROM_REG_SOURCEN: c_source_type := "110";
subtype pc_source_type is std_logic_vector(1 downto 0);
constant FROM_INC4 : pc_source_type := "00";
constant FROM_OPCODE25_0 : pc_source_type := "01";
constant FROM_BRANCH : pc_source_type := "10";
constant FROM_LBRANCH : pc_source_type := "11";
subtype branch_function_type is std_logic_vector(2 downto 0);
constant BRANCH_LTZ : branch_function_type := "000";
constant BRANCH_LEZ : branch_function_type := "001";
constant BRANCH_EQ : branch_function_type := "010";
constant BRANCH_NE : branch_function_type := "011";
constant BRANCH_GEZ : branch_function_type := "100";
constant BRANCH_GTZ : branch_function_type := "101";
constant BRANCH_YES : branch_function_type := "110";
constant BRANCH_NO : branch_function_type := "111";
-- mode(32=1,16=2,8=3), signed, write
subtype mem_source_type is std_logic_vector(3 downto 0);
constant MEM_FETCH : mem_source_type := "0000";
constant MEM_READ32 : mem_source_type := "0100";
constant MEM_WRITE32 : mem_source_type := "0101";
constant MEM_READ16 : mem_source_type := "1000";
constant MEM_READ16S : mem_source_type := "1010";
constant MEM_WRITE16 : mem_source_type := "1001";
constant MEM_READ8 : mem_source_type := "1100";
constant MEM_READ8S : mem_source_type := "1110";
constant MEM_WRITE8 : mem_source_type := "1101";
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector;
function bv_negate(a : in std_logic_vector) return std_logic_vector;
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector;
function bv_inc(a : in std_logic_vector
) return std_logic_vector;
-- For Altera
COMPONENT lpm_add_sub
GENERIC (
lpm_width : NATURAL;
lpm_direction : STRING := "UNUSED";
lpm_type : STRING;
lpm_hint : STRING);
PORT (
dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
add_sub : IN STD_LOGIC ;
datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0));
END COMPONENT;
-- For Altera
COMPONENT lpm_ram_dp
GENERIC (
lpm_width : NATURAL;
lpm_widthad : NATURAL;
rden_used : STRING;
intended_device_family : STRING;
lpm_indata : STRING;
lpm_wraddress_control : STRING;
lpm_rdaddress_control : STRING;
lpm_outdata : STRING;
use_eab : STRING;
lpm_type : STRING);
PORT (
wren : IN STD_LOGIC ;
wrclock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (lpm_widthad-1 DOWNTO 0);
wraddress : IN STD_LOGIC_VECTOR (lpm_widthad-1 DOWNTO 0));
END COMPONENT;
-- For Altera
component LPM_RAM_DQ
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL: string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DQ";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
LPM_HINT : string := "UNUSED");
port (
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
INCLOCK : in std_logic := '0';
OUTCLOCK : in std_logic := '0';
WE : in std_logic;
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
-- For Xilinx
component ramb4_s16_s16
port (
clka : in std_logic;
rsta : in std_logic;
addra : in std_logic_vector;
dia : in std_logic_vector;
ena : in std_logic;
wea : in std_logic;
doa : out std_logic_vector;
clkb : in std_logic;
rstb : in std_logic;
addrb : in std_logic_vector;
dib : in std_logic_vector;
enb : in std_logic;
web : in std_logic);
end component;
-- For Xilinx
component reg_file_dp_ram
port (
addra : IN std_logic_VECTOR(4 downto 0);
addrb : IN std_logic_VECTOR(4 downto 0);
clka : IN std_logic;
clkb : IN std_logic;
dinb : IN std_logic_VECTOR(31 downto 0);
douta : OUT std_logic_VECTOR(31 downto 0);
web : IN std_logic);
end component;
-- For Xilinx
component reg_file_dp_ram_xc4000xla
port (
A : IN std_logic_vector(4 DOWNTO 0);
DI : IN std_logic_vector(31 DOWNTO 0);
WR_EN : IN std_logic;
WR_CLK : IN std_logic;
DPRA : IN std_logic_vector(4 DOWNTO 0);
SPO : OUT std_logic_vector(31 DOWNTO 0);
DPO : OUT std_logic_vector(31 DOWNTO 0));
end component;
component pc_next
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end component;
component mem_ctrl
port(clk : in std_logic;
reset_in : in std_logic;
pause_in : in std_logic;
nullify_op : in std_logic;
address_pc : in std_logic_vector(31 downto 2);
opcode_out : out std_logic_vector(31 downto 0);
address_in : in std_logic_vector(31 downto 0);
mem_source : in mem_source_type;
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
pause_out : out std_logic;
mem_address : out std_logic_vector(31 downto 2);
mem_data_w : out std_logic_vector(31 downto 0);
mem_data_r : in std_logic_vector(31 downto 0);
mem_byte_we : out std_logic_vector(3 downto 0));
end component;
component control
port(opcode : in std_logic_vector(31 downto 0);
intr_signal : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type);
end component;
component reg_bank
generic(memory_type : string := "XILINX_16X");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end component;
component bus_mux
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end component;
component alu
generic(alu_type : string := "DEFAULT");
port(a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
alu_function : in alu_function_type;
c_alu : out std_logic_vector(31 downto 0));
end component;
component shifter
generic(shifter_type : string := "DEFAULT" );
port(value : in std_logic_vector(31 downto 0);
shift_amount : in std_logic_vector(4 downto 0);
shift_func : in shift_function_type;
c_shift : out std_logic_vector(31 downto 0));
end component;
component mult
generic(mult_type : string := "DEFAULT");
port(clk : in std_logic;
reset_in : in std_logic;
a, b : in std_logic_vector(31 downto 0);
mult_func : in mult_function_type;
c_mult : out std_logic_vector(31 downto 0);
pause_out : out std_logic);
end component;
component pipeline
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end component;
component mlite_cpu
generic(memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_
mult_type : string := "DEFAULT";
shifter_type : string := "DEFAULT";
alu_type : string := "DEFAULT";
pipeline_stages : natural := 3); --3 or 4
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
mem_address : out std_logic_vector(31 downto 0);
mem_data_w : out std_logic_vector(31 downto 0);
mem_data_r : in std_logic_vector(31 downto 0);
mem_byte_we : out std_logic_vector(3 downto 0);
mem_pause : in std_logic);
end component;
component ram
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end component; --ram
component uart
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic);
end component; --uart
component plasma
generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
write_byte_enable : out std_logic_vector(3 downto 0);
mem_pause_in : in std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0));
end component; --plasma
end; --package mlite_pack
package body mlite_pack is
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector is
variable carry_in : std_logic;
variable bb : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length downto 0);
begin
if do_add = '1' then
bb := b;
carry_in := '0';
else
bb := not b;
carry_in := '1';
end if;
for index in 0 to a'length-1 loop
result(index) := a(index) xor bb(index) xor carry_in;
carry_in := (carry_in and (a(index) or bb(index))) or
(a(index) and bb(index));
end loop;
result(a'length) := carry_in xnor do_add;
return result;
end; --function
function bv_negate(a : in std_logic_vector) return std_logic_vector is
variable carry_in : std_logic;
variable not_a : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length-1 downto 0);
begin
not_a := not a;
carry_in := '1';
for index in a'reverse_range loop
result(index) := not_a(index) xor carry_in;
carry_in := carry_in and not_a(index);
end loop;
return result;
end; --function
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(31 downto 2);
begin
carry_in := '1';
for index in 2 to 31 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
function bv_inc(a : in std_logic_vector
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(a'length-1 downto 0);
begin
carry_in := '1';
for index in 0 to a'length-1 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
end; --package body
| gpl-3.0 | ee8d3aeff1eb71a623c4da5454282660 | 0.555352 | 3.596052 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_03600_bad.vhd | 1 | 3,322 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1.1
-- Version history :
-- V1 : 2015-04-07 : Mickael Carl (CNES): Creation
-- V1.1 : 2016-05-03 : F.Manni (CNES) : add initialization for D_re
-------------------------------------------------------------------------------------------------
-- File name : STD_03600_bad.vhd
-- File Creation date : 2015-04-07
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Reset sensitive level: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_03600_bad is
port (
i_Reset_n : in std_logic; -- Reset signal
i_Clock : in std_logic; -- Clock signal
i_D : in std_logic; -- Async signal
o_Q : out std_logic -- Rising edge of i_D
);
end STD_03600_bad;
--CODE
architecture Behavioral of STD_03600_bad is
signal D_r1 : std_logic; -- D signal registered 1 time
signal D_r2 : std_logic; -- D signal registered 2 times
signal D_re : std_logic; -- Module output
signal Reset : std_logic; -- Reset signal (active high)
begin
P_First_Register : process(i_Reset_n, i_Clock)
begin
if (i_Reset_n = '0') then
D_r1 <= '0';
elsif (rising_edge(i_Clock)) then
D_r1 <= i_D;
end if;
end process;
Reset <= not i_Reset_n;
P_Second_Register : process(Reset, i_Clock)
begin
if (Reset = '1') then
D_r2 <= '0';
D_re <= '0';
elsif (rising_edge(i_Clock)) then
D_r2 <= D_r1;
D_re <= D_r1 and not D_r2;
end if;
end process;
o_Q <= D_re;
end Behavioral;
--CODE
| gpl-3.0 | 9ba7511759b70a72a550e299281a0d90 | 0.477423 | 4.16813 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/cache/cache.vhd | 1 | 1,149 | library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity cache is
port
(
CLK : in std_logic;
AI : in std_logic_vector(5 downto 0);
DI : in std_logic_vector(7 downto 0);
WE : in std_logic := '1';
AO : in std_logic_vector(5 downto 0);
DO : out std_logic_vector(7 downto 0);
CACHE : in std_logic
);
end cache;
architecture rtl of cache is
signal CACHE_ACTIVE : std_logic := '0';
subtype word_t is std_logic_vector(7 downto 0);
type memory_t is array(0 to 127) of word_t;
shared variable ram : memory_t;
begin
process(CLK)
begin
if rising_edge(CLK) then
if CACHE = '1' then
CACHE_ACTIVE <= not CACHE_ACTIVE;
end if;
end if;
end process;
process(CLK)
begin
if rising_edge(CLK) then
if WE = '0' then
ram(to_integer(unsigned(CACHE_ACTIVE & AI))) := DI;
end if;
end if;
end process;
process(CLK)
begin
if rising_edge(CLK) then
DO <= ram(to_integer(unsigned(not CACHE_ACTIVE & AO)));
end if;
end process;
end rtl;
| gpl-3.0 | 2c47422786fb0b91ae7ec82164b5f1f8 | 0.56745 | 3.369501 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/host/VGA Console/mips_vram/mips_vram/simulation/mips_vram_synth.vhd | 1 | 10,378 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: mips_vram_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY mips_vram_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE mips_vram_synth_ARCH OF mips_vram_synth IS
COMPONENT mips_vram_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL WEB: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEB_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB: STD_LOGIC_VECTOR( 15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB_R: STD_LOGIC_VECTOR( 15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL CHECK_DATA_TDP : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECKER_ENB_R : STD_LOGIC := '0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST_A: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 16,
READ_WIDTH => 16 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECK_DATA_TDP(0) AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_DATA_CHECKER_INST_B: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 16,
READ_WIDTH => 16 )
PORT MAP (
CLK => CLKB,
RST => RSTB,
EN => CHECKER_ENB_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(1)
);
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(RSTB='1') THEN
CHECKER_ENB_R <= '0';
ELSE
CHECKER_ENB_R <= CHECK_DATA_TDP(1) AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => CLKA,
CLKB => CLKB,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
CHECK_DATA => CHECK_DATA_TDP
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
WEB_R <= (OTHERS=>'0') AFTER 50 ns;
DINB_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
WEB_R <= WEB AFTER 50 ns;
DINB_R <= DINB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: mips_vram_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
WEB => WEB_R,
ADDRB => ADDRB_R,
DINB => DINB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
| gpl-3.0 | 38def04f6b2a6c594ff7c18e6d0b34f3 | 0.555791 | 3.602221 | false | false | false | false |
APastorG/APG | real_const_mult/real_const_mult_s.vhd | 1 | 3,952 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Xilinx's Vivado
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is the interface between the instantiation of a real_const_mult an its content. It exists
/ to circumvent the impossibility of reading the attributes of an unconstrained port signal inside
/ the port declaration of an entity. (so as to declare the output's size, which depends on the
/ input's size).
/ Additionally, the generics' consistency and correctness is checked in here.
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.common_pkg.all;
use work.common_data_types_pkg.all;
use work.fixed_generic_pkg.all;
use work.fixed_float_types.all;
use work.real_const_mult_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity real_const_mult_s is
generic(
SPEED_opt : T_speed := t_exc; --exception: value not set
ROUND_STYLE_opt : T_round_style := fixed_truncate; --default
ROUND_TO_BIT_opt : integer_exc := integer'low; --exception: value not set
MAX_ERROR_PCT_opt : real_exc := real'low; --exception: value not set
MULTIPLICANDS : real_v --compulsory
);
port(
input : in u_sfixed;
clk : in std_ulogic;
valid_input : in std_ulogic;
output : out u_sfixed_v;
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture real_const_mult_s_1 of real_const_mult_s is
constant CHECKS : integer := real_const_mult_CHECKS(input'high,
input'low,
false, --UNSIGNED_2COMP_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
MULTIPLICANDS);
constant MULTIPLICANDS_adjusted : real_v(1 to MULTIPLICANDS'length) := MULTIPLICANDS;
/*================================================================================================*/
/*================================================================================================*/
begin
real_const_mult_core_s_1:
entity work.real_const_mult_core_s
generic map(
SPEED_opt => SPEED_opt,
ROUND_STYLE_opt => ROUND_STYLE_opt,
ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
CONSTANTS => MULTIPLICANDS_adjusted,
input_high => input'high,
input_low => input'low
)
port map(
input => input,
clk => clk,
valid_input => valid_input,
output => output,
valid_output => valid_output
);
end architecture; | mit | 6f3c82158cad071b942275403260008b | 0.402501 | 4.760632 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_03200_bad.vhd | 1 | 2,762 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-03 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_03200_bad.vhd
-- File Creation date : 2015-04-03
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Unused output ports components management: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pkg_HBK.all;
entity STD_03200_bad is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end STD_03200_bad;
--CODE
architecture Behavioral of STD_03200_bad is
signal Q_n : std_logic;
begin
FlipFlop : DFlipFlop
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_D => i_D,
o_Q => o_Q,
o_Q_n => Q_n
);
end Behavioral;
--CODE
| gpl-3.0 | 895318ff7240fecee744c8ad956be581 | 0.467777 | 4.527869 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/a8core/cpu_65xx_a.vhd | 1 | 58,958 | -- -----------------------------------------------------------------------
--
-- FPGA 64
--
-- A fully functional commodore 64 implementation in a single FPGA
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2011 by Peter Wendrich ([email protected])
-- All Rights Reserved.
--
-- http://www.syntiac.com/fpga64.html
-- -----------------------------------------------------------------------
--
-- Table driven, cycle exact 6502/6510 core
--
-- -----------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.ALL;
-- -----------------------------------------------------------------------
-- Store Zp (3) => fetch, cycle2, cycleEnd
-- Store Zp,x (4) => fetch, cycle2, preWrite, cycleEnd
-- Read Zp,x (4) => fetch, cycle2, cycleRead, cycleRead2
-- Rmw Zp,x (6) => fetch, cycle2, cycleRead, cycleRead2, cycleRmw, cycleEnd
-- Store Abs (4) => fetch, cycle2, cycle3, cycleEnd
-- Store Abs,x (5) => fetch, cycle2, cycle3, preWrite, cycleEnd
-- Rts (6) => fetch, cycle2, cycle3, cycleRead, cycleJump, cycleIncrEnd
-- Rti (6) => fetch, cycle2, stack1, stack2, stack3, cycleJump
-- Jsr (6) => fetch, cycle2, .. cycle5, cycle6, cycleJump
-- Jmp abs (-) => fetch, cycle2, .., cycleJump
-- Jmp (ind) (-) => fetch, cycle2, .., cycleJump
-- Brk / irq (6) => fetch, cycle2, stack2, stack3, stack4
-- -----------------------------------------------------------------------
architecture rtl of cpu_65xx is
-- Statemachine
type cpuCycles is (
opcodeFetch, -- New opcode is read and registers updated
cycle2,
cycle3,
cyclePreIndirect,
cycleIndirect,
cycleBranchTaken,
cycleBranchPage,
cyclePreRead, -- Cycle before read while doing zeropage indexed addressing.
cycleRead, -- Read cycle
cycleRead2, -- Second read cycle after page-boundary crossing.
cycleRmw, -- Calculate ALU output for read-modify-write instr.
cyclePreWrite, -- Cycle before write when doing indexed addressing.
cycleWrite, -- Write cycle for zeropage or absolute addressing.
cycleStack1,
cycleStack2,
cycleStack3,
cycleStack4,
cycleJump, -- Last cycle of Jsr, Jmp. Next fetch address is target addr.
cycleEnd
);
signal theCpuCycle : cpuCycles;
signal nextCpuCycle : cpuCycles;
signal updateRegisters : boolean;
signal processNmi : std_logic := '0';
signal processIrq : std_logic := '0';
signal processInt : std_logic := '0';
signal nmiReg: std_logic;
signal nmiEdge: std_logic;
signal irqReg : std_logic; -- Delay IRQ input with one clock cycle.
signal so_reg : std_logic; -- SO pin edge detection
-- Opcode decoding
constant opcUpdateA : integer := 0;
constant opcUpdateX : integer := 1;
constant opcUpdateY : integer := 2;
constant opcUpdateS : integer := 3;
constant opcUpdateN : integer := 4;
constant opcUpdateV : integer := 5;
constant opcUpdateD : integer := 6;
constant opcUpdateI : integer := 7;
constant opcUpdateZ : integer := 8;
constant opcUpdateC : integer := 9;
constant opcSecondByte : integer := 10;
constant opcAbsolute : integer := 11;
constant opcZeroPage : integer := 12;
constant opcIndirect : integer := 13;
constant opcStackAddr : integer := 14; -- Push/Pop address
constant opcStackData : integer := 15; -- Push/Pop status/data
constant opcJump : integer := 16;
constant opcBranch : integer := 17;
constant indexX : integer := 18;
constant indexY : integer := 19;
constant opcStackUp : integer := 20;
constant opcWrite : integer := 21;
constant opcRmw : integer := 22;
constant opcIncrAfter : integer := 23; -- Insert extra cycle to increment PC (RTS)
constant opcRti : integer := 24;
constant opcIRQ : integer := 25;
constant opcInA : integer := 26;
constant opcInE : integer := 27;
constant opcInX : integer := 28;
constant opcInY : integer := 29;
constant opcInS : integer := 30;
constant opcInT : integer := 31;
constant opcInH : integer := 32;
constant opcInClear : integer := 33;
constant aluMode1From : integer := 34;
--
constant aluMode1To : integer := 37;
constant aluMode2From : integer := 38;
--
constant aluMode2To : integer := 40;
--
constant opcInCmp : integer := 41;
constant opcInCpx : integer := 42;
constant opcInCpy : integer := 43;
subtype addrDef is unsigned(0 to 15);
--
-- is Interrupt -----------------+
-- instruction is RTI ----------------+|
-- PC++ on last cycle (RTS) ---------------+||
-- RMW --------------+|||
-- Write -------------+||||
-- Pop/Stack up -------------+|||||
-- Branch ---------+ ||||||
-- Jump ----------+| ||||||
-- Push or Pop data -------+|| ||||||
-- Push or Pop addr ------+||| ||||||
-- Indirect -----+|||| ||||||
-- ZeroPage ----+||||| ||||||
-- Absolute ---+|||||| ||||||
-- PC++ on cycle2 --+||||||| ||||||
-- |AZI||JBXY|WM|||
constant immediate : addrDef := "1000000000000000";
constant implied : addrDef := "0000000000000000";
-- Zero page
constant readZp : addrDef := "1010000000000000";
constant writeZp : addrDef := "1010000000010000";
constant rmwZp : addrDef := "1010000000001000";
-- Zero page indexed
constant readZpX : addrDef := "1010000010000000";
constant writeZpX : addrDef := "1010000010010000";
constant rmwZpX : addrDef := "1010000010001000";
constant readZpY : addrDef := "1010000001000000";
constant writeZpY : addrDef := "1010000001010000";
constant rmwZpY : addrDef := "1010000001001000";
-- Zero page indirect
constant readIndX : addrDef := "1001000010000000";
constant writeIndX : addrDef := "1001000010010000";
constant rmwIndX : addrDef := "1001000010001000";
constant readIndY : addrDef := "1001000001000000";
constant writeIndY : addrDef := "1001000001010000";
constant rmwIndY : addrDef := "1001000001001000";
-- |AZI||JBXY|WM||
-- Absolute
constant readAbs : addrDef := "1100000000000000";
constant writeAbs : addrDef := "1100000000010000";
constant rmwAbs : addrDef := "1100000000001000";
constant readAbsX : addrDef := "1100000010000000";
constant writeAbsX : addrDef := "1100000010010000";
constant rmwAbsX : addrDef := "1100000010001000";
constant readAbsY : addrDef := "1100000001000000";
constant writeAbsY : addrDef := "1100000001010000";
constant rmwAbsY : addrDef := "1100000001001000";
-- PHA PHP
constant push : addrDef := "0000010000000000";
-- PLA PLP
constant pop : addrDef := "0000010000100000";
-- Jumps
constant jsr : addrDef := "1000101000000000";
constant jumpAbs : addrDef := "1000001000000000";
constant jumpInd : addrDef := "1100001000000000";
constant relative : addrDef := "1000000100000000";
-- Specials
constant rts : addrDef := "0000101000100100";
constant rti : addrDef := "0000111000100010";
constant brk : addrDef := "1000111000000001";
-- constant : unsigned(0 to 0) := "0";
constant xxxxxxxx : addrDef := "----------0---00";
-- A = accu
-- E = Accu | 0xEE (for ANE, LXA)
-- X = index X
-- Y = index Y
-- S = Stack pointer
-- H = indexH
--
-- AEXYSTHc
constant aluInA : unsigned(0 to 7) := "10000000";
constant aluInE : unsigned(0 to 7) := "01000000";
constant aluInEXT : unsigned(0 to 7) := "01100100";
constant aluInET : unsigned(0 to 7) := "01000100";
constant aluInX : unsigned(0 to 7) := "00100000";
constant aluInXH : unsigned(0 to 7) := "00100010";
constant aluInY : unsigned(0 to 7) := "00010000";
constant aluInYH : unsigned(0 to 7) := "00010010";
constant aluInS : unsigned(0 to 7) := "00001000";
constant aluInT : unsigned(0 to 7) := "00000100";
constant aluInAX : unsigned(0 to 7) := "10100000";
constant aluInAXH : unsigned(0 to 7) := "10100010";
constant aluInAT : unsigned(0 to 7) := "10000100";
constant aluInXT : unsigned(0 to 7) := "00100100";
constant aluInST : unsigned(0 to 7) := "00001100";
constant aluInSet : unsigned(0 to 7) := "00000000";
constant aluInClr : unsigned(0 to 7) := "00000001";
constant aluInXXX : unsigned(0 to 7) := "--------";
-- Most of the aluModes are just like the opcodes.
-- aluModeInp -> input is output. calculate N and Z
-- aluModeCmp -> Compare for CMP, CPX, CPY
-- aluModeFlg -> input to flags needed for PLP, RTI and CLC, SEC, CLV
-- aluModeInc -> for INC but also INX, INY
-- aluModeDec -> for DEC but also DEX, DEY
subtype aluMode1 is unsigned(0 to 3);
subtype aluMode2 is unsigned(0 to 2);
subtype aluMode is unsigned(0 to 9);
-- Logic/Shift ALU
constant aluModeInp : aluMode1 := "0000";
constant aluModeP : aluMode1 := "0001";
constant aluModeInc : aluMode1 := "0010";
constant aluModeDec : aluMode1 := "0011";
constant aluModeFlg : aluMode1 := "0100";
constant aluModeBit : aluMode1 := "0101";
-- 0110
-- 0111
constant aluModeLsr : aluMode1 := "1000";
constant aluModeRor : aluMode1 := "1001";
constant aluModeAsl : aluMode1 := "1010";
constant aluModeRol : aluMode1 := "1011";
-- 1100
-- 1101
-- 1110
constant aluModeAnc : aluMode1 := "1111";
-- Arithmetic ALU
constant aluModePss : aluMode2 := "000";
constant aluModeCmp : aluMode2 := "001";
constant aluModeAdc : aluMode2 := "010";
constant aluModeSbc : aluMode2 := "011";
constant aluModeAnd : aluMode2 := "100";
constant aluModeOra : aluMode2 := "101";
constant aluModeEor : aluMode2 := "110";
constant aluModeArr : aluMode2 := "111";
constant aluInp : aluMode := aluModeInp & aluModePss & "---";
constant aluP : aluMode := aluModeP & aluModePss & "---";
constant aluInc : aluMode := aluModeInc & aluModePss & "---";
constant aluDec : aluMode := aluModeDec & aluModePss & "---";
constant aluFlg : aluMode := aluModeFlg & aluModePss & "---";
constant aluBit : aluMode := aluModeBit & aluModeAnd & "---";
constant aluRor : aluMode := aluModeRor & aluModePss & "---";
constant aluLsr : aluMode := aluModeLsr & aluModePss & "---";
constant aluRol : aluMode := aluModeRol & aluModePss & "---";
constant aluAsl : aluMode := aluModeAsl & aluModePss & "---";
constant aluCmp : aluMode := aluModeInp & aluModeCmp & "100";
constant aluCpx : aluMode := aluModeInp & aluModeCmp & "010";
constant aluCpy : aluMode := aluModeInp & aluModeCmp & "001";
constant aluAdc : aluMode := aluModeInp & aluModeAdc & "---";
constant aluSbc : aluMode := aluModeInp & aluModeSbc & "---";
constant aluAnd : aluMode := aluModeInp & aluModeAnd & "---";
constant aluOra : aluMode := aluModeInp & aluModeOra & "---";
constant aluEor : aluMode := aluModeInp & aluModeEor & "---";
constant aluSlo : aluMode := aluModeAsl & aluModeOra & "---";
constant aluSre : aluMode := aluModeLsr & aluModeEor & "---";
constant aluRra : aluMode := aluModeRor & aluModeAdc & "---";
constant aluRla : aluMode := aluModeRol & aluModeAnd & "---";
constant aluDcp : aluMode := aluModeDec & aluModeCmp & "100";
constant aluIsc : aluMode := aluModeInc & aluModeSbc & "---";
constant aluAnc : aluMode := aluModeAnc & aluModeAnd & "---";
constant aluArr : aluMode := aluModeRor & aluModeArr & "---";
constant aluSbx : aluMode := aluModeInp & aluModeCmp & "110";
constant aluXXX : aluMode := (others => '-');
-- Stack operations. Push/Pop/None
constant stackInc : unsigned(0 to 0) := "0";
constant stackDec : unsigned(0 to 0) := "1";
constant stackXXX : unsigned(0 to 0) := "-";
subtype decodedBitsDef is unsigned(0 to 43);
type opcodeInfoTableDef is array(0 to 255) of decodedBitsDef;
constant opcodeInfoTable : opcodeInfoTableDef := (
-- +------- Update register A
-- |+------ Update register X
-- ||+----- Update register Y
-- |||+---- Update register S
-- |||| +-- Update Flags
-- |||| |
-- |||| _|__
-- |||| / \
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000100" & brk & aluInXXX & aluP, -- 00 BRK
"1000" & "100010" & readIndX & aluInT & aluOra, -- 01 ORA (zp,x)
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 02 *** JAM ***
"1000" & "100011" & rmwIndX & aluInT & aluSlo, -- 03 iSLO (zp,x)
"0000" & "000000" & readZp & aluInXXX & aluXXX, -- 04 iNOP zp
"1000" & "100010" & readZp & aluInT & aluOra, -- 05 ORA zp
"0000" & "100011" & rmwZp & aluInT & aluAsl, -- 06 ASL zp
"1000" & "100011" & rmwZp & aluInT & aluSlo, -- 07 iSLO zp
"0000" & "000000" & push & aluInXXX & aluP, -- 08 PHP
"1000" & "100010" & immediate & aluInT & aluOra, -- 09 ORA imm
"1000" & "100011" & implied & aluInA & aluAsl, -- 0A ASL accu
"1000" & "100011" & immediate & aluInT & aluAnc, -- 0B iANC imm
"0000" & "000000" & readAbs & aluInXXX & aluXXX, -- 0C iNOP abs
"1000" & "100010" & readAbs & aluInT & aluOra, -- 0D ORA abs
"0000" & "100011" & rmwAbs & aluInT & aluAsl, -- 0E ASL abs
"1000" & "100011" & rmwAbs & aluInT & aluSlo, -- 0F iSLO abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 10 BPL
"1000" & "100010" & readIndY & aluInT & aluOra, -- 11 ORA (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 12 *** JAM ***
"1000" & "100011" & rmwIndY & aluInT & aluSlo, -- 13 iSLO (zp),y
"0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 14 iNOP zp,x
"1000" & "100010" & readZpX & aluInT & aluOra, -- 15 ORA zp,x
"0000" & "100011" & rmwZpX & aluInT & aluAsl, -- 16 ASL zp,x
"1000" & "100011" & rmwZpX & aluInT & aluSlo, -- 17 iSLO zp,x
"0000" & "000001" & implied & aluInClr & aluFlg, -- 18 CLC
"1000" & "100010" & readAbsY & aluInT & aluOra, -- 19 ORA abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 1A iNOP implied
"1000" & "100011" & rmwAbsY & aluInT & aluSlo, -- 1B iSLO abs,y
"0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 1C iNOP abs,x
"1000" & "100010" & readAbsX & aluInT & aluOra, -- 1D ORA abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluAsl, -- 1E ASL abs,x
"1000" & "100011" & rmwAbsX & aluInT & aluSlo, -- 1F iSLO abs,x
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & jsr & aluInXXX & aluXXX, -- 20 JSR
"1000" & "100010" & readIndX & aluInT & aluAnd, -- 21 AND (zp,x)
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 22 *** JAM ***
"1000" & "100011" & rmwIndX & aluInT & aluRla, -- 23 iRLA (zp,x)
"0000" & "110010" & readZp & aluInT & aluBit, -- 24 BIT zp
"1000" & "100010" & readZp & aluInT & aluAnd, -- 25 AND zp
"0000" & "100011" & rmwZp & aluInT & aluRol, -- 26 ROL zp
"1000" & "100011" & rmwZp & aluInT & aluRla, -- 27 iRLA zp
"0000" & "111111" & pop & aluInT & aluFlg, -- 28 PLP
"1000" & "100010" & immediate & aluInT & aluAnd, -- 29 AND imm
"1000" & "100011" & implied & aluInA & aluRol, -- 2A ROL accu
"1000" & "100011" & immediate & aluInT & aluAnc, -- 2B iANC imm
"0000" & "110010" & readAbs & aluInT & aluBit, -- 2C BIT abs
"1000" & "100010" & readAbs & aluInT & aluAnd, -- 2D AND abs
"0000" & "100011" & rmwAbs & aluInT & aluRol, -- 2E ROL abs
"1000" & "100011" & rmwAbs & aluInT & aluRla, -- 2F iRLA abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 30 BMI
"1000" & "100010" & readIndY & aluInT & aluAnd, -- 31 AND (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 32 *** JAM ***
"1000" & "100011" & rmwIndY & aluInT & aluRla, -- 33 iRLA (zp),y
"0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 34 iNOP zp,x
"1000" & "100010" & readZpX & aluInT & aluAnd, -- 35 AND zp,x
"0000" & "100011" & rmwZpX & aluInT & aluRol, -- 36 ROL zp,x
"1000" & "100011" & rmwZpX & aluInT & aluRla, -- 37 iRLA zp,x
"0000" & "000001" & implied & aluInSet & aluFlg, -- 38 SEC
"1000" & "100010" & readAbsY & aluInT & aluAnd, -- 39 AND abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 3A iNOP implied
"1000" & "100011" & rmwAbsY & aluInT & aluRla, -- 3B iRLA abs,y
"0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 3C iNOP abs,x
"1000" & "100010" & readAbsX & aluInT & aluAnd, -- 3D AND abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluRol, -- 3E ROL abs,x
"1000" & "100011" & rmwAbsX & aluInT & aluRla, -- 3F iRLA abs,x
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "111111" & rti & aluInT & aluFlg, -- 40 RTI
"1000" & "100010" & readIndX & aluInT & aluEor, -- 41 EOR (zp,x)
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 42 *** JAM ***
"1000" & "100011" & rmwIndX & aluInT & aluSre, -- 43 iSRE (zp,x)
"0000" & "000000" & readZp & aluInXXX & aluXXX, -- 44 iNOP zp
"1000" & "100010" & readZp & aluInT & aluEor, -- 45 EOR zp
"0000" & "100011" & rmwZp & aluInT & aluLsr, -- 46 LSR zp
"1000" & "100011" & rmwZp & aluInT & aluSre, -- 47 iSRE zp
"0000" & "000000" & push & aluInA & aluInp, -- 48 PHA
"1000" & "100010" & immediate & aluInT & aluEor, -- 49 EOR imm
"1000" & "100011" & implied & aluInA & aluLsr, -- 4A LSR accu
"1000" & "100011" & immediate & aluInAT & aluLsr, -- 4B iALR imm
"0000" & "000000" & jumpAbs & aluInXXX & aluXXX, -- 4C JMP abs
"1000" & "100010" & readAbs & aluInT & aluEor, -- 4D EOR abs
"0000" & "100011" & rmwAbs & aluInT & aluLsr, -- 4E LSR abs
"1000" & "100011" & rmwAbs & aluInT & aluSre, -- 4F iSRE abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 50 BVC
"1000" & "100010" & readIndY & aluInT & aluEor, -- 51 EOR (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 52 *** JAM ***
"1000" & "100011" & rmwIndY & aluInT & aluSre, -- 53 iSRE (zp),y
"0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 54 iNOP zp,x
"1000" & "100010" & readZpX & aluInT & aluEor, -- 55 EOR zp,x
"0000" & "100011" & rmwZpX & aluInT & aluLsr, -- 56 LSR zp,x
"1000" & "100011" & rmwZpX & aluInT & aluSre, -- 57 SRE zp,x
"0000" & "000100" & implied & aluInClr & aluXXX, -- 58 CLI
"1000" & "100010" & readAbsY & aluInT & aluEor, -- 59 EOR abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 5A iNOP implied
"1000" & "100011" & rmwAbsY & aluInT & aluSre, -- 5B iSRE abs,y
"0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 5C iNOP abs,x
"1000" & "100010" & readAbsX & aluInT & aluEor, -- 5D EOR abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluLsr, -- 5E LSR abs,x
"1000" & "100011" & rmwAbsX & aluInT & aluSre, -- 5F SRE abs,x
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & rts & aluInXXX & aluXXX, -- 60 RTS
"1000" & "110011" & readIndX & aluInT & aluAdc, -- 61 ADC (zp,x)
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 62 *** JAM ***
"1000" & "110011" & rmwIndX & aluInT & aluRra, -- 63 iRRA (zp,x)
"0000" & "000000" & readZp & aluInXXX & aluXXX, -- 64 iNOP zp
"1000" & "110011" & readZp & aluInT & aluAdc, -- 65 ADC zp
"0000" & "100011" & rmwZp & aluInT & aluRor, -- 66 ROR zp
"1000" & "110011" & rmwZp & aluInT & aluRra, -- 67 iRRA zp
"1000" & "100010" & pop & aluInT & aluInp, -- 68 PLA
"1000" & "110011" & immediate & aluInT & aluAdc, -- 69 ADC imm
"1000" & "100011" & implied & aluInA & aluRor, -- 6A ROR accu
"1000" & "110011" & immediate & aluInAT & aluArr, -- 6B iARR imm
"0000" & "000000" & jumpInd & aluInXXX & aluXXX, -- 6C JMP indirect
"1000" & "110011" & readAbs & aluInT & aluAdc, -- 6D ADC abs
"0000" & "100011" & rmwAbs & aluInT & aluRor, -- 6E ROR abs
"1000" & "110011" & rmwAbs & aluInT & aluRra, -- 6F iRRA abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 70 BVS
"1000" & "110011" & readIndY & aluInT & aluAdc, -- 71 ADC (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 72 *** JAM ***
"1000" & "110011" & rmwIndY & aluInT & aluRra, -- 73 iRRA (zp),y
"0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 74 iNOP zp,x
"1000" & "110011" & readZpX & aluInT & aluAdc, -- 75 ADC zp,x
"0000" & "100011" & rmwZpX & aluInT & aluRor, -- 76 ROR zp,x
"1000" & "110011" & rmwZpX & aluInT & aluRra, -- 77 iRRA zp,x
"0000" & "000100" & implied & aluInSet & aluXXX, -- 78 SEI
"1000" & "110011" & readAbsY & aluInT & aluAdc, -- 79 ADC abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 7A iNOP implied
"1000" & "110011" & rmwAbsY & aluInT & aluRra, -- 7B iRRA abs,y
"0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 7C iNOP abs,x
"1000" & "110011" & readAbsX & aluInT & aluAdc, -- 7D ADC abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluRor, -- 7E ROR abs,x
"1000" & "110011" & rmwAbsX & aluInT & aluRra, -- 7F iRRA abs,x
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 80 iNOP imm
"0000" & "000000" & writeIndX & aluInA & aluInp, -- 81 STA (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 82 iNOP imm
"0000" & "000000" & writeIndX & aluInAX & aluInp, -- 83 iSAX (zp,x)
"0000" & "000000" & writeZp & aluInY & aluInp, -- 84 STY zp
"0000" & "000000" & writeZp & aluInA & aluInp, -- 85 STA zp
"0000" & "000000" & writeZp & aluInX & aluInp, -- 86 STX zp
"0000" & "000000" & writeZp & aluInAX & aluInp, -- 87 iSAX zp
"0010" & "100010" & implied & aluInY & aluDec, -- 88 DEY
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 84 iNOP imm
"1000" & "100010" & implied & aluInX & aluInp, -- 8A TXA
"1000" & "100010" & immediate & aluInEXT & aluInp, -- 8B iANE imm
"0000" & "000000" & writeAbs & aluInY & aluInp, -- 8C STY abs
"0000" & "000000" & writeAbs & aluInA & aluInp, -- 8D STA abs
"0000" & "000000" & writeAbs & aluInX & aluInp, -- 8E STX abs
"0000" & "000000" & writeAbs & aluInAX & aluInp, -- 8F iSAX abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 90 BCC
"0000" & "000000" & writeIndY & aluInA & aluInp, -- 91 STA (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 92 *** JAM ***
"0000" & "000000" & writeIndY & aluInAXH & aluInp, -- 93 iAHX (zp),y
"0000" & "000000" & writeZpX & aluInY & aluInp, -- 94 STY zp,x
"0000" & "000000" & writeZpX & aluInA & aluInp, -- 95 STA zp,x
"0000" & "000000" & writeZpY & aluInX & aluInp, -- 96 STX zp,y
"0000" & "000000" & writeZpY & aluInAX & aluInp, -- 97 iSAX zp,y
"1000" & "100010" & implied & aluInY & aluInp, -- 98 TYA
"0000" & "000000" & writeAbsY & aluInA & aluInp, -- 99 STA abs,y
"0001" & "000000" & implied & aluInX & aluInp, -- 9A TXS
"0001" & "000000" & writeAbsY & aluInAXH & aluInp, -- 9B iSHS abs,y
"0000" & "000000" & writeAbsX & aluInYH & aluInp, -- 9C iSHY abs,x
"0000" & "000000" & writeAbsX & aluInA & aluInp, -- 9D STA abs,x
"0000" & "000000" & writeAbsY & aluInXH & aluInp, -- 9E iSHX abs,y
"0000" & "000000" & writeAbsY & aluInAX & aluInp, -- 9F iAHX abs,y
-- AXYS NVDIZC addressing aluInput aluMode
"0010" & "100010" & immediate & aluInT & aluInp, -- A0 LDY imm
"1000" & "100010" & readIndX & aluInT & aluInp, -- A1 LDA (zp,x)
"0100" & "100010" & immediate & aluInT & aluInp, -- A2 LDX imm
"1100" & "100010" & readIndX & aluInT & aluInp, -- A3 LAX (zp,x)
"0010" & "100010" & readZp & aluInT & aluInp, -- A4 LDY zp
"1000" & "100010" & readZp & aluInT & aluInp, -- A5 LDA zp
"0100" & "100010" & readZp & aluInT & aluInp, -- A6 LDX zp
"1100" & "100010" & readZp & aluInT & aluInp, -- A7 iLAX zp
"0010" & "100010" & implied & aluInA & aluInp, -- A8 TAY
"1000" & "100010" & immediate & aluInT & aluInp, -- A9 LDA imm
"0100" & "100010" & implied & aluInA & aluInp, -- AA TAX
"1100" & "100010" & immediate & aluInET & aluAnd, -- AB iLXA imm - MWW:change for Atari800 CPU
"0010" & "100010" & readAbs & aluInT & aluInp, -- AC LDY abs
"1000" & "100010" & readAbs & aluInT & aluInp, -- AD LDA abs
"0100" & "100010" & readAbs & aluInT & aluInp, -- AE LDX abs
"1100" & "100010" & readAbs & aluInT & aluInp, -- AF iLAX abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- B0 BCS
"1000" & "100010" & readIndY & aluInT & aluInp, -- B1 LDA (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- B2 *** JAM ***
"1100" & "100010" & readIndY & aluInT & aluInp, -- B3 iLAX (zp),y
"0010" & "100010" & readZpX & aluInT & aluInp, -- B4 LDY zp,x
"1000" & "100010" & readZpX & aluInT & aluInp, -- B5 LDA zp,x
"0100" & "100010" & readZpY & aluInT & aluInp, -- B6 LDX zp,y
"1100" & "100010" & readZpY & aluInT & aluInp, -- B7 iLAX zp,y
"0000" & "010000" & implied & aluInClr & aluFlg, -- B8 CLV
"1000" & "100010" & readAbsY & aluInT & aluInp, -- B9 LDA abs,y
"0100" & "100010" & implied & aluInS & aluInp, -- BA TSX
"1101" & "100010" & readAbsY & aluInST & aluInp, -- BB iLAS abs,y
"0010" & "100010" & readAbsX & aluInT & aluInp, -- BC LDY abs,x
"1000" & "100010" & readAbsX & aluInT & aluInp, -- BD LDA abs,x
"0100" & "100010" & readAbsY & aluInT & aluInp, -- BE LDX abs,y
"1100" & "100010" & readAbsY & aluInT & aluInp, -- BF iLAX abs,y
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "100011" & immediate & aluInT & aluCpy, -- C0 CPY imm
"0000" & "100011" & readIndX & aluInT & aluCmp, -- C1 CMP (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- C2 iNOP imm
"0000" & "100011" & rmwIndX & aluInT & aluDcp, -- C3 iDCP (zp,x)
"0000" & "100011" & readZp & aluInT & aluCpy, -- C4 CPY zp
"0000" & "100011" & readZp & aluInT & aluCmp, -- C5 CMP zp
"0000" & "100010" & rmwZp & aluInT & aluDec, -- C6 DEC zp
"0000" & "100011" & rmwZp & aluInT & aluDcp, -- C7 iDCP zp
"0010" & "100010" & implied & aluInY & aluInc, -- C8 INY
"0000" & "100011" & immediate & aluInT & aluCmp, -- C9 CMP imm
"0100" & "100010" & implied & aluInX & aluDec, -- CA DEX
"0100" & "100011" & immediate & aluInT & aluSbx, -- CB SBX imm
"0000" & "100011" & readAbs & aluInT & aluCpy, -- CC CPY abs
"0000" & "100011" & readAbs & aluInT & aluCmp, -- CD CMP abs
"0000" & "100010" & rmwAbs & aluInT & aluDec, -- CE DEC abs
"0000" & "100011" & rmwAbs & aluInT & aluDcp, -- CF iDCP abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- D0 BNE
"0000" & "100011" & readIndY & aluInT & aluCmp, -- D1 CMP (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- D2 *** JAM ***
"0000" & "100011" & rmwIndY & aluInT & aluDcp, -- D3 iDCP (zp),y
"0000" & "000000" & readZpX & aluInXXX & aluXXX, -- D4 iNOP zp,x
"0000" & "100011" & readZpX & aluInT & aluCmp, -- D5 CMP zp,x
"0000" & "100010" & rmwZpX & aluInT & aluDec, -- D6 DEC zp,x
"0000" & "100011" & rmwZpX & aluInT & aluDcp, -- D7 iDCP zp,x
"0000" & "001000" & implied & aluInClr & aluXXX, -- D8 CLD
"0000" & "100011" & readAbsY & aluInT & aluCmp, -- D9 CMP abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- DA iNOP implied
"0000" & "100011" & rmwAbsY & aluInT & aluDcp, -- DB iDCP abs,y
"0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- DC iNOP abs,x
"0000" & "100011" & readAbsX & aluInT & aluCmp, -- DD CMP abs,x
"0000" & "100010" & rmwAbsX & aluInT & aluDec, -- DE DEC abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluDcp, -- DF iDCP abs,x
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "100011" & immediate & aluInT & aluCpx, -- E0 CPX imm
"1000" & "110011" & readIndX & aluInT & aluSbc, -- E1 SBC (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- E2 iNOP imm
"1000" & "110011" & rmwIndX & aluInT & aluIsc, -- E3 iISC (zp,x)
"0000" & "100011" & readZp & aluInT & aluCpx, -- E4 CPX zp
"1000" & "110011" & readZp & aluInT & aluSbc, -- E5 SBC zp
"0000" & "100010" & rmwZp & aluInT & aluInc, -- E6 INC zp
"1000" & "110011" & rmwZp & aluInT & aluIsc, -- E7 iISC zp
"0100" & "100010" & implied & aluInX & aluInc, -- E8 INX
"1000" & "110011" & immediate & aluInT & aluSbc, -- E9 SBC imm
"0000" & "000000" & implied & aluInXXX & aluXXX, -- EA NOP
"1000" & "110011" & immediate & aluInT & aluSbc, -- EB SBC imm (illegal opc)
"0000" & "100011" & readAbs & aluInT & aluCpx, -- EC CPX abs
"1000" & "110011" & readAbs & aluInT & aluSbc, -- ED SBC abs
"0000" & "100010" & rmwAbs & aluInT & aluInc, -- EE INC abs
"1000" & "110011" & rmwAbs & aluInT & aluIsc, -- EF iISC abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- F0 BEQ
"1000" & "110011" & readIndY & aluInT & aluSbc, -- F1 SBC (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- F2 *** JAM ***
"1000" & "110011" & rmwIndY & aluInT & aluIsc, -- F3 iISC (zp),y
"0000" & "000000" & readZpX & aluInXXX & aluXXX, -- F4 iNOP zp,x
"1000" & "110011" & readZpX & aluInT & aluSbc, -- F5 SBC zp,x
"0000" & "100010" & rmwZpX & aluInT & aluInc, -- F6 INC zp,x
"1000" & "110011" & rmwZpX & aluInT & aluIsc, -- F7 iISC zp,x
"0000" & "001000" & implied & aluInSet & aluXXX, -- F8 SED
"1000" & "110011" & readAbsY & aluInT & aluSbc, -- F9 SBC abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- FA iNOP implied
"1000" & "110011" & rmwAbsY & aluInT & aluIsc, -- FB iISC abs,y
"0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- FC iNOP abs,x
"1000" & "110011" & readAbsX & aluInT & aluSbc, -- FD SBC abs,x
"0000" & "100010" & rmwAbsX & aluInT & aluInc, -- FE INC abs,x
"1000" & "110011" & rmwAbsX & aluInT & aluIsc -- FF iISC abs,x
);
signal opcInfo : decodedBitsDef;
signal nextOpcInfo : decodedBitsDef; -- Next opcode (decoded)
signal nextOpcInfoReg : decodedBitsDef; -- Next opcode (decoded) pipelined
signal theOpcode : unsigned(7 downto 0);
signal nextOpcode : unsigned(7 downto 0);
-- Program counter
signal PC : unsigned(15 downto 0); -- Program counter
-- Address generation
type nextAddrDef is (
nextAddrHold,
nextAddrIncr,
nextAddrIncrL, -- Increment low bits only (zeropage accesses)
nextAddrIncrH, -- Increment high bits only (page-boundary)
nextAddrDecrH, -- Decrement high bits (branch backwards)
nextAddrPc,
nextAddrIrq,
nextAddrReset,
nextAddrAbs,
nextAddrAbsIndexed,
nextAddrZeroPage,
nextAddrZPIndexed,
nextAddrStack,
nextAddrRelative
);
signal halt_dly : std_logic := '0'; -- !!! TODO: high address correction on boundary crossing continues on BA=0. Temp register to remember that incr is done.
signal nextAddr : nextAddrDef;
signal myAddr : unsigned(15 downto 0);
signal myAddrIncr : unsigned(15 downto 0);
signal myAddrIncrH : unsigned(7 downto 0);
signal myAddrDecrH : unsigned(7 downto 0);
signal theWe : std_logic;
signal irqActive : std_logic;
-- Output register
signal doReg : unsigned(7 downto 0);
-- Buffer register
signal T : unsigned(7 downto 0);
-- General registers
signal A: unsigned(7 downto 0); -- Accumulator
signal X: unsigned(7 downto 0); -- Index X
signal Y: unsigned(7 downto 0); -- Index Y
signal S: unsigned(7 downto 0); -- stack pointer
-- Status register
signal Creg: std_logic; -- Carry
signal Zreg: std_logic; -- Zero flag
signal Ireg: std_logic; -- Interrupt flag
signal Dreg: std_logic; -- Decimal mode
signal Vreg: std_logic; -- Overflow
signal Nreg: std_logic; -- Negative
-- ALU
-- ALU input
signal aluInput : unsigned(7 downto 0);
signal aluCmpInput : unsigned(7 downto 0);
-- ALU output
signal aluRegisterOut : unsigned(7 downto 0);
signal aluRmwOut : unsigned(7 downto 0);
signal aluC : std_logic;
signal aluZ : std_logic;
signal aluV : std_logic;
signal aluN : std_logic;
-- Pipeline registers
signal aluInputReg : unsigned(7 downto 0);
signal aluCmpInputReg : unsigned(7 downto 0);
signal aluRmwReg : unsigned(7 downto 0);
signal aluNineReg : unsigned(7 downto 0);
signal aluCReg : std_logic;
signal aluZReg : std_logic;
signal aluVReg : std_logic;
signal aluNReg : std_logic;
-- Indexing
signal indexOut : unsigned(8 downto 0);
begin
processAluInput: process(clk, opcInfo, A, X, Y, T, S)
variable temp : unsigned(7 downto 0);
begin
temp := (others => '1');
if opcInfo(opcInA) = '1' then
temp := temp and A;
end if;
if opcInfo(opcInE) = '1' then
temp := temp and (A or X"EE");
end if;
if opcInfo(opcInX) = '1' then
temp := temp and X;
end if;
if opcInfo(opcInY) = '1' then
temp := temp and Y;
end if;
if opcInfo(opcInS) = '1' then
temp := temp and S;
end if;
if opcInfo(opcInT) = '1' then
temp := temp and T;
end if;
if opcInfo(opcInClear) = '1' then
temp := (others => '0');
end if;
if rising_edge(clk) then
aluInputReg <= temp;
end if;
aluInput <= temp;
if pipelineAluMux then
aluInput <= aluInputReg;
end if;
end process;
processCmpInput: process(clk, opcInfo, A, X, Y)
variable temp : unsigned(7 downto 0);
begin
temp := (others => '1');
if opcInfo(opcInCmp) = '1' then
temp := temp and A;
end if;
if opcInfo(opcInCpx) = '1' then
temp := temp and X;
end if;
if opcInfo(opcInCpy) = '1' then
temp := temp and Y;
end if;
if rising_edge(clk) then
aluCmpInputReg <= temp;
end if;
aluCmpInput <= temp;
if pipelineAluMux then
aluCmpInput <= aluCmpInputReg;
end if;
end process;
-- ALU consists of two parts
-- Read-Modify-Write or index instructions: INC/DEC/ASL/LSR/ROR/ROL
-- Accumulator instructions: ADC, SBC, EOR, AND, EOR, ORA
-- Some instructions are both RMW and accumulator so for most
-- instructions the rmw results are routed through accu alu too.
processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, Nreg, Vreg, Dreg, Ireg, Zreg, Creg)
variable lowBits: unsigned(5 downto 0);
variable nineBits: unsigned(8 downto 0);
variable rmwBits: unsigned(8 downto 0);
variable varC : std_logic;
variable varZ : std_logic;
variable varV : std_logic;
variable varN : std_logic;
begin
lowBits := (others => '-');
nineBits := (others => '-');
rmwBits := (others => '-');
varV := aluInput(6); -- Default for BIT / PLP / RTI
-- Shift unit
case opcInfo(aluMode1From to aluMode1To) is
when aluModeInp =>
rmwBits := Creg & aluInput;
when aluModeP =>
rmwBits := Creg & Nreg & Vreg & '1' & (not irqActive) & Dreg & Ireg & Zreg & Creg;
when aluModeInc =>
rmwBits := Creg & (aluInput + 1);
when aluModeDec =>
rmwBits := Creg & (aluInput - 1);
when aluModeAsl =>
rmwBits := aluInput & "0";
when aluModeFlg =>
rmwBits := aluInput(0) & aluInput;
when aluModeLsr =>
rmwBits := aluInput(0) & "0" & aluInput(7 downto 1);
when aluModeRol =>
rmwBits := aluInput & Creg;
when aluModeRoR =>
rmwBits := aluInput(0) & Creg & aluInput(7 downto 1);
when aluModeAnc =>
rmwBits := (aluInput(7) and A(7)) & aluInput;
when others =>
rmwBits := Creg & aluInput;
end case;
-- ALU
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc =>
lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & rmwBits(3 downto 0) & "1");
ninebits := ("0" & A) + ("0" & rmwBits(7 downto 0)) + (B"00000000" & rmwBits(8));
when aluModeSbc =>
lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & (not rmwBits(3 downto 0)) & "1");
ninebits := ("0" & A) + ("0" & (not rmwBits(7 downto 0))) + (B"00000000" & rmwBits(8));
when aluModeCmp =>
ninebits := ("0" & aluCmpInput) + ("0" & (not rmwBits(7 downto 0))) + "000000001";
when aluModeAnd =>
ninebits := rmwBits(8) & (A and rmwBits(7 downto 0));
when aluModeEor =>
ninebits := rmwBits(8) & (A xor rmwBits(7 downto 0));
when aluModeOra =>
ninebits := rmwBits(8) & (A or rmwBits(7 downto 0));
when others =>
ninebits := rmwBits;
end case;
if (to_01(opcInfo(aluMode1From to aluMode1To)) = aluModeFlg) then
varZ := rmwBits(1);
elsif to_01(ninebits(7 downto 0)) = X"00" then
varZ := '1';
else
varZ := '0';
end if;
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc =>
-- decimal mode low bits correction, is done after setting Z flag.
if Dreg = '1' then
if lowBits(5 downto 1) > 9 then
ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
if lowBits(5) = '0' then
ninebits(8 downto 4) := ninebits(8 downto 4) + 1;
end if;
end if;
end if;
when others =>
null;
end case;
if (to_01(opcInfo(aluMode1From to aluMode1To)) = aluModeBit)
or (to_01(opcInfo(aluMode1From to aluMode1To)) = aluModeFlg) then
varN := rmwBits(7);
else
varN := nineBits(7);
end if;
varC := ninebits(8);
if to_01(opcInfo(aluMode2From to aluMode2To)) = aluModeArr then
varC := aluInput(7);
varV := aluInput(7) xor aluInput(6);
end if;
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc =>
-- decimal mode high bits correction, is done after setting Z and N flags
varV := (A(7) xor ninebits(7)) and (rmwBits(7) xor ninebits(7));
if Dreg = '1' then
if ninebits(8 downto 4) > 9 then
ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
varC := '1';
end if;
end if;
when aluModeSbc =>
varV := (A(7) xor ninebits(7)) and ((not rmwBits(7)) xor ninebits(7));
if Dreg = '1' then
-- Check for borrow (lower 4 bits)
if lowBits(5) = '0' then
ninebits(3 downto 0) := ninebits(3 downto 0) - 6;
end if;
-- Check for borrow (upper 4 bits)
if ninebits(8) = '0' then
ninebits(8 downto 4) := ninebits(8 downto 4) - 6;
end if;
end if;
when aluModeArr =>
if Dreg = '1' then
if (("0" & aluInput(3 downto 0)) + ("0000" & aluInput(0))) > 5 then
ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
end if;
if (("0" & aluInput(7 downto 4)) + ("0000" & aluInput(4))) > 5 then
ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
varC := '1';
else
varC := '0';
end if;
end if;
when others =>
null;
end case;
if rising_edge(clk) then
aluRmwReg <= rmwBits(7 downto 0);
aluNineReg <= ninebits(7 downto 0);
aluCReg <= varC;
aluZReg <= varZ;
aluVReg <= varV;
aluNReg <= varN;
end if;
aluRmwOut <= rmwBits(7 downto 0);
aluRegisterOut <= ninebits(7 downto 0);
aluC <= varC;
aluZ <= varZ;
aluV <= varV;
aluN <= varN;
if pipelineAluOut then
aluRmwOut <= aluRmwReg;
aluRegisterOut <= aluNineReg;
aluC <= aluCReg;
aluZ <= aluZReg;
aluV <= aluVReg;
aluN <= aluNReg;
end if;
end process;
calcInterrupt: process(clk)
begin
if rising_edge(clk) then
if (enable = '1') then -- and (halt = '0') then
irqReg <= irq_n;
nmiEdge <= nmi_n;
if (nmiEdge = '1') and (nmi_n = '0') then
nmiReg <= '0';
end if;
if theCpuCycle = cycleStack4 -- MWW
or reset = '1' then
nmiReg <= '1';
end if;
if halt = '0' then
if theCpuCycle /= cycleBranchTaken then
-- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ.
-- Presumably this is done in the real 6502/6510 to prevent a double IRQ.
processNmi <= not (nmiReg or opcInfo(opcIRQ));
processIrq <= not (irqReg or opcInfo(opcIRQ));
end if;
end if;
end if;
processInt <= processNmi or (processIrq and (not Ireg));
end if;
end process;
calcNextOpcode: process(clk, d, reset, processInt)
variable myNextOpcode : unsigned(7 downto 0);
begin
-- Next opcode is read from input unless a reset or IRQ is pending.
myNextOpcode := d;
if reset = '1' then
myNextOpcode := X"4C";
elsif processInt = '1' then
myNextOpcode := X"00";
end if;
nextOpcode <= myNextOpcode;
end process;
nextOpcInfo <= opcodeInfoTable(to_integer(to_01(nextOpcode, '0')));
process(clk)
begin
if rising_edge(clk) then
nextOpcInfoReg <= nextOpcInfo;
end if;
end process;
-- Read bits and flags from opcodeInfoTable and store in opcInfo.
-- This info is used to control the execution of the opcode.
calcOpcInfo: process(clk)
begin
if rising_edge(clk) then
if (enable = '1') and (halt = '0') then
if (reset = '1') or (theCpuCycle = opcodeFetch) then
opcInfo <= nextOpcInfo;
if pipelineOpcode then
opcInfo <= nextOpcInfoReg;
end if;
end if;
end if;
end if;
end process;
calcTheOpcode: process(clk)
begin
if rising_edge(clk) then
if (enable = '1') and (halt = '0') then
if theCpuCycle = opcodeFetch then
irqActive <= '0';
if processInt = '1' then
irqActive <= '1';
end if;
-- Fetch opcode
theOpcode <= nextOpcode;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- State machine
-- -----------------------------------------------------------------------
process(enable, halt, theCpuCycle, opcInfo)
begin
updateRegisters <= false;
if (enable = '1') and (halt = '0') then
if opcInfo(opcRti) = '1' then
if theCpuCycle = cycleRead then
updateRegisters <= true;
end if;
elsif theCpuCycle = opcodeFetch then
updateRegisters <= true;
end if;
end if;
end process;
debugOpcode <= theOpcode;
process(clk)
begin
if rising_edge(clk) then
if (enable = '1') and (halt = '0') then
theCpuCycle <= nextCpuCycle;
end if;
if reset = '1' then
theCpuCycle <= cycle2;
end if;
end if;
end process;
-- Determine the next cpu cycle. After the last cycle we always
-- go to opcodeFetch to get the next opcode.
calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, indexOut, T, Nreg, Vreg, Creg, Zreg)
begin
nextCpuCycle <= opcodeFetch;
case theCpuCycle is
when opcodeFetch =>
nextCpuCycle <= cycle2;
when cycle2 =>
if opcInfo(opcBranch) = '1' then
if (Nreg = theOpcode(5) and theOpcode(7 downto 6) = "00")
or (Vreg = theOpcode(5) and theOpcode(7 downto 6) = "01")
or (Creg = theOpcode(5) and theOpcode(7 downto 6) = "10")
or (Zreg = theOpcode(5) and theOpcode(7 downto 6) = "11") then
-- Branch condition is true
nextCpuCycle <= cycleBranchTaken;
end if;
elsif (opcInfo(opcStackUp) = '1') then
nextCpuCycle <= cycleStack1;
elsif opcInfo(opcStackAddr) = '1'
and opcInfo(opcStackData) = '1' then
nextCpuCycle <= cycleStack2;
elsif opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack1;
elsif opcInfo(opcStackData) = '1' then
nextCpuCycle <= cycleWrite;
elsif opcInfo(opcAbsolute) = '1' then
nextCpuCycle <= cycle3;
elsif opcInfo(opcIndirect) = '1' then
if opcInfo(indexX) = '1' then
nextCpuCycle <= cyclePreIndirect;
else
nextCpuCycle <= cycleIndirect;
end if;
elsif opcInfo(opcZeroPage) = '1' then
if opcInfo(opcWrite) = '1' then
if (opcInfo(indexX) = '1')
or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreWrite;
else
nextCpuCycle <= cycleWrite;
end if;
else
if (opcInfo(indexX) = '1')
or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreRead;
else
nextCpuCycle <= cycleRead2;
end if;
end if;
elsif opcInfo(opcJump) = '1' then
nextCpuCycle <= cycleJump;
end if;
when cycle3 =>
nextCpuCycle <= cycleRead;
if opcInfo(opcWrite) = '1' then
if (opcInfo(indexX) = '1')
or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreWrite;
else
nextCpuCycle <= cycleWrite;
end if;
end if;
if (opcInfo(opcIndirect) = '1')
and (opcInfo(indexX) = '1') then
if opcInfo(opcWrite) = '1' then
nextCpuCycle <= cycleWrite;
else
nextCpuCycle <= cycleRead2;
end if;
end if;
when cyclePreIndirect =>
nextCpuCycle <= cycleIndirect;
when cycleIndirect =>
nextCpuCycle <= cycle3;
when cycleBranchTaken =>
if indexOut(8) /= T(7) then
-- Page boundary crossing during branch.
nextCpuCycle <= cycleBranchPage;
end if;
when cyclePreRead =>
if opcInfo(opcZeroPage) = '1' then
nextCpuCycle <= cycleRead2;
end if;
when cycleRead =>
if opcInfo(opcJump) = '1' then
nextCpuCycle <= cycleJump;
elsif indexOut(8) = '1' then
-- Page boundary crossing while indexed addressing.
nextCpuCycle <= cycleRead2;
elsif opcInfo(opcRmw) = '1' then
nextCpuCycle <= cycleRmw;
if opcInfo(indexX) = '1'
or opcInfo(indexY) = '1' then
-- 6510 needs extra cycle for indexed addressing
-- combined with RMW indexing
nextCpuCycle <= cycleRead2;
end if;
end if;
when cycleRead2 =>
if opcInfo(opcRmw) = '1' then
nextCpuCycle <= cycleRmw;
end if;
when cycleRmw =>
nextCpuCycle <= cycleWrite;
when cyclePreWrite =>
nextCpuCycle <= cycleWrite;
when cycleStack1 =>
nextCpuCycle <= cycleRead;
if opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack2;
end if;
when cycleStack2 =>
nextCpuCycle <= cycleStack3;
if opcInfo(opcRti) = '1' then
nextCpuCycle <= cycleRead;
end if;
if opcInfo(opcStackData) = '0'
and opcInfo(opcStackUp) = '1' then
nextCpuCycle <= cycleJump;
end if;
when cycleStack3 =>
nextCpuCycle <= cycleRead;
if opcInfo(opcStackData) = '0'
or opcInfo(opcStackUp) = '1' then
nextCpuCycle <= cycleJump;
elsif opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack4;
end if;
when cycleStack4 =>
nextCpuCycle <= cycleRead;
when cycleJump =>
if opcInfo(opcIncrAfter) = '1' then
-- Insert extra cycle
nextCpuCycle <= cycleEnd;
end if;
when others =>
null;
end case;
end process;
-- -----------------------------------------------------------------------
-- T register
-- -----------------------------------------------------------------------
calcT: process(clk)
begin
if rising_edge(clk) then
if (enable = '1') and (halt = '0') then
case theCpuCycle is
when cycle2 =>
T <= d;
when cycleStack1 | cycleStack2 =>
if opcInfo(opcStackUp) = '1' then
-- Read from stack
T <= d;
end if;
when cycleIndirect | cycleRead | cycleRead2 =>
T <= d;
when others =>
null;
end case;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- A register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateA) = '1' then
A <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- X register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateX) = '1' then
X <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Y register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateY) = '1' then
Y <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- C flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateC) = '1' then
Creg <= aluC;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Z flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateZ) = '1' then
Zreg <= aluZ;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- I flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateI) = '1' then
Ireg <= aluInput(2);
end if;
end if;
-- Hack to bypass 1 clock delay when CLI is interrupted by RDY/HALT.
if enable = '1' and (theCpuCycle = cycle2) and (halt = '1') then
if (theOpcode = X"58") then
Ireg <= '0';
end if;
if (theOpcode = X"78") then
Ireg <= '1';
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- D flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateD) = '1' then
Dreg <= aluInput(3);
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- V flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateV) = '1' then
Vreg <= aluV;
end if;
end if;
if so_reg = '1' and so_n = '0' then
Vreg <= '1';
end if;
so_reg <= so_n;
end if;
end process;
-- -----------------------------------------------------------------------
-- N flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateN) = '1' then
Nreg <= aluN;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Stack pointer
-- -----------------------------------------------------------------------
process(clk)
variable sIncDec : unsigned(7 downto 0);
variable updateFlag : boolean;
begin
if rising_edge(clk) then
if opcInfo(opcStackUp) = '1' then
sIncDec := S + 1;
else
sIncDec := S - 1;
end if;
if (enable = '1') and (halt = '0') then
updateFlag := false;
case nextCpuCycle is
when cycleStack1 =>
if (opcInfo(opcStackUp) = '1')
or (opcInfo(opcStackData) = '1') then
updateFlag := true;
end if;
when cycleStack2 =>
updateFlag := true;
when cycleStack3 =>
updateFlag := true;
when cycleStack4 =>
updateFlag := true;
when cycleRead =>
if opcInfo(opcRti) = '1' then
updateFlag := true;
end if;
when cycleWrite =>
if opcInfo(opcStackData) = '1' then
updateFlag := true;
end if;
when others =>
null;
end case;
if updateFlag then
S <= sIncDec;
end if;
end if;
if updateRegisters then
if opcInfo(opcUpdateS) = '1' then
S <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Data out
-- -----------------------------------------------------------------------
--calcDo: process(cpuNo, theCpuCycle, aluOut, PC, T)
calcDo: process(clk)
begin
if rising_edge(clk) then
if (enable = '1') and (halt = '0') then
doReg <= aluRmwOut;
if opcInfo(opcInH) = '1' then
-- For illegal opcodes SHA, SHX, SHY, SHS
doReg <= aluRmwOut and myAddrIncrH;
end if;
case nextCpuCycle is
when cycleStack2 =>
if opcInfo(opcIRQ) = '1'
and irqActive = '0' then
doReg <= myAddrIncr(15 downto 8);
else
doReg <= PC(15 downto 8);
end if;
when cycleStack3 =>
doReg <= PC(7 downto 0);
when cycleRmw =>
-- q <= T; -- Read-modify-write write old value first.
doReg <= d; -- Read-modify-write write old value first.
when others => null;
end case;
end if;
end if;
end process;
q <= doReg;
-- -----------------------------------------------------------------------
-- Write enable
-- -----------------------------------------------------------------------
calcWe: process(clk)
begin
if rising_edge(clk) then
if (enable = '1') and (halt = '0') then
theWe <= '0';
case nextCpuCycle is
when cycleStack1 =>
if opcInfo(opcStackUp) = '0'
and ((opcInfo(opcStackAddr) = '0')
or (opcInfo(opcStackData) = '1')) then
theWe <= '1';
end if;
when cycleStack2 | cycleStack3 | cycleStack4 =>
if opcInfo(opcStackUp) = '0' then
theWe <= '1';
end if;
when cycleRmw =>
theWe <= '1';
when cycleWrite =>
theWe <= '1';
when others =>
null;
end case;
if reset = '1' then
theWe <= '0';
end if;
end if;
end if;
end process;
we <= theWe;
-- -----------------------------------------------------------------------
-- Program counter
-- -----------------------------------------------------------------------
calcPC: process(clk)
begin
if rising_edge(clk) then
if (enable = '1') and (halt = '0') then
case theCpuCycle is
when opcodeFetch =>
PC <= myAddr;
when cycle2 =>
if irqActive = '0' then
if opcInfo(opcSecondByte) = '1' then
PC <= myAddrIncr;
else
PC <= myAddr;
end if;
end if;
when cycle3 =>
if opcInfo(opcAbsolute) = '1' then
PC <= myAddrIncr;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
debugPc <= PC;
-- -----------------------------------------------------------------------
-- Address generation
-- -----------------------------------------------------------------------
calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset, processInt)
begin
nextAddr <= nextAddrIncr;
case theCpuCycle is
when opcodeFetch =>
if processInt = '1' then
nextAddr <= nextAddrHold;
end if;
when cycle2 =>
if opcInfo(opcStackAddr) = '1'
or opcInfo(opcStackData) = '1' then
nextAddr <= nextAddrStack;
elsif opcInfo(opcAbsolute) = '1' then
nextAddr <= nextAddrIncr;
elsif opcInfo(opcZeroPage) = '1' then
nextAddr <= nextAddrZeroPage;
elsif opcInfo(opcIndirect) = '1' then
nextAddr <= nextAddrZeroPage;
elsif opcInfo(opcSecondByte) = '1' then
nextAddr <= nextAddrIncr;
else
nextAddr <= nextAddrHold;
end if;
when cycle3 =>
if (opcInfo(opcIndirect) = '1')
and (opcInfo(indexX) = '1') then
nextAddr <= nextAddrAbs;
else
nextAddr <= nextAddrAbsIndexed;
end if;
when cyclePreIndirect =>
nextAddr <= nextAddrZPIndexed;
when cycleIndirect =>
nextAddr <= nextAddrIncrL;
when cycleBranchTaken =>
nextAddr <= nextAddrRelative;
when cycleBranchPage =>
if T(7) = '0' then
nextAddr <= nextAddrIncrH;
else
nextAddr <= nextAddrDecrH;
end if;
when cyclePreRead =>
nextAddr <= nextAddrZPIndexed;
when cycleRead =>
nextAddr <= nextAddrPc;
if opcInfo(opcJump) = '1' then
-- Emulate 6510 bug, jmp(xxFF) fetches from same page.
-- Replace with nextAddrIncr if emulating 65C02 or later cpu.
nextAddr <= nextAddrIncrL;
elsif indexOut(8) = '1' then
nextAddr <= nextAddrIncrH;
elsif opcInfo(opcRmw) = '1' then
nextAddr <= nextAddrHold;
end if;
when cycleRead2 =>
nextAddr <= nextAddrPc;
if opcInfo(opcRmw) = '1' then
nextAddr <= nextAddrHold;
end if;
when cycleRmw =>
nextAddr <= nextAddrHold;
when cyclePreWrite =>
nextAddr <= nextAddrHold;
if opcInfo(opcZeroPage) = '1' then
nextAddr <= nextAddrZPIndexed;
elsif indexOut(8) = '1' then
nextAddr <= nextAddrIncrH;
end if;
when cycleWrite =>
nextAddr <= nextAddrPc;
when cycleStack1 =>
nextAddr <= nextAddrStack;
when cycleStack2 =>
nextAddr <= nextAddrStack;
when cycleStack3 =>
nextAddr <= nextAddrStack;
if opcInfo(opcStackData) = '0' then
nextAddr <= nextAddrPc;
end if;
when cycleStack4 =>
nextAddr <= nextAddrIrq;
when cycleJump =>
nextAddr <= nextAddrAbs;
when others =>
null;
end case;
if reset = '1' then
nextAddr <= nextAddrReset;
end if;
end process;
indexAlu: process(opcInfo, myAddr, T, X, Y)
begin
if opcInfo(indexX) = '1' then
indexOut <= (B"0" & T) + (B"0" & X);
elsif opcInfo(indexY) = '1' then
indexOut <= (B"0" & T) + (B"0" & Y);
elsif opcInfo(opcBranch) = '1' then
indexOut <= (B"0" & T) + (B"0" & myAddr(7 downto 0));
else
indexOut <= B"0" & T;
end if;
end process;
calcAddr: process(clk)
begin
if rising_edge(clk) then
if (enable = '1') then
halt_dly <= halt;
end if;
if (enable = '1') and (halt = '0') then
case nextAddr is
when nextAddrIncr => myAddr <= myAddrIncr;
when nextAddrIncrL => myAddr(7 downto 0) <= myAddrIncr(7 downto 0);
-- !!! TODO fix properly. Real CPU updates address even if BA=0. Using halt_dly to emulate behavior until proper fix.
-- when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH;
when nextAddrDecrH => myAddr(15 downto 8) <= myAddrDecrH;
when nextAddrPc => myAddr <= PC;
when nextAddrIrq =>
myAddr <= X"FFFE";
if nmiReg = '0' then
myAddr <= X"FFFA";
end if;
when nextAddrReset => myAddr <= X"FFFC";
when nextAddrAbs => myAddr <= d & T;
when nextAddrAbsIndexed => myAddr <= d & indexOut(7 downto 0);
when nextAddrZeroPage => myAddr <= "00000000" & d;
when nextAddrZPIndexed => myAddr <= "00000000" & indexOut(7 downto 0);
when nextAddrStack => myAddr <= "00000001" & S;
when nextAddrRelative => myAddr(7 downto 0) <= indexOut(7 downto 0);
when others => null;
end case;
end if;
if (enable = '1') and (halt_dly = '0') then
case nextAddr is
when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH;
when others => null;
end case;
end if;
end if;
end process;
myAddrIncr <= myAddr + 1;
myAddrIncrH <= (aluRmwOut and (myAddr(15 downto 8) + 1)) when (opcInfo(opcInH) and (opcInfo(opcInY) or opcInfo(opcInX))) = '1'
else myAddr(15 downto 8) + 1;
myAddrDecrH <= myAddr(15 downto 8) - 1;
addr <= myAddr;
debugA <= A;
debugX <= X;
debugY <= Y;
debugS <= S;
debug_flags <= Nreg & Vreg & "10" & Dreg & Ireg & Zreg & Creg;
end architecture;
| gpl-3.0 | 0e9517bca2042498aa9250a1b64ec1ba | 0.567896 | 3.298165 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/korvet/src/keyboard/keyboard.vhd | 1 | 12,133 | -- ###################################################################################
--
-- #### #### #####
-- ## ## ##### ## ## ##### ## ###### ##### ##### ##### ## ##
-- ## ## ## ## ## ## ## ## ##### ## ## ## ## ## ## ## ##
-- ## ## ## ## ## ## ###### ## ###### ###### ## ## ######
-- ## ## ## ## ### ## ## ## ## ## ## ##
-- #### ######## ##### # ##### ##### ## ##### ##### ##### #####
--
-- ###################################################################################
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity keyboard is
generic (FilterSize : positive := 10);
port(
clk : in std_logic;
reset : in std_logic;
o_reset : out std_logic;
PS2_Clk : in std_logic;
PS2_Data : in std_logic;
Key_Addr : in std_logic_vector(8 downto 0);
Key_Data : out std_logic_vector(7 downto 0) );
end keyboard;
architecture Behavioral of keyboard is
signal PS2_Datr : std_logic;
signal DoRead : std_logic; -- From outside when reading the scan code
signal Scan_Err : std_logic; -- To outside : Parity or Overflow error
signal Scan_Code : std_logic_vector(7 downto 0); -- Eight bits Data Out
signal Filter : std_logic_vector(FilterSize-1 downto 0);
signal Filter_t0 : std_logic_vector(FilterSize-1 downto 0);
signal Filter_t1 : std_logic_vector(FilterSize-1 downto 0);
signal Fall_Clk : std_logic;
signal Bit_Cnt : unsigned (3 downto 0);
signal Parity : std_logic;
signal S_Reg : std_logic_vector(8 downto 0);
signal PS2_Clk_f : std_logic; signal Code_Readed : std_logic;
signal Key_Released : std_logic;
signal Extend_Key : std_logic;
signal Key_Data_0 : std_logic_vector(7 downto 0);
signal Key_Data_1 : std_logic_vector(7 downto 0);
type Matrix_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal Matrix_0 : Matrix_Image(0 to 7);
signal Matrix_1 : Matrix_Image(0 to 7);
Type State_t is (Idle, Shifting);
signal State : State_t;
begin
Filter_t0 <= (others=>'0');
Filter_t1 <= (others=>'1');
process (Clk,Reset)
begin
if Reset='1' then
PS2_Datr <= '0';
PS2_Clk_f <= '0';
Filter <= (others=>'0');
Fall_Clk <= '0';
elsif rising_edge (Clk) then
PS2_Datr <= PS2_Data and PS2_Data; -- also turns 'H' into '1'
Fall_Clk <= '0';
Filter <= (PS2_Clk and PS2_CLK) & Filter(Filter'high downto 1);
if Filter = Filter_t1 then
PS2_Clk_f <= '1';
elsif Filter = Filter_t0 then
PS2_Clk_f <= '0';
if PS2_Clk_f = '1' then
Fall_Clk <= '1';
end if;
end if;
end if;
end process;
process(Clk,Reset)
begin
if Reset='1' then
State <= Idle;
Bit_Cnt <= (others => '0');
S_Reg <= (others => '0');
Scan_Code <= (others => '0');
Parity <= '0';
Scan_Err <= '0';
Code_Readed <= '0';
elsif rising_edge (Clk) then
Code_Readed <= '0';
case State is
when Idle =>
Parity <= '0';
Bit_Cnt <= (others => '0');
-- note that we dont need to clear the Shift Register
if Fall_Clk='1' and PS2_Datr='0' then -- Start bit
Scan_Err <= '0';
State <= Shifting;
end if;
when Shifting =>
if Bit_Cnt >= 9 then
if Fall_Clk='1' then -- Stop Bit
-- Error is (wrong Parity) or (Stop='0') or Overflow
Scan_Err <= (not Parity) or (not PS2_Datr);
Scan_Code <= S_Reg(7 downto 0);
Code_Readed <= '1';
State <= Idle;
end if;
elsif Fall_Clk='1' then
Bit_Cnt <= Bit_Cnt + 1;
S_Reg <= PS2_Datr & S_Reg (S_Reg'high downto 1); -- Shift right
Parity <= Parity xor PS2_Datr;
end if;
when others => -- never reached
State <= Idle;
end case;
--Scan_Err <= '0'; -- to create an on-purpose error on Scan_Err !
end if;
end process;
process(Clk,Reset)
variable aaa : std_logic_vector(10 downto 0);
variable bbb : std_logic_vector(10 downto 0);
begin
if Reset='1' then
Matrix_0 <= (others => (others => '0'));
Matrix_1 <= (others => (others => '0'));
Key_Released <= '0';
Extend_Key <= '0';
elsif rising_edge (Clk) then
o_reset <= '0';
if Code_Readed = '1' then -- ScanCode is Readed
if Scan_Code = x"F0" then -- Key is Released
Key_Released <= '1';
elsif Scan_Code = x"E0" then -- Extended Key Pressed
Extend_Key <= '1';
else -- Analyse
aaa := (others=>'0');
bbb := (others=>'0');
case Scan_Code is
------------------------------------
when x"52" => aaa := "00000000001"; -- @
when x"1C" => aaa := "00000000010"; -- A
when x"32" => aaa := "00000000100"; -- B
when x"21" => aaa := "00000001000"; -- C
when x"23" => aaa := "00000010000"; -- D
when x"24" => aaa := "00000100000"; -- E
when x"2B" => aaa := "00001000000"; -- F
when x"34" => aaa := "00010000000"; -- G
------------------------------------
when x"33" => aaa := "00100000001"; -- H
when x"43" => aaa := "00100000010"; -- I
when x"3B" => aaa := "00100000100"; -- J
when x"42" => aaa := "00100001000"; -- K
when x"4B" => aaa := "00100010000"; -- L
when x"3A" => aaa := "00100100000"; -- M
when x"31" => aaa := "00101000000"; -- N
when x"44" => aaa := "00110000000"; -- O
------------------------------------
when x"4D" => aaa := "01000000001"; -- P
when x"15" => aaa := "01000000010"; -- Q
when x"2D" => aaa := "01000000100"; -- R
when x"1B" => aaa := "01000001000"; -- S
when x"2C" => aaa := "01000010000"; -- T
when x"3C" => aaa := "01000100000"; -- U
when x"2A" => aaa := "01001000000"; -- V
when x"1D" => aaa := "01010000000"; -- W
------------------------------------
when x"22" => aaa := "01100000001"; -- X
when x"1A" => aaa := "01100000010"; -- Y
when x"35" => aaa := "01100000100"; -- Z
when x"54" => aaa := "01100001000"; -- [
when x"0E" => aaa := "01100010000"; -- ?
when x"5B" => aaa := "01100100000"; -- ]
when x"61" => aaa := "01101000000"; -- ?
when x"4C" => aaa := "01110000000"; -- ?
------------------------------------
when x"45" => aaa := "10000000001"; -- 0
when x"16" => aaa := "10000000010"; -- 1
when x"1E" => aaa := "10000000100"; -- 2
when x"26" => aaa := "10000001000"; -- 3
when x"25" => aaa := "10000010000"; -- 4
when x"2E" => aaa := "10000100000"; -- 5
when x"36" => aaa := "10001000000"; -- 6
when x"3D" => aaa := "10010000000"; -- 7
------------------------------------
when x"3E" => aaa := "10100000001"; -- 8
when x"46" => aaa := "10100000010"; -- 9
when x"5D" => aaa := "10100000100"; -- *
when x"55" => aaa := "10100001000"; -- +
when x"41" => aaa := "10100010000"; -- <
when x"4A" => aaa := "10100100000"; -- =
when x"49" => aaa := "10101000000"; -- >
when x"4E" => aaa := "10110000000"; -- ?
------------------------------------
when x"5A" => aaa := "11000000001"; -- ENTER
when x"7B" => aaa := "11000000010"; -- ????
when x"07" => aaa := "11000000100"; -- ????
when x"77" => aaa := "11000001000"; -- ??
when x"7C" => aaa := "11000010000"; -- ??
when x"66" => aaa := "11000100000"; -- BACKSPACE
when x"0D" => aaa := "11001000000"; -- TAB
when x"29" => aaa := "11010000000"; -- SPACE
------------------------------------
when x"12" => aaa := "11100000001"; -- ?? ???.
when x"11" =>
case Extend_Key is
when '0' => aaa := "11100000010"; -- ???
when others => aaa := "11100000100"; -- ????
end case;
when x"76" => aaa := "11100001000"; -- ???
when x"14" =>
case Extend_Key is
when '0' => aaa := "11101000000"; -- o
when others => aaa := "11100010000"; -- ???
end case;
when x"58" => aaa := "11100100000"; -- ???
when x"59" => aaa := "11110000000"; -- ?? ????.
------------------------------------
when x"70" => bbb := "00000000001"; -- 0
when x"69" => bbb := "00000000010"; -- 1
when x"72" => bbb := "00000000100"; -- 2
when x"7A" => bbb := "00000001000"; -- 3
when x"6B" => bbb := "00000010000"; -- 4
when x"73" => bbb := "00000100000"; -- 5
when x"74" => bbb := "00001000000"; -- 6
when x"6C" => bbb := "00010000000"; -- 7
------------------------------------
when x"75" => bbb := "00100000001"; -- 8
when x"7D" => bbb := "00100000010"; -- 9
when x"71" => bbb := "00101000000"; -- .
------------------------------------
when x"05" => bbb := "01000000001"; -- P
when x"06" => bbb := "01000000010"; -- Q
when x"04" => bbb := "01000000100"; -- R
when x"0C" => bbb := "01000001000"; -- S
when x"03" => bbb := "01000010000"; -- T
------------------------------------
when x"7E" => o_reset <= '1';
when others => null;
end case;
if Key_Released = '0' then
Matrix_0(to_integer(unsigned(aaa(10 downto 8)))) <=
Matrix_0(to_integer(unsigned(aaa(10 downto 8)))) or
std_logic_vector(unsigned(aaa(7 downto 0)));
Matrix_1(to_integer(unsigned(bbb(10 downto 8)))) <=
Matrix_1(to_integer(unsigned(bbb(10 downto 8)))) or
std_logic_vector(unsigned(bbb(7 downto 0)));
else
Matrix_0(to_integer(unsigned(aaa(10 downto 8)))) <=
Matrix_0(to_integer(unsigned(aaa(10 downto 8)))) and
std_logic_vector(not unsigned(aaa(7 downto 0)));
Matrix_1(to_integer(unsigned(bbb(10 downto 8)))) <=
Matrix_1(to_integer(unsigned(bbb(10 downto 8)))) and
std_logic_vector(not unsigned(bbb(7 downto 0)));
end if;
Key_Released <= '0';
Extend_Key <= '0';
end if;
end if;
end if;
end process;
-- if RX_ShiftReg = x"aa" and RX_Received = '1' then
-- Matrix <= (others => (others => '0'));
-- end if;
g_out1 : for i in 0 to 7 generate
Key_Data_0(i) <= (Matrix_0(0)(i) and Key_Addr(0)) or
(Matrix_0(1)(i) and Key_Addr(1)) or
(Matrix_0(2)(i) and Key_Addr(2)) or
(Matrix_0(3)(i) and Key_Addr(3)) or
(Matrix_0(4)(i) and Key_Addr(4)) or
(Matrix_0(5)(i) and Key_Addr(5)) or
(Matrix_0(6)(i) and Key_Addr(6)) or
(Matrix_0(7)(i) and Key_Addr(7));
end generate;
g_out2 : for i in 0 to 7 generate
Key_Data_1(i) <= (Matrix_1(0)(i) and Key_Addr(0)) or
(Matrix_1(1)(i) and Key_Addr(1)) or
(Matrix_1(2)(i) and Key_Addr(2)) or
(Matrix_1(3)(i) and Key_Addr(3)) or
(Matrix_1(4)(i) and Key_Addr(4)) or
(Matrix_1(5)(i) and Key_Addr(5)) or
(Matrix_1(6)(i) and Key_Addr(6)) or
(Matrix_1(7)(i) and Key_Addr(7));
end generate;
Key_Data <= Key_Data_0 when Key_Addr(8) = '0' else Key_Data_1;
end Behavioral;
| gpl-3.0 | c6c28ae837573be37698065e50e98eb7 | 0.430891 | 3.482491 | false | false | false | false |
sonologic/gmzpu | vhdl/wb_slaves/WBOPRT08.vhdl | 1 | 1,044 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity WBOPRT08 is
port(
-- WISHBONE SLAVE interface:
ACK_O : out std_logic;
CLK_I : in std_logic;
DAT_I : in std_logic_vector( 7 downto 0 );
DAT_O : out std_logic_vector( 7 downto 0 );
RST_I : in std_logic;
STB_I : in std_logic;
WE_I : in std_logic;
-- Output port (non-WISHBONE signals):
PRT_O : out std_logic_vector( 7 downto 0 )
);
end entity WBOPRT08;
architecture WBOPRT081 of WBOPRT08 is
signal Q: std_logic_vector( 7 downto 0 );
begin
REG: process( CLK_I )
begin
if( rising_edge( CLK_I ) ) then
if( RST_I = '1' ) then
Q <= B"00000000";
elsif( (STB_I and WE_I) = '1' ) then
Q <= DAT_I( 7 downto 0 );
else
Q <= Q;
end if;
end if;
end process REG;
ACK_O <= STB_I;
DAT_O <= Q;
PRT_O <= Q;
end architecture WBOPRT081;
| bsd-3-clause | 6c6ecda4d7e95b3d90e2995524af48d4 | 0.504789 | 3.222222 | false | false | false | false |
223323/lab2 | HDL/source/rtl/vhdl/vga.vhd | 1 | 9,060 | -------------------------------------------------------------------------------
-- Department of Computer Engineering and Communications
-- Author: LPRS2 <[email protected]>
--
-- Module Name: vga
--
-- Description:
--
-- Instantiate DCM and vga_sync with resolution parameter
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity vga is
generic (
RESOLUTION_TYPE : natural := 0;
H_RES : natural := 640;
V_RES : natural := 480
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
--
direct_mode_i : in std_logic; -- 0 - text and graphics interface mode, 1 - direct mode (direct force RGB component)
dir_red_i : in std_logic_vector(7 downto 0);
dir_green_i : in std_logic_vector(7 downto 0);
dir_blue_i : in std_logic_vector(7 downto 0);
--
show_frame_i : in std_logic;
active_pixel_i : in std_logic;
foreground_color_i : in std_logic_vector(23 downto 0);
background_color_i : in std_logic_vector(23 downto 0);
frame_color_i : in std_logic_vector(23 downto 0);
red_o : out std_logic_vector(7 downto 0);
green_o : out std_logic_vector(7 downto 0);
blue_o : out std_logic_vector(7 downto 0);
pixel_row_o : out std_logic_vector(10 downto 0);
pixel_column_o : out std_logic_vector(10 downto 0);
hsync_o : out std_logic;
vsync_o : out std_logic;
psave_o : out std_logic;
blank_o : out std_logic;
vga_pix_clk_o : out std_logic;
vga_rst_n_o : out std_logic;
sync_o : out std_logic
);
end vga;
architecture rtl of vga is
component vga_sync is generic (
HORIZONTAL_RES : natural := 800;
VERTICAL_RES : natural := 600;
FRAME_SIZE : natural := 4
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
--
direct_mode_i : in std_logic; -- 0 - text and graphics interface mode, 1 - direct mode (direct force RGB component)
dir_red_i : in std_logic_vector(7 downto 0);
dir_green_i : in std_logic_vector(7 downto 0);
dir_blue_i : in std_logic_vector(7 downto 0);
--
show_frame_i : in std_logic;
active_pixel_i : in std_logic;
foreground_color_i : in std_logic_vector(23 downto 0);
background_color_i : in std_logic_vector(23 downto 0);
frame_color_i : in std_logic_vector(23 downto 0);
red_o : out std_logic_vector(7 downto 0);
green_o : out std_logic_vector(7 downto 0);
blue_o : out std_logic_vector(7 downto 0);
horiz_sync_o : out std_logic;
vert_sync_o : out std_logic;
pixel_row_o : out std_logic_vector(10 downto 0);
pixel_column_o : out std_logic_vector(10 downto 0);
psave_o : out std_logic;
blank_o : out std_logic;
pix_clk_o : out std_logic;
sync_o : out std_logic
);
end component vga_sync;
component dcm25MHz
port(
CLK_IN1 : in std_logic;
CLK_OUT1 : out std_logic;
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
component dcm50MHz
port(
CLK_IN1 : in std_logic;
CLK_OUT1 : out std_logic;
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
component dcm75MHz
port(
CLK_IN1 : in std_logic;
CLK_OUT1 : out std_logic;
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
component dcm108MHz
port(
CLK_IN1 : in std_logic;
CLK_OUT1 : out std_logic;
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
component SRL16
generic (
INIT : bit_vector := X"0000"
);
port (
Q : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
-- component srl16 port (
-- a0 : in std_logic;
-- a1 : in std_logic;
-- a2 : in std_logic;
-- a3 : in std_logic;
-- clk : in std_logic;
-- d : in std_logic;
-- q : out std_logic);
-- end component srl16;
-- signali
signal rst_s : std_logic; -- invertovani ulazni reset, povezuje se na dcm, sluzi za resetovanje dcm-a
signal clk_s : std_logic; -- izlazni takt iz dcm-a
signal locked_s : std_logic; -- signal locked iz dcm-a
signal locked_del_s : std_logic; -- zakasnjeni signal locked iz dcm-a
signal locked_del_reg_r : std_logic; -- registrovan zakasnjeni signal locked iz dcm-a
begin
rst_s <= NOT rst_n_i;
SRL16_inst:SRL16 PORT MAP(
CLK => clk_s, -- Clock input
D => locked_s, -- SRL data input
A0 => '1', -- Select[0] input
A1 => '1', -- Select[1] input
A2 => '1', -- Select[2] input
A3 => '1', -- Select[3] input
Q => locked_del_s -- SRL data output
);
process (clk_s)
begin
if (clk_s'event and clk_s='1') then
if ( rst_n_i = '0' ) then
locked_del_reg_r <='0';
else
locked_del_reg_r <= locked_del_s;
end if;
end if;
end process;
vga_rst_n_o <= locked_del_reg_r;
-- povezivanje sa vga_sync modulom
vga_sync_i:vga_sync
generic map(
HORIZONTAL_RES => H_RES,
VERTICAL_RES => V_RES
)
port map(
clk_i => clk_s,
rst_n_i => locked_del_reg_r,
--
direct_mode_i => direct_mode_i,
dir_red_i => dir_red_i,
dir_green_i => dir_green_i,
dir_blue_i => dir_blue_i,
show_frame_i => show_frame_i,
active_pixel_i => active_pixel_i,
foreground_color_i => foreground_color_i,
background_color_i => background_color_i,
frame_color_i => frame_color_i,
red_o => red_o,
green_o => green_o,
blue_o => blue_o,
horiz_sync_o => hsync_o,
vert_sync_o => vsync_o,
pixel_row_o => pixel_row_o,
pixel_column_o => pixel_column_o,
psave_o => psave_o,
blank_o => blank_o,
pix_clk_o => vga_pix_clk_o,
sync_o => sync_o
);
-- u zavisnosti od prametra resolution_type se vrsi instanciranje komponenti (DCM)
res_0: if ( RESOLUTION_TYPE = 0) generate
dcm25_i : dcm25mhz port map(
clk_in1 => clk_i,
clk_out1 => clk_s,
reset => rst_s,
locked => locked_s
);
end generate res_0;
res_1: if ( RESOLUTION_TYPE = 1 ) generate
dcm25_i : dcm25mhz port map(
clk_in1 => clk_i,
clk_out1 => clk_s,
reset => rst_s,
locked => locked_s
);
end generate res_1;
res_2: if ( RESOLUTION_TYPE = 2 ) generate
dcm50_i : dcm50mhz port map(
clk_in1 => clk_i,
clk_out1 => clk_s,
reset => rst_s,
locked => locked_s
);
end generate res_2;
res_3: if ( RESOLUTION_TYPE = 3 ) generate
dcm75_i : dcm75mhz port map(
clk_in1 => clk_i,
clk_out1 => clk_s,
reset => rst_s,
locked => locked_s
);
end generate res_3;
res_4: if ( RESOLUTION_TYPE = 4 ) generate
dcm108_i : dcm108mhz port map(
clk_in1 => clk_i,
clk_out1 => clk_s,
reset => rst_s,
locked => locked_s
);
end generate res_4;
res_5: if ( RESOLUTION_TYPE = 5 ) generate
dcm108_i : dcm108mhz port map(
clk_in1 => clk_i,
clk_out1 => clk_s,
reset => rst_s,
locked => locked_s
);
end generate res_5;
END rtl; | mit | f876b641d6de420b2a37b82dc6bac405 | 0.45872 | 3.475259 | false | false | false | false |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/syn/vhdl/sin_taylor_seriesdEe.vhd | 4 | 3,086 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity sin_taylor_seriesdEe is
generic (
ID : integer := 7;
NUM_STAGE : integer := 5;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of sin_taylor_seriesdEe is
--------------------- Component ---------------------
component sin_taylor_series_ap_dadd_3_full_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
sin_taylor_series_ap_dadd_3_full_dsp_64_u : component sin_taylor_series_ap_dadd_3_full_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| mit | c1b85eb543ca3d514a6541b8e392395a | 0.480881 | 3.67381 | false | false | false | false |
freecores/lq057q3dc02 | design/hsyncx_control.vhd | 1 | 6,094 | ------------------------------------------------------------------------------
-- Copyright (C) 2007 Jonathon W. Donaldson
-- jwdonal a t opencores DOT org
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
------------------------------------------------------------------------------
--
-- $Id: hsyncx_control.vhd,v 1.1 2008-11-07 00:48:12 jwdonal Exp $
--
-- Description:
-- This file controls the HSYNCx signal. The HSYNCx state machine is
-- very simplistic since the current state is only dependent on the number
-- of LCD clocks that have occurred. It has no other dependencies whatsoever!
-- However, all other controllers (i.e. VSYNCx, ENAB, PIX_gen) are all dependent
-- upon HSYNCx.
--
-- Notes: that even though VSYNCx controls the start of a frame
-- you cannot simply disable HSYNCx cycling once the data has been shifted
-- into the LCD. This is b/c there is a MAX cycle time spec in the datasheet
-- of 450 clocks! It is simplest to just leave HSYNCx running at all times
-- no matter what.
--
-- Structure:
-- - xupv2p.ucf
-- - components.vhd
-- - lq057q3dc02_tb.vhd
-- - lq057q3dc02.vhd
-- - dcm_sys_to_lcd.xaw
-- - video_controller.vhd
-- - enab_control.vhd
-- - hsyncx_control.vhd
-- - vsyncx_control.vhd
-- - clk_lcd_cyc_cntr.vhd
-- - image_gen_bram.vhd
-- - image_gen_bram_red.xco
-- - image_gen_bram_green.xco
-- - image_gen_bram_blue.xco
--
------------------------------------------------------------------------------
--
-- Naming Conventions:
-- active low signals "*x"
-- clock signal "CLK_*"
-- reset signal "RST"
-- generic/constant "C_*"
-- user defined type "TYPE_*"
-- state machine next state "*_ns"
-- state machine current state "*_cs""
-- pipelined signals "*_d#"
-- register delay signals "*_p#"
-- signal "*_sig"
-- variable "*_var"
-- storage register "*_reg"
-- clock enable signals "*_ce"
-- internal version of output port used as connecting wire "*_wire"
-- input/output port "ALL_CAPS"
-- process "*_PROC"
--
------------------------------------------------------------------------------
--////////////////////--
-- LIBRARY INCLUSIONS --
--////////////////////--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--////////////////////--
-- ENTITY DECLARATION --
--////////////////////--
ENTITY hsyncx_control IS
generic (
C_HSYNC_TH,
C_HSYNC_THP,
C_NUM_CLKS_WIDTH : POSITIVE
);
port (
RSTx,
CLK_LCD : IN std_logic;
HSYNCx : OUT std_logic
);
END ENTITY hsyncx_control;
--////////////////////////--
-- ARCHITECTURE OF ENTITY --
--////////////////////////--
ARCHITECTURE hsyncx_control_arch OF hsyncx_control IS
signal num_hsyncx_clks_reg : std_logic_vector(C_NUM_CLKS_WIDTH-1 downto 0) := (others => '0');
begin
------------------------------------------------------------------
-- Process Description:
-- This process enables or disables the HSYNCx port depending
-- upon the number of clocks that have passed (num_hsyncx_clks_reg)
-- relative to C_HSYNC_THP.
--
-- Inputs:
-- RSTx
-- CLK_LCD
--
-- Outputs:
-- HSYNCx
--
-- Notes:
-- N/A
------------------------------------------------------------------
HSYNCx_cntrl_PROC : process( RSTx, CLK_LCD )
begin
if( RSTx = '0' ) then
HSYNCx <= '1';
elsif( CLK_LCD'event and CLK_LCD = '1' ) then
if( num_hsyncx_clks_reg < C_HSYNC_THP ) then
HSYNCx <= '0';
else
HSYNCx <= '1';
end if;
end if;
end process HSYNCx_cntrl_PROC;
------------------------------------------------------------------
-- Process Description:
-- This process controls the num_hsyncx_clks_reg counter
-- and resets it when it has reached the defined C_HSYNC_TH
-- parameter.
--
-- Inputs:
-- RSTx
-- CLK_LCD
--
-- Outputs:
-- num_hsyncx_clks_reg
--
-- Notes:
-- N/A
------------------------------------------------------------------
HSYNCx_CLK_LCD_Cntr_PROC : process( RSTx, CLK_LCD )
begin
if( RSTx = '0' ) then
num_hsyncx_clks_reg <= (others => '0');
elsif( CLK_LCD'event and CLK_LCD = '1' ) then
if( num_hsyncx_clks_reg = C_HSYNC_TH - 1 ) then -- 0 to (TH - 1) = TH clocks!
num_hsyncx_clks_reg <= (others => '0'); -- a full HSYNC cycle has completed. START OVER!
else
num_hsyncx_clks_reg <= num_hsyncx_clks_reg + 1; -- keep counting until we have reached a full HSYNC cycle
end if;
end if;
end process HSYNCx_CLK_LCD_Cntr_PROC;
END ARCHITECTURE hsyncx_control_arch;
| gpl-2.0 | 6ece6a40be918e855d9ed31d65216f92 | 0.478996 | 4.137135 | false | false | false | false |
benjmarshall/hls_scratchpad | hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/.autopilot/db/ip_tmp/prjsrcs/sources_1/ip/sin_taylor_series_ap_sitodp_4_no_dsp_32/hdl/xbip_bram18k_v3_0_vh_rfs.vhd | 20 | 103,154 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
AbrLtZEWaMZ9QRIEqn+KbGJaY9tnAHwhbFbsPC7WH49ehpa1EbqXv+qkeNRGupFwZ63XKanLVUyO
My0fDcdlyQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
jBjvZpZ5ZMxrEO8+CEfz6CEl8aMhkYM5vXXCdl+QFohneB/4ao6UdzksCSxNPxkQX54YmGSOciXP
wgiPEkvihckzTQ7V+IwmdcU3758CZsJi1jYV4WKld6YxfbWBrziJy4pEooel9pwm0aG1jMx1yNUM
erFXjNZfwKELIgXdp9g=
`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
bNlKYiiGIQP+R/ChMF9YxWObkJMdPWBzZKUDypAuNCvFSKj2ODeFkzLXYHokfw+rz7RZe5YojYmq
4UkICxShbV1k/N1YYli9QKFi7npsW0xHaRa8L0tSoNNqAKETg1msjVmjBV5kKgQ78l19v/4te7qL
zUqdthBriU3NcZYre5k=
`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
0gJe90X6qrVRqoGU7iK/i5s05zq/0GlJ22Kt2H/04aXbES5oZ4I0aGRfiLSYUCL8istn1JleJ/n3
1/LRSIHwjesRoSy/6j9iedPDLLSSnKq+N+ZcvCJl8gg/L6B9ChU+h5YNE7HqJVfqJzqKWKPqsHB4
WVtjQ/Uh+QwxJp4Q/GXnPw1qlnDs2s6lJ8EK8000R7Any16QZ06T5S1IW5s5v9bKhWJj2Oj7lmWo
6QSr9mTUFxCIV/m+pXzsIOsSgFWqsBmD8jksQw5AorgxI1HaqEa3+sl/imtv2p//6lwEVtz8coiR
PUlfIUpZ3ecBYh1Zuc/GrakwiRgEs/Yjfe+jCA==
`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ux0aTH3zrSOSGrjxNBhNJ8nXWhxNzkLj/DcKiIgChJ1nxm8i4YMzp0L+VdbHtn6L3ZPNF7NTEh1P
v7Gcx16JuF2FM4sw/t6m+FCjX3oHl0zUFDs/HfDB1IEXz+2hsgoR9SYF+bXbSth9Ql5SVw6WlbpS
yFwlhS2eW7RGdfH7yFg8yRwWXcYySMv+L+udV6VzSwe0SODgbmC4o26VRMdm0RBQjLnYxl3eT+4N
Qf9DbWnbFLLU2LtQWORMV3hNidJEmt4J99c08slF3izsh110Cv87/wiU6Xuvi2AB6jI3wVkno8/h
1xSxQBnRHm/fJHMh/8PrydoVk8qMhMXs9UM3dA==
`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
A3eq7CQ1ZEC2Oz4Co0wE9eavdVVL5N2w7vnxu/t08WjNVvgkDcorbVB3GWcUKigHFQo0FHxElw0D
PA15/K+npi+dagAdVUmv5cfV+KYrdhCLG+Kvl0Tcm6fhXM4RH49frRlov9a41BctZWlMEXzlO2Ei
69nxF8+cDN/RPLjSUoKp8oVTX2g6+udi83fdCBYaBZQYCaaDSNeGqephcoL2zlXyK7vU9KpsDUWJ
oZshHV12Yw5hL+4YuSmKv1aODQadN1UJ8qyFc0vRYTAqwP+hcDUwxiR48olGBo7U7czJnFk4AkkD
qULDB9rPKRIK3YJacz6Pp3GAHUDGm2JO78Eg8A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 74224)
`protect data_block
JcYdUx53b3OsTtOdv/P3/dHcfx3utNQitl84Eb3aQ6aN2AhKiDHBCYuvObX/v/9/q30o29Voi9Xv
1eu+5HrxgmBEFCpVYOVqTx+/1TnGsOn7DKuzvOHcne9bSxaTDrHQUCa38xlkHitY67JkqOSIhVm4
jpO7JF5H+JCbmXDt6F2T2wcpFyMe6Oyq6RJfEQlANaFqDnOQOn74eKDH4FfNR3DAsyf+4EzHf5OG
TW+7XXmSI6vfomJkezPGmHNVoROjvgFnK7TnF0VmsgNYiKlql/PnEKKsUxo7PMuYq6GHoxcRo6tI
+AJMZXAcc5avne6SU/2mOc1O1rYlDfuMOYM72e7no1V5trXotFkDNz5Yw9t1TNO5PzYih/V3YVbU
NDBobDLVy/wQ7ecc0PsBimCh2Y7dqxU/EZO5RSJamz23VZJzVUVgJ45yBITzYoilSrt0WNdaFHyC
PWPFiPnYKP0yDw05pHULxNgTnxK3YRDelWlT8Le5QF60m/HLUi8Nyi4fLPTjArMLSc5DKmg658jh
JSjyTrQq++qYQaFFjKBUDtVvAWZYVhPnCexdXjRceDsgeTaL1yHhb8dS3xjv6QOjRzHBL3HR2Ob5
H+AbHQEQSXdGVxRnFCXi/TKUvtom8R7+JjrA+0H8CcmsD19UbQmxBAIgVidUDxKPApBiSOboEK1x
FB7wxHjCEI+8HPUeIwoxSg1FWY9CWrNhv4GbD+j0JemUcvG9HF+3zIwWbp/5UG1Z4uD4VYnIGsT7
ozoOFMVqAbZ9MVvvKWapv0P5mEIR6VlYk3l75W/7tanWiiOn2mFXHWzb40Nep2bXDj+PtAa317DY
eJIwtVGdN/D22e6H24LqEMCT5OepE3aFof4S5dNwpe/x93UfOQs30Ddd+SejlVq1yxXLn0H6PsBG
2LJDA1F5NhqqlcVCkAuKwjG2QTvH5xG2s2mBjJsZDcB5mVc2E341U9VvVXgaof5srM2G8VPHbjwv
DXh5h2kfGC+1flf2tSWIBfCB9zePvwkF/0HWgEUaLfu9AKO9sJBs+saKvXtVjYY3AmDruCCXM26z
hl4STPxaAahx5qIMIXOmXmFBD9wypKP7t90uopZxOSL37I7VO78QjxQB0+h89IrOPr/h3l7Stls3
ewOcb6q5Gu0IOyJEW7lb+6eXgSWd6x0g3hzg/N/0fHiWVO+zcwfulD3tlAEoE9KyD4i0vdFlepNu
nehaW4Kl/Hhl/1NzQ/03nZP9nkSMADlhZm6pW4XVN1+sZ2EXsC3fe1zc08URdBUVJy52cj/GAK5+
2r2x64XO8C9VxmE1bQzv8MFRwuIYwXfn5XQLCu7rRvRxHn1nhqdbNOfyQkaftCvt6pn3YYMqCEsh
NaCh/3weMZZ4R+2N4RQjrFQJ0LGf6cr9DluL4GBsTewvbZWsSk1RPYOSofv5WBejf1lv4vjZeYKx
RT0N6mYldxbDlWR3AdlUyhsionLdPrjCVil218uZBhEBmIUJjEj+IIixWvDe9zXMdMXAfVeqpZe5
iqQSeghvfFX5u+6aI2+Ysjs6Ee6x2Z4Sl4txYDlqsF71hPL2hXSc6O6Lu6rePadCuS7gF4Rym8ap
yTKLTCVQAgHEZym5o0HsXcbzF/5aPPlp31wgnRZmfNLo2MAbQRLWMxImz74O29tn8MGcexq3D763
RrcOOFbske3p1O7voWsQMf3AsMCkdnbqqLGvM/KVFvjqoISK583P/ZBvCj/dKJWuQjiHORGHhex+
CJk6OvfiOuxlB11yDfvQf9E/gaw2yiIbz0M7scZ69+/8as+HhFR3umpKPNlaPOvlqBl73MtouusL
kxQKrCgQpSj7Qz9TERJ471PsJouLReRBseMZ5wZBc9oD/lblzy0p0qnJaa7AAmUfPxj6GfEm2BtD
Ltq3GUYuAqcA5UHCxOS7a4jFsBN3Em6nYBPNTjIQ1GoTDASpjgEbjJ94V8PqXr46HFPrZbhAJoh6
BC7jmwzTPL1boaxSsIHZiq5XkWjiG0Fl2kMRo9pnxn2Djx1GRrzI9JCNWjeGEje8mNA7/sMq2xGf
JoX60sufhWSY6pdJOLeF5ykh3P46LEqWul5krASGOygQ8jsElx0mqMqjwb+rcDi+Bjvk8Mpz+TMB
uvf2Kp7Y/jjNDWbMbS362U1Rz1ik69PIdnDDFhoPs6s+CW6/XvFssTPUPaudKJ9nNu0oEDYW7cjn
dgkTk8++gdo8oLTSQtn/RF2U4FWmN2FPMb9oDXTciVWpMl+r7AfNJpuQ/2qFis4h+iRY615JsAJ7
NrGL/DTL4CzkpsLzb44Im1Le6aGOw6z5DZBueGX2rWkGPbDzW7IdyY0X+JRZlgLcNV0VUYOjrg1i
Q9UCKpY7g3KEHrFiBjrZkPVrmQQWHqhyiTEAjTDTMgaxk5M5wWGtMAe9erd1WbNWN877pjT6GkKD
oR2tonp7V0nHHp2Y9wkittxj4vvtES4nMKMle3rQNn7xz3s5/5wYLOcyKn+J9FybgXezdTbch+3d
nnmF+yZPBt4R71KvlR+NWPI2QTnnFME2T0xXQOpkX9Rm7meHqjpI6cUHaDWKNDxSbZwH7ABw2MZQ
JAFoCu4cHJXWp9PzgxPtuaDrEgxrisO+kyIDzYu0bhr0sE1euNGSHpE7jR2flPgvS3d8F6mzkSsG
LrhGYr5DYGHY3XyRT9mbTgCpgq9+vDOAHnOPh+s5IK7xC2BcD/aL5NLUWbvxtaAjHPhAVXoJdwup
RK3PBpnBswLbjodqVTjZaL4FH79yg8rOmiOGwbOcEaU1+7vhBSX9+Dk6xqZontADrIkL/mI6/lqc
3Ojb8VdJOdxhWKZ0w53OFUYxCLecLiCeye9ZFo6Uh6ZncDqgz3jJFTXhS0tH1j5aHfXiImxrPp4I
/Qmpiw0ZKIaqkGBKYY9368wMcMQNLfEms1B0JJsmahj1namwvs5DE8cHOO1LlHvPOiPm/qFRWTsp
YULmolXqQN3/c/nT2N5bOilFSAj+w0cMfxlWIsnGtGt6x59GN0AsG8PvKo30zEsrjlGc5gii/dwv
6XUuMnvKl+CoOytiFqMjMFV2IaP42joEd4iocd8r/iIOf6IYliossSyQRPFgyMTvcEpKf/AMNPN4
AtaJ8dUn630dEokCmuq1ydM51QFUmf28+9Hy7V7sBhKaMz0J48hve1vluXF+5yy/IpIO+KRooQYO
V0mXcy1Y/RCsmzVk6NKI70DO7/CeSJbZVMig7igFkjxDoi2NzqRTkpd4zAjDpUnIwfjnXZBhtraG
VjPyVRAydV231L3nsz86ywAEQwWGBC7je45ybk7MjxHAN6D/lieDBBVyq2DVXo3qTL7bhVylE4CW
uWfebqqYrXBCii7/pXCvLhvW3SCziIQc8S8wqpaq+J3BoH/fnmtv+53dEN2zhD2Jrki5jpxVMNWH
SCaBDh2r0jwRJ4zkidB+kCuNyteD9V6rH5a7BbKEw/PwqFZB5vQScCy2rz8LJ4lMvDcl937sCcXW
cpcm21xpoSSrEibBkSeZvqz2EdAvqiAHGMzjdDbfQXMnW/sivNDSxFCxvXndmzYZwvOUArLN2t0R
aQZwzyfYWHVx3+rGhSePGi/njGN9N6sBQA9Jl8EMOwt/2rTVzvgNamWDldYkkwTKdWN/pR9tt7J9
y6YlakfarE3ffId0LW7zpmneR0naXLxJBPT9GqkXEy5aYx2UzAm50SWVM2Pbm8i/s7JQDfBSog/J
O44R/R7AEHGp5iIRokL/fQqohmHLNJmc1iQ3Ne7fAXlOH5MOgBlbbZyTy4PQxZ+1dJLhSHy7aHoT
BcQeS5aAZrRMtoGRVL9w8dofqnynherR7FMfx3nLQlUZqgKvuzXIRHZEEH+2gZooyUn8c6z8r9/W
bbz3HVmF+J5ytAYVq6TAm5Jp6bwZ+YJRaNXxiaqQTWLYDeyamHQeZ4PVMP7Tel0iibLAKkHZ/yTM
L1cnxFm7TXC470HHRqomxUoDy7YMsBvZdPOwL4zTCDupNCS51ljfcwj73VPL+deuBxkEeMlh1npP
OVNqxyQ2K3WUbFFMZaCcf9NI+db6FQAm//ghHe1mIOJHwUmAUwnAOoYKeysyzLQiWF66UuQ0vHfe
oeeb6X7UmQyIitKPXi9/8vZo1QMrU3bKeUOfv/Phvaz2ykHcnLaexeXHY0odDTeA/wbmLLMbnU1Z
F14963JOnWa8EI8xVIBOVCndXGs7dHcGUBecRU6D27/gP+MIcbUyu+MomX5Edpzw/RlQMeTRUv+X
gVCepP5hOwpqNENL8PQoEd1+l3QN+CmDrpqxKuDbMruCH1klQGi2KyURrk0xW3tvRx78BzADC6z/
e4krry4RIbgpjKpCMZ36KJhZhOJ4XrMNQOASJHrs/tvs4uubgKfELrt5ffESa0A8mbpQBU4diU/O
jEtRKd4epHxn41mOiRYaHTqpSDWcwv6ETHyqceJCAzmPi5GhHZ0aUYiz3CIV7bOvynVTC6iTkNvY
Fjc16r6Y1AF4aON5OX0kVZO4WQCBVK/j9xz+kFdZtK0WUb96KOXdn8+99oQp/XiLXzlmFCTVa1hk
YeOIbueyaNdKmfjdONFE0ucCtf7MOuHzR7+0E7n9J1cqzYbsW6LMHq0kqwSrE3z80zKDhaPL3ZST
V89l/yh7jw5kkbSnMy0QJLDrU+9YWKdtI2UHS5hLThDdgcMhLv8XU0W81bhsd53nwoI/xPyUKmee
lueOrrko18nZgmGewHoRSJErs+j48xiYcWr0OGSVq1E/EXQp/I0rnG26R6ZMDUS1UlC0M+yzSUKC
KeNa0JnstdmEiAcc2NbqwAkyf6zikHbOmZu7fq0kHO92qH1uIsXGUtn1PPV//e6upK0jNPwS4JG6
W+fAmEd5Wz/lmsUiSgf9YXz44Z2i5CbWP2RuFFTBNbyD9LFni/ox6MuVOkBxtuFhmstwNT9gqMEd
lDbiRGAzlHSBvDfYmvS6pt8YtlIsL4v2RdpKzxu9okBFcaL4dSPCNv9Nde8Cr8h7DgZ5ohreqfr9
r+hYLwBRTUd7nyROUSNYtamBNa8gFFkrWX4gEkuCTz4RW9i9sIVfKRQJ6QN6IticXRe5Ik1GzcO/
AC+Wv6GYuGFVlU5ymWRhL//1GQ0aspVTyq27DhWucO1AQmEH2Le4QTUJzg1zzS2qAIB0TN1lfzRV
qz8RrNO37JkB0SfFFeqMRwoEpRkx6p41enKF7KhvYyLK439yo37yRaQtdIgoWEjrGq743/rj3eMa
XfbwzE1IBPNONtBtmfAm8RhCZDJyGluA7z56GXCnPdm9fNReTlz7L4m2BfO8oaUUr1WevXuYAF/Q
HrxDyxC6BKRD6JWGGNRN6x03NgBssWWLrfVqn4lX85iBN3A6pug+7r6Y5ZNkfKU8FVrbuOqsHlBI
PAaZ0qYincGQoNZs604N10cwNrizRdHbbygRGdqZrrjOX0y788Fa7UrL9KR2mtaO4x+emY/LamW+
/GUGaVhUYUu4SP0mGdFvy9IBl7ORg9VWvzGPQArn2YJwA+a6byIv3fJkkn09rPQxk2EzeSJ7VdO0
2qT/qYJhZoOb0fBEESWBEAGYed+4pgpc/xPo6vdGPYRmxQOcevPZFCuS9f12/LBx976Lq5E4GdKE
BnfH9oHmho57b4VcG6afOLk4VfiqgDpH0oe8+09JtJvIXfzbAHZuNc+OPKf1cgMv7jXQjMhMwkzW
8EA+ZRCMwXy7HedH0b7Lriy/zl5fVlMDRnzmi9cQbE6FPQ8KWLfYNK7tU4xsTaKOHOLDvmuGVpTH
ePdwPKG+N3CqkoXNTM2mfLtow7XbNKflv8klPybOpGPRLXBNlQoXyz2oxIRPAPtIHp1EBciJSDaW
nlm+7Ykx9BI4mAecCUSiyCUGdOhzIA+myCSX02+Q5R8U/4PSFhNgbZo0PVJSs7xBdgq23eVrYHPl
EvhwBx9wyxbasow6R6plTcXdLVyxaVVNat98d77Yi67juUARbex2GWyi/VakJtF47wRT0izyf/fy
B601vCy+lGibHhtljMWAm59ahjCseUxcXcY2mif00YPlwzzgR6mMzEBC97KyNB2bvknFAvEXENP3
1UqCTPvZFCzxiiO0TqRi2Vu7SPI7RKcJhzh2gZSXBbHjUBtKheRR7HKqdQBYG99XmSWwg+DOfq0B
xPCoFTLUzkSuRQl3CWs1gSCw4WaDaN8INIFw5NX4CPiQtmu72WOpCEjqaZOLS+UFqQX5i2Z5lWMF
KMBLc/2dQt5mw0aXUCDvBTgkpZJV7/hejuiGISy5l3doCfteWxAplUsqitu+ykMLdMjqIXuAyFLq
ETohUWC+tHJ+VY0kNxhk/1uSSlzx12cvV/z9lic18VYylN6pzktvG+jRrhBVo73eIDgIIv14BPrw
I+lptJAlOlGsafAJPMuYvP9Fw5WYky2Y1AqW1VQ7a/TfAHjn01q02r2Db/DtzJQ8DRnVEsNr1rnF
boJhSaFcZbmi/Kx4/wlSQBpqA+AJWAS1SP3eDPdv9TA112Oa22AUIQvIalRfsM7LxvT8eCgi+jy6
XJ1azPffzo0+yjdl1ZT4r4RQ8TB4x2g+RAJNx05n1M5fXymF2Y/YR5X17uGfyQC9zuB7kXZACMFQ
D+x6zkLjhZankOAqjdTeikgRRitfIf0urJf9MgP/anRKHIUiG045w6kykistBjUIeQ3XmRT6Xll8
KeE+lRMdmwh5fpGykkGVqdOG4syihTbZ48iNXfpv57sq3D7V0bWkIRAh/pi51PQXWQL06zUeO7r/
DnqH16ELZfkt9Y9+cxFiHNVASWV9LH+ytec/7jJilZovfl+OMm5syDPatNIjxS9KkAVITSJTo5lO
J2usU4984wQ3QRmJW5QHCj1tl1P7E6aVVxBnNvUE7+LbULBIM8hwbcwsnYR2eGZrV+krufP78VXy
b0YVkqUVqu6QPS6AlfPLtllcBMKY7o/ahkMR0mPLUqwUTOt54NFhkGz+qcX6B+d0Via9QyD74ira
CU6sVmDJkm7Ce5UkQz8cYFZRQ/w2LrT2Ed4/zV0s44qhChpbDKHN/XLpG2k8PWf3IDInJpR0J/HR
NCkInRjOI5skGW48TGGODnJpfi1vUawK8EZW4fpSlSQO2GYUaL1YmiyECRD7EfD/ag/pW5ecJHmt
UNqo676wBpztAKd5JcFwFnNLA+WXgotD1W4EbO//gXt/rEJ1z0S/L0CDCtVyJK0E4qJ9CQE8NxJp
wxgdNgL+Iw3C8MRK6ty/XYIeFSvudQ+BWxBp5ZVdnBYAGzEuTxES5650IFL17dwAGQ+aTywCXI6P
adhoH8ADojBD9cN8qOaBoLI+xOhY7BFeCrsdRZELLmDYHNgSBR7P/iMoewh7mHqVkzdXGq0V18PM
8fR2kB8odtL1WYIzgeoJeo4lNfL30glLNQhgEQOa/eaOJnS8cZHacut338uG6+8Fs2FEjy+aFHJY
ETIWZn+hnhvFaZLhTyqQM9URooPYhJ5Czpj/l2RvPed63LMNULVRalShMU9+jNbPxeYxYOTzQ/rB
f9krblIuZE3TZYYPNhwldp4cj0ggSkjdf28lF3219361YkXf9J7ghLDCxBk/WzcTJlWHmRhp/np8
mWRyZsmsKoBzBdCamBk0p4QkIpJJRvIZpc5+Sso/OffOtwyXjjtr4hYCsIXWPRAz8EjxUTshP2QR
aSoKIchtBRHpA02q1SEmWRSs7OMDm8uXxgN/VaXhaPa6wCqbKDL0fk8tZaP3xxSWKU4vuqLutX9h
Dnm8xXrdk/o3Kvy61T8s3WFtVYxP0Q/o0vvlZ1Hnrobw7HxUxuneE/bN1QDXzGVTu0UrlGYd7Bpx
qtkkAr//N5c4wlMGrzT8HYPzYKLG6fpv3sVxoRPZNmD3Bxc8I0+/f4F+Q87NIisF/zU0qALx957A
LufULMilHM1kCVN4BY7Q+LB3Pdn3M/bZb+n3vzJ5dqI8PXZs1sm2Ryfm672gKiOKHTghStPmrMzY
5MLrmhRn7QFHYv6u1aQ/9ETQDgaLrF7RGwoyVk4x1cdlw+VvPLV7BXjUjPsI4e594MK22t2/QiVF
tspBL8yFduk1taZhJ7PDwB+bm7xTWUWC417C50aOqQ5H5A/F2m7faSP7g8kRlqytknbkL5pRol06
MeBV1jyUz6DuDyf2plkgn/DDOIxUdOIw4/YyJv1VZ2emWnkTKlEh5lCkVXy9H5mYTKWilBQ9zBAo
lUsNnDI8aD4S3z36IW7T5AuD+NQiPyg78T1QiwpUuq9hr/2ocrU4vhexSz+cP6diumwEQnzs97R5
p379+2H71G5pQQEM+KJiB3nvMG+d7EqTDH6U+iLtCpvbqYCscGkAvGQ2D/uwrK1I0xFQ/5HM7QPS
zUTJibf5t/XIH4mvjKmGobAbqZkRmPxfCdTk76wwpy8tFca2/5yLehDfE773G1apqZXK6DuDySNo
4RzwtVJLKjuVl+wBts4y3dqY647qoKr1lWi0Nyl1KIH/Cn3Efv5/L1XjjGj0L9UxsXpxNcQbrZoS
tbnc6s3M9h1YhYkLknJggmZ8y7elf5iKpzrBvqdeltXAZ5SD3xr21im5/RCxsOe+JA9ORkzw2C70
eAsPcBt5A0WqXqSQ2xbvPOXHrzgjrLlU+TXmAoCFM1i1El0Y4ylbdaLusiLdAM4uwsPuc5UCxoy0
ljVYY/RFA7wMbK/JaiKALb8gUpdmGTs1wfJgxKIwAM8yZNS1klu5fJ1HY7JFsqF62DJcivymTMnM
nf3gCJ5vfg+LoAStQKYKCgP4Xv/jkPavOJ/SL/cEclAum2Ykz/HmFCBIC+bd8u7yT7W5SePoxJEw
KEgCpNPn27kQTJyDgYWF4hHNLKf2E7L7AR5IHw2c49E00gwuW1WuISObl0c5aZgltrb60GsYxvEC
knKA1oD8BAUfNFMGNa66ej7jRlrbbzMY2L9hdHMEA+p3VLEx8Au9b3I19PjOUzPa1FEeFY7b3tp4
wgDW8yOEqcLW1nmz/8mDKQUtm9MM9fAVi5DsVNfKoRhf6uL+5qK+u0/2mHJu6HMSoSBzfpWpZVNB
i+otpbVNBOrkX3nKfwMPhmFjfkJ0nQ81rcFeO2QUUC8LGKal/1Wsyw9eIVanJt8d4u3rweSnd8/b
eB4KYEaa6pIruitbg7RmnZOS8CSb79Ut8NMGoiOl7LT3kQnO7/4fgg5VNeVCHobiXVCEiXEQWrSb
XfImRKyx8+zu5otLSggxzNiym9h2v8E9ivBQsbWTooJjX7+2poHqVzyVTn4HwbKcAksTBwWPcpJz
GYEH1RIvBJZ+iqX4Z+9GsxKOs/J/FZMwFcaNZM/BvHGNfgQzN8grdFihcBaiiTZFf3CvN935mvSd
wwOsoLgCFZsL75LDt1vmXHytDMPpPTQ0cDv2U6baB74MBU1aFp4auUJ1gg9INJZswLRqEPxjhxT7
pvqyXzxEugYYb08I9PIKRTa9WsC1ZU50HEcNzYH7YB5dMbYTVVlQlIi9R9AnN697NzQLc4nOImjK
mUezr2B3YOd3qvT8SpVISiZb5PTFIrqUi/SCsQNuQwWZZa/TD8BjsLRxARC4twUHG1XrBIVR2gpW
8pFuVJZ4+5XJZcZqu7np+fxFzGx279Re+CRJ6OzDed6LvKJoz3QHpJsarYpUJN/ZREIuyLDpPsDO
ju/nMmkkhGuBK2E/pLNJTnSrNIirAlWWU3pEyOTM+kv/3uR3mqrAPPXMkHHaWe33GKulRioUI+jW
syslOFL77lyYEc8gULqjJkGD1kdEs+aXCjG/1D5RrxMQ+sRWLnyxWYKuCQdk/3emZ19XI0KDph/7
p23cMw1QHvd7vJYhcF041ZaoDhoeEaIJ8XmYgmNI9PUc2U3EiwV31U/uBwDCpoYGXGyojA19pwt8
ZNHUMPmI9pSVYYY2NvpsBuX6+koHR4SYS1YiXSGo/CLHKYWoKE/swVSeR9R2J3X5tDHa9e464wgT
aUd8ArB5HWs6Mxgmi+eglAVeIwYmMODHD/0ERj9LHA5AOBeeenieACCywwu3YaHgqUVLirc0b3od
QbpSiZdV72iCzUxKiJF/nnCPPeL4WmZ9dggPJuWSa4UiiRAkc22NHu9ZbuATZDJJK1xY/KLM44c0
19d8aqVLkyYr8XJ0VxCpfQtoEgyGL9BNW+E7Y6rJbzOSC2RPNW80IrIfSQ1Jxahd8mQDBGIjgz2B
LSa/iitquayrmOMwY1NnmVve3zzW1f3WtuIWJFYIhGGnx345jyarn1vOS3Xj9p674sTITMaZiVpR
7pI3JJ9U/MWkbAjTv455xlDdsFMXDfNVs9VkRAwqaNx6KtT/VNytZqyUCaFRSDWsitwmQdr0kSif
IbwcRmuAxF1cLZgKgAg7qBKCva29KuARigz5TcIv9TDuwnFZxgC9u65AxFtNVH3RkBvD0rPD77pf
maxYisgU3WJOvCoYRg3xJ0BZ4nTGlrAS2gqqMLqWEKTNpaF3EHZHGOkADS0DXhXHqOOjz3S98dAo
6Dm9WcOvhv7d6l7JsqujYrVevdWtzFbSuJAYSaQIla/pOWRqAsr5Z+CutTwQX88MWNgT11jrOMkM
sI1ZpRGpTtisritvFIxnR/2l+sZwlW94qoj4pgIfvW6DLQ4xMKU3TSvp9OWCrYu+YLULCZbDIwVE
xIaI5OEcOAJG7r0SZtE6X12Yt74R+4hQcE1VJjRbrcQrs3v5gJ63KrDQnXGr0U/9fpm9mwxBzn9y
4U6iGmw68kCfqv94cG110M7TYvBVexdMiRYH3gE12bLE6aS6BWXq0uS/ThsucyScEGTXRQQicIAK
7IDvIbuQ69ErdJ8+JTZe8hKbfGACRHuuogoL8yxY8Qmmn3p8zSs/QxPfARNH6NRwP6xd5QTWRSU1
/6F2t+CPp6Jdge12ieWnJrYdQRPsieOL5QtMOsLTltHt/AUwRxdsG0NTvdY6sH4daZ1JrbPWQZ1e
ba8fjhsgT2uMXjiai6sM9zvbXhYvc+ekq/6EnzOJ4SYZj139ygCvK+FsLxvihrWe9wp+rhUlNkai
ZhAQ7AhJ0He2berfZrFTPCBWNpH6ey30tkTo6FzsvvCdXnqiBcUTaPc4dKyVr+WJ7S1ApSz6GKH9
MCgyAnSGAXw/J7dbl769zy+AUeTk5bjK54sD46dXM/2tRMT2UtLdA2KPHrkjq9lBh+39412Q+pyQ
mOZrpp161lq7/lVVz0nsyAl48sif1RhhAV26x9/I5vIfQ2oF+WDuBIZoggVUF2cQ5NrdW47tTzD2
0cncagjmIgdzMTSGXsgnZRW8+NV0dN4wC7PWxgySUYaIEwmWJXDa+cbnfe1vUN4XMrDHvPY2Q94g
ymEPVfCj1DPMhxsdKJteB4IvgCisPRUBAlOG5rZvhN9sV8AkokorL+2bsyq1RvyDMVAG52zGuYgs
Yk0LeDPZt26Qp/lKQlwyd7S6k/Z6l2kGfkqBAyPUSNaDdyVUUJZuRk1B0XW4FsxAMfB9SJThPrq5
bguvqBKfceLelr+Dz/qlXIam1Z0ZeGXoh/grHfJy8Z3Grh46CXKlYFAECzSn3qBmFfgNDP7IHx+X
DlAj29MklmzDJt49muk8qRTiRDBsQ6Ncre/EpqW+mgLvGWwyQS9uvaAkOSHewnijoVwQPhJUzG8g
lrryRx8V+m6sBE0N7OEiUT2FJofYL62FpV5M8RAAUzbQ1Axnz+qoy9sKUQly2sbPrdb9Cdn7KAek
p4De0gHdIeI1gfOcYC9m3IrJ+zOaarxywNN9nMptAgCmzM2MwVO+Jw+Tdd1OR/vbcIICIhIo2doV
vwN4s+HbR7n68+v/jkG+JEBoxvpPiW6uDtd2pDR5tsJqwHrQWsZ6pvJZDSUwkj4XSrCZBhhwwurz
O9A2K0VNCFfR/2YAP0GcnqKD7G0zqqfeexODeCifmWoKvryXu+BcBGnuRIpefnlhT+in8FVF1YN9
ZOYJY89AuhdE8DW3mtEFyPpyEdghzBmt0LhR5lUHj9JrY05fyD8TCV70Wg+u7W2Fe0dKLUV7Ki/+
kvPPb7V6EjWAFIk+MGOAv4o9A7SzzhWs8beqhYfAObTEmDEZqa1gKUGcPnJJo+y4qPYJplmqAbLQ
7+uxBNRjqoYYCYPhq6bdiKY+lqMWnOr8cCgdplkYZKxrbIyCFO3/8X0b4CzoumCs2fO5EsIceGQE
ImryN3EjWshlFGDnocxKObgxpsKRPoGDPVJoIhfS+8u0bA3AC4TauUsKJypkyohhsEEU+Fcir/yM
uamx3cY/LwNyOE1JqZg0fz5ZeyAxLADrLGeUtKS1IjzWTiNBXWeNeOx48kk2L8jThLBNqP+UlZYk
J6MoCz3puRlkf6pC/v1dnvJvcLK0jeR2dt9EHdz+joD7/VoGXA8CW0WjRuE9JypFb97D17ZZi9iI
4z12ubW2sLjwei6XIetG/cGRoRCmGjp0KA16L8XrrlZclGYtIE65YHw15YVdwFZWLbMTKErOXkQa
MyQbduPRSja1RMfVtN9tIg4HMXMcUZTC6+z7lKRjx922S7B0fHkAszrLZdVmhCKO8WzvTOXRG7an
QbWoRzU0hVZqj3xVe2VPBePUFEfD2nHTBNUHjl68osL5YlQpgShYk/1eojJkxtYZuOMVAiDgYfdM
l+LAphuHNK1EQjchqQRaZdV4m4M/DVakoH8f3JOi8lY6HQDeB3VPC6OMeGYTyNx/9JpvxNiY6Gd2
ck9XazVm5BRSauFViMRvGT2uy627TiKMM/JMtTKCPUkraQM9ZoNNePAVW41eze52GvjONGrXFkrk
akjotj7v3x7qG3kUQc9Rd1S8qdq1T3Pbz4V9X/lEm6i1el/NrTcVrVQWr3RCxXIGzG1brM7BH8qp
tpO4C7xfstbzSvgxVWtxSLFp9iP1QV1BP9uJ5KZ4yxtH/F8J28r5kDGgxwszNvtH4+FfS13SBKuA
Uv64P3f10hddaZJIMf33Og2tBH8QE06xOhFKOZEaig0wnI8f4UieZKZRUqmQtNEuAiGo5kVQKBSB
awFbyHqyje58KFujQxFYYOmv+5y/RcifbaDMo0rbI4cl5WYg8QQ6+mbSFfJRU/yVBjEgy4FZlRm4
0hLIJvDwRn76XySt6LRXBeDb0tCmPPZEkCSe7AnVsbG4R/UbFt2DKjKbl4URmSvqzQYeI1/fw9Yr
xRpSdi8P8CQWgbKCt45eINwGzab4sr7cSOnhHVHwMdGARVF+FSmX089gP+U+cmQK+8bWgjeucltf
89ZwZNXNSru6dM1S/KwBkBh+04Vmyln5SF/DDM3PuSXhYBl5FPRv+BxEs0AnP2+dC3Z60ytddep1
iJFCERgqzsTG/73OBNeGZi2D+hJ+Hn70qKtnJy3jtNuq7jPGgWM0ifgj4DVL78hzOb3eUPQy1M1W
vRUQruEyOmZf3FAwNpQJnKEm2Xf3BeW6ajE5VkIq0M9VDFEgtjC2wuRg7v9vc81EIIuIhQYtktCY
19Cn6E52ToW/pmHsGujHwgzVpaQsTvWiQlo9xdW/IBdKW5LlJE7KdxsCxZV46+TGokXVVuByXnab
ky7XEeBEkFwtLPxHkEcVoE0u5oAbH7StocuhSuj/45c8+lppu2csOBRjeRhNU+WP4Ca4nmWPUCTj
qQZYcYC+sXEsy5E7qFy9GvPqGtXAUx8fVsG0OCWEj+qERsXfS5gMM3HK16R6eQtKuOCeV09A3EkW
+vM9y+eNQL8dG3Fi4SuKjdD5ZyiaZT7yRw75YSy7euLpbBu9JuVj53tl/wXNVLs3r7B5w2+8KPSy
mWyVOI4FLGN9wWyy7E9bwaBw1VRmXECID8mllSc+e1W9DT4OYJE3gkfjPHeAe/eh3kb/tvb8m6zQ
QDQPrN1yHJP4CoPX+dwr7Ott2AerFjgPgMCmPgXeXe4B3d3VNctfvYVPcChKZi3OgkIWJdLjiNNm
h3TzngBkmOGbPwv100TVzJcl7gzVHi1B6DbV43IwICvL4Bv5ljKfTHch+57iXykuz9HNTUcpJEg9
l1gajgzcSNwU3jnROTUuD8KSfwUHMwQoglnunc9GQIDqQtxCqzLvGPuQf/WeHxgUHFY0OGw+/SYo
FaFBA6vX3d0T/T0GvV3GCNWQQ0/1IZ62AWedi/l8CR/IG4ymQ4q9iMQ1kWh46NY8ujo+4c3vGG9Y
rWj17IrnVuEdMvpfKBpvifAYOxTk4f90xGVgl0srnhWjFhWJCKODlxaFdvm+gSnpJAoecINNyM6X
h4xtsNbzGa77eDLiWc+r2GcafI/l+F9aTTn40OdNJl8u7lz7MG6Hj4TBgAWGXyrboeMP+Hmonwyb
wWMVRuqC2Fj/X95901o7T73hJJAOlUSWuor9ilpcIpy/bzR7Tf2KCnm/JS5X3Thd5m/KgcIzzxiP
3/gb9OHU2y0SlrGcqSDBkGTQvqVjEtav7WL0noGT3C54XiKGlIbbytZoKNLe5fbJY260WBI9EjJ+
AEkGnSzYXcsjjRv0TdedQUOCrhqFMtS4wXPQFx6M/VmBiMrsF2Uaa7nqfxaRRsyVj5ih7zAutcYc
ehrvYTJous7+AxAotI97YRYRcoweGIwywE3seKuOia1iroengMLFyb9kYZOQkMQG3/QPL+qijt7b
ipOPv2KK+aIn6XRCdgHmXOXTuP9uhPiAmYpLSyqsQsmnl5+kWGPgsig/lWB46DiJHyGlJ0/BdCwy
+Pm6mwINdDIPWqAu763b2qhTbnYdu8UYW+5m4lSWf8l+iZbZidb5XeSPg3k7IqNDKJpH8/XacAgw
G0yC6xiJe7IaoqahzZzsWswmrjLoTIhM9LbKFtQaza1Ntd8+BiAVuoYAbWbM/AnWLUXz6rqudqzq
03pICqagICTZS/0R1Z35Qpyl45SJUOh1SS6WizvdBWnTpvNUzeJt5vtCgiPxuevJNkcS3f1//UOU
PKpOowqBZH6c/vjg9u2G+0lVQc6wwDGlI62yBdejy0uIDOr72Y7e56xe+IloQAMckshvrrtEOmA6
0mKiCNdRVsoOMKH4VB8iO/0ZRtU4x/cvp5r3FYviaG5/t76Silqzz17b8u3HHVXXrTQnnaCXmQGc
qydebcQ2IcCuFInPWJmDKCVHYY2hpXgYohE6x6uN30Aoz4j+3sEpOlxq3T7OitRYUHi/KOXQQ+NN
t6Nl3/E8t+YhU921JnOWSvOFPd+LfwOBXFcqQSTfEe2rO554H9m19jMUpBGrVuXH7vePL9ibIYQy
Gy39BB05M9RCvhM1L37KTtkRfZv/M3DJ7VgyHAYW6TEFjtYA4Feut0m9fJgbyf2BhFhB/7Rs8cxB
TgjXxacFR2xRLP1T6uFkGbvCZDfllnhqqIhy9dp1gNz0XKOBwv/rQhrSfP4p1wfvapouBg01O71h
W/oCXDGmVKVFcnCxlWOdT4z03K8L8TKqnGZ2gDc2UDxfXbIFhNLM1+EUjedcf/wfyg+Iaoup9iUV
Pb8f1C31P2+d8IOmtDFW/aKLcT63oF8xgMIQ5kDNDf1cXhOAsKqahR0JGmmjinJDgQZUh/8xJSMz
8ncCzHJmJAvJR2SQc5Smowi1caGTYSrDqIPmMHWMCUSSOkhDKFhMdxz0YEsC0qleBQtyICVWm2IM
xDa6DZvDZQ4GBGuPNtBFXdTiFVKJrhpnf0heLBsAxkBuUbF0BhZLm/asrAX/emp9eFl5U/pliQQ/
be748yAL7TtinA5NoEY2gCsCPw/vpr6D1Tl8BTnUktJQfsJSseuH2gcvM+6d78Cfji/+meOLHL7m
NQO+fBrdlvmZi/Jzt+whMwM5ZhxDGgPbllaNrEg9siYK3NZCZ9IeadHUg6USFU9oyWwHrLxrDpvO
ufoh9QA94CDxoDpN9AOCBCRdbxHYvOkwIACNupqKuE7IPIM5hP1WLT2hUQIigveMYruSXIbz5cc2
lwbv5pguB9eznThFkBfoYWfpWHS6PDtf/yRqD/YsSikxSvm48M/IH1t36foasHtH8Av5maQeAWdv
WUPt8J5EpE1vq7b9/mfXiX3kFPrse31lSKOQwkxg6YdajXLYjbxokNf/JBgUfbwoS4E4oDhrocTV
SZ2BSCiYqtq9sr0eEQs4zvY5w1UR0zCp0fw6EMA/Gi+GkXyR72BjD/h9pcvElZg4VpebVZSDeDLF
0/sEiYko/lLI2J+82jyIwfdIy0wkwHUe0gsdrzlKf0Yz2NrtCMZkjjv5llJFgagcfSS5lD1mNxtS
W4KY1qkjf8BdFe4q98WFg7sbnpybNL7bTeUlFgGRZFfFKRFYOfAKqFXvv51laNJlqC1hzuLDKVl6
ZPj9EuTAvaMmRNryR6bKHC4A6GtztdvgCvK88XEiI6irfRhG07wqakIehn5Nk92iRR0e0UdMYPWR
qae9UPpViTtCyo6GYP902hPo7yvozwxtoKZvvRwNYP6fviOWHfyFvu61GJ1prsU/rmo2RAbNVWhi
yrJxtbJZuHcRV3Z7Roj9AjFWPD/CcDIo7nKmxOEJStSBXtEvAJEgGnCVzEYFNX/+PkAHxON9hdxr
smrCMa5VP+Kp7IraLz15Bl2lb29wYUo/9loS++BWMm5Z0d5kdzv4r3AOrhy7LZ26QhncntOL5kd1
CiwdMbsNkfnrwscqHi8g5s4ojWWTpskA/T4ekWj5TthdnbWy0t8KbaoWvgWBwqZr5o6v4HnPrW/J
uoXEvNZ473ASwOPEqRNqQ+SlLeVEm/aSiyi4z4xhn1CNhCik9zc/XzJfs2pb53SkondFMWGpsR4m
84GgGc5wIFoVUjcwUDclfL2xByM6MXMwKR4z1sG+dnlMZYUGB+lkwupDW5xNqdlUEoxVcajmYlDv
mrVtaeXhNAin0u6pOCPT5ofhFbyQVB9mAaAR7f/ZGIdWt43x7Pc27aX6Aa6P8c8V6lb3QJ396VNN
1u9HiN/ywU2SU2yV+7J19l2M3FW9B48g1bJgGLI6EsNXf6sLQWs94L+nZZ2yAu9f4M6MzPEF6+E+
DI9skMZfnbgz+1f0//1Bji4bVZtJWRX6Tpo7h9qFiYi3h1VMyNk3uKqGvyMvjzeW/vhVbre72xv/
umJrFxV5pAeQ5IXoLdWPl1MpvbO6+7B0aPFD3Yi8KlS+nWW/PW6RMY1IaMdhBU0g6FcpHiTEqwQH
icS3CuqvOerSkdniXboBC8llqmQlpgymLB99445lQ7LXy+6T+rxqzGG76DjV8j72+Fv+lRReSUwy
n9TX9mxrXyv0+T6eH4D3JIfKD83g2By1qAJIGo2+Z2ZlRVGBJic3HVwMbGq52wFIMM5i2UIzHgoN
Ei/VHQFLKiTGBBhEyayJwDFeu9WezVibxW0gNZXOAYVbDgltbKjwbYmclogxPm6yJAk3wj4vjwfY
aUwEx3S8sP0yySxtLwVrawhVkDi3nEB8gy8h6hRwts2W9+X9jImXQcp1kkcouPf4J2S8M8oJ31sg
Ob+he6XOCj8bQYsvR9FLmhgLQGyIOFZdsyru1T6wMqF+Y0G0JfSzpFuipfRwBP8/oAbCiq8sC6T7
U9VsHFxHXh4c8+Ozd65JWq2h6IdMizWSc3S4Zh8tyqiDgoRq1y9feRb0Im15shQs8WhGdmHwWx6U
UngO4UBkHYB6mYV/RAd7uI3/Ia78hxj5wqXMNW9rsOBisp19fk1YGuxLl9WRidJp5xs1bqv2+5ME
COvyBScinwQ5sYOG3HsUCp8xvI7IxO7YoUYnn4xNng47eL5x07DfCvN8RgiXwede068/tBXvAMbu
S+gTG5EJJnQ3/hu5NIokqwKcd41Nq+U+uEglWS/AJQ+S0TYofj9tDxZAcK/r2WZNAUVr5+6aXFz2
J/E221v964+iz1qcx/t57YTdYnxWLJeekToI/IZ7jinteFjAxadwilw2RZF/y6ZrzI9ujuOU3waA
5/ix7IfcC9rn+jtpfEw71qXrjzJvHsuAtQTAxMoAUQty5e5shU0hmRoOEYdLN9OWZmlAbh7wO3k4
FhBc6ZJiYiWjq0f1orgWRt+ilNyb/Fy4+uXe6XrvySx3mJJ5Wy8NJxgmKP/XWXAgsJfJUVYch6rD
zBrxtANsDssp2lA8IrvzCvmty3iQz3Hv3xClBdW5hJHj2hWY50gaCzIgspntTRVRO3NEtA7+7nHN
bJepMGUoRXoFq0/Cx/csKzXgIf/hddibsT3c9p3j8txs5i2y7PI9xllpXocnmVHYaSqeHJimEmeh
U+vYrW3UYGuEXYkhU3AhJ/vE/ouboLHOhPWW0pI3x47r+kqMbg99VEDpUg9+jk9La4Pwa8wtDH9d
Bt76gHiOxJgqHINu+91wqcahDkCALo4u89VudqE+8ddPLCUK8j+pqFlpHWskAiLY0vVPaJfaXWsh
JPysgyqXWcnCNA5dosPnZWKvAeUPuFxehPN9oZZGAlLVJHuAk/Y53n3OC5451k+zsqUjN6Izn11a
RRNDq17VRuWMDul8yh8ysoXtJGcNwStKmKnxki/dB+dsroBnIW1pST9UpqR97RKhbQi9EAcC7J+v
hKS1+GPPVpYP21G0BWEPLSgFNNcDOPw0t6fvu6/2hwuVe3RVWFYARNR5p0voiVXFGs2HBrm0Pu4d
ZSAu8wORtialobZun3MY9oWE94t2yCPRLCBQnjlDdms60alo1JYYB8RH4Aqleb/hl2B9mHf89mUC
ovHA0m4SgMgLBTtQfpUun/Wg1pk19oL3wBptABgQTXJXkhxNS54RLxb78KleuLZzJhqWfPt0liDk
nkwYzY61VXCWUtVTxmJT8Kyp6IANR5eOC3m6NKL6bioU+kFK/wss/jV42kdthYzrPUGnoSPhR64+
1aldq+HCfJReK0kqHDqodXrdEFPnRuwUsIRcWOP9dhnitn/gYbZedWoU/1Vv6sp9/DiABPaZWs4R
i7AmD9XTedIUW0y5Dqtwe4HQ2eoqtiD5uOiSd6iuJtMtBHE1JRY8RhkHiCj++zPGpKPh2Ftb6dKS
1PSvqnMLq04cqsTTdd7ABbhYbQOi72uwaIUtXinVfCdDnD5HBvK4FMiczAoYM8KZYTk4uk4EnFC6
4b0fG2n35x+9Gz+vWKXSvmVNaPpsJA3AlK39bDUxItaRNuHvKnUv9GjjHJyO09N+wcgK7dTDEjur
rE1+Prw+oUaJUgYsKnOCdIVrm9WEZiIy+oQzj33r7FUb5yFpedWvFD/iWiQ6fMouJMa43JqR+8zd
/7i/q8wR4rsi4qjQvkYOMX/o0HAx4VNboooRxzf9ACcjbgtOFzd7Fl/kMhprIS91hAAm0QakOo+k
jBLNVN4NZeOw0iOVUl4iOj7422aigqUk0UeK03BwrV9+9Jg5twRVJW3zj6XaVX0TA2ZtvE7FRKI7
hLzBohap7EbqZCFcJa3HrMynH16mj/E7nsbwyLlapwM85rq84bjHkKOKaEL1b7j/s6jUEiduZgEU
kLUwjrc+NcqETsCAk86V2QlJzO3b1OJK3XvVeonOiiAGKnCKFmOzuwLJxsAoqAQIGuodd9vtppdn
NS/BsZCuPrqAchkCRGQ8wHDvYqBrT66TSAEktDN47QaH+WC3gCK4hlnC7uRZP0SgweiXhjkhbk4s
J+cYRr4ChIWpc9iofjskI+y+dTmjKnKp4Ttdcdk/vgwafgBqWXjOb0TuU77P5kOAjs4kAJJqeRjw
MsSHX8n3B03k/i3vI7oZZAg54dHJZNr5ObZswhL66ATMJSTod3l6dULK9rGp+PDRDXjrxzVqQutP
+aCalU9rG9/fwtV+jqK/eaRQtzWTCZtW8zxbhjzC6xwyaoXz9T41gf+iG/Z49yRm/ZxrhyIC/pK5
HtFmYzX4KsPKhQs/1LKJQp7TJf2GXzJxbtKknSEe4clk+M33q2zSRVT8vN5qHMcVENgQenKW9hHK
dba7l+SrAbIL3r2i/OPRZCCYe9M+kTZvHu2CTGNymu/Mm0ocwbE0kFt8Gr5ZZnPgjur3iLxe/rpx
SZaolNHKGDo09pFuxER0a9s0Ey/dqzV9ShJuDKzxtT38q0Um+KwK2zqEidJSGu3FiIoYD8uh11Xp
vn7/MwrGepHge9vM2fwIxke00DL1sZuHWJ9L93z/sSuDbotkRHL13ep7D6qGbxdCMYOrB0vXh5YI
2KGzRzIPVJErb2gF7jmO42Y8AtsNiB86lUmTEH6uBMrCQlKRrUeBkgJMc70qWmZFUus6bXJYuO2V
M90Li8UCkinY6O9O9hrSGPziTPy6hksfNIp+L70MwaWiQxZql0uKjEW/bkeCpsoZFCa0efuOZO1/
Tf5+ykHiKHxyuvM0z2A0+sJpzdiUk92VEmo+0V/QL6XfPcNUxJItK5iooHx0WsSwRyjCYqccjhWo
7FWmQ2+UBQG++x8Sz9yrNOHZLWfAX09pVwfyhnF/OEgvUUe7wASxJI0DjYTbtMgixglat49aiCxp
5WiF4J2plpe96n8id01/o4+o3MweVdgzSbKnqt1aWO7yD0ZHfSmsEtiQoBoPnFNL/pOJ4oAYCObf
u63eMZ8zkoikYbSI7R/5iy/Y38uHSYvjHUwCDeZh6Thq3HCafz6fOxF9HXYg/9MBTbp90JAviNIy
QLnnPOgi5aCaMUbwDWjXMhkiN0FTklVjvT/2ILkavaR7nmeEyR5gbuxsk0MF0BPfessdk6WiExHY
SZNR4nQWFNxvXuHWFmKuP0HYVm87WoAcnyURd00oSrJH550NZnv6be6Z/8ZzkI2fJoym9XKNcl8w
JTN0Tf4m1+afImS/biLsqn6ZGlSGdcU1acQ6A6h36jmesM8Z8HFDJ1V3Pge8hz/+WKkLaW+2UEhM
kNjGblptVGd/Qr8FU2EuHTqV5rm3GakYe3iZSbZRp2Ukc2hmsVOoB7yW64dT34KtR1NyxcAm88cx
54hnZ4BP9jTo5zrrLXsWKeEIA3YGFp2d4dy/PGX3G/IMJgNypWL/1qDFoCk1Gno0nhFFlVISn7pc
OhkCWlBxOFyj7l/crIfJBmr0UnxP1HsXbfmk8WPbYvgiHNOTjvS1Sydkdt2oaqWwr943rkopufn5
5LR/bn9noscx5eDXLkPalAjEY1a3Rgxh/oG8aONhi4ILldP4SC/trUDNh+BrFpBOpAc9F8knNZ15
pE9+vsauP801fz9anjnnMy/ailfhtSO8dwUA22dbULLga20HIBY66l9Q4+LhZK0BSwyXCeCH1QM0
WD8Xv3SHvSW9PZuHvVFMxvtW1sqR208UcGbJ+EBtPP+sljvAEAlj9PxciO+a1hTTQbczyZFQePRL
AlT+y5Iic5FZ25dvi/T7iwYTSoDXQP8LZzxquum7yzE/XxeyHXzzrqNlvC8aSqC4V9wki94+3dyp
SNv8HdNiIsNtaKRzVVZvMgeuLNkj2IDuTMxZ1ndpit2SANlNRRvuEzRVLWdcpbYXEVKl8LlANMkv
KUB13U+mUEPciyFG72DMDEVNpXwLY+AZNmmmKS0hCujH0lb8SjYNy6b79aVmXTY1D7YS48QJiz0B
FOr5XjzWUQT4ADBLeM6KvW3VKPDynh+V5xyPbQ7bGSpPndkj0801bfTb7zTd2XZsmq63jTZhr3zV
aSPYsnHE0KVofOX4haAaAyA3gSdaYk0kjO7zZc3E9PyHzfGS+ewhRrUh7+sentiuDB9h0gP2dCMr
gsTfpK9rVGMIsTsVlAiS/8OK77JfINdt7/l19yinmEVxONDpOVfHi0zBjaf6VbiS/tDh0F2EizNc
TryoJpofOOQIBhndUchFK4YRp1W9jU7ux3UlUnMBGaYhEOwOvzLXS4/o2QP/nNUuBwntYLYrY8sg
0fqMlbaivsPLkskyGQab0xsVMVtayALuTrCOO06CpKzioAUPc/UsFHcRzDN17HQ3j6Pb6k1tEIuv
jhA5ExHgz0jk1tE58qzhn2WwUUzcmxLL/j61nKdXTt5keTfcps+Nfg5XkVyu0h7uQ8TE5aOMMQVi
ZREwi+S1/b9K3vBqk7iMaSVBdYwzo1FgpRXpqxgywq1XDhbpzHl3FcxIahnZPcue9uTYssm/Y8W2
6yMPnrOSdA2AiVkfnGTivAsPbd6PbnCAll/lNP7vpZiMsEfTFR0ee+GppwhmtAVSjOY8oS9aO2xP
8IeubCAsMOtzgn5HeMoUi2jjY7211I+ocZxFQET0YLGtuqFPOtNJr7kZdlPGxL8CwzK8N87gf54C
11wra4TUqGJyg0Y+V7ju8t4Z0gaKkopOncDZgBrUasti1q/xGxoIRwpEdbwyAYv1FfSvjokT+kQf
ToA+XU4I5Rlpz79RVX8iv3OkDfAcwBnxB8e1v228VT4AmuK9oqomllObsNzPJVGOexEFKMAjowk4
ITGY/PyzrVEtkKmyppLmdYzs0ITjbKhRgV7U66eOL/4AdwkqHrxQzZaia04Zy7EAojs9jfLmUbtE
5gIdSDXUon5idj0jtw6NFs2uiBV2+VXVgWp5vB9qYngt4/uv4nI8zSXPb3LKSEplQ2d7vEj8PZO9
JAY2/G66HByS8FwPVujFpYFqGNS5dEB8uOP7ms3CfcHKnJR3/2oKujsiPV4+XIed9XZN28aASgE6
7fyisT/3GDtXdJKnWnlLJEawUeoEoukwjPh/DQbUl+Z0M1chMw24wTZq5lz2tPZDRWlM8xHL6raQ
TtsT/uVlXrqPbsfloPiuqvp3e40YL55A5UB5XE2mGf/SBFk4uqWsqq46BFo2P3WC7U112cSyUrFR
TZuV67kuH8dL/0dTBQjnOHmX7yC2ty5nnjs1xcZ92u60UHn6I3HDNY6sgQxQpTrR+ISJONcuxsMu
6/xQqroaaOc0ZOx+55iJPUfw18QgdU25ay/vdSuH90hFgjqEQyuUsBTFkJImAb+MUZ8oxNnWGp8O
1ViKxkHag1FJgKUwfKJEyduSwyYez/aWQ36NVYywkQHTXTRDR0L7N3rn57nzaeqmsst/Noev/se7
2TTVQ4MJV3cAgAWT5Dq7Zumnf0m9k3Jk8MW0w/o+s3mbKlYLhrEbOHBxH2ozh54JHuEEFwHo0HEg
Tycr+G1RlUlzFvNfLVs2pUe7NMKQQkKnCevDjdIAsi0ffRtWR0jYIZW9H+wAO1XRl+P90NGChKdH
Bl3b9+gmvgREe+pqyakstahfkONGxGxNRIxOV0BXyRt3Izmw+zup5Lu0+hc3YwjQQKg1wykjqiLu
4pNcO7rs52jmQleIA7G//vFTKYxpVk/bJMWixmsnDGuRYDCVgfJFanvLAgHTNUSe1fuuIsot+3Lg
V+qALuYrh5Jgz/8C1RCjbKSR2FZWB9S18syGFareYAL6dDOM+fr08lWsi00xxg9r522/EBpY3Yue
vU/52s6GHe4vbbpmSh32FNZL5G8MlOWt61VWdcG0vjAplbsh6HvnFeEF45nwgnzHQUkXOxO74jbb
mYkX4EI71u0/1UF+5UTwCCmvhdSO63dFPW5YtU2WvxY5cmBFsyoJ6mZ/iqaObMJvyuixnaIx6gFf
aeSkD1cNImwVEVfWWi+ubzNscfLjo2/99x5IrRLCwXNP/ExoS9qWEZrJkExq4qJPMGoJVtPXFj7V
Bqq7bufAWu98R2TOGw9vDu6NqKultKWjKY27t+gZ3tijKgwLsJzYhJrItBG1qrQ4TSzzHMXZKIlr
0NVKSD1WDGWgMt2kFmDmRT72j1GAdZ1frH9s+4dfNV4Kf3IoCFyrRJnE0GEzw/ykmEFu7/o/7KYS
uWaSmb/qQ0zvOdV8b9+I0MiYXkOkrm2ZxieF3PTvo0GmjRYVUV847NSX2sC1LSjRDlH8nhf+kIWH
RWKY4oxb6KXmNJpQNRaPdYbvUDuTy9JchpBseSkvPnrh+IOwFT/Zc9MO3WYytpRtc6szXYWkSKiW
W9/Kqt6NI6qlVWSyvPQ0AcEGT59azpkixzpk5suHLIxcomxnVpUON3IXSg2diaNh93BJSv+ub8qc
RpypAWa1kKqvWLXOt2FnT8gpTMSqxBB4qPF7+QG27Cpb9zM5wrLaBBImdUQ5MuibloXTA/hoLZSN
Vp5LeRJSpYUTv9qxjQqcnwVt3PEXyUlAXCgLb+Ti/82GVqFbkVQA+d8KUtLcD7mNQC5+Z8VbgnI1
OQsIiUDDe/DMJ7JJ8NnRT964TLnteBQyiYwU0phA5fZNDfKJsEYQN7ZkmEcZOr9BE6SpJwVXqoZS
PMXFUn6lMFQYRUwA5vXTrRZBPjIebW0vxA+orK3q/yFYDvGnYpV0a2edNiV3QLFUc2nTO2/IpZxB
rH7FjB+uOTCWmFhCE4rqakY4ZSPIkEIKRMNkY+1DtbrK09vkS/FLUuoEC3IK6OytJVuzvWOqHxeW
8efbN03HEQuuFkh8yZE6Iot53inpEX5ONwi9mL8zd18IDU8Nb2FHJaRgfv6OMoxEP4drU1esT9Xz
/+ozcTxEB7W//lx4W5QgxVsNWv0woSZY3mpgvVpDjMUS3tq8yeRDmyG6Gxi3cQwzumGs/p7NeZRb
3RLDw1d0vWawYakltUa3tcQSlk8xs/6zVr9luaLtrBwe6k7gKQLrs5dpPHVZBAL8rtJOw4c5NO4M
eM2WSptEp9vaqhQ5w98+j2bFPUxKyQz2dTn1u6XZWe0Ts09nQKyeQW3ymI1mbaEcwDd8HWucirug
As7ZMY2BjsnoGcILZquembUEf6I8z60LMExgpRrHTIA+kMdOjI8+lLim/oa+A2FN5r8KldwCAqhz
ATsb5jI3k+/E29BeFfAa/lJ0wZcw716JxuZgLqUFy5Xe3vQUSEj/t/vSjV8DhGkcYVEoi/uBfnhQ
eyOiil3arT5B1bx9J4xIyjHNBywD6MiDh+/34Op0mr/J78F3SKEcDdJaCM7w9x98TDKSMBTKHxoX
BKCz3z9UN8OXYwciOsvmlEaY5Pg/v2UtLHzP8NHhjKFOqSv8NIfbAySBRzMKA3naBJxhUYwR2Nv/
jS7FOajSP1CcmZuaxigETBEOS34AinoJ9EosbtyDTVj+YqZo/w3v9LU7Jtv4RQLC9HaKk7MCUwVC
XuDiEjD2WoUfs0hlOtKfOMTtaEnrc1v4QKSwGsDPbeNRXeDGuUbzvEXUor7Zv5ScfPQJTHI6FdbT
r2Njr36r/aBPH9m2cj6/pJTEG8X/J+ALiVoXwLu/VFn/NADKhveLKRdY7rziWvdxTaAyWloQ0lsS
JGIkqLOuHRKIH88LNlIgmBFtB7hHeU/PlrIghKLsA5/RK7IoGsarmPmQJTNtzaDDpb1dClIUN3Si
IHy4fxqS5ayxXkMo9jg5T3aUb6DqozsZX9PA2nMmgBM+OYnLBh6zi1jctWVyon5cEYesqze1a0vT
Az9P/yCslfcU7IeY9wKGM7npwmxDN2EjYQlLAZDKxfXg0OQJs58cpwoMDcDIJwicxtViL0NOFdYU
zacnZMtFF6oCFUMNkmYnBjFAe5zoEUKbNBHFqeQmMiF3ySg44YzCY6PdGzBOcfpU7TbXHKIAjjfx
4iGSLtyrK0qsrCeYuiw5qxfzyib0THOpR0JareWvFpNhR02knNi8IxM/M3N9bDsubF4lmnoaz3K7
syNU51C3FB9boPG/S5pvUk9coc18NBQINRDUIhGv66YIy0ADrOChMagkvAwwXGy3ZUbPmIjt6kr2
kD4JBS0cDC3GqoT60emMpdhrFnA4cfjO7zAJtouXKq/fdk6n/b0Snp3n78oyC76p4a6dN7XuaohK
otDhcAreQFuGogwzR8MlLaj235eRh1/UxIANiMPk5L5NRV0tZy5i8PYoQnvlDgIh7aOjLj46eGbl
2HDV4c00YfAaxjUHiH43wYlIk2AcD/1Aa1QadopBJu5NEVuzZbTa2wvns9v4afIipf/XCcALOlwz
1p7kvcR/Wj+cgIeZvVHGWo/6bVReYckXotW3WTQd8V8QBMzcn8MtTGIfXIxuSDfaCTLgJ9reoCEV
qWNyJwhpptvBTk3pPQewRLsFpzyKsC3Nr4KTXNWqiWiEvHkmALK/Ee62lx9j+rJneTw4kzoF+4+p
iBxVNHcs9X/lTL1KC8cNTEJLtoqjSjpvU6HryF1sTYF5O/XR7taqb0x5oPsF/s37hKDhPJsIfPlX
Qg1hXpeIQPpOXSTXcZtIJuFlyNt0QXjCOds0SDQeWoJuu/U7zS9iJX+xNz+xhNUF0Y1DgyYejMRN
UvNcXSswFEAnYOPP4EVWLT+14hCIm/S+4A1pPCuZAtfLbtyuqNik7ks2Bify49C6dg7ygrF5zbTG
LD0lEt6hDiXGVSatg+ZtV516iAFPsMucPtA2c/P69vn00GluiH+WvKD+Lh87ebzLI7E5TFSDDGBx
37nHnJCvOj6zu0og/t+wlAcp4t9udZnXnriEzXWcvAM6av5TKKdZhvmYdDmQYmp1Z8erxd7L8STb
R55qmdkqR99WC4a1J7h5ib6V2o1aGpPa9wXIBpJNtkIRRBkzNvr5oOBP5pjQNrclnSfRWggHIWV5
uTlT04rQEFX/QYDJzRlpnpYOhs6nVasWh/Jjp4OXcP0edFoMZZLjMA9tpotHwDx4N/n5mXEenq1M
w9n0uBE8IPjEWmdn71m6s+HaQAk47qY6Pzv/82Wlha9xeFGaFehUqf6W99ejSM27rGW47Wi7xcJV
P9BzQi/Q5hVLZogzznHgLWYxihaY4HX1TvhrXZaMV2kRZyivknsbis/Oqn5VKkqqG2+BgsGS/9MD
EDFnNcLJ8taEIZG3p6hEnMzfaJLFoX2EVXfmCuCMOsKGj9FM81kDdmaLfLuzZfodJ4t5+NdvC8/W
Tgnqbx9MHb/+Gviuj7w7WjyZLGFKBRMtCkTtTxzA/BxM88sC0PhUavwo1L6F48tI8PB96bhFAvUO
u5crPyhYpsmAP31pxWM3LmY8mflmuEUl/X2XrOgn5lji3njnYqzQwm8+bH70mKuM5vha5urkTwwQ
6zcQvtQJak8U/QLVuZAkfiZHeLywfbFftr20/r8wfnvzmPeI+RAZ8G5nalKddAN/tlylLPwYEiDK
NGBDSVvkBfWPmUJyxlB1NWKDISN8wXKbTRAD4JY5d5g68rLLBVln4Wnu0RZyIrgWfs5n8mlAFOmq
e+WClNYeFVt0ZYQQ7PyHt5vyiNYKV6gbglx/tsPxhxF/yYFtGSF4frQPg1wbQulhkFd+pu6TRBku
PYhnsWpfiNhKwES86XCAsVPEwZQoBdC7IiRjf111iCQFQvPfjUqBrNZl9MvzcA9cbGoZPH+cHz9D
AmWPRxdFKbDCA7K/iBtiP0WYGsUQrLFwVGw9/52NGFOpYde4KUhSDcIZ5yYZPIniOrhvbCIWCxJD
ids6ppAiUNd/i8vE4Fqfd6ZrD0f1RErevu4cWsN9rRu1jlGUNBO8BxRRudxgCHh2/qzl89Wg9zP3
E09bWqsjdZ2tHZDf/zLYgOmU29t8ZOVCHx2QHoydzNVvqaf3ZJrVSKJ0cmi73nctfuSp4XEMN2Fr
lb6wxlGylV/WUEHoBoq29paVKJcVXCxc/sNq9++vxHF4R8jj4GSBLI2zDnACgCYxgFJaZMb8Ycv7
S742ELy9UpjAE4Y8aS5XTdk+B1ekQPs2GZtGLYJ31j1PIwLr36Kf6trFjBjPxtjuDmXyi4FW6mIK
BSQF5j5z5WyTPhexpL2RjKZ/jHbLr30cd7y0JSuNvKTR7Jw9m0+Xkj67yBIISFb0tt2upnVyiIoV
LOgqMezaQHte/7Z/6l0wPtAF6plYik0SI4VWRNysDVu/mdnaA18erS0sDUKSEsfzmbapbBJbEk1A
ManysZ9hrJgzDTJlJLXTsCMUBTUqIuRTWjsA+M5QCgva8cvxa9rDWijhEfhmhCFsYVxHVv4UJ5G9
J0QmrupeBVV69fyEBRA/HV24qtE0ARMun00mZ1KXWgTCvCXKEpbG8KLqjm3vD1OatqBX5BqQr5Ve
640Gq4pWfYYV+orEikvP4ScBOgklYJxgneTuaLrNmPDeeNPlyNLBxZRMm7lqt/hBYpRiWa+FCTQk
uBfLdofT6fPSjlaVEO7Rbaiyb8ymJykwX477xPFQjiwXBD4P5wfM/+beKSaxe2BsK3o8niKJu/I4
8elImV4s1drTGzgv/0dVMFnfb+7kwR2EnhPkTDmHebhoay0gukDuidQs4NsTtLuJJFD2CwFJvA4O
5XL0id4r3hkkNGw9FKiLN+WxYwkNORL0aCTePlOuC9pZ1HKZT8I9ejkBmQ13Q0zaoTdGU3zsnV5s
4tqGIpTAnZcCbF+CIS0VKKTEF7FMplYDblgMUC93H1uFax+cEIb+njDAV276nYuTVLkOwCxtZCyn
N12y9fAmeFqamZ2g4t/LplOL2AvqfgONtGH3EqOT8oVbiue7DNAFdtdcwPV9xMFxPIwrUt6bmwvk
xMNRMBn4/OrqejycRhEybd3Ywm+B/woBdiLr2Ktw3dOXc2iflDYttFf2ws9DqT3uadZmLmHf/pUo
/kXoFtTUPHt6GNUgW8XSloUponHW9obMsYAWpS9qe5+G51DLSQVDlxLpT6jiLACfVnPZrvrS6dm/
MNwyzR5PrIJMrDLdKhBZJqIzEO9AAU8jiXY5m2Ka7UMRT5OD6WeukwdL1okJQt3v1CzVkHc2wT7+
g0TTwgiK0EoNZUSwV2TdttzH7709amBBgIOnu7vzyH/6SBfMykGu7Vl8H6GShvRlw+/xrN7L46Bc
abIl6d+pq+exwqdFcvMf0EvswOw+MXWj/bU/7tJsdJor6V4OeyQU2EjGpedbYeiF2r/HpdZV42G0
jxtYYUOwUJAtPJheXTmqRA0AUMWQitVunA3PAedGBNs2KyyJVh+OtmDcixRS1PshFxW/pO1Bbfrf
1UxN4WqfdpwCrO5MVpa6/l6indAxqrzQXqNzPkaY7hQ1J1l9JePTV69r3v3W1zoMP7O9tRn6tEWW
EsC6NoWDV/9FrVsBIkYL6ORrCFvU/RJBj455gPpHJ7WOduLhCFxOv2rj7wapzxxnpxLGND0pBW5h
duPiaelmmv+x2ImrhbNv/F3uzBGcwGyj0qediEK0614CPOhijYxmvGcrMgjMAT5WQFC5qefe+qAQ
Gtlt938yxRyb+21FLS/Q571ySk6BOIW6OL5f7iuK/g1LUhp9Y6rPQaq9mRmEqfwaK1T7+ErzIqEA
ZghsUajqkU8SFUd5mZVYBWdCrzj6NCkT2DS+/ilOiqbNPjWOAB8xIKlTI+uTxg4iayhWLqMiHu1I
7QOIcbNf4aO6ey6wXPntUrAwTBQk1LphLtjErVLgLNU8MdSPobT1PUmdGr2MDfuAvc/TMm7KR29j
XCDC02LiwmZcISn1Q5qiKK3SyTbEfhWk0w/2JVOwikO06mwFlFDpc/O3ALgOcGThkB+PDjnW8i3W
1UJ9lyrT7JMhmvFhNJFAIDg4WS3VXKv4kNiNDPlJPx15dT3/CgM43S8AW9PqylubaLdb3MJTNbAu
PCVBWYTKesrSwOPlZbqVvEixA6ep7lVh8y4/nV5vjR6BELXnC5qaaXH9V21l/4bO/qhHh9Cl/8tV
eLYvjhuNlgc/dX6RRAEghKLeT+53soVTPwob2rAiknUpaR2do4faxSQ2HWE9hTyJOjH9yakByfua
WYqCY3X5TaQtV+PCEilMBQ8OqSvLWRf5jP2m0yPUy2Kkae+1XOg6D9fPbsziVvjcwyZUuUgeCLEM
Xuuve+jyghEdtLECcyJK62CfadbntXuKg54KQ25PYg6f9H1gaouP+HtR17KoKxbgLYqe9eDkbMPy
rD2hIcUOZtX3kcnF5IdX0rv0wWhOruHqnqZ9ME+cTI8X1EC1YIunJUN+gFuT00tIKXDNstNKw6su
BycG9B/+hB/au795mTAjoCM65dzYMd56dG6cGLiJZFRecpdcGfIF06y0tZa7Oyotv7+fY+xokXWM
v7lmxMeG2oOtXER1NzwASIzLTdfxLGr3r/Dy8xYADtN4MfcgOChBLN+ilmPNm4vN84vfbwUiQmNa
GwCIIm3Uk0UEsnb/YvNOCX+W9ZTU6V9DDFvDrUS0kpVZA1uRjzg8dGRa08oMeM9Uq/jE3qhB5lE6
4oPKboavpRv+UvPr/+VE8dxM6QjPGPO00UUv1r7OePBP9z2dj+NaQEvhFJ+Yr6eEVdUnQNjtOuwX
lutMH7CHBcNBO15ZzYMOIKYR+H82Ik8thKplf4Sj5bj0KPCjKDIbdlbnWbsRs6JQjE1Sxb1ASD1V
55XcTNqVGCtjytL9P2Igs4d/I7o0kHNHYSM3qTSfqT0n/2af44wxMS0tMkTZ/yBXO4phoohkBPgU
2Ry5d+IjKz3b615ovPgLuMxjNkvxNdwzxyGaJ5X34erQbGceijCNoUm3T+kKnv9kAes82GK9j0wD
ZyhPQgadKNzyhHqmUkhgxy1s4/dOzuqG+Qo79OPMP2SsS4YN6btVfYltRBCmMwh7PpV/+cO3UA7y
/a1NrMCEtnowCKcwTe3AykvN7HCXTy4UnTcZCweezj5obmuu8BMO5+45mtwkx6W5YT7akrFisVNX
PXhtoNSIOqxMyxA89ETyVlbI3X/zSgP746i5QJdJvNM23YuWQYqSBnnnABa9m7SVuY0fVXlg4qX/
CcC1sfUxhImH98IwWMm8fMaIllfQKwH241xNMXiRLytWlRUmr5OvHsW0i8j/GPGDHoH232Ra3aND
e0hUJoLP9ZXkkS10knD8uDS/aYiYzR7epJmoSTG3s4jcDdfV7Qn8qJ7SnvAopX+8hWRUTUwmZRRr
05pqH/yePxZ+o5zUH7U81pMG+HsUqAIMfmKXrNQ7a9bLIYyE29bnnFhEVV6XLIAO7Lzui14xiYy3
g1/fU4Vkl6qmHchC0IyPZDbCbJOz7fKq8rssv1jMajLElN0EJ6T39wlyw7zesFyEqLctPU1vS1mH
0JFNOxW1EotSwd1Da6OzXB1hUBgZmr+GVgfrJsohmQP2RnPu6mZ1kQYHLpAVRpBgqSL/RZ52c5a5
wp0MFvXYmIpE8PtIefjH0rBtsCL6ErOgXPMcXjDDIKIgFc7DgkEdhIK/mmVfNvAhytA2Ey/KnyR8
AVwpUVyaIvJjVCzCSCRaULbd9zbHNtVes4Lbm0gXvtnN2lr1Sza/Hrlu0M48O32UmBgQ2p+xRqK9
A6aj1kSObrADfUXkGLm7dS6qhgtxzMrLnEi8g2q39TI4gF0KpGBefEydA6JVwoXRa8gAYANL7eBF
2NHy2t4VEbFGZFK/LpLWzuGmQZI5cJo4gTBg8zvomqdk7pD/AK+c+4z6SszxPcy0cR+ACx4hh0xG
8A9tPzscgcGlePtc9b0Fu4O0SLWeQyB2PM65tAZxx7wzyYgui2XV5GAGlCd9g/XWAhfRrJ7eWAO9
i9wUYtEVN4yFjW+scVzob86FPHScMMZmFF+SAU+abK7G/QhrTMgden8RtGS4R02xAQeivML5VI6i
RckU49wZGGf5xhz/soopFFLZ7AcBOE3p0P5x34TdXAoAv368r+I079Gi7lKsDPfmBiIi6yHIAFkq
cAbZx8jJ8BRiRV5ZeF2nBK3HhN/APY67i43TeN+fKmH3RAx2R4GN/QPn9QNgkjNKMrTvygWOnEnR
QcRfrnundGIXj9+v5tEYaMni0MlxQNEQJyWB96qf+aoGVJMpBXGwHKHQy2oyPsaptJ41HfD1XDds
wvVIo8rrnkwZ15uKLf42D12MnUpqskHgaHVYrp5GTr9Ws5+fpz6gYocBTWGqc7dp/AARIET358C6
fPkmNPtCyQhSFUEbfuR3iqIV7p6ke/Hgc/SruFGRktq3UVtg4z3DoFsqVWI0qZ5H1Gc1w0728Chy
rq+rftj9cUsBv9DcnHc4YgzbprxJKJ48yf8QUL+DeZBxCaQvTVOIQ00CgBXTfGyQX4oBE+inwOuy
6vTiJDuvEDd2MGjEDJyutinU/DrH1GvVcAKAtqTps6FobhCxMXH/gL0vBOjdRPWdouEEpqVl4393
kQ9htDEzO09lyyncAK+ePkUBWKw3l2fIPuT6wx01rjqGE963Irodp9mqUenGr9QHtsJyciinCDqz
cFlPVVN90AWRkzn9saGtUuXoRq7+B4WxDmcS/JKvw79At5bULnrK685eU6yTMDt5L2st667zkOZx
FJyXU21eJiu913FKK2R0PepblyToKQvUhivCWt3ye3TcotMprOh6xE7WkPes/UA/WFS2Xqtk4064
HvsCAMeH0nVQZmzbueZ5JurbJquQQZriyO/RHRBQWM++62RNGHKMwAD7Axg3kIrG9kqu/SUvPY3e
j8BKWQm1uDasV7r426Wdcj5tYRkhgSLPaD+Y2Tp08oN4+FVzeoxHkMOTFG5JvD0Lb1AVBT/UHDSr
odIFrf4hOzlMU00EJdXWHRIN8wwCHEAGxgUcjtfew9WEElK6E+EgbTHQCOAiuK3yOcLZmRpXYQ0J
tXpvJ4gNxPnU9pX411n8DnHNkwm1sjk37MGi3x4EjGyv4lIewJ3w+Sp5X8wyTesMXSlZzxsD5X19
ntvkpHe+VSeDtHrR/qAnS/Z3y0eYuuFbb3/DzKskRWNaQt0NGvVzgf0zcTTJnSelgyH55lupbXIY
oiAIxpKrrYtxwF4z0F+5+nXBcIx+v2KE/z3rlEyWe0uk1cMg05IzNEKgmJvgqIOyCC0E7+u1MB85
bWJmUmNH2vafWtypvdINF4QqqebqmBjUEbPtHCZmVoJhA/rdapoo1EGS4G4+J66qtMNj9uoMnctK
wGwijsQNKCPXjJDd/9FViY1/uKC9GlkO4vTGgvSW9DcPMLvGXfqRl4h0h1xAGf3KNmZxkrJC0sAm
w/FrHvHG1yZweBpZ4chjsHFgP6kvE54eIlPX0jsln9n5ZnBUXoJT/KruAP1DOv9ba4nuMoZ0HP0z
pupqquuKlO/exnFF3tyBczHhSHjg0gIR/vBVeIlOCGYZY5r+GbI0UNTIXNnD3u14fVV163OXHKxM
cz/74k2ZCGMPS1SoyDVRfDWr+PFrTxC7761FS1zSyWzG6+rn6FJuCNhicpU2DVcWG9NqdZUKqu4N
HgiozMOn6o6KNm17gB6cMuwmYYtEyc59f8IwvBExic/+aKpcNnPr5lYN5Xvc5q7fb7MFuJPMFYI6
9paPOR98ouaUJn2vWfCBoKo/VWJ6d9osaduaaxqoDG2dlAfHVxDO3DjyAcV0V3dJtJygroxaOaH8
CCIoVsj6pQtvIE/sdbzZwt/eiHN+swel0fF5dTDF7vUiN3CjZnOh9HpFTB9rFyKEyjuJH217Xsvr
5xcyl0DWL2mzeqXtIb27ZVP/bulHf/cIbtF33AkidKwXhWFVPkf8EM4YfkyTJuggIYr00n76J9l1
kR7Otss6h428b/iOJ5NHfuRxEYqVvvO9OTn+H2nitqs4Qx+wVnT9r0csYpmbCAc2fTF8WzqjR34q
EpQgP6JmDxqAW06SWJJr+2jp1x1YQ5wAzcODROjaHuIFJngkWDYo4reog233QnJjiy0E8t5CPuOJ
EtVMwG2P5MW3GhrejUw1WNBRKbrwjV/KuSpjGlzm9Hg2Pdqa/7Nf2WqeuG4c9jO5Tbsc1wdNzmhW
jKc3pvU8lSlGZacx6JjcedP2oLIomqb4ZPSkrWkheVjQEs710wbTekvjmcnf9CL8pJMrbknYfkyo
DYzTNUG4xRHa3CWcqmMKTA6EqFr13Qx3iACcHmBVYcsr+vx0DTtVRlN03Cl/Iw8CUuTGg1V3dI8h
IhrelZOMjdgoWK0Fs9Ltk1hWGTpFYuyY0+nvaWg3XyaWpMtM6xJTPP8W+X8o3q455CcEzaP7PYZl
+vCpl6gorY61d/3jRFKw+Kh5PFUIRLIJV+YU0CvD+AU13Ccvzxqff7x9j7+rsVtLpImo35HmWuZH
LrOXSJUEcr507N5jgWSiYXPFTIkLjicElSwT9b1MccIDj7lF/gM6bq/z4ROPPuwljwrFh02f2Z7B
kLmeCnmhO4dASSl9aLc8MWH7C/0Mnplq5NYKxeZl8kDoavG0spJrELRSN17q4GnUakmUy3vAxuPR
cSRZPdRsvIBa1WtZIVMPxUD9LpC1zw6GCpUdJ0DN759Mdqs1lxcHHt8aukPrlODrA+yv43ENtYTf
7QqpLRSuQApl8Q0RJ3BHFYt2xRzLM4HgTNdoIVn4Rj16V+qbfmXxZPCV285MWqwz5+2Ccy4dS5LW
KDhgkKriC6kbjCwDpDxhDJj7ADs0AVFHInYM41acNjfE5xc39oeFNpVd3hD9/bFZ7gDPXXK8OWl8
DIh8XfC0vkDfTklL6K6COI+jcZQZJ+TCFrNOSbp1bH1F1hwCV8i0miUeaUNyCLGfC+8sclONgmqR
IiyyP6eDJXnOiGXaG2NxSNK1Hp9R04V3iruF9uBTc23Azg3bOmfKMXY6N7byUvdMWkLpPgLW5JF3
ggmE31zEx1YsYbD5dfXTXjQFcRK1IdH7tQZQmOalz/jppKy4NqfMxB2DWh/tayxREXZG4Ehxphjv
FL/iIIC40edpLfiYpHKBK120M96DHFXn4g1nYj++hGOY7jvo1OS+TiqJ2XY1w3A3KtaKKCtBRIT9
9RYcnnLoSHV/wCL+xxIgoHIkx/gJOKK0OmftIfzzg/+UUbe+xKB8xg2Nex9juDEVdKMQuPR/JVAE
CqIiDI10UPhZHx/fKaIj5DlW9OWs+s1a/hKhUTdCNM9f19ArVoNbKxTyi9QdkdbEZwIalC+9RIpx
P8QWgAV+UGD9hyVHlety0xejX/VOVusvoIqtiUaX/LvI1Jln0oo2k43GRtOBGsWX3vGPngOJSgCP
hHmetkbcNAmYQrd+XRiGD0ecUgyCPwNaZwOHuhccj0hxMmkMsIhpqqBpSf65xDPR/ddpZ5RSddOu
MKgyiFwOUXZa+6lDuJeupeMTbXETCWf6seoTKKd2yyp4UHwLysVkVA22hSJPKsy7jWiWzHMtK932
tN51Twsl1K3NWHsGognKRpb+XakBjFhuD5Lt0AFVoFFvWhd5cdLUgMKfFiZwCVGP9WL22uDNlEH2
1Ek1c4S+YfIQ3WoVjKGrCUMhK6JSvd3T0l6SQZ7LE+DkgM5ohL1FZstuaSmmf0V4mJaV4QX1vCdK
E+DmWh1uYRWu8WrtFyhN2K77XhlwfcCMQ/LpE2Ej4JXGsqCD5I8zWr9p0Zt8ljeXmdqdDQ5ebcxK
6DUEfJ+uPnwlYWDhmL47YNg/ArHvoaT2mStqNd/48mWzFOv9zC3aaPeedIJOzJnsCLlIMXDCH/X+
7WXOhwmXkKlPRBdSEDBTEZljKy5d4nj3oAUOUzGyvVzw0BQTzTY5d4EYIu7JNj8AeX7A0uQ+zAF2
iAfWb6DxrjzWdCDCvjLU2amBR7lNxGBrA/QvAGgXJK55rEJ+F86vm5grc+576E3MR9CLlYHtDqzU
khjZlMYuiyhkpIZsV67dSPh1fUQ3nD74ADzATffPT4UPNV9ZLRp+B3u2Zb1SbcB2SGnCVAsWnabL
3U+lUCygOh3WbS0k7QC6OzEKCnPqv3XxjajdjovOCM2Xo/6DqHgZ5J+tpIX2z8DspfzkDHbW9KEL
p7swoE+8+mQvlifd3ieNZco9zVPwIi0T+x9Hllut4SoQi5qvAuq5FSQtkoQCLiGzb4X2iBSq9wxl
jyuHLzb2fFfmaTQ3afsZtGr3Ud19TE6GaP9MYVHpWyImm2fkE0ItStlnTFTxoIALdqfribgETNp7
rv2PwNAFIk6wFiMg+Ikx0VgYz8tJmTNmF+nE+XmXpDKYRFEWvHeuOHtWfgh3UNwcg/0ySbjGHp0I
YycB/g71RGJP1uufXjox6s9WjwrqfkAejHAxXXTjHyB75YUF1mQ8dbrzbcpNXuo/ILoyOMvLITnX
ZU2ghMGAzTuDfGCyw43kzyaz7deLIKZt/x48d9oo4zpibODCK3w7cffiYCst9VqNlSY/gnqyBFXR
wMR1pXtOZz8mJLDczxeNgqNUeZbcHEjNxkS3rudh7yVoXKgJkXhBVYdk20prq45ZBvSbJRLDSSkK
PcC80XfhRukSSGP/FwR+UrDOpH1yqMyQkW2jEF8+Qkwh4aH3Zhbno5+QoymNQ8RDhRta+g0NsoAF
YVGWef/NGuM8BiTiPA7zBf49qhphvfXDZ70Ip6urDkHluymW2UKcqzn5IeqwgP5Y7g/I1YSaPF2d
fwXE45Ev4B1ATnaLk5npuJkerYr24ZTVX8ou6YQJKI/i+eu3aMM12Ze7Ldqtm78v5acjtkLnX/5H
lluYy74RzJILe107n4B3Q0F4GnOFFPJgT6TkA6XPjfgMzcvFPx8G0HJJJLMb28ZFNkS9WGtWC4eQ
k+NQoMfzoEVz+103+4kg4STS/+daiHtbn/eTLgWL06QlEhymZUT2f93MjxQH+ylP10TRIdFJSzWA
Q/DhcptHVKj+k6ce51OgIzoJKIE8gXpbucbiJD40YjlQdC123vhNb/TXeyP8F4I3xDc8wQRpugli
i10oQz5m73qFJlJdK1VfEa71VDXW6VwJcVW3qRbAhCWSeV3C4m9Lr00WqU4mduNmEH53I0wZKi0W
Od2gLkBnO+Z/VMw1i+hAGaeVMDBJRxYBtzhssZArz0D4b7ZDOHWU1A5UE3LMaq6DUgYN4K+h7zAX
S0Rl6Y8/ATsVd1h3yCVHCQ6Jherir1WxxhXTZ2b7V0egzWX/1Hntp/nl2AR/2jp7ctbkWgect3HZ
wSA9YrPuLsWgRx53VxqQ8fGaJB0YdFtBWRsrwr8JnPHq2g/gi9g7pZdDm0i5eGPqV+z4klRtlOfr
EJchIncBfY9xWREsXauOrEEVrX14JzdKEPzoO8piGN/vZhZCWXBh+eOVFNo1RpsGz87WLbr/24EC
O+SR1A8ELIN/JzW/y+WbKoXHxEitycEPhKPlfdQ7kYo/3eBEwGsrUYlnwSkrWo3x8PDZcAdNoOlJ
HfFuBwn4KEp8UWYqyd012KPIyuGnS/9PmwUYjiPZz5ORPcIaPL2R4Hf8WTorSOLqsnm8sIduUq4J
xm8O9inkW1SlnTW3AYvpUiBGo1Vt2u7UKSprmuwQmAlVhFtOLIc9nf2ZZFm61Fzm8W69fs/Hn4Vk
ix1gDvrQwKrKVlgraaG7px8GKcsrRgHTxDrlwsjAwHmtGgf7Rqmbkeuf3+JzSzkNaonBEqTdWKiX
ESNl1X+YoSsdaqyhOsDdynBmdqyiB0hxO4pxd8BPPDWJYwuzXdwweWldYOcmsryqhP5g8zQeoBGo
WjQTPr9JYUnc+QTT9PbLWR+p7+Fxa+97EpviP6VAAxnYLOkallfFRm9fSuS9HcnjyIw13DYSgHRg
igGtUqGWaHuBuGlv0hTf8ity4I8EcuREjE6Gac8P4936sSH3uFE20slRZVFgzaziO1xK2apZ8RT/
LQkVf5Pd+Y3wmEdY+iUAuWgeeZe0XZeQLRwqAZc25gKEWKk7X1iI6p4RXtuwDKQPDwauo4fLS5xZ
wm4190/QOMBnxkAan2xVnCLRX2rLzCbeNNioABs9qNFJG/aHEtnNFqbYa0/BeZRZxX9ZC83dTDxu
JTgDi2pxKE8xIWBtcyyaNjAgO6YTmqhl5uvjcO3oRvg+LIg1SivFLZXN2OfTmFbPw003a83M+KuT
eTlX2Yd3ju9bfNqb84MMGgA58fUn/t8LQdNKFjNczd8zAMEI+QFl3BeEtbfAtkEtSVubPWiBIQ+N
Lv0S99GgYOi+V0FmB39XDQTcZOkz2yi4Hf9kCqAhr7fowfyQpCFmHSjFsq6qQXhJy7Bnn16qqwJ2
NcrloXZYxBbbcvb7weFDd0+0bkCskAGxOvoP0YKmDZoKjxspU7njulXc5iFkVLTq5XvAgUWsVasx
220ZCGe4qbR6akR+TT9mwxjO7wkKk6zOU6AlTcWtIlAXYhiqQ0vdjQgSqaYKbeMfO4SfPzxAeF1O
3XIEV9SiirXPXTFM12ZfSZgzxFezATUP0K0SpNK5uhTPEj7XyVnn+/3a2i6Ijh3XOQYoFgnGaW/P
pvwbninyoVIDktGheg8EivLF86+JPNe9Deq4KN5zXolVW1A/Xa7tqKpEGTgJoIn5nG/B5uSH+Qa9
KvnZIfA5aIv+eOj0HFCJ6fEHye289t+YCHZ6VY5WOFkEOSjAFniC25Mu+SaCowS67uQwWkj1qXbs
LO0C83nnNkN5Nc6qGRDqwAzGFe1bTW4o/QbJOtydiOpWi7IHNnmYt0LQPZ1lb6ufHG0zRvdrrE08
/GhsTksUSXLvENRJ288JyGDTfjH/8FL3SqZ1gS31VtNcGBB2Ls8uSZCGfSvXg5TUX/aDEAJxLAhM
c3qiwR4gj6wFDjlWrNIK+6tmxtK3UKiaF2GJRvm/HI3xcaawy2Q8VfG0PFXbhuFl90ghosQpDg8t
rxeuFmG0tsLdKeWML3SV29zeXi+iyyXpRplsIrzjvGSEw9KYgXByIfWulP+tFHw0iQtve6tbz2d8
FZaMWtLmD8Su0I8g0gD99l2zHzkfvTiPAy8gXuSA2EWyA6L7n4+bhaZ9Wt3KOqh44D+Cix8w4G8I
lkuL3dAOz+MMOUIxA48LxWwzsLHg5oA2CPSDlhoz+LGQafS0DAY+sVKhyjchsuZxKOMYf9tauYRX
GnkV1F6s3RGqlzDQPHjI2nwQrnfGVHrOkfZo6AtlfAwiiyi48l8SGMyd7leUKldxnrdBCD1fhons
18TDCkl3ysy6x1baXYTOaDoqTLTY4EVDTs+nVbTu2LzDB+3j4tjjxQLu/FyppjPcO4RqALlnBZ0D
9fU7UAckW/0ycyYA/B0V6cEJbo86zpZthMXxzQZloRoFp/3iIUgiDWbxNSYDLevwFI6sKS3wm1v7
MlZzFejQ6olrykPjPoFpT6WMpOdeR0AJyTrEshDwfe0RFN1iwbAYqQkAuR8SUrLj98dQXuFF07EF
Yt0YD1cqx0Jj38ycQKdmMm3Mcu3oCqN/WyXyO8vgoyCV0jReh34jbG4oS7zkvZJRu2SPYvQr74aR
W1GM5/v4rmGmqLhEKnNSQUwumJENNM7NgJO18bXx1Y18CF0r64ZsDayERq07BDog7yPoUTGpXkX+
IsmtYx9KP/rHNLSgXPVNbm3sYPbgGEJzlwKgXo6OrBzvqb+zej7CvXKWkStq7uqbsOLzlTxKsjYI
qvLtzh+O4XmmPr+ka5eW4kZhh3mmk/Qb9xeb+jgMp36M661v/I2yPz6QbF9nSjGV4LyEnbxlKKx6
xDJw3iXK7AhJSbqIPtU6KxTPMgdfcekwQ4r9k2H1C3T/Jj9JHSt/icQQZzhY2rLbBbdc5E5YkCB8
4YYhRWm/si8h4QkK6UtQLi16fNoLwKbCEWEriaKBDfwyudstWczJxvk/Bk5VhvAPm9MEOrNeKG/i
ucMOunfl2zwdWh60OlqUtRgp3QTzEPiRSO0NIntjwg5RA40Vi8VlcmLcpHdEW6+7E08lyyvM5YDU
VBTKg7efweWx6cNd32BKMNQg4QIHjeUHYA+zPerxlw03RuQVSnEfTSOXQwRC9kJjCl0J4bY17w4L
trFyBkcaXkbxDEAUx7GTEeFIGh/SLPwwDb8pwtlCqnDnfLWreFxYfrtQTA19LYKilWcWyWwdGXbn
HDyeSP9bkMerEkOw4yMMmcmQNr+FbY3R5oda2gnvrmJhednMsN8rG5rh+/LZdX/nMywXdnWu3xRi
axHLL2LOoO2awVaaK/GtmSpLBQgCZJTg3suIoOSiINCcF32s8L0l3aB+kNJVUEOCvXXzjcvGPi9I
i4cYCUUe8T25pDV7NIfAQJyZ3zBeBtuzeaTEYJZ1tr7iuu+JeD4vG+eYhLOi7fnyogSIfmftd8HQ
NM7btqMZZPFOmav9VmLyGHaHILNfCA+clxXrQRAqvGiFwKa40ZlDG1O3sxt0BH9Tw8MdqprmEMga
Kqs+aOZkcrCTf3F5byI8oPK/Wh1wGHoPFvHGOgqXTALkw7jjxNhmxhY7sass0+v5vOqFpmAp8sXq
wmbeeC8nP91G8d2gH4+WKm+WzJ1XvzXfbOvs1g/AuszVwAZUt5L9uyGZav/PW1+A5wfOjc7qj1jJ
2wFV6pF6uM1KOoi7jd/xoLb0YGrdhMO09MaWQbaYohG+wLePnP5OO8bVN9p+ISytVzm9AAyM0NRP
Lmri/rwMl60E9vpIgzrYteh1Kdfn4Du0SfgOebaAsA4xAX60i0y6Uk1HuWgMji072wK2Ws2r7mN/
zbtaWPizAYvCyXW5kt8fRvEqXDvPj2T8bcGnMfsZnrpKGZas19gWPsl3pswMwg449B4cc2TiR4h2
eikMS9abDkgOd9/v9Sy3FWQOb0WISIBG0mcIP9Dh+I7FITX4na9W5SnmLUNmcxE9oZYGZXHR44sJ
Nywu7tBr78jktNamLCLjuMeYPKoUEkpOtxipIspT98nDQ72Sau4ZCmEtV7BpDG/DmXd0NzOQ1MlJ
YKwiF3N2vkYq0p+un249STq5N+FbcImCW6Xr5QYgoHAA33CE7Gus+jTQZpDl9+OmIMn+2l+SLF5A
Vl+2mE1MEXT9SgM76qn+SccGRIgj01jqeSm6YEge03X6btjDu48J/1Pd0Li/Wn/89G30yFD4g/e0
qSwxPbwO/oeQer99PFovwC0FFqxnopzBoGBbVcXfL5L7sfwxHipHXgfa6PQNsV64+TBRXTB67CdZ
2FOr0v9ZIi1JqDSWmUBbwCgDpNSUfik7P/CMpjzU5hmAI2Bo2Ty5b2dXWewpCACARI1/WfOtCo80
QrRcoJ9Y0wltQgykfavoQCm3fViJ8htEBmeUG4Si4X+/2E8vzAMtXTQHtJp8D5bCnPn7LPWvT08Z
Efw9zYIebaSx1gP18kpI7Neo0fHB2i3AUFtI55EVwDL8AK3XxxbklLOGv5zYxlVmFnLhj+a0cIwv
s6NrjoHKzXDGpGU2Fw9kVZ8tSw40Ozz1vy8omLthVP2582iyrtQI/H4m+DcQ6D6MkYHnvZ9EVK+p
0Z2wpwqkW/HtO2uc1T2kfoT5meHZZdbFdDktKw/bpuDiH6xd4QUDjaGBxrvhbYjFnAU56OpkBY1s
s/pQNMFEpbyjDMnKQDtqlz3Nc/23gyipg3hY5vxezcS+8jmcs7adkUryri3xNa66Yc2HFyXj/0bb
9SGSr6ILB6LGwhlavV3PUUSS20mTI0hM3Tr0yIY8xEAvAav1yMi4yPw8WyzCr87/5KGl94z/qW89
5+jn2UERedMvFzE3ImY97iWzToHSxrAurctmcUk7SUmRRWlfODtINpL43dJAtuZiGcGHluHwJTy2
2EmDUQy+MyNU9C57Y/zK0poIkTkpaXOrPyZveRTqtCNyT1+LXMaOFZGmbGOXjl7naPHqzOguhHAn
tHrLvy7tzL4r9Oe+gC8yhZj8MX8GZQce+/4N3//cj5+ZRvAvuNtBqQimL9ZJ+bLwIOb/ZRc0/FoE
owcVPXt/2qJpFVWdyhjqZ0sQwxRBiTey+6Xnf08B8SbBjLPBj8RXI77u2yEuadizrLnhWykVaLcP
933eGpEl/kP3TP5AtBUtzqNcqr18nZaq/Q9I/5vPhe/UbinkAGAatqR5k0OuRL71mI21g3b6AlxA
74Pzd7wNX6IIMNOdhUMKZBF/LzXiD8KgOzkpHk3cK/OJTbtTf8aL3KBG9zezq/YPS5Ayg1tVsIXg
syW/EBG0ompYtIWSwglVmNefWw3brPChoEGkq/qvkWXsF7Ji89RdnmfKJWrLY9j62QlLbHMp26U8
zjlKLHASH3kCsXQsiX52fuix5WBu/u4Sv/cc3Z1iayR9Bolj+KrFYrEtCAGiX/3HGLNsLK6D7oLx
b2Ep+X3HVMpWvap0VCgOJL49K9ENmT9JvNPkx7xgdTqtMTZofPvUvWk7/VWOyLqVUfpVL56VZ5OT
TgG3VrXBjHIo0Mv6AyH0eCYCylFJu2dutb2cJUTUB5IZAFA+/X3/EvsoG/m/9TAi7w2yTudUePju
opI8jF9+eJ24QF8jpFnwLFinN5aLUk0y5YKTEMT5atp0+EOrjxPTKXt1BirJkcGJdAIjjfS9D7MX
d7Blxb+u1WmYO4JqlKlR7XCQe7y9/aGlSQiZpy1mqyvsmadktBY0ofbiPQpSzvwER6utZ+XB8FsD
yhjdCxembGWggYoZKEtW5fQPVHJ55JuY/uE4ZwYMxuFdy+AD3rdBmqy/DF7k74xlOzHYAgJwVjML
O14jsakRzlAoWLFeL3Nq61BZL551K7TF1vfEWqHZ1W6AvihkdrxZXyTomwMUPydU2EUvHHhFU+Tp
x+LgaZcdxXwJAuCCBegktMeUKVVFiFTwfxEUMOF2/9eZmFzq3W0+a1gAeExVgqyc7C4sC40S5f5y
HibJ5GXri1UnEHsUKHy+6/poZO96UAOcRP6ORc/b3uPjvJUYQx/kUsmZ0P+j0SzmDgmBJeSHS4ji
oa+ffdDn9nhqnXM/MvxlBsYZRfWvuGpyc1cU7Wb54Pc1CDTCpM3eW3/xQdZsaX4BUohQu4+n7ijT
Mz6lMnqhf2Q4kpDO4QrT1Ur77RUYMVDfdmJb80qhzcVqmR76KExX7ykYXIKl/zl9HqxbQ8rpD3G6
v0wsAGh5/YkWNno0TCXcwcYVW873shkAZUrBO7hPiiwlZKbw/1EGMs2zTvqRAOc9+2KjFHhF7s6m
FasnXJuPYEvVDfXNW3EpnnnieLO1E+ozUvYuImC/0k6L8bYsWfrYtTBHeDYADKCvgqmP+PkppdpJ
5U3EitGQf1tKpaO4n5Mo6EwddWml/fe5HFo18wUf723Ei0i1bp8tHP23Hav5ghbQ+kCug/ysnr9Q
joZZrPyksBNNQGTkOFvBLtUsbss6+7KStG0lBRbm6Y96wyq0mfJiPOEUn6nFeOu+AsVRN6MhFMjY
zZcdUpJOEqhlKSh5uzj0a1mmTzl7dg9s/bh1xDDnNG1nUUocdm/IYT7r7dzb/NVf9UiU0m2mcc6A
z/ia4nMTJhrGWsMuz1MSkoR/VDFhD4kOQukdMvjufLbA73LWHtcZ07AQnQe+KsoljAh4pm+DTcAH
FJQLcJUzE9DHGjUHBdU00QRoRpF4xFEKVM0rMH4mx8LyYQZS6glbiwzJTLGTCJ4/qHJ9DWhSd0MX
7vIgZYUuUQM9FOV9FBZNFPwNEU/Csn7lMyIc9VTWrKKeL93XDhOMbwhBqaF3Pwavgb//o9xoP0e5
Lq5UcVs5ejRaPIViEEmyzBEJiAg9M+2RGVgRrMpKzoUhnrcSyw4BG+VEODdet0ARJ9q4SxNCcXgN
UTEoPdBnU51TvqwCm0S6Kr/3+n8vDdaboUJ0er3OC3GNmYDUxwvhNhlXBH30JZsx2YNjSWqX6UCk
NoIoj564qIg8VejW7Mz+arqBBbPGdhFy6dZcCSJzFeflPQ48/H4HkMjaCTc1UegGN1QR9osJiYO1
vAQ+Ois+fFFoAXfnHC+8Hepg6GicksHC+GU1R/wnYXoWcscVo0I18FL+X9RzykcsoC6kAuT0Tp/S
Z2GDt342lDnenYogqGNcMGrE31UWWv8d07dpWYTz3y1BORFP7/zRYzPiu31xqGVbnwel9/NRdM2Z
Pr6iHkhWw2BS4wKb7fxcnW7Q8lH+LIVkTotQBaOj/w+gWb8geHX0JaI8xEWPXVYo1cN5+F1Zx5Rd
9sRk9FOzyTBYyVtv4JFMgDshdzrnSr5zhlTm68OeLBTiCXLcyLzdh8SlMyaHWdqjifU50wNK1zCb
WWtQyI0y/L0LNOSGwc4WWpm/5P1/KBCI038oO9JAcHWrjFZb0C4fFP1UNoRzULzKQMW751IJIq3z
PCFjacsdC2BmXJgjF0sqfiAP9DaY/otd5/HURsXnRnXU3oOPI675p97mZSVg67cLCtu3cvyFYpwL
hR0eFmMEoYSmijsHCuVsSN3BARHd9ShMpHaxnB8RGWJHOgJOT1Xt7ZPUeU9oOcH2QlK1ajGdFI5T
vvRAlME0sa39Rqm1Efkgcecqe6bjL9QbjFoa9P2C1Hgbp4O6W1qctoUCdAp8qzH05cW3Fk9Ty/k0
s1BTbhgkgoOCIt3f+wWceIn5ylJAOT45jFeUS+1eON6ywwy75PytMkyfOaGh/QJTE+nsVRaviN1u
gz61wl57YrRaTfvV0KthhL4aDr4qt7O2Dg09Du6XKdtQPSiSEfDKx8gRPPXxoVTeFqDUDKyml4+p
lLPfHmrFXlMFcTVPZo06rY0tdexhr0SVmriNxJ9fmx2lZSTY1HuL/trsXB7k9oVFXJjxVwcrjuAH
HmDolKQbQ5fcMutlE3utHcnpkilighsoqpLnk8l5aSKHt7DYmbpZP6eHp73VhkZ5gLuoBKzBQ4jS
FBYNDxcS9evnq/KZlhYuGqCIGdfYbDpZsIltccYWI1gTlPb2x8OFQiHzFUoRZ4EX5MDM8/gsEHp5
E02vKn76cj+V2D5zO+dZi3plAgkYE0Hb7C7823eFY9wgmBhz25thJQIsduD6ZsL+JC6tAunp8a8H
xm6SSwiglEIDzKx5TfhPMDJ5Ow6mvQ0NTD5olo4EZ10OAjOrSO84T0y8oQZsC6gXz2hF7NbDIRxl
1I1H45gB+Y3ULBrxRWKPlZa5sULVKJ9obTc2AQQOR9iwPcZoOcSAl9ej8H3MpjZAmZOHCgs3xeiK
S/Uz3fNQdeBk06FeE2f4vJZXFqljFZ5yoNCYvDPOYtxMh/NDxANDNPpCyN5Lnd4VNzYEtlLD8QON
iqOOde4e2QyNEaIkqb31GiC4che++Ka7VkeWmPr3ub3fRzpDy/zCKGEl7MbrGQbL4pSz/GlAbyyx
FXY2HvO8VoXZdwwhxJA20/Gt+t6XNosy99A6d/7C/O7sfH5+nvT5t4luhF4LHdntFy4Xhp/omPnO
EE1EpEs4Dc1S5M+O10OSzlKrqKzFdWhncYkjAAvtDLT3LLnYYvBJxvb8XACM/Qh7vPektdIa1Lre
Apl/hFv76p//8pG9iTq4WTLT7CX0doHt/UYEysKLfYA+CJL/3z0Rerxar1nOizYKVSnXTs/cnQNO
vBFRR7oGDQz8RGlt3s87UcvWPL0zf9pQEKFGIINRrZdOiU4xoLz2dXBxM9TyxbjLUbfWb0DJXM/3
LFuWSoJUwwFQD4CiqxfIKtRXtdhHAj5J/kzJPSb2+3adZzowsuof8KNfv63eZ1TuX26fiDH7IedB
SqlYpPGnYqIc18CpLaXUbldFr4dLWB43UXHU5K+PvmT8fCSQfC9KdXqsuTnNGwBfMbvuUtYRfcAF
pwAj0FUPTueRO+2Hh85/SVKbUVcw7o6TEUaAYpOrbvDKxQo2yTEcYSl1XOTVK2LNmtHjCSxGA/58
BEes/7B+1a1osSKyS5cEKfx28UWpK9LQY0pVW8MHPFrfWCNmhdsbRFgQtk1A6WmIX6ANJx5HE327
wFseJPX07m9RDRLBjhbcBY42uyDxX50VXkoYN8/5KgZbt4sRgnAJbnEGyS9wVMrGboCwbFA7zhH6
u7B/zRTuWtBiq3dC4JHchbXUi7Nv+82SkCOMY3Q4DNTm+ziSZdHIttfHv5xi/SmO4e8HSy+44bp4
ofqSxOOYPA4fiJc+ZkwohMbJihDwdioz+K5WEJFD2dnsx2CxULBCqL2Em6AvKvcD5sxC2sN9PjEn
l0yz5UzFZMCWa1Wy0Br+U7N/h+rc1ScicVY3f+HnxmQ6HgxRYMVdR+0SWjtckeTApzqZAambAGUs
7/CfsvwaOk0Z+qMBJsMFVP1GVQirwKaviUKzmpdGS4hLqpB1MN45zOMS/fSFIoFRmuNZqmEXW0eL
dqB6McE0p1aWyYFGAXjRZWOSazRdZWvWo6BaFgiqhD5hBujDwh6ftXkvpawSRoqnEjiiFo8iHyR6
TnLci6OeR2aRe1ZAiJCddIwOFEmeZXQJbYE6fQ1yn0OEJLPRX4gDuuHI5utM2vfqRY75/d4AO8I3
s8kHn6Isyf1YnrbQr5qNKjahUSm47QroTnuJIfwLp69aqut7slXUuJeaSlG+jdX3o48TVnwmHWDc
4c29Q+qw2SzzdVj+jWAcVxlvJyLynD/6CVk8uaLZvyyJQ/gUp6cVPC3kl3yjuF9dc8bKRC5NXz4S
7u1jzBFJeXVkvysUE3qJabG1D+fB5Ea0seir84n0WdOdCzvQFwg72fiowp7yIpDIOAA2q1B+G4/I
HP3/HAWsApK9MZJQTNeirqsyuSRYADD3dPe43nH6Mol4JtKzKAVsiuZKxujv5kIWYPazO+ngVkK8
aUsFy+f9jRHk+bP8qyyKaHFcCg7f39VihoCOxEhrufS6oJ2xJNIp75rRPmG4uWHWlCr/zlCT8FQM
R3w0QCyQpIb7hSzZdU0CMa+AQIUwe6VUzWSeeftmvWdgTQEVb+13oTN4BeQ6LtUkKidxxtTPdTDM
1quBR4kp2BM+F8ONwroVNmQ9Q0OOJMcddJnFB40UClVQzypPS6wGwAW07w6Rlq8pXcX5FsLlNRRH
1S3VNDv5Fu7hHYLA/nTCOI6sSr2LdidIa+vPpWRy01gJaG0mJg5AkTWfMofsOsEIAWSBwR/7ycL5
0mEXBV6IcGXOrPrE8fjPCkgPbbf6+0/XKktS0RUBfppbPBAboXzbSYcfhKidsj6VPqvbwQ26jR/m
hZWQHqRAdo9I2PvSZ1ZHFY3hoevySU0p9CkEYfAIDep9Ql56pdsIYhRr07MP02wpXPBnOY//fdEx
Pc4pu1Rgh8CL6pFjLvX2m0ieAa/2inprumTRuQEVq5h2ketyqyTxVxSZAWkIdUWVx4T8CmQE2qiv
pXkyVPrcgyABLXW59T2LFwfQxDWxKZC0nLRK8rto/gAlUr45aK9BMuJkbQbxKmwsB/2m7Vw4UppB
QpFDeEXr1BxUy6uc00L3gvL6zU2oZXaWIMUIHR6HRihOyr9M5ir7GqwAiXkJnA2zHzkY1rU9u/QN
lKxZezUZFwRAlotukmkQQ6tTv7SXFN6NJMQ27yhNFaifVV1/lpdjKLNluAnjrmDJxwEcygJtN/Rt
1bJ90rNP3/n6R9nMvCZYsmyT/zU7qxnWnE2RAh5b2zEvkqkz/I3Y0YReZRsZI3c4ATdAduzyu5rN
4TH2iSddiF+r5CIkjXZOmZ4AG1q5CKyQbTnDO/7LzC6eaXLipyAhy1Sg1oNnJctEMaxPiQ4vK5TD
Xy/IeksOflwI4boMSH6xcMeyHTz0bN5ctlqkHEjDhPNm+QxD1UHex77dXo0cdqlQIQTUFFHC59U9
lxd3RYteF8xaqPJvO3LOT1bwQU+4CCG/DkzwdPa8dywHV92hkn+aX3i3IZU0cgNw2B0veQDfxz2P
Hxhh3mMDhbtOH5xozu/K9r26nTTyliL6MEcBZK/9YfqgRtDvv25wby9ucfQZNPDgUcuagMBkYEr0
ofMfnXGe/K4p4sOtCQA8538w2Qy6LgDAPg+dJj4ZzeQmEEpOFh+uxx1NAHYlHvMG9NpyalH49ntO
8MClgFW56KxGH4R+DLXY1ciZq8y2PZus1qc1NlCHnV6dBAR2xV++6sE8kmx6BZv9OKNZ72og6S51
xFOkAd3+WgLechTDpzBj219CbfIKvvL1//ZE51Th2uDWZRMHH2sMsZdwPgbsZtN+Gv97QyHW8HF3
SgYqJLvCMczAkAzSX8vRxgT6u0qgrUKKPcDDIHvTgsd6MpVnHGGm9ocTcAcXvqiYUvl8ls0ChwAX
2QWLP4NuK4NRykQ/hdIHAFfZ1gK4sWr21HxGBZAgSxIzlMtpOmCsdI/PWXI0EY/rAwv6nKjtjeS1
DZqdywBDcyXz8EvA65WVTO326/NitSEFiIXONx9ErPkuUSozHJc/S3MaHIqKl3Dng0Fs5L5/wqiF
0QtOGqpFYz/vueX+L4Esq+BdDLG7qzoUTbh2s7rLcPhRT2Mrw19sx0MmOSk1YwgPaw318I9hRIzW
KpX2q1gv61I7bHOwvVat2JM2I9EamMwLbRRldHB0eBlemUUtRT/pRCNVsWtloeYAGGUD1N+YNy49
H7WiBt8BU+dzR7Tn7NuO+s9NkzGNB6DkswwO4ky6RMsSQj0Rh2c0qHkdgf7C75Tco5/8a+MyYy8F
wshWV3H82GFvGVwkZI19Oa2m6yPWAx53JC1TcvUyCfATkbaxzQ+IRq9+A+6cKD8HwfzKoqoBtde6
oDdGWCs25dPvf9c1W/I3wCNwIscBpelFMgEu9uDlc89ze9h96TYCVZXdpBazP8U9uQvN254Q9M/w
FOOomAW9RWTEV6h67m7CMTkd8BKughYlDNDqbMQ+luDfNNkpdyGhgMKlIaFG21JD3fpiOnfFM0Qu
D0WTDx1G81r0yY7/WKVFrnCZZXPyv1mAhjQch71Bo8y4eFRY9rzrgISeJJslqHzNvjNQW7980mxx
5ViQAmcmH+EEVhMKDFp5rHB8E2Bhnt+25yczcukO6RIHvS+LB0hceLgh20o+MT/GYuTduwtFZ0H5
wlk0t/t6dFbQCVf3/WhIygdaapdF4uuhneVc/AHUXEzS8aFSxZ4Oi+8++6Hqu067yPNu+mKQs3mY
0e1rD88FvSjS+sRRgOtbT33LHm4jiB5ZYWX1RTcOwYXTXnCw2s9/uYF/QV1HVMH269ZIjyLvWWK+
Q12YpXE+auPrL9F29XXoGL+RDIrUT1waUUjruBaHkbxTR1UQxuvrIxdBAIA4oZvhFF3YJ2wtcz+m
7hyAHZxG0F3+54Os6g4MQ+9m8bHZWLiHnhpNhsrUJeCB66Wylx82g7stIN6L6OXMo8VhNeY84BMu
NayLxgyL8aPkzluUDJb535P6q6quaiEFezt/rXrLkFj/BdfK/LDPTYpJMPCsvjmG9Ho9TEBS20Zh
463xx9zLcDizsQlUtrh62kJ83Tex9NlQ+meaQ3rkq8Hym2ZgxZwh9C27Dil/8xJCr52uUKx5lSVn
ryTrRdTt2SObsfaHGHoNZJXzeFZh4W2UpYCr8wkYTV+CnevGQTw9V0hNSs7Yls4fx5Qh2jkNjD4X
c87k2WRilCkU/2fr8+z8kMhrBdLfJUItCb6CuvbjpGsqB52mZ04J7Hg6rb70o3cQFewjbPsOkp/T
ue6Lpmw0Nvfn3PnO8r0j+XzTRgV5uj+lUSoHI7GkCZ9hi7BRvSrzfv2SAZ3H24eeyB2NJ8plq3p2
gNhxLMqF22yfifwAkDfBuoSwMIHqD9PJwHAX2XZn0RH2XdThhtP399XQ6E5Nl8+i23ZRkHuW0O4Q
cvp1HOsZvwA1vDTL8gjEYzIj9X4jYjuZ3aXy2rLw81SWKjSAuma42BmrxeqkUgYxgug8voHusaDI
Vdvu/579wO5tgPcrJaWvvtXGQ+uts1hWFkP6qsFuGORKBDY9kNAR1Ay/qhW9LVap1DNiz7HWe2FC
JT7GDf/B+JuAEp+QM0rX+o9bW0JYzTeQZNbDp+V0XzE8hDu178TTF0ub7iWBwq9/peJefPreQK28
O76g9DdUQ5fnaELd+ln2g/l7rq/hnyBQbWc2yw6Erw34+9uXvX7Wa8Kb8tEC/b5VTrE1xFyvXr0U
BtMS3wZIneycyEkQLgjtlnZ289fj1gBbg8vwbzlpn27Od7h0BJnq5+NOayjoC4F7zSG3aow04CQu
cW/tpSq8q709ZqEIlGCnR/FZJKLvTyKeimyxOgujo7GDJMmjkTQVhbn8SPj3dJqDIpR1H303W1oc
JTXF5Az+uMZjREOYp3bXsM3U73CeoUt9ZJiY1GsYJLuLgeztOTtG1+r7R7WPriszEk6M6avKUQlp
N95YcpUBTTPTNNNSUjUsz2CuYZSCesUNrel3zwwre6rXJtoEAc6tkJJxUnjAVCT/tSklaRHPvFYz
442GzDsVpIsCs9cNT6T6NA0wejygO0UeV9sjbNcX5NDpLfxSSPqgclgUqb6EfR3BTpoxfW+ENjDp
LD81JWgTIooRjVt7dXawsTpG1Y+Jk88rf823M7AsRW3go7DPI+4cMBwZrnZK7VpUiSKV9qRjU7tl
t4AOAdbEBgF/eykfHkoyxdh3BWKsx5VVcFDMHcY8TMqUUJZr82bhDfF9xxHAbO9GS2+fUfLoDPNT
68uXYvS6Es6PkDuAN2GVydk9r1iiUlA7W22MEexGc5T53AVgmUdtHDpXk/GjHHRoCtftYH+qn+3F
tI34kkZiVFbeHOKMQEy/6DDaLX7NV66yBJZf5s4gxCY/qn9COOywvWnQ02ZNqsqNywLx6TtbO5Gn
RJL/5JkRq1kD8ylSiD1VyQ5Fx7Y9hc/e9hEFkJGe24Il4rTQgCKb/r43qoiSA4q3/B/OuWhyeceX
7HbDj+Zsv+DWS0FVDxaPFcr9h5od1zukwI9w2qETcakq6LI23AeHLdiw0vB1EjPwO4+TNsS0D3bC
gjZHWTsRqHfuvio5v72+TnHV3HPYGvIPeu7xeDSFm9yiSRUEejmHIaG4pUSvGa17D/CaVQ/DmpKE
lXzpKMqzj3pWbBYWYp9hSoVD4Wsnkw1HMhyfBSzaFGByXzFv3np1yO645NA7GU/77Y7jvOHPsCQj
/gcwUFbqDcYlUA1rxJKpDmTQu3RiIaxI/obNIPJZ7hQKSoRYAVJLchoXWLFO46r6SyL5iVsVfBnX
wf0LmCU5LgMR1s3gs4rJyTsDnhlWXVoJkRaEQw8eD70h8ppa1cirM4aGcJiQRFX39h/5bvMtsEYk
ixJStE4AoTBK59EQfi5m1M+gFOVZ/vQRfGHMI0MQ6xVBoGTKdy432El4BR0JnagOkThbROQfQeQX
b97F4cwiPjI6G66awm1Rv7Ebc7OdeN9guJ1oUwRvVZBcfdxLV8oWQeCjYlq65HtgIj/oT7izngQH
RftDGj4gCR3OVjjKeWebVi36vYmseBnZAZzgn82keFilAujllNsnjrOtzEJlYL1wZayFkiPSiUIR
Y/x73KIuhaljPdIAQ/0xUXerotqH+GvV4H9efxnr/v4qOnO4QnHPCo/PTwz/zh0JhsrwqH3a8R7G
c0zWkYsELO1daIOjDNZ2+YdHcWVuhEB6isQo1aWy2Q+HI9m8ir0kF2+Dr36uWuiqnJVZwJcSHwtY
7SGHHtE91tGVbdM36zSaenQT2xPQnP6OmyXo3tewcmn1nQu+d5KmLQ5PYddrMFfejVEdfszeI5wX
GoVGEBKuy2LEocZYM7gaOwpn5Uvbgl/eSNOrup3OZC6B05lAAtxKK/WS7ui1qMGVPt22reS7VfVz
zBlzYEkVPW8Hii5uH32zPiOcntupE/DQCkleRsFF6ZcQygfF6m/s2dQKLTPnxWVXL0WBu6RUfrIP
xn5c8sEZpKg9vaiaZNW86IOXCBDNiJ0jkLIaUrTgC18doL6c6efIdPj3xTk9hRg/O7WN5bn8ma7Z
FCV3CkMcGGa9ziduBnZ3tY/WSutLDaVWDcdsK+il3svkvu0BwoBkQHfGSL88XYjZCRWIO75PR9RE
ebhcxwS8v9QARNJ6Jnqir7d5zXMLhFkqba5cholsgKgGeSdUaKJVmFUrsTfnmsMJnLuDK9txXGWd
mFQ71Ae6iLwY1k0Gylhu1BBrXNvvvfV3TnFTC00CF8s0HQb9bJzCHiLQg5nkFFEiJZTE5o5b1sKW
NjEvyHb+LiSSC2HMZQL/UA98IMvFeWdnxXkOsManQ5aOkV4ddp/Qp8qvgREQXxPShi/2xRIRV21a
ajdjvKxyzZQGf0TFjW2/6EQ3uKGCurpwixf6cYayTUhnYmPg1OAClp9lQRbE97qyfVBgmZ4+VpE0
LqcdYby05FaK0djpzk/P523sQ1g9jdTCL8pjT1EpfbI+GOOBT0XXpo74h+lJy4DijYi3l0ZDqNSX
yeUq1S9l8u+qdv1DTTvBy1HWfyVz27MM1hCYqnaGBKJwO60md9VtvKjogCjv8MF8zTciKRKqX/Pg
Js1euJiif1HcpCz8yhDklgEMeaJMUkVDRUQdmv0Citu4RvGXiF4HXlLw10bpZu5tqctxcPxxeHr7
hN4+B0ysrhlw52gu/ZD1rsgBtQvm8eJ/tlPyMP9ftIyjNqqSaH5jeAp1d7qzyBgay97PleLvDzgH
LH7VDeX3rp3k9t+AutsX0/z0o7OLe3WCDt0Xws2jB4+AYAiNvAY4k1wrtf4Lp2/XN4miS+YRXtb1
36ixpGO7uZB0z8k3RHHmXdRsNmtmp10NRhP7mjV2DwWjPT/hyrOlwK5svcU2TEtpL19+k756SNnk
BLR4A9/jV2LzD/P0nrxTT5VMhUfCxoJGsw3n0kokn33uIO9OuHH294wDJ4No/WQzCPJVJ9ea7bcJ
uSf7oC09rzeoeXigauvIDNXlEAnEKHNX1XuPKqP3ExytCkrBA2b4DluNhKoFDuH6Axygs1fB5ezN
XAINtXIuHjqmSnj0KbqBFHjVTgPv31c0zbXDz/vrBAL3dLS3aXOmDf+SpZzeM3vwMDo4bE2cBhZe
dBLMpqU2JXGTL34nDcXC8FOZMEvA++RStcEQsP+XupigK1SN53eNq9earYQ0uDawWmCBT78E84IS
EsVLWrfxz7cZ2noqRc0DGb/Fok/OVZgzRfbuTz/rsQDD5wskIgv/jOywP3JsM4Ww0qoBkq1oEz57
X+Z6Km0CDONgFQAIRM+niVFQMeBvXVWCcoLo0bB27JiOEySz7Z9CSrCohAkx3l/IdDgaknyy4iFW
TAb57iyTGBZI87oKKdqH5lV0K2DHhn3+wIKL4ej/X62l9DrdpyCM1lI/Of9ciZ6WaSYnrRVrc+HX
r3ZKptmWeviqoqpaR5igIiGSTZmXuCSw2bhSZwypQCkJ5MJZonwT42CmL+ZZPHfbCcVvt9i0UIK+
5gn4ZldCirv0QJTFB1lABazTSH8vX6ga0TyfEOLb4+YaffqT2IEdTGPhwPzKcG4/7OWie+jHfVGW
BpEN3B5OW3g3j12fu+3fzUwc9h/ozTknvbeFEoKwfXct7Zz4pSECLMcSYf4NOJ7dHa+/TN3iurcN
FvPQojozHXRT5axSheUxPvGiW/8xqmXgDoFeoGr3IJTqM6xX4VDOrpi63bxnB+zXI3vXu26JydVF
O4WinZ+ZohAomQuqF/wD+ZCiU4iK5bjQHDPEvIe/pLeXKJs5QzJg2xN0Ou9g9YHujBBY2WeFQz+U
XXvT15EOs3Lj3NGQuBUS1WMCHGeUs2EMt7ilgSz9lD4wjimiS6UD/HOJZesW+gywvaS7hiKxeZ3O
Qg9LtskAR/x5CWAaT9Il7jHC0e3OrH71oGugkOEkBU8dSaqqbddjczbU0Y0T+677aOl5C9xzO2im
P5t+5+eOc4Ob+33LSwG8KOESrGgQUC0vb1wmI7Plk+yGbeel21+TsBCLch7VZqp4V062CF23Fi7s
8PL/c1hfWm2WUWSfX+y4U0KvH3SKlXJ+s2kH8AFVg8RrKHiSkzfBUJULIdSsbAiJi0VIrNFe/mom
13MSNJ+tHLX0a7t9dVeFBAgVSqF3br82xf6fkeV+9TmNxCHUyXpCWMoj8jghoC0toSt3/ucWyzCW
JvLQm6OR0Dpnn4/osSLPoGtBK9o5CRXx5EgPQ8INB/+rtK0xXdYVSwL7lANv3/2wZEzw8s2e9kdq
LHvcEGWs9qijtqlrNHaoQYwA24ndb9TFjwP/tZeXQYLIWJZJC1OFJQ7dgfTKBvTpZ7DYVCUyeDaP
EN0ixM/HLBfiBImEhPC3H/SOHNwOAmvcvJYMZocQSFr8Ph/wi/JcpJthBgOmZa6ay6/fN6aF0AQS
RPsvcYkA6uC+x42orQNwTdh7ncZpexrPDTeCwek8DvOQYAzY7egtwqtGmjfUnVxv/ZBe2Oj+jnv2
Pi5vpxcR1YnhENCfLu62lJwPAIMUqjrf31Of6LbuPh5ncivVZ11/J8MAnjV9lZZFQSg59ToNd6Da
BUthyVjSb+irW6olZP9z3qlfkr8EoXzSJw+BCAahdO2pxQkYMetyyBM+LYDXX4xn0YcD5I7hg2t9
5QAgPOqY1dfmE/R9x09uzXlXF1aeXH+G4/Fc6qXkrRWjXDakSYsF20T1CcfZ5XSVsZuJ/c9enV5W
Hnt6vdyQYDwTwpakkMUVh598WBvEpX4rSI1tNK9gAcVXdUsXI2aJQaq+Q7YhlbWXablT7UypxQxU
M32MorDxQ0jjPFsqRgPg3t6YVdgiq8LmhYLPbKOO7mxOBk0kU2Z4PfkKro9GuYd3ttVzD10vo8f8
p4obbxd95E19Mq54iIrm5r5ze3gThH4yvvmZy7699m4El41qxm92zowdCab/c0z8ifTOuwJGw5my
CIyy6ogOWwFYIwN6v7SCayvGS9OTqGuLSlpsjdy2SHH0gh31UxepsOsivhhHy3ipNymQ0xpXSJWv
Jx/hz36YAdrcum71jCHw5Axf5AC6arSFQ8ifXjagf4/tgTMfBxfBaSi4LZ9IAx7gQ3oFDnuU628Q
oMloT5KbskXWcbmgIKjMTA1rpByvhOpUOG7h6pv4iLkUsrdrV1GyojnwMlT3OH5sbGPARoTCYMqt
qVKRpLMdowKixUSgprWwrVcY6IxMBhSc+1wpFslUIXPlWNcTsvb80qjPJbOWQKgelsyCVYlWvbK1
Kx9+6GwAV/2KrPhyhQS3+LppIuFSIC02kvD63FGFF+8FZ5NdO2iER9vMvq+SJYlA4I7jUb0tKEwz
ZZF09Oomn504oZ+zSN1jucg9h67Sfh1XcD1jxHBjXJBb71HGcA3cc+HWCum8WC4EFvsWEK4JFojc
DGKGZJofbg/mhPAKwQxKuzJ3MqM7A7fDeyCfyXvFEMbwWzcn9lcIUdoODlWZOmNjXycrUrUNAmH1
F4WHbRSxi/6fn6yJO6Lvay4lQEkx8LT2ykmKO1m8CgqIL/sTzqVzbabu23bnA2yUnT+J4bkR/18N
dR3zwK0y1rYoV4pLoLJNkte8k0RKMjKLhvZMDpxBrnZC+JlP2AdyNQI56EweOUJNimj2teskTwC7
uil7RiTPkFBhepCWYmQPSmqpLqlWoSOro3hf0tcpFcgBikBDZ9pX8H5D6J7s/XZ8WxpKwa7kKz64
qgi2HE5cG+jXRIt4lPrK+ShWeQKcBmMYjTnj3p6Hvkl2ayiEWZCSY30JMuiyUIr1TlrL4VdE7Hux
/d8oMRRUNIOrDs+TQSLXcELaGe7qtYRlkpdnYrmlsjuF+Aam0YR6yeShFxn/AEn1DaoOLS0uXWbx
QY2ppeadhzmSEowQ2PBl85zhjNsUkuML7BC1G4RSXxaHcF1DR9gTXdF5ntyJS+GF/pYkm2FQnk5h
mvbkKZ8uf7WG2lM0QX5wm9gtVkxXWZ4LwJ3T5x+I6/fxL6VQ76VOweb/dO/L/KYWk6i1jXKPv6Ff
wlUG2f3s+tkI8YM/Q09+FJVKnC2YqQ0C7MiqJJWQIAjbCZ4bUVfrKUQPYNiNlnQe5m5Ox8uLt1Wu
8UM78mZvH8OLTUs9IwkFuJjLYgdNhVx6074rrbH1C+rYdw1xv/4avEr654KtpDE/XlmOoCQFb9g1
6a2Ih5M36TimpF4IvcQ5wVAKprJbdfjNhp6ISyNrSqU5rLwAzXv+eypRFMK2yIrdMtYzfhQIzazh
fruLpVnUASGW9TWcGLlK0oFAHRjAq/T9KR3Fh2T2fo+LrX7de+i6Q800d9gtkndcrb+i8Fxk0fCs
kb/13H9OdKVQYARWOoT7CYBCKGHMc/d6VTcnTDgcFXZd+S4TPKvtTWENA+B76+Pfc1UTjhqArWab
EIy9NBHn4PQzH1kAhNEADG+FafDgZb0iUcqhqJ1ZgMZssBrbHsJTzBsWSX23lV6pyY5KDHsnI7+C
3ojVactNevU6H6le04ZFe1k5be21s2rPYsngJUBrV87UL5bQALxY59gYN5uqp3ZMoVjzVIaUn1iK
OHXaQ8vKeQfWvI5G9ncFuXonyla6K3MddPVGhLyVQ5hFB7kY3sfcQMneHo2GpWGB0kfGCGcwZrex
ZnGerLk3HZpWIT8qQhIiwbCigrB2MFpCjoQXl2AZgYMrafu1sq39+db52WbLfbd9fskL92zIG++a
5OSC9jSqHgzifHaKf6fAWL764PeT0Yf2XdDR+XXPobdS494mILS1YAXgrLCHwPNEQsQHMbllzw10
OcX9qiszTjUOtxkZSPG2Q1ps6OYiXHy61aekw8eXLOx1xHoDQBDeEW3A0Pc8XMOkjhWMN8lfz4Dj
2j9AK4Ybr40HDys+cVXSYR5tdW7gPabErvs8oO5bBwx2duq/rRxs8YaRg0sy6cbQSKepiTBu1y3/
0v1XgX1DNxOwnoKYJixLsU1Ym3TdNtqZJPzkVsh9Wxhpp0cXx6D95FfZgJJZOYv79kVSs9Xog3kf
IEOav2ebcHrgU9lcP1AiqRYg3+qdIF0TpYS7ay0KKHBLSwriNh7hy7OuLHHfhpN2sJED3jTPz9j/
vEKD9Pm8FlOozUdZfhE0qt9qA88X0Uq23owvREqB1JA+D+6W/D0OAmRKX1xqqzwqxdoj9EasxUN+
s/VNa8dFg8PTyxs8rpwzcc7R4CJ3gHBQ2Ua4CN6tAk9GDZ/YXekSGtJy6WYBy76ay38njky/NXHq
pzc7QlHSeWtwfH4TPPd8H1pf0Y5KqveGW+MlLrrzK1u0E5i54UatunIUqaTubgNW9GCpGf5eZB0y
lPPiH94/Y/3AEDGukMxGTF6sFr56Mju/0pw04/ul8PsN8DQZdUq3Wmx2JhjRotg30PPqp2IceV2u
Lqw35qx3OElp3t2SixGcfvM7h8pN0362GfUZnnMqZSYquo4LLvet2dAjiCx9q0eZFg7hvH26T+Fw
VXFY8b0fDAPOJVYzkYGEbbnwYVejX5BCajmYLqTwUvEELINozu9DmPv4Vj4oC2PI2a6lKW2JCtT3
6ytr7zvEuVpY7geyBjQFvMpQ6UO4jkIkp82FKqLXOOKIZKovgeEthR6sjaz6DikurOgnzxFrPTju
5lcjS26BP2W+zAKGf+PQkWhjgkKX3l/hvKOjVL/fq5ybUWyTTYgyiHx0Fx8B0KK1P+KmyTfQEjgT
43OiwZpEsCgrdlysg3wa1ms7RL60tKTeARAKWgQk4i6Gpjqs1RpCDG3XxWbPP+9kF0JEbnqNL5x4
PaL9wnQmFLZGoWLrX6uDQCA9cv05WhhOdkXydNSY0VAr8zr8EZQhwwMh+EgqEdqiyfTh3fWX3OXD
leWwpcDJ0roLU8EeUkoW9MPd5i3KvSARXLxXdiJZMcHDFsj7NQ7o4CbrVUT43S1L3gbyIgaCatQ6
CtrhA3iHEm9isqGZIT7b8VnAUI36nP2J5Dv8dh7EG06azh9m8Nrzbv1s8Jh+MsPahaBSaou/xMw9
p0YPi5gX/1iqqdgoqekY1E/TIovnIYHKwKTnNb7j5V8NKJ9UKEhqE9ne9Jhd6Iyz0ZxXJnB2RQ/2
nShnsgEDR9xJ8+OfzvAV6AaLOrEaeCGc+PRiOHO+F4uOg0VXNoKkEUi0peggrmthcs4teQUvCdKl
CtNs9xc3PDavbHgUHQBN+qwYjwn5gAQk2bTs78NG+h7HyGKenk0Muo3ixQ9yA8uzS6MFvrA58i5W
cDe64M+eD3tDRTH58UdSUYYUWW5IEUX+/sNvfkF8P6srCBq3eWrWAGfLi7Gnr20MUOzMjYXiHIXQ
t/vecvxuKG55ktQWM4EZut9XF8ibyD32PLYMRI4UcHH2xuAaZDdjGtR+JXf8VZfTCkEwr1Skm08e
mll1yk8ykyR/QSchWw3P4UPDL+dyyntaxf/aB6eqAEkT4KqdGK5LCT/szsbhe3nDJ9Muhg+whH9x
Z7q1fPlCDlMKvWqmWiTpgim7I2W7PNuIzWKjt61XkieW1LnuJmSWYfsLBK3L3QdfTaDTJ3xFgtu6
IIBLLs6egMbT0jbds5DOUVeg1a7emKSzSTYjx3KOzeyPXnFdFV8rLzT68MUFZOAvuP0xVcjVucaS
47ion9yLa05LwFyXv1Zv2pvaBcBlZVx1iPgMovOQnw1D7n/8iLCKEEJXMa5MkYslWZ2xRnDyjf7M
E+JUrOD1uu9K/JjeXUI1QfSKmftXbz7gkzCqyDRH32nqqGh3nfLWkU29/H+5gU3GeilfhmunfeTP
I4/FJR3ITlz+oFU9mWuAjVPHekDkvZgHyL5LfQakkwWU/IlS57p1yzbNx7X935lAXaTvztaGvcfv
yF105bFxE9Wz094EB1FeVU+hAp6u2dlbIHwEUBWXPrWhU3WQ7TZ+l03olTJ/gNEKonuC5YC8PnSi
kuhlxHKvyS8FtnvVXUmPKsFOYUTdl6BaGWbd5zeKS7ysOsZpd6eX6/bEP+pC20j4bUEhDUHTCjEJ
8HCFe4O9yAsTPGtOJNcj8mIv925AXGaJMSqLLRDVyHht3HKdgfhE/2IAd5Gn6gTplGT57DaJhdq6
2diyDmzZzbNVp+4ICtITyhsUVm7bUy5IWmQfw5C4Visqeva8GJVZ9pWs41K2rY2AX7LxdN8NPaR+
TIYm/hk9qcMza9F85bZG53snKW3HJL7IcqaVVgexXvKh3Sq3d8GByixBfSL7aIDESlu8et9TKr0I
1n9AFo4DZsQLWIvwyNVVnFQS0gROYLwI7GZTceP34dukxl0RxGCPjONp9FBRvAjPqqkgz7VDUVdX
uaXM711VA2H1ylG2PN4sDdQvE1vJb1ghvhdVOGd9LxahGor18+14XWfAyeh1FKkqBecbdn5hpMhz
lMZ42NE13JzOPHwJeudYsuSvOICWB9xjJPlcTkB5C4ujndeGnsmost0H6VD6Wjg2KU83i6kQXEHl
lJas6WF3hRVDVFnZKwUoaJ7e7aNQ0nYdVh/6Z8mIjXUD0Y8ar9VHayfTmIb9YGA5WdLWJRhRe4GU
4CYeJzjv6JfvqsTgAICY1h/N69C3xXBFX3/mBzlBl7co5zB8TTY9u8OQgEtIof/UvaRXFJXx/TfP
7uRHErGPLGfDYzUCzS95YoOujORyBL2v2xMAALt5RRTKvy/yDJ/tGhwP6E9hPpxaDldIl/AMnw1L
caeMp0vNIgNDuZdIDqdzBujJw6XiaHC8xc1EBWwmO00qLsugM3Y6EZZUTMPdenB1ISeS7Ce8+oYg
P4QVkiZUEtMmKEPqYvlFzwQh8OMMctGPr+qpM3ipmgDeiLAtuCWQz1Ti3mQMVypEWWcnVG4u/ZEn
z9P40eT1mylU3u7Im5jceSso8uvbUdv5TC6pe6sWsCAWimerhvKKaoTxhJN5QrD8Rf4tbLPIna53
LRqeTd8351CtkHHMgmUkV7lmKgShtgDHHZeMyxQpKf1z91OOd0VF54rtUQqUDD4HfPpQe+oiva4u
Of+GBJiiXL14aO1qERb+y1J5TZHGuTBV7q6QL7hjDMdfv5baWeBUGEcI6GZnXPLZcXUr55SmWSS4
PoUxxP9AAn8O0cmGOe58iONeKHv5cVNh9SXGpuTcUZf6GNcl4fGdMg10c5SIgNZl9ZV5I0Mp7GHV
viiE+FGS+jQVgsnDbEL6qRyfVgMrFwVH3xa5/Yfzo0SRfFcw/4pSO+97EtogwPzeK923LJ1BPPhZ
rPLftm8pFXD4ibW8iUI7VAzOAy0QTjkrK7KA0XcaUo6WGp9At/4Xm3XQ07tF3U1FKf5iNIuM3wc0
zjlAuqlaKkT9awEJsM7DZreZFWDjVctmFSWlIO3RAzAEt+KtGk/EXOyy/7FlH0Vy1He0UtiuQ0Fd
U/wQEVyJimcLJemexlD3eokvGiLwXjzrwQ6HmNKBgaDpRojs/32ZMn+yqyBmcBglyerqiJuEoMh6
CuaX5sWOopHriiYZpeM4ckpisYmwcS5+u5If1OXXLfYdOJ4dxrOdlt5h2+nrny+KoRZedB9ViKBL
TysKMHl1DERORuAfe2AXyeB08DrfnXSFUwO0xUXeGhBJm4m9brd8JdoNgRFY71O3SZ44WFoVl9XR
svOoFtSBqHimcWdopybuDHE+08LVV6qtWG76IzmjNrCQbYV6xGzMn/iL1S/rPFTltHADz2doaCkO
b4QPuttNZhGYxuLI4CqUC7p4NRXkIht8fxcJAkf2l6SG5jnT4VDeAb0OEaUmrrv3HE6M0qFdW2QH
HNgNWQkO72mObUfDYou3O9QIhedP/4V+gzhxs6v7PYgJGI6HDEBaT4xp+Mczls8e+zx37HZx8nIR
0CVtPCRVPJm773hJ8TK4252dneew4xNgiVWqOt282QvxVrAxB7VYdNMK5Q8BmMIwX9vt4XM7dq9f
BNAb9M4rZozVttUK6J+pDSQlmX/OaU/HaoQLcYDryFq1QgBN2R/xJox7X5DkO+IGDxgKkxiUBI52
PrHBFLDAdtM3hbs7+CDczXmx2DHtKxVCGG2qb6h0XR52CESwkvjScP4LmMea/W/F90yDM6I7tDFR
FR2SN9OrEPAbMUPLuVkjoUJKj17vbLwYS3/u1FyziQTMiACkZvQpWyMORpRtSmuv23Hj6wF/sRKk
XA+bJGFIs1xO8HUaWfRUkWR2qhzyHyGnITTsfTaSHsoJHeL8GDqoHrxyIpKHbat/idRYfG6ahYBP
uuEZ1Eb1B/0WhlQrFam8jZkhshg61hyiHdcONpIHrAMXOYvZQ8Yd67Wr0fBAZYQi6ICpmX+vB4cd
nGwmOJJ8LscIUlFCPcsmmgfD3VvvEL5bpj5zqxtF3QegUzTXUf6iWIC97mvQadVO7zHYclEosd7p
0ESrfT8yW8POSvPtWRgQ1wxTPwdpk+4Kjr13kppWwyvk0dgawAVLFBkGBMxCZ4TBabR+1Trrffdx
cv39qio39/NexKsOnmENzDUwDZSyDFX1eupwnEUdGDKFozQooLyNyCNeEkMVdwz3MxQL8dXlVxzP
TcBIzkYX9f9r/rDuZp7Sn2l/dZRCfkb4zDMQL+Bt9zpWK9TYPeAMRuTc6FVbkK5Sv+Ry5u0H6cnG
9KvSymICqvmtWGZK5+ghF0+xaKVKqkt0D9gnZ5G9/vEjXdg1MaF/wIomJjBfnLUg3h/3AjxnYMxq
gXNkePdDkxenPAoeBW9xdLUqhJgdRsTNyJiYykg7RnOo26naQ9XyLsPZ+XDuGBnxSi8OB2+baqwL
oHwWxCdtFQjdxNGapq541Y5N/osAiz41Yj1enxY/HzRPcgQTVSU3pFFXLh1Pk8bzVeMr4PLN1DYO
JxDCIoFinhh6pLtil+AgvqU6ewMkkelRu7eXEX+j3MfJFhEeenb/v8Vs6rTv17FXhSeRTB65xoIv
w7coEumoxrHvv6Fr/8rTJLMr4NM2UC/rPiEjjoDAaTIkVszglCChoqQcDxaszCmD1ICnsjnC0662
+jmJX54iBcoYOnQXfjvgtOxa8jV+YnnCT/0qKGkw2d0oPLY63JSYKyFDiLhHxMTiEBx23fTXkk0B
qGa1GMJJhshnAMxWgC+CCqCIfZ3k9nTxiHOS3DSablSDx9kaUWnxSxa8H5ic044JA6InFQ6rOSUD
m7uxBJxs47U/c9h4mnhKs7K2y8YVPy7Xt4o3FxRcj15e21Z5ZDH7KmvxQjpmg/kNelAQf6VVNmbt
meg8hah/ZxrnPPdoMMc2oXeRvU4BlJnMDx1Q84KdCv8hetoZL+J/wLrU6d+0PnW2j88pQaKuaqrm
AiKCAu0U2NK2qIGIex7Z4puzkruoqv25kBksiz8hS8YiFnrq96WxGLj+LO/aOE6ozgwlYNbCXLlg
dxVXcNIwaEG49YvfHTu+MHUlcXKj4c7K6vz8TnC/03La7EfcZFlnGUzFAubnV7DW0NVutm3bf5H7
asRaGz8fM5f4nEkFvzyIuCo9FgCmtICoIcUqGggZ+slfJMap9gP2vNbn47CWPKRb4fvQU+NFIDaG
7qS2ATZ7h9BepRD9OsAmC7JOxPlvMFZVl4kmTAlVgQHinFJGby6cx50qlWfzZeiEgNDHz1JaWJyi
jOuX+LRjO/FdjpUnnTOhQmDnf3lfHZ40dWgc1fnC4xG+9i1n4+9Axxgs8JrbVRGssHVA1eJQCl21
qx8USmhdsmtdNUL+tQKs+/YSDBxn1rMzN4KTiraW5ZPIc9SIun7Aa+XQGx0Pkgk6RRCPgTJGvZ+d
tfKkTDJwirValli26rMaL5aLXLkgbzcz//FP1mjWE2TW53d0NJMGCKZWw6BdVCYfW3DHOhZjCdh9
hOlLBDvh459MkHMYw8nuAjZpB7re3i73/QXYFA1SoJ2JlhF7oTfv1+XHTt/iziFmjgeq9Mxs7EQZ
j4Ue0oWPXd6cguoTjAdcC2pqWhMVixnOdoz0KTyeaIOeX1LxmjpOhW6bP5DI6VKcTQPZJ11JF4f1
tAGMMrW2zDKI/iqbH5CNeAzS5OGVpLIaJvgtlj0Sty0b9yUGd+Le1taSixxWU4zTLtjbzvSYaY6t
qGGOre1GttadWk3iE4hlzLBw29GJLQZ2ru68Bf4FnT0faAMzmipTKBe1R1SCW/hwmtWMRAG4Dr/f
ScOABTku9VhUC0ij3AIxhz62DjKVrsDXQPI3+7M1hFSPHOfIq9niz8BEgAE7TJE/i033LgDjt+mT
QBkIMtfuEOkTXXDu+77rYakxC1qx/DtsnqKwOHAAcXV5LzWJ19NNVSNT15ovRJcotaXU9Ddaa/Tz
YU7ylF6Q3diAvywrIgon6NMVccz7IOCd26R0AtdczifyiqJwBxG8MS5CrKkkMes7JpWt7UK7oIeC
eLF9rZAQFK8T7Mim+ry7T6EIvWOQaCsICI7UaoPbLOuogzzQMVEztn0duhVRHIcEnWnHe/OWDrFS
5BVfBorWISmTd/6VR2CWAQuGeSMQ7Iav5uwtUwLb4830jtqtenZO2f6HrB9k6IESwo9+6FF3Tqh0
TvbkBa+9JLofHICPJlGywit9cjwlUm0/DDgll71Nfkx+t8lAVAl8F90GIkktQYmBA4CRIZH7XyQT
vQ9p12q4YQj+/2u03X5KsVP1dShJSBbt/OcS306e0uxOvreaieGGjvP8ctc6QDK3Pa22JxHfttQa
r1jroQraOtNENsxDDQZXdIsZYGNiliTEl49lmA5oroNbW3+GA7YPf0WbmKQbg+xWe2D7dO/9d2te
PzUSgDhL71WYh9O1X2Zm3XgpTHQ7sFzHA9jfnCXc1ydd1YKtGFJlal9hbGLZr0yazrf2KDhIqjz0
FaD+6eGMmAlsM3q6636jkS6DqyFEcFXD+f9JyRiThqRnBISRsDC0VMTmVPBEjOkUybPtZGvd2y9G
dIeUg2ovaAcCieFBM42HQgREZxTsIFMhdilNV0vRwMRxYJty3cKuUzcuJTGgIQXnbrFcu4Ny+VYU
JVe8rfpaZL0ILkChA29wZEZkjS94269i9Sh41YG7ZHU+KRbG2FEyEpaa0P3zZx+ZxpHrGSRowH+h
QzQd70B2YqKP3fM7Inroz3aJ4ohrJZWf9Kwi9y6ll1qxpH4KIbi/wbwdVKcz4rTm7+SDzKoCjv9s
glKvC7hTbt9Wl0LG2VYbqV38tanvGSByLxnl24nykTg4VRVemKaXdeUsG5PyK7YR724rbXjZaRgc
3uddMvAFqHddnmUYfbeeACvyAZ4p29sPgStyTMD7MGWe2UTqDBRvnhMsI/tGGMDQxHLx2J6WT/Q4
yfpuSxbrTFF1UgUGGds071GCQXBV5kLrnjM+0prZFCpUJejuH2+Ac5rh1Md9jTr9TSYI33vXn7lC
kcrgIoOX26zo190a+0oaJK0ImO+DcSpmlsn2uqEpUh8xGYWQWVeSP+WGiCPC2ZcxqyMBucZ5kTFm
2h/A4DOz+T3UC++NJQUWUXhlkK+Xc9n55U7eQMr/54bAo92xmMjIlRBxOceC8aDdz1D4YGLwxzuJ
hHtFFI/yY8BwlqhCWIb0An2E51Q9cm1W0JfhlaGnrmIuyoMIK0vjcZG3hWWwOiWGL4jJfetgX+tx
uf4Yup2VH6bkpOuW9jAOebjGn2mm9mDxmMkXinnKkVfNCOlxCMc7xyrJ4a63p90RrdAR+WgHpdvu
jfAe5+elkbTuL7XtJQiJF1JjBlqq3ZKgD6JAY1XS59Pkaumz6RpPl7Rn+ansfz9JCJBE+e4Tfa9v
PIqEnRnYgbwB7MuKqW1rHq6hLk1ebhFXQIYc/dOca11UMtiy7nc0tAwF7DTxVF57ZuqWvBOoSOBl
QxEZhmSdoRyzsdXIle3VblvZYaVRNz1xvMVNhqxIZmMTN0x52Qc1eZVkcMVlyXDXIBwi97vZdnjf
PxZQvt6U5sUGbtquSIbvm6qTtmhNtiVJf785RRQUtrmA0kOz+Sp2/1yksd+SI+ZMgQgTwUtiLf4P
NwZdT6KPBofQoA94WSshgWk/OSJhGXC5v36ZpnTaVJsCndu1u/apLjyJaTRqOyO0PsMFrxt4/hmh
REPz4mB3xZlcwf23enemQzvUYGQYHqp1p1SD9LasBqU6aBoRuei8mAuWpmeY/phNPTg+w+HKnWTf
2YsTpJ2jSBs0Desf04Dv9X5VhjZiqubcRRGHrngEQgk2lJzTY9+9dCv6VrW+MwS5CfSHZ+FxnKsk
4skSVz9uzH8AkgtVZbpYF54St0mM3EnL3m6w6VL0p/V0NWDUgCXc0UB/Q8OvLM1ulsmDFAlaFB5k
bQCpe6fcT8WBXNrXqwb51Nmx4cFiYvw97O10dwMgg/8kGOBcQI6PzJBM77npaOy8fHNppnrnhdRU
RrAm4ywoIOXLwX6rAqELvuq3TmlxdUdUD0FOL/v7/t8ukAETPxPeufpXKG/Xblh8m6GKhPq12Nix
mh19qzJ9CWIkvDDmdeDZpPxiBVJwqVeBRi6fwac7HsBfahtOqeozYNBlbQhVHVNTwC8hZx275/jN
EcelVFZDQ99muBHkPGSLrojq9YuYjqKfSPGJSdvXMeujQfG95OeEnyfTBkfE8+iVRU7MEQv6XBXW
zO6iPxmGPURneoyEd74bOSi4AqDkob8n9MdjJC7qb/qfyw5qT9Bk2h5cYVGHvyfxuFAw9dejYhqa
vTf0Q05b90Od8KC9Vax3F1g8xw2vZIby8MXp6C24agehdSn7poR7ZGmaLGLxbwtxs62XsSAsM1/Q
HaDwNrSYNKkjYnXuif7Npo6swcs8nMFcpKsSvRYksOA65Wqiw/I+cXjPADDXCdHB25vhW1NJuDU/
F422a+5d/6kw+cieHtJzjKlW9HZm34NCEx7KxoOXaGi1hVlMGgwss+o/BQETkc9BJ4XNxaCThbUg
+BdvMh/aaMWF07cBMrHJLEj1nOeI33TjKmmSt0zSvUk7k1u+1zj0OoZNl9vDBK5gukb3P13kDXVQ
DS8dd1VSoZLY8WPIxzTR/TEPoQjTQcmr3K3fg3GEWYNTPjMyv11osqECfNwAqdg+XlMQvjwesdFW
WBwyJFt1c5fWEH4LIWQQKpXdo+ci1x/QsIixFScVICsphhLqmia0mR/zDIv1VtKJNRIBJV+M0vIM
c/VghBZkMwntgGyq3lg9EysaOv2/UYoW77OiznDHNB4iODF0PolRbnDaUdx3i3UP3MAe4Bj/kvxs
d6mbClcidRPcnJbUsPjzP30JqwEmOJVAzTHgo8bHADM2n+ZvV5SYyZvTnkmRrSN7jbY1pf0VEFwf
7/rUb1XC7W/dwZCQifVvVjmgNZX6l5mNHvQZFgSQ5W/mPYQQdcK57TWh+RblrlaW7Vjv9FXty9M6
+tbkT1E6jyyEFY2vra2dLVRkShEq70f14MKsinFCh+HDaL/cz1jWyYidt69ZuUpAjHPgR2V3uOJg
5WaaVqssETdfLok60Fro/KU3FFIaUBGA+BzwU5mjXX/MSkvmNakbzG4u+zpieKI3/aagug8sr+GV
kvBSSmYuH4Gh3PeAo8rZxvABo+JmsjRwWHS1Hr5J+j3fO7UJFLcbWvok0H5gX4aFf+MOJfsrtomE
75V3Pt908j1XkUe5kznFkMHL/fhxKVkJAbDaDOkEpthdoofvUNnmxZO+Tk0v49nfZO5SJRXff2yz
3rEOM9/13GQUC+qjqkkO6RxzMsN5KEv/jaxuyNU3pdKoDxhidWNYRRxRKrsc0/XPyOzbgkUheN6F
YJChK23Cuxbf8TVCX0YAJhcz6Hv9EkzJDh2fAXjZOT+CwCfKn7HtwOKsjCPv+CnP5tjwjmExCM9k
JmG9y7TJL2p7xG+9C0XB6XX9Xhz+JRL2QSlNMc7PmuoXiZFXHbht41uI9024wUkcbwLg9KWWzyZX
9n8z1cU+i6bkd4mEIzPriYJLA0d/hwxFkpZYI05ClbeN5v8GMYhiKwb221mvAkenNgxsvpInzZtl
3FaSTEaiQoJ0YcHxL3cClUm71pE0AKOQQhkWB2glb+8nAfxcb7MYYC4n5tMbviRqjhCXXGLcDGeK
ralBjbLrQNHu/VQYRDISVdwBmVAcCgbZlk1HA1Ljau280IlHs0T51R9Na+lAZt18l3ewhU2lHC2Y
MkVGUkEo82rRD1igb82OiUzFNPEXnFHlLlZRDUfmswmu7ixrSDGu1Zuj9iWTTsTPqK4blQlBo/+s
v+RCc1Fi6cIJKXbZdzPtKpVAYPGm7aJKpaYV7TQ4cKtXAkoonwck0kzfS7i3W53OTBjCrWgdCpSq
jKMW4jDq1gdu7vwACpnSWOHuG0fe1LyyT7V6l/bdg17yWTsNxZ3IOLehuviLvB3DAYUSacoJamaS
LFKlKD7ObNwXIPbLVcWvplpy76dMith/4aO4dokS6/hEjfUjEgHeXLNAgzvhjmIiKn1dC4v3H95W
bWq4on1R+jjRtjaSsC4AiFlaWj9jmfMOlrYFmw71uaqXe18ZS/K1Z9p6VCiA0lyViVp8OxjTqsIq
HsO8vmDxXJ20/ROXgXG3K18gMvbBhooPtnS13ijhKguNKrw8yryuhroyiZVJZIu7CuO7oyO75UmW
DICJin1EZi7wxrZM88+eFyL4wyKi9st2HYJap60WzPM0MvhlaTUT9+6cThLLu1OQgM3TzO7CwXJ2
NzoHYLEdXbB0/oMmArPcOP78QQk1TCafcpUbmzEXcIWM7EoucqfMX8OB9C3piexkI8odlqkXNLPm
r96IXLvc2k0TqE7DGZxMAbtgGYtbHtJsI1wrGn0lFpFe0sqcaCwMV3nfzoTBgQjqlr1apY1X2xFz
Xfyxh/mBdAK68eLFgG5WC+mgUvBo0KlodQT/9wpVsN/MDyDZMHbT9YtpT4i2CgnIqGSVJNH1VKer
c2feMAlV6K6owW04Qoml7XaaywjC9D5fYt6Z1fledV6B036hwLiOyxDqPW8vh4qPtBd3mic9bWlW
7wgrrVTSF2aHtILvojTtcxFIrQdRZQp2seCRWbG2BkrTv3/1bKZYnGQeaPoJ8cwmNqnnaVolla6b
lUsQOEWia9hB2dZeuE8cuwBqhHcgVoVvvr6bYfCUvY8Q3No6t8prA5eH0SBMStRt5cEdzz/pOLdI
5R6hEOMw6JtbUfYBLPyrTmxSPjZTJPWdRQDzvIi3z0+Pyv5oIFxbSjvT9Vgz5+YJuJFTh0rVfg+l
5DDQsr0aEqpBoajvIUfxU734qOF+R2c3uBoWMNtJUdYn57ygEU3MeH/2MTutznAyClgNDWTWjybg
0tTvEeyV2mNZaQC+nGCAcMqPX4fmU9yuasTmHcuo/tLiXZxDE2heILAzPogw2fCaA8Mbcj7q7qQW
Ut8KSZSNTPiLK6lxSnInN/WYWGikumoBf/w1bkSRgmjhvtLYnKwYnuBrtZLbQ3q3gMrK9Om3J3x5
FoORawc0pin4AzVIQQdWn0Wd0E87+lpqBzjh0tBv69gzK+jfpHDlXnlZFqrDh0zfFqm8nojOe9yY
qiscPhyp8ezAlgS8tQFR7pTF/ysS5udL3GVEEWHCfc2ylNpo/vJodv04tWLe0iW7rRCDcbSUbx09
NMukphcqf38Th+uE8TjBENAj+DbwgXf1/M9lp4dh7+BnSB51fsvRIeoXaEtAAOYMaljNjUE+o8Qi
6GZHX8IeT0o30xHl8ST/hJ5c5z9g8Hm5n5GAlhXn7WXyNrtu4qREdeADPOIAQi9/aN5Fiol75Eam
fYc7aVJwu0SeJdWr0bU4xhTmNKbDmakaUP9SIaeR0ehoitOTkizOLpeHdgoRg/64c9SLaQPsCe3I
ajfoHR8NUe6wmEVSHVco2STg4EPYgqlGx8kXUquWilIgKhdY3MUgn7NNPOKR4IpnIVyy1cv61tqj
x4Pp4Bz0SaBcEsOhuPJNJc2cVR2kQoHtrdhZbcEalbzknYH6DE8VOom2xW+2AY5Ub3vyQCbzbvJk
plWdfFaFqQUjcaLHXEulCNE6D2FMhyV/8PmPPuXh7i+vDiDv6pUngNfrWXgP9SkTKhnK4KSyZt+e
EBU1QO+nGhCUJcbzi60wYvswafRk5BTw1k/6fDffzT+o5Dbt2Fm0yxJshVrqMvwBBrebEpWeL3gf
R1BqbOihhyZvklkwzLChYb6yL1CaB+4LAekiJhhZDRLNP6Ek6PZHoNOW0/sjC/A7pPreTPT97yw5
Ut9Y7FWKji3w4nLPRn+Byy+TuVpjwGZ+/PPWouMentg8vOtNtY8FgvaqzBYc6QclXCpzwlNKGnux
V7tMV5qOrk4K2fdXApTFebb1GZhdGUMGwdSGMq9GyMRIvcNgNo8gzV4w91KRInuPS4Mvl+THKVZ3
SSotRtj+iKGjEodWYJlfA8Sxdgggncagc9jP1Kl6Tx03LBPwdOthrhgsv6ufLS2A4VjYzJ/kzJ/H
3Z6f7I54dGK9cziOyjLGya7EJYcOPzBzfQvEoBtRcoOU3gmIX7APf2IUaFWfC7+IPHxkKBDmwnKN
QCt5LTIgj7DYUTg2c4hAh9qTQwh3XhlzYrhTaxY3zmJzJm27YtaTPwTw9ldCjutK5NaICodvM+0w
pbIzS6ZzGkmQHHfq4sejqsx4uOgRfIhq8pnNm+hcGoQIJzQ8HQTnEOwNSF0SrKt9Fm8yDgvm9Qs3
dONOhdkJFKVcRgtKIf88Xc6eqXpRsgKgY3zZytgoiViuD7JK/cRh2wpSWVT76BCLWC2Qcj4XOag3
1Q+unlrh1HKJ6uhSUZrsuV6UO3s9qH2qr2T9fPPkFhsN/ey0ybR0QaOaBR4+7j/2YNM65CCnlo5t
ZTKfkn+plwTZ1Ks8N2AGOQ+fp7aT0pXOaz8CsZycI7/trB8kbDD1adHIxskNDECBRYjJDKVaecD+
lZj4NmnpqTMimMS/ZcNtOsYNcx2nEu+EJDR3vFc3quPtdVzBmckq6yYC0O20ECe3YLGaKhLIXvMC
X8BLzfskMNaJXNrM9FSV472T1deF8YyB57ZHHwDoTqKFzZPoVNluAk+DZtFGb5lpp1j9J3/8F/nt
6tlkF34T8zLeCIzi2aYAo4Gc7/RIPJxo0FWdPDmwiw73YWTbZjQxQaGs+WbgGT7ntAjf6w2at1/0
ZMsaL9gPS4ToF0st7+MnALnohj3drJ5eKw9GYq7RNt/f2ajsEWacBef/ms3UMzU9cQ9LOidiOTqe
gJ6AsKAQLF4rubIuTVfNSepahE80jU2121xtAuw9WTUex+I3gQ1xYDNBNiIlVaFrrRnVO3Ie1viw
SnJsnntvFxr1PqXLeSXLmDnfdpxD2kF4MOLTK7l4HSa0TQaJucPGBY1Yd63Tie7FYOzFIPkRdG1X
O+olnYxE74o8+yRy+1GmmWGO5f54JREM1MuJUzUU4HLN926nSekVE62AbCS1TLu9El65PiPanD2O
p7UDDjnd93dh0Olynh3OWdUP3jfc00NIZK6NQq/gwJCbmhmFSU/H2AEpXjlWBnNhFmS/TEFS7N/g
8A2LzSW9NclZ5UH+3IbjiukUBhdkm1yrVUz6sl6vW2MBs/IKMXLFyWx6ko/oyBipHDHNgqFkw59A
sG5zX0qzzaCmFJssU2WyCdgVhmHo+7lDnNUO4EyuiV5iJL5fjcpRdmuNsYKJ2Zles7wk9CoDsonC
tHcOeHe8JxgoS3H0jVjB5tIkvtv2SuNhNiD+wbdYX75C8iTFqLqZwks0DYp4ZDeQkLiNWy5am7G2
jG4bvtJxFuiq4l0xnugPkEp51PlkIAwKcT3Fb8jOLG3x1N4e8laXimPKGwvAhyH32BGSADBwl4eH
zSuSMkcm0vx8MZxYgx1AAA74iaHcDdh7sqUpy6wbo/zI6+I/0n3a97U0XB8LuPXlbPSZyoPlzCJE
40/rS89rSHtRKIta/QyiIHEE4tqOa1v9sm5Y7CnFEvkOxcYWbstILv9nRjV9zujaMsUBJASlKI8M
bNkSMQwL2MjEOjtr/H3g378+wTkhwCTBsOJFjbLJ+qByEuVhpaNKpSjPpmnH+94xJHFyqPRs1kWs
4MxBKvTv8kQ3Eir82t2r5dyX0zknU6ZL305y0oZ2yVfhK3yN2xsKjPS+itoPgCFNkqkhLbfG4PE3
TC+5unStJdO0/yiL56FcnuerhOTr5zYS6F2hB1SLUNlMQsl1VMR+UlqTXQr02bobT6PlbKtlOMg/
R9DOROOQpkjjkVMPNdUFJU7s5xhoe39uJ+W885D1/6N91sgg9P4NH5UKJb5UKYGNT5ACYJ+WeN4m
hUWxU3c3OCsZp2CqiWrLMKtgPmCEzCHzUHACnEmc/mA17yGzUAtHXS/0lZmc5lonuDuQHTsnZXhm
MD8243MFed664GMIhCQ/clcsBwnaXCapV8IhoKfPNhIorialVLv+boBc5WVcs/WGk1iCajozJORx
7lA+dG4AltS9k2Ge9WD2iGGixCXOPC8VDMSa0o8r0is8qGCKoZtD+Oujp+ZC4XGkS7hhjTqsIlAv
++LH0nWmsMkNSzxzbxMAmNX3B4SfQnlrugHtdb2vj5CLNwhkCqx4mP0HD5Iut4mAKvPRxP8nwOKM
UzLu5MRGpEwZMGFeGrsJrzv8n23Ja+gAuqF9g14BPNxSJKJIsKdwkBJoVAcio/pvYeeVzgV/4kon
10tCymIlvNLfX+LzBaqe4yoINSL7N/mvRUnkPFhvLyEk30BZfNvWyuzF/7dU1RrGXRERMg1m3BDK
23XKt7pL/fyrKY97g2OPmnzVSLtaLomgLHAGKRlp+ZlggW5NniK7DtyZDcHNvZxHeSqlvpo5qgZM
EgcqTZKphDPI5NhtFCqD8GjJKd+WPgkPQJtaHe5HhbgrbH8vEzju4Vbt3fzCv2S9e3eNPHXYaEg4
15LeGAkCtEVosWO/1dozVGOORUc0U1WkMy+B1Vr28ivrprjLJ7dkUmIKH9eVSLHOiyyoE0vvTwM/
D+WHswrw1tMnL5YJ90qsyLzMmpRzc0upQDDgAAV0JIdOiH86ANnxIKvsqJCfY3lL4P/fsaxu5fge
sR5uDYpR3FT+3N+8zv021EdUIsbz3oiHdGE/hTkg72jHqi5xNLVv59IK71a9VDSxqH8NsO699C6R
iPC4aSXayg10r5K627IwAHs0LVglCF1Iw4mH2WqTKlfnnAh2r65AQe5IHOAuLG8mQCDEUbwArEoI
HeeNTtB20aVmsPVdZBPD4uGFj2N2qkchCkcgGeZMPXyaHyrOpkexBeU0OfbQ2Ww5w9cHmkLPw1hl
cJFbh9mk9gClfpZOrD04iXNViVkXzoa+vqAmpTJ4nz0HxdSjW+6px5B3MMUG7hQs7+pIBGyTVofZ
/PVfJuSNdbuZdPZR3IU02eeastc764i+lT482wQ/WADKpjax0F3yn+i7BIYG80p4nvbqEcJ22NHX
tGA4rC/TPv8gWFULr++TGX3eNNjovlGAYD3qtn5SEwKQjfzMAiB6mwHaCO8OG0WwfiZOitP9kBY/
7sS9VKi1oDefj2r4+TZDsrMS8/+R8hKU7L/Bh/ZmtwPik7nPDe5c1pftGVaj/PVY3/vC/uX+QaJf
XRx0R+TQ3zeChjDIm0vwuIy6BUPl08JaOCOSoD0DC3f65KRQgIK21iiSKVqt8ERiPQWL651s48oC
Qxz6RphQFU7aaGLZ54LZxcWpEhCutR5mTpaeN7anbdI0k4URgw0esgrhzfdmxcGNPODKT+/Nq9ux
QHQE0E6+nNoAHi27JUZednXllXRoXRXORFUS9v7BAw0OBP/wgsuwRrdmYAhGYMhx/Wckiudiamae
vADcBib0JxaNUGnxqYIX0cpRTyJxuNoCOEek79VNBttYwxkvBFL1+rD3sMHTWjbcR6zkZfgFiOHj
KoWikxX+99t5mwHZ3NVB592rOgllSdU0NzrgKhpYgvjBmY7wJaKUBATd7qpL2cgrqMwt+cOqetU5
n8/dxiABLZxPxEeZdjinU4cHKBswkkkhpHgslYC7UpGtThyU60rf2mdvx50nWKfL0RO9qoKJeH8L
WhKnhUyZ0H+ywXD64rGDt8yDdFMLzvnax9h/lJd61uQYLMdOCMAvmUY6A2bLChe+DOsnU526VfDj
QXDzsY9HFT4ssiuvVy/9KfOrwqYAFnUOSrQS2xppt6dhsIoVAxjOl4YsjnPaxMVEVyMHZyaG5kPf
TyCWmZAg5dX41gxeQ8T8XJvPVHgGm44Q49+ZAuvS8uFlyFpXNUgKNRRIUyxC5jaM7t6+nz9J3jPW
Ji+CVHc+hMnZHGe0JNIxuHF6RRr07YAJ4gmGrdtKJoRwxWkE4xEnQqotiAwC8+aEFJZHTJk+oWCP
sMohJd3cl93x6hmcjtv2b0wcCyKYYnnE1HjPbP8gXFxPn6zeFL4rpsSAjCdvmPgzBDxFo1pB0HBR
EnHOBQAwXTdhXrRuy/s9xyfAnFTK2oV5330UzqiMYinSRGYs5o+gIk+B8ZASk52Aq2IehCaD/b2e
uKX0/AHiyCwZyYng/b4NIPE62yWcQruNl2oQUKglwveZH3k/tCQZW9ekoXF0sLHPVLsisidkbB6M
pFVmkc/x0RZlwf6enpxuJtVZy6Ud9oji/GkBg1JutRsfFG131cT1L6bk9aaFBihw9RJOoGQcyM4y
CPWSrnbF7zwTEXjoax0fgspMr4JvunDuu+CRm5cU48t1lyLl+v+uEWOU++NdPjxxML6YMriGpefm
NKt01j1ekgJcLxdCtH3Gyc2m5B6Jq9X6Qn9saon8jXEVwQ17425oITHQ3rY/gpUC/MjwetmF090Y
yBdwDuzB/CgZqfgajquEmLrafICyyxv4c2IPht2gzj8jB8k7FGQfKsbROKTZ+AhSVrLvMSZaXjSK
whEkLTIphoUUtho9Sg+XzGe6ZeDe06aRBwTd/gDodntK8O63taufoD71nmZYPIGfmZ4MnAfjVwkP
wvgkAJVyhOHZD+iZpPHHoQXi58viQ8YMrLq9DUVUPpnqGO+eD5iZFIYAuFC3b8IySlD6jlLeTSuX
Un3dObXeIOsNAohnX4SzvTzuID5U2a8U0WQgZsF7I1eQFW8jQ2GHtgdiqeOZvo4KTR6K7/cJq1Sx
aKpdqlAQNWAjzfFy18O2TPL94puULAszOVHU88IBkqN97nk+pdGddgp7aWDomchT3zFxVJWtSoGz
UcOYVEXKluLUek2RH2KS0hFpHxCs0Pypcq2OXus74VEZpE23qNTpfoMfK2yhK+6hluniXgkYfls8
edE4X3lOrnDJf+ewrRMebvLGYcxwSfep8il6NzeO93DHH0Orr0mOwiVLs1ajXZvjmEBlLmIhlrLE
orAYN03QC2nAa5uyXV4In0kTXxrz6y2ymU/okkMMOLLp/p5rXcVPWJaSjMdW3reZujP3/7u7mqZS
iw9jAx6heCFgI50fNKDZT5FA1cb+pWCCRMpuxJ7KL3H3t+33ph+NBiLJMM/xAyF/YJgl90mFHmVS
F2ySS7WKTxwKnCgQsd0BGfIWckd2tSqsIJrvRxY1HB0DtCiImC5I3YYRQoxMMXQFC2sFfIelOY8d
DMM6P7Obs76wTZ3MycG005D1sAo2huDeoHywdIWd8uMek/TPUcCbSw+ZBQhvjhNZC2KWk/U8fREb
fqfh83kBtbKfC7X2+pUmzjU77QjYyM4TXE76I7DIm7qWQ+cUpK9OyyZ77GJbA1a7cQrU/YJBNRMe
aAP9Osgel1k3TJ6tJTzoR9UF2ylMH2NraeBsC2xda0jx1H1erNUGQyp76bnuTMiSfG7RFHs6667C
XNqVyxG4TxlAoihMko0o3R/qpuS6w47gijGN8m4HabHnlwDK6ysSM2fwZmRD5NbpZIy7qsMN2gqE
L6HkdLI+/JpQqLsxumsshhqL5rEaZ9SqI2Pxb9EYYWn/Mvhs/+EvdDL0CEQEsJMcK2NYyaHq3YuK
Vnebrq2SJpSjVhfnsVyc9Izy9kMNKKyoNJNV4sQ7+vRRvcwPN+G17GYhbr/ISeqsvCadbITNDcIv
aDL8vZoDI6woO3bQ4l9bPw76mjLrHJbjBjnX3OL5zCLcVEtFVH1c+MVZnqrVzLMVzG2c6XIIDMJ0
h2uwUOJvyBfVf4+IPsCaBp6zPz8gf7Fdle1/l52Qr56EdPdmEXe3Gg05HMSGSAkpnjjw+Z2+Dent
e5qFVdMdLE8uSRc8JxZqUjbRBXpUxRBbskvIRe661HqqPufk1OZ4kb76pQwYUXJASgsCEe3aOVlm
9N9ICaL5jUOJedzSEoJmGTOcOZBckB+C22jt9W57bLbGO1RffVQJdMbhVgxCBklKmzAZ5Jdw1TbJ
80FxWhk3cPmaeMKxjSbOMH59FTbGgJw3Q4foE//W4LjV4kLmrUj6eQu9dcFde/aBgJFEMuuLvidi
+2sdG6x+NT7rBHggz9Vw5S0xEF8aQL39PoupTaypkCJGkouDxAGnaHgUzohTqa6c5rnM4BwHCZ1O
+75hgxyjOhwK26+D6XJHV5SMGBBkhSFLD02vumnzekjXL+0961TcEQRuUftjbbPwRufzGwfGFINe
aOX2jjqXEep1pENciMWfiwijNn0SOdURwB3w+717xdzm/lI7hvnJfMZW3/U/RKR6mtoXDV+ijoyx
qoH0NPCmhgW/EyWSKmSgvIQXG0sQ5VLypZLrRIBLU4c6aX75H86z64ovVTocoxnxhkw9EZNdkkw0
9RSXKg8KIwwC8HQBo3Jlv83LCxGSsRuw6MmHCTfJSpnTWCLJfRlLCi6GH6lt4/a1/TBfDLlLW7UN
AhVzcMRCalDOScyHF+rQR13wrkJe0bjwGL8NLWx0Yit0ES/sN0fco7YJu6KjHFM0ViKvQUAuGeKx
+EfgTGMkZJnzRV4B0WSDO2lmSfYkdl17EI/OxtXUyTpsu9TBR4XDyoCZJUaleWNaylpoMtIikfyp
VCq+jANnG0Rzec6Mpk8c8Un1lSXBQPwJnZSEGPxnRG0dW/l3z24YxeYUIhzL0MvIVl+KltdQiB9V
kbjZt1xoA7k0jy6GbN4+Izt79u3AcfGhnhJiaaNaiaQC50FkPT3uKDf5iRFZBxKEAWuoEL3Sl6fT
I9yKXyYiD0w/kdZeqT+8Nmtix293rSnprterokk8DvrBzv3hWv89kved68N0iwvGLIp8rUtmCfJm
fdHX4KMiXtHCNfOCTyF01K+JyGN+STeLLgr/AJpj7TociRxSXFqEY4z4Du2agOeT0LUUtuMSwlCg
CimQlk8BCzIB3IRtc+YO6OpfnMNlBX8zGYhDA2qkrp0UsAIMafLWffTrRc1soPX+AJglxrXMjJVd
c4ihyRZmp/aTOV4o0WET0MtXM2jh9f3Kfwsw9jwFtlptX9popMj8YMwOqammy4k78GdzGZFDNiO4
acSIflOA9t3CxLXmoKhHuVZ3c0g7tG9UjtNmB3LtFgfj1GEK9C3FCBCWhIxwsQIsWDgy7wR04qoM
SKb2GYNsMmokkXRQP9+7YZaHp+0XrFlKyfcKJ4q3uW4HV9xL7Abl4glTNKM6csQpLkv03VqFZVQD
QckLCzY31fNh//Vb7KftZPunp+Mpg60LUla+e+LIV/xf+VR0Ff6Dhu7YD/WO541ApBUK1s14XnaH
BCkAKOSyCx6IQFnRzn2FjJEStpvloVpqWWJuGOrelvSsctoh9tWkJq3KQv43Mmv+lz/nQ1dtiFia
Ak4eS/iBeHstcgUJfS9v3fKTl2dkSml6Kx8o2bUhoSFTU7h9r5HUoUIUBURGBJdbe+V/5aHUaaoC
Q5A9sJBcGZu0swsS4zyWFPC6NEEPsAGlEBtIwpgieIslBQ6uU1ywSGB5A8wgrht9vt0zUf9nqwkj
C1eatsez3G3h2tSMfoyj8799E3MjvSAPxsA/hzWtKF3505zN7Fxr1cmDpYgf+pOSSACBrvjFFQkC
KXA8tlKC2Wu0cS7cCNknMUqs45l4Zg35F7nKNPcCchKCLE2kzxvEuU3976wVlTIttPV4+EcRjSil
glcN+yqCeHO1CD4QaDWMAOIbkWretVW2Ul/iq6XDEkSuUuEAIwrYpCkcqURgO/X2nYVwd69tPTsn
yXmkq4aKhhs1PfXw7g/BO0wCCe/uHbt7sLSQuc8/eJ/hhOekQbPB0xofiU24v8QqfbhuqjC3K3F5
hd5/n/ky8zk94NWNDzODnKtSF7Khy/lkLvQFE2tSesou4lTaLxp3PgKpPb7X+INZuI++P4ygNNO1
z43PhcdJJaVFDByXCu6YZXzKPclePEBhP+uP6R+IDO/iB6kY6TAm2BSTAw06xWEtmfhAtUO7G4Au
cJIBPD0AeJ+MzxAup+RxcydOt88nfkBOVARCugQt9dSYKuVIZMCO2RiY0PXv9Fk5HsrCAmY0ZoPb
CjLb1yiprP5+4t7dTgP75rhPPMd0OL+/8XmaJbGWI8p533imkQaRnDlTBI/34Gb4kAeIzsE3MfMX
taPXdyr+oAMBOzCuVE5+UX+PsnjfVuy00Aejr0Jn01Lv0+PfNNltC9itVB+dYVPCFnqLp8xKnugO
JXGMDAkwCAC1MbgaSQ7wvL0/88JXRdgy0+mGS/LbJquaIFIhPqO8/64yFx9NcLwxwnX5vSGGce6I
xRba6k+SwQh0CFWBYx6YuUouPrwSMOAhPzK5P9SB3WM7d4LWPXsV11BMFKTyFIiBPJKWB7HaMqh5
EKaR/TNsz3AMGLX0t3ipCt2txRxWnGGlaMKwIWWk5hunJnxNpjBCCrkCwnKzuGy4BcfewKTbvCOS
eOe6Jvw43Ds+2haAGePMinAt3X2rWFkDYI6WOQ43ntRfIbSeMXXWVVX/cXXW/TQOV2IWHOMexZgN
Oy9jf6Xus8JF+bOOgD1qnPhD1YOp0rdMtnpY7rvP47uBkLzYSUiXb9KYlvm9jEZHOUgMsLsyrDn/
pZXehSAWGPewAhqxQ8Sd9cEhfZCmvylLc4crbDQXa2P9FclcCsvpEjaAcCoh8Rh0HhHUBKKLaDhL
WHFGFVvbxBCq2sUjJYOX7S6OG7OkmsUPt8fzfNFS7DEzhMkTTklW4RnR5EccFakKdgp4C1+UPtkp
rysaIcOVaNg33rxfysNHC+OByJCdfDmCzoPMmRuoh/wvHU1MJJJ7/1bSK7z41cfbG7HcClas/pEF
KRlU9aCyt5JkcYU6sor5Vu6I3d6zRQE3dmQHnuiSys5ysbnQomnrekdvpMgQZU0lc0dVtqRfdu3P
zE1VCpLmhYyatdz0h0UxCHjF6FjZYbTNCRWtIM/o4wMreU46OaD6HjizI7YYYzasx9w8zctdR8Ee
2pvYozDzwRKpfONtKbYpPp3MJji8rIR3cRDcSsMLpsPTKvlQTi9Kw7dwMFT6ScC4QblbFMr/XIp9
tCmN/7HJhjg5nRdX0evXISxfb3UezgVB7UCtd10X4USmwDZyej2Zwu/XQNV3KvbobeV6f7dk12p4
bmcJQQPi6NxaCJo7vFsTZ1omM2Y/T842JIh+Maw7H3v8vg8fYV/LJUwPvIMtwD7Mo6eKC05qVE/J
8NGesoyF7kc+0QdTrGJNzpa3rrTEWQu0xcbb6gwzclUqtNFmtA1vPsOWGohjwARJg42TMPX0OLFN
PlIqKxmLI7WBDXSiifQac2utwZKa89s3TU6ALf04o+5VBHwwhL4ibqvF/3SGBV+j2ZDcaVNt8n5e
UMX4FedHfh2LmFw5ro3avGU9jRGKOaimppMx5CNbIPdqd80lEcJvdFBRDvBi62TYcNehziSKP4uF
swrBa8flp3cKDzFu9Kv7EyToPPv+YCfSM4U780S697VQ4FTx5jLHGsxCKn6scZ73gNwqxGgEN78U
26KVbGT4h427lnLUXN1XGu7rl9EdvoKF6Rb1a81CLeTpjfGEzlTLmBLumWx/8jPeR890EcfyCrBN
UXIsJEdw9+Rh47hGzGTWQF8UEVIS7BQ2TQzCPMIfgC58BQ7V/u4Fv6yGA7bX3Z90nS2wKYwEjdrY
0ValpsKC/9BihAEcvDw3kNzVo74O9cXrWdNucexO0BYCblOINhMQqfHCa6nWZcMxuWO0R0VVkGEp
VCEWLhWYJwKp2A6V4D7qM9rsswC9bkx8koGNr80vSMElxyyWFCjjBK6y70Nkb3PuCbhJwfVCLYK/
Li6gcMLYTf6y0PfIdJL05XHEAdNOplD7FaAv9GoT3HazeFdpBMCeJx1OQoJOSJbKttbsv/CkKPop
UlpAyqEFrAoUTff8Pt2mx3JWRcajh/yUiPz0KenDn6ZeZs4xMSJugeac43qX/m6u9RZ6w6oeBLwr
oXc1iClGd+3P1WVUPmkr4mmEodJtayc852BXGI0R9tcIEeb0q6jsGsn5y2g86GqTC5p4dvvbnhOa
WvyMaq7Mo/0Z0oOcNsJt6A5owhYnAFoKWGQH5utsS64RebYDJnPdRBjQl34NcpSJC3YTcIP0IBlh
cSHnTTUjiUmpk1Kb1AyPV6gsh62es7NwJxW2xedLuvfs5BGVqrpvhwQ/3qYv29D9zvMbEQRPk75x
f5RNaQoGGAEY3GVCWwORWKozb18x5IyI5kWTQZp35JAIHGWMkUSnUUNAsB/UtRsWfy6/kSA5VoW9
bz4SE9ysxi+jc86lz84yU+Gt0uL0FSLVV4BaOGOyS1vLIlImtJHFXnaIAkre312kYki2awYZNCMa
O7jsrp5eKNdRwlhuvGzrmn8o0ibppRXqXyJ9wpxAarKhWx4CbJrAAde14xvvlk5S1lI403K+glhx
5gyeNTuE/zedaOekbClJmuCb1BbkuDMHSFrDj8/6kaM67Zxnld8NS+RDdBvrhxqD8MFBizampZe6
86rNvhmHlPUMNbq0E4Hqr/3TQNjjY7+dRsrtTwzDjaHvjHPZyo53tVxnUqtAL4XuCZ5zN0aG4mQH
9brsEwDMUCBlOSTt5NGowseB93gC063tvKJm6f+dZyZ8KdbeczrWhQOKd0qeaKzcXJFE6Pio7Gao
QMVJ5PYYXKCxSzELSV6Yfw1D64nr8MlqoaySLfXqB4pbeqk/jPE+bLPCsTGvcE/UA5RsZ1X2+SNa
M6ba2xkt7MnGdn1c1J35nF3DUSp7g8QOjXGnZS5FqnX178tocs98lGJVJlN9ZUVYqylqm06dkgCA
OghuC5vaTeWc9mKKQ3KY4U0bNEUAOD4RO4qOOEmnAbtCNjnjNux3khpS9OlQPQZPIGkY0s1Obd0n
x0x5ymF3NJZOhutxiznyjYB+DwaQb7sExQUeamra/eXLjo9id2DkWc/x/YAqAlOxzCOdQ3hz4GNd
6P0b4ytPfXHpNvOhTAthKdi6f2QAm1q5I3Vj5fdSEGgsv5/RTiD/8xnxR+veX+IX1WDwBhKcVzpE
YKPAaOvfhDul7t6pw81rCE8W59Pv3zVSXkVZnNYfOXROUBmmqpVb3WS1jxgnJSjxZkzlbDIxkG3B
HrmQAFsGRIaaCyFNLAj/Tyoxix33eNk993inYagKzMnvbCKQRcCnjC+BmP8SnRbjyaygBV1anLW7
+zh3SHPmTvft1u8RTB17z+mCsIN+r7ZihT3wlEO/MoDfS/MqAeAk2qCsnOZ6HyUxz34W20uDRbGM
mDRTuPqdDBEfXzcJAhFujZXtKdcV04kQga/sSqjqewsiAS+vckqjHqUOF/MgmuG96tT3OxLNXLV7
LhUS4+NZWsKbBiMdWc8OmiToPgMKlbY3bjUawARXMI0l2mAcAiorIvh69SBeN+ryOMq/N2cs7t+h
CQsspEJ3Jv72/FY9mNinj6R/ormTmIvY1fpHFrYsWQO6Wxh6kEMNgE5Z2PgEAM9N5vxCEjgWRYrm
NRnxZNKg1x7LB4clETjoMn4l7FeIQ9gcuUzh7F+pa+4Uw/e0zxuiw5H4hlOGnGm9MTCuaJOHh+PV
IDObKFFWBe3JBd7WULEmLfHhhOgp4bPbkLmIZkNTfPUyB/StgutCotRT8mnNN45dKpZM24VvL3Gg
nqyh+/yXOh+NMnw0TeqwLbmawaVjHU15rbJwAcLjBLA0yMvdcYlEIpsbqXwM4Uw1v8zKTaG/oyMM
RYnC+hUxY29/TzY9HFJKY1PKB7F9A3pVRjIBba4d8Ca2KsbnKVZqy/HMYbqFtVws1uRVfB+6Mwi2
y84UZRltgaHIXU17dA+gaW18KBVHgx3k4LsLQu9nFz11Ak5dkdaEbWYZ8XqhjbHQIpWtLmp29yAd
+g5Ez2oq4PUoy4M+9SHgAWYFu1HeZoj+3Or3FlNUFC63+FtTppcW2TL64uyNYehfBOTA6EMfWtjo
o7CsBOv1kZguCm0UcvHs7eMtDb7ppyrYU2osSxE5+Yf8NArPBuhGk6nRD9lrcuwHCpOGl+1E+d87
XkForkIqDT1MphRc/FP1yLO+uDLpZRsVNvKNYJrnVmzO7FjVcNwxYOPUXt3DrWt0yslLoXUwjqH7
j+0o338J5SShaRn0MhWoj3kXwNTe2Ml7TTDbhKRyUomck+LX/0psqYhK1CAdPx79QNZxu9o8lhWj
wL2xTNUjkj15pPgdpo5L0aibL7ne7D4RsoZfQXnqud7d/fh+ipncWKl7CuzSjOzt3FzcH8XZ7+ek
kc4HCeZt7/h2RDSaYrqFCDNs/DiSS5LWmLbIZGvE33C4nE3DMFpksbp3ta6TTH2qmPoeMPu8SxDi
PVG9bYEe1u3aBV4wzAvH7y5MjFpjIRfRRJVaTqWnK+jmEUVoZQWSMRXSvLHiAmaDAO1j4MQ02TLu
Y2YbHyvzijizKVQLzRDXN3MNLGBH50+GyJyU+btH93OMRMeFLv0JPQ/kDVaeU/+kD1IolPJQFy+X
AjOrge+nvVJvvWqMIOb8wT/el+6QQ7ERzpswB5dOctESdEERFTwl/DtJ0Lh+S1WGZY2roJ2f9bcF
9qUS19GMxNu6PmlKHpLKeu8dWJNxYTx8i5/9JNH/YeF8fbSjg+iPts5bCs7ZAYGtSX7lBxc0yTZY
X5I5D2JO2AHErrUO30RJ7e32B9UKm01t4RBvRkMYJQkVLGjoozSoKtnACC1D27KxgoOnyGo15Amj
uHBKyRnGb6ZAKZLZmnNv80yR/binSsc5+O8MUWL2MXmk2MnOBLFcLhcT5hq20WSZIDr/0arKHp+9
5zYIGCYZpQHwbaqbaQ/qg4CsgH5gH7+Y0ziEOfQ+8YTkFCWdYrtJsi5cP5010B1/0RZb3JPVC1rJ
NaytL+Nx5wE6HuszU9OhS4lMQAO2P8McIpdsXWMQT9qEbcao4rgJAEUb79ZN/o0nuIasD0uQoXqm
Jhsol7fxQUugHs3VOzhLmnIYdGljs6wwbCw1AiQtUAjZa8NGOp+IiCHaD9VbfSPl9xDkYx4vdJf8
oIhkd2/2WjEVRWU1qsVdtEpwa+zp+D8NaXiB5iJhAgvXEfdemv1d/igigKgyphGZcMlsyOgDrqIU
wcJ9uFNtooYjDaMljuGuQCuLpGjb2ightuk+Qv8QV6ufs1SDJR2UNRdzqDyjGwL62FpK9fCNi/bA
vw3JXQMMbg7EIv2MGBhyqlW8EBDUEYkG6p1JB9+ZjaemjSVID0IyJ26vkdSjffEUFkn3qWcemTfh
cgHk6DUFQmiFkomG4ozWIqxK1GZIss/F7UQaYuJGXlNpNrCbJdPmHy2VisZsnIGDWwn9go9xkl+o
AeJqPWFvbBBKcjTW5ZZfiVSJkzBZIc4GrCOJ+KdjP+0FneQop1Z/NJRpZw0SoMLEd92Ss9hhs/bs
IYx/iVqaWEsLtcBnYlqBTHu0p22cPp6DcNL8zqmFNegXoh5zhVXVkr5atnKABU+IMriXCP6l4qfO
xINykOD/H6oT1e8MEV5dzSn/iN/Ux05xX0DI4eNBpiqIyFFDJLWyGy1HdFzrSxmZiZIRxy7Ry21A
RUD+YmXyZPOqfy6e2e2BqBve28frMLaNDeEw3VHDhMsl0au5qdR2mVk38Tj6aNil1Izlbd0HPVw+
UksrwLgNBOc5L+bzl/M9HwLOLBIPIDvGdRBTJFS69XioAFRelfKb1GXSa3o6aZ0hejfigUJ1+Ggd
WFGsz1Gq0qrY/Mv7w8+/JbwLRVudGRSYkt592wm2qq5zDFFRhXZczrcqYpsnkuIvHEWU4Wjjopwo
0o/jxo9oyM0kipaIgdsCqLI17T8JlAfJK3C67vBLw0Cka1lIon2ndlsLTvhvuUwkRfo0iLPiC1ao
RL+sieu2+DEgdlkwdW1Z0lKbBGg0K5QKy7np9l5s3VmlexU5ZDj/Y2O/A7HfqP4Cp3WkokOjSTsn
ozRhdOdqIHW3xA6MQqGyBAeqsPEjyu4H1pLwNLVucAGUexbTc/Z+wnrkTMDL5b+QqgQhjj/CrW0e
azUd+gtbrFH1q6h6MzKxSU0ynaPJfWLNGShz/h1zu+GRtj2Ty1OPeyY2mea1Xj9i5opy/9Kk/RYd
/AgH7yH+cyNJOJvGBnsQ2+64K8z3q9JoW3CxZhRFUBxMVsd8jVnhPap3ZLL9weu03E6YryX9vrlB
p7nIetGXoQOxBEr/nn33WRc9jQ/jnKMsK1wPnXrXXFk3dUTiiPdIFFt9LPO4s/w7LWpwzxubNWYX
TRYcAZHLK8C1Ho8BMFUdPHXOXoKtmY/nnPKt8pHJcHO7WBb4MIPL6j6CZFuSiieOuK/9ZYZ54Pec
xMmRWJNCsLICImadEOpU8X60EqqTeoQSE9Y6JcgdLl5c9FaAAoDyz9S+atK5lxeNbVZU2qMl+7sj
XklnA2vYZKyYfdI7vWGoDzY5stVOxOPMaKJUTEa9qsJqPUJjr31GfuodK6Nsy9Oazfy2WwVqgib3
QOzy+dmoRt6/wu+i9X4ZArccPkUJkaEYBxHH5dduEd0tD/mjMU+Nhq7V5WcY2j0Y0Mz6simPqCQ1
uXLCXnI0s7UCUUymWvIQPSOtR8CRi2UQ8EHU8UXBA82RnY+NFqWutEXBZThBnvEbKPKNya/quAzN
2VYe4ekHWXqen72M4eY4Nzn3uzK3EYk9jJO036J3GHMHEPjy/424D0npyy7xHunNXFFJ+x0UmBSP
QKR1k29YQI9i3YVDHSyDHZBFdjWIQK/unsjVF31gAkNW77hSJ2kVm/ownxZjv9Cz28WzN1SRJlVj
qLT12PFsyR3ZGbF/OC8egx+jxI1rYYkNRwWFkgBv6bLobftwmNolXHSrM/K0gkOqmcaqhY2NuDDu
KXZNue2oc4b77NeAC19M9L4kYPX1P1fOOCBiyJvgoN+BweWdcOpVixANYrEBE/coO75cZQ1X6lnv
eE5GHgxE2rlxiThkDOZx0fMXWNM4xecuhuQ/pFRHH9MojD3NKZBD/4evxbA7yjSvxDEHOhtUMQ9A
mAxkKyj3DH0oqmAm1FGDki9lHJsxnoN0suib0idfXZ2zf0d0FM9r21yJEM37NpkjaGIQoi7+WVW1
80Ovkt7q3RWhLa8DC3SPHVb2q2uaqSNauUkt9dttdzDH9XnsI2mnzkkkWO/+acCxg9BgWp/nO74R
yKyE9sZJX4Ey48UkiWMD6EaDGKOpt/NXIANq7kMSqxOr3V+gjyd4kVEcsg3D78wD0fHffzQnCE0r
3pbUEFfj+DCgD4PX+Na2e1rIcP8F/nuAZeTWqyF2Ik86TvV+KUok2LdSANeoX8HFFB1TStzpsb7L
Gutjiw+y6Gtk98dsDRPhsWOqftMoKXcGmX2W6S/edkQCWSfQ3i3MvwrJo1tbjOPETjP2i8QEzFBU
ixnyJ4eScq7ahaki8URwaBjMMMZNUipzyD5+Bh538ljk2JoYH86RB/zWomKscLutZkaakfA9TnOU
I8/lQ/F46PNpnW2oXIUt7HmlGM6DA8rDDqaHwFV3C2euLQAmU2ow1MfhwcqH9dMnWeuNURtetYHo
A7GHaWJ80484zftZPtPkWW/f7TYl2H3BtPy1FV0z1NJjR8hw3hHb2/u3DzaAwSus83iv/RTfdY/u
8JdlPbGNfQ7NIOwooX4CmnydI5L2EfrSqRtOP9Xoh6wtyFIs7DwjMAk/5uStGQgQoJ58gpmxCBcd
7DQ2ifNTFEzuCiDXCmEF6u1AVPHDKBqhTDB3qKaNv+iXsrOZl/LPCZQlvPy61k8ZqBtTuxuHU6EU
l/TzDz5v1OlIZtDHDuaybSffLfcx0XSlxE1DMaNy7epTRh8Qk3r7wQE7WAGLoIA0Ylkdso0rpMId
7OEY7axt36ImGEozcYuLaImlQfCtLT38/95F7BEzWcdabPue9qWBnFtsdAG+m/F/LMsK4PWszb/g
wxsMODIxbxFySQA4nCxT3kwA5yAVRV+sbXNvX58qmORfGxl3P0WTGtuCcW3Itbo5rv8aHA5WoTwQ
6lgqaEPKH6KY0GiTw4UB/8ccpbRfgYyGUUYnGkRKWUG9iSmMZhgwf/wGl8x/dIMi5vpsyw2JwZux
KIvO1yaR2v8kXHa/AMoJ/naKGBwXh1kwO8pUqPegP82Li8MlJ16T4o1WjuZnNVdveHE8Yv7NvkpC
1alYHfdsdQUsSbYhY8fApGNfvpg7xHWVw/8AxnORDD57BMepPd6nElIeGTa0WljH2scKgkcIDGHl
23ALnlKw5TdBfHplQuJOch5DkZcRQFOgx2K+rTVUbKh5CNi9CPgep09digSBB50bfyaFmQmGzLG8
XirbWarxPOz85fLxrwhwgQqzg0m6Br72I9Gf2ST+7qeprCheeSAjGuhGWIWDqwyVZafTlXN57RYr
jc7V6jzI8/8y5wqO99depsyzcVK8t9zWZAeHsF7ZoihaWw5/WIyJ/UYfHgZYZ8HrGyuqRkC7U1Zb
2GDfzVjc9iEkPFHn2DPe+F0vZ9Tr/AqxBUJMmZFNtZ1zXllHZWvzxYnEfYWackE5CjwxCdzG9lFK
bAOg98strHi9yroo43Nb05e9X8FYfQmn9wFx+/Gn6w/Coa6h4b4i2cGtSbeHL76kZPSpwDduF3gl
UsQkixW5ttkebGvXNcTmxnHbMQHtqqMGi3tGEv1bvHKBbWVWs90WHeLpaCQy/eMqL8Bv8ABs19oj
wSMoXXvx8khQ2/jhXUhf3JgsVWUbFYA1mMY9c2UDUB2//tKn7KssoI+5OHBN43r7O7j0Z16bNE5o
jCrfoOjl7ud/2JcM+p7PNHyNGy9k8ZlyE31vHaRAaQHvVqvd6R01FhHBZet8ATaVPnVgSnyRaA1l
2jGgmxR42fXWuqAz2n8I1/+kIFQR0u4cuEHx1/+K0YhXgnh/ha8eEU3rpYGIo/HvV4otOZ2Le6Yl
H2LAf0F56gel56jIYSHysr8vPK4/CoX8bR9+HfTDN24sWRbcU6aq3IoPh4BOEErwqb19dW2DLw5F
M0VICtW+o7lZG2dknJCjWSXZzuNZWsHl2fefnUeVB7MXV9qxlglCEeig5cPunkVU39hme3N94HXK
CEftN8sr+SS6gHZM61WQhU/wniPWZykSjBfG8oLS7+bzGcjx3aICJwIUWHYxddVRu15V8Lco8NhF
C7iOM3fCQ94pHHI3nGEnt5uEVxSOmC888yNialsglB5covJ6cyRQxsDCsrwSqBd+2JIoGYSxeEzK
LhrqBvlYmo/Q5xRPaSlx8XA2s+eUNagPmou0Q2h2cj4okfGBua0gbTAV/IuQZaIqtRa/xQeUoVRm
XLUzMEX9En+Lv4PMjUPz18ypVbRrkqmxKwWotKSnL08aJxYjPvl6uos29VWnFBgHnApK3QgiB0Y3
ayCLNR+hO9Piq3IRHeK3AL+7Rz3lVWcmTWq5o1DXaeIRd7vqjcMjHaxvC9LxKspXGDrBxO/o1xMk
WDbNSGx7zhNKrL0QZ/HNMMXOIQMYChLeXQXCRVjFp+6mR/Aq9Hx6KgVrAwF3c9tHupdc7SUeF37v
X1hKkNKfcWDDxjI4cpnZgk8CJGE9vty2UmETgzeZ5jKjOj7J+b55+WxNSydFMBMlALsJV4XDq6Cj
qZLaoE7ueykZZ+yO5Q2B3FhakL3aMlELbhluO5RZGJtSj0/BdfCXO2oAeYw3oS8xI854b98nOVOw
5dDMbs1ztejqClMrAtbou+AhUdCvcipiRMbB0FEIslHDXcJmJcsF4RuQuONpTn6lsN0uuLaijJe8
tou1iIfXdy5irD9nI4syBoNiYb++GTRsmMH3TnEr0dQlvfV2FvUOvbDpgAZPTvgP9qiiQBV2P3E3
6xcAViIK8bqVoCfMaD04QFn2w+zCHd3WE2LD7dgGyDNys/SuSw5+2mOiCw9UPJWeY/OtKBMItorW
tLt8wUZe/hxTVimDedE9cRSq5IPgdZdLkWfhHqUrXzmGuR7vUMOJyzVXe43l4mvPztRfI2NvUSwm
BEszSzt3sJ802rJLTvJd/fpyDg4DinD9sh/pv43hZYE5ZJn/B+a5IdV42ZLocdAFdB0LNDWQ10K6
rDQ4nBVbqL7a7kzuYhFxvZ5ORn6WGS7SWPFXRPTSjG0OtjapwJSjSHX+ASuiYrR4m6xgHWKyegmR
FgD7tPpnH2JKrEGBEzWefAtae/E6x5GFb4Zpa/WBVvZzJpxy84M6/h0FTMWyHZYEvckOCvQtFr8g
wKhE4JCdXKYZVkIpEQYCssqnIT4YI8zjl7VeJpDxbrYtMWo1xU0sXbGxUrIpzRUsAP9f8DvkAqmv
0ORwlnALsfqG6TRL5PY9ZC5d7LOTIUnRMxZipcZoGCbcHwCeJehBIHUiXH0X9Dv7AE19Z7B+plF4
OGUYm07gQQSK4eutQAa+qXf4yJIvSbQ1h0unoq9e7ILmx1DnJXf4miDyVrUBea3Puya3mLjKuCJJ
Zh+xuod00/5opLHI5xq15wxQ99jG9tYxamEViRuPYZSeR5tAj+UsLpmzyy49IFxaHVSEJ+drClL+
DqooVhHBvhDUrbESJBA3Cz/fWFMoOG6s5MTs8HdTFqmSVd73U7DUY7kcpOY9QYtokvHSojwXhAO2
+XsZ2ZnOeLComdfDuSftP+35Y6gSSwxxk8e1xTfMUxMZbGHrCY6vEYkA3tOA0nwilriOWbd7kova
rGSwOgwWmqi9Q8VkYgCJHhqz18neQsCtQt5N4z8Saeywcut5/rwIdckh3Bl9R2dy4Qx3/x/uATCx
OCMVlYkhxF6j+hF6weAMBsvOErGUXnVmYwF5Mlyrwv9ZoLIabEkwPy+dKNfbMwKNtf6D+You4NQa
8W+Egcv4x4/eEqA/YOO13hQHKy8Ta+qEdT8tWc+TGK8GCgLah184lfiETn7LcK4QK6nHTXeVkDOj
1Mz6kvPVW+xf2b42VCQ1F+UougWt/6fzZf69bvgL6/OFQcAIZSFrcBIjiHRt+eBJ7OUS7y8FrWIY
OZ8gKP4u2wm7WrD05mDxY9zZQUpVb5jJcTGELLLNF5aLwmeuzlKmg7VAwlb8r8me+Bj+F4O1Rwqy
MNphW+ruqqP45r67R/Gq+r/WSl1G20kNyamdPfBCmIoWQ9NLdudro4dSdxR1lgillOeqocenye47
3nZyUAC1FXOVzFa/rzrE9Ja6Z6UMiL8HS0uSGqYJ8EbA4vJAaKpxjpJB24V1bB3J7opSdc55u5pq
ueRIbvHHTYKgDlmHKla0pktyXTmWGQmo8ljcZjQcSESXZu8FkSL/HaYWVve13dOxTa0mTppXwkCE
E0cTEhxaIR4EIeejr80/nLtNCIzdzs8cbW8L+p28Q6KRm+dh8SpRzR27QZqgHSRJm1kPUD+WBsav
ONBBA6dQzg5qSqoYP7rR61rJltAHX8xbFUX/fVAHj0wS64gOmS8C89PFTEWpkfkXVu1/0NUhxz76
BgWlvDQ+9d/vyCnBkJC24ZS8vDZJtDi8NcXj4by7+iOET7GvaFAuirRVy9pdNaFt1DiGcKAAADGi
vzGM2F9bjcGcXkeffREsAkVvq/gNO7ShdY80E0TeehOjpvjQOgc8WjHk7grbbBCqkcid4gSHWKBG
MFpdBhStLECAqbqN61yvFfKfUjM7JqvQeEC2ql7h885ERvmhyS8V/2+baFv5o19HEHFngZBYlkD1
YxVOKjWTUo8dryl+08nSHS5EsosSAcmSeG1ufEVpwG3igz/PXCbR08FlslgJPAV1vz9TQIRqnGgv
S4QtAVE9NKTHOuFGeQTHwR5txOTgEbnmPSJt884wlSL9+Y1KcPWlr5TOBO3K/61gD5CnpyLzOMD/
J1sw/uC+ZxeJhIu/LQZlSMPIOmM3w0pNYZFN4eG03UlLEzgBhYBLsTWYsSAGomIYQLNtL7p0YNTd
AqfuwT1HML63UJzBhwCazcHLbW+I7DJs1Oo1ZlXxgrjIFAy2+Yw4/8d91pqzwbfhQiuiCTbv0rjE
18TYisfxAeLmdF9NGdm2cAMapCy6iGnJfaTM0fEAs8+3ZdVMk98jdONR44kCAChvY5fiPIt/RfIg
YD+ILn+JFBKAsM1s0UehGoOKFx4R+gfEPSUByF4t23mA5B9IZbi3x8595JcURtGlS0sfdO8Yxibj
jQYjgNX2KX3B5D35JmMVxpfXrzjo1AMo77FRRslmAu+Wa7Ylyi/6HppTyrZ4wwRKRISdY4ZT4y3p
nVZAXjdciDM+3xjFkbQFOIA/koHHzWlkz3jiSsA9WH4U4nSipeNSiu49VXn4yz32ZcphWP6n9s5h
BcD24LTD2wRRwZt6e9i7QWgppkc+hjZWDQZQVsKeXupucen+UBB+kanGUUEnj1JCgNSN1Wv4mTLB
a1r8jziD2nNKAkDC/KqkqkOJGqgkz1JU76wWc7jvc0Hj6pBl468cj5Ang9TKh5/eZ4wGMnHJpnpK
Zk0tIteA1Tgyz+vhzoZgUMWHL/32tm7jSwETiPDg9hG0tPTahzS75wMw4Y+hWOApAarQ5FiTcosi
VNEyvjpK9VdzNbrYWcHpIb0+UG4ue9MxF87Lkjgx0Cjg0SoDcghY5CvXBll659q56lTbRurlcITn
FYT9kPm9rfHjW8dlyiZmchnPt7ygnXqwcHEGzdZTGwJuw1UliAyxtZVFQAdoqz3s7AGgkg6G1uHO
nPl52YAyE8ggX3LndvQnHVB4RUowiQIPwcoNgt9r5nJcCRcgoICV0tts8AJaJmLj42LAxs8puHSy
rzFeItRbmxcj3Klq0iC9WJuYluBxV7//ubdisOI7hlrHU0gEZB9V2DaYRrb2KpcK26YdMPuRqveQ
6nmOaeLqC6CdZ7EzVnc7Ba0at0/kcD9D169Fkp9sDJ3ICpUAkeQKKYHbhpPGIwoDljNdLxjKWQa9
7g174s7SEpgcE6pKs5VE1gGqS8ftrlaU1TWOW78TZSr2tclzPW9cecWcq0dzs09z+/Gh3MXnL9eG
LwbeM9RHZHGop3Ps3BAwVxwC30us+7zLivjxODTvKsr3un9q7OAqYLfbVMKnig1dauIFz7+SphTu
dwXy4XBpzJwuwFbPXwCaJ+9Jttlm6nHNruHP0QMqr2NK0SPZ4BLfHlyHIkVTs/isyFpbUe437y9M
EMdoP+HCyqi6RXdRylj1cyrUPLRYtr8FyxSyOkt2YfvZc0cwsdhO5CO+nDbKLJUIuuRoAm+xRdVX
hXjNeIdCH5ULIXxoPMZi2eK+aaqn121NFXtur2XAfcRPOZfDmihSZk3vFanfBo4TbAJ5BNes8UIf
6VoapfUi3DG0lkNRX2GUXgHs7vLAWxhTx3b5xBXr9I8f9rhnrfEHWwhhhfCEr3D3gWftdQTdYMFj
WjbEEo0hLQ3XQtcDwpJpGyg9I14rcLJqJ6vnnUz5Mr0QTfX0QCXNSNRmzQsAOP8liX8C8/8TMPaU
evVnu/quhjCUSM6Acwe3r/sW28PVCTXZSdzeBWnBs3/CDnJH+xCRbU52a2W9ckKQnmblXr0/AdQi
O0cEnSwJitssuzLa8m0tNC7T5K6WJ8HwJuMhJlS+uHgtWDQvG7NazeIC8MbZbaca3iDdnlyqppPD
UHuhevws/U145fP9/i5sxXhTZ3SmwQWeiHtQT8jy4SxpOeZR3Oea/0yRstY3hG9gDs09UjxdOty9
tWHjKSmp9aX7dGTygQrw5IEGKYtHUQtYFuYFyhzmrcwOygK5bOyDBGr1j1R3Clkd9hkIRoEf2xyQ
EQKS4qE99m2N11eGYyxtGUi3znW/3tgyDJPUj4YuMDBFQdCL05qG//c++1Przm9xV1nGw2YvTnI8
/GM5S+39mFJKMxaVZrcRxC3b5j93nXerGKgKZHLBopGi/bgbySKo4tODFXE03T8u4jpr4STiJPRt
WN8q8zmUYJVU8OgckNVkCg/IyaWm+ghIm0BZPycbtatjy76nVTOOON/YcbtJ6y1TvS+5ESkYRys4
K6wOn0PpZLIUL0ASjcz/CEqwD5YeDbjBWUbXc/d0R+AJ1gJvcIXD0zcpaqn2qXwP9bF2gha9oDYY
GIBg/geKmvp0TMcVD5TPLcn4oKW6fpZb1/m93NQ2XYC7EIX16f+Qk/vK1rcWCbc8IkmYCHTQsvbF
AuvO7QNEOwEUUaX4KeIJo4FiKjrsqjm7L3i/LY0qieiQwR48HY+CZwv5WptZHRvoIxrT5fdoKqBW
qVJz7s8sfV02XnlLFY0q0LXQKIXggR5yS1NzMqgzen2jSCBIz2dKSSYegYCxayAxS82WX2vMMWDU
8FCBJ+MY0Ey7qDB/riIuf2pQxLbIqOp7kwGitAjAjdE4+dS2hyc+Jco8hcA/AtGRW1UCPr7GEp4A
iXU2xe+DITh6nthXbbfI8HDA6khXGQAIyHNrVyOAj9My5ZNRC5PACjwWOWLrjtgleTWIZ1+bo3p8
ZRnLWN8JbJWWI8cbMPftNmWTlgawWmRQrbCS33HJ1kz1lulcbCymETkuQHyhOG+fnJbiO6ECrTZN
UEWcFO+OfpHvs+5CCU9rAfK2fJYKcOvd/olE3IBVz16N1UuFr0b4YmILFwe0aTu7I/mtYKB3wKfC
ZgLiYT3Hy+dC3TNR2bqur7WBqZdQta5mhF/+1dlUofwU+zVbxArhCImQgLijPkRQ63/EOAZ1NE0F
lE08VgGPgSPOE1YZRwhdR/+uI0HpliffDnwtqjc/L4+3ckwi1EEscIcVjxcDFBki9oItaUNQJ0iQ
ty+KxIb0Bf1nszHNG++vQ+E84kb0WrHVpU96iUpglpx9j7m6t+ai5CZWeWI0GnSa7Q2/1p/z+Ck8
8pHGA9zL2qPmMpopYGFr8BfkIhea61X/skGR3EGTU0+r0as853nUxw2dCmS6ZDa2gP6yEwpfPR5R
9tTXg4gVMFLCgGSf0a4JsZaWq3kwNe+o7JD41h0seEf672thWFsMXmhS4Zlvacf4NxY4yhxntCPm
bZKTgd4RG5YjntuUSQTp+yVgh0TaVlo9KYbgXZmxbbLJ60n3crHjLXOP5pS82YsgKGXDCYrXMQBD
NhEec5cM8RAB/RtrA5MWoV6/PtsCIszyNNaqgxCBIo/9BDxTarwAWWH0TMYOxcXwAbFGKYzOqNh/
daakI9nDpnOp+gjwwfoF3wafMyVGGn4+Al++5+iV+BDell/nwMH6MgnDK17SySGRbKrv/8FToH5I
k0q7SpkFgE3Rx0I+Kk40Oo3vbJyjC0usgBY7myLAdKlhZ0i8JZobEHP/lbmTuGxdw5DEwAFa6h32
ScHh/XGHtx68gfWx6S/k+hfEBORaIYVm6XaaoIBJCZwfivWtt1G2mv+5jdw5c6b5L/vfOCr7HirV
4A4XTx9HbJ5ItkStCqNVKR8VszYFmskIaHYR3FaQYQeUepjy+Fp50GeOzbajv+CbALc9v2r3iSNY
UWyNy5vVjCytgI17cdmYoD+tAlvMFUczXjDxrHNVp3ejvrGNjSRC9MgRbGpE66bwF2GSw3Ir/gBP
mt/wGuDYlvDM8xwGkJD8lNVNxN8eaKF+ZpsEuBkGIc/JpqKPCnl2KzgNbAzk3llkMuJn20xA2YM7
mGf0jvOPKsYDBWJeTa9DR8alQExzG/twaGPHjyxMAwfEHbkk/CnrsllFiWWzSAQl3WAZ6kCPmRLM
PY8cjw42zUvFAvLMvutxpOB8X2nbXIGXObq4NI5Vu0sgVF+NAMng2UTQz766ROIl12D66Wf9tM2N
RBDYzqigUC5n7uADSfRPKlhmBTlSXae4hLY3cmgYHibZjGCAHFaJ15CkGDCTYMbcsa6soiuOhFAh
+C77GckZlRLkcQ7IQKlHgphNx6kPfuDQ9bmB4UFMswyfNYlfAPi+6qPYLaDtBreSHnjMYkEYFCs/
HOgIeEzD70pUj6uhk2pM7XEX5pv4aVvB6jgNyUQWDNhWi0rxcuFlSfRNyaCmOSlxC+DMrXwLGS9B
O/WqZM5FdDbiOaklqSWzGVLBvE1qTpH8ZznZqeL9XvlI2b9YQ17MtuKx8dFp/sUbSOXFgQxDnQ9v
1vsoq9gq5W2SofygzSZX9krdHnwe3yYTOPRSl40OVsTBAjFrUmEk0KL7QkMv9+aTeXiD/ThJe156
ttTkdmyMf+DTCKXc4r+9SwBvss/1oA6BzY2c4Gvx0Cb5JwObv5VTiax0qsAXTyOJLp0q6PvEXVZP
mzgRbXuo7BFY3g9p3w1EinOuF6uejvhCBPrE0HhF98ab4By8WCDdhdSs2gm7kVrFdC72P2gWqz60
Rjh+XaVKTj99kfVj3CwnIsJAVL8sEo0/aGRNE4bxzRP+qPL7rPXigMFWohFvwzqljMWFhLt9jk9F
i17GPOqmQJ8rrgGCunoHsemrGOWhZVK8+GefndukrCO76cAGhXy/VUz/qtl4CVpuYWNCJT2Z/fAt
y8fRuRKLTSTHjyC5stGwYpoeYZhTxvjKNcPC31AUGEIBUe0hNXZuR8vYA5c0YKak7MyCGdpx0vbb
b74xSYZby4l2MezgKI7SWF2UjI/V7nlaME6AsgzHE2O+ygQ+0fuXpyYl7wZHP3FtUrXmsA/NJQyO
joSqhzgn5HTPP27yGQgCt7yKJFxqbI/zTSh8jM73NHL0lIeecNMRzwlAl64gEXO+z6LcPhQAqZ2J
KC6Am4PuKl6FG++MMaF6gUL+mDU+4dhLc/KWvNgIsHptCDdTr8pmbaO0epj6kRI0mp0bcYSsduy+
9X0RVHES1G4qOyVLHZucw5chIsb1QvwEgu5tNTjLJjZx92+LArAvwPbZz3yzEkT6Ig2J99uzVpX6
xJFFtE6iNV/+bY7K7K45cmdtZM3u6CrR2QRYvTnGSz15xQ/FIHavicWVEl+6H8ttsMHIG3jK5lZN
D6PH3aFWJ9EcOpuXvEYFDNz00lKDeL2yNKY4hprcU1oJfUAGldPU1/lDFxgBSUCBAwFHCT5dcRts
PH54dBY44HQ37HEBXe2ueaPk6hSBTkZIhaYJxBQWUe+kKBMT8nLMMFrbOX/wt1lYSyrrB4RBk/k7
np1ZQ7x07UP+vWA6R4JHmtql43xB7q5jS7sy9LLYvWfStB7pmLfUAvOs6fRgXp3du03uhBAVPt8n
QQp5wlghNW+iYz/cRhKlgHrFHftoK6dMTZW5jsowkGzBLLFnCpy3QLetJlEeOp1pqTJPL4i8JPFi
aMSa16AyMyjBJmylF2aMMg/e4CecbXrtDsuRP0FCARXL4JnBm67DRr4Rmu7IuQaC/YsWZ4wiPEpS
+S92cXXWEt3eElADDTrUt0Nxe4K82ptn3zPUGcqnUDItLBh7pGg4vCWnwtKXa5MidpGZCtYLXnEM
yi1vSz4AbfqOkHc+UDx7wEPx8UwjLvxLxG6EH7j9DenqV67J2rOHWDjMLbWz+VNxisfCDhrR1WlW
G7ZmppSyMIJw1jB/zQ3TiSiFrmXuIF7Ev/ujJZrTAb1rz98Ftorg1TL7Y+cAXOkd2M0elrk0Aidl
TPUJPP2QOUunivrDKQbwhJILdhp1kEogh9raA5CP5wpfwp1B1M40EBDI7zjAFLWpefzUikG3H3YC
2JXS+cRMAjONzbb0CyTGaoHNcg1zxu6YcL7HUXzAoU7NpV/BqqehfwjgBmwIAcMd2gEyNrfcIOI9
wqfxGxeSQPfbTcAnZTGSazGxEq5YLUi1dhegw2eiARhMSOHBcy8SphcnHUv+gQnO5Z0gaxy/TdSo
XiuXRjCVJebgbveZA1xehH6EweqyMjOfHV/dO88oongjrvB5RsVxUonE9RwKFB6si/uYQKKZYHuq
5dCv/AIjqeYv9rRYuJo/CHZDzZkso7ixFsIJRjJ9sTlSQO5V2UDBsI0oyPlSjb4avUizHQqnV58c
jEkuk9UIszV2grOnn+voJI3rXCjTWJ9K4YfOFGDew7IvbDENO2vHvaM7UFp/lQ64BeUKU0XqRV0I
qKIlu8MHLdLO5lV6BL2lqfRzQDLcs4xrQ7oBgoi18ePXR+ZLRoW6YvXyQhK75/7G49tZyQJfew3y
7D7nge3E6iUKzgim9VLZAfA1Sk5cnCMMXmkdWKIjI/iRe+1uMuNXnCoLKcU/mS/r+lgjUU1DBt24
Pyw+OP2KhRs+M3eNiVCItp+mmwca5i8uUxMrs9fCOO3lzLUekBrKR9L16q7xFzOyyd9FHgpDkNlR
+TLGd/Q2sidn4AswKqzZ5Mnxqy66xie2TgaDtRmhru3x9OrIn4xBcV5Sh9b1G6mMRtSU/QTG5UVg
5u74HTdJwFsiyd8jLdhLTAuq9XkdsjdY+uP8euFv2yGOGTe4/1MBCZFMEQhLd2LhsZcLWZHr/Uco
cNl0utq9z9p8yLbZbpAgoKonLbp7zpvY0VFswZyS2I6+AJ8GKSHuqDXKswrAs7Bb2JZGCFbT6g+v
+Mtoz6ROhELjdEMw8azcamO8jTDUtTJrELXIpGPqXPkNzCnYe0JMQxWA4mjp+cBsZekBQkKiwJ+L
auCCehdrR4eoyTfFJ67V5zzfhO6rTmPlrVCcqNAa8V/3S/q9T8kSJQFBhxFS93vaOTXJdlWe5oYb
bx7k2l1uXnygqc9h8+AeJMxBRros+TZipVGFhzlyOepuUxAXXkitD3WYKPqQu7+t9q54LPd7LaiL
njpR615OQiYxqzfVBXrP+UqxtW+PbvFHiMcl/VPuXNsukXM6fvo88UGYEQiYO2rzWKPCEneakZxM
WHAY3qCjUl4xLDlTfRIOAyLTSNC/krZv61pMFvWHBkWL3b5e2/RwCCHfV+thmLsEq2FkA01mKi8I
oPQe76p24/zzpENYLDjdyRXr8LWLuvjyH+N2H/b5lm7vUSOIgNbij7sHOfuP4rqMw5F4JFr//MoZ
/gcKklt4nPd3pU60/0bBBZgtnlIOLgsljE244CpbaiPX6RxHMX2ikP4ZQf2FrhDFwJwriP/kKd/d
Quh9ZeOIyGU4NUdS7TR7iUKV9ZvJlhrpFLlJmqsBMhrRSzAvre0C2xKqro1CBpc5203l6eMurV5c
GoN6y+5xsdHMpjU0JDheAChhKa8XsZT0eaA5vAXf45Kpw2XH63HpoKvf6lwU2y4TRf2lYPsii94B
h5HVe9SVaob2WiVA9A7B5r8HJWaih2hP4enj7yLZWNrmz4/Vl2KgDciPypOm8UIq/2YdR9GT3CNb
2rzIfqsAQR+Mu06iMoGuBUL1iAor+ZQJ6hehngkEzmWyEualg2tJBXagOWo7AfrL6DLno1U4vcS+
EUHCWT+FNDZBq+72G6AT+m9zNMPSoKNrmBh+93rsnnvXjL+56XUY01fkpHNPQgxFdPxXDCgZpWBb
jlhJOD/Yp2OjxHdnmq3+9pMVSv9hhxo8swfrL7ehslv5b06Rt9iD/Ly1AF39L1dUDbvdM++2bYZ2
UrJILc35HIMryXNdebctAXSUjrm0txZSIaiN27IWXJMu0/v+X3LSICkb8GeUwgiA+SGEnT3kPAZm
77LIBh+SEcgA3P/26UMXWWCFgPelTI0Z5d2rPEAheDLX8gD7Xty5v7pOFN9GhCPI4lxt16VsUySY
ZbIs5ACH+gET0eyAR06VPhg+1XTYdBACoqCsBlTW69p7T3yaAXgGURgkKApi1yMaktW3p5q6lIc0
fIms5bIhijKcsW+uKUwgKHZWhWsoy4L/5Zw4rg6e570S33p8pLHzBVqyUYrwZlFYpVbwGgs8MO24
Sg6XKmszqDq9cEu29/rKwW+okYQHDY+uyR2yeKCCVgv1YFUXmZ/fJJbNl9FI7aXJFErp5LgyLIX0
9hnGWT4bzmlTDp/1RjJRqQUObSc7PodApCx/d42YdNsvEjkQHNJaNnY+VDjMylAtAUX+1uENzemG
hxl9qgMnd9Yqt4E93887zVF3jcNoDG9i8nYwcoozAR5r/dndUxfLBcTMqubD5tjogc5zSmCO/CAH
36XbjAd9+tKVGi6ENeroLtsTJ+cp9tGT/KzQrOl7j9Pekiey0X0DBjVceOYejUPpp2AY4oCjrhew
u2fH8r6Nwz2r0x0OTqOdlGcDXo7CdV60uOXHMo7A5cmRWh84FuLKjds7sAfNbGXplVvpsLv/Ui1A
Z6SqI2vPBuaCmf6coIYtWUCg5hUmvMIw6tXoJrURt35lfSyoNYi9nKE8aEXIxtLRoub6MugZN6+b
ESEyoptewHrDIyFtJ5v2yGZ1u5MTXH18g1utVR9YllSiqb97eYvPqq+r8hT0uHhqIXgeU7tFa9Ze
mKBMHQaKwvuTyQgMOIJ9cceRw/sz5yT9RS+ZAxOQwQL0nzxPNOjr8b2hP8D22jc16gTROyJFpThu
efh1uTt9f7yW0jhjDpA8RoSgae1TBSGP0IEP1SNlzzSIbiCcwwfu9+1Tfp6V6n6jS4bVjCV0pKI6
aI+oEZg1iSjRZgsFzAkkfat6ZrDoFLZZjlG0q3z4sZ+CYBproa5tAsF7jvPdCpVqI2HG4717OWHw
sUFQwsh+WVIk8BzF1R2C7n19C6FSiAx44dH7bPlK+BOiAE6qGqtIfP7t7FikgE3txmnSvKBQ1lez
PSBbSGcORE7QoTSmThCIYi+I8rrGj26j6HUyMFSIchAdfGVG+xAWb1HlLTrUIHE4bgWlX0mWHD0D
rqF5WwT7UUjvHaK9uG0iardgKd8+CjmRmuoMcRTa2sO5RtXAewZ9PUkUqKU1ku/L5+P3IMOtZdvi
s748CeGByuL9/5oioEVQz81jCgl+PWeaBNKvrtBBKPPIa5ldBe1024sx5Kn8g1HKX8Pe/EkYxqyY
YsgEBHxh/WjZj+TCXGS59aL5UqXv8tsMFOobSjWEds5a1uCENAlxxRw3BVeGxUiTIHGBhq9z1STy
rgWh6XHS4pzFtjMAZ+FvxbsjE/OMbbGcvvHe84+5lLEN9PQgNQLnpPuwfyCcgMxzfMxo/WSVW3NO
7xXNVIeZGBzeI/DDq2wtFv/H8rwseFXMU7s85Y4jCYGDwtGBAbhl9cg1HFSIFMBIYLGQ5FehAJKe
N9vphVrmPYk89pSkIIrC52QBQGZ/QKYkYRUU2IGC8M3EWmrmwybUcTUcOCdp6hDDgr7whY5qlvJ1
TS+u+tJEDY5pG3Pgl8eQtYPiM8TubY7yAWrXRVWNkNN5GhdUepf7Yi+VUYfd0GOMSubgGWjT974F
1I05PvFNG++87akoSEUgrKnNt1PsO+MpbHo5hmleLUur1GlRyIkxlflQWizEcYL0MJ+JFj8yWfMo
m9C00gY93aRxtYN8PiIF7O3B+XSxH9tma94TToUATEQx2YAtWvsEl11/LQXoVAfsxx54g/+T9vB4
JOWhi4FumdtLsXz3uHECb5XZ0cuzvCd3izbpCPuTEQDShKKJKFcD1U+WFH79NmjoJHCNm0KOwiMa
mlm5QLua/gk3JVM/CsloPfEj/2CKP0aE0cxeu9y01v3sKpCQGQ09m1fCgR+jCnC8phoX44ewhSdV
FtJD4+IWAvr1ccQRmlG74dR86dcY8W74Y1bgdAgyXHhATYvxrlRhOocNRQLQ2QGy0sgYiGFhFYJP
2zNPdvB8mYuM28tFo8lX8PLm60X/2gDAXI7UP5J1/6kGHkOQCDkefrSDBuiLmFBDCY7oHSGa3TXN
/Ahr8f1dULQU7wdSY+3GGRGmQRaGo0T0RF8FwrmmvsZTZlOo9H0SLGmbjy+i0/TWqWcTBm6ooyc+
dhj0Z7+gKi4hBscEXYkjV0Jgg1tFXj7YmkleVKYsh8h6S4M2chsoMMQL9J4lL4W08qcOuhVriuG7
P6beQbHl2OdfEx9cydi+/CUJe79GBJMSM1XE1mzeQy39hibl+tQlzVUmWG6anXim2CZaAnLdFTQU
o3MrZ661NpbdJXh8I7vgnuDcRd0+vz7YjtOrPAr8DtjmnA5vOclmyml3xXWfx+kz4RRvNvBlaw6P
OcN/4ZmcYMx+yLu8jeQpGy4iGSWktgJZBfZXNPHPPGZIeOn7xD0n+Y5rmjZSQl1Tp5fxsPqMmJzJ
O43FGn4W2APEj5i8djzHccMcGjO5VhpvksNFgd3yk4dy4VWhZaFYJZLxiibiL+tXNKdZqasVLhjO
pj4YHBpL6xgEA8QE2/2QgAKGKERUhlc5P9l/cSMZk0AutfiaHoxQbO9PIu/O21Df4Z7F13r8FsjN
q2LGA29MgrsZIAYwRpjANNWqkHdgdN9X5Xro9n/BrOgTwn5cuN1sdbgct44iRT+MFBRXDKe+MFqY
DRni/e3soqhJQXhNtWqYE+0JPwRG9nSEkcrLHOc8TEz6v/CXzEjKFMMncU3Yyj+QkT35fDO77k/A
QJQiiZ95UcfEp27UnQ6wFWUX2/iLskvxmy2EnQbiAscN3OdUKHFXjX03aWZN0yJSvV4z1GkaCOQh
yt8J2pGWkPV4X3258qAvxhJDBcNVsu0dTvwhJoPJpBySUl8JYuZFSwmB+WszptX49S05PqUt/Cfh
MrJSVNozt667LWNfSzPArVFHfLYwQtSJ3tol+EQSWh4uKeKaNBJsbMXnin4GhIjRZXgZrDmMcvYX
Rq/r5J+qB8DJrkHxZSipxsXEADYgqH2rbWIXFBL523siPLdmaL83WGhVt23pVjNFG+AxdhXikA8S
e1A5VGAyxxOhUmspL2xeeY0n9S25euRZ4ryCgycMc7a5qSS+Be/blI39I36QgfrAozJpO5yJk2ka
ybYXJIJRI23QcPOG3A2WKjm+LwxDvrCG5LrqT98RA11VUABt8NJdJ4JDoSQtPP5017X+xa05tH4v
sDiTlJSUIl26HPJXubuO0ULvSG4EspM8OlGNNnK274jVaB5q6o9OXoDQhPmMrilOPdmIuPq7dwEt
nxKGucabu7vdZw==
`protect end_protected
| mit | 61dfd916ae22cad61a8f3f63ca5e21f1 | 0.952236 | 1.81782 | false | false | false | false |
APastorG/APG | average_calculator/average_calculator_s.vhd | 1 | 4,571 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Vivado by Xilinx
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is the interface between the instantiation of an adder an its core. It exists to make it
/ possible to use external std_ulogic_vector which contain the numeric values while having modules
/ which are able to manipulate this data as fixed point types (either u_ufixed or u_sfixed).
/ As std_ulogic_vector have a natural range and the u_ufixed and u_sfixed types have an integer
/ range ('high downto 0 is the integer part and -1 downto 'low is the fractional part) it is needed
/ a solution so as to represent the negative indexes in the std_ulogic_vector. A solution is
/ adopted where the integer indexes of the fixed point types are moved to the natural space with a
/ transformation. This consists in limiting the indexes of the fixed point data to +-2**30 and
/ adding 2**30 to obtain the std_ulogic_vector's indexes. [-2**30, 2**30]->[0, 2**31]. For example,
/ fixed point indexes (3 donwto -2) would become (1073741827, 1073741822) in a std_ulogic_vector
/ Additionally, the generics' consistency and correctness are checked in here.
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.adder_pkg.all;
use work.fixed_generic_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity average_calculator_s is
generic(
DATA_IMM_AFTER_START_opt : boolean := false; --default
SPEED_opt : T_speed := t_min; --exception: value not set
ROUND_STYLE_opt : T_round_style := fixed_truncate; --default
ROUND_TO_BIT_opt : integer_exc := integer'low; --exception: value not set
MAX_ERROR_PCT_opt : real_exc := real'low; --exception: value not set
S : positive --compulsory
);
port(
input : in u_sfixed_v; --unconstrained array
clk : in std_ulogic;
start : in std_ulogic;
valid_input : in std_ulogic;
output : out u_sfixed; --unconstrained array
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture average_calculator_s1 of average_calculator_s is
constant P : positive := input'length(1);
/* constant CHECKS : integer := average_calculator_CHECKS();*/
/*================================================================================================*/
/*================================================================================================*/
begin
average_calculator_core_s1:
entity work.average_calculator_core_s
generic map(
DATA_IMM_AFTER_START_opt => DATA_IMM_AFTER_START_opt,
SPEED_opt => SPEED_opt,
ROUND_STYLE_opt => ROUND_STYLE_opt,
ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
S => S,
P => P,
input_high => input'element'high,
input_low => input'element'low
)
port map(
clk => clk,
input => input,
valid_input => valid_input,
start => start,
output => output,
valid_output => valid_output
);
end architecture; | mit | 34999a0eaae6dc45a496aadcbe0b2c0f | 0.456028 | 4.582828 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/host/VGA Console/mips_vram/mips_vram.vhd | 1 | 6,122 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file mips_vram.vhd when simulating
-- the core, mips_vram. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY mips_vram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END mips_vram;
ARCHITECTURE mips_vram_a OF mips_vram IS
-- synthesis translate_off
COMPONENT wrapped_mips_vram
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_mips_vram USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 12,
c_addrb_width => 12,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 4096,
c_read_depth_b => 4096,
c_read_width_a => 16,
c_read_width_b => 16,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 4096,
c_write_depth_b => 4096,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 16,
c_write_width_b => 16,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_mips_vram
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END mips_vram_a;
| gpl-3.0 | 0eacb7a6b4c29c807387d3754831ffcd | 0.538386 | 3.886984 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/cham_rom/cham_rom/simulation/cham_rom_synth.vhd | 1 | 6,828 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cham_rom_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY cham_rom_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE cham_rom_synth_ARCH OF cham_rom_synth IS
COMPONENT cham_rom_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: cham_rom_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| gpl-3.0 | 590d1d8225cccff00995eccfcfaa5d70 | 0.579965 | 3.797553 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/service/src/spi_comm.vhd | 1 | 2,835 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity spi_comm is
port(
CLK : in std_logic;
RESET : in std_logic;
SPI_CS_A : in std_logic;
SPI_CS_D : in std_logic;
SPI_SCK : in std_logic;
SPI_DI : in std_logic;
SPI_DO : out std_logic;
ADDR_O : out std_logic_vector(7 downto 0);
ADDR_I : in std_logic_vector(7 downto 0);
ADDR_REQ : out std_logic;
ADDR_ACK : in std_logic;
DATA_O : out std_logic_vector(7 downto 0);
DATA_I : in std_logic_vector(7 downto 0);
DATA_REQ : out std_logic;
DATA_ACK : in std_logic );
end spi_comm;
architecture RTL of spi_comm is
signal ADDR_IN : std_logic_vector (7 downto 0);
signal DATA_IN : std_logic_vector (7 downto 0);
signal ADDR_OUT : std_logic_vector (7 downto 0);
signal DATA_OUT : std_logic_vector (7 downto 0);
signal CS_A_LAST : std_logic_vector (1 downto 0);
signal CS_D_LAST : std_logic_vector (1 downto 0);
signal A_REQ : std_logic;
signal D_REQ : std_logic;
begin
DATA_REQ <= D_REQ and not DATA_ACK;
ADDR_REQ <= A_REQ and not ADDR_ACK;
process (SPI_SCK)
begin
if rising_edge(SPI_SCK) then
if SPI_CS_A = '0' then
ADDR_IN <= ADDR_IN (6 downto 0) & SPI_DI;
elsif SPI_CS_D = '0' then
DATA_IN <= DATA_IN (6 downto 0) & SPI_DI;
end if;
end if;
end process;
process (CLK) is
begin
if rising_edge(CLK) then
if RESET = '1' then
CS_A_LAST <= "11";
CS_D_LAST <= "11";
A_REQ <= '0';
D_REQ <= '0';
else
if ADDR_ACK = '1' then
A_REQ <= '0';
end if;
if DATA_ACK = '1' then
D_REQ <= '0';
end if;
CS_A_LAST <= CS_A_LAST(0) & SPI_CS_A;
CS_D_LAST <= CS_D_LAST(0) & SPI_CS_D;
if CS_D_LAST = "01" then
DATA_O <= DATA_IN;
D_REQ <= '1';
end if;
if CS_A_LAST = "01" then
ADDR_O <= ADDR_IN;
A_REQ <= '1';
end if;
end if;
end if;
end process;
process (SPI_SCK, ADDR_I, SPI_CS_A, DATA_I, SPI_CS_D)
begin
if SPI_CS_A = '1' then
ADDR_OUT <= ADDR_I;
elsif falling_edge(SPI_SCK) then
ADDR_OUT <= ADDR_OUT(6 downto 0) & '0';
end if;
if SPI_CS_D = '1' then
DATA_OUT <= DATA_I;
elsif falling_edge(SPI_SCK) then
DATA_OUT <= DATA_OUT(6 downto 0) & '0';
end if;
end process;
SPI_DO <= ADDR_OUT(7) when SPI_CS_A = '0' else DATA_OUT(7) when SPI_CS_D = '0' else 'Z';
end RTL;
| gpl-3.0 | b919080586e3a5fbabe387becaf79a9b | 0.482187 | 3.105148 | false | false | false | false |
simpway/HDLC-ICEC | firmware/HDLC_TXRX.vhd | 1 | 4,002 | --!-----------------------------------------------------------------------------
--! --
--! BNL - Brookhaven National Lboratory --
--! Physics Department --
--! Omega Group --
--!-----------------------------------------------------------------------------
--|
--! author: Kai Chen ([email protected])
--!
--!
--!-----------------------------------------------------------------------------
--
-- Create Date: 21:33:01 2015/11/18
-- Design Name:
-- Module Name: HDLC_TXRX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: The MODULE to send data to IC/EC bit, and receive data from
-- IC/EC bit. The data encoding and decoding to/from HDLC shold
-- be done in software. This module only send and receive data
-- to a multi-bytes register. users can change its width.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity HDLC_TXRX is
generic (
REG_WIDTH : integer := 256
);
port (
rx_long_data_reg_o : out std_logic_vector(REG_WIDTH-1 downto 0);
tx_long_data_reg_i : in std_logic_vector(REG_WIDTH-1 downto 0);
tx_trig_i : in std_logic;
rx_trig_o : out std_logic;
txclk_40m : in std_logic;
rxclk_40m : in std_logic;
IC_RX_2b : in std_logic_vector(1 downto 0);
IC_TX_2b : out std_logic_vector(1 downto 0)
);
end HDLC_TXRX;
architecture behv of HDLC_TXRX is
signal tx_long_data_reg : std_logic_vector(REG_WIDTH-1 downto 0);
signal tx_long_data : std_logic_vector(REG_WIDTH-1 downto 0);
signal rx_long_data_reg : std_logic_vector(REG_WIDTH-1 downto 0);
signal rx_long_data : std_logic_vector(REG_WIDTH-1 downto 0);
signal rx_trig : std_logic := '0';
signal rx_trig_r : std_logic := '0';
signal rx_trig_2r : std_logic := '0';
signal RX_IDLE : std_logic := '1';
begin
rx_long_data_reg_o <= rx_long_data_reg;
tx_long_data_reg <= tx_long_data_reg_i;
process(txclk_40m)
begin
if txclk_40m'event and txclk_40m='1' then
if tx_trig_i = '1' then
tx_long_data <= tx_long_data_reg;
else
tx_long_data <= "11" & tx_long_data(255 downto 2);
end if;
IC_TX_2b <= tx_long_data(1 downto 0);
end if;
end process;
process(rxclk_40m)
begin
if rxclk_40m'event and rxclk_40m = '1' then
rx_long_data <= IC_RX_2b & rx_long_data(255 downto 2);
rx_trig_r <= rx_trig;
rx_trig_2r <= rx_trig_r;
rx_trig_o <= rx_trig_2r;
if rx_long_data(7 downto 0) = "01111110" and RX_IDLE = '1' then
rx_long_data_reg <= rx_long_data;
rx_trig <= '1';
elsif rx_long_data(8 downto 1) = "01111110" and RX_IDLE = '1' then
rx_long_data_reg <= '1' & rx_long_data(255 downto 1);
rx_trig <= '1';
else
rx_trig <= '0';
end if;
-- if rx_trig_2r = '1' then
-- rx_long_data_reg <= rx_long_data;
-- else
-- rx_long_data_reg <= rx_long_data_reg;
-- end if;
if rx_long_data(7 downto 0) = "11111111" or rx_long_data(7 downto 0) = "11111110" or rx_long_data(7 downto 0) = "01111111" then
RX_IDLE <= '1';
elsif rx_trig='1' then
RX_IDLE <= '0';
else
RX_IDLE <= RX_IDLE;
end if;
end if;
end process;
end behv;
| gpl-3.0 | baa762bcd86b229ab2bdc0fc11cd19fd | 0.475762 | 3.464935 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/lvov.vhd | 1 | 21,478 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- SRAM is used for Lvov Main 64Kb RAM
-- FPGA is used for all ROM's (16Kb Standard, 16Kb Chameleon )
-- FPGA is used for 16Kb Dual Port VRAM
entity lvov is
Port (
CLK50 : IN STD_LOGIC;
PS2_CLK : in STD_LOGIC;
PS2_DATA : in STD_LOGIC;
SRAM_A : out std_logic_vector(17 downto 0);
SRAM_D : inout std_logic_vector(15 downto 0);
SRAM_WE : buffer std_logic;
SRAM_OE : buffer std_logic;
SRAM_CE0 : buffer std_logic;
SRAM_CE1 : buffer std_logic;
SRAM_LB : buffer std_logic;
SRAM_UB : buffer std_logic;
SOUND_L : out std_logic;
SOUND_R : out std_logic;
IO : out std_logic_vector(15 downto 0);
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_SCK : out std_logic;
SD_CS : out std_logic;
VGA_R : OUT STD_LOGIC_VECTOR(3 downto 0);
VGA_G : OUT STD_LOGIC_VECTOR(3 downto 0);
VGA_B : OUT STD_LOGIC_VECTOR(3 downto 0);
VGA_HSYNC : OUT STD_LOGIC;
VGA_VSYNC : OUT STD_LOGIC );
end lvov;
architecture Behavioral of lvov is
component T80se is
generic (
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 1; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
IOWait : integer := 1 ); -- 0 => Single cycle I/O, 1 => Std I/O cycle
port (
RESET_n : in std_logic;
CLK_n : in std_logic;
CLKEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end component;
component mips_soc
port (
-- CLOCK
CPU_CLK : in std_logic;
VGA_CLK : in std_logic;
CPU_RESET : in std_logic;
-- VGA
VGA_R : OUT STD_LOGIC_VECTOR(3 downto 0);
VGA_G : OUT STD_LOGIC_VECTOR(3 downto 0);
VGA_B : OUT STD_LOGIC_VECTOR(3 downto 0);
VGA_VSYNC : out std_logic;
VGA_HSYNC : out std_logic;
-- SRAM
MEM_A : out std_logic_vector(31 downto 2);
MEM_DI : out std_logic_vector(31 downto 0);
MEM_DO : in std_logic_vector(31 downto 0);
MEM_MASK : out std_logic_vector(3 downto 0);
MEM_WR : out std_logic;
MEM_REQ : out std_logic;
MEM_BUSY : in std_logic;
-- Keyboard
KEYB_DATA : in std_logic_vector(7 downto 0);
-- Sound
MIPS_BEEPER : out std_logic;
-- SD Card
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_SCK : out std_logic;
SD_CS : out std_logic;
-- FDC Ports
VG93_CLK : in std_logic;
VG93_nCLR : in std_logic;
VG93_IRQ : out std_logic;
VG93_DRQ : out std_logic;
VG93_A : in std_logic_vector(1 downto 0);
VG93_D_IN : in std_logic_vector(7 downto 0);
VG93_D_OUT : out std_logic_vector(7 downto 0);
VG93_nCS : in std_logic;
VG93_nRD : in std_logic;
VG93_nWR : in std_logic;
VG93_nDDEN : in std_logic;
VG93_HRDY : in std_logic;
FDC_DRIVE : in std_logic_vector(1 downto 0);
FDC_nSIDE : in std_logic;
TST : out std_logic
);
end component;
COMPONENT a8255 IS
PORT(
RESET : IN std_logic;
CLK : IN std_logic;
nCS : IN std_logic;
nRD : IN std_logic;
nWR : IN std_logic;
A : IN std_logic_vector (1 DOWNTO 0);
DIN : IN std_logic_vector (7 DOWNTO 0);
PAIN : IN std_logic_vector (7 DOWNTO 0);
PBIN : IN std_logic_vector (7 DOWNTO 0);
PCIN : IN std_logic_vector (7 DOWNTO 0);
DOUT : OUT std_logic_vector (7 DOWNTO 0);
PAOUT : OUT std_logic_vector (7 DOWNTO 0);
PAEN : OUT std_logic;
PBOUT : OUT std_logic_vector (7 DOWNTO 0);
PBEN : OUT std_logic;
PCOUT : OUT std_logic_vector (7 DOWNTO 0);
PCEN : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
-- CLK 32.5 MHz is 1/2 of pixelxlock 1024x768@60Hz (65MHz)
signal CLK : std_logic;
signal nRESET : std_logic := '0';
signal TICK : std_logic_vector(3 downto 0) := "0000";
signal LOCKED : std_logic;
signal nRESET_MEM : std_logic := '0';
signal SRAM_DO : std_logic_vector(7 downto 0);
signal KEYB_A : std_logic_vector(7 downto 0);
signal KEYB_D : std_logic_vector(7 downto 0);
signal KEYB_A2 : std_logic_vector(3 downto 0);
signal KEYB_D2 : std_logic_vector(3 downto 0);
signal KEYB_CTRL : std_logic_vector(7 downto 0);
signal COLORS : std_logic_vector(6 downto 0);
-- ROM_INIT = 1 on reset and maps ROM to address 0000
-- ROM_INIT = 0 on first I/O write
signal ROM_INIT : std_logic := '1';
-- CPU_CLK is 2.16MHz (32.5MHz/15) CPU Clock (Original 2.22MHz (20MHz/9))
signal CPU_CLK : std_logic;
signal nCPU_RD : std_logic;
signal nCPU_WR : std_logic;
signal CPU_A : std_logic_vector(15 downto 0);
signal RAM_A : std_logic_vector(17 downto 0);
signal CPU_DI : std_logic_vector(7 downto 0);
signal CPU_DO : std_logic_vector(7 downto 0);
signal nIO_RQ : std_logic;
signal nMEM_RQ : std_logic;
signal nCPU_WAIT : std_logic;
signal LV_SRAM_DO : std_logic_vector(7 downto 0);
signal nLV_SRAM_CS : std_logic;
signal ROM_D : std_logic_vector(7 downto 0);
signal SD_CLK_R : std_logic;
signal SD_DATA : std_logic_vector(6 downto 0);
signal SD_O : std_logic_vector(7 downto 0);
signal VRAM_DO : std_logic_vector(7 downto 0);
signal VRAM_WE : std_logic_vector(0 downto 0);
signal VRAM_VA : std_logic_vector(13 downto 0);
signal VRAM_VD : std_logic_vector(7 downto 0);
signal nVRAM_CS : std_logic;
signal nVRAM_EN : std_logic;
signal VV55_SYS_DO : std_logic_vector(7 downto 0);
signal VV55_KBD_DO : std_logic_vector(7 downto 0);
signal nVV55_SYS_CS : std_logic;
signal nVV55_KBD_CS : std_logic;
signal nROM_CS : std_logic;
signal nHALT : std_logic;
signal nRFSH : std_logic;
signal BEEPER : std_logic;
signal BEEPER_EN : std_logic;
-- Lvov VGA Signals
signal LV_VGA_R : STD_LOGIC_VECTOR(3 downto 0);
signal LV_VGA_G : STD_LOGIC_VECTOR(3 downto 0);
signal LV_VGA_B : STD_LOGIC_VECTOR(3 downto 0);
signal LV_VGA_HSYNC : STD_LOGIC;
signal LV_VGA_VSYNC : STD_LOGIC;
-- VGA Select Signal
signal VGA_SEL : std_logic := '0';
signal CLK25 : std_logic;
signal MIPS_RESET : std_logic := '1';
-- Host VGA Signals
signal MIPS_VGA_R : STD_LOGIC_VECTOR(3 downto 0);
signal MIPS_VGA_G : STD_LOGIC_VECTOR(3 downto 0);
signal MIPS_VGA_B : STD_LOGIC_VECTOR(3 downto 0);
signal MIPS_VGA_HSYNC : STD_LOGIC;
signal MIPS_VGA_VSYNC : STD_LOGIC;
-- Host SRAM Signals
signal MIPS_MEM_A : std_logic_vector(31 downto 2);
signal MIPS_MEM_DI : std_logic_vector(31 downto 0);
signal MIPS_MEM_DO : std_logic_vector(31 downto 0);
signal MIPS_MEM_MASK : std_logic_vector(3 downto 0);
signal MIPS_MEM_WR : std_logic;
signal MIPS_MEM_REQ : std_logic;
signal MIPS_MEM_BUSY : std_logic;
signal MIPS_KEYB_DATA : std_logic_vector(7 downto 0);
signal MIPS_BEEPER : std_logic;
-- FDC Ports
signal VG93_nCLR : std_logic;
signal VG93_CLK : std_logic;
signal VG93_IRQ : std_logic;
signal VG93_DRQ : std_logic;
signal VG93_D_OUT : std_logic_vector(7 downto 0);
signal VG93_nCS : std_logic;
signal VG93_nDDEN : std_logic;
signal VG93_HRDY : std_logic;
signal FDC_DRIVE : std_logic_vector(1 downto 0);
signal FDC_nSIDE : std_logic;
signal nFDC_CS : std_logic;
signal TST : std_logic;
-- PK-02 Signals
signal PORT_F0_CS : std_logic;
signal RAM_PAGE0 : std_logic;
signal RAM_PAGE1 : std_logic;
signal nROM_EN : std_logic;
signal HI_RES : std_logic;
signal BLANK_SCR : std_logic;
signal INT_EN : std_logic;
signal RAM_BANK0 : std_logic;
signal RAM_BANK1 : std_logic;
signal int_cnt : std_logic_vector(19 downto 0);
signal nINT : std_logic := '1';
signal nM1 : std_logic;
-- AY Signals
signal CLC : std_logic;
signal nAY_CS : std_logic;
signal AY_DO : std_logic_vector(7 downto 0);
signal AY_A : std_logic_vector(7 downto 0);
signal AY_B : std_logic_vector(7 downto 0);
signal AY_C : std_logic_vector(7 downto 0);
signal AY_BC : std_logic;
signal AUDIO_L : std_logic_vector(9 downto 0);
signal AUDIO_R : std_logic_vector(9 downto 0);
signal clc_cnt : std_logic_vector(4 downto 0);
begin
LV_Z80:T80se
port map (
RESET_n => nRESET,
CLK_n => CPU_CLK,
CLKEN => '1',
WAIT_n => nCPU_WAIT,
INT_n => nINT,
NMI_n => '1',
BUSRQ_n => '1',
M1_n => nM1,
MREQ_n => nMEM_RQ,
IORQ_n => nIO_RQ,
RD_n => nCPU_RD,
WR_n => nCPU_WR,
RFSH_n => nRFSH,
HALT_n => nHALT,
BUSAK_n => open,
A => CPU_A,
DI => CPU_DI,
DO => CPU_DO
);
u_Host : mips_soc
PORT MAP (
-- CLOCK
CPU_CLK => CLK,
VGA_CLK => CLK25,
CPU_RESET => MIPS_RESET,
-- VGA
VGA_R => MIPS_VGA_R,
VGA_G => MIPS_VGA_G,
VGA_B => MIPS_VGA_B,
VGA_VSYNC => MIPS_VGA_VSYNC,
VGA_HSYNC => MIPS_VGA_HSYNC,
-- SRAM
MEM_A => MIPS_MEM_A,
MEM_DI => MIPS_MEM_DI,
MEM_DO => MIPS_MEM_DO,
MEM_MASK => MIPS_MEM_MASK,
MEM_WR => MIPS_MEM_WR,
MEM_REQ => MIPS_MEM_REQ,
MEM_BUSY => MIPS_MEM_BUSY,
-- Keyboard
KEYB_DATA => MIPS_KEYB_DATA,
-- Sound
MIPS_BEEPER => MIPS_BEEPER,
-- SD Card
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_SCK => SD_SCK,
SD_CS => SD_CS,
-- FDC Ports
VG93_CLK => VG93_CLK,
VG93_nCLR => VG93_nCLR,
VG93_IRQ => VG93_IRQ,
VG93_DRQ => VG93_DRQ,
VG93_A => CPU_A (1 downto 0),
VG93_D_IN => CPU_DO,
VG93_D_OUT => VG93_D_OUT,
VG93_nCS => VG93_nCS,
VG93_nRD => nCPU_RD,
VG93_nWR => nCPU_WR,
VG93_nDDEN => VG93_nDDEN,
VG93_HRDY => VG93_HRDY,
FDC_DRIVE => FDC_DRIVE,
FDC_nSIDE => FDC_nSIDE,
TST => TST
);
u_dp_ram : entity work.dp_sram
PORT MAP (
-- CLOCK
CLK => CLK,
nRESET => nRESET_MEM,
-- PORT A
DI_A => CPU_DO,
DO_A => LV_SRAM_DO,
ADDR_A => RAM_A,
nWE_A => nCPU_WR,
nCS_A => nLV_SRAM_CS,
nOE_A => nCPU_RD,
nWAIT_A => nCPU_WAIT,
-- PORT B - MIPS must be on chanel B
DI_B => MIPS_MEM_DI,
DO_B => MIPS_MEM_DO,
ADDR_B => MIPS_MEM_A,
nWE_B => not MIPS_MEM_WR,
nCS_B => not MIPS_MEM_REQ,
nOE_B => '0',
WAIT_B => MIPS_MEM_BUSY,
MEM_MASK_B => MIPS_MEM_MASK,
-- SRAM
SRAM_A => SRAM_A,
SRAM_D => SRAM_D,
SRAM_WE => SRAM_WE,
SRAM_OE => SRAM_OE,
SRAM_CE0 => SRAM_CE0,
SRAM_CE1 => SRAM_CE1,
SRAM_LB => SRAM_LB,
SRAM_UB => SRAM_UB
);
-- Silicone device resets port registers on reset signal
-- VHDL device - not
-- Important for nVRAM_EN
SYS_VV55: a8255
port map(
RESET => not nRESET,
CLK => CLK,
nCS => nVV55_SYS_CS,
nRD => nCPU_RD,
nWR => nCPU_WR,
A => CPU_A(1 downto 0),
DIN => CPU_DO,
PAIN => (others => '1'),
PBIN => (others => '1'),
PCIN(7 downto 5) => (others => '1'),
PCIN(4) => '1', -- TAPE IN
PCIN(3) => '1', -- PCIN 3 to 0 must be connected like this
PCIN(2) => '1', -- in order to play Hawk Storm game to work
PCIN(1) => nVRAM_EN, -- and do not corrupt memory in Hawk Storm
PCIN(0) => BEEPER, -- and other PK-02 games
DOUT => VV55_SYS_DO,
PAOUT => open,
PAEN => open,
PBOUT(6 downto 0) => COLORS,
PBOUT(7) => BEEPER_EN,
PBEN => open,
PCOUT(0) => BEEPER,
PCOUT(1) => nVRAM_EN,
PCOUT(7 downto 2) => open,
PCEN => open
);
KBD_VV55: a8255
port map(
RESET => not nRESET,
CLK => CLK,
nCS => nVV55_KBD_CS,
nRD => nCPU_RD,
nWR => nCPU_WR,
A => CPU_A(1 downto 0),
DIN => CPU_DO,
PAIN => (others => '1'),
PBIN => KEYB_D,
PCIN(3 downto 0) => KEYB_A2, -- PCIN 3 to 0 must be connected like this,
PCIN(7 downto 4) => KEYB_D2, -- otherwize BASICZ80 will run in step execution (F5) mode always
DOUT => VV55_KBD_DO,
PAOUT => KEYB_A,
PAEN => open,
PBOUT => open,
PBEN => open,
PCOUT(3 downto 0) => KEYB_A2,
PCOUT(7 downto 4) => open,
PCEN => open
);
u_AY8910 : entity work.ay8910
port map(
CLK => CLK,
CLC => CLC,
RESET => nRESET,
BDIR => not nCPU_WR,
CS => nAY_CS,
BC => CPU_A(14),
DI => CPU_DO,
DO => AY_DO,
OUT_A => AY_A,
OUT_B => AY_B,
OUT_C => AY_C );
u_DAC_L : entity work.dac
port map(
clk_i => CLK,
res_n_i => nRESET,
dac_i => AUDIO_L,
dac_o => SOUND_L );
u_DAC_R : entity work.dac
port map(
clk_i => CLK,
res_n_i => nRESET,
dac_i => AUDIO_R,
dac_o => SOUND_R );
-- u_CLOCK is PLL 50 to 32.5 MHz created using wizard
-- CLK 32.5 MHz is 1/2 of pixelxlock 1024x768@60Hz (65MHz)
u_CLOCK : entity work.clock
port map(
CLK_IN => CLK50,
CLK_OUT => CLK,
CLK_OUT2 => CLK25,
LOCKED => LOCKED
);
-- FPGA Standard Lvov ROM 16Kb first 2K replaced with Chameleon DOS ROM created using wizard.
u_ROM : entity work.cham_rom
port map(
CLKA => CLK,
ADDRA => CPU_A(13 downto 0),
DOUTA => ROM_D );
-- Handcrafted Lvov video section
u_VIDEO : entity work.video
port map(
CLK => CLK,
RESET => '1',
VRAM_A => VRAM_VA,
VRAM_D => VRAM_VD,
COLORS => COLORS,
R => LV_VGA_R,
G => LV_VGA_G,
B => LV_VGA_B,
HSYNC => LV_VGA_HSYNC,
VSYNC => LV_VGA_VSYNC,
HI_RES => HI_RES,
BLANK_SCR => BLANK_SCR );
-- FPGA Dual Port RAM 16Kb created using wizard.
u_VRAM : entity work.vram
port map(
clka => CLK,
wea => VRAM_WE,
addra => CPU_A(13 downto 0),
dina => CPU_DO,
douta => VRAM_DO,
clkb => CLK,
web => "0",
addrb => VRAM_VA,
dinb => "11111111",
doutb => VRAM_VD );
-- Handcrafted PS2 to Lvov Matrix keyboard adapter
u_KEYBOARD : entity work.keyboard
port map(
CLK => CLK,
RESET => nRESET,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
CONTROL => KEYB_CTRL,
KEYB_A => KEYB_A,
KEYB_D => KEYB_D,
KEYB_A2 => KEYB_A2,
KEYB_D2 => KEYB_D2,
VGA_SEL => VGA_SEL,
KEYB_DATA => MIPS_KEYB_DATA
);
-- Divider for CPU CLK
-- Generate CPU_CLK 2.16MHz (32.5MHz/15) CPU Clock (Original 2.22MHz (20MHz/9))
-- CLK 32.5 MHz is 1/2 of pixelxlock 1024x768@60Hz (65MHz)
-- nRESET is active during one period of CPU_CLK
process (CLK)
begin
if rising_edge(CLK) then
if KEYB_CTRL(0) = '1' then
TICK <= (others => '0');
nRESET <= '0';
CPU_CLK <= '0';
else
if KEYB_CTRL(1) = '1' then
MIPS_RESET <= '1';
end if;
if KEYB_CTRL(2) = '1' then
VGA_SEL <= '1';
end if;
if KEYB_CTRL(3) = '1' then
VGA_SEL <= '0';
end if;
if LOCKED = '1' then
TICK <= TICK + 1;
end if;
CPU_CLK <= '0';
if TICK = "1111" then
CPU_CLK <= '1';
nRESET <= '1';
MIPS_RESET <= '0';
nRESET_MEM <= '1';
end if;
end if;
end if;
end process;
-- Video output selector
VGA_R <= LV_VGA_R when VGA_SEL = '0' else MIPS_VGA_R;
VGA_G <= LV_VGA_G when VGA_SEL = '0' else MIPS_VGA_G;
VGA_B <= LV_VGA_B when VGA_SEL = '0' else MIPS_VGA_B;
VGA_HSYNC <= LV_VGA_HSYNC when VGA_SEL = '0' else MIPS_VGA_HSYNC;
VGA_VSYNC <= LV_VGA_VSYNC when VGA_SEL = '0' else MIPS_VGA_VSYNC;
-- Debug Stuff
IO(1) <= CLK; -- OSC D8
IO(3) <= MIPS_MEM_REQ;
IO(5) <= MIPS_MEM_WR;
IO(7) <= MIPS_MEM_BUSY;
IO(9) <= nLV_SRAM_CS;
IO(11) <= nCPU_WR;
IO(13) <= nCPU_WAIT;
IO(15) <= MIPS_RESET or (not nRESET); -- OSC D15
IO(14) <= '0'; --SRAM_CE0; -- OSC D0
IO(12) <= '0'; --SRAM_CE1;
IO(10) <= '0'; --SRAM_OE;
IO(8) <= '0'; --SRAM_WE;
IO(6) <= '0'; --SRAM_LB;
IO(4) <= '0'; --SRAM_UB;
IO(2) <= '0';
IO(0) <= TST; -- OSC D7
--IO(14) <= MIPS_MEM_DO(0); -- OSC D0
--IO(12) <= MIPS_MEM_DO(1);
--IO(10) <= MIPS_MEM_DO(2);
--IO(8) <= MIPS_MEM_DO(3);
--IO(6) <= MIPS_MEM_DO(4);
--IO(4) <= MIPS_MEM_DO(5);
--IO(2) <= MIPS_MEM_DO(6);
--IO(0) <= MIPS_MEM_DO(7); -- OSC D7
-- System bus device multiplexor
-- Connecting appropriate memory or I/O to the system bus for reading and writing
-- ROM is in CPU address space 0xC000 - 0xFFFF
-- nLV_SRAM_CS <= '0' when nMEM_RQ = '0' and nRFSH = '1' and nHALT = '1' and nVRAM_CS = '1' and nROM_CS = '1' and TICK = "0100" else '1';
nLV_SRAM_CS <= '0' when nMEM_RQ = '0' and nRFSH = '1' and nHALT = '1' and nVRAM_CS = '1' and nROM_CS = '1' and (nCPU_WR = '0' or nCPU_RD = '0') else '1';
-- Read ROM, VRAM and RAM
CPU_DI <=
ROM_D when nROM_CS = '0' else
VRAM_DO when nVRAM_CS = '0' else
LV_SRAM_DO when nMEM_RQ = '0' and nRFSH = '1' else
-- Read ports
VG93_IRQ & VG93_DRQ & "111111" when nFDC_CS = '0' else
VG93_D_OUT when VG93_nCS = '0' else
VV55_SYS_DO when nVV55_SYS_CS = '0' else
VV55_KBD_DO when nVV55_KBD_CS = '0' else
AY_DO when nAY_CS = '0' else
(others => '1');
nROM_CS <= '0' when nMEM_RQ = '0' and nRFSH = '1' and nHALT = '1' and ( (CPU_A(15 downto 14) = "11" and nROM_EN = '0') or ROM_INIT = '1' ) else '1';
-- VRAM Control
-- VRAM is in CPU address space 0x4000 - 0x7FFF
nVRAM_CS <= '0' when nMEM_RQ = '0' and nRFSH = '1' and nHALT = '1' and CPU_A(15 downto 14) = "01" and nVRAM_EN = '0' else '1';
VRAM_WE <= "1" when nCPU_WR = '0' and nVRAM_CS = '0' else "0";
-- Ports 0xD0-0xDF - PK-02 bits 7-6 (15-14) are ignored
nVV55_KBD_CS <= '0' when nIO_RQ = '0' and CPU_A(5 downto 4) = "01" else '1';
nVV55_SYS_CS <= '0' when nIO_RQ = '0' and CPU_A(5 downto 4) = "00" else '1';
-- VG93 Ports 0xE0-0xE3
VG93_nCS <= '0' when nIO_RQ = '0' and CPU_A(7 downto 2) = "111000" else '1';
VG93_CLK <= '0' when TICK = "0011" else '1';
-- FDC Port 0xE4
nFDC_CS <= '0' when nIO_RQ = '0' and CPU_A(7 downto 0) = x"E4" else '1';
-- Write to ports
process(CLK)
begin
if rising_edge(CLK) then
if nRESET = '0' then
ROM_INIT <= '1';
-- Port #F0 PK-02 Reset
RAM_PAGE0 <= '0';
RAM_PAGE1 <= '0';
nROM_EN <= '0';
HI_RES <= '0';
BLANK_SCR <= '0';
INT_EN <= '0';
RAM_BANK0 <= '0';
RAM_BANK1 <= '0';
elsif TICK = "1011" then
if nIO_RQ = '0' and nCPU_WR = '0' then
ROM_INIT <= '0';
if CPU_A(5 downto 4) = "11" then -- Port #F0 PK-02
RAM_PAGE0 <= CPU_DO(0);
RAM_PAGE1 <= CPU_DO(1);
nROM_EN <= CPU_DO(2);
HI_RES <= CPU_DO(3);
BLANK_SCR <= CPU_DO(4);
INT_EN <= CPU_DO(5);
RAM_BANK0 <= CPU_DO(6);
RAM_BANK1 <= CPU_DO(7);
elsif nFDC_CS = '0' then -- Port #E4 FDC
VG93_nCLR <= CPU_DO(2);
VG93_nDDEN <= CPU_DO(6);
VG93_HRDY <= CPU_DO(3);
FDC_DRIVE <= CPU_DO(1 downto 0);
FDC_nSIDE <= CPU_DO(4);
end if;
end if;
end if;
end if;
end process;
-- PK-02 Interupts and AY CLC
-- Input 38.5 Mhz Output 49 Hz
-- 20 bit counter used, pulse width 10 us
process (CLK)
begin
if rising_edge(CLK) then
int_cnt <= int_cnt + 1;
clc_cnt <= clc_cnt + 1;
-- AY CLC 1.77 MHz (Actial 1.8MHz)
CLC <= '0';
if clc_cnt = 17 then
clc_cnt <= "00000";
CLC <= '1';
end if;
if int_cnt = 325 then
int_cnt <= int_cnt + 1;
nINT <= '1';
end if;
if int_cnt = 663260 then
int_cnt <= (others => '0');
if INT_EN = '1' then
nINT <= '0';
end if;
end if;
end if;
end process;
-- PK-02 RAM Page Switching
RAM_A <= RAM_BANK1 & RAM_BANK0 & RAM_PAGE1 & RAM_PAGE0 & CPU_A(13 downto 0) when CPU_A(15 downto 14) = "11" else
"11" & CPU_A(15 downto 0);
-- PK-02 AY8910 Port
nAY_CS <= '0' when nIO_RQ = '0' and nM1 = '1' and CPU_A(15) = '1' and CPU_A(1) = '0' else '1';
AUDIO_L <= std_logic_vector( unsigned('0' & AY_A & '0') + unsigned('0' & ( (BEEPER and BEEPER_EN) xor MIPS_BEEPER ) & AY_B) );
AUDIO_R <= std_logic_vector( unsigned('0' & AY_C & '0') + unsigned('0' & ( (BEEPER and BEEPER_EN) xor MIPS_BEEPER ) & AY_B) );
end Behavioral;
| gpl-3.0 | 06501a1fa5d762156b2b184a8a38e2b1 | 0.533569 | 2.561479 | false | false | false | false |
APastorG/APG | int_const_mult/int_const_mult_tb.vhd | 1 | 5,553 | /***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Xilinx's Vivado
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is a testbench generated for the int_const_multiplier module.
/
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.common_pkg.all;
use work.common_data_types_pkg.all;
use work.fixed_generic_pkg.all;
use work.tb_pkg.all;
use work.real_const_mult_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity int_const_mult_tb is
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture int_const_mult_tb1 of int_const_mult_tb is
/* constants 1 */
/**************************************************************************************************/
constant UNSIGNED_2COMP_opt : boolean_tb := (true, true); --default
constant SPEED_opt : T_speed_tb := (t_min, false); --exception: value not set
constant MULTIPLICANDS : integer_v := (2, 7); --compulsory
constant used_UNSIGNED_2COMP_opt : boolean := value_used(UNSIGNED_2COMP_opt, false);
constant used_SPEED_opt : T_speed := value_used(SPEED_opt);
constant used_MULTIPLICANDS : integer_v := MULTIPLICANDS;
/* signals 2 */
/**************************************************************************************************/
constant NORMALIZED_IN_HIGH : integer := 1;
constant NORMALIZED_IN_LOW : integer := -2;
function to_real(
vector : integer_v)
return real_v is
variable result : real_v(vector'range);
begin
for i in vector'range loop
result(i) := real(vector(i));
end loop;
return result;
end function;
constant used_MULTIPLICANDS_real : real_v(MULTIPLICANDS'range) := to_real(used_MULTIPLICANDS);
constant IN_HIGH : integer := NORMALIZED_IN_HIGH + SULV_NEW_ZERO;
constant IN_LOW : integer := NORMALIZED_IN_LOW + SULV_NEW_ZERO;
constant OUT_HIGH : integer := SULV_NEW_ZERO + real_const_mult_OH(fixed_truncate,--used_ROUND_STYLE_opt,
integer'low,--used_ROUND_TO_BIT_opt,
real'low,--used_MAX_ERROR_PCT_opt,
used_MULTIPLICANDS_real,
NORMALIZED_IN_HIGH,
NORMALIZED_IN_LOW,
not used_UNSIGNED_2COMP_opt);
constant OUT_LOW : integer := SULV_NEW_ZERO + real_const_mult_OL(fixed_truncate,--used_ROUND_STYLE_opt,
integer'low,--used_ROUND_TO_BIT_opt,
real'low,--used_MAX_ERROR_PCT_opt,
used_MULTIPLICANDS_real,
NORMALIZED_IN_LOW,
not used_UNSIGNED_2COMP_opt);
--IN
signal input : std_ulogic_vector(IN_HIGH DOWNTO IN_LOW);
signal clk : std_ulogic;
signal valid_input : std_ulogic;
--OUT
signal output : sulv_v(1 to MULTIPLICANDS'length)(OUT_HIGH downto OUT_LOW);
signal valid_output : std_ulogic;
/*================================================================================================*/
/*================================================================================================*/
begin
real_const_mult_2:
entity work.real_const_mult
generic map(
UNSIGNED_2COMP_opt => used_UNSIGNED_2COMP_opt,
SPEED_opt => used_SPEED_opt,
--ROUND_STYLE_opt => used_ROUND_STYLE_opt,
--ROUND_TO_BIT_opt => used_ROUND_TO_BIT_opt,
--MAX_ERROR_PCT_opt => used_MAX_ERROR_PCT_opt,
MULTIPLICANDS => used_MULTIPLICANDS_real)
port map(
input => input,
clk => clk,
valid_input => valid_input,
output => output,
valid_output => valid_output
);
end architecture; | mit | 81071a993ba0b83f12081db50de7dd8e | 0.378692 | 5.040183 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/components/generic_ram_infer.vhdl | 1 | 1,827 | ---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
ENTITY generic_ram_infer IS
generic
(
ADDRESS_WIDTH : natural := 9;
SPACE : natural := 512;
DATA_WIDTH : natural := 8
);
PORT
(
clock: IN std_logic;
data: IN std_logic_vector (data_width-1 DOWNTO 0);
address: IN std_logic_vector(address_width-1 downto 0);
we: IN std_logic;
q: OUT std_logic_vector (data_width-1 DOWNTO 0)
);
END generic_ram_infer;
ARCHITECTURE rtl OF generic_ram_infer IS
TYPE mem IS ARRAY(0 TO space-1) OF std_logic_vector(data_width-1 DOWNTO 0);
SIGNAL ram_block : mem;
SIGNAL q_ram : std_logic_vector(data_width-1 downto 0);
SIGNAL we_ram : std_logic;
signal address2 : std_logic_vector(address_width-1 downto 0);
BEGIN
PROCESS (clock)
BEGIN
IF (clock'event AND clock = '1') THEN
IF (we_ram = '1') THEN
ram_block(to_integer(to_01(unsigned(address2), '0'))) <= data;
q_ram <= data;
ELSE
q_ram <= ram_block(to_integer(to_01(unsigned(address2), '0')));
END IF;
END IF;
END PROCESS;
PROCESS(address, we, q_ram)
begin
q <= (others=>'1');
we_ram <= '0';
address2 <= (others=>'0');
IF (to_integer(to_01(unsigned(address))) < space) THEN
q <= q_ram;
we_ram <= we;
address2 <= address;
end if;
end process;
END rtl;
| gpl-3.0 | bf45537a2942ad80e5b117d42658e7b0 | 0.56705 | 3.346154 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/host/plasma v3.0/ram.vhd | 1 | 6,176 | ---------------------------------------------------------------------
-- TITLE: Random Access Memory
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 4/21/01
-- FILENAME: ram.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the RAM, reads the executable from either "code.txt",
-- or for Altera "code[0-3].hex".
-- Modified from "The Designer's Guide to VHDL" by Peter J. Ashenden
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.mlite_pack.all;
--Uncomment following two lines for Xilinx RAM16X1D
library UNISIM; --Xilinx
use UNISIM.vcomponents.all; --Xilinx
entity ram is
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
constant ADDRESS_WIDTH : natural := 13;
begin
generic_ram:
if memory_type /= "ALTERA_LPM" generate
--Simulate a synchronous RAM
ram_proc: process(clk, enable, write_byte_enable,
address, data_write) --mem_write, mem_sel
variable mem_size : natural := 2 ** ADDRESS_WIDTH;
variable data : std_logic_vector(31 downto 0);
subtype word is std_logic_vector(data_write'length-1 downto 0);
type storage_array is
array(natural range 0 to mem_size/4 - 1) of word;
variable storage : storage_array;
variable index : natural := 0;
file load_file : text open read_mode is "code.txt";
variable hex_file_line : line;
begin
--Load in the ram executable image
if index = 0 then
while not endfile(load_file) loop
--The following two lines had to be commented out for synthesis
readline(load_file, hex_file_line);
hread(hex_file_line, data);
storage(index) := data;
index := index + 1;
end loop;
end if;
if rising_edge(clk) then
index := conv_integer(address(ADDRESS_WIDTH-1 downto 2));
data := storage(index);
if enable = '1' then
if write_byte_enable(0) = '1' then
data(7 downto 0) := data_write(7 downto 0);
end if;
if write_byte_enable(1) = '1' then
data(15 downto 8) := data_write(15 downto 8);
end if;
if write_byte_enable(2) = '1' then
data(23 downto 16) := data_write(23 downto 16);
end if;
if write_byte_enable(3) = '1' then
data(31 downto 24) := data_write(31 downto 24);
end if;
end if;
if write_byte_enable /= "0000" then
storage(index) := data;
end if;
end if;
data_read <= data;
end process;
end generate; --generic_ram
altera_ram:
if memory_type = "ALTERA_LPM" generate
lpm_ram_io_component0 : lpm_ram_dq
GENERIC MAP (
intended_device_family => "UNUSED",
lpm_width => 8,
lpm_widthad => ADDRESS_WIDTH-2,
lpm_indata => "REGISTERED",
lpm_address_control => "REGISTERED",
lpm_outdata => "UNREGISTERED",
lpm_file => "code0.hex",
use_eab => "ON",
lpm_type => "LPM_RAM_DQ")
PORT MAP (
data => data_write(31 downto 24),
address => address(ADDRESS_WIDTH-1 downto 2),
inclock => clk,
we => write_byte_enable(3),
q => data_read(31 downto 24));
lpm_ram_io_component1 : lpm_ram_dq
GENERIC MAP (
intended_device_family => "UNUSED",
lpm_width => 8,
lpm_widthad => ADDRESS_WIDTH-2,
lpm_indata => "REGISTERED",
lpm_address_control => "REGISTERED",
lpm_outdata => "UNREGISTERED",
lpm_file => "code1.hex",
use_eab => "ON",
lpm_type => "LPM_RAM_DQ")
PORT MAP (
data => data_write(23 downto 16),
address => address(ADDRESS_WIDTH-1 downto 2),
inclock => clk,
we => write_byte_enable(2),
q => data_read(23 downto 16));
lpm_ram_io_component2 : lpm_ram_dq
GENERIC MAP (
intended_device_family => "UNUSED",
lpm_width => 8,
lpm_widthad => ADDRESS_WIDTH-2,
lpm_indata => "REGISTERED",
lpm_address_control => "REGISTERED",
lpm_outdata => "UNREGISTERED",
lpm_file => "code2.hex",
use_eab => "ON",
lpm_type => "LPM_RAM_DQ")
PORT MAP (
data => data_write(15 downto 8),
address => address(ADDRESS_WIDTH-1 downto 2),
inclock => clk,
we => write_byte_enable(1),
q => data_read(15 downto 8));
lpm_ram_io_component3 : lpm_ram_dq
GENERIC MAP (
intended_device_family => "UNUSED",
lpm_width => 8,
lpm_widthad => ADDRESS_WIDTH-2,
lpm_indata => "REGISTERED",
lpm_address_control => "REGISTERED",
lpm_outdata => "UNREGISTERED",
lpm_file => "code3.hex",
use_eab => "ON",
lpm_type => "LPM_RAM_DQ")
PORT MAP (
data => data_write(7 downto 0),
address => address(ADDRESS_WIDTH-1 downto 2),
inclock => clk,
we => write_byte_enable(0),
q => data_read(7 downto 0));
end generate; --altera_ram
--For XILINX see ram_xilinx.vhd
end; --architecture logic
| gpl-3.0 | 3d3e49491a3493b5f57c8653b3297998 | 0.528335 | 3.97426 | false | false | false | false |
VHDLTool/VHDL_Handbook_STD | Extras/VHDL/STD_06600_good.vhd | 1 | 3,445 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-10 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_06600_good.vhd
-- File Creation date : 2015-04-10
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Dimension of comparison elements: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_06600_good is
port (
i_Clock : in std_logic; -- Main clock signal
i_Reset_n : in std_logic; -- Main reset signal
i_Enable : in std_logic; -- Enables the counter
i_Length : in std_logic_vector(3 downto 0); -- Unsigned Value for Counter Period
o_Count : out std_logic_vector(3 downto 0) -- Counter (unsigned value)
);
end STD_06600_good;
--CODE
architecture Behavioral of STD_06600_good is
signal Count : unsigned(3 downto 0); -- Counter output signal (unsigned converted)
signal Count_Length : unsigned(3 downto 0); -- Length input signal (unsigned converted)
begin
Count_Length <= unsigned(i_Length);
-- Will count undefinitely from 0 to i_Length while i_Enable is asserted
P_Count : process(i_Reset_n, i_Clock)
begin
if (i_Reset_n = '0') then
Count <= (others => '0');
elsif (rising_edge(i_Clock)) then
if (Count >= Count_Length) then -- Counter restarts from 0
Count <= (others => '0');
elsif (i_Enable = '1') then -- Increment counter value
Count <= Count + 1;
end if;
end if;
end process;
o_Count <= std_logic_vector(Count);
end Behavioral;
--CODE
| gpl-3.0 | 010560d7a5e3a29e6b6a7b4356017159 | 0.510305 | 4.532895 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/lvov-pk02-mips/src/xsd/xsd_ram.vhd | 1 | 5,590 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file xsd_ram.vhd when simulating
-- the core, xsd_ram. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY xsd_ram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END xsd_ram;
ARCHITECTURE xsd_ram_a OF xsd_ram IS
-- synthesis translate_off
COMPONENT wrapped_xsd_ram
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_xsd_ram USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 11,
c_addrb_width => 11,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 2048,
c_read_depth_b => 2048,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 2048,
c_write_depth_b => 2048,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_xsd_ram
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END xsd_ram_a;
| gpl-3.0 | 73ea4f1a4ac60a6d3dc9028394153e35 | 0.530233 | 3.911826 | false | false | false | false |
ILoveSpeccy/Aeon-Lite | cores/service/src/fontrom/fontrom.vhd | 1 | 5,445 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file fontrom.vhd when simulating
-- the core, fontrom. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY fontrom IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END fontrom;
ARCHITECTURE fontrom_a OF fontrom IS
-- synthesis translate_off
COMPONENT wrapped_fontrom
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_fontrom USE ENTITY XilinxCoreLib.blk_mem_gen_v6_3(behavioral)
GENERIC MAP (
c_addra_width => 12,
c_addrb_width => 12,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "fontrom.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 4096,
c_read_depth_b => 4096,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 4096,
c_write_depth_b => 4096,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fontrom
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END fontrom_a;
| gpl-3.0 | 04bf759b8b49a60e288fd8c8c23c200f | 0.516253 | 3.977356 | false | false | false | false |
Subsets and Splits